<s> void Mips16FrameLowering :: emitPrologue ( MachineFunction & MF , MachineBasicBlock & MBB ) const { MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const Mips16InstrInfo & TII = * static_cast < const Mips16InstrInfo * > ( STI . getInstrInfo ( ) ) ; MachineBasicBlock :: iterator MBBI = MBB . begin ( ) ; DebugLoc dl ; uint64_t StackSize = MFI . getStackSize ( ) ; if ( StackSize == 0 && ! MFI . adjustsStack ( ) ) return ; MachineModuleInfo & MMI = MF . getMMI ( ) ; const MCRegisterInfo * MRI = MMI . getContext ( ) . getRegisterInfo ( ) ; TII . makeFrame ( Mips :: SP , StackSize , MBB , MBBI ) ; unsigned CFIIndex = MF . addFrameInst ( MCCFIInstruction :: createDefCfaOffset ( nullptr , - StackSize ) ) ; BuildMI ( MBB , MBBI , dl , TII . get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; const std :: vector < CalleeSavedInfo > & CSI = MFI . getCalleeSavedInfo ( ) ; if ( ! CSI . empty ( ) ) { const std :: vector < CalleeSavedInfo > & CSI = MFI . getCalleeSavedInfo ( ) ; for ( std :: vector < CalleeSavedInfo > :: const_iterator I = CSI . begin ( ) , E = CSI . end ( ) ; I != E ; ++ I ) { int64_t Offset = MFI . getObjectOffset ( I -> getFrameIdx ( ) ) ; unsigned Reg = I -> getReg ( ) ; unsigned DReg = MRI -> getDwarfRegNum ( Reg , true ) ; unsigned CFIIndex = MF . addFrameInst ( MCCFIInstruction :: createOffset ( nullptr , DReg , Offset ) ) ; BuildMI ( MBB , MBBI , dl , TII . get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; } } if ( hasFP ( MF ) ) BuildMI ( MBB , MBBI , dl , TII . get ( Mips :: MoveR3216 ) , Mips :: S0 ) . addReg ( Mips :: SP ) . setMIFlag ( MachineInstr :: FrameSetup ) ; } </s>

emitProlog/emitEpilog - These methods insert prolog and epilog code into the function .

Mips Mips Mips Mips 0 Mips::SP Mips::MoveR3216 Mips::S0 Mips::SP


<s> static unsigned long thumb1_compute_save_core_reg_mask ( void ) { unsigned long mask ; unsigned reg ; mask = 0 ; for ( reg = 0 ; reg < 12 ; reg ++ ) if ( df_regs_ever_live_p ( reg ) && callee_saved_reg_p ( reg ) ) mask |= 1 << reg ; if ( frame_pointer_needed ) mask |= 1 << HARD_FRAME_POINTER_REGNUM ; if ( flag_pic && ! TARGET_SINGLE_PIC_BASE && arm_pic_register != INVALID_REGNUM && crtl -> uses_pic_offset_table ) mask |= 1 << PIC_OFFSET_TABLE_REGNUM ; if ( ! frame_pointer_needed && CALLER_INTERWORKING_SLOT_SIZE > 0 ) mask |= 1 << ARM_HARD_FRAME_POINTER_REGNUM ; if ( mask & 0xff || thumb_force_lr_save ( ) ) mask |= ( 1 << LR_REGNUM ) ; if ( ( mask & 0xff ) == 0 && ( ( mask & 0x0f00 ) || TARGET_BACKTRACE ) ) { reg = thumb_find_work_register ( 1 << LAST_LO_REGNUM ) ; if ( reg * UNITS_PER_WORD <= ( unsigned ) arm_size_return_regs ( ) ) reg = LAST_LO_REGNUM ; if ( callee_saved_reg_p ( reg ) ) mask |= 1 << reg ; } if ( ( CALLER_INTERWORKING_SLOT_SIZE + ROUND_UP_WORD ( get_frame_size ( ) ) + crtl -> outgoing_args_size ) >= 504 ) { for ( reg = LAST_ARG_REGNUM + 1 ; reg <= LAST_LO_REGNUM ; reg ++ ) if ( mask & ( 1 << reg ) ) break ; if ( reg > LAST_LO_REGNUM ) { mask |= 1 << LAST_LO_REGNUM ; } } return mask ; } </s>

Compute a bit mask of which core registers need to be saved on the stack for the current function .


<s> const X86RegisterInfo * getRegisterInfo ( ) const override { return & getInstrInfo ( ) -> getRegisterInfo ( ) ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s>
static
tree
rs6000_mangle_decl_assembler_name
(
tree
decl
,
tree
id
)
{
if
(
TARGET_FLOAT128_TYPE
&&
TARGET_IEEEQUAD
&&
TARGET_LONG_DOUBLE_128
&&
TREE_CODE
(
decl
)
==
FUNCTION_DECL
&&
DECL_IS_UNDECLARED_BUILTIN
(
decl
)
&&
DECL_BUILT_IN_CLASS
(
decl
)
==
BUILT_IN_NORMAL
)
{
size_t
len
=
IDENTIFIER_LENGTH
(
id
)
;
const
char
*
name
=
IDENTIFIER_POINTER
(
id
)
;
char
*
newname
=
;
switch
(
DECL_FUNCTION_CODE
(
decl
)
)
{
case
BUILT_IN_DREML
:
newname
=
xstrdup
(
"__remainderieee128"
)
;
break
;
case
BUILT_IN_GAMMAL
:
newname
=
xstrdup
(
"__lgammaieee128"
)
;
break
;
case
BUILT_IN_GAMMAL_R
:
case
BUILT_IN_LGAMMAL_R
:
newname
=
xstrdup
(
"__lgammaieee128_r"
)
;
break
;
case
BUILT_IN_NEXTTOWARD
:
newname
=
xstrdup
(
"__nexttoward_to_ieee128"
)
;
break
;
case
BUILT_IN_NEXTTOWARDF
:
newname
=
xstrdup
(
"__nexttowardf_to_ieee128"
)
;
break
;
case
BUILT_IN_NEXTTOWARDL
:
newname
=
xstrdup
(
"__nexttowardieee128"
)
;
break
;
case
BUILT_IN_POW10L
:
newname
=
xstrdup
(
"__exp10ieee128"
)
;
break
;
case
BUILT_IN_SCALBL
:
newname
=
xstrdup
(
"__scalbieee128"
)
;
break
;
case
BUILT_IN_SIGNIFICANDL
:
newname
=
xstrdup
(
"__significandieee128"
)
;
break
;
case
BUILT_IN_SINCOSL
:
newname
=
xstrdup
(
"__sincosieee128"
)
;
break
;
default
:
break
;
}
if
(
!
newname
)
{
size_t
printf_len
=
strlen
(
"printf"
)
;
size_t
scanf_len
=
strlen
(
"scanf"
)
;
size_t
printf_chk_len
=
strlen
(
"printf_chk"
)
;
if
(
len
>=
printf_len
&&
strcmp
(
name
+
len
printf_len
,
"printf"
)
==
0
)
newname
=
xasprintf
(
"__%sieee128"
,
name
)
;
else
if
(
len
>=
scanf_len
&&
strcmp
(
name
+
len
scanf_len
,
"scanf"
)
==
0
)
newname
=
xasprintf
(
"__isoc99_%sieee128"
,
name
)
;
else
if
(
len
>=
printf_chk_len
&&
strcmp
(
name
+
len
printf_chk_len
,
"printf_chk"
)
==
0
)
newname
=
xasprintf
(
"%sieee128"
,
name
)
;
else
if
(
name
[
len
1
]
==
'l'
)
{
bool
uses_ieee128_p
=
false
;
tree
type
=
TREE_TYPE
(
decl
)
;
machine_mode
ret_mode
=
TYPE_MODE
(
type
)
;
if
(
ret_mode
==
TFmode
||
ret_mode
==
TCmode
)
uses_ieee128_p
=
true
;
else
{
function_args_iterator
args_iter
;
tree
arg
;
FOREACH_FUNCTION_ARGS
(
type
,
arg
,
args_iter
)
{
machine_mode
arg_mode
=
TYPE_MODE
(
arg
)
;
if
(
arg_mode
==
TFmode
||
arg_mode
==
TCmode
)
{
uses_ieee128_p
=
true
;
break
;
}
}
}
if
(
uses_ieee128_p
)
newname
=
xasprintf
(
"__%.*sieee128"
,
(
int
)
(
len
1
)
,
name
)
;
}
}
if
(
newname
)
{
if
(
TARGET_DEBUG_BUILTIN
)
fprintf
(
stderr
,
"Map %s => %s\n"
,
name
,
newname
)
;
id
=
get_identifier
(
newname
)
;
free
(
newname
)
;
}
}
return
id
;
}
</s>

On 64-bit Linux and Freebsd systems , possibly switch the long double library function names from < foo > l to < foo > f128 if the default long double type is IEEE 128-bit . Typically , with the C and C++ languages , the standard math.h include file switches the names on systems that support long double as IEEE 128-bit , but that does n't work if the user uses __builtin_ < foo > l directly . In the future , glibc will export names like __ieee128_sinf128 and we can switch to using those instead of using sinf128 , which pollutes the user 's namespace . This will switch the names for Fortran math functions as well ( which does n't use math.h ) . However , Fortran needs other changes to the compiler and library before you can switch the real * 16 type at compile time . We use the TARGET_MANGLE_DECL_ASSEMBLER_NAME hook to change this name . We only do this transformation if the __float128 type is enabled . This prevents us from doing the transformation on older 32-bit ports that might have enabled using IEEE 128-bit floating point as the default long double type . We also use the TARGET_MANGLE_DECL_ASSEMBLER_NAME hook to change the function names used for complex multiply and divide to the appropriate names .


<s> bool useAA ( ) const override { return true ; } </s>

Enable use of alias analysis during code generation ( during MI scheduling , DAGCombine , etc . ) .


<s> std :: unique_ptr < MCObjectWriter > createObjectWriter ( raw_pwrite_stream & OS ) const override { bool is64 = getPointerSize ( ) == 8 ; return createPPCELFObjectWriter ( OS , is64 , isLittleEndian ( ) , OSABI ) ; } </s>

Create a new MCObjectWriter instance for use by the assembler backend to emit the final object file .


<s> SDValue TVMTargetLowering :: PerformDAGCombine ( SDNode * N , DAGCombinerInfo & DCI ) const { SelectionDAG & DAG = DCI . DAG ; SDLoc DL ( N ) ; switch ( N -> getOpcode ( ) ) { case ISD :: ANY_EXTEND : if ( N -> getOperand ( 0 ) -> getValueType ( 0 ) == N -> getValueType ( 0 ) ) return N -> getOperand ( 0 ) ; break ; case TVMISD :: IFELSE : return performIFELSECombine ( N , DCI , DAG ) ; case TVMISD :: IFJMP : return performIFJMPCombine ( N , DCI , DAG ) ; case ISD :: TRUNCATE : { if ( ! UseTruncMasks ) break ; if ( ! DCI . isBeforeLegalizeOps ( ) ) break ; MVT ResultType = N -> getSimpleValueType ( 0 ) ; MVT OperandType = N -> getOperand ( 0 ) . getSimpleValueType ( ) ; if ( ! ResultType . isInteger ( ) || ! OperandType . isInteger ( ) ) break ; if ( OperandType . getSizeInBits ( ) == ResultType . getSizeInBits ( ) ) break ; APInt TruncateMask ( OperandType . getSizeInBits ( ) , 0 ) ; TruncateMask . setLowBits ( ResultType . getSizeInBits ( ) ) ; SDValue AndNode = DAG . getNode ( TVMISD :: AND , DL , OperandType , N -> getOperand ( 0 ) , DAG . getConstant ( TruncateMask , DL , OperandType ) ) ; SDValue Replacement = DAG . getNode ( ISD :: TRUNCATE , DL , ResultType , AndNode ) ; DCI . CombineTo ( N , Replacement , false ) ; break ; } } return SDValue ( ) ; } </s>

This method will be invoked for all target nodes and for any target-independent nodes that the target has registered with invoke it for .


"unexpected base-type in cris_print_base"

Print a base rtx of an address to file .


<s> static rtx duplicate_cond ( rtx pat , rtx cond_insn ) { rtx cond_pat = PATTERN ( cond_insn ) ; if ( GET_CODE ( cond_pat ) == COND_EXEC ) pat = gen_rtx_COND_EXEC ( VOIDmode , copy_rtx ( COND_EXEC_TEST ( cond_pat ) ) , pat ) ; return pat ; } </s>

If COND_INSN has a COND_EXEC condition , wrap the same condition around PAT . Return PAT either unchanged or modified in this way .


<s> unsigned FISCInstrInfo :: isLoadFromStackSlot ( const MachineInstr * MI , int & FrameIndex ) const { return 0 ; } </s>

isLoadFromStackSlot - If the specified machine instruction is a direct load from a stack slot , return the virtual or physical register number of the destination along with the FrameIndex of the loaded stack slot .


"      Hazard - LOOKUP in prev packet\n"

"      NoHazard - can add to current packet\n"

"      Hazard - can not add to current packet\n"

getHazardType - Return the hazard type of emitting this node .

"      Hazard - LOOKUP in prev packet\n"


<s> Register NVPTXRegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { const NVPTXTargetMachine & TM = static_cast < const NVPTXTargetMachine & > ( MF . getTarget ( ) ) ; return TM . is64Bit ( ) ? NVPTX :: VRFrame64 : NVPTX :: VRFrame32 ; } </s>

NVPTX NVPTX NVPTX NVPTX NVPTX::VRFrame64 NVPTX::VRFrame32


<s> SystemZSubtarget & SystemZSubtarget :: initializeSubtargetDependencies ( StringRef CPU , StringRef FS ) { StringRef CPUName = CPU ; if ( CPUName . empty ( ) ) CPUName = "generic" ; ParseSubtargetFeatures ( CPUName , CPUName , FS ) ; if ( HasSoftFloat ) HasVector = false ; if ( ! HasVector ) { HasVectorEnhancements1 = false ; HasVectorEnhancements2 = false ; HasVectorPackedDecimal = false ; HasVectorPackedDecimalEnhancement = false ; HasVectorPackedDecimalEnhancement2 = false ; } return * this ; } </s>

initializeSubtargetDependencies - Initializes using a CPU , a TuneCPU , and feature string so that we can use initializer lists for subtarget initialization .


<s> bool runOnMachineFunction ( MachineFunction & MF ) override { AArch64FI = MF . getInfo < AArch64FunctionInfo > ( ) ; STI = static_cast < const AArch64Subtarget * > ( & MF . getSubtarget ( ) ) ; SetupMachineFunction ( MF ) ; if ( STI -> isTargetCOFF ( ) ) { bool Internal = MF . getFunction ( ) . hasInternalLinkage ( ) ; COFF :: SymbolStorageClass Scl = Internal ? COFF :: IMAGE_SYM_CLASS_STATIC : COFF :: IMAGE_SYM_CLASS_EXTERNAL ; int Type = COFF :: IMAGE_SYM_DTYPE_FUNCTION << COFF :: SCT_COMPLEX_TYPE_SHIFT ; OutStreamer -> BeginCOFFSymbolDef ( CurrentFnSym ) ; OutStreamer -> EmitCOFFSymbolStorageClass ( Scl ) ; OutStreamer -> EmitCOFFSymbolType ( Type ) ; OutStreamer -> EndCOFFSymbolDef ( ) ; } emitFunctionBody ( ) ; emitXRayTable ( ) ; return false ; } </s>

runOnMachineFunction - Emit the function body .


<s> static void mips_multi_write ( void ) { struct mips_multi_member * member ; unsigned int i ; FOR_EACH_VEC_ELT ( mips_multi_members , i , member ) if ( member -> is_label_p ) fprintf ( asm_out_file , "%s\n" , member -> format ) ; else output_asm_insn ( member -> format , member -> operands ) ; } </s>

Write out the asm code for the current multi-insn sequence .


<s> SDValue ARMTargetLowering :: PerformDAGCombine ( SDNode * N , DAGCombinerInfo & DCI ) const { switch ( N -> getOpcode ( ) ) { default : break ; case ISD :: ADD : return PerformADDCombine ( N , DCI ) ; case ISD :: SUB : return PerformSUBCombine ( N , DCI ) ; case ARMISD :: FMRRD : return PerformFMRRDCombine ( N , DCI ) ; case ISD :: INTRINSIC_WO_CHAIN : return PerformIntrinsicCombine ( N , DCI . DAG ) ; case ISD :: SHL : case ISD :: SRA : case ISD :: SRL : return PerformShiftCombine ( N , DCI . DAG , Subtarget ) ; case ISD :: SIGN_EXTEND : case ISD :: ZERO_EXTEND : case ISD :: ANY_EXTEND : return PerformExtendCombine ( N , DCI . DAG , Subtarget ) ; } return SDValue ( ) ; } </s>

ARM ARM ISD::ADD ISD::SUB ARMISD::FMRRD ISD::INTRINSIC_WO_CHAIN ISD::SHL ISD::SRA ISD::SRL ISD::SIGN_EXTEND ISD::ZERO_EXTEND ISD::ANY_EXTEND


<s> VETargetLowering :: ConstraintType VETargetLowering :: getConstraintType ( StringRef Constraint ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { default : break ; case 'v' : return C_RegisterClass ; } } return TargetLowering :: getConstraintType ( Constraint ) ; } </s>

Given a constraint letter , return the type of constraint for this target .


<s>
bool
HexagonExpandCondsets
::
split
(
MachineInstr
&
MI
,
std
::
set
<
unsigned
>
&
UpdRegs
)
{
if
(
TfrLimitActive
)
{
if
(
TfrCounter
>=
TfrLimit
)
return
false
;
TfrCounter
++
;
}
DEBUG
(
dbgs
(
)
<<
"\nsplitting BB#"
<<
MI
.
getParent
(
)
->
getNumber
(
)
<<
": "
<<
MI
)
;
MachineOperand
&
MD
=
MI
.
getOperand
(
0
)
;
MachineOperand
&
MP
=
MI
.
getOperand
(
1
)
;
assert
(
MD
.
isDef
(
)
)
;
unsigned
DR
=
MD
.
getReg
(
)
,
DSR
=
MD
.
getSubReg
(
)
;
bool
ReadUndef
=
MD
.
isUndef
(
)
;
MachineBasicBlock
::
iterator
At
=
MI
;
MachineOperand
&
ST
=
MI
.
getOperand
(
2
)
;
MachineOperand
&
SF
=
MI
.
getOperand
(
3
)
;
if
(
ST
.
isReg
(
)
&&
SF
.
isReg
(
)
)
{
RegisterRef
RT
(
ST
)
;
if
(
RT
==
RegisterRef
(
SF
)
)
{
MI
.
setDesc
(
HII
->
get
(
TargetOpcode
::
COPY
)
)
;
unsigned
S
=
getRegState
(
ST
)
;
while
(
MI
.
getNumOperands
(
)
>
1
)
MI
.
RemoveOperand
(
MI
.
getNumOperands
(
)
1
)
;
MachineFunction
&
MF
=
*
MI
.
getParent
(
)
->
getParent
(
)
;
MachineInstrBuilder
(
MF
,
MI
)
.
addReg
(
RT
.
Reg
,
S
,
RT
.
Sub
)
;
return
true
;
}
}
MachineInstr
*
TfrT
=
genCondTfrFor
(
ST
,
At
,
DR
,
DSR
,
MP
,
true
,
ReadUndef
,
false
)
;
MachineInstr
*
TfrF
=
genCondTfrFor
(
SF
,
At
,
DR
,
DSR
,
MP
,
false
,
ReadUndef
,
true
)
;
LIS
->
InsertMachineInstrInMaps
(
*
TfrT
)
;
LIS
->
InsertMachineInstrInMaps
(
*
TfrF
)
;
for
(
auto
&
Op
:
MI
.
operands
(
)
)
if
(
Op
.
isReg
(
)
)
UpdRegs
.
insert
(
Op
.
getReg
(
)
)
;
removeInstr
(
MI
)
;
return
true
;
}
</s>

Split into substrings around the occurrences of a separator character .


<s> ARMBaseTargetMachine :: ARMBaseTargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL , bool isLittle ) : LLVMTargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL ) , TargetABI ( computeTargetABI ( Triple ( TT ) , CPU , Options ) ) , DL ( computeDataLayout ( Triple ( TT ) , TargetABI , isLittle ) ) , TLOF ( createTLOF ( Triple ( getTargetTriple ( ) ) ) ) , Subtarget ( TT , CPU , FS , * this , isLittle ) , isLittle ( isLittle ) { if ( Options . FloatABIType == FloatABI :: Default ) this -> Options . FloatABIType = Subtarget . isTargetHardFloat ( ) ? FloatABI :: Hard : FloatABI :: Soft ; } </s>


<s>
void
Z80TargetLowering
::
AdjustInstrPostInstrSelection
(
MachineInstr
&
MI
,
SDNode
*
Node
)
const
{
switch
(
MI
.
getOpcode
(
)
)
{
default
:
llvm_unreachable
(
"Unexpected instr type to insert"
)
;
case
Z80
::
ADJCALLSTACKUP16
:
case
Z80
::
ADJCALLSTACKUP24
:
case
Z80
::
ADJCALLSTACKDOWN16
:
case
Z80
::
ADJCALLSTACKDOWN24
:
return
AdjustAdjCallStack
(
MI
)
;
}
}
</s>

This method should be implemented by targets that mark instructions with the 'hasPostISelHook ' flag .


<s> ArrayRef < MCPhysReg > SIRegisterInfo :: getAllSGPR64 ( const MachineFunction & MF ) const { return makeArrayRef ( AMDGPU :: SGPR_64RegClass . begin ( ) , ST . getMaxNumSGPRs ( MF ) / 2 ) ; } </s>

Return all SGPR64 which satisfy the waves per execution unit requirement of the subtarget .


<s> static struct machine_function * m32c_init_machine_status ( void ) { struct machine_function * machine ; machine = ( machine_function * ) ggc_alloc_cleared ( sizeof ( machine_function ) ) ; return machine ; } </s>

The usual ; we set up our machine_function data .


<s> const uint32_t * ARMBaseRegisterInfo :: getThisReturnPreservedMask ( CallingConv :: ID ) const { return ( STI . isTargetIOS ( ) && ! STI . isAAPCS_ABI ( ) ) ? CSR_iOS_ThisReturn_RegMask : CSR_AAPCS_ThisReturn_RegMask ; } </s>

getThisReturnPreservedMask - Returns a call preserved mask specific to the case that 'returned ' is on an i32 first argument if the calling convention is one that can ( partially ) model this attribute with a preserved mask ( i.e .


<s> bool SIRegisterInfo :: requiresFrameIndexScavenging ( const MachineFunction & MF ) const { return MF . getFrameInfo ( ) . hasStackObjects ( ) ; } </s>

Returns true if the target requires post PEI scavenging of registers for materializing frame index constants .


<s> void bpf_core_reloc_add ( const tree type , const char * section_name , vec < unsigned int > * accessors , rtx_code_label * label , enum btf_core_reloc_kind kind ) { char buf [ 40 ] ; unsigned int i , n = 0 ; if ( accessors -> length ( ) < 1 ) return ; for ( i = 0 ; i < accessors -> length ( ) - 1 ; i ++ ) n += snprintf ( buf + n , sizeof ( buf ) - n , "%u:" , ( * accessors ) [ i ] ) ; snprintf ( buf + n , sizeof ( buf ) - n , "%u" , ( * accessors ) [ i ] ) ; bpf_core_reloc_ref bpfcr = ggc_cleared_alloc < bpf_core_reloc_t > ( ) ; ctf_container_ref ctfc = ctf_get_tu_ctfc ( ) ; ctf_add_string ( ctfc , buf , & ( bpfcr -> bpfcr_astr_off ) , CTF_AUX_STRTAB ) ; bpfcr -> bpfcr_type = get_btf_id ( ctf_lookup_tree_type ( ctfc , type ) ) ; bpfcr -> bpfcr_insn_label = label ; bpfcr -> bpfcr_kind = kind ; bpf_core_section_ref sec ; FOR_EACH_VEC_ELT ( * bpf_core_sections , i , sec ) if ( strcmp ( sec -> name , section_name ) == 0 ) { vec_safe_push ( sec -> relocs , bpfcr ) ; return ; } sec = ggc_cleared_alloc < bpf_core_section_t > ( ) ; ctf_add_string ( ctfc , section_name , & sec -> name_offset , CTF_AUX_STRTAB ) ; if ( strcmp ( section_name , "" ) ) ctfc -> ctfc_aux_strlen += strlen ( section_name ) + 1 ; sec -> name = section_name ; vec_alloc ( sec -> relocs , 1 ) ; vec_safe_push ( sec -> relocs , bpfcr ) ; vec_safe_push ( bpf_core_sections , sec ) ; } </s>

Create a new BPF CO-RE relocation record , and add it to the appropriate CO-RE section .


<s> unsigned find_first ( ) const { int First = BitVector :: find_first ( ) ; if ( First < 0 ) return 0 ; return x2v ( First ) ; } </s>

find_first - Returns the index of the first set bit .


<s> static unsigned getBasePointerSaveOffset ( bool isPPC64 , bool isDarwinABI , bool isPIC ) { if ( isDarwinABI ) return isPPC64 ? - 16U : - 8U ; return isPPC64 ? - 16U : isPIC ? - 12U : - 8U ; } </s>

getBasePointerSaveOffset - Return the previous frame offset to save the base pointer .


<s> FunctionCallee AMDGPULibFunc :: getOrInsertFunction ( Module * M , const AMDGPULibFunc & fInfo ) { std :: string const FuncName = fInfo . mangle ( ) ; Function * F = dyn_cast_or_null < Function > ( M -> getValueSymbolTable ( ) . lookup ( FuncName ) ) ; if ( F && ! F -> isDeclaration ( ) && ! F -> isVarArg ( ) && F -> arg_size ( ) == fInfo . getNumArgs ( ) ) { return F ; } FunctionType * FuncTy = fInfo . getFunctionType ( * M ) ; bool hasPtr = false ; for ( FunctionType :: param_iterator PI = FuncTy -> param_begin ( ) , PE = FuncTy -> param_end ( ) ; PI != PE ; ++ PI ) { const Type * argTy = static_cast < const Type * > ( * PI ) ; if ( argTy -> isPointerTy ( ) ) { hasPtr = true ; break ; } } FunctionCallee C ; if ( hasPtr ) { C = M -> getOrInsertFunction ( FuncName , FuncTy ) ; } else { AttributeList Attr ; LLVMContext & Ctx = M -> getContext ( ) ; Attr = Attr . addAttribute ( Ctx , AttributeList :: FunctionIndex , Attribute :: ReadOnly ) ; Attr = Attr . addAttribute ( Ctx , AttributeList :: FunctionIndex , Attribute :: NoUnwind ) ; C = M -> getOrInsertFunction ( FuncName , FuncTy , Attr ) ; } return C ; } </s>

Look up the specified function in the module symbol table .


<s> rtx m32c_incoming_return_addr_rtx ( void ) { return gen_rtx_MEM ( PSImode , gen_rtx_REG ( PSImode , SP_REGNO ) ) ; } </s>

Implements INCOMING_RETURN_ADDR_RTX . See comment above .


<s> bool X86InstrInfo :: isTailCall ( const MachineInstr & Inst ) const { switch ( Inst . getOpcode ( ) ) { case X86 :: TCRETURNdi : case X86 :: TCRETURNmi : case X86 :: TCRETURNri : case X86 :: TCRETURNdi64 : case X86 :: TCRETURNmi64 : case X86 :: TCRETURNri64 : case X86 :: TAILJMPd : case X86 :: TAILJMPm : case X86 :: TAILJMPr : case X86 :: TAILJMPd64 : case X86 :: TAILJMPm64 : case X86 :: TAILJMPr64 : case X86 :: TAILJMPm64_REX : case X86 :: TAILJMPr64_REX : return true ; default : return false ; } } </s>

Determines whether Inst is a tail call instruction .


<s>
void
TL45AsmBackend
::
applyFixup
(
const
MCAssembler
&
Asm
,
const
MCFixup
&
Fixup
,
const
MCValue
&
Target
,
MutableArrayRef
<
char
>
Data
,
uint64_t
Value
,
bool
IsResolved
,
const
MCSubtargetInfo
*
STI
)
const
{
MCContext
&
Ctx
=
Asm
.
getContext
(
)
;
MCFixupKindInfo
Info
=
getFixupKindInfo
(
Fixup
.
getKind
(
)
)
;
if
(
!
Value
)
return
;
Value
=
adjustFixupValue
(
Fixup
,
Value
,
Ctx
)
;
Value
<<=
Info
.
TargetOffset
;
unsigned
Offset
=
Fixup
.
getOffset
(
)
;
unsigned
NumBytes
=
alignTo
(
Info
.
TargetSize
+
Info
.
TargetOffset
,
8
)
/
8
;
assert
(
Offset
+
NumBytes
<=
Data
.
size
(
)
&&
"Invalid fixup offset!"
)
;
for
(
unsigned
i
=
0
;
i
!=
NumBytes
;
++
i
)
{
Data
[
Offset
+
i
]
|=
uint8_t
(
(
Value
>>
(
i
*
8
)
)
&
0xff
)
;
}
}
</s>

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


<s> bool convertSelectOfConstantsToMath ( EVT VT ) const override { return true ; } </s>

Return true if a select of constants ( select Cond , C1 , C2 ) should be transformed into simple math ops with the condition value .


<s> MachineBasicBlock :: iterator Thumb1FrameLowering :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { const Thumb1InstrInfo & TII = * static_cast < const Thumb1InstrInfo * > ( STI . getInstrInfo ( ) ) ; const ThumbRegisterInfo * RegInfo = static_cast < const ThumbRegisterInfo * > ( STI . getRegisterInfo ( ) ) ; if ( ! hasReservedCallFrame ( MF ) ) { MachineInstr * Old = I ; DebugLoc dl = Old -> getDebugLoc ( ) ; unsigned Amount = Old -> getOperand ( 0 ) . getImm ( ) ; if ( Amount != 0 ) { unsigned Align = getStackAlignment ( ) ; Amount = ( Amount + Align - 1 ) / Align * Align ; unsigned Opc = Old -> getOpcode ( ) ; if ( Opc == ARM :: ADJCALLSTACKDOWN || Opc == ARM :: tADJCALLSTACKDOWN ) { emitSPUpdate ( MBB , I , TII , dl , * RegInfo , - Amount ) ; } else { assert ( Opc == ARM :: ADJCALLSTACKUP || Opc == ARM :: tADJCALLSTACKUP ) ; emitSPUpdate ( MBB , I , TII , dl , * RegInfo , Amount ) ; } } } return MBB . erase ( I ) ; } </s>

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .


<s> bool apply_vl_p ( ) const override { return false ; } </s>

We choose to apply vl operand by default since most of the intrinsics has vl operand .


<s> static unsigned int ia64_function_arg_boundary ( machine_mode mode , const_tree type ) { if ( mode == TFmode && TARGET_HPUX && TARGET_ILP32 ) return PARM_BOUNDARY * 2 ; if ( type ) { if ( TYPE_ALIGN ( type ) > PARM_BOUNDARY ) return PARM_BOUNDARY * 2 ; else return PARM_BOUNDARY ; } if ( GET_MODE_BITSIZE ( mode ) > PARM_BOUNDARY ) return PARM_BOUNDARY * 2 ; else return PARM_BOUNDARY ; } </s>

Arguments with alignment larger than 8 bytes start at the next even boundary . On ILP32 HPUX , TFmode arguments start on next even boundary even though their normal alignment is 8 bytes . See ia64_function_arg .


<s> static unsigned getHashValue ( SPIRV :: SpecialTypeDescriptor Val ) { return Val . getHash ( ) ; } </s>

Using name and line to get hash value . It should already be mostly unique .


<s> SDValue MipsTargetLowering :: PerformDAGCombine ( SDNode * N , DAGCombinerInfo & DCI ) const { SelectionDAG & DAG = DCI . DAG ; unsigned Opc = N -> getOpcode ( ) ; switch ( Opc ) { default : break ; case ISD :: SDIVREM : case ISD :: UDIVREM : return performDivRemCombine ( N , DAG , DCI , Subtarget ) ; case ISD :: SELECT : return performSELECTCombine ( N , DAG , DCI , Subtarget ) ; case MipsISD :: CMovFP_F : case MipsISD :: CMovFP_T : return performCMovFPCombine ( N , DAG , DCI , Subtarget ) ; case ISD :: AND : return performANDCombine ( N , DAG , DCI , Subtarget ) ; case ISD :: OR : return performORCombine ( N , DAG , DCI , Subtarget ) ; case ISD :: ADD : return performADDCombine ( N , DAG , DCI , Subtarget ) ; case ISD :: SHL : return performSHLCombine ( N , DAG , DCI , Subtarget ) ; case ISD :: SUB : return performSUBCombine ( N , DAG , DCI , Subtarget ) ; case ISD :: PTRADD : return performCIncOffsetToCandAddrCombine ( N , DAG , DCI , Subtarget ) ; case ISD :: INTRINSIC_WO_CHAIN : return performINTRINSIC_WO_CHAINCombine ( N , DAG , DCI , Subtarget ) ; } return SDValue ( ) ; } </s>

This method will be invoked for all target nodes and for any target-independent nodes that the target has registered with invoke it for .

Mips Mips ISD::SDIVREM ISD::UDIVREM ISD::SELECT MipsISD::CMovFP_F MipsISD::CMovFP_T ISD::AND ISD::OR ISD::ADD ISD::SHL ISD::SUB ISD::PTRADD ISD::INTRINSIC_WO_CHAIN


<s> EVT getSetCCResultType ( const DataLayout & DL , LLVMContext & Ctx , EVT VT ) const override { if ( VT . isVector ( ) ) return EVT :: getVectorVT ( Ctx , MVT :: i1 , VT . getVectorNumElements ( ) ) ; return MVT :: i1 ; } </s>

Return the value type to use for ISD : :SETCC .


<s> static section * rs6000_elf_select_rtx_section ( machine_mode mode , rtx x , unsigned HOST_WIDE_INT align ) { if ( ASM_OUTPUT_SPECIAL_POOL_ENTRY_P ( x , mode ) ) return toc_section ; else return default_elf_select_rtx_section ( mode , x , align ) ; } </s>

A C statement or statements to switch to the appropriate section for output of RTX in mode MODE . You can assume that RTX is some kind of constant in RTL . The argument MODE is redundant except in the case of a ` const_int ' rtx . Select the section by calling ` text_section ' or one of the alternatives for other sections . Do not define this macro if you put all constants in the read-only data section .


<s> RegisterBankInfo :: InstructionMappings X86RegisterBankInfo :: getInstrAlternativeMappings ( const MachineInstr & MI ) const { const MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ; const TargetSubtargetInfo & STI = MF . getSubtarget ( ) ; const TargetRegisterInfo & TRI = * STI . getRegisterInfo ( ) ; const MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; switch ( MI . getOpcode ( ) ) { case TargetOpcode :: G_LOAD : case TargetOpcode :: G_STORE : case TargetOpcode :: G_IMPLICIT_DEF : { unsigned Size = getSizeInBits ( MI . getOperand ( 0 ) . getReg ( ) , MRI , TRI ) ; if ( Size != 32 && Size != 64 ) break ; unsigned NumOperands = MI . getNumOperands ( ) ; SmallVector < PartialMappingIdx , 4 > OpRegBankIdx ( NumOperands ) ; getInstrPartialMappingIdxs ( MI , MRI , true , OpRegBankIdx ) ; SmallVector < const ValueMapping * , 8 > OpdsMapping ( NumOperands ) ; if ( ! getInstrValueMapping ( MI , OpRegBankIdx , OpdsMapping ) ) break ; const RegisterBankInfo :: InstructionMapping & Mapping = getInstructionMapping ( 1 , 1 , getOperandsMapping ( OpdsMapping ) , NumOperands ) ; InstructionMappings AltMappings ; AltMappings . push_back ( & Mapping ) ; return AltMappings ; } default : break ; } return RegisterBankInfo :: getInstrAlternativeMappings ( MI ) ; } </s>


Value should be nonzero if functions must have frame pointers . Zero means the frame pointer need not be set up ( and parms may be accessed via the stack pointer ) in functions that seem suitable .


<s> unsigned AMDGPUTTI :: getNumberOfRegisters ( bool Vec ) const { if ( Vec ) return 0 ; if ( ST -> getGeneration ( ) >= AMDGPUSubtarget :: SOUTHERN_ISLANDS ) return 256 ; return 4 * 128 ; } </s>


<s> poly_int64 riscv_v_adjust_precision ( machine_mode mode , int scale ) { if ( riscv_v_ext_vector_mode_p ( mode ) ) return riscv_vector_chunks * scale ; return scale ; } </s>

Call from ADJUST_PRECISION in riscv-modes.def . Return the correct PRECISION size for corresponding machine_mode .


<s> outliner :: TargetCostInfo AArch64InstrInfo :: getOutliningCandidateInfo ( std :: vector < outliner :: Candidate > & RepeatedSequenceLocs ) const { unsigned SequenceSize = std :: accumulate ( RepeatedSequenceLocs [ 0 ] . front ( ) , std :: next ( RepeatedSequenceLocs [ 0 ] . back ( ) ) , 0 , [ this ] ( unsigned Sum , const MachineInstr & MI ) { return Sum + getInstSizeInBytes ( MI ) ; } ) ; unsigned CallID = MachineOutlinerDefault ; unsigned FrameID = MachineOutlinerDefault ; unsigned NumBytesForCall = 12 ; unsigned NumBytesToCreateFrame = 4 ; const TargetRegisterInfo & TRI = getRegisterInfo ( ) ; std :: for_each ( RepeatedSequenceLocs . begin ( ) , RepeatedSequenceLocs . end ( ) , [ & TRI ] ( outliner :: Candidate & C ) { C . initLRU ( TRI ) ; } ) ; auto CantGuaranteeValueAcrossCall = [ ] ( outliner :: Candidate & C ) { LiveRegUnits LRU = C . LRU ; return ( ! LRU . available ( AArch64 :: W16 ) || ! LRU . available ( AArch64 :: W17 ) || ! LRU . available ( AArch64 :: NZCV ) ) ; } ; RepeatedSequenceLocs . erase ( std :: remove_if ( RepeatedSequenceLocs . begin ( ) , RepeatedSequenceLocs . end ( ) , CantGuaranteeValueAcrossCall ) , RepeatedSequenceLocs . end ( ) ) ; unsigned LastInstrOpcode = RepeatedSequenceLocs [ 0 ] . back ( ) -> getOpcode ( ) ; if ( RepeatedSequenceLocs [ 0 ] . back ( ) -> isTerminator ( ) ) { CallID = MachineOutlinerTailCall ; FrameID = MachineOutlinerTailCall ; NumBytesForCall = 4 ; NumBytesToCreateFrame = 0 ; } else if ( LastInstrOpcode == AArch64 :: BL || LastInstrOpcode == AArch64 :: BLR ) { CallID = MachineOutlinerThunk ; FrameID = MachineOutlinerThunk ; NumBytesForCall = 4 ; NumBytesToCreateFrame = 0 ; } else if ( std :: all_of ( RepeatedSequenceLocs . begin ( ) , RepeatedSequenceLocs . end ( ) , [ ] ( outliner :: Candidate & C ) { return C . LRU . available ( AArch64 :: LR ) ; } ) ) { CallID = MachineOutlinerNoLRSave ; FrameID = MachineOutlinerNoLRSave ; NumBytesForCall = 4 ; NumBytesToCreateFrame = 4 ; } if ( std :: any_of ( RepeatedSequenceLocs [ 0 ] . front ( ) , RepeatedSequenceLocs [ 0 ] . back ( ) , [ ] ( const MachineInstr & MI ) { return MI . isCall ( ) ; } ) ) NumBytesToCreateFrame += 8 ; else if ( FrameID != MachineOutlinerThunk && FrameID != MachineOutlinerTailCall && RepeatedSequenceLocs [ 0 ] . back ( ) -> isCall ( ) ) NumBytesToCreateFrame += 8 ; return outliner :: TargetCostInfo ( SequenceSize , NumBytesForCall , NumBytesToCreateFrame , CallID , FrameID ) ; } </s>

Returns a outliner : :OutlinedFunction struct containing target-specific information for a set of outlining candidates .


<s> void aarch64_split_compare_and_swap ( rtx operands [ ] ) { rtx rval , mem , oldval , newval , scratch ; machine_mode mode ; bool is_weak ; rtx_code_label * label1 , * label2 ; rtx x , cond ; rval = operands [ 0 ] ; mem = operands [ 1 ] ; oldval = operands [ 2 ] ; newval = operands [ 3 ] ; is_weak = ( operands [ 4 ] != const0_rtx ) ; scratch = operands [ 7 ] ; mode = GET_MODE ( mem ) ; label1 = NULL ; if ( ! is_weak ) { label1 = gen_label_rtx ( ) ; emit_label ( label1 ) ; } label2 = gen_label_rtx ( ) ; aarch64_emit_load_exclusive ( mode , rval , mem , operands [ 5 ] ) ; cond = aarch64_gen_compare_reg ( NE , rval , oldval ) ; x = gen_rtx_NE ( VOIDmode , cond , const0_rtx ) ; x = gen_rtx_IF_THEN_ELSE ( VOIDmode , x , gen_rtx_LABEL_REF ( Pmode , label2 ) , pc_rtx ) ; aarch64_emit_unlikely_jump ( gen_rtx_SET ( VOIDmode , pc_rtx , x ) ) ; aarch64_emit_store_exclusive ( mode , scratch , mem , newval , operands [ 5 ] ) ; if ( ! is_weak ) { x = gen_rtx_NE ( VOIDmode , scratch , const0_rtx ) ; x = gen_rtx_IF_THEN_ELSE ( VOIDmode , x , gen_rtx_LABEL_REF ( Pmode , label1 ) , pc_rtx ) ; aarch64_emit_unlikely_jump ( gen_rtx_SET ( VOIDmode , pc_rtx , x ) ) ; } else { cond = gen_rtx_REG ( CCmode , CC_REGNUM ) ; x = gen_rtx_COMPARE ( CCmode , scratch , const0_rtx ) ; emit_insn ( gen_rtx_SET ( VOIDmode , cond , x ) ) ; } emit_label ( label2 ) ; } </s>


"ARM hazards don't support scoreboard lookahead"

getHazardType - Return the hazard type of emitting this node .


<s> bool MipsTargetLowering :: IsGlobalInSmallSection ( GlobalValue * GV ) { const TargetData * TD = getTargetData ( ) ; const GlobalVariable * GVA = dyn_cast < GlobalVariable > ( GV ) ; if ( ! GVA ) return false ; const Type * Ty = GV -> getType ( ) -> getElementType ( ) ; unsigned Size = TD -> getTypePaddedSize ( Ty ) ; if ( GVA -> hasInitializer ( ) && GV -> hasLocalLinkage ( ) ) { Constant * C = GVA -> getInitializer ( ) ; const ConstantArray * CVA = dyn_cast < ConstantArray > ( C ) ; if ( CVA && CVA -> isCString ( ) ) return false ; } return IsInSmallSection ( Size ) ; } </s>

Return true if this global address should be placed into small data/bss section .


<s> MachineBasicBlock :: iterator PPCFrameLowering :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { const TargetInstrInfo & TII = * Subtarget . getInstrInfo ( ) ; if ( MF . getTarget ( ) . Options . GuaranteedTailCallOpt && I -> getOpcode ( ) == PPC :: ADJCALLSTACKUP ) { if ( int CalleeAmt = I -> getOperand ( 1 ) . getImm ( ) ) { bool is64Bit = Subtarget . isPPC64 ( ) ; CalleeAmt *= - 1 ; unsigned StackReg = is64Bit ? PPC :: X1 : PPC :: R1 ; unsigned TmpReg = is64Bit ? PPC :: X0 : PPC :: R0 ; unsigned ADDIInstr = is64Bit ? PPC :: ADDI8 : PPC :: ADDI ; unsigned ADDInstr = is64Bit ? PPC :: ADD8 : PPC :: ADD4 ; unsigned LISInstr = is64Bit ? PPC :: LIS8 : PPC :: LIS ; unsigned ORIInstr = is64Bit ? PPC :: ORI8 : PPC :: ORI ; const DebugLoc & dl = I -> getDebugLoc ( ) ; if ( isInt < 16 > ( CalleeAmt ) ) { BuildMI ( MBB , I , dl , TII . get ( ADDIInstr ) , StackReg ) . addReg ( StackReg , RegState :: Kill ) . addImm ( CalleeAmt ) ; } else { MachineBasicBlock :: iterator MBBI = I ; BuildMI ( MBB , MBBI , dl , TII . get ( LISInstr ) , TmpReg ) . addImm ( CalleeAmt >> 16 ) ; BuildMI ( MBB , MBBI , dl , TII . get ( ORIInstr ) , TmpReg ) . addReg ( TmpReg , RegState :: Kill ) . addImm ( CalleeAmt & 0xFFFF ) ; BuildMI ( MBB , MBBI , dl , TII . get ( ADDInstr ) , StackReg ) . addReg ( StackReg , RegState :: Kill ) . addReg ( TmpReg ) ; } } } return MBB . erase ( I ) ; } </s>


<s>
void
PPCMIPeephole
::
initialize
(
MachineFunction
&
MFParm
)
{
MF
=
&
MFParm
;
MRI
=
&
MF
->
getRegInfo
(
)
;
MDT
=
&
getAnalysis
<
MachineDominatorTree
>
(
)
;
TII
=
MF
->
getSubtarget
<
PPCSubtarget
>
(
)
.
getInstrInfo
(
)
;
DEBUG
(
dbgs
(
)
<<
"*** PowerPC MI peephole pass ***\n\n"
)
;
DEBUG
(
MF
->
dump
(
)
)
;
}
</s>

Initialize the strategy after building the DAG for a new region .

PowerPC
PPC
PPC
"*** PowerPC MI peephole pass ***\n\n"


<s> void RISCVAsmPrinter :: emitFunctionEntryLabel ( ) { AsmPrinter :: emitFunctionEntryLabel ( ) ; RISCVTargetStreamer & RTS = static_cast < RISCVTargetStreamer & > ( * OutStreamer -> getTargetStreamer ( ) ) ; RTS . setTargetABI ( STI -> getTargetABI ( ) ) ; } </s>

EmitFunctionEntryLabel - Emit the label that is the entrypoint for the function .


<s> static void sparc32_initialize_trampoline ( rtx m_tramp , rtx fnaddr , rtx cxt ) { emit_move_insn ( adjust_address ( m_tramp , SImode , 0 ) , expand_binop ( SImode , ior_optab , expand_shift ( RSHIFT_EXPR , SImode , fnaddr , 10 , 0 , 1 ) , GEN_INT ( trunc_int_for_mode ( 0x03000000 , SImode ) ) , NULL_RTX , 1 , OPTAB_DIRECT ) ) ; emit_move_insn ( adjust_address ( m_tramp , SImode , 4 ) , expand_binop ( SImode , ior_optab , expand_shift ( RSHIFT_EXPR , SImode , cxt , 10 , 0 , 1 ) , GEN_INT ( trunc_int_for_mode ( 0x05000000 , SImode ) ) , NULL_RTX , 1 , OPTAB_DIRECT ) ) ; emit_move_insn ( adjust_address ( m_tramp , SImode , 8 ) , expand_binop ( SImode , ior_optab , expand_and ( SImode , fnaddr , GEN_INT ( 0x3ff ) , NULL_RTX ) , GEN_INT ( trunc_int_for_mode ( 0x81c06000 , SImode ) ) , NULL_RTX , 1 , OPTAB_DIRECT ) ) ; emit_move_insn ( adjust_address ( m_tramp , SImode , 12 ) , expand_binop ( SImode , ior_optab , expand_and ( SImode , cxt , GEN_INT ( 0x3ff ) , NULL_RTX ) , GEN_INT ( trunc_int_for_mode ( 0x8410a000 , SImode ) ) , NULL_RTX , 1 , OPTAB_DIRECT ) ) ; emit_insn ( gen_flushsi ( validize_mem ( adjust_address ( m_tramp , SImode , 0 ) ) ) ) ; if ( sparc_cpu != PROCESSOR_ULTRASPARC && sparc_cpu != PROCESSOR_ULTRASPARC3 && sparc_cpu != PROCESSOR_NIAGARA && sparc_cpu != PROCESSOR_NIAGARA2 && sparc_cpu != PROCESSOR_NIAGARA3 && sparc_cpu != PROCESSOR_NIAGARA4 ) emit_insn ( gen_flushsi ( validize_mem ( adjust_address ( m_tramp , SImode , 8 ) ) ) ) ; emit_library_call ( gen_rtx_SYMBOL_REF ( Pmode , "__enable_execute_stack" ) , LCT_NORMAL , VOIDmode , 1 , XEXP ( m_tramp , 0 ) , Pmode ) ; } </s>

Emit RTL insns to initialize the variable parts of a trampoline . FNADDR is an RTX for the address of the function 's pure code . CXT is an RTX for the static chain value for the function . This takes 16 insns : 2 shifts & 2 ands ( to split up addresses ) , 4 sethi ( to load in opcodes ) , 4 iors ( to merge address and opcodes ) , and 4 writes ( to store insns ) . This is a bit excessive . Perhaps a different mechanism would be better here . Emit enough FLUSH insns to synchronize the data and instruction caches .


<s> void initialize ( MachineBasicBlock & MBB ) { Visited . clear ( ) ; CommonDominators . clear ( ) ; Stack . clear ( ) ; NextLevel . clear ( ) ; VisitedPostDom = nullptr ; FoundLoopLevel = ~ 0u ; DefBlock = & MBB ; } </s>


<s> void ARMConstantPoolValue :: print ( raw_ostream & O ) const { if ( CVal ) O << CVal -> getName ( ) ; else O << S ; if ( Modifier ) O << "(" << Modifier << ")" ; if ( PCAdjust != 0 ) { O << "-(LPC" << LabelId << "+" << ( unsigned ) PCAdjust ; if ( AddCurrentAddress ) O << "-." ; O << ")" ; } } </s>

print - Print a debug representation of the operand to the given stream .


<s>
bool
AArch64InstrInfo
::
areMemAccessesTriviallyDisjoint
(
MachineInstr
*
MIa
,
MachineInstr
*
MIb
,
AliasAnalysis
*
AA
)
const
{
const
TargetRegisterInfo
*
TRI
=
&
getRegisterInfo
(
)
;
unsigned
BaseRegA
=
0
,
BaseRegB
=
0
;
int64_t
OffsetA
=
0
,
OffsetB
=
0
;
unsigned
WidthA
=
0
,
WidthB
=
0
;
assert
(
MIa
&&
MIa
->
mayLoadOrStore
(
)
&&
"MIa must be a load or store."
)
;
assert
(
MIb
&&
MIb
->
mayLoadOrStore
(
)
&&
"MIb must be a load or store."
)
;
if
(
MIa
->
hasUnmodeledSideEffects
(
)
||
MIb
->
hasUnmodeledSideEffects
(
)
||
MIa
->
hasOrderedMemoryRef
(
)
||
MIb
->
hasOrderedMemoryRef
(
)
)
return
false
;
if
(
getMemOpBaseRegImmOfsWidth
(
MIa
,
BaseRegA
,
OffsetA
,
WidthA
,
TRI
)
&&
getMemOpBaseRegImmOfsWidth
(
MIb
,
BaseRegB
,
OffsetB
,
WidthB
,
TRI
)
)
{
if
(
BaseRegA
==
BaseRegB
)
{
int
LowOffset
=
OffsetA
<
OffsetB
OffsetA
:
OffsetB
;
int
HighOffset
=
OffsetA
<
OffsetB
OffsetB
:
OffsetA
;
int
LowWidth
=
(
LowOffset
==
OffsetA
)
WidthA
:
WidthB
;
if
(
LowOffset
+
LowWidth
<=
HighOffset
)
return
true
;
}
}
return
false
;
}
</s>

Sometimes , it is possible for the target to tell , even without aliasing information , that two MIs access different memory addresses .


<s>
SDValue
TriCoreTargetLowering
::
LowerCallResult
(
SDValue
Chain
,
SDValue
InGlue
,
CallingConv
::
ID
CallConv
,
bool
isVarArg
,
const
SmallVectorImpl
<
ISD
::
InputArg
>
&
Ins
,
SDLoc
dl
,
SelectionDAG
&
DAG
,
SmallVectorImpl
<
SDValue
>
&
InVals
)
const
{
assert
(
!
isVarArg
&&
"Unsupported"
)
;
SmallVector
<
CCValAssign
,
16
>
RVLocs
;
CCState
CCInfo
(
CallConv
,
isVarArg
,
DAG
.
getMachineFunction
(
)
,
RVLocs
,
*
DAG
.
getContext
(
)
)
;
Type
*
t
=
DAG
.
getMachineFunction
(
)
.
getFunction
(
)
->
getReturnType
(
)
;
t
->
dump
(
)
;
outs
(
)
<<
"LowerCallResult IsPointer: "
<<
t
->
isPointerTy
(
)
<<
"\n"
;
CCInfo
.
AnalyzeCallResult
(
Ins
,
RetCC_TriCore
)
;
for
(
auto
&
Loc
:
RVLocs
)
{
if
(
t
->
isPointerTy
(
)
)
Loc
.
convertToReg
(
TriCore
::
A2
)
;
Chain
=
DAG
.
getCopyFromReg
(
Chain
,
dl
,
Loc
.
getLocReg
(
)
,
Loc
.
getValVT
(
)
,
InGlue
)
.
getValue
(
1
)
;
InGlue
=
Chain
.
getValue
(
2
)
;
InVals
.
push_back
(
Chain
.
getValue
(
0
)
)
;
}
return
Chain
;
}
</s>

LowerCallResult - Lower the result values of an ISD : :CALL into the appropriate copies out of appropriate physical registers .


<s> unsigned int compute_a_rotate_length ( rtx * operands ) { rtx src = operands [ 1 ] ; rtx amount_rtx = operands [ 2 ] ; machine_mode mode = GET_MODE ( src ) ; int amount ; unsigned int length = 0 ; gcc_assert ( GET_CODE ( amount_rtx ) == CONST_INT ) ; amount = INTVAL ( amount_rtx ) ; if ( amount < 0 ) amount = 0 ; if ( ( unsigned int ) amount > GET_MODE_BITSIZE ( mode ) ) amount = GET_MODE_BITSIZE ( mode ) ; if ( ( unsigned int ) amount > GET_MODE_BITSIZE ( mode ) / ( unsigned ) 2 ) amount = GET_MODE_BITSIZE ( mode ) - amount ; if ( ( mode == HImode && TARGET_H8300H && amount >= 6 ) || ( mode == HImode && TARGET_H8300S && amount == 8 ) || ( mode == SImode && TARGET_H8300H && amount >= 10 ) || ( mode == SImode && TARGET_H8300S && amount >= 13 ) ) { amount = GET_MODE_BITSIZE ( mode ) / 2 - amount ; length += 6 ; } if ( TARGET_H8300S ) amount = amount / 2 + amount % 2 ; length += amount * 2 ; return length ; } </s>


<s> unsigned AMDGPUIntrinsicInfo :: lookupName ( const char * NameData , unsigned Len ) const { StringRef Name ( NameData , Len ) ; if ( ! Name . startswith ( "llvm." ) ) return 0 ; int Idx = Intrinsic :: lookupLLVMIntrinsicByName ( IntrinsicNameTable , Name ) ; if ( Idx >= 0 ) { bool IsPrefixMatch = Name . size ( ) > strlen ( IntrinsicNameTable [ Idx ] ) ; return IsPrefixMatch == isOverloaded ( Idx + 1 ) ? Intrinsic :: num_intrinsics + Idx : 0 ; } return 0 ; } </s>


<s> bool runOnMachineFunction ( MachineFunction & MF ) override { return SelectionDAGISel :: runOnMachineFunction ( MF ) ; } </s>

runOnMachineFunction - Emit the function body .


<s> static Mnode * move_minipool_fix_forward_ref ( Mnode * mp , Mnode * max_mp , HOST_WIDE_INT max_address ) { gcc_assert ( mp != max_mp ) ; if ( max_mp == NULL ) { if ( max_address < mp -> max_address ) mp -> max_address = max_address ; } else { if ( max_address > max_mp -> max_address - mp -> fix_size ) mp -> max_address = max_mp -> max_address - mp -> fix_size ; else mp -> max_address = max_address ; mp -> prev -> next = mp -> next ; if ( mp -> next != NULL ) mp -> next -> prev = mp -> prev ; else minipool_vector_tail = mp -> prev ; mp -> next = max_mp ; mp -> prev = max_mp -> prev ; max_mp -> prev = mp ; if ( mp -> prev != NULL ) mp -> prev -> next = mp ; else minipool_vector_head = mp ; } max_mp = mp ; while ( mp -> prev != NULL && mp -> prev -> max_address > mp -> max_address - mp -> prev -> fix_size ) { mp -> prev -> max_address = mp -> max_address - mp -> prev -> fix_size ; mp = mp -> prev ; } return max_mp ; } </s>

Move a minipool fix MP from its current location to before MAX_MP . If MAX_MP is NULL , then MP does n't need moving , but the addressing contrains may need updating .


"Cannot allocate free scratch registers for the "


getThisReturnPreservedMask - Returns a call preserved mask specific to the case that 'returned ' is on an i32 first argument if the calling convention is one that can ( partially ) model this attribute with a preserved mask ( i.e .


"We need *some* way to materialise a constant"

Main hook for targets to transform nodes into machine nodes .


<s> HOST_WIDE_INT rs6000_builtin_mask_calculate ( void ) { return ( ( ( TARGET_ALTIVEC ) ? RS6000_BTM_ALTIVEC : 0 ) | ( ( TARGET_VSX ) ? RS6000_BTM_VSX : 0 ) | ( ( TARGET_SPE ) ? RS6000_BTM_SPE : 0 ) | ( ( TARGET_PAIRED_FLOAT ) ? RS6000_BTM_PAIRED : 0 ) | ( ( TARGET_FRE ) ? RS6000_BTM_FRE : 0 ) | ( ( TARGET_FRES ) ? RS6000_BTM_FRES : 0 ) | ( ( TARGET_FRSQRTE ) ? RS6000_BTM_FRSQRTE : 0 ) | ( ( TARGET_FRSQRTES ) ? RS6000_BTM_FRSQRTES : 0 ) | ( ( TARGET_POPCNTD ) ? RS6000_BTM_POPCNTD : 0 ) | ( ( rs6000_cpu == PROCESSOR_CELL ) ? RS6000_BTM_CELL : 0 ) | ( ( TARGET_P8_VECTOR ) ? RS6000_BTM_P8_VECTOR : 0 ) | ( ( TARGET_CRYPTO ) ? RS6000_BTM_CRYPTO : 0 ) | ( ( TARGET_HTM ) ? RS6000_BTM_HTM : 0 ) | ( ( TARGET_DFP ) ? RS6000_BTM_DFP : 0 ) | ( ( TARGET_HARD_FLOAT ) ? RS6000_BTM_HARD_FLOAT : 0 ) | ( ( TARGET_LONG_DOUBLE_128 ) ? RS6000_BTM_LDBL128 : 0 ) ) ; } </s>

Return the builtin mask of the various options used that could affect which builtins were used . In the past we used target_flags , but we 've run out of bits , and some options like PAIRED are no longer in target_flags .


<s> void Mips16FrameLowering :: emitPrologue ( MachineFunction & MF , MachineBasicBlock & MBB ) const { MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const Mips16InstrInfo & TII = * static_cast < const Mips16InstrInfo * > ( STI . getInstrInfo ( ) ) ; MachineBasicBlock :: iterator MBBI = MBB . begin ( ) ; DebugLoc dl ; uint64_t StackSize = MFI . getStackSize ( ) ; if ( StackSize == 0 && ! MFI . adjustsStack ( ) ) return ; MachineModuleInfo & MMI = MF . getMMI ( ) ; const MCRegisterInfo * MRI = MMI . getContext ( ) . getRegisterInfo ( ) ; TII . makeFrame ( Mips :: SP , StackSize , MBB , MBBI ) ; unsigned CFIIndex = MF . addFrameInst ( MCCFIInstruction :: cfiDefCfaOffset ( nullptr , StackSize ) ) ; BuildMI ( MBB , MBBI , dl , TII . get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; const std :: vector < CalleeSavedInfo > & CSI = MFI . getCalleeSavedInfo ( ) ; if ( ! CSI . empty ( ) ) { const std :: vector < CalleeSavedInfo > & CSI = MFI . getCalleeSavedInfo ( ) ; for ( std :: vector < CalleeSavedInfo > :: const_iterator I = CSI . begin ( ) , E = CSI . end ( ) ; I != E ; ++ I ) { int64_t Offset = MFI . getObjectOffset ( I -> getFrameIdx ( ) ) ; unsigned Reg = I -> getReg ( ) ; unsigned DReg = MRI -> getDwarfRegNum ( Reg , true ) ; unsigned CFIIndex = MF . addFrameInst ( MCCFIInstruction :: createOffset ( nullptr , DReg , Offset ) ) ; BuildMI ( MBB , MBBI , dl , TII . get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; } } if ( hasFP ( MF ) ) BuildMI ( MBB , MBBI , dl , TII . get ( Mips :: MoveR3216 ) , Mips :: S0 ) . addReg ( Mips :: SP ) . setMIFlag ( MachineInstr :: FrameSetup ) ; } </s>

emitProlog/emitEpilog - These methods insert prolog and epilog code into the function .


<s> static void aarch64_option_save ( struct cl_target_option * ptr , struct gcc_options * opts ) { ptr -> x_aarch64_override_tune_string = opts -> x_aarch64_override_tune_string ; ptr -> x_aarch64_branch_protection_string = opts -> x_aarch64_branch_protection_string ; } </s>


<s> void arm_expand_compare_and_swap ( rtx operands [ ] ) { rtx bval , bdst , rval , mem , oldval , newval , is_weak , mod_s , mod_f , x ; machine_mode mode ; rtx ( * gen ) ( rtx , rtx , rtx , rtx , rtx , rtx , rtx , rtx ) ; bval = operands [ 0 ] ; rval = operands [ 1 ] ; mem = operands [ 2 ] ; oldval = operands [ 3 ] ; newval = operands [ 4 ] ; is_weak = operands [ 5 ] ; mod_s = operands [ 6 ] ; mod_f = operands [ 7 ] ; mode = GET_MODE ( mem ) ; if ( TARGET_HAVE_LDACQ && is_mm_acquire ( memmodel_from_int ( INTVAL ( mod_f ) ) ) && is_mm_release ( memmodel_from_int ( INTVAL ( mod_s ) ) ) ) mod_s = GEN_INT ( MEMMODEL_ACQ_REL ) ; switch ( mode ) { case QImode : case HImode : rval = gen_reg_rtx ( SImode ) ; oldval = convert_modes ( SImode , mode , oldval , true ) ; case SImode : if ( ! arm_add_operand ( oldval , SImode ) ) oldval = force_reg ( SImode , oldval ) ; break ; case DImode : if ( ! cmpdi_operand ( oldval , mode ) ) oldval = force_reg ( mode , oldval ) ; break ; default : gcc_unreachable ( ) ; } switch ( mode ) { case QImode : gen = gen_atomic_compare_and_swapqi_1 ; break ; case HImode : gen = gen_atomic_compare_and_swaphi_1 ; break ; case SImode : gen = gen_atomic_compare_and_swapsi_1 ; break ; case DImode : gen = gen_atomic_compare_and_swapdi_1 ; break ; default : gcc_unreachable ( ) ; } bdst = TARGET_THUMB1 ? bval : gen_rtx_REG ( CCmode , CC_REGNUM ) ; emit_insn ( gen ( bdst , rval , mem , oldval , newval , is_weak , mod_s , mod_f ) ) ; if ( mode == QImode || mode == HImode ) emit_move_insn ( operands [ 1 ] , gen_lowpart ( mode , rval ) ) ; if ( TARGET_THUMB1 ) emit_insn ( gen_cstoresi_eq0_thumb1 ( bval , bdst ) ) ; else { x = gen_rtx_EQ ( SImode , bdst , const0_rtx ) ; emit_insn ( gen_rtx_SET ( bval , x ) ) ; } } </s>


<s>
bool
ARMAsmPrinter
::
PrintAsmMemoryOperand
(
const
MachineInstr
*
MI
,
unsigned
OpNum
,
unsigned
AsmVariant
,
const
char
*
ExtraCode
,
raw_ostream
&
O
)
{
if
(
ExtraCode
&&
ExtraCode
[
0
]
)
return
true
;
const
MachineOperand
&
MO
=
MI
->
getOperand
(
OpNum
)
;
assert
(
MO
.
isReg
(
)
&&
"unexpected inline asm memory operand"
)
;
O
<<
"["
<<
ARMInstPrinter
::
getRegisterName
(
MO
.
getReg
(
)
)
<<
"]"
;
return
false
;
}
</s>

Print the specified operand of MI , an INLINEASM instruction , using the specified assembler variant as an address .

ARM
ARM
0
"unexpected inline asm memory operand"
"["
ARM
"]"


<s> rtx s390_back_chain_rtx ( void ) { rtx chain ; gcc_assert ( TARGET_BACKCHAIN ) ; if ( TARGET_PACKED_STACK ) chain = plus_constant ( stack_pointer_rtx , STACK_POINTER_OFFSET - UNITS_PER_WORD ) ; else chain = stack_pointer_rtx ; chain = gen_rtx_MEM ( Pmode , chain ) ; return chain ; } </s>

Return an RTL expression representing the back chain stored in the current stack frame .


<s> static void bfin_extra_live_on_entry ( bitmap regs ) { if ( TARGET_FDPIC ) bitmap_set_bit ( regs , FDPIC_REGNO ) ; } </s>


<s>
void
AMDGPURegisterInfo
::
eliminateFrameIndex
(
MachineBasicBlock
::
iterator
MI
,
int
SPAdj
,
unsigned
FIOperandNum
,
RegScavenger
*
RS
)
const
{
assert
(
!
"Subroutines not supported yet"
)
;
}
</s>

This method must be overriden to eliminate abstract frame indices from instructions which may use them .


<s>
SDValue
SystemZTargetLowering
::
LowerCall
(
SDValue
Chain
,
SDValue
Callee
,
CallingConv
::
ID
CallConv
,
bool
isVarArg
,
bool
&
isTailCall
,
const
SmallVectorImpl
<
ISD
::
OutputArg
>
&
Outs
,
const
SmallVectorImpl
<
SDValue
>
&
OutVals
,
const
SmallVectorImpl
<
ISD
::
InputArg
>
&
Ins
,
DebugLoc
dl
,
SelectionDAG
&
DAG
,
SmallVectorImpl
<
SDValue
>
&
InVals
)
const
{
isTailCall
=
false
;
switch
(
CallConv
)
{
default
:
llvm_unreachable
(
"Unsupported calling convention"
)
;
case
CallingConv
::
Fast
:
case
CallingConv
::
C
:
return
LowerCCCCallTo
(
Chain
,
Callee
,
CallConv
,
isVarArg
,
isTailCall
,
Outs
,
OutVals
,
Ins
,
dl
,
DAG
,
InVals
)
;
}
}
</s>

This hook must be implemented to lower calls into the specified DAG .

SystemZ
SystemZ
ISD::OutputArg
ISD::InputArg
"Unsupported calling convention"


<s> bool pushpop_regeq ( rtx op , int regno ) { rtx addr ; if ( GET_CODE ( op ) != MEM ) return FALSE ; addr = XEXP ( op , 0 ) ; if ( GET_CODE ( addr ) == MEM ) addr = XEXP ( addr , 0 ) ; switch ( GET_CODE ( addr ) ) { case PRE_DEC : case POST_INC : case PRE_MODIFY : case POST_MODIFY : return REGNO ( XEXP ( addr , 0 ) ) == ( unsigned ) regno ; default : return FALSE ; } } </s>

Return TRUE if op is a push or pop using the register `` regno '' .


<s> unsigned getNumFixupKinds ( ) const override { return RV16K :: NumTargetFixupKinds ; } </s>

Get the number of target specific fixup kinds .


<s> void PPCRegisterInfo :: determineFrameLayout ( MachineFunction & MF ) const { MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; unsigned FrameSize = MFI -> getStackSize ( ) ; unsigned MaxAlign = MFI -> getMaxAlignment ( ) ; unsigned TargetAlign = MF . getTarget ( ) . getFrameInfo ( ) -> getStackAlignment ( ) ; unsigned AlignMask = TargetAlign - 1 ; bool DisableRedZone = MF . getFunction ( ) -> hasFnAttr ( Attribute :: NoRedZone ) ; if ( ! DisableRedZone && FrameSize <= 224 && ! MFI -> hasVarSizedObjects ( ) && ! MFI -> hasCalls ( ) && ( ! ALIGN_STACK || MaxAlign <= TargetAlign ) ) { MFI -> setStackSize ( 0 ) ; return ; } unsigned maxCallFrameSize = MFI -> getMaxCallFrameSize ( ) ; unsigned minCallFrameSize = PPCFrameInfo :: getMinCallFrameSize ( Subtarget . isPPC64 ( ) , Subtarget . isDarwinABI ( ) ) ; maxCallFrameSize = std :: max ( maxCallFrameSize , minCallFrameSize ) ; if ( MFI -> hasVarSizedObjects ( ) ) maxCallFrameSize = ( maxCallFrameSize + AlignMask ) & ~ AlignMask ; MFI -> setMaxCallFrameSize ( maxCallFrameSize ) ; FrameSize += maxCallFrameSize ; FrameSize = ( FrameSize + AlignMask ) & ~ AlignMask ; MFI -> setStackSize ( FrameSize ) ; } </s>

Determine the frame layout but do not update the machine function .


<s>
bool
RISCVInstrInfo
::
reverseBranchCondition
(
SmallVectorImpl
<
MachineOperand
>
&
Cond
)
const
{
assert
(
(
Cond
.
size
(
)
==
3
)
&&
"Invalid branch condition!"
)
;
Cond
[
0
]
.
setImm
(
getOppositeBranchOpcode
(
Cond
[
0
]
.
getImm
(
)
)
)
;
return
false
;
}
</s>

Reverses the branch condition of the specified condition list , returning false on success and true if it can not be reversed .


<s> FunctionPass * JVMPassConfig :: createTargetRegisterAllocator ( bool ) { return nullptr ; } </s>

createTargetRegisterAllocator - Create the register allocator pass for this target at the current optimization level .


<s> bool AMDGPUCFGStructurizer :: prepare ( ) { bool Changed = false ; DEBUG ( dbgs ( ) << "AMDGPUCFGStructurizer::prepare\n" ; ) ; orderBlocks ( FuncRep ) ; SmallVector < MachineBasicBlock * , DEFAULT_VEC_SLOTS > RetBlks ; for ( MachineLoopInfo :: iterator It = MLI -> begin ( ) , E = MLI -> end ( ) ; It != E ; ++ It ) { MachineLoop * LoopRep = ( * It ) ; MBBVector ExitingMBBs ; LoopRep -> getExitingBlocks ( ExitingMBBs ) ; if ( ExitingMBBs . size ( ) == 0 ) { MachineBasicBlock * DummyExitBlk = normalizeInfiniteLoopExit ( LoopRep ) ; if ( DummyExitBlk ) RetBlks . push_back ( DummyExitBlk ) ; } } for ( SmallVectorImpl < MachineBasicBlock * > :: const_iterator It = OrderedBlks . begin ( ) , E = OrderedBlks . end ( ) ; It != E ; ++ It ) { MachineBasicBlock * MBB = * It ; removeUnconditionalBranch ( MBB ) ; removeRedundantConditionalBranch ( MBB ) ; if ( isReturnBlock ( MBB ) ) { RetBlks . push_back ( MBB ) ; } assert ( MBB -> succ_size ( ) <= 2 ) ; } if ( RetBlks . size ( ) >= 2 ) { addDummyExitBlock ( RetBlks ) ; Changed = true ; } return Changed ; } </s>

prepare - Reset state and prepare for a new spill placement computation .


<s> bool SITargetLowering :: canMergeStoresTo ( unsigned AS , EVT MemVT ) const { if ( AS == AMDGPUASI . GLOBAL_ADDRESS || AS == AMDGPUASI . FLAT_ADDRESS ) { return ( MemVT . getSizeInBits ( ) <= 4 * 32 ) ; } else if ( AS == AMDGPUASI . PRIVATE_ADDRESS ) { unsigned MaxPrivateBits = 8 * getSubtarget ( ) -> getMaxPrivateElementSize ( ) ; return ( MemVT . getSizeInBits ( ) <= MaxPrivateBits ) ; } else if ( AS == AMDGPUASI . LOCAL_ADDRESS ) { return ( MemVT . getSizeInBits ( ) <= 2 * 32 ) ; } return true ; } </s>

Returns if it 's reasonable to merge stores to MemVT size .


<s> llvm :: FastISel * ARM64 :: createFastISel ( FunctionLoweringInfo & funcInfo , const TargetLibraryInfo * libInfo ) { return new ARM64FastISel ( funcInfo , libInfo ) ; } </s>

This method returns a target specific FastISel object , or null if the target does not support `` fast '' ISel .


<s> unsigned getSlotSize ( ) const { return 4 ; } </s>

getSlotSize - Stack slot size in bytes .


"bad insn to frv_print_operand_address:"

Print a memory address as an operand to reference that memory location .


<s> BitVector X86RegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; const TargetFrameLowering * TFI = MF . getTarget ( ) . getFrameLowering ( ) ; Reserved . set ( X86 :: RSP ) ; for ( MCSubRegIterator I ( X86 :: RSP , this ) ; I . isValid ( ) ; ++ I ) Reserved . set ( * I ) ; Reserved . set ( X86 :: RIP ) ; for ( MCSubRegIterator I ( X86 :: RIP , this ) ; I . isValid ( ) ; ++ I ) Reserved . set ( * I ) ; if ( TFI -> hasFP ( MF ) ) { Reserved . set ( X86 :: RBP ) ; for ( MCSubRegIterator I ( X86 :: RBP , this ) ; I . isValid ( ) ; ++ I ) Reserved . set ( * I ) ; } Reserved . set ( X86 :: CS ) ; Reserved . set ( X86 :: SS ) ; Reserved . set ( X86 :: DS ) ; Reserved . set ( X86 :: ES ) ; Reserved . set ( X86 :: FS ) ; Reserved . set ( X86 :: GS ) ; Reserved . set ( X86 :: ST0 ) ; Reserved . set ( X86 :: ST1 ) ; Reserved . set ( X86 :: ST2 ) ; Reserved . set ( X86 :: ST3 ) ; Reserved . set ( X86 :: ST4 ) ; Reserved . set ( X86 :: ST5 ) ; Reserved . set ( X86 :: ST6 ) ; Reserved . set ( X86 :: ST7 ) ; if ( ! Is64Bit ) { Reserved . set ( X86 :: SIL ) ; Reserved . set ( X86 :: DIL ) ; Reserved . set ( X86 :: BPL ) ; Reserved . set ( X86 :: SPL ) ; for ( unsigned n = 0 ; n != 8 ; ++ n ) { static const uint16_t GPR64 [ ] = { X86 :: R8 , X86 :: R9 , X86 :: R10 , X86 :: R11 , X86 :: R12 , X86 :: R13 , X86 :: R14 , X86 :: R15 } ; for ( MCRegAliasIterator AI ( GPR64 [ n ] , this , true ) ; AI . isValid ( ) ; ++ AI ) Reserved . set ( * AI ) ; assert ( X86 :: XMM15 == X86 :: XMM8 + 7 ) ; for ( MCRegAliasIterator AI ( X86 :: XMM8 + n , this , true ) ; AI . isValid ( ) ; ++ AI ) Reserved . set ( * AI ) ; } } return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


"invalid id value for interrupt/exception attribute"

"invalid nmi function for reset attribute"

"invalid warm function for reset attribute"

Add some checking when inserting attributes .


<s> bool nds32_gw_mm_to_ex_p ( rtx_insn * producer , rtx_insn * consumer ) { rtx def_reg ; switch ( get_attr_type ( producer ) ) { case TYPE_LOAD : case TYPE_MUL : case TYPE_MAC : case TYPE_DALU64 : case TYPE_DMUL : case TYPE_DMAC : case TYPE_DALUROUND : case TYPE_DBPICK : case TYPE_DWEXT : def_reg = SET_DEST ( PATTERN ( producer ) ) ; break ; case TYPE_DIV : if ( divmod_p ( producer ) ) { rtx def_reg1 = SET_DEST ( parallel_element ( producer , 0 ) ) ; rtx def_reg2 = SET_DEST ( parallel_element ( producer , 1 ) ) ; return ( gw_consumed_by_ex_dep_p ( consumer , def_reg1 ) || gw_consumed_by_ex_dep_p ( consumer , def_reg2 ) ) ; } def_reg = SET_DEST ( PATTERN ( producer ) ) ; break ; default : gcc_unreachable ( ) ; } return gw_consumed_by_ex_dep_p ( consumer , def_reg ) ; } </s>


<s> bool J2FrameLowering :: spillCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo * TRI ) const { if ( CSI . empty ( ) ) return false ; DebugLoc DL ; if ( MI != MBB . end ( ) ) DL = MI -> getDebugLoc ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; const TargetInstrInfo & TII = * MF . getSubtarget ( ) . getInstrInfo ( ) ; for ( unsigned i = CSI . size ( ) ; i != 0 ; -- i ) { unsigned Reg = CSI [ i - 1 ] . getReg ( ) ; MBB . addLiveIn ( Reg ) ; BuildMI ( MBB , MI , DL , TII . get ( J2 :: MOV32rmpush ) , J2 :: R15 ) . addReg ( Reg ) . addReg ( Reg , RegState :: Kill ) ; } return true ; } </s>

spillCalleeSavedRegisters - Issues instruction ( s ) to spill all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of store instructions via storeRegToStackSlot ( ) .


<s> bool OR1KAsmPrinter :: PrintAsmOperand ( const MachineInstr * MI , unsigned OpNo , unsigned AsmVariant , const char * ExtraCode , raw_ostream & O ) { if ( ExtraCode && ExtraCode [ 0 ] ) { if ( ExtraCode [ 1 ] ) return true ; switch ( ExtraCode [ 0 ] ) { default : return true ; case 'H' : if ( OpNo == 0 ) return true ; const MachineOperand & FlagsOP = MI -> getOperand ( OpNo - 1 ) ; if ( ! FlagsOP . isImm ( ) ) return true ; unsigned Flags = FlagsOP . getImm ( ) ; unsigned NumVals = InlineAsm :: getNumOperandRegisters ( Flags ) ; if ( NumVals != 2 ) return true ; unsigned RegOp = OpNo + 1 ; if ( RegOp >= MI -> getNumOperands ( ) ) return true ; const MachineOperand & MO = MI -> getOperand ( RegOp ) ; if ( ! MO . isReg ( ) ) return true ; unsigned Reg = MO . getReg ( ) ; O << OR1KInstPrinter :: getRegisterName ( Reg ) ; return false ; } } printOperand ( MI , OpNo , O ) ; return false ; } </s>

PrintAsmOperand - Print out an operand for an inline asm expression .


<s> unsigned getMaxInlineSizeThreshold ( ) const { return 64 ; } </s>

Returns the maximum memset / memcpy size that still makes it profitable to inline the call .


<s> bool LEGPassConfig :: addInstSelector ( ) { addPass ( createLEGISelDag ( getLEGTargetMachine ( ) , getOptLevel ( ) ) ) ; return false ; } </s>

addInstSelector - This method should install an instruction selector pass , which converts from LLVM code to machine instructions .


<s> LoadInst * X86TargetLowering :: lowerIdempotentRMWIntoFencedLoad ( AtomicRMWInst * AI ) const { unsigned NativeWidth = Subtarget . is64Bit ( ) ? 64 : 32 ; Type * MemType = AI -> getType ( ) ; if ( MemType -> getPrimitiveSizeInBits ( ) > NativeWidth ) return nullptr ; if ( auto * C = dyn_cast < ConstantInt > ( AI -> getValOperand ( ) ) ) if ( AI -> getOperation ( ) == AtomicRMWInst :: Or && C -> isZero ( ) && AI -> use_empty ( ) ) return nullptr ; IRBuilder < > Builder ( AI ) ; Module * M = Builder . GetInsertBlock ( ) -> getParent ( ) -> getParent ( ) ; auto SSID = AI -> getSyncScopeID ( ) ; auto Order = AtomicCmpXchgInst :: getStrongestFailureOrdering ( AI -> getOrdering ( ) ) ; if ( SSID == SyncScope :: SingleThread ) return nullptr ; if ( ! Subtarget . hasMFence ( ) ) return nullptr ; Function * MFence = llvm :: Intrinsic :: getDeclaration ( M , Intrinsic :: x86_sse2_mfence ) ; Builder . CreateCall ( MFence , { } ) ; LoadInst * Loaded = Builder . CreateAlignedLoad ( AI -> getType ( ) , AI -> getPointerOperand ( ) , Align ( AI -> getType ( ) -> getPrimitiveSizeInBits ( ) ) ) ; Loaded -> setAtomic ( Order , SSID ) ; AI -> replaceAllUsesWith ( Loaded ) ; AI -> eraseFromParent ( ) ; return Loaded ; } </s>

On some platforms , an AtomicRMW that never actually modifies the value ( such as fetch_add of 0 ) can be turned into a fence followed by an atomic load .


<s> void Z80AsmBackend :: applyFixup ( const MCAssembler & Asm , const MCFixup & Fixup , const MCValue & Target , MutableArrayRef < char > Data , uint64_t Value , bool IsResolved ) const { llvm_unreachable ( "Unimplemented" ) ; } </s>

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


<s>
bool
SIInstrInfo
::
shouldClusterMemOps
(
ArrayRef
<
const
MachineOperand
*
>
BaseOps1
,
ArrayRef
<
const
MachineOperand
*
>
BaseOps2
,
unsigned
NumLoads
,
unsigned
NumBytes
)
const
{
assert
(
!
BaseOps1
.
empty
(
)
&&
!
BaseOps2
.
empty
(
)
)
;
const
MachineInstr
&
FirstLdSt
=
*
BaseOps1
.
front
(
)
->
getParent
(
)
;
const
MachineInstr
&
SecondLdSt
=
*
BaseOps2
.
front
(
)
->
getParent
(
)
;
if
(
!
memOpsHaveSameBasePtr
(
FirstLdSt
,
BaseOps1
,
SecondLdSt
,
BaseOps2
)
)
return
false
;
assert
(
(
NumLoads
>
0
)
&&
(
NumBytes
>
0
)
&&
(
NumBytes
>=
NumLoads
)
&&
"Invalid NumLoads/NumBytes values"
)
;
unsigned
MaxNumLoads
;
if
(
NumBytes
<=
4
*
NumLoads
)
{
MaxNumLoads
=
5
;
}
else
{
MaxNumLoads
=
4
;
}
return
NumLoads
<=
MaxNumLoads
;
}
</s>

Returns true if the two given memory operations should be scheduled adjacent .


<s> TargetLowering :: AtomicExpansionKind ARMTargetLowering :: shouldExpandAtomicRMWInIR ( AtomicRMWInst * AI ) const { unsigned Size = AI -> getType ( ) -> getPrimitiveSizeInBits ( ) ; bool hasAtomicRMW = ! Subtarget -> isThumb ( ) || Subtarget -> hasV8MBaselineOps ( ) ; return ( Size <= ( Subtarget -> isMClass ( ) ? 32U : 64U ) && hasAtomicRMW ) ? AtomicExpansionKind :: LLSC : AtomicExpansionKind :: None ; } </s>

Returns how the IR-level AtomicExpand pass should expand the given AtomicRMW , if at all .


"unimplemented opcode in encodeInstruction()"

Encode the given Inst to bytes and append to CB .


<s>
void
AArch64InstrInfo
::
loadRegFromStackSlot
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
MBBI
,
unsigned
DestReg
,
int
FrameIdx
,
const
TargetRegisterClass
*
RC
,
const
TargetRegisterInfo
*
TRI
)
const
{
DebugLoc
DL
=
MBB
.
findDebugLoc
(
MBBI
)
;
MachineFunction
&
MF
=
*
MBB
.
getParent
(
)
;
MachineFrameInfo
&
MFI
=
*
MF
.
getFrameInfo
(
)
;
unsigned
Align
=
MFI
.
getObjectAlignment
(
FrameIdx
)
;
MachineMemOperand
*
MMO
=
MF
.
getMachineMemOperand
(
MachinePointerInfo
::
getFixedStack
(
FrameIdx
)
,
MachineMemOperand
::
MOLoad
,
MFI
.
getObjectSize
(
FrameIdx
)
,
Align
)
;
unsigned
LoadOp
=
0
;
if
(
RC
->
hasType
(
MVT
::
i64
)
||
RC
->
hasType
(
MVT
::
i32
)
)
{
switch
(
RC
->
getSize
(
)
)
{
case
4
:
LoadOp
=
AArch64
::
LS32_LDR
;
break
;
case
8
:
LoadOp
=
AArch64
::
LS64_LDR
;
break
;
default
:
llvm_unreachable
(
"Unknown size for regclass"
)
;
}
}
else
if
(
AArch64
::
FPR8RegClass
.
hasSubClassEq
(
RC
)
)
{
LoadOp
=
AArch64
::
LSFP8_LDR
;
}
else
if
(
AArch64
::
FPR16RegClass
.
hasSubClassEq
(
RC
)
)
{
LoadOp
=
AArch64
::
LSFP16_LDR
;
}
else
if
(
RC
->
hasType
(
MVT
::
f32
)
||
RC
->
hasType
(
MVT
::
f64
)
||
RC
->
hasType
(
MVT
::
f128
)
)
{
switch
(
RC
->
getSize
(
)
)
{
case
4
:
LoadOp
=
AArch64
::
LSFP32_LDR
;
break
;
case
8
:
LoadOp
=
AArch64
::
LSFP64_LDR
;
break
;
case
16
:
LoadOp
=
AArch64
::
LSFP128_LDR
;
break
;
default
:
llvm_unreachable
(
"Unknown size for regclass"
)
;
}
}
else
{
if
(
AArch64
::
DPairRegClass
.
hasSubClassEq
(
RC
)
)
LoadOp
=
AArch64
::
LD1x2_8B
;
else
if
(
AArch64
::
DTripleRegClass
.
hasSubClassEq
(
RC
)
)
LoadOp
=
AArch64
::
LD1x3_8B
;
else
if
(
AArch64
::
DQuadRegClass
.
hasSubClassEq
(
RC
)
)
LoadOp
=
AArch64
::
LD1x4_8B
;
else
if
(
AArch64
::
QPairRegClass
.
hasSubClassEq
(
RC
)
)
LoadOp
=
AArch64
::
LD1x2_16B
;
else
if
(
AArch64
::
QTripleRegClass
.
hasSubClassEq
(
RC
)
)
LoadOp
=
AArch64
::
LD1x3_16B
;
else
if
(
AArch64
::
QQuadRegClass
.
hasSubClassEq
(
RC
)
)
LoadOp
=
AArch64
::
LD1x4_16B
;
else
llvm_unreachable
(
"Unknown reg class"
)
;
MachineInstrBuilder
NewMI
=
BuildMI
(
MBB
,
MBBI
,
DL
,
get
(
LoadOp
)
,
DestReg
)
;
NewMI
.
addFrameIndex
(
FrameIdx
)
.
addMemOperand
(
MMO
)
;
return
;
}
MachineInstrBuilder
NewMI
=
BuildMI
(
MBB
,
MBBI
,
DL
,
get
(
LoadOp
)
,
DestReg
)
;
NewMI
.
addFrameIndex
(
FrameIdx
)
.
addImm
(
0
)
.
addMemOperand
(
MMO
)
;
}
</s>

Load the specified register of the given register class from the specified stack frame index .


<s> bool ix86_force_load_from_GOT_p ( rtx x ) { return ( ( TARGET_64BIT || HAVE_AS_IX86_GOT32X ) && ! TARGET_PECOFF && ! TARGET_MACHO && ! flag_plt && ! flag_pic && ix86_cmodel != CM_LARGE && GET_CODE ( x ) == SYMBOL_REF && SYMBOL_REF_FUNCTION_P ( x ) && ! SYMBOL_REF_LOCAL_P ( x ) ) ; } </s>

True if the function symbol operand X should be loaded from GOT . NB : In 32-bit mode , only non-PIC is allowed in inline assembly statements , since a PIC register could not be available at the call site .


<s> static rtx riscv_force_binary ( machine_mode mode , enum rtx_code code , rtx x , rtx y ) { return riscv_emit_binary ( code , gen_reg_rtx ( mode ) , x , y ) ; } </s>

Compute ( CODE X Y ) and store the result in a new register of mode MODE . Return that new register .


<s> static void aarch64_override_options_after_change ( void ) { if ( flag_omit_frame_pointer ) flag_omit_leaf_frame_pointer = false ; else if ( flag_omit_leaf_frame_pointer ) flag_omit_frame_pointer = true ; } </s>


<s>
const
MCPhysReg
*
RISCVRegisterInfo
::
getCalleeSavedRegs
(
const
MachineFunction
*
MF
)
const
{
auto
&
Subtarget
=
MF
->
getSubtarget
<
RISCVSubtarget
>
(
)
;
if
(
MF
->
getFunction
(
)
.
hasFnAttribute
(
"interrupt"
)
)
{
if
(
Subtarget
.
hasStdExtD
(
)
)
return
CSR_XLEN_F64_Interrupt_SaveList
;
if
(
Subtarget
.
hasStdExtF
(
)
)
return
CSR_XLEN_F32_Interrupt_SaveList
;
return
CSR_Interrupt_SaveList
;
if
(
Subtarget
.
hasStdExtV
(
)
)
return
CSR_XLEN_F32_VEC_Interrupt_SaveList
;
return
CSR_Interrupt_SaveList
;
}
if
(
MF
->
getSubtarget
<
RISCVSubtarget
>
(
)
.
hasStdExtV
(
)
)
return
CSR_ILP32F_LP64F_VEC_SaveList
;
switch
(
Subtarget
.
getTargetABI
(
)
)
{
default
:
llvm_unreachable
(
"Unrecognized ABI"
)
;
case
RISCVABI
::
ABI_ILP32
:
case
RISCVABI
::
ABI_LP64
:
return
CSR_ILP32_LP64_SaveList
;
case
RISCVABI
::
ABI_ILP32F
:
case
RISCVABI
::
ABI_LP64F
:
return
CSR_ILP32F_LP64F_SaveList
;
case
RISCVABI
::
ABI_ILP32D
:
case
RISCVABI
::
ABI_LP64D
:
return
CSR_ILP32D_LP64D_SaveList
;
}
}
</s>


<s> bool SIInstrInfo :: isIgnorableUse ( const MachineOperand & MO ) const { return MO . getReg ( ) == AMDGPU :: EXEC && MO . isImplicit ( ) && isVALU ( * MO . getParent ( ) ) && ! readsExecAsData ( * MO . getParent ( ) ) ; } </s>

Given MO is a PhysReg use return if it can be ignored for the purpose of instruction rematerialization or sinking .


<s> static rtx s390_find_constant ( struct constant_pool * pool , rtx val , machine_mode mode ) { struct constant * c ; size_t i ; for ( i = 0 ; i < NR_C_MODES ; i ++ ) if ( constant_modes [ i ] == mode ) break ; gcc_assert ( i != NR_C_MODES ) ; for ( c = pool -> constants [ i ] ; c != NULL ; c = c -> next ) if ( rtx_equal_p ( val , c -> value ) ) break ; gcc_assert ( c ) ; return s390_pool_offset ( pool , gen_rtx_LABEL_REF ( Pmode , c -> label ) ) ; } </s>

Find constant VAL of mode MODE in the constant pool POOL . Return an RTX describing the distance from the start of the pool to the location of the new constant .


<s> void AVRAsmPrinter :: emitStartOfAsmFile ( Module & M ) { const AVRTargetMachine & TM = ( const AVRTargetMachine & ) MMI -> getTarget ( ) ; const AVRSubtarget * SubTM = ( const AVRSubtarget * ) TM . getSubtargetImpl ( ) ; if ( ! SubTM ) return ; OutStreamer -> emitAssignment ( MMI -> getContext ( ) . getOrCreateSymbol ( StringRef ( "__tmp_reg__" ) ) , MCConstantExpr :: create ( SubTM -> getRegTmpIndex ( ) , MMI -> getContext ( ) ) ) ; OutStreamer -> emitAssignment ( MMI -> getContext ( ) . getOrCreateSymbol ( StringRef ( "__zero_reg__" ) ) , MCConstantExpr :: create ( SubTM -> getRegZeroIndex ( ) , MMI -> getContext ( ) ) ) ; OutStreamer -> emitAssignment ( MMI -> getContext ( ) . getOrCreateSymbol ( StringRef ( "__SREG__" ) ) , MCConstantExpr :: create ( SubTM -> getIORegSREG ( ) , MMI -> getContext ( ) ) ) ; if ( ! SubTM -> hasSmallStack ( ) ) OutStreamer -> emitAssignment ( MMI -> getContext ( ) . getOrCreateSymbol ( StringRef ( "__SP_H__" ) ) , MCConstantExpr :: create ( SubTM -> getIORegSPH ( ) , MMI -> getContext ( ) ) ) ; OutStreamer -> emitAssignment ( MMI -> getContext ( ) . getOrCreateSymbol ( StringRef ( "__SP_L__" ) ) , MCConstantExpr :: create ( SubTM -> getIORegSPL ( ) , MMI -> getContext ( ) ) ) ; if ( SubTM -> hasEIJMPCALL ( ) ) OutStreamer -> emitAssignment ( MMI -> getContext ( ) . getOrCreateSymbol ( StringRef ( "__EIND__" ) ) , MCConstantExpr :: create ( SubTM -> getIORegEIND ( ) , MMI -> getContext ( ) ) ) ; if ( SubTM -> hasELPM ( ) ) OutStreamer -> emitAssignment ( MMI -> getContext ( ) . getOrCreateSymbol ( StringRef ( "__RAMPZ__" ) ) , MCConstantExpr :: create ( SubTM -> getIORegRAMPZ ( ) , MMI -> getContext ( ) ) ) ; } </s>

This virtual method can be overridden by targets that want to emit something at the start of their file .


<s> void WebAssemblyAsmPrinter :: emitFunctionBodyStart ( ) { const Function & F = MF -> getFunction ( ) ; SmallVector < MVT , 1 > ResultVTs ; SmallVector < MVT , 4 > ParamVTs ; computeSignatureVTs ( F . getFunctionType ( ) , F , TM , ParamVTs , ResultVTs ) ; auto Signature = signatureFromMVTs ( ResultVTs , ParamVTs ) ; auto * WasmSym = cast < MCSymbolWasm > ( CurrentFnSym ) ; WasmSym -> setSignature ( Signature . get ( ) ) ; addSignature ( std :: move ( Signature ) ) ; WasmSym -> setType ( wasm :: WASM_SYMBOL_TYPE_FUNCTION ) ; getTargetStreamer ( ) -> emitFunctionType ( WasmSym ) ; if ( MDNode * Idx = F . getMetadata ( "wasm.index" ) ) { assert ( Idx -> getNumOperands ( ) == 1 ) ; getTargetStreamer ( ) -> emitIndIdx ( AsmPrinter :: lowerConstant ( cast < ConstantAsMetadata > ( Idx -> getOperand ( 0 ) ) -> getValue ( ) ) ) ; } SmallVector < wasm :: ValType , 16 > Locals ; valTypesFromMVTs ( MFI -> getLocals ( ) , Locals ) ; getTargetStreamer ( ) -> emitLocal ( Locals ) ; AsmPrinter :: emitFunctionBodyStart ( ) ; } </s>

Targets can override this to emit stuff before the first basic block in the function .


<s> bool MipsLongBranch :: runOnMachineFunction ( MachineFunction & F ) { const MipsInstrInfo * TII = static_cast < const MipsInstrInfo * > ( TM . getSubtargetImpl ( ) -> getInstrInfo ( ) ) ; const MipsSubtarget & STI = TM . getSubtarget < MipsSubtarget > ( ) ; if ( STI . inMips16Mode ( ) || ! STI . enableLongBranchPass ( ) ) return false ; if ( ( TM . getRelocationModel ( ) == Reloc :: PIC_ ) && TM . getSubtarget < MipsSubtarget > ( ) . isABI_O32 ( ) && F . getInfo < MipsFunctionInfo > ( ) -> globalBaseRegSet ( ) ) emitGPDisp ( F , TII ) ; if ( SkipLongBranch ) return true ; MF = & F ; initMBBInfo ( ) ; SmallVectorImpl < MBBInfo > :: iterator I , E = MBBInfos . end ( ) ; bool EverMadeChange = false , MadeChange = true ; while ( MadeChange ) { MadeChange = false ; for ( I = MBBInfos . begin ( ) ; I != E ; ++ I ) { if ( ! I -> Br || I -> HasLongBranch ) continue ; int ShVal = TM . getSubtarget < MipsSubtarget > ( ) . inMicroMipsMode ( ) ? 2 : 4 ; int64_t Offset = computeOffset ( I -> Br ) / ShVal ; if ( TM . getSubtarget < MipsSubtarget > ( ) . isTargetNaCl ( ) ) { Offset *= 2 ; } if ( ! ForceLongBranch && isInt < 14 > ( Offset ) ) continue ; I -> HasLongBranch = true ; I -> Size += LongBranchSeqSize * 4 ; ++ LongBranches ; EverMadeChange = MadeChange = true ; } } if ( ! EverMadeChange ) return true ; if ( TM . getRelocationModel ( ) == Reloc :: PIC_ ) { uint64_t Address = 0 ; for ( I = MBBInfos . begin ( ) ; I != E ; Address += I -> Size , ++ I ) I -> Address = Address ; } for ( I = MBBInfos . begin ( ) ; I != E ; ++ I ) if ( I -> HasLongBranch ) expandToLongBranch ( * I ) ; MF -> RenumberBlocks ( ) ; return true ; } </s>

runOnMachineFunction - Emit the function body .

Mips Mips Mips Mips Mips Mips Mips Mips Mips Mips Mips 2 4 Mips 2 14 4 0


<s> const RegisterBankInfo :: InstructionMapping & MipsRegisterBankInfo :: getInstrMapping ( const MachineInstr & MI ) const { unsigned Opc = MI . getOpcode ( ) ; const RegisterBankInfo :: InstructionMapping & Mapping = getInstrMappingImpl ( MI ) ; if ( Mapping . isValid ( ) ) return Mapping ; using namespace TargetOpcode ; unsigned NumOperands = MI . getNumOperands ( ) ; const ValueMapping * OperandsMapping = & Mips :: ValueMappings [ Mips :: GPRIdx ] ; switch ( Opc ) { case G_TRUNC : case G_ADD : case G_SUB : case G_LOAD : case G_STORE : case G_ZEXTLOAD : case G_SEXTLOAD : case G_GEP : case G_AND : case G_OR : case G_XOR : case G_SHL : case G_ASHR : case G_LSHR : case G_SDIV : case G_UDIV : case G_SREM : case G_UREM : OperandsMapping = & Mips :: ValueMappings [ Mips :: GPRIdx ] ; break ; case G_CONSTANT : case G_FRAME_INDEX : case G_GLOBAL_VALUE : OperandsMapping = getOperandsMapping ( { & Mips :: ValueMappings [ Mips :: GPRIdx ] , nullptr } ) ; break ; case G_ICMP : OperandsMapping = getOperandsMapping ( { & Mips :: ValueMappings [ Mips :: GPRIdx ] , nullptr , & Mips :: ValueMappings [ Mips :: GPRIdx ] , & Mips :: ValueMappings [ Mips :: GPRIdx ] } ) ; break ; case G_SELECT : OperandsMapping = getOperandsMapping ( { & Mips :: ValueMappings [ Mips :: GPRIdx ] , & Mips :: ValueMappings [ Mips :: GPRIdx ] , & Mips :: ValueMappings [ Mips :: GPRIdx ] , & Mips :: ValueMappings [ Mips :: GPRIdx ] } ) ; break ; default : return getInvalidInstructionMapping ( ) ; } return getInstructionMapping ( DefaultMappingID , 1 , OperandsMapping , NumOperands ) ; } </s>

Get the mapping of the different operands of MI on the register bank .

Mips Mips Mips::ValueMappings Mips::GPRIdx Mips::ValueMappings Mips::GPRIdx Mips::ValueMappings Mips::GPRIdx Mips::ValueMappings Mips::GPRIdx Mips::ValueMappings Mips::GPRIdx Mips::ValueMappings Mips::GPRIdx Mips::ValueMappings Mips::GPRIdx Mips::ValueMappings Mips::GPRIdx Mips::ValueMappings Mips::GPRIdx Mips::ValueMappings Mips::GPRIdx 1


<s> static bool expand_vec_perm_pshufb2 ( struct expand_vec_perm_d * d ) { rtx rperm [ 2 ] [ 16 ] , vperm , l , h , op , m128 ; unsigned int i , nelt , eltsz ; machine_mode mode ; rtx ( * gen ) ( rtx , rtx , rtx ) ; if ( ! TARGET_SSSE3 || ( GET_MODE_SIZE ( d -> vmode ) != 16 && GET_MODE_SIZE ( d -> vmode ) != 8 && GET_MODE_SIZE ( d -> vmode ) != 4 ) ) return false ; gcc_assert ( ! d -> one_operand_p ) ; if ( d -> testing_p ) return true ; switch ( GET_MODE_SIZE ( d -> vmode ) ) { case 4 : mode = V4QImode ; gen = gen_mmx_pshufbv4qi3 ; break ; case 8 : mode = V8QImode ; gen = gen_mmx_pshufbv8qi3 ; break ; case 16 : mode = V16QImode ; gen = gen_ssse3_pshufbv16qi3 ; break ; default : gcc_unreachable ( ) ; } nelt = d -> nelt ; eltsz = GET_MODE_UNIT_SIZE ( d -> vmode ) ; m128 = GEN_INT ( - 128 ) ; for ( i = 0 ; i < nelt ; ++ i ) { unsigned j , k , e = d -> perm [ i ] ; unsigned which = ( e >= nelt ) ; if ( e >= nelt ) e -= nelt ; for ( j = 0 ; j < eltsz ; ++ j ) { rperm [ which ] [ i * eltsz + j ] = GEN_INT ( e * eltsz + j ) ; rperm [ 1 - which ] [ i * eltsz + j ] = m128 ; } for ( k = i * eltsz + j ; k < 16 ; ++ k ) rperm [ 0 ] [ k ] = rperm [ 1 ] [ k ] = m128 ; } vperm = gen_rtx_CONST_VECTOR ( V16QImode , gen_rtvec_v ( 16 , rperm [ 0 ] ) ) ; vperm = force_reg ( V16QImode , vperm ) ; l = gen_reg_rtx ( mode ) ; op = gen_lowpart ( mode , d -> op0 ) ; emit_insn ( gen ( l , op , vperm ) ) ; vperm = gen_rtx_CONST_VECTOR ( V16QImode , gen_rtvec_v ( 16 , rperm [ 1 ] ) ) ; vperm = force_reg ( V16QImode , vperm ) ; h = gen_reg_rtx ( mode ) ; op = gen_lowpart ( mode , d -> op1 ) ; emit_insn ( gen ( h , op , vperm ) ) ; op = d -> target ; if ( d -> vmode != mode ) op = gen_reg_rtx ( mode ) ; ix86_emit_vec_binop ( IOR , mode , op , l , h ) ; if ( op != d -> target ) emit_move_insn ( d -> target , gen_lowpart ( d -> vmode , op ) ) ; return true ; } </s>

A subroutine of expand_vec_perm_even_odd_1 . Implement the double-word permutation with two pshufb insns and an ior . We should have already failed all two instruction sequences .


<s> bool shouldForceRelocation ( const MCAssembler & Asm , const MCFixup & Fixup , const MCValue & Target ) override { return STI . getFeatureBits ( ) [ RISCV :: FeatureRelax ] || ForceRelocs ; } </s>

Hook to check if a relocation is needed for some target specific reason .


<s> static bool c4x_handle_option ( size_t code , const char * arg , int value ) { switch ( code ) { case OPT_m30 : c4x_cpu_version = 30 ; return true ; case OPT_m31 : c4x_cpu_version = 31 ; return true ; case OPT_m32 : c4x_cpu_version = 32 ; return true ; case OPT_m33 : c4x_cpu_version = 33 ; return true ; case OPT_m40 : c4x_cpu_version = 40 ; return true ; case OPT_m44 : c4x_cpu_version = 44 ; return true ; case OPT_mcpu_ : if ( arg [ 0 ] == 'c' || arg [ 0 ] == 'C' ) arg ++ ; value = atoi ( arg ) ; switch ( value ) { case 30 : case 31 : case 32 : case 33 : case 40 : case 44 : c4x_cpu_version = value ; return true ; } return false ; default : return true ; } } </s>


<s> const int * SIRegisterInfo :: getRegUnitPressureSets ( unsigned RegUnit ) const { static const int Empty [ ] = { - 1 } ; if ( RegPressureIgnoredUnits [ RegUnit ] ) return Empty ; return AMDGPUGenRegisterInfo :: getRegUnitPressureSets ( RegUnit ) ; } </s>

Get the dimensions of register pressure impacted by this register unit .


<s> void RISCVTargetLowering :: LowerAsmOperandForConstraint ( SDValue Op , std :: string & Constraint , std :: vector < SDValue > & Ops , SelectionDAG & DAG ) const { if ( Constraint . length ( ) == 1 ) { switch ( Constraint [ 0 ] ) { case 'I' : if ( auto * C = dyn_cast < ConstantSDNode > ( Op ) ) { uint64_t CVal = C -> getSExtValue ( ) ; if ( isInt < 12 > ( CVal ) ) Ops . push_back ( DAG . getTargetConstant ( CVal , SDLoc ( Op ) , Subtarget . getXLenVT ( ) ) ) ; } return ; case 'J' : if ( auto * C = dyn_cast < ConstantSDNode > ( Op ) ) if ( C -> getZExtValue ( ) == 0 ) Ops . push_back ( DAG . getTargetConstant ( 0 , SDLoc ( Op ) , Subtarget . getXLenVT ( ) ) ) ; return ; case 'K' : if ( auto * C = dyn_cast < ConstantSDNode > ( Op ) ) { uint64_t CVal = C -> getZExtValue ( ) ; if ( isUInt < 5 > ( CVal ) ) Ops . push_back ( DAG . getTargetConstant ( CVal , SDLoc ( Op ) , Subtarget . getXLenVT ( ) ) ) ; } return ; default : break ; } } TargetLowering :: LowerAsmOperandForConstraint ( Op , Constraint , Ops , DAG ) ; } </s>

Lower the specified operand into the Ops vector .


<s> bool PPCTargetLowering :: getPreIndexedAddressParts ( SDNode * N , SDValue & Base , SDValue & Offset , ISD :: MemIndexedMode & AM , SelectionDAG & DAG ) const { if ( DisablePPCPreinc ) return false ; bool isLoad = true ; SDValue Ptr ; EVT VT ; unsigned Alignment ; if ( LoadSDNode * LD = dyn_cast < LoadSDNode > ( N ) ) { Ptr = LD -> getBasePtr ( ) ; VT = LD -> getMemoryVT ( ) ; Alignment = LD -> getAlignment ( ) ; } else if ( StoreSDNode * ST = dyn_cast < StoreSDNode > ( N ) ) { Ptr = ST -> getBasePtr ( ) ; VT = ST -> getMemoryVT ( ) ; Alignment = ST -> getAlignment ( ) ; isLoad = false ; } else return false ; if ( isLoad && usePartialVectorLoads ( N , Subtarget ) ) { return false ; } if ( VT . isVector ( ) ) return false ; if ( SelectAddressRegReg ( Ptr , Base , Offset , DAG ) ) { bool Swap = false ; if ( isa < FrameIndexSDNode > ( Base ) || isa < RegisterSDNode > ( Base ) ) Swap = true ; else if ( ! isLoad ) { SDValue Val = cast < StoreSDNode > ( N ) -> getValue ( ) ; if ( Val == Base || Base . getNode ( ) -> isPredecessorOf ( Val . getNode ( ) ) ) Swap = true ; } if ( Swap ) std :: swap ( Base , Offset ) ; AM = ISD :: PRE_INC ; return true ; } if ( VT != MVT :: i64 ) { if ( ! SelectAddressRegImm ( Ptr , Offset , Base , DAG , None ) ) return false ; } else { if ( Alignment < 4 ) return false ; if ( ! SelectAddressRegImm ( Ptr , Offset , Base , DAG , Align ( 4 ) ) ) return false ; } if ( LoadSDNode * LD = dyn_cast < LoadSDNode > ( N ) ) { if ( LD -> getValueType ( 0 ) == MVT :: i64 && LD -> getMemoryVT ( ) == MVT :: i32 && LD -> getExtensionType ( ) == ISD :: SEXTLOAD && isa < ConstantSDNode > ( Offset ) ) return false ; } AM = ISD :: PRE_INC ; return true ; } </s>

Returns true by value , base pointer and offset pointer and addressing mode by reference if the node 's address can be legally represented as pre-indexed load / store address .


<s> InstructionCost ARMTTIImpl :: getIntrinsicInstrCost ( const IntrinsicCostAttributes & ICA , TTI :: TargetCostKind CostKind ) { switch ( ICA . getID ( ) ) { case Intrinsic :: get_active_lane_mask : if ( ST -> hasMVEIntegerOps ( ) ) return 0 ; break ; case Intrinsic :: sadd_sat : case Intrinsic :: ssub_sat : case Intrinsic :: uadd_sat : case Intrinsic :: usub_sat : { if ( ! ST -> hasMVEIntegerOps ( ) ) break ; Type * VT = ICA . getReturnType ( ) ; std :: pair < InstructionCost , MVT > LT = TLI -> getTypeLegalizationCost ( DL , VT ) ; if ( LT . second == MVT :: v4i32 || LT . second == MVT :: v8i16 || LT . second == MVT :: v16i8 ) { unsigned Instrs = LT . second . getScalarSizeInBits ( ) == VT -> getScalarSizeInBits ( ) ? 1 : 4 ; return LT . first * ST -> getMVEVectorCostFactor ( CostKind ) * Instrs ; } break ; } case Intrinsic :: abs : case Intrinsic :: smin : case Intrinsic :: smax : case Intrinsic :: umin : case Intrinsic :: umax : { if ( ! ST -> hasMVEIntegerOps ( ) ) break ; Type * VT = ICA . getReturnType ( ) ; std :: pair < InstructionCost , MVT > LT = TLI -> getTypeLegalizationCost ( DL , VT ) ; if ( LT . second == MVT :: v4i32 || LT . second == MVT :: v8i16 || LT . second == MVT :: v16i8 ) return LT . first * ST -> getMVEVectorCostFactor ( CostKind ) ; break ; } case Intrinsic :: minnum : case Intrinsic :: maxnum : { if ( ! ST -> hasMVEFloatOps ( ) ) break ; Type * VT = ICA . getReturnType ( ) ; std :: pair < InstructionCost , MVT > LT = TLI -> getTypeLegalizationCost ( DL , VT ) ; if ( LT . second == MVT :: v4f32 || LT . second == MVT :: v8f16 ) return LT . first * ST -> getMVEVectorCostFactor ( CostKind ) ; break ; } } return BaseT :: getIntrinsicInstrCost ( ICA , CostKind ) ; } </s>


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . addRequired < LoopInfo > ( ) ; AU . addPreserved < LoopInfo > ( ) ; AU . addRequired < DominatorTreeWrapperPass > ( ) ; AU . addPreserved < DominatorTreeWrapperPass > ( ) ; AU . addRequired < ScalarEvolution > ( ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> static void setup_incoming_varargs ( CUMULATIVE_ARGS * cum , enum machine_mode mode ATTRIBUTE_UNUSED , tree type ATTRIBUTE_UNUSED , int * pretend_size , int no_rtl ) { rtx mem ; int i ; if ( no_rtl ) return ; for ( i = cum -> words + 1 ; i < max_arg_registers ; i ++ ) { mem = gen_rtx_MEM ( Pmode , plus_constant ( arg_pointer_rtx , ( i * UNITS_PER_WORD ) ) ) ; emit_move_insn ( mem , gen_rtx_REG ( Pmode , i ) ) ; } * pretend_size = 0 ; } </s>

Perform any needed actions needed for a function that is receiving a variable number of arguments . CUM is as above . MODE and TYPE are the mode and type of the current parameter . PRETEND_SIZE is a variable that should be set to the amount of stack that must be pushed by the prolog to pretend that our caller pushed it . Normally , this macro will push all remaining incoming registers on the stack and set PRETEND_SIZE to the length of the registers pushed .


<s> const DataLayout * getDataLayout ( ) const override { return & DL ; } </s>

Return the DataLayout associated with the module this SCEV instance is operating on .


<s>
static
void
complete_vector_type
(
typeinfo
*
typeptr
,
char
*
buf
,
int
*
bufi
)
{
if
(
typeptr
->
isbool
)
buf
[
(
*
bufi
)
++
]
=
'b'
;
buf
[
(
*
bufi
)
++
]
=
'v'
;
if
(
typeptr
->
ispixel
)
{
memcpy
(
&
buf
[
*
bufi
]
,
"p8hi"
,
4
)
;
*
bufi
+=
4
;
return
;
}
switch
(
typeptr
->
base
)
{
case
BT_CHAR
:
memcpy
(
&
buf
[
*
bufi
]
,
"16qi"
,
4
)
;
*
bufi
+=
4
;
break
;
case
BT_SHORT
:
memcpy
(
&
buf
[
*
bufi
]
,
"8hi"
,
3
)
;
*
bufi
+=
3
;
break
;
case
BT_INT
:
memcpy
(
&
buf
[
*
bufi
]
,
"4si"
,
3
)
;
*
bufi
+=
3
;
break
;
case
BT_LONGLONG
:
memcpy
(
&
buf
[
*
bufi
]
,
"2di"
,
3
)
;
*
bufi
+=
3
;
break
;
case
BT_FLOAT
:
memcpy
(
&
buf
[
*
bufi
]
,
"4sf"
,
3
)
;
*
bufi
+=
3
;
break
;
case
BT_DOUBLE
:
memcpy
(
&
buf
[
*
bufi
]
,
"2df"
,
3
)
;
*
bufi
+=
3
;
break
;
case
BT_INT128
:
memcpy
(
&
buf
[
*
bufi
]
,
"1ti"
,
3
)
;
*
bufi
+=
3
;
break
;
case
BT_FLOAT128
:
memcpy
(
&
buf
[
*
bufi
]
,
"1tf"
,
3
)
;
*
bufi
+=
3
;
break
;
case
BT_VPAIR
:
memcpy
(
&
buf
[
*
bufi
]
,
"1poi"
,
4
)
;
*
bufi
+=
4
;
break
;
case
BT_VQUAD
:
memcpy
(
&
buf
[
*
bufi
]
,
"1pxi"
,
4
)
;
*
bufi
+=
4
;
break
;
default
:
diag
(
pos
,
"unhandled basetype %d.\n"
,
typeptr
->
base
)
;
exit
(
1
)
;
}
}
</s>

Convert a vector type into a mode string .


<s> bool ARMPassConfig :: addPreISel ( ) { if ( ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableGlobalMerge == cl :: BOU_UNSET ) || EnableGlobalMerge == cl :: BOU_TRUE ) { bool OnlyOptimizeForSize = ( TM -> getOptLevel ( ) < CodeGenOpt :: Aggressive ) && ( EnableGlobalMerge == cl :: BOU_UNSET ) ; bool MergeExternalByDefault = ! TM -> getTargetTriple ( ) . isOSBinFormatMachO ( ) ; addPass ( createGlobalMergePass ( TM , 127 , OnlyOptimizeForSize , MergeExternalByDefault ) ) ; } if ( TM -> getOptLevel ( ) != CodeGenOpt :: None ) { addPass ( createHardwareLoopsPass ( ) ) ; addPass ( createMVETailPredicationPass ( ) ) ; addPass ( createBarrierNoopPass ( ) ) ; } return false ; } </s>


<s> MachineInstrBuilder SIInstrInfo :: getAddNoCarry ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , const DebugLoc & DL , Register DestReg , RegScavenger & RS ) const { if ( ST . hasAddNoCarry ( ) ) return BuildMI ( MBB , I , DL , get ( AMDGPU :: V_ADD_U32_e32 ) , DestReg ) ; Register UnusedCarry = ! RS . isRegUsed ( AMDGPU :: VCC ) ? Register ( RI . getVCC ( ) ) : RS . scavengeRegister ( RI . getBoolRC ( ) , I , 0 , false ) ; if ( ! UnusedCarry . isValid ( ) ) return MachineInstrBuilder ( ) ; return BuildMI ( MBB , I , DL , get ( AMDGPU :: V_ADD_CO_U32_e64 ) , DestReg ) . addReg ( UnusedCarry , RegState :: Define | RegState :: Dead ) ; } </s>

Return a partially built integer add instruction without carry .


<s>
SDValue
AMDGPUTargetLowering
::
LowerOperation
(
SDValue
Op
,
SelectionDAG
&
DAG
)
const
{
switch
(
Op
.
getOpcode
(
)
)
{
default
:
Op
->
print
(
errs
(
)
,
&
DAG
)
;
llvm_unreachable
(
"Custom lowering code for this "
"instruction is not implemented yet!"
)
;
break
;
case
ISD
::
SIGN_EXTEND_INREG
:
return
LowerSIGN_EXTEND_INREG
(
Op
,
DAG
)
;
case
ISD
::
CONCAT_VECTORS
:
return
LowerCONCAT_VECTORS
(
Op
,
DAG
)
;
case
ISD
::
EXTRACT_SUBVECTOR
:
return
LowerEXTRACT_SUBVECTOR
(
Op
,
DAG
)
;
case
ISD
::
UDIVREM
:
return
LowerUDIVREM
(
Op
,
DAG
)
;
case
ISD
::
SDIVREM
:
return
LowerSDIVREM
(
Op
,
DAG
)
;
case
ISD
::
FREM
:
return
LowerFREM
(
Op
,
DAG
)
;
case
ISD
::
FCEIL
:
return
LowerFCEIL
(
Op
,
DAG
)
;
case
ISD
::
FTRUNC
:
return
LowerFTRUNC
(
Op
,
DAG
)
;
case
ISD
::
FRINT
:
return
LowerFRINT
(
Op
,
DAG
)
;
case
ISD
::
FNEARBYINT
:
return
LowerFNEARBYINT
(
Op
,
DAG
)
;
case
ISD
::
FROUND
:
return
LowerFROUND
(
Op
,
DAG
)
;
case
ISD
::
FFLOOR
:
return
LowerFFLOOR
(
Op
,
DAG
)
;
case
ISD
::
FLOG
:
return
LowerFLOG
(
Op
,
DAG
,
numbers
::
ln2f
)
;
case
ISD
::
FLOG10
:
return
LowerFLOG
(
Op
,
DAG
,
numbers
::
ln2f
/
numbers
::
ln10f
)
;
case
ISD
::
FEXP
:
return
lowerFEXP
(
Op
,
DAG
)
;
case
ISD
::
SINT_TO_FP
:
return
LowerSINT_TO_FP
(
Op
,
DAG
)
;
case
ISD
::
UINT_TO_FP
:
return
LowerUINT_TO_FP
(
Op
,
DAG
)
;
case
ISD
::
FP_TO_FP16
:
return
LowerFP_TO_FP16
(
Op
,
DAG
)
;
case
ISD
::
FP_TO_SINT
:
case
ISD
::
FP_TO_UINT
:
return
LowerFP_TO_INT
(
Op
,
DAG
)
;
case
ISD
::
CTTZ
:
case
ISD
::
CTTZ_ZERO_UNDEF
:
case
ISD
::
CTLZ
:
case
ISD
::
CTLZ_ZERO_UNDEF
:
return
LowerCTLZ_CTTZ
(
Op
,
DAG
)
;
case
ISD
::
DYNAMIC_STACKALLOC
:
return
LowerDYNAMIC_STACKALLOC
(
Op
,
DAG
)
;
}
return
Op
;
}
</s>

LowerOperation - Provide custom lowering hooks for some operations .


initializeSubtargetDependencies - Initializes using a CPU , a TuneCPU , and feature string so that we can use initializer lists for subtarget initialization .


<s> static unsigned int riscv_hard_regno_nregs ( unsigned int regno , machine_mode mode ) { if ( riscv_v_ext_vector_mode_p ( mode ) ) { if ( maybe_lt ( GET_MODE_SIZE ( mode ) , UNITS_PER_V_REG ) ) return 1 ; return exact_div ( GET_MODE_SIZE ( mode ) , UNITS_PER_V_REG ) . to_constant ( ) ; } if ( regno == VTYPE_REGNUM || regno == VL_REGNUM ) return 1 ; if ( V_REG_P ( regno ) ) return 1 ; if ( FP_REG_P ( regno ) ) return ( GET_MODE_SIZE ( mode ) . to_constant ( ) + UNITS_PER_FP_REG - 1 ) / UNITS_PER_FP_REG ; return ( GET_MODE_SIZE ( mode ) . to_constant ( ) + UNITS_PER_WORD - 1 ) / UNITS_PER_WORD ; } </s>


"After Machine LICM, CSE and Sinking passes"

"After codegen peephole optimization pass"

Methods with trivial inline returns are convenient points in the common codegen pass pipeline where targets may insert passes .


<s> static rtx c6x_expand_builtin ( tree exp , rtx target ATTRIBUTE_UNUSED , rtx subtarget ATTRIBUTE_UNUSED , machine_mode mode ATTRIBUTE_UNUSED , int ignore ATTRIBUTE_UNUSED ) { size_t i ; const struct builtin_description * d ; tree fndecl = TREE_OPERAND ( CALL_EXPR_FN ( exp ) , 0 ) ; unsigned int fcode = DECL_FUNCTION_CODE ( fndecl ) ; for ( i = 0 , d = bdesc_2arg ; i < ARRAY_SIZE ( bdesc_2arg ) ; i ++ , d ++ ) if ( d -> code == fcode ) return c6x_expand_binop_builtin ( d -> icode , exp , target , fcode == C6X_BUILTIN_CLRR ) ; for ( i = 0 , d = bdesc_1arg ; i < ARRAY_SIZE ( bdesc_1arg ) ; i ++ , d ++ ) if ( d -> code == fcode ) return c6x_expand_unop_builtin ( d -> icode , exp , target ) ; gcc_unreachable ( ) ; } </s>

Expand an expression EXP that calls a built-in function , with result going to TARGET if that 's convenient ( and in mode MODE if that 's convenient ) . SUBTARGET may be used as the target for computing one of EXP 's operands . IGNORE is nonzero if the value is to be ignored .


<s> static rtx epiphany_function_arg ( cumulative_args_t cum_v , machine_mode mode , const_tree type , bool named ATTRIBUTE_UNUSED ) { CUMULATIVE_ARGS cum = * get_cumulative_args ( cum_v ) ; if ( PASS_IN_REG_P ( cum , mode , type ) ) return gen_rtx_REG ( mode , ROUND_ADVANCE_CUM ( cum , mode , type ) ) ; return 0 ; } </s>

On the EPIPHANY the first MAX_EPIPHANY_PARM_REGS args are normally in registers and the rest are pushed .


<s> bool isMem ( RegisterKind RegKind , bool HasIndex ) const { return ( Kind == KindMem && Mem . RegKind == RegKind && ( HasIndex || ! Mem . Index ) ) ; } </s>


"MMIX Internal: %s is not a shiftable integer"

Print operator suitable for doing something with a shiftable wyde . The type of operator is passed as an asm output modifier .


<s>
void
HexagonFrameLowering
::
processFunctionBeforeFrameFinalized
(
MachineFunction
&
MF
,
RegScavenger
*
RS
)
const
{
MachineFrameInfo
&
MFI
=
MF
.
getFrameInfo
(
)
;
bool
HasAlloca
=
MFI
.
hasVarSizedObjects
(
)
;
bool
NeedsAlign
=
(
MFI
.
getMaxAlignment
(
)
>
getStackAlignment
(
)
)
;
if
(
!
HasAlloca
||
!
NeedsAlign
)
return
;
unsigned
LFS
=
MFI
.
getLocalFrameSize
(
)
;
for
(
int
i
=
0
,
e
=
MFI
.
getObjectIndexEnd
(
)
;
i
!=
e
;
++
i
)
{
if
(
!
MFI
.
isSpillSlotObjectIndex
(
i
)
||
MFI
.
isDeadObjectIndex
(
i
)
)
continue
;
unsigned
S
=
MFI
.
getObjectSize
(
i
)
;
unsigned
A
=
std
::
max
(
MFI
.
getObjectAlignment
(
i
)
,
8U
)
;
MFI
.
setObjectAlignment
(
i
,
8
)
;
LFS
=
alignTo
(
LFS
+
S
,
A
)
;
MFI
.
mapLocalFrameObject
(
i
,
LFS
)
;
}
MFI
.
setLocalFrameSize
(
LFS
)
;
unsigned
A
=
MFI
.
getLocalFrameMaxAlign
(
)
;
assert
(
A
<=
8
&&
"Unexpected local frame alignment"
)
;
if
(
A
==
0
)
MFI
.
setLocalFrameMaxAlign
(
8
)
;
MFI
.
setUseLocalStackAllocationBlock
(
true
)
;
unsigned
AP
=
0
;
if
(
const
MachineInstr
*
AI
=
getAlignaInstr
(
MF
)
)
AP
=
AI
->
getOperand
(
0
)
.
getReg
(
)
;
auto
&
HMFI
=
*
MF
.
getInfo
<
HexagonMachineFunctionInfo
>
(
)
;
HMFI
.
setStackAlignBasePhysReg
(
AP
)
;
}
</s>

processFunctionBeforeFrameFinalized - This method is called immediately before the specified function 's frame layout ( MF.getFrameInfo ( ) ) is finalized .


<s> void PPCFrameLowering :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { const PPCInstrInfo & TII = * static_cast < const PPCInstrInfo * > ( MF . getTarget ( ) . getInstrInfo ( ) ) ; if ( MF . getTarget ( ) . Options . GuaranteedTailCallOpt && I -> getOpcode ( ) == PPC :: ADJCALLSTACKUP ) { if ( int CalleeAmt = I -> getOperand ( 1 ) . getImm ( ) ) { bool is64Bit = Subtarget . isPPC64 ( ) ; CalleeAmt *= - 1 ; unsigned StackReg = is64Bit ? PPC :: X1 : PPC :: R1 ; unsigned TmpReg = is64Bit ? PPC :: X0 : PPC :: R0 ; unsigned ADDIInstr = is64Bit ? PPC :: ADDI8 : PPC :: ADDI ; unsigned ADDInstr = is64Bit ? PPC :: ADD8 : PPC :: ADD4 ; unsigned LISInstr = is64Bit ? PPC :: LIS8 : PPC :: LIS ; unsigned ORIInstr = is64Bit ? PPC :: ORI8 : PPC :: ORI ; MachineInstr * MI = I ; DebugLoc dl = MI -> getDebugLoc ( ) ; if ( isInt < 16 > ( CalleeAmt ) ) { BuildMI ( MBB , I , dl , TII . get ( ADDIInstr ) , StackReg ) . addReg ( StackReg , RegState :: Kill ) . addImm ( CalleeAmt ) ; } else { MachineBasicBlock :: iterator MBBI = I ; BuildMI ( MBB , MBBI , dl , TII . get ( LISInstr ) , TmpReg ) . addImm ( CalleeAmt >> 16 ) ; BuildMI ( MBB , MBBI , dl , TII . get ( ORIInstr ) , TmpReg ) . addReg ( TmpReg , RegState :: Kill ) . addImm ( CalleeAmt & 0xFFFF ) ; BuildMI ( MBB , MBBI , dl , TII . get ( ADDInstr ) , StackReg ) . addReg ( StackReg , RegState :: Kill ) . addReg ( TmpReg ) ; } } } MBB . erase ( I ) ; } </s>

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .


<s> static void arm_init_acle_builtins ( void ) { unsigned int i , fcode = ARM_BUILTIN_ACLE_PATTERN_START ; for ( i = 0 ; i < ARRAY_SIZE ( acle_builtin_data ) ; i ++ , fcode ++ ) { arm_builtin_datum * d = & acle_builtin_data [ i ] ; arm_init_builtin ( fcode , d , "__builtin_arm" ) ; } } </s>

Set up ACLE builtins , even builtins for instructions that are not in the current target ISA to allow the user to compile particular modules with different target specific options that differ from the command line options . Such builtins will be rejected in arm_expand_builtin .


<s> static int arm_get_vfp_saved_size ( void ) { unsigned int regno ; int count ; int saved ; saved = 0 ; if ( TARGET_VFP_BASE ) { count = 0 ; for ( regno = FIRST_VFP_REGNUM ; regno < LAST_VFP_REGNUM ; regno += 2 ) { if ( ! reg_needs_saving_p ( regno ) && ! reg_needs_saving_p ( regno + 1 ) ) { if ( count > 0 ) { if ( count == 2 && ! arm_arch6 ) count ++ ; saved += count * 8 ; } count = 0 ; } else count ++ ; } if ( count > 0 ) { if ( count == 2 && ! arm_arch6 ) count ++ ; saved += count * 8 ; } } return saved ; } </s>

Return the number of bytes required to save VFP registers .


<s>
StringRef
getPassName
(
)
const
override
{
return
"R600 Expand special instructions pass"
;
}
</s>

getPassName - Return a nice clean name for a pass .

AMDGPU
"R600 Expand special instructions pass"


<s> MCSymbol * X86AsmPrinter :: GetCPISymbol ( unsigned CPID ) const { if ( Subtarget -> isTargetKnownWindowsMSVC ( ) ) { const MachineConstantPoolEntry & CPE = MF -> getConstantPool ( ) -> getConstants ( ) [ CPID ] ; if ( ! CPE . isMachineConstantPoolEntry ( ) ) { SectionKind Kind = CPE . getSectionKind ( TM . getSubtargetImpl ( ) -> getDataLayout ( ) ) ; const Constant * C = CPE . Val . ConstVal ; if ( const MCSectionCOFF * S = dyn_cast < MCSectionCOFF > ( getObjFileLowering ( ) . getSectionForConstant ( Kind , C ) ) ) { if ( MCSymbol * Sym = S -> getCOMDATSymbol ( ) ) { if ( Sym -> isUndefined ( ) ) OutStreamer . EmitSymbolAttribute ( Sym , MCSA_Global ) ; return Sym ; } } } } return AsmPrinter :: GetCPISymbol ( CPID ) ; } </s>

Return the symbol for the specified constant pool entry .


<s> void sh_expand_sym_label2reg ( rtx reg , rtx sym , rtx lab , bool sibcall_p ) { const_tree decl = SYMBOL_REF_DECL ( sym ) ; bool is_weak = ( decl && DECL_P ( decl ) && DECL_WEAK ( decl ) ) ; if ( ! is_weak && SYMBOL_REF_LOCAL_P ( sym ) ) emit_insn ( gen_sym_label2reg ( reg , sym , lab ) ) ; else if ( sibcall_p && SYMBOL_REF_LOCAL_P ( sym ) ) emit_insn ( gen_symPCREL_label2reg ( reg , sym , lab ) ) ; else emit_insn ( gen_symPLT_label2reg ( reg , sym , lab ) ) ; } </s>

Expand to appropriate sym * _label2reg for SYM and SIBCALL_P .


<s> bool mprocPassConfig :: addPreEmitPass ( ) { addPass ( createmprocBranchSelectionPass ( ) ) ; return false ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s> bool MOSPassConfig :: addLegalizeMachineIR ( ) { addPass ( new Legalizer ( ) ) ; return false ; } </s>

This method should install a legalize pass , which converts the instruction sequence into one that can be selected by the target .