<s> bool X86AsmPrinter :: runOnMachineFunction ( MachineFunction & MF ) { Subtarget = & MF . getSubtarget < X86Subtarget > ( ) ; SMShadowTracker . startFunction ( MF ) ; CodeEmitter . reset ( TM . getTarget ( ) . createMCCodeEmitter ( * Subtarget -> getInstrInfo ( ) , * Subtarget -> getRegisterInfo ( ) , MF . getContext ( ) ) ) ; EmitFPOData = Subtarget -> isTargetWin32 ( ) && MF . getMMI ( ) . getModule ( ) -> getCodeViewFlag ( ) ; SetupMachineFunction ( MF ) ; if ( Subtarget -> isTargetCOFF ( ) ) { bool Local = MF . getFunction ( ) . hasLocalLinkage ( ) ; OutStreamer -> BeginCOFFSymbolDef ( CurrentFnSym ) ; OutStreamer -> EmitCOFFSymbolStorageClass ( Local ? COFF :: IMAGE_SYM_CLASS_STATIC : COFF :: IMAGE_SYM_CLASS_EXTERNAL ) ; OutStreamer -> EmitCOFFSymbolType ( COFF :: IMAGE_SYM_DTYPE_FUNCTION << COFF :: SCT_COMPLEX_TYPE_SHIFT ) ; OutStreamer -> EndCOFFSymbolDef ( ) ; } EmitFunctionBody ( ) ; emitXRayTable ( ) ; EmitFPOData = false ; return false ; } </s>


<s> nodeType getType ( ) { return type . getNodeType ( ) ; } </s>

Overload to return most specific vector type .


<s> unsigned internalKnownBits ( ) const { unsigned Bits = Unalign ? Unalign : KnownBits ; if ( Size & ( ( 1u << Bits ) - 1 ) ) Bits = countTrailingZeros ( Size ) ; return Bits ; } </s>

Compute the number of known offset bits internally to this block .


<s> MachineInstr * HexagonInstrInfo :: findLoopInstr ( MachineBasicBlock * BB , unsigned EndLoopOp , MachineBasicBlock * TargetBB , SmallPtrSet < MachineBasicBlock * , 8 > & Visited ) const { unsigned LOOPi ; unsigned LOOPr ; if ( EndLoopOp == Hexagon :: ENDLOOP0 ) { LOOPi = Hexagon :: J2_loop0i ; LOOPr = Hexagon :: J2_loop0r ; } else { LOOPi = Hexagon :: J2_loop1i ; LOOPr = Hexagon :: J2_loop1r ; } for ( MachineBasicBlock * PB : BB -> predecessors ( ) ) { if ( ! Visited . insert ( PB ) . second ) continue ; if ( PB == BB ) continue ; for ( MachineInstr & I : llvm :: reverse ( PB -> instrs ( ) ) ) { unsigned Opc = I . getOpcode ( ) ; if ( Opc == LOOPi || Opc == LOOPr ) return & I ; if ( Opc == EndLoopOp && I . getOperand ( 0 ) . getMBB ( ) != TargetBB ) return nullptr ; } if ( MachineInstr * Loop = findLoopInstr ( PB , EndLoopOp , TargetBB , Visited ) ) return Loop ; } return nullptr ; } </s>

Find the hardware loop instruction used to set-up the specified loop .


<s> void loongarch_move_integer ( rtx temp , rtx dest , unsigned HOST_WIDE_INT value ) { struct loongarch_integer_op codes [ LARCH_MAX_INTEGER_OPS ] ; machine_mode mode ; unsigned int i , num_ops ; rtx x ; mode = GET_MODE ( dest ) ; num_ops = loongarch_build_integer ( codes , value ) ; x = GEN_INT ( codes [ 0 ] . value ) ; for ( i = 1 ; i < num_ops ; i ++ ) { if ( ! can_create_pseudo_p ( ) ) { emit_insn ( gen_rtx_SET ( temp , x ) ) ; x = temp ; } else x = force_reg ( mode , x ) ; switch ( codes [ i ] . method ) { case METHOD_NORMAL : x = gen_rtx_fmt_ee ( codes [ i ] . code , mode , x , GEN_INT ( codes [ i ] . value ) ) ; break ; case METHOD_LU32I : emit_insn ( gen_rtx_SET ( x , gen_rtx_IOR ( DImode , gen_rtx_ZERO_EXTEND ( DImode , gen_rtx_SUBREG ( SImode , x , 0 ) ) , GEN_INT ( codes [ i ] . value ) ) ) ) ; break ; case METHOD_LU52I : emit_insn ( gen_lu52i_d ( x , x , GEN_INT ( 0xfffffffffffff ) , GEN_INT ( codes [ i ] . value ) ) ) ; break ; case METHOD_INSV : emit_insn ( gen_rtx_SET ( gen_rtx_ZERO_EXTRACT ( DImode , x , GEN_INT ( 20 ) , GEN_INT ( 32 ) ) , gen_rtx_REG ( DImode , 0 ) ) ) ; break ; default : gcc_unreachable ( ) ; } } emit_insn ( gen_rtx_SET ( dest , x ) ) ; } </s>

Load VALUE into DEST . TEMP is as for loongarch_force_temporary .


"********** Prepare For LiveIntervals **********\n"

"LiveIntervals shouldn't be active yet!"

runOnMachineFunction - Emit the function body .


<s> int h8300_legitimate_constant_p ( rtx x ATTRIBUTE_UNUSED ) { return 1 ; } </s>

Return nonzero if X is a legitimate constant .


<s> TargetLowering :: AtomicExpansionKind ARMTargetLowering :: shouldExpandAtomicCmpXchgInIR ( AtomicCmpXchgInst * AI ) const { unsigned Size = AI -> getOperand ( 1 ) -> getType ( ) -> getPrimitiveSizeInBits ( ) ; bool HasAtomicCmpXchg ; if ( Subtarget -> isMClass ( ) ) HasAtomicCmpXchg = Subtarget -> hasV8MBaselineOps ( ) ; else if ( Subtarget -> isThumb ( ) ) HasAtomicCmpXchg = Subtarget -> hasV7Ops ( ) ; else HasAtomicCmpXchg = Subtarget -> hasV6Ops ( ) ; if ( getTargetMachine ( ) . getOptLevel ( ) != 0 && HasAtomicCmpXchg && Size <= ( Subtarget -> isMClass ( ) ? 32U : 64U ) ) return AtomicExpansionKind :: LLSC ; return AtomicExpansionKind :: None ; } </s>

Returns how the given atomic cmpxchg should be expanded by the IR-level AtomicExpand pass .


<s> SDValue getStoredValue ( SDValue Op ) { switch ( Op -> getOpcode ( ) ) { case ISD :: EXPERIMENTAL_VP_STRIDED_STORE : case VEISD :: VVP_STORE : return Op -> getOperand ( 1 ) ; } if ( auto * StoreN = dyn_cast < StoreSDNode > ( Op . getNode ( ) ) ) return StoreN -> getValue ( ) ; if ( auto * StoreN = dyn_cast < MaskedStoreSDNode > ( Op . getNode ( ) ) ) return StoreN -> getValue ( ) ; if ( auto * StoreN = dyn_cast < VPStridedStoreSDNode > ( Op . getNode ( ) ) ) return StoreN -> getValue ( ) ; if ( auto * StoreN = dyn_cast < VPStoreSDNode > ( Op . getNode ( ) ) ) return StoreN -> getValue ( ) ; if ( auto * StoreN = dyn_cast < MaskedScatterSDNode > ( Op . getNode ( ) ) ) return StoreN -> getValue ( ) ; if ( auto * StoreN = dyn_cast < VPScatterSDNode > ( Op . getNode ( ) ) ) return StoreN -> getValue ( ) ; return SDValue ( ) ; } </s>

Return the address accessed by this recipe .


<s> static bool riscv_naked_function_p ( tree func ) { tree func_decl = func ; if ( func == NULL_TREE ) func_decl = current_function_decl ; return NULL_TREE != lookup_attribute ( "naked" , DECL_ATTRIBUTES ( func_decl ) ) ; } </s>

Return true if func is a naked function .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . addRequired < AssumptionCacheTracker > ( ) ; AU . addPreserved < DominatorTreeWrapperPass > ( ) ; AU . addRequired < LoopInfoWrapperPass > ( ) ; AU . addPreserved < LoopInfoWrapperPass > ( ) ; AU . addRequired < ScalarEvolutionWrapperPass > ( ) ; AU . addRequired < TargetTransformInfoWrapperPass > ( ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> bool AMDGPUPassConfig :: addPreRegAlloc ( ) { const AMDGPUSubtarget & ST = TM -> getSubtarget < AMDGPUSubtarget > ( ) ; if ( ST . getGeneration ( ) <= AMDGPUSubtarget :: NORTHERN_ISLANDS ) { addPass ( createR600VectorRegMerger ( * TM ) ) ; } else { addPass ( createSIFixSGPRCopiesPass ( * TM ) ) ; addPass ( & MachineCSEID ) ; addPass ( createSIShrinkInstructionsPass ( ) ) ; initializeSIFixSGPRLiveRangesPass ( * PassRegistry :: getPassRegistry ( ) ) ; insertPass ( & RegisterCoalescerID , & SIFixSGPRLiveRangesID ) ; } return false ; } </s>

This method may be implemented by targets that want to run passes immediately before register allocation .


<s> bool arc_expand_movmem ( rtx * operands ) { rtx dst = operands [ 0 ] ; rtx src = operands [ 1 ] ; rtx dst_addr , src_addr ; HOST_WIDE_INT size ; int align = INTVAL ( operands [ 3 ] ) ; unsigned n_pieces ; int piece = align ; rtx store [ 2 ] ; rtx tmpx [ 2 ] ; int i ; if ( ! CONST_INT_P ( operands [ 2 ] ) ) return false ; size = INTVAL ( operands [ 2 ] ) ; if ( align >= 4 ) { if ( TARGET_LL64 ) n_pieces = ( size + 4 ) / 8U + ( ( size >> 1 ) & 1 ) + ( size & 1 ) ; else n_pieces = ( size + 2 ) / 4U + ( size & 1 ) ; } else if ( align == 2 ) n_pieces = ( size + 1 ) / 2U ; else n_pieces = size ; if ( n_pieces >= ( unsigned int ) ( optimize_size ? 3 : 15 ) ) return false ; if ( TARGET_LL64 && ( piece >= 4 ) && ( size >= 8 ) ) piece = 8 ; else if ( piece > 4 ) piece = 4 ; dst_addr = force_offsettable ( XEXP ( operands [ 0 ] , 0 ) , size , 0 ) ; src_addr = force_offsettable ( XEXP ( operands [ 1 ] , 0 ) , size , 0 ) ; store [ 0 ] = store [ 1 ] = NULL_RTX ; tmpx [ 0 ] = tmpx [ 1 ] = NULL_RTX ; for ( i = 0 ; size > 0 ; i ^= 1 , size -= piece ) { rtx tmp ; machine_mode mode ; while ( piece > size ) piece >>= 1 ; mode = smallest_int_mode_for_size ( piece * BITS_PER_UNIT ) ; if ( 0 && tmpx [ i ] && GET_MODE ( tmpx [ i ] ) == mode ) tmp = tmpx [ i ] ; else tmpx [ i ] = tmp = gen_reg_rtx ( mode ) ; dst_addr = force_offsettable ( dst_addr , piece , 1 ) ; src_addr = force_offsettable ( src_addr , piece , 1 ) ; if ( store [ i ] ) emit_insn ( store [ i ] ) ; emit_move_insn ( tmp , change_address ( src , mode , src_addr ) ) ; store [ i ] = gen_move_insn ( change_address ( dst , mode , dst_addr ) , tmp ) ; dst_addr = plus_constant ( Pmode , dst_addr , piece ) ; src_addr = plus_constant ( Pmode , src_addr , piece ) ; } if ( store [ i ] ) emit_insn ( store [ i ] ) ; if ( store [ i ^ 1 ] ) emit_insn ( store [ i ^ 1 ] ) ; return true ; } </s>

Like move_by_pieces , but take account of load latency , and actual offset ranges . Return true on success .


<s> static void * spu_init_cost ( struct loop * loop_info ATTRIBUTE_UNUSED ) { unsigned * cost = XNEWVEC ( unsigned , 3 ) ; cost [ vect_prologue ] = cost [ vect_body ] = cost [ vect_epilogue ] = 0 ; return cost ; } </s>


<s> bool AArch64TargetLowering :: shouldExpandAtomicLoadInIR ( LoadInst * LI ) const { unsigned Size = LI -> getType ( ) -> getPrimitiveSizeInBits ( ) ; return Size == 128 ; } </s>

Returns how the given ( atomic ) load should be expanded by the IR-level AtomicExpand pass .


<s> void printCustom ( raw_ostream & OS ) const override { OS << "GWSResource" ; } </s>

Implement printing for PseudoSourceValue .


"data area attributes cannot be specified for "

"data area of %q+D conflicts with previous declaration"

Handle a `` sda '' , `` tda '' or `` zda '' attribute ; arguments as in struct attribute_spec.handler .


<s>
void
SystemZMCAsmBackend
::
applyFixup
(
const
MCFixup
&
Fixup
,
MutableArrayRef
<
char
>
Data
,
uint64_t
Value
,
bool
IsPCRel
,
MCContext
&
Ctx
)
const
{
MCFixupKind
Kind
=
Fixup
.
getKind
(
)
;
unsigned
Offset
=
Fixup
.
getOffset
(
)
;
unsigned
BitSize
=
getFixupKindInfo
(
Kind
)
.
TargetSize
;
unsigned
Size
=
(
BitSize
+
7
)
/
8
;
assert
(
Offset
+
Size
<=
Data
.
size
(
)
&&
"Invalid fixup offset!"
)
;
Value
=
extractBitsForFixup
(
Kind
,
Value
)
;
if
(
BitSize
<
64
)
Value
&=
(
(
uint64_t
)
1
<<
BitSize
)
1
;
unsigned
ShiftValue
=
(
Size
*
8
)
8
;
for
(
unsigned
I
=
0
;
I
!=
Size
;
++
I
)
{
Data
[
Offset
+
I
]
|=
uint8_t
(
Value
>>
ShiftValue
)
;
ShiftValue
-=
8
;
}
}
</s>

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


<s> static bool rs6000_discover_homogeneous_aggregate ( machine_mode mode , const_tree type , machine_mode * elt_mode , int * n_elts ) { if ( TARGET_HARD_FLOAT && DEFAULT_ABI == ABI_ELFv2 && type && AGGREGATE_TYPE_P ( type ) ) { machine_mode field_mode = VOIDmode ; int field_count = rs6000_aggregate_candidate ( type , & field_mode ) ; if ( field_count > 0 ) { int n_regs = ( SCALAR_FLOAT_MODE_P ( field_mode ) ? ( GET_MODE_SIZE ( field_mode ) + 7 ) >> 3 : 1 ) ; if ( field_count * n_regs <= AGGR_ARG_NUM_REG ) { if ( elt_mode ) * elt_mode = field_mode ; if ( n_elts ) * n_elts = field_count ; return true ; } } } if ( elt_mode ) * elt_mode = mode ; if ( n_elts ) * n_elts = 1 ; return false ; } </s>

If an argument , whose type is described by TYPE and MODE , is a homogeneous float or vector aggregate that shall be passed in FP/vector registers according to the ELFv2 ABI , return the homogeneous element mode in * ELT_MODE and the number of elements in * N_ELTS , and return TRUE . Otherwise , set * ELT_MODE to MODE and * N_ELTS to 1 , and return FALSE .


<s> void relaxInstruction ( const MCInst & Inst , const MCSubtargetInfo & STI , MCInst & Res ) const override { } </s>

Relax the instruction in the given fragment to the next wider instruction .


<s> bool empty ( ) const { return getSGRPNum ( ) == 0 && getVGRPNum ( ) == 0 ; } </s>

Determine whether this version information is empty ( e.g. , all version components are zero ) .


<s> unsigned getNumFixupKinds ( ) const override { return CJG :: NumTargetFixupKinds ; } </s>

Get the number of target specific fixup kinds .


<s> bool HexagonInstrInfo :: isProfitableToIfCvt ( MachineBasicBlock & TMBB , unsigned NumTCycles , unsigned ExtraTCycles , MachineBasicBlock & FMBB , unsigned NumFCycles , unsigned ExtraFCycles , BranchProbability Probability ) const { return true ; } </s>


<s> static rtx rs6000_delegitimize_address ( rtx orig_x ) { rtx x , y , offset ; if ( GET_CODE ( orig_x ) == UNSPEC ) switch ( XINT ( orig_x , 1 ) ) { case UNSPEC_FUSION_GPR : case UNSPEC_PCREL_OPT_LD_ADDR : case UNSPEC_PCREL_OPT_LD_SAME_REG : case UNSPEC_PCREL_OPT_ST_ADDR : orig_x = XVECEXP ( orig_x , 0 , 0 ) ; break ; default : break ; } orig_x = delegitimize_mem_from_attrs ( orig_x ) ; x = orig_x ; if ( MEM_P ( x ) ) x = XEXP ( x , 0 ) ; y = x ; if ( TARGET_CMODEL != CMODEL_SMALL && GET_CODE ( y ) == LO_SUM ) y = XEXP ( y , 1 ) ; offset = NULL_RTX ; if ( GET_CODE ( y ) == PLUS && GET_MODE ( y ) == Pmode && CONST_INT_P ( XEXP ( y , 1 ) ) ) { offset = XEXP ( y , 1 ) ; y = XEXP ( y , 0 ) ; } if ( GET_CODE ( y ) == UNSPEC && XINT ( y , 1 ) == UNSPEC_TOCREL ) { y = XVECEXP ( y , 0 , 0 ) ; if ( TARGET_XCOFF && SYMBOL_REF_P ( y ) && CONSTANT_POOL_ADDRESS_P ( y ) && rs6000_real_tls_symbol_ref_p ( get_pool_constant ( y ) ) ) return orig_x ; if ( offset != NULL_RTX ) y = gen_rtx_PLUS ( Pmode , y , offset ) ; if ( ! MEM_P ( orig_x ) ) return y ; else return replace_equiv_address_nv ( orig_x , y ) ; } if ( TARGET_MACHO && GET_CODE ( orig_x ) == LO_SUM && GET_CODE ( XEXP ( orig_x , 1 ) ) == CONST ) { y = XEXP ( XEXP ( orig_x , 1 ) , 0 ) ; if ( GET_CODE ( y ) == UNSPEC && XINT ( y , 1 ) == UNSPEC_MACHOPIC_OFFSET ) return XVECEXP ( y , 0 , 0 ) ; } return orig_x ; } </s>

In the name of slightly smaller debug output , and to cater to general assembler lossage , recognize various UNSPEC sequences and turn them back into a direct symbol reference .


<s>
void
print_operand_address
(
FILE
*
file
,
rtx
addr
)
{
int
basereg
=
31
;
HOST_WIDE_INT
offset
=
0
;
if
(
GET_CODE
(
addr
)
==
AND
)
addr
=
XEXP
(
addr
,
0
)
;
if
(
GET_CODE
(
addr
)
==
PLUS
&&
GET_CODE
(
XEXP
(
addr
,
1
)
)
==
CONST_INT
)
{
offset
=
INTVAL
(
XEXP
(
addr
,
1
)
)
;
addr
=
XEXP
(
addr
,
0
)
;
}
if
(
GET_CODE
(
addr
)
==
LO_SUM
)
{
const
char
*
reloc16
,
*
reloclo
;
rtx
op1
=
XEXP
(
addr
,
1
)
;
if
(
GET_CODE
(
op1
)
==
CONST
&&
GET_CODE
(
XEXP
(
op1
,
0
)
)
==
UNSPEC
)
{
op1
=
XEXP
(
op1
,
0
)
;
switch
(
XINT
(
op1
,
1
)
)
{
case
UNSPEC_DTPREL
:
reloc16
=
;
reloclo
=
(
alpha_tls_size
==
16
"dtprel"
:
"dtprello"
)
;
break
;
case
UNSPEC_TPREL
:
reloc16
=
;
reloclo
=
(
alpha_tls_size
==
16
"tprel"
:
"tprello"
)
;
break
;
default
:
output_operand_lossage
(
"unknown relocation unspec"
)
;
return
;
}
output_addr_const
(
file
,
XVECEXP
(
op1
,
0
,
0
)
)
;
}
else
{
reloc16
=
"gprel"
;
reloclo
=
"gprellow"
;
output_addr_const
(
file
,
op1
)
;
}
if
(
offset
)
fprintf
(
file
,
"+"
HOST_WIDE_INT_PRINT_DEC
,
offset
)
;
addr
=
XEXP
(
addr
,
0
)
;
switch
(
GET_CODE
(
addr
)
)
{
case
REG
:
basereg
=
REGNO
(
addr
)
;
break
;
case
SUBREG
:
basereg
=
subreg_regno
(
addr
)
;
break
;
default
:
gcc_unreachable
(
)
;
}
fprintf
(
file
,
"($%d)\t\t!%s"
,
basereg
,
(
basereg
==
29
reloc16
:
reloclo
)
)
;
return
;
}
switch
(
GET_CODE
(
addr
)
)
{
case
REG
:
basereg
=
REGNO
(
addr
)
;
break
;
case
SUBREG
:
basereg
=
subreg_regno
(
addr
)
;
break
;
case
CONST_INT
:
offset
=
INTVAL
(
addr
)
;
break
;
case
SYMBOL_REF
:
fprintf
(
file
,
"%s"
,
XSTR
(
addr
,
0
)
)
;
return
;
case
CONST
:
gcc_assert
(
GET_CODE
(
XEXP
(
addr
,
0
)
)
==
PLUS
&&
GET_CODE
(
XEXP
(
XEXP
(
addr
,
0
)
,
0
)
)
==
SYMBOL_REF
)
;
fprintf
(
file
,
"%s+"
HOST_WIDE_INT_PRINT_DEC
,
XSTR
(
XEXP
(
XEXP
(
addr
,
0
)
,
0
)
,
0
)
,
INTVAL
(
XEXP
(
XEXP
(
addr
,
0
)
,
1
)
)
)
;
return
;
default
:
gcc_unreachable
(
)
;
}
fprintf
(
file
,
HOST_WIDE_INT_PRINT_DEC
"($%d)"
,
offset
,
basereg
)
;
}
</s>

Print the operand address represented by the rtx addr


"loadRegFromStackSlot didn't insert any code!"

restoreCalleeSavedRegisters - Issues instruction ( s ) to restore all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of load instructions via loadRegToStackSlot ( ) .


<s> BitVector PPCRegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; const PPCSubtarget & Subtarget = MF . getSubtarget < PPCSubtarget > ( ) ; const PPCFrameLowering * TFI = getFrameLowering ( MF ) ; Reserved . set ( PPC :: ZERO ) ; Reserved . set ( PPC :: ZERO8 ) ; Reserved . set ( PPC :: FP ) ; Reserved . set ( PPC :: FP8 ) ; Reserved . set ( PPC :: BP ) ; Reserved . set ( PPC :: BP8 ) ; Reserved . set ( PPC :: CTR ) ; Reserved . set ( PPC :: CTR8 ) ; Reserved . set ( PPC :: R1 ) ; Reserved . set ( PPC :: LR ) ; Reserved . set ( PPC :: LR8 ) ; Reserved . set ( PPC :: RM ) ; if ( ! Subtarget . isDarwinABI ( ) || ! Subtarget . hasAltivec ( ) ) Reserved . set ( PPC :: VRSAVE ) ; if ( Subtarget . isSVR4ABI ( ) ) { Reserved . set ( PPC :: R2 ) ; Reserved . set ( PPC :: R13 ) ; } if ( TM . isPPC64 ( ) ) { Reserved . set ( PPC :: R13 ) ; Reserved . set ( PPC :: X1 ) ; Reserved . set ( PPC :: X13 ) ; if ( TFI -> needsFP ( MF ) ) Reserved . set ( PPC :: X31 ) ; if ( hasBasePointer ( MF ) ) Reserved . set ( PPC :: X30 ) ; if ( Subtarget . isSVR4ABI ( ) ) { const PPCFunctionInfo * FuncInfo = MF . getInfo < PPCFunctionInfo > ( ) ; if ( FuncInfo -> usesTOCBasePtr ( ) || MF . hasInlineAsm ( ) ) Reserved . set ( PPC :: X2 ) ; else Reserved . reset ( PPC :: R2 ) ; } } if ( TFI -> needsFP ( MF ) ) Reserved . set ( PPC :: R31 ) ; bool IsPositionIndependent = TM . isPositionIndependent ( ) ; if ( hasBasePointer ( MF ) ) { if ( Subtarget . isSVR4ABI ( ) && ! TM . isPPC64 ( ) && IsPositionIndependent ) Reserved . set ( PPC :: R29 ) ; else Reserved . set ( PPC :: R30 ) ; } if ( Subtarget . isSVR4ABI ( ) && ! TM . isPPC64 ( ) && IsPositionIndependent ) Reserved . set ( PPC :: R30 ) ; if ( ! Subtarget . hasAltivec ( ) ) for ( TargetRegisterClass :: iterator I = PPC :: VRRCRegClass . begin ( ) , IE = PPC :: VRRCRegClass . end ( ) ; I != IE ; ++ I ) Reserved . set ( * I ) ; return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s> static void ix86_init_large_pic_reg ( unsigned int tmp_regno ) { rtx_code_label * label ; rtx tmp_reg ; gcc_assert ( Pmode == DImode ) ; label = gen_label_rtx ( ) ; emit_label ( label ) ; LABEL_PRESERVE_P ( label ) = 1 ; tmp_reg = gen_rtx_REG ( Pmode , tmp_regno ) ; gcc_assert ( REGNO ( pic_offset_table_rtx ) != tmp_regno ) ; emit_insn ( gen_set_rip_rex64 ( pic_offset_table_rtx , label ) ) ; emit_insn ( gen_set_got_offset_rex64 ( tmp_reg , label ) ) ; emit_insn ( ix86_gen_add3 ( pic_offset_table_rtx , pic_offset_table_rtx , tmp_reg ) ) ; const char * name = LABEL_NAME ( label ) ; PUT_CODE ( label , NOTE ) ; NOTE_KIND ( label ) = NOTE_INSN_DELETED_LABEL ; NOTE_DELETED_LABEL_NAME ( label ) = name ; } </s>


<s> void TLCS900RegisterInfo :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { const TargetFrameLowering * TFI = MF . getTarget ( ) . getFrameLowering ( ) ; if ( ! TFI -> hasReservedCallFrame ( MF ) ) { MachineInstr * Old = I ; uint64_t Amount = Old -> getOperand ( 0 ) . getImm ( ) ; if ( Amount != 0 ) { Amount = ( Amount + StackAlign - 1 ) / StackAlign * StackAlign ; MachineInstr * New = 0 ; if ( Old -> getOpcode ( ) == TII . getCallFrameSetupOpcode ( ) ) { New = BuildMI ( MF , Old -> getDebugLoc ( ) , TII . get ( TLCS900 :: SUB16ri ) , TLCS900 :: SPW ) . addReg ( TLCS900 :: SPW ) . addImm ( Amount ) ; } else { assert ( Old -> getOpcode ( ) == TII . getCallFrameDestroyOpcode ( ) ) ; uint64_t CalleeAmt = Old -> getOperand ( 1 ) . getImm ( ) ; Amount -= CalleeAmt ; if ( Amount ) New = BuildMI ( MF , Old -> getDebugLoc ( ) , TII . get ( TLCS900 :: ADD16ri ) , TLCS900 :: SPW ) . addReg ( TLCS900 :: SPW ) . addImm ( Amount ) ; } if ( New ) { New -> getOperand ( 3 ) . setIsDead ( ) ; MBB . insert ( I , New ) ; } } } else if ( I -> getOpcode ( ) == TII . getCallFrameDestroyOpcode ( ) ) { if ( uint64_t CalleeAmt = I -> getOperand ( 1 ) . getImm ( ) ) { MachineInstr * Old = I ; MachineInstr * New = BuildMI ( MF , Old -> getDebugLoc ( ) , TII . get ( TLCS900 :: SUB16ri ) , TLCS900 :: SPW ) . addReg ( TLCS900 :: SPW ) . addImm ( CalleeAmt ) ; New -> getOperand ( 3 ) . setIsDead ( ) ; MBB . insert ( I , New ) ; } } MBB . erase ( I ) ; } </s>

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .


<s> void PPCDAGToDAGISel :: PostprocessISelDAG ( ) { if ( TM . getOptLevel ( ) == CodeGenOpt :: None ) return ; PeepholePPC64 ( ) ; PeepholdCROps ( ) ; } </s>

PostprocessISelDAG ( ) - This hook allows the target to hack on the graph right after selection .


<s> bool TOYRegisterInfo :: requiresRegisterScavenging ( const MachineFunction & MF ) const { return true ; } </s>

Returns true if the target requires ( and can make use of ) the register scavenger .


<s> static void vector_init_faligndata ( rtx target , rtx elt ) { rtx t1 = gen_reg_rtx ( V4HImode ) ; int i ; elt = convert_modes ( SImode , HImode , elt , true ) ; emit_move_insn ( gen_lowpart ( SImode , t1 ) , elt ) ; emit_insn ( gen_alignaddrsi_vis ( gen_reg_rtx ( SImode ) , force_reg ( SImode , GEN_INT ( 6 ) ) , const0_rtx ) ) ; for ( i = 0 ; i < 4 ; i ++ ) emit_insn ( gen_faligndatav4hi_vis ( target , t1 , target ) ) ; } </s>

Subroutine of sparc_expand_vector_init . Emit code to initialize all fields of TARGET to ELT in V4HI by means of VIS FALIGNDATA insn .


<s>
SDValue
PPCTargetLowering
::
LowerReturn
(
SDValue
Chain
,
CallingConv
::
ID
CallConv
,
bool
isVarArg
,
const
SmallVectorImpl
<
ISD
::
OutputArg
>
&
Outs
,
const
SmallVectorImpl
<
SDValue
>
&
OutVals
,
SDLoc
dl
,
SelectionDAG
&
DAG
)
const
{
SmallVector
<
CCValAssign
,
16
>
RVLocs
;
CCState
CCInfo
(
CallConv
,
isVarArg
,
DAG
.
getMachineFunction
(
)
,
getTargetMachine
(
)
,
RVLocs
,
*
DAG
.
getContext
(
)
)
;
CCInfo
.
AnalyzeReturn
(
Outs
,
RetCC_PPC
)
;
SDValue
Flag
;
SmallVector
<
SDValue
,
4
>
RetOps
(
1
,
Chain
)
;
for
(
unsigned
i
=
0
;
i
!=
RVLocs
.
size
(
)
;
++
i
)
{
CCValAssign
&
VA
=
RVLocs
[
i
]
;
assert
(
VA
.
isRegLoc
(
)
&&
"Can only return in registers!"
)
;
SDValue
Arg
=
OutVals
[
i
]
;
switch
(
VA
.
getLocInfo
(
)
)
{
default
:
llvm_unreachable
(
"Unknown loc info!"
)
;
case
CCValAssign
::
Full
:
break
;
case
CCValAssign
::
AExt
:
Arg
=
DAG
.
getNode
(
ISD
::
ANY_EXTEND
,
dl
,
VA
.
getLocVT
(
)
,
Arg
)
;
break
;
case
CCValAssign
::
ZExt
:
Arg
=
DAG
.
getNode
(
ISD
::
ZERO_EXTEND
,
dl
,
VA
.
getLocVT
(
)
,
Arg
)
;
break
;
case
CCValAssign
::
SExt
:
Arg
=
DAG
.
getNode
(
ISD
::
SIGN_EXTEND
,
dl
,
VA
.
getLocVT
(
)
,
Arg
)
;
break
;
}
Chain
=
DAG
.
getCopyToReg
(
Chain
,
dl
,
VA
.
getLocReg
(
)
,
Arg
,
Flag
)
;
Flag
=
Chain
.
getValue
(
1
)
;
RetOps
.
push_back
(
DAG
.
getRegister
(
VA
.
getLocReg
(
)
,
VA
.
getLocVT
(
)
)
)
;
}
RetOps
[
0
]
=
Chain
;
if
(
Flag
.
getNode
(
)
)
RetOps
.
push_back
(
Flag
)
;
return
DAG
.
getNode
(
PPCISD
::
RET_FLAG
,
dl
,
MVT
::
Other
,
&
RetOps
[
0
]
,
RetOps
.
size
(
)
)
;
}
</s>

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .


<s> static AMDGPUOperand :: Ptr CreateReg ( unsigned RegNo , SMLoc S , SMLoc E , const MCRegisterInfo * TRI , const MCSubtargetInfo * STI , bool ForceVOP3 ) { auto Op = llvm :: make_unique < AMDGPUOperand > ( Register ) ; Op -> Reg . RegNo = RegNo ; Op -> Reg . TRI = TRI ; Op -> Reg . STI = STI ; Op -> Reg . Modifiers = 0 ; Op -> Reg . IsForcedVOP3 = ForceVOP3 ; Op -> StartLoc = S ; Op -> EndLoc = E ; return Op ; } </s>

CreateReg - Allocate a single virtual register for the given type .


<s> static rtx c6x_expand_binop_builtin ( enum insn_code icode , tree exp , rtx target , bool match_op ) { int offs = match_op ? 1 : 0 ; rtx pat ; tree arg0 = CALL_EXPR_ARG ( exp , 0 ) ; tree arg1 = CALL_EXPR_ARG ( exp , 1 ) ; rtx op0 = expand_expr ( arg0 , NULL_RTX , VOIDmode , EXPAND_NORMAL ) ; rtx op1 = expand_expr ( arg1 , NULL_RTX , VOIDmode , EXPAND_NORMAL ) ; machine_mode op0mode = GET_MODE ( op0 ) ; machine_mode op1mode = GET_MODE ( op1 ) ; machine_mode tmode = insn_data [ icode ] . operand [ 0 ] . mode ; machine_mode mode0 = insn_data [ icode ] . operand [ 1 + offs ] . mode ; machine_mode mode1 = insn_data [ icode ] . operand [ 2 + offs ] . mode ; rtx ret = target ; if ( VECTOR_MODE_P ( mode0 ) ) op0 = safe_vector_operand ( op0 , mode0 ) ; if ( VECTOR_MODE_P ( mode1 ) ) op1 = safe_vector_operand ( op1 , mode1 ) ; if ( ! target || GET_MODE ( target ) != tmode || ! ( * insn_data [ icode ] . operand [ 0 ] . predicate ) ( target , tmode ) ) { if ( tmode == SQmode || tmode == V2SQmode ) { ret = gen_reg_rtx ( tmode == SQmode ? SImode : V2SImode ) ; target = gen_lowpart ( tmode , ret ) ; } else target = gen_reg_rtx ( tmode ) ; } if ( ( op0mode == V2HImode || op0mode == SImode || op0mode == VOIDmode ) && ( mode0 == V2HQmode || mode0 == HQmode || mode0 == SQmode ) ) { op0mode = mode0 ; op0 = gen_lowpart ( mode0 , op0 ) ; } if ( ( op1mode == V2HImode || op1mode == SImode || op1mode == VOIDmode ) && ( mode1 == V2HQmode || mode1 == HQmode || mode1 == SQmode ) ) { op1mode = mode1 ; op1 = gen_lowpart ( mode1 , op1 ) ; } gcc_assert ( ( op0mode == mode0 || op0mode == VOIDmode ) && ( op1mode == mode1 || op1mode == VOIDmode ) ) ; if ( ! ( * insn_data [ icode ] . operand [ 1 + offs ] . predicate ) ( op0 , mode0 ) ) op0 = copy_to_mode_reg ( mode0 , op0 ) ; if ( ! ( * insn_data [ icode ] . operand [ 2 + offs ] . predicate ) ( op1 , mode1 ) ) op1 = copy_to_mode_reg ( mode1 , op1 ) ; if ( match_op ) pat = GEN_FCN ( icode ) ( target , target , op0 , op1 ) ; else pat = GEN_FCN ( icode ) ( target , op0 , op1 ) ; if ( ! pat ) return 0 ; emit_insn ( pat ) ; return ret ; } </s>

Subroutine of c6x_expand_builtin to take care of binop insns . MACFLAG is -1 if this is a normal binary op , or one of the MACFLAG_xxx constants .


<s> unsigned X86InstrInfo :: getUndefRegClearance ( const MachineInstr & MI , unsigned & OpNum , const TargetRegisterInfo * TRI ) const { for ( unsigned i = MI . getNumExplicitDefs ( ) , e = MI . getNumExplicitOperands ( ) ; i != e ; ++ i ) { const MachineOperand & MO = MI . getOperand ( i ) ; if ( MO . isReg ( ) && MO . isUndef ( ) && Register :: isPhysicalRegister ( MO . getReg ( ) ) && hasUndefRegUpdate ( MI . getOpcode ( ) , i ) ) { OpNum = i ; return UndefRegClearance ; } } return 0 ; } </s>

Inform the BreakFalseDeps pass how many idle instructions we would like before certain undef register reads .


<s> TargetLoweringObjectFile * getObjFileLowering ( ) const override { return TLOF . get ( ) ; } </s>

Return information about object file lowering .


<s> void nds32_cpu_cpp_builtins ( struct cpp_reader * pfile ) { builtin_define ( "__nds32__" ) ; builtin_define ( "__NDS32__" ) ; if ( ! TARGET_LINUX_ABI ) { if ( TARGET_ISR_VECTOR_SIZE_4_BYTE ) builtin_define ( "__NDS32_ISR_VECTOR_SIZE_4__" ) ; else builtin_define ( "__NDS32_ISR_VECTOR_SIZE_16__" ) ; } if ( TARGET_HARD_FLOAT ) builtin_define ( "__NDS32_ABI_2FP_PLUS__" ) ; else builtin_define ( "__NDS32_ABI_2__" ) ; if ( TARGET_ISA_V2 ) builtin_define ( "__NDS32_ISA_V2__" ) ; if ( TARGET_ISA_V3 ) builtin_define ( "__NDS32_ISA_V3__" ) ; if ( TARGET_ISA_V3M ) builtin_define ( "__NDS32_ISA_V3M__" ) ; if ( TARGET_FPU_SINGLE ) builtin_define ( "__NDS32_EXT_FPU_SP__" ) ; if ( TARGET_FPU_DOUBLE ) builtin_define ( "__NDS32_EXT_FPU_DP__" ) ; if ( TARGET_EXT_FPU_FMA ) builtin_define ( "__NDS32_EXT_FPU_FMA__" ) ; if ( NDS32_EXT_FPU_DOT_E ) builtin_define ( "__NDS32_EXT_FPU_DOT_E__" ) ; if ( TARGET_FPU_SINGLE || TARGET_FPU_DOUBLE ) { switch ( nds32_fp_regnum ) { case 0 : case 4 : builtin_define ( "__NDS32_EXT_FPU_CONFIG_0__" ) ; break ; case 1 : case 5 : builtin_define ( "__NDS32_EXT_FPU_CONFIG_1__" ) ; break ; case 2 : case 6 : builtin_define ( "__NDS32_EXT_FPU_CONFIG_2__" ) ; break ; case 3 : case 7 : builtin_define ( "__NDS32_EXT_FPU_CONFIG_3__" ) ; break ; default : abort ( ) ; } } if ( TARGET_BIG_ENDIAN ) builtin_define ( "__NDS32_EB__" ) ; else builtin_define ( "__NDS32_EL__" ) ; if ( TARGET_REDUCED_REGS ) builtin_define ( "__NDS32_REDUCED_REGS__" ) ; if ( TARGET_CMOV ) builtin_define ( "__NDS32_CMOV__" ) ; if ( TARGET_EXT_PERF ) builtin_define ( "__NDS32_EXT_PERF__" ) ; if ( TARGET_EXT_PERF2 ) builtin_define ( "__NDS32_EXT_PERF2__" ) ; if ( TARGET_EXT_STRING ) builtin_define ( "__NDS32_EXT_STRING__" ) ; if ( TARGET_16_BIT ) builtin_define ( "__NDS32_16_BIT__" ) ; if ( TARGET_GP_DIRECT ) builtin_define ( "__NDS32_GP_DIRECT__" ) ; if ( TARGET_VH ) builtin_define ( "__NDS32_VH__" ) ; if ( NDS32_EXT_DSP_P ( ) ) builtin_define ( "__NDS32_EXT_DSP__" ) ; if ( TARGET_BIG_ENDIAN ) builtin_define ( "__big_endian__" ) ; builtin_assert ( "cpu=nds32" ) ; builtin_assert ( "machine=nds32" ) ; if ( TARGET_HARD_FLOAT ) builtin_define ( "__NDS32_ABI_2FP_PLUS" ) ; else builtin_define ( "__NDS32_ABI_2" ) ; } </s>


<s> static bool check_mduc_usage ( void ) { rtx_insn * insn ; basic_block bb ; FOR_EACH_BB_FN ( bb , cfun ) { FOR_BB_INSNS ( bb , insn ) { if ( INSN_P ( insn ) && ( get_attr_is_g13_muldiv_insn ( insn ) == IS_G13_MULDIV_INSN_YES ) ) return true ; } } return false ; } </s>

Check if the block uses mul/div insns for G13 target .


<s> int ia64_load_pair_ok ( rtx dst , rtx src ) { if ( GET_CODE ( dst ) != REG || ! ( FP_REGNO_P ( REGNO ( dst ) ) && FP_REGNO_P ( REGNO ( dst ) + 1 ) ) ) return 0 ; if ( GET_CODE ( src ) != MEM || MEM_VOLATILE_P ( src ) ) return 0 ; switch ( GET_CODE ( XEXP ( src , 0 ) ) ) { case REG : case POST_INC : break ; case POST_DEC : return 0 ; case POST_MODIFY : { rtx adjust = XEXP ( XEXP ( XEXP ( src , 0 ) , 1 ) , 1 ) ; if ( GET_CODE ( adjust ) != CONST_INT || INTVAL ( adjust ) != GET_MODE_SIZE ( GET_MODE ( src ) ) ) return 0 ; } break ; default : abort ( ) ; } return 1 ; } </s>

Return 1 if the operands are ok for a floating point load pair .


<s> bool XCoreRegisterInfo :: needsFrameMoves ( const MachineFunction & MF ) { return MF . getMMI ( ) . hasDebugInfo ( ) || MF . getFunction ( ) . needsUnwindTableEntry ( ) ; } </s>


<s> SDValue NyuziTargetLowering :: getTargetNode ( const BlockAddressSDNode * N , EVT Ty , SelectionDAG & DAG , unsigned int Flag ) const { return DAG . getTargetBlockAddress ( N -> getBlockAddress ( ) , Ty , 0 , Flag ) ; } </s>

Retrieve the target node this edge connects to .


<s> uint64_t flags ( ) const { return 0x0 ; } </s>

Get the flags for this GlobalValue ( see struct GVFlags ) .


<s>
void
SparcInstrInfo
::
copyPhysReg
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
DebugLoc
DL
,
unsigned
DestReg
,
unsigned
SrcReg
,
bool
KillSrc
)
const
{
if
(
SP
::
IntRegsRegClass
.
contains
(
DestReg
,
SrcReg
)
)
BuildMI
(
MBB
,
I
,
DL
,
get
(
SP
::
ORrr
)
,
DestReg
)
.
addReg
(
SP
::
G0
)
.
addReg
(
SrcReg
,
getKillRegState
(
KillSrc
)
)
;
else
if
(
SP
::
FPRegsRegClass
.
contains
(
DestReg
,
SrcReg
)
)
BuildMI
(
MBB
,
I
,
DL
,
get
(
SP
::
FMOVS
)
,
DestReg
)
.
addReg
(
SrcReg
,
getKillRegState
(
KillSrc
)
)
;
else
if
(
SP
::
DFPRegsRegClass
.
contains
(
DestReg
,
SrcReg
)
)
{
if
(
Subtarget
.
isV9
(
)
)
{
BuildMI
(
MBB
,
I
,
DL
,
get
(
SP
::
FMOVD
)
,
DestReg
)
.
addReg
(
SrcReg
,
getKillRegState
(
KillSrc
)
)
;
}
else
{
const
TargetRegisterInfo
*
TRI
=
&
getRegisterInfo
(
)
;
MachineInstr
*
MovMI
=
0
;
unsigned
subRegIdx
[
]
=
{
SP
::
sub_even
,
SP
::
sub_odd
}
;
for
(
unsigned
i
=
0
;
i
!=
2
;
++
i
)
{
unsigned
Dst
=
TRI
->
getSubReg
(
DestReg
,
subRegIdx
[
i
]
)
;
unsigned
Src
=
TRI
->
getSubReg
(
SrcReg
,
subRegIdx
[
i
]
)
;
assert
(
Dst
&&
Src
&&
"Bad sub-register"
)
;
MovMI
=
BuildMI
(
MBB
,
I
,
DL
,
get
(
SP
::
FMOVS
)
,
Dst
)
.
addReg
(
Src
)
;
}
MovMI
->
addRegisterDefined
(
DestReg
,
TRI
)
;
if
(
KillSrc
)
MovMI
->
addRegisterKilled
(
SrcReg
,
TRI
)
;
}
}
else
llvm_unreachable
(
"Impossible reg-to-reg copy"
)
;
}
</s>


<s> unsigned RISCVTargetLowering :: ComputeNumSignBitsForTargetNode ( SDValue Op , const APInt & DemandedElts , const SelectionDAG & DAG , unsigned Depth ) const { switch ( Op . getOpcode ( ) ) { default : break ; case RISCVISD :: SELECT_CC : { unsigned Tmp = DAG . ComputeNumSignBits ( Op . getOperand ( 3 ) , DemandedElts , Depth + 1 ) ; if ( Tmp == 1 ) return 1 ; unsigned Tmp2 = DAG . ComputeNumSignBits ( Op . getOperand ( 4 ) , DemandedElts , Depth + 1 ) ; return std :: min ( Tmp , Tmp2 ) ; } case RISCVISD :: SLLW : case RISCVISD :: SRAW : case RISCVISD :: SRLW : case RISCVISD :: DIVW : case RISCVISD :: DIVUW : case RISCVISD :: REMUW : case RISCVISD :: ROLW : case RISCVISD :: RORW : case RISCVISD :: GREVW : case RISCVISD :: GORCW : case RISCVISD :: FSLW : case RISCVISD :: FSRW : case RISCVISD :: SHFLW : case RISCVISD :: UNSHFLW : case RISCVISD :: BCOMPRESSW : case RISCVISD :: BDECOMPRESSW : case RISCVISD :: FCVT_W_RTZ_RV64 : case RISCVISD :: FCVT_WU_RTZ_RV64 : return 33 ; case RISCVISD :: SHFL : case RISCVISD :: UNSHFL : { if ( Op . getValueType ( ) == MVT :: i64 && isa < ConstantSDNode > ( Op . getOperand ( 1 ) ) && ( Op . getConstantOperandVal ( 1 ) & 0x10 ) == 0 ) { unsigned Tmp = DAG . ComputeNumSignBits ( Op . getOperand ( 0 ) , Depth + 1 ) ; if ( Tmp > 32 ) return 33 ; } break ; } case RISCVISD :: VMV_X_S : if ( Op . getOperand ( 0 ) . getScalarValueSizeInBits ( ) > Subtarget . getXLen ( ) ) return 1 ; return Subtarget . getXLen ( ) - Op . getOperand ( 0 ) . getScalarValueSizeInBits ( ) + 1 ; } return 1 ; } </s>

Determine the number of bits in the operation that are sign bits .


<s>
bool
AArch64DAGToDAGISel
::
SelectInlineAsmMemoryOperand
(
const
SDValue
&
Op
,
unsigned
ConstraintID
,
std
::
vector
<
SDValue
>
&
OutOps
)
{
switch
(
ConstraintID
)
{
default
:
llvm_unreachable
(
"Unexpected asm memory constraint"
)
;
case
InlineAsm
::
Constraint_i
:
case
InlineAsm
::
Constraint_m
:
case
InlineAsm
::
Constraint_Q
:
const
TargetRegisterInfo
*
TRI
=
Subtarget
->
getRegisterInfo
(
)
;
const
TargetRegisterClass
*
TRC
=
TRI
->
getPointerRegClass
(
*
MF
)
;
SDLoc
dl
(
Op
)
;
SDValue
RC
=
CurDAG
->
getTargetConstant
(
TRC
->
getID
(
)
,
dl
,
MVT
::
i64
)
;
SDValue
NewOp
=
SDValue
(
CurDAG
->
getMachineNode
(
TargetOpcode
::
COPY_TO_REGCLASS
,
dl
,
Op
.
getValueType
(
)
,
Op
,
RC
)
,
0
)
;
OutOps
.
push_back
(
NewOp
)
;
return
false
;
}
return
true
;
}
</s>

SelectInlineAsmMemoryOperand - Select the specified address as a target addressing mode , according to the specified constraint .


<s> static bool m68k_ok_for_sibcall_p ( tree decl , tree exp ) { enum m68k_function_kind kind ; if ( CALL_EXPR_STATIC_CHAIN ( exp ) ) return false ; if ( ! VOID_TYPE_P ( TREE_TYPE ( DECL_RESULT ( cfun -> decl ) ) ) ) { rtx cfun_value ; rtx call_value ; cfun_value = FUNCTION_VALUE ( TREE_TYPE ( DECL_RESULT ( cfun -> decl ) ) , cfun -> decl ) ; call_value = FUNCTION_VALUE ( TREE_TYPE ( exp ) , decl ) ; if ( ! ( rtx_equal_p ( cfun_value , call_value ) || ( REG_P ( cfun_value ) && m68k_reg_present_p ( call_value , REGNO ( cfun_value ) ) ) ) ) return false ; } kind = m68k_get_function_kind ( current_function_decl ) ; if ( kind == m68k_fk_normal_function ) return true ; if ( decl && m68k_get_function_kind ( decl ) == kind ) return true ; return false ; } </s>


<s> bool hasFP ( const MachineFunction & MF ) const override { return false ; } </s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .


<s> static inline bool ix86_using_red_zone ( void ) { return TARGET_RED_ZONE && ! TARGET_64BIT_MS_ABI ; } </s>


<s> bool R600InstrInfo :: fitsConstReadLimitations ( const std :: vector < MachineInstr * > & MIs ) const { std :: vector < unsigned > Consts ; for ( unsigned i = 0 , n = MIs . size ( ) ; i < n ; i ++ ) { MachineInstr * MI = MIs [ i ] ; if ( ! isALUInstr ( MI -> getOpcode ( ) ) ) continue ; const SmallVectorImpl < std :: pair < MachineOperand * , int64_t > > & Srcs = getSrcs ( MI ) ; for ( unsigned j = 0 , e = Srcs . size ( ) ; j < e ; j ++ ) { std :: pair < MachineOperand * , unsigned > Src = Srcs [ j ] ; if ( Src . first -> getReg ( ) == AMDGPU :: ALU_CONST ) Consts . push_back ( Src . second ) ; if ( AMDGPU :: R600_KC0RegClass . contains ( Src . first -> getReg ( ) ) || AMDGPU :: R600_KC1RegClass . contains ( Src . first -> getReg ( ) ) ) { unsigned Index = RI . getEncodingValue ( Src . first -> getReg ( ) ) & 0xff ; unsigned Chan = RI . getHWRegChan ( Src . first -> getReg ( ) ) ; Consts . push_back ( ( Index << 2 ) | Chan ) ; } } } return fitsConstReadLimitations ( Consts ) ; } </s>

Same but using const index set instead of MI set .


<s> bool VectorElementize :: runOnMachineFunction ( MachineFunction & F ) { MRI = & F . getRegInfo ( ) ; RegInfo = TM . getRegisterInfo ( ) ; InstrInfo = TM . getInstrInfo ( ) ; VectorToScalarMap . clear ( ) ; elementize ( F ) ; if ( RemoveRedundantMoves ) while ( 1 ) { if ( copyProp ( F ) == 0 ) break ; removeDeadMoves ( F ) ; } return true ; } </s>

runOnMachineFunction - Emit the function body .


<s> std :: string LineReader :: readLine ( unsigned lineNum ) { if ( lineNum < theCurLine ) { theCurLine = 0 ; fstr . seekg ( 0 , std :: ios :: beg ) ; } while ( theCurLine < lineNum ) { fstr . getline ( buff , 500 ) ; theCurLine ++ ; } return buff ; } </s>


<s> MVT getScalarShiftAmountTy ( const DataLayout & , EVT ) const override { return MVT :: i32 ; } </s>

Return the type to use for a scalar shift opcode , given the shifted amount type .


<s> void Nios2InstPrinter :: printInst ( const MCInst * MI , raw_ostream & O , StringRef Annot , const MCSubtargetInfo & STI ) { if ( ! printAliasInstr ( MI , STI , O ) ) printInstruction ( MI , STI , O ) ; printAnnotation ( O , Annot ) ; } </s>

Print the specified MCInst to the specified raw_ostream .


<s> static bool aarch64_hard_regno_mode_ok ( unsigned regno , machine_mode mode ) { if ( GET_MODE_CLASS ( mode ) == MODE_CC ) return regno == CC_REGNUM ; if ( regno == VG_REGNUM ) return mode == DImode ; unsigned int vec_flags = aarch64_classify_vector_mode ( mode ) ; if ( vec_flags & VEC_SVE_PRED ) return PR_REGNUM_P ( regno ) ; if ( PR_REGNUM_P ( regno ) ) return 0 ; if ( regno == SP_REGNUM ) return mode == Pmode || mode == ptr_mode ; if ( regno == FRAME_POINTER_REGNUM || regno == ARG_POINTER_REGNUM ) return mode == Pmode ; if ( GP_REGNUM_P ( regno ) ) { if ( known_le ( GET_MODE_SIZE ( mode ) , 8 ) ) return true ; else if ( known_le ( GET_MODE_SIZE ( mode ) , 16 ) ) return ( regno & 1 ) == 0 ; } else if ( FP_REGNUM_P ( regno ) ) { if ( vec_flags & VEC_STRUCT ) return end_hard_regno ( mode , regno ) - 1 <= V31_REGNUM ; else return ! VECTOR_MODE_P ( mode ) || vec_flags != 0 ; } return false ; } </s>


"RegScavenger required for long branching"

"new block should be inserted for expanding unconditional branch"

"Branch offsets outside of the signed 32-bit range not supported"

Insert an unconditional indirect branch at the end of MBB to NewDestBB .


<s> void MipsSEInstrInfo :: adjustStackPtr ( unsigned SP , int64_t Amount , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { const MipsSubtarget & STI = TM . getSubtarget < MipsSubtarget > ( ) ; DebugLoc DL = I != MBB . end ( ) ? I -> getDebugLoc ( ) : DebugLoc ( ) ; unsigned ADDu = STI . isABI_N64 ( ) ? Mips :: DADDu : Mips :: ADDu ; unsigned ADDiu = STI . isABI_N64 ( ) ? Mips :: DADDiu : Mips :: ADDiu ; if ( isInt < 16 > ( Amount ) ) BuildMI ( MBB , I , DL , get ( ADDiu ) , SP ) . addReg ( SP ) . addImm ( Amount ) ; else { unsigned Reg = loadImmediate ( Amount , MBB , I , DL , nullptr ) ; BuildMI ( MBB , I , DL , get ( ADDu ) , SP ) . addReg ( SP ) . addReg ( Reg , RegState :: Kill ) ; } } </s>

Mips Mips Mips Mips Mips::DADDu Mips::ADDu Mips::DADDiu Mips::ADDiu 16


<s>
bool
ARMPassConfig
::
addPreSched2
(
)
{
if
(
getOptLevel
(
)
!=
CodeGenOpt
::
)
{
if
(
!
getARMSubtarget
(
)
.
isThumb1Only
(
)
)
{
addPass
(
createARMLoadStoreOptimizationPass
(
)
)
;
printAndVerify
(
"After ARM load / store optimizer"
)
;
}
if
(
getARMSubtarget
(
)
.
hasNEON
(
)
)
addPass
(
createExecutionDependencyFixPass
(
&
ARM
::
DPRRegClass
)
)
;
}
addPass
(
createARMExpandPseudoPass
(
)
)
;
if
(
getOptLevel
(
)
!=
CodeGenOpt
::
)
{
if
(
!
getARMSubtarget
(
)
.
isThumb1Only
(
)
)
{
if
(
getARMSubtarget
(
)
.
hasV8Ops
(
)
&&
!
getARMSubtarget
(
)
.
prefers32BitThumb
(
)
)
addPass
(
createThumb2SizeReductionPass
(
)
)
;
addPass
(
&
IfConverterID
)
;
}
}
if
(
getARMSubtarget
(
)
.
isThumb2
(
)
)
addPass
(
createThumb2ITBlockPass
(
)
)
;
return
true
;
}
</s>

This method may be implemented by targets that want to run passes after prolog-epilog insertion and before the second instruction scheduling pass .

ARM
ARM
ARM
ARM
"After ARM load / store optimizer"
ARM
ARM::DPRRegClass
ARM
ARM
ARM
ARM
ARM


<s> void ARMBaseRegisterInfo :: emitLoadConstPool ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator & MBBI , DebugLoc dl , unsigned DestReg , unsigned SubIdx , int Val , ARMCC :: CondCodes Pred , unsigned PredReg ) const { MachineFunction & MF = * MBB . getParent ( ) ; MachineConstantPool * ConstantPool = MF . getConstantPool ( ) ; const Constant * C = ConstantInt :: get ( Type :: getInt32Ty ( MF . getFunction ( ) -> getContext ( ) ) , Val ) ; unsigned Idx = ConstantPool -> getConstantPoolIndex ( C , 4 ) ; BuildMI ( MBB , MBBI , dl , TII . get ( ARM :: LDRcp ) ) . addReg ( DestReg , getDefRegState ( true ) , SubIdx ) . addConstantPoolIndex ( Idx ) . addReg ( 0 ) . addImm ( 0 ) . addImm ( Pred ) . addReg ( PredReg ) ; } </s>

emitLoadConstPool - Emits a load from constpool to materialize the specified immediate .


<s> void MipsSETargetLowering :: getOpndList ( SmallVectorImpl < SDValue > & Ops , std :: deque < std :: pair < unsigned , SDValue > > & RegsToPass , bool IsPICCall , bool GlobalOrExternal , bool InternalLinkage , CallLoweringInfo & CLI , SDValue Callee , SDValue Chain ) const { if ( IsPICCall || ! GlobalOrExternal ) { unsigned T9Reg = IsN64 ? Mips :: T9_64 : Mips :: T9 ; RegsToPass . push_front ( std :: make_pair ( T9Reg , Callee ) ) ; } else Ops . push_back ( Callee ) ; MipsTargetLowering :: getOpndList ( Ops , RegsToPass , IsPICCall , GlobalOrExternal , InternalLinkage , CLI , Callee , Chain ) ; } </s>

This function fills Ops , which is the list of operands that will later be used when a function call node is created .


<s>
void
HexagonFrameLowering
::
emitPrologue
(
MachineFunction
&
MF
)
const
{
MachineBasicBlock
&
MBB
=
MF
.
front
(
)
;
MachineFrameInfo
*
MFI
=
MF
.
getFrameInfo
(
)
;
MachineBasicBlock
::
iterator
MBBI
=
MBB
.
begin
(
)
;
const
HexagonRegisterInfo
*
QRI
=
static_cast
<
const
HexagonRegisterInfo
*
>
(
MF
.
getTarget
(
)
.
getRegisterInfo
(
)
)
;
DebugLoc
dl
=
MBBI
!=
MBB
.
end
(
)
MBBI
->
getDebugLoc
(
)
:
DebugLoc
(
)
;
determineFrameLayout
(
MF
)
;
int
NumBytes
=
(
int
)
MFI
->
getStackSize
(
)
;
MachineBasicBlock
::
iterator
InsertPt
=
MBB
.
begin
(
)
;
HexagonMachineFunctionInfo
*
FuncInfo
=
MF
.
getInfo
<
HexagonMachineFunctionInfo
>
(
)
;
const
std
::
vector
<
MachineInstr
*
>
&
AdjustRegs
=
FuncInfo
->
getAllocaAdjustInsts
(
)
;
for
(
std
::
vector
<
MachineInstr
*
>
::
const_iterator
i
=
AdjustRegs
.
begin
(
)
,
e
=
AdjustRegs
.
end
(
)
;
i
!=
e
;
++
i
)
{
MachineInstr
*
MI
=
*
i
;
assert
(
(
MI
->
getOpcode
(
)
==
Hexagon
::
ADJDYNALLOC
)
&&
"Expected adjust alloca node"
)
;
MachineOperand
&
MO
=
MI
->
getOperand
(
2
)
;
assert
(
MO
.
isImm
(
)
&&
"Expected immediate"
)
;
MO
.
setImm
(
MFI
->
getMaxCallFrameSize
(
)
)
;
}
if
(
hasFP
(
MF
)
)
{
const
int
ALLOCFRAME_MAX
=
16384
;
const
TargetInstrInfo
&
TII
=
*
MF
.
getTarget
(
)
.
getInstrInfo
(
)
;
if
(
NumBytes
>=
ALLOCFRAME_MAX
)
{
BuildMI
(
MBB
,
InsertPt
,
dl
,
TII
.
get
(
Hexagon
::
ALLOCFRAME
)
)
.
addImm
(
0
)
;
BuildMI
(
MBB
,
InsertPt
,
dl
,
TII
.
get
(
Hexagon
::
CONST32_Int_Real
)
,
HEXAGON_RESERVED_REG_1
)
.
addImm
(
NumBytes
)
;
BuildMI
(
MBB
,
InsertPt
,
dl
,
TII
.
get
(
Hexagon
::
SUB_rr
)
,
QRI
->
getStackRegister
(
)
)
.
addReg
(
QRI
->
getStackRegister
(
)
)
.
addReg
(
HEXAGON_RESERVED_REG_1
)
;
}
else
{
BuildMI
(
MBB
,
InsertPt
,
dl
,
TII
.
get
(
Hexagon
::
ALLOCFRAME
)
)
.
addImm
(
NumBytes
)
;
}
}
}
</s>

emitProlog/emitEpilog - These methods insert prolog and epilog code into the function .

Hexagon
Hexagon
Hexagon
Hexagon
Hexagon
Hexagon
Hexagon::ADJDYNALLOC
"Expected adjust alloca node"
2
"Expected immediate"
16384
Hexagon::ALLOCFRAME
0
Hexagon::CONST32_Int_Real
Hexagon::SUB_rr
Hexagon::ALLOCFRAME


<s> static int ix86_shift_rotate_cost ( const struct processor_costs * cost , enum machine_mode mode , bool constant_op1 , HOST_WIDE_INT op1_val , bool speed , bool and_in_op1 , bool shift_and_truncate , bool * skip_op0 , bool * skip_op1 ) { if ( skip_op0 ) * skip_op0 = * skip_op1 = false ; if ( GET_MODE_CLASS ( mode ) == MODE_VECTOR_INT ) { if ( mode == V16QImode || mode == V32QImode ) { int count = 11 ; if ( TARGET_XOP && mode == V16QImode ) { if ( constant_op1 ) { if ( skip_op1 ) * skip_op1 = true ; return ix86_vec_cost ( mode , cost -> sse_op + ( speed ? 2 : COSTS_N_BYTES ( GET_MODE_UNIT_SIZE ( mode ) ) ) , true ) ; } count = 3 ; } else if ( TARGET_SSSE3 ) count = 7 ; return ix86_vec_cost ( mode , cost -> sse_op * count , true ) ; } else return ix86_vec_cost ( mode , cost -> sse_op , true ) ; } if ( GET_MODE_SIZE ( mode ) > UNITS_PER_WORD ) { if ( constant_op1 ) { if ( op1_val > 32 ) return cost -> shift_const + COSTS_N_INSNS ( 2 ) ; else return cost -> shift_const * 2 ; } else { if ( and_in_op1 ) return cost -> shift_var * 2 ; else return cost -> shift_var * 6 + COSTS_N_INSNS ( 2 ) ; } } else { if ( constant_op1 ) return cost -> shift_const ; else if ( shift_and_truncate ) { if ( skip_op0 ) * skip_op0 = * skip_op1 = true ; return cost -> shift_var ; } else return cost -> shift_var ; } return cost -> shift_const ; } </s>

Return cost of shift in MODE . If CONSTANT_OP1 is true , the op1 value is known and set in OP1_VAL . AND_IN_OP1 specify in op1 is result of AND and SHIFT_AND_TRUNCATE if op1 is a result of subreg . SKIP_OP0/1 is set to true if cost of OP0/1 should be ignored .


<s> bool XCoreTargetMachine :: addInstSelector ( PassManagerBase & PM ) { PM . add ( createXCoreISelDag ( * this ) ) ; return false ; } </s>

addInstSelector - This method should install an instruction selector pass , which converts from LLVM code to machine instructions .


<s> static rtx ix86_function_arg ( cumulative_args_t cum_v , machine_mode omode , const_tree type , bool named ) { CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; machine_mode mode = omode ; HOST_WIDE_INT bytes , words ; rtx arg ; if ( ! cum -> caller && cfun -> machine -> func_type != TYPE_NORMAL ) { gcc_assert ( type != NULL_TREE ) ; if ( POINTER_TYPE_P ( type ) ) { gcc_assert ( TYPE_MODE ( type ) == Pmode ) ; arg = plus_constant ( Pmode , arg_pointer_rtx , - UNITS_PER_WORD ) ; } else { gcc_assert ( cfun -> machine -> func_type == TYPE_EXCEPTION && TREE_CODE ( type ) == INTEGER_TYPE && TYPE_MODE ( type ) == word_mode ) ; arg = gen_rtx_MEM ( word_mode , plus_constant ( Pmode , arg_pointer_rtx , - 2 * UNITS_PER_WORD ) ) ; } return arg ; } if ( ( type && POINTER_BOUNDS_TYPE_P ( type ) ) || POINTER_BOUNDS_MODE_P ( mode ) ) { if ( cum -> bnds_in_bt ) arg = NULL ; else if ( cum -> bnd_regno <= LAST_BND_REG ) arg = gen_rtx_REG ( BNDmode , cum -> bnd_regno ) ; else arg = GEN_INT ( cum -> bnd_regno - LAST_BND_REG - 1 ) ; return arg ; } if ( mode == BLKmode ) bytes = int_size_in_bytes ( type ) ; else bytes = GET_MODE_SIZE ( mode ) ; words = CEIL ( bytes , UNITS_PER_WORD ) ; if ( type && TREE_CODE ( type ) == VECTOR_TYPE ) mode = type_natural_mode ( type , cum , false ) ; if ( TARGET_64BIT ) { enum calling_abi call_abi = cum ? cum -> call_abi : ix86_abi ; if ( call_abi == MS_ABI ) arg = function_arg_ms_64 ( cum , mode , omode , named , bytes ) ; else arg = function_arg_64 ( cum , mode , omode , type , named ) ; } else arg = function_arg_32 ( cum , mode , omode , type , bytes , words ) ; if ( arg == NULL_RTX && cum -> caller ) cfun -> machine -> outgoing_args_on_stack = true ; return arg ; } </s>

Return where to put the arguments to a function . Return zero to push the argument on the stack , or a hard register in which to store the argument . MODE is the argument 's machine mode . TYPE is the data type of the argument . It is null for libcalls where that information may not be available . CUM gives information about the preceding args and about the function being called . NAMED is nonzero if this argument is a named parameter ( otherwise it is an extra parameter matching an ellipsis ) .


<s> void OutgoingValueHandler :: assignValueToReg ( Register ValVReg , const CCValAssign & VA , const EVT & VT ) { Register PhysReg = VA . getLocReg ( ) ; if ( VT == MVT :: f64 && PhysReg >= Mips :: A0 && PhysReg <= Mips :: A3 ) { const MipsSubtarget & STI = static_cast < const MipsSubtarget & > ( MIRBuilder . getMF ( ) . getSubtarget ( ) ) ; bool IsEL = STI . isLittle ( ) ; auto Unmerge = MIRBuilder . buildUnmerge ( LLT :: scalar ( 32 ) , ValVReg ) ; MIRBuilder . buildCopy ( Register ( PhysReg + ( IsEL ? 0 : 1 ) ) , Unmerge . getReg ( 0 ) ) ; MIRBuilder . buildCopy ( Register ( PhysReg + ( IsEL ? 1 : 0 ) ) , Unmerge . getReg ( 1 ) ) ; } else if ( VT == MVT :: f32 && PhysReg >= Mips :: A0 && PhysReg <= Mips :: A3 ) { MIRBuilder . buildCopy ( PhysReg , ValVReg ) ; } else { Register ExtReg = extendRegister ( ValVReg , VA ) ; MIRBuilder . buildCopy ( PhysReg , ExtReg ) ; MIB . addUse ( PhysReg , RegState :: Implicit ) ; } } </s>

The specified value has been assigned to a physical register , handle the appropriate COPY ( either to or from ) and mark any relevant uses/defines as needed .


<s> unsigned getNumFixupKinds ( ) const override { return TriCore :: NumTargetFixupKinds ; } </s>

Get the number of target specific fixup kinds .


<s> static bool arm_output_addr_const_extra ( FILE * fp , rtx x ) { if ( GET_CODE ( x ) == UNSPEC && XINT ( x , 1 ) == UNSPEC_TLS ) return arm_emit_tls_decoration ( fp , x ) ; else if ( GET_CODE ( x ) == UNSPEC && XINT ( x , 1 ) == UNSPEC_PIC_LABEL ) { char label [ 256 ] ; int labelno = INTVAL ( XVECEXP ( x , 0 , 0 ) ) ; ASM_GENERATE_INTERNAL_LABEL ( label , "LPIC" , labelno ) ; assemble_name_raw ( fp , label ) ; return TRUE ; } else if ( GET_CODE ( x ) == UNSPEC && XINT ( x , 1 ) == UNSPEC_GOTSYM_OFF ) { assemble_name ( fp , "_GLOBAL_OFFSET_TABLE_" ) ; if ( GOT_PCREL ) fputs ( "+." , fp ) ; fputs ( "-(" , fp ) ; output_addr_const ( fp , XVECEXP ( x , 0 , 0 ) ) ; fputc ( ')' , fp ) ; return TRUE ; } else if ( GET_CODE ( x ) == UNSPEC && XINT ( x , 1 ) == UNSPEC_SYMBOL_OFFSET ) { output_addr_const ( fp , XVECEXP ( x , 0 , 0 ) ) ; if ( GOT_PCREL ) fputs ( "+." , fp ) ; fputs ( "-(" , fp ) ; output_addr_const ( fp , XVECEXP ( x , 0 , 1 ) ) ; fputc ( ')' , fp ) ; return TRUE ; } else if ( GET_CODE ( x ) == CONST_VECTOR ) return arm_emit_vector_const ( fp , x ) ; return FALSE ; } </s>


Output assembly code for a specific branch instruction , appending the branch prediction flag to the opcode if appropriate .


"Cannot store this register to stack slot!"

Load the specified register of the given register class from the specified stack frame index .


<s>
char
*
aarch64_output_simd_mov_immediate
(
rtx
const_vector
,
machine_mode
mode
,
unsigned
width
)
{
bool
is_valid
;
static
char
templ
[
40
]
;
const
char
*
mnemonic
;
const
char
*
shift_op
;
unsigned
int
lane_count
=
0
;
char
element_char
;
struct
simd_immediate_info
info
=
{
NULL_RTX
,
0
,
0
,
false
,
false
}
;
is_valid
=
aarch64_simd_valid_immediate
(
const_vector
,
mode
,
false
,
&
info
)
;
gcc_assert
(
is_valid
)
;
element_char
=
sizetochar
(
info
.
element_width
)
;
lane_count
=
width
/
info
.
element_width
;
mode
=
GET_MODE_INNER
(
mode
)
;
if
(
GET_MODE_CLASS
(
mode
)
==
MODE_FLOAT
)
{
gcc_assert
(
info
.
shift
==
0
&&
!
info
.
mvn
)
;
if
(
aarch64_float_const_zero_rtx_p
(
info
.
value
)
)
info
.
value
=
GEN_INT
(
0
)
;
else
{
const
unsigned
int
buf_size
=
20
;
char
float_buf
[
buf_size
]
=
{
'\0'
}
;
real_to_decimal_for_mode
(
float_buf
,
CONST_DOUBLE_REAL_VALUE
(
info
.
value
)
,
buf_size
,
buf_size
,
1
,
mode
)
;
if
(
lane_count
==
1
)
snprintf
(
templ
,
sizeof
(
templ
)
,
"fmov\t%%d0, %s"
,
float_buf
)
;
else
snprintf
(
templ
,
sizeof
(
templ
)
,
"fmov\t%%0.%d%c, %s"
,
lane_count
,
element_char
,
float_buf
)
;
return
templ
;
}
}
mnemonic
=
info
.
mvn
"mvni"
:
"movi"
;
shift_op
=
info
.
msl
"msl"
:
"lsl"
;
gcc_assert
(
CONST_INT_P
(
info
.
value
)
)
;
if
(
lane_count
==
1
)
snprintf
(
templ
,
sizeof
(
templ
)
,
"%s\t%%d0, "
HOST_WIDE_INT_PRINT_HEX
,
mnemonic
,
UINTVAL
(
info
.
value
)
)
;
else
if
(
info
.
shift
)
snprintf
(
templ
,
sizeof
(
templ
)
,
"%s\t%%0.%d%c, "
HOST_WIDE_INT_PRINT_HEX
", %s %d"
,
mnemonic
,
lane_count
,
element_char
,
UINTVAL
(
info
.
value
)
,
shift_op
,
info
.
shift
)
;
else
snprintf
(
templ
,
sizeof
(
templ
)
,
"%s\t%%0.%d%c, "
HOST_WIDE_INT_PRINT_HEX
,
mnemonic
,
lane_count
,
element_char
,
UINTVAL
(
info
.
value
)
)
;
return
templ
;
}
</s>

Returns the string with the instruction for AdvSIMD MOVI , MVNI , ORR or BIC immediate with a CONST_VECTOR of MODE and WIDTH . WHICH selects whether to output MOVI/MVNI , ORR or BIC immediate .


<s> inline static bool classof ( const MCStreamer * streamer ) { return true ; } </s>

Methods for support type inquiry through isa , cast , and dyn_cast :


<s> static void mips_init_dfa_post_cycle_insn ( void ) { if ( TUNE_LOONGSON_2EF ) mips_ls2_init_dfa_post_cycle_insn ( ) ; } </s>

Implement TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN hook . Init data used in mips_dfa_post_advance_cycle .


<s> bool runOnMachineFunction ( MachineFunction & MF ) override { Subtarget = & MF . getSubtarget < ARMSubtarget > ( ) ; SelectionDAGISel :: runOnMachineFunction ( MF ) ; return true ; } </s>

runOnMachineFunction - Emit the function body .


<s> bool mayNeedRelaxation ( const MCInst & Inst ) const override { return false ; } </s>

Check whether the given instruction may need relaxation .


<s> virtual const TargetRegisterInfo & getRegisterInfo ( ) const { return RI ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s> bool SIInstrInfo :: isReallyTriviallyReMaterializable ( const MachineInstr & MI , AliasAnalysis * AA ) const { switch ( MI . getOpcode ( ) ) { case AMDGPU :: V_MOV_B32_e32 : case AMDGPU :: V_MOV_B32_e64 : case AMDGPU :: V_MOV_B64_PSEUDO : return true ; default : return false ; } } </s>

For instructions with opcodes for which the M_REMATERIALIZABLE flag is set , this hook lets the target specify whether the instruction is actually trivially rematerializable , taking into consideration its operands .


<s>
SDValue
MSP430TargetLowering
::
LowerOperation
(
SDValue
Op
,
SelectionDAG
&
DAG
)
const
{
switch
(
Op
.
getOpcode
(
)
)
{
case
ISD
::
SHL
:
case
ISD
::
SRL
:
case
ISD
::
SRA
:
return
LowerShifts
(
Op
,
DAG
)
;
case
ISD
::
GlobalAddress
:
return
LowerGlobalAddress
(
Op
,
DAG
)
;
case
ISD
::
BlockAddress
:
return
LowerBlockAddress
(
Op
,
DAG
)
;
case
ISD
::
ExternalSymbol
:
return
LowerExternalSymbol
(
Op
,
DAG
)
;
case
ISD
::
SETCC
:
return
LowerSETCC
(
Op
,
DAG
)
;
case
ISD
::
BR_CC
:
return
LowerBR_CC
(
Op
,
DAG
)
;
case
ISD
::
SELECT_CC
:
return
LowerSELECT_CC
(
Op
,
DAG
)
;
case
ISD
::
SIGN_EXTEND
:
return
LowerSIGN_EXTEND
(
Op
,
DAG
)
;
case
ISD
::
RETURNADDR
:
return
LowerRETURNADDR
(
Op
,
DAG
)
;
case
ISD
::
FRAMEADDR
:
return
LowerFRAMEADDR
(
Op
,
DAG
)
;
default
:
llvm_unreachable
(
"unimplemented operand"
)
;
}
}
</s>

LowerOperation - Provide custom lowering hooks for some operations .

MSP430
MSP430
ISD::SHL
ISD::SRL
ISD::SRA
ISD::GlobalAddress
ISD::BlockAddress
ISD::ExternalSymbol
ISD::SETCC
ISD::BR_CC
ISD::SELECT_CC
ISD::SIGN_EXTEND
ISD::RETURNADDR
ISD::FRAMEADDR
"unimplemented operand"


"CPUs older than z900 are not supported for -fsplit-stack"

Emit -fsplit-stack prologue , which goes before the regular function prologue .


"internal compiler error.  Incorrect shift:"


<s> static bool pdp11_modes_tieable_p ( machine_mode mode1 , machine_mode mode2 ) { return mode1 == HImode && mode2 == QImode ; } </s>


<s> bool isMachineVerifierClean ( ) const override { return false ; } </s>

Returns true if the target is expected to pass all machine verifier checks .


<s> static rtx mn10300_builtin_saveregs ( void ) { rtx offset , mem ; tree fntype = TREE_TYPE ( current_function_decl ) ; int argadj = ( ( ! stdarg_p ( fntype ) ) ? UNITS_PER_WORD : 0 ) ; alias_set_type set = get_varargs_alias_set ( ) ; if ( argadj ) offset = plus_constant ( Pmode , crtl -> args . arg_offset_rtx , argadj ) ; else offset = crtl -> args . arg_offset_rtx ; mem = gen_rtx_MEM ( SImode , crtl -> args . internal_arg_pointer ) ; set_mem_alias_set ( mem , set ) ; emit_move_insn ( mem , gen_rtx_REG ( SImode , 0 ) ) ; mem = gen_rtx_MEM ( SImode , plus_constant ( Pmode , crtl -> args . internal_arg_pointer , 4 ) ) ; set_mem_alias_set ( mem , set ) ; emit_move_insn ( mem , gen_rtx_REG ( SImode , 1 ) ) ; return copy_to_reg ( expand_binop ( Pmode , add_optab , crtl -> args . internal_arg_pointer , offset , 0 , 0 , OPTAB_LIB_WIDEN ) ) ; } </s>

Flush the argument registers to the stack for a stdarg function ; return the new argument pointer .


<s> bool WebAssemblyInstrInfo :: isReallyTriviallyReMaterializable ( const MachineInstr * MI , AliasAnalysis * AA ) const { switch ( MI -> getOpcode ( ) ) { case WebAssembly :: CONST_I32 : case WebAssembly :: CONST_I64 : case WebAssembly :: CONST_F32 : case WebAssembly :: CONST_F64 : return true ; default : return false ; } } </s>


<s> bool ARM64FrameLowering :: hasReservedCallFrame ( const MachineFunction & MF ) const { return ! MF . getFrameInfo ( ) -> hasVarSizedObjects ( ) ; } </s>

hasReservedCallFrame - Under normal circumstances , when a frame pointer is not required , we reserve argument space for call sites in the function immediately on entry to the current function .


"Instr doesn't have FrameIndex operand!"

This method must be overriden to eliminate abstract frame indices from instructions which may use them .


<s> AArch64TargetMachine :: AArch64TargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL , bool LittleEndian ) : LLVMTargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL ) , DL ( Triple ( TT ) . isOSBinFormatMachO ( ) ? "e-m:o-i64:64-i128:128-n32:64-S128" : ( LittleEndian ? "e-m:e-i64:64-i128:128-n32:64-S128" : "E-m:e-i64:64-i128:128-n32:64-S128" ) ) , TLOF ( createTLOF ( Triple ( getTargetTriple ( ) ) ) ) , Subtarget ( TT , CPU , FS , * this , LittleEndian ) , isLittle ( LittleEndian ) { initAsmInfo ( ) ; } </s>


"%qE attribute only applies to functions"

Handle an `` interrupt '' attribute ; arguments as in struct attribute_spec.handler .


<s>
const
char
*
getPassName
(
)
const
override
{
return
"PowerPC Branch Selector"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> static int stackSlotSize ( ) { return 4 ; } </s>


<s> static bool umips_build_save_restore ( mips_save_restore_fn fn , unsigned * mask , HOST_WIDE_INT * offset ) { int nregs ; unsigned int i , j ; rtx pattern , set , reg , mem ; HOST_WIDE_INT this_offset ; rtx this_base ; for ( i = 0 ; i < ARRAY_SIZE ( umips_swm_mask ) ; i ++ ) if ( ( * mask & 0xffff0000 ) == umips_swm_mask [ i ] ) break ; if ( i == ARRAY_SIZE ( umips_swm_mask ) ) return false ; nregs = ( umips_swm_encoding [ i ] & 0xf ) + ( umips_swm_encoding [ i ] >> 4 ) ; this_offset = * offset - UNITS_PER_WORD * ( nregs - 1 ) ; if ( ! UMIPS_12BIT_OFFSET_P ( this_offset ) ) return false ; pattern = gen_rtx_PARALLEL ( VOIDmode , rtvec_alloc ( nregs ) ) ; this_base = stack_pointer_rtx ; for ( j = 0 ; j < ( umips_swm_encoding [ i ] & 0xf ) ; j ++ ) { HOST_WIDE_INT offset = this_offset + j * UNITS_PER_WORD ; mem = gen_frame_mem ( SImode , plus_constant ( Pmode , this_base , offset ) ) ; unsigned int regno = ( j != 8 ) ? 16 + j : 30 ; * mask &= ~ ( 1 << regno ) ; reg = gen_rtx_REG ( SImode , regno ) ; if ( fn == mips_save_reg ) set = mips_frame_set ( mem , reg ) ; else { set = gen_rtx_SET ( reg , mem ) ; mips_add_cfa_restore ( reg ) ; } XVECEXP ( pattern , 0 , j ) = set ; } if ( umips_swm_encoding [ i ] >> 4 ) { HOST_WIDE_INT offset = this_offset + j * UNITS_PER_WORD ; * mask &= ~ ( 1 << 31 ) ; mem = gen_frame_mem ( SImode , plus_constant ( Pmode , this_base , offset ) ) ; reg = gen_rtx_REG ( SImode , 31 ) ; if ( fn == mips_save_reg ) set = mips_frame_set ( mem , reg ) ; else { set = gen_rtx_SET ( reg , mem ) ; mips_add_cfa_restore ( reg ) ; } XVECEXP ( pattern , 0 , j ) = set ; } pattern = emit_insn ( pattern ) ; if ( fn == mips_save_reg ) RTX_FRAME_RELATED_P ( pattern ) = 1 ; * offset -= UNITS_PER_WORD * nregs ; return true ; } </s>

Try to use a microMIPS LWM or SWM instruction to save or restore as many GPRs in * MASK as possible . * OFFSET is the offset from the stack pointer of the topmost save slot . Remove from * MASK all registers that were handled using LWM and SWM . Update * OFFSET so that it points to the first unused save slot .


<s> ARMBaseTargetMachine :: ARMBaseTargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL , bool isLittle ) : LLVMTargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL ) , TargetABI ( computeTargetABI ( Triple ( TT ) , CPU , Options ) ) , TLOF ( createTLOF ( Triple ( getTargetTriple ( ) ) ) ) , Subtarget ( TT , CPU , FS , * this , isLittle ) , isLittle ( isLittle ) { if ( Options . FloatABIType == FloatABI :: Default ) this -> Options . FloatABIType = Subtarget . isTargetHardFloat ( ) ? FloatABI :: Hard : FloatABI :: Soft ; } </s>


<s> bool s390_hard_regno_mode_ok ( unsigned int regno , machine_mode mode ) { switch ( REGNO_REG_CLASS ( regno ) ) { case FP_REGS : if ( REGNO_PAIR_OK ( regno , mode ) ) { if ( mode == SImode || mode == DImode ) return true ; if ( FLOAT_MODE_P ( mode ) && GET_MODE_CLASS ( mode ) != MODE_VECTOR_FLOAT ) return true ; } break ; case ADDR_REGS : if ( FRAME_REGNO_P ( regno ) && mode == Pmode ) return true ; case GENERAL_REGS : if ( REGNO_PAIR_OK ( regno , mode ) ) { if ( TARGET_ZARCH || ( mode != TFmode && mode != TCmode && mode != TDmode ) ) return true ; } break ; case CC_REGS : if ( GET_MODE_CLASS ( mode ) == MODE_CC ) return true ; break ; case ACCESS_REGS : if ( REGNO_PAIR_OK ( regno , mode ) ) { if ( mode == SImode || mode == Pmode ) return true ; } break ; default : return false ; } return false ; } </s>

Return true if it is legal to put a value with MODE into REGNO .


<s>
StringRef
getPassName
(
)
const
override
{
return
"TOY Assembly Printer"
;
}
</s>


<s> bool ARM64PassConfig :: addPreSched2 ( ) { addPass ( createARM64ExpandPseudoPass ( ) ) ; addPass ( createARM64LoadStoreOptimizationPass ( ) ) ; return true ; } </s>

This method may be implemented by targets that want to run passes after prolog-epilog insertion and before the second instruction scheduling pass .


<s> const char * AVRTargetLowering :: getTargetNodeName ( unsigned Opcode ) const { case AVRISD :: name : \ return # name switch ( Opcode ) { default : return nullptr ; NODE ( RET_FLAG ) ; NODE ( RETI_FLAG ) ; NODE ( CALL ) ; NODE ( WRAPPER ) ; NODE ( LSL ) ; NODE ( LSR ) ; NODE ( ROL ) ; NODE ( ROR ) ; NODE ( ASR ) ; NODE ( LSLLOOP ) ; NODE ( LSRLOOP ) ; NODE ( ASRLOOP ) ; NODE ( BRCOND ) ; NODE ( CMP ) ; NODE ( CMPC ) ; NODE ( TST ) ; NODE ( SELECT_CC ) ; } </s>

getTargetNodeName - This method returns the name of a target specific


<s> const uint32_t * RV16KRegisterInfo :: getCallPreservedMask ( const MachineFunction & , CallingConv :: ID ) const { return CSR_RegMask ; } </s>

Return a mask of call-preserved registers for the given calling convention on the current function .


<s> const TargetRegisterClass * getPointerRegClass ( const MachineFunction & MF , unsigned Kind = 0 ) const override { return & SystemZ :: ADDR64BitRegClass ; } </s>

getPointerRegClass - Returns a TargetRegisterClass used for pointer values .


<s> static void ix86_maybe_switch_abi ( void ) { if ( TARGET_64BIT && call_used_regs [ SI_REG ] == ( cfun -> machine -> call_abi == MS_ABI ) ) reinit_regs ( ) ; } </s>

64-bit MS and SYSV ABI have different set of call used registers . Avoid expensive re-initialization of init_regs each time we switch function context since this is needed only during RTL expansion .


<s> bool ARMFrameLowering :: hasFP ( const MachineFunction & MF ) const { const TargetRegisterInfo * RegInfo = MF . getSubtarget ( ) . getRegisterInfo ( ) ; if ( STI . isTargetIOS ( ) || STI . isTargetWatchOS ( ) ) return true ; const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; return ( ( MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) && MFI . hasCalls ( ) ) || RegInfo -> needsStackRealignment ( MF ) || MFI . hasVarSizedObjects ( ) || MFI . isFrameAddressTaken ( ) ) ; } </s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .


<s>
const
char
*
nds32_output_float_store
(
rtx
*
operands
)
{
char
buff
[
100
]
;
const
char
*
pattern
;
rtx
addr
,
addr_op0
,
addr_op1
;
int
dp
=
GET_MODE_SIZE
(
GET_MODE
(
operands
[
0
]
)
)
==
8
;
addr
=
XEXP
(
operands
[
0
]
,
0
)
;
switch
(
GET_CODE
(
addr
)
)
{
case
REG
:
pattern
=
"fs%ci\t%%1, %%0"
;
break
;
case
PLUS
:
addr_op0
=
XEXP
(
addr
,
0
)
;
addr_op1
=
XEXP
(
addr
,
1
)
;
if
(
REG_P
(
addr_op0
)
&&
REG_P
(
addr_op1
)
)
pattern
=
"fs%c\t%%1, %%0"
;
else
if
(
REG_P
(
addr_op0
)
&&
CONST_INT_P
(
addr_op1
)
)
pattern
=
"fs%ci\t%%1, %%0"
;
else
if
(
GET_CODE
(
addr_op0
)
==
MULT
&&
REG_P
(
addr_op1
)
&&
REG_P
(
XEXP
(
addr_op0
,
0
)
)
&&
CONST_INT_P
(
XEXP
(
addr_op0
,
1
)
)
)
pattern
=
"fs%c\t%%1, %%0"
;
else
gcc_unreachable
(
)
;
break
;
case
POST_MODIFY
:
addr_op0
=
XEXP
(
addr
,
0
)
;
addr_op1
=
XEXP
(
addr
,
1
)
;
if
(
REG_P
(
addr_op0
)
&&
GET_CODE
(
addr_op1
)
==
PLUS
&&
REG_P
(
XEXP
(
addr_op1
,
1
)
)
)
pattern
=
"fs%c.bi\t%%1, %%0"
;
else
if
(
REG_P
(
addr_op0
)
&&
GET_CODE
(
addr_op1
)
==
PLUS
&&
CONST_INT_P
(
XEXP
(
addr_op1
,
1
)
)
)
pattern
=
"fs%ci.bi\t%%1, %%0"
;
else
gcc_unreachable
(
)
;
break
;
case
POST_INC
:
if
(
REG_P
(
XEXP
(
addr
,
0
)
)
)
{
if
(
dp
)
pattern
=
"fs%ci.bi\t%%1, %%0, 8"
;
else
pattern
=
"fs%ci.bi\t%%1, %%0, 4"
;
}
else
gcc_unreachable
(
)
;
break
;
case
POST_DEC
:
if
(
REG_P
(
XEXP
(
addr
,
0
)
)
)
{
if
(
dp
)
pattern
=
"fs%ci.bi\t%%1, %%0, -8"
;
else
pattern
=
"fs%ci.bi\t%%1, %%0, -4"
;
}
else
gcc_unreachable
(
)
;
break
;
default
:
gcc_unreachable
(
)
;
}
sprintf
(
buff
,
pattern
,
dp
'd'
:
's'
)
;
output_asm_insn
(
buff
,
operands
)
;
return
""
;
}
</s>


<s>
bool
AMDGPUAsmPrinter
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
SetupMachineFunction
(
MF
)
;
OutStreamer
.
emitRawComment
(
Twine
(
'@'
)
+
MF
.
getName
(
)
+
Twine
(
':'
)
)
;
MCContext
&
Context
=
getObjFileLowering
(
)
.
getContext
(
)
;
const
MCSectionELF
*
ConfigSection
=
Context
.
getELFSection
(
".AMDGPU.config"
,
ELF
::
SHT_PROGBITS
,
0
,
SectionKind
::
getReadOnly
(
)
)
;
OutStreamer
.
SwitchSection
(
ConfigSection
)
;
const
AMDGPUSubtarget
&
STM
=
TM
.
getSubtarget
<
AMDGPUSubtarget
>
(
)
;
SIProgramInfo
KernelInfo
;
if
(
STM
.
getGeneration
(
)
>
AMDGPUSubtarget
::
NORTHERN_ISLANDS
)
{
getSIProgramInfo
(
KernelInfo
,
MF
)
;
EmitProgramInfoSI
(
MF
,
KernelInfo
)
;
}
else
{
EmitProgramInfoR600
(
MF
)
;
}
DisasmLines
.
clear
(
)
;
HexLines
.
clear
(
)
;
DisasmLineMaxLen
=
0
;
OutStreamer
.
SwitchSection
(
getObjFileLowering
(
)
.
getTextSection
(
)
)
;
EmitFunctionBody
(
)
;
if
(
isVerbose
(
)
)
{
const
MCSectionELF
*
CommentSection
=
Context
.
getELFSection
(
".AMDGPU.csdata"
,
ELF
::
SHT_PROGBITS
,
0
,
SectionKind
::
getReadOnly
(
)
)
;
OutStreamer
.
SwitchSection
(
CommentSection
)
;
if
(
STM
.
getGeneration
(
)
>=
AMDGPUSubtarget
::
SOUTHERN_ISLANDS
)
{
OutStreamer
.
emitRawComment
(
" Kernel info:"
,
false
)
;
OutStreamer
.
emitRawComment
(
" codeLenInByte = "
+
Twine
(
KernelInfo
.
CodeLen
)
,
false
)
;
OutStreamer
.
emitRawComment
(
" NumSgprs: "
+
Twine
(
KernelInfo
.
NumSGPR
)
,
false
)
;
OutStreamer
.
emitRawComment
(
" NumVgprs: "
+
Twine
(
KernelInfo
.
NumVGPR
)
,
false
)
;
OutStreamer
.
emitRawComment
(
" FloatMode: "
+
Twine
(
KernelInfo
.
FloatMode
)
,
false
)
;
OutStreamer
.
emitRawComment
(
" IeeeMode: "
+
Twine
(
KernelInfo
.
IEEEMode
)
,
false
)
;
OutStreamer
.
emitRawComment
(
" ScratchSize: "
+
Twine
(
KernelInfo
.
ScratchSize
)
,
false
)
;
}
else
{
R600MachineFunctionInfo
*
MFI
=
MF
.
getInfo
<
R600MachineFunctionInfo
>
(
)
;
OutStreamer
.
emitRawComment
(
Twine
(
"SQ_PGM_RESOURCES:STACK_SIZE = "
+
Twine
(
MFI
->
StackSize
)
)
)
;
}
}
if
(
STM
.
dumpCode
(
)
)
{
MF
.
dump
(
)
;
if
(
DisasmEnabled
)
{
OutStreamer
.
SwitchSection
(
Context
.
getELFSection
(
".AMDGPU.disasm"
,
ELF
::
SHT_NOTE
,
0
,
SectionKind
::
getReadOnly
(
)
)
)
;
for
(
size_t
i
=
0
;
i
<
DisasmLines
.
size
(
)
;
++
i
)
{
std
::
string
Comment
(
DisasmLineMaxLen
DisasmLines
[
i
]
.
size
(
)
,
' '
)
;
Comment
+=
" ; "
+
HexLines
[
i
]
+
"\n"
;
OutStreamer
.
EmitBytes
(
StringRef
(
DisasmLines
[
i
]
)
)
;
OutStreamer
.
EmitBytes
(
StringRef
(
Comment
)
)
;
}
}
}
return
false
;
}
</s>

runOnMachineFunction - Emit the function body .


<s>
void
MetadataStreamer
::
dump
(
StringRef
YamlString
)
const
{
errs
(
)
<<
"AMDGPU Code Object Metadata:\n"
<<
YamlString
<<
'\n'
;
}
</s>

Dump the plan to stderr ( for debugging ) .


<s> bool PatmosRegisterInfo :: isConstantPhysReg ( MCRegister PhysReg ) const { return PhysReg == Patmos :: R0 || PhysReg == Patmos :: P0 ; } </s>

Returns true if PhysReg is unallocatable and constant throughout the function .


<s> const RegisterBankInfo :: InstructionMapping & X86RegisterBankInfo :: getInstrMapping ( const MachineInstr & MI ) const { const MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ; const MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; auto Opc = MI . getOpcode ( ) ; if ( ! isPreISelGenericOpcode ( Opc ) || Opc == TargetOpcode :: G_PHI ) { const InstructionMapping & Mapping = getInstrMappingImpl ( MI ) ; if ( Mapping . isValid ( ) ) return Mapping ; } switch ( Opc ) { case TargetOpcode :: G_ADD : case TargetOpcode :: G_SUB : return getSameOperandsMapping ( MI , false ) ; break ; case TargetOpcode :: G_FADD : case TargetOpcode :: G_FSUB : case TargetOpcode :: G_FMUL : case TargetOpcode :: G_FDIV : return getSameOperandsMapping ( MI , true ) ; break ; default : break ; } unsigned NumOperands = MI . getNumOperands ( ) ; SmallVector < PartialMappingIdx , 4 > OpRegBankIdx ( NumOperands ) ; switch ( Opc ) { case TargetOpcode :: G_FPEXT : case TargetOpcode :: G_FCONSTANT : getInstrPartialMappingIdxs ( MI , MRI , true , OpRegBankIdx ) ; break ; default : getInstrPartialMappingIdxs ( MI , MRI , false , OpRegBankIdx ) ; break ; } SmallVector < const ValueMapping * , 8 > OpdsMapping ( NumOperands ) ; if ( ! getInstrValueMapping ( MI , OpRegBankIdx , OpdsMapping ) ) return getInvalidInstructionMapping ( ) ; return getInstructionMapping ( DefaultMappingID , 1 , getOperandsMapping ( OpdsMapping ) , NumOperands ) ; } </s>

Get the mapping of the different operands of MI on the register bank .


<s>
CCAssignFn
*
AArch64TargetLowering
::
CCAssignFnForCall
(
CallingConv
::
ID
CC
,
bool
IsVarArg
)
const
{
switch
(
CC
)
{
default
:
report_fatal_error
(
"Unsupported calling convention."
)
;
case
CallingConv
::
WebKit_JS
:
return
CC_AArch64_WebKit_JS
;
case
CallingConv
::
GHC
:
return
CC_AArch64_GHC
;
case
CallingConv
::
C
:
case
CallingConv
::
Fast
:
case
CallingConv
::
PreserveMost
:
case
CallingConv
::
CXX_FAST_TLS
:
case
CallingConv
::
Swift
:
if
(
Subtarget
->
isTargetWindows
(
)
&&
IsVarArg
)
return
CC_AArch64_Win64_VarArg
;
if
(
!
Subtarget
->
isTargetDarwin
(
)
)
return
CC_AArch64_AAPCS
;
if
(
!
IsVarArg
)
return
CC_AArch64_DarwinPCS
;
return
Subtarget
->
isTargetILP32
(
)
CC_AArch64_DarwinPCS_ILP32_VarArg
:
CC_AArch64_DarwinPCS_VarArg
;
case
CallingConv
::
Win64
:
return
IsVarArg
CC_AArch64_Win64_VarArg
:
CC_AArch64_AAPCS
;
case
CallingConv
::
AArch64_VectorCall
:
return
CC_AArch64_AAPCS
;
}
}
</s>

Selects the correct CCAssignFn for a given CallingConvention value .


<s>
MOS
::
Fixups
MOSMCExpr
::
getFixupKind
(
)
const
{
MOS
::
Fixups
Kind
=
MOS
::
Fixups
::
LastTargetFixupKind
;
switch
(
getKind
(
)
)
{
case
VK_MOS_IMM16
:
Kind
=
MOS
::
Imm16
;
break
;
case
VK_MOS_ADDR8
:
Kind
=
MOS
::
Addr8
;
break
;
case
VK_MOS_ADDR16_HI
:
Kind
=
MOS
::
Addr16_High
;
break
;
case
VK_MOS_ADDR16_LO
:
Kind
=
MOS
::
Addr16_Low
;
break
;
case
VK_MOS_ADDR24_BANK
:
Kind
=
MOS
::
Addr24_Bank
;
break
;
case
VK_MOS_ADDR24_SEGMENT
:
Kind
=
MOS
::
Addr24_Segment
;
break
;
case
VK_MOS_ADDR24_SEGMENT_HI
:
Kind
=
MOS
::
Addr24_Segment_High
;
break
;
case
VK_MOS_ADDR24_SEGMENT_LO
:
Kind
=
MOS
::
Addr24_Segment_Low
;
break
;
case
VK_MOS_ADDR_ASCIZ
:
Kind
=
MOS
::
AddrAsciz
;
break
;
case
VK_MOS_NONE
:
llvm_unreachable
(
"Uninitialized expression"
)
;
}
return
Kind
;
}
</s>

getFixupKind - Get the fixup kind of this expression .

MOS
MOS::Fixups
MOS
MOS::Fixups
MOS::Fixups
MOS
MOS::Imm16
MOS
MOS::Addr8
MOS
MOS::Addr16_High
MOS
MOS::Addr16_Low
MOS
MOS::Addr24_Bank
MOS
MOS::Addr24_Segment
MOS
MOS::Addr24_Segment_High
MOS
MOS::Addr24_Segment_Low
MOS
MOS::AddrAsciz
MOS
"Uninitialized expression"


<s> static bool exact_store_load_dependency ( rtx_insn * store , rtx_insn * load ) { rtx set1 , set2 ; set1 = single_set ( store ) ; if ( ! set1 ) return false ; if ( ! MEM_P ( SET_DEST ( set1 ) ) ) return false ; set2 = single_set ( load ) ; if ( ! set2 ) return false ; if ( exact_dependency_1 ( SET_DEST ( set1 ) , SET_SRC ( set2 ) ) ) return true ; return false ; } </s>

Return true if there exists exact dependency for store & load , i.e . the same memory address is used in them .


<s> iterator_range < block_iterator > blocks ( ) const override { return Region -> blocks ( ) ; } </s>

Returns a range view of the basic blocks in the region .


<s> static bool compute_fp_layout ( const_tree field , int bitpos , assign_data_t * data , int * pnregs , machine_mode * pmode ) { const int this_slotno = data -> slotno + bitpos / BITS_PER_WORD ; machine_mode mode = DECL_MODE ( field ) ; int nregs , nslots ; if ( VECTOR_TYPE_P ( TREE_TYPE ( field ) ) && mode == BLKmode ) { mode = TYPE_MODE ( TREE_TYPE ( TREE_TYPE ( field ) ) ) ; nregs = TYPE_VECTOR_SUBPARTS ( TREE_TYPE ( field ) ) ; } else if ( TREE_CODE ( TREE_TYPE ( field ) ) == COMPLEX_TYPE ) { mode = TYPE_MODE ( TREE_TYPE ( TREE_TYPE ( field ) ) ) ; nregs = 2 ; } else nregs = 1 ; nslots = CEIL_NWORDS ( nregs * GET_MODE_SIZE ( mode ) ) ; if ( nslots > SPARC_FP_ARG_MAX - this_slotno ) { nslots = SPARC_FP_ARG_MAX - this_slotno ; nregs = ( nslots * UNITS_PER_WORD ) / GET_MODE_SIZE ( mode ) ; data -> stack = 1 ; if ( nregs <= 0 ) return false ; } * pnregs = nregs ; * pmode = mode ; return true ; } </s>

A subroutine of function_arg_record_value . Compute the number and the mode of the FP registers to be assigned for FIELD . Return true if at least one FP register is assigned or false otherwise .


<s> void s390_output_split_stack_data ( rtx parm_block , rtx call_done , rtx frame_size , rtx args_size ) { rtx ops [ ] = { parm_block , call_done } ; switch_to_section ( targetm . asm_out . function_rodata_section ( current_function_decl , false ) ) ; if ( TARGET_64BIT ) output_asm_insn ( ".align\t8" , NULL ) ; else output_asm_insn ( ".align\t4" , NULL ) ; ( * targetm . asm_out . internal_label ) ( asm_out_file , "L" , CODE_LABEL_NUMBER ( parm_block ) ) ; if ( TARGET_64BIT ) { output_asm_insn ( ".quad\t%0" , & frame_size ) ; output_asm_insn ( ".quad\t%0" , & args_size ) ; output_asm_insn ( ".quad\t%1-%0" , ops ) ; } else { output_asm_insn ( ".long\t%0" , & frame_size ) ; output_asm_insn ( ".long\t%0" , & args_size ) ; output_asm_insn ( ".long\t%1-%0" , ops ) ; } switch_to_section ( current_function_section ( ) ) ; } </s>

Emit the parmblock for __morestack into .rodata section . It consists of 3 pointer size entries : - frame size - size of stack arguments - offset between parm block and __morestack return label


<s> bool MipsSEInstrInfo :: expandPostRAPseudo ( MachineBasicBlock :: iterator MI ) const { MachineBasicBlock & MBB = * MI -> getParent ( ) ; switch ( MI -> getDesc ( ) . getOpcode ( ) ) { default : return false ; case Mips :: RetRA : ExpandRetRA ( MBB , MI , Mips :: RET ) ; break ; case Mips :: BuildPairF64 : ExpandBuildPairF64 ( MBB , MI ) ; break ; case Mips :: ExtractElementF64 : ExpandExtractElementF64 ( MBB , MI ) ; break ; } MBB . erase ( MI ) ; return true ; } </s>

This function is called for all pseudo instructions that remain after register allocation .

Mips Mips Mips::RetRA Mips::RET Mips::BuildPairF64 Mips::ExtractElementF64


<s> void MipsPassConfig :: addPreEmitPass ( ) { addPass ( createMicroMipsSizeReducePass ( ) ) ; addPass ( createMipsDelaySlotFillerPass ( ) ) ; addPass ( createMipsBranchExpansion ( ) ) ; addPass ( createMipsConstantIslandPass ( ) ) ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


Control the placement of special register scavenging spill slots when allocating a stack frame .

AMDGPU SI 1 SI AMDGPU SIInstrFlags::FlatScratch SI


<s>
bool
AArch64DAGToDAGISel
::
SelectInlineAsmMemoryOperand
(
const
SDValue
&
Op
,
unsigned
ConstraintID
,
std
::
vector
<
SDValue
>
&
OutOps
)
{
switch
(
ConstraintID
)
{
default
:
llvm_unreachable
(
"Unexpected asm memory constraint"
)
;
case
InlineAsm
::
Constraint_m
:
case
InlineAsm
::
Constraint_Q
:
const
TargetRegisterInfo
*
TRI
=
Subtarget
->
getRegisterInfo
(
)
;
const
TargetRegisterClass
*
TRC
=
TRI
->
getPointerRegClass
(
*
MF
)
;
SDLoc
dl
(
Op
)
;
SDValue
RC
=
CurDAG
->
getTargetConstant
(
TRC
->
getID
(
)
,
dl
,
MVT
::
i64
)
;
SDValue
NewOp
=
SDValue
(
CurDAG
->
getMachineNode
(
TargetOpcode
::
COPY_TO_REGCLASS
,
dl
,
Op
.
getValueType
(
)
,
Op
,
RC
)
,
0
)
;
OutOps
.
push_back
(
NewOp
)
;
return
false
;
}
return
true
;
}
</s>

SelectInlineAsmMemoryOperand - Select the specified address as a target addressing mode , according to the specified constraint .


<s> rtx mcore_gen_compare_reg ( enum rtx_code code ) { rtx op0 = arch_compare_op0 ; rtx op1 = arch_compare_op1 ; rtx cc_reg = gen_rtx_REG ( CCmode , CC_REG ) ; if ( CONSTANT_P ( op1 ) && GET_CODE ( op1 ) != CONST_INT ) op1 = force_reg ( SImode , op1 ) ; switch ( code ) { case EQ : code = NE ; case NE : if ( GET_CODE ( op1 ) == CONST_INT && ! CONST_OK_FOR_K ( INTVAL ( op1 ) ) ) op1 = force_reg ( SImode , op1 ) ; break ; case LE : code = GT ; case GT : if ( GET_CODE ( op1 ) == CONST_INT ) op1 = force_reg ( SImode , op1 ) ; break ; case GE : code = LT ; case LT : if ( GET_CODE ( op1 ) == CONST_INT && INTVAL ( op1 ) != 0 && ! CONST_OK_FOR_J ( INTVAL ( op1 ) ) ) op1 = force_reg ( SImode , op1 ) ; break ; case GTU : gcc_assert ( GET_CODE ( op1 ) != CONST_INT || INTVAL ( op1 ) != 0 ) ; code = LEU ; case LEU : if ( GET_CODE ( op1 ) == CONST_INT && INTVAL ( op1 ) != 0 ) op1 = force_reg ( SImode , op1 ) ; break ; case LTU : code = GEU ; case GEU : if ( GET_CODE ( op1 ) == CONST_INT && INTVAL ( op1 ) != 0 ) op1 = force_reg ( SImode , op1 ) ; break ; default : break ; } emit_insn ( gen_rtx_SET ( VOIDmode , cc_reg , gen_rtx_fmt_ee ( code , CCmode , op0 , op1 ) ) ) ; return cc_reg ; } </s>


<s> static unsigned char riscv_class_max_nregs ( reg_class_t rclass , enum machine_mode mode ) { if ( reg_class_subset_p ( FP_REGS , rclass ) ) return riscv_hard_regno_nregs ( FP_REG_FIRST , mode ) ; if ( reg_class_subset_p ( GR_REGS , rclass ) ) return riscv_hard_regno_nregs ( GP_REG_FIRST , mode ) ; return 0 ; } </s>


<s> bool XCoreTargetLowering :: CanLowerReturn ( CallingConv :: ID CallConv , MachineFunction & MF , bool isVarArg , const SmallVectorImpl < ISD :: OutputArg > & Outs , LLVMContext & Context ) const { SmallVector < CCValAssign , 16 > RVLocs ; CCState CCInfo ( CallConv , isVarArg , MF , RVLocs , Context ) ; if ( ! CCInfo . CheckReturn ( Outs , RetCC_XCore ) ) return false ; if ( CCInfo . getNextStackOffset ( ) != 0 && isVarArg ) return false ; return true ; } </s>

This hook should be implemented to check whether the return values described by the Outs array can fit into the return registers .


<s> bool SIInstrInfo :: findCommutedOpIndices ( const MachineInstr & MI , unsigned & SrcOpIdx0 , unsigned & SrcOpIdx1 ) const { return findCommutedOpIndices ( MI . getDesc ( ) , SrcOpIdx0 , SrcOpIdx1 ) ; } </s>

Returns true iff the routine could find two commutable operands in the given machine instruction .


<s> Optional < MCFixupKind > Nios2AsmBackend :: getFixupKind ( StringRef Name ) const { return StringSwitch < Optional < MCFixupKind >> ( Name ) . Case ( "R_NIOS2_NONE" , ( MCFixupKind ) Nios2 :: fixup_Nios2_32 ) . Case ( "R_NIOS2_32" , FK_Data_4 ) . Default ( MCAsmBackend :: getFixupKind ( Name ) ) ; } </s>


<s> void TPCAsmInstCompress :: flushPendingLabels ( MCStreamer & Out ) { if ( PendingLabels . empty ( ) ) { return ; } for ( MCSymbol * Sym : PendingLabels ) { Sym -> setRedefinable ( true ) ; Out . EmitLabel ( Sym ) ; } PendingLabels . clear ( ) ; } </s>

Associate all pending labels with empty data fragments .


<s> static void arm_emit_load_exclusive ( machine_mode mode , rtx rval , rtx mem , bool acq ) { rtx ( * gen ) ( rtx , rtx ) ; if ( acq ) { switch ( mode ) { case QImode : gen = gen_arm_load_acquire_exclusiveqi ; break ; case HImode : gen = gen_arm_load_acquire_exclusivehi ; break ; case SImode : gen = gen_arm_load_acquire_exclusivesi ; break ; case DImode : gen = gen_arm_load_acquire_exclusivedi ; break ; default : gcc_unreachable ( ) ; } } else { switch ( mode ) { case QImode : gen = gen_arm_load_exclusiveqi ; break ; case HImode : gen = gen_arm_load_exclusivehi ; break ; case SImode : gen = gen_arm_load_exclusivesi ; break ; case DImode : gen = gen_arm_load_exclusivedi ; break ; default : gcc_unreachable ( ) ; } } emit_insn ( gen ( rval , mem ) ) ; } </s>

Emit the load-exclusive and store-exclusive instructions . Use acquire and release versions if necessary .


<s> void mips_push_asm_switch ( struct mips_asm_switch * asm_switch ) { mips_push_asm_switch_1 ( asm_switch , "\t" , "\n" ) ; } </s>

Wrappers around mips_push_asm_switch_1 and mips_pop_asm_switch_1 that either print a complete line or print nothing .


<s> void WebAssemblyPassConfig :: addPreRegAlloc ( ) { TargetPassConfig :: addPreRegAlloc ( ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) addPass ( createWebAssemblyStoreResults ( ) ) ; } </s>

This method may be implemented by targets that want to run passes immediately before register allocation .


<s> SDValue TeakTargetLowering :: LowerCallResult ( SDValue Chain , SDValue InGlue , CallingConv :: ID CallConv , bool isVarArg , const SmallVectorImpl < ISD :: InputArg > & Ins , const SDLoc & dl , SelectionDAG & DAG , SmallVectorImpl < SDValue > & InVals ) const { assert ( ! isVarArg && "Unsupported" ) ; SmallVector < CCValAssign , 16 > RVLocs ; CCState CCInfo ( CallConv , isVarArg , DAG . getMachineFunction ( ) , RVLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeCallResult ( Ins , RetCC_Teak ) ; for ( auto & Loc : RVLocs ) { SDValue RV = DAG . getCopyFromReg ( Chain , dl , Loc . getLocReg ( ) , Loc . getValVT ( ) , InGlue ) ; Chain = RV . getValue ( 1 ) ; InGlue = Chain . getValue ( 2 ) ; InVals . push_back ( RV ) ; } return Chain ; } </s>

LowerCallResult - Lower the result values of an ISD : :CALL into the appropriate copies out of appropriate physical registers .


<s> bool ARMBaseInstrInfo :: hasHighOperandLatency ( const InstrItineraryData * ItinData , const MachineRegisterInfo * MRI , const MachineInstr * DefMI , unsigned DefIdx , const MachineInstr * UseMI , unsigned UseIdx ) const { unsigned DDomain = DefMI -> getDesc ( ) . TSFlags & ARMII :: DomainMask ; unsigned UDomain = UseMI -> getDesc ( ) . TSFlags & ARMII :: DomainMask ; if ( Subtarget . isCortexA8 ( ) && ( DDomain == ARMII :: DomainVFP || UDomain == ARMII :: DomainVFP ) ) return true ; int Latency = computeOperandLatency ( ItinData , DefMI , DefIdx , UseMI , UseIdx ) ; if ( Latency < 0 ) Latency = getInstrLatency ( ItinData , DefMI ) ; if ( Latency <= 3 ) return false ; return DDomain == ARMII :: DomainVFP || DDomain == ARMII :: DomainNEON || UDomain == ARMII :: DomainVFP || UDomain == ARMII :: DomainNEON ; } </s>

Compute operand latency between a def of 'Reg ' and a use in the current loop .

ARM ARM ARMII::DomainMask ARMII::DomainMask ARMII::DomainVFP ARMII::DomainVFP 0 3 ARMII::DomainVFP ARMII::DomainNEON ARMII::DomainVFP ARMII::DomainNEON


<s>
bool
MipsAsmParser
::
ParseDirective
(
AsmToken
DirectiveID
)
{
StringRef
IDVal
=
DirectiveID
.
getString
(
)
;
if
(
IDVal
==
".cpload"
)
return
parseDirectiveCPLoad
(
DirectiveID
.
getLoc
(
)
)
;
if
(
IDVal
==
".dword"
)
{
parseDataDirective
(
8
,
DirectiveID
.
getLoc
(
)
)
;
return
false
;
}
if
(
IDVal
==
".ent"
)
{
Parser
.
Lex
(
)
;
return
false
;
}
if
(
IDVal
==
".end"
)
{
Parser
.
Lex
(
)
;
return
false
;
}
if
(
IDVal
==
".frame"
)
{
Parser
.
eatToEndOfStatement
(
)
;
return
false
;
}
if
(
IDVal
==
".set"
)
{
return
parseDirectiveSet
(
)
;
}
if
(
IDVal
==
".fmask"
)
{
Parser
.
eatToEndOfStatement
(
)
;
return
false
;
}
if
(
IDVal
==
".mask"
)
{
Parser
.
eatToEndOfStatement
(
)
;
return
false
;
}
if
(
IDVal
==
".nan"
)
return
parseDirectiveNaN
(
)
;
if
(
IDVal
==
".gpword"
)
{
parseDirectiveGpWord
(
)
;
return
false
;
}
if
(
IDVal
==
".gpdword"
)
{
parseDirectiveGpDWord
(
)
;
return
false
;
}
if
(
IDVal
==
".word"
)
{
parseDataDirective
(
4
,
DirectiveID
.
getLoc
(
)
)
;
return
false
;
}
if
(
IDVal
==
".option"
)
return
parseDirectiveOption
(
)
;
if
(
IDVal
==
".abicalls"
)
{
getTargetStreamer
(
)
.
emitDirectiveAbiCalls
(
)
;
if
(
Parser
.
getTok
(
)
.
isNot
(
AsmToken
::
EndOfStatement
)
)
{
Error
(
Parser
.
getTok
(
)
.
getLoc
(
)
,
"unexpected token in directive"
)
;
Parser
.
eatToEndOfStatement
(
)
;
}
return
false
;
}
if
(
IDVal
==
".cpsetup"
)
return
parseDirectiveCPSetup
(
)
;
return
true
;
}
</s>

ParseDirective - Parse a target specific assembler directive This method is deprecated , use 'parseDirective ' instead .


<s>
void
RISCVTargetELFStreamer
::
finish
(
)
{
RISCVTargetStreamer
::
finish
(
)
;
MCAssembler
&
MCA
=
getStreamer
(
)
.
getAssembler
(
)
;
const
FeatureBitset
&
Features
=
STI
.
getFeatureBits
(
)
;
RISCVABI
::
ABI
ABI
=
getTargetABI
(
)
;
unsigned
EFlags
=
MCA
.
getELFHeaderEFlags
(
)
;
if
(
Features
[
RISCV
::
FeatureStdExtC
]
)
EFlags
|=
ELF
::
EF_RISCV_RVC
;
switch
(
ABI
)
{
case
RISCVABI
::
ABI_ILP32
:
case
RISCVABI
::
ABI_LP64
:
break
;
case
RISCVABI
::
ABI_ILP32F
:
case
RISCVABI
::
ABI_LP64F
:
EFlags
|=
ELF
::
EF_RISCV_FLOAT_ABI_SINGLE
;
break
;
case
RISCVABI
::
ABI_ILP32D
:
case
RISCVABI
::
ABI_LP64D
:
EFlags
|=
ELF
::
EF_RISCV_FLOAT_ABI_DOUBLE
;
break
;
case
RISCVABI
::
ABI_ILP32E
:
EFlags
|=
ELF
::
EF_RISCV_RVE
;
break
;
case
RISCVABI
::
ABI_Unknown
:
llvm_unreachable
(
"Improperly initialised target ABI"
)
;
}
MCA
.
setELFHeaderEFlags
(
EFlags
)
;
}
</s>

finish - after all the new live ranges have been created , compute the remaining live range , and rewrite instructions to use the new registers .


<s>
StringRef
getPassName
(
)
const
override
{
return
"Hexagon VectorPrint pass"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> rtx gen_compare_reg ( enum rtx_code code , rtx x , rtx y ) { enum machine_mode mode = SELECT_CC_MODE ( code , x , y ) ; rtx cc_reg ; cc_reg = gen_rtx_REG ( mode , 61 ) ; emit_insn ( gen_rtx_SET ( VOIDmode , cc_reg , gen_rtx_COMPARE ( mode , x , y ) ) ) ; return cc_reg ; } </s>

Emit the compare insn and return the CC reg for the comparison in CMP .


<s>
unsigned
WebAssemblyInstrInfo
::
removeBranch
(
MachineBasicBlock
&
MBB
,
int
*
BytesRemoved
)
const
{
assert
(
!
BytesRemoved
&&
"code size not handled"
)
;
MachineBasicBlock
::
instr_iterator
I
=
MBB
.
instr_end
(
)
;
unsigned
Count
=
0
;
while
(
I
!=
MBB
.
instr_begin
(
)
)
{
I
;
if
(
I
->
isDebugInstr
(
)
)
continue
;
if
(
!
I
->
isTerminator
(
)
)
break
;
I
->
eraseFromParent
(
)
;
I
=
MBB
.
instr_end
(
)
;
++
Count
;
}
return
Count
;
}
</s>

Remove the branching code at the end of the specific MBB .

WebAssembly
WebAssembly
"code size not handled"
0


<s> bool hasFP ( const MachineFunction & MF ) const override { return false ; } </s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .


<s> MCSection * ARMElfTargetObjectFile :: getExplicitSectionGlobal ( const GlobalObject * GO , SectionKind SK , const TargetMachine & TM ) const { if ( isExecuteOnlyFunction ( GO , SK , TM ) ) SK = SectionKind :: getExecuteOnly ( ) ; return TargetLoweringObjectFileELF :: getExplicitSectionGlobal ( GO , SK , TM ) ; } </s>

Targets should implement this method to assign a section to globals with an explicit section specfied .


<s> bool RISCVTargetLowering :: shouldConvertFpToSat ( unsigned Op , EVT FPVT , EVT VT ) const { if ( ! isOperationLegalOrCustom ( Op , VT ) || ! FPVT . isSimple ( ) ) return false ; switch ( FPVT . getSimpleVT ( ) . SimpleTy ) { case MVT :: f16 : return Subtarget . hasStdExtZfh ( ) ; case MVT :: f32 : return Subtarget . hasStdExtF ( ) ; case MVT :: f64 : return Subtarget . hasStdExtD ( ) ; default : return false ; } } </s>

Should we generate fp_to_si_sat and fp_to_ui_sat from type FPVT to type VT from min ( max ( fptoi ) ) saturation patterns .


<s> int X86TargetLowering :: getScalingFactorCost ( const DataLayout & DL , const AddrMode & AM , Type * Ty , unsigned AS ) const { if ( isLegalAddressingMode ( DL , AM , Ty , AS ) ) return AM . Scale != 0 ; return - 1 ; } </s>

Return the cost of the scaling factor used in the addressing mode represented by AM for this target , for a load/store of the specified type .


<s> unsigned int rs6000_dbx_register_number ( unsigned int regno ) { if ( regno <= 63 || write_symbols != DWARF2_DEBUG ) return regno ; if ( regno == MQ_REGNO ) return 100 ; if ( regno == LINK_REGISTER_REGNUM ) return 108 ; if ( regno == COUNT_REGISTER_REGNUM ) return 109 ; if ( CR_REGNO_P ( regno ) ) return regno - CR0_REGNO + 86 ; if ( regno == XER_REGNO ) return 101 ; if ( ALTIVEC_REGNO_P ( regno ) ) return regno - FIRST_ALTIVEC_REGNO + 1124 ; if ( regno == VRSAVE_REGNO ) return 356 ; if ( regno == VSCR_REGNO ) return 67 ; if ( regno == SPE_ACC_REGNO ) return 99 ; if ( regno == SPEFSCR_REGNO ) return 612 ; gcc_assert ( regno >= 1200 && regno < 1232 ) ; return regno ; } </s>

Map internal gcc register numbers to DWARF2 register numbers .


<s> void fr30_setup_incoming_varargs ( CUMULATIVE_ARGS * arg_regs_used_so_far , enum machine_mode mode , tree type ATTRIBUTE_UNUSED , int * pretend_size , int second_time ATTRIBUTE_UNUSED ) { int size ; gcc_assert ( mode != BLKmode ) ; if ( targetm . calls . strict_argument_naming ( arg_regs_used_so_far ) ) arg_regs_used_so_far += fr30_num_arg_regs ( mode , type ) ; size = FR30_NUM_ARG_REGS - ( * arg_regs_used_so_far ) ; if ( size <= 0 ) return ; * pretend_size = ( size * UNITS_PER_WORD ) ; } </s>

Do any needed setup for a variadic function . We must create a register parameter block , and then copy any anonymous arguments , plus the last named argument , from registers into memory . * copying actually done in fr30_expand_prologue ( ) . ARG_REGS_USED_SO_FAR has * not * been updated for the last named argument which has type TYPE and mode MODE , and we rely on this fact .


<s> SDValue ARMSelectionDAGInfo :: EmitTargetCodeForMemmove ( SelectionDAG & DAG , const SDLoc & dl , SDValue Chain , SDValue Dst , SDValue Src , SDValue Size , unsigned Align , bool isVolatile , MachinePointerInfo DstPtrInfo , MachinePointerInfo SrcPtrInfo ) const { return EmitSpecializedLibcall ( DAG , dl , Chain , Dst , Src , Size , Align , RTLIB :: MEMMOVE ) ; } </s>

Emit target-specific code that performs a memmove .


<s> unsigned Mips16InstrInfo :: isStoreToStackSlot ( const MachineInstr & MI , int & FrameIndex ) const { return 0 ; } </s>

isStoreToStackSlot - If the specified machine instruction is a direct store to a stack slot , return the virtual or physical register number of the source reg along with the FrameIndex of the loaded stack slot .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . addRequired < LiveIntervals > ( ) ; AU . setPreservesAll ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> void frv_conditional_register_usage ( void ) { int i ; for ( i = GPR_FIRST + NUM_GPRS ; i <= GPR_LAST ; i ++ ) fixed_regs [ i ] = call_used_regs [ i ] = 1 ; for ( i = FPR_FIRST + NUM_FPRS ; i <= FPR_LAST ; i ++ ) fixed_regs [ i ] = call_used_regs [ i ] = 1 ; fixed_regs [ ICC_TEMP ] = call_used_regs [ ICC_TEMP ] = 1 ; fixed_regs [ ICR_TEMP ] = call_used_regs [ ICR_TEMP ] = 1 ; if ( TARGET_FIXED_CC ) { fixed_regs [ ICC_FIRST ] = call_used_regs [ ICC_FIRST ] = 1 ; fixed_regs [ FCC_FIRST ] = call_used_regs [ FCC_FIRST ] = 1 ; fixed_regs [ ICR_FIRST ] = call_used_regs [ ICR_FIRST ] = 1 ; fixed_regs [ FCR_FIRST ] = call_used_regs [ FCR_FIRST ] = 1 ; } if ( TARGET_FDPIC ) fixed_regs [ GPR_FIRST + 16 ] = fixed_regs [ GPR_FIRST + 17 ] = call_used_regs [ GPR_FIRST + 16 ] = call_used_regs [ GPR_FIRST + 17 ] = 0 ; if ( g_switch_value == 0 && ! flag_pic ) fixed_regs [ SDA_BASE_REG ] = call_used_regs [ SDA_BASE_REG ] = 0 ; if ( ! flag_pic ) fixed_regs [ PIC_REGNO ] = call_used_regs [ PIC_REGNO ] = 0 ; } </s>

Zero or more C statements that may conditionally modify two variables ` fixed_regs ' and ` call_used_regs ' ( both of type ` char [ ] ' ) after they have been initialized from the two preceding macros . This is necessary in case the fixed or call-clobbered registers depend on target flags . You need not define this macro if it has no work to do . If the usage of an entire class of registers depends on the target flags , you may indicate this to GCC by using this macro to modify ` fixed_regs ' and ` call_used_regs ' to 1 for each of the registers in the classes which should not be used by GCC . Also define the macro ` REG_CLASS_FROM_LETTER ' to return ` NO_REGS ' if it is called with a letter for a class that should n't be used . ( However , if this class is not included in ` GENERAL_REGS ' and all of the insn patterns whose constraints permit this class are controlled by target switches , then GCC will automatically avoid using these registers when the target switches are opposed to them . )


<s> bool nds32_use_load_post_increment ( machine_mode mode ) { return ( GET_MODE_SIZE ( mode ) <= GET_MODE_SIZE ( E_DImode ) ) ; } </s>

Function that determine whether a load postincrement is a good thing to use for a given mode .


<s> static bool rs6000_is_costly_dependence ( rtx insn , rtx next , rtx link , int cost , int distance ) { if ( rs6000_sched_costly_dep == no_dep_costly ) return false ; if ( rs6000_sched_costly_dep == all_deps_costly ) return true ; if ( rs6000_sched_costly_dep == store_to_load_dep_costly && is_load_insn ( next ) && is_store_insn ( insn ) ) return true ; if ( rs6000_sched_costly_dep == true_store_to_load_dep_costly && is_load_insn ( next ) && is_store_insn ( insn ) && ( ! link || ( int ) REG_NOTE_KIND ( link ) == 0 ) ) return true ; if ( rs6000_sched_costly_dep <= max_dep_latency && ( ( cost - distance ) >= ( int ) rs6000_sched_costly_dep ) ) return true ; return false ; } </s>

Returns whether the dependence between INSN and NEXT is considered costly by the given target .


"loadRegFromStackSlot didn't insert any code!"

restoreCalleeSavedRegisters - Issues instruction ( s ) to restore all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of load instructions via loadRegToStackSlot ( ) .


<s> void finishLayout ( MCAssembler const & Asm , MCAsmLayout & Layout ) const override { for ( auto I : Layout . getSectionOrder ( ) ) { auto & Fragments = I -> getFragmentList ( ) ; for ( auto & J : Fragments ) { switch ( J . getKind ( ) ) { default : break ; case MCFragment :: FT_Align : { auto Size = Asm . computeFragmentSize ( Layout , J ) ; for ( auto K = J . getIterator ( ) ; K != Fragments . begin ( ) && Size >= HEXAGON_PACKET_SIZE ; ) { -- K ; switch ( K -> getKind ( ) ) { default : break ; case MCFragment :: FT_Align : { Size = 0 ; break ; } case MCFragment :: FT_Relaxable : { MCContext & Context = Asm . getContext ( ) ; auto & RF = cast < MCRelaxableFragment > ( * K ) ; auto & Inst = const_cast < MCInst & > ( RF . getInst ( ) ) ; while ( Size > 0 && HexagonMCInstrInfo :: bundleSize ( Inst ) < MaxPacketSize ) { MCInst * Nop = Context . createMCInst ( ) ; Nop -> setOpcode ( Hexagon :: A2_nop ) ; Inst . addOperand ( MCOperand :: createInst ( Nop ) ) ; Size -= 4 ; if ( ! HexagonMCChecker ( Context , * MCII , * RF . getSubtargetInfo ( ) , Inst , * Context . getRegisterInfo ( ) , false ) . check ( ) ) { Inst . erase ( Inst . end ( ) - 1 ) ; Size = 0 ; } } bool Error = HexagonMCShuffle ( Context , true , * MCII , * RF . getSubtargetInfo ( ) , Inst ) ; ( void ) Error ; ReplaceInstruction ( Asm . getEmitter ( ) , RF , Inst ) ; Layout . invalidateFragmentsFrom ( & RF ) ; Size = 0 ; break ; } } } } } } } } </s>

Give backend an opportunity to finish layout after relaxation .


<s> void HexagonTargetLowering :: ReplaceNodeResults ( SDNode * N , SmallVectorImpl < SDValue > & Results , SelectionDAG & DAG ) const { if ( isHvxOperation ( N ) ) { ReplaceHvxNodeResults ( N , Results , DAG ) ; if ( ! Results . empty ( ) ) return ; } const SDLoc & dl ( N ) ; switch ( N -> getOpcode ( ) ) { case ISD :: SRL : case ISD :: SRA : case ISD :: SHL : return ; case ISD :: BITCAST : if ( N -> getValueType ( 0 ) == MVT :: i8 ) { SDValue P = getInstr ( Hexagon :: C2_tfrpr , dl , MVT :: i32 , N -> getOperand ( 0 ) , DAG ) ; SDValue T = DAG . getAnyExtOrTrunc ( P , dl , MVT :: i8 ) ; Results . push_back ( T ) ; } break ; } } </s>

ReplaceNodeResults - Replace the results of node with an illegal result type with new values built out of custom code .


Add common target configurable passes that perform LLVM IR to IR transforms following machine independent optimization .

AMDGPU AMDGPU AMDGPU AMDGPU AMDGPU AMDGPU AMDGPU AMDGPU AMDGPU AMDGPU AMDGPU R600 AMDGPU AMDGPU AMDGPU AMDGPU AMDGPU AMDGPU AMDGPU AMDGPU


<s> bool X86AsmBackend :: allowAutoPadding ( ) const { return ( AlignBoundary != Align :: None ( ) && AlignBranchType != X86 :: AlignBranchNone ) ; } </s>

Return true if this target might automatically pad instructions and thus need to emit padding enable/disable directives around sensative code .


<s> bool GCNPassConfig :: addPreISel ( ) { AMDGPUPassConfig :: addPreISel ( ) ; addPass ( & AMDGPUAnnotateKernelFeaturesID ) ; addPass ( createSinkingPass ( ) ) ; addPass ( createSITypeRewriter ( ) ) ; addPass ( createSIAnnotateControlFlowPass ( ) ) ; addPass ( createAMDGPUAnnotateUniformValues ( ) ) ; return false ; } </s>


"Lower aggregate copies/intrinsics into loops"

getPassName - Return a nice clean name for a pass .