<s> static bool arm_cirrus_insn_p ( rtx insn ) { enum attr_cirrus attr ; if ( ! insn || GET_CODE ( insn ) != INSN || GET_CODE ( PATTERN ( insn ) ) == USE || GET_CODE ( PATTERN ( insn ) ) == CLOBBER ) return 0 ; attr = get_attr_cirrus ( insn ) ; return attr != CIRRUS_NOT ; } </s>

Return TRUE if INSN is a Cirrus instruction .


<s> static rtx lxvrse_expand_builtin ( rtx target , insn_code icode , rtx * op , machine_mode tmode , machine_mode smode ) { rtx pat , addr ; op [ 1 ] = copy_to_mode_reg ( Pmode , op [ 1 ] ) ; if ( op [ 0 ] == const0_rtx ) addr = gen_rtx_MEM ( tmode , op [ 1 ] ) ; else { op [ 0 ] = copy_to_mode_reg ( Pmode , op [ 0 ] ) ; addr = gen_rtx_MEM ( smode , gen_rtx_PLUS ( Pmode , op [ 1 ] , op [ 0 ] ) ) ; } rtx discratch = gen_reg_rtx ( V2DImode ) ; rtx tiscratch = gen_reg_rtx ( TImode ) ; pat = GEN_FCN ( icode ) ( tiscratch , addr ) ; if ( ! pat ) return 0 ; emit_insn ( pat ) ; rtx temp1 ; if ( icode == CODE_FOR_vsx_lxvrbx ) { temp1 = simplify_gen_subreg ( V16QImode , tiscratch , TImode , 0 ) ; emit_insn ( gen_vsx_sign_extend_qi_v2di ( discratch , temp1 ) ) ; } else if ( icode == CODE_FOR_vsx_lxvrhx ) { temp1 = simplify_gen_subreg ( V8HImode , tiscratch , TImode , 0 ) ; emit_insn ( gen_vsx_sign_extend_hi_v2di ( discratch , temp1 ) ) ; } else if ( icode == CODE_FOR_vsx_lxvrwx ) { temp1 = simplify_gen_subreg ( V4SImode , tiscratch , TImode , 0 ) ; emit_insn ( gen_vsx_sign_extend_si_v2di ( discratch , temp1 ) ) ; } else if ( icode == CODE_FOR_vsx_lxvrdx ) discratch = simplify_gen_subreg ( V2DImode , tiscratch , TImode , 0 ) ; else gcc_unreachable ( ) ; rtx temp2 = simplify_gen_subreg ( TImode , discratch , V2DImode , 0 ) ; emit_insn ( gen_extendditi2_vector ( target , temp2 ) ) ; return target ; } </s>

Expand a builtin function that loads a scalar into a vector register with sign extension , and return the expanded rtx .


<s> void SparcDAGToDAGISel :: Select ( SDNode * N ) { SDLoc dl ( N ) ; if ( N -> isMachineOpcode ( ) ) { N -> setNodeId ( - 1 ) ; return ; } switch ( N -> getOpcode ( ) ) { default : break ; case ISD :: INLINEASM : { if ( tryInlineAsm ( N ) ) return ; break ; } case SPISD :: GLOBAL_BASE_REG : ReplaceNode ( N , getGlobalBaseReg ( ) ) ; return ; case ISD :: SDIV : case ISD :: UDIV : { if ( N -> getValueType ( 0 ) == MVT :: i64 ) break ; SDValue DivLHS = N -> getOperand ( 0 ) ; SDValue DivRHS = N -> getOperand ( 1 ) ; SDValue TopPart ; if ( N -> getOpcode ( ) == ISD :: SDIV ) { TopPart = SDValue ( CurDAG -> getMachineNode ( SP :: SRAri , dl , MVT :: i32 , DivLHS , CurDAG -> getTargetConstant ( 31 , dl , MVT :: i32 ) ) , 0 ) ; } else { TopPart = CurDAG -> getRegister ( SP :: G0 , MVT :: i32 ) ; } TopPart = CurDAG -> getCopyToReg ( CurDAG -> getEntryNode ( ) , dl , SP :: Y , TopPart , SDValue ( ) ) . getValue ( 1 ) ; unsigned Opcode = N -> getOpcode ( ) == ISD :: SDIV ? SP :: SDIVrr : SP :: UDIVrr ; CurDAG -> SelectNodeTo ( N , Opcode , MVT :: i32 , DivLHS , DivRHS , TopPart ) ; return ; } case ISD :: MULHU : case ISD :: MULHS : { SDValue MulLHS = N -> getOperand ( 0 ) ; SDValue MulRHS = N -> getOperand ( 1 ) ; unsigned Opcode = N -> getOpcode ( ) == ISD :: MULHU ? SP :: UMULrr : SP :: SMULrr ; SDNode * Mul = CurDAG -> getMachineNode ( Opcode , dl , MVT :: i32 , MVT :: i32 , MulLHS , MulRHS ) ; SDValue ResultHigh = SDValue ( Mul , 1 ) ; ReplaceUses ( SDValue ( N , 0 ) , ResultHigh ) ; CurDAG -> RemoveDeadNode ( N ) ; return ; } } SelectCode ( N ) ; } </s>

Main hook for targets to transform nodes into machine nodes .


<s> void relaxInstruction ( const MCInst & Inst , const MCSubtargetInfo & STI , MCInst & Res ) const override { } </s>

Relax the instruction in the given fragment to the next wider instruction .


<s> unsigned AArch64FrameLowering :: getWinEHFuncletFrameSize ( const MachineFunction & MF ) const { unsigned CSSize = MF . getInfo < AArch64FunctionInfo > ( ) -> getCalleeSavedStackSize ( ) ; return alignTo ( CSSize + MF . getFrameInfo ( ) . getMaxCallFrameSize ( ) , getStackAlignment ( ) ) ; } </s>

Funclets only need to account for space for the callee saved registers , as the locals are accounted for in the parent 's stack frame .


<s> static rtx nios2_unspec_offset ( rtx loc , int unspec ) { return gen_rtx_CONST ( Pmode , gen_rtx_UNSPEC ( Pmode , gen_rtvec ( 1 , loc ) , unspec ) ) ; } </s>


<s> SDValue M68kTargetLowering :: PerformDAGCombine ( SDNode * N , DAGCombinerInfo & DCI ) const { SelectionDAG & DAG = DCI . DAG ; switch ( N -> getOpcode ( ) ) { case M68kISD :: SUBX : return combineSUBX ( N , DAG ) ; case M68kISD :: ADDX : return combineADDX ( N , DAG , DCI ) ; case M68kISD :: SETCC : return combineM68kSetCC ( N , DAG , Subtarget ) ; case M68kISD :: BRCOND : return combineM68kBrCond ( N , DAG , Subtarget ) ; } return SDValue ( ) ; } </s>

This method will be invoked for all target nodes and for any target-independent nodes that the target has registered with invoke it for .


<s> static rtx altivec_expand_st_builtin ( tree exp , rtx target ATTRIBUTE_UNUSED , bool * expandedp ) { tree fndecl = TREE_OPERAND ( CALL_EXPR_FN ( exp ) , 0 ) ; unsigned int fcode = DECL_FUNCTION_CODE ( fndecl ) ; tree arg0 , arg1 ; machine_mode mode0 , mode1 ; rtx pat , op0 , op1 ; enum insn_code icode ; switch ( fcode ) { case ALTIVEC_BUILTIN_ST_INTERNAL_16qi : icode = CODE_FOR_vector_altivec_store_v16qi ; break ; case ALTIVEC_BUILTIN_ST_INTERNAL_8hi : icode = CODE_FOR_vector_altivec_store_v8hi ; break ; case ALTIVEC_BUILTIN_ST_INTERNAL_4si : icode = CODE_FOR_vector_altivec_store_v4si ; break ; case ALTIVEC_BUILTIN_ST_INTERNAL_4sf : icode = CODE_FOR_vector_altivec_store_v4sf ; break ; case ALTIVEC_BUILTIN_ST_INTERNAL_2df : icode = CODE_FOR_vector_altivec_store_v2df ; break ; case ALTIVEC_BUILTIN_ST_INTERNAL_2di : icode = CODE_FOR_vector_altivec_store_v2di ; break ; case ALTIVEC_BUILTIN_ST_INTERNAL_1ti : icode = CODE_FOR_vector_altivec_store_v1ti ; break ; default : * expandedp = false ; return NULL_RTX ; } arg0 = CALL_EXPR_ARG ( exp , 0 ) ; arg1 = CALL_EXPR_ARG ( exp , 1 ) ; op0 = expand_normal ( arg0 ) ; op1 = expand_normal ( arg1 ) ; mode0 = insn_data [ icode ] . operand [ 0 ] . mode ; mode1 = insn_data [ icode ] . operand [ 1 ] . mode ; if ( ! ( * insn_data [ icode ] . operand [ 0 ] . predicate ) ( op0 , mode0 ) ) op0 = gen_rtx_MEM ( mode0 , copy_to_mode_reg ( Pmode , op0 ) ) ; if ( ! ( * insn_data [ icode ] . operand [ 1 ] . predicate ) ( op1 , mode1 ) ) op1 = copy_to_mode_reg ( mode1 , op1 ) ; pat = GEN_FCN ( icode ) ( op0 , op1 ) ; if ( pat ) emit_insn ( pat ) ; * expandedp = true ; return NULL_RTX ; } </s>


<s> static bool nds32_address_register_rtx_p ( rtx x , bool strict ) { int regno ; if ( GET_CODE ( x ) != REG ) return false ; regno = REGNO ( x ) ; if ( strict ) return REGNO_OK_FOR_BASE_P ( regno ) ; else return true ; } </s>

Function that check if ' X ' is a valid address register . The variable 'STRICT ' is very important to make decision for register number . STRICT : true = > We are in reload pass or after reload pass . The register number should be strictly limited in general registers . STRICT : false = > Before reload pass , we are free to use any register number .


<s> rtx frv_split_cond_move ( rtx operands [ ] ) { rtx dest = operands [ 0 ] ; rtx test = operands [ 1 ] ; rtx cc_reg = operands [ 2 ] ; rtx src1 = operands [ 3 ] ; rtx src2 = operands [ 4 ] ; rtx cr_reg = operands [ 5 ] ; rtx ret ; machine_mode cr_mode = GET_MODE ( cr_reg ) ; start_sequence ( ) ; emit_insn ( gen_rtx_SET ( VOIDmode , cr_reg , gen_rtx_fmt_ee ( GET_CODE ( test ) , GET_MODE ( cr_reg ) , cc_reg , const0_rtx ) ) ) ; if ( GET_CODE ( src1 ) == CONST_INT && GET_CODE ( src2 ) == CONST_INT ) { HOST_WIDE_INT value1 = INTVAL ( src1 ) ; HOST_WIDE_INT value2 = INTVAL ( src2 ) ; if ( value1 == 0 ) { emit_move_insn ( dest , src2 ) ; emit_insn ( gen_rtx_COND_EXEC ( VOIDmode , gen_rtx_NE ( cr_mode , cr_reg , const0_rtx ) , gen_rtx_SET ( VOIDmode , dest , src1 ) ) ) ; } else if ( value2 == 0 ) { emit_move_insn ( dest , src1 ) ; emit_insn ( gen_rtx_COND_EXEC ( VOIDmode , gen_rtx_EQ ( cr_mode , cr_reg , const0_rtx ) , gen_rtx_SET ( VOIDmode , dest , src2 ) ) ) ; } else if ( IN_RANGE ( value1 , - 2048 , 2047 ) && IN_RANGE ( value2 - value1 , - 2048 , 2047 ) ) { rtx dest_si = ( ( GET_MODE ( dest ) == SImode ) ? dest : gen_rtx_SUBREG ( SImode , dest , 0 ) ) ; emit_move_insn ( dest_si , GEN_INT ( value2 - value1 ) ) ; emit_insn ( gen_rtx_COND_EXEC ( VOIDmode , gen_rtx_NE ( cr_mode , cr_reg , const0_rtx ) , gen_rtx_SET ( VOIDmode , dest_si , const0_rtx ) ) ) ; emit_insn ( gen_addsi3 ( dest_si , dest_si , src1 ) ) ; } else gcc_unreachable ( ) ; } else { if ( ! rtx_equal_p ( dest , src1 ) ) emit_insn ( gen_rtx_COND_EXEC ( VOIDmode , gen_rtx_NE ( cr_mode , cr_reg , const0_rtx ) , gen_rtx_SET ( VOIDmode , dest , src1 ) ) ) ; if ( ! rtx_equal_p ( dest , src2 ) ) emit_insn ( gen_rtx_COND_EXEC ( VOIDmode , gen_rtx_EQ ( cr_mode , cr_reg , const0_rtx ) , gen_rtx_SET ( VOIDmode , dest , src2 ) ) ) ; } ret = get_insns ( ) ; end_sequence ( ) ; return ret ; } </s>

Split a conditional move into constituent parts , returning a SEQUENCE containing all of the insns .


<s> void expand_fusion_p9_load ( rtx * operands ) { rtx tmp_reg = operands [ 0 ] ; rtx addis_value = operands [ 1 ] ; rtx target = operands [ 2 ] ; rtx orig_mem = operands [ 3 ] ; rtx new_addr , new_mem , orig_addr , offset , set , clobber , insn ; enum rtx_code plus_or_lo_sum ; machine_mode target_mode = GET_MODE ( target ) ; machine_mode extend_mode = target_mode ; machine_mode ptr_mode = Pmode ; enum rtx_code extend = UNKNOWN ; if ( GET_CODE ( orig_mem ) == FLOAT_EXTEND || GET_CODE ( orig_mem ) == ZERO_EXTEND ) { extend = GET_CODE ( orig_mem ) ; orig_mem = XEXP ( orig_mem , 0 ) ; target_mode = GET_MODE ( orig_mem ) ; } gcc_assert ( MEM_P ( orig_mem ) ) ; orig_addr = XEXP ( orig_mem , 0 ) ; plus_or_lo_sum = GET_CODE ( orig_addr ) ; gcc_assert ( plus_or_lo_sum == PLUS || plus_or_lo_sum == LO_SUM ) ; offset = XEXP ( orig_addr , 1 ) ; new_addr = gen_rtx_fmt_ee ( plus_or_lo_sum , ptr_mode , addis_value , offset ) ; new_mem = replace_equiv_address_nv ( orig_mem , new_addr , false ) ; if ( extend != UNKNOWN ) new_mem = gen_rtx_fmt_e ( extend , extend_mode , new_mem ) ; new_mem = gen_rtx_UNSPEC ( extend_mode , gen_rtvec ( 1 , new_mem ) , UNSPEC_FUSION_P9 ) ; set = gen_rtx_SET ( target , new_mem ) ; clobber = gen_rtx_CLOBBER ( VOIDmode , tmp_reg ) ; insn = gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( 2 , set , clobber ) ) ; emit_insn ( insn ) ; return ; } </s>

During the peephole2 pass , adjust and expand the insns for an extended fusion load sequence . The operands are : operands [ 0 ] register set with addis operands [ 1 ] value set via addis operands [ 2 ] target register being loaded operands [ 3 ] D-form memory reference using operands [ 0 ] . This is similar to the fusion introduced with power8 , except it scales to both loads/stores and does not require the result register to be the same as the base register . At the moment , we only do this if register set with addis is dead .


<s> static rtx_insn * frame_insn ( rtx x ) { rtx_insn * insn = emit_insn ( x ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; return insn ; } </s>

Emit the specified insn and mark it as frame related . FIXME : Rename this to emit_frame_insn .


<s>
StringRef
getPassName
(
)
const
override
{
return
"X86 Optimize Call Frame"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> TargetLowering :: ConstraintWeight PPCTargetLowering :: getSingleConstraintMatchWeight ( AsmOperandInfo & info , const char * constraint ) const { ConstraintWeight weight = CW_Invalid ; Value * CallOperandVal = info . CallOperandVal ; if ( ! CallOperandVal ) return CW_Default ; Type * type = CallOperandVal -> getType ( ) ; if ( StringRef ( constraint ) == "wc" && type -> isIntegerTy ( 1 ) ) return CW_Register ; else if ( ( StringRef ( constraint ) == "wa" || StringRef ( constraint ) == "wd" || StringRef ( constraint ) == "wf" ) && type -> isVectorTy ( ) ) return CW_Register ; else if ( StringRef ( constraint ) == "wi" && type -> isIntegerTy ( 64 ) ) return CW_Register ; else if ( StringRef ( constraint ) == "ws" && type -> isDoubleTy ( ) ) return CW_Register ; else if ( StringRef ( constraint ) == "ww" && type -> isFloatTy ( ) ) return CW_Register ; switch ( * constraint ) { default : weight = TargetLowering :: getSingleConstraintMatchWeight ( info , constraint ) ; break ; case 'b' : if ( type -> isIntegerTy ( ) ) weight = CW_Register ; break ; case 'f' : if ( type -> isFloatTy ( ) ) weight = CW_Register ; break ; case 'd' : if ( type -> isDoubleTy ( ) ) weight = CW_Register ; break ; case 'v' : if ( type -> isVectorTy ( ) ) weight = CW_Register ; break ; case 'y' : weight = CW_Register ; break ; case 'Z' : weight = CW_Memory ; break ; } return weight ; } </s>

Examine constraint string and operand type and determine a weight value .

PowerPC PPC "wc" 1 "wa" "wd" "wf" "wi" 64 "ws" "ww"


<s> static tree sparc_handle_vis_mul8x16 ( int fncode , tree inner_type , tree elts0 , tree elts1 ) { tree n_elts = NULL_TREE ; int scale ; switch ( fncode ) { case CODE_FOR_fmul8x16_vis : for ( ; elts0 && elts1 ; elts0 = TREE_CHAIN ( elts0 ) , elts1 = TREE_CHAIN ( elts1 ) ) { int val = sparc_vis_mul8x16 ( TREE_INT_CST_LOW ( TREE_VALUE ( elts0 ) ) , TREE_INT_CST_LOW ( TREE_VALUE ( elts1 ) ) ) ; n_elts = tree_cons ( NULL_TREE , build_int_cst ( inner_type , val ) , n_elts ) ; } break ; case CODE_FOR_fmul8x16au_vis : scale = TREE_INT_CST_LOW ( TREE_VALUE ( elts1 ) ) ; for ( ; elts0 ; elts0 = TREE_CHAIN ( elts0 ) ) { int val = sparc_vis_mul8x16 ( TREE_INT_CST_LOW ( TREE_VALUE ( elts0 ) ) , scale ) ; n_elts = tree_cons ( NULL_TREE , build_int_cst ( inner_type , val ) , n_elts ) ; } break ; case CODE_FOR_fmul8x16al_vis : scale = TREE_INT_CST_LOW ( TREE_VALUE ( TREE_CHAIN ( elts1 ) ) ) ; for ( ; elts0 ; elts0 = TREE_CHAIN ( elts0 ) ) { int val = sparc_vis_mul8x16 ( TREE_INT_CST_LOW ( TREE_VALUE ( elts0 ) ) , scale ) ; n_elts = tree_cons ( NULL_TREE , build_int_cst ( inner_type , val ) , n_elts ) ; } break ; default : gcc_unreachable ( ) ; } return nreverse ( n_elts ) ; } </s>

Multiply the vector elements in ELTS0 to the elements in ELTS1 as specified by FNCODE . All of the elements in ELTS0 and ELTS1 lists must be integer constants . A tree list with the results of the multiplications is returned , and each element in the list is of INNER_TYPE .


Define the ` __builtin_va_list ' type for the ABI .


Pass or return a composite value in the FPR pair REGNO and REGNO + 1 . MODE is the mode of the composite . MODE1 and OFFSET1 are the mode and byte offset for the first value , likewise MODE2 and OFFSET2 for the second value .


<s> void gen_shifty_hi_op ( int code , rtx * operands ) { int value = INTVAL ( operands [ 2 ] ) ; int max , i ; void ( * gen_fun ) ( int , int , rtx ) ; value &= 31 ; if ( value == 0 ) { emit_insn ( gen_nop ( ) ) ; return ; } gen_fun = GET_MODE ( operands [ 0 ] ) == HImode ? gen_ashift_hi : gen_ashift ; if ( code == ASHIFT ) { max = ext_shift_insns [ value ] ; for ( i = 0 ; i < max ; i ++ ) gen_fun ( code , ext_shift_amounts [ value ] [ i ] , operands [ 0 ] ) ; } else for ( i = ext_shift_insns [ value ] - 1 ; i >= 0 ; i -- ) gen_fun ( code , ext_shift_amounts [ value ] [ i ] , operands [ 0 ] ) ; } </s>

Same as above , but optimized for values where the topmost bits do n't matter .


<s> const ARMSubtarget * getSubtarget ( ) const { return Subtarget ; } </s>

getSubtarget - Return the subtarget for which this machine code is being compiled .


<s> static int power6_sched_reorder2 ( rtx_insn * * ready , int lastpos ) { int pos ; rtx load_mem , str_mem ; if ( is_store_insn ( last_scheduled_insn , & str_mem ) ) load_store_pendulum -- ; else if ( is_load_insn ( last_scheduled_insn , & load_mem ) ) load_store_pendulum ++ ; else return cached_can_issue_more ; if ( ( load_store_pendulum == 0 ) || ( lastpos <= 0 ) ) return cached_can_issue_more ; if ( load_store_pendulum == 1 ) { pos = lastpos ; while ( pos >= 0 ) { if ( is_load_insn ( ready [ pos ] , & load_mem ) ) { move_to_end_of_ready ( ready , pos , lastpos ) ; if ( ! sel_sched_p ( ) && INSN_PRIORITY_KNOWN ( ready [ lastpos ] ) ) INSN_PRIORITY ( ready [ lastpos ] ) ++ ; break ; } pos -- ; } } else if ( load_store_pendulum == - 2 ) { pos = lastpos ; while ( pos >= 0 ) { if ( is_load_insn ( ready [ pos ] , & load_mem ) && ! sel_sched_p ( ) && INSN_PRIORITY_KNOWN ( ready [ pos ] ) ) { INSN_PRIORITY ( ready [ pos ] ) ++ ; load_store_pendulum -- ; break ; } pos -- ; } } else if ( load_store_pendulum == - 1 ) { int first_store_pos = - 1 ; pos = lastpos ; while ( pos >= 0 ) { if ( is_store_insn ( ready [ pos ] , & str_mem ) ) { rtx str_mem2 ; if ( first_store_pos == - 1 ) first_store_pos = pos ; if ( is_store_insn ( last_scheduled_insn , & str_mem2 ) && adjacent_mem_locations ( str_mem , str_mem2 ) ) { move_to_end_of_ready ( ready , pos , lastpos ) ; if ( ! sel_sched_p ( ) && INSN_PRIORITY_KNOWN ( ready [ lastpos ] ) ) INSN_PRIORITY ( ready [ lastpos ] ) ++ ; first_store_pos = - 1 ; break ; } ; } pos -- ; } if ( first_store_pos >= 0 ) { move_to_end_of_ready ( ready , first_store_pos , lastpos ) ; if ( ! sel_sched_p ( ) && INSN_PRIORITY_KNOWN ( ready [ lastpos ] ) ) INSN_PRIORITY ( ready [ lastpos ] ) ++ ; } } else if ( load_store_pendulum == 2 ) { pos = lastpos ; while ( pos >= 0 ) { if ( is_store_insn ( ready [ pos ] , & str_mem ) && ! sel_sched_p ( ) && INSN_PRIORITY_KNOWN ( ready [ pos ] ) ) { INSN_PRIORITY ( ready [ pos ] ) ++ ; load_store_pendulum ++ ; break ; } pos -- ; } } return cached_can_issue_more ; } </s>

Do Power6 specific sched_reorder2 reordering of ready list .


<s> static void rs6000_darwin64_record_arg_flush ( CUMULATIVE_ARGS * cum , HOST_WIDE_INT bitpos , rtx rvec [ ] , int * k ) { machine_mode mode ; unsigned int regno ; unsigned int startbit , endbit ; int this_regno , intregs , intoffset ; rtx reg ; if ( cum -> intoffset == - 1 ) return ; intoffset = cum -> intoffset ; cum -> intoffset = - 1 ; if ( intoffset % BITS_PER_WORD != 0 ) { unsigned int bits = BITS_PER_WORD - intoffset % BITS_PER_WORD ; if ( ! int_mode_for_size ( bits , 0 ) . exists ( & mode ) ) { intoffset = ROUND_DOWN ( intoffset , BITS_PER_WORD ) ; mode = word_mode ; } } else mode = word_mode ; startbit = ROUND_DOWN ( intoffset , BITS_PER_WORD ) ; endbit = ROUND_UP ( bitpos , BITS_PER_WORD ) ; intregs = ( endbit - startbit ) / BITS_PER_WORD ; this_regno = cum -> words + intoffset / BITS_PER_WORD ; if ( intregs > 0 && intregs > GP_ARG_NUM_REG - this_regno ) cum -> use_stack = 1 ; intregs = MIN ( intregs , GP_ARG_NUM_REG - this_regno ) ; if ( intregs <= 0 ) return ; intoffset /= BITS_PER_UNIT ; do { regno = GP_ARG_MIN_REG + this_regno ; reg = gen_rtx_REG ( mode , regno ) ; rvec [ ( * k ) ++ ] = gen_rtx_EXPR_LIST ( VOIDmode , reg , GEN_INT ( intoffset ) ) ; this_regno += 1 ; intoffset = ( intoffset | ( UNITS_PER_WORD - 1 ) ) + 1 ; mode = word_mode ; intregs -= 1 ; } while ( intregs > 0 ) ; } </s>

A subroutine of rs6000_darwin64_record_arg . Assign the bits of the structure between cum- > intoffset and bitpos to integer registers .


<s> fma_forest :: fma_forest ( func_fma_steering * fma_steer , fma_root_node * fma_root , int id ) { memset ( this , 0 , sizeof ( * this ) ) ; this -> m_globals = fma_steer ; this -> m_roots = new std :: list < fma_root_node * > ; this -> m_roots -> push_back ( fma_root ) ; this -> m_id = id ; } </s>


<s> void PIC16RegisterInfo :: emitEpilogue ( MachineFunction & MF , MachineBasicBlock & MBB ) const { } </s>


<s> static machine_mode aarch64_preferred_simd_mode ( scalar_mode mode ) { if ( TARGET_SVE && aarch64_cmp_autovec_modes ( VNx16QImode , V16QImode ) ) return aarch64_full_sve_mode ( mode ) . else_mode ( word_mode ) ; if ( TARGET_SIMD ) return aarch64_vq_mode ( mode ) . else_mode ( word_mode ) ; return word_mode ; } </s>

Return 128-bit container as the preferred SIMD mode for MODE .


<s>
bool
SILoadStoreOptimizer
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
if
(
skipFunction
(
MF
.
getFunction
(
)
)
)
return
false
;
STM
=
&
MF
.
getSubtarget
<
GCNSubtarget
>
(
)
;
if
(
!
STM
->
loadStoreOptEnabled
(
)
)
return
false
;
TII
=
STM
->
getInstrInfo
(
)
;
TRI
=
&
TII
->
getRegisterInfo
(
)
;
MRI
=
&
MF
.
getRegInfo
(
)
;
AA
=
&
getAnalysis
<
AAResultsWrapperPass
>
(
)
.
getAAResults
(
)
;
assert
(
MRI
->
isSSA
(
)
&&
"Must be run on SSA"
)
;
LLVM_DEBUG
(
dbgs
(
)
<<
"Running SILoadStoreOptimizer\n"
)
;
bool
Modified
=
false
;
for
(
MachineBasicBlock
&
MBB
:
MF
)
{
std
::
list
<
std
::
list
<
CombineInfo
>
>
MergeableInsts
;
Modified
|=
collectMergeableInsts
(
MBB
,
MergeableInsts
)
;
do
{
OptimizeAgain
=
false
;
Modified
|=
optimizeBlock
(
MergeableInsts
)
;
}
while
(
OptimizeAgain
)
;
}
return
Modified
;
}
</s>

runOnMachineFunction - Emit the function body .

AMDGPU
SI
"Must be run on SSA"
"Running SILoadStoreOptimizer\n"


<s> void X86FrameLowering :: emitSPUpdate ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator & MBBI , int64_t NumBytes , bool InEpilogue ) const { bool isSub = NumBytes < 0 ; uint64_t Offset = isSub ? - NumBytes : NumBytes ; uint64_t Chunk = ( 1LL << 31 ) - 1 ; DebugLoc DL = MBB . findDebugLoc ( MBBI ) ; while ( Offset ) { if ( Offset > Chunk ) { unsigned Reg = 0 ; if ( isSub && ! isEAXLiveIn ( * MBB . getParent ( ) ) ) Reg = ( unsigned ) ( Is64Bit ? X86 :: RAX : X86 :: EAX ) ; else Reg = findDeadCallerSavedReg ( MBB , MBBI , TRI , Is64Bit ) ; if ( Reg ) { unsigned Opc = Is64Bit ? X86 :: MOV64ri : X86 :: MOV32ri ; BuildMI ( MBB , MBBI , DL , TII . get ( Opc ) , Reg ) . addImm ( Offset ) ; Opc = isSub ? getSUBrrOpcode ( Is64Bit ) : getADDrrOpcode ( Is64Bit ) ; MachineInstr * MI = BuildMI ( MBB , MBBI , DL , TII . get ( Opc ) , StackPtr ) . addReg ( StackPtr ) . addReg ( Reg ) ; MI -> getOperand ( 3 ) . setIsDead ( ) ; Offset = 0 ; continue ; } } uint64_t ThisVal = std :: min ( Offset , Chunk ) ; if ( ThisVal == ( Is64Bit ? 8 : 4 ) ) { unsigned Reg = isSub ? ( unsigned ) ( Is64Bit ? X86 :: RAX : X86 :: EAX ) : findDeadCallerSavedReg ( MBB , MBBI , TRI , Is64Bit ) ; if ( Reg ) { unsigned Opc = isSub ? ( Is64Bit ? X86 :: PUSH64r : X86 :: PUSH32r ) : ( Is64Bit ? X86 :: POP64r : X86 :: POP32r ) ; MachineInstr * MI = BuildMI ( MBB , MBBI , DL , TII . get ( Opc ) ) . addReg ( Reg , getDefRegState ( ! isSub ) | getUndefRegState ( isSub ) ) ; if ( isSub ) MI -> setFlag ( MachineInstr :: FrameSetup ) ; else MI -> setFlag ( MachineInstr :: FrameDestroy ) ; Offset -= ThisVal ; continue ; } } MachineInstrBuilder MI = BuildStackAdjustment ( MBB , MBBI , DL , isSub ? - ThisVal : ThisVal , InEpilogue ) ; if ( isSub ) MI . setMIFlag ( MachineInstr :: FrameSetup ) ; else MI . setMIFlag ( MachineInstr :: FrameDestroy ) ; Offset -= ThisVal ; } } </s>

Emit a series of instructions to increment / decrement the stack pointer by a constant value .


<s> static unsigned getReturnSaveOffset ( bool isPPC64 , bool isDarwinABI ) { if ( isDarwinABI ) return isPPC64 ? 16 : 8 ; return isPPC64 ? 16 : 4 ; } </s>

getReturnSaveOffset - Return the previous frame offset to save the return address .


<s> virtual MVT getShiftAmountTy ( EVT LHSTy ) const { return MVT :: i32 ; } </s>

Returns the type for the shift amount of a shift opcode .


<s>
bool
ECLairAsmParser
::
ParseInstruction
(
ParseInstructionInfo
&
Info
,
StringRef
Name
,
SMLoc
NameLoc
,
OperandVector
&
Operands
)
{
Operands
.
push_back
(
ECLairOperand
::
createToken
(
Name
,
NameLoc
)
)
;
if
(
getLexer
(
)
.
is
(
AsmToken
::
EndOfStatement
)
)
return
false
;
if
(
parseOperand
(
Operands
)
)
return
true
;
while
(
getLexer
(
)
.
is
(
AsmToken
::
Comma
)
)
{
getLexer
(
)
.
Lex
(
)
;
if
(
parseOperand
(
Operands
)
)
return
true
;
}
if
(
getLexer
(
)
.
isNot
(
AsmToken
::
EndOfStatement
)
)
{
SMLoc
Loc
=
getLexer
(
)
.
getLoc
(
)
;
getParser
(
)
.
eatToEndOfStatement
(
)
;
return
Error
(
Loc
,
"unexpected token"
)
;
}
getParser
(
)
.
Lex
(
)
;
return
false
;
}
</s>

ParseInstruction - Parse one assembly instruction .

ECLair
ECLair
ECLairOperand::createToken
"unexpected token"


<s> MachineInstr * AArch64InstrInfo :: foldMemoryOperandImpl ( MachineFunction & MF , MachineInstr & MI , ArrayRef < unsigned > Ops , MachineBasicBlock :: iterator InsertPt , int FrameIndex , LiveIntervals * LIS ) const { if ( MI . isCopy ( ) ) { unsigned DstReg = MI . getOperand ( 0 ) . getReg ( ) ; unsigned SrcReg = MI . getOperand ( 1 ) . getReg ( ) ; if ( SrcReg == AArch64 :: SP && TargetRegisterInfo :: isVirtualRegister ( DstReg ) ) { MF . getRegInfo ( ) . constrainRegClass ( DstReg , & AArch64 :: GPR64RegClass ) ; return nullptr ; } if ( DstReg == AArch64 :: SP && TargetRegisterInfo :: isVirtualRegister ( SrcReg ) ) { MF . getRegInfo ( ) . constrainRegClass ( SrcReg , & AArch64 :: GPR64RegClass ) ; return nullptr ; } } return nullptr ; } </s>

foldMemoryOperand - Same as the previous version except it allows folding of any load and store from / to any address , not just from a specific stack slot .


<s> void SystemZHazardRecognizer :: copyState ( SystemZHazardRecognizer * Incoming ) { CurrGroupSize = Incoming -> CurrGroupSize ; LLVM_DEBUG ( CurGroupDbg = Incoming -> CurGroupDbg ; ) ; ProcResourceCounters = Incoming -> ProcResourceCounters ; CriticalResourceIdx = Incoming -> CriticalResourceIdx ; LastFPdOpCycleIdx = Incoming -> LastFPdOpCycleIdx ; GrpCount = Incoming -> GrpCount ; } </s>

Copy counters from end of single predecessor .


Function to tell the preprocessor about the defines for the current target .


<s> static rtx aarch64_gen_compare_reg_maybe_ze ( RTX_CODE code , rtx x , rtx y , machine_mode y_mode ) { if ( y_mode == E_QImode || y_mode == E_HImode ) { if ( CONST_INT_P ( y ) ) y = GEN_INT ( INTVAL ( y ) & GET_MODE_MASK ( y_mode ) ) ; else { rtx t , cc_reg ; machine_mode cc_mode ; t = gen_rtx_ZERO_EXTEND ( SImode , y ) ; t = gen_rtx_COMPARE ( CC_SWPmode , t , x ) ; cc_mode = CC_SWPmode ; cc_reg = gen_rtx_REG ( cc_mode , CC_REGNUM ) ; emit_set_insn ( cc_reg , t ) ; return cc_reg ; } } return aarch64_gen_compare_reg ( code , x , y ) ; } </s>

Similarly , but maybe zero-extend Y if Y_MODE < SImode .


<s> static void mep_rewrite_mulsi3 ( rtx_insn * insn , rtx dest , rtx src1 , rtx src2 ) { rtx lo , pattern ; lo = gen_rtx_REG ( SImode , LO_REGNO ) ; if ( dest ) pattern = gen_mulsi3r ( lo , dest , copy_rtx ( dest ) , mep_mulr_source ( insn , dest , src1 , src2 ) ) ; else pattern = gen_mulsi3_lo ( lo , src1 , src2 ) ; mep_rewrite_mult ( insn , pattern ) ; } </s>

Subroutine of mep_reuse_lo_p . Rewrite instruction INSN so that it calculates SRC1 * SRC2 and stores the result in $ lo . Also make it store the result in DEST if nonnull .


<s> int frv_function_arg_boundary ( enum machine_mode mode ATTRIBUTE_UNUSED , tree type ATTRIBUTE_UNUSED ) { return BITS_PER_WORD ; } </s>

If defined , a C expression that gives the alignment boundary , in bits , of an argument with the specified mode and type . If it is not defined , ` PARM_BOUNDARY ' is used for all arguments .


<s> bool ix86_hardreg_mov_ok ( rtx dst , rtx src ) { if ( REG_P ( dst ) && HARD_REGISTER_P ( dst ) && ! REG_P ( src ) && ! MEM_P ( src ) && ! x86_64_immediate_operand ( src , GET_MODE ( dst ) ) && ix86_class_likely_spilled_p ( REGNO_REG_CLASS ( REGNO ( dst ) ) ) && ! reload_completed ) return false ; return true ; } </s>

Return true if a set of DST by the expression SRC should be allowed . This prevents complex sets of likely_spilled hard regs before reload .


<s> static rtx generate_set_vrsave ( rtx reg , rs6000_stack_t * info , int epiloguep ) { int nclobs , i ; rtx insn , clobs [ TOTAL_ALTIVEC_REGS + 1 ] ; rtx vrsave = gen_rtx_REG ( SImode , VRSAVE_REGNO ) ; clobs [ 0 ] = gen_rtx_SET ( vrsave , gen_rtx_UNSPEC_VOLATILE ( SImode , gen_rtvec ( 2 , reg , vrsave ) , UNSPECV_SET_VRSAVE ) ) ; nclobs = 1 ; for ( i = FIRST_ALTIVEC_REGNO ; i <= LAST_ALTIVEC_REGNO ; ++ i ) if ( info -> vrsave_mask & ALTIVEC_REG_BIT ( i ) ) { if ( ! epiloguep || call_used_or_fixed_reg_p ( i ) ) clobs [ nclobs ++ ] = gen_hard_reg_clobber ( V4SImode , i ) ; else { rtx reg = gen_rtx_REG ( V4SImode , i ) ; clobs [ nclobs ++ ] = gen_rtx_SET ( reg , gen_rtx_UNSPEC ( V4SImode , gen_rtvec ( 1 , reg ) , 27 ) ) ; } } insn = gen_rtx_PARALLEL ( VOIDmode , rtvec_alloc ( nclobs ) ) ; for ( i = 0 ; i < nclobs ; ++ i ) XVECEXP ( insn , 0 , i ) = clobs [ i ] ; return insn ; } </s>

Returns an insn that has a vrsave set operation with the appropriate CLOBBERs .


<s> static int bfin_arg_partial_bytes ( cumulative_args_t cum , machine_mode mode , tree type ATTRIBUTE_UNUSED , bool named ATTRIBUTE_UNUSED ) { int bytes = ( mode == BLKmode ) ? int_size_in_bytes ( type ) : GET_MODE_SIZE ( mode ) ; int bytes_left = get_cumulative_args ( cum ) -> nregs * UNITS_PER_WORD ; if ( bytes == - 1 ) return 0 ; if ( bytes_left == 0 ) return 0 ; if ( bytes > bytes_left ) return bytes_left ; return 0 ; } </s>

For an arg passed partly in registers and partly in memory , this is the number of bytes passed in registers . For args passed entirely in registers or entirely in memory , zero . Refer VDSP C Compiler manual , our ABI . First 3 words are in registers . So , if a an argument is larger than the registers available , it will span the register and stack .


<s> static inline void desc_abi ( unsigned char abi __attribute__ ( ( unused ) ) , unsigned char context __attribute__ ( ( unused ) ) , struct unw_state_record * sr __attribute__ ( ( unused ) ) ) { } </s>


<s> int easy_altivec_constant ( rtx op , machine_mode mode ) { unsigned step , copies ; if ( mode == VOIDmode ) mode = GET_MODE ( op ) ; else if ( mode != GET_MODE ( op ) ) return 0 ; if ( mode == V2DFmode ) return zero_constant ( op , mode ) ? 8 : 0 ; else if ( mode == V2DImode ) { if ( ! CONST_INT_P ( CONST_VECTOR_ELT ( op , 0 ) ) || ! CONST_INT_P ( CONST_VECTOR_ELT ( op , 1 ) ) ) return 0 ; if ( zero_constant ( op , mode ) ) return 8 ; if ( INTVAL ( CONST_VECTOR_ELT ( op , 0 ) ) == - 1 && INTVAL ( CONST_VECTOR_ELT ( op , 1 ) ) == - 1 ) return 8 ; return 0 ; } else if ( mode == V1TImode ) return 0 ; step = GET_MODE_NUNITS ( mode ) / 4 ; copies = 1 ; if ( vspltis_constant ( op , step , copies ) ) return 4 ; if ( step == 1 ) copies <<= 1 ; else step >>= 1 ; if ( vspltis_constant ( op , step , copies ) ) return 2 ; if ( step == 1 ) copies <<= 1 ; else step >>= 1 ; if ( vspltis_constant ( op , step , copies ) ) return 1 ; if ( vspltis_shifted ( op ) != 0 ) return GET_MODE_SIZE ( GET_MODE_INNER ( mode ) ) ; return 0 ; } </s>

Return true if OP is of the given MODE and can be synthesized with a vspltisb , vspltish or vspltisw .


<s> bool save_reg_p ( int reg ) { if ( reg == RS6000_PIC_OFFSET_TABLE_REGNUM && ! TARGET_SINGLE_PIC_BASE ) { if ( crtl -> calls_eh_return && ( ( DEFAULT_ABI == ABI_V4 && flag_pic ) || ( DEFAULT_ABI == ABI_DARWIN && flag_pic ) || ( TARGET_TOC && TARGET_MINIMAL_TOC ) ) ) return true ; if ( TARGET_TOC && TARGET_MINIMAL_TOC && ! constant_pool_empty_p ( ) ) return true ; if ( DEFAULT_ABI == ABI_V4 && ( flag_pic == 1 || ( flag_pic && TARGET_SECURE_PLT ) ) && df_regs_ever_live_p ( RS6000_PIC_OFFSET_TABLE_REGNUM ) ) return true ; if ( DEFAULT_ABI == ABI_DARWIN && flag_pic && crtl -> uses_pic_offset_table ) return true ; } return ! call_used_or_fixed_reg_p ( reg ) && df_regs_ever_live_p ( reg ) ; } </s>

Determine whether the REG is really used .


<s> TargetTransformInfo HexagonTargetMachine :: getTargetTransformInfo ( const Function & F ) { return TargetTransformInfo ( HexagonTTIImpl ( this , F ) ) ; } </s>

Get a TargetTransformInfo implementation for the target .


<s> bool mprocFrameLowering :: spillCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo * TRI ) const { return true ; } </s>

spillCalleeSavedRegisters - Issues instruction ( s ) to spill all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of store instructions via storeRegToStackSlot ( ) .


<s> void mips_emit_binary ( enum rtx_code code , rtx target , rtx op0 , rtx op1 ) { emit_insn ( gen_rtx_SET ( VOIDmode , target , gen_rtx_fmt_ee ( code , GET_MODE ( target ) , op0 , op1 ) ) ) ; } </s>

Emit an instruction of the form ( set TARGET ( CODE OP0 OP1 ) ) .


<s> void AMDGPUAsmPrinter :: emitFunctionBodyStart ( ) { const SIMachineFunctionInfo & MFI = * MF -> getInfo < SIMachineFunctionInfo > ( ) ; if ( ! MFI . isEntryFunction ( ) ) return ; const GCNSubtarget & STM = MF -> getSubtarget < GCNSubtarget > ( ) ; const Function & F = MF -> getFunction ( ) ; if ( ( STM . isMesaKernel ( F ) || isHsaAbiVersion2 ( getGlobalSTI ( ) ) ) && ( F . getCallingConv ( ) == CallingConv :: AMDGPU_KERNEL || F . getCallingConv ( ) == CallingConv :: SPIR_KERNEL ) ) { amd_kernel_code_t KernelCode ; getAmdKernelCode ( KernelCode , CurrentProgramInfo , * MF ) ; getTargetStreamer ( ) -> EmitAMDKernelCodeT ( KernelCode ) ; } if ( STM . isAmdHsaOS ( ) ) HSAMetadataStream -> emitKernel ( * MF , CurrentProgramInfo ) ; } </s>

Targets can override this to emit stuff before the first basic block in the function .


<s> bool AMDGPUInstructionSelector :: select ( MachineInstr & I , CodeGenCoverage & CoverageInfo ) const { if ( I . isPHI ( ) ) return selectPHI ( I ) ; if ( ! isPreISelGenericOpcode ( I . getOpcode ( ) ) ) { if ( I . isCopy ( ) ) return selectCOPY ( I ) ; return true ; } switch ( I . getOpcode ( ) ) { case TargetOpcode :: G_AND : case TargetOpcode :: G_OR : case TargetOpcode :: G_XOR : if ( selectG_AND_OR_XOR ( I ) ) return true ; return selectImpl ( I , CoverageInfo ) ; case TargetOpcode :: G_ADD : case TargetOpcode :: G_SUB : if ( selectG_ADD_SUB ( I ) ) return true ; LLVM_FALLTHROUGH ; default : return selectImpl ( I , CoverageInfo ) ; case TargetOpcode :: G_INTTOPTR : case TargetOpcode :: G_BITCAST : return selectCOPY ( I ) ; case TargetOpcode :: G_CONSTANT : case TargetOpcode :: G_FCONSTANT : return selectG_CONSTANT ( I ) ; case TargetOpcode :: G_EXTRACT : return selectG_EXTRACT ( I ) ; case TargetOpcode :: G_MERGE_VALUES : case TargetOpcode :: G_BUILD_VECTOR : case TargetOpcode :: G_CONCAT_VECTORS : return selectG_MERGE_VALUES ( I ) ; case TargetOpcode :: G_UNMERGE_VALUES : return selectG_UNMERGE_VALUES ( I ) ; case TargetOpcode :: G_GEP : return selectG_GEP ( I ) ; case TargetOpcode :: G_IMPLICIT_DEF : return selectG_IMPLICIT_DEF ( I ) ; case TargetOpcode :: G_INSERT : return selectG_INSERT ( I ) ; case TargetOpcode :: G_INTRINSIC : return selectG_INTRINSIC ( I , CoverageInfo ) ; case TargetOpcode :: G_INTRINSIC_W_SIDE_EFFECTS : return selectG_INTRINSIC_W_SIDE_EFFECTS ( I , CoverageInfo ) ; case TargetOpcode :: G_ICMP : if ( selectG_ICMP ( I ) ) return true ; return selectImpl ( I , CoverageInfo ) ; case TargetOpcode :: G_LOAD : return selectImpl ( I , CoverageInfo ) ; case TargetOpcode :: G_SELECT : return selectG_SELECT ( I ) ; case TargetOpcode :: G_STORE : if ( selectImpl ( I , CoverageInfo ) ) return true ; return selectG_STORE ( I ) ; case TargetOpcode :: G_TRUNC : return selectG_TRUNC ( I ) ; case TargetOpcode :: G_SEXT : case TargetOpcode :: G_ZEXT : case TargetOpcode :: G_ANYEXT : return selectG_SZA_EXT ( I ) ; case TargetOpcode :: G_BRCOND : return selectG_BRCOND ( I ) ; case TargetOpcode :: G_FRAME_INDEX : return selectG_FRAME_INDEX ( I ) ; case TargetOpcode :: G_FENCE : I . setDesc ( TII . get ( AMDGPU :: ATOMIC_FENCE ) ) ; return true ; } return false ; } </s>

Select the ( possibly generic ) instruction I to only use target-specific opcodes .

AMDGPU AMDGPU SI SI SI SI AMDGPU::ATOMIC_FENCE


"; WARNING: The following code is valid only with MASM v8.x"

"; This version of MASM is usually shipped with Microsoft "

"; or (possible) further versions. Unfortunately, there is no "

"; dllexported symbols in the earlier versions of MASM in fully "

"_drectve\t segment info alias('.drectve')\n"

doFinalization - Virtual method overriden by subclasses to do any necessary clean up after all passes have run .


<s> explicit Register ( const MachineOperand & MO ) : Reg ( MO . getReg ( ) ) , SubReg ( MO . getSubReg ( ) ) { } </s>


<s> static void c6x_reorg ( void ) { basic_block bb ; rtx * call_labels ; bool do_selsched = ( c6x_flag_schedule_insns2 && flag_selective_scheduling2 && ! maybe_skip_selective_scheduling ( ) ) ; compute_bb_for_insn ( ) ; df_clear_flags ( DF_LR_RUN_DCE ) ; df_note_add_problem ( ) ; if ( optimize == 0 ) split_all_insns ( ) ; df_analyze ( ) ; if ( c6x_flag_schedule_insns2 ) { int sz = get_max_uid ( ) * 3 / 2 + 1 ; insn_info . create ( sz ) ; } sched_no_dce = true ; c6x_hwloops ( ) ; if ( c6x_flag_schedule_insns2 ) { split_delayed_insns ( ) ; timevar_push ( TV_SCHED2 ) ; if ( do_selsched ) run_selective_scheduling ( ) ; else schedule_ebbs ( ) ; conditionalize_after_sched ( ) ; timevar_pop ( TV_SCHED2 ) ; free_delay_pairs ( ) ; } sched_no_dce = false ; call_labels = XCNEWVEC ( rtx , get_max_uid ( ) + 1 ) ; reorg_split_calls ( call_labels ) ; if ( c6x_flag_schedule_insns2 ) { FOR_EACH_BB_FN ( bb , cfun ) if ( ( bb -> flags & BB_DISABLE_SCHEDULE ) == 0 ) assign_reservations ( BB_HEAD ( bb ) , BB_END ( bb ) ) ; } if ( c6x_flag_var_tracking ) { timevar_push ( TV_VAR_TRACKING ) ; variable_tracking_main ( ) ; timevar_pop ( TV_VAR_TRACKING ) ; } reorg_emit_nops ( call_labels ) ; if ( c6x_flag_schedule_insns2 ) { free_delay_pairs ( ) ; c6x_gen_bundles ( ) ; } df_finish_pass ( false ) ; } </s>

Implement the TARGET_MACHINE_DEPENDENT_REORG pass . We split call insns here into a sequence that loads the return register and performs the call , and emit the return label . If scheduling after reload is requested , it happens here .


<s> BitVector PPCRegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; Reserved . set ( PPC :: R0 ) ; Reserved . set ( PPC :: R1 ) ; Reserved . set ( PPC :: LR ) ; Reserved . set ( PPC :: LR8 ) ; Reserved . set ( PPC :: RM ) ; if ( Subtarget . isSVR4ABI ( ) ) { Reserved . set ( PPC :: R2 ) ; Reserved . set ( PPC :: R13 ) ; } if ( Subtarget . isDarwinABI ( ) ) { Reserved . set ( PPC :: R2 ) ; } if ( Subtarget . isPPC64 ( ) ) { Reserved . set ( PPC :: R13 ) ; Reserved . set ( PPC :: R31 ) ; if ( ! EnableRegisterScavenging ) Reserved . set ( PPC :: R0 ) ; Reserved . set ( PPC :: X0 ) ; Reserved . set ( PPC :: X1 ) ; Reserved . set ( PPC :: X13 ) ; Reserved . set ( PPC :: X31 ) ; if ( Subtarget . isSVR4ABI ( ) ) { Reserved . set ( PPC :: X2 ) ; } if ( Subtarget . isDarwinABI ( ) ) { Reserved . set ( PPC :: X2 ) ; } } if ( needsFP ( MF ) ) Reserved . set ( PPC :: R31 ) ; return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s>
const
MCExpr
*
ARMElfTargetObjectFile
::
getTTypeGlobalReference
(
const
GlobalValue
*
GV
,
Mangler
*
Mang
,
MachineModuleInfo
*
MMI
,
unsigned
Encoding
,
MCStreamer
&
Streamer
)
const
{
assert
(
Encoding
==
DW_EH_PE_absptr
&&
"Can handle absptr encoding only"
)
;
return
MCSymbolRefExpr
::
Create
(
Mang
->
getSymbol
(
GV
)
,
MCSymbolRefExpr
::
VK_ARM_TARGET2
,
getContext
(
)
)
;
}
</s>

The mach-o version of this method defaults to returning a stub reference .

ARM
ARM
"Can handle absptr encoding only"
ARM


"Offset type is not a multiple of bytes"


<s> bool PatmosFrameLowering :: hasFP ( const MachineFunction & MF ) const { auto MFI = MF . getFrameInfo ( ) ; if ( MF . getFunction ( ) . hasFnAttribute ( Attribute :: Naked ) ) return false ; return ( MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) || MF . getFrameInfo ( ) . hasVarSizedObjects ( ) || MFI . isFrameAddressTaken ( ) ) ; } </s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .


"Unexpected Kind in getPointerRegClass!"

getPointerRegClass - Returns a TargetRegisterClass used for pointer values .


<s> bool MipsLongBranch :: runOnMachineFunction ( MachineFunction & F ) { const MipsInstrInfo * TII = static_cast < const MipsInstrInfo * > ( TM . getInstrInfo ( ) ) ; if ( TM . getSubtarget < MipsSubtarget > ( ) . inMips16Mode ( ) ) return false ; if ( ( TM . getRelocationModel ( ) == Reloc :: PIC_ ) && TM . getSubtarget < MipsSubtarget > ( ) . isABI_O32 ( ) && F . getInfo < MipsFunctionInfo > ( ) -> globalBaseRegSet ( ) ) emitGPDisp ( F , TII ) ; if ( SkipLongBranch ) return true ; MF = & F ; initMBBInfo ( ) ; SmallVectorImpl < MBBInfo > :: iterator I , E = MBBInfos . end ( ) ; bool EverMadeChange = false , MadeChange = true ; while ( MadeChange ) { MadeChange = false ; for ( I = MBBInfos . begin ( ) ; I != E ; ++ I ) { if ( ! I -> Br || I -> HasLongBranch ) continue ; int ShVal = TM . getSubtarget < MipsSubtarget > ( ) . inMicroMipsMode ( ) ? 2 : 4 ; if ( ! ForceLongBranch && isInt < 16 > ( computeOffset ( I -> Br ) / ShVal ) ) continue ; I -> HasLongBranch = true ; I -> Size += LongBranchSeqSize * 4 ; ++ LongBranches ; EverMadeChange = MadeChange = true ; } } if ( ! EverMadeChange ) return true ; if ( TM . getRelocationModel ( ) == Reloc :: PIC_ ) { uint64_t Address = 0 ; for ( I = MBBInfos . begin ( ) ; I != E ; Address += I -> Size , ++ I ) I -> Address = Address ; } for ( I = MBBInfos . begin ( ) ; I != E ; ++ I ) if ( I -> HasLongBranch ) expandToLongBranch ( * I ) ; MF -> RenumberBlocks ( ) ; return true ; } </s>

runOnMachineFunction - Emit the function body .

Mips Mips Mips Mips Mips Mips Mips Mips Mips Mips 2 4 16 4 0


<s> void MipsAsmBackend :: applyFixup ( const MCFixup & Fixup , char * Data , unsigned DataSize , uint64_t Value , bool IsPCRel ) const { MCFixupKind Kind = Fixup . getKind ( ) ; Value = adjustFixupValue ( Fixup , Value ) ; if ( ! Value ) return ; unsigned Offset = Fixup . getOffset ( ) ; unsigned NumBytes = ( getFixupKindInfo ( Kind ) . TargetSize + 7 ) / 8 ; unsigned FullSize ; switch ( ( unsigned ) Kind ) { case FK_Data_2 : case Mips :: fixup_Mips_16 : FullSize = 2 ; break ; case FK_Data_8 : case Mips :: fixup_Mips_64 : FullSize = 8 ; break ; case FK_Data_4 : default : FullSize = 4 ; break ; } uint64_t CurVal = 0 ; bool microMipsLEByteOrder = needsMMLEByteOrder ( ( unsigned ) Kind ) ; for ( unsigned i = 0 ; i != NumBytes ; ++ i ) { unsigned Idx = IsLittle ? ( microMipsLEByteOrder ? calculateMMLEIndex ( i ) : i ) : ( FullSize - 1 - i ) ; CurVal |= ( uint64_t ) ( ( uint8_t ) Data [ Offset + Idx ] ) << ( i * 8 ) ; } uint64_t Mask = ( ( uint64_t ) ( - 1 ) >> ( 64 - getFixupKindInfo ( Kind ) . TargetSize ) ) ; CurVal |= Value & Mask ; for ( unsigned i = 0 ; i != NumBytes ; ++ i ) { unsigned Idx = IsLittle ? ( microMipsLEByteOrder ? calculateMMLEIndex ( i ) : i ) : ( FullSize - 1 - i ) ; Data [ Offset + Idx ] = ( uint8_t ) ( ( CurVal >> ( i * 8 ) ) & 0xff ) ; } } </s>

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


<s>
char
*
aarch64_output_sve_addvl_addpl
(
rtx
offset
)
{
static
char
buffer
[
sizeof
(
"addpl\t%x0, %x1, #-"
)
+
3
*
sizeof
(
int
)
]
;
poly_int64
offset_value
=
rtx_to_poly_int64
(
offset
)
;
gcc_assert
(
aarch64_sve_addvl_addpl_immediate_p
(
offset_value
)
)
;
int
factor
=
offset_value
.
coeffs
[
1
]
;
if
(
(
factor
&
15
)
==
0
)
snprintf
(
buffer
,
sizeof
(
buffer
)
,
"addvl\t%%x0, %%x1, #%d"
,
factor
/
16
)
;
else
snprintf
(
buffer
,
sizeof
(
buffer
)
,
"addpl\t%%x0, %%x1, #%d"
,
factor
/
2
)
;
return
buffer
;
}
</s>

Return the asm string for adding ADDVL or ADDPL immediate X to operand 1 and storing the result in operand 0 .


<s> unsigned SIRegisterInfo :: reservedPrivateSegmentBufferReg ( const MachineFunction & MF ) const { unsigned BaseIdx = alignDown ( ST . getMaxNumSGPRs ( MF ) , 4 ) - 4 ; unsigned BaseReg ( AMDGPU :: SGPR_32RegClass . getRegister ( BaseIdx ) ) ; return getMatchingSuperReg ( BaseReg , AMDGPU :: sub0 , & AMDGPU :: SGPR_128RegClass ) ; } </s>

Return the end register initially reserved for the scratch buffer in case spilling is needed .


<s> BitVector XCoreRegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; const TargetFrameLowering * TFI = MF . getSubtarget ( ) . getFrameLowering ( ) ; Reserved . set ( XCore :: CP ) ; Reserved . set ( XCore :: DP ) ; Reserved . set ( XCore :: SP ) ; Reserved . set ( XCore :: LR ) ; if ( TFI -> hasFP ( MF ) ) { Reserved . set ( XCore :: R10 ) ; } return Reserved ; } </s>

XCore XCore XCore::CP XCore::DP XCore::SP XCore::LR XCore::R10


<s> bool isLegalMaskedScatter ( Type * DataType , Align Alignment ) const { return isLegalMaskedGatherScatter ( DataType ) ; } </s>

Return true if the target supports masked scatter .


<s> void PPCAIXAsmPrinter :: SetupMachineFunction ( MachineFunction & MF ) { MCSectionXCOFF * FnDescSec = cast < MCSectionXCOFF > ( getObjFileLowering ( ) . getSectionForFunctionDescriptor ( & MF . getFunction ( ) , TM ) ) ; FnDescSec -> setAlignment ( Align ( Subtarget -> isPPC64 ( ) ? 8 : 4 ) ) ; CurrentFnDescSym = FnDescSec -> getQualNameSymbol ( ) ; return AsmPrinter :: SetupMachineFunction ( MF ) ; } </s>

This should be called when a new MachineFunction is being processed from runOnMachineFunction .


<s> bool ARMBaseTargetMachine :: addInstSelector ( PassManagerBase & PM , CodeGenOpt :: Level OptLevel ) { PM . add ( createARMISelDag ( * this , OptLevel ) ) ; return false ; } </s>

addInstSelector - This method should install an instruction selector pass , which converts from LLVM code to machine instructions .


"SIInstrInfo::loadRegFromStackSlot - Do not know how to"

Load the specified register of the given register class from the specified stack frame index .


<s> bool isImm ( ) const override { return Kind == k_Immediate ; } </s>


<s> unsigned getNumFixupKinds ( ) const override { return CAHP :: NumTargetFixupKinds ; } </s>

Get the number of target specific fixup kinds .


<s> bool AArch64TargetLowering :: isMaskAndCmp0FoldingBeneficial ( const Instruction & AndI ) const { ConstantInt * Mask = dyn_cast < ConstantInt > ( AndI . getOperand ( 1 ) ) ; if ( ! Mask ) return false ; return Mask -> getValue ( ) . isPowerOf2 ( ) ; } </s>

Return if the target supports combining a chain like :


Write the extra assembler code needed to declare a function properly .


<s> bool hasModifiers ( ) const { assert ( isRegKind ( ) || isImm ( ) ) ; return isRegKind ( ) ? Reg . Modifiers != 0 : Imm . Modifiers != 0 ; } </s>

Return true if this instruction has any modifiers .


<s> bool runOnMachineFunction ( MachineFunction & MF ) override { GlobalBaseReg = 0 ; PPCSubTarget = & MF . getSubtarget < PPCSubtarget > ( ) ; Subtarget = & MF . getSubtarget < PPCSubtarget > ( ) ; PPCLowering = Subtarget -> getTargetLowering ( ) ; SelectionDAGISel :: runOnMachineFunction ( MF ) ; if ( ! Subtarget -> isSVR4ABI ( ) ) InsertVRSaveCode ( MF ) ; return true ; } </s>


<s> static machine_mode mips_preferred_simd_mode ( machine_mode mode ) { if ( TARGET_PAIRED_SINGLE_FLOAT && mode == SFmode ) return V2SFmode ; if ( ! ISA_HAS_MSA ) return word_mode ; switch ( mode ) { case QImode : return V16QImode ; case HImode : return V8HImode ; case SImode : return V4SImode ; case DImode : return V2DImode ; case SFmode : return V4SFmode ; case DFmode : return V2DFmode ; default : break ; } return word_mode ; } </s>


<s> void SparcTargetLowering :: computeKnownBitsForTargetNode ( const SDValue Op , APInt & KnownZero , APInt & KnownOne , const SelectionDAG & DAG , unsigned Depth ) const { APInt KnownZero2 , KnownOne2 ; KnownZero = KnownOne = APInt ( KnownZero . getBitWidth ( ) , 0 ) ; switch ( Op . getOpcode ( ) ) { default : break ; case SPISD :: SELECT_ICC : case SPISD :: SELECT_XCC : case SPISD :: SELECT_FCC : DAG . computeKnownBits ( Op . getOperand ( 1 ) , KnownZero , KnownOne , Depth + 1 ) ; DAG . computeKnownBits ( Op . getOperand ( 0 ) , KnownZero2 , KnownOne2 , Depth + 1 ) ; KnownOne &= KnownOne2 ; KnownZero &= KnownZero2 ; break ; } } </s>

Determine which of the bits specified in Mask are known to be either zero or one and return them in the KnownZero/KnownOne bitsets .


<s> unsigned int ix86_local_alignment ( tree exp , machine_mode mode , unsigned int align ) { tree type , decl ; if ( exp && DECL_P ( exp ) ) { type = TREE_TYPE ( exp ) ; decl = exp ; } else { type = exp ; decl = NULL ; } if ( ! TARGET_64BIT && align == 64 && ix86_preferred_stack_boundary < 64 && ( mode == DImode || ( type && TYPE_MODE ( type ) == DImode ) ) && ( ! type || ! TYPE_USER_ALIGN ( type ) ) && ( ! decl || ! DECL_USER_ALIGN ( decl ) ) ) align = 32 ; if ( ! type ) { if ( mode == XFmode && align < GET_MODE_ALIGNMENT ( DFmode ) ) align = GET_MODE_ALIGNMENT ( DFmode ) ; return align ; } if ( TARGET_IAMCU ) return align ; if ( TARGET_64BIT && optimize_function_for_speed_p ( cfun ) && TARGET_SSE ) { if ( AGGREGATE_TYPE_P ( type ) && ( va_list_type_node == NULL_TREE || ( TYPE_MAIN_VARIANT ( type ) != TYPE_MAIN_VARIANT ( va_list_type_node ) ) ) && TYPE_SIZE ( type ) && TREE_CODE ( TYPE_SIZE ( type ) ) == INTEGER_CST && wi :: geu_p ( TYPE_SIZE ( type ) , 128 ) && align < 128 ) return 128 ; } if ( TREE_CODE ( type ) == ARRAY_TYPE ) { if ( TYPE_MODE ( TREE_TYPE ( type ) ) == DFmode && align < 64 ) return 64 ; if ( ALIGN_MODE_128 ( TYPE_MODE ( TREE_TYPE ( type ) ) ) && align < 128 ) return 128 ; } else if ( TREE_CODE ( type ) == COMPLEX_TYPE ) { if ( TYPE_MODE ( type ) == DCmode && align < 64 ) return 64 ; if ( ( TYPE_MODE ( type ) == XCmode || TYPE_MODE ( type ) == TCmode ) && align < 128 ) return 128 ; } else if ( ( TREE_CODE ( type ) == RECORD_TYPE || TREE_CODE ( type ) == UNION_TYPE || TREE_CODE ( type ) == QUAL_UNION_TYPE ) && TYPE_FIELDS ( type ) ) { if ( DECL_MODE ( TYPE_FIELDS ( type ) ) == DFmode && align < 64 ) return 64 ; if ( ALIGN_MODE_128 ( DECL_MODE ( TYPE_FIELDS ( type ) ) ) && align < 128 ) return 128 ; } else if ( TREE_CODE ( type ) == REAL_TYPE || TREE_CODE ( type ) == VECTOR_TYPE || TREE_CODE ( type ) == INTEGER_TYPE ) { if ( TYPE_MODE ( type ) == DFmode && align < 64 ) return 64 ; if ( ALIGN_MODE_128 ( TYPE_MODE ( type ) ) && align < 128 ) return 128 ; } return align ; } </s>

Compute the alignment for a local variable . TYPE is the data type , and ALIGN is the alignment that the object would ordinarily have . The value of this macro is used instead of that alignment to align the object .


<s> static bool mips_callee_copies ( cumulative_args_t , const function_arg_info & arg ) { return mips_abi == ABI_EABI && arg . named ; } </s>


<s> SDValue RISCVSelectionDAGInfo :: EmitTargetCodeForMemmove ( SelectionDAG & DAG , const SDLoc & dl , SDValue Chain , SDValue Dst , SDValue Src , SDValue Size , Align Alignment , bool isVolatile , bool MustPreserveCheriCapabilities , MachinePointerInfo DstPtrInfo , MachinePointerInfo SrcPtrInfo ) const { return EmitTargetCodeForMemOp ( DAG , dl , Chain , Dst , Src , Size , Alignment , isVolatile , false , MustPreserveCheriCapabilities , DstPtrInfo , SrcPtrInfo , false ) ; } </s>

Emit target-specific code that performs a memmove .


<s> bool isScheduled ( ) { return Scheduled ; } </s>


<s> std :: pair < unsigned , unsigned > ARMInstrInfo :: decomposeMachineOperandsTargetFlags ( unsigned TF ) const { const unsigned Mask = ARMII :: MO_OPTION_MASK ; return std :: make_pair ( TF & Mask , TF & ~ Mask ) ; } </s>

Decompose the machine operand 's target flags into two values - the direct target flag value and any of bit flags that are applied .


<s> DecodeStatus Mips64Disassembler :: getInstruction ( MCInst & Instr , uint64_t & Size , ArrayRef < uint8_t > Bytes , uint64_t Address , raw_ostream & VStream , raw_ostream & CStream ) const { uint32_t Insn ; DecodeStatus Result = readInstruction32 ( Bytes , Address , Size , Insn , IsBigEndian , false ) ; if ( Result == MCDisassembler :: Fail ) return MCDisassembler :: Fail ; Result = decodeInstruction ( DecoderTableMips6432 , Instr , Insn , Address , this , STI ) ; if ( Result != MCDisassembler :: Fail ) { Size = 4 ; return Result ; } Result = decodeInstruction ( DecoderTableMips32 , Instr , Insn , Address , this , STI ) ; if ( Result != MCDisassembler :: Fail ) { Size = 4 ; return Result ; } return MCDisassembler :: Fail ; } </s>

Returns the disassembly of a single instruction .


<s>
StringRef
getPassName
(
)
const
override
{
return
"Mips Long Branch"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> bool toc_hasher :: equal ( toc_hash_struct * h1 , toc_hash_struct * h2 ) { rtx r1 = h1 -> key ; rtx r2 = h2 -> key ; if ( h1 -> key_mode != h2 -> key_mode ) return 0 ; return rtx_equal_p ( r1 , r2 ) ; } </s>


initializeSubtargetDependencies - Initializes using a CPU , a TuneCPU , and feature string so that we can use initializer lists for subtarget initialization .


<s>
static
void
arc_output_mi_thunk
(
FILE
*
file
,
tree
thunk
ATTRIBUTE_UNUSED
,
HOST_WIDE_INT
delta
,
HOST_WIDE_INT
vcall_offset
,
tree
function
)
{
int
mi_delta
=
delta
;
const
char
*
const
mi_op
=
mi_delta
<
0
"sub"
:
"add"
;
int
shift
=
0
;
int
this_regno
=
aggregate_value_p
(
TREE_TYPE
(
TREE_TYPE
(
function
)
)
,
function
)
1
:
0
;
rtx
fnaddr
;
if
(
mi_delta
<
0
)
mi_delta
=
mi_delta
;
while
(
mi_delta
!=
0
)
{
if
(
(
mi_delta
&
(
3
<<
shift
)
)
==
0
)
shift
+=
2
;
else
{
asm_fprintf
(
file
,
"\t%s\t%s, %s, %d\n"
,
mi_op
,
reg_names
[
this_regno
]
,
reg_names
[
this_regno
]
,
mi_delta
&
(
0xff
<<
shift
)
)
;
mi_delta
&=
~
(
0xff
<<
shift
)
;
shift
+=
8
;
}
}
if
(
vcall_offset
!=
0
)
{
asm_fprintf
(
file
,
"\tld\t%s, [%s]\n"
,
ARC_TEMP_SCRATCH_REG
,
reg_names
[
this_regno
]
)
;
asm_fprintf
(
file
,
"\tadd\t%s, %s, "
HOST_WIDE_INT_PRINT_DEC
"\n"
,
ARC_TEMP_SCRATCH_REG
,
ARC_TEMP_SCRATCH_REG
,
vcall_offset
)
;
asm_fprintf
(
file
,
"\tld\t%s, [%s]\n"
,
ARC_TEMP_SCRATCH_REG
,
ARC_TEMP_SCRATCH_REG
)
;
asm_fprintf
(
file
,
"\tadd\t%s, %s, %s\n"
,
reg_names
[
this_regno
]
,
reg_names
[
this_regno
]
,
ARC_TEMP_SCRATCH_REG
)
;
}
fnaddr
=
XEXP
(
DECL_RTL
(
function
)
,
0
)
;
if
(
arc_is_longcall_p
(
fnaddr
)
)
fputs
(
"\tj\t"
,
file
)
;
else
fputs
(
"\tb\t"
,
file
)
;
assemble_name
(
file
,
XSTR
(
fnaddr
,
0
)
)
;
fputc
(
'\n'
,
file
)
;
}
</s>

Output code to add DELTA to the first argument , and then jump to FUNCTION . Used for C++ multiple inheritance .


<s> static int rs6000_builtin_vectorization_cost ( enum vect_cost_for_stmt type_of_cost , tree vectype , int misalign ) { unsigned elements ; tree elem_type ; switch ( type_of_cost ) { case scalar_stmt : case scalar_load : case scalar_store : case vector_stmt : case vector_load : case vector_store : case vec_to_scalar : case scalar_to_vec : case cond_branch_not_taken : return 1 ; case vec_perm : if ( TARGET_VSX ) return 3 ; else return 1 ; case vec_promote_demote : if ( TARGET_VSX ) return 4 ; else return 1 ; case cond_branch_taken : return 3 ; case unaligned_load : if ( TARGET_EFFICIENT_UNALIGNED_VSX ) return 1 ; if ( TARGET_VSX && TARGET_ALLOW_MOVMISALIGN ) { elements = TYPE_VECTOR_SUBPARTS ( vectype ) ; if ( elements == 2 ) return 2 ; if ( elements == 4 ) { switch ( misalign ) { case 8 : return 2 ; case - 1 : case 4 : case 12 : return 22 ; default : gcc_unreachable ( ) ; } } } if ( TARGET_ALTIVEC ) gcc_unreachable ( ) ; return 2 ; case unaligned_store : if ( TARGET_EFFICIENT_UNALIGNED_VSX ) return 1 ; if ( TARGET_VSX && TARGET_ALLOW_MOVMISALIGN ) { elements = TYPE_VECTOR_SUBPARTS ( vectype ) ; if ( elements == 2 ) return 2 ; if ( elements == 4 ) { switch ( misalign ) { case 8 : return 2 ; case - 1 : case 4 : case 12 : return 23 ; default : gcc_unreachable ( ) ; } } } if ( TARGET_ALTIVEC ) gcc_unreachable ( ) ; return 2 ; case vec_construct : elements = TYPE_VECTOR_SUBPARTS ( vectype ) ; elem_type = TREE_TYPE ( vectype ) ; if ( SCALAR_FLOAT_TYPE_P ( elem_type ) && TYPE_PRECISION ( elem_type ) == 32 ) return elements + 1 ; else return elements / 2 + 1 ; default : gcc_unreachable ( ) ; } } </s>


<s> bool shouldInsertFencesForAtomic ( const Instruction * I ) const override { return true ; } </s>

Helper functions for atomic operations .


<s> EVT SPUTargetLowering :: getSetCCResultType ( EVT VT ) const { MVT :: SimpleValueType retval ; switch ( VT . getSimpleVT ( ) . SimpleTy ) { case MVT :: i1 : case MVT :: i8 : retval = MVT :: i8 ; break ; case MVT :: i16 : retval = MVT :: i16 ; break ; case MVT :: i32 : default : retval = MVT :: i32 ; } return retval ; } </s>

Return the value type to use for ISD : :SETCC .


<s> const DataLayout * getDataLayout ( ) const { return & DL ; } </s>

Return the DataLayout associated with the module this SCEV instance is operating on .


<s> bool PPCFastISel :: tryToFoldLoadIntoMI ( MachineInstr * MI , unsigned OpNo , const LoadInst * LI ) { MVT VT ; if ( ! isLoadTypeLegal ( LI -> getType ( ) , VT ) ) return false ; bool IsZExt = false ; switch ( MI -> getOpcode ( ) ) { default : return false ; case PPC :: RLDICL : case PPC :: RLDICL_32_64 : { IsZExt = true ; unsigned MB = MI -> getOperand ( 3 ) . getImm ( ) ; if ( ( VT == MVT :: i8 && MB <= 56 ) || ( VT == MVT :: i16 && MB <= 48 ) || ( VT == MVT :: i32 && MB <= 32 ) ) break ; return false ; } case PPC :: RLWINM : case PPC :: RLWINM8 : { IsZExt = true ; unsigned MB = MI -> getOperand ( 3 ) . getImm ( ) ; if ( ( VT == MVT :: i8 && MB <= 24 ) || ( VT == MVT :: i16 && MB <= 16 ) ) break ; return false ; } case PPC :: EXTSB : case PPC :: EXTSB8 : case PPC :: EXTSB8_32_64 : return false ; case PPC :: EXTSH : case PPC :: EXTSH8 : case PPC :: EXTSH8_32_64 : { if ( VT != MVT :: i16 && VT != MVT :: i8 ) return false ; break ; } case PPC :: EXTSW : case PPC :: EXTSW_32 : case PPC :: EXTSW_32_64 : { if ( VT != MVT :: i32 && VT != MVT :: i16 && VT != MVT :: i8 ) return false ; break ; } } Address Addr ; if ( ! PPCComputeAddress ( LI -> getOperand ( 0 ) , Addr ) ) return false ; Register ResultReg = MI -> getOperand ( 0 ) . getReg ( ) ; if ( ! PPCEmitLoad ( VT , ResultReg , Addr , nullptr , IsZExt , Subtarget -> hasSPE ( ) ? PPC :: EVLDD : PPC :: LFD ) ) return false ; MachineBasicBlock :: iterator I ( MI ) ; removeDeadCode ( I , std :: next ( I ) ) ; return true ; } </s>

The specified machine instr operand is a vreg , and that vreg is being provided by the specified load instruction .


<s>
TargetLowering
::
AtomicExpansionKind
X86TargetLowering
::
shouldExpandAtomicRMWInIR
(
AtomicRMWInst
*
AI
)
const
{
unsigned
NativeWidth
=
Subtarget
.
is64Bit
(
)
64
:
32
;
Type
*
MemType
=
AI
->
getType
(
)
;
if
(
MemType
->
getPrimitiveSizeInBits
(
)
>
NativeWidth
)
{
return
needsCmpXchgNb
(
MemType
)
AtomicExpansionKind
::
CmpXChg
:
AtomicExpansionKind
::
;
}
AtomicRMWInst
::
BinOp
Op
=
AI
->
getOperation
(
)
;
switch
(
Op
)
{
default
:
llvm_unreachable
(
"Unknown atomic operation"
)
;
case
AtomicRMWInst
::
Xchg
:
case
AtomicRMWInst
::
Add
:
case
AtomicRMWInst
::
Sub
:
return
AtomicExpansionKind
::
;
case
AtomicRMWInst
::
Or
:
case
AtomicRMWInst
::
And
:
case
AtomicRMWInst
::
Xor
:
return
!
AI
->
use_empty
(
)
AtomicExpansionKind
::
CmpXChg
:
AtomicExpansionKind
::
;
case
AtomicRMWInst
::
Nand
:
case
AtomicRMWInst
::
Max
:
case
AtomicRMWInst
::
Min
:
case
AtomicRMWInst
::
UMax
:
case
AtomicRMWInst
::
UMin
:
case
AtomicRMWInst
::
FAdd
:
case
AtomicRMWInst
::
FSub
:
return
AtomicExpansionKind
::
CmpXChg
;
}
}
</s>

Returns how the IR-level AtomicExpand pass should expand the given AtomicRMW , if at all .


<s> virtual unsigned getABIAlignmentForCallingConv ( Type * ArgTy , DataLayout DL ) const override { if ( ArgTy -> isVectorTy ( ) ) return std :: min ( DL . getABITypeAlignment ( ArgTy ) , 8U ) ; return DL . getABITypeAlignment ( ArgTy ) ; } </s>

Return the correct alignment for the current calling convention .


"instruction use requires option to be enabled"

MatchAndEmitInstruction - Recognize a series of operands of a parsed instruction as an actual MCInst and emit it to the specified MCStreamer .


<s> bool MSP430FrameInfo :: spillCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo * TRI ) const { if ( CSI . empty ( ) ) return false ; DebugLoc DL ; if ( MI != MBB . end ( ) ) DL = MI -> getDebugLoc ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; const TargetInstrInfo & TII = * MF . getTarget ( ) . getInstrInfo ( ) ; MSP430MachineFunctionInfo * MFI = MF . getInfo < MSP430MachineFunctionInfo > ( ) ; MFI -> setCalleeSavedFrameSize ( CSI . size ( ) * 2 ) ; for ( unsigned i = CSI . size ( ) ; i != 0 ; -- i ) { unsigned Reg = CSI [ i - 1 ] . getReg ( ) ; MBB . addLiveIn ( Reg ) ; BuildMI ( MBB , MI , DL , TII . get ( MSP430 :: PUSH16r ) ) . addReg ( Reg , RegState :: Kill ) ; } return true ; } </s>

spillCalleeSavedRegisters - Issues instruction ( s ) to spill all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of store instructions via storeRegToStackSlot ( ) .


<s> static rtx function_arg_vector_value ( int size , int regno ) { const int nregs = MAX ( 1 , size / 8 ) ; rtx regs = gen_rtx_PARALLEL ( BLKmode , rtvec_alloc ( nregs ) ) ; if ( size < 8 ) XVECEXP ( regs , 0 , 0 ) = gen_rtx_EXPR_LIST ( VOIDmode , gen_rtx_REG ( SImode , regno ) , const0_rtx ) ; else for ( int i = 0 ; i < nregs ; i ++ ) XVECEXP ( regs , 0 , i ) = gen_rtx_EXPR_LIST ( VOIDmode , gen_rtx_REG ( DImode , regno + 2 * i ) , GEN_INT ( i * 8 ) ) ; return regs ; } </s>

Used by function_arg and sparc_function_value_1 to implement the conventions for passing and returning BLKmode vectors . Return an expression valid as a return value for the FUNCTION_ARG and TARGET_FUNCTION_VALUE . SIZE is the size in bytes of the vector . REGNO is the FP hard register the vector will be passed in .


<s> SMLoc getEndLoc ( ) const { return End ; } </s>

getEndLoc - Get the location of the last token of this operand .


<s> void Tile64InstrInfo :: loadRegFromStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned DestReg , int FI , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { DebugLoc DL ; if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; BuildMI ( MBB , I , DL , get ( T64 :: LW ) ) . addReg ( DestReg ) . addFrameIndex ( FI ) ; } </s>

Load the specified register of the given register class from the specified stack frame index .


runOnMachineFunction - Emit the function body .


<s> unsigned int calculate_ratio ( unsigned int sew , enum vlmul_type vlmul ) { unsigned int ratio ; switch ( vlmul ) { case LMUL_1 : ratio = sew ; break ; case LMUL_2 : ratio = sew / 2 ; break ; case LMUL_4 : ratio = sew / 4 ; break ; case LMUL_8 : ratio = sew / 8 ; break ; case LMUL_F8 : ratio = sew * 8 ; break ; case LMUL_F4 : ratio = sew * 4 ; break ; case LMUL_F2 : ratio = sew * 2 ; break ; default : gcc_unreachable ( ) ; } return ratio ; } </s>


<s>
void
print
(
DiagnosticPrinter
&
DP
)
const
override
{
std
::
string
Str
;
raw_string_ostream
OS
(
Str
)
;
if
(
DLoc
)
{
auto
DIL
=
DLoc
.
get
(
)
;
StringRef
Filename
=
DIL
->
getFilename
(
)
;
unsigned
Line
=
DIL
->
getLine
(
)
;
unsigned
Column
=
DIL
->
getColumn
(
)
;
OS
<<
Filename
<<
':'
<<
Line
<<
':'
<<
Column
<<
' '
;
}
OS
<<
"in function "
<<
Fn
.
getName
(
)
<<
' '
<<
*
Fn
.
getFunctionType
(
)
<<
'\n'
<<
Description
;
if
(
Value
)
Value
->
print
(
OS
)
;
OS
<<
'\n'
;
OS
.
flush
(
)
;
DP
<<
Str
;
}
</s>

print - Print a debug representation of the operand to the given stream .


<s>
const
char
*
output_return
(
rtx_insn
*
insn
)
{
if
(
crtl
->
calls_eh_return
)
{
gcc_assert
(
!
final_sequence
)
;
if
(
flag_delayed_branch
)
{
if
(
!
TARGET_FLAT
&&
TARGET_V9
)
fputs
(
"\treturn\t%i7+8\n"
,
asm_out_file
)
;
else
{
if
(
!
TARGET_FLAT
)
fputs
(
"\trestore\n"
,
asm_out_file
)
;
fputs
(
"\tjmp\t%o7+8\n"
,
asm_out_file
)
;
}
fputs
(
"\t add\t%sp, %g1, %sp\n"
,
asm_out_file
)
;
}
else
{
if
(
!
TARGET_FLAT
)
fputs
(
"\trestore\n"
,
asm_out_file
)
;
fputs
(
"\tadd\t%sp, %g1, %sp\n"
,
asm_out_file
)
;
fputs
(
"\tjmp\t%o7+8\n\t nop\n"
,
asm_out_file
)
;
}
}
else
if
(
sparc_leaf_function_p
||
TARGET_FLAT
)
{
return
"jmp\t%%o7+%)%#"
;
}
else
{
if
(
final_sequence
)
{
rtx
delay
,
pat
;
delay
=
NEXT_INSN
(
insn
)
;
gcc_assert
(
delay
)
;
pat
=
PATTERN
(
delay
)
;
if
(
TARGET_V9
&&
!
epilogue_renumber
(
&
pat
,
1
)
)
{
epilogue_renumber
(
&
pat
,
0
)
;
return
"return\t%%i7+%)%#"
;
}
else
{
output_asm_insn
(
"jmp\t%%i7+%)"
,
)
;
output_restore
(
pat
)
;
PATTERN
(
delay
)
=
gen_blockage
(
)
;
INSN_CODE
(
delay
)
=
1
;
}
}
else
{
if
(
TARGET_V9
)
return
"return\t%%i7+%)\n\t nop"
;
else
if
(
flag_delayed_branch
)
return
"jmp\t%%i7+%)\n\t restore"
;
else
return
"restore\n\tjmp\t%%o7+%)\n\t nop"
;
}
}
return
""
;
}
</s>


<s>
SDValue
RISCVTargetLowering
::
LowerOperation
(
SDValue
Op
,
SelectionDAG
&
DAG
)
const
{
switch
(
Op
.
getOpcode
(
)
)
{
default
:
report_fatal_error
(
"unimplemented operand"
)
;
case
ISD
::
GlobalAddress
:
return
lowerGlobalAddress
(
Op
,
DAG
)
;
case
ISD
::
BlockAddress
:
return
lowerBlockAddress
(
Op
,
DAG
)
;
case
ISD
::
ConstantPool
:
return
lowerConstantPool
(
Op
,
DAG
)
;
case
ISD
::
GlobalTLSAddress
:
return
lowerGlobalTLSAddress
(
Op
,
DAG
)
;
case
ISD
::
SELECT
:
return
lowerSELECT
(
Op
,
DAG
)
;
case
ISD
::
VASTART
:
return
lowerVASTART
(
Op
,
DAG
)
;
case
ISD
::
FRAMEADDR
:
return
lowerFRAMEADDR
(
Op
,
DAG
)
;
case
ISD
::
RETURNADDR
:
return
lowerRETURNADDR
(
Op
,
DAG
)
;
case
ISD
::
SHL_PARTS
:
return
lowerShiftLeftParts
(
Op
,
DAG
)
;
case
ISD
::
SRA_PARTS
:
return
lowerShiftRightParts
(
Op
,
DAG
,
true
)
;
case
ISD
::
SRL_PARTS
:
return
lowerShiftRightParts
(
Op
,
DAG
,
false
)
;
case
ISD
::
BITCAST
:
{
assert
(
Subtarget
.
is64Bit
(
)
&&
Subtarget
.
hasStdExtF
(
)
&&
"Unexpected custom legalisation"
)
;
SDLoc
DL
(
Op
)
;
SDValue
Op0
=
Op
.
getOperand
(
0
)
;
if
(
Op
.
getValueType
(
)
!=
MVT
::
f32
||
Op0
.
getValueType
(
)
!=
MVT
::
i32
)
return
SDValue
(
)
;
SDValue
NewOp0
=
DAG
.
getNode
(
ISD
::
ANY_EXTEND
,
DL
,
MVT
::
i64
,
Op0
)
;
SDValue
FPConv
=
DAG
.
getNode
(
RISCVISD
::
FMV_W_X_RV64
,
DL
,
MVT
::
f32
,
NewOp0
)
;
return
FPConv
;
}
case
ISD
::
EXTRACT_VECTOR_ELT
:
return
lowerEXTRACT_VECTOR_ELT
(
Op
,
DAG
)
;
case
ISD
::
INTRINSIC_WO_CHAIN
:
return
LowerINTRINSIC_WO_CHAIN
(
Op
,
DAG
)
;
}
}
</s>

LowerOperation - Provide custom lowering hooks for some operations .


<s> static rtx hwloop_pattern_reg ( rtx_insn * insn ) { rtx pat , reg ; if ( ! JUMP_P ( insn ) || recog_memoized ( insn ) != CODE_FOR_loop_end ) return NULL_RTX ; pat = PATTERN ( insn ) ; reg = SET_DEST ( XVECEXP ( pat , 0 , 1 ) ) ; if ( ! REG_P ( reg ) ) return NULL_RTX ; return reg ; } </s>

A callback for the hw-doloop pass . This function examines INSN ; if it is a doloop_end pattern we recognize , return the reg rtx for the loop counter . Otherwise , return NULL_RTX .


"Pseudo opcode found in EmitInstruction()"

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s> bool arc_is_uncached_mem_p ( rtx pat ) { tree attrs = NULL_TREE ; tree addr ; if ( ! MEM_P ( pat ) ) return false ; addr = MEM_EXPR ( pat ) ; if ( ! addr ) return false ; if ( TREE_CODE ( addr ) == MEM_REF ) { attrs = TYPE_ATTRIBUTES ( TREE_TYPE ( addr ) ) ; if ( lookup_attribute ( "uncached" , attrs ) ) return true ; attrs = TYPE_ATTRIBUTES ( TREE_TYPE ( TREE_OPERAND ( addr , 0 ) ) ) ; if ( lookup_attribute ( "uncached" , attrs ) ) return true ; } if ( TREE_CODE ( addr ) == COMPONENT_REF ) { attrs = TYPE_ATTRIBUTES ( TREE_TYPE ( TREE_OPERAND ( addr , 1 ) ) ) ; if ( lookup_attribute ( "uncached" , attrs ) ) return true ; } return false ; } </s>

Return TRUE if PAT is a memory addressing an uncached data .

arc "uncached" 0 "uncached" 1 "uncached"


<s> unsigned postKnownBits ( Align Align = Align :: None ( ) ) const { return std :: max ( Log2 ( std :: max ( PostAlign , Align ) ) , internalKnownBits ( ) ) ; } </s>

Compute the number of known low bits of postOffset .


<s> void finishLayout ( MCAssembler const & Asm , MCAsmLayout & Layout ) const override { for ( auto I : Layout . getSectionOrder ( ) ) { auto & Fragments = I -> getFragmentList ( ) ; for ( auto & J : Fragments ) { switch ( J . getKind ( ) ) { default : break ; case MCFragment :: FT_Align : { auto Size = Asm . computeFragmentSize ( Layout , J ) ; for ( auto K = J . getIterator ( ) ; K != Fragments . begin ( ) && Size >= HEXAGON_PACKET_SIZE ; ) { -- K ; switch ( K -> getKind ( ) ) { default : break ; case MCFragment :: FT_Align : { Size = 0 ; break ; } case MCFragment :: FT_Relaxable : { MCContext & Context = Asm . getContext ( ) ; auto & RF = cast < MCRelaxableFragment > ( * K ) ; auto & Inst = const_cast < MCInst & > ( RF . getInst ( ) ) ; while ( Size > 0 && HexagonMCInstrInfo :: bundleSize ( Inst ) < 4 ) { MCInst * Nop = new ( Context ) MCInst ; Nop -> setOpcode ( Hexagon :: A2_nop ) ; Inst . addOperand ( MCOperand :: createInst ( Nop ) ) ; Size -= 4 ; if ( ! HexagonMCChecker ( Context , * MCII , * RF . getSubtargetInfo ( ) , Inst , * Context . getRegisterInfo ( ) , false ) . check ( ) ) { Inst . erase ( Inst . end ( ) - 1 ) ; Size = 0 ; } } bool Error = HexagonMCShuffle ( Context , true , * MCII , * RF . getSubtargetInfo ( ) , Inst ) ; ( void ) Error ; ReplaceInstruction ( Asm . getEmitter ( ) , RF , Inst ) ; Layout . invalidateFragmentsFrom ( & RF ) ; Size = 0 ; break ; } } } } } } } } </s>

Give backend an opportunity to finish layout after relaxation .


<s>
void
output_dbcc_and_branch
(
rtx
*
operands
,
rtx_code
code
)
{
switch
(
code
)
{
case
EQ
:
output_asm_insn
(
"dbeq %0,%l1\n\tjeq %l2"
,
operands
)
;
break
;
case
NE
:
output_asm_insn
(
"dbne %0,%l1\n\tjne %l2"
,
operands
)
;
break
;
case
GT
:
output_asm_insn
(
"dbgt %0,%l1\n\tjgt %l2"
,
operands
)
;
break
;
case
GTU
:
output_asm_insn
(
"dbhi %0,%l1\n\tjhi %l2"
,
operands
)
;
break
;
case
LT
:
output_asm_insn
(
"dblt %0,%l1\n\tjlt %l2"
,
operands
)
;
break
;
case
LTU
:
output_asm_insn
(
"dbcs %0,%l1\n\tjcs %l2"
,
operands
)
;
break
;
case
GE
:
output_asm_insn
(
"dbge %0,%l1\n\tjge %l2"
,
operands
)
;
break
;
case
GEU
:
output_asm_insn
(
"dbcc %0,%l1\n\tjcc %l2"
,
operands
)
;
break
;
case
LE
:
output_asm_insn
(
"dble %0,%l1\n\tjle %l2"
,
operands
)
;
break
;
case
LEU
:
output_asm_insn
(
"dbls %0,%l1\n\tjls %l2"
,
operands
)
;
break
;
case
PLUS
:
output_asm_insn
(
"dbpl %0,%l1\n\tjle %l2"
,
operands
)
;
break
;
case
MINUS
:
output_asm_insn
(
"dbmi %0,%l1\n\tjle %l2"
,
operands
)
;
break
;
default
:
gcc_unreachable
(
)
;
}
switch
(
GET_MODE
(
operands
[
0
]
)
)
{
case
E_SImode
:
output_asm_insn
(
"clr%.w %0\n\tsubq%.l #1,%0\n\tjpl %l1"
,
operands
)
;
break
;
case
E_HImode
:
break
;
default
:
gcc_unreachable
(
)
;
}
}
</s>

Output a dbCC ; jCC sequence . Note we do not handle the floating point version of this sequence ( Fdbcc ) . We also do not handle alternative conditions when CC_NO_OVERFLOW is set . It is assumed that valid_dbcc_comparison_p and flags_in_68881 will kick those out before we get here .


<s> void SVEVecStackRegion :: emitPrologue ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI , DebugLoc DL , uint64_t & AddedSize , unsigned Basereg , uint64_t Offset ) const { if ( RegionSize == 0 ) return ; if ( CSRs . size ( ) == 0 ) { AddedSize += this -> getRegionSize ( ) ; return ; } unsigned TmpBasereg = Basereg ; if ( CSRs . size ( ) > 0 && ( ( ( AddedSize + Offset ) - Scale ) > ( uint64_t ) Scale * 255 ) ) { TmpBasereg = adjustRegBySVE ( MF , MBB , MBBI , DL , Basereg , 0 , false ) ; Offset = 0 ; } adjustRegBySVE ( MF , MBB , MBBI , DL , Basereg , this -> getRegionSize ( ) + AddedSize , false , AArch64 :: SP ) ; AddedSize = 0 ; SaveRestoreSVEFromPointer ( MF , MBB , MBBI , DL , Offset , TmpBasereg , true ) ; } </s>

emitProlog/emitEpilog - These methods insert prolog and epilog code into the function .


<s>
bool
R600VectorRegMerger
::
runOnMachineFunction
(
MachineFunction
&
Fn
)
{
if
(
skipFunction
(
Fn
.
getFunction
(
)
)
)
return
false
;
const
R600Subtarget
&
ST
=
Fn
.
getSubtarget
<
R600Subtarget
>
(
)
;
TII
=
ST
.
getInstrInfo
(
)
;
MRI
=
&
Fn
.
getRegInfo
(
)
;
for
(
MachineFunction
::
iterator
MBB
=
Fn
.
begin
(
)
,
MBBe
=
Fn
.
end
(
)
;
MBB
!=
MBBe
;
++
MBB
)
{
MachineBasicBlock
*
MB
=
&
*
MBB
;
PreviousRegSeq
.
clear
(
)
;
PreviousRegSeqByReg
.
clear
(
)
;
PreviousRegSeqByUndefCount
.
clear
(
)
;
for
(
MachineBasicBlock
::
iterator
MII
=
MB
->
begin
(
)
,
MIIE
=
MB
->
end
(
)
;
MII
!=
MIIE
;
++
MII
)
{
MachineInstr
&
MI
=
*
MII
;
if
(
MI
.
getOpcode
(
)
!=
AMDGPU
::
REG_SEQUENCE
)
{
if
(
TII
->
get
(
MI
.
getOpcode
(
)
)
.
TSFlags
&
R600_InstFlag
::
TEX_INST
)
{
unsigned
Reg
=
MI
.
getOperand
(
1
)
.
getReg
(
)
;
for
(
MachineRegisterInfo
::
def_instr_iterator
It
=
MRI
->
def_instr_begin
(
Reg
)
,
E
=
MRI
->
def_instr_end
(
)
;
It
!=
E
;
++
It
)
{
RemoveMI
(
&
(
*
It
)
)
;
}
}
continue
;
}
RegSeqInfo
RSI
(
*
MRI
,
&
MI
)
;
unsigned
Reg
=
MI
.
getOperand
(
0
)
.
getReg
(
)
;
if
(
!
areAllUsesSwizzeable
(
Reg
)
)
continue
;
LLVM_DEBUG
(
{
dbgs
(
)
<<
"Trying to optimize "
;
MI
.
dump
(
)
;
}
)
;
RegSeqInfo
CandidateRSI
;
std
::
vector
<
std
::
pair
<
unsigned
,
unsigned
>>
RemapChan
;
LLVM_DEBUG
(
dbgs
(
)
<<
"Using common slots...\n"
;
)
;
if
(
tryMergeUsingCommonSlot
(
RSI
,
CandidateRSI
,
RemapChan
)
)
{
RemoveMI
(
CandidateRSI
.
Instr
)
;
MII
=
RebuildVector
(
&
RSI
,
&
CandidateRSI
,
RemapChan
)
;
trackRSI
(
RSI
)
;
continue
;
}
LLVM_DEBUG
(
dbgs
(
)
<<
"Using free slots...\n"
;
)
;
RemapChan
.
clear
(
)
;
if
(
tryMergeUsingFreeSlot
(
RSI
,
CandidateRSI
,
RemapChan
)
)
{
RemoveMI
(
CandidateRSI
.
Instr
)
;
MII
=
RebuildVector
(
&
RSI
,
&
CandidateRSI
,
RemapChan
)
;
trackRSI
(
RSI
)
;
continue
;
}
trackRSI
(
RSI
)
;
}
}
</s>

AMDGPU
R600
R600
R600
AMDGPU::REG_SEQUENCE
R600_InstFlag::TEX_INST
1
SI
0
"Trying to optimize "
SI
"Using common slots...\n"
SI
SI
SI
SI
SI
SI
SI
"Using free slots...\n"
SI
SI
SI
SI
SI
SI
SI
SI
SI


This is a rather crude register death pass . Death status is reset at every jump or call insn .


<s> bool X86Subtarget :: isLegalToCallImmediateAddr ( ) const { if ( Is64Bit || isTargetWin32 ( ) ) return false ; return isTargetELF ( ) || TM . getRelocationModel ( ) == Reloc :: Static ; } </s>

Return true if the subtarget allows calls to immediate address .


<s> bool AArch64FrameLowering :: canUseRedZone ( const MachineFunction & MF ) const { if ( ! EnableRedZone ) return false ; if ( MF . getFunction ( ) . hasFnAttribute ( Attribute :: NoRedZone ) ) return false ; const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const AArch64FunctionInfo * AFI = MF . getInfo < AArch64FunctionInfo > ( ) ; unsigned NumBytes = AFI -> getLocalStackSize ( ) ; return ! ( MFI . hasCalls ( ) || hasFP ( MF ) || NumBytes > 128 ) ; } </s>

Can this function use the red zone for local allocations .


<s> RISCVSubtarget & RISCVSubtarget :: initializeSubtargetDependencies ( const Triple & TT , StringRef CPU , StringRef TuneCPU , StringRef FS , StringRef ABIName ) { bool Is64Bit = TT . isArch64Bit ( ) ; std :: string CPUName = std :: string ( CPU ) ; std :: string TuneCPUName = std :: string ( TuneCPU ) ; if ( CPUName . empty ( ) ) CPUName = Is64Bit ? "generic-rv64" : "generic-rv32" ; if ( TuneCPUName . empty ( ) ) TuneCPUName = CPUName ; ParseSubtargetFeatures ( CPUName , TuneCPUName , FS ) ; if ( Is64Bit ) { XLenVT = MVT :: i64 ; XLen = 64 ; } TargetABI = RISCVABI :: computeTargetABI ( TT , getFeatureBits ( ) , ABIName ) ; RISCVFeatures :: validate ( TT , getFeatureBits ( ) ) ; return * this ; } </s>

initializeSubtargetDependencies - Initializes using a CPU , a TuneCPU , and feature string so that we can use initializer lists for subtarget initialization .


<s> unsigned R600InstrInfo :: isLegalUpTo ( const std :: vector < std :: vector < std :: pair < int , unsigned > > > & IGSrcs , const std :: vector < R600InstrInfo :: BankSwizzle > & Swz , const std :: vector < std :: pair < int , unsigned > > & TransSrcs , R600InstrInfo :: BankSwizzle TransSwz ) const { int Vector [ 4 ] [ 3 ] ; memset ( Vector , - 1 , sizeof ( Vector ) ) ; for ( unsigned i = 0 , e = IGSrcs . size ( ) ; i < e ; i ++ ) { const std :: vector < std :: pair < int , unsigned > > & Srcs = Swizzle ( IGSrcs [ i ] , Swz [ i ] ) ; for ( unsigned j = 0 ; j < 3 ; j ++ ) { const std :: pair < int , unsigned > & Src = Srcs [ j ] ; if ( Src . first < 0 || Src . first == 255 ) continue ; if ( Src . first == GET_REG_INDEX ( RI . getEncodingValue ( AMDGPU :: OQAP ) ) ) { if ( Swz [ i ] != R600InstrInfo :: ALU_VEC_012_SCL_210 && Swz [ i ] != R600InstrInfo :: ALU_VEC_021_SCL_122 ) { return false ; } continue ; } if ( Vector [ Src . second ] [ j ] < 0 ) Vector [ Src . second ] [ j ] = Src . first ; if ( Vector [ Src . second ] [ j ] != Src . first ) return i ; } } for ( unsigned i = 0 , e = TransSrcs . size ( ) ; i < e ; ++ i ) { const std :: pair < int , unsigned > & Src = TransSrcs [ i ] ; unsigned Cycle = getTransSwizzle ( TransSwz , i ) ; if ( Src . first < 0 ) continue ; if ( Src . first == 255 ) continue ; if ( Vector [ Src . second ] [ Cycle ] < 0 ) Vector [ Src . second ] [ Cycle ] = Src . first ; if ( Vector [ Src . second ] [ Cycle ] != Src . first ) return IGSrcs . size ( ) - 1 ; } return IGSrcs . size ( ) ; } </s>

returns how many MIs ( whose inputs are represented by IGSrcs ) can be packed in the same Instruction Group while meeting read port limitations given a Swz swizzle sequence .


<s> static int nvptx_dim_limit ( int axis ) { switch ( axis ) { case GOMP_DIM_WORKER : return PTX_WORKER_LENGTH ; case GOMP_DIM_VECTOR : return PTX_VECTOR_LENGTH ; default : break ; } return 0 ; } </s>

Return maximum dimension size , or zero for unbounded .


<s>
void
CSKYAsmBackend
::
relaxInstruction
(
MCInst
&
Inst
,
const
MCSubtargetInfo
&
STI
)
const
{
MCInst
Res
;
switch
(
Inst
.
getOpcode
(
)
)
{
default
:
Inst
.
dump
(
)
;
llvm_unreachable
(
"Opcode not expected!"
)
;
case
CSKY
::
LRW16
:
Res
.
setOpcode
(
CSKY
::
LRW32
)
;
Res
.
addOperand
(
Inst
.
getOperand
(
0
)
)
;
Res
.
addOperand
(
Inst
.
getOperand
(
1
)
)
;
break
;
case
CSKY
::
BR16
:
Res
.
setOpcode
(
CSKY
::
BR32
)
;
Res
.
addOperand
(
Inst
.
getOperand
(
0
)
)
;
break
;
case
CSKY
::
JBSR32
:
Res
.
setOpcode
(
CSKY
::
JSRI32
)
;
Res
.
addOperand
(
Inst
.
getOperand
(
1
)
)
;
break
;
case
CSKY
::
JBR32
:
Res
.
setOpcode
(
CSKY
::
JMPI32
)
;
Res
.
addOperand
(
Inst
.
getOperand
(
1
)
)
;
break
;
case
CSKY
::
JBT32
:
case
CSKY
::
JBF32
:
Res
.
setOpcode
(
Inst
.
getOpcode
(
)
==
CSKY
::
JBT32
CSKY
::
JBT_E
:
CSKY
::
JBF_E
)
;
Res
.
addOperand
(
Inst
.
getOperand
(
0
)
)
;
Res
.
addOperand
(
Inst
.
getOperand
(
1
)
)
;
Res
.
addOperand
(
Inst
.
getOperand
(
2
)
)
;
break
;
case
CSKY
::
JBR16
:
Res
.
setOpcode
(
CSKY
::
JBR32
)
;
Res
.
addOperand
(
Inst
.
getOperand
(
0
)
)
;
Res
.
addOperand
(
Inst
.
getOperand
(
1
)
)
;
break
;
case
CSKY
::
JBT16
:
case
CSKY
::
JBF16
:
unsigned
opcode
;
if
(
STI
.
getFeatureBits
(
)
[
CSKY
::
HasE2
]
)
opcode
=
Inst
.
getOpcode
(
)
==
CSKY
::
JBT16
CSKY
::
JBT32
:
CSKY
::
JBF32
;
else
opcode
=
Inst
.
getOpcode
(
)
==
CSKY
::
JBT16
CSKY
::
JBT_E
:
CSKY
::
JBF_E
;
Res
.
setOpcode
(
opcode
)
;
Res
.
addOperand
(
Inst
.
getOperand
(
0
)
)
;
Res
.
addOperand
(
Inst
.
getOperand
(
1
)
)
;
Res
.
addOperand
(
Inst
.
getOperand
(
2
)
)
;
break
;
}
Inst
=
std
::
move
(
Res
)
;
}
</s>

Relax the instruction in the given fragment to the next wider instruction .


<s> static rtx compute_frame_addr ( int offset_from_fp , int * next_scratch_regno ) { rtx base_reg_rtx , tmp_reg_rtx , offset_rtx ; int offset_from_base ; if ( frame_pointer_needed ) { base_reg_rtx = hard_frame_pointer_rtx ; offset_from_base = offset_from_fp ; } else { int offset_from_sp = compute_total_frame_size ( ) + offset_from_fp ; offset_from_base = offset_from_sp ; base_reg_rtx = stack_pointer_rtx ; } if ( offset_from_base == 0 ) return base_reg_rtx ; tmp_reg_rtx = gen_rtx_REG ( Pmode , ( * next_scratch_regno ) -- ) ; offset_rtx = GEN_INT ( offset_from_base ) ; if ( ! add_operand ( offset_rtx , Pmode ) ) { expand_set_cint64 ( tmp_reg_rtx , offset_rtx ) ; offset_rtx = tmp_reg_rtx ; } emit_insn ( gen_rtx_SET ( tmp_reg_rtx , gen_rtx_PLUS ( Pmode , base_reg_rtx , offset_rtx ) ) ) ; return tmp_reg_rtx ; } </s>

Returns an rtx for a stack slot at 'FP + offset_from_fp ' . If there is a frame pointer , it computes the value relative to that . Otherwise it uses the stack pointer .


<s>
void
AMDGPURegisterInfo
::
eliminateFrameIndex
(
MachineBasicBlock
::
iterator
MI
,
int
SPAdj
,
unsigned
FIOperandNum
,
RegScavenger
*
RS
)
const
{
llvm_unreachable
(
"Subroutines not supported yet"
)
;
}
</s>

This method must be overriden to eliminate abstract frame indices from instructions which may use them .


<s> bool MSP430AsmPrinter :: PrintAsmOperand ( const MachineInstr * MI , unsigned OpNo , unsigned AsmVariant , const char * ExtraCode ) { if ( ExtraCode && ExtraCode [ 0 ] ) return true ; printOperand ( MI , OpNo ) ; return false ; } </s>

PrintAsmOperand - Print out an operand for an inline asm expression .


"a nested function is not supported for reduced registers"

Emit RTL insns to initialize the variable parts of a trampoline .


<s>
bool
DeadCodeElimination
::
erase
(
const
SetVector
<
NodeId
>
&
Nodes
)
{
if
(
Nodes
.
empty
(
)
)
return
false
;
NodeList
DRNs
,
DINs
;
for
(
auto
I
:
Nodes
)
{
auto
BA
=
DFG
.
addr
<
NodeBase
*
>
(
I
)
;
uint16_t
Type
=
BA
.
Addr
->
getType
(
)
;
if
(
Type
==
NodeAttrs
::
Ref
)
{
DRNs
.
push_back
(
DFG
.
addr
<
RefNode
*
>
(
I
)
)
;
continue
;
}
uint16_t
Kind
=
BA
.
Addr
->
getKind
(
)
;
if
(
Kind
==
NodeAttrs
::
Stmt
||
Kind
==
NodeAttrs
::
Phi
)
{
for
(
auto
N
:
NodeAddr
<
CodeNode
*
>
(
BA
)
.
Addr
->
members
(
DFG
)
)
DRNs
.
push_back
(
N
)
;
DINs
.
push_back
(
DFG
.
addr
<
InstrNode
*
>
(
I
)
)
;
}
else
{
llvm_unreachable
(
"Unexpected code node"
)
;
return
false
;
}
}
auto
UsesFirst
=
[
]
(
NodeAddr
<
RefNode
*
>
A
,
NodeAddr
<
RefNode
*
>
B
)
->
bool
{
uint16_t
KindA
=
A
.
Addr
->
getKind
(
)
,
KindB
=
B
.
Addr
->
getKind
(
)
;
if
(
KindA
==
NodeAttrs
::
Use
&&
KindB
==
NodeAttrs
::
Def
)
return
true
;
if
(
KindA
==
NodeAttrs
::
Def
&&
KindB
==
NodeAttrs
::
Use
)
return
false
;
return
A
.
Id
<
B
.
Id
;
}
;
std
::
sort
(
DRNs
.
begin
(
)
,
DRNs
.
end
(
)
,
UsesFirst
)
;
if
(
trace
(
)
)
dbgs
(
)
<<
"Removing dead ref nodes:\n"
;
for
(
NodeAddr
<
RefNode
*
>
RA
:
DRNs
)
{
if
(
trace
(
)
)
dbgs
(
)
<<
"  "
<<
PrintNode
<
RefNode
*
>
(
RA
,
DFG
)
<<
'\n'
;
if
(
DFG
.
IsUse
(
RA
)
)
DFG
.
unlinkUse
(
RA
)
;
else
if
(
DFG
.
IsDef
(
RA
)
)
DFG
.
unlinkDef
(
RA
)
;
}
for
(
NodeAddr
<
InstrNode
*
>
IA
:
DINs
)
{
NodeAddr
<
BlockNode
*
>
BA
=
IA
.
Addr
->
getOwner
(
DFG
)
;
BA
.
Addr
->
removeMember
(
IA
,
DFG
)
;
if
(
!
DFG
.
IsCode
<
NodeAttrs
::
Stmt
>
(
IA
)
)
continue
;
MachineInstr
*
MI
=
NodeAddr
<
StmtNode
*
>
(
IA
)
.
Addr
->
getCode
(
)
;
if
(
trace
(
)
)
dbgs
(
)
<<
"erasing: "
<<
*
MI
;
MI
->
eraseFromParent
(
)
;
}
return
true
;
}
</s>

erase - Erases an element identified by Key , if it exists .

Hexagon
"Unexpected code node"
"Removing dead ref nodes:\n"
"  "
"erasing: "


<s>
static
void
rs6000_xcoff_output_toc_section_asm_op
(
const
char
*
data
ATTRIBUTE_UNUSED
)
{
if
(
TARGET_MINIMAL_TOC
)
{
if
(
!
toc_initialized
)
{
fputs
(
"\t.toc\nLCTOC..1:\n"
,
asm_out_file
)
;
fputs
(
"\t.tc toc_table[TC],toc_table[RW]\n"
,
asm_out_file
)
;
toc_initialized
=
1
;
}
fprintf
(
asm_out_file
,
"\t.csect toc_table[RW]%s\n"
,
(
TARGET_32BIT
""
:
",3"
)
)
;
}
else
fputs
(
"\t.toc\n"
,
asm_out_file
)
;
}
</s>

A get_unnamed_section callback , used for switching to toc_section .


<s> bool enableMachineScheduler ( ) const override { return true ; } </s>

Enable the MachineScheduler pass for all X86 subtargets .


<s> static void register_tuple_type ( unsigned int num_vectors , unsigned int type_index ) { aarch64_simd_type_info * type = & aarch64_simd_types [ type_index ] ; const char * vector_type_name = type -> name ; char tuple_type_name [ sizeof ( "bfloat16x4x2_t" ) ] ; snprintf ( tuple_type_name , sizeof ( tuple_type_name ) , "%.*sx%d_t" , ( int ) strlen ( vector_type_name ) - 4 , vector_type_name + 2 , num_vectors ) ; tuple_type_name [ 0 ] = TOLOWER ( tuple_type_name [ 0 ] ) ; tree vector_type = type -> itype ; tree array_type = build_array_type_nelts ( vector_type , num_vectors ) ; if ( type -> mode == DImode ) { if ( num_vectors == 2 ) SET_TYPE_MODE ( array_type , V2x1DImode ) ; else if ( num_vectors == 3 ) SET_TYPE_MODE ( array_type , V3x1DImode ) ; else if ( num_vectors == 4 ) SET_TYPE_MODE ( array_type , V4x1DImode ) ; } unsigned int alignment = known_eq ( GET_MODE_SIZE ( type -> mode ) , 16 ) ? 128 : 64 ; machine_mode tuple_mode = TYPE_MODE_RAW ( array_type ) ; gcc_assert ( VECTOR_MODE_P ( tuple_mode ) && TYPE_MODE ( array_type ) == tuple_mode && TYPE_ALIGN ( array_type ) == alignment ) ; tree field = build_decl ( input_location , FIELD_DECL , get_identifier ( "val" ) , array_type ) ; tree t = lang_hooks . types . simulate_record_decl ( input_location , tuple_type_name , make_array_slice ( & field , 1 ) ) ; gcc_assert ( TYPE_MODE_RAW ( t ) == TYPE_MODE ( t ) && ( flag_pack_struct || maximum_field_alignment || ( TYPE_MODE_RAW ( t ) == tuple_mode && TYPE_ALIGN ( t ) == alignment ) ) ) ; aarch64_simd_tuple_modes [ type_index ] [ num_vectors - 2 ] = tuple_mode ; aarch64_simd_tuple_types [ type_index ] [ num_vectors - 2 ] = t ; } </s>

Register the tuple type that contains NUM_VECTORS vectors of type TYPE .


<s> bool MCS51RegisterInfo :: shouldCoalesce ( MachineInstr * MI , const TargetRegisterClass * SrcRC , unsigned SubReg , const TargetRegisterClass * DstRC , unsigned DstSubReg , const TargetRegisterClass * NewRC , LiveIntervals & LIS ) const { if ( this -> getRegClass ( MCS51 :: PTRDISPREGSRegClassID ) -> hasSubClassEq ( NewRC ) ) { return false ; } return TargetRegisterInfo :: shouldCoalesce ( MI , SrcRC , SubReg , DstRC , DstSubReg , NewRC , LIS ) ; } </s>


"64-bit code requested on a subtarget that doesn't support it!"

This constructor initializes the data members to match that of the specified triple .


<s> void HexagonFrameLowering :: emitPrologue ( MachineFunction & MF , MachineBasicBlock & MBB ) const { auto & HST = static_cast < const HexagonSubtarget & > ( MF . getSubtarget ( ) ) ; auto & HRI = * HST . getRegisterInfo ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const std :: vector < CalleeSavedInfo > & CSI = MFI -> getCalleeSavedInfo ( ) ; MachineBasicBlock * PrologB = & MF . front ( ) , * EpilogB = nullptr ; if ( EnableShrinkWrapping ) findShrunkPrologEpilog ( MF , PrologB , EpilogB ) ; insertCSRSpillsInBlock ( * PrologB , CSI , HRI ) ; insertPrologueInBlock ( * PrologB ) ; if ( EpilogB ) { insertCSRRestoresInBlock ( * EpilogB , CSI , HRI ) ; insertEpilogueInBlock ( * EpilogB ) ; } else { for ( auto & B : MF ) if ( B . isReturnBlock ( ) ) insertCSRRestoresInBlock ( B , CSI , HRI ) ; for ( auto & B : MF ) if ( B . isReturnBlock ( ) ) insertEpilogueInBlock ( B ) ; } } </s>

emitProlog/emitEpilog - These methods insert prolog and epilog code into the function .


<s> static bool mips_callee_copies ( cumulative_args_t cum ATTRIBUTE_UNUSED , machine_mode mode ATTRIBUTE_UNUSED , const_tree type ATTRIBUTE_UNUSED , bool named ) { return mips_abi == ABI_EABI && named ; } </s>


<s> const uint16_t * OR1KRegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { const TargetFrameLowering * TFI = MF -> getTarget ( ) . getFrameLowering ( ) ; return TFI -> hasFP ( * MF ) ? CSR_FP_SaveList : CSR_SaveList ; } </s>


<s> uint64_t AArch64PLT :: emit ( MemoryRegion & pRegion ) { uint64_t result = 0x0 ; iterator it = begin ( ) ; unsigned char * buffer = pRegion . begin ( ) ; memcpy ( buffer , llvm :: cast < AArch64PLT0 > ( ( * it ) ) . getValue ( ) , AArch64PLT0 :: EntrySize ) ; result += AArch64PLT0 :: EntrySize ; ++ it ; AArch64PLT1 * plt1 = NULL ; AArch64PLT :: iterator ie = end ( ) ; while ( it != ie ) { plt1 = & ( llvm :: cast < AArch64PLT1 > ( * it ) ) ; memcpy ( buffer + result , plt1 -> getValue ( ) , AArch64PLT1 :: EntrySize ) ; result += AArch64PLT1 :: EntrySize ; ++ it ; } return result ; } </s>

Output the remark via the diagnostic handler and to the optimization record file .


<s> unsigned Mips16InstrInfo :: isLoadFromStackSlot ( const MachineInstr * MI , int & FrameIndex ) const { return 0 ; } </s>

isLoadFromStackSlot - If the specified machine instruction is a direct load from a stack slot , return the virtual or physical register number of the destination along with the FrameIndex of the loaded stack slot .


<s>
bool
ARMAsmPrinter
::
lowerOperand
(
const
MachineOperand
&
MO
,
MCOperand
&
MCOp
)
{
switch
(
MO
.
getType
(
)
)
{
default
:
llvm_unreachable
(
"unknown operand type"
)
;
case
MachineOperand
::
MO_Register
:
if
(
MO
.
isImplicit
(
)
&&
MO
.
getReg
(
)
!=
ARM
::
CPSR
)
return
false
;
assert
(
!
MO
.
getSubReg
(
)
&&
"Subregs should be eliminated!"
)
;
MCOp
=
MCOperand
::
CreateReg
(
MO
.
getReg
(
)
)
;
break
;
case
MachineOperand
::
MO_Immediate
:
MCOp
=
MCOperand
::
CreateImm
(
MO
.
getImm
(
)
)
;
break
;
case
MachineOperand
::
MO_MachineBasicBlock
:
MCOp
=
MCOperand
::
CreateExpr
(
MCSymbolRefExpr
::
Create
(
MO
.
getMBB
(
)
->
getSymbol
(
)
,
OutContext
)
)
;
break
;
case
MachineOperand
::
MO_GlobalAddress
:
MCOp
=
GetSymbolRef
(
MO
,
Mang
->
getSymbol
(
MO
.
getGlobal
(
)
)
)
;
break
;
case
MachineOperand
::
MO_ExternalSymbol
:
MCOp
=
GetSymbolRef
(
MO
,
GetExternalSymbolSymbol
(
MO
.
getSymbolName
(
)
)
)
;
break
;
case
MachineOperand
::
MO_JumpTableIndex
:
MCOp
=
GetSymbolRef
(
MO
,
GetJTISymbol
(
MO
.
getIndex
(
)
)
)
;
break
;
case
MachineOperand
::
MO_ConstantPoolIndex
:
MCOp
=
GetSymbolRef
(
MO
,
GetCPISymbol
(
MO
.
getIndex
(
)
)
)
;
break
;
case
MachineOperand
::
MO_BlockAddress
:
MCOp
=
GetSymbolRef
(
MO
,
GetBlockAddressSymbol
(
MO
.
getBlockAddress
(
)
)
)
;
break
;
case
MachineOperand
::
MO_FPImmediate
:
{
APFloat
Val
=
MO
.
getFPImm
(
)
->
getValueAPF
(
)
;
bool
ignored
;
Val
.
convert
(
APFloat
::
IEEEdouble
,
APFloat
::
rmTowardZero
,
&
ignored
)
;
MCOp
=
MCOperand
::
CreateFPImm
(
Val
.
convertToDouble
(
)
)
;
break
;
}
case
MachineOperand
::
MO_RegisterMask
:
return
false
;
}
return
true
;
}
</s>

Wrapper for MCInstLowering.lowerOperand ( ) for the tblgen'erated pseudo lowering .

ARM
ARM
"unknown operand type"
ARM::CPSR
"Subregs should be eliminated!"


<s> static rtx sparc_expand_builtin ( tree exp , rtx target , rtx subtarget ATTRIBUTE_UNUSED , enum machine_mode tmode , int ignore ATTRIBUTE_UNUSED ) { tree arglist ; tree fndecl = TREE_OPERAND ( TREE_OPERAND ( exp , 0 ) , 0 ) ; unsigned int icode = DECL_FUNCTION_CODE ( fndecl ) ; rtx pat , op [ 4 ] ; enum machine_mode mode [ 4 ] ; int arg_count = 0 ; mode [ arg_count ] = tmode ; if ( target == 0 || GET_MODE ( target ) != tmode || ! ( * insn_data [ icode ] . operand [ 0 ] . predicate ) ( target , tmode ) ) op [ arg_count ] = gen_reg_rtx ( tmode ) ; else op [ arg_count ] = target ; for ( arglist = TREE_OPERAND ( exp , 1 ) ; arglist ; arglist = TREE_CHAIN ( arglist ) ) { tree arg = TREE_VALUE ( arglist ) ; arg_count ++ ; mode [ arg_count ] = insn_data [ icode ] . operand [ arg_count ] . mode ; op [ arg_count ] = expand_expr ( arg , NULL_RTX , VOIDmode , 0 ) ; if ( ! ( * insn_data [ icode ] . operand [ arg_count ] . predicate ) ( op [ arg_count ] , mode [ arg_count ] ) ) op [ arg_count ] = copy_to_mode_reg ( mode [ arg_count ] , op [ arg_count ] ) ; } switch ( arg_count ) { case 1 : pat = GEN_FCN ( icode ) ( op [ 0 ] , op [ 1 ] ) ; break ; case 2 : pat = GEN_FCN ( icode ) ( op [ 0 ] , op [ 1 ] , op [ 2 ] ) ; break ; case 3 : pat = GEN_FCN ( icode ) ( op [ 0 ] , op [ 1 ] , op [ 2 ] , op [ 3 ] ) ; break ; default : gcc_unreachable ( ) ; } if ( ! pat ) return NULL_RTX ; emit_insn ( pat ) ; return op [ 0 ] ; } </s>

Handle TARGET_EXPAND_BUILTIN target hook . Expand builtin functions for sparc intrinsics .


<s> void AMDGPUTTIImpl :: getUnrollingPreferences ( Loop * L , TTI :: UnrollingPreferences & UP ) { UP . Threshold = 300 ; UP . MaxCount = UINT_MAX ; UP . Partial = true ; for ( const BasicBlock * BB : L -> getBlocks ( ) ) { for ( const Instruction & I : * BB ) { const GetElementPtrInst * GEP = dyn_cast < GetElementPtrInst > ( & I ) ; if ( ! GEP || GEP -> getAddressSpace ( ) != AMDGPUAS :: PRIVATE_ADDRESS ) continue ; const Value * Ptr = GEP -> getPointerOperand ( ) ; const AllocaInst * Alloca = dyn_cast < AllocaInst > ( GetUnderlyingObject ( Ptr ) ) ; if ( Alloca ) { UP . Threshold = 800 ; } } } } </s>

Get target-customized preferences for the generic loop unrolling transformation .


<s> static bool pa_assemble_integer ( rtx x , unsigned int size , int aligned_p ) { if ( size == UNITS_PER_WORD && aligned_p && function_label_operand ( x , VOIDmode ) ) { fputs ( size == 8 ? "\t.dword\t" : "\t.word\t" , asm_out_file ) ; if ( ! TARGET_FAST_INDIRECT_CALLS ) fputs ( "P%" , asm_out_file ) ; output_addr_const ( asm_out_file , x ) ; fputc ( '\n' , asm_out_file ) ; return true ; } return default_assemble_integer ( x , size , aligned_p ) ; } </s>

Target hook for assembling integer objects . This code handles aligned SI and DI integers specially , since function references must be preceded by P % .


<s> bool AArch64TargetLowering :: isMulAddWithConstProfitable ( SDValue AddNode , SDValue ConstNode ) const { const EVT VT = AddNode . getValueType ( ) ; if ( VT . isVector ( ) || VT . getScalarSizeInBits ( ) > 64 ) return true ; const ConstantSDNode * C1Node = cast < ConstantSDNode > ( AddNode . getOperand ( 1 ) ) ; const ConstantSDNode * C2Node = cast < ConstantSDNode > ( ConstNode ) ; const int64_t C1 = C1Node -> getSExtValue ( ) ; const APInt C1C2 = C1Node -> getAPIntValue ( ) * C2Node -> getAPIntValue ( ) ; if ( ! isLegalAddImmediate ( C1 ) || isLegalAddImmediate ( C1C2 . getSExtValue ( ) ) ) return true ; SmallVector < AArch64_IMM :: ImmInsnModel , 4 > Insn ; AArch64_IMM :: expandMOVImm ( C1C2 . getZExtValue ( ) , VT . getSizeInBits ( ) , Insn ) ; if ( Insn . size ( ) > 1 ) return false ; return true ; } </s>

Return true if it may be profitable to transform ( mul ( add x , c1 ) , c2 ) - > ( add ( mul x , c2 ) , c1 * c2 ) .


<s>
const
RegisterBank
&
AArch64RegisterBankInfo
::
getRegBankFromRegClass
(
const
TargetRegisterClass
&
RC
,
LLT
)
const
{
switch
(
RC
.
getID
(
)
)
{
case
AArch64
::
FPR8RegClassID
:
case
AArch64
::
FPR16RegClassID
:
case
AArch64
::
FPR16_loRegClassID
:
case
AArch64
::
FPR32_with_hsub_in_FPR16_loRegClassID
:
case
AArch64
::
FPR32RegClassID
:
case
AArch64
::
FPR64RegClassID
:
case
AArch64
::
FPR64_loRegClassID
:
case
AArch64
::
FPR128RegClassID
:
case
AArch64
::
FPR128_loRegClassID
:
case
AArch64
::
DDRegClassID
:
case
AArch64
::
DDDRegClassID
:
case
AArch64
::
DDDDRegClassID
:
case
AArch64
::
QQRegClassID
:
case
AArch64
::
QQQRegClassID
:
case
AArch64
::
QQQQRegClassID
:
return
getRegBank
(
AArch64
::
FPRRegBankID
)
;
case
AArch64
::
GPR32commonRegClassID
:
case
AArch64
::
GPR32RegClassID
:
case
AArch64
::
GPR32spRegClassID
:
case
AArch64
::
GPR32sponlyRegClassID
:
case
AArch64
::
GPR32argRegClassID
:
case
AArch64
::
GPR32allRegClassID
:
case
AArch64
::
GPR64commonRegClassID
:
case
AArch64
::
GPR64RegClassID
:
case
AArch64
::
GPR64spRegClassID
:
case
AArch64
::
GPR64sponlyRegClassID
:
case
AArch64
::
GPR64argRegClassID
:
case
AArch64
::
GPR64allRegClassID
:
case
AArch64
::
GPR64noipRegClassID
:
case
AArch64
::
GPR64common_and_GPR64noipRegClassID
:
case
AArch64
::
GPR64noip_and_tcGPR64RegClassID
:
case
AArch64
::
tcGPR64RegClassID
:
case
AArch64
::
rtcGPR64RegClassID
:
case
AArch64
::
WSeqPairsClassRegClassID
:
case
AArch64
::
XSeqPairsClassRegClassID
:
return
getRegBank
(
AArch64
::
GPRRegBankID
)
;
case
AArch64
::
CCRRegClassID
:
return
getRegBank
(
AArch64
::
CCRegBankID
)
;
default
:
llvm_unreachable
(
"Register class not supported"
)
;
}
}
</s>


<s> virtual const WDC65816InstrInfo * getInstrInfo ( ) const { return & InstrInfo ; } </s>


<s> bool SystemZMCAsmInfo :: isAcceptableChar ( char C ) const { if ( AssemblerDialect == AD_ATT ) return MCAsmInfo :: isAcceptableChar ( C ) ; return MCAsmInfo :: isAcceptableChar ( C ) || C == '#' ; } </s>

Return true if C is an acceptable character inside a symbol name .


<s> bool trackLivenessAfterRegAlloc ( const MachineFunction & MF ) const override { return true ; } </s>

Returns true if the live-ins should be tracked after register allocation .


<s> const RegClassWeight & HexagonRegisterInfo :: getRegClassWeight ( const TargetRegisterClass * RC ) const { static const RegClassWeight RCWeightTable [ ] = { { 1 , 32 } , { 1 , 8 } , { 1 , 4 } , { 2 , 16 } , { 0 , 0 } } ; return RCWeightTable [ RC -> getID ( ) ] ; } </s>

Get the weight in units of pressure for this register class .


<s> static void reorder_var_tracking_notes ( void ) { basic_block bb ; FOR_EACH_BB_FN ( bb , cfun ) { rtx_insn * insn , * next ; rtx_insn * queue = NULL ; bool in_bundle = false ; for ( insn = BB_HEAD ( bb ) ; insn != BB_END ( bb ) ; insn = next ) { next = NEXT_INSN ( insn ) ; if ( INSN_P ( insn ) ) { if ( GET_MODE ( insn ) == QImode ) { while ( queue ) { rtx_insn * next_queue = PREV_INSN ( queue ) ; SET_PREV_INSN ( NEXT_INSN ( insn ) ) = queue ; SET_NEXT_INSN ( queue ) = NEXT_INSN ( insn ) ; SET_NEXT_INSN ( insn ) = queue ; SET_PREV_INSN ( queue ) = insn ; queue = next_queue ; } in_bundle = false ; } else if ( GET_MODE ( insn ) == SImode ) in_bundle = true ; } else if ( NOTE_P ( insn ) && NOTE_KIND ( insn ) == NOTE_INSN_VAR_LOCATION ) { if ( in_bundle ) { rtx_insn * prev = PREV_INSN ( insn ) ; SET_PREV_INSN ( next ) = prev ; SET_NEXT_INSN ( prev ) = next ; SET_PREV_INSN ( insn ) = queue ; queue = insn ; } } } } } </s>

Ensure that no var tracking notes are emitted in the middle of a three-instruction bundle .


<s> bool sh2a_is_function_vector_call ( rtx x ) { if ( GET_CODE ( x ) == SYMBOL_REF && ( SYMBOL_REF_FLAGS ( x ) & SYMBOL_FLAG_FUNCVEC_FUNCTION ) ) { tree tr = SYMBOL_REF_DECL ( x ) ; if ( sh2a_function_vector_p ( tr ) ) return true ; } return false ; } </s>

Returns true if current function has been assigned the attribute 'function_vector ' .


<s> tree i960_build_va_list ( ) { return build_array_type ( unsigned_type_node , build_index_type ( size_one_node ) ) ; } </s>

Define the ` __builtin_va_list ' type for the ABI .


<s> unsigned getStackAlignment ( ) const { return stackAlignment ; } </s>

Returns the minimum alignment known to hold of the stack frame on entry to the function and which must be maintained by every function for this subtarget .


<s> static void arm_insert_attributes ( tree fndecl , tree * attributes ) { const char * mode ; if ( ! TARGET_FLIP_THUMB ) return ; if ( TREE_CODE ( fndecl ) != FUNCTION_DECL || DECL_EXTERNAL ( fndecl ) || DECL_BUILT_IN ( fndecl ) || DECL_ARTIFICIAL ( fndecl ) ) return ; if ( current_function_decl ) { mode = TARGET_THUMB ? "thumb" : "arm" ; add_attribute ( mode , attributes ) ; return ; } if ( lookup_attribute ( "target" , * attributes ) != NULL ) return ; mode = thumb_flipper ? "thumb" : "arm" ; add_attribute ( mode , attributes ) ; thumb_flipper = ! thumb_flipper ; } </s>

For testing . Insert thumb or arm modes alternatively on functions .

arm "thumb" "arm" "target" "thumb" "arm"


runOnMachineFunction - Emit the function body .

NVPTX NVPTX NVPTX::VRFrame NVPTX::VRFrame


<s> unsigned CSKYInstrInfo :: isLoadFromStackSlot ( const MachineInstr & MI , int & FrameIndex ) const { switch ( MI . getOpcode ( ) ) { default : return 0 ; case CSKY :: LD16B : case CSKY :: LD16H : case CSKY :: LD16W : case CSKY :: LD32B : case CSKY :: LD32BS : case CSKY :: LD32H : case CSKY :: LD32HS : case CSKY :: LD32W : case CSKY :: RESTORE_CARRY : break ; } if ( MI . getOperand ( 1 ) . isFI ( ) && MI . getOperand ( 2 ) . isImm ( ) && MI . getOperand ( 2 ) . getImm ( ) == 0 ) { FrameIndex = MI . getOperand ( 1 ) . getIndex ( ) ; return MI . getOperand ( 0 ) . getReg ( ) ; } return 0 ; } </s>