<s> unsigned WebAssemblyTTIImpl :: getArithmeticInstrCost ( unsigned Opcode , Type * Ty , TTI :: OperandValueKind Opd1Info , TTI :: OperandValueKind Opd2Info , TTI :: OperandValueProperties Opd1PropInfo , TTI :: OperandValueProperties Opd2PropInfo , ArrayRef < const Value * > Args ) { unsigned Cost = BasicTTIImplBase < WebAssemblyTTIImpl > :: getArithmeticInstrCost ( Opcode , Ty , Opd1Info , Opd2Info , Opd1PropInfo , Opd2PropInfo ) ; if ( VectorType * VTy = dyn_cast < VectorType > ( Ty ) ) { switch ( Opcode ) { case Instruction :: LShr : case Instruction :: AShr : case Instruction :: Shl : if ( Opd2Info != TTI :: OK_UniformValue && Opd2Info != TTI :: OK_UniformConstantValue ) Cost = VTy -> getNumElements ( ) * ( TargetTransformInfo :: TCC_Basic + getArithmeticInstrCost ( Opcode , VTy -> getElementType ( ) ) + TargetTransformInfo :: TCC_Basic ) ; break ; } } return Cost ; } </s>

This is an approximation of reciprocal throughput of a math/logic op .


<s> void analyze ( MachineBasicBlock & DefBlock , ArrayRef < MachineBasicBlock * > IncomingBlocks ) { assert ( Stack . empty ( ) ) ; ReachableMap . clear ( ) ; ReachableOrdered . clear ( ) ; Predecessors . clear ( ) ; ReachableMap . try_emplace ( & DefBlock , false ) ; ReachableOrdered . push_back ( & DefBlock ) ; for ( MachineBasicBlock * MBB : IncomingBlocks ) { if ( MBB == & DefBlock ) { ReachableMap [ & DefBlock ] = true ; continue ; } ReachableMap . try_emplace ( MBB , false ) ; ReachableOrdered . push_back ( MBB ) ; bool Divergent = false ; for ( MachineInstr & MI : MBB -> terminators ( ) ) { if ( MI . getOpcode ( ) == AMDGPU :: SI_NON_UNIFORM_BRCOND_PSEUDO || MI . getOpcode ( ) == AMDGPU :: SI_IF || MI . getOpcode ( ) == AMDGPU :: SI_ELSE || MI . getOpcode ( ) == AMDGPU :: SI_LOOP ) { Divergent = true ; break ; } } if ( Divergent && PDT . dominates ( & DefBlock , MBB ) ) { for ( MachineBasicBlock * Succ : MBB -> successors ( ) ) Stack . push_back ( Succ ) ; } } while ( ! Stack . empty ( ) ) { MachineBasicBlock * MBB = Stack . pop_back_val ( ) ; if ( ! ReachableMap . try_emplace ( MBB , false ) . second ) continue ; ReachableOrdered . push_back ( MBB ) ; for ( MachineBasicBlock * Succ : MBB -> successors ( ) ) Stack . push_back ( Succ ) ; } for ( MachineBasicBlock * MBB : ReachableOrdered ) { bool HaveReachablePred = false ; for ( MachineBasicBlock * Pred : MBB -> predecessors ( ) ) { if ( ReachableMap . count ( Pred ) ) { HaveReachablePred = true ; } else { Stack . push_back ( Pred ) ; } } if ( ! HaveReachablePred ) ReachableMap [ MBB ] = true ; if ( HaveReachablePred ) { for ( MachineBasicBlock * UnreachablePred : Stack ) { if ( ! llvm :: is_contained ( Predecessors , UnreachablePred ) ) Predecessors . push_back ( UnreachablePred ) ; } } Stack . clear ( ) ; } } </s>

analyze - set CurLI to the specified interval , and analyze how it may be split .


<s> virtual bool runOnMachineFunction ( MachineFunction & MF ) { X86MachineFunctionInfo * MFI = MF . getInfo < X86MachineFunctionInfo > ( ) ; if ( MFI -> getNumLocalDynamicTLSAccesses ( ) < 2 ) { return false ; } MachineDominatorTree * DT = & getAnalysis < MachineDominatorTree > ( ) ; return VisitNode ( DT -> getRootNode ( ) , 0 ) ; } </s>

runOnMachineFunction - Emit the function body .


<s>
const
MCFixupKindInfo
&
getFixupKindInfo
(
MCFixupKind
Kind
)
const
override
{
const
static
MCFixupKindInfo
Infos
[
AArch64
::
NumTargetFixupKinds
]
=
{
{
"fixup_aarch64_pcrel_adr_imm21"
,
0
,
32
,
PCRelFlagVal
}
,
{
"fixup_aarch64_pcrel_adrp_imm21"
,
0
,
32
,
PCRelFlagVal
}
,
{
"fixup_aarch64_add_imm12"
,
10
,
12
,
0
}
,
{
"fixup_aarch64_ldst_imm12_scale1"
,
10
,
12
,
0
}
,
{
"fixup_aarch64_ldst_imm12_scale2"
,
10
,
12
,
0
}
,
{
"fixup_aarch64_ldst_imm12_scale4"
,
10
,
12
,
0
}
,
{
"fixup_aarch64_ldst_imm12_scale8"
,
10
,
12
,
0
}
,
{
"fixup_aarch64_ldst_imm12_scale16"
,
10
,
12
,
0
}
,
{
"fixup_aarch64_ldr_pcrel_imm19"
,
5
,
19
,
PCRelFlagVal
}
,
{
"fixup_aarch64_movw"
,
5
,
16
,
0
}
,
{
"fixup_aarch64_pcrel_branch14"
,
5
,
14
,
PCRelFlagVal
}
,
{
"fixup_aarch64_pcrel_branch19"
,
5
,
19
,
PCRelFlagVal
}
,
{
"fixup_aarch64_pcrel_branch26"
,
0
,
26
,
PCRelFlagVal
}
,
{
"fixup_aarch64_pcrel_call26"
,
0
,
26
,
PCRelFlagVal
}
}
;
if
(
Kind
>=
FirstLiteralRelocationKind
)
return
MCAsmBackend
::
getFixupKindInfo
(
FK_NONE
)
;
if
(
Kind
<
FirstTargetFixupKind
)
return
MCAsmBackend
::
getFixupKindInfo
(
Kind
)
;
assert
(
unsigned
(
Kind
FirstTargetFixupKind
)
<
getNumFixupKinds
(
)
&&
"Invalid kind!"
)
;
return
Infos
[
Kind
FirstTargetFixupKind
]
;
}
</s>


"Can't store this register to stack slot"

Store the specified register of the given register class to the specified stack frame index .


<s> void X86RegisterInfo :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { if ( ! hasReservedCallFrame ( MF ) ) { MachineInstr * Old = I ; uint64_t Amount = Old -> getOperand ( 0 ) . getImm ( ) ; if ( Amount != 0 ) { Amount = ( Amount + StackAlign - 1 ) / StackAlign * StackAlign ; MachineInstr * New = 0 ; if ( Old -> getOpcode ( ) == getCallFrameSetupOpcode ( ) ) { New = BuildMI ( MF , Old -> getDebugLoc ( ) , TII . get ( getSUBriOpcode ( Is64Bit , Amount ) ) , StackPtr ) . addReg ( StackPtr ) . addImm ( Amount ) ; } else { assert ( Old -> getOpcode ( ) == getCallFrameDestroyOpcode ( ) ) ; uint64_t CalleeAmt = Old -> getOperand ( 1 ) . getImm ( ) ; Amount -= CalleeAmt ; if ( Amount ) { unsigned Opc = getADDriOpcode ( Is64Bit , Amount ) ; New = BuildMI ( MF , Old -> getDebugLoc ( ) , TII . get ( Opc ) , StackPtr ) . addReg ( StackPtr ) . addImm ( Amount ) ; } } if ( New ) { New -> getOperand ( 3 ) . setIsDead ( ) ; MBB . insert ( I , New ) ; } } } else if ( I -> getOpcode ( ) == getCallFrameDestroyOpcode ( ) ) { if ( uint64_t CalleeAmt = I -> getOperand ( 1 ) . getImm ( ) ) { unsigned Opc = getSUBriOpcode ( Is64Bit , CalleeAmt ) ; MachineInstr * Old = I ; MachineInstr * New = BuildMI ( MF , Old -> getDebugLoc ( ) , TII . get ( Opc ) , StackPtr ) . addReg ( StackPtr ) . addImm ( CalleeAmt ) ; New -> getOperand ( 3 ) . setIsDead ( ) ; MBB . insert ( I , New ) ; } } MBB . erase ( I ) ; } </s>

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .


<s> static void mips_setup_incoming_varargs ( cumulative_args_t cum , machine_mode mode , tree type , int * pretend_size ATTRIBUTE_UNUSED , int no_rtl ) { CUMULATIVE_ARGS local_cum ; int gp_saved , fp_saved ; local_cum = * get_cumulative_args ( cum ) ; mips_function_arg_advance ( pack_cumulative_args ( & local_cum ) , mode , type , true ) ; gp_saved = MAX_ARGS_IN_REGISTERS - local_cum . num_gprs ; fp_saved = ( EABI_FLOAT_VARARGS_P ? MAX_ARGS_IN_REGISTERS - local_cum . num_fprs : 0 ) ; if ( ! no_rtl ) { if ( gp_saved > 0 ) { rtx ptr , mem ; ptr = plus_constant ( Pmode , virtual_incoming_args_rtx , REG_PARM_STACK_SPACE ( cfun -> decl ) - gp_saved * UNITS_PER_WORD ) ; mem = gen_frame_mem ( BLKmode , ptr ) ; set_mem_alias_set ( mem , get_varargs_alias_set ( ) ) ; move_block_from_reg ( local_cum . num_gprs + GP_ARG_FIRST , mem , gp_saved ) ; } if ( fp_saved > 0 ) { machine_mode mode ; int off , i ; off = ROUND_DOWN ( - gp_saved * UNITS_PER_WORD , UNITS_PER_FPVALUE ) ; off -= fp_saved * UNITS_PER_FPREG ; mode = TARGET_SINGLE_FLOAT ? SFmode : DFmode ; for ( i = local_cum . num_fprs ; i < MAX_ARGS_IN_REGISTERS ; i += MAX_FPRS_PER_FMT ) { rtx ptr , mem ; ptr = plus_constant ( Pmode , virtual_incoming_args_rtx , off ) ; mem = gen_frame_mem ( mode , ptr ) ; set_mem_alias_set ( mem , get_varargs_alias_set ( ) ) ; mips_emit_move ( mem , gen_rtx_REG ( mode , FP_ARG_FIRST + i ) ) ; off += UNITS_PER_HWFPVALUE ; } } } if ( REG_PARM_STACK_SPACE ( cfun -> decl ) == 0 ) cfun -> machine -> varargs_size = ( gp_saved * UNITS_PER_WORD + fp_saved * UNITS_PER_FPREG ) ; } </s>


"TPC DAG->DAG Pattern Instruction Selection"

getPassName - Return a nice clean name for a pass .


"@c Copyright (C) 2012-2016 Free Software Foundation, Inc.\n"

"@c For copying conditions, see the file "

"@c This file is generated automatically using\n"

Main program to convert flat files into built-in initialization code .


"RVV type %qT does not have a fixed size"

"RVV type %qT does not have a defined alignment"

"variables of type %qT cannot have thread-local"

"member variables cannot have RVV type %qT"

"array elements cannot have RVV type %qT"

"cannot allocate objects with RVV type %qT"

"cannot delete objects with RVV type %qT"

Implement TARGET_VERIFY_TYPE_CONTEXT for RVV types .


<s> unsigned PPCTTIImpl :: getCacheLineSize ( ) { return CacheLineSize ; } </s>

Return the target cache line size in bytes .


<s> bool nds32_can_use_bitci_p ( HOST_WIDE_INT ival ) { return ( TARGET_ISA_V3 && ( ival < 0 ) && satisfies_constraint_Iu15 ( gen_int_mode ( ~ ival , SImode ) ) ) ; } </s>

Function to check if 'bitci ' instruction can be used with IVAL .


<s> static int visium_register_move_cost ( machine_mode mode , reg_class_t from , reg_class_t to ) { const int numwords = ( GET_MODE_SIZE ( mode ) <= UNITS_PER_WORD ) ? 1 : 2 ; if ( from == MDB || to == MDB ) return 4 ; else if ( from == MDC || to == MDC || ( from == FP_REGS ) != ( to == FP_REGS ) ) return 4 * numwords ; else return 2 * numwords ; } </s>

Return the cost of moving data of mode MODE from a register in class FROM to one in class TO . A value of 2 is the default ; other values are interpreted relative to that .


<s>
bool
X86InstrInfo
::
isReallyTriviallyReMaterializable
(
const
MachineInstr
*
MI
)
const
{
switch
(
MI
->
getOpcode
(
)
)
{
default
:
break
;
case
X86
::
MOV8rm
:
case
X86
::
MOV16rm
:
case
X86
::
MOV32rm
:
case
X86
::
MOV64rm
:
case
X86
::
LD_Fp64m
:
case
X86
::
MOVSSrm
:
case
X86
::
MOVSDrm
:
case
X86
::
MOVAPSrm
:
case
X86
::
MOVAPDrm
:
case
X86
::
MOVDQArm
:
case
X86
::
MMX_MOVD64rm
:
case
X86
::
MMX_MOVQ64rm
:
{
if
(
MI
->
getOperand
(
1
)
.
isReg
(
)
&&
MI
->
getOperand
(
2
)
.
isImm
(
)
&&
MI
->
getOperand
(
3
)
.
isReg
(
)
&&
MI
->
getOperand
(
3
)
.
getReg
(
)
==
0
&&
CanRematLoadWithDispOperand
(
MI
->
getOperand
(
4
)
,
TM
)
)
{
unsigned
BaseReg
=
MI
->
getOperand
(
1
)
.
getReg
(
)
;
if
(
BaseReg
==
0
||
BaseReg
==
X86
::
RIP
)
return
true
;
if
(
!
ReMatPICStubLoad
&&
MI
->
getOperand
(
4
)
.
isGlobal
(
)
)
return
false
;
const
MachineFunction
&
MF
=
*
MI
->
getParent
(
)
->
getParent
(
)
;
const
MachineRegisterInfo
&
MRI
=
MF
.
getRegInfo
(
)
;
bool
isPICBase
=
false
;
for
(
MachineRegisterInfo
::
def_iterator
I
=
MRI
.
def_begin
(
BaseReg
)
,
E
=
MRI
.
def_end
(
)
;
I
!=
E
;
++
I
)
{
MachineInstr
*
DefMI
=
I
.
getOperand
(
)
.
getParent
(
)
;
if
(
DefMI
->
getOpcode
(
)
!=
X86
::
MOVPC32r
)
return
false
;
assert
(
!
isPICBase
&&
"More than one PIC base?"
)
;
isPICBase
=
true
;
}
return
isPICBase
;
}
return
false
;
}
case
X86
::
LEA32r
:
case
X86
::
LEA64r
:
{
if
(
MI
->
getOperand
(
2
)
.
isImm
(
)
&&
MI
->
getOperand
(
3
)
.
isReg
(
)
&&
MI
->
getOperand
(
3
)
.
getReg
(
)
==
0
&&
!
MI
->
getOperand
(
4
)
.
isReg
(
)
)
{
if
(
!
MI
->
getOperand
(
1
)
.
isReg
(
)
)
return
true
;
unsigned
BaseReg
=
MI
->
getOperand
(
1
)
.
getReg
(
)
;
if
(
BaseReg
==
0
)
return
true
;
const
MachineFunction
&
MF
=
*
MI
->
getParent
(
)
->
getParent
(
)
;
const
MachineRegisterInfo
&
MRI
=
MF
.
getRegInfo
(
)
;
return
regIsPICBase
(
BaseReg
,
MRI
)
;
}
return
false
;
}
}
return
true
;
}
</s>

For instructions with opcodes for which the M_REMATERIALIZABLE flag is set , this hook lets the target specify whether the instruction is actually trivially rematerializable , taking into consideration its operands .


<s> void cris_asm_output_symbol_ref ( FILE * file , rtx x ) { gcc_assert ( GET_CODE ( x ) == SYMBOL_REF ) ; assemble_name ( file , XSTR ( x , 0 ) ) ; } </s>

Worker function for ASM_OUTPUT_SYMBOL_REF .


<s> bool ARMSubtarget :: enablePostRAScheduler ( CodeGenOpt :: Level OptLevel , TargetSubtargetInfo :: AntiDepBreakMode & Mode , RegClassVector & CriticalPathRCs ) const { Mode = TargetSubtargetInfo :: ANTIDEP_CRITICAL ; CriticalPathRCs . clear ( ) ; CriticalPathRCs . push_back ( & ARM :: GPRRegClass ) ; return PostRAScheduler && OptLevel >= CodeGenOpt :: Default ; } </s>

True if the subtarget should run a scheduler after register allocation .


<s> static bool split_delayed_nonbranch ( rtx_insn * insn ) { int code = recog_memoized ( insn ) ; enum attr_type type ; rtx_insn * i1 ; rtx newpat , src , dest ; rtx pat = PATTERN ( insn ) ; rtvec rtv ; int delay ; if ( GET_CODE ( pat ) == COND_EXEC ) pat = COND_EXEC_CODE ( pat ) ; if ( code < 0 || GET_CODE ( pat ) != SET ) return false ; src = SET_SRC ( pat ) ; dest = SET_DEST ( pat ) ; if ( ! REG_P ( dest ) ) return false ; type = get_attr_type ( insn ) ; if ( code >= 0 && ( type == TYPE_LOAD || type == TYPE_LOADN ) ) { if ( ! MEM_P ( src ) && ( GET_CODE ( src ) != ZERO_EXTEND || ! MEM_P ( XEXP ( src , 0 ) ) ) ) return false ; if ( GET_MODE_SIZE ( GET_MODE ( dest ) ) > 4 && ( GET_MODE_SIZE ( GET_MODE ( dest ) ) != 8 || ! TARGET_LDDW ) ) return false ; rtv = gen_rtvec ( 2 , GEN_INT ( REGNO ( SET_DEST ( pat ) ) ) , SET_SRC ( pat ) ) ; newpat = gen_load_shadow ( SET_DEST ( pat ) ) ; pat = gen_rtx_UNSPEC ( VOIDmode , rtv , UNSPEC_REAL_LOAD ) ; delay = 4 ; } else if ( code >= 0 && ( type == TYPE_MPY2 || type == TYPE_MPY4 ) ) { if ( GET_MODE ( dest ) == SFmode ) return false ; rtv = gen_rtvec ( 2 , GEN_INT ( REGNO ( SET_DEST ( pat ) ) ) , SET_SRC ( pat ) ) ; newpat = gen_mult_shadow ( SET_DEST ( pat ) ) ; pat = gen_rtx_UNSPEC ( VOIDmode , rtv , UNSPEC_REAL_MULT ) ; delay = type == TYPE_MPY2 ? 1 : 3 ; } else return false ; pat = duplicate_cond ( pat , insn ) ; newpat = duplicate_cond ( newpat , insn ) ; i1 = emit_insn_before ( pat , insn ) ; PATTERN ( insn ) = newpat ; INSN_CODE ( insn ) = - 1 ; recog_memoized ( insn ) ; recog_memoized ( i1 ) ; record_delay_slot_pair ( i1 , insn , delay , 0 ) ; return true ; } </s>

If INSN is a multi-cycle insn that should be handled properly in modulo-scheduling , split it into a real insn and a shadow . Return true if we made a change . It is valid for us to fail to split an insn ; the caller has to deal with the possibility . Currently we handle loads and most mpy2 and mpy4 insns .


<s> bool AArch64TargetLowering :: needsFixedCatchObjects ( ) const { return false ; } </s>


"cannot use %<va_start%> in interrupt function"

Implement the stdarg/varargs va_start macro . STDARG_P is non-zero if this is stdarg.h instead of varargs.h . VALIST is the tree of the va_list variable to initialize . NEXTARG is the machine independent notion of the 'next ' argument after the variable arguments .


<s>
void
assignValueToAddress
(
Register
ValVReg
,
Register
Addr
,
uint64_t
Size
,
MachinePointerInfo
&
MPO
,
CCValAssign
&
VA
)
override
{
assert
(
(
Size
==
1
||
Size
==
2
||
Size
==
4
||
Size
==
8
)
&&
"Unsupported size"
)
;
if
(
VA
.
getLocInfo
(
)
==
CCValAssign
::
SExt
||
VA
.
getLocInfo
(
)
==
CCValAssign
::
ZExt
)
{
Size
=
4
;
assert
(
MRI
.
getType
(
ValVReg
)
.
isScalar
(
)
&&
"Only scalars supported atm"
)
;
auto
LoadVReg
=
buildLoad
(
LLT
::
scalar
(
32
)
,
Addr
,
Size
,
MPO
)
;
MIRBuilder
.
buildTrunc
(
ValVReg
,
LoadVReg
)
;
}
else
{
buildLoad
(
ValVReg
,
Addr
,
Size
,
MPO
)
;
}
}
</s>

An overload which takes an ArgInfo if additional information about the arg is needed .


<s>
bool
AArch64InstrInfo
::
isAddImmediate
(
const
MachineInstr
&
MI
,
const
MachineOperand
*
&
Destination
,
const
MachineOperand
*
&
Source
,
int64_t
&
Offset
)
const
{
int
Sign
=
1
;
switch
(
MI
.
getOpcode
(
)
)
{
default
:
return
false
;
case
AArch64
::
SUBWri
:
case
AArch64
::
SUBXri
:
case
AArch64
::
SUBSWri
:
case
AArch64
::
SUBSXri
:
Sign
*=
1
;
LLVM_FALLTHROUGH
;
case
AArch64
::
ADDSWri
:
case
AArch64
::
ADDSXri
:
case
AArch64
::
ADDWri
:
case
AArch64
::
ADDXri
:
{
if
(
!
MI
.
getOperand
(
0
)
.
isReg
(
)
||
!
MI
.
getOperand
(
1
)
.
isReg
(
)
||
!
MI
.
getOperand
(
2
)
.
isImm
(
)
)
return
false
;
Source
=
&
MI
.
getOperand
(
1
)
;
Offset
=
MI
.
getOperand
(
2
)
.
getImm
(
)
*
Sign
;
int
Shift
=
MI
.
getOperand
(
3
)
.
getImm
(
)
;
assert
(
(
Shift
==
0
||
Shift
==
12
)
&&
"Shift can be either 0 or 12"
)
;
Offset
=
Offset
<<
Shift
;
}
}
Destination
=
&
MI
.
getOperand
(
0
)
;
return
true
;
}
</s>

If the specific machine instruction is an instruction that adds an immediate value and a register , and stores the result in the given register Reg , return a pair of the source register and the offset which has been added .


<s> static void rs6000_init_sched_context ( void * _sc , bool clean_p ) { rs6000_sched_context_t sc = ( rs6000_sched_context_t ) _sc ; if ( clean_p ) { sc -> cached_can_issue_more = 0 ; sc -> last_scheduled_insn = NULL ; sc -> load_store_pendulum = 0 ; sc -> divide_cnt = 0 ; sc -> vec_pairing = 0 ; } else { sc -> cached_can_issue_more = cached_can_issue_more ; sc -> last_scheduled_insn = last_scheduled_insn ; sc -> load_store_pendulum = load_store_pendulum ; sc -> divide_cnt = divide_cnt ; sc -> vec_pairing = vec_pairing ; } } </s>

If CLEAN_P is true then initializes _SC with clean data , and from the global context otherwise .


<s> int NVPTXTTIImpl :: getArithmeticInstrCost ( unsigned Opcode , Type * Ty , TTI :: OperandValueKind Opd1Info , TTI :: OperandValueKind Opd2Info , TTI :: OperandValueProperties Opd1PropInfo , TTI :: OperandValueProperties Opd2PropInfo ) { std :: pair < int , MVT > LT = TLI -> getTypeLegalizationCost ( DL , Ty ) ; int ISD = TLI -> InstructionOpcodeToISD ( Opcode ) ; switch ( ISD ) { default : return BaseT :: getArithmeticInstrCost ( Opcode , Ty , Opd1Info , Opd2Info , Opd1PropInfo , Opd2PropInfo ) ; case ISD :: ADD : case ISD :: MUL : case ISD :: XOR : case ISD :: OR : case ISD :: AND : if ( LT . second . SimpleTy == MVT :: i64 ) return 2 * LT . first ; return BaseT :: getArithmeticInstrCost ( Opcode , Ty , Opd1Info , Opd2Info , Opd1PropInfo , Opd2PropInfo ) ; } } </s>

This is an approximation of reciprocal throughput of a math/logic op .

NVPTX NVPTX ISD::ADD ISD::MUL ISD::XOR ISD::OR ISD::AND MVT::i64 2


<s> int xtensa_emit_move_sequence ( rtx * operands , enum machine_mode mode ) { if ( CONSTANT_P ( operands [ 1 ] ) && ( GET_CODE ( operands [ 1 ] ) != CONST_INT || ! xtensa_simm12b ( INTVAL ( operands [ 1 ] ) ) ) ) { if ( ! TARGET_CONST16 ) operands [ 1 ] = force_const_mem ( SImode , operands [ 1 ] ) ; if ( mode != SImode ) { if ( register_operand ( operands [ 0 ] , mode ) ) { operands [ 0 ] = simplify_gen_subreg ( SImode , operands [ 0 ] , mode , 0 ) ; emit_move_insn ( operands [ 0 ] , operands [ 1 ] ) ; return 1 ; } else { operands [ 1 ] = force_reg ( SImode , operands [ 1 ] ) ; operands [ 1 ] = gen_lowpart_SUBREG ( mode , operands [ 1 ] ) ; } } } if ( ! ( reload_in_progress | reload_completed ) && ! xtensa_valid_move ( mode , operands ) ) operands [ 1 ] = force_reg ( mode , operands [ 1 ] ) ; operands [ 1 ] = xtensa_copy_incoming_a7 ( operands [ 1 ] ) ; if ( reload_in_progress ) { operands [ 0 ] = fixup_subreg_mem ( operands [ 0 ] ) ; operands [ 1 ] = fixup_subreg_mem ( operands [ 1 ] ) ; } return 0 ; } </s>

Emit insns to move operands [ 1 ] into operands [ 0 ] . Return 1 if we have written out everything that needs to be done to do the move . Otherwise , return 0 and the caller will emit the move normally .


<s> static bool mflip_mips16_use_mips16_p ( tree decl ) { const char * name ; bool base_is_mips16 = ( mips_base_compression_flags & MASK_MIPS16 ) != 0 ; if ( ! DECL_NAME ( decl ) ) return ! base_is_mips16 ; if ( ! mflip_mips16_htab ) mflip_mips16_htab = hash_map < const char * , bool , mips16_flip_traits > :: create_ggc ( 37 ) ; name = IDENTIFIER_POINTER ( DECL_NAME ( decl ) ) ; bool existed ; bool * slot = & mflip_mips16_htab -> get_or_insert ( name , & existed ) ; if ( ! existed ) { mips16_flipper = ! mips16_flipper ; * slot = mips16_flipper ? ! base_is_mips16 : base_is_mips16 ; } return * slot ; } </s>

DECL is a function that needs a default `` mips16 '' or `` nomips16 '' attribute for -mflip-mips16 . Return true if it should use `` mips16 '' and false if it should use `` nomips16 '' .


<s>
const
MCExpr
*
ARMElfTargetObjectFile
::
getTTypeGlobalReference
(
const
GlobalValue
*
GV
,
Mangler
*
Mang
,
MachineModuleInfo
*
MMI
,
unsigned
Encoding
,
MCStreamer
&
Streamer
)
const
{
assert
(
Encoding
==
DW_EH_PE_absptr
&&
"Can handle absptr encoding only"
)
;
Triple
T
(
MMI
->
getModule
(
)
->
getTargetTriple
(
)
)
;
if
(
T
.
isOSNaCl
(
)
)
return
TargetLoweringObjectFileELF
::
getTTypeGlobalReference
(
GV
,
Mang
,
MMI
,
Encoding
,
Streamer
)
;
return
MCSymbolRefExpr
::
Create
(
getSymbol
(
*
Mang
,
GV
)
,
MCSymbolRefExpr
::
VK_ARM_TARGET2
,
getContext
(
)
)
;
}
</s>

The mach-o version of this method defaults to returning a stub reference .

ARM
ARM
"Can handle absptr encoding only"
ARM


<s> bool mayNeedRelaxation ( const MCInst & , const MCSubtargetInfo & STI ) const override { return false ; } </s>

Check whether the given instruction may need relaxation .


<s> static bool classof ( const MCExpr * E ) { return E -> getKind ( ) == MCExpr :: Target ; } </s>

Methods for support type inquiry through isa , cast , and dyn_cast :


<s> bool ARMSubtarget :: enableAtomicExpand ( ) const { return hasAnyDataBarrier ( ) && ! isThumb1Only ( ) ; } </s>

True if the subtarget should run the atomic expansion pass .


<s> static bool xstormy16_rtx_costs ( rtx x , int code , int outer_code ATTRIBUTE_UNUSED , int * total ) { switch ( code ) { case CONST_INT : if ( INTVAL ( x ) < 16 && INTVAL ( x ) >= 0 ) * total = COSTS_N_INSNS ( 1 ) / 2 ; else if ( INTVAL ( x ) < 256 && INTVAL ( x ) >= 0 ) * total = COSTS_N_INSNS ( 1 ) ; else * total = COSTS_N_INSNS ( 2 ) ; return true ; case CONST_DOUBLE : case CONST : case SYMBOL_REF : case LABEL_REF : * total = COSTS_N_INSNS ( 2 ) ; return true ; case MULT : * total = COSTS_N_INSNS ( 35 + 6 ) ; return true ; case DIV : * total = COSTS_N_INSNS ( 51 - 6 ) ; return true ; default : return false ; } } </s>

Compute a ( partial ) cost for rtx X . Return true if the complete cost has been computed , and false if subexpressions should be scanned . In either case , * TOTAL contains the cost result .


<s> const X86Subtarget * X86TargetMachine :: getSubtargetImpl ( const Function & F ) const { Attribute CPUAttr = F . getFnAttribute ( "target-cpu" ) ; Attribute TuneAttr = F . getFnAttribute ( "tune-cpu" ) ; Attribute FSAttr = F . getFnAttribute ( "target-features" ) ; StringRef CPU = CPUAttr . isValid ( ) ? CPUAttr . getValueAsString ( ) : ( StringRef ) TargetCPU ; StringRef TuneCPU = TuneAttr . isValid ( ) ? TuneAttr . getValueAsString ( ) : ( StringRef ) CPU ; StringRef FS = FSAttr . isValid ( ) ? FSAttr . getValueAsString ( ) : ( StringRef ) TargetFS ; SmallString < 512 > Key ; unsigned PreferVectorWidthOverride = 0 ; Attribute PreferVecWidthAttr = F . getFnAttribute ( "prefer-vector-width" ) ; if ( PreferVecWidthAttr . isValid ( ) ) { StringRef Val = PreferVecWidthAttr . getValueAsString ( ) ; unsigned Width ; if ( ! Val . getAsInteger ( 0 , Width ) ) { Key += 'p' ; Key += Val ; PreferVectorWidthOverride = Width ; } } unsigned RequiredVectorWidth = UINT32_MAX ; Attribute MinLegalVecWidthAttr = F . getFnAttribute ( "min-legal-vector-width" ) ; if ( MinLegalVecWidthAttr . isValid ( ) ) { StringRef Val = MinLegalVecWidthAttr . getValueAsString ( ) ; unsigned Width ; if ( ! Val . getAsInteger ( 0 , Width ) ) { Key += 'm' ; Key += Val ; RequiredVectorWidth = Width ; } } Key += CPU ; Key += TuneCPU ; unsigned FSStart = Key . size ( ) ; bool SoftFloat = F . getFnAttribute ( "use-soft-float" ) . getValueAsBool ( ) ; if ( SoftFloat ) Key += FS . empty ( ) ? "+soft-float" : "+soft-float," ; Key += FS ; FS = Key . substr ( FSStart ) ; auto & I = SubtargetMap [ Key ] ; if ( ! I ) { resetTargetOptions ( F ) ; I = std :: make_unique < X86Subtarget > ( TargetTriple , CPU , TuneCPU , FS , * this , MaybeAlign ( F . getParent ( ) -> getOverrideStackAlignment ( ) ) , PreferVectorWidthOverride , RequiredVectorWidth ) ; } return I . get ( ) ; } </s>

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .


<s>
InstructionCost
X86TTIImpl
::
getScalarizationOverhead
(
VectorType
*
Ty
,
const
APInt
&
DemandedElts
,
bool
Insert
,
bool
Extract
)
{
InstructionCost
Cost
=
0
;
if
(
Insert
)
{
std
::
pair
<
InstructionCost
,
MVT
>
LT
=
TLI
->
getTypeLegalizationCost
(
DL
,
Ty
)
;
MVT
MScalarTy
=
LT
.
second
.
getScalarType
(
)
;
unsigned
SizeInBits
=
LT
.
second
.
getSizeInBits
(
)
;
if
(
(
MScalarTy
==
MVT
::
i16
&&
ST
->
hasSSE2
(
)
)
||
(
MScalarTy
.
isInteger
(
)
&&
ST
->
hasSSE41
(
)
)
||
(
MScalarTy
==
MVT
::
f32
&&
ST
->
hasSSE41
(
)
)
)
{
if
(
SizeInBits
<=
128
)
{
Cost
+=
BaseT
::
getScalarizationOverhead
(
Ty
,
DemandedElts
,
Insert
,
false
)
;
}
else
{
const
int
CostValue
=
*
LT
.
first
.
getValue
(
)
;
assert
(
CostValue
>=
0
&&
"Negative cost!"
)
;
unsigned
Num128Lanes
=
SizeInBits
/
128
*
CostValue
;
unsigned
NumElts
=
LT
.
second
.
getVectorNumElements
(
)
*
CostValue
;
APInt
WidenedDemandedElts
=
DemandedElts
.
zextOrSelf
(
NumElts
)
;
unsigned
Scale
=
NumElts
/
Num128Lanes
;
for
(
unsigned
I
=
0
;
I
<
NumElts
;
I
+=
Scale
)
{
APInt
Mask
=
WidenedDemandedElts
.
getBitsSet
(
NumElts
,
I
,
I
+
Scale
)
;
APInt
MaskedDE
=
Mask
&
WidenedDemandedElts
;
unsigned
Population
=
MaskedDE
.
countPopulation
(
)
;
Cost
+=
(
Population
>
0
&&
Population
!=
Scale
&&
I
%
LT
.
second
.
getVectorNumElements
(
)
!=
0
)
;
Cost
+=
Population
>
0
;
}
Cost
+=
DemandedElts
.
countPopulation
(
)
;
if
(
MScalarTy
==
MVT
::
f32
)
for
(
unsigned
i
=
0
,
e
=
cast
<
FixedVectorType
>
(
Ty
)
->
getNumElements
(
)
;
i
<
e
;
i
+=
4
)
if
(
DemandedElts
[
i
]
)
Cost
;
}
}
else
if
(
LT
.
second
.
isVector
(
)
)
{
if
(
Ty
->
isIntOrIntVectorTy
(
)
)
Cost
+=
DemandedElts
.
countPopulation
(
)
;
unsigned
NumElts
=
LT
.
second
.
getVectorNumElements
(
)
;
unsigned
Pow2Elts
=
PowerOf2Ceil
(
cast
<
FixedVectorType
>
(
Ty
)
->
getNumElements
(
)
)
;
Cost
+=
(
std
::
min
<
unsigned
>
(
NumElts
,
Pow2Elts
)
1
)
*
LT
.
first
;
}
}
if
(
Extract
)
Cost
+=
BaseT
::
getScalarizationOverhead
(
Ty
,
DemandedElts
,
false
,
Extract
)
;
return
Cost
;
}
</s>

Estimate the overhead of scalarizing an instruction .


<s> bool MSP430InstrInfo :: isUnpredicatedTerminator ( const MachineInstr & MI ) const { if ( ! MI . isTerminator ( ) ) return false ; if ( MI . isBranch ( ) && ! MI . isBarrier ( ) ) return true ; if ( ! MI . isPredicable ( ) ) return true ; return ! isPredicated ( MI ) ; } </s>

Returns true if the instruction is a terminator instruction that has not been predicated .


<s> static rtx ix86_expand_sse_compare ( const struct builtin_description * d , tree arglist , rtx target ) { rtx pat ; tree arg0 = TREE_VALUE ( arglist ) ; tree arg1 = TREE_VALUE ( TREE_CHAIN ( arglist ) ) ; rtx op0 = expand_expr ( arg0 , NULL_RTX , VOIDmode , 0 ) ; rtx op1 = expand_expr ( arg1 , NULL_RTX , VOIDmode , 0 ) ; rtx op2 ; enum machine_mode tmode = insn_data [ d -> icode ] . operand [ 0 ] . mode ; enum machine_mode mode0 = insn_data [ d -> icode ] . operand [ 1 ] . mode ; enum machine_mode mode1 = insn_data [ d -> icode ] . operand [ 2 ] . mode ; enum rtx_code comparison = d -> comparison ; if ( VECTOR_MODE_P ( mode0 ) ) op0 = safe_vector_operand ( op0 , mode0 ) ; if ( VECTOR_MODE_P ( mode1 ) ) op1 = safe_vector_operand ( op1 , mode1 ) ; if ( d -> flag & BUILTIN_DESC_SWAP_OPERANDS ) { rtx tmp = gen_reg_rtx ( mode1 ) ; emit_move_insn ( tmp , op1 ) ; op1 = op0 ; op0 = tmp ; } if ( optimize || ! target || GET_MODE ( target ) != tmode || ! ( * insn_data [ d -> icode ] . operand [ 0 ] . predicate ) ( target , tmode ) ) target = gen_reg_rtx ( tmode ) ; if ( ( optimize && ! register_operand ( op0 , mode0 ) ) || ! ( * insn_data [ d -> icode ] . operand [ 1 ] . predicate ) ( op0 , mode0 ) ) op0 = copy_to_mode_reg ( mode0 , op0 ) ; if ( ( optimize && ! register_operand ( op1 , mode1 ) ) || ! ( * insn_data [ d -> icode ] . operand [ 2 ] . predicate ) ( op1 , mode1 ) ) op1 = copy_to_mode_reg ( mode1 , op1 ) ; op2 = gen_rtx_fmt_ee ( comparison , mode0 , op0 , op1 ) ; pat = GEN_FCN ( d -> icode ) ( target , op0 , op1 , op2 ) ; if ( ! pat ) return 0 ; emit_insn ( pat ) ; return target ; } </s>

Subroutine of ix86_expand_builtin to take care of comparison insns .


<s>
rtx
m32c_function_arg
(
CUMULATIVE_ARGS
*
ca
,
enum
machine_mode
mode
,
tree
type
,
int
named
)
{
rtx
rv
=
NULL_RTX
;
fprintf
(
stderr
,
"func_arg %d (%s, %d)\n"
,
ca
->
parm_num
,
mode_name
[
mode
]
,
named
)
;
debug_tree
(
type
)
;
if
(
mode
==
VOIDmode
)
return
GEN_INT
(
0
)
;
if
(
ca
->
force_mem
||
!
named
)
{
fprintf
(
stderr
,
"func arg: force %d named %d, mem\n"
,
ca
->
force_mem
,
named
)
;
return
NULL_RTX
;
}
if
(
type
&&
INTEGRAL_TYPE_P
(
type
)
&&
POINTER_TYPE_P
(
type
)
)
return
NULL_RTX
;
switch
(
ca
->
parm_num
)
{
case
1
:
if
(
GET_MODE_SIZE
(
mode
)
==
1
||
GET_MODE_SIZE
(
mode
)
==
2
)
rv
=
gen_rtx_REG
(
mode
,
TARGET_A16
R1_REGNO
:
R0_REGNO
)
;
break
;
case
2
:
if
(
TARGET_A16
&&
GET_MODE_SIZE
(
mode
)
==
2
)
rv
=
gen_rtx_REG
(
mode
,
R2_REGNO
)
;
break
;
}
debug_rtx
(
rv
)
;
return
rv
;
}
</s>

Implements FUNCTION_ARG . Arguments are passed partly in registers , partly on stack . If our function returns a struct , a pointer to a buffer for it is at the top of the stack ( last thing pushed ) . The first few real arguments may be in registers as follows : R8C/M16C : arg1 in r1 if it 's QI or HI ( else it 's pushed on stack ) arg2 in r2 if it 's HI ( else pushed on stack ) rest on stack M32C : arg1 in r0 if it 's QI or HI ( else it 's pushed on stack ) rest on stack Structs are not passed in registers , even if they fit . Only integer and pointer types are passed in registers . Note that when arg1 does n't fit in r1 , arg2 may still be passed in r2 if it fits .


<s> static int sparc_arg_partial_bytes ( cumulative_args_t cum , machine_mode mode , tree type , bool named ) { int slotno , regno , padding ; slotno = function_arg_slotno ( get_cumulative_args ( cum ) , mode , type , named , false , & regno , & padding ) ; if ( slotno == - 1 ) return 0 ; if ( TARGET_ARCH32 ) { if ( ( slotno + ( mode == BLKmode ? ROUND_ADVANCE ( int_size_in_bytes ( type ) ) : ROUND_ADVANCE ( GET_MODE_SIZE ( mode ) ) ) ) > SPARC_INT_ARG_MAX ) return ( SPARC_INT_ARG_MAX - slotno ) * UNITS_PER_WORD ; } else { if ( type && AGGREGATE_TYPE_P ( type ) ) { int size = int_size_in_bytes ( type ) ; if ( size > UNITS_PER_WORD && slotno == SPARC_INT_ARG_MAX - 1 ) return UNITS_PER_WORD ; } else if ( GET_MODE_CLASS ( mode ) == MODE_COMPLEX_INT || ( GET_MODE_CLASS ( mode ) == MODE_COMPLEX_FLOAT && ! ( TARGET_FPU && named ) ) ) { if ( GET_MODE_SIZE ( mode ) > UNITS_PER_WORD && slotno == SPARC_INT_ARG_MAX - 1 ) return UNITS_PER_WORD ; } else if ( GET_MODE_CLASS ( mode ) == MODE_COMPLEX_FLOAT ) { if ( ( slotno + GET_MODE_SIZE ( mode ) / UNITS_PER_WORD ) > SPARC_FP_ARG_MAX ) return UNITS_PER_WORD ; } } return 0 ; } </s>

For an arg passed partly in registers and partly in memory , this is the number of bytes of registers used . For args passed entirely in registers or entirely in memory , zero . Any arg that starts in the first 6 regs but wo n't entirely fit in them needs partial registers on v8 . On v9 , structures with integer values in arg slots 5,6 will be passed in % o5 and SP+176 , and complex fp values that begin in the last fp reg [ where `` last fp reg '' varies with the mode ] will be split between that reg and memory .


<s> static void aarch64_emit_epilogue_components ( sbitmap components ) { aarch64_process_components ( components , false ) ; } </s>


<s> void SNESTargetLowering :: ReplaceNodeResults ( SDNode * N , SmallVectorImpl < SDValue > & Results , SelectionDAG & DAG ) const { SDLoc DL ( N ) ; switch ( N -> getOpcode ( ) ) { case ISD :: ADD : { if ( const ConstantSDNode * C = dyn_cast < ConstantSDNode > ( N -> getOperand ( 1 ) ) ) { SDValue Sub = DAG . getNode ( ISD :: SUB , DL , N -> getValueType ( 0 ) , N -> getOperand ( 0 ) , DAG . getConstant ( - C -> getAPIntValue ( ) , DL , C -> getValueType ( 0 ) ) ) ; Results . push_back ( Sub ) ; } break ; } default : { SDValue Res = LowerOperation ( SDValue ( N , 0 ) , DAG ) ; for ( unsigned I = 0 , E = Res -> getNumValues ( ) ; I != E ; ++ I ) Results . push_back ( Res . getValue ( I ) ) ; break ; } } } </s>

ReplaceNodeResults - Replace the results of node with an illegal result type with new values built out of custom code .


<s> bool AArch64AsmBackend :: writeNopData ( uint64_t Count , MCObjectWriter * OW ) const { OW -> WriteZeros ( Count % 4 ) ; Count /= 4 ; for ( uint64_t i = 0 ; i != Count ; ++ i ) OW -> Write32 ( 0xd503201f ) ; return true ; } </s>

Write an ( optimal ) nop sequence of Count bytes to the given output .


<s> unsigned XCoreRegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { const XCoreFrameLowering * TFI = getFrameLowering ( MF ) ; return TFI -> hasFP ( MF ) ? XCore :: R10 : XCore :: SP ; } </s>


<s> bool HexagonTargetLowering :: allowsMisalignedMemoryAccesses ( EVT VT , unsigned AS , unsigned Align , bool * Fast ) const { if ( Fast ) * Fast = false ; switch ( VT . getSimpleVT ( ) . SimpleTy ) { default : return false ; case MVT :: v64i8 : case MVT :: v128i8 : case MVT :: v256i8 : case MVT :: v32i16 : case MVT :: v64i16 : case MVT :: v128i16 : case MVT :: v16i32 : case MVT :: v32i32 : case MVT :: v64i32 : return true ; } return false ; } </s>

Returns true if the target allows unaligned memory accesses of the specified type .


<s> std :: unique_ptr < MCObjectWriter > createObjectWriter ( raw_pwrite_stream & OS ) const override { return createARMWinCOFFObjectWriter ( OS , false ) ; } </s>

Create a new MCObjectWriter instance for use by the assembler backend to emit the final object file .


<s> static reg_class_t arc_secondary_reload ( bool in_p , rtx x , reg_class_t cl , machine_mode mode , secondary_reload_info * sri ) { enum rtx_code code = GET_CODE ( x ) ; if ( cl == DOUBLE_REGS ) return GENERAL_REGS ; if ( ( cl == LPCOUNT_REG || cl == WRITABLE_CORE_REGS ) && in_p && MEM_P ( x ) ) return GENERAL_REGS ; if ( code == SUBREG ) { rtx addr = NULL_RTX ; x = SUBREG_REG ( x ) ; if ( REG_P ( x ) ) { int regno = REGNO ( x ) ; if ( regno >= FIRST_PSEUDO_REGISTER ) regno = reg_renumber [ regno ] ; if ( regno != - 1 ) return NO_REGS ; if ( reg_equiv_mem ( REGNO ( x ) ) ) { rtx mem = reg_equiv_mem ( REGNO ( x ) ) ; addr = find_replacement ( & XEXP ( mem , 0 ) ) ; } } else { gcc_assert ( MEM_P ( x ) ) ; addr = XEXP ( x , 0 ) ; addr = simplify_rtx ( addr ) ; } if ( addr && GET_CODE ( addr ) == PLUS && CONST_INT_P ( XEXP ( addr , 1 ) ) && ( ! RTX_OK_FOR_OFFSET_P ( mode , XEXP ( addr , 1 ) ) ) ) { switch ( mode ) { case E_QImode : sri -> icode = in_p ? CODE_FOR_reload_qi_load : CODE_FOR_reload_qi_store ; break ; case E_HImode : sri -> icode = in_p ? CODE_FOR_reload_hi_load : CODE_FOR_reload_hi_store ; break ; default : break ; } } } return NO_REGS ; } </s>

For ARC base register + offset addressing , the validity of the address is mode-dependent for most of the offset range , as the offset can be scaled by the access size . We do n't expose these as mode-dependent addresses in the mode_dependent_address_p target hook , because that would disable lots of optimizations , and most uses of these addresses are for 32 or 64 bit accesses anyways , which are fine . However , that leaves some addresses for 8 / 16 bit values not properly reloaded by the generic code , which is why we have to schedule secondary reloads for these .


<s> int pic_address_needs_scratch ( rtx x ) { if ( GET_CODE ( x ) == CONST && GET_CODE ( XEXP ( x , 0 ) ) == PLUS && GET_CODE ( XEXP ( XEXP ( x , 0 ) , 0 ) ) == SYMBOL_REF && GET_CODE ( XEXP ( XEXP ( x , 0 ) , 1 ) ) == CONST_INT && ! SMALL_INT ( XEXP ( XEXP ( x , 0 ) , 1 ) ) ) return 1 ; return 0 ; } </s>

Return true if X is an address which needs a temporary register when reloaded while generating PIC code .


<s> static rtx rs6000_parallel_return ( machine_mode mode , int n_elts , machine_mode elt_mode , unsigned int regno , unsigned int reg_stride ) { rtx par = gen_rtx_PARALLEL ( mode , rtvec_alloc ( n_elts ) ) ; int i ; for ( i = 0 ; i < n_elts ; i ++ ) { rtx r = gen_rtx_REG ( elt_mode , regno ) ; rtx off = GEN_INT ( i * GET_MODE_SIZE ( elt_mode ) ) ; XVECEXP ( par , 0 , i ) = gen_rtx_EXPR_LIST ( VOIDmode , r , off ) ; regno += reg_stride ; } return par ; } </s>

Return an rtx describing a return value of MODE as a PARALLEL in N_ELTS registers , each of mode ELT_MODE , starting at REGNO , stride REG_STRIDE .


<s> int registers_ok_for_quad_peep ( rtx reg1 , rtx reg2 ) { if ( GET_CODE ( reg1 ) != REG || GET_CODE ( reg2 ) != REG ) return 0 ; if ( ! FP_REGNO_P ( REGNO ( reg1 ) ) || ! FP_REGNO_P ( REGNO ( reg2 ) ) ) return 0 ; return ( REGNO ( reg1 ) == REGNO ( reg2 ) - 1 ) ; } </s>

Return 1 if REGNO ( reg1 ) == REGNO ( reg2 ) - 1 making them candidates for lfq and stfq insns . Note reg1 and reg2 * must * be hard registers . To be sure we will abort if we are passed pseudo registers .


<s>
SDValue
CJGTargetLowering
::
LowerReturn
(
SDValue
Chain
,
CallingConv
::
ID
CallConv
,
bool
IsVarArg
,
const
SmallVectorImpl
<
ISD
::
OutputArg
>
&
Outs
,
const
SmallVectorImpl
<
SDValue
>
&
OutVals
,
const
SDLoc
&
DL
,
SelectionDAG
&
DAG
)
const
{
if
(
IsVarArg
)
{
report_fatal_error
(
"VarArg not supported"
)
;
}
SmallVector
<
CCValAssign
,
16
>
RVLocs
;
CCState
CCInfo
(
CallConv
,
IsVarArg
,
DAG
.
getMachineFunction
(
)
,
RVLocs
,
*
DAG
.
getContext
(
)
)
;
CCInfo
.
AnalyzeReturn
(
Outs
,
RetCC_CJG
)
;
SDValue
Flag
;
SmallVector
<
SDValue
,
4
>
RetOps
(
1
,
Chain
)
;
for
(
unsigned
i
=
0
,
e
=
RVLocs
.
size
(
)
;
i
<
e
;
++
i
)
{
CCValAssign
&
VA
=
RVLocs
[
i
]
;
assert
(
VA
.
isRegLoc
(
)
&&
"Can only return in registers!"
)
;
Chain
=
DAG
.
getCopyToReg
(
Chain
,
DL
,
VA
.
getLocReg
(
)
,
OutVals
[
i
]
,
Flag
)
;
Flag
=
Chain
.
getValue
(
1
)
;
RetOps
.
push_back
(
DAG
.
getRegister
(
VA
.
getLocReg
(
)
,
VA
.
getLocVT
(
)
)
)
;
}
RetOps
[
0
]
=
Chain
;
if
(
Flag
.
getNode
(
)
)
{
RetOps
.
push_back
(
Flag
)
;
}
return
DAG
.
getNode
(
CJGISD
::
RET_FLAG
,
DL
,
MVT
::
Other
,
RetOps
)
;
}
</s>

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .


<s> void ix86_expand_copysign ( rtx operands [ ] ) { machine_mode mode , vmode ; rtx dest , op0 , op1 , mask , nmask ; dest = operands [ 0 ] ; op0 = operands [ 1 ] ; op1 = operands [ 2 ] ; mode = GET_MODE ( dest ) ; if ( mode == SFmode ) vmode = V4SFmode ; else if ( mode == DFmode ) vmode = V2DFmode ; else vmode = mode ; if ( CONST_DOUBLE_P ( op0 ) ) { rtx ( * copysign_insn ) ( rtx , rtx , rtx , rtx ) ; if ( real_isneg ( CONST_DOUBLE_REAL_VALUE ( op0 ) ) ) op0 = simplify_unary_operation ( ABS , mode , op0 , mode ) ; if ( mode == SFmode || mode == DFmode ) { if ( op0 == CONST0_RTX ( mode ) ) op0 = CONST0_RTX ( vmode ) ; else { rtx v = ix86_build_const_vector ( vmode , false , op0 ) ; op0 = force_reg ( vmode , v ) ; } } else if ( op0 != CONST0_RTX ( mode ) ) op0 = force_reg ( mode , op0 ) ; mask = ix86_build_signbit_mask ( vmode , 0 , 0 ) ; if ( mode == SFmode ) copysign_insn = gen_copysignsf3_const ; else if ( mode == DFmode ) copysign_insn = gen_copysigndf3_const ; else copysign_insn = gen_copysigntf3_const ; emit_insn ( copysign_insn ( dest , op0 , op1 , mask ) ) ; } else { rtx ( * copysign_insn ) ( rtx , rtx , rtx , rtx , rtx , rtx ) ; nmask = ix86_build_signbit_mask ( vmode , 0 , 1 ) ; mask = ix86_build_signbit_mask ( vmode , 0 , 0 ) ; if ( mode == SFmode ) copysign_insn = gen_copysignsf3_var ; else if ( mode == DFmode ) copysign_insn = gen_copysigndf3_var ; else copysign_insn = gen_copysigntf3_var ; emit_insn ( copysign_insn ( dest , NULL_RTX , op0 , op1 , nmask , mask ) ) ; } } </s>

Expand a copysign operation . Special case operand 0 being a constant .


<s> static bool gen_one_bundle ( rtx_insn * slot [ 3 ] ) { gcc_assert ( slot [ 1 ] != NULL_RTX ) ; if ( optimize_size && ( slot [ 0 ] == NULL_RTX || slot [ 2 ] == NULL_RTX ) ) return false ; if ( slot [ 0 ] ) { rtx_insn * t = NEXT_INSN ( slot [ 0 ] ) ; while ( t != slot [ 1 ] ) { if ( ! NOTE_P ( t ) || NOTE_KIND ( t ) != NOTE_INSN_DELETED ) return false ; t = NEXT_INSN ( t ) ; } } if ( slot [ 2 ] ) { rtx_insn * t = NEXT_INSN ( slot [ 1 ] ) ; while ( t != slot [ 2 ] ) { if ( ! NOTE_P ( t ) || NOTE_KIND ( t ) != NOTE_INSN_DELETED ) return false ; t = NEXT_INSN ( t ) ; } } if ( slot [ 0 ] == NULL_RTX ) { slot [ 0 ] = emit_insn_before ( gen_mnop ( ) , slot [ 1 ] ) ; df_insn_rescan ( slot [ 0 ] ) ; } if ( slot [ 2 ] == NULL_RTX ) { slot [ 2 ] = emit_insn_after ( gen_forced_nop ( ) , slot [ 1 ] ) ; df_insn_rescan ( slot [ 2 ] ) ; } if ( INSN_LOCATION ( slot [ 1 ] ) && INSN_LOCATION ( slot [ 1 ] ) != INSN_LOCATION ( slot [ 0 ] ) ) INSN_LOCATION ( slot [ 1 ] ) = INSN_LOCATION ( slot [ 0 ] ) ; if ( INSN_LOCATION ( slot [ 2 ] ) && INSN_LOCATION ( slot [ 2 ] ) != INSN_LOCATION ( slot [ 0 ] ) ) INSN_LOCATION ( slot [ 2 ] ) = INSN_LOCATION ( slot [ 0 ] ) ; PUT_MODE ( slot [ 0 ] , SImode ) ; PUT_MODE ( slot [ 1 ] , SImode ) ; PUT_MODE ( slot [ 2 ] , QImode ) ; return true ; } </s>

Create a SEQUENCE rtx to replace the instructions in SLOT , of which there are N_FILLED . REAL_FIRST identifies the slot if the insn that appears first in the original stream .


<s> void emitConstantPool ( ) override { } </s>

Print to the current output stream assembly representations of the constants in the constant pool MCP .


<s> int s390_single_part ( rtx op , machine_mode mode , machine_mode part_mode , int def ) { unsigned HOST_WIDE_INT value = 0 ; int n_parts = GET_MODE_SIZE ( mode ) / GET_MODE_SIZE ( part_mode ) ; unsigned HOST_WIDE_INT part_mask = ( ( unsigned HOST_WIDE_INT ) 1 << GET_MODE_BITSIZE ( part_mode ) ) - 1 ; int i , part = - 1 ; if ( GET_CODE ( op ) != CONST_INT ) return - 1 ; for ( i = 0 ; i < n_parts ; i ++ ) { if ( i == 0 ) value = ( unsigned HOST_WIDE_INT ) INTVAL ( op ) ; else value >>= GET_MODE_BITSIZE ( part_mode ) ; if ( ( value & part_mask ) != ( def & part_mask ) ) { if ( part != - 1 ) return - 1 ; else part = i ; } } return part == - 1 ? - 1 : n_parts - 1 - part ; } </s>

If OP is an integer constant of mode MODE with exactly one part of mode PART_MODE unequal to DEF , return the number of that part . Otherwise , return -1 .


<s>
bool
HexagonPacketizer
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
auto
&
HST
=
MF
.
getSubtarget
<
HexagonSubtarget
>
(
)
;
HII
=
HST
.
getInstrInfo
(
)
;
HRI
=
HST
.
getRegisterInfo
(
)
;
auto
&
MLI
=
getAnalysis
<
MachineLoopInfo
>
(
)
;
auto
*
AA
=
&
getAnalysis
<
AAResultsWrapperPass
>
(
)
.
getAAResults
(
)
;
auto
*
MBPI
=
&
getAnalysis
<
MachineBranchProbabilityInfo
>
(
)
;
if
(
EnableGenAllInsnClass
)
HII
->
genAllInsnTimingClasses
(
MF
)
;
bool
MinOnly
=
Minimal
||
DisablePacketizer
||
!
HST
.
usePackets
(
)
||
skipFunction
(
MF
.
getFunction
(
)
)
;
HexagonPacketizerList
Packetizer
(
MF
,
MLI
,
AA
,
MBPI
,
MinOnly
)
;
assert
(
Packetizer
.
getResourceTracker
(
)
&&
"Empty DFA table!"
)
;
for
(
MachineBasicBlock
&
MB
:
MF
)
{
auto
End
=
MB
.
end
(
)
;
auto
MI
=
MB
.
begin
(
)
;
while
(
MI
!=
End
)
{
auto
NextI
=
std
::
next
(
MI
)
;
if
(
MI
->
isKill
(
)
)
{
MB
.
erase
(
MI
)
;
End
=
MB
.
end
(
)
;
}
MI
=
NextI
;
}
}
if
(
HST
.
isTinyCoreWithDuplex
(
)
)
HII
->
translateInstrsForDup
(
MF
,
true
)
;
for
(
auto
&
MB
:
MF
)
{
auto
Begin
=
MB
.
begin
(
)
,
End
=
MB
.
end
(
)
;
while
(
Begin
!=
End
)
{
MachineBasicBlock
::
iterator
RB
=
Begin
;
while
(
RB
!=
End
&&
HII
->
isSchedulingBoundary
(
*
RB
,
&
MB
,
MF
)
)
++
RB
;
MachineBasicBlock
::
iterator
RE
=
RB
;
while
(
RE
!=
End
&&
!
HII
->
isSchedulingBoundary
(
*
RE
,
&
MB
,
MF
)
)
++
RE
;
if
(
RE
!=
End
)
++
RE
;
if
(
RB
!=
End
)
Packetizer
.
PacketizeMIs
(
&
MB
,
RB
,
RE
)
;
Begin
=
RE
;
}
}
if
(
HST
.
isTinyCoreWithDuplex
(
)
)
HII
->
translateInstrsForDup
(
MF
,
false
)
;
Packetizer
.
unpacketizeSoloInstrs
(
MF
)
;
return
true
;
}
</s>

runOnMachineFunction - Emit the function body .

Hexagon
Hexagon
Hexagon
Hexagon
"Empty DFA table!"


<s> static bool rs6000_secondary_reload_simple_move ( enum rs6000_reg_type to_type , enum rs6000_reg_type from_type , machine_mode mode ) { int size ; size = GET_MODE_SIZE ( mode ) ; if ( TARGET_DIRECT_MOVE && ( ( mode == SDmode ) || ( TARGET_POWERPC64 && size == 8 ) ) && ( ( to_type == GPR_REG_TYPE && from_type == VSX_REG_TYPE ) || ( to_type == VSX_REG_TYPE && from_type == GPR_REG_TYPE ) ) ) return true ; else if ( TARGET_DIRECT_MOVE_128 && size == 16 && ( ( to_type == VSX_REG_TYPE && from_type == GPR_REG_TYPE ) || ( to_type == GPR_REG_TYPE && from_type == VSX_REG_TYPE ) ) ) return true ; else if ( TARGET_MFPGPR && TARGET_POWERPC64 && size == 8 && ( ( to_type == GPR_REG_TYPE && from_type == FPR_REG_TYPE ) || ( to_type == FPR_REG_TYPE && from_type == GPR_REG_TYPE ) ) ) return true ; else if ( ( size == 4 || ( TARGET_POWERPC64 && size == 8 ) ) && ( ( to_type == GPR_REG_TYPE && from_type == SPR_REG_TYPE ) || ( to_type == SPR_REG_TYPE && from_type == GPR_REG_TYPE ) ) ) return true ; return false ; } </s>

Helper function for rs6000_secondary_reload to return true if a move to a different register classe is really a simple move .


<s> static void m32r_setup_incoming_varargs ( cumulative_args_t cum , machine_mode mode , tree type , int * pretend_size , int no_rtl ) { int first_anon_arg ; if ( no_rtl ) return ; gcc_assert ( mode != BLKmode ) ; first_anon_arg = ( ROUND_ADVANCE_CUM ( * get_cumulative_args ( cum ) , mode , type ) + ROUND_ADVANCE_ARG ( mode , type ) ) ; if ( first_anon_arg < M32R_MAX_PARM_REGS ) { int first_reg_offset = first_anon_arg ; int size = M32R_MAX_PARM_REGS - first_reg_offset ; rtx regblock ; regblock = gen_frame_mem ( BLKmode , plus_constant ( Pmode , arg_pointer_rtx , FIRST_PARM_OFFSET ( 0 ) ) ) ; set_mem_alias_set ( regblock , get_varargs_alias_set ( ) ) ; move_block_from_reg ( first_reg_offset , regblock , size ) ; * pretend_size = ( size * UNITS_PER_WORD ) ; } } </s>

Do any needed setup for a variadic function . For the M32R , we must create a register parameter block , and then copy any anonymous arguments in registers to memory . CUM has not been updated for the last named argument which has type TYPE and mode MODE , and we rely on this fact .


<s> bool MipsCCState :: isF128SoftLibCall ( const char * CallSym ) { const char * const LibCalls [ ] = { "__addtf3" , "__divtf3" , "__eqtf2" , "__extenddftf2" , "__extendsftf2" , "__fixtfdi" , "__fixtfsi" , "__fixtfti" , "__fixunstfdi" , "__fixunstfsi" , "__fixunstfti" , "__floatditf" , "__floatsitf" , "__floattitf" , "__floatunditf" , "__floatunsitf" , "__floatuntitf" , "__getf2" , "__gttf2" , "__letf2" , "__lttf2" , "__multf3" , "__netf2" , "__powitf2" , "__subtf3" , "__trunctfdf2" , "__trunctfsf2" , "__unordtf2" , "ceill" , "copysignl" , "cosl" , "exp2l" , "expl" , "floorl" , "fmal" , "fmaxl" , "fmodl" , "log10l" , "log2l" , "logl" , "nearbyintl" , "powl" , "rintl" , "roundl" , "sinl" , "sqrtl" , "truncl" } ; auto Comp = [ ] ( const char * S1 , const char * S2 ) { return strcmp ( S1 , S2 ) < 0 ; } ; assert ( llvm :: is_sorted ( LibCalls , Comp ) ) ; return std :: binary_search ( std :: begin ( LibCalls ) , std :: end ( LibCalls ) , CallSym , Comp ) ; } </s>

This function returns true if CallSym is a long double emulation routine .


<s> static rtx frame_move ( rtx dst , rtx src ) { return frame_insn ( gen_rtx_SET ( VOIDmode , dst , src ) ) ; } </s>


<s> bool enableShrinkWrapping ( const MachineFunction & MF ) const override { return false ; } </s>

Returns true if the target will correctly handle shrink wrapping .


"Unexpected fixup kind in fixupNeedsRelaxation()!"

Simple predicate for targets where ! Resolved implies requiring relaxation .


<s> bool TL45TargetLowering :: canMergeStoresTo ( unsigned AS , EVT MemVT , const SelectionDAG & DAG ) const { return true ; } </s>

Returns if it 's reasonable to merge stores to MemVT size .


<s> static bool nios2_small_section_name_p ( const char * section ) { return ( strcmp ( section , ".sbss" ) == 0 || strncmp ( section , ".sbss." , 6 ) == 0 || strcmp ( section , ".sdata" ) == 0 || strncmp ( section , ".sdata." , 7 ) == 0 ) ; } </s>

Return true if SECTION is a small section name .


<s> static rtx ix86_ssecom_setcc ( const enum rtx_code comparison , bool check_unordered , machine_mode mode , rtx set_dst , rtx target ) { rtx_code_label * label = NULL ; if ( check_unordered ) { gcc_assert ( comparison == EQ || comparison == NE ) ; rtx flag = gen_rtx_REG ( CCFPmode , FLAGS_REG ) ; label = gen_label_rtx ( ) ; rtx tmp = gen_rtx_fmt_ee ( UNORDERED , VOIDmode , flag , const0_rtx ) ; tmp = gen_rtx_IF_THEN_ELSE ( VOIDmode , tmp , gen_rtx_LABEL_REF ( VOIDmode , label ) , pc_rtx ) ; emit_jump_insn ( gen_rtx_SET ( pc_rtx , tmp ) ) ; } if ( GET_MODE ( set_dst ) != mode ) { gcc_assert ( mode == CCAmode || mode == CCCmode || mode == CCOmode || mode == CCPmode || mode == CCSmode || mode == CCZmode ) ; set_dst = gen_rtx_REG ( mode , FLAGS_REG ) ; } emit_insn ( gen_rtx_SET ( gen_rtx_STRICT_LOW_PART ( VOIDmode , target ) , gen_rtx_fmt_ee ( comparison , QImode , set_dst , const0_rtx ) ) ) ; if ( label ) emit_label ( label ) ; return SUBREG_REG ( target ) ; } </s>

Subroutine of ix86_sse_comi and ix86_sse_comi_round to take care of * ordered EQ or unordered NE , generate PF jump .


<s> bool SPIRVInstrInfo :: expandPostRAPseudo ( MachineInstr & MI ) const { if ( MI . getOpcode ( ) == SPIRV :: GET_ID || MI . getOpcode ( ) == SPIRV :: GET_fID || MI . getOpcode ( ) == SPIRV :: GET_pID || MI . getOpcode ( ) == SPIRV :: GET_vfID || MI . getOpcode ( ) == SPIRV :: GET_vID ) { auto & MRI = MI . getMF ( ) -> getRegInfo ( ) ; MRI . replaceRegWith ( MI . getOperand ( 0 ) . getReg ( ) , MI . getOperand ( 1 ) . getReg ( ) ) ; MI . eraseFromParent ( ) ; return true ; } return false ; } </s>

This function is called for all pseudo instructions that remain after register allocation .


<s> static void record_cc_ref ( rtx insn ) { last_insn_set_cc_p = current_insn_set_cc_p ; switch ( get_attr_cond ( insn ) ) { case COND_SET : case COND_SET_ZN : case COND_SET_ZNC : if ( get_attr_length ( insn ) == 1 ) current_insn_set_cc_p = 1 ; else current_insn_set_cc_p = 0 ; break ; default : current_insn_set_cc_p = 0 ; break ; } } </s>

Update compare/branch separation marker .


<s> const SortRegion * SortRegionInfo :: getRegionFor ( const MachineBasicBlock * MBB ) { const auto * ML = MLI . getLoopFor ( MBB ) ; const auto * WE = WEI . getExceptionFor ( MBB ) ; if ( ! ML && ! WE ) return nullptr ; if ( ( ML && ! WE ) || ( ML && WE && WE -> contains ( ML -> getHeader ( ) ) ) ) { if ( LoopMap . count ( ML ) ) return LoopMap [ ML ] . get ( ) ; LoopMap [ ML ] = std :: make_unique < ConcreteSortRegion < MachineLoop >> ( ML ) ; return LoopMap [ ML ] . get ( ) ; } else { if ( ExceptionMap . count ( WE ) ) return ExceptionMap [ WE ] . get ( ) ; ExceptionMap [ WE ] = std :: make_unique < ConcreteSortRegion < WebAssemblyException >> ( WE ) ; return ExceptionMap [ WE ] . get ( ) ; } } </s>

Get the smallest region that contains a BasicBlock .


<s> rtx aarch64_expand_rng_builtin ( tree exp , rtx target , int fcode , int ignore ) { rtx pat ; enum insn_code icode ; if ( fcode == AARCH64_BUILTIN_RNG_RNDR ) icode = CODE_FOR_aarch64_rndr ; else if ( fcode == AARCH64_BUILTIN_RNG_RNDRRS ) icode = CODE_FOR_aarch64_rndrrs ; else gcc_unreachable ( ) ; rtx rand = gen_reg_rtx ( DImode ) ; pat = GEN_FCN ( icode ) ( rand ) ; if ( ! pat ) return NULL_RTX ; tree arg0 = CALL_EXPR_ARG ( exp , 0 ) ; rtx res_addr = expand_normal ( arg0 ) ; res_addr = convert_memory_address ( Pmode , res_addr ) ; rtx res_mem = gen_rtx_MEM ( DImode , res_addr ) ; emit_insn ( pat ) ; emit_move_insn ( res_mem , rand ) ; if ( ignore ) return target ; rtx cc_reg = gen_rtx_REG ( CC_Zmode , CC_REGNUM ) ; rtx cmp_rtx = gen_rtx_fmt_ee ( EQ , SImode , cc_reg , const0_rtx ) ; emit_insn ( gen_aarch64_cstoresi ( target , cmp_rtx , cc_reg ) ) ; return target ; } </s>

Expand a random number builtin EXP with code FCODE , putting the result int TARGET . If IGNORE is true the return value is ignored .


<s> bool isImm ( ) const override { return Kind == k_Immediate ; } </s>


<s> uint64_t PPCFrameLowering :: getFramePointerSaveOffset ( ) const { return FramePointerSaveOffset ; } </s>

getFramePointerSaveOffset - Return the previous frame offset to save the frame pointer .


<s> static inline machine_mode get_mode_wider_vector ( machine_mode o ) { machine_mode n = GET_MODE_WIDER_MODE ( o ) ; gcc_assert ( GET_MODE_NUNITS ( o ) == GET_MODE_NUNITS ( n ) * 2 ) ; gcc_assert ( GET_MODE_SIZE ( o ) == GET_MODE_SIZE ( n ) ) ; return n ; } </s>

Get a vector mode of the same size as the original but with elements twice as wide . This is only guaranteed to apply to integral vectors .


<s>
unsigned
MSP430InstrInfo
::
removeBranch
(
MachineBasicBlock
&
MBB
,
int
*
BytesRemoved
)
const
{
assert
(
!
BytesRemoved
&&
"code size not handled"
)
;
MachineBasicBlock
::
iterator
I
=
MBB
.
end
(
)
;
unsigned
Count
=
0
;
while
(
I
!=
MBB
.
begin
(
)
)
{
I
;
if
(
I
->
isDebugValue
(
)
)
continue
;
if
(
I
->
getOpcode
(
)
!=
MSP430
::
JMP
&&
I
->
getOpcode
(
)
!=
MSP430
::
JCC
&&
I
->
getOpcode
(
)
!=
MSP430
::
Br
&&
I
->
getOpcode
(
)
!=
MSP430
::
Bm
)
break
;
I
->
eraseFromParent
(
)
;
I
=
MBB
.
end
(
)
;
++
Count
;
}
return
Count
;
}
</s>

Remove the branching code at the end of the specific MBB .


<s> static char * find_target_compiler ( const char * name ) { bool found = false ; char * * paths = NULL ; unsigned n_paths , i ; char * target_compiler ; const char * collect_gcc = getenv ( "COLLECT_GCC" ) ; const char * gcc_path = dirname ( ASTRDUP ( collect_gcc ) ) ; const char * gcc_exec = basename ( ASTRDUP ( collect_gcc ) ) ; if ( strcmp ( gcc_exec , collect_gcc ) == 0 ) { target_compiler = XDUPVEC ( char , name , strlen ( name ) + 1 ) ; found = true ; goto out ; } target_compiler = concat ( gcc_path , "/" , name , NULL ) ; if ( access_check ( target_compiler , X_OK ) == 0 ) { found = true ; goto out ; } n_paths = parse_env_var ( getenv ( "COMPILER_PATH" ) , & paths ) ; for ( i = 0 ; i < n_paths ; i ++ ) { size_t len = strlen ( paths [ i ] ) + 1 + strlen ( name ) + 1 ; target_compiler = XRESIZEVEC ( char , target_compiler , len ) ; sprintf ( target_compiler , "%s/%s" , paths [ i ] , name ) ; if ( access_check ( target_compiler , X_OK ) == 0 ) { found = true ; break ; } } out : free_array_of_ptrs ( ( void * * ) paths , n_paths ) ; return found ? target_compiler : NULL ; } </s>

Find target compiler using a path from COLLECT_GCC or COMPILER_PATH .


<s> bool wext_odd_dep_p ( rtx insn , rtx def_reg ) { rtx shift_rtx = XEXP ( SET_SRC ( PATTERN ( insn ) ) , 0 ) ; rtx use_reg = XEXP ( shift_rtx , 0 ) ; rtx pos_rtx = XEXP ( shift_rtx , 1 ) ; if ( REG_P ( pos_rtx ) && reg_overlap_p ( def_reg , pos_rtx ) ) return true ; if ( GET_MODE ( def_reg ) == DImode ) return reg_overlap_p ( def_reg , use_reg ) ; gcc_assert ( REG_P ( def_reg ) || GET_CODE ( def_reg ) == SUBREG ) ; gcc_assert ( REG_P ( use_reg ) || GET_CODE ( use_reg ) == SUBREG ) ; if ( REG_P ( def_reg ) ) { if REG_P ( use_reg ) { if ( ! TARGET_BIG_ENDIAN ) return REGNO ( def_reg ) == REGNO ( use_reg ) + 1 ; else return REGNO ( def_reg ) == REGNO ( use_reg ) ; } else return true ; } if ( GET_CODE ( def_reg ) == SUBREG ) { if ( ! reg_overlap_p ( def_reg , use_reg ) ) return false ; if ( GET_CODE ( use_reg ) == SUBREG ) return true ; if ( ! TARGET_BIG_ENDIAN ) return SUBREG_BYTE ( def_reg ) == 4 ; else return SUBREG_BYTE ( def_reg ) == 0 ; } return false ; } </s>

Check if INSN is a wext insn consuming DEF_REG .


<s> bool WebAssemblyFrameLowering :: hasFP ( const MachineFunction & MF ) const { const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const auto * RegInfo = MF . getSubtarget < WebAssemblySubtarget > ( ) . getRegisterInfo ( ) ; return MFI . isFrameAddressTaken ( ) || MFI . hasVarSizedObjects ( ) || MFI . hasStackMap ( ) || MFI . hasPatchPoint ( ) || RegInfo -> needsStackRealignment ( MF ) ; } </s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .


<s> const MCPhysReg * LC2200RegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { return CC_Save_SaveList ; } </s>


<s> virtual void getAnalysisUsage ( AnalysisUsage & AU ) const { AU . addRequired < LiveIntervals > ( ) ; AU . addPreserved < LiveIntervals > ( ) ; AU . addPreserved < SlotIndexes > ( ) ; AU . addPreservedID ( MachineDominatorsID ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> void MCS51TargetObjectFile :: Initialize ( MCContext & Ctx , const TargetMachine & TM ) { Base :: Initialize ( Ctx , TM ) ; ProgmemDataSection = Ctx . getELFSection ( ".progmem.data" , ELF :: SHT_PROGBITS , ELF :: SHF_ALLOC ) ; } </s>

This method must be called before any actual lowering is done .


<s>
unsigned
getReg
(
)
const
override
{
assert
(
(
Kind
==
k_Register
||
Kind
==
k_Memri
)
&&
"Invalid access!"
)
;
return
RegImm
.
Reg
;
}
</s>

Returns the register associated with this edge .


<s> static bool rs6000_lra_p ( void ) { return TARGET_LRA ; } </s>

Return true if we use LRA instead of reload pass .


<s> InstructionCost AArch64TTIImpl :: getIntImmCostInst ( unsigned Opcode , unsigned Idx , const APInt & Imm , Type * Ty , TTI :: TargetCostKind CostKind , Instruction * Inst ) { assert ( Ty -> isIntegerTy ( ) ) ; unsigned BitSize = Ty -> getPrimitiveSizeInBits ( ) ; if ( BitSize == 0 ) return TTI :: TCC_Free ; unsigned ImmIdx = ~ 0U ; switch ( Opcode ) { default : return TTI :: TCC_Free ; case Instruction :: GetElementPtr : if ( Idx == 0 ) return 2 * TTI :: TCC_Basic ; return TTI :: TCC_Free ; case Instruction :: Store : ImmIdx = 0 ; break ; case Instruction :: Add : case Instruction :: Sub : case Instruction :: Mul : case Instruction :: UDiv : case Instruction :: SDiv : case Instruction :: URem : case Instruction :: SRem : case Instruction :: And : case Instruction :: Or : case Instruction :: Xor : case Instruction :: ICmp : ImmIdx = 1 ; break ; case Instruction :: Shl : case Instruction :: LShr : case Instruction :: AShr : if ( Idx == 1 ) return TTI :: TCC_Free ; break ; case Instruction :: Trunc : case Instruction :: ZExt : case Instruction :: SExt : case Instruction :: IntToPtr : case Instruction :: PtrToInt : case Instruction :: BitCast : case Instruction :: PHI : case Instruction :: Call : case Instruction :: Select : case Instruction :: Ret : case Instruction :: Load : break ; } if ( Idx == ImmIdx ) { int NumConstants = ( BitSize + 63 ) / 64 ; InstructionCost Cost = AArch64TTIImpl :: getIntImmCost ( Imm , Ty , CostKind ) ; return ( Cost <= NumConstants * TTI :: TCC_Basic ) ? static_cast < int > ( TTI :: TCC_Free ) : Cost ; } return AArch64TTIImpl :: getIntImmCost ( Imm , Ty , CostKind ) ; } </s>

Return the expected cost of materialization for the given integer immediate of the specified type for a given instruction .


<s> static void rs6000_do_expand_vec_perm ( rtx target , rtx op0 , rtx op1 , machine_mode vmode , const vec_perm_builder & perm ) { rtx x = expand_vec_perm_const ( vmode , op0 , op1 , perm , BLKmode , target ) ; if ( x != target ) emit_move_insn ( target , x ) ; } </s>

A subroutine for rs6000_expand_extract_even & rs6000_expand_interleave .


<s> static bool isF128SoftLibCall ( const char * CallSym ) { const char * const LibCalls [ ] = { "__addtf3" , "__divtf3" , "__eqtf2" , "__extenddftf2" , "__extendsftf2" , "__fixtfdi" , "__fixtfsi" , "__fixtfti" , "__fixunstfdi" , "__fixunstfsi" , "__fixunstfti" , "__floatditf" , "__floatsitf" , "__floattitf" , "__floatunditf" , "__floatunsitf" , "__floatuntitf" , "__getf2" , "__gttf2" , "__letf2" , "__lttf2" , "__multf3" , "__netf2" , "__powitf2" , "__subtf3" , "__trunctfdf2" , "__trunctfsf2" , "__unordtf2" , "ceill" , "copysignl" , "cosl" , "exp2l" , "expl" , "floorl" , "fmal" , "fmodl" , "log10l" , "log2l" , "logl" , "nearbyintl" , "powl" , "rintl" , "sinl" , "sqrtl" , "truncl" } ; auto Comp = [ ] ( const char * S1 , const char * S2 ) { return strcmp ( S1 , S2 ) < 0 ; } ; assert ( std :: is_sorted ( std :: begin ( LibCalls ) , std :: end ( LibCalls ) , Comp ) ) ; return std :: binary_search ( std :: begin ( LibCalls ) , std :: end ( LibCalls ) , CallSym , Comp ) ; } </s>

This function returns true if CallSym is a long double emulation routine .


"After expanding ARM pseudo instructions."

runOnMachineFunction - Emit the function body .


<s> static void arc_ccfsm_at_label ( const char * prefix , int num , struct arc_ccfsm * state ) { if ( state -> state == 3 && state -> target_label == num && ! strcmp ( prefix , "L" ) ) { state -> state = 0 ; state -> target_insn = NULL ; } } </s>

Record that we are currently outputting label NUM with prefix PREFIX . It it 's the label we 're looking for , reset the ccfsm machinery . Called from ( * targetm.asm_out.internal_label ) .


<s>
virtual
const
char
*
getPassName
(
)
const
{
return
"PTX Machine Function Info Extractor"
;
}
</s>

getPassName - Return a nice clean name for a pass .

PTX
"PTX Machine Function Info Extractor"


<s> bool s390_contiguous_bitmask_nowrap_p ( unsigned HOST_WIDE_INT in , int size , int * pstart , int * pend ) { int start ; int end = - 1 ; int lowbit = HOST_BITS_PER_WIDE_INT - 1 ; int highbit = HOST_BITS_PER_WIDE_INT - size ; unsigned HOST_WIDE_INT bitmask = HOST_WIDE_INT_1U ; gcc_assert ( ! ! pstart == ! ! pend ) ; for ( start = lowbit ; start >= highbit ; bitmask <<= 1 , start -- ) if ( end == - 1 ) { if ( bitmask & in ) end = start ; } else { if ( ! ( bitmask & in ) ) break ; } start ++ ; if ( end == - 1 ) return false ; if ( start > highbit ) { unsigned HOST_WIDE_INT mask ; mask = ( ( ~ HOST_WIDE_INT_0U >> highbit ) & ( ~ HOST_WIDE_INT_0U << ( lowbit - start + 1 ) ) ) ; if ( mask & in ) return false ; } if ( pstart ) { * pstart = start ; * pend = end ; } return true ; } </s>

Return true if IN contains a contiguous bitfield in the lower SIZE bits and no other bits are set in ( the lower SIZE bits of ) IN . PSTART and PEND can be used to obtain the start and end position ( inclusive ) of the bitfield relative to 64 bits . * PSTART / * PEND gives the position of the first/last bit of the bitfield counting from the highest order bit starting with zero .


<s>
bool
SparcAsmParser
::
ParseInstruction
(
ParseInstructionInfo
&
Info
,
StringRef
Name
,
SMLoc
NameLoc
,
OperandVector
&
Operands
)
{
Operands
.
push_back
(
SparcOperand
::
CreateToken
(
Name
,
NameLoc
)
)
;
applyMnemonicAliases
(
Name
,
getAvailableFeatures
(
)
,
0
)
;
if
(
getLexer
(
)
.
isNot
(
AsmToken
::
EndOfStatement
)
)
{
if
(
getLexer
(
)
.
is
(
AsmToken
::
Comma
)
)
{
if
(
parseBranchModifiers
(
Operands
)
!=
MatchOperand_Success
)
{
SMLoc
Loc
=
getLexer
(
)
.
getLoc
(
)
;
Parser
.
eatToEndOfStatement
(
)
;
return
Error
(
Loc
,
"unexpected token"
)
;
}
}
if
(
parseOperand
(
Operands
,
Name
)
!=
MatchOperand_Success
)
{
SMLoc
Loc
=
getLexer
(
)
.
getLoc
(
)
;
Parser
.
eatToEndOfStatement
(
)
;
return
Error
(
Loc
,
"unexpected token"
)
;
}
while
(
getLexer
(
)
.
is
(
AsmToken
::
Comma
)
||
getLexer
(
)
.
is
(
AsmToken
::
Plus
)
)
{
if
(
getLexer
(
)
.
is
(
AsmToken
::
Plus
)
)
{
Operands
.
push_back
(
SparcOperand
::
CreateToken
(
"+"
,
Parser
.
getTok
(
)
.
getLoc
(
)
)
)
;
}
Parser
.
Lex
(
)
;
if
(
parseOperand
(
Operands
,
Name
)
!=
MatchOperand_Success
)
{
SMLoc
Loc
=
getLexer
(
)
.
getLoc
(
)
;
Parser
.
eatToEndOfStatement
(
)
;
return
Error
(
Loc
,
"unexpected token"
)
;
}
}
}
if
(
getLexer
(
)
.
isNot
(
AsmToken
::
EndOfStatement
)
)
{
SMLoc
Loc
=
getLexer
(
)
.
getLoc
(
)
;
Parser
.
eatToEndOfStatement
(
)
;
return
Error
(
Loc
,
"unexpected token"
)
;
}
Parser
.
Lex
(
)
;
return
false
;
}
</s>

ParseInstruction - Parse one assembly instruction .

Sparc
Sparc
SparcOperand::CreateToken
0
"unexpected token"
"unexpected token"
SparcOperand::CreateToken
"+"
"unexpected token"
"unexpected token"


<s> EVT AArch64TargetLowering :: getSetCCResultType ( LLVMContext & , EVT VT ) const { if ( ! VT . isVector ( ) ) return MVT :: i32 ; return VT . changeVectorElementTypeToInteger ( ) ; } </s>

Return the value type to use for ISD : :SETCC .


<s>
const
char
*
avr_out_ashrpsi3
(
rtx_insn
*
insn
,
rtx
*
op
,
int
*
plen
)
{
int
dest
=
REGNO
(
op
[
0
]
)
;
int
src
=
REGNO
(
op
[
1
]
)
;
if
(
CONST_INT_P
(
op
[
2
]
)
)
{
if
(
plen
)
*
plen
=
0
;
switch
(
INTVAL
(
op
[
2
]
)
)
{
case
8
:
if
(
dest
<=
src
)
return
avr_asm_len
(
"mov %A0,%B1"
CR_TAB
"mov %B0,%C1"
CR_TAB
"clr %C0"
CR_TAB
"sbrc %B0,7"
CR_TAB
"dec %C0"
,
op
,
plen
,
5
)
;
else
return
avr_asm_len
(
"clr %C0"
CR_TAB
"sbrc %C1,7"
CR_TAB
"dec %C0"
CR_TAB
"mov %B0,%C1"
CR_TAB
"mov %A0,%B1"
,
op
,
plen
,
5
)
;
case
16
:
if
(
dest
!=
src
+
2
)
avr_asm_len
(
"mov %A0,%C1"
,
op
,
plen
,
1
)
;
return
avr_asm_len
(
"clr %B0"
CR_TAB
"sbrc %A0,7"
CR_TAB
"com %B0"
CR_TAB
"mov %C0,%B0"
,
op
,
plen
,
4
)
;
default
:
if
(
INTVAL
(
op
[
2
]
)
<
24
)
break
;
case
23
:
return
avr_asm_len
(
"lsl %C0"
CR_TAB
"sbc %A0,%A0"
CR_TAB
"mov %B0,%A0"
CR_TAB
"mov %C0,%A0"
,
op
,
plen
,
4
)
;
}
}
out_shift_with_cnt
(
"asr %C0"
CR_TAB
"ror %B0"
CR_TAB
"ror %A0"
,
insn
,
op
,
plen
,
3
)
;
return
""
;
}
</s>


<s> void MandarinRegisterInfo :: eliminateFrameIndex ( MachineBasicBlock :: iterator II , int SPAdj , unsigned FIOperandNum , RegScavenger * RS ) const { assert ( SPAdj == 0 && "Unexpected" ) ; MachineInstr & MI = * II ; MachineBasicBlock & MBB = * MI . getParent ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; const TargetFrameLowering * TFI = MF . getTarget ( ) . getFrameLowering ( ) ; DebugLoc dl = MI . getDebugLoc ( ) ; int FrameIndex = MI . getOperand ( FIOperandNum ) . getIndex ( ) ; unsigned BasePtr = ( TFI -> hasFP ( MF ) ? MD :: R31 : MD :: R30 ) ; int Offset = MF . getFrameInfo ( ) -> getObjectOffset ( FrameIndex ) ; if ( ! TFI -> hasFP ( MF ) ) Offset += MF . getFrameInfo ( ) -> getStackSize ( ) ; MachineRegisterInfo & RegInfo = MF . getRegInfo ( ) ; const TargetInstrInfo & TII = * MF . getTarget ( ) . getInstrInfo ( ) ; unsigned VReg = BasePtr ; if ( Offset ) { VReg = RegInfo . createVirtualRegister ( & MD :: GenericRegsRegClass ) ; if ( Offset > 0 ) BuildMI ( MBB , II , dl , TII . get ( MD :: ADDri ) , VReg ) . addReg ( BasePtr ) . addImm ( Offset ) ; else BuildMI ( MBB , II , dl , TII . get ( MD :: SUBri ) , VReg ) . addReg ( BasePtr ) . addImm ( Offset ) ; } MI . getOperand ( FIOperandNum ) . ChangeToRegister ( VReg , false ) ; } </s>

This method must be overriden to eliminate abstract frame indices from instructions which may use them .


<s> void BPFAsmBackend :: applyFixup ( const MCFixup & Fixup , char * Data , unsigned DataSize , uint64_t Value , bool IsPCRel ) const { if ( Fixup . getKind ( ) == FK_SecRel_4 || Fixup . getKind ( ) == FK_SecRel_8 ) { assert ( Value == 0 ) ; return ; } assert ( Fixup . getKind ( ) == FK_PCRel_2 ) ; Value = ( uint16_t ) ( ( Value - 8 ) / 8 ) ; if ( IsLittleEndian ) { Data [ Fixup . getOffset ( ) + 2 ] = Value & 0xFF ; Data [ Fixup . getOffset ( ) + 3 ] = Value >> 8 ; } else { Data [ Fixup . getOffset ( ) + 2 ] = Value >> 8 ; Data [ Fixup . getOffset ( ) + 3 ] = Value & 0xFF ; } } </s>

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


"********** AArch64 Conditional Branch Tuning  **********\n"


<s> bool SparcDAGToDAGISel :: SelectInlineAsmMemoryOperand ( const SDValue & Op , char ConstraintCode , std :: vector < SDValue > & OutOps ) { SDValue Op0 , Op1 ; switch ( ConstraintCode ) { default : return true ; case 'm' : if ( ! SelectADDRrr ( Op , Op0 , Op1 ) ) SelectADDRri ( Op , Op0 , Op1 ) ; break ; } OutOps . push_back ( Op0 ) ; OutOps . push_back ( Op1 ) ; return false ; } </s>

SelectInlineAsmMemoryOperand - Select the specified address as a target addressing mode , according to the specified constraint .


<s> void storeRegToStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI , unsigned SrcReg , bool isKill , int FrameIndex , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const override { storeRegToStack ( MBB , MBBI , SrcReg , isKill , FrameIndex , RC , TRI , 0 ) ; } </s>

Store the specified register of the given register class to the specified stack frame index .


<s> bool riscv_shamt_matches_mask_p ( int shamt , HOST_WIDE_INT mask ) { return shamt == ctz_hwi ( mask ) ; } </s>

Return true if a shift-amount matches the trailing cleared bits on a bitmask .


<s> static bool arc_pass_by_reference ( cumulative_args_t ca_v ATTRIBUTE_UNUSED , machine_mode mode ATTRIBUTE_UNUSED , const_tree type , bool named ATTRIBUTE_UNUSED ) { return ( type != 0 && ( TREE_CODE ( TYPE_SIZE ( type ) ) != INTEGER_CST || TREE_ADDRESSABLE ( type ) ) ) ; } </s>

For ARC , All aggregates and arguments greater than 8 bytes are passed by reference .


<s> int valid_subreg ( rtx op ) { machine_mode om = GET_MODE ( op ) ; machine_mode im = GET_MODE ( SUBREG_REG ( op ) ) ; return om != VOIDmode && im != VOIDmode && ( GET_MODE_SIZE ( im ) == GET_MODE_SIZE ( om ) || ( GET_MODE_SIZE ( im ) <= 4 && GET_MODE_SIZE ( om ) <= 4 ) || ( GET_MODE_SIZE ( im ) >= 16 && GET_MODE_SIZE ( om ) >= 16 ) ) ; } </s>

GCC assumes that in a paradoxical SUBREG the inner mode occupies the least significant bytes of the outer mode . This function returns TRUE for the SUBREG 's where this is correct .


<s> size_t AArch64CA53ErratumStub :: size ( ) const { return m_Size ; } </s>

The number of name/type pairs is returned .


<s> extern bool arm_is_constant_pool_ref ( rtx x ) { return ( MEM_P ( x ) && GET_CODE ( XEXP ( x , 0 ) ) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P ( XEXP ( x , 0 ) ) ) ; } </s>

return TRUE if x is a reference to a value in a constant pool


"%<asm%> flags not supported in thumb1 mode"

Worker function for TARGET_MD_ASM_ADJUST , while in thumb1 mode . Unlike the arm version , we do NOT implement asm flag outputs .


<s> static void ix86_sched_init_global ( FILE * , int , int ) { switch ( ix86_tune ) { case PROCESSOR_CORE2 : case PROCESSOR_NEHALEM : case PROCESSOR_SANDYBRIDGE : case PROCESSOR_HASWELL : if ( reload_completed ) { targetm . sched . dfa_post_advance_cycle = core2i7_dfa_post_advance_cycle ; targetm . sched . first_cycle_multipass_init = core2i7_first_cycle_multipass_init ; targetm . sched . first_cycle_multipass_begin = core2i7_first_cycle_multipass_begin ; targetm . sched . first_cycle_multipass_issue = core2i7_first_cycle_multipass_issue ; targetm . sched . first_cycle_multipass_backtrack = core2i7_first_cycle_multipass_backtrack ; targetm . sched . first_cycle_multipass_end = core2i7_first_cycle_multipass_end ; targetm . sched . first_cycle_multipass_fini = core2i7_first_cycle_multipass_fini ; core2i7_secondary_decoder_max_insn_size = 8 ; core2i7_ifetch_block_size = 16 ; core2i7_ifetch_block_max_insns = 6 ; break ; } default : targetm . sched . dfa_post_advance_cycle = NULL ; targetm . sched . first_cycle_multipass_init = NULL ; targetm . sched . first_cycle_multipass_begin = NULL ; targetm . sched . first_cycle_multipass_issue = NULL ; targetm . sched . first_cycle_multipass_backtrack = NULL ; targetm . sched . first_cycle_multipass_end = NULL ; targetm . sched . first_cycle_multipass_fini = NULL ; break ; } } </s>


<s>
bool
SystemZInstrInfo
::
PredicateInstruction
(
MachineInstr
&
MI
,
ArrayRef
<
MachineOperand
>
Pred
)
const
{
assert
(
Pred
.
size
(
)
==
2
&&
"Invalid condition"
)
;
unsigned
CCValid
=
Pred
[
0
]
.
getImm
(
)
;
unsigned
CCMask
=
Pred
[
1
]
.
getImm
(
)
;
assert
(
CCMask
>
0
&&
CCMask
<
15
&&
"Invalid predicate"
)
;
unsigned
Opcode
=
MI
.
getOpcode
(
)
;
if
(
Opcode
==
SystemZ
::
Trap
)
{
MI
.
setDesc
(
get
(
SystemZ
::
CondTrap
)
)
;
MachineInstrBuilder
(
*
MI
.
getParent
(
)
->
getParent
(
)
,
MI
)
.
addImm
(
CCValid
)
.
addImm
(
CCMask
)
.
addReg
(
SystemZ
::
CC
,
RegState
::
Implicit
)
;
return
true
;
}
if
(
Opcode
==
SystemZ
::
Return
)
{
MI
.
setDesc
(
get
(
SystemZ
::
CondReturn
)
)
;
MachineInstrBuilder
(
*
MI
.
getParent
(
)
->
getParent
(
)
,
MI
)
.
addImm
(
CCValid
)
.
addImm
(
CCMask
)
.
addReg
(
SystemZ
::
CC
,
RegState
::
Implicit
)
;
return
true
;
}
if
(
Opcode
==
SystemZ
::
CallJG
)
{
MachineOperand
FirstOp
=
MI
.
getOperand
(
0
)
;
const
uint32_t
*
RegMask
=
MI
.
getOperand
(
1
)
.
getRegMask
(
)
;
MI
.
RemoveOperand
(
1
)
;
MI
.
RemoveOperand
(
0
)
;
MI
.
setDesc
(
get
(
SystemZ
::
CallBRCL
)
)
;
MachineInstrBuilder
(
*
MI
.
getParent
(
)
->
getParent
(
)
,
MI
)
.
addImm
(
CCValid
)
.
addImm
(
CCMask
)
.
add
(
FirstOp
)
.
addRegMask
(
RegMask
)
.
addReg
(
SystemZ
::
CC
,
RegState
::
Implicit
)
;
return
true
;
}
if
(
Opcode
==
SystemZ
::
CallBR
)
{
const
uint32_t
*
RegMask
=
MI
.
getOperand
(
0
)
.
getRegMask
(
)
;
MI
.
RemoveOperand
(
0
)
;
MI
.
setDesc
(
get
(
SystemZ
::
CallBCR
)
)
;
MachineInstrBuilder
(
*
MI
.
getParent
(
)
->
getParent
(
)
,
MI
)
.
addImm
(
CCValid
)
.
addImm
(
CCMask
)
.
addRegMask
(
RegMask
)
.
addReg
(
SystemZ
::
CC
,
RegState
::
Implicit
)
;
return
true
;
}
return
false
;
}
</s>

Convert the instruction into a predicated instruction .


<s> void emitPrologue ( MachineFunction & MF , MachineBasicBlock & MBB ) const { } </s>

emitProlog/emitEpilog - These methods insert prolog and epilog code into the function .


<s> SDNode * MBlazeDAGToDAGISel :: getGlobalBaseReg ( ) { unsigned GlobalBaseReg = getInstrInfo ( ) -> getGlobalBaseReg ( MF ) ; return CurDAG -> getRegister ( GlobalBaseReg , getTargetLowering ( ) -> getPointerTy ( ) ) . getNode ( ) ; } </s>

getGlobalBaseReg - Return a virtual register initialized with the the global base register value .


<s> yaml :: MachineFunctionInfo * WebAssemblyTargetMachine :: createDefaultFuncInfoYAML ( ) const { return new yaml :: WebAssemblyFunctionInfo ( ) ; } </s>

Allocate and return a default initialized instance of the YAML representation for the MachineFunctionInfo .


<s> bool X86FrameLowering :: restoreCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo * TRI ) const { if ( CSI . empty ( ) ) return false ; if ( MI != MBB . end ( ) && isFuncletReturnInstr ( * MI ) && STI . isOSWindows ( ) ) { if ( STI . is32Bit ( ) ) return true ; if ( MI -> getOpcode ( ) == X86 :: CATCHRET ) { const Function * Func = MBB . getParent ( ) -> getFunction ( ) ; bool IsSEH = isAsynchronousEHPersonality ( classifyEHPersonality ( Func -> getPersonalityFn ( ) ) ) ; if ( IsSEH ) return true ; } } DebugLoc DL = MBB . findDebugLoc ( MI ) ; for ( unsigned i = 0 , e = CSI . size ( ) ; i != e ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; if ( X86 :: GR64RegClass . contains ( Reg ) || X86 :: GR32RegClass . contains ( Reg ) ) continue ; const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ; TII . loadRegFromStackSlot ( MBB , MI , Reg , CSI [ i ] . getFrameIdx ( ) , RC , TRI ) ; } unsigned Opc = STI . is64Bit ( ) ? X86 :: POP64r : X86 :: POP32r ; for ( unsigned i = 0 , e = CSI . size ( ) ; i != e ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; if ( ! X86 :: GR64RegClass . contains ( Reg ) && ! X86 :: GR32RegClass . contains ( Reg ) ) continue ; BuildMI ( MBB , MI , DL , TII . get ( Opc ) , Reg ) . setMIFlag ( MachineInstr :: FrameDestroy ) ; } return true ; } </s>

restoreCalleeSavedRegisters - Issues instruction ( s ) to restore all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of load instructions via loadRegToStackSlot ( ) .


<s>
SDValue
TMS320C64XLowering
::
LowerReturn
(
SDValue
Chain
,
CallingConv
::
ID
CallConv
,
bool
isVarArg
,
const
SmallVectorImpl
<
ISD
::
OutputArg
>
&
Outs
,
const
SmallVectorImpl
<
SDValue
>
&
OutVals
,
DebugLoc
dl
,
SelectionDAG
&
DAG
)
const
{
SmallVector
<
CCValAssign
,
16
>
RLocs
;
SDValue
Flag
;
CCState
CCInfo
(
CallConv
,
isVarArg
,
DAG
.
getTarget
(
)
,
RLocs
,
*
DAG
.
getContext
(
)
)
;
CCInfo
.
AnalyzeReturn
(
Outs
,
RetCC_TMS320C64X
)
;
if
(
DAG
.
getMachineFunction
(
)
.
getRegInfo
(
)
.
liveout_empty
(
)
)
{
for
(
unsigned
i
=
0
;
i
!=
RLocs
.
size
(
)
;
++
i
)
if
(
RLocs
[
i
]
.
isRegLoc
(
)
)
DAG
.
getMachineFunction
(
)
.
getRegInfo
(
)
.
addLiveOut
(
RLocs
[
i
]
.
getLocReg
(
)
)
;
}
for
(
unsigned
i
=
0
;
i
!=
RLocs
.
size
(
)
;
++
i
)
{
CCValAssign
&
VA
=
RLocs
[
i
]
;
assert
(
VA
.
isRegLoc
(
)
&&
"Invalid return position"
)
;
Chain
=
DAG
.
getCopyToReg
(
Chain
,
dl
,
VA
.
getLocReg
(
)
,
OutVals
[
i
]
,
Flag
)
;
Flag
=
Chain
.
getValue
(
1
)
;
}
if
(
Flag
.
getNode
(
)
)
return
DAG
.
getNode
(
TMSISD
::
RETURN_FLAG
,
dl
,
MVT
::
Other
,
Chain
,
Flag
)
;
else
return
DAG
.
getNode
(
TMSISD
::
RETURN_FLAG
,
dl
,
MVT
::
Other
,
Chain
)
;
}
</s>

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .


<s> enum attr_size m68k_sched_attr_size ( rtx_insn * insn ) { switch ( sched_get_attr_size_int ( insn ) ) { case 1 : return SIZE_1 ; case 2 : return SIZE_2 ; case 3 : return SIZE_3 ; default : gcc_unreachable ( ) ; } } </s>

Return size of INSN as attribute enum value .


Create and return the va_list datatype . On S/390 , va_list is an array type equivalent to typedef struct __va_list_tag { long __gpr ; long __fpr ; void * __overflow_arg_area ; void * __reg_save_area ; } va_list [ 1 ] ; where __gpr and __fpr hold the number of general purpose or floating point arguments used up to now , respectively , __overflow_arg_area points to the stack location of the next argument passed on the stack , and __reg_save_area always points to the start of the register area in the call frame of the current function . The function prologue saves all registers used for argument passing into this area if the function uses variable arguments .


<s> void M88kPostLegalizerLowering :: getAnalysisUsage ( AnalysisUsage & AU ) const { AU . addRequired < TargetPassConfig > ( ) ; AU . setPreservesCFG ( ) ; getSelectionDAGFallbackAnalysisUsage ( AU ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> unsigned LEGInstrInfo :: isStoreToStackSlot ( const MachineInstr & MI , int & FrameIndex ) const { assert ( 0 && "Unimplemented" ) ; return 0 ; } </s>

isStoreToStackSlot - If the specified machine instruction is a direct store to a stack slot , return the virtual or physical register number of the source reg along with the FrameIndex of the loaded stack slot .


<s> static rtx nvptx_condjump_label ( const rtx_insn * insn , bool strict = true ) { rtx x = nvptx_pc_set ( insn , strict ) ; if ( ! x ) return NULL_RTX ; x = SET_SRC ( x ) ; if ( GET_CODE ( x ) == LABEL_REF ) return x ; if ( GET_CODE ( x ) != IF_THEN_ELSE ) return NULL_RTX ; if ( XEXP ( x , 2 ) == pc_rtx && GET_CODE ( XEXP ( x , 1 ) ) == LABEL_REF ) return XEXP ( x , 1 ) ; if ( XEXP ( x , 1 ) == pc_rtx && GET_CODE ( XEXP ( x , 2 ) ) == LABEL_REF ) return XEXP ( x , 2 ) ; return NULL_RTX ; } </s>

Variant of condjump_label that only requires JUMP_P ( INSN ) if STRICT .


<s> bool nds32_valid_smw_lwm_base_p ( rtx op ) { rtx base_addr ; if ( ! MEM_P ( op ) ) return false ; base_addr = XEXP ( op , 0 ) ; if ( REG_P ( base_addr ) ) return true ; else { if ( GET_CODE ( base_addr ) == POST_INC && REG_P ( XEXP ( base_addr , 0 ) ) ) return true ; } return false ; } </s>


<s> int64_t getFrequency ( const MachineBasicBlock * MBB , int64_t Default = - 1 ) { FreqMap :: iterator it = BlockFrequencies . find ( MBB ) ; if ( it != BlockFrequencies . end ( ) ) { return it -> second ; } return Default ; } </s>

Returns the frequency as a fixpoint number scaled by the entry frequency .


<s> OffsetRange & shift ( int32_t S ) { assert ( alignTo ( std :: abs ( S ) , Align ) == uint64_t ( std :: abs ( S ) ) ) ; Min += S ; Max += S ; return * this ; } </s>

Create a new AAMDNode that describes this AAMDNode after applying a constant offset to the start of the pointer .


<s> static bool sparc_pass_by_reference ( cumulative_args_t , const function_arg_info & arg ) { tree type = arg . type ; machine_mode mode = arg . mode ; if ( TARGET_ARCH32 ) return ( ( type && ( AGGREGATE_TYPE_P ( type ) || VECTOR_FLOAT_TYPE_P ( type ) ) ) || mode == SCmode || GET_MODE_SIZE ( mode ) > 8 || ( type && VECTOR_TYPE_P ( type ) && ( unsigned HOST_WIDE_INT ) int_size_in_bytes ( type ) > 8 ) ) ; else return ( ( type && ( AGGREGATE_TYPE_P ( type ) || VECTOR_TYPE_P ( type ) ) && ( unsigned HOST_WIDE_INT ) int_size_in_bytes ( type ) > 16 ) || GET_MODE_SIZE ( mode ) > 16 ) ; } </s>

Handle the TARGET_PASS_BY_REFERENCE target hook . Specify whether to pass the argument by reference .


<s> bool AMDGPULowerIntrinsics :: runOnModule ( Module & M ) { bool Changed = false ; for ( Function & F : M ) { if ( ! F . isDeclaration ( ) ) continue ; switch ( F . getIntrinsicID ( ) ) { case Intrinsic :: memcpy : case Intrinsic :: memmove : case Intrinsic :: memset : if ( expandMemIntrinsicUses ( F ) ) Changed = true ; break ; case Intrinsic :: amdgcn_workitem_id_x : case Intrinsic :: r600_read_tidig_x : case Intrinsic :: amdgcn_workitem_id_y : case Intrinsic :: r600_read_tidig_y : case Intrinsic :: amdgcn_workitem_id_z : case Intrinsic :: r600_read_tidig_z : case Intrinsic :: r600_read_local_size_x : case Intrinsic :: r600_read_local_size_y : case Intrinsic :: r600_read_local_size_z : Changed |= makeLIDRangeMetadata ( F ) ; break ; default : break ; } } return Changed ; } </s>

runOnModule - Virtual method overriden by subclasses to process the module being operated on .


<s> bool isBarrier ( ) const { return Kind == k_Barrier ; } </s>

Tests if this is an Order dependence that is marked as a barrier .


<s> void initialize ( Attributor & A ) override { Function * F = getAssociatedFunction ( ) ; auto & InfoCache = static_cast < AMDGPUInformationCache & > ( A . getInfoCache ( ) ) ; unsigned MinGroupSize , MaxGroupSize ; std :: tie ( MinGroupSize , MaxGroupSize ) = InfoCache . getFlatWorkGroupSizes ( * F ) ; intersectKnown ( ConstantRange ( APInt ( 32 , MinGroupSize ) , APInt ( 32 , MaxGroupSize + 1 ) ) ) ; } </s>

Initialize the strategy after building the DAG for a new region .


<s> const unsigned * X86RegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { bool callsEHReturn = false ; bool ghcCall = false ; if ( MF ) { const MachineFrameInfo * MFI = MF -> getFrameInfo ( ) ; const MachineModuleInfo * MMI = MFI -> getMachineModuleInfo ( ) ; callsEHReturn = ( MMI ? MMI -> callsEHReturn ( ) : false ) ; const Function * F = MF -> getFunction ( ) ; ghcCall = ( F ? F -> getCallingConv ( ) == CallingConv :: GHC : false ) ; } static const unsigned GhcCalleeSavedRegs [ ] = { 0 } ; static const unsigned CalleeSavedRegs32Bit [ ] = { X86 :: ESI , X86 :: EDI , X86 :: EBX , X86 :: EBP , 0 } ; static const unsigned CalleeSavedRegs32EHRet [ ] = { X86 :: EAX , X86 :: EDX , X86 :: ESI , X86 :: EDI , X86 :: EBX , X86 :: EBP , 0 } ; static const unsigned CalleeSavedRegs64Bit [ ] = { X86 :: RBX , X86 :: R12 , X86 :: R13 , X86 :: R14 , X86 :: R15 , X86 :: RBP , 0 } ; static const unsigned CalleeSavedRegs64EHRet [ ] = { X86 :: RAX , X86 :: RDX , X86 :: RBX , X86 :: R12 , X86 :: R13 , X86 :: R14 , X86 :: R15 , X86 :: RBP , 0 } ; static const unsigned CalleeSavedRegsWin64 [ ] = { X86 :: RBX , X86 :: RBP , X86 :: RDI , X86 :: RSI , X86 :: R12 , X86 :: R13 , X86 :: R14 , X86 :: R15 , X86 :: XMM6 , X86 :: XMM7 , X86 :: XMM8 , X86 :: XMM9 , X86 :: XMM10 , X86 :: XMM11 , X86 :: XMM12 , X86 :: XMM13 , X86 :: XMM14 , X86 :: XMM15 , 0 } ; if ( ghcCall ) { return GhcCalleeSavedRegs ; } else if ( Is64Bit ) { if ( IsWin64 ) return CalleeSavedRegsWin64 ; else return ( callsEHReturn ? CalleeSavedRegs64EHRet : CalleeSavedRegs64Bit ) ; } else { return ( callsEHReturn ? CalleeSavedRegs32EHRet : CalleeSavedRegs32Bit ) ; } } </s>


<s> void R600MCCodeEmitter :: encodeInstruction ( const MCInst & MI , raw_ostream & OS , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { verifyInstructionPredicates ( MI , computeAvailableFeatures ( STI . getFeatureBits ( ) ) ) ; const MCInstrDesc & Desc = MCII . get ( MI . getOpcode ( ) ) ; if ( MI . getOpcode ( ) == R600 :: RETURN || MI . getOpcode ( ) == R600 :: FETCH_CLAUSE || MI . getOpcode ( ) == R600 :: ALU_CLAUSE || MI . getOpcode ( ) == R600 :: BUNDLE || MI . getOpcode ( ) == R600 :: KILL ) { return ; } else if ( IS_VTX ( Desc ) ) { uint64_t InstWord01 = getBinaryCodeForInstr ( MI , Fixups , STI ) ; uint32_t InstWord2 = MI . getOperand ( 2 ) . getImm ( ) ; if ( ! ( STI . getFeatureBits ( ) [ R600 :: FeatureCaymanISA ] ) ) { InstWord2 |= 1 << 19 ; } Emit ( InstWord01 , OS ) ; Emit ( InstWord2 , OS ) ; Emit ( ( uint32_t ) 0 , OS ) ; } else if ( IS_TEX ( Desc ) ) { int64_t Sampler = MI . getOperand ( 14 ) . getImm ( ) ; int64_t SrcSelect [ 4 ] = { MI . getOperand ( 2 ) . getImm ( ) , MI . getOperand ( 3 ) . getImm ( ) , MI . getOperand ( 4 ) . getImm ( ) , MI . getOperand ( 5 ) . getImm ( ) } ; int64_t Offsets [ 3 ] = { MI . getOperand ( 6 ) . getImm ( ) & 0x1F , MI . getOperand ( 7 ) . getImm ( ) & 0x1F , MI . getOperand ( 8 ) . getImm ( ) & 0x1F } ; uint64_t Word01 = getBinaryCodeForInstr ( MI , Fixups , STI ) ; uint32_t Word2 = Sampler << 15 | SrcSelect [ ELEMENT_X ] << 20 | SrcSelect [ ELEMENT_Y ] << 23 | SrcSelect [ ELEMENT_Z ] << 26 | SrcSelect [ ELEMENT_W ] << 29 | Offsets [ 0 ] << 0 | Offsets [ 1 ] << 5 | Offsets [ 2 ] << 10 ; Emit ( Word01 , OS ) ; Emit ( Word2 , OS ) ; Emit ( ( uint32_t ) 0 , OS ) ; } else { uint64_t Inst = getBinaryCodeForInstr ( MI , Fixups , STI ) ; if ( ( STI . getFeatureBits ( ) [ R600 :: FeatureR600ALUInst ] ) && ( ( Desc . TSFlags & R600_InstFlag :: OP1 ) || Desc . TSFlags & R600_InstFlag :: OP2 ) ) { uint64_t ISAOpCode = Inst & ( 0x3FFULL << 39 ) ; Inst &= ~ ( 0x3FFULL << 39 ) ; Inst |= ISAOpCode << 1 ; } Emit ( Inst , OS ) ; } } </s>

Encode the given Inst to bytes and append to CB .


<s> bool evaluateBranch ( const MCInst & Inst , uint64_t Addr , uint64_t Size , uint64_t & Target ) const override { const MCInstrDesc & Desc = Info -> get ( Inst . getOpcode ( ) ) ; bool FoundImm = false ; int64_t Imm ; for ( unsigned OpNum = 0 ; OpNum < Desc . getNumOperands ( ) ; ++ OpNum ) { if ( Inst . getOperand ( OpNum ) . isImm ( ) && Desc . OpInfo [ OpNum ] . OperandType == MCOI :: OPERAND_PCREL ) { Imm = Inst . getOperand ( OpNum ) . getImm ( ) ; FoundImm = true ; } } if ( ! FoundImm ) return false ; uint64_t Offset = ( ( Desc . TSFlags & ARMII :: FormMask ) == ARMII :: ThumbFrm ) ? 4 : 8 ; Target = Addr + Imm + Offset ; return true ; } </s>

Given a branch instruction try to get the address the branch targets .


<s> static int reg_encoded_number ( rtx reg ) { unsigned regno = REGNO ( reg ) ; switch ( regno ) { case AX_REG : return 0 ; case CX_REG : return 1 ; case DX_REG : return 2 ; case BX_REG : return 3 ; case SP_REG : return 4 ; case BP_REG : return 5 ; case SI_REG : return 6 ; case DI_REG : return 7 ; default : break ; } if ( IN_RANGE ( regno , FIRST_STACK_REG , LAST_STACK_REG ) ) return regno - FIRST_STACK_REG ; if ( IN_RANGE ( regno , FIRST_SSE_REG , LAST_SSE_REG ) ) return regno - FIRST_SSE_REG ; if ( IN_RANGE ( regno , FIRST_MMX_REG , LAST_MMX_REG ) ) return regno - FIRST_MMX_REG ; if ( IN_RANGE ( regno , FIRST_REX_SSE_REG , LAST_REX_SSE_REG ) ) return regno - FIRST_REX_SSE_REG ; if ( IN_RANGE ( regno , FIRST_REX_INT_REG , LAST_REX_INT_REG ) ) return regno - FIRST_REX_INT_REG ; if ( IN_RANGE ( regno , FIRST_MASK_REG , LAST_MASK_REG ) ) return regno - FIRST_MASK_REG ; if ( IN_RANGE ( regno , FIRST_BND_REG , LAST_BND_REG ) ) return regno - FIRST_BND_REG ; return - 1 ; } </s>

Return the number used for encoding REG , in the range 0 .. 7 .


"\nThe total VSETVL expression num = %d\n"

Assemble the candidates expressions for LCM .


<s> void llvm :: emitSPUpdate ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , DebugLoc dl , const TargetInstrInfo & TII , unsigned ScratchReg , int64_t NumBytes , MachineInstr :: MIFlag MIFlags ) { emitRegUpdate ( MBB , MI , dl , TII , AArch64 :: XSP , AArch64 :: XSP , AArch64 :: X16 , NumBytes , MIFlags ) ; } </s>

Emit a series of instructions to increment / decrement the stack pointer by a constant value .


<s> SDValue RISCVSelectionDAGInfo :: EmitTargetCodeForMemcpy ( SelectionDAG & DAG , const SDLoc & dl , SDValue Chain , SDValue Dst , SDValue Src , SDValue Size , Align Alignment , bool isVolatile , bool AlwaysInline , bool MustPreserveCheriCapabilities , MachinePointerInfo DstPtrInfo , MachinePointerInfo SrcPtrInfo ) const { return EmitTargetCodeForMemOp ( DAG , dl , Chain , Dst , Src , Size , Alignment , isVolatile , AlwaysInline , MustPreserveCheriCapabilities , DstPtrInfo , SrcPtrInfo , true ) ; } </s>

Emit target-specific code that performs a memcpy .


<s> bool SIFrameLowering :: hasFP ( const MachineFunction & MF ) const { const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; if ( MFI . hasCalls ( ) && ! MF . getInfo < SIMachineFunctionInfo > ( ) -> isEntryFunction ( ) ) { return MFI . getStackSize ( ) != 0 ; } return frameTriviallyRequiresSP ( MFI ) || MFI . isFrameAddressTaken ( ) || MF . getSubtarget < GCNSubtarget > ( ) . getRegisterInfo ( ) -> hasStackRealignment ( MF ) || MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) ; } </s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . setPreservesCFG ( ) ; if ( UseStackSafety ) AU . addRequired < StackSafetyGlobalInfoWrapperPass > ( ) ; if ( MergeInit ) AU . addRequired < AAResultsWrapperPass > ( ) ; } </s>


<s>
bool
SITargetLowering
::
isLegalAddressingMode
(
const
DataLayout
&
DL
,
const
AddrMode
&
AM
,
Type
*
Ty
,
unsigned
AS
,
Instruction
*
I
)
const
{
if
(
AM
.
BaseGV
)
return
false
;
if
(
AS
==
AMDGPUASI
.
GLOBAL_ADDRESS
)
return
isLegalGlobalAddressingMode
(
AM
)
;
if
(
AS
==
AMDGPUASI
.
CONSTANT_ADDRESS
)
{
if
(
AM
.
BaseOffs
%
4
!=
0
)
return
isLegalMUBUFAddressingMode
(
AM
)
;
if
(
DL
.
getTypeStoreSize
(
Ty
)
<
4
)
return
isLegalGlobalAddressingMode
(
AM
)
;
if
(
Subtarget
->
getGeneration
(
)
==
SISubtarget
::
SOUTHERN_ISLANDS
)
{
if
(
!
isUInt
<
8
>
(
AM
.
BaseOffs
/
4
)
)
return
false
;
}
else
if
(
Subtarget
->
getGeneration
(
)
==
SISubtarget
::
SEA_ISLANDS
)
{
if
(
!
isUInt
<
32
>
(
AM
.
BaseOffs
/
4
)
)
return
false
;
}
else
if
(
Subtarget
->
getGeneration
(
)
>=
SISubtarget
::
VOLCANIC_ISLANDS
)
{
if
(
!
isUInt
<
20
>
(
AM
.
BaseOffs
)
)
return
false
;
}
else
llvm_unreachable
(
"unhandled generation"
)
;
if
(
AM
.
Scale
==
0
)
return
true
;
if
(
AM
.
Scale
==
1
&&
AM
.
HasBaseReg
)
return
true
;
return
false
;
}
else
if
(
AS
==
AMDGPUASI
.
PRIVATE_ADDRESS
)
{
return
isLegalMUBUFAddressingMode
(
AM
)
;
}
else
if
(
AS
==
AMDGPUASI
.
LOCAL_ADDRESS
||
AS
==
AMDGPUASI
.
REGION_ADDRESS
)
{
if
(
!
isUInt
<
16
>
(
AM
.
BaseOffs
)
)
return
false
;
if
(
AM
.
Scale
==
0
)
return
true
;
if
(
AM
.
Scale
==
1
&&
AM
.
HasBaseReg
)
return
true
;
return
false
;
}
else
if
(
AS
==
AMDGPUASI
.
FLAT_ADDRESS
||
AS
==
AMDGPUASI
.
UNKNOWN_ADDRESS_SPACE
)
{
return
isLegalFlatAddressingMode
(
AM
)
;
}
else
{
llvm_unreachable
(
"unhandled address space"
)
;
}
}
</s>

isLegalAddressingMode - Return true if the addressing mode represented by AM is legal for this target , for a load/store of the specified type .


<s> bool AArch64PreLegalizerCombiner :: runOnMachineFunction ( MachineFunction & MF ) { if ( MF . getProperties ( ) . hasProperty ( MachineFunctionProperties :: Property :: FailedISel ) ) return false ; auto * TPC = & getAnalysis < TargetPassConfig > ( ) ; const Function & F = MF . getFunction ( ) ; bool EnableOpt = MF . getTarget ( ) . getOptLevel ( ) != CodeGenOpt :: None && ! skipFunction ( F ) ; AArch64PreLegalizerCombinerInfo PCInfo ( EnableOpt , F . hasOptSize ( ) , F . hasMinSize ( ) ) ; Combiner C ( PCInfo , TPC ) ; return C . combineMachineInstrs ( MF , nullptr ) ; } </s>

runOnMachineFunction - Emit the function body .


<s> bool ia64_expand_load_address ( rtx dest , rtx src ) { gcc_assert ( GET_CODE ( dest ) == REG ) ; if ( GET_MODE ( dest ) != Pmode ) dest = gen_rtx_REG_offset ( dest , Pmode , REGNO ( dest ) , 0 ) ; if ( TARGET_NO_PIC ) return false ; if ( small_addr_symbolic_operand ( src , VOIDmode ) ) return false ; if ( TARGET_AUTO_PIC ) emit_insn ( gen_load_gprel64 ( dest , src ) ) ; else if ( GET_CODE ( src ) == SYMBOL_REF && SYMBOL_REF_FUNCTION_P ( src ) ) emit_insn ( gen_load_fptr ( dest , src ) ) ; else if ( sdata_symbolic_operand ( src , VOIDmode ) ) emit_insn ( gen_load_gprel ( dest , src ) ) ; else { HOST_WIDE_INT addend = 0 ; rtx tmp ; if ( GET_CODE ( src ) == CONST ) { HOST_WIDE_INT hi , lo ; hi = INTVAL ( XEXP ( XEXP ( src , 0 ) , 1 ) ) ; lo = ( ( hi & 0x3fff ) ^ 0x2000 ) - 0x2000 ; hi = hi - lo ; if ( lo != 0 ) { addend = lo ; src = plus_constant ( XEXP ( XEXP ( src , 0 ) , 0 ) , hi ) ; } } tmp = gen_rtx_HIGH ( Pmode , src ) ; tmp = gen_rtx_PLUS ( Pmode , tmp , pic_offset_table_rtx ) ; emit_insn ( gen_rtx_SET ( VOIDmode , dest , tmp ) ) ; tmp = gen_rtx_LO_SUM ( Pmode , dest , src ) ; emit_insn ( gen_rtx_SET ( VOIDmode , dest , tmp ) ) ; if ( addend ) { tmp = gen_rtx_PLUS ( Pmode , dest , GEN_INT ( addend ) ) ; emit_insn ( gen_rtx_SET ( VOIDmode , dest , tmp ) ) ; } } return true ; } </s>


<s> void AMDGPUDAGToDAGISel :: PostprocessISelDAG ( ) { const AMDGPUTargetLowering & Lowering = ( * ( const AMDGPUTargetLowering * ) getTargetLowering ( ) ) ; bool IsModified = false ; do { IsModified = false ; for ( SelectionDAG :: allnodes_iterator I = CurDAG -> allnodes_begin ( ) , E = CurDAG -> allnodes_end ( ) ; I != E ; ++ I ) { SDNode * Node = I ; MachineSDNode * MachineNode = dyn_cast < MachineSDNode > ( I ) ; if ( ! MachineNode ) continue ; SDNode * ResNode = Lowering . PostISelFolding ( MachineNode , * CurDAG ) ; if ( ResNode != Node ) { ReplaceUses ( Node , ResNode ) ; IsModified = true ; } } CurDAG -> RemoveDeadNodes ( ) ; } while ( IsModified ) ; } </s>

PostprocessISelDAG ( ) - This hook allows the target to hack on the graph right after selection .


<s> static bool compute_offset_order ( int nops , HOST_WIDE_INT * unsorted_offsets , int * order , int * unsorted_regs ) { int i ; for ( i = 1 ; i < nops ; i ++ ) { int j ; order [ i ] = order [ i - 1 ] ; for ( j = 0 ; j < nops ; j ++ ) if ( unsorted_offsets [ j ] == unsorted_offsets [ order [ i - 1 ] ] + 4 ) { if ( order [ i ] != order [ i - 1 ] ) return false ; order [ i ] = j ; } if ( order [ i ] == order [ i - 1 ] ) return false ; if ( unsorted_regs != NULL && unsorted_regs [ order [ i ] ] <= unsorted_regs [ order [ i - 1 ] ] ) return false ; } return true ; } </s>

Subroutine of load_multiple_sequence and store_multiple_sequence . Given an array of UNSORTED_OFFSETS , of which there are NOPS , compute an array ORDER which describes the sequence to use when accessing the offsets that produces an ascending order . In this sequence , each offset must be larger by exactly 4 than the previous one . ORDER [ 0 ] must have been filled in with the lowest offset by the caller . If UNSORTED_REGS is nonnull , it is an array of register numbers that we use to verify that ORDER produces an ascending order of registers . Return true if it was possible to construct such an order , false if not .


<s> bool AArch64LoadStoreOpt :: runOnMachineFunction ( MachineFunction & Fn ) { Subtarget = & static_cast < const AArch64Subtarget & > ( Fn . getSubtarget ( ) ) ; TII = static_cast < const AArch64InstrInfo * > ( Subtarget -> getInstrInfo ( ) ) ; TRI = Subtarget -> getRegisterInfo ( ) ; bool Modified = false ; bool enableNarrowLdOpt = enableNarrowLdMerge ( Fn ) ; for ( auto & MBB : Fn ) Modified |= optimizeBlock ( MBB , enableNarrowLdOpt ) ; return Modified ; } </s>


<s> bool enableMachineScheduler ( ) const override { return true ; } </s>

Enable the MachineScheduler pass for all X86 subtargets .


<s> SDValue PPCTargetLowering :: getSqrtResultForDenormInput ( SDValue Op , SelectionDAG & DAG ) const { EVT VT = Op . getValueType ( ) ; if ( VT != MVT :: f64 && ( ( VT != MVT :: v2f64 && VT != MVT :: v4f32 ) || ! Subtarget . hasVSX ( ) ) ) return TargetLowering :: getSqrtResultForDenormInput ( Op , DAG ) ; return DAG . getNode ( PPCISD :: FSQRT , SDLoc ( Op ) , VT , Op ) ; } </s>

Return a target-dependent result if the input operand is not suitable for use with a square root estimate calculation .


<s>
unsigned
SITargetLowering
::
getRegisterByName
(
const
char
*
RegName
,
EVT
VT
,
SelectionDAG
&
DAG
)
const
{
unsigned
Reg
=
StringSwitch
<
unsigned
>
(
RegName
)
.
Case
(
"m0"
,
AMDGPU
::
M0
)
.
Case
(
"exec"
,
AMDGPU
::
EXEC
)
.
Case
(
"exec_lo"
,
AMDGPU
::
EXEC_LO
)
.
Case
(
"exec_hi"
,
AMDGPU
::
EXEC_HI
)
.
Case
(
"flat_scratch"
,
AMDGPU
::
FLAT_SCR
)
.
Case
(
"flat_scratch_lo"
,
AMDGPU
::
FLAT_SCR_LO
)
.
Case
(
"flat_scratch_hi"
,
AMDGPU
::
FLAT_SCR_HI
)
.
Default
(
AMDGPU
::
NoRegister
)
;
if
(
Reg
==
AMDGPU
::
NoRegister
)
{
report_fatal_error
(
Twine
(
"invalid register name \""
+
StringRef
(
RegName
)
+
"\"."
)
)
;
}
if
(
Subtarget
->
getGeneration
(
)
==
SISubtarget
::
SOUTHERN_ISLANDS
&&
Subtarget
->
getRegisterInfo
(
)
->
regsOverlap
(
Reg
,
AMDGPU
::
FLAT_SCR
)
)
{
report_fatal_error
(
Twine
(
"invalid register \""
+
StringRef
(
RegName
)
+
"\" for subtarget."
)
)
;
}
switch
(
Reg
)
{
case
AMDGPU
::
M0
:
case
AMDGPU
::
EXEC_LO
:
case
AMDGPU
::
EXEC_HI
:
case
AMDGPU
::
FLAT_SCR_LO
:
case
AMDGPU
::
FLAT_SCR_HI
:
if
(
VT
.
getSizeInBits
(
)
==
32
)
return
Reg
;
break
;
case
AMDGPU
::
EXEC
:
case
AMDGPU
::
FLAT_SCR
:
if
(
VT
.
getSizeInBits
(
)
==
64
)
return
Reg
;
break
;
default
:
llvm_unreachable
(
"missing register type checking"
)
;
}
report_fatal_error
(
Twine
(
"invalid type for register \""
+
StringRef
(
RegName
)
+
"\"."
)
)
;
}
</s>

Return the register ID of the name passed in .


<s> void aarch64_addti_scratch_regs ( rtx op1 , rtx op2 , rtx * low_dest , rtx * low_in1 , rtx * low_in2 , rtx * high_dest , rtx * high_in1 , rtx * high_in2 ) { * low_dest = gen_reg_rtx ( DImode ) ; * low_in1 = gen_lowpart ( DImode , op1 ) ; * low_in2 = simplify_gen_subreg ( DImode , op2 , TImode , subreg_lowpart_offset ( DImode , TImode ) ) ; * high_dest = gen_reg_rtx ( DImode ) ; * high_in1 = gen_highpart ( DImode , op1 ) ; * high_in2 = simplify_gen_subreg ( DImode , op2 , TImode , subreg_highpart_offset ( DImode , TImode ) ) ; } </s>

Generate DImode scratch registers for 128-bit ( TImode ) addition . OP1 represents the TImode destination operand 1 OP2 represents the TImode destination operand 2 LOW_DEST represents the low half ( DImode ) of TImode operand 0 LOW_IN1 represents the low half ( DImode ) of TImode operand 1 LOW_IN2 represents the low half ( DImode ) of TImode operand 2 HIGH_DEST represents the high half ( DImode ) of TImode operand 0 HIGH_IN1 represents the high half ( DImode ) of TImode operand 1 HIGH_IN2 represents the high half ( DImode ) of TImode operand 2 .