<s>
bool
R600VectorRegMerger
::
runOnMachineFunction
(
MachineFunction
&
Fn
)
{
if
(
skipFunction
(
Fn
.
getFunction
(
)
)
)
return
false
;
const
R600Subtarget
&
ST
=
Fn
.
getSubtarget
<
R600Subtarget
>
(
)
;
TII
=
ST
.
getInstrInfo
(
)
;
MRI
=
&
Fn
.
getRegInfo
(
)
;
for
(
MachineBasicBlock
&
MB
:
Fn
)
{
PreviousRegSeq
.
clear
(
)
;
PreviousRegSeqByReg
.
clear
(
)
;
PreviousRegSeqByUndefCount
.
clear
(
)
;
for
(
MachineBasicBlock
::
iterator
MII
=
MB
.
begin
(
)
,
MIIE
=
MB
.
end
(
)
;
MII
!=
MIIE
;
++
MII
)
{
MachineInstr
&
MI
=
*
MII
;
if
(
MI
.
getOpcode
(
)
!=
R600
::
REG_SEQUENCE
)
{
if
(
TII
->
get
(
MI
.
getOpcode
(
)
)
.
TSFlags
&
R600_InstFlag
::
TEX_INST
)
{
Register
Reg
=
MI
.
getOperand
(
1
)
.
getReg
(
)
;
for
(
MachineRegisterInfo
::
def_instr_iterator
It
=
MRI
->
def_instr_begin
(
Reg
)
,
E
=
MRI
->
def_instr_end
(
)
;
It
!=
E
;
++
It
)
{
RemoveMI
(
&
(
*
It
)
)
;
}
}
continue
;
}
RegSeqInfo
RSI
(
*
MRI
,
&
MI
)
;
Register
Reg
=
MI
.
getOperand
(
0
)
.
getReg
(
)
;
if
(
!
areAllUsesSwizzeable
(
Reg
)
)
continue
;
LLVM_DEBUG
(
{
dbgs
(
)
<<
"Trying to optimize "
;
MI
.
dump
(
)
;
}
)
;
RegSeqInfo
CandidateRSI
;
std
::
vector
<
std
::
pair
<
unsigned
,
unsigned
>>
RemapChan
;
LLVM_DEBUG
(
dbgs
(
)
<<
"Using common slots...\n"
;
)
;
if
(
tryMergeUsingCommonSlot
(
RSI
,
CandidateRSI
,
RemapChan
)
)
{
RemoveMI
(
CandidateRSI
.
Instr
)
;
MII
=
RebuildVector
(
&
RSI
,
&
CandidateRSI
,
RemapChan
)
;
trackRSI
(
RSI
)
;
continue
;
}
LLVM_DEBUG
(
dbgs
(
)
<<
"Using free slots...\n"
;
)
;
RemapChan
.
clear
(
)
;
if
(
tryMergeUsingFreeSlot
(
RSI
,
CandidateRSI
,
RemapChan
)
)
{
RemoveMI
(
CandidateRSI
.
Instr
)
;
MII
=
RebuildVector
(
&
RSI
,
&
CandidateRSI
,
RemapChan
)
;
trackRSI
(
RSI
)
;
continue
;
}
trackRSI
(
RSI
)
;
}
}
</s>

AMDGPU
R600
R600
R600
R600::REG_SEQUENCE
R600_InstFlag::TEX_INST
1
SI
0
"Trying to optimize "
SI
"Using common slots...\n"
SI
SI
SI
SI
SI
SI
SI
"Using free slots...\n"
SI
SI
SI
SI
SI
SI
SI
SI
SI


<s> static bool msp430_hard_regno_mode_ok ( unsigned int regno , machine_mode mode ) { return regno <= ( ARG_POINTER_REGNUM - ( unsigned int ) msp430_hard_regno_nregs ( regno , mode ) ) ; } </s>


<s> static int rs6000_use_sched_lookahead_guard ( rtx_insn * insn , int ready_index ) { if ( ready_index == 0 ) return 0 ; if ( rs6000_cpu_attr != CPU_CELL ) return 0 ; gcc_assert ( insn != NULL_RTX && INSN_P ( insn ) ) ; if ( ! reload_completed || is_nonpipeline_insn ( insn ) || is_microcoded_insn ( insn ) ) return 1 ; return 0 ; } </s>

We are choosing insn from the ready queue . Return zero if INSN can be chosen .


<s> static void unicosmk_file_end ( void ) { fputs ( "\t.endp\n\n" , asm_out_file ) ; unicosmk_output_externs ( asm_out_file ) ; unicosmk_output_dex ( asm_out_file ) ; fputs ( "\t.end\t" , asm_out_file ) ; unicosmk_output_module_name ( asm_out_file ) ; putc ( '\n' , asm_out_file ) ; } </s>

Output text to appear at the end of an assembler file . This includes all pending extern declarations and DEX expressions .


<s>
SDValue
HexagonTargetLowering
::
LowerOperation
(
SDValue
Op
,
SelectionDAG
&
DAG
)
const
{
switch
(
Op
.
getOpcode
(
)
)
{
default
:
llvm_unreachable
(
"Should not custom lower this!"
)
;
case
ISD
::
ConstantPool
:
return
LowerConstantPool
(
Op
,
DAG
)
;
case
ISD
::
EH_RETURN
:
return
LowerEH_RETURN
(
Op
,
DAG
)
;
case
ISD
::
RETURNADDR
:
return
LowerRETURNADDR
(
Op
,
DAG
)
;
case
ISD
::
FRAMEADDR
:
return
LowerFRAMEADDR
(
Op
,
DAG
)
;
case
ISD
::
GlobalTLSAddress
:
llvm_unreachable
(
"TLS not implemented for Hexagon."
)
;
case
ISD
::
ATOMIC_FENCE
:
return
LowerATOMIC_FENCE
(
Op
,
DAG
)
;
case
ISD
::
GlobalAddress
:
return
LowerGLOBALADDRESS
(
Op
,
DAG
)
;
case
ISD
::
BlockAddress
:
return
LowerBlockAddress
(
Op
,
DAG
)
;
case
ISD
::
VASTART
:
return
LowerVASTART
(
Op
,
DAG
)
;
case
ISD
::
BR_JT
:
return
LowerBR_JT
(
Op
,
DAG
)
;
case
ISD
::
DYNAMIC_STACKALLOC
:
return
LowerDYNAMIC_STACKALLOC
(
Op
,
DAG
)
;
case
ISD
::
SELECT
:
return
Op
;
case
ISD
::
INTRINSIC_WO_CHAIN
:
return
LowerINTRINSIC_WO_CHAIN
(
Op
,
DAG
)
;
case
ISD
::
INLINEASM
:
return
LowerINLINEASM
(
Op
,
DAG
)
;
}
}
</s>

LowerOperation - Provide custom lowering hooks for some operations .

Hexagon
Hexagon
"Should not custom lower this!"
ISD::ConstantPool
ISD::EH_RETURN
ISD::RETURNADDR
ISD::FRAMEADDR
ISD::GlobalTLSAddress
"TLS not implemented for Hexagon."
ISD::ATOMIC_FENCE
ISD::GlobalAddress
ISD::BlockAddress
ISD::VASTART
ISD::BR_JT
ISD::DYNAMIC_STACKALLOC
ISD::SELECT
ISD::INTRINSIC_WO_CHAIN
ISD::INLINEASM


<s> static bool classof ( const MCExpr * E ) { return E -> getKind ( ) == MCExpr :: Target ; } </s>

Methods for support type inquiry through isa , cast , and dyn_cast :


"%<#pragma riscv intrinsic%> requires a string parameter"

"%<#pragma riscv intrinsic%> option %qs needs 'V' extension "

"unknown %<#pragma riscv intrinsic%> option %qs"

Implement `` # pragma riscv intrinsic '' .


<s> bool X86AsmBackend :: mayNeedRelaxation ( const MCInst & Inst , const MCSubtargetInfo & STI ) const { if ( getRelaxedOpcodeBranch ( Inst , false ) != Inst . getOpcode ( ) ) return true ; if ( getRelaxedOpcodeArith ( Inst ) == Inst . getOpcode ( ) ) return false ; unsigned RelaxableOp = Inst . getNumOperands ( ) - 1 ; if ( Inst . getOperand ( RelaxableOp ) . isExpr ( ) ) return true ; return false ; } </s>

Check whether the given instruction may need relaxation .


<s> void m32c_function_arg_advance ( CUMULATIVE_ARGS * ca , enum machine_mode mode ATTRIBUTE_UNUSED , tree type ATTRIBUTE_UNUSED , int named ATTRIBUTE_UNUSED ) { if ( ca -> force_mem ) ca -> force_mem = 0 ; ca -> parm_num ++ ; } </s>

Implements FUNCTION_ARG_ADVANCE . force_mem is set for functions returning structures , so we always reset that . Otherwise , we only need to know the sequence number of the argument to know what to do with it .


<s>
bool
R600VectorRegMerger
::
runOnMachineFunction
(
MachineFunction
&
Fn
)
{
TII
=
static_cast
<
const
R600InstrInfo
*
>
(
Fn
.
getSubtarget
(
)
.
getInstrInfo
(
)
)
;
MRI
=
&
(
Fn
.
getRegInfo
(
)
)
;
for
(
MachineFunction
::
iterator
MBB
=
Fn
.
begin
(
)
,
MBBe
=
Fn
.
end
(
)
;
MBB
!=
MBBe
;
++
MBB
)
{
MachineBasicBlock
*
MB
=
MBB
;
PreviousRegSeq
.
clear
(
)
;
PreviousRegSeqByReg
.
clear
(
)
;
PreviousRegSeqByUndefCount
.
clear
(
)
;
for
(
MachineBasicBlock
::
iterator
MII
=
MB
->
begin
(
)
,
MIIE
=
MB
->
end
(
)
;
MII
!=
MIIE
;
++
MII
)
{
MachineInstr
*
MI
=
MII
;
if
(
MI
->
getOpcode
(
)
!=
AMDGPU
::
REG_SEQUENCE
)
{
if
(
TII
->
get
(
MI
->
getOpcode
(
)
)
.
TSFlags
&
R600_InstFlag
::
TEX_INST
)
{
unsigned
Reg
=
MI
->
getOperand
(
1
)
.
getReg
(
)
;
for
(
MachineRegisterInfo
::
def_instr_iterator
It
=
MRI
->
def_instr_begin
(
Reg
)
,
E
=
MRI
->
def_instr_end
(
)
;
It
!=
E
;
++
It
)
{
RemoveMI
(
&
(
*
It
)
)
;
}
}
continue
;
}
RegSeqInfo
RSI
(
*
MRI
,
MI
)
;
unsigned
Reg
=
MI
->
getOperand
(
0
)
.
getReg
(
)
;
if
(
!
areAllUsesSwizzeable
(
Reg
)
)
continue
;
DEBUG
(
dbgs
(
)
<<
"Trying to optimize "
;
MI
->
dump
(
)
;
)
;
RegSeqInfo
CandidateRSI
;
std
::
vector
<
std
::
pair
<
unsigned
,
unsigned
>
>
RemapChan
;
DEBUG
(
dbgs
(
)
<<
"Using common slots...\n"
;
)
;
if
(
tryMergeUsingCommonSlot
(
RSI
,
CandidateRSI
,
RemapChan
)
)
{
RemoveMI
(
CandidateRSI
.
Instr
)
;
MII
=
RebuildVector
(
&
RSI
,
&
CandidateRSI
,
RemapChan
)
;
trackRSI
(
RSI
)
;
continue
;
}
DEBUG
(
dbgs
(
)
<<
"Using free slots...\n"
;
)
;
RemapChan
.
clear
(
)
;
if
(
tryMergeUsingFreeSlot
(
RSI
,
CandidateRSI
,
RemapChan
)
)
{
RemoveMI
(
CandidateRSI
.
Instr
)
;
MII
=
RebuildVector
(
&
RSI
,
&
CandidateRSI
,
RemapChan
)
;
trackRSI
(
RSI
)
;
continue
;
}
trackRSI
(
RSI
)
;
}
}
return
false
;
}
</s>

runOnMachineFunction - Emit the function body .

R600
R600_InstFlag::TEX_INST
1
SI
0
"Trying to optimize "
SI
"Using common slots...\n"
SI
SI
SI
SI
SI
SI
SI
"Using free slots...\n"
SI
SI
SI
SI
SI
SI
SI
SI
SI


<s> static ARM64Operand * CreateMem ( unsigned BaseRegNum , const MCExpr * Off , SMLoc S , SMLoc E , SMLoc OffsetLoc , MCContext & Ctx ) { ARM64Operand * Op = new ARM64Operand ( k_Memory , Ctx ) ; Op -> Mem . BaseRegNum = BaseRegNum ; Op -> Mem . OffsetRegNum = 0 ; Op -> Mem . OffsetImm = Off ; Op -> Mem . ExtType = ARM64_AM :: UXTX ; Op -> Mem . ShiftVal = 0 ; Op -> Mem . ExplicitShift = false ; Op -> Mem . Mode = ImmediateOffset ; Op -> OffsetLoc = OffsetLoc ; Op -> StartLoc = S ; Op -> EndLoc = E ; return Op ; } </s>


<s> static void bfin_function_arg_advance ( cumulative_args_t cum_v , machine_mode mode , const_tree type , bool named ATTRIBUTE_UNUSED ) { CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; int count , bytes , words ; bytes = ( mode == BLKmode ) ? int_size_in_bytes ( type ) : GET_MODE_SIZE ( mode ) ; words = ( bytes + UNITS_PER_WORD - 1 ) / UNITS_PER_WORD ; cum -> words += words ; cum -> nregs -= words ; if ( cum -> nregs <= 0 ) { cum -> nregs = 0 ; cum -> arg_regs = NULL ; } else { for ( count = 1 ; count <= words ; count ++ ) cum -> arg_regs ++ ; } return ; } </s>

Update the data in CUM to advance over an argument of mode MODE and data type TYPE . ( TYPE is null for libcalls where that information may not be available . )


The guts of ix86_expand_vec_perm_const , also used by the ok hook . With all of the interface bits taken care of , perform the expansion in D and return true on success .


<s> static int arm_movmemqi_unaligned ( rtx * operands ) { HOST_WIDE_INT length = INTVAL ( operands [ 2 ] ) ; if ( optimize_size ) { bool src_aligned = MEM_ALIGN ( operands [ 1 ] ) >= BITS_PER_WORD ; bool dst_aligned = MEM_ALIGN ( operands [ 0 ] ) >= BITS_PER_WORD ; unsigned int interleave_factor = ( src_aligned || dst_aligned ) ? 2 : 1 ; HOST_WIDE_INT bytes_per_iter = ( src_aligned || dst_aligned ) ? 8 : 4 ; if ( length > 12 ) arm_block_move_unaligned_loop ( operands [ 0 ] , operands [ 1 ] , length , interleave_factor , bytes_per_iter ) ; else arm_block_move_unaligned_straight ( operands [ 0 ] , operands [ 1 ] , length , interleave_factor ) ; } else { if ( length > 32 ) arm_block_move_unaligned_loop ( operands [ 0 ] , operands [ 1 ] , length , 4 , 16 ) ; else arm_block_move_unaligned_straight ( operands [ 0 ] , operands [ 1 ] , length , 4 ) ; } return 1 ; } </s>

Emit a block move when either the source or destination is unaligned ( not aligned to a four-byte boundary ) . This may need further tuning depending on core type , optimize_size setting , etc .


<s> void HexagonDAGToDAGISel :: PreprocessISelDAG ( ) { SelectionDAG & DAG = * CurDAG ; std :: vector < SDNode * > Nodes ; for ( auto I = DAG . allnodes_begin ( ) , E = DAG . allnodes_end ( ) ; I != E ; ++ I ) Nodes . push_back ( I ) ; for ( auto I : Nodes ) { if ( I -> getOpcode ( ) != ISD :: OR ) continue ; auto IsZero = [ ] ( const SDValue & V ) -> bool { if ( ConstantSDNode * SC = dyn_cast < ConstantSDNode > ( V . getNode ( ) ) ) return SC -> isNullValue ( ) ; return false ; } ; auto IsSelect0 = [ IsZero ] ( const SDValue & Op ) -> bool { if ( Op . getOpcode ( ) != ISD :: SELECT ) return false ; return IsZero ( Op . getOperand ( 1 ) ) || IsZero ( Op . getOperand ( 2 ) ) ; } ; SDValue N0 = I -> getOperand ( 0 ) , N1 = I -> getOperand ( 1 ) ; EVT VT = I -> getValueType ( 0 ) ; bool SelN0 = IsSelect0 ( N0 ) ; SDValue SOp = SelN0 ? N0 : N1 ; SDValue VOp = SelN0 ? N1 : N0 ; if ( SOp . getOpcode ( ) == ISD :: SELECT && SOp . getNode ( ) -> hasOneUse ( ) ) { SDValue SC = SOp . getOperand ( 0 ) ; SDValue SX = SOp . getOperand ( 1 ) ; SDValue SY = SOp . getOperand ( 2 ) ; SDLoc DLS = SOp ; if ( IsZero ( SY ) ) { SDValue NewOr = DAG . getNode ( ISD :: OR , DLS , VT , SX , VOp ) ; SDValue NewSel = DAG . getNode ( ISD :: SELECT , DLS , VT , SC , NewOr , VOp ) ; DAG . ReplaceAllUsesWith ( I , NewSel . getNode ( ) ) ; } else if ( IsZero ( SX ) ) { SDValue NewOr = DAG . getNode ( ISD :: OR , DLS , VT , SY , VOp ) ; SDValue NewSel = DAG . getNode ( ISD :: SELECT , DLS , VT , SC , VOp , NewOr ) ; DAG . ReplaceAllUsesWith ( I , NewSel . getNode ( ) ) ; } } } } </s>

PreprocessISelDAG - This hook allows targets to hack on the graph before instruction selection starts .


<s> StringRef PPCInstPrinter :: getOpcodeName ( unsigned Opcode ) const { return getInstructionName ( Opcode ) ; } </s>

Return a string representation for an opcode .


<s> SDValue X86TargetLowering :: PerformDAGCombine ( SDNode * N , DAGCombinerInfo & DCI ) const { SelectionDAG & DAG = DCI . DAG ; switch ( N -> getOpcode ( ) ) { default : break ; case ISD :: EXTRACT_VECTOR_ELT : return PerformEXTRACT_VECTOR_ELTCombine ( N , DAG , * this ) ; case ISD :: VSELECT : case ISD :: SELECT : return PerformSELECTCombine ( N , DAG , DCI , Subtarget ) ; case X86ISD :: CMOV : return PerformCMOVCombine ( N , DAG , DCI ) ; case ISD :: ADD : return PerformAddCombine ( N , DAG , Subtarget ) ; case ISD :: SUB : return PerformSubCombine ( N , DAG , Subtarget ) ; case X86ISD :: ADC : return PerformADCCombine ( N , DAG , DCI ) ; case ISD :: MUL : return PerformMulCombine ( N , DAG , DCI ) ; case ISD :: SHL : case ISD :: SRA : case ISD :: SRL : return PerformShiftCombine ( N , DAG , Subtarget ) ; case ISD :: AND : return PerformAndCombine ( N , DAG , DCI , Subtarget ) ; case ISD :: OR : return PerformOrCombine ( N , DAG , DCI , Subtarget ) ; case ISD :: XOR : return PerformXorCombine ( N , DAG , DCI , Subtarget ) ; case ISD :: LOAD : return PerformLOADCombine ( N , DAG , Subtarget ) ; case ISD :: STORE : return PerformSTORECombine ( N , DAG , Subtarget ) ; case ISD :: SINT_TO_FP : return PerformSINT_TO_FPCombine ( N , DAG , this ) ; case ISD :: FADD : return PerformFADDCombine ( N , DAG , Subtarget ) ; case ISD :: FSUB : return PerformFSUBCombine ( N , DAG , Subtarget ) ; case X86ISD :: FXOR : case X86ISD :: FOR : return PerformFORCombine ( N , DAG ) ; case X86ISD :: FAND : return PerformFANDCombine ( N , DAG ) ; case X86ISD :: BT : return PerformBTCombine ( N , DAG , DCI ) ; case X86ISD :: VZEXT_MOVL : return PerformVZEXT_MOVLCombine ( N , DAG ) ; case ISD :: ZERO_EXTEND : return PerformZExtCombine ( N , DAG , Subtarget ) ; case X86ISD :: SETCC : return PerformSETCCCombine ( N , DAG ) ; case X86ISD :: SHUFP : case X86ISD :: PALIGN : case X86ISD :: UNPCKH : case X86ISD :: UNPCKL : case X86ISD :: MOVHLPS : case X86ISD :: MOVLHPS : case X86ISD :: PSHUFD : case X86ISD :: PSHUFHW : case X86ISD :: PSHUFLW : case X86ISD :: MOVSS : case X86ISD :: MOVSD : case X86ISD :: VPERMILP : case X86ISD :: VPERM2X128 : case ISD :: VECTOR_SHUFFLE : return PerformShuffleCombine ( N , DAG , DCI , Subtarget ) ; } return SDValue ( ) ; } </s>

This method will be invoked for all target nodes and for any target-independent nodes that the target has registered with invoke it for .


<s> PreservedAnalyses AMDGPUPromoteAllocaToVectorPass :: run ( Function & F , FunctionAnalysisManager & AM ) { bool Changed = promoteAllocasToVector ( F , TM ) ; if ( Changed ) { PreservedAnalyses PA ; PA . preserveSet < CFGAnalyses > ( ) ; return PA ; } return PreservedAnalyses :: all ( ) ; } </s>

Run the analysis pass over a function and produce a dominator tree .


<s> bool HexagonTargetLowering :: getPostIndexedAddressParts ( SDNode * N , SDNode * Op , SDValue & Base , SDValue & Offset , ISD :: MemIndexedMode & AM , SelectionDAG & DAG ) const { EVT VT ; SDValue Ptr ; if ( LoadSDNode * LD = dyn_cast < LoadSDNode > ( N ) ) { VT = LD -> getMemoryVT ( ) ; } else if ( StoreSDNode * ST = dyn_cast < StoreSDNode > ( N ) ) { VT = ST -> getMemoryVT ( ) ; if ( ST -> getValue ( ) . getValueType ( ) == MVT :: i64 && ST -> isTruncatingStore ( ) ) return false ; } else { return false ; } bool IsInc = false ; bool isLegal = getIndexedAddressParts ( Op , VT , Base , Offset , IsInc , DAG ) ; if ( isLegal ) { auto & HII = * Subtarget . getInstrInfo ( ) ; int32_t OffsetVal = cast < ConstantSDNode > ( Offset . getNode ( ) ) -> getSExtValue ( ) ; if ( HII . isValidAutoIncImm ( VT , OffsetVal ) ) { AM = IsInc ? ISD :: POST_INC : ISD :: POST_DEC ; return true ; } } return false ; } </s>

Returns true by value , base pointer and offset pointer and addressing mode by reference if this node can be combined with a load / store to form a post-indexed load / store .


<s> bool isBarrier ( ) const { return Kind == k_Barrier ; } </s>

Tests if this is an Order dependence that is marked as a barrier .


"\n# of loads of an address of an external symbol = %lu\n"

"# of PCREL_OPT loads = %lu (adjacent %lu)\n"

"# of PCREL_OPT stores = %lu (adjacent %lu)\n"

Optimize pcrel external variable references .


"don't know how to get the name for this callee"


<s>
bool
HexagonCommonGEP
::
runOnFunction
(
Function
&
F
)
{
if
(
skipFunction
(
F
)
)
return
false
;
for
(
const
BasicBlock
&
BB
:
F
)
for
(
const
Instruction
&
I
:
BB
)
if
(
isa
<
InvokeInst
>
(
I
)
||
isa
<
LandingPadInst
>
(
I
)
)
return
false
;
Fn
=
&
F
;
DT
=
&
getAnalysis
<
DominatorTreeWrapperPass
>
(
)
.
getDomTree
(
)
;
PDT
=
&
getAnalysis
<
PostDominatorTreeWrapperPass
>
(
)
.
getPostDomTree
(
)
;
LI
=
&
getAnalysis
<
LoopInfoWrapperPass
>
(
)
.
getLoopInfo
(
)
;
Ctx
=
&
F
.
getContext
(
)
;
Nodes
.
clear
(
)
;
Uses
.
clear
(
)
;
NodeOrder
.
clear
(
)
;
SpecificBumpPtrAllocator
<
GepNode
>
Allocator
;
Mem
=
&
Allocator
;
collect
(
)
;
common
(
)
;
NodeToValueMap
Loc
;
computeNodePlacement
(
Loc
)
;
materialize
(
Loc
)
;
removeDeadCode
(
)
;
if
(
verifyFunction
(
F
,
&
dbgs
(
)
)
)
report_fatal_error
(
"Broken function"
)
;
return
true
;
}
</s>

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .


<s> const MCPhysReg * AArch64TargetLowering :: getScratchRegisters ( CallingConv :: ID ) const { static const MCPhysReg ScratchRegs [ ] = { AArch64 :: X16 , AArch64 :: X17 , AArch64 :: LR , 0 } ; return ScratchRegs ; } </s>

Returns a 0 terminated array of registers that can be safely used as scratch registers .


<s> static bool arm_const_double_prefer_rsbs_rsc ( rtx op ) { if ( TARGET_THUMB || ! CONST_INT_P ( op ) ) return false ; HOST_WIDE_INT hi , lo ; lo = UINTVAL ( op ) & 0xffffffffULL ; hi = UINTVAL ( op ) >> 32 ; return const_ok_for_arm ( lo ) && const_ok_for_arm ( hi ) ; } </s>

Return TRUE if op is a constant where both the low and top words are suitable for RSB/RSC instructions . This is never true for Thumb , since we do not have RSC in that case .


"internal error inserting '%s' in bifo_rbt\n"

Parse a two-line entry for a built-in function .


<s> bool ARMPassConfig :: addPreEmitPass ( ) { if ( getARMSubtarget ( ) . isThumb2 ( ) ) { if ( ! getARMSubtarget ( ) . prefers32BitThumb ( ) ) PM -> add ( createThumb2SizeReductionPass ( ) ) ; addPass ( UnpackMachineBundlesID ) ; } PM -> add ( createARMConstantIslandPass ( ) ) ; return true ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s> static tree ix86_md_asm_clobbers ( tree , tree , tree clobbers ) { clobbers = tree_cons ( NULL_TREE , build_string ( 5 , "flags" ) , clobbers ) ; clobbers = tree_cons ( NULL_TREE , build_string ( 4 , "fpsr" ) , clobbers ) ; return clobbers ; } </s>

Worker function for TARGET_MD_ASM_CLOBBERS . We do this in the new i386 backend to maintain source compatibility with the old cc0-based compiler .


<s> unsigned int ix86_minimum_alignment ( tree exp , machine_mode mode , unsigned int align ) { tree type , decl ; if ( exp && DECL_P ( exp ) ) { type = TREE_TYPE ( exp ) ; decl = exp ; } else { type = exp ; decl = NULL ; } if ( TARGET_64BIT || align != 64 || ix86_preferred_stack_boundary >= 64 ) return align ; if ( ( mode == DImode || ( type && TYPE_MODE ( type ) == DImode ) ) && ( ! type || ! TYPE_USER_ALIGN ( type ) ) && ( ! decl || ! DECL_USER_ALIGN ( decl ) ) ) return 32 ; return align ; } </s>

Compute the minimum required alignment for dynamic stack realignment purposes for a local variable , parameter or a stack slot . EXP is the data type or decl itself , MODE is its mode and ALIGN is the alignment that the object would ordinarily have .


<s> bool isCtlzFast ( ) const override { return true ; } </s>

Return true if ctlz instruction is fast .


<s> void TL45MCCodeEmitter :: encodeInstruction ( const MCInst & Inst , raw_ostream & OS , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { uint32_t CurByte = 0 ; unsigned Value = getBinaryCodeForInstr ( Inst , Fixups , STI ) ; EmitBEConstant ( Value , 4 , CurByte , OS ) ; } </s>

Encode the given Inst to bytes and append to CB .


<s> bool M680x0Subtarget :: isLegalToCallImmediateAddr ( ) const { return true ; } </s>

Return true if the subtarget allows calls to immediate address .


<s> bool ARMTargetLowering :: getPostIndexedAddressParts ( SDNode * N , SDNode * Op , SDValue & Base , SDValue & Offset , ISD :: MemIndexedMode & AM , SelectionDAG & DAG ) const { if ( Subtarget -> isThumb1Only ( ) ) return false ; EVT VT ; SDValue Ptr ; bool isSEXTLoad = false ; if ( LoadSDNode * LD = dyn_cast < LoadSDNode > ( N ) ) { VT = LD -> getMemoryVT ( ) ; Ptr = LD -> getBasePtr ( ) ; isSEXTLoad = LD -> getExtensionType ( ) == ISD :: SEXTLOAD ; } else if ( StoreSDNode * ST = dyn_cast < StoreSDNode > ( N ) ) { VT = ST -> getMemoryVT ( ) ; Ptr = ST -> getBasePtr ( ) ; } else return false ; bool isInc ; bool isLegal = false ; if ( Subtarget -> isThumb2 ( ) ) isLegal = getT2IndexedAddressParts ( Op , VT , isSEXTLoad , Base , Offset , isInc , DAG ) ; else isLegal = getARMIndexedAddressParts ( Op , VT , isSEXTLoad , Base , Offset , isInc , DAG ) ; if ( ! isLegal ) return false ; if ( Ptr != Base ) { if ( Ptr == Offset && Op -> getOpcode ( ) == ISD :: ADD && ! Subtarget -> isThumb2 ( ) ) std :: swap ( Base , Offset ) ; if ( Ptr != Base ) return false ; } AM = isInc ? ISD :: POST_INC : ISD :: POST_DEC ; return true ; } </s>

ARM ARM ISD::MemIndexedMode ISD::SEXTLOAD ARM ISD::ADD ISD::POST_INC ISD::POST_DEC


<s> static tree aarch64_stack_protect_guard ( void ) { if ( aarch64_stack_protector_guard == SSP_GLOBAL ) return default_stack_protect_guard ( ) ; return NULL_TREE ; } </s>

Implement TARGET_STACK_PROTECT_GUARD . In case of a global variable based guard use the default else return a null tree .


"Do not know how to lower this BUILD_VECTOR"

Main hook for targets to transform nodes into machine nodes .


<s> int Z80InstrInfo :: getSPAdjust ( const MachineInstr & MI ) const { switch ( MI . getOpcode ( ) ) { case Z80 :: POP16r : case Z80 :: POP16AF : return 2 ; case Z80 :: POP24r : case Z80 :: POP24AF : return 3 ; case Z80 :: PUSH16r : case Z80 :: PUSH16AF : case Z80 :: PEA16o : return - 2 ; case Z80 :: PUSH24r : case Z80 :: PUSH24AF : case Z80 :: PEA24o : return - 3 ; } return TargetInstrInfo :: getSPAdjust ( MI ) ; } </s>

getSPAdjust - This returns the stack pointer adjustment made by this instruction .


<s> void arm_load_pic_register ( unsigned long saved_regs ATTRIBUTE_UNUSED ) { rtx l1 , labelno , pic_tmp , pic_rtx , pic_reg ; if ( crtl -> uses_pic_offset_table == 0 || TARGET_SINGLE_PIC_BASE ) return ; gcc_assert ( flag_pic ) ; pic_reg = cfun -> machine -> pic_reg ; if ( TARGET_VXWORKS_RTP ) { pic_rtx = gen_rtx_SYMBOL_REF ( Pmode , VXWORKS_GOTT_BASE ) ; pic_rtx = gen_rtx_CONST ( Pmode , pic_rtx ) ; emit_insn ( gen_pic_load_addr_32bit ( pic_reg , pic_rtx ) ) ; emit_insn ( gen_rtx_SET ( pic_reg , gen_rtx_MEM ( Pmode , pic_reg ) ) ) ; pic_tmp = gen_rtx_SYMBOL_REF ( Pmode , VXWORKS_GOTT_INDEX ) ; emit_insn ( gen_pic_offset_arm ( pic_reg , pic_reg , pic_tmp ) ) ; } else { labelno = GEN_INT ( pic_labelno ++ ) ; l1 = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( 1 , labelno ) , UNSPEC_PIC_LABEL ) ; l1 = gen_rtx_CONST ( VOIDmode , l1 ) ; pic_rtx = plus_constant ( Pmode , l1 , TARGET_ARM ? 8 : 4 ) ; pic_rtx = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( 1 , pic_rtx ) , UNSPEC_GOTSYM_OFF ) ; pic_rtx = gen_rtx_CONST ( Pmode , pic_rtx ) ; if ( TARGET_32BIT ) { emit_insn ( gen_pic_load_addr_unified ( pic_reg , pic_rtx , labelno ) ) ; } else { if ( arm_pic_register != INVALID_REGNUM && REGNO ( pic_reg ) > LAST_LO_REGNUM ) { pic_tmp = gen_rtx_REG ( SImode , thumb_find_work_register ( saved_regs ) ) ; emit_insn ( gen_pic_load_addr_thumb1 ( pic_tmp , pic_rtx ) ) ; emit_insn ( gen_movsi ( pic_offset_table_rtx , pic_tmp ) ) ; emit_insn ( gen_pic_add_dot_plus_four ( pic_reg , pic_reg , labelno ) ) ; } else if ( arm_pic_register != INVALID_REGNUM && arm_pic_register > LAST_LO_REGNUM && REGNO ( pic_reg ) <= LAST_LO_REGNUM ) { emit_insn ( gen_pic_load_addr_unified ( pic_reg , pic_rtx , labelno ) ) ; emit_move_insn ( gen_rtx_REG ( Pmode , arm_pic_register ) , pic_reg ) ; emit_use ( gen_rtx_REG ( Pmode , arm_pic_register ) ) ; } else emit_insn ( gen_pic_load_addr_unified ( pic_reg , pic_rtx , labelno ) ) ; } } emit_use ( pic_reg ) ; } </s>

Generate code to load the PIC register . In thumb mode SCRATCH is a low register .


<s> void ARMElfTargetObjectFile :: Initialize ( MCContext & Ctx , const TargetMachine & TM ) { bool isAAPCS_ABI = TM . getSubtarget < ARMSubtarget > ( ) . isAAPCS_ABI ( ) ; TargetLoweringObjectFileELF :: Initialize ( Ctx , TM ) ; InitializeELF ( isAAPCS_ABI ) ; if ( isAAPCS_ABI ) { LSDASection = nullptr ; } AttributesSection = getContext ( ) . getELFSection ( ".ARM.attributes" , ELF :: SHT_ARM_ATTRIBUTES , 0 , SectionKind :: getMetadata ( ) ) ; } </s>

This method must be called before any actual lowering is done .


"\t%@ Function supports interworking.\n"

"\t%@ Fast Interrupt Service Routine.\n"

"\t%@ Naked Function: prologue and epilogue provided by programmer.\n"

"\t%@ Volatile: function does not return.\n"

"\t%@ Nested: function declared inside another function.\n"

"\t%@ Stack Align: May be called with mis-aligned SP.\n"

"\t%@ Non-secure entry function: called from non-secure code.\n"

"\t%@ args = %wd, pretend = %d, frame = %wd\n"

"\t%@ frame_needed = %d, uses_anonymous_args = %d\n"

Place some comments into the assembler stream describing the current function .


<s> MachineBasicBlock * R600MachineCFGStructurizer :: clone ( MachineBasicBlock * MBB ) { MachineFunction * Func = MBB -> getParent ( ) ; MachineBasicBlock * NewMBB = Func -> CreateMachineBasicBlock ( ) ; Func -> push_back ( NewMBB ) ; for ( const MachineInstr & It : * MBB ) NewMBB -> push_back ( Func -> CloneMachineInstr ( & It ) ) ; return NewMBB ; } </s>

Make a functionally equivalent copy of this MachineFunctionInfo in MF .


<s> int lm32_return_in_memory ( tree type ) { HOST_WIDE_INT size ; if ( ! AGGREGATE_TYPE_P ( type ) ) { return 0 ; } size = int_size_in_bytes ( type ) ; if ( size >= 0 && size <= UNITS_PER_WORD ) { return 0 ; } return 1 ; } </s>

Return non-zero if the given return type should be returned in memory .


<s> void mips_declare_object_name ( FILE * stream , const char * name , tree decl ATTRIBUTE_UNUSED ) { if ( USE_GNU_UNIQUE_OBJECT && DECL_ONE_ONLY ( decl ) && ( ! DECL_ARTIFICIAL ( decl ) || ! TREE_READONLY ( decl ) ) ) ASM_OUTPUT_TYPE_DIRECTIVE ( stream , name , "gnu_unique_object" ) ; else ASM_OUTPUT_TYPE_DIRECTIVE ( stream , name , "object" ) ; size_directive_output = 0 ; if ( ! flag_inhibit_size_directive && DECL_SIZE ( decl ) ) { HOST_WIDE_INT size ; size_directive_output = 1 ; size = int_size_in_bytes ( TREE_TYPE ( decl ) ) ; ASM_OUTPUT_SIZE_DIRECTIVE ( stream , name , size ) ; } mips_declare_object ( stream , name , "" , ":\n" ) ; } </s>

Implement ASM_DECLARE_OBJECT_NAME . This is like most of the standard ELF definitions except that it uses mips_declare_object ( ) to emit the label .


<s> bool M68kCallLowering :: lowerCall ( MachineIRBuilder & MIRBuilder , CallLoweringInfo & Info ) const { return false ; } </s>

This hook must be implemented to lower the given call instruction , including argument and return value marshalling .


<s> static bool ix86_nopic_noplt_attribute_p ( rtx call_op ) { if ( flag_pic || ix86_cmodel == CM_LARGE || ! TARGET_64BIT || TARGET_MACHO || TARGET_SEH || TARGET_PECOFF || SYMBOL_REF_LOCAL_P ( call_op ) ) return false ; tree symbol_decl = SYMBOL_REF_DECL ( call_op ) ; if ( ! flag_plt || ( symbol_decl != NULL_TREE && lookup_attribute ( "noplt" , DECL_ATTRIBUTES ( symbol_decl ) ) ) ) return true ; return false ; } </s>

Return true if the function being called was marked with attribute `` noplt '' or using -fno-plt and we are compiling for non-PIC and x86_64 . We need to handle the non-PIC case in the backend because there is no easy interface for the front-end to force non-PLT calls to use the GOT . This is currently used only with 64-bit ELF targets to call the function marked `` noplt '' indirectly .


<s> const MCPhysReg * RISCVRegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { return CSR_SaveList ; } </s>


<s>
StringRef
getPassName
(
)
const
override
{
return
"DLX load / store optimization pass"
;
}
</s>

getPassName - Return a nice clean name for a pass .

DLX
"DLX load / store optimization pass"


<s> bool SystemZShortenInst :: runOnMachineFunction ( MachineFunction & F ) { if ( skipFunction ( * F . getFunction ( ) ) ) return false ; const SystemZSubtarget & ST = F . getSubtarget < SystemZSubtarget > ( ) ; TII = ST . getInstrInfo ( ) ; TRI = ST . getRegisterInfo ( ) ; LiveRegs . init ( * TRI ) ; bool Changed = false ; for ( auto & MBB : F ) Changed |= processBlock ( MBB ) ; return Changed ; } </s>

runOnMachineFunction - Emit the function body .


<s> int mt_epilogue_uses ( int regno ) { if ( cfun -> machine && cfun -> machine -> interrupt_handler && reload_completed ) return 1 ; return regno == GPR_LINK ; } </s>


<s> static bool can_avoid_literal_pool_for_label_p ( rtx x ) { if ( arm_disable_literal_pool && SYMBOL_REF_P ( x ) && CONSTANT_POOL_ADDRESS_P ( x ) ) return 1 ; return 0 ; } </s>

Return true if we can avoid creating a constant pool entry for x .


<s> static rtx compute_frame_addr ( int offset_from_fp , int * next_scratch_regno ) { rtx base_reg_rtx , tmp_reg_rtx , offset_rtx ; int offset_from_base ; if ( frame_pointer_needed ) { base_reg_rtx = hard_frame_pointer_rtx ; offset_from_base = offset_from_fp ; } else { int offset_from_sp = compute_total_frame_size ( ) + offset_from_fp ; base_reg_rtx = stack_pointer_rtx ; offset_from_base = offset_from_sp ; } if ( offset_from_base == 0 ) return base_reg_rtx ; tmp_reg_rtx = gen_rtx_REG ( Pmode , ( * next_scratch_regno ) -- ) ; offset_rtx = gen_int_si ( offset_from_base ) ; if ( ! tilepro_expand_addsi ( tmp_reg_rtx , base_reg_rtx , offset_rtx ) ) { emit_insn ( gen_rtx_SET ( tmp_reg_rtx , gen_rtx_PLUS ( Pmode , base_reg_rtx , offset_rtx ) ) ) ; } return tmp_reg_rtx ; } </s>

Returns an rtx for a stack slot at 'FP + offset_from_fp ' . If there is a frame pointer , it computes the value relative to that . Otherwise it uses the stack pointer .


<s> const char * RV16KTargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( ( RV16KISD :: NodeType ) Opcode ) { case RV16KISD :: FIRST_NUMBER : break ; case RV16KISD :: RET_FLAG : return "RV16KISD::RET_FLAG" ; case RV16KISD :: CALL : return "RV16KISD::CALL" ; case RV16KISD :: BR_CC : return "RV16KISD::BR_CC" ; case RV16KISD :: SELECT_CC : return "RV16KISD::SELECT_CC" ; case RV16KISD :: TAIL : return "RV16KISD::TAIL" ; } return nullptr ; } </s>

getTargetNodeName - This method returns the name of a target specific


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . setPreservesCFG ( ) ; AU . addRequired < AAResultsWrapperPass > ( ) ; AU . addRequired < MachineBranchProbabilityInfo > ( ) ; AU . addRequired < MachineDominatorTree > ( ) ; AU . addRequired < MachineLoopInfo > ( ) ; AU . addPreserved < MachineDominatorTree > ( ) ; AU . addPreserved < MachineLoopInfo > ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> FastISel * X86TargetLowering :: createFastISel ( MachineFunction & mf , MachineModuleInfo * mmo , DwarfWriter * dw , DenseMap < const Value * , unsigned > & vm , DenseMap < const BasicBlock * , MachineBasicBlock * > & bm , DenseMap < const AllocaInst * , int > & am , SmallSet < Instruction * , 8 > & cil ) { return X86 :: createFastISel ( mf , mmo , dw , vm , bm , am , cil ) ; } </s>

This method returns a target specific FastISel object , or null if the target does not support `` fast '' ISel .


<s> int nds32_can_use_return_insn ( void ) { if ( ! reload_completed ) return 0 ; return ( cfun -> machine -> naked_p && ( cfun -> machine -> va_args_size == 0 ) ) ; } </s>

Return nonzero if this function is known to have a null epilogue . This allows the optimizer to omit jumps to jumps if no stack was created .


<s> const TPCRegisterInfo & getRegisterInfo ( ) const { return RI ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s>
virtual
void
dump
(
const
TargetRegisterInfo
*
TRI
,
int
depth
=
0
)
{
dumpDepth
(
depth
)
;
dbgs
(
)
<<
"Region: "
<<
(
void
*
)
Region
;
dbgs
(
)
<<
" In: "
<<
PrintReg
(
getBBSelectRegIn
(
)
,
TRI
)
;
dbgs
(
)
<<
", Out: "
<<
PrintReg
(
getBBSelectRegOut
(
)
,
TRI
)
<<
"\n"
;
dumpDepth
(
depth
)
;
if
(
getSucc
(
)
)
dbgs
(
)
<<
"Succ: "
<<
getSucc
(
)
->
getNumber
(
)
<<
"\n"
;
else
dbgs
(
)
<<
"Succ: none \n"
;
for
(
auto
MRTI
:
Children
)
{
MRTI
->
dump
(
TRI
,
depth
+
1
)
;
}
}
</s>

Dump the plan to stderr ( for debugging ) .

AMDGPU
0
"Region: "
" In: "
", Out: "
"\n"
"Succ: "
"\n"
"Succ: none \n"
1


<s> static bool unknown_for_bundling_p ( rtx_insn * insn ) { return ( INSN_P ( insn ) && ia64_safe_itanium_class ( insn ) == ITANIUM_CLASS_UNKNOWN && GET_CODE ( PATTERN ( insn ) ) != USE && GET_CODE ( PATTERN ( insn ) ) != CLOBBER ) ; } </s>

True when INSN is unknown , but important , for bundling .


<s> X86GenInstrInfo :: MachineOutlinerInstrType X86InstrInfo :: getOutliningType ( MachineBasicBlock :: iterator & MIT , unsigned Flags ) const { MachineInstr & MI = * MIT ; if ( MI . isDebugValue ( ) || MI . isIndirectDebugValue ( ) ) return MachineOutlinerInstrType :: Invisible ; if ( MI . isKill ( ) ) return MachineOutlinerInstrType :: Invisible ; if ( isTailCall ( MI ) ) return MachineOutlinerInstrType :: Legal ; if ( MI . isTerminator ( ) || MI . isReturn ( ) ) { if ( MI . getParent ( ) -> succ_empty ( ) ) return MachineOutlinerInstrType :: Legal ; return MachineOutlinerInstrType :: Illegal ; } if ( MI . modifiesRegister ( X86 :: RSP , & RI ) || MI . readsRegister ( X86 :: RSP , & RI ) || MI . getDesc ( ) . hasImplicitUseOfPhysReg ( X86 :: RSP ) || MI . getDesc ( ) . hasImplicitDefOfPhysReg ( X86 :: RSP ) ) return MachineOutlinerInstrType :: Illegal ; if ( MI . readsRegister ( X86 :: RIP , & RI ) || MI . getDesc ( ) . hasImplicitUseOfPhysReg ( X86 :: RIP ) || MI . getDesc ( ) . hasImplicitDefOfPhysReg ( X86 :: RIP ) ) return MachineOutlinerInstrType :: Illegal ; if ( MI . isPosition ( ) ) return MachineOutlinerInstrType :: Illegal ; for ( const MachineOperand & MOP : MI . operands ( ) ) if ( MOP . isCPI ( ) || MOP . isJTI ( ) || MOP . isCFIIndex ( ) || MOP . isFI ( ) || MOP . isTargetIndex ( ) ) return MachineOutlinerInstrType :: Illegal ; return MachineOutlinerInstrType :: Legal ; } </s>

Returns how or if MIT should be outlined .


<s> MVT getScalarShiftAmountTy ( EVT LHSTy ) const override { return MVT :: i8 ; } </s>

Return the type to use for a scalar shift opcode , given the shifted amount type .


<s> Value * X86TargetLowering :: getIRStackGuard ( IRBuilder < > & IRB ) const { if ( hasStackGuardSlotTLS ( Subtarget . getTargetTriple ( ) ) ) { if ( Subtarget . isTargetFuchsia ( ) ) { return SegmentOffset ( IRB , 0x10 , getAddressSpace ( ) ) ; } else { unsigned AddressSpace = getAddressSpace ( ) ; unsigned Offset = getTargetMachine ( ) . Options . StackProtectorGuardOffset ; if ( Offset == ( unsigned ) - 1 ) Offset = ( Subtarget . is64Bit ( ) ) ? 0x28 : 0x14 ; auto GuardReg = getTargetMachine ( ) . Options . StackProtectorGuardReg ; if ( GuardReg == "fs" ) AddressSpace = X86AS :: FS ; else if ( GuardReg == "gs" ) AddressSpace = X86AS :: GS ; return SegmentOffset ( IRB , Offset , AddressSpace ) ; } } return TargetLowering :: getIRStackGuard ( IRB ) ; } </s>

If the target has a standard location for the stack protector cookie , returns the address of that location .


<s>
SDNode
*
Cpu0DAGToDAGISel
::
Select
(
SDNode
*
Node
)
{
unsigned
Opcode
=
Node
->
getOpcode
(
)
;
DebugLoc
dl
=
Node
->
getDebugLoc
(
)
;
DEBUG
(
errs
(
)
<<
"Selecting: "
;
Node
->
dump
(
CurDAG
)
;
errs
(
)
<<
"\n"
)
;
if
(
Node
->
isMachineOpcode
(
)
)
{
DEBUG
(
errs
(
)
<<
"== "
;
Node
->
dump
(
CurDAG
)
;
errs
(
)
<<
"\n"
)
;
return
;
}
EVT
NodeTy
=
Node
->
getValueType
(
0
)
;
unsigned
MultOpc
;
switch
(
Opcode
)
{
default
:
break
;
case
ISD
::
MULHS
:
case
ISD
::
MULHU
:
{
MultOpc
=
(
Opcode
==
ISD
::
MULHU
Cpu0
::
MULTu
:
Cpu0
::
MULT
)
;
return
SelectMULT
(
Node
,
MultOpc
,
dl
,
NodeTy
,
false
,
true
)
.
second
;
}
case
ISD
::
GLOBAL_OFFSET_TABLE
:
return
getGlobalBaseReg
(
)
;
case
ISD
::
Constant
:
{
const
ConstantSDNode
*
CN
=
dyn_cast
<
ConstantSDNode
>
(
Node
)
;
unsigned
Size
=
CN
->
getValueSizeInBits
(
0
)
;
if
(
Size
==
32
)
break
;
}
}
SDNode
*
ResNode
=
SelectCode
(
Node
)
;
DEBUG
(
errs
(
)
<<
"=> "
)
;
if
(
ResNode
==
||
ResNode
==
Node
)
DEBUG
(
Node
->
dump
(
CurDAG
)
)
;
else
DEBUG
(
ResNode
->
dump
(
CurDAG
)
)
;
DEBUG
(
errs
(
)
<<
"\n"
)
;
return
ResNode
;
}
</s>

Main hook for targets to transform nodes into machine nodes .


<s> bool SystemZTargetLowering :: mayBeEmittedAsTailCall ( const CallInst * CI ) const { return CI -> isTailCall ( ) ; } </s>

Return true if the target may be able emit the call instruction as a tail call .


<s> static rtx_code_label * add_constant ( rtx x , machine_mode mode , rtx last_value ) { int i ; rtx_code_label * lab , * new_rtx ; label_ref_list_t ref , newref ; for ( i = 0 ; i < pool_size ; i ++ ) { if ( x -> code == pool_vector [ i ] . value -> code && mode == pool_vector [ i ] . mode ) { if ( x -> code == CODE_LABEL ) { if ( XINT ( x , 3 ) != XINT ( pool_vector [ i ] . value , 3 ) ) continue ; } if ( rtx_equal_p ( x , pool_vector [ i ] . value ) ) { lab = new_rtx = 0 ; if ( ! last_value || ! i || ! rtx_equal_p ( last_value , pool_vector [ i - 1 ] . value ) ) { new_rtx = gen_label_rtx ( ) ; LABEL_REFS ( new_rtx ) = pool_vector [ i ] . label ; pool_vector [ i ] . label = lab = new_rtx ; } if ( lab && pool_window_label ) { newref = ( label_ref_list_t ) pool_alloc ( label_ref_list_pool ) ; newref -> label = pool_window_label ; ref = pool_vector [ pool_window_last ] . wend ; newref -> next = ref ; pool_vector [ pool_window_last ] . wend = newref ; } if ( new_rtx ) pool_window_label = new_rtx ; pool_window_last = i ; return lab ; } } } pool_vector [ pool_size ] . value = x ; if ( last_value && rtx_equal_p ( last_value , pool_vector [ pool_size - 1 ] . value ) ) { lab = 0 ; pool_vector [ pool_size - 1 ] . part_of_sequence_p = true ; } else lab = gen_label_rtx ( ) ; pool_vector [ pool_size ] . mode = mode ; pool_vector [ pool_size ] . label = lab ; pool_vector [ pool_size ] . wend = NULL ; pool_vector [ pool_size ] . part_of_sequence_p = ( lab == 0 ) ; if ( lab && pool_window_label ) { newref = ( label_ref_list_t ) pool_alloc ( label_ref_list_pool ) ; newref -> label = pool_window_label ; ref = pool_vector [ pool_window_last ] . wend ; newref -> next = ref ; pool_vector [ pool_window_last ] . wend = newref ; } if ( lab ) pool_window_label = lab ; pool_window_last = pool_size ; pool_size ++ ; return lab ; } </s>

Add a constant to the pool and return its label .


<s> bool immed_offset_p ( rtx mem_rtx ) { gcc_assert ( MEM_P ( mem_rtx ) ) ; rtx addr_rtx = XEXP ( mem_rtx , 0 ) ; if ( REG_P ( addr_rtx ) ) return true ; if ( GET_CODE ( addr_rtx ) == PLUS && GET_CODE ( XEXP ( addr_rtx , 1 ) ) == CONST_INT ) return true ; return false ; } </s>

Check if the address of MEM_RTX consists of a base register and an immediate offset .


<s> bool AAPAsmPrinter :: PrintAsmMemoryOperand ( const MachineInstr * MI , unsigned OpNo , unsigned AsmVariant , const char * ExtraCode , raw_ostream & O ) { printMemOffOperand ( MI , OpNo , O ) ; return false ; } </s>

Print the specified operand of MI , an INLINEASM instruction , using the specified assembler variant as an address .


<s> int frv_trampoline_size ( void ) { if ( TARGET_FDPIC ) return 8 + 6 * 4 ; return 5 * 4 ; } </s>

A C expression for the size in bytes of the trampoline , as an integer . The template is : setlo # 0 , < jmp_reg > setlo # 0 , < static_chain > sethi # 0 , < jmp_reg > sethi # 0 , < static_chain > jmpl @ ( gr0 , < jmp_reg > )


<s>
bool
SystemZXPLINKFrameLowering
::
spillCalleeSavedRegisters
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
MBBI
,
ArrayRef
<
CalleeSavedInfo
>
CSI
,
const
TargetRegisterInfo
*
TRI
)
const
{
if
(
CSI
.
empty
(
)
)
return
true
;
MachineFunction
&
MF
=
*
MBB
.
getParent
(
)
;
SystemZMachineFunctionInfo
*
ZFI
=
MF
.
getInfo
<
SystemZMachineFunctionInfo
>
(
)
;
const
SystemZSubtarget
&
Subtarget
=
MF
.
getSubtarget
<
SystemZSubtarget
>
(
)
;
const
TargetInstrInfo
*
TII
=
Subtarget
.
getInstrInfo
(
)
;
auto
&
Regs
=
Subtarget
.
getSpecialRegisters
<
SystemZXPLINK64Registers
>
(
)
;
SystemZ
::
GPRRegs
SpillGPRs
=
ZFI
->
getSpillGPRRegs
(
)
;
DebugLoc
DL
;
if
(
SpillGPRs
.
LowGPR
)
{
assert
(
SpillGPRs
.
LowGPR
!=
SpillGPRs
.
HighGPR
&&
"Should be saving multiple registers"
)
;
MachineInstrBuilder
MIB
=
BuildMI
(
MBB
,
MBBI
,
DL
,
TII
->
get
(
SystemZ
::
STMG
)
)
;
addSavedGPR
(
MBB
,
MIB
,
SpillGPRs
.
LowGPR
,
false
)
;
addSavedGPR
(
MBB
,
MIB
,
SpillGPRs
.
HighGPR
,
false
)
;
MIB
.
addReg
(
Regs
.
getStackPointerRegister
(
)
)
;
MIB
.
addImm
(
SpillGPRs
.
GPROffset
)
;
auto
&
GRRegClass
=
SystemZ
::
GR64BitRegClass
;
for
(
const
CalleeSavedInfo
&
I
:
CSI
)
{
unsigned
Reg
=
I
.
getReg
(
)
;
if
(
GRRegClass
.
contains
(
Reg
)
)
addSavedGPR
(
MBB
,
MIB
,
Reg
,
true
)
;
}
}
for
(
const
CalleeSavedInfo
&
I
:
CSI
)
{
unsigned
Reg
=
I
.
getReg
(
)
;
if
(
SystemZ
::
FP64BitRegClass
.
contains
(
Reg
)
)
{
MBB
.
addLiveIn
(
Reg
)
;
TII
->
storeRegToStackSlot
(
MBB
,
MBBI
,
Reg
,
true
,
I
.
getFrameIdx
(
)
,
&
SystemZ
::
FP64BitRegClass
,
TRI
)
;
}
if
(
SystemZ
::
VR128BitRegClass
.
contains
(
Reg
)
)
{
MBB
.
addLiveIn
(
Reg
)
;
TII
->
storeRegToStackSlot
(
MBB
,
MBBI
,
Reg
,
true
,
I
.
getFrameIdx
(
)
,
&
SystemZ
::
VR128BitRegClass
,
TRI
)
;
}
}
return
true
;
}
</s>

spillCalleeSavedRegisters - Issues instruction ( s ) to spill all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of store instructions via storeRegToStackSlot ( ) .

SystemZ
SystemZ
SystemZ
SystemZ
SystemZ
SystemZ
SystemZ
SystemZ::GPRRegs
"Should be saving multiple registers"
SystemZ::STMG
SystemZ::GR64BitRegClass
SystemZ::FP64BitRegClass
SystemZ::FP64BitRegClass
SystemZ::VR128BitRegClass
SystemZ::VR128BitRegClass


<s> bool TOYInstrInfo :: expandPostRAPseudo ( MachineInstr & MI ) const { return true ; } </s>

This function is called for all pseudo instructions that remain after register allocation .


<s> static int compute_total_frame_size ( void ) { int total_size = ( get_frame_size ( ) + tilegx_saved_regs_size ( ) + crtl -> outgoing_args_size + crtl -> args . pretend_args_size ) ; if ( ! tilegx_current_function_is_leaf ( ) || cfun -> calls_alloca ) { total_size += STACK_POINTER_OFFSET ; } return round_frame_size ( total_size ) ; } </s>


<s> bool rl78_hl_b_c_addr_p ( rtx op ) { rtx hl , bc ; if ( GET_CODE ( op ) != PLUS ) return false ; hl = XEXP ( op , 0 ) ; bc = XEXP ( op , 1 ) ; if ( GET_CODE ( hl ) == ZERO_EXTEND ) { rtx tmp = hl ; hl = bc ; bc = tmp ; } if ( GET_CODE ( hl ) != REG ) return false ; if ( GET_CODE ( bc ) != ZERO_EXTEND ) return false ; bc = XEXP ( bc , 0 ) ; if ( GET_CODE ( bc ) != REG ) return false ; if ( REGNO ( hl ) != HL_REG ) return false ; if ( REGNO ( bc ) != B_REG && REGNO ( bc ) != C_REG ) return false ; return true ; } </s>

Used by the Whb constraint . Match addresses that use HL+B or HL+C addressing .


<s> void aarch64_expand_sve_vec_cmp_int ( rtx target , rtx_code code , rtx op0 , rtx op1 ) { machine_mode pred_mode = GET_MODE ( target ) ; machine_mode data_mode = GET_MODE ( op0 ) ; if ( ! aarch64_sve_cmp_operand_p ( code , op1 ) ) op1 = force_reg ( data_mode , op1 ) ; rtx ptrue = force_reg ( pred_mode , CONSTM1_RTX ( pred_mode ) ) ; rtx unspec = aarch64_gen_unspec_cond ( code , pred_mode , ptrue , op0 , op1 ) ; emit_insn ( gen_set_clobber_cc ( target , unspec ) ) ; } </s>

Expand an SVE integer comparison : TARGET = CODE ( OP0 , OP1 ) .


<s> MipsSubtarget & MipsSubtarget :: initializeSubtargetDependencies ( StringRef CPU , StringRef FS , const TargetMachine & TM ) { std :: string CPUName = MIPS_MC :: selectMipsCPU ( TM . getTargetTriple ( ) , CPU ) ; ParseSubtargetFeatures ( CPUName , FS ) ; InstrItins = getInstrItineraryForCPU ( CPUName ) ; if ( InMips16Mode && ! TM . Options . UseSoftFloat ) InMips16HardFloat = true ; return * this ; } </s>

initializeSubtargetDependencies - Initializes using a CPU , a TuneCPU , and feature string so that we can use initializer lists for subtarget initialization .

Mips Mips Mips MIPS_MC::selectMipsCPU Mips Mips


<s> TargetPassConfig * Z80TargetMachine :: createPassConfig ( PassManagerBase & PM ) { return new Z80PassConfig ( * this , PM ) ; } </s>

Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of CodeGen passes .


<s> PreservedAnalyses AMDGPUUseNativeCallsPass :: run ( Function & F , FunctionAnalysisManager & AM ) { if ( UseNative . empty ( ) ) return PreservedAnalyses :: all ( ) ; AMDGPULibCalls Simplifier ; Simplifier . initNativeFuncs ( ) ; bool Changed = false ; for ( auto & BB : F ) { for ( BasicBlock :: iterator I = BB . begin ( ) , E = BB . end ( ) ; I != E ; ) { CallInst * CI = dyn_cast < CallInst > ( I ) ; ++ I ; if ( ! CI ) continue ; Function * Callee = CI -> getCalledFunction ( ) ; if ( Callee == nullptr ) continue ; if ( Simplifier . useNative ( CI ) ) Changed = true ; } } return Changed ? PreservedAnalyses :: none ( ) : PreservedAnalyses :: all ( ) ; } </s>

Run the analysis pass over a function and produce a dominator tree .


"prioritized sinit and sterm functions are not yet supported on AIX"

This method emits llvm.global_ctors or llvm.global_dtors list .


<s> static char * to_host_file_spec ( char * filespec ) { if ( strchr ( filespec , ']' ) || strchr ( filespec , ':' ) ) { return filespec ; } else { strcpy ( filename_buff , filespec ) ; decc$to_vms ( filespec , translate_unix , 1 , 1 ) ; strcpy ( new_host_filespec , filename_buff ) ; return new_host_filespec ; } return filespec ; } </s>

Translate a Unix syntax file specification FILESPEC into VMS syntax . If indicators of VMS syntax found , return input string . Return a pointer to a static buffer .


"For each split Type there should be exactly one VReg."

This hook behaves as the extended lowerReturn function , but for targets that do not support swifterror value promotion .


<s> bool XCoreFTAOElim :: runOnMachineFunction ( MachineFunction & MF ) { const XCoreInstrInfo & TII = * static_cast < const XCoreInstrInfo * > ( MF . getSubtarget ( ) . getInstrInfo ( ) ) ; unsigned StackSize = MF . getFrameInfo ( ) -> getStackSize ( ) ; for ( MachineFunction :: iterator MFI = MF . begin ( ) , E = MF . end ( ) ; MFI != E ; ++ MFI ) { MachineBasicBlock & MBB = * MFI ; for ( MachineBasicBlock :: iterator MBBI = MBB . begin ( ) , EE = MBB . end ( ) ; MBBI != EE ; ++ MBBI ) { if ( MBBI -> getOpcode ( ) == XCore :: FRAME_TO_ARGS_OFFSET ) { MachineInstr * OldInst = MBBI ; unsigned Reg = OldInst -> getOperand ( 0 ) . getReg ( ) ; MBBI = TII . loadImmediate ( MBB , MBBI , Reg , StackSize ) ; OldInst -> eraseFromParent ( ) ; } } } return true ; } </s>

runOnMachineFunction - Emit the function body .

XCore XCore XCore XCore XCore::FRAME_TO_ARGS_OFFSET 0


<s> bool AArch64InstrInfo :: analyzeBranch ( MachineBasicBlock & MBB , MachineBasicBlock * & TBB , MachineBasicBlock * & FBB , SmallVectorImpl < MachineOperand > & Cond , bool AllowModify ) const { MachineBasicBlock :: iterator I = MBB . getLastNonDebugInstr ( ) ; if ( I == MBB . end ( ) ) return false ; if ( ! isUnpredicatedTerminator ( * I ) ) return false ; MachineInstr * LastInst = & * I ; unsigned LastOpc = LastInst -> getOpcode ( ) ; if ( I == MBB . begin ( ) || ! isUnpredicatedTerminator ( * -- I ) ) { if ( isUncondBranchOpcode ( LastOpc ) ) { TBB = LastInst -> getOperand ( 0 ) . getMBB ( ) ; return false ; } if ( isCondBranchOpcode ( LastOpc ) ) { parseCondBranch ( LastInst , TBB , Cond ) ; return false ; } return true ; } MachineInstr * SecondLastInst = & * I ; unsigned SecondLastOpc = SecondLastInst -> getOpcode ( ) ; if ( AllowModify && isUncondBranchOpcode ( LastOpc ) ) { while ( isUncondBranchOpcode ( SecondLastOpc ) ) { LastInst -> eraseFromParent ( ) ; LastInst = SecondLastInst ; LastOpc = LastInst -> getOpcode ( ) ; if ( I == MBB . begin ( ) || ! isUnpredicatedTerminator ( * -- I ) ) { TBB = LastInst -> getOperand ( 0 ) . getMBB ( ) ; return false ; } else { SecondLastInst = & * I ; SecondLastOpc = SecondLastInst -> getOpcode ( ) ; } } } if ( SecondLastInst && I != MBB . begin ( ) && isUnpredicatedTerminator ( * -- I ) ) return true ; if ( isCondBranchOpcode ( SecondLastOpc ) && isUncondBranchOpcode ( LastOpc ) ) { parseCondBranch ( SecondLastInst , TBB , Cond ) ; FBB = LastInst -> getOperand ( 0 ) . getMBB ( ) ; return false ; } if ( isUncondBranchOpcode ( SecondLastOpc ) && isUncondBranchOpcode ( LastOpc ) ) { TBB = SecondLastInst -> getOperand ( 0 ) . getMBB ( ) ; I = LastInst ; if ( AllowModify ) I -> eraseFromParent ( ) ; return false ; } if ( isIndirectBranchOpcode ( SecondLastOpc ) && isUncondBranchOpcode ( LastOpc ) ) { I = LastInst ; if ( AllowModify ) I -> eraseFromParent ( ) ; return true ; } return true ; } </s>

analyzeBranch - Analyze the branching code at the end of MBB , returning true if it can not be understood ( e.g .


"This resolveFrameIndex does not support Thumb1!"

"Instr doesn't have FrameIndex operand!"

Resolve a frame index operand of an instruction to reference the indicated base register plus offset instead .


<s> bool AMDGPUArgumentUsageInfo :: doFinalization ( Module & M ) { ArgInfoMap . clear ( ) ; return false ; } </s>

doFinalization - Virtual method overriden by subclasses to do any necessary clean up after all passes have run .


<s> bool arm_pad_reg_upward ( machine_mode mode , tree type , int first ATTRIBUTE_UNUSED ) { if ( TARGET_AAPCS_BASED && BYTES_BIG_ENDIAN ) { if ( type ) { if ( ( AGGREGATE_TYPE_P ( type ) || TREE_CODE ( type ) == COMPLEX_TYPE || FIXED_POINT_TYPE_P ( type ) ) && int_size_in_bytes ( type ) <= 4 ) return true ; } else { if ( ( COMPLEX_MODE_P ( mode ) || ALL_FIXED_POINT_MODE_P ( mode ) ) && GET_MODE_SIZE ( mode ) <= 4 ) return true ; } } return ! BYTES_BIG_ENDIAN ; } </s>

Similarly , for use by BLOCK_REG_PADDING ( MODE , TYPE , FIRST ) . For non-AAPCS , return ! BYTES_BIG_ENDIAN if the least significant byte of the register has useful data , and return the opposite if the most significant byte does . For AAPCS , small aggregates and small complex types are always padded upwards .


<s> unsigned HexagonRegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { const TargetFrameLowering * TFI = MF . getSubtarget ( ) . getFrameLowering ( ) ; if ( TFI -> hasFP ( MF ) ) { return Hexagon :: R30 ; } return Hexagon :: R29 ; } </s>


<s> static tree ix86_vectorize_builtin_scatter ( const_tree vectype , const_tree index_type , int scale ) { bool si ; enum ix86_builtins code ; if ( ! TARGET_AVX512F ) return NULL_TREE ; if ( known_eq ( TYPE_VECTOR_SUBPARTS ( vectype ) , 2u ) ? ! TARGET_USE_SCATTER_2PARTS : ( known_eq ( TYPE_VECTOR_SUBPARTS ( vectype ) , 4u ) ? ! TARGET_USE_SCATTER_4PARTS : ! TARGET_USE_SCATTER ) ) return NULL_TREE ; if ( ( TREE_CODE ( index_type ) != INTEGER_TYPE && ! POINTER_TYPE_P ( index_type ) ) || ( TYPE_MODE ( index_type ) != SImode && TYPE_MODE ( index_type ) != DImode ) ) return NULL_TREE ; if ( TYPE_PRECISION ( index_type ) > POINTER_SIZE ) return NULL_TREE ; if ( TYPE_PRECISION ( index_type ) < POINTER_SIZE && TYPE_UNSIGNED ( index_type ) ) return NULL_TREE ; if ( scale <= 0 || scale > 8 || ( scale & ( scale - 1 ) ) != 0 ) return NULL_TREE ; si = TYPE_MODE ( index_type ) == SImode ; switch ( TYPE_MODE ( vectype ) ) { case E_V8DFmode : code = si ? IX86_BUILTIN_SCATTERALTSIV8DF : IX86_BUILTIN_SCATTERDIV8DF ; break ; case E_V8DImode : code = si ? IX86_BUILTIN_SCATTERALTSIV8DI : IX86_BUILTIN_SCATTERDIV8DI ; break ; case E_V16SFmode : code = si ? IX86_BUILTIN_SCATTERSIV16SF : IX86_BUILTIN_SCATTERALTDIV16SF ; break ; case E_V16SImode : code = si ? IX86_BUILTIN_SCATTERSIV16SI : IX86_BUILTIN_SCATTERALTDIV16SI ; break ; case E_V4DFmode : if ( TARGET_AVX512VL ) code = si ? IX86_BUILTIN_SCATTERALTSIV4DF : IX86_BUILTIN_SCATTERDIV4DF ; else return NULL_TREE ; break ; case E_V4DImode : if ( TARGET_AVX512VL ) code = si ? IX86_BUILTIN_SCATTERALTSIV4DI : IX86_BUILTIN_SCATTERDIV4DI ; else return NULL_TREE ; break ; case E_V8SFmode : if ( TARGET_AVX512VL ) code = si ? IX86_BUILTIN_SCATTERSIV8SF : IX86_BUILTIN_SCATTERALTDIV8SF ; else return NULL_TREE ; break ; case E_V8SImode : if ( TARGET_AVX512VL ) code = si ? IX86_BUILTIN_SCATTERSIV8SI : IX86_BUILTIN_SCATTERALTDIV8SI ; else return NULL_TREE ; break ; case E_V2DFmode : if ( TARGET_AVX512VL ) code = si ? IX86_BUILTIN_SCATTERALTSIV2DF : IX86_BUILTIN_SCATTERDIV2DF ; else return NULL_TREE ; break ; case E_V2DImode : if ( TARGET_AVX512VL ) code = si ? IX86_BUILTIN_SCATTERALTSIV2DI : IX86_BUILTIN_SCATTERDIV2DI ; else return NULL_TREE ; break ; case E_V4SFmode : if ( TARGET_AVX512VL ) code = si ? IX86_BUILTIN_SCATTERSIV4SF : IX86_BUILTIN_SCATTERALTDIV4SF ; else return NULL_TREE ; break ; case E_V4SImode : if ( TARGET_AVX512VL ) code = si ? IX86_BUILTIN_SCATTERSIV4SI : IX86_BUILTIN_SCATTERALTDIV4SI ; else return NULL_TREE ; break ; default : return NULL_TREE ; } return get_ix86_builtin ( code ) ; } </s>

Returns a decl of a function that implements scatter store with register type VECTYPE and index type INDEX_TYPE and SCALE . Return NULL_TREE if it is not available .


<s> tree gimple_folder :: convert_pred ( gimple_seq & stmts , tree vectype , unsigned int argno ) { tree pred = gimple_call_arg ( call , argno ) ; if ( known_eq ( TYPE_VECTOR_SUBPARTS ( TREE_TYPE ( pred ) ) , TYPE_VECTOR_SUBPARTS ( vectype ) ) ) return pred ; return gimple_build ( & stmts , VIEW_CONVERT_EXPR , truth_type_for ( vectype ) , pred ) ; } </s>

Convert predicate argument ARGNO so that it has the type appropriate for an operation on VECTYPE . Add any new statements to STMTS .


<s> static rtx legitimize_tls_address ( rtx addr ) { rtx ret , tmp , t1 , t2 , tp ; rtx_insn * insn ; if ( GET_CODE ( addr ) != SYMBOL_REF ) return addr ; switch ( SYMBOL_REF_TLS_MODEL ( addr ) ) { case TLS_MODEL_GLOBAL_DYNAMIC : tmp = gen_reg_rtx ( Pmode ) ; if ( flag_pic ) emit_insn ( gen_tgd_load_pic ( tmp , addr ) ) ; else emit_insn ( gen_tgd_load ( tmp , addr ) ) ; ret = hppa_tls_call ( tmp ) ; break ; case TLS_MODEL_LOCAL_DYNAMIC : ret = gen_reg_rtx ( Pmode ) ; tmp = gen_reg_rtx ( Pmode ) ; start_sequence ( ) ; if ( flag_pic ) emit_insn ( gen_tld_load_pic ( tmp , addr ) ) ; else emit_insn ( gen_tld_load ( tmp , addr ) ) ; t1 = hppa_tls_call ( tmp ) ; insn = get_insns ( ) ; end_sequence ( ) ; t2 = gen_reg_rtx ( Pmode ) ; emit_libcall_block ( insn , t2 , t1 , gen_rtx_UNSPEC ( Pmode , gen_rtvec ( 1 , const0_rtx ) , UNSPEC_TLSLDBASE ) ) ; emit_insn ( gen_tld_offset_load ( ret , addr , t2 ) ) ; break ; case TLS_MODEL_INITIAL_EXEC : tp = gen_reg_rtx ( Pmode ) ; tmp = gen_reg_rtx ( Pmode ) ; ret = gen_reg_rtx ( Pmode ) ; emit_insn ( gen_tp_load ( tp ) ) ; if ( flag_pic ) emit_insn ( gen_tie_load_pic ( tmp , addr ) ) ; else emit_insn ( gen_tie_load ( tmp , addr ) ) ; emit_move_insn ( ret , gen_rtx_PLUS ( Pmode , tp , tmp ) ) ; break ; case TLS_MODEL_LOCAL_EXEC : tp = gen_reg_rtx ( Pmode ) ; ret = gen_reg_rtx ( Pmode ) ; emit_insn ( gen_tp_load ( tp ) ) ; emit_insn ( gen_tle_load ( ret , addr , tp ) ) ; break ; default : gcc_unreachable ( ) ; } return ret ; } </s>

ADDR contains a thread-local SYMBOL_REF . Generate code to compute this ( thread-local ) address .


<s>
SDValue
GBZ80TargetLowering
::
LowerOperation
(
SDValue
Op
,
SelectionDAG
&
DAG
)
const
{
switch
(
Op
.
getOpcode
(
)
)
{
case
ISD
::
ZERO_EXTEND
:
return
LowerZExt
(
Op
,
DAG
)
;
case
ISD
::
SIGN_EXTEND
:
return
LowerSExt
(
Op
,
DAG
)
;
case
ISD
::
SUB
:
case
ISD
::
SUBC
:
return
LowerSUB
(
Op
,
DAG
)
;
case
ISD
::
SRL
:
case
ISD
::
SHL
:
case
ISD
::
SRA
:
case
ISD
::
ROTL
:
case
ISD
::
ROTR
:
return
LowerShifts
(
Op
,
DAG
)
;
case
ISD
::
AND
:
case
ISD
::
OR
:
case
ISD
::
XOR
:
return
LowerBinaryOp
(
Op
,
DAG
)
;
case
ISD
::
SELECT_CC
:
return
LowerSelectCC
(
Op
,
DAG
)
;
case
ISD
::
BR_CC
:
return
LowerBrCC
(
Op
,
DAG
)
;
case
ISD
::
GlobalAddress
:
return
LowerGlobalAddress
(
Op
,
DAG
)
;
case
ISD
::
STORE
:
return
LowerStore
(
Op
,
DAG
)
;
case
ISD
::
LOAD
:
return
LowerLoad
(
Op
,
DAG
)
;
default
:
llvm_unreachable
(
"unimplemented operation"
)
;
}
}
</s>

LowerOperation - Provide custom lowering hooks for some operations .

GBZ80
GB
ISD::ZERO_EXTEND
ISD::SIGN_EXTEND
ISD::SUB
ISD::SUBC
ISD::SRL
ISD::SHL
ISD::SRA
ISD::ROTL
ISD::ROTR
ISD::AND
ISD::OR
ISD::XOR
ISD::SELECT_CC
ISD::BR_CC
ISD::GlobalAddress
ISD::STORE
ISD::LOAD
"unimplemented operation"


<s> void Stack :: addDef ( unsigned Reg , const DILocalVariable * DbgVar ) { Data . push_front ( StackVreg ( Reg , DbgVar ) ) ; } </s>

Add a virtual register definition operand .


<s> static bool csky_can_use_pushpop ( unsigned int mask ) { int i ; int end_reg ; if ( ! TARGET_PUSHPOP ) return false ; if ( mask == 0 ) return false ; if ( mask & 0xeffc700f ) return false ; for ( end_reg = 0 , i = 11 ; i >= 4 ; i -- ) { if ( ! end_reg && ( mask & ( 1 << i ) ) ) end_reg = i ; if ( end_reg && ! ( mask & ( 1 << i ) ) ) return false ; } for ( end_reg = 0 , i = 17 ; i >= 16 ; i -- ) { if ( ! end_reg && ( mask & ( 1 << i ) ) ) end_reg = i ; if ( end_reg && ! ( mask & ( 1 << i ) ) ) return false ; } return true ; } </s>

Return true if push/pop can be used to save/restore all the registers indicated by MASK . We currently do n't attempt to handle situations where some of the registers could be handled by push/pop and others saved and restored individually .


<s> MCFragment * findAssociatedFragment ( ) const override { return getSubExpr ( ) -> findAssociatedFragment ( ) ; } </s>

Find the `` associated section '' for this expression , which is currently defined as the absolute section for constants , or otherwise the section associated with the first defined symbol in the expression .


<s> bool OR1KPassConfig :: addInstSelector ( ) { addPass ( createOR1KISelDag ( getTM < OR1KTargetMachine > ( ) ) ) ; addPass ( createOR1KGlobalBaseRegPass ( ) ) ; return false ; } </s>

addInstSelector - This method should install an instruction selector pass , which converts from LLVM code to machine instructions .


<s> size_t AArch64LongBranchStub :: size ( ) const { return m_Size ; } </s>

The number of name/type pairs is returned .


<s> bool runOnMachineFunction ( MachineFunction & MF ) { TII = static_cast < const R600InstrInfo * > ( MF . getTarget ( ) . getInstrInfo ( ) ) ; TRI = & TII -> getRegisterInfo ( ) ; DEBUG ( MF . dump ( ) ; ) ; OrderedBlks . clear ( ) ; FuncRep = & MF ; MLI = & getAnalysis < MachineLoopInfo > ( ) ; DEBUG ( dbgs ( ) << "LoopInfo:\n" ; PrintLoopinfo ( * MLI ) ; ) ; MDT = & getAnalysis < MachineDominatorTree > ( ) ; DEBUG ( MDT -> print ( dbgs ( ) , ( const llvm :: Module * ) 0 ) ; ) ; PDT = & getAnalysis < MachinePostDominatorTree > ( ) ; DEBUG ( PDT -> print ( dbgs ( ) ) ; ) ; prepare ( ) ; run ( ) ; DEBUG ( MF . dump ( ) ; ) ; return true ; } </s>


<s>
SDValue
MSP430TargetLowering
::
LowerFormalArguments
(
SDValue
Chain
,
CallingConv
::
ID
CallConv
,
bool
isVarArg
,
const
SmallVectorImpl
<
ISD
::
InputArg
>
&
Ins
,
SDLoc
dl
,
SelectionDAG
&
DAG
,
SmallVectorImpl
<
SDValue
>
&
InVals
)
const
{
switch
(
CallConv
)
{
default
:
llvm_unreachable
(
"Unsupported calling convention"
)
;
case
CallingConv
::
C
:
case
CallingConv
::
Fast
:
return
LowerCCCArguments
(
Chain
,
CallConv
,
isVarArg
,
Ins
,
dl
,
DAG
,
InVals
)
;
case
CallingConv
::
MSP430_INTR
:
if
(
Ins
.
empty
(
)
)
return
Chain
;
report_fatal_error
(
"ISRs cannot have arguments"
)
;
}
}
</s>

This hook must be implemented to lower the incoming ( formal ) arguments , described by the Ins array , into the specified DAG .


<s> bool lowerOperand ( const MachineOperand & MO , MCOperand & MCOp ) const { return MCInstLowering . lowerOperand ( MO , MCOp ) ; } </s>

Wrapper for MCInstLowering.lowerOperand ( ) for the tblgen'erated pseudo lowering .


<s> bool PPCInstrInfo :: isUnpredicatedTerminator ( const MachineInstr & MI ) const { if ( ! MI . isTerminator ( ) ) return false ; if ( MI . isBranch ( ) && ! MI . isBarrier ( ) ) return true ; return ! isPredicated ( MI ) ; } </s>

Returns true if the instruction is a terminator instruction that has not been predicated .


<s> bool MipsInstrInfo :: SafeInForbiddenSlot ( const MachineInstr & MI ) const { if ( MI . isInlineAsm ( ) ) return false ; return ( MI . getDesc ( ) . TSFlags & MipsII :: IsCTI ) == 0 ; } </s>

Predicate to determine if an instruction can go in a forbidden slot .


<s> StringRef TriCoreCallingConvHook :: getFunctionName ( uint32_t pos ) { return regRecord [ pos ] . fName ; } </s>


<s> const MCFixup * RISCVMCExpr :: getPCRelHiFixup ( ) const { MCValue AUIPCLoc ; if ( ! getSubExpr ( ) -> evaluateAsRelocatable ( AUIPCLoc , nullptr , nullptr ) ) return nullptr ; const MCSymbolRefExpr * AUIPCSRE = AUIPCLoc . getSymA ( ) ; if ( ! AUIPCSRE ) return nullptr ; const auto * DF = dyn_cast_or_null < MCDataFragment > ( AUIPCSRE -> findAssociatedFragment ( ) ) ; if ( ! DF ) return nullptr ; const MCSymbol * AUIPCSymbol = & AUIPCSRE -> getSymbol ( ) ; for ( const MCFixup & F : DF -> getFixups ( ) ) { if ( F . getOffset ( ) != AUIPCSymbol -> getOffset ( ) ) continue ; switch ( ( unsigned ) F . getKind ( ) ) { default : continue ; case RISCV :: fixup_riscv_got_hi20 : case RISCV :: fixup_riscv_pcrel_hi20 : return & F ; } } return nullptr ; } </s>

Get the corresponding PC-relative HI fixup that a VK_RISCV_PCREL_LO points to , and optionally the fragment containing it .


<s> bool ARMBaseTargetMachine :: addPreRegAlloc ( PassManagerBase & PM , CodeGenOpt :: Level OptLevel ) { if ( OptLevel != CodeGenOpt :: None && ! Subtarget . isThumb1Only ( ) ) PM . add ( createARMLoadStoreOptimizationPass ( true ) ) ; if ( OptLevel != CodeGenOpt :: None && Subtarget . isCortexA9 ( ) ) PM . add ( createMLxExpansionPass ( ) ) ; return true ; } </s>

This method may be implemented by targets that want to run passes immediately before register allocation .


"Unexpected base pointer for inline asm memory operand."

"Unexpected offset for inline asm memory operand."

Print the specified operand of MI , an INLINEASM instruction , using the specified assembler variant as an address .


<s> bool n13_alu_e1_insn_dep_reg_p ( rtx_insn * alu_e1_insn , rtx def_reg ) { rtx unspec_rtx , operand_ra , operand_rb ; rtx src_rtx , dst_rtx ; switch ( INSN_CODE ( alu_e1_insn ) ) { case CODE_FOR_unspec_bsp : case CODE_FOR_unspec_bse : unspec_rtx = SET_SRC ( parallel_element ( alu_e1_insn , 0 ) ) ; gcc_assert ( GET_CODE ( unspec_rtx ) == UNSPEC ) ; operand_ra = XVECEXP ( unspec_rtx , 0 , 0 ) ; operand_rb = XVECEXP ( unspec_rtx , 0 , 1 ) ; if ( rtx_equal_p ( def_reg , operand_ra ) || rtx_equal_p ( def_reg , operand_rb ) ) return true ; return false ; case CODE_FOR_move_di : case CODE_FOR_move_df : src_rtx = SET_SRC ( PATTERN ( alu_e1_insn ) ) ; dst_rtx = SET_DEST ( PATTERN ( alu_e1_insn ) ) ; if ( REG_P ( dst_rtx ) && REG_P ( src_rtx ) && rtx_equal_p ( src_rtx , def_reg ) ) return true ; return false ; default : return false ; } } </s>

Check dependencies from any stages to ALU_E1 ( E1 ) . This is a helper function of n13_consumed_by_e1_dep_p ( ) .


<s> SDValue HexagonTargetLowering :: getInt ( unsigned IntId , MVT ResTy , ArrayRef < SDValue > Ops , const SDLoc & dl , SelectionDAG & DAG ) const { SmallVector < SDValue , 4 > IntOps ; IntOps . push_back ( DAG . getConstant ( IntId , dl , MVT :: i32 ) ) ; for ( const SDValue & Op : Ops ) IntOps . push_back ( Op ) ; return DAG . getNode ( ISD :: INTRINSIC_WO_CHAIN , dl , ResTy , IntOps ) ; } </s>


<s> rtx gen_easy_altivec_constant ( rtx op ) { machine_mode mode = GET_MODE ( op ) ; int nunits = GET_MODE_NUNITS ( mode ) ; rtx val = CONST_VECTOR_ELT ( op , BYTES_BIG_ENDIAN ? nunits - 1 : 0 ) ; unsigned step = nunits / 4 ; unsigned copies = 1 ; if ( vspltis_constant ( op , step , copies ) ) return gen_rtx_VEC_DUPLICATE ( V4SImode , gen_lowpart ( SImode , val ) ) ; if ( step == 1 ) copies <<= 1 ; else step >>= 1 ; if ( vspltis_constant ( op , step , copies ) ) return gen_rtx_VEC_DUPLICATE ( V8HImode , gen_lowpart ( HImode , val ) ) ; if ( step == 1 ) copies <<= 1 ; else step >>= 1 ; if ( vspltis_constant ( op , step , copies ) ) return gen_rtx_VEC_DUPLICATE ( V16QImode , gen_lowpart ( QImode , val ) ) ; gcc_unreachable ( ) ; } </s>

Generate a VEC_DUPLICATE representing a vspltis [ bhw ] instruction whose result is OP . Abort if it is not possible .


<s>
void
WebAssemblyInstPrinter
::
printInst
(
const
MCInst
*
MI
,
raw_ostream
&
OS
,
StringRef
Annot
,
const
MCSubtargetInfo
&
)
{
printInstruction
(
MI
,
OS
)
;
const
MCInstrDesc
&
Desc
=
MII
.
get
(
MI
->
getOpcode
(
)
)
;
if
(
Desc
.
isVariadic
(
)
)
for
(
auto
i
=
Desc
.
getNumOperands
(
)
,
e
=
MI
->
getNumOperands
(
)
;
i
<
e
;
++
i
)
{
if
(
i
!=
0
&&
(
MI
->
getOpcode
(
)
!=
WebAssembly
::
CALL_INDIRECT_VOID
||
i
!=
Desc
.
getNumOperands
(
)
)
)
OS
<<
", "
;
printOperand
(
MI
,
i
,
OS
)
;
}
printAnnotation
(
OS
,
Annot
)
;
if
(
CommentStream
)
{
switch
(
MI
->
getOpcode
(
)
)
{
default
:
break
;
case
WebAssembly
::
LOOP
:
{
printAnnotation
(
OS
,
"label"
+
utostr
(
ControlFlowCounter
)
+
':'
)
;
ControlFlowStack
.
push_back
(
std
::
make_pair
(
ControlFlowCounter
++
,
true
)
)
;
break
;
}
case
WebAssembly
::
BLOCK
:
ControlFlowStack
.
push_back
(
std
::
make_pair
(
ControlFlowCounter
++
,
false
)
)
;
break
;
case
WebAssembly
::
END_LOOP
:
if
(
!
ControlFlowStack
.
empty
(
)
)
ControlFlowStack
.
pop_back
(
)
;
break
;
case
WebAssembly
::
END_BLOCK
:
if
(
!
ControlFlowStack
.
empty
(
)
)
printAnnotation
(
OS
,
"label"
+
utostr
(
ControlFlowStack
.
pop_back_val
(
)
.
first
)
+
':'
)
;
break
;
}
unsigned
NumFixedOperands
=
Desc
.
NumOperands
;
SmallSet
<
uint64_t
,
8
>
Printed
;
for
(
unsigned
i
=
0
,
e
=
MI
->
getNumOperands
(
)
;
i
<
e
;
++
i
)
{
if
(
!
(
i
<
NumFixedOperands
(
Desc
.
OpInfo
[
i
]
.
OperandType
==
WebAssembly
::
OPERAND_BASIC_BLOCK
)
:
(
Desc
.
TSFlags
&
WebAssemblyII
::
VariableOpImmediateIsLabel
)
)
)
continue
;
uint64_t
Depth
=
MI
->
getOperand
(
i
)
.
getImm
(
)
;
if
(
!
Printed
.
insert
(
Depth
)
.
second
)
continue
;
const
auto
&
Pair
=
ControlFlowStack
.
rbegin
(
)
[
Depth
]
;
printAnnotation
(
OS
,
utostr
(
Depth
)
+
": "
+
(
Pair
.
second
"up"
:
"down"
)
+
" to label"
+
utostr
(
Pair
.
first
)
)
;
}
}
}
</s>

Print the specified MCInst to the specified raw_ostream .


<s> bool arm_gen_setmem ( rtx * operands ) { rtx dstbase = operands [ 0 ] ; unsigned HOST_WIDE_INT length ; unsigned HOST_WIDE_INT value ; unsigned HOST_WIDE_INT align ; if ( ! CONST_INT_P ( operands [ 2 ] ) || ! CONST_INT_P ( operands [ 1 ] ) ) return false ; length = UINTVAL ( operands [ 1 ] ) ; if ( length > 64 ) return false ; value = ( UINTVAL ( operands [ 2 ] ) & 0xFF ) ; align = UINTVAL ( operands [ 3 ] ) ; if ( TARGET_NEON && length >= 8 && current_tune -> string_ops_prefer_neon && arm_block_set_vect ( dstbase , length , value , align ) ) return true ; if ( ! unaligned_access && ( align & 3 ) != 0 ) return arm_block_set_unaligned_non_vect ( dstbase , length , value , align ) ; return arm_block_set_aligned_non_vect ( dstbase , length , value , align ) ; } </s>

Expand string store operation . Firstly we try to do that by using vectorization instructions , then try with ARM unaligned access and double-word store if profitable . OPERANDS [ 0 ] is the destination , OPERANDS [ 1 ] is the number of bytes , operands [ 2 ] is the value to initialize the memory , OPERANDS [ 3 ] is the known alignment of the destination .


<s>
bool
AArch64InstrInfo
::
isGPRCopy
(
const
MachineInstr
&
MI
)
{
switch
(
MI
.
getOpcode
(
)
)
{
default
:
break
;
case
TargetOpcode
::
COPY
:
{
Register
DstReg
=
MI
.
getOperand
(
0
)
.
getReg
(
)
;
return
(
AArch64
::
GPR32RegClass
.
contains
(
DstReg
)
||
AArch64
::
GPR64RegClass
.
contains
(
DstReg
)
)
;
}
case
AArch64
::
ORRXrs
:
if
(
MI
.
getOperand
(
1
)
.
getReg
(
)
==
AArch64
::
XZR
)
{
assert
(
MI
.
getDesc
(
)
.
getNumOperands
(
)
==
4
&&
MI
.
getOperand
(
3
)
.
getImm
(
)
==
0
&&
"invalid ORRrs operands"
)
;
return
true
;
}
break
;
case
AArch64
::
ADDXri
:
if
(
MI
.
getOperand
(
2
)
.
getImm
(
)
==
0
)
{
assert
(
MI
.
getDesc
(
)
.
getNumOperands
(
)
==
4
&&
MI
.
getOperand
(
3
)
.
getImm
(
)
==
0
&&
"invalid ADDXri operands"
)
;
return
true
;
}
break
;
}
return
false
;
}
</s>

Does this instruction rename a GPR without modifying bits ?


<s>
Register
SITargetLowering
::
getRegisterByName
(
const
char
*
RegName
,
LLT
VT
,
const
MachineFunction
&
MF
)
const
{
Register
Reg
=
StringSwitch
<
Register
>
(
RegName
)
.
Case
(
"m0"
,
AMDGPU
::
M0
)
.
Case
(
"exec"
,
AMDGPU
::
EXEC
)
.
Case
(
"exec_lo"
,
AMDGPU
::
EXEC_LO
)
.
Case
(
"exec_hi"
,
AMDGPU
::
EXEC_HI
)
.
Case
(
"flat_scratch"
,
AMDGPU
::
FLAT_SCR
)
.
Case
(
"flat_scratch_lo"
,
AMDGPU
::
FLAT_SCR_LO
)
.
Case
(
"flat_scratch_hi"
,
AMDGPU
::
FLAT_SCR_HI
)
.
Default
(
Register
(
)
)
;
if
(
Reg
==
AMDGPU
::
NoRegister
)
{
report_fatal_error
(
Twine
(
"invalid register name \""
+
StringRef
(
RegName
)
+
"\"."
)
)
;
}
if
(
!
Subtarget
->
hasFlatScrRegister
(
)
&&
Subtarget
->
getRegisterInfo
(
)
->
regsOverlap
(
Reg
,
AMDGPU
::
FLAT_SCR
)
)
{
report_fatal_error
(
Twine
(
"invalid register \""
+
StringRef
(
RegName
)
+
"\" for subtarget."
)
)
;
}
switch
(
Reg
)
{
case
AMDGPU
::
M0
:
case
AMDGPU
::
EXEC_LO
:
case
AMDGPU
::
EXEC_HI
:
case
AMDGPU
::
FLAT_SCR_LO
:
case
AMDGPU
::
FLAT_SCR_HI
:
if
(
VT
.
getSizeInBits
(
)
==
32
)
return
Reg
;
break
;
case
AMDGPU
::
EXEC
:
case
AMDGPU
::
FLAT_SCR
:
if
(
VT
.
getSizeInBits
(
)
==
64
)
return
Reg
;
break
;
default
:
llvm_unreachable
(
"missing register type checking"
)
;
}
report_fatal_error
(
Twine
(
"invalid type for register \""
+
StringRef
(
RegName
)
+
"\"."
)
)
;
}
</s>

Return the register ID of the name passed in .


<s> static const char * ix86_mangle_type ( const_tree type ) { type = TYPE_MAIN_VARIANT ( type ) ; if ( TREE_CODE ( type ) != VOID_TYPE && TREE_CODE ( type ) != BOOLEAN_TYPE && TREE_CODE ( type ) != INTEGER_TYPE && TREE_CODE ( type ) != REAL_TYPE ) return NULL ; switch ( TYPE_MODE ( type ) ) { case E_HFmode : return "DF16_" ; case E_TFmode : return "g" ; case E_XFmode : return "e" ; default : return NULL ; } } </s>

Return the mangling of TYPE if it is an extended fundamental type .


<s> unsigned RISCVInstrInfo :: getInstSizeInBytes ( const MachineInstr & MI ) const { if ( MI . isMetaInstruction ( ) ) return 0 ; unsigned Opcode = MI . getOpcode ( ) ; if ( Opcode == TargetOpcode :: INLINEASM || Opcode == TargetOpcode :: INLINEASM_BR ) { const MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ; const auto & TM = static_cast < const RISCVTargetMachine & > ( MF . getTarget ( ) ) ; return getInlineAsmLength ( MI . getOperand ( 0 ) . getSymbolName ( ) , * TM . getMCAsmInfo ( ) ) ; } if ( MI . getParent ( ) && MI . getParent ( ) -> getParent ( ) ) { const auto MF = MI . getMF ( ) ; const auto & TM = static_cast < const RISCVTargetMachine & > ( MF -> getTarget ( ) ) ; const MCRegisterInfo & MRI = * TM . getMCRegisterInfo ( ) ; const MCSubtargetInfo & STI = * TM . getMCSubtargetInfo ( ) ; const RISCVSubtarget & ST = MF -> getSubtarget < RISCVSubtarget > ( ) ; if ( isCompressibleInst ( MI , & ST , MRI , STI ) ) return 2 ; } return get ( Opcode ) . getSize ( ) ; } </s>

Returns the size in bytes of the specified MachineInstr , or ~0U when this function is not implemented by a target .

RISCV RISCV 0 RISCV 0 RISCV RISCV RISCV 2


<s> bool rs6000_is_valid_2insn_and ( rtx c , machine_mode mode ) { if ( rs6000_is_valid_mask ( c , NULL , NULL , mode ) ) return true ; unsigned HOST_WIDE_INT val = INTVAL ( c ) ; unsigned HOST_WIDE_INT bit1 = val & - val ; unsigned HOST_WIDE_INT bit2 = ( val + bit1 ) & ~ val ; unsigned HOST_WIDE_INT val1 = ( val + bit1 ) & val ; unsigned HOST_WIDE_INT bit3 = val1 & - val1 ; return rs6000_is_valid_and_mask ( GEN_INT ( val + bit3 - bit2 ) , mode ) ; } </s>

Return whether an AND with C ( a CONST_INT ) in mode MODE can be done using two machine instructions .


<s>
char
*
aarch64_output_sve_mov_immediate
(
rtx
const_vector
)
{
static
char
templ
[
40
]
;
struct
simd_immediate_info
info
;
char
element_char
;
bool
is_valid
=
aarch64_simd_valid_immediate
(
const_vector
,
&
info
)
;
gcc_assert
(
is_valid
)
;
element_char
=
sizetochar
(
GET_MODE_BITSIZE
(
info
.
elt_mode
)
)
;
if
(
info
.
step
)
{
snprintf
(
templ
,
sizeof
(
templ
)
,
"index\t%%0.%c, #"
HOST_WIDE_INT_PRINT_DEC
", #"
HOST_WIDE_INT_PRINT_DEC
,
element_char
,
INTVAL
(
info
.
value
)
,
INTVAL
(
info
.
step
)
)
;
return
templ
;
}
if
(
GET_MODE_CLASS
(
info
.
elt_mode
)
==
MODE_FLOAT
)
{
if
(
aarch64_float_const_zero_rtx_p
(
info
.
value
)
)
info
.
value
=
GEN_INT
(
0
)
;
else
{
const
int
buf_size
=
20
;
char
float_buf
[
buf_size
]
=
{
}
;
real_to_decimal_for_mode
(
float_buf
,
CONST_DOUBLE_REAL_VALUE
(
info
.
value
)
,
buf_size
,
buf_size
,
1
,
info
.
elt_mode
)
;
snprintf
(
templ
,
sizeof
(
templ
)
,
"fmov\t%%0.%c, #%s"
,
element_char
,
float_buf
)
;
return
templ
;
}
}
snprintf
(
templ
,
sizeof
(
templ
)
,
"mov\t%%0.%c, #"
HOST_WIDE_INT_PRINT_DEC
,
element_char
,
INTVAL
(
info
.
value
)
)
;
return
templ
;
}
</s>

Return the output string to use for moving immediate CONST_VECTOR into an SVE register .


<s> static int sequent_regs_live ( void ) { int reg ; int live_seq = 0 ; int cur_seq = 0 ; for ( reg = 0 ; reg < 18 ; ++ reg ) { if ( ! call_used_regs [ reg ] ) { if ( regs_ever_live [ reg ] ) { ++ live_seq ; ++ cur_seq ; } else cur_seq = 0 ; } } if ( ! frame_pointer_needed ) { if ( regs_ever_live [ REG_Y ] ) { ++ live_seq ; ++ cur_seq ; } else cur_seq = 0 ; if ( regs_ever_live [ REG_Y + 1 ] ) { ++ live_seq ; ++ cur_seq ; } else cur_seq = 0 ; } else { cur_seq += 2 ; live_seq += 2 ; } return ( cur_seq == live_seq ) ? live_seq : 0 ; } </s>

This function checks sequence of live registers


<s> void MetadataStreamerV3 :: end ( ) { std :: string HSAMetadataString ; raw_string_ostream StrOS ( HSAMetadataString ) ; yaml :: Output YOut ( StrOS ) ; YOut << HSAMetadataRoot ; if ( DumpHSAMetadata ) dump ( StrOS . str ( ) ) ; if ( VerifyHSAMetadata ) verify ( StrOS . str ( ) ) ; } </s>

Get a const_iterator to the end of the symbol table .


<s> void MSP430RegisterInfo :: eliminateFrameIndex ( MachineBasicBlock :: iterator II , int SPAdj , unsigned FIOperandNum , RegScavenger * RS ) const { assert ( SPAdj == 0 && "Unexpected" ) ; MachineInstr & MI = * II ; MachineBasicBlock & MBB = * MI . getParent ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; const MSP430FrameLowering * TFI = getFrameLowering ( MF ) ; DebugLoc dl = MI . getDebugLoc ( ) ; int FrameIndex = MI . getOperand ( FIOperandNum ) . getIndex ( ) ; unsigned BasePtr = ( TFI -> hasFP ( MF ) ? MSP430 :: FP : MSP430 :: SP ) ; int Offset = MF . getFrameInfo ( ) -> getObjectOffset ( FrameIndex ) ; Offset += 2 ; if ( ! TFI -> hasFP ( MF ) ) Offset += MF . getFrameInfo ( ) -> getStackSize ( ) ; else Offset += 2 ; Offset += MI . getOperand ( FIOperandNum + 1 ) . getImm ( ) ; if ( MI . getOpcode ( ) == MSP430 :: ADD16ri ) { const TargetInstrInfo & TII = * MF . getSubtarget ( ) . getInstrInfo ( ) ; MI . setDesc ( TII . get ( MSP430 :: MOV16rr ) ) ; MI . getOperand ( FIOperandNum ) . ChangeToRegister ( BasePtr , false ) ; if ( Offset == 0 ) return ; unsigned DstReg = MI . getOperand ( 0 ) . getReg ( ) ; if ( Offset < 0 ) BuildMI ( MBB , std :: next ( II ) , dl , TII . get ( MSP430 :: SUB16ri ) , DstReg ) . addReg ( DstReg ) . addImm ( - Offset ) ; else BuildMI ( MBB , std :: next ( II ) , dl , TII . get ( MSP430 :: ADD16ri ) , DstReg ) . addReg ( DstReg ) . addImm ( Offset ) ; return ; } MI . getOperand ( FIOperandNum ) . ChangeToRegister ( BasePtr , false ) ; MI . getOperand ( FIOperandNum + 1 ) . ChangeToImmediate ( Offset ) ; } </s>

This method must be overriden to eliminate abstract frame indices from instructions which may use them .


"invalid conversion from type %<__vector_quad%>"

"invalid conversion to type %<__vector_quad%>"

"invalid conversion from type %<__vector_pair%>"

"invalid conversion to type %<__vector_pair%>"


<s> bool nds32_n13_last_load_to_e1_p ( rtx_insn * producer , rtx_insn * consumer ) { rtx last_def_reg = extract_nth_access_reg ( producer , - 1 ) ; return n13_consumed_by_e1_dep_p ( consumer , last_def_reg ) ; } </s>

Check dependencies from LMW ( N , N ) to E1 .


<s>
ScheduleHazardRecognizer
::
HazardType
HexagonHazardRecognizer
::
getHazardType
(
SUnit
*
SU
,
int
stalls
)
{
MachineInstr
*
MI
=
SU
->
getInstr
(
)
;
if
(
!
MI
||
TII
->
isZeroCost
(
MI
->
getOpcode
(
)
)
)
return
NoHazard
;
if
(
!
Resources
->
canReserveResources
(
*
MI
)
)
{
LLVM_DEBUG
(
dbgs
(
)
<<
"*** Hazard in cycle "
<<
PacketNum
<<
", "
<<
*
MI
)
;
HazardType
RetVal
=
Hazard
;
if
(
TII
->
mayBeNewStore
(
*
MI
)
)
{
MachineOperand
&
MO
=
MI
->
getOperand
(
MI
->
getNumOperands
(
)
1
)
;
if
(
!
MO
.
isReg
(
)
||
RegDefs
.
count
(
MO
.
getReg
(
)
)
==
0
)
return
Hazard
;
MachineFunction
*
MF
=
MI
->
getParent
(
)
->
getParent
(
)
;
MachineInstr
*
NewMI
=
MF
->
CreateMachineInstr
(
TII
->
get
(
TII
->
getDotNewOp
(
*
MI
)
)
,
MI
->
getDebugLoc
(
)
)
;
if
(
Resources
->
canReserveResources
(
*
NewMI
)
)
RetVal
=
NoHazard
;
LLVM_DEBUG
(
dbgs
(
)
<<
"*** Try .new version? "
<<
(
RetVal
==
NoHazard
)
<<
"\n"
)
;
MF
->
DeleteMachineInstr
(
NewMI
)
;
}
return
RetVal
;
}
if
(
SU
==
UsesDotCur
&&
DotCurPNum
!=
(
int
)
PacketNum
)
{
LLVM_DEBUG
(
dbgs
(
)
<<
"*** .cur Hazard in cycle "
<<
PacketNum
<<
", "
<<
*
MI
)
;
return
Hazard
;
}
return
NoHazard
;
}
</s>

getHazardType - Return the hazard type of emitting this node .

Hexagon
Hexagon
"*** Hazard in cycle "
", "
1
0
"*** Try .new version? "
"\n"
"*** .cur Hazard in cycle "
", "


"Arch64 does not support GOT PC rel with extra offset"

Get the target specific PC relative GOT entry relocation .


<s> unsigned AArch64TTI :: getIntImmCost ( Intrinsic :: ID IID , unsigned Idx , const APInt & Imm , Type * Ty ) const { assert ( Ty -> isIntegerTy ( ) ) ; unsigned BitSize = Ty -> getPrimitiveSizeInBits ( ) ; if ( BitSize == 0 ) return TCC_Free ; switch ( IID ) { default : return TCC_Free ; case Intrinsic :: sadd_with_overflow : case Intrinsic :: uadd_with_overflow : case Intrinsic :: ssub_with_overflow : case Intrinsic :: usub_with_overflow : case Intrinsic :: smul_with_overflow : case Intrinsic :: umul_with_overflow : if ( Idx == 1 ) { unsigned NumConstants = ( BitSize + 63 ) / 64 ; unsigned Cost = AArch64TTI :: getIntImmCost ( Imm , Ty ) ; return ( Cost <= NumConstants * TCC_Basic ) ? static_cast < unsigned > ( TCC_Free ) : Cost ; } break ; case Intrinsic :: experimental_stackmap : if ( ( Idx < 2 ) || ( Imm . getBitWidth ( ) <= 64 && isInt < 64 > ( Imm . getSExtValue ( ) ) ) ) return TCC_Free ; break ; case Intrinsic :: experimental_patchpoint_void : case Intrinsic :: experimental_patchpoint_i64 : if ( ( Idx < 4 ) || ( Imm . getBitWidth ( ) <= 64 && isInt < 64 > ( Imm . getSExtValue ( ) ) ) ) return TCC_Free ; break ; } return AArch64TTI :: getIntImmCost ( Imm , Ty ) ; } </s>

Calculate the cost of materializing a 64-bit value .


<s> unsigned getPrefetchDistance ( ) const override { return PrefetchDistance ; } </s>

Return the preferred prefetch distance in terms of instructions .


<s> static unsigned addLiveIn ( MachineFunction & MF , unsigned PReg , const TargetRegisterClass * RC ) { unsigned VReg = MF . getRegInfo ( ) . createVirtualRegister ( RC ) ; MF . getRegInfo ( ) . addLiveIn ( PReg , VReg ) ; return VReg ; } </s>

addLiveIn - Add the specified register as a live-in .


<s> void X86AsmBackend :: emitInstructionBegin ( MCObjectStreamer & OS , const MCInst & Inst ) { CanPadInst = canPadInst ( Inst , OS ) ; if ( ! canPadBranches ( OS ) ) return ; if ( ! isMacroFused ( PrevInst , Inst ) ) PendingBA = nullptr ; if ( ! CanPadInst ) return ; if ( PendingBA && OS . getCurrentFragment ( ) -> getPrevNode ( ) == PendingBA ) { return ; } if ( needAlign ( Inst ) || ( ( AlignBranchType & X86 :: AlignBranchFused ) && isFirstMacroFusibleInst ( Inst , * MCII ) ) ) { OS . insert ( PendingBA = new MCBoundaryAlignFragment ( AlignBoundary ) ) ; } } </s>

Give the target a chance to manipulate state related to instruction alignment ( e.g .


<s>
void
pa_asm_output_aligned_common
(
FILE
*
stream
,
const
char
*
name
,
unsigned
HOST_WIDE_INT
size
,
unsigned
int
align
)
{
unsigned
int
max_common_align
;
max_common_align
=
TARGET_64BIT
128
:
(
size
>=
4096
256
:
64
)
;
if
(
align
>
max_common_align
)
{
align
=
max_common_align
;
}
switch_to_section
(
bss_section
)
;
assemble_name
(
stream
,
name
)
;
fprintf
(
stream
,
"\t.comm "
HOST_WIDE_INT_PRINT_UNSIGNED
"\n"
,
MAX
(
size
,
align
/
BITS_PER_UNIT
)
)
;
}
</s>

Both the HP and GNU assemblers under HP-UX provide a .comm directive that does n't allow the alignment of global common storage to be directly specified . The SOM linker aligns common storage based on the rounded value of the NUM_BYTES parameter in the .comm directive . It 's not possible to use the .align directive as it does n't affect the alignment of the label associated with a .comm directive .


<s>
static
void
macho_branch_islands
(
void
)
{
char
tmp_buf
[
512
]
;
while
(
!
vec_safe_is_empty
(
branch_islands
)
)
{
branch_island
*
bi
=
&
branch_islands
->
last
(
)
;
const
char
*
label
=
IDENTIFIER_POINTER
(
bi
->
label_name
)
;
const
char
*
name
=
IDENTIFIER_POINTER
(
bi
->
function_name
)
;
char
name_buf
[
512
]
;
if
(
name
[
0
]
==
'*'
||
name
[
0
]
==
'&'
)
strcpy
(
name_buf
,
name
+
1
)
;
else
{
name_buf
[
0
]
=
'_'
;
strcpy
(
name_buf
+
1
,
name
)
;
}
strcpy
(
tmp_buf
,
"\n"
)
;
strcat
(
tmp_buf
,
label
)
;
if
(
flag_pic
)
{
strcat
(
tmp_buf
,
":\n\tmflr r0\n\tbcl 20,31,"
)
;
strcat
(
tmp_buf
,
label
)
;
strcat
(
tmp_buf
,
"_pic\n"
)
;
strcat
(
tmp_buf
,
label
)
;
strcat
(
tmp_buf
,
"_pic:\n\tmflr r11\n"
)
;
strcat
(
tmp_buf
,
"\taddis r11,r11,ha16("
)
;
strcat
(
tmp_buf
,
name_buf
)
;
strcat
(
tmp_buf
,
" - "
)
;
strcat
(
tmp_buf
,
label
)
;
strcat
(
tmp_buf
,
"_pic)\n"
)
;
strcat
(
tmp_buf
,
"\tmtlr r0\n"
)
;
strcat
(
tmp_buf
,
"\taddi r12,r11,lo16("
)
;
strcat
(
tmp_buf
,
name_buf
)
;
strcat
(
tmp_buf
,
" - "
)
;
strcat
(
tmp_buf
,
label
)
;
strcat
(
tmp_buf
,
"_pic)\n"
)
;
strcat
(
tmp_buf
,
"\tmtctr r12\n\tbctr\n"
)
;
}
else
{
strcat
(
tmp_buf
,
":\n\tlis r12,hi16("
)
;
strcat
(
tmp_buf
,
name_buf
)
;
strcat
(
tmp_buf
,
")\n\tori r12,r12,lo16("
)
;
strcat
(
tmp_buf
,
name_buf
)
;
strcat
(
tmp_buf
,
")\n\tmtctr r12\n\tbctr"
)
;
}
output_asm_insn
(
tmp_buf
,
0
)
;
branch_islands
->
pop
(
)
;
}
}
</s>

Generate far-jump branch islands for everything on the branch_island_list . Invoked immediately after the last instruction of the epilogue has been emitted ; the branch-islands must be appended to , and contiguous with , the function body . Mach-O stubs are generated in machopic_output_stub ( ) .


<s> static bool aarch64_scalar_mode_supported_p ( machine_mode mode ) { return ( mode == HFmode ? true : default_scalar_mode_supported_p ( mode ) ) ; } </s>

Implement TARGET_SCALAR_MODE_SUPPORTED_P - return TRUE if MODE is HFmode , and punt to the generic implementation otherwise .


<s> int ConvergingVLIWScheduler :: pressureChange ( const SUnit * SU , bool isBotUp ) { PressureDiff & PD = DAG -> getPressureDiff ( SU ) ; for ( auto & P : PD ) { if ( ! P . isValid ( ) ) continue ; if ( HighPressureSets [ P . getPSet ( ) ] ) return ( isBotUp ? P . getUnitInc ( ) : - P . getUnitInc ( ) ) ; } return 0 ; } </s>

Check if the instruction changes the register pressure of a register in the high pressure set .


<s> void X86IntelInstPrinter :: printInst ( const MCInst * MI , raw_ostream & OS ) { printInstruction ( MI , OS ) ; if ( CommentStream ) EmitAnyX86InstComments ( MI , * CommentStream , getRegisterName ) ; } </s>

Print the specified MCInst to the specified raw_ostream .


"ReadCycleWrite is only to be used on riscv32"

This method should be implemented by targets that mark instructions with the 'usesCustomInserter ' flag .


<s> static rtx aarch64_gen_load_pair ( machine_mode mode , rtx reg1 , rtx mem1 , rtx reg2 , rtx mem2 ) { switch ( mode ) { case DImode : return gen_load_pairdi ( reg1 , mem1 , reg2 , mem2 ) ; case DFmode : return gen_load_pairdf ( reg1 , mem1 , reg2 , mem2 ) ; default : gcc_unreachable ( ) ; } } </s>

Generate and regurn a load pair isntruction of mode MODE to load register REG1 from MEM1 and register REG2 from MEM2 .


<s> void assignValueToReg ( unsigned ValVReg , unsigned PhysReg , CCValAssign & VA ) override { MIB . addUse ( PhysReg , RegState :: Implicit ) ; unsigned ExtReg = extendRegister ( ValVReg , VA ) ; MIRBuilder . buildCopy ( PhysReg , ExtReg ) ; } </s>

The specified value has been assigned to a physical register , handle the appropriate COPY ( either to or from ) and mark any relevant uses/defines as needed .


<s> StringRef SIRegisterInfo :: getRegAsmName ( MCRegister Reg ) const { return AMDGPUInstPrinter :: getRegisterName ( Reg ) ; } </s>


<s> MachineBasicBlock :: iterator eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI ) const override { return MBB . erase ( MI ) ; } </s>

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .


<s> bool ARM64AsmParser :: ParseDirective ( AsmToken DirectiveID ) { StringRef IDVal = DirectiveID . getIdentifier ( ) ; SMLoc Loc = DirectiveID . getLoc ( ) ; if ( IDVal == ".hword" ) return parseDirectiveWord ( 2 , Loc ) ; if ( IDVal == ".word" ) return parseDirectiveWord ( 4 , Loc ) ; if ( IDVal == ".xword" ) return parseDirectiveWord ( 8 , Loc ) ; if ( IDVal == ".tlsdesccall" ) return parseDirectiveTLSDescCall ( Loc ) ; return parseDirectiveLOH ( IDVal , Loc ) ; } </s>

ParseDirective - Parse a target specific assembler directive This method is deprecated , use 'parseDirective ' instead .


<s> bool X86FrameLowering :: hasFP ( const MachineFunction & MF ) const { const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const MachineModuleInfo & MMI = MF . getMMI ( ) ; const TargetRegisterInfo * RegInfo = TM . getRegisterInfo ( ) ; return ( MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) || RegInfo -> needsStackRealignment ( MF ) || MFI -> hasVarSizedObjects ( ) || MFI -> isFrameAddressTaken ( ) || MFI -> hasInlineAsmWithSPAdjust ( ) || MF . getInfo < X86MachineFunctionInfo > ( ) -> getForceFramePointer ( ) || MMI . callsUnwindInit ( ) || MMI . callsEHReturn ( ) ) ; } </s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .


<s> bool PPCFrameLowering :: spillCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , ArrayRef < CalleeSavedInfo > CSI , const TargetRegisterInfo * TRI ) const { MachineFunction * MF = MBB . getParent ( ) ; const PPCInstrInfo & TII = * Subtarget . getInstrInfo ( ) ; PPCFunctionInfo * FI = MF -> getInfo < PPCFunctionInfo > ( ) ; bool MustSaveTOC = FI -> mustSaveTOC ( ) ; DebugLoc DL ; bool CRSpilled = false ; MachineInstrBuilder CRMIB ; for ( unsigned i = 0 , e = CSI . size ( ) ; i != e ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; bool IsCRField = PPC :: CR2 <= Reg && Reg <= PPC :: CR4 ; const MachineRegisterInfo & MRI = MF -> getRegInfo ( ) ; bool IsLiveIn = MRI . isLiveIn ( Reg ) ; if ( ! IsLiveIn ) MBB . addLiveIn ( Reg ) ; if ( CRSpilled && IsCRField ) { CRMIB . addReg ( Reg , RegState :: ImplicitKill ) ; continue ; } if ( ( Reg == PPC :: X2 || Reg == PPC :: R2 ) && MustSaveTOC ) continue ; if ( IsCRField ) { PPCFunctionInfo * FuncInfo = MF -> getInfo < PPCFunctionInfo > ( ) ; if ( ! Subtarget . is32BitELFABI ( ) ) { FuncInfo -> addMustSaveCR ( Reg ) ; } else { CRSpilled = true ; FuncInfo -> setSpillsCR ( ) ; CRMIB = BuildMI ( * MF , DL , TII . get ( PPC :: MFCR ) , PPC :: R12 ) . addReg ( Reg , RegState :: ImplicitKill ) ; MBB . insert ( MI , CRMIB ) ; MBB . insert ( MI , addFrameReference ( BuildMI ( * MF , DL , TII . get ( PPC :: STW ) ) . addReg ( PPC :: R12 , getKillRegState ( true ) ) , CSI [ i ] . getFrameIdx ( ) ) ) ; } } else { if ( CSI [ i ] . isSpilledToReg ( ) ) { NumPESpillVSR ++ ; BuildMI ( MBB , MI , DL , TII . get ( PPC :: MTVSRD ) , CSI [ i ] . getDstReg ( ) ) . addReg ( Reg , getKillRegState ( true ) ) ; } else { const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ; if ( Subtarget . needsSwapsForVSXMemOps ( ) && ! MF -> getFunction ( ) . hasFnAttribute ( Attribute :: NoUnwind ) ) TII . storeRegToStackSlotNoUpd ( MBB , MI , Reg , ! IsLiveIn , CSI [ i ] . getFrameIdx ( ) , RC , TRI ) ; else TII . storeRegToStackSlot ( MBB , MI , Reg , ! IsLiveIn , CSI [ i ] . getFrameIdx ( ) , RC , TRI ) ; } } } return true ; } </s>

spillCalleeSavedRegisters - Issues instruction ( s ) to spill all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of store instructions via storeRegToStackSlot ( ) .


<s> EVT X86TargetLowering :: getSetCCResultType ( const DataLayout & DL , LLVMContext & , EVT VT ) const { if ( ! VT . isVector ( ) ) return Subtarget -> hasAVX512 ( ) ? MVT :: i1 : MVT :: i8 ; if ( VT . isSimple ( ) ) { MVT VVT = VT . getSimpleVT ( ) ; const unsigned NumElts = VVT . getVectorNumElements ( ) ; const MVT EltVT = VVT . getVectorElementType ( ) ; if ( VVT . is512BitVector ( ) ) { if ( Subtarget -> hasAVX512 ( ) ) if ( EltVT == MVT :: i32 || EltVT == MVT :: i64 || EltVT == MVT :: f32 || EltVT == MVT :: f64 ) switch ( NumElts ) { case 8 : return MVT :: v8i1 ; case 16 : return MVT :: v16i1 ; } if ( Subtarget -> hasBWI ( ) ) if ( EltVT == MVT :: i8 || EltVT == MVT :: i16 ) switch ( NumElts ) { case 32 : return MVT :: v32i1 ; case 64 : return MVT :: v64i1 ; } } if ( VVT . is256BitVector ( ) || VVT . is128BitVector ( ) ) { if ( Subtarget -> hasVLX ( ) ) if ( EltVT == MVT :: i32 || EltVT == MVT :: i64 || EltVT == MVT :: f32 || EltVT == MVT :: f64 ) switch ( NumElts ) { case 2 : return MVT :: v2i1 ; case 4 : return MVT :: v4i1 ; case 8 : return MVT :: v8i1 ; } if ( Subtarget -> hasBWI ( ) && Subtarget -> hasVLX ( ) ) if ( EltVT == MVT :: i8 || EltVT == MVT :: i16 ) switch ( NumElts ) { case 8 : return MVT :: v8i1 ; case 16 : return MVT :: v16i1 ; case 32 : return MVT :: v32i1 ; } } } return VT . changeVectorElementTypeToInteger ( ) ; } </s>

Return the value type to use for ISD : :SETCC .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


"insertBranch must not be told to insert a fallthrough"

"VE branch conditions should have three component!"

"Unconditional branch with multiple successors!"

Insert branch code into the end of the specified MachineBasicBlock .


<s> void AArch64ElfTargetObjectFile :: Initialize ( MCContext & Ctx , const TargetMachine & TM ) { TargetLoweringObjectFileELF :: Initialize ( Ctx , TM ) ; InitializeELF ( TM . Options . UseInitArray ) ; } </s>

This method must be called before any actual lowering is done .


<s> static machine_mode ix86_promote_function_mode ( const_tree type , machine_mode mode , int * punsignedp , const_tree fntype , int for_return ) { if ( type != NULL_TREE && POINTER_TYPE_P ( type ) ) { * punsignedp = POINTERS_EXTEND_UNSIGNED ; return word_mode ; } return default_promote_function_mode ( type , mode , punsignedp , fntype , for_return ) ; } </s>

Pointer function arguments and return values are promoted to word_mode .


<s> const TargetRegisterClass * SIRegisterInfo :: getRegClass ( unsigned RCID ) const { switch ( ( int ) RCID ) { case AMDGPU :: SReg_1RegClassID : return getBoolRC ( ) ; case AMDGPU :: SReg_1_XEXECRegClassID : return isWave32 ? & AMDGPU :: SReg_32_XM0_XEXECRegClass : & AMDGPU :: SReg_64_XEXECRegClass ; case - 1 : return nullptr ; default : return AMDGPUGenRegisterInfo :: getRegClass ( RCID ) ; } } </s>

Given a machine instruction descriptor , returns the register class constraint for OpNum , or NULL .


<s> bool aarch64_madd_needs_nop ( rtx_insn * insn ) { enum attr_type attr_type ; rtx_insn * prev ; rtx body ; if ( ! TARGET_FIX_ERR_A53_835769 ) return false ; if ( ! INSN_P ( insn ) || recog_memoized ( insn ) < 0 ) return false ; attr_type = get_attr_type ( insn ) ; if ( ! is_madd_op ( attr_type ) ) return false ; prev = aarch64_prev_real_insn ( insn ) ; extract_constrain_insn_cached ( insn ) ; if ( ! prev || ! has_memory_op ( prev ) ) return false ; body = single_set ( prev ) ; if ( GET_MODE ( recog_data . operand [ 0 ] ) == DImode && ( ! body || ! dep_between_memop_and_curr ( body ) ) ) return true ; return false ; } </s>

When working around the Cortex-A53 erratum 835769 , given rtx_insn INSN , return true if it is a 64-bit multiply-accumulate instruction and has a preceding memory instruction such that a NOP should be inserted between them .


<s> bool Warning ( SMLoc L , const Twine & Msg , ArrayRef < SMRange > Ranges = None ) { return Parser . Warning ( L , Msg , Ranges ) ; } </s>

Emit a warning at the location L , with the message Msg .


<s> void ARMInstrInfo :: reMaterialize ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned DestReg , unsigned SubIdx , const MachineInstr * Orig , const TargetRegisterInfo & TRI ) const { DebugLoc dl = Orig -> getDebugLoc ( ) ; unsigned Opcode = Orig -> getOpcode ( ) ; switch ( Opcode ) { default : break ; case ARM :: MOVi2pieces : { RI . emitLoadConstPool ( MBB , I , dl , DestReg , SubIdx , Orig -> getOperand ( 1 ) . getImm ( ) , ( ARMCC :: CondCodes ) Orig -> getOperand ( 2 ) . getImm ( ) , Orig -> getOperand ( 3 ) . getReg ( ) ) ; MachineInstr * NewMI = prior ( I ) ; NewMI -> getOperand ( 0 ) . setSubReg ( SubIdx ) ; return ; } } return ARMBaseInstrInfo :: reMaterialize ( MBB , I , DestReg , SubIdx , Orig , TRI ) ; } </s>

Re-issue the specified 'original ' instruction at the specific location targeting a new destination register .


<s> static bool riscv_memmodel_needs_amo_acquire ( enum memmodel model ) { switch ( model ) { case MEMMODEL_ACQ_REL : case MEMMODEL_SEQ_CST : case MEMMODEL_SYNC_SEQ_CST : case MEMMODEL_ACQUIRE : case MEMMODEL_CONSUME : case MEMMODEL_SYNC_ACQUIRE : return true ; case MEMMODEL_RELEASE : case MEMMODEL_SYNC_RELEASE : case MEMMODEL_RELAXED : return false ; default : gcc_unreachable ( ) ; } } </s>

Return true if the .AQ suffix should be added to an AMO to implement the acquire portion of memory model MODEL .


<s> bool HexagonPacketizerList :: updateOffset ( SUnit * SUI , SUnit * SUJ ) { assert ( SUI -> getInstr ( ) && SUJ -> getInstr ( ) ) ; MachineInstr & MI = * SUI -> getInstr ( ) ; MachineInstr & MJ = * SUJ -> getInstr ( ) ; unsigned BPI , OPI ; if ( ! HII -> getBaseAndOffsetPosition ( MI , BPI , OPI ) ) return false ; unsigned BPJ , OPJ ; if ( ! HII -> getBaseAndOffsetPosition ( MJ , BPJ , OPJ ) ) return false ; unsigned Reg = MI . getOperand ( BPI ) . getReg ( ) ; if ( Reg != MJ . getOperand ( BPJ ) . getReg ( ) ) return false ; for ( const auto & PI : SUI -> Preds ) if ( PI . getKind ( ) != SDep :: Anti && ( PI . getKind ( ) != SDep :: Data || PI . getReg ( ) != Reg ) ) return false ; int Incr ; if ( ! HII -> getIncrementValue ( MJ , Incr ) ) return false ; int64_t Offset = MI . getOperand ( OPI ) . getImm ( ) ; if ( ! HII -> isValidOffset ( MI . getOpcode ( ) , Offset + Incr , HRI ) ) return false ; MI . getOperand ( OPI ) . setImm ( Offset + Incr ) ; ChangedOffset = Offset ; return true ; } </s>

Return true if we can update the offset in MI so that MI and MJ can be packetized together .


<s>
void
PatmosOperand
::
print
(
raw_ostream
&
OS
)
const
{
switch
(
Kind
)
{
case
Immediate
:
getImm
(
)
->
print
(
OS
,
nullptr
)
;
break
;
case
Register
:
OS
<<
"<register "
;
OS
<<
PatmosInstPrinter
::
getRegisterName
(
getReg
(
)
)
<<
">"
;
break
;
case
Token
:
OS
<<
"'"
<<
getToken
(
)
<<
"'"
;
break
;
case
Memory
:
{
OS
<<
"<memory "
;
OS
<<
getMemBase
(
)
;
OS
<<
", "
;
OS
<<
getMemOff
(
)
;
OS
<<
">"
;
}
break
;
}
}
</s>

print - Print a debug representation of the operand to the given stream .

Patmos
Patmos
"<register "
Patmos
">"
"'"
"'"
"<memory "
", "
">"


<s> bool runOnMachineFunction ( MachineFunction & MF ) override { if ( skipFunction ( MF . getFunction ( ) ) ) return false ; const PPCSubtarget & STI = MF . getSubtarget < PPCSubtarget > ( ) ; if ( ! STI . hasVSX ( ) ) return false ; LIS = & getAnalysis < LiveIntervals > ( ) ; TII = STI . getInstrInfo ( ) ; bool Changed = false ; if ( DisableVSXFMAMutate ) return Changed ; for ( MachineBasicBlock & B : llvm :: make_early_inc_range ( MF ) ) if ( processBlock ( B ) ) Changed = true ; return Changed ; } </s>

runOnMachineFunction - Emit the function body .


<s>
MachineBasicBlock
*
CJGTargetLowering
::
EmitInstrWithCustomInserter
(
MachineInstr
&
MI
,
MachineBasicBlock
*
BB
)
const
{
unsigned
Opc
=
MI
.
getOpcode
(
)
;
const
TargetInstrInfo
&
TII
=
*
BB
->
getParent
(
)
->
getSubtarget
(
)
.
getInstrInfo
(
)
;
DebugLoc
dl
=
MI
.
getDebugLoc
(
)
;
assert
(
Opc
==
CJG
::
Select
&&
"Unexpected instr type to insert"
)
;
const
BasicBlock
*
LLVM_BB
=
BB
->
getBasicBlock
(
)
;
MachineFunction
::
iterator
I
=
++
BB
->
getIterator
(
)
;
MachineBasicBlock
*
thisMBB
=
BB
;
MachineFunction
*
F
=
BB
->
getParent
(
)
;
MachineBasicBlock
*
copy0MBB
=
F
->
CreateMachineBasicBlock
(
LLVM_BB
)
;
MachineBasicBlock
*
copy1MBB
=
F
->
CreateMachineBasicBlock
(
LLVM_BB
)
;
F
->
insert
(
I
,
copy0MBB
)
;
F
->
insert
(
I
,
copy1MBB
)
;
copy1MBB
->
splice
(
copy1MBB
->
begin
(
)
,
BB
,
std
::
next
(
MachineBasicBlock
::
iterator
(
MI
)
)
,
BB
->
end
(
)
)
;
copy1MBB
->
transferSuccessorsAndUpdatePHIs
(
BB
)
;
BB
->
addSuccessor
(
copy0MBB
)
;
BB
->
addSuccessor
(
copy1MBB
)
;
BuildMI
(
BB
,
dl
,
TII
.
get
(
CJG
::
JCC
)
)
.
addMBB
(
copy1MBB
)
.
addImm
(
MI
.
getOperand
(
3
)
.
getImm
(
)
)
;
BB
=
copy0MBB
;
BB
->
addSuccessor
(
copy1MBB
)
;
BB
=
copy1MBB
;
BuildMI
(
*
BB
,
BB
->
begin
(
)
,
dl
,
TII
.
get
(
CJG
::
PHI
)
,
MI
.
getOperand
(
0
)
.
getReg
(
)
)
.
addReg
(
MI
.
getOperand
(
2
)
.
getReg
(
)
)
.
addMBB
(
copy0MBB
)
.
addReg
(
MI
.
getOperand
(
1
)
.
getReg
(
)
)
.
addMBB
(
thisMBB
)
;
MI
.
eraseFromParent
(
)
;
return
BB
;
}
</s>

This method should be implemented by targets that mark instructions with the 'usesCustomInserter ' flag .


<s> const MCPhysReg * SIRegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { CallingConv :: ID CC = MF -> getFunction ( ) . getCallingConv ( ) ; switch ( CC ) { case CallingConv :: C : case CallingConv :: Fast : case CallingConv :: Cold : return ST . hasGFX90AInsts ( ) ? CSR_AMDGPU_GFX90AInsts_SaveList : CSR_AMDGPU_SaveList ; case CallingConv :: AMDGPU_Gfx : return ST . hasGFX90AInsts ( ) ? CSR_AMDGPU_SI_Gfx_GFX90AInsts_SaveList : CSR_AMDGPU_SI_Gfx_SaveList ; default : { static const MCPhysReg NoCalleeSavedReg = AMDGPU :: NoRegister ; return & NoCalleeSavedReg ; } } } </s>

AMDGPU SI AMDGPU AMDGPU AMDGPU SI SI AMDGPU::NoRegister