<s> Register RISCVTargetLowering :: getExceptionPointerRegister ( const Constant * PersonalityFn ) const { return RISCV :: X10 ; } </s>

If a physical register , this returns the register that receives the exception address on entry to an EH pad .


<s> static int cbranch_predicted_taken_p ( rtx insn ) { rtx x = find_reg_note ( insn , REG_BR_PROB , 0 ) ; if ( x ) { int pred_val = XINT ( x , 0 ) ; return pred_val >= REG_BR_PROB_BASE / 2 ; } return 0 ; } </s>

Return nonzero if INSN is annotated with a REG_BR_PROB note that indicates it 's a branch that 's predicted taken .


<s> Register ( ) { PPCTargetMachine :: registerAsmPrinter ( createPPCAsmPrinterPass ) ; } </s>


<s> void HexagonTTIImpl :: getUnrollingPreferences ( Loop * L , ScalarEvolution & SE , TTI :: UnrollingPreferences & UP ) { UP . Runtime = UP . Partial = true ; if ( L && L -> empty ( ) && canPeel ( L ) && SE . getSmallConstantTripCount ( L ) == 0 && SE . getSmallConstantMaxTripCount ( L ) > 0 && SE . getSmallConstantMaxTripCount ( L ) <= 5 ) { UP . PeelCount = 2 ; } } </s>

Get target-customized preferences for the generic loop unrolling transformation .


<s> void tilegx_pre_atomic_barrier ( enum memmodel model ) { if ( need_atomic_barrier_p ( model , true ) ) emit_insn ( gen_memory_barrier ( ) ) ; } </s>

Emit barrier before an atomic , as needed for the memory MODEL .


<s>
bool
SILoadStoreOptimizer
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
if
(
skipFunction
(
*
MF
.
getFunction
(
)
)
)
return
false
;
const
TargetSubtargetInfo
&
STM
=
MF
.
getSubtarget
(
)
;
TRI
=
static_cast
<
const
SIRegisterInfo
*
>
(
STM
.
getRegisterInfo
(
)
)
;
TII
=
static_cast
<
const
SIInstrInfo
*
>
(
STM
.
getInstrInfo
(
)
)
;
MRI
=
&
MF
.
getRegInfo
(
)
;
LIS
=
&
getAnalysis
<
LiveIntervals
>
(
)
;
DEBUG
(
dbgs
(
)
<<
"Running SILoadStoreOptimizer\n"
)
;
assert
(
!
MRI
->
isSSA
(
)
)
;
bool
Modified
=
false
;
for
(
MachineBasicBlock
&
MBB
:
MF
)
Modified
|=
optimizeBlock
(
MBB
)
;
return
Modified
;
}
</s>

runOnMachineFunction - Emit the function body .

AMDGPU
SI
SI
SI
"Running SILoadStoreOptimizer\n"


<s> MCSection * HSAILMCAsmInfo :: getNonexecutableStackSection ( MCContext & Ctx ) const { return nullptr ; } </s>

Targets can implement this method to specify a section to switch to if the translation unit does n't have any trampolines that require an executable stack .


<s> void WebAssemblyExceptionInfo :: print ( raw_ostream & OS , const Module * ) const { for ( auto & WE : TopLevelExceptions ) WE -> print ( OS ) ; } </s>

print - Print a debug representation of the operand to the given stream .


<s> MachineBasicBlock * PIC16TargetLowering :: EmitInstrWithCustomInserter ( MachineInstr * MI , MachineBasicBlock * BB , DenseMap < MachineBasicBlock * , MachineBasicBlock * > * EM ) const { const TargetInstrInfo & TII = * getTargetMachine ( ) . getInstrInfo ( ) ; unsigned CC = ( PIC16CC :: CondCodes ) MI -> getOperand ( 3 ) . getImm ( ) ; DebugLoc dl = MI -> getDebugLoc ( ) ; const BasicBlock * LLVM_BB = BB -> getBasicBlock ( ) ; MachineFunction :: iterator It = BB ; ++ It ; MachineBasicBlock * thisMBB = BB ; MachineFunction * F = BB -> getParent ( ) ; MachineBasicBlock * copy0MBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * sinkMBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; BuildMI ( BB , dl , TII . get ( PIC16 :: pic16brcond ) ) . addMBB ( sinkMBB ) . addImm ( CC ) ; F -> insert ( It , copy0MBB ) ; F -> insert ( It , sinkMBB ) ; for ( MachineBasicBlock :: succ_iterator I = BB -> succ_begin ( ) , E = BB -> succ_end ( ) ; I != E ; ++ I ) { EM -> insert ( std :: make_pair ( * I , sinkMBB ) ) ; sinkMBB -> addSuccessor ( * I ) ; } while ( ! BB -> succ_empty ( ) ) BB -> removeSuccessor ( BB -> succ_begin ( ) ) ; BB -> addSuccessor ( copy0MBB ) ; BB -> addSuccessor ( sinkMBB ) ; BB = copy0MBB ; BB -> addSuccessor ( sinkMBB ) ; BB = sinkMBB ; BuildMI ( BB , dl , TII . get ( PIC16 :: PHI ) , MI -> getOperand ( 0 ) . getReg ( ) ) . addReg ( MI -> getOperand ( 2 ) . getReg ( ) ) . addMBB ( copy0MBB ) . addReg ( MI -> getOperand ( 1 ) . getReg ( ) ) . addMBB ( thisMBB ) ; F -> DeleteMachineInstr ( MI ) ; return BB ; } </s>

This method should be implemented by targets that mark instructions with the 'usesCustomInserter ' flag .


<s> static tree mips_d_handle_target_float_abi ( void ) { const char * abi ; if ( TARGET_HARD_FLOAT_ABI ) abi = "hard" ; else if ( TARGET_SOFT_FLOAT_ABI ) abi = "soft" ; else abi = "" ; return build_string_literal ( strlen ( abi ) + 1 , abi ) ; } </s>

Handle a call to ` __traits ( getTargetInfo , `` floatAbi '' ) ' .


<s> static tree rs6000_stack_protect_fail ( void ) { return ( DEFAULT_ABI == ABI_V4 && TARGET_SECURE_PLT && flag_pic ) ? default_hidden_stack_protect_fail ( ) : default_external_stack_protect_fail ( ) ; } </s>

For TARGET_SECURE_PLT 32-bit PIC code we can save PIC register setup by using __stack_chk_fail_local hidden function instead of calling __stack_chk_fail directly . Otherwise it is better to call __stack_chk_fail directly .


<s> const AMDGPUIntrinsicInfo * getIntrinsicInfo ( ) const override { return & IntrinsicInfo ; } </s>

If intrinsic information is available , return it . If not , return null .


<s> SDValue AMDGPUTargetLowering :: getRecipEstimate ( SDValue Operand , DAGCombinerInfo & DCI , unsigned & RefinementSteps ) const { SelectionDAG & DAG = DCI . DAG ; EVT VT = Operand . getValueType ( ) ; if ( VT == MVT :: f32 ) { RefinementSteps = 0 ; return DAG . getNode ( AMDGPUISD :: RCP , SDLoc ( Operand ) , VT , Operand ) ; } return SDValue ( ) ; } </s>

Return a reciprocal estimate value for the input operand .


<s> void rs6000_emit_cbranch ( machine_mode mode , rtx operands [ ] ) { rtx condition_rtx , loc_ref ; condition_rtx = rs6000_generate_compare ( operands [ 0 ] , mode ) ; loc_ref = gen_rtx_LABEL_REF ( VOIDmode , operands [ 3 ] ) ; emit_jump_insn ( gen_rtx_SET ( VOIDmode , pc_rtx , gen_rtx_IF_THEN_ELSE ( VOIDmode , condition_rtx , loc_ref , pc_rtx ) ) ) ; } </s>

Emit a branch of kind CODE to location LOC .


<s> const uint32_t * X86RegisterInfo :: getCallPreservedMask ( CallingConv :: ID CC ) const { bool HasAVX = TM . getSubtarget < X86Subtarget > ( ) . hasAVX ( ) ; bool HasAVX512 = TM . getSubtarget < X86Subtarget > ( ) . hasAVX512 ( ) ; switch ( CC ) { case CallingConv :: GHC : case CallingConv :: HiPE : return CSR_NoRegs_RegMask ; case CallingConv :: AnyReg : if ( HasAVX ) return CSR_64_AllRegs_AVX_RegMask ; return CSR_64_AllRegs_RegMask ; case CallingConv :: PreserveMost : return CSR_64_RT_MostRegs_RegMask ; case CallingConv :: PreserveAll : if ( HasAVX ) return CSR_64_RT_AllRegs_AVX_RegMask ; return CSR_64_RT_AllRegs_RegMask ; case CallingConv :: Intel_OCL_BI : { if ( IsWin64 && HasAVX512 ) return CSR_Win64_Intel_OCL_BI_AVX512_RegMask ; if ( Is64Bit && HasAVX512 ) return CSR_64_Intel_OCL_BI_AVX512_RegMask ; if ( IsWin64 && HasAVX ) return CSR_Win64_Intel_OCL_BI_AVX_RegMask ; if ( Is64Bit && HasAVX ) return CSR_64_Intel_OCL_BI_AVX_RegMask ; if ( ! HasAVX && ! IsWin64 && Is64Bit ) return CSR_64_Intel_OCL_BI_RegMask ; } case CallingConv :: Cold : if ( Is64Bit ) return CSR_64_MostRegs_RegMask ; break ; default : break ; } if ( Is64Bit ) { if ( IsWin64 ) return CSR_Win64_RegMask ; return CSR_64_RegMask ; } return CSR_32_RegMask ; } </s>

Return a mask of call-preserved registers for the given calling convention on the current function .


<s>
void
WebAssemblyFrameLowering
::
emitPrologue
(
MachineFunction
&
MF
,
MachineBasicBlock
&
MBB
)
const
{
llvm_unreachable
(
"TODO: implement emitPrologue"
)
;
}
</s>

emitProlog/emitEpilog - These methods insert prolog and epilog code into the function .

WebAssembly
WebAssembly
"TODO: implement emitPrologue"


<s> bool AArch64PassConfig :: addPreISel ( ) { if ( TM -> getOptLevel ( ) != CodeGenOpt :: None ) addPass ( createGlobalMergePass ( TM ) ) ; return false ; } </s>


<s> bool SystemZInstrInfo :: isStackSlotCopy ( const MachineInstr & MI , int & DestFrameIndex , int & SrcFrameIndex ) const { const MachineFrameInfo * MFI = MI . getParent ( ) -> getParent ( ) -> getFrameInfo ( ) ; if ( MI . getOpcode ( ) != SystemZ :: MVC || ! MI . getOperand ( 0 ) . isFI ( ) || MI . getOperand ( 1 ) . getImm ( ) != 0 || ! MI . getOperand ( 3 ) . isFI ( ) || MI . getOperand ( 4 ) . getImm ( ) != 0 ) return false ; int64_t Length = MI . getOperand ( 2 ) . getImm ( ) ; unsigned FI1 = MI . getOperand ( 0 ) . getIndex ( ) ; unsigned FI2 = MI . getOperand ( 3 ) . getIndex ( ) ; if ( MFI -> getObjectSize ( FI1 ) != Length || MFI -> getObjectSize ( FI2 ) != Length ) return false ; DestFrameIndex = FI1 ; SrcFrameIndex = FI2 ; return true ; } </s>

Return true if the specified machine instruction is a copy of one stack slot to another and has no other effect .


<s>
StringRef
getPassName
(
)
const
override
{
return
"ARM Assembly Printer"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> bool easy_altivec_constant ( rtx op , machine_mode mode ) { unsigned step , copies ; if ( mode == VOIDmode ) mode = GET_MODE ( op ) ; else if ( mode != GET_MODE ( op ) ) return false ; if ( mode == V2DFmode ) return zero_constant ( op , mode ) ; else if ( mode == V2DImode ) { if ( GET_CODE ( CONST_VECTOR_ELT ( op , 0 ) ) != CONST_INT || GET_CODE ( CONST_VECTOR_ELT ( op , 1 ) ) != CONST_INT ) return false ; if ( zero_constant ( op , mode ) ) return true ; if ( INTVAL ( CONST_VECTOR_ELT ( op , 0 ) ) == - 1 && INTVAL ( CONST_VECTOR_ELT ( op , 1 ) ) == - 1 ) return true ; return false ; } else if ( mode == V1TImode ) return false ; step = GET_MODE_NUNITS ( mode ) / 4 ; copies = 1 ; if ( vspltis_constant ( op , step , copies ) ) return true ; if ( step == 1 ) copies <<= 1 ; else step >>= 1 ; if ( vspltis_constant ( op , step , copies ) ) return true ; if ( step == 1 ) copies <<= 1 ; else step >>= 1 ; if ( vspltis_constant ( op , step , copies ) ) return true ; if ( vspltis_shifted ( op ) != 0 ) return true ; return false ; } </s>

Return true if OP is of the given MODE and can be synthesized with a vspltisb , vspltish or vspltisw .


<s> static rtx ix86_expand_sse_compare ( const struct builtin_description * d , tree exp , rtx target , bool swap ) { rtx pat ; tree arg0 = CALL_EXPR_ARG ( exp , 0 ) ; tree arg1 = CALL_EXPR_ARG ( exp , 1 ) ; rtx op0 = expand_normal ( arg0 ) ; rtx op1 = expand_normal ( arg1 ) ; rtx op2 ; machine_mode tmode = insn_data [ d -> icode ] . operand [ 0 ] . mode ; machine_mode mode0 = insn_data [ d -> icode ] . operand [ 1 ] . mode ; machine_mode mode1 = insn_data [ d -> icode ] . operand [ 2 ] . mode ; enum rtx_code comparison = d -> comparison ; if ( VECTOR_MODE_P ( mode0 ) ) op0 = safe_vector_operand ( op0 , mode0 ) ; if ( VECTOR_MODE_P ( mode1 ) ) op1 = safe_vector_operand ( op1 , mode1 ) ; if ( swap ) std :: swap ( op0 , op1 ) ; if ( optimize || ! target || GET_MODE ( target ) != tmode || ! insn_data [ d -> icode ] . operand [ 0 ] . predicate ( target , tmode ) ) target = gen_reg_rtx ( tmode ) ; if ( ( optimize && ! register_operand ( op0 , mode0 ) ) || ! insn_data [ d -> icode ] . operand [ 1 ] . predicate ( op0 , mode0 ) ) op0 = copy_to_mode_reg ( mode0 , op0 ) ; if ( ( optimize && ! register_operand ( op1 , mode1 ) ) || ! insn_data [ d -> icode ] . operand [ 2 ] . predicate ( op1 , mode1 ) ) op1 = copy_to_mode_reg ( mode1 , op1 ) ; op2 = gen_rtx_fmt_ee ( comparison , mode0 , op0 , op1 ) ; pat = GEN_FCN ( d -> icode ) ( target , op0 , op1 , op2 ) ; if ( ! pat ) return 0 ; emit_insn ( pat ) ; return target ; } </s>

Subroutine of ix86_expand_builtin to take care of comparison insns .


Return an array that contains the direct target flag values and their names .

RISCV RISCV RISCV "riscv-call" "riscv-plt" "riscv-lo" "riscv-hi" "riscv-pcrel-lo" "riscv-pcrel-hi" "riscv-got-hi" "riscv-tprel-lo" "riscv-tprel-hi" "riscv-tprel-add" "riscv-tls-got-hi" "riscv-tls-gd-hi" "riscv-captab-pcrel-hi" "riscv-tprel-cincoffset" "riscv-tls-ie-captab-pcrel-hi" "riscv-tls-gd-captab-pcrel-hi" "riscv-ccall"


<s>
void
ARMTargetLowering
::
ReplaceNodeResults
(
SDNode
*
N
,
SmallVectorImpl
<
SDValue
>
&
Results
,
SelectionDAG
&
DAG
)
const
{
SDValue
Res
;
switch
(
N
->
getOpcode
(
)
)
{
default
:
llvm_unreachable
(
"Don't know how to custom expand this!"
)
;
break
;
case
ISD
::
BITCAST
:
Res
=
ExpandBITCAST
(
N
,
DAG
)
;
break
;
case
ISD
::
SRL
:
case
ISD
::
SRA
:
Res
=
Expand64BitShift
(
N
,
DAG
,
Subtarget
)
;
break
;
case
ISD
::
ATOMIC_LOAD_ADD
:
ReplaceATOMIC_OP_64
(
N
,
Results
,
DAG
,
ARMISD
::
ATOMADD64_DAG
)
;
return
;
case
ISD
::
ATOMIC_LOAD_AND
:
ReplaceATOMIC_OP_64
(
N
,
Results
,
DAG
,
ARMISD
::
ATOMAND64_DAG
)
;
return
;
case
ISD
::
ATOMIC_LOAD_NAND
:
ReplaceATOMIC_OP_64
(
N
,
Results
,
DAG
,
ARMISD
::
ATOMNAND64_DAG
)
;
return
;
case
ISD
::
ATOMIC_LOAD_OR
:
ReplaceATOMIC_OP_64
(
N
,
Results
,
DAG
,
ARMISD
::
ATOMOR64_DAG
)
;
return
;
case
ISD
::
ATOMIC_LOAD_SUB
:
ReplaceATOMIC_OP_64
(
N
,
Results
,
DAG
,
ARMISD
::
ATOMSUB64_DAG
)
;
return
;
case
ISD
::
ATOMIC_LOAD_XOR
:
ReplaceATOMIC_OP_64
(
N
,
Results
,
DAG
,
ARMISD
::
ATOMXOR64_DAG
)
;
return
;
case
ISD
::
ATOMIC_SWAP
:
ReplaceATOMIC_OP_64
(
N
,
Results
,
DAG
,
ARMISD
::
ATOMSWAP64_DAG
)
;
return
;
case
ISD
::
ATOMIC_CMP_SWAP
:
ReplaceATOMIC_OP_64
(
N
,
Results
,
DAG
,
ARMISD
::
ATOMCMPXCHG64_DAG
)
;
return
;
}
if
(
Res
.
getNode
(
)
)
Results
.
push_back
(
Res
)
;
}
</s>

ReplaceNodeResults - Replace the results of node with an illegal result type with new values built out of custom code .


<s> static void frv_reorder_packet ( void ) { unsigned int cursor [ NUM_GROUPS ] ; rtx insns [ ARRAY_SIZE ( frv_unit_groups ) ] ; unsigned int unit , to , from ; enum frv_insn_group group ; struct frv_packet_group * packet_group ; for ( group = GROUP_I ; group < NUM_GROUPS ; group = ( enum frv_insn_group ) ( group + 1 ) ) { cursor [ group ] = 0 ; frv_sort_insn_group ( group ) ; } to = 0 ; for ( unit = 0 ; unit < ARRAY_SIZE ( frv_unit_groups ) ; unit ++ ) { group = frv_unit_groups [ unit ] ; packet_group = & frv_packet . groups [ group ] ; if ( cursor [ group ] < packet_group -> num_insns ) { gcc_assert ( packet_group -> sorted [ cursor [ group ] ] != packet_group -> nop ) ; insns [ to ++ ] = packet_group -> sorted [ cursor [ group ] ++ ] ; } } gcc_assert ( to == frv_packet . num_insns ) ; CLEAR_PACKING_FLAG ( insns [ to - 1 ] ) ; for ( from = 0 ; from < to - 1 ; from ++ ) { remove_insn ( insns [ from ] ) ; add_insn_before ( insns [ from ] , insns [ to - 1 ] , NULL ) ; SET_PACKING_FLAG ( insns [ from ] ) ; } } </s>

Sort the current packet into assembly-language order . Set packing flags as appropriate .


<s> static bool pdp11_assemble_integer ( rtx x , unsigned int size , int aligned_p ) { if ( aligned_p ) switch ( size ) { case 1 : fprintf ( asm_out_file , "\t.byte\t" ) ; output_addr_const_pdp11 ( asm_out_file , GEN_INT ( INTVAL ( x ) & 0xff ) ) ; fputs ( "\n" , asm_out_file ) ; return true ; case 2 : fprintf ( asm_out_file , TARGET_UNIX_ASM ? "\t" : "\t.word\t" ) ; output_addr_const_pdp11 ( asm_out_file , x ) ; fputs ( "\n" , asm_out_file ) ; return true ; } return default_assemble_integer ( x , size , aligned_p ) ; } </s>

Target hook to assemble integer objects . We need to use the pdp-specific version of output_addr_const .


<s> void GCNPassConfig :: addPreEmitPass ( ) { addPass ( createSIInsertWaitsPass ( ) , false ) ; addPass ( createSILowerControlFlowPass ( ) , false ) ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s> bool MOSInstructionSelector :: select ( MachineInstr & MI ) { if ( ! MI . isPreISelOpcode ( ) ) { constrainGenericOp ( MI ) ; return true ; } switch ( MI . getOpcode ( ) ) { case MOS :: G_ADD : case MOS :: G_SUB : if ( selectAddSub ( MI ) ) return true ; break ; case MOS :: G_AND : case MOS :: G_OR : case MOS :: G_XOR : if ( selectLogical ( MI ) ) return true ; break ; } if ( selectImpl ( MI , * CoverageInfo ) ) return true ; switch ( MI . getOpcode ( ) ) { default : return false ; case MOS :: G_BRCOND_IMM : return selectBrCondImm ( MI ) ; case MOS :: G_SBC : return selectSbc ( MI ) ; case MOS :: G_FRAME_INDEX : return selectFrameIndex ( MI ) ; case MOS :: G_BLOCK_ADDR : case MOS :: G_GLOBAL_VALUE : return selectAddr ( MI ) ; case MOS :: G_STORE_ABS : case MOS :: G_STORE_ABS_IDX : return selectStore ( MI ) ; case MOS :: G_LSHRE : case MOS :: G_SHLE : return selectLshrShlE ( MI ) ; case MOS :: G_MERGE_VALUES : return selectMergeValues ( MI ) ; case MOS :: G_TRUNC : return selectTrunc ( MI ) ; case MOS :: G_UADDE : case MOS :: G_SADDE : return selectAddE ( MI ) ; case MOS :: G_INC : case MOS :: G_DEC : case MOS :: G_INC_TMP : case MOS :: G_DEC_TMP : return selectIncDecMB ( MI ) ; case MOS :: G_UNMERGE_VALUES : return selectUnMergeValues ( MI ) ; case MOS :: G_BRINDIRECT : case MOS :: G_IMPLICIT_DEF : case MOS :: G_LOAD_ABS : case MOS :: G_LOAD_ABS_IDX : case MOS :: G_LOAD_INDIR_IDX : case MOS :: G_PHI : case MOS :: G_STORE_INDIR_IDX : return selectGeneric ( MI ) ; } } </s>

Select the ( possibly generic ) instruction I to only use target-specific opcodes .


<s> static bool pa_function_ok_for_sibcall ( tree decl , tree exp ATTRIBUTE_UNUSED ) { if ( TARGET_PORTABLE_RUNTIME ) return false ; if ( TARGET_64BIT ) return false ; return ( decl && ! TREE_PUBLIC ( decl ) ) ; } </s>

Only direct calls to static functions are allowed to be sibling ( tail ) call optimized . This restriction is necessary because some linker generated stubs will store return pointers into rp ' in some cases which might clobber a live value already in rp ' . In a sibcall the current function and the target function share stack space . Thus if the path to the current function and the path to the target function save a value in rp ' , they save the value into the same stack slot , which has undesirable consequences . Because of the deferred binding nature of shared libraries any function with external scope could be in a different load module and thus require rp ' to be saved when calling that function . So sibcall optimizations can only be safe for static function . Note that GCC never needs return value relocations , so we do n't have to worry about static calls with return value relocations ( which require saving rp ' ) . It is safe to perform a sibcall optimization when the target function will never return .


<s> void NVPTXAsmPrinter :: emitInstruction ( const MachineInstr * MI ) { MCInst Inst ; lowerToMCInst ( MI , Inst ) ; EmitToStreamer ( * OutStreamer , Inst ) ; } </s>

Targets should implement this to emit instructions .


<s> void GCNPassConfig :: addPreRegAlloc ( ) { if ( LateCFGStructurize ) { addPass ( createAMDGPUMachineCFGStructurizerPass ( ) ) ; } addPass ( createSIWholeQuadModePass ( ) ) ; } </s>

This method may be implemented by targets that want to run passes immediately before register allocation .


<s> void SparcPassConfig :: addPreEmitPass ( ) { addPass ( createSparcDelaySlotFillerPass ( ) ) ; if ( this -> getSparcTargetMachine ( ) . getSubtargetImpl ( ) -> insertNOPLoad ( ) ) { addPass ( new InsertNOPLoad ( ) ) ; } if ( this -> getSparcTargetMachine ( ) . getSubtargetImpl ( ) -> fixFSMULD ( ) ) { addPass ( new FixFSMULD ( ) ) ; } if ( this -> getSparcTargetMachine ( ) . getSubtargetImpl ( ) -> replaceFMULS ( ) ) { addPass ( new ReplaceFMULS ( ) ) ; } if ( this -> getSparcTargetMachine ( ) . getSubtargetImpl ( ) -> detectRoundChange ( ) ) { addPass ( new DetectRoundChange ( ) ) ; } if ( this -> getSparcTargetMachine ( ) . getSubtargetImpl ( ) -> fixAllFDIVSQRT ( ) ) { addPass ( new FixAllFDIVSQRT ( ) ) ; } } </s>

Sparc Sparc Sparc Sparc Sparc Sparc Sparc Sparc


Check OP is a legal scalar immediate for the MOVI instruction .


<s>
void
HexagonAsmPrinter
::
EmitInstruction
(
const
MachineInstr
*
MI
)
{
if
(
MI
->
isBundle
(
)
)
{
std
::
vector
<
const
MachineInstr
*
>
BundleMIs
;
const
MachineBasicBlock
*
MBB
=
MI
->
getParent
(
)
;
MachineBasicBlock
::
const_instr_iterator
MII
=
MI
;
++
MII
;
unsigned
int
IgnoreCount
=
0
;
while
(
MII
!=
MBB
->
end
(
)
&&
MII
->
isInsideBundle
(
)
)
{
const
MachineInstr
*
MInst
=
MII
;
if
(
MInst
->
getOpcode
(
)
==
TargetOpcode
::
DBG_VALUE
||
MInst
->
getOpcode
(
)
==
TargetOpcode
::
IMPLICIT_DEF
)
{
IgnoreCount
++
;
++
MII
;
continue
;
}
BundleMIs
.
push_back
(
MInst
)
;
++
MII
;
}
unsigned
Size
=
BundleMIs
.
size
(
)
;
assert
(
(
Size
+
IgnoreCount
)
==
MI
->
getBundleSize
(
)
&&
"Corrupt Bundle!"
)
;
for
(
unsigned
Index
=
0
;
Index
<
Size
;
Index
++
)
{
HexagonMCInst
MCI
;
MCI
.
setPacketStart
(
Index
==
0
)
;
MCI
.
setPacketEnd
(
Index
==
(
Size
1
)
)
;
HexagonLowerToMC
(
BundleMIs
[
Index
]
,
MCI
,
*
this
)
;
OutStreamer
.
EmitInstruction
(
MCI
)
;
}
}
else
{
HexagonMCInst
MCI
;
if
(
MI
->
getOpcode
(
)
==
Hexagon
::
ENDLOOP0
)
{
MCI
.
setPacketStart
(
true
)
;
MCI
.
setPacketEnd
(
true
)
;
}
HexagonLowerToMC
(
MI
,
MCI
,
*
this
)
;
OutStreamer
.
EmitInstruction
(
MCI
)
;
}
return
;
}
</s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s> static ARMOperand CreateReg ( unsigned RegNum , bool Writeback ) { ARMOperand Res ; Res . Kind = Register ; Res . Reg . RegNum = RegNum ; Res . Reg . Writeback = Writeback ; return Res ; } </s>

CreateReg - Allocate a single virtual register for the given type .


"Error: check for a non-legal type in this operation\n"

LowerOperation - Provide custom lowering hooks for some operations .


<s> unsigned PPCInstrInfo :: isStoreToStackSlot ( const MachineInstr * MI , int & FrameIndex ) const { switch ( MI -> getOpcode ( ) ) { default : break ; case PPC :: STD : case PPC :: STW : case PPC :: STFS : case PPC :: STFD : case PPC :: SPILL_CR : case PPC :: STVX : case PPC :: SPILL_VRSAVE : if ( MI -> getOperand ( 1 ) . isImm ( ) && ! MI -> getOperand ( 1 ) . getImm ( ) && MI -> getOperand ( 2 ) . isFI ( ) ) { FrameIndex = MI -> getOperand ( 2 ) . getIndex ( ) ; return MI -> getOperand ( 0 ) . getReg ( ) ; } break ; } return 0 ; } </s>

isStoreToStackSlot - If the specified machine instruction is a direct store to a stack slot , return the virtual or physical register number of the source reg along with the FrameIndex of the loaded stack slot .


<s> void Warning ( SMLoc L , const Twine & Msg ) { Parser . Warning ( L , Msg ) ; } </s>

Emit a warning at the location L , with the message Msg .


<s> static rtx aarch64_expand_sve_const_pred_eor ( rtx target , rtx_vector_builder & builder , unsigned int elt_size ) { rtx_vector_builder inv_builder ( VNx16BImode , builder . npatterns ( ) , builder . nelts_per_pattern ( ) ) ; for ( unsigned int i = 0 ; i < builder . encoded_nelts ( ) ; ++ i ) if ( ( i & ( elt_size - 1 ) ) == 0 && INTVAL ( builder . elt ( i ) ) == 0 ) inv_builder . quick_push ( const1_rtx ) ; else inv_builder . quick_push ( const0_rtx ) ; inv_builder . finalize ( ) ; rtx inv = aarch64_expand_sve_const_pred_1 ( NULL_RTX , inv_builder , false ) ; if ( ! inv ) return NULL_RTX ; rtx mask = aarch64_ptrue_all ( elt_size ) ; mask = force_reg ( VNx16BImode , mask ) ; inv = gen_lowpart ( VNx16BImode , inv ) ; target = aarch64_target_reg ( target , VNx16BImode ) ; emit_insn ( gen_aarch64_pred_z ( XOR , VNx16BImode , target , mask , inv , mask ) ) ; return target ; } </s>

BUILDER is a constant predicate in which the index of every set bit is a multiple of ELT_SIZE ( which is < = 8 ) . Try to load the constant by inverting every element at a multiple of ELT_SIZE and EORing the result with an ELT_SIZE PTRUE . Return a register that contains the constant on success , otherwise return null . Use TARGET as the register if it is nonnull and convenient .


<s> rtx assign_386_stack_local ( enum machine_mode mode , enum ix86_stack_slot n ) { struct stack_local_entry * s ; gcc_assert ( n < MAX_386_STACK_LOCALS ) ; for ( s = ix86_stack_locals ; s ; s = s -> next ) if ( s -> mode == mode && s -> n == n ) return s -> rtl ; s = ( struct stack_local_entry * ) ggc_alloc ( sizeof ( struct stack_local_entry ) ) ; s -> n = n ; s -> mode = mode ; s -> rtl = assign_stack_local ( mode , GET_MODE_SIZE ( mode ) , 0 ) ; s -> next = ix86_stack_locals ; ix86_stack_locals = s ; return s -> rtl ; } </s>

Return a MEM corresponding to a stack slot with mode MODE . Allocate a new slot if necessary . The RTL for a function can have several slots available : N is which slot to use .


<s> static bool avr_function_value_regno_p ( const unsigned int regno ) { return ( regno == avr_ret_register ( ) ) ; } </s>

Implement ` TARGET_FUNCTION_VALUE_REGNO_P ' .


<s> size_t THMToARMStub :: size ( ) const { return m_Size ; } </s>

The number of name/type pairs is returned .


<s> static void nvptx_sese_color ( auto_vec < unsigned > & color_counts , bb_pair_vec_t & regions , basic_block block , int coloring ) { bb_sese * sese = BB_GET_SESE ( block ) ; if ( block -> flags & BB_VISITED ) { gcc_assert ( coloring < 0 || ( sese && coloring == sese -> color ) ) ; return ; } block -> flags |= BB_VISITED ; if ( sese ) { if ( coloring < 0 ) { regions [ sese -> color ] . first = block ; coloring = sese -> color ; } if ( ! -- color_counts [ sese -> color ] && sese -> color == coloring ) { regions [ sese -> color ] . second = block ; coloring = - 1 ; } else sese -> color = coloring ; } else gcc_assert ( coloring < 0 ) ; if ( block -> succs && block -> succs -> length ( ) ) { edge e ; edge_iterator ei ; FOR_EACH_EDGE ( e , ei , block -> succs ) nvptx_sese_color ( color_counts , regions , e -> dest , coloring ) ; } else gcc_assert ( coloring < 0 ) ; } </s>

DFS walk of BB graph . Color node BLOCK according to COLORING then proceed to successors . Set SESE entry and exit nodes of REGIONS .


<s> bool empty ( ) const { return Queue . empty ( ) ; } </s>

Determine whether this version information is empty ( e.g. , all version components are zero ) .


<s> static Mnode * add_csky_minipool_forward_ref ( Mfix * fix ) { Mnode * max_mp = NULL ; HOST_WIDE_INT max_address = fix -> address + fix -> forwards ; Mnode * mp ; if ( minipool_vector_head && ( fix -> address + get_attr_length ( fix -> insn ) >= minipool_vector_head -> max_address - fix -> fix_size ) ) return NULL ; for ( mp = minipool_vector_head ; mp != NULL ; mp = mp -> next ) { if ( GET_CODE ( fix -> value ) == GET_CODE ( mp -> value ) && fix -> mode == mp -> mode && ( GET_CODE ( fix -> value ) != CODE_LABEL || ( CODE_LABEL_NUMBER ( fix -> value ) == CODE_LABEL_NUMBER ( mp -> value ) ) ) && rtx_equal_p ( fix -> value , mp -> value ) ) { mp -> refcount ++ ; return mp ; } if ( max_mp == NULL && mp -> max_address > max_address ) max_mp = mp ; } mp = XNEW ( Mnode ) ; mp -> fix_size = fix -> fix_size ; mp -> mode = fix -> mode ; mp -> value = fix -> value ; mp -> refcount = 1 ; mp -> min_address = - 65536 ; if ( max_mp == NULL ) { mp -> max_address = max_address ; mp -> next = NULL ; mp -> prev = minipool_vector_tail ; if ( mp -> prev == NULL ) { minipool_vector_head = mp ; minipool_vector_label = gen_csky_constpool_label ( gen_rtx_CONST_INT ( VOIDmode , constpool_label_no ++ ) ) ; } else mp -> prev -> next = mp ; minipool_vector_tail = mp ; } else { if ( max_address > max_mp -> max_address - mp -> fix_size ) mp -> max_address = max_mp -> max_address - mp -> fix_size ; else mp -> max_address = max_address ; mp -> next = max_mp ; mp -> prev = max_mp -> prev ; max_mp -> prev = mp ; if ( mp -> prev != NULL ) mp -> prev -> next = mp ; else minipool_vector_head = mp ; } max_mp = mp ; while ( mp -> prev != NULL && mp -> prev -> max_address > mp -> max_address - mp -> prev -> fix_size ) { mp -> prev -> max_address = mp -> max_address - mp -> prev -> fix_size ; mp = mp -> prev ; } return max_mp ; } </s>

Add a constant to the minipool for a forward reference . Returns the node added or NULL if the constant will not fit in this pool .


<s> int standard_sse_constant_p ( rtx x ) { machine_mode mode ; if ( ! TARGET_SSE ) return 0 ; mode = GET_MODE ( x ) ; if ( x == const0_rtx || x == CONST0_RTX ( mode ) ) return 1 ; if ( vector_all_ones_operand ( x , mode ) ) switch ( mode ) { case V16QImode : case V8HImode : case V4SImode : case V2DImode : if ( TARGET_SSE2 ) return 2 ; case V32QImode : case V16HImode : case V8SImode : case V4DImode : if ( TARGET_AVX2 ) return 2 ; case V64QImode : case V32HImode : case V16SImode : case V8DImode : if ( TARGET_AVX512F ) return 2 ; default : break ; } return 0 ; } </s>

Return 1 if X is all 0s and 2 if x is all 1s in supported SSE/AVX vector mode .


<s>
void
rvexInstrInfo
::
copyPhysReg
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
DebugLoc
DL
,
unsigned
DestReg
,
unsigned
SrcReg
,
bool
KillSrc
)
const
{
unsigned
Opc
=
0
,
ZeroReg
=
0
;
if
(
rvex
::
CPURegsRegClass
.
contains
(
DestReg
)
)
{
if
(
rvex
::
CPURegsRegClass
.
contains
(
SrcReg
)
)
Opc
=
rvex
::
ADD
,
ZeroReg
=
rvex
::
R0
;
else
if
(
SrcReg
==
rvex
::
HI
)
Opc
=
rvex
::
MFHI
,
SrcReg
=
0
;
else
if
(
SrcReg
==
rvex
::
LO
)
Opc
=
rvex
::
MFLO
,
SrcReg
=
0
;
}
else
if
(
rvex
::
CPURegsRegClass
.
contains
(
SrcReg
)
)
{
if
(
DestReg
==
rvex
::
HI
)
Opc
=
rvex
::
MTHI
,
DestReg
=
0
;
else
if
(
DestReg
==
rvex
::
LO
)
Opc
=
rvex
::
MTLO
,
DestReg
=
0
;
}
assert
(
Opc
&&
"Cannot copy registers"
)
;
MachineInstrBuilder
MIB
=
BuildMI
(
MBB
,
I
,
DL
,
get
(
Opc
)
)
;
if
(
DestReg
)
MIB
.
addReg
(
DestReg
,
RegState
::
Define
)
;
if
(
ZeroReg
)
MIB
.
addReg
(
ZeroReg
)
;
if
(
SrcReg
)
MIB
.
addReg
(
SrcReg
,
getKillRegState
(
KillSrc
)
)
;
}
</s>

rvex
rvex
0
0
rvex::CPURegsRegClass
rvex::CPURegsRegClass
rvex::ADD
rvex::R0
rvex::HI
rvex::MFHI
0
rvex::LO
rvex::MFLO
0
rvex::CPURegsRegClass
rvex::HI
rvex::MTHI
0
rvex::LO
rvex::MTLO
0
"Cannot copy registers"


<s> static bool rs6000_modes_tieable_p ( machine_mode mode1 , machine_mode mode2 ) { if ( mode1 == PTImode ) return mode2 == PTImode ; if ( mode2 == PTImode ) return false ; if ( ALTIVEC_OR_VSX_VECTOR_MODE ( mode1 ) ) return ALTIVEC_OR_VSX_VECTOR_MODE ( mode2 ) ; if ( ALTIVEC_OR_VSX_VECTOR_MODE ( mode2 ) ) return false ; if ( SCALAR_FLOAT_MODE_P ( mode1 ) ) return SCALAR_FLOAT_MODE_P ( mode2 ) ; if ( SCALAR_FLOAT_MODE_P ( mode2 ) ) return false ; if ( GET_MODE_CLASS ( mode1 ) == MODE_CC ) return GET_MODE_CLASS ( mode2 ) == MODE_CC ; if ( GET_MODE_CLASS ( mode2 ) == MODE_CC ) return false ; if ( SPE_VECTOR_MODE ( mode1 ) ) return SPE_VECTOR_MODE ( mode2 ) ; if ( SPE_VECTOR_MODE ( mode2 ) ) return false ; return true ; } </s>

Implement TARGET_MODES_TIEABLE_P . PTImode can not tie with other modes because PTImode is restricted to even GPR registers , and TImode can go in any GPR as well as VSX registers ( PR 57744 ) . Similarly , do n't allow OOmode ( vector pair , restricted to even VSX registers ) or XOmode ( vector quad , restricted to FPR registers divisible by 4 ) to tie with other modes . Altivec/VSX vector tests were moved ahead of scalar float mode , so that IEEE 128-bit floating point on VSX systems ties with other vectors .


<s> static rtx mt_generate_compare ( enum rtx_code code , rtx op0 , rtx op1 ) { rtx scratch0 , scratch1 , const_scratch ; switch ( code ) { case GTU : case LTU : case GEU : case LEU : scratch0 = gen_reg_rtx ( SImode ) ; scratch1 = gen_reg_rtx ( SImode ) ; const_scratch = force_reg ( SImode , GEN_INT ( MT_MIN_INT ) ) ; emit_insn ( gen_addsi3 ( scratch0 , const_scratch , op0 ) ) ; emit_insn ( gen_addsi3 ( scratch1 , const_scratch , op1 ) ) ; break ; default : scratch0 = op0 ; scratch1 = op1 ; break ; } switch ( code ) { case GTU : code = GT ; break ; case LTU : code = LT ; break ; case GEU : code = GE ; break ; case LEU : code = LE ; break ; default : break ; } return gen_rtx_fmt_ee ( code , VOIDmode , scratch0 , scratch1 ) ; } </s>

Generate a compare for CODE . Return a brand-new rtx that represents the result of the compare .


<s> static bool nvptx_use_anchors_for_symbol_p ( const_rtx ARG_UNUSED ( a ) ) { return false ; } </s>

Section anchors do not work . Initialization for flag_section_anchor probes the existence of the anchoring target hooks and prevents anchoring if they do n't exist . However , we may be being used with a host-side compiler that does support anchoring , and hence see the anchor flag set ( as it 's not recalculated ) . So provide an implementation denying anchoring .


<s> Sparc :: Fixups getFixupKind ( ) const { return getFixupKind ( Kind ) ; } </s>

getFixupKind - Get the fixup kind of this expression .


<s> bool NyuziRegisterInfo :: requiresRegisterScavenging ( const MachineFunction & MF ) const { return true ; } </s>

Returns true if the target requires ( and can make use of ) the register scavenger .


<s> static rtx ix86_expand_int_compare ( enum rtx_code code , rtx op0 , rtx op1 ) { machine_mode cmpmode ; rtx tmp , flags ; cmpmode = SELECT_CC_MODE ( code , op0 , op1 ) ; flags = gen_rtx_REG ( cmpmode , FLAGS_REG ) ; tmp = gen_rtx_COMPARE ( cmpmode , op0 , op1 ) ; emit_insn ( gen_rtx_SET ( VOIDmode , flags , tmp ) ) ; return gen_rtx_fmt_ee ( code , VOIDmode , flags , const0_rtx ) ; } </s>

Generate insn patterns to do an integer compare of OPERANDS .


<s> void emitInstruction ( const MCInst & Inst , const MCSubtargetInfo & STI ) override { EmitA64MappingSymbol ( ) ; MCELFStreamer :: emitInstruction ( Inst , STI ) ; } </s>

Targets should implement this to emit instructions .


<s> APFloat getAPFloat ( ) const { return Flt ; } </s>

getSubExpr - Get the child of this expression .


Worker function for TARGET_ASM_CONSTRUCTOR .


<s> bool AArch64FrameLowering :: assignCalleeSavedSpillSlots ( MachineFunction & MF , const TargetRegisterInfo * TRI , std :: vector < CalleeSavedInfo > & CSI ) const { bool NeedsWinCFI = needsWinCFI ( MF ) ; if ( NeedsWinCFI ) std :: reverse ( CSI . begin ( ) , CSI . end ( ) ) ; return false ; } </s>

This function will assign callee saved gprs to volatile vector registers for prologue spills when applicable .


<s> PPCSubtarget :: PPCSubtarget ( const std :: string & TT , const std :: string & CPU , const std :: string & FS , bool is64Bit ) : PPCGenSubtargetInfo ( TT , CPU , FS ) , StackAlignment ( 16 ) , DarwinDirective ( PPC :: DIR_NONE ) , HasMFOCRF ( false ) , Has64BitSupport ( false ) , Use64BitRegs ( false ) , IsPPC64 ( is64Bit ) , HasAltivec ( false ) , HasQPX ( false ) , HasFSQRT ( false ) , HasFRE ( false ) , HasFRES ( false ) , HasFRSQRTE ( false ) , HasFRSQRTES ( false ) , HasRecipPrec ( false ) , HasSTFIWX ( false ) , HasLFIWAX ( false ) , HasFPRND ( false ) , HasFPCVT ( false ) , HasISEL ( false ) , HasPOPCNTD ( false ) , HasLDBRX ( false ) , IsBookE ( false ) , HasLazyResolverStubs ( false ) , IsJITCodeModel ( false ) , TargetTriple ( TT ) { std :: string CPUName = CPU ; if ( CPUName . empty ( ) ) CPUName = "generic" ; ( defined ( __ppc__ ) || defined ( __powerpc__ ) ) if ( CPUName == "generic" ) CPUName = sys :: getHostCPUName ( ) ; InstrItins = getInstrItineraryForCPU ( CPUName ) ; std :: string FullFS = FS ; if ( is64Bit ) { Has64BitSupport = true ; Use64BitRegs = true ; if ( ! FullFS . empty ( ) ) FullFS = "+64bit," + FullFS ; else FullFS = "+64bit" ; } ParseSubtargetFeatures ( CPUName , FullFS ) ; if ( use64BitRegs ( ) && ! has64BitSupport ( ) ) Use64BitRegs = false ; if ( isDarwin ( ) ) HasLazyResolverStubs = true ; if ( hasQPX ( ) || isBGQ ( ) ) StackAlignment = 32 ; } </s>

This constructor initializes the data members to match that of the specified triple .


<s> void PPCTargetLowering :: computeKnownBitsForTargetNode ( const SDValue Op , KnownBits & Known , const APInt & DemandedElts , const SelectionDAG & DAG , unsigned Depth ) const { Known . resetAll ( ) ; switch ( Op . getOpcode ( ) ) { default : break ; case PPCISD :: LBRX : { if ( cast < VTSDNode > ( Op . getOperand ( 2 ) ) -> getVT ( ) == MVT :: i16 ) Known . Zero = 0xFFFF0000 ; break ; } case ISD :: INTRINSIC_WO_CHAIN : { switch ( cast < ConstantSDNode > ( Op . getOperand ( 0 ) ) -> getZExtValue ( ) ) { default : break ; case Intrinsic :: ppc_altivec_vcmpbfp_p : case Intrinsic :: ppc_altivec_vcmpeqfp_p : case Intrinsic :: ppc_altivec_vcmpequb_p : case Intrinsic :: ppc_altivec_vcmpequh_p : case Intrinsic :: ppc_altivec_vcmpequw_p : case Intrinsic :: ppc_altivec_vcmpequd_p : case Intrinsic :: ppc_altivec_vcmpgefp_p : case Intrinsic :: ppc_altivec_vcmpgtfp_p : case Intrinsic :: ppc_altivec_vcmpgtsb_p : case Intrinsic :: ppc_altivec_vcmpgtsh_p : case Intrinsic :: ppc_altivec_vcmpgtsw_p : case Intrinsic :: ppc_altivec_vcmpgtsd_p : case Intrinsic :: ppc_altivec_vcmpgtub_p : case Intrinsic :: ppc_altivec_vcmpgtuh_p : case Intrinsic :: ppc_altivec_vcmpgtuw_p : case Intrinsic :: ppc_altivec_vcmpgtud_p : Known . Zero = ~ 1U ; break ; } } } } </s>

Determine which of the bits specified in Mask are known to be either zero or one and return them in the KnownZero/KnownOne bitsets .


<s> bool fixupNeedsRelaxation ( const MCFixup & Fixup , uint64_t Value , const MCRelaxableFragment * DF , const MCAsmLayout & Layout ) const override { return false ; } </s>

Simple predicate for targets where ! Resolved implies requiring relaxation .


<s> void SparcRegisterInfo :: emitPrologue ( MachineFunction & MF ) const { MachineBasicBlock & MBB = MF . front ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; MachineBasicBlock :: iterator MBBI = MBB . begin ( ) ; DebugLoc dl = ( MBBI != MBB . end ( ) ? MBBI -> getDebugLoc ( ) : DebugLoc :: getUnknownLoc ( ) ) ; int NumBytes = ( int ) MFI -> getStackSize ( ) ; NumBytes += 92 ; NumBytes = ( NumBytes + 7 ) & ~ 7 ; NumBytes = - NumBytes ; if ( NumBytes >= - 4096 ) { BuildMI ( MBB , MBBI , dl , TII . get ( SP :: SAVEri ) , SP :: O6 ) . addReg ( SP :: O6 ) . addImm ( NumBytes ) ; } else { unsigned OffHi = ( unsigned ) NumBytes >> 10U ; BuildMI ( MBB , MBBI , dl , TII . get ( SP :: SETHIi ) , SP :: G1 ) . addImm ( OffHi ) ; BuildMI ( MBB , MBBI , dl , TII . get ( SP :: ORri ) , SP :: G1 ) . addReg ( SP :: G1 ) . addImm ( NumBytes & ( ( 1 << 10 ) - 1 ) ) ; BuildMI ( MBB , MBBI , dl , TII . get ( SP :: SAVErr ) , SP :: O6 ) . addReg ( SP :: O6 ) . addReg ( SP :: G1 ) ; } } </s>

emitProlog/emitEpilog - These methods insert prolog and epilog code into the function .


<s> SDValue AArch64TargetLowering :: BuildSDIVPow2 ( SDNode * N , const APInt & Divisor , SelectionDAG & DAG , SmallVectorImpl < SDNode * > & Created ) const { AttributeList Attr = DAG . getMachineFunction ( ) . getFunction ( ) . getAttributes ( ) ; if ( isIntDivCheap ( N -> getValueType ( 0 ) , Attr ) ) return SDValue ( N , 0 ) ; EVT VT = N -> getValueType ( 0 ) ; if ( ( VT != MVT :: i32 && VT != MVT :: i64 ) || ! ( Divisor . isPowerOf2 ( ) || ( - Divisor ) . isPowerOf2 ( ) ) ) return SDValue ( ) ; SDLoc DL ( N ) ; SDValue N0 = N -> getOperand ( 0 ) ; unsigned Lg2 = Divisor . countTrailingZeros ( ) ; SDValue Zero = DAG . getConstant ( 0 , DL , VT ) ; SDValue Pow2MinusOne = DAG . getConstant ( ( 1ULL << Lg2 ) - 1 , DL , VT ) ; SDValue CCVal ; SDValue Cmp = getAArch64Cmp ( N0 , Zero , ISD :: SETLT , CCVal , DAG , DL ) ; SDValue Add = DAG . getNode ( ISD :: ADD , DL , VT , N0 , Pow2MinusOne ) ; SDValue CSel = DAG . getNode ( AArch64ISD :: CSEL , DL , VT , Add , N0 , CCVal , Cmp ) ; Created . push_back ( Cmp . getNode ( ) ) ; Created . push_back ( Add . getNode ( ) ) ; Created . push_back ( CSel . getNode ( ) ) ; SDValue SRA = DAG . getNode ( ISD :: SRA , DL , VT , CSel , DAG . getConstant ( Lg2 , DL , MVT :: i64 ) ) ; if ( Divisor . isNonNegative ( ) ) return SRA ; Created . push_back ( SRA . getNode ( ) ) ; return DAG . getNode ( ISD :: SUB , DL , VT , DAG . getConstant ( 0 , DL , VT ) , SRA ) ; } </s>

Targets may override this function to provide custom SDIV lowering for power-of-2 denominators .


<s> SDNode * SITargetLowering :: PostISelFolding ( MachineSDNode * Node , SelectionDAG & DAG ) const { const SIInstrInfo * TII = getSubtarget ( ) -> getInstrInfo ( ) ; unsigned Opcode = Node -> getMachineOpcode ( ) ; if ( TII -> isMIMG ( Opcode ) && ! TII -> get ( Opcode ) . mayStore ( ) && ! TII -> isGather4 ( Opcode ) ) adjustWritemask ( Node , DAG ) ; if ( Opcode == AMDGPU :: INSERT_SUBREG || Opcode == AMDGPU :: REG_SEQUENCE ) { legalizeTargetIndependentNode ( Node , DAG ) ; return Node ; } return Node ; } </s>

Fold the instructions after selecting them .


<s> bool MipsExpandPseudo :: runOnMachineFunction ( MachineFunction & MF ) { STI = & static_cast < const MipsSubtarget & > ( MF . getSubtarget ( ) ) ; TII = STI -> getInstrInfo ( ) ; bool Modified = false ; for ( MachineFunction :: iterator MFI = MF . begin ( ) , E = MF . end ( ) ; MFI != E ; ++ MFI ) Modified |= expandMBB ( * MFI ) ; return Modified ; } </s>

runOnMachineFunction - Emit the function body .


<s> bool isMachineVerifierClean ( ) const override { return false ; } </s>

Returns true if the target is expected to pass all machine verifier checks .


<s> bool s390_split_ok_p ( rtx dst , rtx src , enum machine_mode mode , int first_subword ) { if ( FP_REG_P ( src ) || FP_REG_P ( dst ) ) return false ; if ( s_operand ( src , mode ) || s_operand ( dst , mode ) ) return false ; if ( ( GET_CODE ( src ) == MEM && ! offsettable_memref_p ( src ) ) || ( GET_CODE ( dst ) == MEM && ! offsettable_memref_p ( dst ) ) ) return false ; if ( register_operand ( dst , mode ) ) { rtx subreg = operand_subword ( dst , first_subword , 0 , mode ) ; if ( reg_overlap_mentioned_p ( subreg , src ) ) return false ; } return true ; } </s>

Check whether we can ( and want to ) split a double-word move in mode MODE from SRC to DST into two single-word moves , moving the subword FIRST_SUBWORD first .


<s> static unsigned int flags_from_mode ( machine_mode mode ) { switch ( mode ) { case CC_ZSmode : return CC_FLAG_S | CC_FLAG_Z ; case CC_ZSOmode : return CC_FLAG_S | CC_FLAG_Z | CC_FLAG_O ; case CC_ZSCmode : return CC_FLAG_S | CC_FLAG_Z | CC_FLAG_C ; case CCmode : return CC_FLAG_S | CC_FLAG_Z | CC_FLAG_O | CC_FLAG_C ; case CC_Fmode : return CC_FLAG_FP ; default : gcc_unreachable ( ) ; } } </s>

Convert a CC_MODE to the set of flags that it represents .


<s>
unsigned
MipsOutgoingValueHandler
::
assignCustomValue
(
CallLowering
::
ArgInfo
&
Arg
,
ArrayRef
<
CCValAssign
>
VAs
)
{
const
CCValAssign
&
VALo
=
VAs
[
0
]
;
const
CCValAssign
&
VAHi
=
VAs
[
1
]
;
assert
(
VALo
.
getLocVT
(
)
==
MVT
::
i32
&&
VAHi
.
getLocVT
(
)
==
MVT
::
i32
&&
VALo
.
getValVT
(
)
==
MVT
::
f64
&&
VAHi
.
getValVT
(
)
==
MVT
::
f64
&&
"unexpected custom value"
)
;
auto
Unmerge
=
MIRBuilder
.
buildUnmerge
(
{
LLT
::
scalar
(
32
)
,
LLT
::
scalar
(
32
)
}
,
Arg
.
Regs
[
0
]
)
;
Register
Lo
=
Unmerge
.
getReg
(
0
)
;
Register
Hi
=
Unmerge
.
getReg
(
1
)
;
Arg
.
OrigRegs
.
assign
(
Arg
.
Regs
.
begin
(
)
,
Arg
.
Regs
.
end
(
)
)
;
Arg
.
Regs
=
{
Lo
,
Hi
}
;
if
(
!
STI
.
isLittle
(
)
)
std
::
swap
(
Lo
,
Hi
)
;
MIRBuilder
.
buildCopy
(
VALo
.
getLocReg
(
)
,
Lo
)
;
MIRBuilder
.
buildCopy
(
VAHi
.
getLocReg
(
)
,
Hi
)
;
return
2
;
}
</s>

Handle custom values , which may be passed into one or more of VAs .


<s> static inline bool quad_address_offset_p ( HOST_WIDE_INT offset ) { return ( IN_RANGE ( offset , - 32768 , 32767 ) && ( ( offset ) & 0xf ) == 0 ) ; } </s>

Return true if the OFFSET is valid for the quad address instructions that use d-form ( register + offset ) addressing .


<s> void ix86_split_copysign_const ( rtx operands [ ] ) { machine_mode mode , vmode ; rtx dest , op0 , mask , x ; dest = operands [ 0 ] ; op0 = operands [ 1 ] ; mask = operands [ 3 ] ; mode = GET_MODE ( dest ) ; vmode = GET_MODE ( mask ) ; dest = lowpart_subreg ( vmode , dest , mode ) ; x = gen_rtx_AND ( vmode , dest , mask ) ; emit_insn ( gen_rtx_SET ( dest , x ) ) ; if ( op0 != CONST0_RTX ( vmode ) ) { x = gen_rtx_IOR ( vmode , dest , op0 ) ; emit_insn ( gen_rtx_SET ( dest , x ) ) ; } } </s>

Deconstruct a copysign operation into bit masks . Operand 0 is known to be a constant , and so has already been expanded into a vector constant .


"emitting conditional microcode insn %s\t[%s] #%d"

Define FINAL_PRESCAN_INSN if some processing needs to be done before outputting the assembler code . On the PowerPC , we remember if the current insn is a prefixed insn where we need to emit a ' p ' before the insn . In addition , if the insn is part of a PC-relative reference to an external label optimization , this is recorded also .


<s> static enum internal_test map_test_to_internal_test ( enum rtx_code test_code ) { enum internal_test test = ITEST_MAX ; switch ( test_code ) { case EQ : test = ITEST_EQ ; break ; case NE : test = ITEST_NE ; break ; case GT : test = ITEST_GT ; break ; case GE : test = ITEST_GE ; break ; case LT : test = ITEST_LT ; break ; case LE : test = ITEST_LE ; break ; case GTU : test = ITEST_GTU ; break ; case GEU : test = ITEST_GEU ; break ; case LTU : test = ITEST_LTU ; break ; case LEU : test = ITEST_LEU ; break ; default : break ; } return test ; } </s>

Make normal rtx_code into something we can index from an array


<s> void tilepro_cpu_cpp_builtins ( struct cpp_reader * pfile ) { builtin_define ( "__tile__" ) ; builtin_define ( "__tilepro__" ) ; builtin_assert ( "cpu=tile" ) ; builtin_assert ( "machine=tile" ) ; builtin_define ( "__tile_chip__=1" ) ; builtin_define ( "__tile_chip_rev__=0" ) ; builtin_define ( "__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1" ) ; builtin_define ( "__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2" ) ; builtin_define ( "__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4" ) ; builtin_define ( "__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8" ) ; TILEPRO_CPU_CPP_ENDIAN_BUILTINS ( ) ; GNU_USER_TARGET_OS_CPP_BUILTINS ( ) ; } </s>


<s> DecodeStatus RISCVDisassembler :: getInstruction ( MCInst & MI , uint64_t & Size , ArrayRef < uint8_t > Bytes , uint64_t Address , raw_ostream & OS , raw_ostream & CS ) const { Size = 4 ; if ( Bytes . size ( ) < 4 ) { Size = 0 ; return MCDisassembler :: Fail ; } uint32_t Inst = support :: endian :: read32le ( Bytes . data ( ) ) ; return decodeInstruction ( DecoderTable32 , MI , Inst , Address , this , STI ) ; } </s>

Returns the disassembly of a single instruction .


"Encoding of this operand type is not supported yet."

getMachineOpValue - Return binary encoding of operand .


<s>
void
ValueEnumerator
::
print
(
raw_ostream
&
OS
,
const
MetadataMapType
&
Map
,
const
char
*
Name
)
const
{
OS
<<
"Map Name: "
<<
Name
<<
"\n"
;
OS
<<
"Size: "
<<
Map
.
size
(
)
<<
"\n"
;
for
(
const
auto
&
I
:
Map
)
{
const
Metadata
*
MD
=
I
.
first
;
OS
<<
"Metadata: slot = "
<<
I
.
second
.
ID
<<
"\n"
;
OS
<<
"Metadata: function = "
<<
I
.
second
.
F
<<
"\n"
;
MD
->
print
(
OS
)
;
OS
<<
"\n"
;
}
}
</s>

print - Print a debug representation of the operand to the given stream .

DirectX
"Map Name: "
"\n"
"Size: "
"\n"
"Metadata: slot = "
"\n"
"Metadata: function = "
"\n"
"\n"


<s> bool isMem ( ) const { return Kind == k_Memory ; } </s>


<s> machine_mode aarch64_sve_pred_mode ( machine_mode mode ) { unsigned int bits = aarch64_sve_container_bits ( mode ) ; return aarch64_sve_pred_mode ( bits / BITS_PER_UNIT ) . require ( ) ; } </s>

Return the SVE predicate mode that should be used to control SVE mode MODE .


<s>
void
R600SchedStrategy
::
initialize
(
ScheduleDAGMI
*
dag
)
{
assert
(
dag
->
hasVRegLiveness
(
)
&&
"R600SchedStrategy needs vreg liveness"
)
;
DAG
=
static_cast
<
ScheduleDAGMILive
*
>
(
dag
)
;
const
AMDGPUSubtarget
&
ST
=
DAG
->
TM
.
getSubtarget
<
AMDGPUSubtarget
>
(
)
;
TII
=
static_cast
<
const
R600InstrInfo
*
>
(
DAG
->
TII
)
;
TRI
=
static_cast
<
const
R600RegisterInfo
*
>
(
DAG
->
TRI
)
;
VLIW5
=
!
ST
.
hasCaymanISA
(
)
;
MRI
=
&
DAG
->
MRI
;
CurInstKind
=
IDOther
;
CurEmitted
=
0
;
OccupedSlotsMask
=
31
;
InstKindLimit
[
IDAlu
]
=
TII
->
getMaxAlusPerClause
(
)
;
InstKindLimit
[
IDOther
]
=
32
;
InstKindLimit
[
IDFetch
]
=
ST
.
getTexVTXClauseSize
(
)
;
AluInstCount
=
0
;
FetchInstCount
=
0
;
}
</s>

Initialize the strategy after building the DAG for a new region .


<s> MCFragment * findAssociatedFragment ( ) const override { return nullptr ; } </s>

Find the `` associated section '' for this expression , which is currently defined as the absolute section for constants , or otherwise the section associated with the first defined symbol in the expression .


<s>
bool
A15SDOptimizer
::
runOnMachineFunction
(
MachineFunction
&
Fn
)
{
TII
=
static_cast
<
const
ARMBaseInstrInfo
*
>
(
Fn
.
getSubtarget
(
)
.
getInstrInfo
(
)
)
;
TRI
=
Fn
.
getSubtarget
(
)
.
getRegisterInfo
(
)
;
MRI
=
&
Fn
.
getRegInfo
(
)
;
bool
Modified
=
false
;
DEBUG
(
dbgs
(
)
<<
"Running on function "
<<
Fn
.
getName
(
)
<<
"\n"
)
;
DeadInstr
.
clear
(
)
;
Replacements
.
clear
(
)
;
for
(
MachineFunction
::
iterator
MFI
=
Fn
.
begin
(
)
,
E
=
Fn
.
end
(
)
;
MFI
!=
E
;
++
MFI
)
{
for
(
MachineBasicBlock
::
iterator
MI
=
MFI
->
begin
(
)
,
ME
=
MFI
->
end
(
)
;
MI
!=
ME
;
)
{
Modified
|=
runOnInstruction
(
MI
++
)
;
}
}
for
(
std
::
set
<
MachineInstr
*
>
::
iterator
I
=
DeadInstr
.
begin
(
)
,
E
=
DeadInstr
.
end
(
)
;
I
!=
E
;
++
I
)
{
(
*
I
)
->
eraseFromParent
(
)
;
}
return
Modified
;
}
</s>


<s> static tree alpha_fold_builtin_extxx ( tree op [ ] , unsigned HOST_WIDE_INT opint [ ] , long op_const , unsigned HOST_WIDE_INT bytemask , bool is_high ) { long zap_const = 2 ; tree * zap_op = NULL ; if ( op_const & 2 ) { unsigned HOST_WIDE_INT loc ; loc = opint [ 1 ] & 7 ; if ( BYTES_BIG_ENDIAN ) loc ^= 7 ; loc *= 8 ; if ( loc != 0 ) { if ( op_const & 1 ) { unsigned HOST_WIDE_INT temp = opint [ 0 ] ; if ( is_high ) temp <<= loc ; else temp >>= loc ; opint [ 0 ] = temp ; zap_const = 3 ; } } else zap_op = op ; } opint [ 1 ] = bytemask ; return alpha_fold_builtin_zapnot ( zap_op , opint , zap_const ) ; } </s>

Fold the builtins for the EXT family of instructions .


<s>
void
RISCVDAGToDAGISel
::
Select
(
SDNode
*
Node
)
{
unsigned
Opcode
=
Node
->
getOpcode
(
)
;
MVT
XLenVT
=
Subtarget
->
getXLenVT
(
)
;
if
(
Node
->
isMachineOpcode
(
)
)
{
LLVM_DEBUG
(
dbgs
(
)
<<
"== "
;
Node
->
dump
(
CurDAG
)
;
dbgs
(
)
<<
"\n"
)
;
Node
->
setNodeId
(
1
)
;
return
;
}
EVT
VT
=
Node
->
getValueType
(
0
)
;
if
(
Opcode
==
ISD
::
Constant
&&
VT
==
XLenVT
)
{
auto
*
ConstNode
=
cast
<
ConstantSDNode
>
(
Node
)
;
if
(
ConstNode
->
isNullValue
(
)
)
{
SDValue
New
=
CurDAG
->
getCopyFromReg
(
CurDAG
->
getEntryNode
(
)
,
SDLoc
(
Node
)
,
RISCV
::
X0
,
XLenVT
)
;
ReplaceNode
(
Node
,
New
.
getNode
(
)
)
;
return
;
}
}
if
(
Opcode
==
ISD
::
FrameIndex
)
{
SDLoc
DL
(
Node
)
;
SDValue
Imm
=
CurDAG
->
getTargetConstant
(
0
,
DL
,
XLenVT
)
;
int
FI
=
cast
<
FrameIndexSDNode
>
(
Node
)
->
getIndex
(
)
;
EVT
VT
=
Node
->
getValueType
(
0
)
;
SDValue
TFI
=
CurDAG
->
getTargetFrameIndex
(
FI
,
VT
)
;
ReplaceNode
(
Node
,
CurDAG
->
getMachineNode
(
RISCV
::
ADDI
,
DL
,
VT
,
TFI
,
Imm
)
)
;
return
;
}
SelectCode
(
Node
)
;
}
</s>

Main hook for targets to transform nodes into machine nodes .


"Expected SVE area to be calculated by this point"

Returns true if the target wants to use frame pointer based accesses to spill to the scavenger emergency spill slot .


<s>
static
void
add_vector_type_attribute
(
tree
type
,
const
char
*
mangled_name
)
{
tree
mangled_name_tree
=
get_identifier
(
mangled_name
)
;
tree
value
=
tree_cons
(
NULL_TREE
,
mangled_name_tree
,
NULL_TREE
)
;
TYPE_ATTRIBUTES
(
type
)
=
tree_cons
(
get_identifier
(
"RVV type"
)
,
value
,
TYPE_ATTRIBUTES
(
type
)
)
;
}
</s>

Add type attributes to builtin type tree , currently only the mangled name .


<s> void ix86_expand_binary_operator ( enum rtx_code code , enum machine_mode mode , rtx operands [ ] ) { rtx src1 , src2 , dst , op , clob ; dst = ix86_fixup_binary_operands ( code , mode , operands ) ; src1 = operands [ 1 ] ; src2 = operands [ 2 ] ; op = gen_rtx_SET ( VOIDmode , dst , gen_rtx_fmt_ee ( code , mode , src1 , src2 ) ) ; if ( reload_in_progress ) { gcc_assert ( code == PLUS ) ; emit_insn ( op ) ; } else { clob = gen_rtx_CLOBBER ( VOIDmode , gen_rtx_REG ( CCmode , FLAGS_REG ) ) ; emit_insn ( gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( 2 , op , clob ) ) ) ; } if ( dst != operands [ 0 ] ) emit_move_insn ( operands [ 0 ] , dst ) ; } </s>

Attempt to expand a binary operator . Make the expansion closer to the actual machine , then just general_operand , which will allow 3 separate memory references ( one output , two input ) in a single insn .


<s> bool mips_store_by_pieces_p ( unsigned HOST_WIDE_INT size , unsigned int align ) { if ( align <= BITS_PER_UNIT ) return size < 4 ; return size < 8 ; } </s>


<s> bool AAPDAGToDAGISel :: SelectInlineAsmMemoryOperand ( const SDValue & Op , unsigned ConstraintID , std :: vector < SDValue > & OutOps ) { switch ( ConstraintID ) { default : return true ; case InlineAsm :: Constraint_i : case InlineAsm :: Constraint_m : SDLoc DL ( Op ) ; SDValue RC = CurDAG -> getTargetConstant ( AAP :: GR64RegClass . getID ( ) , DL , MVT :: i16 ) ; SDNode * N = CurDAG -> getMachineNode ( TargetOpcode :: COPY_TO_REGCLASS , DL , Op . getValueType ( ) , Op , RC ) ; SDValue Zero = CurDAG -> getTargetConstant ( 0 , DL , MVT :: i16 ) ; OutOps . push_back ( SDValue ( N , 0 ) ) ; OutOps . push_back ( Zero ) ; break ; } return false ; } </s>

SelectInlineAsmMemoryOperand - Select the specified address as a target addressing mode , according to the specified constraint .


<s> bool XCoreTargetLowering :: CanLowerReturn ( CallingConv :: ID CallConv , MachineFunction & MF , bool isVarArg , const SmallVectorImpl < ISD :: OutputArg > & Outs , LLVMContext & Context ) const { SmallVector < CCValAssign , 16 > RVLocs ; CCState CCInfo ( CallConv , isVarArg , MF , getTargetMachine ( ) , RVLocs , Context ) ; return CCInfo . CheckReturn ( Outs , RetCC_XCore ) ; } </s>

This hook should be implemented to check whether the return values described by the Outs array can fit into the return registers .


<s> inline static int thumb1_index_register_rtx_p ( rtx x , int strict_p ) { return thumb1_base_register_rtx_p ( x , QImode , strict_p ) ; } </s>

Return nonzero if x is a legitimate index register . This is the case for any base register that can access a QImode object .


<s> bool isLittleEndian ( ) const { return DL . isLittleEndian ( ) ; } </s>

Tests whether the target triple is little endian .


<s>
virtual
const
char
*
getPassName
(
)
const
{
return
"Videocore Assembly Printer"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s>
static
void
spu_option_override
(
void
)
{
init_machine_status
=
spu_init_machine_status
;
if
(
!
flag_unroll_loops
&&
!
flag_peel_loops
)
maybe_set_param_value
(
PARAM_MAX_COMPLETELY_PEEL_TIMES
,
4
,
global_options
.
x_param_values
,
global_options_set
.
x_param_values
)
;
flag_omit_frame_pointer
=
1
;
parse_alignment_opts
(
)
;
if
(
align_functions
.
levels
[
0
]
.
get_value
(
)
<
8
)
str_align_functions
=
"8"
;
spu_hint_dist
=
8
*
4
spu_max_nops
*
4
;
if
(
spu_hint_dist
<
0
)
spu_hint_dist
=
0
;
if
(
spu_fixed_range_string
)
fix_range
(
spu_fixed_range_string
)
;
if
(
spu_arch_string
)
{
if
(
strcmp
(
&
spu_arch_string
[
0
]
,
"cell"
)
==
0
)
spu_arch
=
PROCESSOR_CELL
;
else
if
(
strcmp
(
&
spu_arch_string
[
0
]
,
"celledp"
)
==
0
)
spu_arch
=
PROCESSOR_CELLEDP
;
else
error
(
"bad value (%s) for %<-march=%> switch"
,
spu_arch_string
)
;
}
if
(
spu_tune_string
)
{
if
(
strcmp
(
&
spu_tune_string
[
0
]
,
"cell"
)
==
0
)
spu_tune
=
PROCESSOR_CELL
;
else
if
(
strcmp
(
&
spu_tune_string
[
0
]
,
"celledp"
)
==
0
)
spu_tune
=
PROCESSOR_CELLEDP
;
else
error
(
"bad value (%s) for %<-mtune=%> switch"
,
spu_tune_string
)
;
}
if
(
spu_arch
==
PROCESSOR_CELLEDP
)
{
if
(
!
(
target_flags_explicit
&
MASK_SAFE_HINTS
)
)
target_flags
&=
~
MASK_SAFE_HINTS
;
}
REAL_MODE_FORMAT
(
SFmode
)
=
&
spu_single_format
;
}
</s>


<s> void GCNPassConfig :: addPostRegAlloc ( ) { addPass ( & SIFixVGPRCopiesID ) ; if ( getOptLevel ( ) > CodeGenOpt :: None ) addPass ( & SIOptimizeExecMaskingID ) ; TargetPassConfig :: addPostRegAlloc ( ) ; } </s>

This method may be implemented by targets that want to run passes after register allocation pass pipeline but before prolog-epilog insertion .


<s> static unsigned int rx_hard_regno_nregs ( unsigned int , machine_mode mode ) { return CLASS_MAX_NREGS ( 0 , mode ) ; } </s>


"not generating patch area, nops not supported"


<s> const XCoreSubtarget * getSubtargetImpl ( const Function & ) const override { return & Subtarget ; } </s>

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .


"function attributes %qs and %qs are mutually exclusive"

"%qs handler, missing %<__vector%> prefix"

" in AVR-LibC.  Consider %<#include <avr/interrupt.h>%>"

Sanity cheching for above function attributes .


<s> unsigned M88kInstrInfo :: isStoreToStackSlot ( const MachineInstr & MI , int & FrameIndex ) const { switch ( MI . getOpcode ( ) ) { case M88k :: STrib : case M88k :: STrih : case M88k :: STriw : case M88k :: STrid : case M88k :: STrrsb : case M88k :: STrrsbt : case M88k :: STrrsbu : case M88k :: STrrsbut : case M88k :: STrrsd : case M88k :: STrrsdt : case M88k :: STrrsdu : case M88k :: STrrsdut : case M88k :: STrrsh : case M88k :: STrrsht : case M88k :: STrrshu : case M88k :: STrrshut : case M88k :: STrrsw : case M88k :: STrrswt : case M88k :: STrrswu : case M88k :: STrrswut : case M88k :: STrrub : case M88k :: STrrubt : case M88k :: STrrubu : case M88k :: STrrubut : case M88k :: STrrud : case M88k :: STrrudt : case M88k :: STrrudu : case M88k :: STrrudut : case M88k :: STrruh : case M88k :: STrruht : case M88k :: STrruhu : case M88k :: STrruhut : case M88k :: STrruw : case M88k :: STrruwt : case M88k :: STrruwu : case M88k :: STrruwut : case M88k :: STxid : case M88k :: STxis : case M88k :: STxix : case M88k :: STxrd : case M88k :: STxrdt : case M88k :: STxrdu : case M88k :: STxrdut : case M88k :: STxrss : case M88k :: STxrsst : case M88k :: STxrssu : case M88k :: STxrssut : case M88k :: STxrsx : case M88k :: STxrsxt : case M88k :: STxrsxu : case M88k :: STxrsxut : case M88k :: STxrud : case M88k :: STxrudt : case M88k :: STxrudu : case M88k :: STxrudut : case M88k :: STxrus : case M88k :: STxrust : case M88k :: STxrusu : case M88k :: STxrusut : case M88k :: STxrux : case M88k :: STxruxt : case M88k :: STxruxu : case M88k :: STxruxut : if ( MI . getOperand ( 1 ) . isFI ( ) ) { FrameIndex = MI . getOperand ( 1 ) . getIndex ( ) ; return MI . getOperand ( 0 ) . getReg ( ) ; } break ; } return 0 ; } </s>

isStoreToStackSlot - If the specified machine instruction is a direct store to a stack slot , return the virtual or physical register number of the source reg along with the FrameIndex of the loaded stack slot .


<s> void HexagonSubtarget :: adjustSchedDependency ( SUnit * Src , SUnit * Dst , SDep & Dep ) const { MachineInstr * SrcInst = Src -> getInstr ( ) ; MachineInstr * DstInst = Dst -> getInstr ( ) ; if ( ! Src -> isInstr ( ) || ! Dst -> isInstr ( ) ) return ; const HexagonInstrInfo * QII = getInstrInfo ( ) ; SmallSet < SUnit * , 4 > ExclSrc ; SmallSet < SUnit * , 4 > ExclDst ; if ( QII -> canExecuteInBundle ( * SrcInst , * DstInst ) && isBestZeroLatency ( Src , Dst , QII , ExclSrc , ExclDst ) ) { Dep . setLatency ( 0 ) ; return ; } if ( ! hasV60Ops ( ) ) return ; if ( DstInst -> isCopy ( ) ) Dep . setLatency ( 0 ) ; if ( ( DstInst -> isRegSequence ( ) || DstInst -> isCopy ( ) ) && Dst -> NumSuccs == 1 ) { unsigned DReg = DstInst -> getOperand ( 0 ) . getReg ( ) ; MachineInstr * DDst = Dst -> Succs [ 0 ] . getSUnit ( ) -> getInstr ( ) ; unsigned UseIdx = - 1 ; for ( unsigned OpNum = 0 ; OpNum < DDst -> getNumOperands ( ) ; OpNum ++ ) { const MachineOperand & MO = DDst -> getOperand ( OpNum ) ; if ( MO . isReg ( ) && MO . getReg ( ) && MO . isUse ( ) && MO . getReg ( ) == DReg ) { UseIdx = OpNum ; break ; } } int DLatency = ( InstrInfo . getOperandLatency ( & InstrItins , * SrcInst , 0 , * DDst , UseIdx ) ) ; DLatency = std :: max ( DLatency , 0 ) ; Dep . setLatency ( ( unsigned ) DLatency ) ; } ExclSrc . clear ( ) ; ExclDst . clear ( ) ; if ( EnableDotCurSched && QII -> isToBeScheduledASAP ( * SrcInst , * DstInst ) && isBestZeroLatency ( Src , Dst , QII , ExclSrc , ExclDst ) ) { Dep . setLatency ( 0 ) ; return ; } updateLatency ( * SrcInst , * DstInst , Dep ) ; } </s>

Perform target specific adjustments to the latency of a schedule dependency .


<s> std :: string MCGNode :: getLabel ( ) const { std :: string tmps ; raw_string_ostream tmp ( tmps ) ; if ( isUnknown ( ) ) tmp << "<UNKNOWN-" << * T << ">" ; else tmp << MF -> getFunction ( ) -> getName ( ) ; return tmps ; } </s>

Returns the MDNode pointer for the label .


"loadRegFromStackSlot didn't insert any code!"

restoreCalleeSavedRegisters - Issues instruction ( s ) to restore all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of load instructions via loadRegToStackSlot ( ) .


<s> bool MipsAsmParser :: ParseDirective ( AsmToken DirectiveID ) { StringRef IDVal = DirectiveID . getString ( ) ; if ( IDVal == ".ent" ) { Parser . Lex ( ) ; return false ; } if ( IDVal == ".end" ) { Parser . Lex ( ) ; return false ; } if ( IDVal == ".frame" ) { Parser . eatToEndOfStatement ( ) ; return false ; } if ( IDVal == ".set" ) { return parseDirectiveSet ( ) ; } if ( IDVal == ".fmask" ) { Parser . eatToEndOfStatement ( ) ; return false ; } if ( IDVal == ".mask" ) { Parser . eatToEndOfStatement ( ) ; return false ; } if ( IDVal == ".gpword" ) { Parser . eatToEndOfStatement ( ) ; return false ; } if ( IDVal == ".word" ) { parseDirectiveWord ( 4 , DirectiveID . getLoc ( ) ) ; return false ; } return true ; } </s>

ParseDirective - Parse a target specific assembler directive This method is deprecated , use 'parseDirective ' instead .


<s> static int visium_issue_rate ( void ) { switch ( visium_cpu ) { case PROCESSOR_GR5 : return 1 ; case PROCESSOR_GR6 : return 2 ; default : gcc_unreachable ( ) ; } } </s>

Return the number of instructions that can issue on the same cycle .


<s> WidenVector ( SelectionDAG & DAG ) : DAG ( DAG ) { } </s>

Widen the vector up to the next power of two using INSERT_SUBVECTOR .


<s> static rtx c4x_struct_value_rtx ( tree fntype ATTRIBUTE_UNUSED , int incoming ATTRIBUTE_UNUSED ) { return gen_rtx_REG ( Pmode , AR0_REGNO ) ; } </s>

Worker function for TARGET_STRUCT_VALUE_RTX .


<s> BitVector MipsRegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { static const uint16_t ReservedCPURegs [ ] = { Mips :: ZERO , Mips :: AT , Mips :: K0 , Mips :: K1 , Mips :: SP } ; static const uint16_t ReservedCPU64Regs [ ] = { Mips :: ZERO_64 , Mips :: AT_64 , Mips :: K0_64 , Mips :: K1_64 , Mips :: SP_64 } ; BitVector Reserved ( getNumRegs ( ) ) ; typedef TargetRegisterClass :: const_iterator RegIter ; for ( unsigned I = 0 ; I < array_lengthof ( ReservedCPURegs ) ; ++ I ) Reserved . set ( ReservedCPURegs [ I ] ) ; if ( Subtarget . hasMips64 ( ) ) { for ( unsigned I = 0 ; I < array_lengthof ( ReservedCPU64Regs ) ; ++ I ) Reserved . set ( ReservedCPU64Regs [ I ] ) ; for ( RegIter Reg = Mips :: AFGR64RegClass . begin ( ) , EReg = Mips :: AFGR64RegClass . end ( ) ; Reg != EReg ; ++ Reg ) Reserved . set ( * Reg ) ; } else { for ( RegIter Reg = Mips :: CPU64RegsRegClass . begin ( ) , EReg = Mips :: CPU64RegsRegClass . end ( ) ; Reg != EReg ; ++ Reg ) Reserved . set ( * Reg ) ; for ( RegIter Reg = Mips :: FGR64RegClass . begin ( ) , EReg = Mips :: FGR64RegClass . end ( ) ; Reg != EReg ; ++ Reg ) Reserved . set ( * Reg ) ; } if ( MF . getTarget ( ) . getFrameLowering ( ) -> hasFP ( MF ) ) { Reserved . set ( Mips :: FP ) ; Reserved . set ( Mips :: FP_64 ) ; } Reserved . set ( Mips :: HWR29 ) ; Reserved . set ( Mips :: HWR29_64 ) ; Reserved . set ( Mips :: DSPCtrl ) ; if ( Subtarget . inMips16Mode ( ) ) { Reserved . set ( Mips :: RA ) ; Reserved . set ( Mips :: RA_64 ) ; } if ( Subtarget . useSmallSection ( ) ) { Reserved . set ( Mips :: GP ) ; Reserved . set ( Mips :: GP_64 ) ; } return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s>
void
dump
(
)
{
errs
(
)
<<
"MSP430ISelAddressMode "
<<
this
<<
'\n'
;
if
(
BaseType
==
RegBase
&&
Base
.
Reg
.
getNode
(
)
!=
0
)
{
errs
(
)
<<
"Base.Reg "
;
Base
.
Reg
.
getNode
(
)
->
dump
(
)
;
}
else
if
(
BaseType
==
FrameIndexBase
)
{
errs
(
)
<<
" Base.FrameIndex "
<<
Base
.
FrameIndex
<<
'\n'
;
}
errs
(
)
<<
" Disp "
<<
Disp
<<
'\n'
;
if
(
GV
)
{
errs
(
)
<<
"GV "
;
GV
->
dump
(
)
;
}
else
if
(
CP
)
{
errs
(
)
<<
" CP "
;
CP
->
dump
(
)
;
errs
(
)
<<
" Align"
<<
Align
<<
'\n'
;
}
else
if
(
ES
)
{
errs
(
)
<<
"ES "
;
errs
(
)
<<
ES
<<
'\n'
;
}
else
if
(
JT
!=
1
)
errs
(
)
<<
" JT"
<<
JT
<<
" Align"
<<
Align
<<
'\n'
;
}
</s>

Dump the plan to stderr ( for debugging ) .

MSP430
"MSP430ISelAddressMode "
0
"Base.Reg "
" Base.FrameIndex "
" Disp "
"GV "
" CP "
" Align"
"ES "
1
" JT"
" Align"


<s>
static
const
struct
mips_cpu_info
*
mips_parse_cpu
(
const
char
*
cpu_string
)
{
const
struct
mips_cpu_info
*
p
;
const
char
*
s
;
for
(
s
=
cpu_string
;
*
s
!=
0
;
s
++
)
if
(
ISUPPER
(
*
s
)
)
{
warning
(
0
,
"the cpu name must be lower case"
)
;
break
;
}
if
(
strcasecmp
(
cpu_string
,
"from-abi"
)
==
0
)
return
mips_cpu_info_from_isa
(
ABI_NEEDS_32BIT_REGS
1
:
ABI_NEEDS_64BIT_REGS
3
:
(
TARGET_64BIT
3
:
1
)
)
;
if
(
strcasecmp
(
cpu_string
,
"default"
)
==
0
)
return
0
;
for
(
p
=
mips_cpu_info_table
;
p
->
name
!=
0
;
p
++
)
if
(
mips_matching_cpu_name_p
(
p
->
name
,
cpu_string
)
)
return
p
;
return
0
;
}
</s>

Return the mips_cpu_info entry for the processor or ISA given by CPU_STRING . Return null if the string is n't recognized . A similar function exists in GAS .


<s> static unsigned size ( const SpillCostAnalysisGraph & G ) { return G . getNodes ( ) . size ( ) ; } </s>

The number of name/type pairs is returned .


<s> void Cpu0SEFrameLowering :: determineCalleeSaves ( MachineFunction & MF , BitVector & SavedRegs , RegScavenger * RS ) const { TargetFrameLowering :: determineCalleeSaves ( MF , SavedRegs , RS ) ; Cpu0MachineFunctionInfo * Cpu0FI = MF . getInfo < Cpu0MachineFunctionInfo > ( ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; unsigned FP = Cpu0 :: FP ; if ( hasFP ( MF ) ) setAliasRegs ( MF , SavedRegs , FP ) ; if ( Cpu0FI -> callsEhReturn ( ) ) Cpu0FI -> createEhDataRegsFI ( ) ; if ( MF . getFrameInfo ( ) . hasCalls ( ) ) setAliasRegs ( MF , SavedRegs , Cpu0 :: LR ) ; return ; } </s>

This method determines which of the registers reported by TargetRegisterInfo : :getCalleeSavedRegs ( ) should actually get saved .


<s> MCObjectWriter * createObjectWriter ( raw_ostream & OS ) const { bool is64 = getPointerSize ( ) == 8 ; return createPPCELFObjectWriter ( OS , is64 , OSABI ) ; } </s>

Create a new MCObjectWriter instance for use by the assembler backend to emit the final object file .


"Didn't find MI in its own basic block?"

getOffsetOf - Return the current offset of the specified machine instruction from the start of the function .


<s> SDValue AArch64TargetLowering :: PerformDAGCombine ( SDNode * N , DAGCombinerInfo & DCI ) const { switch ( N -> getOpcode ( ) ) { default : break ; case ISD :: AND : return PerformANDCombine ( N , DCI ) ; case ISD :: OR : return PerformORCombine ( N , DCI , getSubtarget ( ) ) ; case ISD :: SHL : case ISD :: SRA : case ISD :: SRL : return PerformShiftCombine ( N , DCI , getSubtarget ( ) ) ; case ISD :: INTRINSIC_WO_CHAIN : return PerformIntrinsicCombine ( N , DCI . DAG ) ; } return SDValue ( ) ; } </s>

This method will be invoked for all target nodes and for any target-independent nodes that the target has registered with invoke it for .


<s> bool X86InstrInfo :: isFunctionSafeToOutlineFrom ( MachineFunction & MF , bool OutlineFromLinkOnceODRs ) const { const Function & F = MF . getFunction ( ) ; if ( ! F . hasFnAttribute ( Attribute :: NoRedZone ) ) return false ; if ( ! OutlineFromLinkOnceODRs && F . hasLinkOnceODRLinkage ( ) ) return false ; return true ; } </s>

Return true if the function can safely be outlined from .


<s> static rtx loongarch_force_temporary ( rtx dest , rtx value ) { if ( can_create_pseudo_p ( ) ) return force_reg ( Pmode , value ) ; else { loongarch_emit_move ( dest , value ) ; return dest ; } } </s>

Copy VALUE to a register and return that register . If new pseudos are allowed , copy it into a new register , otherwise use DEST .


<s>
const
char
*
emit_fusion_gpr_load
(
rtx
target
,
rtx
mem
)
{
rtx
addis_value
;
rtx
addr
;
rtx
load_offset
;
const
char
*
load_str
=
;
const
char
*
mode_name
=
;
machine_mode
mode
;
if
(
GET_CODE
(
mem
)
==
ZERO_EXTEND
)
mem
=
XEXP
(
mem
,
0
)
;
gcc_assert
(
REG_P
(
target
)
&&
MEM_P
(
mem
)
)
;
addr
=
XEXP
(
mem
,
0
)
;
fusion_split_address
(
addr
,
&
addis_value
,
&
load_offset
)
;
mode
=
GET_MODE
(
mem
)
;
switch
(
mode
)
{
case
E_QImode
:
mode_name
=
"char"
;
load_str
=
"lbz"
;
break
;
case
E_HImode
:
mode_name
=
"short"
;
load_str
=
"lhz"
;
break
;
case
E_SImode
:
case
E_SFmode
:
mode_name
=
(
mode
==
SFmode
)
"float"
:
"int"
;
load_str
=
"lwz"
;
break
;
case
E_DImode
:
case
E_DFmode
:
gcc_assert
(
TARGET_POWERPC64
)
;
mode_name
=
(
mode
==
DFmode
)
"double"
:
"long"
;
load_str
=
"ld"
;
break
;
default
:
fatal_insn
(
"Bad GPR fusion"
,
gen_rtx_SET
(
target
,
mem
)
)
;
}
emit_fusion_addis
(
target
,
addis_value
,
"gpr load fusion"
,
mode_name
)
;
emit_fusion_load_store
(
target
,
target
,
load_offset
,
load_str
)
;
return
""
;
}
</s>

Return a string to fuse an addis instruction with a gpr load to the same register that we loaded up the addis instruction . The address that is used is the logical address that was formed during peephole2 : ( lo_sum ( high ) ( low-part ) ) The code is complicated , so we call output_asm_insn directly , and just return `` '' .

powerpcspe
0
0
"char"
"lbz"
"short"
"lhz"
"float"
"int"
"lwz"
"double"
"long"
"ld"
"Bad GPR fusion"
"gpr load fusion"
""


"ADJSTACKDOWN and ADJSTACKUP should be no-ops"

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .


<s> static void shrinkToUses ( LiveInterval & LI , LiveIntervals & LIS ) { if ( LIS . shrinkToUses ( & LI ) ) { SmallVector < LiveInterval * , 4 > SplitLIs ; LIS . splitSeparateComponents ( LI , SplitLIs ) ; } } </s>

Specialized version of shrinkToUses ( LiveInterval li , SmallVectorImpl < MachineInstr > * dead ) that works on a subregister live range and only looks at uses matching the lane mask of the subregister range .


<s> static void ix86_function_specific_restore ( struct gcc_options * opts , struct cl_target_option * ptr ) { enum processor_type old_tune = ix86_tune ; enum processor_type old_arch = ix86_arch ; unsigned HOST_WIDE_INT ix86_arch_mask ; int i ; opts -> x_flag_pic = flag_pic ; ix86_arch = ( enum processor_type ) ptr -> arch ; ix86_schedule = ( enum attr_cpu ) ptr -> schedule ; ix86_tune = ( enum processor_type ) ptr -> tune ; x86_prefetch_sse = ptr -> prefetch_sse ; opts -> x_ix86_branch_cost = ptr -> branch_cost ; ix86_tune_defaulted = ptr -> tune_defaulted ; ix86_arch_specified = ptr -> arch_specified ; opts -> x_ix86_isa_flags_explicit = ptr -> x_ix86_isa_flags_explicit ; opts -> x_ix86_isa_flags2_explicit = ptr -> x_ix86_isa_flags2_explicit ; opts -> x_recip_mask_explicit = ptr -> x_recip_mask_explicit ; opts -> x_ix86_arch_string = ptr -> x_ix86_arch_string ; opts -> x_ix86_tune_string = ptr -> x_ix86_tune_string ; opts -> x_ix86_cmodel = ptr -> x_ix86_cmodel ; opts -> x_ix86_abi = ptr -> x_ix86_abi ; opts -> x_ix86_asm_dialect = ptr -> x_ix86_asm_dialect ; opts -> x_ix86_branch_cost = ptr -> x_ix86_branch_cost ; opts -> x_ix86_dump_tunes = ptr -> x_ix86_dump_tunes ; opts -> x_ix86_force_align_arg_pointer = ptr -> x_ix86_force_align_arg_pointer ; opts -> x_ix86_force_drap = ptr -> x_ix86_force_drap ; opts -> x_ix86_incoming_stack_boundary_arg = ptr -> x_ix86_incoming_stack_boundary_arg ; opts -> x_ix86_pmode = ptr -> x_ix86_pmode ; opts -> x_ix86_preferred_stack_boundary_arg = ptr -> x_ix86_preferred_stack_boundary_arg ; opts -> x_ix86_recip_name = ptr -> x_ix86_recip_name ; opts -> x_ix86_regparm = ptr -> x_ix86_regparm ; opts -> x_ix86_section_threshold = ptr -> x_ix86_section_threshold ; opts -> x_ix86_sse2avx = ptr -> x_ix86_sse2avx ; opts -> x_ix86_stack_protector_guard = ptr -> x_ix86_stack_protector_guard ; opts -> x_ix86_stringop_alg = ptr -> x_ix86_stringop_alg ; opts -> x_ix86_tls_dialect = ptr -> x_ix86_tls_dialect ; opts -> x_ix86_tune_ctrl_string = ptr -> x_ix86_tune_ctrl_string ; opts -> x_ix86_tune_memcpy_strategy = ptr -> x_ix86_tune_memcpy_strategy ; opts -> x_ix86_tune_memset_strategy = ptr -> x_ix86_tune_memset_strategy ; opts -> x_ix86_tune_no_default = ptr -> x_ix86_tune_no_default ; opts -> x_ix86_veclibabi_type = ptr -> x_ix86_veclibabi_type ; ix86_tune_cost = processor_cost_table [ ix86_tune ] ; if ( opts -> x_optimize_size ) ix86_cost = & ix86_size_cost ; else ix86_cost = ix86_tune_cost ; if ( old_arch != ix86_arch ) { ix86_arch_mask = HOST_WIDE_INT_1U << ix86_arch ; for ( i = 0 ; i < X86_ARCH_LAST ; ++ i ) ix86_arch_features [ i ] = ! ! ( initial_ix86_arch_features [ i ] & ix86_arch_mask ) ; } if ( old_tune != ix86_tune ) set_ix86_tune_features ( ix86_tune , false ) ; } </s>


<s>
const
MCFixupKindInfo
&
getFixupKindInfo
(
MCFixupKind
Kind
)
const
{
const
static
MCFixupKindInfo
Infos
[
PPC
::
NumTargetFixupKinds
]
=
{
{
"fixup_ppc_br24"
,
6
,
24
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_ppc_brcond14"
,
16
,
14
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_ppc_lo16"
,
16
,
16
,
0
}
,
{
"fixup_ppc_ha16"
,
16
,
16
,
0
}
,
{
"fixup_ppc_lo14"
,
16
,
14
,
0
}
}
;
if
(
Kind
<
FirstTargetFixupKind
)
return
TargetAsmBackend
::
getFixupKindInfo
(
Kind
)
;
assert
(
unsigned
(
Kind
FirstTargetFixupKind
)
<
getNumFixupKinds
(
)
&&
"Invalid kind!"
)
;
return
Infos
[
Kind
FirstTargetFixupKind
]
;
}
</s>


<s>
static
void
aarch64_parse_tune
(
void
)
{
const
struct
processor
*
cpu
;
char
*
str
=
(
char
*
)
alloca
(
strlen
(
aarch64_tune_string
)
+
1
)
;
strcpy
(
str
,
aarch64_tune_string
)
;
for
(
cpu
=
all_cores
;
cpu
->
name
!=
;
cpu
++
)
{
if
(
strcmp
(
cpu
->
name
,
str
)
==
0
)
{
selected_tune
=
cpu
;
return
;
}
}
error
(
"unknown value %qs for -mtune"
,
str
)
;
return
;
}
</s>


<s> const Node * getDest ( ) const { return Dest ; } </s>

Get the current destination live range .


"VLAs and dynamic stack realign, but no FP?!"

getFrameIndexReference - This method should return the base register and offset used to reference a frame index location .


Return an array that contains the bitmask target flag values and their names .

PowerPC PPC PPC "ppc-plt" "ppc-pic" "ppc-nlp" "ppc-nlp-hidden"


<s> InstructionCost getIntImmCost ( const APInt & Imm , Type * Ty , TTI :: TargetCostKind CostKind ) { assert ( Ty -> isIntegerTy ( ) ) ; unsigned BitSize = Ty -> getPrimitiveSizeInBits ( ) ; if ( BitSize == 0 ) return TTI :: TCC_Free ; if ( BitSize > 64 ) return TTI :: TCC_Free ; if ( Imm == 0 ) return TTI :: TCC_Free ; if ( isInt < 16 > ( Imm . getSExtValue ( ) ) ) return TTI :: TCC_Basic ; if ( isInt < 21 > ( Imm . getZExtValue ( ) ) ) return TTI :: TCC_Basic ; if ( isInt < 32 > ( Imm . getSExtValue ( ) ) ) { if ( ( Imm . getSExtValue ( ) & 0xFFFF ) == 0 ) return TTI :: TCC_Basic ; return 2 * TTI :: TCC_Basic ; } return 4 * TTI :: TCC_Basic ; } </s>

Calculate the cost of materializing a 64-bit value .


<s> bool RISCVMCExpr :: evaluateAsConstant ( int64_t & Res ) const { MCValue Value ; if ( Kind == VK_RISCV_PCREL_HI || Kind == VK_RISCV_PCREL_LO || Kind == VK_RISCV_GOT_HI || Kind == VK_RISCV_TPREL_HI || Kind == VK_RISCV_TPREL_LO || Kind == VK_RISCV_TPREL_ADD || Kind == VK_RISCV_TLS_GOT_HI || Kind == VK_RISCV_TLS_GD_HI || Kind == VK_RISCV_CALL || Kind == VK_RISCV_CALL_PLT ) return false ; if ( ! getSubExpr ( ) -> evaluateAsRelocatable ( Value , nullptr , nullptr ) ) return false ; if ( ! Value . isAbsolute ( ) ) return false ; Res = evaluateAsInt64 ( Value . getConstant ( ) ) ; return true ; } </s>

Evaluates the fixup as a constant value .

RISCV RISCV RISCV RISCV RISCV RISCV RISCV RISCV RISCV RISCV RISCV RISCV


<s> const ARMSubtarget * getSubtargetImpl ( ) const { return & Subtarget ; } </s>

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .


<s> static unsigned int h8300_mova_length ( rtx dest , rtx src , rtx offset ) { unsigned int size ; size = ( 2 + h8300_constant_length ( offset ) + h8300_classify_operand ( src , GET_MODE_SIZE ( GET_MODE ( src ) ) , 0 ) ) ; if ( ! REG_P ( dest ) || ! REG_P ( src ) || REGNO ( src ) != REGNO ( dest ) ) size += 2 ; return size ; } </s>

Return the length of a mova instruction with the given operands . DEST is the register destination , SRC is the source address and OFFSET is the 16-bit or 32-bit displacement .


<s> void i386_pe_seh_init ( FILE * f ) { struct seh_frame_state * seh ; if ( ! TARGET_SEH ) return ; if ( cfun -> is_thunk ) return ; gcc_assert ( ! stack_realign_drap ) ; seh = XCNEW ( struct seh_frame_state ) ; cfun -> machine -> seh = seh ; seh -> sp_offset = INCOMING_FRAME_SP_OFFSET ; seh -> cfa_offset = INCOMING_FRAME_SP_OFFSET ; seh -> cfa_reg = stack_pointer_rtx ; fputs ( "\t.seh_proc\t" , f ) ; assemble_name ( f , IDENTIFIER_POINTER ( DECL_ASSEMBLER_NAME ( cfun -> decl ) ) ) ; fputc ( '\n' , f ) ; } </s>

Set up data structures beginning output for SEH .


<s> static int loongarch_set_reg_reg_piece_cost ( machine_mode mode , unsigned int units ) { return COSTS_N_INSNS ( ( GET_MODE_SIZE ( mode ) + units - 1 ) / units ) ; } </s>

Return the cost of moving between two registers of mode MODE , assuming that the move will be in pieces of at most UNITS bytes .


<s> rtx rs6000_force_indexed_or_indirect_mem ( rtx x ) { machine_mode mode = GET_MODE ( x ) ; gcc_assert ( MEM_P ( x ) ) ; if ( can_create_pseudo_p ( ) && ! indexed_or_indirect_operand ( x , mode ) ) { rtx addr = XEXP ( x , 0 ) ; if ( GET_CODE ( addr ) == PRE_INC || GET_CODE ( addr ) == PRE_DEC ) { rtx reg = XEXP ( addr , 0 ) ; HOST_WIDE_INT size = GET_MODE_SIZE ( GET_MODE ( x ) ) ; rtx size_rtx = GEN_INT ( ( GET_CODE ( addr ) == PRE_DEC ) ? - size : size ) ; gcc_assert ( REG_P ( reg ) ) ; emit_insn ( gen_add3_insn ( reg , reg , size_rtx ) ) ; addr = reg ; } else if ( GET_CODE ( addr ) == PRE_MODIFY ) { rtx reg = XEXP ( addr , 0 ) ; rtx expr = XEXP ( addr , 1 ) ; gcc_assert ( REG_P ( reg ) ) ; gcc_assert ( GET_CODE ( expr ) == PLUS ) ; emit_insn ( gen_add3_insn ( reg , XEXP ( expr , 0 ) , XEXP ( expr , 1 ) ) ) ; addr = reg ; } if ( GET_CODE ( addr ) == PLUS ) { rtx op0 = XEXP ( addr , 0 ) ; rtx op1 = XEXP ( addr , 1 ) ; op0 = force_reg ( Pmode , op0 ) ; op1 = force_reg ( Pmode , op1 ) ; x = replace_equiv_address ( x , gen_rtx_PLUS ( Pmode , op0 , op1 ) ) ; } else x = replace_equiv_address ( x , force_reg ( Pmode , addr ) ) ; } return x ; } </s>

Given a memory reference , if it is not a reg or reg+reg addressing , convert to such a form to deal with memory reference instructions like STFIWX and LDBRX that only take reg+reg addressing .


<s> SDNode * SITargetLowering :: PostISelFolding ( MachineSDNode * Node , SelectionDAG & DAG ) const { const SIInstrInfo * TII = static_cast < const SIInstrInfo * > ( getTargetMachine ( ) . getSubtargetImpl ( ) -> getInstrInfo ( ) ) ; Node = AdjustRegClass ( Node , DAG ) ; if ( TII -> isMIMG ( Node -> getMachineOpcode ( ) ) ) adjustWritemask ( Node , DAG ) ; if ( Node -> getMachineOpcode ( ) == AMDGPU :: INSERT_SUBREG ) { legalizeTargetIndependentNode ( Node , DAG ) ; return Node ; } return legalizeOperands ( Node , DAG ) ; } </s>

Fold the instructions after selecting them .


<s> void PPCInstrInfo :: storeRegToStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , unsigned SrcReg , bool isKill , int FrameIdx , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { MachineFunction & MF = * MBB . getParent ( ) ; SmallVector < MachineInstr * , 4 > NewMIs ; if ( StoreRegToStackSlot ( MF , SrcReg , isKill , FrameIdx , RC , NewMIs ) ) { PPCFunctionInfo * FuncInfo = MF . getInfo < PPCFunctionInfo > ( ) ; FuncInfo -> setSpillsCR ( ) ; } for ( unsigned i = 0 , e = NewMIs . size ( ) ; i != e ; ++ i ) MBB . insert ( MI , NewMIs [ i ] ) ; const MachineFrameInfo & MFI = * MF . getFrameInfo ( ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( FrameIdx ) , MachineMemOperand :: MOStore , MFI . getObjectSize ( FrameIdx ) , MFI . getObjectAlignment ( FrameIdx ) ) ; NewMIs . back ( ) -> addMemOperand ( MF , MMO ) ; } </s>

Store the specified register of the given register class to the specified stack frame index .


"ERROR: Unknown type of MachineOperand: "

getMachineOpValue - Return binary encoding of operand .


<s>
bool
AAPInstrInfo
::
reverseBranchCondition
(
SmallVectorImpl
<
MachineOperand
>
&
Cond
)
const
{
assert
(
Cond
.
size
(
)
==
3
&&
"Invalid branch"
)
;
AAPCC
::
CondCode
RCC
=
reverseCondCode
(
(
AAPCC
::
CondCode
)
Cond
[
0
]
.
getImm
(
)
)
;
if
(
RCC
==
AAPCC
::
COND_INVALID
)
return
true
;
Cond
[
0
]
.
setImm
(
RCC
)
;
return
false
;
}
</s>

Reverses the branch condition of the specified condition list , returning false on success and true if it can not be reversed .


<s> bool SILowerControlFlow :: runOnMachineFunction ( MachineFunction & MF ) { const GCNSubtarget & ST = MF . getSubtarget < GCNSubtarget > ( ) ; TII = ST . getInstrInfo ( ) ; TRI = & TII -> getRegisterInfo ( ) ; LIS = getAnalysisIfAvailable < LiveIntervals > ( ) ; MRI = & MF . getRegInfo ( ) ; BoolRC = TRI -> getBoolRC ( ) ; if ( ST . isWave32 ( ) ) { AndOpc = AMDGPU :: S_AND_B32 ; OrOpc = AMDGPU :: S_OR_B32 ; XorOpc = AMDGPU :: S_XOR_B32 ; MovTermOpc = AMDGPU :: S_MOV_B32_term ; Andn2TermOpc = AMDGPU :: S_ANDN2_B32_term ; XorTermrOpc = AMDGPU :: S_XOR_B32_term ; OrSaveExecOpc = AMDGPU :: S_OR_SAVEEXEC_B32 ; Exec = AMDGPU :: EXEC_LO ; } else { AndOpc = AMDGPU :: S_AND_B64 ; OrOpc = AMDGPU :: S_OR_B64 ; XorOpc = AMDGPU :: S_XOR_B64 ; MovTermOpc = AMDGPU :: S_MOV_B64_term ; Andn2TermOpc = AMDGPU :: S_ANDN2_B64_term ; XorTermrOpc = AMDGPU :: S_XOR_B64_term ; OrSaveExecOpc = AMDGPU :: S_OR_SAVEEXEC_B64 ; Exec = AMDGPU :: EXEC ; } MachineFunction :: iterator NextBB ; for ( MachineFunction :: iterator BI = MF . begin ( ) , BE = MF . end ( ) ; BI != BE ; BI = NextBB ) { NextBB = std :: next ( BI ) ; MachineBasicBlock & MBB = * BI ; MachineBasicBlock :: iterator I , Next , Last ; for ( I = MBB . begin ( ) , Last = MBB . end ( ) ; I != MBB . end ( ) ; I = Next ) { Next = std :: next ( I ) ; MachineInstr & MI = * I ; switch ( MI . getOpcode ( ) ) { case AMDGPU :: SI_IF : emitIf ( MI ) ; break ; case AMDGPU :: SI_ELSE : emitElse ( MI ) ; break ; case AMDGPU :: SI_IF_BREAK : emitIfBreak ( MI ) ; break ; case AMDGPU :: SI_LOOP : emitLoop ( MI ) ; break ; case AMDGPU :: SI_END_CF : emitEndCf ( MI ) ; break ; case AMDGPU :: S_AND_B64 : case AMDGPU :: S_OR_B64 : case AMDGPU :: S_AND_B32 : case AMDGPU :: S_OR_B32 : combineMasks ( MI ) ; Last = I ; continue ; default : Last = I ; continue ; } Next = ( Last == MBB . end ( ) ) ? MBB . begin ( ) : Last ; } } optimizeEndCf ( ) ; LoweredEndCf . clear ( ) ; LoweredIf . clear ( ) ; return true ; } </s>

runOnMachineFunction - Emit the function body .


<s> bool X86FastISel :: tryToFoldLoadIntoMI ( MachineInstr * MI , unsigned OpNo , const LoadInst * LI ) { X86AddressMode AM ; if ( ! X86SelectAddress ( LI -> getOperand ( 0 ) , AM ) ) return false ; const X86InstrInfo & XII = ( const X86InstrInfo & ) TII ; unsigned Size = DL . getTypeAllocSize ( LI -> getType ( ) ) ; unsigned Alignment = LI -> getAlignment ( ) ; SmallVector < MachineOperand , 8 > AddrOps ; AM . getFullAddress ( AddrOps ) ; MachineInstr * Result = XII . foldMemoryOperandImpl ( * FuncInfo . MF , MI , OpNo , AddrOps , Size , Alignment ) ; if ( Result == 0 ) return false ; FuncInfo . MBB -> insert ( FuncInfo . InsertPt , Result ) ; MI -> eraseFromParent ( ) ; return true ; } </s>

The specified machine instr operand is a vreg , and that vreg is being provided by the specified load instruction .


<s> unsigned PatmosInstrInfo :: isLoadFromStackSlot ( const MachineInstr * MI , int & FrameIndex ) const { if ( MI -> getOpcode ( ) == Patmos :: LWC || MI -> getOpcode ( ) == Patmos :: LHC || MI -> getOpcode ( ) == Patmos :: LHUC || MI -> getOpcode ( ) == Patmos :: LBC || MI -> getOpcode ( ) == Patmos :: LBUC ) { if ( MI -> getOperand ( 3 ) . isFI ( ) && MI -> getOperand ( 4 ) . isImm ( ) && MI -> getOperand ( 4 ) . getImm ( ) == 0 ) { FrameIndex = MI -> getOperand ( 3 ) . getIndex ( ) ; return MI -> getOperand ( 0 ) . getReg ( ) ; } } return 0 ; } </s>

isLoadFromStackSlot - If the specified machine instruction is a direct load from a stack slot , return the virtual or physical register number of the destination along with the FrameIndex of the loaded stack slot .


<s> void TeeRISCFrameLowering :: emitEpilogue ( MachineFunction & MF , MachineBasicBlock & MBB ) const { MachineBasicBlock :: iterator MBBI = MBB . getLastNonDebugInstr ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; TeeRISCMachineFunctionInfo * TFI = MF . getInfo < TeeRISCMachineFunctionInfo > ( ) ; const TeeRISCInstrInfo & TII = * static_cast < const TeeRISCInstrInfo * > ( MF . getTarget ( ) . getInstrInfo ( ) ) ; DebugLoc dl = MBBI -> getDebugLoc ( ) ; int FPOffset = TFI -> getFPStackOffset ( ) ; int RAOffset = TFI -> getRAStackOffset ( ) ; if ( hasFP ( MF ) ) { BuildMI ( MBB , MBBI , dl , TII . get ( TeeRISC :: ADD ) , TeeRISC :: SP ) . addReg ( TeeRISC :: FP ) . addReg ( TeeRISC :: ZERO ) ; BuildMI ( MBB , MBBI , dl , TII . get ( TeeRISC :: LD ) , TeeRISC :: FP ) . addReg ( TeeRISC :: SP ) . addImm ( FPOffset ) ; } if ( MFI -> adjustsStack ( ) ) { BuildMI ( MBB , MBBI , dl , TII . get ( TeeRISC :: LD ) , TeeRISC :: LR ) . addReg ( TeeRISC :: SP ) . addImm ( RAOffset ) ; } int StackSize = ( int ) MFI -> getStackSize ( ) ; if ( StackSize ) { BuildMI ( MBB , MBBI , dl , TII . get ( TeeRISC :: ADD_IMM ) , TeeRISC :: SP ) . addReg ( TeeRISC :: SP ) . addImm ( StackSize ) ; } } </s>

TeeRISC TeeRISC TeeRISC TeeRISC TeeRISC TeeRISC TeeRISC::ADD TeeRISC::SP TeeRISC::FP TeeRISC::ZERO TeeRISC::LD TeeRISC::FP TeeRISC::SP TeeRISC::LD TeeRISC::LR TeeRISC::SP TeeRISC::ADD_IMM TeeRISC::SP TeeRISC::SP


<s> static bool fa726te_sched_adjust_cost ( rtx_insn * insn , rtx link , rtx_insn * dep , int * cost ) { if ( REG_NOTE_KIND ( link ) == REG_DEP_TRUE && recog_memoized ( insn ) >= 0 && recog_memoized ( dep ) >= 0 && get_attr_conds ( dep ) == CONDS_SET ) { if ( get_attr_conds ( insn ) == CONDS_USE && get_attr_type ( insn ) != TYPE_BRANCH ) { * cost = 3 ; return false ; } if ( GET_CODE ( PATTERN ( insn ) ) == COND_EXEC || get_attr_conds ( insn ) == CONDS_USE ) { * cost = 0 ; return false ; } } return true ; } </s>


<s> static int round_frame_size ( int size ) { return ( ( size + STACK_BOUNDARY / BITS_PER_UNIT - 1 ) & - STACK_BOUNDARY / BITS_PER_UNIT ) ; } </s>


<s>
SDValue
AVRTargetLowering
::
LowerReturn
(
SDValue
Chain
,
CallingConv
::
ID
CallConv
,
bool
isVarArg
,
const
SmallVectorImpl
<
ISD
::
OutputArg
>
&
Outs
,
const
SmallVectorImpl
<
SDValue
>
&
OutVals
,
const
SDLoc
&
dl
,
SelectionDAG
&
DAG
)
const
{
SmallVector
<
CCValAssign
,
16
>
RVLocs
;
CCState
CCInfo
(
CallConv
,
isVarArg
,
DAG
.
getMachineFunction
(
)
,
RVLocs
,
*
DAG
.
getContext
(
)
)
;
MachineFunction
&
MF
=
DAG
.
getMachineFunction
(
)
;
if
(
CallConv
==
CallingConv
::
AVR_BUILTIN
)
{
CCInfo
.
AnalyzeReturn
(
Outs
,
RetCC_AVR_BUILTIN
)
;
}
else
{
analyzeReturnValues
(
Outs
,
CCInfo
)
;
}
SDValue
Flag
;
SmallVector
<
SDValue
,
4
>
RetOps
(
1
,
Chain
)
;
for
(
unsigned
i
=
0
,
e
=
RVLocs
.
size
(
)
;
i
!=
e
;
++
i
)
{
CCValAssign
&
VA
=
RVLocs
[
i
]
;
assert
(
VA
.
isRegLoc
(
)
&&
"Can only return in registers!"
)
;
Chain
=
DAG
.
getCopyToReg
(
Chain
,
dl
,
VA
.
getLocReg
(
)
,
OutVals
[
i
]
,
Flag
)
;
Flag
=
Chain
.
getValue
(
1
)
;
RetOps
.
push_back
(
DAG
.
getRegister
(
VA
.
getLocReg
(
)
,
VA
.
getLocVT
(
)
)
)
;
}
if
(
MF
.
getFunction
(
)
.
getAttributes
(
)
.
hasFnAttr
(
Attribute
::
Naked
)
)
{
return
Chain
;
}
const
AVRMachineFunctionInfo
*
AFI
=
MF
.
getInfo
<
AVRMachineFunctionInfo
>
(
)
;
unsigned
RetOpc
=
AFI
->
isInterruptOrSignalHandler
(
)
AVRISD
::
RETI_FLAG
:
AVRISD
::
RET_FLAG
;
RetOps
[
0
]
=
Chain
;
if
(
Flag
.
getNode
(
)
)
{
RetOps
.
push_back
(
Flag
)
;
}
return
DAG
.
getNode
(
RetOpc
,
dl
,
MVT
::
Other
,
RetOps
)
;
}
</s>

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .


<s> bool SIPeepholeSDWA :: runOnMachineFunction ( MachineFunction & MF ) { const SISubtarget & ST = MF . getSubtarget < SISubtarget > ( ) ; if ( ! ST . hasSDWA ( ) || ! AMDGPU :: isVI ( ST ) ) { return false ; } MRI = & MF . getRegInfo ( ) ; TRI = ST . getRegisterInfo ( ) ; TII = ST . getInstrInfo ( ) ; std :: unordered_map < MachineInstr * , SDWAOperandsVector > PotentialMatches ; matchSDWAOperands ( MF ) ; for ( auto & OperandPair : SDWAOperands ) { auto & Operand = OperandPair . second ; MachineInstr * PotentialMI = Operand -> potentialToConvert ( TII ) ; if ( PotentialMI ) { PotentialMatches [ PotentialMI ] . push_back ( std :: move ( Operand ) ) ; } } for ( auto & PotentialPair : PotentialMatches ) { MachineInstr & PotentialMI = * PotentialPair . first ; convertToSDWA ( PotentialMI , PotentialPair . second ) ; } SDWAOperands . clear ( ) ; return false ; } </s>


"failed to spill SGPR to VGPR when allocated"

processFunctionBeforeFrameFinalized - This method is called immediately before the specified function 's frame layout ( MF.getFrameInfo ( ) ) is finalized .


<s> rtx or1k_dynamic_chain_addr ( rtx frame ) { return plus_constant ( Pmode , frame , - 2 * UNITS_PER_WORD ) ; } </s>

Worker for DYNAMIC_CHAIN_ADDRESS . Returns the RTX representing the address of where the caller 's frame pointer may be stored on the stack .


<s> bool shouldConvertConstantLoadToIntImm ( const APInt & Imm , Type * Ty ) const override { return true ; } </s>

Returns true if it is beneficial to convert a load of a constant to just the constant itself .


<s> static unsigned HOST_WIDE_INT arm_shift_truncation_mask ( enum machine_mode mode ) { return mode == SImode ? 255 : 0 ; } </s>

Implement TARGET_SHIFT_TRUNCATION_MASK . SImode shifts use normal ARM insns and therefore guarantee that the shift count is modulo 256 . DImode shifts ( those implemented by lib1funcs.asm or by optabs.c ) guarantee no particular behavior for out-of-range counts .


<s> bool PTXTargetMachine :: addInstSelector ( PassManagerBase & PM ) { PM . add ( createPTXISelDag ( * this , getOptLevel ( ) ) ) ; return false ; } </s>

addInstSelector - This method should install an instruction selector pass , which converts from LLVM code to machine instructions .


<s> inline hashval_t libcall_hasher :: hash ( const rtx_def * p1 ) { return hash_rtx ( p1 , VOIDmode , NULL , NULL , FALSE ) ; } </s>

Hash function for builtin functions with up to 3 arguments and a return type .


<s>
Register
getStackAddress
(
uint64_t
Size
,
int64_t
Offset
,
MachinePointerInfo
&
MPO
,
ISD
::
ArgFlagsTy
Flags
)
override
{
MachineFunction
&
MF
=
MIRBuilder
.
getMF
(
)
;
LLT
p0
=
LLT
::
pointer
(
0
,
64
)
;
LLT
s64
=
LLT
::
scalar
(
64
)
;
if
(
IsTailCall
)
{
assert
(
!
Flags
.
isByVal
(
)
&&
"byval unhandled with tail calls"
)
;
Offset
+=
FPDiff
;
int
FI
=
MF
.
getFrameInfo
(
)
.
CreateFixedObject
(
Size
,
Offset
,
true
)
;
auto
FIReg
=
MIRBuilder
.
buildFrameIndex
(
p0
,
FI
)
;
MPO
=
MachinePointerInfo
::
getFixedStack
(
MF
,
FI
)
;
return
FIReg
.
getReg
(
0
)
;
}
if
(
!
SPReg
)
SPReg
=
MIRBuilder
.
buildCopy
(
p0
,
Register
(
AArch64
::
SP
)
)
.
getReg
(
0
)
;
auto
OffsetReg
=
MIRBuilder
.
buildConstant
(
s64
,
Offset
)
;
auto
AddrReg
=
MIRBuilder
.
buildPtrAdd
(
p0
,
SPReg
,
OffsetReg
)
;
MPO
=
MachinePointerInfo
::
getStack
(
MF
,
Offset
)
;
return
AddrReg
.
getReg
(
0
)
;
}
</s>

Materialize a VReg containing the address of the specified stack-based object .


We precompute a number of expression trees for multiplying by constants . This generates code for such an expression tree by walking through the nodes in the tree ( which are conveniently pre-linearized ) and emitting an instruction for each one .


<s> static void csky_add_gc_roots ( void ) { gcc_obstack_init ( & minipool_obstack ) ; minipool_startobj = ( char * ) obstack_alloc ( & minipool_obstack , 0 ) ; } </s>

Allow GC scanning of the minipool obstack .


<s> bool SparcTargetLowering :: isOffsetFoldingLegal ( const GlobalAddressSDNode * GA ) const { return false ; } </s>

Return true if folding a constant offset with the given GlobalAddress is legal .


<s> static bool nonindexed_address_p ( rtx x , bool strict ) { rtx xfoo0 ; if ( REG_P ( x ) ) { if ( ! reload_in_progress || reg_equiv_mem ( REGNO ( x ) ) == 0 || indirectable_address_p ( reg_equiv_mem ( REGNO ( x ) ) , strict , false ) ) return true ; } if ( indirectable_constant_address_p ( x , false ) ) return true ; if ( indirectable_address_p ( x , strict , false ) ) return true ; xfoo0 = XEXP ( x , 0 ) ; if ( MEM_P ( x ) && indirectable_address_p ( xfoo0 , strict , true ) ) return true ; if ( ( GET_CODE ( x ) == PRE_DEC || GET_CODE ( x ) == POST_INC ) && BASE_REGISTER_P ( xfoo0 , strict ) ) return true ; return false ; } </s>

Return 1 if x is a valid address not using indexing . ( This much is the easy part . )


<s> static bool arm_memory_load_p ( rtx insn ) { rtx body , lhs , rhs ; ; if ( insn == NULL_RTX || GET_CODE ( insn ) != INSN ) return false ; body = PATTERN ( insn ) ; if ( GET_CODE ( body ) != SET ) return false ; lhs = XEXP ( body , 0 ) ; rhs = XEXP ( body , 1 ) ; lhs = REG_OR_SUBREG_RTX ( lhs ) ; if ( GET_CODE ( lhs ) != REG || REGNO_REG_CLASS ( REGNO ( lhs ) ) != GENERAL_REGS ) return false ; return ( GET_CODE ( rhs ) == MEM || GET_CODE ( rhs ) == SYMBOL_REF || note_invalid_constants ( insn , - 1 , false ) ) ; } </s>

Returns TRUE if INSN is an `` LDR REG , ADDR '' instruction . Use by the Cirrus Maverick code which has to workaround a hardware bug triggered by such instructions .


<s> static int enough_regs_for_param ( CUMULATIVE_ARGS * cum , tree type , enum machine_mode mode ) { int type_size ; int remaining_size ; if ( mode != BLKmode ) type_size = GET_MODE_BITSIZE ( mode ) ; else type_size = int_size_in_bytes ( type ) * BITS_PER_UNIT ; remaining_size = BITS_PER_WORD * ( MAX_REG_FOR_PASSING_ARGS - ( MIN_REG_FOR_PASSING_ARGS + cum -> ints ) + 1 ) ; if ( ( remaining_size >= type_size ) && ( type_size <= 2 * BITS_PER_WORD ) ) return ( type_size + BITS_PER_WORD - 1 ) / BITS_PER_WORD ; return 0 ; } </s>

If enough param regs are available for passing the param of type TYPE return * the number of registers needed else 0 .


<s> static rtx gen_frame_mem_offset ( machine_mode mode , rtx reg , int offset ) { return gen_frame_mem ( mode , gen_rtx_PLUS ( Pmode , reg , GEN_INT ( offset ) ) ) ; } </s>

Emit an offset memory reference suitable for a frame store , while converting to a valid addressing mode .


<s> bool R600InstrInfo :: expandPostRAPseudo ( MachineBasicBlock :: iterator MI ) const { switch ( MI -> getOpcode ( ) ) { default : return AMDGPUInstrInfo :: expandPostRAPseudo ( MI ) ; case AMDGPU :: R600_EXTRACT_ELT_V2 : case AMDGPU :: R600_EXTRACT_ELT_V4 : buildIndirectRead ( MI -> getParent ( ) , MI , MI -> getOperand ( 0 ) . getReg ( ) , RI . getHWRegIndex ( MI -> getOperand ( 1 ) . getReg ( ) ) , MI -> getOperand ( 2 ) . getReg ( ) , RI . getHWRegChan ( MI -> getOperand ( 1 ) . getReg ( ) ) ) ; break ; case AMDGPU :: R600_INSERT_ELT_V2 : case AMDGPU :: R600_INSERT_ELT_V4 : buildIndirectWrite ( MI -> getParent ( ) , MI , MI -> getOperand ( 2 ) . getReg ( ) , RI . getHWRegIndex ( MI -> getOperand ( 1 ) . getReg ( ) ) , MI -> getOperand ( 3 ) . getReg ( ) , RI . getHWRegChan ( MI -> getOperand ( 1 ) . getReg ( ) ) ) ; break ; } MI -> eraseFromParent ( ) ; return true ; } </s>

This function is called for all pseudo instructions that remain after register allocation .


<s> bool ARMTargetLowering :: getPreIndexedAddressParts ( SDNode * N , SDValue & Base , SDValue & Offset , ISD :: MemIndexedMode & AM , SelectionDAG & DAG ) const { if ( Subtarget -> isThumb1Only ( ) ) return false ; EVT VT ; SDValue Ptr ; bool isSEXTLoad = false ; if ( LoadSDNode * LD = dyn_cast < LoadSDNode > ( N ) ) { Ptr = LD -> getBasePtr ( ) ; VT = LD -> getMemoryVT ( ) ; isSEXTLoad = LD -> getExtensionType ( ) == ISD :: SEXTLOAD ; } else if ( StoreSDNode * ST = dyn_cast < StoreSDNode > ( N ) ) { Ptr = ST -> getBasePtr ( ) ; VT = ST -> getMemoryVT ( ) ; } else return false ; bool isInc ; bool isLegal = false ; if ( Subtarget -> isThumb2 ( ) ) isLegal = getT2IndexedAddressParts ( Ptr . getNode ( ) , VT , isSEXTLoad , Base , Offset , isInc , DAG ) ; else isLegal = getARMIndexedAddressParts ( Ptr . getNode ( ) , VT , isSEXTLoad , Base , Offset , isInc , DAG ) ; if ( ! isLegal ) return false ; AM = isInc ? ISD :: PRE_INC : ISD :: PRE_DEC ; return true ; } </s>

Returns true by value , base pointer and offset pointer and addressing mode by reference if the node 's address can be legally represented as pre-indexed load / store address .

ARM ARM ISD::MemIndexedMode ISD::SEXTLOAD ARM ISD::PRE_INC ISD::PRE_DEC


<s> void CSKYPassConfig :: addPreEmitPass ( ) { addPass ( createCSKYConstantIslandPass ( ) ) ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s> void mips_expand_call ( rtx result , rtx addr , rtx args_size , rtx aux , int sibcall_p ) { rtx orig_addr , pattern , insn ; orig_addr = addr ; if ( ! call_insn_operand ( addr , VOIDmode ) ) { addr = gen_reg_rtx ( Pmode ) ; mips_load_call_address ( addr , orig_addr , sibcall_p ) ; } if ( TARGET_MIPS16 && mips16_hard_float && build_mips16_call_stub ( result , addr , args_size , aux == 0 ? 0 : ( int ) GET_MODE ( aux ) ) ) return ; if ( result == 0 ) pattern = ( sibcall_p ? gen_sibcall_internal ( addr , args_size ) : gen_call_internal ( addr , args_size ) ) ; else if ( GET_CODE ( result ) == PARALLEL && XVECLEN ( result , 0 ) == 2 ) { rtx reg1 , reg2 ; reg1 = XEXP ( XVECEXP ( result , 0 , 0 ) , 0 ) ; reg2 = XEXP ( XVECEXP ( result , 0 , 1 ) , 0 ) ; pattern = ( sibcall_p ? gen_sibcall_value_multiple_internal ( reg1 , addr , args_size , reg2 ) : gen_call_value_multiple_internal ( reg1 , addr , args_size , reg2 ) ) ; } else pattern = ( sibcall_p ? gen_sibcall_value_internal ( result , addr , args_size ) : gen_call_value_internal ( result , addr , args_size ) ) ; insn = emit_call_insn ( pattern ) ; if ( global_got_operand ( orig_addr , VOIDmode ) ) use_reg ( & CALL_INSN_FUNCTION_USAGE ( insn ) , pic_offset_table_rtx ) ; } </s>

Expand a call or call_value instruction . RESULT is where the result will go ( null for calls ) , ADDR is the address of the function , ARGS_SIZE is the size of the arguments and AUX is the value passed to us by mips_function_arg . SIBCALL_P is true if we are expanding a sibling call , false if we 're expanding a normal call .


<s> bool X86TargetLowering :: isLegalAddressingMode ( const AddrMode & AM , const Type * Ty ) const { CodeModel :: Model M = getTargetMachine ( ) . getCodeModel ( ) ; Reloc :: Model R = getTargetMachine ( ) . getRelocationModel ( ) ; if ( ! X86 :: isOffsetSuitableForCodeModel ( AM . BaseOffs , M , AM . BaseGV != NULL ) ) return false ; if ( AM . BaseGV ) { unsigned GVFlags = Subtarget -> ClassifyGlobalReference ( AM . BaseGV , getTargetMachine ( ) ) ; if ( isGlobalStubReference ( GVFlags ) ) return false ; if ( AM . HasBaseReg && isGlobalRelativeToPICBase ( GVFlags ) ) return false ; if ( ( M != CodeModel :: Small || R != Reloc :: Static ) && Subtarget -> is64Bit ( ) && ( AM . BaseOffs || AM . Scale > 1 ) ) return false ; } switch ( AM . Scale ) { case 0 : case 1 : case 2 : case 4 : case 8 : break ; case 3 : case 5 : case 9 : if ( AM . HasBaseReg ) return false ; break ; default : return false ; } return true ; } </s>

isLegalAddressingMode - Return true if the addressing mode represented by AM is legal for this target , for a load/store of the specified type .