<s> DFAPacketizer * HexagonInstrInfo :: CreateTargetScheduleState ( const TargetMachine * TM , const ScheduleDAG * DAG ) const { const InstrItineraryData * II = TM -> getInstrItineraryData ( ) ; return TM -> getSubtarget < HexagonGenSubtargetInfo > ( ) . createDFAPacketizer ( II ) ; } </s>

Create machine specific model for scheduling .


<s> static int mn10300_adjust_sched_cost ( rtx_insn * insn , rtx link , rtx_insn * dep , int cost ) { rtx insn_set ; rtx dep_set ; int timings ; if ( ! TARGET_AM33 ) return 1 ; insn_set = single_set ( insn ) ; if ( ! insn_set ) return cost ; dep_set = single_set ( dep ) ; if ( ! dep_set ) return cost ; if ( mn10300_tune_cpu == PROCESSOR_AM34 && set_is_load_p ( dep_set ) && set_is_store_p ( insn_set ) ) cost += 1 ; else if ( mn10300_tune_cpu == PROCESSOR_AM34 && ! set_is_store_p ( insn_set ) && ! JUMP_P ( insn ) && GET_MODE_CLASS ( GET_MODE ( SET_SRC ( dep_set ) ) ) == MODE_FLOAT && GET_MODE_CLASS ( GET_MODE ( SET_SRC ( insn_set ) ) ) == MODE_FLOAT ) cost += 1 ; if ( ! TARGET_AM33_2 ) return cost ; if ( REG_NOTE_KIND ( link ) == 0 ) return cost ; if ( GET_MODE_CLASS ( GET_MODE ( SET_SRC ( dep_set ) ) ) != MODE_FLOAT ) return cost ; if ( ! set_is_load_p ( insn_set ) && ! set_is_store_p ( insn_set ) ) return cost ; if ( GET_MODE_CLASS ( GET_MODE ( SET_SRC ( insn_set ) ) ) != MODE_INT ) return cost ; timings = get_attr_timings ( insn ) ; return timings < 100 ? ( timings % 10 ) : ( timings % 100 ) ; } </s>

Update scheduling costs for situations that can not be described using the attributes and DFA machinery . DEP is the insn being scheduled . INSN is the previous insn . COST is the current cycle cost for DEP .


<s> void MipsELFStreamer :: emitLabel ( MCSymbol * Symbol , SMLoc Loc ) { MCELFStreamer :: emitLabel ( Symbol ) ; Labels . push_back ( Symbol ) ; } </s>

Emit a label for Symbol into the current section .


<s> void AMDGPUPassConfig :: addCodeGenPrepare ( ) { const AMDGPUSubtarget & ST = * getAMDGPUTargetMachine ( ) . getSubtargetImpl ( ) ; if ( ST . isPromoteAllocaEnabled ( ) ) { addPass ( createAMDGPUPromoteAlloca ( TM ) ) ; addPass ( createSROAPass ( ) ) ; } TargetPassConfig :: addCodeGenPrepare ( ) ; } </s>

Add pass to prepare the LLVM IR for code generation .


<s>
static
void
loongarch_print_float_branch_condition
(
FILE
*
file
,
enum
rtx_code
code
,
int
letter
)
{
switch
(
code
)
{
case
EQ
:
fputs
(
"ceqz"
,
file
)
;
break
;
case
NE
:
fputs
(
"cnez"
,
file
)
;
break
;
default
:
output_operand_lossage
(
"'%%%c' is not a valid operand prefix"
,
letter
)
;
break
;
}
}
</s>

loongarch
"ceqz"
"cnez"
"'%%%c' is not a valid operand prefix"


<s> static unsigned get_sew ( machine_mode mode ) { unsigned int sew = GET_MODE_CLASS ( mode ) == MODE_VECTOR_BOOL ? 8 : GET_MODE_BITSIZE ( GET_MODE_INNER ( mode ) ) ; return sew ; } </s>

Helper function to get SEW operand . We always have SEW value for all RVV instructions that have VTYPE OP .


<s> bool ARMTargetLowering :: getPreIndexedAddressParts ( SDNode * N , SDValue & Base , SDValue & Offset , ISD :: MemIndexedMode & AM , SelectionDAG & DAG ) const { if ( Subtarget -> isThumb1Only ( ) ) return false ; const bool restrict_addressing_modes_for_nacl = ( ( FlagSfiLoad && N -> getOpcode ( ) == ISD :: LOAD ) || ( FlagSfiStore && N -> getOpcode ( ) == ISD :: STORE ) ) ; if ( restrict_addressing_modes_for_nacl ) { return false ; } EVT VT ; SDValue Ptr ; bool isSEXTLoad = false ; if ( LoadSDNode * LD = dyn_cast < LoadSDNode > ( N ) ) { Ptr = LD -> getBasePtr ( ) ; VT = LD -> getMemoryVT ( ) ; isSEXTLoad = LD -> getExtensionType ( ) == ISD :: SEXTLOAD ; } else if ( StoreSDNode * ST = dyn_cast < StoreSDNode > ( N ) ) { Ptr = ST -> getBasePtr ( ) ; VT = ST -> getMemoryVT ( ) ; } else return false ; bool isInc ; bool isLegal = false ; if ( Subtarget -> isThumb2 ( ) ) isLegal = getT2IndexedAddressParts ( Ptr . getNode ( ) , VT , isSEXTLoad , Base , Offset , isInc , DAG ) ; else isLegal = getARMIndexedAddressParts ( Ptr . getNode ( ) , VT , isSEXTLoad , Base , Offset , isInc , DAG ) ; if ( ! isLegal ) return false ; AM = isInc ? ISD :: PRE_INC : ISD :: PRE_DEC ; return true ; } </s>

Returns true by value , base pointer and offset pointer and addressing mode by reference if the node 's address can be legally represented as pre-indexed load / store address .

ARM ARM ISD::MemIndexedMode ISD::LOAD ISD::STORE ISD::SEXTLOAD ARM ISD::PRE_INC ISD::PRE_DEC


<s> void m32r_init ( void ) { init_reg_tables ( ) ; memset ( m32r_punct_chars , 0 , sizeof ( m32r_punct_chars ) ) ; m32r_punct_chars [ '#' ] = 1 ; m32r_punct_chars [ '@' ] = 1 ; if ( ! OPTION_SET_P ( g_switch_value ) ) g_switch_value = SDATA_DEFAULT_SIZE ; } </s>

Called by OVERRIDE_OPTIONS to initialize various things .


"Cannot load this register from a stack slot!"

Load the specified register of the given register class from the specified stack frame index .


<s> static void mips_conditional_register_usage ( void ) { if ( ISA_HAS_DSP ) { global_regs [ CCDSP_PO_REGNUM ] = 1 ; global_regs [ CCDSP_SC_REGNUM ] = 1 ; } else accessible_reg_set &= ~ reg_class_contents [ DSP_ACC_REGS ] ; if ( ! ISA_HAS_HILO ) accessible_reg_set &= ~ reg_class_contents [ MD_REGS ] ; if ( ! TARGET_HARD_FLOAT ) accessible_reg_set &= ~ ( reg_class_contents [ FP_REGS ] | reg_class_contents [ ST_REGS ] ) ; else if ( ! ISA_HAS_8CC ) { accessible_reg_set &= ~ reg_class_contents [ ST_REGS ] ; if ( ! ISA_HAS_CCF ) SET_HARD_REG_BIT ( accessible_reg_set , FPSW_REGNUM ) ; fixed_regs [ FPSW_REGNUM ] = 1 ; } if ( TARGET_MIPS16 ) { fixed_regs [ 18 ] = 1 ; fixed_regs [ 19 ] = 1 ; fixed_regs [ 20 ] = 1 ; fixed_regs [ 21 ] = 1 ; fixed_regs [ 22 ] = 1 ; fixed_regs [ 23 ] = 1 ; fixed_regs [ 26 ] = 1 ; fixed_regs [ 27 ] = 1 ; fixed_regs [ 30 ] = 1 ; if ( optimize_size ) { fixed_regs [ 8 ] = 1 ; fixed_regs [ 9 ] = 1 ; fixed_regs [ 10 ] = 1 ; fixed_regs [ 11 ] = 1 ; fixed_regs [ 12 ] = 1 ; fixed_regs [ 13 ] = 1 ; fixed_regs [ 14 ] = 1 ; fixed_regs [ 15 ] = 1 ; } operand_reg_set &= ~ reg_class_contents [ MD_REGS ] ; } if ( mips_abi == ABI_64 ) { int regno ; for ( regno = FP_REG_FIRST + 20 ; regno < FP_REG_FIRST + 24 ; regno ++ ) call_used_regs [ regno ] = 1 ; } if ( mips_abi == ABI_N32 || ( mips_abi == ABI_32 && TARGET_FLOAT64 ) ) { int regno ; for ( regno = FP_REG_FIRST + 21 ; regno <= FP_REG_FIRST + 31 ; regno += 2 ) call_used_regs [ regno ] = 1 ; } if ( TARGET_LITTLE_ENDIAN ) { unsigned int regno ; mips_swap_registers ( MD_REG_FIRST ) ; for ( regno = DSP_ACC_REG_FIRST ; regno <= DSP_ACC_REG_LAST ; regno += 2 ) mips_swap_registers ( regno ) ; } } </s>


<s>
const
char
*
pa_output_parallel_addb
(
rtx
*
operands
,
rtx_insn
*
insn
)
{
int
length
=
get_attr_length
(
insn
)
;
if
(
operands
[
0
]
==
operands
[
1
]
)
operands
[
1
]
=
operands
[
2
]
;
if
(
length
==
4
)
return
"add%I1b,tr %1,%0,%3"
;
if
(
length
==
8
)
{
if
(
dbr_sequence_length
(
)
==
0
)
return
"b %3\n\tadd%I1 %1,%0,%0"
;
else
return
"add%I1 %1,%0,%0\n\tb %3"
;
}
output_asm_insn
(
"add%I1 %1,%0,%0"
,
operands
)
;
return
pa_output_lbranch
(
operands
[
3
]
,
insn
,
1
)
;
}
</s>

Output an unconditional add and branch insn .


"Can only insert epilog into returning blocks"


<s> void MipsSEFrameLowering :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { const MipsSEInstrInfo & TII = * static_cast < const MipsSEInstrInfo * > ( MF . getSubtarget ( ) . getInstrInfo ( ) ) ; if ( ! hasReservedCallFrame ( MF ) ) { int64_t Amount = I -> getOperand ( 0 ) . getImm ( ) ; if ( I -> getOpcode ( ) == Mips :: ADJCALLSTACKDOWN ) Amount = - Amount ; unsigned SP = STI . isABI_N64 ( ) ? Mips :: SP_64 : Mips :: SP ; TII . adjustStackPtr ( SP , Amount , MBB , I ) ; } MBB . erase ( I ) ; } </s>

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .

Mips Mips Mips Mips 0 Mips::ADJCALLSTACKDOWN Mips::SP_64 Mips::SP


<s> bool RISCVExpandCoreVHwlpPseudo :: runOnMachineFunction ( MachineFunction & MF ) { if ( ! MF . getSubtarget < RISCVSubtarget > ( ) . hasExtXCoreVHwlp ( ) ) { return false ; } MachineLoopInfo & MLI = getAnalysis < MachineLoopInfo > ( ) ; bool Changed = false ; for ( auto & ML : MLI ) { Changed |= ProcessLoop ( ML , MF ) ; } return Changed ; } </s>

runOnMachineFunction - Emit the function body .


<s>
static
void
AnalyzeArguments
(
CCState
&
State
,
SmallVectorImpl
<
CCValAssign
>
&
ArgLocs
,
const
SmallVectorImpl
<
ArgT
>
&
Args
)
{
static
const
MCPhysReg
RegList
[
]
=
{
SHUXI
::
R24
,
SHUXI
::
R25
,
SHUXI
::
R26
,
SHUXI
::
R27
,
SHUXI
::
R28
,
SHUXI
::
R29
,
SHUXI
::
R30
,
SHUXI
::
R31
}
;
static
const
MCPhysReg
RegList
[
]
=
{
SHUXI
::
R4
,
SHUXI
::
R5
,
SHUXI
::
R6
,
SHUXI
::
R7
,
SHUXI
::
R8
}
;
static
const
unsigned
NbRegs
=
array_lengthof
(
RegList
)
;
if
(
State
.
isVarArg
(
)
)
{
llvm_unreachable
(
"Cannot support var args"
)
;
}
SmallVector
<
unsigned
,
4
>
ArgsParts
;
ParseFunctionArgs
(
Args
,
ArgsParts
)
;
unsigned
RegsLeft
=
NbRegs
;
bool
UseStack
=
false
;
unsigned
ValNo
=
0
;
for
(
unsigned
i
=
0
,
e
=
ArgsParts
.
size
(
)
;
i
!=
e
;
i
++
)
{
MVT
ArgVT
=
Args
[
ValNo
]
.
VT
;
ISD
::
ArgFlagsTy
ArgFlags
=
Args
[
ValNo
]
.
Flags
;
MVT
LocVT
=
ArgVT
;
CCValAssign
::
LocInfo
LocInfo
=
CCValAssign
::
Full
;
if
(
ArgFlags
.
isByVal
(
)
)
{
State
.
HandleByVal
(
ValNo
++
,
ArgVT
,
LocVT
,
LocInfo
,
4
,
4
,
ArgFlags
)
;
continue
;
}
unsigned
Parts
=
ArgsParts
[
i
]
;
if
(
!
UseStack
&&
Parts
<=
RegsLeft
)
{
unsigned
FirstVal
=
ValNo
;
for
(
unsigned
j
=
0
;
j
<
Parts
;
j
++
)
{
unsigned
Reg
=
State
.
AllocateReg
(
RegList
)
;
State
.
addLoc
(
CCValAssign
::
getReg
(
ValNo
++
,
ArgVT
,
Reg
,
LocVT
,
LocInfo
)
)
;
RegsLeft
;
}
SmallVectorImpl
<
CCValAssign
>
::
iterator
B
=
ArgLocs
.
begin
(
)
+
FirstVal
;
std
::
reverse
(
B
,
B
+
Parts
)
;
}
else
{
UseStack
=
true
;
for
(
unsigned
j
=
0
;
j
<
Parts
;
j
++
)
CC_SHUXI
(
ValNo
++
,
ArgVT
,
LocVT
,
LocInfo
,
ArgFlags
,
State
)
;
}
}
}
</s>

The function will invoke AnalyzeCallOperands .


<s> static int getRegClass ( RegisterKind Is , unsigned RegWidth ) { if ( Is == IS_VGPR ) { switch ( RegWidth ) { default : return - 1 ; case 32 : return AMDGPU :: VGPR_32RegClassID ; case 64 : return AMDGPU :: VReg_64RegClassID ; case 96 : return AMDGPU :: VReg_96RegClassID ; case 128 : return AMDGPU :: VReg_128RegClassID ; case 160 : return AMDGPU :: VReg_160RegClassID ; case 192 : return AMDGPU :: VReg_192RegClassID ; case 224 : return AMDGPU :: VReg_224RegClassID ; case 256 : return AMDGPU :: VReg_256RegClassID ; case 512 : return AMDGPU :: VReg_512RegClassID ; case 1024 : return AMDGPU :: VReg_1024RegClassID ; } } else if ( Is == IS_TTMP ) { switch ( RegWidth ) { default : return - 1 ; case 32 : return AMDGPU :: TTMP_32RegClassID ; case 64 : return AMDGPU :: TTMP_64RegClassID ; case 128 : return AMDGPU :: TTMP_128RegClassID ; case 256 : return AMDGPU :: TTMP_256RegClassID ; case 512 : return AMDGPU :: TTMP_512RegClassID ; } } else if ( Is == IS_SGPR ) { switch ( RegWidth ) { default : return - 1 ; case 32 : return AMDGPU :: SGPR_32RegClassID ; case 64 : return AMDGPU :: SGPR_64RegClassID ; case 96 : return AMDGPU :: SGPR_96RegClassID ; case 128 : return AMDGPU :: SGPR_128RegClassID ; case 160 : return AMDGPU :: SGPR_160RegClassID ; case 192 : return AMDGPU :: SGPR_192RegClassID ; case 224 : return AMDGPU :: SGPR_224RegClassID ; case 256 : return AMDGPU :: SGPR_256RegClassID ; case 512 : return AMDGPU :: SGPR_512RegClassID ; } } else if ( Is == IS_AGPR ) { switch ( RegWidth ) { default : return - 1 ; case 32 : return AMDGPU :: AGPR_32RegClassID ; case 64 : return AMDGPU :: AReg_64RegClassID ; case 96 : return AMDGPU :: AReg_96RegClassID ; case 128 : return AMDGPU :: AReg_128RegClassID ; case 160 : return AMDGPU :: AReg_160RegClassID ; case 192 : return AMDGPU :: AReg_192RegClassID ; case 224 : return AMDGPU :: AReg_224RegClassID ; case 256 : return AMDGPU :: AReg_256RegClassID ; case 512 : return AMDGPU :: AReg_512RegClassID ; case 1024 : return AMDGPU :: AReg_1024RegClassID ; } } return - 1 ; } </s>

Given a machine instruction descriptor , returns the register class constraint for OpNum , or NULL .


<s> bool SparcTargetLowering :: IsEligibleForTailCallOptimization ( CCState & CCInfo , CallLoweringInfo & CLI , MachineFunction & MF ) const { auto & Outs = CLI . Outs ; auto & Caller = MF . getFunction ( ) ; if ( Caller . getFnAttribute ( "disable-tail-calls" ) . getValueAsString ( ) == "true" ) return false ; if ( CCInfo . getNextStackOffset ( ) != 0 ) return false ; if ( ! Outs . empty ( ) && Caller . hasStructRetAttr ( ) != Outs [ 0 ] . Flags . isSRet ( ) ) return false ; for ( auto & Arg : Outs ) if ( Arg . Flags . isByVal ( ) ) return false ; return true ; } </s>

IsEligibleForTailCallOptimization - Check whether the call is eligible for tail call optimization .

Sparc Sparc "disable-tail-calls" "true" 0 0


<s> void AGCAsmPrinter :: EmitInstruction ( const MachineInstr * MI ) { if ( emitPseudoExpansionLowering ( * OutStreamer , MI ) ) return ; MCInst TmpInst ; LowerAGCMachineInstrToMCInst ( MI , TmpInst ) ; EmitToStreamer ( * OutStreamer , TmpInst ) ; } </s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s> std :: pair < unsigned , const TargetRegisterClass * > SparcTargetLowering :: getRegForInlineAsmConstraint ( const std :: string & Constraint , MVT VT ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { case 'r' : return std :: make_pair ( 0U , & SP :: IntRegsRegClass ) ; } } return TargetLowering :: getRegForInlineAsmConstraint ( Constraint , VT ) ; } </s>

Given a physical register constraint ( e.g .


<s> void GCNPassConfig :: addPostRegAlloc ( ) { addPass ( & SIOptimizeExecMaskingID ) ; TargetPassConfig :: addPostRegAlloc ( ) ; } </s>

This method may be implemented by targets that want to run passes after register allocation pass pipeline but before prolog-epilog insertion .


"WebAssembly does not use MCFixupKindInfo flags"

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


<s> TargetTransformInfo GCNTargetMachine :: getTargetTransformInfo ( const Function & F ) const { return TargetTransformInfo ( GCNTTIImpl ( this , F ) ) ; } </s>

Get a TargetTransformInfo implementation for the target .


<s> static bool mips16_local_function_p ( const_rtx x ) { return ( GET_CODE ( x ) == SYMBOL_REF && SYMBOL_REF_LOCAL_P ( x ) && ! SYMBOL_REF_EXTERNAL_P ( x ) && ( mips_get_compress_mode ( SYMBOL_REF_DECL ( x ) ) & MASK_MIPS16 ) ) ; } </s>

Return true if function X is a locally-defined and locally-binding MIPS16 function .


<s>
void
ARMOperand
::
dump
(
raw_ostream
&
OS
)
const
{
switch
(
Kind
)
{
case
CondCode
:
OS
<<
"<ARMCC::"
<<
ARMCondCodeToString
(
getCondCode
(
)
)
<<
">"
;
break
;
case
CCOut
:
OS
<<
"<ccout "
<<
getReg
(
)
<<
">"
;
break
;
case
CoprocNum
:
OS
<<
"<coprocessor number: "
<<
getCoproc
(
)
<<
">"
;
break
;
case
CoprocReg
:
OS
<<
"<coprocessor register: "
<<
getCoproc
(
)
<<
">"
;
break
;
case
MSRMask
:
OS
<<
"<mask: "
<<
getMSRMask
(
)
<<
">"
;
break
;
case
Immediate
:
getImm
(
)
->
print
(
OS
)
;
break
;
case
MemBarrierOpt
:
OS
<<
"<ARM_MB::"
<<
MemBOptToString
(
getMemBarrierOpt
(
)
)
<<
">"
;
break
;
case
Memory
:
OS
<<
"<memory "
<<
"base:"
<<
getMemBaseRegNum
(
)
;
if
(
getMemOffsetIsReg
(
)
)
{
OS
<<
" offset:<register "
<<
getMemOffsetRegNum
(
)
;
if
(
getMemOffsetRegShifted
(
)
)
{
OS
<<
" offset-shift-type:"
<<
getMemShiftType
(
)
;
OS
<<
" offset-shift-amount:"
<<
*
getMemShiftAmount
(
)
;
}
}
else
{
OS
<<
" offset:"
<<
*
getMemOffset
(
)
;
}
if
(
getMemOffsetIsReg
(
)
)
OS
<<
" (offset-is-reg)"
;
if
(
getMemPreindexed
(
)
)
OS
<<
" (pre-indexed)"
;
if
(
getMemPostindexed
(
)
)
OS
<<
" (post-indexed)"
;
if
(
getMemNegative
(
)
)
OS
<<
" (negative)"
;
if
(
getMemWriteback
(
)
)
OS
<<
" (writeback)"
;
OS
<<
">"
;
break
;
case
ProcIFlags
:
{
OS
<<
"<ARM_PROC::"
;
unsigned
IFlags
=
getProcIFlags
(
)
;
for
(
int
i
=
2
;
i
>=
0
;
i
)
if
(
IFlags
&
(
1
<<
i
)
)
OS
<<
ARM_PROC
::
IFlagsToString
(
1
<<
i
)
;
OS
<<
">"
;
break
;
}
case
Register
:
OS
<<
"<register "
<<
getReg
(
)
<<
">"
;
break
;
case
RegisterList
:
case
DPRRegisterList
:
case
SPRRegisterList
:
{
OS
<<
"<register_list "
;
const
SmallVectorImpl
<
unsigned
>
&
RegList
=
getRegList
(
)
;
for
(
SmallVectorImpl
<
unsigned
>
::
const_iterator
I
=
RegList
.
begin
(
)
,
E
=
RegList
.
end
(
)
;
I
!=
E
;
)
{
OS
<<
*
I
;
if
(
++
I
<
E
)
OS
<<
", "
;
}
OS
<<
">"
;
break
;
}
case
Token
:
OS
<<
"'"
<<
getToken
(
)
<<
"'"
;
break
;
}
}
</s>

Dump the plan to stderr ( for debugging ) .

ARM
ARM
"<ARMCC::"
ARM
">"
"<ccout "
">"
"<coprocessor number: "
">"
"<coprocessor register: "
">"
"<mask: "
">"
"<ARM_MB::"
">"
"<memory "
"base:"
" offset:<register "
" offset-shift-type:"
" offset-shift-amount:"
" offset:"
" (offset-is-reg)"
" (pre-indexed)"
" (post-indexed)"
" (negative)"
" (writeback)"
">"
"<ARM_PROC::"
2
0
1
ARM_PROC::IFlagsToString
1
">"
"<register "
">"
"<register_list "
", "
">"
"'"
"'"


<s>
MachineBasicBlock
::
iterator
AArch64FrameLowering
::
eliminateCallFramePseudoInstr
(
MachineFunction
&
MF
,
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
)
const
{
const
AArch64InstrInfo
*
TII
=
static_cast
<
const
AArch64InstrInfo
*
>
(
MF
.
getSubtarget
(
)
.
getInstrInfo
(
)
)
;
DebugLoc
DL
=
I
->
getDebugLoc
(
)
;
unsigned
Opc
=
I
->
getOpcode
(
)
;
bool
IsDestroy
=
Opc
==
TII
->
getCallFrameDestroyOpcode
(
)
;
uint64_t
CalleePopAmount
=
IsDestroy
I
->
getOperand
(
1
)
.
getImm
(
)
:
0
;
if
(
!
hasReservedCallFrame
(
MF
)
)
{
int64_t
Amount
=
I
->
getOperand
(
0
)
.
getImm
(
)
;
Amount
=
alignTo
(
Amount
,
getStackAlign
(
)
)
;
if
(
!
IsDestroy
)
Amount
=
Amount
;
if
(
CalleePopAmount
==
0
)
{
assert
(
Amount
>
0xffffff
&&
Amount
<
0xffffff
&&
"call frame too large"
)
;
emitFrameOffset
(
MBB
,
I
,
DL
,
AArch64
::
SP
,
AArch64
::
SP
,
{
Amount
,
MVT
::
i8
}
,
TII
)
;
}
}
else
if
(
CalleePopAmount
!=
0
)
{
assert
(
CalleePopAmount
<
0xffffff
&&
"call frame too large"
)
;
emitFrameOffset
(
MBB
,
I
,
DL
,
AArch64
::
SP
,
AArch64
::
SP
,
{
(
int64_t
)
CalleePopAmount
,
MVT
::
i8
}
,
TII
)
;
}
return
MBB
.
erase
(
I
)
;
}
</s>


<s> static void arm_emit_multi_reg_pop ( unsigned long saved_regs_mask ) { int num_regs = 0 ; int i , j ; rtx par ; rtx dwarf = NULL_RTX ; rtx tmp , reg ; bool return_in_pc = saved_regs_mask & ( 1 << PC_REGNUM ) ; int offset_adj ; int emit_update ; offset_adj = return_in_pc ? 1 : 0 ; for ( i = 0 ; i <= LAST_ARM_REGNUM ; i ++ ) if ( saved_regs_mask & ( 1 << i ) ) num_regs ++ ; gcc_assert ( num_regs && num_regs <= 16 ) ; emit_update = ( saved_regs_mask & ( 1 << SP_REGNUM ) ) ? 0 : 1 ; par = gen_rtx_PARALLEL ( VOIDmode , rtvec_alloc ( num_regs + emit_update + offset_adj ) ) ; if ( return_in_pc ) XVECEXP ( par , 0 , 0 ) = ret_rtx ; if ( emit_update ) { tmp = gen_rtx_SET ( stack_pointer_rtx , plus_constant ( Pmode , stack_pointer_rtx , 4 * num_regs ) ) ; RTX_FRAME_RELATED_P ( tmp ) = 1 ; XVECEXP ( par , 0 , offset_adj ) = tmp ; } for ( j = 0 , i = 0 ; j < num_regs ; i ++ ) if ( saved_regs_mask & ( 1 << i ) ) { reg = gen_rtx_REG ( SImode , i ) ; if ( ( num_regs == 1 ) && emit_update && ! return_in_pc ) { tmp = gen_frame_mem ( SImode , gen_rtx_POST_INC ( Pmode , stack_pointer_rtx ) ) ; tmp = emit_insn ( gen_rtx_SET ( reg , tmp ) ) ; REG_NOTES ( tmp ) = alloc_reg_note ( REG_CFA_RESTORE , reg , dwarf ) ; return ; } tmp = gen_rtx_SET ( reg , gen_frame_mem ( SImode , plus_constant ( Pmode , stack_pointer_rtx , 4 * j ) ) ) ; RTX_FRAME_RELATED_P ( tmp ) = 1 ; XVECEXP ( par , 0 , j + emit_update + offset_adj ) = tmp ; if ( i != PC_REGNUM ) dwarf = alloc_reg_note ( REG_CFA_RESTORE , reg , dwarf ) ; j ++ ; } if ( return_in_pc ) par = emit_jump_insn ( par ) ; else par = emit_insn ( par ) ; REG_NOTES ( par ) = dwarf ; if ( ! return_in_pc ) arm_add_cfa_adjust_cfa_note ( par , UNITS_PER_WORD * num_regs , stack_pointer_rtx , stack_pointer_rtx ) ; } </s>

Generate and emit an insn pattern that we will recognize as a pop_multi . SAVED_REGS_MASK shows which registers need to be restored . Unfortunately , since this insn does not reflect very well the actual semantics of the operation , we need to annotate the insn for the benefit of DWARF2 frame unwind information .


<s>
bool
runOnMachineFunction
(
MachineFunction
&
MF
)
override
{
if
(
DisableAddressingModeFolder
)
return
false
;
InstrInfo
=
MF
.
getSubtarget
<
MipsSubtarget
>
(
)
.
getInstrInfo
(
)
;
bool
modified
=
false
;
MachineLoopInfo
&
MLI
=
getAnalysis
<
MachineLoopInfo
>
(
)
;
MachineDominatorTree
&
MDT
=
getAnalysis
<
MachineDominatorTree
>
(
)
;
unsigned
NumIterations
=
0
;
while
(
foldMachineFunction
(
MF
,
MLI
,
MDT
)
)
{
modified
=
true
;
NumIterations
++
;
assert
(
NumIterations
<
1000
&&
"Infinite loop in CheriAddrModeFolder?"
)
;
}
if
(
modified
)
{
MF
.
verify
(
)
;
}
return
modified
;
}
</s>


<s> static inline void aarch64_sub_sp ( rtx temp1 , rtx temp2 , poly_int64 delta , bool frame_related_p , bool emit_move_imm = true ) { aarch64_add_offset ( Pmode , stack_pointer_rtx , stack_pointer_rtx , - delta , temp1 , temp2 , frame_related_p , emit_move_imm ) ; } </s>

Subtract DELTA from the stack pointer , marking the instructions frame-related if FRAME_RELATED_P . TEMP1 is available as a temporary if nonnull .


<s> SDValue HexagonTargetLowering :: LowerCallResult ( SDValue Chain , SDValue Glue , CallingConv :: ID CallConv , bool IsVarArg , const SmallVectorImpl < ISD :: InputArg > & Ins , const SDLoc & dl , SelectionDAG & DAG , SmallVectorImpl < SDValue > & InVals , const SmallVectorImpl < SDValue > & OutVals , SDValue Callee ) const { SmallVector < CCValAssign , 16 > RVLocs ; CCState CCInfo ( CallConv , IsVarArg , DAG . getMachineFunction ( ) , RVLocs , * DAG . getContext ( ) ) ; if ( Subtarget . useHVXOps ( ) ) CCInfo . AnalyzeCallResult ( Ins , RetCC_Hexagon_HVX ) ; else CCInfo . AnalyzeCallResult ( Ins , RetCC_Hexagon ) ; for ( unsigned i = 0 ; i != RVLocs . size ( ) ; ++ i ) { SDValue RetVal ; if ( RVLocs [ i ] . getValVT ( ) == MVT :: i1 ) { auto & MRI = DAG . getMachineFunction ( ) . getRegInfo ( ) ; SDValue FR0 = DAG . getCopyFromReg ( Chain , dl , RVLocs [ i ] . getLocReg ( ) , MVT :: i32 , Glue ) ; unsigned PredR = MRI . createVirtualRegister ( & Hexagon :: PredRegsRegClass ) ; SDValue TPR = DAG . getCopyToReg ( FR0 . getValue ( 1 ) , dl , PredR , FR0 . getValue ( 0 ) , FR0 . getValue ( 2 ) ) ; RetVal = DAG . getCopyFromReg ( TPR . getValue ( 0 ) , dl , PredR , MVT :: i1 ) ; Glue = TPR . getValue ( 1 ) ; Chain = TPR . getValue ( 0 ) ; } else { RetVal = DAG . getCopyFromReg ( Chain , dl , RVLocs [ i ] . getLocReg ( ) , RVLocs [ i ] . getValVT ( ) , Glue ) ; Glue = RetVal . getValue ( 2 ) ; Chain = RetVal . getValue ( 1 ) ; } InVals . push_back ( RetVal . getValue ( 0 ) ) ; } return Chain ; } </s>

LowerCallResult - Lower the result values of an ISD : :CALL into the appropriate copies out of appropriate physical registers .


<s>
void
ARMOperand
::
dump
(
raw_ostream
&
OS
)
const
{
switch
(
Kind
)
{
case
CondCode
:
OS
<<
"<ARMCC::"
<<
ARMCondCodeToString
(
getCondCode
(
)
)
<<
">"
;
break
;
case
CCOut
:
OS
<<
"<ccout "
<<
getReg
(
)
<<
">"
;
break
;
case
CoprocNum
:
OS
<<
"<coprocessor number: "
<<
getCoproc
(
)
<<
">"
;
break
;
case
CoprocReg
:
OS
<<
"<coprocessor register: "
<<
getCoproc
(
)
<<
">"
;
break
;
case
MSRMask
:
OS
<<
"<mask: "
<<
getMSRMask
(
)
<<
">"
;
break
;
case
Immediate
:
getImm
(
)
->
print
(
OS
)
;
break
;
case
MemBarrierOpt
:
OS
<<
"<ARM_MB::"
<<
MemBOptToString
(
getMemBarrierOpt
(
)
)
<<
">"
;
break
;
case
Memory
:
OS
<<
"<memory "
<<
"base:"
<<
getMemBaseRegNum
(
)
;
if
(
getMemOffsetIsReg
(
)
)
{
OS
<<
" offset:<register "
<<
getMemOffsetRegNum
(
)
;
if
(
getMemOffsetRegShifted
(
)
)
{
OS
<<
" offset-shift-type:"
<<
getMemShiftType
(
)
;
OS
<<
" offset-shift-amount:"
<<
*
getMemShiftAmount
(
)
;
}
}
else
{
OS
<<
" offset:"
<<
*
getMemOffset
(
)
;
}
if
(
getMemOffsetIsReg
(
)
)
OS
<<
" (offset-is-reg)"
;
if
(
getMemPreindexed
(
)
)
OS
<<
" (pre-indexed)"
;
if
(
getMemPostindexed
(
)
)
OS
<<
" (post-indexed)"
;
if
(
getMemNegative
(
)
)
OS
<<
" (negative)"
;
if
(
getMemWriteback
(
)
)
OS
<<
" (writeback)"
;
OS
<<
">"
;
break
;
case
ProcIFlags
:
{
OS
<<
"<ARM_PROC::"
;
unsigned
IFlags
=
getProcIFlags
(
)
;
for
(
int
i
=
2
;
i
>=
0
;
i
)
if
(
IFlags
&
(
1
<<
i
)
)
OS
<<
ARM_PROC
::
IFlagsToString
(
1
<<
i
)
;
OS
<<
">"
;
break
;
}
case
Register
:
OS
<<
"<register "
<<
getReg
(
)
<<
">"
;
break
;
case
Shifter
:
OS
<<
"<shifter "
<<
getShiftOpcStr
(
Shift
.
ShiftTy
)
<<
">"
;
break
;
case
RegisterList
:
case
DPRRegisterList
:
case
SPRRegisterList
:
{
OS
<<
"<register_list "
;
const
SmallVectorImpl
<
unsigned
>
&
RegList
=
getRegList
(
)
;
for
(
SmallVectorImpl
<
unsigned
>
::
const_iterator
I
=
RegList
.
begin
(
)
,
E
=
RegList
.
end
(
)
;
I
!=
E
;
)
{
OS
<<
*
I
;
if
(
++
I
<
E
)
OS
<<
", "
;
}
OS
<<
">"
;
break
;
}
case
Token
:
OS
<<
"'"
<<
getToken
(
)
<<
"'"
;
break
;
}
}
</s>

ARM
ARM
"<ARMCC::"
ARM
">"
"<ccout "
">"
"<coprocessor number: "
">"
"<coprocessor register: "
">"
"<mask: "
">"
"<ARM_MB::"
">"
"<memory "
"base:"
" offset:<register "
" offset-shift-type:"
" offset-shift-amount:"
" offset:"
" (offset-is-reg)"
" (pre-indexed)"
" (post-indexed)"
" (negative)"
" (writeback)"
">"
"<ARM_PROC::"
2
0
1
ARM_PROC::IFlagsToString
1
">"
"<register "
">"
"<shifter "
">"
"<register_list "
", "
">"
"'"
"'"


<s> unsigned WebAssemblyFastISel :: fastMaterializeConstant ( const Constant * C ) { if ( const GlobalValue * GV = dyn_cast < GlobalValue > ( C ) ) { unsigned ResultReg = createResultReg ( Subtarget -> hasAddr64 ( ) ? & WebAssembly :: I64RegClass : & WebAssembly :: I32RegClass ) ; unsigned Opc = Subtarget -> hasAddr64 ( ) ? WebAssembly :: CONST_I64 : WebAssembly :: CONST_I32 ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , ResultReg ) . addGlobalAddress ( GV ) ; return ResultReg ; } return 0 ; } </s>

Emit a constant in a register using target-specific logic , such as constant pool loads .


<s> static rtx is_jump_table ( rtx insn ) { rtx table ; if ( GET_CODE ( insn ) == JUMP_INSN && JUMP_LABEL ( insn ) != NULL && ( ( table = next_real_insn ( JUMP_LABEL ( insn ) ) ) == next_real_insn ( insn ) ) && table != NULL && GET_CODE ( table ) == JUMP_INSN && ( GET_CODE ( PATTERN ( table ) ) == ADDR_VEC || GET_CODE ( PATTERN ( table ) ) == ADDR_DIFF_VEC ) ) return table ; return NULL_RTX ; } </s>

Determines if INSN is the start of a jump table . Returns the end of the TABLE or NULL_RTX .


<s> TargetPassConfig * AVRTargetMachine :: createPassConfig ( PassManagerBase & PM ) { return new AVRPassConfig ( * this , PM ) ; } </s>

Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of CodeGen passes .


<s> bool isDivergentRegClass ( const TargetRegisterClass * RC ) const override { return ! isSGPRClass ( RC ) ; } </s>

Returns true if the register class is considered divergent .


<s>
static
void
ix86_avoid_jump_misspredicts
(
void
)
{
rtx
insn
,
start
=
get_insns
(
)
;
int
nbytes
=
0
,
njumps
=
0
;
int
isjump
=
0
;
for
(
insn
=
get_insns
(
)
;
insn
;
insn
=
NEXT_INSN
(
insn
)
)
{
nbytes
+=
min_insn_size
(
insn
)
;
if
(
dump_file
)
fprintf
(
dump_file
,
"Insn %i estimated to %i bytes\n"
,
INSN_UID
(
insn
)
,
min_insn_size
(
insn
)
)
;
if
(
(
GET_CODE
(
insn
)
==
JUMP_INSN
&&
GET_CODE
(
PATTERN
(
insn
)
)
!=
ADDR_VEC
&&
GET_CODE
(
PATTERN
(
insn
)
)
!=
ADDR_DIFF_VEC
)
||
GET_CODE
(
insn
)
==
CALL_INSN
)
njumps
++
;
else
continue
;
while
(
njumps
>
3
)
{
start
=
NEXT_INSN
(
start
)
;
if
(
(
GET_CODE
(
start
)
==
JUMP_INSN
&&
GET_CODE
(
PATTERN
(
start
)
)
!=
ADDR_VEC
&&
GET_CODE
(
PATTERN
(
start
)
)
!=
ADDR_DIFF_VEC
)
||
GET_CODE
(
start
)
==
CALL_INSN
)
njumps
,
isjump
=
1
;
else
isjump
=
0
;
nbytes
-=
min_insn_size
(
start
)
;
}
gcc_assert
(
njumps
>=
0
)
;
if
(
dump_file
)
fprintf
(
dump_file
,
"Interval %i to %i has %i bytes\n"
,
INSN_UID
(
start
)
,
INSN_UID
(
insn
)
,
nbytes
)
;
if
(
njumps
==
3
&&
isjump
&&
nbytes
<
16
)
{
int
padsize
=
15
nbytes
+
min_insn_size
(
insn
)
;
if
(
dump_file
)
fprintf
(
dump_file
,
"Padding insn %i by %i bytes!\n"
,
INSN_UID
(
insn
)
,
padsize
)
;
emit_insn_before
(
gen_align
(
GEN_INT
(
padsize
)
)
,
insn
)
;
}
}
}
</s>

AMD K8 core mispredicts jumps when there are more than 3 jumps in 16 byte window .


"missing name in %<target(\"cpu=\")%> pragma or attribute"

"invalid name (\"%s\") in %<target(\"cpu=\")%> pragma or attribute"

"invalid feature modifier %s of value (\"%s\") in "

Handle the argument CPU_STR to the cpu= target attribute . PRAGMA_OR_ATTR is used in potential error messages .


<s> TargetPassConfig * LC3TargetMachine :: createPassConfig ( PassManagerBase & PM ) { return new LC3PassConfig ( this , PM ) ; } </s>


<s> void WebAssemblyAsmPrinter :: emitFunctionBodyStart ( ) { const Function & F = MF -> getFunction ( ) ; SmallVector < MVT , 1 > ResultVTs ; SmallVector < MVT , 4 > ParamVTs ; computeSignatureVTs ( F . getFunctionType ( ) , & F , F , TM , ParamVTs , ResultVTs ) ; auto Signature = signatureFromMVTs ( ResultVTs , ParamVTs ) ; auto * WasmSym = cast < MCSymbolWasm > ( CurrentFnSym ) ; WasmSym -> setSignature ( Signature . get ( ) ) ; addSignature ( std :: move ( Signature ) ) ; WasmSym -> setType ( wasm :: WASM_SYMBOL_TYPE_FUNCTION ) ; getTargetStreamer ( ) -> emitFunctionType ( WasmSym ) ; if ( MDNode * Idx = F . getMetadata ( "wasm.index" ) ) { assert ( Idx -> getNumOperands ( ) == 1 ) ; getTargetStreamer ( ) -> emitIndIdx ( AsmPrinter :: lowerConstant ( cast < ConstantAsMetadata > ( Idx -> getOperand ( 0 ) ) -> getValue ( ) ) ) ; } SmallVector < wasm :: ValType , 16 > Locals ; valTypesFromMVTs ( MFI -> getLocals ( ) , Locals ) ; getTargetStreamer ( ) -> emitLocal ( Locals ) ; AsmPrinter :: emitFunctionBodyStart ( ) ; } </s>

Targets can override this to emit stuff before the first basic block in the function .


"static IO declaration for %q+D needs an address"


<s> void push_back ( Instruction * I ) { Chain . push_back ( I ) ; } </s>

Insert a node at the back ; never copies .


<s> unsigned HSAILIntrinsicInfo :: lookupName ( const char * Name , unsigned Len ) const { return getIntrinsicForGCCBuiltin ( "HSAIL" , Name ) ; } </s>


<s> void msp430_register_pre_includes ( const char * sysroot ATTRIBUTE_UNUSED , const char * iprefix ATTRIBUTE_UNUSED , int stdinc ATTRIBUTE_UNUSED ) { char * include_dir ; if ( msp430_devices_csv_loc ) include_dir = xstrdup ( msp430_devices_csv_loc ) ; else if ( msp430_check_env_var_for_devices ( & include_dir ) ) return ; include_dir = msp430_dirname ( include_dir ) ; include_dir = update_path ( include_dir , "" ) ; add_path ( include_dir , INC_SYSTEM , false , false ) ; } </s>

If the path to the MSP430-GCC support files has been found by examining an environment variable ( see msp430_check_env_var_for_devices in msp430-devices.cc ) , or -mdevices-csv-loc= , register this path as an include directory so the user can # include msp430.h without needing to specify the path to the support files with -I .


<s> static void aarch64_pushwb_single_reg ( machine_mode mode , unsigned regno , HOST_WIDE_INT adjustment ) { rtx base_rtx = stack_pointer_rtx ; rtx insn , reg , mem ; reg = gen_rtx_REG ( mode , regno ) ; mem = gen_rtx_PRE_MODIFY ( Pmode , base_rtx , plus_constant ( Pmode , base_rtx , - adjustment ) ) ; mem = gen_frame_mem ( mode , mem ) ; insn = emit_move_insn ( mem , reg ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; } </s>

Push the register number REGNO of mode MODE to the stack with write-back adjusting the stack by ADJUSTMENT .


"Cannot relax the instruction, value does not fit"

Simple predicate for targets where ! Resolved implies requiring relaxation .


<s> static bool aarch64_array_mode_supported_p ( machine_mode mode , unsigned HOST_WIDE_INT nelems ) { if ( TARGET_SIMD && AARCH64_VALID_SIMD_QREG_MODE ( mode ) && ( nelems >= 2 && nelems <= 4 ) ) return true ; return false ; } </s>

Implement target hook TARGET_ARRAY_MODE_SUPPORTED_P .


<s>
void
AMDGPUAsmPrinter
::
EmitInstruction
(
const
MachineInstr
*
MI
)
{
const
AMDGPUSubtarget
&
STI
=
MF
->
getSubtarget
<
AMDGPUSubtarget
>
(
)
;
AMDGPUMCInstLower
MCInstLowering
(
OutContext
,
STI
)
;
StringRef
Err
;
if
(
!
STI
.
getInstrInfo
(
)
->
verifyInstruction
(
MI
,
Err
)
)
{
LLVMContext
&
C
=
MI
->
getParent
(
)
->
getParent
(
)
->
getFunction
(
)
->
getContext
(
)
;
C
.
emitError
(
"Illegal instruction detected: "
+
Err
)
;
MI
->
dump
(
)
;
}
if
(
MI
->
isBundle
(
)
)
{
const
MachineBasicBlock
*
MBB
=
MI
->
getParent
(
)
;
MachineBasicBlock
::
const_instr_iterator
I
=
++
MI
->
getIterator
(
)
;
while
(
I
!=
MBB
->
instr_end
(
)
&&
I
->
isInsideBundle
(
)
)
{
EmitInstruction
(
&
*
I
)
;
++
I
;
}
}
else
{
MCInst
TmpInst
;
MCInstLowering
.
lower
(
MI
,
TmpInst
)
;
EmitToStreamer
(
*
OutStreamer
,
TmpInst
)
;
if
(
STI
.
dumpCode
(
)
)
{
DisasmLines
.
resize
(
DisasmLines
.
size
(
)
+
1
)
;
std
::
string
&
DisasmLine
=
DisasmLines
.
back
(
)
;
raw_string_ostream
DisasmStream
(
DisasmLine
)
;
AMDGPUInstPrinter
InstPrinter
(
*
TM
.
getMCAsmInfo
(
)
,
*
MF
->
getSubtarget
(
)
.
getInstrInfo
(
)
,
*
MF
->
getSubtarget
(
)
.
getRegisterInfo
(
)
)
;
InstPrinter
.
printInst
(
&
TmpInst
,
DisasmStream
,
StringRef
(
)
,
MF
->
getSubtarget
(
)
)
;
SmallVector
<
MCFixup
,
4
>
Fixups
;
SmallVector
<
char
,
16
>
CodeBytes
;
raw_svector_ostream
CodeStream
(
CodeBytes
)
;
auto
&
ObjStreamer
=
static_cast
<
MCObjectStreamer
&
>
(
*
OutStreamer
)
;
MCCodeEmitter
&
InstEmitter
=
ObjStreamer
.
getAssembler
(
)
.
getEmitter
(
)
;
InstEmitter
.
encodeInstruction
(
TmpInst
,
CodeStream
,
Fixups
,
MF
->
getSubtarget
<
MCSubtargetInfo
>
(
)
)
;
HexLines
.
resize
(
HexLines
.
size
(
)
+
1
)
;
std
::
string
&
HexLine
=
HexLines
.
back
(
)
;
raw_string_ostream
HexStream
(
HexLine
)
;
for
(
size_t
i
=
0
;
i
<
CodeBytes
.
size
(
)
;
i
+=
4
)
{
unsigned
int
CodeDWord
=
*
(
unsigned
int
*
)
&
CodeBytes
[
i
]
;
HexStream
<<
format
(
"%s%08X"
,
(
i
>
0
" "
:
""
)
,
CodeDWord
)
;
}
DisasmStream
.
flush
(
)
;
DisasmLineMaxLen
=
std
::
max
(
DisasmLineMaxLen
,
DisasmLine
.
size
(
)
)
;
}
}
}
</s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s>
static
void
rl78_propogate_register_origins
(
void
)
{
int
origins
[
FIRST_PSEUDO_REGISTER
]
;
int
age
[
FIRST_PSEUDO_REGISTER
]
;
int
i
;
rtx_insn
*
insn
,
*
ninsn
=
;
rtx
pat
;
reset_origins
(
origins
,
age
)
;
for
(
insn
=
get_insns
(
)
;
insn
;
insn
=
ninsn
)
{
ninsn
=
next_nonnote_nondebug_insn
(
insn
)
;
if
(
dump_file
)
{
fprintf
(
dump_file
,
"\n"
)
;
fprintf
(
dump_file
,
"Origins:"
)
;
for
(
i
=
0
;
i
<
FIRST_PSEUDO_REGISTER
;
i
++
)
if
(
origins
[
i
]
!=
i
)
fprintf
(
dump_file
,
" r%d=r%d"
,
i
,
origins
[
i
]
)
;
fprintf
(
dump_file
,
"\n"
)
;
print_rtl_single
(
dump_file
,
insn
)
;
}
switch
(
GET_CODE
(
insn
)
)
{
case
CODE_LABEL
:
case
BARRIER
:
case
CALL_INSN
:
case
JUMP_INSN
:
reset_origins
(
origins
,
age
)
;
break
;
default
:
break
;
case
INSN
:
pat
=
PATTERN
(
insn
)
;
if
(
GET_CODE
(
pat
)
==
PARALLEL
)
{
rtx
clobber
=
XVECEXP
(
pat
,
0
,
1
)
;
pat
=
XVECEXP
(
pat
,
0
,
0
)
;
if
(
GET_CODE
(
clobber
)
==
CLOBBER
&&
GET_CODE
(
XEXP
(
clobber
,
0
)
)
==
REG
)
{
int
cr
=
REGNO
(
XEXP
(
clobber
,
0
)
)
;
int
mb
=
GET_MODE_SIZE
(
GET_MODE
(
XEXP
(
clobber
,
0
)
)
)
;
if
(
dump_file
)
fprintf
(
dump_file
,
"reset origins of %d regs at %d\n"
,
mb
,
cr
)
;
for
(
i
=
0
;
i
<
mb
;
i
++
)
{
origins
[
cr
+
i
]
=
cr
+
i
;
age
[
cr
+
i
]
=
0
;
}
}
else
if
(
GET_CODE
(
clobber
)
==
SET
)
{
set_origin
(
clobber
,
insn
,
origins
,
age
)
;
}
else
break
;
}
if
(
GET_CODE
(
pat
)
==
SET
)
{
set_origin
(
pat
,
insn
,
origins
,
age
)
;
}
else
if
(
GET_CODE
(
pat
)
==
CLOBBER
&&
GET_CODE
(
XEXP
(
pat
,
0
)
)
==
REG
)
{
if
(
REG_P
(
XEXP
(
pat
,
0
)
)
)
{
unsigned
int
reg
=
REGNO
(
XEXP
(
pat
,
0
)
)
;
origins
[
reg
]
=
reg
;
age
[
reg
]
=
0
;
}
}
}
}
}
</s>

The idea behind this optimization is to look for cases where we move data from A to B to C , and instead move from A to B , and A to C. If B is a virtual register or memory , this is a big win on its own . If B turns out to be unneeded after this , it 's a bigger win . For each register , we try to determine where it 's value originally came from , if it 's propogated purely through moves ( and not computes ) . The ORIGINS [ ] array has the regno for the `` origin '' of the value in the [ regno ] it 's indexed by .


<s> bool MipsPreLegalizerCombiner :: runOnMachineFunction ( MachineFunction & MF ) { if ( MF . getProperties ( ) . hasProperty ( MachineFunctionProperties :: Property :: FailedISel ) ) return false ; auto * TPC = & getAnalysis < TargetPassConfig > ( ) ; MipsPreLegalizerCombinerInfo PCInfo ; Combiner C ( PCInfo , TPC ) ; return C . combineMachineInstrs ( MF , nullptr ) ; } </s>

runOnMachineFunction - Emit the function body .


<s> PatmosTargetMachine & getTargetMachine ( ) const { return TM ; } </s>

Return the target machine ( if available ) .


<s>
unsigned
PPCVSXSwapRemoval
::
lookThruCopyLike
(
unsigned
SrcReg
,
unsigned
VecIdx
)
{
MachineInstr
*
MI
=
MRI
->
getVRegDef
(
SrcReg
)
;
if
(
!
MI
->
isCopyLike
(
)
)
return
SrcReg
;
unsigned
CopySrcReg
;
if
(
MI
->
isCopy
(
)
)
CopySrcReg
=
MI
->
getOperand
(
1
)
.
getReg
(
)
;
else
{
assert
(
MI
->
isSubregToReg
(
)
&&
"bad opcode for lookThruCopyLike"
)
;
CopySrcReg
=
MI
->
getOperand
(
2
)
.
getReg
(
)
;
}
if
(
!
Register
::
isVirtualRegister
(
CopySrcReg
)
)
{
if
(
!
isScalarVecReg
(
CopySrcReg
)
)
SwapVector
[
VecIdx
]
.
MentionsPhysVR
=
1
;
return
CopySrcReg
;
}
return
lookThruCopyLike
(
CopySrcReg
,
VecIdx
)
;
}
</s>

Returns the original SrcReg unless it is the target of a copy-like operation , in which case we chain backwards through all such operations to the ultimate source register .


<s> const uint32_t * PPCRegisterInfo :: getCallPreservedMask ( CallingConv :: ID CC ) const { if ( CC == CallingConv :: AnyReg ) { if ( Subtarget . hasVSX ( ) ) return CSR_64_AllRegs_VSX_RegMask ; if ( Subtarget . hasAltivec ( ) ) return CSR_64_AllRegs_Altivec_RegMask ; return CSR_64_AllRegs_RegMask ; } if ( Subtarget . isDarwinABI ( ) ) return Subtarget . isPPC64 ( ) ? ( Subtarget . hasAltivec ( ) ? CSR_Darwin64_Altivec_RegMask : CSR_Darwin64_RegMask ) : ( Subtarget . hasAltivec ( ) ? CSR_Darwin32_Altivec_RegMask : CSR_Darwin32_RegMask ) ; return Subtarget . isPPC64 ( ) ? ( Subtarget . hasAltivec ( ) ? CSR_SVR464_Altivec_RegMask : CSR_SVR464_RegMask ) : ( Subtarget . hasAltivec ( ) ? CSR_SVR432_Altivec_RegMask : CSR_SVR432_RegMask ) ; } </s>

Return a mask of call-preserved registers for the given calling convention on the current function .


<s>
virtual
unsigned
getReg
(
)
const
LLVM_OVERRIDE
{
assert
(
Kind
==
KindReg
&&
"Not a register"
)
;
return
Reg
.
Num
;
}
</s>

Returns the register associated with this edge .


"Not all fixup kinds added to Infos array"


<s> MCSection * getSectionForConstant ( SectionKind Kind , const Constant * C ) const override { return ReadOnlySection ; } </s>

Given a constant with the SectionKind , return a section that it should be placed in .


"selector must be an integer constant in the range 0..%wi"

Return the integer constant in ARG . Constrain it to be in the range of the subparts of VEC_TYPE ; issue an error if not .


<s> bool SITargetLowering :: mayBeEmittedAsTailCall ( const CallInst * CI ) const { if ( ! CI -> isTailCall ( ) ) return false ; const Function * ParentFn = CI -> getParent ( ) -> getParent ( ) ; if ( AMDGPU :: isEntryFunctionCC ( ParentFn -> getCallingConv ( ) ) ) return false ; auto Attr = ParentFn -> getFnAttribute ( "disable-tail-calls" ) ; return ( Attr . getValueAsString ( ) != "true" ) ; } </s>

Return true if the target may be able emit the call instruction as a tail call .

AMDGPU SI AMDGPU::isEntryFunctionCC "disable-tail-calls" "true"


<s>
void
RegisterAggr
::
print
(
raw_ostream
&
OS
)
const
{
OS
<<
'{'
;
for
(
int
U
=
Units
.
find_first
(
)
;
U
>=
0
;
U
=
Units
.
find_next
(
U
)
)
OS
<<
' '
<<
printRegUnit
(
U
,
&
PRI
.
getTRI
(
)
)
;
OS
<<
" }"
;
}
</s>

print - Print a debug representation of the operand to the given stream .


<s> static void def_builtin ( int mask , const char * name , tree type , int code ) { if ( mask & target_flags ) { if ( rs6000_builtin_decls [ code ] ) abort ( ) ; rs6000_builtin_decls [ code ] = lang_hooks . builtin_function ( name , type , code , BUILT_IN_MD , NULL , NULL_TREE ) ; } } </s>

Add a SPARC builtin function with NAME , ICODE , CODE and TYPE . Return the function decl or NULL_TREE if the builtin was not added .


<s> static bool arm_return_in_msb ( const_tree valtype ) { return ( TARGET_AAPCS_BASED && BYTES_BIG_ENDIAN && ( AGGREGATE_TYPE_P ( valtype ) || TREE_CODE ( valtype ) == COMPLEX_TYPE || FIXED_POINT_TYPE_P ( valtype ) ) ) ; } </s>

Values which must be returned in the most-significant end of the return register .


<s> void LanaiAsmBackend :: applyFixup ( const MCFixup & Fixup , char * Data , unsigned , uint64_t Value , bool , MCContext & ) const { MCFixupKind Kind = Fixup . getKind ( ) ; Value = adjustFixupValue ( static_cast < unsigned > ( Kind ) , Value ) ; if ( ! Value ) return ; unsigned Offset = Fixup . getOffset ( ) ; unsigned NumBytes = ( getFixupKindInfo ( Kind ) . TargetSize + 7 ) / 8 ; unsigned FullSize = 4 ; uint64_t CurVal = 0 ; for ( unsigned i = 0 ; i != NumBytes ; ++ i ) { unsigned Idx = ( FullSize - 1 - i ) ; CurVal |= static_cast < uint64_t > ( static_cast < uint8_t > ( Data [ Offset + Idx ] ) ) << ( i * 8 ) ; } uint64_t Mask = ( static_cast < uint64_t > ( - 1 ) >> ( 64 - getFixupKindInfo ( Kind ) . TargetSize ) ) ; CurVal |= Value & Mask ; for ( unsigned i = 0 ; i != NumBytes ; ++ i ) { unsigned Idx = ( FullSize - 1 - i ) ; Data [ Offset + Idx ] = static_cast < uint8_t > ( ( CurVal >> ( i * 8 ) ) & 0xff ) ; } } </s>

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


<s> bool runOnMachineFunction ( MachineFunction & MF ) override { TII = MF . getSubtarget < J2Subtarget > ( ) . getInstrInfo ( ) ; bool Changed = false ; for ( auto FI = MF . begin ( ) , FE = MF . end ( ) ; FI != FE ; ++ FI ) Changed |= runOnMachineBasicBlock ( * FI ) ; return Changed ; } </s>


"Can only insert epilog into returning blocks"


<s> bool BPFInstrInfo :: analyzeBranch ( MachineBasicBlock & MBB , MachineBasicBlock * & TBB , MachineBasicBlock * & FBB , SmallVectorImpl < MachineOperand > & Cond , bool AllowModify ) const { MachineBasicBlock :: iterator I = MBB . end ( ) ; while ( I != MBB . begin ( ) ) { -- I ; if ( I -> isDebugValue ( ) ) continue ; if ( ! isUnpredicatedTerminator ( * I ) ) break ; if ( ! I -> isBranch ( ) ) return true ; if ( I -> getOpcode ( ) == BPF :: JMP ) { if ( ! AllowModify ) { TBB = I -> getOperand ( 0 ) . getMBB ( ) ; continue ; } while ( std :: next ( I ) != MBB . end ( ) ) std :: next ( I ) -> eraseFromParent ( ) ; Cond . clear ( ) ; FBB = 0 ; if ( MBB . isLayoutSuccessor ( I -> getOperand ( 0 ) . getMBB ( ) ) ) { TBB = 0 ; I -> eraseFromParent ( ) ; I = MBB . end ( ) ; continue ; } TBB = I -> getOperand ( 0 ) . getMBB ( ) ; continue ; } return true ; } return false ; } </s>

analyzeBranch - Analyze the branching code at the end of MBB , returning true if it can not be understood ( e.g .


<s>
void
HexagonFrameLowering
::
processFunctionBeforeFrameFinalized
(
MachineFunction
&
MF
,
RegScavenger
*
RS
)
const
{
MachineFrameInfo
&
MFI
=
MF
.
getFrameInfo
(
)
;
bool
HasAlloca
=
MFI
.
hasVarSizedObjects
(
)
;
bool
NeedsAlign
=
(
MFI
.
getMaxAlignment
(
)
>
getStackAlignment
(
)
)
;
if
(
!
HasAlloca
||
!
NeedsAlign
)
return
;
SmallSet
<
int
,
4
>
DealignSlots
;
unsigned
LFS
=
MFI
.
getLocalFrameSize
(
)
;
for
(
int
i
=
0
,
e
=
MFI
.
getObjectIndexEnd
(
)
;
i
!=
e
;
++
i
)
{
if
(
!
MFI
.
isSpillSlotObjectIndex
(
i
)
||
MFI
.
isDeadObjectIndex
(
i
)
)
continue
;
unsigned
S
=
MFI
.
getObjectSize
(
i
)
;
unsigned
A
=
std
::
max
(
MFI
.
getObjectAlignment
(
i
)
,
8U
)
;
MFI
.
setObjectAlignment
(
i
,
8
)
;
LFS
=
alignTo
(
LFS
+
S
,
A
)
;
MFI
.
mapLocalFrameObject
(
i
,
static_cast
<
int64_t
>
(
LFS
)
)
;
DealignSlots
.
insert
(
i
)
;
}
MFI
.
setLocalFrameSize
(
LFS
)
;
Align
A
=
MFI
.
getLocalFrameMaxAlign
(
)
;
assert
(
A
<=
8
&&
"Unexpected local frame alignment"
)
;
if
(
A
==
1
)
MFI
.
setLocalFrameMaxAlign
(
Align
(
8
)
)
;
MFI
.
setUseLocalStackAllocationBlock
(
true
)
;
if
(
!
DealignSlots
.
empty
(
)
)
{
for
(
MachineBasicBlock
&
BB
:
MF
)
{
for
(
MachineInstr
&
MI
:
BB
)
{
bool
KeepOld
=
true
;
ArrayRef
<
MachineMemOperand
*
>
memops
=
MI
.
memoperands
(
)
;
SmallVector
<
MachineMemOperand
*
,
1
>
new_memops
;
for
(
MachineMemOperand
*
MMO
:
memops
)
{
auto
*
PV
=
MMO
->
getPseudoValue
(
)
;
if
(
auto
*
FS
=
dyn_cast_or_null
<
FixedStackPseudoSourceValue
>
(
PV
)
)
{
int
FI
=
FS
->
getFrameIndex
(
)
;
if
(
DealignSlots
.
count
(
FI
)
)
{
unsigned
A
=
MFI
.
getObjectAlignment
(
FI
)
;
auto
*
NewMMO
=
MF
.
getMachineMemOperand
(
MMO
->
getPointerInfo
(
)
,
MMO
->
getFlags
(
)
,
MMO
->
getSize
(
)
,
A
,
MMO
->
getAAInfo
(
)
,
MMO
->
getRanges
(
)
,
MMO
->
getSyncScopeID
(
)
,
MMO
->
getOrdering
(
)
,
MMO
->
getFailureOrdering
(
)
)
;
new_memops
.
push_back
(
NewMMO
)
;
KeepOld
=
false
;
continue
;
}
}
new_memops
.
push_back
(
MMO
)
;
}
if
(
!
KeepOld
)
MI
.
setMemRefs
(
MF
,
new_memops
)
;
}
}
}
unsigned
AP
=
0
;
if
(
const
MachineInstr
*
AI
=
getAlignaInstr
(
MF
)
)
AP
=
AI
->
getOperand
(
0
)
.
getReg
(
)
;
auto
&
HMFI
=
*
MF
.
getInfo
<
HexagonMachineFunctionInfo
>
(
)
;
HMFI
.
setStackAlignBasePhysReg
(
AP
)
;
}
</s>

processFunctionBeforeFrameFinalized - This method is called immediately before the specified function 's frame layout ( MF.getFrameInfo ( ) ) is finalized .


<s> BitVector Comet2RegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; markSuperRegs ( Reserved , Comet2 :: FR ) ; markSuperRegs ( Reserved , Comet2 :: SP ) ; assert ( checkAllSuperRegsMarked ( Reserved ) ) ; return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s> bool AArch64LoadStoreOpt :: runOnMachineFunction ( MachineFunction & Fn ) { const TargetMachine & TM = Fn . getTarget ( ) ; TII = static_cast < const AArch64InstrInfo * > ( TM . getSubtargetImpl ( ) -> getInstrInfo ( ) ) ; TRI = TM . getSubtargetImpl ( ) -> getRegisterInfo ( ) ; bool Modified = false ; for ( auto & MBB : Fn ) Modified |= optimizeBlock ( MBB ) ; return Modified ; } </s>


"Arch64 does not support GOT PC rel with extra offset"

Get the target specific PC relative GOT entry relocation .


<s> const SIRegisterInfo & getRegisterInfo ( ) const { return RI ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s> const char * HexagonTargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( Opcode ) { default : return 0 ; case HexagonISD :: CONST32 : return "HexagonISD::CONST32" ; case HexagonISD :: ADJDYNALLOC : return "HexagonISD::ADJDYNALLOC" ; case HexagonISD :: CMPICC : return "HexagonISD::CMPICC" ; case HexagonISD :: CMPFCC : return "HexagonISD::CMPFCC" ; case HexagonISD :: BRICC : return "HexagonISD::BRICC" ; case HexagonISD :: BRFCC : return "HexagonISD::BRFCC" ; case HexagonISD :: SELECT_ICC : return "HexagonISD::SELECT_ICC" ; case HexagonISD :: SELECT_FCC : return "HexagonISD::SELECT_FCC" ; case HexagonISD :: Hi : return "HexagonISD::Hi" ; case HexagonISD :: Lo : return "HexagonISD::Lo" ; case HexagonISD :: FTOI : return "HexagonISD::FTOI" ; case HexagonISD :: ITOF : return "HexagonISD::ITOF" ; case HexagonISD :: CALL : return "HexagonISD::CALL" ; case HexagonISD :: RET_FLAG : return "HexagonISD::RET_FLAG" ; case HexagonISD :: BR_JT : return "HexagonISD::BR_JT" ; case HexagonISD :: TC_RETURN : return "HexagonISD::TC_RETURN" ; } } </s>

getTargetNodeName - This method returns the name of a target specific


<s> bool MSP430InstrInfo :: isUnpredicatedTerminator ( const MachineInstr * MI ) const { const MCInstrDesc & MCID = MI -> getDesc ( ) ; if ( ! MCID . isTerminator ( ) ) return false ; if ( MCID . isBranch ( ) && ! MCID . isBarrier ( ) ) return true ; if ( ! MCID . isPredicable ( ) ) return true ; return ! isPredicated ( MI ) ; } </s>

Returns true if the instruction is a terminator instruction that has not been predicated .


<s> static void aarch64_add_constant_internal ( machine_mode mode , int regnum , int scratchreg , HOST_WIDE_INT delta , bool frame_related_p , bool emit_move_imm ) { HOST_WIDE_INT mdelta = abs_hwi ( delta ) ; rtx this_rtx = gen_rtx_REG ( mode , regnum ) ; rtx_insn * insn ; if ( ! mdelta ) return ; if ( aarch64_uimm12_shift ( mdelta ) ) { insn = emit_insn ( gen_add2_insn ( this_rtx , GEN_INT ( delta ) ) ) ; RTX_FRAME_RELATED_P ( insn ) = frame_related_p ; return ; } if ( mdelta < 0x1000000 && ! aarch64_move_imm ( mdelta , mode ) ) { HOST_WIDE_INT low_off = mdelta & 0xfff ; low_off = delta < 0 ? - low_off : low_off ; insn = emit_insn ( gen_add2_insn ( this_rtx , GEN_INT ( low_off ) ) ) ; RTX_FRAME_RELATED_P ( insn ) = frame_related_p ; insn = emit_insn ( gen_add2_insn ( this_rtx , GEN_INT ( delta - low_off ) ) ) ; RTX_FRAME_RELATED_P ( insn ) = frame_related_p ; return ; } rtx scratch_rtx = gen_rtx_REG ( mode , scratchreg ) ; if ( emit_move_imm ) aarch64_internal_mov_immediate ( scratch_rtx , GEN_INT ( mdelta ) , true , mode ) ; insn = emit_insn ( delta < 0 ? gen_sub2_insn ( this_rtx , scratch_rtx ) : gen_add2_insn ( this_rtx , scratch_rtx ) ) ; if ( frame_related_p ) { RTX_FRAME_RELATED_P ( insn ) = frame_related_p ; rtx adj = plus_constant ( mode , this_rtx , delta ) ; add_reg_note ( insn , REG_CFA_ADJUST_CFA , gen_rtx_SET ( this_rtx , adj ) ) ; } } </s>

Add DELTA to REGNUM in mode MODE . SCRATCHREG can be used to hold a temporary value if necessary . FRAME_RELATED_P should be true if the RTX_FRAME_RELATED flag should be set and CFA adjustments added to the generated instructions . If SCRATCHREG is known to hold abs ( delta ) , EMIT_MOVE_IMM can be set to false to avoid emitting the immediate again . Since this function may be used to adjust the stack pointer , we must ensure that it can not cause transient stack deallocation ( for example by first incrementing SP and then decrementing when adjusting by a large immediate ) .


<s> void riscv_expand_prologue ( void ) { struct riscv_frame_info * frame = & cfun -> machine -> frame ; HOST_WIDE_INT size = frame -> total_size ; unsigned mask = frame -> mask ; rtx insn ; if ( flag_stack_usage_info ) current_function_static_stack_size = size ; if ( riscv_use_save_libcall ( frame ) ) { rtx dwarf = NULL_RTX ; dwarf = riscv_adjust_libcall_cfi_prologue ( ) ; frame -> mask = 0 ; size -= frame -> save_libcall_adjustment ; insn = emit_insn ( gen_gpr_save ( GEN_INT ( mask ) ) ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; REG_NOTES ( insn ) = dwarf ; } if ( ( frame -> mask | frame -> fmask ) != 0 ) { HOST_WIDE_INT step1 = MIN ( size , riscv_first_stack_step ( frame ) ) ; insn = gen_add3_insn ( stack_pointer_rtx , stack_pointer_rtx , GEN_INT ( - step1 ) ) ; RTX_FRAME_RELATED_P ( emit_insn ( insn ) ) = 1 ; size -= step1 ; riscv_for_each_saved_reg ( size , riscv_save_reg ) ; } frame -> mask = mask ; if ( frame_pointer_needed ) { insn = gen_add3_insn ( hard_frame_pointer_rtx , stack_pointer_rtx , GEN_INT ( frame -> hard_frame_pointer_offset - size ) ) ; RTX_FRAME_RELATED_P ( emit_insn ( insn ) ) = 1 ; riscv_emit_stack_tie ( ) ; } if ( size > 0 ) { if ( SMALL_OPERAND ( - size ) ) { insn = gen_add3_insn ( stack_pointer_rtx , stack_pointer_rtx , GEN_INT ( - size ) ) ; RTX_FRAME_RELATED_P ( emit_insn ( insn ) ) = 1 ; } else { riscv_emit_move ( RISCV_PROLOGUE_TEMP ( Pmode ) , GEN_INT ( - size ) ) ; emit_insn ( gen_add3_insn ( stack_pointer_rtx , stack_pointer_rtx , RISCV_PROLOGUE_TEMP ( Pmode ) ) ) ; insn = plus_constant ( Pmode , stack_pointer_rtx , - size ) ; insn = gen_rtx_SET ( stack_pointer_rtx , insn ) ; riscv_set_frame_expr ( insn ) ; } } } </s>


<s>
static
void
nvptx_assemble_decl_end
(
void
)
{
if
(
decl_offset
!=
0
)
{
if
(
!
object_finished
&&
decl_offset
%
decl_chunk_size
!=
0
)
nvptx_assemble_value
(
0
,
decl_chunk_size
)
;
fprintf
(
asm_out_file
,
" }"
)
;
}
fprintf
(
asm_out_file
,
";\n"
)
;
}
</s>

Called when the initializer for a decl has been completely output through combinations of the three functions above .


Return the bytes needed to compute the frame pointer from the current stack pointer . SIZE is the size needed for local variables .


<s> bool X86TargetLowering :: combineRepeatedFPDivisors ( unsigned NumUsers ) const { return NumUsers > 1 ; } </s>

Indicate whether this target prefers to combine FDIVs with the same divisor .


<s> static int m32r_issue_rate ( ) { return ( ( TARGET_LOW_ISSUE_RATE ) ? 1 : 2 ) ; } </s>

Indicate how many instructions can be issued at the same time . This is sort of a lie . The m32r can issue only 1 long insn at once , but it can issue 2 short insns . The default therefore is set at 2 , but this can be overridden by the command line option -missue-rate=1


<s> unsigned X86TargetLowering :: getJumpTableEncoding ( ) const { if ( getTargetMachine ( ) . getRelocationModel ( ) == Reloc :: PIC_ && Subtarget . isPICStyleGOT ( ) ) return MachineJumpTableInfo :: EK_Custom32 ; return TargetLowering :: getJumpTableEncoding ( ) ; } </s>

Return the entry encoding for a jump table in the current function .


<s> static bool moxie_reg_ok_for_base_p ( const_rtx reg , bool strict_p ) { int regno = REGNO ( reg ) ; if ( strict_p ) return HARD_REGNO_OK_FOR_BASE_P ( regno ) || HARD_REGNO_OK_FOR_BASE_P ( reg_renumber [ regno ] ) ; else return ! HARD_REGISTER_NUM_P ( regno ) || HARD_REGNO_OK_FOR_BASE_P ( regno ) ; } </s>

Helper function for ` moxie_legitimate_address_p ' .


"FISC DAG->DAG Pattern Instruction Selection"

getPassName - Return a nice clean name for a pass .


<s> bool PPCGenScalarMASSEntries :: runOnModule ( Module & M ) { bool Changed = false ; auto * TPC = getAnalysisIfAvailable < TargetPassConfig > ( ) ; if ( ! TPC || skipModule ( M ) ) return false ; for ( Function & Func : M ) { if ( ! Func . isDeclaration ( ) ) continue ; auto Iter = ScalarMASSFuncs . find ( Func . getName ( ) ) ; if ( Iter == ScalarMASSFuncs . end ( ) ) continue ; SmallVector < User * , 4 > TheUsers ; for ( auto * User : Func . users ( ) ) TheUsers . push_back ( User ) ; for ( auto * User : TheUsers ) if ( auto * CI = dyn_cast_or_null < CallInst > ( User ) ) { if ( isCandidateSafeToLower ( * CI ) ) Changed |= createScalarMASSCall ( Iter -> second , * CI , Func ) ; } } return Changed ; } </s>

runOnModule - Virtual method overriden by subclasses to process the module being operated on .


<s>
StringRef
getPassName
(
)
const
override
{
return
"JVM Instruction Selection"
;
}
</s>


<s> void get_aligned_mem ( rtx ref , rtx * paligned_mem , rtx * pbitnum ) { rtx base ; HOST_WIDE_INT disp , offset ; gcc_assert ( MEM_P ( ref ) ) ; if ( reload_in_progress ) { base = find_replacement ( & XEXP ( ref , 0 ) ) ; gcc_assert ( memory_address_p ( GET_MODE ( ref ) , base ) ) ; } else base = XEXP ( ref , 0 ) ; if ( GET_CODE ( base ) == PLUS ) disp = INTVAL ( XEXP ( base , 1 ) ) , base = XEXP ( base , 0 ) ; else disp = 0 ; if ( MEM_ALIGN ( ref ) >= 32 ) offset = 0 ; else offset = disp & 3 ; gcc_assert ( offset + GET_MODE_SIZE ( GET_MODE ( ref ) ) <= GET_MODE_SIZE ( SImode ) ) ; * paligned_mem = widen_memory_access ( ref , SImode , - offset ) ; offset *= BITS_PER_UNIT ; * pbitnum = GEN_INT ( offset ) ; } </s>

REF is an alignable memory location . Place an aligned SImode reference into * PALIGNED_MEM and the number of bits to shift into * PBITNUM . SCRATCH is a free register for use in reloading out of range stack slots .


<s> unsigned AMDGPUSubtarget :: getMaxLocalMemSizeWithWaveCount ( unsigned NWaves , const Function & F ) const { if ( NWaves == 1 ) return getLocalMemorySize ( ) ; unsigned WorkGroupSize = getFlatWorkGroupSizes ( F ) . second ; unsigned WorkGroupsPerCu = getMaxWorkGroupsPerCU ( WorkGroupSize ) ; if ( ! WorkGroupsPerCu ) return 0 ; unsigned MaxWaves = getMaxWavesPerEU ( ) ; return getLocalMemorySize ( ) * MaxWaves / WorkGroupsPerCu / NWaves ; } </s>

Return the amount of LDS that can be used that will not restrict the occupancy lower than WaveCount .


<s> const MSP430InstrInfo * getInstrInfo ( ) const override { return & InstrInfo ; } </s>


<s> void SystemZMCCodeEmitter :: encodeInstruction ( const MCInst & MI , raw_ostream & OS , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { uint64_t Bits = getBinaryCodeForInstr ( MI , Fixups , STI ) ; unsigned Size = MCII . get ( MI . getOpcode ( ) ) . getSize ( ) ; unsigned ShiftValue = ( Size * 8 ) - 8 ; for ( unsigned I = 0 ; I != Size ; ++ I ) { OS << uint8_t ( Bits >> ShiftValue ) ; ShiftValue -= 8 ; } } </s>

Encode the given Inst to bytes and append to CB .


<s> unsigned CSKYInstrInfo :: isStoreToStackSlot ( const MachineInstr & MI , int & FrameIndex ) const { switch ( MI . getOpcode ( ) ) { default : return 0 ; case CSKY :: ST16B : case CSKY :: ST16H : case CSKY :: ST16W : case CSKY :: ST32B : case CSKY :: ST32H : case CSKY :: ST32W : case CSKY :: SPILL_CARRY : break ; } if ( MI . getOperand ( 1 ) . isFI ( ) && MI . getOperand ( 2 ) . isImm ( ) && MI . getOperand ( 2 ) . getImm ( ) == 0 ) { FrameIndex = MI . getOperand ( 1 ) . getIndex ( ) ; return MI . getOperand ( 0 ) . getReg ( ) ; } return 0 ; } </s>

isStoreToStackSlot - If the specified machine instruction is a direct store to a stack slot , return the virtual or physical register number of the source reg along with the FrameIndex of the loaded stack slot .


<s> static inline ChildIteratorType child_begin ( NodeType * N ) { return N -> child_begin ( ) ; } </s>

nodes_iterator/begin/end - Allow iteration over all nodes in the graph


<s> bool writeNopData ( uint64_t Count , MCObjectWriter * OW ) const override { if ( Count == 0 ) { return true ; } return false ; } </s>

Write an ( optimal ) nop sequence of Count bytes to the given output .


<s> LLVM_DUMP_METHOD void WebAssemblyException :: dump ( ) const { print ( dbgs ( ) ) ; } </s>

Dump the plan to stderr ( for debugging ) .


"Module has aliases, which NVPTX does not support."

"Module has a nontrivial global ctor, which NVPTX does not support."

"Module has a nontrivial global dtor, which NVPTX does not support."

Set up the AsmPrinter when we are working on a new module .


<s> void MBlazeInstrInfo :: storeRegToStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned SrcReg , bool isKill , int FI , const TargetRegisterClass * RC ) const { DebugLoc DL ; BuildMI ( MBB , I , DL , get ( MBlaze :: SWI ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addImm ( 0 ) . addFrameIndex ( FI ) ; } </s>

Store the specified register of the given register class to the specified stack frame index .


<s> bool SparcTargetMachine :: addPreEmitPass ( PassManagerBase & PM ) { PM . add ( createSparcFPMoverPass ( * this ) ) ; PM . add ( createSparcDelaySlotFillerPass ( * this ) ) ; return true ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s> bool Error ( SMLoc L , const Twine & Msg , ArrayRef < SMRange > Ranges = None ) { return Parser . Error ( L , Msg , Ranges ) ; } </s>

Return an error at the location L , with the message Msg .


<s> bool DCPU16Peephole :: runOnMachineFunction ( MachineFunction & MF ) { QII = static_cast < const DCPU16InstrInfo * > ( MF . getTarget ( ) . getInstrInfo ( ) ) ; QRI = static_cast < const DCPU16RegisterInfo * > ( MF . getTarget ( ) . getRegisterInfo ( ) ) ; MRI = & MF . getRegInfo ( ) ; if ( DisableDCPU16Peephole ) return false ; for ( MachineFunction :: iterator mbbIter = MF . begin ( ) ; mbbIter != MF . end ( ) ; ++ mbbIter ) { MachineBasicBlock * mbb = mbbIter ; if ( ! DisableOptBrcc ) runOptBrcc ( mbb ) ; } return true ; } </s>

runOnMachineFunction - Emit the function body .


<s> AVRSubtarget :: AVRSubtarget ( const Triple & TT , const std :: string & CPU , const std :: string & FS , const AVRTargetMachine & TM ) : AVRGenSubtargetInfo ( TT , CPU , CPU , FS ) , ELFArch ( 0 ) , m_hasSRAM ( false ) , m_hasJMPCALL ( false ) , m_hasIJMPCALL ( false ) , m_hasEIJMPCALL ( false ) , m_hasADDSUBIW ( false ) , m_hasSmallStack ( false ) , m_hasMOVW ( false ) , m_hasLPM ( false ) , m_hasLPMX ( false ) , m_hasELPM ( false ) , m_hasELPMX ( false ) , m_hasSPM ( false ) , m_hasSPMX ( false ) , m_hasDES ( false ) , m_supportsRMW ( false ) , m_supportsMultiplication ( false ) , m_hasBREAK ( false ) , m_hasTinyEncoding ( false ) , m_hasMemMappedGPR ( false ) , m_FeatureSetDummy ( false ) , InstrInfo ( ) , FrameLowering ( ) , TLInfo ( TM , initializeSubtargetDependencies ( CPU , FS , TM ) ) , TSInfo ( ) { ParseSubtargetFeatures ( CPU , CPU , FS ) ; } </s>


"Instr doesn't have FrameIndex operand!"

Returns true if the instruction 's frame index reference would be better served by a base register other than FP or SP .


"switch %<-mcustom-%s%> is required for "

"conflicting use of %<-mcustom%> switches, "

Check and signal some warnings/errors on FPU insn options .


<s> static bool use_32bit_hwmult ( void ) { static const char * cached_match = NULL ; static bool cached_result ; int i ; if ( msp430_hwmult_type == LARGE ) return true ; if ( target_mcu == NULL || msp430_hwmult_type != AUTO ) return false ; if ( target_mcu == cached_match ) return cached_result ; cached_match = target_mcu ; for ( i = ARRAY_SIZE ( msp430_mcu_data ) ; i -- ; ) if ( strcasecmp ( target_mcu , msp430_mcu_data [ i ] . name ) == 0 ) return cached_result = msp430_mcu_data [ i ] . hwmpy == 4 ; return cached_result = false ; } </s>

Returns true if the current MCU has a second generation 32-bit hardware multiplier .


<s> static struct machine_function * nios2_init_machine_status ( void ) { return ggc_cleared_alloc < machine_function > ( ) ; } </s>

Allocate a chunk of memory for per-function machine-dependent data .


<s> static void aarch64_process_components ( sbitmap components , bool prologue_p ) { rtx ptr_reg = gen_rtx_REG ( Pmode , frame_pointer_needed ? HARD_FRAME_POINTER_REGNUM : STACK_POINTER_REGNUM ) ; unsigned last_regno = SBITMAP_SIZE ( components ) ; unsigned regno = aarch64_get_next_set_bit ( components , R0_REGNUM ) ; rtx_insn * insn = NULL ; while ( regno != last_regno ) { machine_mode mode = GP_REGNUM_P ( regno ) ? E_DImode : E_DFmode ; rtx reg = gen_rtx_REG ( mode , regno ) ; poly_int64 offset = cfun -> machine -> frame . reg_offset [ regno ] ; if ( ! frame_pointer_needed ) offset += cfun -> machine -> frame . frame_size - cfun -> machine -> frame . hard_fp_offset ; rtx addr = plus_constant ( Pmode , ptr_reg , offset ) ; rtx mem = gen_frame_mem ( mode , addr ) ; rtx set = prologue_p ? gen_rtx_SET ( mem , reg ) : gen_rtx_SET ( reg , mem ) ; unsigned regno2 = aarch64_get_next_set_bit ( components , regno + 1 ) ; if ( regno2 == last_regno ) { insn = emit_insn ( set ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; if ( prologue_p ) add_reg_note ( insn , REG_CFA_OFFSET , copy_rtx ( set ) ) ; else add_reg_note ( insn , REG_CFA_RESTORE , reg ) ; break ; } poly_int64 offset2 = cfun -> machine -> frame . reg_offset [ regno2 ] ; if ( ! satisfies_constraint_Ump ( mem ) || GP_REGNUM_P ( regno ) != GP_REGNUM_P ( regno2 ) || maybe_ne ( ( offset2 - cfun -> machine -> frame . reg_offset [ regno ] ) , GET_MODE_SIZE ( mode ) ) ) { insn = emit_insn ( set ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; if ( prologue_p ) add_reg_note ( insn , REG_CFA_OFFSET , copy_rtx ( set ) ) ; else add_reg_note ( insn , REG_CFA_RESTORE , reg ) ; regno = regno2 ; continue ; } rtx reg2 = gen_rtx_REG ( mode , regno2 ) ; if ( ! frame_pointer_needed ) offset2 += cfun -> machine -> frame . frame_size - cfun -> machine -> frame . hard_fp_offset ; rtx addr2 = plus_constant ( Pmode , ptr_reg , offset2 ) ; rtx mem2 = gen_frame_mem ( mode , addr2 ) ; rtx set2 = prologue_p ? gen_rtx_SET ( mem2 , reg2 ) : gen_rtx_SET ( reg2 , mem2 ) ; if ( prologue_p ) insn = emit_insn ( aarch64_gen_store_pair ( mode , mem , reg , mem2 , reg2 ) ) ; else insn = emit_insn ( aarch64_gen_load_pair ( mode , reg , mem , reg2 , mem2 ) ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; if ( prologue_p ) { add_reg_note ( insn , REG_CFA_OFFSET , set ) ; add_reg_note ( insn , REG_CFA_OFFSET , set2 ) ; } else { add_reg_note ( insn , REG_CFA_RESTORE , reg ) ; add_reg_note ( insn , REG_CFA_RESTORE , reg2 ) ; } regno = aarch64_get_next_set_bit ( components , regno2 + 1 ) ; } } </s>

Do the work for aarch64_emit_prologue_components and aarch64_emit_epilogue_components . COMPONENTS is the bitmap of registers to save/restore , PROLOGUE_P indicates whether to emit the prologue sequence for these components or the epilogue sequence . That is , it determines whether we should emit stores or loads and what kind of CFA notes to attach to the insns . Otherwise the logic for the two sequences is very similar .


<s> BitVector SystemZRegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; const TargetFrameLowering * TFI = MF . getTarget ( ) . getFrameLowering ( ) ; if ( TFI -> hasFP ( MF ) ) { Reserved . set ( SystemZ :: R11D ) ; Reserved . set ( SystemZ :: R11L ) ; Reserved . set ( SystemZ :: R11H ) ; Reserved . set ( SystemZ :: R10Q ) ; } Reserved . set ( SystemZ :: R15D ) ; Reserved . set ( SystemZ :: R15L ) ; Reserved . set ( SystemZ :: R15H ) ; Reserved . set ( SystemZ :: R14Q ) ; return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s>
unsigned
getStackAddress
(
uint64_t
Size
,
int64_t
Offset
,
MachinePointerInfo
&
MPO
)
override
{
llvm_unreachable
(
"not implemented"
)
;
}
</s>

Materialize a VReg containing the address of the specified stack-based object .


<s>
bool
Z80oldInstrInfo
::
reverseBranchCondition
(
SmallVectorImpl
<
MachineOperand
>
&
Cond
)
const
{
assert
(
Cond
.
size
(
)
==
1
&&
"Invalid Z80old branch condition!"
)
;
Z80old
::
CondCode
CC
=
static_cast
<
Z80old
::
CondCode
>
(
Cond
[
0
]
.
getImm
(
)
)
;
Cond
[
0
]
.
setImm
(
GetOppositeBranchCondition
(
CC
)
)
;
return
false
;
}
</s>

Reverses the branch condition of the specified condition list , returning false on success and true if it can not be reversed .


<s> bool arc_scheduling_not_expected ( void ) { return cfun -> machine -> arc_reorg_started ; } </s>

Return true if the scheduling pass ( es ) has/have already run , i.e . where possible , we should try to mitigate high latencies by different instruction selection .


<s> void MipsAsmPrinter :: EmitInstruction ( const MachineInstr * MI ) { if ( MI -> isDebugValue ( ) ) { SmallString < 128 > Str ; raw_svector_ostream OS ( Str ) ; PrintDebugValueComment ( MI , OS ) ; return ; } MipsMCInstLower MCInstLowering ( Mang , * MF , * this ) ; unsigned Opc = MI -> getOpcode ( ) ; MCInst TmpInst0 ; SmallVector < MCInst , 4 > MCInsts ; MCInstLowering . Lower ( MI , TmpInst0 ) ; if ( ! OutStreamer . hasRawTextSupport ( ) && isDirective ( Opc ) ) return ; if ( isUnalignedLoadStore ( Opc ) ) { if ( OutStreamer . hasRawTextSupport ( ) ) { MCInst Directive ; Directive . setOpcode ( Mips :: MACRO ) ; OutStreamer . EmitInstruction ( Directive ) ; OutStreamer . EmitInstruction ( TmpInst0 ) ; Directive . setOpcode ( Mips :: NOMACRO ) ; OutStreamer . EmitInstruction ( Directive ) ; } else { MCInstLowering . LowerUnalignedLoadStore ( MI , MCInsts ) ; for ( SmallVector < MCInst , 4 > :: iterator I = MCInsts . begin ( ) ; I != MCInsts . end ( ) ; ++ I ) OutStreamer . EmitInstruction ( * I ) ; } return ; } if ( ! OutStreamer . hasRawTextSupport ( ) ) { if ( Opc == Mips :: CPLOAD ) MCInstLowering . LowerCPLOAD ( MI , MCInsts ) ; else if ( Opc == Mips :: CPRESTORE ) MCInstLowering . LowerCPRESTORE ( MI , MCInsts ) ; if ( ! MCInsts . empty ( ) ) { for ( SmallVector < MCInst , 4 > :: iterator I = MCInsts . begin ( ) ; I != MCInsts . end ( ) ; ++ I ) OutStreamer . EmitInstruction ( * I ) ; return ; } } OutStreamer . EmitInstruction ( TmpInst0 ) ; } </s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s> bool ARMPreAllocLoadStoreOpt :: runOnMachineFunction ( MachineFunction & Fn ) { if ( AssumeMisalignedLoadStores || skipFunction ( Fn . getFunction ( ) ) ) return false ; TD = & Fn . getDataLayout ( ) ; STI = & Fn . getSubtarget < ARMSubtarget > ( ) ; TII = STI -> getInstrInfo ( ) ; TRI = STI -> getRegisterInfo ( ) ; MRI = & Fn . getRegInfo ( ) ; DT = & getAnalysis < MachineDominatorTree > ( ) ; MF = & Fn ; AA = & getAnalysis < AAResultsWrapperPass > ( ) . getAAResults ( ) ; bool Modified = DistributeIncrements ( ) ; for ( MachineBasicBlock & MFI : Fn ) Modified |= RescheduleLoadStoreInstrs ( & MFI ) ; return Modified ; } </s>


<s> Register PPCRegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { const PPCFrameLowering * TFI = getFrameLowering ( MF ) ; if ( ! TM . isPPC64 ( ) ) return TFI -> hasFP ( MF ) ? PPC :: R31 : PPC :: R1 ; else return TFI -> hasFP ( MF ) ? PPC :: X31 : PPC :: X1 ; } </s>


<s>
void
X86AsmPrinter
::
printPCRelImm
(
const
MachineInstr
*
MI
,
unsigned
OpNo
,
raw_ostream
&
O
)
{
const
MachineOperand
&
MO
=
MI
->
getOperand
(
OpNo
)
;
switch
(
MO
.
getType
(
)
)
{
default
:
llvm_unreachable
(
"Unknown pcrel immediate operand"
)
;
case
MachineOperand
::
MO_Register
:
printOperand
(
MI
,
OpNo
,
O
)
;
return
;
case
MachineOperand
::
MO_Immediate
:
O
<<
MO
.
getImm
(
)
;
return
;
case
MachineOperand
::
MO_MachineBasicBlock
:
O
<<
*
MO
.
getMBB
(
)
->
getSymbol
(
)
;
return
;
case
MachineOperand
::
MO_GlobalAddress
:
case
MachineOperand
::
MO_ExternalSymbol
:
printSymbolOperand
(
MO
,
O
)
;
return
;
}
}
</s>


<s> static bool ix86_modes_tieable_p ( machine_mode mode1 , machine_mode mode2 ) { if ( mode1 == mode2 ) return true ; if ( ix86_tieable_integer_mode_p ( mode1 ) && ix86_tieable_integer_mode_p ( mode2 ) ) return true ; if ( mode2 == XFmode ) return mode1 == SFmode || mode1 == DFmode ; if ( mode2 == DFmode ) return mode1 == SFmode ; if ( GET_MODE_SIZE ( mode2 ) == 64 && ix86_hard_regno_mode_ok ( FIRST_SSE_REG , mode2 ) ) return ( GET_MODE_SIZE ( mode1 ) == 64 && ix86_hard_regno_mode_ok ( FIRST_SSE_REG , mode1 ) ) ; if ( GET_MODE_SIZE ( mode2 ) == 32 && ix86_hard_regno_mode_ok ( FIRST_SSE_REG , mode2 ) ) return ( GET_MODE_SIZE ( mode1 ) == 32 && ix86_hard_regno_mode_ok ( FIRST_SSE_REG , mode1 ) ) ; if ( GET_MODE_SIZE ( mode2 ) == 16 && ix86_hard_regno_mode_ok ( FIRST_SSE_REG , mode2 ) ) return ( GET_MODE_SIZE ( mode1 ) == 16 && ix86_hard_regno_mode_ok ( FIRST_SSE_REG , mode1 ) ) ; if ( GET_MODE_SIZE ( mode2 ) == 8 && ix86_hard_regno_mode_ok ( FIRST_MMX_REG , mode2 ) ) return ( GET_MODE_SIZE ( mode1 ) == 8 && ix86_hard_regno_mode_ok ( FIRST_MMX_REG , mode1 ) ) ; if ( ( mode1 == E_SCmode && mode2 == E_DImode ) || ( mode1 == E_DImode && mode2 == E_SCmode ) ) return TARGET_64BIT ; if ( ( mode1 == E_SCmode && mode2 == E_V2SFmode ) || ( mode1 == E_V2SFmode && mode2 == E_SCmode ) || ( mode1 == E_DCmode && mode2 == E_V2DFmode ) || ( mode1 == E_V2DFmode && mode2 == E_DCmode ) ) return true ; return false ; } </s>

Return true if MODE1 is accessible in a register that can hold MODE2 without copying . That is , all register classes that can hold MODE2 can also hold MODE1 .


<s> const NVPTXFloatMCExpr * NVPTXFloatMCExpr :: create ( VariantKind Kind , APFloat Flt , MCContext & Ctx ) { return new ( Ctx ) NVPTXFloatMCExpr ( Kind , Flt ) ; } </s>


"Unexpected Kind in getPointerRegClass!"

getPointerRegClass - Returns a TargetRegisterClass used for pointer values .


<s> static void mt_emit_save_restore ( enum save_direction direction , rtx reg , rtx mem , int stack_offset ) { if ( direction == FROM_PROCESSOR_TO_MEM ) { rtx insn ; insn = emit_move_insn ( mem , reg ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; REG_NOTES ( insn ) = gen_rtx_EXPR_LIST ( REG_FRAME_RELATED_EXPR , gen_rtx_SET ( VOIDmode , gen_rtx_MEM ( SImode , gen_rtx_PLUS ( SImode , stack_pointer_rtx , GEN_INT ( stack_offset ) ) ) , reg ) , REG_NOTES ( insn ) ) ; } else emit_move_insn ( reg , mem ) ; } </s>

Emit code to save REG in stack offset pointed to by MEM . STACK_OFFSET is the offset from the SP where the save will happen . This function sets the REG_FRAME_RELATED_EXPR note accordingly .


<s> void LanaiAsmPrinter :: EmitInstruction ( const MachineInstr * MI ) { MachineBasicBlock :: const_instr_iterator I = MI -> getIterator ( ) ; MachineBasicBlock :: const_instr_iterator E = MI -> getParent ( ) -> instr_end ( ) ; do { if ( I -> isCall ( ) ) { emitCallInstruction ( & * I ) ; continue ; } customEmitInstruction ( & * I ) ; } while ( ( ++ I != E ) && I -> isInsideBundle ( ) ) ; } </s>


<s> void ARMPassConfig :: addIRPasses ( ) { if ( TM -> Options . ThreadModel == ThreadModel :: Single ) addPass ( createLowerAtomicPass ( ) ) ; else addPass ( createAtomicExpandPass ( ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableAtomicTidy ) addPass ( createCFGSimplificationPass ( 1 , false , false , true , true , [ this ] ( const Function & F ) { const auto & ST = this -> TM -> getSubtarget < ARMSubtarget > ( F ) ; return ST . hasAnyDataBarrier ( ) && ! ST . isThumb1Only ( ) ; } ) ) ; addPass ( createMVEGatherScatterLoweringPass ( ) ) ; TargetPassConfig :: addIRPasses ( ) ; if ( getOptLevel ( ) == CodeGenOpt :: Aggressive ) addPass ( createARMParallelDSPPass ( ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None ) addPass ( createInterleavedAccessPass ( ) ) ; if ( TM -> getTargetTriple ( ) . isOSWindows ( ) ) addPass ( createCFGuardCheckPass ( ) ) ; } </s>

Add common target configurable passes that perform LLVM IR to IR transforms following machine independent optimization .


<s> unsigned PPCTTI :: getNumberOfRegisters ( bool Vector ) const { if ( Vector && ! ST -> hasAltivec ( ) ) return 0 ; return 32 ; } </s>


<s> static bool s390_match_ccmode_set ( rtx set , machine_mode req_mode ) { machine_mode set_mode ; gcc_assert ( GET_CODE ( set ) == SET ) ; if ( GET_CODE ( SET_DEST ( set ) ) != REG || ! CC_REGNO_P ( REGNO ( SET_DEST ( set ) ) ) ) return 1 ; set_mode = GET_MODE ( SET_DEST ( set ) ) ; switch ( set_mode ) { case CCSmode : case CCSRmode : case CCUmode : case CCURmode : case CCLmode : case CCL1mode : case CCL2mode : case CCL3mode : case CCT1mode : case CCT2mode : case CCT3mode : if ( req_mode != set_mode ) return 0 ; break ; case CCZmode : if ( req_mode != CCSmode && req_mode != CCUmode && req_mode != CCTmode && req_mode != CCSRmode && req_mode != CCURmode ) return 0 ; break ; case CCAPmode : case CCANmode : if ( req_mode != CCAmode ) return 0 ; break ; default : gcc_unreachable ( ) ; } return ( GET_MODE ( SET_SRC ( set ) ) == set_mode ) ; } </s>

Return true if SET either does n't set the CC register , or else the source and destination have matching CC modes and that CC mode is at least as constrained as REQ_MODE .


<s> static bool ix86_hard_regno_call_part_clobbered ( unsigned int abi_id , unsigned int regno , machine_mode mode ) { if ( abi_id == ABI_VZEROUPPER ) return ( GET_MODE_SIZE ( mode ) > 16 && ( ( TARGET_64BIT && REX_SSE_REGNO_P ( regno ) ) || LEGACY_SSE_REGNO_P ( regno ) ) ) ; return SSE_REGNO_P ( regno ) && GET_MODE_SIZE ( mode ) > 16 ; } </s>

Implement TARGET_HARD_REGNO_CALL_PART_CLOBBERED . The only ABI that saves SSE registers across calls is Win64 ( thus no need to check the current ABI here ) , and with AVX enabled Win64 only guarantees that the low 16 bytes are saved .


<s> int xstormy16_carry_plus_operand ( rtx x , enum machine_mode mode ATTRIBUTE_UNUSED ) { return ( GET_CODE ( x ) == PLUS && GET_CODE ( XEXP ( x , 1 ) ) == CONST_INT && ( INTVAL ( XEXP ( x , 1 ) ) < - 4 || INTVAL ( XEXP ( x , 1 ) ) > 4 ) ) ; } </s>

Recognize a PLUS that needs the carry register .


<s>
bool
PPCDarwinAsmPrinter
::
doFinalization
(
Module
&
M
)
{
bool
isPPC64
=
TM
.
getTargetData
(
)
->
getPointerSizeInBits
(
)
==
64
;
TargetLoweringObjectFileMachO
&
TLOFMacho
=
static_cast
<
TargetLoweringObjectFileMachO
&
>
(
getObjFileLowering
(
)
)
;
MachineModuleInfoMachO
&
MMIMacho
=
MMI
->
getObjFileInfo
<
MachineModuleInfoMachO
>
(
)
;
MachineModuleInfoMachO
::
SymbolListTy
Stubs
=
MMIMacho
.
GetFnStubList
(
)
;
if
(
!
Stubs
.
empty
(
)
)
EmitFunctionStubs
(
Stubs
)
;
if
(
MAI
->
doesSupportExceptionHandling
(
)
&&
MMI
)
{
const
std
::
vector
<
Function
*
>
&
Personalities
=
MMI
->
getPersonalities
(
)
;
for
(
std
::
vector
<
Function
*
>
::
const_iterator
I
=
Personalities
.
begin
(
)
,
E
=
Personalities
.
end
(
)
;
I
!=
E
;
++
I
)
{
if
(
*
I
)
{
MCSymbol
*
NLPSym
=
GetSymbolWithGlobalValueBase
(
*
I
,
"$non_lazy_ptr"
)
;
MCSymbol
*
&
StubSym
=
MMIMacho
.
getGVStubEntry
(
NLPSym
)
;
StubSym
=
GetGlobalValueSymbol
(
*
I
)
;
}
}
}
Stubs
=
MMIMacho
.
GetGVStubList
(
)
;
if
(
!
Stubs
.
empty
(
)
)
{
OutStreamer
.
SwitchSection
(
TLOFMacho
.
getNonLazySymbolPointerSection
(
)
)
;
EmitAlignment
(
isPPC64
3
:
2
)
;
for
(
unsigned
i
=
0
,
e
=
Stubs
.
size
(
)
;
i
!=
e
;
++
i
)
{
O
<<
*
Stubs
[
i
]
.
first
<<
":\n"
;
O
<<
"\t.indirect_symbol "
<<
*
Stubs
[
i
]
.
second
<<
'\n'
;
O
<<
(
isPPC64
"\t.quad\t0\n"
:
"\t.long\t0\n"
)
;
}
}
Stubs
=
MMIMacho
.
GetHiddenGVStubList
(
)
;
if
(
!
Stubs
.
empty
(
)
)
{
OutStreamer
.
SwitchSection
(
getObjFileLowering
(
)
.
getDataSection
(
)
)
;
EmitAlignment
(
isPPC64
3
:
2
)
;
for
(
unsigned
i
=
0
,
e
=
Stubs
.
size
(
)
;
i
!=
e
;
++
i
)
{
O
<<
*
Stubs
[
i
]
.
first
<<
":\n"
;
O
<<
(
isPPC64
"\t.quad\t"
:
"\t.long\t"
)
<<
*
Stubs
[
i
]
.
second
<<
'\n'
;
}
}
OutStreamer
.
EmitAssemblerFlag
(
MCAF_SubsectionsViaSymbols
)
;
return
AsmPrinter
::
doFinalization
(
M
)
;
}
</s>

doFinalization - Virtual method overriden by subclasses to do any necessary clean up after all passes have run .


<s> bool X86TargetLowering :: isFMAFasterThanFMulAndFAdd ( EVT VT ) const { if ( ! ( Subtarget -> hasFMA ( ) || Subtarget -> hasFMA4 ( ) || Subtarget -> hasAVX512 ( ) ) ) return false ; VT = VT . getScalarType ( ) ; if ( ! VT . isSimple ( ) ) return false ; switch ( VT . getSimpleVT ( ) . SimpleTy ) { case MVT :: f32 : case MVT :: f64 : return true ; default : break ; } return false ; } </s>

Return true if an FMA operation is faster than a pair of fmul and fadd instructions .


<s> bool PPCLoopInstrFormPrep :: runOnFunction ( Function & F ) { if ( skipFunction ( F ) ) return false ; LI = & getAnalysis < LoopInfoWrapperPass > ( ) . getLoopInfo ( ) ; SE = & getAnalysis < ScalarEvolutionWrapperPass > ( ) . getSE ( ) ; auto * DTWP = getAnalysisIfAvailable < DominatorTreeWrapperPass > ( ) ; DT = DTWP ? & DTWP -> getDomTree ( ) : nullptr ; PreserveLCSSA = mustPreserveAnalysisID ( LCSSAID ) ; ST = TM ? TM -> getSubtargetImpl ( F ) : nullptr ; SuccPrepCount = 0 ; bool MadeChange = false ; for ( Loop * I : * LI ) for ( Loop * L : depth_first ( I ) ) MadeChange |= runOnLoop ( L ) ; return MadeChange ; } </s>

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .


getTargetNodeName - This method returns the name of a target specific


<s> int PPCInstrInfo :: getOperandLatency ( const InstrItineraryData * ItinData , const MachineInstr * DefMI , unsigned DefIdx , const MachineInstr * UseMI , unsigned UseIdx ) const { int Latency = PPCGenInstrInfo :: getOperandLatency ( ItinData , DefMI , DefIdx , UseMI , UseIdx ) ; const MachineOperand & DefMO = DefMI -> getOperand ( DefIdx ) ; unsigned Reg = DefMO . getReg ( ) ; bool IsRegCR ; if ( TargetRegisterInfo :: isVirtualRegister ( Reg ) ) { const MachineRegisterInfo * MRI = & DefMI -> getParent ( ) -> getParent ( ) -> getRegInfo ( ) ; IsRegCR = MRI -> getRegClass ( Reg ) -> hasSuperClassEq ( & PPC :: CRRCRegClass ) || MRI -> getRegClass ( Reg ) -> hasSuperClassEq ( & PPC :: CRBITRCRegClass ) ; } else { IsRegCR = PPC :: CRRCRegClass . contains ( Reg ) || PPC :: CRBITRCRegClass . contains ( Reg ) ; } if ( UseMI -> isBranch ( ) && IsRegCR ) { if ( Latency < 0 ) Latency = getInstrLatency ( ItinData , DefMI ) ; unsigned Directive = Subtarget . getDarwinDirective ( ) ; switch ( Directive ) { default : break ; case PPC :: DIR_7400 : case PPC :: DIR_750 : case PPC :: DIR_970 : case PPC :: DIR_E5500 : case PPC :: DIR_PWR4 : case PPC :: DIR_PWR5 : case PPC :: DIR_PWR5X : case PPC :: DIR_PWR6 : case PPC :: DIR_PWR6X : case PPC :: DIR_PWR7 : case PPC :: DIR_PWR8 : Latency += 2 ; break ; } } return Latency ; } </s>

Compute and return the use operand latency of a given pair of def and use .


"operand must be an 8-bit PC relative address"

"operand must be an 8 to 16 bit value (between 256 and "

MatchAndEmitInstruction - Recognize a series of operands of a parsed instruction as an actual MCInst and emit it to the specified MCStreamer .


";;\t\tBACKEND: move insn %d to the top of list\n"

";;\t\tBACKEND: best insn %d already on top\n"

"ready list ooo attributes - sched state: %d\n"

This function is called via hook TARGET_SCHED_REORDER before issuing one insn from list READY which contains * NREADYP entries . For target z10 it reorders load instructions to avoid early load conflicts in the floating point pipeline


<s> const RegisterBankInfo * getRegBankInfo ( ) const override { return RegBankInfo . get ( ) ; } </s>

If the information for the register banks is available , return it .


<s> void aarch64_expand_sve_mem_move ( rtx dest , rtx src , machine_mode pred_mode ) { machine_mode mode = GET_MODE ( dest ) ; rtx ptrue = force_reg ( pred_mode , CONSTM1_RTX ( pred_mode ) ) ; if ( ! register_operand ( src , mode ) && ! register_operand ( dest , mode ) ) { rtx tmp = gen_reg_rtx ( mode ) ; if ( MEM_P ( src ) ) aarch64_emit_sve_pred_move ( tmp , ptrue , src ) ; else emit_move_insn ( tmp , src ) ; src = tmp ; } aarch64_emit_sve_pred_move ( dest , ptrue , src ) ; } </s>

Expand a pre-RA SVE data move from SRC to DEST in which at least one operand is in memory . In this case we need to use the predicated LD1 and ST1 instead of LDR and STR , both for correctness on big-endian targets and because LD1 and ST1 support a wider range of addressing modes . PRED_MODE is the mode of the predicate . See the comment at the head of aarch64-sve.md for details about the big-endian handling .


<s>
bool
HexagonAsmParser
::
MatchAndEmitInstruction
(
SMLoc
IDLoc
,
unsigned
&
Opcode
,
OperandVector
&
Operands
,
MCStreamer
&
Out
,
uint64_t
&
ErrorInfo
,
bool
MatchingInlineAsm
)
{
if
(
!
InBrackets
)
{
MCB
.
clear
(
)
;
MCB
.
addOperand
(
MCOperand
::
createImm
(
0
)
)
;
}
HexagonOperand
&
FirstOperand
=
static_cast
<
HexagonOperand
&
>
(
*
Operands
[
0
]
)
;
if
(
FirstOperand
.
isToken
(
)
&&
FirstOperand
.
getToken
(
)
==
"{"
)
{
assert
(
Operands
.
size
(
)
==
1
&&
"Brackets should be by themselves"
)
;
if
(
InBrackets
)
{
getParser
(
)
.
Error
(
IDLoc
,
"Already in a packet"
)
;
return
true
;
}
InBrackets
=
true
;
return
false
;
}
if
(
FirstOperand
.
isToken
(
)
&&
FirstOperand
.
getToken
(
)
==
"}"
)
{
assert
(
Operands
.
size
(
)
==
1
&&
"Brackets should be by themselves"
)
;
if
(
!
InBrackets
)
{
getParser
(
)
.
Error
(
IDLoc
,
"Not in a packet"
)
;
return
true
;
}
InBrackets
=
false
;
if
(
matchBundleOptions
(
)
)
return
true
;
return
finishBundle
(
IDLoc
,
Out
)
;
}
MCInst
*
SubInst
=
new
(
getParser
(
)
.
getContext
(
)
)
MCInst
;
if
(
matchOneInstruction
(
*
SubInst
,
IDLoc
,
Operands
,
ErrorInfo
,
MatchingInlineAsm
)
)
return
true
;
HexagonMCInstrInfo
::
extendIfNeeded
(
getParser
(
)
.
getContext
(
)
,
MII
,
MCB
,
*
SubInst
)
;
MCB
.
addOperand
(
MCOperand
::
createInst
(
SubInst
)
)
;
if
(
!
InBrackets
)
return
finishBundle
(
IDLoc
,
Out
)
;
return
false
;
}
</s>

Hexagon
Hexagon
0
Hexagon
Hexagon
0
"{"
1
"Brackets should be by themselves"
"Already in a packet"
"}"
1
"Brackets should be by themselves"
"Not in a packet"
Hexagon


<s> static const char * rs6000_xcoff_visibility ( tree decl ) { static const char * const visibility_types [ ] = { "" , ",protected" , ",hidden" , ",internal" } ; enum symbol_visibility vis = DECL_VISIBILITY ( decl ) ; if ( TREE_CODE ( decl ) == FUNCTION_DECL && cgraph_node :: get ( decl ) && cgraph_node :: get ( decl ) -> instrumentation_clone && cgraph_node :: get ( decl ) -> instrumented_version ) vis = DECL_VISIBILITY ( cgraph_node :: get ( decl ) -> instrumented_version -> decl ) ; return visibility_types [ vis ] ; } </s>

Helper function to calculate visibility of a DECL and return the value as a const string .

rs6000 "" ",protected" ",hidden" ",internal"


<s> static rtx vax_function_arg ( cumulative_args_t cum ATTRIBUTE_UNUSED , machine_mode mode ATTRIBUTE_UNUSED , const_tree type ATTRIBUTE_UNUSED , bool named ATTRIBUTE_UNUSED ) { return NULL_RTX ; } </s>


<s> rtx bfin_gen_compare ( rtx cmp , machine_mode mode ATTRIBUTE_UNUSED ) { enum rtx_code code1 , code2 ; rtx op0 = XEXP ( cmp , 0 ) , op1 = XEXP ( cmp , 1 ) ; rtx tem = bfin_cc_rtx ; enum rtx_code code = GET_CODE ( cmp ) ; if ( GET_MODE ( op0 ) == BImode ) { gcc_assert ( ( code == NE || code == EQ ) && op1 == const0_rtx ) ; tem = op0 , code2 = code ; } else { switch ( code ) { case EQ : case LT : case LE : case LEU : case LTU : code1 = code ; code2 = NE ; break ; default : code1 = reverse_condition ( code ) ; code2 = EQ ; break ; } emit_insn ( gen_rtx_SET ( tem , gen_rtx_fmt_ee ( code1 , BImode , op0 , op1 ) ) ) ; } return gen_rtx_fmt_ee ( code2 , BImode , tem , CONST0_RTX ( BImode ) ) ; } </s>

Emit rtl for a comparison operation CMP in mode MODE . Operands have been stored in bfin_compare_op0 and bfin_compare_op1 already .


<s> bool SystemZElimCompare :: processBlock ( MachineBasicBlock & MBB ) { bool Changed = false ; bool CompleteCCUsers = ! isCCLiveOut ( MBB ) ; SmallVector < MachineInstr * , 4 > CCUsers ; MachineBasicBlock :: iterator MBBI = MBB . end ( ) ; while ( MBBI != MBB . begin ( ) ) { MachineInstr & MI = * -- MBBI ; if ( CompleteCCUsers && ( MI . isCompare ( ) || isLoadAndTestAsCmp ( MI ) ) && ( optimizeCompareZero ( MI , CCUsers ) || fuseCompareOperations ( MI , CCUsers ) ) ) { ++ MBBI ; MI . eraseFromParent ( ) ; Changed = true ; CCUsers . clear ( ) ; continue ; } if ( MI . definesRegister ( SystemZ :: CC ) ) { CCUsers . clear ( ) ; CompleteCCUsers = true ; } if ( MI . readsRegister ( SystemZ :: CC ) && CompleteCCUsers ) CCUsers . push_back ( & MI ) ; } return Changed ; } </s>

processBlock - If there are any predecessors whose control can be threaded through to a successor , transform them now .

SystemZ SystemZ 4 SystemZ::CC SystemZ::CC


<s> static struct machine_function * eco32_init_machine_status ( void ) { return ggc_alloc_cleared_machine_function ( ) ; } </s>

Allocate a chunk of memory for per-function machine-dependent data .


<s> void ECLairAsmBackend :: applyFixup ( const MCAssembler & Asm , const MCFixup & Fixup , const MCValue & Target , MutableArrayRef < char > Data , uint64_t Value , bool IsResolved , const MCSubtargetInfo * STI ) const { return ; } </s>

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


<s> static void rs6000_alloc_sdmode_stack_slot ( void ) { tree t ; basic_block bb ; gimple_stmt_iterator gsi ; gcc_assert ( cfun -> machine -> sdmode_stack_slot == NULL_RTX ) ; if ( ira_use_lra_p ) return ; if ( TARGET_NO_SDMODE_STACK ) return ; FOR_EACH_BB_FN ( bb , cfun ) for ( gsi = gsi_start_bb ( bb ) ; ! gsi_end_p ( gsi ) ; gsi_next ( & gsi ) ) { tree ret = walk_gimple_op ( gsi_stmt ( gsi ) , rs6000_check_sdmode , NULL ) ; if ( ret ) { rtx stack = assign_stack_local ( DDmode , GET_MODE_SIZE ( DDmode ) , 0 ) ; cfun -> machine -> sdmode_stack_slot = adjust_address_nv ( stack , SDmode , 0 ) ; return ; } } for ( t = DECL_ARGUMENTS ( cfun -> decl ) ; t ; t = DECL_CHAIN ( t ) ) { if ( TREE_TYPE ( t ) == error_mark_node ) continue ; if ( TYPE_MODE ( TREE_TYPE ( t ) ) == SDmode || TYPE_MODE ( DECL_ARG_TYPE ( t ) ) == SDmode ) { rtx stack = assign_stack_local ( DDmode , GET_MODE_SIZE ( DDmode ) , 0 ) ; cfun -> machine -> sdmode_stack_slot = adjust_address_nv ( stack , SDmode , 0 ) ; return ; } } } </s>

Allocate a 64-bit stack slot to be used for copying SDmode values through if this function has any SDmode references . If we are on a power7 or later , we do n't need the 64-bit stack slot since the LFIWZX and STIFWX instructions can load/store the value .


<s> static void s390_dump_pool ( struct constant_pool * pool , bool remote_label ) { struct constant * c ; rtx insn = pool -> pool_insn ; int i ; if ( TARGET_CPU_ZARCH ) { insn = emit_insn_after ( gen_pool_section_start ( ) , insn ) ; INSN_ADDRESSES_NEW ( insn , - 1 ) ; } if ( TARGET_CPU_ZARCH ) insn = emit_insn_after ( gen_pool_align ( GEN_INT ( 8 ) ) , insn ) ; else insn = emit_insn_after ( gen_pool_align ( GEN_INT ( 4 ) ) , insn ) ; INSN_ADDRESSES_NEW ( insn , - 1 ) ; if ( ! remote_label ) { insn = emit_label_after ( pool -> label , insn ) ; INSN_ADDRESSES_NEW ( insn , - 1 ) ; } for ( i = 0 ; i < NR_C_MODES ; i ++ ) for ( c = pool -> constants [ i ] ; c ; c = c -> next ) { rtx value = c -> value ; if ( GET_CODE ( value ) == CONST && GET_CODE ( XEXP ( value , 0 ) ) == UNSPEC && XINT ( XEXP ( value , 0 ) , 1 ) == UNSPEC_LTREL_OFFSET && XVECLEN ( XEXP ( value , 0 ) , 0 ) == 1 ) { value = gen_rtx_MINUS ( Pmode , XVECEXP ( XEXP ( value , 0 ) , 0 , 0 ) , gen_rtx_LABEL_REF ( VOIDmode , pool -> label ) ) ; value = gen_rtx_CONST ( VOIDmode , value ) ; } insn = emit_label_after ( c -> label , insn ) ; INSN_ADDRESSES_NEW ( insn , - 1 ) ; value = gen_rtx_UNSPEC_VOLATILE ( constant_modes [ i ] , gen_rtvec ( 1 , value ) , UNSPECV_POOL_ENTRY ) ; insn = emit_insn_after ( value , insn ) ; INSN_ADDRESSES_NEW ( insn , - 1 ) ; } insn = emit_insn_after ( gen_pool_align ( GEN_INT ( 2 ) ) , insn ) ; INSN_ADDRESSES_NEW ( insn , - 1 ) ; for ( c = pool -> execute ; c ; c = c -> next ) { insn = emit_label_after ( c -> label , insn ) ; INSN_ADDRESSES_NEW ( insn , - 1 ) ; insn = emit_insn_after ( s390_execute_target ( c -> value ) , insn ) ; INSN_ADDRESSES_NEW ( insn , - 1 ) ; } if ( TARGET_CPU_ZARCH ) { insn = emit_insn_after ( gen_pool_section_end ( ) , insn ) ; INSN_ADDRESSES_NEW ( insn , - 1 ) ; } insn = emit_barrier_after ( insn ) ; INSN_ADDRESSES_NEW ( insn , - 1 ) ; remove_insn ( pool -> pool_insn ) ; } </s>

Dump out the constants in POOL . If REMOTE_LABEL is true , do not emit the pool base label .


<s> static void moncontrol ( int mode ) { if ( mode ) { profil ( ( unsigned short * ) ( sbuf + sizeof ( struct phdr ) ) , ssiz - sizeof ( struct phdr ) , ( long ) s_lowpc , s_scale ) ; profiling = 0 ; } else { profil ( ( unsigned short * ) 0 , 0 , 0 , 0 ) ; profiling = 3 ; } } </s>

Control profiling * profiling is what mcount checks to see if * all the data structures are ready .


<s> unsigned X86TTIImpl :: getScalarizationOverhead ( VectorType * Ty , const APInt & DemandedElts , bool Insert , bool Extract ) { unsigned Cost = 0 ; if ( Insert ) { std :: pair < int , MVT > LT = TLI -> getTypeLegalizationCost ( DL , Ty ) ; MVT MScalarTy = LT . second . getScalarType ( ) ; if ( ( MScalarTy == MVT :: i16 && ST -> hasSSE2 ( ) ) || ( MScalarTy . isInteger ( ) && ST -> hasSSE41 ( ) ) || ( MScalarTy == MVT :: f32 && ST -> hasSSE41 ( ) ) ) { if ( LT . second . getSizeInBits ( ) <= 128 ) { Cost += BaseT :: getScalarizationOverhead ( Ty , DemandedElts , Insert , false ) ; } else { unsigned Num128Lanes = LT . second . getSizeInBits ( ) / 128 * LT . first ; unsigned NumElts = LT . second . getVectorNumElements ( ) * LT . first ; APInt WidenedDemandedElts = DemandedElts . zextOrSelf ( NumElts ) ; unsigned Scale = NumElts / Num128Lanes ; for ( unsigned I = 0 ; I < NumElts ; I += Scale ) { APInt Mask = WidenedDemandedElts . getBitsSet ( NumElts , I , I + Scale ) ; APInt MaskedDE = Mask & WidenedDemandedElts ; unsigned Population = MaskedDE . countPopulation ( ) ; Cost += ( Population > 0 && Population != Scale && I % LT . second . getVectorNumElements ( ) != 0 ) ; Cost += Population > 0 ; } Cost += DemandedElts . countPopulation ( ) ; if ( MScalarTy == MVT :: f32 ) for ( unsigned i = 0 , e = cast < FixedVectorType > ( Ty ) -> getNumElements ( ) ; i < e ; i += 4 ) if ( DemandedElts [ i ] ) Cost -- ; } } else if ( LT . second . isVector ( ) ) { if ( Ty -> isIntOrIntVectorTy ( ) ) Cost += DemandedElts . countPopulation ( ) ; unsigned NumElts = LT . second . getVectorNumElements ( ) ; unsigned Pow2Elts = PowerOf2Ceil ( cast < FixedVectorType > ( Ty ) -> getNumElements ( ) ) ; Cost += ( std :: min < unsigned > ( NumElts , Pow2Elts ) - 1 ) * LT . first ; } } if ( Extract ) Cost += BaseT :: getScalarizationOverhead ( Ty , DemandedElts , false , Extract ) ; return Cost ; } </s>

Estimate the overhead of scalarizing an instruction .


<s> void assignValueToAddress ( Register ValVReg , Register Addr , LLT MemTy , MachinePointerInfo & MPO , CCValAssign & VA ) override { MachineFunction & MF = MIRBuilder . getMF ( ) ; auto * MMO = MF . getMachineMemOperand ( MPO , MachineMemOperand :: MOLoad | MachineMemOperand :: MOInvariant , MemTy , inferAlignFromPtrInfo ( MF , MPO ) ) ; MIRBuilder . buildLoad ( ValVReg , Addr , * MMO ) ; } </s>

An overload which takes an ArgInfo if additional information about the arg is needed .


<s>
const
char
*
CSKYTargetLowering
::
getTargetNodeName
(
unsigned
Opcode
)
const
{
switch
(
Opcode
)
{
default
:
llvm_unreachable
(
"unknown CSKYISD node"
)
;
case
CSKYISD
::
NIE
:
return
"CSKYISD::NIE"
;
case
CSKYISD
::
NIR
:
return
"CSKYISD::NIR"
;
case
CSKYISD
::
RET
:
return
"CSKYISD::RET"
;
case
CSKYISD
::
BITCAST_TO_LOHI
:
return
"CSKYISD::BITCAST_TO_LOHI"
;
}
}
</s>

CSKY
CSKY
"unknown CSKYISD node"
CSKYISD::NIE
"CSKYISD::NIE"
CSKYISD::NIR
"CSKYISD::NIR"
CSKYISD::RET
"CSKYISD::RET"
CSKYISD::BITCAST_TO_LOHI
"CSKYISD::BITCAST_TO_LOHI"


<s> const char * PIC16TargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( Opcode ) { default : return NULL ; case PIC16ISD :: Lo : return "PIC16ISD::Lo" ; case PIC16ISD :: Hi : return "PIC16ISD::Hi" ; case PIC16ISD :: MTLO : return "PIC16ISD::MTLO" ; case PIC16ISD :: MTHI : return "PIC16ISD::MTHI" ; case PIC16ISD :: Banksel : return "PIC16ISD::Banksel" ; case PIC16ISD :: PIC16Load : return "PIC16ISD::PIC16Load" ; case PIC16ISD :: PIC16LdWF : return "PIC16ISD::PIC16LdWF" ; case PIC16ISD :: PIC16Store : return "PIC16ISD::PIC16Store" ; case PIC16ISD :: PIC16StWF : return "PIC16ISD::PIC16StWF" ; case PIC16ISD :: BCF : return "PIC16ISD::BCF" ; case PIC16ISD :: LSLF : return "PIC16ISD::LSLF" ; case PIC16ISD :: LRLF : return "PIC16ISD::LRLF" ; case PIC16ISD :: RLF : return "PIC16ISD::RLF" ; case PIC16ISD :: RRF : return "PIC16ISD::RRF" ; case PIC16ISD :: CALL : return "PIC16ISD::CALL" ; case PIC16ISD :: SUBCC : return "PIC16ISD::SUBCC" ; case PIC16ISD :: SELECT_ICC : return "PIC16ISD::SELECT_ICC" ; case PIC16ISD :: BRCOND : return "PIC16ISD::BRCOND" ; case PIC16ISD :: Dummy : return "PIC16ISD::Dummy" ; } } </s>


<s> static MCInstrInfo * createMCInstrInfo ( ) { MCInstrInfo * X = new MCInstrInfo ( ) ; InitWebAssemblyMCInstrInfo ( X ) ; return X ; } </s>

createMCInstrInfo - Create a MCInstrInfo implementation .


<s> unsigned HexagonTTIImpl :: getArithmeticInstrCost ( unsigned Opcode , Type * Ty , TTI :: TargetCostKind CostKind , TTI :: OperandValueKind Opd1Info , TTI :: OperandValueKind Opd2Info , TTI :: OperandValueProperties Opd1PropInfo , TTI :: OperandValueProperties Opd2PropInfo , ArrayRef < const Value * > Args , const Instruction * CxtI ) { if ( Ty -> isVectorTy ( ) ) { std :: pair < int , MVT > LT = TLI . getTypeLegalizationCost ( DL , Ty ) ; if ( LT . second . isFloatingPoint ( ) ) return LT . first + FloatFactor * getTypeNumElements ( Ty ) ; } return BaseT :: getArithmeticInstrCost ( Opcode , Ty , CostKind , Opd1Info , Opd2Info , Opd1PropInfo , Opd2PropInfo , Args , CxtI ) ; } </s>

This is an approximation of reciprocal throughput of a math/logic op .


<s> bool splitFramePushPop ( const MachineFunction & MF ) const { if ( MF . getInfo < ARMFunctionInfo > ( ) -> shouldSignReturnAddress ( ) ) return true ; return ( getFramePointerReg ( ) == ARM :: R7 && MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) ) || isThumb1Only ( ) ; } </s>

Returns true if the frame setup is split into two separate pushes ( first r0-r7 , lr then r8-r11 ) , principally so that the frame pointer is adjacent to lr .


<s> void HexagonTargetMachine :: registerPassBuilderCallbacks ( PassBuilder & PB , bool DebugPassManager ) { PB . registerLateLoopOptimizationsEPCallback ( [ = ] ( LoopPassManager & LPM , PassBuilder :: OptimizationLevel Level ) { LPM . addPass ( HexagonLoopIdiomRecognitionPass ( ) ) ; } ) ; PB . registerOptimizerLastEPCallback ( [ = ] ( ModulePassManager & MPM , PassBuilder :: OptimizationLevel Level ) { LoopPassManager LPM ( DebugPassManager ) ; FunctionPassManager FPM ( DebugPassManager ) ; LPM . addPass ( HexagonVectorLoopCarriedReusePass ( ) ) ; FPM . addPass ( createFunctionToLoopPassAdaptor ( std :: move ( LPM ) ) ) ; MPM . addPass ( createModuleToFunctionPassAdaptor ( std :: move ( FPM ) ) ) ; } ) ; } </s>

Invoke the PassBuilder callback registration .


<s> bool cris_reload_address_legitimized ( rtx x , machine_mode mode ATTRIBUTE_UNUSED , int opnum ATTRIBUTE_UNUSED , int itype , int ind_levels ATTRIBUTE_UNUSED ) { enum reload_type type = ( enum reload_type ) itype ; rtx op0 , op1 ; rtx * op1p ; if ( GET_CODE ( x ) != PLUS ) return false ; op0 = XEXP ( x , 0 ) ; op1 = XEXP ( x , 1 ) ; op1p = & XEXP ( x , 1 ) ; if ( ! REG_P ( op1 ) ) return false ; if ( GET_CODE ( op0 ) == SIGN_EXTEND && MEM_P ( XEXP ( op0 , 0 ) ) ) { rtx op00 = XEXP ( op0 , 0 ) ; rtx op000 = XEXP ( op00 , 0 ) ; rtx * op000p = & XEXP ( op00 , 0 ) ; if ( ( GET_MODE ( op00 ) == HImode || GET_MODE ( op00 ) == QImode ) && ( REG_P ( op000 ) || ( GET_CODE ( op000 ) == POST_INC && REG_P ( XEXP ( op000 , 0 ) ) ) ) ) { bool something_reloaded = false ; if ( GET_CODE ( op000 ) == POST_INC && REG_P ( XEXP ( op000 , 0 ) ) && REGNO ( XEXP ( op000 , 0 ) ) > CRIS_LAST_GENERAL_REGISTER ) return false ; if ( ( REG_P ( op000 ) && REGNO ( op000 ) > CRIS_LAST_GENERAL_REGISTER ) ) { push_reload ( op000 , NULL_RTX , op000p , NULL , GENERAL_REGS , GET_MODE ( x ) , VOIDmode , 0 , 0 , opnum , type ) ; something_reloaded = true ; } if ( REGNO ( op1 ) > CRIS_LAST_GENERAL_REGISTER ) { push_reload ( op1 , NULL_RTX , op1p , NULL , GENERAL_REGS , GET_MODE ( x ) , VOIDmode , 0 , 0 , opnum , type ) ; something_reloaded = true ; } gcc_assert ( something_reloaded ) ; return true ; } } return false ; } </s>

Worker function for LEGITIMIZE_RELOAD_ADDRESS .


<s> bool X86TargetLowering :: isFMAFasterThanFMulAndFAdd ( const MachineFunction & MF , EVT VT ) const { if ( ! Subtarget . hasAnyFMA ( ) ) return false ; VT = VT . getScalarType ( ) ; if ( ! VT . isSimple ( ) ) return false ; switch ( VT . getSimpleVT ( ) . SimpleTy ) { case MVT :: f32 : case MVT :: f64 : return true ; default : break ; } return false ; } </s>

Return true if an FMA operation is faster than a pair of fmul and fadd instructions .


A subroutine that checks multiple load and store using consecutive registers . OP is a parallel rtx we would like to check . LOAD_P indicates whether we are checking load operation . PAR_INDEX is starting element of parallel rtx . FIRST_ELT_REGNO is used to tell starting register number . COUNT helps us to check consecutive register numbers .


<s> TargetLowering :: ConstraintWeight P2TargetLowering :: getSingleConstraintMatchWeight ( AsmOperandInfo & info , const char * constraint ) const { return CW_Default ; } </s>

Examine constraint string and operand type and determine a weight value .