<s> SDValue AMDGPUTargetLowering :: SplitVectorLoad ( const SDValue & Op , SelectionDAG & DAG ) const { LoadSDNode * Load = dyn_cast < LoadSDNode > ( Op ) ; EVT MemEltVT = Load -> getMemoryVT ( ) . getVectorElementType ( ) ; EVT LoadVT = Op . getValueType ( ) ; EVT EltVT = Op . getValueType ( ) . getVectorElementType ( ) ; EVT PtrVT = Load -> getBasePtr ( ) . getValueType ( ) ; unsigned NumElts = Load -> getMemoryVT ( ) . getVectorNumElements ( ) ; SmallVector < SDValue , 8 > Loads ; SmallVector < SDValue , 8 > Chains ; SDLoc SL ( Op ) ; for ( unsigned i = 0 , e = NumElts ; i != e ; ++ i ) { SDValue Ptr = DAG . getNode ( ISD :: ADD , SL , PtrVT , Load -> getBasePtr ( ) , DAG . getConstant ( i * ( MemEltVT . getSizeInBits ( ) / 8 ) , PtrVT ) ) ; SDValue NewLoad = DAG . getExtLoad ( Load -> getExtensionType ( ) , SL , EltVT , Load -> getChain ( ) , Ptr , MachinePointerInfo ( Load -> getMemOperand ( ) -> getValue ( ) ) , MemEltVT , Load -> isVolatile ( ) , Load -> isNonTemporal ( ) , Load -> getAlignment ( ) ) ; Loads . push_back ( NewLoad . getValue ( 0 ) ) ; Chains . push_back ( NewLoad . getValue ( 1 ) ) ; } SDValue Ops [ ] = { DAG . getNode ( ISD :: BUILD_VECTOR , SL , LoadVT , Loads ) , DAG . getNode ( ISD :: TokenFactor , SL , MVT :: Other , Chains ) } ; return DAG . getMergeValues ( Ops , SL ) ; } </s>

Split a vector load into 2 loads of half the vector .


<s> int sh_cfun_interrupt_handler_p ( void ) { return ( lookup_attribute ( "interrupt_handler" , DECL_ATTRIBUTES ( current_function_decl ) ) != NULL_TREE ) ; } </s>

Returns true if the current function has the `` interrupt_handler '' attribute set .


<s> static void ix86_add_cfa_restore_note ( rtx insn , rtx reg , HOST_WIDE_INT cfa_offset ) { if ( ! crtl -> shrink_wrapped && cfa_offset <= cfun -> machine -> fs . red_zone_offset ) return ; if ( insn ) { add_reg_note ( insn , REG_CFA_RESTORE , reg ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; } else queued_cfa_restores = alloc_reg_note ( REG_CFA_RESTORE , reg , queued_cfa_restores ) ; } </s>

Add a REG_CFA_RESTORE REG note to INSN or queue them until next stack manipulation insn . The value is on the stack at CFA - CFA_OFFSET . Do n't add the note if the previously saved value will be left untouched within stack red-zone till return , as unwinders can find the same value in the register and on the stack .


<s>
static
int
getMemSize
(
MachineInstr
*
MI
)
{
switch
(
MI
->
getOpcode
(
)
)
{
default
:
llvm_unreachable
(
"Opcode has unknown size!"
)
;
case
AArch64
::
STRSui
:
case
AArch64
::
STURSi
:
return
4
;
case
AArch64
::
STRDui
:
case
AArch64
::
STURDi
:
return
8
;
case
AArch64
::
STRQui
:
case
AArch64
::
STURQi
:
return
16
;
case
AArch64
::
STRWui
:
case
AArch64
::
STURWi
:
return
4
;
case
AArch64
::
STRXui
:
case
AArch64
::
STURXi
:
return
8
;
case
AArch64
::
LDRSui
:
case
AArch64
::
LDURSi
:
return
4
;
case
AArch64
::
LDRDui
:
case
AArch64
::
LDURDi
:
return
8
;
case
AArch64
::
LDRQui
:
case
AArch64
::
LDURQi
:
return
16
;
case
AArch64
::
LDRWui
:
case
AArch64
::
LDURWi
:
return
4
;
case
AArch64
::
LDRXui
:
case
AArch64
::
LDURXi
:
return
8
;
case
AArch64
::
LDRSWui
:
case
AArch64
::
LDURSWi
:
return
4
;
}
}
</s>

Returns the size in bytes of the memory access .


<s> bool MSP430InstrInfo :: spillCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI ) const { if ( CSI . empty ( ) ) return false ; DebugLoc DL ; if ( MI != MBB . end ( ) ) DL = MI -> getDebugLoc ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; MSP430MachineFunctionInfo * MFI = MF . getInfo < MSP430MachineFunctionInfo > ( ) ; MFI -> setCalleeSavedFrameSize ( CSI . size ( ) * 2 ) ; for ( unsigned i = CSI . size ( ) ; i != 0 ; -- i ) { unsigned Reg = CSI [ i - 1 ] . getReg ( ) ; MBB . addLiveIn ( Reg ) ; BuildMI ( MBB , MI , DL , get ( MSP430 :: PUSH16r ) ) . addReg ( Reg , RegState :: Kill ) ; } return true ; } </s>

spillCalleeSavedRegisters - Issues instruction ( s ) to spill all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of store instructions via storeRegToStackSlot ( ) .


<s> static rtx avr_builtin_setjmp_frame_value ( void ) { rtx xval = gen_reg_rtx ( Pmode ) ; emit_insn ( gen_subhi3 ( xval , virtual_stack_vars_rtx , gen_int_mode ( avr_starting_frame_offset ( ) , Pmode ) ) ) ; return xval ; } </s>

Actual start of frame is virtual_stack_vars_rtx this is offset from frame pointer by +TARGET_STARTING_FRAME_OFFSET . Using saved frame = virtual_stack_vars_rtx - TARGET_STARTING_FRAME_OFFSET avoids creating add/sub of offset in nonlocal goto and setjmp .


<s> bool msp430_has_hwmult ( void ) { static const char * cached_match = NULL ; static bool cached_result ; if ( msp430_hwmult_type == MSP430_HWMULT_NONE ) return false ; if ( msp430_hwmult_type != MSP430_HWMULT_AUTO ) return true ; if ( target_mcu == NULL ) return false ; if ( target_mcu == cached_match ) return cached_result ; cached_match = target_mcu ; msp430_extract_mcu_data ( target_mcu ) ; if ( extracted_mcu_data . name != NULL ) return cached_result = extracted_mcu_data . hwmpy != 0 ; return cached_result = false ; } </s>

Returns true if the current MCU does not have a hardware multiplier of any kind .


<s> DecodeStatus MSP430Disassembler :: getInstruction ( MCInst & MI , uint64_t & Size , ArrayRef < uint8_t > Bytes , uint64_t Address , raw_ostream & VStream , raw_ostream & CStream ) const { if ( Bytes . size ( ) < 2 ) { Size = 0 ; return MCDisassembler :: Fail ; } uint64_t Insn = support :: endian :: read16le ( Bytes . data ( ) ) ; unsigned Opc = fieldFromInstruction ( Insn , 13 , 3 ) ; switch ( Opc ) { case 0 : return getInstructionII ( MI , Size , Bytes , Address , VStream , CStream ) ; case 1 : return getInstructionCJ ( MI , Size , Bytes , Address , VStream , CStream ) ; default : return getInstructionI ( MI , Size , Bytes , Address , VStream , CStream ) ; } } </s>

Returns the disassembly of a single instruction .


<s> SDNode * MipsDAGToDAGISel :: getGlobalBaseReg ( ) { unsigned GlobalBaseReg = MF -> getInfo < MipsFunctionInfo > ( ) -> getGlobalBaseReg ( ) ; return CurDAG -> getRegister ( GlobalBaseReg , getTargetLowering ( ) -> getPointerTy ( ) ) . getNode ( ) ; } </s>

getGlobalBaseReg - Return a virtual register initialized with the the global base register value .


<s> static unsigned long arm_compute_save_core_reg_mask ( void ) { unsigned int save_reg_mask = 0 ; unsigned long func_type = arm_current_func_type ( ) ; unsigned int reg ; if ( IS_NAKED ( func_type ) ) return 0 ; if ( TARGET_APCS_FRAME && frame_pointer_needed && TARGET_ARM ) save_reg_mask |= ( 1 << ARM_HARD_FRAME_POINTER_REGNUM ) | ( 1 << IP_REGNUM ) | ( 1 << LR_REGNUM ) | ( 1 << PC_REGNUM ) ; save_reg_mask |= arm_compute_save_reg0_reg12_mask ( ) ; if ( df_regs_ever_live_p ( LR_REGNUM ) || ( save_reg_mask && optimize_size && ARM_FUNC_TYPE ( func_type ) == ARM_FT_NORMAL && ! crtl -> tail_call_emit && ! crtl -> calls_eh_return ) ) save_reg_mask |= 1 << LR_REGNUM ; if ( cfun -> machine -> lr_save_eliminated ) save_reg_mask &= ~ ( 1 << LR_REGNUM ) ; if ( TARGET_REALLY_IWMMXT && ( ( bit_count ( save_reg_mask ) + ARM_NUM_INTS ( crtl -> args . pretend_args_size + arm_compute_static_chain_stack_bytes ( ) ) ) % 2 ) != 0 ) { for ( reg = 4 ; reg <= 12 ; reg ++ ) if ( ( save_reg_mask & ( 1 << reg ) ) == 0 ) break ; if ( reg <= 12 ) save_reg_mask |= ( 1 << reg ) ; else { cfun -> machine -> sibcall_blocked = 1 ; save_reg_mask |= ( 1 << 3 ) ; } } if ( TARGET_THUMB2 && IS_NESTED ( func_type ) && flag_pic && ( save_reg_mask & THUMB2_WORK_REGS ) == 0 ) { reg = thumb_find_work_register ( 1 << 4 ) ; if ( ! call_used_regs [ reg ] ) save_reg_mask |= ( 1 << reg ) ; } return save_reg_mask ; } </s>

Compute a bit mask of which core registers need to be saved on the stack for the current function . This is used by arm_compute_frame_layout , which may add extra registers .


<s>
bool
SILoadStoreOptimizer
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
if
(
skipFunction
(
MF
.
getFunction
(
)
)
)
return
false
;
STM
=
&
MF
.
getSubtarget
<
GCNSubtarget
>
(
)
;
if
(
!
STM
->
loadStoreOptEnabled
(
)
)
return
false
;
TII
=
STM
->
getInstrInfo
(
)
;
TRI
=
&
TII
->
getRegisterInfo
(
)
;
MRI
=
&
MF
.
getRegInfo
(
)
;
AA
=
&
getAnalysis
<
AAResultsWrapperPass
>
(
)
.
getAAResults
(
)
;
assert
(
MRI
->
isSSA
(
)
&&
"Must be run on SSA"
)
;
LLVM_DEBUG
(
dbgs
(
)
<<
"Running SILoadStoreOptimizer\n"
)
;
bool
Modified
=
false
;
for
(
MachineBasicBlock
&
MBB
:
MF
)
{
CreatedX2
=
0
;
Modified
|=
optimizeBlock
(
MBB
)
;
if
(
CreatedX2
>=
1
)
Modified
|=
optimizeBlock
(
MBB
)
;
}
return
Modified
;
}
</s>

runOnMachineFunction - Emit the function body .

AMDGPU
SI
"Must be run on SSA"
"Running SILoadStoreOptimizer\n"
0
1


<s> static rtx arm_function_arg ( cumulative_args_t pcum_v , machine_mode mode , const_tree type , bool named ) { CUMULATIVE_ARGS * pcum = get_cumulative_args ( pcum_v ) ; int nregs ; if ( mode == VOIDmode ) return const0_rtx ; if ( pcum -> pcs_variant <= ARM_PCS_AAPCS_LOCAL ) { aapcs_layout_arg ( pcum , mode , type , named ) ; return pcum -> aapcs_reg ; } if ( TARGET_IWMMXT_ABI && arm_vector_mode_supported_p ( mode ) && pcum -> named_count > pcum -> nargs + 1 ) { if ( pcum -> iwmmxt_nregs <= 9 ) return gen_rtx_REG ( mode , pcum -> iwmmxt_nregs + FIRST_IWMMXT_REGNUM ) ; else { pcum -> can_split = false ; return NULL_RTX ; } } if ( pcum -> nregs & 1 && ARM_DOUBLEWORD_ALIGN && arm_needs_doubleword_align ( mode , type ) ) pcum -> nregs ++ ; if ( pcum -> can_split ) nregs = 1 ; else nregs = ARM_NUM_REGS2 ( mode , type ) ; if ( ! named || pcum -> nregs + nregs > NUM_ARG_REGS ) return NULL_RTX ; return gen_rtx_REG ( mode , pcum -> nregs ) ; } </s>

Determine where to put an argument to a function . Value is zero to push the argument on the stack , or a hard register in which to store the argument . MODE is the argument 's machine mode . TYPE is the data type of the argument ( as a tree ) . This is null for libcalls where that information may not be available . CUM is a variable of type CUMULATIVE_ARGS which gives info about the preceding args and about the function being called . NAMED is nonzero if this argument is a named parameter ( otherwise it is an extra parameter matching an ellipsis ) . On the ARM , normally the first 16 bytes are passed in registers r0-r3 ; all other arguments are passed on the stack . If ( NAMED == 0 ) ( which happens only in assign_parms , since TARGET_SETUP_INCOMING_VARARGS is defined ) , say it is passed in the stack ( function_prologue will indeed make it pass in the stack if necessary ) .


<s> unsigned SIInstrInfo :: readlaneVGPRToSGPR ( unsigned SrcReg , MachineInstr & UseMI , MachineRegisterInfo & MRI ) const { const TargetRegisterClass * VRC = MRI . getRegClass ( SrcReg ) ; const TargetRegisterClass * SRC = RI . getEquivalentSGPRClass ( VRC ) ; unsigned DstReg = MRI . createVirtualRegister ( SRC ) ; unsigned SubRegs = RI . getRegSizeInBits ( * VRC ) / 32 ; if ( RI . hasAGPRs ( VRC ) ) { VRC = RI . getEquivalentVGPRClass ( VRC ) ; unsigned NewSrcReg = MRI . createVirtualRegister ( VRC ) ; BuildMI ( * UseMI . getParent ( ) , UseMI , UseMI . getDebugLoc ( ) , get ( TargetOpcode :: COPY ) , NewSrcReg ) . addReg ( SrcReg ) ; SrcReg = NewSrcReg ; } if ( SubRegs == 1 ) { BuildMI ( * UseMI . getParent ( ) , UseMI , UseMI . getDebugLoc ( ) , get ( AMDGPU :: V_READFIRSTLANE_B32 ) , DstReg ) . addReg ( SrcReg ) ; return DstReg ; } SmallVector < unsigned , 8 > SRegs ; for ( unsigned i = 0 ; i < SubRegs ; ++ i ) { unsigned SGPR = MRI . createVirtualRegister ( & AMDGPU :: SGPR_32RegClass ) ; BuildMI ( * UseMI . getParent ( ) , UseMI , UseMI . getDebugLoc ( ) , get ( AMDGPU :: V_READFIRSTLANE_B32 ) , SGPR ) . addReg ( SrcReg , 0 , RI . getSubRegFromChannel ( i ) ) ; SRegs . push_back ( SGPR ) ; } MachineInstrBuilder MIB = BuildMI ( * UseMI . getParent ( ) , UseMI , UseMI . getDebugLoc ( ) , get ( AMDGPU :: REG_SEQUENCE ) , DstReg ) ; for ( unsigned i = 0 ; i < SubRegs ; ++ i ) { MIB . addReg ( SRegs [ i ] ) ; MIB . addImm ( RI . getSubRegFromChannel ( i ) ) ; } return DstReg ; } </s>

Copy a value from a VGPR ( SrcReg ) to SGPR .


"CPRESTORE's operand must be an immediate."

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s> bool rx_can_use_simple_return ( void ) { unsigned int low ; unsigned int high ; unsigned int frame_size ; unsigned int stack_size ; unsigned int register_mask ; if ( is_naked_func ( NULL_TREE ) || is_fast_interrupt_func ( NULL_TREE ) || is_interrupt_func ( NULL_TREE ) ) return false ; rx_get_stack_layout ( & low , & high , & register_mask , & frame_size , & stack_size ) ; return ( register_mask == 0 && ( frame_size + stack_size ) == 0 && low == 0 ) ; } </s>

Returns true if a simple return insn can be used .


<s> void AArch64MCCodeEmitter :: encodeInstruction ( const MCInst & MI , raw_ostream & OS , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { verifyInstructionPredicates ( MI , computeAvailableFeatures ( STI . getFeatureBits ( ) ) ) ; if ( MI . getOpcode ( ) == AArch64 :: TLSDESCCALL ) { MCFixupKind Fixup = MCFixupKind ( AArch64 :: fixup_aarch64_tlsdesc_call ) ; Fixups . push_back ( MCFixup :: create ( 0 , MI . getOperand ( 0 ) . getExpr ( ) , Fixup ) ) ; return ; } else if ( MI . getOpcode ( ) == AArch64 :: CompilerBarrier ) { return ; } uint64_t Binary = getBinaryCodeForInstr ( MI , Fixups , STI ) ; support :: endian :: write < uint32_t > ( OS , Binary , support :: little ) ; ++ MCNumEmitted ; } </s>

Encode the given Inst to bytes and append to CB .


Write an ( optimal ) nop sequence of Count bytes to the given output .


<s> static rtx loongarch_expand_builtin_direct ( enum insn_code icode , rtx target , tree exp , bool has_target_p ) { struct expand_operand ops [ MAX_RECOG_OPERANDS ] ; int opno , argno ; opno = 0 ; if ( has_target_p ) create_output_operand ( & ops [ opno ++ ] , target , TYPE_MODE ( TREE_TYPE ( exp ) ) ) ; gcc_assert ( opno + call_expr_nargs ( exp ) == insn_data [ icode ] . n_generator_args ) ; for ( argno = 0 ; argno < call_expr_nargs ( exp ) ; argno ++ ) loongarch_prepare_builtin_arg ( & ops [ opno ++ ] , exp , argno ) ; return loongarch_expand_builtin_insn ( icode , opno , ops , has_target_p ) ; } </s>

Expand a LARCH_BUILTIN_DIRECT or LARCH_BUILTIN_DIRECT_NO_TARGET function ; HAS_TARGET_P says which . EXP is the CALL_EXPR that calls the function and ICODE is the code of the associated .md pattern . TARGET , if nonnull , suggests a good place to put the result .


<s>
const
char
*
getPassName
(
)
const
override
{
return
"Local Dynamic TLS Access Clean-up"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> static bool mayAlias ( MachineInstr & MIa , SmallVectorImpl < MachineInstr * > & MemInsns , AliasAnalysis * AA ) { for ( MachineInstr * MIb : MemInsns ) if ( mayAlias ( MIa , * MIb , AA ) ) return true ; return false ; } </s>

Returns true if this instruction 's memory access aliases the memory access of Other .


<s> unsigned XCoreRegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { bool FP = hasFP ( MF ) ; return FP ? XCore :: R10 : XCore :: SP ; } </s>


<s> static int ia64_arg_partial_bytes ( CUMULATIVE_ARGS * cum , enum machine_mode mode , tree type , bool named ATTRIBUTE_UNUSED ) { int words = ia64_function_arg_words ( type , mode ) ; int offset = ia64_function_arg_offset ( cum , type , words ) ; if ( cum -> words + offset >= MAX_ARGUMENT_SLOTS ) return 0 ; if ( words + cum -> words + offset <= MAX_ARGUMENT_SLOTS ) return 0 ; return ( MAX_ARGUMENT_SLOTS - cum -> words - offset ) * UNITS_PER_WORD ; } </s>

Return number of bytes , at the beginning of the argument , that must be put in registers . 0 is the argument is entirely in registers or entirely in memory .


<s> void print_operand_address ( FILE * file , rtx addr ) { switch ( GET_CODE ( addr ) ) { case REG : fprintf ( file , "0[" ) ; print_operand ( file , addr , 0 ) ; fprintf ( file , "]" ) ; break ; case LO_SUM : if ( GET_CODE ( XEXP ( addr , 0 ) ) == REG ) { fprintf ( file , "lo(" ) ; print_operand ( file , XEXP ( addr , 1 ) , 0 ) ; fprintf ( file , ")[" ) ; print_operand ( file , XEXP ( addr , 0 ) , 0 ) ; fprintf ( file , "]" ) ; } break ; case PLUS : if ( GET_CODE ( XEXP ( addr , 0 ) ) == REG || GET_CODE ( XEXP ( addr , 0 ) ) == SUBREG ) { print_operand ( file , XEXP ( addr , 1 ) , 0 ) ; fprintf ( file , "[" ) ; print_operand ( file , XEXP ( addr , 0 ) , 0 ) ; fprintf ( file , "]" ) ; } else { print_operand ( file , XEXP ( addr , 0 ) , 0 ) ; fprintf ( file , "+" ) ; print_operand ( file , XEXP ( addr , 1 ) , 0 ) ; } break ; case SYMBOL_REF : { const char * off_name = NULL ; const char * reg_name = NULL ; if ( SYMBOL_REF_ZDA_P ( addr ) ) { off_name = "zdaoff" ; reg_name = "r0" ; } else if ( SYMBOL_REF_SDA_P ( addr ) ) { off_name = "sdaoff" ; reg_name = "gp" ; } else if ( SYMBOL_REF_TDA_P ( addr ) ) { off_name = "tdaoff" ; reg_name = "ep" ; } if ( off_name ) fprintf ( file , "%s(" , off_name ) ; output_addr_const ( file , addr ) ; if ( reg_name ) fprintf ( file , ")[%s]" , reg_name ) ; } break ; case CONST : if ( special_symbolref_operand ( addr , VOIDmode ) ) { rtx x = XEXP ( XEXP ( addr , 0 ) , 0 ) ; const char * off_name ; const char * reg_name ; if ( SYMBOL_REF_ZDA_P ( x ) ) { off_name = "zdaoff" ; reg_name = "r0" ; } else if ( SYMBOL_REF_SDA_P ( x ) ) { off_name = "sdaoff" ; reg_name = "gp" ; } else if ( SYMBOL_REF_TDA_P ( x ) ) { off_name = "tdaoff" ; reg_name = "ep" ; } else gcc_unreachable ( ) ; fprintf ( file , "%s(" , off_name ) ; output_addr_const ( file , addr ) ; fprintf ( file , ")[%s]" , reg_name ) ; } else output_addr_const ( file , addr ) ; break ; default : output_addr_const ( file , addr ) ; break ; } } </s>

Print the operand address represented by the rtx addr


<s> void msp430_output_labelref ( FILE * file , const char * name ) { int i ; for ( i = 0 ; helper_function_name_mappings [ i ] . gcc_name ; i ++ ) if ( strcmp ( helper_function_name_mappings [ i ] . gcc_name , name ) == 0 ) { name = helper_function_name_mappings [ i ] . ti_name ; break ; } if ( msp430_hwmult_type != NONE ) { if ( strcmp ( "__mspabi_mpyi" , name ) == 0 ) { if ( msp430_use_f5_series_hwmult ( ) ) name = "__mulhi2_f5" ; else if ( ! msp430_no_hwmult ( ) ) name = "__mulhi2" ; } else if ( strcmp ( "__mspabi_mpyl" , name ) == 0 ) { if ( msp430_use_f5_series_hwmult ( ) ) name = "__mulsi2_f5" ; else if ( use_32bit_hwmult ( ) ) name = "__mulsi2_hw32" ; else if ( ! msp430_no_hwmult ( ) ) name = "__mulsi2" ; } } fputs ( name , file ) ; } </s>

This function does the same as the default , but it will replace GCC function names with the MSPABI-specified ones .


"WDC65816 DAG->DAG Pattern Instruction Selection"


<s> SDValue ARMTargetLowering :: PerformCMOVCombine ( SDNode * N , SelectionDAG & DAG ) const { SDValue Cmp = N -> getOperand ( 4 ) ; if ( Cmp . getOpcode ( ) != ARMISD :: CMPZ ) return SDValue ( ) ; EVT VT = N -> getValueType ( 0 ) ; SDLoc dl ( N ) ; SDValue LHS = Cmp . getOperand ( 0 ) ; SDValue RHS = Cmp . getOperand ( 1 ) ; SDValue FalseVal = N -> getOperand ( 0 ) ; SDValue TrueVal = N -> getOperand ( 1 ) ; SDValue ARMcc = N -> getOperand ( 2 ) ; ARMCC :: CondCodes CC = ( ARMCC :: CondCodes ) cast < ConstantSDNode > ( ARMcc ) -> getZExtValue ( ) ; SDValue Res ; if ( CC == ARMCC :: NE && FalseVal == RHS && FalseVal != LHS ) { Res = DAG . getNode ( ARMISD :: CMOV , dl , VT , LHS , TrueVal , ARMcc , N -> getOperand ( 3 ) , Cmp ) ; } else if ( CC == ARMCC :: EQ && TrueVal == RHS ) { SDValue ARMcc ; SDValue NewCmp = getARMCmp ( LHS , RHS , ISD :: SETNE , ARMcc , DAG , dl ) ; Res = DAG . getNode ( ARMISD :: CMOV , dl , VT , LHS , FalseVal , ARMcc , N -> getOperand ( 3 ) , NewCmp ) ; } if ( Res . getNode ( ) ) { APInt KnownZero , KnownOne ; DAG . ComputeMaskedBits ( SDValue ( N , 0 ) , KnownZero , KnownOne ) ; if ( KnownZero == 0xfffffffe ) Res = DAG . getNode ( ISD :: AssertZext , dl , MVT :: i32 , Res , DAG . getValueType ( MVT :: i1 ) ) ; else if ( KnownZero == 0xffffff00 ) Res = DAG . getNode ( ISD :: AssertZext , dl , MVT :: i32 , Res , DAG . getValueType ( MVT :: i8 ) ) ; else if ( KnownZero == 0xffff0000 ) Res = DAG . getNode ( ISD :: AssertZext , dl , MVT :: i32 , Res , DAG . getValueType ( MVT :: i16 ) ) ; } return Res ; } </s>

PerformCMOVCombine - Target-specific DAG combining for ARMISD : :CMOV .


<s>
bool
NVPTXAsmPrinter
::
doInitialization
(
Module
&
M
)
{
SmallString
<
128
>
Str1
;
raw_svector_ostream
OS1
(
Str1
)
;
MMI
=
getAnalysisIfAvailable
<
MachineModuleInfo
>
(
)
;
MMI
->
AnalyzeModule
(
M
)
;
const_cast
<
TargetLoweringObjectFile
&
>
(
getObjFileLowering
(
)
)
.
Initialize
(
OutContext
,
TM
)
;
Mang
=
new
Mangler
(
TM
.
getDataLayout
(
)
)
;
emitHeader
(
M
,
OS1
)
;
OutStreamer
.
EmitRawText
(
OS1
.
str
(
)
)
;
if
(
!
M
.
getModuleInlineAsm
(
)
.
empty
(
)
)
{
OutStreamer
.
AddComment
(
"Start of file scope inline assembly"
)
;
OutStreamer
.
AddBlankLine
(
)
;
OutStreamer
.
EmitRawText
(
StringRef
(
M
.
getModuleInlineAsm
(
)
)
)
;
OutStreamer
.
AddBlankLine
(
)
;
OutStreamer
.
AddComment
(
"End of file scope inline assembly"
)
;
OutStreamer
.
AddBlankLine
(
)
;
}
if
(
nvptxSubtarget
.
getDrvInterface
(
)
==
NVPTX
::
CUDA
)
recordAndEmitFilenames
(
M
)
;
GlobalsEmitted
=
false
;
return
false
;
}
</s>

Set up the AsmPrinter when we are working on a new module .

NVPTX
NVPTX
128
"Start of file scope inline assembly"
"End of file scope inline assembly"
NVPTX::CUDA


<s> bool n8_consumed_by_addr_in_p ( rtx_insn * consumer , rtx def_reg ) { rtx use_rtx ; switch ( get_attr_type ( consumer ) ) { case TYPE_BRANCH : use_rtx = extract_branch_target_rtx ( consumer ) ; break ; case TYPE_LOAD : if ( load_single_p ( consumer ) ) use_rtx = extract_mem_rtx ( consumer ) ; else use_rtx = extract_base_reg ( consumer ) ; break ; case TYPE_STORE : if ( store_single_p ( consumer ) && ( ! post_update_insn_p ( consumer ) || immed_offset_p ( extract_mem_rtx ( consumer ) ) ) ) use_rtx = extract_mem_rtx ( consumer ) ; else use_rtx = extract_base_reg ( consumer ) ; break ; case TYPE_LOAD_MULTIPLE : case TYPE_STORE_MULTIPLE : use_rtx = extract_base_reg ( consumer ) ; break ; default : gcc_unreachable ( ) ; } return reg_overlap_p ( def_reg , use_rtx ) ; } </s>

Check the dependency between the producer defining DEF_REG and CONSUMER requiring input operand at AG ( II ) .


<s> static short find_insn_regmode_weight ( rtx insn , machine_mode mode ) { rtx x = PATTERN ( insn ) ; short reg_weight = find_set_regmode_weight ( x , mode ) ; if ( GET_CODE ( x ) == PARALLEL ) { int j ; for ( j = XVECLEN ( x , 0 ) - 1 ; j >= 0 ; j -- ) { x = XVECEXP ( PATTERN ( insn ) , 0 , j ) ; reg_weight += find_set_regmode_weight ( x , mode ) ; } } for ( x = REG_NOTES ( insn ) ; x ; x = XEXP ( x , 1 ) ) { if ( REG_NOTE_KIND ( x ) == REG_DEAD || REG_NOTE_KIND ( x ) == REG_UNUSED ) { rtx note = XEXP ( x , 0 ) ; if ( REG_P ( note ) && GET_MODE ( note ) == mode ) reg_weight -- ; } } return reg_weight ; } </s>


"Slot for FPW register must be last in order to be found!"

processFunctionBeforeFrameFinalized - This method is called immediately before the specified function 's frame layout ( MF.getFrameInfo ( ) ) is finalized .


<s> bool PPCInstructionSelector :: select ( MachineInstr & I ) { if ( selectImpl ( I , * CoverageInfo ) ) return true ; return false ; } </s>

Select the ( possibly generic ) instruction I to only use target-specific opcodes .


<s> void GBZ80PassConfig :: addPreRegAlloc ( ) { addPass ( createGBZ80PreRAPass ( ) ) ; } </s>

This method may be implemented by targets that want to run passes immediately before register allocation .


<s> static bool ix86_expand_sse_fp_minmax ( rtx dest , enum rtx_code code , rtx cmp_op0 , rtx cmp_op1 , rtx if_true , rtx if_false ) { machine_mode mode ; bool is_min ; rtx tmp ; if ( code == LT ) ; else if ( code == UNGE ) std :: swap ( if_true , if_false ) ; else return false ; if ( rtx_equal_p ( cmp_op0 , if_true ) && rtx_equal_p ( cmp_op1 , if_false ) ) is_min = true ; else if ( rtx_equal_p ( cmp_op1 , if_true ) && rtx_equal_p ( cmp_op0 , if_false ) ) is_min = false ; else return false ; mode = GET_MODE ( dest ) ; if ( ! flag_finite_math_only || flag_signed_zeros ) { int u = is_min ? UNSPEC_IEEE_MIN : UNSPEC_IEEE_MAX ; rtvec v ; if_true = force_reg ( mode , if_true ) ; v = gen_rtvec ( 2 , if_true , if_false ) ; tmp = gen_rtx_UNSPEC ( mode , v , u ) ; } else { code = is_min ? SMIN : SMAX ; tmp = gen_rtx_fmt_ee ( code , mode , if_true , if_false ) ; } emit_insn ( gen_rtx_SET ( dest , tmp ) ) ; return true ; } </s>

Detect conditional moves that exactly match min/max operational semantics . Note that this is IEEE safe , as long as we do n't interchange the operands . Returns FALSE if this conditional move does n't match a MIN/MAX , and TRUE if the operation is successful and instructions are emitted .


<s> bool X86TargetLowering :: isLegalAddressingMode ( const AddrMode & AM , const Type * Ty ) const { if ( AM . BaseOffs <= - ( 1LL << 32 ) || AM . BaseOffs >= ( 1LL << 32 ) - 1 ) return false ; if ( AM . BaseGV ) { if ( Subtarget -> GVRequiresExtraLoad ( AM . BaseGV , getTargetMachine ( ) , false ) ) return false ; if ( Subtarget -> GVRequiresRegister ( AM . BaseGV , getTargetMachine ( ) , false ) && AM . HasBaseReg ) return false ; if ( Subtarget -> is64Bit ( ) ) { if ( getTargetMachine ( ) . getCodeModel ( ) != CodeModel :: Small ) return false ; if ( AM . BaseOffs || AM . Scale > 1 ) return false ; } } switch ( AM . Scale ) { case 0 : case 1 : case 2 : case 4 : case 8 : break ; case 3 : case 5 : case 9 : if ( AM . HasBaseReg ) return false ; break ; default : return false ; } return true ; } </s>

isLegalAddressingMode - Return true if the addressing mode represented by AM is legal for this target , for a load/store of the specified type .


<s> void GCNPassConfig :: addPreRegAlloc ( ) { if ( getOptLevel ( ) > CodeGenOpt :: None ) { insertPass ( & MachineSchedulerID , & SIFixControlFlowLiveIntervalsID ) ; } if ( getOptLevel ( ) > CodeGenOpt :: None ) { insertPass ( & MachineSchedulerID , & SILoadStoreOptimizerID ) ; insertPass ( & MachineSchedulerID , & RegisterCoalescerID ) ; } addPass ( createSIShrinkInstructionsPass ( ) ) ; addPass ( createSIWholeQuadModePass ( ) ) ; } </s>


<s> void ARMPassConfig :: addPreSched2 ( ) { if ( getOptLevel ( ) != CodeGenOpt :: None ) { if ( EnableARMLoadStoreOpt ) addPass ( createARMLoadStoreOptimizationPass ( ) ) ; addPass ( createExecutionDependencyFixPass ( & ARM :: DPRRegClass ) ) ; } addPass ( createARMExpandPseudoPass ( ) ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) { addPass ( createThumb2SizeReductionPass ( [ this ] ( const Function & F ) { return this -> TM -> getSubtarget < ARMSubtarget > ( F ) . restrictIT ( ) ; } ) ) ; addPass ( createIfConverter ( [ this ] ( const Function & F ) { return ! this -> TM -> getSubtarget < ARMSubtarget > ( F ) . isThumb1Only ( ) ; } ) ) ; } addPass ( createThumb2ITBlockPass ( ) ) ; } </s>

This method may be implemented by targets that want to run passes after prolog-epilog insertion and before the second instruction scheduling pass .

ARM ARM ARM ARM ARM::DPRRegClass ARM ARM ARM


<s> int empty_delay_slot ( rtx_insn * insn ) { rtx seq ; if ( PREV_INSN ( insn ) == NULL ) return 1 ; seq = NEXT_INSN ( PREV_INSN ( insn ) ) ; if ( GET_CODE ( PATTERN ( seq ) ) == SEQUENCE ) return 0 ; return 1 ; } </s>

Return non-zero if a branch or call instruction will be emitting a nop into its delay slot .


<s>
bool
vector_insn_info
::
compatible_p
(
const
vl_vtype_info
&
curr_info
)
const
{
gcc_assert
(
!
uninit_p
(
)
&&
"Can't handle uninitialized info"
)
;
if
(
empty_p
(
)
)
return
false
;
if
(
unknown_p
(
)
)
return
false
;
if
(
!
demand_p
(
DEMAND_AVL
)
)
if
(
m_sew
==
curr_info
.
get_sew
(
)
)
return
true
;
return
compatible_avl_p
(
curr_info
)
&&
compatible_vtype_p
(
curr_info
)
;
}
</s>

Determine whether the vector instructions requirements represented by Require are compatible with the previous vsetvli instruction represented by this . INSN is the instruction whose requirements we 're considering .


<s> bool m68k_illegitimate_symbolic_constant_p ( rtx x ) { rtx base , offset ; if ( M68K_OFFSETS_MUST_BE_WITHIN_SECTIONS_P ) { split_const ( x , & base , & offset ) ; if ( GET_CODE ( base ) == SYMBOL_REF && ! offset_within_block_p ( base , INTVAL ( offset ) ) ) return true ; } return m68k_tls_reference_p ( x , false ) ; } </s>

Return true if X is an illegitimate symbolic constant .


<s> bool runOnMachineFunction ( MachineFunction & MF ) override { AttributeSet FnAttrs = MF . getFunction ( ) -> getAttributes ( ) ; ForCodeSize = FnAttrs . hasAttribute ( AttributeSet :: FunctionIndex , Attribute :: OptimizeForSize ) || FnAttrs . hasAttribute ( AttributeSet :: FunctionIndex , Attribute :: MinSize ) ; return SelectionDAGISel :: runOnMachineFunction ( MF ) ; } </s>

runOnMachineFunction - Emit the function body .


<s> bool X86TargetLowering :: shouldExpandAtomicStoreInIR ( StoreInst * SI ) const { Type * MemType = SI -> getValueOperand ( ) -> getType ( ) ; bool NoImplicitFloatOps = SI -> getFunction ( ) -> hasFnAttribute ( Attribute :: NoImplicitFloat ) ; if ( MemType -> getPrimitiveSizeInBits ( ) == 64 && ! Subtarget . is64Bit ( ) && ! Subtarget . useSoftFloat ( ) && ! NoImplicitFloatOps && ( Subtarget . hasSSE1 ( ) || Subtarget . hasX87 ( ) ) ) return false ; return needsCmpXchgNb ( MemType ) ; } </s>

Returns how the given ( atomic ) store should be expanded by the IR-level AtomicExpand pass into .


<s> const unsigned * MipsRegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { static const unsigned SingleFloatOnlyCalleeSavedRegs [ ] = { Mips :: S0 , Mips :: S1 , Mips :: S2 , Mips :: S3 , Mips :: S4 , Mips :: S5 , Mips :: S6 , Mips :: S7 , Mips :: F20 , Mips :: F21 , Mips :: F22 , Mips :: F23 , Mips :: F24 , Mips :: F25 , Mips :: F26 , Mips :: F27 , Mips :: F28 , Mips :: F29 , Mips :: F30 , 0 } ; static const unsigned BitMode32CalleeSavedRegs [ ] = { Mips :: S0 , Mips :: S1 , Mips :: S2 , Mips :: S3 , Mips :: S4 , Mips :: S5 , Mips :: S6 , Mips :: S7 , Mips :: F20 , Mips :: F22 , Mips :: F24 , Mips :: F26 , Mips :: F28 , Mips :: F30 , 0 } ; if ( Subtarget . isSingleFloat ( ) ) return SingleFloatOnlyCalleeSavedRegs ; else return BitMode32CalleeSavedRegs ; } </s>


<s> bool fixupNeedsRelaxation ( const MCFixup & Fixup , uint64_t Value , const MCRelaxableFragment * DF , const MCAsmLayout & Layout ) const override { return false ; } </s>

Simple predicate for targets where ! Resolved implies requiring relaxation .


<s>
SDValue
SITargetLowering
::
handleD16VData
(
SDValue
VData
,
SelectionDAG
&
DAG
)
const
{
EVT
StoreVT
=
VData
.
getValueType
(
)
;
if
(
!
StoreVT
.
isVector
(
)
)
return
VData
;
SDLoc
DL
(
VData
)
;
assert
(
(
StoreVT
.
getVectorNumElements
(
)
!=
3
)
&&
"Handle v3f16"
)
;
if
(
Subtarget
->
hasUnpackedD16VMem
(
)
)
{
EVT
IntStoreVT
=
StoreVT
.
changeTypeToInteger
(
)
;
SDValue
IntVData
=
DAG
.
getNode
(
ISD
::
BITCAST
,
DL
,
IntStoreVT
,
VData
)
;
EVT
EquivStoreVT
=
EVT
::
getVectorVT
(
*
DAG
.
getContext
(
)
,
MVT
::
i32
,
StoreVT
.
getVectorNumElements
(
)
)
;
SDValue
ZExt
=
DAG
.
getNode
(
ISD
::
ZERO_EXTEND
,
DL
,
EquivStoreVT
,
IntVData
)
;
return
DAG
.
UnrollVectorOp
(
ZExt
.
getNode
(
)
)
;
}
if
(
isTypeLegal
(
StoreVT
)
)
return
VData
;
EVT
EquivStoreVT
=
getEquivalentMemType
(
*
DAG
.
getContext
(
)
,
StoreVT
)
;
return
DAG
.
getNode
(
ISD
::
BITCAST
,
DL
,
EquivStoreVT
,
VData
)
;
}
</s>

Handle register layout difference for f16 images for some subtargets .


<s> bool runOnMachineFunction ( MachineFunction & MF ) { if ( ! MF . getFrameInfo ( ) . hasVarSizedObjects ( ) ) { return false ; } const SNESSubtarget & STI = MF . getSubtarget < SNESSubtarget > ( ) ; const TargetInstrInfo & TII = * STI . getInstrInfo ( ) ; MachineBasicBlock & EntryMBB = MF . front ( ) ; MachineBasicBlock :: iterator MBBI = EntryMBB . begin ( ) ; DebugLoc DL = EntryMBB . findDebugLoc ( MBBI ) ; unsigned SPCopy = MF . getRegInfo ( ) . createVirtualRegister ( & SNES :: MainRegsRegClass ) ; BuildMI ( EntryMBB , MBBI , DL , TII . get ( SNES :: COPY ) , SPCopy ) . addReg ( SNES :: SP ) ; for ( MachineBasicBlock & MBB : MF ) { if ( ! MBB . empty ( ) && MBB . back ( ) . isReturn ( ) ) { MBBI = MBB . getLastNonDebugInstr ( ) ; DL = MBBI -> getDebugLoc ( ) ; BuildMI ( MBB , MBBI , DL , TII . get ( SNES :: COPY ) , SNES :: SP ) . addReg ( SPCopy , RegState :: Kill ) ; } } return true ; } </s>

SNES SNES SNES SNES::MainRegsRegClass SNES::COPY SNES::SP SNES::COPY SNES::SP


<s> bool HexagonPassConfig :: addPreRegAlloc ( ) { if ( ! DisableHardwareLoops ) { PM . add ( createHexagonHardwareLoops ( ) ) ; } return false ; } </s>


<s> static void mn10300_bundle_liw ( void ) { rtx_insn * r ; for ( r = get_insns ( ) ; r != NULL ; r = next_nonnote_nondebug_insn ( r ) ) { rtx_insn * insn1 , * insn2 ; struct liw_data liw1 , liw2 ; insn1 = r ; if ( ! extract_bundle ( insn1 , & liw1 ) ) continue ; insn2 = next_nonnote_nondebug_insn ( insn1 ) ; if ( ! extract_bundle ( insn2 , & liw2 ) ) continue ; if ( ! check_liw_constraints ( & liw1 , & liw2 ) ) continue ; if ( liw1 . slot == LIW_OP2 || liw2 . slot == LIW_OP1 ) { struct liw_data temp ; temp = liw1 ; liw1 = liw2 ; liw2 = temp ; } delete_insn ( insn2 ) ; rtx insn2_pat ; if ( liw1 . op == LIW_OP_CMP ) insn2_pat = gen_cmp_liw ( liw2 . dest , liw2 . src , liw1 . dest , liw1 . src , GEN_INT ( liw2 . op ) ) ; else if ( liw2 . op == LIW_OP_CMP ) insn2_pat = gen_liw_cmp ( liw1 . dest , liw1 . src , liw2 . dest , liw2 . src , GEN_INT ( liw1 . op ) ) ; else insn2_pat = gen_liw ( liw1 . dest , liw2 . dest , liw1 . src , liw2 . src , GEN_INT ( liw1 . op ) , GEN_INT ( liw2 . op ) ) ; insn2 = emit_insn_after ( insn2_pat , insn1 ) ; delete_insn ( insn1 ) ; r = insn2 ; } } </s>

Combine pairs of insns into LIW bundles .


<s> bool AMDGPUTargetLowering :: isLoadBitCastBeneficial ( EVT LoadTy , EVT CastTy ) const { if ( LoadTy . getSizeInBits ( ) != CastTy . getSizeInBits ( ) ) return true ; unsigned LScalarSize = LoadTy . getScalarType ( ) . getSizeInBits ( ) ; unsigned CastScalarSize = CastTy . getScalarType ( ) . getSizeInBits ( ) ; return ( ( LScalarSize <= CastScalarSize ) || ( CastScalarSize >= 32 ) || ( LScalarSize < 32 ) ) ; } </s>

Return true if the following transform is beneficial : fold ( conv ( load x ) ) - > ( load ( conv * ) x ) On architectures that do n't natively support some vector loads efficiently , casting the load to a smaller vector of larger types and loading is more efficient , however , this can be undone by optimizations in dag combiner .


<s>
static
void
microblaze_function_end_prologue
(
FILE
*
file
)
{
if
(
TARGET_STACK_CHECK
)
{
fprintf
(
file
,
"\t# Stack Check Stub -- Start.\n\t"
)
;
fprintf
(
file
,
"ori\tr18,r0,_stack_end\n\t"
)
;
fprintf
(
file
,
"cmpu\tr18,r1,r18\n\t"
)
;
fprintf
(
file
,
"bgei\tr18,_stack_overflow_exit\n\t"
)
;
fprintf
(
file
,
"# Stack Check Stub -- End.\n"
)
;
}
}
</s>

Output extra assembler code at the end of a prologue .


<s>
unsigned
PPCInstrInfo
::
removeBranch
(
MachineBasicBlock
&
MBB
,
int
*
BytesRemoved
)
const
{
assert
(
!
BytesRemoved
&&
"code size not handled"
)
;
MachineBasicBlock
::
iterator
I
=
MBB
.
getLastNonDebugInstr
(
)
;
if
(
I
==
MBB
.
end
(
)
)
return
0
;
if
(
I
->
getOpcode
(
)
!=
PPC
::
B
&&
I
->
getOpcode
(
)
!=
PPC
::
BCC
&&
I
->
getOpcode
(
)
!=
PPC
::
BC
&&
I
->
getOpcode
(
)
!=
PPC
::
BCn
&&
I
->
getOpcode
(
)
!=
PPC
::
BDNZ8
&&
I
->
getOpcode
(
)
!=
PPC
::
BDNZ
&&
I
->
getOpcode
(
)
!=
PPC
::
BDZ8
&&
I
->
getOpcode
(
)
!=
PPC
::
BDZ
)
return
0
;
I
->
eraseFromParent
(
)
;
I
=
MBB
.
end
(
)
;
if
(
I
==
MBB
.
begin
(
)
)
return
1
;
I
;
if
(
I
->
getOpcode
(
)
!=
PPC
::
BCC
&&
I
->
getOpcode
(
)
!=
PPC
::
BC
&&
I
->
getOpcode
(
)
!=
PPC
::
BCn
&&
I
->
getOpcode
(
)
!=
PPC
::
BDNZ8
&&
I
->
getOpcode
(
)
!=
PPC
::
BDNZ
&&
I
->
getOpcode
(
)
!=
PPC
::
BDZ8
&&
I
->
getOpcode
(
)
!=
PPC
::
BDZ
)
return
1
;
I
->
eraseFromParent
(
)
;
return
2
;
}
</s>

Remove the branching code at the end of the specific MBB .


<s> bool X86FrameLowering :: hasReservedCallFrame ( const MachineFunction & MF ) const { return ! MF . getFrameInfo ( ) . hasVarSizedObjects ( ) && ! MF . getInfo < X86MachineFunctionInfo > ( ) -> getHasPushSequences ( ) && ! MF . getInfo < X86MachineFunctionInfo > ( ) -> hasPreallocatedCall ( ) ; } </s>

hasReservedCallFrame - Under normal circumstances , when a frame pointer is not required , we reserve argument space for call sites in the function immediately on entry to the current function .


<s>
void
X86ATTInstPrinter
::
printPCRelImm
(
const
MCInst
*
MI
,
unsigned
OpNo
,
raw_ostream
&
O
)
{
const
MCOperand
&
Op
=
MI
->
getOperand
(
OpNo
)
;
if
(
Op
.
isImm
(
)
)
O
<<
formatImm
(
Op
.
getImm
(
)
)
;
else
{
assert
(
Op
.
isExpr
(
)
&&
"unknown pcrel immediate operand"
)
;
const
MCConstantExpr
*
BranchTarget
=
dyn_cast
<
MCConstantExpr
>
(
Op
.
getExpr
(
)
)
;
int64_t
Address
;
if
(
BranchTarget
&&
BranchTarget
->
EvaluateAsAbsolute
(
Address
)
)
{
O
<<
formatHex
(
(
uint64_t
)
Address
)
;
}
else
{
O
<<
*
Op
.
getExpr
(
)
;
}
}
}
</s>


<s> bool nios2_unspec_reloc_p ( rtx op ) { return ( GET_CODE ( op ) == CONST && GET_CODE ( XEXP ( op , 0 ) ) == UNSPEC && ! nios2_large_offset_p ( XINT ( XEXP ( op , 0 ) , 1 ) ) ) ; } </s>

Return true for conforming unspec relocations . Also used in constraints.md and predicates.md .


<s> unsigned HexagonRegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { const TargetFrameLowering * TFI = MF . getSubtarget ( ) . getFrameLowering ( ) ; if ( TFI -> hasFP ( MF ) ) return Hexagon :: R30 ; return Hexagon :: R29 ; } </s>


<s>
bool
AArch64InstrInfo
::
areMemAccessesTriviallyDisjoint
(
MachineInstr
&
MIa
,
MachineInstr
&
MIb
,
AliasAnalysis
*
AA
)
const
{
const
TargetRegisterInfo
*
TRI
=
&
getRegisterInfo
(
)
;
unsigned
BaseRegA
=
0
,
BaseRegB
=
0
;
int64_t
OffsetA
=
0
,
OffsetB
=
0
;
unsigned
WidthA
=
0
,
WidthB
=
0
;
assert
(
MIa
.
mayLoadOrStore
(
)
&&
"MIa must be a load or store."
)
;
assert
(
MIb
.
mayLoadOrStore
(
)
&&
"MIb must be a load or store."
)
;
if
(
MIa
.
hasUnmodeledSideEffects
(
)
||
MIb
.
hasUnmodeledSideEffects
(
)
||
MIa
.
hasOrderedMemoryRef
(
)
||
MIb
.
hasOrderedMemoryRef
(
)
)
return
false
;
if
(
getMemOpBaseRegImmOfsWidth
(
MIa
,
BaseRegA
,
OffsetA
,
WidthA
,
TRI
)
&&
getMemOpBaseRegImmOfsWidth
(
MIb
,
BaseRegB
,
OffsetB
,
WidthB
,
TRI
)
)
{
if
(
BaseRegA
==
BaseRegB
)
{
int
LowOffset
=
OffsetA
<
OffsetB
OffsetA
:
OffsetB
;
int
HighOffset
=
OffsetA
<
OffsetB
OffsetB
:
OffsetA
;
int
LowWidth
=
(
LowOffset
==
OffsetA
)
WidthA
:
WidthB
;
if
(
LowOffset
+
LowWidth
<=
HighOffset
)
return
true
;
}
}
return
false
;
}
</s>

Sometimes , it is possible for the target to tell , even without aliasing information , that two MIs access different memory addresses .


<s> bool XtensaRegisterInfo :: useFPForScavengingIndex ( const MachineFunction & MF ) const { return false ; } </s>

Returns true if the target wants to use frame pointer based accesses to spill to the scavenger emergency spill slot .


<s>
bool
ARCBranchFinalize
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
DEBUG
(
dbgs
(
)
<<
"Running ARC Branch Finalize on "
<<
MF
.
getName
(
)
<<
"\n"
)
;
std
::
vector
<
MachineInstr
*
>
Branches
;
bool
Changed
=
false
;
unsigned
MaxSize
=
0
;
TII
=
MF
.
getSubtarget
<
ARCSubtarget
>
(
)
.
getInstrInfo
(
)
;
std
::
map
<
MachineBasicBlock
*
,
unsigned
>
BlockToPCMap
;
std
::
vector
<
std
::
pair
<
MachineInstr
*
,
unsigned
>>
BranchToPCList
;
unsigned
PC
=
0
;
for
(
auto
&
MBB
:
MF
)
{
BlockToPCMap
.
insert
(
std
::
make_pair
(
&
MBB
,
PC
)
)
;
for
(
auto
&
MI
:
MBB
)
{
unsigned
Size
=
TII
->
getInstSizeInBytes
(
MI
)
;
if
(
Size
>
8
||
Size
==
0
)
{
DEBUG
(
dbgs
(
)
<<
"Unknown (or size 0) size for: "
<<
MI
<<
"\n"
)
;
}
else
{
MaxSize
+=
Size
;
}
if
(
MI
.
isBranch
(
)
)
{
Branches
.
push_back
(
&
MI
)
;
BranchToPCList
.
emplace_back
(
&
MI
,
PC
)
;
}
PC
+=
Size
;
}
}
for
(
auto
P
:
BranchToPCList
)
{
if
(
isBRccPseudo
(
P
.
first
)
)
isInt
<
9
>
(
MaxSize
)
replaceWithBRcc
(
P
.
first
)
:
replaceWithCmpBcc
(
P
.
first
)
;
}
DEBUG
(
dbgs
(
)
<<
"Estimated function size for "
<<
MF
.
getName
(
)
<<
": "
<<
MaxSize
<<
"\n"
)
;
return
Changed
;
}
</s>

ARC
ARC
"Running ARC Branch Finalize on "
"\n"
0
ARC
0
8
0
"Unknown (or size 0) size for: "
"\n"
9
"Estimated function size for "
": "
"\n"


<s> static section * ia64_select_rtx_section ( machine_mode mode , rtx x , unsigned HOST_WIDE_INT align ) { if ( GET_MODE_SIZE ( mode ) > 0 && GET_MODE_SIZE ( mode ) <= ia64_section_threshold && ! TARGET_NO_SDATA ) return sdata_section ; else return default_elf_select_rtx_section ( mode , x , align ) ; } </s>

Switch to the section to which we should output X . The only thing special we do here is to honor small data .


<s> const FISCRegisterInfo & getRegisterInfo ( ) const { return RI ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s> const HexagonSubtarget * HexagonTargetMachine :: getSubtargetImpl ( const Function & F ) const { AttributeList FnAttrs = F . getAttributes ( ) ; Attribute CPUAttr = FnAttrs . getAttribute ( AttributeList :: FunctionIndex , "target-cpu" ) ; Attribute FSAttr = FnAttrs . getAttribute ( AttributeList :: FunctionIndex , "target-features" ) ; std :: string CPU = CPUAttr . isValid ( ) ? CPUAttr . getValueAsString ( ) . str ( ) : TargetCPU ; std :: string FS = FSAttr . isValid ( ) ? FSAttr . getValueAsString ( ) . str ( ) : TargetFS ; if ( F . getFnAttribute ( "unsafe-fp-math" ) . getValueAsBool ( ) ) FS = FS . empty ( ) ? "+unsafe-fp" : "+unsafe-fp," + FS ; auto & I = SubtargetMap [ CPU + FS ] ; if ( ! I ) { resetTargetOptions ( F ) ; I = std :: make_unique < HexagonSubtarget > ( TargetTriple , CPU , FS , * this ) ; } return I . get ( ) ; } </s>

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .

Hexagon Hexagon Hexagon "target-cpu" "target-features" "unsafe-fp-math" "+unsafe-fp" "+unsafe-fp," Hexagon


<s> int riscv_regno_mode_ok_for_base_p ( int regno , machine_mode mode ATTRIBUTE_UNUSED , bool strict_p ) { if ( ! HARD_REGISTER_NUM_P ( regno ) ) { if ( ! strict_p ) return true ; regno = reg_renumber [ regno ] ; } if ( regno == ARG_POINTER_REGNUM || regno == FRAME_POINTER_REGNUM ) return true ; return GP_REG_P ( regno ) ; } </s>

Return true if register REGNO is a valid base register for mode MODE . STRICT_P is true if REG_OK_STRICT is in effect .


<s> SDValue PIC16TargetLowering :: LowerOperation ( SDValue Op , SelectionDAG & DAG ) const { switch ( Op . getOpcode ( ) ) { case ISD :: ADD : case ISD :: ADDC : case ISD :: ADDE : return LowerADD ( Op , DAG ) ; case ISD :: SUB : case ISD :: SUBC : case ISD :: SUBE : return LowerSUB ( Op , DAG ) ; case ISD :: LOAD : return ExpandLoad ( Op . getNode ( ) , DAG ) ; case ISD :: STORE : return ExpandStore ( Op . getNode ( ) , DAG ) ; case ISD :: MUL : return LowerMUL ( Op , DAG ) ; case ISD :: SHL : case ISD :: SRA : case ISD :: SRL : return LowerShift ( Op , DAG ) ; case ISD :: OR : case ISD :: AND : case ISD :: XOR : return LowerBinOp ( Op , DAG ) ; case ISD :: BR_CC : return LowerBR_CC ( Op , DAG ) ; case ISD :: SELECT_CC : return LowerSELECT_CC ( Op , DAG ) ; } return SDValue ( ) ; } </s>

LowerOperation - Provide custom lowering hooks for some operations .

PIC16 PIC16 ISD::ADD ISD::ADDC ISD::ADDE ISD::SUB ISD::SUBC ISD::SUBE ISD::LOAD ISD::STORE ISD::MUL ISD::SHL ISD::SRA ISD::SRL ISD::OR ISD::AND ISD::XOR ISD::BR_CC ISD::SELECT_CC


<s> static void alpha_pre_atomic_barrier ( enum memmodel model ) { if ( need_atomic_barrier_p ( model , true ) ) emit_insn ( gen_memory_barrier ( ) ) ; } </s>

Subroutines of the atomic operation splitters . Emit barriers as needed for the memory MODEL .


<s> const SystemZInstrInfo * getInstrInfo ( ) const { return & InstrInfo ; } </s>


<s>
CCAssignFn
*
AMDGPUCallLowering
::
CCAssignFnForReturn
(
CallingConv
::
ID
CC
,
bool
IsVarArg
)
{
switch
(
CC
)
{
case
CallingConv
::
AMDGPU_KERNEL
:
case
CallingConv
::
SPIR_KERNEL
:
return
CC_AMDGPU_Kernel
;
case
CallingConv
::
AMDGPU_VS
:
case
CallingConv
::
AMDGPU_GS
:
case
CallingConv
::
AMDGPU_PS
:
case
CallingConv
::
AMDGPU_CS
:
case
CallingConv
::
AMDGPU_HS
:
return
RetCC_SI_Shader
;
case
CallingConv
::
C
:
case
CallingConv
::
Fast
:
return
RetCC_AMDGPU_Func
;
default
:
report_fatal_error
(
"Unsupported calling convention."
)
;
}
}
</s>

Selects the correct CCAssignFn for a given CallingConvention value .

AMDGPU
AMDGPU
AMDGPU
AMDGPU
AMDGPU
AMDGPU
AMDGPU
AMDGPU
AMDGPU
SI
AMDGPU
"Unsupported calling convention."


<s> bool pdp11_fixed_cc_regs ( unsigned int * p1 , unsigned int * p2 ) { * p1 = CC_REGNUM ; * p2 = FCC_REGNUM ; return true ; } </s>

Return the regnums of the CC registers .


<s> static bool alpha_legitimate_address_p ( machine_mode mode , rtx x , bool strict ) { if ( mode == DImode && GET_CODE ( x ) == AND && CONST_INT_P ( XEXP ( x , 1 ) ) && INTVAL ( XEXP ( x , 1 ) ) == - 8 ) x = XEXP ( x , 0 ) ; if ( GET_CODE ( x ) == SUBREG && ( GET_MODE_SIZE ( GET_MODE ( x ) ) < GET_MODE_SIZE ( GET_MODE ( SUBREG_REG ( x ) ) ) ) ) x = SUBREG_REG ( x ) ; if ( REG_P ( x ) && ( strict ? STRICT_REG_OK_FOR_BASE_P ( x ) : NONSTRICT_REG_OK_FOR_BASE_P ( x ) ) ) return true ; if ( CONSTANT_ADDRESS_P ( x ) ) return true ; if ( LINKAGE_SYMBOL_REF_P ( x ) ) return true ; if ( GET_CODE ( x ) == PLUS ) { rtx ofs = XEXP ( x , 1 ) ; x = XEXP ( x , 0 ) ; if ( GET_CODE ( x ) == SUBREG && ( GET_MODE_SIZE ( GET_MODE ( x ) ) < GET_MODE_SIZE ( GET_MODE ( SUBREG_REG ( x ) ) ) ) ) x = SUBREG_REG ( x ) ; if ( REG_P ( x ) ) { if ( ! strict && NONSTRICT_REG_OK_FP_BASE_P ( x ) && CONST_INT_P ( ofs ) ) return true ; if ( ( strict ? STRICT_REG_OK_FOR_BASE_P ( x ) : NONSTRICT_REG_OK_FOR_BASE_P ( x ) ) && CONSTANT_ADDRESS_P ( ofs ) ) return true ; } } else if ( TARGET_EXPLICIT_RELOCS && GET_MODE_SIZE ( mode ) <= UNITS_PER_WORD ) { if ( small_symbolic_operand ( x , Pmode ) ) return true ; if ( GET_CODE ( x ) == LO_SUM ) { rtx ofs = XEXP ( x , 1 ) ; x = XEXP ( x , 0 ) ; if ( GET_CODE ( x ) == SUBREG && ( GET_MODE_SIZE ( GET_MODE ( x ) ) < GET_MODE_SIZE ( GET_MODE ( SUBREG_REG ( x ) ) ) ) ) x = SUBREG_REG ( x ) ; if ( ! ( REG_P ( x ) && ( strict ? STRICT_REG_OK_FOR_BASE_P ( x ) : NONSTRICT_REG_OK_FOR_BASE_P ( x ) ) ) ) return false ; if ( local_symbolic_operand ( ofs , Pmode ) || dtp32_symbolic_operand ( ofs , Pmode ) || tp32_symbolic_operand ( ofs , Pmode ) ) return true ; } } return false ; } </s>

legitimate_address_p recognizes an RTL expression that is a valid memory address for an instruction . The MODE argument is the machine mode for the MEM expression that wants to use this address . For Alpha , we have either a constant address or the sum of a register and a constant address , or just a register . For DImode , any of those forms can be surrounded with an AND that clear the low-order three bits ; this is an `` unaligned '' access .


"Return instruction can only reference SP relative frame objects"

"Requesting 64-bit offset in 32-bit immediate!"

This method must be overriden to eliminate abstract frame indices from instructions which may use them .


<s> MVT getVectorIdxTy ( ) const override { return MVT :: i32 ; } </s>

Returns the type to be used for the index operand of : ISD : :INSERT_VECTOR_ELT , ISD : :EXTRACT_VECTOR_ELT , ISD : :INSERT_SUBVECTOR , and ISD : :EXTRACT_SUBVECTOR .


<s> void ARMBaseRegisterInfo :: emitLoadConstPool ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator & MBBI , DebugLoc dl , unsigned DestReg , unsigned SubIdx , int Val , ARMCC :: CondCodes Pred , unsigned PredReg , unsigned MIFlags ) const { MachineFunction & MF = * MBB . getParent ( ) ; const TargetInstrInfo & TII = * MF . getTarget ( ) . getInstrInfo ( ) ; MachineConstantPool * ConstantPool = MF . getConstantPool ( ) ; const Constant * C = ConstantInt :: get ( Type :: getInt32Ty ( MF . getFunction ( ) -> getContext ( ) ) , Val ) ; unsigned Idx = ConstantPool -> getConstantPoolIndex ( C , 4 ) ; BuildMI ( MBB , MBBI , dl , TII . get ( ARM :: LDRcp ) ) . addReg ( DestReg , getDefRegState ( true ) , SubIdx ) . addConstantPoolIndex ( Idx ) . addImm ( 0 ) . addImm ( Pred ) . addReg ( PredReg ) . setMIFlags ( MIFlags ) ; } </s>

emitLoadConstPool - Emits a load from constpool to materialize the specified immediate .


<s> void AMDGPUMCObjectWriter :: writeObject ( MCAssembler & Asm , const MCAsmLayout & Layout ) { for ( MCAssembler :: iterator I = Asm . begin ( ) , E = Asm . end ( ) ; I != E ; ++ I ) { Asm . writeSectionData ( & * I , Layout ) ; } } </s>

Write the object file and returns the number of bytes written .


<s> static int m32c_hard_regno_nregs_1 ( int regno , machine_mode mode ) { if ( regno == FLG_REGNO && mode == CCmode ) return 1 ; if ( regno >= FIRST_PSEUDO_REGISTER ) return ( ( GET_MODE_SIZE ( mode ) + UNITS_PER_WORD - 1 ) / UNITS_PER_WORD ) ; if ( regno >= MEM0_REGNO && regno <= MEM7_REGNO ) return ( GET_MODE_SIZE ( mode ) + 1 ) / 2 ; if ( GET_MODE_SIZE ( mode ) <= 1 ) return nregs_table [ regno ] . qi_regs ; if ( GET_MODE_SIZE ( mode ) <= 2 ) return nregs_table [ regno ] . hi_regs ; if ( regno == A0_REGNO && mode == SImode && TARGET_A16 ) return 2 ; if ( ( GET_MODE_SIZE ( mode ) <= 3 || mode == PSImode ) && TARGET_A24 ) return nregs_table [ regno ] . pi_regs ; if ( GET_MODE_SIZE ( mode ) <= 4 ) return nregs_table [ regno ] . si_regs ; if ( GET_MODE_SIZE ( mode ) <= 8 ) return nregs_table [ regno ] . di_regs ; return 0 ; } </s>

Implements HARD_REGNO_NREGS . This is complicated by the fact that different registers are different sizes from each other , * and * may be different sizes in different chip families .


<s> TargetLowering :: ConstraintWeight AlphaTargetLowering :: getSingleConstraintMatchWeight ( AsmOperandInfo & info , const char * constraint ) const { ConstraintWeight weight = CW_Invalid ; Value * CallOperandVal = info . CallOperandVal ; if ( CallOperandVal == NULL ) return CW_Default ; switch ( * constraint ) { default : weight = TargetLowering :: getSingleConstraintMatchWeight ( info , constraint ) ; break ; case 'f' : weight = CW_Register ; break ; } return weight ; } </s>

Examine constraint string and operand type and determine a weight value .


<s> FastISel * AArch64TargetLowering :: createFastISel ( FunctionLoweringInfo & funcInfo , const TargetLibraryInfo * libInfo ) const { return AArch64 :: createFastISel ( funcInfo , libInfo ) ; } </s>

This method returns a target specific FastISel object , or null if the target does not support `` fast '' ISel .


<s> static int reg_aligned_for_addr ( rtx x ) { int regno = REGNO ( x ) < FIRST_PSEUDO_REGISTER ? ORIGINAL_REGNO ( x ) : REGNO ( x ) ; return REGNO_POINTER_ALIGN ( regno ) >= 128 ; } </s>

This is called any time we inspect the alignment of a register for addresses .


<s> TargetPassConfig * CSKYTargetMachine :: createPassConfig ( PassManagerBase & PM ) { return new CSKYPassConfig ( * this , PM ) ; } </s>

Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of CodeGen passes .


<s> static bool tryAddingSymbolicOperand ( int64_t Value , bool isBranch , uint64_t Address , uint64_t Offset , uint64_t Width , MCInst & MI , const MCDisassembler * Decoder ) { return Decoder -> tryAddingSymbolicOperand ( MI , Value , Address , isBranch , Offset , Width , 4 ) ; } </s>

Try to add a symbolic operand instead of Value to the MCInst .


"Instr doesn't have FrameIndex operand!"


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . setPreservesCFG ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> void LEGInstrInfo :: loadRegFromStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned DestReg , int FrameIndex , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { BuildMI ( MBB , I , I -> getDebugLoc ( ) , get ( LEG :: LDR ) , DestReg ) . addFrameIndex ( FrameIndex ) . addImm ( 0 ) ; } </s>

Load the specified register of the given register class from the specified stack frame index .


<s> bool X86AsmBackend :: fixupNeedsRelaxation ( const MCFixup & Fixup , uint64_t Value , const MCInstFragment * DF , const MCAsmLayout & Layout ) const { return int64_t ( Value ) != int64_t ( int8_t ( Value ) ) ; } </s>

Simple predicate for targets where ! Resolved implies requiring relaxation .


<s> static bool iq2000_pass_by_reference ( CUMULATIVE_ARGS * cum , enum machine_mode mode , tree type , bool named ATTRIBUTE_UNUSED ) { int size ; if ( cum && targetm . calls . must_pass_in_stack ( mode , type ) ) { CUMULATIVE_ARGS temp ; temp = * cum ; if ( FUNCTION_ARG ( temp , mode , type , named ) != 0 ) return 1 ; } if ( type == NULL_TREE || mode == DImode || mode == DFmode ) return 0 ; size = int_size_in_bytes ( type ) ; return size == - 1 || size > UNITS_PER_WORD ; } </s>

Return true when an argument must be passed by reference .


<s> static int ep_memory_offset ( machine_mode mode , int unsignedp ATTRIBUTE_UNUSED ) { int max_offset = 0 ; switch ( mode ) { case E_QImode : if ( TARGET_SMALL_SLD ) max_offset = ( 1 << 4 ) ; else if ( ( TARGET_V850E_UP ) && unsignedp ) max_offset = ( 1 << 4 ) ; else max_offset = ( 1 << 7 ) ; break ; case E_HImode : if ( TARGET_SMALL_SLD ) max_offset = ( 1 << 5 ) ; else if ( ( TARGET_V850E_UP ) && unsignedp ) max_offset = ( 1 << 5 ) ; else max_offset = ( 1 << 8 ) ; break ; case E_SImode : case E_SFmode : max_offset = ( 1 << 8 ) ; break ; default : break ; } return max_offset ; } </s>

Return maximum offset supported for a short EP memory reference of mode MODE and signedness UNSIGNEDP .


<s> enum machine_mode frv_select_cc_mode ( enum rtx_code code , rtx x , rtx y ) { if ( GET_MODE_CLASS ( GET_MODE ( x ) ) == MODE_FLOAT ) return CC_FPmode ; switch ( code ) { case EQ : case NE : case LT : case GE : return y == const0_rtx ? CC_NZmode : CCmode ; case GTU : case GEU : case LTU : case LEU : return y == const0_rtx ? CC_NZmode : CC_UNSmode ; default : return CCmode ; } } </s>

Implement SELECT_CC_MODE . Choose CC_FP for floating-point comparisons , CC_NZ for comparisons against zero in which a single Z or N flag test is enough , CC_UNS for other unsigned comparisons , and CC for other signed comparisons .


"There are no defined alternate asm variants"

PrintAsmOperand - Print out an operand for an inline asm expression .


<s> ScheduleDAGInstrs * createMachineScheduler ( MachineSchedContext * C ) const override { ScheduleDAGMILive * DAG = createGenericSchedLive ( C ) ; DAG -> addMutation ( createLoadClusterDAGMutation ( DAG -> TII , DAG -> TRI ) ) ; DAG -> addMutation ( createStoreClusterDAGMutation ( DAG -> TII , DAG -> TRI ) ) ; return DAG ; } </s>

Create an instance of ScheduleDAGInstrs to be run within the standard MachineScheduler pass for this function and target at the current optimization level .


<s> static int unit_req_imbalance ( unit_req_table reqs ) { int val = 0 ; int i ; for ( i = 0 ; i < UNIT_REQ_MAX ; i ++ ) { int factor = unit_req_factor ( ( enum unitreqs ) i ) ; int diff = abs ( reqs [ 0 ] [ i ] - reqs [ 1 ] [ i ] ) ; val += ( diff + factor - 1 ) / factor / 2 ; } return val ; } </s>

Examine the table REQS and return a measure of unit imbalance by comparing the two sides of the machine . If , for example , D1 is used twice and D2 used not at all , the return value should be 1 in the absence of other imbalances .


<s> NVPTXSubtarget :: NVPTXSubtarget ( const Triple & TT , const std :: string & CPU , const std :: string & FS , const NVPTXTargetMachine & TM ) : NVPTXGenSubtargetInfo ( TT , CPU , CPU , FS ) , PTXVersion ( 0 ) , SmVersion ( 20 ) , TM ( TM ) , InstrInfo ( ) , TLInfo ( TM , initializeSubtargetDependencies ( CPU , FS ) ) , FrameLowering ( ) { } </s>

This constructor initializes the data members to match that of the specified module .


<s> unsigned AMDGPUPALMetadata :: getRegister ( unsigned Reg ) { auto Regs = getRegisters ( ) ; auto It = Regs . find ( MsgPackDoc . getNode ( Reg ) ) ; if ( It == Regs . end ( ) ) return 0 ; auto N = It -> second ; if ( N . getKind ( ) != msgpack :: Type :: UInt ) return 0 ; return N . getUInt ( ) ; } </s>

Return the specified register in the class .


<s> static unsigned int rs6000_parm_offset ( void ) { return ( DEFAULT_ABI == ABI_V4 ? 2 : DEFAULT_ABI == ABI_ELFv2 ? 4 : 6 ) ; } </s>

The offset in words to the start of the parameter save area .


runOnMachineFunction - Emit the function body .


<s> static bool mcore_legitimate_constant_p ( machine_mode mode ATTRIBUTE_UNUSED , rtx x ) { return GET_CODE ( x ) != CONST_DOUBLE ; } </s>

Implement TARGET_LEGITIMATE_CONSTANT_P On the MCore , allow anything but a double .


<s> void AArch64MCCodeEmitter :: encodeInstruction ( const MCInst & MI , raw_ostream & OS , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { if ( MI . getOpcode ( ) == AArch64 :: TLSDESCCALL ) { MCFixupKind Fixup = MCFixupKind ( AArch64 :: fixup_aarch64_tlsdesc_call ) ; Fixups . push_back ( MCFixup :: create ( 0 , MI . getOperand ( 0 ) . getExpr ( ) , Fixup ) ) ; return ; } uint64_t Binary = getBinaryCodeForInstr ( MI , Fixups , STI ) ; support :: endian :: Writer < support :: little > ( OS ) . write < uint32_t > ( Binary ) ; ++ MCNumEmitted ; } </s>

Encode the given Inst to bytes and append to CB .


<s> void PPCIncomingValueHandler :: assignValueToReg ( Register ValVReg , Register PhysReg , CCValAssign VA ) { markPhysRegUsed ( PhysReg ) ; IncomingValueHandler :: assignValueToReg ( ValVReg , PhysReg , VA ) ; } </s>

The specified value has been assigned to a physical register , handle the appropriate COPY ( either to or from ) and mark any relevant uses/defines as needed .


<s> int PPCInstrInfo :: getOperandLatency ( const InstrItineraryData * ItinData , const MachineInstr * DefMI , unsigned DefIdx , const MachineInstr * UseMI , unsigned UseIdx ) const { int Latency = PPCGenInstrInfo :: getOperandLatency ( ItinData , DefMI , DefIdx , UseMI , UseIdx ) ; const MachineOperand & DefMO = DefMI -> getOperand ( DefIdx ) ; unsigned Reg = DefMO . getReg ( ) ; const TargetRegisterInfo * TRI = & getRegisterInfo ( ) ; bool IsRegCR ; if ( TRI -> isVirtualRegister ( Reg ) ) { const MachineRegisterInfo * MRI = & DefMI -> getParent ( ) -> getParent ( ) -> getRegInfo ( ) ; IsRegCR = MRI -> getRegClass ( Reg ) -> hasSuperClassEq ( & PPC :: CRRCRegClass ) || MRI -> getRegClass ( Reg ) -> hasSuperClassEq ( & PPC :: CRBITRCRegClass ) ; } else { IsRegCR = PPC :: CRRCRegClass . contains ( Reg ) || PPC :: CRBITRCRegClass . contains ( Reg ) ; } if ( UseMI -> isBranch ( ) && IsRegCR ) { if ( Latency < 0 ) Latency = getInstrLatency ( ItinData , DefMI ) ; unsigned Directive = Subtarget . getDarwinDirective ( ) ; switch ( Directive ) { default : break ; case PPC :: DIR_7400 : case PPC :: DIR_750 : case PPC :: DIR_970 : case PPC :: DIR_E5500 : case PPC :: DIR_PWR4 : case PPC :: DIR_PWR5 : case PPC :: DIR_PWR5X : case PPC :: DIR_PWR6 : case PPC :: DIR_PWR6X : case PPC :: DIR_PWR7 : case PPC :: DIR_PWR8 : Latency += 2 ; break ; } } return Latency ; } </s>

Compute and return the use operand latency of a given pair of def and use .


<s> const MCPhysReg * ARMBaseRegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { const ARMSubtarget & STI = MF -> getSubtarget < ARMSubtarget > ( ) ; bool UseSplitPush = STI . splitFramePushPop ( * MF ) ; const MCPhysReg * RegList = STI . isTargetDarwin ( ) ? CSR_iOS_SaveList : ( UseSplitPush ? CSR_AAPCS_SplitPush_SaveList : CSR_AAPCS_SaveList ) ; const Function & F = MF -> getFunction ( ) ; if ( F . getCallingConv ( ) == CallingConv :: GHC ) { return CSR_NoRegs_SaveList ; } else if ( F . hasFnAttribute ( "interrupt" ) ) { if ( STI . isMClass ( ) ) { return UseSplitPush ? CSR_AAPCS_SplitPush_SaveList : CSR_AAPCS_SaveList ; } else if ( F . getFnAttribute ( "interrupt" ) . getValueAsString ( ) == "FIQ" ) { return CSR_FIQ_SaveList ; } else { return CSR_GenericInt_SaveList ; } } if ( STI . getTargetLowering ( ) -> supportSwiftError ( ) && F . getAttributes ( ) . hasAttrSomewhere ( Attribute :: SwiftError ) ) { if ( STI . isTargetDarwin ( ) ) return CSR_iOS_SwiftError_SaveList ; return UseSplitPush ? CSR_AAPCS_SplitPush_SwiftError_SaveList : CSR_AAPCS_SwiftError_SaveList ; } if ( STI . isTargetDarwin ( ) && F . getCallingConv ( ) == CallingConv :: CXX_FAST_TLS ) return MF -> getInfo < ARMFunctionInfo > ( ) -> isSplitCSR ( ) ? CSR_iOS_CXX_TLS_PE_SaveList : CSR_iOS_CXX_TLS_SaveList ; return RegList ; } </s>

ARM ARM ARM ARM "interrupt" "interrupt" "FIQ" ARM


<s> static rtx gen_compare_reg_1 ( enum rtx_code code , rtx x , rtx y ) { machine_mode mode ; rtx cc_reg ; if ( GET_MODE_CLASS ( GET_MODE ( x ) ) == MODE_CC ) return x ; mode = SELECT_CC_MODE ( code , x , y ) ; if ( TARGET_V9 && GET_MODE_CLASS ( GET_MODE ( x ) ) == MODE_FLOAT ) { int reg ; static int next_fcc_reg = 0 ; static rtx prev_args [ 4 ] [ 2 ] ; for ( reg = 0 ; reg < 4 ; reg ++ ) if ( prev_args [ reg ] [ 0 ] == x && prev_args [ reg ] [ 1 ] == y ) break ; if ( reg == 4 ) { reg = next_fcc_reg ; prev_args [ reg ] [ 0 ] = x ; prev_args [ reg ] [ 1 ] = y ; next_fcc_reg = ( next_fcc_reg + 1 ) & 3 ; } cc_reg = gen_rtx_REG ( mode , reg + SPARC_FIRST_V9_FCC_REG ) ; } cc_reg = gen_reg_rtx ( mode ) ; else if ( GET_MODE_CLASS ( GET_MODE ( x ) ) == MODE_FLOAT ) cc_reg = gen_rtx_REG ( mode , SPARC_FCC_REG ) ; else cc_reg = gen_rtx_REG ( mode , SPARC_ICC_REG ) ; emit_insn ( gen_rtx_SET ( VOIDmode , cc_reg , gen_rtx_COMPARE ( mode , x , y ) ) ) ; return cc_reg ; } </s>

Emit the compare insn and return the CC reg for a CODE comparison with operands X and Y .


<s> static rtx m32r_function_arg ( cumulative_args_t cum_v , const function_arg_info & arg ) { CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; return ( PASS_IN_REG_P ( * cum , arg . mode , arg . type ) ? gen_rtx_REG ( arg . mode , ROUND_ADVANCE_CUM ( * cum , arg . mode , arg . type ) ) : NULL_RTX ) ; } </s>

On the M32R the first M32R_MAX_PARM_REGS args are normally in registers and the rest are pushed .


<s> unsigned X86InstrInfo :: getFMA3OpcodeToCommuteOperands ( const MachineInstr & MI , unsigned SrcOpIdx1 , unsigned SrcOpIdx2 , const X86InstrFMA3Group & FMA3Group ) const { unsigned Opc = MI . getOpcode ( ) ; if ( SrcOpIdx1 > SrcOpIdx2 ) std :: swap ( SrcOpIdx1 , SrcOpIdx2 ) ; if ( FMA3Group . isIntrinsic ( ) && SrcOpIdx1 == 1 ) return 0 ; unsigned FMAOp1 = 1 , FMAOp2 = 2 , FMAOp3 = 3 ; if ( FMA3Group . isKMasked ( ) ) { if ( SrcOpIdx1 == 2 ) return 0 ; if ( FMA3Group . isKMergeMasked ( ) && SrcOpIdx1 == FMAOp1 ) return 0 ; FMAOp2 ++ ; FMAOp3 ++ ; } unsigned Case ; if ( SrcOpIdx1 == FMAOp1 && SrcOpIdx2 == FMAOp2 ) Case = 0 ; else if ( SrcOpIdx1 == FMAOp1 && SrcOpIdx2 == FMAOp3 ) Case = 1 ; else if ( SrcOpIdx1 == FMAOp2 && SrcOpIdx2 == FMAOp3 ) Case = 2 ; else return 0 ; const unsigned Form132Index = 0 ; const unsigned Form213Index = 1 ; const unsigned Form231Index = 2 ; static const unsigned FormMapping [ ] [ 3 ] = { { Form231Index , Form213Index , Form132Index } , { Form132Index , Form231Index , Form213Index } , { Form213Index , Form132Index , Form231Index } } ; unsigned FMAForms [ 3 ] ; if ( FMA3Group . isRegOpcodeFromGroup ( Opc ) ) { FMAForms [ 0 ] = FMA3Group . getReg132Opcode ( ) ; FMAForms [ 1 ] = FMA3Group . getReg213Opcode ( ) ; FMAForms [ 2 ] = FMA3Group . getReg231Opcode ( ) ; } else { FMAForms [ 0 ] = FMA3Group . getMem132Opcode ( ) ; FMAForms [ 1 ] = FMA3Group . getMem213Opcode ( ) ; FMAForms [ 2 ] = FMA3Group . getMem231Opcode ( ) ; } unsigned FormIndex ; for ( FormIndex = 0 ; FormIndex < 3 ; FormIndex ++ ) if ( Opc == FMAForms [ FormIndex ] ) break ; FormIndex = FormMapping [ Case ] [ FormIndex ] ; return FMAForms [ FormIndex ] ; } </s>

Returns an adjusted FMA opcode that must be used in FMA instruction that performs the same computations as the given MI but which has the operands SrcOpIdx1 and SrcOpIdx2 commuted .


<s> unsigned BlackfinInstrInfo :: isStoreToStackSlot ( const MachineInstr * MI , int & FrameIndex ) const { switch ( MI -> getOpcode ( ) ) { default : break ; case BF :: STORE32fi : case BF :: STORE16fi : if ( MI -> getOperand ( 1 ) . isFI ( ) && MI -> getOperand ( 2 ) . isImm ( ) && MI -> getOperand ( 2 ) . getImm ( ) == 0 ) { FrameIndex = MI -> getOperand ( 1 ) . getIndex ( ) ; return MI -> getOperand ( 0 ) . getReg ( ) ; } break ; } return 0 ; } </s>

isStoreToStackSlot - If the specified machine instruction is a direct store to a stack slot , return the virtual or physical register number of the source reg along with the FrameIndex of the loaded stack slot .


<s> static void pa_add_gc_roots ( ) { ggc_add_rtx_root ( & hppa_compare_op0 , 1 ) ; ggc_add_rtx_root ( & hppa_compare_op1 , 1 ) ; ggc_add_root ( & deferred_plabels , 1 , sizeof ( & deferred_plabels ) , & mark_deferred_plabels ) ; } </s>

Called to register all of our global variables with the garbage collector .


<s> static bool xstormy16_rtx_costs ( rtx x , machine_mode mode ATTRIBUTE_UNUSED , int outer_code ATTRIBUTE_UNUSED , int opno ATTRIBUTE_UNUSED , int * total , bool speed ATTRIBUTE_UNUSED ) { int code = GET_CODE ( x ) ; switch ( code ) { case CONST_INT : if ( INTVAL ( x ) < 16 && INTVAL ( x ) >= 0 ) * total = COSTS_N_INSNS ( 1 ) / 2 ; else if ( INTVAL ( x ) < 256 && INTVAL ( x ) >= 0 ) * total = COSTS_N_INSNS ( 1 ) ; else * total = COSTS_N_INSNS ( 2 ) ; return true ; case CONST_DOUBLE : case CONST : case SYMBOL_REF : case LABEL_REF : * total = COSTS_N_INSNS ( 2 ) ; return true ; case MULT : * total = COSTS_N_INSNS ( 35 + 6 ) ; return true ; case DIV : * total = COSTS_N_INSNS ( 51 - 6 ) ; return true ; default : return false ; } } </s>

Compute a ( partial ) cost for rtx X . Return true if the complete cost has been computed , and false if subexpressions should be scanned . In either case , * TOTAL contains the cost result .


"MMIX Internal: Last named vararg would not fit in a register"


<s> static Token * parse_list_nosemi ( Token * tok ) { Token * start = tok ; do if ( ! ( ++ tok ) -> kind ) break ; while ( ( ++ tok ) -> kind == ',' ) ; tok [ - 1 ] . end = 1 ; Stmt * stmt = alloc_stmt ( V_dot , start , tok , 0 ) ; append_stmt ( & decls , stmt ) ; return tok ; } </s>


<s> bool requiresFrameIndexScavenging ( const MachineFunction & MF ) const override { return true ; } </s>

Returns true if the target requires post PEI scavenging of registers for materializing frame index constants .


<s> bool isToken ( ) const { return Kind == Token ; } </s>


<s> virtual const SparcSubtarget * getSubtargetImpl ( ) const { return & Subtarget ; } </s>

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .


<s> bool SIRegisterInfo :: needsFrameBaseReg ( MachineInstr * MI , int64_t Offset ) const { return MI -> mayLoadOrStore ( ) ; } </s>

Returns true if the instruction 's frame index reference would be better served by a base register other than FP or SP .


<s> const uint32_t * TL45RegisterInfo :: getCallPreservedMask ( const MachineFunction & MF , CallingConv :: ID ) const { return CC_Save_RegMask ; } </s>

Return a mask of call-preserved registers for the given calling convention on the current function .


<s> InstructionCost AArch64TTIImpl :: getGatherScatterOpCost ( unsigned Opcode , Type * DataTy , const Value * Ptr , bool VariableMask , Align Alignment , TTI :: TargetCostKind CostKind , const Instruction * I ) { if ( ! isa < ScalableVectorType > ( DataTy ) ) return BaseT :: getGatherScatterOpCost ( Opcode , DataTy , Ptr , VariableMask , Alignment , CostKind , I ) ; auto * VT = cast < VectorType > ( DataTy ) ; auto LT = TLI -> getTypeLegalizationCost ( DL , DataTy ) ; if ( ! LT . first . isValid ( ) ) return InstructionCost :: getInvalid ( ) ; if ( cast < VectorType > ( DataTy ) -> getElementCount ( ) == ElementCount :: getScalable ( 1 ) ) return InstructionCost :: getInvalid ( ) ; ElementCount LegalVF = LT . second . getVectorElementCount ( ) ; InstructionCost MemOpCost = getMemoryOpCost ( Opcode , VT -> getElementType ( ) , Alignment , 0 , CostKind , I ) ; return LT . first * MemOpCost * getMaxNumElements ( LegalVF ) ; } </s>

Calculate the cost of Gather / Scatter operation .


"X86-64 PIC uses RIP relative addressing"

getGlobalBaseReg - Return a virtual register initialized with the the global base register value .


<s> EVT ARMTargetLowering :: getOptimalMemOpType ( uint64_t Size , unsigned DstAlign , unsigned SrcAlign , bool IsMemset , bool ZeroMemset , bool MemcpyStrSrc , const AttributeList & FuncAttributes ) const { if ( ( ! IsMemset || ZeroMemset ) && Subtarget -> hasNEON ( ) && ! FuncAttributes . hasFnAttribute ( Attribute :: NoImplicitFloat ) ) { bool Fast ; if ( Size >= 16 && ( memOpAlign ( SrcAlign , DstAlign , 16 ) || ( allowsMisalignedMemoryAccesses ( MVT :: v2f64 , 0 , 1 , MachineMemOperand :: MONone , & Fast ) && Fast ) ) ) { return MVT :: v2f64 ; } else if ( Size >= 8 && ( memOpAlign ( SrcAlign , DstAlign , 8 ) || ( allowsMisalignedMemoryAccesses ( MVT :: f64 , 0 , 1 , MachineMemOperand :: MONone , & Fast ) && Fast ) ) ) { return MVT :: f64 ; } } return MVT :: Other ; } </s>

It returns EVT : :Other if the type should be determined using generic target-independent logic .


<s>
static
void
nds32_asm_function_prologue
(
FILE
*
file
,
HOST_WIDE_INT
size
ATTRIBUTE_UNUSED
)
{
int
r
;
const
char
*
func_name
;
tree
attrs
;
tree
name
;
fprintf
(
file
,
"\t! BEGIN PROLOGUE\n"
)
;
fprintf
(
file
,
"\t!     fp needed: %d\n"
,
frame_pointer_needed
)
;
fprintf
(
file
,
"\t!  pretend_args: %d\n"
,
cfun
->
machine
->
va_args_size
)
;
fprintf
(
file
,
"\t!    local_size: %d\n"
,
cfun
->
machine
->
local_size
)
;
fprintf
(
file
,
"\t! out_args_size: %d\n"
,
cfun
->
machine
->
out_args_size
)
;
fprintf
(
file
,
"\t! registers ever_live: "
)
;
for
(
r
=
0
;
r
<
32
;
r
++
)
{
if
(
df_regs_ever_live_p
(
r
)
)
fprintf
(
file
,
"%s, "
,
reg_names
[
r
]
)
;
}
fputc
(
'\n'
,
file
)
;
fprintf
(
file
,
"\t! function attributes: "
)
;
attrs
=
DECL_ATTRIBUTES
(
current_function_decl
)
;
if
(
!
attrs
)
fprintf
(
file
,
"None"
)
;
func_name
=
IDENTIFIER_POINTER
(
DECL_NAME
(
current_function_decl
)
)
;
nds32_construct_isr_vectors_information
(
attrs
,
func_name
)
;
while
(
attrs
)
{
name
=
TREE_PURPOSE
(
attrs
)
;
fprintf
(
file
,
"%s "
,
IDENTIFIER_POINTER
(
name
)
)
;
attrs
=
TREE_CHAIN
(
attrs
)
;
}
fputc
(
'\n'
,
file
)
;
}
</s>

The content produced from this function will be placed before prologue body .

nds32
"\t! BEGIN PROLOGUE\n"
"\t!     fp needed: %d\n"
"\t!  pretend_args: %d\n"
"\t!    local_size: %d\n"
"\t! out_args_size: %d\n"
"\t! registers ever_live: "
0
32
"%s, "
"\t! function attributes: "
"None"
"%s "


<s> static unsigned int loongarch_build_integer ( struct loongarch_integer_op * codes , HOST_WIDE_INT value ) { unsigned int cost = 0 ; HOST_WIDE_INT low_part = ( int32_t ) value ; if ( IMM12_OPERAND ( low_part ) || IMM12_OPERAND_UNSIGNED ( low_part ) ) { codes [ cost ] . code = UNKNOWN ; codes [ cost ] . method = METHOD_NORMAL ; codes [ cost ] . value = low_part ; codes [ cost ] . curr_value = low_part ; cost ++ ; } else { codes [ cost ] . code = UNKNOWN ; codes [ cost ] . method = METHOD_NORMAL ; codes [ cost ] . value = low_part & ~ ( IMM_REACH - 1 ) ; codes [ cost ] . curr_value = codes [ cost ] . value ; cost ++ ; HOST_WIDE_INT iorv = low_part & ( IMM_REACH - 1 ) ; if ( iorv != 0 ) { codes [ cost ] . code = IOR ; codes [ cost ] . method = METHOD_NORMAL ; codes [ cost ] . value = iorv ; codes [ cost ] . curr_value = low_part ; cost ++ ; } } if ( TARGET_64BIT ) { bool lu32i [ 2 ] = { ( value & LU32I_B ) == 0 , ( value & LU32I_B ) == LU32I_B } ; bool lu52i [ 2 ] = { ( value & LU52I_B ) == 0 , ( value & LU52I_B ) == LU52I_B } ; int sign31 = ( value & ( HOST_WIDE_INT_1U << 31 ) ) >> 31 ; int sign51 = ( value & ( HOST_WIDE_INT_1U << 51 ) ) >> 51 ; if ( lu32i [ sign31 ] && lu52i [ sign31 ] ) return cost ; else if ( lu32i [ sign31 ] ) { codes [ cost ] . method = METHOD_LU52I ; codes [ cost ] . value = value & LU52I_B ; codes [ cost ] . curr_value = value ; return cost + 1 ; } codes [ cost ] . method = METHOD_LU32I ; codes [ cost ] . value = ( value & LU32I_B ) | ( sign51 ? LU52I_B : 0 ) ; codes [ cost ] . curr_value = ( value & 0xfffffffffffff ) | ( sign51 ? LU52I_B : 0 ) ; cost ++ ; if ( ! lu52i [ ( value & ( HOST_WIDE_INT_1U << 51 ) ) >> 51 ] ) { codes [ cost ] . method = METHOD_LU52I ; codes [ cost ] . value = value & LU52I_B ; codes [ cost ] . curr_value = value ; cost ++ ; } } gcc_assert ( cost <= LARCH_MAX_INTEGER_OPS ) ; return cost ; } </s>

Fill CODES with a sequence of rtl operations to load VALUE . Return the number of operations needed .


Check if NAME must be replaced by a DEX expression .


runOnMachineFunction - Emit the function body .


<s> HexagonPLT1 * HexagonPLT :: create ( ) { return new HexagonPLT1 ( * m_pSectionData ) ; } </s>


<s> void relaxInstruction ( const MCInst & Inst , const MCSubtargetInfo & STI , MCInst & Res ) const override { } </s>

Relax the instruction in the given fragment to the next wider instruction .


<s> TargetPassConfig * BPFTargetMachine :: createPassConfig ( PassManagerBase & PM ) { return new BPFPassConfig ( this , PM ) ; } </s>

Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of CodeGen passes .


<s> void frv_split_double_store ( rtx dest , rtx source ) { rtx dest1 = change_address ( dest , SImode , NULL ) ; rtx dest2 = frv_index_memory ( dest , SImode , 1 ) ; if ( ZERO_P ( source ) ) { emit_move_insn ( dest1 , CONST0_RTX ( SImode ) ) ; emit_move_insn ( dest2 , CONST0_RTX ( SImode ) ) ; } else { emit_move_insn ( dest1 , gen_highpart ( SImode , source ) ) ; emit_move_insn ( dest2 , gen_lowpart ( SImode , source ) ) ; } } </s>

Split ( set DEST SOURCE ) , where DEST refers to a dword memory location and SOURCE is either a double register or the constant zero .


<s> void X86InstrInfo :: loadRegFromStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , Register DestReg , int FrameIdx , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { const MachineFunction & MF = * MBB . getParent ( ) ; unsigned Alignment = std :: max < uint32_t > ( TRI -> getSpillSize ( * RC ) , 16 ) ; bool isAligned = ( Subtarget . getFrameLowering ( ) -> getStackAlignment ( ) >= Alignment ) || RI . canRealignStack ( MF ) ; unsigned Opc = getLoadRegOpcode ( DestReg , RC , isAligned , Subtarget ) ; addFrameReference ( BuildMI ( MBB , MI , DebugLoc ( ) , get ( Opc ) , DestReg ) , FrameIdx ) ; } </s>

Load the specified register of the given register class from the specified stack frame index .


<s> bool MipsTargetObjectFile :: IsGlobalInSmallSection ( const GlobalObject * GO , const TargetMachine & TM , SectionKind Kind ) const { return IsGlobalInSmallSectionImpl ( GO , TM ) && ( Kind . isData ( ) || Kind . isBSS ( ) || Kind . isCommon ( ) || Kind . isReadOnly ( ) ) ; } </s>

Return true if this global address should be placed into small data/bss section .


<s> static bool mn10300_asm_output_addr_const_extra ( FILE * file , rtx x ) { if ( GET_CODE ( x ) == UNSPEC ) { switch ( XINT ( x , 1 ) ) { case UNSPEC_PIC : output_addr_const ( file , XVECEXP ( x , 0 , 0 ) ) ; break ; case UNSPEC_GOT : output_addr_const ( file , XVECEXP ( x , 0 , 0 ) ) ; fputs ( "@GOT" , file ) ; break ; case UNSPEC_GOTOFF : output_addr_const ( file , XVECEXP ( x , 0 , 0 ) ) ; fputs ( "@GOTOFF" , file ) ; break ; case UNSPEC_PLT : output_addr_const ( file , XVECEXP ( x , 0 , 0 ) ) ; fputs ( "@PLT" , file ) ; break ; case UNSPEC_GOTSYM_OFF : assemble_name ( file , GOT_SYMBOL_NAME ) ; fputs ( "-(" , file ) ; output_addr_const ( file , XVECEXP ( x , 0 , 0 ) ) ; fputs ( "-.)" , file ) ; break ; default : return false ; } return true ; } else return false ; } </s>

Implement TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA . Used for PIC-specific UNSPECs .


<s> rtx expand ( function_expander & e ) const override { for ( unsigned int i = 0 ; i < 2 ; ++ i ) e . args [ i ] = e . convert_to_pmode ( e . args [ i ] ) ; return e . use_exact_insn ( code_for_while ( m_unspec , Pmode , e . gp_mode ( 0 ) ) ) ; } </s>


"Custom lowering not defined for operation"

LowerOperation - Provide custom lowering hooks for some operations .


<s> unsigned getNumFixupKinds ( ) const { return PPC :: NumTargetFixupKinds ; } </s>

Get the number of target specific fixup kinds .


<s> void microblaze_cpp_define ( cpp_reader * pfile ) { builtin_assert ( "cpu=microblaze" ) ; builtin_assert ( "machine=microblaze" ) ; builtin_define ( "__MICROBLAZE__" ) ; builtin_define ( "__microblaze__" ) ; if ( TARGET_LITTLE_ENDIAN ) { builtin_define ( "_LITTLE_ENDIAN" ) ; builtin_define ( "__LITTLE_ENDIAN__" ) ; builtin_define ( "__MICROBLAZEEL__" ) ; } else { builtin_define ( "_BIG_ENDIAN" ) ; builtin_define ( "__BIG_ENDIAN__" ) ; builtin_define ( "__MICROBLAZEEB__" ) ; } if ( ! TARGET_SOFT_MUL ) { if ( ! flag_iso ) builtin_define ( "HAVE_HW_MUL" ) ; builtin_define ( "__HAVE_HW_MUL__" ) ; } if ( TARGET_MULTIPLY_HIGH ) { if ( ! flag_iso ) builtin_define ( "HAVE_HW_MUL_HIGH" ) ; builtin_define ( "__HAVE_HW_MUL_HIGH__" ) ; } if ( ! TARGET_SOFT_DIV ) { if ( ! flag_iso ) builtin_define ( "HAVE_HW_DIV" ) ; builtin_define ( "__HAVE_HW_DIV__" ) ; } if ( TARGET_BARREL_SHIFT ) { if ( ! flag_iso ) builtin_define ( "HAVE_HW_BSHIFT" ) ; builtin_define ( "__HAVE_HW_BSHIFT__" ) ; } if ( TARGET_PATTERN_COMPARE ) { if ( ! flag_iso ) builtin_define ( "HAVE_HW_PCMP" ) ; builtin_define ( "__HAVE_HW_PCMP__" ) ; } if ( TARGET_HARD_FLOAT ) { if ( ! flag_iso ) builtin_define ( "HAVE_HW_FPU" ) ; builtin_define ( "__HAVE_HW_FPU__" ) ; } if ( TARGET_FLOAT_CONVERT ) { if ( ! flag_iso ) builtin_define ( "HAVE_HW_FPU_CONVERT" ) ; builtin_define ( "__HAVE_HW_FPU_CONVERT__" ) ; } if ( TARGET_FLOAT_SQRT ) { if ( ! flag_iso ) builtin_define ( "HAVE_HW_FPU_SQRT" ) ; builtin_define ( "__HAVE_HW_FPU_SQRT__" ) ; } } </s>

Define preprocessor symbols for MicroBlaze . Symbols which do not start with __ are deprecated .


<s> void HexagonTTIImpl :: getPeelingPreferences ( Loop * L , ScalarEvolution & SE , TTI :: PeelingPreferences & PP ) { BaseT :: getPeelingPreferences ( L , SE , PP ) ; if ( L && L -> empty ( ) && canPeel ( L ) && SE . getSmallConstantTripCount ( L ) == 0 && SE . getSmallConstantMaxTripCount ( L ) > 0 && SE . getSmallConstantMaxTripCount ( L ) <= 5 ) { PP . PeelCount = 2 ; } } </s>

Get target-customized preferences for the generic loop peeling transformation .


<s> const SparcSubtarget * SparcTargetMachine :: getSubtargetImpl ( const Function & F ) const { Attribute CPUAttr = F . getFnAttribute ( "target-cpu" ) ; Attribute FSAttr = F . getFnAttribute ( "target-features" ) ; std :: string CPU = ! CPUAttr . hasAttribute ( Attribute :: None ) ? CPUAttr . getValueAsString ( ) . str ( ) : TargetCPU ; std :: string FS = ! FSAttr . hasAttribute ( Attribute :: None ) ? FSAttr . getValueAsString ( ) . str ( ) : TargetFS ; bool softFloat = F . hasFnAttribute ( "use-soft-float" ) && F . getFnAttribute ( "use-soft-float" ) . getValueAsString ( ) == "true" ; if ( softFloat ) FS += FS . empty ( ) ? "+soft-float" : ",+soft-float" ; auto & I = SubtargetMap [ CPU + FS ] ; if ( ! I ) { resetTargetOptions ( F ) ; I = std :: make_unique < SparcSubtarget > ( TargetTriple , CPU , FS , * this , this -> is64Bit ) ; } return I . get ( ) ; } </s>

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .

Sparc Sparc Sparc "target-cpu" "target-features" "use-soft-float" "use-soft-float" "true" "+soft-float" ",+soft-float" Sparc


<s> static machine_mode mips_promote_function_mode ( const_tree type ATTRIBUTE_UNUSED , machine_mode mode , int * punsignedp ATTRIBUTE_UNUSED , const_tree fntype ATTRIBUTE_UNUSED , int for_return ATTRIBUTE_UNUSED ) { int unsignedp ; if ( type != NULL_TREE ) return promote_mode ( type , mode , punsignedp ) ; unsignedp = * punsignedp ; PROMOTE_MODE ( mode , unsignedp , type ) ; * punsignedp = unsignedp ; return mode ; } </s>


<s> bool ia64_expand_vecint_minmax ( enum rtx_code code , machine_mode mode , rtx operands [ ] ) { rtx xops [ 6 ] ; if ( mode == V8QImode && ( code == UMIN || code == UMAX ) ) return false ; if ( mode == V4HImode && ( code == SMIN || code == SMAX ) ) return false ; if ( mode == V4HImode && code == UMAX ) { rtx x , tmp = gen_reg_rtx ( mode ) ; x = gen_rtx_US_MINUS ( mode , operands [ 1 ] , operands [ 2 ] ) ; emit_insn ( gen_rtx_SET ( tmp , x ) ) ; emit_insn ( gen_addv4hi3 ( operands [ 0 ] , tmp , operands [ 2 ] ) ) ; return true ; } xops [ 0 ] = operands [ 0 ] ; xops [ 4 ] = xops [ 1 ] = operands [ 1 ] ; xops [ 5 ] = xops [ 2 ] = operands [ 2 ] ; switch ( code ) { case UMIN : code = LTU ; break ; case UMAX : code = GTU ; break ; case SMIN : code = LT ; break ; case SMAX : code = GT ; break ; default : gcc_unreachable ( ) ; } xops [ 3 ] = gen_rtx_fmt_ee ( code , VOIDmode , operands [ 1 ] , operands [ 2 ] ) ; ia64_expand_vecint_cmov ( xops ) ; return true ; } </s>

Emit an integral vector min or max operation . Return true if all done .


<s> void ARMELFStreamer :: Reset ( ) { ExTab = nullptr ; FnStart = nullptr ; Personality = nullptr ; PersonalityIndex = ARM :: EHABI :: NUM_PERSONALITY_INDEX ; FPReg = ARM :: SP ; FPOffset = 0 ; SPOffset = 0 ; PendingOffset = 0 ; UsedFP = false ; CantUnwind = false ; Opcodes . clear ( ) ; UnwindOpAsm . Reset ( ) ; } </s>


Check OP is a legal scalar immediate for the MOVI instruction .


<s> static rtx msp430_addr_space_convert ( rtx op , tree from_type , tree to_type ) { addr_space_t from_as = TYPE_ADDR_SPACE ( TREE_TYPE ( from_type ) ) ; addr_space_t to_as = TYPE_ADDR_SPACE ( TREE_TYPE ( to_type ) ) ; rtx result ; if ( to_as != ADDR_SPACE_FAR && from_as == ADDR_SPACE_FAR ) { if ( CONSTANT_P ( op ) ) return gen_rtx_CONST ( HImode , op ) ; result = gen_reg_rtx ( HImode ) ; emit_insn ( gen_truncpsihi2 ( result , op ) ) ; return result ; } else if ( to_as == ADDR_SPACE_FAR && from_as != ADDR_SPACE_FAR ) { if ( CONSTANT_P ( op ) ) return gen_rtx_CONST ( PSImode , op ) ; result = gen_reg_rtx ( PSImode ) ; emit_insn ( gen_zero_extendhipsi2 ( result , op ) ) ; return result ; } else gcc_unreachable ( ) ; } </s>

Convert from one address space to another .


<s> SparcSubtarget & SparcSubtarget :: initializeSubtargetDependencies ( StringRef CPU , StringRef FS ) { IsV9 = false ; IsLeon = false ; V8DeprecatedInsts = false ; IsVIS = false ; HasHardQuad = false ; UsePopc = false ; UseSoftFloat = false ; HasLeonCasa = false ; HasUmacSmac = false ; InsertNOPLoad = false ; FixFSMULD = false ; ReplaceFMULS = false ; FixAllFDIVSQRT = false ; std :: string CPUName = CPU ; if ( CPUName . empty ( ) ) CPUName = ( Is64Bit ) ? "v9" : "v8" ; ParseSubtargetFeatures ( CPUName , FS ) ; if ( ! IsV9 ) UsePopc = false ; return * this ; } </s>

initializeSubtargetDependencies - Initializes using a CPU , a TuneCPU , and feature string so that we can use initializer lists for subtarget initialization .


<s> void Thumb2InstrInfo :: ReplaceTailWithBranchTo ( MachineBasicBlock :: iterator Tail , MachineBasicBlock * NewDest ) const { MachineBasicBlock * MBB = Tail -> getParent ( ) ; ARMFunctionInfo * AFI = MBB -> getParent ( ) -> getInfo < ARMFunctionInfo > ( ) ; if ( ! AFI -> hasITBlocks ( ) || Tail -> isBranch ( ) ) { TargetInstrInfo :: ReplaceTailWithBranchTo ( Tail , NewDest ) ; return ; } unsigned PredReg = 0 ; ARMCC :: CondCodes CC = getInstrPredicate ( * Tail , PredReg ) ; MachineBasicBlock :: iterator MBBI = Tail ; if ( CC != ARMCC :: AL ) -- MBBI ; TargetInstrInfo :: ReplaceTailWithBranchTo ( Tail , NewDest ) ; if ( CC != ARMCC :: AL ) { MachineBasicBlock :: iterator E = MBB -> begin ( ) ; unsigned Count = 4 ; while ( Count && MBBI != E ) { if ( MBBI -> isDebugValue ( ) ) { -- MBBI ; continue ; } if ( MBBI -> getOpcode ( ) == ARM :: t2IT ) { unsigned Mask = MBBI -> getOperand ( 1 ) . getImm ( ) ; if ( Count == 4 ) MBBI -> eraseFromParent ( ) ; else { unsigned MaskOn = 1 << Count ; unsigned MaskOff = ~ ( MaskOn - 1 ) ; MBBI -> getOperand ( 1 ) . setImm ( ( Mask & MaskOff ) | MaskOn ) ; } return ; } -- MBBI ; -- Count ; } } } </s>

Delete the instruction OldInst and everything after it , replacing it with an unconditional branch to NewDest .


<s>
bool
X86CallFrameOptimization
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
STI
=
&
MF
.
getSubtarget
<
X86Subtarget
>
(
)
;
TII
=
STI
->
getInstrInfo
(
)
;
TFL
=
STI
->
getFrameLowering
(
)
;
MRI
=
&
MF
.
getRegInfo
(
)
;
const
X86RegisterInfo
&
RegInfo
=
*
static_cast
<
const
X86RegisterInfo
*
>
(
STI
->
getRegisterInfo
(
)
)
;
SlotSize
=
RegInfo
.
getSlotSize
(
)
;
assert
(
isPowerOf2_32
(
SlotSize
)
&&
"Expect power of 2 stack slot size"
)
;
Log2SlotSize
=
Log2_32
(
SlotSize
)
;
if
(
skipFunction
(
MF
.
getFunction
(
)
)
||
!
isLegal
(
MF
)
)
return
false
;
unsigned
FrameSetupOpcode
=
TII
->
getCallFrameSetupOpcode
(
)
;
bool
Changed
=
false
;
ContextVector
CallSeqVector
;
for
(
auto
&
MBB
:
MF
)
for
(
auto
&
MI
:
MBB
)
if
(
MI
.
getOpcode
(
)
==
FrameSetupOpcode
)
{
CallContext
Context
;
collectCallInfo
(
MF
,
MBB
,
MI
,
Context
)
;
CallSeqVector
.
push_back
(
Context
)
;
}
if
(
!
isProfitable
(
MF
,
CallSeqVector
)
)
return
false
;
for
(
auto
CC
:
CallSeqVector
)
{
if
(
CC
.
UsePush
)
{
adjustCallSequence
(
MF
,
CC
)
;
Changed
=
true
;
}
}
return
Changed
;
}
</s>

runOnMachineFunction - Emit the function body .


"Cannot load this register from a stack slot!"


"SIInstrInfo::storeRegToStackSlot - Do not know how to"

Store the specified register of the given register class to the specified stack frame index .


<s> static bool arm_return_in_memory ( const_tree type , const_tree fntype ) { HOST_WIDE_INT size ; size = int_size_in_bytes ( type ) ; if ( TARGET_AAPCS_BASED ) { if ( ! AGGREGATE_TYPE_P ( type ) && TREE_CODE ( type ) != VECTOR_TYPE && TREE_CODE ( type ) != COMPLEX_TYPE ) return false ; if ( ( ( unsigned HOST_WIDE_INT ) size ) <= UNITS_PER_WORD ) return false ; if ( aapcs_select_return_coproc ( type , fntype ) >= 0 ) return false ; if ( TREE_CODE ( type ) == VECTOR_TYPE ) return ( size < 0 || size > ( 4 * UNITS_PER_WORD ) ) ; return true ; } if ( TREE_CODE ( type ) == VECTOR_TYPE ) return ( size < 0 || size > ( 4 * UNITS_PER_WORD ) ) ; if ( ! AGGREGATE_TYPE_P ( type ) && ( TREE_CODE ( type ) != VECTOR_TYPE ) ) return false ; if ( arm_abi != ARM_ABI_APCS ) { return ( size < 0 || size > UNITS_PER_WORD ) ; } if ( size < 0 || size > UNITS_PER_WORD ) return true ; if ( TREE_CODE ( type ) == RECORD_TYPE ) { tree field ; for ( field = TYPE_FIELDS ( type ) ; field && TREE_CODE ( field ) != FIELD_DECL ; field = DECL_CHAIN ( field ) ) continue ; if ( field == NULL ) return false ; if ( FLOAT_TYPE_P ( TREE_TYPE ( field ) ) ) return true ; if ( arm_return_in_memory ( TREE_TYPE ( field ) , NULL_TREE ) ) return true ; for ( field = DECL_CHAIN ( field ) ; field ; field = DECL_CHAIN ( field ) ) { if ( TREE_CODE ( field ) != FIELD_DECL ) continue ; if ( ! DECL_BIT_FIELD_TYPE ( field ) ) return true ; } return false ; } if ( TREE_CODE ( type ) == UNION_TYPE ) { tree field ; for ( field = TYPE_FIELDS ( type ) ; field ; field = DECL_CHAIN ( field ) ) { if ( TREE_CODE ( field ) != FIELD_DECL ) continue ; if ( FLOAT_TYPE_P ( TREE_TYPE ( field ) ) ) return true ; if ( arm_return_in_memory ( TREE_TYPE ( field ) , NULL_TREE ) ) return true ; } return false ; } return true ; } </s>

Decide whether a type should be returned in memory ( true ) or in a register ( false ) . This is called by the macro RETURN_IN_MEMORY .


<s> bool quad_address_p ( rtx addr , machine_mode mode , bool strict ) { rtx op0 , op1 ; if ( GET_MODE_SIZE ( mode ) != 16 ) return false ; if ( legitimate_indirect_address_p ( addr , strict ) ) return true ; if ( VECTOR_MODE_P ( mode ) && ! mode_supports_dq_form ( mode ) ) return false ; if ( GET_CODE ( addr ) != PLUS ) return false ; op0 = XEXP ( addr , 0 ) ; if ( ! REG_P ( op0 ) || ! INT_REG_OK_FOR_BASE_P ( op0 , strict ) ) return false ; op1 = XEXP ( addr , 1 ) ; if ( ! CONST_INT_P ( op1 ) ) return false ; return quad_address_offset_p ( INTVAL ( op1 ) ) ; } </s>

Return true if the ADDR is an acceptable address for a quad memory operation of mode MODE ( either LQ/STQ for general purpose registers , or LXV/STXV for vector registers under ISA 3.0 . GPR_P is true if this address is intended for LQ/STQ . If it is false , the address is intended for the ISA 3.0 LXV/STXV instruction .


<s> static void mips_arg_info ( const CUMULATIVE_ARGS * cum , enum machine_mode mode , tree type , int named , struct mips_arg_info * info ) { bool doubleword_aligned_p ; unsigned int num_bytes , num_words , max_regs ; num_bytes = type ? int_size_in_bytes ( type ) : GET_MODE_SIZE ( mode ) ; num_words = ( num_bytes + UNITS_PER_WORD - 1 ) / UNITS_PER_WORD ; switch ( mips_abi ) { case ABI_EABI : info -> fpr_p = ( ( GET_MODE_CLASS ( mode ) == MODE_FLOAT || GET_MODE_CLASS ( mode ) == MODE_VECTOR_FLOAT ) && GET_MODE_SIZE ( mode ) <= UNITS_PER_FPVALUE ) ; break ; case ABI_32 : case ABI_O64 : info -> fpr_p = ( ! cum -> gp_reg_found && cum -> arg_number < 2 && ( type == 0 || SCALAR_FLOAT_TYPE_P ( type ) || VECTOR_FLOAT_TYPE_P ( type ) ) && ( GET_MODE_CLASS ( mode ) == MODE_FLOAT || GET_MODE_CLASS ( mode ) == MODE_VECTOR_FLOAT ) && GET_MODE_SIZE ( mode ) <= UNITS_PER_FPVALUE ) ; break ; case ABI_N32 : case ABI_64 : info -> fpr_p = ( named && ( type == 0 || FLOAT_TYPE_P ( type ) ) && ( GET_MODE_CLASS ( mode ) == MODE_FLOAT || GET_MODE_CLASS ( mode ) == MODE_COMPLEX_FLOAT || GET_MODE_CLASS ( mode ) == MODE_VECTOR_FLOAT ) && GET_MODE_UNIT_SIZE ( mode ) <= UNITS_PER_FPVALUE ) ; if ( info -> fpr_p && GET_MODE_CLASS ( mode ) == MODE_COMPLEX_FLOAT && GET_MODE_UNIT_SIZE ( mode ) < UNITS_PER_FPVALUE ) { if ( cum -> num_gprs >= MAX_ARGS_IN_REGISTERS - 1 ) info -> fpr_p = false ; else num_words = 2 ; } break ; default : gcc_unreachable ( ) ; } doubleword_aligned_p = FUNCTION_ARG_BOUNDARY ( mode , type ) > BITS_PER_WORD ; info -> reg_offset = ( mips_abi == ABI_EABI && info -> fpr_p ? cum -> num_fprs : cum -> num_gprs ) ; if ( doubleword_aligned_p ) info -> reg_offset += info -> reg_offset & 1 ; info -> stack_offset = cum -> stack_words ; if ( doubleword_aligned_p ) info -> stack_offset += info -> stack_offset & 1 ; max_regs = MAX_ARGS_IN_REGISTERS - info -> reg_offset ; info -> reg_words = MIN ( num_words , max_regs ) ; info -> stack_words = num_words - info -> reg_words ; } </s>

Fill INFO with information about a single argument . CUM is the cumulative state for earlier arguments . MODE is the mode of this argument and TYPE is its type ( if known ) . NAMED is true if this is a named ( fixed ) argument rather than a variable one .


<s> bool X86PassConfig :: addInstSelector ( ) { PM . add ( createX86ISelDag ( getX86TargetMachine ( ) , getOptLevel ( ) ) ) ; if ( ! getX86Subtarget ( ) . is64Bit ( ) ) PM . add ( createGlobalBaseRegPass ( ) ) ; return false ; } </s>

addInstSelector - This method should install an instruction selector pass , which converts from LLVM code to machine instructions .


<s> static rtx aarch64_extend_bitfield_pattern_p ( rtx x ) { rtx_code outer_code = GET_CODE ( x ) ; machine_mode outer_mode = GET_MODE ( x ) ; if ( outer_code != ZERO_EXTEND && outer_code != SIGN_EXTEND && outer_mode != SImode && outer_mode != DImode ) return NULL_RTX ; rtx inner = XEXP ( x , 0 ) ; rtx_code inner_code = GET_CODE ( inner ) ; machine_mode inner_mode = GET_MODE ( inner ) ; rtx op = NULL_RTX ; switch ( inner_code ) { case ASHIFT : if ( CONST_INT_P ( XEXP ( inner , 1 ) ) && ( inner_mode == QImode || inner_mode == HImode ) ) op = XEXP ( inner , 0 ) ; break ; case LSHIFTRT : if ( outer_code == ZERO_EXTEND && CONST_INT_P ( XEXP ( inner , 1 ) ) && ( inner_mode == QImode || inner_mode == HImode ) ) op = XEXP ( inner , 0 ) ; break ; case ASHIFTRT : if ( outer_code == SIGN_EXTEND && CONST_INT_P ( XEXP ( inner , 1 ) ) && ( inner_mode == QImode || inner_mode == HImode ) ) op = XEXP ( inner , 0 ) ; break ; default : break ; } return op ; } </s>

Check whether X is a bitfield operation of the form shift + extend that maps down to a UBFIZ/SBFIZ/UBFX/SBFX instruction . If so , return the operand to which the bitfield operation is applied . Otherwise return NULL_RTX .


<s> static bool aarch64_evpc_uzp ( struct expand_vec_perm_d * d ) { HOST_WIDE_INT odd ; rtx out , in0 , in1 , x ; machine_mode vmode = d -> vmode ; if ( GET_MODE_UNIT_SIZE ( vmode ) > 8 ) return false ; if ( ! d -> perm [ 0 ] . is_constant ( & odd ) || ( odd != 0 && odd != 1 ) || ! d -> perm . series_p ( 0 , 1 , odd , 2 ) ) return false ; if ( d -> testing_p ) return true ; in0 = d -> op0 ; in1 = d -> op1 ; if ( BYTES_BIG_ENDIAN && d -> vec_flags == VEC_ADVSIMD ) { x = in0 , in0 = in1 , in1 = x ; odd = ! odd ; } out = d -> target ; emit_set_insn ( out , gen_rtx_UNSPEC ( vmode , gen_rtvec ( 2 , in0 , in1 ) , odd ? UNSPEC_UZP2 : UNSPEC_UZP1 ) ) ; return true ; } </s>

Recognize patterns suitable for the UZP instructions .


<s> void or1k_expand_atomic_op ( rtx_code code , rtx mem , rtx val , rtx orig_before , rtx orig_after ) { machine_mode mode = GET_MODE ( mem ) ; rtx before = orig_before , after = orig_after ; rtx label ; label = gen_rtx_LABEL_REF ( VOIDmode , gen_label_rtx ( ) ) ; emit_label ( XEXP ( label , 0 ) ) ; if ( before == NULL_RTX ) before = gen_reg_rtx ( mode ) ; emit_load_locked ( mode , before , mem ) ; if ( code == MULT ) { after = expand_binop ( mode , and_optab , before , val , after , 1 , OPTAB_LIB_WIDEN ) ; after = expand_unop ( mode , one_cmpl_optab , after , after , 1 ) ; } else after = expand_simple_binop ( mode , code , before , val , after , 1 , OPTAB_LIB_WIDEN ) ; emit_store_conditional ( mode , mem , after ) ; emit_unlikely_jump ( EQ , label ) ; if ( orig_before ) emit_move_insn ( orig_before , before ) ; if ( orig_after ) emit_move_insn ( orig_after , after ) ; } </s>

Expand an atomic fetch-and-operate pattern . CODE is the binary operation to perform ( with MULT as a stand-in for NAND ) . MEM is the memory on which to operate . VAL is the second operand of the binary operator . BEFORE and AFTER are optional locations to return the value of MEM either before of after the operation .


<s> AliasResult AMDGPUAAResult :: alias ( const MemoryLocation & LocA , const MemoryLocation & LocB , AAQueryInfo & AAQI ) { unsigned asA = LocA . Ptr -> getType ( ) -> getPointerAddressSpace ( ) ; unsigned asB = LocB . Ptr -> getType ( ) -> getPointerAddressSpace ( ) ; AliasResult Result = getAliasResult ( asA , asB ) ; if ( Result == AliasResult :: NoAlias ) return Result ; MemoryLocation A = LocA ; MemoryLocation B = LocB ; if ( asA != AMDGPUAS :: FLAT_ADDRESS ) { std :: swap ( asA , asB ) ; std :: swap ( A , B ) ; } if ( asA == AMDGPUAS :: FLAT_ADDRESS && ( asB == AMDGPUAS :: LOCAL_ADDRESS || asB == AMDGPUAS :: PRIVATE_ADDRESS ) ) { const auto * ObjA = getUnderlyingObject ( A . Ptr -> stripPointerCastsForAliasAnalysis ( ) ) ; if ( const LoadInst * LI = dyn_cast < LoadInst > ( ObjA ) ) { if ( LI -> getPointerAddressSpace ( ) == AMDGPUAS :: CONSTANT_ADDRESS ) return AliasResult :: NoAlias ; } else if ( const Argument * Arg = dyn_cast < Argument > ( ObjA ) ) { const Function * F = Arg -> getParent ( ) ; switch ( F -> getCallingConv ( ) ) { case CallingConv :: AMDGPU_KERNEL : return AliasResult :: NoAlias ; default : break ; } } } return AAResultBase :: alias ( LocA , LocB , AAQI ) ; } </s>

alias - If one of the pointers is to a global that we are tracking , and the other is some random pointer , we know there can not be an alias , because the address of the global is n't taken .

AMDGPU AMDGPU AMDGPU AMDGPU AMDGPU AMDGPU AMDGPU AMDGPU


<s> virtual bool doInitialization ( Module & M ) { return false ; } </s>

Set up the AsmPrinter when we are working on a new module .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . addRequired < TargetPassConfig > ( ) ; AU . addPreserved < StackProtector > ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> const char * AMDGPUTargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( Opcode ) { default : return 0 ; NODE_NAME_CASE ( CALL ) ; NODE_NAME_CASE ( UMUL ) ; NODE_NAME_CASE ( DIV_INF ) ; NODE_NAME_CASE ( RET_FLAG ) ; NODE_NAME_CASE ( BRANCH_COND ) ; NODE_NAME_CASE ( DWORDADDR ) NODE_NAME_CASE ( FRACT ) NODE_NAME_CASE ( FMAX ) NODE_NAME_CASE ( SMAX ) NODE_NAME_CASE ( UMAX ) NODE_NAME_CASE ( FMIN ) NODE_NAME_CASE ( SMIN ) NODE_NAME_CASE ( UMIN ) NODE_NAME_CASE ( URECIP ) NODE_NAME_CASE ( EXPORT ) NODE_NAME_CASE ( CONST_ADDRESS ) NODE_NAME_CASE ( REGISTER_LOAD ) NODE_NAME_CASE ( REGISTER_STORE ) } } </s>

getTargetNodeName - This method returns the name of a target specific


<s> AliasResult TPCAAResult :: alias ( const MemoryLocation & LocA , const MemoryLocation & LocB , AAQueryInfo & AAQI ) { unsigned asA = LocA . Ptr -> getType ( ) -> getPointerAddressSpace ( ) ; unsigned asB = LocB . Ptr -> getType ( ) -> getPointerAddressSpace ( ) ; AliasResult Result = getAliasResult ( asA , asB ) ; if ( Result == NoAlias ) return Result ; if ( asA != asB && asA != 0 && asB != 0 ) return NoAlias ; return AAResultBase :: alias ( LocA , LocB , AAQI ) ; } </s>


"Return instruction can only reference SP relative frame objects"

"Requesting 64-bit offset in 32-bit immediate!"

This method must be overriden to eliminate abstract frame indices from instructions which may use them .


<s> static void allocateSpecialInputVGPRs ( CCState & CCInfo , MachineFunction & MF , const SIRegisterInfo & TRI , SIMachineFunctionInfo & Info ) { const unsigned Mask = 0x3ff ; ArgDescriptor Arg ; if ( Info . hasWorkItemIDX ( ) ) { Arg = allocateVGPR32Input ( CCInfo , Mask ) ; Info . setWorkItemIDX ( Arg ) ; } if ( Info . hasWorkItemIDY ( ) ) { Arg = allocateVGPR32Input ( CCInfo , Mask << 10 , Arg ) ; Info . setWorkItemIDY ( Arg ) ; } if ( Info . hasWorkItemIDZ ( ) ) Info . setWorkItemIDZ ( allocateVGPR32Input ( CCInfo , Mask << 20 , Arg ) ) ; } </s>

Allocate implicit function VGPR arguments at the end of allocated user arguments .