<s> static bool is_prefetch ( rtx_insn * insn ) { return NONJUMP_INSN_P ( insn ) && GET_CODE ( PATTERN ( insn ) ) == PREFETCH ; } </s>

Return true if insn is a prefetch instruction .


<s> const X86InstrInfo * getInstrInfo ( ) const { return & InstrInfo ; } </s>


<s> void ix86_split_copysign_const ( rtx operands [ ] ) { enum machine_mode mode , vmode ; rtx dest , op0 , op1 , mask , x ; dest = operands [ 0 ] ; op0 = operands [ 1 ] ; op1 = operands [ 2 ] ; mask = operands [ 3 ] ; mode = GET_MODE ( dest ) ; vmode = GET_MODE ( mask ) ; dest = simplify_gen_subreg ( vmode , dest , mode , 0 ) ; x = gen_rtx_AND ( vmode , dest , mask ) ; emit_insn ( gen_rtx_SET ( VOIDmode , dest , x ) ) ; if ( op0 != CONST0_RTX ( vmode ) ) { x = gen_rtx_IOR ( vmode , dest , op0 ) ; emit_insn ( gen_rtx_SET ( VOIDmode , dest , x ) ) ; } } </s>

Deconstruct a copysign operation into bit masks . Operand 0 is known to be a constant , and so has already been expanded into a vector constant .


<s> bool AArch64FastISel :: fastSelectInstruction ( const Instruction * I ) { switch ( I -> getOpcode ( ) ) { default : break ; case Instruction :: Add : case Instruction :: Sub : return selectAddSub ( I ) ; case Instruction :: Mul : return selectMul ( I ) ; case Instruction :: SDiv : return selectSDiv ( I ) ; case Instruction :: SRem : if ( ! selectBinaryOp ( I , ISD :: SREM ) ) return selectRem ( I , ISD :: SREM ) ; return true ; case Instruction :: URem : if ( ! selectBinaryOp ( I , ISD :: UREM ) ) return selectRem ( I , ISD :: UREM ) ; return true ; case Instruction :: Shl : case Instruction :: LShr : case Instruction :: AShr : return selectShift ( I ) ; case Instruction :: And : case Instruction :: Or : case Instruction :: Xor : return selectLogicalOp ( I ) ; case Instruction :: Br : return selectBranch ( I ) ; case Instruction :: IndirectBr : return selectIndirectBr ( I ) ; case Instruction :: BitCast : if ( ! FastISel :: selectBitCast ( I ) ) return selectBitCast ( I ) ; return true ; case Instruction :: FPToSI : if ( ! selectCast ( I , ISD :: FP_TO_SINT ) ) return selectFPToInt ( I , true ) ; return true ; case Instruction :: FPToUI : return selectFPToInt ( I , false ) ; case Instruction :: ZExt : case Instruction :: SExt : return selectIntExt ( I ) ; case Instruction :: Trunc : if ( ! selectCast ( I , ISD :: TRUNCATE ) ) return selectTrunc ( I ) ; return true ; case Instruction :: FPExt : return selectFPExt ( I ) ; case Instruction :: FPTrunc : return selectFPTrunc ( I ) ; case Instruction :: SIToFP : if ( ! selectCast ( I , ISD :: SINT_TO_FP ) ) return selectIntToFP ( I , true ) ; return true ; case Instruction :: UIToFP : return selectIntToFP ( I , false ) ; case Instruction :: Load : return selectLoad ( I ) ; case Instruction :: Store : return selectStore ( I ) ; case Instruction :: FCmp : case Instruction :: ICmp : return selectCmp ( I ) ; case Instruction :: Select : return selectSelect ( I ) ; case Instruction :: Ret : return selectRet ( I ) ; case Instruction :: FRem : return selectFRem ( I ) ; } return selectOperator ( I , I -> getOpcode ( ) ) ; ( void ) & CC_AArch64_DarwinPCS_VarArg ; } </s>

This method is called by target-independent code when the normal FastISel process fails to select an instruction .


<s> char c6x_get_unit_specifier ( rtx_insn * insn ) { enum attr_units units ; if ( insn_info . exists ( ) ) { int unit = INSN_INFO_ENTRY ( INSN_UID ( insn ) ) . reservation ; return c6x_unit_names [ unit ] [ 0 ] ; } units = get_attr_units ( insn ) ; switch ( units ) { case UNITS_D : case UNITS_DL : case UNITS_DS : case UNITS_DLS : case UNITS_D_ADDR : return 'd' ; case UNITS_L : case UNITS_LS : return 'l' ; case UNITS_S : return 's' ; case UNITS_M : return 'm' ; default : gcc_unreachable ( ) ; } } </s>

Return a single character , which is either ' l ' , 's ' , 'd ' or 'm ' , which specifies the functional unit used by INSN .


<s> bool X86PassConfig :: addIRTranslator ( ) { addPass ( new IRTranslator ( getOptLevel ( ) ) ) ; return false ; } </s>

This method should install an IR translator pass , which converts from LLVM code to machine instructions with possibly generic opcodes .


<s> const char * aarch64_sls_barrier ( int mitigation_required ) { return mitigation_required ? ( TARGET_SB ? "sb" : "dsb\tsy\n\tisb" ) : "" ; } </s>

Helper function for straight line speculation . Return what barrier should be emitted for straight line speculation mitigation . When not mitigating against straight line speculation this function returns an empty string . When mitigating against straight line speculation , use : * SB when the v8.5-A SB extension is enabled . * DSB+ISB otherwise .


<s> const uint32_t * Cpu0RegisterInfo :: getCallPreservedMask ( const MachineFunction & MF , CallingConv :: ID ) const { return CSR_O32_RegMask ; } </s>

Return a mask of call-preserved registers for the given calling convention on the current function .


<s> bool TL45InstrInfo :: analyzeBranch ( MachineBasicBlock & MBB , MachineBasicBlock * & TBB , MachineBasicBlock * & FBB , SmallVectorImpl < MachineOperand > & Cond , bool AllowModify ) const { MachineBasicBlock :: reverse_iterator I = MBB . rbegin ( ) , REnd = MBB . rend ( ) ; while ( I != REnd && I -> isDebugInstr ( ) ) ++ I ; if ( I == REnd || ! isUnpredicatedTerminator ( * I ) ) { TBB = FBB = nullptr ; return false ; } SmallVector < MachineInstr * , 4 > BranchInstrs ; MachineInstr * LastInst = & * I ; unsigned LastOpc = LastInst -> getOpcode ( ) ; BranchInstrs . push_back ( LastInst ) ; if ( ! getAnalyzableBrOpc ( LastOpc ) ) return true ; unsigned SecondLastOpc = 0 ; MachineInstr * SecondLastInst = nullptr ; ++ I ; while ( I != REnd && I -> isDebugInstr ( ) ) ++ I ; if ( I != REnd ) { SecondLastInst = & * I ; SecondLastOpc = SecondLastInst -> getOpcode ( ) ; if ( isUnpredicatedTerminator ( * SecondLastInst ) && ! getAnalyzableBrOpc ( SecondLastOpc ) ) return true ; } if ( ! SecondLastOpc || ! getAnalyzableBrOpc ( SecondLastOpc ) ) { if ( LastInst -> isUnconditionalBranch ( ) ) { TBB = LastInst -> getOperand ( 0 ) . getMBB ( ) ; return false ; } AnalyzeCondBr ( LastInst , LastOpc , TBB , Cond , I ) ; return false ; } if ( ++ I != REnd && isUnpredicatedTerminator ( * I ) ) return true ; BranchInstrs . insert ( BranchInstrs . begin ( ) , SecondLastInst ) ; if ( SecondLastInst -> isUnconditionalBranch ( ) ) { if ( ! AllowModify ) { return true ; } TBB = SecondLastInst -> getOperand ( 0 ) . getMBB ( ) ; LastInst -> eraseFromParent ( ) ; BranchInstrs . pop_back ( ) ; return false ; } if ( ! LastInst -> isUnconditionalBranch ( ) ) return true ; AnalyzeCondBr ( SecondLastInst , SecondLastOpc , TBB , Cond , I ) ; FBB = LastInst -> getOperand ( 0 ) . getMBB ( ) ; return false ; } </s>

analyzeBranch - Analyze the branching code at the end of MBB , returning true if it can not be understood ( e.g .


"InlineAsmMemoryOperand 'v' constraint not handled."

SelectInlineAsmMemoryOperand - Select the specified address as a target addressing mode , according to the specified constraint .


<s> unsigned ARMBaseInstrInfo :: getNumLDMAddresses ( const MachineInstr & MI ) const { unsigned Size = 0 ; for ( MachineInstr :: mmo_iterator I = MI . memoperands_begin ( ) , E = MI . memoperands_end ( ) ; I != E ; ++ I ) { Size += ( * I ) -> getSize ( ) ; } return std :: min ( Size / 4 , 16U ) ; } </s>

Get the number of addresses by LDM or VLDM or zero for unknown .


<s> bool SITargetLowering :: isEligibleForTailCallOptimization ( SDValue Callee , CallingConv :: ID CalleeCC , bool IsVarArg , const SmallVectorImpl < ISD :: OutputArg > & Outs , const SmallVectorImpl < SDValue > & OutVals , const SmallVectorImpl < ISD :: InputArg > & Ins , SelectionDAG & DAG ) const { if ( ! mayTailCallThisCC ( CalleeCC ) ) return false ; if ( Callee -> isDivergent ( ) ) return false ; MachineFunction & MF = DAG . getMachineFunction ( ) ; const Function & CallerF = MF . getFunction ( ) ; CallingConv :: ID CallerCC = CallerF . getCallingConv ( ) ; const SIRegisterInfo * TRI = getSubtarget ( ) -> getRegisterInfo ( ) ; const uint32_t * CallerPreserved = TRI -> getCallPreservedMask ( MF , CallerCC ) ; if ( ! CallerPreserved ) return false ; bool CCMatch = CallerCC == CalleeCC ; if ( DAG . getTarget ( ) . Options . GuaranteedTailCallOpt ) { if ( canGuaranteeTCO ( CalleeCC ) && CCMatch ) return true ; return false ; } if ( IsVarArg ) return false ; for ( const Argument & Arg : CallerF . args ( ) ) { if ( Arg . hasByValAttr ( ) ) return false ; } LLVMContext & Ctx = * DAG . getContext ( ) ; if ( ! CCState :: resultsCompatible ( CalleeCC , CallerCC , MF , Ctx , Ins , CCAssignFnForCall ( CalleeCC , IsVarArg ) , CCAssignFnForCall ( CallerCC , IsVarArg ) ) ) return false ; if ( ! CCMatch ) { const uint32_t * CalleePreserved = TRI -> getCallPreservedMask ( MF , CalleeCC ) ; if ( ! TRI -> regmaskSubsetEqual ( CallerPreserved , CalleePreserved ) ) return false ; } if ( Outs . empty ( ) ) return true ; SmallVector < CCValAssign , 16 > ArgLocs ; CCState CCInfo ( CalleeCC , IsVarArg , MF , ArgLocs , Ctx ) ; CCInfo . AnalyzeCallOperands ( Outs , CCAssignFnForCall ( CalleeCC , IsVarArg ) ) ; const SIMachineFunctionInfo * FuncInfo = MF . getInfo < SIMachineFunctionInfo > ( ) ; if ( CCInfo . getNextStackOffset ( ) > FuncInfo -> getBytesInStackArgArea ( ) ) return false ; const MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; return parametersInCSRMatch ( MRI , CallerPreserved , ArgLocs , OutVals ) ; } </s>

Returns true if the call can be lowered as a tail call .

AMDGPU SI ISD::OutputArg ISD::InputArg SI 16 SI SI


"ignoring unrecognized switch %<-mcustom-fpu-cfg%> "

Use CFGNAME to lookup FPU config , ENDP if not NULL marks end of string . OVERRIDE is true if loaded config codes should overwrite current state .


<s> SDValue WebAssemblySelectionDAGInfo :: EmitTargetCodeForMemmove ( SelectionDAG & DAG , const SDLoc & DL , SDValue Chain , SDValue Op1 , SDValue Op2 , SDValue Op3 , unsigned Align , bool IsVolatile , MachinePointerInfo DstPtrInfo , MachinePointerInfo SrcPtrInfo ) const { return EmitTargetCodeForMemcpy ( DAG , DL , Chain , Op1 , Op2 , Op3 , Align , IsVolatile , false , DstPtrInfo , SrcPtrInfo ) ; } </s>

Emit target-specific code that performs a memmove .


<s> const uint32_t * LC2200RegisterInfo :: getCallPreservedMask ( const MachineFunction & MF , CallingConv :: ID ) const { return CC_Save_RegMask ; } </s>


"Handling of TOC entry displacement larger than 32767 "

This virtual method can be overridden by targets that want to emit something at the end of their file .


"PrintAsmOperand not implemented yet!\n"

PrintAsmOperand - Print out an operand for an inline asm expression .


<s> static inline _Unwind_Control_Block * unwind_UCB_from_context ( _Unwind_Context * context ) { return ( _Unwind_Control_Block * ) _Unwind_GetGR ( context , R_IP ) ; } </s>

Get the _Unwind_Control_Block from an _Unwind_Context .


<s> static int power9_sched_reorder2 ( rtx_insn * * ready , int lastpos ) { int pos ; enum attr_type type , type2 ; type = get_attr_type ( last_scheduled_insn ) ; if ( type == TYPE_DIV && divide_cnt == 0 ) { divide_cnt = 1 ; pos = lastpos ; while ( pos >= 0 ) { if ( recog_memoized ( ready [ pos ] ) >= 0 && get_attr_type ( ready [ pos ] ) == TYPE_DIV ) { move_to_end_of_ready ( ready , pos , lastpos ) ; break ; } pos -- ; } } else { divide_cnt = 0 ; if ( type == TYPE_VECLOAD ) { if ( vec_pairing == 0 ) { int vecload_pos = - 1 ; pos = lastpos ; while ( pos >= 0 ) { if ( recog_memoized ( ready [ pos ] ) >= 0 ) { type2 = get_attr_type ( ready [ pos ] ) ; if ( is_power9_pairable_vec_type ( type2 ) ) { move_to_end_of_ready ( ready , pos , lastpos ) ; vec_pairing = 1 ; return cached_can_issue_more ; } else if ( type2 == TYPE_VECLOAD && vecload_pos == - 1 ) vecload_pos = pos ; } pos -- ; } if ( vecload_pos >= 0 ) { move_to_end_of_ready ( ready , vecload_pos , lastpos ) ; vec_pairing = 1 ; return cached_can_issue_more ; } } } else if ( is_power9_pairable_vec_type ( type ) ) { if ( vec_pairing == 0 ) { int vec_pos = - 1 ; pos = lastpos ; while ( pos >= 0 ) { if ( recog_memoized ( ready [ pos ] ) >= 0 ) { type2 = get_attr_type ( ready [ pos ] ) ; if ( type2 == TYPE_VECLOAD ) { move_to_end_of_ready ( ready , pos , lastpos ) ; vec_pairing = 1 ; return cached_can_issue_more ; } else if ( is_power9_pairable_vec_type ( type2 ) && vec_pos == - 1 ) vec_pos = pos ; } pos -- ; } if ( vec_pos >= 0 ) { move_to_end_of_ready ( ready , vec_pos , lastpos ) ; vec_pairing = 1 ; return cached_can_issue_more ; } } } vec_pairing = 0 ; } return cached_can_issue_more ; } </s>

Do Power9 specific sched_reorder2 reordering of ready list .


<s> static rtx frame_insn ( rtx x ) { x = emit_insn ( x ) ; RTX_FRAME_RELATED_P ( x ) = 1 ; return x ; } </s>

Emit the specified insn and mark it as frame related . FIXME : Rename this to emit_frame_insn .


<s> static void delete_output_files ( void ) { fclose ( header_file ) ; fclose ( init_file ) ; fclose ( defines_file ) ; remove ( header_path ) ; remove ( init_path ) ; remove ( defines_path ) ; } </s>

Close and delete output files after any failure , so that subsequent build dependencies will fail .


<s> void XCoreInstPrinter :: printInst ( const MCInst * MI , raw_ostream & O , StringRef Annot ) { printInstruction ( MI , O ) ; printAnnotation ( O , Annot ) ; } </s>

Print the specified MCInst to the specified raw_ostream .


<s> bool Inserter :: runOnMachineFunction ( MachineFunction & F ) { MipsFunctionInfo * MipsFI = F . getInfo < MipsFunctionInfo > ( ) ; if ( ( TM . getRelocationModel ( ) != Reloc :: PIC_ ) || ( ! MipsFI -> globalBaseRegFixed ( ) ) ) return false ; bool Changed = false ; int FI = MipsFI -> getGPFI ( ) ; for ( MachineFunction :: iterator MFI = F . begin ( ) , MFE = F . end ( ) ; MFI != MFE ; ++ MFI ) { MachineBasicBlock & MBB = * MFI ; MachineBasicBlock :: iterator I = MFI -> begin ( ) ; if ( MBB . isLandingPad ( ) ) { for ( ; I -> getOpcode ( ) != TargetOpcode :: EH_LABEL ; ++ I ) ; ++ I ; DebugLoc dl = I != MBB . end ( ) ? I -> getDebugLoc ( ) : DebugLoc ( ) ; BuildMI ( MBB , I , dl , TII -> get ( Mips :: LW ) , Mips :: GP ) . addFrameIndex ( FI ) . addImm ( 0 ) ; Changed = true ; } while ( I != MFI -> end ( ) ) { if ( I -> getOpcode ( ) != Mips :: JALR ) { ++ I ; continue ; } DebugLoc dl = I -> getDebugLoc ( ) ; BuildMI ( MBB , ++ I , dl , TII -> get ( Mips :: LW ) , Mips :: GP ) . addFrameIndex ( FI ) . addImm ( 0 ) ; Changed = true ; } } return Changed ; } </s>

runOnMachineFunction - Emit the function body .

Mips Mips Mips Mips Mips Mips Mips::LW Mips::GP 0 Mips::JALR Mips::LW Mips::GP 0


<s> bool X86FrameLowering :: restoreCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo * TRI ) const { if ( CSI . empty ( ) ) return false ; if ( MI != MBB . end ( ) && isFuncletReturnInstr ( * MI ) && STI . isOSWindows ( ) ) { if ( STI . is32Bit ( ) ) return true ; if ( MI -> getOpcode ( ) == X86 :: CATCHRET ) { const Function & F = MBB . getParent ( ) -> getFunction ( ) ; bool IsSEH = isAsynchronousEHPersonality ( classifyEHPersonality ( F . getPersonalityFn ( ) ) ) ; if ( IsSEH ) return true ; } } DebugLoc DL = MBB . findDebugLoc ( MI ) ; for ( unsigned i = 0 , e = CSI . size ( ) ; i != e ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; if ( X86 :: GR64RegClass . contains ( Reg ) || X86 :: GR32RegClass . contains ( Reg ) ) continue ; MVT VT = MVT :: Other ; if ( X86 :: VK16RegClass . contains ( Reg ) ) VT = STI . hasBWI ( ) ? MVT :: v64i1 : MVT :: v16i1 ; const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg , VT ) ; TII . loadRegFromStackSlot ( MBB , MI , Reg , CSI [ i ] . getFrameIdx ( ) , RC , TRI ) ; } unsigned Opc = STI . is64Bit ( ) ? X86 :: POP64r : X86 :: POP32r ; for ( unsigned i = 0 , e = CSI . size ( ) ; i != e ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; if ( ! X86 :: GR64RegClass . contains ( Reg ) && ! X86 :: GR32RegClass . contains ( Reg ) ) continue ; BuildMI ( MBB , MI , DL , TII . get ( Opc ) , Reg ) . setMIFlag ( MachineInstr :: FrameDestroy ) ; } return true ; } </s>

restoreCalleeSavedRegisters - Issues instruction ( s ) to restore all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of load instructions via loadRegToStackSlot ( ) .


<s> const char * output_387_reg_move ( rtx_insn * insn , rtx * operands ) { if ( REG_P ( operands [ 0 ] ) ) { if ( REG_P ( operands [ 1 ] ) && find_regno_note ( insn , REG_DEAD , REGNO ( operands [ 1 ] ) ) ) { if ( REGNO ( operands [ 0 ] ) == FIRST_STACK_REG ) return output_387_ffreep ( operands , 0 ) ; return "fstp\t%y0" ; } if ( STACK_TOP_P ( operands [ 0 ] ) ) return "fld%Z1\t%y1" ; return "fst\t%y0" ; } else if ( MEM_P ( operands [ 0 ] ) ) { gcc_assert ( REG_P ( operands [ 1 ] ) ) ; if ( find_regno_note ( insn , REG_DEAD , REGNO ( operands [ 1 ] ) ) ) return "fstp%Z0\t%y0" ; else { if ( GET_MODE ( operands [ 0 ] ) == XFmode ) return "fstp%Z0\t%y0\n\tfld%Z0\t%y0" ; else return "fst%Z0\t%y0" ; } } else gcc_unreachable ( ) ; } </s>

Output code to perform an x87 FP register move , from OPERANDS [ 1 ] to OPERANDS [ 0 ] .


<s> static void expand_prologue_reg_save ( rtx spreg , int saveall , bool is_inthandler ) { int ndregs = saveall ? 8 : n_dregs_to_save ( is_inthandler ) ; int npregs = saveall ? 6 : n_pregs_to_save ( is_inthandler ) ; int dregno = REG_R7 + 1 - ndregs ; int pregno = REG_P5 + 1 - npregs ; int total = ndregs + npregs ; int i ; rtx pat , insn , val ; if ( total == 0 ) return ; val = GEN_INT ( - total * 4 ) ; pat = gen_rtx_PARALLEL ( VOIDmode , rtvec_alloc ( total + 2 ) ) ; XVECEXP ( pat , 0 , 0 ) = gen_rtx_UNSPEC ( VOIDmode , gen_rtvec ( 1 , val ) , UNSPEC_PUSH_MULTIPLE ) ; XVECEXP ( pat , 0 , total + 1 ) = gen_rtx_SET ( VOIDmode , spreg , gen_rtx_PLUS ( Pmode , spreg , val ) ) ; RTX_FRAME_RELATED_P ( XVECEXP ( pat , 0 , total + 1 ) ) = 1 ; for ( i = 0 ; i < total ; i ++ ) { rtx memref = gen_rtx_MEM ( word_mode , gen_rtx_PLUS ( Pmode , spreg , GEN_INT ( - i * 4 - 4 ) ) ) ; rtx subpat ; if ( ndregs > 0 ) { subpat = gen_rtx_SET ( VOIDmode , memref , gen_rtx_REG ( word_mode , dregno ++ ) ) ; ndregs -- ; } else { subpat = gen_rtx_SET ( VOIDmode , memref , gen_rtx_REG ( word_mode , pregno ++ ) ) ; npregs ++ ; } XVECEXP ( pat , 0 , i + 1 ) = subpat ; RTX_FRAME_RELATED_P ( subpat ) = 1 ; } insn = emit_insn ( pat ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; } </s>

Emit code to save registers in the prologue . SAVEALL is nonzero if we must save all registers ; this is used for interrupt handlers . SPREG contains ( reg : SI REG_SP ) . IS_INTHANDLER is true if we 're doing this for an interrupt ( or exception ) handler .


<s> void Nios2AsmBackend :: applyFixup ( const MCAssembler & Asm , const MCFixup & Fixup , const MCValue & Target , MutableArrayRef < char > Data , uint64_t Value , bool IsResolved ) const { MCFixupKind Kind = Fixup . getKind ( ) ; Value = adjustFixupValue ( Fixup , Value ) ; if ( ! Value ) return ; unsigned Offset = Fixup . getOffset ( ) ; unsigned NumBytes = ( getFixupKindInfo ( Kind ) . TargetSize + 7 ) / 8 ; uint64_t CurVal = 0 ; for ( unsigned i = 0 ; i != NumBytes ; ++ i ) { unsigned Idx = calculateLEIndex ( i ) ; CurVal |= ( uint64_t ) ( ( uint8_t ) Data [ Offset + Idx ] ) << ( i * 8 ) ; } uint64_t Mask = ( ( uint64_t ) ( - 1 ) >> ( 64 - getFixupKindInfo ( Kind ) . TargetSize ) ) ; CurVal |= Value & Mask ; for ( unsigned i = 0 ; i != NumBytes ; ++ i ) { unsigned Idx = calculateLEIndex ( i ) ; Data [ Offset + Idx ] = ( uint8_t ) ( ( CurVal >> ( i * 8 ) ) & 0xff ) ; } } </s>

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


<s> inline rtx_insn * rx_find_use_of_reg ( rtx reg , rtx_insn * insn , F stepfunc ) { if ( ! REG_P ( reg ) || insn == NULL_RTX ) return NULL ; for ( rtx_insn * i = stepfunc ( insn ) ; i != NULL_RTX ; i = stepfunc ( i ) ) { if ( BARRIER_P ( i ) ) break ; if ( ! INSN_P ( i ) || DEBUG_INSN_P ( i ) ) continue ; if ( reg_overlap_mentioned_p ( reg , PATTERN ( i ) ) || ( CALL_P ( i ) && find_reg_fusage ( i , USE , reg ) ) ) return i ; } return NULL ; } </s>


<s>
virtual
const
char
*
getPassName
(
)
const
{
return
"Mips Long Branch"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s>
virtual
unsigned
getFrameRegister
(
const
MachineFunction
&
MF
)
const
{
llvm_unreachable
(
"PTX does not have a frame register"
)
;
return
0
;
}
</s>

PTX
"PTX does not have a frame register"
0


<s> unsigned MipsSEInstrInfo :: isStoreToStackSlot ( const MachineInstr * MI , int & FrameIndex ) const { unsigned Opc = MI -> getOpcode ( ) ; if ( ( Opc == Mips :: SW ) || ( Opc == Mips :: SWC1 ) || ( Opc == Mips :: SDC1 ) ) { if ( ( MI -> getOperand ( 1 ) . isFI ( ) ) && ( MI -> getOperand ( 2 ) . isImm ( ) ) && ( isZeroImm ( MI -> getOperand ( 2 ) ) ) ) { FrameIndex = MI -> getOperand ( 1 ) . getIndex ( ) ; return MI -> getOperand ( 0 ) . getReg ( ) ; } } return 0 ; } </s>

isStoreToStackSlot - If the specified machine instruction is a direct store to a stack slot , return the virtual or physical register number of the source reg along with the FrameIndex of the loaded stack slot .


<s> void print ( raw_ostream & OS , const TargetRegisterInfo * TRI = nullptr ) const { if ( isReg ( ) ) { OS << PrintReg ( Contents . R . Reg , TRI , Contents . R . Sub ) ; } if ( isImm ( ) ) { OS << Contents . ImmVal ; } } </s>

print - Print a debug representation of the operand to the given stream .


<s> static rtx aarch64_target_reg ( rtx target , machine_mode mode ) { if ( target && REG_P ( target ) && GET_MODE ( target ) == mode ) return target ; if ( ! can_create_pseudo_p ( ) ) { gcc_assert ( target ) ; return gen_lowpart ( mode , target ) ; } return gen_reg_rtx ( mode ) ; } </s>

Return TARGET if it is nonnull and a register of mode MODE . Otherwise , return a fresh register of mode MODE if we can , or TARGET reinterpreted as MODE if we ca n't .


<s> void ix86_call_abi_override ( const_tree fndecl ) { if ( fndecl == NULL_TREE ) cfun -> machine -> call_abi = ix86_abi ; else cfun -> machine -> call_abi = ix86_function_type_abi ( TREE_TYPE ( fndecl ) ) ; } </s>

Implementation of call abi switching target hook . Specific to FNDECL the specific call register sets are set . See also ix86_conditional_register_usage for more details .


<s>
const
ArrayRef
<
MCPhysReg
>
SICABIInfo
::
GetByValArgRegs
(
)
const
{
if
(
IsO32
(
)
)
return
makeArrayRef
(
O32IntRegs
)
;
if
(
IsS32
(
)
)
return
makeArrayRef
(
S32IntRegs
)
;
llvm_unreachable
(
"Unhandled ABI"
)
;
}
</s>

The registers to use for byval arguments .


Output a return instruction . Also copy the return value to its outgoing location .


<s> static rtx conditionalize_block ( rtx first ) { rtx insn ; rtx br_pat ; rtx end_blk_1_br = 0 ; rtx end_blk_2_insn = 0 ; rtx start_blk_3_lab = 0 ; int cond ; int br_lab_num ; int blk_size = 0 ; if ( GET_CODE ( first ) != JUMP_INSN || GET_CODE ( PATTERN ( first ) ) != SET || GET_CODE ( XEXP ( PATTERN ( first ) , 1 ) ) != IF_THEN_ELSE ) return NEXT_INSN ( first ) ; end_blk_1_br = first ; br_pat = PATTERN ( end_blk_1_br ) ; cond = ( GET_CODE ( XEXP ( XEXP ( br_pat , 1 ) , 0 ) ) == EQ ) ; if ( GET_CODE ( XEXP ( XEXP ( br_pat , 1 ) , 1 ) ) == LABEL_REF ) { br_lab_num = CODE_LABEL_NUMBER ( XEXP ( XEXP ( XEXP ( br_pat , 1 ) , 1 ) , 0 ) ) ; } else { cond = ( cond == 0 ) ; br_lab_num = CODE_LABEL_NUMBER ( XEXP ( XEXP ( XEXP ( br_pat , 1 ) , 2 ) , 0 ) ) ; } for ( insn = NEXT_INSN ( first ) ; insn ; insn = NEXT_INSN ( insn ) ) { enum rtx_code code ; code = GET_CODE ( insn ) ; if ( code == CODE_LABEL && CODE_LABEL_NUMBER ( insn ) == br_lab_num ) break ; if ( code != BARRIER && code != NOTE && ! is_cond_candidate ( insn ) ) return NEXT_INSN ( insn ) ; if ( code == JUMP_INSN || code == INSN ) { blk_size ++ ; end_blk_2_insn = insn ; } } if ( ! insn ) return insn ; if ( optimize > 1 && blk_size > 2 ) return insn ; start_blk_3_lab = insn ; for ( insn = NEXT_INSN ( end_blk_1_br ) ; insn != start_blk_3_lab ; insn = NEXT_INSN ( insn ) ) { rtx newinsn ; if ( INSN_DELETED_P ( insn ) ) continue ; if ( ( newinsn = emit_new_cond_insn ( insn , cond ) ) ) { if ( end_blk_2_insn == insn ) end_blk_2_insn = newinsn ; insn = newinsn ; } } if ( LABEL_NUSES ( start_blk_3_lab ) == 1 ) { start_blk_3_lab = 0 ; } delete_insn ( end_blk_1_br ) ; if ( ! start_blk_3_lab ) return end_blk_2_insn ; return NEXT_INSN ( start_blk_3_lab ) ; } </s>

Attempt to change a basic block into a series of conditional insns . This works by taking the branch at the end of the 1st block and scanning for the end of the 2nd block . If all instructions in the 2nd block have cond . versions and the label at the start of block 3 is the same as the target from the branch at block 1 , then conditionalize all insn in block 2 using the inverse condition of the branch at block 1 . ( Note I 'm bending the definition of basic block here . ) e.g. , change : bt L2 < -- end of block 1 ( delete ) mov r7 , r8 addu r7,1 br L3 < -- end of block 2 L2 : ... < -- start of block 3 ( NUSES==1 ) L3 : ... to : movf r7 , r8 incf r7 bf L3 L3 : ... we can delete the L2 label if NUSES==1 and re-apply the optimization starting at the last instruction of block 2 . This may allow an entire if-then-else statement to be conditionalized . BRC


<s> bool enableShrinkWrapping ( const MachineFunction & MF ) const override { return false ; } </s>

Returns true if the target will correctly handle shrink wrapping .


<s> static rtx frv_expand_unop_builtin ( enum insn_code icode , tree arglist , rtx target ) { rtx pat ; rtx op0 = frv_read_argument ( & arglist ) ; target = frv_legitimize_target ( icode , target ) ; op0 = frv_legitimize_argument ( icode , 1 , op0 ) ; pat = GEN_FCN ( icode ) ( target , op0 ) ; if ( ! pat ) return NULL_RTX ; emit_insn ( pat ) ; return target ; } </s>


<s> bool arm_small_register_classes_for_mode_p ( machine_mode mode ATTRIBUTE_UNUSED ) { return TARGET_THUMB1 ; } </s>

Implements target hook small_register_classes_for_mode_p .


<s> static bool tilegx_pass_by_reference ( cumulative_args_t , const function_arg_info & arg ) { return ( arg . type && TYPE_SIZE ( arg . type ) && TREE_CODE ( TYPE_SIZE ( arg . type ) ) != INTEGER_CST ) ; } </s>

Implement TARGET_PASS_BY_REFERENCE . Variable sized types are passed by reference .


<s> static int epiphany_adjust_cost ( rtx_insn * insn , rtx link , rtx_insn * dep_insn , int cost ) { if ( REG_NOTE_KIND ( link ) == 0 ) { rtx dep_set ; if ( recog_memoized ( insn ) < 0 || recog_memoized ( dep_insn ) < 0 ) return cost ; dep_set = single_set ( dep_insn ) ; if ( dep_set && MEM_P ( SET_SRC ( dep_set ) ) && cost > 1 ) { rtx set = single_set ( insn ) ; if ( set && ! reg_overlap_mentioned_p ( SET_DEST ( dep_set ) , SET_SRC ( set ) ) && ( ! MEM_P ( SET_DEST ( set ) ) || ! reg_overlap_mentioned_p ( SET_DEST ( dep_set ) , XEXP ( SET_DEST ( set ) , 0 ) ) ) ) cost = 1 ; } } return cost ; } </s>

Function to update the integer COST based on the relationship between INSN that is dependent on DEP_INSN through the dependence LINK . The default is to make no adjustment to COST . This can be used for example to specify to the scheduler that an output- or anti-dependence does not incur the same cost as a data-dependence . The return value should be the new value for COST .


<s> void X86FlagsCopyLoweringPass :: getAnalysisUsage ( AnalysisUsage & AU ) const { AU . addRequired < MachineDominatorTree > ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> bool X86PassConfig :: addPreISel ( ) { Triple TT ( TM -> getTargetTriple ( ) ) ; if ( TT . isOSWindows ( ) && TT . getArch ( ) == Triple :: x86 ) addPass ( createX86WinEHStatePass ( ) ) ; return true ; } </s>


<s> static int sparc_register_move_cost ( machine_mode mode ATTRIBUTE_UNUSED , reg_class_t from , reg_class_t to ) { bool need_memory = false ; if ( from == FPCC_REGS || to == FPCC_REGS ) need_memory = true ; else if ( ( FP_REG_CLASS_P ( from ) && general_or_i64_p ( to ) ) || ( general_or_i64_p ( from ) && FP_REG_CLASS_P ( to ) ) ) { if ( TARGET_VIS3 ) { int size = GET_MODE_SIZE ( mode ) ; if ( size == 8 || size == 4 ) { if ( ! TARGET_ARCH32 || size == 4 ) return 4 ; else return 6 ; } } need_memory = true ; } if ( need_memory ) { if ( sparc_cpu == PROCESSOR_ULTRASPARC || sparc_cpu == PROCESSOR_ULTRASPARC3 || sparc_cpu == PROCESSOR_NIAGARA || sparc_cpu == PROCESSOR_NIAGARA2 || sparc_cpu == PROCESSOR_NIAGARA3 || sparc_cpu == PROCESSOR_NIAGARA4 ) return 12 ; return 6 ; } return 2 ; } </s>


<s> PPCSubtarget :: PPCSubtarget ( const std :: string & TT , const std :: string & CPU , const std :: string & FS , bool is64Bit ) : PPCGenSubtargetInfo ( TT , CPU , FS ) , StackAlignment ( 16 ) , DarwinDirective ( PPC :: DIR_NONE ) , HasMFOCRF ( false ) , Has64BitSupport ( false ) , Use64BitRegs ( false ) , IsPPC64 ( is64Bit ) , HasAltivec ( false ) , HasFSQRT ( false ) , HasSTFIWX ( false ) , HasISEL ( false ) , IsBookE ( false ) , HasLazyResolverStubs ( false ) , IsJITCodeModel ( false ) , TargetTriple ( TT ) { std :: string CPUName = CPU ; if ( CPUName . empty ( ) ) CPUName = "generic" ; ( defined ( __ppc__ ) || defined ( __powerpc__ ) ) if ( CPUName == "generic" ) CPUName = sys :: getHostCPUName ( ) ; ParseSubtargetFeatures ( CPUName , FS ) ; InstrItins = getInstrItineraryForCPU ( CPUName ) ; if ( is64Bit ) { Has64BitSupport = true ; Use64BitRegs = true ; } if ( use64BitRegs ( ) && ! has64BitSupport ( ) ) Use64BitRegs = false ; if ( isDarwin ( ) ) HasLazyResolverStubs = true ; } </s>

This constructor initializes the data members to match that of the specified triple .

PowerPC PPC PPC PPC 16 PPC::DIR_NONE PPC "generic" "generic"


<s>
Value
*
HexagonTargetLowering
::
emitLoadLinked
(
IRBuilder
<
>
&
Builder
,
Value
*
Addr
,
AtomicOrdering
Ord
)
const
{
BasicBlock
*
BB
=
Builder
.
GetInsertBlock
(
)
;
Module
*
M
=
BB
->
getParent
(
)
->
getParent
(
)
;
Type
*
Ty
=
cast
<
PointerType
>
(
Addr
->
getType
(
)
)
->
getElementType
(
)
;
unsigned
SZ
=
Ty
->
getPrimitiveSizeInBits
(
)
;
assert
(
(
SZ
==
32
||
SZ
==
64
)
&&
"Only 32/64-bit atomic loads supported"
)
;
Intrinsic
::
ID
IntID
=
(
SZ
==
32
)
Intrinsic
::
hexagon_L2_loadw_locked
:
Intrinsic
::
hexagon_L4_loadd_locked
;
Value
*
Fn
=
Intrinsic
::
getDeclaration
(
M
,
IntID
)
;
return
Builder
.
CreateCall
(
Fn
,
Addr
,
"larx"
)
;
}
</s>

Perform a load-linked operation on Addr , returning a `` Value * '' with the corresponding pointee type .


<s> unsigned getNumArgs ( ) const { return Impl -> getNumArgs ( ) ; } </s>

Return the number of arguments associated with this function or call site scope .


<s> bool X86AvoidSFBPass :: alias ( const MachineMemOperand & Op1 , const MachineMemOperand & Op2 ) const { if ( ! Op1 . getValue ( ) || ! Op2 . getValue ( ) ) return true ; int64_t MinOffset = std :: min ( Op1 . getOffset ( ) , Op2 . getOffset ( ) ) ; int64_t Overlapa = Op1 . getSize ( ) + Op1 . getOffset ( ) - MinOffset ; int64_t Overlapb = Op2 . getSize ( ) + Op2 . getOffset ( ) - MinOffset ; AliasResult AAResult = AA -> alias ( MemoryLocation ( Op1 . getValue ( ) , Overlapa , Op1 . getAAInfo ( ) ) , MemoryLocation ( Op2 . getValue ( ) , Overlapb , Op2 . getAAInfo ( ) ) ) ; return AAResult != NoAlias ; } </s>

alias - If one of the pointers is to a global that we are tracking , and the other is some random pointer , we know there can not be an alias , because the address of the global is n't taken .


<s> bool isReg ( ) const override { return Kind == Local || Kind == Stack ; } </s>


<s>
void
Thumb1InstrInfo
::
copyPhysReg
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
const
DebugLoc
&
DL
,
unsigned
DestReg
,
unsigned
SrcReg
,
bool
KillSrc
)
const
{
MachineFunction
&
MF
=
*
MBB
.
getParent
(
)
;
const
ARMSubtarget
&
st
=
MF
.
getSubtarget
<
ARMSubtarget
>
(
)
;
assert
(
ARM
::
GPRRegClass
.
contains
(
DestReg
,
SrcReg
)
&&
"Thumb1 can only copy GPR registers"
)
;
if
(
st
.
hasV6Ops
(
)
||
ARM
::
hGPRRegClass
.
contains
(
SrcReg
)
||
!
ARM
::
tGPRRegClass
.
contains
(
DestReg
)
)
BuildMI
(
MBB
,
I
,
DL
,
get
(
ARM
::
tMOVr
)
,
DestReg
)
.
addReg
(
SrcReg
,
getKillRegState
(
KillSrc
)
)
.
add
(
predOps
(
ARMCC
::
AL
)
)
;
else
{
const
TargetRegisterInfo
*
RegInfo
=
st
.
getRegisterInfo
(
)
;
if
(
MBB
.
computeRegisterLiveness
(
RegInfo
,
ARM
::
CPSR
,
I
)
==
MachineBasicBlock
::
LQR_Dead
)
{
BuildMI
(
MBB
,
I
,
DL
,
get
(
ARM
::
tMOVSr
)
,
DestReg
)
.
addReg
(
SrcReg
,
getKillRegState
(
KillSrc
)
)
->
addRegisterDead
(
ARM
::
CPSR
,
RegInfo
)
;
return
;
}
BuildMI
(
MBB
,
I
,
DL
,
get
(
ARM
::
tPUSH
)
)
.
add
(
predOps
(
ARMCC
::
AL
)
)
.
addReg
(
SrcReg
,
getKillRegState
(
KillSrc
)
)
;
BuildMI
(
MBB
,
I
,
DL
,
get
(
ARM
::
tPOP
)
)
.
add
(
predOps
(
ARMCC
::
AL
)
)
.
addReg
(
DestReg
,
getDefRegState
(
true
)
)
;
}
}
</s>

ARM
ARM
ARM
ARM::GPRRegClass
"Thumb1 can only copy GPR registers"
ARM::hGPRRegClass
ARM::tGPRRegClass
ARM::tMOVr
ARMCC::AL
ARM::CPSR
ARM::tMOVSr
ARM::CPSR
ARM::tPUSH
ARMCC::AL
ARM::tPOP
ARMCC::AL


"rs6000_register_move_cost: ret=%d, mode=%s, from=%s, to=%s\n"

A C expression returning the cost of moving data from a register of class CLASS1 to one of CLASS2 .


<s> void nds32_expand_prologue ( void ) { int fp_adjust ; int sp_adjust ; unsigned Rb , Re ; nds32_compute_stack_frame ( ) ; if ( cfun -> machine -> va_args_size != 0 ) { Rb = cfun -> machine -> va_args_first_regno ; Re = cfun -> machine -> va_args_last_regno ; nds32_emit_stack_push_multiple ( Rb , Re , false , false , false , true ) ; if ( cfun -> machine -> va_args_area_padding_bytes ) { sp_adjust = cfun -> machine -> va_args_area_padding_bytes ; nds32_emit_adjust_frame ( stack_pointer_rtx , stack_pointer_rtx , - 1 * sp_adjust ) ; } } if ( cfun -> machine -> naked_p ) return ; Rb = cfun -> machine -> callee_saved_first_gpr_regno ; Re = cfun -> machine -> callee_saved_last_gpr_regno ; if ( ! ( Rb == SP_REGNUM && Re == SP_REGNUM && cfun -> machine -> fp_size == 0 && cfun -> machine -> gp_size == 0 && cfun -> machine -> lp_size == 0 ) ) { nds32_emit_stack_push_multiple ( Rb , Re , cfun -> machine -> fp_size , cfun -> machine -> gp_size , cfun -> machine -> lp_size , false ) ; } if ( cfun -> machine -> use_eh_return_p ) { Rb = cfun -> machine -> eh_return_data_first_regno ; Re = cfun -> machine -> eh_return_data_last_regno ; nds32_emit_stack_push_multiple ( Rb , Re , false , false , false , false ) ; } if ( frame_pointer_needed ) { fp_adjust = cfun -> machine -> fp_size + cfun -> machine -> gp_size + cfun -> machine -> lp_size + cfun -> machine -> callee_saved_gpr_regs_size + cfun -> machine -> eh_return_data_regs_size ; nds32_emit_adjust_frame ( hard_frame_pointer_rtx , stack_pointer_rtx , fp_adjust ) ; } if ( cfun -> machine -> callee_saved_first_fpr_regno != SP_REGNUM ) { int fpr_offset = cfun -> machine -> local_size + cfun -> machine -> out_args_size + cfun -> machine -> callee_saved_fpr_regs_size ; if ( ! satisfies_constraint_Is14 ( GEN_INT ( fpr_offset ) ) ) { int fpr_space = cfun -> machine -> callee_saved_area_gpr_padding_bytes + cfun -> machine -> callee_saved_fpr_regs_size ; nds32_emit_adjust_frame ( stack_pointer_rtx , stack_pointer_rtx , - 1 * fpr_space ) ; nds32_emit_push_fpr_callee_saved ( 0 ) ; sp_adjust = cfun -> machine -> local_size + cfun -> machine -> out_args_size ; nds32_emit_adjust_frame ( stack_pointer_rtx , stack_pointer_rtx , - 1 * sp_adjust ) ; } else { sp_adjust = cfun -> machine -> local_size + cfun -> machine -> out_args_size + cfun -> machine -> callee_saved_area_gpr_padding_bytes + cfun -> machine -> callee_saved_fpr_regs_size ; nds32_emit_adjust_frame ( stack_pointer_rtx , stack_pointer_rtx , - 1 * sp_adjust ) ; int fpr_position = cfun -> machine -> out_args_size + cfun -> machine -> local_size ; nds32_emit_push_fpr_callee_saved ( fpr_position ) ; } } else { sp_adjust = cfun -> machine -> local_size + cfun -> machine -> out_args_size + cfun -> machine -> callee_saved_area_gpr_padding_bytes ; nds32_emit_adjust_frame ( stack_pointer_rtx , stack_pointer_rtx , - 1 * sp_adjust ) ; } emit_insn ( gen_blockage ( ) ) ; } </s>

Function for normal multiple push prologue .


<s> MCObjectWriter * createObjectWriter ( raw_ostream & OS ) const { return createMipsELFObjectWriter ( OS , true , OSABI ) ; } </s>

Create a new MCObjectWriter instance for use by the assembler backend to emit the final object file .


<s> bool hasFP ( const MachineFunction & MF ) const { return false ; } </s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .


<s> static void v850_print_operand_address ( FILE * file , machine_mode , rtx addr ) { switch ( GET_CODE ( addr ) ) { case REG : fprintf ( file , "0[" ) ; v850_print_operand ( file , addr , 0 ) ; fprintf ( file , "]" ) ; break ; case LO_SUM : if ( GET_CODE ( XEXP ( addr , 0 ) ) == REG ) { fprintf ( file , "lo(" ) ; v850_print_operand ( file , XEXP ( addr , 1 ) , 0 ) ; fprintf ( file , ")[" ) ; v850_print_operand ( file , XEXP ( addr , 0 ) , 0 ) ; fprintf ( file , "]" ) ; } break ; case PLUS : if ( GET_CODE ( XEXP ( addr , 0 ) ) == REG || GET_CODE ( XEXP ( addr , 0 ) ) == SUBREG ) { v850_print_operand ( file , XEXP ( addr , 1 ) , 0 ) ; fprintf ( file , "[" ) ; v850_print_operand ( file , XEXP ( addr , 0 ) , 0 ) ; fprintf ( file , "]" ) ; } else { v850_print_operand ( file , XEXP ( addr , 0 ) , 0 ) ; fprintf ( file , "+" ) ; v850_print_operand ( file , XEXP ( addr , 1 ) , 0 ) ; } break ; case SYMBOL_REF : { const char * off_name = NULL ; const char * reg_name = NULL ; if ( SYMBOL_REF_ZDA_P ( addr ) ) { off_name = "zdaoff" ; reg_name = "r0" ; } else if ( SYMBOL_REF_SDA_P ( addr ) ) { off_name = "sdaoff" ; reg_name = "gp" ; } else if ( SYMBOL_REF_TDA_P ( addr ) ) { off_name = "tdaoff" ; reg_name = "ep" ; } if ( off_name ) fprintf ( file , "%s(" , off_name ) ; output_addr_const ( file , addr ) ; if ( reg_name ) fprintf ( file , ")[%s]" , reg_name ) ; } break ; case CONST : if ( special_symbolref_operand ( addr , VOIDmode ) ) { rtx x = XEXP ( XEXP ( addr , 0 ) , 0 ) ; const char * off_name ; const char * reg_name ; if ( SYMBOL_REF_ZDA_P ( x ) ) { off_name = "zdaoff" ; reg_name = "r0" ; } else if ( SYMBOL_REF_SDA_P ( x ) ) { off_name = "sdaoff" ; reg_name = "gp" ; } else if ( SYMBOL_REF_TDA_P ( x ) ) { off_name = "tdaoff" ; reg_name = "ep" ; } else gcc_unreachable ( ) ; fprintf ( file , "%s(" , off_name ) ; output_addr_const ( file , addr ) ; fprintf ( file , ")[%s]" , reg_name ) ; } else output_addr_const ( file , addr ) ; break ; default : output_addr_const ( file , addr ) ; break ; } } </s>

Output assembly language output for the address ADDR to FILE .


<s> static bool alpha_function_value_regno_p ( const unsigned int regno ) { return ( regno == 0 || regno == 1 || regno == 32 || regno == 33 ) ; } </s>

Implement TARGET_FUNCTION_VALUE_REGNO_P . On the Alpha , $ 0 $ 1 and $ f0 $ f1 are the only register thus used .


<s> int mems_ok_for_ldd_peep ( rtx mem1 , rtx mem2 , rtx dependent_reg_rtx ) { rtx addr1 , addr2 ; unsigned int reg1 ; HOST_WIDE_INT offset1 ; if ( MEM_VOLATILE_P ( mem1 ) || MEM_VOLATILE_P ( mem2 ) ) return 0 ; if ( MEM_ALIGN ( mem1 ) < 64 ) return 0 ; addr1 = XEXP ( mem1 , 0 ) ; addr2 = XEXP ( mem2 , 0 ) ; if ( GET_CODE ( addr1 ) == PLUS ) { if ( GET_CODE ( XEXP ( addr1 , 0 ) ) != REG ) return 0 ; else { reg1 = REGNO ( XEXP ( addr1 , 0 ) ) ; if ( GET_CODE ( XEXP ( addr1 , 1 ) ) != CONST_INT ) return 0 ; offset1 = INTVAL ( XEXP ( addr1 , 1 ) ) ; } } else if ( GET_CODE ( addr1 ) != REG ) return 0 ; else { reg1 = REGNO ( addr1 ) ; offset1 = 0 ; } if ( GET_CODE ( addr2 ) != PLUS ) return 0 ; if ( GET_CODE ( XEXP ( addr2 , 0 ) ) != REG || GET_CODE ( XEXP ( addr2 , 1 ) ) != CONST_INT ) return 0 ; if ( reg1 != REGNO ( XEXP ( addr2 , 0 ) ) ) return 0 ; if ( dependent_reg_rtx != NULL_RTX && reg1 == REGNO ( dependent_reg_rtx ) ) return 0 ; if ( offset1 % 8 != 0 ) return 0 ; if ( INTVAL ( XEXP ( addr2 , 1 ) ) != offset1 + 4 ) return 0 ; return 1 ; } </s>

Return 1 if the addresses in mem1 and mem2 are suitable for use in an ldd or std insn . This can only happen when addr1 and addr2 , the addresses in mem1 and mem2 , are consecutive memory locations ( addr1 + 4 == addr2 ) . addr1 must also be aligned on a 64-bit boundary . Also iff dependent_reg_rtx is not null it should not be used to compute the address for mem1 , i.e . we can not optimize a sequence like : ld [ % o0 ] , % o0 ld [ % o0 + 4 ] , % o1 to ldd [ % o0 ] , % o0 nor : ld [ % g3 + 4 ] , % g3 ld [ % g3 ] , % g2 to ldd [ % g3 ] , % g2 But , note that the transformation from : ld [ % g2 + 4 ] , % g3 ld [ % g2 ] , % g2 to ldd [ % g2 ] , % g2 is perfectly fine . Thus , the peephole2 patterns always pass us the destination register of the first load , never the second one . For stores we do n't have a similar problem , so dependent_reg_rtx is NULL_RTX .


<s>
void
NVPTXAsmPrinter
::
emitFunctionEntryLabel
(
)
{
SmallString
<
128
>
Str
;
raw_svector_ostream
O
(
Str
)
;
if
(
!
GlobalsEmitted
)
{
emitGlobals
(
*
MF
->
getFunction
(
)
.
getParent
(
)
)
;
GlobalsEmitted
=
true
;
}
MRI
=
&
MF
->
getRegInfo
(
)
;
F
=
&
MF
->
getFunction
(
)
;
emitLinkageDirective
(
F
,
O
)
;
if
(
isKernelFunction
(
*
F
)
)
O
<<
".entry "
;
else
{
O
<<
".func "
;
printReturnValStr
(
*
MF
,
O
)
;
}
CurrentFnSym
->
print
(
O
,
MAI
)
;
emitFunctionParamList
(
*
MF
,
O
)
;
if
(
isKernelFunction
(
*
F
)
)
emitKernelFunctionDirectives
(
*
F
,
O
)
;
OutStreamer
->
emitRawText
(
O
.
str
(
)
)
;
VRegMapping
.
clear
(
)
;
OutStreamer
->
emitRawText
(
StringRef
(
"{\n"
)
)
;
setAndEmitFunctionVirtualRegisters
(
*
MF
)
;
if
(
MMI
&&
MMI
->
hasDebugInfo
(
)
)
emitInitialRawDwarfLocDirective
(
*
MF
)
;
}
</s>

EmitFunctionEntryLabel - Emit the label that is the entrypoint for the function .

NVPTX
NVPTX
128
".entry "
".func "
"{\n"


<s> unsigned getNumFixupKinds ( ) const { return 3 ; } </s>

Get the number of target specific fixup kinds .


<s> static sbitmap aarch64_components_for_bb ( basic_block bb ) { bitmap in = DF_LIVE_IN ( bb ) ; bitmap gen = & DF_LIVE_BB_INFO ( bb ) -> gen ; bitmap kill = & DF_LIVE_BB_INFO ( bb ) -> kill ; sbitmap components = sbitmap_alloc ( LAST_SAVED_REGNUM + 1 ) ; bitmap_clear ( components ) ; for ( unsigned regno = 0 ; regno <= LAST_SAVED_REGNUM ; regno ++ ) if ( ( ! call_used_regs [ regno ] ) && ( bitmap_bit_p ( in , regno ) || bitmap_bit_p ( gen , regno ) || bitmap_bit_p ( kill , regno ) ) ) { unsigned regno2 , offset , offset2 ; bitmap_set_bit ( components , regno ) ; offset = cfun -> machine -> frame . reg_offset [ regno ] ; regno2 = ( ( offset & 8 ) == 0 ) ? regno + 1 : regno - 1 ; if ( regno2 <= LAST_SAVED_REGNUM ) { offset2 = cfun -> machine -> frame . reg_offset [ regno2 ] ; if ( ( offset & ~ 8 ) == ( offset2 & ~ 8 ) ) bitmap_set_bit ( components , regno2 ) ; } } return components ; } </s>


<s> const MCSection * SystemZMCAsmInfo :: getNonexecutableStackSection ( MCContext & Ctx ) const { return Ctx . getELFSection ( ".note.GNU-stack" , ELF :: SHT_PROGBITS , 0 , SectionKind :: getMetadata ( ) ) ; } </s>

Targets can implement this method to specify a section to switch to if the translation unit does n't have any trampolines that require an executable stack .


<s> bool MCS51FrameLowering :: hasReservedCallFrame ( const MachineFunction & MF ) const { const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; return hasFP ( MF ) && ! MFI . hasVarSizedObjects ( ) ; } </s>

hasReservedCallFrame - Under normal circumstances , when a frame pointer is not required , we reserve argument space for call sites in the function immediately on entry to the current function .


<s> void MipsPassConfig :: addPreEmitPass ( ) { MipsTargetMachine & TM = getMipsTargetMachine ( ) ; addPass ( createMipsDelaySlotFillerPass ( TM ) ) ; addPass ( createMipsLongBranchPass ( TM ) ) ; addPass ( createMipsConstantIslandPass ( TM ) ) ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s> static bool is_load_insn1 ( rtx pat , rtx * load_mem ) { if ( ! pat || pat == NULL_RTX ) return false ; if ( GET_CODE ( pat ) == SET ) return find_mem_ref ( SET_SRC ( pat ) , load_mem ) ; if ( GET_CODE ( pat ) == PARALLEL ) { int i ; for ( i = 0 ; i < XVECLEN ( pat , 0 ) ; i ++ ) if ( is_load_insn1 ( XVECEXP ( pat , 0 , i ) , load_mem ) ) return true ; } return false ; } </s>

Determine if PAT is a PATTERN of a load insn .


<s> SDValue NVPTXTargetLowering :: PerformDAGCombine ( SDNode * N , DAGCombinerInfo & DCI ) const { CodeGenOpt :: Level OptLevel = getTargetMachine ( ) . getOptLevel ( ) ; switch ( N -> getOpcode ( ) ) { default : break ; case ISD :: ADD : case ISD :: FADD : return PerformADDCombine ( N , DCI , STI , OptLevel ) ; case ISD :: MUL : return PerformMULCombine ( N , DCI , OptLevel ) ; case ISD :: SHL : return PerformSHLCombine ( N , DCI , OptLevel ) ; case ISD :: AND : return PerformANDCombine ( N , DCI ) ; } return SDValue ( ) ; } </s>

This method will be invoked for all target nodes and for any target-independent nodes that the target has registered with invoke it for .

NVPTX NVPTX ISD::ADD ISD::FADD ISD::MUL ISD::SHL ISD::AND


<s> bool AlphaTargetMachine :: addInstSelector ( PassManagerBase & PM , bool Fast ) { PM . add ( createAlphaISelDag ( * this ) ) ; return false ; } </s>

addInstSelector - This method should install an instruction selector pass , which converts from LLVM code to machine instructions .


"********** Optimize returned Attributes **********\n"

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .


<s> bool evaluateBranch ( MCInst const & Inst , uint64_t Addr , uint64_t Size , uint64_t & Target ) const override { if ( ! HexagonMCInstrInfo :: isExtendable ( * Info , Inst ) ) return false ; auto const & Extended ( HexagonMCInstrInfo :: getExtendableOperand ( * Info , Inst ) ) ; assert ( Extended . isExpr ( ) ) ; int64_t Value ; if ( ! Extended . getExpr ( ) -> evaluateAsAbsolute ( Value ) ) return false ; Target = Value ; return true ; } </s>

Given a branch instruction try to get the address the branch targets .


<s> static reg_class_t ix86_preferred_reload_class ( rtx x , reg_class_t regclass ) { machine_mode mode = GET_MODE ( x ) ; if ( regclass == NO_REGS ) return NO_REGS ; if ( x == CONST0_RTX ( mode ) ) return regclass ; if ( CONSTANT_P ( x ) && ( MAYBE_MMX_CLASS_P ( regclass ) || MAYBE_SSE_CLASS_P ( regclass ) || MAYBE_MASK_CLASS_P ( regclass ) ) ) return NO_REGS ; if ( CONST_DOUBLE_P ( x ) ) { if ( INTEGER_CLASS_P ( regclass ) ) return regclass ; if ( IS_STACK_MODE ( mode ) && standard_80387_constant_p ( x ) > 0 ) { if ( FLOAT_CLASS_P ( regclass ) ) return FLOAT_REGS ; } return NO_REGS ; } if ( SSE_FLOAT_MODE_P ( mode ) && TARGET_SSE_MATH ) { if ( TARGET_INTER_UNIT_MOVES_FROM_VEC && TARGET_INTER_UNIT_MOVES_TO_VEC && GET_MODE_SIZE ( mode ) <= GET_MODE_SIZE ( word_mode ) ) return INT_SSE_CLASS_P ( regclass ) ? regclass : NO_REGS ; else return SSE_CLASS_P ( regclass ) ? regclass : NO_REGS ; } if ( GET_CODE ( x ) == PLUS ) return INTEGER_CLASS_P ( regclass ) ? regclass : NO_REGS ; if ( GET_MODE ( x ) == QImode && ! CONSTANT_P ( x ) ) { if ( Q_CLASS_P ( regclass ) ) return regclass ; else if ( reg_class_subset_p ( Q_REGS , regclass ) ) return Q_REGS ; else if ( MASK_CLASS_P ( regclass ) ) return regclass ; else return NO_REGS ; } return regclass ; } </s>

Put float CONST_DOUBLE in the constant pool instead of fp regs . QImode must go into class Q_REGS . Narrow ALL_REGS to GENERAL_REGS . This supports allowing movsf and movdf to do mem-to-mem moves through integer regs .


<s> bool SIInstrInfo :: findCommutedOpIndices ( MachineInstr & MI , unsigned & SrcOpIdx0 , unsigned & SrcOpIdx1 ) const { if ( ! MI . isCommutable ( ) ) return false ; unsigned Opc = MI . getOpcode ( ) ; int Src0Idx = AMDGPU :: getNamedOperandIdx ( Opc , AMDGPU :: OpName :: src0 ) ; if ( Src0Idx == - 1 ) return false ; int Src1Idx = AMDGPU :: getNamedOperandIdx ( Opc , AMDGPU :: OpName :: src1 ) ; if ( Src1Idx == - 1 ) return false ; return fixCommutedOpIndices ( SrcOpIdx0 , SrcOpIdx1 , Src0Idx , Src1Idx ) ; } </s>

Returns true iff the routine could find two commutable operands in the given machine instruction .

AMDGPU SI AMDGPU::getNamedOperandIdx AMDGPU::OpName 1 AMDGPU::getNamedOperandIdx AMDGPU::OpName 1


<s> bool fixupNeedsRelaxationAdvanced ( const MCFixup & Fixup , bool Resolved , uint64_t Value , const MCRelaxableFragment * DF , const MCAsmLayout & Layout , const bool WasForced ) const override { MCInst const & MCB = DF -> getInst ( ) ; assert ( HexagonMCInstrInfo :: isBundle ( MCB ) ) ; * RelaxTarget = nullptr ; MCInst & MCI = const_cast < MCInst & > ( HexagonMCInstrInfo :: instruction ( MCB , Fixup . getOffset ( ) / HEXAGON_INSTR_SIZE ) ) ; bool Relaxable = isInstRelaxable ( MCI ) ; if ( Relaxable == false ) return false ; if ( ! Resolved ) { switch ( ( unsigned ) Fixup . getKind ( ) ) { case fixup_Hexagon_B22_PCREL : LLVM_FALLTHROUGH ; default : return false ; break ; case fixup_Hexagon_B13_PCREL : case fixup_Hexagon_B15_PCREL : case fixup_Hexagon_B9_PCREL : case fixup_Hexagon_B7_PCREL : { if ( HexagonMCInstrInfo :: bundleSize ( MCB ) < HEXAGON_PACKET_SIZE ) { ++ relaxedCnt ; * RelaxTarget = & MCI ; setExtender ( Layout . getAssembler ( ) . getContext ( ) ) ; return true ; } else { return false ; } break ; } } } MCFixupKind Kind = Fixup . getKind ( ) ; int64_t sValue = Value ; int64_t maxValue ; switch ( ( unsigned ) Kind ) { case fixup_Hexagon_B7_PCREL : maxValue = 1 << 8 ; break ; case fixup_Hexagon_B9_PCREL : maxValue = 1 << 10 ; break ; case fixup_Hexagon_B15_PCREL : maxValue = 1 << 16 ; break ; case fixup_Hexagon_B22_PCREL : maxValue = 1 << 23 ; break ; default : maxValue = INT64_MAX ; break ; } bool isFarAway = - maxValue > sValue || sValue > maxValue - 1 ; if ( isFarAway ) { if ( HexagonMCInstrInfo :: bundleSize ( MCB ) < HEXAGON_PACKET_SIZE ) { ++ relaxedCnt ; * RelaxTarget = & MCI ; setExtender ( Layout . getAssembler ( ) . getContext ( ) ) ; return true ; } } return false ; } </s>

Target specific predicate for whether a given fixup requires the associated instruction to be relaxed .


"LowerFormalArguments Unhandled argument type: "

This hook must be implemented to lower the incoming ( formal ) arguments , described by the Ins array , into the specified DAG .


<s> void SystemZTargetLowering :: LowerAsmOperandForConstraint ( SDValue Op , std :: string & Constraint , std :: vector < SDValue > & Ops , SelectionDAG & DAG ) const { if ( Constraint . length ( ) == 1 ) { switch ( Constraint [ 0 ] ) { case 'I' : if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Op ) ) if ( isUInt < 8 > ( C -> getZExtValue ( ) ) ) Ops . push_back ( DAG . getTargetConstant ( C -> getZExtValue ( ) , Op . getValueType ( ) ) ) ; return ; case 'J' : if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Op ) ) if ( isUInt < 12 > ( C -> getZExtValue ( ) ) ) Ops . push_back ( DAG . getTargetConstant ( C -> getZExtValue ( ) , Op . getValueType ( ) ) ) ; return ; case 'K' : if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Op ) ) if ( isInt < 16 > ( C -> getSExtValue ( ) ) ) Ops . push_back ( DAG . getTargetConstant ( C -> getSExtValue ( ) , Op . getValueType ( ) ) ) ; return ; case 'L' : if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Op ) ) if ( isInt < 20 > ( C -> getSExtValue ( ) ) ) Ops . push_back ( DAG . getTargetConstant ( C -> getSExtValue ( ) , Op . getValueType ( ) ) ) ; return ; case 'M' : if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Op ) ) if ( C -> getZExtValue ( ) == 0x7fffffff ) Ops . push_back ( DAG . getTargetConstant ( C -> getZExtValue ( ) , Op . getValueType ( ) ) ) ; return ; } } TargetLowering :: LowerAsmOperandForConstraint ( Op , Constraint , Ops , DAG ) ; } </s>

Lower the specified operand into the Ops vector .


<s>
void
print
(
raw_ostream
&
O
)
const
override
{
switch
(
Kind
)
{
case
k_None
:
O
<<
"None"
;
break
;
case
k_Token
:
O
<<
"Token: \""
<<
getToken
(
)
<<
"\""
;
break
;
case
k_Register
:
O
<<
"Register: "
<<
getReg
(
)
;
break
;
case
k_Immediate
:
O
<<
"Immediate: \""
<<
*
getImm
(
)
<<
"\""
;
break
;
}
O
<<
"\n"
;
}
</s>

print - Print a debug representation of the operand to the given stream .

MOS
"None"
"Token: \""
"\""
"Register: "
"Immediate: \""
"\""
"\n"


<s>
EVT
AMDGPUTargetLowering
::
getTypeForExtReturn
(
LLVMContext
&
Context
,
EVT
VT
,
ISD
::
NodeType
ExtendKind
)
const
{
assert
(
!
VT
.
isVector
(
)
&&
"only scalar expected"
)
;
unsigned
Size
=
VT
.
getSizeInBits
(
)
;
if
(
Size
<=
32
)
return
MVT
::
i32
;
return
EVT
::
getIntegerVT
(
Context
,
32
*
(
(
Size
+
31
)
/
32
)
)
;
}
</s>

Return the type that should be used to zero or sign extend a zeroext/signext integer return value .


<s> void scalar_chain :: convert_insn ( rtx_insn * insn ) { rtx def_set = single_set ( insn ) ; rtx src = SET_SRC ( def_set ) ; rtx dst = SET_DEST ( def_set ) ; rtx subreg ; if ( MEM_P ( dst ) && ! REG_P ( src ) ) { rtx tmp = gen_reg_rtx ( DImode ) ; emit_conversion_insns ( gen_move_insn ( dst , tmp ) , insn ) ; dst = gen_rtx_SUBREG ( V2DImode , tmp , 0 ) ; } switch ( GET_CODE ( src ) ) { case PLUS : case MINUS : case IOR : case XOR : case AND : convert_op ( & XEXP ( src , 0 ) , insn ) ; convert_op ( & XEXP ( src , 1 ) , insn ) ; PUT_MODE ( src , V2DImode ) ; break ; case MEM : if ( ! REG_P ( dst ) ) convert_op ( & src , insn ) ; break ; case REG : if ( ! MEM_P ( dst ) ) convert_op ( & src , insn ) ; break ; case SUBREG : gcc_assert ( GET_MODE ( src ) == V2DImode ) ; break ; case COMPARE : src = SUBREG_REG ( XEXP ( XEXP ( src , 0 ) , 0 ) ) ; gcc_assert ( ( REG_P ( src ) && GET_MODE ( src ) == DImode ) || ( SUBREG_P ( src ) && GET_MODE ( src ) == V2DImode ) ) ; if ( REG_P ( src ) ) subreg = gen_rtx_SUBREG ( V2DImode , src , 0 ) ; else subreg = copy_rtx_if_shared ( src ) ; emit_insn_before ( gen_vec_interleave_lowv2di ( copy_rtx_if_shared ( subreg ) , copy_rtx_if_shared ( subreg ) , copy_rtx_if_shared ( subreg ) ) , insn ) ; dst = gen_rtx_REG ( CCmode , FLAGS_REG ) ; src = gen_rtx_UNSPEC ( CCmode , gen_rtvec ( 2 , copy_rtx_if_shared ( src ) , copy_rtx_if_shared ( src ) ) , UNSPEC_PTEST ) ; break ; default : gcc_unreachable ( ) ; } SET_SRC ( def_set ) = src ; SET_DEST ( def_set ) = dst ; PATTERN ( insn ) = def_set ; INSN_CODE ( insn ) = - 1 ; recog_memoized ( insn ) ; df_insn_rescan ( insn ) ; } </s>


<s> pad_direction rs6000_function_arg_padding ( machine_mode mode , const_tree type ) { if ( ! AGGREGATE_PADDING_FIXED ) { if ( BYTES_BIG_ENDIAN ) { HOST_WIDE_INT size = 0 ; if ( mode == BLKmode ) { if ( type && TREE_CODE ( TYPE_SIZE ( type ) ) == INTEGER_CST ) size = int_size_in_bytes ( type ) ; } else size = GET_MODE_SIZE ( mode ) ; if ( size == 1 || size == 2 || size == 4 ) return PAD_DOWNWARD ; } return PAD_UPWARD ; } if ( AGGREGATES_PAD_UPWARD_ALWAYS ) { if ( type != 0 && AGGREGATE_TYPE_P ( type ) ) return PAD_UPWARD ; } return default_function_arg_padding ( mode , type ) ; } </s>

Implement TARGET_FUNCTION_ARG_PADDING . For the AIX ABI structs are always stored left shifted in their argument slot .


<s> rtx v850_return_addr ( int count ) { if ( count != 0 ) return const0_rtx ; return get_hard_reg_initial_val ( Pmode , LINK_POINTER_REGNUM ) ; } </s>

Return an RTX indicating where the return address to the calling function can be found .


<s>
void
emit_safe_across_calls
(
void
)
{
unsigned
int
rs
,
re
;
int
out_state
;
rs
=
1
;
out_state
=
0
;
while
(
1
)
{
while
(
rs
<
64
&&
call_used_or_fixed_reg_p
(
PR_REG
(
rs
)
)
)
rs
++
;
if
(
rs
>=
64
)
break
;
for
(
re
=
rs
+
1
;
re
<
64
&&
!
call_used_or_fixed_reg_p
(
PR_REG
(
re
)
)
;
re
++
)
continue
;
if
(
out_state
==
0
)
{
fputs
(
"\t.pred.safe_across_calls "
,
asm_out_file
)
;
out_state
=
1
;
}
else
fputc
(
','
,
asm_out_file
)
;
if
(
re
==
rs
+
1
)
fprintf
(
asm_out_file
,
"p%u"
,
rs
)
;
else
fprintf
(
asm_out_file
,
"p%u-p%u"
,
rs
,
re
1
)
;
rs
=
re
+
1
;
}
if
(
out_state
)
fputc
(
'\n'
,
asm_out_file
)
;
}
</s>


<s> BitVector ARMBaseRegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { const TargetFrameLowering * TFI = MF . getTarget ( ) . getFrameLowering ( ) ; BitVector Reserved ( getNumRegs ( ) ) ; Reserved . set ( ARM :: SP ) ; Reserved . set ( ARM :: PC ) ; Reserved . set ( ARM :: FPSCR ) ; if ( TFI -> hasFP ( MF ) ) Reserved . set ( FramePtr ) ; if ( hasBasePointer ( MF ) ) Reserved . set ( BasePtr ) ; if ( STI . isR9Reserved ( ) ) Reserved . set ( ARM :: R9 ) ; if ( ! STI . hasVFP3 ( ) || STI . hasD16 ( ) ) { assert ( ARM :: D31 == ARM :: D16 + 15 ) ; for ( unsigned i = 0 ; i != 16 ; ++ i ) Reserved . set ( ARM :: D16 + i ) ; } return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s> void HexagonInstrInfo :: storeRegToStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned SrcReg , bool isKill , int FI , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { DebugLoc DL = MBB . findDebugLoc ( I ) ; MachineFunction & MF = * MBB . getParent ( ) ; MachineFrameInfo & MFI = * MF . getFrameInfo ( ) ; unsigned Align = MFI . getObjectAlignment ( FI ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( MF , FI ) , MachineMemOperand :: MOStore , MFI . getObjectSize ( FI ) , Align ) ; if ( Hexagon :: IntRegsRegClass . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( Hexagon :: S2_storeri_io ) ) . addFrameIndex ( FI ) . addImm ( 0 ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addMemOperand ( MMO ) ; } else if ( Hexagon :: DoubleRegsRegClass . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( Hexagon :: S2_storerd_io ) ) . addFrameIndex ( FI ) . addImm ( 0 ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addMemOperand ( MMO ) ; } else if ( Hexagon :: PredRegsRegClass . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( Hexagon :: STriw_pred ) ) . addFrameIndex ( FI ) . addImm ( 0 ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addMemOperand ( MMO ) ; } else if ( Hexagon :: ModRegsRegClass . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( Hexagon :: STriw_mod ) ) . addFrameIndex ( FI ) . addImm ( 0 ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addMemOperand ( MMO ) ; } else { llvm_unreachable ( "Unimplemented" ) ; } } </s>

Store the specified register of the given register class to the specified stack frame index .


<s> static int msp430_single_op_cost ( rtx dst , bool speed , rtx outer_rtx ) { enum rtx_code dst_code = GET_CODE ( dst ) ; const struct single_op_cost * cost_p ; const struct double_op_cost * double_op_cost_p ; cost_p = ( speed ? & cycle_cost_single_op : & size_cost_single_op ) ; double_op_cost_p = ( speed ? & cycle_cost_double_op : & size_cost_double_op ) ; switch ( dst_code ) { case REG : return cost_p -> reg ; case MEM : if ( msp430_is_mem_indirect ( dst ) ) return cost_p -> ind ; else return cost_p -> mem ; case CONST_INT : case CONST_FIXED : case CONST_DOUBLE : case SYMBOL_REF : case CONST : return double_op_cost_p -> imm2r + cost_p -> reg ; default : return cost_p -> mem ; } } </s>

Calculate the cost of an MSP430 single-operand instruction , for operand DST within the RTX OUTER_RTX , optimizing for speed if SPEED is true .


<s> MachineFunction & getMF ( ) const { return MF ; } </s>

Return the function that contains the basic block that this instruction belongs to .


<s> const uint32_t * X86RegisterInfo :: getCallPreservedMask ( const MachineFunction & MF , CallingConv :: ID CC ) const { const X86Subtarget & Subtarget = MF . getSubtarget < X86Subtarget > ( ) ; bool HasSSE = Subtarget . hasSSE1 ( ) ; bool HasAVX = Subtarget . hasAVX ( ) ; bool HasAVX512 = Subtarget . hasAVX512 ( ) ; switch ( CC ) { case CallingConv :: GHC : case CallingConv :: HiPE : return CSR_NoRegs_RegMask ; case CallingConv :: AnyReg : if ( HasAVX ) return CSR_64_AllRegs_AVX_RegMask ; return CSR_64_AllRegs_RegMask ; case CallingConv :: PreserveMost : return CSR_64_RT_MostRegs_RegMask ; case CallingConv :: PreserveAll : if ( HasAVX ) return CSR_64_RT_AllRegs_AVX_RegMask ; return CSR_64_RT_AllRegs_RegMask ; case CallingConv :: CXX_FAST_TLS : if ( Is64Bit ) return CSR_64_TLS_Darwin_RegMask ; break ; case CallingConv :: Intel_OCL_BI : { if ( HasAVX512 && IsWin64 ) return CSR_Win64_Intel_OCL_BI_AVX512_RegMask ; if ( HasAVX512 && Is64Bit ) return CSR_64_Intel_OCL_BI_AVX512_RegMask ; if ( HasAVX && IsWin64 ) return CSR_Win64_Intel_OCL_BI_AVX_RegMask ; if ( HasAVX && Is64Bit ) return CSR_64_Intel_OCL_BI_AVX_RegMask ; if ( ! HasAVX && ! IsWin64 && Is64Bit ) return CSR_64_Intel_OCL_BI_RegMask ; break ; } case CallingConv :: HHVM : return CSR_64_HHVM_RegMask ; case CallingConv :: X86_RegCall : if ( Is64Bit ) { if ( IsWin64 ) { return ( HasSSE ? CSR_Win64_RegCall_RegMask : CSR_Win64_RegCall_NoSSE_RegMask ) ; } else { return ( HasSSE ? CSR_SysV64_RegCall_RegMask : CSR_SysV64_RegCall_NoSSE_RegMask ) ; } } else { return ( HasSSE ? CSR_32_RegCall_RegMask : CSR_32_RegCall_NoSSE_RegMask ) ; } case CallingConv :: Cold : if ( Is64Bit ) return CSR_64_MostRegs_RegMask ; break ; case CallingConv :: Win64 : return CSR_Win64_RegMask ; case CallingConv :: X86_64_SysV : return CSR_64_RegMask ; case CallingConv :: X86_INTR : if ( Is64Bit ) { if ( HasAVX512 ) return CSR_64_AllRegs_AVX512_RegMask ; if ( HasAVX ) return CSR_64_AllRegs_AVX_RegMask ; if ( HasSSE ) return CSR_64_AllRegs_RegMask ; return CSR_64_AllRegs_NoSSE_RegMask ; } else { if ( HasAVX512 ) return CSR_32_AllRegs_AVX512_RegMask ; if ( HasAVX ) return CSR_32_AllRegs_AVX_RegMask ; if ( HasSSE ) return CSR_32_AllRegs_SSE_RegMask ; return CSR_32_AllRegs_RegMask ; } default : break ; } if ( Is64Bit ) { const Function & F = MF . getFunction ( ) ; bool IsSwiftCC = Subtarget . getTargetLowering ( ) -> supportSwiftError ( ) && F . getAttributes ( ) . hasAttrSomewhere ( Attribute :: SwiftError ) ; if ( IsSwiftCC ) return IsWin64 ? CSR_Win64_SwiftError_RegMask : CSR_64_SwiftError_RegMask ; return IsWin64 ? CSR_Win64_RegMask : CSR_64_RegMask ; } return CSR_32_RegMask ; } </s>

Return a mask of call-preserved registers for the given calling convention on the current function .


<s>
StringRef
getPassName
(
)
const
override
{
return
"TVM Cheap Definitions Rematerialize"
;
}
</s>

getPassName - Return a nice clean name for a pass .

TVM
"TVM Cheap Definitions Rematerialize"


<s> static int aarch64_ld234_st234_vectors ( vect_cost_for_stmt kind , stmt_vec_info stmt_info ) { if ( ( kind == vector_load || kind == unaligned_load || kind == vector_store || kind == unaligned_store ) && STMT_VINFO_DATA_REF ( stmt_info ) ) { stmt_info = DR_GROUP_FIRST_ELEMENT ( stmt_info ) ; if ( stmt_info && STMT_VINFO_MEMORY_ACCESS_TYPE ( stmt_info ) == VMAT_LOAD_STORE_LANES ) return DR_GROUP_SIZE ( stmt_info ) ; } return 0 ; } </s>

Return true if an access of kind KIND for STMT_INFO represents one vector of an LD [ 234 ] or ST [ 234 ] operation . Return the total number of vectors ( 2 , 3 or 4 ) if so , otherwise return a value outside that range .


<s> bool AArch64AsmBackend :: shouldForceRelocation ( const MCAssembler & Asm , const MCFixup & Fixup , const MCValue & Target ) { if ( ( uint32_t ) Fixup . getKind ( ) == AArch64 :: fixup_aarch64_pcrel_adrp_imm21 ) return true ; AArch64MCExpr :: VariantKind RefKind = static_cast < AArch64MCExpr :: VariantKind > ( Target . getRefKind ( ) ) ; AArch64MCExpr :: VariantKind SymLoc = AArch64MCExpr :: getSymbolLoc ( RefKind ) ; if ( ( uint32_t ) Fixup . getKind ( ) == AArch64 :: fixup_aarch64_ldr_pcrel_imm19 && SymLoc == AArch64MCExpr :: VK_GOT ) return true ; return false ; } </s>

Hook to check if a relocation is needed for some target specific reason .


<s> static reg_class_t xtensa_secondary_reload ( bool in_p , rtx x , reg_class_t rclass , machine_mode mode , secondary_reload_info * sri ) { int regno ; if ( in_p && constantpool_mem_p ( x ) ) { if ( rclass == FP_REGS ) return RL_REGS ; if ( mode == QImode ) sri -> icode = CODE_FOR_reloadqi_literal ; else if ( mode == HImode ) sri -> icode = CODE_FOR_reloadhi_literal ; } regno = xt_true_regnum ( x ) ; if ( ACC_REG_P ( regno ) ) return ( ( rclass == GR_REGS || rclass == RL_REGS ) ? NO_REGS : RL_REGS ) ; if ( rclass == ACC_REG ) return ( GP_REG_P ( regno ) ? NO_REGS : RL_REGS ) ; return NO_REGS ; } </s>

Worker function for TARGET_SECONDARY_RELOAD .


<s> static bool arm_valid_target_attribute_p ( tree fndecl , tree ARG_UNUSED ( name ) , tree args , int ARG_UNUSED ( flags ) ) { bool ret = true ; struct gcc_options func_options ; tree cur_tree , new_optimize ; gcc_assert ( ( fndecl != NULL_TREE ) && ( args != NULL_TREE ) ) ; tree func_optimize = DECL_FUNCTION_SPECIFIC_OPTIMIZATION ( fndecl ) ; if ( ! func_optimize ) func_optimize = optimization_default_node ; memset ( & func_options , 0 , sizeof ( func_options ) ) ; init_options_struct ( & func_options , NULL ) ; lang_hooks . init_options_struct ( & func_options ) ; cl_optimization_restore ( & func_options , TREE_OPTIMIZATION ( func_optimize ) ) ; cl_target_option_restore ( & func_options , TREE_TARGET_OPTION ( target_option_default_node ) ) ; cur_tree = arm_valid_target_attribute_tree ( args , & func_options , & global_options_set ) ; if ( cur_tree == NULL_TREE ) ret = false ; new_optimize = build_optimization_node ( & func_options ) ; DECL_FUNCTION_SPECIFIC_TARGET ( fndecl ) = cur_tree ; DECL_FUNCTION_SPECIFIC_OPTIMIZATION ( fndecl ) = new_optimize ; finalize_options_struct ( & func_options ) ; return ret ; } </s>

Hook to validate attribute ( ( target ( `` string '' ) ) ) .


<s> static bool epiphany_return_in_memory ( const_tree type , const_tree fntype ATTRIBUTE_UNUSED ) { HOST_WIDE_INT size = int_size_in_bytes ( type ) ; if ( AGGREGATE_TYPE_P ( type ) && ( TYPE_MODE ( type ) == BLKmode || TYPE_NEEDS_CONSTRUCTING ( type ) ) ) return true ; return ( size == - 1 || size > 8 ) ; } </s>

Worker function for TARGET_RETURN_IN_MEMORY .


<s> bool isCall ( const MCInst & MI , bool * IsIndirectCall ) { unsigned Opcode = MI . getOpcode ( ) ; * IsIndirectCall = false ; switch ( Opcode ) { default : return false ; case Mips :: JAL : case Mips :: BAL_BR : return true ; case Mips :: JALR : assert ( MI . getOperand ( 0 ) . isReg ( ) ) ; if ( MI . getOperand ( 0 ) . getReg ( ) == Mips :: ZERO ) return false ; * IsIndirectCall = true ; return true ; } } </s>


"Instr doesn't have FrameIndex operand!"

Resolve a frame index operand of an instruction to reference the indicated base register plus offset instead .


<s> bool M68kPassConfig :: addLegalizeMachineIR ( ) { addPass ( new Legalizer ( ) ) ; return false ; } </s>

This method should install a legalize pass , which converts the instruction sequence into one that can be selected by the target .


<s> int X86TTIImpl :: getIntImmCost ( unsigned Opcode , unsigned Idx , const APInt & Imm , Type * Ty ) { assert ( Ty -> isIntegerTy ( ) ) ; unsigned BitSize = Ty -> getPrimitiveSizeInBits ( ) ; if ( BitSize == 0 ) return TTI :: TCC_Free ; unsigned ImmIdx = ~ 0U ; switch ( Opcode ) { default : return TTI :: TCC_Free ; case Instruction :: GetElementPtr : if ( Idx == 0 ) return 2 * TTI :: TCC_Basic ; return TTI :: TCC_Free ; case Instruction :: Store : ImmIdx = 0 ; break ; case Instruction :: ICmp : if ( Idx == 1 && Imm . getBitWidth ( ) == 64 ) { uint64_t ImmVal = Imm . getZExtValue ( ) ; if ( ImmVal == 0x100000000ULL || ImmVal == 0xffffffff ) return TTI :: TCC_Free ; } ImmIdx = 1 ; break ; case Instruction :: And : if ( Idx == 1 && Imm . getBitWidth ( ) == 64 && isUInt < 32 > ( Imm . getZExtValue ( ) ) ) return TTI :: TCC_Free ; ImmIdx = 1 ; break ; case Instruction :: Add : case Instruction :: Sub : if ( Idx == 1 && Imm . getBitWidth ( ) == 64 && isInt < 32 > ( - Imm . getSExtValue ( ) ) ) return TTI :: TCC_Free ; ImmIdx = 1 ; break ; case Instruction :: Mul : case Instruction :: UDiv : case Instruction :: SDiv : case Instruction :: URem : case Instruction :: SRem : case Instruction :: Or : case Instruction :: Xor : ImmIdx = 1 ; break ; case Instruction :: Shl : case Instruction :: LShr : case Instruction :: AShr : if ( Idx == 1 ) return TTI :: TCC_Free ; break ; case Instruction :: Trunc : case Instruction :: ZExt : case Instruction :: SExt : case Instruction :: IntToPtr : case Instruction :: PtrToInt : case Instruction :: BitCast : case Instruction :: PHI : case Instruction :: Call : case Instruction :: Select : case Instruction :: Ret : case Instruction :: Load : break ; } if ( Idx == ImmIdx ) { int NumConstants = divideCeil ( BitSize , 64 ) ; int Cost = X86TTIImpl :: getIntImmCost ( Imm , Ty ) ; return ( Cost <= NumConstants * TTI :: TCC_Basic ) ? static_cast < int > ( TTI :: TCC_Free ) : Cost ; } return X86TTIImpl :: getIntImmCost ( Imm , Ty ) ; } </s>

Calculate the cost of materializing a 64-bit value .


<s> unsigned getNumFixupKinds ( ) const override { return 0 ; } </s>

Get the number of target specific fixup kinds .


<s> DecodeStatus ARM64Disassembler :: getInstruction ( MCInst & MI , uint64_t & Size , const MemoryObject & Region , uint64_t Address , raw_ostream & os , raw_ostream & cs ) const { CommentStream = & cs ; uint8_t bytes [ 4 ] ; Size = 0 ; if ( Region . readBytes ( Address , 4 , ( uint8_t * ) bytes ) == - 1 ) return Fail ; Size = 4 ; uint32_t insn = ( bytes [ 3 ] << 24 ) | ( bytes [ 2 ] << 16 ) | ( bytes [ 1 ] << 8 ) | ( bytes [ 0 ] << 0 ) ; DecodeStatus result = decodeInstruction ( DecoderTable32 , MI , insn , Address , this , STI ) ; if ( ! result ) return Fail ; return Success ; } </s>

Returns the disassembly of a single instruction .


<s> bool PatmosSPClone :: doInitialization ( Module & M ) { PatmosSinglePathInfo :: getRootNames ( SPRoots ) ; return false ; } </s>

Set up the AsmPrinter when we are working on a new module .


<s> void rs6000_split_v4si_init ( rtx operands [ ] ) { rtx dest = operands [ 0 ] ; if ( REG_P ( dest ) || SUBREG_P ( dest ) ) { int d_regno = regno_or_subregno ( dest ) ; rtx scalar1 = operands [ 1 ] ; rtx scalar2 = operands [ 2 ] ; rtx scalar3 = operands [ 3 ] ; rtx scalar4 = operands [ 4 ] ; rtx tmp1 = operands [ 5 ] ; rtx tmp2 = operands [ 6 ] ; if ( BYTES_BIG_ENDIAN ) { rtx di_lo = gen_rtx_REG ( DImode , d_regno ) ; rtx di_hi = gen_rtx_REG ( DImode , d_regno + 1 ) ; rs6000_split_v4si_init_di_reg ( di_lo , scalar1 , scalar2 , tmp1 ) ; rs6000_split_v4si_init_di_reg ( di_hi , scalar3 , scalar4 , tmp2 ) ; } else { rtx di_lo = gen_rtx_REG ( DImode , d_regno + 1 ) ; rtx di_hi = gen_rtx_REG ( DImode , d_regno ) ; gcc_assert ( ! VECTOR_ELT_ORDER_BIG ) ; rs6000_split_v4si_init_di_reg ( di_lo , scalar4 , scalar3 , tmp1 ) ; rs6000_split_v4si_init_di_reg ( di_hi , scalar2 , scalar1 , tmp2 ) ; } return ; } else gcc_unreachable ( ) ; } </s>


<s>
static
void
mmix_asm_output_mi_thunk
(
FILE
*
stream
,
tree
fndecl
ATTRIBUTE_UNUSED
,
HOST_WIDE_INT
delta
,
HOST_WIDE_INT
vcall_offset
ATTRIBUTE_UNUSED
,
tree
func
)
{
const
char
*
regname
=
reg_names
[
MMIX_FIRST_INCOMING_ARG_REGNUM
]
;
if
(
delta
>=
0
&&
delta
<
65536
)
fprintf
(
stream
,
"\tINCL %s,%d\n"
,
regname
,
(
int
)
delta
)
;
else
if
(
delta
<
0
&&
delta
>=
255
)
fprintf
(
stream
,
"\tSUBU %s,%s,%d\n"
,
regname
,
regname
,
(
int
)
delta
)
;
else
{
mmix_output_register_setting
(
stream
,
255
,
delta
,
1
)
;
fprintf
(
stream
,
"\tADDU %s,%s,$255\n"
,
regname
,
regname
)
;
}
fprintf
(
stream
,
"\tJMP "
)
;
assemble_name
(
stream
,
XSTR
(
XEXP
(
DECL_RTL
(
func
)
,
0
)
,
0
)
)
;
fprintf
(
stream
,
"\n"
)
;
}
</s>


<s> void TeakInstPrinter :: printRegName ( raw_ostream & OS , unsigned RegNo ) const { OS << StringRef ( getRegisterName ( RegNo ) ) . lower ( ) ; } </s>


"RegScavenger required for long branching"

"new block should be inserted for expanding unconditional branch"

"Branch offsets outside of the signed 32-bit range not supported"

Insert an unconditional indirect branch at the end of MBB to NewDestBB .


<s>
bool
MipsAsmParser
::
ParseInstruction
(
ParseInstructionInfo
&
Info
,
StringRef
Name
,
SMLoc
NameLoc
,
OperandVector
&
Operands
)
{
DEBUG
(
dbgs
(
)
<<
"ParseInstruction\n"
)
;
getTargetStreamer
(
)
.
setCanHaveModuleDir
(
false
)
;
if
(
!
mnemonicIsValid
(
Name
,
0
)
)
{
Parser
.
eatToEndOfStatement
(
)
;
return
Error
(
NameLoc
,
"Unknown instruction"
)
;
}
Operands
.
push_back
(
MipsOperand
::
CreateToken
(
Name
,
NameLoc
,
*
this
)
)
;
if
(
getLexer
(
)
.
isNot
(
AsmToken
::
EndOfStatement
)
)
{
if
(
ParseOperand
(
Operands
,
Name
)
)
{
SMLoc
Loc
=
getLexer
(
)
.
getLoc
(
)
;
Parser
.
eatToEndOfStatement
(
)
;
return
Error
(
Loc
,
"unexpected token in argument list"
)
;
}
if
(
getLexer
(
)
.
is
(
AsmToken
::
LBrac
)
&&
ParseBracketSuffix
(
Name
,
Operands
)
)
return
true
;
while
(
getLexer
(
)
.
is
(
AsmToken
::
Comma
)
)
{
Parser
.
Lex
(
)
;
if
(
ParseOperand
(
Operands
,
Name
)
)
{
SMLoc
Loc
=
getLexer
(
)
.
getLoc
(
)
;
Parser
.
eatToEndOfStatement
(
)
;
return
Error
(
Loc
,
"unexpected token in argument list"
)
;
}
if
(
getLexer
(
)
.
is
(
AsmToken
::
LBrac
)
)
{
if
(
ParseBracketSuffix
(
Name
,
Operands
)
)
return
true
;
}
else
if
(
getLexer
(
)
.
is
(
AsmToken
::
LParen
)
&&
ParseParenSuffix
(
Name
,
Operands
)
)
return
true
;
}
}
if
(
getLexer
(
)
.
isNot
(
AsmToken
::
EndOfStatement
)
)
{
SMLoc
Loc
=
getLexer
(
)
.
getLoc
(
)
;
Parser
.
eatToEndOfStatement
(
)
;
return
Error
(
Loc
,
"unexpected token in argument list"
)
;
}
Parser
.
Lex
(
)
;
return
false
;
}
</s>

ParseInstruction - Parse one assembly instruction .

Mips
Mips
"ParseInstruction\n"
0
"Unknown instruction"
MipsOperand::CreateToken
"unexpected token in argument list"
"unexpected token in argument list"
"unexpected token in argument list"


<s> int mve_struct_mem_operand ( rtx op ) { rtx ind = XEXP ( op , 0 ) ; if ( REG_P ( ind ) ) return arm_address_register_rtx_p ( ind , 0 ) ; if ( GET_CODE ( ind ) == POST_INC ) return arm_address_register_rtx_p ( XEXP ( ind , 0 ) , 0 ) ; return FALSE ; } </s>

Return TRUE if OP is a mem suitable for loading/storing an MVE struct type .


<s> static unsigned int aarch64_sve_adjust_stmt_cost ( vect_cost_for_stmt kind , stmt_vec_info stmt_info , tree vectype , unsigned int stmt_cost ) { if ( kind == vector_stmt && aarch64_extending_load_p ( stmt_info ) ) stmt_cost = 0 ; if ( kind == vector_stmt && aarch64_integer_truncation_p ( stmt_info ) ) stmt_cost = 0 ; if ( STMT_VINFO_GROUPED_ACCESS ( stmt_info ) ) { stmt_vec_info first = DR_GROUP_FIRST_ELEMENT ( stmt_info ) ; unsigned int count = DR_GROUP_SIZE ( first ) - DR_GROUP_GAP ( first ) ; unsigned int elt_bits = GET_MODE_UNIT_BITSIZE ( TYPE_MODE ( vectype ) ) ; if ( multiple_p ( count * elt_bits , 256 ) && aarch64_advsimd_ldp_stp_p ( kind , stmt_info ) ) stmt_cost *= 2 ; } return stmt_cost ; } </s>

STMT_COST is the cost calculated by aarch64_builtin_vectorization_cost for STMT_INFO , which has cost kind KIND and which when vectorized would operate on vector type VECTYPE . Adjust the cost as necessary for SVE targets .


<s> static bool bfin_vector_mode_supported_p ( enum machine_mode mode ) { return mode == V2HImode ; } </s>

Implements target hook vector_mode_supported_p .


<s> int aarch64_add_offset_temporaries ( rtx x ) { poly_int64 offset ; if ( ! poly_int_rtx_p ( x , & offset ) ) return - 1 ; return aarch64_offset_temporaries ( true , offset ) ; } </s>

If X can be represented as a poly_int64 , return the number of temporaries that are required to add it to a register . Return -1 otherwise .


<s> bool SPUSubtarget :: enablePostRAScheduler ( CodeGenOpt :: Level OptLevel , TargetSubtargetInfo :: AntiDepBreakMode & Mode , RegClassVector & CriticalPathRCs ) const { Mode = TargetSubtargetInfo :: ANTIDEP_CRITICAL ; CriticalPathRCs . clear ( ) ; CriticalPathRCs . push_back ( & SPU :: R8CRegClass ) ; CriticalPathRCs . push_back ( & SPU :: R16CRegClass ) ; CriticalPathRCs . push_back ( & SPU :: R32CRegClass ) ; CriticalPathRCs . push_back ( & SPU :: R32FPRegClass ) ; CriticalPathRCs . push_back ( & SPU :: R64CRegClass ) ; CriticalPathRCs . push_back ( & SPU :: VECREGRegClass ) ; return OptLevel >= CodeGenOpt :: Default ; } </s>

True if the subtarget should run a scheduler after register allocation .


<s> virtual bool SelectInlineAsmMemoryOperand ( const SDValue & Op , char ConstraintCode , std :: vector < SDValue > & OutOps ) { OutOps . push_back ( Op ) ; return false ; } </s>

SelectInlineAsmMemoryOperand - Select the specified address as a target addressing mode , according to the specified constraint .


"Kudeyar DAG->DAG Pattern Instruction Selection"

getPassName - Return a nice clean name for a pass .


<s> rtx widen_mem_for_ldd_peep ( rtx mem1 , rtx mem2 , machine_mode mode ) { rtx x = widen_memory_access ( mem1 , mode , 0 ) ; MEM_NOTRAP_P ( x ) = MEM_NOTRAP_P ( mem1 ) && MEM_NOTRAP_P ( mem2 ) ; return x ; } </s>

Return the widened memory access made of MEM1 and MEM2 in MODE .


<s> void MBlazeAsmPrinter :: emitFrameDirective ( ) { if ( ! OutStreamer . hasRawTextSupport ( ) ) return ; const TargetRegisterInfo & RI = * TM . getRegisterInfo ( ) ; unsigned stkReg = RI . getFrameRegister ( * MF ) ; unsigned retReg = RI . getRARegister ( ) ; unsigned stkSze = MF -> getFrameInfo ( ) -> getStackSize ( ) ; OutStreamer . EmitRawText ( "\t.frame\t" + Twine ( MBlazeInstPrinter :: getRegisterName ( stkReg ) ) + "," + Twine ( stkSze ) + "," + Twine ( MBlazeInstPrinter :: getRegisterName ( retReg ) ) ) ; } </s>

MBlaze MBlaze "\t.frame\t" MBlaze "," "," MBlaze


<s> static tree ix86_d_handle_target_object_format ( void ) { const char * objfmt = NULL ; if ( TARGET_MACHO ) objfmt = "macho" ; else if ( TARGET_COFF || TARGET_PECOFF ) objfmt = "coff" ; if ( objfmt == NULL ) return NULL_TREE ; return build_string_literal ( strlen ( objfmt ) + 1 , objfmt ) ; } </s>

Handle a call to ` __traits ( getTargetInfo , `` objectFormat '' ) ' .


<s> bool SIInstrInfo :: shouldClusterMemOps ( ArrayRef < const MachineOperand * > BaseOps1 , ArrayRef < const MachineOperand * > BaseOps2 , unsigned NumLoads , unsigned NumBytes ) const { if ( ! BaseOps1 . empty ( ) && ! BaseOps2 . empty ( ) ) { const MachineInstr & FirstLdSt = * BaseOps1 . front ( ) -> getParent ( ) ; const MachineInstr & SecondLdSt = * BaseOps2 . front ( ) -> getParent ( ) ; if ( ! memOpsHaveSameBasePtr ( FirstLdSt , BaseOps1 , SecondLdSt , BaseOps2 ) ) return false ; } else if ( ! BaseOps1 . empty ( ) || ! BaseOps2 . empty ( ) ) { return false ; } const unsigned LoadSize = NumBytes / NumLoads ; const unsigned NumDWORDs = ( ( LoadSize + 3 ) / 4 ) * NumLoads ; return NumDWORDs <= 8 ; } </s>

Returns true if the two given memory operations should be scheduled adjacent .


<s> bool AArch64AsmParser :: parsePrimaryExpr ( const MCExpr * & Res , SMLoc & EndLoc ) { if ( ! parseAuthExpr ( Res , EndLoc ) ) return false ; return getParser ( ) . parsePrimaryExpr ( Res , EndLoc ) ; } </s>


"Basic block should contain at least a RET but is empty"

runOnMachineFunction - Emit the function body .


<s> static tree aarch64_fold_builtin ( tree fndecl , int nargs , tree * args , bool ) { unsigned int code = DECL_MD_FUNCTION_CODE ( fndecl ) ; unsigned int subcode = code >> AARCH64_BUILTIN_SHIFT ; tree type = TREE_TYPE ( TREE_TYPE ( fndecl ) ) ; switch ( code & AARCH64_BUILTIN_CLASS ) { case AARCH64_BUILTIN_GENERAL : return aarch64_general_fold_builtin ( subcode , type , nargs , args ) ; case AARCH64_BUILTIN_SVE : return NULL_TREE ; } gcc_unreachable ( ) ; } </s>


<s>
bool
SIOptimizeVGPRLiveRange
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
const
GCNSubtarget
&
ST
=
MF
.
getSubtarget
<
GCNSubtarget
>
(
)
;
TII
=
ST
.
getInstrInfo
(
)
;
TRI
=
&
TII
->
getRegisterInfo
(
)
;
MDT
=
&
getAnalysis
<
MachineDominatorTree
>
(
)
;
Loops
=
&
getAnalysis
<
MachineLoopInfo
>
(
)
;
LV
=
&
getAnalysis
<
LiveVariables
>
(
)
;
MRI
=
&
MF
.
getRegInfo
(
)
;
if
(
skipFunction
(
MF
.
getFunction
(
)
)
)
return
false
;
bool
MadeChange
=
false
;
for
(
MachineBasicBlock
&
MBB
:
MF
)
{
for
(
auto
&
MI
:
MBB
.
terminators
(
)
)
{
if
(
MI
.
getOpcode
(
)
==
AMDGPU
::
SI_IF
)
{
MachineBasicBlock
*
IfTarget
=
MI
.
getOperand
(
2
)
.
getMBB
(
)
;
auto
*
Endif
=
getElseTarget
(
IfTarget
)
;
if
(
!
Endif
)
continue
;
SmallSetVector
<
MachineBasicBlock
*
,
16
>
ElseBlocks
;
SmallVector
<
Register
>
CandidateRegs
;
LLVM_DEBUG
(
dbgs
(
)
<<
"Checking IF-ELSE-ENDIF: "
<<
printMBBReference
(
MBB
)
<<
' '
<<
printMBBReference
(
*
IfTarget
)
<<
' '
<<
printMBBReference
(
*
Endif
)
<<
'\n'
)
;
collectElseRegionBlocks
(
IfTarget
,
Endif
,
ElseBlocks
)
;
collectCandidateRegisters
(
&
MBB
,
IfTarget
,
Endif
,
ElseBlocks
,
CandidateRegs
)
;
MadeChange
|=
!
CandidateRegs
.
empty
(
)
;
for
(
auto
Reg
:
CandidateRegs
)
optimizeLiveRange
(
Reg
,
&
MBB
,
IfTarget
,
Endif
,
ElseBlocks
)
;
}
else
if
(
MI
.
getOpcode
(
)
==
AMDGPU
::
SI_WATERFALL_LOOP
)
{
auto
*
LoopHeader
=
MI
.
getOperand
(
0
)
.
getMBB
(
)
;
auto
*
LoopEnd
=
&
MBB
;
LLVM_DEBUG
(
dbgs
(
)
<<
"Checking Waterfall loop: "
<<
printMBBReference
(
*
LoopHeader
)
<<
'\n'
)
;
SmallSetVector
<
Register
,
16
>
CandidateRegs
;
SmallVector
<
MachineInstr
*
,
16
>
Instructions
;
SmallSetVector
<
MachineBasicBlock
*
,
2
>
Blocks
;
collectWaterfallCandidateRegisters
(
LoopHeader
,
LoopEnd
,
CandidateRegs
,
Blocks
,
Instructions
)
;
MadeChange
|=
!
CandidateRegs
.
empty
(
)
;
for
(
auto
Reg
:
CandidateRegs
)
optimizeWaterfallLiveRange
(
Reg
,
LoopHeader
,
Blocks
,
Instructions
)
;
}
}
}
return
MadeChange
;
}
</s>


<s> static bool rs6000_cannot_copy_insn_p ( rtx_insn * insn ) { return recog_memoized ( insn ) >= 0 && get_attr_cannot_copy ( insn ) ; } </s>

Return true if INSN should not be copied .


<s> void aarch64_gen_atomic_cas ( rtx rval , rtx mem , rtx expected , rtx desired , rtx model ) { rtx ( * gen ) ( rtx , rtx , rtx , rtx ) ; machine_mode mode ; mode = GET_MODE ( mem ) ; switch ( mode ) { case QImode : gen = gen_aarch64_atomic_casqi ; break ; case HImode : gen = gen_aarch64_atomic_cashi ; break ; case SImode : gen = gen_aarch64_atomic_cassi ; break ; case DImode : gen = gen_aarch64_atomic_casdi ; break ; default : gcc_unreachable ( ) ; } emit_insn ( gen_rtx_SET ( rval , expected ) ) ; emit_insn ( gen ( rval , mem , desired , model ) ) ; aarch64_gen_compare_reg ( EQ , rval , expected ) ; } </s>

Emit an atomic compare-and-swap operation . RVAL is the destination register for the data in memory . EXPECTED is the value expected to be in memory . DESIRED is the value to store to memory . MEM is the memory location . MODEL is the memory ordering to use .


<s> bool X86IndirectBranchTrackingPass :: runOnMachineFunction ( MachineFunction & MF ) { const X86Subtarget & SubTarget = MF . getSubtarget < X86Subtarget > ( ) ; Metadata * isCFProtectionSupported = MF . getMMI ( ) . getModule ( ) -> getModuleFlag ( "cf-protection-branch" ) ; const X86TargetMachine * TM = static_cast < const X86TargetMachine * > ( & MF . getTarget ( ) ) ; bool isJITwithCET = TM -> isJIT ( ) ; bool isJITwithCET = false ; if ( ! isCFProtectionSupported && ! IndirectBranchTracking && ! isJITwithCET ) return false ; bool Changed = false ; TII = SubTarget . getInstrInfo ( ) ; EndbrOpcode = SubTarget . is64Bit ( ) ? X86 :: ENDBR64 : X86 :: ENDBR32 ; if ( ( TM -> getCodeModel ( ) == CodeModel :: Large || MF . getFunction ( ) . hasAddressTaken ( ) || ! MF . getFunction ( ) . hasLocalLinkage ( ) ) && ! MF . getFunction ( ) . doesNoCfCheck ( ) ) { auto MBB = MF . begin ( ) ; Changed |= addENDBR ( * MBB , MBB -> begin ( ) ) ; } for ( auto & MBB : MF ) { if ( MBB . hasAddressTaken ( ) ) Changed |= addENDBR ( MBB , MBB . begin ( ) ) ; for ( MachineBasicBlock :: iterator I = MBB . begin ( ) ; I != MBB . end ( ) ; ++ I ) { if ( I -> isCall ( ) && I -> getNumOperands ( ) > 0 && IsCallReturnTwice ( I -> getOperand ( 0 ) ) ) { Changed |= addENDBR ( MBB , std :: next ( I ) ) ; } } if ( TM -> Options . ExceptionModel == ExceptionHandling :: SjLj ) { for ( MachineBasicBlock :: iterator I = MBB . begin ( ) ; I != MBB . end ( ) ; ++ I ) { if ( MBB . isEHPad ( ) ) { if ( I -> isDebugInstr ( ) ) continue ; Changed |= addENDBR ( MBB , I ) ; break ; } else if ( I -> isEHLabel ( ) ) { MCSymbol * Sym = I -> getOperand ( 0 ) . getMCSymbol ( ) ; if ( ! MF . hasCallSiteLandingPad ( Sym ) ) continue ; Changed |= addENDBR ( MBB , std :: next ( I ) ) ; break ; } } } else if ( MBB . isEHPad ( ) ) { for ( MachineBasicBlock :: iterator I = MBB . begin ( ) ; I != MBB . end ( ) ; ++ I ) { if ( ! I -> isEHLabel ( ) ) continue ; Changed |= addENDBR ( MBB , std :: next ( I ) ) ; break ; } } } return Changed ; } </s>


<s> static void frv_conditional_register_usage ( void ) { int i ; for ( i = GPR_FIRST + NUM_GPRS ; i <= GPR_LAST ; i ++ ) fixed_regs [ i ] = call_used_regs [ i ] = 1 ; for ( i = FPR_FIRST + NUM_FPRS ; i <= FPR_LAST ; i ++ ) fixed_regs [ i ] = call_used_regs [ i ] = 1 ; fixed_regs [ ICC_TEMP ] = call_used_regs [ ICC_TEMP ] = 1 ; fixed_regs [ ICR_TEMP ] = call_used_regs [ ICR_TEMP ] = 1 ; if ( TARGET_FIXED_CC ) { fixed_regs [ ICC_FIRST ] = call_used_regs [ ICC_FIRST ] = 1 ; fixed_regs [ FCC_FIRST ] = call_used_regs [ FCC_FIRST ] = 1 ; fixed_regs [ ICR_FIRST ] = call_used_regs [ ICR_FIRST ] = 1 ; fixed_regs [ FCR_FIRST ] = call_used_regs [ FCR_FIRST ] = 1 ; } if ( TARGET_FDPIC ) fixed_regs [ GPR_FIRST + 16 ] = fixed_regs [ GPR_FIRST + 17 ] = call_used_regs [ GPR_FIRST + 16 ] = call_used_regs [ GPR_FIRST + 17 ] = 0 ; if ( g_switch_value == 0 && ! flag_pic ) fixed_regs [ SDA_BASE_REG ] = call_used_regs [ SDA_BASE_REG ] = 0 ; if ( ! flag_pic ) fixed_regs [ PIC_REGNO ] = call_used_regs [ PIC_REGNO ] = 0 ; } </s>

Zero or more C statements that may conditionally modify two variables ` fixed_regs ' and ` call_used_regs ' ( both of type ` char [ ] ' ) after they have been initialized from the two preceding macros . This is necessary in case the fixed or call-clobbered registers depend on target flags . You need not define this macro if it has no work to do . If the usage of an entire class of registers depends on the target flags , you may indicate this to GCC by using this macro to modify ` fixed_regs ' and ` call_used_regs ' to 1 for each of the registers in the classes which should not be used by GCC . Also define the macro ` REG_CLASS_FROM_LETTER ' to return ` NO_REGS ' if it is called with a letter for a class that should n't be used . ( However , if this class is not included in ` GENERAL_REGS ' and all of the insn patterns whose constraints permit this class are controlled by target switches , then GCC will automatically avoid using these registers when the target switches are opposed to them . )


<s> bool MipsTargetLowering :: CanLowerReturn ( CallingConv :: ID CallConv , MachineFunction & MF , bool IsVarArg , const SmallVectorImpl < ISD :: OutputArg > & Outs , LLVMContext & Context ) const { SmallVector < CCValAssign , 16 > RVLocs ; CCState CCInfo ( CallConv , IsVarArg , MF , getTargetMachine ( ) , RVLocs , Context ) ; return CCInfo . CheckReturn ( Outs , RetCC_Mips ) ; } </s>

This hook should be implemented to check whether the return values described by the Outs array can fit into the return registers .


"Can't load this register from stack slot"

Load the specified register of the given register class from the specified stack frame index .


<s> static void frv_output_const_unspec ( FILE * stream , const struct frv_unspec * unspec ) { fprintf ( stream , "#%s(" , unspec_got_name ( unspec -> reloc ) ) ; output_addr_const ( stream , plus_constant ( unspec -> symbol , unspec -> offset ) ) ; fputs ( ")" , stream ) ; } </s>

Write the assembler syntax for UNSPEC to STREAM . Note that any offset is added inside the relocation operator .


<s>
unsigned
P2MCCodeEmitter
::
getMachineOpValue
(
const
MCInst
&
MI
,
const
MCOperand
&
MO
,
SmallVectorImpl
<
MCFixup
>
&
Fixups
,
const
MCSubtargetInfo
&
STI
)
const
{
if
(
MO
.
isReg
(
)
)
{
unsigned
Reg
=
MO
.
getReg
(
)
;
unsigned
RegNo
=
Ctx
.
getRegisterInfo
(
)
->
getEncodingValue
(
Reg
)
;
LLVM_DEBUG
(
errs
(
)
<<
"-- register number is "
<<
RegNo
<<
" for reg "
<<
Reg
<<
"\n"
)
;
return
RegNo
;
}
else
if
(
MO
.
isImm
(
)
)
{
LLVM_DEBUG
(
errs
(
)
<<
"-- immediate operand is "
<<
MO
.
getImm
(
)
<<
"\n"
)
;
return
static_cast
<
unsigned
>
(
MO
.
getImm
(
)
)
;
}
LLVM_DEBUG
(
errs
(
)
<<
" -- operand is an expression\n"
)
;
assert
(
MO
.
isExpr
(
)
)
;
return
getExprOpValue
(
MI
,
MO
.
getExpr
(
)
,
Fixups
,
STI
)
;
}
</s>

getMachineOpValue - Return binary encoding of operand .

P2
P2
"-- register number is "
" for reg "
"\n"
"-- immediate operand is "
"\n"
" -- operand is an expression\n"


<s> bool SystemZTargetLowering :: allowsMisalignedMemoryAccesses ( EVT VT , unsigned , unsigned , bool * Fast ) const { if ( Fast ) * Fast = true ; return true ; } </s>

Returns true if the target allows unaligned memory accesses of the specified type .


"Unknown opcode to check as cheap as a move!"

Return true if the instruction is as cheap as a move instruction .


<s> bool HexagonInstrInfo :: isPredicable ( const MachineInstr & MI ) const { return MI . getDesc ( ) . isPredicable ( ) ; } </s>

Return true if the specified instruction can be predicated .


<s> static rtx mips_gen_const_int_vector_shuffle ( machine_mode mode , int val ) { int nunits = GET_MODE_NUNITS ( mode ) ; int nsets = nunits / 4 ; rtx elts [ MAX_VECT_LEN ] ; int set = 0 ; int i , j ; for ( j = 0 ; j < nsets ; j ++ , set = 4 * j ) for ( i = 0 ; i < 4 ; i ++ ) elts [ set + i ] = GEN_INT ( set + ( ( val >> ( 2 * i ) ) & 0x3 ) ) ; return gen_rtx_PARALLEL ( VOIDmode , gen_rtvec_v ( nunits , elts ) ) ; } </s>

Return a vector of repeated 4-element sets generated from immediate VAL in mode MODE .


<s> int v850_interrupt_function_p ( tree func ) { tree a ; int ret = 0 ; if ( v850_interrupt_cache_p ) return v850_interrupt_p ; if ( TREE_CODE ( func ) != FUNCTION_DECL ) return 0 ; a = lookup_attribute ( "interrupt_handler" , DECL_ATTRIBUTES ( func ) ) ; if ( a != NULL_TREE ) ret = 1 ; else { a = lookup_attribute ( "interrupt" , DECL_ATTRIBUTES ( func ) ) ; ret = a != NULL_TREE ; } if ( reload_completed | reload_in_progress ) v850_interrupt_p = ret ; return ret ; } </s>

Return nonzero if FUNC is an interrupt function as specified by the `` interrupt '' attribute .


<s>
SDValue
mprocTargetLowering
::
LowerOperation
(
SDValue
Op
,
SelectionDAG
&
DAG
)
const
{
switch
(
Op
.
getOpcode
(
)
)
{
default
:
llvm_unreachable
(
"unimplemented operand"
)
;
}
}
</s>

LowerOperation - Provide custom lowering hooks for some operations .


<s> bool SILowerControlFlow :: runOnMachineFunction ( MachineFunction & MF ) { const GCNSubtarget & ST = MF . getSubtarget < GCNSubtarget > ( ) ; TII = ST . getInstrInfo ( ) ; TRI = & TII -> getRegisterInfo ( ) ; LIS = getAnalysisIfAvailable < LiveIntervals > ( ) ; MRI = & MF . getRegInfo ( ) ; BoolRC = TRI -> getBoolRC ( ) ; InsertKillCleanups = MF . getFunction ( ) . getCallingConv ( ) == CallingConv :: AMDGPU_PS ; if ( ST . isWave32 ( ) ) { AndOpc = AMDGPU :: S_AND_B32 ; OrOpc = AMDGPU :: S_OR_B32 ; XorOpc = AMDGPU :: S_XOR_B32 ; MovTermOpc = AMDGPU :: S_MOV_B32_term ; Andn2TermOpc = AMDGPU :: S_ANDN2_B32_term ; XorTermrOpc = AMDGPU :: S_XOR_B32_term ; OrSaveExecOpc = AMDGPU :: S_OR_SAVEEXEC_B32 ; Exec = AMDGPU :: EXEC_LO ; } else { AndOpc = AMDGPU :: S_AND_B64 ; OrOpc = AMDGPU :: S_OR_B64 ; XorOpc = AMDGPU :: S_XOR_B64 ; MovTermOpc = AMDGPU :: S_MOV_B64_term ; Andn2TermOpc = AMDGPU :: S_ANDN2_B64_term ; XorTermrOpc = AMDGPU :: S_XOR_B64_term ; OrSaveExecOpc = AMDGPU :: S_OR_SAVEEXEC_B64 ; Exec = AMDGPU :: EXEC ; } SmallVector < MachineInstr * , 32 > Worklist ; MachineFunction :: iterator NextBB ; for ( MachineFunction :: iterator BI = MF . begin ( ) , BE = MF . end ( ) ; BI != BE ; BI = NextBB ) { NextBB = std :: next ( BI ) ; MachineBasicBlock & MBB = * BI ; MachineBasicBlock :: iterator I , Next ; for ( I = MBB . begin ( ) ; I != MBB . end ( ) ; I = Next ) { Next = std :: next ( I ) ; MachineInstr & MI = * I ; switch ( MI . getOpcode ( ) ) { case AMDGPU :: SI_IF : process ( MI ) ; break ; case AMDGPU :: SI_ELSE : case AMDGPU :: SI_IF_BREAK : case AMDGPU :: SI_LOOP : case AMDGPU :: SI_END_CF : if ( InsertKillCleanups ) Worklist . push_back ( & MI ) ; else process ( MI ) ; break ; default : break ; } } } for ( MachineInstr * MI : Worklist ) process ( * MI ) ; optimizeEndCf ( ) ; LoweredEndCf . clear ( ) ; LoweredIf . clear ( ) ; NeedsKillCleanup . clear ( ) ; return true ; } </s>


<s> static void ix86_check_avx_upper_stores ( rtx dest , const_rtx , void * data ) { if ( ix86_check_avx_upper_register ( dest ) ) { bool * used = ( bool * ) data ; * used = true ; } } </s>

Check if a 256bit or 512bit AVX register is referenced in stores .


<s> bool SystemZMCAsmBackend :: writeNopData ( uint64_t Count , MCObjectWriter * OW ) const { for ( uint64_t I = 0 ; I != Count ; ++ I ) OW -> Write8 ( 7 ) ; return true ; } </s>

Write an ( optimal ) nop sequence of Count bytes to the given output .


<s> void m32c_register_pragmas ( void ) { c_register_pragma ( "GCC" , "memregs" , m32c_pragma_memregs ) ; c_register_pragma ( NULL , "ADDRESS" , m32c_pragma_address ) ; c_register_pragma ( NULL , "address" , m32c_pragma_address ) ; if ( TARGET_A16 ) c_register_addr_space ( "__far" , ADDR_SPACE_FAR ) ; else c_register_addr_space ( "__far" , ADDR_SPACE_GENERIC ) ; } </s>


Emit MSPABI and GNU object attributes . Tags and values for MSPABI attributes are : OFBA_MSPABI_Tag_ISA 4 MSP430 1 MSP430X 2 OFBA_MSPABI_Tag_Code_Model 6 Small 1 Large 2 OFBA_MSPABI_Tag_Data_Model 8 Small 1 Large 2 Restricted 3 ( Unused by GNU ) OFBA_MSPABI_Tag_enum_size 10 ( Unused by GNU ) Note that Code_Model and Data_Model are always equal for GNU . We define a new .gnu_attribute to keep track of the data region used . Tag_GNU_MSP430_Data_Region 4 LOWER 1 ANY 2 See binutils-gdb/include/elf/msp430.h for the full details .


<s> uint64_t MipsMCCodeEmitter :: getMachineOpValue ( const MCInst & MI , const MCOperand & MO , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { if ( MO . isReg ( ) ) { unsigned Reg = MO . getReg ( ) ; unsigned RegNo = Ctx . getRegisterInfo ( ) -> getEncodingValue ( Reg ) ; return RegNo ; } else if ( MO . isImm ( ) ) { return static_cast < uint64_t > ( MO . getImm ( ) ) ; } else if ( MO . isFPImm ( ) ) { return static_cast < uint64_t > ( APFloat ( MO . getFPImm ( ) ) . bitcastToAPInt ( ) . getHiBits ( 32 ) . getLimitedValue ( ) ) ; } assert ( MO . isExpr ( ) ) ; return getExprOpValue ( MO . getExpr ( ) , Fixups , STI ) ; } </s>


<s> static ArgDescriptor createRegister ( unsigned Reg ) { return ArgDescriptor ( Reg , false , true ) ; } </s>

.cfi_register Previous value of Register1 is saved in register Register2 .


"instruction use requires an option to be enabled"

MatchAndEmitInstruction - Recognize a series of operands of a parsed instruction as an actual MCInst and emit it to the specified MCStreamer .


<s> static bool avr_address_tiny_absdata_p ( rtx x , machine_mode mode ) { if ( CONST == GET_CODE ( x ) ) x = XEXP ( XEXP ( x , 0 ) , 0 ) ; if ( SYMBOL_REF_P ( x ) ) return SYMBOL_REF_FLAGS ( x ) & AVR_SYMBOL_FLAG_TINY_ABSDATA ; if ( CONST_INT_P ( x ) && IN_RANGE ( INTVAL ( x ) , 0 , 0xc0 - GET_MODE_SIZE ( mode ) ) ) return true ; return false ; } </s>

Return true if rtx X is a CONST_INT , CONST or SYMBOL_REF address with the ` absdata ' variable attribute , i.e . respective data can be read / written by LDS / STS instruction . This is used only for AVR_TINY .


<s> static int unspec_prof_htab_eq ( const void * x , const void * y ) { const_rtx u0 = ( const_rtx ) x ; const_rtx u1 = ( const_rtx ) y ; const_rtx s01 = XVECEXP ( u0 , 0 , 1 ) ; const_rtx s11 = XVECEXP ( u1 , 0 , 1 ) ; return ( ! strcmp ( XSTR ( XVECEXP ( u0 , 0 , 0 ) , 0 ) , XSTR ( XVECEXP ( u1 , 0 , 0 ) , 0 ) ) && rtx_equal_p ( s01 , s11 ) ) ; } </s>

Equality function for UNSPEC_PROF htab . Two pieces of UNSPEC_PROF rtl shall refer to the same counter if both caller name and callee rtl are identical .


<s> Optional < Instruction * > AArch64TTIImpl :: instCombineIntrinsic ( InstCombiner & IC , IntrinsicInst & II ) const { Intrinsic :: ID IID = II . getIntrinsicID ( ) ; switch ( IID ) { default : break ; case Intrinsic :: aarch64_sve_convert_from_svbool : return instCombineConvertFromSVBool ( IC , II ) ; case Intrinsic :: aarch64_sve_dup : return instCombineSVEDup ( IC , II ) ; case Intrinsic :: aarch64_sve_rdffr : return instCombineRDFFR ( IC , II ) ; case Intrinsic :: aarch64_sve_lasta : case Intrinsic :: aarch64_sve_lastb : return instCombineSVELast ( IC , II ) ; } return None ; } </s>

Targets can implement their own combinations for target-specific intrinsics .


<s> static bool timode_scalar_to_vector_candidate_p ( rtx_insn * insn ) { rtx def_set = pseudo_reg_set ( insn ) ; if ( ! def_set ) return false ; rtx src = SET_SRC ( def_set ) ; rtx dst = SET_DEST ( def_set ) ; if ( GET_CODE ( src ) == COMPARE ) return convertible_comparison_p ( insn , TImode ) ; if ( GET_MODE ( dst ) != TImode || ( GET_MODE ( src ) != TImode && ! CONST_SCALAR_INT_P ( src ) ) ) return false ; if ( ! REG_P ( dst ) && ! MEM_P ( dst ) ) return false ; if ( MEM_P ( dst ) && misaligned_operand ( dst , TImode ) && ! TARGET_SSE_UNALIGNED_STORE_OPTIMAL ) return false ; if ( REG_P ( dst ) && ! single_def_chain_p ( dst ) ) return false ; switch ( GET_CODE ( src ) ) { case REG : return single_def_chain_p ( src ) ; case CONST_WIDE_INT : return true ; case CONST_INT : return standard_sse_constant_p ( src , TImode ) ; case MEM : return ( REG_P ( dst ) && ( ! misaligned_operand ( src , TImode ) || TARGET_SSE_UNALIGNED_LOAD_OPTIMAL ) ) ; case AND : if ( ! MEM_P ( dst ) && GET_CODE ( XEXP ( src , 0 ) ) == NOT && REG_P ( XEXP ( XEXP ( src , 0 ) , 0 ) ) && ( REG_P ( XEXP ( src , 1 ) ) || CONST_SCALAR_INT_P ( XEXP ( src , 1 ) ) || timode_mem_p ( XEXP ( src , 1 ) ) ) ) return true ; return REG_P ( XEXP ( src , 0 ) ) && ( REG_P ( XEXP ( src , 1 ) ) || CONST_SCALAR_INT_P ( XEXP ( src , 1 ) ) || timode_mem_p ( XEXP ( src , 1 ) ) ) ; case IOR : case XOR : return REG_P ( XEXP ( src , 0 ) ) && ( REG_P ( XEXP ( src , 1 ) ) || CONST_SCALAR_INT_P ( XEXP ( src , 1 ) ) || timode_mem_p ( XEXP ( src , 1 ) ) ) ; case NOT : return REG_P ( XEXP ( src , 0 ) ) || timode_mem_p ( XEXP ( src , 0 ) ) ; case ASHIFT : case LSHIFTRT : case ASHIFTRT : case ROTATERT : case ROTATE : return REG_P ( XEXP ( src , 0 ) ) && CONST_INT_P ( XEXP ( src , 1 ) ) && ( INTVAL ( XEXP ( src , 1 ) ) & ~ 0x7f ) == 0 ; default : return false ; } } </s>

The TImode version of scalar_to_vector_candidate_p .


<s> void MipsAsmPrinter :: emitInlineAsmStart ( ) const { MipsTargetStreamer & TS = getTargetStreamer ( ) ; TS . emitDirectiveSetPush ( ) ; TS . emitDirectiveSetAt ( ) ; TS . emitDirectiveSetMacro ( ) ; TS . emitDirectiveSetReorder ( ) ; OutStreamer -> AddBlankLine ( ) ; } </s>

Let the target do anything it needs to do before emitting inlineasm .


<s> bool X86PassConfig :: addILPOpts ( ) { addPass ( & EarlyIfConverterID ) ; if ( EnableMachineCombinerPass ) addPass ( & MachineCombinerID ) ; addPass ( createX86CmovConverterPass ( ) ) ; return true ; } </s>

Add passes that optimize instruction level parallelism for out-of-order targets .