<s> bool FixAllFDIVSQRT :: runOnMachineFunction ( MachineFunction & MF ) { Subtarget = & MF . getSubtarget < SparcSubtarget > ( ) ; const TargetInstrInfo & TII = * Subtarget -> getInstrInfo ( ) ; DebugLoc DL = DebugLoc ( ) ; bool Modified = false ; for ( auto MFI = MF . begin ( ) , E = MF . end ( ) ; MFI != E ; ++ MFI ) { MachineBasicBlock & MBB = * MFI ; for ( auto MBBI = MBB . begin ( ) , E = MBB . end ( ) ; MBBI != E ; ++ MBBI ) { MachineInstr & MI = * MBBI ; unsigned Opcode = MI . getOpcode ( ) ; if ( MI . isInlineAsm ( ) ) { std :: string AsmString ( MI . getOperand ( InlineAsm :: MIOp_AsmString ) . getSymbolName ( ) ) ; std :: string FSQRTDOpCode ( "fsqrtd" ) ; std :: string FDIVDOpCode ( "fdivd" ) ; std :: transform ( AsmString . begin ( ) , AsmString . end ( ) , AsmString . begin ( ) , :: tolower ) ; if ( AsmString . find ( FSQRTDOpCode ) == 0 ) { Opcode = SP :: FSQRTD ; } else if ( AsmString . find ( FDIVDOpCode ) == 0 ) { Opcode = SP :: FDIVD ; } } if ( Opcode == SP :: FSQRTD || Opcode == SP :: FDIVD ) { for ( int InsertedCount = 0 ; InsertedCount < 5 ; InsertedCount ++ ) BuildMI ( MBB , MBBI , DL , TII . get ( SP :: NOP ) ) ; MachineBasicBlock :: iterator NMBBI = std :: next ( MBBI ) ; for ( int InsertedCount = 0 ; InsertedCount < 28 ; InsertedCount ++ ) BuildMI ( MBB , NMBBI , DL , TII . get ( SP :: NOP ) ) ; Modified = true ; } } } return Modified ; } </s>

runOnMachineFunction - Emit the function body .


<s>
static
void
frv_expand_builtin_va_start
(
tree
valist
,
rtx
nextarg
)
{
tree
t
;
int
num
=
crtl
->
args
.
info
FIRST_ARG_REGNUM
FRV_NUM_ARG_REGS
;
nextarg
=
gen_rtx_PLUS
(
Pmode
,
virtual_incoming_args_rtx
,
GEN_INT
(
UNITS_PER_WORD
*
num
)
)
;
if
(
TARGET_DEBUG_ARG
)
{
fprintf
(
stderr
,
"va_start: args_info = %d, num = %d\n"
,
crtl
->
args
.
info
,
num
)
;
debug_rtx
(
nextarg
)
;
}
t
=
build2
(
MODIFY_EXPR
,
TREE_TYPE
(
valist
)
,
valist
,
fold_convert
(
TREE_TYPE
(
valist
)
,
make_tree
(
sizetype
,
nextarg
)
)
)
;
TREE_SIDE_EFFECTS
(
t
)
=
1
;
expand_expr
(
t
,
const0_rtx
,
VOIDmode
,
EXPAND_NORMAL
)
;
}
</s>

Expand __builtin_va_start to do the va_start macro .

frv
"va_start: args_info = %d, num = %d\n"
1


<s>
SDValue
MSP430TargetLowering
::
LowerOperation
(
SDValue
Op
,
SelectionDAG
&
DAG
)
{
switch
(
Op
.
getOpcode
(
)
)
{
case
ISD
::
SHL
:
case
ISD
::
SRL
:
case
ISD
::
SRA
:
return
LowerShifts
(
Op
,
DAG
)
;
case
ISD
::
GlobalAddress
:
return
LowerGlobalAddress
(
Op
,
DAG
)
;
case
ISD
::
ExternalSymbol
:
return
LowerExternalSymbol
(
Op
,
DAG
)
;
case
ISD
::
BR_CC
:
return
LowerBR_CC
(
Op
,
DAG
)
;
case
ISD
::
SELECT_CC
:
return
LowerSELECT_CC
(
Op
,
DAG
)
;
case
ISD
::
SIGN_EXTEND
:
return
LowerSIGN_EXTEND
(
Op
,
DAG
)
;
default
:
llvm_unreachable
(
"unimplemented operand"
)
;
return
SDValue
(
)
;
}
}
</s>

LowerOperation - Provide custom lowering hooks for some operations .


<s> bool X86TargetLowering :: isTypeDesirableForOp ( unsigned Opc , EVT VT ) const { if ( ! isTypeLegal ( VT ) ) return false ; if ( Opc == ISD :: SHL && VT . isVector ( ) && VT . getVectorElementType ( ) == MVT :: i8 ) return false ; if ( VT != MVT :: i16 ) return true ; switch ( Opc ) { default : return true ; case ISD :: LOAD : case ISD :: SIGN_EXTEND : case ISD :: ZERO_EXTEND : case ISD :: ANY_EXTEND : case ISD :: SHL : case ISD :: SRL : case ISD :: SUB : case ISD :: ADD : case ISD :: MUL : case ISD :: AND : case ISD :: OR : case ISD :: XOR : return false ; } } </s>

Return true if the target has native support for the specified value type and it is 'desirable ' to use the type for the given node type .


<s>
DecodeStatus
AArch64Disassembler
::
getInstruction
(
MCInst
&
MI
,
uint64_t
&
Size
,
ArrayRef
<
uint8_t
>
Bytes
,
uint64_t
Address
,
raw_ostream
&
CS
)
const
{
CommentStream
=
&
CS
;
Size
=
0
;
if
(
Bytes
.
size
(
)
<
4
)
return
Fail
;
Size
=
4
;
uint32_t
Insn
=
(
Bytes
[
3
]
<<
24
)
|
(
Bytes
[
2
]
<<
16
)
|
(
Bytes
[
1
]
<<
8
)
|
(
Bytes
[
0
]
<<
0
)
;
const
uint8_t
*
Tables
[
]
=
{
DecoderTable32
,
DecoderTableFallback32
}
;
for
(
auto
Table
:
Tables
)
{
DecodeStatus
Result
=
decodeInstruction
(
Table
,
MI
,
Insn
,
Address
,
this
,
STI
)
;
switch
(
MI
.
getOpcode
(
)
)
{
default
:
break
;
case
AArch64
::
LDR_ZA
:
case
AArch64
::
STR_ZA
:
{
MI
.
insert
(
MI
.
begin
(
)
,
MCOperand
::
createReg
(
AArch64
::
ZA
)
)
;
const
MCOperand
&
Imm4Op
=
MI
.
getOperand
(
2
)
;
assert
(
Imm4Op
.
isImm
(
)
&&
"Unexpected operand type!"
)
;
MI
.
addOperand
(
Imm4Op
)
;
break
;
}
case
AArch64
::
LD1_MXIPXX_H_B
:
case
AArch64
::
LD1_MXIPXX_V_B
:
case
AArch64
::
ST1_MXIPXX_H_B
:
case
AArch64
::
ST1_MXIPXX_V_B
:
case
AArch64
::
INSERT_MXIPZ_H_B
:
case
AArch64
::
INSERT_MXIPZ_V_B
:
MI
.
insert
(
MI
.
begin
(
)
,
MCOperand
::
createReg
(
AArch64
::
ZAB0
)
)
;
break
;
case
AArch64
::
EXTRACT_ZPMXI_H_B
:
case
AArch64
::
EXTRACT_ZPMXI_V_B
:
MI
.
insert
(
MI
.
begin
(
)
+
2
,
MCOperand
::
createReg
(
AArch64
::
ZAB0
)
)
;
break
;
}
if
(
Result
!=
MCDisassembler
::
Fail
)
return
Result
;
}
return
MCDisassembler
::
Fail
;
}
</s>

Returns the disassembly of a single instruction .


<s> unsigned CFGStructurizer < PassT > :: getLoopDepth ( LoopT * loopRep ) { return loopRep ? loopRep -> getLoopDepth ( ) : 0 ; } </s>

Return the loop nesting level of the specified block .


<s> bool HexagonTargetLowering :: getTgtMemIntrinsic ( IntrinsicInfo & Info , const CallInst & I , MachineFunction & MF , unsigned Intrinsic ) const { switch ( Intrinsic ) { case Intrinsic :: hexagon_L2_loadrd_pbr : case Intrinsic :: hexagon_L2_loadri_pbr : case Intrinsic :: hexagon_L2_loadrh_pbr : case Intrinsic :: hexagon_L2_loadruh_pbr : case Intrinsic :: hexagon_L2_loadrb_pbr : case Intrinsic :: hexagon_L2_loadrub_pbr : { Info . opc = ISD :: INTRINSIC_W_CHAIN ; auto & DL = I . getCalledFunction ( ) -> getParent ( ) -> getDataLayout ( ) ; auto & Cont = I . getCalledFunction ( ) -> getParent ( ) -> getContext ( ) ; Type * ElTy = I . getCalledFunction ( ) -> getReturnType ( ) -> getStructElementType ( 0 ) ; Info . memVT = MVT :: getVT ( ElTy ) ; llvm :: Value * BasePtrVal = I . getOperand ( 0 ) ; Info . ptrVal = getUnderLyingObjectForBrevLdIntr ( BasePtrVal ) ; Info . offset = 0 ; Info . align = MaybeAlign ( DL . getABITypeAlignment ( Info . memVT . getTypeForEVT ( Cont ) ) ) ; Info . flags = MachineMemOperand :: MOLoad ; return true ; } case Intrinsic :: hexagon_V6_vgathermw : case Intrinsic :: hexagon_V6_vgathermw_128B : case Intrinsic :: hexagon_V6_vgathermh : case Intrinsic :: hexagon_V6_vgathermh_128B : case Intrinsic :: hexagon_V6_vgathermhw : case Intrinsic :: hexagon_V6_vgathermhw_128B : case Intrinsic :: hexagon_V6_vgathermwq : case Intrinsic :: hexagon_V6_vgathermwq_128B : case Intrinsic :: hexagon_V6_vgathermhq : case Intrinsic :: hexagon_V6_vgathermhq_128B : case Intrinsic :: hexagon_V6_vgathermhwq : case Intrinsic :: hexagon_V6_vgathermhwq_128B : { const Module & M = * I . getParent ( ) -> getParent ( ) -> getParent ( ) ; Info . opc = ISD :: INTRINSIC_W_CHAIN ; Type * VecTy = I . getArgOperand ( 1 ) -> getType ( ) ; Info . memVT = MVT :: getVT ( VecTy ) ; Info . ptrVal = I . getArgOperand ( 0 ) ; Info . offset = 0 ; Info . align = MaybeAlign ( M . getDataLayout ( ) . getTypeAllocSizeInBits ( VecTy ) / 8 ) ; Info . flags = MachineMemOperand :: MOLoad | MachineMemOperand :: MOStore | MachineMemOperand :: MOVolatile ; return true ; } default : break ; } return false ; } </s>

Given an intrinsic , checks if on the target the intrinsic will need to map to a MemIntrinsicNode ( touches memory ) .


<s> bool ARMTargetLowering :: shouldExpandAtomicCmpXchgInIR ( AtomicCmpXchgInst * AI ) const { bool hasAtomicCmpXchg = ! Subtarget -> isThumb ( ) || Subtarget -> hasV8MBaselineOps ( ) ; return getTargetMachine ( ) . getOptLevel ( ) != 0 && hasAtomicCmpXchg ; } </s>

Returns how the given atomic cmpxchg should be expanded by the IR-level AtomicExpand pass .


<s> static void rs6000_emit_prologue_components ( sbitmap components ) { rs6000_stack_t * info = rs6000_stack_info ( ) ; rtx ptr_reg = gen_rtx_REG ( Pmode , frame_pointer_needed ? HARD_FRAME_POINTER_REGNUM : STACK_POINTER_REGNUM ) ; machine_mode reg_mode = Pmode ; int reg_size = TARGET_32BIT ? 4 : 8 ; machine_mode fp_reg_mode = ( TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT ) ? DFmode : SFmode ; int fp_reg_size = 8 ; if ( bitmap_bit_p ( components , 0 ) ) { rtx reg = gen_rtx_REG ( reg_mode , 0 ) ; rtx_insn * insn = emit_move_insn ( reg , gen_rtx_REG ( reg_mode , LR_REGNO ) ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; add_reg_note ( insn , REG_CFA_REGISTER , NULL ) ; int offset = info -> lr_save_offset ; if ( info -> push_p ) offset += info -> total_size ; insn = emit_insn ( gen_frame_store ( reg , ptr_reg , offset ) ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; rtx lr = gen_rtx_REG ( reg_mode , LR_REGNO ) ; rtx mem = copy_rtx ( SET_DEST ( single_set ( insn ) ) ) ; add_reg_note ( insn , REG_CFA_OFFSET , gen_rtx_SET ( mem , lr ) ) ; } int offset = info -> gp_save_offset ; if ( info -> push_p ) offset += info -> total_size ; for ( int i = info -> first_gp_reg_save ; i < 32 ; i ++ ) { if ( bitmap_bit_p ( components , i ) ) { rtx reg = gen_rtx_REG ( reg_mode , i ) ; rtx_insn * insn = emit_insn ( gen_frame_store ( reg , ptr_reg , offset ) ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; rtx set = copy_rtx ( single_set ( insn ) ) ; add_reg_note ( insn , REG_CFA_OFFSET , set ) ; } offset += reg_size ; } offset = info -> fp_save_offset ; if ( info -> push_p ) offset += info -> total_size ; for ( int i = info -> first_fp_reg_save ; i < 64 ; i ++ ) { if ( bitmap_bit_p ( components , i ) ) { rtx reg = gen_rtx_REG ( fp_reg_mode , i ) ; rtx_insn * insn = emit_insn ( gen_frame_store ( reg , ptr_reg , offset ) ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; rtx set = copy_rtx ( single_set ( insn ) ) ; add_reg_note ( insn , REG_CFA_OFFSET , set ) ; } offset += fp_reg_size ; } } </s>


<s> static bool rs6000_vectorize_vec_perm_const ( machine_mode vmode , rtx target , rtx op0 , rtx op1 , const vec_perm_indices & sel ) { bool testing_p = ! target ; if ( TARGET_ALTIVEC && testing_p ) return true ; if ( ( vmode == V2SFmode && TARGET_PAIRED_FLOAT ) || ( vmode == V2SImode && TARGET_SPE ) || ( ( vmode == V2DFmode || vmode == V2DImode ) && VECTOR_MEM_VSX_P ( vmode ) ) ) { if ( testing_p ) { op0 = gen_raw_REG ( vmode , LAST_VIRTUAL_REGISTER + 1 ) ; op1 = gen_raw_REG ( vmode , LAST_VIRTUAL_REGISTER + 2 ) ; } if ( rs6000_expand_vec_perm_const_1 ( target , op0 , op1 , sel [ 0 ] , sel [ 1 ] ) ) return true ; } if ( TARGET_ALTIVEC ) { if ( vmode != V16QImode ) return false ; if ( altivec_expand_vec_perm_const ( target , op0 , op1 , sel ) ) return true ; } return false ; } </s>


<s> static int get_insn_spec_code ( const_rtx insn ) { rtx pat , reg , mem ; pat = PATTERN ( insn ) ; if ( GET_CODE ( pat ) == COND_EXEC ) pat = COND_EXEC_CODE ( pat ) ; if ( GET_CODE ( pat ) != SET ) return - 1 ; reg = SET_DEST ( pat ) ; if ( ! REG_P ( reg ) ) return - 1 ; mem = SET_SRC ( pat ) ; if ( GET_CODE ( mem ) == ZERO_EXTEND ) mem = XEXP ( mem , 0 ) ; return get_spec_unspec_code ( mem ) ; } </s>

If INSN is a speculative load , return its UNSPEC code . Return -1 otherwise .


<s> rtx z8k_legitimize_address ( rtx x , rtx oldx ATTRIBUTE_UNUSED , enum machine_mode mode ATTRIBUTE_UNUSED ) { if ( TARGET_PIC ) { if ( GET_CODE ( oldx ) == SYMBOL_REF || GET_CODE ( oldx ) == LABEL_REF ) { rtx ptr = gen_reg_rtx ( Pmode ) ; emit_insn ( gen_rtx_SET ( VOIDmode , ptr , gen_rtx_LO_SUM ( pic_reg , oldx ) ) ) ; return gen_rtx_MEM ( mode , ptr ) ; } } return x ; } </s>

This hook is given an invalid memory address x for an operand of mode mode and should try to return a valid memory address . x will always be the result of a call to break_out_memory_refs , and oldx will be the operand that was given to that function to produce x . The code of the hook should not alter the substructure of x . If it transforms x into a more legitimate form , it should return the new x .


<s> const TargetRegisterClass * getPointerRegClass ( const MachineFunction & MF , unsigned Kind = 0 ) const override { return & RISCV :: GPRRegClass ; } </s>

getPointerRegClass - Returns a TargetRegisterClass used for pointer values .


<s> static int bfin_address_cost ( rtx addr ATTRIBUTE_UNUSED ) { return 1 ; } </s>

Return cost of the memory address ADDR . All addressing modes are equally cheap on the Blackfin .


<s>
static
void
adjust_concat
(
rtx_insn
*
insn
)
{
rtx
set
=
PATTERN
(
insn
)
;
rtx
concat
=
XEXP
(
set
,
1
)
;
rtx
src0
=
XEXP
(
concat
,
0
)
;
XEXP
(
concat
,
0
)
=
XEXP
(
concat
,
1
)
;
XEXP
(
concat
,
1
)
=
src0
;
INSN_CODE
(
insn
)
=
1
;
df_insn_rescan
(
insn
)
;
if
(
dump_file
)
fprintf
(
dump_file
,
"Reversing inputs for concat %d\n"
,
INSN_UID
(
insn
)
)
;
}
</s>

Given OP that contains a VEC_CONCAT operation of two doublewords , reverse the order of those inputs .


<s>
void
addExpr
(
MCInst
&
Inst
,
const
MCExpr
*
Expr
)
const
{
assert
(
Expr
&&
"Expr shouldn't be null!"
)
;
if
(
auto
*
CE
=
dyn_cast
<
MCConstantExpr
>
(
Expr
)
)
Inst
.
addOperand
(
MCOperand
::
createImm
(
CE
->
getValue
(
)
)
)
;
else
Inst
.
addOperand
(
MCOperand
::
createExpr
(
Expr
)
)
;
}
</s>


<s> bool SIPostRABundler :: runOnMachineFunction ( MachineFunction & MF ) { if ( skipFunction ( MF . getFunction ( ) ) ) return false ; TRI = MF . getSubtarget < GCNSubtarget > ( ) . getRegisterInfo ( ) ; bool Changed = false ; const uint64_t MemFlags = SIInstrFlags :: MTBUF | SIInstrFlags :: MUBUF | SIInstrFlags :: SMRD | SIInstrFlags :: DS | SIInstrFlags :: FLAT | SIInstrFlags :: MIMG ; for ( MachineBasicBlock & MBB : MF ) { MachineBasicBlock :: instr_iterator Next ; MachineBasicBlock :: instr_iterator B = MBB . instr_begin ( ) ; MachineBasicBlock :: instr_iterator E = MBB . instr_end ( ) ; for ( auto I = B ; I != E ; I = Next ) { Next = std :: next ( I ) ; const uint64_t IMemFlags = I -> getDesc ( ) . TSFlags & MemFlags ; if ( IMemFlags == 0 || I -> isBundled ( ) || ! I -> mayLoadOrStore ( ) || B -> mayLoad ( ) != I -> mayLoad ( ) || B -> mayStore ( ) != I -> mayStore ( ) || ( ( B -> getDesc ( ) . TSFlags & MemFlags ) != IMemFlags ) || isDependentLoad ( * I ) ) { if ( B != I ) { if ( std :: next ( B ) != I ) { finalizeBundle ( MBB , B , I ) ; Changed = true ; } Next = I ; } B = Next ; Defs . clear ( ) ; continue ; } if ( I -> getNumExplicitDefs ( ) == 0 ) continue ; Defs . insert ( I -> defs ( ) . begin ( ) -> getReg ( ) ) ; } if ( B != E && std :: next ( B ) != E ) { finalizeBundle ( MBB , B , E ) ; Changed = true ; } Defs . clear ( ) ; } return Changed ; } </s>

AMDGPU SI SIInstrFlags::MTBUF SIInstrFlags::MUBUF SIInstrFlags::SMRD SIInstrFlags::DS SIInstrFlags::FLAT SIInstrFlags::MIMG 0 0


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . setPreservesCFG ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; AU . addRequired < MachineDominatorTree > ( ) ; AU . addPreserved < MachineDominatorTree > ( ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


This adds a condition to the basic_block NEW_BB in function FUNCTION_DECL to return a pointer to VERSION_DECL if we are running on a machine that supports the index CLONE_ISA hardware architecture bits . This function will be called during version dispatch to decide which function version to execute . It returns the basic block at the end , to which more conditions can be added .


<s> const GBZ80Subtarget * GBZ80TargetMachine :: getSubtargetImpl ( const Function & ) const { return & SubTarget ; } </s>

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .


<s> void AArch64PassConfig :: addIRPasses ( ) { addPass ( createAtomicExpandPass ( ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableAtomicTidy ) addPass ( createCFGSimplificationPass ( ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None ) { if ( EnableLoopDataPrefetch ) addPass ( createLoopDataPrefetchPass ( ) ) ; if ( EnableFalkorHWPFFix ) addPass ( createFalkorMarkStridedAccessesPass ( ) ) ; } TargetPassConfig :: addIRPasses ( ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None ) addPass ( createInterleavedAccessPass ( ) ) ; if ( TM -> getOptLevel ( ) == CodeGenOpt :: Aggressive && EnableGEPOpt ) { addPass ( createSeparateConstOffsetFromGEPPass ( TM , true ) ) ; addPass ( createEarlyCSEPass ( ) ) ; addPass ( createLICMPass ( ) ) ; } } </s>

Add common target configurable passes that perform LLVM IR to IR transforms following machine independent optimization .


<s> static void rs6000_setup_reg_addr_masks ( void ) { ssize_t rc , reg , m , nregs ; addr_mask_type any_addr_mask , addr_mask ; for ( m = 0 ; m < NUM_MACHINE_MODES ; ++ m ) { machine_mode m2 = ( machine_mode ) m ; unsigned short msize = GET_MODE_SIZE ( m2 ) ; bool indexed_only_p = ( m == SDmode && TARGET_NO_SDMODE_STACK ) ; any_addr_mask = 0 ; for ( rc = FIRST_RELOAD_REG_CLASS ; rc <= LAST_RELOAD_REG_CLASS ; rc ++ ) { addr_mask = 0 ; reg = reload_reg_map [ rc ] . reg ; if ( reg >= 0 && rs6000_hard_regno_mode_ok_p [ m ] [ reg ] ) { nregs = rs6000_hard_regno_nregs [ m ] [ reg ] ; addr_mask |= RELOAD_REG_VALID ; if ( nregs > 1 || m == BLKmode ) addr_mask |= RELOAD_REG_MULTIPLE ; else addr_mask |= RELOAD_REG_INDEXED ; if ( TARGET_UPDATE && ( rc == RELOAD_REG_GPR || rc == RELOAD_REG_FPR ) && msize <= 8 && ! VECTOR_MODE_P ( m2 ) && ! FLOAT128_VECTOR_P ( m2 ) && ! COMPLEX_MODE_P ( m2 ) && ( m2 != DFmode || ! TARGET_UPPER_REGS_DF ) && ( m2 != SFmode || ! TARGET_UPPER_REGS_SF ) && ! ( TARGET_E500_DOUBLE && msize == 8 ) ) { addr_mask |= RELOAD_REG_PRE_INCDEC ; switch ( m ) { default : addr_mask |= RELOAD_REG_PRE_MODIFY ; break ; case DImode : if ( TARGET_POWERPC64 ) addr_mask |= RELOAD_REG_PRE_MODIFY ; break ; case DFmode : case DDmode : if ( TARGET_DF_INSN ) addr_mask |= RELOAD_REG_PRE_MODIFY ; break ; } } } if ( ( addr_mask != 0 ) && ! indexed_only_p && msize <= 8 && ( rc == RELOAD_REG_GPR || rc == RELOAD_REG_FPR || ( rc == RELOAD_REG_VMX && TARGET_P9_DFORM && ( m2 == DFmode || m2 == SFmode ) ) ) ) addr_mask |= RELOAD_REG_OFFSET ; if ( rc == RELOAD_REG_VMX && msize == 16 && ( addr_mask & RELOAD_REG_VALID ) != 0 ) addr_mask |= RELOAD_REG_AND_M16 ; reg_addr [ m ] . addr_mask [ rc ] = addr_mask ; any_addr_mask |= addr_mask ; } reg_addr [ m ] . addr_mask [ RELOAD_REG_ANY ] = any_addr_mask ; } } </s>

Update the addr mask bits in reg_addr to help secondary reload and go if legitimate address support to figure out the appropriate addressing to use .


<s> unsigned Mips16InstrInfo :: loadImmediate ( unsigned FrameReg , int64_t Imm , MachineBasicBlock & MBB , MachineBasicBlock :: iterator II , DebugLoc DL , unsigned & NewImm ) const { RegScavenger rs ; int32_t lo = Imm & 0xFFFF ; int32_t hi = ( ( Imm >> 16 ) + ( lo >> 15 ) ) & 0xFFFF ; NewImm = lo ; unsigned Reg = 0 ; unsigned SpReg = 0 ; rs . enterBasicBlock ( & MBB ) ; rs . forward ( II ) ; unsigned FirstRegSaved = 0 , SecondRegSaved = 0 ; unsigned FirstRegSavedTo = 0 , SecondRegSavedTo = 0 ; Reg = rs . FindUnusedReg ( & Mips :: CPU16RegsRegClass ) ; if ( Reg == 0 ) { FirstRegSaved = Reg = Mips :: V0 ; FirstRegSavedTo = Mips :: T0 ; copyPhysReg ( MBB , II , DL , FirstRegSavedTo , FirstRegSaved , true ) ; } else rs . setUsed ( Reg ) ; BuildMI ( MBB , II , DL , get ( Mips :: LiRxImmX16 ) , Reg ) . addImm ( hi ) ; BuildMI ( MBB , II , DL , get ( Mips :: SllX16 ) , Reg ) . addReg ( Reg ) . addImm ( 16 ) ; if ( FrameReg == Mips :: SP ) { SpReg = rs . FindUnusedReg ( & Mips :: CPU16RegsRegClass ) ; if ( SpReg == 0 ) { if ( Reg != Mips :: V1 ) { SecondRegSaved = SpReg = Mips :: V1 ; SecondRegSavedTo = Mips :: T1 ; } else { SecondRegSaved = SpReg = Mips :: V0 ; SecondRegSavedTo = Mips :: T0 ; } copyPhysReg ( MBB , II , DL , SecondRegSavedTo , SecondRegSaved , true ) ; } else rs . setUsed ( SpReg ) ; copyPhysReg ( MBB , II , DL , SpReg , Mips :: SP , false ) ; BuildMI ( MBB , II , DL , get ( Mips :: AdduRxRyRz16 ) , Reg ) . addReg ( SpReg ) . addReg ( Reg ) ; } else BuildMI ( MBB , II , DL , get ( Mips :: AdduRxRyRz16 ) , Reg ) . addReg ( FrameReg ) . addReg ( Reg , RegState :: Kill ) ; if ( FirstRegSaved || SecondRegSaved ) { II = llvm :: next ( II ) ; if ( FirstRegSaved ) copyPhysReg ( MBB , II , DL , FirstRegSaved , FirstRegSavedTo , true ) ; if ( SecondRegSaved ) copyPhysReg ( MBB , II , DL , SecondRegSaved , SecondRegSavedTo , true ) ; } return Reg ; } </s>

Emit a series of instructions to load an immediate .


<s> TargetStackID :: Value AArch64FrameLowering :: getStackIDForScalableVectors ( ) const { return TargetStackID :: ScalableVector ; } </s>

Returns the StackID that scalable vectors should be associated with .


<s> bool AArch64AsmParser :: ParseDirective ( AsmToken DirectiveID ) { const MCObjectFileInfo :: Environment Format = getContext ( ) . getObjectFileInfo ( ) -> getObjectFileType ( ) ; bool IsMachO = Format == MCObjectFileInfo :: IsMachO ; bool IsCOFF = Format == MCObjectFileInfo :: IsCOFF ; StringRef IDVal = DirectiveID . getIdentifier ( ) ; SMLoc Loc = DirectiveID . getLoc ( ) ; if ( IDVal == ".hword" ) return parseDirectiveWord ( 2 , Loc ) ; if ( IDVal == ".word" ) return parseDirectiveWord ( 4 , Loc ) ; if ( IDVal == ".xword" ) return parseDirectiveWord ( 8 , Loc ) ; if ( IDVal == ".tlsdesccall" ) return parseDirectiveTLSDescCall ( Loc ) ; if ( IDVal == ".ltorg" || IDVal == ".pool" ) return parseDirectiveLtorg ( Loc ) ; if ( IDVal == ".unreq" ) return parseDirectiveUnreq ( DirectiveID . getLoc ( ) ) ; if ( ! IsMachO && ! IsCOFF ) { if ( IDVal == ".inst" ) return parseDirectiveInst ( Loc ) ; } return parseDirectiveLOH ( IDVal , Loc ) ; } </s>

ParseDirective - Parse a target specific assembler directive This method is deprecated , use 'parseDirective ' instead .


<s> const uint32_t * ARMBaseRegisterInfo :: getCallPreservedMask ( const MachineFunction & MF , CallingConv :: ID CC ) const { const ARMSubtarget & STI = MF . getSubtarget < ARMSubtarget > ( ) ; if ( CC == CallingConv :: GHC ) return CSR_NoRegs_RegMask ; if ( STI . getTargetLowering ( ) -> supportSwiftError ( ) && MF . getFunction ( ) -> getAttributes ( ) . hasAttrSomewhere ( Attribute :: SwiftError ) ) return STI . isTargetDarwin ( ) ? CSR_iOS_SwiftError_RegMask : CSR_AAPCS_SwiftError_RegMask ; if ( STI . isTargetDarwin ( ) && CC == CallingConv :: CXX_FAST_TLS ) return CSR_iOS_CXX_TLS_RegMask ; return STI . isTargetDarwin ( ) ? CSR_iOS_RegMask : CSR_AAPCS_RegMask ; } </s>

Return a mask of call-preserved registers for the given calling convention on the current function .


<s> static int rs6000_emit_p9_fp_cmove ( rtx dest , rtx op , rtx true_cond , rtx false_cond ) { enum rtx_code code = GET_CODE ( op ) ; rtx op0 = XEXP ( op , 0 ) ; rtx op1 = XEXP ( op , 1 ) ; machine_mode result_mode = GET_MODE ( dest ) ; rtx compare_rtx ; rtx cmove_rtx ; rtx clobber_rtx ; if ( ! can_create_pseudo_p ( ) ) return 0 ; switch ( code ) { case EQ : case GE : case GT : break ; case NE : case LT : case LE : code = swap_condition ( code ) ; std :: swap ( op0 , op1 ) ; break ; default : return 0 ; } compare_rtx = gen_rtx_fmt_ee ( code , CCFPmode , op0 , op1 ) ; cmove_rtx = gen_rtx_SET ( dest , gen_rtx_IF_THEN_ELSE ( result_mode , compare_rtx , true_cond , false_cond ) ) ; clobber_rtx = gen_rtx_CLOBBER ( VOIDmode , gen_rtx_SCRATCH ( V2DImode ) ) ; emit_insn ( gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( 2 , cmove_rtx , clobber_rtx ) ) ) ; return 1 ; } </s>

ISA 3.0 ( power9 ) conditional move subcase to emit XSCMP { EQ , GE , GT , NE } DP and XXSEL instructions for SF/DF scalars . Move TRUE_COND to DEST if OP of the operands of the last comparison is nonzero/true , FALSE_COND if it is zero/false . Return 0 if the hardware has no such operation .


<s> std :: pair < uint16_t , uint16_t > ARMBaseInstrInfo :: getExecutionDomain ( const MachineInstr * MI ) const { if ( MI -> getOpcode ( ) == ARM :: VMOVD && ! isPredicated ( MI ) ) return std :: make_pair ( ExeVFP , ( 1 << ExeVFP ) | ( 1 << ExeNEON ) ) ; unsigned Domain = MI -> getDesc ( ) . TSFlags & ARMII :: DomainMask ; if ( Domain & ARMII :: DomainNEON ) return std :: make_pair ( ExeNEON , 0 ) ; if ( ( Domain & ARMII :: DomainNEONA8 ) && Subtarget . isCortexA8 ( ) ) return std :: make_pair ( ExeNEON , 0 ) ; if ( Domain & ARMII :: DomainVFP ) return std :: make_pair ( ExeVFP , 0 ) ; return std :: make_pair ( ExeGeneric , 0 ) ; } </s>

Return the current execution domain and bit mask of possible domains for instruction .


<s> bool isReg ( ) const { return Kind == Register ; } </s>


"optionally flag setting instruction missing optional def operand"

checkTargetMatchPredicate - Validate the instruction match against any complex target predicates not expressible via match classes .


Return true if the vector misalignment factor is supported by the target .


<s> Register getGlobalBaseReg ( ) const { return GlobalBaseReg ; } </s>

getGlobalBaseReg - Return a virtual register initialized with the the global base register value .


<s> const char * getPassName ( ) const override { return AARCH64_ADVSIMD_NAME ; } </s>

getPassName - Return a nice clean name for a pass .


<s> SDValue PIC16TargetLowering :: LowerOperation ( SDValue Op , SelectionDAG & DAG ) { switch ( Op . getOpcode ( ) ) { case ISD :: FORMAL_ARGUMENTS : return LowerFORMAL_ARGUMENTS ( Op , DAG ) ; case ISD :: ADD : case ISD :: ADDC : case ISD :: ADDE : return LowerADD ( Op , DAG ) ; case ISD :: SUB : case ISD :: SUBC : case ISD :: SUBE : return LowerSUB ( Op , DAG ) ; case ISD :: LOAD : return ExpandLoad ( Op . getNode ( ) , DAG ) ; case ISD :: STORE : return ExpandStore ( Op . getNode ( ) , DAG ) ; case ISD :: SHL : case ISD :: SRA : case ISD :: SRL : return LowerShift ( Op , DAG ) ; case ISD :: OR : case ISD :: AND : case ISD :: XOR : return LowerBinOp ( Op , DAG ) ; case ISD :: CALL : return LowerCALL ( Op , DAG ) ; case ISD :: RET : return LowerRET ( Op , DAG ) ; case ISD :: BR_CC : return LowerBR_CC ( Op , DAG ) ; case ISD :: SELECT_CC : return LowerSELECT_CC ( Op , DAG ) ; } return SDValue ( ) ; } </s>

LowerOperation - Provide custom lowering hooks for some operations .

PIC16 PIC16 ISD::FORMAL_ARGUMENTS ISD::ADD ISD::ADDC ISD::ADDE ISD::SUB ISD::SUBC ISD::SUBE ISD::LOAD ISD::STORE ISD::SHL ISD::SRA ISD::SRL ISD::OR ISD::AND ISD::XOR ISD::CALL ISD::RET ISD::BR_CC ISD::SELECT_CC


<s> bool SIPeepholeSDWA :: runOnMachineFunction ( MachineFunction & MF ) { const GCNSubtarget & ST = MF . getSubtarget < GCNSubtarget > ( ) ; if ( ! ST . hasSDWA ( ) || skipFunction ( MF . getFunction ( ) ) ) return false ; MRI = & MF . getRegInfo ( ) ; TRI = ST . getRegisterInfo ( ) ; TII = ST . getInstrInfo ( ) ; bool Ret = false ; for ( MachineBasicBlock & MBB : MF ) { bool Changed = false ; do { matchSDWAOperands ( MBB ) ; for ( const auto & OperandPair : SDWAOperands ) { const auto & Operand = OperandPair . second ; MachineInstr * PotentialMI = Operand -> potentialToConvert ( TII ) ; if ( PotentialMI && ( PotentialMI -> getOpcode ( ) == AMDGPU :: V_ADD_I32_e64 || PotentialMI -> getOpcode ( ) == AMDGPU :: V_SUB_I32_e64 ) ) pseudoOpConvertToVOP2 ( * PotentialMI , ST ) ; } SDWAOperands . clear ( ) ; matchSDWAOperands ( MBB ) ; for ( const auto & OperandPair : SDWAOperands ) { const auto & Operand = OperandPair . second ; MachineInstr * PotentialMI = Operand -> potentialToConvert ( TII ) ; if ( PotentialMI && isConvertibleToSDWA ( * PotentialMI , ST ) ) { PotentialMatches [ PotentialMI ] . push_back ( Operand . get ( ) ) ; } } for ( auto & PotentialPair : PotentialMatches ) { MachineInstr & PotentialMI = * PotentialPair . first ; convertToSDWA ( PotentialMI , PotentialPair . second ) ; } PotentialMatches . clear ( ) ; SDWAOperands . clear ( ) ; Changed = ! ConvertedInstructions . empty ( ) ; if ( Changed ) Ret = true ; while ( ! ConvertedInstructions . empty ( ) ) legalizeScalarOperands ( * ConvertedInstructions . pop_back_val ( ) , ST ) ; } while ( Changed ) ; } return Ret ; } </s>

runOnMachineFunction - Emit the function body .


<s> static bool isThumb ( const MCSubtargetInfo & STI ) { return ( STI . getFeatureBits ( ) & ARM :: ModeThumb ) != 0 ; } </s>

Tests whether the target is Thumb ( little and big endian ) .


<s> void SystemZAsmPrinter :: emitMachineConstantPoolValue ( MachineConstantPoolValue * MCPV ) { auto * ZCPV = static_cast < SystemZConstantPoolValue * > ( MCPV ) ; const MCExpr * Expr = MCSymbolRefExpr :: create ( getSymbol ( ZCPV -> getGlobalValue ( ) ) , getModifierVariantKind ( ZCPV -> getModifier ( ) ) , OutContext ) ; uint64_t Size = getDataLayout ( ) . getTypeAllocSize ( ZCPV -> getType ( ) ) ; OutStreamer -> emitValue ( Expr , Size ) ; } </s>

EmitMachineConstantPoolValue - Print a machine constantpool value to the .s file .


<s> bool NVPTXLowerAggrCopies :: runOnFunction ( Function & F ) { SmallVector < LoadInst * , 4 > AggrLoads ; SmallVector < MemIntrinsic * , 4 > MemCalls ; const DataLayout & DL = F . getParent ( ) -> getDataLayout ( ) ; LLVMContext & Context = F . getParent ( ) -> getContext ( ) ; for ( Function :: iterator BI = F . begin ( ) , BE = F . end ( ) ; BI != BE ; ++ BI ) { for ( BasicBlock :: iterator II = BI -> begin ( ) , IE = BI -> end ( ) ; II != IE ; ++ II ) { if ( LoadInst * LI = dyn_cast < LoadInst > ( II ) ) { if ( ! LI -> hasOneUse ( ) ) continue ; if ( DL . getTypeStoreSize ( LI -> getType ( ) ) < MaxAggrCopySize ) continue ; if ( StoreInst * SI = dyn_cast < StoreInst > ( LI -> user_back ( ) ) ) { if ( SI -> getOperand ( 0 ) != LI ) continue ; AggrLoads . push_back ( LI ) ; } } else if ( MemIntrinsic * IntrCall = dyn_cast < MemIntrinsic > ( II ) ) { if ( ConstantInt * LenCI = dyn_cast < ConstantInt > ( IntrCall -> getLength ( ) ) ) { if ( LenCI -> getZExtValue ( ) >= MaxAggrCopySize ) { MemCalls . push_back ( IntrCall ) ; } } else { MemCalls . push_back ( IntrCall ) ; } } } } if ( AggrLoads . size ( ) == 0 && MemCalls . size ( ) == 0 ) { return false ; } for ( LoadInst * LI : AggrLoads ) { StoreInst * SI = dyn_cast < StoreInst > ( * LI -> user_begin ( ) ) ; Value * SrcAddr = LI -> getOperand ( 0 ) ; Value * DstAddr = SI -> getOperand ( 1 ) ; unsigned NumLoads = DL . getTypeStoreSize ( LI -> getType ( ) ) ; Value * CopyLen = ConstantInt :: get ( Type :: getInt32Ty ( Context ) , NumLoads ) ; createMemCpyLoop ( SI , SrcAddr , DstAddr , CopyLen , LI -> getAlignment ( ) , SI -> getAlignment ( ) , LI -> isVolatile ( ) , SI -> isVolatile ( ) ) ; SI -> eraseFromParent ( ) ; LI -> eraseFromParent ( ) ; } for ( MemIntrinsic * MemCall : MemCalls ) { if ( MemCpyInst * Memcpy = dyn_cast < MemCpyInst > ( MemCall ) ) { expandMemCpyAsLoop ( Memcpy ) ; } else if ( MemMoveInst * Memmove = dyn_cast < MemMoveInst > ( MemCall ) ) { expandMemMoveAsLoop ( Memmove ) ; } else if ( MemSetInst * Memset = dyn_cast < MemSetInst > ( MemCall ) ) { expandMemSetAsLoop ( Memset ) ; } MemCall -> eraseFromParent ( ) ; } return true ; } </s>

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .


<s> static int microblaze_save_volatiles ( tree func ) { tree a ; if ( TREE_CODE ( func ) != FUNCTION_DECL ) return 0 ; a = lookup_attribute ( "save_volatiles" , DECL_ATTRIBUTES ( func ) ) ; return a != NULL_TREE ; } </s>

Return true if FUNC is an interrupt function which uses normal return , indicated by the `` save_volatiles '' attribute .


<s> const SparcMCExpr * SparcMCExpr :: Create ( VariantKind Kind , const MCExpr * Expr , MCContext & Ctx ) { return new ( Ctx ) SparcMCExpr ( Kind , Expr ) ; } </s>

Construct a unary instruction , given the opcode and an operand .


<s> void MBlazeInstrInfo :: storeRegToStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned SrcReg , bool isKill , int FI , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { DebugLoc DL ; BuildMI ( MBB , I , DL , get ( MBlaze :: SWI ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addFrameIndex ( FI ) . addImm ( 0 ) ; } </s>

Store the specified register of the given register class to the specified stack frame index .


<s> static machine_mode rs6000_c_mode_for_suffix ( char suffix ) { if ( TARGET_FLOAT128_TYPE ) { if ( suffix == 'q' || suffix == 'Q' ) return ( FLOAT128_IEEE_P ( TFmode ) ) ? TFmode : KFmode ; } return VOIDmode ; } </s>


<s> bool Z80Operand :: isImm ( ) const { return this -> Kind == k_Imm ; } </s>


<s> BitVector MSP430RegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; const TargetFrameLowering * TFI = MF . getTarget ( ) . getFrameLowering ( ) ; Reserved . set ( MSP430 :: PCB ) ; Reserved . set ( MSP430 :: SPB ) ; Reserved . set ( MSP430 :: SRB ) ; Reserved . set ( MSP430 :: CGB ) ; Reserved . set ( MSP430 :: PCW ) ; Reserved . set ( MSP430 :: SPW ) ; Reserved . set ( MSP430 :: SRW ) ; Reserved . set ( MSP430 :: CGW ) ; if ( TFI -> hasFP ( MF ) ) Reserved . set ( MSP430 :: FPW ) ; return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s> Instruction * front ( ) const { return Chain . front ( ) ; } </s>

front - Get the first character in the string .


<s>
MachineBasicBlock
::
iterator
ARMBaseInstrInfo
::
insertOutlinedCall
(
Module
&
M
,
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
&
It
,
MachineFunction
&
MF
,
const
outliner
::
Candidate
&
C
)
const
{
MachineInstrBuilder
MIB
;
MachineBasicBlock
::
iterator
CallPt
;
unsigned
Opc
;
bool
isThumb
=
Subtarget
.
isThumb
(
)
;
if
(
C
.
CallConstructionID
==
MachineOutlinerTailCall
)
{
Opc
=
isThumb
Subtarget
.
isTargetMachO
(
)
ARM
::
tTAILJMPd
:
ARM
::
tTAILJMPdND
:
ARM
::
TAILJMPd
;
MIB
=
BuildMI
(
MF
,
DebugLoc
(
)
,
get
(
Opc
)
)
.
addGlobalAddress
(
M
.
getNamedValue
(
MF
.
getName
(
)
)
)
;
if
(
isThumb
)
MIB
.
add
(
predOps
(
ARMCC
::
AL
)
)
;
It
=
MBB
.
insert
(
It
,
MIB
)
;
return
It
;
}
Opc
=
isThumb
ARM
::
tBL
:
ARM
::
BL
;
MachineInstrBuilder
CallMIB
=
BuildMI
(
MF
,
DebugLoc
(
)
,
get
(
Opc
)
)
;
if
(
isThumb
)
CallMIB
.
add
(
predOps
(
ARMCC
::
AL
)
)
;
CallMIB
.
addGlobalAddress
(
M
.
getNamedValue
(
MF
.
getName
(
)
)
)
;
if
(
C
.
CallConstructionID
==
MachineOutlinerNoLRSave
||
C
.
CallConstructionID
==
MachineOutlinerThunk
)
{
It
=
MBB
.
insert
(
It
,
CallMIB
)
;
return
It
;
}
const
ARMFunctionInfo
&
AFI
=
*
C
.
getMF
(
)
->
getInfo
<
ARMFunctionInfo
>
(
)
;
if
(
C
.
CallConstructionID
==
MachineOutlinerRegSave
)
{
unsigned
Reg
=
findRegisterToSaveLRTo
(
C
)
;
assert
(
Reg
!=
0
&&
"No callee-saved register available?"
)
;
copyPhysReg
(
MBB
,
It
,
DebugLoc
(
)
,
Reg
,
ARM
::
LR
,
true
)
;
if
(
!
AFI
.
isLRSpilled
(
)
)
emitCFIForLRSaveToReg
(
MBB
,
It
,
Reg
)
;
CallPt
=
MBB
.
insert
(
It
,
CallMIB
)
;
copyPhysReg
(
MBB
,
It
,
DebugLoc
(
)
,
ARM
::
LR
,
Reg
,
true
)
;
if
(
!
AFI
.
isLRSpilled
(
)
)
emitCFIForLRRestoreFromReg
(
MBB
,
It
)
;
It
;
return
CallPt
;
}
if
(
!
MBB
.
isLiveIn
(
ARM
::
LR
)
)
MBB
.
addLiveIn
(
ARM
::
LR
)
;
saveLROnStack
(
MBB
,
It
)
;
if
(
!
AFI
.
isLRSpilled
(
)
)
emitCFIForLRSaveOnStack
(
MBB
,
It
)
;
CallPt
=
MBB
.
insert
(
It
,
CallMIB
)
;
restoreLRFromStack
(
MBB
,
It
)
;
if
(
!
AFI
.
isLRSpilled
(
)
)
emitCFIForLRRestoreFromStack
(
MBB
,
It
)
;
It
;
return
CallPt
;
}
</s>

Insert a call to an outlined function into the program .

ARM
ARM
ARM::tTAILJMPd
ARM::tTAILJMPdND
ARM::TAILJMPd
ARMCC::AL
ARM::tBL
ARM::BL
ARMCC::AL
ARM
ARM
0
"No callee-saved register available?"
ARM::LR
ARM::LR
ARM::LR
ARM::LR


<s> bool AMDGPUTargetLowering :: isCheapToSpeculateCttz ( ) const { return true ; } </s>

Return true if it is cheap to speculate a call to intrinsic cttz .


<s> MachineBasicBlock :: iterator VEFrameLowering :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { if ( ! hasReservedCallFrame ( MF ) ) { MachineInstr & MI = * I ; int64_t Size = MI . getOperand ( 0 ) . getImm ( ) ; if ( MI . getOpcode ( ) == VE :: ADJCALLSTACKDOWN ) Size = - Size ; if ( Size ) emitSPAdjustment ( MF , MBB , I , Size ) ; } return MBB . erase ( I ) ; } </s>

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .


<s> static bool spu_function_ok_for_sibcall ( tree decl , tree exp ATTRIBUTE_UNUSED ) { return decl && ! TARGET_LARGE_MEM ; } </s>

Decide whether we can make a sibling call to a function . DECL is the declaration of the function being targeted by the call and EXP is the CALL_EXPR representing the call .


"multiversioning needs %<ifunc%> which is not supported "

Make a dispatcher declaration for the multi-versioned function DECL . Calls to DECL function will be replaced with calls to the dispatcher by the front-end . Returns the decl of the dispatcher function .


<s> static HOST_WIDE_INT get_label_padding ( rtx label ) { HOST_WIDE_INT align , min_insn_size ; align = 1 << label_to_alignment ( label ) ; min_insn_size = TARGET_THUMB ? 2 : 4 ; return align > min_insn_size ? align - min_insn_size : 0 ; } </s>

Return the maximum amount of padding that will be inserted before label LABEL .


<s> virtual const VideocoreRegisterInfo * getRegisterInfo ( ) const { return & getInstrInfo ( ) -> getRegisterInfo ( ) ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s>
SDValue
M68kTargetLowering
::
LowerOperation
(
SDValue
Op
,
SelectionDAG
&
DAG
)
const
{
switch
(
Op
.
getOpcode
(
)
)
{
default
:
llvm_unreachable
(
"Should not custom lower this!"
)
;
case
ISD
::
SADDO
:
case
ISD
::
UADDO
:
case
ISD
::
SSUBO
:
case
ISD
::
USUBO
:
case
ISD
::
SMULO
:
case
ISD
::
UMULO
:
return
LowerXALUO
(
Op
,
DAG
)
;
case
ISD
::
SETCC
:
return
LowerSETCC
(
Op
,
DAG
)
;
case
ISD
::
SETCCCARRY
:
return
LowerSETCCCARRY
(
Op
,
DAG
)
;
case
ISD
::
SELECT
:
return
LowerSELECT
(
Op
,
DAG
)
;
case
ISD
::
BRCOND
:
return
LowerBRCOND
(
Op
,
DAG
)
;
case
ISD
::
ADDC
:
case
ISD
::
ADDE
:
case
ISD
::
SUBC
:
case
ISD
::
SUBE
:
return
LowerADDC_ADDE_SUBC_SUBE
(
Op
,
DAG
)
;
case
ISD
::
ConstantPool
:
return
LowerConstantPool
(
Op
,
DAG
)
;
case
ISD
::
GlobalAddress
:
return
LowerGlobalAddress
(
Op
,
DAG
)
;
case
ISD
::
ExternalSymbol
:
return
LowerExternalSymbol
(
Op
,
DAG
)
;
case
ISD
::
BlockAddress
:
return
LowerBlockAddress
(
Op
,
DAG
)
;
case
ISD
::
JumpTable
:
return
LowerJumpTable
(
Op
,
DAG
)
;
case
ISD
::
VASTART
:
return
LowerVASTART
(
Op
,
DAG
)
;
case
ISD
::
DYNAMIC_STACKALLOC
:
return
LowerDYNAMIC_STACKALLOC
(
Op
,
DAG
)
;
}
}
</s>

LowerOperation - Provide custom lowering hooks for some operations .

M68k
M68k
"Should not custom lower this!"
ISD::SADDO
ISD::UADDO
ISD::SSUBO
ISD::USUBO
ISD::SMULO
ISD::UMULO
ISD::SETCC
ISD::SETCCCARRY
ISD::SELECT
ISD::BRCOND
ISD::ADDC
ISD::ADDE
ISD::SUBC
ISD::SUBE
ISD::ConstantPool
ISD::GlobalAddress
ISD::ExternalSymbol
ISD::BlockAddress
ISD::JumpTable
ISD::VASTART
ISD::DYNAMIC_STACKALLOC


<s> void X86PassConfig :: addPreRegAlloc ( ) { if ( getOptLevel ( ) != CodeGenOpt :: None ) { addPass ( & LiveRangeShrinkID ) ; addPass ( createX86FixupSetCC ( ) ) ; addPass ( createX86OptimizeLEAs ( ) ) ; addPass ( createX86CallFrameOptimization ( ) ) ; addPass ( createX86FixupSFB ( ) ) ; } addPass ( createX86WinAllocaExpander ( ) ) ; } </s>

This method may be implemented by targets that want to run passes immediately before register allocation .


<s> virtual const TargetRegisterInfo & getRegisterInfo ( ) const { return RI ; } </s>


<s> bool hasVolatileVariant ( Instruction * I , unsigned AddrSpace ) { if ( ! ( AddrSpace == llvm :: ADDRESS_SPACE_GENERIC || AddrSpace == llvm :: ADDRESS_SPACE_GLOBAL || AddrSpace == llvm :: ADDRESS_SPACE_SHARED ) ) return false ; switch ( I -> getOpcode ( ) ) { default : return false ; case Instruction :: Load : case Instruction :: Store : return true ; } } </s>

Return true if the given instruction ( assumed to be a memory access instruction ) has a volatile variant .


<s> static rtx xstormy16_libcall_value ( machine_mode mode , const_rtx fun ATTRIBUTE_UNUSED ) { return gen_rtx_REG ( mode , RETURN_VALUE_REGNUM ) ; } </s>

Worker function for TARGET_LIBCALL_VALUE .


<s> int valid_dbcc_comparison_p_2 ( rtx x , enum machine_mode mode ATTRIBUTE_UNUSED ) { switch ( GET_CODE ( x ) ) { case EQ : case NE : case GTU : case LTU : case GEU : case LEU : return 1 ; case GT : case LT : case GE : case LE : return ! ( cc_prev_status . flags & CC_NO_OVERFLOW ) ; default : return 0 ; } } </s>

Return true if X is a valid comparison operator for the dbcc instruction . Note it rejects floating point comparison operators . ( In the future we could use Fdbcc ) . It also rejects some comparisons when CC_NO_OVERFLOW is set .


<s> void M88kMCAsmBackend :: applyFixup ( const MCAssembler & Asm , const MCFixup & Fixup , const MCValue & Target , MutableArrayRef < char > Data , uint64_t Value , bool IsResolved , const MCSubtargetInfo * STI ) const { MCFixupKind Kind = Fixup . getKind ( ) ; unsigned Offset = Fixup . getOffset ( ) ; unsigned NumBytes = ( getFixupKindInfo ( Kind ) . TargetSize + 7 ) / 8 ; unsigned FullSize = 4 ; uint64_t CurVal = 0 ; for ( unsigned i = 0 ; i != NumBytes ; ++ i ) { unsigned Idx = ( FullSize - 1 - i ) ; CurVal |= static_cast < uint64_t > ( static_cast < uint8_t > ( Data [ Offset + Idx ] ) ) << ( i * 8 ) ; } uint64_t Mask = ( static_cast < uint64_t > ( - 1 ) >> ( 64 - getFixupKindInfo ( Kind ) . TargetSize ) ) ; CurVal |= Value & Mask ; for ( unsigned i = 0 ; i != NumBytes ; ++ i ) { unsigned Idx = ( FullSize - 1 - i ) ; Data [ Offset + Idx ] = static_cast < uint8_t > ( ( CurVal >> ( i * 8 ) ) & 0xff ) ; } } </s>

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


<s>
bool
SITargetLowering
::
isLegalAddressingMode
(
const
DataLayout
&
DL
,
const
AddrMode
&
AM
,
Type
*
Ty
,
unsigned
AS
)
const
{
if
(
AM
.
BaseGV
)
return
false
;
switch
(
AS
)
{
case
AMDGPUAS
::
GLOBAL_ADDRESS
:
{
if
(
Subtarget
->
getGeneration
(
)
>=
AMDGPUSubtarget
::
VOLCANIC_ISLANDS
)
{
return
isLegalFlatAddressingMode
(
AM
)
;
}
return
isLegalMUBUFAddressingMode
(
AM
)
;
}
case
AMDGPUAS
::
CONSTANT_ADDRESS
:
{
if
(
AM
.
BaseOffs
%
4
!=
0
)
return
isLegalMUBUFAddressingMode
(
AM
)
;
if
(
DL
.
getTypeStoreSize
(
Ty
)
<
4
)
return
isLegalMUBUFAddressingMode
(
AM
)
;
if
(
Subtarget
->
getGeneration
(
)
==
AMDGPUSubtarget
::
SOUTHERN_ISLANDS
)
{
if
(
!
isUInt
<
8
>
(
AM
.
BaseOffs
/
4
)
)
return
false
;
}
else
if
(
Subtarget
->
getGeneration
(
)
==
AMDGPUSubtarget
::
SEA_ISLANDS
)
{
if
(
!
isUInt
<
32
>
(
AM
.
BaseOffs
/
4
)
)
return
false
;
}
else
if
(
Subtarget
->
getGeneration
(
)
==
AMDGPUSubtarget
::
VOLCANIC_ISLANDS
)
{
if
(
!
isUInt
<
20
>
(
AM
.
BaseOffs
)
)
return
false
;
}
else
llvm_unreachable
(
"unhandled generation"
)
;
if
(
AM
.
Scale
==
0
)
return
true
;
if
(
AM
.
Scale
==
1
&&
AM
.
HasBaseReg
)
return
true
;
return
false
;
}
case
AMDGPUAS
::
PRIVATE_ADDRESS
:
return
isLegalMUBUFAddressingMode
(
AM
)
;
case
AMDGPUAS
::
LOCAL_ADDRESS
:
case
AMDGPUAS
::
REGION_ADDRESS
:
{
if
(
!
isUInt
<
16
>
(
AM
.
BaseOffs
)
)
return
false
;
if
(
AM
.
Scale
==
0
)
return
true
;
if
(
AM
.
Scale
==
1
&&
AM
.
HasBaseReg
)
return
true
;
return
false
;
}
case
AMDGPUAS
::
FLAT_ADDRESS
:
case
AMDGPUAS
::
UNKNOWN_ADDRESS_SPACE
:
return
isLegalFlatAddressingMode
(
AM
)
;
default
:
llvm_unreachable
(
"unhandled address space"
)
;
}
}
</s>

isLegalAddressingMode - Return true if the addressing mode represented by AM is legal for this target , for a load/store of the specified type .


<s> bool MipsCallLowering :: lowerFormalArguments ( MachineIRBuilder & MIRBuilder , const Function & F , ArrayRef < unsigned > VRegs ) const { if ( F . arg_empty ( ) ) return true ; if ( F . isVarArg ( ) ) { return false ; } for ( auto & Arg : F . args ( ) ) { if ( ! isSupportedType ( Arg . getType ( ) ) ) return false ; } MachineFunction & MF = MIRBuilder . getMF ( ) ; const DataLayout & DL = MF . getDataLayout ( ) ; const MipsTargetLowering & TLI = * getTLI < MipsTargetLowering > ( ) ; SmallVector < ArgInfo , 8 > ArgInfos ; SmallVector < unsigned , 8 > OrigArgIndices ; unsigned i = 0 ; for ( auto & Arg : F . args ( ) ) { ArgInfo AInfo ( VRegs [ i ] , Arg . getType ( ) ) ; setArgFlags ( AInfo , i + AttributeList :: FirstArgIndex , DL , F ) ; splitToValueTypes ( AInfo , i , ArgInfos , OrigArgIndices ) ; ++ i ; } SmallVector < ISD :: InputArg , 8 > Ins ; subTargetRegTypeForCallingConv ( MIRBuilder , ArgInfos , OrigArgIndices , [ & ] ( ISD :: ArgFlagsTy flags , EVT vt , EVT argvt , bool used , unsigned origIdx , unsigned partOffs ) { Ins . emplace_back ( flags , vt , argvt , used , origIdx , partOffs ) ; } ) ; SmallVector < CCValAssign , 16 > ArgLocs ; MipsCCState CCInfo ( F . getCallingConv ( ) , F . isVarArg ( ) , MF , ArgLocs , F . getContext ( ) ) ; const MipsTargetMachine & TM = static_cast < const MipsTargetMachine & > ( MF . getTarget ( ) ) ; const MipsABIInfo & ABI = TM . getABI ( ) ; CCInfo . AllocateStack ( ABI . GetCalleeAllocdArgSizeInBytes ( F . getCallingConv ( ) ) , 1 ) ; CCInfo . AnalyzeFormalArguments ( Ins , TLI . CCAssignFnForCall ( ) ) ; IncomingValueHandler Handler ( MIRBuilder , MF . getRegInfo ( ) ) ; if ( ! Handler . handle ( ArgLocs , ArgInfos ) ) return false ; return true ; } </s>

This hook must be implemented to lower the incoming ( formal ) arguments , described by VRegs , for GlobalISel .


<s>
const
char
*
getPassName
(
)
const
override
{
return
"optimise barriers pass"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> bool PadShortFunc :: runOnMachineFunction ( MachineFunction & MF ) { bool OptForSize = MF . getFunction ( ) -> getAttributes ( ) . hasAttribute ( AttributeSet :: FunctionIndex , Attribute :: OptimizeForSize ) ; if ( OptForSize ) return false ; TM = & MF . getTarget ( ) ; TII = TM -> getInstrInfo ( ) ; ReturnBBs . clear ( ) ; findReturns ( MF . begin ( ) ) ; bool MadeChange = false ; MachineBasicBlock :: iterator ReturnLoc ; MachineBasicBlock * MBB ; unsigned int Cycles = 0 ; unsigned int BBCycles ; for ( DenseMap < MachineBasicBlock * , unsigned int > :: iterator I = ReturnBBs . begin ( ) ; I != ReturnBBs . end ( ) ; ++ I ) { MBB = I -> first ; Cycles = I -> second ; if ( Cycles < Threshold ) { if ( ! cyclesUntilReturn ( MBB , BBCycles , & ReturnLoc ) ) continue ; addPadding ( MBB , ReturnLoc , Threshold - Cycles ) ; NumBBsPadded ++ ; MadeChange = true ; } } return MadeChange ; } </s>

runOnMachineFunction - Emit the function body .


<s> virtual void * getAdjustedAnalysisPointer ( const void * ID ) override { if ( ID == & TargetTransformInfo :: ID ) return ( TargetTransformInfo * ) this ; return this ; } </s>

getAdjustedAnalysisPointer - This method is used when a pass implements an analysis interface through multiple inheritance .


<s> static void ia64_override_options_after_change ( void ) { if ( optimize >= 3 && ! OPTION_SET_P ( flag_selective_scheduling ) && ! OPTION_SET_P ( flag_selective_scheduling2 ) ) { flag_selective_scheduling2 = 1 ; flag_sel_sched_pipelining = 1 ; } if ( mflag_sched_control_spec == 2 ) { mflag_sched_control_spec = flag_selective_scheduling2 ? 1 : 0 ; } if ( flag_sel_sched_pipelining && flag_auto_inc_dec ) { flag_auto_inc_dec = 0 ; } } </s>


<s> unsigned X86TargetLowering :: getRegPressureLimit ( const TargetRegisterClass * RC , MachineFunction & MF ) const { const TargetFrameInfo * TFI = MF . getTarget ( ) . getFrameInfo ( ) ; unsigned FPDiff = TFI -> hasFP ( MF ) ? 1 : 0 ; switch ( RC -> getID ( ) ) { default : return 0 ; case X86 :: GR32RegClassID : return 4 - FPDiff ; case X86 :: GR64RegClassID : return 8 - FPDiff ; case X86 :: VR128RegClassID : return Subtarget -> is64Bit ( ) ? 10 : 4 ; case X86 :: VR64RegClassID : return 4 ; } } </s>

Return the register pressure `` high water mark '' for the specific register class .


<s> SDValue FISCTargetLowering :: LowerCallResult ( SDValue Chain , SDValue InGlue , CallingConv :: ID CallConv , bool isVarArg , const SmallVectorImpl < ISD :: InputArg > & Ins , SDLoc dl , SelectionDAG & DAG , SmallVectorImpl < SDValue > & InVals ) const { SmallVector < CCValAssign , 16 > RVLocs ; CCState CCInfo ( CallConv , isVarArg , DAG . getMachineFunction ( ) , RVLocs , * DAG . getContext ( ) ) ; AnalyzeReturnValues ( CCInfo , RVLocs , Ins ) ; for ( unsigned i = 0 ; i != RVLocs . size ( ) ; ++ i ) { Chain = DAG . getCopyFromReg ( Chain , dl , RVLocs [ i ] . getLocReg ( ) , RVLocs [ i ] . getValVT ( ) , InGlue ) . getValue ( 1 ) ; InGlue = Chain . getValue ( 2 ) ; InVals . push_back ( Chain . getValue ( 0 ) ) ; } return Chain ; } </s>

LowerCallResult - Lower the result values of an ISD : :CALL into the appropriate copies out of appropriate physical registers .


<s> unsigned PPCFastISel :: fastMaterializeConstant ( const Constant * C ) { EVT CEVT = TLI . getValueType ( C -> getType ( ) , true ) ; if ( ! CEVT . isSimple ( ) ) return 0 ; MVT VT = CEVT . getSimpleVT ( ) ; if ( const ConstantFP * CFP = dyn_cast < ConstantFP > ( C ) ) return PPCMaterializeFP ( CFP , VT ) ; else if ( const GlobalValue * GV = dyn_cast < GlobalValue > ( C ) ) return PPCMaterializeGV ( GV , VT ) ; else if ( isa < ConstantInt > ( C ) ) return PPCMaterializeInt ( C , VT ) ; return 0 ; } </s>

Emit a constant in a register using target-specific logic , such as constant pool loads .


<s> const TargetRegisterClass * getRegClass ( const MCInstrDesc & TID , unsigned OpNum , const TargetRegisterInfo * TRI , const MachineFunction & MF ) const override { if ( OpNum >= TID . getNumOperands ( ) ) return nullptr ; return RI . getRegClass ( TID . OpInfo [ OpNum ] . RegClass ) ; } </s>

Given a machine instruction descriptor , returns the register class constraint for OpNum , or NULL .


<s> bool AMDGPUAnnotateKernelFeatures :: runOnModule ( Module & M ) { Triple TT ( M . getTargetTriple ( ) ) ; static const StringRef IntrinsicToAttr [ ] [ 2 ] = { { "llvm.amdgcn.workitem.id.y" , "amdgpu-work-item-id-y" } , { "llvm.amdgcn.workitem.id.z" , "amdgpu-work-item-id-z" } , { "llvm.amdgcn.workgroup.id.y" , "amdgpu-work-group-id-y" } , { "llvm.amdgcn.workgroup.id.z" , "amdgpu-work-group-id-z" } , { "llvm.r600.read.tgid.y" , "amdgpu-work-group-id-y" } , { "llvm.r600.read.tgid.z" , "amdgpu-work-group-id-z" } , { "llvm.r600.read.tidig.y" , "amdgpu-work-item-id-y" } , { "llvm.r600.read.tidig.z" , "amdgpu-work-item-id-z" } } ; static const StringRef HSAIntrinsicToAttr [ ] [ 2 ] = { { "llvm.amdgcn.dispatch.ptr" , "amdgpu-dispatch-ptr" } , { "llvm.amdgcn.queue.ptr" , "amdgpu-queue-ptr" } , { "llvm.amdgcn.dispatch.id" , "amdgpu-dispatch-id" } , { "llvm.trap" , "amdgpu-queue-ptr" } , { "llvm.debugtrap" , "amdgpu-queue-ptr" } } ; bool Changed = addAttrsForIntrinsics ( M , IntrinsicToAttr ) ; if ( TT . getOS ( ) == Triple :: AMDHSA || TT . getOS ( ) == Triple :: Mesa3D ) { Changed |= addAttrsForIntrinsics ( M , HSAIntrinsicToAttr ) ; for ( Function & F : M ) { if ( F . hasFnAttribute ( "amdgpu-queue-ptr" ) ) continue ; if ( hasAddrSpaceCast ( F ) ) F . addFnAttr ( "amdgpu-queue-ptr" ) ; } } return Changed ; } </s>

runOnModule - Virtual method overriden by subclasses to process the module being operated on .


"Can't load this register from stack slot"

Load the specified register of the given register class from the specified stack frame index .


<s> static void s390_mainpool_finish ( struct constant_pool * pool ) { rtx base_reg = cfun -> machine -> base_reg ; rtx set ; rtx_insn * insn ; if ( pool -> size == 0 ) { cfun -> machine -> base_reg = NULL_RTX ; if ( pool -> pool_insn ) remove_insn ( pool -> pool_insn ) ; s390_free_pool ( pool ) ; return ; } shorten_branches ( get_insns ( ) ) ; set = gen_main_base_64 ( base_reg , pool -> label ) ; insn = emit_insn_after ( set , pool -> pool_insn ) ; INSN_ADDRESSES_NEW ( insn , - 1 ) ; remove_insn ( pool -> pool_insn ) ; insn = get_last_insn ( ) ; pool -> pool_insn = emit_insn_after ( gen_pool ( const0_rtx ) , insn ) ; INSN_ADDRESSES_NEW ( pool -> pool_insn , - 1 ) ; s390_dump_pool ( pool , 0 ) ; for ( rtx_insn * insn = get_insns ( ) ; insn ; insn = NEXT_INSN ( insn ) ) { if ( NONJUMP_INSN_P ( insn ) || CALL_P ( insn ) ) { rtx addr , pool_ref = NULL_RTX ; find_constant_pool_ref ( insn , & pool_ref ) ; if ( pool_ref ) { if ( s390_execute_label ( insn ) ) addr = s390_find_execute ( pool , insn ) ; else addr = s390_find_constant ( pool , get_pool_constant ( pool_ref ) , get_pool_mode ( pool_ref ) ) ; replace_constant_pool_ref ( insn , pool_ref , addr ) ; INSN_CODE ( insn ) = - 1 ; } } } s390_free_pool ( pool ) ; } </s>

POOL holds the main literal pool as collected by s390_mainpool_start . Modify the current function to output the pool constants as well as the pool register setup instruction .


<s> inline bool registered_function_hasher :: equal ( value_type value , const compare_type & key ) { return value -> instance == key ; } </s>


<s> static bool s390_vector_mode_supported_p ( machine_mode mode ) { machine_mode inner ; if ( ! VECTOR_MODE_P ( mode ) || ! TARGET_VX || GET_MODE_SIZE ( mode ) > 16 ) return false ; inner = GET_MODE_INNER ( mode ) ; switch ( inner ) { case QImode : case HImode : case SImode : case DImode : case TImode : case SFmode : case DFmode : case TFmode : return true ; default : return false ; } } </s>

Return true if the back end supports vector mode MODE .


<s> bool convertSelectOfConstantsToMath ( EVT VT ) const override { return true ; } </s>

Return true if a select of constants ( select Cond , C1 , C2 ) should be transformed into simple math ops with the condition value .


<s>
void
TPCHazardRecognizer
::
RecedeCycle
(
)
{
PacketNum
++
;
LLVM_DEBUG
(
dbgs
(
)
<<
"  *HR* RecedeCycle("
<<
PacketNum
<<
")\n"
)
;
dumpCurPacket
(
)
;
clearResources
(
)
;
}
</s>

RecedeCycle - This callback is invoked whenever the next bottom-up instruction to be scheduled can not issue in the current cycle , either because of latency or resource conflicts .


<s>
void
SystemZPostRASchedStrategy
::
enterMBB
(
MachineBasicBlock
*
NextMBB
)
{
assert
(
(
SchedStates
.
find
(
NextMBB
)
==
SchedStates
.
end
(
)
)
&&
"Entering MBB twice?"
)
;
LLVM_DEBUG
(
dbgs
(
)
<<
"** Entering "
<<
printMBBReference
(
*
NextMBB
)
)
;
MBB
=
NextMBB
;
HazardRec
=
SchedStates
[
MBB
]
=
new
SystemZHazardRecognizer
(
TII
,
&
SchedModel
)
;
LLVM_DEBUG
(
const
MachineLoop
*
Loop
=
MLI
->
getLoopFor
(
MBB
)
;
if
(
Loop
&&
Loop
->
getHeader
(
)
==
MBB
)
dbgs
(
)
<<
" (Loop header)"
;
dbgs
(
)
<<
":\n"
;
)
;
MachineBasicBlock
*
SinglePredMBB
=
getSingleSchedPred
(
MBB
,
MLI
->
getLoopFor
(
MBB
)
)
;
if
(
SinglePredMBB
==
nullptr
||
SchedStates
.
find
(
SinglePredMBB
)
==
SchedStates
.
end
(
)
)
return
;
LLVM_DEBUG
(
dbgs
(
)
<<
"** Continued scheduling from "
<<
printMBBReference
(
*
SinglePredMBB
)
<<
"\n"
;
)
;
HazardRec
->
copyState
(
SchedStates
[
SinglePredMBB
]
)
;
LLVM_DEBUG
(
HazardRec
->
dumpState
(
)
;
)
;
for
(
MachineInstr
&
MI
:
SinglePredMBB
->
terminators
(
)
)
{
LLVM_DEBUG
(
dbgs
(
)
<<
"** Emitting incoming branch: "
;
MI
.
dump
(
)
;
)
;
bool
TakenBranch
=
(
MI
.
isBranch
(
)
&&
(
TII
->
getBranchInfo
(
MI
)
.
isIndirect
(
)
||
TII
->
getBranchInfo
(
MI
)
.
getMBBTarget
(
)
==
MBB
)
)
;
HazardRec
->
emitInstruction
(
&
MI
,
TakenBranch
)
;
if
(
TakenBranch
)
break
;
}
}
</s>

Tell the strategy that MBB is about to be processed .

SystemZ
SystemZ
"Entering MBB twice?"
"** Entering "
SystemZ
" (Loop header)"
":\n"
"** Continued scheduling from "
"\n"
"** Emitting incoming branch: "


<s> static unsigned int get_csky_live_regs ( int * count ) { int reg ; unsigned int live_regs_mask = 0 ; * count = 0 ; for ( reg = 0 ; reg < CSKY_NGPR_REGS ; reg ++ ) { bool save = false ; if ( CSKY_TARGET_ARCH ( CK801 ) && reg > 8 && reg < 13 ) continue ; if ( ( CSKY_TARGET_ARCH ( CK801 ) || CSKY_TARGET_ARCH ( CK802 ) || CSKY_TARGET_ARCH ( CK803 ) ) && reg > 15 ) break ; if ( df_regs_ever_live_p ( reg ) && ! call_really_used_regs [ reg ] ) save = true ; else if ( frame_pointer_needed && reg == FRAME_POINTER_REGNUM ) save = true ; else if ( crtl -> calls_eh_return && reg == FRAME_POINTER_REGNUM ) save = true ; else if ( ( CSKY_TARGET_ARCH ( CK801 ) || CSKY_TARGET_ARCH ( CK802 ) ) && reg == CSKY_LR_REGNUM && ( ! crtl -> is_leaf || csky_far_jump_used_p ( ) ) ) save = true ; else if ( crtl -> calls_eh_return && reg >= CSKY_FIRST_EH_RETDATA_REGNUM && reg <= CSKY_LAST_EH_RETDATA_REGNUM ) save = true ; if ( reg == CSKY_STACKADJUST_REGNUM && cfun -> machine -> reg_offset > CSKY_MAX_SP_ADJUST * 2 ) save = true ; if ( save ) { ( * count ) ++ ; live_regs_mask |= ( 1 << reg ) ; } } return live_regs_mask ; } </s>

Return the mask of registers used by the current function . Set COUNT to the number of registers used .


<s> bool SIWholeQuadMode :: runOnMachineFunction ( MachineFunction & MF ) { if ( MF . getFunction ( ) -> getCallingConv ( ) != CallingConv :: AMDGPU_PS ) return false ; Instructions . clear ( ) ; Blocks . clear ( ) ; ExecExports . clear ( ) ; LiveMaskQueries . clear ( ) ; TII = static_cast < const SIInstrInfo * > ( MF . getSubtarget ( ) . getInstrInfo ( ) ) ; TRI = static_cast < const SIRegisterInfo * > ( MF . getSubtarget ( ) . getRegisterInfo ( ) ) ; MRI = & MF . getRegInfo ( ) ; char GlobalFlags = analyzeFunction ( MF ) ; if ( ! ( GlobalFlags & StateWQM ) ) { lowerLiveMaskQueries ( AMDGPU :: EXEC ) ; return ! LiveMaskQueries . empty ( ) ; } MachineBasicBlock & Entry = MF . front ( ) ; MachineInstr * EntryMI = Entry . getFirstNonPHI ( ) ; unsigned LiveMaskReg = 0 ; if ( GlobalFlags & StateExact || ! LiveMaskQueries . empty ( ) ) { LiveMaskReg = MRI -> createVirtualRegister ( & AMDGPU :: SReg_64RegClass ) ; BuildMI ( Entry , EntryMI , DebugLoc ( ) , TII -> get ( AMDGPU :: COPY ) , LiveMaskReg ) . addReg ( AMDGPU :: EXEC ) ; } if ( GlobalFlags == StateWQM ) { BuildMI ( Entry , EntryMI , DebugLoc ( ) , TII -> get ( AMDGPU :: S_WQM_B64 ) , AMDGPU :: EXEC ) . addReg ( AMDGPU :: EXEC ) ; lowerLiveMaskQueries ( LiveMaskReg ) ; return true ; } lowerLiveMaskQueries ( LiveMaskReg ) ; EntryMI = nullptr ; for ( const auto & BII : Blocks ) processBlock ( const_cast < MachineBasicBlock & > ( * BII . first ) , LiveMaskReg , BII . first == & * MF . begin ( ) ) ; return true ; } </s>

AMDGPU SI AMDGPU SI SI AMDGPU::EXEC 0 AMDGPU::SReg_64RegClass AMDGPU::COPY AMDGPU::EXEC AMDGPU::S_WQM_B64 AMDGPU::EXEC AMDGPU::EXEC


<s> bool avr_emit3_fix_outputs ( rtx ( * gen ) ( rtx , rtx , rtx ) , rtx * op , unsigned opmask , unsigned rmask ) { const int n = 3 ; rtx hreg [ n ] ; static bool lock = false ; gcc_assert ( opmask < ( 1u << n ) ) ; if ( lock ) return false ; avr_fix_operands ( op , hreg , opmask , rmask ) ; lock = true ; emit_insn ( gen ( op [ 0 ] , op [ 1 ] , op [ 2 ] ) ) ; lock = false ; return avr_move_fixed_operands ( op , hreg , opmask ) ; } </s>

PR63633 : The middle-end might come up with hard regs as output operands . GEN is a sequence generating function like gen_mulsi3 with 3 operands OP [ ] . RMASK is a bit mask representing a subset of hard registers R0 ... R31 : Rn is an element of that set iff bit n of RMASK is set . OPMASK describes a subset of OP [ ] : If bit n of OPMASK is 1 then OP [ n ] has to be fixed ; otherwise OP [ n ] is left alone . Emit the insn sequence as generated by GEN ( ) with all elements of OPMASK which are hard registers overlapping RMASK replaced by newly created pseudo registers . After the sequence has been emitted , emit insns that move the contents of respective pseudos to their hard regs .


<s> bool requiresRegisterScavenging ( const MachineFunction & MF ) const override { return true ; } </s>

Returns true if the target requires ( and can make use of ) the register scavenger .


<s> bool isFMAFasterThanFMulAndFAdd ( const MachineFunction & MF , EVT ) const override { return true ; } </s>

Return true if an FMA operation is faster than a pair of fmul and fadd instructions .


Write an ( optimal ) nop sequence of Count bytes to the given output .


<s>
MachineBasicBlock
::
iterator
ARMBaseInstrInfo
::
insertOutlinedCall
(
Module
&
M
,
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
&
It
,
MachineFunction
&
MF
,
const
outliner
::
Candidate
&
C
)
const
{
MachineInstrBuilder
MIB
;
MachineBasicBlock
::
iterator
CallPt
;
unsigned
Opc
;
bool
isThumb
=
Subtarget
.
isThumb
(
)
;
if
(
C
.
CallConstructionID
==
MachineOutlinerTailCall
)
{
Opc
=
isThumb
Subtarget
.
isTargetMachO
(
)
ARM
::
tTAILJMPd
:
ARM
::
tTAILJMPdND
:
ARM
::
TAILJMPd
;
MIB
=
BuildMI
(
MF
,
DebugLoc
(
)
,
get
(
Opc
)
)
.
addGlobalAddress
(
M
.
getNamedValue
(
MF
.
getName
(
)
)
)
;
if
(
isThumb
)
MIB
.
add
(
predOps
(
ARMCC
::
AL
)
)
;
It
=
MBB
.
insert
(
It
,
MIB
)
;
return
It
;
}
Opc
=
isThumb
ARM
::
tBL
:
ARM
::
BL
;
MachineInstrBuilder
CallMIB
=
BuildMI
(
MF
,
DebugLoc
(
)
,
get
(
Opc
)
)
;
if
(
isThumb
)
CallMIB
.
add
(
predOps
(
ARMCC
::
AL
)
)
;
CallMIB
.
addGlobalAddress
(
M
.
getNamedValue
(
MF
.
getName
(
)
)
)
;
if
(
C
.
CallConstructionID
==
MachineOutlinerNoLRSave
||
C
.
CallConstructionID
==
MachineOutlinerThunk
)
{
It
=
MBB
.
insert
(
It
,
CallMIB
)
;
return
It
;
}
const
ARMFunctionInfo
&
AFI
=
*
C
.
getMF
(
)
->
getInfo
<
ARMFunctionInfo
>
(
)
;
if
(
C
.
CallConstructionID
==
MachineOutlinerRegSave
)
{
unsigned
Reg
=
findRegisterToSaveLRTo
(
C
)
;
assert
(
Reg
!=
0
&&
"No callee-saved register available?"
)
;
copyPhysReg
(
MBB
,
It
,
DebugLoc
(
)
,
Reg
,
ARM
::
LR
,
true
)
;
if
(
!
AFI
.
isLRSpilled
(
)
)
emitCFIForLRSaveToReg
(
MBB
,
It
,
Reg
)
;
CallPt
=
MBB
.
insert
(
It
,
CallMIB
)
;
copyPhysReg
(
MBB
,
It
,
DebugLoc
(
)
,
ARM
::
LR
,
Reg
,
true
)
;
if
(
!
AFI
.
isLRSpilled
(
)
)
emitCFIForLRRestoreFromReg
(
MBB
,
It
)
;
It
;
return
CallPt
;
}
if
(
!
MBB
.
isLiveIn
(
ARM
::
LR
)
)
MBB
.
addLiveIn
(
ARM
::
LR
)
;
bool
Auth
=
!
AFI
.
isLRSpilled
(
)
&&
AFI
.
shouldSignReturnAddress
(
true
)
;
saveLROnStack
(
MBB
,
It
,
!
AFI
.
isLRSpilled
(
)
,
Auth
)
;
CallPt
=
MBB
.
insert
(
It
,
CallMIB
)
;
restoreLRFromStack
(
MBB
,
It
,
!
AFI
.
isLRSpilled
(
)
,
Auth
)
;
It
;
return
CallPt
;
}
</s>

Insert a call to an outlined function into the program .


<s> void altivec_expand_lvx_be ( rtx op0 , rtx op1 , machine_mode mode , unsigned unspec ) { rtx tmp = gen_reg_rtx ( mode ) ; rtx load = gen_rtx_SET ( tmp , op1 ) ; rtx lvx = gen_rtx_UNSPEC ( mode , gen_rtvec ( 1 , const0_rtx ) , unspec ) ; rtx par = gen_rtx_PARALLEL ( mode , gen_rtvec ( 2 , load , lvx ) ) ; rtx sel = swap_selector_for_mode ( mode ) ; rtx vperm = gen_rtx_UNSPEC ( mode , gen_rtvec ( 3 , tmp , tmp , sel ) , UNSPEC_VPERM ) ; gcc_assert ( REG_P ( op0 ) ) ; emit_insn ( par ) ; emit_insn ( gen_rtx_SET ( op0 , vperm ) ) ; } </s>

Generate code for an `` lvx '' , `` lvxl '' , or `` lve * x '' built-in for a little endian target with -maltivec=be specified . Issue the load followed by an element-reversing permute .


<s> rtx avr_to_int_mode ( rtx x ) { machine_mode mode = GET_MODE ( x ) ; return VOIDmode == mode ? x : simplify_gen_subreg ( int_mode_for_mode ( mode ) , x , mode , 0 ) ; } </s>

Access some RTX as INT_MODE . If X is a CONST_FIXED we can get the bit representation of X by `` casting '' it to CONST_INT .


<s> static bool ft32_pass_by_reference ( cumulative_args_t cum ATTRIBUTE_UNUSED , enum machine_mode mode , const_tree type , bool named ATTRIBUTE_UNUSED ) { unsigned HOST_WIDE_INT size ; if ( type ) { if ( AGGREGATE_TYPE_P ( type ) ) return true ; size = int_size_in_bytes ( type ) ; } else size = GET_MODE_SIZE ( mode ) ; return size > 4 * 6 ; } </s>

Return non-zero if the function argument described by TYPE is to be passed by reference .


<s> void mips_declare_object ( FILE * stream , const char * name , const char * init_string , const char * final_string , ... ) { va_list ap ; fputs ( init_string , stream ) ; assemble_name ( stream , name ) ; va_start ( ap , final_string ) ; vfprintf ( stream , final_string , ap ) ; va_end ( ap ) ; if ( ! TARGET_EXPLICIT_RELOCS ) { tree name_tree = get_identifier ( name ) ; TREE_ASM_WRITTEN ( name_tree ) = 1 ; } } </s>

Emit either a label , .comm , or .lcomm directive . When using assembler macros , mark the symbol as written so that mips_file_end wo n't emit an .extern for it . STREAM is the output file , NAME is the name of the symbol , INIT_STRING is the string that should be written before the symbol and FINAL_STRING is the string that should be written after it . FINAL_STRING is a printf ( ) format that consumes the remaining arguments .


<s> void X86AsmPrinter :: emitEndOfAsmFile ( Module & M ) { const Triple & TT = TM . getTargetTriple ( ) ; if ( TT . isOSBinFormatMachO ( ) ) { emitNonLazyStubs ( MMI , * OutStreamer ) ; emitStackMaps ( SM ) ; FM . serializeToFaultMapSection ( ) ; OutStreamer -> emitAssemblerFlag ( MCAF_SubsectionsViaSymbols ) ; } else if ( TT . isOSBinFormatCOFF ( ) ) { if ( MMI -> usesMSVCFloatingPoint ( ) ) { StringRef SymbolName = ( TT . getArch ( ) == Triple :: x86 ) ? "__fltused" : "_fltused" ; MCSymbol * S = MMI -> getContext ( ) . getOrCreateSymbol ( SymbolName ) ; OutStreamer -> emitSymbolAttribute ( S , MCSA_Global ) ; return ; } emitStackMaps ( SM ) ; } else if ( TT . isOSBinFormatELF ( ) ) { emitStackMaps ( SM ) ; FM . serializeToFaultMapSection ( ) ; } if ( TT . getArch ( ) == Triple :: x86_64 && TM . getCodeModel ( ) == CodeModel :: Large ) { if ( MCSymbol * AddrSymbol = OutContext . lookupSymbol ( "__morestack_addr" ) ) { Align Alignment ( 1 ) ; MCSection * ReadOnlySection = getObjFileLowering ( ) . getSectionForConstant ( getDataLayout ( ) , SectionKind :: getReadOnly ( ) , nullptr , Alignment ) ; OutStreamer -> SwitchSection ( ReadOnlySection ) ; OutStreamer -> emitLabel ( AddrSymbol ) ; unsigned PtrSize = MAI -> getCodePointerSize ( ) ; OutStreamer -> emitSymbolValue ( GetExternalSymbolSymbol ( "__morestack" ) , PtrSize ) ; } } } </s>

This virtual method can be overridden by targets that want to emit something at the end of their file .


<s> const M680x0InstrInfo * getInstrInfo ( ) const override { return & InstrInfo ; } </s>


<s> SDValue ARM64TargetLowering :: PerformDAGCombine ( SDNode * N , DAGCombinerInfo & DCI ) const { SelectionDAG & DAG = DCI . DAG ; switch ( N -> getOpcode ( ) ) { default : break ; case ISD :: ADD : case ISD :: SUB : return performAddSubLongCombine ( N , DCI , DAG ) ; case ISD :: XOR : return performXorCombine ( N , DAG , DCI , Subtarget ) ; case ISD :: MUL : return performMulCombine ( N , DAG , DCI , Subtarget ) ; case ISD :: SINT_TO_FP : case ISD :: UINT_TO_FP : return performIntToFpCombine ( N , DAG ) ; case ISD :: OR : return performORCombine ( N , DCI , Subtarget ) ; case ISD :: INTRINSIC_WO_CHAIN : return performIntrinsicCombine ( N , DCI , Subtarget ) ; case ISD :: ANY_EXTEND : case ISD :: ZERO_EXTEND : case ISD :: SIGN_EXTEND : return performExtendCombine ( N , DCI , DAG ) ; case ISD :: BITCAST : return performBitcastCombine ( N , DCI , DAG ) ; case ISD :: CONCAT_VECTORS : return performConcatVectorsCombine ( N , DCI , DAG ) ; case ISD :: SELECT : return performSelectCombine ( N , DAG ) ; case ISD :: VSELECT : return performVSelectCombine ( N , DCI . DAG ) ; case ISD :: STORE : return performSTORECombine ( N , DCI , DAG , Subtarget ) ; case ARM64ISD :: BRCOND : return performBRCONDCombine ( N , DCI , DAG ) ; } return SDValue ( ) ; } </s>

This method will be invoked for all target nodes and for any target-independent nodes that the target has registered with invoke it for .


<s> void MOSMCELFStreamer :: changeSection ( MCSection * Section , const MCExpr * Subsection ) { MCELFStreamer :: changeSection ( Section , Subsection ) ; HasBSS |= Section -> getName ( ) . startswith ( ".bss" ) ; HasData |= Section -> getName ( ) . startswith ( ".data" ) ; HasInitArray |= Section -> getName ( ) . startswith ( ".init_array" ) ; HasFiniArray |= Section -> getName ( ) . startswith ( ".fini_array" ) ; } </s>

Update streamer for a new active section .


<s> SDValue LanaiTargetLowering :: LowerCallResult ( SDValue Chain , SDValue InFlag , CallingConv :: ID CallConv , bool IsVarArg , const SmallVectorImpl < ISD :: InputArg > & Ins , const SDLoc & DL , SelectionDAG & DAG , SmallVectorImpl < SDValue > & InVals ) const { SmallVector < CCValAssign , 16 > RVLocs ; CCState CCInfo ( CallConv , IsVarArg , DAG . getMachineFunction ( ) , RVLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeCallResult ( Ins , RetCC_Lanai32 ) ; for ( unsigned I = 0 ; I != RVLocs . size ( ) ; ++ I ) { Chain = DAG . getCopyFromReg ( Chain , DL , RVLocs [ I ] . getLocReg ( ) , RVLocs [ I ] . getValVT ( ) , InFlag ) . getValue ( 1 ) ; InFlag = Chain . getValue ( 2 ) ; InVals . push_back ( Chain . getValue ( 0 ) ) ; } return Chain ; } </s>

LowerCallResult - Lower the result values of an ISD : :CALL into the appropriate copies out of appropriate physical registers .


<s> bool MipsSEDAGToDAGISel :: runOnMachineFunction ( MachineFunction & MF ) { if ( Subtarget -> inMips16Mode ( ) ) return false ; return MipsDAGToDAGISel :: runOnMachineFunction ( MF ) ; } </s>

runOnMachineFunction - Emit the function body .


<s> const CallLowering * getCallLowering ( ) const override { return CallLoweringInfo . get ( ) ; } </s>


<s> int AMDGPUInstrInfo :: pseudoToMCOpcode ( int Opcode ) const { int MCOp = AMDGPU :: getMCOpcode ( Opcode , subtargetEncodingFamily ( ST ) ) ; if ( MCOp == - 1 ) return Opcode ; if ( MCOp == ( uint16_t ) - 1 ) return - 1 ; return MCOp ; } </s>

Return a target-specific opcode if Opcode is a pseudo instruction .


<s> bool Nios2InstrInfo :: expandPostRAPseudo ( MachineInstr & MI ) const { MachineBasicBlock & MBB = * MI . getParent ( ) ; switch ( MI . getDesc ( ) . getOpcode ( ) ) { default : return false ; case Nios2 :: RetRA : BuildMI ( MBB , MI , MI . getDebugLoc ( ) , get ( Nios2 :: RET_R1 ) ) . addReg ( Nios2 :: RA ) ; break ; } MBB . erase ( MI ) ; return true ; } </s>

This function is called for all pseudo instructions that remain after register allocation .


<s> bool NVPTXAsmPrinter :: runOnMachineFunction ( MachineFunction & F ) { bool Result = AsmPrinter :: runOnMachineFunction ( F ) ; OutStreamer -> emitRawText ( StringRef ( "}\n" ) ) ; return Result ; } </s>


<s> TargetLoweringObjectFile * getObjFileLowering ( ) const override { return TLOF ; } </s>

Return information about object file lowering .


<s> const InstrItineraryData * getInstrItineraryData ( ) const override { return Subtarget . inMips16Mode ( ) ? nullptr : & getSubtargetImpl ( ) -> getInstrItineraryData ( ) ; } </s>

getInstrItineraryData - Returns instruction itinerary data for the target or specific subtarget .


"Default init of reg %u inserted: insn %u\n"

Initialize all declared regs at function entry . Advantage : Fool-proof . Disadvantage : Potentially creates a lot of long live ranges and adds a lot of insns .


<s>
SDValue
AMDGPUTargetLowering
::
LowerOperation
(
SDValue
Op
,
SelectionDAG
&
DAG
)
const
{
switch
(
Op
.
getOpcode
(
)
)
{
default
:
Op
.
getNode
(
)
->
dump
(
)
;
llvm_unreachable
(
"Custom lowering code for this"
"instruction is not implemented yet!"
)
;
break
;
case
ISD
::
SIGN_EXTEND_INREG
:
return
LowerSIGN_EXTEND_INREG
(
Op
,
DAG
)
;
case
ISD
::
CONCAT_VECTORS
:
return
LowerCONCAT_VECTORS
(
Op
,
DAG
)
;
case
ISD
::
EXTRACT_SUBVECTOR
:
return
LowerEXTRACT_SUBVECTOR
(
Op
,
DAG
)
;
case
ISD
::
FrameIndex
:
return
LowerFrameIndex
(
Op
,
DAG
)
;
case
ISD
::
INTRINSIC_WO_CHAIN
:
return
LowerINTRINSIC_WO_CHAIN
(
Op
,
DAG
)
;
case
ISD
::
UDIVREM
:
return
LowerUDIVREM
(
Op
,
DAG
)
;
case
ISD
::
SDIVREM
:
return
LowerSDIVREM
(
Op
,
DAG
)
;
case
ISD
::
FREM
:
return
LowerFREM
(
Op
,
DAG
)
;
case
ISD
::
FCEIL
:
return
LowerFCEIL
(
Op
,
DAG
)
;
case
ISD
::
FTRUNC
:
return
LowerFTRUNC
(
Op
,
DAG
)
;
case
ISD
::
FRINT
:
return
LowerFRINT
(
Op
,
DAG
)
;
case
ISD
::
FNEARBYINT
:
return
LowerFNEARBYINT
(
Op
,
DAG
)
;
case
ISD
::
FFLOOR
:
return
LowerFFLOOR
(
Op
,
DAG
)
;
case
ISD
::
UINT_TO_FP
:
return
LowerUINT_TO_FP
(
Op
,
DAG
)
;
}
return
Op
;
}
</s>

LowerOperation - Provide custom lowering hooks for some operations .

R600
"Custom lowering code for this"
"instruction is not implemented yet!"
ISD::SIGN_EXTEND_INREG
SI
ISD::CONCAT_VECTORS
ISD::EXTRACT_SUBVECTOR
ISD::FrameIndex
ISD::INTRINSIC_WO_CHAIN
SI
ISD::UDIVREM
ISD::SDIVREM
ISD::FREM
ISD::FCEIL
ISD::FTRUNC
ISD::FRINT
ISD::FNEARBYINT
ISD::FFLOOR
ISD::UINT_TO_FP


<s> bool isImm ( ) const override { return Kind == k_Imm ; } </s>


<s> bool isProfitableToIfCvt ( MachineBasicBlock & MBB , unsigned NumCycles , unsigned ExtraPredCycles , const BranchProbability & Probability ) const override { return true ; } </s>


<s>
bool
RISCVAsmParser
::
ParseInstruction
(
ParseInstructionInfo
&
Info
,
StringRef
Name
,
SMLoc
NameLoc
,
OperandVector
&
Operands
)
{
Operands
.
push_back
(
RISCVOperand
::
createToken
(
Name
,
NameLoc
)
)
;
if
(
getLexer
(
)
.
is
(
AsmToken
::
EndOfStatement
)
)
return
false
;
if
(
parseOperand
(
Operands
)
)
return
true
;
while
(
getLexer
(
)
.
is
(
AsmToken
::
Comma
)
)
{
getLexer
(
)
.
Lex
(
)
;
if
(
parseOperand
(
Operands
)
)
return
true
;
}
if
(
getLexer
(
)
.
isNot
(
AsmToken
::
EndOfStatement
)
)
{
SMLoc
Loc
=
getLexer
(
)
.
getLoc
(
)
;
getParser
(
)
.
eatToEndOfStatement
(
)
;
return
Error
(
Loc
,
"unexpected token"
)
;
}
getParser
(
)
.
Lex
(
)
;
return
false
;
}
</s>

ParseInstruction - Parse one assembly instruction .


For stack frames that ca n't be allocated with a single ADDI instruction , compute the best value to initially allocate . It must at a minimum allocate enough space to spill the callee-saved registers .


<s> TTI :: AddressingModeKind HexagonTTIImpl :: getPreferredAddressingMode ( const Loop * L , ScalarEvolution * SE ) const { return TTI :: AMK_PostIndexed ; } </s>

Return the preferred addressing mode LSR should make efforts to generate .


<s> unsigned LEGInstrInfo :: insertBranch ( MachineBasicBlock & MBB , MachineBasicBlock * TBB , MachineBasicBlock * FBB , ArrayRef < MachineOperand > Cond , const DebugLoc & DL , int * BytesAdded ) const { unsigned NumInserted = 0 ; if ( Cond . size ( ) > 0 ) { BuildMI ( MBB , MBB . end ( ) , DL , get ( LEG :: Bcc ) ) . addOperand ( Cond [ 0 ] ) . addMBB ( TBB ) ; NumInserted ++ ; } if ( Cond . empty ( ) || FBB ) { BuildMI ( MBB , MBB . end ( ) , DL , get ( LEG :: B ) ) . addMBB ( Cond . empty ( ) ? TBB : FBB ) ; NumInserted ++ ; } return NumInserted ; } </s>

Insert branch code into the end of the specified MachineBasicBlock .


<s>
void
P2FrameLowering
::
emitPrologue
(
MachineFunction
&
MF
,
MachineBasicBlock
&
MBB
)
const
{
LLVM_DEBUG
(
dbgs
(
)
<<
"Emit Prologue: "
<<
MF
.
getName
(
)
<<
"\n"
)
;
const
P2InstrInfo
*
TII
=
MF
.
getSubtarget
<
P2Subtarget
>
(
)
.
getInstrInfo
(
)
;
MachineBasicBlock
::
iterator
MBBI
=
MBB
.
begin
(
)
;
P2FunctionInfo
*
P2FI
=
MF
.
getInfo
<
P2FunctionInfo
>
(
)
;
MachineFrameInfo
&
MFI
=
MF
.
getFrameInfo
(
)
;
uint64_t
StackSize
=
MFI
.
getStackSize
(
)
4
P2FI
->
getIncomingArgSize
(
)
;
LLVM_DEBUG
(
errs
(
)
<<
"Allocating "
<<
StackSize
<<
" bytes for stack (original value: "
<<
MFI
.
getStackSize
(
)
<<
")\n"
)
;
if
(
StackSize
==
0
)
{
LLVM_DEBUG
(
errs
(
)
<<
"No need to allocate stack space\n"
)
;
return
;
}
TII
->
adjustStackPtr
(
P2
::
PTRA
,
StackSize
,
MBB
,
MBBI
)
;
}
</s>

emitProlog/emitEpilog - These methods insert prolog and epilog code into the function .


"Memory Intrinsic results: call to builtin function "

"with wrong signature, from/to mismatch"

optimizeCall - Take the given call instruction and return a more optimal value to replace the instruction with or 0 if a more optimal form ca n't be found .


<s> bool hasBranchDivergence ( ) { return true ; } </s>

Return true if branch divergence exists .


<s> static SDValue LowerCallResult ( SDValue Chain , SDValue InFlag , const SmallVectorImpl < CCValAssign > & RVLocs , SDLoc dl , SelectionDAG & DAG , SmallVectorImpl < SDValue > & InVals ) { SmallVector < std :: pair < int , unsigned > , 4 > ResultMemLocs ; for ( unsigned i = 0 , e = RVLocs . size ( ) ; i != e ; ++ i ) { const CCValAssign & VA = RVLocs [ i ] ; if ( VA . isRegLoc ( ) ) { Chain = DAG . getCopyFromReg ( Chain , dl , VA . getLocReg ( ) , VA . getValVT ( ) , InFlag ) . getValue ( 1 ) ; InFlag = Chain . getValue ( 2 ) ; InVals . push_back ( Chain . getValue ( 0 ) ) ; } else { assert ( VA . isMemLoc ( ) ) ; ResultMemLocs . push_back ( std :: make_pair ( VA . getLocMemOffset ( ) , InVals . size ( ) ) ) ; InVals . push_back ( SDValue ( ) ) ; } } SmallVector < SDValue , 4 > MemOpChains ; for ( unsigned i = 0 , e = ResultMemLocs . size ( ) ; i != e ; ++ i ) { int offset = ResultMemLocs [ i ] . first ; unsigned index = ResultMemLocs [ i ] . second ; SDVTList VTs = DAG . getVTList ( MVT :: i32 , MVT :: Other ) ; SDValue Ops [ ] = { Chain , DAG . getConstant ( offset / 4 , MVT :: i32 ) } ; SDValue load = DAG . getNode ( XCoreISD :: LDWSP , dl , VTs , Ops , 2 ) ; InVals [ index ] = load ; MemOpChains . push_back ( load . getValue ( 1 ) ) ; } if ( ! MemOpChains . empty ( ) ) Chain = DAG . getNode ( ISD :: TokenFactor , dl , MVT :: Other , & MemOpChains [ 0 ] , MemOpChains . size ( ) ) ; return Chain ; } </s>


<s> bool DLXInstrInfo :: expandPostRAPseudo ( MachineInstr & MI ) const { return false ; } </s>


<s> static int thumb2_legitimate_address_p ( machine_mode mode , rtx x , int strict_p ) { bool use_ldrd ; enum rtx_code code = GET_CODE ( x ) ; if ( arm_address_register_rtx_p ( x , strict_p ) ) return 1 ; use_ldrd = ( TARGET_LDRD && ( mode == DImode || mode == DFmode ) ) ; if ( code == POST_INC || code == PRE_DEC || ( ( code == PRE_INC || code == POST_DEC ) && ( use_ldrd || GET_MODE_SIZE ( mode ) <= 4 ) ) ) return arm_address_register_rtx_p ( XEXP ( x , 0 ) , strict_p ) ; else if ( ( code == POST_MODIFY || code == PRE_MODIFY ) && arm_address_register_rtx_p ( XEXP ( x , 0 ) , strict_p ) && GET_CODE ( XEXP ( x , 1 ) ) == PLUS && rtx_equal_p ( XEXP ( XEXP ( x , 1 ) , 0 ) , XEXP ( x , 0 ) ) ) { rtx addend = XEXP ( XEXP ( x , 1 ) , 1 ) ; HOST_WIDE_INT offset ; if ( ! CONST_INT_P ( addend ) ) return 0 ; offset = INTVAL ( addend ) ; if ( GET_MODE_SIZE ( mode ) <= 4 ) return ( offset > - 256 && offset < 256 ) ; return ( use_ldrd && offset > - 1024 && offset < 1024 && ( offset & 3 ) == 0 ) ; } else if ( reload_completed && ( code == LABEL_REF || ( code == CONST && GET_CODE ( XEXP ( x , 0 ) ) == PLUS && GET_CODE ( XEXP ( XEXP ( x , 0 ) , 0 ) ) == LABEL_REF && CONST_INT_P ( XEXP ( XEXP ( x , 0 ) , 1 ) ) ) ) ) return 1 ; else if ( mode == TImode || ( TARGET_NEON && VALID_NEON_STRUCT_MODE ( mode ) ) ) return 0 ; else if ( code == PLUS ) { rtx xop0 = XEXP ( x , 0 ) ; rtx xop1 = XEXP ( x , 1 ) ; return ( ( arm_address_register_rtx_p ( xop0 , strict_p ) && ( thumb2_legitimate_index_p ( mode , xop1 , strict_p ) || ( ! strict_p && will_be_in_index_register ( xop1 ) ) ) ) || ( arm_address_register_rtx_p ( xop1 , strict_p ) && thumb2_legitimate_index_p ( mode , xop0 , strict_p ) ) ) ; } else if ( can_avoid_literal_pool_for_label_p ( x ) ) return 0 ; else if ( GET_MODE_CLASS ( mode ) != MODE_FLOAT && code == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P ( x ) && ! ( flag_pic && symbol_mentioned_p ( get_pool_constant ( x ) ) && ! pcrel_constant_p ( get_pool_constant ( x ) ) ) ) return 1 ; return 0 ; } </s>

Return nonzero if X is a valid Thumb-2 address operand .


<s> Optional < DestSourcePair > MipsSEInstrInfo :: isCopyInstrImpl ( const MachineInstr & MI ) const { bool isDSPControlWrite = false ; if ( isReadOrWriteToDSPReg ( MI , isDSPControlWrite ) ) { if ( ! MI . getOperand ( 1 ) . isImm ( ) || MI . getOperand ( 1 ) . getImm ( ) != ( 1 << 4 ) ) return None ; else if ( isDSPControlWrite ) { return DestSourcePair { MI . getOperand ( 2 ) , MI . getOperand ( 0 ) } ; } else { return DestSourcePair { MI . getOperand ( 0 ) , MI . getOperand ( 2 ) } ; } } else if ( MI . isMoveReg ( ) || isORCopyInst ( MI ) ) { return DestSourcePair { MI . getOperand ( 0 ) , MI . getOperand ( 1 ) } ; } return None ; } </s>

If the specific machine instruction is a instruction that moves/copies value from one register to another register return destination and source registers as machine operands .


<s> rtx rs6000_gen_stvx ( enum machine_mode mode , rtx dest_exp , rtx src_exp ) { rtx stvx ; if ( mode == V16QImode ) stvx = gen_altivec_stvx_v16qi ( src_exp , dest_exp ) ; else if ( mode == V8HImode ) stvx = gen_altivec_stvx_v8hi ( src_exp , dest_exp ) ; else if ( mode == V8HFmode ) stvx = gen_altivec_stvx_v8hf ( src_exp , dest_exp ) ; else if ( mode == V4SImode ) stvx = gen_altivec_stvx_v4si ( src_exp , dest_exp ) ; else if ( mode == V4SFmode ) stvx = gen_altivec_stvx_v4sf ( src_exp , dest_exp ) ; else if ( mode == V2DImode ) stvx = gen_altivec_stvx_v2di ( src_exp , dest_exp ) ; else if ( mode == V2DFmode ) stvx = gen_altivec_stvx_v2df ( src_exp , dest_exp ) ; else if ( mode == V1TImode ) stvx = gen_altivec_stvx_v1ti ( src_exp , dest_exp ) ; else gcc_unreachable ( ) ; rtx new_mem_exp = SET_DEST ( PATTERN ( stvx ) ) ; mimic_memory_attributes_and_flags ( new_mem_exp , dest_exp ) ; return stvx ; } </s>

Generate an rtx expression to represent use of the stvx insn to store the value represented by register SRC_EXP into the memory at address DEST_EXP , with vector mode MODE .


<s> virtual bool isVerboseAsm ( ) const { return IsVerboseAsm ; } </s>

Return true if this streamer supports verbose assembly and if it is enabled .


"alias without a base object is not yet supported on AIX"

Set up the AsmPrinter when we are working on a new module .


<s> static rtx ix86_expand_unop_builtin ( enum insn_code icode , tree arglist , rtx target , int do_load ) { rtx pat ; tree arg0 = TREE_VALUE ( arglist ) ; rtx op0 = expand_expr ( arg0 , NULL_RTX , VOIDmode , 0 ) ; enum machine_mode tmode = insn_data [ icode ] . operand [ 0 ] . mode ; enum machine_mode mode0 = insn_data [ icode ] . operand [ 1 ] . mode ; if ( optimize || ! target || GET_MODE ( target ) != tmode || ! ( * insn_data [ icode ] . operand [ 0 ] . predicate ) ( target , tmode ) ) target = gen_reg_rtx ( tmode ) ; if ( do_load ) op0 = gen_rtx_MEM ( mode0 , copy_to_mode_reg ( Pmode , op0 ) ) ; else { if ( VECTOR_MODE_P ( mode0 ) ) op0 = safe_vector_operand ( op0 , mode0 ) ; if ( ( optimize && ! register_operand ( op0 , mode0 ) ) || ! ( * insn_data [ icode ] . operand [ 1 ] . predicate ) ( op0 , mode0 ) ) op0 = copy_to_mode_reg ( mode0 , op0 ) ; } pat = GEN_FCN ( icode ) ( target , op0 ) ; if ( ! pat ) return 0 ; emit_insn ( pat ) ; return target ; } </s>

Subroutine of ix86_expand_builtin to take care of unop insns .


<s> static void nds32_encode_section_info ( tree decl , rtx rtl , int new_decl_p ) { default_encode_section_info ( decl , rtl , new_decl_p ) ; if ( MEM_P ( rtl ) && MEM_READONLY_P ( rtl ) ) { rtx addr = XEXP ( rtl , 0 ) ; if ( GET_CODE ( addr ) == SYMBOL_REF ) { SYMBOL_REF_FLAGS ( addr ) |= NDS32_SYMBOL_FLAG_RODATA ; } else if ( GET_CODE ( addr ) == CONST && GET_CODE ( XEXP ( addr , 0 ) ) == PLUS ) { rtx plus_op = XEXP ( addr , 0 ) ; rtx op0 = XEXP ( plus_op , 0 ) ; rtx op1 = XEXP ( plus_op , 1 ) ; if ( GET_CODE ( op0 ) == SYMBOL_REF && CONST_INT_P ( op1 ) ) SYMBOL_REF_FLAGS ( op0 ) |= NDS32_SYMBOL_FLAG_RODATA ; } } } </s>

If references to a symbol or a constant must be treated differently depending on something about the variable or function named by the symbol ( such as what section it is in ) , we use this hook to store flags in symbol_ref rtx .


<s> void M88kPassConfig :: addPreRegBankSelect ( ) { addPass ( createM88kPostLegalizerLowering ( ) ) ; } </s>

This method may be implemented by targets that want to run passes immediately before the register bank selection .


<s> void print_operand_address ( FILE * file , rtx addr ) { switch ( GET_CODE ( addr ) ) { case REG : fprintf ( file , ptrreg_to_str ( REGNO ( addr ) ) ) ; break ; case PRE_DEC : fprintf ( file , "-%s" , ptrreg_to_str ( REGNO ( XEXP ( addr , 0 ) ) ) ) ; break ; case POST_INC : fprintf ( file , "%s+" , ptrreg_to_str ( REGNO ( XEXP ( addr , 0 ) ) ) ) ; break ; default : if ( CONSTANT_ADDRESS_P ( addr ) && ( ( GET_CODE ( addr ) == SYMBOL_REF && SYMBOL_REF_FUNCTION_P ( addr ) ) || GET_CODE ( addr ) == LABEL_REF ) ) { fprintf ( file , "pm(" ) ; output_addr_const ( file , addr ) ; fprintf ( file , ")" ) ; } else output_addr_const ( file , addr ) ; } } </s>

Print the operand address represented by the rtx addr


<s> static int reduce_class ( int original_class , int limiting_class , int returned_if_empty ) { int cc = class_contents [ original_class ] [ 0 ] ; int i , best = NO_REGS ; int best_size = 0 ; if ( original_class == limiting_class ) return original_class ; if ( ! class_sizes ) { int r ; class_sizes = ( int * ) xmalloc ( LIM_REG_CLASSES * sizeof ( int ) ) ; for ( i = 0 ; i < LIM_REG_CLASSES ; i ++ ) { class_sizes [ i ] = 0 ; for ( r = 0 ; r < FIRST_PSEUDO_REGISTER ; r ++ ) if ( class_contents [ i ] [ 0 ] & ( 1 << r ) ) class_sizes [ i ] ++ ; } } cc &= class_contents [ limiting_class ] [ 0 ] ; for ( i = 0 ; i < LIM_REG_CLASSES ; i ++ ) { int ic = class_contents [ i ] [ 0 ] ; if ( ( ~ cc & ic ) == 0 ) if ( best_size < class_sizes [ i ] ) { best = i ; best_size = class_sizes [ i ] ; } } if ( best == NO_REGS ) return returned_if_empty ; return best ; } </s>

Given two register classes , find the largest intersection between them . If there is no intersection , return RETURNED_IF_EMPTY instead .


<s> rtx loongarch_subword ( rtx op , bool high_p ) { unsigned int byte ; machine_mode mode ; byte = high_p ? UNITS_PER_WORD : 0 ; mode = GET_MODE ( op ) ; if ( mode == VOIDmode ) mode = TARGET_64BIT ? TImode : DImode ; if ( FP_REG_RTX_P ( op ) ) return gen_rtx_REG ( word_mode , REGNO ( op ) + high_p ) ; if ( MEM_P ( op ) ) return loongarch_rewrite_small_data ( adjust_address ( op , word_mode , byte ) ) ; return simplify_gen_subreg ( word_mode , op , mode , byte ) ; } </s>

Return one word of double-word value OP , taking into account the fixed endianness of certain registers . HIGH_P is true to select the high part , false to select the low part .


<s> BitVector PPCRegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; Reserved . set ( PPC :: R0 ) ; Reserved . set ( PPC :: R1 ) ; Reserved . set ( PPC :: LR ) ; Reserved . set ( PPC :: LR8 ) ; Reserved . set ( PPC :: RM ) ; if ( Subtarget . isSVR4ABI ( ) ) { Reserved . set ( PPC :: R2 ) ; Reserved . set ( PPC :: R13 ) ; } if ( Subtarget . isPPC64 ( ) ) { Reserved . set ( PPC :: R13 ) ; Reserved . set ( PPC :: R31 ) ; if ( ! EnableRegisterScavenging ) Reserved . set ( PPC :: R0 ) ; Reserved . set ( PPC :: X0 ) ; Reserved . set ( PPC :: X1 ) ; Reserved . set ( PPC :: X13 ) ; Reserved . set ( PPC :: X31 ) ; if ( Subtarget . isSVR4ABI ( ) ) { Reserved . set ( PPC :: X2 ) ; } } if ( needsFP ( MF ) ) Reserved . set ( PPC :: R31 ) ; return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s> const char * iq2000_fill_delay_slot ( const char * ret , enum delay_type type , rtx operands [ ] , rtx_insn * cur_insn ) { rtx set_reg ; machine_mode mode ; rtx_insn * next_insn = cur_insn ? NEXT_INSN ( cur_insn ) : NULL ; int num_nops ; if ( type == DELAY_LOAD || type == DELAY_FCMP ) num_nops = 1 ; else num_nops = 0 ; next_insn = NEXT_INSN ( cur_insn ) ; while ( next_insn != 0 && ( NOTE_P ( next_insn ) || LABEL_P ( next_insn ) ) ) next_insn = NEXT_INSN ( next_insn ) ; dslots_load_total += num_nops ; if ( TARGET_DEBUG_C_MODE || type == DELAY_NONE || operands == 0 || cur_insn == 0 || next_insn == 0 || LABEL_P ( next_insn ) || ( set_reg = operands [ 0 ] ) == 0 ) { dslots_number_nops = 0 ; iq2000_load_reg = 0 ; iq2000_load_reg2 = 0 ; iq2000_load_reg3 = 0 ; iq2000_load_reg4 = 0 ; return ret ; } set_reg = operands [ 0 ] ; if ( set_reg == 0 ) return ret ; while ( GET_CODE ( set_reg ) == SUBREG ) set_reg = SUBREG_REG ( set_reg ) ; mode = GET_MODE ( set_reg ) ; dslots_number_nops = num_nops ; iq2000_load_reg = set_reg ; if ( GET_MODE_SIZE ( mode ) > ( unsigned ) ( UNITS_PER_WORD ) ) iq2000_load_reg2 = gen_rtx_REG ( SImode , REGNO ( set_reg ) + 1 ) ; else iq2000_load_reg2 = 0 ; return ret ; } </s>

Returns an operand string for the given instruction 's delay slot , after updating filled delay slot statistics . We assume that operands [ 0 ] is the target register that is set . In order to check the next insn , most of this functionality is moved to FINAL_PRESCAN_INSN , and we just set the global variables that it needs .


<s> bool runOnMachineFunction ( MachineFunction & MF ) override { if ( skipFunction ( MF . getFunction ( ) ) ) return false ; TII = MF . getSubtarget ( ) . getInstrInfo ( ) ; bool Changed = false ; if ( MF . size ( ) < 2 ) return Changed ; for ( MachineFunction :: iterator I = MF . begin ( ) , E = MF . end ( ) ; I != E ; ) { MachineBasicBlock & B = * I ++ ; Changed |= processBlock ( B ) ; } return Changed ; } </s>

runOnMachineFunction - Emit the function body .


<s>
bool
AMDGPUAnnotateKernelFeatures
::
doInitialization
(
CallGraph
&
CG
)
{
auto
*
TPC
=
getAnalysisIfAvailable
<
TargetPassConfig
>
(
)
;
if
(
!
TPC
)
report_fatal_error
(
"TargetMachine is required"
)
;
TM
=
&
TPC
->
getTM
<
TargetMachine
>
(
)
;
return
false
;
}
</s>

AMDGPU
AMDGPU
"TargetMachine is required"


<s> static bool aarch64_if_then_else_costs ( rtx op0 , rtx op1 , rtx op2 , int * cost , bool speed ) { rtx inner ; rtx comparator ; enum rtx_code cmpcode ; if ( COMPARISON_P ( op0 ) ) { inner = XEXP ( op0 , 0 ) ; comparator = XEXP ( op0 , 1 ) ; cmpcode = GET_CODE ( op0 ) ; } else { inner = op0 ; comparator = const0_rtx ; cmpcode = NE ; } if ( GET_CODE ( op1 ) == PC || GET_CODE ( op2 ) == PC ) { if ( GET_MODE_CLASS ( GET_MODE ( inner ) ) == MODE_CC ) return true ; else { if ( cmpcode == NE || cmpcode == EQ ) { if ( comparator == const0_rtx ) { if ( GET_CODE ( inner ) == ZERO_EXTRACT ) * cost += rtx_cost ( XEXP ( inner , 0 ) , ZERO_EXTRACT , 0 , speed ) ; else * cost += rtx_cost ( inner , cmpcode , 0 , speed ) ; return true ; } } else if ( cmpcode == LT || cmpcode == GE ) { if ( comparator == const0_rtx ) return true ; } } } else if ( GET_MODE_CLASS ( GET_MODE ( inner ) ) == MODE_CC ) { if ( GET_CODE ( op1 ) == NEG || GET_CODE ( op1 ) == NOT || ( GET_CODE ( op1 ) == PLUS && XEXP ( op1 , 1 ) == const1_rtx ) ) op1 = XEXP ( op1 , 0 ) ; * cost += rtx_cost ( op1 , IF_THEN_ELSE , 1 , speed ) ; * cost += rtx_cost ( op2 , IF_THEN_ELSE , 2 , speed ) ; return true ; } return false ; } </s>

Calculate the cost of calculating ( if_then_else ( OP0 ) ( OP1 ) ( OP2 ) ) , storing it in * COST . Result is true if the total cost of the operation has now been calculated .


<s> static void arm_option_params_internal ( void ) { if ( TARGET_THUMB1 ) { targetm . min_anchor_offset = 0 ; targetm . max_anchor_offset = 127 ; } else if ( TARGET_THUMB2 ) { targetm . min_anchor_offset = - 248 ; targetm . max_anchor_offset = 4095 ; } else { targetm . min_anchor_offset = TARGET_MIN_ANCHOR_OFFSET ; targetm . max_anchor_offset = TARGET_MAX_ANCHOR_OFFSET ; } if ( optimize_size ) { max_insns_skipped = 6 ; if ( TARGET_THUMB2 ) max_insns_skipped = arm_restrict_it ? 1 : 4 ; } else max_insns_skipped = ( TARGET_THUMB2 && arm_restrict_it ) ? 1 : current_tune -> max_insns_skipped ; } </s>

Recompute the global settings depending on target attribute options .


<s> int ft32_initial_elimination_offset ( int from , int to ) { ft32_compute_frame ( ) ; if ( from == ARG_POINTER_REGNUM && to == FRAME_POINTER_REGNUM ) { return cfun -> machine -> callee_saved_reg_size + 2 * UNITS_PER_WORD ; } if ( from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM ) { int arg_offset ; arg_offset = must_link ( ) ? 2 : 1 ; return ( ( cfun -> machine -> callee_saved_reg_size + arg_offset * UNITS_PER_WORD ) + cfun -> machine -> size_for_adjusting_sp ) ; } if ( ( from == FRAME_POINTER_REGNUM ) && ( to == STACK_POINTER_REGNUM ) ) { return cfun -> machine -> size_for_adjusting_sp ; } gcc_unreachable ( ) ; } </s>

Implements the macro INITIAL_ELIMINATION_OFFSET , return the OFFSET .


<s>
void
X86AsmBackend
::
relaxInstruction
(
const
MCInst
&
Inst
,
MCInst
&
Res
)
const
{
unsigned
RelaxedOp
=
getRelaxedOpcode
(
Inst
.
getOpcode
(
)
)
;
if
(
RelaxedOp
==
Inst
.
getOpcode
(
)
)
{
SmallString
<
256
>
Tmp
;
raw_svector_ostream
OS
(
Tmp
)
;
Inst
.
dump_pretty
(
OS
)
;
OS
<<
"\n"
;
report_fatal_error
(
"unexpected instruction to relax: "
+
OS
.
str
(
)
)
;
}
Res
=
Inst
;
Res
.
setOpcode
(
RelaxedOp
)
;
}
</s>

Relax the instruction in the given fragment to the next wider instruction .


<s> bool SILowerControlFlowPass :: runOnMachineFunction ( MachineFunction & MF ) { TII = MF . getTarget ( ) . getInstrInfo ( ) ; TRI = MF . getTarget ( ) . getRegisterInfo ( ) ; bool HaveKill = false ; bool NeedM0 = false ; bool NeedWQM = false ; unsigned Depth = 0 ; for ( MachineFunction :: iterator BI = MF . begin ( ) , BE = MF . end ( ) ; BI != BE ; ++ BI ) { MachineBasicBlock & MBB = * BI ; for ( MachineBasicBlock :: iterator I = MBB . begin ( ) , Next = llvm :: next ( I ) ; I != MBB . end ( ) ; I = Next ) { Next = llvm :: next ( I ) ; MachineInstr & MI = * I ; switch ( MI . getOpcode ( ) ) { default : break ; case AMDGPU :: SI_IF : ++ Depth ; If ( MI ) ; break ; case AMDGPU :: SI_ELSE : Else ( MI ) ; break ; case AMDGPU :: SI_BREAK : Break ( MI ) ; break ; case AMDGPU :: SI_IF_BREAK : IfBreak ( MI ) ; break ; case AMDGPU :: SI_ELSE_BREAK : ElseBreak ( MI ) ; break ; case AMDGPU :: SI_LOOP : ++ Depth ; Loop ( MI ) ; break ; case AMDGPU :: SI_END_CF : if ( -- Depth == 0 && HaveKill ) { SkipIfDead ( MI ) ; HaveKill = false ; } EndCf ( MI ) ; break ; case AMDGPU :: SI_KILL : if ( Depth == 0 ) SkipIfDead ( MI ) ; else HaveKill = true ; Kill ( MI ) ; break ; case AMDGPU :: S_BRANCH : Branch ( MI ) ; break ; case AMDGPU :: SI_INDIRECT_SRC : IndirectSrc ( MI ) ; break ; case AMDGPU :: SI_INDIRECT_DST_V2 : case AMDGPU :: SI_INDIRECT_DST_V4 : case AMDGPU :: SI_INDIRECT_DST_V8 : case AMDGPU :: SI_INDIRECT_DST_V16 : IndirectDst ( MI ) ; break ; case AMDGPU :: DS_READ_B32 : NeedWQM = true ; case AMDGPU :: DS_WRITE_B32 : NeedM0 = true ; break ; case AMDGPU :: V_INTERP_P1_F32 : case AMDGPU :: V_INTERP_P2_F32 : case AMDGPU :: V_INTERP_MOV_F32 : NeedWQM = true ; break ; } } } if ( NeedM0 ) { MachineBasicBlock & MBB = MF . front ( ) ; BuildMI ( MBB , MBB . getFirstNonPHI ( ) , DebugLoc ( ) , TII -> get ( AMDGPU :: S_MOV_B32 ) , AMDGPU :: M0 ) . addImm ( 0xffffffff ) ; } if ( NeedWQM ) { MachineBasicBlock & MBB = MF . front ( ) ; BuildMI ( MBB , MBB . getFirstNonPHI ( ) , DebugLoc ( ) , TII -> get ( AMDGPU :: S_WQM_B64 ) , AMDGPU :: EXEC ) . addReg ( AMDGPU :: EXEC ) ; } return true ; } </s>

R600 SI 0 SI SI SI SI SI SI SI 0 SI 0 SI SI SI SI SI 0xffffffff


<s> void CJGInstrInfo :: loadRegFromStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , unsigned DestReg , int FrameIdx , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { DebugLoc DL ; if ( MI != MBB . end ( ) ) DL = MI -> getDebugLoc ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; BuildMI ( MBB , MI , DL , get ( CJG :: POP ) ) . addReg ( DestReg , getDefRegState ( true ) ) ; } </s>

Load the specified register of the given register class from the specified stack frame index .


<s> static const char * mips_sync_insn1_template ( enum attr_sync_insn1 type , bool is_64bit_p ) { switch ( type ) { case SYNC_INSN1_MOVE : return "move\t%0,%z2" ; case SYNC_INSN1_LI : return "li\t%0,%2" ; case SYNC_INSN1_ADDU : return is_64bit_p ? "daddu\t%0,%1,%z2" : "addu\t%0,%1,%z2" ; case SYNC_INSN1_ADDIU : return is_64bit_p ? "daddiu\t%0,%1,%2" : "addiu\t%0,%1,%2" ; case SYNC_INSN1_SUBU : return is_64bit_p ? "dsubu\t%0,%1,%z2" : "subu\t%0,%1,%z2" ; case SYNC_INSN1_AND : return "and\t%0,%1,%z2" ; case SYNC_INSN1_ANDI : return "andi\t%0,%1,%2" ; case SYNC_INSN1_OR : return "or\t%0,%1,%z2" ; case SYNC_INSN1_ORI : return "ori\t%0,%1,%2" ; case SYNC_INSN1_XOR : return "xor\t%0,%1,%z2" ; case SYNC_INSN1_XORI : return "xori\t%0,%1,%2" ; } gcc_unreachable ( ) ; } </s>

Return the asm template associated with sync_insn1 value TYPE . IS_64BIT_P is true if we want a 64-bit rather than 32-bit operation .


<s> const MCExpr * PPC64LinuxTargetObjectFile :: getDebugThreadLocalSymbol ( const MCSymbol * Sym ) const { const MCExpr * Expr = MCSymbolRefExpr :: Create ( Sym , MCSymbolRefExpr :: VK_PPC_DTPREL , getContext ( ) ) ; return MCBinaryExpr :: CreateAdd ( Expr , MCConstantExpr :: Create ( 0x8000 , getContext ( ) ) , getContext ( ) ) ; } </s>

Describe a TLS variable address within debug info .


<s>
ScheduleHazardRecognizer
*
PPCInstrInfo
::
CreateTargetHazardRecognizer
(
const
TargetMachine
*
TM
,
const
ScheduleDAG
*
DAG
)
const
{
const
TargetInstrInfo
*
TII
=
TM
->
getInstrInfo
(
)
;
(
void
)
TII
;
assert
(
TII
&&
"No InstrInfo?"
)
;
unsigned
Directive
=
TM
->
getSubtarget
<
PPCSubtarget
>
(
)
.
getDarwinDirective
(
)
;
if
(
Directive
==
PPC
::
DIR_440
)
{
const
InstrItineraryData
*
II
=
TM
->
getInstrItineraryData
(
)
;
return
new
PPCHazardRecognizer440
(
II
,
DAG
)
;
}
else
{
return
new
ScheduleHazardRecognizer
(
)
;
}
}
</s>

Allocate and return a hazard recognizer to use for this target when scheduling the machine instructions before register allocation .

PowerPC
PPC
"No InstrInfo?"
PPC
PPC::DIR_440
PPC


<s> static bool arm_function_ok_for_sibcall ( tree decl , tree exp ) { unsigned long func_type ; if ( cfun -> machine -> sibcall_blocked ) return false ; if ( TARGET_THUMB1 ) return false ; if ( TARGET_VXWORKS_RTP && flag_pic && ! targetm . binds_local_p ( decl ) ) return false ; if ( TARGET_INTERWORK && decl && TREE_PUBLIC ( decl ) && ! TREE_ASM_WRITTEN ( decl ) ) return false ; func_type = arm_current_func_type ( ) ; if ( IS_INTERRUPT ( func_type ) ) return false ; if ( ! VOID_TYPE_P ( TREE_TYPE ( DECL_RESULT ( cfun -> decl ) ) ) ) { rtx a , b ; tree decl_or_type = decl ; if ( ! decl ) decl_or_type = TREE_TYPE ( TREE_TYPE ( CALL_EXPR_FN ( exp ) ) ) ; a = arm_function_value ( TREE_TYPE ( exp ) , decl_or_type , false ) ; b = arm_function_value ( TREE_TYPE ( DECL_RESULT ( cfun -> decl ) ) , cfun -> decl , false ) ; if ( ! rtx_equal_p ( a , b ) ) return false ; } if ( IS_STACKALIGN ( func_type ) ) return false ; if ( TARGET_AAPCS_BASED && arm_abi == ARM_ABI_AAPCS && decl && DECL_WEAK ( decl ) ) return false ; return true ; } </s>

Return non-zero if it is ok to make a tail-call to DECL .


<s>
const
MCFixupKindInfo
&
P2AsmBackend
::
getFixupKindInfo
(
MCFixupKind
Kind
)
const
{
const
static
MCFixupKindInfo
Infos
[
P2
::
NumTargetFixupKinds
]
=
{
{
"fixup_P2_32"
,
0
,
32
,
0
}
,
{
"fixup_P2_PC32"
,
0
,
32
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_P2_20"
,
0
,
20
,
0
}
,
{
"fixup_P2_PC20"
,
0
,
20
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_P2_AUG20"
,
0
,
20
,
0
}
,
{
"fixup_P2_COG9"
,
0
,
9
,
0
}
}
;
if
(
Kind
<
FirstTargetFixupKind
)
return
MCAsmBackend
::
getFixupKindInfo
(
Kind
)
;
assert
(
unsigned
(
Kind
FirstTargetFixupKind
)
<
getNumFixupKinds
(
)
&&
"Invalid kind!"
)
;
return
Infos
[
Kind
FirstTargetFixupKind
]
;
}
</s>