<s>
void
ARMTargetStreamer
::
emitInst
(
uint32_t
Inst
,
char
Suffix
)
{
unsigned
Size
;
char
Buffer
[
4
]
;
const
bool
LittleEndian
=
getStreamer
(
)
.
getContext
(
)
.
getAsmInfo
(
)
->
isLittleEndian
(
)
;
switch
(
Suffix
)
{
case
'\0'
:
Size
=
4
;
for
(
unsigned
II
=
0
,
IE
=
Size
;
II
!=
IE
;
II
++
)
{
const
unsigned
I
=
LittleEndian
(
Size
II
1
)
:
II
;
Buffer
[
Size
II
1
]
=
uint8_t
(
Inst
>>
I
*
CHAR_BIT
)
;
}
break
;
case
'n'
:
case
'w'
:
Size
=
(
Suffix
==
'n'
2
:
4
)
;
for
(
unsigned
II
=
0
,
IE
=
Size
;
II
!=
IE
;
II
=
II
+
2
)
{
const
unsigned
I0
=
LittleEndian
II
+
0
:
II
+
1
;
const
unsigned
I1
=
LittleEndian
II
+
1
:
II
+
0
;
Buffer
[
Size
II
2
]
=
uint8_t
(
Inst
>>
I0
*
CHAR_BIT
)
;
Buffer
[
Size
II
1
]
=
uint8_t
(
Inst
>>
I1
*
CHAR_BIT
)
;
}
break
;
default
:
llvm_unreachable
(
"Invalid Suffix"
)
;
}
getStreamer
(
)
.
EmitBytes
(
StringRef
(
Buffer
,
Size
)
)
;
}
</s>

Callback used to implement the .inst directive .


<s> void ARMPassConfig :: addPreSched2 ( ) { if ( getOptLevel ( ) != CodeGenOpt :: None ) { if ( EnableARMLoadStoreOpt ) addPass ( createARMLoadStoreOptimizationPass ( ) ) ; addPass ( createExecutionDependencyFixPass ( & ARM :: DPRRegClass ) ) ; } addPass ( createARMExpandPseudoPass ( ) ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) { if ( getARMSubtarget ( ) . restrictIT ( ) ) addPass ( createThumb2SizeReductionPass ( ) ) ; if ( ! getARMSubtarget ( ) . isThumb1Only ( ) ) addPass ( & IfConverterID ) ; } addPass ( createThumb2ITBlockPass ( ) ) ; } </s>

This method may be implemented by targets that want to run passes after prolog-epilog insertion and before the second instruction scheduling pass .

ARM ARM ARM ARM ARM::DPRRegClass ARM ARM ARM


<s> bool SparcFrameLowering :: hasFP ( const MachineFunction & MF ) const { const TargetRegisterInfo * RegInfo = MF . getSubtarget ( ) . getRegisterInfo ( ) ; const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; return MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) || RegInfo -> needsStackRealignment ( MF ) || MFI . hasVarSizedObjects ( ) || MFI . isFrameAddressTaken ( ) ; } </s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .


<s> bool runOnModule ( Module & M ) override { UsedList = AMDGPU :: getUsedList ( M ) ; bool Changed = processUsedLDS ( M ) ; for ( Function & F : M . functions ( ) ) { if ( ! AMDGPU :: isKernel ( F . getCallingConv ( ) ) ) continue ; Changed |= processUsedLDS ( M , & F ) ; } UsedList . clear ( ) ; return Changed ; } </s>

runOnModule - Virtual method overriden by subclasses to process the module being operated on .


<s> bool X86FrameLowering :: hasFP ( const MachineFunction & MF ) const { const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; return ( MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) || TRI -> needsStackRealignment ( MF ) || MFI . hasVarSizedObjects ( ) || MFI . isFrameAddressTaken ( ) || MFI . hasOpaqueSPAdjustment ( ) || MF . getInfo < X86MachineFunctionInfo > ( ) -> getForceFramePointer ( ) || MF . callsUnwindInit ( ) || MF . hasEHFunclets ( ) || MF . callsEHReturn ( ) || MFI . hasStackMap ( ) || MFI . hasPatchPoint ( ) || MFI . hasCopyImplyingStackAdjustment ( ) ) ; } </s>


<s> unsigned ARMBaseInstrInfo :: extraSizeToPredicateInstructions ( const MachineFunction & MF , unsigned NumInsts ) const { return Subtarget . isThumb2 ( ) ? divideCeil ( NumInsts , 4 ) * 2 : 0 ; } </s>

Return the increase in code size needed to predicate a contiguous run of NumInsts instructions .


<s> static void * mingw32_gt_pch_get_address ( size_t size , int ) { void * res ; size = ( size + va_granularity - 1 ) & ~ ( va_granularity - 1 ) ; if ( size > pch_VA_max_size ) return NULL ; res = VirtualAlloc ( NULL , pch_VA_max_size , MEM_RESERVE | MEM_TOP_DOWN , PAGE_NOACCESS ) ; if ( ! res ) w32_error ( __FUNCTION__ , __FILE__ , __LINE__ , "VirtualAlloc" ) ; else VirtualFree ( res , 0 , MEM_RELEASE ) ; return res ; } </s>

Identify an address that 's likely to be free in a subsequent invocation of the compiler . The area should be able to hold SIZE bytes . FD is an open file descriptor if the host would like to probe with mmap .


<s> static MachineInstr * findLoopInstr ( MachineBasicBlock * BB , int EndLoopOp , SmallPtrSet < MachineBasicBlock * , 8 > & Visited ) { int LOOPi ; int LOOPr ; if ( EndLoopOp == Hexagon :: ENDLOOP0 ) { LOOPi = Hexagon :: J2_loop0i ; LOOPr = Hexagon :: J2_loop0r ; } else { LOOPi = Hexagon :: J2_loop1i ; LOOPr = Hexagon :: J2_loop1r ; } for ( MachineBasicBlock :: pred_iterator PB = BB -> pred_begin ( ) , PE = BB -> pred_end ( ) ; PB != PE ; ++ PB ) { if ( ! Visited . insert ( * PB ) . second ) continue ; if ( * PB == BB ) continue ; for ( MachineBasicBlock :: reverse_instr_iterator I = ( * PB ) -> instr_rbegin ( ) , E = ( * PB ) -> instr_rend ( ) ; I != E ; ++ I ) { int Opc = I -> getOpcode ( ) ; if ( Opc == LOOPi || Opc == LOOPr ) return & * I ; if ( Opc == EndLoopOp ) return nullptr ; } MachineInstr * loop = findLoopInstr ( * PB , EndLoopOp , Visited ) ; if ( loop ) return loop ; } return nullptr ; } </s>

Find the hardware loop instruction used to set-up the specified loop .


runOnMachineFunction - Emit the function body .


<s> virtual const MandarinRegisterInfo * getRegisterInfo ( ) const { return & InstrInfo . getRegisterInfo ( ) ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


"selected fp16 options are incompatible"

Reconfigure global status flags from the active_target.isa .


<s> static void loongarch_va_start ( tree valist , rtx nextarg ) { nextarg = plus_constant ( Pmode , nextarg , - cfun -> machine -> varargs_size ) ; std_expand_builtin_va_start ( valist , nextarg ) ; } </s>


<s> const Region * getRegionFor ( const MachineBasicBlock * MBB ) { const auto * ML = MLI . getLoopFor ( MBB ) ; const auto * WE = WEI . getExceptionFor ( MBB ) ; if ( ! ML && ! WE ) return nullptr ; if ( ( ML && ! WE ) || ( ML && WE && WE -> contains ( ML -> getHeader ( ) ) ) ) { if ( LoopMap . count ( ML ) ) return LoopMap [ ML ] . get ( ) ; LoopMap [ ML ] = std :: make_unique < ConcreteRegion < MachineLoop >> ( ML ) ; return LoopMap [ ML ] . get ( ) ; } else { if ( ExceptionMap . count ( WE ) ) return ExceptionMap [ WE ] . get ( ) ; ExceptionMap [ WE ] = std :: make_unique < ConcreteRegion < WebAssemblyException >> ( WE ) ; return ExceptionMap [ WE ] . get ( ) ; } } </s>

Get the smallest region that contains a BasicBlock .


<s> bool SITargetLowering :: allowsMisalignedMemoryAccesses ( EVT VT , unsigned AddrSpace , unsigned Align , bool * IsFast ) const { if ( IsFast ) * IsFast = false ; if ( VT == MVT :: Other || ( VT != MVT :: Other && VT . getSizeInBits ( ) > 1024 && VT . getStoreSize ( ) > 16 ) ) { return false ; } if ( AddrSpace == AMDGPUAS :: LOCAL_ADDRESS || AddrSpace == AMDGPUAS :: REGION_ADDRESS ) { bool AlignedBy4 = ( Align % 4 == 0 ) ; if ( IsFast ) * IsFast = AlignedBy4 ; return AlignedBy4 ; } if ( ! Subtarget -> hasUnalignedScratchAccess ( ) && ( AddrSpace == AMDGPUAS :: PRIVATE_ADDRESS || AddrSpace == AMDGPUAS :: FLAT_ADDRESS ) ) { bool AlignedBy4 = Align >= 4 ; if ( IsFast ) * IsFast = AlignedBy4 ; return AlignedBy4 ; } if ( Subtarget -> hasUnalignedBufferAccess ( ) ) { if ( IsFast ) { * IsFast = ( AddrSpace == AMDGPUAS :: CONSTANT_ADDRESS || AddrSpace == AMDGPUAS :: CONSTANT_ADDRESS_32BIT ) ? ( Align % 4 == 0 ) : true ; } return true ; } if ( VT . bitsLT ( MVT :: i32 ) ) return false ; if ( IsFast ) * IsFast = true ; return VT . bitsGT ( MVT :: i32 ) && Align % 4 == 0 ; } </s>

Returns true if the target allows unaligned memory accesses of the specified type .


" was Pass-through, is now Dirty-out.\n"


<s>
static
void
mips_output_cplocal
(
void
)
{
if
(
!
TARGET_EXPLICIT_RELOCS
&&
mips_must_initialize_gp_p
(
)
&&
cfun
->
machine
->
global_pointer
!=
GLOBAL_POINTER_REGNUM
)
output_asm_insn
(
".cplocal %+"
,
0
)
;
}
</s>

If we 're generating n32 or n64 abicalls , and the current function does not use $ 28 as its global pointer , emit a cplocal directive . Use pic_offset_table_rtx as the argument to the directive .


<s>
bool
PIC16AsmPrinter
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
SetupMachineFunction
(
MF
)
;
const
Function
*
F
=
MF
.
getFunction
(
)
;
ColorAutoSection
(
F
)
;
EmitFunctionFrame
(
MF
)
;
DbgInfo
.
BeginFunction
(
MF
)
;
const
MCSection
*
fCodeSection
=
getObjFileLowering
(
)
.
SectionForCode
(
CurrentFnSym
->
getName
(
)
,
PAN
::
isISR
(
F
->
getSection
(
)
)
)
;
O
<<
"\n"
;
OutStreamer
.
SwitchSection
(
fCodeSection
)
;
O
<<
"\tretlw  low("
<<
PAN
::
getFrameLabel
(
CurrentFnSym
->
getName
(
)
)
<<
")\n"
;
O
<<
"\tretlw  high("
<<
PAN
::
getFrameLabel
(
CurrentFnSym
->
getName
(
)
)
<<
")\n"
;
O
<<
*
CurrentFnSym
<<
":\n"
;
DebugLoc
CurDL
;
O
<<
"\n"
;
for
(
MachineFunction
::
const_iterator
I
=
MF
.
begin
(
)
,
E
=
MF
.
end
(
)
;
I
!=
E
;
++
I
)
{
if
(
I
!=
MF
.
begin
(
)
)
{
EmitBasicBlockStart
(
I
)
;
}
for
(
MachineBasicBlock
::
const_iterator
II
=
I
->
begin
(
)
,
E
=
I
->
end
(
)
;
II
!=
E
;
++
II
)
{
const
DebugLoc
DL
=
II
->
getDebugLoc
(
)
;
if
(
!
DL
.
isUnknown
(
)
&&
DL
!=
CurDL
)
{
DbgInfo
.
ChangeDebugLoc
(
MF
,
DL
)
;
CurDL
=
DL
;
}
EmitInstruction
(
II
)
;
}
}
DbgInfo
.
EndFunction
(
MF
)
;
return
false
;
}
</s>

PIC16
PIC16
"\n"
"\tretlw  low("
")\n"
"\tretlw  high("
")\n"
":\n"
"\n"


<s> bool runOnMachineFunction ( MachineFunction & F ) override { TM = & F . getTarget ( ) ; bool Changed = false ; for ( MachineBasicBlock & MBB : F ) Changed |= runOnMachineBasicBlock ( MBB ) ; if ( Changed ) F . getRegInfo ( ) . invalidateLiveness ( ) ; return Changed ; } </s>


<s> bool XNCMFrameLowering :: hasReservedCallFrame ( const MachineFunction & MF ) const { return ! MF . getFrameInfo ( ) -> hasVarSizedObjects ( ) ; } </s>

hasReservedCallFrame - Under normal circumstances , when a frame pointer is not required , we reserve argument space for call sites in the function immediately on entry to the current function .


<s> unsigned char AArch64Subtarget :: ClassifyGlobalReference ( const GlobalValue * GV , const TargetMachine & TM ) const { bool isDecl = GV -> isDeclarationForLinker ( ) ; if ( TM . getCodeModel ( ) == CodeModel :: Large && isTargetMachO ( ) ) return AArch64II :: MO_GOT ; if ( TM . getCodeModel ( ) == CodeModel :: Small && GV -> isWeakForLinker ( ) && isDecl ) { if ( TM . getRelocationModel ( ) == Reloc :: Static ) return AArch64II :: MO_CONSTPOOL ; else return AArch64II :: MO_GOT ; } if ( TM . getRelocationModel ( ) != Reloc :: Static && GV -> hasDefaultVisibility ( ) ) { if ( isTargetMachO ( ) ) return ( isDecl || GV -> isWeakForLinker ( ) ) ? AArch64II :: MO_GOT : AArch64II :: MO_NO_FLAG ; else return GV -> hasLocalLinkage ( ) ? AArch64II :: MO_NO_FLAG : AArch64II :: MO_GOT ; } return AArch64II :: MO_NO_FLAG ; } </s>

ClassifyGlobalReference - Find the target operand flags that describe how a global value should be referenced for the current subtarget .


<s> bool RISCVAsmPrinter :: PrintAsmOperand ( const MachineInstr * MI , unsigned OpNo , unsigned AsmVariant , const char * ExtraCode , raw_ostream & OS ) { if ( ExtraCode && * ExtraCode == 'n' ) { if ( ! MI -> getOperand ( OpNo ) . isImm ( ) ) return true ; OS << - int64_t ( MI -> getOperand ( OpNo ) . getImm ( ) ) ; } else { printOperand ( MI , OpNo , OS ) ; } return false ; } </s>

PrintAsmOperand - Print out an operand for an inline asm expression .


<s> unsigned X86TargetLowering :: getNumRegistersForCallingConv ( LLVMContext & Context , CallingConv :: ID CC , EVT VT ) const { if ( VT == MVT :: v32i1 && Subtarget . hasAVX512 ( ) && ! Subtarget . hasBWI ( ) ) return 1 ; if ( VT . isVector ( ) && VT . getVectorElementType ( ) == MVT :: i1 && Subtarget . hasAVX512 ( ) && ( ! isPowerOf2_32 ( VT . getVectorNumElements ( ) ) || ( VT . getVectorNumElements ( ) > 16 && ! Subtarget . hasBWI ( ) ) || ( VT . getVectorNumElements ( ) > 64 && Subtarget . hasBWI ( ) ) ) ) return VT . getVectorNumElements ( ) ; if ( VT == MVT :: v64i1 && Subtarget . hasBWI ( ) && ! Subtarget . useAVX512Regs ( ) && CC != CallingConv :: X86_RegCall ) return 2 ; if ( ( VT == MVT :: v32i16 || VT == MVT :: v64i8 ) && ! EnableOldKNLABI && Subtarget . useAVX512Regs ( ) && ! Subtarget . hasBWI ( ) ) return 1 ; return TargetLowering :: getNumRegistersForCallingConv ( Context , CC , VT ) ; } </s>

Certain targets require unusual breakdowns of certain types .


<s> bool X86InstrInfo :: classifyLEAReg ( MachineInstr & MI , const MachineOperand & Src , unsigned Opc , bool AllowSP , unsigned & NewSrc , bool & isKill , bool & isUndef , MachineOperand & ImplicitOp ) const { MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ; const TargetRegisterClass * RC ; if ( AllowSP ) { RC = Opc != X86 :: LEA32r ? & X86 :: GR64RegClass : & X86 :: GR32RegClass ; } else { RC = Opc != X86 :: LEA32r ? & X86 :: GR64_NOSPRegClass : & X86 :: GR32_NOSPRegClass ; } unsigned SrcReg = Src . getReg ( ) ; if ( Opc != X86 :: LEA64_32r ) { NewSrc = SrcReg ; isKill = Src . isKill ( ) ; isUndef = Src . isUndef ( ) ; if ( TargetRegisterInfo :: isVirtualRegister ( NewSrc ) && ! MF . getRegInfo ( ) . constrainRegClass ( NewSrc , RC ) ) return false ; return true ; } if ( TargetRegisterInfo :: isPhysicalRegister ( SrcReg ) ) { ImplicitOp = Src ; ImplicitOp . setImplicit ( ) ; NewSrc = getX86SubSuperRegister ( Src . getReg ( ) , 64 ) ; isKill = Src . isKill ( ) ; isUndef = Src . isUndef ( ) ; } else { NewSrc = MF . getRegInfo ( ) . createVirtualRegister ( RC ) ; BuildMI ( * MI . getParent ( ) , MI , MI . getDebugLoc ( ) , get ( TargetOpcode :: COPY ) ) . addReg ( NewSrc , RegState :: Define | RegState :: Undef , X86 :: sub_32bit ) . addOperand ( Src ) ; isKill = true ; isUndef = false ; } return true ; } </s>

Given an operand within a MachineInstr , insert preceding code to put it into the right format for a particular kind of LEA instruction .


<s> bool X86TargetMachine :: addPostRegAlloc ( PassManagerBase & PM , bool Fast ) { PM . add ( createX86FloatingPointStackifierPass ( ) ) ; return true ; } </s>

This method may be implemented by targets that want to run passes after register allocation pass pipeline but before prolog-epilog insertion .


<s> static bool aarch64_legitimate_address_hook_p ( machine_mode mode , rtx x , bool strict_p ) { struct aarch64_address_info addr ; return aarch64_classify_address ( & addr , x , mode , strict_p ) ; } </s>

Return TRUE if X is a legitimate address for accessing memory in mode MODE .


<s> TargetLowering :: AtomicExpansionKind SITargetLowering :: shouldExpandAtomicLoadInIR ( LoadInst * LI ) const { return LI -> getPointerAddressSpace ( ) == AMDGPUAS :: PRIVATE_ADDRESS ? AtomicExpansionKind :: NotAtomic : AtomicExpansionKind :: None ; } </s>

Returns how the given ( atomic ) load should be expanded by the IR-level AtomicExpand pass .


<s> const MCPhysReg * M680x0RegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { return CSR_STD_SaveList ; } </s>


"DLX DAG->DAG Pattern Instruction Selection"

getPassName - Return a nice clean name for a pass .


<s> bool HexagonCopyToCombine :: runOnMachineFunction ( MachineFunction & MF ) { if ( skipFunction ( MF . getFunction ( ) ) ) return false ; if ( IsCombinesDisabled ) return false ; bool HasChanged = false ; ST = & MF . getSubtarget < HexagonSubtarget > ( ) ; TRI = ST -> getRegisterInfo ( ) ; TII = ST -> getInstrInfo ( ) ; const Function & F = MF . getFunction ( ) ; bool OptForSize = F . hasFnAttribute ( Attribute :: OptimizeForSize ) ; ShouldCombineAggressively = MF . getTarget ( ) . getOptLevel ( ) <= CodeGenOpt :: Default ; if ( ! OptForSize && ST -> isTinyCore ( ) ) IsConst64Disabled = true ; for ( MachineFunction :: iterator BI = MF . begin ( ) , BE = MF . end ( ) ; BI != BE ; ++ BI ) { PotentiallyNewifiableTFR . clear ( ) ; findPotentialNewifiableTFRs ( * BI ) ; for ( MachineBasicBlock :: iterator MI = BI -> begin ( ) , End = BI -> end ( ) ; MI != End ; ) { MachineInstr & I1 = * MI ++ ; if ( I1 . isDebugInstr ( ) ) continue ; if ( ShouldCombineAggressively && PotentiallyNewifiableTFR . count ( & I1 ) ) continue ; if ( ! isCombinableInstType ( I1 , TII , ShouldCombineAggressively ) ) continue ; bool DoInsertAtI1 = false ; DbgMItoMove . clear ( ) ; MachineInstr * I2 = findPairable ( I1 , DoInsertAtI1 , OptForSize ) ; if ( I2 ) { HasChanged = true ; combine ( I1 , * I2 , MI , DoInsertAtI1 , OptForSize ) ; } } } return HasChanged ; } </s>


<s> void M680x0PassConfig :: addPreSched2 ( ) { addPass ( createM680x0ExpandPseudoPass ( ) ) ; } </s>

This method may be implemented by targets that want to run passes after prolog-epilog insertion and before the second instruction scheduling pass .


<s> unsigned getStackAlignment ( ) const { return StackAlign ; } </s>

Returns the minimum alignment known to hold of the stack frame on entry to the function and which must be maintained by every function for this subtarget .


<s>
void
X86InstPrinterCommon
::
printPCRelImm
(
const
MCInst
*
MI
,
unsigned
OpNo
,
raw_ostream
&
O
)
{
const
MCOperand
&
Op
=
MI
->
getOperand
(
OpNo
)
;
if
(
Op
.
isImm
(
)
)
O
<<
formatImm
(
Op
.
getImm
(
)
)
;
else
{
assert
(
Op
.
isExpr
(
)
&&
"unknown pcrel immediate operand"
)
;
const
MCConstantExpr
*
BranchTarget
=
dyn_cast
<
MCConstantExpr
>
(
Op
.
getExpr
(
)
)
;
int64_t
Address
;
if
(
BranchTarget
&&
BranchTarget
->
evaluateAsAbsolute
(
Address
)
)
{
O
<<
formatHex
(
(
uint64_t
)
Address
)
;
}
else
{
Op
.
getExpr
(
)
->
print
(
O
,
&
MAI
)
;
}
}
}
</s>


"LowerFormalArguments Unhandled argument type: "

"functions with VarArgs or StructRet are not supported"

This hook must be implemented to lower the incoming ( formal ) arguments , described by the Ins array , into the specified DAG .


<s> ScheduleHazardRecognizer * HexagonInstrInfo :: CreateTargetPostRAHazardRecognizer ( const InstrItineraryData * II , const ScheduleDAG * DAG ) const { if ( UseDFAHazardRec ) { auto & HST = DAG -> MF . getSubtarget < HexagonSubtarget > ( ) ; return new HexagonHazardRecognizer ( II , this , HST ) ; } return TargetInstrInfo :: CreateTargetPostRAHazardRecognizer ( II , DAG ) ; } </s>

Allocate and return a hazard recognizer to use for by non-scheduling passes .


<s> int borx_reg_operand ( rtx op , enum machine_mode mode ) { if ( GET_CODE ( op ) != REG ) return 0 ; if ( op == virtual_incoming_args_rtx || op == virtual_stack_vars_rtx || op == virtual_stack_dynamic_rtx || op == virtual_outgoing_args_rtx || op == virtual_cfa_rtx ) return 0 ; if ( ! reload_completed && flag_omit_frame_pointer && ! current_function_calls_alloca && op == frame_pointer_rtx ) return 0 ; return register_operand ( op , mode ) ; } </s>

Return 1 if OP is valid as a base or index register in a REG+REG address .


<s> static bool xscale_sched_adjust_cost ( rtx_insn * insn , rtx link , rtx_insn * dep , int * cost ) { if ( REG_NOTE_KIND ( link ) == 0 && recog_memoized ( insn ) >= 0 && recog_memoized ( dep ) >= 0 ) { int shift_opnum = get_attr_shift ( insn ) ; enum attr_type attr_type = get_attr_type ( dep ) ; if ( shift_opnum != 0 && ( attr_type == TYPE_ALU_SHIFT_IMM || attr_type == TYPE_ALUS_SHIFT_IMM || attr_type == TYPE_LOGIC_SHIFT_IMM || attr_type == TYPE_LOGICS_SHIFT_IMM || attr_type == TYPE_ALU_SHIFT_REG || attr_type == TYPE_ALUS_SHIFT_REG || attr_type == TYPE_LOGIC_SHIFT_REG || attr_type == TYPE_LOGICS_SHIFT_REG || attr_type == TYPE_MOV_SHIFT || attr_type == TYPE_MVN_SHIFT || attr_type == TYPE_MOV_SHIFT_REG || attr_type == TYPE_MVN_SHIFT_REG ) ) { rtx shifted_operand ; int opno ; extract_insn ( insn ) ; shifted_operand = recog_data . operand [ shift_opnum ] ; extract_insn ( dep ) ; preprocess_constraints ( dep ) ; for ( opno = 0 ; opno < recog_data . n_operands ; opno ++ ) { if ( recog_data . operand_type [ opno ] == OP_IN ) continue ; if ( reg_overlap_mentioned_p ( recog_data . operand [ opno ] , shifted_operand ) ) { * cost = 2 ; return false ; } } } } return true ; } </s>


<s> void TMS320C64XClusterAssignment :: assign ( MachineInstr * MI , int res ) { Assigned [ MI ] = res ; } </s>


<s> static bool pa_modes_tieable_p ( machine_mode mode1 , machine_mode mode2 ) { if ( GET_MODE_CLASS ( mode1 ) != GET_MODE_CLASS ( mode2 ) ) return false ; return true ; } </s>

Returns TRUE if it is a good idea to tie two pseudo registers when one has mode MODE1 and one has mode MODE2 . If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2 , for any hard reg , then this must be FALSE for correct output . We should return FALSE for QImode and HImode because these modes are not ok in the floating-point registers . However , this prevents tieing these modes to SImode and DImode in the general registers . So , this is n't a good idea . We rely on HARD_REGNO_MODE_OK and CANNOT_CHANGE_MODE_CLASS to prevent these modes from being used in the floating-point registers .


<s>
bool
SIAnnotateControlFlow
::
runOnFunction
(
Function
&
F
)
{
DT
=
&
getAnalysis
<
DominatorTreeWrapperPass
>
(
)
.
getDomTree
(
)
;
LI
=
&
getAnalysis
<
LoopInfoWrapperPass
>
(
)
.
getLoopInfo
(
)
;
DA
=
&
getAnalysis
<
LegacyDivergenceAnalysis
>
(
)
;
TargetPassConfig
&
TPC
=
getAnalysis
<
TargetPassConfig
>
(
)
;
const
TargetMachine
&
TM
=
TPC
.
getTM
<
TargetMachine
>
(
)
;
bool
Changed
=
false
;
initialize
(
*
F
.
getParent
(
)
,
TM
.
getSubtarget
<
GCNSubtarget
>
(
F
)
)
;
for
(
df_iterator
<
BasicBlock
*
>
I
=
df_begin
(
&
F
.
getEntryBlock
(
)
)
,
E
=
df_end
(
&
F
.
getEntryBlock
(
)
)
;
I
!=
E
;
++
I
)
{
BasicBlock
*
BB
=
*
I
;
BranchInst
*
Term
=
dyn_cast
<
BranchInst
>
(
BB
->
getTerminator
(
)
)
;
if
(
!
Term
||
Term
->
isUnconditional
(
)
)
{
if
(
isTopOfStack
(
BB
)
)
Changed
|=
closeControlFlow
(
BB
)
;
continue
;
}
if
(
I
.
nodeVisited
(
Term
->
getSuccessor
(
1
)
)
)
{
if
(
isTopOfStack
(
BB
)
)
Changed
|=
closeControlFlow
(
BB
)
;
if
(
DT
->
dominates
(
Term
->
getSuccessor
(
1
)
,
BB
)
)
Changed
|=
handleLoop
(
Term
)
;
continue
;
}
if
(
isTopOfStack
(
BB
)
)
{
PHINode
*
Phi
=
dyn_cast
<
PHINode
>
(
Term
->
getCondition
(
)
)
;
if
(
Phi
&&
Phi
->
getParent
(
)
==
BB
&&
isElse
(
Phi
)
&&
!
hasKill
(
BB
)
)
{
Changed
|=
insertElse
(
Term
)
;
Changed
|=
eraseIfUnused
(
Phi
)
;
continue
;
}
Changed
|=
closeControlFlow
(
BB
)
;
}
Changed
|=
openIf
(
Term
)
;
}
if
(
!
Stack
.
empty
(
)
)
{
report_fatal_error
(
"failed to annotate CFG"
)
;
}
return
Changed
;
}
</s>

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .


<s> void F2003fFrameLowering :: emitEpilogue ( MachineFunction & MF , MachineBasicBlock & MBB ) const { const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const F2003fInstrInfo & TII = * static_cast < const F2003fInstrInfo * > ( MF . getSubtarget ( ) . getInstrInfo ( ) ) ; MachineBasicBlock :: iterator MBBI = MBB . getLastNonDebugInstr ( ) ; DebugLoc DL = MBBI -> getDebugLoc ( ) ; uint64_t StackSize = MFI . getStackSize ( ) ; if ( StackSize ) { BuildMI ( MBB , MBBI , DL , TII . get ( F2003f :: ATAri ) , F2003f :: F5 ) . addReg ( F2003f :: F5 ) . addImm ( StackSize ) ; } } </s>


<s>
static
rtx
EM2
(
int
line
ATTRIBUTE_UNUSED
,
rtx
r
)
{
fprintf
(
stderr
,
"\033[36m%d: "
,
line
)
;
debug_rtx
(
r
)
;
fprintf
(
stderr
,
"\033[0m"
)
;
if
(
virt_insn_was_frame
)
RTX_FRAME_RELATED_P
(
r
)
=
1
;
return
r
;
}
</s>

Hook for all insns we emit . Re-mark them as FRAME_RELATED if needed .


<s> bool WebAssemblyTargetLowering :: isOffsetFoldingLegal ( const GlobalAddressSDNode * GA ) const { return false ; } </s>

Return true if folding a constant offset with the given GlobalAddress is legal .


<s>
bool
AArch64CallLowering
::
lowerReturn
(
MachineIRBuilder
&
MIRBuilder
,
const
Value
*
Val
,
unsigned
VReg
)
const
{
MachineFunction
&
MF
=
MIRBuilder
.
getMF
(
)
;
const
Function
&
F
=
MF
.
getFunction
(
)
;
auto
MIB
=
MIRBuilder
.
buildInstrNoInsert
(
AArch64
::
RET_ReallyLR
)
;
assert
(
(
(
Val
&&
VReg
)
||
(
!
Val
&&
!
VReg
)
)
&&
"Return value without a vreg"
)
;
bool
Success
=
true
;
if
(
VReg
)
{
const
AArch64TargetLowering
&
TLI
=
*
getTLI
<
AArch64TargetLowering
>
(
)
;
CCAssignFn
*
AssignFn
=
TLI
.
CCAssignFnForReturn
(
F
.
getCallingConv
(
)
)
;
MachineRegisterInfo
&
MRI
=
MF
.
getRegInfo
(
)
;
auto
&
DL
=
F
.
getParent
(
)
->
getDataLayout
(
)
;
ArgInfo
OrigArg
{
VReg
,
Val
->
getType
(
)
}
;
setArgFlags
(
OrigArg
,
AttributeList
::
ReturnIndex
,
DL
,
F
)
;
SmallVector
<
ArgInfo
,
8
>
SplitArgs
;
splitToValueTypes
(
OrigArg
,
SplitArgs
,
DL
,
MRI
,
F
.
getCallingConv
(
)
,
[
&
]
(
unsigned
Reg
,
uint64_t
Offset
)
{
MIRBuilder
.
buildExtract
(
Reg
,
VReg
,
Offset
)
;
}
)
;
OutgoingArgHandler
Handler
(
MIRBuilder
,
MRI
,
MIB
,
AssignFn
,
AssignFn
)
;
Success
=
handleAssignments
(
MIRBuilder
,
SplitArgs
,
Handler
)
;
}
MIRBuilder
.
insertInstr
(
MIB
)
;
return
Success
;
}
</s>

This hook behaves as the extended lowerReturn function , but for targets that do not support swifterror value promotion .


<s> static void riscv_for_each_saved_reg ( HOST_WIDE_INT sp_offset , riscv_save_restore_fn fn , bool epilogue , bool maybe_eh_return ) { HOST_WIDE_INT offset ; offset = cfun -> machine -> frame . gp_sp_offset - sp_offset ; for ( unsigned int regno = GP_REG_FIRST ; regno <= GP_REG_LAST ; regno ++ ) if ( BITSET_P ( cfun -> machine -> frame . mask , regno - GP_REG_FIRST ) ) { bool handle_reg = TRUE ; if ( epilogue && ! maybe_eh_return && crtl -> calls_eh_return ) { unsigned int i , regnum ; for ( i = 0 ; ( regnum = EH_RETURN_DATA_REGNO ( i ) ) != INVALID_REGNUM ; i ++ ) if ( regno == regnum ) { handle_reg = FALSE ; break ; } } if ( handle_reg ) riscv_save_restore_reg ( word_mode , regno , offset , fn ) ; offset -= UNITS_PER_WORD ; } offset = cfun -> machine -> frame . fp_sp_offset - sp_offset ; for ( unsigned int regno = FP_REG_FIRST ; regno <= FP_REG_LAST ; regno ++ ) if ( BITSET_P ( cfun -> machine -> frame . fmask , regno - FP_REG_FIRST ) ) { machine_mode mode = TARGET_DOUBLE_FLOAT ? DFmode : SFmode ; riscv_save_restore_reg ( mode , regno , offset , fn ) ; offset -= GET_MODE_SIZE ( mode ) ; } } </s>

Call FN for each register that is saved by the current function . SP_OFFSET is the offset of the current stack pointer from the start of the frame .


<s> static rtx aarch64_expand_fpsr_fpcr_getter ( enum insn_code icode , machine_mode mode , rtx target ) { expand_operand op ; create_output_operand ( & op , target , mode ) ; expand_insn ( icode , 1 , & op ) ; return op . value ; } </s>

Expand a fpsr or fpcr getter ( depending on UNSPEC ) using MODE . Return the target .


<s> void ix86_expand_rounddf_32 ( rtx operand0 , rtx operand1 ) { machine_mode mode = GET_MODE ( operand0 ) ; rtx xa , xa2 , dxa , TWO52 , tmp , half , mhalf , one , res , mask ; rtx_code_label * label ; TWO52 = ix86_gen_TWO52 ( mode ) ; res = gen_reg_rtx ( mode ) ; emit_move_insn ( res , operand1 ) ; xa = ix86_expand_sse_fabs ( res , & mask ) ; label = ix86_expand_sse_compare_and_jump ( UNLE , TWO52 , xa , false ) ; xa2 = expand_simple_binop ( mode , PLUS , xa , TWO52 , NULL_RTX , 0 , OPTAB_DIRECT ) ; xa2 = expand_simple_binop ( mode , MINUS , xa2 , TWO52 , xa2 , 0 , OPTAB_DIRECT ) ; dxa = expand_simple_binop ( mode , MINUS , xa2 , xa , NULL_RTX , 0 , OPTAB_DIRECT ) ; half = force_reg ( mode , const_double_from_real_value ( dconsthalf , mode ) ) ; one = expand_simple_binop ( mode , PLUS , half , half , NULL_RTX , 0 , OPTAB_DIRECT ) ; mhalf = expand_simple_binop ( mode , MINUS , half , one , NULL_RTX , 0 , OPTAB_DIRECT ) ; tmp = gen_reg_rtx ( mode ) ; tmp = ix86_expand_sse_compare_mask ( UNGT , dxa , half , false ) ; emit_insn ( gen_rtx_SET ( VOIDmode , tmp , gen_rtx_AND ( mode , one , tmp ) ) ) ; xa2 = expand_simple_binop ( mode , MINUS , xa2 , tmp , NULL_RTX , 0 , OPTAB_DIRECT ) ; tmp = ix86_expand_sse_compare_mask ( UNGE , mhalf , dxa , false ) ; emit_insn ( gen_rtx_SET ( VOIDmode , tmp , gen_rtx_AND ( mode , one , tmp ) ) ) ; xa2 = expand_simple_binop ( mode , PLUS , xa2 , tmp , NULL_RTX , 0 , OPTAB_DIRECT ) ; ix86_sse_copysign_to_positive ( res , xa2 , force_reg ( mode , operand1 ) , mask ) ; emit_label ( label ) ; LABEL_NUSES ( label ) = 1 ; emit_move_insn ( operand0 , res ) ; } </s>

Expand SSE sequence for computing round from OPERAND1 storing into OPERAND0 . Sequence that works without relying on DImode truncation via cvttsd2siq that is only available on 64bit targets .


<s> bool Thumb2InstrInfo :: isProfitableToIfCvt ( MachineBasicBlock & TMBB , unsigned NumT , MachineBasicBlock & FMBB , unsigned NumF ) const { return NumT && NumF && NumT <= ( IfCvtDiamondLimit ) && NumF <= ( IfCvtDiamondLimit ) ; } </s>


<s> static int arc_sched_issue_rate ( void ) { switch ( arc_tune ) { case ARC_TUNE_ARCHS4X : case ARC_TUNE_ARCHS4XD : return 3 ; default : break ; } return 1 ; } </s>

Implements target hook TARGET_SCHED_ISSUE_RATE .


<s>
void
rx_emit_stack_popm
(
rtx
*
operands
,
bool
is_popm
)
{
HOST_WIDE_INT
stack_adjust
;
HOST_WIDE_INT
last_reg
;
rtx
first_push
;
gcc_assert
(
CONST_INT_P
(
operands
[
0
]
)
)
;
stack_adjust
=
INTVAL
(
operands
[
0
]
)
;
gcc_assert
(
GET_CODE
(
operands
[
1
]
)
==
PARALLEL
)
;
last_reg
=
XVECLEN
(
operands
[
1
]
,
0
)
(
is_popm
2
:
3
)
;
first_push
=
XVECEXP
(
operands
[
1
]
,
0
,
1
)
;
gcc_assert
(
SET_P
(
first_push
)
)
;
first_push
=
SET_DEST
(
first_push
)
;
gcc_assert
(
REG_P
(
first_push
)
)
;
if
(
is_popm
)
asm_fprintf
(
asm_out_file
,
"\tpopm\t%s-%s\n"
,
reg_names
[
REGNO
(
first_push
)
]
,
reg_names
[
REGNO
(
first_push
)
+
last_reg
]
)
;
else
asm_fprintf
(
asm_out_file
,
"\trtsd\t#%d, %s-%s\n"
,
(
int
)
stack_adjust
,
reg_names
[
REGNO
(
first_push
)
]
,
reg_names
[
REGNO
(
first_push
)
+
last_reg
]
)
;
}
</s>

Generate a POPM or RTSD instruction that matches the given operands .


<s> AArch64ELFStreamer & AArch64TargetELFStreamer :: getStreamer ( ) { return static_cast < AArch64ELFStreamer & > ( Streamer ) ; } </s>

Return the output streamer for the assembler .


<s> static bool s390_safe_relative_long_p ( rtx_insn * insn ) { if ( recog_memoized ( insn ) >= 0 ) return get_attr_relative_long ( insn ) == RELATIVE_LONG_YES ; else return false ; } </s>

Return attribute relative_long of insn .


<s> static rtx pru_add3_frame_adjust ( rtx op0 , rtx op1 , int addendum , const enum reg_note kind ) { rtx insn ; rtx op0_adjust = gen_rtx_SET ( op0 , plus_constant ( Pmode , op1 , addendum ) ) ; if ( UBYTE_INT ( addendum ) || UBYTE_INT ( - addendum ) ) insn = emit_insn ( op0_adjust ) ; else { rtx tmpreg = gen_rtx_REG ( Pmode , PROLOGUE_TEMP_REGNUM ) ; if ( addendum < 0 ) { emit_insn ( gen_rtx_SET ( tmpreg , gen_int_mode ( - addendum , Pmode ) ) ) ; insn = emit_insn ( gen_sub3_insn ( op0 , op1 , tmpreg ) ) ; } else { emit_insn ( gen_rtx_SET ( tmpreg , gen_int_mode ( addendum , Pmode ) ) ) ; insn = emit_insn ( gen_add3_insn ( op0 , op1 , tmpreg ) ) ; } } if ( kind != REG_NOTE_MAX ) add_reg_note ( insn , kind , copy_rtx ( op0_adjust ) ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; return insn ; } </s>

Emit efficient RTL equivalent of ADD3 with the given const_int for frame-related registers . op0 - Destination register . op1 - First addendum operand ( a register ) . addendum - Second addendum operand ( a constant ) . kind - Note kind . REG_NOTE_MAX if no note must be added .


<s> static void sparc_file_end ( void ) { if ( pic_helper_symbol_name [ 0 ] && ! pic_helper_emitted_p ) emit_pic_helper ( ) ; if ( NEED_INDICATE_EXEC_STACK ) file_end_indicate_exec_stack ( ) ; } </s>

Do whatever processing is required at the end of a file .


<s> bool ARMBaseRegisterInfo :: isAsmClobberable ( const MachineFunction & MF , unsigned PhysReg ) const { return ! getReservedRegs ( MF ) . test ( PhysReg ) ; } </s>

Returns false if we ca n't guarantee that Physreg , specified as an IR asm clobber constraint , will be preserved across the statement .


<s> bool GBZ80FrameLowering :: hasFP ( const MachineFunction & MF ) const { return false ; } </s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .


<s> BitVector MipsRegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { static const uint16_t ReservedCPURegs [ ] = { Mips :: ZERO , Mips :: AT , Mips :: K0 , Mips :: K1 , Mips :: SP , Mips :: FP , Mips :: RA } ; static const uint16_t ReservedCPU64Regs [ ] = { Mips :: ZERO_64 , Mips :: AT_64 , Mips :: K0_64 , Mips :: K1_64 , Mips :: SP_64 , Mips :: FP_64 , Mips :: RA_64 } ; BitVector Reserved ( getNumRegs ( ) ) ; typedef TargetRegisterClass :: iterator RegIter ; for ( unsigned I = 0 ; I < array_lengthof ( ReservedCPURegs ) ; ++ I ) Reserved . set ( ReservedCPURegs [ I ] ) ; if ( Subtarget . hasMips64 ( ) ) { for ( unsigned I = 0 ; I < array_lengthof ( ReservedCPU64Regs ) ; ++ I ) Reserved . set ( ReservedCPU64Regs [ I ] ) ; for ( RegIter Reg = Mips :: AFGR64RegisterClass -> begin ( ) ; Reg != Mips :: AFGR64RegisterClass -> end ( ) ; ++ Reg ) Reserved . set ( * Reg ) ; } else { for ( RegIter Reg = Mips :: CPU64RegsRegisterClass -> begin ( ) ; Reg != Mips :: CPU64RegsRegisterClass -> end ( ) ; ++ Reg ) Reserved . set ( * Reg ) ; for ( RegIter Reg = Mips :: FGR64RegisterClass -> begin ( ) ; Reg != Mips :: FGR64RegisterClass -> end ( ) ; ++ Reg ) Reserved . set ( * Reg ) ; } if ( MF . getInfo < MipsFunctionInfo > ( ) -> globalBaseRegFixed ( ) ) { Reserved . set ( Mips :: GP ) ; Reserved . set ( Mips :: GP_64 ) ; } return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s> const char * XCoreTargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( Opcode ) { case XCoreISD :: BL : return "XCoreISD::BL" ; case XCoreISD :: PCRelativeWrapper : return "XCoreISD::PCRelativeWrapper" ; case XCoreISD :: DPRelativeWrapper : return "XCoreISD::DPRelativeWrapper" ; case XCoreISD :: CPRelativeWrapper : return "XCoreISD::CPRelativeWrapper" ; case XCoreISD :: STWSP : return "XCoreISD::STWSP" ; case XCoreISD :: RETSP : return "XCoreISD::RETSP" ; case XCoreISD :: LADD : return "XCoreISD::LADD" ; case XCoreISD :: LSUB : return "XCoreISD::LSUB" ; case XCoreISD :: LMUL : return "XCoreISD::LMUL" ; case XCoreISD :: MACCU : return "XCoreISD::MACCU" ; case XCoreISD :: MACCS : return "XCoreISD::MACCS" ; case XCoreISD :: CRC8 : return "XCoreISD::CRC8" ; case XCoreISD :: BR_JT : return "XCoreISD::BR_JT" ; case XCoreISD :: BR_JT32 : return "XCoreISD::BR_JT32" ; default : return NULL ; } } </s>

getTargetNodeName - This method returns the name of a target specific

XCore XCore XCoreISD::BL "XCoreISD::BL" XCoreISD::PCRelativeWrapper "XCoreISD::PCRelativeWrapper" XCoreISD::DPRelativeWrapper "XCoreISD::DPRelativeWrapper" XCoreISD::CPRelativeWrapper "XCoreISD::CPRelativeWrapper" XCoreISD::STWSP "XCoreISD::STWSP" XCoreISD::RETSP "XCoreISD::RETSP" XCoreISD::LADD "XCoreISD::LADD" XCoreISD::LSUB "XCoreISD::LSUB" XCoreISD::LMUL "XCoreISD::LMUL" XCoreISD::MACCU "XCoreISD::MACCU" XCoreISD::MACCS "XCoreISD::MACCS" XCoreISD::CRC8 "XCoreISD::CRC8" XCoreISD::BR_JT "XCoreISD::BR_JT" XCoreISD::BR_JT32 "XCoreISD::BR_JT32"


<s> inline bool sgpr_1reg_mode_p ( machine_mode mode ) { return ( mode == SImode || mode == SFmode || mode == HImode || mode == QImode || mode == BImode ) ; } </s>

Return true if MODE is valid for 1 SGPR register .


<s> static int riscv_build_integer ( struct riscv_integer_op * codes , HOST_WIDE_INT value , machine_mode mode ) { int cost = riscv_build_integer_1 ( codes , value , mode ) ; if ( value > 0 && cost > 2 ) { struct riscv_integer_op alt_codes [ RISCV_MAX_INTEGER_OPS ] ; int alt_cost , shift = clz_hwi ( value ) ; HOST_WIDE_INT shifted_val ; shifted_val = ( value << shift ) | ( ( ( ( HOST_WIDE_INT ) 1 ) << shift ) - 1 ) ; alt_cost = 1 + riscv_build_integer_1 ( alt_codes , shifted_val , mode ) ; if ( alt_cost < cost ) { alt_codes [ alt_cost - 1 ] . code = LSHIFTRT ; alt_codes [ alt_cost - 1 ] . value = shift ; memcpy ( codes , alt_codes , sizeof ( alt_codes ) ) ; cost = alt_cost ; } shifted_val = value << shift ; alt_cost = 1 + riscv_build_integer_1 ( alt_codes , shifted_val , mode ) ; if ( alt_cost < cost ) { alt_codes [ alt_cost - 1 ] . code = LSHIFTRT ; alt_codes [ alt_cost - 1 ] . value = shift ; memcpy ( codes , alt_codes , sizeof ( alt_codes ) ) ; cost = alt_cost ; } } if ( ! TARGET_64BIT && ( value > INT32_MAX || value < INT32_MIN ) ) { unsigned HOST_WIDE_INT loval = sext_hwi ( value , 32 ) ; unsigned HOST_WIDE_INT hival = sext_hwi ( ( value - loval ) >> 32 , 32 ) ; struct riscv_integer_op alt_codes [ RISCV_MAX_INTEGER_OPS ] ; struct riscv_integer_op hicode [ RISCV_MAX_INTEGER_OPS ] ; int hi_cost , lo_cost ; hi_cost = riscv_build_integer_1 ( hicode , hival , mode ) ; if ( hi_cost < cost ) { lo_cost = riscv_build_integer_1 ( alt_codes , loval , mode ) ; if ( lo_cost + hi_cost < cost ) { memcpy ( codes , alt_codes , lo_cost * sizeof ( struct riscv_integer_op ) ) ; memcpy ( codes + lo_cost , hicode , hi_cost * sizeof ( struct riscv_integer_op ) ) ; cost = lo_cost + hi_cost ; } } } return cost ; } </s>

Fill CODES with a sequence of rtl operations to load VALUE . Return the number of operations needed .


<s> bool Thumb1RegisterInfo :: saveScavengerRegister ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , MachineBasicBlock :: iterator & UseMI , const TargetRegisterClass * RC , unsigned Reg ) const { const TargetInstrInfo & TII = * STI . getInstrInfo ( ) ; DebugLoc DL ; AddDefaultPred ( BuildMI ( MBB , I , DL , TII . get ( ARM :: tMOVr ) ) . addReg ( ARM :: R12 , RegState :: Define ) . addReg ( Reg , RegState :: Kill ) ) ; bool done = false ; for ( MachineBasicBlock :: iterator II = I ; ! done && II != UseMI ; ++ II ) { if ( II -> isDebugValue ( ) ) continue ; for ( unsigned i = 0 , e = II -> getNumOperands ( ) ; i != e ; ++ i ) { const MachineOperand & MO = II -> getOperand ( i ) ; if ( MO . isRegMask ( ) && MO . clobbersPhysReg ( ARM :: R12 ) ) { UseMI = II ; done = true ; break ; } if ( ! MO . isReg ( ) || MO . isUndef ( ) || ! MO . getReg ( ) || TargetRegisterInfo :: isVirtualRegister ( MO . getReg ( ) ) ) continue ; if ( MO . getReg ( ) == ARM :: R12 ) { UseMI = II ; done = true ; break ; } } } AddDefaultPred ( BuildMI ( MBB , UseMI , DL , TII . get ( ARM :: tMOVr ) ) . addReg ( Reg , RegState :: Define ) . addReg ( ARM :: R12 , RegState :: Kill ) ) ; return true ; } </s>

Spill the register so it can be used by the register scavenger .


<s> bool isInlineConstant ( const MachineOperand & MO ) const { const MachineInstr * Parent = MO . getParent ( ) ; return isInlineConstant ( * Parent , Parent -> getOperandNo ( & MO ) ) ; } </s>

returns true if the operand OpIdx in MI is a valid inline immediate .


<s> bool MipsTargetLowering :: IsGlobalInSmallSection ( GlobalValue * GV ) { const TargetData * TD = getTargetData ( ) ; const GlobalVariable * GVA = dyn_cast < GlobalVariable > ( GV ) ; if ( ! GVA ) return false ; const Type * Ty = GV -> getType ( ) -> getElementType ( ) ; unsigned Size = TD -> getTypeAllocSize ( Ty ) ; if ( GVA -> hasInitializer ( ) && GV -> hasLocalLinkage ( ) ) { Constant * C = GVA -> getInitializer ( ) ; const ConstantArray * CVA = dyn_cast < ConstantArray > ( C ) ; if ( CVA && CVA -> isCString ( ) ) return false ; } return IsInSmallSection ( Size ) ; } </s>

Return true if this global address should be placed into small data/bss section .


<s> int h8300_hard_regno_nregs ( int regno ATTRIBUTE_UNUSED , machine_mode mode ) { return ( GET_MODE_SIZE ( mode ) + UNITS_PER_WORD - 1 ) / UNITS_PER_WORD ; } </s>

Worker function for HARD_REGNO_NREGS . We pretend the MAC register is 32bits -- we do n't have any data types on the H8 series to handle more than 32bits .


"Instr doesn't have FrameIndex operand!"

This method must be overriden to eliminate abstract frame indices from instructions which may use them .


<s> bool AMDGPUReplaceLDSUseWithPointer :: runOnModule ( Module & M ) { ReplaceLDSUseImpl LDSUseReplacer { M } ; return LDSUseReplacer . replaceLDSUse ( ) ; } </s>

runOnModule - Virtual method overriden by subclasses to process the module being operated on .


<s> Register TeakRegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { return Teak :: R7 ; } </s>


<s> int m32c_prepare_move ( rtx * operands , enum machine_mode mode ) { if ( TARGET_A16 && mode == PSImode ) return m32c_split_move ( operands , mode , 1 ) ; if ( ( GET_CODE ( operands [ 0 ] ) == MEM ) && ( GET_CODE ( XEXP ( operands [ 0 ] , 0 ) ) == PRE_MODIFY ) ) { rtx pmv = XEXP ( operands [ 0 ] , 0 ) ; rtx dest_reg = XEXP ( pmv , 0 ) ; rtx dest_mod = XEXP ( pmv , 1 ) ; emit_insn ( gen_rtx_SET ( Pmode , dest_reg , dest_mod ) ) ; operands [ 0 ] = gen_rtx_MEM ( mode , dest_reg ) ; } if ( ! no_new_pseudos && MEM_P ( operands [ 0 ] ) && MEM_P ( operands [ 1 ] ) ) operands [ 1 ] = copy_to_mode_reg ( mode , operands [ 1 ] ) ; return 0 ; } </s>

Used to emit move instructions . We split some moves , and avoid mem-mem moves .


<s> bool Mips16InstrInfo :: expandPostRAPseudo ( MachineBasicBlock :: iterator MI ) const { MachineBasicBlock & MBB = * MI -> getParent ( ) ; switch ( MI -> getDesc ( ) . getOpcode ( ) ) { default : return false ; case Mips :: RetRA16 : ExpandRetRA16 ( MBB , MI , Mips :: JrRa16 ) ; break ; } MBB . erase ( MI ) ; return true ; } </s>

This function is called for all pseudo instructions that remain after register allocation .


<s> static rtx cris_function_value ( const_tree type , const_tree func ATTRIBUTE_UNUSED , bool outgoing ATTRIBUTE_UNUSED ) { return gen_rtx_REG ( TYPE_MODE ( type ) , CRIS_FIRST_ARG_REG ) ; } </s>

Let 's assume all functions return in r [ CRIS_FIRST_ARG_REG ] for the time being .


<s> bool MipsFrameLowering :: targetHandlesStackFrameRounding ( ) const { return true ; } </s>

targetHandlesStackFrameRounding - Returns true if the target is responsible for rounding up the stack frame ( probably at emitPrologue time ) .


<s> unsigned M68kSubtarget :: getJumpTableEncoding ( ) const { if ( isPositionIndependent ( ) ) { if ( TM . getCodeModel ( ) == CodeModel :: Medium && ! atLeastM68020 ( ) ) return MachineJumpTableInfo :: EK_Custom32 ; return MachineJumpTableInfo :: EK_LabelDifference32 ; } return MachineJumpTableInfo :: EK_BlockAddress ; } </s>

Return the entry encoding for a jump table in the current function .


<s> bool arm_expand_vector_compare ( rtx target , rtx_code code , rtx op0 , rtx op1 , bool can_invert ) { machine_mode cmp_result_mode = GET_MODE ( target ) ; machine_mode cmp_mode = GET_MODE ( op0 ) ; bool inverted ; switch ( code ) { case UNORDERED : case UNLT : case UNLE : case UNGT : case UNGE : case UNEQ : case NE : code = reverse_condition_maybe_unordered ( code ) ; if ( ! can_invert ) { rtx tmp = gen_reg_rtx ( cmp_result_mode ) ; if ( arm_expand_vector_compare ( tmp , code , op0 , op1 , true ) ) gcc_unreachable ( ) ; emit_insn ( gen_rtx_SET ( target , gen_rtx_NOT ( cmp_result_mode , tmp ) ) ) ; return false ; } inverted = true ; break ; default : inverted = false ; break ; } switch ( code ) { case LE : case LT : if ( op1 != CONST0_RTX ( cmp_mode ) ) { code = swap_condition ( code ) ; std :: swap ( op0 , op1 ) ; } case EQ : case GE : case GT : emit_insn ( gen_neon_vc ( code , cmp_mode , target , op0 , op1 ) ) ; return inverted ; case GEU : case GTU : emit_insn ( gen_neon_vc ( code , cmp_mode , target , op0 , force_reg ( cmp_mode , op1 ) ) ) ; return inverted ; case LEU : case LTU : emit_insn ( gen_neon_vc ( swap_condition ( code ) , cmp_mode , target , force_reg ( cmp_mode , op1 ) , op0 ) ) ; return inverted ; case LTGT : case ORDERED : { rtx gt_res = gen_reg_rtx ( cmp_result_mode ) ; rtx alt_res = gen_reg_rtx ( cmp_result_mode ) ; rtx_code alt_code = ( code == LTGT ? LT : LE ) ; if ( arm_expand_vector_compare ( gt_res , GT , op0 , op1 , true ) || arm_expand_vector_compare ( alt_res , alt_code , op0 , op1 , true ) ) gcc_unreachable ( ) ; emit_insn ( gen_rtx_SET ( target , gen_rtx_IOR ( cmp_result_mode , gt_res , alt_res ) ) ) ; return inverted ; } default : gcc_unreachable ( ) ; } } </s>

Expand code to compare vectors OP0 and OP1 using condition CODE . If CAN_INVERT , store either the result or its inverse in TARGET and return true if TARGET contains the inverse . If ! CAN_INVERT , always store the result in TARGET , never its inverse . Note that the handling of floating-point comparisons is not IEEE compliant .


<s> bool VLIWResourceModel :: isResourceAvailable ( SUnit * SU , bool IsTop ) { if ( ! SU || ! SU -> getInstr ( ) ) return false ; switch ( SU -> getInstr ( ) -> getOpcode ( ) ) { default : if ( ! ResourcesModel -> canReserveResources ( * SU -> getInstr ( ) ) ) return false ; break ; case TargetOpcode :: EXTRACT_SUBREG : case TargetOpcode :: INSERT_SUBREG : case TargetOpcode :: SUBREG_TO_REG : case TargetOpcode :: REG_SEQUENCE : case TargetOpcode :: IMPLICIT_DEF : case TargetOpcode :: COPY : case TargetOpcode :: INLINEASM : break ; } MachineBasicBlock * MBB = SU -> getInstr ( ) -> getParent ( ) ; auto & QST = MBB -> getParent ( ) -> getSubtarget < HexagonSubtarget > ( ) ; const auto & QII = * QST . getInstrInfo ( ) ; if ( IsTop ) { for ( unsigned i = 0 , e = Packet . size ( ) ; i != e ; ++ i ) if ( hasDependence ( Packet [ i ] , SU , QII ) ) return false ; } else { for ( unsigned i = 0 , e = Packet . size ( ) ; i != e ; ++ i ) if ( hasDependence ( SU , Packet [ i ] , QII ) ) return false ; } return true ; } </s>

Check if scheduling of this SU is possible in the current packet .


<s> static bool equal ( tree a , tree b ) { return a == b ; } </s>


<s> MipsInstrInfo :: BranchType MipsInstrInfo :: analyzeBranch ( MachineBasicBlock & MBB , MachineBasicBlock * & TBB , MachineBasicBlock * & FBB , SmallVectorImpl < MachineOperand > & Cond , bool AllowModify , SmallVectorImpl < MachineInstr * > & BranchInstrs ) const { MachineBasicBlock :: reverse_iterator I = MBB . rbegin ( ) , REnd = MBB . rend ( ) ; while ( I != REnd && I -> isDebugInstr ( ) ) ++ I ; if ( I == REnd || ! isUnpredicatedTerminator ( * I ) ) { TBB = FBB = nullptr ; return BT_NoBranch ; } MachineInstr * LastInst = & * I ; unsigned LastOpc = LastInst -> getOpcode ( ) ; BranchInstrs . push_back ( LastInst ) ; if ( ! getAnalyzableBrOpc ( LastOpc ) ) return LastInst -> isIndirectBranch ( ) ? BT_Indirect : BT_None ; unsigned SecondLastOpc = 0 ; MachineInstr * SecondLastInst = nullptr ; ++ I ; while ( I != REnd && I -> isDebugInstr ( ) ) ++ I ; if ( I != REnd ) { SecondLastInst = & * I ; SecondLastOpc = getAnalyzableBrOpc ( SecondLastInst -> getOpcode ( ) ) ; if ( isUnpredicatedTerminator ( * SecondLastInst ) && ! SecondLastOpc ) return BT_None ; } if ( ! SecondLastOpc ) { if ( LastInst -> isUnconditionalBranch ( ) ) { TBB = LastInst -> getOperand ( 0 ) . getMBB ( ) ; return BT_Uncond ; } AnalyzeCondBr ( LastInst , LastOpc , TBB , Cond ) ; return BT_Cond ; } if ( ++ I != REnd && isUnpredicatedTerminator ( * I ) ) return BT_None ; BranchInstrs . insert ( BranchInstrs . begin ( ) , SecondLastInst ) ; if ( SecondLastInst -> isUnconditionalBranch ( ) ) { if ( ! AllowModify ) return BT_None ; TBB = SecondLastInst -> getOperand ( 0 ) . getMBB ( ) ; LastInst -> eraseFromParent ( ) ; BranchInstrs . pop_back ( ) ; return BT_Uncond ; } if ( ! LastInst -> isUnconditionalBranch ( ) ) return BT_None ; AnalyzeCondBr ( SecondLastInst , SecondLastOpc , TBB , Cond ) ; FBB = LastInst -> getOperand ( 0 ) . getMBB ( ) ; return BT_CondUncond ; } </s>

analyzeBranch - Analyze the branching code at the end of MBB , returning true if it can not be understood ( e.g .


<s> static sbitmap riscv_components_for_bb ( basic_block bb ) { bitmap in = DF_LIVE_IN ( bb ) ; bitmap gen = & DF_LIVE_BB_INFO ( bb ) -> gen ; bitmap kill = & DF_LIVE_BB_INFO ( bb ) -> kill ; sbitmap components = sbitmap_alloc ( FIRST_PSEUDO_REGISTER ) ; bitmap_clear ( components ) ; function_abi_aggregator callee_abis ; rtx_insn * insn ; FOR_BB_INSNS ( bb , insn ) if ( CALL_P ( insn ) ) callee_abis . note_callee_abi ( insn_callee_abi ( insn ) ) ; HARD_REG_SET extra_caller_saves = callee_abis . caller_save_regs ( * crtl -> abi ) ; for ( unsigned int regno = GP_REG_FIRST ; regno <= GP_REG_LAST ; regno ++ ) if ( ! fixed_regs [ regno ] && ! crtl -> abi -> clobbers_full_reg_p ( regno ) && ( TEST_HARD_REG_BIT ( extra_caller_saves , regno ) || bitmap_bit_p ( in , regno ) || bitmap_bit_p ( gen , regno ) || bitmap_bit_p ( kill , regno ) ) ) bitmap_set_bit ( components , regno ) ; for ( unsigned int regno = FP_REG_FIRST ; regno <= FP_REG_LAST ; regno ++ ) if ( ! fixed_regs [ regno ] && ! crtl -> abi -> clobbers_full_reg_p ( regno ) && ( TEST_HARD_REG_BIT ( extra_caller_saves , regno ) || bitmap_bit_p ( in , regno ) || bitmap_bit_p ( gen , regno ) || bitmap_bit_p ( kill , regno ) ) ) bitmap_set_bit ( components , regno ) ; return components ; } </s>


<s> static bool riscv_function_ok_for_sibcall ( tree decl ATTRIBUTE_UNUSED , tree exp ATTRIBUTE_UNUSED ) { if ( TARGET_SAVE_RESTORE ) return riscv_leaf_function_p ( ) ; return true ; } </s>


<s> static HOST_WIDE_INT epiphany_constant_alignment ( const_tree exp , HOST_WIDE_INT align ) { if ( TREE_CODE ( exp ) == STRING_CST ) return MAX ( align , FASTEST_ALIGNMENT ) ; return align ; } </s>


<s> bool RISCVAsmBackend :: writeNopData ( raw_ostream & OS , uint64_t Count ) const { bool HasStdExtC = STI . getFeatureBits ( ) [ RISCV :: FeatureStdExtC ] ; unsigned MinNopLen = HasStdExtC ? 2 : 4 ; if ( ( Count % MinNopLen ) != 0 ) return false ; for ( ; Count >= 4 ; Count -= 4 ) OS . write ( "\x13\0\0\0" , 4 ) ; if ( Count && HasStdExtC ) OS . write ( "\x01\0" , 2 ) ; return true ; } </s>

Write an ( optimal ) nop sequence of Count bytes to the given output .


<s> rtx nios2_split_large_constant ( rtx x , rtx temp ) { if ( CONST_INT_P ( x ) ) { HOST_WIDE_INT val = INTVAL ( x ) ; if ( SMALL_INT ( val ) ) return x ; else if ( SMALL_INT_UNSIGNED ( val ) || UPPER16_INT ( val ) ) { emit_move_insn ( temp , x ) ; return temp ; } else { HOST_WIDE_INT high = ( val + 0x8000 ) & ~ 0xffff ; HOST_WIDE_INT low = val - high ; emit_move_insn ( temp , gen_int_mode ( high , Pmode ) ) ; return gen_rtx_PLUS ( Pmode , temp , gen_int_mode ( low , Pmode ) ) ; } } emit_insn ( gen_rtx_SET ( temp , gen_rtx_HIGH ( Pmode , copy_rtx ( x ) ) ) ) ; return gen_rtx_LO_SUM ( Pmode , temp , copy_rtx ( x ) ) ; } </s>

Given an RTX X that satisfies nios2_large_constant_p , split it into high and lo_sum parts using TEMP as a scratch register . Emit the high instruction and return the lo_sum expression . Also handle special cases involving constant integers .


<s> static void s390_register_info_gprtofpr ( ) { int save_reg_slot = FPR0_REGNUM ; int i , j ; if ( ! TARGET_Z10 || ! TARGET_HARD_FLOAT || ! crtl -> is_leaf ) return ; if ( crtl -> calls_eh_return ) return ; for ( i = 15 ; i >= 6 ; i -- ) { if ( cfun_gpr_save_slot ( i ) == SAVE_SLOT_NONE ) continue ; while ( ( ! call_really_used_regs [ save_reg_slot ] || df_regs_ever_live_p ( save_reg_slot ) || cfun_fpr_save_p ( save_reg_slot ) ) && FP_REGNO_P ( save_reg_slot ) ) save_reg_slot ++ ; if ( ! FP_REGNO_P ( save_reg_slot ) ) { for ( j = 6 ; j <= 15 ; j ++ ) if ( FP_REGNO_P ( cfun_gpr_save_slot ( j ) ) ) cfun_gpr_save_slot ( j ) = SAVE_SLOT_STACK ; break ; } cfun_gpr_save_slot ( i ) = save_reg_slot ++ ; } } </s>

Update gpr_save_slots in the frame layout trying to make use of FPRs as GPR save slots . This is a helper routine of s390_register_info .


<s> int frv_emit_scc ( rtx operands [ ] ) { rtx set ; rtx test_rtx ; rtx clobber ; rtx cr_reg ; enum rtx_code test = GET_CODE ( operands [ 1 ] ) ; rtx cc_reg = frv_emit_comparison ( test , operands [ 2 ] , operands [ 3 ] ) ; test_rtx = gen_rtx_fmt_ee ( test , SImode , cc_reg , const0_rtx ) ; set = gen_rtx_SET ( operands [ 0 ] , test_rtx ) ; cr_reg = ( ( TARGET_ALLOC_CC ) ? gen_reg_rtx ( CC_CCRmode ) : gen_rtx_REG ( CC_CCRmode , ( ( GET_MODE ( cc_reg ) == CC_FPmode ) ? FCR_FIRST : ICR_FIRST ) ) ) ; clobber = gen_rtx_CLOBBER ( VOIDmode , cr_reg ) ; emit_insn ( gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( 2 , set , clobber ) ) ) ; return TRUE ; } </s>

Emit code to set a gpr to 1/0 based on a comparison . The comparison operands were previously stored in frv_compare_op0 and frv_compare_op1 .


<s> void addExpr ( MCInst & Inst , const MCExpr * Expr ) const { if ( Expr == 0 ) Inst . addOperand ( MCOperand :: createImm ( 0 ) ) ; else if ( const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( Expr ) ) Inst . addOperand ( MCOperand :: createImm ( CE -> getValue ( ) ) ) ; else Inst . addOperand ( MCOperand :: createExpr ( Expr ) ) ; } </s>


<s> int shl_sext_length ( rtx insn ) { rtx set_src , left_rtx , size_rtx ; int cost ; set_src = SET_SRC ( XVECEXP ( PATTERN ( insn ) , 0 , 0 ) ) ; left_rtx = XEXP ( XEXP ( set_src , 0 ) , 1 ) ; size_rtx = XEXP ( set_src , 1 ) ; shl_sext_kind ( left_rtx , size_rtx , & cost ) ; return cost ; } </s>

Function to be used in the length attribute of the instructions implementing this pattern .


<s> bool AArch64AsmParser :: ParseDirective ( AsmToken DirectiveID ) { const MCObjectFileInfo :: Environment Format = getContext ( ) . getObjectFileInfo ( ) -> getObjectFileType ( ) ; bool IsMachO = Format == MCObjectFileInfo :: IsMachO ; StringRef IDVal = DirectiveID . getIdentifier ( ) ; SMLoc Loc = DirectiveID . getLoc ( ) ; if ( IDVal == ".arch" ) parseDirectiveArch ( Loc ) ; else if ( IDVal == ".cpu" ) parseDirectiveCPU ( Loc ) ; else if ( IDVal == ".tlsdesccall" ) parseDirectiveTLSDescCall ( Loc ) ; else if ( IDVal == ".ltorg" || IDVal == ".pool" ) parseDirectiveLtorg ( Loc ) ; else if ( IDVal == ".unreq" ) parseDirectiveUnreq ( Loc ) ; else if ( IDVal == ".inst" ) parseDirectiveInst ( Loc ) ; else if ( IsMachO ) { if ( IDVal == MCLOHDirectiveName ( ) ) parseDirectiveLOH ( IDVal , Loc ) ; else return true ; } else return true ; return false ; } </s>

ParseDirective - Parse a target specific assembler directive This method is deprecated , use 'parseDirective ' instead .


<s>
SUnit
*
SystemZPostRASchedStrategy
::
pickNode
(
bool
&
IsTopNode
)
{
IsTopNode
=
true
;
if
(
Available
.
empty
(
)
)
return
nullptr
;
if
(
Available
.
size
(
)
==
1
)
{
LLVM_DEBUG
(
dbgs
(
)
<<
"** Only one: "
;
HazardRec
->
dumpSU
(
*
Available
.
begin
(
)
,
dbgs
(
)
)
;
dbgs
(
)
<<
"\n"
;
)
;
return
*
Available
.
begin
(
)
;
}
LLVM_DEBUG
(
dbgs
(
)
<<
"** Available: "
;
Available
.
dump
(
*
HazardRec
)
;
)
;
Candidate
Best
;
for
(
auto
*
SU
:
Available
)
{
Candidate
c
(
SU
,
*
HazardRec
)
;
if
(
Best
.
SU
==
nullptr
||
c
<
Best
)
{
Best
=
c
;
LLVM_DEBUG
(
dbgs
(
)
<<
"** Best so far: "
;
)
;
}
else
LLVM_DEBUG
(
dbgs
(
)
<<
"** Tried      : "
;
)
;
LLVM_DEBUG
(
HazardRec
->
dumpSU
(
c
.
SU
,
dbgs
(
)
)
;
c
.
dumpCosts
(
)
;
dbgs
(
)
<<
" Height:"
<<
c
.
SU
->
getHeight
(
)
;
dbgs
(
)
<<
"\n"
;
)
;
if
(
!
SU
->
isScheduleHigh
&&
Best
.
noCost
(
)
)
break
;
}
assert
(
Best
.
SU
!=
nullptr
)
;
return
Best
.
SU
;
}
</s>

Pick the next node to schedule , or return NULL .

SystemZ
SystemZ
1
"** Only one: "
"\n"
"** Available: "
"** Best so far: "
"** Tried      : "
" Height:"
"\n"


<s> static void ea_load_store ( rtx mem , bool is_store , rtx ea_addr , rtx data_addr ) { if ( is_store ) { rtx ndirty = GEN_INT ( GET_MODE_SIZE ( GET_MODE ( mem ) ) ) ; if ( ! cache_fetch_dirty ) cache_fetch_dirty = init_one_libfunc ( "__cache_fetch_dirty" ) ; emit_library_call_value ( cache_fetch_dirty , data_addr , LCT_NORMAL , Pmode , ea_addr , EAmode , ndirty , SImode ) ; } else { if ( ! cache_fetch ) cache_fetch = init_one_libfunc ( "__cache_fetch" ) ; emit_library_call_value ( cache_fetch , data_addr , LCT_NORMAL , Pmode , ea_addr , EAmode ) ; } } </s>

MEM is known to be an __ea qualified memory access . Emit a call to fetch the ppu memory to local store , and return its address in local store .


<s> static section * spu_select_section ( tree decl , int reloc , unsigned HOST_WIDE_INT align ) { if ( TREE_TYPE ( decl ) != error_mark_node && TYPE_ADDR_SPACE ( TREE_TYPE ( decl ) ) == ADDR_SPACE_EA ) { if ( ! DECL_P ( decl ) ) return get_section ( "._ea" , SECTION_WRITE | SECTION_DEBUG , NULL ) ; return get_named_section ( decl , "._ea" , reloc ) ; } return default_elf_select_section ( decl , reloc , align ) ; } </s>


<s> bool LEGPassConfig :: addPreEmitPass ( ) { return false ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s> void sparc_flat_expand_prologue ( void ) { HOST_WIDE_INT size ; rtx_insn * insn ; sparc_leaf_function_p = optimize > 0 && crtl -> is_leaf ; size = sparc_compute_frame_size ( get_frame_size ( ) , sparc_leaf_function_p ) ; if ( flag_stack_usage_info ) current_function_static_stack_size = size ; if ( flag_stack_check == STATIC_BUILTIN_STACK_CHECK || flag_stack_clash_protection ) { if ( crtl -> is_leaf && ! cfun -> calls_alloca ) { if ( size > PROBE_INTERVAL && size > get_stack_check_protect ( ) ) sparc_emit_probe_stack_range ( get_stack_check_protect ( ) , size - get_stack_check_protect ( ) ) ; } else if ( size > 0 ) sparc_emit_probe_stack_range ( get_stack_check_protect ( ) , size ) ; } if ( sparc_save_local_in_regs_p ) emit_save_or_restore_local_in_regs ( stack_pointer_rtx , SPARC_STACK_BIAS , SORR_SAVE ) ; if ( size == 0 ) ; else { rtx size_int_rtx , size_rtx ; size_rtx = size_int_rtx = GEN_INT ( - size ) ; if ( size <= 4096 ) insn = emit_insn ( gen_stack_pointer_inc ( size_int_rtx ) ) ; else if ( size <= 8192 && ! frame_pointer_needed ) { insn = emit_insn ( gen_stack_pointer_inc ( GEN_INT ( - 4096 ) ) ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; insn = emit_insn ( gen_stack_pointer_inc ( GEN_INT ( 4096 - size ) ) ) ; } else { size_rtx = gen_rtx_REG ( Pmode , 1 ) ; emit_move_insn ( size_rtx , size_int_rtx ) ; insn = emit_insn ( gen_stack_pointer_inc ( size_rtx ) ) ; add_reg_note ( insn , REG_CFA_ADJUST_CFA , gen_stack_pointer_inc ( size_int_rtx ) ) ; } RTX_FRAME_RELATED_P ( insn ) = 1 ; emit_insn ( gen_frame_blockage ( ) ) ; if ( frame_pointer_needed ) { insn = emit_insn ( gen_rtx_SET ( hard_frame_pointer_rtx , gen_rtx_MINUS ( Pmode , stack_pointer_rtx , size_rtx ) ) ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; add_reg_note ( insn , REG_CFA_ADJUST_CFA , gen_rtx_SET ( hard_frame_pointer_rtx , plus_constant ( Pmode , stack_pointer_rtx , size ) ) ) ; } if ( return_addr_reg_needed_p ( sparc_leaf_function_p ) ) { rtx o7 = gen_rtx_REG ( Pmode , INCOMING_RETURN_ADDR_REGNUM ) ; rtx i7 = gen_rtx_REG ( Pmode , RETURN_ADDR_REGNUM ) ; insn = emit_move_insn ( i7 , o7 ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; add_reg_note ( insn , REG_CFA_REGISTER , gen_rtx_SET ( i7 , o7 ) ) ; emit_use ( i7 ) ; } } if ( frame_pointer_needed ) { sparc_frame_base_reg = hard_frame_pointer_rtx ; sparc_frame_base_offset = SPARC_STACK_BIAS ; } else { sparc_frame_base_reg = stack_pointer_rtx ; sparc_frame_base_offset = size + SPARC_STACK_BIAS ; } if ( sparc_n_global_fp_regs > 0 ) emit_save_or_restore_global_fp_regs ( sparc_frame_base_reg , sparc_frame_base_offset - sparc_apparent_frame_size , SORR_SAVE ) ; sparc_prologue_data_valid_p = true ; } </s>

Expand the function prologue . The prologue is responsible for reserving storage for the frame , saving the call-saved registers and loading the GOT register if needed .


<s>
void
NVPTXAsmPrinter
::
emitHeader
(
Module
&
M
,
raw_ostream
&
O
,
const
NVPTXSubtarget
&
STI
)
{
O
<<
"//\n"
;
O
<<
"// Generated by LLVM NVPTX Back-End\n"
;
O
<<
"//\n"
;
O
<<
"\n"
;
unsigned
PTXVersion
=
STI
.
getPTXVersion
(
)
;
O
<<
".version "
<<
(
PTXVersion
/
10
)
<<
"."
<<
(
PTXVersion
%
10
)
<<
"\n"
;
O
<<
".target "
;
O
<<
STI
.
getTargetName
(
)
;
const
NVPTXTargetMachine
&
NTM
=
static_cast
<
const
NVPTXTargetMachine
&
>
(
TM
)
;
if
(
NTM
.
getDrvInterface
(
)
==
NVPTX
::
NVCL
)
O
<<
", texmode_independent"
;
if
(
MAI
->
doesSupportDebugInformation
(
)
)
O
<<
", debug"
;
O
<<
"\n"
;
O
<<
".address_size "
;
if
(
NTM
.
is64Bit
(
)
)
O
<<
"64"
;
else
O
<<
"32"
;
O
<<
"\n"
;
O
<<
"\n"
;
}
</s>

Emit the header for this unit , not including the initial length field .

NVPTX
NVPTX
NVPTX
"//\n"
"// Generated by LLVM NVPTX Back-End\n"
"//\n"
"\n"
".version "
10
"."
10
"\n"
".target "
NVPTX
NVPTX
NVPTX::NVCL
", texmode_independent"
", debug"
"\n"
".address_size "
"64"
"32"
"\n"
"\n"


<s> bool symbolic_reference_mentioned_p ( rtx op ) { const char * fmt ; int i ; if ( GET_CODE ( op ) == SYMBOL_REF || GET_CODE ( op ) == LABEL_REF ) return 1 ; fmt = GET_RTX_FORMAT ( GET_CODE ( op ) ) ; for ( i = GET_RTX_LENGTH ( GET_CODE ( op ) ) - 1 ; i >= 0 ; i -- ) { if ( fmt [ i ] == 'E' ) { int j ; for ( j = XVECLEN ( op , i ) - 1 ; j >= 0 ; j -- ) if ( symbolic_reference_mentioned_p ( XVECEXP ( op , i , j ) ) ) return 1 ; } else if ( fmt [ i ] == 'e' && symbolic_reference_mentioned_p ( XEXP ( op , i ) ) ) return 1 ; } return 0 ; } </s>

Return true if OP contains a symbol reference


<s> const std :: string & AArch64LongBranchStub :: name ( ) const { return m_Name ; } </s>

Gets the name of the pass we are mixed into .


<s> static void mips_expand_vi_loongson_one_pinsrh ( rtx target , rtx vals , unsigned one_var ) { mips_expand_vi_constant ( V4HImode , 4 , target , vals ) ; emit_insn ( gen_vec_setv4hi ( target , target , XVECEXP ( vals , 0 , one_var ) , GEN_INT ( one_var ) ) ) ; } </s>

A subroutine of mips_expand_vec_init , expand via pinsrh .


<s> int SparcFrameLowering :: getFrameIndexReference ( const MachineFunction & MF , int FI , unsigned & FrameReg ) const { const SparcSubtarget & Subtarget = MF . getSubtarget < SparcSubtarget > ( ) ; const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const SparcRegisterInfo * RegInfo = Subtarget . getRegisterInfo ( ) ; const SparcMachineFunctionInfo * FuncInfo = MF . getInfo < SparcMachineFunctionInfo > ( ) ; bool isFixed = MFI -> isFixedObjectIndex ( FI ) ; bool UseFP ; if ( FuncInfo -> isLeafProc ( ) ) { UseFP = false ; } else if ( isFixed ) { UseFP = true ; } else if ( RegInfo -> needsStackRealignment ( MF ) ) { UseFP = false ; } else { UseFP = true ; } int64_t FrameOffset = MF . getFrameInfo ( ) -> getObjectOffset ( FI ) + Subtarget . getStackPointerBias ( ) ; if ( UseFP ) { FrameReg = RegInfo -> getFrameRegister ( MF ) ; return FrameOffset ; } else { FrameReg = SP :: O6 ; return FrameOffset + MF . getFrameInfo ( ) -> getStackSize ( ) ; } } </s>

getFrameIndexReference - This method should return the base register and offset used to reference a frame index location .

Sparc Sparc Sparc Sparc Sparc Sparc Sparc SP::O6


"AIX's linkage directives take a visibility setting."

"InternalLinkage should not have other visibility setting."

"CommonLinkage of XCOFF should not come to this path"

This emits linkage information about GVSym based on GV , if this is supported by the target .


<s> void SPScope :: dump ( raw_ostream & os , unsigned indent , bool recursive ) const { os . indent ( indent ) << "Scope[" << this << "]:\n" ; auto blocks = getFcfgBlocks ( ) ; for ( auto block : blocks ) { if ( isSubheader ( block ) ) { block -> printID ( os . indent ( indent + 2 ) ) << "<SUBHEADER>\n" ; } else { block -> dump ( os , indent + 2 ) ; } } if ( recursive ) { os << "\n" ; for ( auto subscope : Priv -> Subscopes ) { subscope -> dump ( os , indent + 2 , true ) ; } } } </s>

Dump the plan to stderr ( for debugging ) .


<s>
void
ARMTTIImpl
::
getUnrollingPreferences
(
Loop
*
L
,
ScalarEvolution
&
SE
,
TTI
::
UnrollingPreferences
&
UP
)
{
if
(
!
ST
->
isMClass
(
)
)
return
BasicTTIImplBase
::
getUnrollingPreferences
(
L
,
SE
,
UP
)
;
UP
.
OptSizeThreshold
=
0
;
UP
.
PartialOptSizeThreshold
=
0
;
if
(
L
->
getHeader
(
)
->
getParent
(
)
->
hasOptSize
(
)
)
return
;
if
(
!
ST
->
isThumb2
(
)
)
return
;
SmallVector
<
BasicBlock
*
,
4
>
ExitingBlocks
;
L
->
getExitingBlocks
(
ExitingBlocks
)
;
LLVM_DEBUG
(
dbgs
(
)
<<
"Loop has:\n"
<<
"Blocks: "
<<
L
->
getNumBlocks
(
)
<<
"\n"
<<
"Exit blocks: "
<<
ExitingBlocks
.
size
(
)
<<
"\n"
)
;
if
(
ExitingBlocks
.
size
(
)
>
2
)
return
;
if
(
ST
->
hasBranchPredictor
(
)
&&
L
->
getNumBlocks
(
)
>
4
)
return
;
unsigned
Cost
=
0
;
for
(
auto
*
BB
:
L
->
getBlocks
(
)
)
{
for
(
auto
&
I
:
*
BB
)
{
if
(
I
.
getType
(
)
->
isVectorTy
(
)
)
return
;
if
(
isa
<
CallInst
>
(
I
)
||
isa
<
InvokeInst
>
(
I
)
)
{
if
(
const
Function
*
F
=
cast
<
CallBase
>
(
I
)
.
getCalledFunction
(
)
)
{
if
(
!
isLoweredToCall
(
F
)
)
continue
;
}
return
;
}
SmallVector
<
const
Value
*
,
4
>
Operands
(
I
.
value_op_begin
(
)
,
I
.
value_op_end
(
)
)
;
Cost
+=
getUserCost
(
&
I
,
Operands
,
TargetTransformInfo
::
TCK_CodeSize
)
;
}
}
LLVM_DEBUG
(
dbgs
(
)
<<
"Cost of loop: "
<<
Cost
<<
"\n"
)
;
UP
.
Partial
=
true
;
UP
.
Runtime
=
true
;
UP
.
UpperBound
=
true
;
UP
.
UnrollRemainder
=
true
;
UP
.
DefaultUnrollRuntimeCount
=
4
;
UP
.
UnrollAndJam
=
true
;
UP
.
UnrollAndJamInnerLoopThreshold
=
60
;
if
(
Cost
<
12
)
UP
.
Force
=
true
;
}
</s>

Get target-customized preferences for the generic loop unrolling transformation .


<s> int attr_length_save_restore_dltp ( rtx insn ) { if ( find_reg_note ( insn , REG_NORETURN , NULL_RTX ) ) return 0 ; return 8 ; } </s>

Return the total length of the save and restore instructions needed for the data linkage table pointer ( i.e. , the PIC register ) across the call instruction INSN . No-return calls do not require a save and restore . In addition , we may be able to avoid the save and restore for calls within the same translation unit .


"Can't load this register from stack slot"

Load the specified register of the given register class from the specified stack frame index .


<s> unsigned X86TTIImpl :: getScalarizationOverhead ( VectorType * Ty , const APInt & DemandedElts , bool Insert , bool Extract ) { unsigned Cost = 0 ; if ( Insert ) { std :: pair < int , MVT > LT = TLI -> getTypeLegalizationCost ( DL , Ty ) ; MVT MScalarTy = LT . second . getScalarType ( ) ; if ( ( MScalarTy == MVT :: i16 && ST -> hasSSE2 ( ) ) || ( MScalarTy . isInteger ( ) && ST -> hasSSE41 ( ) ) || ( MScalarTy == MVT :: f32 && ST -> hasSSE41 ( ) ) ) { if ( LT . second . getSizeInBits ( ) <= 128 ) { Cost += BaseT :: getScalarizationOverhead ( Ty , DemandedElts , Insert , false ) ; } else { unsigned NumSubVecs = LT . second . getSizeInBits ( ) / 128 ; Cost += ( PowerOf2Ceil ( NumSubVecs ) - 1 ) * LT . first ; Cost += DemandedElts . countPopulation ( ) ; if ( MScalarTy == MVT :: f32 ) for ( unsigned i = 0 , e = cast < FixedVectorType > ( Ty ) -> getNumElements ( ) ; i < e ; i += 4 ) if ( DemandedElts [ i ] ) Cost -- ; } } else if ( LT . second . isVector ( ) ) { if ( Ty -> isIntOrIntVectorTy ( ) ) Cost += DemandedElts . countPopulation ( ) ; unsigned NumElts = LT . second . getVectorNumElements ( ) ; unsigned Pow2Elts = PowerOf2Ceil ( cast < FixedVectorType > ( Ty ) -> getNumElements ( ) ) ; Cost += ( std :: min < unsigned > ( NumElts , Pow2Elts ) - 1 ) * LT . first ; } } if ( Extract ) Cost += BaseT :: getScalarizationOverhead ( Ty , DemandedElts , false , Extract ) ; return Cost ; } </s>

Estimate the overhead of scalarizing an instruction .


<s> void GCNPassConfig :: addOptimizedRegAlloc ( ) { insertPass ( & MachineSchedulerID , & SIWholeQuadModeID ) ; insertPass ( & MachineSchedulerID , & SIPreAllocateWWMRegsID ) ; if ( OptExecMaskPreRA ) insertPass ( & MachineSchedulerID , & SIOptimizeExecMaskingPreRAID ) ; if ( TM -> getOptLevel ( ) > CodeGenOpt :: Less ) insertPass ( & MachineSchedulerID , & SIFormMemoryClausesID ) ; insertPass ( & PHIEliminationID , & SILowerControlFlowID , false ) ; if ( EnableDCEInRA ) insertPass ( & DetectDeadLanesID , & DeadMachineInstructionElimID ) ; TargetPassConfig :: addOptimizedRegAlloc ( ) ; } </s>

addOptimizedRegAlloc - Add passes related to register allocation .


<s> void AMDGPUCFGPerform :: getAnalysisUsage ( AnalysisUsage & AU ) const { AU . addPreserved < MachineFunctionAnalysis > ( ) ; AU . addRequired < MachineFunctionAnalysis > ( ) ; AU . addRequired < MachineDominatorTree > ( ) ; AU . addRequired < MachinePostDominatorTree > ( ) ; AU . addRequired < MachineLoopInfo > ( ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> unsigned Z80RegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { return getFrameLowering ( MF ) -> hasFP ( MF ) ? ( Is24Bit ? Z80 :: UIX : Z80 :: IX ) : ( Is24Bit ? Z80 :: SPL : Z80 :: SPS ) ; } </s>


<s> static int try_issue_insn ( struct bundle_state * curr_state , rtx insn ) { if ( insn && state_transition ( curr_state -> dfa_state , insn ) >= 0 ) { free_bundle_state ( curr_state ) ; return FALSE ; } return TRUE ; } </s>

The following function tries to issue INSN for the current state without advancing processor cycle . If it failed , the function returns FALSE and frees the current state .


<s>
void
WebAssemblyInstPrinter
::
printInst
(
const
MCInst
*
MI
,
raw_ostream
&
OS
,
StringRef
Annot
,
const
MCSubtargetInfo
&
)
{
printInstruction
(
MI
,
OS
)
;
const
MCInstrDesc
&
Desc
=
MII
.
get
(
MI
->
getOpcode
(
)
)
;
if
(
Desc
.
isVariadic
(
)
)
for
(
auto
i
=
Desc
.
getNumOperands
(
)
,
e
=
MI
->
getNumOperands
(
)
;
i
<
e
;
++
i
)
{
if
(
i
!=
0
&&
(
MI
->
getOpcode
(
)
!=
WebAssembly
::
CALL_INDIRECT_VOID
||
i
!=
Desc
.
getNumOperands
(
)
)
)
OS
<<
", "
;
printOperand
(
MI
,
i
,
OS
)
;
}
printAnnotation
(
OS
,
Annot
)
;
if
(
CommentStream
)
{
switch
(
MI
->
getOpcode
(
)
)
{
default
:
break
;
case
WebAssembly
::
LOOP
:
{
printAnnotation
(
OS
,
"label"
+
utostr
(
ControlFlowCounter
)
+
':'
)
;
ControlFlowStack
.
push_back
(
std
::
make_pair
(
ControlFlowCounter
++
,
true
)
)
;
break
;
}
case
WebAssembly
::
BLOCK
:
ControlFlowStack
.
push_back
(
std
::
make_pair
(
ControlFlowCounter
++
,
false
)
)
;
break
;
case
WebAssembly
::
END_LOOP
:
ControlFlowStack
.
pop_back
(
)
;
break
;
case
WebAssembly
::
END_BLOCK
:
printAnnotation
(
OS
,
"label"
+
utostr
(
ControlFlowStack
.
pop_back_val
(
)
.
first
)
+
':'
)
;
break
;
}
unsigned
NumFixedOperands
=
Desc
.
NumOperands
;
SmallSet
<
uint64_t
,
8
>
Printed
;
for
(
unsigned
i
=
0
,
e
=
MI
->
getNumOperands
(
)
;
i
<
e
;
++
i
)
{
if
(
!
(
i
<
NumFixedOperands
(
Desc
.
OpInfo
[
i
]
.
OperandType
==
WebAssembly
::
OPERAND_BASIC_BLOCK
)
:
(
Desc
.
TSFlags
&
WebAssemblyII
::
VariableOpImmediateIsLabel
)
)
)
continue
;
uint64_t
Depth
=
MI
->
getOperand
(
i
)
.
getImm
(
)
;
if
(
!
Printed
.
insert
(
Depth
)
.
second
)
continue
;
const
auto
&
Pair
=
ControlFlowStack
.
rbegin
(
)
[
Depth
]
;
printAnnotation
(
OS
,
utostr
(
Depth
)
+
": "
+
(
Pair
.
second
"up"
:
"down"
)
+
" to label"
+
utostr
(
Pair
.
first
)
)
;
}
}
}
</s>

Print the specified MCInst to the specified raw_ostream .


"Slot for FPW register must be last in order to be found!"

processFunctionBeforeFrameFinalized - This method is called immediately before the specified function 's frame layout ( MF.getFrameInfo ( ) ) is finalized .


<s>
unsigned
ECLairMCCodeEmitter
::
getMachineOpValue
(
const
MCInst
&
MI
,
const
MCOperand
&
MO
,
SmallVectorImpl
<
MCFixup
>
&
Fixups
,
const
MCSubtargetInfo
&
STI
)
const
{
if
(
MO
.
isReg
(
)
)
return
Ctx
.
getRegisterInfo
(
)
->
getEncodingValue
(
MO
.
getReg
(
)
)
;
if
(
MO
.
isImm
(
)
)
return
static_cast
<
unsigned
>
(
MO
.
getImm
(
)
)
;
llvm_unreachable
(
"Unhandled expression!"
)
;
return
0
;
}
</s>

getMachineOpValue - Return binary encoding of operand .


"Unexpected data type for Gather/Scatter"

Calculate the cost of Gather / Scatter operation .


<s>
void
RISCVMCCodeEmitter
::
encodeInstruction
(
const
MCInst
&
MI
,
raw_ostream
&
OS
,
SmallVectorImpl
<
MCFixup
>
&
Fixups
,
const
MCSubtargetInfo
&
STI
)
const
{
verifyInstructionPredicates
(
MI
,
computeAvailableFeatures
(
STI
.
getFeatureBits
(
)
)
)
;
const
MCInstrDesc
&
Desc
=
MCII
.
get
(
MI
.
getOpcode
(
)
)
;
unsigned
Size
=
Desc
.
getSize
(
)
;
if
(
MI
.
getOpcode
(
)
==
RISCV
::
PseudoCALLReg
||
MI
.
getOpcode
(
)
==
RISCV
::
PseudoCALL
||
MI
.
getOpcode
(
)
==
RISCV
::
PseudoTAIL
||
MI
.
getOpcode
(
)
==
RISCV
::
PseudoJump
)
{
expandFunctionCall
(
MI
,
OS
,
Fixups
,
STI
)
;
MCNumEmitted
+=
2
;
return
;
}
if
(
MI
.
getOpcode
(
)
==
RISCV
::
PseudoAddTPRel
)
{
expandAddTPRel
(
MI
,
OS
,
Fixups
,
STI
)
;
MCNumEmitted
+=
1
;
return
;
}
if
(
MI
.
getOpcode
(
)
==
RISCV
::
PseudoVMSGEU_VX
||
MI
.
getOpcode
(
)
==
RISCV
::
PseudoVMSGE_VX
||
MI
.
getOpcode
(
)
==
RISCV
::
PseudoVMSGEU_VX_M
||
MI
.
getOpcode
(
)
==
RISCV
::
PseudoVMSGE_VX_M
||
MI
.
getOpcode
(
)
==
RISCV
::
PseudoVMSGEU_VX_M_T
||
MI
.
getOpcode
(
)
==
RISCV
::
PseudoVMSGE_VX_M_T
)
{
expandVMSGE
(
MI
,
OS
,
Fixups
,
STI
)
;
return
;
}
switch
(
Size
)
{
default
:
llvm_unreachable
(
"Unhandled encodeInstruction length!"
)
;
case
2
:
{
uint16_t
Bits
=
getBinaryCodeForInstr
(
MI
,
Fixups
,
STI
)
;
support
::
endian
::
write
<
uint16_t
>
(
OS
,
Bits
,
support
::
little
)
;
break
;
}
case
4
:
{
uint32_t
Bits
=
getBinaryCodeForInstr
(
MI
,
Fixups
,
STI
)
;
support
::
endian
::
write
(
OS
,
Bits
,
support
::
little
)
;
break
;
}
}
++
MCNumEmitted
;
}
</s>

Encode the given Inst to bytes and append to CB .


<s>
void
XCoreAsmPrinter
::
EmitInstruction
(
const
MachineInstr
*
MI
)
{
SmallString
<
128
>
Str
;
raw_svector_ostream
O
(
Str
)
;
if
(
MI
->
getOpcode
(
)
==
XCore
::
ADD_2rus
&&
!
MI
->
getOperand
(
2
)
.
getImm
(
)
)
O
<<
"\tmov "
<<
getRegisterName
(
MI
->
getOperand
(
0
)
.
getReg
(
)
)
<<
", "
<<
getRegisterName
(
MI
->
getOperand
(
1
)
.
getReg
(
)
)
;
else
printInstruction
(
MI
,
O
)
;
OutStreamer
.
EmitRawText
(
O
.
str
(
)
)
;
}
</s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


"%qE attribute only applies to functions"

Handle an `` interrupt '' attribute ; arguments as in struct attribute_spec.handler .


<s> void MipsMCInstLower :: Initialize ( Mangler * M , MCContext * C ) { Mang = M ; Ctx = C ; } </s>

This method must be called before any actual lowering is done .


<s> void Mips16FrameLowering :: emitPrologue ( MachineFunction & MF ) const { MachineBasicBlock & MBB = MF . front ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const MipsInstrInfo & TII = * static_cast < const MipsInstrInfo * > ( MF . getTarget ( ) . getInstrInfo ( ) ) ; MachineBasicBlock :: iterator MBBI = MBB . begin ( ) ; DebugLoc dl = MBBI != MBB . end ( ) ? MBBI -> getDebugLoc ( ) : DebugLoc ( ) ; uint64_t StackSize = MFI -> getStackSize ( ) ; if ( StackSize == 0 && ! MFI -> adjustsStack ( ) ) return ; if ( isInt < 16 > ( - StackSize ) ) BuildMI ( MBB , MBBI , dl , TII . get ( Mips :: SaveRaF16 ) ) . addImm ( StackSize ) ; } </s>

emitProlog/emitEpilog - These methods insert prolog and epilog code into the function .


<s> bool runOnMachineFunction ( MachineFunction & F ) override { nvptxSubtarget = & F . getSubtarget < NVPTXSubtarget > ( ) ; return AsmPrinter :: runOnMachineFunction ( F ) ; } </s>

runOnMachineFunction - Emit the function body .


"Odd number of callee-saved regs to spill!"

"Expected GPR64 callee-saved register pair!"

"Expected FPR64 callee-saved register pair!"

"Offset out of bounds for STP immediate"

spillCalleeSavedRegisters - Issues instruction ( s ) to spill all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of store instructions via storeRegToStackSlot ( ) .


"EBP/ESI restoration only required on win32"

"restoring EBP/ESI on non-32-bit target"

"end of registration object above normal EBP position!"

"32-bit frames with WinEH must use FramePtr or BasePtr"

Sets up EBP and optionally ESI based on the incoming EBP value .


<s>
bool
AMDGPUAsmPrinter
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
MF
.
setAlignment
(
8
)
;
SetupMachineFunction
(
MF
)
;
EmitFunctionHeader
(
)
;
MCContext
&
Context
=
getObjFileLowering
(
)
.
getContext
(
)
;
const
MCSectionELF
*
ConfigSection
=
Context
.
getELFSection
(
".AMDGPU.config"
,
ELF
::
SHT_PROGBITS
,
0
,
SectionKind
::
getReadOnly
(
)
)
;
OutStreamer
.
SwitchSection
(
ConfigSection
)
;
const
AMDGPUSubtarget
&
STM
=
TM
.
getSubtarget
<
AMDGPUSubtarget
>
(
)
;
SIProgramInfo
KernelInfo
;
if
(
STM
.
isAmdHsaOS
(
)
)
{
getSIProgramInfo
(
KernelInfo
,
MF
)
;
EmitAmdKernelCodeT
(
MF
,
KernelInfo
)
;
OutStreamer
.
EmitCodeAlignment
(
2
<<
(
MF
.
getAlignment
(
)
1
)
)
;
}
else
if
(
STM
.
getGeneration
(
)
>=
AMDGPUSubtarget
::
SOUTHERN_ISLANDS
)
{
getSIProgramInfo
(
KernelInfo
,
MF
)
;
EmitProgramInfoSI
(
MF
,
KernelInfo
)
;
}
else
{
EmitProgramInfoR600
(
MF
)
;
}
DisasmLines
.
clear
(
)
;
HexLines
.
clear
(
)
;
DisasmLineMaxLen
=
0
;
OutStreamer
.
SwitchSection
(
getObjFileLowering
(
)
.
getTextSection
(
)
)
;
EmitFunctionBody
(
)
;
if
(
isVerbose
(
)
)
{
const
MCSectionELF
*
CommentSection
=
Context
.
getELFSection
(
".AMDGPU.csdata"
,
ELF
::
SHT_PROGBITS
,
0
,
SectionKind
::
getReadOnly
(
)
)
;
OutStreamer
.
SwitchSection
(
CommentSection
)
;
if
(
STM
.
getGeneration
(
)
>=
AMDGPUSubtarget
::
SOUTHERN_ISLANDS
)
{
OutStreamer
.
emitRawComment
(
" Kernel info:"
,
false
)
;
OutStreamer
.
emitRawComment
(
" codeLenInByte = "
+
Twine
(
KernelInfo
.
CodeLen
)
,
false
)
;
OutStreamer
.
emitRawComment
(
" NumSgprs: "
+
Twine
(
KernelInfo
.
NumSGPR
)
,
false
)
;
OutStreamer
.
emitRawComment
(
" NumVgprs: "
+
Twine
(
KernelInfo
.
NumVGPR
)
,
false
)
;
OutStreamer
.
emitRawComment
(
" FloatMode: "
+
Twine
(
KernelInfo
.
FloatMode
)
,
false
)
;
OutStreamer
.
emitRawComment
(
" IeeeMode: "
+
Twine
(
KernelInfo
.
IEEEMode
)
,
false
)
;
OutStreamer
.
emitRawComment
(
" ScratchSize: "
+
Twine
(
KernelInfo
.
ScratchSize
)
,
false
)
;
}
else
{
R600MachineFunctionInfo
*
MFI
=
MF
.
getInfo
<
R600MachineFunctionInfo
>
(
)
;
OutStreamer
.
emitRawComment
(
Twine
(
"SQ_PGM_RESOURCES:STACK_SIZE = "
+
Twine
(
MFI
->
StackSize
)
)
)
;
}
}
if
(
STM
.
dumpCode
(
)
&&
DisasmEnabled
)
{
OutStreamer
.
SwitchSection
(
Context
.
getELFSection
(
".AMDGPU.disasm"
,
ELF
::
SHT_NOTE
,
0
,
SectionKind
::
getReadOnly
(
)
)
)
;
for
(
size_t
i
=
0
;
i
<
DisasmLines
.
size
(
)
;
++
i
)
{
std
::
string
Comment
(
DisasmLineMaxLen
DisasmLines
[
i
]
.
size
(
)
,
' '
)
;
Comment
+=
" ; "
+
HexLines
[
i
]
+
"\n"
;
OutStreamer
.
EmitBytes
(
StringRef
(
DisasmLines
[
i
]
)
)
;
OutStreamer
.
EmitBytes
(
StringRef
(
Comment
)
)
;
}
}
return
false
;
}
</s>


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . addRequired < MachineDominatorTree > ( ) ; AU . addRequired < MachineLoopInfo > ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>


<s> static int h8300_register_move_cost ( machine_mode mode ATTRIBUTE_UNUSED , reg_class_t from , reg_class_t to ) { if ( from == MAC_REGS || to == MAC_REGS ) return 6 ; else return 3 ; } </s>

Implements TARGET_REGISTER_MOVE_COST . Any SI register-to-register move may need to be reloaded , so inmplement h8300_register_move_cost to return > 2 so that reload never shortcuts .


"64-bit code requested on a subtarget that doesn't support it!"

"Segmented stacks are only implemented on ELF."

This constructor initializes the data members to match that of the specified triple .


<s> static bool alpha_return_in_memory ( tree type , tree fndecl ATTRIBUTE_UNUSED ) { enum machine_mode mode = VOIDmode ; int size ; if ( type ) { mode = TYPE_MODE ( type ) ; if ( AGGREGATE_TYPE_P ( type ) ) return true ; } size = GET_MODE_SIZE ( mode ) ; switch ( GET_MODE_CLASS ( mode ) ) { case MODE_VECTOR_FLOAT : return true ; case MODE_COMPLEX_FLOAT : size = GET_MODE_UNIT_SIZE ( mode ) ; break ; case MODE_INT : case MODE_FLOAT : case MODE_COMPLEX_INT : case MODE_VECTOR_INT : break ; default : return true ; } return size > UNITS_PER_WORD ; } </s>

Return true if TYPE must be returned in memory , instead of in registers .


<s> bool ARMBaseInstrInfo :: analyzeCompare ( const MachineInstr & MI , unsigned & SrcReg , unsigned & SrcReg2 , int & CmpMask , int & CmpValue ) const { switch ( MI . getOpcode ( ) ) { default : break ; case ARM :: CMPri : case ARM :: t2CMPri : case ARM :: tCMPi8 : SrcReg = MI . getOperand ( 0 ) . getReg ( ) ; SrcReg2 = 0 ; CmpMask = ~ 0 ; CmpValue = MI . getOperand ( 1 ) . getImm ( ) ; return true ; case ARM :: CMPrr : case ARM :: t2CMPrr : SrcReg = MI . getOperand ( 0 ) . getReg ( ) ; SrcReg2 = MI . getOperand ( 1 ) . getReg ( ) ; CmpMask = ~ 0 ; CmpValue = 0 ; return true ; case ARM :: TSTri : case ARM :: t2TSTri : SrcReg = MI . getOperand ( 0 ) . getReg ( ) ; SrcReg2 = 0 ; CmpMask = MI . getOperand ( 1 ) . getImm ( ) ; CmpValue = 0 ; return true ; } return false ; } </s>

analyzeCompare - For a comparison instruction , return the source registers in SrcReg and SrcReg2 if having two register operands , and the value it compares against in CmpValue .


<s> static bool mips_insn_has_flexible_gp_ref_p ( rtx_insn * insn ) { return ( get_attr_got ( insn ) != GOT_UNSET || mips_small_data_pattern_p ( PATTERN ( insn ) ) || reg_overlap_mentioned_p ( pic_offset_table_rtx , PATTERN ( insn ) ) ) ; } </s>

Return true if INSN refers to the global pointer in a `` flexible '' way . See mips_cfun_has_flexible_gp_ref_p for details .


<s>
const
char
*
mcore_output_movedouble
(
rtx
operands
[
]
,
enum
machine_mode
mode
ATTRIBUTE_UNUSED
)
{
rtx
dst
=
operands
[
0
]
;
rtx
src
=
operands
[
1
]
;
if
(
GET_CODE
(
dst
)
==
REG
)
{
if
(
GET_CODE
(
src
)
==
REG
)
{
int
dstreg
=
REGNO
(
dst
)
;
int
srcreg
=
REGNO
(
src
)
;
if
(
srcreg
+
1
==
dstreg
)
return
"mov	%R0,%R1\n\tmov	%0,%1"
;
else
return
"mov	%0,%1\n\tmov	%R0,%R1"
;
}
else
if
(
GET_CODE
(
src
)
==
MEM
)
{
rtx
memexp
=
memexp
=
XEXP
(
src
,
0
)
;
int
dstreg
=
REGNO
(
dst
)
;
int
basereg
=
1
;
if
(
GET_CODE
(
memexp
)
==
LABEL_REF
)
return
"lrw\t%0,[%1]\n\tlrw\t%R0,[%R1]"
;
else
if
(
GET_CODE
(
memexp
)
==
REG
)
basereg
=
REGNO
(
memexp
)
;
else
if
(
GET_CODE
(
memexp
)
==
PLUS
)
{
if
(
GET_CODE
(
XEXP
(
memexp
,
0
)
)
==
REG
)
basereg
=
REGNO
(
XEXP
(
memexp
,
0
)
)
;
else
if
(
GET_CODE
(
XEXP
(
memexp
,
1
)
)
==
REG
)
basereg
=
REGNO
(
XEXP
(
memexp
,
1
)
)
;
else
gcc_unreachable
(
)
;
}
else
gcc_unreachable
(
)
;
if
(
dstreg
==
basereg
)
{
return
"ldw\t%R0,%R1\n\tldw\t%0,%1"
;
}
else
return
"ldw\t%0,%1\n\tldw\t%R0,%R1"
;
}
else
if
(
GET_CODE
(
src
)
==
CONST_INT
)
{
if
(
TARGET_LITTLE_END
)
{
if
(
CONST_OK_FOR_I
(
INTVAL
(
src
)
)
)
output_asm_insn
(
"movi	%0,%1"
,
operands
)
;
else
if
(
CONST_OK_FOR_M
(
INTVAL
(
src
)
)
)
output_asm_insn
(
"bgeni	%0,%P1"
,
operands
)
;
else
if
(
INTVAL
(
src
)
==
1
)
output_asm_insn
(
"bmaski	%0,32"
,
operands
)
;
else
if
(
CONST_OK_FOR_N
(
INTVAL
(
src
)
)
)
output_asm_insn
(
"bmaski	%0,%N1"
,
operands
)
;
else
gcc_unreachable
(
)
;
if
(
INTVAL
(
src
)
<
0
)
return
"bmaski	%R0,32"
;
else
return
"movi	%R0,0"
;
}
else
{
if
(
CONST_OK_FOR_I
(
INTVAL
(
src
)
)
)
output_asm_insn
(
"movi	%R0,%1"
,
operands
)
;
else
if
(
CONST_OK_FOR_M
(
INTVAL
(
src
)
)
)
output_asm_insn
(
"bgeni	%R0,%P1"
,
operands
)
;
else
if
(
INTVAL
(
src
)
==
1
)
output_asm_insn
(
"bmaski	%R0,32"
,
operands
)
;
else
if
(
CONST_OK_FOR_N
(
INTVAL
(
src
)
)
)
output_asm_insn
(
"bmaski	%R0,%N1"
,
operands
)
;
else
gcc_unreachable
(
)
;
if
(
INTVAL
(
src
)
<
0
)
return
"bmaski	%0,32"
;
else
return
"movi	%0,0"
;
}
}
else
gcc_unreachable
(
)
;
}
else
if
(
GET_CODE
(
dst
)
==
MEM
&&
GET_CODE
(
src
)
==
REG
)
return
"stw\t%1,%0\n\tstw\t%R1,%R0"
;
else
gcc_unreachable
(
)
;
}
</s>

Return a sequence of instructions to perform DI or DF move . Since the MCORE can not move a DI or DF in one instruction , we have to take care when we see overlapping source and dest registers .


<s> int64_t getBytes ( ) const { return Bytes ; } </s>

Extract a fixed number of bytes from the location given by the cursor .


<s>
unsigned
AMDGPURegisterBankInfo
::
getBreakDownCost
(
const
ValueMapping
&
ValMapping
,
const
RegisterBank
*
CurBank
)
const
{
assert
(
CurBank
==
nullptr
&&
"shouldn't see already assigned bank"
)
;
assert
(
ValMapping
.
NumBreakDowns
==
2
&&
ValMapping
.
BreakDown
[
0
]
.
Length
==
32
&&
ValMapping
.
BreakDown
[
0
]
.
StartIdx
==
0
&&
ValMapping
.
BreakDown
[
1
]
.
Length
==
32
&&
ValMapping
.
BreakDown
[
1
]
.
StartIdx
==
32
&&
ValMapping
.
BreakDown
[
0
]
.
RegBank
==
ValMapping
.
BreakDown
[
1
]
.
RegBank
)
;
return
1
;
}
</s>

Get the cost of using ValMapping to decompose a register .


<s> void aarch64_split_combinev16qi ( rtx operands [ 3 ] ) { unsigned int dest = REGNO ( operands [ 0 ] ) ; unsigned int src1 = REGNO ( operands [ 1 ] ) ; unsigned int src2 = REGNO ( operands [ 2 ] ) ; machine_mode halfmode = GET_MODE ( operands [ 1 ] ) ; unsigned int halfregs = REG_NREGS ( operands [ 1 ] ) ; rtx destlo , desthi ; gcc_assert ( halfmode == V16QImode ) ; if ( src1 == dest && src2 == dest + halfregs ) { emit_note ( NOTE_INSN_DELETED ) ; return ; } destlo = gen_rtx_REG_offset ( operands [ 0 ] , halfmode , dest , 0 ) ; desthi = gen_rtx_REG_offset ( operands [ 0 ] , halfmode , dest + halfregs , GET_MODE_SIZE ( halfmode ) ) ; if ( reg_overlap_mentioned_p ( operands [ 2 ] , destlo ) && reg_overlap_mentioned_p ( operands [ 1 ] , desthi ) ) { emit_insn ( gen_xorv16qi3 ( operands [ 1 ] , operands [ 1 ] , operands [ 2 ] ) ) ; emit_insn ( gen_xorv16qi3 ( operands [ 2 ] , operands [ 1 ] , operands [ 2 ] ) ) ; emit_insn ( gen_xorv16qi3 ( operands [ 1 ] , operands [ 1 ] , operands [ 2 ] ) ) ; } else if ( ! reg_overlap_mentioned_p ( operands [ 2 ] , destlo ) ) { if ( src1 != dest ) emit_move_insn ( destlo , operands [ 1 ] ) ; if ( src2 != dest + halfregs ) emit_move_insn ( desthi , operands [ 2 ] ) ; } else { if ( src2 != dest + halfregs ) emit_move_insn ( desthi , operands [ 2 ] ) ; if ( src1 != dest ) emit_move_insn ( destlo , operands [ 1 ] ) ; } } </s>

Split operands into moves from op [ 1 ] + op [ 2 ] into op [ 0 ] .


<s>
unsigned
char
M680x0Subtarget
::
classifyLocalReference
(
const
GlobalValue
*
GV
)
const
{
switch
(
TM
.
getCodeModel
(
)
)
{
default
:
llvm_unreachable
(
"Unsupported code model"
)
;
case
CodeModel
::
Small
:
case
CodeModel
::
Kernel
:
{
return
M680x0II
::
MO_PC_RELATIVE_ADDRESS
;
}
case
CodeModel
::
Medium
:
{
if
(
isPositionIndependent
(
)
)
{
if
(
IsM68020
)
{
return
M680x0II
::
MO_PC_RELATIVE_ADDRESS
;
}
return
M680x0II
::
MO_GOTOFF
;
}
else
{
if
(
IsM68020
)
{
return
M680x0II
::
MO_PC_RELATIVE_ADDRESS
;
}
return
M680x0II
::
MO_ABSOLUTE_ADDRESS
;
}
}
}
}
</s>

Classify a global variable reference for the current subtarget according to how we should reference it in a non-pcrel context .


"Unknown fence ordering in emitLeadingFence"


<s> bool PPCRegisterInfo :: requiresRegisterScavenging ( const MachineFunction & ) const { return EnableRegisterScavenging ; } </s>

Returns true if the target requires ( and can make use of ) the register scavenger .


<s> bool MSP430RegisterInfo :: hasFP ( const MachineFunction & MF ) const { return NoFramePointerElim || MF . getFrameInfo ( ) -> hasVarSizedObjects ( ) ; } </s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .


"bad insn to frv_print_operand_memory_reference:"

Print a memory reference suitable for the ld/st instructions .


<s> bool PTXPassConfig :: addPostRegAlloc ( ) { return false ; } </s>

This method may be implemented by targets that want to run passes after register allocation pass pipeline but before prolog-epilog insertion .


<s>
const
char
*
aarch64_output_probe_stack_range
(
rtx
reg1
,
rtx
reg2
)
{
static
int
labelno
=
0
;
char
loop_lab
[
32
]
;
rtx
xops
[
2
]
;
ASM_GENERATE_INTERNAL_LABEL
(
loop_lab
,
"LPSRL"
,
labelno
++
)
;
ASM_OUTPUT_INTERNAL_LABEL
(
asm_out_file
,
loop_lab
)
;
HOST_WIDE_INT
stack_clash_probe_interval
=
1
<<
param_stack_clash_protection_guard_size
;
xops
[
0
]
=
reg1
;
HOST_WIDE_INT
interval
;
if
(
flag_stack_clash_protection
)
interval
=
stack_clash_probe_interval
;
else
interval
=
PROBE_INTERVAL
;
gcc_assert
(
aarch64_uimm12_shift
(
interval
)
)
;
xops
[
1
]
=
GEN_INT
(
interval
)
;
output_asm_insn
(
"sub\t%0, %0, %1"
,
xops
)
;
if
(
flag_stack_clash_protection
)
xops
[
1
]
=
GEN_INT
(
STACK_CLASH_CALLER_GUARD
)
;
else
xops
[
1
]
=
CONST0_RTX
(
GET_MODE
(
xops
[
1
]
)
)
;
output_asm_insn
(
"str\txzr, [%0, %1]"
,
xops
)
;
xops
[
1
]
=
reg2
;
output_asm_insn
(
"cmp\t%0, %1"
,
xops
)
;
fputs
(
"\tb.ne\t"
,
asm_out_file
)
;
assemble_name_raw
(
asm_out_file
,
loop_lab
)
;
fputc
(
'\n'
,
asm_out_file
)
;
return
""
;
}
</s>

Probe a range of stack addresses from REG1 to REG2 inclusive . These are absolute addresses .


<s> bool AMDGPUAsmBackend :: writeNopData ( raw_ostream & OS , uint64_t Count ) const { OS . write_zeros ( Count % 4 ) ; Count /= 4 ; const uint32_t Encoded_S_NOP_0 = 0xbf800000 ; for ( uint64_t I = 0 ; I != Count ; ++ I ) support :: endian :: write < uint32_t > ( OS , Encoded_S_NOP_0 , Endian ) ; return true ; } </s>

Write an ( optimal ) nop sequence of Count bytes to the given output .


"Byval argument's alignment should be a multiple of"

Target-specific cleanup for formal ByVal parameters .


<s>
StringRef
getPassName
(
)
const
override
{
return
"Hexagon Copy-To-Combine Pass"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> static int cris_initial_frame_pointer_offset ( void ) { int regno ; int offs = 0 ; bool got_really_used = false ; if ( current_function_uses_pic_offset_table ) { push_topmost_sequence ( ) ; got_really_used = reg_used_between_p ( pic_offset_table_rtx , get_insns ( ) , NULL_RTX ) ; pop_topmost_sequence ( ) ; } for ( regno = 0 ; regno < FIRST_PSEUDO_REGISTER ; regno ++ ) if ( cris_reg_saved_in_regsave_area ( regno , got_really_used ) ) offs += 4 ; offs += get_frame_size ( ) ; offs += current_function_outgoing_args_size ; if ( TARGET_STACK_ALIGN ) offs = TARGET_ALIGN_BY_32 ? ( offs + 3 ) & ~ 3 : ( offs + 1 ) & ~ 1 ; return offs ; } </s>

This used to be the INITIAL_FRAME_POINTER_OFFSET worker ; now only handles FP - > SP elimination offset .


<s> int nds32_expand_movmemqi ( rtx dstmem , rtx srcmem , rtx total_bytes , rtx alignment ) { HOST_WIDE_INT in_words , out_words ; rtx dst_base_reg , src_base_reg ; int maximum_bytes ; if ( TARGET_REDUCED_REGS ) maximum_bytes = 16 ; else maximum_bytes = 32 ; if ( GET_CODE ( total_bytes ) != CONST_INT || GET_CODE ( alignment ) != CONST_INT || INTVAL ( total_bytes ) > maximum_bytes || INTVAL ( total_bytes ) & 3 || INTVAL ( alignment ) & 3 ) return 0 ; dst_base_reg = copy_to_mode_reg ( SImode , XEXP ( dstmem , 0 ) ) ; src_base_reg = copy_to_mode_reg ( SImode , XEXP ( srcmem , 0 ) ) ; out_words = in_words = INTVAL ( total_bytes ) / UNITS_PER_WORD ; emit_insn ( nds32_expand_load_multiple ( 0 , in_words , src_base_reg , srcmem ) ) ; emit_insn ( nds32_expand_store_multiple ( 0 , out_words , dst_base_reg , dstmem ) ) ; return 1 ; } </s>

Function to move block memory content by using load_multiple and store_multiple . This is auxiliary extern function to help create rtx template . Check nds32-multiple.md file for the patterns .


<s> SparcTargetMachine :: SparcTargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL , bool is64bit ) : LLVMTargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL ) , Subtarget ( TT , CPU , FS , is64bit ) , DataLayout ( Subtarget . getDataLayout ( ) ) , TLInfo ( * this ) , TSInfo ( * this ) , InstrInfo ( Subtarget ) , FrameLowering ( Subtarget ) { } </s>


"WebAssemblyDebugFixup: Pop: Register not matched!"

"WebAssemblyDebugFixup: Stack not empty at end of basic block!"

runOnMachineFunction - Emit the function body .


<s> TargetPassConfig * FPGATargetMachine :: createPassConfig ( PassManagerBase & PM ) { return new FPGAPassConfig ( * this , PM ) ; } </s>

Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of CodeGen passes .


<s> bool mem_operand_ds_form ( rtx op , machine_mode mode ) { unsigned HOST_WIDE_INT offset ; int extra ; rtx addr = XEXP ( op , 0 ) ; if ( address_is_prefixed ( addr , mode , NON_PREFIXED_DS ) ) return true ; if ( ! offsettable_address_p ( false , mode , addr ) ) return false ; op = address_offset ( addr ) ; if ( op == NULL_RTX ) return true ; offset = INTVAL ( op ) ; if ( ( offset & 3 ) != 0 ) return false ; extra = GET_MODE_SIZE ( mode ) - UNITS_PER_WORD ; if ( extra < 0 ) extra = 0 ; if ( GET_CODE ( addr ) == LO_SUM ) offset = ( ( offset & 0xffff ) ^ 0x8000 ) - 0x8000 ; return SIGNED_16BIT_OFFSET_EXTRA_P ( offset , extra ) ; } </s>

As above , but for DS-FORM VSX insns . Unlike mem_operand_gpr , enforce an offset divisible by 4 even for 32-bit .


<s>
static
void
add_sve_type_attribute
(
tree
type
,
unsigned
int
num_zr
,
unsigned
int
num_pr
,
const
char
*
mangled_name
,
const
char
*
acle_name
)
{
tree
mangled_name_tree
=
(
mangled_name
get_identifier
(
mangled_name
)
:
NULL_TREE
)
;
tree
value
=
tree_cons
(
NULL_TREE
,
get_identifier
(
acle_name
)
,
NULL_TREE
)
;
value
=
tree_cons
(
NULL_TREE
,
mangled_name_tree
,
value
)
;
value
=
tree_cons
(
NULL_TREE
,
size_int
(
num_pr
)
,
value
)
;
value
=
tree_cons
(
NULL_TREE
,
size_int
(
num_zr
)
,
value
)
;
TYPE_ATTRIBUTES
(
type
)
=
tree_cons
(
get_identifier
(
"SVE type"
)
,
value
,
TYPE_ATTRIBUTES
(
type
)
)
;
}
</s>

Record that TYPE is an ABI-defined SVE type that contains NUM_ZR SVE vectors and NUM_PR SVE predicates . MANGLED_NAME , if nonnull , is the ABI-defined mangling of the type . ACLE_NAME is the < arm_sve.h > name of the type .


<s> static void or1k_option_override ( void ) { init_machine_status = or1k_init_machine_status ; } </s>

Worker for TARGET_OPTION_OVERRIDE . We currently only use this to setup init_machine_status .


<s> static rtx altivec_expand_st_builtin ( tree exp , rtx target ATTRIBUTE_UNUSED , bool * expandedp ) { tree fndecl = TREE_OPERAND ( CALL_EXPR_FN ( exp ) , 0 ) ; unsigned int fcode = DECL_FUNCTION_CODE ( fndecl ) ; tree arg0 , arg1 ; machine_mode mode0 , mode1 ; rtx pat , op0 , op1 ; enum insn_code icode ; switch ( fcode ) { case ALTIVEC_BUILTIN_ST_INTERNAL_16qi : icode = CODE_FOR_vector_altivec_store_v16qi ; break ; case ALTIVEC_BUILTIN_ST_INTERNAL_8hi : icode = CODE_FOR_vector_altivec_store_v8hi ; break ; case ALTIVEC_BUILTIN_ST_INTERNAL_4si : icode = CODE_FOR_vector_altivec_store_v4si ; break ; case ALTIVEC_BUILTIN_ST_INTERNAL_4sf : icode = CODE_FOR_vector_altivec_store_v4sf ; break ; case ALTIVEC_BUILTIN_ST_INTERNAL_2df : icode = CODE_FOR_vector_altivec_store_v2df ; break ; case ALTIVEC_BUILTIN_ST_INTERNAL_2di : icode = CODE_FOR_vector_altivec_store_v2di ; case ALTIVEC_BUILTIN_ST_INTERNAL_1ti : icode = CODE_FOR_vector_altivec_store_v1ti ; break ; default : * expandedp = false ; return NULL_RTX ; } arg0 = CALL_EXPR_ARG ( exp , 0 ) ; arg1 = CALL_EXPR_ARG ( exp , 1 ) ; op0 = expand_normal ( arg0 ) ; op1 = expand_normal ( arg1 ) ; mode0 = insn_data [ icode ] . operand [ 0 ] . mode ; mode1 = insn_data [ icode ] . operand [ 1 ] . mode ; if ( ! ( * insn_data [ icode ] . operand [ 0 ] . predicate ) ( op0 , mode0 ) ) op0 = gen_rtx_MEM ( mode0 , copy_to_mode_reg ( Pmode , op0 ) ) ; if ( ! ( * insn_data [ icode ] . operand [ 1 ] . predicate ) ( op1 , mode1 ) ) op1 = copy_to_mode_reg ( mode1 , op1 ) ; pat = GEN_FCN ( icode ) ( op0 , op1 ) ; if ( pat ) emit_insn ( pat ) ; * expandedp = true ; return NULL_RTX ; } </s>


<s>
void
MCGSite
::
print
(
raw_ostream
&
OS
)
const
{
if
(
MI
)
{
MachineBasicBlock
*
MBB
=
MI
->
getParent
(
)
;
OS
<<
"BB#"
<<
MBB
->
getNumber
(
)
<<
":"
<<
std
::
distance
(
MBB
->
instr_begin
(
)
,
MachineBasicBlock
::
instr_iterator
(
MI
)
)
<<
":"
;
}
OS
<<
*
Caller
<<
(
IsInSCC
" *--> "
:
" --> "
)
<<
*
Callee
;
}
</s>

print - Print a debug representation of the operand to the given stream .


"use_as_extended_reg: converting non-extending mem load in "

"use_as_extended_reg: dest reg %d of extending insn %d is "

Given a reg that is known to be sign or zero extended at some insn , take the appropriate measures so that the extended value can be used as a reg at the specified insn and return the resulting reg rtx .


<s> ScheduleDAGInstrs * createPostMachineScheduler ( MachineSchedContext * C ) const override { const AArch64Subtarget & ST = C -> MF -> getSubtarget < AArch64Subtarget > ( ) ; if ( ST . hasFusion ( ) ) { ScheduleDAGMI * DAG = createGenericSchedPostRA ( C ) ; DAG -> addMutation ( createAArch64MacroFusionDAGMutation ( ) ) ; return DAG ; } return nullptr ; } </s>

Similar to createMachineScheduler but used when postRA machine scheduling is enabled .


<s> static rtx s390_legitimize_address ( rtx x , rtx oldx ATTRIBUTE_UNUSED , machine_mode mode ATTRIBUTE_UNUSED ) { rtx constant_term = const0_rtx ; if ( TLS_SYMBOLIC_CONST ( x ) ) { x = legitimize_tls_address ( x , 0 ) ; if ( s390_legitimate_address_p ( mode , x , FALSE ) ) return x ; } else if ( GET_CODE ( x ) == PLUS && ( TLS_SYMBOLIC_CONST ( XEXP ( x , 0 ) ) || TLS_SYMBOLIC_CONST ( XEXP ( x , 1 ) ) ) ) { return x ; } else if ( flag_pic ) { if ( SYMBOLIC_CONST ( x ) || ( GET_CODE ( x ) == PLUS && ( SYMBOLIC_CONST ( XEXP ( x , 0 ) ) || SYMBOLIC_CONST ( XEXP ( x , 1 ) ) ) ) ) x = legitimize_pic_address ( x , 0 ) ; if ( s390_legitimate_address_p ( mode , x , FALSE ) ) return x ; } x = eliminate_constant_term ( x , & constant_term ) ; if ( GET_CODE ( constant_term ) == CONST_INT && ! TARGET_LONG_DISPLACEMENT && ! DISP_IN_RANGE ( INTVAL ( constant_term ) ) && ! ( REG_P ( x ) && REGNO_PTR_FRAME_P ( REGNO ( x ) ) ) ) { HOST_WIDE_INT lower = INTVAL ( constant_term ) & 0xfff ; HOST_WIDE_INT upper = INTVAL ( constant_term ) ^ lower ; rtx temp = gen_reg_rtx ( Pmode ) ; rtx val = force_operand ( GEN_INT ( upper ) , temp ) ; if ( val != temp ) emit_move_insn ( temp , val ) ; x = gen_rtx_PLUS ( Pmode , x , temp ) ; constant_term = GEN_INT ( lower ) ; } if ( GET_CODE ( x ) == PLUS ) { if ( GET_CODE ( XEXP ( x , 0 ) ) == REG ) { rtx temp = gen_reg_rtx ( Pmode ) ; rtx val = force_operand ( XEXP ( x , 1 ) , temp ) ; if ( val != temp ) emit_move_insn ( temp , val ) ; x = gen_rtx_PLUS ( Pmode , XEXP ( x , 0 ) , temp ) ; } else if ( GET_CODE ( XEXP ( x , 1 ) ) == REG ) { rtx temp = gen_reg_rtx ( Pmode ) ; rtx val = force_operand ( XEXP ( x , 0 ) , temp ) ; if ( val != temp ) emit_move_insn ( temp , val ) ; x = gen_rtx_PLUS ( Pmode , temp , XEXP ( x , 1 ) ) ; } } if ( constant_term != const0_rtx ) x = gen_rtx_PLUS ( Pmode , x , constant_term ) ; return x ; } </s>

Try machine-dependent ways of modifying an illegitimate address X to be legitimate . If we find one , return the new , valid address . OLDX is the address as it was before break_out_memory_refs was called . In some cases it is useful to look at this to decide what needs to be done . MODE is the mode of the operand pointed to by X . When -fpic is used , special handling is needed for symbolic references . See comments by legitimize_pic_address for details .


<s>
bool
AMDGPUSimplifyLibCalls
::
runOnFunction
(
Function
&
F
)
{
if
(
skipFunction
(
F
)
)
return
false
;
bool
Changed
=
false
;
auto
AA
=
&
getAnalysis
<
AAResultsWrapperPass
>
(
)
.
getAAResults
(
)
;
DEBUG
(
dbgs
(
)
<<
"AMDIC: process function "
;
F
.
printAsOperand
(
dbgs
(
)
,
false
,
F
.
getParent
(
)
)
;
dbgs
(
)
<<
'\n'
;
)
;
if
(
!
EnablePreLink
)
Changed
|=
setFastFlags
(
F
,
Options
)
;
for
(
auto
&
BB
:
F
)
{
for
(
BasicBlock
::
iterator
I
=
BB
.
begin
(
)
,
E
=
BB
.
end
(
)
;
I
!=
E
;
)
{
CallInst
*
CI
=
dyn_cast
<
CallInst
>
(
I
)
;
++
I
;
if
(
!
CI
)
continue
;
Function
*
Callee
=
CI
->
getCalledFunction
(
)
;
if
(
Callee
==
0
)
continue
;
DEBUG
(
dbgs
(
)
<<
"AMDIC: try folding "
<<
*
CI
<<
"\n"
;
dbgs
(
)
.
flush
(
)
)
;
if
(
Simplifier
.
fold
(
CI
,
AA
)
)
Changed
=
true
;
}
}
return
Changed
;
}
</s>

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .

AMDGPU
AMDGPU
"AMDIC: process function "
0
"AMDIC: try folding "
"\n"