<s> Value * X86TargetLowering :: getSafeStackPointerLocation ( IRBuilder < > & IRB ) const { if ( ! Subtarget . isTargetAndroid ( ) ) return TargetLowering :: getSafeStackPointerLocation ( IRB ) ; unsigned AddressSpace , Offset ; if ( Subtarget . is64Bit ( ) ) { Offset = 0x48 ; if ( getTargetMachine ( ) . getCodeModel ( ) == CodeModel :: Kernel ) AddressSpace = 256 ; else AddressSpace = 257 ; } else { Offset = 0x24 ; AddressSpace = 256 ; } return ConstantExpr :: getIntToPtr ( ConstantInt :: get ( Type :: getInt32Ty ( IRB . getContext ( ) ) , Offset ) , Type :: getInt8PtrTy ( IRB . getContext ( ) ) -> getPointerTo ( AddressSpace ) ) ; } </s>

Return true if the target stores SafeStack pointer at a fixed offset in some non-standard address space , and populates the address space and offset as appropriate .


<s>
void
print
(
raw_ostream
&
OS
)
const
override
{
switch
(
Kind
)
{
case
Immediate
:
OS
<<
*
getImm
(
)
;
break
;
case
Register
:
OS
<<
"<register x"
;
OS
<<
getReg
(
)
<<
">"
;
break
;
case
Token
:
OS
<<
"'"
<<
getToken
(
)
<<
"'"
;
break
;
}
}
</s>

print - Print a debug representation of the operand to the given stream .


<s>
CCAssignFn
*
AArch64TargetLowering
::
CCAssignFnForCall
(
CallingConv
::
ID
CC
,
bool
IsVarArg
)
const
{
switch
(
CC
)
{
default
:
report_fatal_error
(
"Unsupported calling convention."
)
;
case
CallingConv
::
WebKit_JS
:
return
CC_AArch64_WebKit_JS
;
case
CallingConv
::
GHC
:
return
CC_AArch64_GHC
;
case
CallingConv
::
C
:
case
CallingConv
::
Fast
:
case
CallingConv
::
PreserveMost
:
case
CallingConv
::
CXX_FAST_TLS
:
case
CallingConv
::
Swift
:
if
(
Subtarget
->
isTargetWindows
(
)
&&
IsVarArg
)
return
CC_AArch64_Win64_VarArg
;
if
(
!
Subtarget
->
isTargetDarwin
(
)
)
return
CC_AArch64_AAPCS
;
return
IsVarArg
CC_AArch64_DarwinPCS_VarArg
:
CC_AArch64_DarwinPCS
;
case
CallingConv
::
Win64
:
return
IsVarArg
CC_AArch64_Win64_VarArg
:
CC_AArch64_AAPCS
;
case
CallingConv
::
AArch64_VectorCall
:
return
CC_AArch64_AAPCS
;
}
}
</s>

Selects the correct CCAssignFn for a given CallingConvention value .


<s> SDValue AMDGPUTargetLowering :: SplitVectorLoad ( const SDValue & Op , SelectionDAG & DAG ) const { LoadSDNode * Load = dyn_cast < LoadSDNode > ( Op ) ; EVT MemEltVT = Load -> getMemoryVT ( ) . getVectorElementType ( ) ; EVT EltVT = Op . getValueType ( ) . getVectorElementType ( ) ; EVT PtrVT = Load -> getBasePtr ( ) . getValueType ( ) ; unsigned NumElts = Load -> getMemoryVT ( ) . getVectorNumElements ( ) ; SmallVector < SDValue , 8 > Loads ; SDLoc SL ( Op ) ; for ( unsigned i = 0 , e = NumElts ; i != e ; ++ i ) { SDValue Ptr = DAG . getNode ( ISD :: ADD , SL , PtrVT , Load -> getBasePtr ( ) , DAG . getConstant ( i * ( MemEltVT . getSizeInBits ( ) / 8 ) , PtrVT ) ) ; Loads . push_back ( DAG . getExtLoad ( Load -> getExtensionType ( ) , SL , EltVT , Load -> getChain ( ) , Ptr , MachinePointerInfo ( Load -> getMemOperand ( ) -> getValue ( ) ) , MemEltVT , Load -> isVolatile ( ) , Load -> isNonTemporal ( ) , Load -> getAlignment ( ) ) ) ; } return DAG . getNode ( ISD :: BUILD_VECTOR , SL , Op . getValueType ( ) , & Loads [ 0 ] , Loads . size ( ) ) ; } </s>

Split a vector load into 2 loads of half the vector .


<s>
static
void
xstormy16_print_operand
(
FILE
*
file
,
rtx
x
,
int
code
)
{
switch
(
code
)
{
case
'B'
:
{
static
int
bits_set
[
8
]
=
{
0
,
1
,
1
,
2
,
1
,
2
,
2
,
3
}
;
HOST_WIDE_INT
xx
=
1
;
HOST_WIDE_INT
l
;
if
(
CONST_INT_P
(
x
)
)
xx
=
INTVAL
(
x
)
;
else
output_operand_lossage
(
"'B' operand is not constant"
)
;
if
(
bits_set
[
xx
&
7
]
<=
1
)
{
if
(
(
~
xx
&
~
(
HOST_WIDE_INT
)
0xff
)
==
0
)
xx
&=
0xff
;
else
if
(
(
~
xx
&
~
(
HOST_WIDE_INT
)
0xffff
)
==
0
)
xx
&=
0xffff
;
l
=
exact_log2
(
xx
)
;
}
else
{
if
(
(
xx
&
~
(
HOST_WIDE_INT
)
0xff
)
==
0
)
xx
|=
~
(
HOST_WIDE_INT
)
0xff
;
else
if
(
(
xx
&
~
(
HOST_WIDE_INT
)
0xffff
)
==
0
)
xx
|=
~
(
HOST_WIDE_INT
)
0xffff
;
l
=
exact_log2
(
~
xx
)
;
}
if
(
l
==
1
)
output_operand_lossage
(
"'B' operand has multiple bits set"
)
;
fprintf
(
file
,
IMMEDIATE_PREFIX
HOST_WIDE_INT_PRINT_DEC
,
l
)
;
return
;
}
case
'C'
:
if
(
GET_CODE
(
x
)
==
SYMBOL_REF
)
assemble_name
(
file
,
XSTR
(
x
,
0
)
)
;
else
if
(
LABEL_P
(
x
)
)
output_asm_label
(
x
)
;
else
xstormy16_print_operand_address
(
file
,
VOIDmode
,
x
)
;
return
;
case
'o'
:
case
'O'
:
{
HOST_WIDE_INT
xx
=
0
;
if
(
CONST_INT_P
(
x
)
)
xx
=
INTVAL
(
x
)
;
else
output_operand_lossage
(
"'o' operand is not constant"
)
;
if
(
code
==
'O'
)
xx
=
xx
;
fprintf
(
file
,
IMMEDIATE_PREFIX
HOST_WIDE_INT_PRINT_DEC
,
xx
1
)
;
return
;
}
case
'b'
:
{
HOST_WIDE_INT
xx
=
1
;
HOST_WIDE_INT
l
;
if
(
CONST_INT_P
(
x
)
)
xx
=
INTVAL
(
x
)
;
else
output_operand_lossage
(
"'B' operand is not constant"
)
;
l
=
7
xx
;
fputs
(
IMMEDIATE_PREFIX
,
file
)
;
fprintf
(
file
,
HOST_WIDE_INT_PRINT_DEC
,
l
)
;
return
;
}
case
0
:
break
;
default
:
output_operand_lossage
(
"xstormy16_print_operand: unknown code"
)
;
return
;
}
switch
(
GET_CODE
(
x
)
)
{
case
REG
:
fputs
(
reg_names
[
REGNO
(
x
)
]
,
file
)
;
break
;
case
MEM
:
xstormy16_print_operand_address
(
file
,
GET_MODE
(
x
)
,
XEXP
(
x
,
0
)
)
;
break
;
default
:
fputs
(
IMMEDIATE_PREFIX
,
file
)
;
output_addr_const
(
file
,
x
)
;
break
;
}
return
;
}
</s>

Print an operand to an assembler instruction .


"ReadCycleWrite is only to be used on riscv32"

This method should be implemented by targets that mark instructions with the 'usesCustomInserter ' flag .


<s> bool SICPassConfig :: addInstSelector ( ) { addPass ( createSICISelDag ( getSICTargetMachine ( ) , getOptLevel ( ) ) ) ; return false ; } </s>

addInstSelector - This method should install an instruction selector pass , which converts from LLVM code to machine instructions .


"-mno-power9-vector turns off -mpower9-dform"

If the user used -mno-vsx , we need turn off all of the implicit ISA 2.06 , 2.07 , and 3.0 options that relate to the vector unit ( -mdirect-move , -mupper-regs-df , etc. ) . If the user used -mno-power8-vector , we need to turn off all of the implicit ISA 2.07 and 3.0 options that relate to the vector unit . If the user used -mno-power9-vector , we need to turn off all of the implicit ISA 3.0 options that relate to the vector unit . This function does not handle explicit options such as the user specifying -mdirect-move . These are handled in rs6000_option_override_internal , and the appropriate error is given if needed . We return a mask of all of the implicit options that should not be enabled by default .


<s> void WebAssemblyPassConfig :: addPostRegAlloc ( ) { disablePass ( & PrologEpilogCodeInserterID ) ; disablePass ( & MachineCopyPropagationID ) ; disablePass ( & MachineBlockPlacementID ) ; } </s>

This method may be implemented by targets that want to run passes after register allocation pass pipeline but before prolog-epilog insertion .


<s> void emitValueImpl ( const MCExpr * Value , unsigned Size , SMLoc Loc = SMLoc ( ) ) override { } </s>

Overriding these functions allows us to dismiss all labels that are candidates for marking as microMIPS when .word/.long/.4byte etc directives are emitted .


<s> StringRef getPassName ( ) const override { return AVOIDCALL_DESC ; } </s>

getPassName - Return a nice clean name for a pass .


<s> static bool reg_plus_index_p ( rtx x , machine_mode mode , bool strict ) { rtx xfoo0 , xfoo1 ; if ( GET_CODE ( x ) != PLUS ) return false ; xfoo0 = XEXP ( x , 0 ) ; xfoo1 = XEXP ( x , 1 ) ; if ( BASE_REGISTER_P ( xfoo0 , strict ) && index_term_p ( xfoo1 , mode , strict ) ) return true ; if ( BASE_REGISTER_P ( xfoo1 , strict ) && index_term_p ( xfoo0 , mode , strict ) ) return true ; return false ; } </s>

Return 1 if X is the sum of a register and a valid index term for mode MODE .


<s> const TargetRegisterClass * PPCRegisterInfo :: getLargestLegalSuperClass ( const TargetRegisterClass * RC , const MachineFunction & MF ) const { const PPCSubtarget & Subtarget = MF . getSubtarget < PPCSubtarget > ( ) ; if ( Subtarget . hasVSX ( ) ) { if ( TM . isELFv2ABI ( ) ) { if ( Subtarget . hasP9Vector ( ) && EnableGPRToVecSpills && RC == & PPC :: G8RCRegClass ) { InflateGP8RC ++ ; return & PPC :: SPILLTOVSRRCRegClass ; } if ( RC == & PPC :: GPRCRegClass && EnableGPRToVecSpills ) InflateGPRC ++ ; } if ( RC == & PPC :: F8RCRegClass ) return & PPC :: VSFRCRegClass ; else if ( RC == & PPC :: VRRCRegClass ) return & PPC :: VSRCRegClass ; else if ( RC == & PPC :: F4RCRegClass && Subtarget . hasP8Vector ( ) ) return & PPC :: VSSRCRegClass ; } return TargetRegisterInfo :: getLargestLegalSuperClass ( RC , MF ) ; } </s>

Returns the largest super class of RC that is legal to use in the current sub-target and has the same spill size .

PowerPC PPC PPC PPC PPC::G8RCRegClass PPC::SPILLTOVSRRCRegClass PPC::GPRCRegClass PPC::F8RCRegClass PPC::VSFRCRegClass PPC::VRRCRegClass PPC::VSRCRegClass PPC::F4RCRegClass PPC::VSSRCRegClass


<s> bool mayNeedRelaxation ( const MCInst & Inst , const MCSubtargetInfo & STI ) const override { return false ; } </s>

Check whether the given instruction may need relaxation .


<s> const char * output_mul_insn ( int unsignedp ATTRIBUTE_UNUSED , rtx insn ) { import_milli ( mulI ) ; return output_millicode_call ( insn , gen_rtx_SYMBOL_REF ( Pmode , "$$mulI" ) ) ; } </s>

The register constraints have put the operands and return value in the proper registers .


"All regions recorded, starting actual scheduling.\n"

"Retrying function scheduling without clustering.\n"

"Retrying function scheduling with lowest recorded occupancy "

After the schedule has been formed , call this function to combine the instructions from the different stages/cycles .


<s> bool NVPTXAsmPrinter :: PrintAsmMemoryOperand ( const MachineInstr * MI , unsigned OpNo , const char * ExtraCode , raw_ostream & O ) { if ( ExtraCode && ExtraCode [ 0 ] ) return true ; O << '[' ; printMemOperand ( MI , OpNo , O ) ; O << ']' ; return false ; } </s>

Print the specified operand of MI , an INLINEASM instruction , using the specified assembler variant as an address .


<s>
bool
RISCVInstrInfo
::
isBranchOffsetInRange
(
unsigned
BranchOp
,
int64_t
BrOffset
)
const
{
unsigned
XLen
=
STI
.
getXLen
(
)
;
switch
(
BranchOp
)
{
default
:
llvm_unreachable
(
"Unexpected opcode!"
)
;
case
RISCV
::
BEQ
:
case
RISCV
::
BNE
:
case
RISCV
::
BLT
:
case
RISCV
::
BGE
:
case
RISCV
::
BLTU
:
case
RISCV
::
BGEU
:
return
isIntN
(
13
,
BrOffset
)
;
case
RISCV
::
JAL
:
case
RISCV
::
CJAL
:
case
RISCV
::
PseudoBR
:
case
RISCV
::
PseudoCBR
:
return
isIntN
(
21
,
BrOffset
)
;
case
RISCV
::
PseudoJump
:
case
RISCV
::
PseudoCJump
:
return
isIntN
(
32
,
SignExtend64
(
BrOffset
+
0x800
,
XLen
)
)
;
}
}
</s>

Determine if the branch target is in range .

RISCV
RISCV
"Unexpected opcode!"
RISCV::BEQ
RISCV::BNE
RISCV::BLT
RISCV::BGE
RISCV::BLTU
RISCV::BGEU
13
RISCV::JAL
RISCV::CJAL
RISCV::PseudoBR
RISCV::PseudoCBR
21
RISCV::PseudoJump
RISCV::PseudoCJump
32
0x800


<s> void Mips16FrameLowering :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { if ( ! hasReservedCallFrame ( MF ) ) { int64_t Amount = I -> getOperand ( 0 ) . getImm ( ) ; if ( I -> getOpcode ( ) == Mips :: ADJCALLSTACKDOWN ) Amount = - Amount ; const Mips16InstrInfo & TII = * static_cast < const Mips16InstrInfo * > ( MF . getTarget ( ) . getInstrInfo ( ) ) ; TII . adjustStackPtr ( Mips :: SP , Amount , MBB , I ) ; } MBB . erase ( I ) ; } </s>

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .

Mips Mips 0 Mips::ADJCALLSTACKDOWN Mips Mips Mips::SP


<s>
bool
ARMBaseInstrInfo
::
expandPostRAPseudo
(
MachineInstr
&
MI
)
const
{
if
(
MI
.
getOpcode
(
)
==
TargetOpcode
::
LOAD_STACK_GUARD
)
{
expandLoadStackGuard
(
MI
)
;
MI
.
getParent
(
)
->
erase
(
MI
)
;
return
true
;
}
if
(
MI
.
getOpcode
(
)
==
ARM
::
MEMCPY
)
{
expandMEMCPY
(
MI
)
;
return
true
;
}
if
(
!
MI
.
isCopy
(
)
||
Subtarget
.
dontWidenVMOVS
(
)
||
!
Subtarget
.
hasFP64
(
)
)
return
false
;
Register
DstRegS
=
MI
.
getOperand
(
0
)
.
getReg
(
)
;
Register
SrcRegS
=
MI
.
getOperand
(
1
)
.
getReg
(
)
;
if
(
!
ARM
::
SPRRegClass
.
contains
(
DstRegS
,
SrcRegS
)
)
return
false
;
const
TargetRegisterInfo
*
TRI
=
&
getRegisterInfo
(
)
;
unsigned
DstRegD
=
TRI
->
getMatchingSuperReg
(
DstRegS
,
ARM
::
ssub_0
,
&
ARM
::
DPRRegClass
)
;
unsigned
SrcRegD
=
TRI
->
getMatchingSuperReg
(
SrcRegS
,
ARM
::
ssub_0
,
&
ARM
::
DPRRegClass
)
;
if
(
!
DstRegD
||
!
SrcRegD
)
return
false
;
if
(
!
MI
.
definesRegister
(
DstRegD
,
TRI
)
||
MI
.
readsRegister
(
DstRegD
,
TRI
)
)
return
false
;
if
(
MI
.
getOperand
(
0
)
.
isDead
(
)
)
return
false
;
LLVM_DEBUG
(
dbgs
(
)
<<
"widening:    "
<<
MI
)
;
MachineInstrBuilder
MIB
(
*
MI
.
getParent
(
)
->
getParent
(
)
,
MI
)
;
int
ImpDefIdx
=
MI
.
findRegisterDefOperandIdx
(
DstRegD
)
;
if
(
ImpDefIdx
!=
1
)
MI
.
RemoveOperand
(
ImpDefIdx
)
;
MI
.
setDesc
(
get
(
ARM
::
VMOVD
)
)
;
MI
.
getOperand
(
0
)
.
setReg
(
DstRegD
)
;
MI
.
getOperand
(
1
)
.
setReg
(
SrcRegD
)
;
MIB
.
add
(
predOps
(
ARMCC
::
AL
)
)
;
MI
.
getOperand
(
1
)
.
setIsUndef
(
)
;
MIB
.
addReg
(
SrcRegS
,
RegState
::
Implicit
)
;
if
(
MI
.
getOperand
(
1
)
.
isKill
(
)
)
{
MI
.
getOperand
(
1
)
.
setIsKill
(
false
)
;
MI
.
addRegisterKilled
(
SrcRegS
,
TRI
,
true
)
;
}
LLVM_DEBUG
(
dbgs
(
)
<<
"replaced by: "
<<
MI
)
;
return
true
;
}
</s>

This function is called for all pseudo instructions that remain after register allocation .


"Can't load this register from stack slot"

Load the specified register of the given register class from the specified stack frame index .


<s>
StringRef
getPassName
(
)
const
override
{
return
"Scalar to IRF"
;
}
</s>


<s> const uint32_t * getRegMaskBits ( RegisterId R ) const { return RegMasks . get ( Register :: stackSlot2Index ( R ) ) ; } </s>

Returns an array of register mask pointers corresponding to getRegMaskSlots ( ) .


<s> MVT getScalarShiftAmountTy ( const DataLayout & , EVT ) const override { return MVT :: i8 ; } </s>

Return the type to use for a scalar shift opcode , given the shifted amount type .


<s> static const char * nios2_unspec_reloc_name ( int unspec ) { switch ( unspec ) { case UNSPEC_PIC_SYM : return "got" ; case UNSPEC_PIC_CALL_SYM : return "call" ; case UNSPEC_PIC_GOTOFF_SYM : return "gotoff" ; case UNSPEC_LOAD_TLS_IE : return "tls_ie" ; case UNSPEC_ADD_TLS_LE : return "tls_le" ; case UNSPEC_ADD_TLS_GD : return "tls_gd" ; case UNSPEC_ADD_TLS_LDM : return "tls_ldm" ; case UNSPEC_ADD_TLS_LDO : return "tls_ldo" ; default : return NULL ; } } </s>

Return the name string for a supported unspec reloc offset .


<s> Register MipsRegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { const MipsSubtarget & Subtarget = MF . getSubtarget < MipsSubtarget > ( ) ; const TargetFrameLowering * TFI = Subtarget . getFrameLowering ( ) ; auto & ABI = static_cast < const MipsTargetMachine & > ( MF . getTarget ( ) ) . getABI ( ) ; if ( Subtarget . inMips16Mode ( ) ) return TFI -> hasFP ( MF ) ? Mips :: S0 : Mips :: SP ; else return TFI -> hasFP ( MF ) ? ABI . GetFramePtr ( ) : ABI . GetStackPtr ( ) ; } </s>

Mips Mips Mips Mips Mips Mips Mips::S0 Mips::SP


<s> static rtx sparc_struct_value_rtx ( tree fndecl , int incoming ) { if ( TARGET_ARCH64 ) return 0 ; else { rtx mem ; if ( incoming ) mem = gen_frame_mem ( Pmode , plus_constant ( Pmode , frame_pointer_rtx , STRUCT_VALUE_OFFSET ) ) ; else mem = gen_frame_mem ( Pmode , plus_constant ( Pmode , stack_pointer_rtx , STRUCT_VALUE_OFFSET ) ) ; if ( incoming == 2 && sparc_std_struct_return && TYPE_SIZE_UNIT ( TREE_TYPE ( fndecl ) ) && TREE_CODE ( TYPE_SIZE_UNIT ( TREE_TYPE ( fndecl ) ) ) == INTEGER_CST ) { rtx ret_reg = gen_rtx_REG ( Pmode , 31 ) ; rtx scratch = gen_reg_rtx ( SImode ) ; rtx_code_label * endlab = gen_label_rtx ( ) ; tree size = TYPE_SIZE_UNIT ( TREE_TYPE ( fndecl ) ) ; rtx size_rtx = GEN_INT ( TREE_INT_CST_LOW ( size ) & 0xfff ) ; rtx temp_val = assign_stack_local ( Pmode , TREE_INT_CST_LOW ( size ) , 0 ) ; emit_move_insn ( scratch , gen_rtx_MEM ( SImode , plus_constant ( Pmode , ret_reg , 8 ) ) ) ; emit_insn ( gen_add3_insn ( ret_reg , ret_reg , GEN_INT ( 4 ) ) ) ; emit_cmp_and_jump_insns ( scratch , size_rtx , EQ , const0_rtx , SImode , 0 , endlab ) ; emit_insn ( gen_sub3_insn ( ret_reg , ret_reg , GEN_INT ( 4 ) ) ) ; emit_move_insn ( mem , XEXP ( temp_val , 0 ) ) ; emit_label ( endlab ) ; } return mem ; } } </s>

Handle the TARGET_STRUCT_VALUE target hook . Return where to find the structure return value address .


<s>
unsigned
Z80oldInstrInfo
::
removeBranch
(
MachineBasicBlock
&
MBB
,
int
*
BytesRemoved
)
const
{
assert
(
!
BytesRemoved
&&
"code size not handled"
)
;
MachineBasicBlock
::
iterator
I
=
MBB
.
end
(
)
;
unsigned
Count
=
0
;
while
(
I
!=
MBB
.
begin
(
)
)
{
I
;
if
(
I
->
isDebugValue
(
)
)
{
continue
;
}
if
(
I
->
getOpcode
(
)
!=
Z80old
::
JQ
&&
I
->
getOpcode
(
)
!=
Z80old
::
JQCC
)
{
break
;
}
I
->
eraseFromParent
(
)
;
I
=
MBB
.
end
(
)
;
++
Count
;
}
return
Count
;
}
</s>

Remove the branching code at the end of the specific MBB .


<s>
SDValue
HexagonTargetLowering
::
LowerOperation
(
SDValue
Op
,
SelectionDAG
&
DAG
)
const
{
switch
(
Op
.
getOpcode
(
)
)
{
default
:
llvm_unreachable
(
"Should not custom lower this!"
)
;
case
ISD
::
ConstantPool
:
return
LowerConstantPool
(
Op
,
DAG
)
;
case
ISD
::
RETURNADDR
:
return
LowerRETURNADDR
(
Op
,
DAG
)
;
case
ISD
::
FRAMEADDR
:
return
LowerFRAMEADDR
(
Op
,
DAG
)
;
case
ISD
::
GlobalTLSAddress
:
llvm_unreachable
(
"TLS not implemented for Hexagon."
)
;
case
ISD
::
MEMBARRIER
:
return
LowerMEMBARRIER
(
Op
,
DAG
)
;
case
ISD
::
ATOMIC_FENCE
:
return
LowerATOMIC_FENCE
(
Op
,
DAG
)
;
case
ISD
::
GlobalAddress
:
return
LowerGLOBALADDRESS
(
Op
,
DAG
)
;
case
ISD
::
BlockAddress
:
return
LowerBlockAddress
(
Op
,
DAG
)
;
case
ISD
::
VASTART
:
return
LowerVASTART
(
Op
,
DAG
)
;
case
ISD
::
BR_JT
:
return
LowerBR_JT
(
Op
,
DAG
)
;
case
ISD
::
DYNAMIC_STACKALLOC
:
return
LowerDYNAMIC_STACKALLOC
(
Op
,
DAG
)
;
case
ISD
::
SELECT_CC
:
return
LowerSELECT_CC
(
Op
,
DAG
)
;
case
ISD
::
SELECT
:
return
Op
;
case
ISD
::
INTRINSIC_WO_CHAIN
:
return
LowerINTRINSIC_WO_CHAIN
(
Op
,
DAG
)
;
case
ISD
::
INLINEASM
:
return
LowerINLINEASM
(
Op
,
DAG
)
;
}
}
</s>

LowerOperation - Provide custom lowering hooks for some operations .

Hexagon
Hexagon
"Should not custom lower this!"
ISD::ConstantPool
ISD::RETURNADDR
ISD::FRAMEADDR
ISD::GlobalTLSAddress
"TLS not implemented for Hexagon."
ISD::MEMBARRIER
ISD::ATOMIC_FENCE
ISD::GlobalAddress
ISD::BlockAddress
ISD::VASTART
ISD::BR_JT
ISD::DYNAMIC_STACKALLOC
ISD::SELECT_CC
ISD::SELECT
ISD::INTRINSIC_WO_CHAIN
ISD::INLINEASM


<s> unsigned getNumFixupKinds ( ) const override { return SIC :: NumTargetFixupKinds ; } </s>

Get the number of target specific fixup kinds .


<s> bool isToken ( ) const override { return Kind == k_Token ; } </s>


The guts of ix86_expand_vec_perm_const , also used by the ok hook . With all of the interface bits taken care of , perform the expansion in D and return true on success .


<s> std :: unique_ptr < MCObjectWriter > createObjectWriter ( raw_pwrite_stream & OS ) const override { return std :: unique_ptr < MCObjectWriter > ( createTOYELFObjectWriter ( OS , OSABI ) ) ; } </s>

Create a new MCObjectWriter instance for use by the assembler backend to emit the final object file .


<s>
bool
SystemZInstrInfo
::
analyzeBranch
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
*
&
TBB
,
MachineBasicBlock
*
&
FBB
,
SmallVectorImpl
<
MachineOperand
>
&
Cond
,
bool
AllowModify
)
const
{
MachineBasicBlock
::
iterator
I
=
MBB
.
end
(
)
;
while
(
I
!=
MBB
.
begin
(
)
)
{
I
;
if
(
I
->
isDebugInstr
(
)
)
continue
;
if
(
!
isUnpredicatedTerminator
(
*
I
)
)
break
;
if
(
!
I
->
isBranch
(
)
)
return
true
;
SystemZII
::
Branch
Branch
(
getBranchInfo
(
*
I
)
)
;
if
(
!
Branch
.
Target
->
isMBB
(
)
)
return
true
;
if
(
Branch
.
Type
!=
SystemZII
::
BranchNormal
)
return
true
;
if
(
Branch
.
CCMask
==
SystemZ
::
CCMASK_ANY
)
{
if
(
!
AllowModify
)
{
TBB
=
Branch
.
Target
->
getMBB
(
)
;
continue
;
}
while
(
std
::
next
(
I
)
!=
MBB
.
end
(
)
)
std
::
next
(
I
)
->
eraseFromParent
(
)
;
Cond
.
clear
(
)
;
FBB
=
nullptr
;
if
(
MBB
.
isLayoutSuccessor
(
Branch
.
Target
->
getMBB
(
)
)
)
{
TBB
=
nullptr
;
I
->
eraseFromParent
(
)
;
I
=
MBB
.
end
(
)
;
continue
;
}
TBB
=
Branch
.
Target
->
getMBB
(
)
;
continue
;
}
if
(
Cond
.
empty
(
)
)
{
FBB
=
TBB
;
TBB
=
Branch
.
Target
->
getMBB
(
)
;
Cond
.
push_back
(
MachineOperand
::
CreateImm
(
Branch
.
CCValid
)
)
;
Cond
.
push_back
(
MachineOperand
::
CreateImm
(
Branch
.
CCMask
)
)
;
continue
;
}
assert
(
Cond
.
size
(
)
==
2
&&
TBB
&&
"Should have seen a conditional branch"
)
;
if
(
TBB
!=
Branch
.
Target
->
getMBB
(
)
)
return
true
;
unsigned
OldCCValid
=
Cond
[
0
]
.
getImm
(
)
;
unsigned
OldCCMask
=
Cond
[
1
]
.
getImm
(
)
;
if
(
OldCCValid
==
Branch
.
CCValid
&&
OldCCMask
==
Branch
.
CCMask
)
continue
;
return
false
;
}
return
false
;
}
</s>

analyzeBranch - Analyze the branching code at the end of MBB , returning true if it can not be understood ( e.g .


<s> MCSymbol * WebAssemblyMCInstLower :: GetExternalSymbolSymbol ( const MachineOperand & MO ) const { const char * Name = MO . getSymbolName ( ) ; MCSymbolWasm * WasmSym = cast < MCSymbolWasm > ( Printer . GetExternalSymbolSymbol ( Name ) ) ; const WebAssemblySubtarget & Subtarget = Printer . getSubtarget ( ) ; if ( strcmp ( Name , "__stack_pointer" ) == 0 ) { WasmSym -> setType ( wasm :: WASM_SYMBOL_TYPE_GLOBAL ) ; WasmSym -> setGlobalType ( wasm :: WasmGlobalType { uint8_t ( Subtarget . hasAddr64 ( ) ? wasm :: WASM_TYPE_I64 : wasm :: WASM_TYPE_I32 ) , true } ) ; return WasmSym ; } SmallVector < wasm :: ValType , 4 > Returns ; SmallVector < wasm :: ValType , 4 > Params ; GetSignature ( Subtarget , Name , Returns , Params ) ; WasmSym -> setReturns ( std :: move ( Returns ) ) ; WasmSym -> setParams ( std :: move ( Params ) ) ; WasmSym -> setType ( wasm :: WASM_SYMBOL_TYPE_FUNCTION ) ; return WasmSym ; } </s>

Return the MCSymbol for the specified ExternalSymbol .


<s> bool MCS51TargetLowering :: getPreIndexedAddressParts ( SDNode * N , SDValue & Base , SDValue & Offset , ISD :: MemIndexedMode & AM , SelectionDAG & DAG ) const { EVT VT ; const SDNode * Op ; SDLoc DL ( N ) ; if ( const LoadSDNode * LD = dyn_cast < LoadSDNode > ( N ) ) { VT = LD -> getMemoryVT ( ) ; Op = LD -> getBasePtr ( ) . getNode ( ) ; if ( LD -> getExtensionType ( ) != ISD :: NON_EXTLOAD ) return false ; if ( MCS51 :: isProgramMemoryAccess ( LD ) ) { return false ; } } else if ( const StoreSDNode * ST = dyn_cast < StoreSDNode > ( N ) ) { VT = ST -> getMemoryVT ( ) ; Op = ST -> getBasePtr ( ) . getNode ( ) ; if ( MCS51 :: isProgramMemoryAccess ( ST ) ) { return false ; } } else { return false ; } if ( VT != MVT :: i8 && VT != MVT :: i16 ) { return false ; } if ( Op -> getOpcode ( ) != ISD :: ADD && Op -> getOpcode ( ) != ISD :: SUB ) { return false ; } if ( const ConstantSDNode * RHS = dyn_cast < ConstantSDNode > ( Op -> getOperand ( 1 ) ) ) { int RHSC = RHS -> getSExtValue ( ) ; if ( Op -> getOpcode ( ) == ISD :: SUB ) RHSC = - RHSC ; if ( ( VT == MVT :: i16 && RHSC != - 2 ) || ( VT == MVT :: i8 && RHSC != - 1 ) ) { return false ; } Base = Op -> getOperand ( 0 ) ; Offset = DAG . getConstant ( RHSC , DL , MVT :: i8 ) ; AM = ISD :: PRE_DEC ; return true ; } return false ; } </s>

Returns true by value , base pointer and offset pointer and addressing mode by reference if the node 's address can be legally represented as pre-indexed load / store address .


<s>
void
SIInstrInfo
::
storeRegToStackSlot
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
MI
,
Register
SrcReg
,
bool
isKill
,
int
FrameIndex
,
const
TargetRegisterClass
*
RC
,
const
TargetRegisterInfo
*
TRI
)
const
{
MachineFunction
*
MF
=
MBB
.
getParent
(
)
;
SIMachineFunctionInfo
*
MFI
=
MF
->
getInfo
<
SIMachineFunctionInfo
>
(
)
;
MachineFrameInfo
&
FrameInfo
=
MF
->
getFrameInfo
(
)
;
const
DebugLoc
&
DL
=
MBB
.
findDebugLoc
(
MI
)
;
MachinePointerInfo
PtrInfo
=
MachinePointerInfo
::
getFixedStack
(
*
MF
,
FrameIndex
)
;
MachineMemOperand
*
MMO
=
MF
->
getMachineMemOperand
(
PtrInfo
,
MachineMemOperand
::
MOStore
,
FrameInfo
.
getObjectSize
(
FrameIndex
)
,
FrameInfo
.
getObjectAlign
(
FrameIndex
)
)
;
unsigned
SpillSize
=
TRI
->
getSpillSize
(
*
RC
)
;
if
(
RI
.
isSGPRClass
(
RC
)
)
{
MFI
->
setHasSpilledSGPRs
(
)
;
assert
(
SrcReg
!=
AMDGPU
::
M0
&&
"m0 should not be spilled"
)
;
assert
(
SrcReg
!=
AMDGPU
::
EXEC_LO
&&
SrcReg
!=
AMDGPU
::
EXEC_HI
&&
SrcReg
!=
AMDGPU
::
EXEC
&&
"exec should not be spilled"
)
;
const
MCInstrDesc
&
OpDesc
=
get
(
getSGPRSpillSaveOpcode
(
SpillSize
)
)
;
if
(
SrcReg
.
isVirtual
(
)
&&
SpillSize
==
4
)
{
MachineRegisterInfo
&
MRI
=
MF
->
getRegInfo
(
)
;
MRI
.
constrainRegClass
(
SrcReg
,
&
AMDGPU
::
SReg_32_XM0_XEXECRegClass
)
;
}
BuildMI
(
MBB
,
MI
,
DL
,
OpDesc
)
.
addReg
(
SrcReg
,
getKillRegState
(
isKill
)
)
.
addFrameIndex
(
FrameIndex
)
.
addMemOperand
(
MMO
)
.
addReg
(
MFI
->
getStackPtrOffsetReg
(
)
,
RegState
::
Implicit
)
;
if
(
RI
.
spillSGPRToVGPR
(
)
)
FrameInfo
.
setStackID
(
FrameIndex
,
TargetStackID
::
SGPRSpill
)
;
return
;
}
unsigned
Opcode
=
RI
.
hasAGPRs
(
RC
)
getAGPRSpillSaveOpcode
(
SpillSize
)
:
getVGPRSpillSaveOpcode
(
SpillSize
)
;
MFI
->
setHasSpilledVGPRs
(
)
;
BuildMI
(
MBB
,
MI
,
DL
,
get
(
Opcode
)
)
.
addReg
(
SrcReg
,
getKillRegState
(
isKill
)
)
.
addFrameIndex
(
FrameIndex
)
.
addReg
(
MFI
->
getStackPtrOffsetReg
(
)
)
.
addImm
(
0
)
.
addMemOperand
(
MMO
)
;
}
</s>

Store the specified register of the given register class to the specified stack frame index .


"Pseudo opcode found in EmitInstruction()"

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s>
bool
SystemZDAGToDAGISel
::
SelectInlineAsmMemoryOperand
(
const
SDValue
&
Op
,
unsigned
ConstraintID
,
std
::
vector
<
SDValue
>
&
OutOps
)
{
SystemZAddressingMode
::
AddrForm
Form
;
SystemZAddressingMode
::
DispRange
DispRange
;
SDValue
Base
,
Disp
,
Index
;
switch
(
ConstraintID
)
{
default
:
llvm_unreachable
(
"Unexpected asm memory constraint"
)
;
case
InlineAsm
::
Constraint_i
:
case
InlineAsm
::
Constraint_Q
:
Form
=
SystemZAddressingMode
::
FormBD
;
DispRange
=
SystemZAddressingMode
::
Disp12Only
;
break
;
case
InlineAsm
::
Constraint_R
:
Form
=
SystemZAddressingMode
::
FormBDXNormal
;
DispRange
=
SystemZAddressingMode
::
Disp12Only
;
break
;
case
InlineAsm
::
Constraint_S
:
Form
=
SystemZAddressingMode
::
FormBD
;
DispRange
=
SystemZAddressingMode
::
Disp20Only
;
break
;
case
InlineAsm
::
Constraint_T
:
case
InlineAsm
::
Constraint_m
:
case
InlineAsm
::
Constraint_o
:
case
InlineAsm
::
Constraint_p
:
Form
=
SystemZAddressingMode
::
FormBDXNormal
;
DispRange
=
SystemZAddressingMode
::
Disp20Only
;
break
;
}
if
(
selectBDXAddr
(
Form
,
DispRange
,
Op
,
Base
,
Disp
,
Index
)
)
{
const
TargetRegisterClass
*
TRC
=
Subtarget
->
getRegisterInfo
(
)
->
getPointerRegClass
(
*
MF
)
;
SDLoc
DL
(
Base
)
;
SDValue
RC
=
CurDAG
->
getTargetConstant
(
TRC
->
getID
(
)
,
DL
,
MVT
::
i32
)
;
if
(
Base
.
getOpcode
(
)
!=
ISD
::
TargetFrameIndex
&&
Base
.
getOpcode
(
)
!=
ISD
::
Register
)
{
Base
=
SDValue
(
CurDAG
->
getMachineNode
(
TargetOpcode
::
COPY_TO_REGCLASS
,
DL
,
Base
.
getValueType
(
)
,
Base
,
RC
)
,
0
)
;
}
if
(
Index
.
getOpcode
(
)
!=
ISD
::
Register
)
{
Index
=
SDValue
(
CurDAG
->
getMachineNode
(
TargetOpcode
::
COPY_TO_REGCLASS
,
DL
,
Index
.
getValueType
(
)
,
Index
,
RC
)
,
0
)
;
}
OutOps
.
push_back
(
Base
)
;
OutOps
.
push_back
(
Disp
)
;
OutOps
.
push_back
(
Index
)
;
return
false
;
}
return
true
;
}
</s>

SelectInlineAsmMemoryOperand - Select the specified address as a target addressing mode , according to the specified constraint .


<s> static void aarch64_restore_callee_saves ( poly_int64 start_offset , unsigned start , unsigned limit , bool skip_wb , rtx * cfi_ops ) { unsigned regno ; unsigned regno2 ; poly_int64 offset ; rtx anchor_reg = NULL_RTX , ptrue = NULL_RTX ; for ( regno = aarch64_next_callee_save ( start , limit ) ; regno <= limit ; regno = aarch64_next_callee_save ( regno + 1 , limit ) ) { bool frame_related_p = aarch64_emit_cfi_for_reg_p ( regno ) ; if ( cfun -> machine -> reg_is_wrapped_separately [ regno ] ) continue ; rtx reg , mem ; if ( skip_wb && ( regno == cfun -> machine -> frame . wb_candidate1 || regno == cfun -> machine -> frame . wb_candidate2 ) ) continue ; machine_mode mode = aarch64_reg_save_mode ( regno ) ; reg = gen_rtx_REG ( mode , regno ) ; offset = start_offset + cfun -> machine -> frame . reg_offset [ regno ] ; rtx base_rtx = stack_pointer_rtx ; if ( mode == VNx2DImode && BYTES_BIG_ENDIAN ) aarch64_adjust_sve_callee_save_base ( mode , base_rtx , anchor_reg , offset , ptrue ) ; mem = gen_frame_mem ( mode , plus_constant ( Pmode , base_rtx , offset ) ) ; if ( ! aarch64_sve_mode_p ( mode ) && ( regno2 = aarch64_next_callee_save ( regno + 1 , limit ) ) <= limit && ! cfun -> machine -> reg_is_wrapped_separately [ regno2 ] && known_eq ( GET_MODE_SIZE ( mode ) , cfun -> machine -> frame . reg_offset [ regno2 ] - cfun -> machine -> frame . reg_offset [ regno ] ) ) { rtx reg2 = gen_rtx_REG ( mode , regno2 ) ; rtx mem2 ; offset += GET_MODE_SIZE ( mode ) ; mem2 = gen_frame_mem ( mode , plus_constant ( Pmode , base_rtx , offset ) ) ; emit_insn ( aarch64_gen_load_pair ( mode , reg , mem , reg2 , mem2 ) ) ; * cfi_ops = alloc_reg_note ( REG_CFA_RESTORE , reg2 , * cfi_ops ) ; regno = regno2 ; } else if ( mode == VNx2DImode && BYTES_BIG_ENDIAN ) emit_insn ( gen_aarch64_pred_mov ( mode , reg , ptrue , mem ) ) ; else if ( aarch64_sve_mode_p ( mode ) ) emit_insn ( gen_rtx_SET ( reg , mem ) ) ; else emit_move_insn ( reg , mem ) ; if ( frame_related_p ) * cfi_ops = alloc_reg_note ( REG_CFA_RESTORE , reg , * cfi_ops ) ; } } </s>

Emit code to restore the callee registers of mode MODE from register number START up to and including LIMIT . Restore from the stack offset START_OFFSET , skipping any write-back candidates if SKIP_WB is true . Write the appropriate REG_CFA_RESTORE notes into CFI_OPS .


<s> void pass_vsetvl :: compute_probabilities ( void ) { if ( ! optimize ) return ; edge e ; edge_iterator ei ; for ( const bb_info * bb : crtl -> ssa -> bbs ( ) ) { basic_block cfg_bb = bb -> cfg_bb ( ) ; auto & curr_prob = m_vector_manager -> vector_block_infos [ cfg_bb -> index ] . probability ; if ( ENTRY_BLOCK_PTR_FOR_FN ( cfun ) == cfg_bb ) curr_prob = profile_probability :: always ( ) ; if ( EXIT_BLOCK_PTR_FOR_FN ( cfun ) == cfg_bb ) continue ; gcc_assert ( curr_prob . initialized_p ( ) ) ; FOR_EACH_EDGE ( e , ei , cfg_bb -> succs ) { auto & new_prob = m_vector_manager -> vector_block_infos [ e -> dest -> index ] . probability ; if ( ! new_prob . initialized_p ( ) ) new_prob = curr_prob * e -> probability ; else if ( new_prob == profile_probability :: always ( ) ) continue ; else new_prob += curr_prob * e -> probability ; } } } </s>


<s> const LegalizerInfo * MipsSubtarget :: getLegalizerInfo ( ) const { return Legalizer . get ( ) ; } </s>

Expose LegalizerInfo so the clients can re-use .


<s> void MipsTargetELFStreamer :: finish ( ) { MCAssembler & MCA = getStreamer ( ) . getAssembler ( ) ; const MCObjectFileInfo & OFI = * MCA . getContext ( ) . getObjectFileInfo ( ) ; MCSectionData & TextSectionData = MCA . getOrCreateSectionData ( * OFI . getTextSection ( ) ) ; MCSectionData & DataSectionData = MCA . getOrCreateSectionData ( * OFI . getDataSection ( ) ) ; MCSectionData & BSSSectionData = MCA . getOrCreateSectionData ( * OFI . getBSSSection ( ) ) ; TextSectionData . setAlignment ( std :: max ( 16u , TextSectionData . getAlignment ( ) ) ) ; DataSectionData . setAlignment ( std :: max ( 16u , DataSectionData . getAlignment ( ) ) ) ; BSSSectionData . setAlignment ( std :: max ( 16u , BSSSectionData . getAlignment ( ) ) ) ; uint64_t Features = STI . getFeatureBits ( ) ; unsigned EFlags = MCA . getELFHeaderEFlags ( ) ; if ( getABI ( ) . IsO32 ( ) ) EFlags |= ELF :: EF_MIPS_ABI_O32 ; else if ( getABI ( ) . IsN32 ( ) ) EFlags |= ELF :: EF_MIPS_ABI2 ; if ( Features & Mips :: FeatureGP64Bit ) { if ( getABI ( ) . IsO32 ( ) ) EFlags |= ELF :: EF_MIPS_32BITMODE ; } else if ( Features & Mips :: FeatureMips64r2 || Features & Mips :: FeatureMips64 ) EFlags |= ELF :: EF_MIPS_32BITMODE ; if ( EFlags & ELF :: EF_MIPS_CPIC && getABI ( ) . IsN64 ( ) ) EFlags |= ELF :: EF_MIPS_PIC ; MCA . setELFHeaderEFlags ( EFlags ) ; MipsELFStreamer & MEF = static_cast < MipsELFStreamer & > ( Streamer ) ; MEF . EmitMipsOptionRecords ( ) ; emitMipsAbiFlags ( ) ; } </s>

finish - after all the new live ranges have been created , compute the remaining live range , and rewrite instructions to use the new registers .


<s> int legitimate_constant_address_p ( rtx x ) { return ( GET_CODE ( x ) == LABEL_REF || GET_CODE ( x ) == SYMBOL_REF || GET_CODE ( x ) == CONST_INT || GET_CODE ( x ) == CONST || GET_CODE ( x ) == HIGH ) ; } </s>

1 if X is an rtx for a constant that is a valid address .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . setPreservesCFG ( ) ; AU . addRequired < AAResultsWrapperPass > ( ) ; AU . addRequired < MachineDominatorTree > ( ) ; AU . addRequired < LiveIntervals > ( ) ; AU . addPreserved < MachineBlockFrequencyInfo > ( ) ; AU . addPreserved < SlotIndexes > ( ) ; AU . addPreserved < LiveIntervals > ( ) ; AU . addPreservedID ( LiveVariablesID ) ; AU . addPreserved < MachineDominatorTree > ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> static inline bool is_interrupt_func ( const_tree decl ) { return has_func_attr ( decl , "interrupt" ) || has_func_attr ( decl , "brk_interrupt" ) ; } </s>

Returns true if the provided function has the `` interrupt '' attribute .


<s> void DLXTargetObjectFile :: Initialize ( MCContext & Ctx , const TargetMachine & TM ) { TargetLoweringObjectFileELF :: Initialize ( Ctx , TM ) ; InitializeELF ( TM . Options . UseInitArray ) ; SmallDataSection = getContext ( ) . getELFSection ( ".sdata" , ELF :: SHT_PROGBITS , ELF :: SHF_WRITE | ELF :: SHF_ALLOC ) ; SmallBSSSection = getContext ( ) . getELFSection ( ".sbss" , ELF :: SHT_NOBITS , ELF :: SHF_WRITE | ELF :: SHF_ALLOC ) ; } </s>

This method must be called before any actual lowering is done .


<s> bool LanaiSetflagAluCombiner :: runOnMachineFunction ( MachineFunction & MF ) { if ( DisableSetflagAluCombiner ) return false ; bool Modified = false ; MfIterator End = MF . end ( ) ; for ( MfIterator MFI = MF . begin ( ) ; MFI != End ; ++ MFI ) { Modified |= CombineSetflagAluInBasicBlock ( & MF , & * MFI ) ; } return Modified ; } </s>

runOnMachineFunction - Emit the function body .


<s>
StringRef
getPassName
(
)
const
override
{
return
"MIPS16 Hard Float Pass"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> bool aarch64_can_const_movi_rtx_p ( rtx x , machine_mode mode ) { if ( ! TARGET_SIMD ) return false ; machine_mode vmode ; scalar_int_mode imode ; unsigned HOST_WIDE_INT ival ; if ( CONST_DOUBLE_P ( x ) && SCALAR_FLOAT_MODE_P ( mode ) ) { if ( ! aarch64_reinterpret_float_as_int ( x , & ival ) ) return false ; if ( aarch64_float_const_zero_rtx_p ( x ) ) return true ; imode = int_mode_for_mode ( mode ) . require ( ) ; } else if ( CONST_INT_P ( x ) && is_a < scalar_int_mode > ( mode , & imode ) ) ival = INTVAL ( x ) ; else return false ; int width = GET_MODE_BITSIZE ( imode ) == 64 ? 128 : 64 ; vmode = aarch64_simd_container_mode ( imode , width ) ; rtx v_op = aarch64_simd_gen_const_vector_dup ( vmode , ival ) ; return aarch64_simd_valid_immediate ( v_op , NULL ) ; } </s>

Return TRUE if rtx X is immediate constant that fits in a single MOVI immediate operation .


<s> static void nvptx_function_arg_advance ( cumulative_args_t cum_v , machine_mode ARG_UNUSED ( mode ) , const_tree ARG_UNUSED ( type ) , bool ARG_UNUSED ( named ) ) { CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; cum -> count ++ ; } </s>


"unexpected index-type in cris_print_index"

Print an index part of an address to file .


<s> unsigned PPCFrameLowering :: determineFrameLayout ( MachineFunction & MF , bool UpdateMF , bool UseEstimate ) const { MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; unsigned FrameSize = UseEstimate ? MFI . estimateStackSize ( MF ) : MFI . getStackSize ( ) ; unsigned TargetAlign = getStackAlignment ( ) ; unsigned MaxAlign = MFI . getMaxAlignment ( ) ; unsigned AlignMask = std :: max ( MaxAlign , TargetAlign ) - 1 ; const PPCRegisterInfo * RegInfo = static_cast < const PPCRegisterInfo * > ( Subtarget . getRegisterInfo ( ) ) ; bool DisableRedZone = MF . getFunction ( ) -> hasFnAttribute ( Attribute :: NoRedZone ) ; unsigned LR = RegInfo -> getRARegister ( ) ; if ( ! DisableRedZone && ( Subtarget . isPPC64 ( ) || ! Subtarget . isSVR4ABI ( ) || FrameSize == 0 ) && FrameSize <= 224 && ! MFI . hasVarSizedObjects ( ) && ! MFI . adjustsStack ( ) && ! MustSaveLR ( MF , LR ) && ! RegInfo -> hasBasePointer ( MF ) ) { if ( UpdateMF ) MFI . setStackSize ( 0 ) ; return 0 ; } unsigned maxCallFrameSize = MFI . getMaxCallFrameSize ( ) ; unsigned minCallFrameSize = getLinkageSize ( ) ; maxCallFrameSize = std :: max ( maxCallFrameSize , minCallFrameSize ) ; if ( MFI . hasVarSizedObjects ( ) ) maxCallFrameSize = ( maxCallFrameSize + AlignMask ) & ~ AlignMask ; if ( UpdateMF ) MFI . setMaxCallFrameSize ( maxCallFrameSize ) ; FrameSize += maxCallFrameSize ; FrameSize = ( FrameSize + AlignMask ) & ~ AlignMask ; if ( UpdateMF ) MFI . setStackSize ( FrameSize ) ; return FrameSize ; } </s>

Determine the frame layout but do not update the machine function .


<s>
void
MipsRegisterInfo
::
eliminateFrameIndex
(
MachineBasicBlock
::
iterator
II
,
int
SPAdj
,
unsigned
FIOperandNum
,
RegScavenger
*
RS
)
const
{
MachineInstr
&
MI
=
*
II
;
MachineFunction
&
MF
=
*
MI
.
getParent
(
)
->
getParent
(
)
;
LLVM_DEBUG
(
errs
(
)
<<
"\nFunction : "
<<
MF
.
getName
(
)
<<
"\n"
;
errs
(
)
<<
"<--------->\n"
<<
MI
)
;
int
FrameIndex
=
MI
.
getOperand
(
FIOperandNum
)
.
getIndex
(
)
;
uint64_t
stackSize
=
MF
.
getFrameInfo
(
)
.
getStackSize
(
)
;
int64_t
spOffset
=
MF
.
getFrameInfo
(
)
.
getObjectOffset
(
FrameIndex
)
;
LLVM_DEBUG
(
errs
(
)
<<
"FrameIndex : "
<<
FrameIndex
<<
"\n"
<<
"spOffset   : "
<<
spOffset
<<
"\n"
<<
"stackSize  : "
<<
stackSize
<<
"\n"
<<
"alignment  : "
<<
DebugStr
(
MF
.
getFrameInfo
(
)
.
getObjectAlign
(
FrameIndex
)
)
<<
"\n"
)
;
eliminateFI
(
MI
,
FIOperandNum
,
FrameIndex
,
stackSize
,
spOffset
)
;
}
</s>

This method must be overriden to eliminate abstract frame indices from instructions which may use them .

Mips
Mips
"\nFunction : "
"\n"
"<--------->\n"
"FrameIndex : "
"\n"
"spOffset   : "
"\n"
"stackSize  : "
"\n"
"alignment  : "
"\n"


<s> bool X86InstrInfo :: hasHighOperandLatency ( const InstrItineraryData * ItinData , const MachineRegisterInfo * MRI , const MachineInstr * DefMI , unsigned DefIdx , const MachineInstr * UseMI , unsigned UseIdx ) const { return isHighLatencyDef ( DefMI -> getOpcode ( ) ) ; } </s>

Compute operand latency between a def of 'Reg ' and a use in the current loop .


<s> bool X86TargetLowering :: mayBeEmittedAsTailCall ( const CallInst * CI ) const { auto Attr = CI -> getParent ( ) -> getParent ( ) -> getFnAttribute ( "disable-tail-calls" ) ; if ( ! CI -> isTailCall ( ) || Attr . getValueAsString ( ) == "true" ) return false ; ImmutableCallSite CS ( CI ) ; CallingConv :: ID CalleeCC = CS . getCallingConv ( ) ; if ( ! mayTailCallThisCC ( CalleeCC ) ) return false ; return true ; } </s>

Return true if the target may be able emit the call instruction as a tail call .


<s> static void rs6000_init_hard_regno_mode_ok ( void ) { int r , m ; for ( r = 0 ; r < FIRST_PSEUDO_REGISTER ; ++ r ) for ( m = 0 ; m < NUM_MACHINE_MODES ; ++ m ) if ( rs6000_hard_regno_mode_ok ( r , m ) ) rs6000_hard_regno_mode_ok_p [ m ] [ r ] = true ; } </s>

Initialize rs6000_hard_regno_mode_ok_p table .


"Found `main` function with incorrect type: "

runOnModule - Virtual method overriden by subclasses to process the module being operated on .


"%Klane index must be a constant immediate"

"%Ktotal size and element size must be a non-zero constant immediate"

Expand an AArch64 AdvSIMD builtin ( intrinsic ) .


<s> static bool isKnownNonNull ( SDValue Val , SelectionDAG & DAG , const AMDGPUTargetMachine & TM , unsigned AddrSpace ) { if ( isa < FrameIndexSDNode > ( Val ) || isa < GlobalAddressSDNode > ( Val ) || isa < BasicBlockSDNode > ( Val ) ) return true ; if ( auto * ConstVal = dyn_cast < ConstantSDNode > ( Val ) ) return ConstVal -> getSExtValue ( ) != TM . getNullPointerValue ( AddrSpace ) ; return false ; } </s>

Return true if we know that underlying value is nonnull .


<s> bool ARMRegisterInfo :: requiresRegisterScavenging ( const MachineFunction & MF ) const { const ARMFunctionInfo * AFI = MF . getInfo < ARMFunctionInfo > ( ) ; return ThumbRegScavenging || ! AFI -> isThumbFunction ( ) ; } </s>

Returns true if the target requires ( and can make use of ) the register scavenger .


<s> bool X86InstrInfo :: analyzeBranch ( MachineBasicBlock & MBB , MachineBasicBlock * & TBB , MachineBasicBlock * & FBB , SmallVectorImpl < MachineOperand > & Cond , bool AllowModify ) const { SmallVector < MachineInstr * , 4 > CondBranches ; return AnalyzeBranchImpl ( MBB , TBB , FBB , Cond , CondBranches , AllowModify ) ; } </s>

analyzeBranch - Analyze the branching code at the end of MBB , returning true if it can not be understood ( e.g .


<s>
void
NVPTXInstrInfo
::
copyPhysReg
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
DebugLoc
DL
,
unsigned
DestReg
,
unsigned
SrcReg
,
bool
KillSrc
)
const
{
if
(
NVPTX
::
Int32RegsRegClass
.
contains
(
DestReg
)
&&
NVPTX
::
Int32RegsRegClass
.
contains
(
SrcReg
)
)
BuildMI
(
MBB
,
I
,
DL
,
get
(
NVPTX
::
IMOV32rr
)
,
DestReg
)
.
addReg
(
SrcReg
,
getKillRegState
(
KillSrc
)
)
;
else
if
(
NVPTX
::
Int8RegsRegClass
.
contains
(
DestReg
)
&&
NVPTX
::
Int8RegsRegClass
.
contains
(
SrcReg
)
)
BuildMI
(
MBB
,
I
,
DL
,
get
(
NVPTX
::
IMOV8rr
)
,
DestReg
)
.
addReg
(
SrcReg
,
getKillRegState
(
KillSrc
)
)
;
else
if
(
NVPTX
::
Int1RegsRegClass
.
contains
(
DestReg
)
&&
NVPTX
::
Int1RegsRegClass
.
contains
(
SrcReg
)
)
BuildMI
(
MBB
,
I
,
DL
,
get
(
NVPTX
::
IMOV1rr
)
,
DestReg
)
.
addReg
(
SrcReg
,
getKillRegState
(
KillSrc
)
)
;
else
if
(
NVPTX
::
Float32RegsRegClass
.
contains
(
DestReg
)
&&
NVPTX
::
Float32RegsRegClass
.
contains
(
SrcReg
)
)
BuildMI
(
MBB
,
I
,
DL
,
get
(
NVPTX
::
FMOV32rr
)
,
DestReg
)
.
addReg
(
SrcReg
,
getKillRegState
(
KillSrc
)
)
;
else
if
(
NVPTX
::
Int16RegsRegClass
.
contains
(
DestReg
)
&&
NVPTX
::
Int16RegsRegClass
.
contains
(
SrcReg
)
)
BuildMI
(
MBB
,
I
,
DL
,
get
(
NVPTX
::
IMOV16rr
)
,
DestReg
)
.
addReg
(
SrcReg
,
getKillRegState
(
KillSrc
)
)
;
else
if
(
NVPTX
::
Int64RegsRegClass
.
contains
(
DestReg
)
&&
NVPTX
::
Int64RegsRegClass
.
contains
(
SrcReg
)
)
BuildMI
(
MBB
,
I
,
DL
,
get
(
NVPTX
::
IMOV64rr
)
,
DestReg
)
.
addReg
(
SrcReg
,
getKillRegState
(
KillSrc
)
)
;
else
if
(
NVPTX
::
Float64RegsRegClass
.
contains
(
DestReg
)
&&
NVPTX
::
Float64RegsRegClass
.
contains
(
SrcReg
)
)
BuildMI
(
MBB
,
I
,
DL
,
get
(
NVPTX
::
FMOV64rr
)
,
DestReg
)
.
addReg
(
SrcReg
,
getKillRegState
(
KillSrc
)
)
;
else
{
llvm_unreachable
(
"Don't know how to copy a register"
)
;
}
}
</s>


<s>
static
void
cr16_print_operand
(
FILE
*
file
,
rtx
x
,
int
code
)
{
int
ptr_dereference
=
0
;
switch
(
code
)
{
case
'd'
:
{
const
char
*
cr16_cmp_str
;
switch
(
GET_CODE
(
x
)
)
{
case
EQ
:
cr16_cmp_str
=
"eq"
;
break
;
case
NE
:
cr16_cmp_str
=
"ne"
;
break
;
case
GT
:
cr16_cmp_str
=
"lt"
;
break
;
case
GTU
:
cr16_cmp_str
=
"lo"
;
break
;
case
LT
:
cr16_cmp_str
=
"gt"
;
break
;
case
LTU
:
cr16_cmp_str
=
"hi"
;
break
;
case
GE
:
cr16_cmp_str
=
"le"
;
break
;
case
GEU
:
cr16_cmp_str
=
"ls"
;
break
;
case
LE
:
cr16_cmp_str
=
"ge"
;
break
;
case
LEU
:
cr16_cmp_str
=
"hs"
;
break
;
default
:
gcc_unreachable
(
)
;
}
fprintf
(
file
,
"%s"
,
cr16_cmp_str
)
;
return
;
}
case
'$'
:
putc
(
'$'
,
file
)
;
return
;
case
'p'
:
if
(
GET_CODE
(
x
)
==
REG
)
{
fprintf
(
file
,
"%s"
,
reg_names
[
REGNO
(
x
)
]
)
;
return
;
}
break
;
case
'b'
:
fprintf
(
file
,
"0x%lx"
,
INTVAL
(
x
)
)
;
return
;
case
'r'
:
fprintf
(
file
,
"%d"
,
cr16_operand_bit_pos
(
INTVAL
(
x
)
,
0
)
)
;
return
;
case
's'
:
fprintf
(
file
,
"%d"
,
cr16_operand_bit_pos
(
INTVAL
(
x
)
,
1
)
)
;
return
;
case
'g'
:
ptr_dereference
=
1
;
case
'f'
:
case
0
:
switch
(
GET_CODE
(
x
)
)
{
case
REG
:
if
(
GET_MODE_BITSIZE
(
GET_MODE
(
x
)
)
>
BITS_PER_WORD
)
{
if
(
LONG_REG_P
(
REGNO
(
x
)
)
)
fprintf
(
file
,
"(%s)"
,
reg_names
[
REGNO
(
x
)
]
)
;
else
fprintf
(
file
,
"(%s,%s)"
,
reg_names
[
REGNO
(
x
)
+
1
]
,
reg_names
[
REGNO
(
x
)
]
)
;
}
else
fprintf
(
file
,
"%s"
,
reg_names
[
REGNO
(
x
)
]
)
;
return
;
case
MEM
:
output_address
(
GET_MODE
(
x
)
,
XEXP
(
x
,
0
)
)
;
return
;
case
CONST_DOUBLE
:
{
long
l
;
REAL_VALUE_TO_TARGET_SINGLE
(
*
CONST_DOUBLE_REAL_VALUE
(
x
)
,
l
)
;
fprintf
(
file
,
"$0x%lx"
,
l
)
;
return
;
}
case
CONST_INT
:
{
fprintf
(
file
,
"$%ld"
,
INTVAL
(
x
)
)
;
return
;
}
case
UNSPEC
:
switch
(
XINT
(
x
,
1
)
)
{
default
:
gcc_unreachable
(
)
;
}
break
;
default
:
if
(
!
ptr_dereference
)
{
putc
(
'$'
,
file
)
;
}
cr16_print_operand_address
(
file
,
VOIDmode
,
x
)
;
return
;
}
default
:
output_operand_lossage
(
"invalid %%xn code"
)
;
}
gcc_unreachable
(
)
;
}
</s>

Implements the macro PRINT_OPERAND defined in cr16.h .


<s> rsqrts_type get_rsqrts_type ( machine_mode mode ) { switch ( mode ) { case DFmode : return gen_aarch64_rsqrts_df3 ; case SFmode : return gen_aarch64_rsqrts_sf3 ; case V2DFmode : return gen_aarch64_rsqrts_v2df3 ; case V2SFmode : return gen_aarch64_rsqrts_v2sf3 ; case V4SFmode : return gen_aarch64_rsqrts_v4sf3 ; default : gcc_unreachable ( ) ; } } </s>

Select reciprocal square root series step insn depending on machine mode .


<s> bool Z80Operand :: isReg ( ) const { return this -> Kind == k_Register ; } </s>


<s> SDNode * TeeRISCDAGToDAGISel :: Select ( SDNode * N ) { DebugLoc dl = N -> getDebugLoc ( ) ; if ( N -> isMachineOpcode ( ) ) return NULL ; switch ( N -> getOpcode ( ) ) { default : break ; case TeeRISC_ISD :: GLOBAL_BASE_REG : return getGlobalBaseReg ( ) ; } return SelectCode ( N ) ; } </s>

Main hook for targets to transform nodes into machine nodes .


<s> bool BPFAsmBackend :: writeNopData ( uint64_t Count , MCObjectWriter * OW ) const { if ( ( Count % 8 ) != 0 ) return false ; for ( uint64_t i = 0 ; i < Count ; i += 8 ) OW -> Write64 ( 0x15000000 ) ; return true ; } </s>

Write an ( optimal ) nop sequence of Count bytes to the given output .


<s>
void
Thumb1InstrInfo
::
loadRegFromStackSlot
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
Register
DestReg
,
int
FI
,
const
TargetRegisterClass
*
RC
,
const
TargetRegisterInfo
*
TRI
)
const
{
assert
(
(
RC
->
hasSuperClassEq
(
&
ARM
::
tGPRRegClass
)
||
(
Register
::
isPhysicalRegister
(
DestReg
)
&&
isARMLowRegister
(
DestReg
)
)
)
&&
"Unknown regclass!"
)
;
if
(
RC
->
hasSuperClassEq
(
&
ARM
::
tGPRRegClass
)
||
(
Register
::
isPhysicalRegister
(
DestReg
)
&&
isARMLowRegister
(
DestReg
)
)
)
{
DebugLoc
DL
;
if
(
I
!=
MBB
.
end
(
)
)
DL
=
I
->
getDebugLoc
(
)
;
MachineFunction
&
MF
=
*
MBB
.
getParent
(
)
;
MachineFrameInfo
&
MFI
=
MF
.
getFrameInfo
(
)
;
MachineMemOperand
*
MMO
=
MF
.
getMachineMemOperand
(
MachinePointerInfo
::
getFixedStack
(
MF
,
FI
)
,
MachineMemOperand
::
MOLoad
,
MFI
.
getObjectSize
(
FI
)
,
MFI
.
getObjectAlignment
(
FI
)
)
;
BuildMI
(
MBB
,
I
,
DL
,
get
(
ARM
::
tLDRspi
)
,
DestReg
)
.
addFrameIndex
(
FI
)
.
addImm
(
0
)
.
addMemOperand
(
MMO
)
.
add
(
predOps
(
ARMCC
::
AL
)
)
;
}
}
</s>

Load the specified register of the given register class from the specified stack frame index .

ARM
ARM::tGPRRegClass
ARM
"Unknown regclass!"
ARM::tGPRRegClass
ARM
ARM::tLDRspi
0
ARMCC::AL


<s> void expand_fusion_gpr_load ( rtx * operands ) { rtx addis_value = operands [ 1 ] ; rtx target = operands [ 2 ] ; rtx orig_mem = operands [ 3 ] ; rtx new_addr , new_mem , orig_addr , offset ; enum rtx_code plus_or_lo_sum ; machine_mode target_mode = GET_MODE ( target ) ; machine_mode extend_mode = target_mode ; machine_mode ptr_mode = Pmode ; enum rtx_code extend = UNKNOWN ; if ( GET_CODE ( orig_mem ) == ZERO_EXTEND || ( TARGET_P8_FUSION_SIGN && GET_CODE ( orig_mem ) == SIGN_EXTEND ) ) { extend = GET_CODE ( orig_mem ) ; orig_mem = XEXP ( orig_mem , 0 ) ; target_mode = GET_MODE ( orig_mem ) ; } gcc_assert ( MEM_P ( orig_mem ) ) ; orig_addr = XEXP ( orig_mem , 0 ) ; plus_or_lo_sum = GET_CODE ( orig_addr ) ; gcc_assert ( plus_or_lo_sum == PLUS || plus_or_lo_sum == LO_SUM ) ; offset = XEXP ( orig_addr , 1 ) ; new_addr = gen_rtx_fmt_ee ( plus_or_lo_sum , ptr_mode , addis_value , offset ) ; new_mem = replace_equiv_address_nv ( orig_mem , new_addr , false ) ; if ( extend != UNKNOWN ) new_mem = gen_rtx_fmt_e ( ZERO_EXTEND , extend_mode , new_mem ) ; new_mem = gen_rtx_UNSPEC ( extend_mode , gen_rtvec ( 1 , new_mem ) , UNSPEC_FUSION_GPR ) ; emit_insn ( gen_rtx_SET ( target , new_mem ) ) ; if ( extend == SIGN_EXTEND ) { int sub_off = ( ( BYTES_BIG_ENDIAN ) ? GET_MODE_SIZE ( extend_mode ) - GET_MODE_SIZE ( target_mode ) : 0 ) ; rtx sign_reg = simplify_subreg ( target_mode , target , extend_mode , sub_off ) ; emit_insn ( gen_rtx_SET ( target , gen_rtx_SIGN_EXTEND ( extend_mode , sign_reg ) ) ) ; } return ; } </s>

During the peephole2 pass , adjust and expand the insns for a load fusion sequence . We adjust the addis register to use the target register . If the load sign extends , we adjust the code to do the zero extending load , and an explicit sign extension later since the fusion only covers zero extending loads . The operands are : operands [ 0 ] register set with addis ( to be replaced with target ) operands [ 1 ] value set via addis operands [ 2 ] target register being loaded operands [ 3 ] D-form memory reference using operands [ 0 ] .


<s> bool ARM64TargetLowering :: isLegalAddImmediate ( int64_t Immed ) const { if ( ( Immed >> 12 ) == 0 || ( ( Immed & 0xfff ) == 0 && Immed >> 24 == 0 ) ) return true ; return false ; } </s>

Return true if the specified immediate is legal add immediate , that is the target has add instructions which can add a register and the immediate without having to materialize the immediate into a register .


<s> Cpu0TargetLowering :: ConstraintType Cpu0TargetLowering :: getConstraintType ( StringRef Constraint ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { default : break ; case 'c' : return C_RegisterClass ; case 'R' : return C_Memory ; } } return TargetLowering :: getConstraintType ( Constraint ) ; } </s>

Given a constraint letter , return the type of constraint for this target .


<s> static rtx altivec_expand_vec_ext_builtin ( tree exp , rtx target ) { machine_mode tmode , mode0 ; tree arg0 , arg1 ; rtx op0 ; rtx op1 ; arg0 = CALL_EXPR_ARG ( exp , 0 ) ; arg1 = CALL_EXPR_ARG ( exp , 1 ) ; op0 = expand_normal ( arg0 ) ; op1 = expand_normal ( arg1 ) ; if ( TREE_CODE ( arg1 ) == INTEGER_CST ) ( void ) get_element_number ( TREE_TYPE ( arg0 ) , arg1 ) ; tmode = TYPE_MODE ( TREE_TYPE ( TREE_TYPE ( arg0 ) ) ) ; mode0 = TYPE_MODE ( TREE_TYPE ( arg0 ) ) ; gcc_assert ( VECTOR_MODE_P ( mode0 ) ) ; op0 = force_reg ( mode0 , op0 ) ; if ( optimize || ! target || ! register_operand ( target , tmode ) ) target = gen_reg_rtx ( tmode ) ; rs6000_expand_vector_extract ( target , op0 , op1 ) ; return target ; } </s>


<s>
void
X86InstrInfo
::
reMaterialize
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
Register
DestReg
,
unsigned
SubIdx
,
const
MachineInstr
&
Orig
,
const
TargetRegisterInfo
&
TRI
)
const
{
bool
ClobbersEFLAGS
=
Orig
.
modifiesRegister
(
X86
::
EFLAGS
,
&
TRI
)
;
if
(
ClobbersEFLAGS
&&
!
isSafeToClobberEFLAGS
(
MBB
,
I
)
)
{
int
Value
;
switch
(
Orig
.
getOpcode
(
)
)
{
case
X86
::
MOV32r0
:
Value
=
0
;
break
;
case
X86
::
MOV32r1
:
Value
=
1
;
break
;
case
X86
::
MOV32r_1
:
Value
=
1
;
break
;
default
:
llvm_unreachable
(
"Unexpected instruction!"
)
;
}
const
DebugLoc
&
DL
=
Orig
.
getDebugLoc
(
)
;
BuildMI
(
MBB
,
I
,
DL
,
get
(
X86
::
MOV32ri
)
)
.
add
(
Orig
.
getOperand
(
0
)
)
.
addImm
(
Value
)
;
}
else
{
MachineInstr
*
MI
=
MBB
.
getParent
(
)
->
CloneMachineInstr
(
&
Orig
)
;
MBB
.
insert
(
I
,
MI
)
;
}
MachineInstr
&
NewMI
=
*
std
::
prev
(
I
)
;
NewMI
.
substituteRegister
(
Orig
.
getOperand
(
0
)
.
getReg
(
)
,
DestReg
,
SubIdx
,
TRI
)
;
}
</s>

Re-issue the specified 'original ' instruction at the specific location targeting a new destination register .


<s>
DecodeStatus
CAHPDisassembler
::
getInstruction
(
MCInst
&
MI
,
uint64_t
&
Size
,
ArrayRef
<
uint8_t
>
Bytes
,
uint64_t
Address
,
raw_ostream
&
OS
,
raw_ostream
&
CS
)
const
{
if
(
Bytes
.
size
(
)
<
2
)
{
Size
=
0
;
return
MCDisassembler
::
Fail
;
}
uint32_t
Inst
;
DecodeStatus
Result
;
uint8_t
is24bitInst
=
Bytes
[
0
]
&
1
;
if
(
is24bitInst
)
{
if
(
Bytes
.
size
(
)
<
3
)
{
Size
=
0
;
return
MCDisassembler
::
Fail
;
}
Inst
=
Bytes
[
0
]
|
(
Bytes
[
1
]
<<
8
)
|
(
Bytes
[
2
]
<<
16
)
;
LLVM_DEBUG
(
dbgs
(
)
<<
"Trying CAHP 24bit table :\n"
)
;
Result
=
decodeInstruction
(
DecoderTable24
,
MI
,
Inst
,
Address
,
this
,
STI
)
;
Size
=
3
;
}
else
{
if
(
Bytes
.
size
(
)
<
2
)
{
Size
=
0
;
return
MCDisassembler
::
Fail
;
}
Inst
=
support
::
endian
::
read16le
(
Bytes
.
data
(
)
)
;
LLVM_DEBUG
(
dbgs
(
)
<<
"Trying CAHP 16bit table :\n"
)
;
Result
=
decodeInstruction
(
DecoderTable16
,
MI
,
Inst
,
Address
,
this
,
STI
)
;
Size
=
2
;
}
return
Result
;
}
</s>

Returns the disassembly of a single instruction .


<s>
void
CSKYDAGToDAGISel
::
Select
(
SDNode
*
N
)
{
if
(
N
->
isMachineOpcode
(
)
)
{
LLVM_DEBUG
(
dbgs
(
)
<<
"== "
;
N
->
dump
(
CurDAG
)
;
dbgs
(
)
<<
"\n"
)
;
N
->
setNodeId
(
1
)
;
return
;
}
SDLoc
Dl
(
N
)
;
unsigned
Opcode
=
N
->
getOpcode
(
)
;
bool
IsSelected
=
false
;
switch
(
Opcode
)
{
default
:
break
;
case
ISD
::
ADDCARRY
:
IsSelected
=
selectAddCarry
(
N
)
;
break
;
case
ISD
::
SUBCARRY
:
IsSelected
=
selectSubCarry
(
N
)
;
break
;
case
ISD
::
GLOBAL_OFFSET_TABLE
:
{
Register
GP
=
Subtarget
->
getInstrInfo
(
)
->
getGlobalBaseReg
(
*
MF
)
;
ReplaceNode
(
N
,
CurDAG
->
getRegister
(
GP
,
N
->
getValueType
(
0
)
)
.
getNode
(
)
)
;
IsSelected
=
true
;
break
;
}
case
ISD
::
FrameIndex
:
{
SDValue
Imm
=
CurDAG
->
getTargetConstant
(
0
,
Dl
,
MVT
::
i32
)
;
int
FI
=
cast
<
FrameIndexSDNode
>
(
N
)
->
getIndex
(
)
;
SDValue
TFI
=
CurDAG
->
getTargetFrameIndex
(
FI
,
MVT
::
i32
)
;
ReplaceNode
(
N
,
CurDAG
->
getMachineNode
(
Subtarget
->
hasE2
(
)
CSKY
::
ADDI32
:
CSKY
::
ADDI16XZ
,
Dl
,
MVT
::
i32
,
TFI
,
Imm
)
)
;
IsSelected
=
true
;
break
;
}
case
ISD
::
INLINEASM
:
case
ISD
::
INLINEASM_BR
:
IsSelected
=
selectInlineAsm
(
N
)
;
break
;
}
if
(
IsSelected
)
return
;
SelectCode
(
N
)
;
}
</s>


"Caller should have handled 0-size case"

Emit target-specific code that performs a memcmp/bcmp , in cases where that is faster than a libcall .


<s> static int mmix_register_move_cost ( machine_mode mode ATTRIBUTE_UNUSED , reg_class_t from , reg_class_t to ) { return ( from == GENERAL_REGS && from == to ) ? 2 : 3 ; } </s>


<s>
static
void
loongarch_print_int_branch_condition
(
FILE
*
file
,
enum
rtx_code
code
,
int
letter
)
{
switch
(
code
)
{
case
EQ
:
case
NE
:
case
GT
:
case
GE
:
case
LT
:
case
LE
:
case
GTU
:
case
GEU
:
case
LTU
:
case
LEU
:
fputs
(
GET_RTX_NAME
(
code
)
,
file
)
;
break
;
default
:
output_operand_lossage
(
"'%%%c' is not a valid operand prefix"
,
letter
)
;
break
;
}
}
</s>

PRINT_OPERAND prefix LETTER refers to the integer branch instruction associated with condition CODE . Print the condition part of the opcode to FILE .

loongarch
"'%%%c' is not a valid operand prefix"


<s> void x86_function_profiler ( FILE * file , int labelno ATTRIBUTE_UNUSED ) { if ( TARGET_64BIT ) if ( flag_pic ) { fprintf ( file , "\tleaq\t%sP%d@(%%rip),%%r11\n" , LPREFIX , labelno ) ; fprintf ( file , "\tcall\t*%s@GOTPCREL(%%rip)\n" , MCOUNT_NAME ) ; } else { fprintf ( file , "\tmovq\t$%sP%d,%%r11\n" , LPREFIX , labelno ) ; fprintf ( file , "\tcall\t%s\n" , MCOUNT_NAME ) ; } else if ( flag_pic ) { fprintf ( file , "\tleal\t%sP%d@GOTOFF(%%ebx),%%%s\n" , LPREFIX , labelno , PROFILE_COUNT_REGISTER ) ; fprintf ( file , "\tcall\t*%s@GOT(%%ebx)\n" , MCOUNT_NAME ) ; } else { fprintf ( file , "\tmovl\t$%sP%d,%%%s\n" , LPREFIX , labelno , PROFILE_COUNT_REGISTER ) ; fprintf ( file , "\tcall\t%s\n" , MCOUNT_NAME ) ; } } </s>

Output assembler code to FILE to increment profiler label # LABELNO for profiling a function entry .


";; [Local] Removing membar %d since order"

";; [Local] Removing membar %d since the target"

" of %d is used before the I/O operation\n"

Go through block BB looking for membars to remove . There are two cases where intra-block analysis is enough : - a membar is redundant if it occurs between two consecutive I/O operations and if those operations are guaranteed to complete in order . - a membar for a __builtin_read is redundant if the result is used before the next I/O operation is issued . If the last membar in the block could not be removed , and there are guaranteed to be no I/O operations between that membar and the end of the block , store the membar in * LAST_MEMBAR , otherwise store null . Describe the block 's first I/O operation in * NEXT_IO . Describe an unknown operation if the block does n't do any I/O .


<s> unsigned AAPInstrInfo :: isStoreToStackSlot ( const MachineInstr & MI , int & FrameIndex ) const { switch ( MI . getOpcode ( ) ) { default : return 0 ; case AAP :: STB : case AAP :: STW : case AAP :: STB_postinc : case AAP :: STW_postinc : case AAP :: STB_predec : case AAP :: STW_predec : break ; } if ( MI . getOperand ( 0 ) . isFI ( ) && MI . getOperand ( 1 ) . isImm ( ) && MI . getOperand ( 1 ) . getImm ( ) == 0 ) { FrameIndex = MI . getOperand ( 0 ) . getIndex ( ) ; return MI . getOperand ( 2 ) . getReg ( ) ; } return 0 ; } </s>

isStoreToStackSlot - If the specified machine instruction is a direct store to a stack slot , return the virtual or physical register number of the source reg along with the FrameIndex of the loaded stack slot .


<s>
Function
*
MBlazeIntrinsicInfo
::
getDeclaration
(
Module
*
M
,
unsigned
IntrID
,
const
Type
*
*
Tys
,
unsigned
numTy
)
const
{
assert
(
!
isOverloaded
(
IntrID
)
&&
"MBlaze intrinsics are not overloaded"
)
;
AttrListPtr
AList
=
getAttributes
(
(
mblazeIntrinsic
::
ID
)
IntrID
)
;
return
cast
<
Function
>
(
M
->
getOrInsertFunction
(
getName
(
IntrID
)
,
getType
(
M
->
getContext
(
)
,
IntrID
)
,
AList
)
)
;
}
</s>

Create or insert an LLVM Function declaration for an intrinsic , and return it .

MBlaze
MBlaze
"MBlaze intrinsics are not overloaded"
mblazeIntrinsic::ID


<s> unsigned Z80MCCodeEmitter :: getMachineOpValue ( const MCInst & MI , const MCOperand & MO , SmallVectorImpl < MCFixup > & Fixups ) const { if ( MO . isReg ( ) ) { unsigned Reg = MO . getReg ( ) ; unsigned RegNo = Ctx . getRegisterInfo ( ) -> getEncodingValue ( Reg ) ; return RegNo ; } else if ( MO . isImm ( ) ) { return static_cast < unsigned > ( MO . getImm ( ) ) ; } else if ( MO . isExpr ( ) ) { if ( hasRegPrefix ( ) ) Fixups . push_back ( MCFixup :: Create ( 2 , MO . getExpr ( ) , FK_Data_2 ) ) ; else Fixups . push_back ( MCFixup :: Create ( 1 , MO . getExpr ( ) , FK_Data_2 ) ) ; } return 0 ; } </s>

getMachineOpValue - Return binary encoding of operand .


<s> bool TPCSetSpillBase :: runOnMachineFunction ( MachineFunction & MF ) { const TPCSubtarget & Subtarget = MF . getSubtarget < TPCSubtarget > ( ) ; TPCFrameLowering & FL = * const_cast < TPCFrameLowering * > ( Subtarget . getFrameLowering ( ) ) ; unsigned SpillVectorSz = FL . getSpillVectorDataSize ( ) ; if ( SpillVectorSz && Subtarget . hasAddr2 ( ) ) { MachineBasicBlock & MBB = * MF . begin ( ) ; DebugLoc DL = MBB . findDebugLoc ( MBB . instr_begin ( ) ) ; const MCInstrDesc & InstrDesc = Subtarget . getInstrInfo ( ) -> get ( TPC :: MOV_ld_sip ) ; const TPCTargetLowering & TL = * Subtarget . getTargetLowering ( ) ; unsigned ZR = TL . getZeroReg ( ) ; BuildMI ( MBB , MBB . instr_begin ( ) , DL , InstrDesc , ZR ) . addImm ( 0 ) . addImm ( TPCII :: OpType :: INT32 ) . addImm ( 0 ) . addReg ( ZR , RegState :: Undef ) . addReg ( TPC :: SP0 ) . addImm ( 0 ) ; return true ; } return false ; } </s>

runOnMachineFunction - Emit the function body .


<s> void ScheduleDAGPostRA :: updateQueues ( SUnit * SU , bool IsTopNode , bool IsBundled ) { if ( IsTopNode ) releaseSuccessors ( SU ) ; else releasePredecessors ( SU ) ; SU -> isScheduled = true ; if ( DFSResult ) { unsigned SubtreeID = DFSResult -> getSubtreeID ( SU ) ; if ( ! ScheduledTrees . test ( SubtreeID ) ) { ScheduledTrees . set ( SubtreeID ) ; DFSResult -> scheduleTree ( SubtreeID ) ; SchedImpl -> scheduleTree ( SubtreeID ) ; } } } </s>

Update scheduler DAG and queues after scheduling an instruction .


<s>
StringRef
getPassName
(
)
const
override
{
return
"WebAssembly Assembly Printer"
;
}
</s>

getPassName - Return a nice clean name for a pass .

WebAssembly
"WebAssembly Assembly Printer"


<s> void MipsOutgoingValueHandler :: assignValueToReg ( Register ValVReg , const CCValAssign & VA , const EVT & VT ) { Register PhysReg = VA . getLocReg ( ) ; if ( VT == MVT :: f64 && PhysReg >= Mips :: A0 && PhysReg <= Mips :: A3 ) { const MipsSubtarget & STI = static_cast < const MipsSubtarget & > ( MIRBuilder . getMF ( ) . getSubtarget ( ) ) ; bool IsEL = STI . isLittle ( ) ; auto Unmerge = MIRBuilder . buildUnmerge ( LLT :: scalar ( 32 ) , ValVReg ) ; MIRBuilder . buildCopy ( Register ( PhysReg + ( IsEL ? 0 : 1 ) ) , Unmerge . getReg ( 0 ) ) ; MIRBuilder . buildCopy ( Register ( PhysReg + ( IsEL ? 1 : 0 ) ) , Unmerge . getReg ( 1 ) ) ; } else if ( VT == MVT :: f32 && PhysReg >= Mips :: A0 && PhysReg <= Mips :: A3 ) { MIRBuilder . buildCopy ( PhysReg , ValVReg ) ; } else { Register ExtReg = extendRegister ( ValVReg , VA ) ; MIRBuilder . buildCopy ( PhysReg , ExtReg ) ; MIB . addUse ( PhysReg , RegState :: Implicit ) ; } } </s>

The specified value has been assigned to a physical register , handle the appropriate COPY ( either to or from ) and mark any relevant uses/defines as needed .


<s> SDValue Z80TargetLowering :: LowerCallResult ( SDValue Chain , SDValue Flag , CallingConv :: ID CallConv , bool isVarArg , const SmallVectorImpl < ISD :: InputArg > & Ins , SDLoc dl , SelectionDAG & DAG , SmallVectorImpl < SDValue > & InVals ) const { SmallVector < CCValAssign , 16 > RVLocs ; CCState CCInfo ( CallConv , isVarArg , DAG . getMachineFunction ( ) , getTargetMachine ( ) , RVLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeCallResult ( Ins , RetCC_Z80 ) ; for ( unsigned i = 0 , e = Ins . size ( ) ; i != e ; i ++ ) { Chain = DAG . getCopyFromReg ( Chain , dl , RVLocs [ i ] . getLocReg ( ) , RVLocs [ i ] . getValVT ( ) , Flag ) . getValue ( 1 ) ; Flag = Chain . getValue ( 2 ) ; InVals . push_back ( Chain . getValue ( 0 ) ) ; } return Chain ; } </s>

LowerCallResult - Lower the result values of an ISD : :CALL into the appropriate copies out of appropriate physical registers .


This is the top of the devritualization pass .


<s>
static
void
mips_file_end
(
void
)
{
tree
name_tree
;
struct
extern_list
*
p
;
if
(
extern_head
)
{
fputs
(
"\n"
,
asm_out_file
)
;
for
(
p
=
extern_head
;
p
!=
0
;
p
=
p
->
next
)
{
name_tree
=
get_identifier
(
p
->
name
)
;
if
(
!
TREE_ASM_WRITTEN
(
name_tree
)
&&
TREE_SYMBOL_REFERENCED
(
name_tree
)
)
{
TREE_ASM_WRITTEN
(
name_tree
)
=
1
;
if
(
TARGET_IRIX
&&
mips_abi
==
ABI_32
&&
p
->
size
==
1
)
{
fputs
(
"\t.globl "
,
asm_out_file
)
;
assemble_name
(
asm_out_file
,
p
->
name
)
;
fputs
(
" .text\n"
,
asm_out_file
)
;
}
else
{
fputs
(
"\t.extern\t"
,
asm_out_file
)
;
assemble_name
(
asm_out_file
,
p
->
name
)
;
fprintf
(
asm_out_file
,
", %d\n"
,
p
->
size
)
;
}
}
}
}
}
</s>

Implement TARGET_ASM_FILE_END . When using assembler macros , emit .externs for any small-data variables that turned out to be external .


<s> TargetPassConfig * StackPU2TargetMachine :: createPassConfig ( PassManagerBase & PM ) { return new StackPU2PassConfig ( * this , PM ) ; } </s>

Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of CodeGen passes .


<s> void HSAILPrintfInfo :: addOperand ( size_t idx , uint32_t size ) { mOperands . resize ( ( unsigned ) ( idx + 1 ) ) ; mOperands [ ( unsigned ) idx ] = size ; } </s>


<s> DecodeStatus PPCDisassembler :: getInstruction ( MCInst & MI , uint64_t & Size , ArrayRef < uint8_t > Bytes , uint64_t Address , raw_ostream & OS , raw_ostream & CS ) const { Size = 4 ; if ( Bytes . size ( ) < 4 ) { Size = 0 ; return MCDisassembler :: Fail ; } uint32_t Inst = IsLittleEndian ? support :: endian :: read32le ( Bytes . data ( ) ) : support :: endian :: read32be ( Bytes . data ( ) ) ; if ( STI . getFeatureBits ( ) [ PPC :: FeatureQPX ] ) { DecodeStatus result = decodeInstruction ( DecoderTableQPX32 , MI , Inst , Address , this , STI ) ; if ( result != MCDisassembler :: Fail ) return result ; MI . clear ( ) ; } return decodeInstruction ( DecoderTable32 , MI , Inst , Address , this , STI ) ; } </s>


"Wasn't expecting to be able to lower this!"

LowerOperation - Provide custom lowering hooks for some operations .


<s> RegisterBankInfo :: InstructionMappings AMDGPURegisterBankInfo :: getInstrAlternativeMappings ( const MachineInstr & MI ) const { const MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ; const MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; unsigned Size = getSizeInBits ( MI . getOperand ( 0 ) . getReg ( ) , MRI , * TRI ) ; InstructionMappings AltMappings ; switch ( MI . getOpcode ( ) ) { case TargetOpcode :: G_LOAD : { InstructionMapping SSMapping ( 1 , 1 , getOperandsMapping ( { AMDGPU :: getValueMapping ( AMDGPU :: SGPRRegBankID , Size ) , AMDGPU :: getValueMapping ( AMDGPU :: SGPRRegBankID , 64 ) } ) , 2 ) ; AltMappings . emplace_back ( std :: move ( SSMapping ) ) ; InstructionMapping VVMapping ( 2 , 1 , getOperandsMapping ( { AMDGPU :: getValueMapping ( AMDGPU :: VGPRRegBankID , Size ) , AMDGPU :: getValueMapping ( AMDGPU :: VGPRRegBankID , 64 ) } ) , 2 ) ; AltMappings . emplace_back ( std :: move ( VVMapping ) ) ; InstructionMapping VSMapping ( 3 , 1 , getOperandsMapping ( { AMDGPU :: getValueMapping ( AMDGPU :: VGPRRegBankID , Size ) , AMDGPU :: getValueMapping ( AMDGPU :: SGPRRegBankID , 64 ) } ) , 2 ) ; AltMappings . emplace_back ( std :: move ( VSMapping ) ) ; return AltMappings ; } default : break ; } return RegisterBankInfo :: getInstrAlternativeMappings ( MI ) ; } </s>


<s> void trackStatistics ( ) const override { } </s>

Hook to enable custom statistic tracking , called after manifest that resulted in a change if statistics are enabled .


<s>
bool
FPS
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
bool
FPIsUsed
=
false
;
static_assert
(
X86
::
FP6
==
X86
::
FP0
+
6
,
"Register enums aren't sorted right!"
)
;
for
(
unsigned
i
=
0
;
i
<=
6
;
++
i
)
if
(
MF
.
getRegInfo
(
)
.
isPhysRegUsed
(
X86
::
FP0
+
i
)
)
{
FPIsUsed
=
true
;
break
;
}
if
(
!
FPIsUsed
)
return
false
;
Bundles
=
&
getAnalysis
<
EdgeBundles
>
(
)
;
TII
=
MF
.
getSubtarget
(
)
.
getInstrInfo
(
)
;
bundleCFG
(
MF
)
;
StackTop
=
0
;
SmallPtrSet
<
MachineBasicBlock
*
,
8
>
Processed
;
MachineBasicBlock
*
Entry
=
MF
.
begin
(
)
;
bool
Changed
=
false
;
for
(
MachineBasicBlock
*
BB
:
depth_first_ext
(
Entry
,
Processed
)
)
Changed
|=
processBasicBlock
(
MF
,
*
BB
)
;
if
(
MF
.
size
(
)
!=
Processed
.
size
(
)
)
for
(
MachineFunction
::
iterator
BB
=
MF
.
begin
(
)
,
E
=
MF
.
end
(
)
;
BB
!=
E
;
++
BB
)
if
(
Processed
.
insert
(
BB
)
.
second
)
Changed
|=
processBasicBlock
(
MF
,
*
BB
)
;
LiveBundles
.
clear
(
)
;
return
Changed
;
}
</s>


<s> void arm_d_register_target_info ( void ) { const struct d_target_info_spec handlers [ ] = { { "floatAbi" , arm_d_handle_target_float_abi } , { NULL , NULL } , } ; d_add_target_info_handlers ( handlers ) ; } </s>


<s> const InstrItineraryData * getInstrItineraryData ( ) const override { return & InstrItins ; } </s>

getInstrItineraryData - Returns instruction itinerary data for the target or specific subtarget .


<s> bool shouldFormOverflowOp ( unsigned Opcode , EVT VT , bool MathUsed ) const override { return VT == MVT :: i32 || VT == MVT :: i64 ; } </s>

Overflow nodes should get combined/lowered to optimal instructions ( they should allow eliminating explicit compares by getting flags from math ops ) .


<s> void xstormy16_split_cbranch ( enum machine_mode mode , rtx label , rtx comparison , rtx dest , rtx carry ) { rtx op0 = XEXP ( comparison , 0 ) ; rtx op1 = XEXP ( comparison , 1 ) ; rtx seq , last_insn ; rtx compare ; start_sequence ( ) ; xstormy16_expand_arith ( mode , COMPARE , dest , op0 , op1 , carry ) ; seq = get_insns ( ) ; end_sequence ( ) ; gcc_assert ( INSN_P ( seq ) ) ; last_insn = seq ; while ( NEXT_INSN ( last_insn ) != NULL_RTX ) last_insn = NEXT_INSN ( last_insn ) ; compare = SET_SRC ( XVECEXP ( PATTERN ( last_insn ) , 0 , 0 ) ) ; PUT_CODE ( XEXP ( compare , 0 ) , GET_CODE ( comparison ) ) ; XEXP ( compare , 1 ) = gen_rtx_LABEL_REF ( VOIDmode , label ) ; emit_insn ( seq ) ; } </s>

Take a SImode conditional branch , one of GT/LE/GTU/LEU , and split the arithmetic operation . Most of the work is done by xstormy16_expand_arith .


<s> static bool aarch64_rtx_arith_op_extract_p ( rtx x , scalar_int_mode mode ) { if ( GET_CODE ( x ) == SIGN_EXTRACT || GET_CODE ( x ) == ZERO_EXTRACT ) { rtx op0 = XEXP ( x , 0 ) ; rtx op1 = XEXP ( x , 1 ) ; rtx op2 = XEXP ( x , 2 ) ; if ( GET_CODE ( op0 ) == MULT && CONST_INT_P ( op1 ) && op2 == const0_rtx && CONST_INT_P ( XEXP ( op0 , 1 ) ) && aarch64_is_extend_from_extract ( mode , XEXP ( op0 , 1 ) , op1 ) ) { return true ; } } else if ( GET_CODE ( x ) == SIGN_EXTEND || GET_CODE ( x ) == ZERO_EXTEND ) return REG_P ( XEXP ( x , 0 ) ) ; return false ; } </s>

Return true if X is a zero or sign extract usable in an ADD or SUB ( extended register ) instruction .


<s> void rs6000_aix_emit_builtin_unwind_init ( void ) { rtx mem ; rtx stack_top = gen_reg_rtx ( Pmode ) ; rtx opcode_addr = gen_reg_rtx ( Pmode ) ; rtx opcode = gen_reg_rtx ( SImode ) ; rtx tocompare = gen_reg_rtx ( SImode ) ; rtx no_toc_save_needed = gen_label_rtx ( ) ; mem = gen_frame_mem ( Pmode , hard_frame_pointer_rtx ) ; emit_move_insn ( stack_top , mem ) ; mem = gen_frame_mem ( Pmode , gen_rtx_PLUS ( Pmode , stack_top , GEN_INT ( 2 * GET_MODE_SIZE ( Pmode ) ) ) ) ; emit_move_insn ( opcode_addr , mem ) ; emit_move_insn ( opcode , gen_rtx_MEM ( SImode , opcode_addr ) ) ; emit_move_insn ( tocompare , gen_int_mode ( TARGET_32BIT ? 0x80410014 : 0xE8410028 , SImode ) ) ; do_compare_rtx_and_jump ( opcode , tocompare , EQ , 1 , SImode , NULL_RTX , NULL_RTX , no_toc_save_needed ) ; mem = gen_frame_mem ( Pmode , gen_rtx_PLUS ( Pmode , stack_top , GEN_INT ( 5 * GET_MODE_SIZE ( Pmode ) ) ) ) ; emit_move_insn ( mem , gen_rtx_REG ( Pmode , 2 ) ) ; emit_label ( no_toc_save_needed ) ; } </s>

If _Unwind_ * has been called from within the same module , toc register is not guaranteed to be saved to 40 ( 1 ) on function entry . Save it there in that case .


<s> void SITargetLowering :: LowerAsmOperandForConstraint ( SDValue Op , std :: string & Constraint , std :: vector < SDValue > & Ops , SelectionDAG & DAG ) const { if ( Constraint . length ( ) == 1 && Constraint [ 0 ] == 'A' ) { LowerAsmOperandForConstraintA ( Op , Ops , DAG ) ; } else { TargetLowering :: LowerAsmOperandForConstraint ( Op , Constraint , Ops , DAG ) ; } } </s>

Lower the specified operand into the Ops vector .


<s> TargetLowering :: AtomicExpansionKind RISCVTargetLowering :: shouldExpandAtomicRMWInIR ( AtomicRMWInst * AI ) const { if ( AI -> isFloatingPointOperation ( ) ) return AtomicExpansionKind :: CmpXChg ; unsigned Size = AI -> getType ( ) -> getPrimitiveSizeInBits ( ) ; if ( ( Size == 8 || Size == 16 ) && ! RISCVABI :: isCheriPureCapABI ( Subtarget . getTargetABI ( ) ) ) return AtomicExpansionKind :: MaskedIntrinsic ; return AtomicExpansionKind :: None ; } </s>

Returns how the IR-level AtomicExpand pass should expand the given AtomicRMW , if at all .


<s> static int ix86_builtin_vectorization_cost ( enum vect_cost_for_stmt type_of_cost , tree vectype , int ) { bool fp = false ; machine_mode mode = TImode ; int index ; if ( vectype != NULL ) { fp = FLOAT_TYPE_P ( vectype ) ; mode = TYPE_MODE ( vectype ) ; } switch ( type_of_cost ) { case scalar_stmt : return fp ? ix86_cost -> addss : COSTS_N_INSNS ( 1 ) ; case scalar_load : return COSTS_N_INSNS ( fp ? ix86_cost -> sse_load [ 0 ] : ix86_cost -> int_load [ 2 ] ) / 2 ; case scalar_store : return COSTS_N_INSNS ( fp ? ix86_cost -> sse_store [ 0 ] : ix86_cost -> int_store [ 2 ] ) / 2 ; case vector_stmt : return ix86_vec_cost ( mode , fp ? ix86_cost -> addss : ix86_cost -> sse_op ) ; case vector_load : index = sse_store_index ( mode ) ; if ( index < 0 ) index = 2 ; return COSTS_N_INSNS ( ix86_cost -> sse_load [ index ] ) / 2 ; case vector_store : index = sse_store_index ( mode ) ; if ( index < 0 ) index = 2 ; return COSTS_N_INSNS ( ix86_cost -> sse_store [ index ] ) / 2 ; case vec_to_scalar : case scalar_to_vec : return ix86_vec_cost ( mode , ix86_cost -> sse_op ) ; case unaligned_load : index = sse_store_index ( mode ) ; if ( index < 0 ) index = 2 ; return COSTS_N_INSNS ( ix86_cost -> sse_unaligned_load [ index ] ) / 2 ; case unaligned_store : index = sse_store_index ( mode ) ; if ( index < 0 ) index = 2 ; return COSTS_N_INSNS ( ix86_cost -> sse_unaligned_store [ index ] ) / 2 ; case vector_gather_load : return ix86_vec_cost ( mode , COSTS_N_INSNS ( ix86_cost -> gather_static + ix86_cost -> gather_per_elt * TYPE_VECTOR_SUBPARTS ( vectype ) ) / 2 ) ; case vector_scatter_store : return ix86_vec_cost ( mode , COSTS_N_INSNS ( ix86_cost -> scatter_static + ix86_cost -> scatter_per_elt * TYPE_VECTOR_SUBPARTS ( vectype ) ) / 2 ) ; case cond_branch_taken : return ix86_cost -> cond_taken_branch_cost ; case cond_branch_not_taken : return ix86_cost -> cond_not_taken_branch_cost ; case vec_perm : case vec_promote_demote : return ix86_vec_cost ( mode , ix86_cost -> sse_op ) ; case vec_construct : { int n = TYPE_VECTOR_SUBPARTS ( vectype ) ; if ( GET_MODE_BITSIZE ( mode ) <= 128 ) return ( n - 1 ) * ix86_cost -> sse_op ; else if ( GET_MODE_BITSIZE ( mode ) == 256 ) return ( ( n - 2 ) * ix86_cost -> sse_op + ix86_vec_cost ( mode , ix86_cost -> addss ) ) ; else if ( GET_MODE_BITSIZE ( mode ) == 512 ) return ( ( n - 4 ) * ix86_cost -> sse_op + 3 * ix86_vec_cost ( mode , ix86_cost -> addss ) ) ; gcc_unreachable ( ) ; } default : gcc_unreachable ( ) ; } } </s>


<s> bool MemSelOpt :: processInstruction ( MachineInstr * MI ) { bool Changed = false ; unsigned NumOperands = MI -> getNumOperands ( ) ; if ( NumOperands == 0 ) return false ; const TargetInstrDesc & TID = TII -> get ( MI -> getOpcode ( ) ) ; if ( ! ( TID . isBranch ( ) || TID . isCall ( ) || TID . mayLoad ( ) || TID . mayStore ( ) ) ) return false ; int MemOpPos = - 1 ; for ( unsigned i = 0 ; i < NumOperands ; i ++ ) { MachineOperand Op = MI -> getOperand ( i ) ; if ( Op . getType ( ) == MachineOperand :: MO_GlobalAddress || Op . getType ( ) == MachineOperand :: MO_ExternalSymbol || Op . getType ( ) == MachineOperand :: MO_MachineBasicBlock ) { MemOpPos = i ; break ; } } if ( MemOpPos == - 1 ) return Changed ; MachineOperand & Op = MI -> getOperand ( MemOpPos ) ; if ( MI -> getOpcode ( ) == PIC16 :: CALL || MI -> getOpcode ( ) == PIC16 :: br_uncond ) { DebugLoc dl = MI -> getDebugLoc ( ) ; BuildMI ( * MBB , MI , dl , TII -> get ( PIC16 :: pagesel ) ) . addOperand ( Op ) ; return true ; } std :: string NewBank = CurBank ; if ( Op . getType ( ) == MachineOperand :: MO_GlobalAddress && Op . getGlobal ( ) -> getType ( ) -> getAddressSpace ( ) == PIC16ISD :: RAM_SPACE ) { NewBank = Op . getGlobal ( ) -> getSection ( ) ; } else if ( Op . getType ( ) == MachineOperand :: MO_ExternalSymbol ) { std :: string Sym = Op . getSymbolName ( ) ; NewBank = PAN :: getSectionNameForSym ( Sym ) ; } if ( NewBank . compare ( CurBank ) != 0 ) { DebugLoc dl = MI -> getDebugLoc ( ) ; BuildMI ( * MBB , MI , dl , TII -> get ( PIC16 :: banksel ) ) . addOperand ( Op ) ; Changed = true ; CurBank = NewBank ; } return Changed ; } </s>

Process a single instruction and collect debug info anchors .


<s>
SDValue
AMDGPUTargetLowering
::
LowerOperation
(
SDValue
Op
,
SelectionDAG
&
DAG
)
const
{
switch
(
Op
.
getOpcode
(
)
)
{
default
:
Op
.
getNode
(
)
->
dump
(
)
;
llvm_unreachable
(
"Custom lowering code for this"
"instruction is not implemented yet!"
)
;
break
;
case
ISD
::
SIGN_EXTEND_INREG
:
return
LowerSIGN_EXTEND_INREG
(
Op
,
DAG
)
;
case
ISD
::
CONCAT_VECTORS
:
return
LowerCONCAT_VECTORS
(
Op
,
DAG
)
;
case
ISD
::
EXTRACT_SUBVECTOR
:
return
LowerEXTRACT_SUBVECTOR
(
Op
,
DAG
)
;
case
ISD
::
FrameIndex
:
return
LowerFrameIndex
(
Op
,
DAG
)
;
case
ISD
::
INTRINSIC_WO_CHAIN
:
return
LowerINTRINSIC_WO_CHAIN
(
Op
,
DAG
)
;
case
ISD
::
SDIV
:
return
LowerSDIV
(
Op
,
DAG
)
;
case
ISD
::
SREM
:
return
LowerSREM
(
Op
,
DAG
)
;
case
ISD
::
UDIVREM
:
return
LowerUDIVREM
(
Op
,
DAG
)
;
case
ISD
::
SDIVREM
:
return
LowerSDIVREM
(
Op
,
DAG
)
;
case
ISD
::
FCEIL
:
return
LowerFCEIL
(
Op
,
DAG
)
;
case
ISD
::
FTRUNC
:
return
LowerFTRUNC
(
Op
,
DAG
)
;
case
ISD
::
FRINT
:
return
LowerFRINT
(
Op
,
DAG
)
;
case
ISD
::
FNEARBYINT
:
return
LowerFNEARBYINT
(
Op
,
DAG
)
;
case
ISD
::
FFLOOR
:
return
LowerFFLOOR
(
Op
,
DAG
)
;
case
ISD
::
UINT_TO_FP
:
return
LowerUINT_TO_FP
(
Op
,
DAG
)
;
}
return
Op
;
}
</s>

R600
"Custom lowering code for this"
"instruction is not implemented yet!"
ISD::SIGN_EXTEND_INREG
SI
ISD::CONCAT_VECTORS
ISD::EXTRACT_SUBVECTOR
ISD::FrameIndex
ISD::INTRINSIC_WO_CHAIN
SI
ISD::SDIV
ISD::SREM
ISD::UDIVREM
ISD::SDIVREM
ISD::FCEIL
ISD::FTRUNC
ISD::FRINT
ISD::FNEARBYINT
ISD::FFLOOR
ISD::UINT_TO_FP


<s>
const
char
*
mips_output_conditional_branch
(
rtx_insn
*
insn
,
rtx
*
operands
,
const
char
*
branch_if_true
,
const
char
*
branch_if_false
)
{
unsigned
int
length
;
rtx
taken
;
gcc_assert
(
LABEL_P
(
operands
[
0
]
)
)
;
length
=
get_attr_length
(
insn
)
;
if
(
length
<=
8
)
{
mips_branch_likely
=
(
final_sequence
&&
INSN_ANNULLED_BRANCH_P
(
insn
)
)
;
return
branch_if_true
;
}
mips_branch_likely
=
false
;
rtx_code_label
*
not_taken
=
gen_label_rtx
(
)
;
taken
=
operands
[
0
]
;
operands
[
0
]
=
not_taken
;
output_asm_insn
(
branch_if_false
,
operands
)
;
if
(
final_sequence
)
{
if
(
!
INSN_ANNULLED_BRANCH_P
(
insn
)
)
{
final_scan_insn
(
final_sequence
->
insn
(
1
)
,
asm_out_file
,
optimize
,
1
,
)
;
final_sequence
->
insn
(
1
)
->
set_deleted
(
)
;
}
else
output_asm_insn
(
"nop"
,
0
)
;
fprintf
(
asm_out_file
,
"\n"
)
;
}
if
(
TARGET_ABSOLUTE_JUMPS
&&
TARGET_CB_MAYBE
)
{
if
(
!
final_sequence
)
{
output_asm_insn
(
"nop\t\t# hazard nop"
,
0
)
;
fprintf
(
asm_out_file
,
"\n"
)
;
}
output_asm_insn
(
MIPS_ABSOLUTE_JUMP
(
"bc\t%0"
)
,
&
taken
)
;
}
else
if
(
TARGET_ABSOLUTE_JUMPS
)
output_asm_insn
(
MIPS_ABSOLUTE_JUMP
(
"j\t%0%/"
)
,
&
taken
)
;
else
{
mips_output_load_label
(
taken
)
;
if
(
TARGET_CB_MAYBE
)
output_asm_insn
(
"jrc\t%@%]"
,
0
)
;
else
output_asm_insn
(
"jr\t%@%]%/"
,
0
)
;
}
if
(
final_sequence
)
{
if
(
INSN_ANNULLED_BRANCH_P
(
insn
)
)
{
final_scan_insn
(
final_sequence
->
insn
(
1
)
,
asm_out_file
,
optimize
,
1
,
)
;
final_sequence
->
insn
(
1
)
->
set_deleted
(
)
;
}
else
if
(
TARGET_CB_NEVER
)
output_asm_insn
(
"nop"
,
0
)
;
fprintf
(
asm_out_file
,
"\n"
)
;
}
targetm
.
asm_out
.
internal_label
(
asm_out_file
,
"L"
,
CODE_LABEL_NUMBER
(
not_taken
)
)
;
return
""
;
}
</s>

Output assembly instructions to peform a conditional branch . INSN is the branch instruction . OPERANDS [ 0 ] is the condition . OPERANDS [ 1 ] is the target of the branch . OPERANDS [ 2 ] is the target of the first operand to the condition . If TWO_OPERANDS_P is nonzero the comparison takes two operands ; OPERANDS [ 3 ] will be the second operand . If INVERTED_P is nonzero we are to branch if the condition does not hold . If FLOAT_P is nonzero this is a floating-point comparison . LENGTH is the length ( in bytes ) of the sequence we are to generate . That tells us whether to generate a simple conditional branch , or a reversed conditional branch around a ` jr ' instruction .


<s> static unsigned ix86_add_stmt_cost ( void * data , int count , enum vect_cost_for_stmt kind , struct _stmt_vec_info * stmt_info , int misalign , enum vect_cost_model_location where ) { unsigned * cost = ( unsigned * ) data ; unsigned retval = 0 ; tree vectype = stmt_info ? stmt_vectype ( stmt_info ) : NULL_TREE ; int stmt_cost = ix86_builtin_vectorization_cost ( kind , vectype , misalign ) ; if ( TARGET_BONNELL && kind == vector_stmt && vectype && GET_MODE_INNER ( TYPE_MODE ( vectype ) ) == DFmode ) stmt_cost *= 5 ; if ( where == vect_body && stmt_info && stmt_in_inner_loop_p ( stmt_info ) ) count *= 50 ; retval = ( unsigned ) ( count * stmt_cost ) ; if ( ( TARGET_SILVERMONT || TARGET_INTEL ) && stmt_info && stmt_info -> stmt ) { tree lhs_op = gimple_get_lhs ( stmt_info -> stmt ) ; if ( lhs_op && TREE_CODE ( TREE_TYPE ( lhs_op ) ) == INTEGER_TYPE ) retval = ( retval * 17 ) / 10 ; } cost [ where ] += retval ; return retval ; } </s>


<s> bool isThumb ( const MCSubtargetInfo & STI ) const { return STI . getFeatureBits ( ) [ ARM :: ModeThumb ] ; } </s>

Tests whether the target is Thumb ( little and big endian ) .


"AMD IL Control Flow Graph structurizer Pass"

getPassName - Return a nice clean name for a pass .


<s> bool R600TargetLowering :: allowsMisalignedMemoryAccesses ( EVT VT , unsigned AddrSpace , unsigned Align , MachineMemOperand :: Flags Flags , bool * IsFast ) const { if ( IsFast ) * IsFast = false ; if ( ! VT . isSimple ( ) || VT == MVT :: Other ) return false ; if ( VT . bitsLT ( MVT :: i32 ) ) return false ; if ( IsFast ) * IsFast = true ; return VT . bitsGT ( MVT :: i32 ) && Align % 4 == 0 ; } </s>

Returns true if the target allows unaligned memory accesses of the specified type .


<s> const TargetRegisterInfo & XtensaInstrInfo :: getRegisterInfo ( ) const { return RI ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s> bool AArch64AsmParser :: ParseDirective ( AsmToken DirectiveID ) { const MCObjectFileInfo :: Environment Format = getContext ( ) . getObjectFileInfo ( ) -> getObjectFileType ( ) ; bool IsMachO = Format == MCObjectFileInfo :: IsMachO ; bool IsCOFF = Format == MCObjectFileInfo :: IsCOFF ; StringRef IDVal = DirectiveID . getIdentifier ( ) ; SMLoc Loc = DirectiveID . getLoc ( ) ; if ( IDVal == ".arch" ) parseDirectiveArch ( Loc ) ; else if ( IDVal == ".cpu" ) parseDirectiveCPU ( Loc ) ; else if ( IDVal == ".tlsdesccall" ) parseDirectiveTLSDescCall ( Loc ) ; else if ( IDVal == ".ltorg" || IDVal == ".pool" ) parseDirectiveLtorg ( Loc ) ; else if ( IDVal == ".unreq" ) parseDirectiveUnreq ( Loc ) ; else if ( ! IsMachO && ! IsCOFF ) { if ( IDVal == ".inst" ) parseDirectiveInst ( Loc ) ; else return true ; } else if ( IDVal == MCLOHDirectiveName ( ) ) parseDirectiveLOH ( IDVal , Loc ) ; else return true ; return false ; } </s>

ParseDirective - Parse a target specific assembler directive This method is deprecated , use 'parseDirective ' instead .


<s> unsigned HexagonInstrInfo :: isStoreToStackSlot ( const MachineInstr * MI , int & FrameIndex ) const { switch ( MI -> getOpcode ( ) ) { default : break ; case Hexagon :: S2_storerb_io : case Hexagon :: S2_storerh_io : case Hexagon :: S2_storeri_io : case Hexagon :: S2_storerd_io : case Hexagon :: V6_vS32b_ai : case Hexagon :: V6_vS32b_ai_128B : case Hexagon :: V6_vS32Ub_ai : case Hexagon :: V6_vS32Ub_ai_128B : case Hexagon :: STriw_pred : case Hexagon :: STriw_mod : case Hexagon :: STriq_pred_V6 : case Hexagon :: STriq_pred_vec_V6 : case Hexagon :: STriv_pseudo_V6 : case Hexagon :: STrivv_pseudo_V6 : case Hexagon :: STriq_pred_V6_128B : case Hexagon :: STriq_pred_vec_V6_128B : case Hexagon :: STriv_pseudo_V6_128B : case Hexagon :: STrivv_pseudo_V6_128B : { const MachineOperand & OpFI = MI -> getOperand ( 0 ) ; if ( ! OpFI . isFI ( ) ) return 0 ; const MachineOperand & OpOff = MI -> getOperand ( 1 ) ; if ( ! OpOff . isImm ( ) || OpOff . getImm ( ) != 0 ) return 0 ; FrameIndex = OpFI . getIndex ( ) ; return MI -> getOperand ( 2 ) . getReg ( ) ; } case Hexagon :: S2_pstorerbt_io : case Hexagon :: S2_pstorerbf_io : case Hexagon :: S2_pstorerht_io : case Hexagon :: S2_pstorerhf_io : case Hexagon :: S2_pstorerit_io : case Hexagon :: S2_pstorerif_io : case Hexagon :: S2_pstorerdt_io : case Hexagon :: S2_pstorerdf_io : { const MachineOperand & OpFI = MI -> getOperand ( 1 ) ; if ( ! OpFI . isFI ( ) ) return 0 ; const MachineOperand & OpOff = MI -> getOperand ( 2 ) ; if ( ! OpOff . isImm ( ) || OpOff . getImm ( ) != 0 ) return 0 ; FrameIndex = OpFI . getIndex ( ) ; return MI -> getOperand ( 3 ) . getReg ( ) ; } } return 0 ; } </s>

isStoreToStackSlot - If the specified machine instruction is a direct store to a stack slot , return the virtual or physical register number of the source reg along with the FrameIndex of the loaded stack slot .


<s> static rtx transcode_memory_rtx ( rtx m , rtx newbase , rtx before ) { rtx base , index , addendr ; int addend = 0 ; int need_es = 0 ; if ( ! MEM_P ( m ) ) return m ; if ( GET_MODE ( XEXP ( m , 0 ) ) == SImode ) { rtx new_m ; rtx seg = rl78_hi8 ( XEXP ( m , 0 ) ) ; if ( ! TARGET_ES0 ) { emit_insn_before ( EM ( gen_movqi ( A , seg ) ) , before ) ; emit_insn_before ( EM ( gen_movqi_to_es ( A ) ) , before ) ; } record_content ( A , NULL_RTX ) ; new_m = gen_rtx_MEM ( GET_MODE ( m ) , rl78_lo16 ( XEXP ( m , 0 ) ) ) ; MEM_COPY_ATTRIBUTES ( new_m , m ) ; m = new_m ; need_es = 1 ; } characterize_address ( XEXP ( m , 0 ) , & base , & index , & addendr ) ; gcc_assert ( index == NULL_RTX ) ; if ( base == NULL_RTX ) return m ; if ( addendr && GET_CODE ( addendr ) == CONST_INT ) addend = INTVAL ( addendr ) ; gcc_assert ( REG_P ( base ) ) ; gcc_assert ( REG_P ( newbase ) ) ; int limit = 256 - GET_MODE_SIZE ( GET_MODE ( m ) ) ; if ( REGNO ( base ) == SP_REG ) { if ( addend >= 0 && addend <= limit ) return m ; } if ( addend < 0 || ( addend > limit && REGNO ( newbase ) != BC_REG ) || ( addendr && ( GET_CODE ( addendr ) != CONST_INT ) && ( ( REGNO ( newbase ) != BC_REG ) ) ) ) { EM ( emit_insn_before ( gen_movhi ( AX , base ) , before ) ) ; EM ( emit_insn_before ( gen_addhi3 ( AX , AX , addendr ) , before ) ) ; EM ( emit_insn_before ( gen_movhi ( newbase , AX ) , before ) ) ; record_content ( AX , NULL_RTX ) ; record_content ( newbase , NULL_RTX ) ; base = newbase ; addend = 0 ; addendr = 0 ; } else { base = gen_and_emit_move ( newbase , base , before , true ) ; } if ( addend ) { record_content ( base , NULL_RTX ) ; base = gen_rtx_PLUS ( HImode , base , GEN_INT ( addend ) ) ; } else if ( addendr ) { record_content ( base , NULL_RTX ) ; base = gen_rtx_PLUS ( HImode , base , addendr ) ; } if ( need_es ) { m = change_address ( m , GET_MODE ( m ) , gen_es_addr ( base ) ) ; cfun -> machine -> uses_es = true ; } else m = change_address ( m , GET_MODE ( m ) , base ) ; return m ; } </s>

If M is MEM ( REG ) or MEM ( PLUS ( REG , INT ) ) and REG is virtual then copy it into NEWBASE and return the updated MEM . Otherwise just return M. Any needed insns are emitted before BEFORE .


<s> bool M68kOperand :: isToken ( ) const { return Kind == KindTy :: Token ; } </s>


runOnMachineFunction - Emit the function body .


<s> SDValue MipsTargetLowering :: LowerOperation ( SDValue Op , SelectionDAG & DAG ) { switch ( Op . getOpcode ( ) ) { case ISD :: AND : return LowerANDOR ( Op , DAG ) ; case ISD :: BRCOND : return LowerBRCOND ( Op , DAG ) ; case ISD :: CALL : return LowerCALL ( Op , DAG ) ; case ISD :: ConstantPool : return LowerConstantPool ( Op , DAG ) ; case ISD :: DYNAMIC_STACKALLOC : return LowerDYNAMIC_STACKALLOC ( Op , DAG ) ; case ISD :: FORMAL_ARGUMENTS : return LowerFORMAL_ARGUMENTS ( Op , DAG ) ; case ISD :: FP_TO_SINT : return LowerFP_TO_SINT ( Op , DAG ) ; case ISD :: GlobalAddress : return LowerGlobalAddress ( Op , DAG ) ; case ISD :: GlobalTLSAddress : return LowerGlobalTLSAddress ( Op , DAG ) ; case ISD :: JumpTable : return LowerJumpTable ( Op , DAG ) ; case ISD :: OR : return LowerANDOR ( Op , DAG ) ; case ISD :: RET : return LowerRET ( Op , DAG ) ; case ISD :: SELECT : return LowerSELECT ( Op , DAG ) ; case ISD :: SETCC : return LowerSETCC ( Op , DAG ) ; } return SDValue ( ) ; } </s>

LowerOperation - Provide custom lowering hooks for some operations .

Mips Mips ISD::AND ISD::BRCOND ISD::CALL ISD::ConstantPool ISD::DYNAMIC_STACKALLOC ISD::FORMAL_ARGUMENTS ISD::FP_TO_SINT ISD::GlobalAddress ISD::GlobalTLSAddress ISD::JumpTable ISD::OR ISD::RET ISD::SELECT ISD::SETCC


<s> bool msp430_use_f5_series_hwmult ( void ) { static const char * cached_match = NULL ; static bool cached_result ; if ( msp430_hwmult_type == MSP430_HWMULT_F5SERIES ) return true ; if ( target_mcu == NULL || msp430_hwmult_type != MSP430_HWMULT_AUTO ) return false ; if ( target_mcu == cached_match ) return cached_result ; cached_match = target_mcu ; if ( strncasecmp ( target_mcu , "msp430f5" , 8 ) == 0 ) return cached_result = true ; if ( strncasecmp ( target_mcu , "msp430fr5" , 9 ) == 0 ) return cached_result = true ; if ( strncasecmp ( target_mcu , "msp430f6" , 8 ) == 0 ) return cached_result = true ; msp430_extract_mcu_data ( target_mcu ) ; if ( extracted_mcu_data . name != NULL ) return cached_result = extracted_mcu_data . hwmpy == 8 ; return cached_result = false ; } </s>

Returns true if the current MCU supports an F5xxx series hardware multiper .


<s> bool usesPhysRegsForValues ( ) const override { return false ; } </s>

True if the target uses physical regs ( as nearly all targets do ) .


<s> int check_pic ( int i ) { rtx op ; switch ( flag_pic ) { case 1 : op = recog_data . operand [ i ] ; gcc_assert ( GET_CODE ( op ) != SYMBOL_REF && ( GET_CODE ( op ) != CONST || ( GET_CODE ( XEXP ( op , 0 ) ) == MINUS && XEXP ( XEXP ( op , 0 ) , 0 ) == sparc_got ( ) && GET_CODE ( XEXP ( XEXP ( op , 0 ) , 1 ) ) == CONST ) ) ) ; case 2 : default : return 1 ; } } </s>

Ensure that we are not using patterns that are not OK with PIC .


<s> poly_int64 cr16_push_rounding ( poly_int64 bytes ) { return ( bytes + 1 ) & ~ 1 ; } </s>


<s> bool X86ExpandPseudo :: runOnMachineFunction ( MachineFunction & MF ) { STI = & static_cast < const X86Subtarget & > ( MF . getSubtarget ( ) ) ; TII = STI -> getInstrInfo ( ) ; TRI = STI -> getRegisterInfo ( ) ; X86FL = STI -> getFrameLowering ( ) ; bool Modified = false ; for ( MachineBasicBlock & MBB : MF ) Modified |= ExpandMBB ( MBB ) ; return Modified ; } </s>


<s>
FunctionType
*
AMDGPUIntrinsicInfo
::
getType
(
LLVMContext
&
Context
,
unsigned
ID
,
ArrayRef
<
Type
*
>
Tys
)
const
{
switch
(
ID
)
{
case
AMDGPUIntrinsic
::
amdgcn_fdiv_fast
:
{
Type
*
F32Ty
=
Type
::
getFloatTy
(
Context
)
;
return
FunctionType
::
get
(
F32Ty
,
{
F32Ty
,
F32Ty
}
,
false
)
;
}
default
:
llvm_unreachable
(
"unhandled intrinsic"
)
;
}
}
</s>

Overload to return most specific vector type .

AMDGPU
AMDGPU
AMDGPUIntrinsic::amdgcn_fdiv_fast
"unhandled intrinsic"


"Didn't find MI in its own basic block?"

getOffsetOf - Return the current offset of the specified machine instruction from the start of the function .


<s> void RISCVAsmPrinter :: emitBasicBlockEnd ( const MachineBasicBlock & MBB ) { auto * RVFI = MF -> getInfo < RISCVMachineFunctionInfo > ( ) ; RISCVTargetStreamer & RTS = static_cast < RISCVTargetStreamer & > ( * OutStreamer -> getTargetStreamer ( ) ) ; if ( RVFI -> isHwlpBasicBlock ( & MBB ) ) { RTS . emitDirectiveOptionPop ( ) ; } AsmPrinter :: emitBasicBlockEnd ( MBB ) ; } </s>

Targets can override this to emit stuff at the end of a basic block .


<s> bool SIInstrInfo :: isLegalFLATOffset ( int64_t Offset , unsigned AddrSpace , bool Signed ) const { if ( ! ST . hasFlatInstOffsets ( ) ) return false ; if ( ST . hasFlatSegmentOffsetBug ( ) && AddrSpace == AMDGPUAS :: FLAT_ADDRESS ) return false ; if ( ST . getGeneration ( ) >= AMDGPUSubtarget :: GFX10 ) { return ( Signed && isInt < 12 > ( Offset ) ) || ( ! Signed && isUInt < 11 > ( Offset ) ) ; } return ( Signed && isInt < 13 > ( Offset ) ) || ( ! Signed && isUInt < 12 > ( Offset ) ) ; } </s>

Returns if Offset is legal for the subtarget as the offset to a FLAT encoded instruction .


<s>
void
WebAssemblyInstrInfo
::
copyPhysReg
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
const
DebugLoc
&
DL
,
unsigned
DestReg
,
unsigned
SrcReg
,
bool
KillSrc
)
const
{
auto
&
MRI
=
MBB
.
getParent
(
)
->
getRegInfo
(
)
;
const
TargetRegisterClass
*
RC
=
TargetRegisterInfo
::
isVirtualRegister
(
DestReg
)
MRI
.
getRegClass
(
DestReg
)
:
MRI
.
getTargetRegisterInfo
(
)
->
getMinimalPhysRegClass
(
DestReg
)
;
unsigned
CopyOpcode
;
if
(
RC
==
&
WebAssembly
::
I32RegClass
)
CopyOpcode
=
WebAssembly
::
COPY_I32
;
else
if
(
RC
==
&
WebAssembly
::
I64RegClass
)
CopyOpcode
=
WebAssembly
::
COPY_I64
;
else
if
(
RC
==
&
WebAssembly
::
F32RegClass
)
CopyOpcode
=
WebAssembly
::
COPY_F32
;
else
if
(
RC
==
&
WebAssembly
::
F64RegClass
)
CopyOpcode
=
WebAssembly
::
COPY_F64
;
else
llvm_unreachable
(
"Unexpected register class"
)
;
BuildMI
(
MBB
,
I
,
DL
,
get
(
CopyOpcode
)
,
DestReg
)
.
addReg
(
SrcReg
,
KillSrc
RegState
::
Kill
:
0
)
;
}
</s>


<s> static void bfin_function_arg_advance ( cumulative_args_t cum_v , const function_arg_info & arg ) { CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; int count , bytes , words ; bytes = arg . promoted_size_in_bytes ( ) ; words = ( bytes + UNITS_PER_WORD - 1 ) / UNITS_PER_WORD ; cum -> words += words ; cum -> nregs -= words ; if ( cum -> nregs <= 0 ) { cum -> nregs = 0 ; cum -> arg_regs = NULL ; } else { for ( count = 1 ; count <= words ; count ++ ) cum -> arg_regs ++ ; } return ; } </s>

Update the data in CUM to advance over an argument of mode MODE and data type TYPE . ( TYPE is null for libcalls where that information may not be available . )


<s> SDValue BPFSelectionDAGInfo :: EmitTargetCodeForMemcpy ( SelectionDAG & DAG , const SDLoc & dl , SDValue Chain , SDValue Dst , SDValue Src , SDValue Size , Align Alignment , bool isVolatile , bool AlwaysInline , MachinePointerInfo DstPtrInfo , MachinePointerInfo SrcPtrInfo ) const { ConstantSDNode * ConstantSize = dyn_cast < ConstantSDNode > ( Size ) ; if ( ! ConstantSize ) return SDValue ( ) ; unsigned CopyLen = ConstantSize -> getZExtValue ( ) ; unsigned StoresNumEstimate = alignTo ( CopyLen , Alignment ) >> Log2 ( Alignment ) ; if ( StoresNumEstimate > getCommonMaxStoresPerMemFunc ( ) ) return SDValue ( ) ; SDVTList VTs = DAG . getVTList ( MVT :: Other , MVT :: Glue ) ; Dst = DAG . getNode ( BPFISD :: MEMCPY , dl , VTs , Chain , Dst , Src , DAG . getConstant ( CopyLen , dl , MVT :: i64 ) , DAG . getConstant ( Alignment . value ( ) , dl , MVT :: i64 ) ) ; return Dst . getValue ( 0 ) ; } </s>

Emit target-specific code that performs a memcpy .


<s>
TTI
::
PopcntSupportKind
getPopcntSupport
(
unsigned
TyWidth
)
{
assert
(
isPowerOf2_32
(
TyWidth
)
&&
"Ty width must be power of 2"
)
;
return
ST
->
hasBCNT
(
TyWidth
)
TTI
::
PSK_FastHardware
:
TTI
::
PSK_Software
;
}
</s>

Return hardware support for population count .


<s> bool arm_validize_comparison ( rtx * comparison , rtx * op1 , rtx * op2 ) { enum rtx_code code = GET_CODE ( * comparison ) ; int code_int ; machine_mode mode = ( GET_MODE ( * op1 ) == VOIDmode ) ? GET_MODE ( * op2 ) : GET_MODE ( * op1 ) ; gcc_assert ( GET_MODE ( * op1 ) != VOIDmode || GET_MODE ( * op2 ) != VOIDmode ) ; if ( code == UNEQ || code == LTGT ) return false ; code_int = ( int ) code ; arm_canonicalize_comparison ( & code_int , op1 , op2 , 0 ) ; PUT_CODE ( * comparison , ( enum rtx_code ) code_int ) ; switch ( mode ) { case SImode : if ( ! arm_add_operand ( * op1 , mode ) ) * op1 = force_reg ( mode , * op1 ) ; if ( ! arm_add_operand ( * op2 , mode ) ) * op2 = force_reg ( mode , * op2 ) ; return true ; case DImode : if ( ! cmpdi_operand ( * op1 , mode ) ) * op1 = force_reg ( mode , * op1 ) ; if ( ! cmpdi_operand ( * op2 , mode ) ) * op2 = force_reg ( mode , * op2 ) ; return true ; case SFmode : case DFmode : if ( ! arm_float_compare_operand ( * op1 , mode ) ) * op1 = force_reg ( mode , * op1 ) ; if ( ! arm_float_compare_operand ( * op2 , mode ) ) * op2 = force_reg ( mode , * op2 ) ; return true ; default : break ; } return false ; } </s>

Returns true if a valid comparison operation and makes the operands in a form that is valid .


<s> bool AMDGPUCallLowering :: lowerFormalArguments ( MachineIRBuilder & MIRBuilder , const Function :: ArgumentListType & Args , ArrayRef < unsigned > VRegs ) const { return true ; } </s>

This hook must be implemented to lower the incoming ( formal ) arguments , described by VRegs , for GlobalISel .


<s> bool X86TargetLowering :: shouldFormOverflowOp ( unsigned Opcode , EVT VT ) const { if ( VT . isVector ( ) ) return false ; return VT . isSimple ( ) || ! isOperationExpand ( Opcode , VT ) ; } </s>

Overflow nodes should get combined/lowered to optimal instructions ( they should allow eliminating explicit compares by getting flags from math ops ) .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . addRequired < MachineDominatorTree > ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s>
bool
AArch64MCInstLower
::
lowerOperand
(
const
MachineOperand
&
MO
,
MCOperand
&
MCOp
)
const
{
switch
(
MO
.
getType
(
)
)
{
default
:
llvm_unreachable
(
"unknown operand type"
)
;
case
MachineOperand
::
MO_Register
:
if
(
MO
.
isImplicit
(
)
)
return
false
;
MCOp
=
MCOperand
::
createReg
(
MO
.
getReg
(
)
)
;
break
;
case
MachineOperand
::
MO_RegisterMask
:
return
false
;
case
MachineOperand
::
MO_Immediate
:
MCOp
=
MCOperand
::
createImm
(
MO
.
getImm
(
)
)
;
break
;
case
MachineOperand
::
MO_MachineBasicBlock
:
MCOp
=
MCOperand
::
createExpr
(
MCSymbolRefExpr
::
create
(
MO
.
getMBB
(
)
->
getSymbol
(
)
,
Ctx
)
)
;
break
;
case
MachineOperand
::
MO_GlobalAddress
:
MCOp
=
LowerSymbolOperand
(
MO
,
GetGlobalAddressSymbol
(
MO
)
)
;
break
;
case
MachineOperand
::
MO_ExternalSymbol
:
MCOp
=
LowerSymbolOperand
(
MO
,
GetExternalSymbolSymbol
(
MO
)
)
;
break
;
case
MachineOperand
::
MO_JumpTableIndex
:
MCOp
=
LowerSymbolOperand
(
MO
,
Printer
.
GetJTISymbol
(
MO
.
getIndex
(
)
)
)
;
break
;
case
MachineOperand
::
MO_ConstantPoolIndex
:
MCOp
=
LowerSymbolOperand
(
MO
,
Printer
.
GetCPISymbol
(
MO
.
getIndex
(
)
)
)
;
break
;
case
MachineOperand
::
MO_BlockAddress
:
MCOp
=
LowerSymbolOperand
(
MO
,
Printer
.
GetBlockAddressSymbol
(
MO
.
getBlockAddress
(
)
)
)
;
break
;
}
return
true
;
}
</s>

Wrapper for MCInstLowering.lowerOperand ( ) for the tblgen'erated pseudo lowering .