<s> bool GCNDPPCombine :: runOnMachineFunction ( MachineFunction & MF ) { auto & ST = MF . getSubtarget < GCNSubtarget > ( ) ; if ( ! ST . hasDPP ( ) || skipFunction ( MF . getFunction ( ) ) ) return false ; MRI = & MF . getRegInfo ( ) ; TII = ST . getInstrInfo ( ) ; bool Changed = false ; for ( auto & MBB : MF ) { for ( auto I = MBB . rbegin ( ) , E = MBB . rend ( ) ; I != E ; ) { auto & MI = * I ++ ; if ( MI . getOpcode ( ) == AMDGPU :: V_MOV_B32_dpp && combineDPPMov ( MI ) ) { Changed = true ; ++ NumDPPMovsCombined ; } else if ( MI . getOpcode ( ) == AMDGPU :: V_MOV_B64_DPP_PSEUDO ) { auto Split = TII -> expandMovDPP64 ( MI ) ; for ( auto M : { Split . first , Split . second } ) { if ( combineDPPMov ( * M ) ) ++ NumDPPMovsCombined ; } Changed = true ; } } } return Changed ; } </s>

runOnMachineFunction - Emit the function body .


<s> static bool microblaze_elf_in_small_data_p ( const_tree decl ) { HOST_WIDE_INT size ; if ( ! TARGET_XLGPOPT ) return false ; if ( TREE_CODE ( decl ) == STRING_CST ) return false ; if ( TREE_CODE ( decl ) == FUNCTION_DECL ) return false ; if ( TREE_CODE ( decl ) == VAR_DECL && DECL_SECTION_NAME ( decl ) ) { const char * section = DECL_SECTION_NAME ( decl ) ; if ( strcmp ( section , ".sdata" ) == 0 || strcmp ( section , ".sdata2" ) == 0 || strcmp ( section , ".sbss" ) == 0 || strcmp ( section , ".sbss2" ) == 0 ) return true ; } size = int_size_in_bytes ( TREE_TYPE ( decl ) ) ; return ( size > 0 && size <= microblaze_section_threshold ) ; } </s>

Returns true if decl should be placed into a `` small data '' section .


"Can't store this register to stack slot"

Store the specified register of the given register class to the specified stack frame index .


<s>
MachineInstr
*
ARMBaseInstrInfo
::
optimizeSelect
(
MachineInstr
&
MI
,
SmallPtrSetImpl
<
MachineInstr
*
>
&
SeenMIs
,
bool
PreferFalse
)
const
{
assert
(
(
MI
.
getOpcode
(
)
==
ARM
::
MOVCCr
||
MI
.
getOpcode
(
)
==
ARM
::
t2MOVCCr
)
&&
"Unknown select instruction"
)
;
MachineRegisterInfo
&
MRI
=
MI
.
getParent
(
)
->
getParent
(
)
->
getRegInfo
(
)
;
MachineInstr
*
DefMI
=
canFoldIntoMOVCC
(
MI
.
getOperand
(
2
)
.
getReg
(
)
,
MRI
,
this
)
;
bool
Invert
=
!
DefMI
;
if
(
!
DefMI
)
DefMI
=
canFoldIntoMOVCC
(
MI
.
getOperand
(
1
)
.
getReg
(
)
,
MRI
,
this
)
;
if
(
!
DefMI
)
return
nullptr
;
MachineOperand
FalseReg
=
MI
.
getOperand
(
Invert
2
:
1
)
;
Register
DestReg
=
MI
.
getOperand
(
0
)
.
getReg
(
)
;
const
TargetRegisterClass
*
PreviousClass
=
MRI
.
getRegClass
(
FalseReg
.
getReg
(
)
)
;
if
(
!
MRI
.
constrainRegClass
(
DestReg
,
PreviousClass
)
)
return
nullptr
;
MachineInstrBuilder
NewMI
=
BuildMI
(
*
MI
.
getParent
(
)
,
MI
,
MI
.
getDebugLoc
(
)
,
DefMI
->
getDesc
(
)
,
DestReg
)
;
const
MCInstrDesc
&
DefDesc
=
DefMI
->
getDesc
(
)
;
for
(
unsigned
i
=
1
,
e
=
DefDesc
.
getNumOperands
(
)
;
i
!=
e
&&
!
DefDesc
.
OpInfo
[
i
]
.
isPredicate
(
)
;
++
i
)
NewMI
.
add
(
DefMI
->
getOperand
(
i
)
)
;
unsigned
CondCode
=
MI
.
getOperand
(
3
)
.
getImm
(
)
;
if
(
Invert
)
NewMI
.
addImm
(
ARMCC
::
getOppositeCondition
(
ARMCC
::
CondCodes
(
CondCode
)
)
)
;
else
NewMI
.
addImm
(
CondCode
)
;
NewMI
.
add
(
MI
.
getOperand
(
4
)
)
;
if
(
NewMI
->
hasOptionalDef
(
)
)
NewMI
.
add
(
condCodeOp
(
)
)
;
FalseReg
.
setImplicit
(
)
;
NewMI
.
add
(
FalseReg
)
;
NewMI
->
tieOperands
(
0
,
NewMI
->
getNumOperands
(
)
1
)
;
SeenMIs
.
insert
(
NewMI
)
;
SeenMIs
.
erase
(
DefMI
)
;
if
(
DefMI
->
getParent
(
)
!=
MI
.
getParent
(
)
)
NewMI
->
clearKillInfo
(
)
;
DefMI
->
eraseFromParent
(
)
;
return
NewMI
;
}
</s>

Given a select instruction that was understood by analyzeSelect and returned Optimizable = true , attempt to optimize MI by merging it with one of its operands .


<s> static tree aarch64_simd_builtin_type ( machine_mode mode , enum aarch64_type_qualifiers qualifiers ) { tree type = NULL_TREE ; if ( ( qualifiers & qualifier_pointer ) && VECTOR_MODE_P ( mode ) ) mode = GET_MODE_INNER ( mode ) ; if ( ( qualifiers & qualifier_poly ) || VECTOR_MODE_P ( mode ) ) type = aarch64_lookup_simd_type_in_table ( mode , qualifiers ) ; else type = aarch64_int_or_fp_type ( mode , qualifiers ) ; gcc_assert ( type != NULL_TREE ) ; if ( qualifiers & qualifier_const ) type = build_qualified_type ( type , TYPE_QUAL_CONST ) ; if ( qualifiers & qualifier_pointer ) type = build_pointer_type ( type ) ; return type ; } </s>

Return a type for an operand with specified mode and qualifiers .


<s> void relaxInstruction ( const MCInst & Inst , const MCSubtargetInfo & STI , MCInst & Res ) const override { } </s>

Relax the instruction in the given fragment to the next wider instruction .


<s> MachineInstrBuilder R600InstrInfo :: buildIndirectRead ( MachineBasicBlock * MBB , MachineBasicBlock :: iterator I , unsigned ValueReg , unsigned Address , unsigned OffsetReg ) const { unsigned AddrReg = AMDGPU :: R600_AddrRegClass . getRegister ( Address ) ; MachineInstr * MOVA = buildDefaultInstruction ( * MBB , I , AMDGPU :: MOVA_INT_eg , AMDGPU :: AR_X , OffsetReg ) ; setImmOperand ( MOVA , AMDGPU :: OpName :: write , 0 ) ; MachineInstrBuilder Mov = buildDefaultInstruction ( * MBB , I , AMDGPU :: MOV , ValueReg , AddrReg ) . addReg ( AMDGPU :: AR_X , RegState :: Implicit | RegState :: Kill ) ; setImmOperand ( Mov , AMDGPU :: OpName :: src0_rel , 1 ) ; return Mov ; } </s>

Build instruction ( s ) for an indirect register read .


<s> bool SIMemoryLegalizer :: runOnMachineFunction ( MachineFunction & MF ) { bool Changed = false ; SIMemOpAccess MOA ( MF ) ; CC = SICacheControl :: create ( MF . getSubtarget < GCNSubtarget > ( ) ) ; for ( auto & MBB : MF ) { for ( auto MI = MBB . begin ( ) ; MI != MBB . end ( ) ; ++ MI ) { if ( MI -> isBundle ( ) ) { MachineBasicBlock :: instr_iterator II ( MI -> getIterator ( ) ) ; for ( MachineBasicBlock :: instr_iterator I = ++ II , E = MBB . instr_end ( ) ; I != E && I -> isBundledWithPred ( ) ; ++ I ) { I -> unbundleFromPred ( ) ; for ( MachineOperand & MO : I -> operands ( ) ) if ( MO . isReg ( ) ) MO . setIsInternalRead ( false ) ; } MI -> eraseFromParent ( ) ; MI = II -> getIterator ( ) ; } if ( ! ( MI -> getDesc ( ) . TSFlags & SIInstrFlags :: maybeAtomic ) ) continue ; if ( const auto & MOI = MOA . getLoadInfo ( MI ) ) Changed |= expandLoad ( MOI . getValue ( ) , MI ) ; else if ( const auto & MOI = MOA . getStoreInfo ( MI ) ) Changed |= expandStore ( MOI . getValue ( ) , MI ) ; else if ( const auto & MOI = MOA . getAtomicFenceInfo ( MI ) ) Changed |= expandAtomicFence ( MOI . getValue ( ) , MI ) ; else if ( const auto & MOI = MOA . getAtomicCmpxchgOrRmwInfo ( MI ) ) Changed |= expandAtomicCmpxchgOrRmw ( MOI . getValue ( ) , MI ) ; } } Changed |= removeAtomicPseudoMIs ( ) ; return Changed ; } </s>

AMDGPU SI SI SI SIInstrFlags::maybeAtomic


<s> static void sh_setup_incoming_varargs ( CUMULATIVE_ARGS * ca , enum machine_mode mode , tree type , int * pretend_arg_size , int second_time ATTRIBUTE_UNUSED ) { gcc_assert ( current_function_stdarg ) ; if ( TARGET_VARARGS_PRETEND_ARGS ( current_function_decl ) ) { int named_parm_regs , anon_parm_regs ; named_parm_regs = ( ROUND_REG ( * ca , mode ) + ( mode == BLKmode ? ROUND_ADVANCE ( int_size_in_bytes ( type ) ) : ROUND_ADVANCE ( GET_MODE_SIZE ( mode ) ) ) ) ; anon_parm_regs = NPARM_REGS ( SImode ) - named_parm_regs ; if ( anon_parm_regs > 0 ) * pretend_arg_size = anon_parm_regs * 4 ; } } </s>

We actually emit the code in sh_expand_prologue . We used to use a static variable to flag that we need to emit this code , but that does n't when inlining , when functions are deferred and then emitted later . Fortunately , we already have two flags that are part of struct function that tell if a function uses varargs or stdarg .


<s> void Z80InstPrinter :: printRegName ( raw_ostream & OS , unsigned RegNo ) const { OS << StringRef ( getRegisterName ( RegNo ) ) . lower ( ) ; } </s>


<s>
bool
MSP430AsmPrinter
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
SetupMachineFunction
(
MF
)
;
O
<<
"\n\n"
;
emitFunctionHeader
(
MF
)
;
for
(
MachineFunction
::
const_iterator
I
=
MF
.
begin
(
)
,
E
=
MF
.
end
(
)
;
I
!=
E
;
++
I
)
{
if
(
!
VerboseAsm
&&
(
I
->
pred_empty
(
)
||
I
->
isOnlyReachableByFallthrough
(
)
)
)
{
}
else
{
printBasicBlockLabel
(
I
,
true
,
true
,
VerboseAsm
)
;
O
<<
'\n'
;
}
for
(
MachineBasicBlock
::
const_iterator
II
=
I
->
begin
(
)
,
E
=
I
->
end
(
)
;
II
!=
E
;
++
II
)
printMachineInstruction
(
II
)
;
}
if
(
TAI
->
hasDotTypeDotSizeDirective
(
)
)
O
<<
"\t.size\t"
<<
CurrentFnName
<<
", .-"
<<
CurrentFnName
<<
'\n'
;
return
false
;
}
</s>


<s> static bool cris_pass_by_reference ( cumulative_args_t ca ATTRIBUTE_UNUSED , machine_mode mode , const_tree type , bool named ATTRIBUTE_UNUSED ) { return ( targetm . calls . must_pass_in_stack ( mode , type ) || CRIS_FUNCTION_ARG_SIZE ( mode , type ) > 8 ) ; } </s>

Return true if TYPE must be passed by invisible reference . For cris , we pass < = 8 bytes by value , others by reference .


<s> static bool isAssociativeAndCommutative ( const MachineInstr & Inst ) { switch ( Inst . getOpcode ( ) ) { case X86 :: AND8rr : case X86 :: AND16rr : case X86 :: AND32rr : case X86 :: AND64rr : case X86 :: OR8rr : case X86 :: OR16rr : case X86 :: OR32rr : case X86 :: OR64rr : case X86 :: XOR8rr : case X86 :: XOR16rr : case X86 :: XOR32rr : case X86 :: XOR64rr : case X86 :: IMUL16rr : case X86 :: IMUL32rr : case X86 :: IMUL64rr : case X86 :: MAXCPDrr : case X86 :: MAXCPSrr : case X86 :: MAXCSDrr : case X86 :: MAXCSSrr : case X86 :: MINCPDrr : case X86 :: MINCPSrr : case X86 :: MINCSDrr : case X86 :: MINCSSrr : case X86 :: VMAXCPDrr : case X86 :: VMAXCPSrr : case X86 :: VMAXCPDYrr : case X86 :: VMAXCPSYrr : case X86 :: VMAXCSDrr : case X86 :: VMAXCSSrr : case X86 :: VMINCPDrr : case X86 :: VMINCPSrr : case X86 :: VMINCPDYrr : case X86 :: VMINCPSYrr : case X86 :: VMINCSDrr : case X86 :: VMINCSSrr : return true ; case X86 :: ADDPDrr : case X86 :: ADDPSrr : case X86 :: ADDSDrr : case X86 :: ADDSSrr : case X86 :: MULPDrr : case X86 :: MULPSrr : case X86 :: MULSDrr : case X86 :: MULSSrr : case X86 :: VADDPDrr : case X86 :: VADDPSrr : case X86 :: VADDPDYrr : case X86 :: VADDPSYrr : case X86 :: VADDSDrr : case X86 :: VADDSSrr : case X86 :: VMULPDrr : case X86 :: VMULPSrr : case X86 :: VMULPDYrr : case X86 :: VMULPSYrr : case X86 :: VMULSDrr : case X86 :: VMULSSrr : return Inst . getParent ( ) -> getParent ( ) -> getTarget ( ) . Options . UnsafeFPMath ; default : return false ; } } </s>

Return true when \P Inst is both associative and commutative .


<s> static void do_sub3 ( rtx dest , rtx src1 , rtx src2 ) { if ( GET_MODE ( dest ) == DImode ) emit_insn ( gen_subdi3 ( dest , src1 , src2 ) ) ; else emit_insn ( gen_subsi3 ( dest , src1 , src2 ) ) ; } </s>

Emit a subtract of the proper mode for DEST . DEST is the destination register for the subtract . SRC1 is the first subtract input . SRC2 is the second subtract input . Computes DEST = SRC1-SRC2 .


<s> bool MipsAsmPrinter :: runOnMachineFunction ( MachineFunction & MF ) { if ( Subtarget -> allowMixed16_32 ( ) ) const_cast < TargetLoweringObjectFile & > ( getObjFileLowering ( ) ) . Initialize ( OutContext , TM ) ; MipsFI = MF . getInfo < MipsFunctionInfo > ( ) ; AsmPrinter :: runOnMachineFunction ( MF ) ; return true ; } </s>


<s> static int vax_address_cost ( rtx x ) { return ( 1 + ( GET_CODE ( x ) == REG ? 0 : vax_address_cost_1 ( x ) ) ) ; } </s>

Return the cost in cycles of a memory address , relative to register indirect . Each of the following adds the indicated number of cycles : 1 - symbolic address 1 - pre-decrement 1 - indexing and/or offset ( register ) 2 - indirect


<s>
void
frv_init_cumulative_args
(
CUMULATIVE_ARGS
*
cum
,
tree
fntype
,
rtx
libname
,
tree
fndecl
,
int
incoming
)
{
*
cum
=
FIRST_ARG_REGNUM
;
if
(
TARGET_DEBUG_ARG
)
{
fprintf
(
stderr
,
"\ninit_cumulative_args:"
)
;
if
(
!
fndecl
&&
fntype
)
fputs
(
" indirect"
,
stderr
)
;
if
(
incoming
)
fputs
(
" incoming"
,
stderr
)
;
if
(
fntype
)
{
tree
ret_type
=
TREE_TYPE
(
fntype
)
;
fprintf
(
stderr
,
" return=%s,"
,
get_tree_code_name
(
TREE_CODE
(
ret_type
)
)
)
;
}
if
(
libname
&&
GET_CODE
(
libname
)
==
SYMBOL_REF
)
fprintf
(
stderr
,
" libname=%s"
,
XSTR
(
libname
,
0
)
)
;
if
(
cfun
->
returns_struct
)
fprintf
(
stderr
,
" return-struct"
)
;
putc
(
'\n'
,
stderr
)
;
}
}
</s>

A C statement ( sans semicolon ) for initializing the variable CUM for the state at the beginning of the argument list . The variable has type ` CUMULATIVE_ARGS ' . The value of FNTYPE is the tree node for the data type of the function which will receive the args , or 0 if the args are to a compiler support library function . The value of INDIRECT is nonzero when processing an indirect call , for example a call through a function pointer . The value of INDIRECT is zero for a call to an explicitly named function , a library function call , or when ` INIT_CUMULATIVE_ARGS ' is used to find arguments for the function being compiled . When processing a call to a compiler support library function , LIBNAME identifies which one . It is a ` symbol_ref ' rtx which contains the name of the function , as a string . LIBNAME is 0 when an ordinary C function call is being processed . Thus , each time this macro is called , either LIBNAME or FNTYPE is nonzero , but never both of them at once .

frv
"\ninit_cumulative_args:"
" indirect"
" incoming"
" return=%s,"
" libname=%s"
0
" return-struct"


<s> static bool riscv_pass_aggregate_in_fpr_and_gpr_p ( const_tree type , riscv_aggregate_field fields [ 2 ] ) { unsigned num_int = 0 , num_float = 0 ; int n = riscv_flatten_aggregate_argument ( type , fields ) ; for ( int i = 0 ; i < n ; i ++ ) { num_float += SCALAR_FLOAT_TYPE_P ( fields [ i ] . type ) ; num_int += INTEGRAL_TYPE_P ( fields [ i ] . type ) ; } return num_int == 1 && num_float == 1 ; } </s>

See whether TYPE is a record whose fields should be returned in one or floating-point register and one integer register . If so , populate FIELDS accordingly .


<s>
void
dump
(
)
{
errs
(
)
<<
"mprocISelAddressMode "
<<
this
<<
'\n'
;
if
(
BaseType
==
RegBase
&&
Base
.
Reg
.
getNode
(
)
!=
0
)
{
errs
(
)
<<
"Base.Reg "
;
Base
.
Reg
.
getNode
(
)
->
dump
(
)
;
}
else
if
(
BaseType
==
FrameIndexBase
)
{
errs
(
)
<<
" Base.FrameIndex "
<<
Base
.
FrameIndex
<<
'\n'
;
}
errs
(
)
<<
" Disp "
<<
Disp
<<
'\n'
;
if
(
GV
)
{
errs
(
)
<<
"GV "
;
GV
->
dump
(
)
;
}
else
if
(
CP
)
{
errs
(
)
<<
" CP "
;
CP
->
dump
(
)
;
errs
(
)
<<
" Align"
<<
Align
<<
'\n'
;
}
else
if
(
ES
)
{
errs
(
)
<<
"ES "
;
errs
(
)
<<
ES
<<
'\n'
;
}
else
if
(
JT
!=
1
)
errs
(
)
<<
" JT"
<<
JT
<<
" Align"
<<
Align
<<
'\n'
;
}
</s>

Dump the plan to stderr ( for debugging ) .

mproc
"mprocISelAddressMode "
0
"Base.Reg "
" Base.FrameIndex "
" Disp "
"GV "
" CP "
" Align"
"ES "
1
" JT"
" Align"


<s> const GCNSubtarget * SITargetLowering :: getSubtarget ( ) const { return Subtarget ; } </s>

getSubtarget - Return the subtarget for which this machine code is being compiled .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . addRequired < AAResultsWrapperPass > ( ) ; AU . addRequired < MachineDominatorTree > ( ) ; AU . addPreserved < MachineDominatorTree > ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> bool isMem ( ) const override { return false ; } </s>


<s> bool X86TargetLowering :: getTgtMemIntrinsic ( IntrinsicInfo & Info , const CallInst & I , unsigned Intrinsic ) const { const IntrinsicData * IntrData = getIntrinsicWithChain ( Intrinsic ) ; if ( ! IntrData ) return false ; Info . opc = ISD :: INTRINSIC_W_CHAIN ; Info . readMem = false ; Info . writeMem = false ; Info . vol = false ; Info . offset = 0 ; switch ( IntrData -> Type ) { case LOADA : case LOADU : { Info . ptrVal = I . getArgOperand ( 0 ) ; Info . memVT = MVT :: getVT ( I . getType ( ) ) ; Info . align = ( IntrData -> Type == LOADA ? Info . memVT . getSizeInBits ( ) / 8 : 1 ) ; Info . readMem = true ; break ; } case EXPAND_FROM_MEM : { Info . ptrVal = I . getArgOperand ( 0 ) ; Info . memVT = MVT :: getVT ( I . getType ( ) ) ; Info . align = 1 ; Info . readMem = true ; break ; } case COMPRESS_TO_MEM : { Info . ptrVal = I . getArgOperand ( 0 ) ; Info . memVT = MVT :: getVT ( I . getArgOperand ( 1 ) -> getType ( ) ) ; Info . align = 1 ; Info . writeMem = true ; break ; } case TRUNCATE_TO_MEM_VI8 : case TRUNCATE_TO_MEM_VI16 : case TRUNCATE_TO_MEM_VI32 : { Info . ptrVal = I . getArgOperand ( 0 ) ; MVT VT = MVT :: getVT ( I . getArgOperand ( 1 ) -> getType ( ) ) ; MVT ScalarVT = MVT :: INVALID_SIMPLE_VALUE_TYPE ; if ( IntrData -> Type == TRUNCATE_TO_MEM_VI8 ) ScalarVT = MVT :: i8 ; else if ( IntrData -> Type == TRUNCATE_TO_MEM_VI16 ) ScalarVT = MVT :: i16 ; else if ( IntrData -> Type == TRUNCATE_TO_MEM_VI32 ) ScalarVT = MVT :: i32 ; Info . memVT = MVT :: getVectorVT ( ScalarVT , VT . getVectorNumElements ( ) ) ; Info . align = 1 ; Info . writeMem = true ; break ; } case STOREA : case STOREANT : case STOREU : { Info . ptrVal = I . getArgOperand ( 0 ) ; Info . memVT = MVT :: getVT ( I . getArgOperand ( 1 ) -> getType ( ) ) ; Info . align = ( IntrData -> Type == STOREU ? 1 : Info . memVT . getSizeInBits ( ) / 8 ) ; Info . writeMem = true ; break ; } default : return false ; } return true ; } </s>

Given an intrinsic , checks if on the target the intrinsic will need to map to a MemIntrinsicNode ( touches memory ) .


"Altivec is not implemented on AIX yet."

Return a mask of call-preserved registers for the given calling convention on the current function .


"FrameIndex should have been previously eliminated!"

"Instr does not have a FrameIndex operand!"

This method must be overriden to eliminate abstract frame indices from instructions which may use them .


<s> static scalar_int_mode rs6000_eh_return_filter_mode ( void ) { return TARGET_32BIT ? SImode : word_mode ; } </s>


<s>
MachineBasicBlock
::
iterator
AArch64FrameLowering
::
eliminateCallFramePseudoInstr
(
MachineFunction
&
MF
,
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
)
const
{
const
AArch64InstrInfo
*
TII
=
static_cast
<
const
AArch64InstrInfo
*
>
(
MF
.
getSubtarget
(
)
.
getInstrInfo
(
)
)
;
DebugLoc
DL
=
I
->
getDebugLoc
(
)
;
unsigned
Opc
=
I
->
getOpcode
(
)
;
bool
IsDestroy
=
Opc
==
TII
->
getCallFrameDestroyOpcode
(
)
;
uint64_t
CalleePopAmount
=
IsDestroy
I
->
getOperand
(
1
)
.
getImm
(
)
:
0
;
if
(
!
hasReservedCallFrame
(
MF
)
)
{
unsigned
Align
=
getStackAlignment
(
)
;
int64_t
Amount
=
I
->
getOperand
(
0
)
.
getImm
(
)
;
Amount
=
alignTo
(
Amount
,
Align
)
;
if
(
!
IsDestroy
)
Amount
=
Amount
;
if
(
CalleePopAmount
==
0
)
{
assert
(
Amount
>
0xffffff
&&
Amount
<
0xffffff
&&
"call frame too large"
)
;
emitFrameOffset
(
MBB
,
I
,
DL
,
AArch64
::
SP
,
AArch64
::
SP
,
Amount
,
TII
)
;
}
}
else
if
(
CalleePopAmount
!=
0
)
{
assert
(
CalleePopAmount
<
0xffffff
&&
"call frame too large"
)
;
emitFrameOffset
(
MBB
,
I
,
DL
,
AArch64
::
SP
,
AArch64
::
SP
,
CalleePopAmount
,
TII
)
;
}
return
MBB
.
erase
(
I
)
;
}
</s>

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .


<s>
unsigned
ARMTargetLowering
::
getRegisterByName
(
const
char
*
RegName
,
EVT
VT
)
const
{
unsigned
Reg
=
StringSwitch
<
unsigned
>
(
RegName
)
.
Case
(
"sp"
,
ARM
::
SP
)
.
Default
(
0
)
;
if
(
Reg
)
return
Reg
;
report_fatal_error
(
"Invalid register name global variable"
)
;
}
</s>

Return the register ID of the name passed in .

ARM
ARM
"sp"
ARM::SP
0
"Invalid register name global variable"


<s> bool X86PassConfig :: addLegalizeMachineIR ( ) { addPass ( new Legalizer ( ) ) ; return false ; } </s>

This method should install a legalize pass , which converts the instruction sequence into one that can be selected by the target .


<s> int ARMTTIImpl :: getIntImmCostInst ( unsigned Opcode , unsigned Idx , const APInt & Imm , Type * Ty , TTI :: TargetCostKind CostKind , Instruction * Inst ) { if ( ( Opcode == Instruction :: SDiv || Opcode == Instruction :: UDiv || Opcode == Instruction :: SRem || Opcode == Instruction :: URem ) && Idx == 1 ) return 0 ; if ( Opcode == Instruction :: And ) { if ( Imm == 255 || Imm == 65535 ) return 0 ; return std :: min ( getIntImmCost ( Imm , Ty , CostKind ) , getIntImmCost ( ~ Imm , Ty , CostKind ) ) ; } if ( Opcode == Instruction :: Add ) return std :: min ( getIntImmCost ( Imm , Ty , CostKind ) , getIntImmCost ( - Imm , Ty , CostKind ) ) ; if ( Opcode == Instruction :: ICmp && Imm . isNegative ( ) && Ty -> getIntegerBitWidth ( ) == 32 ) { int64_t NegImm = - Imm . getSExtValue ( ) ; if ( ST -> isThumb2 ( ) && NegImm < 1 << 12 ) return 0 ; if ( ST -> isThumb ( ) && NegImm < 1 << 8 ) return 0 ; } if ( Opcode == Instruction :: Xor && Imm . isAllOnesValue ( ) ) return 0 ; if ( Inst && ( ( ST -> hasV6Ops ( ) && ! ST -> isThumb ( ) ) || ST -> isThumb2 ( ) ) && Ty -> getIntegerBitWidth ( ) <= 32 ) { if ( isSSATMinMaxPattern ( Inst , Imm ) || ( isa < ICmpInst > ( Inst ) && Inst -> hasOneUse ( ) && isSSATMinMaxPattern ( cast < Instruction > ( * Inst -> user_begin ( ) ) , Imm ) ) ) return 0 ; } return getIntImmCost ( Imm , Ty , CostKind ) ; } </s>

Return the expected cost of materialization for the given integer immediate of the specified type for a given instruction .


<s> static bool sh_cannot_modify_jumps_p ( void ) { return ( TARGET_SHMEDIA && ( reload_in_progress || reload_completed ) ) ; } </s>

SHmedia requires registers for branches , so we ca n't generate new branches past reload .


<s>
bool
SystemZAsmParser
::
ParseInstruction
(
ParseInstructionInfo
&
Info
,
StringRef
Name
,
SMLoc
NameLoc
,
OperandVector
&
Operands
)
{
Operands
.
push_back
(
SystemZOperand
::
createToken
(
Name
,
NameLoc
)
)
;
if
(
getLexer
(
)
.
isNot
(
AsmToken
::
EndOfStatement
)
)
{
if
(
parseOperand
(
Operands
,
Name
)
)
{
return
true
;
}
while
(
getLexer
(
)
.
is
(
AsmToken
::
Comma
)
)
{
Parser
.
Lex
(
)
;
if
(
parseOperand
(
Operands
,
Name
)
)
{
return
true
;
}
}
if
(
getLexer
(
)
.
isNot
(
AsmToken
::
EndOfStatement
)
)
{
SMLoc
Loc
=
getLexer
(
)
.
getLoc
(
)
;
return
Error
(
Loc
,
"unexpected token in argument list"
)
;
}
}
Parser
.
Lex
(
)
;
return
false
;
}
</s>

ParseInstruction - Parse one assembly instruction .

SystemZ
SystemZ
SystemZ
"unexpected token in argument list"


<s>
void
CSKYAsmBackend
::
applyFixup
(
const
MCAssembler
&
Asm
,
const
MCFixup
&
Fixup
,
const
MCValue
&
Target
,
MutableArrayRef
<
char
>
Data
,
uint64_t
Value
,
bool
IsResolved
,
const
MCSubtargetInfo
*
STI
)
const
{
MCFixupKind
Kind
=
Fixup
.
getKind
(
)
;
if
(
Kind
>=
FirstLiteralRelocationKind
)
return
;
MCContext
&
Ctx
=
Asm
.
getContext
(
)
;
MCFixupKindInfo
Info
=
getFixupKindInfo
(
Kind
)
;
if
(
!
Value
)
return
;
Value
=
adjustFixupValue
(
Fixup
,
Value
,
Ctx
)
;
Value
<<=
Info
.
TargetOffset
;
unsigned
Offset
=
Fixup
.
getOffset
(
)
;
unsigned
NumBytes
=
alignTo
(
Info
.
TargetSize
+
Info
.
TargetOffset
,
8
)
/
8
;
assert
(
Offset
+
NumBytes
<=
Data
.
size
(
)
&&
"Invalid fixup offset!"
)
;
bool
IsLittleEndian
=
(
Endian
==
support
::
little
)
;
bool
IsInstFixup
=
(
Kind
>=
FirstTargetFixupKind
)
;
if
(
IsLittleEndian
&&
IsInstFixup
&&
(
NumBytes
==
4
)
)
{
Data
[
Offset
+
0
]
|=
uint8_t
(
(
Value
>>
16
)
&
0xff
)
;
Data
[
Offset
+
1
]
|=
uint8_t
(
(
Value
>>
24
)
&
0xff
)
;
Data
[
Offset
+
2
]
|=
uint8_t
(
Value
&
0xff
)
;
Data
[
Offset
+
3
]
|=
uint8_t
(
(
Value
>>
8
)
&
0xff
)
;
}
else
{
for
(
unsigned
I
=
0
;
I
!=
NumBytes
;
I
++
)
{
unsigned
Idx
=
IsLittleEndian
I
:
(
NumBytes
1
I
)
;
Data
[
Offset
+
Idx
]
|=
uint8_t
(
(
Value
>>
(
I
*
8
)
)
&
0xff
)
;
}
}
}
</s>

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


<s> static unsigned int aarch64_unspec_cond_code ( rtx_code code ) { switch ( code ) { case NE : return UNSPEC_COND_NE ; case EQ : return UNSPEC_COND_EQ ; case LT : return UNSPEC_COND_LT ; case GT : return UNSPEC_COND_GT ; case LE : return UNSPEC_COND_LE ; case GE : return UNSPEC_COND_GE ; default : gcc_unreachable ( ) ; } } </s>

Return the UNSPEC_COND_ * code for comparison CODE .


<s> void AArch64CallLowering :: splitToValueTypes ( const ArgInfo & OrigArg , SmallVectorImpl < ArgInfo > & SplitArgs , const DataLayout & DL , MachineRegisterInfo & MRI , const SplitArgTy & PerformArgSplit ) const { const AArch64TargetLowering & TLI = * getTLI < AArch64TargetLowering > ( ) ; LLVMContext & Ctx = OrigArg . Ty -> getContext ( ) ; SmallVector < EVT , 4 > SplitVTs ; SmallVector < uint64_t , 4 > Offsets ; ComputeValueVTs ( TLI , DL , OrigArg . Ty , SplitVTs , & Offsets , 0 ) ; if ( SplitVTs . size ( ) == 1 ) { SplitArgs . emplace_back ( OrigArg . Reg , SplitVTs [ 0 ] . getTypeForEVT ( Ctx ) , OrigArg . Flags , OrigArg . IsFixed ) ; return ; } unsigned FirstRegIdx = SplitArgs . size ( ) ; for ( auto SplitVT : SplitVTs ) { Type * SplitTy = SplitVT . getTypeForEVT ( Ctx ) ; SplitArgs . push_back ( ArgInfo { MRI . createGenericVirtualRegister ( LLT { * SplitTy , DL } ) , SplitTy , OrigArg . Flags , OrigArg . IsFixed } ) ; } SmallVector < uint64_t , 4 > BitOffsets ; for ( auto Offset : Offsets ) BitOffsets . push_back ( Offset * 8 ) ; SmallVector < unsigned , 8 > SplitRegs ; for ( auto I = & SplitArgs [ FirstRegIdx ] ; I != SplitArgs . end ( ) ; ++ I ) SplitRegs . push_back ( I -> Reg ) ; PerformArgSplit ( SplitRegs , BitOffsets ) ; } </s>

Break OrigArgInfo into one or more pieces the calling convention can process , returned in SplitArgs .


<s> void FPGATTIImpl :: getUnrollingPreferences ( Loop * L , ScalarEvolution & SE , TTI :: UnrollingPreferences & UP ) { UP . Threshold = 0 ; UP . PartialThreshold = 0 ; UP . Count = 1 ; UP . MaxCount = 1 ; UP . FullUnrollMaxCount = 1 ; UP . Partial = false ; UP . Runtime = false ; UP . AllowRemainder = false ; } </s>

Get target-customized preferences for the generic loop unrolling transformation .


<s> const ARMTargetLowering * getTLI ( ) const { return TLI ; } </s>

Getter for generic TargetLowering class .


<s> bool isImm ( ) const override { return Kind == Immediate ; } </s>


<s> unsigned DLXMCCodeEmitter :: getMachineOpValue ( const MCInst & Inst , const MCOperand & MCOp , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & SubtargetInfo ) const { if ( MCOp . isReg ( ) ) return getDLXRegisterNumbering ( MCOp . getReg ( ) ) ; if ( MCOp . isImm ( ) ) return static_cast < unsigned > ( MCOp . getImm ( ) ) ; assert ( MCOp . isExpr ( ) ) ; const MCExpr * Expr = MCOp . getExpr ( ) ; if ( Expr -> getKind ( ) == MCExpr :: Binary ) { const MCBinaryExpr * BinaryExpr = static_cast < const MCBinaryExpr * > ( Expr ) ; Expr = BinaryExpr -> getLHS ( ) ; } assert ( isa < DLXMCExpr > ( Expr ) || Expr -> getKind ( ) == MCExpr :: SymbolRef ) ; Fixups . push_back ( MCFixup :: create ( 0 , MCOp . getExpr ( ) , MCFixupKind ( FixupKind ( Expr ) ) ) ) ; return 0 ; } </s>

getMachineOpValue - Return binary encoding of operand .


<s> bool function_resolver :: require_integer_immediate ( unsigned int argno ) { if ( ! scalar_argument_p ( argno ) ) { report_non_ice ( location , fndecl , argno ) ; return false ; } return true ; } </s>

Require argument ARGNO to be suitable for an integer constant expression . Return true if it is , otherwise report an appropriate error . function_checker checks whether the argument is actually constant and has a suitable range . The reason for distinguishing immediate arguments here is because it provides more consistent error messages than require_scalar_type would .


<s> enum aarch64_symbol_type aarch64_classify_symbol ( rtx x , HOST_WIDE_INT offset ) { if ( GET_CODE ( x ) == LABEL_REF ) { switch ( aarch64_cmodel ) { case AARCH64_CMODEL_LARGE : return SYMBOL_FORCE_TO_MEM ; case AARCH64_CMODEL_TINY_PIC : case AARCH64_CMODEL_TINY : return SYMBOL_TINY_ABSOLUTE ; case AARCH64_CMODEL_SMALL_SPIC : case AARCH64_CMODEL_SMALL_PIC : case AARCH64_CMODEL_SMALL : return SYMBOL_SMALL_ABSOLUTE ; default : gcc_unreachable ( ) ; } } if ( GET_CODE ( x ) == SYMBOL_REF ) { if ( aarch64_tls_symbol_p ( x ) ) return aarch64_classify_tls_symbol ( x ) ; switch ( aarch64_cmodel ) { case AARCH64_CMODEL_TINY : if ( SYMBOL_REF_WEAK ( x ) && ! aarch64_symbol_binds_local_p ( x ) ) return SYMBOL_FORCE_TO_MEM ; if ( ! ( IN_RANGE ( offset , - 0x10000 , 0x10000 ) || offset_within_block_p ( x , offset ) ) ) return SYMBOL_FORCE_TO_MEM ; return SYMBOL_TINY_ABSOLUTE ; case AARCH64_CMODEL_SMALL : if ( SYMBOL_REF_WEAK ( x ) && ! aarch64_symbol_binds_local_p ( x ) ) return SYMBOL_FORCE_TO_MEM ; if ( ! ( IN_RANGE ( offset , - 0x100000 , 0x100000 ) || offset_within_block_p ( x , offset ) ) ) return SYMBOL_FORCE_TO_MEM ; return SYMBOL_SMALL_ABSOLUTE ; case AARCH64_CMODEL_TINY_PIC : if ( ! aarch64_symbol_binds_local_p ( x ) ) return SYMBOL_TINY_GOT ; return SYMBOL_TINY_ABSOLUTE ; case AARCH64_CMODEL_SMALL_SPIC : case AARCH64_CMODEL_SMALL_PIC : if ( ! aarch64_symbol_binds_local_p ( x ) ) return ( aarch64_cmodel == AARCH64_CMODEL_SMALL_SPIC ? SYMBOL_SMALL_GOT_28K : SYMBOL_SMALL_GOT_4G ) ; return SYMBOL_SMALL_ABSOLUTE ; case AARCH64_CMODEL_LARGE : if ( ! aarch64_pcrelative_literal_loads && CONSTANT_POOL_ADDRESS_P ( x ) ) return SYMBOL_SMALL_ABSOLUTE ; else return SYMBOL_FORCE_TO_MEM ; default : gcc_unreachable ( ) ; } } return SYMBOL_FORCE_TO_MEM ; } </s>

Return the method that should be used to access SYMBOL_REF or LABEL_REF X .


<s> static inline bool is_reverse_perm_mask ( const struct expand_vec_perm_d & d ) { for ( int i = 0 ; i < d . nelt ; i ++ ) if ( d . perm [ i ] != d . nelt - i - 1 ) return false ; return true ; } </s>

Helper that checks if a vector permutation mask D represents a reversal of the vector 's elements .


<s> Value * AArch64TargetLowering :: emitStoreConditional ( IRBuilder < > & Builder , Value * Val , Value * Addr , AtomicOrdering Ord ) const { Module * M = Builder . GetInsertBlock ( ) -> getParent ( ) -> getParent ( ) ; bool IsRelease = isAtLeastRelease ( Ord ) ; if ( Val -> getType ( ) -> getPrimitiveSizeInBits ( ) == 128 ) { Intrinsic :: ID Int = IsRelease ? Intrinsic :: aarch64_stlxp : Intrinsic :: aarch64_stxp ; Function * Stxr = Intrinsic :: getDeclaration ( M , Int ) ; Type * Int64Ty = Type :: getInt64Ty ( M -> getContext ( ) ) ; Value * Lo = Builder . CreateTrunc ( Val , Int64Ty , "lo" ) ; Value * Hi = Builder . CreateTrunc ( Builder . CreateLShr ( Val , 64 ) , Int64Ty , "hi" ) ; Addr = Builder . CreateBitCast ( Addr , Type :: getInt8PtrTy ( M -> getContext ( ) ) ) ; return Builder . CreateCall3 ( Stxr , Lo , Hi , Addr ) ; } Intrinsic :: ID Int = IsRelease ? Intrinsic :: aarch64_stlxr : Intrinsic :: aarch64_stxr ; Type * Tys [ ] = { Addr -> getType ( ) } ; Function * Stxr = Intrinsic :: getDeclaration ( M , Int , Tys ) ; return Builder . CreateCall2 ( Stxr , Builder . CreateZExtOrBitCast ( Val , Stxr -> getFunctionType ( ) -> getParamType ( 0 ) ) , Addr ) ; } </s>

Perform a store-conditional operation to Addr .


<s> MachineBasicBlock * MipsSETargetLowering :: EmitInstrWithCustomInserter ( MachineInstr * MI , MachineBasicBlock * BB ) const { switch ( MI -> getOpcode ( ) ) { default : return MipsTargetLowering :: EmitInstrWithCustomInserter ( MI , BB ) ; } } </s>

This method should be implemented by targets that mark instructions with the 'usesCustomInserter ' flag .


<s> void VEAsmPrinter :: emitInstruction ( const MachineInstr * MI ) { switch ( MI -> getOpcode ( ) ) { default : break ; case TargetOpcode :: DBG_VALUE : return ; case VE :: GETGOT : lowerGETGOTAndEmitMCInsts ( MI , getSubtargetInfo ( ) ) ; return ; case VE :: GETFUNPLT : lowerGETFunPLTAndEmitMCInsts ( MI , getSubtargetInfo ( ) ) ; return ; case VE :: GETTLSADDR : lowerGETTLSAddrAndEmitMCInsts ( MI , getSubtargetInfo ( ) ) ; return ; } MachineBasicBlock :: const_instr_iterator I = MI -> getIterator ( ) ; MachineBasicBlock :: const_instr_iterator E = MI -> getParent ( ) -> instr_end ( ) ; do { MCInst TmpInst ; LowerVEMachineInstrToMCInst ( & * I , TmpInst , * this ) ; EmitToStreamer ( * OutStreamer , TmpInst ) ; } while ( ( ++ I != E ) && I -> isInsideBundle ( ) ) ; } </s>

Targets should implement this to emit instructions .

VE VE VE::GETGOT VE::GETFUNPLT VE::GETTLSADDR VE


"WebAssembly doesn't support non-C calling conventions"

"WebAssembly hasn't implemented inalloca arguments"

"WebAssembly hasn't implemented nest arguments"

"WebAssembly hasn't implemented cons regs arguments"

"WebAssembly hasn't implemented cons regs last arguments"

This hook must be implemented to lower the incoming ( formal ) arguments , described by the Ins array , into the specified DAG .


<s> bool AMDGPUAsmPrinter :: PrintAsmOperand ( const MachineInstr * MI , unsigned OpNo , unsigned AsmVariant , const char * ExtraCode , raw_ostream & O ) { if ( ExtraCode && ExtraCode [ 0 ] ) { if ( ExtraCode [ 1 ] != 0 ) return true ; switch ( ExtraCode [ 0 ] ) { default : return AsmPrinter :: PrintAsmOperand ( MI , OpNo , AsmVariant , ExtraCode , O ) ; case 'r' : break ; } } AMDGPUInstPrinter :: printRegOperand ( MI -> getOperand ( OpNo ) . getReg ( ) , O , * TM . getSubtargetImpl ( * MF -> getFunction ( ) ) -> getRegisterInfo ( ) ) ; return false ; } </s>

PrintAsmOperand - Print out an operand for an inline asm expression .


<s> unsigned X86InstrInfo :: getOpcodeAfterMemoryUnfold ( unsigned Opc , bool UnfoldLoad , bool UnfoldStore , unsigned * LoadRegIndex ) const { DenseMap < unsigned , std :: pair < unsigned , unsigned > > :: const_iterator I = MemOp2RegOpTable . find ( Opc ) ; if ( I == MemOp2RegOpTable . end ( ) ) return 0 ; bool FoldedLoad = I -> second . second & TB_FOLDED_LOAD ; bool FoldedStore = I -> second . second & TB_FOLDED_STORE ; if ( UnfoldLoad && ! FoldedLoad ) return 0 ; if ( UnfoldStore && ! FoldedStore ) return 0 ; if ( LoadRegIndex ) * LoadRegIndex = I -> second . second & TB_INDEX_MASK ; return I -> second . first ; } </s>

getOpcodeAfterMemoryUnfold - Returns the opcode of the would be new instruction after load / store are unfolded from an instruction of the specified opcode .


<s> bool X86PassConfig :: addPreRegAlloc ( ) { return false ; } </s>

This method may be implemented by targets that want to run passes immediately before register allocation .


<s> static void arc_internal_label ( FILE * stream , const char * prefix , unsigned long labelno ) { if ( cfun ) arc_ccfsm_at_label ( prefix , labelno , & arc_ccfsm_current ) ; default_internal_label ( stream , prefix , labelno ) ; } </s>

This is how to output a definition of an internal numbered label where PREFIX is the class of label and NUM is the number within the class .


<s> short PIC16DbgInfo :: getClass ( DIGlobalVariable DIGV ) { short ClassNo ; if ( PAN :: isLocalName ( DIGV . getGlobal ( ) -> getName ( ) ) ) { ClassNo = PIC16Dbg :: C_STAT ; } else if ( DIGV . isLocalToUnit ( ) ) ClassNo = PIC16Dbg :: C_STAT ; else ClassNo = PIC16Dbg :: C_EXT ; return ClassNo ; } </s>


<s> MachineBasicBlock :: iterator Cpu0FrameLowering :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { unsigned SP = Cpu0 :: SP ; if ( ! hasReservedCallFrame ( MF ) ) { int64_t Amount = I -> getOperand ( 0 ) . getImm ( ) ; if ( I -> getOpcode ( ) == Cpu0 :: ADJCALLSTACKDOWN ) Amount = - Amount ; STI . getInstrInfo ( ) -> adjustStackPtr ( SP , Amount , MBB , I ) ; } return MBB . erase ( I ) ; } </s>

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .


<s> static void eco32_compute_frame ( void ) { int regno ; int args_size ; int pretend_args_size ; args_size = ( ACCUMULATE_OUTGOING_ARGS ? crtl -> outgoing_args_size : 0 ) ; pretend_args_size = crtl -> args . pretend_args_size ; if ( pretend_args_size > 0 ) { cfun -> machine -> pretend_size = pretend_args_size ; } cfun -> machine -> fp_needed = FALSE ; if ( eco32_frame_pointer_required ( ) ) cfun -> machine -> fp_needed = TRUE ; cfun -> machine -> local_vars_size = get_frame_size ( ) ; cfun -> machine -> saved_reg_size = 0 ; for ( regno = 0 ; regno < FIRST_PSEUDO_REGISTER ; regno ++ ) if ( df_regs_ever_live_p ( regno ) && ( ! call_used_regs [ regno ] ) ) cfun -> machine -> saved_reg_size += ECO32_REG_SIZE ; if ( ! crtl -> is_leaf ) { cfun -> machine -> save_ret = 1 ; } cfun -> machine -> sp_fp_offset = args_size + cfun -> machine -> saved_reg_size + ( cfun -> machine -> save_ret ? ECO32_REG_SIZE : 0 ) ; cfun -> machine -> size_for_adjusting_sp = cfun -> machine -> local_vars_size + cfun -> machine -> saved_reg_size + ( cfun -> machine -> save_ret ? ECO32_REG_SIZE : 0 ) + args_size ; } </s>

Compute the size of the local area and the size to be adjusted by the prologue and epilogue .


<s> MachineInstr * X86InstrInfo :: foldMemoryOperandImpl ( MachineFunction & MF , MachineInstr & MI , ArrayRef < unsigned > Ops , MachineBasicBlock :: iterator InsertPt , int FrameIndex , LiveIntervals * LIS ) const { if ( NoFusing ) return nullptr ; if ( ! MF . getFunction ( ) . hasOptSize ( ) && ( hasPartialRegUpdate ( MI . getOpcode ( ) , Subtarget , true ) || shouldPreventUndefRegUpdateMemFold ( MF , MI ) ) ) return nullptr ; for ( auto Op : Ops ) { MachineOperand & MO = MI . getOperand ( Op ) ; auto SubReg = MO . getSubReg ( ) ; if ( SubReg && ( MO . isDef ( ) || SubReg == X86 :: sub_8bit_hi ) ) return nullptr ; } const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; unsigned Size = MFI . getObjectSize ( FrameIndex ) ; unsigned Alignment = MFI . getObjectAlignment ( FrameIndex ) ; if ( ! RI . needsStackRealignment ( MF ) ) Alignment = std :: min ( Alignment , Subtarget . getFrameLowering ( ) -> getStackAlignment ( ) ) ; if ( Ops . size ( ) == 2 && Ops [ 0 ] == 0 && Ops [ 1 ] == 1 ) { unsigned NewOpc = 0 ; unsigned RCSize = 0 ; switch ( MI . getOpcode ( ) ) { default : return nullptr ; case X86 :: TEST8rr : NewOpc = X86 :: CMP8ri ; RCSize = 1 ; break ; case X86 :: TEST16rr : NewOpc = X86 :: CMP16ri8 ; RCSize = 2 ; break ; case X86 :: TEST32rr : NewOpc = X86 :: CMP32ri8 ; RCSize = 4 ; break ; case X86 :: TEST64rr : NewOpc = X86 :: CMP64ri8 ; RCSize = 8 ; break ; } if ( Size < RCSize ) return nullptr ; MI . setDesc ( get ( NewOpc ) ) ; MI . getOperand ( 1 ) . ChangeToImmediate ( 0 ) ; } else if ( Ops . size ( ) != 1 ) return nullptr ; return foldMemoryOperandImpl ( MF , MI , Ops [ 0 ] , MachineOperand :: CreateFI ( FrameIndex ) , InsertPt , Size , Alignment , true ) ; } </s>

foldMemoryOperand - Same as the previous version except it allows folding of any load and store from / to any address , not just from a specific stack slot .


<s> MSP430Subtarget & MSP430Subtarget :: initializeSubtargetDependencies ( StringRef CPU , StringRef FS ) { ExtendedInsts = false ; HWMultMode = NoHWMult ; std :: string CPUName = CPU ; if ( CPUName . empty ( ) ) CPUName = "msp430" ; ParseSubtargetFeatures ( CPUName , FS ) ; if ( HWMultModeOption != NoHWMult ) HWMultMode = HWMultModeOption ; return * this ; } </s>

initializeSubtargetDependencies - Initializes using a CPU , a TuneCPU , and feature string so that we can use initializer lists for subtarget initialization .


"Instr does not have a Frame Index operand!"

"Currently LEA immediates must be in the range [-1023, 1023]"

This method must be overriden to eliminate abstract frame indices from instructions which may use them .


<s> bool X86OptimizeLEAPass :: runOnMachineFunction ( MachineFunction & MF ) { bool Changed = false ; if ( DisableX86LEAOpt || skipFunction ( MF . getFunction ( ) ) ) return false ; MRI = & MF . getRegInfo ( ) ; TII = MF . getSubtarget < X86Subtarget > ( ) . getInstrInfo ( ) ; TRI = MF . getSubtarget < X86Subtarget > ( ) . getRegisterInfo ( ) ; auto * PSI = & getAnalysis < ProfileSummaryInfoWrapperPass > ( ) . getPSI ( ) ; auto * MBFI = ( PSI && PSI -> hasProfileSummary ( ) ) ? & getAnalysis < LazyMachineBlockFrequencyInfoPass > ( ) . getBFI ( ) : nullptr ; for ( auto & MBB : MF ) { MemOpMap LEAs ; InstrPos . clear ( ) ; findLEAs ( MBB , LEAs ) ; if ( LEAs . empty ( ) ) continue ; Changed |= removeRedundantLEAs ( LEAs ) ; bool OptForSize = MF . getFunction ( ) . hasOptSize ( ) || llvm :: shouldOptimizeForSize ( & MBB , PSI , MBFI ) ; if ( OptForSize ) Changed |= removeRedundantAddrCalc ( LEAs ) ; } return Changed ; } </s>

runOnMachineFunction - Emit the function body .


<s> const MCExpr * PPC64LinuxTargetObjectFile :: getDebugThreadLocalSymbol ( const MCSymbol * Sym ) const { const MCExpr * Expr = MCSymbolRefExpr :: create ( Sym , MCSymbolRefExpr :: VK_PPC_DTPREL , getContext ( ) ) ; return MCBinaryExpr :: createAdd ( Expr , MCConstantExpr :: create ( 0x8000 , getContext ( ) ) , getContext ( ) ) ; } </s>

Describe a TLS variable address within debug info .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const { MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> bool mips_cfun_has_cprestore_slot_p ( void ) { return ( cfun -> machine -> global_pointer != INVALID_REGNUM && cfun -> machine -> frame . cprestore_size > 0 ) ; } </s>

Return true if the current function has a cprestore slot .


Add common target configurable passes that perform LLVM IR to IR transforms following machine independent optimization .

NVPTX NVPTX NVPTX NVPTX NVPTX NVPTX NVPTX


<s> static bool use_rsqrt_p ( machine_mode mode ) { return ( ( mode == HFmode || ( TARGET_SSE && TARGET_SSE_MATH ) ) && flag_finite_math_only && ! flag_trapping_math && flag_unsafe_math_optimizations ) ; } </s>

Return true if it is safe to use the rsqrt optabs to optimize 1.0/sqrt .


<s> bool apply_mask_policy_p ( ) const override { return false ; } </s>

We choose to apply mask policy operand by default since most of the intrinsics has mask policy operand .


<s> bool X86InstrInfo :: spillCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI ) const { if ( CSI . empty ( ) ) return false ; DebugLoc DL = DebugLoc :: getUnknownLoc ( ) ; if ( MI != MBB . end ( ) ) DL = MI -> getDebugLoc ( ) ; bool is64Bit = TM . getSubtarget < X86Subtarget > ( ) . is64Bit ( ) ; unsigned SlotSize = is64Bit ? 8 : 4 ; MachineFunction & MF = * MBB . getParent ( ) ; X86MachineFunctionInfo * X86FI = MF . getInfo < X86MachineFunctionInfo > ( ) ; X86FI -> setCalleeSavedFrameSize ( CSI . size ( ) * SlotSize ) ; unsigned Opc = is64Bit ? X86 :: PUSH64r : X86 :: PUSH32r ; for ( unsigned i = CSI . size ( ) ; i != 0 ; -- i ) { unsigned Reg = CSI [ i - 1 ] . getReg ( ) ; MBB . addLiveIn ( Reg ) ; BuildMI ( MBB , MI , DL , get ( Opc ) ) . addReg ( Reg , false , false , true ) ; } return true ; } </s>

spillCalleeSavedRegisters - Issues instruction ( s ) to spill all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of store instructions via storeRegToStackSlot ( ) .


"instruction use requires an option to be enabled"

"immediate must be a multiple of 2 bytes in the range"

MatchAndEmitInstruction - Recognize a series of operands of a parsed instruction as an actual MCInst and emit it to the specified MCStreamer .


<s> static void mcore_reorg ( void ) { current_function_anonymous_args = 0 ; if ( optimize == 0 ) return ; conditionalize_optimization ( ) ; } </s>

This is to handle loads from the constant pool .


<s> SMLoc getLoc ( ) const { return getParser ( ) . getTok ( ) . getLoc ( ) ; } </s>

Get the source location of the point where the field was defined .


<s>
void
SPUInstrInfo
::
storeRegToStackSlot
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
MI
,
unsigned
SrcReg
,
bool
isKill
,
int
FrameIdx
,
const
TargetRegisterClass
*
RC
,
const
TargetRegisterInfo
*
TRI
)
const
{
unsigned
opc
;
bool
isValidFrameIdx
=
(
FrameIdx
<
SPUFrameLowering
::
maxFrameOffset
(
)
)
;
if
(
RC
==
&
SPU
::
GPRCRegClass
)
opc
=
isValidFrameIdx
SPU
::
STQDr128
:
SPU
::
STQXr128
;
else
if
(
RC
==
&
SPU
::
R64CRegClass
)
opc
=
isValidFrameIdx
SPU
::
STQDr64
:
SPU
::
STQXr64
;
else
if
(
RC
==
&
SPU
::
R64FPRegClass
)
opc
=
isValidFrameIdx
SPU
::
STQDr64
:
SPU
::
STQXr64
;
else
if
(
RC
==
&
SPU
::
R32CRegClass
)
opc
=
isValidFrameIdx
SPU
::
STQDr32
:
SPU
::
STQXr32
;
else
if
(
RC
==
&
SPU
::
R32FPRegClass
)
opc
=
isValidFrameIdx
SPU
::
STQDr32
:
SPU
::
STQXr32
;
else
if
(
RC
==
&
SPU
::
R16CRegClass
)
opc
=
isValidFrameIdx
SPU
::
STQDr16
:
SPU
::
STQXr16
;
else
if
(
RC
==
&
SPU
::
R8CRegClass
)
opc
=
isValidFrameIdx
SPU
::
STQDr8
:
SPU
::
STQXr8
;
else
if
(
RC
==
&
SPU
::
VECREGRegClass
)
opc
=
isValidFrameIdx
SPU
::
STQDv16i8
:
SPU
::
STQXv16i8
;
else
llvm_unreachable
(
"Unknown regclass!"
)
;
DebugLoc
DL
;
if
(
MI
!=
MBB
.
end
(
)
)
DL
=
MI
->
getDebugLoc
(
)
;
addFrameReference
(
BuildMI
(
MBB
,
MI
,
DL
,
get
(
opc
)
)
.
addReg
(
SrcReg
,
getKillRegState
(
isKill
)
)
,
FrameIdx
)
;
}
</s>

Store the specified register of the given register class to the specified stack frame index .


<s> static void aarch64_run_selftests ( void ) { aarch64_test_loading_full_dump ( ) ; } </s>


<s>
bool
HexagonPassConfig
::
addInstSelector
(
)
{
HexagonTargetMachine
&
TM
=
getHexagonTargetMachine
(
)
;
bool
NoOpt
=
(
getOptLevel
(
)
==
CodeGenOpt
::
)
;
if
(
!
NoOpt
)
addPass
(
createHexagonOptimizeSZextends
(
)
)
;
addPass
(
createHexagonISelDag
(
TM
,
getOptLevel
(
)
)
)
;
if
(
!
NoOpt
)
{
if
(
EnableGenPred
)
addPass
(
createHexagonGenPredicate
(
)
,
false
)
;
if
(
EnableLoopResched
)
addPass
(
createHexagonLoopRescheduling
(
)
,
false
)
;
if
(
!
DisableHSDR
)
addPass
(
createHexagonSplitDoubleRegs
(
)
)
;
if
(
EnableBitSimplify
)
addPass
(
createHexagonBitSimplify
(
)
,
false
)
;
addPass
(
createHexagonPeephole
(
)
)
;
printAndVerify
(
"After hexagon peephole pass"
)
;
if
(
!
DisableHCP
)
{
addPass
(
createHexagonConstPropagationPass
(
)
,
false
)
;
addPass
(
&
UnreachableMachineBlockElimID
,
false
)
;
}
if
(
EnableGenInsert
)
addPass
(
createHexagonGenInsert
(
)
,
false
)
;
if
(
EnableEarlyIf
)
addPass
(
createHexagonEarlyIfConversion
(
)
,
false
)
;
}
return
false
;
}
</s>

addInstSelector - This method should install an instruction selector pass , which converts from LLVM code to machine instructions .

Hexagon
Hexagon
Hexagon
Hexagon
Hexagon
Hexagon
Hexagon
Hexagon
Hexagon
Hexagon
Hexagon
"After hexagon peephole pass"
Hexagon
Hexagon
Hexagon


<s> bool cr16_is_data_model ( enum data_model_type model ) { return ( model == data_model ) ; } </s>

Returns true if data model selected via command line option is same as function argument .


<s> void alpha_split_atomic_op ( enum rtx_code code , rtx mem , rtx val , rtx before , rtx after , rtx scratch , enum memmodel model ) { machine_mode mode = GET_MODE ( mem ) ; rtx label , x , cond = gen_rtx_REG ( DImode , REGNO ( scratch ) ) ; alpha_pre_atomic_barrier ( model ) ; label = gen_label_rtx ( ) ; emit_label ( label ) ; label = gen_rtx_LABEL_REF ( DImode , label ) ; if ( before == NULL ) before = scratch ; emit_load_locked ( mode , before , mem ) ; if ( code == NOT ) { x = gen_rtx_AND ( mode , before , val ) ; emit_insn ( gen_rtx_SET ( val , x ) ) ; x = gen_rtx_NOT ( mode , val ) ; } else x = gen_rtx_fmt_ee ( code , mode , before , val ) ; if ( after ) emit_insn ( gen_rtx_SET ( after , copy_rtx ( x ) ) ) ; emit_insn ( gen_rtx_SET ( scratch , x ) ) ; emit_store_conditional ( mode , cond , mem , scratch ) ; x = gen_rtx_EQ ( DImode , cond , const0_rtx ) ; emit_unlikely_jump ( x , label ) ; alpha_post_atomic_barrier ( model ) ; } </s>

Expand an an atomic fetch-and-operate pattern . CODE is the binary operation to perform . MEM is the memory on which to operate . VAL is the second operand of the binary operator . BEFORE and AFTER are optional locations to return the value of MEM either before of after the operation . SCRATCH is a scratch register .


"Can't store this register to stack slot"


<s> void PPCDispatchGroupSBHazardRecognizer :: EmitNoop ( ) { unsigned Directive = DAG -> MF . getSubtarget < PPCSubtarget > ( ) . getDarwinDirective ( ) ; if ( Directive == PPC :: DIR_PWR6 || Directive == PPC :: DIR_PWR7 || Directive == PPC :: DIR_PWR8 || CurSlots == 6 ) { CurGroup . clear ( ) ; CurSlots = CurBranches = 0 ; } else { CurGroup . push_back ( nullptr ) ; ++ CurSlots ; } } </s>

EmitNoop - This callback is invoked when a noop was added to the instruction stream .


<s> unsigned char AArch64Subtarget :: ClassifyGlobalReference ( const GlobalValue * GV , const TargetMachine & TM ) const { bool isDecl = GV -> hasAvailableExternallyLinkage ( ) ; if ( GV -> isDeclaration ( ) && ! GV -> isMaterializable ( ) ) isDecl = true ; if ( TM . getCodeModel ( ) == CodeModel :: Large && isTargetMachO ( ) ) return AArch64II :: MO_GOT ; if ( TM . getCodeModel ( ) == CodeModel :: Small && GV -> isWeakForLinker ( ) && isDecl ) return AArch64II :: MO_GOT ; if ( TM . getRelocationModel ( ) != Reloc :: Static && GV -> hasDefaultVisibility ( ) ) { if ( isTargetMachO ( ) ) return ( isDecl || GV -> isWeakForLinker ( ) ) ? AArch64II :: MO_GOT : AArch64II :: MO_NO_FLAG ; else return GV -> hasLocalLinkage ( ) ? AArch64II :: MO_NO_FLAG : AArch64II :: MO_GOT ; } return AArch64II :: MO_NO_FLAG ; } </s>

ClassifyGlobalReference - Find the target operand flags that describe how a global value should be referenced for the current subtarget .


"missing %<target%> attribute for multi-versioned %D"

This function returns true if FN1 and FN2 are versions of the same function , that is , the target strings of the function decls are different . This assumes that FN1 and FN2 have the same signature .


<s> bool runOnMachineFunction ( MachineFunction & F ) override { bool Changed = false ; for ( MachineFunction :: iterator FI = F . begin ( ) , FE = F . end ( ) ; FI != FE ; ++ FI ) Changed |= runOnMachineBasicBlock ( * FI ) ; return Changed ; } </s>

runOnMachineFunction - Emit the function body .


<s> const uint32_t * X86RegisterInfo :: getCallPreservedMask ( const MachineFunction & MF , CallingConv :: ID CC ) const { const X86Subtarget & Subtarget = MF . getSubtarget < X86Subtarget > ( ) ; bool HasSSE = Subtarget . hasSSE1 ( ) ; bool HasAVX = Subtarget . hasAVX ( ) ; bool HasAVX512 = Subtarget . hasAVX512 ( ) ; switch ( CC ) { case CallingConv :: GHC : case CallingConv :: HiPE : return CSR_NoRegs_RegMask ; case CallingConv :: AnyReg : if ( HasAVX ) return CSR_64_AllRegs_AVX_RegMask ; return CSR_64_AllRegs_RegMask ; case CallingConv :: PreserveMost : return CSR_64_RT_MostRegs_RegMask ; case CallingConv :: PreserveAll : if ( HasAVX ) return CSR_64_RT_AllRegs_AVX_RegMask ; return CSR_64_RT_AllRegs_RegMask ; case CallingConv :: CXX_FAST_TLS : if ( Is64Bit ) return CSR_64_TLS_Darwin_RegMask ; break ; case CallingConv :: Intel_OCL_BI : { if ( HasAVX512 && IsWin64 ) return CSR_Win64_Intel_OCL_BI_AVX512_RegMask ; if ( HasAVX512 && Is64Bit ) return CSR_64_Intel_OCL_BI_AVX512_RegMask ; if ( HasAVX && IsWin64 ) return CSR_Win64_Intel_OCL_BI_AVX_RegMask ; if ( HasAVX && Is64Bit ) return CSR_64_Intel_OCL_BI_AVX_RegMask ; if ( ! HasAVX && ! IsWin64 && Is64Bit ) return CSR_64_Intel_OCL_BI_RegMask ; break ; } case CallingConv :: HHVM : return CSR_64_HHVM_RegMask ; case CallingConv :: X86_RegCall : if ( Is64Bit ) { if ( IsWin64 ) { return ( HasSSE ? CSR_Win64_RegCall_RegMask : CSR_Win64_RegCall_NoSSE_RegMask ) ; } else { return ( HasSSE ? CSR_SysV64_RegCall_RegMask : CSR_SysV64_RegCall_NoSSE_RegMask ) ; } } else { return ( HasSSE ? CSR_32_RegCall_RegMask : CSR_32_RegCall_NoSSE_RegMask ) ; } case CallingConv :: Cold : if ( Is64Bit ) return CSR_64_MostRegs_RegMask ; break ; case CallingConv :: Win64 : return CSR_Win64_RegMask ; case CallingConv :: X86_64_SysV : return CSR_64_RegMask ; case CallingConv :: X86_INTR : if ( Is64Bit ) { if ( HasAVX512 ) return CSR_64_AllRegs_AVX512_RegMask ; if ( HasAVX ) return CSR_64_AllRegs_AVX_RegMask ; if ( HasSSE ) return CSR_64_AllRegs_RegMask ; return CSR_64_AllRegs_NoSSE_RegMask ; } else { if ( HasAVX512 ) return CSR_32_AllRegs_AVX512_RegMask ; if ( HasAVX ) return CSR_32_AllRegs_AVX_RegMask ; if ( HasSSE ) return CSR_32_AllRegs_SSE_RegMask ; return CSR_32_AllRegs_RegMask ; } default : break ; } if ( Is64Bit ) { if ( IsWin64 ) return CSR_Win64_RegMask ; if ( Subtarget . getTargetLowering ( ) -> supportSwiftError ( ) && MF . getFunction ( ) -> getAttributes ( ) . hasAttrSomewhere ( Attribute :: SwiftError ) ) return CSR_64_SwiftError_RegMask ; return CSR_64_RegMask ; } return CSR_32_RegMask ; } </s>

Return a mask of call-preserved registers for the given calling convention on the current function .


<s> void ARMBaseRegisterInfo :: materializeFrameBaseRegister ( MachineBasicBlock * MBB , unsigned BaseReg , int FrameIdx , int64_t Offset ) const { ARMFunctionInfo * AFI = MBB -> getParent ( ) -> getInfo < ARMFunctionInfo > ( ) ; unsigned ADDriOpc = ! AFI -> isThumbFunction ( ) ? ARM :: ADDri : ( AFI -> isThumb1OnlyFunction ( ) ? ARM :: tADDframe : ARM :: t2ADDri ) ; MachineBasicBlock :: iterator Ins = MBB -> begin ( ) ; DebugLoc DL ; if ( Ins != MBB -> end ( ) ) DL = Ins -> getDebugLoc ( ) ; const MachineFunction & MF = * MBB -> getParent ( ) ; MachineRegisterInfo & MRI = MBB -> getParent ( ) -> getRegInfo ( ) ; const TargetInstrInfo & TII = * MF . getSubtarget ( ) . getInstrInfo ( ) ; const MCInstrDesc & MCID = TII . get ( ADDriOpc ) ; MRI . constrainRegClass ( BaseReg , TII . getRegClass ( MCID , 0 , this , MF ) ) ; MachineInstrBuilder MIB = BuildMI ( * MBB , Ins , DL , MCID , BaseReg ) . addFrameIndex ( FrameIdx ) . addImm ( Offset ) ; if ( ! AFI -> isThumb1OnlyFunction ( ) ) AddDefaultCC ( AddDefaultPred ( MIB ) ) ; } </s>

Insert defining instruction ( s ) for a pointer to FrameIdx before insertion point I .

ARM ARM ARM ARM ARM::ADDri ARM::tADDframe ARM::t2ADDri 0


Load the specified register of the given register class from the specified stack frame index .


<s>
const
char
*
getPassName
(
)
const
override
{
return
"AArch64 Store Pair Suppression"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> void MipsTargetObjectFile :: Initialize ( MCContext & Ctx , const TargetMachine & TM ) { TargetLoweringObjectFileELF :: Initialize ( Ctx , TM ) ; InitializeELF ( TM . Options . UseInitArray ) ; SmallDataSection = getContext ( ) . getELFSection ( ".sdata" , ELF :: SHT_PROGBITS , ELF :: SHF_WRITE | ELF :: SHF_ALLOC , SectionKind :: getDataRel ( ) ) ; SmallBSSSection = getContext ( ) . getELFSection ( ".sbss" , ELF :: SHT_NOBITS , ELF :: SHF_WRITE | ELF :: SHF_ALLOC , SectionKind :: getBSS ( ) ) ; } </s>

This method must be called before any actual lowering is done .


"Unexpected commutable machine instruction."

Returns true iff the routine could find two commutable operands in the given machine instruction .


"Offset must be aligned to 4 bytes because memory is "

This method must be overriden to eliminate abstract frame indices from instructions which may use them .


<s> Value * simplify ( Instruction * I , const TargetLibraryInfo * TLI , const DominatorTree * DT ) { return SimplifyInstruction ( I , { * TD , TLI , DT } ) ; } </s>

Go through all the nodes in the graph and collapse any two nodes ' a ' and ' b ' if all of the following are true :


<s> BitVector MSP430RegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; const TargetFrameLowering * TFI = MF . getTarget ( ) . getFrameLowering ( ) ; Reserved . set ( MSP430 :: PCW ) ; Reserved . set ( MSP430 :: SPW ) ; Reserved . set ( MSP430 :: SRW ) ; Reserved . set ( MSP430 :: CGW ) ; if ( TFI -> hasFP ( MF ) ) Reserved . set ( MSP430 :: FPW ) ; return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s> const uint16_t * X86RegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { switch ( MF -> getFunction ( ) -> getCallingConv ( ) ) { case CallingConv :: GHC : case CallingConv :: HiPE : return CSR_NoRegs_SaveList ; case CallingConv :: Intel_OCL_BI : { bool HasAVX = TM . getSubtarget < X86Subtarget > ( ) . hasAVX ( ) ; bool HasAVX512 = TM . getSubtarget < X86Subtarget > ( ) . hasAVX512 ( ) ; if ( HasAVX512 && IsWin64 ) return CSR_Win64_Intel_OCL_BI_AVX512_SaveList ; if ( HasAVX512 && Is64Bit ) return CSR_64_Intel_OCL_BI_AVX512_SaveList ; if ( HasAVX && IsWin64 ) return CSR_Win64_Intel_OCL_BI_AVX_SaveList ; if ( HasAVX && Is64Bit ) return CSR_64_Intel_OCL_BI_AVX_SaveList ; if ( ! HasAVX && ! IsWin64 && Is64Bit ) return CSR_64_Intel_OCL_BI_SaveList ; break ; } case CallingConv :: Cold : if ( Is64Bit ) return CSR_MostRegs_64_SaveList ; break ; default : break ; } bool CallsEHReturn = MF -> getMMI ( ) . callsEHReturn ( ) ; if ( Is64Bit ) { if ( IsWin64 ) return CSR_Win64_SaveList ; if ( CallsEHReturn ) return CSR_64EHRet_SaveList ; return CSR_64_SaveList ; } if ( CallsEHReturn ) return CSR_32EHRet_SaveList ; return CSR_32_SaveList ; } </s>


<s> unsigned getNumFixupKinds ( ) const override { return WebAssembly :: NumTargetFixupKinds ; } </s>

Get the number of target specific fixup kinds .


<s> bool legitimate_constant_pool_address_p ( const_rtx x , machine_mode mode , bool strict ) { return ( toc_relative_expr_p ( x , strict ) && ( TARGET_CMODEL != CMODEL_MEDIUM || constant_pool_expr_p ( XVECEXP ( tocrel_base , 0 , 0 ) ) || mode == QImode || offsettable_ok_by_alignment ( XVECEXP ( tocrel_base , 0 , 0 ) , INTVAL ( tocrel_offset ) , mode ) ) ) ; } </s>

Return true if X is a constant pool address , and also for cmodel=medium if X is a toc-relative address known to be offsettable within MODE .


<s> static unsigned long arm_compute_save_reg_mask ( void ) { unsigned int save_reg_mask = 0 ; unsigned long func_type = arm_current_func_type ( ) ; unsigned int reg ; if ( IS_NAKED ( func_type ) ) return 0 ; if ( TARGET_APCS_FRAME && frame_pointer_needed && TARGET_ARM ) save_reg_mask |= ( 1 << ARM_HARD_FRAME_POINTER_REGNUM ) | ( 1 << IP_REGNUM ) | ( 1 << LR_REGNUM ) | ( 1 << PC_REGNUM ) ; save_reg_mask |= arm_compute_save_reg0_reg12_mask ( ) ; if ( df_regs_ever_live_p ( LR_REGNUM ) || ( save_reg_mask && optimize_size && ARM_FUNC_TYPE ( func_type ) == ARM_FT_NORMAL && ! crtl -> tail_call_emit && ! crtl -> calls_eh_return ) ) save_reg_mask |= 1 << LR_REGNUM ; if ( cfun -> machine -> lr_save_eliminated ) save_reg_mask &= ~ ( 1 << LR_REGNUM ) ; if ( TARGET_REALLY_IWMMXT && ( ( bit_count ( save_reg_mask ) + ARM_NUM_INTS ( crtl -> args . pretend_args_size + arm_compute_static_chain_stack_bytes ( ) ) ) % 2 ) != 0 ) { for ( reg = 4 ; reg <= 12 ; reg ++ ) if ( ( save_reg_mask & ( 1 << reg ) ) == 0 ) break ; if ( reg <= 12 ) save_reg_mask |= ( 1 << reg ) ; else { cfun -> machine -> sibcall_blocked = 1 ; save_reg_mask |= ( 1 << 3 ) ; } } if ( TARGET_THUMB2 && IS_NESTED ( func_type ) && flag_pic && ( save_reg_mask & THUMB2_WORK_REGS ) == 0 ) { reg = thumb_find_work_register ( 1 << 4 ) ; if ( ! call_used_regs [ reg ] ) save_reg_mask |= ( 1 << reg ) ; } return save_reg_mask ; } </s>

Compute a bit mask of which registers need to be saved on the stack for the current function . This is used by arm_get_frame_offsets , which may add extra registers .


<s> void sh_remove_reg_dead_or_unused_notes ( rtx_insn * i , int regno ) { if ( rtx n = find_regno_note ( i , REG_DEAD , regno ) ) remove_note ( i , n ) ; if ( rtx n = find_regno_note ( i , REG_UNUSED , regno ) ) remove_note ( i , n ) ; } </s>

Given an insn and a reg number , remove reg dead or reg unused notes to mark it as being used after the insn .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . addRequired < MachineDominatorTree > ( ) ; AU . addPreserved < MachineDominatorTree > ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s>
bool
MOSNoRecurse
::
runOnSCC
(
CallGraphSCC
&
SCC
)
{
if
(
!
SCC
.
isSingular
(
)
)
return
false
;
const
CallGraphNode
&
N
=
*
*
SCC
.
begin
(
)
;
if
(
!
N
.
getFunction
(
)
||
N
.
getFunction
(
)
->
isDeclaration
(
)
||
N
.
getFunction
(
)
->
doesNotRecurse
(
)
)
return
false
;
if
(
callsSelf
(
N
)
)
return
false
;
LLVM_DEBUG
(
dbgs
(
)
<<
"Found new non-recursive function.\n"
)
;
LLVM_DEBUG
(
N
.
print
(
dbgs
(
)
)
)
;
N
.
getFunction
(
)
->
setDoesNotRecurse
(
)
;
return
true
;
}
</s>

runOnSCC - This method should be implemented by the subclass to perform whatever action is necessary for the specified SCC .

MOS
MOS
"Found new non-recursive function.\n"


<s>
SDValue
XCoreTargetLowering
::
LowerOperation
(
SDValue
Op
,
SelectionDAG
&
DAG
)
{
switch
(
Op
.
getOpcode
(
)
)
{
case
ISD
::
GlobalAddress
:
return
LowerGlobalAddress
(
Op
,
DAG
)
;
case
ISD
::
GlobalTLSAddress
:
return
LowerGlobalTLSAddress
(
Op
,
DAG
)
;
case
ISD
::
BlockAddress
:
return
LowerBlockAddress
(
Op
,
DAG
)
;
case
ISD
::
ConstantPool
:
return
LowerConstantPool
(
Op
,
DAG
)
;
case
ISD
::
BR_JT
:
return
LowerBR_JT
(
Op
,
DAG
)
;
case
ISD
::
LOAD
:
return
LowerLOAD
(
Op
,
DAG
)
;
case
ISD
::
STORE
:
return
LowerSTORE
(
Op
,
DAG
)
;
case
ISD
::
SELECT_CC
:
return
LowerSELECT_CC
(
Op
,
DAG
)
;
case
ISD
::
VAARG
:
return
LowerVAARG
(
Op
,
DAG
)
;
case
ISD
::
VASTART
:
return
LowerVASTART
(
Op
,
DAG
)
;
case
ISD
::
ADD
:
case
ISD
::
SUB
:
return
ExpandADDSUB
(
Op
.
getNode
(
)
,
DAG
)
;
case
ISD
::
FRAMEADDR
:
return
LowerFRAMEADDR
(
Op
,
DAG
)
;
default
:
llvm_unreachable
(
"unimplemented operand"
)
;
return
SDValue
(
)
;
}
}
</s>

LowerOperation - Provide custom lowering hooks for some operations .

XCore
XCore
ISD::GlobalAddress
ISD::GlobalTLSAddress
ISD::BlockAddress
ISD::ConstantPool
ISD::BR_JT
ISD::LOAD
ISD::STORE
ISD::SELECT_CC
ISD::VAARG
ISD::VASTART
ISD::ADD
ISD::SUB
ISD::FRAMEADDR
"unimplemented operand"


<s> void PrintSpecial ( const MCInst * MI , raw_ostream & O , const char * Kind ) { } </s>

Print information related to the specified machine instr that is independent of the operand , and may be independent of the instr itself .


<s> static void mips_sim_init ( struct mips_sim * state , state_t dfa_state ) { if ( targetm . sched . init_dfa_pre_cycle_insn ) targetm . sched . init_dfa_pre_cycle_insn ( ) ; if ( targetm . sched . init_dfa_post_cycle_insn ) targetm . sched . init_dfa_post_cycle_insn ( ) ; state -> issue_rate = mips_issue_rate ( ) ; state -> dfa_state = dfa_state ; mips_sim_reset ( state ) ; } </s>

Initialize STATE before its first use . DFA_STATE points to an allocated but uninitialized DFA state .


<s> AArch64Subtarget :: AArch64Subtarget ( const Triple & TT , const std :: string & CPU , const std :: string & TuneCPU , const std :: string & FS , const TargetMachine & TM , bool LittleEndian , unsigned MinSVEVectorSizeInBitsOverride , unsigned MaxSVEVectorSizeInBitsOverride ) : AArch64GenSubtargetInfo ( TT , CPU , TuneCPU , FS ) , ReserveXRegister ( AArch64 :: GPR64commonRegClass . getNumRegs ( ) ) , CustomCallSavedXRegs ( AArch64 :: GPR64commonRegClass . getNumRegs ( ) ) , IsLittle ( LittleEndian ) , MinSVEVectorSizeInBits ( MinSVEVectorSizeInBitsOverride ) , MaxSVEVectorSizeInBits ( MaxSVEVectorSizeInBitsOverride ) , TargetTriple ( TT ) , InstrInfo ( initializeSubtargetDependencies ( FS , CPU , TuneCPU ) ) , TLInfo ( TM , * this ) { if ( AArch64 :: isX18ReservedByDefault ( TT ) ) ReserveXRegister . set ( 18 ) ; CallLoweringInfo . reset ( new AArch64CallLowering ( * getTargetLowering ( ) ) ) ; InlineAsmLoweringInfo . reset ( new InlineAsmLowering ( getTargetLowering ( ) ) ) ; Legalizer . reset ( new AArch64LegalizerInfo ( * this ) ) ; auto * RBI = new AArch64RegisterBankInfo ( * getRegisterInfo ( ) ) ; InstSelector . reset ( createAArch64InstructionSelector ( * static_cast < const AArch64TargetMachine * > ( & TM ) , * this , * RBI ) ) ; RegBankInfo . reset ( RBI ) ; } </s>

This constructor initializes the data members to match that of the specified triple .


<s> rtx rs6000_gen_le_vsx_permute ( rtx source , machine_mode mode ) { if ( FLOAT128_VECTOR_P ( mode ) || mode == TImode || mode == V1TImode ) return gen_rtx_ROTATE ( mode , source , GEN_INT ( 64 ) ) ; else { rtx par = gen_rtx_PARALLEL ( VOIDmode , rs6000_const_vec ( mode ) ) ; return gen_rtx_VEC_SELECT ( mode , source , par ) ; } } </s>

Generate a permute rtx that represents an lxvd2x , stxvd2x , or xxpermdi for a VSX load or store operation .


<s> static bool isZero ( Register Reg , const MachineRegisterInfo & MRI ) { int64_t Val ; return mi_match ( Reg , MRI , m_ICst ( Val ) ) && Val == 0 ; } </s>

Return true if the expression is a constant zero .


<s> bool MipsExpandPseudo :: runOnMachineFunction ( MachineFunction & F ) { bool Changed = false ; for ( MachineFunction :: iterator I = F . begin ( ) ; I != F . end ( ) ; ++ I ) Changed |= runOnMachineBasicBlock ( * I ) ; return Changed ; } </s>

runOnMachineFunction - Emit the function body .


<s>
void
WebAssemblyTargetAsmStreamer
::
emitTableType
(
const
MCSymbolWasm
*
Sym
)
{
assert
(
Sym
->
isTable
(
)
)
;
OS
<<
"\t.tabletype\t"
<<
Sym
->
getName
(
)
<<
", "
<<
WebAssembly
::
typeToString
(
Sym
->
getTableType
(
)
)
;
OS
<<
'\n'
;
}
</s>

WebAssembly
WebAssembly
"\t.tabletype\t"
", "
WebAssembly::typeToString


<s> bool ARM64LoadStoreOpt :: runOnMachineFunction ( MachineFunction & Fn ) { const TargetMachine & TM = Fn . getTarget ( ) ; TII = static_cast < const ARM64InstrInfo * > ( TM . getInstrInfo ( ) ) ; TRI = TM . getRegisterInfo ( ) ; bool Modified = false ; for ( auto & MBB : Fn ) Modified |= optimizeBlock ( MBB ) ; return Modified ; } </s>


<s> static enum aarch64_parse_opt_result aarch64_parse_cpu ( const char * to_parse , const struct processor * * res , uint64_t * isa_flags , std :: string * invalid_extension ) { const char * ext ; const struct processor * cpu ; size_t len ; ext = strchr ( to_parse , '+' ) ; if ( ext != NULL ) len = ext - to_parse ; else len = strlen ( to_parse ) ; if ( len == 0 ) return AARCH64_PARSE_MISSING_ARG ; for ( cpu = all_cores ; cpu -> name != NULL ; cpu ++ ) { if ( strlen ( cpu -> name ) == len && strncmp ( cpu -> name , to_parse , len ) == 0 ) { uint64_t isa_temp = cpu -> flags ; if ( ext != NULL ) { enum aarch64_parse_opt_result ext_res = aarch64_parse_extension ( ext , & isa_temp , invalid_extension ) ; if ( ext_res != AARCH64_PARSE_OK ) return ext_res ; } * res = cpu ; * isa_flags = isa_temp ; return AARCH64_PARSE_OK ; } } return AARCH64_PARSE_INVALID_ARG ; } </s>

Parse the TO_PARSE string and put the result tuning in RES and the architecture flags in ISA_FLAGS . Return an aarch64_parse_opt_result describing the parse result . If there is an error parsing , RES and ISA_FLAGS are left unchanged .


<s> BitVector RISCVRegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { const RISCVFrameLowering * TFI = getFrameLowering ( MF ) ; BitVector Reserved ( getNumRegs ( ) ) ; for ( size_t Reg = 0 ; Reg < getNumRegs ( ) ; Reg ++ ) { if ( MF . getSubtarget < RISCVSubtarget > ( ) . isRegisterReservedByUser ( Reg ) ) markSuperRegs ( Reserved , Reg ) ; } markSuperRegs ( Reserved , RISCV :: X0 ) ; markSuperRegs ( Reserved , RISCV :: X2 ) ; markSuperRegs ( Reserved , RISCV :: X3 ) ; markSuperRegs ( Reserved , RISCV :: X4 ) ; if ( TFI -> hasFP ( MF ) ) markSuperRegs ( Reserved , RISCV :: X8 ) ; if ( TFI -> hasBP ( MF ) ) markSuperRegs ( Reserved , RISCVABI :: getBPReg ( ) ) ; markSuperRegs ( Reserved , RISCV :: VL ) ; markSuperRegs ( Reserved , RISCV :: VTYPE ) ; markSuperRegs ( Reserved , RISCV :: VXSAT ) ; markSuperRegs ( Reserved , RISCV :: VXRM ) ; assert ( checkAllSuperRegsMarked ( Reserved ) ) ; return Reserved ; } </s>


<s> bool riscv_can_use_return_insn ( void ) { return ( reload_completed && known_eq ( cfun -> machine -> frame . total_size , 0 ) && ! cfun -> machine -> interrupt_handler_p ) ; } </s>

Return nonzero if this function is known to have a null epilogue . This allows the optimizer to omit jumps to jumps if no stack was created .


"Disqualifying LR because GPR0 is live "


<s> static int riscv_arg_partial_bytes ( cumulative_args_t cum , enum machine_mode mode , tree type , bool named ) { struct riscv_arg_info arg ; riscv_get_arg_info ( & arg , get_cumulative_args ( cum ) , mode , type , named , false ) ; return arg . stack_p ? arg . num_gprs * UNITS_PER_WORD : 0 ; } </s>


<s>
void
mips_output_filename
(
FILE
*
stream
,
const
char
*
name
)
{
if
(
write_symbols
==
DWARF2_DEBUG
)
return
;
else
if
(
mips_output_filename_first_time
)
{
mips_output_filename_first_time
=
0
;
num_source_filenames
+=
1
;
current_function_file
=
name
;
fprintf
(
stream
,
"\t.file\t%d "
,
num_source_filenames
)
;
output_quoted_string
(
stream
,
name
)
;
putc
(
'\n'
,
stream
)
;
}
else
if
(
write_symbols
==
DBX_DEBUG
)
return
;
else
if
(
name
!=
current_function_file
&&
strcmp
(
name
,
current_function_file
)
!=
0
)
{
num_source_filenames
+=
1
;
current_function_file
=
name
;
fprintf
(
stream
,
"\t.file\t%d "
,
num_source_filenames
)
;
output_quoted_string
(
stream
,
name
)
;
putc
(
'\n'
,
stream
)
;
}
}
</s>

Emit a new filename to a stream . If we are smuggling stabs , try to put out a MIPS ECOFF file and a stab .


<s>
static
void
rs6000_parse_yes_no_option
(
const
char
*
name
,
const
char
*
value
,
int
*
flag
)
{
if
(
value
==
0
)
return
;
else
if
(
!
strcmp
(
value
,
"yes"
)
)
*
flag
=
1
;
else
if
(
!
strcmp
(
value
,
"no"
)
)
*
flag
=
0
;
else
error
(
"unknown -m%s= option specified: '%s'"
,
name
,
value
)
;
}
</s>

Handle generic options of the form -mfoo=yes/no . NAME is the option name . VALUE is the option value . FLAG is the pointer to the flag where to store a 1 or 0 , depending on whether the option value is 'yes ' or 'no ' respectively .


<s> static bool mips_valid_base_register_p ( rtx x , machine_mode mode , bool strict_p ) { if ( ! strict_p && GET_CODE ( x ) == SUBREG ) x = SUBREG_REG ( x ) ; return ( REG_P ( x ) && mips_regno_mode_ok_for_base_p ( REGNO ( x ) , mode , strict_p ) ) ; } </s>

Return true if X is a valid base register for the given mode . Allow only hard registers if STRICT .


<s> static void tilepro_function_arg_advance ( cumulative_args_t cum_v , machine_mode mode , const_tree type , bool named ATTRIBUTE_UNUSED ) { CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; int byte_size = ( ( mode == BLKmode ) ? int_size_in_bytes ( type ) : GET_MODE_SIZE ( mode ) ) ; int word_size = ( byte_size + UNITS_PER_WORD - 1 ) / UNITS_PER_WORD ; bool doubleword_aligned_p ; doubleword_aligned_p = tilepro_function_arg_boundary ( mode , type ) > BITS_PER_WORD ; if ( doubleword_aligned_p ) * cum += * cum & 1 ; if ( * cum < TILEPRO_NUM_ARG_REGS && * cum + word_size > TILEPRO_NUM_ARG_REGS ) * cum = TILEPRO_NUM_ARG_REGS ; * cum += word_size ; } </s>


<s> bool SystemZTargetLowering :: isLegalAddressingMode ( const AddrMode & AM , Type * Ty ) const { if ( AM . BaseGV ) return false ; if ( ! isInt < 20 > ( AM . BaseOffs ) ) return false ; return AM . Scale == 0 || AM . Scale == 1 ; } </s>

isLegalAddressingMode - Return true if the addressing mode represented by AM is legal for this target , for a load/store of the specified type .


<s> static rtx v850_function_value ( const_tree valtype , const_tree fn_decl_or_type ATTRIBUTE_UNUSED , bool outgoing ATTRIBUTE_UNUSED ) { return gen_rtx_REG ( TYPE_MODE ( valtype ) , RV_REGNUM ) ; } </s>

Worker function for TARGET_FUNCTION_VALUE .


<s> static int mingw32_gt_pch_use_address ( void * addr , size_t size , int fd , size_t offset ) { void * mmap_addr ; static HANDLE mmap_handle ; if ( size == 0 ) return 0 ; if ( ( offset & ( va_granularity - 1 ) ) != 0 || size > pch_VA_max_size ) return - 1 ; mmap_handle = CreateFileMapping ( ( HANDLE ) _get_osfhandle ( fd ) , NULL , PAGE_WRITECOPY | SEC_COMMIT , 0 , 0 , NULL ) ; if ( mmap_handle == NULL ) { w32_error ( __FUNCTION__ , __FILE__ , __LINE__ , "CreateFileMapping" ) ; return - 1 ; } mmap_addr = MapViewOfFileEx ( mmap_handle , FILE_MAP_COPY , 0 , offset , size , addr ) ; if ( mmap_addr != addr ) { w32_error ( __FUNCTION__ , __FILE__ , __LINE__ , "MapViewOfFileEx" ) ; CloseHandle ( mmap_handle ) ; return - 1 ; } return 1 ; } </s>

ADDR is an address returned by gt_pch_get_address . Attempt to allocate SIZE bytes at the same address and load it with the data from FD at OFFSET . Return -1 if we could n't allocate memory at ADDR , return 0 if the memory is allocated but the data not loaded , return 1 if done .


<s>
static
void
mmix_asm_output_source_filename
(
FILE
*
stream
,
const
char
*
name
)
{
fprintf
(
stream
,
"# 1 "
)
;
OUTPUT_QUOTED_STRING
(
stream
,
name
)
;
fprintf
(
stream
,
"\n"
)
;
}
</s>


<s> bool PPCPassConfig :: addInstSelector ( ) { addPass ( createPPCISelDag ( getPPCTargetMachine ( ) ) ) ; return false ; } </s>

addInstSelector - This method should install an instruction selector pass , which converts from LLVM code to machine instructions .


<s> bool Thumb1RegisterInfo :: saveScavengerRegister ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , MachineBasicBlock :: iterator & UseMI , const TargetRegisterClass * RC , unsigned Reg ) const { DebugLoc DL ; AddDefaultPred ( BuildMI ( MBB , I , DL , TII . get ( ARM :: tMOVr ) ) . addReg ( ARM :: R12 , RegState :: Define ) . addReg ( Reg , RegState :: Kill ) ) ; bool done = false ; for ( MachineBasicBlock :: iterator II = I ; ! done && II != UseMI ; ++ II ) { if ( II -> isDebugValue ( ) ) continue ; for ( unsigned i = 0 , e = II -> getNumOperands ( ) ; i != e ; ++ i ) { const MachineOperand & MO = II -> getOperand ( i ) ; if ( ! MO . isReg ( ) || MO . isUndef ( ) || ! MO . getReg ( ) || TargetRegisterInfo :: isVirtualRegister ( MO . getReg ( ) ) ) continue ; if ( MO . getReg ( ) == ARM :: R12 ) { UseMI = II ; done = true ; break ; } } } AddDefaultPred ( BuildMI ( MBB , UseMI , DL , TII . get ( ARM :: tMOVr ) ) . addReg ( Reg , RegState :: Define ) . addReg ( ARM :: R12 , RegState :: Kill ) ) ; return true ; } </s>

Spill the register so it can be used by the register scavenger .


"emitEpilogue doesn't support framepointer-less functions"


<s> bool X86TargetLowering :: isShuffleMaskLegal ( const SmallVectorImpl < int > & M , EVT VT ) const { if ( VT . getSizeInBits ( ) == 64 ) return isPALIGNRMask ( M , VT , Subtarget -> hasSSSE3 ( ) || Subtarget -> hasAVX ( ) ) ; return ( VT . getVectorNumElements ( ) == 2 || ShuffleVectorSDNode :: isSplatMask ( & M [ 0 ] , VT ) || isMOVLMask ( M , VT ) || isSHUFPMask ( M , VT ) || isPSHUFDMask ( M , VT ) || isPSHUFHWMask ( M , VT ) || isPSHUFLWMask ( M , VT ) || isPALIGNRMask ( M , VT , Subtarget -> hasSSSE3 ( ) || Subtarget -> hasAVX ( ) ) || isUNPCKLMask ( M , VT ) || isUNPCKHMask ( M , VT ) || isUNPCKL_v_undef_Mask ( M , VT ) || isUNPCKH_v_undef_Mask ( M , VT ) ) ; } </s>

Targets can use this to indicate that they only support some VECTOR_SHUFFLE operations , those with specific masks .


<s> SDValue R600TargetLowering :: LowerFormalArguments ( SDValue Chain , CallingConv :: ID CallConv , bool isVarArg , const SmallVectorImpl < ISD :: InputArg > & Ins , const SDLoc & DL , SelectionDAG & DAG , SmallVectorImpl < SDValue > & InVals ) const { SmallVector < CCValAssign , 16 > ArgLocs ; CCState CCInfo ( CallConv , isVarArg , DAG . getMachineFunction ( ) , ArgLocs , * DAG . getContext ( ) ) ; MachineFunction & MF = DAG . getMachineFunction ( ) ; R600MachineFunctionInfo * MFI = MF . getInfo < R600MachineFunctionInfo > ( ) ; SmallVector < ISD :: InputArg , 8 > LocalIns ; if ( AMDGPU :: isShader ( CallConv ) ) { CCInfo . AnalyzeFormalArguments ( Ins , CCAssignFnForCall ( CallConv , isVarArg ) ) ; } else { analyzeFormalArgumentsCompute ( CCInfo , Ins ) ; } for ( unsigned i = 0 , e = Ins . size ( ) ; i < e ; ++ i ) { CCValAssign & VA = ArgLocs [ i ] ; const ISD :: InputArg & In = Ins [ i ] ; EVT VT = In . VT ; EVT MemVT = VA . getLocVT ( ) ; if ( ! VT . isVector ( ) && MemVT . isVector ( ) ) { MemVT = MemVT . getVectorElementType ( ) ; } if ( AMDGPU :: isShader ( CallConv ) ) { unsigned Reg = MF . addLiveIn ( VA . getLocReg ( ) , & AMDGPU :: R600_Reg128RegClass ) ; SDValue Register = DAG . getCopyFromReg ( Chain , DL , Reg , VT ) ; InVals . push_back ( Register ) ; continue ; } PointerType * PtrTy = PointerType :: get ( VT . getTypeForEVT ( * DAG . getContext ( ) ) , AMDGPUASI . CONSTANT_BUFFER_0 ) ; ISD :: LoadExtType Ext = ISD :: NON_EXTLOAD ; if ( MemVT . getScalarSizeInBits ( ) != VT . getScalarSizeInBits ( ) ) { Ext = ISD :: SEXTLOAD ; } unsigned ValBase = ArgLocs [ In . getOrigArgIndex ( ) ] . getLocMemOffset ( ) ; unsigned PartOffset = VA . getLocMemOffset ( ) ; unsigned Offset = Subtarget -> getExplicitKernelArgOffset ( MF ) + VA . getLocMemOffset ( ) ; MachinePointerInfo PtrInfo ( UndefValue :: get ( PtrTy ) , PartOffset - ValBase ) ; SDValue Arg = DAG . getLoad ( ISD :: UNINDEXED , Ext , VT , DL , Chain , DAG . getConstant ( Offset , DL , MVT :: i32 ) , DAG . getUNDEF ( MVT :: i32 ) , PtrInfo , MemVT , 4 , MachineMemOperand :: MONonTemporal | MachineMemOperand :: MODereferenceable | MachineMemOperand :: MOInvariant ) ; InVals . push_back ( Arg ) ; MFI -> setABIArgOffset ( Offset + MemVT . getStoreSize ( ) ) ; } return Chain ; } </s>

This hook must be implemented to lower the incoming ( formal ) arguments , described by the Ins array , into the specified DAG .


<s> void DLXFrameLowering :: emitEpilogue ( MachineFunction & , MachineBasicBlock & MBB ) const { } </s>


<s> bool AMDGPUPassConfig :: addPreRegAlloc ( ) { const AMDGPUSubtarget & ST = TM -> getSubtarget < AMDGPUSubtarget > ( ) ; if ( ST . device ( ) -> getGeneration ( ) > AMDGPUDeviceInfo :: HD6XXX ) { addPass ( createSIAssignInterpRegsPass ( * TM ) ) ; } addPass ( createAMDGPUConvertToISAPass ( * TM ) ) ; return false ; } </s>

This method may be implemented by targets that want to run passes immediately before register allocation .


<s> int visium_epilogue_uses ( int regno ) { if ( regno == LINK_REGNUM ) return 1 ; if ( reload_completed ) { enum reg_type reg_type = GET_REG_TYPE ( regno ) ; int mask_bit = 1 << ( regno - first_regno [ reg_type ] ) ; return ( current_frame_info . mask [ reg_type ] & mask_bit ) != 0 ; } return 0 ; } </s>

For an interrupt handler , we may be saving call-clobbered registers . Say the epilogue uses these in addition to the link register .


<s> bool MBlazeAsmParser :: ParseDirective ( AsmToken DirectiveID ) { StringRef IDVal = DirectiveID . getIdentifier ( ) ; if ( IDVal == ".word" ) return ParseDirectiveWord ( 2 , DirectiveID . getLoc ( ) ) ; return true ; } </s>

ParseDirective - Parse a target specific assembler directive This method is deprecated , use 'parseDirective ' instead .


<s> static bool crx_return_in_memory ( tree type , tree fntype ATTRIBUTE_UNUSED ) { if ( TYPE_MODE ( type ) == BLKmode ) { HOST_WIDE_INT size = int_size_in_bytes ( type ) ; return ( size == - 1 || size > 8 ) ; } else return false ; } </s>

Implements hook TARGET_RETURN_IN_MEMORY .


<s> FastISel * PPC :: createFastISel ( FunctionLoweringInfo & FuncInfo , const TargetLibraryInfo * LibInfo ) { const PPCSubtarget & Subtarget = FuncInfo . MF -> getSubtarget < PPCSubtarget > ( ) ; if ( Subtarget . is64BitELFABI ( ) ) return new PPCFastISel ( FuncInfo , LibInfo ) ; return nullptr ; } </s>

This method returns a target specific FastISel object , or null if the target does not support `` fast '' ISel .


"Only FP0 could be passed as an argument"

runOnMachineFunction - Emit the function body .


<s>
void
PPCInstPrinter
::
printInst
(
const
MCInst
*
MI
,
raw_ostream
&
O
)
{
if
(
MI
->
getOpcode
(
)
==
PPC
::
RLWINM
)
{
unsigned
char
SH
=
MI
->
getOperand
(
2
)
.
getImm
(
)
;
unsigned
char
MB
=
MI
->
getOperand
(
3
)
.
getImm
(
)
;
unsigned
char
ME
=
MI
->
getOperand
(
4
)
.
getImm
(
)
;
bool
useSubstituteMnemonic
=
false
;
if
(
SH
<=
31
&&
MB
==
0
&&
ME
==
(
31
SH
)
)
{
O
<<
"\tslwi "
;
useSubstituteMnemonic
=
true
;
}
if
(
SH
<=
31
&&
MB
==
(
32
SH
)
&&
ME
==
31
)
{
O
<<
"\tsrwi "
;
useSubstituteMnemonic
=
true
;
SH
=
32
SH
;
}
if
(
useSubstituteMnemonic
)
{
printOperand
(
MI
,
0
,
O
)
;
O
<<
", "
;
printOperand
(
MI
,
1
,
O
)
;
O
<<
", "
<<
(
unsigned
int
)
SH
;
return
;
}
}
if
(
(
MI
->
getOpcode
(
)
==
PPC
::
OR
||
MI
->
getOpcode
(
)
==
PPC
::
OR8
)
&&
MI
->
getOperand
(
1
)
.
getReg
(
)
==
MI
->
getOperand
(
2
)
.
getReg
(
)
)
{
O
<<
"\tmr "
;
printOperand
(
MI
,
0
,
O
)
;
O
<<
", "
;
printOperand
(
MI
,
1
,
O
)
;
return
;
}
if
(
MI
->
getOpcode
(
)
==
PPC
::
RLDICR
)
{
unsigned
char
SH
=
MI
->
getOperand
(
2
)
.
getImm
(
)
;
unsigned
char
ME
=
MI
->
getOperand
(
3
)
.
getImm
(
)
;
if
(
63
SH
==
ME
)
{
O
<<
"\tsldi "
;
printOperand
(
MI
,
0
,
O
)
;
O
<<
", "
;
printOperand
(
MI
,
1
,
O
)
;
O
<<
", "
<<
(
unsigned
int
)
SH
;
return
;
}
}
printInstruction
(
MI
,
O
)
;
}
</s>

Print the specified MCInst to the specified raw_ostream .


<s> MCELFStreamer & getStreamer ( ) { return static_cast < MCELFStreamer & > ( Streamer ) ; } </s>

Return the output streamer for the assembler .


<s> registered_function & function_builder :: add_function ( const function_instance & instance , const char * name , tree fntype , tree attrs , aarch64_feature_flags required_extensions , bool overloaded_p , bool placeholder_p ) { unsigned int code = vec_safe_length ( registered_functions ) ; code = ( code << AARCH64_BUILTIN_SHIFT ) | AARCH64_BUILTIN_SVE ; tree decl = placeholder_p ? integer_zero_node : simulate_builtin_function_decl ( input_location , name , fntype , code , NULL , attrs ) ; registered_function & rfn = * ggc_alloc < registered_function > ( ) ; rfn . instance = instance ; rfn . decl = decl ; rfn . required_extensions = required_extensions ; rfn . overloaded_p = overloaded_p ; vec_safe_push ( registered_functions , & rfn ) ; return rfn ; } </s>

Add a function called NAME with type FNTYPE and attributes ATTRS . INSTANCE describes what the function does .


<s> bool AMDGPUAtomicOptimizer :: runOnFunction ( Function & F ) { if ( skipFunction ( F ) ) { return false ; } DA = & getAnalysis < LegacyDivergenceAnalysis > ( ) ; DL = & F . getParent ( ) -> getDataLayout ( ) ; DominatorTreeWrapperPass * const DTW = getAnalysisIfAvailable < DominatorTreeWrapperPass > ( ) ; DT = DTW ? & DTW -> getDomTree ( ) : nullptr ; const TargetPassConfig & TPC = getAnalysis < TargetPassConfig > ( ) ; const TargetMachine & TM = TPC . getTM < TargetMachine > ( ) ; ST = & TM . getSubtarget < GCNSubtarget > ( F ) ; IsPixelShader = F . getCallingConv ( ) == CallingConv :: AMDGPU_PS ; visit ( F ) ; const bool Changed = ! ToReplace . empty ( ) ; for ( ReplacementInfo & Info : ToReplace ) { optimizeAtomic ( * Info . I , Info . Op , Info . ValIdx , Info . ValDivergent ) ; } ToReplace . clear ( ) ; return Changed ; } </s>

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .


<s> virtual const IA64RegisterInfo * getRegisterInfo ( ) const { return & InstrInfo . getRegisterInfo ( ) ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


"LowerFormalArguments Unhandled argument type: "

"LowerFormalArguments unhandled argument type: "


<s> bool FixFunctionBitcasts :: runOnModule ( Module & M ) { SmallVector < std :: pair < Use * , Function * > , 0 > Uses ; SmallPtrSet < Constant * , 2 > ConstantBCs ; for ( Function & F : M ) FindUses ( & F , F , Uses , ConstantBCs ) ; DenseMap < std :: pair < Function * , FunctionType * > , Function * > Wrappers ; for ( auto & UseFunc : Uses ) { Use * U = UseFunc . first ; Function * F = UseFunc . second ; PointerType * PTy = cast < PointerType > ( U -> get ( ) -> getType ( ) ) ; FunctionType * Ty = dyn_cast < FunctionType > ( PTy -> getElementType ( ) ) ; if ( ! Ty ) continue ; auto Pair = Wrappers . insert ( std :: make_pair ( std :: make_pair ( F , Ty ) , nullptr ) ) ; if ( Pair . second ) Pair . first -> second = CreateWrapper ( F , Ty ) ; Function * Wrapper = Pair . first -> second ; if ( ! Wrapper ) continue ; if ( isa < Constant > ( U -> get ( ) ) ) U -> get ( ) -> replaceAllUsesWith ( Wrapper ) ; else U -> set ( Wrapper ) ; } return true ; } </s>

runOnModule - Virtual method overriden by subclasses to process the module being operated on .


<s> int expand_a_rotate ( rtx operands [ ] ) { rtx dst = operands [ 0 ] ; rtx src = operands [ 1 ] ; rtx rotate_amount = operands [ 2 ] ; machine_mode mode = GET_MODE ( dst ) ; if ( h8sx_classify_shift ( mode , ROTATE , rotate_amount ) == H8SX_SHIFT_UNARY ) return false ; emit_move_insn ( dst , src ) ; if ( GET_CODE ( rotate_amount ) != CONST_INT ) { rtx counter = gen_reg_rtx ( QImode ) ; rtx_code_label * start_label = gen_label_rtx ( ) ; rtx_code_label * end_label = gen_label_rtx ( ) ; emit_cmp_and_jump_insns ( rotate_amount , const0_rtx , LE , NULL_RTX , QImode , 0 , end_label ) ; emit_move_insn ( counter , rotate_amount ) ; emit_label ( start_label ) ; switch ( mode ) { case E_QImode : emit_insn ( gen_rotlqi3_1 ( dst , dst , const1_rtx ) ) ; break ; case E_HImode : emit_insn ( gen_rotlhi3_1 ( dst , dst , const1_rtx ) ) ; break ; case E_SImode : emit_insn ( gen_rotlsi3_1 ( dst , dst , const1_rtx ) ) ; break ; default : gcc_unreachable ( ) ; } emit_insn ( gen_addqi3 ( counter , counter , constm1_rtx ) ) ; emit_cmp_and_jump_insns ( counter , const0_rtx , NE , NULL_RTX , QImode , 1 , start_label ) ; emit_label ( end_label ) ; } else { switch ( mode ) { case E_QImode : emit_insn ( gen_rotlqi3_1 ( dst , dst , rotate_amount ) ) ; break ; case E_HImode : emit_insn ( gen_rotlhi3_1 ( dst , dst , rotate_amount ) ) ; break ; case E_SImode : emit_insn ( gen_rotlsi3_1 ( dst , dst , rotate_amount ) ) ; break ; default : gcc_unreachable ( ) ; } } return 1 ; } </s>

A rotation by a non-constant will cause a loop to be generated , in which a rotation by one bit is used . A rotation by a constant , including the one in the loop , will be taken care of by emit_a_rotate ( ) at the insn emit time .


<s> int m32r_hard_regno_rename_ok ( unsigned int old_reg ATTRIBUTE_UNUSED , unsigned int new_reg ) { if ( lookup_attribute ( "interrupt" , DECL_ATTRIBUTES ( current_function_decl ) ) && ! regs_ever_live [ new_reg ] ) return 0 ; if ( current_function_is_leaf && new_reg == RETURN_ADDR_REGNUM ) return 0 ; return 1 ; } </s>

Return true if using NEW_REG in place of OLD_REG is ok .


<s> OperandMatchResultTy tryParseRegister ( OperandVector & Operands ) { unsigned RegNo = 0 ; SMLoc S = getLexer ( ) . getLoc ( ) ; SMLoc E = getLexer ( ) . getTok ( ) . getEndLoc ( ) ; if ( tryParseRegister ( RegNo , S , E ) == MatchOperand_Success ) { Operands . push_back ( MOSOperand :: createReg ( RegNo , S , E ) ) ; return MatchOperand_Success ; } return MatchOperand_NoMatch ; } </s>

tryParseRegister - parse one register if possible


<s>
static
void
write_shared_buffer
(
FILE
*
file
,
rtx
sym
,
unsigned
align
,
unsigned
size
)
{
const
char
*
name
=
XSTR
(
sym
,
0
)
;
write_var_marker
(
file
,
true
,
false
,
name
)
;
fprintf
(
file
,
".shared .align %d .u8 %s[%d];\n"
,
align
,
name
,
size
)
;
}
</s>

Emit a declaration for a worker and vector-level buffer in .shared memory .

nvptx
0
".shared .align %d .u8 %s[%d];\n"


<s> static int power10_sched_reorder ( rtx_insn * * ready , int lastpos ) { rtx mem1 ; if ( ! reload_completed ) return cached_can_issue_more ; if ( load_store_pendulum != 0 ) { load_store_pendulum = 0 ; return cached_can_issue_more ; } if ( TARGET_P10_FUSION && is_fusable_store ( last_scheduled_insn , & mem1 ) ) { int pos = lastpos ; while ( pos >= 0 ) { rtx mem2 ; if ( is_fusable_store ( ready [ pos ] , & mem2 ) && ( ( INTEGRAL_MODE_P ( GET_MODE ( mem1 ) ) && adjacent_mem_locations ( mem1 , mem2 ) ) || ( FLOAT_MODE_P ( GET_MODE ( mem1 ) ) && ( adjacent_mem_locations ( mem1 , mem2 ) == mem1 ) ) ) ) { move_to_end_of_ready ( ready , pos , lastpos ) ; load_store_pendulum = - 1 ; break ; } pos -- ; } } return cached_can_issue_more ; } </s>

Do Power10 specific reordering of the ready list .


<s> bool VEInstrInfo :: reverseBranchCondition ( SmallVectorImpl < MachineOperand > & Cond ) const { VECC :: CondCodes CC = static_cast < VECC :: CondCodes > ( Cond [ 0 ] . getImm ( ) ) ; Cond [ 0 ] . setImm ( GetOppositeBranchCondition ( CC ) ) ; return false ; } </s>

Reverses the branch condition of the specified condition list , returning false on success and true if it can not be reversed .

VE VE VECC::CondCodes VECC::CondCodes 0 0


<s> static void frame_related_constant_load ( rtx reg , HOST_WIDE_INT constant , bool related ) { rtx_insn * insn ; rtx cst = GEN_INT ( constant ) ; if ( constant >= - 32768 && constant < 65536 ) insn = emit_move_insn ( reg , cst ) ; else { insn = emit_insn ( gen_movsi_high ( reg , cst ) ) ; if ( related ) RTX_FRAME_RELATED_P ( insn ) = 1 ; insn = emit_insn ( gen_movsi_low ( reg , reg , cst ) ) ; } if ( related ) RTX_FRAME_RELATED_P ( insn ) = 1 ; } </s>

Emit code to load a constant CONSTANT into register REG ; setting RTX_FRAME_RELATED_P on all insns we generate if RELATED is true . Make sure that the insns we generate need not be split .


<s> bool MipsBranchExpansion :: runOnMachineFunction ( MachineFunction & MF ) { const TargetMachine & TM = MF . getTarget ( ) ; IsPIC = TM . isPositionIndependent ( ) ; ABI = static_cast < const MipsTargetMachine & > ( TM ) . getABI ( ) ; STI = & MF . getSubtarget < MipsSubtarget > ( ) ; TII = static_cast < const MipsInstrInfo * > ( STI -> getInstrInfo ( ) ) ; if ( IsPIC && ABI . IsO32 ( ) && MF . getInfo < MipsFunctionInfo > ( ) -> globalBaseRegSet ( ) ) emitGPDisp ( MF , TII ) ; MFp = & MF ; ForceLongBranchFirstPass = ForceLongBranch ; bool longBranchChanged = handlePossibleLongBranch ( ) ; bool forbiddenSlotChanged = handleForbiddenSlot ( ) ; bool fpuDelaySlotChanged = handleFPUDelaySlot ( ) ; bool loadDelaySlotChanged = handleLoadDelaySlot ( ) ; bool Changed = longBranchChanged || forbiddenSlotChanged || fpuDelaySlotChanged || loadDelaySlotChanged ; while ( forbiddenSlotChanged ) { longBranchChanged = handlePossibleLongBranch ( ) ; fpuDelaySlotChanged = handleFPUDelaySlot ( ) ; loadDelaySlotChanged = handleLoadDelaySlot ( ) ; if ( ! longBranchChanged && ! fpuDelaySlotChanged && ! loadDelaySlotChanged ) break ; forbiddenSlotChanged = handleForbiddenSlot ( ) ; } return Changed ; } </s>


<s> static bool v850_legitimate_constant_p ( machine_mode mode ATTRIBUTE_UNUSED , rtx x ) { return ( GET_CODE ( x ) == CONST_DOUBLE || ! ( GET_CODE ( x ) == CONST && GET_CODE ( XEXP ( x , 0 ) ) == PLUS && GET_CODE ( XEXP ( XEXP ( x , 0 ) , 0 ) ) == SYMBOL_REF && GET_CODE ( XEXP ( XEXP ( x , 0 ) , 1 ) ) == CONST_INT && ! CONST_OK_FOR_K ( INTVAL ( XEXP ( XEXP ( x , 0 ) , 1 ) ) ) ) ) ; } </s>


<s> void ARMElfTargetObjectFile :: Initialize ( MCContext & Ctx , const TargetMachine & TM ) { bool isAAPCS_ABI = static_cast < const ARMTargetMachine & > ( TM ) . TargetABI == ARMTargetMachine :: ARMABI :: ARM_ABI_AAPCS ; TargetLoweringObjectFileELF :: Initialize ( Ctx , TM ) ; InitializeELF ( isAAPCS_ABI ) ; if ( isAAPCS_ABI ) { LSDASection = nullptr ; } AttributesSection = getContext ( ) . getELFSection ( ".ARM.attributes" , ELF :: SHT_ARM_ATTRIBUTES , 0 ) ; } </s>

This method must be called before any actual lowering is done .


<s> void Mips16FrameLowering :: emitPrologue ( MachineFunction & MF ) const { MachineBasicBlock & MBB = MF . front ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const Mips16InstrInfo & TII = * static_cast < const Mips16InstrInfo * > ( MF . getTarget ( ) . getInstrInfo ( ) ) ; MachineBasicBlock :: iterator MBBI = MBB . begin ( ) ; DebugLoc dl = MBBI != MBB . end ( ) ? MBBI -> getDebugLoc ( ) : DebugLoc ( ) ; uint64_t StackSize = MFI -> getStackSize ( ) ; if ( StackSize == 0 && ! MFI -> adjustsStack ( ) ) return ; MachineModuleInfo & MMI = MF . getMMI ( ) ; const MCRegisterInfo * MRI = MMI . getContext ( ) . getRegisterInfo ( ) ; MachineLocation DstML , SrcML ; TII . makeFrame ( Mips :: SP , StackSize , MBB , MBBI ) ; unsigned CFIIndex = MMI . addFrameInst ( MCCFIInstruction :: createDefCfaOffset ( nullptr , - StackSize ) ) ; BuildMI ( MBB , MBBI , dl , TII . get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; const std :: vector < CalleeSavedInfo > & CSI = MFI -> getCalleeSavedInfo ( ) ; if ( CSI . size ( ) ) { const std :: vector < CalleeSavedInfo > & CSI = MFI -> getCalleeSavedInfo ( ) ; for ( std :: vector < CalleeSavedInfo > :: const_iterator I = CSI . begin ( ) , E = CSI . end ( ) ; I != E ; ++ I ) { int64_t Offset = MFI -> getObjectOffset ( I -> getFrameIdx ( ) ) ; unsigned Reg = I -> getReg ( ) ; unsigned DReg = MRI -> getDwarfRegNum ( Reg , true ) ; unsigned CFIIndex = MMI . addFrameInst ( MCCFIInstruction :: createOffset ( nullptr , DReg , Offset ) ) ; BuildMI ( MBB , MBBI , dl , TII . get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; } } if ( hasFP ( MF ) ) BuildMI ( MBB , MBBI , dl , TII . get ( Mips :: MoveR3216 ) , Mips :: S0 ) . addReg ( Mips :: SP ) . setMIFlag ( MachineInstr :: FrameSetup ) ; } </s>

emitProlog/emitEpilog - These methods insert prolog and epilog code into the function .

Mips Mips Mips Mips 0 Mips::SP Mips::MoveR3216 Mips::S0 Mips::SP


<s> void sparc_expand_prologue ( void ) { HOST_WIDE_INT size ; rtx_insn * insn ; sparc_leaf_function_p = optimize > 0 && crtl -> is_leaf && only_leaf_regs_used ( ) ; size = sparc_compute_frame_size ( get_frame_size ( ) , sparc_leaf_function_p ) ; if ( flag_stack_usage_info ) current_function_static_stack_size = size ; if ( flag_stack_check == STATIC_BUILTIN_STACK_CHECK || flag_stack_clash_protection ) { if ( crtl -> is_leaf && ! cfun -> calls_alloca ) { if ( size > PROBE_INTERVAL && size > get_stack_check_protect ( ) ) sparc_emit_probe_stack_range ( get_stack_check_protect ( ) , size - get_stack_check_protect ( ) ) ; } else if ( size > 0 ) sparc_emit_probe_stack_range ( get_stack_check_protect ( ) , size ) ; } if ( size == 0 ) ; else if ( sparc_leaf_function_p ) { rtx size_int_rtx = GEN_INT ( - size ) ; if ( size <= 4096 ) insn = emit_insn ( gen_stack_pointer_inc ( size_int_rtx ) ) ; else if ( size <= 8192 ) { insn = emit_insn ( gen_stack_pointer_inc ( GEN_INT ( - 4096 ) ) ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; insn = emit_insn ( gen_stack_pointer_inc ( GEN_INT ( 4096 - size ) ) ) ; } else { rtx size_rtx = gen_rtx_REG ( Pmode , 1 ) ; emit_move_insn ( size_rtx , size_int_rtx ) ; insn = emit_insn ( gen_stack_pointer_inc ( size_rtx ) ) ; add_reg_note ( insn , REG_FRAME_RELATED_EXPR , gen_stack_pointer_inc ( size_int_rtx ) ) ; } RTX_FRAME_RELATED_P ( insn ) = 1 ; emit_insn ( gen_frame_blockage ( ) ) ; } else { rtx size_int_rtx = GEN_INT ( - size ) ; if ( size <= 4096 ) emit_window_save ( size_int_rtx ) ; else if ( size <= 8192 ) { emit_window_save ( GEN_INT ( - 4096 ) ) ; emit_insn ( gen_stack_pointer_inc ( GEN_INT ( 4096 - size ) ) ) ; emit_insn ( gen_frame_blockage ( ) ) ; } else { rtx size_rtx = gen_rtx_REG ( Pmode , 1 ) ; emit_move_insn ( size_rtx , size_int_rtx ) ; emit_window_save ( size_rtx ) ; } } if ( sparc_leaf_function_p ) { sparc_frame_base_reg = stack_pointer_rtx ; sparc_frame_base_offset = size + SPARC_STACK_BIAS ; } else { sparc_frame_base_reg = hard_frame_pointer_rtx ; sparc_frame_base_offset = SPARC_STACK_BIAS ; } if ( sparc_n_global_fp_regs > 0 ) emit_save_or_restore_global_fp_regs ( sparc_frame_base_reg , sparc_frame_base_offset - sparc_apparent_frame_size , SORR_SAVE ) ; sparc_prologue_data_valid_p = true ; } </s>

Expand the function prologue . The prologue is responsible for reserving storage for the frame , saving the call-saved registers and loading the PIC register if needed .


<s> int GCNTTIImpl :: getArithmeticReductionCost ( unsigned Opcode , Type * Ty , bool IsPairwise ) { EVT OrigTy = TLI -> getValueType ( DL , Ty ) ; if ( IsPairwise || ! ST -> hasVOP3PInsts ( ) || OrigTy . getScalarSizeInBits ( ) != 16 ) return BaseT :: getArithmeticReductionCost ( Opcode , Ty , IsPairwise ) ; std :: pair < int , MVT > LT = TLI -> getTypeLegalizationCost ( DL , Ty ) ; return LT . first * getFullRateInstrCost ( ) ; } </s>

Calculate the cost of vector reduction intrinsics .


<s> static rtx s390_function_and_libcall_value ( machine_mode mode , const_tree ret_type , const_tree fntype_or_decl , bool outgoing ATTRIBUTE_UNUSED ) { bool vector_ret_type_p = ( ( ret_type && VECTOR_TYPE_P ( ret_type ) ) || ( ! ret_type && VECTOR_MODE_P ( mode ) ) ) ; if ( ret_type ) { int unsignedp = TYPE_UNSIGNED ( ret_type ) ; mode = promote_function_mode ( ret_type , mode , & unsignedp , fntype_or_decl , 1 ) ; } gcc_assert ( GET_MODE_CLASS ( mode ) == MODE_INT || SCALAR_FLOAT_MODE_P ( mode ) || ( TARGET_VX_ABI && vector_ret_type_p ) ) ; gcc_assert ( GET_MODE_SIZE ( mode ) <= ( TARGET_VX_ABI ? 16 : 8 ) ) ; if ( TARGET_VX_ABI && vector_ret_type_p ) return gen_rtx_REG ( mode , FIRST_VEC_ARG_REGNO ) ; else if ( TARGET_HARD_FLOAT && SCALAR_FLOAT_MODE_P ( mode ) ) return gen_rtx_REG ( mode , 16 ) ; else if ( GET_MODE_SIZE ( mode ) <= UNITS_PER_LONG || UNITS_PER_LONG == UNITS_PER_WORD ) return gen_rtx_REG ( mode , 2 ) ; else if ( GET_MODE_SIZE ( mode ) == 2 * UNITS_PER_LONG ) { rtvec p = rtvec_alloc ( 2 ) ; RTVEC_ELT ( p , 0 ) = gen_rtx_EXPR_LIST ( SImode , gen_rtx_REG ( SImode , 2 ) , const0_rtx ) ; RTVEC_ELT ( p , 1 ) = gen_rtx_EXPR_LIST ( SImode , gen_rtx_REG ( SImode , 3 ) , GEN_INT ( 4 ) ) ; return gen_rtx_PARALLEL ( mode , p ) ; } gcc_unreachable ( ) ; } </s>

Define where to return a ( scalar ) value of type RET_TYPE . If RET_TYPE is null , define where to return a ( scalar ) value of mode MODE from a libcall .


<s> void clear ( ) { minimalCaps . clear ( ) ; allCaps . clear ( ) ; allExtensions . clear ( ) ; minVersion = 0 ; maxVersion = 0 ; } </s>


<s> void initializePass ( ) override { pushTTIStack ( this ) ; } </s>

initializePass - This method may be overriden by immutable passes to allow them to perform various initialization actions they require .


<s>
StringRef
getPassName
(
)
const
override
{
return
"WebAssembly MC Lower Pre Pass"
;
}
</s>

getPassName - Return a nice clean name for a pass .

WebAssembly
"WebAssembly MC Lower Pre Pass"


<s> static int s390_address_cost ( rtx addr ) { struct s390_address ad ; if ( ! s390_decompose_address ( addr , & ad ) ) return 1000 ; return ad . indx ? COSTS_N_INSNS ( 1 ) + 1 : COSTS_N_INSNS ( 1 ) ; } </s>

Return the cost of an address rtx ADDR .


<s> void BPFPassConfig :: addMachineSSAOptimization ( ) { addPass ( createBPFMISimplifyPatchablePass ( ) ) ; TargetPassConfig :: addMachineSSAOptimization ( ) ; const BPFSubtarget * Subtarget = getBPFTargetMachine ( ) . getSubtargetImpl ( ) ; if ( Subtarget -> getHasAlu32 ( ) && ! DisableMIPeephole ) addPass ( createBPFMIPeepholePass ( ) ) ; } </s>

Methods with trivial inline returns are convenient points in the common codegen pass pipeline where targets may insert passes .


<s> const char * output_probe_stack_range ( rtx reg1 , rtx reg2 , rtx reg3 ) { if ( flag_stack_clash_protection ) return output_probe_stack_range_stack_clash ( reg1 , reg2 , reg3 ) ; else return output_probe_stack_range_1 ( reg1 , reg3 ) ; } </s>

Wrapper around the output_probe_stack_range routines .