getTargetNodeName - This method returns the name of a target specific


<s> rtx riscv_legitimize_call_address ( rtx addr ) { if ( ! call_insn_operand ( addr , VOIDmode ) ) { rtx reg = RISCV_CALL_ADDRESS_TEMP ( Pmode ) ; riscv_emit_move ( reg , addr ) ; return reg ; } return addr ; } </s>

Make ADDR suitable for use as a call or sibcall target .


<s> unsigned VETargetLowering :: getMinimumJumpTableEntries ( ) const { if ( isJumpTableRelative ( ) ) return 8 ; return TargetLowering :: getMinimumJumpTableEntries ( ) ; } </s>


<s>
static
void
m68hc11_encode_section_info
(
tree
decl
,
rtx
rtl
,
int
first
ATTRIBUTE_UNUSED
)
{
tree
func_attr
;
int
trap_handler
;
int
is_far
=
0
;
if
(
TREE_CODE
(
decl
)
==
VAR_DECL
)
{
if
(
lookup_attribute
(
"page0"
,
DECL_ATTRIBUTES
(
decl
)
)
!=
0
)
m68hc11_encode_label
(
decl
)
;
return
;
}
if
(
TREE_CODE
(
decl
)
!=
FUNCTION_DECL
)
return
;
func_attr
=
TYPE_ATTRIBUTES
(
TREE_TYPE
(
decl
)
)
;
if
(
lookup_attribute
(
"far"
,
func_attr
)
!=
NULL_TREE
)
is_far
=
1
;
else
if
(
lookup_attribute
(
"near"
,
func_attr
)
==
NULL_TREE
)
is_far
=
TARGET_LONG_CALLS
!=
0
;
trap_handler
=
lookup_attribute
(
"trap"
,
func_attr
)
!=
NULL_TREE
;
if
(
trap_handler
&&
is_far
)
{
warning
(
OPT_Wattributes
,
"%<trap%> and %<far%> attributes are "
"not compatible, ignoring %<far%>"
)
;
trap_handler
=
0
;
}
if
(
trap_handler
)
{
if
(
trap_handler_symbol
!=
0
)
warning
(
OPT_Wattributes
,
"%<trap%> attribute is already used"
)
;
else
trap_handler_symbol
=
XEXP
(
rtl
,
0
)
;
}
SYMBOL_REF_FLAG
(
XEXP
(
rtl
,
0
)
)
=
is_far
;
}
</s>

We want to recognize trap handlers so that we handle calls to traps in a special manner ( by issuing the trap ) . This information is stored in SYMBOL_REF_FLAG .


<s> static tree xstormy16_build_builtin_va_list ( void ) { tree f_1 , f_2 , record , type_decl ; record = ( * lang_hooks . types . make_type ) ( RECORD_TYPE ) ; type_decl = build_decl ( BUILTINS_LOCATION , TYPE_DECL , get_identifier ( "__va_list_tag" ) , record ) ; f_1 = build_decl ( BUILTINS_LOCATION , FIELD_DECL , get_identifier ( "base" ) , ptr_type_node ) ; f_2 = build_decl ( BUILTINS_LOCATION , FIELD_DECL , get_identifier ( "count" ) , unsigned_type_node ) ; DECL_FIELD_CONTEXT ( f_1 ) = record ; DECL_FIELD_CONTEXT ( f_2 ) = record ; TYPE_STUB_DECL ( record ) = type_decl ; TYPE_NAME ( record ) = type_decl ; TYPE_FIELDS ( record ) = f_1 ; DECL_CHAIN ( f_1 ) = f_2 ; layout_type ( record ) ; return record ; } </s>

Build the va_list type . For this chip , va_list is a record containing a counter and a pointer . The counter is of type 'int ' and indicates how many bytes have been used to date . The pointer indicates the stack position for arguments that have not been passed in registers . To keep the layout nice , the pointer is first in the structure .


"Do not know how to custom type legalize this operation!"

"Unexpected result type for CTR decrement intrinsic"

ReplaceNodeResults - Replace the results of node with an illegal result type with new values built out of custom code .


<s>
void
XCoreTargetLowering
::
ReplaceNodeResults
(
SDNode
*
N
,
SmallVectorImpl
<
SDValue
>
&
Results
,
SelectionDAG
&
DAG
)
{
switch
(
N
->
getOpcode
(
)
)
{
default
:
llvm_unreachable
(
"Don't know how to custom expand this!"
)
;
return
;
case
ISD
::
ADD
:
case
ISD
::
SUB
:
Results
.
push_back
(
ExpandADDSUB
(
N
,
DAG
)
)
;
return
;
}
}
</s>

XCore
XCore
"Don't know how to custom expand this!"
ISD::ADD
ISD::SUB


<s> bool PPCFrameLowering :: spillCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo * TRI ) const { if ( ! Subtarget . isSVR4ABI ( ) ) return false ; MachineFunction * MF = MBB . getParent ( ) ; const PPCInstrInfo & TII = * static_cast < const PPCInstrInfo * > ( MF -> getTarget ( ) . getInstrInfo ( ) ) ; DebugLoc DL ; bool CRSpilled = false ; MachineInstrBuilder CRMIB ; for ( unsigned i = 0 , e = CSI . size ( ) ; i != e ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; if ( Reg == PPC :: VRSAVE && ! Subtarget . isDarwinABI ( ) ) continue ; bool IsCRField = PPC :: CR2 <= Reg && Reg <= PPC :: CR4 ; MBB . addLiveIn ( Reg ) ; if ( CRSpilled && IsCRField ) { CRMIB . addReg ( Reg , RegState :: ImplicitKill ) ; continue ; } if ( IsCRField ) { PPCFunctionInfo * FuncInfo = MF -> getInfo < PPCFunctionInfo > ( ) ; if ( Subtarget . isPPC64 ( ) ) { FuncInfo -> addMustSaveCR ( Reg ) ; } else { CRSpilled = true ; FuncInfo -> setSpillsCR ( ) ; CRMIB = BuildMI ( * MF , DL , TII . get ( PPC :: MFCR ) , PPC :: R12 ) . addReg ( Reg , RegState :: ImplicitKill ) ; MBB . insert ( MI , CRMIB ) ; MBB . insert ( MI , addFrameReference ( BuildMI ( * MF , DL , TII . get ( PPC :: STW ) ) . addReg ( PPC :: R12 , getKillRegState ( true ) ) , CSI [ i ] . getFrameIdx ( ) ) ) ; } } else { const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ; TII . storeRegToStackSlot ( MBB , MI , Reg , true , CSI [ i ] . getFrameIdx ( ) , RC , TRI ) ; } } return true ; } </s>

spillCalleeSavedRegisters - Issues instruction ( s ) to spill all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of store instructions via storeRegToStackSlot ( ) .

PowerPC PPC PPC PPC 0 PPC::VRSAVE PPC::CR2 PPC::CR4 PPC PPC PPC PPC::MFCR PPC::R12 PPC::STW PPC::R12


<s>
virtual
const
char
*
getPassName
(
)
const
{
return
"AArch64 Instruction Selection"
;
}
</s>

getPassName - Return a nice clean name for a pass .


"%qs declared as both exported to and imported from a DLL"

"failure in redeclaration of %q+D: dllimport'd symbol lacks external linkage"


<s> static bool save_reg_p ( int reg ) { if ( reg == RS6000_PIC_OFFSET_TABLE_REGNUM && ! TARGET_SINGLE_PIC_BASE ) { if ( TARGET_TOC && TARGET_MINIMAL_TOC && ( crtl -> calls_eh_return || df_regs_ever_live_p ( reg ) || ! constant_pool_empty_p ( ) ) ) return true ; if ( ( DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_DARWIN ) && flag_pic ) return true ; } return ! call_used_regs [ reg ] && df_regs_ever_live_p ( reg ) ; } </s>

Determine whether the REG is really used .


<s> static void visium_save_regs ( int alloc , int offset , int low_regno , int high_regno ) { const int volatile_p = current_frame_info . interrupt ; int regno ; emit_frame_insn ( gen_addsi3_flags ( stack_pointer_rtx , stack_pointer_rtx , GEN_INT ( - alloc ) ) ) ; for ( regno = low_regno ; regno <= high_regno ; regno ++ ) { enum reg_type reg_type = GET_REG_TYPE ( regno ) ; int mask_bit = 1 << ( regno - first_regno [ reg_type ] ) ; rtx insn ; if ( current_frame_info . mask [ reg_type ] & mask_bit ) { offset -= reg_type_size [ reg_type ] ; switch ( reg_type ) { case general : { rtx mem = gen_frame_mem ( SImode , plus_constant ( Pmode , stack_pointer_rtx , offset ) ) ; MEM_VOLATILE_P ( mem ) = volatile_p ; emit_frame_insn ( gen_movsi ( mem , gen_rtx_REG ( SImode , regno ) ) ) ; } break ; case mdb : { rtx tmp = gen_rtx_REG ( DImode , PROLOGUE_TMP_REGNUM ) ; rtx mem = gen_frame_mem ( DImode , plus_constant ( Pmode , stack_pointer_rtx , offset ) ) ; rtx reg = gen_rtx_REG ( DImode , regno ) ; MEM_VOLATILE_P ( mem ) = volatile_p ; emit_insn ( gen_movdi ( tmp , reg ) ) ; if ( volatile_p ) emit_insn ( gen_movdi ( mem , tmp ) ) ; else { insn = emit_frame_insn ( gen_movdi ( mem , tmp ) ) ; add_reg_note ( insn , REG_FRAME_RELATED_EXPR , gen_rtx_SET ( mem , reg ) ) ; } } break ; case mdc : { rtx tmp = gen_rtx_REG ( SImode , PROLOGUE_TMP_REGNUM ) ; rtx mem = gen_frame_mem ( SImode , plus_constant ( Pmode , stack_pointer_rtx , offset ) ) ; rtx reg = gen_rtx_REG ( SImode , regno ) ; MEM_VOLATILE_P ( mem ) = volatile_p ; emit_insn ( gen_movsi ( tmp , reg ) ) ; insn = emit_frame_insn ( gen_movsi ( mem , tmp ) ) ; add_reg_note ( insn , REG_FRAME_RELATED_EXPR , gen_rtx_SET ( mem , reg ) ) ; } break ; case floating : { rtx tmp = gen_rtx_REG ( SFmode , PROLOGUE_TMP_REGNUM ) ; rtx mem = gen_frame_mem ( SFmode , plus_constant ( Pmode , stack_pointer_rtx , offset ) ) ; rtx reg = gen_rtx_REG ( SFmode , regno ) ; MEM_VOLATILE_P ( mem ) = volatile_p ; emit_insn ( gen_movsf ( tmp , reg ) ) ; insn = emit_frame_insn ( gen_movsf ( mem , tmp ) ) ; add_reg_note ( insn , REG_FRAME_RELATED_EXPR , gen_rtx_SET ( mem , reg ) ) ; } break ; default : break ; } } } } </s>

Allocate ALLOC bytes on the stack and save the registers LOW_REGNO to HIGH_REGNO at OFFSET from the stack pointer .


<s> void setupMF ( MachineFunction & MF , GISelKnownBits & KB , CodeGenCoverage & CoverageInfo ) override { InstructionSelector :: setupMF ( MF , KB , CoverageInfo ) ; ProduceNonFlagSettingCondBr = ! MF . getFunction ( ) . hasFnAttribute ( Attribute :: SpeculativeLoadHardening ) ; processPHIs ( MF ) ; } </s>


"Hexagon optimize redundant zero and size extends"


<s> static void frv_frame_access_standard_regs ( enum frv_stack_op op , frv_stack_t * info ) { frv_frame_accessor_t accessor ; accessor . op = op ; accessor . base = stack_pointer_rtx ; accessor . base_offset = 0 ; frv_frame_access_multi ( & accessor , info , STACK_REGS_GPR ) ; frv_frame_access_multi ( & accessor , info , STACK_REGS_FPR ) ; frv_frame_access_multi ( & accessor , info , STACK_REGS_LCR ) ; } </s>

Save or restore callee-saved registers that are kept outside the frame header . The function saves the registers if OP is FRV_STORE and restores them if OP is FRV_LOAD . INFO is the stack information generated by frv_stack_info .


<s> unsigned MipsTargetLowering :: getJumpTableEncoding ( ) const { if ( Subtarget -> isABI_N64 ( ) ) return MachineJumpTableInfo :: EK_GPRel64BlockAddress ; return TargetLowering :: getJumpTableEncoding ( ) ; } </s>

Return the entry encoding for a jump table in the current function .


<s> rtx nvptx_expand_compare ( rtx compare ) { rtx pred = gen_reg_rtx ( BImode ) ; rtx cmp = gen_rtx_fmt_ee ( GET_CODE ( compare ) , BImode , XEXP ( compare , 0 ) , XEXP ( compare , 1 ) ) ; emit_insn ( gen_rtx_SET ( VOIDmode , pred , cmp ) ) ; return gen_rtx_NE ( BImode , pred , const0_rtx ) ; } </s>

Emit a comparison COMPARE , and return the new test to be used in the jump .


"argument to %qs must be a 2-bit unsigned literal"


<s> static void mips_expand_msa_cmp ( rtx dest , enum rtx_code cond , rtx op0 , rtx op1 ) { machine_mode cmp_mode = GET_MODE ( op0 ) ; int unspec = - 1 ; bool negate = false ; switch ( cmp_mode ) { case E_V16QImode : case E_V8HImode : case E_V4SImode : case E_V2DImode : switch ( cond ) { case NE : cond = reverse_condition ( cond ) ; negate = true ; break ; case EQ : case LT : case LE : case LTU : case LEU : break ; case GE : case GT : case GEU : case GTU : std :: swap ( op0 , op1 ) ; cond = swap_condition ( cond ) ; break ; default : gcc_unreachable ( ) ; } mips_emit_binary ( cond , dest , op0 , op1 ) ; if ( negate ) emit_move_insn ( dest , gen_rtx_NOT ( GET_MODE ( dest ) , dest ) ) ; break ; case E_V4SFmode : case E_V2DFmode : switch ( cond ) { case UNORDERED : case ORDERED : case EQ : case NE : case UNEQ : case UNLE : case UNLT : break ; case LTGT : cond = NE ; break ; case UNGE : cond = UNLE ; std :: swap ( op0 , op1 ) ; break ; case UNGT : cond = UNLT ; std :: swap ( op0 , op1 ) ; break ; case LE : unspec = UNSPEC_MSA_FSLE ; break ; case LT : unspec = UNSPEC_MSA_FSLT ; break ; case GE : unspec = UNSPEC_MSA_FSLE ; std :: swap ( op0 , op1 ) ; break ; case GT : unspec = UNSPEC_MSA_FSLT ; std :: swap ( op0 , op1 ) ; break ; default : gcc_unreachable ( ) ; } if ( unspec < 0 ) mips_emit_binary ( cond , dest , op0 , op1 ) ; else { rtx x = gen_rtx_UNSPEC ( GET_MODE ( dest ) , gen_rtvec ( 2 , op0 , op1 ) , unspec ) ; emit_insn ( gen_rtx_SET ( dest , x ) ) ; } break ; default : gcc_unreachable ( ) ; break ; } } </s>

Generate RTL for comparing CMP_OP0 and CMP_OP1 using condition COND and store the result -1 or 0 in DEST .


"AAAMDWorkGroupSize is only valid for function position"

Create an abstract attribute view for the position IRP .


<s> static int ia64_mode_to_int ( machine_mode mode ) { switch ( mode ) { case E_BImode : return 0 ; case E_QImode : return 1 ; case E_HImode : return 2 ; case E_SImode : return 3 ; case E_DImode : return 4 ; case E_SFmode : return 5 ; case E_DFmode : return 6 ; case E_XFmode : return 7 ; case E_TImode : return SPEC_MODE_INVALID ; default : return SPEC_MODE_INVALID ; } } </s>


<s>
bool
MipsCodeEmitter
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
JTI
=
(
(
MipsTargetMachine
&
)
MF
.
getTarget
(
)
)
.
getJITInfo
(
)
;
II
=
(
(
const
MipsTargetMachine
&
)
MF
.
getTarget
(
)
)
.
getInstrInfo
(
)
;
TD
=
(
(
const
MipsTargetMachine
&
)
MF
.
getTarget
(
)
)
.
getTargetData
(
)
;
Subtarget
=
&
TM
.
getSubtarget
<
MipsSubtarget
>
(
)
;
MCPEs
=
&
MF
.
getConstantPool
(
)
->
getConstants
(
)
;
MJTEs
=
0
;
if
(
MF
.
getJumpTableInfo
(
)
)
MJTEs
=
&
MF
.
getJumpTableInfo
(
)
->
getJumpTables
(
)
;
JTI
->
Initialize
(
MF
,
IsPIC
)
;
MCE
.
setModuleInfo
(
&
getAnalysis
<
MachineModuleInfo
>
(
)
)
;
do
{
DEBUG
(
errs
(
)
<<
"JITTing function '"
<<
MF
.
getFunction
(
)
->
getName
(
)
<<
"'\n"
)
;
MCE
.
startFunction
(
MF
)
;
for
(
MachineFunction
::
iterator
MBB
=
MF
.
begin
(
)
,
E
=
MF
.
end
(
)
;
MBB
!=
E
;
++
MBB
)
{
MCE
.
StartMachineBasicBlock
(
MBB
)
;
for
(
MachineBasicBlock
::
instr_iterator
I
=
MBB
->
instr_begin
(
)
,
E
=
MBB
->
instr_end
(
)
;
I
!=
E
;
++
I
)
emitInstruction
(
*
I
)
;
}
}
while
(
MCE
.
finishFunction
(
MF
)
)
;
return
false
;
}
</s>

runOnMachineFunction - Emit the function body .

Mips
Mips
Mips
Mips
Mips
Mips
0
"JITTing function '"
"'\n"


<s> bool X86TargetLowering :: getSafeStackPointerLocation ( unsigned & AddressSpace , unsigned & Offset ) const { if ( ! Subtarget -> isTargetAndroid ( ) ) return false ; if ( Subtarget -> is64Bit ( ) ) { Offset = 0x48 ; if ( getTargetMachine ( ) . getCodeModel ( ) == CodeModel :: Kernel ) AddressSpace = 256 ; else AddressSpace = 257 ; } else { Offset = 0x24 ; AddressSpace = 256 ; } return true ; } </s>

Return true if the target stores SafeStack pointer at a fixed offset in some non-standard address space , and populates the address space and offset as appropriate .


"Unexpected instruction type for reassociation"

"Must have dead EFLAGS operand in reassociable instruction"

"Unexpected operand in reassociable instruction"

This is an architecture-specific helper function of reassociateOps .


<s> void WebAssemblyFrameLowering :: emitPrologue ( MachineFunction & MF , MachineBasicBlock & MBB ) const { } </s>

emitProlog/emitEpilog - These methods insert prolog and epilog code into the function .


<s> static HOST_WIDE_INT cris_preferred_mininum_alignment ( void ) { if ( ! TARGET_CONST_ALIGN ) return 8 ; if ( TARGET_ALIGN_BY_32 ) return 32 ; return 16 ; } </s>

Return the preferred minimum alignment for a static object .


<s> bool AMDGPUAsmParser :: ParseDirective ( AsmToken DirectiveID ) { StringRef IDVal = DirectiveID . getString ( ) ; if ( IDVal == ".hsa_code_object_version" ) return ParseDirectiveHSACodeObjectVersion ( ) ; if ( IDVal == ".hsa_code_object_isa" ) return ParseDirectiveHSACodeObjectISA ( ) ; if ( IDVal == ".amd_kernel_code_t" ) return ParseDirectiveAMDKernelCodeT ( ) ; if ( IDVal == ".hsatext" || IDVal == ".text" ) return ParseSectionDirectiveHSAText ( ) ; if ( IDVal == ".amdgpu_hsa_kernel" ) return ParseDirectiveAMDGPUHsaKernel ( ) ; return true ; } </s>

ParseDirective - Parse a target specific assembler directive This method is deprecated , use 'parseDirective ' instead .


<s> static int ix86_agi_dependant ( rtx insn , rtx dep_insn , enum attr_type insn_type ) { rtx addr ; if ( insn_type == TYPE_LEA && TARGET_PENTIUM ) { addr = PATTERN ( insn ) ; if ( GET_CODE ( addr ) == PARALLEL ) addr = XVECEXP ( addr , 0 , 0 ) ; gcc_assert ( GET_CODE ( addr ) == SET ) ; addr = SET_SRC ( addr ) ; } else { int i ; extract_insn_cached ( insn ) ; for ( i = recog_data . n_operands - 1 ; i >= 0 ; -- i ) if ( GET_CODE ( recog_data . operand [ i ] ) == MEM ) { addr = XEXP ( recog_data . operand [ i ] , 0 ) ; goto found ; } return 0 ; found : ; } return modified_in_p ( addr , dep_insn ) ; } </s>

A subroutine of ix86_adjust_cost -- return true iff INSN has a memory address with operands set by DEP_INSN .


<s> static int alpha_register_move_cost ( machine_mode , reg_class_t from , reg_class_t to ) { if ( ( from == FLOAT_REGS ) == ( to == FLOAT_REGS ) ) return 2 ; if ( TARGET_FIX ) return ( from == FLOAT_REGS ) ? 6 : 8 ; return 4 + 2 * alpha_memory_latency ; } </s>

Return the cost of moving between registers of various classes . Moving between FLOAT_REGS and anything else except float regs is expensive . In fact , we make it quite expensive because we really do n't want to do these moves unless it is clearly worth it . Optimizations may reduce the impact of not being able to allocate a pseudo to a hard register .


Create an WebAssembly architecture model .


<s> void connect ( Node & n , SPScope :: Edge e ) { outedges [ & n ] = e ; connect ( n ) ; } </s>

Assuming nodes Src and Dst are already in the graph , connect node Src to node Dst using the provided edge E .


<s>
bool
PPCInstrInfo
::
FoldImmediate
(
MachineInstr
&
UseMI
,
MachineInstr
&
DefMI
,
unsigned
Reg
,
MachineRegisterInfo
*
MRI
)
const
{
unsigned
DefOpc
=
DefMI
.
getOpcode
(
)
;
if
(
DefOpc
!=
PPC
::
LI
&&
DefOpc
!=
PPC
::
LI8
)
return
false
;
if
(
!
DefMI
.
getOperand
(
1
)
.
isImm
(
)
)
return
false
;
if
(
DefMI
.
getOperand
(
1
)
.
getImm
(
)
!=
0
)
return
false
;
const
MCInstrDesc
&
UseMCID
=
UseMI
.
getDesc
(
)
;
if
(
UseMCID
.
isPseudo
(
)
)
return
false
;
unsigned
UseIdx
;
for
(
UseIdx
=
0
;
UseIdx
<
UseMI
.
getNumOperands
(
)
;
++
UseIdx
)
if
(
UseMI
.
getOperand
(
UseIdx
)
.
isReg
(
)
&&
UseMI
.
getOperand
(
UseIdx
)
.
getReg
(
)
==
Reg
)
break
;
assert
(
UseIdx
<
UseMI
.
getNumOperands
(
)
&&
"Cannot find Reg in UseMI"
)
;
assert
(
UseIdx
<
UseMCID
.
getNumOperands
(
)
&&
"No operand description for Reg"
)
;
const
MCOperandInfo
*
UseInfo
=
&
UseMCID
.
OpInfo
[
UseIdx
]
;
if
(
UseInfo
->
isLookupPtrRegClass
(
)
)
{
if
(
UseInfo
->
RegClass
!=
1
)
return
false
;
}
else
{
if
(
UseInfo
->
RegClass
!=
PPC
::
GPRC_NOR0RegClassID
&&
UseInfo
->
RegClass
!=
PPC
::
G8RC_NOX0RegClassID
)
return
false
;
}
if
(
UseInfo
->
Constraints
!=
0
)
return
false
;
unsigned
ZeroReg
;
if
(
UseInfo
->
isLookupPtrRegClass
(
)
)
{
bool
isPPC64
=
Subtarget
.
isPPC64
(
)
;
ZeroReg
=
isPPC64
PPC
::
ZERO8
:
PPC
::
ZERO
;
}
else
{
ZeroReg
=
UseInfo
->
RegClass
==
PPC
::
G8RC_NOX0RegClassID
PPC
::
ZERO8
:
PPC
::
ZERO
;
}
bool
DeleteDef
=
MRI
->
hasOneNonDBGUse
(
Reg
)
;
UseMI
.
getOperand
(
UseIdx
)
.
setReg
(
ZeroReg
)
;
if
(
DeleteDef
)
DefMI
.
eraseFromParent
(
)
;
return
true
;
}
</s>

Reg is known to be defined by a move immediate instruction , try to fold the immediate into the use instruction .


<s> unsigned int rs6000_special_adjust_field_align ( tree type , unsigned int computed ) { if ( computed <= 32 || TYPE_PACKED ( type ) ) return computed ; while ( TREE_CODE ( type ) == ARRAY_TYPE ) type = TREE_TYPE ( type ) ; while ( AGGREGATE_TYPE_P ( type ) ) { tree field = TYPE_FIELDS ( type ) ; while ( field != NULL && ( TREE_CODE ( field ) != FIELD_DECL || DECL_FIELD_ABI_IGNORED ( field ) ) ) field = DECL_CHAIN ( field ) ; if ( ! field ) break ; if ( DECL_PACKED ( field ) ) return computed ; type = TREE_TYPE ( field ) ; while ( TREE_CODE ( type ) == ARRAY_TYPE ) type = TREE_TYPE ( type ) ; } if ( ! AGGREGATE_TYPE_P ( type ) && type != error_mark_node && ( TYPE_MODE ( type ) == DFmode || TYPE_MODE ( type ) == DCmode ) ) computed = MIN ( computed , 32 ) ; return computed ; } </s>

AIX word-aligns FP doubles but doubleword-aligns 64-bit ints .


<s> static int arc_save_callee_enter ( uint64_t gmask , bool save_blink , bool save_fp , HOST_WIDE_INT offset ) { int start_reg = ENTER_LEAVE_START_REG ; int end_reg = ENTER_LEAVE_END_REG ; int regno , indx , off , nregs ; rtx insn , reg , mem ; int frame_allocated = 0 ; for ( regno = start_reg ; regno <= end_reg && ( gmask & ( 1ULL << regno ) ) ; ) regno ++ ; end_reg = regno - 1 ; nregs = end_reg - start_reg + 1 ; nregs += save_blink ? 1 : 0 ; nregs += save_fp ? 1 : 0 ; if ( offset ) frame_stack_add ( offset ) ; insn = gen_rtx_PARALLEL ( VOIDmode , rtvec_alloc ( nregs + ( save_fp ? 1 : 0 ) + 1 ) ) ; indx = 0 ; reg = gen_rtx_SET ( stack_pointer_rtx , plus_constant ( Pmode , stack_pointer_rtx , - nregs * UNITS_PER_WORD ) ) ; RTX_FRAME_RELATED_P ( reg ) = 1 ; XVECEXP ( insn , 0 , indx ++ ) = reg ; off = nregs * UNITS_PER_WORD ; if ( save_blink ) { reg = gen_rtx_REG ( Pmode , RETURN_ADDR_REGNUM ) ; mem = gen_frame_mem ( Pmode , plus_constant ( Pmode , stack_pointer_rtx , - off ) ) ; XVECEXP ( insn , 0 , indx ) = gen_rtx_SET ( mem , reg ) ; RTX_FRAME_RELATED_P ( XVECEXP ( insn , 0 , indx ++ ) ) = 1 ; off -= UNITS_PER_WORD ; save_blink = false ; } for ( regno = start_reg ; regno <= end_reg ; regno ++ , indx ++ , off -= UNITS_PER_WORD ) { reg = gen_rtx_REG ( SImode , regno ) ; mem = gen_frame_mem ( SImode , plus_constant ( Pmode , stack_pointer_rtx , - off ) ) ; XVECEXP ( insn , 0 , indx ) = gen_rtx_SET ( mem , reg ) ; RTX_FRAME_RELATED_P ( XVECEXP ( insn , 0 , indx ) ) = 1 ; gmask = gmask & ~ ( 1ULL << regno ) ; } if ( save_fp ) { mem = gen_frame_mem ( Pmode , plus_constant ( Pmode , stack_pointer_rtx , - off ) ) ; XVECEXP ( insn , 0 , indx ) = gen_rtx_SET ( mem , hard_frame_pointer_rtx ) ; RTX_FRAME_RELATED_P ( XVECEXP ( insn , 0 , indx ++ ) ) = 1 ; off -= UNITS_PER_WORD ; XVECEXP ( insn , 0 , indx ) = gen_rtx_SET ( hard_frame_pointer_rtx , stack_pointer_rtx ) ; RTX_FRAME_RELATED_P ( XVECEXP ( insn , 0 , indx ++ ) ) = 1 ; save_fp = false ; } gcc_assert ( off == 0 ) ; insn = frame_insn ( insn ) ; add_reg_note ( insn , REG_INC , stack_pointer_rtx ) ; frame_allocated = nregs * UNITS_PER_WORD ; return frame_allocated - offset ; } </s>

ARC prologue , save the registers using enter instruction . Leave instruction can also save $ blink ( SAVE_BLINK ) and $ fp ( SAVE_FP ) register .


Return true if globals in this address space can have initializers other than undef .


<s> DFAPacketizer * PatmosInstrInfo :: CreateTargetScheduleState ( const TargetMachine * TM , const ScheduleDAG * DAG ) const { const InstrItineraryData * II = TM -> getInstrItineraryData ( ) ; return TM -> getSubtarget < PatmosGenSubtargetInfo > ( ) . createDFAPacketizer ( II ) ; } </s>

Create machine specific model for scheduling .


<s> void RISCVFrameLowering :: determineFrameLayout ( MachineFunction & MF ) const { MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const RISCVRegisterInfo * RI = STI . getRegisterInfo ( ) ; uint64_t FrameSize = MFI . getStackSize ( ) ; uint64_t StackAlign = RI -> needsStackRealignment ( MF ) ? MFI . getMaxAlignment ( ) : getStackAlignment ( ) ; uint64_t MaxCallFrameSize = MFI . getMaxCallFrameSize ( ) ; if ( MFI . hasVarSizedObjects ( ) ) MaxCallFrameSize = alignTo ( MaxCallFrameSize , StackAlign ) ; MFI . setMaxCallFrameSize ( MaxCallFrameSize ) ; if ( ! ( hasReservedCallFrame ( MF ) && MFI . adjustsStack ( ) ) ) FrameSize += MaxCallFrameSize ; FrameSize = alignTo ( FrameSize , StackAlign ) ; MFI . setStackSize ( FrameSize ) ; } </s>

Determine the frame layout but do not update the machine function .


<s> static bool msp430_special_register_convention_p ( const char * name ) { int i ; for ( i = 0 ; special_convention_function_names [ i ] ; i ++ ) if ( ! strcmp ( name , special_convention_function_names [ i ] ) ) return true ; return false ; } </s>

TRUE if the function passed is a `` speical '' function . Special functions pass two DImode parameters in registers .


<s> void RISCVTargetStreamer :: emitTargetAttributes ( const MCSubtargetInfo & STI ) { if ( STI . hasFeature ( RISCV :: FeatureRV32E ) ) emitAttribute ( RISCVAttrs :: STACK_ALIGN , RISCVAttrs :: ALIGN_4 ) ; else emitAttribute ( RISCVAttrs :: STACK_ALIGN , RISCVAttrs :: ALIGN_16 ) ; std :: string Arch = "rv32" ; if ( STI . hasFeature ( RISCV :: Feature64Bit ) ) Arch = "rv64" ; if ( STI . hasFeature ( RISCV :: FeatureRV32E ) ) Arch += "e1p9" ; else Arch += "i2p0" ; if ( STI . hasFeature ( RISCV :: FeatureStdExtM ) ) Arch += "_m2p0" ; if ( STI . hasFeature ( RISCV :: FeatureStdExtA ) ) Arch += "_a2p0" ; if ( STI . hasFeature ( RISCV :: FeatureStdExtF ) ) Arch += "_f2p0" ; if ( STI . hasFeature ( RISCV :: FeatureStdExtD ) ) Arch += "_d2p0" ; if ( STI . hasFeature ( RISCV :: FeatureStdExtC ) ) Arch += "_c2p0" ; if ( STI . hasFeature ( RISCV :: FeatureStdExtB ) ) Arch += "_b0p93" ; if ( STI . hasFeature ( RISCV :: FeatureStdExtV ) ) Arch += "_v0p10" ; if ( STI . hasFeature ( RISCV :: FeatureExtZfh ) ) Arch += "_zfh0p1" ; if ( STI . hasFeature ( RISCV :: FeatureExtZba ) ) Arch += "_zba0p93" ; if ( STI . hasFeature ( RISCV :: FeatureExtZbb ) ) Arch += "_zbb0p93" ; if ( STI . hasFeature ( RISCV :: FeatureExtZbc ) ) Arch += "_zbc0p93" ; if ( STI . hasFeature ( RISCV :: FeatureExtZbe ) ) Arch += "_zbe0p93" ; if ( STI . hasFeature ( RISCV :: FeatureExtZbf ) ) Arch += "_zbf0p93" ; if ( STI . hasFeature ( RISCV :: FeatureExtZbm ) ) Arch += "_zbm0p93" ; if ( STI . hasFeature ( RISCV :: FeatureExtZbp ) ) Arch += "_zbp0p93" ; if ( STI . hasFeature ( RISCV :: FeatureExtZbproposedc ) ) Arch += "_zbproposedc0p93" ; if ( STI . hasFeature ( RISCV :: FeatureExtZbr ) ) Arch += "_zbr0p93" ; if ( STI . hasFeature ( RISCV :: FeatureExtZbs ) ) Arch += "_zbs0p93" ; if ( STI . hasFeature ( RISCV :: FeatureExtZbt ) ) Arch += "_zbt0p93" ; if ( STI . hasFeature ( RISCV :: FeatureExtZvamo ) ) Arch += "_zvamo0p10" ; if ( STI . hasFeature ( RISCV :: FeatureStdExtZvlsseg ) ) Arch += "_zvlsseg0p10" ; emitTextAttribute ( RISCVAttrs :: ARCH , Arch ) ; } </s>

Emit the build attributes that only depend on the hardware that we expect .


<s>
static
bool
aarch64_pass_by_reference
(
cumulative_args_t
pcum_v
,
const
function_arg_info
&
arg
)
{
CUMULATIVE_ARGS
*
pcum
=
get_cumulative_args
(
pcum_v
)
;
if
(
!
arg
.
type
)
return
aarch64_pass_by_reference_1
(
pcum
,
arg
)
;
pure_scalable_type_info
pst_info
;
switch
(
pst_info
.
analyze
(
arg
.
type
)
)
{
case
pure_scalable_type_info
::
IS_PST
:
if
(
pcum
&&
!
pcum
->
silent_p
&&
!
TARGET_SVE
)
fatal_error
(
input_location
,
"arguments of type %qT require"
" the SVE ISA extension"
,
arg
.
type
)
;
return
(
!
arg
.
named
||
pcum
->
aapcs_nvrn
+
pst_info
.
num_zr
(
)
>
NUM_FP_ARG_REGS
||
pcum
->
aapcs_nprn
+
pst_info
.
num_pr
(
)
>
NUM_PR_ARG_REGS
)
;
case
pure_scalable_type_info
::
DOESNT_MATTER
:
gcc_assert
(
aarch64_pass_by_reference_1
(
pcum
,
arg
)
)
;
return
true
;
case
pure_scalable_type_info
::
NO_ABI_IDENTITY
:
case
pure_scalable_type_info
::
ISNT_PST
:
return
aarch64_pass_by_reference_1
(
pcum
,
arg
)
;
}
gcc_unreachable
(
)
;
}
</s>

aarch64
"arguments of type %qT require"
" the SVE ISA extension"


<s> static void expand_strncmp_align_check ( rtx strncmp_label , rtx src , HOST_WIDE_INT bytes ) { rtx lab_ref = gen_rtx_LABEL_REF ( VOIDmode , strncmp_label ) ; rtx src_check = copy_addr_to_reg ( XEXP ( src , 0 ) ) ; if ( GET_MODE ( src_check ) == SImode ) emit_insn ( gen_andsi3 ( src_check , src_check , GEN_INT ( 0xfff ) ) ) ; else emit_insn ( gen_anddi3 ( src_check , src_check , GEN_INT ( 0xfff ) ) ) ; rtx cond = gen_reg_rtx ( CCmode ) ; emit_move_insn ( cond , gen_rtx_COMPARE ( CCmode , src_check , GEN_INT ( 4096 - bytes ) ) ) ; rtx cmp_rtx = gen_rtx_GE ( VOIDmode , cond , const0_rtx ) ; rtx ifelse = gen_rtx_IF_THEN_ELSE ( VOIDmode , cmp_rtx , lab_ref , pc_rtx ) ; rtx j = emit_jump_insn ( gen_rtx_SET ( pc_rtx , ifelse ) ) ; JUMP_LABEL ( j ) = strncmp_label ; LABEL_NUSES ( strncmp_label ) += 1 ; } </s>

Generate page crossing check and branch code to set up for strncmp when we do n't have DI alignment . STRNCMP_LABEL is the label to branch if there is a page crossing . SRC_ADDR is the string address to be examined . BYTES is the max number of bytes to compare .


<s>
static
void
fr30_asm_trampoline_template
(
FILE
*
f
)
{
fprintf
(
f
,
"\tnop\n"
)
;
fprintf
(
f
,
"\tldi:32\t#0, %s\n"
,
reg_names
[
STATIC_CHAIN_REGNUM
]
)
;
fprintf
(
f
,
"\tnop\n"
)
;
fprintf
(
f
,
"\tldi:32\t#0, %s\n"
,
reg_names
[
COMPILER_SCRATCH_REGISTER
]
)
;
fprintf
(
f
,
"\tjmp\t@%s\n"
,
reg_names
[
COMPILER_SCRATCH_REGISTER
]
)
;
}
</s>

Implement TARGET_ASM_TRAMPOLINE_TEMPLATE . On the FR30 , the trampoline is : nop ldi:32 STATIC , r12 nop ldi:32 FUNCTION , r0 jmp @ r0 The no-ops are to guarantee that the static chain and final target are 32 bit aligned within the trampoline . That allows us to initialize those locations with simple SImode stores . The alternative would be to use HImode stores .


<s> static int ia32_multipass_dfa_lookahead ( void ) { if ( ix86_tune == PROCESSOR_PENTIUM ) return 2 ; if ( ix86_tune == PROCESSOR_PENTIUMPRO || ix86_tune == PROCESSOR_K6 ) return 1 ; else return 0 ; } </s>

How many alternative schedules to try . This should be as wide as the scheduling freedom in the DFA , but no wider . Making this value too large results extra work for the scheduler .


<s> static rtx rs6000_delegitimize_address ( rtx orig_x ) { rtx x , y , offset ; orig_x = delegitimize_mem_from_attrs ( orig_x ) ; x = orig_x ; if ( MEM_P ( x ) ) x = XEXP ( x , 0 ) ; y = x ; if ( TARGET_CMODEL != CMODEL_SMALL && GET_CODE ( y ) == LO_SUM ) y = XEXP ( y , 1 ) ; offset = NULL_RTX ; if ( GET_CODE ( y ) == PLUS && GET_MODE ( y ) == Pmode && CONST_INT_P ( XEXP ( y , 1 ) ) ) { offset = XEXP ( y , 1 ) ; y = XEXP ( y , 0 ) ; } if ( GET_CODE ( y ) == UNSPEC && XINT ( y , 1 ) == UNSPEC_TOCREL ) { y = XVECEXP ( y , 0 , 0 ) ; if ( TARGET_XCOFF && GET_CODE ( y ) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P ( y ) && rs6000_real_tls_symbol_ref_p ( get_pool_constant ( y ) ) ) return orig_x ; if ( offset != NULL_RTX ) y = gen_rtx_PLUS ( Pmode , y , offset ) ; if ( ! MEM_P ( orig_x ) ) return y ; else return replace_equiv_address_nv ( orig_x , y ) ; } if ( TARGET_MACHO && GET_CODE ( orig_x ) == LO_SUM && GET_CODE ( XEXP ( orig_x , 1 ) ) == CONST ) { y = XEXP ( XEXP ( orig_x , 1 ) , 0 ) ; if ( GET_CODE ( y ) == UNSPEC && XINT ( y , 1 ) == UNSPEC_MACHOPIC_OFFSET ) return XVECEXP ( y , 0 , 0 ) ; } return orig_x ; } </s>

In the name of slightly smaller debug output , and to cater to general assembler lossage , recognize various UNSPEC sequences and turn them back into a direct symbol reference .


"ERROR: Unknown type of MachineOperand: "

getMachineOpValue - Return binary encoding of operand .


<s>
void
SystemZMCAsmBackend
::
applyFixup
(
const
MCAssembler
&
Asm
,
const
MCFixup
&
Fixup
,
const
MCValue
&
Target
,
MutableArrayRef
<
char
>
Data
,
uint64_t
Value
,
bool
IsResolved
)
const
{
MCFixupKind
Kind
=
Fixup
.
getKind
(
)
;
unsigned
Offset
=
Fixup
.
getOffset
(
)
;
unsigned
BitSize
=
getFixupKindInfo
(
Kind
)
.
TargetSize
;
unsigned
Size
=
(
BitSize
+
7
)
/
8
;
assert
(
Offset
+
Size
<=
Data
.
size
(
)
&&
"Invalid fixup offset!"
)
;
Value
=
extractBitsForFixup
(
Kind
,
Value
)
;
if
(
BitSize
<
64
)
Value
&=
(
(
uint64_t
)
1
<<
BitSize
)
1
;
unsigned
ShiftValue
=
(
Size
*
8
)
8
;
for
(
unsigned
I
=
0
;
I
!=
Size
;
++
I
)
{
Data
[
Offset
+
I
]
|=
uint8_t
(
Value
>>
ShiftValue
)
;
ShiftValue
-=
8
;
}
}
</s>

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


<s> bool ix86_hard_regno_mode_ok ( int regno , machine_mode mode ) { if ( CC_REGNO_P ( regno ) ) return GET_MODE_CLASS ( mode ) == MODE_CC ; if ( GET_MODE_CLASS ( mode ) == MODE_CC || GET_MODE_CLASS ( mode ) == MODE_RANDOM || GET_MODE_CLASS ( mode ) == MODE_PARTIAL_INT ) return false ; if ( STACK_REGNO_P ( regno ) ) return VALID_FP_MODE_P ( mode ) ; if ( MASK_REGNO_P ( regno ) ) return ( VALID_MASK_REG_MODE ( mode ) || ( TARGET_AVX512BW && VALID_MASK_AVX512BW_MODE ( mode ) ) ) ; if ( BND_REGNO_P ( regno ) ) return VALID_BND_REG_MODE ( mode ) ; if ( SSE_REGNO_P ( regno ) ) { if ( TARGET_AVX512F && ( mode == XImode || VALID_AVX512F_REG_MODE ( mode ) || VALID_AVX512F_SCALAR_MODE ( mode ) ) ) return true ; if ( ( TARGET_AVX5124FMAPS || TARGET_AVX5124VNNIW ) && MOD4_SSE_REGNO_P ( regno ) && mode == V64SFmode ) return true ; if ( ( TARGET_AVX5124FMAPS || TARGET_AVX5124VNNIW ) && MOD4_SSE_REGNO_P ( regno ) && mode == V64SImode ) return true ; if ( TARGET_AVX512VL && ( mode == OImode || mode == TImode || VALID_AVX256_REG_MODE ( mode ) || VALID_AVX512VL_128_REG_MODE ( mode ) ) ) return true ; if ( EXT_REX_SSE_REGNO_P ( regno ) ) return false ; return ( ( TARGET_AVX && VALID_AVX256_REG_OR_OI_MODE ( mode ) ) || VALID_SSE_REG_MODE ( mode ) || VALID_SSE2_REG_MODE ( mode ) || VALID_MMX_REG_MODE ( mode ) || VALID_MMX_REG_MODE_3DNOW ( mode ) ) ; } if ( MMX_REGNO_P ( regno ) ) { return ( VALID_MMX_REG_MODE ( mode ) || VALID_MMX_REG_MODE_3DNOW ( mode ) ) ; } if ( mode == QImode ) { if ( ANY_QI_REGNO_P ( regno ) ) return true ; if ( ! TARGET_PARTIAL_REG_STALL ) return true ; if ( lra_in_progress ) return true ; return ! can_create_pseudo_p ( ) ; } else if ( VALID_INT_MODE_P ( mode ) ) return true ; else if ( VALID_FP_MODE_P ( mode ) ) return true ; else if ( VALID_DFP_MODE_P ( mode ) ) return true ; else if ( VALID_MMX_REG_MODE_3DNOW ( mode ) || VALID_MMX_REG_MODE ( mode ) ) return true ; return false ; } </s>

Return TRUE if hard register REGNO can hold a value of machine-mode MODE .


<s> BitVector SHUXIRegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; Reserved . set ( SHUXI :: SR ) ; Reserved . set ( SHUXI :: PC ) ; Reserved . set ( SHUXI :: SP ) ; return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .

SHUXI SHUXI SHUXI::SR SHUXI::PC SHUXI::SP


<s> SDNode * SparcDAGToDAGISel :: getGlobalBaseReg ( ) { unsigned GlobalBaseReg = TM . getSubtargetImpl ( ) -> getInstrInfo ( ) -> getGlobalBaseReg ( MF ) ; return CurDAG -> getRegister ( GlobalBaseReg , getTargetLowering ( ) -> getPointerTy ( ) ) . getNode ( ) ; } </s>

getGlobalBaseReg - Return a virtual register initialized with the the global base register value .


<s> int ia64_eh_uses ( int regno ) { unsigned int r ; if ( ! reload_completed ) return 0 ; if ( regno == 0 ) return 0 ; for ( r = reg_save_b0 ; r <= reg_save_ar_lc ; r ++ ) if ( regno == current_frame_info . r [ r ] || regno == emitted_frame_related_regs [ r ] ) return 1 ; return 0 ; } </s>

Return true if REGNO is used by the frame unwinder .


<s> void applyFixup ( const MCAssembler & Asm , const MCFixup & Fixup , const MCValue & Target , MutableArrayRef < char > Data , uint64_t Value , bool IsResolved , const MCSubtargetInfo * ) const override { const MCFixupKindInfo & Info = getFixupKindInfo ( Fixup . getKind ( ) ) ; Value = adjustFixupValue ( Fixup , Value , & Asm . getContext ( ) ) ; unsigned Offset = Fixup . getOffset ( ) ; unsigned NumBytes = 4 ; uint64_t CurVal = 0 ; for ( unsigned i = 0 ; i != NumBytes ; ++ i ) { CurVal |= ( uint64_t ) ( ( uint8_t ) Data [ Offset + i ] ) << ( i * 8 ) ; } uint64_t Mask = ( ( uint64_t ) ( - 1 ) >> ( 64 - Info . TargetSize ) ) ; Value <<= Info . TargetOffset ; Mask <<= Info . TargetOffset ; CurVal |= Value & Mask ; for ( unsigned i = 0 ; i != NumBytes ; ++ i ) { Data [ Offset + i ] = ( uint8_t ) ( ( CurVal >> ( i * 8 ) ) & 0xff ) ; } } </s>


<s> static rtx ft32_function_arg ( cumulative_args_t cum_v , enum machine_mode mode , const_tree type ATTRIBUTE_UNUSED , bool named ATTRIBUTE_UNUSED ) { CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; if ( * cum < 8 ) return gen_rtx_REG ( mode , * cum ) ; else return NULL_RTX ; } </s>

Return the next register to be used to hold a function argument or NULL_RTX if there 's no more space .


<s> bool ARMBaseTargetMachine :: addPreEmitPass ( PassManagerBase & PM , CodeGenOpt :: Level OptLevel ) { if ( OptLevel != CodeGenOpt :: None ) { if ( ! Subtarget . isThumb1Only ( ) ) PM . add ( createIfConverterPass ( ) ) ; } if ( Subtarget . isThumb2 ( ) ) { PM . add ( createThumb2ITBlockPass ( ) ) ; PM . add ( createThumb2SizeReductionPass ( ) ) ; } PM . add ( createARMConstantIslandPass ( ) ) ; return true ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s> unsigned TLCS900RegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { const TargetFrameLowering * TFI = MF . getTarget ( ) . getFrameLowering ( ) ; return TFI -> hasFP ( MF ) ? TLCS900 :: FPW : TLCS900 :: SPW ; } </s>


<s> static const char * avr_asm_len ( const char * tpl , rtx * operands , int * plen , int n_words ) { if ( NULL == plen ) { output_asm_insn ( tpl , operands ) ; } else { if ( n_words < 0 ) * plen = - n_words ; else * plen += n_words ; } return "" ; } </s>

Helper function to print assembler resp . track instruction sequence lengths . Always return `` '' . If PLEN == NULL : Output assembler code from template TPL with operands supplied by OPERANDS . This is just forwarding to output_asm_insn . If PLEN ! = NULL : If N_WORDS > = 0 Add N_WORDS to * PLEN . If N_WORDS < 0 Set * PLEN to -N_WORDS . Do n't output anything .


<s> rtx swap_endian_selector_for_mode ( machine_mode mode ) { unsigned int swap1 [ 16 ] = { 15 , 14 , 13 , 12 , 11 , 10 , 9 , 8 , 7 , 6 , 5 , 4 , 3 , 2 , 1 , 0 } ; unsigned int swap2 [ 16 ] = { 7 , 6 , 5 , 4 , 3 , 2 , 1 , 0 , 15 , 14 , 13 , 12 , 11 , 10 , 9 , 8 } ; unsigned int swap4 [ 16 ] = { 3 , 2 , 1 , 0 , 7 , 6 , 5 , 4 , 11 , 10 , 9 , 8 , 15 , 14 , 13 , 12 } ; unsigned int swap8 [ 16 ] = { 1 , 0 , 3 , 2 , 5 , 4 , 7 , 6 , 9 , 8 , 11 , 10 , 13 , 12 , 15 , 14 } ; unsigned int * swaparray , i ; rtx perm [ 16 ] ; switch ( mode ) { case E_V1TImode : swaparray = swap1 ; break ; case E_V2DFmode : case E_V2DImode : swaparray = swap2 ; break ; case E_V4SFmode : case E_V4SImode : swaparray = swap4 ; break ; case E_V8HImode : swaparray = swap8 ; break ; default : gcc_unreachable ( ) ; } for ( i = 0 ; i < 16 ; ++ i ) if ( BYTES_BIG_ENDIAN ) perm [ i ] = GEN_INT ( swaparray [ i ] ) ; else perm [ i ] = GEN_INT ( ~ swaparray [ i ] & 0x0000001f ) ; return force_reg ( V16QImode , gen_rtx_CONST_VECTOR ( V16QImode , gen_rtvec_v ( 16 , perm ) ) ) ; } </s>

Return the permutation index for the swapping on the given vector mode . Note that the permutation index is correspondingly generated by endianness , it should be used by direct vector permutation .


<s> TargetLowering :: ConstraintWeight SparcTargetLowering :: getSingleConstraintMatchWeight ( AsmOperandInfo & info , const char * constraint ) const { ConstraintWeight weight = CW_Invalid ; Value * CallOperandVal = info . CallOperandVal ; if ( CallOperandVal == NULL ) return CW_Default ; switch ( * constraint ) { default : weight = TargetLowering :: getSingleConstraintMatchWeight ( info , constraint ) ; break ; case 'I' : if ( ConstantInt * C = dyn_cast < ConstantInt > ( info . CallOperandVal ) ) { if ( isInt < 13 > ( C -> getSExtValue ( ) ) ) weight = CW_Constant ; } break ; } return weight ; } </s>

Examine constraint string and operand type and determine a weight value .


"Cannot store this register to stack slot!"

Store the specified register of the given register class to the specified stack frame index .


<s> static bool need_to_save ( unsigned int regno ) { if ( is_interrupt_func ( cfun -> decl ) ) { if ( regno < 8 ) return true ; if ( regno > 23 ) return false ; if ( ! crtl -> is_leaf && call_used_regs [ regno ] ) return true ; return df_regs_ever_live_p ( regno ) ; } if ( regno == FRAME_POINTER_REGNUM && frame_pointer_needed ) return true ; if ( fixed_regs [ regno ] ) return false ; if ( crtl -> calls_eh_return ) return true ; if ( df_regs_ever_live_p ( regno ) && ! call_used_regs [ regno ] ) return true ; return false ; } </s>

Returns true if the given register needs to be saved by the current function .


<s>
bool
P2FrameLowering
::
restoreCalleeSavedRegisters
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
MI
,
MutableArrayRef
<
CalleeSavedInfo
>
CSI
,
const
TargetRegisterInfo
*
TRI
)
const
{
MachineFunction
&
MF
=
*
MBB
.
getParent
(
)
;
const
P2Subtarget
&
STI
=
MF
.
getSubtarget
<
P2Subtarget
>
(
)
;
const
TargetInstrInfo
&
TII
=
*
STI
.
getInstrInfo
(
)
;
DebugLoc
DL
=
MBB
.
findDebugLoc
(
MI
)
;
LLVM_DEBUG
(
errs
(
)
<<
"=== Function: "
<<
MF
.
getName
(
)
<<
" ===\n"
)
;
LLVM_DEBUG
(
errs
(
)
<<
"Restore CSRs\n"
)
;
if
(
CSI
.
empty
(
)
)
{
LLVM_DEBUG
(
errs
(
)
<<
"--- nothing to restore\n"
)
;
return
false
;
}
for
(
unsigned
i
=
CSI
.
size
(
)
;
i
!=
0
;
i
)
{
unsigned
Reg
=
CSI
[
i
1
]
.
getReg
(
)
;
const
TargetRegisterClass
*
RC
=
TRI
->
getMinimalPhysRegClass
(
Reg
)
;
TII
.
loadRegFromStackSlot
(
MBB
,
MI
,
Reg
,
CSI
[
i
1
]
.
getFrameIdx
(
)
,
RC
,
TRI
)
;
LLVM_DEBUG
(
errs
(
)
<<
"--- restoring "
<<
Reg
<<
" from index "
<<
CSI
[
i
1
]
.
getFrameIdx
(
)
<<
"\n"
)
;
}
LLVM_DEBUG
(
errs
(
)
<<
"\n"
)
;
return
true
;
}
</s>

restoreCalleeSavedRegisters - Issues instruction ( s ) to restore all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of load instructions via loadRegToStackSlot ( ) .


<s> static unsigned int rest_of_insert_bti ( void ) { timevar_push ( TV_MACH_DEP ) ; rtx bti_insn ; rtx_insn * insn ; basic_block bb ; bb = 0 ; FOR_EACH_BB_FN ( bb , cfun ) { for ( insn = BB_HEAD ( bb ) ; insn != NEXT_INSN ( BB_END ( bb ) ) ; insn = NEXT_INSN ( insn ) ) { if ( LABEL_P ( insn ) && ( LABEL_PRESERVE_P ( insn ) || bb -> flags & BB_NON_LOCAL_GOTO_TARGET ) ) { bti_insn = gen_bti_j ( ) ; emit_insn_after ( bti_insn , insn ) ; continue ; } if ( JUMP_P ( insn ) ) { rtx_jump_table_data * table ; if ( tablejump_p ( insn , NULL , & table ) ) { rtvec vec = table -> get_labels ( ) ; int j ; rtx_insn * label ; for ( j = GET_NUM_ELEM ( vec ) - 1 ; j >= 0 ; -- j ) { label = as_a < rtx_insn * > ( XEXP ( RTVEC_ELT ( vec , j ) , 0 ) ) ; rtx_insn * next = next_nonnote_nondebug_insn ( label ) ; if ( aarch64_bti_j_insn_p ( next ) ) continue ; bti_insn = gen_bti_j ( ) ; emit_insn_after ( bti_insn , label ) ; } } } if ( CALL_P ( insn ) && ( find_reg_note ( insn , REG_SETJMP , NULL ) ) ) { bti_insn = gen_bti_j ( ) ; emit_insn_after ( bti_insn , insn ) ; continue ; } } } if ( ! cgraph_node :: get ( cfun -> decl ) -> only_called_directly_p ( ) ) { bb = ENTRY_BLOCK_PTR_FOR_FN ( cfun ) -> next_bb ; insn = BB_HEAD ( bb ) ; if ( ! aarch64_pac_insn_p ( get_first_nonnote_insn ( ) ) ) { bti_insn = gen_bti_c ( ) ; emit_insn_before ( bti_insn , insn ) ; } } timevar_pop ( TV_MACH_DEP ) ; return 0 ; } </s>

This is implemented as a late RTL pass that runs before branch shortening and does the following .


<s> TargetLoweringBase :: LegalizeTypeAction X86TargetLowering :: getPreferredVectorAction ( EVT VT ) const { if ( ExperimentalVectorWideningLegalization && VT . getVectorNumElements ( ) != 1 && VT . getVectorElementType ( ) . getSimpleVT ( ) != MVT :: i1 ) return TypeWidenVector ; return TargetLoweringBase :: getPreferredVectorAction ( VT ) ; } </s>

Customize the preferred legalization strategy for certain types .


<s> MCLOHType getKind ( ) const { return Kind ; } </s>


<s> bool ARMConstantPoolValue :: hasSameValue ( ARMConstantPoolValue * ACPV ) { if ( ACPV -> Kind == Kind && ACPV -> CVal == CVal && ACPV -> PCAdjust == PCAdjust && ( ACPV -> S == S || strcmp ( ACPV -> S , S ) == 0 ) && ( ACPV -> Modifier == Modifier || strcmp ( ACPV -> Modifier , Modifier ) == 0 ) ) { if ( ACPV -> LabelId == LabelId ) return true ; if ( Kind == ARMCP :: CPValue || Kind == ARMCP :: CPExtSymbol ) return true ; } return false ; } </s>

hasSameValue - Return true if this ARM constpool value can share the same constantpool entry as another ARM constpool value .

ARM ARM ARM 0 0 ARMCP::CPValue ARMCP::CPExtSymbol


<s>
void
AArch64RegisterInfo
::
eliminateFrameIndex
(
MachineBasicBlock
::
iterator
II
,
int
SPAdj
,
unsigned
FIOperandNum
,
RegScavenger
*
RS
)
const
{
assert
(
SPAdj
==
0
&&
"Unexpected"
)
;
MachineInstr
&
MI
=
*
II
;
MachineBasicBlock
&
MBB
=
*
MI
.
getParent
(
)
;
MachineFunction
&
MF
=
*
MBB
.
getParent
(
)
;
const
AArch64InstrInfo
*
TII
=
MF
.
getSubtarget
<
AArch64Subtarget
>
(
)
.
getInstrInfo
(
)
;
const
AArch64FrameLowering
*
TFI
=
getFrameLowering
(
MF
)
;
int
FrameIndex
=
MI
.
getOperand
(
FIOperandNum
)
.
getIndex
(
)
;
unsigned
FrameReg
;
int
Offset
;
if
(
MI
.
isDebugValue
(
)
||
MI
.
getOpcode
(
)
==
TargetOpcode
::
STACKMAP
||
MI
.
getOpcode
(
)
==
TargetOpcode
::
PATCHPOINT
)
{
Offset
=
TFI
->
resolveFrameIndexReference
(
MF
,
FrameIndex
,
FrameReg
,
true
,
false
)
;
Offset
+=
MI
.
getOperand
(
FIOperandNum
+
1
)
.
getImm
(
)
;
MI
.
getOperand
(
FIOperandNum
)
.
ChangeToRegister
(
FrameReg
,
false
)
;
MI
.
getOperand
(
FIOperandNum
+
1
)
.
ChangeToImmediate
(
Offset
)
;
return
;
}
if
(
MI
.
getOpcode
(
)
==
TargetOpcode
::
LOCAL_ESCAPE
)
{
MachineOperand
&
FI
=
MI
.
getOperand
(
FIOperandNum
)
;
Offset
=
TFI
->
getNonLocalFrameIndexReference
(
MF
,
FrameIndex
)
;
FI
.
ChangeToImmediate
(
Offset
)
;
return
;
}
if
(
MI
.
getOpcode
(
)
==
AArch64
::
TAGPstack
)
{
const
MachineFrameInfo
&
MFI
=
MF
.
getFrameInfo
(
)
;
const
AArch64FunctionInfo
*
AFI
=
MF
.
getInfo
<
AArch64FunctionInfo
>
(
)
;
FrameReg
=
MI
.
getOperand
(
3
)
.
getReg
(
)
;
Offset
=
MFI
.
getObjectOffset
(
FrameIndex
)
+
AFI
->
getTaggedBasePointerOffset
(
)
;
}
else
{
Offset
=
TFI
->
resolveFrameIndexReference
(
MF
,
FrameIndex
,
FrameReg
,
false
,
true
)
;
}
if
(
rewriteAArch64FrameIndex
(
MI
,
FIOperandNum
,
FrameReg
,
Offset
,
TII
)
)
return
;
assert
(
(
!
RS
||
!
RS
->
isScavengingFrameIndex
(
FrameIndex
)
)
&&
"Emergency spill slot is out of reach"
)
;
unsigned
ScratchReg
=
MF
.
getRegInfo
(
)
.
createVirtualRegister
(
&
AArch64
::
GPR64RegClass
)
;
emitFrameOffset
(
MBB
,
II
,
MI
.
getDebugLoc
(
)
,
ScratchReg
,
FrameReg
,
Offset
,
TII
)
;
MI
.
getOperand
(
FIOperandNum
)
.
ChangeToRegister
(
ScratchReg
,
false
,
false
,
true
)
;
}
</s>

This method must be overriden to eliminate abstract frame indices from instructions which may use them .


<s> unsigned int h8300_unary_length ( rtx op ) { enum h8300_operand_class class ; unsigned int size , operand_length ; size = GET_MODE_SIZE ( GET_MODE ( op ) ) ; operand_length = h8300_classify_operand ( op , size , & class ) ; switch ( class ) { case H8OP_REGISTER : return 2 ; case H8OP_MEM_BASE : return ( size == 4 ? 6 : 4 ) ; case H8OP_MEM_ABSOLUTE : return operand_length + ( size == 4 ? 6 : 4 ) ; case H8OP_MEM_COMPLEX : return operand_length + 6 ; default : gcc_unreachable ( ) ; } } static unsigned int h8300_short_immediate_length ( rtx op ) { enum h8300_operand_class class ; unsigned int size , operand_length ; size = GET_MODE_SIZE ( GET_MODE ( op ) ) ; operand_length = h8300_classify_operand ( op , size , & class ) ; switch ( class ) { case H8OP_REGISTER : return 2 ; case H8OP_MEM_BASE : case H8OP_MEM_ABSOLUTE : case H8OP_MEM_COMPLEX : return 4 + operand_length ; default : gcc_unreachable ( ) ; } } </s>

Return the length of a unary instruction such as neg or not given that its operand is OP .


"  Skipping pass: no machine model present.\n"

runOnMachineFunction - Emit the function body .


<s> const GCNSubtarget & getSubtarget ( ) const { return ST ; } </s>

getSubtarget - Return the subtarget for which this machine code is being compiled .


<s> bool X86TargetLowering :: isGAPlusOffset ( SDNode * N , GlobalValue * & GA , int64_t & Offset ) const { if ( N -> getOpcode ( ) == X86ISD :: Wrapper ) { if ( isa < GlobalAddressSDNode > ( N -> getOperand ( 0 ) ) ) { GA = cast < GlobalAddressSDNode > ( N -> getOperand ( 0 ) ) -> getGlobal ( ) ; Offset = cast < GlobalAddressSDNode > ( N -> getOperand ( 0 ) ) -> getOffset ( ) ; return true ; } } return TargetLowering :: isGAPlusOffset ( N , GA , Offset ) ; } </s>

Returns true ( and the GlobalValue and the offset ) if the node is a GlobalAddress + offset .


<s>
const
TargetRegisterClass
*
JVMRegisterInfo
::
getPointerRegClass
(
const
MachineFunction
&
MF
,
unsigned
Kind
)
const
{
assert
(
Kind
==
0
&&
"Only one kind of pointer on JVM"
)
;
if
(
MF
.
getSubtarget
<
JVMSubtarget
>
(
)
.
hasAddr64
(
)
)
return
&
JVM
::
I64RegClass
;
return
&
JVM
::
I32RegClass
;
}
</s>

getPointerRegClass - Returns a TargetRegisterClass used for pointer values .


<s>
bool
ARM64InstrInfo
::
isFPRCopy
(
const
MachineInstr
*
MI
)
const
{
switch
(
MI
->
getOpcode
(
)
)
{
default
:
break
;
case
TargetOpcode
::
COPY
:
{
unsigned
DstReg
=
MI
->
getOperand
(
0
)
.
getReg
(
)
;
return
(
ARM64
::
FPR64RegClass
.
contains
(
DstReg
)
||
ARM64
::
FPR128RegClass
.
contains
(
DstReg
)
)
;
}
case
ARM64
::
ORRv16i8
:
if
(
MI
->
getOperand
(
1
)
.
getReg
(
)
==
MI
->
getOperand
(
2
)
.
getReg
(
)
)
{
assert
(
MI
->
getDesc
(
)
.
getNumOperands
(
)
==
3
&&
MI
->
getOperand
(
0
)
.
isReg
(
)
&&
"invalid ORRv16i8 operands"
)
;
return
true
;
}
}
return
false
;
}
</s>

Does this instruction rename an FPR without modifying bits ?


<s>
rtx
avr_legitimize_reload_address
(
rtx
*
px
,
machine_mode
mode
,
int
opnum
,
int
type
,
int
addr_type
,
int
ind_levels
ATTRIBUTE_UNUSED
,
rtx
(
*
mk_memloc
)
(
rtx
,
int
)
)
{
rtx
x
=
*
px
;
if
(
avr_log
.
legitimize_reload_address
)
avr_edump
(
"\n%?:%m %r\n"
,
mode
,
x
)
;
if
(
1
&&
(
GET_CODE
(
x
)
==
POST_INC
||
GET_CODE
(
x
)
==
PRE_DEC
)
)
{
push_reload
(
XEXP
(
x
,
0
)
,
XEXP
(
x
,
0
)
,
&
XEXP
(
x
,
0
)
,
&
XEXP
(
x
,
0
)
,
POINTER_REGS
,
GET_MODE
(
x
)
,
GET_MODE
(
x
)
,
0
,
0
,
opnum
,
RELOAD_OTHER
)
;
if
(
avr_log
.
legitimize_reload_address
)
avr_edump
(
" RCLASS.1 = %R\n IN = %r\n OUT = %r\n"
,
POINTER_REGS
,
XEXP
(
x
,
0
)
,
XEXP
(
x
,
0
)
)
;
return
x
;
}
if
(
GET_CODE
(
x
)
==
PLUS
&&
REG_P
(
XEXP
(
x
,
0
)
)
&&
0
==
reg_equiv_constant
(
REGNO
(
XEXP
(
x
,
0
)
)
)
&&
CONST_INT_P
(
XEXP
(
x
,
1
)
)
&&
INTVAL
(
XEXP
(
x
,
1
)
)
>=
1
)
{
bool
fit
=
INTVAL
(
XEXP
(
x
,
1
)
)
<=
MAX_LD_OFFSET
(
mode
)
;
if
(
fit
)
{
if
(
reg_equiv_address
(
REGNO
(
XEXP
(
x
,
0
)
)
)
!=
0
)
{
int
regno
=
REGNO
(
XEXP
(
x
,
0
)
)
;
rtx
mem
=
mk_memloc
(
x
,
regno
)
;
push_reload
(
XEXP
(
mem
,
0
)
,
NULL_RTX
,
&
XEXP
(
mem
,
0
)
,
,
POINTER_REGS
,
Pmode
,
VOIDmode
,
0
,
0
,
1
,
(
enum
reload_type
)
addr_type
)
;
if
(
avr_log
.
legitimize_reload_address
)
avr_edump
(
" RCLASS.2 = %R\n IN = %r\n OUT = %r\n"
,
POINTER_REGS
,
XEXP
(
mem
,
0
)
,
NULL_RTX
)
;
push_reload
(
mem
,
NULL_RTX
,
&
XEXP
(
x
,
0
)
,
,
BASE_POINTER_REGS
,
GET_MODE
(
x
)
,
VOIDmode
,
0
,
0
,
opnum
,
(
enum
reload_type
)
type
)
;
if
(
avr_log
.
legitimize_reload_address
)
avr_edump
(
" RCLASS.2 = %R\n IN = %r\n OUT = %r\n"
,
BASE_POINTER_REGS
,
mem
,
NULL_RTX
)
;
return
x
;
}
}
else
if
(
!
(
frame_pointer_needed
&&
XEXP
(
x
,
0
)
==
frame_pointer_rtx
)
)
{
push_reload
(
x
,
NULL_RTX
,
px
,
,
POINTER_REGS
,
GET_MODE
(
x
)
,
VOIDmode
,
0
,
0
,
opnum
,
(
enum
reload_type
)
type
)
;
if
(
avr_log
.
legitimize_reload_address
)
avr_edump
(
" RCLASS.3 = %R\n IN = %r\n OUT = %r\n"
,
POINTER_REGS
,
x
,
NULL_RTX
)
;
return
x
;
}
}
return
NULL_RTX
;
}
</s>

This will allow register R26/27 to be used where it is no worse than normal base pointers R28/29 or R30/31 . For example , if base offset is greater than 63 bytes or for R++ or -- R addressing .


<s> SDValue AMDGPUTargetLowering :: SplitVectorStore ( SDValue Op , SelectionDAG & DAG ) const { StoreSDNode * Store = cast < StoreSDNode > ( Op ) ; EVT MemEltVT = Store -> getMemoryVT ( ) . getVectorElementType ( ) ; EVT EltVT = Store -> getValue ( ) . getValueType ( ) . getVectorElementType ( ) ; EVT PtrVT = Store -> getBasePtr ( ) . getValueType ( ) ; unsigned NumElts = Store -> getMemoryVT ( ) . getVectorNumElements ( ) ; SDLoc SL ( Op ) ; SmallVector < SDValue , 8 > Chains ; for ( unsigned i = 0 , e = NumElts ; i != e ; ++ i ) { SDValue Val = DAG . getNode ( ISD :: EXTRACT_VECTOR_ELT , SL , EltVT , Store -> getValue ( ) , DAG . getConstant ( i , MVT :: i32 ) ) ; SDValue Ptr = DAG . getNode ( ISD :: ADD , SL , PtrVT , Store -> getBasePtr ( ) , DAG . getConstant ( i * ( MemEltVT . getSizeInBits ( ) / 8 ) , PtrVT ) ) ; Chains . push_back ( DAG . getTruncStore ( Store -> getChain ( ) , SL , Val , Ptr , MachinePointerInfo ( Store -> getMemOperand ( ) -> getValue ( ) ) , MemEltVT , Store -> isVolatile ( ) , Store -> isNonTemporal ( ) , Store -> getAlignment ( ) ) ) ; } return DAG . getNode ( ISD :: TokenFactor , SL , MVT :: Other , & Chains [ 0 ] , NumElts ) ; } </s>

Split a vector store into 2 stores of half the vector .


<s> virtual const InstrItineraryData getInstrItineraryData ( ) const { return InstrItins ; } </s>

getInstrItineraryData - Returns instruction itinerary data for the target or specific subtarget .


<s> const char * output_cbranch ( rtx label , enum rtx_code code , machine_mode cc_mode , int reversed , rtx_insn * insn ) { const char * cond ; if ( reversed ) { if ( cc_mode == CCFPmode || cc_mode == CCFPEmode ) code = reverse_condition_maybe_unordered ( code ) ; else code = reverse_condition ( code ) ; } switch ( code ) { case NE : if ( cc_mode == CCCmode ) cond = "cs" ; else if ( cc_mode == CCVmode ) cond = "os" ; else cond = "ne" ; break ; case EQ : if ( cc_mode == CCCmode ) cond = "cc" ; else if ( cc_mode == CCVmode ) cond = "oc" ; else cond = "eq" ; break ; case GE : if ( cc_mode == CCNZmode ) cond = "nc" ; else cond = "ge" ; break ; case GT : cond = "gt" ; break ; case LE : if ( cc_mode == CCFPmode || cc_mode == CCFPEmode ) cond = "ls" ; else cond = "le" ; break ; case LT : if ( cc_mode == CCFPmode || cc_mode == CCFPEmode ) cond = "cs" ; else if ( cc_mode == CCNZmode ) cond = "ns" ; else cond = "lt" ; break ; case GEU : cond = "cc" ; break ; case GTU : cond = "hi" ; break ; case LEU : cond = "ls" ; break ; case LTU : cond = "cs" ; break ; case UNORDERED : cond = "os" ; break ; case ORDERED : cond = "oc" ; break ; case UNGE : cond = "cc" ; break ; case UNGT : cond = "hi" ; break ; case UNLE : cond = "le" ; break ; case UNLT : cond = "lt" ; break ; case UNEQ : case LTGT : default : gcc_unreachable ( ) ; } return output_branch ( label , cond , insn ) ; } </s>

Output a conditional branch to LABEL . CODE is the comparison code . CC_MODE is the mode of the CC register . REVERSED is non-zero if we should reverse the sense of the comparison . INSN is the instruction .

visium "cs" "os" "ne" "cc" "oc" "eq" "nc" "ge" "gt" "ls" "le" "cs" "ns" "lt" "cc" "hi" "ls" "cs" "os" "oc" "cc" "hi" "le" "lt"


<s> void print ( raw_ostream & OS ) const { } </s>

print - Print a debug representation of the operand to the given stream .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . addRequired < MachineModuleInfo > ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> const KudeyarRegisterInfo & KudeyarInstrInfo :: getRegisterInfo ( ) const { return RI ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s> bool M88kCallLowering :: lowerCall ( MachineIRBuilder & MIRBuilder , CallLoweringInfo & Info ) const { MachineFunction & MF = MIRBuilder . getMF ( ) ; const Function & F = MF . getFunction ( ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; auto & DL = F . getParent ( ) -> getDataLayout ( ) ; SmallVector < ArgInfo , 8 > OutArgs ; for ( auto & OrigArg : Info . OrigArgs ) { splitToValueTypes ( OrigArg , OutArgs , DL , Info . CallConv ) ; } SmallVector < ArgInfo , 8 > InArgs ; if ( ! Info . OrigRet . Ty -> isVoidTy ( ) ) splitToValueTypes ( Info . OrigRet , InArgs , DL , Info . CallConv ) ; MachineInstrBuilder CallSeqStart ; CallSeqStart = MIRBuilder . buildInstr ( M88k :: ADJCALLSTACKDOWN ) ; unsigned Opc = Info . Callee . isReg ( ) ? M88k :: JSR : M88k :: BSR ; auto MIB = MIRBuilder . buildInstrNoInsert ( Opc ) ; MIB . add ( Info . Callee ) ; const uint32_t * Mask ; const M88kSubtarget & Subtarget = MF . getSubtarget < M88kSubtarget > ( ) ; const auto * TRI = Subtarget . getRegisterInfo ( ) ; OutgoingValueAssigner ArgAssigner ( CC_M88k ) ; OutgoingArgHandler Handler ( MIRBuilder , MRI , MIB ) ; if ( ! determineAndHandleAssignments ( Handler , ArgAssigner , OutArgs , MIRBuilder , Info . CallConv , Info . IsVarArg ) ) return false ; Mask = TRI -> getCallPreservedMask ( MF , Info . CallConv ) ; MIB . addRegMask ( Mask ) ; MIRBuilder . insertInstr ( MIB ) ; if ( Info . Callee . isReg ( ) ) constrainOperandRegClass ( MF , * TRI , MRI , * Subtarget . getInstrInfo ( ) , * Subtarget . getRegBankInfo ( ) , * MIB , MIB -> getDesc ( ) , Info . Callee , 0 ) ; if ( ! Info . OrigRet . Ty -> isVoidTy ( ) ) { OutgoingValueAssigner ArgAssigner ( RetCC_M88k ) ; CallReturnHandler ReturnedArgHandler ( MIRBuilder , MRI , MIB ) ; if ( ! determineAndHandleAssignments ( ReturnedArgHandler , ArgAssigner , InArgs , MIRBuilder , Info . CallConv , Info . IsVarArg , OutArgs [ 0 ] . Regs [ 0 ] ) ) return false ; } CallSeqStart . addImm ( ArgAssigner . StackOffset ) . addImm ( 0 ) ; MIRBuilder . buildInstr ( M88k :: ADJCALLSTACKUP ) . addImm ( ArgAssigner . StackOffset ) . addImm ( 0 ) ; return true ; } </s>

This hook must be implemented to lower the given call instruction , including argument and return value marshalling .


<s> DecodeStatus HexagonDisassembler :: getInstruction ( MCInst & MI , uint64_t & Size , ArrayRef < uint8_t > Bytes , uint64_t Address , raw_ostream & os , raw_ostream & cs ) const { DecodeStatus Result = DecodeStatus :: Success ; bool Complete = false ; Size = 0 ; * CurrentBundle = & MI ; MI . setOpcode ( Hexagon :: BUNDLE ) ; MI . addOperand ( MCOperand :: createImm ( 0 ) ) ; while ( Result == Success && ! Complete ) { if ( Bytes . size ( ) < HEXAGON_INSTR_SIZE ) return MCDisassembler :: Fail ; MCInst * Inst = new ( getContext ( ) ) MCInst ; Result = getSingleInstruction ( * Inst , MI , Bytes , Address , os , cs , Complete ) ; MI . addOperand ( MCOperand :: createInst ( Inst ) ) ; Size += HEXAGON_INSTR_SIZE ; Bytes = Bytes . slice ( HEXAGON_INSTR_SIZE ) ; } if ( Result == MCDisassembler :: Fail ) return Result ; if ( Size > HEXAGON_MAX_PACKET_SIZE ) return MCDisassembler :: Fail ; HexagonMCChecker Checker ( getContext ( ) , * MCII , STI , MI , * getContext ( ) . getRegisterInfo ( ) , false ) ; if ( ! Checker . check ( ) ) return MCDisassembler :: Fail ; remapInstruction ( MI ) ; return MCDisassembler :: Success ; } </s>

Returns the disassembly of a single instruction .

Hexagon Hexagon 0 Hexagon::BUNDLE 0 Hexagon


<s> virtual const AMDGPUIntrinsicInfo * getIntrinsicInfo ( ) const { return & IntrinsicInfo ; } </s>

If intrinsic information is available , return it . If not , return null .


<s> bool VZeroUpperInserter :: runOnMachineFunction ( MachineFunction & MF ) { TII = MF . getTarget ( ) . getInstrInfo ( ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; bool EverMadeChange = false ; bool YMMUsed = false ; const TargetRegisterClass * RC = & X86 :: VR256RegClass ; for ( TargetRegisterClass :: iterator i = RC -> begin ( ) , e = RC -> end ( ) ; i != e ; i ++ ) { if ( MRI . isPhysRegUsed ( * i ) ) { YMMUsed = true ; break ; } } if ( ! YMMUsed ) return EverMadeChange ; FnHasLiveInYmm = checkFnHasLiveInYmm ( MRI ) ; assert ( BBState . empty ( ) ) ; BBState . resize ( MF . getNumBlockIDs ( ) , 0 ) ; BBSolved . resize ( MF . getNumBlockIDs ( ) , 0 ) ; while ( 1 ) { bool MadeChange = false ; for ( MachineFunction :: iterator I = MF . begin ( ) , E = MF . end ( ) ; I != E ; ++ I ) MadeChange |= processBasicBlock ( MF , * I ) ; if ( ! MadeChange ) break ; EverMadeChange = true ; } BBState . clear ( ) ; BBSolved . clear ( ) ; return EverMadeChange ; } </s>


<s> HOST_WIDE_INT rs6000_builtin_mask_calculate ( void ) { return ( ( ( TARGET_ALTIVEC ) ? RS6000_BTM_ALTIVEC : 0 ) | ( ( TARGET_CMPB ) ? RS6000_BTM_CMPB : 0 ) | ( ( TARGET_VSX ) ? RS6000_BTM_VSX : 0 ) | ( ( TARGET_SPE ) ? RS6000_BTM_SPE : 0 ) | ( ( TARGET_PAIRED_FLOAT ) ? RS6000_BTM_PAIRED : 0 ) | ( ( TARGET_FRE ) ? RS6000_BTM_FRE : 0 ) | ( ( TARGET_FRES ) ? RS6000_BTM_FRES : 0 ) | ( ( TARGET_FRSQRTE ) ? RS6000_BTM_FRSQRTE : 0 ) | ( ( TARGET_FRSQRTES ) ? RS6000_BTM_FRSQRTES : 0 ) | ( ( TARGET_POPCNTD ) ? RS6000_BTM_POPCNTD : 0 ) | ( ( rs6000_cpu == PROCESSOR_CELL ) ? RS6000_BTM_CELL : 0 ) | ( ( TARGET_P8_VECTOR ) ? RS6000_BTM_P8_VECTOR : 0 ) | ( ( TARGET_P9_VECTOR ) ? RS6000_BTM_P9_VECTOR : 0 ) | ( ( TARGET_P9_MISC ) ? RS6000_BTM_P9_MISC : 0 ) | ( ( TARGET_MODULO ) ? RS6000_BTM_MODULO : 0 ) | ( ( TARGET_64BIT ) ? RS6000_BTM_64BIT : 0 ) | ( ( TARGET_CRYPTO ) ? RS6000_BTM_CRYPTO : 0 ) | ( ( TARGET_HTM ) ? RS6000_BTM_HTM : 0 ) | ( ( TARGET_DFP ) ? RS6000_BTM_DFP : 0 ) | ( ( TARGET_HARD_FLOAT ) ? RS6000_BTM_HARD_FLOAT : 0 ) | ( ( TARGET_LONG_DOUBLE_128 ) ? RS6000_BTM_LDBL128 : 0 ) | ( ( TARGET_FLOAT128_TYPE ) ? RS6000_BTM_FLOAT128 : 0 ) ) ; } </s>

Return the builtin mask of the various options used that could affect which builtins were used . In the past we used target_flags , but we 've run out of bits , and some options like PAIRED are no longer in target_flags .


<s> static void emit_link_insn ( rtx spreg , HOST_WIDE_INT frame_size ) { HOST_WIDE_INT link_size = frame_size ; rtx_insn * insn ; int i ; if ( link_size > 262140 ) link_size = 262140 ; insn = emit_insn ( gen_link ( GEN_INT ( - 8 - link_size ) ) ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; for ( i = 0 ; i < XVECLEN ( PATTERN ( insn ) , 0 ) ; i ++ ) { rtx set = XVECEXP ( PATTERN ( insn ) , 0 , i ) ; gcc_assert ( GET_CODE ( set ) == SET ) ; RTX_FRAME_RELATED_P ( set ) = 1 ; } frame_size -= link_size ; if ( frame_size > 0 ) { rtx tmpreg = gen_rtx_REG ( Pmode , REG_P1 ) ; frame_related_constant_load ( tmpreg , - frame_size , TRUE ) ; insn = emit_insn ( gen_addsi3 ( spreg , spreg , tmpreg ) ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; } } </s>

Generate a LINK insn for a frame sized FRAME_SIZE . If this constant is too large , generate a sequence of insns that has the same effect . SPREG contains ( reg : SI REG_SP ) .


<s> Value * ARMTargetLowering :: emitLoadLinked ( IRBuilder < > & Builder , Value * Addr , AtomicOrdering Ord ) const { Module * M = Builder . GetInsertBlock ( ) -> getParent ( ) -> getParent ( ) ; Type * ValTy = cast < PointerType > ( Addr -> getType ( ) ) -> getElementType ( ) ; bool IsAcquire = isAcquireOrStronger ( Ord ) ; if ( ValTy -> getPrimitiveSizeInBits ( ) == 64 ) { Intrinsic :: ID Int = IsAcquire ? Intrinsic :: arm_ldaexd : Intrinsic :: arm_ldrexd ; Function * Ldrex = llvm :: Intrinsic :: getDeclaration ( M , Int ) ; Addr = Builder . CreateBitCast ( Addr , Type :: getInt8PtrTy ( M -> getContext ( ) ) ) ; Value * LoHi = Builder . CreateCall ( Ldrex , Addr , "lohi" ) ; Value * Lo = Builder . CreateExtractValue ( LoHi , 0 , "lo" ) ; Value * Hi = Builder . CreateExtractValue ( LoHi , 1 , "hi" ) ; if ( ! Subtarget -> isLittle ( ) ) std :: swap ( Lo , Hi ) ; Lo = Builder . CreateZExt ( Lo , ValTy , "lo64" ) ; Hi = Builder . CreateZExt ( Hi , ValTy , "hi64" ) ; return Builder . CreateOr ( Lo , Builder . CreateShl ( Hi , ConstantInt :: get ( ValTy , 32 ) ) , "val64" ) ; } Type * Tys [ ] = { Addr -> getType ( ) } ; Intrinsic :: ID Int = IsAcquire ? Intrinsic :: arm_ldaex : Intrinsic :: arm_ldrex ; Function * Ldrex = llvm :: Intrinsic :: getDeclaration ( M , Int , Tys ) ; return Builder . CreateTruncOrBitCast ( Builder . CreateCall ( Ldrex , Addr ) , cast < PointerType > ( Addr -> getType ( ) ) -> getElementType ( ) ) ; } </s>

Perform a load-linked operation on Addr , returning a `` Value * '' with the corresponding pointee type .


<s>
static
tree
h8300_handle_tiny_data_attribute
(
tree
*
node
,
tree
name
,
tree
args
ATTRIBUTE_UNUSED
,
int
flags
ATTRIBUTE_UNUSED
,
bool
*
no_add_attrs
)
{
tree
decl
=
*
node
;
if
(
TREE_STATIC
(
decl
)
||
DECL_EXTERNAL
(
decl
)
)
{
DECL_SECTION_NAME
(
decl
)
=
build_string
(
6
,
".tiny"
)
;
}
else
{
warning
(
OPT_Wattributes
,
"%qs attribute ignored"
,
IDENTIFIER_POINTER
(
name
)
)
;
*
no_add_attrs
=
true
;
}
return
NULL_TREE
;
}
</s>

Handle an `` tiny_data '' attribute ; arguments as in struct attribute_spec.handler .


<s> static bool sh_use_by_pieces_infrastructure_p ( unsigned HOST_WIDE_INT size , unsigned int align , enum by_pieces_operation op , bool speed_p ) { switch ( op ) { case MOVE_BY_PIECES : return move_by_pieces_ninsns ( size , align , MOVE_MAX_PIECES + 1 ) < ( ! speed_p ? 2 : ( align >= 32 ) ? 16 : 2 ) ; case STORE_BY_PIECES : case SET_BY_PIECES : return move_by_pieces_ninsns ( size , align , STORE_MAX_PIECES + 1 ) < ( ! speed_p ? 2 : ( align >= 32 ) ? 16 : 2 ) ; default : return default_use_by_pieces_infrastructure_p ( size , align , op , speed_p ) ; } } </s>


<s> unsigned int riscv_hard_regno_nregs ( int regno , enum machine_mode mode ) { if ( FP_REG_P ( regno ) ) return ( GET_MODE_SIZE ( mode ) + UNITS_PER_FP_REG - 1 ) / UNITS_PER_FP_REG ; return ( GET_MODE_SIZE ( mode ) + UNITS_PER_WORD - 1 ) / UNITS_PER_WORD ; } </s>


This pass may be implemented by targets that want to run passes immediately before machine code is emitted .

WebAssembly WebAssembly WebAssembly WebAssembly WebAssembly WebAssembly WebAssembly


<s> bool mayLoad ( ) const { return ( Load ) ; } </s>

Return true if this instruction could possibly read memory .


<s>
bool
FPS
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
bool
FPIsUsed
=
false
;
static_assert
(
X86
::
FP6
==
X86
::
FP0
+
6
,
"Register enums aren't sorted right!"
)
;
const
MachineRegisterInfo
&
MRI
=
MF
.
getRegInfo
(
)
;
for
(
unsigned
i
=
0
;
i
<=
6
;
++
i
)
if
(
!
MRI
.
reg_nodbg_empty
(
X86
::
FP0
+
i
)
)
{
FPIsUsed
=
true
;
break
;
}
if
(
!
FPIsUsed
)
return
false
;
Bundles
=
&
getAnalysis
<
EdgeBundles
>
(
)
;
TII
=
MF
.
getSubtarget
(
)
.
getInstrInfo
(
)
;
bundleCFG
(
MF
)
;
StackTop
=
0
;
SmallPtrSet
<
MachineBasicBlock
*
,
8
>
Processed
;
MachineBasicBlock
*
Entry
=
&
MF
.
front
(
)
;
bool
Changed
=
false
;
for
(
MachineBasicBlock
*
BB
:
depth_first_ext
(
Entry
,
Processed
)
)
Changed
|=
processBasicBlock
(
MF
,
*
BB
)
;
if
(
MF
.
size
(
)
!=
Processed
.
size
(
)
)
for
(
MachineBasicBlock
&
BB
:
MF
)
if
(
Processed
.
insert
(
&
BB
)
.
second
)
Changed
|=
processBasicBlock
(
MF
,
BB
)
;
LiveBundles
.
clear
(
)
;
return
Changed
;
}
</s>

runOnMachineFunction - Emit the function body .


<s> const MCPhysReg * MINA32RegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { return nullptr ; } </s>


<s> int mmix_use_simple_return ( void ) { int regno ; int stack_space_to_allocate = ( current_function_outgoing_args_size + current_function_pretend_args_size + get_frame_size ( ) + 7 ) & ~ 7 ; if ( ! TARGET_USE_RETURN_INSN || ! reload_completed ) return 0 ; for ( regno = 255 ; regno >= MMIX_FIRST_GLOBAL_REGNUM ; regno -- ) if ( ( ( ( regno != MMIX_FRAME_POINTER_REGNUM || ! frame_pointer_needed ) && regs_ever_live [ regno ] && ! call_used_regs [ regno ] ) ) || IS_MMIX_EH_RETURN_DATA_REG ( regno ) ) return 0 ; if ( frame_pointer_needed ) stack_space_to_allocate += 8 ; if ( MMIX_CFUN_HAS_LANDING_PAD ) stack_space_to_allocate += 16 ; else if ( MMIX_CFUN_NEEDS_SAVED_EH_RETURN_ADDRESS ) stack_space_to_allocate += 8 ; return stack_space_to_allocate == 0 ; } </s>

Nonzero when the function epilogue is simple enough that a single `` POP % d,0 '' should be used even within the function .


<s> virtual bool isNoopAddrSpaceCast ( unsigned SrcAS , unsigned DestAS ) const { return true ; } </s>

Returns true if a cast between SrcAS and DestAS is a noop .


<s> int paired_emit_vector_cond_expr ( rtx dest , rtx op1 , rtx op2 , rtx cond , rtx cc_op0 , rtx cc_op1 ) { enum rtx_code rcode = GET_CODE ( cond ) ; if ( ! TARGET_PAIRED_FLOAT ) return 0 ; paired_emit_vector_compare ( rcode , dest , op1 , op2 , cc_op0 , cc_op1 ) ; return 1 ; } </s>

Emit vector conditional expression . DEST is destination . OP1 and OP2 are two VEC_COND_EXPR operands . CC_OP0 and CC_OP1 are the two operands for the relation operation COND .


<s> const predefined_function_abi & ix86_insn_callee_abi ( const rtx_insn * insn ) { unsigned int abi_id = 0 ; rtx pat = PATTERN ( insn ) ; if ( vzeroupper_pattern ( pat , VOIDmode ) ) abi_id = ABI_VZEROUPPER ; return function_abis [ abi_id ] ; } </s>


<s> TargetLoweringBase :: LegalizeTypeAction X86TargetLowering :: getPreferredVectorAction ( MVT VT ) const { if ( ( VT == MVT :: v32i1 || VT == MVT :: v64i1 ) && Subtarget . hasAVX512 ( ) && ! Subtarget . hasBWI ( ) ) return TypeSplitVector ; if ( VT . getVectorNumElements ( ) != 1 && VT . getVectorElementType ( ) != MVT :: i1 ) return TypeWidenVector ; return TargetLoweringBase :: getPreferredVectorAction ( VT ) ; } </s>

Customize the preferred legalization strategy for certain types .


<s> static machine_mode avr_addr_space_pointer_mode ( addr_space_t as ) { return avr_addr_space_address_mode ( as ) ; } </s>

Implement ` TARGET_ADDR_SPACE_POINTER_MODE ' .


<s> const uint16_t * SparcRegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { static const uint16_t CalleeSavedRegs [ ] = { 0 } ; return CalleeSavedRegs ; } </s>


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . addRequired < LiveIntervals > ( ) ; AU . addRequired < MachinePostDominatorTree > ( ) ; AU . setPreservesCFG ( ) ; AU . addPreserved < LiveIntervals > ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> const ARMSubtarget * ARMBaseTargetMachine :: getSubtargetImpl ( const Function & F ) const { AttributeSet FnAttrs = F . getAttributes ( ) ; Attribute CPUAttr = FnAttrs . getAttribute ( AttributeSet :: FunctionIndex , "target-cpu" ) ; Attribute FSAttr = FnAttrs . getAttribute ( AttributeSet :: FunctionIndex , "target-features" ) ; std :: string CPU = ! CPUAttr . hasAttribute ( Attribute :: None ) ? CPUAttr . getValueAsString ( ) . str ( ) : TargetCPU ; std :: string FS = ! FSAttr . hasAttribute ( Attribute :: None ) ? FSAttr . getValueAsString ( ) . str ( ) : TargetFS ; Attribute SFAttr = FnAttrs . getAttribute ( AttributeSet :: FunctionIndex , "use-soft-float" ) ; bool SoftFloat = ! SFAttr . hasAttribute ( Attribute :: None ) ? SFAttr . getValueAsString ( ) == "true" : Options . UseSoftFloat ; auto & I = SubtargetMap [ CPU + FS + ( SoftFloat ? "use-soft-float=true" : "use-soft-float=false" ) ] ; if ( ! I ) { resetTargetOptions ( F ) ; I = llvm :: make_unique < ARMSubtarget > ( TargetTriple , CPU , FS , * this , isLittle ) ; } return I . get ( ) ; } </s>

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .

ARM ARM ARM "target-cpu" "target-features" "use-soft-float" "true" "use-soft-float=true" "use-soft-float=false" ARM


<s> static bool aarch64_needs_frame_chain ( void ) { if ( frame_pointer_needed || crtl -> calls_eh_return ) return true ; bool is_leaf = crtl -> is_leaf && ! df_regs_ever_live_p ( LR_REGNUM ) ; if ( flag_omit_leaf_frame_pointer && is_leaf ) return false ; return aarch64_use_frame_pointer ; } </s>

Determine whether a frame chain needs to be generated .


<s> bool mips_stack_address_p ( rtx x , machine_mode mode ) { struct mips_address_info addr ; return ( mips_classify_address ( & addr , x , mode , false ) && addr . type == ADDRESS_REG && addr . reg == stack_pointer_rtx ) ; } </s>

Return true if X is a legitimate $ sp-based address for mode MDOE .


<s> static rtx ix86_expand_sse_ptest ( const struct builtin_description * d , tree exp , rtx target ) { rtx pat ; tree arg0 = CALL_EXPR_ARG ( exp , 0 ) ; tree arg1 = CALL_EXPR_ARG ( exp , 1 ) ; rtx op0 = expand_normal ( arg0 ) ; rtx op1 = expand_normal ( arg1 ) ; machine_mode mode0 = insn_data [ d -> icode ] . operand [ 0 ] . mode ; machine_mode mode1 = insn_data [ d -> icode ] . operand [ 1 ] . mode ; enum rtx_code comparison = d -> comparison ; if ( VECTOR_MODE_P ( mode0 ) ) op0 = safe_vector_operand ( op0 , mode0 ) ; if ( VECTOR_MODE_P ( mode1 ) ) op1 = safe_vector_operand ( op1 , mode1 ) ; target = gen_reg_rtx ( SImode ) ; emit_move_insn ( target , const0_rtx ) ; target = gen_rtx_SUBREG ( QImode , target , 0 ) ; if ( ( optimize && ! register_operand ( op0 , mode0 ) ) || ! insn_data [ d -> icode ] . operand [ 0 ] . predicate ( op0 , mode0 ) ) op0 = copy_to_mode_reg ( mode0 , op0 ) ; if ( ( optimize && ! register_operand ( op1 , mode1 ) ) || ! insn_data [ d -> icode ] . operand [ 1 ] . predicate ( op1 , mode1 ) ) op1 = copy_to_mode_reg ( mode1 , op1 ) ; pat = GEN_FCN ( d -> icode ) ( op0 , op1 ) ; if ( ! pat ) return 0 ; emit_insn ( pat ) ; emit_insn ( gen_rtx_SET ( gen_rtx_STRICT_LOW_PART ( VOIDmode , target ) , gen_rtx_fmt_ee ( comparison , QImode , SET_DEST ( pat ) , const0_rtx ) ) ) ; return SUBREG_REG ( target ) ; } </s>

Subroutine of ix86_expand_builtin to take care of ptest insns .


<s> bool AArch64TargetLowering :: isFMAFasterThanFMulAndFAdd ( const MachineFunction & MF , EVT VT ) const { VT = VT . getScalarType ( ) ; if ( ! VT . isSimple ( ) ) return false ; switch ( VT . getSimpleVT ( ) . SimpleTy ) { case MVT :: f32 : case MVT :: f64 : return true ; default : break ; } return false ; } </s>

Return true if an FMA operation is faster than a pair of fmul and fadd instructions .


<s> bool SIWholeQuadMode :: runOnMachineFunction ( MachineFunction & MF ) { Instructions . clear ( ) ; Blocks . clear ( ) ; LiveMaskQueries . clear ( ) ; LowerToCopyInstrs . clear ( ) ; CallingConv = MF . getFunction ( ) . getCallingConv ( ) ; const GCNSubtarget & ST = MF . getSubtarget < GCNSubtarget > ( ) ; TII = ST . getInstrInfo ( ) ; TRI = & TII -> getRegisterInfo ( ) ; MRI = & MF . getRegInfo ( ) ; LIS = & getAnalysis < LiveIntervals > ( ) ; char GlobalFlags = analyzeFunction ( MF ) ; unsigned LiveMaskReg = 0 ; if ( ! ( GlobalFlags & StateWQM ) ) { lowerLiveMaskQueries ( AMDGPU :: EXEC ) ; if ( ! ( GlobalFlags & StateWWM ) ) return ! LiveMaskQueries . empty ( ) ; } else { MachineBasicBlock & Entry = MF . front ( ) ; MachineBasicBlock :: iterator EntryMI = Entry . getFirstNonPHI ( ) ; if ( GlobalFlags & StateExact || ! LiveMaskQueries . empty ( ) ) { LiveMaskReg = MRI -> createVirtualRegister ( & AMDGPU :: SReg_64RegClass ) ; MachineInstr * MI = BuildMI ( Entry , EntryMI , DebugLoc ( ) , TII -> get ( AMDGPU :: COPY ) , LiveMaskReg ) . addReg ( AMDGPU :: EXEC ) ; LIS -> InsertMachineInstrInMaps ( * MI ) ; } lowerLiveMaskQueries ( LiveMaskReg ) ; if ( GlobalFlags == StateWQM ) { BuildMI ( Entry , EntryMI , DebugLoc ( ) , TII -> get ( AMDGPU :: S_WQM_B64 ) , AMDGPU :: EXEC ) . addReg ( AMDGPU :: EXEC ) ; lowerCopyInstrs ( ) ; return true ; } } LLVM_DEBUG ( printInfo ( ) ) ; lowerCopyInstrs ( ) ; for ( auto BII : Blocks ) processBlock ( * BII . first , LiveMaskReg , BII . first == & * MF . begin ( ) ) ; LIS -> removeRegUnit ( * MCRegUnitIterator ( AMDGPU :: SCC , TRI ) ) ; return true ; } </s>

AMDGPU SI 0 AMDGPU::EXEC AMDGPU::SReg_64RegClass AMDGPU::COPY AMDGPU::EXEC AMDGPU::S_WQM_B64 AMDGPU::EXEC AMDGPU::EXEC AMDGPU::SCC


<s>
void
MipsInstrInfo
::
storeRegToStackSlot
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
unsigned
SrcReg
,
bool
isKill
,
int
FI
,
const
TargetRegisterClass
*
RC
)
const
{
DebugLoc
DL
=
DebugLoc
::
getUnknownLoc
(
)
;
if
(
I
!=
MBB
.
end
(
)
)
DL
=
I
->
getDebugLoc
(
)
;
if
(
RC
==
Mips
::
CPURegsRegisterClass
)
BuildMI
(
MBB
,
I
,
DL
,
get
(
Mips
::
SW
)
)
.
addReg
(
SrcReg
,
getKillRegState
(
isKill
)
)
.
addImm
(
0
)
.
addFrameIndex
(
FI
)
;
else
if
(
RC
==
Mips
::
FGR32RegisterClass
)
BuildMI
(
MBB
,
I
,
DL
,
get
(
Mips
::
SWC1
)
)
.
addReg
(
SrcReg
,
getKillRegState
(
isKill
)
)
.
addImm
(
0
)
.
addFrameIndex
(
FI
)
;
else
if
(
RC
==
Mips
::
AFGR64RegisterClass
)
{
if
(
!
TM
.
getSubtarget
<
MipsSubtarget
>
(
)
.
isMips1
(
)
)
{
BuildMI
(
MBB
,
I
,
DL
,
get
(
Mips
::
SDC1
)
)
.
addReg
(
SrcReg
,
getKillRegState
(
isKill
)
)
.
addImm
(
0
)
.
addFrameIndex
(
FI
)
;
}
else
{
const
TargetRegisterInfo
*
TRI
=
MBB
.
getParent
(
)
->
getTarget
(
)
.
getRegisterInfo
(
)
;
const
unsigned
*
SubSet
=
TRI
->
getSubRegisters
(
SrcReg
)
;
BuildMI
(
MBB
,
I
,
DL
,
get
(
Mips
::
SWC1
)
)
.
addReg
(
SubSet
[
0
]
,
getKillRegState
(
isKill
)
)
.
addImm
(
0
)
.
addFrameIndex
(
FI
)
;
BuildMI
(
MBB
,
I
,
DL
,
get
(
Mips
::
SWC1
)
)
.
addReg
(
SubSet
[
1
]
,
getKillRegState
(
isKill
)
)
.
addImm
(
4
)
.
addFrameIndex
(
FI
)
;
}
}
else
llvm_unreachable
(
"Register class not handled!"
)
;
}
</s>

Store the specified register of the given register class to the specified stack frame index .


<s> static bool arm_return_in_msb ( tree valtype ) { return ( TARGET_AAPCS_BASED && BYTES_BIG_ENDIAN && ( AGGREGATE_TYPE_P ( valtype ) || TREE_CODE ( valtype ) == COMPLEX_TYPE ) ) ; } </s>

Values which must be returned in the most-significant end of the return register .


<s> bool X86TTIImpl :: isLSRCostLess ( TargetTransformInfo :: LSRCost & C1 , TargetTransformInfo :: LSRCost & C2 ) { return std :: tie ( C1 . Insns , C1 . NumRegs , C1 . AddRecCost , C1 . NumIVMuls , C1 . NumBaseAdds , C1 . ScaleCost , C1 . ImmCost , C1 . SetupCost ) < std :: tie ( C2 . Insns , C2 . NumRegs , C2 . AddRecCost , C2 . NumIVMuls , C2 . NumBaseAdds , C2 . ScaleCost , C2 . ImmCost , C2 . SetupCost ) ; } </s>

Return true if LSR cost of C1 is lower than C2 .


<s> bool runOnModule ( Module & M ) override { UsedList = getUsedList ( M ) ; bool Changed = superAlignLDSGlobals ( M ) ; Changed |= processUsedLDS ( M ) ; for ( Function & F : M . functions ( ) ) { if ( F . isDeclaration ( ) ) continue ; if ( ! AMDGPU :: isKernel ( F . getCallingConv ( ) ) ) continue ; Changed |= processUsedLDS ( M , & F ) ; } UsedList . clear ( ) ; return Changed ; } </s>

runOnModule - Virtual method overriden by subclasses to process the module being operated on .


<s> bool X86TargetLowering :: areJTsAllowed ( const Function * Fn ) const { if ( Subtarget . useRetpoline ( ) ) return false ; return TargetLowering :: areJTsAllowed ( Fn ) ; } </s>

Returns true if lowering to a jump table is allowed .


<s> void X86RegisterInfo :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { const TargetFrameLowering * TFI = MF . getTarget ( ) . getFrameLowering ( ) ; bool reseveCallFrame = TFI -> hasReservedCallFrame ( MF ) ; int Opcode = I -> getOpcode ( ) ; bool isDestroy = Opcode == TII . getCallFrameDestroyOpcode ( ) ; DebugLoc DL = I -> getDebugLoc ( ) ; uint64_t Amount = ! reseveCallFrame ? I -> getOperand ( 0 ) . getImm ( ) : 0 ; uint64_t CalleeAmt = isDestroy ? I -> getOperand ( 1 ) . getImm ( ) : 0 ; I = MBB . erase ( I ) ; if ( ! reseveCallFrame ) { if ( Amount == 0 ) return ; unsigned StackAlign = TM . getFrameLowering ( ) -> getStackAlignment ( ) ; Amount = ( Amount + StackAlign - 1 ) / StackAlign * StackAlign ; MachineInstr * New = 0 ; if ( Opcode == TII . getCallFrameSetupOpcode ( ) ) { New = BuildMI ( MF , DL , TII . get ( getSUBriOpcode ( Is64Bit , Amount ) ) , StackPtr ) . addReg ( StackPtr ) . addImm ( Amount ) ; } else { assert ( Opcode == TII . getCallFrameDestroyOpcode ( ) ) ; Amount -= CalleeAmt ; if ( Amount ) { unsigned Opc = getADDriOpcode ( Is64Bit , Amount ) ; New = BuildMI ( MF , DL , TII . get ( Opc ) , StackPtr ) . addReg ( StackPtr ) . addImm ( Amount ) ; } } if ( New ) { New -> getOperand ( 3 ) . setIsDead ( ) ; MBB . insert ( I , New ) ; } return ; } if ( Opcode == TII . getCallFrameDestroyOpcode ( ) && CalleeAmt ) { unsigned Opc = getSUBriOpcode ( Is64Bit , CalleeAmt ) ; MachineInstr * New = BuildMI ( MF , DL , TII . get ( Opc ) , StackPtr ) . addReg ( StackPtr ) . addImm ( CalleeAmt ) ; New -> getOperand ( 3 ) . setIsDead ( ) ; MachineBasicBlock :: iterator B = MBB . begin ( ) ; while ( I != B && ! llvm :: prior ( I ) -> isCall ( ) ) -- I ; MBB . insert ( I , New ) ; } } </s>

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .


<s> bool MipsFrameLowering :: hasFP ( const MachineFunction & MF ) const { const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const TargetRegisterInfo * TRI = STI . getRegisterInfo ( ) ; return MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) || MFI . hasVarSizedObjects ( ) || MFI . isFrameAddressTaken ( ) || TRI -> hasStackRealignment ( MF ) ; } </s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .


<s> static void addarg ( const char * str ) { if ( ++ lib_arg_index >= lib_arg_max ) { lib_arg_max += 1000 ; lib_args = XRESIZEVEC ( const char * , lib_args , lib_arg_max ) ; } lib_args [ lib_arg_index ] = str ; } </s>

Append STR to the command line to invoke the linker . Expand the line as necessary to accommodate .


For most targets , an LLVM type must be broken down into multiple smaller types .


<s> unsigned int compute_a_shift_length ( rtx insn ATTRIBUTE_UNUSED , rtx * operands ) { rtx shift = operands [ 3 ] ; machine_mode mode = GET_MODE ( shift ) ; enum rtx_code code = GET_CODE ( shift ) ; enum shift_type shift_type ; enum shift_mode shift_mode ; struct shift_info info ; unsigned int wlength = 0 ; switch ( mode ) { case E_QImode : shift_mode = QIshift ; break ; case E_HImode : shift_mode = HIshift ; break ; case E_SImode : shift_mode = SIshift ; break ; default : gcc_unreachable ( ) ; } switch ( code ) { case ASHIFTRT : shift_type = SHIFT_ASHIFTRT ; break ; case LSHIFTRT : shift_type = SHIFT_LSHIFTRT ; break ; case ASHIFT : shift_type = SHIFT_ASHIFT ; break ; default : gcc_unreachable ( ) ; } if ( GET_CODE ( operands [ 2 ] ) != CONST_INT ) { get_shift_alg ( shift_type , shift_mode , 1 , & info ) ; return ( 4 + h8300_asm_insn_count ( info . shift1 ) ) * 2 ; } else { int n = INTVAL ( operands [ 2 ] ) ; if ( n < 0 ) n = 0 ; else if ( ( unsigned int ) n > GET_MODE_BITSIZE ( mode ) ) n = GET_MODE_BITSIZE ( mode ) ; get_shift_alg ( shift_type , shift_mode , n , & info ) ; switch ( info . alg ) { case SHIFT_SPECIAL : wlength += h8300_asm_insn_count ( info . special ) ; if ( strstr ( info . special , "xor.l" ) != NULL ) wlength ++ ; case SHIFT_INLINE : n = info . remainder ; if ( info . shift2 != NULL ) { wlength += h8300_asm_insn_count ( info . shift2 ) * ( n / 2 ) ; n = n % 2 ; } wlength += h8300_asm_insn_count ( info . shift1 ) * n ; return 2 * wlength ; case SHIFT_ROT_AND : { int m = GET_MODE_BITSIZE ( mode ) - n ; gcc_assert ( info . shift1 ) ; if ( info . shift2 != NULL ) { wlength += h8300_asm_insn_count ( info . shift2 ) * ( m / 2 ) ; m = m % 2 ; } wlength += h8300_asm_insn_count ( info . shift1 ) * m ; switch ( mode ) { case E_QImode : wlength += 1 ; break ; case E_HImode : wlength += 2 ; break ; case E_SImode : wlength += 3 ; break ; default : gcc_unreachable ( ) ; } return 2 * wlength ; } case SHIFT_LOOP : if ( info . shift2 != NULL ) { wlength += 3 + h8300_asm_insn_count ( info . shift2 ) ; if ( n % 2 ) wlength += h8300_asm_insn_count ( info . shift1 ) ; } else { wlength += 3 + h8300_asm_insn_count ( info . shift1 ) ; } return 2 * wlength ; default : gcc_unreachable ( ) ; } } } </s>


"Second offset should be larger than first offset!"

shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to determine ( in conjunction with areLoadsFromSameBasePtr ) if two loads should be scheduled togther .


<s> const RISCVMCExpr * RISCVMCExpr :: create ( const MCExpr * Expr , VariantKind Kind , MCContext & Ctx ) { return new ( Ctx ) RISCVMCExpr ( Expr , Kind ) ; } </s>


<s> TargetIRAnalysis AMDGPUTargetMachine :: getTargetIRAnalysis ( ) { return TargetIRAnalysis ( [ this ] ( const Function & F ) { return TargetTransformInfo ( AMDGPUTTIImpl ( this , F ) ) ; } ) ; } </s>

Get a TargetIRAnalysis appropriate for the target .


<s>
VE
::
Fixups
VEMCExpr
::
getFixupKind
(
VEMCExpr
::
VariantKind
Kind
)
{
switch
(
Kind
)
{
default
:
llvm_unreachable
(
"Unhandled VEMCExpr::VariantKind"
)
;
case
VK_VE_HI32
:
return
VE
::
fixup_ve_hi32
;
case
VK_VE_LO32
:
return
VE
::
fixup_ve_lo32
;
case
VK_VE_PC_HI32
:
return
VE
::
fixup_ve_pc_hi32
;
case
VK_VE_PC_LO32
:
return
VE
::
fixup_ve_pc_lo32
;
case
VK_VE_GOT_HI32
:
return
VE
::
fixup_ve_got_hi32
;
case
VK_VE_GOT_LO32
:
return
VE
::
fixup_ve_got_lo32
;
case
VK_VE_GOTOFF_HI32
:
return
VE
::
fixup_ve_gotoff_hi32
;
case
VK_VE_GOTOFF_LO32
:
return
VE
::
fixup_ve_gotoff_lo32
;
case
VK_VE_PLT_HI32
:
return
VE
::
fixup_ve_plt_hi32
;
case
VK_VE_PLT_LO32
:
return
VE
::
fixup_ve_plt_lo32
;
}
}
</s>

getFixupKind - Get the fixup kind of this expression .


<s> static rtx cris_function_incoming_arg ( cumulative_args_t ca , const function_arg_info & arg ) { return cris_function_arg_1 ( ca , arg , true ) ; } </s>

Worker function for TARGET_FUNCTION_INCOMING_ARG . The differences between this and the previous , is that this one checks that an argument is named , since incoming stdarg/varargs arguments are pushed onto the stack , and we do n't have to check against the `` closing '' void_type_node TYPE parameter .


"rs6000_builtin_md_vectorized_function (%s, %s, %s)\n"


<s> bool X86TargetMachine :: addPreRegAlloc ( PassManagerBase & PM ) { PM . add ( createX86MaxStackAlignmentHeuristicPass ( ) ) ; return false ; } </s>

This method may be implemented by targets that want to run passes immediately before register allocation .


<s> const MCExpr * WebAssemblyAsmPrinter :: lowerConstant ( const Constant * CV ) { if ( const GlobalValue * GV = dyn_cast < GlobalValue > ( CV ) ) if ( GV -> getValueType ( ) -> isFunctionTy ( ) ) { return MCSymbolRefExpr :: create ( getSymbol ( GV ) , MCSymbolRefExpr :: VK_WebAssembly_FUNCTION , OutContext ) ; } return AsmPrinter :: lowerConstant ( CV ) ; } </s>

Lower the specified LLVM Constant to an MCExpr .


<s> rtx gen_pop ( rtx operand0 , enum machine_mode mode ) { return gen_rtx_SET ( VOIDmode , operand0 , gen_rtx_MEM ( mode , gen_rtx_POST_INC ( mode , gen_rtx_REG ( Pmode , STACK_POINTER_REGNUM ) ) ) ) ; } </s>

Generate an `` pop '' pattern for input ARG .


<s> StringRef getPassName ( ) const override { return "MOSCombiner" ; } </s>

getPassName - Return a nice clean name for a pass .


<s> int rs6000_loop_align ( rtx label ) { basic_block bb ; int ninsns ; if ( ! can_override_loop_align ) return align_loops_log ; bb = BLOCK_FOR_INSN ( label ) ; ninsns = num_loop_insns ( bb -> loop_father ) ; if ( ninsns > 4 && ninsns <= 8 && ( rs6000_tune == PROCESSOR_POWER4 || rs6000_tune == PROCESSOR_POWER5 || rs6000_tune == PROCESSOR_POWER6 || rs6000_tune == PROCESSOR_POWER7 || rs6000_tune == PROCESSOR_POWER8 ) ) return 5 ; else return align_loops_log ; } </s>


<s> rtx gen_mlo ( void ) { return gen_rtx_REG ( SImode , TARGET_BIG_ENDIAN ? 59 : 58 ) ; } </s>

Return a REG rtx for mlo . N.B . the gcc-internal representation may differ from the hardware register number in order to allow the generic code to correctly split the concatenation of mhi and mlo .


<s>
SDValue
PatmosTargetLowering
::
LowerFormalArguments
(
SDValue
Chain
,
CallingConv
::
ID
CallConv
,
bool
isVarArg
,
const
SmallVectorImpl
<
ISD
::
InputArg
>
&
Ins
,
SDLoc
dl
,
SelectionDAG
&
DAG
,
SmallVectorImpl
<
SDValue
>
&
InVals
)
const
{
switch
(
CallConv
)
{
default
:
llvm_unreachable
(
"Unsupported calling convention"
)
;
case
CallingConv
::
C
:
case
CallingConv
::
Fast
:
return
LowerCCCArguments
(
Chain
,
CallConv
,
isVarArg
,
Ins
,
dl
,
DAG
,
InVals
)
;
}
}
</s>

This hook must be implemented to lower the incoming ( formal ) arguments , described by the Ins array , into the specified DAG .

Patmos
Patmos
ISD::InputArg
"Unsupported calling convention"


<s> static bool or1k_cannot_force_const_mem ( machine_mode , rtx x ) { rtx_code code = GET_CODE ( x ) ; return ( code == SYMBOL_REF || code == LABEL_REF || code == CONST || code == HIGH ) ; } </s>

Worker for TARGET_CANNOT_FORCE_CONST_MEM . Primarily this is required for TLS symbols , but given that our move patterns * ought * to be able to handle any symbol at any time , we should never be spilling symbolic operands to the constant pool , ever .


"*** BPF MachineSSA TRUNC Elim peephole pass ***\n\n"

Initialize the strategy after building the DAG for a new region .


<s>
void
assignValueToReg
(
unsigned
ValVReg
,
unsigned
PhysReg
,
CCValAssign
&
VA
)
override
{
assert
(
VA
.
isRegLoc
(
)
&&
"Value shouldn't be assigned to reg"
)
;
assert
(
VA
.
getLocReg
(
)
==
PhysReg
&&
"Assigning to the wrong reg?"
)
;
auto
ValSize
=
VA
.
getValVT
(
)
.
getSizeInBits
(
)
;
auto
LocSize
=
VA
.
getLocVT
(
)
.
getSizeInBits
(
)
;
assert
(
ValSize
<=
64
&&
"Unsupported value size"
)
;
assert
(
LocSize
<=
64
&&
"Unsupported location size"
)
;
markPhysRegUsed
(
PhysReg
)
;
if
(
ValSize
==
LocSize
)
{
MIRBuilder
.
buildCopy
(
ValVReg
,
PhysReg
)
;
}
else
{
assert
(
ValSize
<
LocSize
&&
"Extensions not supported"
)
;
auto
PhysRegToVReg
=
MRI
.
createGenericVirtualRegister
(
LLT
::
scalar
(
LocSize
)
)
;
MIRBuilder
.
buildCopy
(
PhysRegToVReg
,
PhysReg
)
;
MIRBuilder
.
buildTrunc
(
ValVReg
,
PhysRegToVReg
)
;
}
}
</s>

The specified value has been assigned to a physical register , handle the appropriate COPY ( either to or from ) and mark any relevant uses/defines as needed .

ARM
"Value shouldn't be assigned to reg"
"Assigning to the wrong reg?"
64
"Unsupported value size"
64
"Unsupported location size"
"Extensions not supported"


<s> int long_immediate_loadstore_operand ( rtx op , enum machine_mode mode ATTRIBUTE_UNUSED ) { if ( GET_CODE ( op ) != MEM ) return 0 ; op = XEXP ( op , 0 ) ; switch ( GET_CODE ( op ) ) { case SYMBOL_REF : case LABEL_REF : case CONST : return 1 ; case CONST_INT : return 1 ; case CONST_DOUBLE : return 1 ; case REG : return 0 ; case PLUS : if ( GET_CODE ( XEXP ( op , 1 ) ) == CONST_INT && ! SMALL_INT ( INTVAL ( XEXP ( op , 1 ) ) ) ) return 1 ; return 0 ; default : break ; } return 0 ; } </s>

Return true if OP is a MEM that when used as a load or store address will require an 8 byte insn . Load and store instructions do n't allow the same possibilities but they 're similar enough that this one function will do . This is currently only used when calculating length attributes .


<s> static bool r10k_needs_protection_p_call ( const_rtx x ) { subrtx_iterator :: array_type array ; FOR_EACH_SUBRTX ( iter , array , x , NONCONST ) { const_rtx mem = * iter ; if ( MEM_P ( mem ) ) { const_rtx addr = XEXP ( mem , 0 ) ; if ( GET_CODE ( addr ) == SYMBOL_REF && SYMBOL_REF_DECL ( addr ) ) iter . skip_subrtxes ( ) ; else return true ; } } return false ; } </s>

X is the pattern of a call instruction . Return true if the call is not to a declared function .


<s> static bool f_constraint_p ( const char * constraint ) { bool seen_f_p = false ; bool seen_v_p = false ; for ( size_t i = 0 , c_len = strlen ( constraint ) ; i < c_len ; i += CONSTRAINT_LEN ( constraint [ i ] , constraint + i ) ) { if ( constraint [ i ] == 'f' ) seen_f_p = true ; if ( constraint [ i ] == 'v' ) seen_v_p = true ; } return seen_f_p && ! seen_v_p ; } </s>

Return TRUE iff CONSTRAINT is an `` f '' constraint , possibly with additional modifiers .


<s> bool isAliased ( const MachineFrameInfo * ) const override { return true ; } </s>

Test whether the memory pointed to by this PseudoSourceValue may also be pointed to by an LLVM IR Value .


<s> static int pru_function_arg_size ( machine_mode mode , const_tree type ) { HOST_WIDE_INT param_size ; if ( mode == BLKmode ) param_size = int_size_in_bytes ( type ) ; else param_size = GET_MODE_SIZE ( mode ) ; param_size = ( UNITS_PER_WORD - 1 + param_size ) / UNITS_PER_WORD ; gcc_assert ( param_size >= 0 ) ; return param_size ; } </s>

Return the number of bytes needed for storing an argument with the given MODE and TYPE .


<s> unsigned count ( ) const { return Bits . count ( ) ; } </s>

Return 1 if the specified key is in the map , 0 otherwise .


<s>
static
bool
alpha_handle_option
(
size_t
code
,
const
char
*
arg
,
int
value
)
{
switch
(
code
)
{
case
OPT_mfp_regs
:
if
(
value
==
0
)
target_flags
|=
MASK_SOFT_FP
;
break
;
case
OPT_mieee
:
case
OPT_mieee_with_inexact
:
target_flags
|=
MASK_IEEE_CONFORMANT
;
break
;
case
OPT_mtls_size_
:
if
(
value
!=
16
&&
value
!=
32
&&
value
!=
64
)
error
(
"bad value %qs for -mtls-size switch"
,
arg
)
;
break
;
}
return
true
;
}
</s>


<s> bool AMDGPUUnifyDivergentExitNodes :: runOnFunction ( Function & F ) { auto & PDT = getAnalysis < PostDominatorTreeWrapperPass > ( ) . getPostDomTree ( ) ; if ( PDT . getRoots ( ) . size ( ) <= 1 ) return false ; DivergenceAnalysis & DA = getAnalysis < DivergenceAnalysis > ( ) ; SmallVector < BasicBlock * , 4 > ReturningBlocks ; SmallVector < BasicBlock * , 4 > UnreachableBlocks ; for ( BasicBlock * BB : PDT . getRoots ( ) ) { if ( isa < ReturnInst > ( BB -> getTerminator ( ) ) ) { if ( ! isUniformlyReached ( DA , * BB ) ) ReturningBlocks . push_back ( BB ) ; } else if ( isa < UnreachableInst > ( BB -> getTerminator ( ) ) ) { if ( ! isUniformlyReached ( DA , * BB ) ) UnreachableBlocks . push_back ( BB ) ; } } if ( ! UnreachableBlocks . empty ( ) ) { BasicBlock * UnreachableBlock = nullptr ; if ( UnreachableBlocks . size ( ) == 1 ) { UnreachableBlock = UnreachableBlocks . front ( ) ; } else { UnreachableBlock = BasicBlock :: Create ( F . getContext ( ) , "UnifiedUnreachableBlock" , & F ) ; new UnreachableInst ( F . getContext ( ) , UnreachableBlock ) ; for ( BasicBlock * BB : UnreachableBlocks ) { BB -> getInstList ( ) . pop_back ( ) ; BranchInst :: Create ( UnreachableBlock , BB ) ; } } if ( ! ReturningBlocks . empty ( ) ) { Type * RetTy = F . getReturnType ( ) ; Value * RetVal = RetTy -> isVoidTy ( ) ? nullptr : UndefValue :: get ( RetTy ) ; UnreachableBlock -> getInstList ( ) . pop_back ( ) ; Function * UnreachableIntrin = Intrinsic :: getDeclaration ( F . getParent ( ) , Intrinsic :: amdgcn_unreachable ) ; CallInst :: Create ( UnreachableIntrin , { } , "" , UnreachableBlock ) ; ReturnInst :: Create ( F . getContext ( ) , RetVal , UnreachableBlock ) ; ReturningBlocks . push_back ( UnreachableBlock ) ; } } if ( ReturningBlocks . empty ( ) ) return false ; if ( ReturningBlocks . size ( ) == 1 ) return false ; const TargetTransformInfo & TTI = getAnalysis < TargetTransformInfoWrapperPass > ( ) . getTTI ( F ) ; unifyReturnBlockSet ( F , ReturningBlocks , TTI , "UnifiedReturnBlock" ) ; return true ; } </s>

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .


"AAAMDFlatWorkGroupSize is only valid for function position"

Create an abstract attribute view for the position IRP .


"Can only put epilog before 'ret' instruction!"

"Unimplemented - per function stack size limited to 32767 bytes."


<s> bool aarch64_can_tag_addresses ( ) { return ! TARGET_ILP32 ; } </s>

Implement TARGET_MEMTAG_CAN_TAG_ADDRESSES . Here we tell the rest of the compiler that we automatically ignore the top byte of our pointers , which allows using -fsanitize=hwaddress .


<s> const MCExpr * getSubExpr ( ) const { return Expr ; } </s>

getSubExpr - Get the child of this expression .


<s> static rtx nvptx_gen_shuffle ( rtx dst , rtx src , rtx idx , nvptx_shuffle_kind kind ) { rtx res ; switch ( GET_MODE ( dst ) ) { case SImode : res = gen_nvptx_shufflesi ( dst , src , idx , GEN_INT ( kind ) ) ; break ; case SFmode : res = gen_nvptx_shufflesf ( dst , src , idx , GEN_INT ( kind ) ) ; break ; case DImode : case DFmode : { rtx tmp0 = gen_reg_rtx ( SImode ) ; rtx tmp1 = gen_reg_rtx ( SImode ) ; start_sequence ( ) ; emit_insn ( nvptx_gen_unpack ( tmp0 , tmp1 , src ) ) ; emit_insn ( nvptx_gen_shuffle ( tmp0 , tmp0 , idx , kind ) ) ; emit_insn ( nvptx_gen_shuffle ( tmp1 , tmp1 , idx , kind ) ) ; emit_insn ( nvptx_gen_pack ( dst , tmp0 , tmp1 ) ) ; res = get_insns ( ) ; end_sequence ( ) ; } break ; case BImode : { rtx tmp = gen_reg_rtx ( SImode ) ; start_sequence ( ) ; emit_insn ( gen_sel_truesi ( tmp , src , GEN_INT ( 1 ) , const0_rtx ) ) ; emit_insn ( nvptx_gen_shuffle ( tmp , tmp , idx , kind ) ) ; emit_insn ( gen_rtx_SET ( dst , gen_rtx_NE ( BImode , tmp , const0_rtx ) ) ) ; res = get_insns ( ) ; end_sequence ( ) ; } break ; case QImode : case HImode : { rtx tmp = gen_reg_rtx ( SImode ) ; start_sequence ( ) ; emit_insn ( gen_rtx_SET ( tmp , gen_rtx_fmt_e ( ZERO_EXTEND , SImode , src ) ) ) ; emit_insn ( nvptx_gen_shuffle ( tmp , tmp , idx , kind ) ) ; emit_insn ( gen_rtx_SET ( dst , gen_rtx_fmt_e ( TRUNCATE , GET_MODE ( dst ) , tmp ) ) ) ; res = get_insns ( ) ; end_sequence ( ) ; } break ; default : gcc_unreachable ( ) ; } return res ; } </s>

Generate an instruction or sequence to broadcast register REG across the vectors of a single warp .


<s> Register PPCRegisterInfo :: materializeFrameBaseRegister ( MachineBasicBlock * MBB , int FrameIdx , int64_t Offset ) const { unsigned ADDriOpc = TM . isPPC64 ( ) ? PPC :: ADDI8 : PPC :: ADDI ; MachineBasicBlock :: iterator Ins = MBB -> begin ( ) ; DebugLoc DL ; if ( Ins != MBB -> end ( ) ) DL = Ins -> getDebugLoc ( ) ; const MachineFunction & MF = * MBB -> getParent ( ) ; const PPCSubtarget & Subtarget = MF . getSubtarget < PPCSubtarget > ( ) ; const TargetInstrInfo & TII = * Subtarget . getInstrInfo ( ) ; const MCInstrDesc & MCID = TII . get ( ADDriOpc ) ; MachineRegisterInfo & MRI = MBB -> getParent ( ) -> getRegInfo ( ) ; const TargetRegisterClass * RC = getPointerRegClass ( MF ) ; Register BaseReg = MRI . createVirtualRegister ( RC ) ; MRI . constrainRegClass ( BaseReg , TII . getRegClass ( MCID , 0 , this , MF ) ) ; BuildMI ( * MBB , Ins , DL , MCID , BaseReg ) . addFrameIndex ( FrameIdx ) . addImm ( Offset ) ; return BaseReg ; } </s>

Insert defining instruction ( s ) for a pointer to FrameIdx before insertion point I .

PowerPC PPC PPC PPC::ADDI8 PPC::ADDI PPC PPC 0


"non-standard ABI extension with no compatibility guarantee"

Return a nonzero value to say to return the function value in memory , just as large structures are always returned . TYPE will be the data type of the value , and FNTYPE will be the type of the function doing the returning , or @ code { NULL } for libcalls . The AIX ABI for the RS/6000 specifies that all structures are returned in memory . The Darwin ABI does the same . The SVR4 ABI specifies that structures < = 8 bytes are returned in r3/r4 , but a draft put them in memory , and GCC used to implement the draft instead of the final standard . Therefore , aix_struct_return controls this instead of DEFAULT_ABI ; V.4 targets needing backward compatibility can change DRAFT_V4_STRUCT_RET to override the default , and -m switches get the final word . See rs6000_override_options for more details . The PPC32 SVR4 ABI uses IEEE double extended for long double , if 128-bit long double support is enabled . These values are returned in memory . int_size_in_bytes returns -1 for variable size objects , which go in memory always . The cast to unsigned makes -1 > 8 .


"Unsupported cpu name returned from kernel for -mcpu=native: %s\n"

"Please use an explicit cpu name.  Valid cpu names are: %s"

Returns the canonical AT_PLATFORM if present , otherwise NULL .


<s> bool VETargetLowering :: allowsMisalignedMemoryAccesses ( EVT VT , unsigned AddrSpace , unsigned Align , MachineMemOperand :: Flags , bool * Fast ) const { if ( Fast ) { * Fast = true ; } return true ; } </s>

Returns true if the target allows unaligned memory accesses of the specified type .


<s> static rtx sparc_function_value ( const_tree valtype , const_tree fn_decl_or_type ATTRIBUTE_UNUSED , bool outgoing ) { return sparc_function_value_1 ( valtype , TYPE_MODE ( valtype ) , outgoing ) ; } </s>

Handle TARGET_FUNCTION_VALUE . On the SPARC , the value is found in the first `` output '' register , but the called function leaves it in the first `` input '' register .