<s> static bool aarch64_short_vector_p ( const_tree type , machine_mode mode ) { HOST_WIDE_INT size = - 1 ; if ( type && TREE_CODE ( type ) == VECTOR_TYPE ) size = int_size_in_bytes ( type ) ; else if ( ! aarch64_composite_type_p ( type , mode ) && ( GET_MODE_CLASS ( mode ) == MODE_VECTOR_INT || GET_MODE_CLASS ( mode ) == MODE_VECTOR_FLOAT ) ) size = GET_MODE_SIZE ( mode ) ; return ( size == 8 || size == 16 ) ? true : false ; } </s>

Return TRUE if the type , as described by TYPE and MODE , is a short vector type as described in AAPCS64 \S 4.1.2 . See the comment above aarch64_composite_type_p for the notes on MODE .


<s> static int loongarch_small_data_pattern_1 ( rtx x ) { subrtx_var_iterator :: array_type array ; FOR_EACH_SUBRTX_VAR ( iter , array , x , ALL ) { rtx x = * iter ; if ( GET_CODE ( x ) == ASM_OPERANDS ) iter . skip_subrtxes ( ) ; else if ( MEM_P ( x ) ) { if ( loongarch_small_data_pattern_1 ( XEXP ( x , 0 ) ) ) return true ; iter . skip_subrtxes ( ) ; } } return false ; } </s>

Return true if OP refers to small data symbols directly .


<s>
void
WebAssemblyDAGToDAGISel
::
Select
(
SDNode
*
Node
)
{
if
(
Node
->
isMachineOpcode
(
)
)
{
DEBUG
(
errs
(
)
<<
"== "
;
Node
->
dump
(
CurDAG
)
;
errs
(
)
<<
"\n"
)
;
Node
->
setNodeId
(
1
)
;
return
;
}
EVT
VT
=
Node
->
getValueType
(
0
)
;
switch
(
Node
->
getOpcode
(
)
)
{
default
:
break
;
(
void
)
VT
;
}
SelectCode
(
Node
)
;
}
</s>

Main hook for targets to transform nodes into machine nodes .


<s> ARMSubtarget & ARMSubtarget :: initializeSubtargetDependencies ( StringRef CPU , StringRef FS ) { initializeEnvironment ( ) ; resetSubtargetFeatures ( CPU , FS ) ; return * this ; } </s>

initializeSubtargetDependencies - Initializes using a CPU , a TuneCPU , and feature string so that we can use initializer lists for subtarget initialization .


<s> bool ARMTargetLowering :: SimplifyDemandedBitsForTargetNode ( SDValue Op , const APInt & OriginalDemandedBits , const APInt & OriginalDemandedElts , KnownBits & Known , TargetLoweringOpt & TLO , unsigned Depth ) const { unsigned Opc = Op . getOpcode ( ) ; switch ( Opc ) { case ARMISD :: ASRL : case ARMISD :: LSRL : { if ( Op . getResNo ( ) == 0 && ! Op -> hasAnyUseOfValue ( 1 ) && isa < ConstantSDNode > ( Op -> getOperand ( 2 ) ) ) { unsigned ShAmt = Op -> getConstantOperandVal ( 2 ) ; if ( ShAmt < 32 && OriginalDemandedBits . isSubsetOf ( APInt :: getAllOnes ( 32 ) << ( 32 - ShAmt ) ) ) return TLO . CombineTo ( Op , TLO . DAG . getNode ( ISD :: SHL , SDLoc ( Op ) , MVT :: i32 , Op . getOperand ( 1 ) , TLO . DAG . getConstant ( 32 - ShAmt , SDLoc ( Op ) , MVT :: i32 ) ) ) ; } break ; } } return TargetLowering :: SimplifyDemandedBitsForTargetNode ( Op , OriginalDemandedBits , OriginalDemandedElts , Known , TLO , Depth ) ; } </s>

Attempt to simplify any target nodes based on the demanded bits/elts , returning true on success .


<s> bool X86InstrInfo :: canMakeTailCallConditional ( SmallVectorImpl < MachineOperand > & BranchCond , const MachineInstr & TailCall ) const { if ( TailCall . getOpcode ( ) != X86 :: TCRETURNdi && TailCall . getOpcode ( ) != X86 :: TCRETURNdi64 ) { return false ; } if ( Subtarget . isTargetWin64 ( ) ) { return false ; } assert ( BranchCond . size ( ) == 1 ) ; if ( BranchCond [ 0 ] . getImm ( ) > X86 :: LAST_VALID_COND ) { return false ; } const X86MachineFunctionInfo * X86FI = TailCall . getParent ( ) -> getParent ( ) -> getInfo < X86MachineFunctionInfo > ( ) ; if ( X86FI -> getTCReturnAddrDelta ( ) != 0 || TailCall . getOperand ( 1 ) . getImm ( ) != 0 ) { return false ; } return true ; } </s>

Returns true if the tail call can be made conditional on BranchCond .


<s>
static
void
const_double_split
(
rtx
x
,
HOST_WIDE_INT
*
p_high
,
HOST_WIDE_INT
*
p_low
)
{
if
(
GET_CODE
(
x
)
==
CONST_DOUBLE
)
{
long
t
[
2
]
;
switch
(
GET_MODE
(
x
)
)
{
case
E_DFmode
:
REAL_VALUE_TO_TARGET_DOUBLE
(
*
CONST_DOUBLE_REAL_VALUE
(
x
)
,
t
)
;
*
p_high
=
t
[
1
]
;
*
p_low
=
t
[
0
]
;
return
;
case
E_SFmode
:
REAL_VALUE_TO_TARGET_SINGLE
(
*
CONST_DOUBLE_REAL_VALUE
(
x
)
,
*
p_high
)
;
*
p_low
=
0
;
return
;
case
E_VOIDmode
:
case
E_DImode
:
*
p_high
=
CONST_DOUBLE_HIGH
(
x
)
;
*
p_low
=
CONST_DOUBLE_LOW
(
x
)
;
return
;
default
:
break
;
}
}
fatal_insn
(
"const_double_split got a bad insn:"
,
x
)
;
}
</s>

Return the high and low words of a CONST_DOUBLE


<s>
int
MipsRegisterInfo
::
getDwarfRegNum
(
unsigned
RegNum
,
bool
isEH
)
const
{
assert
(
0
&&
"What is the dwarf register number"
)
;
return
1
;
}
</s>

Map a target register to an equivalent dwarf register number .


<s> BitVector getReservedRegs ( const MachineFunction & MF ) const override { assert ( ! "Unimplemented" ) ; return BitVector ( ) ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s> int avr_epilogue_uses ( int regno ATTRIBUTE_UNUSED ) { if ( reload_completed && cfun -> machine && ( cfun -> machine -> is_interrupt || cfun -> machine -> is_signal ) ) return 1 ; return 0 ; } </s>


<s> bool RISCVTargetLowering :: CanLowerReturn ( CallingConv :: ID CallConv , MachineFunction & MF , bool IsVarArg , const SmallVectorImpl < ISD :: OutputArg > & Outs , LLVMContext & Context ) const { SmallVector < CCValAssign , 16 > RVLocs ; CCState CCInfo ( CallConv , IsVarArg , MF , RVLocs , Context ) ; for ( unsigned i = 0 , e = Outs . size ( ) ; i != e ; ++ i ) { MVT VT = Outs [ i ] . VT ; ISD :: ArgFlagsTy ArgFlags = Outs [ i ] . Flags ; RISCVABI :: ABI ABI = MF . getSubtarget < RISCVSubtarget > ( ) . getTargetABI ( ) ; if ( CC_RISCV ( MF . getDataLayout ( ) , ABI , i , VT , VT , CCValAssign :: Full , ArgFlags , CCInfo , true , true , nullptr ) ) return false ; } return true ; } </s>

This hook should be implemented to check whether the return values described by the Outs array can fit into the return registers .

RISCV RISCV ISD::OutputArg 16 0 ISD::ArgFlagsTy RISCVABI::ABI RISCV RISCV


"Lanai DAG->DAG Pattern Instruction Selection"

getPassName - Return a nice clean name for a pass .


<s> bool SVEIntrinsicOpts :: runOnModule ( Module & M ) { bool Changed = false ; SmallSetVector < Function * , 4 > Functions ; for ( auto & F : M . getFunctionList ( ) ) { if ( ! F . isDeclaration ( ) ) continue ; switch ( F . getIntrinsicID ( ) ) { case Intrinsic :: aarch64_sve_ptrue : for ( User * U : F . users ( ) ) Functions . insert ( cast < Instruction > ( U ) -> getFunction ( ) ) ; break ; default : break ; } } if ( ! Functions . empty ( ) ) Changed |= optimizeFunctions ( Functions ) ; return Changed ; } </s>

runOnModule - Virtual method overriden by subclasses to process the module being operated on .


<s> static rtx gen_pop ( rtx arg ) { if ( REG_P ( arg ) && GET_MODE ( arg ) != word_mode ) arg = gen_rtx_REG ( word_mode , REGNO ( arg ) ) ; return gen_rtx_SET ( VOIDmode , arg , gen_rtx_MEM ( word_mode , gen_rtx_POST_INC ( Pmode , stack_pointer_rtx ) ) ) ; } </s>

Generate an `` pop '' pattern for input ARG .


<s> static void riscv_output_mi_thunk ( FILE * file , tree thunk_fndecl ATTRIBUTE_UNUSED , HOST_WIDE_INT delta , HOST_WIDE_INT vcall_offset , tree function ) { rtx this_rtx , temp1 , temp2 , fnaddr ; rtx_insn * insn ; reload_completed = 1 ; emit_note ( NOTE_INSN_PROLOGUE_END ) ; fnaddr = gen_rtx_MEM ( FUNCTION_MODE , XEXP ( DECL_RTL ( function ) , 0 ) ) ; temp1 = gen_rtx_REG ( Pmode , RISCV_PROLOGUE_TEMP_REGNUM ) ; temp2 = gen_rtx_REG ( Pmode , STATIC_CHAIN_REGNUM ) ; if ( aggregate_value_p ( TREE_TYPE ( TREE_TYPE ( function ) ) , function ) ) this_rtx = gen_rtx_REG ( Pmode , GP_ARG_FIRST + 1 ) ; else this_rtx = gen_rtx_REG ( Pmode , GP_ARG_FIRST ) ; if ( delta != 0 ) { rtx offset = GEN_INT ( delta ) ; if ( ! SMALL_OPERAND ( delta ) ) { riscv_emit_move ( temp1 , offset ) ; offset = temp1 ; } emit_insn ( gen_add3_insn ( this_rtx , this_rtx , offset ) ) ; } if ( vcall_offset != 0 ) { rtx addr ; riscv_emit_move ( temp1 , gen_rtx_MEM ( Pmode , this_rtx ) ) ; addr = riscv_add_offset ( temp2 , temp1 , vcall_offset ) ; riscv_emit_move ( temp1 , gen_rtx_MEM ( Pmode , addr ) ) ; emit_insn ( gen_add3_insn ( this_rtx , this_rtx , temp1 ) ) ; } insn = emit_call_insn ( gen_sibcall ( fnaddr , const0_rtx , NULL , const0_rtx ) ) ; SIBLING_CALL_P ( insn ) = 1 ; insn = get_insns ( ) ; split_all_insns_noflow ( ) ; shorten_branches ( insn ) ; final_start_function ( insn , file , 1 ) ; final ( insn , file , 1 ) ; final_end_function ( ) ; reload_completed = 0 ; } </s>

Implement TARGET_ASM_OUTPUT_MI_THUNK . Generate rtl rather than asm text in order to avoid duplicating too much logic from elsewhere .


<s> SDValue Cpu0TargetLowering :: getTargetNode ( JumpTableSDNode * N , EVT Ty , SelectionDAG & DAG , unsigned Flag ) const { return DAG . getTargetJumpTable ( N -> getIndex ( ) , Ty , Flag ) ; } </s>

Retrieve the target node this edge connects to .


<s>
void
m32r_output_block_move
(
rtx
insn
ATTRIBUTE_UNUSED
,
rtx
operands
[
]
)
{
HOST_WIDE_INT
bytes
=
INTVAL
(
operands
[
2
]
)
;
int
first_time
;
int
got_extra
=
0
;
gcc_assert
(
bytes
>=
1
&&
bytes
<=
MAX_MOVE_BYTES
)
;
first_time
=
1
;
while
(
bytes
>
0
)
{
if
(
bytes
>=
8
)
{
if
(
first_time
)
{
output_asm_insn
(
"ld\t%5, %p1"
,
operands
)
;
output_asm_insn
(
"ld\t%6, %p1"
,
operands
)
;
output_asm_insn
(
"st\t%5, @%0"
,
operands
)
;
output_asm_insn
(
"st\t%6, %s0"
,
operands
)
;
}
else
{
output_asm_insn
(
"ld\t%5, %p1"
,
operands
)
;
output_asm_insn
(
"ld\t%6, %p1"
,
operands
)
;
output_asm_insn
(
"st\t%5, %s0"
,
operands
)
;
output_asm_insn
(
"st\t%6, %s0"
,
operands
)
;
}
bytes
-=
8
;
}
else
if
(
bytes
>=
4
)
{
if
(
bytes
>
4
)
got_extra
=
1
;
output_asm_insn
(
"ld\t%5, %p1"
,
operands
)
;
if
(
got_extra
)
output_asm_insn
(
"ld\t%6, %p1"
,
operands
)
;
if
(
first_time
)
output_asm_insn
(
"st\t%5, @%0"
,
operands
)
;
else
output_asm_insn
(
"st\t%5, %s0"
,
operands
)
;
bytes
-=
4
;
}
else
{
int
dst_offset
=
first_time
0
:
4
;
int
dst_inc_amount
=
dst_offset
+
bytes
4
;
int
src_inc_amount
=
bytes
(
got_extra
4
:
0
)
;
int
last_shift
;
rtx
my_operands
[
3
]
;
if
(
!
got_extra
)
output_asm_insn
(
"ld\t%6, @%1"
,
operands
)
;
if
(
bytes
>=
2
)
{
bytes
-=
2
;
output_asm_insn
(
"sra3\t%5, %6, #16"
,
operands
)
;
my_operands
[
0
]
=
operands
[
5
]
;
my_operands
[
1
]
=
GEN_INT
(
dst_offset
)
;
my_operands
[
2
]
=
operands
[
0
]
;
output_asm_insn
(
"sth\t%0, @(%1,%2)"
,
my_operands
)
;
if
(
bytes
>
0
)
{
dst_offset
+=
2
;
last_shift
=
8
;
}
}
else
last_shift
=
24
;
if
(
bytes
>
0
)
{
my_operands
[
0
]
=
operands
[
6
]
;
my_operands
[
1
]
=
GEN_INT
(
last_shift
)
;
output_asm_insn
(
"srai\t%0, #%1"
,
my_operands
)
;
my_operands
[
0
]
=
operands
[
6
]
;
my_operands
[
1
]
=
GEN_INT
(
dst_offset
)
;
my_operands
[
2
]
=
operands
[
0
]
;
output_asm_insn
(
"stb\t%0, @(%1,%2)"
,
my_operands
)
;
}
if
(
dst_inc_amount
&&
!
find_reg_note
(
insn
,
REG_UNUSED
,
operands
[
0
]
)
)
{
my_operands
[
0
]
=
operands
[
0
]
;
my_operands
[
1
]
=
GEN_INT
(
dst_inc_amount
)
;
output_asm_insn
(
"addi\t%0, #%1"
,
my_operands
)
;
}
if
(
src_inc_amount
&&
!
find_reg_note
(
insn
,
REG_UNUSED
,
operands
[
1
]
)
)
{
my_operands
[
0
]
=
operands
[
1
]
;
my_operands
[
1
]
=
GEN_INT
(
src_inc_amount
)
;
output_asm_insn
(
"addi\t%0, #%1"
,
my_operands
)
;
}
bytes
=
0
;
}
first_time
=
0
;
}
}
</s>

Emit load/stores for a small constant word aligned block_move . operands [ 0 ] is the memory address of the destination . operands [ 1 ] is the memory address of the source . operands [ 2 ] is the number of bytes to move . operands [ 3 ] is a temp register . operands [ 4 ] is a temp register .


<s> static void alpha_setup_incoming_varargs ( cumulative_args_t pcum , const function_arg_info & arg , int * pretend_size , int no_rtl ) { CUMULATIVE_ARGS cum = * get_cumulative_args ( pcum ) ; if ( ! TYPE_NO_NAMED_ARGS_STDARG_P ( TREE_TYPE ( current_function_decl ) ) ) targetm . calls . function_arg_advance ( pack_cumulative_args ( & cum ) , arg ) ; if ( cum . num_args < 6 ) { if ( ! no_rtl ) { emit_move_insn ( gen_rtx_REG ( DImode , 1 ) , virtual_incoming_args_rtx ) ; emit_insn ( gen_arg_home ( ) ) ; } * pretend_size = 7 * UNITS_PER_WORD ; } if ( cum >= 6 ) return ; if ( ! no_rtl ) { int count ; alias_set_type set = get_varargs_alias_set ( ) ; rtx tmp ; count = cfun -> va_list_gpr_size / UNITS_PER_WORD ; if ( count > 6 - cum ) count = 6 - cum ; gcc_assert ( ( VA_LIST_MAX_FPR_SIZE & 3 ) == 3 ) ; if ( cfun -> va_list_fpr_size & 1 ) { tmp = gen_rtx_MEM ( BLKmode , plus_constant ( Pmode , virtual_incoming_args_rtx , ( cum + 6 ) * UNITS_PER_WORD ) ) ; MEM_NOTRAP_P ( tmp ) = 1 ; set_mem_alias_set ( tmp , set ) ; move_block_from_reg ( 16 + cum , tmp , count ) ; } if ( cfun -> va_list_fpr_size & 2 ) { tmp = gen_rtx_MEM ( BLKmode , plus_constant ( Pmode , virtual_incoming_args_rtx , cum * UNITS_PER_WORD ) ) ; MEM_NOTRAP_P ( tmp ) = 1 ; set_mem_alias_set ( tmp , set ) ; move_block_from_reg ( 16 + cum + TARGET_FPREGS * 32 , tmp , count ) ; } } * pretend_size = 12 * UNITS_PER_WORD ; } </s>

Perform any needed actions needed for a function that is receiving a variable number of arguments .


<s> int m68hc11_memory_move_cost ( enum machine_mode mode , enum reg_class class , int in ATTRIBUTE_UNUSED ) { if ( class <= H_REGS && class > NO_REGS ) { if ( GET_MODE_SIZE ( mode ) <= 2 ) return COSTS_N_INSNS ( 1 ) + ( reload_completed | reload_in_progress ) ; else return COSTS_N_INSNS ( 2 ) + ( reload_completed | reload_in_progress ) ; } </s>


"failed to parse register and immediate pair"

ParseInstruction - Parse one assembly instruction .


<s> bool MipsAsmPrinter :: PrintAsmOperand ( const MachineInstr * MI , unsigned OpNo , unsigned AsmVariant , const char * ExtraCode ) { if ( ExtraCode && ExtraCode [ 0 ] ) return true ; printOperand ( MI , OpNo ) ; return false ; } </s>

PrintAsmOperand - Print out an operand for an inline asm expression .


<s> machine_mode rs6000_promote_function_mode ( const_tree type ATTRIBUTE_UNUSED , machine_mode mode , int * punsignedp ATTRIBUTE_UNUSED , const_tree , int for_return ATTRIBUTE_UNUSED ) { PROMOTE_MODE ( mode , * punsignedp , type ) ; return mode ; } </s>

On rs6000 , function arguments are promoted , as are function return values .


<s> BitVector ARMBaseRegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; Reserved . set ( ARM :: SP ) ; Reserved . set ( ARM :: PC ) ; if ( STI . isTargetDarwin ( ) || hasFP ( MF ) ) Reserved . set ( FramePtr ) ; if ( STI . isR9Reserved ( ) ) Reserved . set ( ARM :: R9 ) ; return Reserved ; } </s>


<s> static bool bpf_rtx_costs ( rtx x ATTRIBUTE_UNUSED , enum machine_mode mode ATTRIBUTE_UNUSED , int outer_code ATTRIBUTE_UNUSED , int opno ATTRIBUTE_UNUSED , int * total ATTRIBUTE_UNUSED , bool speed ATTRIBUTE_UNUSED ) { return false ; } </s>

Describe the relative costs of RTL expressions . Return true when all subexpressions of X have been processed , and false when ` rtx_cost ' should recurse .


<s> MCObjectWriter * createObjectWriter ( raw_ostream & OS ) const { return createX86MachObjectWriter ( OS , true , MachO :: CPU_TYPE_X86_64 , Subtype ) ; } </s>

Create a new MCObjectWriter instance for use by the assembler backend to emit the final object file .


<s> unsigned PPCRegisterInfo :: getRegPressureLimit ( const TargetRegisterClass * RC , MachineFunction & MF ) const { const PPCSubtarget & Subtarget = MF . getSubtarget < PPCSubtarget > ( ) ; const TargetFrameLowering * TFI = Subtarget . getFrameLowering ( ) ; const unsigned DefaultSafety = 1 ; switch ( RC -> getID ( ) ) { default : return 0 ; case PPC :: G8RC_NOX0RegClassID : case PPC :: GPRC_NOR0RegClassID : case PPC :: G8RCRegClassID : case PPC :: GPRCRegClassID : { unsigned FP = TFI -> hasFP ( MF ) ? 1 : 0 ; return 32 - FP - DefaultSafety ; } case PPC :: F8RCRegClassID : case PPC :: F4RCRegClassID : case PPC :: QFRCRegClassID : case PPC :: QSRCRegClassID : case PPC :: QBRCRegClassID : case PPC :: VRRCRegClassID : case PPC :: VFRCRegClassID : case PPC :: VSLRCRegClassID : case PPC :: VSHRCRegClassID : return 32 - DefaultSafety ; case PPC :: VSRCRegClassID : case PPC :: VSFRCRegClassID : return 64 - DefaultSafety ; case PPC :: CRRCRegClassID : return 8 - DefaultSafety ; } } </s>

Return the register pressure `` high water mark '' for the specific register class .


<s> bool M680x0InstrInfo :: analyzeBranch ( MachineBasicBlock & MBB , MachineBasicBlock * & TBB , MachineBasicBlock * & FBB , SmallVectorImpl < MachineOperand > & Cond , bool AllowModify ) const { return AnalyzeBranchImpl ( MBB , TBB , FBB , Cond , AllowModify ) ; } </s>

analyzeBranch - Analyze the branching code at the end of MBB , returning true if it can not be understood ( e.g .


<s> static bool aarch64_simd_vector_alignment_reachable ( const_tree type , bool is_packed ) { if ( is_packed ) return false ; if ( tree_int_cst_compare ( TYPE_SIZE ( type ) , bitsize_int ( BIGGEST_ALIGNMENT ) ) > 0 ) return false ; return true ; } </s>


<s> static bool ix86_pass_by_reference ( cumulative_args_t cum_v , const function_arg_info & arg ) { CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; if ( TARGET_64BIT ) { enum calling_abi call_abi = cum ? cum -> call_abi : ix86_abi ; if ( call_abi == MS_ABI ) { HOST_WIDE_INT msize = GET_MODE_SIZE ( arg . mode ) ; if ( tree type = arg . type ) { if ( TREE_CODE ( type ) == ARRAY_TYPE ) return true ; if ( RECORD_OR_UNION_TYPE_P ( type ) ) { msize = int_size_in_bytes ( type ) ; } } return msize != 1 && msize != 2 && msize != 4 && msize != 8 ; } else if ( arg . type && int_size_in_bytes ( arg . type ) == - 1 ) return true ; } return false ; } </s>

A C expression that indicates when an argument must be passed by reference . If nonzero for an argument , a copy of that argument is made in memory and a pointer to the argument is passed instead of the argument itself . The pointer is passed in whatever way is appropriate for passing a pointer to that type .


<s> bool X86TargetLowering :: hasCopyImplyingStackAdjustment ( MachineFunction * MF ) const { const MachineRegisterInfo & MRI = MF -> getRegInfo ( ) ; return any_of ( MRI . reg_instructions ( X86 :: EFLAGS ) , [ ] ( const MachineInstr & RI ) { return RI . isCopy ( ) ; } ) ; } </s>

Returns true if the function contains operations which will lower down to instructions which manipulate the stack pointer .


<s> void rs6000_expand_atomic_exchange ( rtx operands [ ] ) { rtx retval , mem , val , cond ; machine_mode mode ; enum memmodel model ; rtx label , x , mask , shift ; retval = operands [ 0 ] ; mem = operands [ 1 ] ; val = operands [ 2 ] ; model = memmodel_base ( INTVAL ( operands [ 3 ] ) ) ; mode = GET_MODE ( mem ) ; mask = shift = NULL_RTX ; if ( ! TARGET_SYNC_HI_QI && ( mode == QImode || mode == HImode ) ) { mem = rs6000_adjust_atomic_subword ( mem , & shift , & mask ) ; val = convert_modes ( SImode , mode , val , 1 ) ; val = expand_simple_binop ( SImode , ASHIFT , val , shift , NULL_RTX , 1 , OPTAB_LIB_WIDEN ) ; retval = gen_reg_rtx ( SImode ) ; mode = SImode ; } mem = rs6000_pre_atomic_barrier ( mem , model ) ; label = gen_rtx_LABEL_REF ( VOIDmode , gen_label_rtx ( ) ) ; emit_label ( XEXP ( label , 0 ) ) ; emit_load_locked ( mode , retval , mem ) ; x = val ; if ( mask ) x = rs6000_mask_atomic_subword ( retval , val , mask ) ; cond = gen_reg_rtx ( CCmode ) ; emit_store_conditional ( mode , cond , mem , x ) ; x = gen_rtx_NE ( VOIDmode , cond , const0_rtx ) ; emit_unlikely_jump ( x , label ) ; rs6000_post_atomic_barrier ( model ) ; if ( shift ) rs6000_finish_atomic_subword ( operands [ 0 ] , retval , shift ) ; } </s>


<s> static reg_class_t ix86_spill_class ( reg_class_t rclass , machine_mode mode ) { if ( TARGET_SSE && TARGET_GENERAL_REGS_SSE_SPILL && ! TARGET_MMX && ( mode == SImode || ( TARGET_64BIT && mode == DImode ) ) && rclass != NO_REGS && INTEGER_CLASS_P ( rclass ) ) return ALL_SSE_REGS ; return NO_REGS ; } </s>

Return class of registers which could be used for pseudo of MODE and of class RCLASS for spilling instead of memory . Return NO_REGS if it is not possible or non-profitable .


<s> static bool ia64_needs_block_p ( ds_t ts ) { if ( ts & BEGIN_DATA ) return ! mflag_sched_spec_ldc ; gcc_assert ( ( ts & BEGIN_CONTROL ) != 0 ) ; return ! ( mflag_sched_spec_control_ldc && mflag_sched_spec_ldc ) ; } </s>

Return nonzero , if INSN needs branchy recovery check .


<s> void BTFTypeDeclTag :: emitType ( MCStreamer & OS ) { BTFTypeBase :: emitType ( OS ) ; OS . emitInt32 ( Info ) ; } </s>


<s>
void
UPTDAGToDAGISel
::
Select
(
SDNode
*
N
)
{
LLVM_DEBUG
(
outs
(
)
<<
"Selecting: "
;
N
->
dump
(
CurDAG
)
;
outs
(
)
<<
"\n"
)
;
switch
(
N
->
getOpcode
(
)
)
{
default
:
break
;
case
ISD
::
Constant
:
if
(
SelectMoveImmediate
(
N
)
)
return
;
break
;
case
ISD
::
BR_CC
:
if
(
SelectConditionalBranch
(
N
)
)
return
;
break
;
}
SelectCode
(
N
)
;
}
</s>

Main hook for targets to transform nodes into machine nodes .

UPT
UPT
"Selecting: "
"\n"
ISD::Constant
ISD::BR_CC


<s>
SDNode
*
MBlazeDAGToDAGISel
::
Select
(
SDNode
*
Node
)
{
unsigned
Opcode
=
Node
->
getOpcode
(
)
;
DebugLoc
dl
=
Node
->
getDebugLoc
(
)
;
if
(
Node
->
isMachineOpcode
(
)
)
return
;
switch
(
Opcode
)
{
default
:
break
;
case
ISD
::
GLOBAL_OFFSET_TABLE
:
return
getGlobalBaseReg
(
)
;
case
ISD
::
FrameIndex
:
{
SDValue
imm
=
CurDAG
->
getTargetConstant
(
0
,
MVT
::
i32
)
;
int
FI
=
dyn_cast
<
FrameIndexSDNode
>
(
Node
)
->
getIndex
(
)
;
EVT
VT
=
Node
->
getValueType
(
0
)
;
SDValue
TFI
=
CurDAG
->
getTargetFrameIndex
(
FI
,
VT
)
;
unsigned
Opc
=
MBlaze
::
ADDIK
;
if
(
Node
->
hasOneUse
(
)
)
return
CurDAG
->
SelectNodeTo
(
Node
,
Opc
,
VT
,
TFI
,
imm
)
;
return
CurDAG
->
getMachineNode
(
Opc
,
dl
,
VT
,
TFI
,
imm
)
;
}
case
MBlazeISD
::
JmpLink
:
{
if
(
TM
.
getRelocationModel
(
)
==
Reloc
::
PIC_
)
{
SDValue
Chain
=
Node
->
getOperand
(
0
)
;
SDValue
Callee
=
Node
->
getOperand
(
1
)
;
SDValue
R20Reg
=
CurDAG
->
getRegister
(
MBlaze
::
R20
,
MVT
::
i32
)
;
SDValue
InFlag
(
0
,
0
)
;
if
(
(
isa
<
GlobalAddressSDNode
>
(
Callee
)
)
||
(
isa
<
ExternalSymbolSDNode
>
(
Callee
)
)
)
{
SDValue
GPReg
=
CurDAG
->
getRegister
(
MBlaze
::
R15
,
MVT
::
i32
)
;
SDValue
Ops
[
]
=
{
Callee
,
GPReg
,
Chain
}
;
SDValue
Load
=
SDValue
(
CurDAG
->
getMachineNode
(
MBlaze
::
LW
,
dl
,
MVT
::
i32
,
MVT
::
Other
,
Ops
)
,
0
)
;
Chain
=
Load
.
getValue
(
1
)
;
Chain
=
CurDAG
->
getCopyToReg
(
Chain
,
dl
,
R20Reg
,
Load
,
InFlag
)
;
}
else
Chain
=
CurDAG
->
getCopyToReg
(
Chain
,
dl
,
R20Reg
,
Callee
,
InFlag
)
;
SDNode
*
ResNode
=
CurDAG
->
getMachineNode
(
MBlaze
::
BRLID
,
dl
,
MVT
::
Other
,
MVT
::
Glue
,
R20Reg
,
Chain
)
;
Chain
=
SDValue
(
ResNode
,
0
)
;
InFlag
=
SDValue
(
ResNode
,
1
)
;
ReplaceUses
(
SDValue
(
Node
,
0
)
,
Chain
)
;
ReplaceUses
(
SDValue
(
Node
,
1
)
,
InFlag
)
;
return
ResNode
;
}
}
}
SDNode
*
ResNode
=
SelectCode
(
Node
)
;
DEBUG
(
errs
(
)
<<
"=> "
)
;
if
(
ResNode
==
||
ResNode
==
Node
)
DEBUG
(
Node
->
dump
(
CurDAG
)
)
;
else
DEBUG
(
ResNode
->
dump
(
CurDAG
)
)
;
DEBUG
(
errs
(
)
<<
"\n"
)
;
return
ResNode
;
}
</s>


<s> void RISCVELFTargetObjectFile :: Initialize ( MCContext & Ctx , const TargetMachine & TM ) { TargetLoweringObjectFileELF :: Initialize ( Ctx , TM ) ; SmallDataSection = getContext ( ) . getELFSection ( ".sdata" , ELF :: SHT_PROGBITS , ELF :: SHF_WRITE | ELF :: SHF_ALLOC ) ; SmallBSSSection = getContext ( ) . getELFSection ( ".sbss" , ELF :: SHT_NOBITS , ELF :: SHF_WRITE | ELF :: SHF_ALLOC ) ; } </s>

This method must be called before any actual lowering is done .


<s> int xstormy16_initial_elimination_offset ( int from , int to ) { struct xstormy16_stack_layout layout ; int result ; layout = xstormy16_compute_stack_layout ( ) ; if ( from == FRAME_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM ) result = layout . sp_minus_fp - layout . locals_size ; else if ( from == FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM ) result = - layout . locals_size ; else if ( from == ARG_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM ) result = - layout . fp_minus_ap ; else if ( from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM ) result = - ( layout . sp_minus_fp + layout . fp_minus_ap ) ; else gcc_unreachable ( ) ; return result ; } </s>

Determine how all the special registers get eliminated .


<s> void X86FrameLowering :: orderFrameObjects ( const MachineFunction & MF , SmallVectorImpl < int > & ObjectsToAllocate ) const { const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; if ( ObjectsToAllocate . empty ( ) ) return ; std :: vector < X86FrameSortingObject > SortingObjects ( MFI -> getObjectIndexEnd ( ) ) ; for ( auto & Obj : ObjectsToAllocate ) { SortingObjects [ Obj ] . IsValid = true ; SortingObjects [ Obj ] . ObjectIndex = Obj ; SortingObjects [ Obj ] . ObjectAlignment = MFI -> getObjectAlignment ( Obj ) ; int ObjectSize = MFI -> getObjectSize ( Obj ) ; if ( ObjectSize == 0 ) SortingObjects [ Obj ] . ObjectSize = 4 ; else SortingObjects [ Obj ] . ObjectSize = ObjectSize ; } for ( auto & MBB : MF ) { for ( auto & MI : MBB ) { if ( MI . isDebugValue ( ) ) continue ; for ( const MachineOperand & MO : MI . operands ( ) ) { if ( ! MO . isFI ( ) ) continue ; int Index = MO . getIndex ( ) ; if ( Index >= 0 && Index < MFI -> getObjectIndexEnd ( ) && SortingObjects [ Index ] . IsValid ) SortingObjects [ Index ] . ObjectNumUses ++ ; } } } std :: stable_sort ( SortingObjects . begin ( ) , SortingObjects . end ( ) , X86FrameSortingComparator ( ) ) ; int i = 0 ; for ( auto & Obj : SortingObjects ) { if ( ! Obj . IsValid ) break ; ObjectsToAllocate [ i ++ ] = Obj . ObjectIndex ; } if ( ! TRI -> needsStackRealignment ( MF ) && hasFP ( MF ) ) std :: reverse ( ObjectsToAllocate . begin ( ) , ObjectsToAllocate . end ( ) ) ; } </s>


<s> static rtx gen_lvx_v4si_move ( rtx dest , rtx src ) { gcc_assert ( MEM_P ( dest ) ^ MEM_P ( src ) ) ; gcc_assert ( GET_MODE ( dest ) == V4SImode && GET_MODE ( src ) == V4SImode ) ; if ( MEM_P ( dest ) ) return gen_altivec_stvx_v4si_internal ( dest , src ) ; else return gen_altivec_lvx_v4si_internal ( dest , src ) ; } </s>

Generate loads and stores for a move of v4si mode using lvx/stvx . This uses altivec_ { l , st } vx_ < mode > _internal which use unspecs to keep combine from changing what instruction gets used . DEST is the destination for the data . SRC is the source of the data for the move .


<s>
const
MCFixupKindInfo
&
getFixupKindInfo
(
MCFixupKind
Kind
)
const
override
{
const
static
MCFixupKindInfo
Infos
[
Sparc
::
NumTargetFixupKinds
]
=
{
{
"fixup_sparc_call30"
,
2
,
30
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_sparc_br22"
,
10
,
22
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_sparc_br19"
,
13
,
19
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_sparc_br16_2"
,
10
,
2
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_sparc_br16_14"
,
18
,
14
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_sparc_hi22"
,
10
,
22
,
0
}
,
{
"fixup_sparc_lo10"
,
22
,
10
,
0
}
,
{
"fixup_sparc_h44"
,
10
,
22
,
0
}
,
{
"fixup_sparc_m44"
,
22
,
10
,
0
}
,
{
"fixup_sparc_l44"
,
20
,
12
,
0
}
,
{
"fixup_sparc_hh"
,
10
,
22
,
0
}
,
{
"fixup_sparc_hm"
,
22
,
10
,
0
}
,
{
"fixup_sparc_pc22"
,
10
,
22
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_sparc_pc10"
,
22
,
10
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_sparc_got22"
,
10
,
22
,
0
}
,
{
"fixup_sparc_got10"
,
22
,
10
,
0
}
,
{
"fixup_sparc_wplt30"
,
2
,
30
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_sparc_tls_gd_hi22"
,
10
,
22
,
0
}
,
{
"fixup_sparc_tls_gd_lo10"
,
22
,
10
,
0
}
,
{
"fixup_sparc_tls_gd_add"
,
0
,
0
,
0
}
,
{
"fixup_sparc_tls_gd_call"
,
0
,
0
,
0
}
,
{
"fixup_sparc_tls_ldm_hi22"
,
10
,
22
,
0
}
,
{
"fixup_sparc_tls_ldm_lo10"
,
22
,
10
,
0
}
,
{
"fixup_sparc_tls_ldm_add"
,
0
,
0
,
0
}
,
{
"fixup_sparc_tls_ldm_call"
,
0
,
0
,
0
}
,
{
"fixup_sparc_tls_ldo_hix22"
,
10
,
22
,
0
}
,
{
"fixup_sparc_tls_ldo_lox10"
,
22
,
10
,
0
}
,
{
"fixup_sparc_tls_ldo_add"
,
0
,
0
,
0
}
,
{
"fixup_sparc_tls_ie_hi22"
,
10
,
22
,
0
}
,
{
"fixup_sparc_tls_ie_lo10"
,
22
,
10
,
0
}
,
{
"fixup_sparc_tls_ie_ld"
,
0
,
0
,
0
}
,
{
"fixup_sparc_tls_ie_ldx"
,
0
,
0
,
0
}
,
{
"fixup_sparc_tls_ie_add"
,
0
,
0
,
0
}
,
{
"fixup_sparc_tls_le_hix22"
,
0
,
0
,
0
}
,
{
"fixup_sparc_tls_le_lox10"
,
0
,
0
,
0
}
}
;
if
(
Kind
<
FirstTargetFixupKind
)
return
MCAsmBackend
::
getFixupKindInfo
(
Kind
)
;
assert
(
unsigned
(
Kind
FirstTargetFixupKind
)
<
getNumFixupKinds
(
)
&&
"Invalid kind!"
)
;
return
Infos
[
Kind
FirstTargetFixupKind
]
;
}
</s>


<s> bool aarch64_sve_index_immediate_p ( rtx base_or_step ) { return ( CONST_INT_P ( base_or_step ) && IN_RANGE ( INTVAL ( base_or_step ) , - 16 , 15 ) ) ; } </s>

Return true if BASE_OR_STEP is a valid immediate operand for an SVE INDEX instruction .


<s> rtl_opt_pass * make_pass_tag_collision_avoidance ( gcc :: context * ctxt ) { return new pass_tag_collision_avoidance ( ctxt ) ; } </s>


<s>
bool
isMem
(
)
const
override
{
llvm_unreachable
(
"No isMem"
)
;
}
</s>


<s> bool AMDGPULibFunc :: parse ( StringRef FuncName , AMDGPULibFunc & F ) { if ( FuncName . empty ( ) ) { F . Impl = std :: unique_ptr < AMDGPULibFuncImpl > ( ) ; return false ; } if ( eatTerm ( FuncName , "_Z" ) ) F . Impl = make_unique < AMDGPUMangledLibFunc > ( ) ; else F . Impl = make_unique < AMDGPUUnmangledLibFunc > ( ) ; if ( F . Impl -> parseFuncName ( FuncName ) ) return true ; F . Impl = std :: unique_ptr < AMDGPULibFuncImpl > ( ) ; return false ; } </s>

Parses just-constructed SpecialCaseList entries from a memory buffer .

AMDGPU AMDGPU AMDGPU AMDGPU "_Z" AMDGPU AMDGPU AMDGPU


<s> Instruction * getRoot ( ) { return Root ; } </s>

Similar to getMemoryRoot , but also flushes PendingConstrainedFP ( Strict ) items .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { MachineFunctionPass :: getAnalysisUsage ( AU ) ; AU . addRequired < AAResultsWrapperPass > ( ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> Sched :: Preference ARMTargetLowering :: getSchedulingPreference ( SDNode * N ) const { unsigned NumVals = N -> getNumValues ( ) ; if ( ! NumVals ) return Sched :: RegPressure ; for ( unsigned i = 0 ; i != NumVals ; ++ i ) { EVT VT = N -> getValueType ( i ) ; if ( VT == MVT :: Glue || VT == MVT :: Other ) continue ; if ( VT . isFloatingPoint ( ) || VT . isVector ( ) ) return Sched :: ILP ; } if ( ! N -> isMachineOpcode ( ) ) return Sched :: RegPressure ; const TargetInstrInfo * TII = getTargetMachine ( ) . getSubtargetImpl ( ) -> getInstrInfo ( ) ; const MCInstrDesc & MCID = TII -> get ( N -> getMachineOpcode ( ) ) ; if ( MCID . getNumDefs ( ) == 0 ) return Sched :: RegPressure ; if ( ! Itins -> isEmpty ( ) && Itins -> getOperandCycle ( MCID . getSchedClass ( ) , 0 ) > 2 ) return Sched :: ILP ; return Sched :: RegPressure ; } </s>


"Load should return a value and a chain"

LowerOperation - Provide custom lowering hooks for some operations .


<s> bool addGCPasses ( ) override { return false ; } </s>

addGCPasses - Add late codegen passes that analyze code for garbage collection .


<s> int loongarch_const_insns ( rtx x ) { enum loongarch_symbol_type symbol_type ; rtx offset ; switch ( GET_CODE ( x ) ) { case HIGH : if ( ! loongarch_symbolic_constant_p ( XEXP ( x , 0 ) , & symbol_type ) || ! loongarch_split_symbol_type ( symbol_type ) ) return 0 ; return 1 ; case CONST_INT : return loongarch_integer_cost ( INTVAL ( x ) ) ; case CONST_VECTOR : case CONST_DOUBLE : return x == CONST0_RTX ( GET_MODE ( x ) ) ? 1 : 0 ; case CONST : if ( loongarch_symbolic_constant_p ( x , & symbol_type ) ) return loongarch_symbol_insns ( symbol_type , MAX_MACHINE_MODE ) ; split_const ( x , & x , & offset ) ; if ( offset != 0 ) { int n = loongarch_const_insns ( x ) ; if ( n != 0 ) { if ( IMM12_INT ( offset ) ) return n + 1 ; else if ( ! targetm . cannot_force_const_mem ( GET_MODE ( x ) , x ) ) return n + 1 + loongarch_integer_cost ( INTVAL ( offset ) ) ; } } return 0 ; case SYMBOL_REF : case LABEL_REF : return loongarch_symbol_insns ( loongarch_classify_symbol ( x ) , MAX_MACHINE_MODE ) ; default : return 0 ; } } </s>

Return the number of instructions needed to load constant X , Return 0 if X is n't a valid constant .


initializeSubtargetDependencies - Initializes using a CPU , a TuneCPU , and feature string so that we can use initializer lists for subtarget initialization .


<s> bool MipsFrameLowering :: hasFP ( const MachineFunction & MF ) const { const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; return MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) || MFI -> hasVarSizedObjects ( ) || MFI -> isFrameAddressTaken ( ) ; } </s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .


<s> bool ARMIndirectThunks :: runOnMachineFunction ( MachineFunction & MF ) { LLVM_DEBUG ( dbgs ( ) << getPassName ( ) << '\n' ) ; auto & MMI = getAnalysis < MachineModuleInfoWrapperPass > ( ) . getMMI ( ) ; return runTIs ( MMI , MF , TIs ) ; } </s>

runOnMachineFunction - Emit the function body .


<s> void HexagonTargetObjectFile :: Initialize ( MCContext & Ctx , const TargetMachine & TM ) { TargetLoweringObjectFileELF :: Initialize ( Ctx , TM ) ; SmallDataSection = getContext ( ) . getELFSection ( ".sdata" , ELF :: SHT_PROGBITS , ELF :: SHF_WRITE | ELF :: SHF_ALLOC | ELF :: SHF_HEX_GPREL ) ; SmallBSSSection = getContext ( ) . getELFSection ( ".sbss" , ELF :: SHT_NOBITS , ELF :: SHF_WRITE | ELF :: SHF_ALLOC | ELF :: SHF_HEX_GPREL ) ; } </s>


<s> virtual void EmitInstruction ( const MCInst & Inst ) { EmitA64MappingSymbol ( ) ; MCELFStreamer :: EmitInstruction ( Inst ) ; } </s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s> static void mark_swaps_for_removal ( swap_web_entry * insn_entry , unsigned int i ) { rtx insn = insn_entry [ i ] . insn ; struct df_insn_info * insn_info = DF_INSN_INFO_GET ( insn ) ; if ( insn_entry [ i ] . is_load ) { df_ref def ; FOR_EACH_INSN_INFO_DEF ( def , insn_info ) { struct df_link * link = DF_REF_CHAIN ( def ) ; while ( link ) { rtx use_insn = DF_REF_INSN ( link -> ref ) ; insn_entry [ INSN_UID ( use_insn ) ] . will_delete = 1 ; link = link -> next ; } } } else if ( insn_entry [ i ] . is_store ) { df_ref use ; FOR_EACH_INSN_INFO_USE ( use , insn_info ) { machine_mode mode = GET_MODE ( DF_REF_REG ( use ) ) ; if ( ! ALTIVEC_OR_VSX_VECTOR_MODE ( mode ) ) continue ; struct df_link * link = DF_REF_CHAIN ( use ) ; while ( link ) { rtx def_insn = DF_REF_INSN ( link -> ref ) ; insn_entry [ INSN_UID ( def_insn ) ] . will_delete = 1 ; link = link -> next ; } } } } </s>

Mark the xxswapdi instructions associated with permuting loads and stores for removal . Note that we only flag them for deletion here , as there is a possibility of a swap being reached from multiple loads , etc .


<s> bool AMDGPUPassConfig :: addInstSelector ( ) { addPass ( createAMDGPUISelDag ( getAMDGPUTargetMachine ( ) ) ) ; const AMDGPUSubtarget & ST = TM -> getSubtarget < AMDGPUSubtarget > ( ) ; if ( ST . getGeneration ( ) <= AMDGPUSubtarget :: NORTHERN_ISLANDS ) { addPass ( createAMDGPUIndirectAddressingPass ( * TM ) ) ; } return false ; } </s>

addInstSelector - This method should install an instruction selector pass , which converts from LLVM code to machine instructions .


<s> static void mips_sim_wait_reg ( struct mips_sim * state , rtx_insn * insn , rtx reg ) { unsigned int regno , end_regno ; end_regno = END_REGNO ( reg ) ; for ( regno = REGNO ( reg ) ; regno < end_regno ; regno ++ ) if ( state -> last_set [ regno ] . insn != 0 ) { unsigned int t ; t = ( state -> last_set [ regno ] . time + insn_latency ( state -> last_set [ regno ] . insn , insn ) ) ; while ( state -> time < t ) mips_sim_next_cycle ( state ) ; } } </s>

Advance simulation state STATE until instruction INSN can read register REG .


<s> Align getStackAlignment ( ) const { return Align ( stackAlignment ) ; } </s>

Returns the minimum alignment known to hold of the stack frame on entry to the function and which must be maintained by every function for this subtarget .


<s> std :: pair < unsigned , const TargetRegisterClass * > AArch64TargetLowering :: getRegForInlineAsmConstraint ( const TargetRegisterInfo * TRI , StringRef Constraint , MVT VT ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { case 'r' : if ( VT . getSizeInBits ( ) == 64 ) return std :: make_pair ( 0U , & AArch64 :: GPR64commonRegClass ) ; return std :: make_pair ( 0U , & AArch64 :: GPR32commonRegClass ) ; case 'w' : if ( ! Subtarget -> hasFPARMv8 ( ) ) break ; if ( VT . getSizeInBits ( ) == 16 ) return std :: make_pair ( 0U , & AArch64 :: FPR16RegClass ) ; if ( VT . getSizeInBits ( ) == 32 ) return std :: make_pair ( 0U , & AArch64 :: FPR32RegClass ) ; if ( VT . getSizeInBits ( ) == 64 ) return std :: make_pair ( 0U , & AArch64 :: FPR64RegClass ) ; if ( VT . getSizeInBits ( ) == 128 ) return std :: make_pair ( 0U , & AArch64 :: FPR128RegClass ) ; break ; case 'x' : if ( ! Subtarget -> hasFPARMv8 ( ) ) break ; if ( VT . getSizeInBits ( ) == 128 ) return std :: make_pair ( 0U , & AArch64 :: FPR128_loRegClass ) ; break ; } } if ( StringRef ( "{cc}" ) . equals_lower ( Constraint ) ) return std :: make_pair ( unsigned ( AArch64 :: NZCV ) , & AArch64 :: CCRRegClass ) ; std :: pair < unsigned , const TargetRegisterClass * > Res ; Res = TargetLowering :: getRegForInlineAsmConstraint ( TRI , Constraint , VT ) ; if ( ! Res . second ) { unsigned Size = Constraint . size ( ) ; if ( ( Size == 4 || Size == 5 ) && Constraint [ 0 ] == '{' && tolower ( Constraint [ 1 ] ) == 'v' && Constraint [ Size - 1 ] == '}' ) { int RegNo ; bool Failed = Constraint . slice ( 2 , Size - 1 ) . getAsInteger ( 10 , RegNo ) ; if ( ! Failed && RegNo >= 0 && RegNo <= 31 ) { if ( VT != MVT :: Other && VT . getSizeInBits ( ) == 64 ) { Res . first = AArch64 :: FPR64RegClass . getRegister ( RegNo ) ; Res . second = & AArch64 :: FPR64RegClass ; } else { Res . first = AArch64 :: FPR128RegClass . getRegister ( RegNo ) ; Res . second = & AArch64 :: FPR128RegClass ; } } } } if ( Res . second && ! Subtarget -> hasFPARMv8 ( ) && ! AArch64 :: GPR32allRegClass . hasSubClassEq ( Res . second ) && ! AArch64 :: GPR64allRegClass . hasSubClassEq ( Res . second ) ) return std :: make_pair ( 0U , nullptr ) ; return Res ; } </s>

Given a physical register constraint ( e.g .


<s> static rtx riscv_legitimize_address ( rtx x , rtx oldx ATTRIBUTE_UNUSED , enum machine_mode mode ) { rtx addr ; if ( riscv_tls_symbol_p ( x ) ) return riscv_legitimize_tls_address ( x ) ; if ( riscv_split_symbol ( NULL , x , mode , & addr ) ) return riscv_force_address ( addr , mode ) ; if ( GET_CODE ( x ) == PLUS && CONST_INT_P ( XEXP ( x , 1 ) ) && INTVAL ( XEXP ( x , 1 ) ) != 0 ) { rtx base = XEXP ( x , 0 ) ; HOST_WIDE_INT offset = INTVAL ( XEXP ( x , 1 ) ) ; if ( ! riscv_valid_base_register_p ( base , mode , false ) ) base = copy_to_mode_reg ( Pmode , base ) ; addr = riscv_add_offset ( NULL , base , offset ) ; return riscv_force_address ( addr , mode ) ; } return x ; } </s>

This function is used to implement LEGITIMIZE_ADDRESS . If X can be legitimized in a way that the generic machinery might not expect , return a new address , otherwise return NULL . MODE is the mode of the memory being accessed .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . addRequired < LoopInfoWrapperPass > ( ) ; AU . addRequired < DominatorTreeWrapperPass > ( ) ; AU . addRequired < LegacyDivergenceAnalysis > ( ) ; AU . addPreserved < DominatorTreeWrapperPass > ( ) ; AU . addRequired < TargetPassConfig > ( ) ; FunctionPass :: getAnalysisUsage ( AU ) ; } </s>


<s> void LanaiAsmBackend :: applyFixup ( const MCFixup & Fixup , char * Data , unsigned DataSize , uint64_t Value , bool IsPCRel ) const { MCFixupKind Kind = Fixup . getKind ( ) ; Value = adjustFixupValue ( static_cast < unsigned > ( Kind ) , Value ) ; if ( ! Value ) return ; unsigned Offset = Fixup . getOffset ( ) ; unsigned NumBytes = ( getFixupKindInfo ( Kind ) . TargetSize + 7 ) / 8 ; unsigned FullSize = 4 ; uint64_t CurVal = 0 ; for ( unsigned i = 0 ; i != NumBytes ; ++ i ) { unsigned Idx = ( FullSize - 1 - i ) ; CurVal |= static_cast < uint64_t > ( static_cast < uint8_t > ( Data [ Offset + Idx ] ) ) << ( i * 8 ) ; } uint64_t Mask = ( static_cast < uint64_t > ( - 1 ) >> ( 64 - getFixupKindInfo ( Kind ) . TargetSize ) ) ; CurVal |= Value & Mask ; for ( unsigned i = 0 ; i != NumBytes ; ++ i ) { unsigned Idx = ( FullSize - 1 - i ) ; Data [ Offset + Idx ] = static_cast < uint8_t > ( ( CurVal >> ( i * 8 ) ) & 0xff ) ; } } </s>

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


<s>
bool
MSP430AsmParser
::
ParseInstruction
(
ParseInstructionInfo
&
Info
,
StringRef
Name
,
SMLoc
NameLoc
,
OperandVector
&
Operands
)
{
if
(
Name
.
endswith_insensitive
(
".w"
)
)
Name
=
Name
.
drop_back
(
2
)
;
if
(
!
parseJccInstruction
(
Info
,
Name
,
NameLoc
,
Operands
)
)
return
false
;
Operands
.
push_back
(
MSP430Operand
::
CreateToken
(
Name
,
NameLoc
)
)
;
if
(
getLexer
(
)
.
is
(
AsmToken
::
EndOfStatement
)
)
return
false
;
if
(
ParseOperand
(
Operands
)
)
return
true
;
if
(
getLexer
(
)
.
is
(
AsmToken
::
Comma
)
)
{
getLexer
(
)
.
Lex
(
)
;
if
(
ParseOperand
(
Operands
)
)
return
true
;
}
if
(
getLexer
(
)
.
isNot
(
AsmToken
::
EndOfStatement
)
)
{
SMLoc
Loc
=
getLexer
(
)
.
getLoc
(
)
;
getParser
(
)
.
eatToEndOfStatement
(
)
;
return
Error
(
Loc
,
"unexpected token"
)
;
}
getParser
(
)
.
Lex
(
)
;
return
false
;
}
</s>

ParseInstruction - Parse one assembly instruction .


<s> bool FISCTargetLowering :: CanLowerReturn ( CallingConv :: ID CallConv , MachineFunction & MF , bool isVarArg , const SmallVectorImpl < ISD :: OutputArg > & Outs , LLVMContext & Context ) const { SmallVector < CCValAssign , 16 > RVLocs ; CCState CCInfo ( CallConv , isVarArg , MF , RVLocs , Context ) ; if ( ! CCInfo . CheckReturn ( Outs , RetCC_FISC ) ) return false ; if ( CCInfo . getNextStackOffset ( ) != 0 && isVarArg ) return false ; return true ; } </s>

This hook should be implemented to check whether the return values described by the Outs array can fit into the return registers .


<s>
void
PPCAsmPrinter
::
EmitInstruction
(
const
MachineInstr
*
MI
)
{
SmallString
<
128
>
Str
;
raw_svector_ostream
O
(
Str
)
;
if
(
MI
->
getOpcode
(
)
==
PPC
::
RLWINM
)
{
unsigned
char
SH
=
MI
->
getOperand
(
2
)
.
getImm
(
)
;
unsigned
char
MB
=
MI
->
getOperand
(
3
)
.
getImm
(
)
;
unsigned
char
ME
=
MI
->
getOperand
(
4
)
.
getImm
(
)
;
bool
useSubstituteMnemonic
=
false
;
if
(
SH
<=
31
&&
MB
==
0
&&
ME
==
(
31
SH
)
)
{
O
<<
"\tslwi "
;
useSubstituteMnemonic
=
true
;
}
if
(
SH
<=
31
&&
MB
==
(
32
SH
)
&&
ME
==
31
)
{
O
<<
"\tsrwi "
;
useSubstituteMnemonic
=
true
;
SH
=
32
SH
;
}
if
(
useSubstituteMnemonic
)
{
printOperand
(
MI
,
0
,
O
)
;
O
<<
", "
;
printOperand
(
MI
,
1
,
O
)
;
O
<<
", "
<<
(
unsigned
int
)
SH
;
OutStreamer
.
EmitRawText
(
O
.
str
(
)
)
;
return
;
}
}
if
(
(
MI
->
getOpcode
(
)
==
PPC
::
OR
||
MI
->
getOpcode
(
)
==
PPC
::
OR8
)
&&
MI
->
getOperand
(
1
)
.
getReg
(
)
==
MI
->
getOperand
(
2
)
.
getReg
(
)
)
{
O
<<
"\tmr "
;
printOperand
(
MI
,
0
,
O
)
;
O
<<
", "
;
printOperand
(
MI
,
1
,
O
)
;
OutStreamer
.
EmitRawText
(
O
.
str
(
)
)
;
return
;
}
if
(
MI
->
getOpcode
(
)
==
PPC
::
RLDICR
)
{
unsigned
char
SH
=
MI
->
getOperand
(
2
)
.
getImm
(
)
;
unsigned
char
ME
=
MI
->
getOperand
(
3
)
.
getImm
(
)
;
if
(
63
SH
==
ME
)
{
O
<<
"\tsldi "
;
printOperand
(
MI
,
0
,
O
)
;
O
<<
", "
;
printOperand
(
MI
,
1
,
O
)
;
O
<<
", "
<<
(
unsigned
int
)
SH
;
OutStreamer
.
EmitRawText
(
O
.
str
(
)
)
;
return
;
}
}
printInstruction
(
MI
,
O
)
;
OutStreamer
.
EmitRawText
(
O
.
str
(
)
)
;
}
</s>


<s> static void s390_dump_pool ( struct constant_pool * pool , bool remote_label ) { struct constant * c ; rtx_insn * insn = pool -> pool_insn ; int i ; if ( TARGET_CPU_ZARCH ) { insn = emit_insn_after ( gen_pool_section_start ( ) , insn ) ; INSN_ADDRESSES_NEW ( insn , - 1 ) ; } if ( TARGET_CPU_ZARCH ) insn = emit_insn_after ( gen_pool_align ( GEN_INT ( 8 ) ) , insn ) ; else insn = emit_insn_after ( gen_pool_align ( GEN_INT ( 4 ) ) , insn ) ; INSN_ADDRESSES_NEW ( insn , - 1 ) ; if ( ! remote_label ) { insn = emit_label_after ( pool -> label , insn ) ; INSN_ADDRESSES_NEW ( insn , - 1 ) ; } for ( i = 0 ; i < NR_C_MODES ; i ++ ) for ( c = pool -> constants [ i ] ; c ; c = c -> next ) { rtx value = copy_rtx ( c -> value ) ; if ( GET_CODE ( value ) == CONST && GET_CODE ( XEXP ( value , 0 ) ) == UNSPEC && XINT ( XEXP ( value , 0 ) , 1 ) == UNSPEC_LTREL_OFFSET && XVECLEN ( XEXP ( value , 0 ) , 0 ) == 1 ) value = s390_pool_offset ( pool , XVECEXP ( XEXP ( value , 0 ) , 0 , 0 ) ) ; insn = emit_label_after ( c -> label , insn ) ; INSN_ADDRESSES_NEW ( insn , - 1 ) ; value = gen_rtx_UNSPEC_VOLATILE ( constant_modes [ i ] , gen_rtvec ( 1 , value ) , UNSPECV_POOL_ENTRY ) ; insn = emit_insn_after ( value , insn ) ; INSN_ADDRESSES_NEW ( insn , - 1 ) ; } insn = emit_insn_after ( gen_pool_align ( GEN_INT ( 2 ) ) , insn ) ; INSN_ADDRESSES_NEW ( insn , - 1 ) ; for ( c = pool -> execute ; c ; c = c -> next ) { insn = emit_label_after ( c -> label , insn ) ; INSN_ADDRESSES_NEW ( insn , - 1 ) ; insn = emit_insn_after ( s390_execute_target ( c -> value ) , insn ) ; INSN_ADDRESSES_NEW ( insn , - 1 ) ; } if ( TARGET_CPU_ZARCH ) { insn = emit_insn_after ( gen_pool_section_end ( ) , insn ) ; INSN_ADDRESSES_NEW ( insn , - 1 ) ; } insn = emit_barrier_after ( insn ) ; INSN_ADDRESSES_NEW ( insn , - 1 ) ; remove_insn ( pool -> pool_insn ) ; } </s>

Dump out the constants in POOL . If REMOTE_LABEL is true , do not emit the pool base label .


<s>
bool
R600VectorRegMerger
::
runOnMachineFunction
(
MachineFunction
&
Fn
)
{
if
(
skipFunction
(
*
Fn
.
getFunction
(
)
)
)
return
false
;
const
R600Subtarget
&
ST
=
Fn
.
getSubtarget
<
R600Subtarget
>
(
)
;
TII
=
ST
.
getInstrInfo
(
)
;
MRI
=
&
Fn
.
getRegInfo
(
)
;
for
(
MachineFunction
::
iterator
MBB
=
Fn
.
begin
(
)
,
MBBe
=
Fn
.
end
(
)
;
MBB
!=
MBBe
;
++
MBB
)
{
MachineBasicBlock
*
MB
=
&
*
MBB
;
PreviousRegSeq
.
clear
(
)
;
PreviousRegSeqByReg
.
clear
(
)
;
PreviousRegSeqByUndefCount
.
clear
(
)
;
for
(
MachineBasicBlock
::
iterator
MII
=
MB
->
begin
(
)
,
MIIE
=
MB
->
end
(
)
;
MII
!=
MIIE
;
++
MII
)
{
MachineInstr
&
MI
=
*
MII
;
if
(
MI
.
getOpcode
(
)
!=
AMDGPU
::
REG_SEQUENCE
)
{
if
(
TII
->
get
(
MI
.
getOpcode
(
)
)
.
TSFlags
&
R600_InstFlag
::
TEX_INST
)
{
unsigned
Reg
=
MI
.
getOperand
(
1
)
.
getReg
(
)
;
for
(
MachineRegisterInfo
::
def_instr_iterator
It
=
MRI
->
def_instr_begin
(
Reg
)
,
E
=
MRI
->
def_instr_end
(
)
;
It
!=
E
;
++
It
)
{
RemoveMI
(
&
(
*
It
)
)
;
}
}
continue
;
}
RegSeqInfo
RSI
(
*
MRI
,
&
MI
)
;
unsigned
Reg
=
MI
.
getOperand
(
0
)
.
getReg
(
)
;
if
(
!
areAllUsesSwizzeable
(
Reg
)
)
continue
;
DEBUG
(
{
dbgs
(
)
<<
"Trying to optimize "
;
MI
.
dump
(
)
;
}
)
;
RegSeqInfo
CandidateRSI
;
std
::
vector
<
std
::
pair
<
unsigned
,
unsigned
>>
RemapChan
;
DEBUG
(
dbgs
(
)
<<
"Using common slots...\n"
;
)
;
if
(
tryMergeUsingCommonSlot
(
RSI
,
CandidateRSI
,
RemapChan
)
)
{
RemoveMI
(
CandidateRSI
.
Instr
)
;
MII
=
RebuildVector
(
&
RSI
,
&
CandidateRSI
,
RemapChan
)
;
trackRSI
(
RSI
)
;
continue
;
}
DEBUG
(
dbgs
(
)
<<
"Using free slots...\n"
;
)
;
RemapChan
.
clear
(
)
;
if
(
tryMergeUsingFreeSlot
(
RSI
,
CandidateRSI
,
RemapChan
)
)
{
RemoveMI
(
CandidateRSI
.
Instr
)
;
MII
=
RebuildVector
(
&
RSI
,
&
CandidateRSI
,
RemapChan
)
;
trackRSI
(
RSI
)
;
continue
;
}
trackRSI
(
RSI
)
;
}
}
</s>

AMDGPU
R600
R600
R600
AMDGPU::REG_SEQUENCE
R600_InstFlag::TEX_INST
1
SI
0
"Trying to optimize "
SI
"Using common slots...\n"
SI
SI
SI
SI
SI
SI
SI
"Using free slots...\n"
SI
SI
SI
SI
SI
SI
SI
SI
SI


<s> bool SPIRVPassConfig :: addRegBankSelect ( ) { disablePass ( & RegBankSelect :: ID ) ; return false ; } </s>

This method should install a register bank selector pass , which assigns register banks to virtual registers without a register class or register banks .


<s> bool SparcAsmParser :: ParseDirective ( AsmToken DirectiveID ) { StringRef IDVal = DirectiveID . getString ( ) ; if ( IDVal == ".register" ) { Parser . eatToEndOfStatement ( ) ; return false ; } if ( IDVal == ".proc" ) { Parser . eatToEndOfStatement ( ) ; return false ; } return true ; } </s>

ParseDirective - Parse a target specific assembler directive This method is deprecated , use 'parseDirective ' instead .


<s> bool VEInstrInfo :: expandPostRAPseudo ( MachineInstr & MI ) const { switch ( MI . getOpcode ( ) ) { case VE :: EXTEND_STACK : { return expandExtendStackPseudo ( MI ) ; } case VE :: EXTEND_STACK_GUARD : { MI . eraseFromParent ( ) ; return true ; } case VE :: GETSTACKTOP : { return expandGetStackTopPseudo ( MI ) ; } } return false ; } </s>

This function is called for all pseudo instructions that remain after register allocation .


<s> LoadInst * X86TargetLowering :: lowerIdempotentRMWIntoFencedLoad ( AtomicRMWInst * AI ) const { unsigned NativeWidth = Subtarget . is64Bit ( ) ? 64 : 32 ; Type * MemType = AI -> getType ( ) ; if ( MemType -> getPrimitiveSizeInBits ( ) > NativeWidth ) return nullptr ; if ( auto * C = dyn_cast < ConstantInt > ( AI -> getValOperand ( ) ) ) if ( AI -> getOperation ( ) == AtomicRMWInst :: Or && C -> isZero ( ) && AI -> use_empty ( ) ) return nullptr ; auto Builder = IRBuilder < > ( AI ) ; Module * M = Builder . GetInsertBlock ( ) -> getParent ( ) -> getParent ( ) ; auto SSID = AI -> getSyncScopeID ( ) ; auto Order = AtomicCmpXchgInst :: getStrongestFailureOrdering ( AI -> getOrdering ( ) ) ; if ( SSID == SyncScope :: SingleThread ) return nullptr ; if ( ! Subtarget . hasMFence ( ) ) return nullptr ; Function * MFence = llvm :: Intrinsic :: getDeclaration ( M , Intrinsic :: x86_sse2_mfence ) ; Builder . CreateCall ( MFence , { } ) ; LoadInst * Loaded = Builder . CreateAlignedLoad ( AI -> getType ( ) , AI -> getPointerOperand ( ) , Align ( AI -> getType ( ) -> getPrimitiveSizeInBits ( ) ) ) ; Loaded -> setAtomic ( Order , SSID ) ; AI -> replaceAllUsesWith ( Loaded ) ; AI -> eraseFromParent ( ) ; return Loaded ; } </s>

On some platforms , an AtomicRMW that never actually modifies the value ( such as fetch_add of 0 ) can be turned into a fence followed by an atomic load .


<s> TargetLowering :: ConstraintWeight AArch64TargetLowering :: getSingleConstraintMatchWeight ( AsmOperandInfo & info , const char * constraint ) const { ConstraintWeight weight = CW_Invalid ; Value * CallOperandVal = info . CallOperandVal ; if ( ! CallOperandVal ) return CW_Default ; Type * type = CallOperandVal -> getType ( ) ; switch ( * constraint ) { default : weight = TargetLowering :: getSingleConstraintMatchWeight ( info , constraint ) ; break ; case 'x' : case 'w' : if ( type -> isFloatingPointTy ( ) || type -> isVectorTy ( ) ) weight = CW_Register ; break ; case 'z' : weight = CW_Constant ; break ; } return weight ; } </s>

Examine constraint string and operand type and determine a weight value .


<s> SDValue SystemZTargetLowering :: PerformDAGCombine ( SDNode * N , DAGCombinerInfo & DCI ) const { switch ( N -> getOpcode ( ) ) { default : break ; case ISD :: ZERO_EXTEND : return combineZERO_EXTEND ( N , DCI ) ; case ISD :: SIGN_EXTEND : return combineSIGN_EXTEND ( N , DCI ) ; case ISD :: SIGN_EXTEND_INREG : return combineSIGN_EXTEND_INREG ( N , DCI ) ; case SystemZISD :: MERGE_HIGH : case SystemZISD :: MERGE_LOW : return combineMERGE ( N , DCI ) ; case ISD :: LOAD : return combineLOAD ( N , DCI ) ; case ISD :: STORE : return combineSTORE ( N , DCI ) ; case ISD :: VECTOR_SHUFFLE : return combineVECTOR_SHUFFLE ( N , DCI ) ; case ISD :: EXTRACT_VECTOR_ELT : return combineEXTRACT_VECTOR_ELT ( N , DCI ) ; case SystemZISD :: JOIN_DWORDS : return combineJOIN_DWORDS ( N , DCI ) ; case ISD :: STRICT_FP_ROUND : case ISD :: FP_ROUND : return combineFP_ROUND ( N , DCI ) ; case ISD :: STRICT_FP_EXTEND : case ISD :: FP_EXTEND : return combineFP_EXTEND ( N , DCI ) ; case ISD :: BSWAP : return combineBSWAP ( N , DCI ) ; case SystemZISD :: BR_CCMASK : return combineBR_CCMASK ( N , DCI ) ; case SystemZISD :: SELECT_CCMASK : return combineSELECT_CCMASK ( N , DCI ) ; case SystemZISD :: GET_CCMASK : return combineGET_CCMASK ( N , DCI ) ; case ISD :: SDIV : case ISD :: UDIV : case ISD :: SREM : case ISD :: UREM : return combineIntDIVREM ( N , DCI ) ; } return SDValue ( ) ; } </s>

This method will be invoked for all target nodes and for any target-independent nodes that the target has registered with invoke it for .


<s> bool MipsInstrInfo :: verifyInstruction ( const MachineInstr & MI , StringRef & ErrInfo ) const { switch ( MI . getOpcode ( ) ) { case Mips :: EXT : case Mips :: EXT_MM : case Mips :: INS : case Mips :: INS_MM : case Mips :: DINS : case Mips :: DINS_MM64R6 : return verifyInsExtInstruction ( MI , ErrInfo , 0 , 32 , 0 , 32 , 0 , 32 ) ; case Mips :: DINSM : case Mips :: DINSM_MM64R6 : return verifyInsExtInstruction ( MI , ErrInfo , 0 , 32 , 1 , 64 , 32 , 64 ) ; case Mips :: DINSU : case Mips :: DINSU_MM64R6 : return verifyInsExtInstruction ( MI , ErrInfo , 32 , 64 , 1 , 32 , 32 , 64 ) ; case Mips :: DEXT : case Mips :: DEXT_MM64R6 : return verifyInsExtInstruction ( MI , ErrInfo , 0 , 32 , 0 , 32 , 0 , 63 ) ; case Mips :: DEXTM : case Mips :: DEXTM_MM64R6 : return verifyInsExtInstruction ( MI , ErrInfo , 0 , 32 , 32 , 64 , 32 , 64 ) ; case Mips :: DEXTU : case Mips :: DEXTU_MM64R6 : return verifyInsExtInstruction ( MI , ErrInfo , 32 , 64 , 0 , 32 , 32 , 64 ) ; default : return true ; } return true ; } </s>

Perform target-specific instruction verification .


"Only optimizing constant comparisons so far"

optimizeCompareInstr - Check if there exists an earlier instruction that operates on the same source operands and sets flags in the same way as Compare ; remove Compare if possible .


<s> bool ARM64TargetLowering :: shouldConvertConstantLoadToIntImm ( const APInt & Imm , Type * Ty ) const { assert ( Ty -> isIntegerTy ( ) ) ; unsigned BitSize = Ty -> getPrimitiveSizeInBits ( ) ; if ( BitSize == 0 ) return false ; int64_t Val = Imm . getSExtValue ( ) ; if ( Val == 0 || ARM64_AM :: isLogicalImmediate ( Val , BitSize ) ) return true ; if ( ( int64_t ) Val < 0 ) Val = ~ Val ; if ( BitSize == 32 ) Val &= ( 1LL << 32 ) - 1 ; unsigned LZ = countLeadingZeros ( ( uint64_t ) Val ) ; unsigned Shift = ( 63 - LZ ) / 16 ; return ( Shift < 3 ) ? true : false ; } </s>

Returns true if it is beneficial to convert a load of a constant to just the constant itself .


<s> unsigned getNumFixupKinds ( ) const override { return TOY :: NumTargetFixupKinds ; } </s>

Get the number of target specific fixup kinds .


<s> bool PPCPassConfig :: addPreISel ( ) { if ( ! DisablePreIncPrep && getOptLevel ( ) != CodeGenOpt :: None ) addPass ( createPPCLoopPreIncPrepPass ( getPPCTargetMachine ( ) ) ) ; if ( ! DisableCTRLoops && getOptLevel ( ) != CodeGenOpt :: None ) addPass ( createPPCCTRLoops ( ) ) ; return false ; } </s>


<s>
MachineBasicBlock
*
GBZ80TargetLowering
::
EmitInstrWithCustomInserter
(
MachineInstr
*
MI
,
MachineBasicBlock
*
MBB
)
const
{
unsigned
Opc
=
MI
->
getOpcode
(
)
;
switch
(
Opc
)
{
case
GBZ80
::
SELECT8
:
case
GBZ80
::
SELECT16
:
return
EmitSelectInstr
(
MI
,
MBB
)
;
case
GBZ80
::
SHL8
:
case
GBZ80
::
LSHR8
:
case
GBZ80
::
ASHR8
:
case
GBZ80
::
SHL16
:
case
GBZ80
::
LSHR16
:
case
GBZ80
::
ASHR16
:
return
EmitShiftInstr
(
MI
,
MBB
)
;
default
:
llvm_unreachable
(
"Invalid Custom Inserter Instruction"
)
;
}
}
</s>

This method should be implemented by targets that mark instructions with the 'usesCustomInserter ' flag .


<s> static void replace_constant_pool_ref ( rtx_insn * insn , rtx ref , rtx offset ) { if ( s390_safe_relative_long_p ( insn ) ) return ; replace_constant_pool_ref_1 ( & PATTERN ( insn ) , ref , offset ) ; } </s>

Replace every reference to the annotated literal pool symbol REF in X by its base plus OFFSET .


<s> bool MSP430TargetLowering :: shouldAvoidTransformToShift ( EVT VT , unsigned Amount ) const { return ! ( Amount == 8 || Amount == 9 || Amount <= 2 ) ; } </s>

Return true if creating a shift of the type by the given amount is not profitable .


<s> static rtx_insn * arc_active_insn ( rtx_insn * insn ) { while ( insn ) { insn = NEXT_INSN ( insn ) ; if ( insn == 0 || ( active_insn_p ( insn ) && NONDEBUG_INSN_P ( insn ) && ! NOTE_P ( insn ) && GET_CODE ( PATTERN ( insn ) ) != UNSPEC_VOLATILE && GET_CODE ( PATTERN ( insn ) ) != PARALLEL ) ) break ; } return insn ; } </s>

Return the next active insn , skiping the inline assembly code .


<s> bool PPCCTRLoops :: runOnFunction ( Function & F ) { LI = & getAnalysis < LoopInfoWrapperPass > ( ) . getLoopInfo ( ) ; SE = & getAnalysis < ScalarEvolution > ( ) ; DT = & getAnalysis < DominatorTreeWrapperPass > ( ) . getDomTree ( ) ; DL = & F . getParent ( ) -> getDataLayout ( ) ; auto * TLIP = getAnalysisIfAvailable < TargetLibraryInfoWrapperPass > ( ) ; LibInfo = TLIP ? & TLIP -> getTLI ( ) : nullptr ; bool MadeChange = false ; for ( LoopInfo :: iterator I = LI -> begin ( ) , E = LI -> end ( ) ; I != E ; ++ I ) { Loop * L = * I ; if ( ! L -> getParentLoop ( ) ) MadeChange |= convertToCTRLoop ( L ) ; } return MadeChange ; } </s>

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .


<s> SDValue AMDGPUTargetLowering :: splitBinaryBitConstantOpImpl ( DAGCombinerInfo & DCI , const SDLoc & SL , unsigned Opc , SDValue LHS , uint32_t ValLo , uint32_t ValHi ) const { SelectionDAG & DAG = DCI . DAG ; SDValue Lo , Hi ; std :: tie ( Lo , Hi ) = split64BitValue ( LHS , DAG ) ; SDValue LoRHS = DAG . getConstant ( ValLo , SL , MVT :: i32 ) ; SDValue HiRHS = DAG . getConstant ( ValHi , SL , MVT :: i32 ) ; SDValue LoAnd = DAG . getNode ( Opc , SL , MVT :: i32 , Lo , LoRHS ) ; SDValue HiAnd = DAG . getNode ( Opc , SL , MVT :: i32 , Hi , HiRHS ) ; DCI . AddToWorklist ( Lo . getNode ( ) ) ; DCI . AddToWorklist ( Hi . getNode ( ) ) ; SDValue Vec = DAG . getBuildVector ( MVT :: v2i32 , SL , { LoAnd , HiAnd } ) ; return DAG . getNode ( ISD :: BITCAST , SL , MVT :: i64 , Vec ) ; } </s>

Split the 64-bit value LHS into two 32-bit components , and perform the binary operation Opc to it with the corresponding constant operands .


<s>
unsigned
SystemZInstrInfo
::
removeBranch
(
MachineBasicBlock
&
MBB
,
int
*
BytesRemoved
)
const
{
assert
(
!
BytesRemoved
&&
"code size not handled"
)
;
MachineBasicBlock
::
iterator
I
=
MBB
.
end
(
)
;
unsigned
Count
=
0
;
while
(
I
!=
MBB
.
begin
(
)
)
{
I
;
if
(
I
->
isDebugInstr
(
)
)
continue
;
if
(
!
I
->
isBranch
(
)
)
break
;
if
(
!
getBranchInfo
(
*
I
)
.
Target
->
isMBB
(
)
)
break
;
I
->
eraseFromParent
(
)
;
I
=
MBB
.
end
(
)
;
++
Count
;
}
return
Count
;
}
</s>

Remove the branching code at the end of the specific MBB .

SystemZ
SystemZ
"code size not handled"
0


<s> virtual void getAnalysisUsage ( AnalysisUsage & AU ) const { AU . addRequired < MachineFunctionAnalysis > ( ) ; AU . addPreserved < MachineFunctionAnalysis > ( ) ; FunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> bool AMDGPUAnnotateKernelFeatures :: runOnSCC ( CallGraphSCC & SCC ) { bool Changed = false ; for ( CallGraphNode * I : SCC ) { if ( I -> getNumReferences ( ) ) NodeList . push_back ( I ) ; else { processUniformWorkGroupAttribute ( ) ; NodeList . clear ( ) ; } Function * F = I -> getFunction ( ) ; if ( ! F || F -> isDeclaration ( ) || AMDGPU :: isGraphics ( F -> getCallingConv ( ) ) ) continue ; Changed |= addFeatureAttributes ( * F ) ; } return Changed ; } </s>

runOnSCC - This method should be implemented by the subclass to perform whatever action is necessary for the specified SCC .


<s> enum reg_class mips_secondary_reload_class ( enum reg_class rclass , machine_mode mode , rtx x , bool ) { int regno ; if ( mips_dangerous_for_la25_p ( x ) ) return reg_class_subset_p ( rclass , LEA_REGS ) ? NO_REGS : LEA_REGS ; regno = true_regnum ( x ) ; if ( TARGET_MIPS16 ) { if ( ! reg_class_subset_p ( rclass , M16_REGS ) && ! M16_REG_P ( regno ) ) return M16_REGS ; return NO_REGS ; } if ( reg_class_subset_p ( rclass , ACC_REGS ) ) return GP_REG_P ( regno ) ? NO_REGS : GR_REGS ; if ( ACC_REG_P ( regno ) ) return reg_class_subset_p ( rclass , GR_REGS ) ? NO_REGS : GR_REGS ; if ( reg_class_subset_p ( rclass , FP_REGS ) ) { if ( regno < 0 || ( MEM_P ( x ) && ( GET_MODE_SIZE ( mode ) == 4 || GET_MODE_SIZE ( mode ) == 8 ) ) ) return NO_REGS ; if ( MEM_P ( x ) && MSA_SUPPORTED_MODE_P ( mode ) ) return NO_REGS ; if ( GP_REG_P ( regno ) || x == CONST0_RTX ( mode ) ) return NO_REGS ; if ( CONSTANT_P ( x ) && ! targetm . cannot_force_const_mem ( mode , x ) ) return NO_REGS ; if ( FP_REG_P ( regno ) && mips_mode_ok_for_mov_fmt_p ( mode ) ) return NO_REGS ; return GR_REGS ; } if ( FP_REG_P ( regno ) ) return reg_class_subset_p ( rclass , GR_REGS ) ? NO_REGS : GR_REGS ; return NO_REGS ; } </s>

This function returns the register class required for a secondary register when copying between one of the registers in CLASS , and X , using MODE . If IN_P is nonzero , the copy is going from X to the register , otherwise the register is the source . A return value of NO_REGS means that no secondary register is required .


<s> std :: pair < uint16_t , uint16_t > X86InstrInfo :: getExecutionDomain ( const MachineInstr * MI ) const { uint16_t domain = ( MI -> getDesc ( ) . TSFlags >> X86II :: SSEDomainShift ) & 3 ; bool hasAVX2 = TM . getSubtarget < X86Subtarget > ( ) . hasAVX2 ( ) ; uint16_t validDomains = 0 ; if ( domain && lookup ( MI -> getOpcode ( ) , domain ) ) validDomains = 0xe ; else if ( domain && lookupAVX2 ( MI -> getOpcode ( ) , domain ) ) validDomains = hasAVX2 ? 0xe : 0x6 ; return std :: make_pair ( domain , validDomains ) ; } </s>

Return the current execution domain and bit mask of possible domains for instruction .


<s> static tree ix86_fn_abi_va_list ( tree fndecl ) { if ( ! TARGET_64BIT ) return va_list_type_node ; gcc_assert ( fndecl != NULL_TREE ) ; if ( ix86_function_abi ( ( const_tree ) fndecl ) == MS_ABI ) return ms_va_list_type_node ; else return sysv_va_list_type_node ; } </s>

This function returns the calling abi specific va_list type node . It returns the FNDECL specific va_list type .


<s> unsigned PPCTargetLowering :: getJumpTableEncoding ( ) const { if ( isJumpTableRelative ( ) ) return MachineJumpTableInfo :: EK_LabelDifference32 ; return TargetLowering :: getJumpTableEncoding ( ) ; } </s>

Return the entry encoding for a jump table in the current function .


<s>
unsigned
getReg
(
)
const
{
assert
(
(
Kind
==
k_Register
||
Kind
==
k_Memri
)
&&
"Invalid access!"
)
;
return
RegImm
.
Reg
;
}
</s>

Returns the register associated with this edge .


Add common target configurable passes that perform LLVM IR to IR transforms following machine independent optimization .

NVPTX NVPTX NVPTX NVPTX NVPTX NVPTX NVPTX NVPTX


<s> static fixed_size_mode mips_get_reg_raw_mode ( int regno ) { if ( TARGET_FLOATXX && FP_REG_P ( regno ) ) return DFmode ; return default_get_reg_raw_mode ( regno ) ; } </s>


<s> void emitELFSize ( MCSymbol * Symbol , const MCExpr * Value ) override { } </s>


<s> static rtx riscv_legitimize_tls_address ( rtx loc ) { rtx dest , tp , tmp ; enum tls_model model = SYMBOL_REF_TLS_MODEL ( loc ) ; if ( ! flag_pic ) model = TLS_MODEL_LOCAL_EXEC ; switch ( model ) { case TLS_MODEL_LOCAL_DYNAMIC : case TLS_MODEL_GLOBAL_DYNAMIC : tmp = gen_rtx_REG ( Pmode , GP_RETURN ) ; dest = gen_reg_rtx ( Pmode ) ; emit_libcall_block ( riscv_call_tls_get_addr ( loc , tmp ) , dest , tmp , loc ) ; break ; case TLS_MODEL_INITIAL_EXEC : tp = gen_rtx_REG ( Pmode , THREAD_POINTER_REGNUM ) ; tmp = gen_reg_rtx ( Pmode ) ; emit_insn ( riscv_got_load_tls_ie ( tmp , loc ) ) ; dest = gen_reg_rtx ( Pmode ) ; emit_insn ( gen_add3_insn ( dest , tmp , tp ) ) ; break ; case TLS_MODEL_LOCAL_EXEC : tmp = riscv_unspec_offset_high ( NULL , loc , SYMBOL_TLS_LE ) ; dest = gen_reg_rtx ( Pmode ) ; emit_insn ( riscv_tls_add_tp_le ( dest , tmp , loc ) ) ; dest = gen_rtx_LO_SUM ( Pmode , dest , riscv_unspec_address ( loc , SYMBOL_TLS_LE ) ) ; break ; default : gcc_unreachable ( ) ; } return dest ; } </s>

Generate the code to access LOC , a thread-local SYMBOL_REF , and return its address . The return value will be both a valid address and a valid SET_SRC ( either a REG or a LO_SUM ) .


<s> bool s390_check_symref_alignment ( rtx addr , HOST_WIDE_INT alignment ) { HOST_WIDE_INT addend ; rtx symref ; if ( ! s390_loadrelative_operand_p ( addr , & symref , & addend ) ) return false ; if ( addend & ( alignment - 1 ) ) return false ; if ( GET_CODE ( symref ) == SYMBOL_REF && ! SYMBOL_REF_NOT_NATURALLY_ALIGNED_P ( symref ) ) return true ; if ( GET_CODE ( symref ) == UNSPEC && alignment <= UNITS_PER_LONG ) return true ; return false ; } </s>

Return true if ADDR is SYMBOL_REF + addend with addend being a multiple of ALIGNMENT and the SYMBOL_REF being naturally aligned .


<s> static bool r10k_safe_address_p ( rtx x , rtx_insn * insn ) { rtx base , offset ; HOST_WIDE_INT offset_val ; x = r10k_simplify_address ( x , insn ) ; mips_split_plus ( x , & base , & offset_val ) ; if ( base == virtual_incoming_args_rtx && offset_val >= - cfun -> machine -> frame . total_size && offset_val < cfun -> machine -> frame . args_size ) return true ; if ( CONST_INT_P ( x ) ) return r10k_uncached_address_p ( INTVAL ( x ) ) ; split_const ( x , & base , & offset ) ; return offset_within_block_p ( base , INTVAL ( offset ) ) ; } </s>

Return true if we can prove that an access to address X in instruction INSN would be safe from R10K speculation . This X is a general expression ; it might not be a legitimate address .


<s> bool XCoreTargetMachine :: addInstSelector ( PassManagerBase & PM ) { PM . add ( createXCoreISelDag ( * this , getOptLevel ( ) ) ) ; return false ; } </s>

addInstSelector - This method should install an instruction selector pass , which converts from LLVM code to machine instructions .


<s> static void mep_rewrite_mult ( rtx_insn * insn , rtx pattern ) { rtx hi_clobber ; hi_clobber = XVECEXP ( pattern , 0 , XVECLEN ( pattern , 0 ) - 1 ) ; XEXP ( hi_clobber , 0 ) = gen_rtx_REG ( SImode , HI_REGNO ) ; PATTERN ( insn ) = pattern ; INSN_CODE ( insn ) = - 1 ; } </s>

Replace INSN 's pattern with PATTERN , a multiplication PARALLEL . Change the last element of PATTERN from ( clobber ( scratch : SI ) ) to ( clobber ( reg : SI HI_REGNO ) ) .


<s> bool AMDGPUDAGToDAGISel :: runOnMachineFunction ( MachineFunction & MF ) { DominatorTree & DT = getAnalysis < DominatorTreeWrapperPass > ( ) . getDomTree ( ) ; LoopInfo * LI = & getAnalysis < LoopInfoWrapperPass > ( ) . getLoopInfo ( ) ; for ( auto & L : LI -> getLoopsInPreorder ( ) ) { assert ( L -> isLCSSAForm ( DT ) ) ; } Subtarget = & MF . getSubtarget < GCNSubtarget > ( ) ; Mode = AMDGPU :: SIModeRegisterDefaults ( MF . getFunction ( ) ) ; return SelectionDAGISel :: runOnMachineFunction ( MF ) ; } </s>

runOnMachineFunction - Emit the function body .


<s> void PPCFrameLowering :: determineCalleeSaves ( MachineFunction & MF , BitVector & SavedRegs , RegScavenger * RS ) const { TargetFrameLowering :: determineCalleeSaves ( MF , SavedRegs , RS ) ; const PPCRegisterInfo * RegInfo = static_cast < const PPCRegisterInfo * > ( Subtarget . getRegisterInfo ( ) ) ; PPCFunctionInfo * FI = MF . getInfo < PPCFunctionInfo > ( ) ; unsigned LR = RegInfo -> getRARegister ( ) ; FI -> setMustSaveLR ( MustSaveLR ( MF , LR ) ) ; SavedRegs . reset ( LR ) ; int FPSI = FI -> getFramePointerSaveIndex ( ) ; bool isPPC64 = Subtarget . isPPC64 ( ) ; bool isDarwinABI = Subtarget . isDarwinABI ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; if ( ! FPSI && needsFP ( MF ) ) { int FPOffset = getFramePointerSaveOffset ( ) ; FPSI = MFI -> CreateFixedObject ( isPPC64 ? 8 : 4 , FPOffset , true ) ; FI -> setFramePointerSaveIndex ( FPSI ) ; } int BPSI = FI -> getBasePointerSaveIndex ( ) ; if ( ! BPSI && RegInfo -> hasBasePointer ( MF ) ) { int BPOffset = getBasePointerSaveOffset ( ) ; BPSI = MFI -> CreateFixedObject ( isPPC64 ? 8 : 4 , BPOffset , true ) ; FI -> setBasePointerSaveIndex ( BPSI ) ; } if ( FI -> usesPICBase ( ) ) { int PBPSI = MFI -> CreateFixedObject ( 4 , - 8 , true ) ; FI -> setPICBasePointerSaveIndex ( PBPSI ) ; } int TCSPDelta = 0 ; if ( MF . getTarget ( ) . Options . GuaranteedTailCallOpt && ( TCSPDelta = FI -> getTailCallSPDelta ( ) ) < 0 ) { MFI -> CreateFixedObject ( - 1 * TCSPDelta , TCSPDelta , true ) ; } if ( ! isPPC64 && ! isDarwinABI && ( SavedRegs . test ( PPC :: CR2 ) || SavedRegs . test ( PPC :: CR3 ) || SavedRegs . test ( PPC :: CR4 ) ) ) { int FrameIdx = MFI -> CreateFixedObject ( ( uint64_t ) 4 , ( int64_t ) - 4 , true ) ; FI -> setCRSpillFrameIndex ( FrameIdx ) ; } } </s>

This method determines which of the registers reported by TargetRegisterInfo : :getCalleeSavedRegs ( ) should actually get saved .


<s> void assignValueToReg ( unsigned ValVReg , unsigned PhysReg , CCValAssign & VA ) override { markPhysRegUsed ( PhysReg ) ; switch ( VA . getLocInfo ( ) ) { default : MIRBuilder . buildCopy ( ValVReg , PhysReg ) ; break ; case CCValAssign :: LocInfo :: SExt : case CCValAssign :: LocInfo :: ZExt : case CCValAssign :: LocInfo :: AExt : { auto Copy = MIRBuilder . buildCopy ( LLT { VA . getLocVT ( ) } , PhysReg ) ; MIRBuilder . buildTrunc ( ValVReg , Copy ) ; break ; } } } </s>

The specified value has been assigned to a physical register , handle the appropriate COPY ( either to or from ) and mark any relevant uses/defines as needed .


<s> static SDValue getTargetNode ( JumpTableSDNode * N , SDLoc DL , EVT Ty , SelectionDAG & DAG , unsigned Flags ) { return DAG . getTargetJumpTable ( N -> getIndex ( ) , Ty , Flags ) ; } </s>

Retrieve the target node this edge connects to .


<s> bool MipsOptimizeMathLibCalls :: runOnFunction ( Function & F ) { if ( DisableOpt ) return false ; const MipsSubtarget & Subtarget = TM . getSubtarget < MipsSubtarget > ( ) ; if ( Subtarget . inMips16Mode ( ) ) return false ; bool Changed = false ; Function :: iterator CurrBB ; const TargetLibraryInfo * LibInfo = & getAnalysis < TargetLibraryInfo > ( ) ; for ( Function :: iterator BB = F . begin ( ) , BE = F . end ( ) ; BB != BE ; ) { CurrBB = BB ++ ; for ( BasicBlock :: iterator II = CurrBB -> begin ( ) , IE = CurrBB -> end ( ) ; II != IE ; ++ II ) { CallInst * Call = dyn_cast < CallInst > ( & * II ) ; Function * CalledFunc ; if ( ! Call || ! ( CalledFunc = Call -> getCalledFunction ( ) ) ) continue ; LibFunc :: Func LibFunc ; Attribute A = CalledFunc -> getAttributes ( ) . getAttribute ( AttributeSet :: FunctionIndex , "use-soft-float" ) ; if ( ( A . isStringAttribute ( ) && ( A . getValueAsString ( ) == "true" ) ) || TM . Options . UseSoftFloat ) continue ; if ( CalledFunc -> hasLocalLinkage ( ) || ! CalledFunc -> hasName ( ) || ! LibInfo -> getLibFunc ( CalledFunc -> getName ( ) , LibFunc ) ) continue ; switch ( LibFunc ) { case LibFunc :: sqrtf : case LibFunc :: sqrt : if ( optimizeSQRT ( Call , CalledFunc , * CurrBB , BB ) ) break ; continue ; default : continue ; } Changed = true ; break ; } } return Changed ; } </s>

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .

Mips Mips Mips Mips Mips "use-soft-float" "true"


<s> static bool hasOneUse ( unsigned Reg , MachineInstr * Def , MachineRegisterInfo & MRI , MachineDominatorTree & MDT , LiveIntervals & LIS ) { if ( MRI . hasOneUse ( Reg ) ) return true ; bool HasOne = false ; const LiveInterval & LI = LIS . getInterval ( Reg ) ; const VNInfo * DefVNI = LI . getVNInfoAt ( LIS . getInstructionIndex ( * Def ) . getRegSlot ( ) ) ; assert ( DefVNI ) ; for ( auto & I : MRI . use_nodbg_operands ( Reg ) ) { const auto & Result = LI . Query ( LIS . getInstructionIndex ( * I . getParent ( ) ) ) ; if ( Result . valueIn ( ) == DefVNI ) { if ( ! Result . isKill ( ) ) return false ; if ( HasOne ) return false ; HasOne = true ; } } return HasOne ; } </s>

Return true if there is exactly one node using value ResNo of Node .


<s> bool AMDGPUAsmPrinter :: lowerOperand ( const MachineOperand & MO , MCOperand & MCOp ) const { const GCNSubtarget & STI = MF -> getSubtarget < GCNSubtarget > ( ) ; AMDGPUMCInstLower MCInstLowering ( OutContext , STI , * this ) ; return MCInstLowering . lowerOperand ( MO , MCOp ) ; } </s>

Wrapper for MCInstLowering.lowerOperand ( ) for the tblgen'erated pseudo lowering .


<s> static unsigned estimateStackSize ( MachineFunction & MF ) { const MachineFrameInfo * FFI = MF . getFrameInfo ( ) ; int Offset = 0 ; for ( int i = FFI -> getObjectIndexBegin ( ) ; i != 0 ; ++ i ) { int FixedOff = - FFI -> getObjectOffset ( i ) ; if ( FixedOff > Offset ) Offset = FixedOff ; } for ( unsigned i = 0 , e = FFI -> getObjectIndexEnd ( ) ; i != e ; ++ i ) { if ( FFI -> isDeadObjectIndex ( i ) ) continue ; Offset += FFI -> getObjectSize ( i ) ; unsigned Align = FFI -> getObjectAlignment ( i ) ; Offset = ( Offset + Align - 1 ) / Align * Align ; } return ( unsigned ) Offset ; } </s>

Estimate and return the size of the stack frame .


<s> EVT HexagonTargetLowering :: getOptimalMemOpType ( uint64_t Size , unsigned DstAlign , unsigned SrcAlign , bool IsMemset , bool ZeroMemset , bool MemcpyStrSrc , MachineFunction & MF ) const { auto Aligned = [ ] ( unsigned GivenA , unsigned MinA ) -> bool { return ( GivenA % MinA ) == 0 ; } ; if ( Size >= 8 && Aligned ( DstAlign , 8 ) && ( IsMemset || Aligned ( SrcAlign , 8 ) ) ) return MVT :: i64 ; if ( Size >= 4 && Aligned ( DstAlign , 4 ) && ( IsMemset || Aligned ( SrcAlign , 4 ) ) ) return MVT :: i32 ; if ( Size >= 2 && Aligned ( DstAlign , 2 ) && ( IsMemset || Aligned ( SrcAlign , 2 ) ) ) return MVT :: i16 ; return MVT :: Other ; } </s>

It returns EVT : :Other if the type should be determined using generic target-independent logic .


<s> unsigned getABIAlignmentForCallingConv ( Type * ArgTy , DataLayout DL ) const override { if ( ArgTy -> isVectorTy ( ) ) return std :: min ( DL . getABITypeAlignment ( ArgTy ) , 8U ) ; return DL . getABITypeAlignment ( ArgTy ) ; } </s>

Return the correct alignment for the current calling convention .


<s> void arm_split_compare_and_swap ( rtx operands [ ] ) { rtx rval , mem , oldval , newval , neg_bval , mod_s_rtx ; machine_mode mode ; enum memmodel mod_s , mod_f ; bool is_weak ; rtx_code_label * label1 , * label2 ; rtx x , cond ; rval = operands [ 1 ] ; mem = operands [ 2 ] ; oldval = operands [ 3 ] ; newval = operands [ 4 ] ; is_weak = ( operands [ 5 ] != const0_rtx ) ; mod_s_rtx = operands [ 6 ] ; mod_s = memmodel_from_int ( INTVAL ( mod_s_rtx ) ) ; mod_f = memmodel_from_int ( INTVAL ( operands [ 7 ] ) ) ; neg_bval = TARGET_THUMB1 ? operands [ 0 ] : operands [ 8 ] ; mode = GET_MODE ( mem ) ; bool is_armv8_sync = arm_arch8 && is_mm_sync ( mod_s ) ; bool use_acquire = TARGET_HAVE_LDACQ && aarch_mm_needs_acquire ( mod_s_rtx ) ; bool use_release = TARGET_HAVE_LDACQ && aarch_mm_needs_release ( mod_s_rtx ) ; if ( is_armv8_sync ) use_acquire = false ; if ( ! ( use_acquire || use_release ) ) arm_pre_atomic_barrier ( mod_s ) ; label1 = NULL ; if ( ! is_weak ) { label1 = gen_label_rtx ( ) ; emit_label ( label1 ) ; } label2 = gen_label_rtx ( ) ; arm_emit_load_exclusive ( mode , rval , mem , use_acquire ) ; if ( TARGET_32BIT ) { cond = arm_gen_compare_reg ( NE , rval , oldval , neg_bval ) ; x = gen_rtx_NE ( VOIDmode , cond , const0_rtx ) ; x = gen_rtx_IF_THEN_ELSE ( VOIDmode , x , gen_rtx_LABEL_REF ( Pmode , label2 ) , pc_rtx ) ; emit_unlikely_jump ( gen_rtx_SET ( pc_rtx , x ) ) ; } else { cond = gen_rtx_NE ( VOIDmode , rval , oldval ) ; if ( thumb1_cmpneg_operand ( oldval , SImode ) ) { rtx src = rval ; if ( ! satisfies_constraint_L ( oldval ) ) { gcc_assert ( satisfies_constraint_J ( oldval ) ) ; emit_move_insn ( neg_bval , rval ) ; src = neg_bval ; } emit_unlikely_jump ( gen_cbranchsi4_neg_late ( neg_bval , src , oldval , label2 , cond ) ) ; } else { emit_move_insn ( neg_bval , const1_rtx ) ; emit_unlikely_jump ( gen_cbranchsi4_insn ( cond , rval , oldval , label2 ) ) ; } } arm_emit_store_exclusive ( mode , neg_bval , mem , newval , use_release ) ; if ( TARGET_32BIT ) { cond = gen_rtx_REG ( CCmode , CC_REGNUM ) ; x = gen_rtx_COMPARE ( CCmode , neg_bval , const0_rtx ) ; emit_insn ( gen_rtx_SET ( cond , x ) ) ; } if ( ! is_weak ) { x = gen_rtx_NE ( VOIDmode , neg_bval , const0_rtx ) ; emit_unlikely_jump ( gen_cbranchsi4 ( x , neg_bval , const0_rtx , label1 ) ) ; } if ( ! is_mm_relaxed ( mod_f ) ) emit_label ( label2 ) ; if ( is_armv8_sync || ! ( use_acquire || use_release ) ) arm_post_atomic_barrier ( mod_s ) ; if ( is_mm_relaxed ( mod_f ) ) emit_label ( label2 ) ; } </s>

Split a compare and swap pattern . It is IMPLEMENTATION DEFINED whether another memory store between the load-exclusive and store-exclusive can reset the monitor from Exclusive to Open state . This means we must wait until after reload to split the pattern , lest we get a register spill in the middle of the atomic sequence .


<s> bool PPCTargetLowering :: SelectAddressRegReg ( SDValue N , SDValue & Base , SDValue & Index , SelectionDAG & DAG , unsigned EncodingAlignment ) const { int16_t imm = 0 ; if ( N . getOpcode ( ) == ISD :: ADD ) { if ( hasSPE ( ) && SelectAddressEVXRegReg ( N , Base , Index , DAG ) ) return true ; if ( isIntS16Immediate ( N . getOperand ( 1 ) , imm ) && ( ! EncodingAlignment || ! ( imm % EncodingAlignment ) ) ) return false ; if ( N . getOperand ( 1 ) . getOpcode ( ) == PPCISD :: Lo ) return false ; Base = N . getOperand ( 0 ) ; Index = N . getOperand ( 1 ) ; return true ; } else if ( N . getOpcode ( ) == ISD :: OR ) { if ( isIntS16Immediate ( N . getOperand ( 1 ) , imm ) && ( ! EncodingAlignment || ! ( imm % EncodingAlignment ) ) ) return false ; KnownBits LHSKnown = DAG . computeKnownBits ( N . getOperand ( 0 ) ) ; if ( LHSKnown . Zero . getBoolValue ( ) ) { KnownBits RHSKnown = DAG . computeKnownBits ( N . getOperand ( 1 ) ) ; if ( ~ ( LHSKnown . Zero | RHSKnown . Zero ) == 0 ) { Base = N . getOperand ( 0 ) ; Index = N . getOperand ( 1 ) ; return true ; } } } return false ; } </s>

SelectAddressRegReg - Given the specified addressed , check to see if it can be more efficiently represented as [ r+imm ] .


<s> std :: pair < unsigned , unsigned > getWavesPerEU ( const Function & F ) const { std :: pair < unsigned , unsigned > FlatWorkGroupSizes = getFlatWorkGroupSizes ( F ) ; return getWavesPerEU ( F , FlatWorkGroupSizes ) ; } </s>

Overload which uses the specified values for the flat work group sizes , rather than querying the function itself .


<s> unsigned HexagonInstrInfo :: getInlineAsmLength ( const char * Str , const MCAsmInfo & MAI ) const { StringRef AStr ( Str ) ; bool atInsnStart = true ; unsigned Length = 0 ; for ( ; * Str ; ++ Str ) { if ( * Str == '\n' || strncmp ( Str , MAI . getSeparatorString ( ) , strlen ( MAI . getSeparatorString ( ) ) ) == 0 ) atInsnStart = true ; if ( atInsnStart && ! std :: isspace ( static_cast < unsigned char > ( * Str ) ) ) { Length += MAI . getMaxInstLength ( ) ; atInsnStart = false ; } if ( atInsnStart && strncmp ( Str , MAI . getCommentString ( ) . data ( ) , MAI . getCommentString ( ) . size ( ) ) == 0 ) atInsnStart = false ; } StringRef Occ ( "##" ) ; Length += AStr . count ( Occ ) * 4 ; return Length ; } </s>

Measure the specified inline asm to determine an approximation of its length .


"insertBranch must not be told to insert a fallthrough"

"RISCV branch conditions have two components!"

Insert branch code into the end of the specified MachineBasicBlock .


<s> static const char * byte_reg ( rtx x , int b ) { static const char * const names_small [ ] = { "r0l" , "r0h" , "r1l" , "r1h" , "r2l" , "r2h" , "r3l" , "r3h" , "r4l" , "r4h" , "r5l" , "r5h" , "r6l" , "r6h" , "r7l" , "r7h" } ; gcc_assert ( REG_P ( x ) ) ; return names_small [ REGNO ( x ) * 2 + b ] ; } </s>

Return the byte register name for a register rtx X . B should be 0 if you want a lower byte register . B should be 1 if you want an upper byte register .


<s> void PPCBranchCoalescing :: initialize ( MachineFunction & MF ) { MDT = & getAnalysis < MachineDominatorTree > ( ) ; MPDT = & getAnalysis < MachinePostDominatorTree > ( ) ; TII = MF . getSubtarget ( ) . getInstrInfo ( ) ; MRI = & MF . getRegInfo ( ) ; } </s>

Initialize the strategy after building the DAG for a new region .


"Should use MaskedValueIsZero if you don't know whether Op"

Determine which of the bits specified in Mask are known to be either zero or one and return them in the KnownZero/KnownOne bitsets .


"No expandLargeImm(SP, StackSize, false, TII, MBB, MBBI, dl);"


<s>
static
void
output_compadr
(
rtx
operands
[
2
]
)
{
output_asm_insn
(
"lea %a1,%0"
,
operands
)
;
}
</s>

Output assembler to load address OPERANDS [ 0 ] to register OPERANDS [ 1 ] .


<s> bool runOnMachineFunction ( MachineFunction & MF ) override { ARMFunctionInfo * AFI = MF . getInfo < ARMFunctionInfo > ( ) ; if ( AFI -> getGlobalBaseReg ( ) == 0 ) return false ; const ARMSubtarget & STI = static_cast < const ARMSubtarget & > ( MF . getSubtarget ( ) ) ; const TargetMachine & TM = MF . getTarget ( ) ; if ( TM . getRelocationModel ( ) != Reloc :: PIC_ ) return false ; LLVMContext * Context = & MF . getFunction ( ) -> getContext ( ) ; unsigned ARMPCLabelIndex = AFI -> createPICLabelUId ( ) ; unsigned PCAdj = STI . isThumb ( ) ? 4 : 8 ; ARMConstantPoolValue * CPV = ARMConstantPoolSymbol :: Create ( * Context , "_GLOBAL_OFFSET_TABLE_" , ARMPCLabelIndex , PCAdj ) ; unsigned Align = TM . getDataLayout ( ) -> getPrefTypeAlignment ( Type :: getInt32PtrTy ( * Context ) ) ; unsigned Idx = MF . getConstantPool ( ) -> getConstantPoolIndex ( CPV , Align ) ; MachineBasicBlock & FirstMBB = MF . front ( ) ; MachineBasicBlock :: iterator MBBI = FirstMBB . begin ( ) ; DebugLoc DL = FirstMBB . findDebugLoc ( MBBI ) ; unsigned TempReg = MF . getRegInfo ( ) . createVirtualRegister ( & ARM :: rGPRRegClass ) ; unsigned Opc = STI . isThumb2 ( ) ? ARM :: t2LDRpci : ARM :: LDRcp ; const TargetInstrInfo & TII = * STI . getInstrInfo ( ) ; MachineInstrBuilder MIB = BuildMI ( FirstMBB , MBBI , DL , TII . get ( Opc ) , TempReg ) . addConstantPoolIndex ( Idx ) ; if ( Opc == ARM :: LDRcp ) MIB . addImm ( 0 ) ; AddDefaultPred ( MIB ) ; unsigned GlobalBaseReg = AFI -> getGlobalBaseReg ( ) ; Opc = STI . isThumb2 ( ) ? ARM :: tPICADD : ARM :: PICADD ; MIB = BuildMI ( FirstMBB , MBBI , DL , TII . get ( Opc ) , GlobalBaseReg ) . addReg ( TempReg ) . addImm ( ARMPCLabelIndex ) ; if ( Opc == ARM :: PICADD ) AddDefaultPred ( MIB ) ; return true ; } </s>

runOnMachineFunction - Emit the function body .

ARM ARM ARM 0 ARM ARM ARM 4 8 ARM ARM "_GLOBAL_OFFSET_TABLE_" ARM ARM::rGPRRegClass ARM::t2LDRpci ARM::LDRcp ARM::LDRcp 0 ARM::tPICADD ARM::PICADD ARM ARM::PICADD


<s> const P2InstrInfo * getInstrInfo ( ) const override { return & InstrInfo ; } </s>


<s> bool M68kInstructionSelector :: select ( MachineInstr & I ) { if ( ! isPreISelGenericOpcode ( I . getOpcode ( ) ) ) return true ; if ( selectImpl ( I , * CoverageInfo ) ) return true ; return false ; } </s>

Select the ( possibly generic ) instruction I to only use target-specific opcodes .


<s>
void
X86DAGToDAGISel
::
PreprocessISelDAG
(
)
{
OptForSize
=
MF
->
getFunction
(
)
->
optForSize
(
)
;
OptForMinSize
=
MF
->
getFunction
(
)
->
optForMinSize
(
)
;
assert
(
(
!
OptForMinSize
||
OptForSize
)
&&
"OptForMinSize implies OptForSize"
)
;
for
(
SelectionDAG
::
allnodes_iterator
I
=
CurDAG
->
allnodes_begin
(
)
,
E
=
CurDAG
->
allnodes_end
(
)
;
I
!=
E
;
)
{
SDNode
*
N
=
&
*
I
++
;
if
(
OptLevel
!=
CodeGenOpt
::
&&
(
(
(
N
->
getOpcode
(
)
==
X86ISD
::
CALL
||
N
->
getOpcode
(
)
==
X86ISD
::
CPS_CALL
)
&&
!
Subtarget
->
callRegIndirect
(
)
)
||
(
N
->
getOpcode
(
)
==
X86ISD
::
TC_RETURN
&&
(
Subtarget
->
is64Bit
(
)
||
!
getTargetMachine
(
)
.
isPositionIndependent
(
)
)
)
)
)
{
bool
HasCallSeq
=
N
->
getOpcode
(
)
==
X86ISD
::
CALL
||
N
->
getOpcode
(
)
==
X86ISD
::
CPS_CALL
;
SDValue
Chain
=
N
->
getOperand
(
0
)
;
SDValue
Load
=
N
->
getOperand
(
1
)
;
if
(
!
isCalleeLoad
(
Load
,
Chain
,
HasCallSeq
)
)
continue
;
moveBelowOrigChain
(
CurDAG
,
Load
,
SDValue
(
N
,
0
)
,
Chain
)
;
++
NumLoadMoved
;
continue
;
}
if
(
N
->
getOpcode
(
)
!=
ISD
::
FP_ROUND
&&
N
->
getOpcode
(
)
!=
ISD
::
FP_EXTEND
)
continue
;
MVT
SrcVT
=
N
->
getOperand
(
0
)
.
getSimpleValueType
(
)
;
MVT
DstVT
=
N
->
getSimpleValueType
(
0
)
;
if
(
SrcVT
.
isVector
(
)
||
DstVT
.
isVector
(
)
)
continue
;
const
X86TargetLowering
*
X86Lowering
=
static_cast
<
const
X86TargetLowering
*
>
(
TLI
)
;
bool
SrcIsSSE
=
X86Lowering
->
isScalarFPTypeInSSEReg
(
SrcVT
)
;
bool
DstIsSSE
=
X86Lowering
->
isScalarFPTypeInSSEReg
(
DstVT
)
;
if
(
SrcIsSSE
&&
DstIsSSE
)
continue
;
if
(
!
SrcIsSSE
&&
!
DstIsSSE
)
{
if
(
N
->
getOpcode
(
)
==
ISD
::
FP_EXTEND
)
continue
;
if
(
N
->
getConstantOperandVal
(
1
)
)
continue
;
}
MVT
MemVT
;
if
(
N
->
getOpcode
(
)
==
ISD
::
FP_ROUND
)
MemVT
=
DstVT
;
else
MemVT
=
SrcIsSSE
SrcVT
:
DstVT
;
SDValue
MemTmp
=
CurDAG
->
CreateStackTemporary
(
MemVT
)
;
SDLoc
dl
(
N
)
;
SDValue
Store
=
CurDAG
->
getTruncStore
(
CurDAG
->
getEntryNode
(
)
,
dl
,
N
->
getOperand
(
0
)
,
MemTmp
,
MachinePointerInfo
(
)
,
MemVT
)
;
SDValue
Result
=
CurDAG
->
getExtLoad
(
ISD
::
EXTLOAD
,
dl
,
DstVT
,
Store
,
MemTmp
,
MachinePointerInfo
(
)
,
MemVT
)
;
I
;
CurDAG
->
ReplaceAllUsesOfValueWith
(
SDValue
(
N
,
0
)
,
Result
)
;
++
I
;
CurDAG
->
DeleteNode
(
N
)
;
}
}
</s>

PreprocessISelDAG - This hook allows targets to hack on the graph before instruction selection starts .


<s> bool MMIXInstrInfo :: expandPostRAPseudo ( MachineInstr & MI ) const { switch ( MI . getOpcode ( ) ) { default : return false ; case MMIX :: LDI : expandLDImm ( MI ) ; return true ; case MMIX :: LDA : expandLDAddr ( MI ) ; return true ; } } </s>

This function is called for all pseudo instructions that remain after register allocation .


<s> MCSymbol * WebAssemblyMCInstLower :: GetExternalSymbolSymbol ( const MachineOperand & MO ) const { return Printer . getOrCreateWasmSymbol ( MO . getSymbolName ( ) ) ; } </s>

Return the MCSymbol for the specified ExternalSymbol .


<s> static const char * getName ( ) { return DEBUG_TYPE ; } </s>

Return a string with the name of the plan and the applicable VFs and UFs .


<s>
static
void
const_double_split
(
rtx
x
,
HOST_WIDE_INT
*
p_high
,
HOST_WIDE_INT
*
p_low
)
{
if
(
GET_CODE
(
x
)
==
CONST_DOUBLE
)
{
long
t
[
2
]
;
switch
(
GET_MODE
(
x
)
)
{
case
DFmode
:
REAL_VALUE_TO_TARGET_DOUBLE
(
*
CONST_DOUBLE_REAL_VALUE
(
x
)
,
t
)
;
*
p_high
=
t
[
1
]
;
*
p_low
=
t
[
0
]
;
return
;
case
SFmode
:
REAL_VALUE_TO_TARGET_SINGLE
(
*
CONST_DOUBLE_REAL_VALUE
(
x
)
,
*
p_high
)
;
*
p_low
=
0
;
return
;
case
VOIDmode
:
case
DImode
:
*
p_high
=
CONST_DOUBLE_HIGH
(
x
)
;
*
p_low
=
CONST_DOUBLE_LOW
(
x
)
;
return
;
default
:
break
;
}
}
fatal_insn
(
"const_double_split got a bad insn:"
,
x
)
;
}
</s>

Return the high and low words of a CONST_DOUBLE


<s> static void jli_call_scan ( void ) { rtx_insn * insn ; for ( insn = get_insns ( ) ; insn ; insn = NEXT_INSN ( insn ) ) { if ( ! CALL_P ( insn ) ) continue ; rtx pat = PATTERN ( insn ) ; if ( GET_CODE ( pat ) == COND_EXEC ) pat = COND_EXEC_CODE ( pat ) ; pat = XVECEXP ( pat , 0 , 0 ) ; if ( GET_CODE ( pat ) == SET ) pat = SET_SRC ( pat ) ; pat = XEXP ( XEXP ( pat , 0 ) , 0 ) ; if ( GET_CODE ( pat ) == SYMBOL_REF && arc_is_jli_call_p ( pat ) ) arc_add_jli_section ( pat ) ; } } </s>

Scan all calls and add symbols to be emitted in the jli section if needed .


<s> bool AArch64PassConfig :: addPostRegAlloc ( ) { if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableDeadRegisterElimination ) addPass ( createAArch64DeadRegisterDefinitions ( ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && TM -> getSubtarget < AArch64Subtarget > ( ) . isCortexA57 ( ) ) addPass ( createAArch64A57FPLoadBalancing ( ) ) ; return true ; } </s>

This method may be implemented by targets that want to run passes after register allocation pass pipeline but before prolog-epilog insertion .


<s> static bool expand_set_cint64_one_inst ( rtx dest_reg , HOST_WIDE_INT val , bool three_wide_only ) { if ( val == trunc_int_for_mode ( val , QImode ) ) { emit_move_insn ( dest_reg , GEN_INT ( val ) ) ; return true ; } else if ( ! three_wide_only ) { if ( ( val >= - 32768 && val <= 65535 ) || ( ( val == ( val & 0xFF ) * 0x0101010101010101LL ) ) || ( val == ( ( trunc_int_for_mode ( val , QImode ) & 0xFFFF ) * 0x0001000100010001LL ) ) ) { emit_move_insn ( dest_reg , GEN_INT ( val ) ) ; return true ; } } return false ; } </s>

Returns true iff VAL can be moved into a register in one instruction . And if it can , it emits the code to move the constant into DEST_REG . If THREE_WIDE_ONLY is true , this insists on an instruction that works in a bundle containing three instructions .


<s> void MipsSETargetLowering :: addMSAIntType ( MVT :: SimpleValueType Ty , const TargetRegisterClass * RC ) { addRegisterClass ( Ty , RC ) ; for ( unsigned Opc = 0 ; Opc < ISD :: BUILTIN_OP_END ; ++ Opc ) setOperationAction ( Opc , Ty , Expand ) ; setOperationAction ( ISD :: BITCAST , Ty , Legal ) ; setOperationAction ( ISD :: LOAD , Ty , Legal ) ; setOperationAction ( ISD :: STORE , Ty , Legal ) ; setOperationAction ( ISD :: EXTRACT_VECTOR_ELT , Ty , Custom ) ; setOperationAction ( ISD :: INSERT_VECTOR_ELT , Ty , Legal ) ; setOperationAction ( ISD :: BUILD_VECTOR , Ty , Custom ) ; setOperationAction ( ISD :: ADD , Ty , Legal ) ; setOperationAction ( ISD :: AND , Ty , Legal ) ; setOperationAction ( ISD :: CTLZ , Ty , Legal ) ; setOperationAction ( ISD :: CTPOP , Ty , Legal ) ; setOperationAction ( ISD :: MUL , Ty , Legal ) ; setOperationAction ( ISD :: OR , Ty , Legal ) ; setOperationAction ( ISD :: SDIV , Ty , Legal ) ; setOperationAction ( ISD :: SREM , Ty , Legal ) ; setOperationAction ( ISD :: SHL , Ty , Legal ) ; setOperationAction ( ISD :: SRA , Ty , Legal ) ; setOperationAction ( ISD :: SRL , Ty , Legal ) ; setOperationAction ( ISD :: SUB , Ty , Legal ) ; setOperationAction ( ISD :: UDIV , Ty , Legal ) ; setOperationAction ( ISD :: UREM , Ty , Legal ) ; setOperationAction ( ISD :: VECTOR_SHUFFLE , Ty , Custom ) ; setOperationAction ( ISD :: VSELECT , Ty , Legal ) ; setOperationAction ( ISD :: XOR , Ty , Legal ) ; if ( Ty == MVT :: v4i32 || Ty == MVT :: v2i64 ) { setOperationAction ( ISD :: FP_TO_SINT , Ty , Legal ) ; setOperationAction ( ISD :: FP_TO_UINT , Ty , Legal ) ; setOperationAction ( ISD :: SINT_TO_FP , Ty , Legal ) ; setOperationAction ( ISD :: UINT_TO_FP , Ty , Legal ) ; } setOperationAction ( ISD :: SETCC , Ty , Legal ) ; setCondCodeAction ( ISD :: SETNE , Ty , Expand ) ; setCondCodeAction ( ISD :: SETGE , Ty , Expand ) ; setCondCodeAction ( ISD :: SETGT , Ty , Expand ) ; setCondCodeAction ( ISD :: SETUGE , Ty , Expand ) ; setCondCodeAction ( ISD :: SETUGT , Ty , Expand ) ; } </s>

Enable MSA support for the given integer type and Register class .

Mips Mips MVT::SimpleValueType 0 ISD::BUILTIN_OP_END ISD::BITCAST ISD::LOAD ISD::STORE ISD::EXTRACT_VECTOR_ELT ISD::INSERT_VECTOR_ELT ISD::BUILD_VECTOR ISD::ADD ISD::AND ISD::CTLZ ISD::CTPOP ISD::MUL ISD::OR ISD::SDIV ISD::SREM ISD::SHL ISD::SRA ISD::SRL ISD::SUB ISD::UDIV ISD::UREM ISD::VECTOR_SHUFFLE ISD::VSELECT ISD::XOR MVT::v4i32 MVT::v2i64 ISD::FP_TO_SINT ISD::FP_TO_UINT ISD::SINT_TO_FP ISD::UINT_TO_FP ISD::SETCC ISD::SETNE ISD::SETGE ISD::SETGT ISD::SETUGE ISD::SETUGT


<s> bool X86TargetLowering :: CanLowerReturn ( CallingConv :: ID CallConv , bool isVarArg , const SmallVectorImpl < EVT > & OutTys , const SmallVectorImpl < ISD :: ArgFlagsTy > & ArgsFlags , SelectionDAG & DAG ) { SmallVector < CCValAssign , 16 > RVLocs ; CCState CCInfo ( CallConv , isVarArg , getTargetMachine ( ) , RVLocs , * DAG . getContext ( ) ) ; return CCInfo . CheckReturn ( OutTys , ArgsFlags , RetCC_X86 ) ; } </s>

This hook should be implemented to check whether the return values described by the Outs array can fit into the return registers .


<s> const uint32_t * MipsRegisterInfo :: getCallPreservedMask ( CallingConv :: ID ) const { if ( Subtarget . isSingleFloat ( ) ) return CSR_SingleFloatOnly_RegMask ; else if ( ! Subtarget . hasMips64 ( ) ) return CSR_O32_RegMask ; else if ( Subtarget . isABI_N32 ( ) ) return CSR_N32_RegMask ; assert ( Subtarget . isABI_N64 ( ) ) ; return CSR_N64_RegMask ; } </s>

Return a mask of call-preserved registers for the given calling convention on the current function .


<s> static void s390_restore_gprs_from_fprs ( void ) { int i ; if ( ! TARGET_Z10 || ! TARGET_HARD_FLOAT || ! crtl -> is_leaf ) return ; for ( i = 6 ; i < 16 ; i ++ ) { if ( FP_REGNO_P ( cfun_gpr_save_slot ( i ) ) ) { rtx_insn * insn = emit_move_insn ( gen_rtx_REG ( DImode , i ) , gen_rtx_REG ( DImode , cfun_gpr_save_slot ( i ) ) ) ; df_set_regs_ever_live ( i , true ) ; add_reg_note ( insn , REG_CFA_RESTORE , gen_rtx_REG ( DImode , i ) ) ; if ( i == STACK_POINTER_REGNUM ) add_reg_note ( insn , REG_CFA_DEF_CFA , plus_constant ( Pmode , stack_pointer_rtx , STACK_POINTER_OFFSET ) ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; } } } </s>


<s> StringRef getPassName ( ) const override { return PASS_NAME ; } </s>

getPassName - Return a nice clean name for a pass .


<s> static bool arm_promote_prototypes ( const_tree t ATTRIBUTE_UNUSED ) { return ! TARGET_AAPCS_BASED ; } </s>

We ca n't rely on the caller doing the proper promotion when using APCS or ATPCS .


<s> ISD :: NodeType getExtendForAtomicOps ( ) const override { return ISD :: SIGN_EXTEND ; } </s>

Returns how the platform 's atomic operations are extended ( ZERO_EXTEND , SIGN_EXTEND , or ANY_EXTEND ) .


<s> void Tile64InstrInfo :: storeRegToStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned SrcReg , bool isKill , int FI , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { DebugLoc DL ; if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; BuildMI ( MBB , I , DL , get ( T64 :: SW ) ) . addFrameIndex ( FI ) . addReg ( SrcReg , getKillRegState ( isKill ) ) ; } </s>

Store the specified register of the given register class to the specified stack frame index .


<s> void Z80oldAsmPrinter :: emitInlineAsmEnd ( const MCSubtargetInfo & StartInfo , const MCSubtargetInfo * EndInfo ) const { return ; if ( TM . getTargetTriple ( ) . getArch ( ) != Triple :: ez80old ) { return ; } bool Was16 = isCode16 ( StartInfo . getTargetTriple ( ) ) ; if ( ! EndInfo || Was16 != isCode16 ( EndInfo -> getTargetTriple ( ) ) ) { OutStreamer -> EmitAssemblerFlag ( Was16 ? MCAF_Code16 : MCAF_Code24 ) ; } } </s>

Let the target do anything it needs to do after emitting inlineasm .


<s> static unsigned getLinkageSize ( bool isPPC64 , bool isDarwinABI ) { if ( isDarwinABI || isPPC64 ) return 6 * ( isPPC64 ? 8 : 4 ) ; return 8 ; } </s>

getLinkageSize - Return the size of the PowerPC ABI linkage area .


<s> bool AArch64ExpandPseudo :: runOnMachineFunction ( MachineFunction & MF ) { TII = static_cast < const AArch64InstrInfo * > ( MF . getSubtarget ( ) . getInstrInfo ( ) ) ; bool Modified = false ; for ( auto & MBB : MF ) Modified |= expandMBB ( MBB ) ; return Modified ; } </s>

runOnMachineFunction - Emit the function body .


<s> void addExpr ( MCInst & Inst , const MCExpr * Expr ) const { if ( ! Expr ) Inst . addOperand ( MCOperand :: CreateImm ( 0 ) ) ; else if ( const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( Expr ) ) Inst . addOperand ( MCOperand :: CreateImm ( CE -> getValue ( ) ) ) ; else Inst . addOperand ( MCOperand :: CreateExpr ( Expr ) ) ; } </s>


<s> unsigned int pass_shorten_memrefs :: execute ( function * fn ) { basic_block bb ; FOR_ALL_BB_FN ( bb , fn ) { regno_map * m ; if ( optimize_bb_for_speed_p ( bb ) ) continue ; m = analyze ( bb ) ; transform ( m , bb ) ; } return 0 ; } </s>


<s> DecodeStatus ARMDisassembler :: getInstruction ( MCInst & MI , uint64_t & Size , ArrayRef < uint8_t > Bytes , uint64_t Address , raw_ostream & OS , raw_ostream & CS ) const { if ( STI . getFeatureBits ( ) [ ARM :: ModeThumb ] ) return getThumbInstruction ( MI , Size , Bytes , Address , OS , CS ) ; return getARMInstruction ( MI , Size , Bytes , Address , OS , CS ) ; } </s>

Returns the disassembly of a single instruction .


<s> unsigned AArch64InstrInfo :: getLoadStoreImmIdx ( unsigned Opc ) { switch ( Opc ) { default : return 2 ; case AArch64 :: LDPXi : case AArch64 :: LDPDi : case AArch64 :: STPXi : case AArch64 :: STPDi : case AArch64 :: LDNPXi : case AArch64 :: LDNPDi : case AArch64 :: STNPXi : case AArch64 :: STNPDi : case AArch64 :: LDPQi : case AArch64 :: STPQi : case AArch64 :: LDNPQi : case AArch64 :: STNPQi : case AArch64 :: LDPWi : case AArch64 :: LDPSi : case AArch64 :: STPWi : case AArch64 :: STPSi : case AArch64 :: LDNPWi : case AArch64 :: LDNPSi : case AArch64 :: STNPWi : case AArch64 :: STNPSi : case AArch64 :: LDG : case AArch64 :: STGPi : case AArch64 :: LD1B_IMM : case AArch64 :: LD1H_IMM : case AArch64 :: LD1W_IMM : case AArch64 :: LD1D_IMM : case AArch64 :: ST1B_IMM : case AArch64 :: ST1H_IMM : case AArch64 :: ST1W_IMM : case AArch64 :: ST1D_IMM : case AArch64 :: LD1B_H_IMM : case AArch64 :: LD1SB_H_IMM : case AArch64 :: LD1H_S_IMM : case AArch64 :: LD1SH_S_IMM : case AArch64 :: LD1W_D_IMM : case AArch64 :: LD1SW_D_IMM : case AArch64 :: ST1B_H_IMM : case AArch64 :: ST1H_S_IMM : case AArch64 :: ST1W_D_IMM : case AArch64 :: LD1B_S_IMM : case AArch64 :: LD1SB_S_IMM : case AArch64 :: LD1H_D_IMM : case AArch64 :: LD1SH_D_IMM : case AArch64 :: ST1B_S_IMM : case AArch64 :: ST1H_D_IMM : case AArch64 :: LD1B_D_IMM : case AArch64 :: LD1SB_D_IMM : case AArch64 :: ST1B_D_IMM : case AArch64 :: LD1RB_IMM : case AArch64 :: LD1RB_H_IMM : case AArch64 :: LD1RB_S_IMM : case AArch64 :: LD1RB_D_IMM : case AArch64 :: LD1RSB_H_IMM : case AArch64 :: LD1RSB_S_IMM : case AArch64 :: LD1RSB_D_IMM : case AArch64 :: LD1RH_IMM : case AArch64 :: LD1RH_S_IMM : case AArch64 :: LD1RH_D_IMM : case AArch64 :: LD1RSH_S_IMM : case AArch64 :: LD1RSH_D_IMM : case AArch64 :: LD1RW_IMM : case AArch64 :: LD1RW_D_IMM : case AArch64 :: LD1RSW_IMM : case AArch64 :: LD1RD_IMM : return 3 ; case AArch64 :: ADDG : case AArch64 :: STGOffset : case AArch64 :: LDR_PXI : case AArch64 :: STR_PXI : return 2 ; } } </s>

Returns the index for the immediate for a given instruction .


<s> static void mips_sim_next_cycle ( struct mips_sim * state ) { curr_state = state -> dfa_state ; state -> time ++ ; state -> insns_left = state -> issue_rate ; advance_state ( curr_state ) ; } </s>


<s> int AArch64FrameLowering :: getFrameIndexReference ( const MachineFunction & MF , int FI , unsigned & FrameReg ) const { return resolveFrameIndexReference ( MF , FI , FrameReg ) ; } </s>

getFrameIndexReference - This method should return the base register and offset used to reference a frame index location .


<s> BitVector LanaiRegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; Reserved . set ( Lanai :: R0 ) ; Reserved . set ( Lanai :: R1 ) ; Reserved . set ( Lanai :: PC ) ; Reserved . set ( Lanai :: R2 ) ; Reserved . set ( Lanai :: SP ) ; Reserved . set ( Lanai :: R4 ) ; Reserved . set ( Lanai :: FP ) ; Reserved . set ( Lanai :: R5 ) ; Reserved . set ( Lanai :: RR1 ) ; Reserved . set ( Lanai :: R10 ) ; Reserved . set ( Lanai :: RR2 ) ; Reserved . set ( Lanai :: R11 ) ; Reserved . set ( Lanai :: RCA ) ; Reserved . set ( Lanai :: R15 ) ; if ( hasBasePointer ( MF ) ) Reserved . set ( getBaseRegister ( ) ) ; return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s>
bool
X86TargetLowering
::
isNoopAddrSpaceCast
(
unsigned
SrcAS
,
unsigned
DestAS
)
const
{
assert
(
SrcAS
!=
DestAS
&&
"Expected different address spaces!"
)
;
return
SrcAS
<
256
&&
DestAS
<
256
;
}
</s>

Returns true if a cast between SrcAS and DestAS is a noop .