<s>
void
AVRInstrInfo
::
copyPhysReg
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
MI
,
const
DebugLoc
&
DL
,
unsigned
DestReg
,
unsigned
SrcReg
,
bool
KillSrc
)
const
{
const
AVRSubtarget
&
STI
=
MBB
.
getParent
(
)
->
getSubtarget
<
AVRSubtarget
>
(
)
;
const
AVRRegisterInfo
&
TRI
=
*
STI
.
getRegisterInfo
(
)
;
unsigned
Opc
;
if
(
AVR
::
DREGSRegClass
.
contains
(
DestReg
,
SrcReg
)
)
{
if
(
STI
.
hasMOVW
(
)
)
{
BuildMI
(
MBB
,
MI
,
DL
,
get
(
AVR
::
MOVWRdRr
)
,
DestReg
)
.
addReg
(
SrcReg
,
getKillRegState
(
KillSrc
)
)
;
}
else
{
unsigned
DestLo
,
DestHi
,
SrcLo
,
SrcHi
;
TRI
.
splitReg
(
DestReg
,
DestLo
,
DestHi
)
;
TRI
.
splitReg
(
SrcReg
,
SrcLo
,
SrcHi
)
;
BuildMI
(
MBB
,
MI
,
DL
,
get
(
AVR
::
MOVRdRr
)
,
DestLo
)
.
addReg
(
SrcLo
,
getKillRegState
(
KillSrc
)
)
;
BuildMI
(
MBB
,
MI
,
DL
,
get
(
AVR
::
MOVRdRr
)
,
DestHi
)
.
addReg
(
SrcHi
,
getKillRegState
(
KillSrc
)
)
;
}
}
else
{
if
(
AVR
::
GPR8RegClass
.
contains
(
DestReg
,
SrcReg
)
)
{
Opc
=
AVR
::
MOVRdRr
;
}
else
if
(
SrcReg
==
AVR
::
SP
&&
AVR
::
DREGSRegClass
.
contains
(
DestReg
)
)
{
Opc
=
AVR
::
SPREAD
;
}
else
if
(
DestReg
==
AVR
::
SP
&&
AVR
::
DREGSRegClass
.
contains
(
SrcReg
)
)
{
Opc
=
AVR
::
SPWRITE
;
}
else
{
llvm_unreachable
(
"Impossible reg-to-reg copy"
)
;
}
BuildMI
(
MBB
,
MI
,
DL
,
get
(
Opc
)
,
DestReg
)
.
addReg
(
SrcReg
,
getKillRegState
(
KillSrc
)
)
;
}
}
</s>

AVR
AVR
AVR
AVR
AVR
AVR::DREGSRegClass
AVR::MOVWRdRr
AVR::MOVRdRr
AVR::MOVRdRr
AVR::GPR8RegClass
AVR::MOVRdRr
AVR::SP
AVR::DREGSRegClass
AVR::SPREAD
AVR::SP
AVR::DREGSRegClass
AVR::SPWRITE
"Impossible reg-to-reg copy"


<s> void MSP430AsmPrinter :: EmitInstruction ( const MachineInstr * MI ) { MSP430MCInstLower MCInstLowering ( OutContext , * this ) ; MCInst TmpInst ; MCInstLowering . Lower ( MI , TmpInst ) ; EmitToStreamer ( OutStreamer , TmpInst ) ; } </s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s> static bool mips_insn_has_inflexible_gp_ref_p ( rtx_insn * insn ) { return find_reg_fusage ( insn , USE , pic_offset_table_rtx ) ; } </s>

Return true if INSN refers to the global pointer in an `` inflexible '' way . See mips_cfun_has_inflexible_gp_ref_p for details .


<s> bool HexagonOptimizeSZExtends :: runOnMachineFunction ( MachineFunction & MF ) { DenseMap < unsigned , unsigned > SExtMap ; for ( MachineFunction :: iterator MBBb = MF . begin ( ) , MBBe = MF . end ( ) ; MBBb != MBBe ; ++ MBBb ) { MachineBasicBlock * MBB = MBBb ; SExtMap . clear ( ) ; for ( MachineBasicBlock :: iterator MII = MBB -> begin ( ) ; MII != MBB -> end ( ) ; ++ MII ) { MachineInstr * MI = MII ; if ( MI -> getOpcode ( ) == Hexagon :: SXTW ) { assert ( MI -> getNumOperands ( ) == 2 ) ; MachineOperand & Dst = MI -> getOperand ( 0 ) ; MachineOperand & Src = MI -> getOperand ( 1 ) ; unsigned DstReg = Dst . getReg ( ) ; unsigned SrcReg = Src . getReg ( ) ; if ( TargetRegisterInfo :: isVirtualRegister ( DstReg ) && TargetRegisterInfo :: isVirtualRegister ( SrcReg ) ) { SExtMap [ DstReg ] = SrcReg ; } } if ( MI -> isCopy ( ) ) { assert ( MI -> getNumOperands ( ) == 2 ) ; MachineOperand & Dst = MI -> getOperand ( 0 ) ; MachineOperand & Src = MI -> getOperand ( 1 ) ; if ( Src . getSubReg ( ) != Hexagon :: subreg_loreg ) continue ; unsigned DstReg = Dst . getReg ( ) ; unsigned SrcReg = Src . getReg ( ) ; if ( TargetRegisterInfo :: isVirtualRegister ( DstReg ) && TargetRegisterInfo :: isVirtualRegister ( SrcReg ) ) { if ( unsigned SextSrc = SExtMap . lookup ( SrcReg ) ) { MI -> RemoveOperand ( 1 ) ; MI -> addOperand ( MachineOperand :: CreateReg ( SextSrc , false ) ) ; } } } } } return true ; } </s>

runOnMachineFunction - Emit the function body .


"Interrupt handlers take exactly one integer or unsigned argument"

This hook must be implemented to lower the incoming ( formal ) arguments , described by the Ins array , into the specified DAG .


<s> bool X86TTIImpl :: isLegalMaskedGather ( Type * DataTy , Align Alignment ) { if ( ! supportsGather ( ) ) return false ; if ( auto * DataVTy = dyn_cast < FixedVectorType > ( DataTy ) ) { unsigned NumElts = DataVTy -> getNumElements ( ) ; if ( NumElts == 1 ) return false ; if ( ST -> hasAVX512 ( ) && ( NumElts == 2 || ( NumElts == 4 && ! ST -> hasVLX ( ) ) ) ) return false ; } Type * ScalarTy = DataTy -> getScalarType ( ) ; if ( ScalarTy -> isPointerTy ( ) ) return true ; if ( ScalarTy -> isFloatTy ( ) || ScalarTy -> isDoubleTy ( ) ) return true ; if ( ! ScalarTy -> isIntegerTy ( ) ) return false ; unsigned IntWidth = ScalarTy -> getIntegerBitWidth ( ) ; return IntWidth == 32 || IntWidth == 64 ; } </s>

Return true if the target supports masked gather .


"invalid feature modifier %qs in %<-mcpu=%s%>"

Validate a command-line -mcpu option . Parse the cpu and extensions ( if any ) specified in STR and throw errors if appropriate . Put the results if they are valid in RES and ISA_FLAGS . Return whether the option is valid .


<s> bool hasReservedCallFrame ( const MachineFunction & MF ) const override { return true ; } </s>

hasReservedCallFrame - Under normal circumstances , when a frame pointer is not required , we reserve argument space for call sites in the function immediately on entry to the current function .


<s>
void
LanaiInstrInfo
::
copyPhysReg
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
Position
,
const
DebugLoc
&
DL
,
MCRegister
DestinationRegister
,
MCRegister
SourceRegister
,
bool
KillSource
)
const
{
if
(
!
Lanai
::
GPRRegClass
.
contains
(
DestinationRegister
,
SourceRegister
)
)
{
llvm_unreachable
(
"Impossible reg-to-reg copy"
)
;
}
BuildMI
(
MBB
,
Position
,
DL
,
get
(
Lanai
::
OR_I_LO
)
,
DestinationRegister
)
.
addReg
(
SourceRegister
,
getKillRegState
(
KillSource
)
)
.
addImm
(
0
)
;
}
</s>

Lanai
Lanai
Lanai::GPRRegClass
"Impossible reg-to-reg copy"
Lanai::OR_I_LO
0


<s> static bool m68k_jump_table_ref_p ( rtx x ) { if ( GET_CODE ( x ) != LABEL_REF ) return false ; rtx_insn * insn = as_a < rtx_insn * > ( XEXP ( x , 0 ) ) ; if ( ! NEXT_INSN ( insn ) && ! PREV_INSN ( insn ) ) return true ; insn = next_nonnote_insn ( insn ) ; return insn && JUMP_TABLE_DATA_P ( insn ) ; } </s>

Return true if X is a LABEL_REF for a jump table . Assume that unplaced labels will become jump tables .


<s> const char * RISCVTargetLowering :: getTargetNodeName ( unsigned Opcode ) const { case RISCVISD :: NODE : \ return "RISCVISD::" # NODE ; switch ( ( RISCVISD :: NodeType ) Opcode ) { case RISCVISD :: FIRST_NUMBER : break ; NODE_NAME_CASE ( RET_FLAG ) NODE_NAME_CASE ( URET_FLAG ) NODE_NAME_CASE ( SRET_FLAG ) NODE_NAME_CASE ( MRET_FLAG ) NODE_NAME_CASE ( CALL ) NODE_NAME_CASE ( SELECT_CC ) NODE_NAME_CASE ( BuildPairF64 ) NODE_NAME_CASE ( SplitF64 ) NODE_NAME_CASE ( TAIL ) NODE_NAME_CASE ( SLLW ) NODE_NAME_CASE ( SRAW ) NODE_NAME_CASE ( SRLW ) NODE_NAME_CASE ( DIVW ) NODE_NAME_CASE ( DIVUW ) NODE_NAME_CASE ( REMUW ) NODE_NAME_CASE ( ROLW ) NODE_NAME_CASE ( RORW ) NODE_NAME_CASE ( FSLW ) NODE_NAME_CASE ( FSRW ) NODE_NAME_CASE ( FMV_H_X ) NODE_NAME_CASE ( FMV_X_ANYEXTH ) NODE_NAME_CASE ( FMV_W_X_RV64 ) NODE_NAME_CASE ( FMV_X_ANYEXTW_RV64 ) NODE_NAME_CASE ( READ_CYCLE_WIDE ) NODE_NAME_CASE ( GREVI ) NODE_NAME_CASE ( GREVIW ) NODE_NAME_CASE ( GORCI ) NODE_NAME_CASE ( GORCIW ) } return nullptr ; } </s>

getTargetNodeName - This method returns the name of a target specific

RISCV RISCV RISCVISD::NODE "RISCVISD::" RISCVISD::NodeType RISCVISD::FIRST_NUMBER


<s> bool ix86_modes_tieable_p ( enum machine_mode mode1 , enum machine_mode mode2 ) { if ( mode1 == mode2 ) return true ; if ( ix86_tieable_integer_mode_p ( mode1 ) && ix86_tieable_integer_mode_p ( mode2 ) ) return true ; if ( mode2 == XFmode ) return mode1 == SFmode || mode1 == DFmode ; if ( mode2 == DFmode ) return mode1 == SFmode ; if ( GET_MODE_SIZE ( mode2 ) >= 8 && ix86_hard_regno_mode_ok ( FIRST_SSE_REG , mode2 ) ) return ix86_hard_regno_mode_ok ( FIRST_SSE_REG , mode1 ) ; if ( GET_MODE_SIZE ( mode2 ) == 8 && ix86_hard_regno_mode_ok ( FIRST_MMX_REG , mode2 ) ) return ix86_hard_regno_mode_ok ( FIRST_MMX_REG , mode1 ) ; return false ; } </s>

Return true if MODE1 is accessible in a register that can hold MODE2 without copying . That is , all register classes that can hold MODE2 can also hold MODE1 .


<s> std :: pair < const TargetRegisterClass * , uint8_t > X86TargetLowering :: findRepresentativeClass ( EVT VT ) const { const TargetRegisterClass * RRC = 0 ; uint8_t Cost = 1 ; switch ( VT . getSimpleVT ( ) . SimpleTy ) { default : return TargetLowering :: findRepresentativeClass ( VT ) ; case MVT :: i8 : case MVT :: i16 : case MVT :: i32 : case MVT :: i64 : RRC = ( Subtarget -> is64Bit ( ) ? X86 :: GR64RegisterClass : X86 :: GR32RegisterClass ) ; break ; case MVT :: x86mmx : RRC = X86 :: VR64RegisterClass ; break ; case MVT :: f32 : case MVT :: f64 : case MVT :: v16i8 : case MVT :: v8i16 : case MVT :: v4i32 : case MVT :: v2i64 : case MVT :: v4f32 : case MVT :: v2f64 : case MVT :: v32i8 : case MVT :: v8i32 : case MVT :: v4i64 : case MVT :: v8f32 : case MVT :: v4f64 : RRC = X86 :: VR128RegisterClass ; break ; } return std :: make_pair ( RRC , Cost ) ; } </s>

Return the largest legal super-reg register class of the register class for the specified type and its associated `` cost '' .


<s>
SDValue
X86TargetLowering
::
LowerCallResult
(
SDValue
Chain
,
SDValue
InFlag
,
CallingConv
::
ID
CallConv
,
bool
isVarArg
,
const
SmallVectorImpl
<
ISD
::
InputArg
>
&
Ins
,
DebugLoc
dl
,
SelectionDAG
&
DAG
,
SmallVectorImpl
<
SDValue
>
&
InVals
)
{
SmallVector
<
CCValAssign
,
16
>
RVLocs
;
bool
Is64Bit
=
Subtarget
->
is64Bit
(
)
;
CCState
CCInfo
(
CallConv
,
isVarArg
,
getTargetMachine
(
)
,
RVLocs
,
*
DAG
.
getContext
(
)
)
;
CCInfo
.
AnalyzeCallResult
(
Ins
,
RetCC_X86
)
;
for
(
unsigned
i
=
0
;
i
!=
RVLocs
.
size
(
)
;
++
i
)
{
CCValAssign
&
VA
=
RVLocs
[
i
]
;
EVT
CopyVT
=
VA
.
getValVT
(
)
;
if
(
(
CopyVT
==
MVT
::
f32
||
CopyVT
==
MVT
::
f64
)
&&
(
(
Is64Bit
||
Ins
[
i
]
.
Flags
.
isInReg
(
)
)
&&
!
Subtarget
->
hasSSE1
(
)
)
)
{
llvm_report_error
(
"SSE register return with SSE disabled"
)
;
}
if
(
(
VA
.
getLocReg
(
)
==
X86
::
ST0
||
VA
.
getLocReg
(
)
==
X86
::
ST1
)
&&
isScalarFPTypeInSSEReg
(
VA
.
getValVT
(
)
)
)
{
CopyVT
=
MVT
::
f80
;
}
SDValue
Val
;
if
(
Is64Bit
&&
CopyVT
.
isVector
(
)
&&
CopyVT
.
getSizeInBits
(
)
==
64
)
{
if
(
VA
.
getLocReg
(
)
==
X86
::
XMM0
||
VA
.
getLocReg
(
)
==
X86
::
XMM1
)
{
Chain
=
DAG
.
getCopyFromReg
(
Chain
,
dl
,
VA
.
getLocReg
(
)
,
MVT
::
v2i64
,
InFlag
)
.
getValue
(
1
)
;
Val
=
Chain
.
getValue
(
0
)
;
Val
=
DAG
.
getNode
(
ISD
::
EXTRACT_VECTOR_ELT
,
dl
,
MVT
::
i64
,
Val
,
DAG
.
getConstant
(
0
,
MVT
::
i64
)
)
;
}
else
{
Chain
=
DAG
.
getCopyFromReg
(
Chain
,
dl
,
VA
.
getLocReg
(
)
,
MVT
::
i64
,
InFlag
)
.
getValue
(
1
)
;
Val
=
Chain
.
getValue
(
0
)
;
}
Val
=
DAG
.
getNode
(
ISD
::
BIT_CONVERT
,
dl
,
CopyVT
,
Val
)
;
}
else
{
Chain
=
DAG
.
getCopyFromReg
(
Chain
,
dl
,
VA
.
getLocReg
(
)
,
CopyVT
,
InFlag
)
.
getValue
(
1
)
;
Val
=
Chain
.
getValue
(
0
)
;
}
InFlag
=
Chain
.
getValue
(
2
)
;
if
(
CopyVT
!=
VA
.
getValVT
(
)
)
{
Val
=
DAG
.
getNode
(
ISD
::
FP_ROUND
,
dl
,
VA
.
getValVT
(
)
,
Val
,
DAG
.
getIntPtrConstant
(
1
)
)
;
}
InVals
.
push_back
(
Val
)
;
}
return
Chain
;
}
</s>

LowerCallResult - Lower the result values of an ISD : :CALL into the appropriate copies out of appropriate physical registers .


<s>
const
char
*
rs6000_insn_for_shift_mask
(
machine_mode
mode
,
rtx
*
operands
,
bool
dot
)
{
int
nb
,
ne
;
if
(
!
rs6000_is_valid_mask
(
operands
[
3
]
,
&
nb
,
&
ne
,
mode
)
)
gcc_unreachable
(
)
;
if
(
mode
==
DImode
&&
ne
==
0
)
{
if
(
GET_CODE
(
operands
[
4
]
)
==
LSHIFTRT
&&
INTVAL
(
operands
[
2
]
)
)
operands
[
2
]
=
GEN_INT
(
64
INTVAL
(
operands
[
2
]
)
)
;
operands
[
3
]
=
GEN_INT
(
63
nb
)
;
if
(
dot
)
return
"rld%I2cl. %0,%1,%2,%3"
;
return
"rld%I2cl %0,%1,%2,%3"
;
}
if
(
mode
==
DImode
&&
nb
==
63
)
{
operands
[
3
]
=
GEN_INT
(
63
ne
)
;
if
(
dot
)
return
"rld%I2cr. %0,%1,%2,%3"
;
return
"rld%I2cr %0,%1,%2,%3"
;
}
if
(
mode
==
DImode
&&
GET_CODE
(
operands
[
4
]
)
!=
LSHIFTRT
&&
CONST_INT_P
(
operands
[
2
]
)
&&
ne
==
INTVAL
(
operands
[
2
]
)
)
{
operands
[
3
]
=
GEN_INT
(
63
nb
)
;
if
(
dot
)
return
"rld%I2c. %0,%1,%2,%3"
;
return
"rld%I2c %0,%1,%2,%3"
;
}
if
(
nb
<
32
&&
ne
<
32
)
{
if
(
GET_CODE
(
operands
[
4
]
)
==
LSHIFTRT
&&
INTVAL
(
operands
[
2
]
)
)
operands
[
2
]
=
GEN_INT
(
32
INTVAL
(
operands
[
2
]
)
)
;
operands
[
3
]
=
GEN_INT
(
31
nb
)
;
operands
[
4
]
=
GEN_INT
(
31
ne
)
;
if
(
dot
)
return
"rlw%I2nm. %0,%1,%h2,%3,%4"
;
return
"rlw%I2nm %0,%1,%h2,%3,%4"
;
}
gcc_unreachable
(
)
;
}
</s>

Return the instruction template for a shift with mask in mode MODE , with operands OPERANDS . If DOT is true , make it a record-form instruction .


<s> SDNode * VEDAGToDAGISel :: getGlobalBaseReg ( ) { Register GlobalBaseReg = Subtarget -> getInstrInfo ( ) -> getGlobalBaseReg ( MF ) ; return CurDAG -> getRegister ( GlobalBaseReg , TLI -> getPointerTy ( CurDAG -> getDataLayout ( ) ) ) . getNode ( ) ; } </s>

getGlobalBaseReg - Return a virtual register initialized with the the global base register value .


<s> bool m68k_regno_mode_ok ( int regno , enum machine_mode mode ) { if ( regno < 8 ) { if ( regno + GET_MODE_SIZE ( mode ) / 4 <= 8 ) return true ; } else if ( regno < 16 ) { if ( GET_MODE_SIZE ( mode ) == 1 ) return false ; if ( regno + GET_MODE_SIZE ( mode ) / 4 <= 16 ) return true ; } else if ( regno < 24 ) { if ( ( GET_MODE_CLASS ( mode ) == MODE_FLOAT || GET_MODE_CLASS ( mode ) == MODE_COMPLEX_FLOAT ) && GET_MODE_UNIT_SIZE ( mode ) <= 12 ) return true ; } return false ; } </s>

Value is true if hard register REGNO can hold a value of machine-mode MODE . On the 68000 , we let the cpu registers can hold any mode , but restrict the 68881 registers to floating-point modes .


<s> static bool contains ( const T & container , const U & contained ) { return container . count ( contained ) ; } </s>

contains - Returns true if this trace contains the given basic block .


Insert code to lockfully update * PTR with * PTR OP VAR just before GSI . This is necessary for types larger than 64 bits , where there is no cmp & swap instruction to implement a lockless scheme . We use a lock variable in global memory . while ( cmp & swap ( & lock_var , 0 , 1 ) ) continue ; T accum = * ptr ; accum = accum OP var ; * ptr = accum ; cmp & swap ( & lock_var , 1 , 0 ) ; return accum ; A lock in global memory is necessary to force execution engine descheduling and avoid resource starvation that can occur if the lock is in .shared memory .


<s> const AMDGPUSubtarget * getSubtargetImpl ( const Function & ) const override { return & Subtarget ; } </s>

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .


<s> static void frv_trampoline_init ( rtx m_tramp , tree fndecl , rtx static_chain ) { rtx addr = XEXP ( m_tramp , 0 ) ; rtx fnaddr = XEXP ( DECL_RTL ( fndecl ) , 0 ) ; rtx sc_reg = force_reg ( Pmode , static_chain ) ; emit_library_call ( gen_rtx_SYMBOL_REF ( SImode , "__trampoline_setup" ) , LCT_NORMAL , VOIDmode , 4 , addr , Pmode , GEN_INT ( frv_trampoline_size ( ) ) , SImode , fnaddr , Pmode , sc_reg , Pmode ) ; } </s>

A C statement to initialize the variable parts of a trampoline . ADDR is an RTX for the address of the trampoline ; FNADDR is an RTX for the address of the nested function ; STATIC_CHAIN is an RTX for the static chain value that should be passed to the function when it is called . The template is : setlo # 0 , < jmp_reg > setlo # 0 , < static_chain > sethi # 0 , < jmp_reg > sethi # 0 , < static_chain > jmpl @ ( gr0 , < jmp_reg > )


<s> const MipsRegisterInfo & Mips16InstrInfo :: getRegisterInfo ( ) const { return RI ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s> unsigned AlphaInstrInfo :: getGlobalBaseReg ( MachineFunction * MF ) const { AlphaMachineFunctionInfo * AlphaFI = MF -> getInfo < AlphaMachineFunctionInfo > ( ) ; unsigned GlobalBaseReg = AlphaFI -> getGlobalBaseReg ( ) ; if ( GlobalBaseReg != 0 ) return GlobalBaseReg ; MachineBasicBlock & FirstMBB = MF -> front ( ) ; MachineBasicBlock :: iterator MBBI = FirstMBB . begin ( ) ; MachineRegisterInfo & RegInfo = MF -> getRegInfo ( ) ; const TargetInstrInfo * TII = MF -> getTarget ( ) . getInstrInfo ( ) ; GlobalBaseReg = RegInfo . createVirtualRegister ( & Alpha :: GPRCRegClass ) ; BuildMI ( FirstMBB , MBBI , DebugLoc ( ) , TII -> get ( TargetOpcode :: COPY ) , GlobalBaseReg ) . addReg ( Alpha :: R29 ) ; RegInfo . addLiveIn ( Alpha :: R29 ) ; AlphaFI -> setGlobalBaseReg ( GlobalBaseReg ) ; return GlobalBaseReg ; } </s>

Alpha Alpha Alpha Alpha Alpha Alpha 0 Alpha::GPRCRegClass Alpha::R29 Alpha::R29 Alpha


"%<msp430_set_driver_var%> expects 2 arguments"

"unhandled arguments %qs and %qs to %<msp430_set_driver_var%>"

Spec function to set a global variable to a specific value in the driver . The first argument is the variable name , and the second is the value to set it to . Currently only `` msp430_warn_devices_csv '' and `` msp430_devices_csv_loc '' are supported . The intention is that we can take a `` Target '' option and set the variable associated with it in the driver as well . Whilst the driver sees `` Target '' options , it does not set the variables associated with that option .


<s> void handleAssemblerFlag ( MCAssemblerFlag Flag ) override { switch ( Flag ) { default : break ; case MCAF_Code16 : setIsThumb ( true ) ; break ; case MCAF_Code32 : setIsThumb ( false ) ; break ; } } </s>

Handle any target-specific assembler flags . By default , do nothing .


<s> rtx frv_matching_accg_for_acc ( rtx acc ) { return gen_rtx_REG ( frv_matching_accg_mode ( GET_MODE ( acc ) ) , REGNO ( acc ) - ACC_FIRST + ACCG_FIRST ) ; } </s>

Return the accumulator guard that should be paired with accumulator register ACC . The mode of the returned register is in the same class as ACC , but is four times smaller .


<s> virtual const KudeyarSubtarget * getSubtargetImpl ( ) const { return & Subtarget ; } </s>


<s>
void
XCoreFrameLowering
::
processFunctionBeforeFrameFinalized
(
MachineFunction
&
MF
,
RegScavenger
*
RS
)
const
{
assert
(
RS
&&
"requiresRegisterScavenging failed"
)
;
MachineFrameInfo
&
MFI
=
MF
.
getFrameInfo
(
)
;
const
TargetRegisterClass
*
RC
=
&
XCore
::
GRRegsRegClass
;
XCoreFunctionInfo
*
XFI
=
MF
.
getInfo
<
XCoreFunctionInfo
>
(
)
;
if
(
XFI
->
isLargeFrame
(
MF
)
||
hasFP
(
MF
)
)
RS
->
addScavengingFrameIndex
(
MFI
.
CreateStackObject
(
RC
->
getSize
(
)
,
RC
->
getAlignment
(
)
,
false
)
)
;
if
(
XFI
->
isLargeFrame
(
MF
)
&&
!
hasFP
(
MF
)
)
RS
->
addScavengingFrameIndex
(
MFI
.
CreateStackObject
(
RC
->
getSize
(
)
,
RC
->
getAlignment
(
)
,
false
)
)
;
}
</s>

processFunctionBeforeFrameFinalized - This method is called immediately before the specified function 's frame layout ( MF.getFrameInfo ( ) ) is finalized .

XCore
XCore
"requiresRegisterScavenging failed"
XCore::GRRegsRegClass
XCore
XCore


<s> bool WebAssemblyTargetLowering :: isCheapToSpeculateCtlz ( ) const { return true ; } </s>

Return true if it is cheap to speculate a call to intrinsic ctlz .


<s> static bool nios2_valid_compare_const_p ( enum rtx_code code , rtx op ) { gcc_assert ( CONST_INT_P ( op ) ) ; switch ( code ) { case EQ : case NE : case GE : case LT : return SMALL_INT ( INTVAL ( op ) ) ; case GEU : case LTU : return SMALL_INT_UNSIGNED ( INTVAL ( op ) ) ; default : return false ; } } </s>

Return true if the constant comparison is supported by nios2 .


"Nyuzi DAG->DAG Pattern Instruction Selection"

getPassName - Return a nice clean name for a pass .


<s> Value * RISCVTargetLowering :: emitMaskedAtomicCmpXchgIntrinsic ( IRBuilder < > & Builder , AtomicCmpXchgInst * CI , Value * AlignedAddr , Value * CmpVal , Value * NewVal , Value * Mask , AtomicOrdering Ord ) const { unsigned XLen = Subtarget . getXLen ( ) ; Value * Ordering = Builder . getIntN ( XLen , static_cast < uint64_t > ( Ord ) ) ; Intrinsic :: ID CmpXchgIntrID = Intrinsic :: riscv_masked_cmpxchg_i32 ; if ( XLen == 64 ) { CmpVal = Builder . CreateSExt ( CmpVal , Builder . getInt64Ty ( ) ) ; NewVal = Builder . CreateSExt ( NewVal , Builder . getInt64Ty ( ) ) ; Mask = Builder . CreateSExt ( Mask , Builder . getInt64Ty ( ) ) ; CmpXchgIntrID = Intrinsic :: riscv_masked_cmpxchg_i64 ; } Type * Tys [ ] = { AlignedAddr -> getType ( ) } ; Function * MaskedCmpXchg = Intrinsic :: getDeclaration ( CI -> getModule ( ) , CmpXchgIntrID , Tys ) ; Value * Result = Builder . CreateCall ( MaskedCmpXchg , { AlignedAddr , CmpVal , NewVal , Mask , Ordering } ) ; if ( XLen == 64 ) Result = Builder . CreateTrunc ( Result , Builder . getInt32Ty ( ) ) ; return Result ; } </s>

Perform a masked cmpxchg using a target-specific intrinsic .


"Encoding of this operand type is not supported yet."

getMachineOpValue - Return binary encoding of operand .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const { AU . addRequired < MachineBranchProbabilityInfo > ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> static bool h8300_function_value_regno_p ( const unsigned int regno ) { return ( regno == R0_REG ) ; } </s>

Worker function for TARGET_FUNCTION_VALUE_REGNO_P . On the H8 , R0 is the only register thus used .


"parameter passing for argument of type "

Worker function for TARGET_SETUP_INCOMING_VARARGS . On the ARM , PRETEND_SIZE is set in order to have the prologue push the last named arg and all anonymous args onto the stack . XXX I know the prologue should n't be pushing registers , but it is faster that way .


<s> bool X86FastISel :: fastSelectInstruction ( const Instruction * I ) { switch ( I -> getOpcode ( ) ) { default : break ; case Instruction :: Load : return X86SelectLoad ( I ) ; case Instruction :: Store : return X86SelectStore ( I ) ; case Instruction :: Ret : return X86SelectRet ( I ) ; case Instruction :: ICmp : case Instruction :: FCmp : return X86SelectCmp ( I ) ; case Instruction :: ZExt : return X86SelectZExt ( I ) ; case Instruction :: Br : return X86SelectBranch ( I ) ; case Instruction :: LShr : case Instruction :: AShr : case Instruction :: Shl : return X86SelectShift ( I ) ; case Instruction :: SDiv : case Instruction :: UDiv : case Instruction :: SRem : case Instruction :: URem : return X86SelectDivRem ( I ) ; case Instruction :: Select : return X86SelectSelect ( I ) ; case Instruction :: Trunc : return X86SelectTrunc ( I ) ; case Instruction :: FPExt : return X86SelectFPExt ( I ) ; case Instruction :: FPTrunc : return X86SelectFPTrunc ( I ) ; case Instruction :: SIToFP : return X86SelectSIToFP ( I ) ; case Instruction :: IntToPtr : case Instruction :: PtrToInt : { EVT SrcVT = TLI . getValueType ( DL , I -> getOperand ( 0 ) -> getType ( ) ) ; EVT DstVT = TLI . getValueType ( DL , I -> getType ( ) ) ; if ( DstVT . bitsGT ( SrcVT ) ) return X86SelectZExt ( I ) ; if ( DstVT . bitsLT ( SrcVT ) ) return X86SelectTrunc ( I ) ; unsigned Reg = getRegForValue ( I -> getOperand ( 0 ) ) ; if ( Reg == 0 ) return false ; updateValueMap ( I , Reg ) ; return true ; } case Instruction :: BitCast : { if ( ! Subtarget -> hasSSE2 ( ) ) return false ; EVT SrcVT = TLI . getValueType ( DL , I -> getOperand ( 0 ) -> getType ( ) ) ; EVT DstVT = TLI . getValueType ( DL , I -> getType ( ) ) ; if ( ! SrcVT . isSimple ( ) || ! DstVT . isSimple ( ) ) return false ; MVT SVT = SrcVT . getSimpleVT ( ) ; MVT DVT = DstVT . getSimpleVT ( ) ; if ( ! SVT . is128BitVector ( ) && ! ( Subtarget -> hasAVX ( ) && SVT . is256BitVector ( ) ) && ! ( Subtarget -> hasAVX512 ( ) && SVT . is512BitVector ( ) && ( Subtarget -> hasBWI ( ) || ( SVT . getScalarSizeInBits ( ) >= 32 && DVT . getScalarSizeInBits ( ) >= 32 ) ) ) ) return false ; unsigned Reg = getRegForValue ( I -> getOperand ( 0 ) ) ; if ( Reg == 0 ) return false ; updateValueMap ( I , Reg ) ; return true ; } } return false ; } </s>

This method is called by target-independent code when the normal FastISel process fails to select an instruction .


<s> rtl_opt_pass * make_pass_track_speculation ( gcc :: context * ctxt ) { return new pass_track_speculation ( ctxt ) ; } </s>


<s> const char * mips_output_order_conditional_branch ( rtx_insn * insn , rtx * operands , bool inverted_p ) { const char * branch [ 2 ] ; switch ( GET_CODE ( operands [ 1 ] ) ) { case LEU : inverted_p = ! inverted_p ; case GTU : branch [ ! inverted_p ] = MIPS_BRANCH ( "bne" , "%2,%.,%0" ) ; branch [ inverted_p ] = MIPS_BRANCH ( "beq" , "%2,%.,%0" ) ; break ; case LTU : inverted_p = ! inverted_p ; case GEU : branch [ ! inverted_p ] = MIPS_BRANCH ( "beq" , "%.,%.,%0" ) ; branch [ inverted_p ] = MIPS_BRANCH ( "bne" , "%.,%.,%0" ) ; break ; default : branch [ ! inverted_p ] = MIPS_BRANCH ( "b%C1z" , "%2,%0" ) ; branch [ inverted_p ] = MIPS_BRANCH ( "b%N1z" , "%2,%0" ) ; break ; } return mips_output_conditional_branch ( insn , operands , branch [ 1 ] , branch [ 0 ] ) ; } </s>

Return the assembly code for INSN , which branches to OPERANDS [ 0 ] if some ordering condition is true . The condition is given by OPERANDS [ 1 ] if ! INVERTED_P , otherwise it is the inverse of OPERANDS [ 1 ] . OPERANDS [ 2 ] is the comparison 's first operand ; its second is always zero .


<s>
void
dump
(
)
{
LLVM_DEBUG
(
dbgs
(
)
<<
"Reduction:\n"
;
for
(
auto
*
Add
:
Adds
)
LLVM_DEBUG
(
dbgs
(
)
<<
*
Add
<<
"\n"
)
;
for
(
auto
&
Mul
:
Muls
)
LLVM_DEBUG
(
dbgs
(
)
<<
*
Mul
->
Root
<<
"\n"
<<
"  "
<<
*
Mul
->
LHS
<<
"\n"
<<
"  "
<<
*
Mul
->
RHS
<<
"\n"
)
;
LLVM_DEBUG
(
if
(
Acc
)
dbgs
(
)
<<
"Acc in: "
<<
*
Acc
<<
"\n"
)
)
;
}
</s>

Dump the plan to stderr ( for debugging ) .


<s> static bool isNodeHidden ( const T N , const MCallSubGraph & G ) { return G . isNodeHidden ( N ) ; } </s>

Do not print nodes that are part of a pi-block separately .


"frame pointer should not have been eliminated"

"SecondSPAdjustAmount should be greater than zero"


<s> static bool or1k_legitimate_constant_p ( machine_mode , rtx x ) { switch ( GET_CODE ( x ) ) { case CONST_INT : case CONST_WIDE_INT : case HIGH : return true ; case CONST : case SYMBOL_REF : case LABEL_REF : return or1k_tls_symbolic_operand ( x ) == TLS_MODEL_NONE ; default : return false ; } } </s>

Worker for TARGET_LEGITIMATE_CONSTANT_P . Returns true is the RTX X represents a constant that can be used as an immediate operand in OpenRISC .


<s> void WebAssemblyPassConfig :: addIRPasses ( ) { if ( TM -> Options . ThreadModel == ThreadModel :: Single ) addPass ( createLowerAtomicPass ( ) ) ; else addPass ( createAtomicExpandPass ( TM ) ) ; addPass ( createWebAssemblyFixFunctionBitcasts ( ) ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) addPass ( createWebAssemblyOptimizeReturned ( ) ) ; if ( ! EnableEmException ) { addPass ( createLowerInvokePass ( ) ) ; addPass ( createUnreachableBlockEliminationPass ( ) ) ; } if ( EnableEmException || EnableEmSjLj ) addPass ( createWebAssemblyLowerEmscriptenEHSjLj ( EnableEmException , EnableEmSjLj ) ) ; TargetPassConfig :: addIRPasses ( ) ; } </s>

Add common target configurable passes that perform LLVM IR to IR transforms following machine independent optimization .

WebAssembly WebAssembly WebAssembly WebAssembly WebAssembly


"********** ARM EXPAND PSEUDO INSTRUCTIONS **********\n"

"After expanding ARM pseudo instructions."

runOnMachineFunction - Emit the function body .


<s>
static
void
nds32_asm_function_prologue
(
FILE
*
file
)
{
int
r
;
const
char
*
func_name
;
tree
attrs
;
tree
name
;
fprintf
(
file
,
"\t! BEGIN PROLOGUE\n"
)
;
fprintf
(
file
,
"\t!     fp needed: %d\n"
,
frame_pointer_needed
)
;
fprintf
(
file
,
"\t!  pretend_args: %d\n"
,
cfun
->
machine
->
va_args_size
)
;
fprintf
(
file
,
"\t!    local_size: %d\n"
,
cfun
->
machine
->
local_size
)
;
fprintf
(
file
,
"\t! out_args_size: %d\n"
,
cfun
->
machine
->
out_args_size
)
;
fprintf
(
file
,
"\t! registers ever_live: "
)
;
for
(
r
=
0
;
r
<
65
;
r
++
)
{
if
(
df_regs_ever_live_p
(
r
)
)
fprintf
(
file
,
"%s, "
,
reg_names
[
r
]
)
;
}
fputc
(
'\n'
,
file
)
;
fprintf
(
file
,
"\t! function attributes: "
)
;
attrs
=
DECL_ATTRIBUTES
(
current_function_decl
)
;
if
(
!
attrs
)
fprintf
(
file
,
"None"
)
;
func_name
=
IDENTIFIER_POINTER
(
DECL_NAME
(
current_function_decl
)
)
;
nds32_construct_isr_vectors_information
(
attrs
,
func_name
)
;
while
(
attrs
)
{
name
=
TREE_PURPOSE
(
attrs
)
;
fprintf
(
file
,
"%s "
,
IDENTIFIER_POINTER
(
name
)
)
;
attrs
=
TREE_CHAIN
(
attrs
)
;
}
fputc
(
'\n'
,
file
)
;
}
</s>

The content produced from this function will be placed before prologue body .

nds32
"\t! BEGIN PROLOGUE\n"
"\t!     fp needed: %d\n"
"\t!  pretend_args: %d\n"
"\t!    local_size: %d\n"
"\t! out_args_size: %d\n"
"\t! registers ever_live: "
0
65
"%s, "
"\t! function attributes: "
"None"
"%s "


<s> bool MOSFrameLowering :: spillCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , ArrayRef < CalleeSavedInfo > CSI , const TargetRegisterInfo * TRI ) const { MachineIRBuilder Builder ( MBB , MI ) ; MachineInstrSpan MIS ( MI , & MBB ) ; const MOSSubtarget & STI = MBB . getParent ( ) -> getSubtarget < MOSSubtarget > ( ) ; const TargetInstrInfo & TII = * STI . getInstrInfo ( ) ; const TargetRegisterClass & StackRegClass = STI . has65C02 ( ) ? MOS :: GPRRegClass : MOS :: AcRegClass ; for ( const CalleeSavedInfo & CI : CSI ) { Register Reg = CI . getReg ( ) ; if ( ! CI . isTargetSpilled ( ) ) continue ; if ( ! StackRegClass . contains ( Reg ) ) Reg = Builder . buildCopy ( & StackRegClass , Reg ) . getReg ( 0 ) ; Builder . buildInstr ( MOS :: PH , { } , { Reg } ) ; } for ( auto & MI : make_range ( MIS . begin ( ) , MIS . getInitial ( ) ) ) MI . setFlag ( MachineInstr :: FrameSetup ) ; for ( const CalleeSavedInfo & CI : CSI ) { Register Reg = CI . getReg ( ) ; if ( CI . isTargetSpilled ( ) ) continue ; assert ( ! CI . isSpilledToReg ( ) ) ; const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ; TII . storeRegToStackSlot ( MBB , Builder . getInsertPt ( ) , Reg , true , CI . getFrameIdx ( ) , RC , TRI ) ; } return true ; } </s>

spillCalleeSavedRegisters - Issues instruction ( s ) to spill all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of store instructions via storeRegToStackSlot ( ) .

MOS MOS MOS MOS MOS::GPRRegClass MOS::AcRegClass 0 MOS::PH


<s> void SIRegisterInfo :: materializeFrameBaseRegister ( MachineBasicBlock * MBB , unsigned BaseReg , int FrameIdx , int64_t Offset ) const { MachineBasicBlock :: iterator Ins = MBB -> begin ( ) ; DebugLoc DL ; if ( Ins != MBB -> end ( ) ) DL = Ins -> getDebugLoc ( ) ; MachineFunction * MF = MBB -> getParent ( ) ; const AMDGPUSubtarget & Subtarget = MF -> getSubtarget < AMDGPUSubtarget > ( ) ; const TargetInstrInfo * TII = Subtarget . getInstrInfo ( ) ; if ( Offset == 0 ) { BuildMI ( * MBB , Ins , DL , TII -> get ( AMDGPU :: V_MOV_B32_e32 ) , BaseReg ) . addFrameIndex ( FrameIdx ) ; return ; } MachineRegisterInfo & MRI = MF -> getRegInfo ( ) ; unsigned UnusedCarry = MRI . createVirtualRegister ( & AMDGPU :: SReg_64RegClass ) ; BuildMI ( * MBB , Ins , DL , TII -> get ( AMDGPU :: V_ADD_I32_e64 ) , BaseReg ) . addReg ( UnusedCarry , RegState :: Define | RegState :: Dead ) . addImm ( Offset ) . addFrameIndex ( FrameIdx ) ; } </s>

Insert defining instruction ( s ) for a pointer to FrameIdx before insertion point I .


<s> static void rs6000_emit_nmsub ( rtx dst , rtx m1 , rtx m2 , rtx a ) { machine_mode mode = GET_MODE ( dst ) ; rtx r ; gcc_assert ( optab_handler ( fma_optab , mode ) != CODE_FOR_nothing ) ; r = gen_rtx_NEG ( mode , a ) ; r = gen_rtx_FMA ( mode , m1 , m2 , r ) ; r = gen_rtx_NEG ( mode , r ) ; emit_insn ( gen_rtx_SET ( VOIDmode , dst , r ) ) ; } </s>

Generate a FNMSUB instruction : dst = -fma ( m1 , m2 , -a ) .


<s> static AArch64Operand * CreateReg ( unsigned RegNum , SMLoc S , SMLoc E ) { AArch64Operand * Op = new AArch64Operand ( k_Register , S , E ) ; Op -> Reg . RegNum = RegNum ; return Op ; } </s>

CreateReg - Allocate a single virtual register for the given type .


<s> static rtx riscv_function_arg ( cumulative_args_t cum_v , enum machine_mode mode , const_tree type , bool named ) { CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; struct riscv_arg_info info ; if ( mode == VOIDmode ) return NULL ; return riscv_get_arg_info ( & info , cum , mode , type , named , false ) ; } </s>


<s> const TargetRegisterClass * X86RegisterInfo :: getCrossCopyRegClass ( const TargetRegisterClass * RC ) const { if ( RC == & X86 :: CCRRegClass ) { if ( Is64Bit ) return & X86 :: GR64RegClass ; else return & X86 :: GR32RegClass ; } return RC ; } </s>

getCrossCopyRegClass - Returns a legal register class to copy a register in the specified class to or from .


<s> SMLoc getEndLoc ( ) const override { return End ; } </s>

getEndLoc - Get the location of the last token of this operand .


<s> MipsInstrInfo :: BranchType MipsInstrInfo :: analyzeBranch ( MachineBasicBlock & MBB , MachineBasicBlock * & TBB , MachineBasicBlock * & FBB , SmallVectorImpl < MachineOperand > & Cond , bool AllowModify , SmallVectorImpl < MachineInstr * > & BranchInstrs ) const { MachineBasicBlock :: reverse_iterator I = MBB . rbegin ( ) , REnd = MBB . rend ( ) ; while ( I != REnd && I -> isDebugValue ( ) ) ++ I ; if ( I == REnd || ! isUnpredicatedTerminator ( * I ) ) { TBB = FBB = nullptr ; return BT_NoBranch ; } MachineInstr * LastInst = & * I ; unsigned LastOpc = LastInst -> getOpcode ( ) ; BranchInstrs . push_back ( LastInst ) ; if ( ! getAnalyzableBrOpc ( LastOpc ) ) return LastInst -> isIndirectBranch ( ) ? BT_Indirect : BT_None ; unsigned SecondLastOpc = 0 ; MachineInstr * SecondLastInst = nullptr ; if ( ++ I != REnd ) { SecondLastInst = & * I ; SecondLastOpc = getAnalyzableBrOpc ( SecondLastInst -> getOpcode ( ) ) ; if ( isUnpredicatedTerminator ( * SecondLastInst ) && ! SecondLastOpc ) return BT_None ; } if ( ! SecondLastOpc ) { if ( LastInst -> isUnconditionalBranch ( ) ) { TBB = LastInst -> getOperand ( 0 ) . getMBB ( ) ; return BT_Uncond ; } AnalyzeCondBr ( LastInst , LastOpc , TBB , Cond ) ; return BT_Cond ; } if ( ++ I != REnd && isUnpredicatedTerminator ( * I ) ) return BT_None ; BranchInstrs . insert ( BranchInstrs . begin ( ) , SecondLastInst ) ; if ( SecondLastInst -> isUnconditionalBranch ( ) ) { if ( ! AllowModify ) return BT_None ; TBB = SecondLastInst -> getOperand ( 0 ) . getMBB ( ) ; LastInst -> eraseFromParent ( ) ; BranchInstrs . pop_back ( ) ; return BT_Uncond ; } if ( ! LastInst -> isUnconditionalBranch ( ) ) return BT_None ; AnalyzeCondBr ( SecondLastInst , SecondLastOpc , TBB , Cond ) ; FBB = LastInst -> getOperand ( 0 ) . getMBB ( ) ; return BT_CondUncond ; } </s>

analyzeBranch - Analyze the branching code at the end of MBB , returning true if it can not be understood ( e.g .


<s> int frv_emit_cond_move ( rtx dest , rtx test_rtx , rtx src1 , rtx src2 ) { rtx set ; rtx clobber_cc ; rtx test2 ; rtx cr_reg ; rtx if_rtx ; enum rtx_code test = GET_CODE ( test_rtx ) ; rtx cc_reg = frv_emit_comparison ( test , XEXP ( test_rtx , 0 ) , XEXP ( test_rtx , 1 ) ) ; machine_mode cc_mode = GET_MODE ( cc_reg ) ; if ( GET_CODE ( src1 ) == CONST_INT && GET_CODE ( src2 ) == CONST_INT ) { HOST_WIDE_INT value1 = INTVAL ( src1 ) ; HOST_WIDE_INT value2 = INTVAL ( src2 ) ; if ( value1 == 0 || value2 == 0 ) ; else if ( IN_RANGE ( value1 , - 2048 , 2047 ) && IN_RANGE ( value2 - value1 , - 2048 , 2047 ) ) ; else { src1 = force_reg ( GET_MODE ( dest ) , src1 ) ; src2 = force_reg ( GET_MODE ( dest ) , src2 ) ; } } else { if ( GET_CODE ( src1 ) == CONST_INT && INTVAL ( src1 ) != 0 ) src1 = force_reg ( GET_MODE ( dest ) , src1 ) ; if ( GET_CODE ( src2 ) == CONST_INT && INTVAL ( src2 ) != 0 ) src2 = force_reg ( GET_MODE ( dest ) , src2 ) ; } test2 = gen_rtx_fmt_ee ( test , cc_mode , cc_reg , const0_rtx ) ; if_rtx = gen_rtx_IF_THEN_ELSE ( GET_MODE ( dest ) , test2 , src1 , src2 ) ; set = gen_rtx_SET ( dest , if_rtx ) ; cr_reg = ( ( TARGET_ALLOC_CC ) ? gen_reg_rtx ( CC_CCRmode ) : gen_rtx_REG ( CC_CCRmode , ( cc_mode == CC_FPmode ) ? FCR_FIRST : ICR_FIRST ) ) ; clobber_cc = gen_rtx_CLOBBER ( VOIDmode , cr_reg ) ; emit_insn ( gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( 2 , set , clobber_cc ) ) ) ; return TRUE ; } </s>

Emit the code for a conditional move , return TRUE if we could do the move .


<s> const char * AGCTargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( ( AGCISD :: NodeType ) Opcode ) { default : break ; case AGCISD :: RET_FLAG : return "AGCISD::RET_FLAG" ; } return nullptr ; } </s>

getTargetNodeName - This method returns the name of a target specific


"Frame indices can only appear as the first "

"operand of a DBG_VALUE machine instruction"


<s> virtual const Cpu0RegisterInfo * getRegisterInfo ( ) const { return & InstrInfo . getRegisterInfo ( ) ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s>
bool
SelectInlineAsmMemoryOperand
(
const
SDValue
&
Op
,
unsigned
ConstraintID
,
std
::
vector
<
SDValue
>
&
OutOps
)
override
{
switch
(
ConstraintID
)
{
default
:
errs
(
)
<<
"ConstraintID: "
<<
ConstraintID
<<
"\n"
;
llvm_unreachable
(
"Unexpected asm memory constraint"
)
;
case
InlineAsm
::
Constraint_es
:
case
InlineAsm
::
Constraint_i
:
case
InlineAsm
::
Constraint_m
:
case
InlineAsm
::
Constraint_o
:
case
InlineAsm
::
Constraint_Q
:
case
InlineAsm
::
Constraint_Z
:
case
InlineAsm
::
Constraint_Zy
:
const
TargetRegisterInfo
*
TRI
=
PPCSubTarget
->
getRegisterInfo
(
)
;
const
TargetRegisterClass
*
TRC
=
TRI
->
getPointerRegClass
(
*
MF
,
1
)
;
SDValue
RC
=
CurDAG
->
getTargetConstant
(
TRC
->
getID
(
)
,
MVT
::
i32
)
;
SDValue
NewOp
=
SDValue
(
CurDAG
->
getMachineNode
(
TargetOpcode
::
COPY_TO_REGCLASS
,
SDLoc
(
Op
)
,
Op
.
getValueType
(
)
,
Op
,
RC
)
,
0
)
;
OutOps
.
push_back
(
NewOp
)
;
return
false
;
}
return
true
;
}
</s>

SelectInlineAsmMemoryOperand - Select the specified address as a target addressing mode , according to the specified constraint .


<s>
const
char
*
th_mempair_output_move
(
rtx
operands
[
4
]
,
bool
load_p
,
machine_mode
mode
,
RTX_CODE
code
)
{
rtx
reg1
,
reg2
,
mem1
,
mem2
,
base1
,
base2
;
HOST_WIDE_INT
offset1
,
offset2
;
rtx
output_operands
[
5
]
;
const
char
*
format
;
gcc_assert
(
mode
==
SImode
||
mode
==
DImode
)
;
unsigned
shamt
=
(
mode
==
DImode
)
4
:
3
;
if
(
load_p
)
{
reg1
=
copy_rtx
(
operands
[
0
]
)
;
reg2
=
copy_rtx
(
operands
[
2
]
)
;
mem1
=
copy_rtx
(
operands
[
1
]
)
;
mem2
=
copy_rtx
(
operands
[
3
]
)
;
if
(
mode
==
SImode
)
if
(
code
==
ZERO_EXTEND
)
format
=
"th.lwud\t%0, %1, (%2), %3, %4"
;
else
format
=
"th.lwd\t%0, %1, (%2), %3, %4"
;
else
format
=
"th.ldd\t%0, %1, (%2), %3, %4"
;
}
else
{
reg1
=
copy_rtx
(
operands
[
1
]
)
;
reg2
=
copy_rtx
(
operands
[
3
]
)
;
mem1
=
copy_rtx
(
operands
[
0
]
)
;
mem2
=
copy_rtx
(
operands
[
2
]
)
;
if
(
mode
==
SImode
)
format
=
"th.swd\t%z0, %z1, (%2), %3, %4"
;
else
format
=
"th.sdd\t%z0, %z1, (%2), %3, %4"
;
}
split_plus
(
XEXP
(
mem1
,
0
)
,
&
base1
,
&
offset1
)
;
split_plus
(
XEXP
(
mem2
,
0
)
,
&
base2
,
&
offset2
)
;
gcc_assert
(
rtx_equal_p
(
base1
,
base2
)
)
;
auto
size1
=
MEM_SIZE
(
mem1
)
;
auto
size2
=
MEM_SIZE
(
mem2
)
;
gcc_assert
(
known_eq
(
size1
,
size2
)
)
;
gcc_assert
(
known_eq
(
offset1
+
size1
,
offset2
)
)
;
HOST_WIDE_INT
imm2
=
offset1
>>
shamt
;
gcc_assert
(
imm2
>=
0
&&
imm2
<
4
)
;
gcc_assert
(
(
imm2
<<
shamt
)
==
offset1
)
;
gcc_assert
(
REG_P
(
reg1
)
)
;
gcc_assert
(
REG_P
(
reg2
)
)
;
gcc_assert
(
REG_P
(
base1
)
)
;
if
(
load_p
)
{
gcc_assert
(
REGNO
(
reg1
)
!=
REGNO
(
reg2
)
)
;
gcc_assert
(
REGNO
(
reg1
)
!=
REGNO
(
base1
)
)
;
gcc_assert
(
REGNO
(
reg2
)
!=
REGNO
(
base1
)
)
;
}
output_operands
[
0
]
=
copy_rtx
(
reg1
)
;
output_operands
[
1
]
=
copy_rtx
(
reg2
)
;
output_operands
[
2
]
=
copy_rtx
(
base1
)
;
output_operands
[
3
]
=
gen_rtx_CONST_INT
(
mode
,
imm2
)
;
output_operands
[
4
]
=
gen_rtx_CONST_INT
(
mode
,
shamt
)
;
output_asm_insn
(
format
,
output_operands
)
;
return
""
;
}
</s>

Output a mempair instruction with the provided OPERANDS . LOAD_P is true if a we have a pair of loads ( stores otherwise ) . MODE is the access mode ( DI or SI ) . CODE is the extension code ( UNKNOWN , SIGN_EXTEND or ZERO_EXTEND ) . This instruction does not handle invalid inputs gracefully , but is full of assertions to ensure that only valid instructions are emitted .


"SIInstrInfo::storeRegToStackSlot - Do not know how to"

Store the specified register of the given register class to the specified stack frame index .


<s>
void
RISCVAsmBackend
::
applyFixup
(
const
MCAssembler
&
Asm
,
const
MCFixup
&
Fixup
,
const
MCValue
&
Target
,
MutableArrayRef
<
char
>
Data
,
uint64_t
Value
,
bool
IsResolved
)
const
{
MCContext
&
Ctx
=
Asm
.
getContext
(
)
;
MCFixupKind
Kind
=
Fixup
.
getKind
(
)
;
unsigned
NumBytes
=
(
getFixupKindInfo
(
Kind
)
.
TargetSize
+
7
)
/
8
;
if
(
!
Value
)
return
;
MCFixupKindInfo
Info
=
getFixupKindInfo
(
Fixup
.
getKind
(
)
)
;
Value
=
adjustFixupValue
(
Fixup
,
Value
,
Ctx
)
;
Value
<<=
Info
.
TargetOffset
;
unsigned
Offset
=
Fixup
.
getOffset
(
)
;
assert
(
Offset
+
NumBytes
<=
Data
.
size
(
)
&&
"Invalid fixup offset!"
)
;
for
(
unsigned
i
=
0
;
i
!=
4
;
++
i
)
{
Data
[
Offset
+
i
]
|=
uint8_t
(
(
Value
>>
(
i
*
8
)
)
&
0xff
)
;
}
return
;
}
</s>

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


<s>
static
void
init_output_initializer
(
FILE
*
file
,
const
char
*
name
,
const_tree
type
,
bool
is_public
)
{
fprintf
(
file
,
"// BEGIN%s VAR DEF: "
,
is_public
" GLOBAL"
:
""
)
;
assemble_name_raw
(
file
,
name
)
;
fputc
(
'\n'
,
file
)
;
if
(
TREE_CODE
(
type
)
==
ARRAY_TYPE
)
type
=
TREE_TYPE
(
type
)
;
int
sz
=
int_size_in_bytes
(
type
)
;
if
(
(
TREE_CODE
(
type
)
!=
INTEGER_TYPE
&&
TREE_CODE
(
type
)
!=
ENUMERAL_TYPE
&&
TREE_CODE
(
type
)
!=
REAL_TYPE
)
||
sz
<
0
||
sz
>
HOST_BITS_PER_WIDE_INT
)
type
=
ptr_type_node
;
decl_chunk_size
=
int_size_in_bytes
(
type
)
;
decl_chunk_mode
=
int_mode_for_mode
(
TYPE_MODE
(
type
)
)
;
decl_offset
=
0
;
init_part
=
0
;
object_finished
=
false
;
}
</s>

Start a declaration of a variable of TYPE with NAME to FILE . IS_PUBLIC says whether this will be externally visible . Here we just write the linker hint and decide on the chunk size to use .


<s> void rvexMCInstLower :: Initialize ( Mangler * M , MCContext * C ) { Mang = M ; Ctx = C ; } </s>

This method must be called before any actual lowering is done .


"LoongArch DAG->DAG Pattern Instruction Selection"

getPassName - Return a nice clean name for a pass .


<s> bool AArch64InstrInfo :: getMemOperandWithOffset ( const MachineInstr & LdSt , const MachineOperand * & BaseOp , int64_t & Offset , const TargetRegisterInfo * TRI ) const { unsigned Width ; return getMemOperandWithOffsetWidth ( LdSt , BaseOp , Offset , Width , TRI ) ; } </s>

Get the base operand and byte offset of an instruction that reads/writes memory .


<s> const InstrItineraryData & getInstrItineraryData ( ) const { return InstrItins ; } </s>

getInstrItineraryData - Returns instruction itinerary data for the target or specific subtarget .


<s> static int mips_fp_mult_cost ( machine_mode mode ) { return mode == DFmode ? mips_cost -> fp_mult_df : mips_cost -> fp_mult_sf ; } </s>

Return the cost of floating-point multiplications of mode MODE .


<s> void ARMAsmPrinter :: emitFunctionBodyEnd ( ) { if ( ! InConstantPool ) return ; InConstantPool = false ; OutStreamer -> emitDataRegion ( MCDR_DataRegionEnd ) ; } </s>

Targets can override this to emit stuff after the last basic block in the function .


<s> static void spu_va_start ( tree valist , rtx nextarg ) { tree f_args , f_skip ; tree args , skip , t ; f_args = TYPE_FIELDS ( TREE_TYPE ( va_list_type_node ) ) ; f_skip = DECL_CHAIN ( f_args ) ; valist = build_simple_mem_ref ( valist ) ; args = build3 ( COMPONENT_REF , TREE_TYPE ( f_args ) , valist , f_args , NULL_TREE ) ; skip = build3 ( COMPONENT_REF , TREE_TYPE ( f_skip ) , valist , f_skip , NULL_TREE ) ; t = make_tree ( TREE_TYPE ( args ) , nextarg ) ; if ( crtl -> args . pretend_args_size > 0 ) t = fold_build_pointer_plus_hwi ( t , - STACK_POINTER_OFFSET ) ; t = build2 ( MODIFY_EXPR , TREE_TYPE ( args ) , args , t ) ; TREE_SIDE_EFFECTS ( t ) = 1 ; expand_expr ( t , const0_rtx , VOIDmode , EXPAND_NORMAL ) ; t = make_tree ( TREE_TYPE ( skip ) , virtual_incoming_args_rtx ) ; t = fold_build_pointer_plus_hwi ( t , ( crtl -> args . pretend_args_size - STACK_POINTER_OFFSET ) ) ; t = build2 ( MODIFY_EXPR , TREE_TYPE ( skip ) , skip , t ) ; TREE_SIDE_EFFECTS ( t ) = 1 ; expand_expr ( t , const0_rtx , VOIDmode , EXPAND_NORMAL ) ; } </s>

Implement va_start by filling the va_list structure VALIST . NEXTARG points to the first anonymous stack argument . The following global variables are used to initialize the va_list structure : crtl- > args.info ; the CUMULATIVE_ARGS for this function crtl- > args.arg_offset_rtx : holds the offset of the first anonymous stack argument ( relative to the virtual arg pointer ) .


<s> bool SystemZRegisterInfo :: hasFP ( const MachineFunction & MF ) const { const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; return NoFramePointerElim || MFI -> hasVarSizedObjects ( ) ; } </s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .


<s>
void
GBZ80SectionData
::
getAsString
(
SmallVectorImpl
<
char
>
&
Str
)
const
{
raw_svector_ostream
O
(
Str
)
;
if
(
SectionName
.
empty
(
)
)
O
<<
"SECTION @,"
;
else
O
<<
"SECTION \""
<<
SectionName
<<
"\","
;
switch
(
Type
)
{
case
ST_ROM0
:
O
<<
"ROM0"
;
break
;
case
ST_ROMX
:
O
<<
"ROMX"
;
break
;
case
ST_VRAM
:
O
<<
"VRAM"
;
break
;
case
ST_SRAM
:
O
<<
"SRAM"
;
break
;
case
ST_WRAM0
:
O
<<
"WRAM0"
;
break
;
case
ST_WRAMX
:
O
<<
"WRAMX"
;
break
;
case
ST_OAM
:
O
<<
"OAM"
;
break
;
case
ST_HRAM
:
O
<<
"HRAM"
;
break
;
default
:
llvm_unreachable
(
"Tried to print an invalid section!"
)
;
}
if
(
hasAddress
(
)
)
O
<<
"[$"
<<
format
(
"%04x"
,
Address
)
<<
"]"
;
if
(
hasBank
(
)
)
O
<<
",BANK["
<<
Bank
<<
"]"
;
if
(
hasAlignment
(
)
)
O
<<
",ALIGN["
<<
Log2_32_Ceil
(
Alignment
)
<<
"]"
;
}
</s>

Retrieve a string representation of the version number .

GBZ80
GB
"SECTION @,"
"SECTION \""
"\","
"ROM0"
"ROMX"
"VRAM"
"SRAM"
"WRAM0"
"WRAMX"
"OAM"
"HRAM"
"Tried to print an invalid section!"
"[$"
"%04x"
"]"
",BANK["
"]"
",ALIGN["
"]"


<s> bool isMem ( ) const { return Kind == k_Memory ; } </s>


<s> bool runOnMachineFunction ( MachineFunction & MF ) override { TII = MF . getSubtarget < R600Subtarget > ( ) . getInstrInfo ( ) ; TRI = & TII -> getRegisterInfo ( ) ; DEBUG ( MF . dump ( ) ; ) ; OrderedBlks . clear ( ) ; Visited . clear ( ) ; FuncRep = & MF ; MLI = & getAnalysis < MachineLoopInfo > ( ) ; DEBUG ( dbgs ( ) << "LoopInfo:\n" ; PrintLoopinfo ( * MLI ) ; ) ; MDT = & getAnalysis < MachineDominatorTree > ( ) ; DEBUG ( MDT -> print ( dbgs ( ) , ( const llvm :: Module * ) nullptr ) ; ) ; PDT = & getAnalysis < MachinePostDominatorTree > ( ) ; DEBUG ( PDT -> print ( dbgs ( ) ) ; ) ; prepare ( ) ; run ( ) ; DEBUG ( MF . dump ( ) ; ) ; return true ; } </s>

runOnMachineFunction - Emit the function body .


"insertBranch must not be told to insert a fallthrough"

"ARM branch conditions have two components!"

Insert branch code into the end of the specified MachineBasicBlock .


<s> gimple * fold ( gimple_folder & f ) const OVERRIDE { poly_uint64 nelts = TYPE_VECTOR_SUBPARTS ( TREE_TYPE ( f . lhs ) ) ; poly_uint64 base = m_base * exact_div ( nelts , 2 ) ; vec_perm_builder builder ( nelts , 2 , 3 ) ; for ( unsigned int i = 0 ; i < 3 ; ++ i ) { builder . quick_push ( base + i ) ; builder . quick_push ( base + i + nelts ) ; } return fold_permute ( f , builder ) ; } </s>

Try to fold the call . Return the new statement on success and null on failure .


"Couldn't assign to global base register!"

getGlobalBaseReg - Return a virtual register initialized with the the global base register value .


For most targets , an LLVM type must be broken down into multiple smaller types .


<s> bool X86TargetLowering :: isShuffleMaskLegal ( const SmallVectorImpl < int > & M , EVT VT ) const { if ( VT . getSizeInBits ( ) == 64 ) return isPALIGNRMask ( M , VT , Subtarget -> hasSSSE3orAVX ( ) ) ; return ( VT . getVectorNumElements ( ) == 2 || ShuffleVectorSDNode :: isSplatMask ( & M [ 0 ] , VT ) || isMOVLMask ( M , VT ) || isSHUFPMask ( M , VT ) || isPSHUFDMask ( M , VT ) || isPSHUFHWMask ( M , VT ) || isPSHUFLWMask ( M , VT ) || isPALIGNRMask ( M , VT , Subtarget -> hasSSSE3orAVX ( ) ) || isUNPCKLMask ( M , VT , Subtarget -> hasAVX2 ( ) ) || isUNPCKHMask ( M , VT , Subtarget -> hasAVX2 ( ) ) || isUNPCKL_v_undef_Mask ( M , VT ) || isUNPCKH_v_undef_Mask ( M , VT ) ) ; } </s>

Targets can use this to indicate that they only support some VECTOR_SHUFFLE operations , those with specific masks .


<s> bool SIAnnotateControlFlow :: doInitialization ( Module & M ) { LLVMContext & Context = M . getContext ( ) ; Void = Type :: getVoidTy ( Context ) ; Boolean = Type :: getInt1Ty ( Context ) ; Int64 = Type :: getInt64Ty ( Context ) ; ReturnStruct = StructType :: get ( Boolean , Int64 , ( Type * ) nullptr ) ; BoolTrue = ConstantInt :: getTrue ( Context ) ; BoolFalse = ConstantInt :: getFalse ( Context ) ; BoolUndef = UndefValue :: get ( Boolean ) ; Int64Zero = ConstantInt :: get ( Int64 , 0 ) ; If = M . getOrInsertFunction ( IfIntrinsic , ReturnStruct , Boolean , ( Type * ) nullptr ) ; Else = M . getOrInsertFunction ( ElseIntrinsic , ReturnStruct , Int64 , ( Type * ) nullptr ) ; Break = M . getOrInsertFunction ( BreakIntrinsic , Int64 , Int64 , ( Type * ) nullptr ) ; IfBreak = M . getOrInsertFunction ( IfBreakIntrinsic , Int64 , Boolean , Int64 , ( Type * ) nullptr ) ; ElseBreak = M . getOrInsertFunction ( ElseBreakIntrinsic , Int64 , Int64 , Int64 , ( Type * ) nullptr ) ; Loop = M . getOrInsertFunction ( LoopIntrinsic , Boolean , Int64 , ( Type * ) nullptr ) ; EndCf = M . getOrInsertFunction ( EndCfIntrinsic , Void , Int64 , ( Type * ) nullptr ) ; return false ; } </s>

Set up the AsmPrinter when we are working on a new module .


<s>
Function
*
AMDGPUIntrinsicInfo
::
getDeclaration
(
Module
*
M
,
unsigned
IntrID
,
Type
*
*
Tys
,
unsigned
numTys
)
const
{
llvm_unreachable
(
"Not implemented"
)
;
}
</s>

Create or insert an LLVM Function declaration for an intrinsic , and return it .


<s> static int try_issue_nops ( struct bundle_state * curr_state , int nops_num ) { int i ; for ( i = 0 ; i < nops_num ; i ++ ) if ( state_transition ( curr_state -> dfa_state , ia64_nop ) >= 0 ) { free_bundle_state ( curr_state ) ; return FALSE ; } return TRUE ; } </s>

The following function tries to issue NOPS_NUM nops for the current state without advancing processor cycle . If it failed , the function returns FALSE and frees the current state .


<s> void ix86_emit_i387_log1p ( rtx op0 , rtx op1 ) { rtx_code_label * label1 = gen_label_rtx ( ) ; rtx_code_label * label2 = gen_label_rtx ( ) ; rtx tmp = gen_reg_rtx ( XFmode ) ; rtx tmp2 = gen_reg_rtx ( XFmode ) ; rtx test ; emit_insn ( gen_absxf2 ( tmp , op1 ) ) ; test = gen_rtx_GE ( VOIDmode , tmp , CONST_DOUBLE_FROM_REAL_VALUE ( REAL_VALUE_ATOF ( "0.29289321881345247561810596348408353" , XFmode ) , XFmode ) ) ; emit_jump_insn ( gen_cbranchxf4 ( test , XEXP ( test , 0 ) , XEXP ( test , 1 ) , label1 ) ) ; emit_move_insn ( tmp2 , standard_80387_constant_rtx ( 4 ) ) ; emit_insn ( gen_fyl2xp1xf3_i387 ( op0 , op1 , tmp2 ) ) ; emit_jump ( label2 ) ; emit_label ( label1 ) ; emit_move_insn ( tmp , CONST1_RTX ( XFmode ) ) ; emit_insn ( gen_addxf3 ( tmp , op1 , tmp ) ) ; emit_move_insn ( tmp2 , standard_80387_constant_rtx ( 4 ) ) ; emit_insn ( gen_fyl2xxf3_i387 ( op0 , tmp , tmp2 ) ) ; emit_label ( label2 ) ; } </s>

Output code to perform a log1p XFmode calculation .


<s> int ix86_attr_length_address_default ( rtx_insn * insn ) { int i ; if ( get_attr_type ( insn ) == TYPE_LEA ) { rtx set = PATTERN ( insn ) , addr ; if ( GET_CODE ( set ) == PARALLEL ) set = XVECEXP ( set , 0 , 0 ) ; gcc_assert ( GET_CODE ( set ) == SET ) ; addr = SET_SRC ( set ) ; return memory_address_length ( addr , true ) ; } extract_insn_cached ( insn ) ; for ( i = recog_data . n_operands - 1 ; i >= 0 ; -- i ) { rtx op = recog_data . operand [ i ] ; if ( MEM_P ( op ) ) { constrain_operands_cached ( insn , reload_completed ) ; if ( which_alternative != - 1 ) { const char * constraints = recog_data . constraints [ i ] ; int alt = which_alternative ; while ( * constraints == '=' || * constraints == '+' ) constraints ++ ; while ( alt -- > 0 ) while ( * constraints ++ != ',' ) ; if ( * constraints == 'X' ) continue ; } int len = memory_address_length ( XEXP ( op , 0 ) , false ) ; if ( ! ADDR_SPACE_GENERIC_P ( MEM_ADDR_SPACE ( op ) ) ) len ++ ; return len ; } } return 0 ; } </s>

Compute default value for `` length_address '' attribute .


<s> inline bool function_base :: apply_mask_policy_p ( ) const { return true ; } </s>

We choose to apply mask policy operand by default since most of the intrinsics has mask policy operand .


<s> void MipsPassConfig :: addMachineSSAOptimization ( ) { addPass ( createMipsOptimizePICCallPass ( getMipsTargetMachine ( ) ) ) ; TargetPassConfig :: addMachineSSAOptimization ( ) ; } </s>

Methods with trivial inline returns are convenient points in the common codegen pass pipeline where targets may insert passes .


<s> void HexagonInstrInfo :: copyPhysReg ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , DebugLoc DL , unsigned DestReg , unsigned SrcReg , bool KillSrc ) const { if ( Hexagon :: IntRegsRegClass . contains ( SrcReg , DestReg ) ) { BuildMI ( MBB , I , DL , get ( Hexagon :: TFR ) , DestReg ) . addReg ( SrcReg ) ; return ; } if ( Hexagon :: DoubleRegsRegClass . contains ( SrcReg , DestReg ) ) { BuildMI ( MBB , I , DL , get ( Hexagon :: TFR64 ) , DestReg ) . addReg ( SrcReg ) ; return ; } if ( Hexagon :: PredRegsRegClass . contains ( SrcReg , DestReg ) ) { BuildMI ( MBB , I , DL , get ( Hexagon :: OR_pp ) , DestReg ) . addReg ( SrcReg ) . addReg ( SrcReg ) ; return ; } if ( Hexagon :: DoubleRegsRegClass . contains ( DestReg ) && Hexagon :: IntRegsRegClass . contains ( SrcReg ) ) { if ( SrcReg == RI . getSubReg ( DestReg , Hexagon :: subreg_loreg ) ) { BuildMI ( MBB , I , DL , get ( Hexagon :: TFRI ) , ( RI . getSubReg ( DestReg , Hexagon :: subreg_hireg ) ) ) . addImm ( 0 ) ; } else { BuildMI ( MBB , I , DL , get ( Hexagon :: TFR ) , ( RI . getSubReg ( DestReg , Hexagon :: subreg_loreg ) ) ) . addReg ( SrcReg ) ; BuildMI ( MBB , I , DL , get ( Hexagon :: TFRI ) , ( RI . getSubReg ( DestReg , Hexagon :: subreg_hireg ) ) ) . addImm ( 0 ) ; } return ; } if ( Hexagon :: CRRegsRegClass . contains ( DestReg ) && Hexagon :: IntRegsRegClass . contains ( SrcReg ) ) { BuildMI ( MBB , I , DL , get ( Hexagon :: TFCR ) , DestReg ) . addReg ( SrcReg ) ; return ; } if ( Hexagon :: PredRegsRegClass . contains ( SrcReg ) && Hexagon :: IntRegsRegClass . contains ( DestReg ) ) { BuildMI ( MBB , I , DL , get ( Hexagon :: TFR_RsPd ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; return ; } if ( Hexagon :: IntRegsRegClass . contains ( SrcReg ) && Hexagon :: PredRegsRegClass . contains ( DestReg ) ) { BuildMI ( MBB , I , DL , get ( Hexagon :: TFR_PdRs ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; return ; } llvm_unreachable ( "Unimplemented" ) ; } </s>


"getJumpTargetOpValue expects only expressions"

"unexpect opcode in getJumpAbsoluteTargetOpValue()"

getJumpTargetOpValue - Return binary encoding of the jump target operand .


<s> Sched :: Preference ARMTargetLowering :: getSchedulingPreference ( SDNode * N ) const { unsigned NumVals = N -> getNumValues ( ) ; if ( ! NumVals ) return Sched :: RegPressure ; for ( unsigned i = 0 ; i != NumVals ; ++ i ) { EVT VT = N -> getValueType ( i ) ; if ( VT == MVT :: Glue || VT == MVT :: Other ) continue ; if ( VT . isFloatingPoint ( ) || VT . isVector ( ) ) return Sched :: ILP ; } if ( ! N -> isMachineOpcode ( ) ) return Sched :: RegPressure ; const TargetInstrInfo * TII = getTargetMachine ( ) . getInstrInfo ( ) ; const MCInstrDesc & MCID = TII -> get ( N -> getMachineOpcode ( ) ) ; if ( MCID . getNumDefs ( ) == 0 ) return Sched :: RegPressure ; if ( ! Itins -> isEmpty ( ) && Itins -> getOperandCycle ( MCID . getSchedClass ( ) , 0 ) > 2 ) return Sched :: ILP ; return Sched :: RegPressure ; } </s>


<s> bool lowerCall ( MachineIRBuilder & MIRBuilder , CallingConv :: ID CallConv , const MachineOperand & Callee , const ArgInfo & OrigRet , ArrayRef < ArgInfo > OrigArgs , const MDNode * KnownCallees = nullptr ) const override { return lowerCall ( MIRBuilder , CallConv , Callee , OrigRet , OrigArgs , 0 , KnownCallees ) ; } </s>

This hook must be implemented to lower the given call instruction , including argument and return value marshalling .


<s> virtual bool isUnconditionalBranch ( const MCInst & Inst ) const { if ( Inst . getOpcode ( ) == AArch64 :: Bcc && Inst . getOperand ( 0 ) . getImm ( ) == A64CC :: AL ) return true ; return MCInstrAnalysis :: isUnconditionalBranch ( Inst ) ; } </s>

Return true if this is a branch which always transfers control flow to some other block .


<s> bool runOnMachineFunction ( MachineFunction & MF ) override { if ( skipFunction ( * MF . getFunction ( ) ) ) return false ; X86MachineFunctionInfo * MFI = MF . getInfo < X86MachineFunctionInfo > ( ) ; if ( MFI -> getNumLocalDynamicTLSAccesses ( ) < 2 ) { return false ; } MachineDominatorTree * DT = & getAnalysis < MachineDominatorTree > ( ) ; return VisitNode ( DT -> getRootNode ( ) , 0 ) ; } </s>


<s> FastISel * ARMTargetLowering :: createFastISel ( FunctionLoweringInfo & funcInfo ) const { return ARM :: createFastISel ( funcInfo ) ; } </s>

This method returns a target specific FastISel object , or null if the target does not support `` fast '' ISel .


<s> bool PTXTargetMachine :: addPostRegAlloc ( PassManagerBase & PM , CodeGenOpt :: Level OptLevel ) { PM . add ( createPTXMFInfoExtract ( * this , OptLevel ) ) ; return false ; } </s>

This method may be implemented by targets that want to run passes after register allocation pass pipeline but before prolog-epilog insertion .


<s> void aarch64_expand_call ( rtx result , rtx mem , rtx callee_abi , bool sibcall ) { rtx call , callee , tmp ; rtvec vec ; machine_mode mode ; gcc_assert ( MEM_P ( mem ) ) ; callee = XEXP ( mem , 0 ) ; mode = GET_MODE ( callee ) ; gcc_assert ( mode == Pmode ) ; if ( SYMBOL_REF_P ( callee ) ? ( aarch64_is_long_call_p ( callee ) || aarch64_is_noplt_call_p ( callee ) ) : ! REG_P ( callee ) ) XEXP ( mem , 0 ) = force_reg ( mode , callee ) ; call = gen_rtx_CALL ( VOIDmode , mem , const0_rtx ) ; if ( result != NULL_RTX ) call = gen_rtx_SET ( result , call ) ; if ( sibcall ) tmp = ret_rtx ; else tmp = gen_rtx_CLOBBER ( VOIDmode , gen_rtx_REG ( Pmode , LR_REGNUM ) ) ; gcc_assert ( CONST_INT_P ( callee_abi ) ) ; callee_abi = gen_rtx_UNSPEC ( DImode , gen_rtvec ( 1 , callee_abi ) , UNSPEC_CALLEE_ABI ) ; vec = gen_rtvec ( 3 , call , callee_abi , tmp ) ; call = gen_rtx_PARALLEL ( VOIDmode , vec ) ; aarch64_emit_call_insn ( call ) ; } </s>

This function is used by the call expanders of the machine description . RESULT is the register in which the result is returned . It 's NULL for `` call '' and `` sibcall '' . MEM is the location of the function call . SIBCALL indicates whether this function call is normal call or sibling call . It will generate different pattern accordingly .


<s>
StringRef
getPassName
(
)
const
override
{
return
"SI Fix CF Live Intervals"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> const TargetRegisterClass * getPointerRegClass ( const MachineFunction & MF , unsigned Kind = 0 ) const override { return & LC2200 :: GRRegsRegClass ; } </s>

getPointerRegClass - Returns a TargetRegisterClass used for pointer values .


<s> virtual const PPCRegisterInfo & getRegisterInfo ( ) const { return RI ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s> virtual bool runOnMachineFunction ( MachineFunction & MF ) { MachineFrameInfo * FFI = MF . getFrameInfo ( ) ; MachineRegisterInfo & RI = MF . getRegInfo ( ) ; unsigned MaxAlign = calculateMaxStackAlignment ( FFI ) ; for ( unsigned RegNum = TargetRegisterInfo :: FirstVirtualRegister ; RegNum < RI . getLastVirtReg ( ) ; ++ RegNum ) MaxAlign = std :: max ( MaxAlign , RI . getRegClass ( RegNum ) -> getAlignment ( ) ) ; FFI -> setMaxAlignment ( MaxAlign ) ; return false ; } </s>

runOnMachineFunction - Emit the function body .


<s> bool LanaiAsmBackend :: writeNopData ( raw_ostream & OS , uint64_t Count ) const { if ( ( Count % 4 ) != 0 ) return false ; for ( uint64_t i = 0 ; i < Count ; i += 4 ) OS . write ( "\x15\0\0\0" , 4 ) ; return true ; } </s>

Write an ( optimal ) nop sequence of Count bytes to the given output .


<s>
const
MCFixupKindInfo
&
getFixupKindInfo
(
MCFixupKind
Kind
)
const
{
const
static
MCFixupKindInfo
Infos
[
PPC
::
NumTargetFixupKinds
]
=
{
{
"fixup_ppc_br24"
,
6
,
24
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_ppc_brcond14"
,
16
,
14
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_ppc_br24abs"
,
6
,
24
,
0
}
,
{
"fixup_ppc_brcond14abs"
,
16
,
14
,
0
}
,
{
"fixup_ppc_half16"
,
0
,
16
,
0
}
,
{
"fixup_ppc_half16ds"
,
0
,
14
,
0
}
,
{
"fixup_ppc_nofixup"
,
0
,
0
,
0
}
}
;
if
(
Kind
<
FirstTargetFixupKind
)
return
MCAsmBackend
::
getFixupKindInfo
(
Kind
)
;
assert
(
unsigned
(
Kind
FirstTargetFixupKind
)
<
getNumFixupKinds
(
)
&&
"Invalid kind!"
)
;
return
Infos
[
Kind
FirstTargetFixupKind
]
;
}
</s>


<s> int use_return_insn ( ) { int regno ; if ( ! reload_completed || frame_pointer_needed || get_frame_size ( ) != 0 ) return 0 ; for ( regno = 0 ; regno < FIRST_PSEUDO_REGISTER ; regno ++ ) if ( regs_ever_live [ regno ] && ! call_used_regs [ regno ] ) return 0 ; if ( flag_pic && current_function_uses_pic_offset_table ) return 0 ; return 1 ; } </s>

Return true if this function 's epilogue can be output as RTL .


<s> static bool mips_got_symbol_type_p ( enum mips_symbol_type type ) { switch ( type ) { case SYMBOL_GOT_PAGE_OFST : case SYMBOL_GOT_DISP : return true ; default : return false ; } } </s>

Return true if symbols of type TYPE require a GOT access .


<s> virtual void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . addRequired < DominatorTreeWrapperPass > ( ) ; AU . addPreserved < DominatorTreeWrapperPass > ( ) ; AU . addPreserved < MachineFunctionAnalysis > ( ) ; FunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> static void or1k_output_mi_thunk ( FILE * file , tree , HOST_WIDE_INT delta , HOST_WIDE_INT vcall_offset , tree function ) { rtx this_rtx , funexp ; rtx_insn * insn ; reload_completed = 1 ; epilogue_completed = 1 ; emit_note ( NOTE_INSN_PROLOGUE_END ) ; if ( aggregate_value_p ( TREE_TYPE ( TREE_TYPE ( function ) ) , function ) ) this_rtx = gen_rtx_REG ( Pmode , 4 ) ; else this_rtx = gen_rtx_REG ( Pmode , 3 ) ; if ( delta ) { rtx delta_rtx = GEN_INT ( delta ) ; if ( ! satisfies_constraint_I ( delta_rtx ) ) { rtx scratch = gen_rtx_REG ( Pmode , PE_TMP_REGNUM ) ; emit_move_insn ( scratch , delta_rtx ) ; delta_rtx = scratch ; } emit_insn ( gen_add2_insn ( this_rtx , delta_rtx ) ) ; } if ( vcall_offset ) { rtx scratch = gen_rtx_REG ( Pmode , PE_TMP_REGNUM ) ; HOST_WIDE_INT lo = sext_hwi ( vcall_offset , 16 ) ; HOST_WIDE_INT hi = vcall_offset - lo ; rtx tmp ; tmp = gen_rtx_MEM ( Pmode , this_rtx ) ; emit_move_insn ( scratch , tmp ) ; if ( hi != 0 ) { rtx scratch2 = gen_rtx_REG ( Pmode , RV_REGNUM ) ; emit_move_insn ( scratch2 , GEN_INT ( hi ) ) ; emit_insn ( gen_add2_insn ( scratch , scratch2 ) ) ; } tmp = plus_constant ( Pmode , scratch , lo ) ; tmp = gen_rtx_MEM ( Pmode , tmp ) ; emit_move_insn ( scratch , tmp ) ; emit_insn ( gen_add2_insn ( this_rtx , scratch ) ) ; } if ( ! TREE_USED ( function ) ) { assemble_external ( function ) ; TREE_USED ( function ) = 1 ; } funexp = XEXP ( DECL_RTL ( function ) , 0 ) ; gcc_assert ( SYMBOL_REF_LOCAL_P ( funexp ) ) ; funexp = gen_rtx_MEM ( FUNCTION_MODE , funexp ) ; insn = emit_call_insn ( gen_sibcall ( funexp , const0_rtx ) ) ; SIBLING_CALL_P ( insn ) = 1 ; emit_barrier ( ) ; insn = get_insns ( ) ; shorten_branches ( insn ) ; final_start_function ( insn , file , 1 ) ; final ( insn , file , 1 ) ; final_end_function ( ) ; reload_completed = 0 ; epilogue_completed = 0 ; } </s>

Worker for TARGET_ASM_OUTPUT_MI_THUNK . Output the assembler code for a thunk function . THUNK_DECL is the declaration for the thunk function itself , FUNCTION is the decl for the target function . DELTA is an immediate constant offset to be added to THIS . If VCALL_OFFSET is nonzero , the word at address ( * THIS + VCALL_OFFSET ) should be additionally added to THIS .


<s>
void
RISCVDAGToDAGISel
::
Select
(
SDNode
*
Node
)
{
if
(
Node
->
isMachineOpcode
(
)
)
{
LLVM_DEBUG
(
dbgs
(
)
<<
"== "
;
Node
->
dump
(
CurDAG
)
;
dbgs
(
)
<<
"\n"
)
;
Node
->
setNodeId
(
1
)
;
return
;
}
unsigned
Opcode
=
Node
->
getOpcode
(
)
;
MVT
XLenVT
=
Subtarget
->
getXLenVT
(
)
;
SDLoc
DL
(
Node
)
;
EVT
VT
=
Node
->
getValueType
(
0
)
;
switch
(
Opcode
)
{
case
ISD
::
Constant
:
{
auto
ConstNode
=
cast
<
ConstantSDNode
>
(
Node
)
;
if
(
VT
==
XLenVT
&&
ConstNode
->
isNullValue
(
)
)
{
SDValue
New
=
CurDAG
->
getCopyFromReg
(
CurDAG
->
getEntryNode
(
)
,
SDLoc
(
Node
)
,
RISCV
::
X0
,
XLenVT
)
;
ReplaceNode
(
Node
,
New
.
getNode
(
)
)
;
return
;
}
break
;
}
case
ISD
::
FrameIndex
:
{
SDValue
Imm
=
CurDAG
->
getTargetConstant
(
0
,
DL
,
XLenVT
)
;
int
FI
=
cast
<
FrameIndexSDNode
>
(
Node
)
->
getIndex
(
)
;
SDValue
TFI
=
CurDAG
->
getTargetFrameIndex
(
FI
,
VT
)
;
ReplaceNode
(
Node
,
CurDAG
->
getMachineNode
(
RISCV
::
ADDI
,
DL
,
VT
,
TFI
,
Imm
)
)
;
return
;
}
}
SelectCode
(
Node
)
;
}
</s>

Main hook for targets to transform nodes into machine nodes .


<s> std :: pair < unsigned , const TargetRegisterClass * > XCoreTargetLowering :: getRegForInlineAsmConstraint ( const std :: string & Constraint , MVT VT ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { default : break ; case 'r' : return std :: make_pair ( 0U , & XCore :: GRRegsRegClass ) ; } } return TargetLowering :: getRegForInlineAsmConstraint ( Constraint , VT ) ; } </s>

Given a physical register constraint ( e.g .


<s> bool GCNPassConfig :: addPreISel ( ) { AMDGPUPassConfig :: addPreISel ( ) ; if ( EnableAtomicOptimizations ) { addPass ( createAMDGPUAtomicOptimizerPass ( ) ) ; } addPass ( createAMDGPUAnnotateKernelFeaturesPass ( ) ) ; addPass ( & AMDGPUUnifyDivergentExitNodesID ) ; if ( ! LateCFGStructurize ) { addPass ( createStructurizeCFGPass ( true ) ) ; } addPass ( createSinkingPass ( ) ) ; addPass ( createAMDGPUAnnotateUniformValues ( ) ) ; if ( ! LateCFGStructurize ) { addPass ( createSIAnnotateControlFlowPass ( ) ) ; } return false ; } </s>

AMDGPU AMDGPU AMDGPU AMDGPU AMDGPU AMDGPU SI


<s> bool HexagonCopyToCombine :: runOnMachineFunction ( MachineFunction & MF ) { if ( skipFunction ( MF . getFunction ( ) ) ) return false ; if ( IsCombinesDisabled ) return false ; bool HasChanged = false ; ST = & MF . getSubtarget < HexagonSubtarget > ( ) ; TRI = ST -> getRegisterInfo ( ) ; TII = ST -> getInstrInfo ( ) ; const Function & F = MF . getFunction ( ) ; bool OptForSize = F . hasFnAttribute ( Attribute :: OptimizeForSize ) ; ShouldCombineAggressively = MF . getTarget ( ) . getOptLevel ( ) <= CodeGenOpt :: Default ; for ( MachineFunction :: iterator BI = MF . begin ( ) , BE = MF . end ( ) ; BI != BE ; ++ BI ) { PotentiallyNewifiableTFR . clear ( ) ; findPotentialNewifiableTFRs ( * BI ) ; for ( MachineBasicBlock :: iterator MI = BI -> begin ( ) , End = BI -> end ( ) ; MI != End ; ) { MachineInstr & I1 = * MI ++ ; if ( I1 . isDebugInstr ( ) ) continue ; if ( ShouldCombineAggressively && PotentiallyNewifiableTFR . count ( & I1 ) ) continue ; if ( ! isCombinableInstType ( I1 , TII , ShouldCombineAggressively ) ) continue ; bool DoInsertAtI1 = false ; DbgMItoMove . clear ( ) ; MachineInstr * I2 = findPairable ( I1 , DoInsertAtI1 , OptForSize ) ; if ( I2 ) { HasChanged = true ; combine ( I1 , * I2 , MI , DoInsertAtI1 , OptForSize ) ; } } } return HasChanged ; } </s>


Load the specified register of the given register class from the specified stack frame index .


<s> static const struct processor * aarch64_get_tune_cpu ( enum aarch64_processor cpu ) { if ( cpu != aarch64_none ) return & all_cores [ cpu ] ; return & all_cores [ TARGET_CPU_DEFAULT & 0x3f ] ; } </s>

Return the CPU corresponding to the enum CPU . If it does n't specify a cpu , return the default .


<s>
SDValue
PatmosTargetLowering
::
LowerCallResult
(
SDValue
Chain
,
SDValue
InFlag
,
CallingConv
::
ID
CallConv
,
bool
isVarArg
,
const
SmallVectorImpl
<
ISD
::
InputArg
>
&
Ins
,
SDLoc
dl
,
SelectionDAG
&
DAG
,
SmallVectorImpl
<
SDValue
>
&
InVals
)
const
{
SmallVector
<
CCValAssign
,
16
>
RVLocs
;
CCState
CCInfo
(
CallConv
,
isVarArg
,
DAG
.
getMachineFunction
(
)
,
RVLocs
,
*
DAG
.
getContext
(
)
)
;
CCInfo
.
AnalyzeCallResult
(
Ins
,
RetCC_Patmos
)
;
for
(
unsigned
i
=
0
;
i
!=
RVLocs
.
size
(
)
;
++
i
)
{
assert
(
(
RVLocs
[
i
]
.
getLocReg
(
)
==
Patmos
::
R1
||
RVLocs
[
i
]
.
getLocReg
(
)
==
Patmos
::
R2
)
&&
"Invalid return register"
)
;
SDValue
val
=
DAG
.
getCopyFromReg
(
Chain
,
dl
,
RVLocs
[
i
]
.
getLocReg
(
)
,
MVT
::
i32
,
InFlag
)
;
Chain
=
val
.
getValue
(
1
)
;
InFlag
=
val
.
getValue
(
2
)
;
if
(
RVLocs
[
i
]
.
getValVT
(
)
==
MVT
::
i1
)
{
val
=
DAG
.
getZExtOrTrunc
(
val
,
dl
,
RVLocs
[
i
]
.
getValVT
(
)
)
;
}
InVals
.
push_back
(
val
)
;
}
return
Chain
;
}
</s>

LowerCallResult - Lower the result values of an ISD : :CALL into the appropriate copies out of appropriate physical registers .


<s> int ARMAsmParser :: tryParseRegister ( ) { const AsmToken & Tok = Parser . getTok ( ) ; if ( Tok . isNot ( AsmToken :: Identifier ) ) return - 1 ; std :: string lowerCase = Tok . getString ( ) . lower ( ) ; unsigned RegNum = MatchRegisterName ( lowerCase ) ; if ( ! RegNum ) { RegNum = StringSwitch < unsigned > ( lowerCase ) . Case ( "r13" , ARM :: SP ) . Case ( "r14" , ARM :: LR ) . Case ( "r15" , ARM :: PC ) . Case ( "ip" , ARM :: R12 ) . Case ( "a1" , ARM :: R0 ) . Case ( "a2" , ARM :: R1 ) . Case ( "a3" , ARM :: R2 ) . Case ( "a4" , ARM :: R3 ) . Case ( "v1" , ARM :: R4 ) . Case ( "v2" , ARM :: R5 ) . Case ( "v3" , ARM :: R6 ) . Case ( "v4" , ARM :: R7 ) . Case ( "v5" , ARM :: R8 ) . Case ( "v6" , ARM :: R9 ) . Case ( "v7" , ARM :: R10 ) . Case ( "v8" , ARM :: R11 ) . Case ( "sb" , ARM :: R9 ) . Case ( "sl" , ARM :: R10 ) . Case ( "fp" , ARM :: R11 ) . Default ( 0 ) ; } if ( ! RegNum ) { StringMap < unsigned > :: const_iterator Entry = RegisterReqs . find ( lowerCase ) ; if ( Entry == RegisterReqs . end ( ) ) return - 1 ; Parser . Lex ( ) ; return Entry -> getValue ( ) ; } Parser . Lex ( ) ; return RegNum ; } </s>

tryParseRegister - parse one register if possible


<s> bool X86IntelAsmPrinter :: PrintAsmOperand ( const MachineInstr * MI , unsigned OpNo , unsigned AsmVariant , const char * ExtraCode ) { if ( ExtraCode && ExtraCode [ 0 ] ) { if ( ExtraCode [ 1 ] != 0 ) return true ; switch ( ExtraCode [ 0 ] ) { default : return true ; case 'b' : case 'h' : case 'w' : case 'k' : return printAsmMRegister ( MI -> getOperand ( OpNo ) , ExtraCode [ 0 ] ) ; } } printOperand ( MI , OpNo ) ; return false ; } </s>

PrintAsmOperand - Print out an operand for an inline asm expression .


<s> const PatmosInstrInfo * getInstrInfo ( ) const { return Subtarget . getInstrInfo ( ) ; } </s>


<s> void VEMCCodeEmitter :: encodeInstruction ( const MCInst & MI , raw_ostream & OS , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { verifyInstructionPredicates ( MI , computeAvailableFeatures ( STI . getFeatureBits ( ) ) ) ; uint64_t Bits = getBinaryCodeForInstr ( MI , Fixups , STI ) ; support :: endian :: write < uint64_t > ( OS , Bits , support :: little ) ; ++ MCNumEmitted ; } </s>

Encode the given Inst to bytes and append to CB .


<s> bool writeNopData ( uint64_t Count , MCObjectWriter * OW ) const override { if ( Count % 4 != 0 ) return false ; uint64_t NumNops = Count / 4 ; for ( uint64_t i = 0 ; i != NumNops ; ++ i ) OW -> Write32 ( 0x01000000 ) ; return true ; } </s>


<s> MCFragment * findAssociatedFragment ( ) const override { return getSubExpr ( ) -> findAssociatedFragment ( ) ; } </s>

Find the `` associated section '' for this expression , which is currently defined as the absolute section for constants , or otherwise the section associated with the first defined symbol in the expression .


<s>
void
TPCSchedStrategy
::
initialize
(
ScheduleDAGMI
*
dag
)
{
LLVM_DEBUG
(
dbgs
(
)
<<
"TPCSchedStrategy :: initialize\n"
)
;
DAG
=
static_cast
<
TPCMachineScheduler
*
>
(
dag
)
;
SchedModel
=
DAG
->
getSchedModel
(
)
;
Top
.
init
(
DAG
,
SchedModel
)
;
Bot
.
init
(
DAG
,
SchedModel
)
;
const
InstrItineraryData
*
Itin
=
DAG
->
getSchedModel
(
)
->
getInstrItineraries
(
)
;
const
TargetSubtargetInfo
&
STI
=
DAG
->
MF
.
getSubtarget
(
)
;
const
TargetInstrInfo
*
TII
=
STI
.
getInstrInfo
(
)
;
if
(
!
TPCUseFullSched
)
{
llvm
::
ForceTopDown
=
true
;
}
delete
Top
.
HazardRec
;
delete
Bot
.
HazardRec
;
Top
.
HazardRec
=
TII
->
CreateTargetMIHazardRecognizer
(
Itin
,
DAG
)
;
Bot
.
HazardRec
=
TII
->
CreateTargetMIHazardRecognizer
(
Itin
,
DAG
)
;
delete
Top
.
ResourceModel
;
delete
Bot
.
ResourceModel
;
Top
.
ResourceModel
=
new
TPCResourceModel
(
STI
,
DAG
->
getSchedModel
(
)
)
;
Bot
.
ResourceModel
=
new
TPCResourceModel
(
STI
,
DAG
->
getSchedModel
(
)
)
;
if
(
!
isPostRA
)
{
const
std
::
vector
<
unsigned
>
&
MaxPressure
=
DAG
->
getRegPressure
(
)
.
MaxSetPressure
;
HighPressureSets
.
assign
(
MaxPressure
.
size
(
)
,
0
)
;
for
(
unsigned
i
=
0
,
e
=
MaxPressure
.
size
(
)
;
i
<
e
;
++
i
)
{
unsigned
Limit
=
DAG
->
getRegClassInfo
(
)
->
getRegPressureSetLimit
(
i
)
;
HighPressureSets
[
i
]
=
(
(
float
)
MaxPressure
[
i
]
>
(
(
float
)
Limit
*
RPThreshold
)
)
;
}
liveInsADRF
=
0
;
const
llvm
::
MachineFunction
&
MF
=
DAG
->
MF
;
const
TargetRegisterInfo
&
TRI
=
*
MF
.
getSubtarget
(
)
.
getRegisterInfo
(
)
;
for
(
const
auto
&
RegMaskPair
:
DAG
->
getTopRPTracker
(
)
.
getPressure
(
)
.
LiveInRegs
)
{
Register
Reg
=
RegMaskPair
.
RegUnit
;
if
(
Reg
.
isPhysical
(
)
)
continue
;
const
TargetRegisterClass
*
rClass
=
MF
.
getRegInfo
(
)
.
getRegClass
(
Reg
)
;
if
(
rClass
==
&
TPC
::
ADRFRegClass
)
{
liveInsADRF
++
;
}
}
}
}
</s>

Initialize the strategy after building the DAG for a new region .

TPC
TPC
"TPCSchedStrategy :: initialize\n"
TPC
TPC
TPC
TPC
0
0
0
TPC::ADRFRegClass


<s> void MipsFrameLowering :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { unsigned SP = STI . getABI ( ) . IsN64 ( ) ? Mips :: SP_64 : Mips :: SP ; if ( ! hasReservedCallFrame ( MF ) ) { int64_t Amount = I -> getOperand ( 0 ) . getImm ( ) ; if ( I -> getOpcode ( ) == Mips :: ADJCALLSTACKDOWN ) Amount = - Amount ; STI . getInstrInfo ( ) -> adjustStackPtr ( SP , Amount , MBB , I ) ; } MBB . erase ( I ) ; } </s>

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .

Mips Mips Mips::SP_64 Mips::SP 0 Mips::ADJCALLSTACKDOWN


<s> bool X86FastISel :: tryToFoldLoadIntoMI ( MachineInstr * MI , unsigned OpNo , const LoadInst * LI ) { const Value * Ptr = LI -> getPointerOperand ( ) ; X86AddressMode AM ; if ( ! X86SelectAddress ( Ptr , AM ) ) return false ; const X86InstrInfo & XII = ( const X86InstrInfo & ) TII ; unsigned Size = DL . getTypeAllocSize ( LI -> getType ( ) ) ; SmallVector < MachineOperand , 8 > AddrOps ; AM . getFullAddress ( AddrOps ) ; MachineInstr * Result = XII . foldMemoryOperandImpl ( * FuncInfo . MF , * MI , OpNo , AddrOps , FuncInfo . InsertPt , Size , LI -> getAlign ( ) , true ) ; if ( ! Result ) return false ; unsigned OperandNo = 0 ; for ( MachineInstr :: mop_iterator I = Result -> operands_begin ( ) , E = Result -> operands_end ( ) ; I != E ; ++ I , ++ OperandNo ) { MachineOperand & MO = * I ; if ( ! MO . isReg ( ) || MO . isDef ( ) || MO . getReg ( ) != AM . IndexReg ) continue ; Register IndexReg = constrainOperandRegClass ( Result -> getDesc ( ) , MO . getReg ( ) , OperandNo ) ; if ( IndexReg == MO . getReg ( ) ) continue ; MO . setReg ( IndexReg ) ; } Result -> addMemOperand ( * FuncInfo . MF , createMachineMemOperandFor ( LI ) ) ; Result -> cloneInstrSymbols ( * FuncInfo . MF , * MI ) ; MachineBasicBlock :: iterator I ( MI ) ; removeDeadCode ( I , std :: next ( I ) ) ; return true ; } </s>

The specified machine instr operand is a vreg , and that vreg is being provided by the specified load instruction .


<s> TargetPassConfig * TeeRISCTargetMachine :: createPassConfig ( PassManagerBase & PM ) { return new TeeRISCPassConfig ( this , PM ) ; } </s>

Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of CodeGen passes .


<s> bool MSP430RegisterInfo :: hasFP ( const MachineFunction & MF ) const { const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; return ( DisableFramePointerElim ( MF ) || MF . getFrameInfo ( ) -> hasVarSizedObjects ( ) || MFI -> isFrameAddressTaken ( ) ) ; } </s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .


<s> unsigned ARMFastISel :: fastEmitInst_rr ( unsigned MachineInstOpcode , const TargetRegisterClass * RC , unsigned Op0 , unsigned Op1 ) { Register ResultReg = createResultReg ( RC ) ; const MCInstrDesc & II = TII . get ( MachineInstOpcode ) ; Op0 = constrainOperandRegClass ( II , Op0 , 1 ) ; Op1 = constrainOperandRegClass ( II , Op1 , 2 ) ; if ( II . getNumDefs ( ) >= 1 ) { AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , II , ResultReg ) . addReg ( Op0 ) . addReg ( Op1 ) ) ; } else { AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , II ) . addReg ( Op0 ) . addReg ( Op1 ) ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: COPY ) , ResultReg ) . addReg ( II . ImplicitDefs [ 0 ] ) ) ; } return ResultReg ; } </s>

Emit a MachineInstr with two register operands and a result register in the given register class .


<s> bool AArch64AsmParser :: ParseDirective ( AsmToken DirectiveID ) { const MCObjectFileInfo :: Environment Format = getContext ( ) . getObjectFileInfo ( ) -> getObjectFileType ( ) ; bool IsMachO = Format == MCObjectFileInfo :: IsMachO ; bool IsCOFF = Format == MCObjectFileInfo :: IsCOFF ; StringRef IDVal = DirectiveID . getIdentifier ( ) ; SMLoc Loc = DirectiveID . getLoc ( ) ; if ( IDVal == ".arch" ) parseDirectiveArch ( Loc ) ; else if ( IDVal == ".cpu" ) parseDirectiveCPU ( Loc ) ; else if ( IDVal == ".hword" ) parseDirectiveWord ( 2 , Loc ) ; else if ( IDVal == ".word" ) parseDirectiveWord ( 4 , Loc ) ; else if ( IDVal == ".xword" ) parseDirectiveWord ( 8 , Loc ) ; else if ( IDVal == ".tlsdesccall" ) parseDirectiveTLSDescCall ( Loc ) ; else if ( IDVal == ".ltorg" || IDVal == ".pool" ) parseDirectiveLtorg ( Loc ) ; else if ( IDVal == ".unreq" ) parseDirectiveUnreq ( Loc ) ; else if ( ! IsMachO && ! IsCOFF ) { if ( IDVal == ".inst" ) parseDirectiveInst ( Loc ) ; else return true ; } else if ( IDVal == MCLOHDirectiveName ( ) ) parseDirectiveLOH ( IDVal , Loc ) ; else return true ; return false ; } </s>

ParseDirective - Parse a target specific assembler directive This method is deprecated , use 'parseDirective ' instead .


<s> bool HexagonDAGToDAGISel :: SelectInlineAsmMemoryOperand ( const SDValue & Op , unsigned ConstraintID , std :: vector < SDValue > & OutOps ) { SDValue Inp = Op , Res ; switch ( ConstraintID ) { default : return true ; case InlineAsm :: Constraint_i : case InlineAsm :: Constraint_o : case InlineAsm :: Constraint_v : case InlineAsm :: Constraint_m : if ( SelectAddrFI ( Inp , Res ) ) OutOps . push_back ( Res ) ; else OutOps . push_back ( Inp ) ; break ; } OutOps . push_back ( CurDAG -> getTargetConstant ( 0 , MVT :: i32 ) ) ; return false ; } </s>

SelectInlineAsmMemoryOperand - Select the specified address as a target addressing mode , according to the specified constraint .


<s>
void
HexagonInstPrinter
::
printInst
(
const
MCInst
*
MI
,
raw_ostream
&
OS
,
StringRef
Annot
,
const
MCSubtargetInfo
&
STI
)
{
assert
(
HexagonMCInstrInfo
::
isBundle
(
*
MI
)
)
;
assert
(
HexagonMCInstrInfo
::
bundleSize
(
*
MI
)
<=
HEXAGON_PACKET_SIZE
)
;
assert
(
HexagonMCInstrInfo
::
bundleSize
(
*
MI
)
>
0
)
;
HasExtender
=
false
;
for
(
auto
const
&
I
:
HexagonMCInstrInfo
::
bundleInstructions
(
*
MI
)
)
{
MCInst
const
&
MCI
=
*
I
.
getInst
(
)
;
if
(
HexagonMCInstrInfo
::
isDuplex
(
MII
,
MCI
)
)
{
printInstruction
(
MCI
.
getOperand
(
1
)
.
getInst
(
)
,
OS
)
;
OS
<<
'\v'
;
HasExtender
=
false
;
printInstruction
(
MCI
.
getOperand
(
0
)
.
getInst
(
)
,
OS
)
;
}
else
printInstruction
(
&
MCI
,
OS
)
;
HasExtender
=
HexagonMCInstrInfo
::
isImmext
(
MCI
)
;
OS
<<
"\n"
;
}
bool
IsLoop0
=
HexagonMCInstrInfo
::
isInnerLoop
(
*
MI
)
;
bool
IsLoop1
=
HexagonMCInstrInfo
::
isOuterLoop
(
*
MI
)
;
if
(
IsLoop0
)
{
OS
<<
(
IsLoop1
" :endloop01"
:
" :endloop0"
)
;
}
else
if
(
IsLoop1
)
{
OS
<<
" :endloop1"
;
}
}
</s>

Print the specified MCInst to the specified raw_ostream .

Hexagon
Hexagon
Hexagon
Hexagon
Hexagon
0
Hexagon
Hexagon
1
0
Hexagon
"\n"
Hexagon
Hexagon
" :endloop01"
" :endloop0"
" :endloop1"


<s> static bool compare_eq_p ( rtx_insn * insn ) { RTX_CODE cond = compare_condition ( insn ) ; return ( cond == EQ || cond == NE ) ; } </s>

Returns nonzero if INSN is a compare insn with the EQ or NE condition .


<s> bool ARM64PassConfig :: addPreISel ( ) { if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnablePromoteConstant ) addPass ( createARM64PromoteConstantPass ( ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None ) addPass ( createGlobalMergePass ( TM ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None ) addPass ( createARM64AddressTypePromotionPass ( ) ) ; addPass ( createAtomicExpandLoadLinkedPass ( TM ) ) ; return false ; } </s>


"Unable to create a unique discriminator "

"for instruction with memory operand in: "

". This is likely due to a large macro expansion. \n"

"New discriminator shouldn't be present in set"

runOnMachineFunction - Emit the function body .


<s> void MipsAsmPrinter :: EmitInstruction ( const MachineInstr * MI ) { if ( MI -> isDebugValue ( ) ) { SmallString < 128 > Str ; raw_svector_ostream OS ( Str ) ; PrintDebugValueComment ( MI , OS ) ; return ; } MipsMCInstLower MCInstLowering ( Mang , * MF , * this ) ; unsigned Opc = MI -> getOpcode ( ) ; MCInst TmpInst0 ; SmallVector < MCInst , 4 > MCInsts ; MCInstLowering . Lower ( MI , TmpInst0 ) ; if ( ! OutStreamer . hasRawTextSupport ( ) && isDirective ( Opc ) ) return ; if ( isUnalignedLoadStore ( Opc ) ) { if ( OutStreamer . hasRawTextSupport ( ) ) { MCInst Directive ; Directive . setOpcode ( Mips :: MACRO ) ; OutStreamer . EmitInstruction ( Directive ) ; OutStreamer . EmitInstruction ( TmpInst0 ) ; Directive . setOpcode ( Mips :: NOMACRO ) ; OutStreamer . EmitInstruction ( Directive ) ; } else { MCInstLowering . LowerUnalignedLoadStore ( MI , MCInsts ) ; for ( SmallVector < MCInst , 4 > :: iterator I = MCInsts . begin ( ) ; I != MCInsts . end ( ) ; ++ I ) OutStreamer . EmitInstruction ( * I ) ; } return ; } if ( ! OutStreamer . hasRawTextSupport ( ) ) { if ( Opc == Mips :: CPLOAD ) MCInstLowering . LowerCPLOAD ( MI , MCInsts ) ; else if ( Opc == Mips :: CPRESTORE ) MCInstLowering . LowerCPRESTORE ( MI , MCInsts ) ; if ( ! MCInsts . empty ( ) ) { for ( SmallVector < MCInst , 4 > :: iterator I = MCInsts . begin ( ) ; I != MCInsts . end ( ) ; ++ I ) OutStreamer . EmitInstruction ( * I ) ; return ; } } if ( Opc == Mips :: SETGP01 ) { MCInstLowering . LowerSETGP01 ( MI , MCInsts ) ; for ( SmallVector < MCInst , 4 > :: iterator I = MCInsts . begin ( ) ; I != MCInsts . end ( ) ; ++ I ) OutStreamer . EmitInstruction ( * I ) ; return ; } OutStreamer . EmitInstruction ( TmpInst0 ) ; } </s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s> void Mips16FrameLowering :: emitPrologue ( MachineFunction & MF ) const { MachineBasicBlock & MBB = MF . front ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const Mips16InstrInfo & TII = * static_cast < const Mips16InstrInfo * > ( MF . getTarget ( ) . getInstrInfo ( ) ) ; MachineBasicBlock :: iterator MBBI = MBB . begin ( ) ; DebugLoc dl = MBBI != MBB . end ( ) ? MBBI -> getDebugLoc ( ) : DebugLoc ( ) ; uint64_t StackSize = MFI -> getStackSize ( ) ; if ( StackSize == 0 && ! MFI -> adjustsStack ( ) ) return ; MachineModuleInfo & MMI = MF . getMMI ( ) ; std :: vector < MachineMove > & Moves = MMI . getFrameMoves ( ) ; MachineLocation DstML , SrcML ; TII . makeFrame ( Mips :: SP , StackSize , MBB , MBBI ) ; MCSymbol * AdjustSPLabel = MMI . getContext ( ) . CreateTempSymbol ( ) ; BuildMI ( MBB , MBBI , dl , TII . get ( TargetOpcode :: PROLOG_LABEL ) ) . addSym ( AdjustSPLabel ) ; DstML = MachineLocation ( MachineLocation :: VirtualFP ) ; SrcML = MachineLocation ( MachineLocation :: VirtualFP , - StackSize ) ; Moves . push_back ( MachineMove ( AdjustSPLabel , DstML , SrcML ) ) ; MCSymbol * CSLabel = MMI . getContext ( ) . CreateTempSymbol ( ) ; BuildMI ( MBB , MBBI , dl , TII . get ( TargetOpcode :: PROLOG_LABEL ) ) . addSym ( CSLabel ) ; DstML = MachineLocation ( MachineLocation :: VirtualFP , - 8 ) ; SrcML = MachineLocation ( Mips :: S1 ) ; Moves . push_back ( MachineMove ( CSLabel , DstML , SrcML ) ) ; DstML = MachineLocation ( MachineLocation :: VirtualFP , - 12 ) ; SrcML = MachineLocation ( Mips :: S0 ) ; Moves . push_back ( MachineMove ( CSLabel , DstML , SrcML ) ) ; DstML = MachineLocation ( MachineLocation :: VirtualFP , - 4 ) ; SrcML = MachineLocation ( Mips :: RA ) ; Moves . push_back ( MachineMove ( CSLabel , DstML , SrcML ) ) ; if ( hasFP ( MF ) ) BuildMI ( MBB , MBBI , dl , TII . get ( Mips :: MoveR3216 ) , Mips :: S0 ) . addReg ( Mips :: SP ) ; } </s>

emitProlog/emitEpilog - These methods insert prolog and epilog code into the function .


"Missing call preserved mask for calling convention"

This function fills Ops , which is the list of operands that will later be used when a function call node is created .


"WDC_TODO - Need to implement hasStructRetAttr() case"

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> MCObjectWriter * createObjectWriter ( raw_ostream & OS ) const override { uint8_t OSABI = MCELFObjectTargetWriter :: getOSABI ( OSType ) ; return createSparcELFObjectWriter ( OS , is64Bit ( ) , OSABI ) ; } </s>

Create a new MCObjectWriter instance for use by the assembler backend to emit the final object file .


<s> virtual const TargetFrameInfo * getFrameInfo ( ) const { return & FrameInfo ; } </s>

getFrameInfo - Return the frame info object for the current function .


<s> const GBZ80RegisterInfo & getRegisterInfo ( ) const { return RI ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s> bool ARMTargetLowering :: shouldSinkOperands ( Instruction * I , SmallVectorImpl < Use * > & Ops ) const { if ( ! I -> getType ( ) -> isVectorTy ( ) ) return false ; if ( Subtarget -> hasNEON ( ) ) { switch ( I -> getOpcode ( ) ) { case Instruction :: Sub : case Instruction :: Add : { if ( ! areExtractExts ( I -> getOperand ( 0 ) , I -> getOperand ( 1 ) ) ) return false ; Ops . push_back ( & I -> getOperandUse ( 0 ) ) ; Ops . push_back ( & I -> getOperandUse ( 1 ) ) ; return true ; } default : return false ; } } if ( ! Subtarget -> hasMVEIntegerOps ( ) ) return false ; auto IsFMSMul = [ & ] ( Instruction * I ) { if ( ! I -> hasOneUse ( ) ) return false ; auto * Sub = cast < Instruction > ( * I -> users ( ) . begin ( ) ) ; return Sub -> getOpcode ( ) == Instruction :: FSub && Sub -> getOperand ( 1 ) == I ; } ; auto IsSinker = [ & ] ( Instruction * I , int Operand ) { switch ( I -> getOpcode ( ) ) { case Instruction :: Add : case Instruction :: Mul : case Instruction :: FAdd : case Instruction :: ICmp : case Instruction :: FCmp : return true ; case Instruction :: FMul : return ! IsFMSMul ( I ) ; case Instruction :: Sub : case Instruction :: FSub : case Instruction :: Shl : case Instruction :: LShr : case Instruction :: AShr : return Operand == 1 ; default : return false ; } } ; int Op = 0 ; if ( ! isa < ShuffleVectorInst > ( I -> getOperand ( Op ) ) ) Op = 1 ; if ( ! IsSinker ( I , Op ) ) return false ; if ( ! match ( I -> getOperand ( Op ) , m_ShuffleVector ( m_InsertElement ( m_Undef ( ) , m_Value ( ) , m_ZeroInt ( ) ) , m_Undef ( ) , m_ZeroMask ( ) ) ) ) { return false ; } Instruction * Shuffle = cast < Instruction > ( I -> getOperand ( Op ) ) ; for ( Use & U : Shuffle -> uses ( ) ) { Instruction * Insn = cast < Instruction > ( U . getUser ( ) ) ; if ( ! IsSinker ( Insn , U . getOperandNo ( ) ) ) return false ; } Ops . push_back ( & Shuffle -> getOperandUse ( 0 ) ) ; Ops . push_back ( & I -> getOperandUse ( Op ) ) ; return true ; } </s>

Return true if sinking I 's operands to the same basic block as I is profitable , e.g .


<s> static tree ix86_vectorize_builtin_gather ( const_tree mem_vectype , const_tree index_type , int scale ) { bool si ; enum ix86_builtins code ; if ( ! TARGET_AVX2 ) return NULL_TREE ; if ( ( TREE_CODE ( index_type ) != INTEGER_TYPE && ! POINTER_TYPE_P ( index_type ) ) || ( TYPE_MODE ( index_type ) != SImode && TYPE_MODE ( index_type ) != DImode ) ) return NULL_TREE ; if ( TYPE_PRECISION ( index_type ) > POINTER_SIZE ) return NULL_TREE ; if ( TYPE_PRECISION ( index_type ) < POINTER_SIZE && TYPE_UNSIGNED ( index_type ) ) return NULL_TREE ; if ( scale <= 0 || scale > 8 || ( scale & ( scale - 1 ) ) != 0 ) return NULL_TREE ; si = TYPE_MODE ( index_type ) == SImode ; switch ( TYPE_MODE ( mem_vectype ) ) { case V2DFmode : if ( TARGET_AVX512VL ) code = si ? IX86_BUILTIN_GATHER3SIV2DF : IX86_BUILTIN_GATHER3DIV2DF ; else code = si ? IX86_BUILTIN_GATHERSIV2DF : IX86_BUILTIN_GATHERDIV2DF ; break ; case V4DFmode : if ( TARGET_AVX512VL ) code = si ? IX86_BUILTIN_GATHER3ALTSIV4DF : IX86_BUILTIN_GATHER3DIV4DF ; else code = si ? IX86_BUILTIN_GATHERALTSIV4DF : IX86_BUILTIN_GATHERDIV4DF ; break ; case V2DImode : if ( TARGET_AVX512VL ) code = si ? IX86_BUILTIN_GATHER3SIV2DI : IX86_BUILTIN_GATHER3DIV2DI ; else code = si ? IX86_BUILTIN_GATHERSIV2DI : IX86_BUILTIN_GATHERDIV2DI ; break ; case V4DImode : if ( TARGET_AVX512VL ) code = si ? IX86_BUILTIN_GATHER3ALTSIV4DI : IX86_BUILTIN_GATHER3DIV4DI ; else code = si ? IX86_BUILTIN_GATHERALTSIV4DI : IX86_BUILTIN_GATHERDIV4DI ; break ; case V4SFmode : if ( TARGET_AVX512VL ) code = si ? IX86_BUILTIN_GATHER3SIV4SF : IX86_BUILTIN_GATHER3DIV4SF ; else code = si ? IX86_BUILTIN_GATHERSIV4SF : IX86_BUILTIN_GATHERDIV4SF ; break ; case V8SFmode : if ( TARGET_AVX512VL ) code = si ? IX86_BUILTIN_GATHER3SIV8SF : IX86_BUILTIN_GATHER3ALTDIV8SF ; else code = si ? IX86_BUILTIN_GATHERSIV8SF : IX86_BUILTIN_GATHERALTDIV8SF ; break ; case V4SImode : if ( TARGET_AVX512VL ) code = si ? IX86_BUILTIN_GATHER3SIV4SI : IX86_BUILTIN_GATHER3DIV4SI ; else code = si ? IX86_BUILTIN_GATHERSIV4SI : IX86_BUILTIN_GATHERDIV4SI ; break ; case V8SImode : if ( TARGET_AVX512VL ) code = si ? IX86_BUILTIN_GATHER3SIV8SI : IX86_BUILTIN_GATHER3ALTDIV8SI ; else code = si ? IX86_BUILTIN_GATHERSIV8SI : IX86_BUILTIN_GATHERALTDIV8SI ; break ; case V8DFmode : if ( TARGET_AVX512F ) code = si ? IX86_BUILTIN_GATHER3ALTSIV8DF : IX86_BUILTIN_GATHER3DIV8DF ; else return NULL_TREE ; break ; case V8DImode : if ( TARGET_AVX512F ) code = si ? IX86_BUILTIN_GATHER3ALTSIV8DI : IX86_BUILTIN_GATHER3DIV8DI ; else return NULL_TREE ; break ; case V16SFmode : if ( TARGET_AVX512F ) code = si ? IX86_BUILTIN_GATHER3SIV16SF : IX86_BUILTIN_GATHER3ALTDIV16SF ; else return NULL_TREE ; break ; case V16SImode : if ( TARGET_AVX512F ) code = si ? IX86_BUILTIN_GATHER3SIV16SI : IX86_BUILTIN_GATHER3ALTDIV16SI ; else return NULL_TREE ; break ; default : return NULL_TREE ; } return ix86_get_builtin ( code ) ; } </s>

Returns a decl of a function that implements gather load with memory type MEM_VECTYPE and index type INDEX_VECTYPE and SCALE . Return NULL_TREE if it is not available .


<s> static bool arm_bfi_p ( rtx x , rtx * sub0 , rtx * sub1 ) { if ( GET_CODE ( x ) != IOR ) return false ; if ( GET_CODE ( XEXP ( x , 0 ) ) != AND || GET_CODE ( XEXP ( x , 1 ) ) != AND ) return false ; return ( arm_bfi_1_p ( XEXP ( x , 0 ) , XEXP ( x , 1 ) , sub0 , sub1 ) || arm_bfi_1_p ( XEXP ( x , 1 ) , XEXP ( x , 0 ) , sub1 , sub0 ) ) ; } </s>

Recognize a BFI idiom . Helper for arm_rtx_costs_internal . The format looks something like : ( IOR ( AND ( reg1 ) ( ~const1 ) ) ( AND ( ASHIFT ( reg2 ) ( const2 ) ) ( const1 ) ) ) where const1 is a consecutive sequence of 1-bits with the least-significant non-zero bit starting at bit position const2 . If const2 is zero , then the shift will not appear at all , due to canonicalization . The two arms of the IOR expression may be flipped .


<s> void mmix_make_decl_one_only ( tree decl ) { DECL_WEAK ( decl ) = 1 ; } </s>


<s> void x86_emit_floatuns ( rtx operands [ 2 ] ) { rtx neglab , donelab , i0 , i1 , f0 , in , out ; enum machine_mode mode , inmode ; inmode = GET_MODE ( operands [ 1 ] ) ; gcc_assert ( inmode == SImode || inmode == DImode ) ; out = operands [ 0 ] ; in = force_reg ( inmode , operands [ 1 ] ) ; mode = GET_MODE ( out ) ; neglab = gen_label_rtx ( ) ; donelab = gen_label_rtx ( ) ; i1 = gen_reg_rtx ( Pmode ) ; f0 = gen_reg_rtx ( mode ) ; emit_cmp_and_jump_insns ( in , const0_rtx , LT , const0_rtx , Pmode , 0 , neglab ) ; emit_insn ( gen_rtx_SET ( VOIDmode , out , gen_rtx_FLOAT ( mode , in ) ) ) ; emit_jump_insn ( gen_jump ( donelab ) ) ; emit_barrier ( ) ; emit_label ( neglab ) ; i0 = expand_simple_binop ( Pmode , LSHIFTRT , in , const1_rtx , NULL , 1 , OPTAB_DIRECT ) ; i1 = expand_simple_binop ( Pmode , AND , in , const1_rtx , NULL , 1 , OPTAB_DIRECT ) ; i0 = expand_simple_binop ( Pmode , IOR , i0 , i1 , i0 , 1 , OPTAB_DIRECT ) ; expand_float ( f0 , i0 , 0 ) ; emit_insn ( gen_rtx_SET ( VOIDmode , out , gen_rtx_PLUS ( mode , f0 , f0 ) ) ) ; emit_label ( donelab ) ; } </s>

Generate an unsigned DImode/SImode to FP conversion . This is the same code optabs would emit if we did n't have TFmode patterns .


<s> void TL45AsmBackend :: relaxInstruction ( const MCInst & Inst , const MCSubtargetInfo & STI , MCInst & Res ) const { } </s>

Relax the instruction in the given fragment to the next wider instruction .


<s> static void mep_insn_dependent_p_1 ( rtx x , const_rtx pat ATTRIBUTE_UNUSED , void * data ) { rtx * pinsn = ( rtx * ) data ; if ( * pinsn && reg_mentioned_p ( x , * pinsn ) ) * pinsn = NULL_RTX ; } </s>

A helper routine for ms1_insn_dependent_p called through note_stores .


"getBranchTarget21OpValueMM expects only expressions or immediates"

getBranchTarget21OpValueMM - Return binary encoding of the branch target operand for microMIPS .


<s> virtual gimple * fold ( gimple_folder & ) const { return NULL ; } </s>

Try to fold the call . Return the new statement on success and null on failure .


"frame pointer should not have been eliminated"

"SecondSPAdjustAmount should be greater than zero"


<s> void addExpr ( MCInst & Inst , const MCExpr * Expr ) const { if ( Expr == 0 ) Inst . addOperand ( MCOperand :: CreateImm ( 0 ) ) ; else if ( const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( Expr ) ) Inst . addOperand ( MCOperand :: CreateImm ( CE -> getValue ( ) ) ) ; else Inst . addOperand ( MCOperand :: CreateExpr ( Expr ) ) ; } </s>


<s> static bool cortexa7_older_only ( rtx_insn * insn ) { if ( recog_memoized ( insn ) < 0 ) return false ; switch ( get_attr_type ( insn ) ) { case TYPE_ALU_DSP_REG : case TYPE_ALU_SREG : case TYPE_ALUS_SREG : case TYPE_LOGIC_REG : case TYPE_LOGICS_REG : case TYPE_ADC_REG : case TYPE_ADCS_REG : case TYPE_ADR : case TYPE_BFM : case TYPE_REV : case TYPE_MVN_REG : case TYPE_SHIFT_IMM : case TYPE_SHIFT_REG : case TYPE_LOAD_BYTE : case TYPE_LOAD_4 : case TYPE_STORE_4 : case TYPE_FFARITHS : case TYPE_FADDS : case TYPE_FFARITHD : case TYPE_FADDD : case TYPE_FMOV : case TYPE_F_CVT : case TYPE_FCMPS : case TYPE_FCMPD : case TYPE_FCONSTS : case TYPE_FCONSTD : case TYPE_FMULS : case TYPE_FMACS : case TYPE_FMULD : case TYPE_FMACD : case TYPE_FDIVS : case TYPE_FDIVD : case TYPE_F_MRC : case TYPE_F_MRRC : case TYPE_F_FLAG : case TYPE_F_LOADS : case TYPE_F_STORES : return true ; default : return false ; } } </s>

Return true if and only if this insn can dual-issue only as older .


<s> static const unsigned * lookup ( unsigned opcode , unsigned domain ) { for ( unsigned i = 0 , e = array_lengthof ( ReplaceableInstrs ) ; i != e ; ++ i ) if ( ReplaceableInstrs [ i ] [ domain - 1 ] == opcode ) return ReplaceableInstrs [ i ] ; return 0 ; } </s>

This method finds the value with the given Name in the the symbol table .


<s> static rtx riscv_legitimize_address ( rtx x , rtx oldx ATTRIBUTE_UNUSED , machine_mode mode ) { rtx addr ; if ( riscv_tls_symbol_p ( x ) ) return riscv_legitimize_tls_address ( x ) ; if ( riscv_split_symbol ( NULL , x , mode , & addr , FALSE ) ) return riscv_force_address ( addr , mode ) ; if ( GET_CODE ( x ) == PLUS && CONST_INT_P ( XEXP ( x , 1 ) ) && INTVAL ( XEXP ( x , 1 ) ) != 0 ) { rtx base = XEXP ( x , 0 ) ; HOST_WIDE_INT offset = INTVAL ( XEXP ( x , 1 ) ) ; if ( ! riscv_valid_base_register_p ( base , mode , false ) ) base = copy_to_mode_reg ( Pmode , base ) ; if ( optimize_function_for_size_p ( cfun ) && ( strcmp ( current_pass -> name , "shorten_memrefs" ) == 0 ) && mode == SImode ) addr = riscv_shorten_lw_offset ( base , offset ) ; else addr = riscv_add_offset ( NULL , base , offset ) ; return riscv_force_address ( addr , mode ) ; } return x ; } </s>

This function is used to implement LEGITIMIZE_ADDRESS . If X can be legitimized in a way that the generic machinery might not expect , return a new address , otherwise return NULL . MODE is the mode of the memory being accessed .


<s> bool ARMAsmPrinter :: PrintAsmOperand ( const MachineInstr * MI , unsigned OpNum , unsigned AsmVariant , const char * ExtraCode ) { if ( ExtraCode && ExtraCode [ 0 ] ) { if ( ExtraCode [ 1 ] != 0 ) return true ; switch ( ExtraCode [ 0 ] ) { default : return true ; case 'a' : if ( MI -> getOperand ( OpNum ) . isReg ( ) ) { O << "[" << getRegisterName ( MI -> getOperand ( OpNum ) . getReg ( ) ) << "]" ; return false ; } case 'c' : if ( ! MI -> getOperand ( OpNum ) . isImm ( ) ) return true ; printNoHashImmediate ( MI , OpNum ) ; return false ; case 'P' : case 'q' : printOperand ( MI , OpNum ) ; return false ; case 'Q' : if ( TM . getTargetData ( ) -> isLittleEndian ( ) ) break ; case 'R' : if ( TM . getTargetData ( ) -> isBigEndian ( ) ) break ; case 'H' : if ( ! MI -> getOperand ( OpNum ) . isReg ( ) || OpNum + 1 == MI -> getNumOperands ( ) || ! MI -> getOperand ( OpNum + 1 ) . isReg ( ) ) return true ; ++ OpNum ; } } printOperand ( MI , OpNum ) ; return false ; } </s>

PrintAsmOperand - Print out an operand for an inline asm expression .


<s> bool shouldBuildLookupTables ( ) const { return false ; } </s>

Return true if switches should be turned into lookup tables for the target .