<s>
static
bool
sizeless_type_p
(
const_tree
type
)
{
if
(
type
==
error_mark_node
)
return
NULL_TREE
;
return
lookup_attribute
(
"SVE sizeless type"
,
TYPE_ATTRIBUTES
(
type
)
)
;
}
</s>

Return true if TYPE is a sizeless type .


<s>
StringRef
AArch64MCExpr
::
getVariantKindName
(
)
const
{
switch
(
static_cast
<
uint32_t
>
(
getKind
(
)
)
)
{
case
VK_CALL
:
return
""
;
case
VK_LO12
:
return
":lo12:"
;
case
VK_ABS_G3
:
return
":abs_g3:"
;
case
VK_ABS_G2
:
return
":abs_g2:"
;
case
VK_ABS_G2_S
:
return
":abs_g2_s:"
;
case
VK_ABS_G2_NC
:
return
":abs_g2_nc:"
;
case
VK_ABS_G1
:
return
":abs_g1:"
;
case
VK_ABS_G1_S
:
return
":abs_g1_s:"
;
case
VK_ABS_G1_NC
:
return
":abs_g1_nc:"
;
case
VK_ABS_G0
:
return
":abs_g0:"
;
case
VK_ABS_G0_S
:
return
":abs_g0_s:"
;
case
VK_ABS_G0_NC
:
return
":abs_g0_nc:"
;
case
VK_DTPREL_G2
:
return
":dtprel_g2:"
;
case
VK_DTPREL_G1
:
return
":dtprel_g1:"
;
case
VK_DTPREL_G1_NC
:
return
":dtprel_g1_nc:"
;
case
VK_DTPREL_G0
:
return
":dtprel_g0:"
;
case
VK_DTPREL_G0_NC
:
return
":dtprel_g0_nc:"
;
case
VK_DTPREL_HI12
:
return
":dtprel_hi12:"
;
case
VK_DTPREL_LO12
:
return
":dtprel_lo12:"
;
case
VK_DTPREL_LO12_NC
:
return
":dtprel_lo12_nc:"
;
case
VK_TPREL_G2
:
return
":tprel_g2:"
;
case
VK_TPREL_G1
:
return
":tprel_g1:"
;
case
VK_TPREL_G1_NC
:
return
":tprel_g1_nc:"
;
case
VK_TPREL_G0
:
return
":tprel_g0:"
;
case
VK_TPREL_G0_NC
:
return
":tprel_g0_nc:"
;
case
VK_TPREL_HI12
:
return
":tprel_hi12:"
;
case
VK_TPREL_LO12
:
return
":tprel_lo12:"
;
case
VK_TPREL_LO12_NC
:
return
":tprel_lo12_nc:"
;
case
VK_TLSDESC_LO12
:
return
":tlsdesc_lo12:"
;
case
VK_ABS_PAGE
:
return
""
;
case
VK_GOT_PAGE
:
return
":got:"
;
case
VK_GOT_LO12
:
return
":got_lo12:"
;
case
VK_GOTTPREL_PAGE
:
return
":gottprel:"
;
case
VK_GOTTPREL_LO12_NC
:
return
":gottprel_lo12:"
;
case
VK_GOTTPREL_G1
:
return
":gottprel_g1:"
;
case
VK_GOTTPREL_G0_NC
:
return
":gottprel_g0_nc:"
;
case
VK_TLSDESC
:
return
""
;
case
VK_TLSDESC_PAGE
:
return
":tlsdesc:"
;
default
:
llvm_unreachable
(
"Invalid ELF symbol kind"
)
;
}
}
</s>

Convert the variant kind into an ELF-appropriate modifier ( e.g .


<s>
bool
X86InstrInfo
::
classifyLEAReg
(
MachineInstr
&
MI
,
const
MachineOperand
&
Src
,
unsigned
Opc
,
bool
AllowSP
,
Register
&
NewSrc
,
bool
&
isKill
,
MachineOperand
&
ImplicitOp
,
LiveVariables
*
LV
)
const
{
MachineFunction
&
MF
=
*
MI
.
getParent
(
)
->
getParent
(
)
;
const
TargetRegisterClass
*
RC
;
if
(
AllowSP
)
{
RC
=
Opc
!=
X86
::
LEA32r
&
X86
::
GR64RegClass
:
&
X86
::
GR32RegClass
;
}
else
{
RC
=
Opc
!=
X86
::
LEA32r
&
X86
::
GR64_NOSPRegClass
:
&
X86
::
GR32_NOSPRegClass
;
}
Register
SrcReg
=
Src
.
getReg
(
)
;
if
(
Opc
!=
X86
::
LEA64_32r
)
{
NewSrc
=
SrcReg
;
isKill
=
Src
.
isKill
(
)
;
assert
(
!
Src
.
isUndef
(
)
&&
"Undef op doesn't need optimization"
)
;
if
(
NewSrc
.
isVirtual
(
)
&&
!
MF
.
getRegInfo
(
)
.
constrainRegClass
(
NewSrc
,
RC
)
)
return
false
;
return
true
;
}
if
(
SrcReg
.
isPhysical
(
)
)
{
ImplicitOp
=
Src
;
ImplicitOp
.
setImplicit
(
)
;
NewSrc
=
getX86SubSuperRegister
(
Src
.
getReg
(
)
,
64
)
;
isKill
=
Src
.
isKill
(
)
;
assert
(
!
Src
.
isUndef
(
)
&&
"Undef op doesn't need optimization"
)
;
}
else
{
NewSrc
=
MF
.
getRegInfo
(
)
.
createVirtualRegister
(
RC
)
;
MachineInstr
*
Copy
=
BuildMI
(
*
MI
.
getParent
(
)
,
MI
,
MI
.
getDebugLoc
(
)
,
get
(
TargetOpcode
::
COPY
)
)
.
addReg
(
NewSrc
,
RegState
::
Define
|
RegState
::
Undef
,
X86
::
sub_32bit
)
.
add
(
Src
)
;
isKill
=
true
;
if
(
LV
)
LV
->
replaceKillInstruction
(
SrcReg
,
MI
,
*
Copy
)
;
}
return
true
;
}
</s>

Given an operand within a MachineInstr , insert preceding code to put it into the right format for a particular kind of LEA instruction .


<s> enum reg_class mips_secondary_reload_class ( enum reg_class class , enum machine_mode mode , rtx x , int in_p ) { enum reg_class gr_regs = TARGET_MIPS16 ? M16_REGS : GR_REGS ; int regno = - 1 ; int gp_reg_p ; if ( REG_P ( x ) || GET_CODE ( x ) == SUBREG ) regno = true_regnum ( x ) ; gp_reg_p = TARGET_MIPS16 ? M16_REG_P ( regno ) : GP_REG_P ( regno ) ; if ( mips_dangerous_for_la25_p ( x ) ) { gr_regs = LEA_REGS ; if ( TEST_HARD_REG_BIT ( reg_class_contents [ ( int ) class ] , 25 ) ) return gr_regs ; } if ( reg_class_subset_p ( class , ACC_REGS ) ) { if ( TARGET_MIPS16 && in_p ) { return M16_REGS ; } return gp_reg_p ? NO_REGS : gr_regs ; } if ( ACC_REG_P ( regno ) ) { if ( TARGET_MIPS16 && ! in_p ) { return M16_REGS ; } return class == gr_regs ? NO_REGS : gr_regs ; } if ( class == ST_REGS ) { if ( in_p ) return FP_REGS ; return gp_reg_p ? NO_REGS : gr_regs ; } if ( ST_REG_P ( regno ) ) { if ( ! in_p ) return FP_REGS ; return class == gr_regs ? NO_REGS : gr_regs ; } if ( class == FP_REGS ) { if ( MEM_P ( x ) ) { return NO_REGS ; } else if ( CONSTANT_P ( x ) && GET_MODE_CLASS ( mode ) == MODE_FLOAT ) { return NO_REGS ; } else if ( gp_reg_p || x == CONST0_RTX ( mode ) ) { return NO_REGS ; } else if ( FP_REG_P ( regno ) ) { return NO_REGS ; } else { return gr_regs ; } } </s>

This function returns the register class required for a secondary register when copying between one of the registers in CLASS , and X , using MODE . If IN_P is nonzero , the copy is going from X to the register , otherwise the register is the source . A return value of NO_REGS means that no secondary register is required .


"Unknown regclass in loadRegFromStackSlot!"

Load the specified register of the given register class from the specified stack frame index .


<s> bool AMDGPUStructurizeCFG :: doInitialization ( Region * R , RGPassManager & RGM ) { LLVMContext & Context = R -> getEntry ( ) -> getContext ( ) ; Boolean = Type :: getInt1Ty ( Context ) ; BoolTrue = ConstantInt :: getTrue ( Context ) ; BoolFalse = ConstantInt :: getFalse ( Context ) ; BoolUndef = UndefValue :: get ( Boolean ) ; return false ; } </s>

Set up the AsmPrinter when we are working on a new module .


<s> int SystemZFrameLowering :: getFrameIndexReference ( const MachineFunction & MF , int FI , Register & FrameReg ) const { int64_t Offset = TargetFrameLowering :: getFrameIndexReference ( MF , FI , FrameReg ) ; return Offset + SystemZMC :: CallFrameSize ; } </s>

getFrameIndexReference - This method should return the base register and offset used to reference a frame index location .


<s> void rs6000_call_sysv ( rtx value , rtx func_desc , rtx tlsarg , rtx cookie ) { rtx func = func_desc ; rtx func_addr ; rtx call [ 4 ] ; rtx insn ; rtx abi_reg = NULL_RTX ; int n ; if ( global_tlsarg ) tlsarg = global_tlsarg ; if ( ( INTVAL ( cookie ) & CALL_LONG ) != 0 && GET_CODE ( func_desc ) == SYMBOL_REF ) { func = rs6000_longcall_ref ( func_desc , tlsarg ) ; if ( TARGET_PLTSEQ ) abi_reg = func ; } if ( GET_CODE ( func ) != SYMBOL_REF ) { func = force_reg ( Pmode , func ) ; func_addr = gen_rtx_REG ( Pmode , CTR_REGNO ) ; if ( abi_reg ) { rtvec v = gen_rtvec ( 3 , func , func_desc , tlsarg ) ; rtx mark_func = gen_rtx_UNSPEC ( Pmode , v , UNSPEC_PLTSEQ ) ; emit_insn ( gen_rtx_SET ( func_addr , mark_func ) ) ; v = gen_rtvec ( 2 , func_addr , func_desc ) ; func_addr = gen_rtx_UNSPEC ( Pmode , v , UNSPEC_PLTSEQ ) ; } else emit_move_insn ( func_addr , func ) ; } else func_addr = func ; call [ 0 ] = gen_rtx_CALL ( VOIDmode , gen_rtx_MEM ( SImode , func_addr ) , tlsarg ) ; if ( value != NULL_RTX ) call [ 0 ] = gen_rtx_SET ( value , call [ 0 ] ) ; call [ 1 ] = gen_rtx_USE ( VOIDmode , cookie ) ; n = 2 ; if ( TARGET_SECURE_PLT && flag_pic && GET_CODE ( func_addr ) == SYMBOL_REF && ! SYMBOL_REF_LOCAL_P ( func_addr ) ) call [ n ++ ] = gen_rtx_USE ( VOIDmode , pic_offset_table_rtx ) ; call [ n ++ ] = gen_hard_reg_clobber ( Pmode , LR_REGNO ) ; insn = gen_rtx_PARALLEL ( VOIDmode , gen_rtvec_v ( n , call ) ) ; insn = emit_call_insn ( insn ) ; if ( abi_reg ) use_reg ( & CALL_INSN_FUNCTION_USAGE ( insn ) , abi_reg ) ; } </s>

Expand code to perform a call under the SYSV4 ABI .


<s>
void
AArch64FrameLowering
::
orderFrameObjects
(
const
MachineFunction
&
MF
,
SmallVectorImpl
<
int
>
&
ObjectsToAllocate
)
const
{
if
(
!
OrderFrameObjects
||
ObjectsToAllocate
.
empty
(
)
)
return
;
const
MachineFrameInfo
&
MFI
=
MF
.
getFrameInfo
(
)
;
std
::
vector
<
FrameObject
>
FrameObjects
(
MFI
.
getObjectIndexEnd
(
)
)
;
for
(
auto
&
Obj
:
ObjectsToAllocate
)
{
FrameObjects
[
Obj
]
.
IsValid
=
true
;
FrameObjects
[
Obj
]
.
ObjectIndex
=
Obj
;
}
GroupBuilder
GB
(
FrameObjects
)
;
for
(
auto
&
MBB
:
MF
)
{
for
(
auto
&
MI
:
MBB
)
{
if
(
MI
.
isDebugInstr
(
)
)
continue
;
int
OpIndex
;
switch
(
MI
.
getOpcode
(
)
)
{
case
AArch64
::
STGloop
:
case
AArch64
::
STZGloop
:
OpIndex
=
3
;
break
;
case
AArch64
::
STGOffset
:
case
AArch64
::
STZGOffset
:
case
AArch64
::
ST2GOffset
:
case
AArch64
::
STZ2GOffset
:
OpIndex
=
1
;
break
;
default
:
OpIndex
=
1
;
}
int
TaggedFI
=
1
;
if
(
OpIndex
>=
0
)
{
const
MachineOperand
&
MO
=
MI
.
getOperand
(
OpIndex
)
;
if
(
MO
.
isFI
(
)
)
{
int
FI
=
MO
.
getIndex
(
)
;
if
(
FI
>=
0
&&
FI
<
MFI
.
getObjectIndexEnd
(
)
&&
FrameObjects
[
FI
]
.
IsValid
)
TaggedFI
=
FI
;
}
}
if
(
TaggedFI
>=
0
)
GB
.
AddMember
(
TaggedFI
)
;
else
GB
.
EndCurrentGroup
(
)
;
}
GB
.
EndCurrentGroup
(
)
;
}
const
AArch64FunctionInfo
&
AFI
=
*
MF
.
getInfo
<
AArch64FunctionInfo
>
(
)
;
Optional
<
int
>
TBPI
=
AFI
.
getTaggedBasePointerIndex
(
)
;
if
(
TBPI
)
{
FrameObjects
[
*
TBPI
]
.
ObjectFirst
=
true
;
FrameObjects
[
*
TBPI
]
.
GroupFirst
=
true
;
int
FirstGroupIndex
=
FrameObjects
[
*
TBPI
]
.
GroupIndex
;
if
(
FirstGroupIndex
>=
0
)
for
(
FrameObject
&
Object
:
FrameObjects
)
if
(
Object
.
GroupIndex
==
FirstGroupIndex
)
Object
.
GroupFirst
=
true
;
}
llvm
::
stable_sort
(
FrameObjects
,
FrameObjectCompare
)
;
int
i
=
0
;
for
(
auto
&
Obj
:
FrameObjects
)
{
if
(
!
Obj
.
IsValid
)
break
;
ObjectsToAllocate
[
i
++
]
=
Obj
.
ObjectIndex
;
}
LLVM_DEBUG
(
dbgs
(
)
<<
"Final frame order:\n"
;
for
(
auto
&
Obj
:
FrameObjects
)
{
if
(
!
Obj
.
IsValid
)
break
;
dbgs
(
)
<<
"  "
<<
Obj
.
ObjectIndex
<<
": group "
<<
Obj
.
GroupIndex
;
if
(
Obj
.
ObjectFirst
)
dbgs
(
)
<<
", first"
;
if
(
Obj
.
GroupFirst
)
dbgs
(
)
<<
", group-first"
;
dbgs
(
)
<<
"\n"
;
}
)
;
}
</s>


<s> ScheduleHazardRecognizer * ARMBaseInstrInfo :: CreateTargetPostRAHazardRecognizer ( const InstrItineraryData * II ) const { if ( Subtarget . isThumb2 ( ) || Subtarget . hasVFP2 ( ) ) return ( ScheduleHazardRecognizer * ) new ARMHazardRecognizer ( II , * this , getRegisterInfo ( ) , Subtarget ) ; return TargetInstrInfoImpl :: CreateTargetPostRAHazardRecognizer ( II ) ; } </s>

Allocate and return a hazard recognizer to use for by non-scheduling passes .


<s>
SDValue
XCoreTargetLowering
::
LowerCall
(
TargetLowering
::
CallLoweringInfo
&
CLI
,
SmallVectorImpl
<
SDValue
>
&
InVals
)
const
{
SelectionDAG
&
DAG
=
CLI
.
DAG
;
DebugLoc
&
dl
=
CLI
.
DL
;
SmallVector
<
ISD
::
OutputArg
,
32
>
&
Outs
=
CLI
.
Outs
;
SmallVector
<
SDValue
,
32
>
&
OutVals
=
CLI
.
OutVals
;
SmallVector
<
ISD
::
InputArg
,
32
>
&
Ins
=
CLI
.
Ins
;
SDValue
Chain
=
CLI
.
Chain
;
SDValue
Callee
=
CLI
.
Callee
;
bool
&
isTailCall
=
CLI
.
IsTailCall
;
CallingConv
::
ID
CallConv
=
CLI
.
CallConv
;
bool
isVarArg
=
CLI
.
IsVarArg
;
isTailCall
=
false
;
switch
(
CallConv
)
{
default
:
llvm_unreachable
(
"Unsupported calling convention"
)
;
case
CallingConv
::
Fast
:
case
CallingConv
::
C
:
return
LowerCCCCallTo
(
Chain
,
Callee
,
CallConv
,
isVarArg
,
isTailCall
,
Outs
,
OutVals
,
Ins
,
dl
,
DAG
,
InVals
)
;
}
}
</s>

This hook must be implemented to lower calls into the specified DAG .


<s> static rtx load_cr_save ( int regno , rtx frame_reg_rtx , int offset , bool exit_func ) { rtx mem = gen_frame_mem_offset ( SImode , frame_reg_rtx , offset ) ; rtx reg = gen_rtx_REG ( SImode , regno ) ; rtx_insn * insn = emit_move_insn ( reg , mem ) ; if ( ! exit_func && DEFAULT_ABI == ABI_V4 ) { rtx cr = gen_rtx_REG ( SImode , CR2_REGNO ) ; rtx set = gen_rtx_SET ( reg , cr ) ; add_reg_note ( insn , REG_CFA_REGISTER , set ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; } return reg ; } </s>

Restoring cr is a two step process : loading a reg from the frame save , then moving the reg to cr . For ABI_V4 we must let the unwinder know that the stack location is no longer valid at or before the stack deallocation , but we ca n't emit a cfa_restore for cr at the stack deallocation like we do for other registers . The trouble is that it is possible for the move to cr to be scheduled after the stack deallocation . So say exactly where cr is located on each of the two insns .


<s>
static
void
nvptx_asm_declare_constant_name
(
FILE
*
file
,
const
char
*
name
,
const_tree
exp
,
HOST_WIDE_INT
size
)
{
tree
type
=
TREE_TYPE
(
exp
)
;
init_output_initializer
(
file
,
name
,
type
,
false
)
;
fprintf
(
file
,
"\t.const .align %d .u%d "
,
TYPE_ALIGN
(
TREE_TYPE
(
exp
)
)
/
BITS_PER_UNIT
,
decl_chunk_size
*
BITS_PER_UNIT
)
;
assemble_name
(
file
,
name
)
;
fprintf
(
file
,
"["
HOST_WIDE_INT_PRINT_DEC
"]"
,
(
size
+
decl_chunk_size
1
)
/
decl_chunk_size
)
;
object_size
=
size
;
}
</s>

Implement TARGET_ASM_DECLARE_CONSTANT_NAME . Begin the process of writing a constant variable EXP with NAME and SIZE and its initializer to FILE .

nvptx
"\t.const .align %d .u%d "
"["
"]"
1


<s> static void ix86_adjust_stack_and_probe ( const HOST_WIDE_INT size ) { const int dope = 4 * UNITS_PER_WORD ; rtx size_rtx = GEN_INT ( size ) , last ; if ( size <= 5 * PROBE_INTERVAL ) { HOST_WIDE_INT i , adjust ; bool first_probe = true ; for ( i = PROBE_INTERVAL ; i < size ; i += PROBE_INTERVAL ) { if ( first_probe ) { adjust = 2 * PROBE_INTERVAL + dope ; first_probe = false ; } else adjust = PROBE_INTERVAL ; emit_insn ( gen_rtx_SET ( VOIDmode , stack_pointer_rtx , plus_constant ( Pmode , stack_pointer_rtx , - adjust ) ) ) ; emit_stack_probe ( stack_pointer_rtx ) ; } if ( first_probe ) adjust = size + PROBE_INTERVAL + dope ; else adjust = size + PROBE_INTERVAL - i ; emit_insn ( gen_rtx_SET ( VOIDmode , stack_pointer_rtx , plus_constant ( Pmode , stack_pointer_rtx , - adjust ) ) ) ; emit_stack_probe ( stack_pointer_rtx ) ; last = emit_insn ( gen_rtx_SET ( VOIDmode , stack_pointer_rtx , plus_constant ( Pmode , stack_pointer_rtx , PROBE_INTERVAL + dope ) ) ) ; } else { HOST_WIDE_INT rounded_size ; struct scratch_reg sr ; get_scratch_register_on_entry ( & sr ) ; rounded_size = size & - PROBE_INTERVAL ; emit_insn ( gen_rtx_SET ( VOIDmode , stack_pointer_rtx , plus_constant ( Pmode , stack_pointer_rtx , - ( PROBE_INTERVAL + dope ) ) ) ) ; emit_move_insn ( sr . reg , GEN_INT ( - rounded_size ) ) ; emit_insn ( gen_rtx_SET ( VOIDmode , sr . reg , gen_rtx_PLUS ( Pmode , sr . reg , stack_pointer_rtx ) ) ) ; emit_insn ( ix86_gen_adjust_stack_and_probe ( sr . reg , sr . reg , size_rtx ) ) ; if ( size != rounded_size ) { emit_insn ( gen_rtx_SET ( VOIDmode , stack_pointer_rtx , plus_constant ( Pmode , stack_pointer_rtx , rounded_size - size ) ) ) ; emit_stack_probe ( stack_pointer_rtx ) ; } last = emit_insn ( gen_rtx_SET ( VOIDmode , stack_pointer_rtx , plus_constant ( Pmode , stack_pointer_rtx , PROBE_INTERVAL + dope ) ) ) ; release_scratch_register_on_entry ( & sr ) ; } gcc_assert ( cfun -> machine -> fs . cfa_reg != stack_pointer_rtx ) ; if ( size > 0 ) { rtx expr = gen_rtx_SEQUENCE ( VOIDmode , rtvec_alloc ( 2 ) ) ; XVECEXP ( expr , 0 , 0 ) = gen_rtx_SET ( VOIDmode , stack_pointer_rtx , plus_constant ( Pmode , stack_pointer_rtx , - size ) ) ; XVECEXP ( expr , 0 , 1 ) = gen_rtx_SET ( VOIDmode , stack_pointer_rtx , plus_constant ( Pmode , stack_pointer_rtx , PROBE_INTERVAL + dope + size ) ) ; add_reg_note ( last , REG_FRAME_RELATED_EXPR , expr ) ; RTX_FRAME_RELATED_P ( last ) = 1 ; cfun -> machine -> fs . sp_offset += size ; } emit_insn ( gen_blockage ( ) ) ; } </s>

Emit code to adjust the stack pointer by SIZE bytes while probing it .


<s> void emitConstantPool ( ) override { bool UsingConstantPools = ( Subtarget -> inMips16Mode ( ) && Subtarget -> useConstantIslands ( ) ) ; if ( ! UsingConstantPools ) AsmPrinter :: emitConstantPool ( ) ; } </s>

Print to the current output stream assembly representations of the constants in the constant pool MCP .


<s> void assignValueToAddress ( Register ValVReg , Register Addr , LLT MemTy , MachinePointerInfo & MPO , CCValAssign & VA ) override { MachineFunction & MF = MIRBuilder . getMF ( ) ; Register ExtReg = extendRegister ( ValVReg , VA ) ; auto * MMO = MF . getMachineMemOperand ( MPO , MachineMemOperand :: MOStore , MemTy , inferAlignFromPtrInfo ( MF , MPO ) ) ; MIRBuilder . buildStore ( ExtReg , Addr , * MMO ) ; } </s>

An overload which takes an ArgInfo if additional information about the arg is needed .


<s> bool MSP430AsmPrinter :: PrintAsmMemoryOperand ( const MachineInstr * MI , unsigned OpNo , unsigned AsmVariant , const char * ExtraCode , raw_ostream & O ) { if ( ExtraCode && ExtraCode [ 0 ] ) { return true ; } printSrcMemOperand ( MI , OpNo , O ) ; return false ; } </s>

Print the specified operand of MI , an INLINEASM instruction , using the specified assembler variant as an address .


<s> bool aarch64_sve_ld1rq_ld1ro_operand_p ( rtx op , machine_mode mode , scalar_mode elem_mode ) { struct aarch64_address_info addr ; if ( ! MEM_P ( op ) || ! aarch64_classify_address ( & addr , XEXP ( op , 0 ) , elem_mode , false ) ) return false ; if ( addr . type == ADDRESS_REG_IMM ) return offset_4bit_signed_scaled_p ( mode , addr . const_offset ) ; if ( addr . type == ADDRESS_REG_REG ) return ( 1U << addr . shift ) == GET_MODE_SIZE ( elem_mode ) ; return false ; } </s>

Return true if OP is a valid MEM operand for an SVE LD1R { Q , O } instruction where the size of the read data is specified by ` mode ` and the size of the vector elements are specified by ` elem_mode ` .


<s> bool HexagonMCInstrInfo :: isVector ( MCInstrInfo const & MCII , MCInst const & MCI ) { if ( ( getType ( MCII , MCI ) <= HexagonII :: TypeCVI_LAST ) && ( getType ( MCII , MCI ) >= HexagonII :: TypeCVI_FIRST ) ) return true ; return false ; } </s>

Vector instructions are instructions that must fill all instruction slots within an instruction group .


<s> NVPTXSubtarget :: NVPTXSubtarget ( const std :: string & TT , const std :: string & CPU , const std :: string & FS , const NVPTXTargetMachine & TM ) : NVPTXGenSubtargetInfo ( TT , CPU , FS ) , PTXVersion ( 0 ) , SmVersion ( 20 ) , TM ( TM ) , InstrInfo ( ) , TLInfo ( TM , initializeSubtargetDependencies ( CPU , FS ) ) , TSInfo ( TM . getDataLayout ( ) ) , FrameLowering ( ) { } </s>

This constructor initializes the data members to match that of the specified module .


<s> static bool cris_rtx_costs ( rtx x , machine_mode mode , int outer_code , int opno , int * total , bool speed ) { int code = GET_CODE ( x ) ; switch ( code ) { case CONST_INT : { HOST_WIDE_INT val = INTVAL ( x ) ; if ( val == 0 ) * total = 0 ; else if ( val < 32 && val >= - 32 ) * total = 1 ; else if ( val <= 32767 && val >= - 32768 ) * total = 2 ; else * total = 4 ; return true ; } case LABEL_REF : * total = 6 ; return true ; case CONST : case SYMBOL_REF : * total = 6 ; return true ; case CONST_DOUBLE : if ( x != CONST0_RTX ( mode == VOIDmode ? DImode : mode ) ) * total = 12 ; else * total = 0 ; return true ; case MULT : if ( outer_code == PLUS && cris_biap_index_p ( x , false ) ) { * total = 0 ; return true ; } if ( ! CONST_INT_P ( XEXP ( x , 1 ) ) || exact_log2 ( INTVAL ( XEXP ( x , 1 ) ) < 0 ) ) { if ( TARGET_HAS_MUL_INSNS ) { * total = COSTS_N_INSNS ( 1 ) + COSTS_N_INSNS ( 1 ) / 2 ; return true ; } * total = COSTS_N_INSNS ( 132 ) ; return true ; } return false ; case UDIV : case MOD : case UMOD : case DIV : if ( ! CONST_INT_P ( XEXP ( x , 1 ) ) || exact_log2 ( INTVAL ( XEXP ( x , 1 ) ) < 0 ) ) { * total = COSTS_N_INSNS ( 260 ) ; return true ; } return false ; case AND : if ( CONST_INT_P ( XEXP ( x , 1 ) ) && ! CONST_INT_P ( XEXP ( x , 0 ) ) && ! satisfies_constraint_I ( XEXP ( x , 1 ) ) ) { * total = ( rtx_cost ( XEXP ( x , 0 ) , mode , ( enum rtx_code ) outer_code , opno , speed ) + 2 + 2 * GET_MODE_NUNITS ( mode ) ) ; return true ; } return false ; case ZERO_EXTRACT : if ( reload_completed ) { if ( outer_code != COMPARE ) return false ; } else switch ( outer_code ) { case EQ : case NE : case LT : case LTU : case LE : case LEU : case GT : case GTU : case GE : case GEU : break ; default : return false ; } case ZERO_EXTEND : case SIGN_EXTEND : * total = rtx_cost ( XEXP ( x , 0 ) , VOIDmode , ( enum rtx_code ) outer_code , opno , speed ) ; return true ; default : return false ; } } </s>

Compute a ( partial ) cost for rtx X . Return true if the complete cost has been computed , and false if subexpressions should be scanned . In either case , * TOTAL contains the cost result .


<s> bool mem_operand_gpr ( rtx op , machine_mode mode ) { unsigned HOST_WIDE_INT offset ; int extra ; rtx addr = XEXP ( op , 0 ) ; if ( TARGET_UPDATE && ( GET_CODE ( addr ) == PRE_INC || GET_CODE ( addr ) == PRE_DEC ) && mode_supports_pre_incdec_p ( mode ) && legitimate_indirect_address_p ( XEXP ( addr , 0 ) , false ) ) return true ; if ( address_is_prefixed ( addr , mode , NON_PREFIXED_DS ) ) return true ; if ( TARGET_MACHO && GET_CODE ( addr ) == LO_SUM ) return darwin_rs6000_legitimate_lo_sum_const_p ( XEXP ( addr , 1 ) , mode ) ; if ( ! rs6000_offsettable_memref_p ( op , mode , false ) ) return false ; op = address_offset ( addr ) ; if ( op == NULL_RTX ) return true ; offset = INTVAL ( op ) ; if ( TARGET_POWERPC64 && ( offset & 3 ) != 0 ) return false ; extra = GET_MODE_SIZE ( mode ) - UNITS_PER_WORD ; if ( extra < 0 ) extra = 0 ; if ( GET_CODE ( addr ) == LO_SUM ) offset = sext_hwi ( offset , 16 ) ; return SIGNED_16BIT_OFFSET_EXTRA_P ( offset , extra ) ; } </s>

Return true if the MEM operand is a memory operand suitable for use with a ( full width , possibly multiple ) gpr load/store . On powerpc64 this means the offset must be divisible by 4 . Implements ' Y ' constraint . Accept direct , indexed , offset , lo_sum and tocref . Since this is a constraint function we know the operand has satisfied a suitable memory predicate . Offsetting a lo_sum should not be allowed , except where we know by alignment that a 32k boundary is not crossed . Note that by `` offsetting '' here we mean a further offset to access parts of the MEM . It 's fine to have a lo_sum where the inner address is offset from a sym , since the same sym+offset will appear in the high part of the address calculation .


"Should only have register or immediate operands"

Legalize operands in MI by either commuting it or inserting a copy of src1 .


<s> TargetLowering :: ConstraintWeight SystemZTargetLowering :: getSingleConstraintMatchWeight ( AsmOperandInfo & info , const char * constraint ) const { ConstraintWeight weight = CW_Invalid ; Value * CallOperandVal = info . CallOperandVal ; if ( ! CallOperandVal ) return CW_Default ; Type * type = CallOperandVal -> getType ( ) ; switch ( * constraint ) { default : weight = TargetLowering :: getSingleConstraintMatchWeight ( info , constraint ) ; break ; case 'a' : case 'd' : case 'h' : case 'r' : if ( CallOperandVal -> getType ( ) -> isIntegerTy ( ) ) weight = CW_Register ; break ; case 'f' : if ( type -> isFloatingPointTy ( ) ) weight = CW_Register ; break ; case 'v' : if ( ( type -> isVectorTy ( ) || type -> isFloatingPointTy ( ) ) && Subtarget . hasVector ( ) ) weight = CW_Register ; break ; case 'I' : if ( auto * C = dyn_cast < ConstantInt > ( CallOperandVal ) ) if ( isUInt < 8 > ( C -> getZExtValue ( ) ) ) weight = CW_Constant ; break ; case 'J' : if ( auto * C = dyn_cast < ConstantInt > ( CallOperandVal ) ) if ( isUInt < 12 > ( C -> getZExtValue ( ) ) ) weight = CW_Constant ; break ; case 'K' : if ( auto * C = dyn_cast < ConstantInt > ( CallOperandVal ) ) if ( isInt < 16 > ( C -> getSExtValue ( ) ) ) weight = CW_Constant ; break ; case 'L' : if ( auto * C = dyn_cast < ConstantInt > ( CallOperandVal ) ) if ( isInt < 20 > ( C -> getSExtValue ( ) ) ) weight = CW_Constant ; break ; case 'M' : if ( auto * C = dyn_cast < ConstantInt > ( CallOperandVal ) ) if ( C -> getZExtValue ( ) == 0x7fffffff ) weight = CW_Constant ; break ; } return weight ; } </s>

Examine constraint string and operand type and determine a weight value .


<s> rtx sh_find_equiv_gbr_addr ( rtx_insn * insn , rtx mem ) { if ( ! MEM_P ( mem ) || gbr_address_mem ( mem , GET_MODE ( mem ) ) ) return NULL_RTX ; if ( side_effects_p ( XEXP ( mem , 0 ) ) ) return NULL_RTX ; if ( df == NULL ) return NULL_RTX ; base_reg_disp gbr_disp = sh_find_base_reg_disp ( insn , XEXP ( mem , 0 ) ) ; if ( gbr_disp . is_reg ( ) && REGNO ( gbr_disp . reg ( ) ) == GBR_REG ) { for ( df_ref d = DF_REG_DEF_CHAIN ( GBR_REG ) ; d != NULL ; d = DF_REF_NEXT_REG ( d ) ) { if ( CALL_P ( DF_REF_INSN ( d ) ) ) { if ( TEST_HARD_REG_BIT ( regs_invalidated_by_call , GBR_REG ) ) return NULL_RTX ; else continue ; } else return NULL_RTX ; } rtx disp = GEN_INT ( gbr_disp . disp ( ) ) ; if ( gbr_displacement ( disp , GET_MODE ( mem ) ) ) return gen_rtx_PLUS ( SImode , gen_rtx_REG ( SImode , GBR_REG ) , disp ) ; } return NULL_RTX ; } </s>

Given an insn and a memory operand , try to find an equivalent GBR based memory address and return the corresponding new memory address . Return NULL_RTX if not found .


"Stack realignment in presence of dynamic allocas is not supported with"

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s> virtual const PIC16RegisterInfo & getRegisterInfo ( ) const { return RegInfo ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s> unsigned ARMTargetLowering :: getJumpTableEncoding ( ) const { return MachineJumpTableInfo :: EK_Inline ; } </s>

Return the entry encoding for a jump table in the current function .


"Can't store this register to stack slot"

Store the specified register of the given register class to the specified stack frame index .


<s>
void
HexagonCommonGEP
::
materialize
(
NodeToValueMap
&
Loc
)
{
DEBUG
(
dbgs
(
)
<<
"Nodes before materialization:\n"
<<
Nodes
<<
'\n'
)
;
NodeChildrenMap
NCM
;
NodeVect
Roots
;
invert_find_roots
(
Nodes
,
NCM
,
Roots
)
;
while
(
!
Roots
.
empty
(
)
)
{
NodeVect
::
iterator
First
=
Roots
.
begin
(
)
;
GepNode
*
Root
=
*
First
,
*
Last
=
*
First
;
Roots
.
erase
(
First
)
;
NodeVect
;
bool
LastUsed
=
false
;
unsigned
LastCN
=
0
;
Value
*
LocV
=
Loc
[
Last
]
;
if
(
!
LocV
)
continue
;
BasicBlock
*
LastB
=
cast
<
BasicBlock
>
(
LocV
)
;
do
{
.
push_back
(
Last
)
;
LastUsed
=
(
Last
->
Flags
&
GepNode
::
Used
)
;
if
(
LastUsed
)
break
;
NodeChildrenMap
::
iterator
CF
=
NCM
.
find
(
Last
)
;
LastCN
=
(
CF
!=
NCM
.
end
(
)
)
CF
->
second
.
size
(
)
:
0
;
if
(
LastCN
!=
1
)
break
;
GepNode
*
Child
=
CF
->
second
.
front
(
)
;
BasicBlock
*
ChildB
=
cast_or_null
<
BasicBlock
>
(
Loc
[
Child
]
)
;
if
(
ChildB
!=
0
&&
LastB
!=
ChildB
)
break
;
Last
=
Child
;
}
while
(
true
)
;
BasicBlock
::
iterator
InsertAt
=
LastB
->
getTerminator
(
)
->
getIterator
(
)
;
if
(
LastUsed
||
LastCN
>
0
)
{
ValueVect
Urs
;
getAllUsersForNode
(
Root
,
Urs
,
NCM
)
;
BasicBlock
::
iterator
FirstUse
=
first_use_of_in_block
(
Urs
,
LastB
)
;
if
(
FirstUse
!=
LastB
->
end
(
)
)
InsertAt
=
FirstUse
;
}
Value
*
NewInst
=
fabricateGEP
(
,
InsertAt
,
LastB
)
;
if
(
LastCN
>
0
)
{
NodeVect
&
Cs
=
NCM
[
Last
]
;
for
(
NodeVect
::
iterator
I
=
Cs
.
begin
(
)
,
E
=
Cs
.
end
(
)
;
I
!=
E
;
++
I
)
{
GepNode
*
CN
=
*
I
;
CN
->
Flags
&=
~
GepNode
::
Internal
;
CN
->
Flags
|=
GepNode
::
Root
;
CN
->
BaseVal
=
NewInst
;
Roots
.
push_back
(
CN
)
;
}
}
if
(
LastUsed
)
{
NodeToUsesMap
::
iterator
UF
=
Uses
.
find
(
Last
)
;
assert
(
UF
!=
Uses
.
end
(
)
&&
"No use information found"
)
;
UseSet
&
Us
=
UF
->
second
;
for
(
UseSet
::
iterator
I
=
Us
.
begin
(
)
,
E
=
Us
.
end
(
)
;
I
!=
E
;
++
I
)
{
Use
*
U
=
*
I
;
U
->
set
(
NewInst
)
;
}
}
}
}
</s>

This method can be implemented to generate a mapped Value on demand .


<s> static void iq2000_emit_frame_related_store ( rtx mem , rtx reg , HOST_WIDE_INT offset ) { rtx dwarf_address = plus_constant ( Pmode , stack_pointer_rtx , offset ) ; rtx dwarf_mem = gen_rtx_MEM ( GET_MODE ( reg ) , dwarf_address ) ; iq2000_annotate_frame_insn ( emit_move_insn ( mem , reg ) , gen_rtx_SET ( dwarf_mem , reg ) ) ; } </s>

Emit a move instruction that stores REG in MEM . Make the instruction frame related and note that it stores REG at ( SP + OFFSET ) .


<s> virtual const TargetRegisterInfo * getRegisterInfo ( ) const { return & InstrInfo . getRegisterInfo ( ) ; } </s>


<s> unsigned X86TargetLowering :: getByValTypeAlignment ( Type * Ty , const DataLayout & DL ) const { if ( Subtarget . is64Bit ( ) ) { Align TyAlign = DL . getABITypeAlign ( Ty ) ; if ( TyAlign > 8 ) return TyAlign . value ( ) ; return 8 ; } Align Alignment ( 4 ) ; if ( Subtarget . hasSSE1 ( ) ) getMaxByValAlign ( Ty , Alignment ) ; return Alignment . value ( ) ; } </s>

Return the desired alignment for ByVal aggregate function arguments in the caller parameter area .


<s> void ARCDAGToDAGISel :: Select ( SDNode * N ) { switch ( N -> getOpcode ( ) ) { case ISD :: Constant : { uint64_t CVal = cast < ConstantSDNode > ( N ) -> getZExtValue ( ) ; ReplaceNode ( N , CurDAG -> getMachineNode ( isInt < 12 > ( CVal ) ? ARC :: MOV_rs12 : ARC :: MOV_rlimm , SDLoc ( N ) , MVT :: i32 , CurDAG -> getTargetConstant ( CVal , SDLoc ( N ) , MVT :: i32 ) ) ) ; return ; } } SelectCode ( N ) ; } </s>

Main hook for targets to transform nodes into machine nodes .


"Only Linux target is expected to contain LOAD_STACK_GUARD"

This function is called for all pseudo instructions that remain after register allocation .


<s> bool LEGFrameLowering :: hasFP ( const MachineFunction & MF ) const { return MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) || MF . getFrameInfo ( ) . hasVarSizedObjects ( ) ; } </s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .


<s> unsigned SystemZRegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { const SystemZFrameLowering * TFI = getFrameLowering ( MF ) ; return TFI -> hasFP ( MF ) ? SystemZ :: R11D : SystemZ :: R15D ; } </s>


<s> bool X86TTIImpl :: isLegalMaskedStore ( Type * DataType , MaybeAlign Alignment ) { return isLegalMaskedLoad ( DataType , Alignment ) ; } </s>

Return true if the target supports masked store .


<s> void ARMBaseRegisterInfo :: emitLoadConstPool ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator & MBBI , const DebugLoc & dl , Register DestReg , unsigned SubIdx , int Val , ARMCC :: CondCodes Pred , Register PredReg , unsigned MIFlags ) const { MachineFunction & MF = * MBB . getParent ( ) ; const TargetInstrInfo & TII = * MF . getSubtarget ( ) . getInstrInfo ( ) ; MachineConstantPool * ConstantPool = MF . getConstantPool ( ) ; const Constant * C = ConstantInt :: get ( Type :: getInt32Ty ( MF . getFunction ( ) . getContext ( ) ) , Val ) ; unsigned Idx = ConstantPool -> getConstantPoolIndex ( C , Align ( 4 ) ) ; BuildMI ( MBB , MBBI , dl , TII . get ( ARM :: LDRcp ) ) . addReg ( DestReg , getDefRegState ( true ) , SubIdx ) . addConstantPoolIndex ( Idx ) . addImm ( 0 ) . add ( predOps ( Pred , PredReg ) ) . setMIFlags ( MIFlags ) ; } </s>

emitLoadConstPool - Emits a load from constpool to materialize the specified immediate .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . setPreservesCFG ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


"Instr doesn't have FrameIndex operand!"

Determine whether a given base register plus offset immediate is encodable to resolve a frame index .


<s> static rtx mips_builtin_branch_and_move ( rtx condition , rtx target , rtx value_if_true , rtx value_if_false ) { rtx_code_label * true_label , * done_label ; true_label = gen_label_rtx ( ) ; done_label = gen_label_rtx ( ) ; mips_emit_move ( target , value_if_false ) ; emit_jump_insn ( gen_condjump ( condition , true_label ) ) ; emit_jump_insn ( gen_jump ( done_label ) ) ; emit_barrier ( ) ; emit_label ( true_label ) ; mips_emit_move ( target , value_if_true ) ; emit_label ( done_label ) ; return target ; } </s>

Move VALUE_IF_TRUE into TARGET if CONDITION is true ; move VALUE_IF_FALSE into TARGET otherwise . Return TARGET .


<s> int fp_mov_p ( rtx op ) { if ( GET_CODE ( op ) == CONST_DOUBLE ) { long i ; REAL_VALUE_TO_TARGET_SINGLE ( * CONST_DOUBLE_REAL_VALUE ( op ) , i ) ; return SPARC_SIMM13_P ( i ) ; } return 0 ; } </s>

Nonzero if OP is a floating point constant which can be loaded into an integer register using a single mov instruction .


<s> TargetPassConfig * M68kTargetMachine :: createPassConfig ( PassManagerBase & PM ) { return new M68kPassConfig ( * this , PM ) ; } </s>

Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of CodeGen passes .


"SGPR spill should have been removed in SILowerSGPRSpills"

processFunctionBeforeFrameFinalized - This method is called immediately before the specified function 's frame layout ( MF.getFrameInfo ( ) ) is finalized .


<s> static bool insn_defines_reg ( unsigned int regno1 , unsigned int regno2 , rtx insn ) { df_ref def ; FOR_EACH_INSN_DEF ( def , insn ) if ( DF_REF_REG_DEF_P ( def ) && ! DF_REF_IS_ARTIFICIAL ( def ) && ( regno1 == DF_REF_REGNO ( def ) || regno2 == DF_REF_REGNO ( def ) ) ) return true ; return false ; } </s>

Function checks if instruction INSN defines register number REGNO1 or REGNO2 .


<s>
MachineInstr
*
RISCVInstrInfo
::
convertToThreeAddress
(
MachineInstr
&
MI
,
LiveVariables
*
LV
,
LiveIntervals
*
LIS
)
const
{
switch
(
MI
.
getOpcode
(
)
)
{
default
:
break
;
case
CASE_WIDEOP_OPCODE_LMULS
(
FWADD_WV
)
:
case
CASE_WIDEOP_OPCODE_LMULS
(
FWSUB_WV
)
:
case
CASE_WIDEOP_OPCODE_LMULS
(
WADD_WV
)
:
case
CASE_WIDEOP_OPCODE_LMULS
(
WADDU_WV
)
:
case
CASE_WIDEOP_OPCODE_LMULS
(
WSUB_WV
)
:
case
CASE_WIDEOP_OPCODE_LMULS
(
WSUBU_WV
)
:
{
unsigned
NewOpc
;
switch
(
MI
.
getOpcode
(
)
)
{
default
:
llvm_unreachable
(
"Unexpected opcode"
)
;
CASE_WIDEOP_CHANGE_OPCODE_LMULS
(
FWADD_WV
)
CASE_WIDEOP_CHANGE_OPCODE_LMULS
(
FWSUB_WV
)
CASE_WIDEOP_CHANGE_OPCODE_LMULS
(
WADD_WV
)
CASE_WIDEOP_CHANGE_OPCODE_LMULS
(
WADDU_WV
)
CASE_WIDEOP_CHANGE_OPCODE_LMULS
(
WSUB_WV
)
CASE_WIDEOP_CHANGE_OPCODE_LMULS
(
WSUBU_WV
)
}
MachineBasicBlock
&
MBB
=
*
MI
.
getParent
(
)
;
MachineInstrBuilder
MIB
=
BuildMI
(
MBB
,
MI
,
MI
.
getDebugLoc
(
)
,
get
(
NewOpc
)
)
.
add
(
MI
.
getOperand
(
0
)
)
.
add
(
MI
.
getOperand
(
1
)
)
.
add
(
MI
.
getOperand
(
2
)
)
.
add
(
MI
.
getOperand
(
3
)
)
.
add
(
MI
.
getOperand
(
4
)
)
;
MIB
.
copyImplicitOps
(
MI
)
;
if
(
LV
)
{
unsigned
NumOps
=
MI
.
getNumOperands
(
)
;
for
(
unsigned
I
=
1
;
I
<
NumOps
;
++
I
)
{
MachineOperand
&
Op
=
MI
.
getOperand
(
I
)
;
if
(
Op
.
isReg
(
)
&&
Op
.
isKill
(
)
)
LV
->
replaceKillInstruction
(
Op
.
getReg
(
)
,
MI
,
*
MIB
)
;
}
}
if
(
LIS
)
{
SlotIndex
Idx
=
LIS
->
ReplaceMachineInstrInMaps
(
MI
,
*
MIB
)
;
if
(
MI
.
getOperand
(
0
)
.
isEarlyClobber
(
)
)
{
LiveInterval
&
LI
=
LIS
->
getInterval
(
MI
.
getOperand
(
1
)
.
getReg
(
)
)
;
LiveRange
::
Segment
*
S
=
LI
.
getSegmentContaining
(
Idx
)
;
if
(
S
->
end
==
Idx
.
getRegSlot
(
true
)
)
S
->
end
=
Idx
.
getRegSlot
(
)
;
}
}
return
MIB
;
}
}
return
nullptr
;
}
</s>

convertToThreeAddress - This method must be implemented by targets that set the M_CONVERTIBLE_TO_3_ADDR flag .


<s> bool MSP430DAGToDAGISel :: SelectInlineAsmMemoryOperand ( const SDValue & Op , char ConstraintCode , std :: vector < SDValue > & OutOps ) { SDValue Op0 , Op1 ; switch ( ConstraintCode ) { default : return true ; case 'm' : if ( ! SelectAddr ( Op , Op0 , Op1 ) ) return true ; break ; } OutOps . push_back ( Op0 ) ; OutOps . push_back ( Op1 ) ; return false ; } </s>

SelectInlineAsmMemoryOperand - Select the specified address as a target addressing mode , according to the specified constraint .


<s>
StringRef
getPassName
(
)
const
override
{
return
"Define undefs in store instructions"
;
}
</s>

getPassName - Return a nice clean name for a pass .

TVM
"Define undefs in store instructions"


<s> void AArch64TTIImpl :: getUnrollingPreferences ( Loop * L , TTI :: UnrollingPreferences & UP ) { BaseT :: getUnrollingPreferences ( L , UP ) ; if ( L -> getLoopDepth ( ) > 1 ) UP . PartialThreshold *= 2 ; UP . PartialOptSizeThreshold = 0 ; } </s>

Get target-customized preferences for the generic loop unrolling transformation .


<s> int AArch64TTIImpl :: getArithmeticInstrCost ( unsigned Opcode , Type * Ty , TTI :: OperandValueKind Opd1Info , TTI :: OperandValueKind Opd2Info , TTI :: OperandValueProperties Opd1PropInfo , TTI :: OperandValueProperties Opd2PropInfo , ArrayRef < const Value * > Args ) { std :: pair < int , MVT > LT = TLI -> getTypeLegalizationCost ( DL , Ty ) ; int Cost = 0 ; if ( isWideningInstruction ( Ty , Opcode , Args ) ) Cost += ST -> getWideningBaseCost ( ) ; int ISD = TLI -> InstructionOpcodeToISD ( Opcode ) ; switch ( ISD ) { default : return Cost + BaseT :: getArithmeticInstrCost ( Opcode , Ty , Opd1Info , Opd2Info , Opd1PropInfo , Opd2PropInfo ) ; case ISD :: SDIV : if ( Opd2Info == TargetTransformInfo :: OK_UniformConstantValue && Opd2PropInfo == TargetTransformInfo :: OP_PowerOf2 ) { Cost += getArithmeticInstrCost ( Instruction :: Add , Ty , Opd1Info , Opd2Info , TargetTransformInfo :: OP_None , TargetTransformInfo :: OP_None ) ; Cost += getArithmeticInstrCost ( Instruction :: Sub , Ty , Opd1Info , Opd2Info , TargetTransformInfo :: OP_None , TargetTransformInfo :: OP_None ) ; Cost += getArithmeticInstrCost ( Instruction :: Select , Ty , Opd1Info , Opd2Info , TargetTransformInfo :: OP_None , TargetTransformInfo :: OP_None ) ; Cost += getArithmeticInstrCost ( Instruction :: AShr , Ty , Opd1Info , Opd2Info , TargetTransformInfo :: OP_None , TargetTransformInfo :: OP_None ) ; return Cost ; } LLVM_FALLTHROUGH ; case ISD :: UDIV : Cost += BaseT :: getArithmeticInstrCost ( Opcode , Ty , Opd1Info , Opd2Info , Opd1PropInfo , Opd2PropInfo ) ; if ( Ty -> isVectorTy ( ) ) { Cost += getArithmeticInstrCost ( Instruction :: ExtractElement , Ty , Opd1Info , Opd2Info , Opd1PropInfo , Opd2PropInfo ) ; Cost += getArithmeticInstrCost ( Instruction :: InsertElement , Ty , Opd1Info , Opd2Info , Opd1PropInfo , Opd2PropInfo ) ; Cost += Cost ; } return Cost ; case ISD :: ADD : case ISD :: MUL : case ISD :: XOR : case ISD :: OR : case ISD :: AND : return ( Cost + 1 ) * LT . first ; } } </s>

This is an approximation of reciprocal throughput of a math/logic op .


"WebAssembly hasn't implemented computed gotos"

LowerOperation - Provide custom lowering hooks for some operations .


<s> ScheduleHazardRecognizer * TPCInstrInfo :: CreateTargetMIHazardRecognizer ( const InstrItineraryData * II , const ScheduleDAGMI * DAG ) const { return createTPCHazardRecognizer ( II , DAG , false ) ; } </s>

Allocate and return a hazard recognizer to use for this target when scheduling the machine instructions before register allocation .


<s> SparcSubtarget & SparcSubtarget :: initializeSubtargetDependencies ( StringRef CPU , StringRef FS ) { UseSoftMulDiv = false ; IsV9 = false ; IsLeon = false ; V8DeprecatedInsts = false ; IsVIS = false ; IsVIS2 = false ; IsVIS3 = false ; HasHardQuad = false ; UsePopc = false ; UseSoftFloat = false ; HasNoFSMULD = false ; HasNoFMULS = false ; HasLeonCasa = false ; HasUmacSmac = false ; InsertNOPLoad = false ; FixAllFDIVSQRT = false ; DetectRoundChange = false ; std :: string CPUName = CPU ; if ( CPUName . empty ( ) ) CPUName = ( Is64Bit ) ? "v9" : "v8" ; ParseSubtargetFeatures ( CPUName , FS ) ; if ( ! IsV9 ) UsePopc = false ; return * this ; } </s>

initializeSubtargetDependencies - Initializes using a CPU , a TuneCPU , and feature string so that we can use initializer lists for subtarget initialization .


<s> int eligible_for_call_delay ( rtx_insn * trial ) { rtx pat ; if ( get_attr_in_branch_delay ( trial ) == IN_BRANCH_DELAY_FALSE ) return 0 ; if ( TARGET_GNU_TLS || ! TARGET_TLS ) return 1 ; pat = PATTERN ( trial ) ; if ( GET_CODE ( pat ) == SET && GET_CODE ( SET_SRC ( pat ) ) == PLUS ) { rtx unspec = XEXP ( SET_SRC ( pat ) , 1 ) ; if ( GET_CODE ( unspec ) == UNSPEC && ( XINT ( unspec , 1 ) == UNSPEC_TLSGD || XINT ( unspec , 1 ) == UNSPEC_TLSLDM ) ) return 0 ; } return 1 ; } </s>

Return nonzero if TRIAL can go into the call delay slot .


<s> SDValue R600TargetLowering :: LowerFormalArguments ( SDValue Chain , CallingConv :: ID CallConv , bool isVarArg , const SmallVectorImpl < ISD :: InputArg > & Ins , SDLoc DL , SelectionDAG & DAG , SmallVectorImpl < SDValue > & InVals ) const { SmallVector < CCValAssign , 16 > ArgLocs ; CCState CCInfo ( CallConv , isVarArg , DAG . getMachineFunction ( ) , ArgLocs , * DAG . getContext ( ) ) ; MachineFunction & MF = DAG . getMachineFunction ( ) ; R600MachineFunctionInfo * MFI = MF . getInfo < R600MachineFunctionInfo > ( ) ; SmallVector < ISD :: InputArg , 8 > LocalIns ; getOriginalFunctionArgs ( DAG , MF . getFunction ( ) , Ins , LocalIns ) ; AnalyzeFormalArguments ( CCInfo , LocalIns ) ; for ( unsigned i = 0 , e = Ins . size ( ) ; i < e ; ++ i ) { CCValAssign & VA = ArgLocs [ i ] ; const ISD :: InputArg & In = Ins [ i ] ; EVT VT = In . VT ; EVT MemVT = VA . getLocVT ( ) ; if ( ! VT . isVector ( ) && MemVT . isVector ( ) ) { MemVT = MemVT . getVectorElementType ( ) ; } if ( MFI -> getShaderType ( ) != ShaderType :: COMPUTE ) { unsigned Reg = MF . addLiveIn ( VA . getLocReg ( ) , & AMDGPU :: R600_Reg128RegClass ) ; SDValue Register = DAG . getCopyFromReg ( Chain , DL , Reg , VT ) ; InVals . push_back ( Register ) ; continue ; } PointerType * PtrTy = PointerType :: get ( VT . getTypeForEVT ( * DAG . getContext ( ) ) , AMDGPUAS :: CONSTANT_BUFFER_0 ) ; ISD :: LoadExtType Ext = ISD :: NON_EXTLOAD ; if ( MemVT . getScalarSizeInBits ( ) != VT . getScalarSizeInBits ( ) ) { Ext = ISD :: SEXTLOAD ; } unsigned ValBase = ArgLocs [ In . getOrigArgIndex ( ) ] . getLocMemOffset ( ) ; unsigned PartOffset = VA . getLocMemOffset ( ) ; unsigned Offset = 36 + VA . getLocMemOffset ( ) ; MachinePointerInfo PtrInfo ( UndefValue :: get ( PtrTy ) , PartOffset - ValBase ) ; SDValue Arg = DAG . getLoad ( ISD :: UNINDEXED , Ext , VT , DL , Chain , DAG . getConstant ( Offset , DL , MVT :: i32 ) , DAG . getUNDEF ( MVT :: i32 ) , PtrInfo , MemVT , false , true , true , 4 ) ; InVals . push_back ( Arg ) ; MFI -> ABIArgOffset = Offset + MemVT . getStoreSize ( ) ; } return Chain ; } </s>

This hook must be implemented to lower the incoming ( formal ) arguments , described by the Ins array , into the specified DAG .


<s> const MCPhysReg * NVPTXRegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { static const MCPhysReg CalleeSavedRegs [ ] = { 0 } ; return CalleeSavedRegs ; } </s>


<s>
static
void
ix86_avoid_jump_mispredicts
(
void
)
{
rtx_insn
*
insn
,
*
start
=
get_insns
(
)
;
int
nbytes
=
0
,
njumps
=
0
;
bool
isjump
=
false
;
for
(
insn
=
start
;
insn
;
insn
=
NEXT_INSN
(
insn
)
)
{
int
min_size
;
if
(
LABEL_P
(
insn
)
)
{
align_flags
alignment
=
label_to_alignment
(
insn
)
;
int
align
=
alignment
.
levels
[
0
]
.
log
;
int
max_skip
=
alignment
.
levels
[
0
]
.
maxskip
;
if
(
max_skip
>
15
)
max_skip
=
15
;
if
(
align
<=
0
||
(
align
<=
3
&&
max_skip
!=
(
1
<<
align
)
1
)
)
max_skip
=
0
;
if
(
dump_file
)
fprintf
(
dump_file
,
"Label %i with max_skip %i\n"
,
INSN_UID
(
insn
)
,
max_skip
)
;
if
(
max_skip
)
{
while
(
nbytes
+
max_skip
>=
16
)
{
start
=
NEXT_INSN
(
start
)
;
if
(
(
JUMP_P
(
start
)
&&
asm_noperands
(
PATTERN
(
start
)
)
<
0
)
||
CALL_P
(
start
)
)
njumps
,
isjump
=
true
;
else
isjump
=
false
;
nbytes
-=
ix86_min_insn_size
(
start
)
;
}
}
continue
;
}
min_size
=
ix86_min_insn_size
(
insn
)
;
nbytes
+=
min_size
;
if
(
dump_file
)
fprintf
(
dump_file
,
"Insn %i estimated to %i bytes\n"
,
INSN_UID
(
insn
)
,
min_size
)
;
if
(
(
JUMP_P
(
insn
)
&&
asm_noperands
(
PATTERN
(
insn
)
)
<
0
)
||
CALL_P
(
insn
)
)
njumps
++
;
else
continue
;
while
(
njumps
>
3
)
{
start
=
NEXT_INSN
(
start
)
;
if
(
(
JUMP_P
(
start
)
&&
asm_noperands
(
PATTERN
(
start
)
)
<
0
)
||
CALL_P
(
start
)
)
njumps
,
isjump
=
true
;
else
isjump
=
false
;
nbytes
-=
ix86_min_insn_size
(
start
)
;
}
gcc_assert
(
njumps
>=
0
)
;
if
(
dump_file
)
fprintf
(
dump_file
,
"Interval %i to %i has %i bytes\n"
,
INSN_UID
(
start
)
,
INSN_UID
(
insn
)
,
nbytes
)
;
if
(
njumps
==
3
&&
isjump
&&
nbytes
<
16
)
{
int
padsize
=
15
nbytes
+
ix86_min_insn_size
(
insn
)
;
if
(
dump_file
)
fprintf
(
dump_file
,
"Padding insn %i by %i bytes!\n"
,
INSN_UID
(
insn
)
,
padsize
)
;
emit_insn_before
(
gen_pad
(
GEN_INT
(
padsize
)
)
,
insn
)
;
}
}
}
</s>

AMD K8 core mispredicts jumps when there are more than 3 jumps in 16 byte window .


<s> static void pa_init_libfuncs ( void ) { if ( HPUX_LONG_DOUBLE_LIBRARY ) { set_optab_libfunc ( add_optab , TFmode , "_U_Qfadd" ) ; set_optab_libfunc ( sub_optab , TFmode , "_U_Qfsub" ) ; set_optab_libfunc ( smul_optab , TFmode , "_U_Qfmpy" ) ; set_optab_libfunc ( sdiv_optab , TFmode , "_U_Qfdiv" ) ; set_optab_libfunc ( smin_optab , TFmode , "_U_Qmin" ) ; set_optab_libfunc ( smax_optab , TFmode , "_U_Qfmax" ) ; set_optab_libfunc ( sqrt_optab , TFmode , "_U_Qfsqrt" ) ; set_optab_libfunc ( abs_optab , TFmode , "_U_Qfabs" ) ; set_optab_libfunc ( neg_optab , TFmode , "_U_Qfneg" ) ; set_optab_libfunc ( eq_optab , TFmode , "_U_Qfeq" ) ; set_optab_libfunc ( ne_optab , TFmode , "_U_Qfne" ) ; set_optab_libfunc ( gt_optab , TFmode , "_U_Qfgt" ) ; set_optab_libfunc ( ge_optab , TFmode , "_U_Qfge" ) ; set_optab_libfunc ( lt_optab , TFmode , "_U_Qflt" ) ; set_optab_libfunc ( le_optab , TFmode , "_U_Qfle" ) ; set_optab_libfunc ( unord_optab , TFmode , "_U_Qfunord" ) ; set_conv_libfunc ( sext_optab , TFmode , SFmode , "_U_Qfcnvff_sgl_to_quad" ) ; set_conv_libfunc ( sext_optab , TFmode , DFmode , "_U_Qfcnvff_dbl_to_quad" ) ; set_conv_libfunc ( trunc_optab , SFmode , TFmode , "_U_Qfcnvff_quad_to_sgl" ) ; set_conv_libfunc ( trunc_optab , DFmode , TFmode , "_U_Qfcnvff_quad_to_dbl" ) ; set_conv_libfunc ( sfix_optab , SImode , TFmode , TARGET_64BIT ? "__U_Qfcnvfxt_quad_to_sgl" : "_U_Qfcnvfxt_quad_to_sgl" ) ; set_conv_libfunc ( sfix_optab , DImode , TFmode , "_U_Qfcnvfxt_quad_to_dbl" ) ; set_conv_libfunc ( ufix_optab , SImode , TFmode , "_U_Qfcnvfxt_quad_to_usgl" ) ; set_conv_libfunc ( ufix_optab , DImode , TFmode , "_U_Qfcnvfxt_quad_to_udbl" ) ; set_conv_libfunc ( sfloat_optab , TFmode , SImode , "_U_Qfcnvxf_sgl_to_quad" ) ; set_conv_libfunc ( sfloat_optab , TFmode , DImode , "_U_Qfcnvxf_dbl_to_quad" ) ; set_conv_libfunc ( ufloat_optab , TFmode , SImode , "_U_Qfcnvxf_usgl_to_quad" ) ; set_conv_libfunc ( ufloat_optab , TFmode , DImode , "_U_Qfcnvxf_udbl_to_quad" ) ; } if ( TARGET_SYNC_LIBCALLS ) init_sync_libfuncs ( MAX_SYNC_LIBFUNC_SIZE ) ; } </s>

Initialize optabs to point to emulation routines .


<s> void RISCVInstrInfo :: adjustStackPtr ( unsigned SP , int64_t Amount , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { DebugLoc DL = I != MBB . end ( ) ? I -> getDebugLoc ( ) : DebugLoc ( ) ; unsigned ADD = STI . isRV64 ( ) ? RISCV :: ADD64 : RISCV :: ADD ; unsigned ADDI = STI . isRV64 ( ) ? RISCV :: ADDI64 : RISCV :: ADDI ; if ( isInt < 12 > ( Amount ) ) BuildMI ( MBB , I , DL , get ( ADDI ) , SP ) . addReg ( SP ) . addImm ( Amount ) ; else { unsigned Reg ; loadImmediate ( MBB , I , & Reg , Amount ) ; BuildMI ( MBB , I , DL , get ( ADD ) , SP ) . addReg ( SP ) . addReg ( Reg , RegState :: Kill ) ; } } </s>


<s>
void
HexagonMCCodeEmitter
::
encodeInstruction
(
const
MCInst
&
MI
,
raw_ostream
&
OS
,
SmallVectorImpl
<
MCFixup
>
&
Fixups
,
const
MCSubtargetInfo
&
STI
)
const
{
MCInst
&
HMB
=
const_cast
<
MCInst
&
>
(
MI
)
;
assert
(
HexagonMCInstrInfo
::
isBundle
(
HMB
)
)
;
DEBUG
(
dbgs
(
)
<<
"Encoding bundle\n"
;
)
;
*
Addend
=
0
;
*
Extended
=
false
;
*
CurrentBundle
=
&
MI
;
*
CurrentIndex
=
0
;
size_t
Last
=
HexagonMCInstrInfo
::
bundleSize
(
HMB
)
1
;
for
(
auto
&
I
:
HexagonMCInstrInfo
::
bundleInstructions
(
HMB
)
)
{
MCInst
&
HMI
=
const_cast
<
MCInst
&
>
(
*
I
.
getInst
(
)
)
;
verifyInstructionPredicates
(
HMI
,
computeAvailableFeatures
(
STI
.
getFeatureBits
(
)
)
)
;
EncodeSingleInstruction
(
HMI
,
OS
,
Fixups
,
STI
,
parseBits
(
Last
,
HMB
,
HMI
)
)
;
*
Extended
=
HexagonMCInstrInfo
::
isImmext
(
HMI
)
;
*
Addend
+=
HEXAGON_INSTR_SIZE
;
++
*
CurrentIndex
;
}
}
</s>

Encode the given Inst to bytes and append to CB .

Hexagon
Hexagon
Hexagon
"Encoding bundle\n"
0
0
Hexagon
1
Hexagon
Hexagon


<s> static void x86_64_elf_unique_section ( tree decl , int reloc ) { if ( ( ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_MEDIUM_PIC ) && ix86_in_large_data_p ( decl ) ) { const char * prefix = NULL ; bool one_only = DECL_ONE_ONLY ( decl ) && ! HAVE_COMDAT_GROUP ; switch ( categorize_decl_for_section ( decl , reloc , flag_pic ) ) { case SECCAT_DATA : case SECCAT_DATA_REL : case SECCAT_DATA_REL_LOCAL : case SECCAT_DATA_REL_RO : case SECCAT_DATA_REL_RO_LOCAL : prefix = one_only ? ".gnu.linkonce.ld." : ".ldata." ; break ; case SECCAT_BSS : prefix = one_only ? ".gnu.linkonce.lb." : ".lbss." ; break ; case SECCAT_RODATA : case SECCAT_RODATA_MERGE_STR : case SECCAT_RODATA_MERGE_STR_INIT : case SECCAT_RODATA_MERGE_CONST : prefix = one_only ? ".gnu.linkonce.lr." : ".lrodata." ; break ; case SECCAT_SRODATA : case SECCAT_SDATA : case SECCAT_SBSS : gcc_unreachable ( ) ; case SECCAT_TEXT : case SECCAT_TDATA : case SECCAT_TBSS : break ; } if ( prefix ) { const char * name ; size_t nlen , plen ; char * string ; plen = strlen ( prefix ) ; name = IDENTIFIER_POINTER ( DECL_ASSEMBLER_NAME ( decl ) ) ; name = targetm . strip_name_encoding ( name ) ; nlen = strlen ( name ) ; string = alloca ( nlen + plen + 1 ) ; memcpy ( string , prefix , plen ) ; memcpy ( string + plen , name , nlen + 1 ) ; DECL_SECTION_NAME ( decl ) = build_string ( nlen + plen , string ) ; return ; } } default_unique_section ( decl , reloc ) ; } </s>

Build up a unique section name , expressed as a STRING_CST node , and assign it to DECL_SECTION_NAME ( decl ) . RELOC indicates whether the initial value of EXP requires link-time relocations .


<s>
bool
TOYPreEmit
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
DEBUG
(
dbgs
(
)
<<
"********* TOY PreRmit *********\n"
)
;
TII
=
MF
.
getTarget
(
)
.
getInstrInfo
(
)
;
bool
Changed
=
false
;
Changed
|=
optimizeLoopBranch
(
MF
)
;
Changed
|=
removeFallThroughBranch
(
MF
)
;
Changed
|=
localValueNumbering
(
MF
)
;
return
Changed
;
}
</s>

runOnMachineFunction - Emit the function body .


<s> MachineInstr * SystemZInstrInfo :: foldMemoryOperandImpl ( MachineFunction & MF , MachineInstr * MI , ArrayRef < unsigned > Ops , MachineBasicBlock :: iterator InsertPt , MachineInstr * LoadMI ) const { return nullptr ; } </s>

foldMemoryOperand - Same as the previous version except it allows folding of any load and store from / to any address , not just from a specific stack slot .


<s> bool ix86_tls_address_pattern_p ( rtx op ) { subrtx_var_iterator :: array_type array ; FOR_EACH_SUBRTX_VAR ( iter , array , op , ALL ) { rtx op = * iter ; if ( MEM_P ( op ) ) { rtx * x = & XEXP ( op , 0 ) ; while ( GET_CODE ( * x ) == PLUS ) { int i ; for ( i = 0 ; i < 2 ; i ++ ) { rtx u = XEXP ( * x , i ) ; if ( GET_CODE ( u ) == ZERO_EXTEND ) u = XEXP ( u , 0 ) ; if ( GET_CODE ( u ) == UNSPEC && XINT ( u , 1 ) == UNSPEC_TP ) return true ; } x = & XEXP ( * x , 0 ) ; } iter . skip_subrtxes ( ) ; } } return false ; } </s>

Return true if OP refers to a TLS address .


<s> static bool mips_can_inline_p ( tree caller , tree callee ) { if ( mips_get_compress_mode ( callee ) != mips_get_compress_mode ( caller ) ) return false ; return default_target_can_inline_p ( caller , callee ) ; } </s>


"Prologue matched, checking for no-return epilogue.\n"

"Prologue call to riscv_save_0 followed by noreturn call, "


<s> static void ix86_store_bounds ( rtx ptr , rtx slot , rtx bounds , rtx slot_no ) { rtx addr ; addr = ix86_get_arg_address_for_bt ( slot , slot_no , stack_pointer_rtx ) ; if ( ! ptr ) { gcc_assert ( MEM_P ( slot ) ) ; ptr = copy_addr_to_reg ( slot ) ; } if ( ! register_operand ( ptr , Pmode ) ) ptr = ix86_zero_extend_to_Pmode ( ptr ) ; gcc_assert ( POINTER_BOUNDS_MODE_P ( GET_MODE ( bounds ) ) ) ; if ( ! register_operand ( bounds , BNDmode ) ) bounds = copy_to_mode_reg ( BNDmode , bounds ) ; emit_insn ( BNDmode == BND64mode ? gen_bnd64_stx ( addr , ptr , bounds ) : gen_bnd32_stx ( addr , ptr , bounds ) ) ; } </s>

Expand pass uses this hook to store BOUNDS for call argument PTR passed in SLOT in case BOUNDS are not passed in a register . If SLOT is a memory , then BOUNDS are stored as for regular pointer stored in memory . PTR may be NULL in case SLOT is a memory . In such case value of PTR ( if required ) may be loaded from SLOT . If SLOT is NULL or a register then SLOT_NO is an integer constant holding number of the target dependent special slot which should be used to store BOUNDS .


<s> static bool is_ldr_shift_p ( HOST_WIDE_INT shift , enum rtx_code code ) { if ( code == ASHIFT ) return ( shift >= 0 && shift <= 3 ) ; else if ( code == MULT ) return ( shift == 1 || shift == 2 || shift == 4 || shift == 8 ) ; else return false ; } </s>

The instruction ldr rz , ( rx , ry < < i ) , i can be 0,1,2,3 . Check that SHIFT is valid , that the code is MULT , and that the shift is a power of 2 .


<s>
void
BlackfinAsmPrinter
::
emitLinkage
(
const
std
::
string
&
name
,
GlobalValue
::
LinkageTypes
l
)
{
switch
(
l
)
{
default
:
llvm_unreachable
(
"Unknown linkage type!"
)
;
case
GlobalValue
::
InternalLinkage
:
case
GlobalValue
::
PrivateLinkage
:
case
GlobalValue
::
LinkerPrivateLinkage
:
break
;
case
GlobalValue
::
ExternalLinkage
:
O
<<
TAI
->
getGlobalDirective
(
)
<<
name
<<
"\n"
;
break
;
case
GlobalValue
::
LinkOnceAnyLinkage
:
case
GlobalValue
::
LinkOnceODRLinkage
:
case
GlobalValue
::
WeakAnyLinkage
:
case
GlobalValue
::
WeakODRLinkage
:
O
<<
TAI
->
getGlobalDirective
(
)
<<
name
<<
"\n"
;
O
<<
TAI
->
getWeakDefDirective
(
)
<<
name
<<
"\n"
;
break
;
}
}
</s>

This emits linkage information about GVSym based on GV , if this is supported by the target .

Blackfin
"Unknown linkage type!"
"\n"
"\n"
"\n"


<s> static bool ix86_noce_conversion_profitable_p ( rtx_insn * seq , struct noce_if_info * if_info ) { if ( TARGET_ONE_IF_CONV_INSN && if_info -> speed_p ) { int cmov_cnt = 0 ; for ( rtx_insn * insn = seq ; insn ; insn = NEXT_INSN ( insn ) ) { rtx set = single_set ( insn ) ; if ( ! set ) continue ; if ( GET_CODE ( SET_SRC ( set ) ) != IF_THEN_ELSE ) continue ; rtx src = SET_SRC ( set ) ; enum machine_mode mode = GET_MODE ( src ) ; if ( GET_MODE_CLASS ( mode ) != MODE_INT && GET_MODE_CLASS ( mode ) != MODE_FLOAT ) continue ; if ( ( ! REG_P ( XEXP ( src , 1 ) ) && ! MEM_P ( XEXP ( src , 1 ) ) ) || ( ! REG_P ( XEXP ( src , 2 ) ) && ! MEM_P ( XEXP ( src , 2 ) ) ) ) continue ; if ( ++ cmov_cnt > 1 ) return false ; } } return default_noce_conversion_profitable_p ( seq , if_info ) ; } </s>

Return true if SEQ is a good candidate as a replacement for the if-convertible sequence described in IF_INFO .


<s> void X86PassConfig :: addPreEmitPass2 ( ) { addPass ( createX86RetpolineThunksPass ( ) ) ; addPass ( createSandBoxingPass ( ) ) ; } </s>

Targets may add passes immediately before machine code is emitted in this callback .


<s> bool X86TargetLowering :: allowsMisalignedMemoryAccesses ( EVT VT , unsigned , unsigned , bool * Fast ) const { if ( Fast ) { switch ( VT . getSizeInBits ( ) ) { default : * Fast = true ; break ; case 128 : * Fast = ! Subtarget -> isUnalignedMem16Slow ( ) ; break ; case 256 : * Fast = ! Subtarget -> isUnalignedMem32Slow ( ) ; break ; } } return true ; } </s>

Returns true if the target allows unaligned memory accesses of the specified type .


<s>
void
ft32_print_operand
(
FILE
*
file
,
rtx
x
,
int
code
)
{
rtx
operand
=
x
;
switch
(
code
)
{
case
0
:
break
;
case
'h'
:
if
(
GET_CODE
(
operand
)
!=
REG
)
internal_error
(
"%<h%> applied to non-register operand"
)
;
fprintf
(
file
,
"%s"
,
reg_names
[
REGNO
(
operand
)
+
1
]
)
;
return
;
case
'm'
:
fprintf
(
file
,
"%ld"
,
(
long
)
(
INTVAL
(
x
)
)
)
;
return
;
case
'd'
:
{
int
i
=
INTVAL
(
x
)
;
char
dwspec
;
switch
(
i
)
{
case
1
:
dwspec
=
'b'
;
break
;
case
2
:
dwspec
=
's'
;
break
;
case
4
:
dwspec
=
'l'
;
break
;
default
:
if
(
(
i
%
4
)
!=
0
)
internal_error
(
"bad alignment: %d"
,
i
)
;
else
dwspec
=
'l'
;
break
;
}
fprintf
(
file
,
"%c"
,
dwspec
)
;
return
;
}
case
'f'
:
{
int
bf
=
ft32_as_bitfield
(
INTVAL
(
x
)
)
;
fprintf
(
file
,
"512|(%d<<5)|%d"
,
bf
>>
5
,
bf
&
31
)
;
return
;
}
case
'g'
:
{
int
bf
=
ft32_as_bitfield
(
0xffffffff
^
INTVAL
(
x
)
)
;
fprintf
(
file
,
"(%d<<5)|%d"
,
bf
>>
5
,
bf
&
31
)
;
return
;
}
case
'b'
:
{
ft32_print_operand
(
file
,
XEXP
(
x
,
0
)
,
0
)
;
return
;
}
default
:
LOSE_AND_RETURN
(
"invalid operand modifier letter"
,
x
)
;
}
switch
(
GET_CODE
(
operand
)
)
{
case
REG
:
fprintf
(
file
,
"%s"
,
reg_names
[
REGNO
(
operand
)
]
)
;
return
;
case
MEM
:
output_address
(
GET_MODE
(
XEXP
(
operand
,
0
)
)
,
XEXP
(
operand
,
0
)
)
;
return
;
default
:
if
(
CONSTANT_P
(
operand
)
)
{
output_addr_const
(
file
,
operand
)
;
return
;
}
LOSE_AND_RETURN
(
"unexpected operand"
,
x
)
;
}
}
</s>


<s>
static
tree
ix86_handle_struct_attribute
(
tree
*
node
,
tree
name
,
tree
,
int
,
bool
*
no_add_attrs
)
{
tree
*
type
=
;
if
(
DECL_P
(
*
node
)
)
{
if
(
TREE_CODE
(
*
node
)
==
TYPE_DECL
)
type
=
&
TREE_TYPE
(
*
node
)
;
}
else
type
=
node
;
if
(
!
(
type
&&
RECORD_OR_UNION_TYPE_P
(
*
type
)
)
)
{
warning
(
OPT_Wattributes
,
"%qE attribute ignored"
,
name
)
;
*
no_add_attrs
=
true
;
}
else
if
(
(
is_attribute_p
(
"ms_struct"
,
name
)
&&
lookup_attribute
(
"gcc_struct"
,
TYPE_ATTRIBUTES
(
*
type
)
)
)
||
(
(
is_attribute_p
(
"gcc_struct"
,
name
)
&&
lookup_attribute
(
"ms_struct"
,
TYPE_ATTRIBUTES
(
*
type
)
)
)
)
)
{
warning
(
OPT_Wattributes
,
"%qE incompatible attribute ignored"
,
name
)
;
*
no_add_attrs
=
true
;
}
return
NULL_TREE
;
}
</s>

Handle a `` ms_struct '' or `` gcc_struct '' attribute ; arguments as in struct attribute_spec.handler .


<s> void Thumb2InstrInfo :: storeRegToStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , Register SrcReg , bool isKill , int FI , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { DebugLoc DL ; if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( MF , FI ) , MachineMemOperand :: MOStore , MFI . getObjectSize ( FI ) , MFI . getObjectAlign ( FI ) ) ; if ( ARM :: GPRRegClass . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( ARM :: t2STRi12 ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addFrameIndex ( FI ) . addImm ( 0 ) . addMemOperand ( MMO ) . add ( predOps ( ARMCC :: AL ) ) ; return ; } if ( ARM :: GPRPairRegClass . hasSubClassEq ( RC ) ) { if ( Register :: isVirtualRegister ( SrcReg ) ) { MachineRegisterInfo * MRI = & MF . getRegInfo ( ) ; MRI -> constrainRegClass ( SrcReg , & ARM :: GPRPairnospRegClass ) ; } MachineInstrBuilder MIB = BuildMI ( MBB , I , DL , get ( ARM :: t2STRDi8 ) ) ; AddDReg ( MIB , SrcReg , ARM :: gsub_0 , getKillRegState ( isKill ) , TRI ) ; AddDReg ( MIB , SrcReg , ARM :: gsub_1 , 0 , TRI ) ; MIB . addFrameIndex ( FI ) . addImm ( 0 ) . addMemOperand ( MMO ) . add ( predOps ( ARMCC :: AL ) ) ; return ; } ARMBaseInstrInfo :: storeRegToStackSlot ( MBB , I , SrcReg , isKill , FI , RC , TRI ) ; } </s>

Store the specified register of the given register class to the specified stack frame index .


"This eliminateCallFramePseudoInstr does not support Thumb1!"

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .


<s>
static
void
mips_output_filename
(
FILE
*
stream
,
const
char
*
name
)
{
if
(
dwarf_debuginfo_p
(
)
)
return
;
else
if
(
mips_output_filename_first_time
)
{
mips_output_filename_first_time
=
0
;
num_source_filenames
+=
1
;
current_function_file
=
name
;
fprintf
(
stream
,
"\t.file\t%d "
,
num_source_filenames
)
;
output_quoted_string
(
stream
,
name
)
;
putc
(
'\n'
,
stream
)
;
}
else
if
(
write_symbols
==
DBX_DEBUG
)
return
;
else
if
(
name
!=
current_function_file
&&
strcmp
(
name
,
current_function_file
)
!=
0
)
{
num_source_filenames
+=
1
;
current_function_file
=
name
;
fprintf
(
stream
,
"\t.file\t%d "
,
num_source_filenames
)
;
output_quoted_string
(
stream
,
name
)
;
putc
(
'\n'
,
stream
)
;
}
}
</s>

Emit a new filename to a stream . If we are smuggling stabs , try to put out a MIPS ECOFF file and a stab .


<s> static bool isUndef ( ArrayRef < int > Mask ) { for ( int Idx : Mask ) if ( Idx != - 1 ) return false ; return true ; } </s>

Return true if the result of this operation is always undefined .


<s> void m88k_layout_frame ( ) { int regno , sp_size ; frame_laid_out ++ ; memset ( ( char * ) & save_regs [ 0 ] , 0 , sizeof ( save_regs ) ) ; sp_size = nregs = nxregs = 0 ; frame_size = get_frame_size ( ) ; if ( current_function_profile ) save_regs [ 1 ] = 1 ; if ( write_symbols != NO_DEBUG && ! TARGET_OCS_FRAME_POSITION ) save_regs [ 1 ] = 1 ; if ( regs_ever_live [ 1 ] || frame_pointer_needed ) { save_regs [ 1 ] = 1 ; sp_size += REG_PARM_STACK_SPACE ( 0 ) ; } if ( flag_pic && current_function_uses_pic_offset_table ) { save_regs [ PIC_OFFSET_TABLE_REGNUM ] = 1 ; nregs ++ ; } if ( frame_pointer_needed ) save_regs [ FRAME_POINTER_REGNUM ] = save_regs [ 1 ] = 1 ; else if ( regs_ever_live [ FRAME_POINTER_REGNUM ] ) save_regs [ FRAME_POINTER_REGNUM ] = 1 ; for ( regno = FIRST_EXTENDED_REGISTER + 1 ; regno < FIRST_PSEUDO_REGISTER ; regno ++ ) if ( regs_ever_live [ regno ] && ! call_used_regs [ regno ] ) { save_regs [ regno ] = 1 ; nxregs ++ ; } for ( regno = 2 ; regno < FRAME_POINTER_REGNUM ; regno ++ ) if ( regs_ever_live [ regno ] && ! call_used_regs [ regno ] ) { save_regs [ regno ] = 1 ; nregs ++ ; } if ( nregs >= 2 && save_regs [ 1 ] && ! save_regs [ FRAME_POINTER_REGNUM ] ) sp_size += 4 ; nregs += save_regs [ 1 ] + save_regs [ FRAME_POINTER_REGNUM ] ; if ( nxregs > 0 && ( nregs & 1 ) != 0 ) sp_size += 4 ; sp_size += 4 * nregs ; sp_size += 8 * nxregs ; sp_size += current_function_outgoing_args_size ; if ( frame_pointer_needed || sp_size ) m88k_fp_offset = ROUND_CALL_BLOCK_SIZE ( sp_size - STARTING_FRAME_OFFSET ) ; else m88k_fp_offset = - STARTING_FRAME_OFFSET ; m88k_stack_size = m88k_fp_offset + STARTING_FRAME_OFFSET ; { int need = ( ( m88k_stack_size ? STACK_UNIT_BOUNDARY - STARTING_FRAME_OFFSET : 0 ) - ( frame_size % STACK_UNIT_BOUNDARY ) ) ; if ( need < 0 ) need += STACK_UNIT_BOUNDARY ; m88k_stack_size = ROUND_CALL_BLOCK_SIZE ( m88k_stack_size + frame_size + need + current_function_pretend_args_size ) ; } } </s>

Establish the position of the FP relative to the SP . This is done either during output_function_prologue ( ) or by INITIAL_ELIMINATION_OFFSET .


<s> bool runOnMachineFunction ( MachineFunction & MF ) override { TII = static_cast < const R600InstrInfo * > ( MF . getTarget ( ) . getInstrInfo ( ) ) ; TRI = & TII -> getRegisterInfo ( ) ; DEBUG ( MF . dump ( ) ; ) ; OrderedBlks . clear ( ) ; FuncRep = & MF ; MLI = & getAnalysis < MachineLoopInfo > ( ) ; DEBUG ( dbgs ( ) << "LoopInfo:\n" ; PrintLoopinfo ( * MLI ) ; ) ; MDT = & getAnalysis < MachineDominatorTree > ( ) ; DEBUG ( MDT -> print ( dbgs ( ) , ( const llvm :: Module * ) nullptr ) ; ) ; PDT = & getAnalysis < MachinePostDominatorTree > ( ) ; DEBUG ( PDT -> print ( dbgs ( ) ) ; ) ; prepare ( ) ; run ( ) ; DEBUG ( MF . dump ( ) ; ) ; return true ; } </s>


<s> void AArch64TargetLowering :: finalizeLowering ( MachineFunction & MF ) const { MF . getFrameInfo ( ) . computeMaxCallFrameSize ( MF ) ; TargetLoweringBase :: finalizeLowering ( MF ) ; } </s>

Execute target specific actions to finalize target lowering .


<s> MVT :: SimpleValueType getCmpLibcallReturnType ( ) const override { return MVT :: i8 ; } </s>

Return the ValueType for comparison libcalls .


<s> void z8k_output_external ( const char * name ) { struct extern_list * p ; p = ( struct extern_list * ) xmalloc ( ( long ) sizeof ( struct extern_list ) ) ; p -> next = extern_head ; p -> name = xstrdup ( name ) ; extern_head = p ; } </s>

Keep track of all externs , so that we can output an .extern declaration for them at the end of the file , but only if they are not defined in this file . We assume that all names passed to us are in the permanent obstack , so that they will be valid at the end of the compilation .


<s> std :: unique_ptr < MCObjectWriter > createObjectWriter ( raw_pwrite_stream & OS ) const override { return createAMDGPUELFObjectWriter ( Is64Bit , OSABI , HasRelocationAddend , OS ) ; } </s>

Create a new MCObjectWriter instance for use by the assembler backend to emit the final object file .


<s> SDValue PPCTargetLowering :: getSqrtEstimate ( SDValue Operand , SelectionDAG & DAG , int Enabled , int & RefinementSteps , bool & UseOneConstNR , bool Reciprocal ) const { EVT VT = Operand . getValueType ( ) ; if ( ( VT == MVT :: f32 && Subtarget . hasFRSQRTES ( ) ) || ( VT == MVT :: f64 && Subtarget . hasFRSQRTE ( ) ) || ( VT == MVT :: v4f32 && Subtarget . hasAltivec ( ) ) || ( VT == MVT :: v2f64 && Subtarget . hasVSX ( ) ) || ( VT == MVT :: v4f32 && Subtarget . hasQPX ( ) ) || ( VT == MVT :: v4f64 && Subtarget . hasQPX ( ) ) ) { if ( RefinementSteps == ReciprocalEstimate :: Unspecified ) RefinementSteps = getEstimateRefinementSteps ( VT , Subtarget ) ; UseOneConstNR = ! Subtarget . needsTwoConstNR ( ) ; return DAG . getNode ( PPCISD :: FRSQRTE , SDLoc ( Operand ) , VT , Operand ) ; } return SDValue ( ) ; } </s>

Hooks for building estimates in place of slower divisions and square roots .


Return a function that will generate a check for speculation TS with mode MODE_NO . If simple check is needed , pass true for SIMPLE_CHECK_P . If clearing check is needed , pass true for CLEARING_CHECK_P .


<s> bool NVPTXFrameLowering :: hasFP ( const MachineFunction & MF ) const { return true ; } </s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .


"********** Memory Intrinsic Results **********\n"

"MemIntrinsicResults expects liveness tracking"

runOnMachineFunction - Emit the function body .


<s> poly_int64 riscv_v_adjust_nunits ( machine_mode mode , int scale ) { if ( riscv_v_ext_vector_mode_p ( mode ) ) return riscv_vector_chunks * scale ; return scale ; } </s>

Call from ADJUST_NUNITS in riscv-modes.def . Return the correct NUNITS size for corresponding machine_mode .


"Relocation required in an instruction that we cannot encode!"

getMachineOpValue - Return binary encoding of operand .


<s> StackOffset SystemZELFFrameLowering :: getFrameIndexReference ( const MachineFunction & MF , int FI , Register & FrameReg ) const { StackOffset Offset = TargetFrameLowering :: getFrameIndexReference ( MF , FI , FrameReg ) ; return Offset + StackOffset :: getFixed ( SystemZMC :: ELFCallFrameSize ) ; } </s>

getFrameIndexReference - This method should return the base register and offset used to reference a frame index location .


<s> static rtx m68k_legitimize_address ( rtx x , rtx oldx , machine_mode mode ) { if ( m68k_tls_symbol_p ( x ) ) return m68k_legitimize_tls_address ( x ) ; if ( GET_CODE ( x ) == PLUS ) { int ch = ( x ) != ( oldx ) ; int copied = 0 ; if ( GET_CODE ( XEXP ( x , 0 ) ) == MULT ) { COPY_ONCE ( x ) ; XEXP ( x , 0 ) = force_operand ( XEXP ( x , 0 ) , 0 ) ; } if ( GET_CODE ( XEXP ( x , 1 ) ) == MULT ) { COPY_ONCE ( x ) ; XEXP ( x , 1 ) = force_operand ( XEXP ( x , 1 ) , 0 ) ; } if ( ch ) { if ( GET_CODE ( XEXP ( x , 1 ) ) == REG && GET_CODE ( XEXP ( x , 0 ) ) == REG ) { if ( TARGET_COLDFIRE_FPU && GET_MODE_CLASS ( mode ) == MODE_FLOAT ) { COPY_ONCE ( x ) ; x = force_operand ( x , 0 ) ; } return x ; } if ( memory_address_p ( mode , x ) ) return x ; } if ( GET_CODE ( XEXP ( x , 0 ) ) == REG || ( GET_CODE ( XEXP ( x , 0 ) ) == SIGN_EXTEND && GET_CODE ( XEXP ( XEXP ( x , 0 ) , 0 ) ) == REG && GET_MODE ( XEXP ( XEXP ( x , 0 ) , 0 ) ) == HImode ) ) { rtx temp = gen_reg_rtx ( Pmode ) ; rtx val = force_operand ( XEXP ( x , 1 ) , 0 ) ; emit_move_insn ( temp , val ) ; COPY_ONCE ( x ) ; XEXP ( x , 1 ) = temp ; if ( TARGET_COLDFIRE_FPU && GET_MODE_CLASS ( mode ) == MODE_FLOAT && GET_CODE ( XEXP ( x , 0 ) ) == REG ) x = force_operand ( x , 0 ) ; } else if ( GET_CODE ( XEXP ( x , 1 ) ) == REG || ( GET_CODE ( XEXP ( x , 1 ) ) == SIGN_EXTEND && GET_CODE ( XEXP ( XEXP ( x , 1 ) , 0 ) ) == REG && GET_MODE ( XEXP ( XEXP ( x , 1 ) , 0 ) ) == HImode ) ) { rtx temp = gen_reg_rtx ( Pmode ) ; rtx val = force_operand ( XEXP ( x , 0 ) , 0 ) ; emit_move_insn ( temp , val ) ; COPY_ONCE ( x ) ; XEXP ( x , 0 ) = temp ; if ( TARGET_COLDFIRE_FPU && GET_MODE_CLASS ( mode ) == MODE_FLOAT && GET_CODE ( XEXP ( x , 1 ) ) == REG ) x = force_operand ( x , 0 ) ; } } return x ; } </s>

Convert X to a legitimate address and return it if successful . Otherwise return X . For the 68000 , we handle X+REG by loading X into a register R and using R+REG . R will go in an address reg and indexing will be used . However , if REG is a broken-out memory address or multiplication , nothing needs to be done because REG can certainly go in an address reg .


<s> std :: pair < unsigned , const TargetRegisterClass * > TL45TargetLowering :: getRegForInlineAsmConstraint ( const TargetRegisterInfo * TRI , StringRef Constraint , MVT VT ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { case 'r' : return std :: make_pair ( 0U , & TL45 :: GRRegsRegClass ) ; default : break ; } } Register XRegFromAlias = StringSwitch < Register > ( Constraint . lower ( ) ) . Cases ( "{zero}" , "{r0}" , TL45 :: r0 ) . Case ( "{r1}" , TL45 :: r1 ) . Case ( "{r2}" , TL45 :: r2 ) . Case ( "{r3}" , TL45 :: r3 ) . Case ( "{r4}" , TL45 :: r4 ) . Case ( "{r5}" , TL45 :: r5 ) . Case ( "{r6}" , TL45 :: r6 ) . Case ( "{r7}" , TL45 :: r7 ) . Case ( "{r8}" , TL45 :: r8 ) . Case ( "{r9}" , TL45 :: r9 ) . Case ( "{r10}" , TL45 :: r10 ) . Case ( "{r11}" , TL45 :: r11 ) . Case ( "{r12}" , TL45 :: r12 ) . Case ( "{r13}" , TL45 :: r13 ) . Cases ( "{bp}" , "{r14}" , TL45 :: bp ) . Cases ( "{sp}" , "{r15}" , TL45 :: sp ) . Default ( TL45 :: NoRegister ) ; if ( XRegFromAlias != TL45 :: NoRegister ) return std :: make_pair ( XRegFromAlias , & TL45 :: GRRegsRegClass ) ; return TargetLowering :: getRegForInlineAsmConstraint ( TRI , Constraint , VT ) ; } </s>

Given a physical register constraint ( e.g .


<s> void JVMTargetLowering :: finalizeLowering ( MachineFunction & MF ) const { auto & MRI = MF . getRegInfo ( ) ; MRI . freezeReservedRegs ( MF ) ; } </s>


<s> void NVPTXPassConfig :: addIRPasses ( ) { disablePass ( & PrologEpilogCodeInserterID ) ; disablePass ( & MachineCopyPropagationID ) ; disablePass ( & BranchFolderPassID ) ; disablePass ( & TailDuplicateID ) ; TargetPassConfig :: addIRPasses ( ) ; addPass ( createGenericToNVVMPass ( ) ) ; } </s>

Add common target configurable passes that perform LLVM IR to IR transforms following machine independent optimization .


<s> const char * AVRTargetLowering :: getTargetNodeName ( unsigned Opcode ) const { case AVRISD :: name : \ return # name switch ( Opcode ) { default : return nullptr ; NODE ( RET_FLAG ) ; NODE ( RETI_FLAG ) ; NODE ( CALL ) ; NODE ( WRAPPER ) ; NODE ( LSL ) ; NODE ( LSR ) ; NODE ( ROL ) ; NODE ( ROR ) ; NODE ( ASR ) ; NODE ( LSLLOOP ) ; NODE ( LSRLOOP ) ; NODE ( ROLLOOP ) ; NODE ( RORLOOP ) ; NODE ( ASRLOOP ) ; NODE ( BRCOND ) ; NODE ( CMP ) ; NODE ( CMPC ) ; NODE ( TST ) ; NODE ( SELECT_CC ) ; } </s>

getTargetNodeName - This method returns the name of a target specific


<s> static void add_compiler_branch_island ( tree label_name , tree function_name , int line_number ) { branch_island bi = { function_name , label_name , line_number } ; vec_safe_push ( branch_islands , bi ) ; } </s>

Remember to generate a branch island for far calls to the given function .


<s> static bool xtensa_function_value_regno_p ( const unsigned int regno ) { return IN_RANGE ( regno , GP_RETURN_FIRST , GP_RETURN_LAST ) ; } </s>

Worker function TARGET_FUNCTION_VALUE_REGNO_P .


<s> static bool arm_slowmul_rtx_costs ( rtx x , int code , int outer_code , int * total ) { enum machine_mode mode = GET_MODE ( x ) ; if ( TARGET_THUMB ) { * total = thumb_rtx_costs ( x , code , outer_code ) ; return true ; } switch ( code ) { case MULT : if ( GET_MODE_CLASS ( mode ) == MODE_FLOAT || mode == DImode ) { * total = 30 ; return true ; } if ( GET_CODE ( XEXP ( x , 1 ) ) == CONST_INT ) { unsigned HOST_WIDE_INT i = ( INTVAL ( XEXP ( x , 1 ) ) & ( unsigned HOST_WIDE_INT ) 0xffffffff ) ; int cost , const_ok = const_ok_for_arm ( i ) ; int j , booth_unit_size ; cost = const_ok ? 4 : 8 ; booth_unit_size = 2 ; for ( j = 0 ; i && j < 32 ; j += booth_unit_size ) { i >>= booth_unit_size ; cost += 2 ; } * total = cost ; return true ; } * total = 30 + ( REG_OR_SUBREG_REG ( XEXP ( x , 0 ) ) ? 0 : 4 ) + ( REG_OR_SUBREG_REG ( XEXP ( x , 1 ) ) ? 0 : 4 ) ; return true ; default : * total = arm_rtx_costs_1 ( x , code , outer_code ) ; return true ; } } </s>

RTX costs for cores with a slow MUL implementation . Thumb-2 is not supported on any `` slowmul '' cores , so it can be ignored .


<s> bool XCoreAsmPrinter :: doInitialization ( Module & M ) { bool Result = AsmPrinter :: doInitialization ( M ) ; DW = getAnalysisIfAvailable < DwarfWriter > ( ) ; return Result ; } </s>

Set up the AsmPrinter when we are working on a new module .


<s> bool GCNPassConfig :: addInstSelector ( ) { AMDGPUPassConfig :: addInstSelector ( ) ; addPass ( createSILowerI1CopiesPass ( ) ) ; addPass ( createSIFixSGPRCopiesPass ( * TM ) ) ; addPass ( createSIFoldOperandsPass ( ) ) ; return false ; } </s>

addInstSelector - This method should install an instruction selector pass , which converts from LLVM code to machine instructions .


This function is used to print CPU tuning information as comment in assembler file . Pointers are not printed for now .


<s>
PPC
::
Predicate
PPC
::
getSwappedPredicate
(
PPC
::
Predicate
Opcode
)
{
switch
(
Opcode
)
{
case
PPC
::
PRED_EQ
:
return
PPC
::
PRED_EQ
;
case
PPC
::
PRED_NE
:
return
PPC
::
PRED_NE
;
case
PPC
::
PRED_LT
:
return
PPC
::
PRED_GT
;
case
PPC
::
PRED_GE
:
return
PPC
::
PRED_LE
;
case
PPC
::
PRED_GT
:
return
PPC
::
PRED_LT
;
case
PPC
::
PRED_LE
:
return
PPC
::
PRED_GE
;
case
PPC
::
PRED_NU
:
return
PPC
::
PRED_NU
;
case
PPC
::
PRED_UN
:
return
PPC
::
PRED_UN
;
case
PPC
::
PRED_EQ_MINUS
:
return
PPC
::
PRED_EQ_MINUS
;
case
PPC
::
PRED_NE_MINUS
:
return
PPC
::
PRED_NE_MINUS
;
case
PPC
::
PRED_LT_MINUS
:
return
PPC
::
PRED_GT_MINUS
;
case
PPC
::
PRED_GE_MINUS
:
return
PPC
::
PRED_LE_MINUS
;
case
PPC
::
PRED_GT_MINUS
:
return
PPC
::
PRED_LT_MINUS
;
case
PPC
::
PRED_LE_MINUS
:
return
PPC
::
PRED_GE_MINUS
;
case
PPC
::
PRED_NU_MINUS
:
return
PPC
::
PRED_NU_MINUS
;
case
PPC
::
PRED_UN_MINUS
:
return
PPC
::
PRED_UN_MINUS
;
case
PPC
::
PRED_EQ_PLUS
:
return
PPC
::
PRED_EQ_PLUS
;
case
PPC
::
PRED_NE_PLUS
:
return
PPC
::
PRED_NE_PLUS
;
case
PPC
::
PRED_LT_PLUS
:
return
PPC
::
PRED_GT_PLUS
;
case
PPC
::
PRED_GE_PLUS
:
return
PPC
::
PRED_LE_PLUS
;
case
PPC
::
PRED_GT_PLUS
:
return
PPC
::
PRED_LT_PLUS
;
case
PPC
::
PRED_LE_PLUS
:
return
PPC
::
PRED_GE_PLUS
;
case
PPC
::
PRED_NU_PLUS
:
return
PPC
::
PRED_NU_PLUS
;
case
PPC
::
PRED_UN_PLUS
:
return
PPC
::
PRED_UN_PLUS
;
}
llvm_unreachable
(
"Unknown PPC branch opcode!"
)
;
}
</s>

This is a static version that you can use without an instruction available .


<s>
void
X86InstrInfo
::
copyPhysReg
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
MI
,
DebugLoc
DL
,
unsigned
DestReg
,
unsigned
SrcReg
,
bool
KillSrc
)
const
{
unsigned
Opc
=
0
;
if
(
X86
::
GR64RegClass
.
contains
(
DestReg
,
SrcReg
)
)
Opc
=
X86
::
MOV64rr
;
else
if
(
X86
::
GR32RegClass
.
contains
(
DestReg
,
SrcReg
)
)
Opc
=
X86
::
MOV32rr
;
else
if
(
X86
::
GR16RegClass
.
contains
(
DestReg
,
SrcReg
)
)
Opc
=
X86
::
MOV16rr
;
else
if
(
X86
::
GR8RegClass
.
contains
(
DestReg
,
SrcReg
)
)
{
if
(
(
isHReg
(
DestReg
)
||
isHReg
(
SrcReg
)
)
&&
TM
.
getSubtarget
<
X86Subtarget
>
(
)
.
is64Bit
(
)
)
Opc
=
X86
::
MOV8rr_NOREX
;
else
Opc
=
X86
::
MOV8rr
;
}
else
if
(
X86
::
VR128RegClass
.
contains
(
DestReg
,
SrcReg
)
)
Opc
=
X86
::
MOVAPSrr
;
else
if
(
X86
::
VR64RegClass
.
contains
(
DestReg
,
SrcReg
)
)
Opc
=
X86
::
MMX_MOVQ64rr
;
else
Opc
=
CopyToFromAsymmetricReg
(
DestReg
,
SrcReg
)
;
if
(
Opc
)
{
BuildMI
(
MBB
,
MI
,
DL
,
get
(
Opc
)
,
DestReg
)
.
addReg
(
SrcReg
,
getKillRegState
(
KillSrc
)
)
;
return
;
}
if
(
SrcReg
==
X86
::
EFLAGS
)
{
if
(
X86
::
GR64RegClass
.
contains
(
DestReg
)
)
{
BuildMI
(
MBB
,
MI
,
DL
,
get
(
X86
::
PUSHF64
)
)
;
BuildMI
(
MBB
,
MI
,
DL
,
get
(
X86
::
POP64r
)
,
DestReg
)
;
return
;
}
else
if
(
X86
::
GR32RegClass
.
contains
(
DestReg
)
)
{
BuildMI
(
MBB
,
MI
,
DL
,
get
(
X86
::
PUSHF32
)
)
;
BuildMI
(
MBB
,
MI
,
DL
,
get
(
X86
::
POP32r
)
,
DestReg
)
;
return
;
}
}
if
(
DestReg
==
X86
::
EFLAGS
)
{
if
(
X86
::
GR64RegClass
.
contains
(
SrcReg
)
)
{
BuildMI
(
MBB
,
MI
,
DL
,
get
(
X86
::
PUSH64r
)
)
.
addReg
(
SrcReg
,
getKillRegState
(
KillSrc
)
)
;
BuildMI
(
MBB
,
MI
,
DL
,
get
(
X86
::
POPF64
)
)
;
return
;
}
else
if
(
X86
::
GR32RegClass
.
contains
(
SrcReg
)
)
{
BuildMI
(
MBB
,
MI
,
DL
,
get
(
X86
::
PUSH32r
)
)
.
addReg
(
SrcReg
,
getKillRegState
(
KillSrc
)
)
;
BuildMI
(
MBB
,
MI
,
DL
,
get
(
X86
::
POPF32
)
)
;
return
;
}
}
DEBUG
(
dbgs
(
)
<<
"Cannot copy "
<<
RI
.
getName
(
SrcReg
)
<<
" to "
<<
RI
.
getName
(
DestReg
)
<<
'\n'
)
;
llvm_unreachable
(
"Cannot emit physreg copy instruction"
)
;
}
</s>


<s> FastISel * X86TargetLowering :: createFastISel ( FunctionLoweringInfo & funcInfo ) const { return X86 :: createFastISel ( funcInfo ) ; } </s>

This method returns a target specific FastISel object , or null if the target does not support `` fast '' ISel .


<s> void Z80PassConfig :: addPreEmitPass ( ) { } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s> static void hwloop_fail ( hwloop_info loop ) { rtx insn = loop -> loop_end ; if ( DPREG_P ( loop -> iter_reg ) ) { rtx insn , test ; emit_insn_before ( gen_addsi3 ( loop -> iter_reg , loop -> iter_reg , constm1_rtx ) , loop -> loop_end ) ; test = gen_rtx_NE ( VOIDmode , loop -> iter_reg , const0_rtx ) ; insn = emit_jump_insn_before ( gen_cbranchsi4 ( test , loop -> iter_reg , const0_rtx , loop -> start_label ) , loop -> loop_end ) ; JUMP_LABEL ( insn ) = loop -> start_label ; LABEL_NUSES ( loop -> start_label ) ++ ; delete_insn ( loop -> loop_end ) ; } else { splitting_loops = 1 ; try_split ( PATTERN ( insn ) , insn , 1 ) ; splitting_loops = 0 ; } } </s>

A callback for the hw-doloop pass . Called when a loop we have discovered turns out not to be optimizable ; we have to split the doloop_end pattern into a subtract and a test .


<s> bool VideocoreAsmParser :: ParseDirective ( AsmToken DirectiveID ) { return true ; } </s>

ParseDirective - Parse a target specific assembler directive This method is deprecated , use 'parseDirective ' instead .


<s>
bool
X86AsmParser
::
ParseDirective
(
AsmToken
DirectiveID
)
{
MCAsmParser
&
Parser
=
getParser
(
)
;
StringRef
IDVal
=
DirectiveID
.
getIdentifier
(
)
;
if
(
IDVal
==
".word"
)
return
ParseDirectiveWord
(
2
,
DirectiveID
.
getLoc
(
)
)
;
else
if
(
IDVal
.
startswith
(
".code"
)
)
return
ParseDirectiveCode
(
IDVal
,
DirectiveID
.
getLoc
(
)
)
;
else
if
(
IDVal
.
startswith
(
".att_syntax"
)
)
{
if
(
getLexer
(
)
.
isNot
(
AsmToken
::
EndOfStatement
)
)
{
if
(
Parser
.
getTok
(
)
.
getString
(
)
==
"prefix"
)
Parser
.
Lex
(
)
;
else
if
(
Parser
.
getTok
(
)
.
getString
(
)
==
"noprefix"
)
return
Error
(
DirectiveID
.
getLoc
(
)
,
"'.att_syntax noprefix' is not "
"supported: registers must have a "
"'%' prefix in .att_syntax"
)
;
}
getParser
(
)
.
setAssemblerDialect
(
0
)
;
return
false
;
}
else
if
(
IDVal
.
startswith
(
".intel_syntax"
)
)
{
getParser
(
)
.
setAssemblerDialect
(
1
)
;
if
(
getLexer
(
)
.
isNot
(
AsmToken
::
EndOfStatement
)
)
{
if
(
Parser
.
getTok
(
)
.
getString
(
)
==
"noprefix"
)
Parser
.
Lex
(
)
;
else
if
(
Parser
.
getTok
(
)
.
getString
(
)
==
"prefix"
)
return
Error
(
DirectiveID
.
getLoc
(
)
,
"'.intel_syntax prefix' is not "
"supported: registers must not have "
"a '%' prefix in .intel_syntax"
)
;
}
return
false
;
}
return
true
;
}
</s>


<s> bool ARMSubtarget :: enablePostRAScheduler ( ) const { if ( disablePostRAScheduler ( ) ) return false ; return ! isThumb1Only ( ) ; } </s>

True if the subtarget should run a scheduler after register allocation .


<s> unsigned AlphaRegisterInfo :: getRARegister ( ) const { return Alpha :: R26 ; } </s>

This method should return the register where the return address can be found .


"Can't load this register from stack slot"

Load the specified register of the given register class from the specified stack frame index .


<s> virtual bool requiresFrameIndexScavenging ( const MachineFunction & MF ) const { return false ; } </s>

Returns true if the target requires post PEI scavenging of registers for materializing frame index constants .


<s>
static
void
printPCRelImm
(
X86AsmPrinter
&
P
,
const
MachineInstr
*
MI
,
unsigned
OpNo
,
raw_ostream
&
O
)
{
const
MachineOperand
&
MO
=
MI
->
getOperand
(
OpNo
)
;
switch
(
MO
.
getType
(
)
)
{
default
:
llvm_unreachable
(
"Unknown pcrel immediate operand"
)
;
case
MachineOperand
::
MO_Register
:
printOperand
(
P
,
MI
,
OpNo
,
O
)
;
return
;
case
MachineOperand
::
MO_Immediate
:
O
<<
MO
.
getImm
(
)
;
return
;
case
MachineOperand
::
MO_GlobalAddress
:
printSymbolOperand
(
P
,
MO
,
O
)
;
return
;
}
}
</s>


<s> static void insert_wic ( void ) { rtx_insn * insn ; int i , j ; basic_block bb , prev = 0 ; rtx branch_target = 0 ; shorten_branches ( get_insns ( ) ) ; for ( i = 0 ; i < n_basic_blocks_for_fn ( cfun ) - 1 ; i ++ ) { edge e ; edge_iterator ei ; bool simple_loop = false ; bb = BASIC_BLOCK_FOR_FN ( cfun , i ) ; if ( bb == NULL ) continue ; if ( ( prev != 0 ) && ( prev != bb ) ) continue ; else prev = 0 ; FOR_EACH_EDGE ( e , ei , bb -> preds ) if ( e -> src == bb ) { simple_loop = true ; prev = e -> dest ; break ; } for ( insn = BB_END ( bb ) ; insn ; insn = PREV_INSN ( insn ) ) { if ( INSN_P ( insn ) && ! simple_loop && CALL_P ( insn ) ) { if ( ( branch_target = get_branch_target ( insn ) ) ) insert_wic_for_ilb_runout ( next_active_insn ( next_active_insn ( insn ) ) ) ; } if ( insn == BB_HEAD ( bb ) ) break ; } } } </s>

Insert instruction prefetch instruction at the fall through path of the function call .


<s>
unsigned
SparcMCCodeEmitter
::
getMachineOpValue
(
const
MCInst
&
MI
,
const
MCOperand
&
MO
,
SmallVectorImpl
<
MCFixup
>
&
Fixups
,
const
MCSubtargetInfo
&
STI
)
const
{
if
(
MO
.
isReg
(
)
)
return
Ctx
.
getRegisterInfo
(
)
->
getEncodingValue
(
MO
.
getReg
(
)
)
;
if
(
MO
.
isImm
(
)
)
return
MO
.
getImm
(
)
;
assert
(
MO
.
isExpr
(
)
)
;
const
MCExpr
*
Expr
=
MO
.
getExpr
(
)
;
if
(
const
SparcMCExpr
*
SExpr
=
dyn_cast
<
SparcMCExpr
>
(
Expr
)
)
{
MCFixupKind
Kind
=
(
MCFixupKind
)
SExpr
->
getFixupKind
(
)
;
Fixups
.
push_back
(
MCFixup
::
Create
(
0
,
Expr
,
Kind
)
)
;
return
0
;
}
int64_t
Res
;
if
(
Expr
->
EvaluateAsAbsolute
(
Res
)
)
return
Res
;
llvm_unreachable
(
"Unhandled expression!"
)
;
return
0
;
}
</s>

getMachineOpValue - Return binary encoding of operand .


<s>
static
rtx
alpha_expand_builtin
(
tree
exp
,
rtx
target
,
rtx
subtarget
ATTRIBUTE_UNUSED
,
enum
machine_mode
mode
ATTRIBUTE_UNUSED
,
int
ignore
ATTRIBUTE_UNUSED
)
{
tree
fndecl
=
TREE_OPERAND
(
TREE_OPERAND
(
exp
,
0
)
,
0
)
;
unsigned
int
fcode
=
DECL_FUNCTION_CODE
(
fndecl
)
;
tree
arglist
=
TREE_OPERAND
(
exp
,
1
)
;
enum
insn_code
icode
;
rtx
op
[
MAX_ARGS
]
,
pat
;
int
arity
;
bool
nonvoid
;
if
(
fcode
>=
ALPHA_BUILTIN_max
)
internal_error
(
"bad builtin fcode"
)
;
icode
=
code_for_builtin
[
fcode
]
;
if
(
icode
==
0
)
internal_error
(
"bad builtin fcode"
)
;
nonvoid
=
TREE_TYPE
(
TREE_TYPE
(
fndecl
)
)
!=
void_type_node
;
for
(
arglist
=
TREE_OPERAND
(
exp
,
1
)
,
arity
=
0
;
arglist
;
arglist
=
TREE_CHAIN
(
arglist
)
,
arity
++
)
{
const
struct
insn_operand_data
*
insn_op
;
tree
arg
=
TREE_VALUE
(
arglist
)
;
if
(
arg
==
error_mark_node
)
return
NULL_RTX
;
if
(
arity
>
MAX_ARGS
)
return
NULL_RTX
;
insn_op
=
&
insn_data
[
icode
]
.
operand
[
arity
+
nonvoid
]
;
op
[
arity
]
=
expand_expr
(
arg
,
NULL_RTX
,
insn_op
->
mode
,
0
)
;
if
(
!
(
*
insn_op
->
predicate
)
(
op
[
arity
]
,
insn_op
->
mode
)
)
op
[
arity
]
=
copy_to_mode_reg
(
insn_op
->
mode
,
op
[
arity
]
)
;
}
if
(
nonvoid
)
{
enum
machine_mode
tmode
=
insn_data
[
icode
]
.
operand
[
0
]
.
mode
;
if
(
!
target
||
GET_MODE
(
target
)
!=
tmode
||
!
(
*
insn_data
[
icode
]
.
operand
[
0
]
.
predicate
)
(
target
,
tmode
)
)
target
=
gen_reg_rtx
(
tmode
)
;
}
switch
(
arity
)
{
case
0
:
pat
=
GEN_FCN
(
icode
)
(
target
)
;
break
;
case
1
:
if
(
nonvoid
)
pat
=
GEN_FCN
(
icode
)
(
target
,
op
[
0
]
)
;
else
pat
=
GEN_FCN
(
icode
)
(
op
[
0
]
)
;
break
;
case
2
:
pat
=
GEN_FCN
(
icode
)
(
target
,
op
[
0
]
,
op
[
1
]
)
;
break
;
default
:
gcc_unreachable
(
)
;
}
if
(
!
pat
)
return
NULL_RTX
;
emit_insn
(
pat
)
;
if
(
nonvoid
)
return
target
;
else
return
const0_rtx
;
}
</s>

Expand an expression EXP that calls a built-in function , with result going to TARGET if that 's convenient ( and in mode MODE if that 's convenient ) . SUBTARGET may be used as the target for computing one of EXP 's operands . IGNORE is nonzero if the value is to be ignored .


<s> void mips_expand_prologue ( void ) { HOST_WIDE_INT size ; if ( cfun -> machine -> global_pointer > 0 ) REGNO ( pic_offset_table_rtx ) = cfun -> machine -> global_pointer ; size = compute_frame_size ( get_frame_size ( ) ) ; if ( ( cfun -> machine -> frame . mask | cfun -> machine -> frame . fmask ) != 0 ) { HOST_WIDE_INT step1 ; step1 = MIN ( size , MIPS_MAX_FIRST_STACK_STEP ) ; RTX_FRAME_RELATED_P ( emit_insn ( gen_add3_insn ( stack_pointer_rtx , stack_pointer_rtx , GEN_INT ( - step1 ) ) ) ) = 1 ; size -= step1 ; mips_for_each_saved_reg ( size , mips_save_reg ) ; } if ( size > 0 ) { if ( SMALL_OPERAND ( - size ) ) RTX_FRAME_RELATED_P ( emit_insn ( gen_add3_insn ( stack_pointer_rtx , stack_pointer_rtx , GEN_INT ( - size ) ) ) ) = 1 ; else { emit_move_insn ( MIPS_PROLOGUE_TEMP ( Pmode ) , GEN_INT ( size ) ) ; if ( TARGET_MIPS16 ) { gcc_assert ( frame_pointer_needed ) ; emit_move_insn ( hard_frame_pointer_rtx , stack_pointer_rtx ) ; emit_insn ( gen_sub3_insn ( hard_frame_pointer_rtx , hard_frame_pointer_rtx , MIPS_PROLOGUE_TEMP ( Pmode ) ) ) ; emit_move_insn ( stack_pointer_rtx , hard_frame_pointer_rtx ) ; } else emit_insn ( gen_sub3_insn ( stack_pointer_rtx , stack_pointer_rtx , MIPS_PROLOGUE_TEMP ( Pmode ) ) ) ; mips_set_frame_expr ( gen_rtx_SET ( VOIDmode , stack_pointer_rtx , plus_constant ( stack_pointer_rtx , - size ) ) ) ; } } if ( frame_pointer_needed ) { if ( TARGET_MIPS16 && cfun -> machine -> frame . args_size != 0 ) { rtx offset = GEN_INT ( cfun -> machine -> frame . args_size ) ; if ( SMALL_OPERAND ( cfun -> machine -> frame . args_size ) ) RTX_FRAME_RELATED_P ( emit_insn ( gen_add3_insn ( hard_frame_pointer_rtx , stack_pointer_rtx , offset ) ) ) = 1 ; else { emit_move_insn ( MIPS_PROLOGUE_TEMP ( Pmode ) , offset ) ; emit_move_insn ( hard_frame_pointer_rtx , stack_pointer_rtx ) ; emit_insn ( gen_add3_insn ( hard_frame_pointer_rtx , hard_frame_pointer_rtx , MIPS_PROLOGUE_TEMP ( Pmode ) ) ) ; mips_set_frame_expr ( gen_rtx_SET ( VOIDmode , hard_frame_pointer_rtx , plus_constant ( stack_pointer_rtx , cfun -> machine -> frame . args_size ) ) ) ; } } else RTX_FRAME_RELATED_P ( emit_move_insn ( hard_frame_pointer_rtx , stack_pointer_rtx ) ) = 1 ; } if ( TARGET_ABICALLS && ! TARGET_NEWABI && ! current_function_is_leaf ) emit_insn ( gen_cprestore ( GEN_INT ( current_function_outgoing_args_size ) ) ) ; mips_emit_loadgp ( ) ; if ( current_function_profile ) emit_insn ( gen_blockage ( ) ) ; } </s>

Expand the prologue into a bunch of separate insns .


<s> int simd_immediate_valid_for_move ( rtx op , machine_mode mode , rtx * modconst , int * elementwidth ) { rtx tmpconst ; int tmpwidth ; int retval = simd_valid_immediate ( op , mode , 0 , & tmpconst , & tmpwidth ) ; if ( retval == - 1 ) return 0 ; if ( modconst ) * modconst = tmpconst ; if ( elementwidth ) * elementwidth = tmpwidth ; return 1 ; } </s>

Return TRUE if rtx X is legal for use as either a Neon or MVE VMOV ( or , implicitly , VMVN ) immediate . Write back width per element to * ELEMENTWIDTH ( or zero for float elements ) , and a modified constant ( whatever should be output for a VMOV ) in * MODCONST . `` neon_immediate_valid_for_move '' function is modified to `` simd_immediate_valid_for_move '' as this function will be used both by neon and mve .


<s> bool isToken ( ) const override { return Kind == Token ; } </s>


<s> unsigned AMDGPUMCAsmInfo :: getMaxInstLength ( const MCSubtargetInfo * STI ) const { if ( ! STI || STI -> getTargetTriple ( ) . getArch ( ) == Triple :: r600 ) return MaxInstLength ; if ( STI -> getFeatureBits ( ) [ AMDGPU :: FeatureNSAEncoding ] ) return 20 ; if ( STI -> getFeatureBits ( ) [ AMDGPU :: FeatureVOP3Literal ] ) return 12 ; return 8 ; } </s>

Returns the maximum possible encoded instruction size in bytes .


<s> unsigned RV16KInstrInfo :: getInstSizeInBytes ( const MachineInstr & MI ) const { unsigned Opcode = MI . getOpcode ( ) ; switch ( Opcode ) { default : return get ( Opcode ) . getSize ( ) ; case TargetOpcode :: EH_LABEL : case TargetOpcode :: IMPLICIT_DEF : case TargetOpcode :: KILL : case TargetOpcode :: DBG_VALUE : return 0 ; case TargetOpcode :: INLINEASM : { const MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ; const auto & TM = static_cast < const RV16KTargetMachine & > ( MF . getTarget ( ) ) ; return getInlineAsmLength ( MI . getOperand ( 0 ) . getSymbolName ( ) , * TM . getMCAsmInfo ( ) ) ; } } } </s>

Returns the size in bytes of the specified MachineInstr , or ~0U when this function is not implemented by a target .


<s> void validate_condition_mode ( enum rtx_code code , machine_mode mode ) { gcc_assert ( ( GET_RTX_CLASS ( code ) == RTX_COMPARE || GET_RTX_CLASS ( code ) == RTX_COMM_COMPARE ) && GET_MODE_CLASS ( mode ) == MODE_CC ) ; gcc_assert ( ( code != GT && code != LT && code != GE && code != LE ) || mode != CCUNSmode ) ; gcc_assert ( ( code != GTU && code != LTU && code != GEU && code != LEU ) || mode == CCUNSmode ) ; gcc_assert ( mode == CCFPmode || ( code != ORDERED && code != UNORDERED && code != UNEQ && code != LTGT && code != UNGT && code != UNLT && code != UNGE && code != UNLE ) ) ; gcc_assert ( mode != CCFPmode || flag_finite_math_only || ( code != LE && code != GE && code != UNEQ && code != LTGT && code != UNGT && code != UNLT ) ) ; gcc_assert ( mode != CCEQmode || code == EQ || code == NE ) ; } </s>

A validation routine : say whether CODE , a condition code , and MODE match . The other alternatives either do n't make sense or should never be generated .


<s> static bool classof ( const Type * T ) { return T -> getTypeID ( ) == DXILPointerTyID ; } </s>

Methods for support type inquiry through isa , cast , and dyn_cast :


<s> int tls_symbolic_operand_1 ( rtx op , int size , int unspec ) { op = XEXP ( op , 0 ) ; if ( GET_CODE ( op ) != UNSPEC || XINT ( op , 1 ) != unspec ) return 0 ; op = XVECEXP ( op , 0 , 0 ) ; if ( GET_CODE ( op ) != SYMBOL_REF ) return 0 ; switch ( SYMBOL_REF_TLS_MODEL ( op ) ) { case TLS_MODEL_LOCAL_DYNAMIC : return unspec == UNSPEC_DTPREL && size == alpha_tls_size ; case TLS_MODEL_INITIAL_EXEC : return unspec == UNSPEC_TPREL && size == 64 ; case TLS_MODEL_LOCAL_EXEC : return unspec == UNSPEC_TPREL && size == alpha_tls_size ; default : gcc_unreachable ( ) ; } } </s>

Return true if OP is valid for a particular TLS relocation . We are already guaranteed that OP is a CONST .


<s> static bool mips_valid_pointer_mode ( enum machine_mode mode ) { return ( mode == SImode || ( TARGET_64BIT && mode == DImode ) ) ; } </s>


<s> void M88kPassConfig :: addPreLegalizeMachineIR ( ) { addPass ( createM88kPreLegalizerCombiner ( ) ) ; } </s>

This method may be implemented by targets that want to run passes immediately before legalization .


<s> bool HexagonBitSimplify :: runOnMachineFunction ( MachineFunction & MF ) { if ( skipFunction ( * MF . getFunction ( ) ) ) return false ; auto & HST = MF . getSubtarget < HexagonSubtarget > ( ) ; auto & HRI = * HST . getRegisterInfo ( ) ; auto & HII = * HST . getInstrInfo ( ) ; MDT = & getAnalysis < MachineDominatorTree > ( ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; bool Changed ; Changed = DeadCodeElimination ( MF , * MDT ) . run ( ) ; const HexagonEvaluator HE ( HRI , MRI , HII , MF ) ; BitTracker BT ( HE , MF ) ; DEBUG ( BT . trace ( true ) ) ; BT . run ( ) ; MachineBasicBlock & Entry = MF . front ( ) ; RegisterSet AIG ; ConstGeneration ImmG ( BT , HII , MRI ) ; Changed |= visitBlock ( Entry , ImmG , AIG ) ; RegisterSet ARE ; RedundantInstrElimination RIE ( BT , HII , MRI ) ; bool Ried = visitBlock ( Entry , RIE , ARE ) ; if ( Ried ) { Changed = true ; BT . run ( ) ; } RegisterSet ACG ; CopyGeneration CopyG ( BT , HII , HRI , MRI ) ; Changed |= visitBlock ( Entry , CopyG , ACG ) ; RegisterSet ACP ; CopyPropagation CopyP ( HRI , MRI ) ; Changed |= visitBlock ( Entry , CopyP , ACP ) ; Changed = DeadCodeElimination ( MF , * MDT ) . run ( ) || Changed ; BT . run ( ) ; RegisterSet ABS ; BitSimplification BitS ( BT , HII , HRI , MRI , MF ) ; Changed |= visitBlock ( Entry , BitS , ABS ) ; Changed = DeadCodeElimination ( MF , * MDT ) . run ( ) || Changed ; if ( Changed ) { for ( auto & B : MF ) for ( auto & I : B ) I . clearKillInfo ( ) ; DeadCodeElimination ( MF , * MDT ) . run ( ) ; } return Changed ; } </s>

runOnMachineFunction - Emit the function body .


<s> rtx rs6000_address_for_fpconvert ( rtx x ) { rtx addr ; gcc_assert ( MEM_P ( x ) ) ; addr = XEXP ( x , 0 ) ; if ( can_create_pseudo_p ( ) && ! legitimate_indirect_address_p ( addr , reload_completed ) && ! legitimate_indexed_address_p ( addr , reload_completed ) ) { if ( GET_CODE ( addr ) == PRE_INC || GET_CODE ( addr ) == PRE_DEC ) { rtx reg = XEXP ( addr , 0 ) ; HOST_WIDE_INT size = GET_MODE_SIZE ( GET_MODE ( x ) ) ; rtx size_rtx = GEN_INT ( ( GET_CODE ( addr ) == PRE_DEC ) ? - size : size ) ; gcc_assert ( REG_P ( reg ) ) ; emit_insn ( gen_add3_insn ( reg , reg , size_rtx ) ) ; addr = reg ; } else if ( GET_CODE ( addr ) == PRE_MODIFY ) { rtx reg = XEXP ( addr , 0 ) ; rtx expr = XEXP ( addr , 1 ) ; gcc_assert ( REG_P ( reg ) ) ; gcc_assert ( GET_CODE ( expr ) == PLUS ) ; emit_insn ( gen_add3_insn ( reg , XEXP ( expr , 0 ) , XEXP ( expr , 1 ) ) ) ; addr = reg ; } x = replace_equiv_address ( x , copy_addr_to_reg ( addr ) ) ; } return x ; } </s>

Given a memory reference , if it is not a reg or reg+reg addressing , convert to such a form to deal with memory reference instructions like STFIWX that only take reg+reg addressing .


<s> static bool isNot ( const MachineRegisterInfo & MRI , const MachineInstr & MI ) { if ( MI . getOpcode ( ) != TargetOpcode :: G_XOR ) return false ; auto ConstVal = getConstantVRegVal ( MI . getOperand ( 2 ) . getReg ( ) , MRI ) ; return ConstVal && * ConstVal == - 1 ; } </s>


<s> static rtx promote_duplicated_reg_to_size ( rtx val , int size_needed , int desired_align , int align ) { rtx promoted_val ; if ( TARGET_64BIT && ( size_needed > 4 || ( desired_align > align && desired_align > 4 ) ) ) promoted_val = promote_duplicated_reg ( DImode , val ) ; else if ( size_needed > 2 || ( desired_align > align && desired_align > 2 ) ) promoted_val = promote_duplicated_reg ( SImode , val ) ; else if ( size_needed > 1 || ( desired_align > align && desired_align > 1 ) ) promoted_val = promote_duplicated_reg ( HImode , val ) ; else promoted_val = val ; return promoted_val ; } </s>

Duplicate value VAL using promote_duplicated_reg into maximal size that will be needed by main loop copying SIZE_NEEDED chunks and prologue getting alignment from ALIGN to DESIRED_ALIGN .


<s> static bool frv_class_likely_spilled_p ( reg_class_t rclass ) { switch ( rclass ) { default : break ; case GR8_REGS : case GR9_REGS : case GR89_REGS : case FDPIC_FPTR_REGS : case FDPIC_REGS : case ICC_REGS : case FCC_REGS : case CC_REGS : case ICR_REGS : case FCR_REGS : case CR_REGS : case LCR_REG : case LR_REG : case SPR_REGS : case QUAD_ACC_REGS : case ACCG_REGS : return true ; } return false ; } </s>

A C expression whose value is nonzero if pseudos that have been assigned to registers of class CLASS would likely be spilled because registers of CLASS are needed for spill registers . The default value of this macro returns 1 if CLASS has exactly one register and zero otherwise . On most machines , this default should be used . Only define this macro to some other expression if pseudo allocated by ` local-alloc.c ' end up in memory because their hard registers were needed for spill registers . If this macro returns nonzero for those classes , those pseudos will only be allocated by ` global.c ' , which knows how to reallocate the pseudo to another register . If there would not be another register available for reallocation , you should not change the definition of this macro since the only effect of such a definition would be to slow down register allocation .


<s>
bool
NVPTXAsmPrinter
::
lowerOperand
(
const
MachineOperand
&
MO
,
MCOperand
&
MCOp
)
{
switch
(
MO
.
getType
(
)
)
{
default
:
llvm_unreachable
(
"unknown operand type"
)
;
case
MachineOperand
::
MO_Register
:
MCOp
=
MCOperand
::
createReg
(
encodeVirtualRegister
(
MO
.
getReg
(
)
)
)
;
break
;
case
MachineOperand
::
MO_Immediate
:
MCOp
=
MCOperand
::
createImm
(
MO
.
getImm
(
)
)
;
break
;
case
MachineOperand
::
MO_MachineBasicBlock
:
MCOp
=
MCOperand
::
createExpr
(
MCSymbolRefExpr
::
create
(
MO
.
getMBB
(
)
->
getSymbol
(
)
,
OutContext
)
)
;
break
;
case
MachineOperand
::
MO_ExternalSymbol
:
MCOp
=
GetSymbolRef
(
GetExternalSymbolSymbol
(
MO
.
getSymbolName
(
)
)
)
;
break
;
case
MachineOperand
::
MO_GlobalAddress
:
MCOp
=
GetSymbolRef
(
getSymbol
(
MO
.
getGlobal
(
)
)
)
;
break
;
case
MachineOperand
::
MO_FPImmediate
:
{
const
ConstantFP
*
Cnt
=
MO
.
getFPImm
(
)
;
APFloat
Val
=
Cnt
->
getValueAPF
(
)
;
switch
(
Cnt
->
getType
(
)
->
getTypeID
(
)
)
{
default
:
report_fatal_error
(
"Unsupported FP type"
)
;
break
;
case
Type
::
FloatTyID
:
MCOp
=
MCOperand
::
createExpr
(
NVPTXFloatMCExpr
::
createConstantFPSingle
(
Val
,
OutContext
)
)
;
break
;
case
Type
::
DoubleTyID
:
MCOp
=
MCOperand
::
createExpr
(
NVPTXFloatMCExpr
::
createConstantFPDouble
(
Val
,
OutContext
)
)
;
break
;
}
break
;
}
}
return
true
;
}
</s>

Wrapper for MCInstLowering.lowerOperand ( ) for the tblgen'erated pseudo lowering .

NVPTX
NVPTX
"unknown operand type"
"Unsupported FP type"
NVPTX
NVPTX


<s> registered_function & function_builder :: add_function ( const function_instance & instance , const char * name , tree fntype , tree attrs , uint64_t required_extensions , bool overloaded_p , bool placeholder_p ) { unsigned int code = vec_safe_length ( registered_functions ) ; code = ( code << AARCH64_BUILTIN_SHIFT ) | AARCH64_BUILTIN_SVE ; tree decl = placeholder_p ? integer_zero_node : simulate_builtin_function_decl ( input_location , name , fntype , code , NULL , attrs ) ; registered_function & rfn = * ggc_alloc < registered_function > ( ) ; rfn . instance = instance ; rfn . decl = decl ; rfn . required_extensions = required_extensions ; rfn . overloaded_p = overloaded_p ; vec_safe_push ( registered_functions , & rfn ) ; return rfn ; } </s>

Add a function called NAME with type FNTYPE and attributes ATTRS . INSTANCE describes what the function does .