<s>
void
GCNUpwardRPTracker
::
recede
(
const
MachineInstr
&
MI
)
{
assert
(
MRI
&&
"call reset first"
)
;
LastTrackedMI
=
&
MI
;
if
(
MI
.
isDebugValue
(
)
)
return
;
auto
const
RegUses
=
collectVirtualRegUses
(
MI
,
LIS
,
*
MRI
)
;
auto
AtMIPressure
=
CurPressure
;
for
(
const
auto
&
U
:
RegUses
)
{
auto
LiveMask
=
LiveRegs
[
U
.
RegUnit
]
;
AtMIPressure
.
inc
(
U
.
RegUnit
,
LiveMask
,
LiveMask
|
U
.
LaneMask
,
*
MRI
)
;
}
MaxPressure
=
max
(
AtMIPressure
,
MaxPressure
)
;
for
(
const
auto
&
MO
:
MI
.
defs
(
)
)
{
if
(
!
MO
.
isReg
(
)
||
!
TargetRegisterInfo
::
isVirtualRegister
(
MO
.
getReg
(
)
)
||
MO
.
isDead
(
)
)
continue
;
auto
Reg
=
MO
.
getReg
(
)
;
auto
I
=
LiveRegs
.
find
(
Reg
)
;
if
(
I
==
LiveRegs
.
end
(
)
)
continue
;
auto
&
LiveMask
=
I
->
second
;
auto
PrevMask
=
LiveMask
;
LiveMask
&=
~
getDefRegMask
(
MO
,
*
MRI
)
;
CurPressure
.
inc
(
Reg
,
PrevMask
,
LiveMask
,
*
MRI
)
;
if
(
LiveMask
.
(
)
)
LiveRegs
.
erase
(
I
)
;
}
for
(
const
auto
&
U
:
RegUses
)
{
auto
&
LiveMask
=
LiveRegs
[
U
.
RegUnit
]
;
auto
PrevMask
=
LiveMask
;
LiveMask
|=
U
.
LaneMask
;
CurPressure
.
inc
(
U
.
RegUnit
,
PrevMask
,
LiveMask
,
*
MRI
)
;
}
assert
(
CurPressure
==
getRegPressure
(
*
MRI
,
LiveRegs
)
)
;
}
</s>

Recede across the previous instruction .


<s> void MipsInstPrinter :: printInst ( const MCInst * MI , raw_ostream & O , StringRef Annot ) { switch ( MI -> getOpcode ( ) ) { default : break ; case Mips :: RDHWR : case Mips :: RDHWR64 : O << "\t.set\tpush\n" ; O << "\t.set\tmips32r2\n" ; } if ( ! printAliasInstr ( MI , O ) ) printInstruction ( MI , O ) ; printAnnotation ( O , Annot ) ; switch ( MI -> getOpcode ( ) ) { default : break ; case Mips :: RDHWR : case Mips :: RDHWR64 : O << "\n\t.set\tpop" ; } } </s>

Print the specified MCInst to the specified raw_ostream .


<s> static bool arc_must_save_register ( int regno , struct function * func ) { unsigned int fn_type = arc_compute_function_type ( func ) ; bool irq_auto_save_p = ( ( irq_ctrl_saved . irq_save_last_reg >= regno ) && ARC_AUTO_IRQ_P ( fn_type ) ) ; bool firq_auto_save_p = ARC_FAST_INTERRUPT_P ( fn_type ) ; switch ( rgf_banked_register_count ) { case 4 : firq_auto_save_p &= ( regno < 4 ) ; break ; case 8 : firq_auto_save_p &= ( ( regno < 4 ) || ( ( regno > 11 ) && ( regno < 16 ) ) ) ; break ; case 16 : firq_auto_save_p &= ( ( regno < 4 ) || ( ( regno > 9 ) && ( regno < 16 ) ) || ( ( regno > 25 ) && ( regno < 29 ) ) || ( ( regno > 29 ) && ( regno < 32 ) ) ) ; break ; case 32 : firq_auto_save_p &= ( regno != 29 ) && ( regno < 32 ) ; break ; default : firq_auto_save_p = false ; break ; } switch ( regno ) { case RETURN_ADDR_REGNUM : case STACK_POINTER_REGNUM : return false ; case HARD_FRAME_POINTER_REGNUM : if ( arc_frame_pointer_needed ( ) ) return false ; default : if ( df_regs_ever_live_p ( regno ) && ( ! call_used_regs [ regno ] || ARC_INTERRUPT_P ( fn_type ) ) && ! irq_auto_save_p && ! firq_auto_save_p ) return true ; } return false ; } </s>

Tell prologue and epilogue if register REGNO should be saved / restored . The return address , stack pointer and frame pointer are treated separately . Do n't consider them here . Addition for pic : The gp register needs to be saved if the current function changes it to access gotoff variables . FIXME : This will not be needed if we used some arbitrary register instead of r26 .


<s> Register PPCTargetLowering :: getExceptionSelectorRegister ( const Constant * PersonalityFn ) const { return Subtarget . isPPC64 ( ) ? PPC :: X4 : PPC :: R4 ; } </s>

If a physical register , this returns the register that receives the exception typeid on entry to a landing pad .


<s> static alias_set_type ix86_GOT_alias_set ( void ) { static alias_set_type set = - 1 ; if ( set == - 1 ) set = new_alias_set ( ) ; return set ; } </s>

Return an unique alias set for the GOT .


<s> static void mips_encode_section_info ( tree decl , rtx rtl , int first ) { default_encode_section_info ( decl , rtl , first ) ; if ( TREE_CODE ( decl ) == FUNCTION_DECL ) { rtx symbol = XEXP ( rtl , 0 ) ; tree type = TREE_TYPE ( decl ) ; if ( ( TARGET_LONG_CALLS && ! mips_near_type_p ( type ) ) || mips_far_type_p ( type ) ) SYMBOL_REF_FLAGS ( symbol ) |= SYMBOL_FLAG_LONG_CALL ; } } </s>

Set SYMBOL_REF_FLAGS for the SYMBOL_REF inside RTL , which belongs to DECL . FIRST is true if this is the first time handling this decl .


<s>
void
RISCVFrameLowering
::
emitPrologue
(
MachineFunction
&
MF
,
MachineBasicBlock
&
MBB
)
const
{
assert
(
&
MF
.
front
(
)
==
&
MBB
&&
"Shrink-wrapping not yet supported"
)
;
MachineFrameInfo
&
MFI
=
MF
.
getFrameInfo
(
)
;
auto
*
RVFI
=
MF
.
getInfo
<
RISCVMachineFunctionInfo
>
(
)
;
MachineBasicBlock
::
iterator
MBBI
=
MBB
.
begin
(
)
;
unsigned
FPReg
=
getFPReg
(
STI
)
;
unsigned
SPReg
=
getSPReg
(
STI
)
;
DebugLoc
DL
;
determineFrameLayout
(
MF
)
;
uint64_t
StackSize
=
MFI
.
getStackSize
(
)
;
if
(
StackSize
==
0
&&
!
MFI
.
adjustsStack
(
)
)
return
;
adjustReg
(
MBB
,
MBBI
,
DL
,
SPReg
,
SPReg
,
StackSize
,
MachineInstr
::
FrameSetup
)
;
const
std
::
vector
<
CalleeSavedInfo
>
&
CSI
=
MFI
.
getCalleeSavedInfo
(
)
;
std
::
advance
(
MBBI
,
CSI
.
size
(
)
)
;
if
(
hasFP
(
MF
)
)
adjustReg
(
MBB
,
MBBI
,
DL
,
FPReg
,
SPReg
,
StackSize
RVFI
->
getVarArgsSaveSize
(
)
,
MachineInstr
::
FrameSetup
)
;
}
</s>

emitProlog/emitEpilog - These methods insert prolog and epilog code into the function .

RISCV
RISCV
"Shrink-wrapping not yet supported"
RISCV
0


<s> bool AArch64TargetLowering :: isDesirableToCommuteWithShift ( const SDNode * N , CombineLevel Level ) const { N = N -> getOperand ( 0 ) . getNode ( ) ; EVT VT = N -> getValueType ( 0 ) ; if ( N -> getOpcode ( ) == ISD :: AND && ( VT == MVT :: i32 || VT == MVT :: i64 ) && isa < ConstantSDNode > ( N -> getOperand ( 1 ) ) ) { uint64_t TruncMask = N -> getConstantOperandVal ( 1 ) ; if ( isMask_64 ( TruncMask ) && N -> getOperand ( 0 ) . getOpcode ( ) == ISD :: SRL && isa < ConstantSDNode > ( N -> getOperand ( 0 ) -> getOperand ( 1 ) ) ) return false ; } return true ; } </s>

Return true if it is profitable to move this shift by a constant amount through its operand , adjusting any immediate operands as necessary to preserve semantics .


<s> BitVector R600RegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; const R600Subtarget & ST = MF . getSubtarget < R600Subtarget > ( ) ; const R600InstrInfo * TII = ST . getInstrInfo ( ) ; reserveRegisterTuples ( Reserved , R600 :: ZERO ) ; reserveRegisterTuples ( Reserved , R600 :: HALF ) ; reserveRegisterTuples ( Reserved , R600 :: ONE ) ; reserveRegisterTuples ( Reserved , R600 :: ONE_INT ) ; reserveRegisterTuples ( Reserved , R600 :: NEG_HALF ) ; reserveRegisterTuples ( Reserved , R600 :: NEG_ONE ) ; reserveRegisterTuples ( Reserved , R600 :: PV_X ) ; reserveRegisterTuples ( Reserved , R600 :: ALU_LITERAL_X ) ; reserveRegisterTuples ( Reserved , R600 :: ALU_CONST ) ; reserveRegisterTuples ( Reserved , R600 :: PREDICATE_BIT ) ; reserveRegisterTuples ( Reserved , R600 :: PRED_SEL_OFF ) ; reserveRegisterTuples ( Reserved , R600 :: PRED_SEL_ZERO ) ; reserveRegisterTuples ( Reserved , R600 :: PRED_SEL_ONE ) ; reserveRegisterTuples ( Reserved , R600 :: INDIRECT_BASE_ADDR ) ; for ( TargetRegisterClass :: iterator I = R600 :: R600_AddrRegClass . begin ( ) , E = R600 :: R600_AddrRegClass . end ( ) ; I != E ; ++ I ) { reserveRegisterTuples ( Reserved , * I ) ; } TII -> reserveIndirectRegisters ( Reserved , MF , * this ) ; return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


"X86 Support for protection of register spills"

getPassName - Return a nice clean name for a pass .


<s> bool m68k_matches_u_p ( rtx x ) { struct m68k_address address ; return ( m68k_legitimate_mem_p ( x , & address ) && address . code == UNKNOWN && address . base && address . offset && ! address . index ) ; } </s>

Return true if X matches the ' U ' constraint . It must be a base address with a constant offset and no index .


"LowerFormalArguments Unhandled argument type: "

This hook must be implemented to lower the incoming ( formal ) arguments , described by the Ins array , into the specified DAG .


<s>
MachineInstr
*
ARMBaseInstrInfo
::
optimizeSelect
(
MachineInstr
*
MI
,
bool
PreferFalse
)
const
{
assert
(
(
MI
->
getOpcode
(
)
==
ARM
::
MOVCCr
||
MI
->
getOpcode
(
)
==
ARM
::
t2MOVCCr
)
&&
"Unknown select instruction"
)
;
const
MachineRegisterInfo
&
MRI
=
MI
->
getParent
(
)
->
getParent
(
)
->
getRegInfo
(
)
;
MachineInstr
*
DefMI
=
canFoldIntoMOVCC
(
MI
->
getOperand
(
2
)
.
getReg
(
)
,
MRI
,
this
)
;
bool
Invert
=
!
DefMI
;
if
(
!
DefMI
)
DefMI
=
canFoldIntoMOVCC
(
MI
->
getOperand
(
1
)
.
getReg
(
)
,
MRI
,
this
)
;
if
(
!
DefMI
)
return
0
;
MachineInstrBuilder
NewMI
=
BuildMI
(
*
MI
->
getParent
(
)
,
MI
,
MI
->
getDebugLoc
(
)
,
DefMI
->
getDesc
(
)
,
MI
->
getOperand
(
0
)
.
getReg
(
)
)
;
const
MCInstrDesc
&
DefDesc
=
DefMI
->
getDesc
(
)
;
for
(
unsigned
i
=
1
,
e
=
DefDesc
.
getNumOperands
(
)
;
i
!=
e
&&
!
DefDesc
.
OpInfo
[
i
]
.
isPredicate
(
)
;
++
i
)
NewMI
.
addOperand
(
DefMI
->
getOperand
(
i
)
)
;
unsigned
CondCode
=
MI
->
getOperand
(
3
)
.
getImm
(
)
;
if
(
Invert
)
NewMI
.
addImm
(
ARMCC
::
getOppositeCondition
(
ARMCC
::
CondCodes
(
CondCode
)
)
)
;
else
NewMI
.
addImm
(
CondCode
)
;
NewMI
.
addOperand
(
MI
->
getOperand
(
4
)
)
;
if
(
NewMI
->
hasOptionalDef
(
)
)
AddDefaultCC
(
NewMI
)
;
MachineOperand
FalseReg
=
MI
->
getOperand
(
Invert
2
:
1
)
;
FalseReg
.
setImplicit
(
)
;
NewMI
->
addOperand
(
FalseReg
)
;
NewMI
->
tieOperands
(
0
,
NewMI
->
getNumOperands
(
)
1
)
;
DefMI
->
eraseFromParent
(
)
;
return
NewMI
;
}
</s>

Given a select instruction that was understood by analyzeSelect and returned Optimizable = true , attempt to optimize MI by merging it with one of its operands .


<s>
const
char
*
output_tst
(
rtx
operand
,
rtx
insn
)
{
rtx
temp
;
int
past_call
=
0
;
temp
=
PREV_INSN
(
insn
)
;
while
(
optimize
&&
temp
)
{
rtx
set
;
if
(
GET_CODE
(
temp
)
==
CODE_LABEL
||
GET_CODE
(
temp
)
==
JUMP_INSN
||
GET_CODE
(
temp
)
==
BARRIER
)
break
;
if
(
GET_CODE
(
temp
)
==
CALL_INSN
)
past_call
=
1
;
if
(
GET_CODE
(
temp
)
==
NOTE
)
{
temp
=
PREV_INSN
(
temp
)
;
continue
;
}
set
=
single_set
(
temp
)
;
if
(
!
set
)
{
temp
=
PREV_INSN
(
temp
)
;
continue
;
}
if
(
REG_P
(
SET_DEST
(
set
)
)
&&
SET_SRC
(
set
)
==
CONST0_RTX
(
GET_MODE
(
SET_DEST
(
set
)
)
)
&&
!
reg_set_between_p
(
SET_DEST
(
set
)
,
temp
,
insn
)
&&
(
REGNO_REG_CLASS
(
REGNO
(
SET_DEST
(
set
)
)
)
==
REGNO_REG_CLASS
(
REGNO
(
operand
)
)
)
&&
REGNO_REG_CLASS
(
REGNO
(
SET_DEST
(
set
)
)
)
!=
EXTENDED_REGS
&&
REGNO
(
SET_DEST
(
set
)
)
!=
REGNO
(
operand
)
&&
(
!
past_call
||
!
call_used_regs
[
REGNO
(
SET_DEST
(
set
)
)
]
)
)
{
rtx
xoperands
[
2
]
;
xoperands
[
0
]
=
operand
;
xoperands
[
1
]
=
SET_DEST
(
set
)
;
output_asm_insn
(
"cmp %1,%0"
,
xoperands
)
;
return
""
;
}
if
(
REGNO_REG_CLASS
(
REGNO
(
operand
)
)
==
EXTENDED_REGS
&&
REG_P
(
SET_DEST
(
set
)
)
&&
SET_SRC
(
set
)
==
CONST0_RTX
(
GET_MODE
(
SET_DEST
(
set
)
)
)
&&
!
reg_set_between_p
(
SET_DEST
(
set
)
,
temp
,
insn
)
&&
(
REGNO_REG_CLASS
(
REGNO
(
SET_DEST
(
set
)
)
)
!=
REGNO_REG_CLASS
(
REGNO
(
operand
)
)
)
&&
REGNO_REG_CLASS
(
REGNO
(
SET_DEST
(
set
)
)
)
==
EXTENDED_REGS
&&
REGNO
(
SET_DEST
(
set
)
)
!=
REGNO
(
operand
)
&&
(
!
past_call
||
!
call_used_regs
[
REGNO
(
SET_DEST
(
set
)
)
]
)
)
{
rtx
xoperands
[
2
]
;
xoperands
[
0
]
=
operand
;
xoperands
[
1
]
=
SET_DEST
(
set
)
;
output_asm_insn
(
"cmp %1,%0"
,
xoperands
)
;
return
""
;
}
temp
=
PREV_INSN
(
temp
)
;
}
return
"cmp 0,%0"
;
}
</s>


<s> void SIFrameLowering :: emitPrologue ( MachineFunction & MF , MachineBasicBlock & MBB ) const { const SIMachineFunctionInfo * FuncInfo = MF . getInfo < SIMachineFunctionInfo > ( ) ; if ( FuncInfo -> isEntryFunction ( ) ) { emitEntryFunctionPrologue ( MF , MBB ) ; return ; } const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const SISubtarget & ST = MF . getSubtarget < SISubtarget > ( ) ; const SIInstrInfo * TII = ST . getInstrInfo ( ) ; unsigned StackPtrReg = FuncInfo -> getStackPtrOffsetReg ( ) ; unsigned FramePtrReg = FuncInfo -> getFrameOffsetReg ( ) ; MachineBasicBlock :: iterator MBBI = MBB . begin ( ) ; DebugLoc DL ; bool NeedFP = hasFP ( MF ) ; if ( NeedFP ) { BuildMI ( MBB , MBBI , DL , TII -> get ( AMDGPU :: COPY ) , FramePtrReg ) . addReg ( StackPtrReg ) . setMIFlag ( MachineInstr :: FrameSetup ) ; } uint32_t NumBytes = MFI . getStackSize ( ) ; if ( NumBytes != 0 && hasSP ( MF ) ) { BuildMI ( MBB , MBBI , DL , TII -> get ( AMDGPU :: S_ADD_U32 ) , StackPtrReg ) . addReg ( StackPtrReg ) . addImm ( NumBytes * ST . getWavefrontSize ( ) ) . setMIFlag ( MachineInstr :: FrameSetup ) ; } } </s>

AMDGPU SI SI SI SI SI SI AMDGPU::COPY 0 AMDGPU::S_ADD_U32


<s>
bool
SILoadStoreOptimizer
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
if
(
skipFunction
(
*
MF
.
getFunction
(
)
)
)
return
false
;
const
SISubtarget
&
STM
=
MF
.
getSubtarget
<
SISubtarget
>
(
)
;
if
(
!
STM
.
loadStoreOptEnabled
(
)
)
return
false
;
TII
=
STM
.
getInstrInfo
(
)
;
TRI
=
&
TII
->
getRegisterInfo
(
)
;
MRI
=
&
MF
.
getRegInfo
(
)
;
AA
=
&
getAnalysis
<
AAResultsWrapperPass
>
(
)
.
getAAResults
(
)
;
DEBUG
(
dbgs
(
)
<<
"Running SILoadStoreOptimizer\n"
)
;
bool
Modified
=
false
;
for
(
MachineBasicBlock
&
MBB
:
MF
)
Modified
|=
optimizeBlock
(
MBB
)
;
return
Modified
;
}
</s>

runOnMachineFunction - Emit the function body .

AMDGPU
SI
SI
SI
"Running SILoadStoreOptimizer\n"


<s> bool PPCTargetLowering :: IsEligibleForTailCallOptimization ( SDValue Callee , CallingConv :: ID CalleeCC , bool isVarArg , const SmallVectorImpl < ISD :: InputArg > & Ins , SelectionDAG & DAG ) const { if ( ! GuaranteedTailCallOpt ) return false ; if ( isVarArg ) return false ; MachineFunction & MF = DAG . getMachineFunction ( ) ; CallingConv :: ID CallerCC = MF . getFunction ( ) -> getCallingConv ( ) ; if ( CalleeCC == CallingConv :: Fast && CallerCC == CalleeCC ) { for ( unsigned i = 0 ; i != Ins . size ( ) ; i ++ ) { ISD :: ArgFlagsTy Flags = Ins [ i ] . Flags ; if ( Flags . isByVal ( ) ) return false ; } if ( getTargetMachine ( ) . getRelocationModel ( ) != Reloc :: PIC_ ) return true ; if ( GlobalAddressSDNode * G = dyn_cast < GlobalAddressSDNode > ( Callee ) ) return G -> getGlobal ( ) -> hasHiddenVisibility ( ) || G -> getGlobal ( ) -> hasProtectedVisibility ( ) ; } return false ; } </s>

IsEligibleForTailCallOptimization - Check whether the call is eligible for tail call optimization .

PowerPC PPC ISD::InputArg 0 ISD::ArgFlagsTy


<s> TargetPassConfig * M680x0TargetMachine :: createPassConfig ( PassManagerBase & PM ) { return new M680x0PassConfig ( * this , PM ) ; } </s>

Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of CodeGen passes .


<s> MachineBasicBlock :: iterator F2003fFrameLowering :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { const F2003fInstrInfo & TII = * static_cast < const F2003fInstrInfo * > ( MF . getSubtarget ( ) . getInstrInfo ( ) ) ; MachineInstr & Old = * I ; DebugLoc DL = Old . getDebugLoc ( ) ; unsigned Amount = TII . getFrameSize ( Old ) ; if ( Amount != 0 ) { unsigned Opc = Old . getOpcode ( ) ; if ( Opc == F2003f :: ADJCALLSTACKDOWN ) { BuildMI ( MBB , I , DL , TII . get ( F2003f :: NTAri ) , F2003f :: F5 ) . addReg ( F2003f :: F5 ) . addImm ( Amount ) ; } else { assert ( Opc == F2003f :: ADJCALLSTACKUP ) ; BuildMI ( MBB , I , DL , TII . get ( F2003f :: ATAri ) , F2003f :: F5 ) . addReg ( F2003f :: F5 ) . addImm ( Amount ) ; } } return MBB . erase ( I ) ; } </s>

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .


<s> rtx rs6000_libcall_value ( machine_mode mode ) { unsigned int regno ; if ( TARGET_32BIT && TARGET_POWERPC64 && mode == DImode ) return rs6000_parallel_return ( mode , 2 , SImode , GP_ARG_RETURN , 1 ) ; if ( DECIMAL_FLOAT_MODE_P ( mode ) && TARGET_HARD_FLOAT && TARGET_FPRS ) regno = ( mode == TDmode ) ? FP_ARG_RETURN + 1 : FP_ARG_RETURN ; else if ( SCALAR_FLOAT_MODE_P ( mode ) && TARGET_HARD_FLOAT && TARGET_FPRS && ( ( TARGET_SINGLE_FLOAT && mode == SFmode ) || TARGET_DOUBLE_FLOAT ) ) regno = FP_ARG_RETURN ; else if ( ALTIVEC_OR_VSX_VECTOR_MODE ( mode ) && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI ) regno = ALTIVEC_ARG_RETURN ; else if ( COMPLEX_MODE_P ( mode ) && targetm . calls . split_complex_arg ) return rs6000_complex_function_value ( mode ) ; else if ( TARGET_E500_DOUBLE && TARGET_HARD_FLOAT && ( mode == DFmode || mode == DCmode || mode == TFmode || mode == TCmode ) ) return spe_build_register_parallel ( mode , GP_ARG_RETURN ) ; else regno = GP_ARG_RETURN ; return gen_rtx_REG ( mode , regno ) ; } </s>

Define how to find the value returned by a library function assuming the value has mode MODE .


<s> static bool aarch64_get_sve_pred_bits ( rtx_vector_builder & builder , rtx x ) { if ( GET_CODE ( x ) != CONST_VECTOR ) return false ; unsigned int factor = vector_element_size ( GET_MODE_NUNITS ( VNx16BImode ) , GET_MODE_NUNITS ( GET_MODE ( x ) ) ) ; unsigned int npatterns = CONST_VECTOR_NPATTERNS ( x ) * factor ; unsigned int nelts_per_pattern = CONST_VECTOR_NELTS_PER_PATTERN ( x ) ; builder . new_vector ( VNx16BImode , npatterns , nelts_per_pattern ) ; unsigned int nelts = const_vector_encoded_nelts ( x ) ; for ( unsigned int i = 0 ; i < nelts ; ++ i ) { rtx elt = CONST_VECTOR_ENCODED_ELT ( x , i ) ; if ( ! CONST_INT_P ( elt ) ) return false ; builder . quick_push ( elt ) ; for ( unsigned int j = 1 ; j < factor ; ++ j ) builder . quick_push ( const0_rtx ) ; } builder . finalize ( ) ; return true ; } </s>

Return true if predicate value X is a constant in which every element is a CONST_INT . When returning true , describe X in BUILDER as a VNx16BI value , i.e . as a predicate in which all bits are significant .


<s> bool isMachineVerifierClean ( ) const override { return false ; } </s>

Returns true if the target is expected to pass all machine verifier checks .


<s> void TeakFrameLowering :: emitPrologue ( MachineFunction & MF , MachineBasicBlock & MBB ) const { const TargetInstrInfo & TII = * MF . getSubtarget ( ) . getInstrInfo ( ) ; MachineBasicBlock :: iterator MBBI = MBB . begin ( ) ; DebugLoc dl = MBBI != MBB . end ( ) ? MBBI -> getDebugLoc ( ) : DebugLoc ( ) ; uint64_t StackSize = computeStackSize ( MF ) ; if ( ! StackSize ) return ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const std :: vector < CalleeSavedInfo > & CSI = MFI . getCalleeSavedInfo ( ) ; StackSize -= CSI . size ( ) * 2 ; if ( ! StackSize ) return ; BuildMI ( MBB , MBBI , dl , TII . get ( Teak :: PUSH_regnob16 ) , Teak :: R7 ) . setMIFlag ( MachineInstr :: FrameSetup ) ; BuildMI ( MBB , MBBI , dl , TII . get ( Teak :: MOV_regnobp016_regnob16 ) , Teak :: R7 ) . addReg ( Teak :: SP ) . setMIFlag ( MachineInstr :: FrameSetup ) ; BuildMI ( MBB , MBBI , dl , TII . get ( Teak :: ADDV_imm16_RegNoBRegs16 ) , Teak :: SP ) . addImm ( - ( StackSize >> 1 ) ) . addReg ( Teak :: SP ) . setMIFlag ( MachineInstr :: FrameSetup ) ; BuildMI ( MBB , MBBI , dl , TII . get ( Teak :: NOP ) ) . setMIFlag ( MachineInstr :: FrameSetup ) ; } </s>


<s> bool requiresRegisterScavenging ( const MachineFunction & MF ) const override { return true ; } </s>

Returns true if the target requires ( and can make use of ) the register scavenger .


<s> bool isFMAFasterThanFMulAndFAdd ( EVT ) const override { return true ; } </s>

Return true if an FMA operation is faster than a pair of fmul and fadd instructions .


<s> unsigned ARMFastISel :: fastEmitInst_rrr ( unsigned MachineInstOpcode , const TargetRegisterClass * RC , unsigned Op0 , bool Op0IsKill , unsigned Op1 , bool Op1IsKill , unsigned Op2 , bool Op2IsKill ) { unsigned ResultReg = createResultReg ( RC ) ; const MCInstrDesc & II = TII . get ( MachineInstOpcode ) ; Op0 = constrainOperandRegClass ( II , Op0 , 1 ) ; Op1 = constrainOperandRegClass ( II , Op1 , 2 ) ; Op2 = constrainOperandRegClass ( II , Op1 , 3 ) ; if ( II . getNumDefs ( ) >= 1 ) { AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , II , ResultReg ) . addReg ( Op0 , Op0IsKill * RegState :: Kill ) . addReg ( Op1 , Op1IsKill * RegState :: Kill ) . addReg ( Op2 , Op2IsKill * RegState :: Kill ) ) ; } else { AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , II ) . addReg ( Op0 , Op0IsKill * RegState :: Kill ) . addReg ( Op1 , Op1IsKill * RegState :: Kill ) . addReg ( Op2 , Op2IsKill * RegState :: Kill ) ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: COPY ) , ResultReg ) . addReg ( II . ImplicitDefs [ 0 ] ) ) ; } return ResultReg ; } </s>

Emit a MachineInstr with three register operands and a result register in the given register class .


<s> static void emitSPUpdate ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator & MBBI , unsigned StackPtr , int64_t NumBytes , bool Is64Bit , const TargetInstrInfo & TII ) { bool isSub = NumBytes < 0 ; uint64_t Offset = isSub ? - NumBytes : NumBytes ; unsigned Opc = isSub ? ( ( Offset < 128 ) ? ( Is64Bit ? X86 :: SUB64ri8 : X86 :: SUB32ri8 ) : ( Is64Bit ? X86 :: SUB64ri32 : X86 :: SUB32ri ) ) : ( ( Offset < 128 ) ? ( Is64Bit ? X86 :: ADD64ri8 : X86 :: ADD32ri8 ) : ( Is64Bit ? X86 :: ADD64ri32 : X86 :: ADD32ri ) ) ; uint64_t Chunk = ( 1LL << 31 ) - 1 ; DebugLoc DL = ( MBBI != MBB . end ( ) ? MBBI -> getDebugLoc ( ) : DebugLoc :: getUnknownLoc ( ) ) ; while ( Offset ) { uint64_t ThisVal = ( Offset > Chunk ) ? Chunk : Offset ; MachineInstr * MI = BuildMI ( MBB , MBBI , DL , TII . get ( Opc ) , StackPtr ) . addReg ( StackPtr ) . addImm ( ThisVal ) ; MI -> getOperand ( 3 ) . setIsDead ( ) ; Offset -= ThisVal ; } } </s>

Emit a series of instructions to increment / decrement the stack pointer by a constant value .


<s> bool PPCPassConfig :: addPreEmitPass ( ) { addPass ( createPPCBranchSelectionPass ( ) ) ; return false ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s> void ARMBaseRegisterInfo :: materializeFrameBaseRegister ( MachineBasicBlock * MBB , unsigned BaseReg , int FrameIdx , int64_t Offset ) const { ARMFunctionInfo * AFI = MBB -> getParent ( ) -> getInfo < ARMFunctionInfo > ( ) ; unsigned ADDriOpc = ! AFI -> isThumbFunction ( ) ? ARM :: ADDri : ( AFI -> isThumb1OnlyFunction ( ) ? ARM :: tADDrSPi : ARM :: t2ADDri ) ; MachineBasicBlock :: iterator Ins = MBB -> begin ( ) ; DebugLoc DL ; if ( Ins != MBB -> end ( ) ) DL = Ins -> getDebugLoc ( ) ; const MachineFunction & MF = * MBB -> getParent ( ) ; MachineRegisterInfo & MRI = MBB -> getParent ( ) -> getRegInfo ( ) ; const TargetInstrInfo & TII = * MF . getTarget ( ) . getInstrInfo ( ) ; const MCInstrDesc & MCID = TII . get ( ADDriOpc ) ; MRI . constrainRegClass ( BaseReg , TII . getRegClass ( MCID , 0 , this , MF ) ) ; MachineInstrBuilder MIB = AddDefaultPred ( BuildMI ( * MBB , Ins , DL , MCID , BaseReg ) . addFrameIndex ( FrameIdx ) . addImm ( Offset ) ) ; if ( ! AFI -> isThumb1OnlyFunction ( ) ) AddDefaultCC ( MIB ) ; } </s>

Insert defining instruction ( s ) for a pointer to FrameIdx before insertion point I .

ARM ARM ARM ARM ARM::ADDri ARM::tADDrSPi ARM::t2ADDri 0


<s> static rtx aarch64_emit_set_immediate ( rtx target , rtx_vector_builder & builder ) { rtx src = builder . build ( ) ; target = aarch64_target_reg ( target , GET_MODE ( src ) ) ; emit_insn ( gen_rtx_SET ( target , src ) ) ; return target ; } </s>

Return a register that contains the constant in BUILDER , given that the constant is a legitimate move operand . Use TARGET as the register if it is nonnull and convenient .


<s> static void s390_register_info_gprtofpr ( ) { int save_reg_slot = FPR0_REGNUM ; int i , j ; if ( ! TARGET_Z10 || ! TARGET_HARD_FLOAT || ! crtl -> is_leaf ) return ; for ( i = 15 ; i >= 6 ; i -- ) { if ( cfun_gpr_save_slot ( i ) == SAVE_SLOT_NONE ) continue ; while ( ( ! call_really_used_regs [ save_reg_slot ] || df_regs_ever_live_p ( save_reg_slot ) || cfun_fpr_save_p ( save_reg_slot ) ) && FP_REGNO_P ( save_reg_slot ) ) save_reg_slot ++ ; if ( ! FP_REGNO_P ( save_reg_slot ) ) { for ( j = 6 ; j <= 15 ; j ++ ) if ( FP_REGNO_P ( cfun_gpr_save_slot ( j ) ) ) cfun_gpr_save_slot ( j ) = SAVE_SLOT_STACK ; break ; } cfun_gpr_save_slot ( i ) = save_reg_slot ++ ; } } </s>

Update gpr_save_slots in the frame layout trying to make use of FPRs as GPR save slots . This is a helper routine of s390_register_info .


<s>
void
Thumb1InstrInfo
::
copyPhysReg
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
const
DebugLoc
&
DL
,
MCRegister
DestReg
,
MCRegister
SrcReg
,
bool
KillSrc
)
const
{
MachineFunction
&
MF
=
*
MBB
.
getParent
(
)
;
const
ARMSubtarget
&
st
=
MF
.
getSubtarget
<
ARMSubtarget
>
(
)
;
assert
(
ARM
::
GPRRegClass
.
contains
(
DestReg
,
SrcReg
)
&&
"Thumb1 can only copy GPR registers"
)
;
if
(
st
.
hasV6Ops
(
)
||
ARM
::
hGPRRegClass
.
contains
(
SrcReg
)
||
!
ARM
::
tGPRRegClass
.
contains
(
DestReg
)
)
BuildMI
(
MBB
,
I
,
DL
,
get
(
ARM
::
tMOVr
)
,
DestReg
)
.
addReg
(
SrcReg
,
getKillRegState
(
KillSrc
)
)
.
add
(
predOps
(
ARMCC
::
AL
)
)
;
else
{
const
TargetRegisterInfo
*
RegInfo
=
st
.
getRegisterInfo
(
)
;
if
(
MBB
.
computeRegisterLiveness
(
RegInfo
,
ARM
::
CPSR
,
I
)
==
MachineBasicBlock
::
LQR_Dead
)
{
BuildMI
(
MBB
,
I
,
DL
,
get
(
ARM
::
tMOVSr
)
,
DestReg
)
.
addReg
(
SrcReg
,
getKillRegState
(
KillSrc
)
)
->
addRegisterDead
(
ARM
::
CPSR
,
RegInfo
)
;
return
;
}
BuildMI
(
MBB
,
I
,
DL
,
get
(
ARM
::
tPUSH
)
)
.
add
(
predOps
(
ARMCC
::
AL
)
)
.
addReg
(
SrcReg
,
getKillRegState
(
KillSrc
)
)
;
BuildMI
(
MBB
,
I
,
DL
,
get
(
ARM
::
tPOP
)
)
.
add
(
predOps
(
ARMCC
::
AL
)
)
.
addReg
(
DestReg
,
getDefRegState
(
true
)
)
;
}
}
</s>

ARM
ARM
ARM
ARM::GPRRegClass
"Thumb1 can only copy GPR registers"
ARM::hGPRRegClass
ARM::tGPRRegClass
ARM::tMOVr
ARMCC::AL
ARM::CPSR
ARM::tMOVSr
ARM::CPSR
ARM::tPUSH
ARMCC::AL
ARM::tPOP
ARMCC::AL


<s> const RISCVMCExpr * RISCVMCExpr :: create ( const MCExpr * Expr , VariantKind Kind , MCContext & Ctx ) { return new ( Ctx ) RISCVMCExpr ( Expr , Kind ) ; } </s>


<s> unsigned MipsRegisterInfo :: getRegPressureLimit ( const TargetRegisterClass * RC , MachineFunction & MF ) const { switch ( RC -> getID ( ) ) { default : return 0 ; case Mips :: GPR32RegClassID : case Mips :: GPR64RegClassID : case Mips :: DSPRegsRegClassID : { const TargetFrameLowering * TFI = MF . getTarget ( ) . getFrameLowering ( ) ; return 28 - TFI -> hasFP ( MF ) ; } case Mips :: FGR32RegClassID : return 32 ; case Mips :: AFGR64RegClassID : return 16 ; case Mips :: FGR64RegClassID : return 32 ; } } </s>

Return the register pressure `` high water mark '' for the specific register class .


<s> static rtx save_fpr ( rtx base , int offset , int regnum ) { rtx addr ; addr = gen_rtx_MEM ( DFmode , plus_constant ( Pmode , base , offset ) ) ; if ( regnum >= 16 && regnum <= ( 16 + FP_ARG_NUM_REG ) ) set_mem_alias_set ( addr , get_varargs_alias_set ( ) ) ; else set_mem_alias_set ( addr , get_frame_alias_set ( ) ) ; return emit_move_insn ( addr , gen_rtx_REG ( DFmode , regnum ) ) ; } </s>

Emit insn to save fpr REGNUM at offset OFFSET relative to register BASE . Return generated insn .


<s> static void c6x_initialize_trampoline ( rtx tramp , tree fndecl , rtx cxt ) { rtx fnaddr = XEXP ( DECL_RTL ( fndecl ) , 0 ) ; rtx t1 = copy_to_reg ( fnaddr ) ; rtx t2 = copy_to_reg ( cxt ) ; rtx mask = gen_reg_rtx ( SImode ) ; int i ; emit_block_move ( tramp , assemble_trampoline_template ( ) , GEN_INT ( TRAMPOLINE_SIZE ) , BLOCK_OP_NORMAL ) ; emit_move_insn ( mask , GEN_INT ( 0xffff << 7 ) ) ; for ( i = 0 ; i < 4 ; i ++ ) { rtx mem = adjust_address ( tramp , SImode , i * 4 ) ; rtx t = ( i & 1 ) ? t2 : t1 ; rtx v1 = gen_reg_rtx ( SImode ) ; rtx v2 = gen_reg_rtx ( SImode ) ; emit_move_insn ( v1 , mem ) ; if ( i < 2 ) emit_insn ( gen_ashlsi3 ( v2 , t , GEN_INT ( 7 ) ) ) ; else emit_insn ( gen_lshrsi3 ( v2 , t , GEN_INT ( 9 ) ) ) ; emit_insn ( gen_andsi3 ( v2 , v2 , mask ) ) ; emit_insn ( gen_iorsi3 ( v2 , v2 , v1 ) ) ; emit_move_insn ( mem , v2 ) ; } tramp = XEXP ( tramp , 0 ) ; maybe_emit_call_builtin___clear_cache ( tramp , plus_constant ( Pmode , tramp , TRAMPOLINE_SIZE ) ) ; } </s>

Emit RTL insns to initialize the variable parts of a trampoline at TRAMP . FNADDR is an RTX for the address of the function 's pure code . CXT is an RTX for the static chain value for the function .


<s> static void rs6000_elf_select_section ( tree decl , int reloc , unsigned HOST_WIDE_INT align ) { default_elf_select_section_1 ( decl , reloc , align , flag_pic || DEFAULT_ABI == ABI_AIX ) ; } </s>

A C statement or statements to switch to the appropriate section for output of DECL . DECL is either a ` VAR_DECL ' node or a constant of some sort . RELOC indicates whether forming the initial value of DECL requires link-time relocations .


<s> const char * nvptx_output_simt_exit ( rtx src ) { nvptx_output_unisimt_switch ( asm_out_file , false ) ; nvptx_output_softstack_switch ( asm_out_file , false , src , NULL_RTX , NULL_RTX ) ; return "" ; } </s>

Output code to leave non-uniform execution region . SRC is the register holding per-lane storage previously allocated by omp_simt_enter insn .


<s> RISCVTargetLowering :: ConstraintType RISCVTargetLowering :: getConstraintType ( StringRef Constraint ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { default : break ; case 'C' : case 'f' : case 'v' : return C_RegisterClass ; case 'I' : case 'J' : case 'K' : return C_Immediate ; case 'A' : return C_Memory ; case 'S' : return C_Other ; } } return TargetLowering :: getConstraintType ( Constraint ) ; } </s>

Given a constraint letter , return the type of constraint for this target .


<s> MachineBasicBlock :: iterator SparcFrameLowering :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { if ( ! hasReservedCallFrame ( MF ) ) { MachineInstr & MI = * I ; int Size = MI . getOperand ( 0 ) . getImm ( ) ; if ( MI . getOpcode ( ) == SP :: ADJCALLSTACKDOWN ) Size = - Size ; if ( Size ) emitSPAdjustment ( MF , MBB , I , Size , SP :: ADDrr , SP :: ADDri ) ; } return MBB . erase ( I ) ; } </s>

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .

Sparc Sparc 0 SP::ADJCALLSTACKDOWN SP SP::ADDrr SP::ADDri


<s> static rtx nds32_legitimize_argument ( enum insn_code icode , int opnum , rtx arg ) { enum machine_mode mode = insn_data [ icode ] . operand [ opnum ] . mode ; if ( ( * insn_data [ icode ] . operand [ opnum ] . predicate ) ( arg , mode ) ) return arg ; else if ( VECTOR_MODE_P ( mode ) && CONST_INT_P ( arg ) ) { int nunits = GET_MODE_NUNITS ( mode ) ; int i , shift = 0 ; rtvec v = rtvec_alloc ( nunits ) ; int val = INTVAL ( arg ) ; enum machine_mode val_mode = ( mode == V4QImode ) ? QImode : HImode ; int shift_acc = ( val_mode == QImode ) ? 8 : 16 ; int mask = ( val_mode == QImode ) ? 0xff : 0xffff ; int tmp_val = val ; if ( TARGET_BIG_ENDIAN ) for ( i = 0 ; i < nunits ; i ++ ) { tmp_val = ( val >> shift ) & mask ; RTVEC_ELT ( v , nunits - i - 1 ) = gen_int_mode ( tmp_val , val_mode ) ; shift += shift_acc ; } else for ( i = 0 ; i < nunits ; i ++ ) { tmp_val = ( val >> shift ) & mask ; RTVEC_ELT ( v , i ) = gen_int_mode ( tmp_val , val_mode ) ; shift += shift_acc ; } return copy_to_mode_reg ( mode , gen_rtx_CONST_VECTOR ( mode , v ) ) ; } else { rtx tmp_rtx = gen_reg_rtx ( mode ) ; convert_move ( tmp_rtx , arg , false ) ; return tmp_rtx ; } } </s>

Given that ARG is being passed as operand OPNUM to instruction ICODE , check whether ARG satisfies the operand 's constraints . If it does n't , copy ARG to a temporary register and return that . Otherwise return ARG itself .


<s> static int s390_split_branches ( void ) { rtx temp_reg = gen_rtx_REG ( Pmode , RETURN_REGNUM ) ; int new_literal = 0 , ret ; rtx_insn * insn ; rtx pat , target ; rtx * label ; shorten_branches ( get_insns ( ) ) ; for ( insn = get_insns ( ) ; insn ; insn = NEXT_INSN ( insn ) ) { if ( ! JUMP_P ( insn ) || tablejump_p ( insn , NULL , NULL ) ) continue ; pat = PATTERN ( insn ) ; if ( GET_CODE ( pat ) == PARALLEL ) pat = XVECEXP ( pat , 0 , 0 ) ; if ( GET_CODE ( pat ) != SET || SET_DEST ( pat ) != pc_rtx ) continue ; if ( GET_CODE ( SET_SRC ( pat ) ) == LABEL_REF ) { label = & SET_SRC ( pat ) ; } else if ( GET_CODE ( SET_SRC ( pat ) ) == IF_THEN_ELSE ) { if ( GET_CODE ( XEXP ( SET_SRC ( pat ) , 1 ) ) == LABEL_REF ) label = & XEXP ( SET_SRC ( pat ) , 1 ) ; else if ( GET_CODE ( XEXP ( SET_SRC ( pat ) , 2 ) ) == LABEL_REF ) label = & XEXP ( SET_SRC ( pat ) , 2 ) ; else continue ; } else continue ; if ( get_attr_length ( insn ) <= 4 ) continue ; cfun_frame_layout . save_return_addr_p = 1 ; if ( ! flag_pic ) { new_literal = 1 ; rtx mem = force_const_mem ( Pmode , * label ) ; rtx_insn * set_insn = emit_insn_before ( gen_rtx_SET ( Pmode , temp_reg , mem ) , insn ) ; INSN_ADDRESSES_NEW ( set_insn , - 1 ) ; annotate_constant_pool_refs ( & PATTERN ( set_insn ) ) ; target = temp_reg ; } else { new_literal = 1 ; target = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( 1 , * label ) , UNSPEC_LTREL_OFFSET ) ; target = gen_rtx_CONST ( Pmode , target ) ; target = force_const_mem ( Pmode , target ) ; rtx_insn * set_insn = emit_insn_before ( gen_rtx_SET ( Pmode , temp_reg , target ) , insn ) ; INSN_ADDRESSES_NEW ( set_insn , - 1 ) ; annotate_constant_pool_refs ( & PATTERN ( set_insn ) ) ; target = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( 2 , XEXP ( target , 0 ) , cfun -> machine -> base_reg ) , UNSPEC_LTREL_BASE ) ; target = gen_rtx_PLUS ( Pmode , temp_reg , target ) ; } ret = validate_change ( insn , label , target , 0 ) ; gcc_assert ( ret ) ; } return new_literal ; } </s>

Split all branches that exceed the maximum distance . Returns true if this created a new literal pool entry .


<s> bool isLegalMaskedLoad ( Type * DataType , MaybeAlign Alignment ) { return isVectorLaneType ( * getLaneType ( DataType ) ) ; } </s>

Return true if the target supports masked load .


<s>
const
MipsMCExpr
*
MipsMCExpr
::
create
(
MCSymbolRefExpr
::
VariantKind
VK
,
const
MCExpr
*
Expr
,
MCContext
&
Ctx
)
{
VariantKind
Kind
;
switch
(
VK
)
{
case
MCSymbolRefExpr
::
VK_Mips_ABS_LO
:
Kind
=
VK_Mips_LO
;
break
;
case
MCSymbolRefExpr
::
VK_Mips_ABS_HI
:
Kind
=
VK_Mips_HI
;
break
;
case
MCSymbolRefExpr
::
VK_Mips_HIGHER
:
Kind
=
VK_Mips_HIGHER
;
break
;
case
MCSymbolRefExpr
::
VK_Mips_HIGHEST
:
Kind
=
VK_Mips_HIGHEST
;
break
;
default
:
llvm_unreachable
(
"Invalid kind!"
)
;
}
return
new
(
Ctx
)
MipsMCExpr
(
Kind
,
Expr
)
;
}
</s>

Mips
Mips
Mips
Mips
Mips
Mips
Mips
Mips
Mips
Mips
Mips
"Invalid kind!"
Mips


<s> unsigned SIRegisterInfo :: getRegPressureSetLimit ( const MachineFunction & MF , unsigned Idx ) const { const SISubtarget & STI = MF . getSubtarget < SISubtarget > ( ) ; unsigned SGPRLimit = getNumSGPRsAllowed ( STI , STI . getMaxWavesPerCU ( ) ) ; unsigned VGPRLimit = getNumVGPRsAllowed ( STI . getMaxWavesPerCU ( ) ) ; unsigned VSLimit = SGPRLimit + VGPRLimit ; if ( SGPRPressureSets . test ( Idx ) && VGPRPressureSets . test ( Idx ) ) { return VSLimit ; } if ( SGPRPressureSets . test ( Idx ) ) return SGPRLimit ; return VGPRLimit ; } </s>

Get the register unit pressure limit for this dimension .


<s> void RISCVPassConfig :: addIRPasses ( ) { addPass ( createAtomicExpandPass ( ) ) ; TargetPassConfig :: addIRPasses ( ) ; } </s>

Add common target configurable passes that perform LLVM IR to IR transforms following machine independent optimization .


runOnMachineFunction - Emit the function body .


<s> CountValueType getType ( ) const { return Kind ; } </s>

Overload to return most specific vector type .


<s> bool AMDGPUTTIImpl :: getTgtMemIntrinsic ( IntrinsicInst * Inst , MemIntrinsicInfo & Info ) const { switch ( Inst -> getIntrinsicID ( ) ) { case Intrinsic :: amdgcn_atomic_inc : case Intrinsic :: amdgcn_atomic_dec : case Intrinsic :: amdgcn_ds_fadd : case Intrinsic :: amdgcn_ds_fmin : case Intrinsic :: amdgcn_ds_fmax : { auto * Ordering = dyn_cast < ConstantInt > ( Inst -> getArgOperand ( 2 ) ) ; auto * Volatile = dyn_cast < ConstantInt > ( Inst -> getArgOperand ( 4 ) ) ; if ( ! Ordering || ! Volatile ) return false ; unsigned OrderingVal = Ordering -> getZExtValue ( ) ; if ( OrderingVal > static_cast < unsigned > ( AtomicOrdering :: SequentiallyConsistent ) ) return false ; Info . PtrVal = Inst -> getArgOperand ( 0 ) ; Info . Ordering = static_cast < AtomicOrdering > ( OrderingVal ) ; Info . ReadMem = true ; Info . WriteMem = true ; Info . IsVolatile = ! Volatile -> isNullValue ( ) ; return true ; } default : return false ; } } </s>

Given an intrinsic , checks if on the target the intrinsic will need to map to a MemIntrinsicNode ( touches memory ) .


<s> void RISCVAsmPrinter :: emitInstruction ( const MachineInstr * MI ) { if ( emitPseudoExpansionLowering ( * OutStreamer , MI ) ) return ; MCInst TmpInst ; LowerRISCVMachineInstrToMCInst ( MI , TmpInst , * this ) ; EmitToStreamer ( * OutStreamer , TmpInst ) ; } </s>

Targets should implement this to emit instructions .


<s> bool HexagonTargetLowering :: allowsMisalignedMemoryAccesses ( EVT VT , unsigned AS , unsigned Align , MachineMemOperand :: Flags Flags , bool * Fast ) const { if ( Fast ) * Fast = false ; return Subtarget . isHVXVectorType ( VT . getSimpleVT ( ) ) ; } </s>

Returns true if the target allows unaligned memory accesses of the specified type .


<s> bool avr_regno_mode_code_ok_for_base_p ( int regno , machine_mode mode ATTRIBUTE_UNUSED , addr_space_t as ATTRIBUTE_UNUSED , RTX_CODE outer_code , RTX_CODE index_code ATTRIBUTE_UNUSED ) { bool ok = false ; if ( ! ADDR_SPACE_GENERIC_P ( as ) ) { if ( regno < FIRST_PSEUDO_REGISTER && regno == REG_Z ) { return true ; } if ( reg_renumber ) { regno = reg_renumber [ regno ] ; if ( regno == REG_Z ) { return true ; } } return false ; } if ( regno < FIRST_PSEUDO_REGISTER && ( regno == REG_X || regno == REG_Y || regno == REG_Z || regno == ARG_POINTER_REGNUM ) ) { ok = true ; } else if ( reg_renumber ) { regno = reg_renumber [ regno ] ; if ( regno == REG_X || regno == REG_Y || regno == REG_Z || regno == ARG_POINTER_REGNUM ) { ok = true ; } } if ( avr_strict_X && PLUS == outer_code && regno == REG_X ) { ok = false ; } return ok ; } </s>

Implement ` REGNO_MODE_CODE_OK_FOR_BASE_P ' .


<s> virtual const OpenRISCInstrInfo * getInstrInfo ( ) const { return & InstrInfo ; } </s>


<s> static bool rtx_ok_for_offset_p ( enum machine_mode mode , rtx op ) { if ( ! CONST_INT_P ( op ) || INTVAL ( op ) < 0 ) return false ; switch ( mode ) { case QImode : return INTVAL ( op ) <= 31 ; case HImode : return ( INTVAL ( op ) % 2 ) == 0 && INTVAL ( op ) < 63 ; case SImode : case SFmode : return ( INTVAL ( op ) % 4 ) == 0 && INTVAL ( op ) < 127 ; case DImode : case DFmode : return ( INTVAL ( op ) % 4 ) == 0 && INTVAL ( op ) < 123 ; default : return false ; } } </s>

Return true if OP is an offset suitable for use as a displacement in the address of a memory access in mode MODE .


<s> static rtx gen_conditional_move ( enum rtx_code code , machine_mode mode , rtx op0 , rtx op1 ) { if ( mode == SImode ) { rtx cmp ; if ( ( code == GT ) && ( op1 == constm1_rtx ) ) { code = GE ; op1 = const0_rtx ; } cmp = gen_rtx_fmt_ee ( code , VOIDmode , pc_rtx , const0_rtx ) ; if ( boolean_operator ( cmp , VOIDmode ) ) { if ( op0 == const0_rtx ) { op0 = op1 ; op1 = const0_rtx ; } if ( op1 != const0_rtx ) { op0 = expand_binop ( SImode , sub_optab , op0 , op1 , 0 , 0 , OPTAB_LIB_WIDEN ) ; op1 = const0_rtx ; } } else if ( branch_operator ( cmp , VOIDmode ) ) { if ( op0 == const0_rtx ) { op0 = op1 ; op1 = const0_rtx ; switch ( code ) { case LT : code = GE ; break ; case GE : code = LT ; break ; default : gcc_unreachable ( ) ; } } if ( op1 != const0_rtx ) return 0 ; } else return 0 ; return gen_rtx_fmt_ee ( code , VOIDmode , op0 , op1 ) ; } if ( TARGET_HARD_FLOAT && mode == SFmode ) return gen_float_relational ( code , op0 , op1 ) ; return 0 ; } </s>

Emit the common code for conditional moves . OPERANDS is the array of operands passed to the conditional move define_expand .


<s> static void ix86_function_specific_restore ( struct gcc_options * opts , struct cl_target_option * ptr ) { enum processor_type old_tune = ix86_tune ; enum processor_type old_arch = ix86_arch ; unsigned int ix86_arch_mask ; int i ; opts -> x_flag_pic = flag_pic ; ix86_arch = ( enum processor_type ) ptr -> arch ; ix86_schedule = ( enum attr_cpu ) ptr -> schedule ; ix86_tune = ( enum processor_type ) ptr -> tune ; x86_prefetch_sse = ptr -> prefetch_sse ; opts -> x_ix86_branch_cost = ptr -> branch_cost ; ix86_tune_defaulted = ptr -> tune_defaulted ; ix86_arch_specified = ptr -> arch_specified ; opts -> x_ix86_isa_flags_explicit = ptr -> x_ix86_isa_flags_explicit ; opts -> x_ix86_target_flags_explicit = ptr -> x_ix86_target_flags_explicit ; opts -> x_recip_mask_explicit = ptr -> x_recip_mask_explicit ; opts -> x_ix86_arch_string = ptr -> x_ix86_arch_string ; opts -> x_ix86_tune_string = ptr -> x_ix86_tune_string ; opts -> x_ix86_cmodel = ptr -> x_ix86_cmodel ; opts -> x_ix86_abi = ptr -> x_ix86_abi ; opts -> x_ix86_asm_dialect = ptr -> x_ix86_asm_dialect ; opts -> x_ix86_branch_cost = ptr -> x_ix86_branch_cost ; opts -> x_ix86_dump_tunes = ptr -> x_ix86_dump_tunes ; opts -> x_ix86_force_align_arg_pointer = ptr -> x_ix86_force_align_arg_pointer ; opts -> x_ix86_force_drap = ptr -> x_ix86_force_drap ; opts -> x_ix86_incoming_stack_boundary_arg = ptr -> x_ix86_incoming_stack_boundary_arg ; opts -> x_ix86_pmode = ptr -> x_ix86_pmode ; opts -> x_ix86_preferred_stack_boundary_arg = ptr -> x_ix86_preferred_stack_boundary_arg ; opts -> x_ix86_recip_name = ptr -> x_ix86_recip_name ; opts -> x_ix86_regparm = ptr -> x_ix86_regparm ; opts -> x_ix86_section_threshold = ptr -> x_ix86_section_threshold ; opts -> x_ix86_sse2avx = ptr -> x_ix86_sse2avx ; opts -> x_ix86_stack_protector_guard = ptr -> x_ix86_stack_protector_guard ; opts -> x_ix86_stringop_alg = ptr -> x_ix86_stringop_alg ; opts -> x_ix86_tls_dialect = ptr -> x_ix86_tls_dialect ; opts -> x_ix86_tune_ctrl_string = ptr -> x_ix86_tune_ctrl_string ; opts -> x_ix86_tune_memcpy_strategy = ptr -> x_ix86_tune_memcpy_strategy ; opts -> x_ix86_tune_memset_strategy = ptr -> x_ix86_tune_memset_strategy ; opts -> x_ix86_tune_no_default = ptr -> x_ix86_tune_no_default ; opts -> x_ix86_veclibabi_type = ptr -> x_ix86_veclibabi_type ; ix86_tune_cost = processor_target_table [ ix86_tune ] . cost ; if ( opts -> x_optimize_size ) ix86_cost = & ix86_size_cost ; else ix86_cost = ix86_tune_cost ; if ( old_arch != ix86_arch ) { ix86_arch_mask = 1u << ix86_arch ; for ( i = 0 ; i < X86_ARCH_LAST ; ++ i ) ix86_arch_features [ i ] = ! ! ( initial_ix86_arch_features [ i ] & ix86_arch_mask ) ; } if ( old_tune != ix86_tune ) set_ix86_tune_features ( ix86_tune , false ) ; } </s>


<s> virtual bool isShuffleMaskLegal ( const SmallVectorImpl < int > & Mask , EVT VT ) const { return false ; } </s>

Targets can use this to indicate that they only support some VECTOR_SHUFFLE operations , those with specific masks .


<s> void VEPassConfig :: addIRPasses ( ) { addPass ( createAtomicExpandPass ( ) ) ; TargetPassConfig :: addIRPasses ( ) ; } </s>


<s> bool ARMTargetLowering :: mayBeEmittedAsTailCall ( CallInst * CI ) const { if ( ! EnableARMTailCalls && ! Subtarget -> supportsTailCall ( ) ) return false ; if ( ! CI -> isTailCall ( ) ) return false ; return ! Subtarget -> isThumb1Only ( ) ; } </s>

Return true if the target may be able emit the call instruction as a tail call .


<s> bool SystemZElimCompare :: processBlock ( MachineBasicBlock & MBB ) { bool Changed = false ; bool CompleteCCUsers = ! isCCLiveOut ( MBB ) ; SmallVector < MachineInstr * , 4 > CCUsers ; MachineBasicBlock :: iterator MBBI = MBB . end ( ) ; while ( MBBI != MBB . begin ( ) ) { MachineInstr * MI = -- MBBI ; if ( CompleteCCUsers && MI -> isCompare ( ) && ( optimizeCompareZero ( MI , CCUsers ) || fuseCompareAndBranch ( MI , CCUsers ) ) ) { ++ MBBI ; MI -> removeFromParent ( ) ; Changed = true ; CCUsers . clear ( ) ; CompleteCCUsers = true ; continue ; } Reference CCRefs ( getRegReferences ( MI , SystemZ :: CC ) ) ; if ( CCRefs . Def ) { CCUsers . clear ( ) ; CompleteCCUsers = ! CCRefs . IndirectDef ; } if ( CompleteCCUsers && CCRefs . Use ) CCUsers . push_back ( MI ) ; } return Changed ; } </s>

processBlock - If there are any predecessors whose control can be threaded through to a successor , transform them now .


<s> void Cpu0FrameLowering :: emitPrologue ( MachineFunction & MF , MachineBasicBlock & MBB ) const { } </s>

emitProlog/emitEpilog - These methods insert prolog and epilog code into the function .


<s> void RISCVInstPrinter :: printInst ( const MCInst * MI , uint64_t Address , StringRef Annot , const MCSubtargetInfo & STI , raw_ostream & O ) { bool Res = false ; const MCInst * NewMI = MI ; MCInst UncompressedMI ; if ( ! NoAliases ) Res = uncompressInst ( UncompressedMI , * MI , MRI , STI ) ; if ( Res ) NewMI = const_cast < MCInst * > ( & UncompressedMI ) ; if ( NoAliases || ! printAliasInstr ( NewMI , STI , O ) ) printInstruction ( NewMI , Address , STI , O ) ; printAnnotation ( O , Annot ) ; } </s>

Print the specified MCInst to the specified raw_ostream .


<s> void mep_print_operand_address ( FILE * stream , rtx address ) { if ( GET_CODE ( address ) == MEM ) address = XEXP ( address , 0 ) ; else gcc_assert ( GET_CODE ( address ) == REG ) ; mep_print_operand ( stream , address , 0 ) ; } </s>


<s> static void emitSPUpdate ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator & MBBI , const TargetInstrInfo & TII , DebugLoc dl , const Thumb1RegisterInfo & MRI , int NumBytes ) { emitThumbRegPlusImmediate ( MBB , MBBI , ARM :: SP , ARM :: SP , NumBytes , TII , MRI , dl ) ; } </s>

Emit a series of instructions to increment / decrement the stack pointer by a constant value .


<s> static rtx aapcs_vfp_allocate_return_reg ( enum arm_pcs pcs_variant ATTRIBUTE_UNUSED , machine_mode mode , const_tree type ATTRIBUTE_UNUSED ) { if ( ! use_vfp_abi ( pcs_variant , false ) ) return NULL ; if ( mode == BLKmode || ( mode == TImode && ! TARGET_NEON ) ) { int count ; machine_mode ag_mode ; int i ; rtx par ; int shift ; aapcs_vfp_is_call_or_return_candidate ( pcs_variant , mode , type , & ag_mode , & count ) ; if ( ! TARGET_NEON ) { if ( ag_mode == V2SImode ) ag_mode = DImode ; else if ( ag_mode == V4SImode ) { ag_mode = DImode ; count *= 2 ; } } shift = GET_MODE_SIZE ( ag_mode ) / GET_MODE_SIZE ( SFmode ) ; par = gen_rtx_PARALLEL ( mode , rtvec_alloc ( count ) ) ; for ( i = 0 ; i < count ; i ++ ) { rtx tmp = gen_rtx_REG ( ag_mode , FIRST_VFP_REGNUM + i * shift ) ; tmp = gen_rtx_EXPR_LIST ( VOIDmode , tmp , GEN_INT ( i * GET_MODE_SIZE ( ag_mode ) ) ) ; XVECEXP ( par , 0 , i ) = tmp ; } return par ; } return gen_rtx_REG ( mode , FIRST_VFP_REGNUM ) ; } </s>

Implement the allocate_return_reg field in aapcs_cp_arg_layout . See the comment there for the behaviour of this function .


<s> static unsigned int h8300_bitfield_length ( rtx op , rtx op2 ) { enum h8300_operand_class opclass ; unsigned int size , operand_length ; if ( GET_CODE ( op ) == REG ) op = op2 ; gcc_assert ( GET_CODE ( op ) != REG ) ; size = GET_MODE_SIZE ( GET_MODE ( op ) ) ; operand_length = h8300_classify_operand ( op , size , & opclass ) ; switch ( opclass ) { case H8OP_MEM_BASE : case H8OP_MEM_ABSOLUTE : case H8OP_MEM_COMPLEX : return 4 + operand_length ; default : gcc_unreachable ( ) ; } } </s>

Likewise bitfield load and store instructions .


<s>
SDValue
VideoCore4TargetLowering
::
LowerReturn
(
SDValue
Chain
,
CallingConv
::
ID
CallConv
,
bool
isVarArg
,
const
SmallVectorImpl
<
ISD
::
OutputArg
>
&
Outs
,
const
SmallVectorImpl
<
SDValue
>
&
OutVals
,
SDLoc
dl
,
SelectionDAG
&
DAG
)
const
{
SmallVector
<
CCValAssign
,
16
>
RVLocs
;
CCState
CCInfo
(
CallConv
,
isVarArg
,
DAG
.
getMachineFunction
(
)
,
getTargetMachine
(
)
,
RVLocs
,
*
DAG
.
getContext
(
)
)
;
CCInfo
.
AnalyzeReturn
(
Outs
,
RetCC_VideoCore4
)
;
SDValue
Flag
;
SmallVector
<
SDValue
,
4
>
RetOps
(
1
,
Chain
)
;
for
(
unsigned
i
=
0
;
i
!=
RVLocs
.
size
(
)
;
++
i
)
{
CCValAssign
&
VA
=
RVLocs
[
i
]
;
assert
(
VA
.
isRegLoc
(
)
&&
"Can only return in registers!"
)
;
Chain
=
DAG
.
getCopyToReg
(
Chain
,
dl
,
VA
.
getLocReg
(
)
,
OutVals
[
i
]
,
Flag
)
;
Flag
=
Chain
.
getValue
(
1
)
;
RetOps
.
push_back
(
DAG
.
getRegister
(
VA
.
getLocReg
(
)
,
VA
.
getLocVT
(
)
)
)
;
}
RetOps
[
0
]
=
Chain
;
if
(
Flag
.
getNode
(
)
)
RetOps
.
push_back
(
Flag
)
;
return
DAG
.
getNode
(
VideoCore4ISD
::
RET_FLAG
,
dl
,
MVT
::
Other
,
ArrayRef
<
SDValue
>
(
&
RetOps
[
0
]
,
RetOps
.
size
(
)
)
)
;
}
</s>

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .


<s> void nvptx_output_skip ( FILE * , unsigned HOST_WIDE_INT size ) { if ( init_frag . offset ) { unsigned part = init_frag . size - init_frag . offset ; part = MIN ( part , ( unsigned ) size ) ; size -= part ; nvptx_assemble_value ( 0 , part ) ; } if ( size < init_frag . remaining * init_frag . size ) { while ( size >= init_frag . size ) { size -= init_frag . size ; output_init_frag ( NULL_RTX ) ; } if ( size ) nvptx_assemble_value ( 0 , size ) ; } } </s>

Output SIZE zero bytes . We ignore the FILE argument since the functions we 're calling to perform the output just use asm_out_file .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . setPreservesCFG ( ) ; AU . addRequired < ReachingDefAnalysis > ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> static int rs6000_builtin_vectorization_cost ( enum vect_cost_for_stmt type_of_cost , tree vectype , int misalign ) { unsigned elements ; tree elem_type ; switch ( type_of_cost ) { case scalar_stmt : case scalar_load : case scalar_store : case vector_stmt : case vector_load : case vector_store : case vec_to_scalar : case scalar_to_vec : case cond_branch_not_taken : return 1 ; case vec_perm : if ( TARGET_VSX ) return 3 ; else return 1 ; case vec_promote_demote : if ( TARGET_VSX ) return 4 ; else return 1 ; case cond_branch_taken : return 3 ; case unaligned_load : if ( TARGET_P9_VECTOR ) return 3 ; if ( TARGET_EFFICIENT_UNALIGNED_VSX ) return 1 ; if ( TARGET_VSX && TARGET_ALLOW_MOVMISALIGN ) { elements = TYPE_VECTOR_SUBPARTS ( vectype ) ; if ( elements == 2 ) return 2 ; if ( elements == 4 ) { switch ( misalign ) { case 8 : return 2 ; case - 1 : case 4 : case 12 : return 22 ; default : gcc_unreachable ( ) ; } } } if ( TARGET_ALTIVEC ) gcc_unreachable ( ) ; return 2 ; case unaligned_store : if ( TARGET_EFFICIENT_UNALIGNED_VSX ) return 1 ; if ( TARGET_VSX && TARGET_ALLOW_MOVMISALIGN ) { elements = TYPE_VECTOR_SUBPARTS ( vectype ) ; if ( elements == 2 ) return 2 ; if ( elements == 4 ) { switch ( misalign ) { case 8 : return 2 ; case - 1 : case 4 : case 12 : return 23 ; default : gcc_unreachable ( ) ; } } } if ( TARGET_ALTIVEC ) gcc_unreachable ( ) ; return 2 ; case vec_construct : elem_type = TREE_TYPE ( vectype ) ; if ( SCALAR_FLOAT_TYPE_P ( elem_type ) && TYPE_PRECISION ( elem_type ) == 32 ) return 5 ; else return max ( 2 , TYPE_VECTOR_SUBPARTS ( vectype ) - 1 ) ; default : gcc_unreachable ( ) ; } } </s>


<s> static tree mips_std_gimplify_va_arg_expr ( tree valist , tree type , gimple_seq * pre_p , gimple_seq * post_p ) { tree addr , t , type_size , rounded_size , valist_tmp ; unsigned HOST_WIDE_INT align , boundary ; bool indirect ; indirect = pass_by_reference ( NULL , TYPE_MODE ( type ) , type , false ) ; if ( indirect ) type = build_pointer_type ( type ) ; align = PARM_BOUNDARY / BITS_PER_UNIT ; boundary = targetm . calls . function_arg_boundary ( TYPE_MODE ( type ) , type ) ; if ( boundary > MAX_SUPPORTED_STACK_ALIGNMENT ) boundary = MAX_SUPPORTED_STACK_ALIGNMENT ; boundary /= BITS_PER_UNIT ; valist_tmp = get_initialized_tmp_var ( valist , pre_p , NULL ) ; if ( boundary > align ) { t = build2 ( MODIFY_EXPR , TREE_TYPE ( valist ) , valist_tmp , fold_build_pointer_plus_hwi ( valist_tmp , boundary - 1 ) ) ; gimplify_and_add ( t , pre_p ) ; t = build2 ( MODIFY_EXPR , TREE_TYPE ( valist ) , valist_tmp , fold_build2 ( BIT_AND_EXPR , TREE_TYPE ( valist ) , valist_tmp , build_int_cst ( TREE_TYPE ( valist ) , - boundary ) ) ) ; gimplify_and_add ( t , pre_p ) ; } else boundary = align ; boundary *= BITS_PER_UNIT ; if ( boundary < TYPE_ALIGN ( type ) ) { type = build_variant_type_copy ( type ) ; SET_TYPE_ALIGN ( type , boundary ) ; } type_size = size_in_bytes ( type ) ; rounded_size = round_up ( type_size , align ) ; gimplify_expr ( & rounded_size , pre_p , post_p , is_gimple_val , fb_rvalue ) ; addr = valist_tmp ; if ( PAD_VARARGS_DOWN && ! integer_zerop ( rounded_size ) ) { t = fold_build2_loc ( input_location , GT_EXPR , sizetype , rounded_size , size_int ( align ) ) ; t = fold_build3 ( COND_EXPR , sizetype , t , size_zero_node , size_binop ( MINUS_EXPR , rounded_size , type_size ) ) ; addr = fold_build_pointer_plus ( addr , t ) ; } t = fold_build_pointer_plus ( valist_tmp , rounded_size ) ; t = build2 ( MODIFY_EXPR , TREE_TYPE ( valist ) , valist , t ) ; gimplify_and_add ( t , pre_p ) ; addr = fold_convert ( build_pointer_type ( type ) , addr ) ; if ( indirect ) addr = build_va_arg_indirect_ref ( addr ) ; return build_va_arg_indirect_ref ( addr ) ; } </s>

Like std_gimplify_va_arg_expr , but apply alignment to zero-sized types as well .


<s> bool rl78_flags_already_set ( rtx op , rtx operand ) { if ( GET_CODE ( op ) != EQ && GET_CODE ( op ) != NE ) return false ; if ( current_output_insn == NULL_RTX ) return false ; rtx_insn * insn ; bool res = false ; for ( insn = prev_nonnote_nondebug_insn ( current_output_insn ) ; insn != NULL_RTX ; insn = prev_nonnote_nondebug_insn ( insn ) ) { if ( LABEL_P ( insn ) ) break ; if ( ! INSN_P ( insn ) ) continue ; if ( recog_memoized ( insn ) == - 1 ) continue ; enum attr_update_Z updated = get_attr_update_Z ( insn ) ; rtx set = single_set ( insn ) ; bool must_break = ( set != NULL_RTX && rtx_equal_p ( operand , SET_DEST ( set ) ) ) ; switch ( updated ) { case UPDATE_Z_NO : break ; case UPDATE_Z_CLOBBER : must_break = true ; break ; case UPDATE_Z_UPDATE_Z : res = must_break ; must_break = true ; break ; default : gcc_unreachable ( ) ; } if ( must_break ) break ; } recog_memoized ( current_output_insn ) ; cleanup_subreg_operands ( current_output_insn ) ; constrain_operands_cached ( current_output_insn , 1 ) ; return res ; } </s>

Scan backwards through the insn chain looking to see if the flags have been set for a comparison of OP against OPERAND . Start with the insn * before * the current insn .


<s> const DataLayout * getDataLayout ( ) const override { return getSubtargetImpl ( ) -> getDataLayout ( ) ; } </s>

Return the DataLayout associated with the module this SCEV instance is operating on .


<s> void AMDGPUInstructionSelector :: setupMF ( MachineFunction & MF , GISelKnownBits & KB , CodeGenCoverage & CoverageInfo ) { MRI = & MF . getRegInfo ( ) ; InstructionSelector :: setupMF ( MF , KB , CoverageInfo ) ; } </s>


<s>
__inline__
static
unsigned
long
long
sh_media_LDHI_L
(
void
*
p
,
int
s
)
{
unsigned
long
long
res
;
__asm__
(
"ldhi.l	%m1, %0"
:
"=r"
(
res
)
:
"o"
(
(
(
char
*
)
p
)
[
s
]
)
)
;
return
res
;
}
</s>


<s> void or1k_expand_atomic_compare_and_swap ( rtx operands [ ] ) { rtx boolval , retval , mem , oldval , newval ; rtx label1 , label2 ; machine_mode mode ; bool is_weak ; boolval = operands [ 0 ] ; retval = operands [ 1 ] ; mem = operands [ 2 ] ; oldval = operands [ 3 ] ; newval = operands [ 4 ] ; is_weak = ( INTVAL ( operands [ 5 ] ) != 0 ) ; mode = GET_MODE ( mem ) ; if ( reg_overlap_mentioned_p ( retval , oldval ) ) oldval = copy_to_reg ( oldval ) ; label1 = NULL_RTX ; if ( ! is_weak ) { label1 = gen_rtx_LABEL_REF ( VOIDmode , gen_label_rtx ( ) ) ; emit_label ( XEXP ( label1 , 0 ) ) ; } label2 = gen_rtx_LABEL_REF ( VOIDmode , gen_label_rtx ( ) ) ; emit_load_locked ( mode , retval , mem ) ; emit_compare ( EQ , retval , oldval ) ; emit_unlikely_jump ( EQ , label2 ) ; emit_store_conditional ( mode , mem , newval ) ; if ( ! is_weak ) emit_unlikely_jump ( EQ , label1 ) ; emit_label ( XEXP ( label2 , 0 ) ) ; emit_insn ( gen_sne_sr_f ( boolval ) ) ; } </s>

Expand an atomic compare and swap operation . Emits the RTX to perform a compare and swap operation . This function takes 8 RTX arguments in the OPERANDS array . The compare and swap operation loads a value from memory ( OPERANDS [ 2 ] ) and compares it with an expected value ( OPERANDS [ 3 ] ) , if the values are equal it stores a new value ( OPERANDS [ 4 ] ) to memory . The argument OPERANDS [ 0 ] represents a boolean result which will be set to true if the operation succeeds . A return value ( OPERANDS [ 1 ] ) will be set to what was loaded from memory . The argument OPERAND [ 5 ] is used to indicate if the compare and swap is to be treated as weak . OpenRISC does not use OPERANDS [ 5 ] or OPERANDS [ 6 ] which provide memory model details . For OpenRISC this emits RTX which will translate to assembly using the ' l.lwa ' ( load word atomic ) and ' l.swa ' ( store word atomic ) instructions .


<s> void NVPTXPassConfig :: addIRPasses ( ) { disablePass ( & PrologEpilogCodeInserterID ) ; disablePass ( & MachineCopyPropagationID ) ; disablePass ( & TailDuplicateID ) ; disablePass ( & StackMapLivenessID ) ; disablePass ( & LiveDebugValuesID ) ; disablePass ( & PostRAMachineSinkingID ) ; disablePass ( & PostRASchedulerID ) ; disablePass ( & FuncletLayoutID ) ; disablePass ( & PatchableFunctionID ) ; disablePass ( & ShrinkWrapID ) ; const NVPTXSubtarget & ST = * getTM < NVPTXTargetMachine > ( ) . getSubtargetImpl ( ) ; addPass ( createNVVMReflectPass ( ST . getSmVersion ( ) ) ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) addPass ( createNVPTXImageOptimizerPass ( ) ) ; addPass ( createNVPTXAssignValidGlobalNamesPass ( ) ) ; addPass ( createGenericToNVVMPass ( ) ) ; addPass ( createNVPTXLowerArgsPass ( & getNVPTXTargetMachine ( ) ) ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) { addAddressSpaceInferencePasses ( ) ; if ( ! DisableLoadStoreVectorizer ) addPass ( createLoadStoreVectorizerPass ( ) ) ; addStraightLineScalarOptimizationPasses ( ) ; } TargetPassConfig :: addIRPasses ( ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) addEarlyCSEOrGVNPass ( ) ; } </s>

Add common target configurable passes that perform LLVM IR to IR transforms following machine independent optimization .

NVPTX NVPTX NVPTX NVPTX NVPTX NVPTX NVPTX NVPTX


<s>
void
print_operand_address
(
FILE
*
file
,
rtx
addr
)
{
struct
microblaze_address_info
info
;
enum
microblaze_address_type
type
;
if
(
!
microblaze_classify_address
(
&
info
,
addr
,
GET_MODE
(
addr
)
,
2
)
)
fatal_insn
(
"insn contains an invalid address !"
,
addr
)
;
type
=
info
.
type
;
switch
(
info
.
type
)
{
case
ADDRESS_REG
:
fprintf
(
file
,
"%s,"
,
reg_names
[
REGNO
(
info
.
regA
)
]
)
;
output_addr_const
(
file
,
info
.
offset
)
;
break
;
case
ADDRESS_REG_INDEX
:
if
(
REGNO
(
info
.
regA
)
==
0
)
fprintf
(
file
,
"%s,%s"
,
reg_names
[
REGNO
(
info
.
regB
)
]
,
reg_names
[
REGNO
(
info
.
regA
)
]
)
;
else
if
(
REGNO
(
info
.
regB
)
!=
0
)
fprintf
(
file
,
"%s,%s"
,
reg_names
[
REGNO
(
info
.
regB
)
]
,
reg_names
[
REGNO
(
info
.
regA
)
]
)
;
break
;
case
ADDRESS_CONST_INT
:
fprintf
(
file
,
"%s,"
,
reg_names
[
REGNO
(
info
.
regA
)
]
)
;
output_addr_const
(
file
,
info
.
offset
)
;
break
;
case
ADDRESS_SYMBOLIC
:
case
ADDRESS_SYMBOLIC_TXT_REL
:
case
ADDRESS_GOTOFF
:
case
ADDRESS_PLT
:
case
ADDRESS_TLS
:
if
(
info
.
regA
)
fprintf
(
file
,
"%s,"
,
reg_names
[
REGNO
(
info
.
regA
)
]
)
;
output_addr_const
(
file
,
info
.
symbol
)
;
if
(
type
==
ADDRESS_GOTOFF
)
{
fputs
(
"@GOT"
,
file
)
;
}
else
if
(
type
==
ADDRESS_PLT
)
{
fputs
(
"@PLT"
,
file
)
;
}
else
if
(
type
==
ADDRESS_SYMBOLIC_TXT_REL
)
{
if
(
info
.
offset
!=
&&
CONST_INT_P
(
info
.
offset
)
&&
INTVAL
(
info
.
offset
)
>
0
)
{
fprintf
(
file
,
"+"
)
;
output_addr_const
(
file
,
info
.
offset
)
;
}
fputs
(
"@TXTREL"
,
file
)
;
}
else
if
(
type
==
ADDRESS_TLS
)
{
switch
(
info
.
tls_type
)
{
case
TLS_GD
:
fputs
(
"@TLSGD"
,
file
)
;
break
;
case
TLS_LDM
:
fputs
(
"@TLSLDM"
,
file
)
;
break
;
case
TLS_DTPREL
:
fputs
(
"@TLSDTPREL"
,
file
)
;
break
;
default
:
gcc_unreachable
(
)
;
break
;
}
}
break
;
case
ADDRESS_INVALID
:
fatal_insn
(
"invalid address"
,
addr
)
;
break
;
}
}
</s>

Print the operand address represented by the rtx addr


<s>
bool
HexagonExpandCondsets
::
split
(
MachineInstr
*
MI
,
std
::
set
<
unsigned
>
&
UpdRegs
)
{
if
(
TfrLimitActive
)
{
if
(
TfrCounter
>=
TfrLimit
)
return
false
;
TfrCounter
++
;
}
DEBUG
(
dbgs
(
)
<<
"\nsplitting BB#"
<<
MI
->
getParent
(
)
->
getNumber
(
)
<<
": "
<<
*
MI
)
;
MachineOperand
&
MD
=
MI
->
getOperand
(
0
)
;
MachineOperand
&
MP
=
MI
->
getOperand
(
1
)
;
MachineOperand
&
MS1
=
MI
->
getOperand
(
2
)
;
MachineOperand
&
MS2
=
MI
->
getOperand
(
3
)
;
assert
(
MD
.
isDef
(
)
)
;
unsigned
DR
=
MD
.
getReg
(
)
,
DSR
=
MD
.
getSubReg
(
)
;
bool
ReadUndef
=
MD
.
isUndef
(
)
;
MachineBasicBlock
::
iterator
At
=
MI
;
if
(
ReadUndef
&&
DSR
!=
0
&&
MRI
->
shouldTrackSubRegLiveness
(
DR
)
)
{
unsigned
NewSR
=
0
;
MachineBasicBlock
::
iterator
DefAt
=
At
;
bool
SameReg
=
(
MS1
.
isReg
(
)
&&
DR
==
MS1
.
getReg
(
)
)
||
(
MS2
.
isReg
(
)
&&
DR
==
MS2
.
getReg
(
)
)
;
if
(
SameReg
)
{
NewSR
=
(
DSR
==
Hexagon
::
subreg_loreg
)
Hexagon
::
subreg_hireg
:
Hexagon
::
subreg_loreg
;
if
(
(
MS1
.
isReg
(
)
&&
NewSR
==
MS1
.
getSubReg
(
)
)
||
(
MS2
.
isReg
(
)
&&
NewSR
==
MS2
.
getSubReg
(
)
)
)
++
DefAt
;
}
MachineBasicBlock
&
B
=
*
At
->
getParent
(
)
;
DebugLoc
DL
=
At
->
getDebugLoc
(
)
;
auto
ImpD
=
BuildMI
(
B
,
DefAt
,
DL
,
HII
->
get
(
TargetOpcode
::
IMPLICIT_DEF
)
)
.
addReg
(
DR
,
RegState
::
Define
,
NewSR
)
;
LIS
->
InsertMachineInstrInMaps
(
*
ImpD
)
;
LocalImpDefs
.
insert
(
&
*
ImpD
)
;
}
MachineInstr
*
TfrT
=
genCondTfrFor
(
MI
->
getOperand
(
2
)
,
At
,
DR
,
DSR
,
MP
,
true
,
ReadUndef
,
false
)
;
MachineInstr
*
TfrF
=
genCondTfrFor
(
MI
->
getOperand
(
3
)
,
At
,
DR
,
DSR
,
MP
,
false
,
ReadUndef
,
true
)
;
LIS
->
InsertMachineInstrInMaps
(
*
TfrT
)
;
LIS
->
InsertMachineInstrInMaps
(
*
TfrF
)
;
for
(
auto
&
Op
:
MI
->
operands
(
)
)
if
(
Op
.
isReg
(
)
)
UpdRegs
.
insert
(
Op
.
getReg
(
)
)
;
removeInstr
(
MI
)
;
return
true
;
}
</s>

Split into substrings around the occurrences of a separator character .


<s> static rtx arm_expand_binop_builtin ( enum insn_code icode , tree exp , rtx target ) { rtx pat ; tree arg0 = CALL_EXPR_ARG ( exp , 0 ) ; tree arg1 = CALL_EXPR_ARG ( exp , 1 ) ; rtx op0 = expand_normal ( arg0 ) ; rtx op1 = expand_normal ( arg1 ) ; machine_mode tmode = insn_data [ icode ] . operand [ 0 ] . mode ; machine_mode mode0 = insn_data [ icode ] . operand [ 1 ] . mode ; machine_mode mode1 = insn_data [ icode ] . operand [ 2 ] . mode ; if ( VECTOR_MODE_P ( mode0 ) ) op0 = safe_vector_operand ( op0 , mode0 ) ; if ( VECTOR_MODE_P ( mode1 ) ) op1 = safe_vector_operand ( op1 , mode1 ) ; if ( ! target || GET_MODE ( target ) != tmode || ! ( * insn_data [ icode ] . operand [ 0 ] . predicate ) ( target , tmode ) ) target = gen_reg_rtx ( tmode ) ; gcc_assert ( ( GET_MODE ( op0 ) == mode0 || GET_MODE ( op0 ) == VOIDmode ) && ( GET_MODE ( op1 ) == mode1 || GET_MODE ( op1 ) == VOIDmode ) ) ; if ( ! ( * insn_data [ icode ] . operand [ 1 ] . predicate ) ( op0 , mode0 ) ) op0 = copy_to_mode_reg ( mode0 , op0 ) ; if ( ! ( * insn_data [ icode ] . operand [ 2 ] . predicate ) ( op1 , mode1 ) ) op1 = copy_to_mode_reg ( mode1 , op1 ) ; pat = GEN_FCN ( icode ) ( target , op0 , op1 ) ; if ( ! pat ) return 0 ; emit_insn ( pat ) ; return target ; } </s>

Subroutine of arm_expand_builtin to take care of binop insns .


<s> std :: unique_ptr < MCObjectWriter > createObjectWriter ( raw_pwrite_stream & OS ) const override { return createARMELFObjectWriter ( OS , OSABI , isLittle ( ) ) ; } </s>

Create a new MCObjectWriter instance for use by the assembler backend to emit the final object file .


<s> SparcSubtarget & SparcSubtarget :: initializeSubtargetDependencies ( StringRef CPU , StringRef FS ) { IsV9 = false ; IsLeon = false ; V8DeprecatedInsts = false ; IsVIS = false ; HasHardQuad = false ; UsePopc = false ; UseSoftFloat = false ; HasLeonCasa = false ; HasUmacSmac = false ; PerformSDIVReplace = false ; InsertNOPLoad = false ; FixFSMULD = false ; ReplaceFMULS = false ; FixAllFDIVSQRT = false ; DetectRoundChange = false ; std :: string CPUName = CPU ; if ( CPUName . empty ( ) ) CPUName = ( Is64Bit ) ? "v9" : "v8" ; ParseSubtargetFeatures ( CPUName , FS ) ; if ( ! IsV9 ) UsePopc = false ; return * this ; } </s>

initializeSubtargetDependencies - Initializes using a CPU , a TuneCPU , and feature string so that we can use initializer lists for subtarget initialization .


<s> static int toc_hash_eq ( const void * h1 , const void * h2 ) { rtx r1 = ( ( const struct toc_hash_struct * ) h1 ) -> key ; rtx r2 = ( ( const struct toc_hash_struct * ) h2 ) -> key ; if ( ( ( const struct toc_hash_struct * ) h1 ) -> key_mode != ( ( const struct toc_hash_struct * ) h2 ) -> key_mode ) return 0 ; return rtx_equal_p ( r1 , r2 ) ; } </s>


<s> void TVMContinuationsHoist :: collect ( MachineFunction & MF ) { Info . clear ( ) ; DeleteMIs . clear ( ) ; for ( MachineBasicBlock & MBB : MF ) for ( MachineInstr & MI : MBB ) collectInstr ( MI ) ; } </s>

Analyze the given instruction MI and fill in the Uses , Defs and DeadDefs list based on the MachineOperand flags .


<s> const LEGInstrInfo * getInstrInfo ( ) const override { return & InstrInfo ; } </s>


<s> static void arm_unwind_emit ( FILE * asm_out_file , rtx insn ) { rtx pat ; if ( ! ARM_EABI_UNWIND_TABLES ) return ; if ( GET_CODE ( insn ) == NOTE || ! RTX_FRAME_RELATED_P ( insn ) ) return ; pat = find_reg_note ( insn , REG_FRAME_RELATED_EXPR , NULL_RTX ) ; if ( pat ) pat = XEXP ( pat , 0 ) ; else pat = PATTERN ( insn ) ; switch ( GET_CODE ( pat ) ) { case SET : arm_unwind_emit_set ( asm_out_file , pat ) ; break ; case SEQUENCE : arm_unwind_emit_stm ( asm_out_file , pat ) ; break ; default : abort ( ) ; } } </s>

Emit unwind directives for the given insn .


<s> SDValue X86TargetLowering :: getPICJumpTableRelocBase ( SDValue Table , SelectionDAG & DAG ) const { if ( usesGlobalOffsetTable ( ) ) return DAG . getGLOBAL_OFFSET_TABLE ( getPointerTy ( ) ) ; if ( ! Subtarget -> is64Bit ( ) ) return DAG . getNode ( X86ISD :: GlobalBaseReg , DebugLoc :: getUnknownLoc ( ) , getPointerTy ( ) ) ; return Table ; } </s>

Returns relocation base for the given PIC jumptable .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . addRequired < LoopInfoWrapperPass > ( ) ; AU . addRequired < DominatorTreeWrapperPass > ( ) ; AU . addPreserved < DominatorTreeWrapperPass > ( ) ; FunctionPass :: getAnalysisUsage ( AU ) ; } </s>


<s> int aarch64_uxt_size ( int shift , HOST_WIDE_INT mask ) { if ( shift >= 0 && shift <= 3 ) { int size ; for ( size = 8 ; size <= 32 ; size *= 2 ) { HOST_WIDE_INT bits = ( ( HOST_WIDE_INT ) 1U << size ) - 1 ; if ( mask == bits << shift ) return size ; } } return 0 ; } </s>

Return size in bits of an arithmetic operand which is shifted/scaled and masked such that it is suitable for a UXTB , UXTH , or UXTW extend operator .


<s> LaneBitmask HexagonExpandCondsets :: getLaneMask ( unsigned Reg , unsigned Sub ) { assert ( Register :: isVirtualRegister ( Reg ) ) ; return Sub != 0 ? TRI -> getSubRegIndexLaneMask ( Sub ) : MRI -> getMaxLaneMaskForVReg ( Reg ) ; } </s>

Returns the combination of all lane masks of register in this class .


<s> bool AArch64PreLegalizerCombiner :: runOnMachineFunction ( MachineFunction & MF ) { if ( MF . getProperties ( ) . hasProperty ( MachineFunctionProperties :: Property :: FailedISel ) ) return false ; auto * TPC = & getAnalysis < TargetPassConfig > ( ) ; const Function & F = MF . getFunction ( ) ; bool EnableOpt = MF . getTarget ( ) . getOptLevel ( ) != CodeGenOpt :: None && ! skipFunction ( F ) ; GISelKnownBits * KB = & getAnalysis < GISelKnownBitsAnalysis > ( ) . get ( MF ) ; AArch64PreLegalizerCombinerInfo PCInfo ( EnableOpt , F . hasOptSize ( ) , F . hasMinSize ( ) , KB ) ; Combiner C ( PCInfo , TPC ) ; return C . combineMachineInstrs ( MF , nullptr ) ; } </s>

runOnMachineFunction - Emit the function body .


<s> static tree ix86_vectorize_builtin_gather ( const_tree mem_vectype , const_tree index_type , int scale ) { bool si ; enum ix86_builtins code ; if ( ! TARGET_AVX2 || ! TARGET_USE_GATHER ) return NULL_TREE ; if ( ( TREE_CODE ( index_type ) != INTEGER_TYPE && ! POINTER_TYPE_P ( index_type ) ) || ( TYPE_MODE ( index_type ) != SImode && TYPE_MODE ( index_type ) != DImode ) ) return NULL_TREE ; if ( TYPE_PRECISION ( index_type ) > POINTER_SIZE ) return NULL_TREE ; if ( TYPE_PRECISION ( index_type ) < POINTER_SIZE && TYPE_UNSIGNED ( index_type ) ) return NULL_TREE ; if ( scale <= 0 || scale > 8 || ( scale & ( scale - 1 ) ) != 0 ) return NULL_TREE ; si = TYPE_MODE ( index_type ) == SImode ; switch ( TYPE_MODE ( mem_vectype ) ) { case E_V2DFmode : if ( TARGET_AVX512VL ) code = si ? IX86_BUILTIN_GATHER3SIV2DF : IX86_BUILTIN_GATHER3DIV2DF ; else code = si ? IX86_BUILTIN_GATHERSIV2DF : IX86_BUILTIN_GATHERDIV2DF ; break ; case E_V4DFmode : if ( TARGET_AVX512VL ) code = si ? IX86_BUILTIN_GATHER3ALTSIV4DF : IX86_BUILTIN_GATHER3DIV4DF ; else code = si ? IX86_BUILTIN_GATHERALTSIV4DF : IX86_BUILTIN_GATHERDIV4DF ; break ; case E_V2DImode : if ( TARGET_AVX512VL ) code = si ? IX86_BUILTIN_GATHER3SIV2DI : IX86_BUILTIN_GATHER3DIV2DI ; else code = si ? IX86_BUILTIN_GATHERSIV2DI : IX86_BUILTIN_GATHERDIV2DI ; break ; case E_V4DImode : if ( TARGET_AVX512VL ) code = si ? IX86_BUILTIN_GATHER3ALTSIV4DI : IX86_BUILTIN_GATHER3DIV4DI ; else code = si ? IX86_BUILTIN_GATHERALTSIV4DI : IX86_BUILTIN_GATHERDIV4DI ; break ; case E_V4SFmode : if ( TARGET_AVX512VL ) code = si ? IX86_BUILTIN_GATHER3SIV4SF : IX86_BUILTIN_GATHER3DIV4SF ; else code = si ? IX86_BUILTIN_GATHERSIV4SF : IX86_BUILTIN_GATHERDIV4SF ; break ; case E_V8SFmode : if ( TARGET_AVX512VL ) code = si ? IX86_BUILTIN_GATHER3SIV8SF : IX86_BUILTIN_GATHER3ALTDIV8SF ; else code = si ? IX86_BUILTIN_GATHERSIV8SF : IX86_BUILTIN_GATHERALTDIV8SF ; break ; case E_V4SImode : if ( TARGET_AVX512VL ) code = si ? IX86_BUILTIN_GATHER3SIV4SI : IX86_BUILTIN_GATHER3DIV4SI ; else code = si ? IX86_BUILTIN_GATHERSIV4SI : IX86_BUILTIN_GATHERDIV4SI ; break ; case E_V8SImode : if ( TARGET_AVX512VL ) code = si ? IX86_BUILTIN_GATHER3SIV8SI : IX86_BUILTIN_GATHER3ALTDIV8SI ; else code = si ? IX86_BUILTIN_GATHERSIV8SI : IX86_BUILTIN_GATHERALTDIV8SI ; break ; case E_V8DFmode : if ( TARGET_AVX512F ) code = si ? IX86_BUILTIN_GATHER3ALTSIV8DF : IX86_BUILTIN_GATHER3DIV8DF ; else return NULL_TREE ; break ; case E_V8DImode : if ( TARGET_AVX512F ) code = si ? IX86_BUILTIN_GATHER3ALTSIV8DI : IX86_BUILTIN_GATHER3DIV8DI ; else return NULL_TREE ; break ; case E_V16SFmode : if ( TARGET_AVX512F ) code = si ? IX86_BUILTIN_GATHER3SIV16SF : IX86_BUILTIN_GATHER3ALTDIV16SF ; else return NULL_TREE ; break ; case E_V16SImode : if ( TARGET_AVX512F ) code = si ? IX86_BUILTIN_GATHER3SIV16SI : IX86_BUILTIN_GATHER3ALTDIV16SI ; else return NULL_TREE ; break ; default : return NULL_TREE ; } return ix86_get_builtin ( code ) ; } </s>

Returns a decl of a function that implements gather load with memory type MEM_VECTYPE and index type INDEX_VECTYPE and SCALE . Return NULL_TREE if it is not available .


<s> BitVector J2RegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { static constexpr MCPhysReg ReservedRegs [ ] = { J2 :: R15 , J2 :: SR , J2 :: GBR , J2 :: VBR , J2 :: MACH , J2 :: MACL , J2 :: PR , J2 :: PC } ; BitVector Reserved ( getNumRegs ( ) ) ; for ( auto Reg : ReservedRegs ) Reserved . set ( Reg ) ; return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s> virtual const DataLayout * getDataLayout ( ) const { return & DL ; } </s>


<s> void X86FrameLowering :: processFunctionBeforeFrameFinalized ( MachineFunction & MF , RegScavenger * RS ) const { const Function * Fn = MF . getFunction ( ) ; if ( ! STI . is64Bit ( ) || ! MF . hasEHFunclets ( ) || classifyEHPersonality ( Fn -> getPersonalityFn ( ) ) != EHPersonality :: MSVC_CXX ) return ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; WinEHFuncInfo & EHInfo = * MF . getWinEHFuncInfo ( ) ; int64_t MinFixedObjOffset = - SlotSize ; for ( int I = MFI . getObjectIndexBegin ( ) ; I < 0 ; ++ I ) MinFixedObjOffset = std :: min ( MinFixedObjOffset , MFI . getObjectOffset ( I ) ) ; for ( WinEHTryBlockMapEntry & TBME : EHInfo . TryBlockMap ) { for ( WinEHHandlerType & H : TBME . HandlerArray ) { int FrameIndex = H . CatchObj . FrameIndex ; if ( FrameIndex != INT_MAX ) { unsigned Align = MFI . getObjectAlignment ( FrameIndex ) ; MinFixedObjOffset -= std :: abs ( MinFixedObjOffset ) % Align ; MinFixedObjOffset -= MFI . getObjectSize ( FrameIndex ) ; MFI . setObjectOffset ( FrameIndex , MinFixedObjOffset ) ; } } } MinFixedObjOffset -= std :: abs ( MinFixedObjOffset ) % 8 ; int64_t UnwindHelpOffset = MinFixedObjOffset - SlotSize ; int UnwindHelpFI = MFI . CreateFixedObject ( SlotSize , UnwindHelpOffset , false ) ; EHInfo . UnwindHelpFrameIdx = UnwindHelpFI ; MachineBasicBlock & MBB = MF . front ( ) ; auto MBBI = MBB . begin ( ) ; while ( MBBI != MBB . end ( ) && MBBI -> getFlag ( MachineInstr :: FrameSetup ) ) ++ MBBI ; DebugLoc DL = MBB . findDebugLoc ( MBBI ) ; addFrameReference ( BuildMI ( MBB , MBBI , DL , TII . get ( X86 :: MOV64mi32 ) ) , UnwindHelpFI ) . addImm ( - 2 ) ; } </s>

processFunctionBeforeFrameFinalized - This method is called immediately before the specified function 's frame layout ( MF.getFrameInfo ( ) ) is finalized .


<s> bool runOnMachineFunction ( MachineFunction & MF ) override { TII = MF . getSubtarget ( ) . getInstrInfo ( ) ; bool Changed = false ; if ( MF . size ( ) < 2 ) return Changed ; for ( MachineFunction :: iterator I = MF . begin ( ) ; I != MF . end ( ) ; ) { MachineBasicBlock & B = * I ++ ; if ( processBlock ( B ) ) Changed = true ; } return Changed ; } </s>


<s> unsigned X86TargetLowering :: ComputeNumSignBitsForTargetNode ( SDValue Op , unsigned Depth ) const { if ( Op . getOpcode ( ) == X86ISD :: SETCC_CARRY ) return Op . getValueType ( ) . getScalarType ( ) . getSizeInBits ( ) ; return 1 ; } </s>

Determine the number of bits in the operation that are sign bits .


<s> static rtx_insn * next_nonnote_insn_bb ( rtx_insn * insn ) { while ( insn ) { insn = NEXT_INSN ( insn ) ; if ( insn == 0 || ! NOTE_P ( insn ) ) break ; if ( NOTE_INSN_BASIC_BLOCK_P ( insn ) ) return NULL ; } return insn ; } </s>

Return the next insn after INSN that is not a NOTE , but stop the search before we enter another basic block . This routine does not look inside SEQUENCEs .


<s> EVT ARMTargetLowering :: getSetCCResultType ( LLVMContext & , EVT VT ) const { if ( ! VT . isVector ( ) ) return getPointerTy ( ) ; return VT . changeVectorElementTypeToInteger ( ) ; } </s>

Return the value type to use for ISD : :SETCC .


<s> bool AArch64TargetLowering :: CanLowerReturn ( CallingConv :: ID CallConv , MachineFunction & MF , bool isVarArg , const SmallVectorImpl < ISD :: OutputArg > & Outs , LLVMContext & Context ) const { CCAssignFn * RetCC = CallConv == CallingConv :: WebKit_JS ? RetCC_AArch64_WebKit_JS : RetCC_AArch64_AAPCS ; SmallVector < CCValAssign , 16 > RVLocs ; CCState CCInfo ( CallConv , isVarArg , MF , RVLocs , Context ) ; return CCInfo . CheckReturn ( Outs , RetCC ) ; } </s>

This hook should be implemented to check whether the return values described by the Outs array can fit into the return registers .


<s> bool AVRTargetLowering :: getPostIndexedAddressParts ( SDNode * N , SDNode * Op , SDValue & Base , SDValue & Offset , ISD :: MemIndexedMode & AM , SelectionDAG & DAG ) const { EVT VT ; SDLoc DL ( N ) ; if ( const LoadSDNode * LD = dyn_cast < LoadSDNode > ( N ) ) { VT = LD -> getMemoryVT ( ) ; if ( LD -> getExtensionType ( ) != ISD :: NON_EXTLOAD ) return false ; } else if ( const StoreSDNode * ST = dyn_cast < StoreSDNode > ( N ) ) { VT = ST -> getMemoryVT ( ) ; if ( AVR :: isProgramMemoryAccess ( ST ) ) { return false ; } } else { return false ; } if ( VT != MVT :: i8 && VT != MVT :: i16 ) { return false ; } if ( Op -> getOpcode ( ) != ISD :: ADD && Op -> getOpcode ( ) != ISD :: SUB ) { return false ; } if ( const ConstantSDNode * RHS = dyn_cast < ConstantSDNode > ( Op -> getOperand ( 1 ) ) ) { int RHSC = RHS -> getSExtValue ( ) ; if ( Op -> getOpcode ( ) == ISD :: SUB ) RHSC = - RHSC ; if ( ( VT == MVT :: i16 && RHSC != 2 ) || ( VT == MVT :: i8 && RHSC != 1 ) ) { return false ; } Base = Op -> getOperand ( 0 ) ; Offset = DAG . getConstant ( RHSC , DL , MVT :: i8 ) ; AM = ISD :: POST_INC ; return true ; } return false ; } </s>

Returns true by value , base pointer and offset pointer and addressing mode by reference if this node can be combined with a load / store to form a post-indexed load / store .


<s> const char * OpenRISCTargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( Opcode ) { default : return NULL ; case OpenRISCISD :: RET_FLAG : return "OpenRISCISD::RET_FLAG" ; case OpenRISCISD :: CALL : return "OpenRISCISD::CALL" ; } } </s>

getTargetNodeName - This method returns the name of a target specific

OpenRISC OpenRISC OpenRISCISD::RET_FLAG "OpenRISCISD::RET_FLAG" OpenRISCISD::CALL "OpenRISCISD::CALL"


<s> void applyFixup ( const MCFixup & Fixup , char * Data , unsigned DataSize , uint64_t Value ) const { MCFixupKind Kind = Fixup . getKind ( ) ; Value = adjustFixupValue ( ( unsigned ) Kind , Value ) ; if ( ! Value ) return ; unsigned Offset = Fixup . getOffset ( ) ; unsigned NumBytes = ( getFixupKindInfo ( Kind ) . TargetSize + 7 ) / 8 ; unsigned FullSize ; FullSize = 4 ; uint64_t CurVal = 0 ; for ( unsigned i = 0 ; i != NumBytes ; ++ i ) { unsigned Idx = i ; CurVal |= ( uint64_t ) ( ( uint8_t ) Data [ Offset + Idx ] ) << ( i * 8 ) ; } uint64_t Mask = ( ( uint64_t ) ( - 1 ) >> ( 64 - getFixupKindInfo ( Kind ) . TargetSize ) ) ; CurVal |= Value & Mask ; for ( unsigned i = 0 ; i != NumBytes ; ++ i ) { unsigned Idx = i ; Data [ Offset + Idx ] = ( uint8_t ) ( ( CurVal >> ( i * 8 ) ) & 0xff ) ; } } </s>

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


<s> void ARMTargetLowering :: insertSSPDeclarations ( Module & M ) const { if ( ! Subtarget -> getTargetTriple ( ) . isWindowsMSVCEnvironment ( ) ) return TargetLowering :: insertSSPDeclarations ( M ) ; M . getOrInsertGlobal ( "__security_cookie" , Type :: getInt8PtrTy ( M . getContext ( ) ) ) ; FunctionCallee SecurityCheckCookie = M . getOrInsertFunction ( "__security_check_cookie" , Type :: getVoidTy ( M . getContext ( ) ) , Type :: getInt8PtrTy ( M . getContext ( ) ) ) ; if ( Function * F = dyn_cast < Function > ( SecurityCheckCookie . getCallee ( ) ) ) F -> addParamAttr ( 0 , Attribute :: AttrKind :: InReg ) ; } </s>

Inserts necessary declarations for SSP ( stack protection ) purpose .


<s> int GCNTTIImpl :: getIntrinsicInstrCost ( const IntrinsicCostAttributes & ICA , TTI :: TargetCostKind CostKind ) { if ( ! intrinsicHasPackedVectorBenefit ( ICA . getID ( ) ) ) return BaseT :: getIntrinsicInstrCost ( ICA , CostKind ) ; Type * RetTy = ICA . getReturnType ( ) ; EVT OrigTy = TLI -> getValueType ( DL , RetTy ) ; if ( ! OrigTy . isSimple ( ) ) { return BaseT :: getIntrinsicInstrCost ( ICA , CostKind ) ; } std :: pair < int , MVT > LT = TLI -> getTypeLegalizationCost ( DL , RetTy ) ; unsigned NElts = LT . second . isVector ( ) ? LT . second . getVectorNumElements ( ) : 1 ; MVT :: SimpleValueType SLT = LT . second . getScalarType ( ) . SimpleTy ; if ( SLT == MVT :: f64 ) return LT . first * NElts * get64BitInstrCost ( ) ; if ( ST -> has16BitInsts ( ) && SLT == MVT :: f16 ) NElts = ( NElts + 1 ) / 2 ; unsigned InstRate = getQuarterRateInstrCost ( ) ; if ( ICA . getID ( ) == Intrinsic :: fma ) { InstRate = ST -> hasFastFMAF32 ( ) ? getHalfRateInstrCost ( ) : getQuarterRateInstrCost ( ) ; } return LT . first * NElts * InstRate ; } </s>


<s> void NVPTXPassConfig :: addIRPasses ( ) { disablePass ( & PrologEpilogCodeInserterID ) ; disablePass ( & MachineCopyPropagationID ) ; disablePass ( & TailDuplicateID ) ; disablePass ( & StackMapLivenessID ) ; disablePass ( & LiveDebugValuesID ) ; disablePass ( & PostRAMachineSinkingID ) ; disablePass ( & PostRASchedulerID ) ; disablePass ( & FuncletLayoutID ) ; disablePass ( & PatchableFunctionID ) ; disablePass ( & ShrinkWrapID ) ; const NVPTXSubtarget & ST = * getTM < NVPTXTargetMachine > ( ) . getSubtargetImpl ( ) ; addPass ( createNVVMReflectPass ( ST . getSmVersion ( ) ) ) ; if ( getTM < NVPTXTargetMachine > ( ) . getTargetTriple ( ) . getOS ( ) == Triple :: CUDA && getTM < NVPTXTargetMachine > ( ) . getTargetTriple ( ) . getEnvironment ( ) == Triple :: SYCLDevice ) { addPass ( createLocalAccessorToSharedMemoryPass ( ) ) ; } if ( getOptLevel ( ) != CodeGenOpt :: None ) addPass ( createNVPTXImageOptimizerPass ( ) ) ; addPass ( createNVPTXAssignValidGlobalNamesPass ( ) ) ; addPass ( createGenericToNVVMPass ( ) ) ; addPass ( createNVPTXLowerArgsPass ( & getNVPTXTargetMachine ( ) ) ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) { addAddressSpaceInferencePasses ( ) ; addStraightLineScalarOptimizationPasses ( ) ; } TargetPassConfig :: addIRPasses ( ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) { addEarlyCSEOrGVNPass ( ) ; if ( ! DisableLoadStoreVectorizer ) addPass ( createLoadStoreVectorizerPass ( ) ) ; } } </s>

Add common target configurable passes that perform LLVM IR to IR transforms following machine independent optimization .

NVPTX NVPTX NVPTX NVPTX NVPTX NVPTX NVPTX NVPTX NVPTX NVPTX


<s>
void
AArch64AsmBackend
::
applyFixup
(
const
MCAssembler
&
Asm
,
const
MCFixup
&
Fixup
,
const
MCValue
&
Target
,
MutableArrayRef
<
char
>
Data
,
uint64_t
Value
,
bool
IsResolved
,
const
MCSubtargetInfo
*
STI
)
const
{
unsigned
NumBytes
=
getFixupKindNumBytes
(
Fixup
.
getKind
(
)
)
;
if
(
!
Value
)
return
;
MCFixupKindInfo
Info
=
getFixupKindInfo
(
Fixup
.
getKind
(
)
)
;
MCContext
&
Ctx
=
Asm
.
getContext
(
)
;
Value
=
adjustFixupValue
(
Fixup
,
Value
,
Ctx
,
TheTriple
,
IsResolved
)
;
Value
<<=
Info
.
TargetOffset
;
unsigned
Offset
=
Fixup
.
getOffset
(
)
;
assert
(
Offset
+
NumBytes
<=
Data
.
size
(
)
&&
"Invalid fixup offset!"
)
;
unsigned
FulleSizeInBytes
=
getFixupKindContainereSizeInBytes
(
Fixup
.
getKind
(
)
)
;
if
(
FulleSizeInBytes
==
0
)
{
for
(
unsigned
i
=
0
;
i
!=
NumBytes
;
++
i
)
{
Data
[
Offset
+
i
]
|=
uint8_t
(
(
Value
>>
(
i
*
8
)
)
&
0xff
)
;
}
}
else
{
assert
(
(
Offset
+
FulleSizeInBytes
)
<=
Data
.
size
(
)
&&
"Invalid fixup size!"
)
;
assert
(
NumBytes
<=
FulleSizeInBytes
&&
"Invalid fixup size!"
)
;
for
(
unsigned
i
=
0
;
i
!=
NumBytes
;
++
i
)
{
unsigned
Idx
=
FulleSizeInBytes
1
i
;
Data
[
Offset
+
Idx
]
|=
uint8_t
(
(
Value
>>
(
i
*
8
)
)
&
0xff
)
;
}
}
}
</s>


<s> static int s390_sched_score ( rtx_insn * insn ) { unsigned int mask = s390_get_sched_attrmask ( insn ) ; int score = 0 ; switch ( s390_sched_state ) { case 0 : if ( ( mask & S390_SCHED_ATTR_MASK_CRACKED ) != 0 || ( mask & S390_SCHED_ATTR_MASK_EXPANDED ) != 0 ) score += 5 ; if ( ( mask & S390_SCHED_ATTR_MASK_GROUPALONE ) != 0 ) score += 10 ; case 1 : if ( ( mask & S390_SCHED_ATTR_MASK_CRACKED ) == 0 && ( mask & S390_SCHED_ATTR_MASK_EXPANDED ) == 0 && ( mask & S390_SCHED_ATTR_MASK_GROUPALONE ) == 0 ) score += 10 ; if ( ( mask & S390_SCHED_ATTR_MASK_ENDGROUP ) == 0 ) score += 5 ; break ; case 2 : if ( ( mask & S390_SCHED_ATTR_MASK_CRACKED ) == 0 && ( mask & S390_SCHED_ATTR_MASK_EXPANDED ) == 0 && ( mask & S390_SCHED_ATTR_MASK_GROUPALONE ) == 0 ) score += 10 ; if ( ( mask & S390_SCHED_ATTR_MASK_ENDGROUP ) != 0 ) score += 10 ; break ; case S390_SCHED_STATE_NORMAL : if ( ( mask & S390_SCHED_ATTR_MASK_CRACKED ) == 0 && ( mask & S390_SCHED_ATTR_MASK_EXPANDED ) == 0 ) score += 5 ; if ( ( mask & S390_SCHED_ATTR_MASK_GROUPALONE ) != 0 ) score += 10 ; break ; case S390_SCHED_STATE_CRACKED : if ( ( mask & S390_SCHED_ATTR_MASK_CRACKED ) != 0 || ( mask & S390_SCHED_ATTR_MASK_EXPANDED ) != 0 ) score += 5 ; break ; } if ( s390_tune == PROCESSOR_2964_Z13 ) { int units , i ; unsigned unit_mask , m = 1 ; unit_mask = s390_get_unit_mask ( insn , & units ) ; gcc_assert ( units <= MAX_SCHED_UNITS ) ; for ( i = 0 ; i < units ; i ++ , m <<= 1 ) if ( m & unit_mask ) score += ( last_scheduled_unit_distance [ i ] * MAX_SCHED_MIX_SCORE / MAX_SCHED_MIX_DISTANCE ) ; } return score ; } </s>

Return the scheduling score for INSN . The higher the score the better . The score is calculated from the OOO scheduling attributes of INSN and the scheduling state s390_sched_state .


<s> BitVector SIRegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; Reserved . set ( AMDGPU :: EXEC ) ; Reserved . set ( AMDGPU :: INDIRECT_BASE_ADDR ) ; Reserved . set ( AMDGPU :: FLAT_SCR ) ; return Reserved ; } </s>


<s> bool PPCAsmParser :: ParseInstruction ( ParseInstructionInfo & Info , StringRef Name , SMLoc NameLoc , OperandVector & Operands ) { std :: string NewOpcode ; if ( parseOptionalToken ( AsmToken :: Plus ) ) { NewOpcode = std :: string ( Name ) ; NewOpcode += '+' ; Name = NewOpcode ; } if ( parseOptionalToken ( AsmToken :: Minus ) ) { NewOpcode = std :: string ( Name ) ; NewOpcode += '-' ; Name = NewOpcode ; } size_t Dot = Name . find ( '.' ) ; StringRef Mnemonic = Name . slice ( 0 , Dot ) ; if ( ! NewOpcode . empty ( ) ) Operands . push_back ( PPCOperand :: CreateTokenWithStringCopy ( Mnemonic , NameLoc , isPPC64 ( ) ) ) ; else Operands . push_back ( PPCOperand :: CreateToken ( Mnemonic , NameLoc , isPPC64 ( ) ) ) ; if ( Dot != StringRef :: npos ) { SMLoc DotLoc = SMLoc :: getFromPointer ( NameLoc . getPointer ( ) + Dot ) ; StringRef DotStr = Name . slice ( Dot , StringRef :: npos ) ; if ( ! NewOpcode . empty ( ) ) Operands . push_back ( PPCOperand :: CreateTokenWithStringCopy ( DotStr , DotLoc , isPPC64 ( ) ) ) ; else Operands . push_back ( PPCOperand :: CreateToken ( DotStr , DotLoc , isPPC64 ( ) ) ) ; } if ( parseOptionalToken ( AsmToken :: EndOfStatement ) ) return false ; if ( ParseOperand ( Operands ) ) return true ; while ( ! parseOptionalToken ( AsmToken :: EndOfStatement ) ) { if ( parseToken ( AsmToken :: Comma ) || ParseOperand ( Operands ) ) return true ; } if ( getSTI ( ) . getFeatureBits ( ) [ PPC :: FeatureBookE ] && Operands . size ( ) == 4 && ( Name == "dcbt" || Name == "dcbtst" ) ) { std :: swap ( Operands [ 1 ] , Operands [ 3 ] ) ; std :: swap ( Operands [ 2 ] , Operands [ 1 ] ) ; } return false ; } </s>

ParseInstruction - Parse one assembly instruction .

PowerPC PPC 0 PPC PPC PPC PPC PPC PPC PPC PPC PPC::FeatureBookE 4 "dcbt" "dcbtst" 1 3 2 1


<s> tree aarch64_general_fold_builtin ( unsigned int fcode , tree type , unsigned int n_args ATTRIBUTE_UNUSED , tree * args ) { switch ( fcode ) { BUILTIN_VDQF ( UNOP , abs , 2 , ALL ) return fold_build1 ( ABS_EXPR , type , args [ 0 ] ) ; VAR1 ( UNOP , floatv2si , 2 , ALL , v2sf ) VAR1 ( UNOP , floatv4si , 2 , ALL , v4sf ) VAR1 ( UNOP , floatv2di , 2 , ALL , v2df ) return fold_build1 ( FLOAT_EXPR , type , args [ 0 ] ) ; AARCH64_SIMD_VREINTERPRET_BUILTINS return fold_build1 ( VIEW_CONVERT_EXPR , type , args [ 0 ] ) ; case AARCH64_SIMD_BUILTIN_LANE_CHECK : gcc_assert ( n_args == 3 ) ; if ( aarch64_fold_builtin_lane_check ( args [ 0 ] , args [ 1 ] , args [ 2 ] ) ) return void_node ; break ; default : break ; } return NULL_TREE ; } </s>

Try to fold a call to the built-in function with subcode FCODE . The function is passed the N_ARGS arguments in ARGS and it returns a value of type TYPE . Return the new expression on success and NULL_TREE on failure .


<s> bool s390_can_use_return_insn ( void ) { int i ; if ( ! reload_completed ) return false ; if ( crtl -> profile ) return false ; if ( TARGET_TPF_PROFILING ) return false ; for ( i = 0 ; i < 16 ; i ++ ) if ( cfun_gpr_save_slot ( i ) != SAVE_SLOT_NONE ) return false ; if ( ! TARGET_64BIT && ( cfun_fpr_save_p ( FPR4_REGNUM ) || cfun_fpr_save_p ( FPR6_REGNUM ) ) ) return false ; if ( cfun -> machine -> base_reg && ! call_used_regs [ REGNO ( cfun -> machine -> base_reg ) ] ) return false ; return cfun_frame_layout . frame_size == 0 ; } </s>

Return true if the epilogue is guaranteed to contain only a return instruction and if a direct return can therefore be used instead . One of the main advantages of using direct return instructions is that we can then use conditional returns .


<s> void X86FrameLowering :: emitStackProbe ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI , const DebugLoc & DL , bool InProlog ) const { const X86Subtarget & STI = MF . getSubtarget < X86Subtarget > ( ) ; if ( STI . isTargetWindowsCoreCLR ( ) ) { if ( InProlog ) { emitStackProbeInlineStub ( MF , MBB , MBBI , DL , true ) ; } else { emitStackProbeInline ( MF , MBB , MBBI , DL , false ) ; } } else { emitStackProbeCall ( MF , MBB , MBBI , DL , InProlog ) ; } } </s>


<s> void applyFixup ( const MCFixup & Fixup , MutableArrayRef < char > Data , uint64_t Value , bool IsPCRel , MCContext & Ctx ) const override { Value = adjustFixupValue ( Fixup . getKind ( ) , Value ) ; if ( ! Value ) return ; unsigned Offset = Fixup . getOffset ( ) ; unsigned NumBytes = getFixupKindNumBytes ( Fixup . getKind ( ) ) ; for ( unsigned i = 0 ; i != NumBytes ; ++ i ) { unsigned Idx = IsLittleEndian ? i : ( NumBytes - 1 - i ) ; Data [ Offset + i ] |= uint8_t ( ( Value >> ( Idx * 8 ) ) & 0xff ) ; } } </s>


<s>
const
MCPhysReg
*
AArch64RegisterInfo
::
getCalleeSavedRegs
(
const
MachineFunction
*
MF
)
const
{
assert
(
MF
&&
"Invalid MachineFunction pointer."
)
;
if
(
MF
->
getFunction
(
)
.
getCallingConv
(
)
==
CallingConv
::
GHC
)
return
CSR_AArch64_NoRegs_SaveList
;
if
(
MF
->
getFunction
(
)
.
getCallingConv
(
)
==
CallingConv
::
AnyReg
)
return
CSR_AArch64_AllRegs_SaveList
;
if
(
MF
->
getSubtarget
<
AArch64Subtarget
>
(
)
.
isTargetDarwin
(
)
)
return
getDarwinCalleeSavedRegs
(
MF
)
;
if
(
MF
->
getFunction
(
)
.
getCallingConv
(
)
==
CallingConv
::
CFGuard_Check
)
return
CSR_Win_AArch64_CFGuard_Check_SaveList
;
if
(
MF
->
getSubtarget
<
AArch64Subtarget
>
(
)
.
isTargetWindows
(
)
)
return
CSR_Win_AArch64_AAPCS_SaveList
;
if
(
MF
->
getFunction
(
)
.
getCallingConv
(
)
==
CallingConv
::
AArch64_VectorCall
)
return
CSR_AArch64_AAVPCS_SaveList
;
if
(
MF
->
getFunction
(
)
.
getCallingConv
(
)
==
CallingConv
::
AArch64_SVE_VectorCall
)
return
CSR_AArch64_SVE_AAPCS_SaveList
;
if
(
MF
->
getSubtarget
<
AArch64Subtarget
>
(
)
.
getTargetLowering
(
)
->
supportSwiftError
(
)
&&
MF
->
getFunction
(
)
.
getAttributes
(
)
.
hasAttrSomewhere
(
Attribute
::
SwiftError
)
)
return
CSR_AArch64_AAPCS_SwiftError_SaveList
;
if
(
MF
->
getFunction
(
)
.
getCallingConv
(
)
==
CallingConv
::
PreserveMost
)
return
CSR_AArch64_RT_MostRegs_SaveList
;
return
CSR_AArch64_AAPCS_SaveList
;
}
</s>


<s>
void
print
(
raw_ostream
&
OS
)
const
override
{
switch
(
Kind
)
{
case
k_Immediate
:
OS
<<
"Imm<"
;
OS
<<
*
Imm
.
Val
;
OS
<<
">"
;
break
;
case
k_Memory
:
OS
<<
"Mem<"
;
Mem
.
Base
->
print
(
OS
)
;
OS
<<
", "
;
OS
<<
*
Mem
.
Off
;
OS
<<
">"
;
break
;
case
k_RegisterIndex
:
OS
<<
"RegIdx<"
<<
RegIdx
.
Index
<<
":"
<<
RegIdx
.
Kind
<<
", "
<<
StringRef
(
RegIdx
.
Tok
.
Data
,
RegIdx
.
Tok
.
Length
)
<<
">"
;
break
;
case
k_Token
:
OS
<<
getToken
(
)
;
break
;
case
k_RegList
:
OS
<<
"RegList< "
;
for
(
auto
Reg
:
(
*
RegList
.
List
)
)
OS
<<
Reg
<<
" "
;
OS
<<
">"
;
break
;
case
k_RegPair
:
OS
<<
"RegPair<"
<<
RegIdx
.
Index
<<
","
<<
RegIdx
.
Index
+
1
<<
">"
;
break
;
}
}
</s>

print - Print a debug representation of the operand to the given stream .


<s> bool TPCFrameLowering :: hasReservedCallFrame ( const MachineFunction & MF ) const { return false ; } </s>

hasReservedCallFrame - Under normal circumstances , when a frame pointer is not required , we reserve argument space for call sites in the function immediately on entry to the current function .


<s> static void rs6000_set_sched_context ( void * _sc ) { rs6000_sched_context_t sc = ( rs6000_sched_context_t ) _sc ; gcc_assert ( sc != NULL ) ; cached_can_issue_more = sc -> cached_can_issue_more ; last_scheduled_insn = sc -> last_scheduled_insn ; load_store_pendulum = sc -> load_store_pendulum ; divide_cnt = sc -> divide_cnt ; vec_pairing = sc -> vec_pairing ; } </s>

Sets the global scheduling context to the one pointed to by _SC .


<s> SMLoc getLoc ( ) const { return getParser ( ) . getTok ( ) . getLoc ( ) ; } </s>

Get the source location of the point where the field was defined .


<s> DecodeStatus BPFDisassembler :: getInstruction ( MCInst & Instr , uint64_t & Size , ArrayRef < uint8_t > Bytes , uint64_t Address , raw_ostream & VStream , raw_ostream & CStream ) const { bool IsLittleEndian = getContext ( ) . getAsmInfo ( ) -> isLittleEndian ( ) ; uint64_t Insn , Hi ; DecodeStatus Result ; Result = readInstruction64 ( Bytes , Address , Size , Insn , IsLittleEndian ) ; if ( Result == MCDisassembler :: Fail ) return MCDisassembler :: Fail ; uint8_t InstClass = getInstClass ( Insn ) ; uint8_t InstMode = getInstMode ( Insn ) ; if ( ( InstClass == BPF_LDX || InstClass == BPF_STX ) && getInstSize ( Insn ) != BPF_DW && ( InstMode == BPF_MEM || InstMode == BPF_XADD ) && STI . getFeatureBits ( ) [ BPF :: ALU32 ] ) Result = decodeInstruction ( DecoderTableBPFALU3264 , Instr , Insn , Address , this , STI ) ; else Result = decodeInstruction ( DecoderTableBPF64 , Instr , Insn , Address , this , STI ) ; if ( Result == MCDisassembler :: Fail ) return MCDisassembler :: Fail ; switch ( Instr . getOpcode ( ) ) { case BPF :: LD_imm64 : case BPF :: LD_pseudo : { if ( Bytes . size ( ) < 16 ) { Size = 0 ; return MCDisassembler :: Fail ; } Size = 16 ; if ( IsLittleEndian ) Hi = ( Bytes [ 12 ] << 0 ) | ( Bytes [ 13 ] << 8 ) | ( Bytes [ 14 ] << 16 ) | ( Bytes [ 15 ] << 24 ) ; else Hi = ( Bytes [ 12 ] << 24 ) | ( Bytes [ 13 ] << 16 ) | ( Bytes [ 14 ] << 8 ) | ( Bytes [ 15 ] << 0 ) ; auto & Op = Instr . getOperand ( 1 ) ; Op . setImm ( Make_64 ( Hi , Op . getImm ( ) ) ) ; break ; } case BPF :: LD_ABS_B : case BPF :: LD_ABS_H : case BPF :: LD_ABS_W : case BPF :: LD_IND_B : case BPF :: LD_IND_H : case BPF :: LD_IND_W : { auto Op = Instr . getOperand ( 0 ) ; Instr . clear ( ) ; Instr . addOperand ( MCOperand :: createReg ( BPF :: R6 ) ) ; Instr . addOperand ( Op ) ; break ; } } return Result ; } </s>

Returns the disassembly of a single instruction .


<s> bool X86FastTileConfig :: runOnMachineFunction ( MachineFunction & MFunc ) { MF = & MFunc ; MRI = & MFunc . getRegInfo ( ) ; ST = & MFunc . getSubtarget < X86Subtarget > ( ) ; TRI = ST -> getRegisterInfo ( ) ; TII = MFunc . getSubtarget ( ) . getInstrInfo ( ) ; X86FI = MFunc . getInfo < X86MachineFunctionInfo > ( ) ; return fastTileConfig ( ) ; } </s>

runOnMachineFunction - Emit the function body .


<s> bool X86InstrInfo :: isCoalescableExtInstr ( const MachineInstr & MI , unsigned & SrcReg , unsigned & DstReg , unsigned & SubIdx ) const { switch ( MI . getOpcode ( ) ) { default : break ; case X86 :: MOVSX16rr8 : case X86 :: MOVZX16rr8 : case X86 :: MOVSX32rr8 : case X86 :: MOVZX32rr8 : case X86 :: MOVSX64rr8 : case X86 :: MOVZX64rr8 : if ( ! TM . getSubtarget < X86Subtarget > ( ) . is64Bit ( ) ) return false ; case X86 :: MOVSX32rr16 : case X86 :: MOVZX32rr16 : case X86 :: MOVSX64rr16 : case X86 :: MOVZX64rr16 : case X86 :: MOVSX64rr32 : case X86 :: MOVZX64rr32 : { if ( MI . getOperand ( 0 ) . getSubReg ( ) || MI . getOperand ( 1 ) . getSubReg ( ) ) return false ; SrcReg = MI . getOperand ( 1 ) . getReg ( ) ; DstReg = MI . getOperand ( 0 ) . getReg ( ) ; switch ( MI . getOpcode ( ) ) { default : llvm_unreachable ( "Unreachable!" ) ; case X86 :: MOVSX16rr8 : case X86 :: MOVZX16rr8 : case X86 :: MOVSX32rr8 : case X86 :: MOVZX32rr8 : case X86 :: MOVSX64rr8 : case X86 :: MOVZX64rr8 : SubIdx = X86 :: sub_8bit ; break ; case X86 :: MOVSX32rr16 : case X86 :: MOVZX32rr16 : case X86 :: MOVSX64rr16 : case X86 :: MOVZX64rr16 : SubIdx = X86 :: sub_16bit ; break ; case X86 :: MOVSX64rr32 : case X86 :: MOVZX64rr32 : SubIdx = X86 :: sub_32bit ; break ; } return true ; } } return false ; } </s>

isCoalescableExtInstr - Return true if the instruction is a `` coalescable '' extension instruction .


<s> bool AArch64LoadStoreOpt :: runOnMachineFunction ( MachineFunction & Fn ) { if ( skipFunction ( Fn . getFunction ( ) ) ) return false ; Subtarget = & static_cast < const AArch64Subtarget & > ( Fn . getSubtarget ( ) ) ; TII = static_cast < const AArch64InstrInfo * > ( Subtarget -> getInstrInfo ( ) ) ; TRI = Subtarget -> getRegisterInfo ( ) ; AA = & getAnalysis < AAResultsWrapperPass > ( ) . getAAResults ( ) ; ModifiedRegs . resize ( TRI -> getNumRegs ( ) ) ; UsedRegs . resize ( TRI -> getNumRegs ( ) ) ; bool Modified = false ; bool enableNarrowZeroStOpt = ! Subtarget -> requiresStrictAlign ( ) ; for ( auto & MBB : Fn ) Modified |= optimizeBlock ( MBB , enableNarrowZeroStOpt ) ; return Modified ; } </s>


<s> bool ARMPassConfig :: addRegBankSelect ( ) { addPass ( new RegBankSelect ( ) ) ; return false ; } </s>

This method should install a register bank selector pass , which assigns register banks to virtual registers without a register class or register banks .


<s> void msp430_output_labelref ( FILE * file , const char * name ) { int i ; for ( i = 0 ; helper_function_name_mappings [ i ] . gcc_name ; i ++ ) if ( strcmp ( helper_function_name_mappings [ i ] . gcc_name , name ) == 0 ) { name = helper_function_name_mappings [ i ] . ti_name ; break ; } if ( msp430_hwmult_type != MSP430_HWMULT_NONE ) { if ( strcmp ( "__mspabi_mpyi" , name ) == 0 ) { if ( msp430_use_f5_series_hwmult ( ) ) name = "__mulhi2_f5" ; else if ( ! msp430_no_hwmult ( ) ) name = "__mulhi2" ; } else if ( strcmp ( "__mspabi_mpyl" , name ) == 0 ) { if ( msp430_use_f5_series_hwmult ( ) ) name = "__mulsi2_f5" ; else if ( use_32bit_hwmult ( ) ) name = "__mulsi2_hw32" ; else if ( ! msp430_no_hwmult ( ) ) name = "__mulsi2" ; } } fputs ( name , file ) ; } </s>

This function does the same as the default , but it will replace GCC function names with the MSPABI-specified ones .


<s>
bool
AVRExpandPseudo
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
bool
Modified
=
false
;
const
AVRSubtarget
&
STI
=
MF
.
getSubtarget
<
AVRSubtarget
>
(
)
;
TRI
=
STI
.
getRegisterInfo
(
)
;
TII
=
STI
.
getInstrInfo
(
)
;
MF
.
getProperties
(
)
.
set
(
MachineFunctionProperties
::
Property
::
TracksLiveness
)
;
for
(
Block
&
MBB
:
MF
)
{
bool
ContinueExpanding
=
true
;
unsigned
ExpandCount
=
0
;
do
{
assert
(
ExpandCount
<
10
&&
"pseudo expand limit reached"
)
;
(
void
)
ExpandCount
;
bool
BlockModified
=
expandMBB
(
MBB
)
;
Modified
|=
BlockModified
;
ExpandCount
++
;
ContinueExpanding
=
BlockModified
;
}
while
(
ContinueExpanding
)
;
}
return
Modified
;
}
</s>

AVR
AVR
AVR
AVR
0
10
"pseudo expand limit reached"


<s> bool Thumb1FrameLowering :: canUseAsEpilogue ( const MachineBasicBlock & MBB ) const { if ( ! needPopSpecialFixUp ( * MBB . getParent ( ) ) ) return true ; MachineBasicBlock * TmpMBB = const_cast < MachineBasicBlock * > ( & MBB ) ; return emitPopSpecialFixUp ( * TmpMBB , false ) ; } </s>

Check whether or not the given MBB can be used as a epilogue for the target .