<s>
void
print_operand_address
(
FILE
*
file
,
rtx
addr
)
{
struct
microblaze_address_info
info
;
enum
microblaze_address_type
type
;
if
(
!
microblaze_classify_address
(
&
info
,
addr
,
GET_MODE
(
addr
)
,
2
)
)
fatal_insn
(
"insn contains an invalid address !"
,
addr
)
;
type
=
info
.
type
;
switch
(
info
.
type
)
{
case
ADDRESS_REG
:
fprintf
(
file
,
"%s,"
,
reg_names
[
REGNO
(
info
.
regA
)
]
)
;
output_addr_const
(
file
,
info
.
offset
)
;
break
;
case
ADDRESS_REG_INDEX
:
if
(
REGNO
(
info
.
regA
)
==
0
)
fprintf
(
file
,
"%s,%s"
,
reg_names
[
REGNO
(
info
.
regB
)
]
,
reg_names
[
REGNO
(
info
.
regA
)
]
)
;
else
if
(
REGNO
(
info
.
regB
)
!=
0
)
fprintf
(
file
,
"%s,%s"
,
reg_names
[
REGNO
(
info
.
regB
)
]
,
reg_names
[
REGNO
(
info
.
regA
)
]
)
;
break
;
case
ADDRESS_CONST_INT
:
fprintf
(
file
,
"%s,"
,
reg_names
[
REGNO
(
info
.
regA
)
]
)
;
output_addr_const
(
file
,
info
.
offset
)
;
break
;
case
ADDRESS_SYMBOLIC
:
case
ADDRESS_SYMBOLIC_TXT_REL
:
case
ADDRESS_GOTOFF
:
case
ADDRESS_PLT
:
case
ADDRESS_TLS
:
if
(
info
.
regA
)
fprintf
(
file
,
"%s,"
,
reg_names
[
REGNO
(
info
.
regA
)
]
)
;
output_addr_const
(
file
,
info
.
symbol
)
;
if
(
type
==
ADDRESS_GOTOFF
)
{
fputs
(
"@GOT"
,
file
)
;
}
else
if
(
type
==
ADDRESS_PLT
)
{
fputs
(
"@PLT"
,
file
)
;
}
else
if
(
type
==
ADDRESS_SYMBOLIC_TXT_REL
)
{
if
(
info
.
offset
!=
&&
CONST_INT_P
(
info
.
offset
)
&&
INTVAL
(
info
.
offset
)
>
0
)
{
fprintf
(
file
,
"+"
)
;
output_addr_const
(
file
,
info
.
offset
)
;
}
fputs
(
"@TXTREL"
,
file
)
;
}
else
if
(
type
==
ADDRESS_TLS
)
{
switch
(
info
.
tls_type
)
{
case
TLS_GD
:
fputs
(
"@TLSGD"
,
file
)
;
break
;
case
TLS_LDM
:
fputs
(
"@TLSLDM"
,
file
)
;
break
;
case
TLS_DTPREL
:
fputs
(
"@TLSDTPREL"
,
file
)
;
break
;
default
:
abort
(
)
;
break
;
}
}
break
;
case
ADDRESS_INVALID
:
fatal_insn
(
"invalid address"
,
addr
)
;
break
;
}
}
</s>

Print the operand address represented by the rtx addr


<s> rtx ix86_find_base_term ( rtx x ) { rtx term ; if ( TARGET_64BIT ) { if ( GET_CODE ( x ) != CONST ) return x ; term = XEXP ( x , 0 ) ; if ( GET_CODE ( term ) == PLUS && ( GET_CODE ( XEXP ( term , 1 ) ) == CONST_INT || GET_CODE ( XEXP ( term , 1 ) ) == CONST_DOUBLE ) ) term = XEXP ( term , 0 ) ; if ( GET_CODE ( term ) != UNSPEC || XINT ( term , 1 ) != UNSPEC_GOTPCREL ) return x ; term = XVECEXP ( term , 0 , 0 ) ; if ( GET_CODE ( term ) != SYMBOL_REF && GET_CODE ( term ) != LABEL_REF ) return x ; return term ; } term = ix86_delegitimize_address ( x ) ; if ( GET_CODE ( term ) != SYMBOL_REF && GET_CODE ( term ) != LABEL_REF ) return x ; return term ; } </s>

If X is a machine specific address ( i.e . a symbol or label being referenced as a displacement from the GOT implemented using an UNSPEC ) , then return the base term . Otherwise return X .


<s> void PPCRegisterInfo :: lowerCRSpilling ( MachineBasicBlock :: iterator II , unsigned FrameIndex ) const { MachineInstr & MI = * II ; MachineBasicBlock & MBB = * MI . getParent ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; const PPCSubtarget & Subtarget = MF . getSubtarget < PPCSubtarget > ( ) ; const TargetInstrInfo & TII = * Subtarget . getInstrInfo ( ) ; DebugLoc dl = MI . getDebugLoc ( ) ; bool LP64 = TM . isPPC64 ( ) ; const TargetRegisterClass * G8RC = & PPC :: G8RCRegClass ; const TargetRegisterClass * GPRC = & PPC :: GPRCRegClass ; Register Reg = MF . getRegInfo ( ) . createVirtualRegister ( LP64 ? G8RC : GPRC ) ; Register SrcReg = MI . getOperand ( 0 ) . getReg ( ) ; BuildMI ( MBB , II , dl , TII . get ( LP64 ? PPC :: MFOCRF8 : PPC :: MFOCRF ) , Reg ) . addReg ( SrcReg , getKillRegState ( MI . getOperand ( 0 ) . isKill ( ) ) ) ; if ( SrcReg != PPC :: CR0 ) { unsigned Reg1 = Reg ; Reg = MF . getRegInfo ( ) . createVirtualRegister ( LP64 ? G8RC : GPRC ) ; BuildMI ( MBB , II , dl , TII . get ( LP64 ? PPC :: RLWINM8 : PPC :: RLWINM ) , Reg ) . addReg ( Reg1 , RegState :: Kill ) . addImm ( getEncodingValue ( SrcReg ) * 4 ) . addImm ( 0 ) . addImm ( 31 ) ; } addFrameReference ( BuildMI ( MBB , II , dl , TII . get ( LP64 ? PPC :: STW8 : PPC :: STW ) ) . addReg ( Reg , RegState :: Kill ) , FrameIndex ) ; MBB . erase ( II ) ; } </s>

lowerCRSpilling - Generate the code for spilling a CR register .


<s> static void emit_hard_tfmode_operation ( enum rtx_code code , rtx * operands ) { rtx op , dest ; if ( GET_RTX_CLASS ( code ) == RTX_UNARY ) { operands [ 1 ] = force_reg ( GET_MODE ( operands [ 1 ] ) , operands [ 1 ] ) ; op = gen_rtx_fmt_e ( code , GET_MODE ( operands [ 0 ] ) , operands [ 1 ] ) ; } else { operands [ 1 ] = force_reg ( GET_MODE ( operands [ 1 ] ) , operands [ 1 ] ) ; operands [ 2 ] = force_reg ( GET_MODE ( operands [ 2 ] ) , operands [ 2 ] ) ; op = gen_rtx_fmt_ee ( code , GET_MODE ( operands [ 0 ] ) , operands [ 1 ] , operands [ 2 ] ) ; } if ( register_operand ( operands [ 0 ] , VOIDmode ) ) dest = operands [ 0 ] ; else dest = gen_reg_rtx ( GET_MODE ( operands [ 0 ] ) ) ; emit_insn ( gen_rtx_SET ( VOIDmode , dest , op ) ) ; if ( dest != operands [ 0 ] ) emit_move_insn ( operands [ 0 ] , dest ) ; } </s>

Expand a hard-float tfmode operation . All arguments must be in registers .


If the function has any GOTOFF relocations , then the GOTBASE register has to be setup in the prologue The instruction needed at the function start for setting up the GOTBASE register is add rdest , pc , -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- The rtl to be emitted for this should be : set ( reg basereg ) ( plus ( reg pc ) ( const ( unspec ( symref _DYNAMIC ) 3 ) ) ) -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --


<s>
const
char
*
getPassName
(
)
const
override
{
return
"Windows 32-bit x86 EH state insertion"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s>
void
print
(
raw_ostream
&
OS
)
const
override
{
switch
(
Kind
)
{
case
k_Token
:
OS
<<
"Token: "
<<
getToken
(
)
<<
"\n"
;
break
;
case
k_Register
:
OS
<<
"Reg: #"
<<
getReg
(
)
<<
"\n"
;
break
;
case
k_Immediate
:
OS
<<
"Imm: "
<<
getImm
(
)
<<
"\n"
;
break
;
case
k_MemoryRegRegImm
:
assert
(
getMemOffset
(
)
!=
nullptr
)
;
OS
<<
"Mem: #"
<<
getMemBase
(
)
<<
"+#"
<<
getMemIndexReg
(
)
<<
"+"
<<
*
getMemOffset
(
)
<<
"\n"
;
break
;
case
k_MemoryRegImmImm
:
assert
(
getMemIndex
(
)
!=
nullptr
&&
getMemOffset
(
)
!=
nullptr
)
;
OS
<<
"Mem: #"
<<
getMemBase
(
)
<<
"+"
<<
*
getMemIndex
(
)
<<
"+"
<<
*
getMemOffset
(
)
<<
"\n"
;
break
;
case
k_MemoryZeroRegImm
:
assert
(
getMemOffset
(
)
!=
nullptr
)
;
OS
<<
"Mem: 0+#"
<<
getMemIndexReg
(
)
<<
"+"
<<
*
getMemOffset
(
)
<<
"\n"
;
break
;
case
k_MemoryZeroImmImm
:
assert
(
getMemIndex
(
)
!=
nullptr
&&
getMemOffset
(
)
!=
nullptr
)
;
OS
<<
"Mem: 0+"
<<
*
getMemIndex
(
)
<<
"+"
<<
*
getMemOffset
(
)
<<
"\n"
;
break
;
}
}
</s>

print - Print a debug representation of the operand to the given stream .


<s> static section * aarch64_select_rtx_section ( machine_mode mode ATTRIBUTE_UNUSED , rtx x ATTRIBUTE_UNUSED , unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED ) { return function_section ( current_function_decl ) ; } </s>

Select appropriate section for constants depending on where we place literal pools .


<s> SparcTargetMachine :: SparcTargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL , bool is64bit ) : LLVMTargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL ) , Subtarget ( TT , CPU , FS , is64bit ) , DL ( Subtarget . getDataLayout ( ) ) , InstrInfo ( Subtarget ) , TLInfo ( * this ) , TSInfo ( * this ) , FrameLowering ( Subtarget ) , STTI ( & TLInfo ) , VTTI ( & TLInfo ) { } </s>


<s> void AArch64InstructionSelector :: beginFunction ( const MachineFunction & MF ) { ForCodeSize = MF . getFunction ( ) -> optForSize ( ) ; AvailableFeatures = computeAvailableFeatures ( & MF , & STI ) ; } </s>

Gather pre-function exception information .


<s> bool R600PassConfig :: addPreISel ( ) { AMDGPUPassConfig :: addPreISel ( ) ; const AMDGPUSubtarget & ST = * getAMDGPUTargetMachine ( ) . getSubtargetImpl ( ) ; if ( ST . IsIRStructurizerEnabled ( ) ) addPass ( createStructurizeCFGPass ( ) ) ; addPass ( createR600TextureIntrinsicsReplacer ( ) ) ; return false ; } </s>


"%qs attribute only applies to functions"

Handle an attribute requiring a FUNCTION_DECL ; arguments as in struct attribute_spec.handler .


<s> bool ARMPassConfig :: addPreEmitPass ( ) { if ( getARMSubtarget ( ) . isThumb2 ( ) ) { if ( ! getARMSubtarget ( ) . prefers32BitThumb ( ) ) PM . add ( createThumb2SizeReductionPass ( ) ) ; addPass ( UnpackMachineBundlesID ) ; } PM . add ( createARMConstantIslandPass ( ) ) ; return true ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s> static void pad_return ( void ) { rtx_insn * insn ; long offset ; if ( ! TARGET_PAD_RETURN ) return ; for ( insn = get_insns ( ) ; insn ; insn = NEXT_INSN ( insn ) ) { rtx_insn * prev0 = prev_active_insn ( insn ) ; bool wantlong = false ; if ( ! INSN_P ( insn ) || GET_CODE ( PATTERN ( insn ) ) != SIMPLE_RETURN ) continue ; if ( ! prev0 ) { prev0 = emit_insn_before ( gen_nopv ( ) , insn ) ; add_reg_note ( prev0 , REG_SAVE_NOTE , GEN_INT ( 1 ) ) ; emit_insn_before ( gen_nopv ( ) , insn ) ; continue ; } offset = get_attr_length ( prev0 ) ; if ( get_attr_length ( prev0 ) == 2 && get_attr_iscompact ( prev0 ) != ISCOMPACT_TRUE ) { wantlong = true ; offset += 2 ; } rtx_insn * prev = prev_active_insn ( prev0 ) ; if ( prev ) offset += get_attr_length ( prev ) ; prev = prev_active_insn ( prev ) ; if ( prev ) offset += get_attr_length ( prev ) ; switch ( offset ) { case 2 : prev = emit_insn_before ( gen_nopv ( ) , insn ) ; add_reg_note ( prev , REG_SAVE_NOTE , GEN_INT ( 1 ) ) ; break ; case 4 : emit_insn_before ( gen_nopv ( ) , insn ) ; break ; default : continue ; } if ( wantlong ) add_reg_note ( prev0 , REG_SAVE_NOTE , GEN_INT ( 1 ) ) ; emit_insn_before ( gen_blockage ( ) , insn ) ; } } </s>

Add padding if necessary to avoid a mispredict . A return could happen immediately after the function start . A call/return and return/return must be 6 bytes apart to avoid mispredict .


<s> const char * HexagonTargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( Opcode ) { default : return nullptr ; case HexagonISD :: CONST32 : return "HexagonISD::CONST32" ; case HexagonISD :: CONST32_GP : return "HexagonISD::CONST32_GP" ; case HexagonISD :: CONST32_Int_Real : return "HexagonISD::CONST32_Int_Real" ; case HexagonISD :: ADJDYNALLOC : return "HexagonISD::ADJDYNALLOC" ; case HexagonISD :: CMPICC : return "HexagonISD::CMPICC" ; case HexagonISD :: CMPFCC : return "HexagonISD::CMPFCC" ; case HexagonISD :: BRICC : return "HexagonISD::BRICC" ; case HexagonISD :: BRFCC : return "HexagonISD::BRFCC" ; case HexagonISD :: SELECT_ICC : return "HexagonISD::SELECT_ICC" ; case HexagonISD :: SELECT_FCC : return "HexagonISD::SELECT_FCC" ; case HexagonISD :: Hi : return "HexagonISD::Hi" ; case HexagonISD :: Lo : return "HexagonISD::Lo" ; case HexagonISD :: JT : return "HexagonISD::JT" ; case HexagonISD :: CP : return "HexagonISD::CP" ; case HexagonISD :: POPCOUNT : return "HexagonISD::POPCOUNT" ; case HexagonISD :: COMBINE : return "HexagonISD::COMBINE" ; case HexagonISD :: PACKHL : return "HexagonISD::PACKHL" ; case HexagonISD :: VSPLATB : return "HexagonISD::VSPLTB" ; case HexagonISD :: VSPLATH : return "HexagonISD::VSPLATH" ; case HexagonISD :: SHUFFEB : return "HexagonISD::SHUFFEB" ; case HexagonISD :: SHUFFEH : return "HexagonISD::SHUFFEH" ; case HexagonISD :: SHUFFOB : return "HexagonISD::SHUFFOB" ; case HexagonISD :: SHUFFOH : return "HexagonISD::SHUFFOH" ; case HexagonISD :: VSXTBH : return "HexagonISD::VSXTBH" ; case HexagonISD :: VSXTBW : return "HexagonISD::VSXTBW" ; case HexagonISD :: VSRAW : return "HexagonISD::VSRAW" ; case HexagonISD :: VSRAH : return "HexagonISD::VSRAH" ; case HexagonISD :: VSRLW : return "HexagonISD::VSRLW" ; case HexagonISD :: VSRLH : return "HexagonISD::VSRLH" ; case HexagonISD :: VSHLW : return "HexagonISD::VSHLW" ; case HexagonISD :: VSHLH : return "HexagonISD::VSHLH" ; case HexagonISD :: VCMPBEQ : return "HexagonISD::VCMPBEQ" ; case HexagonISD :: VCMPBGT : return "HexagonISD::VCMPBGT" ; case HexagonISD :: VCMPBGTU : return "HexagonISD::VCMPBGTU" ; case HexagonISD :: VCMPHEQ : return "HexagonISD::VCMPHEQ" ; case HexagonISD :: VCMPHGT : return "HexagonISD::VCMPHGT" ; case HexagonISD :: VCMPHGTU : return "HexagonISD::VCMPHGTU" ; case HexagonISD :: VCMPWEQ : return "HexagonISD::VCMPWEQ" ; case HexagonISD :: VCMPWGT : return "HexagonISD::VCMPWGT" ; case HexagonISD :: VCMPWGTU : return "HexagonISD::VCMPWGTU" ; case HexagonISD :: INSERT_ri : return "HexagonISD::INSERT_ri" ; case HexagonISD :: INSERT_rd : return "HexagonISD::INSERT_rd" ; case HexagonISD :: INSERT_riv : return "HexagonISD::INSERT_riv" ; case HexagonISD :: INSERT_rdv : return "HexagonISD::INSERT_rdv" ; case HexagonISD :: EXTRACTU_ri : return "HexagonISD::EXTRACTU_ri" ; case HexagonISD :: EXTRACTU_rd : return "HexagonISD::EXTRACTU_rd" ; case HexagonISD :: EXTRACTU_riv : return "HexagonISD::EXTRACTU_riv" ; case HexagonISD :: EXTRACTU_rdv : return "HexagonISD::EXTRACTU_rdv" ; case HexagonISD :: FTOI : return "HexagonISD::FTOI" ; case HexagonISD :: ITOF : return "HexagonISD::ITOF" ; case HexagonISD :: CALLv3 : return "HexagonISD::CALLv3" ; case HexagonISD :: CALLv3nr : return "HexagonISD::CALLv3nr" ; case HexagonISD :: CALLR : return "HexagonISD::CALLR" ; case HexagonISD :: RET_FLAG : return "HexagonISD::RET_FLAG" ; case HexagonISD :: BR_JT : return "HexagonISD::BR_JT" ; case HexagonISD :: TC_RETURN : return "HexagonISD::TC_RETURN" ; case HexagonISD :: EH_RETURN : return "HexagonISD::EH_RETURN" ; } } </s>

getTargetNodeName - This method returns the name of a target specific

Hexagon Hexagon HexagonISD::CONST32 "HexagonISD::CONST32" HexagonISD::CONST32_GP "HexagonISD::CONST32_GP" HexagonISD::CONST32_Int_Real "HexagonISD::CONST32_Int_Real" HexagonISD::ADJDYNALLOC "HexagonISD::ADJDYNALLOC" HexagonISD::CMPICC "HexagonISD::CMPICC" HexagonISD::CMPFCC "HexagonISD::CMPFCC" HexagonISD::BRICC "HexagonISD::BRICC" HexagonISD::BRFCC "HexagonISD::BRFCC" HexagonISD::SELECT_ICC "HexagonISD::SELECT_ICC" HexagonISD::SELECT_FCC "HexagonISD::SELECT_FCC" HexagonISD::Hi "HexagonISD::Hi" HexagonISD::Lo "HexagonISD::Lo" HexagonISD::JT "HexagonISD::JT" HexagonISD::CP "HexagonISD::CP" HexagonISD::POPCOUNT "HexagonISD::POPCOUNT" HexagonISD::COMBINE "HexagonISD::COMBINE" HexagonISD::PACKHL "HexagonISD::PACKHL" HexagonISD::VSPLATB "HexagonISD::VSPLTB" HexagonISD::VSPLATH "HexagonISD::VSPLATH" HexagonISD::SHUFFEB "HexagonISD::SHUFFEB" HexagonISD::SHUFFEH "HexagonISD::SHUFFEH" HexagonISD::SHUFFOB "HexagonISD::SHUFFOB" HexagonISD::SHUFFOH "HexagonISD::SHUFFOH" HexagonISD::VSXTBH "HexagonISD::VSXTBH" HexagonISD::VSXTBW "HexagonISD::VSXTBW" HexagonISD::VSRAW "HexagonISD::VSRAW" HexagonISD::VSRAH "HexagonISD::VSRAH" HexagonISD::VSRLW "HexagonISD::VSRLW" HexagonISD::VSRLH "HexagonISD::VSRLH" HexagonISD::VSHLW "HexagonISD::VSHLW" HexagonISD::VSHLH "HexagonISD::VSHLH" HexagonISD::VCMPBEQ "HexagonISD::VCMPBEQ" HexagonISD::VCMPBGT "HexagonISD::VCMPBGT" HexagonISD::VCMPBGTU "HexagonISD::VCMPBGTU" HexagonISD::VCMPHEQ "HexagonISD::VCMPHEQ" HexagonISD::VCMPHGT "HexagonISD::VCMPHGT" HexagonISD::VCMPHGTU "HexagonISD::VCMPHGTU" HexagonISD::VCMPWEQ "HexagonISD::VCMPWEQ" HexagonISD::VCMPWGT "HexagonISD::VCMPWGT" HexagonISD::VCMPWGTU "HexagonISD::VCMPWGTU" HexagonISD::INSERT_ri "HexagonISD::INSERT_ri" HexagonISD::INSERT_rd "HexagonISD::INSERT_rd" HexagonISD::INSERT_riv "HexagonISD::INSERT_riv" HexagonISD::INSERT_rdv "HexagonISD::INSERT_rdv" HexagonISD::EXTRACTU_ri "HexagonISD::EXTRACTU_ri" HexagonISD::EXTRACTU_rd "HexagonISD::EXTRACTU_rd" HexagonISD::EXTRACTU_riv "HexagonISD::EXTRACTU_riv" HexagonISD::EXTRACTU_rdv "HexagonISD::EXTRACTU_rdv" HexagonISD::FTOI "HexagonISD::FTOI" HexagonISD::ITOF "HexagonISD::ITOF" HexagonISD::CALLv3 "HexagonISD::CALLv3" HexagonISD::CALLv3nr "HexagonISD::CALLv3nr" HexagonISD::CALLR "HexagonISD::CALLR" HexagonISD::RET_FLAG "HexagonISD::RET_FLAG" HexagonISD::BR_JT "HexagonISD::BR_JT" HexagonISD::TC_RETURN "HexagonISD::TC_RETURN" HexagonISD::EH_RETURN "HexagonISD::EH_RETURN"


<s>
void
RISCVDAGToDAGISel
::
PreprocessISelDAG
(
)
{
for
(
SelectionDAG
::
allnodes_iterator
I
=
CurDAG
->
allnodes_begin
(
)
,
E
=
CurDAG
->
allnodes_end
(
)
;
I
!=
E
;
)
{
SDNode
*
N
=
&
*
I
++
;
if
(
N
->
getOpcode
(
)
!=
RISCVISD
::
SPLAT_VECTOR_SPLIT_I64_VL
)
continue
;
assert
(
N
->
getNumOperands
(
)
==
3
&&
"Unexpected number of operands"
)
;
MVT
VT
=
N
->
getSimpleValueType
(
0
)
;
SDValue
Lo
=
N
->
getOperand
(
0
)
;
SDValue
Hi
=
N
->
getOperand
(
1
)
;
SDValue
VL
=
N
->
getOperand
(
2
)
;
assert
(
VT
.
getVectorElementType
(
)
==
MVT
::
i64
&&
VT
.
isScalableVector
(
)
&&
Lo
.
getValueType
(
)
==
MVT
::
i32
&&
Hi
.
getValueType
(
)
==
MVT
::
i32
&&
"Unexpected VTs!"
)
;
MachineFunction
&
MF
=
CurDAG
->
getMachineFunction
(
)
;
RISCVMachineFunctionInfo
*
FuncInfo
=
MF
.
getInfo
<
RISCVMachineFunctionInfo
>
(
)
;
SDLoc
DL
(
N
)
;
int
FI
=
FuncInfo
->
getMoveF64FrameIndex
(
MF
)
;
MachinePointerInfo
MPI
=
MachinePointerInfo
::
getFixedStack
(
MF
,
FI
)
;
const
TargetLowering
&
TLI
=
CurDAG
->
getTargetLoweringInfo
(
)
;
SDValue
StackSlot
=
CurDAG
->
getFrameIndex
(
FI
,
TLI
.
getPointerTy
(
CurDAG
->
getDataLayout
(
)
)
)
;
SDValue
Chain
=
CurDAG
->
getEntryNode
(
)
;
Lo
=
CurDAG
->
getStore
(
Chain
,
DL
,
Lo
,
StackSlot
,
MPI
,
Align
(
8
)
)
;
SDValue
OffsetSlot
=
CurDAG
->
getMemBasePlusOffset
(
StackSlot
,
TypeSize
::
Fixed
(
4
)
,
DL
)
;
Hi
=
CurDAG
->
getStore
(
Chain
,
DL
,
Hi
,
OffsetSlot
,
MPI
.
getWithOffset
(
4
)
,
Align
(
8
)
)
;
Chain
=
CurDAG
->
getNode
(
ISD
::
TokenFactor
,
DL
,
MVT
::
Other
,
Lo
,
Hi
)
;
SDVTList
VTs
=
CurDAG
->
getVTList
(
{
VT
,
MVT
::
Other
}
)
;
SDValue
IntID
=
CurDAG
->
getTargetConstant
(
Intrinsic
::
riscv_vlse
,
DL
,
MVT
::
i64
)
;
SDValue
Ops
[
]
=
{
Chain
,
IntID
,
StackSlot
,
CurDAG
->
getRegister
(
RISCV
::
X0
,
MVT
::
i64
)
,
VL
}
;
SDValue
Result
=
CurDAG
->
getMemIntrinsicNode
(
ISD
::
INTRINSIC_W_CHAIN
,
DL
,
VTs
,
Ops
,
MVT
::
i64
,
MPI
,
Align
(
8
)
,
MachineMemOperand
::
MOLoad
)
;
I
;
CurDAG
->
ReplaceAllUsesOfValueWith
(
SDValue
(
N
,
0
)
,
Result
)
;
++
I
;
CurDAG
->
DeleteNode
(
N
)
;
}
}
</s>

PreprocessISelDAG - This hook allows targets to hack on the graph before instruction selection starts .


<s> static rtx pa_trampoline_adjust_address ( rtx addr ) { if ( ! TARGET_64BIT ) addr = memory_address ( Pmode , plus_constant ( Pmode , addr , 58 ) ) ; return addr ; } </s>

Perform any machine-specific adjustment in the address of the trampoline . ADDR contains the address that was passed to pa_trampoline_init . Adjust the trampoline address to point to the plabel at offset 44 .


<s> static bool nios2_valid_target_attribute_p ( tree fndecl , tree ARG_UNUSED ( name ) , tree args , int ARG_UNUSED ( flags ) ) { struct cl_target_option cur_target ; bool ret = true ; tree old_optimize = build_optimization_node ( & global_options , & global_options_set ) ; tree new_target , new_optimize ; tree func_optimize = DECL_FUNCTION_SPECIFIC_OPTIMIZATION ( fndecl ) ; if ( func_optimize && func_optimize != old_optimize ) cl_optimization_restore ( & global_options , & global_options_set , TREE_OPTIMIZATION ( func_optimize ) ) ; cl_target_option_save ( & cur_target , & global_options , & global_options_set ) ; new_target = nios2_valid_target_attribute_tree ( args ) ; new_optimize = build_optimization_node ( & global_options , & global_options_set ) ; if ( ! new_target ) ret = false ; else if ( fndecl ) { DECL_FUNCTION_SPECIFIC_TARGET ( fndecl ) = new_target ; if ( old_optimize != new_optimize ) DECL_FUNCTION_SPECIFIC_OPTIMIZATION ( fndecl ) = new_optimize ; } cl_target_option_restore ( & global_options , & global_options_set , & cur_target ) ; if ( old_optimize != new_optimize ) cl_optimization_restore ( & global_options , & global_options_set , TREE_OPTIMIZATION ( old_optimize ) ) ; return ret ; } </s>

Hook to validate attribute ( ( target ( `` string '' ) ) ) .


<s> bool ARMPassConfig :: addPreEmitPass ( ) { if ( getARMSubtarget ( ) . isThumb2 ( ) ) { if ( ! getARMSubtarget ( ) . prefers32BitThumb ( ) ) addPass ( createThumb2SizeReductionPass ( ) ) ; addPass ( & UnpackMachineBundlesID ) ; } if ( FlagSfiDisableCP ) { assert ( getARMSubtarget ( ) . useMovt ( ) ) ; } addPass ( createARMConstantIslandPass ( ) ) ; if ( getARMSubtarget ( ) . isTargetNaCl ( ) ) { addPass ( createARMNaClRewritePass ( ) ) ; } return true ; } </s>


<s>
SDValue
XCoreTargetLowering
::
LowerOperation
(
SDValue
Op
,
SelectionDAG
&
DAG
)
const
{
switch
(
Op
.
getOpcode
(
)
)
{
case
ISD
::
GlobalAddress
:
return
LowerGlobalAddress
(
Op
,
DAG
)
;
case
ISD
::
GlobalTLSAddress
:
return
LowerGlobalTLSAddress
(
Op
,
DAG
)
;
case
ISD
::
BlockAddress
:
return
LowerBlockAddress
(
Op
,
DAG
)
;
case
ISD
::
ConstantPool
:
return
LowerConstantPool
(
Op
,
DAG
)
;
case
ISD
::
BR_JT
:
return
LowerBR_JT
(
Op
,
DAG
)
;
case
ISD
::
LOAD
:
return
LowerLOAD
(
Op
,
DAG
)
;
case
ISD
::
STORE
:
return
LowerSTORE
(
Op
,
DAG
)
;
case
ISD
::
SELECT_CC
:
return
LowerSELECT_CC
(
Op
,
DAG
)
;
case
ISD
::
VAARG
:
return
LowerVAARG
(
Op
,
DAG
)
;
case
ISD
::
VASTART
:
return
LowerVASTART
(
Op
,
DAG
)
;
case
ISD
::
SMUL_LOHI
:
return
LowerSMUL_LOHI
(
Op
,
DAG
)
;
case
ISD
::
UMUL_LOHI
:
return
LowerUMUL_LOHI
(
Op
,
DAG
)
;
case
ISD
::
ADD
:
case
ISD
::
SUB
:
return
ExpandADDSUB
(
Op
.
getNode
(
)
,
DAG
)
;
case
ISD
::
FRAMEADDR
:
return
LowerFRAMEADDR
(
Op
,
DAG
)
;
case
ISD
::
INIT_TRAMPOLINE
:
return
LowerINIT_TRAMPOLINE
(
Op
,
DAG
)
;
case
ISD
::
ADJUST_TRAMPOLINE
:
return
LowerADJUST_TRAMPOLINE
(
Op
,
DAG
)
;
case
ISD
::
INTRINSIC_WO_CHAIN
:
return
LowerINTRINSIC_WO_CHAIN
(
Op
,
DAG
)
;
default
:
llvm_unreachable
(
"unimplemented operand"
)
;
}
}
</s>

LowerOperation - Provide custom lowering hooks for some operations .

XCore
XCore
ISD::GlobalAddress
ISD::GlobalTLSAddress
ISD::BlockAddress
ISD::ConstantPool
ISD::BR_JT
ISD::LOAD
ISD::STORE
ISD::SELECT_CC
ISD::VAARG
ISD::VASTART
ISD::SMUL_LOHI
ISD::UMUL_LOHI
ISD::ADD
ISD::SUB
ISD::FRAMEADDR
ISD::INIT_TRAMPOLINE
ISD::ADJUST_TRAMPOLINE
ISD::INTRINSIC_WO_CHAIN
"unimplemented operand"


<s> SparcTargetMachine :: SparcTargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL , bool is64bit ) : LLVMTargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL ) , Subtarget ( TT , CPU , FS , * this , is64bit ) { initAsmInfo ( ) ; } </s>


<s> const MCSubtargetInfo * TPCII :: getSubtargetInfo ( ) { assert ( SubTargetInfo ) ; return SubTargetInfo ; } </s>


<s> TargetPassConfig * ECLairTargetMachine :: createPassConfig ( PassManagerBase & PM ) { return new TargetPassConfig ( * this , PM ) ; } </s>

Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of CodeGen passes .


<s>
SDValue
X86TargetLowering
::
BuildSDIVPow2
(
SDNode
*
N
,
const
APInt
&
Divisor
,
SelectionDAG
&
DAG
,
SmallVectorImpl
<
SDNode
*
>
&
Created
)
const
{
AttributeList
Attr
=
DAG
.
getMachineFunction
(
)
.
getFunction
(
)
.
getAttributes
(
)
;
if
(
isIntDivCheap
(
N
->
getValueType
(
0
)
,
Attr
)
)
return
SDValue
(
N
,
0
)
;
assert
(
(
Divisor
.
isPowerOf2
(
)
||
Divisor
.
isNegatedPowerOf2
(
)
)
&&
"Unexpected divisor!"
)
;
if
(
!
Subtarget
.
hasCMov
(
)
)
return
SDValue
(
)
;
EVT
VT
=
N
->
getValueType
(
0
)
;
if
(
VT
!=
MVT
::
i16
&&
VT
!=
MVT
::
i32
&&
!
(
Subtarget
.
is64Bit
(
)
&&
VT
==
MVT
::
i64
)
)
return
SDValue
(
)
;
unsigned
Lg2
=
Divisor
.
countTrailingZeros
(
)
;
if
(
Lg2
==
1
)
return
SDValue
(
)
;
SDLoc
DL
(
N
)
;
SDValue
N0
=
N
->
getOperand
(
0
)
;
SDValue
Zero
=
DAG
.
getConstant
(
0
,
DL
,
VT
)
;
APInt
Lg2Mask
=
APInt
::
getLowBitsSet
(
VT
.
getSizeInBits
(
)
,
Lg2
)
;
SDValue
Pow2MinusOne
=
DAG
.
getConstant
(
Lg2Mask
,
DL
,
VT
)
;
SDValue
Cmp
=
DAG
.
getSetCC
(
DL
,
MVT
::
i8
,
N0
,
Zero
,
ISD
::
SETLT
)
;
SDValue
Add
=
DAG
.
getNode
(
ISD
::
ADD
,
DL
,
VT
,
N0
,
Pow2MinusOne
)
;
SDValue
CMov
=
DAG
.
getNode
(
ISD
::
SELECT
,
DL
,
VT
,
Cmp
,
Add
,
N0
)
;
Created
.
push_back
(
Cmp
.
getNode
(
)
)
;
Created
.
push_back
(
Add
.
getNode
(
)
)
;
Created
.
push_back
(
CMov
.
getNode
(
)
)
;
SDValue
SRA
=
DAG
.
getNode
(
ISD
::
SRA
,
DL
,
VT
,
CMov
,
DAG
.
getConstant
(
Lg2
,
DL
,
MVT
::
i8
)
)
;
if
(
Divisor
.
isNonNegative
(
)
)
return
SRA
;
Created
.
push_back
(
SRA
.
getNode
(
)
)
;
return
DAG
.
getNode
(
ISD
::
SUB
,
DL
,
VT
,
Zero
,
SRA
)
;
}
</s>

Targets may override this function to provide custom SDIV lowering for power-of-2 denominators .


<s> static void pdp11_function_arg_advance ( cumulative_args_t cum_v , machine_mode mode , const_tree type , bool named ATTRIBUTE_UNUSED ) { CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; * cum += ( mode != BLKmode ? GET_MODE_SIZE ( mode ) : int_size_in_bytes ( type ) ) ; } </s>

Worker function for TARGET_FUNCTION_ARG_ADVANCE . Update the data in CUM to advance over an argument of mode MODE and data type TYPE . ( TYPE is null for libcalls where that information may not be available . )


<s> bool isReg ( ) const override { return Kind == Register && Reg . Modifiers == 0 ; } </s>


<s> static rtx nios2_got_address ( rtx loc , int unspec ) { rtx offset = nios2_unspec_offset ( loc , unspec ) ; crtl -> uses_pic_offset_table = 1 ; if ( nios2_large_offset_p ( unspec ) ) return force_reg ( Pmode , nios2_large_got_address ( offset , NULL_RTX ) ) ; return gen_rtx_PLUS ( Pmode , pic_offset_table_rtx , offset ) ; } </s>


A get_unnamed_decl callback , used for read-only sections . PTR points to the section string variable .


<s>
static
bool
aarch64_validate_mtune
(
const
char
*
str
,
const
struct
processor
*
*
res
)
{
enum
aarch64_parse_opt_result
parse_res
=
aarch64_parse_tune
(
str
,
res
)
;
if
(
parse_res
==
AARCH64_PARSE_OK
)
return
true
;
switch
(
parse_res
)
{
case
AARCH64_PARSE_MISSING_ARG
:
error
(
"missing cpu name in %<-mtune=%s%>"
,
str
)
;
break
;
case
AARCH64_PARSE_INVALID_ARG
:
error
(
"unknown value %qs for -mtune"
,
str
)
;
aarch64_print_hint_for_core
(
str
)
;
break
;
default
:
gcc_unreachable
(
)
;
}
return
false
;
}
</s>

Validate a command-line -mtune option . Parse the cpu specified in STR and throw errors if appropriate . Put the result , if it is valid , in RES . Return whether the option is valid .

aarch64
"missing cpu name in %<-mtune=%s%>"
"unknown value %qs for -mtune"


<s> unsigned MOSInstrInfo :: removeBranch ( MachineBasicBlock & MBB , int * BytesRemoved ) const { auto Begin = MBB . getFirstTerminator ( ) ; auto End = MBB . end ( ) ; while ( Begin != End && Begin -> isCompare ( ) ) ++ Begin ; unsigned NumRemoved = std :: distance ( Begin , End ) ; if ( BytesRemoved ) { * BytesRemoved = 0 ; for ( const auto & I : make_range ( Begin , End ) ) * BytesRemoved += getInstSizeInBytes ( I ) ; } MBB . erase ( Begin , End ) ; return NumRemoved ; } </s>

Remove the branching code at the end of the specific MBB .


<s>
void
SystemZOperand
::
print
(
raw_ostream
&
OS
)
const
{
llvm_unreachable
(
"Not implemented"
)
;
}
</s>

print - Print a debug representation of the operand to the given stream .


<s> bool s390_hard_regno_mode_ok ( unsigned int regno , machine_mode mode ) { if ( ! TARGET_VX && VECTOR_NOFP_REGNO_P ( regno ) ) return false ; switch ( REGNO_REG_CLASS ( regno ) ) { case VEC_REGS : return ( ( GET_MODE_CLASS ( mode ) == MODE_INT && s390_class_max_nregs ( VEC_REGS , mode ) == 1 ) || mode == DFmode || s390_vector_mode_supported_p ( mode ) ) ; break ; case FP_REGS : if ( TARGET_VX && ( ( GET_MODE_CLASS ( mode ) == MODE_INT && s390_class_max_nregs ( FP_REGS , mode ) == 1 ) || mode == DFmode || s390_vector_mode_supported_p ( mode ) ) ) return true ; if ( REGNO_PAIR_OK ( regno , mode ) ) { if ( mode == SImode || mode == DImode ) return true ; if ( FLOAT_MODE_P ( mode ) && GET_MODE_CLASS ( mode ) != MODE_VECTOR_FLOAT ) return true ; } break ; case ADDR_REGS : if ( FRAME_REGNO_P ( regno ) && mode == Pmode ) return true ; case GENERAL_REGS : if ( REGNO_PAIR_OK ( regno , mode ) ) { if ( TARGET_ZARCH || ( mode != TFmode && mode != TCmode && mode != TDmode ) ) return true ; } break ; case CC_REGS : if ( GET_MODE_CLASS ( mode ) == MODE_CC ) return true ; break ; case ACCESS_REGS : if ( REGNO_PAIR_OK ( regno , mode ) ) { if ( mode == SImode || mode == Pmode ) return true ; } break ; default : return false ; } return false ; } </s>

Return true if it is legal to put a value with MODE into REGNO .


<s> static bool c6x_hard_regno_mode_ok ( unsigned int regno , machine_mode mode ) { return GET_MODE_SIZE ( mode ) <= UNITS_PER_WORD || ( regno & 1 ) == 0 ; } </s>


<s> bool AMDGPUTargetLowering :: isFNegFree ( EVT VT ) const { assert ( VT . isFloatingPoint ( ) ) ; return VT == MVT :: f32 || VT == MVT :: f64 ; } </s>

Return true if an fneg operation is free to the point where it is never worthwhile to replace it with a bitwise operation .


<s> bool function_instance :: modifies_global_state_p ( ) const { unsigned int flags = call_properties ( ) ; if ( flags & CP_RAISE_FP_EXCEPTIONS ) return true ; if ( flags & CP_PREFETCH_MEMORY ) return true ; return flags & ( CP_WRITE_MEMORY | CP_WRITE_FFR ) ; } </s>

Return true if calls to the function could modify some form of global state .


<s> void AMDGPUTargetLowering :: ReplaceNodeResults ( SDNode * N , SmallVectorImpl < SDValue > & Results , SelectionDAG & DAG ) const { switch ( N -> getOpcode ( ) ) { case ISD :: SIGN_EXTEND_INREG : return ; default : return ; } } </s>

ReplaceNodeResults - Replace the results of node with an illegal result type with new values built out of custom code .


<s> const MCRegisterInfo * getRegInfo ( ) const { return RegInfo ; } </s>

getRegInfo - Return information about the registers currently in use .


<s>
void
s390_function_profiler
(
FILE
*
file
,
int
labelno
)
{
rtx
op
[
7
]
;
char
label
[
128
]
;
ASM_GENERATE_INTERNAL_LABEL
(
label
,
"LP"
,
labelno
)
;
fprintf
(
file
,
"# function profiler \n"
)
;
op
[
0
]
=
gen_rtx_REG
(
Pmode
,
RETURN_REGNUM
)
;
op
[
1
]
=
gen_rtx_REG
(
Pmode
,
STACK_POINTER_REGNUM
)
;
op
[
1
]
=
gen_rtx_MEM
(
Pmode
,
plus_constant
(
Pmode
,
op
[
1
]
,
UNITS_PER_LONG
)
)
;
op
[
2
]
=
gen_rtx_REG
(
Pmode
,
1
)
;
op
[
3
]
=
gen_rtx_SYMBOL_REF
(
Pmode
,
label
)
;
SYMBOL_REF_FLAGS
(
op
[
3
]
)
=
SYMBOL_FLAG_LOCAL
;
op
[
4
]
=
gen_rtx_SYMBOL_REF
(
Pmode
,
"_mcount"
)
;
if
(
flag_pic
)
{
op
[
4
]
=
gen_rtx_UNSPEC
(
Pmode
,
gen_rtvec
(
1
,
op
[
4
]
)
,
UNSPEC_PLT
)
;
op
[
4
]
=
gen_rtx_CONST
(
Pmode
,
op
[
4
]
)
;
}
if
(
TARGET_64BIT
)
{
output_asm_insn
(
"stg\t%0,%1"
,
op
)
;
output_asm_insn
(
"larl\t%2,%3"
,
op
)
;
output_asm_insn
(
"brasl\t%0,%4"
,
op
)
;
output_asm_insn
(
"lg\t%0,%1"
,
op
)
;
}
else
if
(
!
flag_pic
)
{
op
[
6
]
=
gen_label_rtx
(
)
;
output_asm_insn
(
"st\t%0,%1"
,
op
)
;
output_asm_insn
(
"bras\t%2,%l6"
,
op
)
;
output_asm_insn
(
".long\t%4"
,
op
)
;
output_asm_insn
(
".long\t%3"
,
op
)
;
targetm
.
asm_out
.
internal_label
(
file
,
"L"
,
CODE_LABEL_NUMBER
(
op
[
6
]
)
)
;
output_asm_insn
(
"l\t%0,0(%2)"
,
op
)
;
output_asm_insn
(
"l\t%2,4(%2)"
,
op
)
;
output_asm_insn
(
"basr\t%0,%0"
,
op
)
;
output_asm_insn
(
"l\t%0,%1"
,
op
)
;
}
else
{
op
[
5
]
=
gen_label_rtx
(
)
;
op
[
6
]
=
gen_label_rtx
(
)
;
output_asm_insn
(
"st\t%0,%1"
,
op
)
;
output_asm_insn
(
"bras\t%2,%l6"
,
op
)
;
targetm
.
asm_out
.
internal_label
(
file
,
"L"
,
CODE_LABEL_NUMBER
(
op
[
5
]
)
)
;
output_asm_insn
(
".long\t%4-%l5"
,
op
)
;
output_asm_insn
(
".long\t%3-%l5"
,
op
)
;
targetm
.
asm_out
.
internal_label
(
file
,
"L"
,
CODE_LABEL_NUMBER
(
op
[
6
]
)
)
;
output_asm_insn
(
"lr\t%0,%2"
,
op
)
;
output_asm_insn
(
"a\t%0,0(%2)"
,
op
)
;
output_asm_insn
(
"a\t%2,4(%2)"
,
op
)
;
output_asm_insn
(
"basr\t%0,%0"
,
op
)
;
output_asm_insn
(
"l\t%0,%1"
,
op
)
;
}
}
</s>

Output assembler code to FILE to call a profiler hook .


<s> static void ia64_hpux_init_libfuncs ( void ) { ia64_init_libfuncs ( ) ; set_optab_libfunc ( sdiv_optab , SImode , 0 ) ; set_optab_libfunc ( udiv_optab , SImode , 0 ) ; set_optab_libfunc ( smod_optab , SImode , 0 ) ; set_optab_libfunc ( umod_optab , SImode , 0 ) ; set_optab_libfunc ( sdiv_optab , DImode , "__milli_divI" ) ; set_optab_libfunc ( udiv_optab , DImode , "__milli_divU" ) ; set_optab_libfunc ( smod_optab , DImode , "__milli_remI" ) ; set_optab_libfunc ( umod_optab , DImode , "__milli_remU" ) ; set_optab_libfunc ( smin_optab , TFmode , "_U_Qfmin" ) ; set_optab_libfunc ( smax_optab , TFmode , "_U_Qfmax" ) ; set_optab_libfunc ( abs_optab , TFmode , "_U_Qfabs" ) ; cmptf_libfunc = init_one_libfunc ( "_U_Qfcmp" ) ; set_optab_libfunc ( eq_optab , TFmode , 0 ) ; set_optab_libfunc ( ne_optab , TFmode , 0 ) ; set_optab_libfunc ( gt_optab , TFmode , 0 ) ; set_optab_libfunc ( ge_optab , TFmode , 0 ) ; set_optab_libfunc ( lt_optab , TFmode , 0 ) ; set_optab_libfunc ( le_optab , TFmode , 0 ) ; } </s>

Rename all the TFmode libfuncs using the HPUX conventions .


<s> bool P2DAGToDAGISel :: runOnMachineFunction ( MachineFunction & MF ) { return SelectionDAGISel :: runOnMachineFunction ( MF ) ; } </s>

runOnMachineFunction - Emit the function body .


<s> TargetLoweringObjectFile * getObjFileLowering ( ) const override { return TLOF . get ( ) ; } </s>

Return information about object file lowering .


"node still has unscheduled dependencies"

Move an instruction and update register pressure .


<s> void X86WinAllocaExpander :: lower ( MachineInstr * MI , Lowering L ) { DebugLoc DL = MI -> getDebugLoc ( ) ; MachineBasicBlock * MBB = MI -> getParent ( ) ; MachineBasicBlock :: iterator I = * MI ; int64_t Amount = getWinAllocaAmount ( MI , MRI ) ; if ( Amount == 0 ) { MI -> eraseFromParent ( ) ; return ; } bool Is64Bit = STI -> is64Bit ( ) ; bool Is64BitAlloca = MI -> getOpcode ( ) == X86 :: WIN_ALLOCA_64 ; assert ( SlotSize == 4 || SlotSize == 8 ) ; switch ( L ) { case TouchAndSub : { assert ( Amount >= SlotSize ) ; unsigned RegA = Is64Bit ? X86 :: RAX : X86 :: EAX ; BuildMI ( * MBB , I , DL , TII -> get ( Is64Bit ? X86 :: PUSH64r : X86 :: PUSH32r ) ) . addReg ( RegA , RegState :: Undef ) ; Amount -= SlotSize ; if ( ! Amount ) break ; LLVM_FALLTHROUGH ; } case Sub : assert ( Amount > 0 ) ; if ( Amount == SlotSize ) { unsigned RegA = Is64Bit ? X86 :: RAX : X86 :: EAX ; BuildMI ( * MBB , I , DL , TII -> get ( Is64Bit ? X86 :: PUSH64r : X86 :: PUSH32r ) ) . addReg ( RegA , RegState :: Undef ) ; } else { BuildMI ( * MBB , I , DL , TII -> get ( getSubOpcode ( Is64BitAlloca , Amount ) ) , StackPtr ) . addReg ( StackPtr ) . addImm ( Amount ) ; } break ; case Probe : if ( ! NoStackArgProbe ) { unsigned RegA = Is64BitAlloca ? X86 :: RAX : X86 :: EAX ; BuildMI ( * MBB , MI , DL , TII -> get ( TargetOpcode :: COPY ) , RegA ) . addReg ( MI -> getOperand ( 0 ) . getReg ( ) ) ; STI -> getFrameLowering ( ) -> emitStackProbe ( * MBB -> getParent ( ) , * MBB , MI , DL , false ) ; } else { BuildMI ( * MBB , I , DL , TII -> get ( Is64BitAlloca ? X86 :: SUB64rr : X86 :: SUB32rr ) , StackPtr ) . addReg ( StackPtr ) . addReg ( MI -> getOperand ( 0 ) . getReg ( ) ) ; } break ; } Register AmountReg = MI -> getOperand ( 0 ) . getReg ( ) ; MI -> eraseFromParent ( ) ; if ( MRI -> use_empty ( AmountReg ) ) if ( MachineInstr * AmountDef = MRI -> getUniqueVRegDef ( AmountReg ) ) AmountDef -> eraseFromParent ( ) ; } </s>


<s> const char * X86TargetLowering :: LowerXConstraint ( EVT ConstraintVT ) const { if ( ConstraintVT . isFloatingPoint ( ) ) { if ( Subtarget -> hasSSE2 ( ) ) return "Y" ; if ( Subtarget -> hasSSE1 ( ) ) return "x" ; } return TargetLowering :: LowerXConstraint ( ConstraintVT ) ; } </s>

Try to replace an X constraint , which matches anything , with another that has more specific requirements based on the type of the corresponding operand .


<s> static bool nvptx_record_fndecl ( tree decl , bool force = false ) { if ( decl == NULL_TREE || TREE_CODE ( decl ) != FUNCTION_DECL || ! DECL_EXTERNAL ( decl ) ) return true ; if ( ! force && TYPE_ARG_TYPES ( TREE_TYPE ( decl ) ) == NULL_TREE ) return false ; tree * slot = declared_fndecls_htab -> find_slot ( decl , INSERT ) ; if ( * slot == NULL ) { * slot = decl ; const char * name = get_fnname_from_decl ( decl ) ; name = nvptx_name_replacement ( name ) ; write_function_decl_and_comment ( func_decls , name , decl ) ; } return true ; } </s>

DECL is an external FUNCTION_DECL , make sure its in the fndecl hash table and and write a ptx prototype . These are emitted at end of compilation .


<s> static unsigned int mips_load_label_num_insns ( void ) { if ( cfun -> machine -> load_label_num_insns == 0 ) { mips_process_load_label ( pc_rtx ) ; cfun -> machine -> load_label_num_insns = mips_multi_num_insns ; } return cfun -> machine -> load_label_num_insns ; } </s>

Return the number of instructions needed to load a label into $ AT .


<s> void ia64_expand_call ( rtx retval , rtx addr , rtx nextarg ATTRIBUTE_UNUSED , int sibcall_p ) { rtx insn , b0 ; addr = XEXP ( addr , 0 ) ; addr = convert_memory_address ( DImode , addr ) ; b0 = gen_rtx_REG ( DImode , R_BR ( 0 ) ) ; if ( TARGET_NO_PIC || TARGET_AUTO_PIC ) { if ( sibcall_p ) insn = gen_sibcall_nogp ( addr ) ; else if ( ! retval ) insn = gen_call_nogp ( addr , b0 ) ; else insn = gen_call_value_nogp ( retval , addr , b0 ) ; insn = emit_call_insn ( insn ) ; } else { if ( sibcall_p ) insn = gen_sibcall_gp ( addr ) ; else if ( ! retval ) insn = gen_call_gp ( addr , b0 ) ; else insn = gen_call_value_gp ( retval , addr , b0 ) ; insn = emit_call_insn ( insn ) ; use_reg ( & CALL_INSN_FUNCTION_USAGE ( insn ) , pic_offset_table_rtx ) ; } if ( sibcall_p ) use_reg ( & CALL_INSN_FUNCTION_USAGE ( insn ) , b0 ) ; } </s>

Emit the appropriate sequence for a call .


<s> void ix86_split_copysign_var ( rtx operands [ ] ) { machine_mode mode , vmode ; rtx dest , scratch , op0 , op1 , mask , nmask , x ; dest = operands [ 0 ] ; scratch = operands [ 1 ] ; op0 = operands [ 2 ] ; op1 = operands [ 3 ] ; nmask = operands [ 4 ] ; mask = operands [ 5 ] ; mode = GET_MODE ( dest ) ; vmode = GET_MODE ( mask ) ; if ( rtx_equal_p ( op0 , op1 ) ) { emit_move_insn ( dest , op0 ) ; return ; } if ( REG_P ( mask ) && REGNO ( dest ) == REGNO ( mask ) ) { gcc_assert ( REGNO ( op1 ) == REGNO ( scratch ) ) ; x = gen_rtx_AND ( vmode , scratch , mask ) ; emit_insn ( gen_rtx_SET ( scratch , x ) ) ; dest = mask ; op0 = lowpart_subreg ( vmode , op0 , mode ) ; x = gen_rtx_NOT ( vmode , dest ) ; x = gen_rtx_AND ( vmode , x , op0 ) ; emit_insn ( gen_rtx_SET ( dest , x ) ) ; } else { if ( REGNO ( op1 ) == REGNO ( scratch ) ) { x = gen_rtx_AND ( vmode , scratch , mask ) ; } else { gcc_assert ( REGNO ( mask ) == REGNO ( scratch ) ) ; op1 = lowpart_subreg ( vmode , op1 , mode ) ; x = gen_rtx_AND ( vmode , scratch , op1 ) ; } emit_insn ( gen_rtx_SET ( scratch , x ) ) ; if ( REGNO ( op0 ) == REGNO ( dest ) ) { dest = lowpart_subreg ( vmode , op0 , mode ) ; x = gen_rtx_AND ( vmode , dest , nmask ) ; } else { gcc_assert ( REGNO ( nmask ) == REGNO ( dest ) ) ; dest = nmask ; op0 = lowpart_subreg ( vmode , op0 , mode ) ; x = gen_rtx_AND ( vmode , dest , op0 ) ; } emit_insn ( gen_rtx_SET ( dest , x ) ) ; } x = gen_rtx_IOR ( vmode , dest , scratch ) ; emit_insn ( gen_rtx_SET ( dest , x ) ) ; } </s>

Deconstruct a copysign operation into bit masks . Operand 0 is variable , so we have to do two masks .


<s> bool Z80InstrInfo :: analyzeCompare ( const MachineInstr & MI , unsigned & SrcReg , unsigned & SrcReg2 , int & CmpMask , int & CmpValue ) const { switch ( MI . getOpcode ( ) ) { default : return false ; case Z80 :: OR8ar : SrcReg = Z80 :: A ; if ( MI . getOperand ( 1 ) . getReg ( ) != SrcReg ) return false ; SrcReg2 = 0 ; CmpMask = ~ 0 ; CmpValue = 0 ; break ; case Z80 :: CP8ai : case Z80 :: SUB8ai : SrcReg = Z80 :: A ; SrcReg2 = 0 ; CmpMask = CmpValue = 0 ; if ( MI . getOperand ( 0 ) . isImm ( ) ) { CmpMask = ~ 0 ; CmpValue = MI . getOperand ( 0 ) . getImm ( ) ; } break ; case Z80 :: CP8ar : case Z80 :: SUB8ar : SrcReg = Z80 :: A ; SrcReg2 = MI . getOperand ( 0 ) . getReg ( ) ; CmpMask = CmpValue = 0 ; break ; case Z80 :: CP8ap : case Z80 :: CP8ao : case Z80 :: SUB8ap : case Z80 :: SUB8ao : SrcReg = Z80 :: A ; SrcReg2 = CmpMask = CmpValue = 0 ; break ; } MachineBasicBlock :: const_reverse_iterator I = MI , E = MI . getParent ( ) -> rend ( ) ; while ( ++ I != E && I -> isFullCopy ( ) ) for ( unsigned * Reg : { & SrcReg , & SrcReg2 } ) if ( TargetRegisterInfo :: isPhysicalRegister ( * Reg ) && * Reg == I -> getOperand ( 0 ) . getReg ( ) ) * Reg = I -> getOperand ( 1 ) . getReg ( ) ; return true ; } </s>

analyzeCompare - For a comparison instruction , return the source registers in SrcReg and SrcReg2 if having two register operands , and the value it compares against in CmpValue .


<s> void AMDGPUTargetLowering :: computeKnownBitsForTargetNode ( const SDValue Op , KnownBits & Known , const APInt & DemandedElts , const SelectionDAG & DAG , unsigned Depth ) const { Known . resetAll ( ) ; unsigned Opc = Op . getOpcode ( ) ; switch ( Opc ) { default : break ; case AMDGPUISD :: CARRY : case AMDGPUISD :: BORROW : { Known . Zero = APInt :: getHighBitsSet ( 32 , 31 ) ; break ; } case AMDGPUISD :: BFE_I32 : case AMDGPUISD :: BFE_U32 : { ConstantSDNode * CWidth = dyn_cast < ConstantSDNode > ( Op . getOperand ( 2 ) ) ; if ( ! CWidth ) return ; uint32_t Width = CWidth -> getZExtValue ( ) & 0x1f ; if ( Opc == AMDGPUISD :: BFE_U32 ) Known . Zero = APInt :: getHighBitsSet ( 32 , 32 - Width ) ; break ; } case AMDGPUISD :: FP_TO_FP16 : case AMDGPUISD :: FP16_ZEXT : { unsigned BitWidth = Known . getBitWidth ( ) ; Known . Zero = APInt :: getHighBitsSet ( BitWidth , BitWidth - 16 ) ; break ; } case AMDGPUISD :: MUL_U24 : case AMDGPUISD :: MUL_I24 : { KnownBits LHSKnown , RHSKnown ; DAG . computeKnownBits ( Op . getOperand ( 0 ) , LHSKnown , Depth + 1 ) ; DAG . computeKnownBits ( Op . getOperand ( 1 ) , RHSKnown , Depth + 1 ) ; unsigned TrailZ = LHSKnown . countMinTrailingZeros ( ) + RHSKnown . countMinTrailingZeros ( ) ; Known . Zero . setLowBits ( std :: min ( TrailZ , 32u ) ) ; unsigned LHSValBits = 32 - std :: max ( LHSKnown . countMinSignBits ( ) , 8u ) ; unsigned RHSValBits = 32 - std :: max ( RHSKnown . countMinSignBits ( ) , 8u ) ; unsigned MaxValBits = std :: min ( LHSValBits + RHSValBits , 32u ) ; if ( MaxValBits >= 32 ) break ; bool Negative = false ; if ( Opc == AMDGPUISD :: MUL_I24 ) { bool LHSNegative = ! ! ( LHSKnown . One & ( 1 << 23 ) ) ; bool LHSPositive = ! ! ( LHSKnown . Zero & ( 1 << 23 ) ) ; bool RHSNegative = ! ! ( RHSKnown . One & ( 1 << 23 ) ) ; bool RHSPositive = ! ! ( RHSKnown . Zero & ( 1 << 23 ) ) ; if ( ( ! LHSNegative && ! LHSPositive ) || ( ! RHSNegative && ! RHSPositive ) ) break ; Negative = ( LHSNegative && RHSPositive ) || ( LHSPositive && RHSNegative ) ; } if ( Negative ) Known . One . setHighBits ( 32 - MaxValBits ) ; else Known . Zero . setHighBits ( 32 - MaxValBits ) ; break ; } } } </s>

Determine which of the bits specified in Mask are known to be either zero or one and return them in the KnownZero/KnownOne bitsets .


<s> const PPCSubtarget * PPCTargetMachine :: getSubtargetImpl ( const Function & F ) const { Attribute CPUAttr = F . getFnAttribute ( "target-cpu" ) ; Attribute FSAttr = F . getFnAttribute ( "target-features" ) ; std :: string CPU = ! CPUAttr . hasAttribute ( Attribute :: None ) ? CPUAttr . getValueAsString ( ) . str ( ) : TargetCPU ; std :: string FS = ! FSAttr . hasAttribute ( Attribute :: None ) ? FSAttr . getValueAsString ( ) . str ( ) : TargetFS ; bool SoftFloat = F . getFnAttribute ( "use-soft-float" ) . getValueAsString ( ) == "true" ; if ( SoftFloat ) FS += FS . empty ( ) ? "+soft-float" : ",+soft-float" ; auto & I = SubtargetMap [ CPU + FS ] ; if ( ! I ) { resetTargetOptions ( F ) ; I = llvm :: make_unique < PPCSubtarget > ( TargetTriple , CPU , computeFSAdditions ( FS , getOptLevel ( ) , getTargetTriple ( ) ) , * this ) ; } return I . get ( ) ; } </s>

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .

PowerPC PPC PPC "target-cpu" "target-features" "use-soft-float" "true" "+soft-float" ",+soft-float" PPC


<s> uint16_t getAddress ( ) const { return Address ; } </s>

Returns the address of this pointer in this block .


<s> static bool mips_has_long_branch_p ( void ) { rtx_insn * insn , * subinsn ; int normal_length ; shorten_branches ( get_insns ( ) ) ; normal_length = ( TARGET_MIPS16 ? 4 : 8 ) ; for ( insn = get_insns ( ) ; insn ; insn = NEXT_INSN ( insn ) ) FOR_EACH_SUBINSN ( subinsn , insn ) if ( JUMP_P ( subinsn ) && get_attr_length ( subinsn ) > normal_length && ( any_condjump_p ( subinsn ) || any_uncondjump_p ( subinsn ) ) ) return true ; return false ; } </s>

Return true if the function has a long branch instruction .


"Can't load this register from stack slot"

Load the specified register of the given register class from the specified stack frame index .


<s> static bool expand_perm_with_vpdi ( const struct expand_vec_perm_d & d ) { bool vpdi1_p = false ; bool vpdi4_p = false ; rtx op0_reg , op1_reg ; if ( d . nelt != 2 ) return false ; if ( d . perm [ 0 ] == 0 && d . perm [ 1 ] == 3 ) vpdi1_p = true ; if ( ( d . perm [ 0 ] == 1 && d . perm [ 1 ] == 2 ) || ( d . perm [ 0 ] == 1 && d . perm [ 1 ] == 0 ) || ( d . perm [ 0 ] == 3 && d . perm [ 1 ] == 2 ) ) vpdi4_p = true ; if ( ! vpdi1_p && ! vpdi4_p ) return false ; if ( d . testing_p ) return true ; op0_reg = force_reg ( GET_MODE ( d . op0 ) , d . op0 ) ; op1_reg = force_reg ( GET_MODE ( d . op1 ) , d . op1 ) ; if ( d . only_op0 ) op1_reg = op0_reg ; else if ( d . only_op1 ) op0_reg = op1_reg ; if ( vpdi1_p ) emit_insn ( gen_vpdi1 ( d . vmode , d . target , op0_reg , op1_reg ) ) ; if ( vpdi4_p ) emit_insn ( gen_vpdi4 ( d . vmode , d . target , op0_reg , op1_reg ) ) ; return true ; } </s>

Try to expand the vector permute operation described by D using the vector permute doubleword immediate instruction vpdi . Return true if vpdi could be used . VPDI allows 4 different immediate values ( 0 , 1 , 4 , 5 ) . The 0 and 5 cases are covered by vmrhg and vmrlg already . So we only care about the 1 , 4 cases here . 1 - First element of src1 and second of src2 4 - Second element of src1 and first of src2


<s> void X86PassConfig :: addIRPasses ( ) { addPass ( createAtomicExpandPass ( ) ) ; TargetPassConfig :: addIRPasses ( ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None ) { addPass ( createInterleavedAccessPass ( ) ) ; addPass ( createX86PartialReductionPass ( ) ) ; } addPass ( createIndirectBrExpandPass ( ) ) ; const Triple & TT = TM -> getTargetTriple ( ) ; if ( TT . isOSWindows ( ) ) { if ( TT . getArch ( ) == Triple :: x86_64 ) { addPass ( createCFGuardDispatchPass ( ) ) ; } else { addPass ( createCFGuardCheckPass ( ) ) ; } } if ( TT . getArch ( ) == Triple :: x86_64 ) addPass ( createFineIBTHashesSectionPass ( ) ) ; } </s>

Add common target configurable passes that perform LLVM IR to IR transforms following machine independent optimization .


<s> static bool sh_modes_tieable_p ( machine_mode mode1 , machine_mode mode2 ) { return ( mode1 == mode2 || ( GET_MODE_CLASS ( mode1 ) == GET_MODE_CLASS ( mode2 ) && ( mode1 != SFmode && mode2 != SFmode ) ) ) ; } </s>

Implement TARGET_MODES_TIEABLE_P . If TARGET_HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2 , for any hard reg , then this must be false for correct output . That 's the case for xd registers : we do n't hold SFmode values in them , so we ca n't tie an SFmode pseudos with one in another floating-point mode .


<s> bool SIInstrInfo :: isReallyTriviallyReMaterializable ( const MachineInstr * MI , AliasAnalysis * AA ) const { switch ( MI -> getOpcode ( ) ) { case AMDGPU :: V_MOV_B32_e32 : case AMDGPU :: V_MOV_B32_e64 : return true ; default : return false ; } } </s>

For instructions with opcodes for which the M_REMATERIALIZABLE flag is set , this hook lets the target specify whether the instruction is actually trivially rematerializable , taking into consideration its operands .


<s> static bool offsettable_ok_by_alignment ( rtx op , HOST_WIDE_INT offset , machine_mode mode ) { tree decl ; unsigned HOST_WIDE_INT dsize , dalign , lsb , mask ; if ( ! SYMBOL_REF_P ( op ) ) return false ; if ( mode_supports_dq_form ( mode ) ) return false ; dsize = GET_MODE_SIZE ( mode ) ; decl = SYMBOL_REF_DECL ( op ) ; if ( ! decl ) { if ( dsize == 0 ) return false ; dalign = BITS_PER_UNIT ; if ( SYMBOL_REF_HAS_BLOCK_INFO_P ( op ) && SYMBOL_REF_ANCHOR_P ( op ) && SYMBOL_REF_BLOCK ( op ) != NULL ) { struct object_block * block = SYMBOL_REF_BLOCK ( op ) ; dalign = block -> alignment ; offset += SYMBOL_REF_BLOCK_OFFSET ( op ) ; } else if ( CONSTANT_POOL_ADDRESS_P ( op ) ) { machine_mode cmode = get_pool_mode ( op ) ; dalign = GET_MODE_ALIGNMENT ( cmode ) ; } } else if ( DECL_P ( decl ) ) { dalign = DECL_ALIGN ( decl ) ; if ( dsize == 0 ) { if ( ! DECL_SIZE_UNIT ( decl ) ) return false ; if ( ! tree_fits_uhwi_p ( DECL_SIZE_UNIT ( decl ) ) ) return false ; dsize = tree_to_uhwi ( DECL_SIZE_UNIT ( decl ) ) ; if ( dsize > 32768 ) return false ; dalign /= BITS_PER_UNIT ; if ( dalign > POWERPC64_TOC_POINTER_ALIGNMENT ) dalign = POWERPC64_TOC_POINTER_ALIGNMENT ; return dalign >= dsize ; } } else gcc_unreachable ( ) ; dalign /= BITS_PER_UNIT ; if ( dalign > POWERPC64_TOC_POINTER_ALIGNMENT ) dalign = POWERPC64_TOC_POINTER_ALIGNMENT ; mask = dalign - 1 ; lsb = offset & - offset ; mask &= lsb - 1 ; dalign = mask + 1 ; return dalign >= dsize ; } </s>

Return true if a MODE sized memory accesses to OP plus OFFSET is known to not straddle a 32k boundary .


<s> static rtx alpha_emit_xfloating_compare ( enum rtx_code * pcode , rtx op0 , rtx op1 ) { enum rtx_code cmp_code , res_code ; rtx func , out , operands [ 2 ] , note ; cmp_code = * pcode ; switch ( cmp_code ) { case UNORDERED : cmp_code = EQ ; res_code = LT ; break ; case ORDERED : cmp_code = EQ ; res_code = GE ; break ; case NE : res_code = NE ; break ; case EQ : case LT : case GT : case LE : case GE : res_code = GT ; break ; default : gcc_unreachable ( ) ; } * pcode = res_code ; func = alpha_lookup_xfloating_lib_func ( cmp_code ) ; operands [ 0 ] = op0 ; operands [ 1 ] = op1 ; out = gen_reg_rtx ( DImode ) ; note = gen_rtx_fmt_ee ( cmp_code , VOIDmode , op0 , op1 ) ; note = gen_rtx_UNSPEC ( DImode , gen_rtvec ( 1 , note ) , UNSPEC_XFLT_COMPARE ) ; alpha_emit_xfloating_libcall ( func , out , operands , 2 , note ) ; return out ; } </s>

Emit an X_floating library function call for a comparison .


<s> static rtx alpha_function_value_1 ( const_tree valtype , const_tree func ATTRIBUTE_UNUSED , machine_mode mode ) { unsigned int regnum , dummy ATTRIBUTE_UNUSED ; enum mode_class mclass ; gcc_assert ( ! valtype || ! alpha_return_in_memory ( valtype , func ) ) ; if ( valtype ) mode = TYPE_MODE ( valtype ) ; mclass = GET_MODE_CLASS ( mode ) ; switch ( mclass ) { case MODE_INT : if ( ! ( TARGET_ABI_OPEN_VMS && valtype && AGGREGATE_TYPE_P ( valtype ) ) ) PROMOTE_MODE ( mode , dummy , valtype ) ; case MODE_COMPLEX_INT : case MODE_VECTOR_INT : regnum = 0 ; break ; case MODE_FLOAT : regnum = 32 ; break ; case MODE_COMPLEX_FLOAT : { machine_mode cmode = GET_MODE_INNER ( mode ) ; return gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( 2 , gen_rtx_EXPR_LIST ( VOIDmode , gen_rtx_REG ( cmode , 32 ) , const0_rtx ) , gen_rtx_EXPR_LIST ( VOIDmode , gen_rtx_REG ( cmode , 33 ) , GEN_INT ( GET_MODE_SIZE ( cmode ) ) ) ) ) ; } case MODE_RANDOM : gcc_assert ( TARGET_ABI_OPEN_VMS && mode == BLKmode ) ; regnum = 0 ; break ; default : gcc_unreachable ( ) ; } return gen_rtx_REG ( mode , regnum ) ; } </s>

Define how to find the value returned by a function . VALTYPE is the data type of the value ( as a tree ) . If the precise function being called is known , FUNC is its FUNCTION_DECL ; otherwise , FUNC is 0 . MODE is set instead of VALTYPE for libcalls . On Alpha the value is found in $ 0 for integer functions and $ f0 for floating-point functions .


<s>
void
s390_function_profiler
(
FILE
*
file
,
int
labelno
)
{
rtx
op
[
7
]
;
char
label
[
128
]
;
ASM_GENERATE_INTERNAL_LABEL
(
label
,
"LP"
,
labelno
)
;
fprintf
(
file
,
"# function profiler \n"
)
;
op
[
0
]
=
gen_rtx_REG
(
Pmode
,
RETURN_REGNUM
)
;
op
[
1
]
=
gen_rtx_REG
(
Pmode
,
STACK_POINTER_REGNUM
)
;
op
[
1
]
=
gen_rtx_MEM
(
Pmode
,
plus_constant
(
Pmode
,
op
[
1
]
,
UNITS_PER_LONG
)
)
;
op
[
2
]
=
gen_rtx_REG
(
Pmode
,
1
)
;
op
[
3
]
=
gen_rtx_SYMBOL_REF
(
Pmode
,
label
)
;
SYMBOL_REF_FLAGS
(
op
[
3
]
)
=
SYMBOL_FLAG_LOCAL
;
op
[
4
]
=
gen_rtx_SYMBOL_REF
(
Pmode
,
"_mcount"
)
;
if
(
flag_pic
)
{
op
[
4
]
=
gen_rtx_UNSPEC
(
Pmode
,
gen_rtvec
(
1
,
op
[
4
]
)
,
UNSPEC_PLT
)
;
op
[
4
]
=
gen_rtx_CONST
(
Pmode
,
op
[
4
]
)
;
}
if
(
TARGET_64BIT
)
{
output_asm_insn
(
"stg\t%0,%1"
,
op
)
;
output_asm_insn
(
"larl\t%2,%3"
,
op
)
;
output_asm_insn
(
"brasl\t%0,%4"
,
op
)
;
output_asm_insn
(
"lg\t%0,%1"
,
op
)
;
}
else
if
(
TARGET_CPU_ZARCH
)
{
output_asm_insn
(
"st\t%0,%1"
,
op
)
;
output_asm_insn
(
"larl\t%2,%3"
,
op
)
;
output_asm_insn
(
"brasl\t%0,%4"
,
op
)
;
output_asm_insn
(
"l\t%0,%1"
,
op
)
;
}
else
if
(
!
flag_pic
)
{
op
[
6
]
=
gen_label_rtx
(
)
;
output_asm_insn
(
"st\t%0,%1"
,
op
)
;
output_asm_insn
(
"bras\t%2,%l6"
,
op
)
;
output_asm_insn
(
".long\t%4"
,
op
)
;
output_asm_insn
(
".long\t%3"
,
op
)
;
targetm
.
asm_out
.
internal_label
(
file
,
"L"
,
CODE_LABEL_NUMBER
(
op
[
6
]
)
)
;
output_asm_insn
(
"l\t%0,0(%2)"
,
op
)
;
output_asm_insn
(
"l\t%2,4(%2)"
,
op
)
;
output_asm_insn
(
"basr\t%0,%0"
,
op
)
;
output_asm_insn
(
"l\t%0,%1"
,
op
)
;
}
else
{
op
[
5
]
=
gen_label_rtx
(
)
;
op
[
6
]
=
gen_label_rtx
(
)
;
output_asm_insn
(
"st\t%0,%1"
,
op
)
;
output_asm_insn
(
"bras\t%2,%l6"
,
op
)
;
targetm
.
asm_out
.
internal_label
(
file
,
"L"
,
CODE_LABEL_NUMBER
(
op
[
5
]
)
)
;
output_asm_insn
(
".long\t%4-%l5"
,
op
)
;
output_asm_insn
(
".long\t%3-%l5"
,
op
)
;
targetm
.
asm_out
.
internal_label
(
file
,
"L"
,
CODE_LABEL_NUMBER
(
op
[
6
]
)
)
;
output_asm_insn
(
"lr\t%0,%2"
,
op
)
;
output_asm_insn
(
"a\t%0,0(%2)"
,
op
)
;
output_asm_insn
(
"a\t%2,4(%2)"
,
op
)
;
output_asm_insn
(
"basr\t%0,%0"
,
op
)
;
output_asm_insn
(
"l\t%0,%1"
,
op
)
;
}
}
</s>

Output assembler code to FILE to call a profiler hook .


<s> bool DCPU16DAGToDAGISel :: SelectInlineAsmMemoryOperand ( const SDValue & Op , char ConstraintCode , std :: vector < SDValue > & OutOps ) { SDValue Op0 , Op1 ; switch ( ConstraintCode ) { default : return true ; case 'm' : if ( ! SelectAddr ( Op , Op0 , Op1 ) ) return true ; break ; } OutOps . push_back ( Op0 ) ; OutOps . push_back ( Op1 ) ; return false ; } </s>

SelectInlineAsmMemoryOperand - Select the specified address as a target addressing mode , according to the specified constraint .


<s> virtual const LC3bSubtarget * getSubtargetImpl ( ) const { return & Subtarget ; } </s>


<s> static void mep_rewrite_maddsi3 ( rtx_insn * insn , rtx dest , rtx src1 , rtx src2 , rtx src3 ) { rtx lo , pattern ; lo = gen_rtx_REG ( SImode , LO_REGNO ) ; emit_insn_before ( gen_movsi ( copy_rtx ( lo ) , src3 ) , insn ) ; if ( dest ) pattern = gen_maddsi3r ( lo , dest , copy_rtx ( dest ) , mep_mulr_source ( insn , dest , src1 , src2 ) , copy_rtx ( lo ) ) ; else pattern = gen_maddsi3_lo ( lo , src1 , src2 , copy_rtx ( lo ) ) ; mep_rewrite_mult ( insn , pattern ) ; } </s>

Like mep_rewrite_mulsi3 , but calculate SRC1 * SRC2 + SRC3 . First copy SRC3 into $ lo , then use either madd or maddr . The move into $ lo will be deleted by a peephole2 if SRC3 is already in $ lo .


<s> static void rs6000_set_handled_components ( sbitmap components ) { rs6000_stack_t * info = rs6000_stack_info ( ) ; for ( int i = info -> first_gp_reg_save ; i < 32 ; i ++ ) if ( bitmap_bit_p ( components , i ) ) cfun -> machine -> gpr_is_wrapped_separately [ i ] = true ; for ( int i = info -> first_fp_reg_save ; i < 64 ; i ++ ) if ( bitmap_bit_p ( components , i ) ) cfun -> machine -> fpr_is_wrapped_separately [ i - 32 ] = true ; if ( bitmap_bit_p ( components , 0 ) ) cfun -> machine -> lr_is_wrapped_separately = true ; } </s>


<s> virtual unsigned int execute ( function * ) { return aarch64_do_track_speculation ( ) ; } </s>


<s> StringRef getPassName ( ) const override { return RISCV_EXPAND_PSEUDO_NAME ; } </s>

getPassName - Return a nice clean name for a pass .


"instruction requires a WASM feature not currently enabled"

MatchAndEmitInstruction - Recognize a series of operands of a parsed instruction as an actual MCInst and emit it to the specified MCStreamer .


<s> void RISCVTargetStreamer :: emitTargetAttributes ( const MCSubtargetInfo & STI ) { if ( STI . hasFeature ( RISCV :: FeatureRV32E ) ) emitAttribute ( RISCVAttrs :: STACK_ALIGN , RISCVAttrs :: ALIGN_4 ) ; else emitAttribute ( RISCVAttrs :: STACK_ALIGN , RISCVAttrs :: ALIGN_16 ) ; std :: string Arch = "rv32" ; if ( STI . hasFeature ( RISCV :: Feature64Bit ) ) Arch = "rv64" ; if ( STI . hasFeature ( RISCV :: FeatureRV32E ) ) Arch += "e1p9" ; else Arch += "i2p0" ; if ( STI . hasFeature ( RISCV :: FeatureStdExtM ) ) Arch += "_m2p0" ; if ( STI . hasFeature ( RISCV :: FeatureStdExtA ) ) Arch += "_a2p0" ; if ( STI . hasFeature ( RISCV :: FeatureStdExtF ) ) Arch += "_f2p0" ; if ( STI . hasFeature ( RISCV :: FeatureStdExtD ) ) Arch += "_d2p0" ; if ( STI . hasFeature ( RISCV :: FeatureStdExtC ) ) Arch += "_c2p0" ; if ( STI . hasFeature ( RISCV :: FeatureStdExtB ) ) Arch += "_b0p93" ; if ( STI . hasFeature ( RISCV :: FeatureStdExtV ) ) Arch += "_v0p10" ; if ( STI . hasFeature ( RISCV :: FeatureStdExtZfh ) ) Arch += "_zfh0p1" ; if ( STI . hasFeature ( RISCV :: FeatureStdExtZba ) ) Arch += "_zba0p93" ; if ( STI . hasFeature ( RISCV :: FeatureStdExtZbb ) ) Arch += "_zbb0p93" ; if ( STI . hasFeature ( RISCV :: FeatureStdExtZbc ) ) Arch += "_zbc0p93" ; if ( STI . hasFeature ( RISCV :: FeatureStdExtZbe ) ) Arch += "_zbe0p93" ; if ( STI . hasFeature ( RISCV :: FeatureStdExtZbf ) ) Arch += "_zbf0p93" ; if ( STI . hasFeature ( RISCV :: FeatureStdExtZbm ) ) Arch += "_zbm0p93" ; if ( STI . hasFeature ( RISCV :: FeatureStdExtZbp ) ) Arch += "_zbp0p93" ; if ( STI . hasFeature ( RISCV :: FeatureStdExtZbproposedc ) ) Arch += "_zbproposedc0p93" ; if ( STI . hasFeature ( RISCV :: FeatureStdExtZbr ) ) Arch += "_zbr0p93" ; if ( STI . hasFeature ( RISCV :: FeatureStdExtZbs ) ) Arch += "_zbs0p93" ; if ( STI . hasFeature ( RISCV :: FeatureStdExtZbt ) ) Arch += "_zbt0p93" ; if ( STI . hasFeature ( RISCV :: FeatureStdExtZvamo ) ) Arch += "_zvamo0p10" ; if ( STI . hasFeature ( RISCV :: FeatureStdExtZvlsseg ) ) Arch += "_zvlsseg0p10" ; emitTextAttribute ( RISCVAttrs :: ARCH , Arch ) ; } </s>

Emit the build attributes that only depend on the hardware that we expect .


<s> bool DLXTargetObjectFile :: isConstantInSmallSection ( const DataLayout & DL , const Constant * CN ) const { return isInSmallSection ( DL . getTypeAllocSize ( CN -> getType ( ) ) ) ; } </s>

Return true if this constant should be placed into small data section .


<s>
bool
X86FrameLowering
::
canUseAsEpilogue
(
const
MachineBasicBlock
&
MBB
)
const
{
assert
(
MBB
.
getParent
(
)
&&
"Block is not attached to a function!"
)
;
if
(
canUseLEAForSPInEpilogue
(
*
MBB
.
getParent
(
)
)
)
return
true
;
return
!
terminatorsNeedFlagsAsInput
(
MBB
)
;
}
</s>

Check whether or not the given MBB can be used as a epilogue for the target .


<s> static void mips_emit_int_order_test ( enum rtx_code code , bool * invert_ptr , rtx target , rtx cmp0 , rtx cmp1 ) { machine_mode mode ; mode = GET_MODE ( cmp0 ) ; if ( mips_canonicalize_int_order_test ( & code , & cmp1 , mode ) ) mips_emit_binary ( code , target , cmp0 , cmp1 ) ; else { enum rtx_code inv_code = reverse_condition ( code ) ; if ( ! mips_canonicalize_int_order_test ( & inv_code , & cmp1 , mode ) ) { cmp1 = force_reg ( mode , cmp1 ) ; mips_emit_int_order_test ( code , invert_ptr , target , cmp0 , cmp1 ) ; } else if ( invert_ptr == 0 ) { rtx inv_target ; inv_target = mips_force_binary ( GET_MODE ( target ) , inv_code , cmp0 , cmp1 ) ; mips_emit_binary ( XOR , target , inv_target , const1_rtx ) ; } else { * invert_ptr = ! * invert_ptr ; mips_emit_binary ( inv_code , target , cmp0 , cmp1 ) ; } } } </s>

Compare CMP0 and CMP1 using ordering test CODE and store the result in TARGET . CMP0 and TARGET are register_operands . If INVERT_PTR is nonnull , it 's OK to set TARGET to the inverse of the result and flip * INVERT_PTR instead .


<s> bool Thumb1FrameLowering :: restoreCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo * TRI ) const { if ( CSI . empty ( ) ) return false ; MachineFunction & MF = * MBB . getParent ( ) ; ARMFunctionInfo * AFI = MF . getInfo < ARMFunctionInfo > ( ) ; const TargetInstrInfo & TII = * MF . getTarget ( ) . getInstrInfo ( ) ; bool isVarArg = AFI -> getVarArgsRegSaveSize ( ) > 0 ; DebugLoc DL = MI -> getDebugLoc ( ) ; MachineInstrBuilder MIB = BuildMI ( MF , DL , TII . get ( ARM :: tPOP ) ) ; AddDefaultPred ( MIB ) ; bool NumRegs = false ; for ( unsigned i = CSI . size ( ) ; i != 0 ; -- i ) { unsigned Reg = CSI [ i - 1 ] . getReg ( ) ; if ( Reg == ARM :: LR ) { if ( isVarArg ) continue ; Reg = ARM :: PC ; ( * MIB ) . setDesc ( TII . get ( ARM :: tPOP_RET ) ) ; MIB . copyImplicitOps ( & * MI ) ; MI = MBB . erase ( MI ) ; } MIB . addReg ( Reg , getDefRegState ( true ) ) ; NumRegs = true ; } if ( NumRegs ) MBB . insert ( MI , & * MIB ) ; else MF . DeleteMachineInstr ( MIB ) ; return true ; } </s>

restoreCalleeSavedRegisters - Issues instruction ( s ) to restore all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of load instructions via loadRegToStackSlot ( ) .


<s> void MBlazeAsmPrinter :: EmitInstruction ( const MachineInstr * MI ) { MBlazeMCInstLower MCInstLowering ( OutContext , * Mang , * this ) ; MCInst TmpInst ; MCInstLowering . Lower ( MI , TmpInst ) ; OutStreamer . EmitInstruction ( TmpInst ) ; } </s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s> bool AArch64TargetLowering :: isIntDivCheap ( EVT VT , AttributeList Attr ) const { bool OptSize = Attr . hasFnAttribute ( Attribute :: MinSize ) ; return OptSize && ! VT . isVector ( ) ; } </s>

Return true if integer divide is usually cheaper than a sequence of several shifts , adds , and multiplies for this target .


<s> MachineBasicBlock :: iterator OR1KFrameLowering :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { return MBB . erase ( I ) ; } </s>

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .


Conditionally modify the settings of the register file .


<s> void PPCInstrInfo :: setSpecialOperandAttr ( MachineInstr & MI , uint16_t Flags ) const { MI . setFlags ( Flags ) ; MI . clearFlag ( MachineInstr :: MIFlag :: NoSWrap ) ; MI . clearFlag ( MachineInstr :: MIFlag :: NoUWrap ) ; MI . clearFlag ( MachineInstr :: MIFlag :: IsExact ) ; } </s>

This is an architecture-specific helper function of reassociateOps .


<s> static unsigned int insn_is_store_p ( rtx insn ) { rtx body = PATTERN ( insn ) ; if ( GET_CODE ( body ) == SET && GET_CODE ( SET_DEST ( body ) ) == MEM ) return 1 ; if ( GET_CODE ( body ) != PARALLEL ) return 0 ; rtx set = XVECEXP ( body , 0 , 0 ) ; if ( GET_CODE ( set ) == SET && GET_CODE ( SET_DEST ( set ) ) == MEM ) return 1 ; return 0 ; } </s>

Return 1 iff INSN is a store insn , including permuting stores that represent an stvxd2x instruction ; else return 0 .


<s>
bool
M88kAsmParser
::
ParseInstruction
(
ParseInstructionInfo
&
Info
,
StringRef
Name
,
SMLoc
NameLoc
,
OperandVector
&
Operands
)
{
Operands
.
push_back
(
M88kOperand
::
createToken
(
Name
,
NameLoc
)
)
;
if
(
getLexer
(
)
.
isNot
(
AsmToken
::
EndOfStatement
)
)
{
if
(
parseOperand
(
Operands
,
Name
)
)
{
return
Error
(
getLexer
(
)
.
getLoc
(
)
,
"expected operand"
)
;
}
if
(
getLexer
(
)
.
is
(
AsmToken
::
Comma
)
)
{
Parser
.
Lex
(
)
;
if
(
parseOperand
(
Operands
,
Name
)
)
{
return
Error
(
getLexer
(
)
.
getLoc
(
)
,
"expected operand"
)
;
}
if
(
getLexer
(
)
.
is
(
AsmToken
::
Comma
)
)
{
Parser
.
Lex
(
)
;
if
(
parseOperand
(
Operands
,
Name
)
)
{
return
Error
(
getLexer
(
)
.
getLoc
(
)
,
"expected operand"
)
;
}
}
else
if
(
getLexer
(
)
.
is
(
AsmToken
::
LBrac
)
)
{
if
(
parseScaledRegister
(
Operands
)
)
return
Error
(
getLexer
(
)
.
getLoc
(
)
,
"expected scaled register operand"
)
;
}
}
if
(
getLexer
(
)
.
isNot
(
AsmToken
::
EndOfStatement
)
)
return
Error
(
getLexer
(
)
.
getLoc
(
)
,
"unexpected token in argument list"
)
;
}
Parser
.
Lex
(
)
;
return
false
;
}
</s>

ParseInstruction - Parse one assembly instruction .


<s> unsigned find_next ( unsigned Prev ) const { int Next = Bits . find_next ( v2x ( Prev ) ) ; if ( Next < 0 ) return 0 ; return x2v ( Next ) ; } </s>

find_next - Returns the index of the next set bit starting from the `` Curr '' bit .


<s>
const
MCFixupKindInfo
&
getFixupKindInfo
(
MCFixupKind
Kind
)
const
override
{
const
static
MCFixupKindInfo
Infos
[
TOY
::
NumTargetFixupKinds
]
=
{
{
"fixup_toy_mov_hi16_pcrel"
,
0
,
32
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_toy_mov_lo16_pcrel"
,
0
,
32
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
}
;
if
(
Kind
<
FirstTargetFixupKind
)
{
return
MCAsmBackend
::
getFixupKindInfo
(
Kind
)
;
}
assert
(
unsigned
(
Kind
FirstTargetFixupKind
)
<
getNumFixupKinds
(
)
&&
"Invalid kind!"
)
;
return
Infos
[
Kind
FirstTargetFixupKind
]
;
}
</s>


<s> static machine_mode ia64_c_mode_for_suffix ( char suffix ) { if ( suffix == 'q' ) return TFmode ; if ( suffix == 'w' ) return XFmode ; return VOIDmode ; } </s>


<s> bool PPCLoopDataPrefetch :: runOnFunction ( Function & F ) { LI = & getAnalysis < LoopInfoWrapperPass > ( ) . getLoopInfo ( ) ; SE = & getAnalysis < ScalarEvolution > ( ) ; DL = & F . getParent ( ) -> getDataLayout ( ) ; AC = & getAnalysis < AssumptionCacheTracker > ( ) . getAssumptionCache ( F ) ; TTI = & getAnalysis < TargetTransformInfoWrapperPass > ( ) . getTTI ( F ) ; bool MadeChange = false ; for ( auto I = LI -> begin ( ) , IE = LI -> end ( ) ; I != IE ; ++ I ) for ( auto L = df_begin ( * I ) , LE = df_end ( * I ) ; L != LE ; ++ L ) MadeChange |= runOnLoop ( * L ) ; return MadeChange ; } </s>

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .


<s> bool ARMTargetMachine :: addPreEmitPass ( PassManagerBase & PM , bool Fast ) { if ( ! Fast && ! DisableLdStOpti && ! Subtarget . isThumb ( ) ) PM . add ( createARMLoadStoreOptimizationPass ( ) ) ; if ( ! Fast && ! DisableIfConversion && ! Subtarget . isThumb ( ) ) PM . add ( createIfConverterPass ( ) ) ; PM . add ( createARMConstantIslandPass ( ) ) ; return true ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s> bool PPCTargetLowering :: SelectAddressRegRegOnly ( SDValue N , SDValue & Base , SDValue & Index , SelectionDAG & DAG ) const { if ( SelectAddressRegReg ( N , Base , Index , DAG ) ) return true ; if ( N . getOpcode ( ) == ISD :: ADD ) { Base = N . getOperand ( 0 ) ; Index = N . getOperand ( 1 ) ; return true ; } Base = DAG . getRegister ( PPCSubTarget . isPPC64 ( ) ? PPC :: X0 : PPC :: R0 , N . getValueType ( ) ) ; Index = N ; return true ; } </s>

SelectAddressRegRegOnly - Given the specified addressed , force it to be represented as an indexed [ r+r ] operation .


<s> bool AMDGPUAsmParser :: ParseDirective ( AsmToken DirectiveID ) { StringRef IDVal = DirectiveID . getString ( ) ; if ( AMDGPU :: IsaInfo :: hasCodeObjectV3 ( & getSTI ( ) ) ) { if ( IDVal == ".amdgcn_target" ) return ParseDirectiveAMDGCNTarget ( ) ; if ( IDVal == ".amdhsa_kernel" ) return ParseDirectiveAMDHSAKernel ( ) ; if ( IDVal == AMDGPU :: HSAMD :: V3 :: AssemblerDirectiveBegin ) return ParseDirectiveHSAMetadata ( ) ; } else { if ( IDVal == ".hsa_code_object_version" ) return ParseDirectiveHSACodeObjectVersion ( ) ; if ( IDVal == ".hsa_code_object_isa" ) return ParseDirectiveHSACodeObjectISA ( ) ; if ( IDVal == ".amd_kernel_code_t" ) return ParseDirectiveAMDKernelCodeT ( ) ; if ( IDVal == ".amdgpu_hsa_kernel" ) return ParseDirectiveAMDGPUHsaKernel ( ) ; if ( IDVal == ".amd_amdgpu_isa" ) return ParseDirectiveISAVersion ( ) ; if ( IDVal == AMDGPU :: HSAMD :: AssemblerDirectiveBegin ) return ParseDirectiveHSAMetadata ( ) ; } if ( IDVal == ".amdgpu_lds" ) return ParseDirectiveAMDGPULDS ( ) ; if ( IDVal == PALMD :: AssemblerDirectiveBegin ) return ParseDirectivePALMetadataBegin ( ) ; if ( IDVal == PALMD :: AssemblerDirective ) return ParseDirectivePALMetadata ( ) ; return true ; } </s>

ParseDirective - Parse a target specific assembler directive This method is deprecated , use 'parseDirective ' instead .


<s> static void mips_load_call_address ( rtx dest , rtx addr , int sibcall_p ) { if ( TARGET_EXPLICIT_RELOCS && ! ( sibcall_p && TARGET_NEWABI ) && global_got_operand ( addr , VOIDmode ) ) { rtx high , lo_sum_symbol ; high = mips_unspec_offset_high ( dest , pic_offset_table_rtx , addr , SYMBOL_GOTOFF_CALL ) ; lo_sum_symbol = mips_unspec_address ( addr , SYMBOL_GOTOFF_CALL ) ; if ( Pmode == SImode ) emit_insn ( gen_load_callsi ( dest , high , lo_sum_symbol ) ) ; else emit_insn ( gen_load_calldi ( dest , high , lo_sum_symbol ) ) ; } else emit_move_insn ( dest , addr ) ; } </s>

Load function address ADDR into register DEST . SIBCALL_P is true if the address is needed for a sibling call .


<s> bool NyuziTargetLowering :: isShuffleMaskLegal ( ArrayRef < int > Mask , EVT VT ) const { if ( Mask . size ( ) != 16 ) return false ; for ( int val : Mask ) { if ( val > 31 ) return false ; } return true ; } </s>

Targets can use this to indicate that they only support some VECTOR_SHUFFLE operations , those with specific masks .


<s>
int
MSP430RegisterInfo
::
getDwarfRegNum
(
unsigned
RegNum
,
bool
isEH
)
const
{
llvm_unreachable
(
"Not implemented yet!"
)
;
return
0
;
}
</s>

Map a target register to an equivalent dwarf register number .


<s> bool ARMPassConfig :: addInstSelector ( ) { addPass ( createARMISelDag ( getARMTargetMachine ( ) , getOptLevel ( ) ) ) ; return false ; } </s>

addInstSelector - This method should install an instruction selector pass , which converts from LLVM code to machine instructions .


<s> void s390_set_has_landing_pad_p ( bool value ) { cfun -> machine -> has_landing_pad_p = value ; } </s>

Set the has_landing_pad_p flag in struct machine_function to VALUE .


<s>
bool
ARCBranchFinalize
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
LLVM_DEBUG
(
dbgs
(
)
<<
"Running ARC Branch Finalize on "
<<
MF
.
getName
(
)
<<
"\n"
)
;
std
::
vector
<
MachineInstr
*
>
Branches
;
bool
Changed
=
false
;
unsigned
MaxSize
=
0
;
TII
=
MF
.
getSubtarget
<
ARCSubtarget
>
(
)
.
getInstrInfo
(
)
;
std
::
map
<
MachineBasicBlock
*
,
unsigned
>
BlockToPCMap
;
std
::
vector
<
std
::
pair
<
MachineInstr
*
,
unsigned
>>
BranchToPCList
;
unsigned
PC
=
0
;
for
(
auto
&
MBB
:
MF
)
{
BlockToPCMap
.
insert
(
std
::
make_pair
(
&
MBB
,
PC
)
)
;
for
(
auto
&
MI
:
MBB
)
{
unsigned
Size
=
TII
->
getInstSizeInBytes
(
MI
)
;
if
(
Size
>
8
||
Size
==
0
)
{
LLVM_DEBUG
(
dbgs
(
)
<<
"Unknown (or size 0) size for: "
<<
MI
<<
"\n"
)
;
}
else
{
MaxSize
+=
Size
;
}
if
(
MI
.
isBranch
(
)
)
{
Branches
.
push_back
(
&
MI
)
;
BranchToPCList
.
emplace_back
(
&
MI
,
PC
)
;
}
PC
+=
Size
;
}
}
for
(
auto
P
:
BranchToPCList
)
{
if
(
isBRccPseudo
(
P
.
first
)
)
isInt
<
9
>
(
MaxSize
)
replaceWithBRcc
(
P
.
first
)
:
replaceWithCmpBcc
(
P
.
first
)
;
}
LLVM_DEBUG
(
dbgs
(
)
<<
"Estimated function size for "
<<
MF
.
getName
(
)
<<
": "
<<
MaxSize
<<
"\n"
)
;
return
Changed
;
}
</s>

runOnMachineFunction - Emit the function body .

ARC
ARC
"Running ARC Branch Finalize on "
"\n"
0
ARC
0
8
0
"Unknown (or size 0) size for: "
"\n"
9
"Estimated function size for "
": "
"\n"


"_reflect function should not have a body"

"_reflect's return type should be integer"

"Wrong number of operands to __nvvm_reflect function"

"Format of __nvvm__reflect function not recognized"

"Format of __nvvm_reflect function not recognized"

"Format of _reflect function not recognized"


<s> bool AArch64CallLowering :: lowerFormalArguments ( MachineIRBuilder & MIRBuilder , const Function & F , ArrayRef < ArrayRef < Register >> VRegs , FunctionLoweringInfo & FLI ) const { MachineFunction & MF = MIRBuilder . getMF ( ) ; MachineBasicBlock & MBB = MIRBuilder . getMBB ( ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; auto & DL = F . getParent ( ) -> getDataLayout ( ) ; SmallVector < ArgInfo , 8 > SplitArgs ; unsigned i = 0 ; for ( auto & Arg : F . args ( ) ) { if ( DL . getTypeStoreSize ( Arg . getType ( ) ) . isZero ( ) ) continue ; ArgInfo OrigArg { VRegs [ i ] , Arg } ; setArgFlags ( OrigArg , i + AttributeList :: FirstArgIndex , DL , F ) ; if ( Arg . hasAttribute ( Attribute :: SwiftAsync ) ) MF . getInfo < AArch64FunctionInfo > ( ) -> setHasSwiftAsyncContext ( true ) ; splitToValueTypes ( OrigArg , SplitArgs , DL , F . getCallingConv ( ) ) ; ++ i ; } if ( ! MBB . empty ( ) ) MIRBuilder . setInstr ( * MBB . begin ( ) ) ; const AArch64TargetLowering & TLI = * getTLI < AArch64TargetLowering > ( ) ; CCAssignFn * AssignFn = TLI . CCAssignFnForCall ( F . getCallingConv ( ) , false ) ; AArch64IncomingValueAssigner Assigner ( AssignFn , AssignFn ) ; FormalArgHandler Handler ( MIRBuilder , MRI ) ; if ( ! determineAndHandleAssignments ( Handler , Assigner , SplitArgs , MIRBuilder , F . getCallingConv ( ) , F . isVarArg ( ) ) ) return false ; AArch64FunctionInfo * FuncInfo = MF . getInfo < AArch64FunctionInfo > ( ) ; uint64_t StackOffset = Assigner . StackOffset ; if ( F . isVarArg ( ) ) { auto & Subtarget = MF . getSubtarget < AArch64Subtarget > ( ) ; if ( ! Subtarget . isTargetDarwin ( ) ) { return false ; } StackOffset = alignTo ( Assigner . StackOffset , Subtarget . isTargetILP32 ( ) ? 4 : 8 ) ; auto & MFI = MIRBuilder . getMF ( ) . getFrameInfo ( ) ; FuncInfo -> setVarArgsStackIndex ( MFI . CreateFixedObject ( 4 , StackOffset , true ) ) ; } if ( doesCalleeRestoreStack ( F . getCallingConv ( ) , MF . getTarget ( ) . Options . GuaranteedTailCallOpt ) ) { StackOffset = alignTo ( StackOffset , 16 ) ; FuncInfo -> setArgumentStackToRestore ( StackOffset ) ; } FuncInfo -> setBytesInStackArgArea ( StackOffset ) ; auto & Subtarget = MF . getSubtarget < AArch64Subtarget > ( ) ; if ( Subtarget . hasCustomCallingConv ( ) ) Subtarget . getRegisterInfo ( ) -> UpdateCustomCalleeSavedRegs ( MF ) ; handleMustTailForwardedRegisters ( MIRBuilder , AssignFn ) ; MIRBuilder . setMBB ( MBB ) ; return true ; } </s>

This hook must be implemented to lower the incoming ( formal ) arguments , described by VRegs , for GlobalISel .


" was Pass-through, is now Dirty-out.\n"


<s>
static
rtx
gen_float_relational
(
enum
rtx_code
test_code
,
rtx
cmp0
,
rtx
cmp1
)
{
rtx
(
*
gen_fn
)
(
rtx
,
rtx
,
rtx
)
;
rtx
brtmp
;
int
reverse_regs
,
invert
;
switch
(
test_code
)
{
case
EQ
:
reverse_regs
=
0
;
invert
=
0
;
gen_fn
=
gen_seq_sf
;
break
;
case
NE
:
reverse_regs
=
0
;
invert
=
1
;
gen_fn
=
gen_seq_sf
;
break
;
case
LE
:
reverse_regs
=
0
;
invert
=
0
;
gen_fn
=
gen_sle_sf
;
break
;
case
GT
:
reverse_regs
=
1
;
invert
=
0
;
gen_fn
=
gen_slt_sf
;
break
;
case
LT
:
reverse_regs
=
0
;
invert
=
0
;
gen_fn
=
gen_slt_sf
;
break
;
case
GE
:
reverse_regs
=
1
;
invert
=
0
;
gen_fn
=
gen_sle_sf
;
break
;
case
UNEQ
:
reverse_regs
=
0
;
invert
=
0
;
gen_fn
=
gen_suneq_sf
;
break
;
case
LTGT
:
reverse_regs
=
0
;
invert
=
1
;
gen_fn
=
gen_suneq_sf
;
break
;
case
UNLE
:
reverse_regs
=
0
;
invert
=
0
;
gen_fn
=
gen_sunle_sf
;
break
;
case
UNGT
:
reverse_regs
=
1
;
invert
=
0
;
gen_fn
=
gen_sunlt_sf
;
break
;
case
UNLT
:
reverse_regs
=
0
;
invert
=
0
;
gen_fn
=
gen_sunlt_sf
;
break
;
case
UNGE
:
reverse_regs
=
1
;
invert
=
0
;
gen_fn
=
gen_sunle_sf
;
break
;
case
UNORDERED
:
reverse_regs
=
0
;
invert
=
0
;
gen_fn
=
gen_sunordered_sf
;
break
;
case
ORDERED
:
reverse_regs
=
0
;
invert
=
1
;
gen_fn
=
gen_sunordered_sf
;
break
;
default
:
fatal_insn
(
"bad test"
,
gen_rtx_fmt_ee
(
test_code
,
VOIDmode
,
cmp0
,
cmp1
)
)
;
reverse_regs
=
0
;
invert
=
0
;
gen_fn
=
0
;
}
if
(
reverse_regs
)
{
rtx
temp
=
cmp0
;
cmp0
=
cmp1
;
cmp1
=
temp
;
}
brtmp
=
gen_rtx_REG
(
CCmode
,
FPCC_REGNUM
)
;
emit_insn
(
gen_fn
(
brtmp
,
cmp0
,
cmp1
)
)
;
return
gen_rtx_fmt_ee
(
invert
EQ
:
NE
,
VOIDmode
,
brtmp
,
const0_rtx
)
;
}
</s>

Generate the code to compare two float values . The return value is the comparison expression .


<s> void AArch64ConditionalCompares :: getAnalysisUsage ( AnalysisUsage & AU ) const { AU . addRequired < MachineDominatorTree > ( ) ; AU . addPreserved < MachineDominatorTree > ( ) ; AU . addRequired < MachineLoopInfo > ( ) ; AU . addPreserved < MachineLoopInfo > ( ) ; AU . addRequired < MachineTraceMetrics > ( ) ; AU . addPreserved < MachineTraceMetrics > ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> MachineBasicBlock * AMDGPUCFGStructurizer :: clone ( MachineBasicBlock * MBB ) { MachineFunction * Func = MBB -> getParent ( ) ; MachineBasicBlock * NewMBB = Func -> CreateMachineBasicBlock ( ) ; Func -> push_back ( NewMBB ) ; for ( const MachineInstr & It : * MBB ) NewMBB -> push_back ( Func -> CloneMachineInstr ( & It ) ) ; return NewMBB ; } </s>

Make a functionally equivalent copy of this MachineFunctionInfo in MF .


<s> void SIInstrInfo :: storeRegToStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , unsigned SrcReg , bool isKill , int FrameIndex , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { MachineFunction * MF = MBB . getParent ( ) ; SIMachineFunctionInfo * MFI = MF -> getInfo < SIMachineFunctionInfo > ( ) ; MachineFrameInfo & FrameInfo = MF -> getFrameInfo ( ) ; const DebugLoc & DL = MBB . findDebugLoc ( MI ) ; unsigned Size = FrameInfo . getObjectSize ( FrameIndex ) ; unsigned Align = FrameInfo . getObjectAlignment ( FrameIndex ) ; MachinePointerInfo PtrInfo = MachinePointerInfo :: getFixedStack ( * MF , FrameIndex ) ; MachineMemOperand * MMO = MF -> getMachineMemOperand ( PtrInfo , MachineMemOperand :: MOStore , Size , Align ) ; unsigned SpillSize = TRI -> getSpillSize ( * RC ) ; if ( RI . isSGPRClass ( RC ) ) { MFI -> setHasSpilledSGPRs ( ) ; const MCInstrDesc & OpDesc = get ( getSGPRSpillSaveOpcode ( SpillSize ) ) ; if ( TargetRegisterInfo :: isVirtualRegister ( SrcReg ) && SpillSize == 4 ) { MachineRegisterInfo & MRI = MF -> getRegInfo ( ) ; MRI . constrainRegClass ( SrcReg , & AMDGPU :: SReg_32_XM0RegClass ) ; } MachineInstrBuilder Spill = BuildMI ( MBB , MI , DL , OpDesc ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addFrameIndex ( FrameIndex ) . addMemOperand ( MMO ) . addReg ( MFI -> getScratchRSrcReg ( ) , RegState :: Implicit ) . addReg ( MFI -> getStackPtrOffsetReg ( ) , RegState :: Implicit ) ; if ( RI . spillSGPRToVGPR ( ) ) FrameInfo . setStackID ( FrameIndex , TargetStackID :: SGPRSpill ) ; if ( ST . hasScalarStores ( ) ) { Spill . addReg ( AMDGPU :: M0 , RegState :: ImplicitDefine | RegState :: Dead ) ; } return ; } unsigned Opcode = RI . hasAGPRs ( RC ) ? getAGPRSpillSaveOpcode ( SpillSize ) : getVGPRSpillSaveOpcode ( SpillSize ) ; MFI -> setHasSpilledVGPRs ( ) ; auto MIB = BuildMI ( MBB , MI , DL , get ( Opcode ) ) ; if ( RI . hasAGPRs ( RC ) ) { MachineRegisterInfo & MRI = MF -> getRegInfo ( ) ; unsigned Tmp = MRI . createVirtualRegister ( & AMDGPU :: VGPR_32RegClass ) ; MIB . addReg ( Tmp , RegState :: Define ) ; } MIB . addReg ( SrcReg , getKillRegState ( isKill ) ) . addFrameIndex ( FrameIndex ) . addReg ( MFI -> getScratchRSrcReg ( ) ) . addReg ( MFI -> getStackPtrOffsetReg ( ) ) . addImm ( 0 ) . addMemOperand ( MMO ) ; } </s>

Store the specified register of the given register class to the specified stack frame index .


<s> bool requiresRegisterScavenging ( const MachineFunction & MF ) const override { return true ; } </s>

Returns true if the target requires ( and can make use of ) the register scavenger .


<s> bool pru_return_in_memory ( const_tree type , const_tree fntype ATTRIBUTE_UNUSED ) { bool in_memory = ( ! pru_arg_in_reg_bysize ( int_size_in_bytes ( type ) ) || int_size_in_bytes ( type ) == - 1 ) ; return in_memory ; } </s>


<s> bool X86TTI :: isLegalMaskedStore ( Type * DataType , int Consecutive ) const { return isLegalMaskedLoad ( DataType , Consecutive ) ; } </s>

Return true if the target supports masked store .


<s> rtx rs6000_adjust_vec_address ( rtx scalar_reg , rtx mem , rtx element , rtx base_tmp , machine_mode scalar_mode ) { unsigned scalar_size = GET_MODE_SIZE ( scalar_mode ) ; rtx addr = XEXP ( mem , 0 ) ; rtx new_addr ; gcc_assert ( ! reg_mentioned_p ( base_tmp , addr ) ) ; gcc_assert ( ! reg_mentioned_p ( base_tmp , element ) ) ; gcc_assert ( GET_RTX_CLASS ( GET_CODE ( addr ) ) != RTX_AUTOINC ) ; rtx element_offset = get_vector_offset ( mem , element , base_tmp , scalar_size ) ; if ( element_offset == const0_rtx ) new_addr = addr ; else if ( REG_P ( addr ) || SUBREG_P ( addr ) ) new_addr = gen_rtx_PLUS ( Pmode , addr , element_offset ) ; else if ( pcrel_local_address ( addr , Pmode ) && CONST_INT_P ( element_offset ) ) new_addr = adjust_vec_address_pcrel ( addr , element_offset , base_tmp ) ; else if ( GET_CODE ( addr ) == PLUS ) { rtx op0 = XEXP ( addr , 0 ) ; rtx op1 = XEXP ( addr , 1 ) ; gcc_assert ( REG_P ( op0 ) || SUBREG_P ( op0 ) ) ; if ( CONST_INT_P ( op1 ) && CONST_INT_P ( element_offset ) ) { gcc_assert ( reg_or_subregno ( op0 ) != 0 ) ; HOST_WIDE_INT offset = INTVAL ( op1 ) + INTVAL ( element_offset ) ; rtx offset_rtx = GEN_INT ( offset ) ; new_addr = gen_rtx_PLUS ( Pmode , op0 , offset_rtx ) ; } else { emit_insn ( gen_rtx_SET ( base_tmp , gen_rtx_PLUS ( Pmode , op0 , op1 ) ) ) ; new_addr = gen_rtx_PLUS ( Pmode , base_tmp , element_offset ) ; } } else { emit_move_insn ( base_tmp , addr ) ; new_addr = gen_rtx_PLUS ( Pmode , base_tmp , element_offset ) ; } enum insn_form iform = address_to_insn_form ( new_addr , scalar_mode , reg_to_non_prefixed ( scalar_reg , scalar_mode ) ) ; if ( iform == INSN_FORM_BAD ) { emit_move_insn ( base_tmp , new_addr ) ; new_addr = base_tmp ; } return change_address ( mem , scalar_mode , new_addr ) ; } </s>

Adjust a memory address ( MEM ) of a vector type to point to a scalar field within the vector ( ELEMENT ) with a mode ( SCALAR_MODE ) . Use a base register temporary ( BASE_TMP ) to fixup the address . Return the new memory address that is valid for reads or writes to a given register ( SCALAR_REG ) . This function is expected to be called after reload is completed when we are splitting insns . The temporary BASE_TMP might be set multiple times with this code .


"Unsupported asm expression. Only absolute address "

getMachineOpValue - Return binary encoding of operand .


<s> static rtx arm_gen_load_multiple_1 ( int count , int * regs , rtx * mems , rtx basereg , HOST_WIDE_INT wback_offset ) { int i = 0 , j ; rtx result ; if ( ! multiple_operation_profitable_p ( false , count , 0 ) ) { rtx seq ; start_sequence ( ) ; for ( i = 0 ; i < count ; i ++ ) emit_move_insn ( gen_rtx_REG ( SImode , regs [ i ] ) , mems [ i ] ) ; if ( wback_offset != 0 ) emit_move_insn ( basereg , plus_constant ( Pmode , basereg , wback_offset ) ) ; seq = get_insns ( ) ; end_sequence ( ) ; return seq ; } result = gen_rtx_PARALLEL ( VOIDmode , rtvec_alloc ( count + ( wback_offset != 0 ? 1 : 0 ) ) ) ; if ( wback_offset != 0 ) { XVECEXP ( result , 0 , 0 ) = gen_rtx_SET ( basereg , plus_constant ( Pmode , basereg , wback_offset ) ) ; i = 1 ; count ++ ; } for ( j = 0 ; i < count ; i ++ , j ++ ) XVECEXP ( result , 0 , i ) = gen_rtx_SET ( gen_rtx_REG ( SImode , regs [ j ] ) , mems [ j ] ) ; return result ; } </s>

Generate a load-multiple instruction . COUNT is the number of loads in the instruction ; REGS and MEMS are arrays containing the operands . BASEREG is the base register to be used in addressing the memory operands . WBACK_OFFSET is nonzero if the instruction should update the base register .


<s> bool X86AsmPrinter :: PrintAsmMemoryOperand ( const MachineInstr * MI , unsigned OpNo , const char * ExtraCode , raw_ostream & O ) { if ( ExtraCode && ExtraCode [ 0 ] ) { if ( ExtraCode [ 1 ] != 0 ) return true ; switch ( ExtraCode [ 0 ] ) { default : return true ; case 'b' : case 'h' : case 'w' : case 'k' : case 'q' : break ; case 'H' : if ( MI -> getInlineAsmDialect ( ) == InlineAsm :: AD_Intel ) { return true ; } else { PrintMemReference ( MI , OpNo , O , "H" ) ; } return false ; case 'P' : if ( MI -> getInlineAsmDialect ( ) == InlineAsm :: AD_Intel ) { PrintIntelMemReference ( MI , OpNo , O , "disp-only" ) ; } else { PrintMemReference ( MI , OpNo , O , "disp-only" ) ; } return false ; } } if ( MI -> getInlineAsmDialect ( ) == InlineAsm :: AD_Intel ) { PrintIntelMemReference ( MI , OpNo , O , nullptr ) ; } else { PrintMemReference ( MI , OpNo , O , nullptr ) ; } return false ; } </s>

Print the specified operand of MI , an INLINEASM instruction , using the specified assembler variant as an address .


<s> static tree ia64_builtin_decl ( unsigned code , bool initialize_p ATTRIBUTE_UNUSED ) { if ( code >= IA64_BUILTIN_max ) return error_mark_node ; return ia64_builtins [ code ] ; } </s>


<s>
const
char
*
getPassName
(
)
const
override
{
return
"WebAssembly Store Results"
;
}
</s>

getPassName - Return a nice clean name for a pass .


"insertBranch must not be told to insert a fallthrough"

"SNES branch conditions have one component!"

"Unconditional branch with multiple successors!"

Insert branch code into the end of the specified MachineBasicBlock .


<s> void aarch64_emit_approx_rsqrt ( rtx dst , rtx src ) { machine_mode mode = GET_MODE ( src ) ; gcc_assert ( mode == SFmode || mode == V2SFmode || mode == V4SFmode || mode == DFmode || mode == V2DFmode ) ; rtx xsrc = gen_reg_rtx ( mode ) ; emit_move_insn ( xsrc , src ) ; rtx x0 = gen_reg_rtx ( mode ) ; emit_insn ( ( * get_rsqrte_type ( mode ) ) ( x0 , xsrc ) ) ; bool double_mode = ( mode == DFmode || mode == V2DFmode ) ; int iterations = double_mode ? 3 : 2 ; if ( flag_mrecip_low_precision_sqrt ) iterations -- ; for ( int i = 0 ; i < iterations ; ++ i ) { rtx x1 = gen_reg_rtx ( mode ) ; rtx x2 = gen_reg_rtx ( mode ) ; rtx x3 = gen_reg_rtx ( mode ) ; emit_set_insn ( x2 , gen_rtx_MULT ( mode , x0 , x0 ) ) ; emit_insn ( ( * get_rsqrts_type ( mode ) ) ( x3 , xsrc , x2 ) ) ; emit_set_insn ( x1 , gen_rtx_MULT ( mode , x0 , x3 ) ) ; x0 = x1 ; } emit_move_insn ( dst , x0 ) ; } </s>

Emit instruction sequence to compute the reciprocal square root using the Newton-Raphson series . Iterate over the series twice for SF and thrice for DF .


<s> void R600SchedStrategy :: initialize ( ScheduleDAGMI * dag ) { DAG = dag ; TII = static_cast < const R600InstrInfo * > ( DAG -> TII ) ; TRI = static_cast < const R600RegisterInfo * > ( DAG -> TRI ) ; MRI = & DAG -> MRI ; Available [ IDAlu ] -> clear ( ) ; Available [ IDFetch ] -> clear ( ) ; Available [ IDOther ] -> clear ( ) ; CurInstKind = IDOther ; CurEmitted = 0 ; OccupedSlotsMask = 15 ; InstKindLimit [ IDAlu ] = 120 ; const AMDGPUSubtarget & ST = DAG -> TM . getSubtarget < AMDGPUSubtarget > ( ) ; if ( ST . device ( ) -> getGeneration ( ) <= AMDGPUDeviceInfo :: HD5XXX ) { InstKindLimit [ IDFetch ] = 7 ; } else { InstKindLimit [ IDFetch ] = 15 ; } } </s>

Initialize the strategy after building the DAG for a new region .


<s> bool SPIRVTargetLowering :: getTgtMemIntrinsic ( IntrinsicInfo & Info , const CallInst & I , MachineFunction & MF , unsigned Intrinsic ) const { unsigned AlignIdx = 3 ; switch ( Intrinsic ) { case Intrinsic :: spv_load : AlignIdx = 2 ; LLVM_FALLTHROUGH ; case Intrinsic :: spv_store : { if ( I . getNumOperands ( ) >= AlignIdx + 1 ) { auto * AlignOp = cast < ConstantInt > ( I . getOperand ( AlignIdx ) ) ; Info . align = Align ( AlignOp -> getZExtValue ( ) ) ; } Info . flags = static_cast < MachineMemOperand :: Flags > ( cast < ConstantInt > ( I . getOperand ( AlignIdx - 1 ) ) -> getZExtValue ( ) ) ; Info . memVT = MVT :: i64 ; return true ; break ; } default : break ; } return false ; } </s>

Given an intrinsic , checks if on the target the intrinsic will need to map to a MemIntrinsicNode ( touches memory ) .


<s> static void emitSPUpdate ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator & MBBI , unsigned StackPtr , int64_t NumBytes , bool Is64Bit , const TargetInstrInfo & TII , const TargetRegisterInfo & TRI ) { bool isSub = NumBytes < 0 ; uint64_t Offset = isSub ? - NumBytes : NumBytes ; unsigned Opc = isSub ? getSUBriOpcode ( Is64Bit , Offset ) : getADDriOpcode ( Is64Bit , Offset ) ; uint64_t Chunk = ( 1LL << 31 ) - 1 ; DebugLoc DL = MBB . findDebugLoc ( MBBI ) ; while ( Offset ) { uint64_t ThisVal = ( Offset > Chunk ) ? Chunk : Offset ; if ( ThisVal == ( Is64Bit ? 8 : 4 ) ) { unsigned Reg = isSub ? ( unsigned ) ( Is64Bit ? X86 :: RAX : X86 :: EAX ) : findDeadCallerSavedReg ( MBB , MBBI , TRI , Is64Bit ) ; if ( Reg ) { Opc = isSub ? ( Is64Bit ? X86 :: PUSH64r : X86 :: PUSH32r ) : ( Is64Bit ? X86 :: POP64r : X86 :: POP32r ) ; MachineInstr * MI = BuildMI ( MBB , MBBI , DL , TII . get ( Opc ) ) . addReg ( Reg , getDefRegState ( ! isSub ) | getUndefRegState ( isSub ) ) ; if ( isSub ) MI -> setFlag ( MachineInstr :: FrameSetup ) ; Offset -= ThisVal ; continue ; } } MachineInstr * MI = BuildMI ( MBB , MBBI , DL , TII . get ( Opc ) , StackPtr ) . addReg ( StackPtr ) . addImm ( ThisVal ) ; if ( isSub ) MI -> setFlag ( MachineInstr :: FrameSetup ) ; MI -> getOperand ( 3 ) . setIsDead ( ) ; Offset -= ThisVal ; } } </s>

Emit a series of instructions to increment / decrement the stack pointer by a constant value .


<s> int nds32_alloc_relax_group_id ( ) { return relax_group_id ++ ; } </s>

Group the following pattern as relax candidates : 1. sethi $ ra , hi20 ( sym ) ori $ ra , $ ra , lo12 ( sym ) == > addi.gp $ ra , sym 2. sethi $ ra , hi20 ( sym ) lwi $ rb , [ $ ra + lo12 ( sym ) ] == > lwi.gp $ rb , [ ( sym ) ] 3. sethi $ ra , hi20 ( sym ) ori $ ra , $ ra , lo12 ( sym ) lwi $ rb , [ $ ra ] swi $ rc , [ $ ra ] == > lwi37 $ rb , [ ( sym ) ] swi37 $ rc , [ ( sym ) ]


<s> bpf_small_register_classes_for_mode_p static bool bpf_is_valid_preserve_field_info_arg ( tree expr ) { switch ( TREE_CODE ( expr ) ) { case COMPONENT_REF : case BIT_FIELD_REF : case ARRAY_REF : case ARRAY_RANGE_REF : return true ; case NOP_EXPR : return bpf_is_valid_preserve_field_info_arg ( TREE_OPERAND ( expr , 0 ) ) ; case ADDR_EXPR : return ( TREE_CODE ( TREE_TYPE ( TREE_OPERAND ( expr , 0 ) ) ) == ARRAY_TYPE ) ; default : return false ; } } </s>

Return whether EXPR is a valid first argument for a call to __builtin_preserve_field_info .


<s> bool MipsLongBranch :: runOnMachineFunction ( MachineFunction & F ) { const MipsInstrInfo * TII = static_cast < const MipsInstrInfo * > ( TM . getInstrInfo ( ) ) ; if ( TM . getSubtarget < MipsSubtarget > ( ) . inMips16Mode ( ) ) return false ; if ( ( TM . getRelocationModel ( ) == Reloc :: PIC_ ) && TM . getSubtarget < MipsSubtarget > ( ) . isABI_O32 ( ) && F . getInfo < MipsFunctionInfo > ( ) -> globalBaseRegSet ( ) ) emitGPDisp ( F , TII ) ; if ( SkipLongBranch ) return true ; MF = & F ; initMBBInfo ( ) ; SmallVectorImpl < MBBInfo > :: iterator I , E = MBBInfos . end ( ) ; bool EverMadeChange = false , MadeChange = true ; while ( MadeChange ) { MadeChange = false ; for ( I = MBBInfos . begin ( ) ; I != E ; ++ I ) { if ( ! I -> Br || I -> HasLongBranch ) continue ; int ShVal = TM . getSubtarget < MipsSubtarget > ( ) . inMicroMipsMode ( ) ? 2 : 4 ; int64_t Offset = computeOffset ( I -> Br ) / ShVal ; if ( TM . getSubtarget < MipsSubtarget > ( ) . isTargetNaCl ( ) ) { Offset *= 2 ; } if ( ! ForceLongBranch && isInt < 16 > ( Offset ) ) continue ; I -> HasLongBranch = true ; I -> Size += LongBranchSeqSize * 4 ; ++ LongBranches ; EverMadeChange = MadeChange = true ; } } if ( ! EverMadeChange ) return true ; if ( TM . getRelocationModel ( ) == Reloc :: PIC_ ) { uint64_t Address = 0 ; for ( I = MBBInfos . begin ( ) ; I != E ; Address += I -> Size , ++ I ) I -> Address = Address ; } for ( I = MBBInfos . begin ( ) ; I != E ; ++ I ) if ( I -> HasLongBranch ) expandToLongBranch ( * I ) ; MF -> RenumberBlocks ( ) ; return true ; } </s>

runOnMachineFunction - Emit the function body .


<s>
static
const
char
*
ia64_invalid_conversion
(
const_tree
fromtype
,
const_tree
totype
)
{
if
(
TYPE_MODE
(
fromtype
)
==
RFmode
&&
TYPE_MODE
(
totype
)
!=
RFmode
&&
TYPE_MODE
(
totype
)
!=
VOIDmode
)
return
N_
(
"invalid conversion from %<__fpreg%>"
)
;
if
(
TYPE_MODE
(
totype
)
==
RFmode
&&
TYPE_MODE
(
fromtype
)
!=
RFmode
)
return
N_
(
"invalid conversion to %<__fpreg%>"
)
;
return
;
}
</s>

Return the diagnostic message string if conversion from FROMTYPE to TOTYPE is not allowed , NULL otherwise .

ia64
"invalid conversion from %<__fpreg%>"
"invalid conversion to %<__fpreg%>"


<s> static bool arc_can_eliminate ( const int from ATTRIBUTE_UNUSED , const int to ) { return to == FRAME_POINTER_REGNUM || ! arc_frame_pointer_required ( ) ; } </s>

Given FROM and TO register numbers , say whether this elimination is allowed . Frame pointer elimination is automatically handled . All eliminations are permissible . If we need a frame pointer , we must eliminate ARG_POINTER_REGNUM into FRAME_POINTER_REGNUM and not into STACK_POINTER_REGNUM .


<s> void MipsTargetELFStreamer :: emitLabel ( MCSymbol * Symbol ) { if ( ! isMicroMipsEnabled ( ) ) return ; MCSymbolData & Data = getStreamer ( ) . getOrCreateSymbolData ( Symbol ) ; uint8_t Type = MCELF :: GetType ( Data ) ; if ( Type != ELF :: STT_FUNC ) return ; MCELF :: setOther ( Data , ELF :: STO_MIPS_MICROMIPS >> 2 ) ; } </s>

Emit a label for Symbol into the current section .


<s> int sh_can_redirect_branch ( rtx branch1 , rtx branch2 ) { if ( flag_expensive_optimizations && simplejump_p ( branch2 ) ) { rtx dest = XEXP ( SET_SRC ( single_set ( branch2 ) ) , 0 ) ; rtx insn ; int distance ; for ( distance = 0 , insn = NEXT_INSN ( branch1 ) ; insn && distance < 256 ; insn = PREV_INSN ( insn ) ) { if ( insn == dest ) return 1 ; else distance += get_attr_length ( insn ) ; } for ( distance = 0 , insn = NEXT_INSN ( branch1 ) ; insn && distance < 256 ; insn = NEXT_INSN ( insn ) ) { if ( insn == dest ) return 1 ; else distance += get_attr_length ( insn ) ; } } return 0 ; } </s>

Return true if it 's possible to redirect BRANCH1 to the destination of an unconditional jump BRANCH2 . We only want to do this if the resulting branch will have a short displacement .


<s> static void pdp11_conditional_register_usage ( void ) { int i ; HARD_REG_SET x ; if ( ! TARGET_FPU ) { x = reg_class_contents [ FPU_REGS ] ; for ( i = 0 ; i < FIRST_PSEUDO_REGISTER ; i ++ ) if ( TEST_HARD_REG_BIT ( x , i ) ) fixed_regs [ i ] = call_used_regs [ i ] = 1 ; } if ( TARGET_AC0 ) call_used_regs [ AC0_REGNUM ] = 1 ; if ( TARGET_UNIX_ASM ) { reg_names [ 8 ] = "fr0" ; reg_names [ 9 ] = "fr1" ; reg_names [ 10 ] = "fr2" ; reg_names [ 11 ] = "fr3" ; reg_names [ 12 ] = "fr4" ; reg_names [ 13 ] = "fr5" ; } } </s>

Make sure everything 's fine if we * do n't * have an FPU . This assumes that putting a register in fixed_regs will keep the compiler 's mitts completely off it . We do n't bother to zero it out of register classes . Also fix incompatible register naming with the UNIX assembler .


<s> static void vax_init_libfuncs ( void ) { if ( TARGET_BSD_DIVMOD ) { set_optab_libfunc ( udiv_optab , SImode , TARGET_ELF ? "*__udiv" : "*udiv" ) ; set_optab_libfunc ( umod_optab , SImode , TARGET_ELF ? "*__urem" : "*urem" ) ; } } </s>

We can use the BSD C library routines for the libgcc calls that are still generated , since that 's what they boil down to anyways . When ELF , avoid the user 's namespace .


<s> int mcore_expand_insv ( rtx operands [ ] ) { int width = INTVAL ( operands [ 1 ] ) ; int posn = INTVAL ( operands [ 2 ] ) ; int mask ; rtx mreg , sreg , ereg ; if ( width == 1 && GET_CODE ( operands [ 3 ] ) == CONST_INT ) { if ( ( INTVAL ( operands [ 3 ] ) & 1 ) == 0 ) { mask = ~ ( 1 << posn ) ; emit_insn ( gen_rtx_SET ( SImode , operands [ 0 ] , gen_rtx_AND ( SImode , operands [ 0 ] , GEN_INT ( mask ) ) ) ) ; } else { mask = 1 << posn ; emit_insn ( gen_rtx_SET ( SImode , operands [ 0 ] , gen_rtx_IOR ( SImode , operands [ 0 ] , GEN_INT ( mask ) ) ) ) ; } return 1 ; } if ( ! TARGET_W_FIELD ) return 0 ; if ( width == 8 && posn % 8 == 0 ) return 0 ; if ( width == 16 && posn % 16 == 0 ) return 0 ; if ( GET_CODE ( operands [ 3 ] ) == CONST_INT && INTVAL ( operands [ 3 ] ) == ( ( 1 << width ) - 1 ) ) { mreg = force_reg ( SImode , GEN_INT ( INTVAL ( operands [ 3 ] ) << posn ) ) ; emit_insn ( gen_rtx_SET ( SImode , operands [ 0 ] , gen_rtx_IOR ( SImode , operands [ 0 ] , mreg ) ) ) ; return 1 ; } mreg = force_reg ( SImode , GEN_INT ( ~ ( ( ( 1 << width ) - 1 ) << posn ) ) ) ; emit_insn ( gen_rtx_SET ( SImode , operands [ 0 ] , gen_rtx_AND ( SImode , operands [ 0 ] , mreg ) ) ) ; if ( GET_CODE ( operands [ 3 ] ) == CONST_INT && INTVAL ( operands [ 3 ] ) == 0 ) return 1 ; sreg = copy_to_mode_reg ( SImode , operands [ 3 ] ) ; if ( width + posn != ( int ) GET_MODE_SIZE ( SImode ) ) { ereg = force_reg ( SImode , GEN_INT ( ( 1 << width ) - 1 ) ) ; emit_insn ( gen_rtx_SET ( SImode , sreg , gen_rtx_AND ( SImode , sreg , ereg ) ) ) ; } if ( posn != 0 ) emit_insn ( gen_rtx_SET ( SImode , sreg , gen_rtx_ASHIFT ( SImode , sreg , GEN_INT ( posn ) ) ) ) ; emit_insn ( gen_rtx_SET ( SImode , operands [ 0 ] , gen_rtx_IOR ( SImode , operands [ 0 ] , sreg ) ) ) ; return 1 ; } </s>


<s> static bool expand_vec_perm_pshuflw_pshufhw ( struct expand_vec_perm_d * d ) { unsigned char perm2 [ MAX_VECT_LEN ] ; unsigned i ; bool ok ; if ( d -> vmode != V8HImode || ! d -> one_operand_p ) return false ; for ( i = 0 ; i < 4 ; ++ i ) if ( d -> perm [ i ] >= 4 ) return false ; for ( i = 4 ; i < 8 ; ++ i ) if ( d -> perm [ i ] < 4 ) return false ; if ( d -> testing_p ) return true ; memcpy ( perm2 , d -> perm , 4 ) ; for ( i = 4 ; i < 8 ; ++ i ) perm2 [ i ] = i ; ok = expand_vselect ( d -> target , d -> op0 , perm2 , 8 , d -> testing_p ) ; gcc_assert ( ok ) ; memcpy ( perm2 + 4 , d -> perm + 4 , 4 ) ; for ( i = 0 ; i < 4 ; ++ i ) perm2 [ i ] = i ; ok = expand_vselect ( d -> target , d -> target , perm2 , 8 , d -> testing_p ) ; gcc_assert ( ok ) ; return true ; } </s>

A subroutine of ix86_expand_vec_perm_builtin_1 . Try to implement D in terms of a pair of pshuflw + pshufhw instructions .


<s> bool RISCVAsmParser :: processInstruction ( MCInst & Inst , SMLoc IDLoc , MCStreamer & Out ) { Inst . setLoc ( IDLoc ) ; if ( Inst . getOpcode ( ) == RISCV :: PseudoLI ) { auto Reg = Inst . getOperand ( 0 ) . getReg ( ) ; int64_t Imm = Inst . getOperand ( 1 ) . getImm ( ) ; if ( ! isRV64 ( ) ) Imm = SignExtend64 < 32 > ( Imm ) ; emitLoadImm ( Reg , Imm , Out ) ; return false ; } emitToStreamer ( Out , Inst ) ; return false ; } </s>

Process a single instruction and collect debug info anchors .