<s> static section * mips_select_rtx_section ( machine_mode mode , rtx x , unsigned HOST_WIDE_INT align ) { if ( mips_rtx_constant_in_small_data_p ( mode ) ) return get_named_section ( NULL , ".sdata" , 0 ) ; return default_elf_select_rtx_section ( mode , x , align ) ; } </s>

Choose the section to use for the constant rtx expression X that has mode MODE .


<s> enum machine_mode visium_select_cc_mode ( enum rtx_code code , rtx op0 , rtx op1 ) { if ( GET_MODE_CLASS ( GET_MODE ( op0 ) ) == MODE_FLOAT ) { switch ( code ) { case EQ : case NE : case ORDERED : case UNORDERED : case UNLT : case UNLE : case UNGT : case UNGE : return CCFPmode ; case LT : case LE : case GT : case GE : return CCFPEmode ; case UNEQ : case LTGT : default : gcc_unreachable ( ) ; } } if ( op1 != const0_rtx ) return CCmode ; switch ( GET_CODE ( op0 ) ) { case PLUS : case MINUS : case NEG : case ASHIFT : case LTU : case LT : return CC_NOOVmode ; case ZERO_EXTRACT : return CC_BTSTmode ; case CONST_INT : gcc_assert ( op0 == constm1_rtx ) ; case REG : case AND : case IOR : case XOR : case NOT : case ASHIFTRT : case LSHIFTRT : case TRUNCATE : case SIGN_EXTEND : return CCmode ; default : gcc_unreachable ( ) ; } } </s>

Given a comparison code ( EQ , NE , etc . ) and the operands of a COMPARE , return the mode to be used for the comparison .


"Instr doesn't have FrameIndex operand!"

This method must be overriden to eliminate abstract frame indices from instructions which may use them .


<s> const std :: string getAsStr ( ) const override { std :: string Str ; raw_string_ostream OS ( Str ) ; OS << "AMDFlatWorkGroupSize[" ; OS << getAssumed ( ) . getLower ( ) << ',' << getAssumed ( ) . getUpper ( ) - 1 ; OS << ']' ; return OS . str ( ) ; } </s>

See AbstractState : :getAsStr ( Attributor ) .


<s> bool riscv_split_symbol ( rtx temp , rtx addr , machine_mode mode , rtx * low_out ) { enum riscv_symbol_type symbol_type ; if ( ( GET_CODE ( addr ) == HIGH && mode == MAX_MACHINE_MODE ) || ! riscv_symbolic_constant_p ( addr , & symbol_type ) || riscv_symbol_insns ( symbol_type ) == 0 || ! riscv_split_symbol_type ( symbol_type ) ) return false ; if ( low_out ) switch ( symbol_type ) { case SYMBOL_ABSOLUTE : { rtx high = gen_rtx_HIGH ( Pmode , copy_rtx ( addr ) ) ; high = riscv_force_temporary ( temp , high ) ; * low_out = gen_rtx_LO_SUM ( Pmode , high , addr ) ; } break ; case SYMBOL_PCREL : { static unsigned seqno ; char buf [ 32 ] ; rtx label ; ssize_t bytes = snprintf ( buf , sizeof ( buf ) , ".LA%u" , seqno ) ; gcc_assert ( ( size_t ) bytes < sizeof ( buf ) ) ; label = gen_rtx_SYMBOL_REF ( Pmode , ggc_strdup ( buf ) ) ; SYMBOL_REF_FLAGS ( label ) |= SYMBOL_FLAG_LOCAL ; if ( ! nonzero_address_p ( addr ) ) SYMBOL_REF_WEAK ( label ) = 1 ; if ( temp == NULL ) temp = gen_reg_rtx ( Pmode ) ; if ( Pmode == DImode ) emit_insn ( gen_auipcdi ( temp , copy_rtx ( addr ) , GEN_INT ( seqno ) ) ) ; else emit_insn ( gen_auipcsi ( temp , copy_rtx ( addr ) , GEN_INT ( seqno ) ) ) ; * low_out = gen_rtx_LO_SUM ( Pmode , temp , label ) ; seqno ++ ; } break ; default : gcc_unreachable ( ) ; } return true ; } </s>

If MODE is MAX_MACHINE_MODE , ADDR appears as a move operand , otherwise it appears in a MEM of that mode . Return true if ADDR is a legitimate constant in that context and can be split into high and low parts . If so , and if LOW_OUT is nonnull , emit the high part and store the low part in * LOW_OUT . Leave * LOW_OUT unchanged otherwise . TEMP is as for riscv_force_temporary and is used to load the high part into a register . When MODE is MAX_MACHINE_MODE , the low part is guaranteed to be a legitimize SET_SRC for an .md pattern , otherwise the low part is guaranteed to be a legitimate address for mode MODE .


<s> void ARMPassConfig :: addPreSched2 ( ) { if ( getOptLevel ( ) != CodeGenOpt :: None ) { if ( EnableARMLoadStoreOpt ) addPass ( createARMLoadStoreOptimizationPass ( ) ) ; addPass ( new ARMExecutionDomainFix ( ) ) ; addPass ( createBreakFalseDeps ( ) ) ; } addPass ( createARMExpandPseudoPass ( ) ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) { addPass ( createThumb2SizeReductionPass ( [ this ] ( const Function & F ) { return this -> TM -> getSubtarget < ARMSubtarget > ( F ) . hasMinSize ( ) || this -> TM -> getSubtarget < ARMSubtarget > ( F ) . restrictIT ( ) ; } ) ) ; addPass ( createIfConverter ( [ ] ( const MachineFunction & MF ) { return ! MF . getSubtarget < ARMSubtarget > ( ) . isThumb1Only ( ) ; } ) ) ; } addPass ( createMVEVPTBlockPass ( ) ) ; addPass ( createThumb2ITBlockPass ( ) ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) { addPass ( & PostMachineSchedulerID ) ; addPass ( & PostRASchedulerID ) ; } } </s>

This method may be implemented by targets that want to run passes after prolog-epilog insertion and before the second instruction scheduling pass .


<s> const Nios2RegisterInfo & Nios2InstrInfo :: getRegisterInfo ( ) const { return RI ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s> static bool classof ( const RISCVMCExpr * ) { return true ; } </s>

Methods for support type inquiry through isa , cast , and dyn_cast :


<s>
const
char
*
cris_op_str
(
rtx
x
)
{
cris_output_insn_is_bound
=
0
;
switch
(
GET_CODE
(
x
)
)
{
case
PLUS
:
return
"add"
;
break
;
case
MINUS
:
return
"sub"
;
break
;
case
MULT
:
internal_error
(
"MULT case in cris_op_str"
)
;
break
;
case
DIV
:
return
"div"
;
break
;
case
AND
:
return
"and"
;
break
;
case
IOR
:
return
"or"
;
break
;
case
XOR
:
return
"xor"
;
break
;
case
NOT
:
return
"not"
;
break
;
case
ASHIFT
:
return
"lsl"
;
break
;
case
LSHIFTRT
:
return
"lsr"
;
break
;
case
ASHIFTRT
:
return
"asr"
;
break
;
case
UMIN
:
cris_output_insn_is_bound
=
1
;
return
"bound"
;
break
;
default
:
return
"Unknown operator"
;
break
;
}
}
</s>

Given an rtx , return the text string corresponding to the CODE of X . Intended for use in the assembly language output section of a define_insn .

cris
0
"add"
"sub"
"MULT case in cris_op_str"
"div"
"and"
"or"
"xor"
"not"
"lsl"
"lsr"
"asr"
1
"bound"
"Unknown operator"


<s> unsigned char X86Subtarget :: classifyGlobalFunctionReference ( const GlobalValue * GV , const Module & M ) const { if ( TM . shouldAssumeDSOLocal ( M , GV ) ) return X86II :: MO_NO_FLAG ; if ( isTargetCOFF ( ) ) { if ( ! GV ) return X86II :: MO_NO_FLAG ; if ( GV -> hasDLLImportStorageClass ( ) ) return X86II :: MO_DLLIMPORT ; return X86II :: MO_COFFSTUB ; } const Function * F = dyn_cast_or_null < Function > ( GV ) ; if ( isTargetELF ( ) ) { if ( is64Bit ( ) && F && ( CallingConv :: X86_RegCall == F -> getCallingConv ( ) ) ) return X86II :: MO_GOTPCREL ; if ( ( ( F && F -> hasFnAttribute ( Attribute :: NonLazyBind ) ) || ( ! F && M . getRtLibUseGOT ( ) ) ) && is64Bit ( ) ) return X86II :: MO_GOTPCREL ; if ( ! is64Bit ( ) && ! GV && TM . getRelocationModel ( ) == Reloc :: Static ) return X86II :: MO_NO_FLAG ; return X86II :: MO_PLT ; } if ( is64Bit ( ) ) { if ( F && F -> hasFnAttribute ( Attribute :: NonLazyBind ) ) return X86II :: MO_GOTPCREL ; return X86II :: MO_NO_FLAG ; } return X86II :: MO_NO_FLAG ; } </s>

Classify a global function reference for the current subtarget .


<s> static rtx rs6000_savres_routine_sym ( rs6000_stack_t * info , int sel ) { int regno = ( ( sel & SAVRES_REG ) == SAVRES_GPR ? info -> first_gp_reg_save : ( sel & SAVRES_REG ) == SAVRES_FPR ? info -> first_fp_reg_save - 32 : ( sel & SAVRES_REG ) == SAVRES_VR ? info -> first_altivec_reg_save - FIRST_ALTIVEC_REGNO : - 1 ) ; rtx sym ; int select = sel ; if ( TARGET_SPE_ABI && ( sel & SAVRES_REG ) == SAVRES_GPR && info -> spe_64bit_regs_used ) select ^= SAVRES_FPR ^ SAVRES_GPR ; gcc_assert ( FIRST_SAVRES_REGISTER <= regno && regno <= LAST_SAVRES_REGISTER && select >= 0 && select <= 12 ) ; sym = savres_routine_syms [ regno - FIRST_SAVRES_REGISTER ] [ select ] ; if ( sym == NULL ) { char * name ; name = rs6000_savres_routine_name ( info , regno , sel ) ; sym = savres_routine_syms [ regno - FIRST_SAVRES_REGISTER ] [ select ] = gen_rtx_SYMBOL_REF ( Pmode , ggc_strdup ( name ) ) ; SYMBOL_REF_FLAGS ( sym ) |= SYMBOL_FLAG_FUNCTION ; } return sym ; } </s>

Return an RTL SYMBOL_REF for an out-of-line register save/restore routine . We are saving/restoring GPRs if GPR is true .


"AMDGPUMCInstLower::lower - Pseudo instruction doesn't have "


Execute an already-loaded kernel on the device .


<s> int64_t TeakRegisterInfo :: getFrameIndexInstrOffset ( const MachineInstr * MI , int Idx ) const { switch ( MI -> getOpcode ( ) ) { default : return 0 ; case Teak :: STORE_REG_TO_STACK_PSEUDO_16 : case Teak :: STORE_REG_TO_STACK_PSEUDO_TRUNC16 : case Teak :: STORE_REG_TO_STACK_PSEUDO_32 : case Teak :: LOAD_REG_FROM_STACK_PSEUDO_16 : case Teak :: LOAD_REG_FROM_STACK_PSEUDO_16_SEXT40 : case Teak :: LOAD_REG_FROM_STACK_PSEUDO_16_ZEXT40 : case Teak :: LOAD_REG_FROM_STACK_PSEUDO_32_SEXT40 : return MI -> getOperand ( Idx + 1 ) . getImm ( ) ; } } </s>

Get the offset from the referenced frame index in the instruction , if there is one .


"%qE attribute only applies to functions"


<s>
bool
AVRAsmParser
::
MatchAndEmitInstruction
(
SMLoc
Loc
,
unsigned
&
Opcode
,
OperandVector
&
Operands
,
MCStreamer
&
Out
,
uint64_t
&
ErrorInfo
,
bool
MatchingInlineAsm
)
{
MCInst
Inst
;
unsigned
MatchResult
=
MatchInstructionImpl
(
Operands
,
Inst
,
ErrorInfo
,
MatchingInlineAsm
)
;
switch
(
MatchResult
)
{
case
Match_Success
:
return
emit
(
Inst
,
Loc
,
Out
)
;
case
Match_MissingFeature
:
return
missingFeature
(
Loc
,
ErrorInfo
)
;
case
Match_InvalidOperand
:
return
invalidOperand
(
Loc
,
Operands
,
ErrorInfo
)
;
case
Match_MnemonicFail
:
return
Error
(
Loc
,
"invalid instruction"
)
;
default
:
return
true
;
}
}
</s>

MatchAndEmitInstruction - Recognize a series of operands of a parsed instruction as an actual MCInst and emit it to the specified MCStreamer .


<s> static void arm_expand_builtin_va_start ( tree valist , rtx nextarg ) { valist = arm_extract_valist_ptr ( valist ) ; std_expand_builtin_va_start ( valist , nextarg ) ; } </s>


<s> static inline bool return_addr_reg_needed_p ( int leaf_function ) { if ( df_regs_ever_live_p ( RETURN_ADDR_REGNUM ) ) return true ; if ( ! leaf_function || crtl -> uses_pic_offset_table || df_regs_ever_live_p ( INCOMING_RETURN_ADDR_REGNUM ) ) return true ; return false ; } </s>

Return whether the return address register ( % i7 ) is needed .


<s> static reg_class_t ix86_preferred_output_reload_class ( rtx x , reg_class_t regclass ) { machine_mode mode = GET_MODE ( x ) ; mode = GET_MODE ( x ) ; if ( TARGET_SSE_MATH && SSE_FLOAT_MODE_P ( mode ) ) return MAYBE_SSE_CLASS_P ( regclass ) ? ALL_SSE_REGS : NO_REGS ; if ( X87_FLOAT_MODE_P ( mode ) ) { if ( regclass == FP_TOP_SSE_REGS ) return FP_TOP_REG ; else if ( regclass == FP_SECOND_SSE_REGS ) return FP_SECOND_REG ; else return FLOAT_CLASS_P ( regclass ) ? regclass : NO_REGS ; } return regclass ; } </s>

Discourage putting floating-point values in SSE registers unless SSE math is being used , and likewise for the 387 registers .


<s> bool SIInstrInfo :: isInlineConstant ( const MachineOperand & MO ) const { if ( MO . isImm ( ) ) return isInlineConstant ( APInt ( 32 , MO . getImm ( ) , true ) ) ; if ( MO . isFPImm ( ) ) { APFloat FpImm = MO . getFPImm ( ) -> getValueAPF ( ) ; return isInlineConstant ( FpImm . bitcastToAPInt ( ) ) ; } return false ; } </s>

returns true if the operand OpIdx in MI is a valid inline immediate .


<s> void CJGInstPrinter :: printRegName ( raw_ostream & O , unsigned RegNo ) const { O << StringRef ( getRegisterName ( RegNo ) ) ; } </s>


<s>
void
pa_asm_output_aligned_bss
(
FILE
*
stream
,
const
char
*
name
,
unsigned
HOST_WIDE_INT
size
,
unsigned
int
align
)
{
bss_section
(
)
;
fprintf
(
stream
,
"\t.align %u\n"
,
align
/
BITS_PER_UNIT
)
;
ASM_OUTPUT_TYPE_DIRECTIVE
(
stream
,
name
,
"object"
)
;
ASM_OUTPUT_SIZE_DIRECTIVE
(
stream
,
name
,
size
)
;
fprintf
(
stream
,
"\t.align %u\n"
,
align
/
BITS_PER_UNIT
)
;
ASM_OUTPUT_LABEL
(
stream
,
name
)
;
fprintf
(
stream
,
"\t.block "
HOST_WIDE_INT_PRINT_UNSIGNED
"\n"
,
size
)
;
}
</s>

This function places uninitialized global data in the bss section . The ASM_OUTPUT_ALIGNED_BSS macro needs to be defined to call this function on the SOM port to prevent uninitialized global data from being placed in the data section .

pa
"\t.align %u\n"
"object"
"\t.align %u\n"
"\t.block "
"\n"


<s> MCELFStreamer & getStreamer ( ) { return static_cast < MCELFStreamer & > ( Streamer ) ; } </s>

Return the output streamer for the assembler .


<s> static unsigned int mips_global_pointer ( void ) { unsigned int regno ; if ( ! TARGET_ABICALLS ) return GLOBAL_POINTER_REGNUM ; if ( ! TARGET_EXPLICIT_RELOCS ) return GLOBAL_POINTER_REGNUM ; if ( current_function_profile ) return GLOBAL_POINTER_REGNUM ; if ( current_function_has_nonlocal_goto ) return GLOBAL_POINTER_REGNUM ; if ( ! regs_ever_live [ GLOBAL_POINTER_REGNUM ] && ! current_function_uses_const_pool && ! mips_function_has_gp_insn ( ) ) return 0 ; if ( TARGET_NEWABI && current_function_is_leaf ) for ( regno = GP_REG_FIRST ; regno <= GP_REG_LAST ; regno ++ ) if ( ! regs_ever_live [ regno ] && call_used_regs [ regno ] && ! fixed_regs [ regno ] && regno != PIC_FUNCTION_ADDR_REGNUM ) return regno ; return GLOBAL_POINTER_REGNUM ; } </s>

Return the register that should be used as the global pointer within this function . Return 0 if the function does n't need a global pointer .


<s> static int arm_effective_regno ( rtx op , bool strict ) { gcc_assert ( REG_P ( op ) ) ; if ( ! strict || REGNO ( op ) < FIRST_PSEUDO_REGISTER || ! reg_renumber || reg_renumber [ REGNO ( op ) ] < 0 ) return REGNO ( op ) ; return reg_renumber [ REGNO ( op ) ] ; } </s>

In non-STRICT mode , return the register number ; in STRICT mode return the hard regno or the replacement if it wo n't be a mem . Otherwise , return the original pseudo number .


<s> static int getMaxValue ( uint64_t TSFlags ) { unsigned isSigned = ( TSFlags >> HexagonII :: ExtentSignedPos ) & HexagonII :: ExtentSignedMask ; unsigned bits = ( TSFlags >> HexagonII :: ExtentBitsPos ) & HexagonII :: ExtentBitsMask ; if ( isSigned ) return ~ ( - 1U << ( bits - 1 ) ) ; return ~ ( - 1U << bits ) ; } </s>

Return the maximal unsigned value possible given these KnownBits .


<s> bool isMem ( ) const override { return Kind == k_Memri ; } </s>


<s> void ARMConstantPoolMBB :: print ( raw_ostream & O ) const { ARMConstantPoolValue :: print ( O ) ; } </s>

print - Print a debug representation of the operand to the given stream .


<s>
bool
HexagonExpandCondsets
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
if
(
skipFunction
(
MF
.
getFunction
(
)
)
)
return
false
;
HII
=
static_cast
<
const
HexagonInstrInfo
*
>
(
MF
.
getSubtarget
(
)
.
getInstrInfo
(
)
)
;
TRI
=
MF
.
getSubtarget
(
)
.
getRegisterInfo
(
)
;
MDT
=
&
getAnalysis
<
MachineDominatorTree
>
(
)
;
LIS
=
&
getAnalysis
<
LiveIntervals
>
(
)
;
MRI
=
&
MF
.
getRegInfo
(
)
;
LLVM_DEBUG
(
LIS
->
print
(
dbgs
(
)
<<
"Before expand-condsets\n"
,
MF
.
getFunction
(
)
.
getParent
(
)
)
)
;
bool
Changed
=
false
;
std
::
set
<
Register
>
CoalUpd
,
PredUpd
;
SmallVector
<
MachineInstr
*
,
16
>
Condsets
;
for
(
auto
&
B
:
MF
)
for
(
auto
&
I
:
B
)
if
(
isCondset
(
I
)
)
Condsets
.
push_back
(
&
I
)
;
Changed
|=
coalesceSegments
(
Condsets
,
CoalUpd
)
;
std
::
set
<
Register
>
KillUpd
;
for
(
MachineInstr
*
MI
:
Condsets
)
for
(
MachineOperand
&
Op
:
MI
->
operands
(
)
)
if
(
Op
.
isReg
(
)
&&
Op
.
isUse
(
)
)
if
(
!
CoalUpd
.
count
(
Op
.
getReg
(
)
)
)
KillUpd
.
insert
(
Op
.
getReg
(
)
)
;
updateLiveness
(
KillUpd
,
false
,
true
,
false
)
;
LLVM_DEBUG
(
LIS
->
print
(
dbgs
(
)
<<
"After coalescing\n"
,
MF
.
getFunction
(
)
.
getParent
(
)
)
)
;
for
(
MachineInstr
*
MI
:
Condsets
)
Changed
|=
split
(
*
MI
,
PredUpd
)
;
Condsets
.
clear
(
)
;
LLVM_DEBUG
(
LIS
->
print
(
dbgs
(
)
<<
"After splitting\n"
,
MF
.
getFunction
(
)
.
getParent
(
)
)
)
;
for
(
auto
&
B
:
MF
)
Changed
|=
predicateInBlock
(
B
,
PredUpd
)
;
LLVM_DEBUG
(
LIS
->
print
(
dbgs
(
)
<<
"After predicating\n"
,
MF
.
getFunction
(
)
.
getParent
(
)
)
)
;
PredUpd
.
insert
(
CoalUpd
.
begin
(
)
,
CoalUpd
.
end
(
)
)
;
updateLiveness
(
PredUpd
,
true
,
true
,
true
)
;
LLVM_DEBUG
(
{
if
(
Changed
)
LIS
->
print
(
dbgs
(
)
<<
"After expand-condsets\n"
,
MF
.
getFunction
(
)
.
getParent
(
)
)
;
}
)
;
return
Changed
;
}
</s>

runOnMachineFunction - Emit the function body .

Hexagon
Hexagon
Hexagon
"Before expand-condsets\n"
16
"After coalescing\n"
"After splitting\n"
"After predicating\n"
"After expand-condsets\n"


<s> virtual const HexagonRegisterInfo * getRegisterInfo ( ) const { return & InstrInfo . getRegisterInfo ( ) ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s>
const
char
*
getPassName
(
)
const
override
{
return
"Mips Constant Islands"
;
}
</s>

getPassName - Return a nice clean name for a pass .


"Can't store this register to stack slot"

Store the specified register of the given register class to the specified stack frame index .


<s> static int alpha_compute_xfloating_mode_arg ( enum rtx_code code , enum alpha_fp_rounding_mode round ) { int mode ; switch ( round ) { case ALPHA_FPRM_NORM : mode = 2 ; break ; case ALPHA_FPRM_MINF : mode = 1 ; break ; case ALPHA_FPRM_CHOP : mode = 0 ; break ; case ALPHA_FPRM_DYN : mode = 4 ; break ; default : gcc_unreachable ( ) ; } if ( code == FLOAT_TRUNCATE && alpha_fptm == ALPHA_FPTM_N ) mode |= 0x10000 ; return mode ; } </s>

Most X_floating operations take the rounding mode as an argument . Compute that here .


<s>
bool
ARCInstrInfo
::
analyzeBranch
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
*
&
TBB
,
MachineBasicBlock
*
&
FBB
,
SmallVectorImpl
<
MachineOperand
>
&
Cond
,
bool
AllowModify
)
const
{
TBB
=
FBB
=
nullptr
;
MachineBasicBlock
::
iterator
I
=
MBB
.
end
(
)
;
if
(
I
==
MBB
.
begin
(
)
)
return
false
;
I
;
while
(
isPredicated
(
*
I
)
||
I
->
isTerminator
(
)
||
I
->
isDebugValue
(
)
)
{
bool
CantAnalyze
=
false
;
while
(
I
->
isDebugInstr
(
)
||
!
I
->
isTerminator
(
)
)
{
if
(
I
==
MBB
.
begin
(
)
)
return
false
;
I
;
}
if
(
isJumpOpcode
(
I
->
getOpcode
(
)
)
)
{
CantAnalyze
=
true
;
}
else
if
(
isUncondBranchOpcode
(
I
->
getOpcode
(
)
)
)
{
TBB
=
I
->
getOperand
(
0
)
.
getMBB
(
)
;
}
else
if
(
isCondBranchOpcode
(
I
->
getOpcode
(
)
)
)
{
if
(
!
Cond
.
empty
(
)
)
return
true
;
assert
(
!
FBB
&&
"FBB should have been null."
)
;
FBB
=
TBB
;
TBB
=
I
->
getOperand
(
0
)
.
getMBB
(
)
;
Cond
.
push_back
(
I
->
getOperand
(
1
)
)
;
Cond
.
push_back
(
I
->
getOperand
(
2
)
)
;
Cond
.
push_back
(
I
->
getOperand
(
3
)
)
;
}
else
if
(
I
->
isReturn
(
)
)
{
CantAnalyze
=
!
isPredicated
(
*
I
)
;
}
else
{
return
true
;
}
if
(
!
isPredicated
(
*
I
)
&&
(
isUncondBranchOpcode
(
I
->
getOpcode
(
)
)
||
isJumpOpcode
(
I
->
getOpcode
(
)
)
||
I
->
isReturn
(
)
)
)
{
Cond
.
clear
(
)
;
FBB
=
nullptr
;
if
(
AllowModify
)
{
MachineBasicBlock
::
iterator
DI
=
std
::
next
(
I
)
;
while
(
DI
!=
MBB
.
end
(
)
)
{
MachineInstr
&
InstToDelete
=
*
DI
;
++
DI
;
InstToDelete
.
eraseFromParent
(
)
;
}
}
}
if
(
CantAnalyze
)
return
true
;
if
(
I
==
MBB
.
begin
(
)
)
return
false
;
I
;
}
return
false
;
}
</s>

analyzeBranch - Analyze the branching code at the end of MBB , returning true if it can not be understood ( e.g .


<s> SMLoc getEndLoc ( ) const override { return EndLoc ; } </s>

getEndLoc - Get the location of the last token of this operand .


<s> int h8300_expand_movsi ( rtx operands [ ] ) { rtx src = operands [ 1 ] ; rtx dst = operands [ 0 ] ; if ( ! reload_in_progress && ! reload_completed ) { if ( ! register_operand ( dst , GET_MODE ( dst ) ) ) { rtx tmp = gen_reg_rtx ( GET_MODE ( dst ) ) ; emit_move_insn ( tmp , src ) ; operands [ 1 ] = tmp ; } } return 0 ; } </s>


<s>
SDValue
RISCVTargetLowering
::
LowerReturn
(
SDValue
Chain
,
CallingConv
::
ID
CallConv
,
bool
IsVarArg
,
const
SmallVectorImpl
<
ISD
::
OutputArg
>
&
Outs
,
const
SmallVectorImpl
<
SDValue
>
&
OutVals
,
const
SDLoc
&
DL
,
SelectionDAG
&
DAG
)
const
{
SmallVector
<
CCValAssign
,
16
>
RVLocs
;
CCState
CCInfo
(
CallConv
,
IsVarArg
,
DAG
.
getMachineFunction
(
)
,
RVLocs
,
*
DAG
.
getContext
(
)
)
;
analyzeOutputArgs
(
DAG
.
getMachineFunction
(
)
,
CCInfo
,
Outs
,
true
,
nullptr
)
;
SDValue
Glue
;
SmallVector
<
SDValue
,
4
>
RetOps
(
1
,
Chain
)
;
for
(
unsigned
i
=
0
,
e
=
RVLocs
.
size
(
)
;
i
<
e
;
++
i
)
{
SDValue
Val
=
OutVals
[
i
]
;
CCValAssign
&
VA
=
RVLocs
[
i
]
;
assert
(
VA
.
isRegLoc
(
)
&&
"Can only return in registers!"
)
;
if
(
VA
.
getLocVT
(
)
==
MVT
::
i32
&&
VA
.
getValVT
(
)
==
MVT
::
f64
)
{
assert
(
VA
.
isRegLoc
(
)
&&
"Expected return via registers"
)
;
SDValue
SplitF64
=
DAG
.
getNode
(
RISCVISD
::
SplitF64
,
DL
,
DAG
.
getVTList
(
MVT
::
i32
,
MVT
::
i32
)
,
Val
)
;
SDValue
Lo
=
SplitF64
.
getValue
(
0
)
;
SDValue
Hi
=
SplitF64
.
getValue
(
1
)
;
unsigned
RegLo
=
VA
.
getLocReg
(
)
;
unsigned
RegHi
=
RegLo
+
1
;
Chain
=
DAG
.
getCopyToReg
(
Chain
,
DL
,
RegLo
,
Lo
,
Glue
)
;
Glue
=
Chain
.
getValue
(
1
)
;
RetOps
.
push_back
(
DAG
.
getRegister
(
RegLo
,
MVT
::
i32
)
)
;
Chain
=
DAG
.
getCopyToReg
(
Chain
,
DL
,
RegHi
,
Hi
,
Glue
)
;
Glue
=
Chain
.
getValue
(
1
)
;
RetOps
.
push_back
(
DAG
.
getRegister
(
RegHi
,
MVT
::
i32
)
)
;
}
else
{
Val
=
packIntoRegLoc
(
DAG
,
Val
,
VA
,
DL
)
;
Chain
=
DAG
.
getCopyToReg
(
Chain
,
DL
,
VA
.
getLocReg
(
)
,
Val
,
Glue
)
;
Glue
=
Chain
.
getValue
(
1
)
;
RetOps
.
push_back
(
DAG
.
getRegister
(
VA
.
getLocReg
(
)
,
VA
.
getLocVT
(
)
)
)
;
}
}
RetOps
[
0
]
=
Chain
;
if
(
Glue
.
getNode
(
)
)
{
RetOps
.
push_back
(
Glue
)
;
}
return
DAG
.
getNode
(
RISCVISD
::
RET_FLAG
,
DL
,
MVT
::
Other
,
RetOps
)
;
}
</s>

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .


<s> void RISCVTargetStreamer :: emitTargetAttributes ( const MCSubtargetInfo & STI ) { if ( STI . hasFeature ( RISCV :: FeatureRV32E ) ) emitAttribute ( RISCVAttrs :: STACK_ALIGN , RISCVAttrs :: ALIGN_4 ) ; else emitAttribute ( RISCVAttrs :: STACK_ALIGN , RISCVAttrs :: ALIGN_16 ) ; std :: string Arch = "rv32" ; if ( STI . hasFeature ( RISCV :: Feature64Bit ) ) Arch = "rv64" ; if ( STI . hasFeature ( RISCV :: FeatureRV32E ) ) Arch += "e1p9" ; else Arch += "i2p0" ; if ( STI . hasFeature ( RISCV :: FeatureStdExtM ) ) Arch += "_m2p0" ; if ( STI . hasFeature ( RISCV :: FeatureStdExtA ) ) Arch += "_a2p0" ; if ( STI . hasFeature ( RISCV :: FeatureStdExtF ) ) Arch += "_f2p0" ; if ( STI . hasFeature ( RISCV :: FeatureStdExtD ) ) Arch += "_d2p0" ; if ( STI . hasFeature ( RISCV :: FeatureStdExtC ) ) Arch += "_c2p0" ; if ( STI . hasFeature ( RISCV :: FeatureStdExtB ) ) Arch += "_b0p93" ; if ( STI . hasFeature ( RISCV :: FeatureStdExtV ) ) Arch += "_v0p10" ; if ( STI . hasFeature ( RISCV :: FeatureExtZfh ) ) Arch += "_zfh0p1" ; if ( STI . hasFeature ( RISCV :: FeatureExtZba ) ) Arch += "_zba0p93" ; if ( STI . hasFeature ( RISCV :: FeatureExtZbb ) ) Arch += "_zbb0p93" ; if ( STI . hasFeature ( RISCV :: FeatureExtZbc ) ) Arch += "_zbc0p93" ; if ( STI . hasFeature ( RISCV :: FeatureExtZbe ) ) Arch += "_zbe0p93" ; if ( STI . hasFeature ( RISCV :: FeatureExtZbf ) ) Arch += "_zbf0p93" ; if ( STI . hasFeature ( RISCV :: FeatureExtZbm ) ) Arch += "_zbm0p93" ; if ( STI . hasFeature ( RISCV :: FeatureExtZbp ) ) Arch += "_zbp0p93" ; if ( STI . hasFeature ( RISCV :: FeatureExtZbproposedc ) ) Arch += "_zbproposedc0p93" ; if ( STI . hasFeature ( RISCV :: FeatureExtZbr ) ) Arch += "_zbr0p93" ; if ( STI . hasFeature ( RISCV :: FeatureExtZbs ) ) Arch += "_zbs0p93" ; if ( STI . hasFeature ( RISCV :: FeatureExtZbt ) ) Arch += "_zbt0p93" ; if ( STI . hasFeature ( RISCV :: FeatureExtZvamo ) ) Arch += "_zvamo0p10" ; if ( STI . hasFeature ( RISCV :: FeatureStdExtZvlsseg ) ) Arch += "_zvlsseg0p10" ; if ( STI . hasFeature ( RISCV :: FeatureCheri ) ) Arch += "_xcheri0p0" ; emitTextAttribute ( RISCVAttrs :: ARCH , Arch ) ; } </s>

Emit the build attributes that only depend on the hardware that we expect .


<s> bool MipsAsmBackend :: writeNopData ( uint64_t Count , MCObjectWriter * OW ) const { OW -> WriteZeros ( Count ) ; return true ; } </s>

Write an ( optimal ) nop sequence of Count bytes to the given output .


<s> static bool m68k_legitimate_mem_p ( rtx x , struct m68k_address * address ) { return ( MEM_P ( x ) && m68k_decompose_address ( GET_MODE ( x ) , XEXP ( x , 0 ) , reload_in_progress || reload_completed , address ) ) ; } </s>

Return true if X is a memory , describing its address in ADDRESS if so . Apply strict checking if called during or after reload .


<s>
void
WebAssemblyAsmPrinter
::
emitInstruction
(
const
MachineInstr
*
MI
)
{
LLVM_DEBUG
(
dbgs
(
)
<<
"EmitInstruction: "
<<
*
MI
<<
'\n'
)
;
switch
(
MI
->
getOpcode
(
)
)
{
case
WebAssembly
::
ARGUMENT_i32
:
case
WebAssembly
::
ARGUMENT_i32_S
:
case
WebAssembly
::
ARGUMENT_i64
:
case
WebAssembly
::
ARGUMENT_i64_S
:
case
WebAssembly
::
ARGUMENT_f32
:
case
WebAssembly
::
ARGUMENT_f32_S
:
case
WebAssembly
::
ARGUMENT_f64
:
case
WebAssembly
::
ARGUMENT_f64_S
:
case
WebAssembly
::
ARGUMENT_v16i8
:
case
WebAssembly
::
ARGUMENT_v16i8_S
:
case
WebAssembly
::
ARGUMENT_v8i16
:
case
WebAssembly
::
ARGUMENT_v8i16_S
:
case
WebAssembly
::
ARGUMENT_v4i32
:
case
WebAssembly
::
ARGUMENT_v4i32_S
:
case
WebAssembly
::
ARGUMENT_v2i64
:
case
WebAssembly
::
ARGUMENT_v2i64_S
:
case
WebAssembly
::
ARGUMENT_v4f32
:
case
WebAssembly
::
ARGUMENT_v4f32_S
:
case
WebAssembly
::
ARGUMENT_v2f64
:
case
WebAssembly
::
ARGUMENT_v2f64_S
:
break
;
case
WebAssembly
::
FALLTHROUGH_RETURN
:
{
if
(
isVerbose
(
)
)
{
OutStreamer
->
AddComment
(
"fallthrough-return"
)
;
OutStreamer
->
AddBlankLine
(
)
;
}
break
;
}
case
WebAssembly
::
COMPILER_FENCE
:
break
;
case
WebAssembly
::
EXTRACT_EXCEPTION_I32
:
case
WebAssembly
::
EXTRACT_EXCEPTION_I32_S
:
if
(
!
WasmKeepRegisters
)
break
;
LLVM_FALLTHROUGH
;
default
:
{
WebAssemblyMCInstLower
MCInstLowering
(
OutContext
,
*
this
)
;
MCInst
TmpInst
;
MCInstLowering
.
lower
(
MI
,
TmpInst
)
;
EmitToStreamer
(
*
OutStreamer
,
TmpInst
)
;
break
;
}
}
}
</s>

Targets should implement this to emit instructions .


<s>
void
RISCVAsmBackend
::
applyFixup
(
const
MCAssembler
&
Asm
,
const
MCFixup
&
Fixup
,
const
MCValue
&
Target
,
MutableArrayRef
<
char
>
Data
,
uint64_t
Value
,
bool
IsResolved
)
const
{
MCContext
&
Ctx
=
Asm
.
getContext
(
)
;
MCFixupKindInfo
Info
=
getFixupKindInfo
(
Fixup
.
getKind
(
)
)
;
if
(
!
Value
)
return
;
Value
=
adjustFixupValue
(
Fixup
,
Value
,
Ctx
)
;
Value
<<=
Info
.
TargetOffset
;
unsigned
Offset
=
Fixup
.
getOffset
(
)
;
unsigned
NumBytes
=
alignTo
(
Info
.
TargetSize
+
Info
.
TargetOffset
,
8
)
/
8
;
assert
(
Offset
+
NumBytes
<=
Data
.
size
(
)
&&
"Invalid fixup offset!"
)
;
for
(
unsigned
i
=
0
;
i
!=
NumBytes
;
++
i
)
{
Data
[
Offset
+
i
]
|=
uint8_t
(
(
Value
>>
(
i
*
8
)
)
&
0xff
)
;
}
}
</s>

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


<s>
ScheduleHazardRecognizer
::
HazardType
SPUHazardRecognizer
::
getHazardType
(
SUnit
*
SU
)
{
const
SDNode
*
Node
=
SU
->
getNode
(
)
->
getFlaggedMachineNode
(
)
;
ScheduleHazardRecognizer
::
HazardType
retval
=
NoHazard
;
bool
mustBeOdd
=
false
;
switch
(
Node
->
getOpcode
(
)
)
{
case
SPU
::
LQDv16i8
:
case
SPU
::
LQDv8i16
:
case
SPU
::
LQDv4i32
:
case
SPU
::
LQDv4f32
:
case
SPU
::
LQDv2f64
:
case
SPU
::
LQDr128
:
case
SPU
::
LQDr64
:
case
SPU
::
LQDr32
:
case
SPU
::
LQDr16
:
case
SPU
::
LQAv16i8
:
case
SPU
::
LQAv8i16
:
case
SPU
::
LQAv4i32
:
case
SPU
::
LQAv4f32
:
case
SPU
::
LQAv2f64
:
case
SPU
::
LQAr128
:
case
SPU
::
LQAr64
:
case
SPU
::
LQAr32
:
case
SPU
::
LQXv4i32
:
case
SPU
::
LQXr128
:
case
SPU
::
LQXr64
:
case
SPU
::
LQXr32
:
case
SPU
::
LQXr16
:
case
SPU
::
STQDv16i8
:
case
SPU
::
STQDv8i16
:
case
SPU
::
STQDv4i32
:
case
SPU
::
STQDv4f32
:
case
SPU
::
STQDv2f64
:
case
SPU
::
STQDr128
:
case
SPU
::
STQDr64
:
case
SPU
::
STQDr32
:
case
SPU
::
STQDr16
:
case
SPU
::
STQDr8
:
case
SPU
::
STQAv16i8
:
case
SPU
::
STQAv8i16
:
case
SPU
::
STQAv4i32
:
case
SPU
::
STQAv4f32
:
case
SPU
::
STQAv2f64
:
case
SPU
::
STQAr128
:
case
SPU
::
STQAr64
:
case
SPU
::
STQAr32
:
case
SPU
::
STQAr16
:
case
SPU
::
STQAr8
:
case
SPU
::
STQXv16i8
:
case
SPU
::
STQXv8i16
:
case
SPU
::
STQXv4i32
:
case
SPU
::
STQXv4f32
:
case
SPU
::
STQXv2f64
:
case
SPU
::
STQXr128
:
case
SPU
::
STQXr64
:
case
SPU
::
STQXr32
:
case
SPU
::
STQXr16
:
case
SPU
::
STQXr8
:
case
SPU
::
RET
:
mustBeOdd
=
true
;
break
;
default
:
break
;
}
if
(
mustBeOdd
&&
!
EvenOdd
)
retval
=
Hazard
;
DEBUG
(
errs
(
)
<<
"SPUHazardRecognizer EvenOdd "
<<
EvenOdd
<<
" Hazard "
<<
retval
<<
"\n"
)
;
EvenOdd
^=
1
;
return
retval
;
return
NoHazard
;
}
</s>

getHazardType - Return the hazard type of emitting this node .


<s>
void
AlphaInstrInfo
::
storeRegToStackSlot
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
MI
,
unsigned
SrcReg
,
bool
isKill
,
int
FrameIdx
,
const
TargetRegisterClass
*
RC
)
const
{
DebugLoc
DL
;
if
(
MI
!=
MBB
.
end
(
)
)
DL
=
MI
->
getDebugLoc
(
)
;
if
(
RC
==
Alpha
::
F4RCRegisterClass
)
BuildMI
(
MBB
,
MI
,
DL
,
get
(
Alpha
::
STS
)
)
.
addReg
(
SrcReg
,
getKillRegState
(
isKill
)
)
.
addFrameIndex
(
FrameIdx
)
.
addReg
(
Alpha
::
F31
)
;
else
if
(
RC
==
Alpha
::
F8RCRegisterClass
)
BuildMI
(
MBB
,
MI
,
DL
,
get
(
Alpha
::
STT
)
)
.
addReg
(
SrcReg
,
getKillRegState
(
isKill
)
)
.
addFrameIndex
(
FrameIdx
)
.
addReg
(
Alpha
::
F31
)
;
else
if
(
RC
==
Alpha
::
GPRCRegisterClass
)
BuildMI
(
MBB
,
MI
,
DL
,
get
(
Alpha
::
STQ
)
)
.
addReg
(
SrcReg
,
getKillRegState
(
isKill
)
)
.
addFrameIndex
(
FrameIdx
)
.
addReg
(
Alpha
::
F31
)
;
else
llvm_unreachable
(
"Unhandled register class"
)
;
}
</s>


<s>
int
R600InstrInfo
::
getOperandIdx
(
unsigned
Opcode
,
R600Operands
::
Ops
Op
)
const
{
const
static
int
OpTable
[
3
]
[
R600Operands
::
COUNT
]
=
{
{
0
,
1
,
1
,
1
,
2
,
3
,
4
,
5
,
6
,
7
,
8
,
1
,
1
,
1
,
1
,
1
,
1
,
1
,
9
,
10
,
11
}
,
{
0
,
1
,
2
,
3
,
4
,
5
,
6
,
7
,
8
,
9
,
10
,
11
,
12
,
1
,
1
,
1
,
13
,
14
,
15
,
16
,
17
}
,
{
0
,
1
,
1
,
1
,
1
,
1
,
2
,
3
,
4
,
5
,
1
,
6
,
7
,
8
,
1
,
9
,
10
,
11
,
12
,
13
,
14
}
}
;
unsigned
TargetFlags
=
get
(
Opcode
)
.
TSFlags
;
unsigned
OpTableIdx
;
if
(
!
HAS_NATIVE_OPERANDS
(
TargetFlags
)
)
{
switch
(
Op
)
{
case
R600Operands
::
DST
:
return
0
;
case
R600Operands
::
SRC0
:
return
1
;
case
R600Operands
::
SRC1
:
return
2
;
case
R600Operands
::
SRC2
:
return
3
;
default
:
assert
(
!
"Unknown operand type for instruction"
)
;
return
1
;
}
}
if
(
TargetFlags
&
R600_InstFlag
::
OP1
)
{
OpTableIdx
=
0
;
}
else
if
(
TargetFlags
&
R600_InstFlag
::
OP2
)
{
OpTableIdx
=
1
;
}
else
{
assert
(
(
TargetFlags
&
R600_InstFlag
::
OP3
)
&&
"OP1, OP2, or OP3 not defined "
"for this instruction"
)
;
OpTableIdx
=
2
;
}
return
OpTable
[
OpTableIdx
]
[
Op
]
;
}
</s>

Get the index of Op for the given Opcode .


<s> bool enablePostRAScheduler ( ) const override { return isGeneric ( ) || isCortexA53 ( ) || isCortexA57 ( ) || isKryo ( ) ; } </s>

True if the subtarget should run a scheduler after register allocation .


"Can only put epilog before 'ret' instruction!"


<s> bool Z80CallFrameOptimization :: runOnMachineFunction ( MachineFunction & MF ) { if ( skipFunction ( MF . getFunction ( ) ) || NoZ80CFOpt . getValue ( ) ) { return false ; } return false ; } </s>


<s> bool PPCLinuxAsmPrinter :: doFinalization ( Module & M ) { const DataLayout * TD = TM . getSubtargetImpl ( ) -> getDataLayout ( ) ; bool isPPC64 = TD -> getPointerSizeInBits ( ) == 64 ; PPCTargetStreamer & TS = static_cast < PPCTargetStreamer & > ( * OutStreamer . getTargetStreamer ( ) ) ; if ( ! TOC . empty ( ) ) { const MCSectionELF * Section ; if ( isPPC64 ) Section = OutStreamer . getContext ( ) . getELFSection ( ".toc" , ELF :: SHT_PROGBITS , ELF :: SHF_WRITE | ELF :: SHF_ALLOC , SectionKind :: getReadOnly ( ) ) ; else Section = OutStreamer . getContext ( ) . getELFSection ( ".got2" , ELF :: SHT_PROGBITS , ELF :: SHF_WRITE | ELF :: SHF_ALLOC , SectionKind :: getReadOnly ( ) ) ; OutStreamer . SwitchSection ( Section ) ; for ( MapVector < MCSymbol * , MCSymbol * > :: iterator I = TOC . begin ( ) , E = TOC . end ( ) ; I != E ; ++ I ) { OutStreamer . EmitLabel ( I -> second ) ; MCSymbol * S = OutContext . GetOrCreateSymbol ( I -> first -> getName ( ) ) ; if ( isPPC64 ) TS . emitTCEntry ( * S ) ; else OutStreamer . EmitSymbolValue ( S , 4 ) ; } } MachineModuleInfoELF & MMIELF = MMI -> getObjFileInfo < MachineModuleInfoELF > ( ) ; MachineModuleInfoELF :: SymbolListTy Stubs = MMIELF . GetGVStubList ( ) ; if ( ! Stubs . empty ( ) ) { OutStreamer . SwitchSection ( getObjFileLowering ( ) . getDataSection ( ) ) ; for ( unsigned i = 0 , e = Stubs . size ( ) ; i != e ; ++ i ) { OutStreamer . EmitLabel ( Stubs [ i ] . first ) ; OutStreamer . EmitValue ( MCSymbolRefExpr :: Create ( Stubs [ i ] . second . getPointer ( ) , OutContext ) , isPPC64 ? 8 : 4 ) ; } Stubs . clear ( ) ; OutStreamer . AddBlankLine ( ) ; } return AsmPrinter :: doFinalization ( M ) ; } </s>

doFinalization - Virtual method overriden by subclasses to do any necessary clean up after all passes have run .


<s> bool AArch64AsmParser :: ParseDirective ( AsmToken DirectiveID ) { StringRef IDVal = DirectiveID . getIdentifier ( ) ; SMLoc Loc = DirectiveID . getLoc ( ) ; if ( IDVal == ".hword" ) return parseDirectiveWord ( 2 , Loc ) ; if ( IDVal == ".word" ) return parseDirectiveWord ( 4 , Loc ) ; if ( IDVal == ".xword" ) return parseDirectiveWord ( 8 , Loc ) ; if ( IDVal == ".tlsdesccall" ) return parseDirectiveTLSDescCall ( Loc ) ; if ( IDVal == ".ltorg" || IDVal == ".pool" ) return parseDirectiveLtorg ( Loc ) ; if ( IDVal == ".unreq" ) return parseDirectiveUnreq ( DirectiveID . getLoc ( ) ) ; return parseDirectiveLOH ( IDVal , Loc ) ; } </s>

ParseDirective - Parse a target specific assembler directive This method is deprecated , use 'parseDirective ' instead .


<s> bool Thumb1RegisterInfo :: saveScavengerRegister ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , MachineBasicBlock :: iterator & UseMI , const TargetRegisterClass * RC , unsigned Reg ) const { DebugLoc DL ; BuildMI ( MBB , I , DL , TII . get ( ARM :: tMOVtgpr2gpr ) ) . addReg ( ARM :: R12 , RegState :: Define ) . addReg ( Reg , RegState :: Kill ) ; bool done = false ; for ( MachineBasicBlock :: iterator II = I ; ! done && II != UseMI ; ++ II ) { for ( unsigned i = 0 , e = II -> getNumOperands ( ) ; i != e ; ++ i ) { const MachineOperand & MO = II -> getOperand ( i ) ; if ( ! MO . isReg ( ) || MO . isUndef ( ) || ! MO . getReg ( ) || TargetRegisterInfo :: isVirtualRegister ( MO . getReg ( ) ) ) continue ; if ( MO . getReg ( ) == ARM :: R12 ) { UseMI = II ; done = true ; break ; } } } BuildMI ( MBB , UseMI , DL , TII . get ( ARM :: tMOVgpr2tgpr ) ) . addReg ( Reg , RegState :: Define ) . addReg ( ARM :: R12 , RegState :: Kill ) ; return true ; } </s>

Spill the register so it can be used by the register scavenger .


<s> static void AnalyzeArguments ( CCState & State , SmallVectorImpl < CCValAssign > & ArgLocs , const SmallVectorImpl < ArgT > & Args ) { static const MCPhysReg RegList [ ] = { MSP430 :: R12 , MSP430 :: R13 , MSP430 :: R14 , MSP430 :: R15 } ; static const unsigned NbRegs = array_lengthof ( RegList ) ; if ( State . isVarArg ( ) ) { AnalyzeVarArgs ( State , Args ) ; return ; } SmallVector < unsigned , 4 > ArgsParts ; ParseFunctionArgs ( Args , ArgsParts ) ; unsigned RegsLeft = NbRegs ; bool UsedStack = false ; unsigned ValNo = 0 ; for ( unsigned i = 0 , e = ArgsParts . size ( ) ; i != e ; i ++ ) { MVT ArgVT = Args [ ValNo ] . VT ; ISD :: ArgFlagsTy ArgFlags = Args [ ValNo ] . Flags ; MVT LocVT = ArgVT ; CCValAssign :: LocInfo LocInfo = CCValAssign :: Full ; if ( LocVT == MVT :: i8 ) { LocVT = MVT :: i16 ; if ( ArgFlags . isSExt ( ) ) LocInfo = CCValAssign :: SExt ; else if ( ArgFlags . isZExt ( ) ) LocInfo = CCValAssign :: ZExt ; else LocInfo = CCValAssign :: AExt ; } if ( ArgFlags . isByVal ( ) ) { State . HandleByVal ( ValNo ++ , ArgVT , LocVT , LocInfo , 2 , 2 , ArgFlags ) ; continue ; } unsigned Parts = ArgsParts [ i ] ; if ( ! UsedStack && Parts == 2 && RegsLeft == 1 ) { unsigned Reg = State . AllocateReg ( RegList ) ; State . addLoc ( CCValAssign :: getReg ( ValNo ++ , ArgVT , Reg , LocVT , LocInfo ) ) ; RegsLeft -= 1 ; UsedStack = true ; CC_MSP430_AssignStack ( ValNo ++ , ArgVT , LocVT , LocInfo , ArgFlags , State ) ; } else if ( Parts <= RegsLeft ) { for ( unsigned j = 0 ; j < Parts ; j ++ ) { unsigned Reg = State . AllocateReg ( RegList ) ; State . addLoc ( CCValAssign :: getReg ( ValNo ++ , ArgVT , Reg , LocVT , LocInfo ) ) ; RegsLeft -- ; } } else { UsedStack = true ; for ( unsigned j = 0 ; j < Parts ; j ++ ) CC_MSP430_AssignStack ( ValNo ++ , ArgVT , LocVT , LocInfo , ArgFlags , State ) ; } } } </s>

The function will invoke AnalyzeCallOperands .


<s> const PPCInstrInfo * getInstrInfo ( ) const { return & InstrInfo ; } </s>


<s> rtx get_avl ( ) const { return m_avl . get_value ( ) ; } </s>


<s> bool R600InstrInfo :: isPredicated ( const MachineInstr & MI ) const { int idx = MI . findFirstPredOperandIdx ( ) ; if ( idx < 0 ) return false ; unsigned Reg = MI . getOperand ( idx ) . getReg ( ) ; switch ( Reg ) { default : return false ; case AMDGPU :: PRED_SEL_ONE : case AMDGPU :: PRED_SEL_ZERO : case AMDGPU :: PREDICATE_BIT : return true ; } } </s>

Returns true if the instruction is already predicated .


<s>
bool
AMDGPUAsmPrinter
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
MF
.
setAlignment
(
8
)
;
SetupMachineFunction
(
MF
)
;
MCContext
&
Context
=
getObjFileLowering
(
)
.
getContext
(
)
;
MCSectionELF
*
ConfigSection
=
Context
.
getELFSection
(
".AMDGPU.config"
,
ELF
::
SHT_PROGBITS
,
0
)
;
OutStreamer
->
SwitchSection
(
ConfigSection
)
;
const
AMDGPUSubtarget
&
STM
=
MF
.
getSubtarget
<
AMDGPUSubtarget
>
(
)
;
SIProgramInfo
KernelInfo
;
if
(
STM
.
isAmdHsaOS
(
)
)
{
getSIProgramInfo
(
KernelInfo
,
MF
)
;
EmitAmdKernelCodeT
(
MF
,
KernelInfo
)
;
OutStreamer
->
EmitCodeAlignment
(
2
<<
(
MF
.
getAlignment
(
)
1
)
)
;
}
else
if
(
STM
.
getGeneration
(
)
>=
AMDGPUSubtarget
::
SOUTHERN_ISLANDS
)
{
getSIProgramInfo
(
KernelInfo
,
MF
)
;
EmitProgramInfoSI
(
MF
,
KernelInfo
)
;
}
else
{
EmitProgramInfoR600
(
MF
)
;
}
DisasmLines
.
clear
(
)
;
HexLines
.
clear
(
)
;
DisasmLineMaxLen
=
0
;
EmitFunctionBody
(
)
;
if
(
isVerbose
(
)
)
{
MCSectionELF
*
CommentSection
=
Context
.
getELFSection
(
".AMDGPU.csdata"
,
ELF
::
SHT_PROGBITS
,
0
)
;
OutStreamer
->
SwitchSection
(
CommentSection
)
;
if
(
STM
.
getGeneration
(
)
>=
AMDGPUSubtarget
::
SOUTHERN_ISLANDS
)
{
OutStreamer
->
emitRawComment
(
" Kernel info:"
,
false
)
;
OutStreamer
->
emitRawComment
(
" codeLenInByte = "
+
Twine
(
KernelInfo
.
CodeLen
)
,
false
)
;
OutStreamer
->
emitRawComment
(
" NumSgprs: "
+
Twine
(
KernelInfo
.
NumSGPR
)
,
false
)
;
OutStreamer
->
emitRawComment
(
" NumVgprs: "
+
Twine
(
KernelInfo
.
NumVGPR
)
,
false
)
;
OutStreamer
->
emitRawComment
(
" FloatMode: "
+
Twine
(
KernelInfo
.
FloatMode
)
,
false
)
;
OutStreamer
->
emitRawComment
(
" IeeeMode: "
+
Twine
(
KernelInfo
.
IEEEMode
)
,
false
)
;
OutStreamer
->
emitRawComment
(
" ScratchSize: "
+
Twine
(
KernelInfo
.
ScratchSize
)
,
false
)
;
}
else
{
R600MachineFunctionInfo
*
MFI
=
MF
.
getInfo
<
R600MachineFunctionInfo
>
(
)
;
OutStreamer
->
emitRawComment
(
Twine
(
"SQ_PGM_RESOURCES:STACK_SIZE = "
+
Twine
(
MFI
->
StackSize
)
)
)
;
}
}
if
(
STM
.
dumpCode
(
)
)
{
OutStreamer
->
SwitchSection
(
Context
.
getELFSection
(
".AMDGPU.disasm"
,
ELF
::
SHT_NOTE
,
0
)
)
;
for
(
size_t
i
=
0
;
i
<
DisasmLines
.
size
(
)
;
++
i
)
{
std
::
string
Comment
(
DisasmLineMaxLen
DisasmLines
[
i
]
.
size
(
)
,
' '
)
;
Comment
+=
" ; "
+
HexLines
[
i
]
+
"\n"
;
OutStreamer
->
EmitBytes
(
StringRef
(
DisasmLines
[
i
]
)
)
;
OutStreamer
->
EmitBytes
(
StringRef
(
Comment
)
)
;
}
}
return
false
;
}
</s>

runOnMachineFunction - Emit the function body .


<s> void GCNPassConfig :: addMachineSSAOptimization ( ) { TargetPassConfig :: addMachineSSAOptimization ( ) ; addPass ( & SIFoldOperandsID ) ; addPass ( & DeadMachineInstructionElimID ) ; addPass ( & SILoadStoreOptimizerID ) ; addPass ( createSIShrinkInstructionsPass ( ) ) ; if ( EnableSDWAPeephole ) { addPass ( & SIPeepholeSDWAID ) ; addPass ( & DeadMachineInstructionElimID ) ; } } </s>

Methods with trivial inline returns are convenient points in the common codegen pass pipeline where targets may insert passes .


<s> const MCPhysReg * RISCVRegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { auto & Subtarget = MF -> getSubtarget < RISCVSubtarget > ( ) ; if ( MF -> getFunction ( ) . hasFnAttribute ( "interrupt" ) ) { if ( Subtarget . hasStdExtD ( ) ) return CSR_XLEN_F64_Interrupt_SaveList ; if ( Subtarget . hasStdExtF ( ) ) return CSR_XLEN_F32_Interrupt_SaveList ; return CSR_Interrupt_SaveList ; } return CSR_ILP32_LP64_SaveList ; } </s>


"ABI for flattened struct with zero-length "

See whether TYPE is a record whose fields should be returned in one or floating-point register and one integer register . If so , populate FIELDS accordingly .


<s>
static
void
rs6000_xcoff_file_start
(
void
)
{
rs6000_gen_section_name
(
&
xcoff_bss_section_name
,
main_input_filename
,
".bss_"
)
;
rs6000_gen_section_name
(
&
xcoff_private_data_section_name
,
main_input_filename
,
".rw_"
)
;
rs6000_gen_section_name
(
&
xcoff_read_only_section_name
,
main_input_filename
,
".ro_"
)
;
fputs
(
"\t.file\t"
,
asm_out_file
)
;
output_quoted_string
(
asm_out_file
,
main_input_filename
)
;
fputc
(
'\n'
,
asm_out_file
)
;
if
(
write_symbols
!=
NO_DEBUG
)
private_data_section
(
)
;
text_section
(
)
;
if
(
profile_flag
)
fprintf
(
asm_out_file
,
"\t.extern %s\n"
,
RS6000_MCOUNT
)
;
rs6000_file_start
(
)
;
}
</s>

Output at beginning of assembler file . Initialize the section names for the RS/6000 at this point . Specify filename , including full path , to assembler . We want to go into the TOC section so at least one .toc will be emitted . Also , in order to output proper .bs/.es pairs , we need at least one static [ RW ] section emitted . Finally , declare mcount when profiling to make the assembler happy .


<s> static int mips_issue_rate ( void ) { switch ( mips_tune ) { case PROCESSOR_74KC : case PROCESSOR_74KF2_1 : case PROCESSOR_74KF1_1 : case PROCESSOR_74KF3_2 : case PROCESSOR_R10000 : return 4 ; case PROCESSOR_20KC : case PROCESSOR_R4130 : case PROCESSOR_R5400 : case PROCESSOR_R5500 : case PROCESSOR_R5900 : case PROCESSOR_R7000 : case PROCESSOR_R9000 : case PROCESSOR_OCTEON : case PROCESSOR_OCTEON2 : case PROCESSOR_OCTEON3 : case PROCESSOR_I6400 : return 2 ; case PROCESSOR_SB1 : case PROCESSOR_SB1A : return 3 ; case PROCESSOR_LOONGSON_2E : case PROCESSOR_LOONGSON_2F : case PROCESSOR_LOONGSON_3A : case PROCESSOR_P5600 : return 4 ; case PROCESSOR_XLP : return ( reload_completed ? 4 : 3 ) ; default : return 1 ; } } </s>

Return the number of instructions that can be issued per cycle .


<s>
void
print
(
raw_ostream
&
OS
)
const
override
{
switch
(
Kind
)
{
case
k_Immediate
:
OS
<<
"Imm<"
;
OS
<<
*
Imm
.
Val
;
OS
<<
">"
;
break
;
case
k_Memory
:
OS
<<
"Mem<"
;
OS
<<
Mem
.
Base
;
OS
<<
", "
;
OS
<<
*
Mem
.
Off
;
OS
<<
">"
;
break
;
case
k_Register
:
OS
<<
"Register<"
<<
Reg
.
RegNum
<<
">"
;
break
;
case
k_Token
:
OS
<<
Tok
.
Data
;
break
;
}
}
</s>

print - Print a debug representation of the operand to the given stream .


"Attempted to created cross-class register copy"


<s> HOST_WIDE_INT alpha_initial_elimination_offset ( unsigned int from , unsigned int to ATTRIBUTE_UNUSED ) { HOST_WIDE_INT ret ; ret = alpha_sa_size ( ) ; ret += ALPHA_ROUND ( crtl -> outgoing_args_size ) ; switch ( from ) { case FRAME_POINTER_REGNUM : break ; case ARG_POINTER_REGNUM : ret += ( ALPHA_ROUND ( get_frame_size ( ) + crtl -> args . pretend_args_size ) - crtl -> args . pretend_args_size ) ; break ; default : gcc_unreachable ( ) ; } return ret ; } </s>

Define the offset between two registers , one to be eliminated , and the other its replacement , at the start of a routine .


<s> bool Z80TargetLowering :: isZExtFree ( EVT VT1 , EVT VT2 ) const { return VT1 == MVT :: i16 && VT2 == MVT :: i24 && Subtarget . is24Bit ( ) ; } </s>

Return true if zero-extending the specific node Val to type VT2 is free ( either because it 's implicitly zero-extended such as ARM ldrb / ldrh or because it 's folded such as X86 zero-extending loads ) .


<s> bool AArch64CallLowering :: lowerFormalArguments ( MachineIRBuilder & MIRBuilder , const Function & F , ArrayRef < unsigned > VRegs ) const { MachineFunction & MF = MIRBuilder . getMF ( ) ; MachineBasicBlock & MBB = MIRBuilder . getMBB ( ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; auto & DL = F . getParent ( ) -> getDataLayout ( ) ; SmallVector < ArgInfo , 8 > SplitArgs ; unsigned i = 0 ; for ( auto & Arg : F . args ( ) ) { ArgInfo OrigArg { VRegs [ i ] , Arg . getType ( ) } ; setArgFlags ( OrigArg , i + 1 , DL , F ) ; bool Split = false ; LLT Ty = MRI . getType ( VRegs [ i ] ) ; unsigned Dst = VRegs [ i ] ; splitToValueTypes ( OrigArg , SplitArgs , DL , MRI , [ & ] ( unsigned Reg , uint64_t Offset ) { if ( ! Split ) { Split = true ; Dst = MRI . createGenericVirtualRegister ( Ty ) ; MIRBuilder . buildUndef ( Dst ) ; } unsigned Tmp = MRI . createGenericVirtualRegister ( Ty ) ; MIRBuilder . buildInsert ( Tmp , Dst , Reg , Offset ) ; Dst = Tmp ; } ) ; if ( Dst != VRegs [ i ] ) MIRBuilder . buildCopy ( VRegs [ i ] , Dst ) ; ++ i ; } if ( ! MBB . empty ( ) ) MIRBuilder . setInstr ( * MBB . begin ( ) ) ; const AArch64TargetLowering & TLI = * getTLI < AArch64TargetLowering > ( ) ; CCAssignFn * AssignFn = TLI . CCAssignFnForCall ( F . getCallingConv ( ) , false ) ; FormalArgHandler Handler ( MIRBuilder , MRI , AssignFn ) ; if ( ! handleAssignments ( MIRBuilder , SplitArgs , Handler ) ) return false ; if ( F . isVarArg ( ) ) { if ( ! MF . getSubtarget < AArch64Subtarget > ( ) . isTargetDarwin ( ) ) { return false ; } uint64_t StackOffset = alignTo ( Handler . StackUsed , 8 ) ; auto & MFI = MIRBuilder . getMF ( ) . getFrameInfo ( ) ; AArch64FunctionInfo * FuncInfo = MF . getInfo < AArch64FunctionInfo > ( ) ; FuncInfo -> setVarArgsStackIndex ( MFI . CreateFixedObject ( 4 , StackOffset , true ) ) ; } MIRBuilder . setMBB ( MBB ) ; return true ; } </s>

This hook must be implemented to lower the incoming ( formal ) arguments , described by VRegs , for GlobalISel .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . addRequired < ProfileSummaryInfoWrapperPass > ( ) ; AU . addRequired < LazyMachineBlockFrequencyInfoPass > ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> OperandMatchResultTy PPCAsmParser :: tryParseRegister ( unsigned & RegNo , SMLoc & StartLoc , SMLoc & EndLoc ) { const AsmToken & Tok = getParser ( ) . getTok ( ) ; StartLoc = Tok . getLoc ( ) ; EndLoc = Tok . getEndLoc ( ) ; RegNo = 0 ; int64_t IntVal ; if ( MatchRegisterName ( RegNo , IntVal ) ) return MatchOperand_NoMatch ; return MatchOperand_Success ; } </s>

tryParseRegister - parse one register if possible


<s> bool GCNPreRAOptimizations :: runOnMachineFunction ( MachineFunction & MF ) { if ( skipFunction ( MF . getFunction ( ) ) ) return false ; const GCNSubtarget & ST = MF . getSubtarget < GCNSubtarget > ( ) ; TII = ST . getInstrInfo ( ) ; MRI = & MF . getRegInfo ( ) ; LIS = & getAnalysis < LiveIntervals > ( ) ; TRI = ST . getRegisterInfo ( ) ; bool Changed = false ; for ( unsigned I = 0 , E = MRI -> getNumVirtRegs ( ) ; I != E ; ++ I ) { Register Reg = Register :: index2VirtReg ( I ) ; if ( ! LIS -> hasInterval ( Reg ) ) continue ; const TargetRegisterClass * RC = MRI -> getRegClass ( Reg ) ; if ( ( RC -> MC -> getSizeInBits ( ) != 64 || ! TRI -> isSGPRClass ( RC ) ) && ( ST . hasGFX90AInsts ( ) || ! TRI -> isAGPRClass ( RC ) ) ) continue ; Changed |= processReg ( Reg ) ; } return Changed ; } </s>


<s> bool X86IndirectBranchTrackingPass :: runOnMachineFunction ( MachineFunction & MF ) { const X86Subtarget & SubTarget = MF . getSubtarget < X86Subtarget > ( ) ; Metadata * isCFProtectionSupported = MF . getMMI ( ) . getModule ( ) -> getModuleFlag ( "cf-protection-branch" ) ; if ( ! isCFProtectionSupported && ! IndirectBranchTracking ) return false ; bool Changed = false ; TII = SubTarget . getInstrInfo ( ) ; EndbrOpcode = SubTarget . is64Bit ( ) ? X86 :: ENDBR64 : X86 :: ENDBR32 ; if ( ( MF . getFunction ( ) . hasAddressTaken ( ) || ! MF . getFunction ( ) . hasLocalLinkage ( ) ) && ! MF . getFunction ( ) . doesNoCfCheck ( ) ) { auto MBB = MF . begin ( ) ; Changed |= addENDBR ( * MBB ) ; } for ( auto & MBB : MF ) if ( MBB . hasAddressTaken ( ) ) Changed |= addENDBR ( MBB ) ; return Changed ; } </s>


Add common target configurable passes that perform LLVM IR to IR transforms following machine independent optimization .


<s> bool ARMPagerandoOptimizer :: runOnMachineFunction ( MachineFunction & MF ) { auto & F = MF . getFunction ( ) ; if ( ! F . isPagerando ( ) || skipFunction ( F ) ) { return false ; } auto BinPrefix = F . getSectionPrefix ( ) . getValue ( ) ; auto & CPEntries = MF . getConstantPool ( ) -> getConstants ( ) ; SmallSet < int , 8 > CPIndices ; int Index = 0 ; for ( auto & E : CPEntries ) { if ( isIntraBin ( E , BinPrefix ) ) CPIndices . insert ( Index ) ; Index ++ ; } if ( CPIndices . empty ( ) ) return false ; std :: vector < MachineInstr * > Uses ; for ( auto & BB : MF ) { for ( auto & MI : BB ) { int Index = getCPIndex ( MI ) ; if ( CPIndices . count ( Index ) ) Uses . push_back ( & MI ) ; } } for ( auto * MI : Uses ) { int Index = getCPIndex ( * MI ) ; auto * Callee = getCallee ( CPEntries [ Index ] ) ; optimizeCalls ( MI , Callee ) ; } deleteCPEntries ( MF , CPIndices ) ; return true ; } </s>


<s> SDValue R600TargetLowering :: LowerFormalArguments ( SDValue Chain , CallingConv :: ID CallConv , bool isVarArg , const SmallVectorImpl < ISD :: InputArg > & Ins , SDLoc DL , SelectionDAG & DAG , SmallVectorImpl < SDValue > & InVals ) const { SmallVector < CCValAssign , 16 > ArgLocs ; CCState CCInfo ( CallConv , isVarArg , DAG . getMachineFunction ( ) , ArgLocs , * DAG . getContext ( ) ) ; MachineFunction & MF = DAG . getMachineFunction ( ) ; unsigned ShaderType = MF . getInfo < R600MachineFunctionInfo > ( ) -> getShaderType ( ) ; SmallVector < ISD :: InputArg , 8 > LocalIns ; getOriginalFunctionArgs ( DAG , MF . getFunction ( ) , Ins , LocalIns ) ; AnalyzeFormalArguments ( CCInfo , LocalIns ) ; for ( unsigned i = 0 , e = Ins . size ( ) ; i < e ; ++ i ) { CCValAssign & VA = ArgLocs [ i ] ; const ISD :: InputArg & In = Ins [ i ] ; EVT VT = In . VT ; EVT MemVT = VA . getLocVT ( ) ; if ( ! VT . isVector ( ) && MemVT . isVector ( ) ) { MemVT = MemVT . getVectorElementType ( ) ; } if ( ShaderType != ShaderType :: COMPUTE ) { unsigned Reg = MF . addLiveIn ( VA . getLocReg ( ) , & AMDGPU :: R600_Reg128RegClass ) ; SDValue Register = DAG . getCopyFromReg ( Chain , DL , Reg , VT ) ; InVals . push_back ( Register ) ; continue ; } PointerType * PtrTy = PointerType :: get ( VT . getTypeForEVT ( * DAG . getContext ( ) ) , AMDGPUAS :: CONSTANT_BUFFER_0 ) ; ISD :: LoadExtType Ext = ISD :: NON_EXTLOAD ; if ( MemVT . getScalarSizeInBits ( ) != VT . getScalarSizeInBits ( ) ) { Ext = ISD :: SEXTLOAD ; } unsigned ValBase = ArgLocs [ In . OrigArgIndex ] . getLocMemOffset ( ) ; unsigned PartOffset = VA . getLocMemOffset ( ) ; MachinePointerInfo PtrInfo ( UndefValue :: get ( PtrTy ) , PartOffset - ValBase ) ; SDValue Arg = DAG . getLoad ( ISD :: UNINDEXED , Ext , VT , DL , Chain , DAG . getConstant ( 36 + PartOffset , MVT :: i32 ) , DAG . getUNDEF ( MVT :: i32 ) , PtrInfo , MemVT , false , true , true , 4 ) ; InVals . push_back ( Arg ) ; } return Chain ; } </s>

This hook must be implemented to lower the incoming ( formal ) arguments , described by the Ins array , into the specified DAG .


<s> void ia64_expand_call ( rtx retval , rtx addr , rtx nextarg ATTRIBUTE_UNUSED , int sibcall_p ) { rtx insn , b0 ; addr = XEXP ( addr , 0 ) ; addr = convert_memory_address ( DImode , addr ) ; b0 = gen_rtx_REG ( DImode , R_BR ( 0 ) ) ; if ( TARGET_NO_PIC || TARGET_AUTO_PIC ) { if ( sibcall_p ) insn = gen_sibcall_nogp ( addr ) ; else if ( ! retval ) insn = gen_call_nogp ( addr , b0 ) ; else insn = gen_call_value_nogp ( retval , addr , b0 ) ; insn = emit_call_insn ( insn ) ; } else { if ( sibcall_p ) insn = gen_sibcall_gp ( addr ) ; else if ( ! retval ) insn = gen_call_gp ( addr , b0 ) ; else insn = gen_call_value_gp ( retval , addr , b0 ) ; insn = emit_call_insn ( insn ) ; use_reg ( & CALL_INSN_FUNCTION_USAGE ( insn ) , pic_offset_table_rtx ) ; } if ( sibcall_p ) use_reg ( & CALL_INSN_FUNCTION_USAGE ( insn ) , b0 ) ; if ( TARGET_ABI_OPEN_VMS ) use_reg ( & CALL_INSN_FUNCTION_USAGE ( insn ) , gen_rtx_REG ( DImode , GR_REG ( 25 ) ) ) ; } </s>

Emit the appropriate sequence for a call .


<s> void SIRegisterInfo :: materializeFrameBaseRegister ( MachineBasicBlock * MBB , unsigned BaseReg , int FrameIdx , int64_t Offset ) const { MachineBasicBlock :: iterator Ins = MBB -> begin ( ) ; DebugLoc DL ; if ( Ins != MBB -> end ( ) ) DL = Ins -> getDebugLoc ( ) ; MachineFunction * MF = MBB -> getParent ( ) ; const GCNSubtarget & Subtarget = MF -> getSubtarget < GCNSubtarget > ( ) ; const SIInstrInfo * TII = Subtarget . getInstrInfo ( ) ; if ( Offset == 0 ) { BuildMI ( * MBB , Ins , DL , TII -> get ( AMDGPU :: V_MOV_B32_e32 ) , BaseReg ) . addFrameIndex ( FrameIdx ) ; return ; } MachineRegisterInfo & MRI = MF -> getRegInfo ( ) ; unsigned OffsetReg = MRI . createVirtualRegister ( & AMDGPU :: SReg_32_XM0RegClass ) ; unsigned FIReg = MRI . createVirtualRegister ( & AMDGPU :: VGPR_32RegClass ) ; BuildMI ( * MBB , Ins , DL , TII -> get ( AMDGPU :: S_MOV_B32 ) , OffsetReg ) . addImm ( Offset ) ; BuildMI ( * MBB , Ins , DL , TII -> get ( AMDGPU :: V_MOV_B32_e32 ) , FIReg ) . addFrameIndex ( FrameIdx ) ; TII -> getAddNoCarry ( * MBB , Ins , DL , BaseReg ) . addReg ( OffsetReg , RegState :: Kill ) . addReg ( FIReg ) . addImm ( 0 ) ; } </s>

Insert defining instruction ( s ) for a pointer to FrameIdx before insertion point I .


<s> unsigned char PPCSubtarget :: classifyGlobalReference ( const GlobalValue * GV ) const { if ( TM . getCodeModel ( ) == CodeModel :: Large ) return PPCII :: MO_PIC_FLAG | PPCII :: MO_NLP_FLAG ; unsigned char flags = PPCII :: MO_PIC_FLAG ; if ( TM . getRelocationModel ( ) == Reloc :: PIC_ ) { if ( ! GV -> hasLocalLinkage ( ) && GV -> hasDefaultVisibility ( ) ) { flags |= PPCII :: MO_NLP_FLAG ; } return flags ; } if ( GV -> isStrongDefinitionForLinker ( ) ) return flags ; return flags | PPCII :: MO_NLP_FLAG ; } </s>

Classify a global variable reference for the current subtarget according to how we should reference it in a non-pcrel context .


<s> SDValue getMergeValues ( ArrayRef < SDValue > Values ) const { return DAG . getMergeValues ( Values , DL ) ; } </s>


<s> bool RISCVAsmPrinter :: PrintAsmMemoryOperand ( const MachineInstr * MI , unsigned OpNo , const char * ExtraCode , raw_ostream & OS ) { if ( ! ExtraCode ) { const MachineOperand & MO = MI -> getOperand ( OpNo ) ; if ( ! MO . isReg ( ) ) return true ; OS << "0(" << RISCVInstPrinter :: getRegisterName ( MO . getReg ( ) ) << ")" ; return false ; } return AsmPrinter :: PrintAsmMemoryOperand ( MI , OpNo , ExtraCode , OS ) ; } </s>

Print the specified operand of MI , an INLINEASM instruction , using the specified assembler variant as an address .


<s> RISCVTargetLowering :: ConstraintType RISCVTargetLowering :: getConstraintType ( StringRef Constraint ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { case 'A' : return C_Memory ; default : break ; } } return TargetLowering :: getConstraintType ( Constraint ) ; } </s>

Given a constraint letter , return the type of constraint for this target .


"control register number must be in range 0-31 for %s"


<s> unsigned AArch64Subtarget :: classifyGlobalFunctionReference ( const GlobalValue * GV , const TargetMachine & TM ) const { if ( TM . getCodeModel ( ) == CodeModel :: Large && isTargetMachO ( ) && ! GV -> hasInternalLinkage ( ) ) return AArch64II :: MO_GOT ; auto * F = dyn_cast < Function > ( GV ) ; if ( UseNonLazyBind && F && F -> hasFnAttribute ( Attribute :: NonLazyBind ) && ! TM . shouldAssumeDSOLocal ( * GV -> getParent ( ) , GV ) ) return AArch64II :: MO_GOT ; if ( getTargetTriple ( ) . isOSWindows ( ) ) return ClassifyGlobalReference ( GV , TM ) ; return AArch64II :: MO_NO_FLAG ; } </s>

Classify a global function reference for the current subtarget .


<s>
bool
X86IntelAsmPrinter
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
this
->
MF
=
&
MF
;
SetupMachineFunction
(
MF
)
;
O
<<
"\n\n"
;
EmitConstantPool
(
MF
.
getConstantPool
(
)
)
;
const
Function
*
F
=
MF
.
getFunction
(
)
;
unsigned
CC
=
F
->
getCallingConv
(
)
;
unsigned
FnAlign
=
MF
.
getAlignment
(
)
;
if
(
CC
==
CallingConv
::
X86_StdCall
||
CC
==
CallingConv
::
X86_FastCall
)
FunctionInfoMap
[
F
]
=
*
MF
.
getInfo
<
X86MachineFunctionInfo
>
(
)
;
decorateName
(
CurrentFnName
,
F
)
;
OutStreamer
.
SwitchSection
(
getObjFileLowering
(
)
.
SectionForGlobal
(
F
,
Mang
,
TM
)
)
;
switch
(
F
->
getLinkage
(
)
)
{
default
:
llvm_unreachable
(
"Unsupported linkage type!"
)
;
case
Function
::
PrivateLinkage
:
case
Function
::
LinkerPrivateLinkage
:
case
Function
::
InternalLinkage
:
EmitAlignment
(
FnAlign
)
;
break
;
case
Function
::
DLLExportLinkage
:
DLLExportedFns
.
insert
(
CurrentFnName
)
;
case
Function
::
ExternalLinkage
:
O
<<
"\tpublic "
<<
CurrentFnName
<<
"\n"
;
EmitAlignment
(
FnAlign
)
;
break
;
}
O
<<
CurrentFnName
<<
"\tproc near\n"
;
for
(
MachineFunction
::
const_iterator
I
=
MF
.
begin
(
)
,
E
=
MF
.
end
(
)
;
I
!=
E
;
++
I
)
{
if
(
!
I
->
pred_empty
(
)
)
{
printBasicBlockLabel
(
I
,
true
,
true
)
;
O
<<
'\n'
;
}
for
(
MachineBasicBlock
::
const_iterator
II
=
I
->
begin
(
)
,
E
=
I
->
end
(
)
;
II
!=
E
;
++
II
)
{
printMachineInstruction
(
II
)
;
}
}
EmitJumpTableInfo
(
MF
.
getJumpTableInfo
(
)
,
MF
)
;
O
<<
CurrentFnName
<<
"\tendp\n"
;
return
false
;
}
</s>

runOnMachineFunction - Emit the function body .


<s> static rtx ix86_expand_binop_builtin ( enum insn_code icode , tree arglist , rtx target ) { rtx pat , xops [ 3 ] ; tree arg0 = TREE_VALUE ( arglist ) ; tree arg1 = TREE_VALUE ( TREE_CHAIN ( arglist ) ) ; rtx op0 = expand_expr ( arg0 , NULL_RTX , VOIDmode , 0 ) ; rtx op1 = expand_expr ( arg1 , NULL_RTX , VOIDmode , 0 ) ; enum machine_mode tmode = insn_data [ icode ] . operand [ 0 ] . mode ; enum machine_mode mode0 = insn_data [ icode ] . operand [ 1 ] . mode ; enum machine_mode mode1 = insn_data [ icode ] . operand [ 2 ] . mode ; if ( VECTOR_MODE_P ( mode0 ) ) op0 = safe_vector_operand ( op0 , mode0 ) ; if ( VECTOR_MODE_P ( mode1 ) ) op1 = safe_vector_operand ( op1 , mode1 ) ; if ( optimize || ! target || GET_MODE ( target ) != tmode || ! ( * insn_data [ icode ] . operand [ 0 ] . predicate ) ( target , tmode ) ) target = gen_reg_rtx ( tmode ) ; if ( GET_MODE ( op1 ) == SImode && mode1 == TImode ) { rtx x = gen_reg_rtx ( V4SImode ) ; emit_insn ( gen_sse2_loadd ( x , op1 ) ) ; op1 = gen_lowpart ( TImode , x ) ; } gcc_assert ( ( GET_MODE ( op0 ) == mode0 || GET_MODE ( op0 ) == VOIDmode ) && ( GET_MODE ( op1 ) == mode1 || GET_MODE ( op1 ) == VOIDmode ) ) ; if ( ! ( * insn_data [ icode ] . operand [ 1 ] . predicate ) ( op0 , mode0 ) ) op0 = copy_to_mode_reg ( mode0 , op0 ) ; if ( ! ( * insn_data [ icode ] . operand [ 2 ] . predicate ) ( op1 , mode1 ) ) op1 = copy_to_mode_reg ( mode1 , op1 ) ; xops [ 0 ] = target ; xops [ 1 ] = op0 ; xops [ 2 ] = op1 ; if ( tmode == mode0 && tmode == mode1 ) { target = ix86_fixup_binary_operands ( UNKNOWN , tmode , xops ) ; op0 = xops [ 1 ] ; op1 = xops [ 2 ] ; } else if ( optimize || ! ix86_binary_operator_ok ( UNKNOWN , tmode , xops ) ) { op0 = force_reg ( mode0 , op0 ) ; op1 = force_reg ( mode1 , op1 ) ; target = gen_reg_rtx ( tmode ) ; } pat = GEN_FCN ( icode ) ( target , op0 , op1 ) ; if ( ! pat ) return 0 ; emit_insn ( pat ) ; return target ; } </s>

Subroutine of ix86_expand_builtin to take care of binop insns .


"-fstack-check=specific not implemented for MIPS16"

Emit code to probe a range of stack addresses from FIRST to FIRST+SIZE , inclusive . These are offsets from the current stack pointer .


<s>
StringRef
getPassName
(
)
const
override
{
return
"WebAssembly Prepare For LiveIntervals"
;
}
</s>

getPassName - Return a nice clean name for a pass .

WebAssembly
"WebAssembly Prepare For LiveIntervals"


<s> bool isLegalMaskedScatter ( Type * Ty , Align Alignment ) { return isLegalMaskedGather ( Ty , Alignment ) ; } </s>

Return true if the target supports masked scatter .


<s> bool Thumb2InstrInfo :: isLegalToSplitMBBAt ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI ) const { while ( MBBI -> isDebugValue ( ) ) { ++ MBBI ; if ( MBBI == MBB . end ( ) ) return false ; } unsigned PredReg = 0 ; return getITInstrPredicate ( * MBBI , PredReg ) == ARMCC :: AL ; } </s>

Return true if it 's legal to split the given basic block at the specified instruction ( i.e .


Return a mask for the call-clobbered low registers that are unused at the end of the prologue .


<s> bool MSP430DAGToDAGISel :: runOnMachineFunction ( MachineFunction & MF ) { Subtarget = & MF . getSubtarget < MSP430Subtarget > ( ) ; return SelectionDAGISel :: runOnMachineFunction ( MF ) ; } </s>


<s> SDValue AMDGPUTargetLowering :: SplitVectorStore ( SDValue Op , SelectionDAG & DAG ) const { StoreSDNode * Store = cast < StoreSDNode > ( Op ) ; SDValue Val = Store -> getValue ( ) ; EVT VT = Val . getValueType ( ) ; if ( VT . getVectorNumElements ( ) == 2 ) return ScalarizeVectorStore ( Op , DAG ) ; EVT MemVT = Store -> getMemoryVT ( ) ; SDValue Chain = Store -> getChain ( ) ; SDValue BasePtr = Store -> getBasePtr ( ) ; SDLoc SL ( Op ) ; EVT LoVT , HiVT ; EVT LoMemVT , HiMemVT ; SDValue Lo , Hi ; std :: tie ( LoVT , HiVT ) = DAG . GetSplitDestVTs ( VT ) ; std :: tie ( LoMemVT , HiMemVT ) = DAG . GetSplitDestVTs ( MemVT ) ; std :: tie ( Lo , Hi ) = DAG . SplitVector ( Val , SL , LoVT , HiVT ) ; EVT PtrVT = BasePtr . getValueType ( ) ; SDValue HiPtr = DAG . getNode ( ISD :: ADD , SL , PtrVT , BasePtr , DAG . getConstant ( LoMemVT . getStoreSize ( ) , SL , PtrVT ) ) ; MachinePointerInfo SrcValue ( Store -> getMemOperand ( ) -> getValue ( ) ) ; SDValue LoStore = DAG . getTruncStore ( Chain , SL , Lo , BasePtr , SrcValue , LoMemVT , Store -> isNonTemporal ( ) , Store -> isVolatile ( ) , Store -> getAlignment ( ) ) ; SDValue HiStore = DAG . getTruncStore ( Chain , SL , Hi , HiPtr , SrcValue . getWithOffset ( LoMemVT . getStoreSize ( ) ) , HiMemVT , Store -> isNonTemporal ( ) , Store -> isVolatile ( ) , Store -> getAlignment ( ) ) ; return DAG . getNode ( ISD :: TokenFactor , SL , MVT :: Other , LoStore , HiStore ) ; } </s>

Split a vector store into 2 stores of half the vector .


<s>
CCAssignFn
*
XtensaTargetLowering
::
CCAssignFnForCall
(
CallingConv
::
ID
CC
,
bool
IsVarArg
)
const
{
assert
(
!
IsVarArg
&&
"We don't support variadic arguments"
)
;
return
CC_Xtensa
;
}
</s>

Selects the correct CCAssignFn for a given CallingConvention value .

Xtensa
Xtensa
"We don't support variadic arguments"
Xtensa


<s> unsigned PPCRegisterInfo :: getRegPressureLimit ( const TargetRegisterClass * RC , MachineFunction & MF ) const { const PPCSubtarget & Subtarget = MF . getSubtarget < PPCSubtarget > ( ) ; const TargetFrameLowering * TFI = Subtarget . getFrameLowering ( ) ; const unsigned DefaultSafety = 1 ; switch ( RC -> getID ( ) ) { default : return 0 ; case PPC :: G8RC_NOX0RegClassID : case PPC :: GPRC_NOR0RegClassID : case PPC :: G8RCRegClassID : case PPC :: GPRCRegClassID : { unsigned FP = TFI -> hasFP ( MF ) ? 1 : 0 ; return 32 - FP - DefaultSafety ; } case PPC :: F8RCRegClassID : case PPC :: F4RCRegClassID : case PPC :: QFRCRegClassID : case PPC :: QSRCRegClassID : case PPC :: QBRCRegClassID : case PPC :: VRRCRegClassID : case PPC :: VFRCRegClassID : case PPC :: VSLRCRegClassID : case PPC :: VSHRCRegClassID : return 32 - DefaultSafety ; case PPC :: VSRCRegClassID : case PPC :: VSFRCRegClassID : case PPC :: VSSRCRegClassID : return 64 - DefaultSafety ; case PPC :: CRRCRegClassID : return 8 - DefaultSafety ; } } </s>

Return the register pressure `` high water mark '' for the specific register class .


<s> static bool nios2_r0rel_section_name_p ( const char * section ) { return ( nios2_r0rel_sec && regexec ( & nios2_r0rel_sec_regex , section , 0 , NULL , 0 ) == 0 ) ; } </s>

Return true if SECTION is a r0-relative section name .


<s> static void ia64_setup_incoming_varargs ( cumulative_args_t cum , const function_arg_info & arg , int * pretend_size , int second_time ATTRIBUTE_UNUSED ) { CUMULATIVE_ARGS next_cum = * get_cumulative_args ( cum ) ; ia64_function_arg_advance ( pack_cumulative_args ( & next_cum ) , arg ) ; if ( next_cum . words < MAX_ARGUMENT_SLOTS ) { int n = MAX_ARGUMENT_SLOTS - next_cum . words ; * pretend_size = n * UNITS_PER_WORD ; cfun -> machine -> n_varargs = n ; } } </s>

Do any needed setup for a variadic function . CUM has not been updated for the last named argument which has type TYPE and mode MODE . We generate the actual spill instructions during prologue generation .


<s> bool AArch64InstrInfo :: isQForm ( const MachineInstr & MI ) { auto IsQFPR = [ & ] ( const MachineOperand & Op ) { if ( ! Op . isReg ( ) ) return false ; auto Reg = Op . getReg ( ) ; if ( Reg . isPhysical ( ) ) return AArch64 :: FPR128RegClass . contains ( Reg ) ; const TargetRegisterClass * TRC = :: getRegClass ( MI , Reg ) ; return TRC == & AArch64 :: FPR128RegClass || TRC == & AArch64 :: FPR128_loRegClass ; } ; return llvm :: any_of ( MI . operands ( ) , IsQFPR ) ; } </s>

Returns whether the instruction is in Q form ( 128 bit operands )


"option %s is not supported together with -fopenacc"

Issue a diagnostic when option OPTNAME is enabled ( as indicated by OPTVAL ) and -fopenacc is also enabled .


<s> bool HexagonTargetMachine :: addPreEmitPass ( PassManagerBase & PM ) { if ( ! DisableHardwareLoops ) { PM . add ( createHexagonFixupHwLoops ( ) ) ; } PM . add ( createHexagonExpandPredSpillCode ( * this ) ) ; PM . add ( createHexagonSplitTFRCondSets ( * this ) ) ; return false ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s> ARMSubtarget :: ARMSubtarget ( const std :: string & TT , const std :: string & CPU , const std :: string & FS ) : ARMGenSubtargetInfo ( TT , CPU , FS ) , ARMProcFamily ( Others ) , HasV4TOps ( false ) , HasV5TOps ( false ) , HasV5TEOps ( false ) , HasV6Ops ( false ) , HasV6T2Ops ( false ) , HasV7Ops ( false ) , HasVFPv2 ( false ) , HasVFPv3 ( false ) , HasVFPv4 ( false ) , HasNEON ( false ) , HasNEONVFPv4 ( false ) , UseNEONForSinglePrecisionFP ( false ) , SlowFPVMLx ( false ) , HasVMLxForwarding ( false ) , SlowFPBrcc ( false ) , InThumbMode ( false ) , HasThumb2 ( false ) , IsMClass ( false ) , NoARM ( false ) , PostRAScheduler ( false ) , IsR9Reserved ( ReserveR9 ) , UseMovt ( false ) , SupportsTailCall ( false ) , HasFP16 ( false ) , HasD16 ( false ) , HasHardwareDivide ( false ) , HasT2ExtractPack ( false ) , HasDataBarrier ( false ) , Pref32BitThumb ( false ) , AvoidCPSRPartialUpdate ( false ) , HasMPExtension ( false ) , FPOnlySP ( false ) , AllowsUnalignedMem ( false ) , Thumb2DSP ( false ) , stackAlignment ( 4 ) , CPUString ( CPU ) , TargetTriple ( TT ) , TargetABI ( ARM_ABI_APCS ) { if ( CPUString . empty ( ) ) CPUString = "generic" ; std :: string ArchFS = ARM_MC :: ParseARMTriple ( TT ) ; if ( ! FS . empty ( ) ) { if ( ! ArchFS . empty ( ) ) ArchFS = ArchFS + "," + FS ; else ArchFS = FS ; } ParseSubtargetFeatures ( CPUString , ArchFS ) ; if ( ! HasV6T2Ops && hasThumb2 ( ) ) HasV4TOps = HasV5TOps = HasV5TEOps = HasV6Ops = HasV6T2Ops = true ; InstrItins = getInstrItineraryForCPU ( CPUString ) ; computeIssueWidth ( ) ; if ( TT . find ( "eabi" ) != std :: string :: npos ) TargetABI = ARM_ABI_AAPCS ; if ( isAAPCS_ABI ( ) ) stackAlignment = 8 ; if ( ! isTargetIOS ( ) ) UseMovt = hasV6T2Ops ( ) ; else { IsR9Reserved = ReserveR9 | ! HasV6Ops ; UseMovt = DarwinUseMOVT && hasV6T2Ops ( ) ; const Triple & T = getTargetTriple ( ) ; SupportsTailCall = ! T . isOSVersionLT ( 5 , 0 ) ; } if ( ! isThumb ( ) || hasThumb2 ( ) ) PostRAScheduler = true ; if ( ! StrictAlign && hasV6Ops ( ) && isTargetDarwin ( ) ) AllowsUnalignedMem = true ; } </s>

This constructor initializes the data members to match that of the specified triple .

ARM ARM ARM ARM ARM ARM 4 ARM "generic" ARM ARM "," "eabi" ARM 8 5 0


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . setPreservesCFG ( ) ; AU . addRequired < DominatorTreeWrapperPass > ( ) ; AU . addPreserved < DominatorTreeWrapperPass > ( ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> void XCoreInstrInfo :: loadRegFromStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned DestReg , int FrameIndex , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { DebugLoc DL ; if ( I != MBB . end ( ) && ! I -> isDebugInstr ( ) ) DL = I -> getDebugLoc ( ) ; MachineFunction * MF = MBB . getParent ( ) ; const MachineFrameInfo & MFI = MF -> getFrameInfo ( ) ; MachineMemOperand * MMO = MF -> getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( * MF , FrameIndex ) , MachineMemOperand :: MOLoad , MFI . getObjectSize ( FrameIndex ) , MFI . getObjectAlignment ( FrameIndex ) ) ; BuildMI ( MBB , I , DL , get ( XCore :: LDWFI ) , DestReg ) . addFrameIndex ( FrameIndex ) . addImm ( 0 ) . addMemOperand ( MMO ) ; } </s>

Load the specified register of the given register class from the specified stack frame index .


<s> void AMDGPUFrameLowering :: emitPrologue ( MachineFunction & MF , MachineBasicBlock & MBB ) const { } </s>

emitProlog/emitEpilog - These methods insert prolog and epilog code into the function .


<s>
SDValue
RISCVTargetLowering
::
LowerReturn
(
SDValue
Chain
,
CallingConv
::
ID
CallConv
,
bool
IsVarArg
,
const
SmallVectorImpl
<
ISD
::
OutputArg
>
&
Outs
,
const
SmallVectorImpl
<
SDValue
>
&
OutVals
,
const
SDLoc
&
DL
,
SelectionDAG
&
DAG
)
const
{
SmallVector
<
CCValAssign
,
16
>
RVLocs
;
CCState
CCInfo
(
CallConv
,
IsVarArg
,
DAG
.
getMachineFunction
(
)
,
RVLocs
,
*
DAG
.
getContext
(
)
)
;
analyzeOutputArgs
(
DAG
.
getMachineFunction
(
)
,
CCInfo
,
Outs
,
true
,
nullptr
)
;
SDValue
Flag
;
SmallVector
<
SDValue
,
4
>
RetOps
(
1
,
Chain
)
;
for
(
unsigned
i
=
0
,
e
=
RVLocs
.
size
(
)
;
i
<
e
;
++
i
)
{
SDValue
Val
=
OutVals
[
i
]
;
CCValAssign
&
VA
=
RVLocs
[
i
]
;
assert
(
VA
.
isRegLoc
(
)
&&
"Can only return in registers!"
)
;
Val
=
packIntoRegLoc
(
DAG
,
Val
,
VA
,
DL
)
;
Chain
=
DAG
.
getCopyToReg
(
Chain
,
DL
,
VA
.
getLocReg
(
)
,
Val
,
Flag
)
;
Flag
=
Chain
.
getValue
(
1
)
;
RetOps
.
push_back
(
DAG
.
getRegister
(
VA
.
getLocReg
(
)
,
VA
.
getLocVT
(
)
)
)
;
}
RetOps
[
0
]
=
Chain
;
if
(
Flag
.
getNode
(
)
)
{
RetOps
.
push_back
(
Flag
)
;
}
return
DAG
.
getNode
(
RISCVISD
::
RET_FLAG
,
DL
,
MVT
::
Other
,
RetOps
)
;
}
</s>

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .


<s> bool X86TargetMachine :: addInstSelector ( PassManagerBase & PM , CodeGenOpt :: Level OptLevel ) { PM . add ( createX86ISelDag ( * this , OptLevel ) ) ; if ( ! Subtarget . is64Bit ( ) ) PM . add ( createGlobalBaseRegPass ( ) ) ; return false ; } </s>

addInstSelector - This method should install an instruction selector pass , which converts from LLVM code to machine instructions .


<s> static void nvptx_reorg ( void ) { compute_bb_for_insn ( ) ; thread_prologue_and_epilogue_insns ( ) ; bb_insn_map_t bb_insn_map ; nvptx_split_blocks ( & bb_insn_map ) ; df_clear_flags ( DF_LR_RUN_DCE ) ; df_set_flags ( DF_NO_INSN_RESCAN | DF_NO_HARD_REGS ) ; df_live_add_problem ( ) ; df_live_set_all_dirty ( ) ; df_analyze ( ) ; regstat_init_n_sets_and_refs ( ) ; if ( dump_file ) df_dump ( dump_file ) ; int max_regs = max_reg_num ( ) ; for ( int i = LAST_VIRTUAL_REGISTER + 1 ; i < max_regs ; i ++ ) if ( REG_N_SETS ( i ) == 0 && REG_N_REFS ( i ) == 0 ) regno_reg_rtx [ i ] = const0_rtx ; tree attr = oacc_get_fn_attrib ( current_function_decl ) ; if ( attr ) { unsigned mask = 0 ; tree dims = TREE_VALUE ( attr ) ; unsigned ix ; for ( ix = 0 ; ix != GOMP_DIM_MAX ; ix ++ , dims = TREE_CHAIN ( dims ) ) { int size = TREE_INT_CST_LOW ( TREE_VALUE ( dims ) ) ; tree allowed = TREE_PURPOSE ( dims ) ; if ( size != 1 && ! ( allowed && integer_zerop ( allowed ) ) ) mask |= GOMP_DIM_MASK ( ix ) ; } gcc_assert ( ! ( mask & GOMP_DIM_MASK ( GOMP_DIM_WORKER ) ) || ( mask & GOMP_DIM_MASK ( GOMP_DIM_VECTOR ) ) ) ; parallel * pars = nvptx_discover_pars ( & bb_insn_map ) ; nvptx_process_pars ( pars ) ; nvptx_neuter_pars ( pars , mask , 0 ) ; delete pars ; } nvptx_reorg_subreg ( ) ; if ( TARGET_UNIFORM_SIMT ) nvptx_reorg_uniform_simt ( ) ; prevent_branch_around_nothing ( ) ; regstat_free_n_sets_and_refs ( ) ; df_finish_pass ( true ) ; } </s>

Clean up subreg operands . In ptx assembly , everything is typed , and the presence of subregs would break the rules for most instructions . Replace them with a suitable new register of the right size , plus conversion copyin/copyout instructions .


"X86-64 PIC uses RIP relative addressing"

getGlobalBaseReg - Return a virtual register initialized with the the global base register value .


<s> static void rs6000_emit_epilogue_components ( sbitmap components ) { rs6000_stack_t * info = rs6000_stack_info ( ) ; rtx ptr_reg = gen_rtx_REG ( Pmode , frame_pointer_needed ? HARD_FRAME_POINTER_REGNUM : STACK_POINTER_REGNUM ) ; machine_mode reg_mode = Pmode ; int reg_size = TARGET_32BIT ? 4 : 8 ; machine_mode fp_reg_mode = ( TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT ) ? DFmode : SFmode ; int fp_reg_size = 8 ; int offset = info -> fp_save_offset ; if ( info -> push_p ) offset += info -> total_size ; for ( int i = info -> first_fp_reg_save ; i < 64 ; i ++ ) { if ( bitmap_bit_p ( components , i ) ) { rtx reg = gen_rtx_REG ( fp_reg_mode , i ) ; rtx_insn * insn = emit_insn ( gen_frame_load ( reg , ptr_reg , offset ) ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; add_reg_note ( insn , REG_CFA_RESTORE , reg ) ; } offset += fp_reg_size ; } offset = info -> gp_save_offset ; if ( info -> push_p ) offset += info -> total_size ; for ( int i = info -> first_gp_reg_save ; i < 32 ; i ++ ) { if ( bitmap_bit_p ( components , i ) ) { rtx reg = gen_rtx_REG ( reg_mode , i ) ; rtx_insn * insn = emit_insn ( gen_frame_load ( reg , ptr_reg , offset ) ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; add_reg_note ( insn , REG_CFA_RESTORE , reg ) ; } offset += reg_size ; } if ( bitmap_bit_p ( components , 0 ) ) { int offset = info -> lr_save_offset ; if ( info -> push_p ) offset += info -> total_size ; rtx reg = gen_rtx_REG ( reg_mode , 0 ) ; rtx_insn * insn = emit_insn ( gen_frame_load ( reg , ptr_reg , offset ) ) ; rtx lr = gen_rtx_REG ( Pmode , LR_REGNO ) ; insn = emit_move_insn ( lr , reg ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; add_reg_note ( insn , REG_CFA_RESTORE , lr ) ; } } </s>


<s> int m32c_print_operand_punct_valid_p ( int c ) { if ( c == '&' || c == '!' ) return 1 ; return 0 ; } </s>

Implements PRINT_OPERAND_PUNCT_VALID_P . See m32c_print_operand above for descriptions of what these do .


"Slot for FP register must be last in order to be found!"

processFunctionBeforeFrameFinalized - This method is called immediately before the specified function 's frame layout ( MF.getFrameInfo ( ) ) is finalized .


<s> void HexagonTargetLowering :: ReplaceNodeResults ( SDNode * N , SmallVectorImpl < SDValue > & Results , SelectionDAG & DAG ) const { const SDLoc & dl ( N ) ; switch ( N -> getOpcode ( ) ) { case ISD :: SRL : case ISD :: SRA : case ISD :: SHL : return ; case ISD :: BITCAST : if ( N -> getValueType ( 0 ) == MVT :: i8 ) { SDValue P = getInstr ( Hexagon :: C2_tfrpr , dl , MVT :: i32 , N -> getOperand ( 0 ) , DAG ) ; SDValue T = DAG . getAnyExtOrTrunc ( P , dl , MVT :: i8 ) ; Results . push_back ( T ) ; } break ; } } </s>

ReplaceNodeResults - Replace the results of node with an illegal result type with new values built out of custom code .


<s> bool valid_operands_ldrd_strd ( rtx * operands , bool load ) { int nops = 2 ; HOST_WIDE_INT offsets [ 2 ] , offset , align [ 2 ] ; rtx base = NULL_RTX ; rtx cur_base , cur_offset ; int i , gap ; for ( i = 0 ; i < nops ; i ++ ) { if ( ! mem_ok_for_ldrd_strd ( operands [ nops + i ] , & cur_base , & cur_offset , & align [ i ] ) ) return false ; if ( i == 0 ) base = cur_base ; else if ( REGNO ( base ) != REGNO ( cur_base ) ) return false ; offsets [ i ] = INTVAL ( cur_offset ) ; if ( GET_CODE ( operands [ i ] ) == SUBREG ) return false ; } if ( offsets [ 0 ] > offsets [ 1 ] ) return false ; gap = offsets [ 1 ] - offsets [ 0 ] ; offset = offsets [ 0 ] ; if ( gap != GET_MODE_SIZE ( SImode ) ) return false ; if ( ! align_ok_ldrd_strd ( align [ 0 ] , offset ) ) return false ; return operands_ok_ldrd_strd ( operands [ 0 ] , operands [ 1 ] , base , offset , false , load ) ; } </s>

Return true if parallel execution of the two word-size accesses provided could be satisfied with a single LDRD/STRD instruction . Two word-size accesses are represented by the OPERANDS array , where OPERANDS [ 0,1 ] are register operands and OPERANDS [ 2,3 ] are the corresponding memory operands .


"Found a PhiRef node as a real reached use!!"

processBlock - If there are any predecessors whose control can be threaded through to a successor , transform them now .


<s> bool XCoreFTAOElim :: runOnMachineFunction ( MachineFunction & MF ) { const XCoreInstrInfo & TII = * static_cast < const XCoreInstrInfo * > ( MF . getSubtarget ( ) . getInstrInfo ( ) ) ; unsigned StackSize = MF . getFrameInfo ( ) . getStackSize ( ) ; for ( MachineFunction :: iterator MFI = MF . begin ( ) , E = MF . end ( ) ; MFI != E ; ++ MFI ) { MachineBasicBlock & MBB = * MFI ; for ( MachineBasicBlock :: iterator MBBI = MBB . begin ( ) , EE = MBB . end ( ) ; MBBI != EE ; ++ MBBI ) { if ( MBBI -> getOpcode ( ) == XCore :: FRAME_TO_ARGS_OFFSET ) { MachineInstr & OldInst = * MBBI ; unsigned Reg = OldInst . getOperand ( 0 ) . getReg ( ) ; MBBI = TII . loadImmediate ( MBB , MBBI , Reg , StackSize ) ; OldInst . eraseFromParent ( ) ; } } } return true ; } </s>

runOnMachineFunction - Emit the function body .

XCore XCore XCore XCore XCore::FRAME_TO_ARGS_OFFSET 0


<s> static bool valid_sew_p ( size_t sew ) { return exact_log2 ( sew ) && sew >= 8 && sew <= 64 ; } </s>

Is this a SEW value that can be encoded into the VTYPE format .


<s> bool SVEExpandLibCall :: runOnFunction ( Function & F ) { this -> F = & F ; bool Changed = false ; SmallVector < Instruction * , 4 > VectorWorkList ; SmallVector < Instruction * , 4 > MemWorkList ; SmallVector < Instruction * , 4 > StructLoadWorkList ; SmallVector < Instruction * , 4 > StructStoreWorkList ; for ( auto I = inst_begin ( F ) , E = inst_end ( F ) ; I != E ; ++ I ) { if ( isVectorLibCall ( & * I ) ) VectorWorkList . push_back ( & * I ) ; else if ( isMemLibCall ( & * I ) ) MemWorkList . push_back ( & * I ) ; else if ( isStructMemOp < LoadInst > ( & * I ) ) StructLoadWorkList . push_back ( & * I ) ; else if ( isStructMemOp < StoreInst > ( & * I ) ) StructStoreWorkList . push_back ( & * I ) ; } for ( auto I : VectorWorkList ) Changed |= ExpandCallToLoop ( cast < IntrinsicInst > ( I ) ) ; for ( auto I : MemWorkList ) Changed |= ExpandMemCallToLoop ( cast < MemIntrinsic > ( I ) ) ; for ( auto I : StructLoadWorkList ) Changed |= ExpandStructLoad ( cast < LoadInst > ( I ) ) ; for ( auto I : StructStoreWorkList ) Changed |= ExpandStructStore ( cast < StoreInst > ( I ) ) ; return Changed ; } </s>

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .


<s> void Warning ( SMLoc L , const Twine & Msg ) { Parser . Warning ( L , Msg ) ; } </s>

Emit a warning at the location L , with the message Msg .


<s> AArch64TargetMachine :: AArch64TargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , Optional < CodeModel :: Model > CM , CodeGenOpt :: Level OL , bool JIT , bool LittleEndian ) : LLVMTargetMachine ( T , computeDataLayout ( TT , Options . MCOptions , LittleEndian ) , TT , computeDefaultCPU ( TT , CPU ) , FS , Options , getEffectiveRelocModel ( TT , RM ) , getEffectiveAArch64CodeModel ( TT , CM , JIT ) , OL ) , TLOF ( createTLOF ( getTargetTriple ( ) ) ) , isLittle ( LittleEndian ) { initAsmInfo ( ) ; if ( TT . isOSBinFormatMachO ( ) ) { this -> Options . TrapUnreachable = true ; this -> Options . NoTrapAfterNoreturn = true ; } if ( getMCAsmInfo ( ) -> usesWindowsCFI ( ) ) { this -> Options . TrapUnreachable = true ; } if ( this -> Options . TLSSize == 0 ) this -> Options . TLSSize = 24 ; if ( ( getCodeModel ( ) == CodeModel :: Small || getCodeModel ( ) == CodeModel :: Kernel ) && this -> Options . TLSSize > 32 ) this -> Options . TLSSize = 32 ; else if ( getCodeModel ( ) == CodeModel :: Tiny && this -> Options . TLSSize > 24 ) this -> Options . TLSSize = 24 ; if ( getOptLevel ( ) <= EnableGlobalISelAtO && TT . getArch ( ) != Triple :: aarch64_32 && TT . getEnvironment ( ) != Triple :: GNUILP32 && ! ( getCodeModel ( ) == CodeModel :: Large && TT . isOSBinFormatMachO ( ) ) ) { setGlobalISel ( true ) ; setGlobalISelAbort ( GlobalISelAbortMode :: Disable ) ; } setMachineOutliner ( true ) ; setSupportsDefaultOutlining ( true ) ; setSupportsDebugEntryValues ( true ) ; if ( ! getMCAsmInfo ( ) -> usesWindowsCFI ( ) ) setCFIFixup ( true ) ; } </s>


"ARM hazards don't support scoreboard lookahead"

getHazardType - Return the hazard type of emitting this node .


<s> void m32c_init_expanders ( void ) { init_machine_status = m32c_init_machine_status ; } </s>

Implements INIT_EXPANDERS . We just set up to call the above function .


<s> bool X86EncodeLiteralsPass :: runOnMachineFunction ( MachineFunction & MF ) { bool Changed = false ; MRI = & MF . getRegInfo ( ) ; TII = MF . getSubtarget < X86Subtarget > ( ) . getInstrInfo ( ) ; TRI = MF . getSubtarget < X86Subtarget > ( ) . getRegisterInfo ( ) ; if ( ! EnableEncodeLiterals ) return false ; for ( auto & MBB : MF ) { unsigned Index = 0 ; for ( MachineBasicBlock :: iterator MI = MBB . begin ( ) , E = MBB . end ( ) ; MI != E ; ++ MI , ++ Index ) { if ( isStoreLocalValue ( * MI ) ) { obfuscateLiteralOperand ( MF , * MI , Index ) ; Changed = true ; } } } return Changed ; } </s>


<s>
MachineBasicBlock
*
MipsTargetLowering
::
EmitInstrWithCustomInserter
(
MachineInstr
*
MI
,
MachineBasicBlock
*
BB
)
const
{
const
TargetInstrInfo
*
TII
=
getTargetMachine
(
)
.
getInstrInfo
(
)
;
bool
isFPCmp
=
false
;
DebugLoc
dl
=
MI
->
getDebugLoc
(
)
;
switch
(
MI
->
getOpcode
(
)
)
{
default
:
assert
(
false
&&
"Unexpected instr type to insert"
)
;
case
Mips
::
Select_FCC
:
case
Mips
::
Select_FCC_S32
:
case
Mips
::
Select_FCC_D32
:
isFPCmp
=
true
;
case
Mips
::
Select_CC
:
case
Mips
::
Select_CC_S32
:
case
Mips
::
Select_CC_D32
:
{
const
BasicBlock
*
LLVM_BB
=
BB
->
getBasicBlock
(
)
;
MachineFunction
::
iterator
It
=
BB
;
++
It
;
MachineBasicBlock
*
thisMBB
=
BB
;
MachineFunction
*
F
=
BB
->
getParent
(
)
;
MachineBasicBlock
*
copy0MBB
=
F
->
CreateMachineBasicBlock
(
LLVM_BB
)
;
MachineBasicBlock
*
sinkMBB
=
F
->
CreateMachineBasicBlock
(
LLVM_BB
)
;
F
->
insert
(
It
,
copy0MBB
)
;
F
->
insert
(
It
,
sinkMBB
)
;
sinkMBB
->
splice
(
sinkMBB
->
begin
(
)
,
BB
,
llvm
::
next
(
MachineBasicBlock
::
iterator
(
MI
)
)
,
BB
->
end
(
)
)
;
sinkMBB
->
transferSuccessorsAndUpdatePHIs
(
BB
)
;
BB
->
addSuccessor
(
copy0MBB
)
;
BB
->
addSuccessor
(
sinkMBB
)
;
if
(
isFPCmp
)
{
Mips
::
CondCode
CC
=
(
Mips
::
CondCode
)
MI
->
getOperand
(
4
)
.
getImm
(
)
;
unsigned
Opc
=
FPBranchCodeToOpc
(
GetFPBranchCodeFromCond
(
CC
)
)
;
BuildMI
(
BB
,
dl
,
TII
->
get
(
Opc
)
)
.
addMBB
(
sinkMBB
)
;
}
else
BuildMI
(
BB
,
dl
,
TII
->
get
(
Mips
::
BNE
)
)
.
addReg
(
MI
->
getOperand
(
1
)
.
getReg
(
)
)
.
addReg
(
Mips
::
ZERO
)
.
addMBB
(
sinkMBB
)
;
BB
=
copy0MBB
;
BB
->
addSuccessor
(
sinkMBB
)
;
BB
=
sinkMBB
;
BuildMI
(
*
BB
,
BB
->
begin
(
)
,
dl
,
TII
->
get
(
Mips
::
PHI
)
,
MI
->
getOperand
(
0
)
.
getReg
(
)
)
.
addReg
(
MI
->
getOperand
(
2
)
.
getReg
(
)
)
.
addMBB
(
thisMBB
)
.
addReg
(
MI
->
getOperand
(
3
)
.
getReg
(
)
)
.
addMBB
(
copy0MBB
)
;
MI
->
eraseFromParent
(
)
;
return
BB
;
}
}
}
</s>

This method should be implemented by targets that mark instructions with the 'usesCustomInserter ' flag .


<s> static tree get_prev_label ( tree function_name ) { branch_island * bi ; unsigned ix ; FOR_EACH_VEC_SAFE_ELT ( branch_islands , ix , bi ) if ( function_name == bi -> function_name ) return bi -> label_name ; return NULL_TREE ; } </s>

GET_PREV_LABEL gets the label name from the previous definition of the function .


<s> static int mips_sim_wait_regs_2 ( rtx * x , void * data ) { if ( REG_P ( * x ) ) mips_sim_wait_reg ( data , mips_sim_insn , * x ) ; return 0 ; } </s>

A for_each_rtx callback . If * X is a register , advance simulation state DATA until mips_sim_insn can read the register 's value .


<s>
StringRef
AArch64MCExpr
::
getVariantKindName
(
)
const
{
switch
(
static_cast
<
uint32_t
>
(
getKind
(
)
)
)
{
case
VK_CALL
:
return
""
;
case
VK_LO12
:
return
":lo12:"
;
case
VK_ABS_G3
:
return
":abs_g3:"
;
case
VK_ABS_G2
:
return
":abs_g2:"
;
case
VK_ABS_G2_S
:
return
":abs_g2_s:"
;
case
VK_ABS_G2_NC
:
return
":abs_g2_nc:"
;
case
VK_ABS_G1
:
return
":abs_g1:"
;
case
VK_ABS_G1_S
:
return
":abs_g1_s:"
;
case
VK_ABS_G1_NC
:
return
":abs_g1_nc:"
;
case
VK_ABS_G0
:
return
":abs_g0:"
;
case
VK_ABS_G0_S
:
return
":abs_g0_s:"
;
case
VK_ABS_G0_NC
:
return
":abs_g0_nc:"
;
case
VK_DTPREL_G2
:
return
":dtprel_g2:"
;
case
VK_DTPREL_G1
:
return
":dtprel_g1:"
;
case
VK_DTPREL_G1_NC
:
return
":dtprel_g1_nc:"
;
case
VK_DTPREL_G0
:
return
":dtprel_g0:"
;
case
VK_DTPREL_G0_NC
:
return
":dtprel_g0_nc:"
;
case
VK_DTPREL_HI12
:
return
":dtprel_hi12:"
;
case
VK_DTPREL_LO12
:
return
":dtprel_lo12:"
;
case
VK_DTPREL_LO12_NC
:
return
":dtprel_lo12_nc:"
;
case
VK_TPREL_G2
:
return
":tprel_g2:"
;
case
VK_TPREL_G1
:
return
":tprel_g1:"
;
case
VK_TPREL_G1_NC
:
return
":tprel_g1_nc:"
;
case
VK_TPREL_G0
:
return
":tprel_g0:"
;
case
VK_TPREL_G0_NC
:
return
":tprel_g0_nc:"
;
case
VK_TPREL_HI12
:
return
":tprel_hi12:"
;
case
VK_TPREL_LO12
:
return
":tprel_lo12:"
;
case
VK_TPREL_LO12_NC
:
return
":tprel_lo12_nc:"
;
case
VK_TLSDESC_LO12
:
return
":tlsdesc_lo12:"
;
case
VK_ABS_PAGE
:
return
""
;
case
VK_ABS_PAGE_NC
:
return
":pg_hi21_nc:"
;
case
VK_GOT
:
return
":got:"
;
case
VK_GOT_PAGE
:
return
":got:"
;
case
VK_GOT_LO12
:
return
":got_lo12:"
;
case
VK_GOTTPREL
:
return
":gottprel:"
;
case
VK_GOTTPREL_PAGE
:
return
":gottprel:"
;
case
VK_GOTTPREL_LO12_NC
:
return
":gottprel_lo12:"
;
case
VK_GOTTPREL_G1
:
return
":gottprel_g1:"
;
case
VK_GOTTPREL_G0_NC
:
return
":gottprel_g0_nc:"
;
case
VK_TLSDESC
:
return
""
;
case
VK_TLSDESC_PAGE
:
return
":tlsdesc:"
;
case
VK_SECREL_LO12
:
return
":secrel_lo12:"
;
case
VK_SECREL_HI12
:
return
":secrel_hi12:"
;
case
VK_GOTOFF
:
return
":gotoff:"
;
case
VK_GOTOFF_G3
:
return
":gotoff_g3:"
;
case
VK_GOTOFF_G2
:
return
":gotoff_g2:"
;
case
VK_GOTOFF_G2_NC
:
return
":gotoff_g2_nc:"
;
case
VK_GOTOFF_G1
:
return
":gotoff_g1:"
;
case
VK_GOTOFF_G1_NC
:
return
":gotoff_g1_nc:"
;
case
VK_GOTOFF_G0
:
return
":gotoff_g0:"
;
case
VK_GOTOFF_G0_NC
:
return
":gotoff_g0_nc:"
;
case
VK_SEC_HI12
:
return
":sec_hi12:"
;
case
VK_SEC_LO12
:
return
":sec_lo12:"
;
case
VK_SEC
:
return
":sec:"
;
case
VK_SEC_G3
:
return
":sec_g3:"
;
case
VK_SEC_G2
:
return
":sec_g2:"
;
case
VK_SEC_G2_NC
:
return
":sec_g2_nc:"
;
case
VK_SEC_G1
:
return
":sec_g1:"
;
case
VK_SEC_G1_NC
:
return
":sec_g1_nc:"
;
case
VK_SEC_G0
:
return
":sec_g0:"
;
case
VK_SEC_G0_NC
:
return
":sec_g0_nc:"
;
default
:
llvm_unreachable
(
"Invalid ELF symbol kind"
)
;
}
}
</s>

Convert the variant kind into an ELF-appropriate modifier ( e.g .


<s>
InstructionCost
AArch64TTIImpl
::
getMinMaxReductionCost
(
VectorType
*
Ty
,
VectorType
*
CondTy
,
bool
IsUnsigned
,
TTI
::
TargetCostKind
CostKind
)
{
if
(
!
isa
<
ScalableVectorType
>
(
Ty
)
)
return
BaseT
::
getMinMaxReductionCost
(
Ty
,
CondTy
,
IsUnsigned
,
CostKind
)
;
assert
(
(
isa
<
ScalableVectorType
>
(
Ty
)
&&
isa
<
ScalableVectorType
>
(
CondTy
)
)
&&
"Both vector needs to be scalable"
)
;
std
::
pair
<
InstructionCost
,
MVT
>
LT
=
TLI
->
getTypeLegalizationCost
(
DL
,
Ty
)
;
InstructionCost
LegalizationCost
=
0
;
if
(
LT
.
first
>
1
)
{
Type
*
LegalVTy
=
EVT
(
LT
.
second
)
.
getTypeForEVT
(
Ty
->
getContext
(
)
)
;
unsigned
CmpOpcode
=
Ty
->
isFPOrFPVectorTy
(
)
Instruction
::
FCmp
:
Instruction
::
ICmp
;
LegalizationCost
=
getCmpSelInstrCost
(
CmpOpcode
,
LegalVTy
,
LegalVTy
,
CmpInst
::
BAD_ICMP_PREDICATE
,
CostKind
)
+
getCmpSelInstrCost
(
Instruction
::
Select
,
LegalVTy
,
LegalVTy
,
CmpInst
::
BAD_ICMP_PREDICATE
,
CostKind
)
;
LegalizationCost
*=
LT
.
first
1
;
}
return
LegalizationCost
+
2
;
}
</s>

Try to calculate op costs for min/max reduction operations .


<s> bool AVRTargetLowering :: isOffsetFoldingLegal ( const GlobalAddressSDNode * GA ) const { return true ; } </s>

Return true if folding a constant offset with the given GlobalAddress is legal .


<s> static int visium_compute_frame_size ( int size ) { const int save_area_size = visium_reg_parm_save_area_size ; const int var_size = VISIUM_STACK_ALIGN ( size ) ; const int save_fp = frame_pointer_needed || df_regs_ever_live_p ( HARD_FRAME_POINTER_REGNUM ) ; const int save_lr = frame_pointer_needed || ! crtl -> is_leaf ; const int lr_slot = ! save_lr && df_regs_ever_live_p ( long_branch_regnum ) ; const int local_frame_offset = ( save_fp + save_lr + lr_slot ) * UNITS_PER_WORD ; const int interrupt = visium_interrupt_function_p ( ) ; unsigned int mask [ last_type ] ; int reg_size1 = 0 ; int max_reg1 = 0 ; int reg_size2 = 0 ; int reg_size ; int combine ; int frame_size ; int regno ; memset ( mask , 0 , last_type * sizeof ( unsigned int ) ) ; for ( regno = 0 ; regno < FIRST_PSEUDO_REGISTER ; regno ++ ) { if ( visium_save_reg_p ( interrupt , regno ) ) { enum reg_type reg_type = GET_REG_TYPE ( regno ) ; int mask_bit = 1 << ( regno - first_regno [ reg_type ] ) ; int nbytes = reg_type_size [ reg_type ] ; if ( reg_size1 + nbytes > 32 * UNITS_PER_WORD ) break ; reg_size1 += nbytes ; max_reg1 = regno ; mask [ reg_type ] |= mask_bit ; } } for ( regno = max_reg1 + 1 ; regno < FIRST_PSEUDO_REGISTER ; regno ++ ) { if ( visium_save_reg_p ( interrupt , regno ) ) { enum reg_type reg_type = GET_REG_TYPE ( regno ) ; int mask_bit = 1 << ( regno - first_regno [ reg_type ] ) ; int nbytes = reg_type_size [ reg_type ] ; reg_size2 += nbytes ; mask [ reg_type ] |= mask_bit ; } } reg_size = reg_size2 ? reg_size2 : reg_size1 ; combine = ( local_frame_offset + var_size + reg_size ) <= 32 * UNITS_PER_WORD ; frame_size = local_frame_offset + var_size + reg_size2 + reg_size1 + save_area_size ; current_frame_info . save_area_size = save_area_size ; current_frame_info . reg_size1 = reg_size1 ; current_frame_info . max_reg1 = max_reg1 ; current_frame_info . reg_size2 = reg_size2 ; current_frame_info . var_size = var_size ; current_frame_info . save_fp = save_fp ; current_frame_info . save_lr = save_lr ; current_frame_info . lr_slot = lr_slot ; current_frame_info . combine = combine ; current_frame_info . interrupt = interrupt ; memcpy ( current_frame_info . mask , mask , last_type * sizeof ( unsigned int ) ) ; return frame_size ; } </s>

Compute the frame size required by the function . This function is called during the reload pass and also by visium_expand_prologue .


"instruction requires a CPU feature not currently enabled"

MatchAndEmitInstruction - Recognize a series of operands of a parsed instruction as an actual MCInst and emit it to the specified MCStreamer .


<s> static int mips_zero_extend_cost ( machine_mode mode , rtx op ) { if ( MEM_P ( op ) ) return 0 ; if ( TARGET_64BIT && mode == DImode && GET_MODE ( op ) == SImode ) return COSTS_N_INSNS ( TARGET_MIPS16 ? 4 : 2 ) ; if ( GENERATE_MIPS16E ) return COSTS_N_INSNS ( 1 ) ; if ( TARGET_MIPS16 ) return COSTS_N_INSNS ( GET_MODE ( op ) == QImode ? 2 : 3 ) ; return COSTS_N_INSNS ( 1 ) ; } </s>

Return the cost of zero-extending OP to mode MODE , not including the cost of OP itself .


<s> static int ix86_nsaved_regs ( void ) { int nregs = 0 ; int regno ; for ( regno = 0 ; regno < FIRST_PSEUDO_REGISTER ; regno ++ ) if ( GENERAL_REGNO_P ( regno ) && ix86_save_reg ( regno , true , true ) ) nregs ++ ; return nregs ; } </s>

Return number of registers to be saved on the stack .


<s> void GCNPassConfig :: addMachineSSAOptimization ( ) { TargetPassConfig :: addMachineSSAOptimization ( ) ; addPass ( & SIFoldOperandsID ) ; addPass ( & DeadMachineInstructionElimID ) ; addPass ( & SILoadStoreOptimizerID ) ; } </s>

Methods with trivial inline returns are convenient points in the common codegen pass pipeline where targets may insert passes .


<s> static rtx or1k_function_value ( const_tree valtype , const_tree , bool ) { return gen_rtx_REG ( TYPE_MODE ( valtype ) , RV_REGNUM ) ; } </s>

Worker for TARGET_FUNCTION_VALUE . Returns an RTX representing the location where function return values will be stored . On OpenRISC this is the register r11 . 64-bit return value 's upper 32-bits are returned in r12 , this is automatically done by GCC .


<s> static unsigned getReg ( const void * D , unsigned RC , unsigned RegNo ) { const XCoreDisassembler * Dis = static_cast < const XCoreDisassembler * > ( D ) ; const MCRegisterInfo * RegInfo = Dis -> getContext ( ) . getRegisterInfo ( ) ; return * ( RegInfo -> getRegClass ( RC ) . begin ( ) + RegNo ) ; } </s>

Returns the register associated with this edge .


<s> void s390_load_address ( rtx dst , rtx src ) { if ( TARGET_64BIT ) emit_move_insn ( dst , src ) ; else emit_insn ( gen_force_la_31 ( dst , src ) ) ; } </s>

Emit a forced load-address operation to load SRC into DST . This will use the LOAD ADDRESS instruction even in situations where legitimate_la_operand_p ( SRC ) returns false .


<s> void SystemZPassConfig :: addPreRegAlloc ( ) { addPass ( createSystemZCopyPhysRegsPass ( getSystemZTargetMachine ( ) ) ) ; } </s>

This method may be implemented by targets that want to run passes immediately before register allocation .


<s> void VEDAGToDAGISel :: Select ( SDNode * N ) { SDLoc dl ( N ) ; if ( N -> isMachineOpcode ( ) ) { N -> setNodeId ( - 1 ) ; return ; } SelectCode ( N ) ; } </s>

Main hook for targets to transform nodes into machine nodes .


Return a mask of call-preserved registers for the given calling convention on the current function .


<s> unsigned PPCDispatchGroupSBHazardRecognizer :: PreEmitNoops ( SUnit * SU ) { if ( isLoadAfterStore ( SU ) && CurSlots < 6 ) { unsigned Directive = DAG -> MF . getSubtarget < PPCSubtarget > ( ) . getCPUDirective ( ) ; if ( Directive == PPC :: DIR_PWR6 || Directive == PPC :: DIR_PWR7 || Directive == PPC :: DIR_PWR8 || Directive == PPC :: DIR_PWR9 ) return 1 ; return 5 - CurSlots ; } return ScoreboardHazardRecognizer :: PreEmitNoops ( SU ) ; } </s>

PreEmitNoops - This callback is invoked prior to emitting an instruction .


<s>
bool
NVPTXAsmPrinter
::
lowerOperand
(
const
MachineOperand
&
MO
,
MCOperand
&
MCOp
)
{
switch
(
MO
.
getType
(
)
)
{
default
:
llvm_unreachable
(
"unknown operand type"
)
;
case
MachineOperand
::
MO_Register
:
MCOp
=
MCOperand
::
CreateReg
(
encodeVirtualRegister
(
MO
.
getReg
(
)
)
)
;
break
;
case
MachineOperand
::
MO_Immediate
:
MCOp
=
MCOperand
::
CreateImm
(
MO
.
getImm
(
)
)
;
break
;
case
MachineOperand
::
MO_MachineBasicBlock
:
MCOp
=
MCOperand
::
CreateExpr
(
MCSymbolRefExpr
::
Create
(
MO
.
getMBB
(
)
->
getSymbol
(
)
,
OutContext
)
)
;
break
;
case
MachineOperand
::
MO_ExternalSymbol
:
MCOp
=
GetSymbolRef
(
MO
,
GetExternalSymbolSymbol
(
MO
.
getSymbolName
(
)
)
)
;
break
;
case
MachineOperand
::
MO_GlobalAddress
:
MCOp
=
GetSymbolRef
(
MO
,
Mang
->
getSymbol
(
MO
.
getGlobal
(
)
)
)
;
break
;
case
MachineOperand
::
MO_FPImmediate
:
{
const
ConstantFP
*
Cnt
=
MO
.
getFPImm
(
)
;
APFloat
Val
=
Cnt
->
getValueAPF
(
)
;
switch
(
Cnt
->
getType
(
)
->
getTypeID
(
)
)
{
default
:
report_fatal_error
(
"Unsupported FP type"
)
;
break
;
case
Type
::
FloatTyID
:
MCOp
=
MCOperand
::
CreateExpr
(
NVPTXFloatMCExpr
::
CreateConstantFPSingle
(
Val
,
OutContext
)
)
;
break
;
case
Type
::
DoubleTyID
:
MCOp
=
MCOperand
::
CreateExpr
(
NVPTXFloatMCExpr
::
CreateConstantFPDouble
(
Val
,
OutContext
)
)
;
break
;
}
break
;
}
}
return
true
;
}
</s>

Wrapper for MCInstLowering.lowerOperand ( ) for the tblgen'erated pseudo lowering .

NVPTX
NVPTX
"unknown operand type"
"Unsupported FP type"
NVPTX
NVPTX


<s> ARMTargetLowering :: ConstraintType ARMTargetLowering :: getConstraintType ( const std :: string & Constraint ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { default : break ; case 'l' : return C_RegisterClass ; case 'w' : return C_RegisterClass ; } } return TargetLowering :: getConstraintType ( Constraint ) ; } </s>

Given a constraint letter , return the type of constraint for this target .


<s> rtx aarch64_sls_create_blr_label ( int regnum ) { gcc_assert ( STUB_REGNUM_P ( regnum ) ) ; if ( optimize_function_for_size_p ( cfun ) ) { aarch64_sls_shared_thunks_needed = true ; const char * thunk_name = indirect_symbol_names [ regnum ] ; if ( aarch64_sls_shared_thunks [ regnum ] == NULL ) { tree decl = build_decl ( BUILTINS_LOCATION , FUNCTION_DECL , get_identifier ( thunk_name ) , build_function_type_list ( void_type_node , NULL_TREE ) ) ; DECL_RESULT ( decl ) = build_decl ( BUILTINS_LOCATION , RESULT_DECL , NULL_TREE , void_type_node ) ; TREE_PUBLIC ( decl ) = 1 ; TREE_STATIC ( decl ) = 1 ; DECL_IGNORED_P ( decl ) = 1 ; DECL_ARTIFICIAL ( decl ) = 1 ; make_decl_one_only ( decl , DECL_ASSEMBLER_NAME ( decl ) ) ; resolve_unique_section ( decl , 0 , false ) ; aarch64_sls_shared_thunks [ regnum ] = decl ; } return gen_rtx_SYMBOL_REF ( Pmode , thunk_name ) ; } if ( cfun -> machine -> call_via [ regnum ] == NULL ) cfun -> machine -> call_via [ regnum ] = gen_rtx_LABEL_REF ( Pmode , gen_label_rtx ( ) ) ; return cfun -> machine -> call_via [ regnum ] ; } </s>

Function to create a BLR thunk . This thunk is used to mitigate straight line speculation . Instead of a simple BLR that can be speculated past , we emit a BL to this thunk , and this thunk contains a BR to the relevant register . These thunks have the relevant speculation barries put after their indirect branch so that speculation is blocked . We use such a thunk so the speculation barriers are kept off the architecturally executed path in order to reduce the performance overhead . When optimizing for size we use stubs shared by the linked object . When optimizing for performance we emit stubs for each function in the hope that the branch predictor can better train on jumps specific for a given function .