<s> static void push_regs ( HARD_REG_SET * mask , bool interrupt_handler ) { bool skip_fpscr = false ; for ( int i = interrupt_handler ? LAST_BANKED_REG + 1 : 0 ; i < FIRST_PSEUDO_REGISTER ; i ++ ) { if ( i == FIRST_FP_REG && interrupt_handler && TARGET_FMOVD && hard_reg_set_intersect_p ( * mask , reg_class_contents [ DF_REGS ] ) ) { push ( FPSCR_REG ) ; fpscr_set_from_mem ( NORMAL_MODE ( FP_MODE ) , ~ * mask ) ; skip_fpscr = true ; } if ( i != PR_REG && ( i != FPSCR_REG || ! skip_fpscr ) && TEST_HARD_REG_BIT ( * mask , i ) ) { if ( ! ( sh_cfun_resbank_handler_p ( ) && ( ( i >= FIRST_GENERAL_REG && i < LAST_GENERAL_REG ) || i == MACH_REG || i == MACL_REG || i == GBR_REG ) ) ) push ( i ) ; } } if ( interrupt_handler ) { bool use_movml = false ; if ( TARGET_SH2A ) { unsigned int count = 0 ; for ( int i = FIRST_BANKED_REG ; i <= LAST_BANKED_REG ; i ++ ) if ( TEST_HARD_REG_BIT ( * mask , i ) ) count ++ ; else break ; if ( count == LAST_BANKED_REG - FIRST_BANKED_REG + 1 ) use_movml = true ; } if ( sh_cfun_resbank_handler_p ( ) ) ; else if ( use_movml ) { rtx x , mem , reg , set ; rtx sp_reg = gen_rtx_REG ( SImode , STACK_POINTER_REGNUM ) ; emit_insn ( gen_blockage ( ) ) ; x = gen_movml_push_banked ( sp_reg ) ; x = emit_frame_insn ( x ) ; for ( int i = FIRST_BANKED_REG ; i <= LAST_BANKED_REG ; i ++ ) { mem = gen_rtx_MEM ( SImode , plus_constant ( Pmode , sp_reg , i * 4 ) ) ; reg = gen_rtx_REG ( SImode , i ) ; add_reg_note ( x , REG_CFA_OFFSET , gen_rtx_SET ( mem , reg ) ) ; } set = gen_rtx_SET ( sp_reg , plus_constant ( Pmode , sp_reg , - 32 ) ) ; add_reg_note ( x , REG_CFA_ADJUST_CFA , set ) ; emit_insn ( gen_blockage ( ) ) ; } else for ( int i = FIRST_BANKED_REG ; i <= LAST_BANKED_REG ; i ++ ) if ( TEST_HARD_REG_BIT ( * mask , i ) ) push ( i ) ; } if ( TEST_HARD_REG_BIT ( * mask , PR_REG ) && ! sh_cfun_resbank_handler_p ( ) ) push ( PR_REG ) ; } </s>

Generate code to push the regs specified in the mask . remember that the mask is of the internal shape of the regs , not the external shape - so go through the renumber vector


"%qs attribute only applies to functions"

"attribute interrupt_handler is not compatible with -m5-compact"

Handle an `` interrupt_handler '' attribute ; arguments as in struct attribute_spec.handler .


<s> void JVMPassConfig :: addOptimizedRegAlloc ( FunctionPass * RegAllocPass ) { disablePass ( & RegisterCoalescerID ) ; TargetPassConfig :: addOptimizedRegAlloc ( RegAllocPass ) ; } </s>

addOptimizedRegAlloc - Add passes related to register allocation .


<s> std :: pair < SDValue , SDValue > SystemZSelectionDAGInfo :: EmitTargetCodeForStrcpy ( SelectionDAG & DAG , const SDLoc & DL , SDValue Chain , SDValue Dest , SDValue Src , MachinePointerInfo DestPtrInfo , MachinePointerInfo SrcPtrInfo , bool isStpcpy ) const { SDVTList VTs = DAG . getVTList ( Dest . getValueType ( ) , MVT :: Other ) ; SDValue EndDest = DAG . getNode ( SystemZISD :: STPCPY , DL , VTs , Chain , Dest , Src , DAG . getConstant ( 0 , DL , MVT :: i32 ) ) ; return std :: make_pair ( isStpcpy ? EndDest : Dest , EndDest . getValue ( 1 ) ) ; } </s>

Emit target-specific code that performs a strcpy or stpcpy , in cases where that is faster than a libcall .


<s> bool isMem ( RegisterKind RegKind , MemoryKind MemKind ) const { return ( Kind == KindMem && Mem . RegKind == RegKind && ( MemKind == BDXMem || ! Mem . Index ) && ( MemKind == BDLMem ) == ( Mem . Length != 0 ) ) ; } </s>


<s>
bool
X86InstrInfo
::
expandPostRAPseudo
(
MachineBasicBlock
::
iterator
MI
)
const
{
bool
HasAVX
=
TM
.
getSubtarget
<
X86Subtarget
>
(
)
.
hasAVX
(
)
;
switch
(
MI
->
getOpcode
(
)
)
{
case
X86
::
SETB_C8r
:
return
Expand2AddrUndef
(
MI
,
get
(
X86
::
SBB8rr
)
)
;
case
X86
::
SETB_C16r
:
return
Expand2AddrUndef
(
MI
,
get
(
X86
::
SBB16rr
)
)
;
case
X86
::
SETB_C32r
:
return
Expand2AddrUndef
(
MI
,
get
(
X86
::
SBB32rr
)
)
;
case
X86
::
SETB_C64r
:
return
Expand2AddrUndef
(
MI
,
get
(
X86
::
SBB64rr
)
)
;
case
X86
::
V_SET0
:
case
X86
::
FsFLD0SS
:
case
X86
::
FsFLD0SD
:
return
Expand2AddrUndef
(
MI
,
get
(
HasAVX
X86
::
VXORPSrr
:
X86
::
XORPSrr
)
)
;
case
X86
::
AVX_SET0
:
assert
(
HasAVX
&&
"AVX not supported"
)
;
return
Expand2AddrUndef
(
MI
,
get
(
X86
::
VXORPSYrr
)
)
;
case
X86
::
V_SETALLONES
:
return
Expand2AddrUndef
(
MI
,
get
(
HasAVX
X86
::
VPCMPEQDrr
:
X86
::
PCMPEQDrr
)
)
;
case
X86
::
AVX2_SETALLONES
:
return
Expand2AddrUndef
(
MI
,
get
(
X86
::
VPCMPEQDYrr
)
)
;
case
X86
::
TEST8ri_NOREX
:
MI
->
setDesc
(
get
(
X86
::
TEST8ri
)
)
;
return
true
;
}
return
false
;
}
</s>

This function is called for all pseudo instructions that remain after register allocation .


<s> uint32_t BTFStringTable :: addString ( StringRef S ) { for ( auto & OffsetM : OffsetToIdMap ) { if ( Table [ OffsetM . second ] == S ) return OffsetM . first ; } uint32_t Offset = Size ; OffsetToIdMap [ Offset ] = Table . size ( ) ; Table . push_back ( std :: string ( S ) ) ; Size += S . size ( ) + 1 ; return Offset ; } </s>


<s> const InstrItineraryData & getInstrItineraryData ( ) const { return InstrItins ; } </s>

getInstrItineraryData - Returns instruction itinerary data for the target or specific subtarget .


<s>
const
char
*
getPassName
(
)
const
override
{
return
"Workaround A53 erratum 835769 pass"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> void applyFixup ( const MCAssembler & Asm , const MCFixup & Fixup , const MCValue & Target , MutableArrayRef < char > Data , uint64_t Value , bool IsResolved ) const override { Value = adjustFixupValue ( Fixup . getKind ( ) , Value ) ; if ( ! Value ) return ; unsigned Offset = Fixup . getOffset ( ) ; unsigned NumBytes = getFixupKindNumBytes ( Fixup . getKind ( ) ) ; for ( unsigned i = 0 ; i != NumBytes ; ++ i ) { unsigned Idx = Endian == support :: little ? i : ( NumBytes - 1 - i ) ; Data [ Offset + i ] |= uint8_t ( ( Value >> ( Idx * 8 ) ) & 0xff ) ; } } </s>

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


<s> bool AMDGPUDAGToDAGISel :: runOnMachineFunction ( MachineFunction & MF ) { Subtarget = & static_cast < const AMDGPUSubtarget & > ( MF . getSubtarget ( ) ) ; return SelectionDAGISel :: runOnMachineFunction ( MF ) ; } </s>

runOnMachineFunction - Emit the function body .


<s>
void
AArch64RegisterInfo
::
eliminateFrameIndex
(
MachineBasicBlock
::
iterator
II
,
int
SPAdj
,
unsigned
FIOperandNum
,
RegScavenger
*
RS
)
const
{
assert
(
SPAdj
==
0
&&
"Unexpected"
)
;
MachineInstr
&
MI
=
*
II
;
MachineBasicBlock
&
MBB
=
*
MI
.
getParent
(
)
;
MachineFunction
&
MF
=
*
MBB
.
getParent
(
)
;
const
AArch64InstrInfo
*
TII
=
MF
.
getSubtarget
<
AArch64Subtarget
>
(
)
.
getInstrInfo
(
)
;
const
AArch64FrameLowering
*
TFI
=
getFrameLowering
(
MF
)
;
int
FrameIndex
=
MI
.
getOperand
(
FIOperandNum
)
.
getIndex
(
)
;
unsigned
FrameReg
;
int
Offset
;
if
(
MI
.
isDebugValue
(
)
||
MI
.
getOpcode
(
)
==
TargetOpcode
::
STACKMAP
||
MI
.
getOpcode
(
)
==
TargetOpcode
::
PATCHPOINT
)
{
Offset
=
TFI
->
resolveFrameIndexReference
(
MF
,
FrameIndex
,
FrameReg
,
true
)
;
Offset
+=
MI
.
getOperand
(
FIOperandNum
+
1
)
.
getImm
(
)
;
MI
.
getOperand
(
FIOperandNum
)
.
ChangeToRegister
(
FrameReg
,
false
)
;
MI
.
getOperand
(
FIOperandNum
+
1
)
.
ChangeToImmediate
(
Offset
)
;
return
;
}
if
(
MI
.
getOpcode
(
)
==
TargetOpcode
::
LOCAL_ESCAPE
)
{
MachineOperand
&
FI
=
MI
.
getOperand
(
FIOperandNum
)
;
Offset
=
TFI
->
getNonLocalFrameIndexReference
(
MF
,
FrameIndex
)
;
FI
.
ChangeToImmediate
(
Offset
)
;
return
;
}
Offset
=
TFI
->
getFrameIndexReference
(
MF
,
FrameIndex
,
FrameReg
)
;
if
(
rewriteAArch64FrameIndex
(
MI
,
FIOperandNum
,
FrameReg
,
Offset
,
TII
)
)
return
;
assert
(
(
!
RS
||
!
RS
->
isScavengingFrameIndex
(
FrameIndex
)
)
&&
"Emergency spill slot is out of reach"
)
;
unsigned
ScratchReg
=
MF
.
getRegInfo
(
)
.
createVirtualRegister
(
&
AArch64
::
GPR64RegClass
)
;
emitFrameOffset
(
MBB
,
II
,
MI
.
getDebugLoc
(
)
,
ScratchReg
,
FrameReg
,
Offset
,
TII
)
;
MI
.
getOperand
(
FIOperandNum
)
.
ChangeToRegister
(
ScratchReg
,
false
,
false
,
true
)
;
}
</s>

This method must be overriden to eliminate abstract frame indices from instructions which may use them .


<s> void AMDGPUCallLowering :: splitToValueTypes ( const ArgInfo & OrigArg , SmallVectorImpl < ArgInfo > & SplitArgs , const DataLayout & DL , MachineRegisterInfo & MRI , CallingConv :: ID CallConv , SplitArgTy PerformArgSplit ) const { const SITargetLowering & TLI = * getTLI < SITargetLowering > ( ) ; LLVMContext & Ctx = OrigArg . Ty -> getContext ( ) ; if ( OrigArg . Ty -> isVoidTy ( ) ) return ; SmallVector < EVT , 4 > SplitVTs ; ComputeValueVTs ( TLI , DL , OrigArg . Ty , SplitVTs ) ; assert ( OrigArg . Regs . size ( ) == SplitVTs . size ( ) ) ; int SplitIdx = 0 ; for ( EVT VT : SplitVTs ) { unsigned NumParts = TLI . getNumRegistersForCallingConv ( Ctx , CallConv , VT ) ; Type * Ty = VT . getTypeForEVT ( Ctx ) ; if ( NumParts == 1 ) { SplitArgs . emplace_back ( OrigArg . Regs [ SplitIdx ] , Ty , OrigArg . Flags , OrigArg . IsFixed ) ; ++ SplitIdx ; continue ; } LLT LLTy = getLLTForType ( * Ty , DL ) ; SmallVector < Register , 8 > SplitRegs ; EVT PartVT = TLI . getRegisterTypeForCallingConv ( Ctx , CallConv , VT ) ; Type * PartTy = PartVT . getTypeForEVT ( Ctx ) ; LLT PartLLT = getLLTForType ( * PartTy , DL ) ; for ( unsigned i = 0 ; i < NumParts ; ++ i ) { Register PartReg = MRI . createGenericVirtualRegister ( PartLLT ) ; SplitRegs . push_back ( PartReg ) ; SplitArgs . emplace_back ( ArrayRef < Register > ( PartReg ) , PartTy , OrigArg . Flags ) ; } PerformArgSplit ( SplitRegs , LLTy , PartLLT , SplitIdx ) ; ++ SplitIdx ; } } </s>

Break OrigArgInfo into one or more pieces the calling convention can process , returned in SplitArgs .


<s>
StringRef
getPassName
(
)
const
override
{
return
"AMDGPU OpenCL Image Type Pass"
;
}
</s>


<s> bool X86TTIImpl :: isLegalMaskedGather ( Type * DataTy ) { if ( isa < VectorType > ( DataTy ) ) { unsigned NumElts = DataTy -> getVectorNumElements ( ) ; if ( NumElts == 1 || ! isPowerOf2_32 ( NumElts ) ) return false ; } Type * ScalarTy = DataTy -> getScalarType ( ) ; int DataWidth = isa < PointerType > ( ScalarTy ) ? DL . getPointerSizeInBits ( ) : ScalarTy -> getPrimitiveSizeInBits ( ) ; return ( DataWidth == 32 || DataWidth == 64 ) && ( ST -> hasAVX512 ( ) || ( ST -> hasFastGather ( ) && ST -> hasAVX2 ( ) ) ) ; } </s>

Return true if the target supports masked gather .


<s> bool aarch64_sve_arith_immediate_p ( rtx x , bool negate_p ) { rtx elt ; if ( ! const_vec_duplicate_p ( x , & elt ) || ! CONST_INT_P ( elt ) ) return false ; HOST_WIDE_INT val = INTVAL ( elt ) ; if ( negate_p ) val = - val ; val &= GET_MODE_MASK ( GET_MODE_INNER ( GET_MODE ( x ) ) ) ; if ( val & 0xff ) return IN_RANGE ( val , 0 , 0xff ) ; return IN_RANGE ( val , 0 , 0xff00 ) ; } </s>

Return true if X is a valid immediate for the SVE ADD and SUB instructions . Negate X first if NEGATE_P is true .


<s> bool HexagonTargetLowering :: allowsMemoryAccess ( LLVMContext & Context , const DataLayout & DL , EVT VT , unsigned AddrSpace , unsigned Alignment , MachineMemOperand :: Flags Flags , bool * Fast ) const { MVT SVT = VT . getSimpleVT ( ) ; if ( Subtarget . isHVXVectorType ( SVT , true ) ) return allowsHvxMemoryAccess ( SVT , Alignment , Flags , Fast ) ; return TargetLoweringBase :: allowsMemoryAccess ( Context , DL , VT , AddrSpace , Alignment , Flags , Fast ) ; } </s>

This function returns true if the memory access is aligned or if the target allows this specific unaligned memory access .


<s> static void avr_conditional_register_usage ( void ) { if ( AVR_TINY ) { unsigned int i ; const int tiny_reg_alloc_order [ ] = { 24 , 25 , 22 , 23 , 30 , 31 , 26 , 27 , 28 , 29 , 21 , 20 , 19 , 18 , 16 , 17 , 32 , 33 , 34 , 35 , 15 , 14 , 13 , 12 , 11 , 10 , 9 , 8 , 7 , 6 , 5 , 4 , 3 , 2 , 1 , 0 } ; for ( i = 0 ; i <= 17 ; i ++ ) { fixed_regs [ i ] = 1 ; call_used_regs [ i ] = 1 ; } for ( i = 18 ; i <= LAST_CALLEE_SAVED_REG ; i ++ ) { call_used_regs [ i ] = 0 ; } for ( i = 0 ; i < ARRAY_SIZE ( tiny_reg_alloc_order ) ; i ++ ) { reg_alloc_order [ i ] = tiny_reg_alloc_order [ i ] ; } CLEAR_HARD_REG_SET ( reg_class_contents [ ( int ) ADDW_REGS ] ) ; CLEAR_HARD_REG_SET ( reg_class_contents [ ( int ) NO_LD_REGS ] ) ; } } </s>

Implement ` TARGET_CONDITIONAL_REGISTER_USAGE ' .


<s> print_operand_address ( FILE , ADDR ) { \ extern void __gcc_cleanup ( ) ; \ if ( __gcc_cleanup != _cleanup ) \ __gcc_cleanup ( ) ; \ _cleanup ( ) ; \ } </s>

Print the operand address represented by the rtx addr


<s> int ix86_data_alignment ( tree type , unsigned int align , bool opt ) { unsigned int max_align_compat = MIN ( 256 , MAX_OFILE_ALIGNMENT ) ; unsigned int max_align = MIN ( ( unsigned ) ix86_tune_cost -> prefetch_block * 8 , MAX_OFILE_ALIGNMENT ) ; if ( max_align < BITS_PER_WORD ) max_align = BITS_PER_WORD ; switch ( ix86_align_data_type ) { case ix86_align_data_type_abi : opt = false ; break ; case ix86_align_data_type_compat : max_align = BITS_PER_WORD ; break ; case ix86_align_data_type_cacheline : break ; } if ( TARGET_IAMCU ) align = iamcu_alignment ( type , align ) ; if ( opt && AGGREGATE_TYPE_P ( type ) && TYPE_SIZE ( type ) && TREE_CODE ( TYPE_SIZE ( type ) ) == INTEGER_CST ) { if ( wi :: geu_p ( wi :: to_wide ( TYPE_SIZE ( type ) ) , max_align_compat ) && align < max_align_compat ) align = max_align_compat ; if ( wi :: geu_p ( wi :: to_wide ( TYPE_SIZE ( type ) ) , max_align ) && align < max_align ) align = max_align ; } if ( TARGET_64BIT ) { if ( ( opt ? AGGREGATE_TYPE_P ( type ) : TREE_CODE ( type ) == ARRAY_TYPE ) && TYPE_SIZE ( type ) && TREE_CODE ( TYPE_SIZE ( type ) ) == INTEGER_CST && wi :: geu_p ( wi :: to_wide ( TYPE_SIZE ( type ) ) , 128 ) && align < 128 ) return 128 ; } if ( ! opt ) return align ; if ( TREE_CODE ( type ) == ARRAY_TYPE ) { if ( TYPE_MODE ( TREE_TYPE ( type ) ) == DFmode && align < 64 ) return 64 ; if ( ALIGN_MODE_128 ( TYPE_MODE ( TREE_TYPE ( type ) ) ) && align < 128 ) return 128 ; } else if ( TREE_CODE ( type ) == COMPLEX_TYPE ) { if ( TYPE_MODE ( type ) == DCmode && align < 64 ) return 64 ; if ( ( TYPE_MODE ( type ) == XCmode || TYPE_MODE ( type ) == TCmode ) && align < 128 ) return 128 ; } else if ( ( TREE_CODE ( type ) == RECORD_TYPE || TREE_CODE ( type ) == UNION_TYPE || TREE_CODE ( type ) == QUAL_UNION_TYPE ) && TYPE_FIELDS ( type ) ) { if ( DECL_MODE ( TYPE_FIELDS ( type ) ) == DFmode && align < 64 ) return 64 ; if ( ALIGN_MODE_128 ( DECL_MODE ( TYPE_FIELDS ( type ) ) ) && align < 128 ) return 128 ; } else if ( TREE_CODE ( type ) == REAL_TYPE || TREE_CODE ( type ) == VECTOR_TYPE || TREE_CODE ( type ) == INTEGER_TYPE ) { if ( TYPE_MODE ( type ) == DFmode && align < 64 ) return 64 ; if ( ALIGN_MODE_128 ( TYPE_MODE ( type ) ) && align < 128 ) return 128 ; } return align ; } </s>

Compute the alignment for a static variable . TYPE is the data type , and ALIGN is the alignment that the object would ordinarily have . The value of this function is used instead of that alignment to align the object .


<s>
void
relaxInstruction
(
MCInst
&
Inst
,
const
MCSubtargetInfo
&
STI
)
const
override
{
llvm_unreachable
(
"relaxInstruction() unimplemented"
)
;
}
</s>

Relax the instruction in the given fragment to the next wider instruction .


"MMIX Internal: %s is not a shiftable int"

Print the presumed shiftable wyde argument shifted into place ( to be output with an operand ) .


<s> static HOST_WIDE_INT xtensa_starting_frame_offset ( void ) { if ( FRAME_GROWS_DOWNWARD ) return 0 ; return crtl -> outgoing_args_size ; } </s>


<s> const MSP430InstrInfo * getInstrInfo ( ) const override { return getSubtargetImpl ( ) -> getInstrInfo ( ) ; } </s>


This method may be implemented by targets that want to run passes immediately before register allocation .


<s>
SDValue
RISCVTargetLowering
::
LowerReturn
(
SDValue
Chain
,
CallingConv
::
ID
CallConv
,
bool
IsVarArg
,
const
SmallVectorImpl
<
ISD
::
OutputArg
>
&
Outs
,
const
SmallVectorImpl
<
SDValue
>
&
OutVals
,
const
SDLoc
&
DL
,
SelectionDAG
&
DAG
)
const
{
if
(
IsVarArg
)
{
report_fatal_error
(
"VarArg not supported"
)
;
}
SmallVector
<
CCValAssign
,
16
>
RVLocs
;
CCState
CCInfo
(
CallConv
,
IsVarArg
,
DAG
.
getMachineFunction
(
)
,
RVLocs
,
*
DAG
.
getContext
(
)
)
;
CCInfo
.
AnalyzeReturn
(
Outs
,
RetCC_RISCV32
)
;
SDValue
Flag
;
SmallVector
<
SDValue
,
4
>
RetOps
(
1
,
Chain
)
;
for
(
unsigned
i
=
0
,
e
=
RVLocs
.
size
(
)
;
i
<
e
;
++
i
)
{
CCValAssign
&
VA
=
RVLocs
[
i
]
;
assert
(
VA
.
isRegLoc
(
)
&&
"Can only return in registers!"
)
;
Chain
=
DAG
.
getCopyToReg
(
Chain
,
DL
,
VA
.
getLocReg
(
)
,
OutVals
[
i
]
,
Flag
)
;
Flag
=
Chain
.
getValue
(
1
)
;
RetOps
.
push_back
(
DAG
.
getRegister
(
VA
.
getLocReg
(
)
,
VA
.
getLocVT
(
)
)
)
;
}
RetOps
[
0
]
=
Chain
;
if
(
Flag
.
getNode
(
)
)
{
RetOps
.
push_back
(
Flag
)
;
}
return
DAG
.
getNode
(
RISCVISD
::
RET_FLAG
,
DL
,
MVT
::
Other
,
RetOps
)
;
}
</s>

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .


<s> static bool or1k_function_value_regno_p ( const unsigned int regno ) { return ( regno == RV_REGNUM ) ; } </s>

Worker for TARGET_FUNCTION_VALUE_REGNO_P . Returns true if REGNO is a valid register for storing a function return value .


<s> unsigned ARM64RegisterInfo :: getRegPressureLimit ( const TargetRegisterClass * RC , MachineFunction & MF ) const { const TargetFrameLowering * TFI = MF . getTarget ( ) . getFrameLowering ( ) ; switch ( RC -> getID ( ) ) { default : return 0 ; case ARM64 :: GPR32RegClassID : case ARM64 :: GPR32spRegClassID : case ARM64 :: GPR32allRegClassID : case ARM64 :: GPR64spRegClassID : case ARM64 :: GPR64allRegClassID : case ARM64 :: GPR64RegClassID : case ARM64 :: GPR32commonRegClassID : case ARM64 :: GPR64commonRegClassID : return 32 - 1 - ( TFI -> hasFP ( MF ) || STI -> isTargetDarwin ( ) ) - STI -> isTargetDarwin ( ) - hasBasePointer ( MF ) ; case ARM64 :: FPR8RegClassID : case ARM64 :: FPR16RegClassID : case ARM64 :: FPR32RegClassID : case ARM64 :: FPR64RegClassID : case ARM64 :: FPR128RegClassID : return 32 ; case ARM64 :: DDRegClassID : case ARM64 :: DDDRegClassID : case ARM64 :: DDDDRegClassID : case ARM64 :: QQRegClassID : case ARM64 :: QQQRegClassID : case ARM64 :: QQQQRegClassID : return 32 ; case ARM64 :: FPR128_loRegClassID : return 16 ; } } </s>

Return the register pressure `` high water mark '' for the specific register class .


<s> static FunctionType * getType ( LLVMContext & Context , unsigned id ) { Type * ResultTy = NULL ; SmallVector < Type * , 8 > ArgTys ; bool IsVarArg = false ; return FunctionType :: get ( ResultTy , ArgTys , IsVarArg ) ; } </s>

Overload to return most specific vector type .


<s> static bool c6x_call_saved_register_used ( tree call_expr ) { CUMULATIVE_ARGS cum_v ; cumulative_args_t cum ; HARD_REG_SET call_saved_regset ; tree parameter ; rtx parm_rtx ; int i ; INIT_CUMULATIVE_ARGS ( cum_v , NULL , NULL , 0 , 0 ) ; cum = pack_cumulative_args ( & cum_v ) ; call_saved_regset = ~ call_used_or_fixed_regs ; for ( i = 0 ; i < call_expr_nargs ( call_expr ) ; i ++ ) { parameter = CALL_EXPR_ARG ( call_expr , i ) ; gcc_assert ( parameter ) ; if ( TREE_CODE ( parameter ) == ERROR_MARK ) return true ; function_arg_info arg ( TREE_TYPE ( parameter ) , true ) ; apply_pass_by_reference_rules ( & cum_v , arg ) ; parm_rtx = c6x_function_arg ( cum , arg ) ; c6x_function_arg_advance ( cum , arg ) ; if ( ! parm_rtx ) continue ; if ( REG_P ( parm_rtx ) && overlaps_hard_reg_set_p ( call_saved_regset , GET_MODE ( parm_rtx ) , REGNO ( parm_rtx ) ) ) return true ; if ( GET_CODE ( parm_rtx ) == PARALLEL ) { int n = XVECLEN ( parm_rtx , 0 ) ; while ( n -- > 0 ) { rtx x = XEXP ( XVECEXP ( parm_rtx , 0 , n ) , 0 ) ; if ( REG_P ( x ) && overlaps_hard_reg_set_p ( call_saved_regset , GET_MODE ( x ) , REGNO ( x ) ) ) return true ; } } } return false ; } </s>

Checks whether the given CALL_EXPR would use a caller saved register . This is used to decide whether sibling call optimization could be performed on the respective function call .


<s>
MachineBasicBlock
*
WebAssemblyTargetLowering
::
EmitInstrWithCustomInserter
(
MachineInstr
&
MI
,
MachineBasicBlock
*
BB
)
const
{
const
TargetInstrInfo
&
TII
=
*
Subtarget
->
getInstrInfo
(
)
;
DebugLoc
DL
=
MI
.
getDebugLoc
(
)
;
switch
(
MI
.
getOpcode
(
)
)
{
default
:
llvm_unreachable
(
"Unexpected instr type to insert"
)
;
case
WebAssembly
::
FP_TO_SINT_I32_F32
:
return
LowerFPToInt
(
MI
,
DL
,
BB
,
TII
,
false
,
false
,
false
,
WebAssembly
::
I32_TRUNC_S_F32
)
;
case
WebAssembly
::
FP_TO_UINT_I32_F32
:
return
LowerFPToInt
(
MI
,
DL
,
BB
,
TII
,
true
,
false
,
false
,
WebAssembly
::
I32_TRUNC_U_F32
)
;
case
WebAssembly
::
FP_TO_SINT_I64_F32
:
return
LowerFPToInt
(
MI
,
DL
,
BB
,
TII
,
false
,
true
,
false
,
WebAssembly
::
I64_TRUNC_S_F32
)
;
case
WebAssembly
::
FP_TO_UINT_I64_F32
:
return
LowerFPToInt
(
MI
,
DL
,
BB
,
TII
,
true
,
true
,
false
,
WebAssembly
::
I64_TRUNC_U_F32
)
;
case
WebAssembly
::
FP_TO_SINT_I32_F64
:
return
LowerFPToInt
(
MI
,
DL
,
BB
,
TII
,
false
,
false
,
true
,
WebAssembly
::
I32_TRUNC_S_F64
)
;
case
WebAssembly
::
FP_TO_UINT_I32_F64
:
return
LowerFPToInt
(
MI
,
DL
,
BB
,
TII
,
true
,
false
,
true
,
WebAssembly
::
I32_TRUNC_U_F64
)
;
case
WebAssembly
::
FP_TO_SINT_I64_F64
:
return
LowerFPToInt
(
MI
,
DL
,
BB
,
TII
,
false
,
true
,
true
,
WebAssembly
::
I64_TRUNC_S_F64
)
;
case
WebAssembly
::
FP_TO_UINT_I64_F64
:
return
LowerFPToInt
(
MI
,
DL
,
BB
,
TII
,
true
,
true
,
true
,
WebAssembly
::
I64_TRUNC_U_F64
)
;
case
WebAssembly
::
CALL_RESULTS
:
case
WebAssembly
::
RET_CALL_RESULTS
:
return
LowerCallResults
(
MI
,
DL
,
BB
,
TII
)
;
}
}
</s>

This method should be implemented by targets that mark instructions with the 'usesCustomInserter ' flag .


<s> void MSP430RegisterInfo :: eliminateFrameIndex ( MachineBasicBlock :: iterator II , int SPAdj , unsigned FIOperandNum , RegScavenger * RS ) const { assert ( SPAdj == 0 && "Unexpected" ) ; MachineInstr & MI = * II ; MachineBasicBlock & MBB = * MI . getParent ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; const MSP430FrameLowering * TFI = getFrameLowering ( MF ) ; DebugLoc dl = MI . getDebugLoc ( ) ; int FrameIndex = MI . getOperand ( FIOperandNum ) . getIndex ( ) ; unsigned BasePtr = ( TFI -> hasFP ( MF ) ? MSP430 :: FP : MSP430 :: SP ) ; int Offset = MF . getFrameInfo ( ) . getObjectOffset ( FrameIndex ) ; Offset += 2 ; if ( ! TFI -> hasFP ( MF ) ) Offset += MF . getFrameInfo ( ) . getStackSize ( ) ; else Offset += 2 ; Offset += MI . getOperand ( FIOperandNum + 1 ) . getImm ( ) ; if ( MI . getOpcode ( ) == MSP430 :: ADDframe ) { const TargetInstrInfo & TII = * MF . getSubtarget ( ) . getInstrInfo ( ) ; MI . setDesc ( TII . get ( MSP430 :: MOV16rr ) ) ; MI . getOperand ( FIOperandNum ) . ChangeToRegister ( BasePtr , false ) ; if ( Offset == 0 ) return ; Register DstReg = MI . getOperand ( 0 ) . getReg ( ) ; if ( Offset < 0 ) BuildMI ( MBB , std :: next ( II ) , dl , TII . get ( MSP430 :: SUB16ri ) , DstReg ) . addReg ( DstReg ) . addImm ( - Offset ) ; else BuildMI ( MBB , std :: next ( II ) , dl , TII . get ( MSP430 :: ADD16ri ) , DstReg ) . addReg ( DstReg ) . addImm ( Offset ) ; return ; } MI . getOperand ( FIOperandNum ) . ChangeToRegister ( BasePtr , false ) ; MI . getOperand ( FIOperandNum + 1 ) . ChangeToImmediate ( Offset ) ; } </s>

This method must be overriden to eliminate abstract frame indices from instructions which may use them .


<s> static unsigned long arm_compute_save_reg0_reg12_mask ( void ) { unsigned long func_type = arm_current_func_type ( ) ; unsigned long save_reg_mask = 0 ; unsigned int reg ; if ( IS_INTERRUPT ( func_type ) ) { unsigned int max_reg ; if ( ARM_FUNC_TYPE ( func_type ) == ARM_FT_FIQ ) max_reg = 7 ; else max_reg = 12 ; for ( reg = 0 ; reg <= max_reg ; reg ++ ) if ( regs_ever_live [ reg ] || ( ! current_function_is_leaf && call_used_regs [ reg ] ) ) save_reg_mask |= ( 1 << reg ) ; if ( flag_pic && ! TARGET_SINGLE_PIC_BASE && current_function_uses_pic_offset_table ) save_reg_mask |= 1 << PIC_OFFSET_TABLE_REGNUM ; } else { for ( reg = 0 ; reg <= 10 ; reg ++ ) if ( regs_ever_live [ reg ] && ! call_used_regs [ reg ] ) save_reg_mask |= ( 1 << reg ) ; if ( ! TARGET_APCS_FRAME && ! frame_pointer_needed && regs_ever_live [ HARD_FRAME_POINTER_REGNUM ] && ! call_used_regs [ HARD_FRAME_POINTER_REGNUM ] ) save_reg_mask |= 1 << HARD_FRAME_POINTER_REGNUM ; if ( flag_pic && ! TARGET_SINGLE_PIC_BASE && ( regs_ever_live [ PIC_OFFSET_TABLE_REGNUM ] || current_function_uses_pic_offset_table ) ) save_reg_mask |= 1 << PIC_OFFSET_TABLE_REGNUM ; } if ( current_function_calls_eh_return ) { unsigned int i ; for ( i = 0 ; ; i ++ ) { reg = EH_RETURN_DATA_REGNO ( i ) ; if ( reg == INVALID_REGNUM ) break ; save_reg_mask |= 1 << reg ; } } return save_reg_mask ; } </s>

Compute the register save mask for registers 0 through 12 inclusive . This code is used by arm_compute_save_reg_mask .


<s> static int no_previous_def ( tree function_name ) { branch_island * bi ; unsigned ix ; FOR_EACH_VEC_SAFE_ELT ( branch_islands , ix , bi ) if ( function_name == bi -> function_name ) return 0 ; return 1 ; } </s>

NO_PREVIOUS_DEF checks in the link list whether the function name is already there or not .


<s> bool riscv_expand_block_move ( rtx dest , rtx src , rtx length ) { if ( CONST_INT_P ( length ) ) { unsigned HOST_WIDE_INT hwi_length = UINTVAL ( length ) ; unsigned HOST_WIDE_INT factor , align ; align = MIN ( MIN ( MEM_ALIGN ( src ) , MEM_ALIGN ( dest ) ) , BITS_PER_WORD ) ; factor = BITS_PER_WORD / align ; if ( optimize_function_for_size_p ( cfun ) && hwi_length * factor * UNITS_PER_WORD > MOVE_RATIO ( false ) ) return false ; if ( hwi_length <= ( RISCV_MAX_MOVE_BYTES_STRAIGHT / factor ) ) { riscv_block_move_straight ( dest , src , INTVAL ( length ) ) ; return true ; } else if ( optimize && align >= BITS_PER_WORD ) { unsigned min_iter_words = RISCV_MAX_MOVE_BYTES_PER_LOOP_ITER / UNITS_PER_WORD ; unsigned iter_words = min_iter_words ; unsigned HOST_WIDE_INT bytes = hwi_length ; unsigned HOST_WIDE_INT words = bytes / UNITS_PER_WORD ; for ( unsigned i = min_iter_words ; i < min_iter_words * 2 - 1 ; i ++ ) { unsigned cur_cost = iter_words + words % iter_words ; unsigned new_cost = i + words % i ; if ( new_cost <= cur_cost ) iter_words = i ; } riscv_block_move_loop ( dest , src , bytes , iter_words * UNITS_PER_WORD ) ; return true ; } } return false ; } </s>

Expand a movmemsi instruction , which copies LENGTH bytes from memory reference SRC to memory reference DEST .


<s> static bool i386_asm_output_addr_const_extra ( FILE * file , rtx x ) { rtx op ; if ( GET_CODE ( x ) != UNSPEC ) return false ; op = XVECEXP ( x , 0 , 0 ) ; switch ( XINT ( x , 1 ) ) { case UNSPEC_GOTTPOFF : output_addr_const ( file , op ) ; fputs ( "@gottpoff" , file ) ; break ; case UNSPEC_TPOFF : output_addr_const ( file , op ) ; fputs ( "@tpoff" , file ) ; break ; case UNSPEC_NTPOFF : output_addr_const ( file , op ) ; if ( TARGET_64BIT ) fputs ( "@tpoff" , file ) ; else fputs ( "@ntpoff" , file ) ; break ; case UNSPEC_DTPOFF : output_addr_const ( file , op ) ; fputs ( "@dtpoff" , file ) ; break ; case UNSPEC_GOTNTPOFF : output_addr_const ( file , op ) ; if ( TARGET_64BIT ) fputs ( ASSEMBLER_DIALECT == ASM_ATT ? "@gottpoff(%rip)" : "@gottpoff[rip]" , file ) ; else fputs ( "@gotntpoff" , file ) ; break ; case UNSPEC_INDNTPOFF : output_addr_const ( file , op ) ; fputs ( "@indntpoff" , file ) ; break ; case UNSPEC_MACHOPIC_OFFSET : output_addr_const ( file , op ) ; putc ( '-' , file ) ; machopic_output_function_base_name ( file ) ; break ; case UNSPEC_STACK_CHECK : { int offset ; gcc_assert ( flag_split_stack ) ; offset = TARGET_THREAD_SPLIT_STACK_OFFSET ; gcc_unreachable ( ) ; fprintf ( file , "%s:%d" , TARGET_64BIT ? "%fs" : "%gs" , offset ) ; } break ; default : return false ; } return true ; } </s>

Implementation of TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA .


<s> OffsetRange & intersect ( OffsetRange A ) { Align = std :: max ( Align , A . Align ) ; Min = std :: max ( Min , A . Min ) ; Max = std :: min ( Max , A . Max ) ; if ( Min > Max ) std :: tie ( Min , Max , Align ) = std :: make_tuple ( 0 , - 1 , 1 ) ; return * this ; } </s>

Intersect this set with a temporary other set in place .


<s> static void register_svprfop ( ) { auto_vec < string_int_pair , 16 > values ; values . quick_push ( string_int_pair ( "SV_" # UPPER , VALUE ) ) ; AARCH64_FOR_SVPRFOP ( PUSH ) acle_svprfop = lang_hooks . types . simulate_enum_decl ( input_location , "svprfop" , & values ) ; } </s>


<s> static unsigned rs6000_hash_constant ( rtx k ) { enum rtx_code code = GET_CODE ( k ) ; machine_mode mode = GET_MODE ( k ) ; unsigned result = ( code << 3 ) ^ mode ; const char * format ; int flen , fidx ; format = GET_RTX_FORMAT ( code ) ; flen = strlen ( format ) ; fidx = 0 ; switch ( code ) { case LABEL_REF : return result * 1231 + ( unsigned ) INSN_UID ( XEXP ( k , 0 ) ) ; case CONST_WIDE_INT : { int i ; flen = CONST_WIDE_INT_NUNITS ( k ) ; for ( i = 0 ; i < flen ; i ++ ) result = result * 613 + CONST_WIDE_INT_ELT ( k , i ) ; return result ; } case CONST_DOUBLE : if ( mode != VOIDmode ) return real_hash ( CONST_DOUBLE_REAL_VALUE ( k ) ) * result ; flen = 2 ; break ; case CODE_LABEL : fidx = 3 ; break ; default : break ; } for ( ; fidx < flen ; fidx ++ ) switch ( format [ fidx ] ) { case 's' : { unsigned i , len ; const char * str = XSTR ( k , fidx ) ; len = strlen ( str ) ; result = result * 613 + len ; for ( i = 0 ; i < len ; i ++ ) result = result * 613 + ( unsigned ) str [ i ] ; break ; } case 'u' : case 'e' : result = result * 1231 + rs6000_hash_constant ( XEXP ( k , fidx ) ) ; break ; case 'i' : case 'n' : result = result * 613 + ( unsigned ) XINT ( k , fidx ) ; break ; case 'w' : if ( sizeof ( unsigned ) >= sizeof ( HOST_WIDE_INT ) ) result = result * 613 + ( unsigned ) XWINT ( k , fidx ) ; else { size_t i ; for ( i = 0 ; i < sizeof ( HOST_WIDE_INT ) / sizeof ( unsigned ) ; i ++ ) result = result * 613 + ( unsigned ) ( XWINT ( k , fidx ) >> CHAR_BIT * i ) ; } break ; case '0' : break ; default : gcc_unreachable ( ) ; } return result ; } </s>


<s> void NVPTXAsmPrinter :: EmitInstruction ( const MachineInstr * MI ) { SmallString < 128 > Str ; raw_svector_ostream OS ( Str ) ; if ( nvptxSubtarget . getDrvInterface ( ) == NVPTX :: CUDA ) emitLineNumberAsDotLoc ( * MI ) ; MCInst Inst ; lowerToMCInst ( MI , Inst ) ; EmitToStreamer ( OutStreamer , Inst ) ; } </s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s> void AVRMCCodeEmitter :: emitInstruction ( uint64_t Val , unsigned Size , const MCSubtargetInfo & STI , raw_ostream & OS ) const { size_t WordCount = Size / 2 ; for ( int64_t i = WordCount - 1 ; i >= 0 ; -- i ) { uint16_t Word = ( Val >> ( i * 16 ) ) & 0xFFFF ; support :: endian :: write ( OS , Word , support :: endianness :: little ) ; } } </s>

Targets should implement this to emit instructions .


"\nRelevant insns with their flag settings\n\n"


<s> Register MOSRegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { const TargetFrameLowering * TFI = getFrameLowering ( MF ) ; return TFI -> hasFP ( MF ) ? MOS :: RS15 : MOS :: RS0 ; } </s>


<s> bool MOSFrameLowering :: assignCalleeSavedSpillSlots ( MachineFunction & MF , const TargetRegisterInfo * TRI , std :: vector < CalleeSavedInfo > & CSI ) const { MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; for ( const auto & Info : enumerate ( CSI ) ) { if ( Info . index ( ) < 4 ) Info . value ( ) . setTargetSpilled ( ) ; else Info . value ( ) . setFrameIdx ( MFI . CreateSpillStackObject ( 1 , Align ( ) ) ) ; } return true ; } </s>

This function will assign callee saved gprs to volatile vector registers for prologue spills when applicable .


<s> static rtx frv_ifcvt_rewrite_mem ( rtx mem , enum machine_mode mode , rtx insn ) { rtx addr = XEXP ( mem , 0 ) ; if ( ! frv_legitimate_address_p ( mode , addr , reload_completed , TRUE , FALSE ) ) { if ( GET_CODE ( addr ) == PLUS ) { rtx addr_op0 = XEXP ( addr , 0 ) ; rtx addr_op1 = XEXP ( addr , 1 ) ; if ( GET_CODE ( addr_op0 ) == REG && CONSTANT_P ( addr_op1 ) ) { rtx reg = frv_ifcvt_load_value ( addr_op1 , insn ) ; if ( ! reg ) return NULL_RTX ; addr = gen_rtx_PLUS ( Pmode , addr_op0 , reg ) ; } else return NULL_RTX ; } else if ( CONSTANT_P ( addr ) ) addr = frv_ifcvt_load_value ( addr , insn ) ; else return NULL_RTX ; if ( addr == NULL_RTX ) return NULL_RTX ; else if ( XEXP ( mem , 0 ) != addr ) return change_address ( mem , mode , addr ) ; } return mem ; } </s>

Update a MEM used in conditional code that might contain an offset to put the offset into a scratch register , so that the conditional load/store operations can be used . This function returns the original pointer if the MEM is valid to use in conditional code , NULL if we ca n't load up the offset into a temporary register , or the new MEM if we were successful .


"could not find corresponding %pcrel_hi"

Hook to check if a relocation is needed for some target specific reason .


<s> static bool ix86_compat_aligned_value_p ( const_tree type ) { machine_mode mode = TYPE_MODE ( type ) ; if ( ( ( TARGET_SSE && SSE_REG_MODE_P ( mode ) ) || mode == TDmode || mode == TFmode || mode == TCmode ) && ( ! TYPE_USER_ALIGN ( type ) || TYPE_ALIGN ( type ) > 128 ) ) return true ; if ( TYPE_ALIGN ( type ) < 128 ) return false ; if ( AGGREGATE_TYPE_P ( type ) ) { switch ( TREE_CODE ( type ) ) { case RECORD_TYPE : case UNION_TYPE : case QUAL_UNION_TYPE : { tree field ; for ( field = TYPE_FIELDS ( type ) ; field ; field = DECL_CHAIN ( field ) ) { if ( TREE_CODE ( field ) == FIELD_DECL && ix86_compat_aligned_value_p ( TREE_TYPE ( field ) ) ) return true ; } break ; } case ARRAY_TYPE : if ( ix86_compat_aligned_value_p ( TREE_TYPE ( type ) ) ) return true ; break ; default : gcc_unreachable ( ) ; } } return false ; } </s>

Return true when TYPE should be 128bit aligned for 32bit argument passing ABI . XXX : This function is obsolete and is only used for checking psABI compatibility with previous versions of GCC .


"missing name in %<target(\"arch=\")%> pragma or attribute"

"invalid name (\"%s\") in %<target(\"arch=\")%> pragma or attribute"

"invalid feature modifier %s of value (\"%s\") in "

Handle the ARCH_STR argument to the arch= target attribute . PRAGMA_OR_ATTR is used in potential error messages .


<s> bool GCNTTIImpl :: isSourceOfDivergence ( const Value * V ) const { if ( const Argument * A = dyn_cast < Argument > ( V ) ) return ! isArgPassedInSGPR ( A ) ; if ( const LoadInst * Load = dyn_cast < LoadInst > ( V ) ) return Load -> getPointerAddressSpace ( ) == AMDGPUAS :: PRIVATE_ADDRESS || Load -> getPointerAddressSpace ( ) == AMDGPUAS :: FLAT_ADDRESS ; if ( isa < AtomicRMWInst > ( V ) || isa < AtomicCmpXchgInst > ( V ) ) return true ; if ( const IntrinsicInst * Intrinsic = dyn_cast < IntrinsicInst > ( V ) ) return AMDGPU :: isIntrinsicSourceOfDivergence ( Intrinsic -> getIntrinsicID ( ) ) ; if ( const CallInst * CI = dyn_cast < CallInst > ( V ) ) { if ( isa < InlineAsm > ( CI -> getCalledValue ( ) ) ) return isInlineAsmSourceOfDivergence ( CI ) ; return true ; } if ( isa < InvokeInst > ( V ) ) return true ; return false ; } </s>

Returns whether V is a source of divergence .

AMDGPU AMDGPU AMDGPU AMDGPU::isIntrinsicSourceOfDivergence


<s> HOST_WIDE_INT ia64_initial_elimination_offset ( int from , int to ) { HOST_WIDE_INT offset ; ia64_compute_frame_size ( get_frame_size ( ) ) ; switch ( from ) { case FRAME_POINTER_REGNUM : switch ( to ) { case HARD_FRAME_POINTER_REGNUM : offset = - current_frame_info . total_size ; if ( ! crtl -> is_leaf || cfun -> calls_alloca ) offset += 16 + crtl -> outgoing_args_size ; break ; case STACK_POINTER_REGNUM : offset = 0 ; if ( ! crtl -> is_leaf || cfun -> calls_alloca ) offset += 16 + crtl -> outgoing_args_size ; break ; default : gcc_unreachable ( ) ; } break ; case ARG_POINTER_REGNUM : switch ( to ) { case HARD_FRAME_POINTER_REGNUM : offset = 16 - crtl -> args . pretend_args_size ; break ; case STACK_POINTER_REGNUM : offset = ( current_frame_info . total_size + 16 - crtl -> args . pretend_args_size ) ; break ; default : gcc_unreachable ( ) ; } break ; default : gcc_unreachable ( ) ; } return offset ; } </s>

Compute the initial difference between the specified pair of registers .


<s> bool isToken ( ) const override { return Kind == TOKEN ; } </s>


<s> void ARMPassConfig :: addCodeGenPrepare ( ) { if ( getOptLevel ( ) != CodeGenOpt :: None ) addPass ( createARMCodeGenPreparePass ( ) ) ; TargetPassConfig :: addCodeGenPrepare ( ) ; } </s>

Add pass to prepare the LLVM IR for code generation .


<s> static void * rs6000_init_cost ( struct loop * loop_info ) { rs6000_cost_data * data = XNEW ( struct _rs6000_cost_data ) ; data -> loop_info = loop_info ; data -> cost [ vect_prologue ] = 0 ; data -> cost [ vect_body ] = 0 ; data -> cost [ vect_epilogue ] = 0 ; return data ; } </s>


<s> static void emit_cbcond_insn ( enum rtx_code code , rtx op0 , rtx op1 , rtx label ) { rtx if_then_else ; if_then_else = gen_rtx_IF_THEN_ELSE ( VOIDmode , gen_rtx_fmt_ee ( code , GET_MODE ( op0 ) , op0 , op1 ) , gen_rtx_LABEL_REF ( VOIDmode , label ) , pc_rtx ) ; emit_jump_insn ( gen_rtx_SET ( VOIDmode , pc_rtx , if_then_else ) ) ; } </s>

Emit a conditional jump insn for the UA2011 architecture using comparison code CODE and jump target LABEL . This function exists to take advantage of the UA2011 Compare and Branch insns .


"Encoding of this operand type is not supported yet."

getMachineOpValue - Return binary encoding of operand .


<s> void s390_expand_vec_compare ( rtx target , enum rtx_code cond , rtx cmp_op1 , rtx cmp_op2 ) { machine_mode mode = GET_MODE ( target ) ; bool neg_p = false , swap_p = false ; rtx tmp ; if ( GET_MODE ( cmp_op1 ) == V2DFmode ) { switch ( cond ) { case NE : cond = EQ ; neg_p = true ; break ; case UNGT : cond = GE ; neg_p = true ; swap_p = true ; break ; case UNGE : cond = GT ; neg_p = true ; swap_p = true ; break ; case LE : cond = GE ; swap_p = true ; break ; case UNLE : cond = GT ; neg_p = true ; break ; case LT : cond = GT ; swap_p = true ; break ; case UNLT : cond = GE ; neg_p = true ; break ; case UNEQ : emit_insn ( gen_vec_cmpuneqv2df ( target , cmp_op1 , cmp_op2 ) ) ; return ; case LTGT : emit_insn ( gen_vec_cmpltgtv2df ( target , cmp_op1 , cmp_op2 ) ) ; return ; case ORDERED : emit_insn ( gen_vec_orderedv2df ( target , cmp_op1 , cmp_op2 ) ) ; return ; case UNORDERED : emit_insn ( gen_vec_unorderedv2df ( target , cmp_op1 , cmp_op2 ) ) ; return ; default : break ; } } else { switch ( cond ) { case NE : cond = EQ ; neg_p = true ; break ; case GE : cond = GT ; neg_p = true ; swap_p = true ; break ; case GEU : cond = GTU ; neg_p = true ; swap_p = true ; break ; case LE : cond = GT ; neg_p = true ; break ; case LEU : cond = GTU ; neg_p = true ; break ; case LT : cond = GT ; swap_p = true ; break ; case LTU : cond = GTU ; swap_p = true ; break ; default : break ; } } if ( swap_p ) { tmp = cmp_op1 ; cmp_op1 = cmp_op2 ; cmp_op2 = tmp ; } emit_insn ( gen_rtx_SET ( target , gen_rtx_fmt_ee ( cond , mode , cmp_op1 , cmp_op2 ) ) ) ; if ( neg_p ) emit_insn ( gen_rtx_SET ( target , gen_rtx_NOT ( mode , target ) ) ) ; } </s>

Generate a vector comparison COND of CMP_OP1 and CMP_OP2 and store the result in TARGET .


<s>
bool
WebAssemblyArgumentMove
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
DEBUG
(
{
dbgs
(
)
<<
"********** Argument Move **********\n"
<<
"********** Function: "
<<
MF
.
getName
(
)
<<
'\n'
;
}
)
;
bool
Changed
=
false
;
MachineBasicBlock
&
EntryMBB
=
MF
.
front
(
)
;
MachineBasicBlock
::
iterator
InsertPt
=
EntryMBB
.
end
(
)
;
for
(
MachineInstr
&
MI
:
EntryMBB
)
{
if
(
!
WebAssembly
::
isArgument
(
MI
)
)
{
InsertPt
=
MI
;
break
;
}
}
for
(
MachineInstr
&
MI
:
llvm
::
make_range
(
InsertPt
,
EntryMBB
.
end
(
)
)
)
{
if
(
WebAssembly
::
isArgument
(
MI
)
)
{
EntryMBB
.
insert
(
InsertPt
,
MI
.
removeFromParent
(
)
)
;
Changed
=
true
;
}
}
return
Changed
;
}
</s>

runOnMachineFunction - Emit the function body .

WebAssembly
WebAssembly
"********** Argument Move **********\n"
"********** Function: "
WebAssembly::isArgument
WebAssembly::isArgument


<s> static void fusion_split_address ( rtx addr , rtx * p_hi , rtx * p_lo ) { rtx hi , lo ; if ( GET_CODE ( addr ) == UNSPEC && XINT ( addr , 1 ) == UNSPEC_FUSION_ADDIS ) { lo = XVECEXP ( addr , 0 , 0 ) ; hi = gen_rtx_HIGH ( Pmode , lo ) ; } else if ( GET_CODE ( addr ) == PLUS || GET_CODE ( addr ) == LO_SUM ) { hi = XEXP ( addr , 0 ) ; lo = XEXP ( addr , 1 ) ; } else gcc_unreachable ( ) ; * p_hi = hi ; * p_lo = lo ; } </s>

Given an address , convert it into the addis and load offset parts . Addresses created during the peephole2 process look like : ( lo_sum ( high ( unspec [ ( sym ) ] UNSPEC_TOCREL ) ) ( unspec [ ( ... ) ] UNSPEC_TOCREL ) )


"Check for a non-legal type in this operation\n"

LowerOperation - Provide custom lowering hooks for some operations .


<s> static void xstormy16_asm_out_destructor ( rtx symbol , int priority ) { const char * section = ".dtors" ; char buf [ 18 ] ; if ( priority != DEFAULT_INIT_PRIORITY ) { sprintf ( buf , ".dtors.%.5u" , MAX_INIT_PRIORITY - priority ) ; section = buf ; } switch_to_section ( get_section ( section , 0 , NULL ) ) ; assemble_align ( POINTER_SIZE ) ; assemble_integer ( symbol , POINTER_SIZE / BITS_PER_UNIT , POINTER_SIZE , 1 ) ; } </s>

Output constructors and destructors . Just like default_named_section_asm_out_ * but do n't set the sections writable .


<s>
SDValue
XCoreTargetLowering
::
LowerReturn
(
SDValue
Chain
,
CallingConv
::
ID
CallConv
,
bool
isVarArg
,
const
SmallVectorImpl
<
ISD
::
OutputArg
>
&
Outs
,
const
SmallVectorImpl
<
SDValue
>
&
OutVals
,
DebugLoc
dl
,
SelectionDAG
&
DAG
)
const
{
SmallVector
<
CCValAssign
,
16
>
RVLocs
;
CCState
CCInfo
(
CallConv
,
isVarArg
,
getTargetMachine
(
)
,
RVLocs
,
*
DAG
.
getContext
(
)
)
;
CCInfo
.
AnalyzeReturn
(
Outs
,
RetCC_XCore
)
;
if
(
DAG
.
getMachineFunction
(
)
.
getRegInfo
(
)
.
liveout_empty
(
)
)
{
for
(
unsigned
i
=
0
;
i
!=
RVLocs
.
size
(
)
;
++
i
)
if
(
RVLocs
[
i
]
.
isRegLoc
(
)
)
DAG
.
getMachineFunction
(
)
.
getRegInfo
(
)
.
addLiveOut
(
RVLocs
[
i
]
.
getLocReg
(
)
)
;
}
SDValue
Flag
;
for
(
unsigned
i
=
0
;
i
!=
RVLocs
.
size
(
)
;
++
i
)
{
CCValAssign
&
VA
=
RVLocs
[
i
]
;
assert
(
VA
.
isRegLoc
(
)
&&
"Can only return in registers!"
)
;
Chain
=
DAG
.
getCopyToReg
(
Chain
,
dl
,
VA
.
getLocReg
(
)
,
OutVals
[
i
]
,
Flag
)
;
Flag
=
Chain
.
getValue
(
1
)
;
}
if
(
Flag
.
getNode
(
)
)
return
DAG
.
getNode
(
XCoreISD
::
RETSP
,
dl
,
MVT
::
Other
,
Chain
,
DAG
.
getConstant
(
0
,
MVT
::
i32
)
,
Flag
)
;
else
return
DAG
.
getNode
(
XCoreISD
::
RETSP
,
dl
,
MVT
::
Other
,
Chain
,
DAG
.
getConstant
(
0
,
MVT
::
i32
)
)
;
}
</s>

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .


<s> bool gen_ldm_seq ( rtx * operands , int nops , bool sort_regs ) { int regs [ MAX_LDM_STM_OPS ] , mem_order [ MAX_LDM_STM_OPS ] ; rtx mems [ MAX_LDM_STM_OPS ] ; int i , j , base_reg ; rtx base_reg_rtx ; HOST_WIDE_INT offset ; int write_back = FALSE ; int ldm_case ; rtx addr ; ldm_case = load_multiple_sequence ( operands , nops , regs , mem_order , & base_reg , & offset , ! sort_regs ) ; if ( ldm_case == 0 ) return false ; if ( sort_regs ) for ( i = 0 ; i < nops - 1 ; i ++ ) for ( j = i + 1 ; j < nops ; j ++ ) if ( regs [ i ] > regs [ j ] ) { int t = regs [ i ] ; regs [ i ] = regs [ j ] ; regs [ j ] = t ; } base_reg_rtx = gen_rtx_REG ( Pmode , base_reg ) ; if ( TARGET_THUMB1 ) { gcc_assert ( peep2_reg_dead_p ( nops , base_reg_rtx ) ) ; gcc_assert ( ldm_case == 1 || ldm_case == 5 ) ; write_back = TRUE ; } if ( ldm_case == 5 ) { rtx newbase = TARGET_THUMB1 ? base_reg_rtx : gen_rtx_REG ( SImode , regs [ 0 ] ) ; emit_insn ( gen_addsi3 ( newbase , base_reg_rtx , GEN_INT ( offset ) ) ) ; offset = 0 ; if ( ! TARGET_THUMB1 ) base_reg_rtx = newbase ; } for ( i = 0 ; i < nops ; i ++ ) { addr = plus_constant ( Pmode , base_reg_rtx , offset + i * 4 ) ; mems [ i ] = adjust_automodify_address_nv ( operands [ nops + mem_order [ i ] ] , SImode , addr , 0 ) ; } emit_insn ( arm_gen_load_multiple_1 ( nops , regs , mems , base_reg_rtx , write_back ? offset + i * 4 : 0 ) ) ; return true ; } </s>

Called from a peephole2 expander to turn a sequence of loads into an LDM instruction . OPERANDS are the operands found by the peephole matcher ; NOPS indicates how many separate loads we are trying to combine . SORT_REGS is true if we can reorder the registers because they are used commutatively subsequently . Returns true iff we could generate a new instruction .


<s> bool TLCS900AsmPrinter :: PrintAsmMemoryOperand ( const MachineInstr * MI , unsigned OpNo , unsigned AsmVariant , const char * ExtraCode , raw_ostream & O ) { if ( ExtraCode && ExtraCode [ 0 ] ) { return true ; } printSrcMemOperand ( MI , OpNo , O ) ; return false ; } </s>

Print the specified operand of MI , an INLINEASM instruction , using the specified assembler variant as an address .


<s>
void
SystemZInstrInfo
::
insertSelect
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
const
DebugLoc
&
DL
,
unsigned
DstReg
,
ArrayRef
<
MachineOperand
>
Pred
,
unsigned
TrueReg
,
unsigned
FalseReg
)
const
{
MachineRegisterInfo
&
MRI
=
MBB
.
getParent
(
)
->
getRegInfo
(
)
;
const
TargetRegisterClass
*
RC
=
MRI
.
getRegClass
(
DstReg
)
;
assert
(
Pred
.
size
(
)
==
2
&&
"Invalid condition"
)
;
unsigned
CCValid
=
Pred
[
0
]
.
getImm
(
)
;
unsigned
CCMask
=
Pred
[
1
]
.
getImm
(
)
;
unsigned
Opc
;
if
(
SystemZ
::
GRX32BitRegClass
.
hasSubClassEq
(
RC
)
)
{
if
(
STI
.
hasLoadStoreOnCond2
(
)
)
Opc
=
SystemZ
::
LOCRMux
;
else
{
Opc
=
SystemZ
::
LOCR
;
MRI
.
constrainRegClass
(
DstReg
,
&
SystemZ
::
GR32BitRegClass
)
;
unsigned
TReg
=
MRI
.
createVirtualRegister
(
&
SystemZ
::
GR32BitRegClass
)
;
unsigned
FReg
=
MRI
.
createVirtualRegister
(
&
SystemZ
::
GR32BitRegClass
)
;
BuildMI
(
MBB
,
I
,
DL
,
get
(
TargetOpcode
::
COPY
)
,
TReg
)
.
addReg
(
TrueReg
)
;
BuildMI
(
MBB
,
I
,
DL
,
get
(
TargetOpcode
::
COPY
)
,
FReg
)
.
addReg
(
FalseReg
)
;
TrueReg
=
TReg
;
FalseReg
=
FReg
;
}
}
else
if
(
SystemZ
::
GR64BitRegClass
.
hasSubClassEq
(
RC
)
)
Opc
=
SystemZ
::
LOCGR
;
else
llvm_unreachable
(
"Invalid register class"
)
;
BuildMI
(
MBB
,
I
,
DL
,
get
(
Opc
)
,
DstReg
)
.
addReg
(
FalseReg
)
.
addReg
(
TrueReg
)
.
addImm
(
CCValid
)
.
addImm
(
CCMask
)
;
}
</s>

Insert a select instruction into MBB before I that will copy TrueReg to DstReg when Cond is true , and FalseReg to DstReg when Cond is false .


<s>
StringRef
getPassName
(
)
const
override
{
return
"Mips MipsOptimizePICCall"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> void init ( VLIWMachineScheduler * dag , const TargetSchedModel * smodel ) { DAG = dag ; SchedModel = smodel ; IssueCount = 0 ; } </s>

Initialize the machine model for instruction scheduling .


<s> bool HexagonTargetMachine :: addPostRegAlloc ( PassManagerBase & PM ) { PM . add ( createHexagonCFGOptimizer ( * this ) ) ; return true ; } </s>

This method may be implemented by targets that want to run passes after register allocation pass pipeline but before prolog-epilog insertion .


<s>
StringRef
getPassName
(
)
const
override
{
return
"ARM pseudo instruction expansion pass"
;
}
</s>

ARM
"ARM pseudo instruction expansion pass"


"Can't store this register to stack slot"

Store the specified register of the given register class to the specified stack frame index .


<s> void PPCFrameLowering :: determineCalleeSaves ( MachineFunction & MF , BitVector & SavedRegs , RegScavenger * RS ) const { TargetFrameLowering :: determineCalleeSaves ( MF , SavedRegs , RS ) ; const PPCRegisterInfo * RegInfo = Subtarget . getRegisterInfo ( ) ; PPCFunctionInfo * FI = MF . getInfo < PPCFunctionInfo > ( ) ; unsigned LR = RegInfo -> getRARegister ( ) ; FI -> setMustSaveLR ( MustSaveLR ( MF , LR ) ) ; SavedRegs . reset ( LR ) ; int FPSI = FI -> getFramePointerSaveIndex ( ) ; const bool isPPC64 = Subtarget . isPPC64 ( ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; if ( ! FPSI && needsFP ( MF ) ) { int FPOffset = getFramePointerSaveOffset ( ) ; FPSI = MFI . CreateFixedObject ( isPPC64 ? 8 : 4 , FPOffset , true ) ; FI -> setFramePointerSaveIndex ( FPSI ) ; } int BPSI = FI -> getBasePointerSaveIndex ( ) ; if ( ! BPSI && RegInfo -> hasBasePointer ( MF ) ) { int BPOffset = getBasePointerSaveOffset ( ) ; BPSI = MFI . CreateFixedObject ( isPPC64 ? 8 : 4 , BPOffset , true ) ; FI -> setBasePointerSaveIndex ( BPSI ) ; } if ( FI -> usesPICBase ( ) ) { int PBPSI = MFI . CreateFixedObject ( 4 , - 8 , true ) ; FI -> setPICBasePointerSaveIndex ( PBPSI ) ; } if ( needsFP ( MF ) ) SavedRegs . reset ( isPPC64 ? PPC :: X31 : PPC :: R31 ) ; if ( RegInfo -> hasBasePointer ( MF ) ) SavedRegs . reset ( RegInfo -> getBaseRegister ( MF ) ) ; if ( FI -> usesPICBase ( ) ) SavedRegs . reset ( PPC :: R30 ) ; int TCSPDelta = 0 ; if ( MF . getTarget ( ) . Options . GuaranteedTailCallOpt && ( TCSPDelta = FI -> getTailCallSPDelta ( ) ) < 0 ) { MFI . CreateFixedObject ( - 1 * TCSPDelta , TCSPDelta , true ) ; } if ( Subtarget . isSVR4ABI ( ) && ( SavedRegs . test ( PPC :: CR2 ) || SavedRegs . test ( PPC :: CR3 ) || SavedRegs . test ( PPC :: CR4 ) ) ) { const uint64_t SpillSize = 4 ; const int64_t SpillOffset = Subtarget . isPPC64 ( ) ? 8 : - 4 ; int FrameIdx = MFI . CreateFixedObject ( SpillSize , SpillOffset , true , false ) ; FI -> setCRSpillFrameIndex ( FrameIdx ) ; } } </s>

This method determines which of the registers reported by TargetRegisterInfo : :getCalleeSavedRegs ( ) should actually get saved .


"Inline assembly clobbers cannot have '$' preceding clobbered registers"

Given a physical register constraint ( e.g .


<s> unsigned BlackfinIntrinsicInfo :: lookupName ( const char * Name , unsigned Len ) const { return 0 ; } </s>


<s> static HOST_WIDE_INT microblaze_constant_alignment ( const_tree exp , HOST_WIDE_INT align ) { if ( TREE_CODE ( exp ) == STRING_CST || TREE_CODE ( exp ) == CONSTRUCTOR ) return MAX ( align , BITS_PER_WORD ) ; return align ; } </s>


<s> bool X86RegisterInfo :: hasReservedSpillSlot ( const MachineFunction & MF , unsigned Reg , int & FrameIdx ) const { const TargetFrameLowering * TFI = MF . getTarget ( ) . getFrameLowering ( ) ; if ( Reg == FramePtr && TFI -> hasFP ( MF ) ) { FrameIdx = MF . getFrameInfo ( ) -> getObjectIndexBegin ( ) ; return true ; } return false ; } </s>

Return true if target has reserved a spill slot in the stack frame of the given function for the specified register .


<s> static bool rs6000_modes_tieable_p ( machine_mode mode1 , machine_mode mode2 ) { if ( mode1 == PTImode || mode1 == OOmode || mode1 == XOmode || mode2 == PTImode || mode2 == OOmode || mode2 == XOmode ) return mode1 == mode2 ; if ( ALTIVEC_OR_VSX_VECTOR_MODE ( mode1 ) ) return ALTIVEC_OR_VSX_VECTOR_MODE ( mode2 ) ; if ( ALTIVEC_OR_VSX_VECTOR_MODE ( mode2 ) ) return false ; if ( SCALAR_FLOAT_MODE_P ( mode1 ) ) return SCALAR_FLOAT_MODE_P ( mode2 ) ; if ( SCALAR_FLOAT_MODE_P ( mode2 ) ) return false ; if ( GET_MODE_CLASS ( mode1 ) == MODE_CC ) return GET_MODE_CLASS ( mode2 ) == MODE_CC ; if ( GET_MODE_CLASS ( mode2 ) == MODE_CC ) return false ; return true ; } </s>

Implement TARGET_MODES_TIEABLE_P . PTImode can not tie with other modes because PTImode is restricted to even GPR registers , and TImode can go in any GPR as well as VSX registers ( PR 57744 ) . Similarly , do n't allow OOmode ( vector pair , restricted to even VSX registers ) or XOmode ( vector quad , restricted to FPR registers divisible by 4 ) to tie with other modes . Altivec/VSX vector tests were moved ahead of scalar float mode , so that IEEE 128-bit floating point on VSX systems ties with other vectors .


<s> Z80TargetLowering :: ConstraintType Z80TargetLowering :: getConstraintType ( const std :: string & Constraint ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { default : break ; case 'c' : return C_RegisterClass ; case 'R' : return C_Memory ; } } return TargetLowering :: getConstraintType ( Constraint ) ; } </s>

Given a constraint letter , return the type of constraint for this target .


"asm flags not supported in thumb1 mode"

Worker function for TARGET_MD_ASM_ADJUST , while in thumb1 mode . Unlike the arm version , we do NOT implement asm flag outputs .


<s> bool ARMBaseRegisterInfo :: canRealignStack ( const MachineFunction & MF ) const { const MachineRegisterInfo * MRI = & MF . getRegInfo ( ) ; const ARMFunctionInfo * AFI = MF . getInfo < ARMFunctionInfo > ( ) ; if ( MF . getFunction ( ) -> hasFnAttribute ( "no-realign-stack" ) ) return false ; if ( AFI -> isThumb1OnlyFunction ( ) ) return false ; if ( ! MRI -> canReserveReg ( FramePtr ) ) return false ; if ( MF . getSubtarget ( ) . getFrameLowering ( ) -> hasReservedCallFrame ( MF ) ) return true ; return MRI -> canReserveReg ( BasePtr ) ; } </s>

True if the stack can be realigned for the target .


<s> TargetLowering :: AtomicExpansionKind HexagonTargetLowering :: shouldExpandAtomicLoadInIR ( LoadInst * LI ) const { return LI -> getType ( ) -> getPrimitiveSizeInBits ( ) > 64 ? AtomicExpansionKind :: LLOnly : AtomicExpansionKind :: None ; } </s>

Returns how the given ( atomic ) load should be expanded by the IR-level AtomicExpand pass .


<s>
void
AArch64FrameLowering
::
eliminateCallFramePseudoInstr
(
MachineFunction
&
MF
,
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
MI
)
const
{
const
AArch64InstrInfo
&
TII
=
*
static_cast
<
const
AArch64InstrInfo
*
>
(
MF
.
getTarget
(
)
.
getInstrInfo
(
)
)
;
DebugLoc
dl
=
MI
->
getDebugLoc
(
)
;
int
Opcode
=
MI
->
getOpcode
(
)
;
bool
IsDestroy
=
Opcode
==
TII
.
getCallFrameDestroyOpcode
(
)
;
uint64_t
CalleePopAmount
=
IsDestroy
MI
->
getOperand
(
1
)
.
getImm
(
)
:
0
;
if
(
!
hasReservedCallFrame
(
MF
)
)
{
unsigned
Align
=
getStackAlignment
(
)
;
int64_t
Amount
=
MI
->
getOperand
(
0
)
.
getImm
(
)
;
Amount
=
RoundUpToAlignment
(
Amount
,
Align
)
;
if
(
!
IsDestroy
)
Amount
=
Amount
;
if
(
CalleePopAmount
==
0
)
{
assert
(
Amount
>
0xfff
&&
Amount
<
0xfff
&&
"call frame too large"
)
;
emitSPUpdate
(
MBB
,
MI
,
dl
,
TII
,
AArch64
::
NoRegister
,
Amount
)
;
}
}
else
if
(
CalleePopAmount
!=
0
)
{
assert
(
CalleePopAmount
<
0xfff
&&
"call frame too large"
)
;
emitSPUpdate
(
MBB
,
MI
,
dl
,
TII
,
AArch64
::
NoRegister
,
CalleePopAmount
)
;
}
MBB
.
erase
(
MI
)
;
}
</s>

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .


<s> static bool ix86_vector_duplicate_value ( machine_mode mode , rtx target , rtx val ) { bool ok ; rtx_insn * insn ; rtx dup ; dup = gen_rtx_VEC_DUPLICATE ( mode , val ) ; insn = emit_insn ( gen_rtx_SET ( VOIDmode , target , dup ) ) ; if ( recog_memoized ( insn ) < 0 ) { rtx_insn * seq ; start_sequence ( ) ; XEXP ( dup , 0 ) = force_reg ( GET_MODE_INNER ( mode ) , val ) ; seq = get_insns ( ) ; end_sequence ( ) ; if ( seq ) emit_insn_before ( seq , insn ) ; ok = recog_memoized ( insn ) >= 0 ; gcc_assert ( ok ) ; } return true ; } </s>

A subroutine of ix86_expand_vector_init_duplicate . Tries to fill target with val via vec_duplicate .


<s> bool AArch64VectorByElementOpt :: runOnMachineFunction ( MachineFunction & MF ) { if ( skipFunction ( * MF . getFunction ( ) ) ) return false ; TII = MF . getSubtarget ( ) . getInstrInfo ( ) ; MRI = & MF . getRegInfo ( ) ; const TargetSubtargetInfo & ST = MF . getSubtarget ( ) ; const AArch64InstrInfo * AAII = static_cast < const AArch64InstrInfo * > ( ST . getInstrInfo ( ) ) ; if ( ! AAII ) return false ; SchedModel . init ( ST . getSchedModel ( ) , & ST , AAII ) ; if ( ! SchedModel . hasInstrSchedModel ( ) ) return false ; if ( earlyExitVectElement ( & MF ) ) return false ; bool Changed = false ; std :: map < unsigned , bool > VecInstElemTable ; SmallVector < MachineInstr * , 8 > RemoveMIs ; for ( MachineBasicBlock & MBB : MF ) { for ( MachineBasicBlock :: iterator MII = MBB . begin ( ) , MIE = MBB . end ( ) ; MII != MIE ; ) { MachineInstr & MI = * MII ; if ( optimizeVectElement ( MI , & VecInstElemTable ) ) { RemoveMIs . push_back ( & MI ) ; Changed = true ; } ++ MII ; } } for ( MachineInstr * MI : RemoveMIs ) MI -> eraseFromParent ( ) ; return Changed ; } </s>

runOnMachineFunction - Emit the function body .


<s>
static
rtx
frv_read_iacc_argument
(
enum
machine_mode
mode
,
tree
*
arglistptr
)
{
int
i
,
regno
;
rtx
op
;
op
=
frv_read_argument
(
arglistptr
)
;
if
(
GET_CODE
(
op
)
!=
CONST_INT
||
INTVAL
(
op
)
<
0
||
INTVAL
(
op
)
>
IACC_LAST
IACC_FIRST
||
(
(
INTVAL
(
op
)
*
4
)
&
(
GET_MODE_SIZE
(
mode
)
1
)
)
!=
0
)
{
error
(
"invalid IACC argument"
)
;
op
=
const0_rtx
;
}
regno
=
INTVAL
(
op
)
+
IACC_FIRST
;
for
(
i
=
0
;
i
<
HARD_REGNO_NREGS
(
regno
,
mode
)
;
i
++
)
global_regs
[
regno
+
i
]
=
1
;
return
gen_rtx_REG
(
mode
,
regno
)
;
}
</s>

Like frv_read_argument , but interpret the argument as the number of an IACC register and return a ( reg : MODE ... ) rtx for it .


<s> unsigned RISCVRegisterInfo :: getRegisterCostTableIndex ( const MachineFunction & MF ) const { return MF . getSubtarget < RISCVSubtarget > ( ) . hasStdExtC ( ) ? 1 : 0 ; } </s>


<s> bool aarch64_emit_approx_sqrt ( rtx dst , rtx src , bool recp ) { machine_mode mode = GET_MODE ( dst ) ; if ( GET_MODE_INNER ( mode ) == HFmode ) { gcc_assert ( ! recp ) ; return false ; } if ( ! recp ) { if ( ! ( flag_mlow_precision_sqrt || ( aarch64_tune_params . approx_modes -> sqrt & AARCH64_APPROX_MODE ( mode ) ) ) ) return false ; if ( ! flag_finite_math_only || flag_trapping_math || ! flag_unsafe_math_optimizations || optimize_function_for_size_p ( cfun ) ) return false ; } else gcc_assert ( use_rsqrt_p ( mode ) ) ; rtx pg = NULL_RTX ; if ( aarch64_sve_mode_p ( mode ) ) pg = aarch64_ptrue_reg ( aarch64_sve_pred_mode ( mode ) ) ; machine_mode mmsk = ( VECTOR_MODE_P ( mode ) ? related_int_vector_mode ( mode ) . require ( ) : int_mode_for_mode ( mode ) . require ( ) ) ; rtx xmsk = NULL_RTX ; if ( ! recp ) { rtx zero = CONST0_RTX ( mode ) ; if ( pg ) { xmsk = gen_reg_rtx ( GET_MODE ( pg ) ) ; rtx hint = gen_int_mode ( SVE_KNOWN_PTRUE , SImode ) ; emit_insn ( gen_aarch64_pred_fcm ( UNSPEC_COND_FCMNE , mode , xmsk , pg , hint , src , zero ) ) ; } else { xmsk = gen_reg_rtx ( mmsk ) ; emit_insn ( gen_rtx_SET ( xmsk , gen_rtx_NEG ( mmsk , gen_rtx_EQ ( mmsk , src , zero ) ) ) ) ; } } rtx xdst = gen_reg_rtx ( mode ) ; emit_insn ( gen_aarch64_rsqrte ( mode , xdst , src ) ) ; int iterations = ( GET_MODE_INNER ( mode ) == DFmode ) ? 3 : 2 ; if ( ( recp && flag_mrecip_low_precision_sqrt ) || ( ! recp && flag_mlow_precision_sqrt ) ) iterations -- ; rtx x1 = gen_reg_rtx ( mode ) ; while ( iterations -- ) { rtx x2 = gen_reg_rtx ( mode ) ; aarch64_emit_mult ( x2 , pg , xdst , xdst ) ; emit_insn ( gen_aarch64_rsqrts ( mode , x1 , src , x2 ) ) ; if ( iterations > 0 ) aarch64_emit_mult ( xdst , pg , xdst , x1 ) ; } if ( ! recp ) { if ( pg ) emit_insn ( gen_cond ( UNSPEC_COND_FMUL , mode , xdst , xmsk , xdst , src , CONST0_RTX ( mode ) ) ) ; else { rtx xtmp = gen_reg_rtx ( mmsk ) ; emit_set_insn ( xtmp , gen_rtx_AND ( mmsk , gen_rtx_NOT ( mmsk , xmsk ) , gen_rtx_SUBREG ( mmsk , xdst , 0 ) ) ) ; emit_move_insn ( xdst , gen_rtx_SUBREG ( mode , xtmp , 0 ) ) ; aarch64_emit_mult ( xdst , pg , xdst , src ) ; } } aarch64_emit_mult ( dst , pg , xdst , x1 ) ; return true ; } </s>

Emit instruction sequence to compute either the approximate square root or its approximate reciprocal , depending on the flag RECP , and return whether the sequence was emitted or not .


<s> bool canAddEdge ( const SUnit * Succ , const SUnit * Pred ) const { if ( Pred -> NodeNum < Succ -> NodeNum ) return true ; SmallVector < const SUnit * , 64 > Succs ( { Succ } ) , Preds ( { Pred } ) ; for ( unsigned I = 0 ; I < Succs . size ( ) ; ++ I ) { for ( const SDep & SI : Succs [ I ] -> Succs ) { const SUnit * SU = SI . getSUnit ( ) ; if ( SU != Succs [ I ] && ! llvm :: is_contained ( Succs , SU ) ) Succs . push_back ( SU ) ; } } SmallPtrSet < const SUnit * , 32 > Visited ; while ( ! Preds . empty ( ) ) { const SUnit * SU = Preds . pop_back_val ( ) ; if ( llvm :: is_contained ( Succs , SU ) ) return false ; Visited . insert ( SU ) ; for ( const SDep & SI : SU -> Preds ) if ( SI . getSUnit ( ) != SU && ! Visited . count ( SI . getSUnit ( ) ) ) Preds . push_back ( SI . getSUnit ( ) ) ; } return true ; } </s>

True if an edge can be added from PredSU to SuccSU without creating a cycle .


<s> static machine_mode s390_secondary_memory_needed_mode ( machine_mode mode ) { if ( GET_MODE_BITSIZE ( mode ) < 32 ) return mode_for_size ( 32 , GET_MODE_CLASS ( mode ) , 0 ) . require ( ) ; return mode ; } </s>

Implement TARGET_SECONDARY_MEMORY_NEEDED_MODE . get_secondary_mem widens its argument to BITS_PER_WORD which loses on 64bit because the movsi and movsf patterns do n't handle r/f moves .


<s> bool Mips16RegisterInfo :: requiresRegisterScavenging ( const MachineFunction & MF ) const { return false ; } </s>

Returns true if the target requires ( and can make use of ) the register scavenger .


<s>
void
WebAssemblyTargetAsmStreamer
::
emitExportName
(
const
MCSymbolWasm
*
Sym
,
StringRef
ExportName
)
{
OS
<<
"\t.export_name\t"
<<
Sym
->
getName
(
)
<<
", "
<<
ExportName
<<
'\n'
;
}
</s>

WebAssembly
WebAssembly
"\t.export_name\t"
", "


<s> R600Subtarget & R600Subtarget :: initializeSubtargetDependencies ( const Triple & TT , StringRef GPU , StringRef FS ) { SmallString < 256 > FullFS ( "+promote-alloca," ) ; FullFS += FS ; ParseSubtargetFeatures ( GPU , GPU , FullFS ) ; HasMulU24 = getGeneration ( ) >= EVERGREEN ; HasMulI24 = hasCaymanISA ( ) ; return * this ; } </s>

initializeSubtargetDependencies - Initializes using a CPU , a TuneCPU , and feature string so that we can use initializer lists for subtarget initialization .


<s> bool Thumb1FrameLowering :: restoreCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo * TRI ) const { if ( CSI . empty ( ) ) return false ; MachineFunction & MF = * MBB . getParent ( ) ; ARMFunctionInfo * AFI = MF . getInfo < ARMFunctionInfo > ( ) ; const TargetInstrInfo & TII = * MF . getTarget ( ) . getInstrInfo ( ) ; bool isVarArg = AFI -> getVarArgsRegSaveSize ( ) > 0 ; DebugLoc DL = MI -> getDebugLoc ( ) ; MachineInstrBuilder MIB = BuildMI ( MF , DL , TII . get ( ARM :: tPOP ) ) ; AddDefaultPred ( MIB ) ; bool NumRegs = false ; for ( unsigned i = CSI . size ( ) ; i != 0 ; -- i ) { unsigned Reg = CSI [ i - 1 ] . getReg ( ) ; if ( Reg == ARM :: LR ) { if ( isVarArg ) continue ; Reg = ARM :: PC ; ( * MIB ) . setDesc ( TII . get ( ARM :: tPOP_RET ) ) ; MIB -> copyImplicitOps ( & * MI ) ; MI = MBB . erase ( MI ) ; } MIB . addReg ( Reg , getDefRegState ( true ) ) ; NumRegs = true ; } if ( NumRegs ) MBB . insert ( MI , & * MIB ) ; else MF . DeleteMachineInstr ( MIB ) ; return true ; } </s>

restoreCalleeSavedRegisters - Issues instruction ( s ) to restore all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of load instructions via loadRegToStackSlot ( ) .


<s> bool LC3PassConfig :: addInstSelector ( ) { addPass ( createLC3ISelDag ( getLC3TargetMachine ( ) , getOptLevel ( ) ) ) ; return false ; } </s>

addInstSelector - This method should install an instruction selector pass , which converts from LLVM code to machine instructions .


<s> std :: string InstructionForLatencyDetermination :: str ( ) const { std :: stringstream ss ; ss << * this ; return ss . str ( ) ; } </s>

Return the twine contents as a std : :string .


<s> const MipsMCExpr * MipsMCExpr :: create ( MipsMCExpr :: MipsExprKind Kind , const MCExpr * Expr , MCContext & Ctx ) { return new ( Ctx ) MipsMCExpr ( Kind , Expr ) ; } </s>


<s>
void
UPTFrameLowering
::
emitPrologue
(
MachineFunction
&
MF
,
MachineBasicBlock
&
MBB
)
const
{
LLVM_DEBUG
(
dbgs
(
)
<<
">> FrameLowering::emitPrologue <<\n"
)
;
MachineFrameInfo
MFI
=
MF
.
getFrameInfo
(
)
;
const
TargetInstrInfo
&
TII
=
*
MF
.
getSubtarget
(
)
.
getInstrInfo
(
)
;
const
std
::
vector
<
CalleeSavedInfo
>
&
CSI
=
MFI
.
getCalleeSavedInfo
(
)
;
const
MCRegisterInfo
*
MRI
=
MF
.
getMMI
(
)
.
getContext
(
)
.
getRegisterInfo
(
)
;
MachineBasicBlock
::
iterator
MBBI
=
MBB
.
begin
(
)
;
DebugLoc
dl
=
MBBI
!=
MBB
.
end
(
)
MBBI
->
getDebugLoc
(
)
:
DebugLoc
(
)
;
uint64_t
StackSize
=
computeStackSize
(
MF
)
;
if
(
!
StackSize
)
{
return
;
}
unsigned
StackReg
=
UPT
::
SP
;
unsigned
OffsetReg
=
materializeOffset
(
MF
,
MBB
,
MBBI
,
(
unsigned
)
StackSize
)
;
if
(
OffsetReg
)
{
BuildMI
(
MBB
,
MBBI
,
dl
,
TII
.
get
(
UPT
::
SUBR
)
,
StackReg
)
.
addReg
(
StackReg
)
.
addReg
(
OffsetReg
)
.
setMIFlag
(
MachineInstr
::
FrameSetup
)
;
}
else
{
BuildMI
(
MBB
,
MBBI
,
dl
,
TII
.
get
(
UPT
::
SUBI
)
,
StackReg
)
.
addReg
(
StackReg
)
.
addImm
(
StackSize
)
.
setMIFlag
(
MachineInstr
::
FrameSetup
)
;
}
if
(
CSI
.
size
(
)
)
{
for
(
unsigned
i
=
0
;
i
<
CSI
.
size
(
)
;
++
i
)
++
MBBI
;
for
(
std
::
vector
<
CalleeSavedInfo
>
::
const_iterator
I
=
CSI
.
begin
(
)
,
E
=
CSI
.
end
(
)
;
I
!=
E
;
++
I
)
{
int64_t
Offset
=
MFI
.
getObjectOffset
(
I
->
getFrameIdx
(
)
)
;
unsigned
CFIIndex
=
MF
.
addFrameInst
(
MCCFIInstruction
::
createOffset
(
nullptr
,
MRI
->
getDwarfRegNum
(
I
->
getReg
(
)
,
1
)
,
Offset
)
)
;
BuildMI
(
MBB
,
MBBI
,
dl
,
TII
.
get
(
TargetOpcode
::
CFI_INSTRUCTION
)
)
.
addCFIIndex
(
CFIIndex
)
;
}
}
uint64_t
StackSize
=
4
*
16
;
MF
.
getFrameInfo
(
)
.
setStackSize
(
StackSize
)
;
unsigned
StackReg
=
UPT
::
SP
;
BuildMI
(
MBB
,
MBBI
,
dl
,
TII
.
get
(
UPT
::
SUBI
)
,
StackReg
)
.
addReg
(
UPT
::
SP
)
.
addImm
(
StackSize
)
.
setMIFlag
(
MachineInstr
::
FrameSetup
)
;
}
</s>

emitProlog/emitEpilog - These methods insert prolog and epilog code into the function .

UPT
UPT
">> FrameLowering::emitPrologue <<\n"
UPT::SP
UPT::SUBR
UPT::SUBI
0
1
4
16
UPT::SP
UPT::SUBI
UPT::SP


<s> bool X86TTIImpl :: isLegalNTStore ( Type * DataType , unsigned Alignment ) { unsigned DataSize = DL . getTypeStoreSize ( DataType ) ; if ( ST -> hasSSE4A ( ) && ( DataType -> isFloatTy ( ) || DataType -> isDoubleTy ( ) ) ) return true ; if ( Alignment < DataSize || DataSize < 4 || DataSize > 32 || ! isPowerOf2_32 ( DataSize ) ) return false ; if ( DataSize == 32 ) return ST -> hasAVX ( ) ; else if ( DataSize == 16 ) return ST -> hasSSE1 ( ) ; return true ; } </s>

Return true if the target supports nontemporal store .


<s> bool ARM64PassConfig :: addPreRegAlloc ( ) { if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableAdvSIMDScalar ) addPass ( createARM64AdvSIMDScalar ( ) ) ; return true ; } </s>

This method may be implemented by targets that want to run passes immediately before register allocation .


<s> BPFSubtarget & BPFSubtarget :: initializeSubtargetDependencies ( StringRef CPU , StringRef FS ) { initializeEnvironment ( ) ; initSubtargetFeatures ( CPU , FS ) ; ParseSubtargetFeatures ( CPU , CPU , FS ) ; return * this ; } </s>


<s>
bool
SILoadStoreOptimizer
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
if
(
skipFunction
(
*
MF
.
getFunction
(
)
)
)
return
false
;
const
SISubtarget
&
STM
=
MF
.
getSubtarget
<
SISubtarget
>
(
)
;
if
(
!
STM
.
loadStoreOptEnabled
(
)
)
return
false
;
TII
=
STM
.
getInstrInfo
(
)
;
TRI
=
&
TII
->
getRegisterInfo
(
)
;
MRI
=
&
MF
.
getRegInfo
(
)
;
LIS
=
&
getAnalysis
<
LiveIntervals
>
(
)
;
DEBUG
(
dbgs
(
)
<<
"Running SILoadStoreOptimizer\n"
)
;
assert
(
!
MRI
->
isSSA
(
)
)
;
bool
Modified
=
false
;
for
(
MachineBasicBlock
&
MBB
:
MF
)
Modified
|=
optimizeBlock
(
MBB
)
;
return
Modified
;
}
</s>

AMDGPU
SI
SI
SI
"Running SILoadStoreOptimizer\n"


<s> bool ARMAsmPrinter :: runOnMachineFunction ( MachineFunction & MF ) { AFI = MF . getInfo < ARMFunctionInfo > ( ) ; MCP = MF . getConstantPool ( ) ; return AsmPrinter :: runOnMachineFunction ( MF ) ; } </s>


<s> void PPCPassConfig :: addIRPasses ( ) { addPass ( createAtomicExpandPass ( & getPPCTargetMachine ( ) ) ) ; TargetPassConfig :: addIRPasses ( ) ; } </s>

Add common target configurable passes that perform LLVM IR to IR transforms following machine independent optimization .


"Unknown regclass in loadRegFromStackSlot!"

Load the specified register of the given register class from the specified stack frame index .


<s> bool SITargetLowering :: isOffsetFoldingLegal ( const GlobalAddressSDNode * GA ) const { return ( GA -> getAddressSpace ( ) == AMDGPUASI . GLOBAL_ADDRESS || GA -> getAddressSpace ( ) == AMDGPUASI . CONSTANT_ADDRESS || GA -> getAddressSpace ( ) == AMDGPUASI . CONSTANT_ADDRESS_32BIT ) && ! shouldEmitGOTReloc ( GA -> getGlobal ( ) ) ; } </s>

Return true if folding a constant offset with the given GlobalAddress is legal .


<s> TargetLowering :: ConstraintWeight MipsTargetLowering :: getSingleConstraintMatchWeight ( AsmOperandInfo & info , const char * constraint ) const { ConstraintWeight weight = CW_Invalid ; Value * CallOperandVal = info . CallOperandVal ; if ( CallOperandVal == NULL ) return CW_Default ; Type * type = CallOperandVal -> getType ( ) ; switch ( * constraint ) { default : weight = TargetLowering :: getSingleConstraintMatchWeight ( info , constraint ) ; break ; case 'd' : case 'y' : if ( type -> isIntegerTy ( ) ) weight = CW_Register ; break ; case 'f' : if ( Subtarget -> hasMSA ( ) && type -> isVectorTy ( ) && cast < VectorType > ( type ) -> getBitWidth ( ) == 128 ) weight = CW_Register ; else if ( type -> isFloatTy ( ) ) weight = CW_Register ; break ; case 'c' : case 'l' : case 'x' : if ( type -> isIntegerTy ( ) ) weight = CW_SpecificReg ; break ; case 'I' : case 'J' : case 'K' : case 'L' : case 'N' : case 'O' : case 'P' : if ( isa < ConstantInt > ( CallOperandVal ) ) weight = CW_Constant ; break ; case 'R' : weight = CW_Memory ; break ; } return weight ; } </s>

Examine constraint string and operand type and determine a weight value .


<s>
unsigned
AMDGPURegisterInfo
::
getFrameRegister
(
const
MachineFunction
&
MF
)
const
{
assert
(
!
"Subroutines not supported yet"
)
;
return
0
;
}
</s>


"Custom lowering not defined for operation"

LowerOperation - Provide custom lowering hooks for some operations .


<s> const DataLayout * getDataLayout ( ) const { return & DL ; } </s>

Return the DataLayout associated with the module this SCEV instance is operating on .