<s> void M68kFrameLowering :: determineCalleeSaves ( MachineFunction & MF , BitVector & SavedRegs , RegScavenger * RS ) const { TargetFrameLowering :: determineCalleeSaves ( MF , SavedRegs , RS ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; M68kMachineFunctionInfo * M68kFI = MF . getInfo < M68kMachineFunctionInfo > ( ) ; int64_t TailCallReturnAddrDelta = M68kFI -> getTCReturnAddrDelta ( ) ; if ( TailCallReturnAddrDelta < 0 ) { MFI . CreateFixedObject ( - TailCallReturnAddrDelta , TailCallReturnAddrDelta - SlotSize , true ) ; } if ( TRI -> hasBasePointer ( MF ) ) { SavedRegs . set ( TRI -> getBaseRegister ( ) ) ; } } </s>

This method determines which of the registers reported by TargetRegisterInfo : :getCalleeSavedRegs ( ) should actually get saved .


Return nonzero if register OLD_REG can be renamed to register NEW_REG .


<s> static bool cbranch_predicted_p ( rtx_insn * insn ) { rtx x = find_reg_note ( insn , REG_BR_PROB , 0 ) ; if ( x ) { return profile_probability :: from_reg_br_prob_note ( XINT ( x , 0 ) ) >= profile_probability :: even ( ) ; } return false ; } </s>

Return true if INSN is annotated with a REG_BR_PROB note that indicates it 's a branch that 's predicted taken .


"rs6000_register_move_cost:, ret=%d, mode=%s, from=%s, to=%s\n"

A C expression returning the cost of moving data from a register of class CLASS1 to one of CLASS2 .


<s> bool ConstGeneration :: processBlock ( MachineBasicBlock & B , const RegisterSet & ) { bool Changed = false ; RegisterSet Defs ; for ( auto I = B . begin ( ) , E = B . end ( ) ; I != E ; ++ I ) { if ( isTfrConst ( * I ) ) continue ; Defs . clear ( ) ; HBS :: getInstrDefs ( * I , Defs ) ; if ( Defs . count ( ) != 1 ) continue ; unsigned DR = Defs . find_first ( ) ; if ( ! TargetRegisterInfo :: isVirtualRegister ( DR ) ) continue ; int64_t C ; if ( isConst ( DR , C ) ) { DebugLoc DL = I -> getDebugLoc ( ) ; auto At = I -> isPHI ( ) ? B . getFirstNonPHI ( ) : I ; unsigned ImmReg = genTfrConst ( MRI . getRegClass ( DR ) , C , B , At , DL ) ; if ( ImmReg ) { HBS :: replaceReg ( DR , ImmReg , MRI ) ; BT . put ( ImmReg , BT . lookup ( DR ) ) ; Changed = true ; } } } return Changed ; } </s>

processBlock - If there are any predecessors whose control can be threaded through to a successor , transform them now .


<s> rtx pa_eh_return_handler_rtx ( void ) { rtx tmp ; tmp = gen_rtx_PLUS ( word_mode , hard_frame_pointer_rtx , TARGET_64BIT ? GEN_INT ( - 16 ) : GEN_INT ( - 20 ) ) ; tmp = gen_rtx_MEM ( word_mode , tmp ) ; tmp -> volatil = 1 ; return tmp ; } </s>

Implement EH_RETURN_HANDLER_RTX . The MEM needs to be volatile to prevent it from being deleted .


<s> void RISCVTTIImpl :: getPeelingPreferences ( Loop * L , ScalarEvolution & SE , TTI :: PeelingPreferences & PP ) { BaseT :: getPeelingPreferences ( L , SE , PP ) ; } </s>

Get target-customized preferences for the generic loop peeling transformation .


"Unexpected register class in CSRsViaCopy!"

Insert explicit copies in entry and exit blocks .


"Not all fixup kinds added to Infos array"


<s> const MCPhysReg * TGSIRegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { static const MCPhysReg regs [ ] = { TGSI :: TEMP2 , TGSI :: TEMP3 , TGSI :: TEMP4 , TGSI :: TEMP5 , TGSI :: TEMP6 , TGSI :: TEMP7 , TGSI :: TEMP8 , TGSI :: TEMP9 , TGSI :: TEMP10 , TGSI :: TEMP11 , TGSI :: TEMP12 , TGSI :: TEMP13 , TGSI :: TEMP14 , TGSI :: TEMP15 , TGSI :: TEMP16 , TGSI :: TEMP17 , TGSI :: TEMP18 , TGSI :: TEMP19 , TGSI :: TEMP20 , TGSI :: TEMP21 , TGSI :: TEMP22 , TGSI :: TEMP23 , TGSI :: TEMP24 , TGSI :: TEMP25 , TGSI :: TEMP26 , TGSI :: TEMP27 , TGSI :: TEMP28 , TGSI :: TEMP29 , TGSI :: TEMP30 , TGSI :: TEMP31 } ; return regs ; } </s>


<s> Optional < Instruction * > AArch64TTIImpl :: instCombineIntrinsic ( InstCombiner & IC , IntrinsicInst & II ) const { Intrinsic :: ID IID = II . getIntrinsicID ( ) ; switch ( IID ) { default : break ; case Intrinsic :: aarch64_sve_convert_from_svbool : return instCombineConvertFromSVBool ( IC , II ) ; case Intrinsic :: aarch64_sve_dup : return instCombineSVEDup ( IC , II ) ; case Intrinsic :: aarch64_sve_dup_x : return instCombineSVEDupX ( IC , II ) ; case Intrinsic :: aarch64_sve_cmpne : case Intrinsic :: aarch64_sve_cmpne_wide : return instCombineSVECmpNE ( IC , II ) ; case Intrinsic :: aarch64_sve_rdffr : return instCombineRDFFR ( IC , II ) ; case Intrinsic :: aarch64_sve_lasta : case Intrinsic :: aarch64_sve_lastb : return instCombineSVELast ( IC , II ) ; case Intrinsic :: aarch64_sve_cntd : return instCombineSVECntElts ( IC , II , 2 ) ; case Intrinsic :: aarch64_sve_cntw : return instCombineSVECntElts ( IC , II , 4 ) ; case Intrinsic :: aarch64_sve_cnth : return instCombineSVECntElts ( IC , II , 8 ) ; case Intrinsic :: aarch64_sve_cntb : return instCombineSVECntElts ( IC , II , 16 ) ; case Intrinsic :: aarch64_sve_ptest_any : case Intrinsic :: aarch64_sve_ptest_first : case Intrinsic :: aarch64_sve_ptest_last : return instCombineSVEPTest ( IC , II ) ; case Intrinsic :: aarch64_sve_mul : case Intrinsic :: aarch64_sve_fmul : return instCombineSVEVectorMul ( IC , II ) ; case Intrinsic :: aarch64_sve_fadd : return instCombineSVEVectorFAdd ( IC , II ) ; case Intrinsic :: aarch64_sve_fsub : return instCombineSVEVectorBinOp ( IC , II ) ; case Intrinsic :: aarch64_sve_tbl : return instCombineSVETBL ( IC , II ) ; case Intrinsic :: aarch64_sve_uunpkhi : case Intrinsic :: aarch64_sve_uunpklo : case Intrinsic :: aarch64_sve_sunpkhi : case Intrinsic :: aarch64_sve_sunpklo : return instCombineSVEUnpack ( IC , II ) ; case Intrinsic :: aarch64_sve_tuple_get : return instCombineSVETupleGet ( IC , II ) ; case Intrinsic :: aarch64_sve_zip1 : case Intrinsic :: aarch64_sve_zip2 : return instCombineSVEZip ( IC , II ) ; case Intrinsic :: aarch64_sve_ld1_gather_index : return instCombineLD1GatherIndex ( IC , II ) ; case Intrinsic :: aarch64_sve_st1_scatter_index : return instCombineST1ScatterIndex ( IC , II ) ; case Intrinsic :: aarch64_sve_ld1 : return instCombineSVELD1 ( IC , II , DL ) ; case Intrinsic :: aarch64_sve_st1 : return instCombineSVEST1 ( IC , II , DL ) ; case Intrinsic :: aarch64_sve_sdiv : return instCombineSVESDIV ( IC , II ) ; } return None ; } </s>

Targets can implement their own combinations for target-specific intrinsics .


<s> void initialize ( ScheduleDAGMI * DAG ) override { } </s>

Initialize the strategy after building the DAG for a new region .


<s> bool MandarinFrameLowering :: hasReservedCallFrame ( const MachineFunction & MF ) const { return ! MF . getFrameInfo ( ) -> hasVarSizedObjects ( ) ; } </s>

hasReservedCallFrame - Under normal circumstances , when a frame pointer is not required , we reserve argument space for call sites in the function immediately on entry to the current function .


<s>
const
char
*
getPassName
(
)
const
override
{
return
"FISC Delay Slot Filler"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s>
void
print
(
raw_ostream
&
OS
)
const
override
{
switch
(
Kind
)
{
case
k_Token
:
OS
<<
"Token: "
<<
getToken
(
)
<<
"\n"
;
break
;
case
k_Register
:
OS
<<
"Reg: #"
<<
getReg
(
)
<<
"\n"
;
break
;
case
k_Immediate
:
OS
<<
"Imm: "
<<
getImm
(
)
<<
"\n"
;
break
;
case
k_MemoryRegRegImm
:
assert
(
getMemOffset
(
)
!=
nullptr
)
;
OS
<<
"Mem: #"
<<
getMemBase
(
)
<<
"+#"
<<
getMemIndexReg
(
)
<<
"+"
<<
*
getMemOffset
(
)
<<
"\n"
;
break
;
case
k_MemoryRegImmImm
:
assert
(
getMemIndex
(
)
!=
nullptr
&&
getMemOffset
(
)
!=
nullptr
)
;
OS
<<
"Mem: #"
<<
getMemBase
(
)
<<
"+"
<<
*
getMemIndex
(
)
<<
"+"
<<
*
getMemOffset
(
)
<<
"\n"
;
break
;
case
k_MemoryZeroRegImm
:
assert
(
getMemOffset
(
)
!=
nullptr
)
;
OS
<<
"Mem: 0+#"
<<
getMemIndexReg
(
)
<<
"+"
<<
*
getMemOffset
(
)
<<
"\n"
;
break
;
case
k_MemoryZeroImmImm
:
assert
(
getMemIndex
(
)
!=
nullptr
&&
getMemOffset
(
)
!=
nullptr
)
;
OS
<<
"Mem: 0+"
<<
*
getMemIndex
(
)
<<
"+"
<<
*
getMemOffset
(
)
<<
"\n"
;
break
;
case
k_MemoryRegImm
:
assert
(
getMemOffset
(
)
!=
nullptr
)
;
OS
<<
"Mem: #"
<<
getMemBase
(
)
<<
"+"
<<
*
getMemOffset
(
)
<<
"\n"
;
break
;
case
k_MemoryZeroImm
:
assert
(
getMemOffset
(
)
!=
nullptr
)
;
OS
<<
"Mem: 0+"
<<
*
getMemOffset
(
)
<<
"\n"
;
break
;
case
k_CCOp
:
OS
<<
"CCOp: "
<<
getCCVal
(
)
<<
"\n"
;
break
;
case
k_RDOp
:
OS
<<
"RDOp: "
<<
getRDVal
(
)
<<
"\n"
;
break
;
case
k_MImmOp
:
OS
<<
"MImm: ("
<<
getMImmVal
(
)
<<
(
getM0Flag
(
)
")0"
:
")1"
)
<<
"\n"
;
break
;
}
}
</s>

print - Print a debug representation of the operand to the given stream .


<s> static bool aarch64_evpc_zip ( struct expand_vec_perm_d * d ) { unsigned int i , high , mask , nelt = d -> nelt ; rtx out , in0 , in1 , x ; rtx ( * gen ) ( rtx , rtx , rtx ) ; machine_mode vmode = d -> vmode ; if ( GET_MODE_UNIT_SIZE ( vmode ) > 8 ) return false ; high = nelt / 2 ; if ( d -> perm [ 0 ] == high ) ; else if ( d -> perm [ 0 ] == 0 ) high = 0 ; else return false ; mask = ( d -> one_vector_p ? nelt - 1 : 2 * nelt - 1 ) ; for ( i = 0 ; i < nelt / 2 ; i ++ ) { unsigned elt = ( i + high ) & mask ; if ( d -> perm [ i * 2 ] != elt ) return false ; elt = ( elt + nelt ) & mask ; if ( d -> perm [ i * 2 + 1 ] != elt ) return false ; } if ( d -> testing_p ) return true ; in0 = d -> op0 ; in1 = d -> op1 ; if ( BYTES_BIG_ENDIAN ) { x = in0 , in0 = in1 , in1 = x ; high = ! high ; } out = d -> target ; if ( high ) { switch ( vmode ) { case V16QImode : gen = gen_aarch64_zip2v16qi ; break ; case V8QImode : gen = gen_aarch64_zip2v8qi ; break ; case V8HImode : gen = gen_aarch64_zip2v8hi ; break ; case V4HImode : gen = gen_aarch64_zip2v4hi ; break ; case V4SImode : gen = gen_aarch64_zip2v4si ; break ; case V2SImode : gen = gen_aarch64_zip2v2si ; break ; case V2DImode : gen = gen_aarch64_zip2v2di ; break ; case V4SFmode : gen = gen_aarch64_zip2v4sf ; break ; case V2SFmode : gen = gen_aarch64_zip2v2sf ; break ; case V2DFmode : gen = gen_aarch64_zip2v2df ; break ; default : return false ; } } else { switch ( vmode ) { case V16QImode : gen = gen_aarch64_zip1v16qi ; break ; case V8QImode : gen = gen_aarch64_zip1v8qi ; break ; case V8HImode : gen = gen_aarch64_zip1v8hi ; break ; case V4HImode : gen = gen_aarch64_zip1v4hi ; break ; case V4SImode : gen = gen_aarch64_zip1v4si ; break ; case V2SImode : gen = gen_aarch64_zip1v2si ; break ; case V2DImode : gen = gen_aarch64_zip1v2di ; break ; case V4SFmode : gen = gen_aarch64_zip1v4sf ; break ; case V2SFmode : gen = gen_aarch64_zip1v2sf ; break ; case V2DFmode : gen = gen_aarch64_zip1v2df ; break ; default : return false ; } } emit_insn ( gen ( out , in0 , in1 ) ) ; return true ; } </s>

Recognize patterns suitable for the ZIP instructions .


<s> static bool isIdentityMask ( SDNode * N , bool RHS = false ) { unsigned NumElems = N -> getNumOperands ( ) ; for ( unsigned i = 0 ; i < NumElems ; ++ i ) if ( ! isUndefOrEqual ( N -> getOperand ( i ) , i + ( RHS ? NumElems : 0 ) ) ) return false ; return true ; } </s>

Return true if this shuffle mask chooses elements from exactly one source vector without lane crossings .


<s> BitVector MipsRegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { static const uint16_t ReservedCPURegs [ ] = { Mips :: ZERO , Mips :: AT , Mips :: K0 , Mips :: K1 , Mips :: SP } ; static const uint16_t ReservedCPU64Regs [ ] = { Mips :: ZERO_64 , Mips :: AT_64 , Mips :: K0_64 , Mips :: K1_64 , Mips :: SP_64 } ; BitVector Reserved ( getNumRegs ( ) ) ; typedef TargetRegisterClass :: const_iterator RegIter ; for ( unsigned I = 0 ; I < array_lengthof ( ReservedCPURegs ) ; ++ I ) Reserved . set ( ReservedCPURegs [ I ] ) ; if ( Subtarget . hasMips64 ( ) ) { for ( unsigned I = 0 ; I < array_lengthof ( ReservedCPU64Regs ) ; ++ I ) Reserved . set ( ReservedCPU64Regs [ I ] ) ; for ( RegIter Reg = Mips :: AFGR64RegClass . begin ( ) , EReg = Mips :: AFGR64RegClass . end ( ) ; Reg != EReg ; ++ Reg ) Reserved . set ( * Reg ) ; } else { for ( RegIter Reg = Mips :: CPU64RegsRegClass . begin ( ) , EReg = Mips :: CPU64RegsRegClass . end ( ) ; Reg != EReg ; ++ Reg ) Reserved . set ( * Reg ) ; for ( RegIter Reg = Mips :: FGR64RegClass . begin ( ) , EReg = Mips :: FGR64RegClass . end ( ) ; Reg != EReg ; ++ Reg ) Reserved . set ( * Reg ) ; } if ( MF . getTarget ( ) . getFrameLowering ( ) -> hasFP ( MF ) ) { if ( Subtarget . inMips16Mode ( ) ) Reserved . set ( Mips :: S0 ) ; else { Reserved . set ( Mips :: FP ) ; Reserved . set ( Mips :: FP_64 ) ; } } Reserved . set ( Mips :: HWR29 ) ; Reserved . set ( Mips :: HWR29_64 ) ; Reserved . set ( Mips :: DSPCtrl ) ; if ( Subtarget . inMips16Mode ( ) ) { Reserved . set ( Mips :: RA ) ; Reserved . set ( Mips :: RA_64 ) ; } if ( Subtarget . useSmallSection ( ) ) { Reserved . set ( Mips :: GP ) ; Reserved . set ( Mips :: GP_64 ) ; } return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s> bool X86TargetLowering :: hasAndNotCompare ( SDValue Y ) const { if ( ! Subtarget . hasBMI ( ) ) return false ; EVT VT = Y . getValueType ( ) ; if ( VT != MVT :: i32 && VT != MVT :: i64 ) return false ; return true ; } </s>

Return true if the target should transform : ( X & Y ) == Y � ? ( ~X & Y ) == 0 ( X & Y ) ! = Y � ? ( ~X & Y ) ! = 0 .


<s> void VERegisterInfo :: eliminateFrameIndex ( MachineBasicBlock :: iterator II , int SPAdj , unsigned FIOperandNum , RegScavenger * RS ) const { assert ( SPAdj == 0 && "Unexpected" ) ; MachineInstr & MI = * II ; DebugLoc dl = MI . getDebugLoc ( ) ; int FrameIndex = MI . getOperand ( FIOperandNum ) . getIndex ( ) ; MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ; const VEFrameLowering * TFI = getFrameLowering ( MF ) ; Register FrameReg ; int Offset ; Offset = TFI -> getFrameIndexReference ( MF , FrameIndex , FrameReg ) ; Offset += MI . getOperand ( FIOperandNum + 2 ) . getImm ( ) ; if ( MI . getOpcode ( ) == VE :: STQrii ) { const TargetInstrInfo & TII = * MF . getSubtarget ( ) . getInstrInfo ( ) ; Register SrcReg = MI . getOperand ( 3 ) . getReg ( ) ; Register SrcHiReg = getSubReg ( SrcReg , VE :: sub_even ) ; Register SrcLoReg = getSubReg ( SrcReg , VE :: sub_odd ) ; MachineInstr * StMI = BuildMI ( * MI . getParent ( ) , II , dl , TII . get ( VE :: STrii ) ) . addReg ( FrameReg ) . addImm ( 0 ) . addImm ( 0 ) . addReg ( SrcLoReg ) ; replaceFI ( MF , II , * StMI , dl , 0 , Offset , FrameReg ) ; MI . setDesc ( TII . get ( VE :: STrii ) ) ; MI . getOperand ( 3 ) . setReg ( SrcHiReg ) ; Offset += 8 ; } else if ( MI . getOpcode ( ) == VE :: LDQrii ) { const TargetInstrInfo & TII = * MF . getSubtarget ( ) . getInstrInfo ( ) ; Register DestReg = MI . getOperand ( 0 ) . getReg ( ) ; Register DestHiReg = getSubReg ( DestReg , VE :: sub_even ) ; Register DestLoReg = getSubReg ( DestReg , VE :: sub_odd ) ; MachineInstr * StMI = BuildMI ( * MI . getParent ( ) , II , dl , TII . get ( VE :: LDrii ) , DestLoReg ) . addReg ( FrameReg ) . addImm ( 0 ) . addImm ( 0 ) ; replaceFI ( MF , II , * StMI , dl , 1 , Offset , FrameReg ) ; MI . setDesc ( TII . get ( VE :: LDrii ) ) ; MI . getOperand ( 0 ) . setReg ( DestHiReg ) ; Offset += 8 ; } replaceFI ( MF , II , MI , dl , FIOperandNum , Offset , FrameReg ) ; } </s>

This method must be overriden to eliminate abstract frame indices from instructions which may use them .


<s> bool HexagonMCInst :: isExtended ( void ) const { const uint64_t F = getDesc ( ) . TSFlags ; return ( F >> HexagonII :: ExtendedPos ) & HexagonII :: ExtendedMask ; } </s>

Test if the given EVT is extended ( as opposed to being simple ) .

Hexagon Hexagon HexagonII::ExtendedPos HexagonII::ExtendedMask


<s> SDValue MSP430TargetLowering :: LowerCallResult ( SDValue Chain , SDValue InFlag , CallingConv :: ID CallConv , bool isVarArg , const SmallVectorImpl < ISD :: InputArg > & Ins , SDLoc dl , SelectionDAG & DAG , SmallVectorImpl < SDValue > & InVals ) const { SmallVector < CCValAssign , 16 > RVLocs ; CCState CCInfo ( CallConv , isVarArg , DAG . getMachineFunction ( ) , getTargetMachine ( ) , RVLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeCallResult ( Ins , RetCC_MSP430 ) ; for ( unsigned i = 0 ; i != RVLocs . size ( ) ; ++ i ) { Chain = DAG . getCopyFromReg ( Chain , dl , RVLocs [ i ] . getLocReg ( ) , RVLocs [ i ] . getValVT ( ) , InFlag ) . getValue ( 1 ) ; InFlag = Chain . getValue ( 2 ) ; InVals . push_back ( Chain . getValue ( 0 ) ) ; } return Chain ; } </s>

LowerCallResult - Lower the result values of an ISD : :CALL into the appropriate copies out of appropriate physical registers .


<s> bool XCoreInstrInfo :: spillCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI ) const { if ( CSI . empty ( ) ) { return true ; } MachineFunction * MF = MBB . getParent ( ) ; const MachineFrameInfo * MFI = MF -> getFrameInfo ( ) ; MachineModuleInfo * MMI = MFI -> getMachineModuleInfo ( ) ; XCoreFunctionInfo * XFI = MF -> getInfo < XCoreFunctionInfo > ( ) ; bool emitFrameMoves = XCoreRegisterInfo :: needsFrameMoves ( * MF ) ; DebugLoc DL = DebugLoc :: getUnknownLoc ( ) ; if ( MI != MBB . end ( ) ) DL = MI -> getDebugLoc ( ) ; for ( std :: vector < CalleeSavedInfo > :: const_iterator it = CSI . begin ( ) ; it != CSI . end ( ) ; ++ it ) { MBB . addLiveIn ( it -> getReg ( ) ) ; storeRegToStackSlot ( MBB , MI , it -> getReg ( ) , true , it -> getFrameIdx ( ) , it -> getRegClass ( ) ) ; if ( emitFrameMoves ) { MCSymbol * SaveLabel = MMI -> getContext ( ) . CreateTempSymbol ( ) ; BuildMI ( MBB , MI , DL , get ( XCore :: DBG_LABEL ) ) . addSym ( SaveLabel ) ; XFI -> getSpillLabels ( ) . push_back ( std :: make_pair ( SaveLabel , * it ) ) ; } } return true ; } </s>

spillCalleeSavedRegisters - Issues instruction ( s ) to spill all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of store instructions via storeRegToStackSlot ( ) .

XCore XCore XCore XCore XCore XCore::DBG_LABEL


<s> static void rs6000_do_expand_vec_perm ( rtx target , rtx op0 , rtx op1 , machine_mode vmode , unsigned nelt , rtx perm [ ] ) { machine_mode imode ; rtx x ; imode = vmode ; if ( GET_MODE_CLASS ( vmode ) != MODE_VECTOR_INT ) { imode = mode_for_size ( GET_MODE_UNIT_BITSIZE ( vmode ) , MODE_INT , 0 ) ; imode = mode_for_vector ( imode , nelt ) ; } x = gen_rtx_CONST_VECTOR ( imode , gen_rtvec_v ( nelt , perm ) ) ; x = expand_vec_perm ( vmode , op0 , op1 , x , target ) ; if ( x != target ) emit_move_insn ( target , x ) ; } </s>

A subroutine for rs6000_expand_extract_even & rs6000_expand_interleave .


<s>
void
WebAssemblyInstPrinter
::
printInst
(
const
MCInst
*
MI
,
raw_ostream
&
OS
,
StringRef
Annot
,
const
MCSubtargetInfo
&
STI
)
{
printInstruction
(
MI
,
OS
)
;
const
MCInstrDesc
&
Desc
=
MII
.
get
(
MI
->
getOpcode
(
)
)
;
if
(
Desc
.
isVariadic
(
)
)
for
(
auto
i
=
Desc
.
getNumOperands
(
)
,
e
=
MI
->
getNumOperands
(
)
;
i
<
e
;
++
i
)
{
if
(
i
!=
0
&&
(
MI
->
getOpcode
(
)
!=
WebAssembly
::
CALL_INDIRECT_VOID
||
i
!=
Desc
.
getNumOperands
(
)
)
)
OS
<<
", "
;
printOperand
(
MI
,
i
,
OS
)
;
}
printAnnotation
(
OS
,
Annot
)
;
if
(
CommentStream
)
{
switch
(
MI
->
getOpcode
(
)
)
{
default
:
break
;
case
WebAssembly
::
LOOP
:
case
WebAssembly
::
LOOP_S
:
{
printAnnotation
(
OS
,
"label"
+
utostr
(
ControlFlowCounter
)
+
':'
)
;
ControlFlowStack
.
push_back
(
std
::
make_pair
(
ControlFlowCounter
++
,
true
)
)
;
break
;
}
case
WebAssembly
::
BLOCK
:
case
WebAssembly
::
BLOCK_S
:
ControlFlowStack
.
push_back
(
std
::
make_pair
(
ControlFlowCounter
++
,
false
)
)
;
break
;
case
WebAssembly
::
END_LOOP
:
case
WebAssembly
::
END_LOOP_S
:
if
(
!
ControlFlowStack
.
empty
(
)
)
ControlFlowStack
.
pop_back
(
)
;
break
;
case
WebAssembly
::
END_BLOCK
:
case
WebAssembly
::
END_BLOCK_S
:
if
(
!
ControlFlowStack
.
empty
(
)
)
printAnnotation
(
OS
,
"label"
+
utostr
(
ControlFlowStack
.
pop_back_val
(
)
.
first
)
+
':'
)
;
break
;
}
unsigned
NumFixedOperands
=
Desc
.
NumOperands
;
SmallSet
<
uint64_t
,
8
>
Printed
;
for
(
unsigned
i
=
0
,
e
=
MI
->
getNumOperands
(
)
;
i
<
e
;
++
i
)
{
if
(
!
(
i
<
NumFixedOperands
(
Desc
.
OpInfo
[
i
]
.
OperandType
==
WebAssembly
::
OPERAND_BASIC_BLOCK
)
:
(
Desc
.
TSFlags
&
WebAssemblyII
::
VariableOpImmediateIsLabel
)
)
)
continue
;
uint64_t
Depth
=
MI
->
getOperand
(
i
)
.
getImm
(
)
;
if
(
!
Printed
.
insert
(
Depth
)
.
second
)
continue
;
const
auto
&
Pair
=
ControlFlowStack
.
rbegin
(
)
[
Depth
]
;
printAnnotation
(
OS
,
utostr
(
Depth
)
+
": "
+
(
Pair
.
second
"up"
:
"down"
)
+
" to label"
+
utostr
(
Pair
.
first
)
)
;
}
}
}
</s>

Print the specified MCInst to the specified raw_ostream .


<s> bool isValid ( ) const { return ScalableBytes % 2 == 0 ; } </s>

Returns true if this iterator is still pointing at a valid entry .


<s> int hard_regno_mode_ok ( int regno , enum machine_mode mode ) { switch ( GET_MODE_SIZE ( mode ) ) { case 8 : return S_REGNO_P ( regno ) && m68hc11_soft_reg_count >= 4 ; case 4 : return ( X_REGNO_P ( regno ) || ( S_REGNO_P ( regno ) && m68hc11_soft_reg_count >= 2 ) ) ; case 2 : return G_REGNO_P ( regno ) ; case 1 : return G_REGNO_P ( regno ) && ! SP_REGNO_P ( regno ) ; default : return 0 ; } } </s>

Value is 1 if hard register REGNO can hold a value of machine-mode MODE .


"AltiVec argument passed to unprototyped function"

Target hook for invalid_arg_for_unprototyped_fn .


<s> const TargetRegisterClass * RISCVRegisterInfo :: getPointerRegClass ( const MachineFunction & MF , unsigned Kind ) const { return & RISCV :: GPRRegClass ; } </s>

getPointerRegClass - Returns a TargetRegisterClass used for pointer values .


<s>
const
char
*
rs6000_insn_for_and_mask
(
machine_mode
mode
,
rtx
*
operands
,
bool
dot
)
{
int
nb
,
ne
;
if
(
!
rs6000_is_valid_mask
(
operands
[
2
]
,
&
nb
,
&
ne
,
mode
)
)
gcc_unreachable
(
)
;
if
(
mode
==
DImode
&&
ne
==
0
)
{
operands
[
3
]
=
GEN_INT
(
63
nb
)
;
if
(
dot
)
return
"rldicl. %0,%1,0,%3"
;
return
"rldicl %0,%1,0,%3"
;
}
if
(
mode
==
DImode
&&
nb
==
63
)
{
operands
[
3
]
=
GEN_INT
(
63
ne
)
;
if
(
dot
)
return
"rldicr. %0,%1,0,%3"
;
return
"rldicr %0,%1,0,%3"
;
}
if
(
nb
<
32
&&
ne
<
32
)
{
operands
[
3
]
=
GEN_INT
(
31
nb
)
;
operands
[
4
]
=
GEN_INT
(
31
ne
)
;
if
(
dot
)
return
"rlwinm. %0,%1,0,%3,%4"
;
return
"rlwinm %0,%1,0,%3,%4"
;
}
gcc_unreachable
(
)
;
}
</s>

Return the instruction template for an AND with mask in mode MODE , with operands OPERANDS . If DOT is true , make it a record-form instruction .


<s> std :: pair < unsigned , const TargetRegisterClass * > SystemZTargetLowering :: getRegForInlineAsmConstraint ( const std :: string & Constraint , EVT VT ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { default : break ; case 'd' : case 'r' : if ( VT == MVT :: i64 ) return std :: make_pair ( 0U , & SystemZ :: GR64BitRegClass ) ; else if ( VT == MVT :: i128 ) return std :: make_pair ( 0U , & SystemZ :: GR128BitRegClass ) ; return std :: make_pair ( 0U , & SystemZ :: GR32BitRegClass ) ; case 'a' : if ( VT == MVT :: i64 ) return std :: make_pair ( 0U , & SystemZ :: ADDR64BitRegClass ) ; else if ( VT == MVT :: i128 ) return std :: make_pair ( 0U , & SystemZ :: ADDR128BitRegClass ) ; return std :: make_pair ( 0U , & SystemZ :: ADDR32BitRegClass ) ; case 'f' : if ( VT == MVT :: f64 ) return std :: make_pair ( 0U , & SystemZ :: FP64BitRegClass ) ; else if ( VT == MVT :: f128 ) return std :: make_pair ( 0U , & SystemZ :: FP128BitRegClass ) ; return std :: make_pair ( 0U , & SystemZ :: FP32BitRegClass ) ; } } return TargetLowering :: getRegForInlineAsmConstraint ( Constraint , VT ) ; } </s>

Given a physical register constraint ( e.g .


<s> int getRegTmpIndex ( void ) const { return hasTinyEncoding ( ) ? 16 : 0 ; } </s>


<s> static int push_reg ( rtx reg ) { rtx stkslot = gen_rtx_MEM ( GET_MODE ( reg ) , gen_rtx_PRE_DEC ( Pmode , stack_pointer_rtx ) ) ; rtx insn = emit_move_insn ( stkslot , reg ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; add_reg_note ( insn , REG_CFA_ADJUST_CFA , gen_rtx_SET ( stack_pointer_rtx , plus_constant ( Pmode , stack_pointer_rtx , - GET_MODE_SIZE ( GET_MODE ( reg ) ) ) ) ) ; return GET_MODE_SIZE ( GET_MODE ( reg ) ) ; } </s>

Helper used when saving AUX regs during ISR .


<s> MCSymbol * WebAssemblyMCInstLower :: GetExternalSymbolSymbol ( const MachineOperand & MO ) const { return Printer . GetExternalSymbolSymbol ( MO . getSymbolName ( ) ) ; } </s>

Return the MCSymbol for the specified ExternalSymbol .


<s> void ARMBaseRegisterInfo :: emitLoadConstPool ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator & MBBI , const DebugLoc & dl , Register DestReg , unsigned SubIdx , int Val , ARMCC :: CondCodes Pred , Register PredReg , unsigned MIFlags ) const { MachineFunction & MF = * MBB . getParent ( ) ; const TargetInstrInfo & TII = * MF . getSubtarget ( ) . getInstrInfo ( ) ; MachineConstantPool * ConstantPool = MF . getConstantPool ( ) ; const Constant * C = ConstantInt :: get ( Type :: getInt32Ty ( MF . getFunction ( ) . getContext ( ) ) , Val ) ; unsigned Idx = ConstantPool -> getConstantPoolIndex ( C , 4 ) ; BuildMI ( MBB , MBBI , dl , TII . get ( ARM :: LDRcp ) ) . addReg ( DestReg , getDefRegState ( true ) , SubIdx ) . addConstantPoolIndex ( Idx ) . addImm ( 0 ) . add ( predOps ( Pred , PredReg ) ) . setMIFlags ( MIFlags ) ; } </s>

emitLoadConstPool - Emits a load from constpool to materialize the specified immediate .


<s> const char * nvptx_output_simt_enter ( rtx dest , rtx size , rtx align ) { nvptx_output_unisimt_switch ( asm_out_file , true ) ; nvptx_output_softstack_switch ( asm_out_file , true , dest , size , align ) ; return "" ; } </s>

Output code to enter non-uniform execution region . DEST is a register to hold a per-lane allocation given by SIZE and ALIGN .


<s> static void nds32_group_float_insns ( rtx_insn * insn ) { df_ref def_record , use_record ; df_link * link ; rtx_insn * use_insn = NULL ; rtx group_id ; def_record = DF_INSN_DEFS ( insn ) ; for ( link = DF_REF_CHAIN ( def_record ) ; link ; link = link -> next ) { if ( ! DF_REF_INSN_INFO ( link -> ref ) ) continue ; use_insn = DF_REF_INSN ( link -> ref ) ; if ( ! dominated_by_p ( CDI_DOMINATORS , BLOCK_FOR_INSN ( use_insn ) , BLOCK_FOR_INSN ( insn ) ) ) return ; use_record = DF_INSN_USES ( use_insn ) ; if ( DF_REF_CHAIN ( use_record ) && DF_REF_CHAIN ( use_record ) -> next ) return ; if ( ! active_insn_p ( use_insn ) ) return ; if ( ! nds32_float_reg_load_store_p ( use_insn ) || find_post_update_rtx ( use_insn ) != - 1 ) return ; } group_id = GEN_INT ( nds32_alloc_relax_group_id ( ) ) ; emit_insn_before ( gen_relax_group ( group_id ) , insn ) ; for ( link = DF_REF_CHAIN ( def_record ) ; link ; link = link -> next ) { if ( ! DF_REF_INSN_INFO ( link -> ref ) ) continue ; use_insn = DF_REF_INSN ( link -> ref ) ; emit_insn_before ( gen_relax_group ( group_id ) , use_insn ) ; } } </s>

Group float load-store instructions : la $ ra , symbol flsi $ rt , [ $ ra + offset ]


<s> void emitBundleUnlock ( ) override { } </s>


<s>
SDValue
VETargetLowering
::
withTargetFlags
(
SDValue
Op
,
unsigned
TF
,
SelectionDAG
&
DAG
)
const
{
if
(
const
GlobalAddressSDNode
*
GA
=
dyn_cast
<
GlobalAddressSDNode
>
(
Op
)
)
return
DAG
.
getTargetGlobalAddress
(
GA
->
getGlobal
(
)
,
SDLoc
(
GA
)
,
GA
->
getValueType
(
0
)
,
GA
->
getOffset
(
)
,
TF
)
;
if
(
const
BlockAddressSDNode
*
BA
=
dyn_cast
<
BlockAddressSDNode
>
(
Op
)
)
return
DAG
.
getTargetBlockAddress
(
BA
->
getBlockAddress
(
)
,
Op
.
getValueType
(
)
,
0
,
TF
)
;
if
(
const
ConstantPoolSDNode
*
CP
=
dyn_cast
<
ConstantPoolSDNode
>
(
Op
)
)
return
DAG
.
getTargetConstantPool
(
CP
->
getConstVal
(
)
,
CP
->
getValueType
(
0
)
,
CP
->
getAlign
(
)
,
CP
->
getOffset
(
)
,
TF
)
;
if
(
const
ExternalSymbolSDNode
*
ES
=
dyn_cast
<
ExternalSymbolSDNode
>
(
Op
)
)
return
DAG
.
getTargetExternalSymbol
(
ES
->
getSymbol
(
)
,
ES
->
getValueType
(
0
)
,
TF
)
;
llvm_unreachable
(
"Unhandled address SDNode"
)
;
}
</s>


<s> void GCNMinRegScheduler :: releaseSuccessors ( const SUnit * SU , int Priority ) { for ( const auto & S : SU -> Succs ) { auto SuccSU = S . getSUnit ( ) ; if ( S . isWeak ( ) ) continue ; assert ( SuccSU -> isBoundaryNode ( ) || getNumPreds ( SuccSU ) > 0 ) ; if ( ! SuccSU -> isBoundaryNode ( ) && decNumPreds ( SuccSU ) == 0 ) RQ . push_front ( * new ( Alloc . Allocate ( ) ) Candidate ( SuccSU , Priority ) ) ; } } </s>

releaseSuccessors - Call releaseSucc on each of SU 's successors .


"argument type: isvoid = %d, isconst = %d, isvector = %d, "

"issigned = %d, isunsigned = %d, isbool = %d, ispixel = %d, "

"ispointer = %d, base = %d, restr = %d, val1 = \"%s\", "


<s> unsigned AArch64RegisterInfo :: getRegPressureLimit ( const TargetRegisterClass * RC , MachineFunction & MF ) const { const AArch64FrameLowering * TFI = getFrameLowering ( MF ) ; switch ( RC -> getID ( ) ) { default : return 0 ; case AArch64 :: GPR32RegClassID : case AArch64 :: GPR32spRegClassID : case AArch64 :: GPR32allRegClassID : case AArch64 :: GPR64spRegClassID : case AArch64 :: GPR64allRegClassID : case AArch64 :: GPR64RegClassID : case AArch64 :: GPR32commonRegClassID : case AArch64 :: GPR64commonRegClassID : return 32 - 1 - ( TFI -> hasFP ( MF ) || TT . isOSDarwin ( ) ) - MF . getSubtarget < AArch64Subtarget > ( ) . isX18Reserved ( ) - MF . getSubtarget < AArch64Subtarget > ( ) . isX20Reserved ( ) - hasBasePointer ( MF ) ; case AArch64 :: FPR8RegClassID : case AArch64 :: FPR16RegClassID : case AArch64 :: FPR32RegClassID : case AArch64 :: FPR64RegClassID : case AArch64 :: FPR128RegClassID : return 32 ; case AArch64 :: DDRegClassID : case AArch64 :: DDDRegClassID : case AArch64 :: DDDDRegClassID : case AArch64 :: QQRegClassID : case AArch64 :: QQQRegClassID : case AArch64 :: QQQQRegClassID : return 32 ; case AArch64 :: FPR128_loRegClassID : return 16 ; } } </s>

Return the register pressure `` high water mark '' for the specific register class .


<s> static int mips_symbol_insns ( enum mips_symbol_type type , machine_mode mode ) { return mips_symbol_insns_1 ( type , mode ) * ( TARGET_MIPS16 ? 2 : 1 ) ; } </s>

Return the number of instructions needed to load a symbol of the given type into a register . If valid in an address , the same number of instructions are needed for loads and stores . Treat extended mips16 instructions as two instructions .


<s> bool GCNPassConfig :: addInstSelector ( ) { AMDGPUPassConfig :: addInstSelector ( ) ; addPass ( createSILowerI1CopiesPass ( ) ) ; addPass ( & SIFixSGPRCopiesID ) ; return false ; } </s>

addInstSelector - This method should install an instruction selector pass , which converts from LLVM code to machine instructions .


<s> void rs6000_split_stack_space_check ( rtx size , rtx label ) { rtx sp = gen_rtx_REG ( Pmode , STACK_POINTER_REGNUM ) ; rtx limit = gen_reg_rtx ( Pmode ) ; rtx requested = gen_reg_rtx ( Pmode ) ; rtx cmp = gen_reg_rtx ( CCUNSmode ) ; rtx jump ; emit_insn ( gen_load_split_stack_limit ( limit ) ) ; if ( CONST_INT_P ( size ) ) emit_insn ( gen_add3_insn ( requested , sp , GEN_INT ( - INTVAL ( size ) ) ) ) ; else { size = force_reg ( Pmode , size ) ; emit_move_insn ( requested , gen_rtx_MINUS ( Pmode , sp , size ) ) ; } emit_insn ( gen_rtx_SET ( cmp , gen_rtx_COMPARE ( CCUNSmode , requested , limit ) ) ) ; jump = gen_rtx_IF_THEN_ELSE ( VOIDmode , gen_rtx_GEU ( VOIDmode , cmp , const0_rtx ) , gen_rtx_LABEL_REF ( VOIDmode , label ) , pc_rtx ) ; jump = emit_jump_insn ( gen_rtx_SET ( pc_rtx , jump ) ) ; JUMP_LABEL ( jump ) = label ; } </s>

Emit -fsplit-stack dynamic stack allocation space check .


"********** MI Converging Scheduling VLIW "

"** VLIWMachineScheduler::schedule picking next node\n"

Schedule - This is called back from ScheduleDAGInstrs : :Run ( ) when it 's time to do some work .


<s> static bool vr4130_true_reg_dependence_p ( rtx insn ) { note_stores ( PATTERN ( vr4130_last_insn ) , vr4130_true_reg_dependence_p_1 , & insn ) ; return insn == 0 ; } </s>

Return true if there is true register dependence between vr4130_last_insn and INSN .


<s>
bool
processBlock
(
MachineBasicBlock
&
MBB
)
{
bool
Changed
=
false
;
bool
Is64Bit
=
MBB
.
getParent
(
)
->
getSubtarget
<
PPCSubtarget
>
(
)
.
isPPC64
(
)
;
for
(
MachineBasicBlock
::
iterator
I
=
MBB
.
begin
(
)
,
IE
=
MBB
.
end
(
)
;
I
!=
IE
;
++
I
)
{
MachineInstr
*
MI
=
I
;
if
(
MI
->
getOpcode
(
)
!=
PPC
::
ADDItlsgdLADDR
&&
MI
->
getOpcode
(
)
!=
PPC
::
ADDItlsldLADDR
&&
MI
->
getOpcode
(
)
!=
PPC
::
ADDItlsgdLADDR32
&&
MI
->
getOpcode
(
)
!=
PPC
::
ADDItlsldLADDR32
)
continue
;
DEBUG
(
dbgs
(
)
<<
"TLS Dynamic Call Fixup:\n    "
<<
*
MI
;
)
;
unsigned
OutReg
=
MI
->
getOperand
(
0
)
.
getReg
(
)
;
unsigned
InReg
=
MI
->
getOperand
(
1
)
.
getReg
(
)
;
DebugLoc
DL
=
MI
->
getDebugLoc
(
)
;
unsigned
GPR3
=
Is64Bit
PPC
::
X3
:
PPC
::
R3
;
unsigned
Opc1
,
Opc2
;
SmallVector
<
unsigned
,
4
>
OrigRegs
;
OrigRegs
.
push_back
(
OutReg
)
;
OrigRegs
.
push_back
(
InReg
)
;
OrigRegs
.
push_back
(
GPR3
)
;
switch
(
MI
->
getOpcode
(
)
)
{
default
:
llvm_unreachable
(
"Opcode inconsistency error"
)
;
case
PPC
::
ADDItlsgdLADDR
:
Opc1
=
PPC
::
ADDItlsgdL
;
Opc2
=
PPC
::
GETtlsADDR
;
break
;
case
PPC
::
ADDItlsldLADDR
:
Opc1
=
PPC
::
ADDItlsldL
;
Opc2
=
PPC
::
GETtlsldADDR
;
break
;
case
PPC
::
ADDItlsgdLADDR32
:
Opc1
=
PPC
::
ADDItlsgdL32
;
Opc2
=
PPC
::
GETtlsADDR32
;
break
;
case
PPC
::
ADDItlsldLADDR32
:
Opc1
=
PPC
::
ADDItlsldL32
;
Opc2
=
PPC
::
GETtlsldADDR32
;
break
;
}
MachineInstr
*
Addi
=
BuildMI
(
MBB
,
I
,
DL
,
TII
->
get
(
Opc1
)
,
GPR3
)
.
addReg
(
InReg
)
;
Addi
->
addOperand
(
MI
->
getOperand
(
2
)
)
;
MachineBasicBlock
::
iterator
First
=
I
;
First
;
MachineInstr
*
Call
=
(
BuildMI
(
MBB
,
I
,
DL
,
TII
->
get
(
Opc2
)
,
GPR3
)
.
addReg
(
GPR3
)
)
;
Call
->
addOperand
(
MI
->
getOperand
(
3
)
)
;
BuildMI
(
MBB
,
I
,
DL
,
TII
->
get
(
TargetOpcode
::
COPY
)
,
OutReg
)
.
addReg
(
GPR3
)
;
MachineBasicBlock
::
iterator
Last
=
I
;
Last
;
++
I
;
MI
->
removeFromParent
(
)
;
LIS
->
repairIntervalsInRange
(
&
MBB
,
First
,
Last
,
OrigRegs
)
;
Changed
=
true
;
}
return
Changed
;
}
</s>

processBlock - If there are any predecessors whose control can be threaded through to a successor , transform them now .


<s> void ELFAArch64AsmBackend :: applyFixup ( const MCFixup & Fixup , char * Data , unsigned DataSize , uint64_t Value , bool IsPCRel ) const { if ( ! IsLittleEndian && Fixup . getKind ( ) == FK_Data_4 ) { if ( isByteSwappedFixup ( Fixup . getValue ( ) ) ) Value = ByteSwap_32 ( unsigned ( Value ) ) ; } AArch64AsmBackend :: applyFixup ( Fixup , Data , DataSize , Value , IsPCRel ) ; } </s>

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


<s> bool SITargetLowering :: allowsMisalignedMemoryAccesses ( EVT VT , unsigned AddrSpace , unsigned Align , MachineMemOperand :: Flags Flags , bool * IsFast ) const { if ( IsFast ) * IsFast = false ; if ( VT == MVT :: Other || ( VT != MVT :: Other && VT . getSizeInBits ( ) > 1024 && VT . getStoreSize ( ) > 16 ) ) { return false ; } if ( AddrSpace == AMDGPUAS :: LOCAL_ADDRESS || AddrSpace == AMDGPUAS :: REGION_ADDRESS ) { bool AlignedBy4 = ( Align % 4 == 0 ) ; if ( IsFast ) * IsFast = AlignedBy4 ; return AlignedBy4 ; } if ( ! Subtarget -> hasUnalignedScratchAccess ( ) && ( AddrSpace == AMDGPUAS :: PRIVATE_ADDRESS || AddrSpace == AMDGPUAS :: FLAT_ADDRESS ) ) { bool AlignedBy4 = Align >= 4 ; if ( IsFast ) * IsFast = AlignedBy4 ; return AlignedBy4 ; } if ( Subtarget -> hasUnalignedBufferAccess ( ) ) { if ( IsFast ) { * IsFast = ( AddrSpace == AMDGPUAS :: CONSTANT_ADDRESS || AddrSpace == AMDGPUAS :: CONSTANT_ADDRESS_32BIT ) ? ( Align % 4 == 0 ) : true ; } return true ; } if ( VT . bitsLT ( MVT :: i32 ) ) return false ; if ( IsFast ) * IsFast = true ; return VT . bitsGT ( MVT :: i32 ) && Align % 4 == 0 ; } </s>

Returns true if the target allows unaligned memory accesses of the specified type .


<s> bool AArch64LoadStoreOpt :: runOnMachineFunction ( MachineFunction & Fn ) { Subtarget = & static_cast < const AArch64Subtarget & > ( Fn . getSubtarget ( ) ) ; TII = static_cast < const AArch64InstrInfo * > ( Subtarget -> getInstrInfo ( ) ) ; TRI = Subtarget -> getRegisterInfo ( ) ; ModifiedRegs . resize ( TRI -> getNumRegs ( ) ) ; UsedRegs . resize ( TRI -> getNumRegs ( ) ) ; bool Modified = false ; bool enableNarrowLdOpt = enableNarrowLdMerge ( Fn ) ; for ( auto & MBB : Fn ) Modified |= optimizeBlock ( MBB , enableNarrowLdOpt ) ; return Modified ; } </s>

runOnMachineFunction - Emit the function body .


<s> rtx find_addr_reg ( rtx addr ) { while ( GET_CODE ( addr ) == PLUS ) { if ( REG_P ( XEXP ( addr , 0 ) ) && REGNO ( XEXP ( addr , 0 ) ) != 0 ) addr = XEXP ( addr , 0 ) ; else if ( REG_P ( XEXP ( addr , 1 ) ) && REGNO ( XEXP ( addr , 1 ) ) != 0 ) addr = XEXP ( addr , 1 ) ; else if ( CONSTANT_P ( XEXP ( addr , 0 ) ) ) addr = XEXP ( addr , 1 ) ; else if ( CONSTANT_P ( XEXP ( addr , 1 ) ) ) addr = XEXP ( addr , 0 ) ; else gcc_unreachable ( ) ; } gcc_assert ( REG_P ( addr ) && REGNO ( addr ) != 0 ) ; return addr ; } </s>

Return a REG that occurs in ADDR with coefficient 1 . ADDR can be effectively incremented by incrementing REG . r0 is special and we must not select it as an address register by this routine since our caller will try to increment the returned register via an `` la '' instruction .


<s> bool SIInstrInfo :: hasVALU32BitEncoding ( unsigned Opcode ) const { int Op32 = AMDGPU :: getVOPe32 ( Opcode ) ; if ( Op32 == - 1 ) return false ; return pseudoToMCOpcode ( Op32 ) != - 1 ; } </s>

Return true if this 64-bit VALU instruction has a 32-bit encoding .


<s> int arm_const_double_rtx ( rtx x ) { REAL_VALUE_TYPE r ; int i ; if ( ! fp_consts_inited ) init_fp_table ( ) ; REAL_VALUE_FROM_CONST_DOUBLE ( r , x ) ; if ( REAL_VALUE_MINUS_ZERO ( r ) ) return 0 ; for ( i = 0 ; i < fp_consts_inited ; i ++ ) if ( REAL_VALUES_EQUAL ( r , values_fp [ i ] ) ) return 1 ; return 0 ; } </s>

Return TRUE if rtx X is a valid immediate FP constant .


<s> void CSKYAsmPrinter :: emitEndOfAsmFile ( Module & M ) { CSKYTargetStreamer & CTS = static_cast < CSKYTargetStreamer & > ( * OutStreamer -> getTargetStreamer ( ) ) ; if ( TM . getTargetTriple ( ) . isOSBinFormatELF ( ) ) CTS . finishAttributeSection ( ) ; } </s>

This virtual method can be overridden by targets that want to emit something at the end of their file .


<s> static void rs6000_emit_madd ( rtx target , rtx m1 , rtx m2 , rtx a ) { machine_mode mode = GET_MODE ( target ) ; rtx dst ; dst = expand_ternary_op ( mode , fma_optab , m1 , m2 , a , target , 0 ) ; gcc_assert ( dst != NULL ) ; if ( dst != target ) emit_move_insn ( target , dst ) ; } </s>


<s> static void nvptx_call_args ( rtx arg , tree funtype ) { if ( cfun -> machine -> start_call == NULL_RTX ) { cfun -> machine -> call_args = NULL ; cfun -> machine -> funtype = funtype ; cfun -> machine -> start_call = const0_rtx ; } if ( arg == pc_rtx ) return ; rtx_expr_list * args_so_far = cfun -> machine -> call_args ; if ( REG_P ( arg ) ) cfun -> machine -> call_args = alloc_EXPR_LIST ( VOIDmode , arg , args_so_far ) ; } </s>

Implement the TARGET_CALL_ARGS hook . Record information about one argument to the next call .


<s> unsigned AArch64RegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { const TargetFrameLowering * TFI = MF . getTarget ( ) . getFrameLowering ( ) ; if ( TFI -> hasFP ( MF ) ) return AArch64 :: X29 ; else return AArch64 :: XSP ; } </s>


<s> static void mmix_reorg ( void ) { int regno ; for ( regno = MMIX_LAST_STACK_REGISTER_REGNUM ; regno >= 0 ; regno -- ) if ( ( df_regs_ever_live_p ( regno ) && ! call_used_regs [ regno ] ) || ( regno == MMIX_FRAME_POINTER_REGNUM && frame_pointer_needed ) ) break ; if ( ! TARGET_ABI_GNU && regno < crtl -> args . info . regs - 1 ) { regno = crtl -> args . info . regs - 1 ; if ( regno > MMIX_RETURN_VALUE_REGNUM - 1 ) regno = MMIX_RETURN_VALUE_REGNUM - 1 ; } cfun -> machine -> highest_saved_stack_register = regno ; } </s>

Implement TARGET_MACHINE_DEPENDENT_REORG . No actual rearrangements done here ; just virtually by calculating the highest saved stack register number used to modify the register numbers at output time .


<s> TargetPassConfig * NVPTXTargetMachine :: createPassConfig ( PassManagerBase & PM ) { return new NVPTXPassConfig ( this , PM ) ; } </s>

Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of CodeGen passes .


<s> bool AArch64FrameLowering :: canUseRedZone ( const MachineFunction & MF ) const { if ( ! EnableRedZone ) return false ; if ( MF . getFunction ( ) -> hasFnAttribute ( Attribute :: NoRedZone ) ) return false ; const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const AArch64FunctionInfo * AFI = MF . getInfo < AArch64FunctionInfo > ( ) ; unsigned NumBytes = AFI -> getLocalStackSize ( ) ; if ( MFI -> hasCalls ( ) || hasFP ( MF ) || NumBytes > 128 ) return false ; return true ; } </s>

Can this function use the red zone for local allocations .


<s> bool isTarget64BitILP32 ( ) const { return In64BitMode && ( TargetTriple . isX32 ( ) || TargetTriple . isOSNaCl ( ) ) ; } </s>

Is this x86_64 with the ILP32 programming model ( x32 ABI ) ?


<s>
static
void
m68hc11_file_start
(
void
)
{
default_file_start
(
)
;
fprintf
(
asm_out_file
,
"\t.mode %s\n"
,
TARGET_SHORT
"mshort"
:
"mlong"
)
;
}
</s>

Worker function for TARGET_ASM_FILE_START .


<s> Align getABIAlignmentForCallingConv ( Type * ArgTy , DataLayout DL ) const override { const Align ABIAlign ( DL . getABITypeAlignment ( ArgTy ) ) ; if ( ArgTy -> isVectorTy ( ) ) return std :: min ( ABIAlign , Align ( 8 ) ) ; return ABIAlign ; } </s>

Return the correct alignment for the current calling convention .


<s> void MOSCallLowering :: splitToValueTypes ( const ArgInfo & OrigArg , SmallVectorImpl < ArgInfo > & SplitArgs , const DataLayout & DL ) const { size_t OldSize = SplitArgs . size ( ) ; CallLowering :: splitToValueTypes ( OrigArg , SplitArgs , DL , CallingConv :: C ) ; auto NewArgs = make_range ( SplitArgs . begin ( ) + OldSize , SplitArgs . end ( ) ) ; SmallVector < LLT > SplitLLTs ; computeValueLLTs ( DL , * OrigArg . Ty , SplitLLTs ) ; assert ( ( size_t ) size ( NewArgs ) == SplitLLTs . size ( ) ) ; for ( const auto & I : zip ( NewArgs , SplitLLTs ) ) apply_tuple ( adjustArgFlags , I ) ; } </s>

Break OrigArgInfo into one or more pieces the calling convention can process , returned in SplitArgs .


<s> unsigned HexagonInstrInfo :: isStoreToStackSlot ( const MachineInstr & MI , int & FrameIndex ) const { switch ( MI . getOpcode ( ) ) { default : break ; case Hexagon :: S2_storerb_io : case Hexagon :: S2_storerh_io : case Hexagon :: S2_storeri_io : case Hexagon :: S2_storerd_io : case Hexagon :: V6_vS32b_ai : case Hexagon :: V6_vS32b_ai_128B : case Hexagon :: V6_vS32Ub_ai : case Hexagon :: V6_vS32Ub_ai_128B : case Hexagon :: STriw_pred : case Hexagon :: STriw_mod : case Hexagon :: STriq_pred_V6 : case Hexagon :: STriq_pred_vec_V6 : case Hexagon :: STriv_pseudo_V6 : case Hexagon :: STrivv_pseudo_V6 : case Hexagon :: STriq_pred_V6_128B : case Hexagon :: STriq_pred_vec_V6_128B : case Hexagon :: STriv_pseudo_V6_128B : case Hexagon :: STrivv_pseudo_V6_128B : { const MachineOperand & OpFI = MI . getOperand ( 0 ) ; if ( ! OpFI . isFI ( ) ) return 0 ; const MachineOperand & OpOff = MI . getOperand ( 1 ) ; if ( ! OpOff . isImm ( ) || OpOff . getImm ( ) != 0 ) return 0 ; FrameIndex = OpFI . getIndex ( ) ; return MI . getOperand ( 2 ) . getReg ( ) ; } case Hexagon :: S2_pstorerbt_io : case Hexagon :: S2_pstorerbf_io : case Hexagon :: S2_pstorerht_io : case Hexagon :: S2_pstorerhf_io : case Hexagon :: S2_pstorerit_io : case Hexagon :: S2_pstorerif_io : case Hexagon :: S2_pstorerdt_io : case Hexagon :: S2_pstorerdf_io : { const MachineOperand & OpFI = MI . getOperand ( 1 ) ; if ( ! OpFI . isFI ( ) ) return 0 ; const MachineOperand & OpOff = MI . getOperand ( 2 ) ; if ( ! OpOff . isImm ( ) || OpOff . getImm ( ) != 0 ) return 0 ; FrameIndex = OpFI . getIndex ( ) ; return MI . getOperand ( 3 ) . getReg ( ) ; } } return 0 ; } </s>

isStoreToStackSlot - If the specified machine instruction is a direct store to a stack slot , return the virtual or physical register number of the source reg along with the FrameIndex of the loaded stack slot .


<s> bool SIAnnotateControlFlow :: doInitialization ( Module & M ) { LLVMContext & Context = M . getContext ( ) ; Void = Type :: getVoidTy ( Context ) ; Boolean = Type :: getInt1Ty ( Context ) ; Int64 = Type :: getInt64Ty ( Context ) ; ReturnStruct = StructType :: get ( Boolean , Int64 , ( Type * ) nullptr ) ; BoolTrue = ConstantInt :: getTrue ( Context ) ; BoolFalse = ConstantInt :: getFalse ( Context ) ; BoolUndef = UndefValue :: get ( Boolean ) ; Int64Zero = ConstantInt :: get ( Int64 , 0 ) ; If = M . getOrInsertFunction ( IfIntrinsic , ReturnStruct , Boolean , ( Type * ) nullptr ) ; Else = M . getOrInsertFunction ( ElseIntrinsic , ReturnStruct , Int64 , ( Type * ) nullptr ) ; Break = M . getOrInsertFunction ( BreakIntrinsic , Int64 , Int64 , ( Type * ) nullptr ) ; IfBreak = M . getOrInsertFunction ( IfBreakIntrinsic , Int64 , Boolean , Int64 , ( Type * ) nullptr ) ; ElseBreak = M . getOrInsertFunction ( ElseBreakIntrinsic , Int64 , Int64 , Int64 , ( Type * ) nullptr ) ; Loop = M . getOrInsertFunction ( LoopIntrinsic , Boolean , Int64 , ( Type * ) nullptr ) ; EndCf = M . getOrInsertFunction ( EndCfIntrinsic , Void , Int64 , ( Type * ) nullptr ) ; return false ; } </s>

Set up the AsmPrinter when we are working on a new module .


<s> static rtx rs6000_spe_function_arg ( const CUMULATIVE_ARGS * cum , machine_mode mode , const_tree type ) { int gregno = cum -> sysv_gregno ; if ( TARGET_E500_DOUBLE && ( mode == DFmode || mode == TFmode || mode == DCmode || mode == TCmode ) ) { int n_words = rs6000_arg_size ( mode , type ) ; if ( mode == DFmode ) gregno += ( 1 - gregno ) & 1 ; if ( gregno + n_words - 1 > GP_ARG_MAX_REG ) return NULL_RTX ; return spe_build_register_parallel ( mode , gregno ) ; } if ( cum -> stdarg ) { int n_words = rs6000_arg_size ( mode , type ) ; if ( n_words == 2 && ( gregno & 1 ) == 0 ) gregno += 1 ; if ( gregno + n_words - 1 <= GP_ARG_MAX_REG ) { rtx r1 , r2 ; machine_mode m = SImode ; r1 = gen_rtx_REG ( m , gregno ) ; r1 = gen_rtx_EXPR_LIST ( m , r1 , const0_rtx ) ; r2 = gen_rtx_REG ( m , gregno + 1 ) ; r2 = gen_rtx_EXPR_LIST ( m , r2 , GEN_INT ( 4 ) ) ; return gen_rtx_PARALLEL ( mode , gen_rtvec ( 2 , r1 , r2 ) ) ; } else return NULL_RTX ; } else { if ( gregno <= GP_ARG_MAX_REG ) return gen_rtx_REG ( mode , gregno ) ; else return NULL_RTX ; } } </s>

Determine where to put a SIMD argument on the SPE .


"Chain: broken invariant. A Chain can only be killed after its last "


<s> TargetLowering :: ConstraintWeight SystemZTargetLowering :: getSingleConstraintMatchWeight ( AsmOperandInfo & info , const char * constraint ) const { ConstraintWeight weight = CW_Invalid ; Value * CallOperandVal = info . CallOperandVal ; if ( CallOperandVal == NULL ) return CW_Default ; Type * type = CallOperandVal -> getType ( ) ; switch ( * constraint ) { default : weight = TargetLowering :: getSingleConstraintMatchWeight ( info , constraint ) ; break ; case 'a' : case 'd' : case 'h' : case 'r' : if ( CallOperandVal -> getType ( ) -> isIntegerTy ( ) ) weight = CW_Register ; break ; case 'f' : if ( type -> isFloatingPointTy ( ) ) weight = CW_Register ; break ; case 'I' : if ( ConstantInt * C = dyn_cast < ConstantInt > ( CallOperandVal ) ) if ( isUInt < 8 > ( C -> getZExtValue ( ) ) ) weight = CW_Constant ; break ; case 'J' : if ( ConstantInt * C = dyn_cast < ConstantInt > ( CallOperandVal ) ) if ( isUInt < 12 > ( C -> getZExtValue ( ) ) ) weight = CW_Constant ; break ; case 'K' : if ( ConstantInt * C = dyn_cast < ConstantInt > ( CallOperandVal ) ) if ( isInt < 16 > ( C -> getSExtValue ( ) ) ) weight = CW_Constant ; break ; case 'L' : if ( ConstantInt * C = dyn_cast < ConstantInt > ( CallOperandVal ) ) if ( isInt < 20 > ( C -> getSExtValue ( ) ) ) weight = CW_Constant ; break ; case 'M' : if ( ConstantInt * C = dyn_cast < ConstantInt > ( CallOperandVal ) ) if ( C -> getZExtValue ( ) == 0x7fffffff ) weight = CW_Constant ; break ; } return weight ; } </s>

Examine constraint string and operand type and determine a weight value .


<s>
void
ARMTargetLowering
::
HandleByVal
(
CCState
*
State
,
unsigned
&
size
,
unsigned
Align
)
const
{
unsigned
reg
=
State
->
AllocateReg
(
GPRArgRegs
,
4
)
;
assert
(
(
State
->
getCallOrPrologue
(
)
==
Prologue
||
State
->
getCallOrPrologue
(
)
==
Call
)
&&
"unhandled ParmContext"
)
;
if
(
(
ARM
::
R0
<=
reg
)
&&
(
reg
<=
ARM
::
R3
)
)
{
if
(
Subtarget
->
isAAPCS_ABI
(
)
&&
Align
>
4
)
{
unsigned
AlignInRegs
=
Align
/
4
;
unsigned
Waste
=
(
ARM
::
R4
reg
)
%
AlignInRegs
;
for
(
unsigned
i
=
0
;
i
<
Waste
;
++
i
)
reg
=
State
->
AllocateReg
(
GPRArgRegs
,
4
)
;
}
if
(
reg
!=
0
)
{
unsigned
excess
=
4
*
(
ARM
::
R4
reg
)
;
const
unsigned
NSAAOffset
=
State
->
getNextStackOffset
(
)
;
if
(
Subtarget
->
isAAPCS_ABI
(
)
&&
NSAAOffset
!=
0
&&
size
>
excess
)
{
while
(
State
->
AllocateReg
(
GPRArgRegs
,
4
)
)
;
return
;
}
unsigned
ByValRegBegin
=
reg
;
unsigned
ByValRegEnd
=
(
size
<
excess
)
reg
+
size
/
4
:
(
unsigned
)
ARM
::
R4
;
State
->
addInRegsParamInfo
(
ByValRegBegin
,
ByValRegEnd
)
;
for
(
unsigned
i
=
reg
+
1
;
i
!=
ByValRegEnd
;
++
i
)
State
->
AllocateReg
(
GPRArgRegs
,
4
)
;
if
(
size
<
excess
)
size
=
0
;
else
size
-=
excess
;
}
}
}
</s>

Target-specific cleanup for formal ByVal parameters .


<s> uint32_t generateCompactUnwindEncoding ( ArrayRef < MCCFIInstruction > Instrs ) const override { return generateCompactUnwindEncodingImpl ( Instrs ) ; } </s>

Generate compact unwind encoding for the function based on the CFI instructions .


<s> static tree fold_build_vec_cmp ( tree_code code , tree type , tree arg0 , tree arg1 ) { tree cmp_type = truth_type_for ( type ) ; tree zero_vec = build_zero_cst ( type ) ; tree minus_one_vec = build_minus_one_cst ( type ) ; tree cmp = fold_build2 ( code , cmp_type , arg0 , arg1 ) ; return fold_build3 ( VEC_COND_EXPR , type , cmp , minus_one_vec , zero_vec ) ; } </s>

Helper function to handle the gimple folding of a vector compare operation . This sets up true/false vectors , and uses the VEC_COND_EXPR operation . CODE indicates which comparison is to be made . ( EQ , GT , ... ) . TYPE indicates the type of the result .


A helper function to handle isr stuff at the end of asm file .


<s> bool runOnMachineFunction ( MachineFunction & MF ) override { const TargetMachine & TM = MF . getTarget ( ) ; if ( MF . getFunction ( ) -> hasFnAttribute ( Attribute :: Naked ) ) return false ; if ( TM . getRelocationModel ( ) != Reloc :: PIC_ ) return false ; OR1KMachineFunctionInfo * OR1KFI = MF . getInfo < OR1KMachineFunctionInfo > ( ) ; unsigned GlobalBaseReg = OR1KFI -> getGlobalBaseReg ( ) ; if ( GlobalBaseReg == 0 ) return false ; MachineBasicBlock & FirstMBB = MF . front ( ) ; MachineBasicBlock :: iterator MBBI = FirstMBB . begin ( ) ; DebugLoc DL = FirstMBB . findDebugLoc ( MBBI ) ; MachineRegisterInfo & RegInfo = MF . getRegInfo ( ) ; const TargetInstrInfo * TII = MF . getSubtarget ( ) . getInstrInfo ( ) ; unsigned Scratch1 = RegInfo . createVirtualRegister ( & OR1K :: GPRRegClass ) ; unsigned Scratch2 = RegInfo . createVirtualRegister ( & OR1K :: GPRRegClass ) ; BuildMI ( FirstMBB , MBBI , DL , TII -> get ( OR1K :: GETPC ) ) . addImm ( 0 ) ; BuildMI ( FirstMBB , MBBI , DL , TII -> get ( OR1K :: MOVHI ) , Scratch1 ) . addExternalSymbol ( "_GLOBAL_OFFSET_TABLE_" , OR1KII :: MO_GOTPCHI ) ; BuildMI ( FirstMBB , MBBI , DL , TII -> get ( OR1K :: ORI ) , Scratch2 ) . addReg ( Scratch1 ) . addExternalSymbol ( "_GLOBAL_OFFSET_TABLE_" , OR1KII :: MO_GOTPCLO ) ; BuildMI ( FirstMBB , MBBI , DL , TII -> get ( OR1K :: ADD ) , GlobalBaseReg ) . addReg ( OR1K :: R9 ) . addReg ( Scratch2 ) ; return true ; } </s>

runOnMachineFunction - Emit the function body .


"Can only insert epilog into returning blocks"


<s>
void
SIScheduleBlock
::
addPred
(
SIScheduleBlock
*
Pred
)
{
unsigned
PredID
=
Pred
->
getID
(
)
;
for
(
SIScheduleBlock
*
P
:
Preds
)
{
if
(
PredID
==
P
->
getID
(
)
)
return
;
}
Preds
.
push_back
(
Pred
)
;
assert
(
none_of
(
Succs
,
[
=
]
(
std
::
pair
<
SIScheduleBlock
*
,
SIScheduleBlockLinkKind
>
S
)
{
return
PredID
==
S
.
first
->
getID
(
)
;
}
)
&&
"Loop in the Block Graph!"
)
;
}
</s>

Adds the specified edge as a pred of the current node if not already .

AMDGPU
SI
SI
SI
SI
SI
"Loop in the Block Graph!"


<s> bool PPCInstrInfo :: getMemOperandWithOffsetWidth ( const MachineInstr & LdSt , const MachineOperand * & BaseReg , int64_t & Offset , unsigned & Width , const TargetRegisterInfo * TRI ) const { if ( ! LdSt . mayLoadOrStore ( ) || LdSt . getNumExplicitOperands ( ) != 3 ) return false ; if ( ! LdSt . getOperand ( 1 ) . isImm ( ) || ( ! LdSt . getOperand ( 2 ) . isReg ( ) && ! LdSt . getOperand ( 2 ) . isFI ( ) ) ) return false ; if ( ! LdSt . getOperand ( 1 ) . isImm ( ) || ( ! LdSt . getOperand ( 2 ) . isReg ( ) && ! LdSt . getOperand ( 2 ) . isFI ( ) ) ) return false ; if ( ! LdSt . hasOneMemOperand ( ) ) return false ; Width = ( * LdSt . memoperands_begin ( ) ) -> getSize ( ) ; Offset = LdSt . getOperand ( 1 ) . getImm ( ) ; BaseReg = & LdSt . getOperand ( 2 ) ; return true ; } </s>

Return true if get the base operand , byte offset of an instruction and the memory width .


<s> const Z80InstrInfo * getInstrInfo ( ) const override { return & InstrInfo ; } </s>


<s> unsigned constant_generates_xxspltidp ( vec_const_128bit_type * vsx_const ) { if ( ! TARGET_SPLAT_FLOAT_CONSTANT || ! TARGET_PREFIXED || ! TARGET_VSX ) return 0 ; if ( ! vsx_const -> all_double_words_same ) return 0 ; if ( vsx_const -> all_bytes_same || vsx_const -> all_half_words_same || vsx_const -> all_words_same ) return 0 ; unsigned HOST_WIDE_INT value = vsx_const -> double_words [ 0 ] ; if ( value != RS6000_CONST_DF_NAN && value != RS6000_CONST_DF_NANS && value != RS6000_CONST_DF_INF && value != RS6000_CONST_DF_NEG_INF ) { int df_exponent = ( value >> 52 ) & 0x7ff ; unsigned HOST_WIDE_INT df_mantissa = value & ( ( HOST_WIDE_INT_1U << 52 ) - HOST_WIDE_INT_1U ) ; if ( df_exponent == 0x7ff && df_mantissa != 0 ) return 0 ; if ( df_exponent == 0 && df_mantissa != 0 ) return 0 ; } long df_words [ 2 ] = { vsx_const -> words [ 0 ] , vsx_const -> words [ 1 ] } ; if ( ! BYTES_BIG_ENDIAN ) std :: swap ( df_words [ 0 ] , df_words [ 1 ] ) ; REAL_VALUE_TYPE rv_type ; real_from_target ( & rv_type , df_words , DFmode ) ; const REAL_VALUE_TYPE * rv = & rv_type ; if ( ! exact_real_truncate ( SFmode , rv ) ) return 0 ; long sf_value ; real_to_target ( & sf_value , rv , SFmode ) ; long sf_exponent = ( sf_value >> 23 ) & 0xFF ; long sf_mantissa = sf_value & 0x7FFFFF ; if ( sf_exponent == 0 && sf_mantissa != 0 ) return 0 ; return sf_value ; } </s>

Determine if a vector constant can be loaded with XXSPLTIDP . Return zero if the XXSPLTIDP instruction can not be used . Otherwise return the immediate value to be used with the XXSPLTIDP instruction .


<s> const std :: string & ARMToTHMStub :: name ( ) const { return m_Name ; } </s>

Gets the name of the pass we are mixed into .


<s> virtual void getAnalysisUsage ( AnalysisUsage & AU ) const { AU . addRequired < LiveIntervals > ( ) ; AU . addPreserved < LiveIntervals > ( ) ; AU . addPreserved < SlotIndexes > ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s>
const
char
*
nios2_add_insn_asm
(
rtx_insn
*
insn
,
rtx
*
operands
)
{
static
char
buf
[
256
]
;
int
ln
=
256
;
enum
nios2_add_insn_kind
kind
=
nios2_add_insn_classify
(
insn
,
operands
[
0
]
,
operands
[
1
]
,
operands
[
2
]
)
;
if
(
kind
==
nios2_subi_n_kind
)
snprintf
(
buf
,
ln
,
"subi.n\t%%0, %%1, %d"
,
(
int
)
INTVAL
(
operands
[
2
]
)
)
;
else
if
(
kind
==
nios2_spaddi_n_kind
)
snprintf
(
buf
,
ln
,
"spaddi.n\t%%0, %%2"
)
;
else
if
(
kind
==
nios2_spinci_n_kind
)
snprintf
(
buf
,
ln
,
"spinci.n\t%%2"
)
;
else
if
(
kind
==
nios2_spdeci_n_kind
)
snprintf
(
buf
,
ln
,
"spdeci.n\t%d"
,
(
int
)
INTVAL
(
operands
[
2
]
)
)
;
else
snprintf
(
buf
,
ln
,
"%s\t%%0, %%1, %%z2"
,
nios2_add_insn_names
[
(
int
)
kind
]
)
;
return
buf
;
}
</s>

Emit assembly language for the different kinds of add instructions .


"Pseudo opcode found in EmitInstruction()"

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


"For each split Type there should be exactly one VReg."

This hook behaves as the extended lowerReturn function , but for targets that do not support swifterror value promotion .


<s> bool SystemZXPLINKFrameLowering :: hasFP ( const MachineFunction & MF ) const { return ( MF . getFrameInfo ( ) . hasVarSizedObjects ( ) ) ; } </s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .


<s> static rtx h8300_function_arg ( cumulative_args_t cum_v , machine_mode mode , const_tree type , bool named ) { CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; static const char * const hand_list [ ] = { "__main" , "__cmpsi2" , "__divhi3" , "__modhi3" , "__udivhi3" , "__umodhi3" , "__divsi3" , "__modsi3" , "__udivsi3" , "__umodsi3" , "__mulhi3" , "__mulsi3" , "__reg_memcpy" , "__reg_memset" , "__ucmpsi2" , 0 , } ; rtx result = NULL_RTX ; const char * fname ; int regpass = 0 ; if ( ! named ) return NULL_RTX ; if ( TARGET_QUICKCALL ) regpass = 3 ; if ( cum -> libcall ) { const char * const * p ; fname = XSTR ( cum -> libcall , 0 ) ; for ( p = hand_list ; * p && strcmp ( * p , fname ) != 0 ; p ++ ) ; if ( * p ) regpass = 4 ; } if ( regpass ) { int size ; if ( mode == BLKmode ) size = int_size_in_bytes ( type ) ; else size = GET_MODE_SIZE ( mode ) ; if ( size + cum -> nbytes <= regpass * UNITS_PER_WORD && cum -> nbytes / UNITS_PER_WORD <= 3 ) result = gen_rtx_REG ( mode , cum -> nbytes / UNITS_PER_WORD ) ; } return result ; } </s>

If the next function argument with MODE and TYPE is to be passed in a register , return a reg RTX for the hard register in which to pass the argument . CUM represents the state after the last argument . If the argument is to be pushed , NULL_RTX is returned . On the H8/300 all normal args are pushed , unless -mquickcall in which case the first 3 arguments are passed in registers .


<s> static void sparc_emit_set_const32 ( rtx op0 , rtx op1 ) { machine_mode mode = GET_MODE ( op0 ) ; rtx temp = op0 ; if ( can_create_pseudo_p ( ) ) temp = gen_reg_rtx ( mode ) ; if ( GET_CODE ( op1 ) == CONST_INT ) { gcc_assert ( ! small_int_operand ( op1 , mode ) && ! const_high_operand ( op1 , mode ) ) ; emit_insn ( gen_rtx_SET ( VOIDmode , temp , GEN_INT ( INTVAL ( op1 ) & ~ ( HOST_WIDE_INT ) 0x3ff ) ) ) ; emit_insn ( gen_rtx_SET ( VOIDmode , op0 , gen_rtx_IOR ( mode , temp , GEN_INT ( INTVAL ( op1 ) & 0x3ff ) ) ) ) ; } else { emit_insn ( gen_rtx_SET ( VOIDmode , temp , gen_rtx_HIGH ( mode , op1 ) ) ) ; emit_insn ( gen_rtx_SET ( VOIDmode , op0 , gen_rtx_LO_SUM ( mode , temp , op1 ) ) ) ; } } </s>

We know it ca n't be done in one insn when we get here , the movsi expander guarentees this .


<s> int arc_return_address_register ( unsigned int fn_type ) { int regno = 0 ; if ( ARC_INTERRUPT_P ( fn_type ) ) { if ( ( fn_type & ( ARC_FUNCTION_ILINK1 | ARC_FUNCTION_FIRQ ) ) != 0 ) regno = ILINK1_REG ; else if ( ( fn_type & ARC_FUNCTION_ILINK2 ) != 0 ) regno = ILINK2_REG ; else gcc_unreachable ( ) ; } else if ( ARC_NORMAL_P ( fn_type ) || ARC_NAKED_P ( fn_type ) ) regno = RETURN_ADDR_REGNUM ; gcc_assert ( regno != 0 ) ; return regno ; } </s>

Return the register number of the register holding the return address for a function of type TYPE .


<s> EVT PPCTargetLowering :: getOptimalMemOpType ( uint64_t Size , unsigned DstAlign , unsigned SrcAlign , bool IsMemset , bool ZeroMemset , bool MemcpyStrSrc , MachineFunction & MF ) const { if ( getTargetMachine ( ) . getOptLevel ( ) != CodeGenOpt :: None ) { const Function * F = MF . getFunction ( ) ; if ( Subtarget . hasQPX ( ) && Size >= 32 && ( ! IsMemset || Size >= 64 ) && ( ! SrcAlign || SrcAlign >= 32 ) && ( ! DstAlign || DstAlign >= 32 ) && ! F -> hasFnAttribute ( Attribute :: NoImplicitFloat ) ) { return MVT :: v4f64 ; } if ( Subtarget . hasAltivec ( ) && Size >= 16 && ( ( ( ! SrcAlign || SrcAlign >= 16 ) && ( ! DstAlign || DstAlign >= 16 ) ) || ( ( IsMemset && Subtarget . hasVSX ( ) ) || Subtarget . hasP8Vector ( ) ) ) ) return MVT :: v4i32 ; } if ( Subtarget . isPPC64 ( ) ) { return MVT :: i64 ; } return MVT :: i32 ; } </s>

It returns EVT : :Other if the type should be determined using generic target-independent logic .


<s> static unsigned arc_predicate_delay_insns ( void ) { for ( rtx_insn * insn = get_insns ( ) ; insn ; insn = NEXT_INSN ( insn ) ) { rtx pat , jump , dlay , src , cond , * patp ; int reverse ; if ( ! NONJUMP_INSN_P ( insn ) || GET_CODE ( pat = PATTERN ( insn ) ) != SEQUENCE ) continue ; jump = XVECEXP ( pat , 0 , 0 ) ; dlay = XVECEXP ( pat , 0 , 1 ) ; if ( ! JUMP_P ( jump ) || ! INSN_ANNULLED_BRANCH_P ( jump ) ) continue ; if ( ! TARGET_AT_DBR_CONDEXEC && ! INSN_FROM_TARGET_P ( dlay ) ) continue ; gcc_assert ( GET_CODE ( PATTERN ( jump ) ) == SET ) ; gcc_assert ( SET_DEST ( PATTERN ( jump ) ) == pc_rtx ) ; src = SET_SRC ( PATTERN ( jump ) ) ; gcc_assert ( GET_CODE ( src ) == IF_THEN_ELSE ) ; cond = XEXP ( src , 0 ) ; if ( XEXP ( src , 2 ) == pc_rtx ) reverse = 0 ; else if ( XEXP ( src , 1 ) == pc_rtx ) reverse = 1 ; else gcc_unreachable ( ) ; if ( reverse != ! INSN_FROM_TARGET_P ( dlay ) ) { machine_mode ccm = GET_MODE ( XEXP ( cond , 0 ) ) ; enum rtx_code code = reverse_condition ( GET_CODE ( cond ) ) ; if ( code == UNKNOWN || ccm == CC_FP_GTmode || ccm == CC_FP_GEmode ) code = reverse_condition_maybe_unordered ( GET_CODE ( cond ) ) ; cond = gen_rtx_fmt_ee ( code , GET_MODE ( cond ) , copy_rtx ( XEXP ( cond , 0 ) ) , copy_rtx ( XEXP ( cond , 1 ) ) ) ; } else cond = copy_rtx ( cond ) ; patp = & PATTERN ( dlay ) ; pat = * patp ; pat = conditionalize_nonjump ( pat , cond , dlay , true ) ; validate_change ( dlay , patp , pat , 1 ) ; if ( ! apply_change_group ( ) ) gcc_unreachable ( ) ; } return 0 ; } </s>

Find annulled delay insns and convert them to use the appropriate predicate . This allows branch shortening to size up these insns properly .


<s> void X86DAGToDAGISel :: PreprocessISelDAG ( ) { OptForSize = MF -> getFunction ( ) -> getAttributes ( ) . hasAttribute ( AttributeSet :: FunctionIndex , Attribute :: OptimizeForSize ) ; for ( SelectionDAG :: allnodes_iterator I = CurDAG -> allnodes_begin ( ) , E = CurDAG -> allnodes_end ( ) ; I != E ; ) { SDNode * N = I ++ ; if ( OptLevel != CodeGenOpt :: None && ( ( N -> getOpcode ( ) == X86ISD :: CALL && ! Subtarget -> callRegIndirect ( ) ) || ( N -> getOpcode ( ) == X86ISD :: TC_RETURN && ( Subtarget -> is64Bit ( ) || getTargetMachine ( ) . getRelocationModel ( ) != Reloc :: PIC_ ) ) ) ) { bool HasCallSeq = N -> getOpcode ( ) == X86ISD :: CALL ; SDValue Chain = N -> getOperand ( 0 ) ; SDValue Load = N -> getOperand ( 1 ) ; if ( ! isCalleeLoad ( Load , Chain , HasCallSeq ) ) continue ; MoveBelowOrigChain ( CurDAG , Load , SDValue ( N , 0 ) , Chain ) ; ++ NumLoadMoved ; continue ; } if ( N -> getOpcode ( ) != ISD :: FP_ROUND && N -> getOpcode ( ) != ISD :: FP_EXTEND ) continue ; EVT SrcVT = N -> getOperand ( 0 ) . getValueType ( ) ; EVT DstVT = N -> getValueType ( 0 ) ; if ( SrcVT . isVector ( ) || DstVT . isVector ( ) ) continue ; const X86TargetLowering * X86Lowering = static_cast < const X86TargetLowering * > ( getTargetLowering ( ) ) ; bool SrcIsSSE = X86Lowering -> isScalarFPTypeInSSEReg ( SrcVT ) ; bool DstIsSSE = X86Lowering -> isScalarFPTypeInSSEReg ( DstVT ) ; if ( SrcIsSSE && DstIsSSE ) continue ; if ( ! SrcIsSSE && ! DstIsSSE ) { if ( N -> getOpcode ( ) == ISD :: FP_EXTEND ) continue ; if ( N -> getConstantOperandVal ( 1 ) ) continue ; } EVT MemVT ; if ( N -> getOpcode ( ) == ISD :: FP_ROUND ) MemVT = DstVT ; else MemVT = SrcIsSSE ? SrcVT : DstVT ; SDValue MemTmp = CurDAG -> CreateStackTemporary ( MemVT ) ; SDLoc dl ( N ) ; SDValue Store = CurDAG -> getTruncStore ( CurDAG -> getEntryNode ( ) , dl , N -> getOperand ( 0 ) , MemTmp , MachinePointerInfo ( ) , MemVT , false , false , 0 ) ; SDValue Result = CurDAG -> getExtLoad ( ISD :: EXTLOAD , dl , DstVT , Store , MemTmp , MachinePointerInfo ( ) , MemVT , false , false , 0 ) ; -- I ; CurDAG -> ReplaceAllUsesOfValueWith ( SDValue ( N , 0 ) , Result ) ; ++ I ; CurDAG -> DeleteNode ( N ) ; } } </s>

PreprocessISelDAG - This hook allows targets to hack on the graph before instruction selection starts .


<s> void HexagonMCELFStreamer :: EmitInstruction ( const MCInst & MCK , const MCSubtargetInfo & STI ) { MCInst HMI = HexagonMCInstrInfo :: createBundle ( ) ; MCInst * MCB ; if ( MCK . getOpcode ( ) != Hexagon :: BUNDLE ) { HMI . addOperand ( MCOperand :: createInst ( & MCK ) ) ; MCB = & HMI ; } else MCB = const_cast < MCInst * > ( & MCK ) ; HexagonMCInstrInfo :: padEndloop ( getContext ( ) , * MCB ) ; HexagonMCShuffle ( * MCII , STI , * MCB ) ; assert ( HexagonMCInstrInfo :: bundleSize ( * MCB ) <= HEXAGON_PACKET_SIZE ) ; bool Extended = false ; for ( auto & I : HexagonMCInstrInfo :: bundleInstructions ( * MCB ) ) { MCInst * MCI = const_cast < MCInst * > ( I . getInst ( ) ) ; if ( Extended ) { if ( HexagonMCInstrInfo :: isDuplex ( * MCII , * MCI ) ) { MCInst * SubInst = const_cast < MCInst * > ( MCI -> getOperand ( 1 ) . getInst ( ) ) ; HexagonMCInstrInfo :: clampExtended ( * MCII , getContext ( ) , * SubInst ) ; } else { HexagonMCInstrInfo :: clampExtended ( * MCII , getContext ( ) , * MCI ) ; } Extended = false ; } else { Extended = HexagonMCInstrInfo :: isImmext ( * MCI ) ; } } for ( auto const & I : HexagonMCInstrInfo :: bundleInstructions ( * MCB ) ) { MCInst * MCI = const_cast < MCInst * > ( I . getInst ( ) ) ; EmitSymbol ( * MCI ) ; } MCObjectStreamer :: EmitInstruction ( * MCB , STI ) ; } </s>

Hexagon Hexagon Hexagon Hexagon::BUNDLE Hexagon Hexagon Hexagon Hexagon Hexagon 1 Hexagon Hexagon Hexagon Hexagon


<s> const uint16_t * PPCRegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { if ( Subtarget . isDarwinABI ( ) ) return Subtarget . isPPC64 ( ) ? CSR_Darwin64_SaveList : CSR_Darwin32_SaveList ; return Subtarget . isPPC64 ( ) ? CSR_SVR464_SaveList : CSR_SVR432_SaveList ; } </s>


<s>
void
RISCVDAGToDAGISel
::
Select
(
SDNode
*
Node
)
{
unsigned
Opcode
=
Node
->
getOpcode
(
)
;
MVT
XLenVT
=
Subtarget
->
getXLenVT
(
)
;
DEBUG
(
dbgs
(
)
<<
"Selecting: "
;
Node
->
dump
(
CurDAG
)
;
dbgs
(
)
<<
"\n"
)
;
if
(
Node
->
isMachineOpcode
(
)
)
{
DEBUG
(
dbgs
(
)
<<
"== "
;
Node
->
dump
(
CurDAG
)
;
dbgs
(
)
<<
"\n"
)
;
Node
->
setNodeId
(
1
)
;
return
;
}
EVT
VT
=
Node
->
getValueType
(
0
)
;
if
(
Opcode
==
ISD
::
Constant
&&
VT
==
XLenVT
)
{
auto
*
ConstNode
=
cast
<
ConstantSDNode
>
(
Node
)
;
if
(
ConstNode
->
isNullValue
(
)
)
{
SDValue
New
=
CurDAG
->
getCopyFromReg
(
CurDAG
->
getEntryNode
(
)
,
SDLoc
(
Node
)
,
RISCV
::
X0
,
XLenVT
)
;
ReplaceNode
(
Node
,
New
.
getNode
(
)
)
;
return
;
}
}
if
(
Opcode
==
ISD
::
FrameIndex
)
{
SDLoc
DL
(
Node
)
;
SDValue
Imm
=
CurDAG
->
getTargetConstant
(
0
,
DL
,
XLenVT
)
;
int
FI
=
dyn_cast
<
FrameIndexSDNode
>
(
Node
)
->
getIndex
(
)
;
EVT
VT
=
Node
->
getValueType
(
0
)
;
SDValue
TFI
=
CurDAG
->
getTargetFrameIndex
(
FI
,
VT
)
;
ReplaceNode
(
Node
,
CurDAG
->
getMachineNode
(
RISCV
::
ADDI
,
DL
,
VT
,
TFI
,
Imm
)
)
;
return
;
}
SelectCode
(
Node
)
;
}
</s>

Main hook for targets to transform nodes into machine nodes .


<s>
const
char
*
cris_op_str
(
rtx
x
)
{
cris_output_insn_is_bound
=
0
;
switch
(
GET_CODE
(
x
)
)
{
case
PLUS
:
return
"add"
;
case
MINUS
:
return
"sub"
;
case
MULT
:
internal_error
(
"MULT case in %<cris_op_str%>"
)
;
break
;
case
DIV
:
return
"div"
;
case
AND
:
return
"and"
;
case
IOR
:
return
"or"
;
case
XOR
:
return
"xor"
;
case
NOT
:
return
"not"
;
case
ASHIFT
:
return
"lsl"
;
case
LSHIFTRT
:
return
"lsr"
;
case
ASHIFTRT
:
return
"asr"
;
case
UMIN
:
cris_output_insn_is_bound
=
1
;
return
"bound"
;
default
:
return
"Unknown operator"
;
}
}
</s>

Given an rtx , return the text string corresponding to the CODE of X . Intended for use in the assembly language output section of a define_insn .

cris
0
"add"
"sub"
"MULT case in %<cris_op_str%>"
"div"
"and"
"or"
"xor"
"not"
"lsl"
"lsr"
"asr"
1
"bound"
"Unknown operator"


"Process function before frame finalized: "

processFunctionBeforeFrameFinalized - This method is called immediately before the specified function 's frame layout ( MF.getFrameInfo ( ) ) is finalized .


<s> MCRegister SIRegisterInfo :: findUnusedRegister ( const MachineRegisterInfo & MRI , const TargetRegisterClass * RC , const MachineFunction & MF ) const { for ( MCRegister Reg : * RC ) if ( MRI . isAllocatable ( Reg ) && ! MRI . isPhysRegUsed ( Reg ) ) return Reg ; return MCRegister ( ) ; } </s>

Returns a lowest register that is not used at any point in the function .


<s> int X86InstrInfo :: getSPAdjust ( const MachineInstr & MI ) const { const MachineFunction * MF = MI . getParent ( ) -> getParent ( ) ; const TargetFrameLowering * TFI = MF -> getSubtarget ( ) . getFrameLowering ( ) ; if ( isFrameInstr ( MI ) ) { int SPAdj = alignTo ( getFrameSize ( MI ) , TFI -> getStackAlign ( ) ) ; SPAdj -= getFrameAdjustment ( MI ) ; if ( ! isFrameSetup ( MI ) ) SPAdj = - SPAdj ; return SPAdj ; } if ( MI . isCall ( ) ) { const MachineBasicBlock * MBB = MI . getParent ( ) ; auto I = ++ MachineBasicBlock :: const_iterator ( MI ) ; for ( auto E = MBB -> end ( ) ; I != E ; ++ I ) { if ( I -> getOpcode ( ) == getCallFrameDestroyOpcode ( ) || I -> isCall ( ) ) break ; } if ( I -> getOpcode ( ) != getCallFrameDestroyOpcode ( ) ) return 0 ; return - ( I -> getOperand ( 1 ) . getImm ( ) ) ; } switch ( MI . getOpcode ( ) ) { default : return 0 ; case X86 :: PUSH32i8 : case X86 :: PUSH32r : case X86 :: PUSH32rmm : case X86 :: PUSH32rmr : case X86 :: PUSHi32 : return 4 ; case X86 :: PUSH64i8 : case X86 :: PUSH64r : case X86 :: PUSH64rmm : case X86 :: PUSH64rmr : case X86 :: PUSH64i32 : return 8 ; } } </s>

getSPAdjust - This returns the stack pointer adjustment made by this instruction .


<s> bool useAA ( ) const override { return true ; } </s>

Enable use of alias analysis during code generation ( during MI scheduling , DAGCombine , etc . ) .


<s> std :: pair < const TargetRegisterClass * , uint8_t > HexagonTargetLowering :: findRepresentativeClass ( const TargetRegisterInfo * TRI , MVT VT ) const { const TargetRegisterClass * RRC = nullptr ; uint8_t Cost = 1 ; switch ( VT . SimpleTy ) { default : return TargetLowering :: findRepresentativeClass ( TRI , VT ) ; case MVT :: v64i8 : case MVT :: v32i16 : case MVT :: v16i32 : case MVT :: v8i64 : RRC = & Hexagon :: VectorRegsRegClass ; break ; case MVT :: v128i8 : case MVT :: v64i16 : case MVT :: v32i32 : case MVT :: v16i64 : if ( Subtarget . hasV60TOps ( ) && Subtarget . useHVXOps ( ) && Subtarget . useHVXDblOps ( ) ) RRC = & Hexagon :: VectorRegs128BRegClass ; else RRC = & Hexagon :: VecDblRegsRegClass ; break ; case MVT :: v256i8 : case MVT :: v128i16 : case MVT :: v64i32 : case MVT :: v32i64 : RRC = & Hexagon :: VecDblRegs128BRegClass ; break ; } return std :: make_pair ( RRC , Cost ) ; } </s>

Return the largest legal super-reg register class of the register class for the specified type and its associated `` cost '' .


<s>
StringRef
getPassName
(
)
const
override
{
return
"Xtensa Assembly Printer"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> static const char * detect_processor_aix ( void ) { switch ( _system_configuration . implementation ) { case 0x0008 : return "601" ; case 0x0020 : return "603" ; case 0x0010 : return "604" ; case 0x0040 : return "620" ; case 0x0080 : return "630" ; case 0x0100 : case 0x0200 : case 0x0400 : return "rs64" ; case 0x0800 : return "power4" ; case 0x2000 : if ( _system_configuration . version == 0x0F0000 ) return "power5" ; else return "power5+" ; case 0x4000 : return "power6" ; case 0x8000 : return "power7" ; case 0x10000 : return "power8" ; case 0x20000 : return "power9" ; case 0x40000 : return "power10" ; default : return "powerpc" ; } } </s>

Returns the processor implementation on AIX .


<s> void SIFrameLowering :: emitPrologue ( MachineFunction & MF , MachineBasicBlock & MBB ) const { const SIMachineFunctionInfo * MFI = MF . getInfo < SIMachineFunctionInfo > ( ) ; if ( MFI -> isEntryFunction ( ) ) emitEntryFunctionPrologue ( MF , MBB ) ; } </s>

emitProlog/emitEpilog - These methods insert prolog and epilog code into the function .


"Can only put epilogue before a return instruction!"


"\nrs6000_preferred_reload_class, return %s, rclass = %s, "

Debug version of rs6000_preferred_reload_class .


"Found a PhiRef node as a real reached use!!"

processBlock - If there are any predecessors whose control can be threaded through to a successor , transform them now .


<s>
void
HexagonHazardRecognizer
::
EmitInstruction
(
SUnit
*
SU
)
{
MachineInstr
*
MI
=
SU
->
getInstr
(
)
;
if
(
!
MI
)
return
;
for
(
const
MachineOperand
&
MO
:
MI
->
operands
(
)
)
if
(
MO
.
isReg
(
)
&&
MO
.
isDef
(
)
&&
!
MO
.
isImplicit
(
)
)
RegDefs
.
insert
(
MO
.
getReg
(
)
)
;
if
(
TII
->
isZeroCost
(
MI
->
getOpcode
(
)
)
)
return
;
if
(
!
Resources
->
canReserveResources
(
*
MI
)
)
{
assert
(
TII
->
mayBeNewStore
(
*
MI
)
&&
"Expecting .new store"
)
;
MachineFunction
*
MF
=
MI
->
getParent
(
)
->
getParent
(
)
;
MachineInstr
*
NewMI
=
MF
->
CreateMachineInstr
(
TII
->
get
(
TII
->
getDotNewOp
(
*
MI
)
)
,
MI
->
getDebugLoc
(
)
)
;
assert
(
Resources
->
canReserveResources
(
*
NewMI
)
)
;
Resources
->
reserveResources
(
*
NewMI
)
;
MF
->
DeleteMachineInstr
(
NewMI
)
;
}
else
Resources
->
reserveResources
(
*
MI
)
;
DEBUG
(
dbgs
(
)
<<
" Add instruction "
<<
*
MI
)
;
if
(
TII
->
mayBeCurLoad
(
*
MI
)
)
for
(
auto
&
S
:
SU
->
Succs
)
if
(
S
.
isAssignedRegDep
(
)
&&
S
.
getLatency
(
)
==
0
&&
SU
->
getHeight
(
)
==
S
.
getSUnit
(
)
->
getHeight
(
)
)
{
UsesDotCur
=
S
.
getSUnit
(
)
;
DotCurPNum
=
PacketNum
;
break
;
}
if
(
SU
==
UsesDotCur
)
{
UsesDotCur
=
nullptr
;
DotCurPNum
=
1
;
}
}
</s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .

Hexagon
Hexagon
"Expecting .new store"
" Add instruction "
0
1


<s> static tree parse_signature ( const function_instance & instance , const char * format , vec < tree > & argument_types ) { tree return_type = parse_type ( instance , format ) ; while ( format [ 0 ] == ',' ) { format += 1 ; tree argument_type = parse_type ( instance , format ) ; unsigned int count = parse_count ( instance , format ) ; for ( unsigned int i = 0 ; i < count ; ++ i ) argument_types . quick_push ( argument_type ) ; } gcc_assert ( format [ 0 ] == 0 ) ; return return_type ; } </s>

Read a type signature for INSTANCE from FORMAT . Add the argument types to ARGUMENT_TYPES and return the return type . The format is a comma-separated list of types ( as for parse_type ) , with the first type being the return type and the rest being the argument types . Each argument type can be followed by an optional count ( as for parse_count ) .


<s> static bool arc_rewrite_small_data_p ( const_rtx x ) { if ( GET_CODE ( x ) == CONST ) x = XEXP ( x , 0 ) ; if ( GET_CODE ( x ) == PLUS ) { if ( GET_CODE ( XEXP ( x , 1 ) ) == CONST_INT ) x = XEXP ( x , 0 ) ; } return ( GET_CODE ( x ) == SYMBOL_REF && SYMBOL_REF_SMALL_P ( x ) ) ; } </s>

Return true if X is a small data address that can be rewritten as a gp+symref .


<s> bool BPFTargetLowering :: isZExtFree ( EVT VT1 , EVT VT2 ) const { if ( ! getHasAlu32 ( ) || ! VT1 . isInteger ( ) || ! VT2 . isInteger ( ) ) return false ; unsigned NumBits1 = VT1 . getSizeInBits ( ) ; unsigned NumBits2 = VT2 . getSizeInBits ( ) ; return NumBits1 == 32 && NumBits2 == 64 ; } </s>

Return true if zero-extending the specific node Val to type VT2 is free ( either because it 's implicitly zero-extended such as ARM ldrb / ldrh or because it 's folded such as X86 zero-extending loads ) .


<s>
bool
WebAssemblyCFGSort
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
LLVM_DEBUG
(
dbgs
(
)
<<
"********** CFG Sorting **********\n"
"********** Function: "
<<
MF
.
getName
(
)
<<
'\n'
)
;
const
auto
&
MLI
=
getAnalysis
<
MachineLoopInfo
>
(
)
;
const
auto
&
WEI
=
getAnalysis
<
WebAssemblyExceptionInfo
>
(
)
;
auto
&
MDT
=
getAnalysis
<
MachineDominatorTree
>
(
)
;
MF
.
getRegInfo
(
)
.
invalidateLiveness
(
)
;
sortBlocks
(
MF
,
MLI
,
WEI
,
MDT
)
;
return
true
;
}
</s>

runOnMachineFunction - Emit the function body .

WebAssembly
WebAssembly
"********** CFG Sorting **********\n"
"********** Function: "
WebAssembly


<s> static int visium_memory_move_cost ( machine_mode mode , reg_class_t to ATTRIBUTE_UNUSED , bool in ) { if ( in ) { if ( GET_MODE_SIZE ( mode ) <= UNITS_PER_WORD ) return 7 ; else return 13 ; } else { if ( GET_MODE_SIZE ( mode ) <= UNITS_PER_WORD ) return 6 ; else return 12 ; } } </s>

Return the cost of moving data of mode MODE between a register of class CLASS and memory . IN is zero if the value is to be written to memory , non-zero if it is to be read in . This cost is relative to those in visium_register_move_cost .


<s>
const
char
*
m68k_output_branch_float_rev
(
rtx_code
code
)
{
switch
(
code
)
{
case
EQ
:
return
"fjne %l3"
;
case
NE
:
return
"fjeq %l3"
;
case
GT
:
return
"fjngt %l3"
;
case
LT
:
return
"fjnlt %l3"
;
case
GE
:
return
"fjnge %l3"
;
case
LE
:
return
"fjnle %l3"
;
case
ORDERED
:
return
"fjun %l3"
;
case
UNORDERED
:
return
"fjor %l3"
;
case
UNEQ
:
return
"fjogl %l3"
;
case
UNGE
:
return
"fjolt %l3"
;
case
UNGT
:
return
"fjole %l3"
;
case
UNLE
:
return
"fjogt %l3"
;
case
UNLT
:
return
"fjoge %l3"
;
case
LTGT
:
return
"fjueq %l3"
;
default
:
gcc_unreachable
(
)
;
}
}
</s>

Return an output template for a reversed floating point branch instruction with CODE .

m68k
"fjne %l3"
"fjeq %l3"
"fjngt %l3"
"fjnlt %l3"
"fjnge %l3"
"fjnle %l3"
"fjun %l3"
"fjor %l3"
"fjogl %l3"
"fjolt %l3"
"fjole %l3"
"fjogt %l3"
"fjoge %l3"
"fjueq %l3"


<s> void arm_load_pic_register ( unsigned long saved_regs ATTRIBUTE_UNUSED , rtx pic_reg ) { rtx l1 , labelno , pic_tmp , pic_rtx ; if ( crtl -> uses_pic_offset_table == 0 || TARGET_SINGLE_PIC_BASE || TARGET_FDPIC ) return ; gcc_assert ( flag_pic ) ; if ( pic_reg == NULL_RTX ) pic_reg = cfun -> machine -> pic_reg ; if ( TARGET_VXWORKS_RTP ) { pic_rtx = gen_rtx_SYMBOL_REF ( Pmode , VXWORKS_GOTT_BASE ) ; pic_rtx = gen_rtx_CONST ( Pmode , pic_rtx ) ; emit_insn ( gen_pic_load_addr_32bit ( pic_reg , pic_rtx ) ) ; emit_insn ( gen_rtx_SET ( pic_reg , gen_rtx_MEM ( Pmode , pic_reg ) ) ) ; pic_tmp = gen_rtx_SYMBOL_REF ( Pmode , VXWORKS_GOTT_INDEX ) ; emit_insn ( gen_pic_offset_arm ( pic_reg , pic_reg , pic_tmp ) ) ; } else { labelno = GEN_INT ( pic_labelno ++ ) ; l1 = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( 1 , labelno ) , UNSPEC_PIC_LABEL ) ; l1 = gen_rtx_CONST ( VOIDmode , l1 ) ; pic_rtx = plus_constant ( Pmode , l1 , TARGET_ARM ? 8 : 4 ) ; pic_rtx = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( 1 , pic_rtx ) , UNSPEC_GOTSYM_OFF ) ; pic_rtx = gen_rtx_CONST ( Pmode , pic_rtx ) ; if ( TARGET_32BIT ) { emit_insn ( gen_pic_load_addr_unified ( pic_reg , pic_rtx , labelno ) ) ; } else { if ( arm_pic_register != INVALID_REGNUM && REGNO ( pic_reg ) > LAST_LO_REGNUM ) { pic_tmp = gen_rtx_REG ( SImode , thumb_find_work_register ( saved_regs ) ) ; emit_insn ( gen_pic_load_addr_thumb1 ( pic_tmp , pic_rtx ) ) ; emit_insn ( gen_movsi ( pic_offset_table_rtx , pic_tmp ) ) ; emit_insn ( gen_pic_add_dot_plus_four ( pic_reg , pic_reg , labelno ) ) ; } else if ( arm_pic_register != INVALID_REGNUM && arm_pic_register > LAST_LO_REGNUM && REGNO ( pic_reg ) <= LAST_LO_REGNUM ) { emit_insn ( gen_pic_load_addr_unified ( pic_reg , pic_rtx , labelno ) ) ; emit_move_insn ( gen_rtx_REG ( Pmode , arm_pic_register ) , pic_reg ) ; emit_use ( gen_rtx_REG ( Pmode , arm_pic_register ) ) ; } else emit_insn ( gen_pic_load_addr_unified ( pic_reg , pic_rtx , labelno ) ) ; } } emit_use ( pic_reg ) ; } </s>

Generate code to load the PIC register . In thumb mode SCRATCH is a low register .


<s> const uint32_t * X86RegisterInfo :: getCallPreservedMask ( const MachineFunction & MF , CallingConv :: ID CC ) const { const X86Subtarget & Subtarget = MF . getSubtarget < X86Subtarget > ( ) ; bool HasAVX = Subtarget . hasAVX ( ) ; bool HasAVX512 = Subtarget . hasAVX512 ( ) ; switch ( CC ) { case CallingConv :: GHC : case CallingConv :: HiPE : return CSR_NoRegs_RegMask ; case CallingConv :: AnyReg : if ( HasAVX ) return CSR_64_AllRegs_AVX_RegMask ; return CSR_64_AllRegs_RegMask ; case CallingConv :: PreserveMost : return CSR_64_RT_MostRegs_RegMask ; case CallingConv :: PreserveAll : if ( HasAVX ) return CSR_64_RT_AllRegs_AVX_RegMask ; return CSR_64_RT_AllRegs_RegMask ; case CallingConv :: Intel_OCL_BI : { if ( HasAVX512 && IsWin64 ) return CSR_Win64_Intel_OCL_BI_AVX512_RegMask ; if ( HasAVX512 && Is64Bit ) return CSR_64_Intel_OCL_BI_AVX512_RegMask ; if ( HasAVX && IsWin64 ) return CSR_Win64_Intel_OCL_BI_AVX_RegMask ; if ( HasAVX && Is64Bit ) return CSR_64_Intel_OCL_BI_AVX_RegMask ; if ( ! HasAVX && ! IsWin64 && Is64Bit ) return CSR_64_Intel_OCL_BI_RegMask ; break ; } case CallingConv :: Cold : if ( Is64Bit ) return CSR_64_MostRegs_RegMask ; break ; default : break ; case CallingConv :: X86_64_Win64 : return CSR_Win64_RegMask ; case CallingConv :: X86_64_SysV : return CSR_64_RegMask ; } if ( Is64Bit ) { if ( IsWin64 ) return CSR_Win64_RegMask ; return CSR_64_RegMask ; } return CSR_32_RegMask ; } </s>

Return a mask of call-preserved registers for the given calling convention on the current function .


<s> static void addExpr ( MCInst & Inst , const MCExpr * Expr ) { if ( const auto * CE = dyn_cast < MCConstantExpr > ( Expr ) ) { Inst . addOperand ( MCOperand :: createImm ( CE -> getValue ( ) ) ) ; } else { Inst . addOperand ( MCOperand :: createExpr ( Expr ) ) ; } } </s>


<s> bool PatmosInstrInfo :: expandPostRAPseudo ( MachineInstr & MI ) const { return false ; } </s>

This function is called for all pseudo instructions that remain after register allocation .


<s> void MBlazeInstrInfo :: loadRegFromStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned DestReg , int FI , const TargetRegisterClass * RC ) const { DebugLoc DL ; BuildMI ( MBB , I , DL , get ( MBlaze :: LWI ) , DestReg ) . addImm ( 0 ) . addFrameIndex ( FI ) ; } </s>

Load the specified register of the given register class from the specified stack frame index .


"Did not fully process a global variable"

EmitGlobals - Emit all of the global variables to memory , storing their addresses into GlobalAddress .


<s> CCAssignFn * CSKYTargetLowering :: CCAssignFnForCall ( CallingConv :: ID CC , bool IsVarArg ) const { if ( IsVarArg || ! Subtarget . useHardFloatABI ( ) ) return CC_CSKY_ABIV2_SOFT ; else return CC_CSKY_ABIV2_FP ; } </s>

Selects the correct CCAssignFn for a given CallingConvention value .


<s> int sparc_splitdi_legitimate ( rtx reg , rtx mem ) { gcc_assert ( reload_completed ) ; if ( ! offsettable_memref_p ( mem ) ) return 0 ; if ( ( REGNO ( reg ) % 2 ) == 0 && mem_min_alignment ( mem , 8 ) ) return 0 ; return 1 ; } </s>

Return 1 if REG and MEM are legitimate enough to allow the various mem < -- > reg splits to be run .


<s> void X86MCCodeEmitter :: emitPrefix ( const MCInst & MI , raw_ostream & OS , const MCSubtargetInfo & STI ) const { unsigned Opcode = MI . getOpcode ( ) ; const MCInstrDesc & Desc = MCII . get ( Opcode ) ; uint64_t TSFlags = Desc . TSFlags ; if ( ( TSFlags & X86II :: FormMask ) == X86II :: Pseudo ) return ; unsigned CurOp = X86II :: getOperandBias ( Desc ) ; unsigned CurByte = 0 ; bool Rex = false ; emitPrefixImpl ( TSFlags , CurOp , CurByte , Rex , MI , Desc , STI , OS ) ; } </s>

Append the prefixes of given instruction to the code buffer .


<s>
MCObjectWriter
*
createObjectWriter
(
raw_ostream
&
OS
)
const
{
llvm_unreachable
(
"createObjectWriter() unimplemented"
)
;
}
</s>

Create a new MCObjectWriter instance for use by the assembler backend to emit the final object file .


<s> MCObjectWriter * BPFAsmBackend :: createObjectWriter ( raw_ostream & OS ) const { return createBPFELFObjectWriter ( OS , 0 ) ; } </s>


<s> bool ARMCallLowering :: lowerFormalArguments ( MachineIRBuilder & MIRBuilder , const Function & F , ArrayRef < unsigned > VRegs ) const { auto & TLI = * getTLI < ARMTargetLowering > ( ) ; auto Subtarget = TLI . getSubtarget ( ) ; if ( Subtarget -> isThumb1Only ( ) ) return false ; if ( F . arg_empty ( ) ) return true ; if ( F . isVarArg ( ) ) return false ; auto & MF = MIRBuilder . getMF ( ) ; auto & MBB = MIRBuilder . getMBB ( ) ; auto DL = MF . getDataLayout ( ) ; for ( auto & Arg : F . args ( ) ) { if ( ! isSupportedType ( DL , TLI , Arg . getType ( ) ) ) return false ; if ( Arg . hasByValOrInAllocaAttr ( ) ) return false ; } CCAssignFn * AssignFn = TLI . CCAssignFnForCall ( F . getCallingConv ( ) , F . isVarArg ( ) ) ; FormalArgHandler ArgHandler ( MIRBuilder , MIRBuilder . getMF ( ) . getRegInfo ( ) , AssignFn ) ; SmallVector < ArgInfo , 8 > ArgInfos ; SmallVector < unsigned , 4 > SplitRegs ; unsigned Idx = 0 ; for ( auto & Arg : F . args ( ) ) { ArgInfo AInfo ( VRegs [ Idx ] , Arg . getType ( ) ) ; setArgFlags ( AInfo , Idx + AttributeList :: FirstArgIndex , DL , F ) ; SplitRegs . clear ( ) ; splitToValueTypes ( AInfo , ArgInfos , MF , [ & ] ( unsigned Reg ) { SplitRegs . push_back ( Reg ) ; } ) ; if ( ! SplitRegs . empty ( ) ) MIRBuilder . buildMerge ( VRegs [ Idx ] , SplitRegs ) ; Idx ++ ; } if ( ! MBB . empty ( ) ) MIRBuilder . setInstr ( * MBB . begin ( ) ) ; if ( ! handleAssignments ( MIRBuilder , ArgInfos , ArgHandler ) ) return false ; MIRBuilder . setMBB ( MBB ) ; return true ; } </s>

This hook must be implemented to lower the incoming ( formal ) arguments , described by VRegs , for GlobalISel .


<s> static rtx swap_selector_for_mode ( machine_mode mode ) { unsigned int swap2 [ 16 ] = { 7 , 6 , 5 , 4 , 3 , 2 , 1 , 0 , 15 , 14 , 13 , 12 , 11 , 10 , 9 , 8 } ; unsigned int swap4 [ 16 ] = { 3 , 2 , 1 , 0 , 7 , 6 , 5 , 4 , 11 , 10 , 9 , 8 , 15 , 14 , 13 , 12 } ; unsigned int swap8 [ 16 ] = { 1 , 0 , 3 , 2 , 5 , 4 , 7 , 6 , 9 , 8 , 11 , 10 , 13 , 12 , 15 , 14 } ; unsigned int swap16 [ 16 ] = { 0 , 1 , 2 , 3 , 4 , 5 , 6 , 7 , 8 , 9 , 10 , 11 , 12 , 13 , 14 , 15 } ; unsigned int * swaparray , i ; rtx perm [ 16 ] ; switch ( mode ) { case V2DFmode : case V2DImode : swaparray = swap2 ; break ; case V4SFmode : case V4SImode : swaparray = swap4 ; break ; case V8HImode : swaparray = swap8 ; break ; case V16QImode : swaparray = swap16 ; break ; default : gcc_unreachable ( ) ; } for ( i = 0 ; i < 16 ; ++ i ) perm [ i ] = GEN_INT ( swaparray [ i ] ) ; return force_reg ( V16QImode , gen_rtx_CONST_VECTOR ( V16QImode , gen_rtvec_v ( 16 , perm ) ) ) ; } </s>

Return a constant vector for use as a little-endian permute control vector to reverse the order of elements of the given vector mode .


<s> ScheduleDAGInstrs * createPostMachineScheduler ( MachineSchedContext * C ) const override { const AArch64Subtarget & ST = C -> MF -> getSubtarget < AArch64Subtarget > ( ) ; if ( ST . hasFuseLiterals ( ) ) { ScheduleDAGMI * DAG = createGenericSchedPostRA ( C ) ; DAG -> addMutation ( createAArch64MacroFusionDAGMutation ( ) ) ; return DAG ; } return nullptr ; } </s>

Similar to createMachineScheduler but used when postRA machine scheduling is enabled .


<s> bool R600InstrInfo :: isProfitableToUnpredicate ( MachineBasicBlock & TMBB , MachineBasicBlock & FMBB ) const { return false ; } </s>

Return true if it 's profitable to unpredicate one side of a 'diamond ' , i.e .


<s> EVT AArch64TargetLowering :: getOptimalMemOpType ( const MemOp & Op , const AttributeList & FuncAttributes ) const { bool CanImplicitFloat = ! FuncAttributes . hasFnAttr ( Attribute :: NoImplicitFloat ) ; bool CanUseNEON = Subtarget -> hasNEON ( ) && CanImplicitFloat ; bool CanUseFP = Subtarget -> hasFPARMv8 ( ) && CanImplicitFloat ; bool IsSmallMemset = Op . isMemset ( ) && Op . size ( ) < 32 ; auto AlignmentIsAcceptable = [ & ] ( EVT VT , Align AlignCheck ) { if ( Op . isAligned ( AlignCheck ) ) return true ; bool Fast ; return allowsMisalignedMemoryAccesses ( VT , 0 , Align ( 1 ) , MachineMemOperand :: MONone , & Fast ) && Fast ; } ; if ( CanUseNEON && Op . isMemset ( ) && ! IsSmallMemset && AlignmentIsAcceptable ( MVT :: v16i8 , Align ( 16 ) ) ) return MVT :: v16i8 ; if ( CanUseFP && ! IsSmallMemset && AlignmentIsAcceptable ( MVT :: f128 , Align ( 16 ) ) ) return MVT :: f128 ; if ( Op . size ( ) >= 8 && AlignmentIsAcceptable ( MVT :: i64 , Align ( 8 ) ) ) return MVT :: i64 ; if ( Op . size ( ) >= 4 && AlignmentIsAcceptable ( MVT :: i32 , Align ( 4 ) ) ) return MVT :: i32 ; return MVT :: Other ; } </s>

It returns EVT : :Other if the type should be determined using generic target-independent logic .


<s> const char * AMDGPUInstructionSelector :: getName ( ) { return DEBUG_TYPE ; } </s>

Return a string with the name of the plan and the applicable VFs and UFs .


<s> static int uses_TOC ( void ) { rtx_insn * insn ; for ( insn = get_insns ( ) ; insn ; insn = NEXT_INSN ( insn ) ) if ( INSN_P ( insn ) ) { rtx pat = PATTERN ( insn ) ; int i ; if ( GET_CODE ( pat ) == PARALLEL ) for ( i = 0 ; i < XVECLEN ( pat , 0 ) ; i ++ ) { rtx sub = XVECEXP ( pat , 0 , i ) ; if ( GET_CODE ( sub ) == USE ) { sub = XEXP ( sub , 0 ) ; if ( GET_CODE ( sub ) == UNSPEC && XINT ( sub , 1 ) == UNSPEC_TOC ) return 1 ; } } } return 0 ; } </s>

This retuns nonzero if the current function uses the TOC . This is determined by the presence of ( unspec ... 7 ) , which is generated by the various load_toc_ * patterns .


<s>
bool
X86CallFrameOptimization
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
STI
=
&
MF
.
getSubtarget
<
X86Subtarget
>
(
)
;
TII
=
STI
->
getInstrInfo
(
)
;
TFL
=
STI
->
getFrameLowering
(
)
;
MRI
=
&
MF
.
getRegInfo
(
)
;
const
X86RegisterInfo
&
RegInfo
=
*
static_cast
<
const
X86RegisterInfo
*
>
(
STI
->
getRegisterInfo
(
)
)
;
SlotSize
=
RegInfo
.
getSlotSize
(
)
;
assert
(
isPowerOf2_32
(
SlotSize
)
&&
"Expect power of 2 stack slot size"
)
;
Log2SlotSize
=
Log2_32
(
SlotSize
)
;
if
(
skipFunction
(
MF
.
getFunction
(
)
)
||
!
isLegal
(
MF
)
)
return
false
;
unsigned
FrameSetupOpcode
=
TII
->
getCallFrameSetupOpcode
(
)
;
bool
Changed
=
false
;
ContextVector
CallSeqVector
;
for
(
auto
&
MBB
:
MF
)
for
(
auto
&
MI
:
MBB
)
if
(
MI
.
getOpcode
(
)
==
FrameSetupOpcode
)
{
CallContext
Context
;
collectCallInfo
(
MF
,
MBB
,
MI
,
Context
)
;
CallSeqVector
.
push_back
(
Context
)
;
}
if
(
!
isProfitable
(
MF
,
CallSeqVector
)
)
return
false
;
for
(
const
auto
&
CC
:
CallSeqVector
)
{
if
(
CC
.
UsePush
)
{
adjustCallSequence
(
MF
,
CC
)
;
Changed
=
true
;
}
}
return
Changed
;
}
</s>

runOnMachineFunction - Emit the function body .


<s> static rtx pdp11_function_arg ( cumulative_args_t , const function_arg_info & ) { return NULL_RTX ; } </s>

Worker function for TARGET_FUNCTION_ARG . Determine where to put an argument to a function . Value is zero to push the argument on the stack , or a hard register in which to store the argument . MODE is the argument 's machine mode . TYPE is the data type of the argument ( as a tree ) . This is null for libcalls where that information may not be available . CUM is a variable of type CUMULATIVE_ARGS which gives info about the preceding args and about the function being called . NAMED is nonzero if this argument is a named parameter ( otherwise it is an extra parameter matching an ellipsis ) .


<s> static int insn_uid_get_clock ( int uid ) { return INSN_INFO_ENTRY ( uid ) . clock ; } </s>

Return the clock cycle we set for the insn with uid UID .


"Unmatched number of shufflevectors and indices"

Lower interleaved load ( s ) into target specific instructions/intrinsics .


<s>
const
char
*
getPassName
(
)
const
override
{
return
"HSAIL DAG->DAG Instruction Selection"
;
}
</s>

getPassName - Return a nice clean name for a pass .

HSAIL
"HSAIL DAG->DAG Instruction Selection"


<s> bool SIInstrInfo :: isOperandLegal ( const MachineInstr * MI , unsigned OpIdx , const MachineOperand * MO ) const { const MachineRegisterInfo & MRI = MI -> getParent ( ) -> getParent ( ) -> getRegInfo ( ) ; const MCInstrDesc & InstDesc = get ( MI -> getOpcode ( ) ) ; const MCOperandInfo & OpInfo = InstDesc . OpInfo [ OpIdx ] ; const TargetRegisterClass * DefinedRC = OpInfo . RegClass != - 1 ? RI . getRegClass ( OpInfo . RegClass ) : nullptr ; if ( ! MO ) MO = & MI -> getOperand ( OpIdx ) ; if ( MO -> isReg ( ) ) { assert ( DefinedRC ) ; const TargetRegisterClass * RC = MRI . getRegClass ( MO -> getReg ( ) ) ; return RI . getCommonSubClass ( RC , RI . getRegClass ( OpInfo . RegClass ) ) ; } assert ( MO -> isImm ( ) || MO -> isFPImm ( ) || MO -> isTargetIndex ( ) || MO -> isFI ( ) ) ; if ( ! DefinedRC ) return true ; return RI . regClassCanUseImmediate ( DefinedRC ) ; } </s>

Check if MO is a legal operand if it was the OpIdx Operand for MI .


<s> static unsigned int visium_reorg ( void ) { if ( visium_cpu == PROCESSOR_GR5 ) gr5_hazard_avoidance ( ) ; return 0 ; } </s>

Perform a target-specific pass over the instruction stream . The compiler will run it at all optimization levels , just after the point at which it normally does delayed-branch scheduling .


<s> bool ARMTargetLowering :: getPostIndexedAddressParts ( SDNode * N , SDNode * Op , SDValue & Base , SDValue & Offset , ISD :: MemIndexedMode & AM , SelectionDAG & DAG ) const { if ( Subtarget -> isThumb1Only ( ) ) return false ; const bool restrict_addressing_modes_for_nacl = Subtarget -> isTargetNaCl ( ) && isa < MemSDNode > ( N ) ; if ( restrict_addressing_modes_for_nacl ) { return false ; } EVT VT ; SDValue Ptr ; bool isSEXTLoad = false ; if ( LoadSDNode * LD = dyn_cast < LoadSDNode > ( N ) ) { VT = LD -> getMemoryVT ( ) ; Ptr = LD -> getBasePtr ( ) ; isSEXTLoad = LD -> getExtensionType ( ) == ISD :: SEXTLOAD ; } else if ( StoreSDNode * ST = dyn_cast < StoreSDNode > ( N ) ) { VT = ST -> getMemoryVT ( ) ; Ptr = ST -> getBasePtr ( ) ; } else return false ; bool isInc ; bool isLegal = false ; if ( Subtarget -> isThumb2 ( ) ) isLegal = getT2IndexedAddressParts ( Op , VT , isSEXTLoad , Base , Offset , isInc , DAG ) ; else isLegal = getARMIndexedAddressParts ( Op , VT , isSEXTLoad , Base , Offset , isInc , DAG ) ; if ( ! isLegal ) return false ; if ( Ptr != Base ) { if ( Ptr == Offset && Op -> getOpcode ( ) == ISD :: ADD && ! Subtarget -> isThumb2 ( ) ) std :: swap ( Base , Offset ) ; if ( Ptr != Base ) return false ; } AM = isInc ? ISD :: POST_INC : ISD :: POST_DEC ; return true ; } </s>

Returns true by value , base pointer and offset pointer and addressing mode by reference if this node can be combined with a load / store to form a post-indexed load / store .

ARM ARM ISD::MemIndexedMode ISD::SEXTLOAD ARM ISD::ADD ISD::POST_INC ISD::POST_DEC


"Pseudo flag-setting opcodes must be marked with 'hasPostISelHook'"

"converted opcode should be the same except for cc_out"

"expect uninitialized optional cc_out operand"

This method should be implemented by targets that mark instructions with the 'hasPostISelHook ' flag .


<s>
const
char
*
getPassName
(
)
const
override
{
return
"SI Fix SGPR live ranges"
;
}
</s>


<s> static int rs6000_psave_function_arg ( machine_mode mode , const_tree type , int align_words , rtx * rvec ) { int k = 0 ; if ( align_words < GP_ARG_NUM_REG ) { int n_words = rs6000_arg_size ( mode , type ) ; if ( align_words + n_words > GP_ARG_NUM_REG || mode == BLKmode || ( TARGET_32BIT && TARGET_POWERPC64 ) ) { machine_mode rmode = TARGET_32BIT ? SImode : DImode ; int i = 0 ; if ( align_words + n_words > GP_ARG_NUM_REG ) { rvec [ k ++ ] = gen_rtx_EXPR_LIST ( VOIDmode , NULL_RTX , const0_rtx ) ; } do { rtx r = gen_rtx_REG ( rmode , GP_ARG_MIN_REG + align_words ) ; rtx off = GEN_INT ( i ++ * GET_MODE_SIZE ( rmode ) ) ; rvec [ k ++ ] = gen_rtx_EXPR_LIST ( VOIDmode , r , off ) ; } while ( ++ align_words < GP_ARG_NUM_REG && -- n_words != 0 ) ; } else { rtx r = gen_rtx_REG ( mode , GP_ARG_MIN_REG + align_words ) ; rvec [ k ++ ] = gen_rtx_EXPR_LIST ( VOIDmode , r , const0_rtx ) ; } } else { rvec [ k ++ ] = gen_rtx_EXPR_LIST ( VOIDmode , NULL_RTX , const0_rtx ) ; } return k ; } </s>

We have an argument of MODE and TYPE that goes into FPRs or VRs , but must also be copied into the parameter save area starting at offset ALIGN_WORDS . Fill in RVEC with the elements corresponding to the GPRs and/or memory . Return the number of elements used .


<s>
void
\
toc_section
(
)
\
{
\
if
(
TARGET_MINIMAL_TOC
)
\
{
\
\
if
(
!
toc_initialized
)
\
{
\
fputs
(
"\t.toc\nLCTOC..1:\n"
,
asm_out_file
)
;
\
fputs
(
"\t.tc toc_table[TC],toc_table[RW]\n"
,
asm_out_file
)
;
\
toc_initialized
=
1
;
\
}
\
\
if
(
in_section
!=
toc
)
\
fprintf
(
asm_out_file
,
"\t.csect toc_table[RW]%s\n"
,
\
(
TARGET_32BIT
""
:
",3"
)
)
;
\
}
\
else
\
{
\
if
(
in_section
!=
toc
)
\
fputs
(
"\t.toc\n"
,
asm_out_file
)
;
\
}
\
in_section
=
toc
;
\
}
</s>

This is just a placeholder to make linking work without having to add this to the generic Darwin EXTRA_SECTIONS . If -mcall-aix is ever needed for Darwin ( not too likely ! ) this would have to get a real definition .


<s> unsigned M88kAsmParser :: validateTargetOperandClass ( MCParsedAsmOperand & AsmOp , unsigned Kind ) { if ( Kind == MCK_GPR64RC && AsmOp . isReg ( ) ) { switch ( AsmOp . getReg ( ) ) { case M88k :: R0 : case M88k :: R2 : case M88k :: R4 : case M88k :: R6 : case M88k :: R8 : case M88k :: R10 : case M88k :: R12 : case M88k :: R14 : case M88k :: R16 : case M88k :: R18 : case M88k :: R20 : case M88k :: R22 : case M88k :: R24 : case M88k :: R26 : case M88k :: R28 : case M88k :: R30 : return Match_Success ; case M88k :: R1 : case M88k :: R3 : case M88k :: R5 : case M88k :: R7 : case M88k :: R9 : case M88k :: R11 : case M88k :: R13 : case M88k :: R15 : case M88k :: R17 : case M88k :: R19 : case M88k :: R21 : case M88k :: R23 : case M88k :: R25 : case M88k :: R27 : case M88k :: R29 : case M88k :: R31 : return Match_Success ; default : return Match_InvalidOperand ; } } return Match_InvalidOperand ; } </s>

Allow a target to add special case operand matching for things that tblgen doesn't/ca n't handle effectively .


<s>
MachineInstrBuilder
R600InstrInfo
::
buildIndirectWrite
(
MachineBasicBlock
*
MBB
,
MachineBasicBlock
::
iterator
I
,
unsigned
ValueReg
,
unsigned
Address
,
unsigned
OffsetReg
,
unsigned
AddrChan
)
const
{
unsigned
AddrReg
;
switch
(
AddrChan
)
{
default
:
llvm_unreachable
(
"Invalid Channel"
)
;
case
0
:
AddrReg
=
AMDGPU
::
R600_AddrRegClass
.
getRegister
(
Address
)
;
break
;
case
1
:
AddrReg
=
AMDGPU
::
R600_Addr_YRegClass
.
getRegister
(
Address
)
;
break
;
case
2
:
AddrReg
=
AMDGPU
::
R600_Addr_ZRegClass
.
getRegister
(
Address
)
;
break
;
case
3
:
AddrReg
=
AMDGPU
::
R600_Addr_WRegClass
.
getRegister
(
Address
)
;
break
;
}
MachineInstr
*
MOVA
=
buildDefaultInstruction
(
*
MBB
,
I
,
AMDGPU
::
MOVA_INT_eg
,
AMDGPU
::
AR_X
,
OffsetReg
)
;
setImmOperand
(
MOVA
,
AMDGPU
::
OpName
::
write
,
0
)
;
MachineInstrBuilder
Mov
=
buildDefaultInstruction
(
*
MBB
,
I
,
AMDGPU
::
MOV
,
AddrReg
,
ValueReg
)
.
addReg
(
AMDGPU
::
AR_X
,
RegState
::
Implicit
|
RegState
::
Kill
)
;
setImmOperand
(
Mov
,
AMDGPU
::
OpName
::
dst_rel
,
1
)
;
return
Mov
;
}
</s>

Build instruction ( s ) for an indirect register write .