<s> bool runOnModule ( Module & M ) override { PointerTypeMap PointerTypes = PointerTypeAnalysis :: run ( M ) ; AttributeMask AttrMask ; for ( Attribute :: AttrKind I = Attribute :: None ; I != Attribute :: EndAttrKinds ; I = Attribute :: AttrKind ( I + 1 ) ) { if ( ! isValidForDXIL ( I ) ) AttrMask . addAttribute ( I ) ; } for ( auto & F : M . functions ( ) ) { F . removeFnAttrs ( AttrMask ) ; F . removeRetAttrs ( AttrMask ) ; for ( size_t Idx = 0 , End = F . arg_size ( ) ; Idx < End ; ++ Idx ) F . removeParamAttrs ( Idx , AttrMask ) ; for ( auto & BB : F ) { IRBuilder < > Builder ( & BB ) ; for ( auto & I : make_early_inc_range ( BB ) ) { if ( I . getOpcode ( ) == Instruction :: FNeg ) { Builder . SetInsertPoint ( & I ) ; Value * In = I . getOperand ( 0 ) ; Value * Zero = ConstantFP :: get ( In -> getType ( ) , - 0.0 ) ; I . replaceAllUsesWith ( Builder . CreateFSub ( Zero , In ) ) ; I . eraseFromParent ( ) ; continue ; } if ( ! M . getContext ( ) . hasSetOpaquePointersValue ( ) ) continue ; if ( auto LI = dyn_cast < LoadInst > ( & I ) ) { if ( Value * NoOpBitcast = maybeGenerateBitcast ( Builder , PointerTypes , I , LI -> getPointerOperand ( ) , LI -> getType ( ) ) ) { LI -> replaceAllUsesWith ( Builder . CreateLoad ( LI -> getType ( ) , NoOpBitcast ) ) ; LI -> eraseFromParent ( ) ; } continue ; } if ( auto SI = dyn_cast < StoreInst > ( & I ) ) { if ( Value * NoOpBitcast = maybeGenerateBitcast ( Builder , PointerTypes , I , SI -> getPointerOperand ( ) , SI -> getValueOperand ( ) -> getType ( ) ) ) { SI -> replaceAllUsesWith ( Builder . CreateStore ( SI -> getValueOperand ( ) , NoOpBitcast ) ) ; SI -> eraseFromParent ( ) ; } continue ; } if ( auto GEP = dyn_cast < GetElementPtrInst > ( & I ) ) { if ( Value * NoOpBitcast = maybeGenerateBitcast ( Builder , PointerTypes , I , GEP -> getPointerOperand ( ) , GEP -> getResultElementType ( ) ) ) GEP -> setOperand ( 0 , NoOpBitcast ) ; continue ; } } } } return true ; } </s>

runOnModule - Virtual method overriden by subclasses to process the module being operated on .


<s> static rtx_insn * rs6000_emit_allocate_stack_1 ( HOST_WIDE_INT size_int , rtx orig_sp ) { rtx_insn * insn ; rtx size_rtx = GEN_INT ( - size_int ) ; if ( size_int > 32767 ) { rtx tmp_reg = gen_rtx_REG ( Pmode , 0 ) ; if ( get_last_insn ( ) == NULL_RTX ) emit_note ( NOTE_INSN_DELETED ) ; insn = emit_move_insn ( tmp_reg , size_rtx ) ; try_split ( PATTERN ( insn ) , insn , 0 ) ; size_rtx = tmp_reg ; } if ( TARGET_32BIT ) insn = emit_insn ( gen_movsi_update_stack ( stack_pointer_rtx , stack_pointer_rtx , size_rtx , orig_sp ) ) ; else insn = emit_insn ( gen_movdi_update_stack ( stack_pointer_rtx , stack_pointer_rtx , size_rtx , orig_sp ) ) ; rtx par = PATTERN ( insn ) ; gcc_assert ( GET_CODE ( par ) == PARALLEL ) ; rtx set = XVECEXP ( par , 0 , 0 ) ; gcc_assert ( GET_CODE ( set ) == SET ) ; rtx mem = SET_DEST ( set ) ; gcc_assert ( MEM_P ( mem ) ) ; MEM_NOTRAP_P ( mem ) = 1 ; set_mem_alias_set ( mem , get_frame_alias_set ( ) ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; add_reg_note ( insn , REG_FRAME_RELATED_EXPR , gen_rtx_SET ( stack_pointer_rtx , gen_rtx_PLUS ( Pmode , stack_pointer_rtx , GEN_INT ( - size_int ) ) ) ) ; if ( flag_stack_clash_protection ) { add_reg_note ( insn , REG_STACK_CHECK , const0_rtx ) ; emit_insn ( gen_blockage ( ) ) ; } return insn ; } </s>

Allocate SIZE_INT bytes on the stack using a store with update style insn and set the appropriate attributes for the generated insn . Return the first insn which adjusts the stack pointer or the last insn before the stack adjustment loop . SIZE_INT is used to create the CFI note for the allocation . SIZE_RTX is an rtx containing the size of the adjustment . Note that since stacks grow to lower addresses its runtime value is -SIZE_INT . ORIG_SP contains the backchain value that must be stored at * sp .


<s> void AMDGPUDAGToDAGISel :: PostprocessISelDAG ( ) { if ( Subtarget . getGeneration ( ) < AMDGPUSubtarget :: SOUTHERN_ISLANDS ) { return ; } const AMDGPUTargetLowering & Lowering = ( * ( const AMDGPUTargetLowering * ) getTargetLowering ( ) ) ; for ( SelectionDAG :: allnodes_iterator I = CurDAG -> allnodes_begin ( ) , E = CurDAG -> allnodes_end ( ) ; I != E ; ++ I ) { SDNode * Node = I ; switch ( Node -> getOpcode ( ) ) { case ISD :: CopyToReg : { unsigned Reg = cast < RegisterSDNode > ( Node -> getOperand ( 1 ) ) -> getReg ( ) ; SDValue Val = Node -> getOperand ( 2 ) ; const TargetRegisterClass * RC = RegInfo -> getRegClass ( Reg ) ; if ( RC != & AMDGPU :: SReg_64RegClass ) { continue ; } if ( ! Val . getNode ( ) -> isMachineOpcode ( ) || Val . getNode ( ) -> getMachineOpcode ( ) == AMDGPU :: IMPLICIT_DEF ) { continue ; } const MCInstrDesc Desc = TM . getInstrInfo ( ) -> get ( Val . getNode ( ) -> getMachineOpcode ( ) ) ; const TargetRegisterInfo * TRI = TM . getRegisterInfo ( ) ; RegInfo -> setRegClass ( Reg , TRI -> getRegClass ( Desc . OpInfo [ 0 ] . RegClass ) ) ; continue ; } } MachineSDNode * MachineNode = dyn_cast < MachineSDNode > ( I ) ; if ( ! MachineNode ) continue ; SDNode * ResNode = Lowering . PostISelFolding ( MachineNode , * CurDAG ) ; if ( ResNode != Node ) { ReplaceUses ( Node , ResNode ) ; } } } </s>

PostprocessISelDAG ( ) - This hook allows the target to hack on the graph right after selection .


<s> void assignValueToAddress ( unsigned ValVReg , unsigned Addr , uint64_t Size , MachinePointerInfo & MPO , CCValAssign & VA ) override { auto MMO = MIRBuilder . getMF ( ) . getMachineMemOperand ( MPO , MachineMemOperand :: MOLoad | MachineMemOperand :: MOInvariant , Size , 0 ) ; MIRBuilder . buildLoad ( ValVReg , Addr , * MMO ) ; } </s>

An overload which takes an ArgInfo if additional information about the arg is needed .


"X32 does not support %<ms_abi%> attribute"

Returns value SYSV_ABI , MS_ABI dependent on fntype , specifying the call abi used .


"AMDGPUMCInstLower::lower - Pseudo instruction doesn't have "


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . addRequired < MachineDominatorTree > ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s>
void
AArch64TargetLowering
::
computeKnownBitsForTargetNode
(
const
SDValue
Op
,
KnownBits
&
Known
,
const
APInt
&
DemandedElts
,
const
SelectionDAG
&
DAG
,
unsigned
Depth
)
const
{
switch
(
Op
.
getOpcode
(
)
)
{
default
:
break
;
case
AArch64ISD
::
CSEL
:
{
KnownBits
Known2
;
DAG
.
computeKnownBits
(
Op
->
getOperand
(
0
)
,
Known
,
Depth
+
1
)
;
DAG
.
computeKnownBits
(
Op
->
getOperand
(
1
)
,
Known2
,
Depth
+
1
)
;
Known
.
Zero
&=
Known2
.
Zero
;
Known
.
One
&=
Known2
.
One
;
break
;
}
case
ISD
::
INTRINSIC_W_CHAIN
:
{
ConstantSDNode
*
CN
=
cast
<
ConstantSDNode
>
(
Op
->
getOperand
(
1
)
)
;
Intrinsic
::
ID
IntID
=
static_cast
<
Intrinsic
::
ID
>
(
CN
->
getZExtValue
(
)
)
;
switch
(
IntID
)
{
default
:
return
;
case
Intrinsic
::
aarch64_ldaxr
:
case
Intrinsic
::
aarch64_ldxr
:
{
unsigned
BitWidth
=
Known
.
getBitWidth
(
)
;
EVT
VT
=
cast
<
MemIntrinsicSDNode
>
(
Op
)
->
getMemoryVT
(
)
;
unsigned
MemBits
=
VT
.
getScalarSizeInBits
(
)
;
Known
.
Zero
|=
APInt
::
getHighBitsSet
(
BitWidth
,
BitWidth
MemBits
)
;
return
;
}
}
break
;
}
case
ISD
::
INTRINSIC_WO_CHAIN
:
case
ISD
::
INTRINSIC_VOID
:
{
unsigned
IntNo
=
cast
<
ConstantSDNode
>
(
Op
.
getOperand
(
0
)
)
->
getZExtValue
(
)
;
switch
(
IntNo
)
{
default
:
break
;
case
Intrinsic
::
aarch64_neon_umaxv
:
case
Intrinsic
::
aarch64_neon_uminv
:
{
MVT
VT
=
Op
.
getOperand
(
1
)
.
getValueType
(
)
.
getSimpleVT
(
)
;
unsigned
BitWidth
=
Known
.
getBitWidth
(
)
;
if
(
VT
==
MVT
::
v8i8
||
VT
==
MVT
::
v16i8
)
{
assert
(
BitWidth
>=
8
&&
"Unexpected width!"
)
;
APInt
Mask
=
APInt
::
getHighBitsSet
(
BitWidth
,
BitWidth
8
)
;
Known
.
Zero
|=
Mask
;
}
else
if
(
VT
==
MVT
::
v4i16
||
VT
==
MVT
::
v8i16
)
{
assert
(
BitWidth
>=
16
&&
"Unexpected width!"
)
;
APInt
Mask
=
APInt
::
getHighBitsSet
(
BitWidth
,
BitWidth
16
)
;
Known
.
Zero
|=
Mask
;
}
break
;
}
break
;
}
}
}
}
</s>

Determine which of the bits specified in Mask are known to be either zero or one and return them in the KnownZero/KnownOne bitsets .


<s> void fixup_addr_diff_vecs ( rtx first ) { rtx insn ; for ( insn = first ; insn ; insn = NEXT_INSN ( insn ) ) { rtx vec_lab , pat , prev , prevpat , x , braf_label ; if ( GET_CODE ( insn ) != JUMP_INSN || GET_CODE ( PATTERN ( insn ) ) != ADDR_DIFF_VEC ) continue ; pat = PATTERN ( insn ) ; vec_lab = XEXP ( XEXP ( pat , 0 ) , 0 ) ; for ( prev = vec_lab ; ; prev = PREV_INSN ( prev ) ) { if ( GET_CODE ( prev ) != JUMP_INSN ) continue ; prevpat = PATTERN ( prev ) ; if ( GET_CODE ( prevpat ) != PARALLEL || XVECLEN ( prevpat , 0 ) != 2 ) continue ; x = XVECEXP ( prevpat , 0 , 1 ) ; if ( GET_CODE ( x ) != USE ) continue ; x = XEXP ( x , 0 ) ; if ( GET_CODE ( x ) == LABEL_REF && XEXP ( x , 0 ) == vec_lab ) break ; } if ( ! prev ) continue ; braf_label = XEXP ( XEXP ( SET_SRC ( XVECEXP ( prevpat , 0 , 0 ) ) , 1 ) , 0 ) ; emit_label_after ( braf_label , prev ) ; XEXP ( XEXP ( pat , 0 ) , 0 ) = braf_label ; } } </s>


<s> static rtx rs6000_expand_builtin ( tree exp , rtx target , rtx subtarget ATTRIBUTE_UNUSED , enum machine_mode mode ATTRIBUTE_UNUSED , int ignore ATTRIBUTE_UNUSED ) { tree fndecl = TREE_OPERAND ( TREE_OPERAND ( exp , 0 ) , 0 ) ; tree arglist = TREE_OPERAND ( exp , 1 ) ; unsigned int fcode = DECL_FUNCTION_CODE ( fndecl ) ; struct builtin_description * d ; size_t i ; rtx ret ; bool success ; if ( fcode == ALTIVEC_BUILTIN_MASK_FOR_LOAD || fcode == ALTIVEC_BUILTIN_MASK_FOR_STORE ) { int icode = ( int ) CODE_FOR_altivec_lvsr ; enum machine_mode tmode = insn_data [ icode ] . operand [ 0 ] . mode ; enum machine_mode mode = insn_data [ icode ] . operand [ 1 ] . mode ; tree arg ; rtx op , addr , pat ; gcc_assert ( TARGET_ALTIVEC ) ; arg = TREE_VALUE ( arglist ) ; gcc_assert ( TREE_CODE ( TREE_TYPE ( arg ) ) == POINTER_TYPE ) ; op = expand_expr ( arg , NULL_RTX , Pmode , EXPAND_NORMAL ) ; addr = memory_address ( mode , op ) ; if ( fcode == ALTIVEC_BUILTIN_MASK_FOR_STORE ) op = addr ; else { op = gen_reg_rtx ( GET_MODE ( addr ) ) ; emit_insn ( gen_rtx_SET ( VOIDmode , op , gen_rtx_NEG ( GET_MODE ( addr ) , addr ) ) ) ; } op = gen_rtx_MEM ( mode , op ) ; if ( target == 0 || GET_MODE ( target ) != tmode || ! ( * insn_data [ icode ] . operand [ 0 ] . predicate ) ( target , tmode ) ) target = gen_reg_rtx ( tmode ) ; pat = GEN_FCN ( icode ) ( target , op ) ; if ( ! pat ) return 0 ; emit_insn ( pat ) ; return target ; } if ( TARGET_ALTIVEC ) { ret = altivec_expand_builtin ( exp , target , & success ) ; if ( success ) return ret ; } if ( TARGET_SPE ) { ret = spe_expand_builtin ( exp , target , & success ) ; if ( success ) return ret ; } gcc_assert ( TARGET_ALTIVEC || TARGET_SPE ) ; d = ( struct builtin_description * ) bdesc_1arg ; for ( i = 0 ; i < ARRAY_SIZE ( bdesc_1arg ) ; i ++ , d ++ ) if ( d -> code == fcode ) return rs6000_expand_unop_builtin ( d -> icode , arglist , target ) ; d = ( struct builtin_description * ) bdesc_2arg ; for ( i = 0 ; i < ARRAY_SIZE ( bdesc_2arg ) ; i ++ , d ++ ) if ( d -> code == fcode ) return rs6000_expand_binop_builtin ( d -> icode , arglist , target ) ; d = ( struct builtin_description * ) bdesc_3arg ; for ( i = 0 ; i < ARRAY_SIZE ( bdesc_3arg ) ; i ++ , d ++ ) if ( d -> code == fcode ) return rs6000_expand_ternop_builtin ( d -> icode , arglist , target ) ; gcc_unreachable ( ) ; } </s>

Expand an expression EXP that calls a built-in function , with result going to TARGET if that 's convenient ( and in mode MODE if that 's convenient ) . SUBTARGET may be used as the target for computing one of EXP 's operands . IGNORE is nonzero if the value is to be ignored . Use the new builtin infrastructure .


<s> static void tryAddingPcLoadReferenceComment ( uint64_t Address , int Value , const MCDisassembler * Decoder ) { const MCDisassembler * Dis = static_cast < const MCDisassembler * > ( Decoder ) ; Dis -> tryAddingPcLoadReferenceComment ( Value , Address ) ; } </s>

Try to add a comment on the PC-relative load .


<s> rtx aarch64_stack_protect_canary_mem ( machine_mode mode , rtx decl_rtl , aarch64_salt_type salt_type ) { rtx addr ; if ( aarch64_stack_protector_guard == SSP_GLOBAL ) { gcc_assert ( MEM_P ( decl_rtl ) ) ; addr = XEXP ( decl_rtl , 0 ) ; poly_int64 offset ; rtx base = strip_offset_and_salt ( addr , & offset ) ; if ( ! SYMBOL_REF_P ( base ) ) return decl_rtl ; rtvec v = gen_rtvec ( 2 , base , GEN_INT ( salt_type ) ) ; addr = gen_rtx_UNSPEC ( Pmode , v , UNSPEC_SALT_ADDR ) ; addr = gen_rtx_CONST ( Pmode , addr ) ; addr = plus_constant ( Pmode , addr , offset ) ; } else { rtx salt = GEN_INT ( salt_type ) ; addr = gen_reg_rtx ( mode ) ; if ( mode == DImode ) emit_insn ( gen_reg_stack_protect_address_di ( addr , salt ) ) ; else { emit_insn ( gen_reg_stack_protect_address_si ( addr , salt ) ) ; addr = convert_memory_address ( Pmode , addr ) ; } addr = plus_constant ( Pmode , addr , aarch64_stack_protector_guard_offset ) ; } return gen_rtx_MEM ( mode , force_reg ( Pmode , addr ) ) ; } </s>

Return the MEM rtx that provides the canary value that should be used for stack-smashing protection . MODE is the mode of the memory . For SSP_GLOBAL , DECL_RTL is the MEM rtx for the canary variable ( __stack_chk_guard ) , otherwise it has no useful value . SALT_TYPE indicates whether the caller is performing a SET or a TEST operation .


<s> SDValue AMDGPUTargetLowering :: CreateLiveInRegister ( SelectionDAG & DAG , const TargetRegisterClass * RC , Register Reg , EVT VT , const SDLoc & SL , bool RawReg ) const { MachineFunction & MF = DAG . getMachineFunction ( ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; Register VReg ; if ( ! MRI . isLiveIn ( Reg ) ) { VReg = MRI . createVirtualRegister ( RC ) ; MRI . addLiveIn ( Reg , VReg ) ; } else { VReg = MRI . getLiveInVirtReg ( Reg ) ; } if ( RawReg ) return DAG . getRegister ( VReg , VT ) ; return DAG . getCopyFromReg ( DAG . getEntryNode ( ) , SL , VReg , VT ) ; } </s>

Helper function that adds Reg to the LiveIn list of the DAG 's MachineFunction .


<s> static int arm_get_vfp_saved_size ( void ) { unsigned int regno ; int count ; int saved ; saved = 0 ; if ( TARGET_HARD_FLOAT && TARGET_VFP ) { count = 0 ; for ( regno = FIRST_VFP_REGNUM ; regno < LAST_VFP_REGNUM ; regno += 2 ) { if ( ( ! regs_ever_live [ regno ] || call_used_regs [ regno ] ) && ( ! regs_ever_live [ regno + 1 ] || call_used_regs [ regno + 1 ] ) ) { if ( count > 0 ) { if ( count == 2 && ! arm_arch6 ) count ++ ; saved += count * 8 + 4 ; } count = 0 ; } else count ++ ; } if ( count > 0 ) { if ( count == 2 && ! arm_arch6 ) count ++ ; saved += count * 8 + 4 ; } } return saved ; } </s>

Return the number of bytes required to save VFP registers .


<s> void OpenRISCFrameLowering :: emitEpilogue ( MachineFunction & MF , MachineBasicBlock & MBB ) const { } </s>


<s>
unsigned
AArch64TargetLowering
::
getRegisterByName
(
const
char
*
RegName
,
EVT
VT
,
SelectionDAG
&
DAG
)
const
{
unsigned
Reg
=
StringSwitch
<
unsigned
>
(
RegName
)
.
Case
(
"sp"
,
AArch64
::
SP
)
.
Case
(
"x18"
,
AArch64
::
X18
)
.
Case
(
"w18"
,
AArch64
::
W18
)
.
Case
(
"x20"
,
AArch64
::
X20
)
.
Case
(
"w20"
,
AArch64
::
W20
)
.
Default
(
0
)
;
if
(
(
(
Reg
==
AArch64
::
X18
||
Reg
==
AArch64
::
W18
)
&&
!
Subtarget
->
isX18Reserved
(
)
)
||
(
(
Reg
==
AArch64
::
X20
||
Reg
==
AArch64
::
W20
)
&&
!
Subtarget
->
isX20Reserved
(
)
)
)
Reg
=
0
;
if
(
Reg
)
return
Reg
;
report_fatal_error
(
Twine
(
"Invalid register name \""
+
StringRef
(
RegName
)
+
"\"."
)
)
;
}
</s>

Return the register ID of the name passed in .


<s>
const
MCFixupKindInfo
&
getFixupKindInfo
(
MCFixupKind
Kind
)
const
override
{
const
static
MCFixupKindInfo
Infos
[
LC3
::
NumTargetFixupKinds
]
=
{
{
"fixup_lc3_mov_hi16_pcrel"
,
0
,
32
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_lc3_mov_lo16_pcrel"
,
0
,
32
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
}
;
if
(
Kind
<
FirstTargetFixupKind
)
{
return
MCAsmBackend
::
getFixupKindInfo
(
Kind
)
;
}
assert
(
unsigned
(
Kind
FirstTargetFixupKind
)
<
getNumFixupKinds
(
)
&&
"Invalid kind!"
)
;
return
Infos
[
Kind
FirstTargetFixupKind
]
;
}
</s>


<s> bool aarch64_split_dimode_const_store ( rtx dst , rtx src ) { rtx lo = gen_lowpart ( SImode , src ) ; rtx hi = gen_highpart_mode ( SImode , DImode , src ) ; bool size_p = optimize_function_for_size_p ( cfun ) ; if ( ! rtx_equal_p ( lo , hi ) ) return false ; unsigned int orig_cost = aarch64_internal_mov_immediate ( NULL_RTX , src , false , DImode ) ; unsigned int lo_cost = aarch64_internal_mov_immediate ( NULL_RTX , lo , false , SImode ) ; if ( size_p && orig_cost <= lo_cost ) return false ; if ( ! size_p && ( orig_cost <= lo_cost + 1 ) ) return false ; rtx mem_lo = adjust_address ( dst , SImode , 0 ) ; if ( ! aarch64_mem_pair_operand ( mem_lo , SImode ) ) return false ; rtx tmp_reg = gen_reg_rtx ( SImode ) ; aarch64_expand_mov_immediate ( tmp_reg , lo ) ; rtx mem_hi = aarch64_move_pointer ( mem_lo , GET_MODE_SIZE ( SImode ) ) ; emit_move_insn ( mem_lo , tmp_reg ) ; emit_move_insn ( mem_hi , tmp_reg ) ; return true ; } </s>

Split a DImode store of a CONST_INT SRC to MEM DST as two SImode stores . Handle the case when the constant has identical bottom and top halves . This is beneficial when the two stores can be merged into an STP and we avoid synthesising potentially expensive immediates twice . Return true if such a split is possible .


<s> std :: pair < unsigned , const TargetRegisterClass * > SITargetLowering :: getRegForInlineAsmConstraint ( const TargetRegisterInfo * TRI , StringRef Constraint , MVT VT ) const { const TargetRegisterClass * RC = nullptr ; if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { default : return TargetLowering :: getRegForInlineAsmConstraint ( TRI , Constraint , VT ) ; case 's' : case 'r' : switch ( VT . getSizeInBits ( ) ) { default : return std :: make_pair ( 0U , nullptr ) ; case 32 : case 16 : RC = & AMDGPU :: SReg_32_XM0RegClass ; break ; case 64 : RC = & AMDGPU :: SGPR_64RegClass ; break ; case 128 : RC = & AMDGPU :: SReg_128RegClass ; break ; case 256 : RC = & AMDGPU :: SReg_256RegClass ; break ; case 512 : RC = & AMDGPU :: SReg_512RegClass ; break ; } break ; case 'v' : switch ( VT . getSizeInBits ( ) ) { default : return std :: make_pair ( 0U , nullptr ) ; case 32 : case 16 : RC = & AMDGPU :: VGPR_32RegClass ; break ; case 64 : RC = & AMDGPU :: VReg_64RegClass ; break ; case 96 : RC = & AMDGPU :: VReg_96RegClass ; break ; case 128 : RC = & AMDGPU :: VReg_128RegClass ; break ; case 256 : RC = & AMDGPU :: VReg_256RegClass ; break ; case 512 : RC = & AMDGPU :: VReg_512RegClass ; break ; } break ; } if ( RC && ( isTypeLegal ( VT ) || VT . SimpleTy == MVT :: i128 || VT . SimpleTy == MVT :: i16 || VT . SimpleTy == MVT :: f16 ) ) return std :: make_pair ( 0U , RC ) ; } if ( Constraint . size ( ) > 1 ) { if ( Constraint [ 1 ] == 'v' ) { RC = & AMDGPU :: VGPR_32RegClass ; } else if ( Constraint [ 1 ] == 's' ) { RC = & AMDGPU :: SGPR_32RegClass ; } if ( RC ) { uint32_t Idx ; bool Failed = Constraint . substr ( 2 ) . getAsInteger ( 10 , Idx ) ; if ( ! Failed && Idx < RC -> getNumRegs ( ) ) return std :: make_pair ( RC -> getRegister ( Idx ) , RC ) ; } } return TargetLowering :: getRegForInlineAsmConstraint ( TRI , Constraint , VT ) ; } </s>

Given a physical register constraint ( e.g .


<s> static rtx ix86_expand_sse_comi ( const struct builtin_description * d , tree arglist , rtx target ) { rtx pat ; tree arg0 = TREE_VALUE ( arglist ) ; tree arg1 = TREE_VALUE ( TREE_CHAIN ( arglist ) ) ; rtx op0 = expand_expr ( arg0 , NULL_RTX , VOIDmode , 0 ) ; rtx op1 = expand_expr ( arg1 , NULL_RTX , VOIDmode , 0 ) ; rtx op2 ; enum machine_mode mode0 = insn_data [ d -> icode ] . operand [ 0 ] . mode ; enum machine_mode mode1 = insn_data [ d -> icode ] . operand [ 1 ] . mode ; enum rtx_code comparison = d -> comparison ; if ( VECTOR_MODE_P ( mode0 ) ) op0 = safe_vector_operand ( op0 , mode0 ) ; if ( VECTOR_MODE_P ( mode1 ) ) op1 = safe_vector_operand ( op1 , mode1 ) ; if ( d -> flag & BUILTIN_DESC_SWAP_OPERANDS ) { rtx tmp = op1 ; op1 = op0 ; op0 = tmp ; } target = gen_reg_rtx ( SImode ) ; emit_move_insn ( target , const0_rtx ) ; target = gen_rtx_SUBREG ( QImode , target , 0 ) ; if ( ( optimize && ! register_operand ( op0 , mode0 ) ) || ! ( * insn_data [ d -> icode ] . operand [ 0 ] . predicate ) ( op0 , mode0 ) ) op0 = copy_to_mode_reg ( mode0 , op0 ) ; if ( ( optimize && ! register_operand ( op1 , mode1 ) ) || ! ( * insn_data [ d -> icode ] . operand [ 1 ] . predicate ) ( op1 , mode1 ) ) op1 = copy_to_mode_reg ( mode1 , op1 ) ; op2 = gen_rtx_fmt_ee ( comparison , mode0 , op0 , op1 ) ; pat = GEN_FCN ( d -> icode ) ( op0 , op1 ) ; if ( ! pat ) return 0 ; emit_insn ( pat ) ; emit_insn ( gen_rtx_SET ( VOIDmode , gen_rtx_STRICT_LOW_PART ( VOIDmode , target ) , gen_rtx_fmt_ee ( comparison , QImode , SET_DEST ( pat ) , const0_rtx ) ) ) ; return SUBREG_REG ( target ) ; } </s>

Subroutine of ix86_expand_builtin to take care of comi insns .


<s> static void fold_mergeeo_helper ( gimple_stmt_iterator * gsi , gimple * stmt , int use_odd ) { tree arg0 = gimple_call_arg ( stmt , 0 ) ; tree arg1 = gimple_call_arg ( stmt , 1 ) ; tree lhs = gimple_call_lhs ( stmt ) ; tree lhs_type = TREE_TYPE ( lhs ) ; int n_elts = TYPE_VECTOR_SUBPARTS ( lhs_type ) ; tree permute_type ; permute_type = map_to_integral_tree_type ( lhs_type ) ; tree_vector_builder elts ( permute_type , VECTOR_CST_NELTS ( arg0 ) , 1 ) ; for ( int i = 0 ; i < n_elts / 2 ; i ++ ) { elts . safe_push ( build_int_cst ( TREE_TYPE ( permute_type ) , 2 * i + use_odd ) ) ; elts . safe_push ( build_int_cst ( TREE_TYPE ( permute_type ) , 2 * i + use_odd + n_elts ) ) ; } tree permute = elts . build ( ) ; gimple * g = gimple_build_assign ( lhs , VEC_PERM_EXPR , arg0 , arg1 , permute ) ; gimple_set_location ( g , gimple_location ( stmt ) ) ; gsi_replace ( gsi , g , true ) ; } </s>

Helper function to handle the vector merge [ eo ] built-ins .


<s> void PPCTargetLowering :: insertSSPDeclarations ( Module & M ) const { if ( Subtarget . isAIXABI ( ) ) { M . getOrInsertGlobal ( AIXSSPCanaryWordName , Type :: getInt8PtrTy ( M . getContext ( ) ) ) ; return ; } if ( ! Subtarget . isTargetLinux ( ) ) return TargetLowering :: insertSSPDeclarations ( M ) ; } </s>

Inserts necessary declarations for SSP ( stack protection ) purpose .


<s> unsigned GCNHazardRecognizer :: PreEmitNoops ( MachineInstr * MI ) { int WaitStates = std :: max ( 0 , checkAnyInstHazards ( MI ) ) ; if ( SIInstrInfo :: isSMRD ( * MI ) ) return std :: max ( WaitStates , checkSMRDHazards ( MI ) ) ; if ( SIInstrInfo :: isVALU ( * MI ) ) WaitStates = std :: max ( WaitStates , checkVALUHazards ( MI ) ) ; if ( SIInstrInfo :: isVMEM ( * MI ) || SIInstrInfo :: isFLAT ( * MI ) ) WaitStates = std :: max ( WaitStates , checkVMEMHazards ( MI ) ) ; if ( SIInstrInfo :: isDPP ( * MI ) ) WaitStates = std :: max ( WaitStates , checkDPPHazards ( MI ) ) ; if ( isDivFMas ( MI -> getOpcode ( ) ) ) WaitStates = std :: max ( WaitStates , checkDivFMasHazards ( MI ) ) ; if ( isRWLane ( MI -> getOpcode ( ) ) ) WaitStates = std :: max ( WaitStates , checkRWLaneHazards ( MI ) ) ; if ( MI -> isInlineAsm ( ) ) return std :: max ( WaitStates , checkInlineAsmHazards ( MI ) ) ; if ( isSGetReg ( MI -> getOpcode ( ) ) ) return std :: max ( WaitStates , checkGetRegHazards ( MI ) ) ; if ( isSSetReg ( MI -> getOpcode ( ) ) ) return std :: max ( WaitStates , checkSetRegHazards ( MI ) ) ; if ( isRFE ( MI -> getOpcode ( ) ) ) return std :: max ( WaitStates , checkRFEHazards ( MI ) ) ; if ( ST . hasReadM0MovRelInterpHazard ( ) && ( TII . isVINTRP ( * MI ) || isSMovRel ( MI -> getOpcode ( ) ) ) ) return std :: max ( WaitStates , checkReadM0Hazards ( MI ) ) ; if ( ST . hasReadM0SendMsgHazard ( ) && isSendMsgTraceDataOrGDS ( TII , * MI ) ) return std :: max ( WaitStates , checkReadM0Hazards ( MI ) ) ; return WaitStates ; } </s>

PreEmitNoops - This callback is invoked prior to emitting an instruction .


<s> static rsqrts_type get_rsqrts_type ( machine_mode mode ) { switch ( mode ) { case DFmode : return gen_aarch64_rsqrtsdf ; case SFmode : return gen_aarch64_rsqrtssf ; case V2DFmode : return gen_aarch64_rsqrtsv2df ; case V2SFmode : return gen_aarch64_rsqrtsv2sf ; case V4SFmode : return gen_aarch64_rsqrtsv4sf ; default : gcc_unreachable ( ) ; } } </s>

Select reciprocal square root series step insn depending on machine mode .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . addPreserved < SlotIndexes > ( ) ; AU . addPreserved < LiveIntervals > ( ) ; AU . addPreservedID ( LiveVariablesID ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>


<s> bool valid_mov3q_const ( HOST_WIDE_INT i ) { return TARGET_ISAB && ( i == - 1 || IN_RANGE ( i , 1 , 7 ) ) ; } </s>

Return 1 if 'constant ' can be represented by mov3q on a ColdFire V4 core .


<s> static int stackSlotSize ( ) { return 8 ; } </s>


<s> int m32c_prepare_shift ( rtx * operands , int scale , int bits ) { rtx temp ; if ( GET_CODE ( operands [ 2 ] ) == CONST_INT && INTVAL ( operands [ 2 ] ) <= ( 1 << ( bits - 1 ) ) && INTVAL ( operands [ 2 ] ) >= - ( 1 << ( bits - 1 ) ) ) { operands [ 2 ] = GEN_INT ( scale * INTVAL ( operands [ 2 ] ) ) ; return 0 ; } if ( scale < 0 ) { temp = gen_reg_rtx ( QImode ) ; if ( GET_CODE ( operands [ 2 ] ) == CONST_INT ) temp = GEN_INT ( - INTVAL ( operands [ 2 ] ) ) ; else emit_move_insn ( temp , gen_rtx_NEG ( QImode , operands [ 2 ] ) ) ; } else temp = operands [ 2 ] ; operands [ 2 ] = temp ; return 0 ; } </s>

The m32c only has one shift , but it takes a signed count . GCC does n't want this , so we fake it by negating any shift count when we 're pretending to shift the other way .


<s> int pa_attr_length_indirect_call ( rtx_insn * insn ) { unsigned long distance = - 1 ; unsigned long total = IN_NAMED_SECTION_P ( cfun -> decl ) ? 0 : total_code_bytes ; if ( INSN_ADDRESSES_SET_P ( ) ) { distance = ( total + insn_current_reference_address ( insn ) ) ; if ( distance < total ) distance = - 1 ; } if ( TARGET_64BIT ) return 12 ; if ( TARGET_FAST_INDIRECT_CALLS ) return 8 ; if ( TARGET_PORTABLE_RUNTIME ) return 16 ; if ( ! TARGET_LONG_CALLS && ( ( TARGET_PA_20 && ! TARGET_SOM && distance < 7600000 ) || distance < MAX_PCREL17F_OFFSET ) ) return 8 ; if ( ! flag_pic ) return 12 ; if ( ! optimize_size ) { if ( TARGET_NO_SPACE_REGS ) return 28 ; if ( TARGET_PA_20 ) return 32 ; } return 20 ; } </s>

Return the attribute length of the indirect call instruction INSN . The length must match the code generated by output_indirect call . The returned length includes the delay slot . Currently , the delay slot of an indirect call sequence is not exposed and it is used by the sequence itself .


Relax the instruction in the given fragment to the next wider instruction .


<s>
void
ARMTargetLowering
::
ReplaceNodeResults
(
SDNode
*
N
,
SmallVectorImpl
<
SDValue
>
&
Results
,
SelectionDAG
&
DAG
)
const
{
SDValue
Res
;
switch
(
N
->
getOpcode
(
)
)
{
default
:
llvm_unreachable
(
"Don't know how to custom expand this!"
)
;
break
;
case
ISD
::
BIT_CONVERT
:
Res
=
ExpandBIT_CONVERT
(
N
,
DAG
)
;
break
;
case
ISD
::
SRL
:
case
ISD
::
SRA
:
Res
=
LowerShift
(
N
,
DAG
,
Subtarget
)
;
break
;
}
if
(
Res
.
getNode
(
)
)
Results
.
push_back
(
Res
)
;
}
</s>

ReplaceNodeResults - Replace the results of node with an illegal result type with new values built out of custom code .

ARM
ARM
"Don't know how to custom expand this!"
ISD::BIT_CONVERT
ISD::SRL
ISD::SRA


<s> void i386_pe_record_external_function ( tree decl , const char * name ) { struct extern_list * p ; p = ( struct extern_list * ) ggc_alloc ( sizeof * p ) ; p -> next = extern_head ; p -> decl = decl ; p -> name = name ; extern_head = p ; } </s>

Assemble an external function reference . We need to keep a list of these , so that we can output the function types at the end of the assembly . We ca n't output the types now , because we might see a definition of the function later on and emit debugging information for it then .


<s> rtx sh_movrt_set_dest ( const_rtx pat ) { if ( GET_CODE ( pat ) == PARALLEL ) pat = XVECEXP ( pat , 0 , 0 ) ; return GET_CODE ( pat ) == SET && arith_reg_dest ( XEXP ( pat , 0 ) , SImode ) && negt_reg_operand ( XEXP ( pat , 1 ) , VOIDmode ) ? XEXP ( pat , 0 ) : NULL ; } </s>

Given an insn , check whether it 's a 'movrt ' kind of insn , i.e . an insn that stores the negated T bit in a register , and return the destination register rtx , or null .


<s> bool isValid ( ) const { return ( Valid ) ; } </s>

Returns true if this iterator is still pointing at a valid entry .


<s> static bool match_pcrel_step2 ( rtx_insn * insn ) { rtx unspec ; rtx addr ; if ( TARGET_32BIT ) { if ( recog_memoized ( insn ) != CODE_FOR_insn_addr_shl16insli_32bit ) return false ; } else { if ( recog_memoized ( insn ) != CODE_FOR_insn_addr_shl16insli ) return false ; } unspec = SET_SRC ( PATTERN ( insn ) ) ; addr = XVECEXP ( unspec , 0 , 1 ) ; return ( GET_CODE ( addr ) == CONST && GET_CODE ( XEXP ( addr , 0 ) ) == UNSPEC && XINT ( XEXP ( addr , 0 ) , 1 ) == UNSPEC_HW0_PCREL ) ; } </s>

Returns true if INSN is the second instruction of a pc-relative address compuatation .


<s> bool avr_load_libgcc_p ( rtx op ) { machine_mode mode = GET_MODE ( op ) ; int n_bytes = GET_MODE_SIZE ( mode ) ; return ( n_bytes > 2 && ! AVR_HAVE_LPMX && avr_mem_flash_p ( op ) ) ; } </s>

Return true if a value of mode MODE is read from flash by __load_ * function from libgcc .


"Only FP0 could be passed as an argument"

runOnMachineFunction - Emit the function body .


<s> int microblaze_can_use_return_insn ( void ) { if ( ! reload_completed ) return 0 ; if ( df_regs_ever_live_p ( MB_ABI_SUB_RETURN_ADDR_REGNUM ) || profile_flag ) return 0 ; if ( current_frame_info . initialized ) return current_frame_info . total_size == 0 ; return compute_frame_size ( get_frame_size ( ) ) == 0 ; } </s>

Return nonzero if this function is known to have a null epilogue . This allows the optimizer to omit jumps to jumps if no stack was created .


<s> unsigned AMDGPUAsmParser :: validateTargetOperandClass ( MCParsedAsmOperand & Op , unsigned Kind ) { AMDGPUOperand & Operand = ( AMDGPUOperand & ) Op ; switch ( Kind ) { case MCK_addr64 : return Operand . isAddr64 ( ) ? Match_Success : Match_InvalidOperand ; case MCK_gds : return Operand . isGDS ( ) ? Match_Success : Match_InvalidOperand ; case MCK_lds : return Operand . isLDS ( ) ? Match_Success : Match_InvalidOperand ; case MCK_idxen : return Operand . isIdxen ( ) ? Match_Success : Match_InvalidOperand ; case MCK_offen : return Operand . isOffen ( ) ? Match_Success : Match_InvalidOperand ; case MCK_SSrcB32 : return Operand . isSSrcB32 ( ) ? Match_Success : Match_InvalidOperand ; case MCK_SSrcF32 : return Operand . isSSrcF32 ( ) ? Match_Success : Match_InvalidOperand ; case MCK_SoppBrTarget : return Operand . isSoppBrTarget ( ) ? Match_Success : Match_InvalidOperand ; case MCK_VReg32OrOff : return Operand . isVReg32OrOff ( ) ? Match_Success : Match_InvalidOperand ; case MCK_InterpSlot : return Operand . isInterpSlot ( ) ? Match_Success : Match_InvalidOperand ; case MCK_Attr : return Operand . isInterpAttr ( ) ? Match_Success : Match_InvalidOperand ; case MCK_AttrChan : return Operand . isAttrChan ( ) ? Match_Success : Match_InvalidOperand ; case MCK_ImmSMEMOffset : return Operand . isSMEMOffset ( ) ? Match_Success : Match_InvalidOperand ; case MCK_SReg_64 : case MCK_SReg_64_XEXEC : return Operand . isNull ( ) ? Match_Success : Match_InvalidOperand ; default : return Match_InvalidOperand ; } } </s>

Allow a target to add special case operand matching for things that tblgen doesn't/ca n't handle effectively .


<s> static int is_regular_file ( char * name ) { int ret ; struct stat statbuf ; ret = stat ( name , & statbuf ) ; return ! ret && S_ISREG ( statbuf . st_mode ) ; } </s>

Check to see if NAME is a regular file , i.e . not a directory .


<s> unsigned HexagonInstrInfo :: nonDbgBBSize ( const MachineBasicBlock * BB ) const { return nonDbgMICount ( BB -> instr_begin ( ) , BB -> instr_end ( ) ) ; } </s>

getInstrTimingClassLatency - Compute the instruction latency of a given instruction using Timing Class information , if available .


<s> Register X86RegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { const X86FrameLowering * TFI = getFrameLowering ( MF ) ; return TFI -> hasFP ( MF ) ? FramePtr : StackPtr ; } </s>


<s> void SPIRVInstructionSelector :: setupMF ( MachineFunction & MF , GISelKnownBits * KB , CodeGenCoverage & CoverageInfo , ProfileSummaryInfo * PSI , BlockFrequencyInfo * BFI ) { MRI = & MF . getRegInfo ( ) ; GR . setCurrentFunc ( MF ) ; InstructionSelector :: setupMF ( MF , KB , CoverageInfo , PSI , BFI ) ; } </s>


<s>
unsigned
X86InstrInfo
::
removeBranch
(
MachineBasicBlock
&
MBB
,
int
*
BytesRemoved
)
const
{
assert
(
!
BytesRemoved
&&
"code size not handled"
)
;
MachineBasicBlock
::
iterator
I
=
MBB
.
end
(
)
;
unsigned
Count
=
0
;
while
(
I
!=
MBB
.
begin
(
)
)
{
I
;
if
(
I
->
isDebugValue
(
)
)
continue
;
if
(
I
->
getOpcode
(
)
!=
X86
::
JMP_1
&&
X86
::
getCondFromBranchOpc
(
I
->
getOpcode
(
)
)
==
X86
::
COND_INVALID
)
break
;
I
->
eraseFromParent
(
)
;
I
=
MBB
.
end
(
)
;
++
Count
;
}
return
Count
;
}
</s>

Remove the branching code at the end of the specific MBB .


<s> bool WebAssemblyAsmBackend :: writeNopData ( raw_ostream & OS , uint64_t Count ) const { for ( uint64_t i = 0 ; i < Count ; ++ i ) OS << char ( WebAssembly :: Nop ) ; return true ; } </s>

Write an ( optimal ) nop sequence of Count bytes to the given output .

WebAssembly WebAssembly 0 WebAssembly::Nop


<s> bool isIncomingArgumentHandler ( ) const override { return true ; } </s>

Returns true if the handler is dealing with incoming arguments , i.e .


<s> const MipsRegisterInfo * getRegisterInfo ( ) const override { return & InstrInfo -> getRegisterInfo ( ) ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s> void AArch64PassConfig :: addIRPasses ( ) { addPass ( createAtomicExpandPass ( ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableAtomicTidy ) addPass ( createCFGSimplificationPass ( 1 , true , true , false , true ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None ) { if ( EnableLoopDataPrefetch ) addPass ( createLoopDataPrefetchPass ( ) ) ; if ( EnableFalkorHWPFFix ) addPass ( createFalkorMarkStridedAccessesPass ( ) ) ; } TargetPassConfig :: addIRPasses ( ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None ) addPass ( createInterleavedAccessPass ( ) ) ; if ( TM -> getOptLevel ( ) == CodeGenOpt :: Aggressive && EnableGEPOpt ) { addPass ( createSeparateConstOffsetFromGEPPass ( true ) ) ; addPass ( createEarlyCSEPass ( ) ) ; addPass ( createLICMPass ( ) ) ; } } </s>

Add common target configurable passes that perform LLVM IR to IR transforms following machine independent optimization .


<s> static unsigned int mips_autovectorize_vector_modes ( vector_modes * modes , bool ) { if ( ISA_HAS_MSA ) modes -> safe_push ( V16QImode ) ; return 0 ; } </s>


<s>
bool
HexagonExpandCondsets
::
split
(
MachineInstr
&
MI
,
std
::
set
<
unsigned
>
&
UpdRegs
)
{
if
(
TfrLimitActive
)
{
if
(
TfrCounter
>=
TfrLimit
)
return
false
;
TfrCounter
++
;
}
LLVM_DEBUG
(
dbgs
(
)
<<
"\nsplitting "
<<
printMBBReference
(
*
MI
.
getParent
(
)
)
<<
": "
<<
MI
)
;
MachineOperand
&
MD
=
MI
.
getOperand
(
0
)
;
MachineOperand
&
MP
=
MI
.
getOperand
(
1
)
;
assert
(
MD
.
isDef
(
)
)
;
unsigned
DR
=
MD
.
getReg
(
)
,
DSR
=
MD
.
getSubReg
(
)
;
bool
ReadUndef
=
MD
.
isUndef
(
)
;
MachineBasicBlock
::
iterator
At
=
MI
;
auto
updateRegs
=
[
&
UpdRegs
]
(
const
MachineInstr
&
MI
)
->
void
{
for
(
auto
&
Op
:
MI
.
operands
(
)
)
if
(
Op
.
isReg
(
)
)
UpdRegs
.
insert
(
Op
.
getReg
(
)
)
;
}
;
MachineOperand
&
ST
=
MI
.
getOperand
(
2
)
;
MachineOperand
&
SF
=
MI
.
getOperand
(
3
)
;
if
(
ST
.
isReg
(
)
&&
SF
.
isReg
(
)
)
{
RegisterRef
RT
(
ST
)
;
if
(
RT
==
RegisterRef
(
SF
)
)
{
updateRegs
(
MI
)
;
MI
.
setDesc
(
HII
->
get
(
TargetOpcode
::
COPY
)
)
;
unsigned
S
=
getRegState
(
ST
)
;
while
(
MI
.
getNumOperands
(
)
>
1
)
MI
.
RemoveOperand
(
MI
.
getNumOperands
(
)
1
)
;
MachineFunction
&
MF
=
*
MI
.
getParent
(
)
->
getParent
(
)
;
MachineInstrBuilder
(
MF
,
MI
)
.
addReg
(
RT
.
Reg
,
S
,
RT
.
Sub
)
;
return
true
;
}
}
MachineInstr
*
TfrT
=
genCondTfrFor
(
ST
,
At
,
DR
,
DSR
,
MP
,
true
,
ReadUndef
,
false
)
;
MachineInstr
*
TfrF
=
genCondTfrFor
(
SF
,
At
,
DR
,
DSR
,
MP
,
false
,
ReadUndef
,
true
)
;
LIS
->
InsertMachineInstrInMaps
(
*
TfrT
)
;
LIS
->
InsertMachineInstrInMaps
(
*
TfrF
)
;
updateRegs
(
MI
)
;
removeInstr
(
MI
)
;
return
true
;
}
</s>

Split into substrings around the occurrences of a separator character .


"__attribute__ ((__used__, visibility (\"hidden\"),\n"

"section (\".gnu.offload_funcs\"))) = { };\n\n"

"section (\".gnu.offload_vars\"))) = { };\n\n"

"__attribute__ ((__used__, visibility (\"hidden\"))) = {\n"

"  &__offload_func_table, &__offload_funcs_end,\n"

"  &__offload_var_table, &__offload_vars_end\n"

"void target_register_lib (const void *);\n\n"

"  target_register_lib (__OFFLOAD_TARGET_TABLE__);\n"

Generates object file with the descriptor for the target library .


<s>
bool
HexagonInstrInfo
::
PredicateInstruction
(
MachineInstr
*
MI
,
const
SmallVectorImpl
<
MachineOperand
>
&
Cond
)
const
{
int
Opc
=
MI
->
getOpcode
(
)
;
assert
(
isPredicable
(
MI
)
&&
"Expected predicable instruction"
)
;
bool
invertJump
=
(
!
Cond
.
empty
(
)
&&
Cond
[
0
]
.
isImm
(
)
&&
(
Cond
[
0
]
.
getImm
(
)
==
0
)
)
;
MI
->
setDesc
(
get
(
getMatchingCondBranchOpcode
(
Opc
,
invertJump
)
)
)
;
MI
->
addOperand
(
MI
->
getOperand
(
MI
->
getNumOperands
(
)
1
)
)
;
int
oper
;
for
(
oper
=
MI
->
getNumOperands
(
)
3
;
oper
>=
0
;
oper
)
{
MachineOperand
MO
=
MI
->
getOperand
(
oper
)
;
if
(
(
MO
.
isReg
(
)
&&
!
MO
.
isUse
(
)
&&
!
MO
.
isImplicit
(
)
)
)
{
break
;
}
if
(
MO
.
isReg
(
)
)
{
MI
->
getOperand
(
oper
+
1
)
.
ChangeToRegister
(
MO
.
getReg
(
)
,
MO
.
isDef
(
)
,
MO
.
isImplicit
(
)
,
MO
.
isKill
(
)
,
MO
.
isDead
(
)
,
MO
.
isUndef
(
)
,
MO
.
isDebug
(
)
)
;
}
else
if
(
MO
.
isImm
(
)
)
{
MI
->
getOperand
(
oper
+
1
)
.
ChangeToImmediate
(
MO
.
getImm
(
)
)
;
}
else
{
assert
(
false
&&
"Unexpected operand type"
)
;
}
}
int
regPos
=
invertJump
1
:
0
;
MachineOperand
PredMO
=
Cond
[
regPos
]
;
MI
->
getOperand
(
oper
+
1
)
.
ChangeToRegister
(
PredMO
.
getReg
(
)
,
PredMO
.
isDef
(
)
,
PredMO
.
isImplicit
(
)
,
PredMO
.
isKill
(
)
,
PredMO
.
isDead
(
)
,
PredMO
.
isUndef
(
)
,
PredMO
.
isDebug
(
)
)
;
return
true
;
}
</s>

Convert the instruction into a predicated instruction .


<s> Candidate ( ) : SU ( nullptr ) , GroupingCost ( 0 ) , ResourcesCost ( 0 ) { } </s>


<s> bool SparcDAGToDAGISel :: SelectInlineAsmMemoryOperand ( const SDValue & Op , char ConstraintCode , std :: vector < SDValue > & OutOps ) { SDValue Op0 , Op1 ; switch ( ConstraintCode ) { default : return true ; case 'm' : if ( ! SelectADDRrr ( Op , Op0 , Op1 ) ) SelectADDRri ( Op , Op0 , Op1 ) ; break ; } OutOps . push_back ( Op0 ) ; OutOps . push_back ( Op1 ) ; return false ; } </s>

SelectInlineAsmMemoryOperand - Select the specified address as a target addressing mode , according to the specified constraint .


<s>
static
uint8_t
name
(
struct
InternalInstruction
*
insn
,
\
OperandType
type
,
\
uint8_t
index
,
\
uint8_t
*
valid
)
{
\
*
valid
=
1
;
\
switch
(
type
)
{
\
default
:
\
unreachable
(
"Unhandled register type"
)
;
\
case
TYPE_Rv
:
\
return
base
+
index
;
\
case
TYPE_R8
:
\
if
(
insn
->
rexPrefix
&&
\
index
>=
4
&&
index
<=
7
)
{
\
return
prefix
##
_SPL
+
(
index
4
)
;
\
}
else
{
\
return
prefix
##
_AL
+
index
;
\
}
\
case
TYPE_R16
:
\
return
prefix
##
_AX
+
index
;
\
case
TYPE_R32
:
\
return
prefix
##
_EAX
+
index
;
\
case
TYPE_R64
:
\
return
prefix
##
_RAX
+
index
;
\
case
TYPE_XMM128
:
\
case
TYPE_XMM64
:
\
case
TYPE_XMM32
:
\
case
TYPE_XMM
:
\
return
prefix
##
_XMM0
+
index
;
\
case
TYPE_MM64
:
\
case
TYPE_MM32
:
\
case
TYPE_MM
:
\
if
(
index
>
7
)
\
*
valid
=
0
;
\
return
prefix
##
_MM0
+
index
;
\
case
TYPE_SEGMENTREG
:
\
if
(
index
>
5
)
\
*
valid
=
0
;
\
return
prefix
##
_ES
+
index
;
\
case
TYPE_DEBUGREG
:
\
if
(
index
>
7
)
\
*
valid
=
0
;
\
return
prefix
##
_DR0
+
index
;
\
case
TYPE_CR32
:
\
if
(
index
>
7
)
\
*
valid
=
0
;
\
return
prefix
##
_ECR0
+
index
;
\
case
TYPE_CR64
:
\
if
(
index
>
8
)
\
*
valid
=
0
;
\
return
prefix
##
_RCR0
+
index
;
\
}
\
}
</s>

Gets the name of the pass we are mixed into .


<s> void JVMRegisterInfo :: eliminateFrameIndex ( MachineBasicBlock :: iterator II , int SPAdj , unsigned FIOperandNum , RegScavenger * ) const { } </s>

This method must be overriden to eliminate abstract frame indices from instructions which may use them .


<s> static bool arm_xscale_rtx_costs ( rtx x , enum rtx_code code , enum rtx_code outer_code , int * total , bool speed ) { machine_mode mode = GET_MODE ( x ) ; if ( TARGET_THUMB ) { * total = thumb1_rtx_costs ( x , code , outer_code ) ; return true ; } switch ( code ) { case COMPARE : if ( GET_CODE ( XEXP ( x , 0 ) ) != MULT ) return arm_rtx_costs_1 ( x , outer_code , total , speed ) ; * total = COSTS_N_INSNS ( 3 ) ; return false ; case MULT : if ( mode == DImode && ( GET_CODE ( XEXP ( x , 0 ) ) == GET_CODE ( XEXP ( x , 1 ) ) ) && ( GET_CODE ( XEXP ( x , 0 ) ) == ZERO_EXTEND || GET_CODE ( XEXP ( x , 0 ) ) == SIGN_EXTEND ) ) { * total = COSTS_N_INSNS ( 2 ) ; return false ; } if ( mode == DImode ) { * total = COSTS_N_INSNS ( 5 ) ; return false ; } if ( CONST_INT_P ( XEXP ( x , 1 ) ) ) { unsigned HOST_WIDE_INT i = INTVAL ( XEXP ( x , 1 ) ) ; int cost = 1 ; unsigned HOST_WIDE_INT masked_const ; if ( i & 0x80000000 ) i = ~ i ; i &= ( unsigned HOST_WIDE_INT ) 0xffffffff ; masked_const = i & 0xffff8000 ; if ( masked_const != 0 ) { cost ++ ; masked_const = i & 0xf8000000 ; if ( masked_const != 0 ) cost ++ ; } * total = COSTS_N_INSNS ( cost ) ; return false ; } if ( mode == SImode ) { * total = COSTS_N_INSNS ( 3 ) ; return false ; } * total = COSTS_N_INSNS ( 20 ) ; return false ; default : return arm_rtx_costs_1 ( x , outer_code , total , speed ) ; } } </s>

RTX cost for XScale CPUs . Thumb-2 is not supported on any xscale cores , so it can be ignored .


<s> void initializePass ( ) override { pushTTIStack ( this ) ; } </s>

initializePass - This method may be overriden by immutable passes to allow them to perform various initialization actions they require .


"RegVT not supported by FORMAL_ARGUMENTS Lowering"

"TODO implement argument passing on stack"

This hook must be implemented to lower the incoming ( formal ) arguments , described by the Ins array , into the specified DAG .


<s>
std
::
pair
<
unsigned
,
const
TargetRegisterClass
*
>
MipsTargetLowering
::
getRegForInlineAsmConstraint
(
const
std
::
string
&
Constraint
,
MVT
VT
)
const
{
if
(
Constraint
.
size
(
)
==
1
)
{
switch
(
Constraint
[
0
]
)
{
case
'd'
:
case
'y'
:
case
'r'
:
if
(
VT
==
MVT
::
i32
||
VT
==
MVT
::
i16
||
VT
==
MVT
::
i8
)
{
if
(
Subtarget
->
inMips16Mode
(
)
)
return
std
::
make_pair
(
0U
,
&
Mips
::
CPU16RegsRegClass
)
;
return
std
::
make_pair
(
0U
,
&
Mips
::
GPR32RegClass
)
;
}
if
(
VT
==
MVT
::
i64
&&
!
HasMips64
)
return
std
::
make_pair
(
0U
,
&
Mips
::
GPR32RegClass
)
;
if
(
VT
==
MVT
::
i64
&&
HasMips64
)
return
std
::
make_pair
(
0U
,
&
Mips
::
GPR64RegClass
)
;
return
std
::
make_pair
(
0u
,
static_cast
<
const
TargetRegisterClass
*
>
(
0
)
)
;
case
'f'
:
if
(
VT
==
MVT
::
f32
)
return
std
::
make_pair
(
0U
,
&
Mips
::
FGR32RegClass
)
;
if
(
(
VT
==
MVT
::
f64
)
&&
(
!
Subtarget
->
isSingleFloat
(
)
)
)
{
if
(
Subtarget
->
isFP64bit
(
)
)
return
std
::
make_pair
(
0U
,
&
Mips
::
FGR64RegClass
)
;
return
std
::
make_pair
(
0U
,
&
Mips
::
AFGR64RegClass
)
;
}
break
;
case
'c'
:
if
(
VT
==
MVT
::
i32
)
return
std
::
make_pair
(
(
unsigned
)
Mips
::
T9
,
&
Mips
::
GPR32RegClass
)
;
assert
(
VT
==
MVT
::
i64
&&
"Unexpected type."
)
;
return
std
::
make_pair
(
(
unsigned
)
Mips
::
T9_64
,
&
Mips
::
GPR64RegClass
)
;
case
'l'
:
if
(
VT
==
MVT
::
i32
)
return
std
::
make_pair
(
(
unsigned
)
Mips
::
LO0
,
&
Mips
::
LO32RegClass
)
;
return
std
::
make_pair
(
(
unsigned
)
Mips
::
LO0_64
,
&
Mips
::
LO64RegClass
)
;
case
'x'
:
return
std
::
make_pair
(
0u
,
static_cast
<
const
TargetRegisterClass
*
>
(
0
)
)
;
}
}
std
::
pair
<
unsigned
,
const
TargetRegisterClass
*
>
R
;
R
=
parseRegForInlineAsmConstraint
(
Constraint
,
VT
)
;
if
(
R
.
second
)
return
R
;
return
TargetLowering
::
getRegForInlineAsmConstraint
(
Constraint
,
VT
)
;
}
</s>

Given a physical register constraint ( e.g .


<s> void ARMWinCOFFStreamer :: emitThumbFunc ( MCSymbol * Symbol ) { getAssembler ( ) . setIsThumbFunc ( Symbol ) ; } </s>

Note in the output that the specified Func is a Thumb mode function ( ARM target only ) .


<s> void Z80AsmPrinter :: EmitInstruction ( const MachineInstr * MI ) { Z80MCInstLower MCInstLowering ( Mang , * MF , * this ) ; MCInst TmpInst ; MCInstLowering . Lower ( MI , TmpInst ) ; OutStreamer . EmitInstruction ( TmpInst ) ; } </s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s> Optional < DestSourcePair > RISCVInstrInfo :: isCopyInstrImpl ( const MachineInstr & MI ) const { if ( MI . isMoveReg ( ) ) return DestSourcePair { MI . getOperand ( 0 ) , MI . getOperand ( 1 ) } ; switch ( MI . getOpcode ( ) ) { default : break ; case RISCV :: ADDI : if ( MI . getOperand ( 1 ) . isReg ( ) && MI . getOperand ( 2 ) . isImm ( ) && MI . getOperand ( 2 ) . getImm ( ) == 0 ) return DestSourcePair { MI . getOperand ( 0 ) , MI . getOperand ( 1 ) } ; break ; case RISCV :: FSGNJ_D : case RISCV :: FSGNJ_S : if ( MI . getOperand ( 1 ) . isReg ( ) && MI . getOperand ( 2 ) . isReg ( ) && MI . getOperand ( 1 ) . getReg ( ) == MI . getOperand ( 2 ) . getReg ( ) ) return DestSourcePair { MI . getOperand ( 0 ) , MI . getOperand ( 1 ) } ; break ; } return None ; } </s>

If the specific machine instruction is a instruction that moves/copies value from one register to another register return destination and source registers as machine operands .


<s> static bool aarch64_modes_tieable_p ( machine_mode mode1 , machine_mode mode2 ) { if ( GET_MODE_CLASS ( mode1 ) == GET_MODE_CLASS ( mode2 ) ) return true ; if ( aarch64_vector_data_mode_p ( mode1 ) && aarch64_vector_data_mode_p ( mode2 ) ) return true ; if ( aarch64_vector_mode_supported_p ( mode1 ) || aarch64_vector_mode_supported_p ( mode2 ) ) return true ; return false ; } </s>

Implement MODES_TIEABLE_P . In principle we should always return true . However due to issues with register allocation it is preferable to avoid tieing integer scalar and FP scalar modes . Executing integer operations in general registers is better than treating them as scalar vector operations . This reduces latency and avoids redundant int < - > FP moves . So tie modes if they are either the same class , or vector modes with other vector modes , vector structs or any scalar mode .


<s> Optional < Instruction * > NVPTXTTIImpl :: instCombineIntrinsic ( InstCombiner & IC , IntrinsicInst & II ) const { if ( Instruction * I = simplifyNvvmIntrinsic ( & II , IC ) ) { return I ; } return None ; } </s>

Targets can implement their own combinations for target-specific intrinsics .


<s>
SDValue
PatmosTargetLowering
::
LowerCallResult
(
SDValue
Chain
,
SDValue
InFlag
,
CallingConv
::
ID
CallConv
,
bool
isVarArg
,
const
SmallVectorImpl
<
ISD
::
InputArg
>
&
Ins
,
SDLoc
dl
,
SelectionDAG
&
DAG
,
SmallVectorImpl
<
SDValue
>
&
InVals
)
const
{
SmallVector
<
CCValAssign
,
16
>
RVLocs
;
CCState
CCInfo
(
CallConv
,
isVarArg
,
DAG
.
getMachineFunction
(
)
,
getTargetMachine
(
)
,
RVLocs
,
*
DAG
.
getContext
(
)
)
;
CCInfo
.
AnalyzeCallResult
(
Ins
,
RetCC_Patmos
)
;
for
(
unsigned
i
=
0
;
i
!=
RVLocs
.
size
(
)
;
++
i
)
{
assert
(
(
RVLocs
[
i
]
.
getLocReg
(
)
==
Patmos
::
R1
||
RVLocs
[
i
]
.
getLocReg
(
)
==
Patmos
::
R2
)
&&
"Invalid return register"
)
;
Chain
=
DAG
.
getCopyFromReg
(
Chain
,
dl
,
RVLocs
[
i
]
.
getLocReg
(
)
,
MVT
::
i32
,
InFlag
)
.
getValue
(
1
)
;
InFlag
=
Chain
.
getValue
(
2
)
;
InVals
.
push_back
(
Chain
.
getValue
(
0
)
)
;
}
return
Chain
;
}
</s>

LowerCallResult - Lower the result values of an ISD : :CALL into the appropriate copies out of appropriate physical registers .


<s> X86Subtarget & X86Subtarget :: initializeSubtargetDependencies ( StringRef CPU , StringRef FS ) { initializeEnvironment ( ) ; initSubtargetFeatures ( CPU , FS ) ; return * this ; } </s>

initializeSubtargetDependencies - Initializes using a CPU , a TuneCPU , and feature string so that we can use initializer lists for subtarget initialization .


<s> unsigned postOffset ( unsigned LogAlign = 0 ) const { unsigned PO = Offset + Size ; return PO ; } </s>

Compute the offset immediately following this block .


"WebAssembly can only return up to one value"

"WebAssembly doesn't support non-C calling conventions"

"WebAssembly doesn't support varargs yet"

"WebAssembly hasn't implemented byval results"

"WebAssembly hasn't implemented inalloca results"

"WebAssembly hasn't implemented nest results"

"WebAssembly hasn't implemented cons regs results"

"WebAssembly hasn't implemented cons regs last results"

"WebAssembly doesn't support non-fixed results yet"

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .


"invalid feature modifier in %<-march=%s%>"

Validate a command-line -march option . Parse the arch and extensions ( if any ) specified in STR and throw errors if appropriate . Put the results , if they are valid , in RES and ISA_FLAGS . Return whether the option is valid .


"ReadCycleWrite is only to be used on riscv32"

This method should be implemented by targets that mark instructions with the 'usesCustomInserter ' flag .


"instruction buffer too short to truncate"

Like resize , but requires that N is less than size ( ) .


<s> static enum aarch64_parse_opt_result aarch64_parse_tune ( const char * to_parse , const struct processor * * res ) { const struct processor * cpu ; char * str = ( char * ) alloca ( strlen ( to_parse ) + 1 ) ; strcpy ( str , to_parse ) ; for ( cpu = all_cores ; cpu -> name != NULL ; cpu ++ ) { if ( strcmp ( cpu -> name , str ) == 0 ) { * res = cpu ; return AARCH64_PARSE_OK ; } } return AARCH64_PARSE_INVALID_ARG ; } </s>


"Callee should be an llvm::Function object."

"failed to perform tail call elimination on a call "

This hook must be implemented to lower calls into the specified DAG .


<s>
SDValue
BPFTargetLowering
::
LowerCallResult
(
SDValue
Chain
,
SDValue
InFlag
,
CallingConv
::
ID
CallConv
,
bool
IsVarArg
,
const
SmallVectorImpl
<
ISD
::
InputArg
>
&
Ins
,
const
SDLoc
&
DL
,
SelectionDAG
&
DAG
,
SmallVectorImpl
<
SDValue
>
&
InVals
)
const
{
MachineFunction
&
MF
=
DAG
.
getMachineFunction
(
)
;
SmallVector
<
CCValAssign
,
16
>
RVLocs
;
CCState
CCInfo
(
CallConv
,
IsVarArg
,
MF
,
RVLocs
,
*
DAG
.
getContext
(
)
)
;
if
(
Ins
.
size
(
)
>=
2
)
{
fail
(
DL
,
DAG
,
"only small returns supported"
)
;
for
(
unsigned
i
=
0
,
e
=
Ins
.
size
(
)
;
i
!=
e
;
++
i
)
InVals
.
push_back
(
DAG
.
getConstant
(
0
,
DL
,
Ins
[
i
]
.
VT
)
)
;
return
DAG
.
getCopyFromReg
(
Chain
,
DL
,
1
,
Ins
[
0
]
.
VT
,
InFlag
)
.
getValue
(
1
)
;
}
CCInfo
.
AnalyzeCallResult
(
Ins
,
RetCC_BPF64
)
;
for
(
auto
&
Val
:
RVLocs
)
{
Chain
=
DAG
.
getCopyFromReg
(
Chain
,
DL
,
Val
.
getLocReg
(
)
,
Val
.
getValVT
(
)
,
InFlag
)
.
getValue
(
1
)
;
InFlag
=
Chain
.
getValue
(
2
)
;
InVals
.
push_back
(
Chain
.
getValue
(
0
)
)
;
}
return
Chain
;
}
</s>


<s> bool isToken ( ) const { return Kind == Token ; } </s>


<s>
StringRef
getPassName
(
)
const
override
{
return
"Patmos Function Splitter"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> bool HexagonGenInsert :: removeDeadCode ( MachineDomTreeNode * N ) { bool Changed = false ; for ( auto * DTN : children < MachineDomTreeNode * > ( N ) ) Changed |= removeDeadCode ( DTN ) ; MachineBasicBlock * B = N -> getBlock ( ) ; std :: vector < MachineInstr * > Instrs ; for ( auto I = B -> rbegin ( ) , E = B -> rend ( ) ; I != E ; ++ I ) Instrs . push_back ( & * I ) ; for ( auto I = Instrs . begin ( ) , E = Instrs . end ( ) ; I != E ; ++ I ) { MachineInstr * MI = * I ; unsigned Opc = MI -> getOpcode ( ) ; if ( Opc == TargetOpcode :: LIFETIME_START || Opc == TargetOpcode :: LIFETIME_END ) continue ; bool Store = false ; if ( MI -> isInlineAsm ( ) || ! MI -> isSafeToMove ( nullptr , Store ) ) continue ; bool AllDead = true ; SmallVector < unsigned , 2 > Regs ; for ( const MachineOperand & MO : MI -> operands ( ) ) { if ( ! MO . isReg ( ) || ! MO . isDef ( ) ) continue ; unsigned R = MO . getReg ( ) ; if ( ! TargetRegisterInfo :: isVirtualRegister ( R ) || ! MRI -> use_nodbg_empty ( R ) ) { AllDead = false ; break ; } Regs . push_back ( R ) ; } if ( ! AllDead ) continue ; B -> erase ( MI ) ; for ( unsigned I = 0 , N = Regs . size ( ) ; I != N ; ++ I ) MRI -> markUsesInDebugValueAsUndef ( Regs [ I ] ) ; Changed = true ; } return Changed ; } </s>

Remove all dead instructions between the I and E .


<s>
void
PPCHazardRecognizer970
::
EmitInstruction
(
SUnit
*
SU
)
{
const
SDNode
*
Node
=
SU
->
getNode
(
)
->
getGluedMachineNode
(
)
;
bool
isFirst
,
isSingle
,
isCracked
,
isLoad
,
isStore
;
PPCII
::
PPC970_Unit
InstrType
=
GetInstrType
(
Node
->
getOpcode
(
)
,
isFirst
,
isSingle
,
isCracked
,
isLoad
,
isStore
)
;
if
(
InstrType
==
PPCII
::
PPC970_Pseudo
)
return
;
unsigned
Opcode
=
Node
->
getMachineOpcode
(
)
;
if
(
Opcode
==
PPC
::
MTCTR
||
Opcode
==
PPC
::
MTCTR8
)
HasCTRSet
=
true
;
if
(
isStore
)
{
unsigned
ThisStoreSize
;
switch
(
Opcode
)
{
default
:
llvm_unreachable
(
"Unknown store instruction!"
)
;
case
PPC
::
STB
:
case
PPC
::
STB8
:
case
PPC
::
STBU
:
case
PPC
::
STBU8
:
case
PPC
::
STBX
:
case
PPC
::
STBX8
:
case
PPC
::
STVEBX
:
ThisStoreSize
=
1
;
break
;
case
PPC
::
STH
:
case
PPC
::
STH8
:
case
PPC
::
STHU
:
case
PPC
::
STHU8
:
case
PPC
::
STHX
:
case
PPC
::
STHX8
:
case
PPC
::
STVEHX
:
case
PPC
::
STHBRX
:
ThisStoreSize
=
2
;
break
;
case
PPC
::
STFS
:
case
PPC
::
STFSU
:
case
PPC
::
STFSX
:
case
PPC
::
STWX
:
case
PPC
::
STWX8
:
case
PPC
::
STWUX
:
case
PPC
::
STW
:
case
PPC
::
STW8
:
case
PPC
::
STWU
:
case
PPC
::
STVEWX
:
case
PPC
::
STFIWX
:
case
PPC
::
STWBRX
:
ThisStoreSize
=
4
;
break
;
case
PPC
::
STD_32
:
case
PPC
::
STDX_32
:
case
PPC
::
STD
:
case
PPC
::
STDU
:
case
PPC
::
STFD
:
case
PPC
::
STFDX
:
case
PPC
::
STDX
:
case
PPC
::
STDUX
:
ThisStoreSize
=
8
;
break
;
case
PPC
::
STVX
:
case
PPC
::
STVXL
:
ThisStoreSize
=
16
;
break
;
}
StoreSize
[
NumStores
]
=
ThisStoreSize
;
StorePtr1
[
NumStores
]
=
Node
->
getOperand
(
1
)
;
StorePtr2
[
NumStores
]
=
Node
->
getOperand
(
2
)
;
++
NumStores
;
}
if
(
InstrType
==
PPCII
::
PPC970_BRU
||
isSingle
)
NumIssued
=
4
;
++
NumIssued
;
if
(
isCracked
)
++
NumIssued
;
if
(
NumIssued
==
5
)
EndDispatchGroup
(
)
;
}
</s>


<s> MCObjectWriter * createObjectWriter ( raw_ostream & OS ) const { return createMipsELFObjectWriter ( OS , OSType , IsLittle , Is64Bit ) ; } </s>

Create a new MCObjectWriter instance for use by the assembler backend to emit the final object file .


<s>
StringRef
getPassName
(
)
const
override
{
return
"M88k Assembly Printer"
;
}
</s>


<s> virtual const AlphaInstrInfo * getInstrInfo ( ) const { return & InstrInfo ; } </s>


<s> ARMSubtarget :: ARMSubtarget ( const Triple & TT , const std :: string & CPU , const std :: string & FS , const ARMBaseTargetMachine & TM , bool IsLittle ) : ARMGenSubtargetInfo ( TT , CPU , FS ) , ARMProcFamily ( Others ) , ARMProcClass ( None ) , ARMArch ( ARMv4t ) , stackAlignment ( 4 ) , CPUString ( CPU ) , IsLittle ( IsLittle ) , TargetTriple ( TT ) , Options ( TM . Options ) , TM ( TM ) , FrameLowering ( initializeFrameLowering ( CPU , FS ) ) , InstrInfo ( isThumb1Only ( ) ? ( ARMBaseInstrInfo * ) new Thumb1InstrInfo ( * this ) : ! isThumb ( ) ? ( ARMBaseInstrInfo * ) new ARMInstrInfo ( * this ) : ( ARMBaseInstrInfo * ) new Thumb2InstrInfo ( * this ) ) , TLInfo ( TM , * this ) { } </s>

This constructor initializes the data members to match that of the specified triple .

ARM ARM ARM ARM ARM ARM ARM ARM ARM 4 ARM ARM ARM ARM


<s> bool X86TargetLowering :: isMaskAndCmp0FoldingBeneficial ( const Instruction & AndI ) const { return true ; } </s>

Return if the target supports combining a chain like :


<s> MachineInstr * SystemZInstrInfo :: foldMemoryOperandImpl ( MachineFunction & MF , MachineInstr * MI , ArrayRef < unsigned > Ops , MachineInstr * LoadMI ) const { return nullptr ; } </s>

foldMemoryOperand - Same as the previous version except it allows folding of any load and store from / to any address , not just from a specific stack slot .


<s> void SITargetLowering :: legalizeTargetIndependentNode ( SDNode * Node , SelectionDAG & DAG ) const { SmallVector < SDValue , 8 > Ops ; for ( unsigned i = 0 ; i < Node -> getNumOperands ( ) ; ++ i ) { if ( ! isa < FrameIndexSDNode > ( Node -> getOperand ( i ) ) ) { Ops . push_back ( Node -> getOperand ( i ) ) ; continue ; } SDLoc DL ( Node ) ; Ops . push_back ( SDValue ( DAG . getMachineNode ( AMDGPU :: S_MOV_B32 , DL , Node -> getOperand ( i ) . getValueType ( ) , Node -> getOperand ( i ) ) , 0 ) ) ; } DAG . UpdateNodeOperands ( Node , Ops ) ; } </s>

Legalize target independent instructions ( e.g .


<s> void WebAssemblyAsmPrinter :: emitEndOfAsmFile ( Module & M ) { emitExternalDecls ( M ) ; for ( const auto & F : M ) { if ( ! F . isIntrinsic ( ) && F . hasAddressTaken ( ) ) { MCSymbolWasm * FunctionTable = WebAssembly :: getOrCreateFunctionTableSymbol ( OutContext , Subtarget ) ; OutStreamer -> emitSymbolAttribute ( FunctionTable , MCSA_NoDeadStrip ) ; break ; } } for ( const auto & G : M . globals ( ) ) { if ( ! G . hasInitializer ( ) && G . hasExternalLinkage ( ) && ! WebAssembly :: isWasmVarAddressSpace ( G . getAddressSpace ( ) ) && G . getValueType ( ) -> isSized ( ) ) { uint16_t Size = M . getDataLayout ( ) . getTypeAllocSize ( G . getValueType ( ) ) ; OutStreamer -> emitELFSize ( getSymbol ( & G ) , MCConstantExpr :: create ( Size , OutContext ) ) ; } } if ( const NamedMDNode * Named = M . getNamedMetadata ( "wasm.custom_sections" ) ) { for ( const Metadata * MD : Named -> operands ( ) ) { const auto * Tuple = dyn_cast < MDTuple > ( MD ) ; if ( ! Tuple || Tuple -> getNumOperands ( ) != 2 ) continue ; const MDString * Name = dyn_cast < MDString > ( Tuple -> getOperand ( 0 ) ) ; const MDString * Contents = dyn_cast < MDString > ( Tuple -> getOperand ( 1 ) ) ; if ( ! Name || ! Contents ) continue ; OutStreamer -> PushSection ( ) ; std :: string SectionName = ( ".custom_section." + Name -> getString ( ) ) . str ( ) ; MCSectionWasm * MySection = OutContext . getWasmSection ( SectionName , SectionKind :: getMetadata ( ) ) ; OutStreamer -> SwitchSection ( MySection ) ; OutStreamer -> emitBytes ( Contents -> getString ( ) ) ; OutStreamer -> PopSection ( ) ; } } EmitProducerInfo ( M ) ; EmitTargetFeatures ( M ) ; } </s>

This virtual method can be overridden by targets that want to emit something at the end of their file .


<s>
static
void
visium_print_operand_address
(
FILE
*
file
,
enum
machine_mode
mode
,
rtx
addr
)
{
switch
(
GET_CODE
(
addr
)
)
{
case
REG
:
case
SUBREG
:
fprintf
(
file
,
"(%s)"
,
reg_names
[
true_regnum
(
addr
)
]
)
;
break
;
case
PLUS
:
{
rtx
x
=
XEXP
(
addr
,
0
)
,
y
=
XEXP
(
addr
,
1
)
;
switch
(
GET_CODE
(
x
)
)
{
case
REG
:
case
SUBREG
:
if
(
CONST_INT_P
(
y
)
)
{
unsigned
int
regno
=
true_regnum
(
x
)
;
HOST_WIDE_INT
val
=
INTVAL
(
y
)
;
switch
(
mode
)
{
case
SImode
:
case
DImode
:
case
SFmode
:
case
DFmode
:
val
>>=
2
;
break
;
case
HImode
:
val
>>=
1
;
break
;
case
QImode
:
default
:
break
;
}
fprintf
(
file
,
HOST_WIDE_INT_PRINT_DEC
"(%s)"
,
val
,
reg_names
[
regno
]
)
;
}
else
fatal_insn
(
"illegal operand address (1)"
,
addr
)
;
break
;
default
:
if
(
CONSTANT_P
(
x
)
&&
CONSTANT_P
(
y
)
)
output_addr_const
(
file
,
addr
)
;
else
fatal_insn
(
"illegal operand address (2)"
,
addr
)
;
break
;
}
}
break
;
case
LABEL_REF
:
case
SYMBOL_REF
:
case
CONST_INT
:
case
CONST
:
output_addr_const
(
file
,
addr
)
;
break
;
case
NOTE
:
if
(
NOTE_KIND
(
addr
)
!=
NOTE_INSN_DELETED_LABEL
)
fatal_insn
(
"illegal operand address (3)"
,
addr
)
;
break
;
case
CODE_LABEL
:
asm_fprintf
(
file
,
"%LL%d"
,
CODE_LABEL_NUMBER
(
addr
)
)
;
break
;
default
:
fatal_insn
(
"illegal operand address (4)"
,
addr
)
;
break
;
}
}
</s>

Implement TARGET_PRINT_OPERAND_ADDRESS . Output to stdio stream FILE the assembler syntax for an instruction operand that is a memory reference whose address is ADDR .

visium
"(%s)"
0
1
2
1
"(%s)"
"illegal operand address (1)"
"illegal operand address (2)"
"illegal operand address (3)"
"%LL%d"
"illegal operand address (4)"


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const { AU . setPreservesAll ( ) ; AU . addRequired < MachineModuleInfo > ( ) ; AU . addRequired < DwarfWriter > ( ) ; SPUAsmPrinter :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


"SGPR spill should have been removed in SILowerSGPRSpills"

processFunctionBeforeFrameFinalized - This method is called immediately before the specified function 's frame layout ( MF.getFrameInfo ( ) ) is finalized .


<s> SDValue PIC16TargetLowering :: LowerFormalArguments ( SDValue Chain , CallingConv :: ID CallConv , bool isVarArg , const SmallVectorImpl < ISD :: InputArg > & Ins , DebugLoc dl , SelectionDAG & DAG , SmallVectorImpl < SDValue > & InVals ) { unsigned NumArgVals = Ins . size ( ) ; MachineFunction & MF = DAG . getMachineFunction ( ) ; const Function * F = MF . getFunction ( ) ; std :: string FuncName = F -> getName ( ) ; ResetTmpOffsetMap ( ) ; InitReservedFrameCount ( F ) ; const char * tmpName = createESName ( PAN :: getArgsLabel ( FuncName ) ) ; SDValue ES = DAG . getTargetExternalSymbol ( tmpName , MVT :: i8 ) ; SDVTList VTs = DAG . getVTList ( MVT :: i8 , MVT :: Other ) ; SDValue BS = DAG . getConstant ( 1 , MVT :: i8 ) ; for ( unsigned i = 0 ; i < NumArgVals ; ++ i ) { SDValue Offset = DAG . getConstant ( i , MVT :: i8 ) ; SDValue PICLoad = DAG . getNode ( PIC16ISD :: PIC16LdArg , dl , VTs , Chain , ES , BS , Offset ) ; Chain = getChain ( PICLoad ) ; InVals . push_back ( PICLoad ) ; } return Chain ; } </s>

This hook must be implemented to lower the incoming ( formal ) arguments , described by the Ins array , into the specified DAG .


<s> virtual const MBlazeInstrInfo * getInstrInfo ( ) const { return & InstrInfo ; } </s>


<s>
SUnit
*
R600SchedStrategy
::
pickNode
(
bool
&
IsTopNode
)
{
SUnit
*
SU
=
nullptr
;
NextInstKind
=
IDOther
;
IsTopNode
=
false
;
bool
AllowSwitchToAlu
=
(
CurEmitted
>=
InstKindLimit
[
CurInstKind
]
)
||
(
Available
[
CurInstKind
]
.
empty
(
)
)
;
bool
AllowSwitchFromAlu
=
(
CurEmitted
>=
InstKindLimit
[
CurInstKind
]
)
&&
(
!
Available
[
IDFetch
]
.
empty
(
)
||
!
Available
[
IDOther
]
.
empty
(
)
)
;
if
(
CurInstKind
==
IDAlu
&&
!
Available
[
IDFetch
]
.
empty
(
)
)
{
float
ALUFetchRationEstimate
=
(
AluInstCount
+
AvailablesAluCount
(
)
+
Pending
[
IDAlu
]
.
size
(
)
)
/
(
FetchInstCount
+
Available
[
IDFetch
]
.
size
(
)
)
;
if
(
ALUFetchRationEstimate
==
0
)
{
AllowSwitchFromAlu
=
true
;
}
else
{
unsigned
NeededWF
=
62.5f
/
ALUFetchRationEstimate
;
LLVM_DEBUG
(
dbgs
(
)
<<
NeededWF
<<
" approx. Wavefronts Required\n"
)
;
unsigned
NearRegisterRequirement
=
2
*
Available
[
IDFetch
]
.
size
(
)
;
if
(
NeededWF
>
getWFCountLimitedByGPR
(
NearRegisterRequirement
)
)
AllowSwitchFromAlu
=
true
;
}
}
if
(
!
SU
&&
(
(
AllowSwitchToAlu
&&
CurInstKind
!=
IDAlu
)
||
(
!
AllowSwitchFromAlu
&&
CurInstKind
==
IDAlu
)
)
)
{
SU
=
pickAlu
(
)
;
if
(
!
SU
&&
!
PhysicalRegCopy
.
empty
(
)
)
{
SU
=
PhysicalRegCopy
.
front
(
)
;
PhysicalRegCopy
.
erase
(
PhysicalRegCopy
.
begin
(
)
)
;
}
if
(
SU
)
{
if
(
CurEmitted
>=
InstKindLimit
[
IDAlu
]
)
CurEmitted
=
0
;
NextInstKind
=
IDAlu
;
}
}
if
(
!
SU
)
{
SU
=
pickOther
(
IDFetch
)
;
if
(
SU
)
NextInstKind
=
IDFetch
;
}
if
(
!
SU
)
{
SU
=
pickOther
(
IDOther
)
;
if
(
SU
)
NextInstKind
=
IDOther
;
}
LLVM_DEBUG
(
if
(
SU
)
{
dbgs
(
)
<<
" ** Pick node **\n"
;
DAG
->
dumpNode
(
*
SU
)
;
}
else
{
dbgs
(
)
<<
"NO NODE \n"
;
for
(
const
SUnit
&
S
:
DAG
->
SUnits
)
if
(
!
S
.
isScheduled
)
DAG
->
dumpNode
(
S
)
;
}
</s>

Pick the next node to schedule , or return NULL .


<s> int avr_ret_register ( ) { return 24 ; } </s>

Returns register number for function return value .


<s> SDValue SITargetLowering :: PerformDAGCombine ( SDNode * N , DAGCombinerInfo & DCI ) const { SelectionDAG & DAG = DCI . DAG ; SDLoc DL ( N ) ; EVT VT = N -> getValueType ( 0 ) ; switch ( N -> getOpcode ( ) ) { default : return AMDGPUTargetLowering :: PerformDAGCombine ( N , DCI ) ; case ISD :: SELECT_CC : { ConstantSDNode * True , * False ; if ( ( True = dyn_cast < ConstantSDNode > ( N -> getOperand ( 2 ) ) ) && ( False = dyn_cast < ConstantSDNode > ( N -> getOperand ( 3 ) ) ) && True -> isAllOnesValue ( ) && False -> isNullValue ( ) && VT == MVT :: i1 ) { return DAG . getNode ( ISD :: SETCC , DL , VT , N -> getOperand ( 0 ) , N -> getOperand ( 1 ) , N -> getOperand ( 4 ) ) ; } break ; } case ISD :: SETCC : { SDValue Arg0 = N -> getOperand ( 0 ) ; SDValue Arg1 = N -> getOperand ( 1 ) ; SDValue CC = N -> getOperand ( 2 ) ; ConstantSDNode * C = nullptr ; ISD :: CondCode CCOp = dyn_cast < CondCodeSDNode > ( CC ) -> get ( ) ; if ( VT == MVT :: i1 && Arg0 . getOpcode ( ) == ISD :: SIGN_EXTEND && Arg0 . getOperand ( 0 ) . getValueType ( ) == MVT :: i1 && ( C = dyn_cast < ConstantSDNode > ( Arg1 ) ) && C -> isNullValue ( ) && CCOp == ISD :: SETNE ) { return SimplifySetCC ( VT , Arg0 . getOperand ( 0 ) , DAG . getConstant ( 0 , MVT :: i1 ) , CCOp , true , DCI , DL ) ; } break ; } case AMDGPUISD :: CVT_F32_UBYTE0 : case AMDGPUISD :: CVT_F32_UBYTE1 : case AMDGPUISD :: CVT_F32_UBYTE2 : case AMDGPUISD :: CVT_F32_UBYTE3 : { unsigned Offset = N -> getOpcode ( ) - AMDGPUISD :: CVT_F32_UBYTE0 ; SDValue Src = N -> getOperand ( 0 ) ; APInt Demanded = APInt :: getBitsSet ( 32 , 8 * Offset , 8 * Offset + 8 ) ; APInt KnownZero , KnownOne ; TargetLowering :: TargetLoweringOpt TLO ( DAG , ! DCI . isBeforeLegalize ( ) , ! DCI . isBeforeLegalizeOps ( ) ) ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; if ( TLO . ShrinkDemandedConstant ( Src , Demanded ) || TLI . SimplifyDemandedBits ( Src , Demanded , KnownZero , KnownOne , TLO ) ) { DCI . CommitTargetLoweringOpt ( TLO ) ; } break ; } case ISD :: UINT_TO_FP : { return performUCharToFloatCombine ( N , DCI ) ; } } return AMDGPUTargetLowering :: PerformDAGCombine ( N , DCI ) ; } </s>

This method will be invoked for all target nodes and for any target-independent nodes that the target has registered with invoke it for .


<s> rtx microblaze_return_addr ( int count , rtx frame ATTRIBUTE_UNUSED ) { if ( count != 0 ) return NULL_RTX ; return get_hard_reg_initial_val ( Pmode , MB_ABI_SUB_RETURN_ADDR_REGNUM ) ; } </s>

Return an RTX indicating where the return address to the calling function can be found .


<s> void StackVreg :: print ( const Stack & S ) const { S . printElement ( dbgs ( ) , * this ) ; } </s>

print - Print a debug representation of the operand to the given stream .


<s> void R600InstrInfo :: reserveIndirectRegisters ( BitVector & Reserved , const MachineFunction & MF , const R600RegisterInfo & TRI ) const { const R600Subtarget & ST = MF . getSubtarget < R600Subtarget > ( ) ; const R600FrameLowering * TFL = ST . getFrameLowering ( ) ; unsigned StackWidth = TFL -> getStackWidth ( MF ) ; int End = getIndirectIndexEnd ( MF ) ; if ( End == - 1 ) return ; for ( int Index = getIndirectIndexBegin ( MF ) ; Index <= End ; ++ Index ) { for ( unsigned Chan = 0 ; Chan < StackWidth ; ++ Chan ) { unsigned Reg = R600 :: R600_TReg32RegClass . getRegister ( ( 4 * Index ) + Chan ) ; TRI . reserveRegisterTuples ( Reserved , Reg ) ; } } } </s>

Reserve the registers that may be accessed using indirect addressing .


<s> static void mips_ls2_variable_issue ( rtx_insn * insn ) { if ( mips_ls2 . alu1_turn_p ) { if ( cpu_unit_reservation_p ( curr_state , mips_ls2 . alu1_core_unit_code ) ) mips_ls2 . alu1_turn_p = false ; } else { if ( cpu_unit_reservation_p ( curr_state , mips_ls2 . alu2_core_unit_code ) ) mips_ls2 . alu1_turn_p = true ; } if ( mips_ls2 . falu1_turn_p ) { if ( cpu_unit_reservation_p ( curr_state , mips_ls2 . falu1_core_unit_code ) ) mips_ls2 . falu1_turn_p = false ; } else { if ( cpu_unit_reservation_p ( curr_state , mips_ls2 . falu2_core_unit_code ) ) mips_ls2 . falu1_turn_p = true ; } if ( recog_memoized ( insn ) >= 0 ) mips_ls2 . cycle_has_multi_p |= ( get_attr_type ( insn ) == TYPE_MULTI ) ; } </s>

Update round-robin counters for ALU1/2 and FALU1/2 .


<s> unsigned SIRegisterInfo :: reservedPrivateSegmentBufferReg ( const MachineFunction & MF ) const { const AMDGPUSubtarget & ST = MF . getSubtarget < AMDGPUSubtarget > ( ) ; if ( ST . hasSGPRInitBug ( ) ) { unsigned BaseIdx = AMDGPUSubtarget :: FIXED_SGPR_COUNT_FOR_INIT_BUG - 4 - 4 ; if ( ST . isXNACKEnabled ( ) ) BaseIdx -= 4 ; unsigned BaseReg ( AMDGPU :: SGPR_32RegClass . getRegister ( BaseIdx ) ) ; return getMatchingSuperReg ( BaseReg , AMDGPU :: sub0 , & AMDGPU :: SReg_128RegClass ) ; } if ( ST . getGeneration ( ) >= AMDGPUSubtarget :: VOLCANIC_ISLANDS ) { return AMDGPU :: SGPR92_SGPR93_SGPR94_SGPR95 ; } return AMDGPU :: SGPR96_SGPR97_SGPR98_SGPR99 ; } </s>

Return the end register initially reserved for the scratch buffer in case spilling is needed .


<s> void riscv_expand_conditional_branch ( rtx label , rtx_code code , rtx op0 , rtx op1 ) { if ( FLOAT_MODE_P ( GET_MODE ( op1 ) ) ) riscv_emit_float_compare ( & code , & op0 , & op1 ) ; else riscv_emit_int_compare ( & code , & op0 , & op1 ) ; rtx condition = gen_rtx_fmt_ee ( code , VOIDmode , op0 , op1 ) ; emit_jump_insn ( gen_condjump ( condition , label ) ) ; } </s>

Jump to LABEL if ( CODE OP0 OP1 ) holds .


<s> unsigned getMinPrefetchStride ( ) { return 2048 ; } </s>

Some HW prefetchers can handle accesses up to a certain constant stride .


<s> static rtx m32r_libcall_value ( machine_mode mode , const_rtx fun ATTRIBUTE_UNUSED ) { return gen_rtx_REG ( mode , 0 ) ; } </s>

Worker function for TARGET_LIBCALL_VALUE .


<s> bool isImm ( ) const { return Kind == k_Immediate ; } </s>


<s> const MCFixup * RISCVMCExpr :: getPCRelHiFixup ( ) const { MCValue AUIPCLoc ; if ( ! getSubExpr ( ) -> evaluateAsRelocatable ( AUIPCLoc , nullptr , nullptr ) ) return nullptr ; const MCSymbolRefExpr * AUIPCSRE = AUIPCLoc . getSymA ( ) ; if ( ! AUIPCSRE ) return nullptr ; const auto * DF = dyn_cast_or_null < MCDataFragment > ( AUIPCSRE -> findAssociatedFragment ( ) ) ; if ( ! DF ) return nullptr ; const MCSymbol * AUIPCSymbol = & AUIPCSRE -> getSymbol ( ) ; for ( const MCFixup & F : DF -> getFixups ( ) ) { if ( F . getOffset ( ) != AUIPCSymbol -> getOffset ( ) ) continue ; switch ( ( unsigned ) F . getKind ( ) ) { default : continue ; case RISCV :: fixup_riscv_pcrel_hi20 : return & F ; } } return nullptr ; } </s>

Get the corresponding PC-relative HI fixup that a VK_RISCV_PCREL_LO points to , and optionally the fragment containing it .


<s> rtx_insn * mips_emit_move ( rtx dest , rtx src ) { return ( can_create_pseudo_p ( ) ? emit_move_insn ( dest , src ) : emit_move_insn_1 ( dest , src ) ) ; } </s>

Emit a move from SRC to DEST . Assume that the move expanders can handle all moves if ! can_create_pseudo_p ( ) . The distinction is important because , unlike emit_move_insn , the move expanders know how to force Pmode objects into the constant pool even when the constant pool address is not itself legitimate .


<s> bool X86IndirectThunks :: runOnMachineFunction ( MachineFunction & MF ) { LLVM_DEBUG ( dbgs ( ) << getPassName ( ) << '\n' ) ; auto & MMI = getAnalysis < MachineModuleInfoWrapperPass > ( ) . getMMI ( ) ; return runTIs ( MMI , MF , TIs ) ; } </s>

runOnMachineFunction - Emit the function body .


<s> SDNode * X86DAGToDAGISel :: getGlobalBaseReg ( ) { unsigned GlobalBaseReg = getInstrInfo ( ) -> getGlobalBaseReg ( MF ) ; return CurDAG -> getRegister ( GlobalBaseReg , getTargetLowering ( ) -> getPointerTy ( ) ) . getNode ( ) ; } </s>

getGlobalBaseReg - Return a virtual register initialized with the the global base register value .


<s>
bool
NVPTXAsmPrinter
::
doInitialization
(
Module
&
M
)
{
StringRef
TT
=
TM
.
getTargetTriple
(
)
;
StringRef
CPU
=
TM
.
getTargetCPU
(
)
;
StringRef
FS
=
TM
.
getTargetFeatureString
(
)
;
const
NVPTXTargetMachine
&
NTM
=
static_cast
<
const
NVPTXTargetMachine
&
>
(
TM
)
;
const
NVPTXSubtarget
STI
(
TT
,
CPU
,
FS
,
NTM
)
;
SmallString
<
128
>
Str1
;
raw_svector_ostream
OS1
(
Str1
)
;
MMI
=
getAnalysisIfAvailable
<
MachineModuleInfo
>
(
)
;
MMI
->
AnalyzeModule
(
M
)
;
const_cast
<
TargetLoweringObjectFile
&
>
(
getObjFileLowering
(
)
)
.
Initialize
(
OutContext
,
TM
)
;
Mang
=
new
Mangler
(
TM
.
getDataLayout
(
)
)
;
emitHeader
(
M
,
OS1
,
STI
)
;
OutStreamer
->
EmitRawText
(
OS1
.
str
(
)
)
;
if
(
!
M
.
getModuleInlineAsm
(
)
.
empty
(
)
)
{
OutStreamer
->
AddComment
(
"Start of file scope inline assembly"
)
;
OutStreamer
->
AddBlankLine
(
)
;
OutStreamer
->
EmitRawText
(
StringRef
(
M
.
getModuleInlineAsm
(
)
)
)
;
OutStreamer
->
AddBlankLine
(
)
;
OutStreamer
->
AddComment
(
"End of file scope inline assembly"
)
;
OutStreamer
->
AddBlankLine
(
)
;
}
if
(
Triple
(
TM
.
getTargetTriple
(
)
)
.
getOS
(
)
!=
Triple
::
NVCL
)
recordAndEmitFilenames
(
M
)
;
GlobalsEmitted
=
false
;
return
false
;
}
</s>

Set up the AsmPrinter when we are working on a new module .

NVPTX
NVPTX
NVPTX
NVPTX
NVPTX
128
"Start of file scope inline assembly"
"End of file scope inline assembly"


<s> bool ARMBaseInstrInfo :: isSchedulingBoundary ( const MachineInstr & MI , const MachineBasicBlock * MBB , const MachineFunction & MF ) const { if ( MI . isDebugInstr ( ) ) return false ; if ( MI . isTerminator ( ) || MI . isPosition ( ) ) return true ; if ( MI . getOpcode ( ) == TargetOpcode :: INLINEASM_BR ) return true ; MachineBasicBlock :: const_iterator I = MI ; while ( ++ I != MBB -> end ( ) && I -> isDebugInstr ( ) ) ; if ( I != MBB -> end ( ) && I -> getOpcode ( ) == ARM :: t2IT ) return true ; if ( ! MI . isCall ( ) && MI . definesRegister ( ARM :: SP ) ) return true ; return false ; } </s>

isSchedulingBoundary - Overrides the isSchedulingBoundary from Codegen/TargetInstrInfo.cpp to make it capable of identifying ENDBR intructions and prevent it from being re-scheduled .


<s> static inline bool has_func_attr ( const_tree decl , const char * func_attr ) { if ( decl == NULL_TREE ) decl = current_function_decl ; return lookup_attribute ( func_attr , DECL_ATTRIBUTES ( decl ) ) != NULL_TREE ; } </s>

Returns true if the provided function has the specified attribute .


<s> void Thumb2InstrInfo :: loadRegFromStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned DestReg , int FI , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { if ( RC == ARM :: GPRRegisterClass || RC == ARM :: tGPRRegisterClass || RC == ARM :: tcGPRRegisterClass || RC == ARM :: rGPRRegisterClass ) { DebugLoc DL ; if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; MachineFrameInfo & MFI = * MF . getFrameInfo ( ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( PseudoSourceValue :: getFixedStack ( FI ) , MachineMemOperand :: MOLoad , 0 , MFI . getObjectSize ( FI ) , MFI . getObjectAlignment ( FI ) ) ; AddDefaultPred ( BuildMI ( MBB , I , DL , get ( ARM :: t2LDRi12 ) , DestReg ) . addFrameIndex ( FI ) . addImm ( 0 ) . addMemOperand ( MMO ) ) ; return ; } ARMBaseInstrInfo :: loadRegFromStackSlot ( MBB , I , DestReg , FI , RC , TRI ) ; } </s>

Load the specified register of the given register class from the specified stack frame index .

ARM ARM::GPRRegisterClass ARM::tGPRRegisterClass ARM::tcGPRRegisterClass ARM::rGPRRegisterClass 0 ARM::t2LDRi12 0 ARM


<s> static rtx pro_epilogue_adjust_stack ( rtx dest , rtx src , rtx offset , int style , bool set_cfa ) { struct machine_function * m = cfun -> machine ; rtx insn ; bool add_frame_related_expr = false ; if ( Pmode == SImode ) insn = gen_pro_epilogue_adjust_stack_si_add ( dest , src , offset ) ; else if ( x86_64_immediate_operand ( offset , DImode ) ) insn = gen_pro_epilogue_adjust_stack_di_add ( dest , src , offset ) ; else { rtx tmp ; if ( style ) tmp = gen_rtx_REG ( DImode , R11_REG ) ; else { gcc_assert ( src != hard_frame_pointer_rtx && dest != hard_frame_pointer_rtx ) ; tmp = hard_frame_pointer_rtx ; } insn = emit_insn ( gen_rtx_SET ( tmp , offset ) ) ; if ( style < 0 ) add_frame_related_expr = true ; insn = gen_pro_epilogue_adjust_stack_di_add ( dest , src , tmp ) ; } insn = emit_insn ( insn ) ; if ( style >= 0 ) ix86_add_queued_cfa_restore_notes ( insn ) ; if ( set_cfa ) { rtx r ; gcc_assert ( m -> fs . cfa_reg == src ) ; m -> fs . cfa_offset += INTVAL ( offset ) ; m -> fs . cfa_reg = dest ; r = gen_rtx_PLUS ( Pmode , src , offset ) ; r = gen_rtx_SET ( dest , r ) ; add_reg_note ( insn , REG_CFA_ADJUST_CFA , r ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; } else if ( style < 0 ) { RTX_FRAME_RELATED_P ( insn ) = 1 ; if ( add_frame_related_expr ) { rtx r = gen_rtx_PLUS ( Pmode , src , offset ) ; r = gen_rtx_SET ( dest , r ) ; add_reg_note ( insn , REG_FRAME_RELATED_EXPR , r ) ; } } if ( dest == stack_pointer_rtx ) { HOST_WIDE_INT ooffset = m -> fs . sp_offset ; bool valid = m -> fs . sp_valid ; bool realigned = m -> fs . sp_realigned ; if ( src == hard_frame_pointer_rtx ) { valid = m -> fs . fp_valid ; realigned = false ; ooffset = m -> fs . fp_offset ; } else if ( src == crtl -> drap_reg ) { valid = m -> fs . drap_valid ; realigned = false ; ooffset = 0 ; } else { gcc_checking_assert ( src == stack_pointer_rtx || offset == const0_rtx ) ; } m -> fs . sp_offset = ooffset - INTVAL ( offset ) ; m -> fs . sp_valid = valid ; m -> fs . sp_realigned = realigned ; } return insn ; } </s>

Expand prologue or epilogue stack adjustment . The pattern exist to put a dependency on all ebp-based memory accesses . STYLE should be negative if instructions should be marked as frame related , zero if % r11 register is live and can not be freely used and positive otherwise .


"expression value must be representable in 32 bits"

Allow a target to add special case operand matching for things that tblgen doesn't/ca n't handle effectively .


<s> void PPCPassConfig :: addPreRegAlloc ( ) { initializePPCVSXFMAMutatePass ( * PassRegistry :: getPassRegistry ( ) ) ; insertPass ( VSXFMAMutateEarly ? & RegisterCoalescerID : & MachineSchedulerID , & PPCVSXFMAMutateID ) ; if ( getPPCTargetMachine ( ) . getRelocationModel ( ) == Reloc :: PIC_ ) addPass ( createPPCTLSDynamicCallPass ( ) ) ; if ( EnableExtraTOCRegDeps ) addPass ( createPPCTOCRegDepsPass ( ) ) ; } </s>

This method may be implemented by targets that want to run passes immediately before register allocation .


<s> void altivec_expand_vec_perm_le ( rtx operands [ 4 ] ) { rtx notx , iorx , unspec ; rtx target = operands [ 0 ] ; rtx op0 = operands [ 1 ] ; rtx op1 = operands [ 2 ] ; rtx sel = operands [ 3 ] ; rtx tmp = target ; rtx norreg = gen_reg_rtx ( V16QImode ) ; machine_mode mode = GET_MODE ( target ) ; if ( ! REG_P ( op0 ) ) op0 = force_reg ( mode , op0 ) ; if ( ! REG_P ( op1 ) ) op1 = force_reg ( mode , op1 ) ; if ( ! REG_P ( sel ) ) sel = force_reg ( V16QImode , sel ) ; if ( ! REG_P ( target ) ) tmp = gen_reg_rtx ( mode ) ; if ( TARGET_P9_VECTOR ) { unspec = gen_rtx_UNSPEC ( mode , gen_rtvec ( 3 , op1 , op0 , sel ) , UNSPEC_VPERMR ) ; } else { notx = gen_rtx_NOT ( V16QImode , sel ) ; iorx = ( TARGET_P8_VECTOR ? gen_rtx_IOR ( V16QImode , notx , notx ) : gen_rtx_AND ( V16QImode , notx , notx ) ) ; emit_insn ( gen_rtx_SET ( norreg , iorx ) ) ; unspec = gen_rtx_UNSPEC ( mode , gen_rtvec ( 3 , op1 , op0 , norreg ) , UNSPEC_VPERM ) ; } if ( ! REG_P ( target ) ) { emit_move_insn ( tmp , unspec ) ; unspec = tmp ; } emit_move_insn ( target , unspec ) ; } </s>

Similarly to altivec_expand_vec_perm_const_le , we must adjust the permute control vector . But here it 's not a constant , so we must generate a vector NAND or NOR to do the adjustment .


<s>
void
SIScheduleBlock
::
addPred
(
SIScheduleBlock
*
Pred
)
{
unsigned
PredID
=
Pred
->
getID
(
)
;
for
(
SIScheduleBlock
*
P
:
Preds
)
{
if
(
PredID
==
P
->
getID
(
)
)
return
;
}
Preds
.
push_back
(
Pred
)
;
for
(
SIScheduleBlock
*
S
:
Succs
)
{
if
(
PredID
==
S
->
getID
(
)
)
assert
(
!
"Loop in the Block Graph!\n"
)
;
}
}
</s>

Adds the specified edge as a pred of the current node if not already .

AMDGPU
SI
SI
SI
SI
"Loop in the Block Graph!\n"


<s> bool PPCInstrInfo :: analyzeCompare ( const MachineInstr & MI , unsigned & SrcReg , unsigned & SrcReg2 , int & Mask , int & Value ) const { unsigned Opc = MI . getOpcode ( ) ; switch ( Opc ) { default : return false ; case PPC :: CMPWI : case PPC :: CMPLWI : case PPC :: CMPDI : case PPC :: CMPLDI : SrcReg = MI . getOperand ( 1 ) . getReg ( ) ; SrcReg2 = 0 ; Value = MI . getOperand ( 2 ) . getImm ( ) ; Mask = 0xFFFF ; return true ; case PPC :: CMPW : case PPC :: CMPLW : case PPC :: CMPD : case PPC :: CMPLD : case PPC :: FCMPUS : case PPC :: FCMPUD : SrcReg = MI . getOperand ( 1 ) . getReg ( ) ; SrcReg2 = MI . getOperand ( 2 ) . getReg ( ) ; Value = 0 ; Mask = 0 ; return true ; } } </s>

analyzeCompare - For a comparison instruction , return the source registers in SrcReg and SrcReg2 if having two register operands , and the value it compares against in CmpValue .


<s> int fp_mov_p ( rtx op ) { if ( GET_CODE ( op ) == CONST_DOUBLE ) { REAL_VALUE_TYPE r ; long i ; REAL_VALUE_FROM_CONST_DOUBLE ( r , op ) ; REAL_VALUE_TO_TARGET_SINGLE ( r , i ) ; return SPARC_SIMM13_P ( i ) ; } return 0 ; } </s>

Nonzero if OP is a floating point constant which can be loaded into an integer register using a single mov instruction .


<s> static void ix86_emit_mode_set ( int entity , int mode , int prev_mode ATTRIBUTE_UNUSED , HARD_REG_SET regs_live ATTRIBUTE_UNUSED ) { switch ( entity ) { case X86_DIRFLAG : if ( mode == X86_DIRFLAG_RESET ) emit_insn ( gen_cld ( ) ) ; break ; case AVX_U128 : if ( mode == AVX_U128_CLEAN ) emit_insn ( gen_avx_vzeroupper ( ) ) ; break ; case I387_TRUNC : case I387_FLOOR : case I387_CEIL : if ( mode != I387_CW_ANY && mode != I387_CW_UNINITIALIZED ) emit_i387_cw_initialization ( mode ) ; break ; default : gcc_unreachable ( ) ; } } </s>

Generate one or more insns to set ENTITY to MODE . HARD_REG_LIVE is the set of hard registers live at the point where the insn ( s ) are to be inserted .


<s> bool PPCFrameLowering :: spillCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo * TRI ) const { if ( ! Subtarget . isSVR4ABI ( ) ) return false ; MachineFunction * MF = MBB . getParent ( ) ; const PPCInstrInfo & TII = * Subtarget . getInstrInfo ( ) ; DebugLoc DL ; bool CRSpilled = false ; MachineInstrBuilder CRMIB ; for ( unsigned i = 0 , e = CSI . size ( ) ; i != e ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; if ( Reg == PPC :: VRSAVE && ! Subtarget . isDarwinABI ( ) ) continue ; bool IsCRField = PPC :: CR2 <= Reg && Reg <= PPC :: CR4 ; const MachineRegisterInfo & MRI = MF -> getRegInfo ( ) ; bool IsLiveIn = MRI . isLiveIn ( Reg ) ; if ( ! IsLiveIn ) MBB . addLiveIn ( Reg ) ; if ( CRSpilled && IsCRField ) { CRMIB . addReg ( Reg , RegState :: ImplicitKill ) ; continue ; } if ( IsCRField ) { PPCFunctionInfo * FuncInfo = MF -> getInfo < PPCFunctionInfo > ( ) ; if ( Subtarget . isPPC64 ( ) ) { FuncInfo -> addMustSaveCR ( Reg ) ; } else { CRSpilled = true ; FuncInfo -> setSpillsCR ( ) ; CRMIB = BuildMI ( * MF , DL , TII . get ( PPC :: MFCR ) , PPC :: R12 ) . addReg ( Reg , RegState :: ImplicitKill ) ; MBB . insert ( MI , CRMIB ) ; MBB . insert ( MI , addFrameReference ( BuildMI ( * MF , DL , TII . get ( PPC :: STW ) ) . addReg ( PPC :: R12 , getKillRegState ( true ) ) , CSI [ i ] . getFrameIdx ( ) ) ) ; } } else { const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ; TII . storeRegToStackSlot ( MBB , MI , Reg , ! IsLiveIn , CSI [ i ] . getFrameIdx ( ) , RC , TRI ) ; } } return true ; } </s>

spillCalleeSavedRegisters - Issues instruction ( s ) to spill all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of store instructions via storeRegToStackSlot ( ) .


<s> void GCNPassConfig :: addPreEmitPass ( ) { addPass ( createSIMemoryLegalizerPass ( ) ) ; addPass ( createSIInsertWaitcntsPass ( ) ) ; addPass ( createSIShrinkInstructionsPass ( ) ) ; addPass ( createSIModeRegisterPass ( ) ) ; if ( getOptLevel ( ) > CodeGenOpt :: None ) addPass ( & SIInsertHardClausesID ) ; addPass ( & SIRemoveShortExecBranchesID ) ; addPass ( & SIInsertSkipsPassID ) ; addPass ( & SIPreEmitPeepholeID ) ; addPass ( & PostRAHazardRecognizerID ) ; addPass ( & BranchRelaxationPassID ) ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s> void AArch64InstrInfo :: suppressLdStPair ( MachineInstr & MI ) { if ( MI . memoperands_empty ( ) ) return ; ( * MI . memoperands_begin ( ) ) -> setFlags ( MOSuppressPair ) ; } </s>

Hint that pairing the given load or store is unprofitable .


<s>
static
uint8_t
name
(
struct
InternalInstruction
*
insn
,
\
OperandType
type
,
\
uint8_t
index
,
\
uint8_t
*
valid
)
{
\
*
valid
=
1
;
\
switch
(
type
)
{
\
default
:
\
debug
(
"Unhandled register type"
)
;
\
*
valid
=
0
;
\
return
0
;
\
case
TYPE_Rv
:
\
return
base
+
index
;
\
case
TYPE_R8
:
\
if
(
insn
->
rexPrefix
&&
\
index
>=
4
&&
index
<=
7
)
{
\
return
prefix
##
_SPL
+
(
index
4
)
;
\
}
else
{
\
return
prefix
##
_AL
+
index
;
\
}
\
case
TYPE_R16
:
\
return
prefix
##
_AX
+
index
;
\
case
TYPE_R32
:
\
return
prefix
##
_EAX
+
index
;
\
case
TYPE_R64
:
\
return
prefix
##
_RAX
+
index
;
\
case
TYPE_XMM512
:
\
return
prefix
##
_ZMM0
+
index
;
\
case
TYPE_XMM256
:
\
return
prefix
##
_YMM0
+
index
;
\
case
TYPE_XMM128
:
\
case
TYPE_XMM64
:
\
case
TYPE_XMM32
:
\
return
prefix
##
_XMM0
+
index
;
\
case
TYPE_VK1
:
\
case
TYPE_VK2
:
\
case
TYPE_VK4
:
\
case
TYPE_VK8
:
\
case
TYPE_VK16
:
\
case
TYPE_VK32
:
\
case
TYPE_VK64
:
\
if
(
index
>
7
)
\
*
valid
=
0
;
\
return
prefix
##
_K0
+
index
;
\
case
TYPE_MM64
:
\
return
prefix
##
_MM0
+
(
index
&
0x7
)
;
\
case
TYPE_SEGMENTREG
:
\
if
(
index
>
5
)
\
*
valid
=
0
;
\
return
prefix
##
_ES
+
index
;
\
case
TYPE_DEBUGREG
:
\
return
prefix
##
_DR0
+
index
;
\
case
TYPE_CONTROLREG
:
\
return
prefix
##
_CR0
+
index
;
\
}
\
}
</s>

Gets the name of the pass we are mixed into .


<s> bool ARCTargetLowering :: CanLowerReturn ( CallingConv :: ID CallConv , MachineFunction & MF , bool IsVarArg , const SmallVectorImpl < ISD :: OutputArg > & Outs , LLVMContext & Context ) const { SmallVector < CCValAssign , 16 > RVLocs ; CCState CCInfo ( CallConv , IsVarArg , MF , RVLocs , Context ) ; if ( ! CCInfo . CheckReturn ( Outs , RetCC_ARC ) ) return false ; if ( CCInfo . getNextStackOffset ( ) != 0 && IsVarArg ) return false ; return true ; } </s>

This hook should be implemented to check whether the return values described by the Outs array can fit into the return registers .


<s> int c4x_immed_float_p ( rtx op ) { long convval [ 2 ] ; int exponent ; REAL_VALUE_TYPE r ; REAL_VALUE_FROM_CONST_DOUBLE ( r , op ) ; if ( GET_MODE ( op ) == HFmode ) REAL_VALUE_TO_TARGET_DOUBLE ( r , convval ) ; else { REAL_VALUE_TO_TARGET_SINGLE ( r , convval [ 0 ] ) ; convval [ 1 ] = 0 ; } exponent = ( ( ( convval [ 0 ] >> 24 ) & 0xff ) ^ 0x80 ) - 0x80 ; if ( exponent == - 128 ) return 1 ; if ( ( convval [ 0 ] & 0x00000fff ) != 0 || convval [ 1 ] != 0 ) return 0 ; return ( exponent <= 7 ) && ( exponent >= - 7 ) ; } </s>

Return nonzero if the floating point operand will fit in the immediate field .


<s>
void
WebAssemblyAsmPrinter
::
EmitInstruction
(
const
MachineInstr
*
MI
)
{
DEBUG
(
dbgs
(
)
<<
"EmitInstruction: "
<<
*
MI
<<
'\n'
)
;
switch
(
MI
->
getOpcode
(
)
)
{
case
WebAssembly
::
ARGUMENT_I32
:
case
WebAssembly
::
ARGUMENT_I64
:
case
WebAssembly
::
ARGUMENT_F32
:
case
WebAssembly
::
ARGUMENT_F64
:
case
WebAssembly
::
ARGUMENT_v16i8
:
case
WebAssembly
::
ARGUMENT_v8i16
:
case
WebAssembly
::
ARGUMENT_v4i32
:
case
WebAssembly
::
ARGUMENT_v4f32
:
break
;
case
WebAssembly
::
FALLTHROUGH_RETURN_I32
:
case
WebAssembly
::
FALLTHROUGH_RETURN_I64
:
case
WebAssembly
::
FALLTHROUGH_RETURN_F32
:
case
WebAssembly
::
FALLTHROUGH_RETURN_F64
:
case
WebAssembly
::
FALLTHROUGH_RETURN_v16i8
:
case
WebAssembly
::
FALLTHROUGH_RETURN_v8i16
:
case
WebAssembly
::
FALLTHROUGH_RETURN_v4i32
:
case
WebAssembly
::
FALLTHROUGH_RETURN_v4f32
:
{
assert
(
MFI
->
isVRegStackified
(
MI
->
getOperand
(
0
)
.
getReg
(
)
)
)
;
if
(
isVerbose
(
)
)
{
OutStreamer
->
AddComment
(
"fallthrough-return: $pop"
+
utostr
(
MFI
->
getWARegStackId
(
MFI
->
getWAReg
(
MI
->
getOperand
(
0
)
.
getReg
(
)
)
)
)
)
;
OutStreamer
->
AddBlankLine
(
)
;
}
break
;
}
case
WebAssembly
::
FALLTHROUGH_RETURN_VOID
:
if
(
isVerbose
(
)
)
{
OutStreamer
->
AddComment
(
"fallthrough-return"
)
;
OutStreamer
->
AddBlankLine
(
)
;
}
break
;
default
:
{
WebAssemblyMCInstLower
MCInstLowering
(
OutContext
,
*
this
)
;
MCInst
TmpInst
;
MCInstLowering
.
Lower
(
MI
,
TmpInst
)
;
EmitToStreamer
(
*
OutStreamer
,
TmpInst
)
;
break
;
}
}
}
</s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s> static void sparc_init_libfuncs ( void ) { if ( TARGET_ARCH32 ) { set_optab_libfunc ( smul_optab , SImode , "*.umul" ) ; set_optab_libfunc ( sdiv_optab , SImode , "*.div" ) ; set_optab_libfunc ( udiv_optab , SImode , "*.udiv" ) ; set_optab_libfunc ( smod_optab , SImode , "*.rem" ) ; set_optab_libfunc ( umod_optab , SImode , "*.urem" ) ; set_optab_libfunc ( add_optab , TFmode , "_Q_add" ) ; set_optab_libfunc ( sub_optab , TFmode , "_Q_sub" ) ; set_optab_libfunc ( neg_optab , TFmode , "_Q_neg" ) ; set_optab_libfunc ( smul_optab , TFmode , "_Q_mul" ) ; set_optab_libfunc ( sdiv_optab , TFmode , "_Q_div" ) ; if ( TARGET_FPU ) set_optab_libfunc ( sqrt_optab , TFmode , "_Q_sqrt" ) ; set_optab_libfunc ( eq_optab , TFmode , "_Q_feq" ) ; set_optab_libfunc ( ne_optab , TFmode , "_Q_fne" ) ; set_optab_libfunc ( gt_optab , TFmode , "_Q_fgt" ) ; set_optab_libfunc ( ge_optab , TFmode , "_Q_fge" ) ; set_optab_libfunc ( lt_optab , TFmode , "_Q_flt" ) ; set_optab_libfunc ( le_optab , TFmode , "_Q_fle" ) ; set_conv_libfunc ( sext_optab , TFmode , SFmode , "_Q_stoq" ) ; set_conv_libfunc ( sext_optab , TFmode , DFmode , "_Q_dtoq" ) ; set_conv_libfunc ( trunc_optab , SFmode , TFmode , "_Q_qtos" ) ; set_conv_libfunc ( trunc_optab , DFmode , TFmode , "_Q_qtod" ) ; set_conv_libfunc ( sfix_optab , SImode , TFmode , "_Q_qtoi" ) ; set_conv_libfunc ( ufix_optab , SImode , TFmode , "_Q_qtou" ) ; set_conv_libfunc ( sfloat_optab , TFmode , SImode , "_Q_itoq" ) ; if ( DITF_CONVERSION_LIBFUNCS ) { set_conv_libfunc ( sfix_optab , DImode , TFmode , "_Q_qtoll" ) ; set_conv_libfunc ( ufix_optab , DImode , TFmode , "_Q_qtoull" ) ; set_conv_libfunc ( sfloat_optab , TFmode , DImode , "_Q_lltoq" ) ; } if ( SUN_CONVERSION_LIBFUNCS ) { set_conv_libfunc ( sfix_optab , DImode , SFmode , "__ftoll" ) ; set_conv_libfunc ( ufix_optab , DImode , SFmode , "__ftoull" ) ; set_conv_libfunc ( sfix_optab , DImode , DFmode , "__dtoll" ) ; set_conv_libfunc ( ufix_optab , DImode , DFmode , "__dtoull" ) ; } } if ( TARGET_ARCH64 ) { set_optab_libfunc ( smul_optab , SImode , 0 ) ; set_optab_libfunc ( sdiv_optab , SImode , 0 ) ; set_optab_libfunc ( udiv_optab , SImode , 0 ) ; set_optab_libfunc ( smod_optab , SImode , 0 ) ; set_optab_libfunc ( umod_optab , SImode , 0 ) ; if ( SUN_INTEGER_MULTIPLY_64 ) { set_optab_libfunc ( smul_optab , DImode , "__mul64" ) ; set_optab_libfunc ( sdiv_optab , DImode , "__div64" ) ; set_optab_libfunc ( udiv_optab , DImode , "__udiv64" ) ; set_optab_libfunc ( smod_optab , DImode , "__rem64" ) ; set_optab_libfunc ( umod_optab , DImode , "__urem64" ) ; } if ( SUN_CONVERSION_LIBFUNCS ) { set_conv_libfunc ( sfix_optab , DImode , SFmode , "__ftol" ) ; set_conv_libfunc ( ufix_optab , DImode , SFmode , "__ftoul" ) ; set_conv_libfunc ( sfix_optab , DImode , DFmode , "__dtol" ) ; set_conv_libfunc ( ufix_optab , DImode , DFmode , "__dtoul" ) ; } } gofast_maybe_init_libfuncs ( ) ; } </s>


<s> int PPCInstrInfo :: getOperandLatency ( const InstrItineraryData * ItinData , const MachineInstr & DefMI , unsigned DefIdx , const MachineInstr & UseMI , unsigned UseIdx ) const { int Latency = PPCGenInstrInfo :: getOperandLatency ( ItinData , DefMI , DefIdx , UseMI , UseIdx ) ; if ( ! DefMI . getParent ( ) ) return Latency ; const MachineOperand & DefMO = DefMI . getOperand ( DefIdx ) ; unsigned Reg = DefMO . getReg ( ) ; bool IsRegCR ; if ( TargetRegisterInfo :: isVirtualRegister ( Reg ) ) { const MachineRegisterInfo * MRI = & DefMI . getParent ( ) -> getParent ( ) -> getRegInfo ( ) ; IsRegCR = MRI -> getRegClass ( Reg ) -> hasSuperClassEq ( & PPC :: CRRCRegClass ) || MRI -> getRegClass ( Reg ) -> hasSuperClassEq ( & PPC :: CRBITRCRegClass ) ; } else { IsRegCR = PPC :: CRRCRegClass . contains ( Reg ) || PPC :: CRBITRCRegClass . contains ( Reg ) ; } if ( UseMI . isBranch ( ) && IsRegCR ) { if ( Latency < 0 ) Latency = getInstrLatency ( ItinData , DefMI ) ; unsigned Directive = Subtarget . getMcpu ( ) ; switch ( Directive ) { default : break ; case PPC :: MCPU_7400 : case PPC :: MCPU_750 : case PPC :: MCPU_970 : case PPC :: MCPU_E5500 : case PPC :: MCPU_PWR4 : case PPC :: MCPU_PWR5 : case PPC :: MCPU_PWR5X : case PPC :: MCPU_PWR6 : case PPC :: MCPU_PWR6X : case PPC :: MCPU_PWR7 : case PPC :: MCPU_PWR8 : Latency += 2 ; break ; } } return Latency ; } </s>

Compute and return the use operand latency of a given pair of def and use .


"Basic block should contain at least a RET but is empty"

runOnMachineFunction - Emit the function body .


<s>
bool
ARMCallLowering
::
lowerReturn
(
MachineIRBuilder
&
MIRBuilder
,
const
Value
*
Val
,
unsigned
VReg
)
const
{
assert
(
!
Val
==
!
VReg
&&
"Return value without a vreg"
)
;
auto
Ret
=
AddDefaultPred
(
MIRBuilder
.
buildInstrNoInsert
(
ARM
::
BX_RET
)
)
;
if
(
!
lowerReturnVal
(
MIRBuilder
,
Val
,
VReg
,
Ret
)
)
return
false
;
MIRBuilder
.
insertInstr
(
Ret
)
;
return
true
;
}
</s>

This hook behaves as the extended lowerReturn function , but for targets that do not support swifterror value promotion .

ARM
ARM
"Return value without a vreg"
ARM::BX_RET


<s> Optional < RegImmPair > MipsInstrInfo :: isAddImmediate ( const MachineInstr & MI , Register Reg ) const { const MachineOperand & Op0 = MI . getOperand ( 0 ) ; if ( ! Op0 . isReg ( ) || Reg != Op0 . getReg ( ) ) return None ; switch ( MI . getOpcode ( ) ) { case Mips :: ADDiu : case Mips :: DADDiu : { const MachineOperand & Dop = MI . getOperand ( 0 ) ; const MachineOperand & Sop1 = MI . getOperand ( 1 ) ; const MachineOperand & Sop2 = MI . getOperand ( 2 ) ; if ( Dop . isReg ( ) && Sop1 . isReg ( ) && Sop2 . isImm ( ) ) return RegImmPair { Sop1 . getReg ( ) , Sop2 . getImm ( ) } ; } } return None ; } </s>

If the specific machine instruction is an instruction that adds an immediate value and a register , and stores the result in the given register Reg , return a pair of the source register and the offset which has been added .


<s> static bool isNodeHidden ( const SCANode * N , const SpillCostAnalysisGraph & G ) { return ! N -> isVisible ( ) ; } </s>

Do not print nodes that are part of a pi-block separately .


<s>
virtual
const
char
*
getPassName
(
)
const
{
return
"X86 Maximal Stack Alignment Check"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> static ARMOperand * CreateReg ( unsigned RegNum , SMLoc S , SMLoc E ) { ARMOperand * Op = new ARMOperand ( Register ) ; Op -> Reg . RegNum = RegNum ; Op -> StartLoc = S ; Op -> EndLoc = E ; return Op ; } </s>

CreateReg - Allocate a single virtual register for the given type .


<s> static int sh_register_move_cost ( machine_mode mode , reg_class_t srcclass , reg_class_t dstclass ) { if ( dstclass == T_REGS || dstclass == PR_REGS ) return 10 ; if ( dstclass == MAC_REGS && srcclass == MAC_REGS ) return 4 ; if ( mode == SImode && ! TARGET_SHMEDIA && TARGET_FMOVD && REGCLASS_HAS_FP_REG ( srcclass ) && REGCLASS_HAS_FP_REG ( dstclass ) ) return 4 ; if ( REGCLASS_HAS_FP_REG ( dstclass ) && srcclass == T_REGS ) return ( ( TARGET_HARD_SH4 && ! optimize_size ) ? 10 : 7 ) ; if ( ( REGCLASS_HAS_FP_REG ( dstclass ) && srcclass == MAC_REGS ) || ( dstclass == MAC_REGS && REGCLASS_HAS_FP_REG ( srcclass ) ) ) return 9 ; if ( ( REGCLASS_HAS_FP_REG ( dstclass ) && REGCLASS_HAS_GENERAL_REG ( srcclass ) ) || ( REGCLASS_HAS_GENERAL_REG ( dstclass ) && REGCLASS_HAS_FP_REG ( srcclass ) ) ) { int addend = ( mode == Pmode ) ? 40 : 0 ; return ( ( ( TARGET_SHMEDIA ? 4 : TARGET_FMOVD ? 8 : 12 ) + addend ) * ( ( GET_MODE_SIZE ( mode ) + 7 ) / 8U ) ) ; } if ( ( dstclass == FPUL_REGS && REGCLASS_HAS_GENERAL_REG ( srcclass ) ) || ( srcclass == FPUL_REGS && REGCLASS_HAS_GENERAL_REG ( dstclass ) ) ) return 5 ; if ( ( dstclass == FPUL_REGS && ( srcclass == PR_REGS || srcclass == MAC_REGS || srcclass == T_REGS ) ) || ( srcclass == FPUL_REGS && ( dstclass == PR_REGS || dstclass == MAC_REGS ) ) ) return 7 ; if ( ( srcclass == TARGET_REGS && ! REGCLASS_HAS_GENERAL_REG ( dstclass ) ) || ( ( dstclass ) == TARGET_REGS && ! REGCLASS_HAS_GENERAL_REG ( srcclass ) ) ) return 20 ; if ( TARGET_SHMEDIA && ( ( srcclass ) == TARGET_REGS || ( srcclass ) == SIBCALL_REGS ) ) { if ( sh_gettrcost >= 0 ) return sh_gettrcost ; else if ( ! TARGET_PT_FIXED ) return 100 ; } if ( ( srcclass == FPSCR_REGS && ! REGCLASS_HAS_GENERAL_REG ( dstclass ) ) || ( dstclass == FPSCR_REGS && ! REGCLASS_HAS_GENERAL_REG ( srcclass ) ) ) return 4 ; if ( TARGET_SHMEDIA || ( TARGET_FMOVD && ! REGCLASS_HAS_GENERAL_REG ( srcclass ) && ! REGCLASS_HAS_GENERAL_REG ( dstclass ) ) ) return 2 * ( ( GET_MODE_SIZE ( mode ) + 7 ) / 8U ) ; return 2 * ( ( GET_MODE_SIZE ( mode ) + 3 ) / 4U ) ; } </s>

If SECONDARY * _RELOAD_CLASS says something about the src/dst pair , regclass uses this information . Hence , the general register < - > floating point register information here is not used for SFmode .