<s> void UnwindOpcodeAssembler :: EmitSPOffset ( int64_t Offset ) { if ( Offset > 0x200 ) { uint8_t Buff [ 16 ] ; Buff [ 0 ] = ARM :: EHABI :: UNWIND_OPCODE_INC_VSP_ULEB128 ; size_t ULEBSize = encodeULEB128 ( ( Offset - 0x204 ) >> 2 , Buff + 1 ) ; emitBytes ( Buff , ULEBSize + 1 ) ; } else if ( Offset > 0 ) { if ( Offset > 0x100 ) { EmitInt8 ( ARM :: EHABI :: UNWIND_OPCODE_INC_VSP | 0x3fu ) ; Offset -= 0x100 ; } EmitInt8 ( ARM :: EHABI :: UNWIND_OPCODE_INC_VSP | static_cast < uint8_t > ( ( Offset - 4 ) >> 2 ) ) ; } else if ( Offset < 0 ) { while ( Offset < - 0x100 ) { EmitInt8 ( ARM :: EHABI :: UNWIND_OPCODE_DEC_VSP | 0x3fu ) ; Offset += 0x100 ; } EmitInt8 ( ARM :: EHABI :: UNWIND_OPCODE_DEC_VSP | static_cast < uint8_t > ( ( ( - Offset ) - 4 ) >> 2 ) ) ; } } </s>

Emit unwind opcodes to add $ sp with an offset .


<s> void X86AsmParser :: emitInstruction ( MCInst & Inst , OperandVector & Operands , MCStreamer & Out ) { if ( LVIInlineAsmHardening && getSTI ( ) . getFeatureBits ( ) [ X86 :: FeatureLVIControlFlowIntegrity ] ) applyLVICFIMitigation ( Inst , Out ) ; Out . emitInstruction ( Inst , getSTI ( ) ) ; if ( LVIInlineAsmHardening && getSTI ( ) . getFeatureBits ( ) [ X86 :: FeatureLVILoadHardening ] ) applyLVILoadHardeningMitigation ( Inst , Out ) ; } </s>

Targets should implement this to emit instructions .


<s> const TargetRegisterClass * SIInstrInfo :: getRegClass ( const MCInstrDesc & TID , unsigned OpNum , const TargetRegisterInfo * TRI , const MachineFunction & MF ) const { if ( OpNum >= TID . getNumOperands ( ) ) return nullptr ; auto RegClass = TID . OpInfo [ OpNum ] . RegClass ; bool IsAllocatable = false ; if ( TID . TSFlags & ( SIInstrFlags :: DS | SIInstrFlags :: FLAT ) ) { const int VDstIdx = AMDGPU :: getNamedOperandIdx ( TID . Opcode , AMDGPU :: OpName :: vdst ) ; const int DataIdx = AMDGPU :: getNamedOperandIdx ( TID . Opcode , ( TID . TSFlags & SIInstrFlags :: DS ) ? AMDGPU :: OpName :: data0 : AMDGPU :: OpName :: vdata ) ; if ( DataIdx != - 1 ) { IsAllocatable = VDstIdx != - 1 || AMDGPU :: getNamedOperandIdx ( TID . Opcode , AMDGPU :: OpName :: data1 ) != - 1 ; } } RegClass = adjustAllocatableRegClass ( ST , MF . getRegInfo ( ) , TID , RegClass , IsAllocatable ) ; return RI . getRegClass ( RegClass ) ; } </s>

Given a machine instruction descriptor , returns the register class constraint for OpNum , or NULL .

AMDGPU SI SIInstrFlags::DS SIInstrFlags::FLAT AMDGPU::getNamedOperandIdx AMDGPU::OpName AMDGPU::getNamedOperandIdx SIInstrFlags::DS AMDGPU::OpName AMDGPU::OpName 1 1 AMDGPU::getNamedOperandIdx AMDGPU::OpName 1


Adjust code for uniform-simt code generation variant by making atomics and `` syscalls '' conditionally executed , and inserting shuffle-based propagation for registers being set .


<s> static void ix86_emit_restore_regs_using_pop ( void ) { unsigned int regno ; for ( regno = 0 ; regno < FIRST_PSEUDO_REGISTER ; regno ++ ) if ( GENERAL_REGNO_P ( regno ) && ix86_save_reg ( regno , false ) ) ix86_emit_restore_reg_using_pop ( gen_rtx_REG ( word_mode , regno ) ) ; } </s>

Emit code to restore saved registers using POP insns .


<s> bool PPCCTRLoops :: runOnFunction ( Function & F ) { LI = & getAnalysis < LoopInfoWrapperPass > ( ) . getLoopInfo ( ) ; SE = & getAnalysis < ScalarEvolutionWrapperPass > ( ) . getSE ( ) ; DT = & getAnalysis < DominatorTreeWrapperPass > ( ) . getDomTree ( ) ; DL = & F . getParent ( ) -> getDataLayout ( ) ; auto * TLIP = getAnalysisIfAvailable < TargetLibraryInfoWrapperPass > ( ) ; LibInfo = TLIP ? & TLIP -> getTLI ( ) : nullptr ; bool MadeChange = false ; for ( LoopInfo :: iterator I = LI -> begin ( ) , E = LI -> end ( ) ; I != E ; ++ I ) { Loop * L = * I ; if ( ! L -> getParentLoop ( ) ) MadeChange |= convertToCTRLoop ( L ) ; } return MadeChange ; } </s>

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .


<s>
void
ARM64RegisterInfo
::
eliminateFrameIndex
(
MachineBasicBlock
::
iterator
II
,
int
SPAdj
,
unsigned
FIOperandNum
,
RegScavenger
*
RS
)
const
{
assert
(
SPAdj
==
0
&&
"Unexpected"
)
;
MachineInstr
&
MI
=
*
II
;
MachineBasicBlock
&
MBB
=
*
MI
.
getParent
(
)
;
MachineFunction
&
MF
=
*
MBB
.
getParent
(
)
;
const
ARM64FrameLowering
*
TFI
=
static_cast
<
const
ARM64FrameLowering
*
>
(
MF
.
getTarget
(
)
.
getFrameLowering
(
)
)
;
int
FrameIndex
=
MI
.
getOperand
(
FIOperandNum
)
.
getIndex
(
)
;
unsigned
FrameReg
;
int
Offset
;
if
(
MI
.
isDebugValue
(
)
||
MI
.
getOpcode
(
)
==
TargetOpcode
::
STACKMAP
||
MI
.
getOpcode
(
)
==
TargetOpcode
::
PATCHPOINT
)
{
Offset
=
TFI
->
resolveFrameIndexReference
(
MF
,
FrameIndex
,
FrameReg
,
true
)
;
Offset
+=
MI
.
getOperand
(
FIOperandNum
+
1
)
.
getImm
(
)
;
MI
.
getOperand
(
FIOperandNum
)
.
ChangeToRegister
(
FrameReg
,
false
)
;
MI
.
getOperand
(
FIOperandNum
+
1
)
.
ChangeToImmediate
(
Offset
)
;
return
;
}
Offset
=
TFI
->
resolveFrameIndexReference
(
MF
,
FrameIndex
,
FrameReg
)
;
if
(
rewriteARM64FrameIndex
(
MI
,
FIOperandNum
,
FrameReg
,
Offset
,
TII
)
)
return
;
assert
(
(
!
RS
||
!
RS
->
isScavengingFrameIndex
(
FrameIndex
)
)
&&
"Emergency spill slot is out of reach"
)
;
unsigned
ScratchReg
=
MF
.
getRegInfo
(
)
.
createVirtualRegister
(
&
ARM64
::
GPR64RegClass
)
;
emitFrameOffset
(
MBB
,
II
,
MI
.
getDebugLoc
(
)
,
ScratchReg
,
FrameReg
,
Offset
,
TII
)
;
MI
.
getOperand
(
FIOperandNum
)
.
ChangeToRegister
(
ScratchReg
,
false
,
false
,
true
)
;
}
</s>

This method must be overriden to eliminate abstract frame indices from instructions which may use them .


<s> unsigned X86InstrInfo :: getUndefRegClearance ( const MachineInstr & MI , unsigned & OpNum , const TargetRegisterInfo * TRI ) const { if ( ! hasUndefRegUpdate ( MI . getOpcode ( ) ) ) return 0 ; OpNum = 1 ; const MachineOperand & MO = MI . getOperand ( OpNum ) ; if ( MO . isUndef ( ) && TargetRegisterInfo :: isPhysicalRegister ( MO . getReg ( ) ) ) { return UndefRegClearance ; } return 0 ; } </s>

Inform the BreakFalseDeps pass how many idle instructions we would like before certain undef register reads .


<s> const char * TOYTargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( Opcode ) { default : return NULL ; case TOYISD :: RET_FLAG : return "RetFlag" ; case TOYISD :: LOAD_SYM : return "LOAD_SYM" ; case TOYISD :: MOVEi32 : return "MOVEi32" ; case TOYISD :: CALL : return "CALL" ; } } </s>

getTargetNodeName - This method returns the name of a target specific


<s> unsigned AArch64TargetLowering :: getNumInterleavedAccesses ( VectorType * VecTy , const DataLayout & DL ) const { return ( DL . getTypeSizeInBits ( VecTy ) + 127 ) / 128 ; } </s>

Returns the number of interleaved accesses that will be generated when lowering accesses of the given type .


<s> DFAPacketizer * TPCInstrInfo :: CreateTargetScheduleState ( const TargetSubtargetInfo & STI ) const { const InstrItineraryData * II = STI . getInstrItineraryData ( ) ; return static_cast < const TPCSubtarget & > ( STI ) . createDFAPacketizer ( II ) ; } </s>

Create machine specific model for scheduling .


"%qE attribute only applies to functions"

Handle an attribute requiring a FUNCTION_DECL ; arguments as in struct attribute_spec.handler .


<s>
bool
TL45AsmParser
::
ParseInstruction
(
ParseInstructionInfo
&
Info
,
StringRef
Name
,
SMLoc
NameLoc
,
OperandVector
&
Operands
)
{
Operands
.
push_back
(
TL45Operand
::
CreateToken
(
Name
,
NameLoc
)
)
;
if
(
getLexer
(
)
.
is
(
AsmToken
::
EndOfStatement
)
)
return
false
;
if
(
ParseOperand
(
Operands
)
)
return
true
;
while
(
getLexer
(
)
.
isNot
(
AsmToken
::
EndOfStatement
)
)
{
if
(
getLexer
(
)
.
is
(
AsmToken
::
Comma
)
)
{
getLexer
(
)
.
Lex
(
)
;
continue
;
}
if
(
ParseOperand
(
Operands
)
)
return
true
;
}
if
(
getLexer
(
)
.
isNot
(
AsmToken
::
EndOfStatement
)
)
return
Error
(
getLexer
(
)
.
getTok
(
)
.
getLoc
(
)
,
"unexpected token in operand list"
)
;
return
false
;
}
</s>

ParseInstruction - Parse one assembly instruction .


<s> void MipsAsmPrinter :: emitFrameDirective ( ) { const TargetRegisterInfo & RI = * TM . getRegisterInfo ( ) ; unsigned stackReg = RI . getFrameRegister ( * MF ) ; unsigned returnReg = RI . getRARegister ( ) ; unsigned stackSize = MF -> getFrameInfo ( ) -> getStackSize ( ) ; OutStreamer . EmitRawText ( "\t.frame\t$" + Twine ( LowercaseString ( getRegisterName ( stackReg ) ) ) + "," + Twine ( stackSize ) + ",$" + Twine ( LowercaseString ( getRegisterName ( returnReg ) ) ) ) ; } </s>


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . setPreservesAll ( ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s>
virtual
const
char
*
getPassName
(
)
const
{
return
"ARM64 Address Type Promotion"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s>
SDValue
J2TargetLowering
::
LowerFormalArguments
(
SDValue
Chain
,
CallingConv
::
ID
CallConv
,
bool
IsVarArg
,
const
SmallVectorImpl
<
ISD
::
InputArg
>
&
Ins
,
const
SDLoc
&
DL
,
SelectionDAG
&
DAG
,
SmallVectorImpl
<
SDValue
>
&
InVals
)
const
{
assert
(
!
IsVarArg
&&
"Variable arguments not supported."
)
;
auto
&
MF
=
DAG
.
getMachineFunction
(
)
;
SmallVector
<
CCValAssign
,
16
>
ArgLocs
;
CCState
CCInfo
(
CallConv
,
IsVarArg
,
MF
,
ArgLocs
,
*
DAG
.
getContext
(
)
)
;
CCInfo
.
AnalyzeFormalArguments
(
Ins
,
CC_J2
)
;
for
(
unsigned
i
=
0
,
e
=
ArgLocs
.
size
(
)
;
i
!=
e
;
++
i
)
{
CCValAssign
&
VA
=
ArgLocs
[
i
]
;
MVT
RegVT
=
VA
.
getLocVT
(
)
;
const
TargetRegisterClass
*
RC
=
getRegClassFor
(
RegVT
)
;
unsigned
Reg
=
MF
.
addLiveIn
(
VA
.
getLocReg
(
)
,
RC
)
;
SDValue
ArgValue
=
DAG
.
getCopyFromReg
(
Chain
,
DL
,
Reg
,
RegVT
)
;
InVals
.
push_back
(
ArgValue
)
;
}
return
Chain
;
}
</s>

This hook must be implemented to lower the incoming ( formal ) arguments , described by the Ins array , into the specified DAG .


<s>
SDValue
TL45TargetLowering
::
LowerReturn
(
SDValue
Chain
,
CallingConv
::
ID
CallConv
,
bool
IsVarArg
,
const
SmallVectorImpl
<
ISD
::
OutputArg
>
&
Outs
,
const
SmallVectorImpl
<
SDValue
>
&
OutVals
,
const
SDLoc
&
DL
,
SelectionDAG
&
DAG
)
const
{
SmallVector
<
CCValAssign
,
16
>
RVLocs
;
CCState
CCInfo
(
CallConv
,
IsVarArg
,
DAG
.
getMachineFunction
(
)
,
RVLocs
,
*
DAG
.
getContext
(
)
)
;
analyzeOutputArgs
(
DAG
.
getMachineFunction
(
)
,
CCInfo
,
Outs
,
true
,
nullptr
)
;
SDValue
Glue
;
SmallVector
<
SDValue
,
4
>
RetOps
(
1
,
Chain
)
;
for
(
unsigned
i
=
0
,
e
=
RVLocs
.
size
(
)
;
i
<
e
;
++
i
)
{
SDValue
Val
=
OutVals
[
i
]
;
CCValAssign
&
VA
=
RVLocs
[
i
]
;
assert
(
VA
.
isRegLoc
(
)
&&
"Can only return in registers!"
)
;
if
(
VA
.
getLocVT
(
)
==
MVT
::
i32
&&
VA
.
getValVT
(
)
==
MVT
::
f64
)
{
llvm_unreachable
(
"not supported"
)
;
}
else
{
Val
=
convertValVTToLocVT
(
DAG
,
Val
,
VA
,
DL
)
;
Chain
=
DAG
.
getCopyToReg
(
Chain
,
DL
,
VA
.
getLocReg
(
)
,
Val
,
Glue
)
;
Glue
=
Chain
.
getValue
(
1
)
;
RetOps
.
push_back
(
DAG
.
getRegister
(
VA
.
getLocReg
(
)
,
VA
.
getLocVT
(
)
)
)
;
}
}
RetOps
[
0
]
=
Chain
;
if
(
Glue
.
getNode
(
)
)
{
RetOps
.
push_back
(
Glue
)
;
}
const
Function
&
Func
=
DAG
.
getMachineFunction
(
)
.
getFunction
(
)
;
if
(
Func
.
hasFnAttribute
(
"interrupt"
)
)
{
llvm_unreachable
(
"interrupts not supported"
)
;
}
return
DAG
.
getNode
(
TL45ISD
::
RET
,
DL
,
MVT
::
Other
,
RetOps
)
;
}
</s>

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .


<s> static int function_arg_slotno ( const struct sparc_args * cum , machine_mode mode , const_tree type , bool named , bool incoming , int * pregno , int * ppadding ) { const int regbase = incoming ? SPARC_INCOMING_INT_ARG_FIRST : SPARC_OUTGOING_INT_ARG_FIRST ; int slotno = cum -> words , regno ; enum mode_class mclass = GET_MODE_CLASS ( mode ) ; * pregno = - 1 ; * ppadding = - 1 ; if ( type && TREE_ADDRESSABLE ( type ) ) return - 1 ; if ( TARGET_ARCH64 && ( type ? TYPE_ALIGN ( type ) : GET_MODE_ALIGNMENT ( mode ) ) >= 128 && ( slotno & 1 ) != 0 ) { slotno ++ ; * ppadding = 1 ; } else * ppadding = 0 ; if ( type && VECTOR_TYPE_P ( type ) ) { if ( TREE_CODE ( TREE_TYPE ( type ) ) == REAL_TYPE ) { gcc_assert ( mode == BLKmode ) ; } else { gcc_assert ( mode != BLKmode ) ; mclass = MODE_FLOAT ; } } switch ( mclass ) { case MODE_FLOAT : case MODE_COMPLEX_FLOAT : case MODE_VECTOR_INT : if ( TARGET_ARCH64 && TARGET_FPU && named ) { if ( slotno >= SPARC_FP_ARG_MAX ) return - 1 ; regno = SPARC_FP_ARG_FIRST + slotno * 2 ; if ( GET_MODE_SIZE ( mode ) <= 4 ) regno ++ ; break ; } case MODE_INT : case MODE_COMPLEX_INT : if ( slotno >= SPARC_INT_ARG_MAX ) return - 1 ; regno = regbase + slotno ; break ; case MODE_RANDOM : if ( mode == VOIDmode ) return - 1 ; if ( TARGET_64BIT && TARGET_FPU && named && type && ( TREE_CODE ( type ) == RECORD_TYPE || VECTOR_TYPE_P ( type ) ) ) { if ( slotno >= SPARC_FP_ARG_MAX ) return - 1 ; if ( TREE_CODE ( type ) == RECORD_TYPE ) { classify_data_t data = { false , false } ; traverse_record_type < classify_data_t , classify_registers > ( type , named , & data ) ; if ( data . fp_regs ) { if ( slotno >= SPARC_FP_ARG_MAX - 1 && ! data . fp_regs_in_first_word ) return - 1 ; } else { if ( slotno >= SPARC_INT_ARG_MAX ) return - 1 ; } return slotno ; } regno = SPARC_FP_ARG_FIRST + slotno * 2 ; } else { if ( slotno >= SPARC_INT_ARG_MAX ) return - 1 ; regno = regbase + slotno ; } break ; default : gcc_unreachable ( ) ; } * pregno = regno ; return slotno ; } </s>

Compute the slot number to pass an argument in . Return the slot number or -1 if passing on the stack . CUM is a variable of type CUMULATIVE_ARGS which gives info about the preceding args and about the function being called . MODE is the argument 's machine mode . TYPE is the data type of the argument ( as a tree ) . This is null for libcalls where that information may not be available . NAMED is nonzero if this argument is a named parameter ( otherwise it is an extra parameter matching an ellipsis ) . INCOMING_P is zero for FUNCTION_ARG , nonzero for FUNCTION_INCOMING_ARG . * PREGNO records the register number to use if scalar type . * PPADDING records the amount of padding needed in words .


<s> std :: unique_ptr < TargetInstrInfo :: PipelinerLoopInfo > PPCInstrInfo :: analyzeLoopForPipelining ( MachineBasicBlock * LoopBB ) const { MachineBasicBlock :: iterator I = LoopBB -> getFirstTerminator ( ) ; MachineBasicBlock * Preheader = * LoopBB -> pred_begin ( ) ; if ( Preheader == LoopBB ) Preheader = * std :: next ( LoopBB -> pred_begin ( ) ) ; MachineFunction * MF = Preheader -> getParent ( ) ; if ( I != LoopBB -> end ( ) && isBDNZ ( I -> getOpcode ( ) ) ) { SmallPtrSet < MachineBasicBlock * , 8 > Visited ; if ( MachineInstr * LoopInst = findLoopInstr ( * Preheader , Visited ) ) { Register LoopCountReg = LoopInst -> getOperand ( 0 ) . getReg ( ) ; MachineRegisterInfo & MRI = MF -> getRegInfo ( ) ; MachineInstr * LoopCount = MRI . getUniqueVRegDef ( LoopCountReg ) ; return std :: make_unique < PPCPipelinerLoopInfo > ( LoopInst , & * I , LoopCount ) ; } } return nullptr ; } </s>

Analyze loop L , which must be a single-basic-block loop , and if the conditions can be understood enough produce a PipelinerLoopInfo object .


<s> void init ( TPCMachineScheduler * dag , const TargetSchedModel * smodel ) { DAG = dag ; SchedModel = smodel ; IssueCount = 0 ; CurrCycle = 0 ; CriticalPathLength = 1 ; int bbApproxSize = 0 ; for ( auto & SU : DAG -> SUnits ) { if ( SU . getInstr ( ) -> isPseudo ( ) && ! SU . getInstr ( ) -> isCopy ( ) ) { continue ; } bbApproxSize ++ ; } if ( bbApproxSize < 100 ) { CriticalPathLength >>= 1 ; return ; } unsigned MaxPath = 0 ; for ( auto & SU : DAG -> SUnits ) MaxPath = std :: max ( MaxPath , isTop ( ) ? SU . getHeight ( ) : SU . getDepth ( ) ) ; CriticalPathLength = std :: max ( CriticalPathLength , MaxPath ) + 1 ; } </s>

Initialize the machine model for instruction scheduling .


<s>
const
char
*
getPassName
(
)
const
override
{
return
"SI Fix SGPR copies"
;
}
</s>


<s> static bool rs6000_builtin_valid_without_lhs ( enum rs6000_builtins fn_code ) { switch ( fn_code ) { case ALTIVEC_BUILTIN_STVX_V16QI : case ALTIVEC_BUILTIN_STVX_V8HI : case ALTIVEC_BUILTIN_STVX_V4SI : case ALTIVEC_BUILTIN_STVX_V4SF : case ALTIVEC_BUILTIN_STVX_V2DI : case ALTIVEC_BUILTIN_STVX_V2DF : case VSX_BUILTIN_STXVW4X_V16QI : case VSX_BUILTIN_STXVW4X_V8HI : case VSX_BUILTIN_STXVW4X_V4SF : case VSX_BUILTIN_STXVW4X_V4SI : case VSX_BUILTIN_STXVD2X_V2DF : case VSX_BUILTIN_STXVD2X_V2DI : return true ; default : return false ; } } </s>

Helper function to sort out which built-ins may be valid without having a LHS .


<s> virtual const MipsInstrInfo * getInstrInfo ( ) const { return & InstrInfo ; } </s>


<s> bool runOnMachineFunction ( MachineFunction & MF ) override { const X86TargetMachine * TM = static_cast < const X86TargetMachine * > ( & MF . getTarget ( ) ) ; const X86Subtarget & STI = MF . getSubtarget < X86Subtarget > ( ) ; if ( STI . is64Bit ( ) ) return false ; if ( TM -> getRelocationModel ( ) != Reloc :: PIC_ ) return false ; X86MachineFunctionInfo * X86FI = MF . getInfo < X86MachineFunctionInfo > ( ) ; unsigned GlobalBaseReg = X86FI -> getGlobalBaseReg ( ) ; if ( GlobalBaseReg == 0 ) return false ; MachineBasicBlock & FirstMBB = MF . front ( ) ; MachineBasicBlock :: iterator MBBI = FirstMBB . begin ( ) ; DebugLoc DL = FirstMBB . findDebugLoc ( MBBI ) ; MachineRegisterInfo & RegInfo = MF . getRegInfo ( ) ; const X86InstrInfo * TII = STI . getInstrInfo ( ) ; unsigned PC ; if ( STI . isPICStyleGOT ( ) ) PC = RegInfo . createVirtualRegister ( & X86 :: GR32RegClass ) ; else PC = GlobalBaseReg ; BuildMI ( FirstMBB , MBBI , DL , TII -> get ( X86 :: MOVPC32r ) , PC ) . addImm ( 0 ) ; if ( STI . isPICStyleGOT ( ) ) { BuildMI ( FirstMBB , MBBI , DL , TII -> get ( X86 :: ADD32ri ) , GlobalBaseReg ) . addReg ( PC ) . addExternalSymbol ( "_GLOBAL_OFFSET_TABLE_" , X86II :: MO_GOT_ABSOLUTE_ADDRESS ) ; } return true ; } </s>

runOnMachineFunction - Emit the function body .


<s> void XCoreInstrInfo :: loadRegFromStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned DestReg , int FrameIndex , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { DebugLoc DL ; if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; BuildMI ( MBB , I , DL , get ( XCore :: LDWFI ) , DestReg ) . addFrameIndex ( FrameIndex ) . addImm ( 0 ) ; } </s>

Load the specified register of the given register class from the specified stack frame index .


<s> bool AArch64InstrInfo :: isFunctionSafeToOutlineFrom ( MachineFunction & MF , bool OutlineFromLinkOnceODRs ) const { const Function & F = MF . getFunction ( ) ; if ( ! F . hasFnAttribute ( Attribute :: NoRedZone ) ) return false ; if ( F . hasAddressTaken ( ) ) return false ; if ( ! OutlineFromLinkOnceODRs && F . hasLinkOnceODRLinkage ( ) ) return false ; return true ; } </s>

Return true if the function can safely be outlined from .


<s>
const
char
*
MipsAsmPrinter
::
getCurrentABIString
(
)
const
{
switch
(
static_cast
<
MipsTargetMachine
&
>
(
TM
)
.
getABI
(
)
.
GetEnumValue
(
)
)
{
case
MipsABIInfo
::
ABI
::
O32
:
return
"abi32"
;
case
MipsABIInfo
::
ABI
::
N32
:
return
"abiN32"
;
case
MipsABIInfo
::
ABI
::
N64
:
return
"abi64"
;
default
:
llvm_unreachable
(
"Unknown Mips ABI"
)
;
}
}
</s>

Mips
Mips
Mips
Mips
"abi32"
Mips
"abiN32"
Mips
"abi64"
"Unknown Mips ABI"


<s> static void emit_add_sp_const ( HOST_WIDE_INT offset , bool frame_related_p ) { rtx to_add = GEN_INT ( offset ) ; rtx orig_to_add = to_add ; rtx_insn * insn ; if ( offset == 0 ) return ; if ( offset < - 32768 || offset > 32767 ) { rtx reg = gen_rtx_REG ( SImode , REG_A0 ) ; rtx low = GEN_INT ( trunc_int_for_mode ( offset , HImode ) ) ; insn = emit_insn ( gen_movsi_high ( reg , low ) ) ; if ( frame_related_p ) RTX_FRAME_RELATED_P ( insn ) = 1 ; insn = emit_insn ( gen_movsi_lo_sum ( reg , reg , to_add ) ) ; if ( frame_related_p ) RTX_FRAME_RELATED_P ( insn ) = 1 ; to_add = reg ; } insn = emit_insn ( gen_addsi3 ( stack_pointer_rtx , stack_pointer_rtx , to_add ) ) ; if ( frame_related_p ) { if ( REG_P ( to_add ) ) add_reg_note ( insn , REG_FRAME_RELATED_EXPR , gen_rtx_SET ( stack_pointer_rtx , gen_rtx_PLUS ( Pmode , stack_pointer_rtx , orig_to_add ) ) ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; } } </s>

Emit insns to increment the stack pointer by OFFSET . If FRAME_RELATED_P , set the RTX_FRAME_RELATED_P flag on the insns . Does nothing if the offset is zero .


<s>
SDValue
LoongArchTargetLowering
::
LowerFormalArguments
(
SDValue
Chain
,
CallingConv
::
ID
CallConv
,
bool
IsVarArg
,
const
SmallVectorImpl
<
ISD
::
InputArg
>
&
Ins
,
const
SDLoc
&
DL
,
SelectionDAG
&
DAG
,
SmallVectorImpl
<
SDValue
>
&
InVals
)
const
{
MachineFunction
&
MF
=
DAG
.
getMachineFunction
(
)
;
switch
(
CallConv
)
{
default
:
llvm_unreachable
(
"Unsupported calling convention"
)
;
case
CallingConv
::
C
:
break
;
}
SmallVector
<
CCValAssign
>
ArgLocs
;
CCState
CCInfo
(
CallConv
,
IsVarArg
,
MF
,
ArgLocs
,
*
DAG
.
getContext
(
)
)
;
analyzeInputArgs
(
CCInfo
,
Ins
,
CC_LoongArch
)
;
for
(
unsigned
i
=
0
,
e
=
ArgLocs
.
size
(
)
;
i
!=
e
;
++
i
)
InVals
.
push_back
(
unpackFromRegLoc
(
DAG
,
Chain
,
ArgLocs
[
i
]
,
DL
,
*
this
)
)
;
return
Chain
;
}
</s>

LoongArch
LoongArch
ISD::InputArg
"Unsupported calling convention"
LoongArch
0


<s> Expected < const MCExpr * > createExprForCAPIVariantKind ( const MCExpr * SubExpr , unsigned VariantKind ) override { switch ( VariantKind ) { case LLVMDisassembler_VariantKind_ARM_HI16 : return ARMMCExpr :: createUpper16 ( SubExpr , Ctx ) ; case LLVMDisassembler_VariantKind_ARM_LO16 : return ARMMCExpr :: createLower16 ( SubExpr , Ctx ) ; default : return MCRelocationInfo :: createExprForCAPIVariantKind ( SubExpr , VariantKind ) ; } } </s>

Create an MCExpr for the target-specific VariantKind .


<s> static void ix86_canonicalize_comparison ( int * code , rtx * op0 , rtx * op1 , bool op0_preserve_value ) { if ( ! op0_preserve_value && GET_CODE ( * op0 ) == FLOAT && MEM_P ( XEXP ( * op0 , 0 ) ) && REG_P ( * op1 ) ) { enum rtx_code scode = swap_condition ( ( enum rtx_code ) * code ) ; if ( ix86_fp_compare_code_to_integer ( scode ) != UNKNOWN ) { std :: swap ( * op0 , * op1 ) ; * code = ( int ) scode ; } } } </s>

Canonicalize a comparison from one we do n't have to one we do have .


<s> static bool mips_expand_vpc_loongson_bcast ( struct expand_vec_perm_d * d ) { unsigned i , elt ; rtx t0 , t1 ; if ( ! ( TARGET_HARD_FLOAT && TARGET_LOONGSON_MMI ) ) return false ; if ( d -> vmode != V8QImode ) return false ; if ( ! d -> one_vector_p ) return false ; elt = d -> perm [ 0 ] ; for ( i = 1 ; i < 8 ; ++ i ) if ( d -> perm [ i ] != elt ) return false ; if ( d -> testing_p ) return true ; t0 = gen_reg_rtx ( V8QImode ) ; if ( elt < 4 ) emit_insn ( gen_loongson_punpcklbh ( t0 , d -> op0 , d -> op0 ) ) ; else emit_insn ( gen_loongson_punpckhbh ( t0 , d -> op0 , d -> op0 ) ) ; elt &= 3 ; elt *= 0x55 ; t1 = gen_reg_rtx ( V4HImode ) ; emit_insn ( gen_loongson_pshufh ( t1 , gen_lowpart ( V4HImode , t0 ) , force_reg ( SImode , GEN_INT ( elt ) ) ) ) ; emit_move_insn ( d -> target , gen_lowpart ( V8QImode , t1 ) ) ; return true ; } </s>

Recognize broadcast patterns for the Loongson .


"This eliminateCallFramePseudoInstr does not support Thumb1!"

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .


<s> int m32c_hard_regno_ok ( int regno , enum machine_mode mode ) { return m32c_hard_regno_nregs ( regno , mode ) != 0 ; } </s>

Implements HARD_REGNO_MODE_OK . The above function does the work already ; just test its return value .


<s> unsigned MipsMCCodeEmitter :: getMachineOpValue ( const MCInst & MI , const MCOperand & MO , SmallVectorImpl < MCFixup > & Fixups ) const { if ( MO . isReg ( ) ) { unsigned Reg = MO . getReg ( ) ; unsigned RegNo = getMipsRegisterNumbering ( Reg ) ; return RegNo ; } else if ( MO . isImm ( ) ) { return static_cast < unsigned > ( MO . getImm ( ) ) ; } else if ( MO . isFPImm ( ) ) { return static_cast < unsigned > ( APFloat ( MO . getFPImm ( ) ) . bitcastToAPInt ( ) . getHiBits ( 32 ) . getLimitedValue ( ) ) ; } assert ( MO . isExpr ( ) ) ; const MCExpr * Expr = MO . getExpr ( ) ; MCExpr :: ExprKind Kind = Expr -> getKind ( ) ; if ( Kind == MCExpr :: Binary ) { Expr = static_cast < const MCBinaryExpr * > ( Expr ) -> getLHS ( ) ; Kind = Expr -> getKind ( ) ; } assert ( Kind == MCExpr :: SymbolRef ) ; Mips :: Fixups FixupKind = Mips :: Fixups ( 0 ) ; switch ( cast < MCSymbolRefExpr > ( Expr ) -> getKind ( ) ) { case MCSymbolRefExpr :: VK_Mips_GPREL : FixupKind = Mips :: fixup_Mips_GPREL16 ; break ; case MCSymbolRefExpr :: VK_Mips_GOT_CALL : FixupKind = Mips :: fixup_Mips_CALL16 ; break ; case MCSymbolRefExpr :: VK_Mips_GOT16 : FixupKind = Mips :: fixup_Mips_GOT_Global ; break ; case MCSymbolRefExpr :: VK_Mips_GOT : FixupKind = Mips :: fixup_Mips_GOT_Local ; break ; case MCSymbolRefExpr :: VK_Mips_ABS_HI : FixupKind = Mips :: fixup_Mips_HI16 ; break ; case MCSymbolRefExpr :: VK_Mips_ABS_LO : FixupKind = Mips :: fixup_Mips_LO16 ; break ; case MCSymbolRefExpr :: VK_Mips_TLSGD : FixupKind = Mips :: fixup_Mips_TLSGD ; break ; case MCSymbolRefExpr :: VK_Mips_TLSLDM : FixupKind = Mips :: fixup_Mips_TLSLDM ; break ; case MCSymbolRefExpr :: VK_Mips_DTPREL_HI : FixupKind = Mips :: fixup_Mips_DTPREL_HI ; break ; case MCSymbolRefExpr :: VK_Mips_DTPREL_LO : FixupKind = Mips :: fixup_Mips_DTPREL_LO ; break ; case MCSymbolRefExpr :: VK_Mips_GOTTPREL : FixupKind = Mips :: fixup_Mips_GOTTPREL ; break ; case MCSymbolRefExpr :: VK_Mips_TPREL_HI : FixupKind = Mips :: fixup_Mips_TPREL_HI ; break ; case MCSymbolRefExpr :: VK_Mips_TPREL_LO : FixupKind = Mips :: fixup_Mips_TPREL_LO ; break ; default : break ; } Fixups . push_back ( MCFixup :: Create ( 0 , MO . getExpr ( ) , MCFixupKind ( FixupKind ) ) ) ; return 0 ; } </s>

getMachineOpValue - Return binary encoding of operand .


<s> bool hasVMEMReadSGPRVALUDefHazard ( ) const { return getGeneration ( ) >= VOLCANIC_ISLANDS ; } </s>

A read of an SGPR by a VMEM instruction requires 5 wait states when the SGPR was written by a VALU Instruction .


"Module has aliases, which NVPTX does not support."

"Module has a nontrivial global ctor, which NVPTX does not support."

"Module has a nontrivial global dtor, which NVPTX does not support."

Set up the AsmPrinter when we are working on a new module .


<s> void loongarch_output_ascii ( FILE * stream , const char * string , size_t len ) { size_t i ; int cur_pos ; cur_pos = 17 ; fprintf ( stream , "\t.ascii\t\"" ) ; for ( i = 0 ; i < len ; i ++ ) { int c ; c = ( unsigned char ) string [ i ] ; if ( ISPRINT ( c ) ) { if ( c == '\\' || c == '\"' ) { putc ( '\\' , stream ) ; cur_pos ++ ; } putc ( c , stream ) ; cur_pos ++ ; } else { fprintf ( stream , "\\%03o" , c ) ; cur_pos += 4 ; } if ( cur_pos > 72 && i + 1 < len ) { cur_pos = 17 ; fprintf ( stream , "\"\n\t.ascii\t\"" ) ; } } fprintf ( stream , "\"\n" ) ; } </s>


<s> bool ix86_lea_for_add_ok ( rtx_insn * insn , rtx operands [ ] ) { unsigned int regno0 = true_regnum ( operands [ 0 ] ) ; unsigned int regno1 = true_regnum ( operands [ 1 ] ) ; unsigned int regno2 = true_regnum ( operands [ 2 ] ) ; if ( regno0 != regno1 && regno0 != regno2 ) return true ; if ( ! TARGET_OPT_AGU || optimize_function_for_size_p ( cfun ) ) return false ; return ix86_lea_outperforms ( insn , regno0 , regno1 , regno2 , 0 , false ) ; } </s>

Return true if it is ok to optimize an ADD operation to LEA operation to avoid flag register consumation . For most processors , ADD is faster than LEA . For the processors like BONNELL , if the destination register of LEA holds an actual address which will be used soon , LEA is better and otherwise ADD is better .


<s> void X86IntelInstPrinter :: printInst ( const MCInst * MI , raw_ostream & OS , StringRef Annot , const MCSubtargetInfo & STI ) { printInstFlags ( MI , OS ) ; if ( MI -> getOpcode ( ) == X86 :: DATA16_PREFIX && STI . getFeatureBits ( ) [ X86 :: Mode16Bit ] ) { OS << "\tdata32" ; } else if ( ! printAliasInstr ( MI , OS ) && ! printVecCompareInstr ( MI , OS ) ) printInstruction ( MI , OS ) ; printAnnotation ( OS , Annot ) ; if ( CommentStream ) EmitAnyX86InstComments ( MI , * CommentStream , MII ) ; } </s>

Print the specified MCInst to the specified raw_ostream .


"CPU0 DAG->DAG Pattern Instruction Selection"

getPassName - Return a nice clean name for a pass .


<s> static void expand_strncmp_align_check ( rtx strncmp_label , rtx src , HOST_WIDE_INT bytes ) { rtx lab_ref = gen_rtx_LABEL_REF ( VOIDmode , strncmp_label ) ; rtx src_check = copy_addr_to_reg ( XEXP ( src , 0 ) ) ; if ( GET_MODE ( src_check ) == SImode ) emit_insn ( gen_andsi3 ( src_check , src_check , GEN_INT ( 0xfff ) ) ) ; else emit_insn ( gen_anddi3 ( src_check , src_check , GEN_INT ( 0xfff ) ) ) ; rtx cond = gen_reg_rtx ( CCmode ) ; emit_move_insn ( cond , gen_rtx_COMPARE ( CCmode , src_check , GEN_INT ( 4096 - bytes ) ) ) ; rtx cmp_rtx = gen_rtx_LT ( VOIDmode , cond , const0_rtx ) ; rtx ifelse = gen_rtx_IF_THEN_ELSE ( VOIDmode , cmp_rtx , pc_rtx , lab_ref ) ; rtx j = emit_jump_insn ( gen_rtx_SET ( pc_rtx , ifelse ) ) ; JUMP_LABEL ( j ) = strncmp_label ; LABEL_NUSES ( strncmp_label ) += 1 ; } </s>

Generate page crossing check and branch code to set up for strncmp when we do n't have DI alignment . STRNCMP_LABEL is the label to branch if there is a page crossing . SRC_ADDR is the string address to be examined . BYTES is the max number of bytes to compare .


<s> static int arm_comp_type_attributes ( const_tree type1 , const_tree type2 ) { int l1 , l2 , s1 , s2 ; if ( TREE_CODE ( type1 ) != FUNCTION_TYPE ) return 1 ; l1 = lookup_attribute ( "long_call" , TYPE_ATTRIBUTES ( type1 ) ) != NULL ; l2 = lookup_attribute ( "long_call" , TYPE_ATTRIBUTES ( type2 ) ) != NULL ; s1 = lookup_attribute ( "short_call" , TYPE_ATTRIBUTES ( type1 ) ) != NULL ; s2 = lookup_attribute ( "short_call" , TYPE_ATTRIBUTES ( type2 ) ) != NULL ; if ( l1 | l2 | s1 | s2 ) { if ( ( l1 != l2 ) || ( s1 != s2 ) ) return 0 ; if ( ( l1 & s2 ) || ( l2 & s1 ) ) return 0 ; } l1 = lookup_attribute ( "isr" , TYPE_ATTRIBUTES ( type1 ) ) != NULL ; if ( ! l1 ) l1 = lookup_attribute ( "interrupt" , TYPE_ATTRIBUTES ( type1 ) ) != NULL ; l2 = lookup_attribute ( "isr" , TYPE_ATTRIBUTES ( type2 ) ) != NULL ; if ( ! l2 ) l1 = lookup_attribute ( "interrupt" , TYPE_ATTRIBUTES ( type2 ) ) != NULL ; if ( l1 != l2 ) return 0 ; return 1 ; } </s>

Return 0 if the attributes for two types are incompatible , 1 if they are compatible , and 2 if they are nearly compatible ( which causes a warning to be generated ) .


<s> static void dump_tree_root_info ( fma_forest * forest , fma_root_node * node ) { node -> dump_info ( forest ) ; } </s>

Wrapper around fma_root_node : :dump_info for use as parameter of function pointer type in func_fma_steering : :dfs .


<s> static const char * rs6000_mangle_type ( const_tree type ) { type = TYPE_MAIN_VARIANT ( type ) ; if ( TREE_CODE ( type ) != VOID_TYPE && TREE_CODE ( type ) != BOOLEAN_TYPE && TREE_CODE ( type ) != INTEGER_TYPE && TREE_CODE ( type ) != REAL_TYPE && TREE_CODE ( type ) != OPAQUE_TYPE ) return NULL ; if ( type == bool_char_type_node ) return "U6__boolc" ; if ( type == bool_short_type_node ) return "U6__bools" ; if ( type == pixel_type_node ) return "u7__pixel" ; if ( type == bool_int_type_node ) return "U6__booli" ; if ( type == bool_long_long_type_node ) return "U6__boolx" ; if ( type == float128_type_node || type == float64x_type_node ) return NULL ; if ( SCALAR_FLOAT_TYPE_P ( type ) && FLOAT128_IBM_P ( TYPE_MODE ( type ) ) ) return "g" ; if ( SCALAR_FLOAT_TYPE_P ( type ) && FLOAT128_IEEE_P ( TYPE_MODE ( type ) ) ) return "u9__ieee128" ; if ( type == vector_pair_type_node ) return "u13__vector_pair" ; if ( type == vector_quad_type_node ) return "u13__vector_quad" ; return NULL ; } </s>

AltiVec defines five built-in scalar types that serve as vector elements ; we must teach the compiler how to mangle them . The 128-bit floating point mangling is target-specific as well . MMA defines two built-in types to be used as opaque vector types .


<s> void M68kIncomingValueHandler :: assignValueToAddress ( Register ValVReg , Register Addr , LLT MemTy , MachinePointerInfo & MPO , CCValAssign & VA ) { MachineFunction & MF = MIRBuilder . getMF ( ) ; auto * MMO = MF . getMachineMemOperand ( MPO , MachineMemOperand :: MOLoad , MemTy , inferAlignFromPtrInfo ( MF , MPO ) ) ; MIRBuilder . buildLoad ( ValVReg , Addr , * MMO ) ; } </s>

An overload which takes an ArgInfo if additional information about the arg is needed .


<s> void PPCDispatchGroupSBHazardRecognizer :: EmitNoop ( ) { unsigned Directive = DAG -> MF . getSubtarget < PPCSubtarget > ( ) . getDarwinDirective ( ) ; if ( Directive == PPC :: DIR_PWR6 || Directive == PPC :: DIR_PWR7 || Directive == PPC :: DIR_PWR8 || Directive == PPC :: DIR_PWR9 || CurSlots == 6 ) { CurGroup . clear ( ) ; CurSlots = CurBranches = 0 ; } else { CurGroup . push_back ( nullptr ) ; ++ CurSlots ; } } </s>

EmitNoop - This callback is invoked when a noop was added to the instruction stream .


<s> unsigned getExceptionSelectorRegister ( const Constant * PersonalityFn ) const override { return SystemZ :: R7D ; } </s>

If a physical register , this returns the register that receives the exception typeid on entry to a landing pad .


"returning values via memory not yet supported!"

LowerCallResult - Lower the result values of an ISD : :CALL into the appropriate copies out of appropriate physical registers .


<s> bool isMem ( ) const { return false ; } </s>


<s> void nds32_expand_epilogue_v3pop ( bool sibcall_p ) { int sp_adjust ; unsigned Rb , Re ; nds32_compute_stack_frame ( ) ; emit_insn ( gen_blockage ( ) ) ; if ( cfun -> machine -> naked_p ) { if ( ! sibcall_p ) { if ( cfun -> machine -> attr_naked_p && ! flag_ret_in_naked_func ) return ; emit_jump_insn ( gen_return_internal ( ) ) ; } return ; } Rb = cfun -> machine -> callee_saved_first_gpr_regno ; Re = cfun -> machine -> callee_saved_last_gpr_regno ; sp_adjust = cfun -> machine -> local_size + cfun -> machine -> out_args_size + cfun -> machine -> callee_saved_area_gpr_padding_bytes + cfun -> machine -> callee_saved_fpr_regs_size ; if ( satisfies_constraint_Iu08 ( GEN_INT ( sp_adjust ) ) && NDS32_DOUBLE_WORD_ALIGN_P ( sp_adjust ) && ! cfun -> calls_alloca ) { if ( cfun -> machine -> callee_saved_first_fpr_regno != SP_REGNUM ) { int fpr_position = cfun -> machine -> local_size + cfun -> machine -> out_args_size ; nds32_emit_v3pop_fpr_callee_saved ( fpr_position ) ; } nds32_emit_stack_v3pop ( Rb , Re , sp_adjust ) ; } else { if ( frame_pointer_needed ) { sp_adjust = cfun -> machine -> fp_size + cfun -> machine -> gp_size + cfun -> machine -> lp_size + cfun -> machine -> callee_saved_gpr_regs_size ; if ( cfun -> machine -> callee_saved_first_fpr_regno != SP_REGNUM ) { sp_adjust = sp_adjust + cfun -> machine -> callee_saved_area_gpr_padding_bytes + cfun -> machine -> callee_saved_fpr_regs_size ; nds32_emit_adjust_frame ( stack_pointer_rtx , hard_frame_pointer_rtx , - 1 * sp_adjust ) ; nds32_emit_v3pop_fpr_callee_saved ( 0 ) ; } else { nds32_emit_adjust_frame ( stack_pointer_rtx , hard_frame_pointer_rtx , - 1 * sp_adjust ) ; } } else { sp_adjust = cfun -> machine -> local_size + cfun -> machine -> out_args_size + cfun -> machine -> callee_saved_area_gpr_padding_bytes + cfun -> machine -> callee_saved_fpr_regs_size ; if ( cfun -> machine -> callee_saved_first_fpr_regno != SP_REGNUM ) { sp_adjust = sp_adjust - cfun -> machine -> callee_saved_area_gpr_padding_bytes - cfun -> machine -> callee_saved_fpr_regs_size ; nds32_emit_adjust_frame ( stack_pointer_rtx , stack_pointer_rtx , sp_adjust ) ; nds32_emit_v3pop_fpr_callee_saved ( 0 ) ; } else { nds32_emit_adjust_frame ( stack_pointer_rtx , stack_pointer_rtx , sp_adjust ) ; } } if ( cfun -> machine -> callee_saved_first_fpr_regno != SP_REGNUM ) { int fpr_space = cfun -> machine -> callee_saved_area_gpr_padding_bytes + cfun -> machine -> callee_saved_fpr_regs_size ; nds32_emit_stack_v3pop ( Rb , Re , fpr_space ) ; } else { nds32_emit_stack_v3pop ( Rb , Re , 0 ) ; } } emit_jump_insn ( gen_pop25return ( ) ) ; } </s>


<s> Optional < DestSourcePair > MipsSEInstrInfo :: isCopyInstrImpl ( const MachineInstr & MI ) const { bool isDSPControlWrite = false ; if ( isReadOrWriteToDSPReg ( MI , isDSPControlWrite ) ) { if ( ! MI . getOperand ( 1 ) . isImm ( ) || MI . getOperand ( 1 ) . getImm ( ) != ( 1 << 4 ) ) return None ; else if ( isDSPControlWrite ) { return DestSourcePair { MI . getOperand ( 2 ) , MI . getOperand ( 0 ) } ; } else { return DestSourcePair { MI . getOperand ( 0 ) , MI . getOperand ( 2 ) } ; } } else if ( MI . isMoveReg ( ) || isORCopyInst ( MI ) || isCIncOffsetCopyInst ( MI ) ) { return DestSourcePair { MI . getOperand ( 0 ) , MI . getOperand ( 1 ) } ; } return None ; } </s>

If the specific machine instruction is a instruction that moves/copies value from one register to another register return destination and source registers as machine operands .


<s>
bool
SILoadStoreOptimizer
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
if
(
skipFunction
(
*
MF
.
getFunction
(
)
)
)
return
false
;
STM
=
&
MF
.
getSubtarget
<
SISubtarget
>
(
)
;
if
(
!
STM
->
loadStoreOptEnabled
(
)
)
return
false
;
TII
=
STM
->
getInstrInfo
(
)
;
TRI
=
&
TII
->
getRegisterInfo
(
)
;
MRI
=
&
MF
.
getRegInfo
(
)
;
AA
=
&
getAnalysis
<
AAResultsWrapperPass
>
(
)
.
getAAResults
(
)
;
assert
(
MRI
->
isSSA
(
)
&&
"Must be run on SSA"
)
;
DEBUG
(
dbgs
(
)
<<
"Running SILoadStoreOptimizer\n"
)
;
bool
Modified
=
false
;
CreatedX2
=
0
;
for
(
MachineBasicBlock
&
MBB
:
MF
)
Modified
|=
optimizeBlock
(
MBB
)
;
if
(
CreatedX2
>=
1
)
{
for
(
MachineBasicBlock
&
MBB
:
MF
)
Modified
|=
optimizeBlock
(
MBB
)
;
}
return
Modified
;
}
</s>

runOnMachineFunction - Emit the function body .

AMDGPU
SI
SI
"Must be run on SSA"
"Running SILoadStoreOptimizer\n"
0
1


<s> bool AArch64FrameLowering :: assignCalleeSavedSpillSlots ( MachineFunction & MF , const TargetRegisterInfo * RegInfo , std :: vector < CalleeSavedInfo > & CSI , unsigned & MinCSFrameIndex , unsigned & MaxCSFrameIndex ) const { bool NeedsWinCFI = needsWinCFI ( MF ) ; if ( NeedsWinCFI ) std :: reverse ( CSI . begin ( ) , CSI . end ( ) ) ; if ( CSI . empty ( ) ) return true ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; auto * AFI = MF . getInfo < AArch64FunctionInfo > ( ) ; for ( auto & CS : CSI ) { Register Reg = CS . getReg ( ) ; const TargetRegisterClass * RC = RegInfo -> getMinimalPhysRegClass ( Reg ) ; unsigned Size = RegInfo -> getSpillSize ( * RC ) ; Align Alignment ( RegInfo -> getSpillAlign ( * RC ) ) ; int FrameIdx = MFI . CreateStackObject ( Size , Alignment , true ) ; CS . setFrameIdx ( FrameIdx ) ; if ( ( unsigned ) FrameIdx < MinCSFrameIndex ) MinCSFrameIndex = FrameIdx ; if ( ( unsigned ) FrameIdx > MaxCSFrameIndex ) MaxCSFrameIndex = FrameIdx ; if ( hasFP ( MF ) && AFI -> hasSwiftAsyncContext ( ) && Reg == AArch64 :: FP ) { FrameIdx = MFI . CreateStackObject ( 8 , Alignment , true ) ; AFI -> setSwiftAsyncContextFrameIdx ( FrameIdx ) ; if ( ( unsigned ) FrameIdx < MinCSFrameIndex ) MinCSFrameIndex = FrameIdx ; if ( ( unsigned ) FrameIdx > MaxCSFrameIndex ) MaxCSFrameIndex = FrameIdx ; } } return true ; } </s>

This function will assign callee saved gprs to volatile vector registers for prologue spills when applicable .


<s> bool ARMTargetLowering :: isShuffleMaskLegal ( const SmallVectorImpl < int > & M , EVT VT ) const { if ( VT . getVectorNumElements ( ) == 4 && ( VT . is128BitVector ( ) || VT . is64BitVector ( ) ) ) { unsigned PFIndexes [ 4 ] ; for ( unsigned i = 0 ; i != 4 ; ++ i ) { if ( M [ i ] < 0 ) PFIndexes [ i ] = 8 ; else PFIndexes [ i ] = M [ i ] ; } unsigned PFTableIndex = PFIndexes [ 0 ] * 9 * 9 * 9 + PFIndexes [ 1 ] * 9 * 9 + PFIndexes [ 2 ] * 9 + PFIndexes [ 3 ] ; unsigned PFEntry = PerfectShuffleTable [ PFTableIndex ] ; unsigned Cost = ( PFEntry >> 30 ) ; if ( Cost <= 4 ) return true ; } bool ReverseVEXT , isV_UNDEF ; unsigned Imm , WhichResult ; unsigned EltSize = VT . getScalarSizeInBits ( ) ; return ( EltSize >= 32 || ShuffleVectorSDNode :: isSplatMask ( & M [ 0 ] , VT ) || isVREVMask ( M , VT , 64 ) || isVREVMask ( M , VT , 32 ) || isVREVMask ( M , VT , 16 ) || isVEXTMask ( M , VT , ReverseVEXT , Imm ) || isVTBLMask ( M , VT ) || isNEONTwoResultShuffleMask ( M , VT , WhichResult , isV_UNDEF ) || ( ( VT == MVT :: v8i16 || VT == MVT :: v16i8 ) && isReverseMask ( M , VT ) ) ) ; } </s>

Targets can use this to indicate that they only support some VECTOR_SHUFFLE operations , those with specific masks .


<s> void setError ( unsigned e , unsigned r = Hexagon :: NoRegister ) { s . Error = e ; s . Register = r ; } </s>


<s>
void
R600SchedStrategy
::
releaseTopNode
(
SUnit
*
SU
)
{
DEBUG
(
dbgs
(
)
<<
"Top Releasing "
;
SU
->
dump
(
DAG
)
;
)
;
}
</s>

SU has had all predecessor dependencies resolved .


<s> bool X86TargetLowering :: getTgtMemIntrinsic ( IntrinsicInfo & Info , const CallInst & I , MachineFunction & MF , unsigned Intrinsic ) const { const IntrinsicData * IntrData = getIntrinsicWithChain ( Intrinsic ) ; if ( ! IntrData ) return false ; Info . flags = MachineMemOperand :: MONone ; Info . offset = 0 ; switch ( IntrData -> Type ) { case TRUNCATE_TO_MEM_VI8 : case TRUNCATE_TO_MEM_VI16 : case TRUNCATE_TO_MEM_VI32 : { Info . opc = ISD :: INTRINSIC_VOID ; Info . ptrVal = I . getArgOperand ( 0 ) ; MVT VT = MVT :: getVT ( I . getArgOperand ( 1 ) -> getType ( ) ) ; MVT ScalarVT = MVT :: INVALID_SIMPLE_VALUE_TYPE ; if ( IntrData -> Type == TRUNCATE_TO_MEM_VI8 ) ScalarVT = MVT :: i8 ; else if ( IntrData -> Type == TRUNCATE_TO_MEM_VI16 ) ScalarVT = MVT :: i16 ; else if ( IntrData -> Type == TRUNCATE_TO_MEM_VI32 ) ScalarVT = MVT :: i32 ; Info . memVT = MVT :: getVectorVT ( ScalarVT , VT . getVectorNumElements ( ) ) ; Info . align = 1 ; Info . flags |= MachineMemOperand :: MOStore ; break ; } case GATHER : case GATHER_AVX2 : { Info . opc = ISD :: INTRINSIC_W_CHAIN ; Info . ptrVal = nullptr ; MVT DataVT = MVT :: getVT ( I . getType ( ) ) ; MVT IndexVT = MVT :: getVT ( I . getArgOperand ( 2 ) -> getType ( ) ) ; unsigned NumElts = std :: min ( DataVT . getVectorNumElements ( ) , IndexVT . getVectorNumElements ( ) ) ; Info . memVT = MVT :: getVectorVT ( DataVT . getVectorElementType ( ) , NumElts ) ; Info . align = 1 ; Info . flags |= MachineMemOperand :: MOLoad ; break ; } case SCATTER : { Info . opc = ISD :: INTRINSIC_VOID ; Info . ptrVal = nullptr ; MVT DataVT = MVT :: getVT ( I . getArgOperand ( 3 ) -> getType ( ) ) ; MVT IndexVT = MVT :: getVT ( I . getArgOperand ( 2 ) -> getType ( ) ) ; unsigned NumElts = std :: min ( DataVT . getVectorNumElements ( ) , IndexVT . getVectorNumElements ( ) ) ; Info . memVT = MVT :: getVectorVT ( DataVT . getVectorElementType ( ) , NumElts ) ; Info . align = 1 ; Info . flags |= MachineMemOperand :: MOStore ; break ; } default : return false ; } return true ; } </s>

Given an intrinsic , checks if on the target the intrinsic will need to map to a MemIntrinsicNode ( touches memory ) .


<s> DecodeStatus Mips64Disassembler :: getInstruction ( MCInst & instr , uint64_t & Size , const MemoryObject & Region , uint64_t Address , raw_ostream & vStream , raw_ostream & cStream ) const { uint32_t Insn ; DecodeStatus Result = readInstruction32 ( Region , Address , Size , Insn , isBigEndian ) ; if ( Result == MCDisassembler :: Fail ) return MCDisassembler :: Fail ; Result = decodeInstruction ( DecoderTableMips6432 , instr , Insn , Address , this , STI ) ; if ( Result != MCDisassembler :: Fail ) { Size = 4 ; return Result ; } Result = decodeInstruction ( DecoderTableMips32 , instr , Insn , Address , this , STI ) ; if ( Result != MCDisassembler :: Fail ) { Size = 4 ; return Result ; } return MCDisassembler :: Fail ; } </s>

Returns the disassembly of a single instruction .


<s> int d30v_trampoline_size ( ) { return 16 ; } </s>

A C expression for the size in bytes of the trampoline , as an integer .


<s> TargetPassConfig * ARCTargetMachine :: createPassConfig ( PassManagerBase & PM ) { return new ARCPassConfig ( * this , PM ) ; } </s>

Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of CodeGen passes .


<s> bool isFPImm ( ) const { return Kind == k_FPImmediate ; } </s>

isFPImm - Tests if this is a MO_FPImmediate operand .


<s>
SUnit
*
ConvergingVLIWScheduler
::
pickNodeBidrectional
(
bool
&
IsTopNode
)
{
if
(
SUnit
*
SU
=
Bot
.
pickOnlyChoice
(
)
)
{
DEBUG
(
dbgs
(
)
<<
"Picked only Bottom\n"
)
;
IsTopNode
=
false
;
return
SU
;
}
if
(
SUnit
*
SU
=
Top
.
pickOnlyChoice
(
)
)
{
DEBUG
(
dbgs
(
)
<<
"Picked only Top\n"
)
;
IsTopNode
=
true
;
return
SU
;
}
SchedCandidate
BotCand
;
CandResult
BotResult
=
pickNodeFromQueue
(
Bot
,
DAG
->
getBotRPTracker
(
)
,
BotCand
)
;
assert
(
BotResult
!=
NoCand
&&
"failed to find the first candidate"
)
;
if
(
BotResult
==
SingleExcess
||
BotResult
==
SingleCritical
)
{
DEBUG
(
dbgs
(
)
<<
"Prefered Bottom Node\n"
)
;
IsTopNode
=
false
;
return
BotCand
.
SU
;
}
SchedCandidate
TopCand
;
CandResult
TopResult
=
pickNodeFromQueue
(
Top
,
DAG
->
getTopRPTracker
(
)
,
TopCand
)
;
assert
(
TopResult
!=
NoCand
&&
"failed to find the first candidate"
)
;
if
(
TopResult
==
SingleExcess
||
TopResult
==
SingleCritical
)
{
DEBUG
(
dbgs
(
)
<<
"Prefered Top Node\n"
)
;
IsTopNode
=
true
;
return
TopCand
.
SU
;
}
if
(
BotResult
==
SingleMax
)
{
DEBUG
(
dbgs
(
)
<<
"Prefered Bottom Node SingleMax\n"
)
;
IsTopNode
=
false
;
return
BotCand
.
SU
;
}
if
(
TopResult
==
SingleMax
)
{
DEBUG
(
dbgs
(
)
<<
"Prefered Top Node SingleMax\n"
)
;
IsTopNode
=
true
;
return
TopCand
.
SU
;
}
if
(
TopCand
.
SCost
>
BotCand
.
SCost
)
{
DEBUG
(
dbgs
(
)
<<
"Prefered Top Node Cost\n"
)
;
IsTopNode
=
true
;
return
TopCand
.
SU
;
}
DEBUG
(
dbgs
(
)
<<
"Prefered Bottom in Node order\n"
)
;
IsTopNode
=
false
;
return
BotCand
.
SU
;
}
</s>

Pick the best candidate node from either the top or bottom queue .

Hexagon
"Picked only Bottom\n"
"Picked only Top\n"
"failed to find the first candidate"
"Prefered Bottom Node\n"
"failed to find the first candidate"
"Prefered Top Node\n"
"Prefered Bottom Node SingleMax\n"
"Prefered Top Node SingleMax\n"
"Prefered Top Node Cost\n"
"Prefered Bottom in Node order\n"


<s> bool HexagonConstEvaluator :: evaluate ( const MachineInstr & BrI , const CellMap & Inputs , SetVector < const MachineBasicBlock * > & Targets , bool & FallsThru ) { unsigned Opc = BrI . getOpcode ( ) ; bool SimpleBranch = false ; bool Negated = false ; switch ( Opc ) { case Hexagon :: J2_jumpf : case Hexagon :: J2_jumpfnew : case Hexagon :: J2_jumpfnewpt : Negated = true ; LLVM_FALLTHROUGH ; case Hexagon :: J2_jumpt : case Hexagon :: J2_jumptnew : case Hexagon :: J2_jumptnewpt : SimpleBranch = true ; break ; case Hexagon :: J2_jump : Targets . insert ( BrI . getOperand ( 0 ) . getMBB ( ) ) ; FallsThru = false ; return true ; default : Undetermined : FallsThru = ! BrI . isUnconditionalBranch ( ) ; return false ; } if ( SimpleBranch ) { const MachineOperand & MD = BrI . getOperand ( 0 ) ; Register PR ( MD ) ; if ( PR . SubReg ) goto Undetermined ; assert ( Inputs . has ( PR . Reg ) ) ; const LatticeCell & PredC = Inputs . get ( PR . Reg ) ; if ( PredC . isBottom ( ) ) goto Undetermined ; uint32_t Props = PredC . properties ( ) ; bool CTrue = false , CFalse = false ; if ( Props & ConstantProperties :: Zero ) CFalse = true ; else if ( Props & ConstantProperties :: NonZero ) CTrue = true ; if ( ! CTrue && ! CFalse ) goto Undetermined ; const MachineBasicBlock * BranchTarget = BrI . getOperand ( 1 ) . getMBB ( ) ; FallsThru = false ; if ( ( ! Negated && CTrue ) || ( Negated && CFalse ) ) Targets . insert ( BranchTarget ) ; else if ( ( ! Negated && CFalse ) || ( Negated && CTrue ) ) FallsThru = true ; else goto Undetermined ; } return true ; } </s>

evaluate - Evaluate Expr and append the resulting set to Elts .


<s>
void
MipsRegisterInfo
::
eliminateFrameIndex
(
MachineBasicBlock
::
iterator
II
,
int
SPAdj
,
unsigned
FIOperandNum
,
RegScavenger
*
RS
)
const
{
MachineInstr
&
MI
=
*
II
;
MachineFunction
&
MF
=
*
MI
.
getParent
(
)
->
getParent
(
)
;
DEBUG
(
errs
(
)
<<
"\nFunction : "
<<
MF
.
getName
(
)
<<
"\n"
;
errs
(
)
<<
"<--------->\n"
<<
MI
)
;
int
FrameIndex
=
MI
.
getOperand
(
FIOperandNum
)
.
getIndex
(
)
;
uint64_t
stackSize
=
MF
.
getFrameInfo
(
)
->
getStackSize
(
)
;
int64_t
spOffset
=
MF
.
getFrameInfo
(
)
->
getObjectOffset
(
FrameIndex
)
;
DEBUG
(
errs
(
)
<<
"FrameIndex : "
<<
FrameIndex
<<
"\n"
<<
"spOffset   : "
<<
spOffset
<<
"\n"
<<
"stackSize  : "
<<
stackSize
<<
"\n"
)
;
eliminateFI
(
MI
,
FIOperandNum
,
FrameIndex
,
stackSize
,
spOffset
)
;
}
</s>

This method must be overriden to eliminate abstract frame indices from instructions which may use them .

Mips
Mips
"\nFunction : "
"\n"
"<--------->\n"
"FrameIndex : "
"\n"
"spOffset   : "
"\n"
"stackSize  : "
"\n"


<s>
const
char
*
host_detect_local_cpu
(
int
argc
,
const
char
*
*
argv
)
{
const
char
*
val
=
;
char
buf
[
128
]
;
FILE
*
f
=
;
bool
arch
;
const
struct
vendor_cpu
*
cpu_table
=
;
if
(
argc
<
1
)
goto
not_found
;
arch
=
strcmp
(
argv
[
0
]
,
"arch"
)
==
0
;
if
(
!
arch
&&
strcmp
(
argv
[
0
]
,
"cpu"
)
!=
0
&&
strcmp
(
argv
[
0
]
,
"tune"
)
)
goto
not_found
;
f
=
fopen
(
"/proc/cpuinfo"
,
"r"
)
;
if
(
f
==
)
goto
not_found
;
while
(
fgets
(
buf
,
sizeof
(
buf
)
,
f
)
!=
)
{
if
(
strncmp
(
buf
,
"CPU implementer"
,
sizeof
(
"CPU implementer"
)
1
)
==
0
)
{
int
i
;
for
(
i
=
0
;
vendors
[
i
]
.
vendor_no
!=
;
i
++
)
if
(
strstr
(
buf
,
vendors
[
i
]
.
vendor_no
)
!=
)
{
cpu_table
=
vendors
[
i
]
.
vendor_parts
;
break
;
}
}
if
(
strncmp
(
buf
,
"CPU part"
,
sizeof
(
"CPU part"
)
1
)
==
0
)
{
int
i
;
if
(
cpu_table
==
)
goto
not_found
;
for
(
i
=
0
;
cpu_table
[
i
]
.
part_no
!=
;
i
++
)
if
(
strstr
(
buf
,
cpu_table
[
i
]
.
part_no
)
!=
)
{
val
=
arch
cpu_table
[
i
]
.
arch_name
:
cpu_table
[
i
]
.
cpu_name
;
break
;
}
break
;
}
}
if
(
val
)
{
fclose
(
f
)
;
return
concat
(
"-m"
,
argv
[
0
]
,
"="
,
val
,
)
;
}
not_found
:
{
unsigned
int
i
;
unsigned
int
opt
;
const
char
*
search
[
]
=
{
,
"arch"
}
;
if
(
f
)
fclose
(
f
)
;
search
[
0
]
=
argv
[
0
]
;
for
(
opt
=
0
;
opt
<
ARRAY_SIZE
(
search
)
;
opt
++
)
for
(
i
=
0
;
i
<
ARRAY_SIZE
(
configure_default_options
)
;
i
++
)
if
(
strcmp
(
configure_default_options
[
i
]
.
name
,
search
[
opt
]
)
==
0
)
return
concat
(
"-m"
,
search
[
opt
]
,
"="
,
configure_default_options
[
i
]
.
value
,
)
;
return
;
}
}
</s>

This will be called by the spec parser in gcc.cc when it sees a % : local_cpu_detect ( args ) construct . Currently it will be called with either `` cpu '' or `` tune '' as argument depending on if -mcpu=native or -mtune=native is to be substituted . It returns a string containing new command line parameters to be put at the place of the above two options , depending on what CPU this is executed . E.g . `` -mcpu=ultrasparc3 '' on an UltraSPARC III for -mcpu=native . If the routine ca n't detect a known processor , the -mcpu or -mtune option is discarded . ARGC and ARGV are set depending on the actual arguments given in the spec .


<s> const uint32_t * SystemZRegisterInfo :: getCallPreservedMask ( const MachineFunction & MF , CallingConv :: ID CC ) const { return CSR_SystemZ_RegMask ; } </s>

Return a mask of call-preserved registers for the given calling convention on the current function .


<s> virtual const XCoreInstrInfo * getInstrInfo ( ) const { return & InstrInfo ; } </s>


<s> static tree visium_md_asm_clobbers ( tree outputs ATTRIBUTE_UNUSED , tree inputs ATTRIBUTE_UNUSED , tree clobbers ) { const char * flags = reg_names [ FLAGS_REGNUM ] ; return tree_cons ( NULL_TREE , build_string ( strlen ( flags ) , flags ) , clobbers ) ; } </s>

Prepend to CLOBBERS hard registers that are automatically clobbered for an asm We do this for the FLAGS to maintain source compatibility with the original cc0-based compiler .


<s> rtx extract_nth_access_reg ( rtx_insn * insn , int index ) { switch ( GET_CODE ( PATTERN ( insn ) ) ) { case PARALLEL : return extract_nth_lmsw_access_reg ( insn , index ) ; case SET : return extract_nth_ls2_access_reg ( insn , index ) ; default : gcc_unreachable ( ) ; } } </s>

Returns the register operated by the nth load/store operation in the real micro-operation accessing order .


<s> unsigned NVPTXRegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { return NVPTX :: VRFrame ; } </s>


<s> rtx tilegx_emit_conditional_move ( rtx cmp ) { return tilegx_emit_cc_test ( GET_CODE ( cmp ) , XEXP ( cmp , 0 ) , XEXP ( cmp , 1 ) , GET_MODE ( XEXP ( cmp , 0 ) ) , true ) ; } </s>


<s>
static
int
rs6000_arg_partial_bytes
(
cumulative_args_t
cum_v
,
machine_mode
mode
,
tree
type
,
bool
named
)
{
CUMULATIVE_ARGS
*
cum
=
get_cumulative_args
(
cum_v
)
;
bool
passed_in_gprs
=
true
;
int
ret
=
0
;
int
align_words
;
machine_mode
elt_mode
;
int
n_elts
;
rs6000_discover_homogeneous_aggregate
(
mode
,
type
,
&
elt_mode
,
&
n_elts
)
;
if
(
DEFAULT_ABI
==
ABI_V4
)
return
0
;
if
(
USE_ALTIVEC_FOR_ARG_P
(
cum
,
elt_mode
,
named
)
)
{
if
(
TARGET_64BIT
&&
!
cum
->
prototype
&&
(
!
cum
->
libcall
||
!
FLOAT128_VECTOR_P
(
elt_mode
)
)
)
return
0
;
passed_in_gprs
=
false
;
if
(
cum
->
vregno
+
n_elts
>
ALTIVEC_ARG_MAX_REG
+
1
)
ret
=
(
ALTIVEC_ARG_MAX_REG
+
1
cum
->
vregno
)
*
16
;
}
if
(
TARGET_MACHO
&&
rs6000_darwin64_struct_check_p
(
mode
,
type
)
)
return
0
;
align_words
=
rs6000_parm_start
(
mode
,
type
,
cum
->
words
)
;
if
(
USE_FP_FOR_ARG_P
(
cum
,
elt_mode
)
)
{
unsigned
long
n_fpreg
=
(
GET_MODE_SIZE
(
elt_mode
)
+
7
)
>>
3
;
if
(
type
&&
(
cum
->
nargs_prototype
<=
0
||
(
(
DEFAULT_ABI
==
ABI_AIX
||
DEFAULT_ABI
==
ABI_ELFv2
)
&&
TARGET_XL_COMPAT
&&
align_words
>=
GP_ARG_NUM_REG
)
)
)
return
0
;
passed_in_gprs
=
false
;
if
(
cum
->
fregno
+
n_elts
*
n_fpreg
>
FP_ARG_MAX_REG
+
1
)
{
int
fpr
=
(
(
FP_ARG_MAX_REG
+
1
cum
->
fregno
)
*
MIN
(
8
,
GET_MODE_SIZE
(
elt_mode
)
)
)
;
int
fpr_words
=
fpr
/
(
TARGET_32BIT
4
:
8
)
;
if
(
align_words
+
fpr_words
<
GP_ARG_NUM_REG
)
passed_in_gprs
=
true
;
else
ret
=
fpr
;
}
}
if
(
passed_in_gprs
&&
align_words
<
GP_ARG_NUM_REG
&&
GP_ARG_NUM_REG
<
align_words
+
rs6000_arg_size
(
mode
,
type
)
)
ret
=
(
GP_ARG_NUM_REG
align_words
)
*
(
TARGET_32BIT
4
:
8
)
;
if
(
ret
!=
0
&&
TARGET_DEBUG_ARG
)
fprintf
(
stderr
,
"rs6000_arg_partial_bytes: %d\n"
,
ret
)
;
return
ret
;
}
</s>

For an arg passed partly in registers and partly in memory , this is the number of bytes passed in registers . For args passed entirely in registers or entirely in memory , zero . When an arg is described by a PARALLEL , perhaps using more than one register type , this function returns the number of bytes used by the first element of the PARALLEL .


<s> rtx get_deferred_plabel ( rtx symbol ) { const char * fname = XSTR ( symbol , 0 ) ; size_t i ; for ( i = 0 ; i < n_deferred_plabels ; i ++ ) if ( strcmp ( fname , XSTR ( deferred_plabels [ i ] . symbol , 0 ) ) == 0 ) break ; if ( deferred_plabels == NULL || i == n_deferred_plabels ) { tree id ; if ( deferred_plabels == 0 ) deferred_plabels = ( struct deferred_plabel * ) ggc_alloc ( sizeof ( struct deferred_plabel ) ) ; else deferred_plabels = ( struct deferred_plabel * ) ggc_realloc ( deferred_plabels , ( ( n_deferred_plabels + 1 ) * sizeof ( struct deferred_plabel ) ) ) ; i = n_deferred_plabels ++ ; deferred_plabels [ i ] . internal_label = gen_label_rtx ( ) ; deferred_plabels [ i ] . symbol = symbol ; id = maybe_get_identifier ( targetm . strip_name_encoding ( fname ) ) ; if ( id ) mark_referenced ( id ) ; } return deferred_plabels [ i ] . internal_label ; } </s>

Search the deferred plabel list for SYMBOL and return its internal label . If an entry for SYMBOL is not found , a new entry is created .


<s> bool SPUPassConfig :: addPreEmitPass ( ) { typedef llvm :: FunctionPass * ( * BuilderFunc ) ( const char * ) ; BuilderFunc schedulerCreator = ( BuilderFunc ) ( intptr_t ) sys :: DynamicLibrary :: SearchForAddressOfSymbol ( "createTCESchedulerPass" ) ; if ( schedulerCreator != NULL ) addPass ( schedulerCreator ( "cellspu" ) ) ; addPass ( createSPUNopFillerPass ( getSPUTargetMachine ( ) ) ) ; return true ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .

CellSPU SPU "createTCESchedulerPass" "cellspu" SPU SPU


<s> static void ix86_default_align ( struct gcc_options * opts ) { if ( opts -> x_flag_align_loops && ! opts -> x_str_align_loops ) opts -> x_str_align_loops = processor_cost_table [ ix86_tune ] -> align_loop ; if ( opts -> x_flag_align_jumps && ! opts -> x_str_align_jumps ) opts -> x_str_align_jumps = processor_cost_table [ ix86_tune ] -> align_jump ; if ( opts -> x_flag_align_labels && ! opts -> x_str_align_labels ) opts -> x_str_align_labels = processor_cost_table [ ix86_tune ] -> align_label ; if ( opts -> x_flag_align_functions && ! opts -> x_str_align_functions ) opts -> x_str_align_functions = processor_cost_table [ ix86_tune ] -> align_func ; } </s>

Default align_ * from the processor table .


<s>
unsigned
MipsCodeEmitter
::
getJumpTargetOpValue
(
const
MachineInstr
&
MI
,
unsigned
OpNo
)
const
{
MachineOperand
MO
=
MI
.
getOperand
(
OpNo
)
;
if
(
MO
.
isGlobal
(
)
)
emitGlobalAddress
(
MO
.
getGlobal
(
)
,
getRelocation
(
MI
,
MO
)
,
true
)
;
else
if
(
MO
.
isSymbol
(
)
)
emitExternalSymbolAddress
(
MO
.
getSymbolName
(
)
,
getRelocation
(
MI
,
MO
)
)
;
else
if
(
MO
.
isMBB
(
)
)
emitMachineBasicBlock
(
MO
.
getMBB
(
)
,
getRelocation
(
MI
,
MO
)
)
;
else
llvm_unreachable
(
"Unexpected jump target operand kind."
)
;
return
0
;
}
</s>

getJumpTargetOpValue - Return binary encoding of the jump target operand .

Mips
Mips
"Unexpected jump target operand kind."
0


<s> bool ARMInstPrinter :: applyTargetSpecificCLOption ( StringRef Opt ) { if ( Opt == "reg-names-std" ) { DefaultAltIdx = ARM :: NoRegAltName ; return true ; } if ( Opt == "reg-names-raw" ) { DefaultAltIdx = ARM :: RegNamesRaw ; return true ; } return false ; } </s>

Customize the printer according to a command line option .

ARM ARM "reg-names-std" ARM::NoRegAltName "reg-names-raw" ARM::RegNamesRaw


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . addRequired < MachineLoopInfo > ( ) ; AU . addRequired < LiveIntervals > ( ) ; AU . addRequired < VirtRegMap > ( ) ; AU . addRequired < LiveRegMatrix > ( ) ; AU . setPreservesAll ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> unsigned postKnownBits ( unsigned LogAlign = 0 ) const { return std :: max ( std :: max ( unsigned ( PostAlign ) , LogAlign ) , internalKnownBits ( ) ) ; } </s>

Compute the number of known low bits of postOffset .


<s>
void
dump
(
)
{
errs
(
)
<<
"SystemZAddressingMode "
<<
this
<<
'\n'
;
errs
(
)
<<
" Base "
;
if
(
Base
.
getNode
(
)
!=
0
)
Base
.
getNode
(
)
->
dump
(
)
;
else
errs
(
)
<<
"null\n"
;
if
(
hasIndexField
(
)
)
{
errs
(
)
<<
" Index "
;
if
(
Index
.
getNode
(
)
!=
0
)
Index
.
getNode
(
)
->
dump
(
)
;
else
errs
(
)
<<
"null\n"
;
}
errs
(
)
<<
" Disp "
<<
Disp
;
if
(
IncludesDynAlloc
)
errs
(
)
<<
" + ADJDYNALLOC"
;
errs
(
)
<<
'\n'
;
}
</s>

Dump the plan to stderr ( for debugging ) .

SystemZ
"SystemZAddressingMode "
" Base "
0
"null\n"
" Index "
0
"null\n"
" Disp "
" + ADJDYNALLOC"


<s> void Z80MCCodeEmitter :: encodeInstruction ( const MCInst & MC , raw_ostream & OS , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { llvm_unreachable ( "Unimplemented" ) ; } </s>

Encode the given Inst to bytes and append to CB .


<s> unsigned MipsFastISel :: fastMaterializeConstant ( const Constant * C ) { EVT CEVT = TLI . getValueType ( DL , C -> getType ( ) , true ) ; if ( ! CEVT . isSimple ( ) ) return 0 ; MVT VT = CEVT . getSimpleVT ( ) ; if ( const ConstantFP * CFP = dyn_cast < ConstantFP > ( C ) ) return ( UnsupportedFPMode ) ? 0 : materializeFP ( CFP , VT ) ; else if ( const GlobalValue * GV = dyn_cast < GlobalValue > ( C ) ) return materializeGV ( GV , VT ) ; else if ( isa < ConstantInt > ( C ) ) return materializeInt ( C , VT ) ; return 0 ; } </s>

Emit a constant in a register using target-specific logic , such as constant pool loads .


<s> int crx_memory_move_cost ( enum machine_mode mode , enum reg_class class ATTRIBUTE_UNUSED , int in ATTRIBUTE_UNUSED ) { if ( reg_classes_intersect_p ( class , GENERAL_REGS ) ) { return 4 * HARD_REGNO_NREGS ( 0 , mode ) ; } else if ( reg_classes_intersect_p ( class , HILO_REGS ) ) { return ( REGISTER_MOVE_COST ( mode , in ? GENERAL_REGS : HILO_REGS , in ? HILO_REGS : GENERAL_REGS ) + 4 ) * HARD_REGNO_NREGS ( 0 , mode ) ; } else { return 100 ; } } </s>

Return the cost of moving data of mode MODE between a register of class * CLASS and memory ; IN is zero if the value is to be written to memory , * nonzero if it is to be read in . This cost is relative to those in * REGISTER_MOVE_COST .


<s> static bool ix86_hard_regno_call_part_clobbered ( unsigned int regno , machine_mode mode ) { return SSE_REGNO_P ( regno ) && GET_MODE_SIZE ( mode ) > 16 ; } </s>

Implement TARGET_HARD_REGNO_CALL_PART_CLOBBERED . The only ABI that saves SSE registers across calls is Win64 ( thus no need to check the current ABI here ) , and with AVX enabled Win64 only guarantees that the low 16 bytes are saved .


<s> SDNode * PPCDAGToDAGISel :: getGlobalBaseReg ( ) { if ( ! GlobalBaseReg ) { const TargetInstrInfo & TII = * TM . getInstrInfo ( ) ; MachineBasicBlock & FirstMBB = MF -> front ( ) ; MachineBasicBlock :: iterator MBBI = FirstMBB . begin ( ) ; DebugLoc dl ; if ( PPCLowering . getPointerTy ( ) == MVT :: i32 ) { GlobalBaseReg = RegInfo -> createVirtualRegister ( PPC :: GPRCRegisterClass ) ; BuildMI ( FirstMBB , MBBI , dl , TII . get ( PPC :: MovePCtoLR ) ) ; BuildMI ( FirstMBB , MBBI , dl , TII . get ( PPC :: MFLR ) , GlobalBaseReg ) ; } else { GlobalBaseReg = RegInfo -> createVirtualRegister ( PPC :: G8RCRegisterClass ) ; BuildMI ( FirstMBB , MBBI , dl , TII . get ( PPC :: MovePCtoLR8 ) ) ; BuildMI ( FirstMBB , MBBI , dl , TII . get ( PPC :: MFLR8 ) , GlobalBaseReg ) ; } } return CurDAG -> getRegister ( GlobalBaseReg , PPCLowering . getPointerTy ( ) ) . getNode ( ) ; } </s>

getGlobalBaseReg - Return a virtual register initialized with the the global base register value .


<s>
static
void
frv_function_prologue
(
FILE
*
file
)
{
if
(
frv_stack_info
(
)
->
total_size
==
0
&&
frv_function_contains_far_jump
(
)
)
{
rtx_insn
*
insn
;
gcc_assert
(
!
df_regs_ever_live_p
(
GPR_FIRST
+
3
)
)
;
fprintf
(
file
,
"\tmovsg lr,gr3\n"
)
;
for
(
insn
=
get_insns
(
)
;
insn
!=
;
insn
=
NEXT_INSN
(
insn
)
)
if
(
JUMP_P
(
insn
)
)
{
rtx
pattern
=
PATTERN
(
insn
)
;
if
(
GET_CODE
(
pattern
)
==
PARALLEL
&&
XVECLEN
(
pattern
,
0
)
>=
2
&&
GET_CODE
(
XVECEXP
(
pattern
,
0
,
0
)
)
==
RETURN
&&
GET_CODE
(
XVECEXP
(
pattern
,
0
,
1
)
)
==
USE
)
{
rtx
address
=
XEXP
(
XVECEXP
(
pattern
,
0
,
1
)
,
0
)
;
if
(
GET_CODE
(
address
)
==
REG
&&
REGNO
(
address
)
==
LR_REGNO
)
SET_REGNO
(
address
,
GPR_FIRST
+
3
)
;
}
}
}
frv_pack_insns
(
)
;
memset
(
frv_nops
,
0
,
sizeof
(
frv_nops
)
)
;
}
</s>

For the FRV , this function makes sure that a function with far jumps will return correctly . It also does the VLIW packing .


<s> rtx mmix_function_arg ( const CUMULATIVE_ARGS * argsp , enum machine_mode mode , tree type , int named ATTRIBUTE_UNUSED , int incoming ) { if ( type == void_type_node ) return ( argsp -> regs < MMIX_MAX_ARGS_IN_REGS ) ? gen_rtx_REG ( mode , ( incoming ? MMIX_FIRST_INCOMING_ARG_REGNUM : MMIX_FIRST_ARG_REGNUM ) + argsp -> regs ) : NULL_RTX ; return ( argsp -> regs < MMIX_MAX_ARGS_IN_REGS && ! targetm . calls . must_pass_in_stack ( mode , type ) && ( GET_MODE_BITSIZE ( mode ) <= 64 || argsp -> lib || TARGET_LIBFUNC ) ) ? gen_rtx_REG ( mode , ( incoming ? MMIX_FIRST_INCOMING_ARG_REGNUM : MMIX_FIRST_ARG_REGNUM ) + argsp -> regs ) : NULL_RTX ; } </s>

Return an rtx for a function argument to go in a register , and 0 for one that must go on stack .


<s> bool s390_output_addr_const_extra ( FILE * file , rtx x ) { if ( GET_CODE ( x ) == UNSPEC && XVECLEN ( x , 0 ) == 1 ) switch ( XINT ( x , 1 ) ) { case UNSPEC_GOTENT : output_addr_const ( file , XVECEXP ( x , 0 , 0 ) ) ; fprintf ( file , "@GOTENT" ) ; return true ; case UNSPEC_GOT : output_addr_const ( file , XVECEXP ( x , 0 , 0 ) ) ; fprintf ( file , "@GOT" ) ; return true ; case UNSPEC_GOTOFF : output_addr_const ( file , XVECEXP ( x , 0 , 0 ) ) ; fprintf ( file , "@GOTOFF" ) ; return true ; case UNSPEC_PLT : output_addr_const ( file , XVECEXP ( x , 0 , 0 ) ) ; fprintf ( file , "@PLT" ) ; return true ; case UNSPEC_PLTOFF : output_addr_const ( file , XVECEXP ( x , 0 , 0 ) ) ; fprintf ( file , "@PLTOFF" ) ; return true ; case UNSPEC_TLSGD : output_addr_const ( file , XVECEXP ( x , 0 , 0 ) ) ; fprintf ( file , "@TLSGD" ) ; return true ; case UNSPEC_TLSLDM : assemble_name ( file , get_some_local_dynamic_name ( ) ) ; fprintf ( file , "@TLSLDM" ) ; return true ; case UNSPEC_DTPOFF : output_addr_const ( file , XVECEXP ( x , 0 , 0 ) ) ; fprintf ( file , "@DTPOFF" ) ; return true ; case UNSPEC_NTPOFF : output_addr_const ( file , XVECEXP ( x , 0 , 0 ) ) ; fprintf ( file , "@NTPOFF" ) ; return true ; case UNSPEC_GOTNTPOFF : output_addr_const ( file , XVECEXP ( x , 0 , 0 ) ) ; fprintf ( file , "@GOTNTPOFF" ) ; return true ; case UNSPEC_INDNTPOFF : output_addr_const ( file , XVECEXP ( x , 0 , 0 ) ) ; fprintf ( file , "@INDNTPOFF" ) ; return true ; } return false ; } </s>

Output machine-dependent UNSPECs occurring in address constant X in assembler syntax to stdio stream FILE . Returns true if the constant X could be recognized , false otherwise .


<s> unsigned getRegister ( ) const { assert ( ! IsStack ) ; return Register ; } </s>

Return the specified register in the class .


<s> void X86FrameLowering :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { const TargetInstrInfo & TII = * MF . getSubtarget ( ) . getInstrInfo ( ) ; const X86RegisterInfo & RegInfo = * static_cast < const X86RegisterInfo * > ( MF . getSubtarget ( ) . getRegisterInfo ( ) ) ; unsigned StackPtr = RegInfo . getStackRegister ( ) ; bool reseveCallFrame = hasReservedCallFrame ( MF ) ; int Opcode = I -> getOpcode ( ) ; bool isDestroy = Opcode == TII . getCallFrameDestroyOpcode ( ) ; const X86Subtarget & STI = MF . getTarget ( ) . getSubtarget < X86Subtarget > ( ) ; bool IsLP64 = STI . isTarget64BitLP64 ( ) ; DebugLoc DL = I -> getDebugLoc ( ) ; uint64_t Amount = ! reseveCallFrame ? I -> getOperand ( 0 ) . getImm ( ) : 0 ; uint64_t CalleeAmt = isDestroy ? I -> getOperand ( 1 ) . getImm ( ) : 0 ; I = MBB . erase ( I ) ; if ( ! reseveCallFrame ) { if ( Amount == 0 ) return ; unsigned StackAlign = MF . getTarget ( ) . getSubtargetImpl ( ) -> getFrameLowering ( ) -> getStackAlignment ( ) ; Amount = ( Amount + StackAlign - 1 ) / StackAlign * StackAlign ; MachineInstr * New = nullptr ; if ( Opcode == TII . getCallFrameSetupOpcode ( ) ) { New = BuildMI ( MF , DL , TII . get ( getSUBriOpcode ( IsLP64 , Amount ) ) , StackPtr ) . addReg ( StackPtr ) . addImm ( Amount ) ; } else { assert ( Opcode == TII . getCallFrameDestroyOpcode ( ) ) ; Amount -= CalleeAmt ; if ( Amount ) { unsigned Opc = getADDriOpcode ( IsLP64 , Amount ) ; New = BuildMI ( MF , DL , TII . get ( Opc ) , StackPtr ) . addReg ( StackPtr ) . addImm ( Amount ) ; } } if ( New ) { New -> getOperand ( 3 ) . setIsDead ( ) ; MBB . insert ( I , New ) ; } return ; } if ( Opcode == TII . getCallFrameDestroyOpcode ( ) && CalleeAmt ) { unsigned Opc = getSUBriOpcode ( IsLP64 , CalleeAmt ) ; MachineInstr * New = BuildMI ( MF , DL , TII . get ( Opc ) , StackPtr ) . addReg ( StackPtr ) . addImm ( CalleeAmt ) ; New -> getOperand ( 3 ) . setIsDead ( ) ; MachineBasicBlock :: iterator B = MBB . begin ( ) ; while ( I != B && ! std :: prev ( I ) -> isCall ( ) ) -- I ; MBB . insert ( I , New ) ; } } </s>

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .


<s> void SystemZFrameLowering :: determineCalleeSaves ( MachineFunction & MF , BitVector & SavedRegs , RegScavenger * RS ) const { TargetFrameLowering :: determineCalleeSaves ( MF , SavedRegs , RS ) ; MachineFrameInfo & MFFrame = MF . getFrameInfo ( ) ; const TargetRegisterInfo * TRI = MF . getSubtarget ( ) . getRegisterInfo ( ) ; bool HasFP = hasFP ( MF ) ; SystemZMachineFunctionInfo * MFI = MF . getInfo < SystemZMachineFunctionInfo > ( ) ; bool IsVarArg = MF . getFunction ( ) -> isVarArg ( ) ; if ( IsVarArg ) for ( unsigned I = MFI -> getVarArgsFirstGPR ( ) ; I < SystemZ :: NumArgGPRs ; ++ I ) SavedRegs . set ( SystemZ :: ArgGPRs [ I ] ) ; if ( ! MF . getMMI ( ) . getLandingPads ( ) . empty ( ) ) { SavedRegs . set ( SystemZ :: R6D ) ; SavedRegs . set ( SystemZ :: R7D ) ; } if ( HasFP ) SavedRegs . set ( SystemZ :: R11D ) ; if ( MFFrame . hasCalls ( ) ) SavedRegs . set ( SystemZ :: R14D ) ; const MCPhysReg * CSRegs = TRI -> getCalleeSavedRegs ( & MF ) ; for ( unsigned I = 0 ; CSRegs [ I ] ; ++ I ) { unsigned Reg = CSRegs [ I ] ; if ( SystemZ :: GR64BitRegClass . contains ( Reg ) && SavedRegs . test ( Reg ) ) { SavedRegs . set ( SystemZ :: R15D ) ; break ; } } } </s>

This method determines which of the registers reported by TargetRegisterInfo : :getCalleeSavedRegs ( ) should actually get saved .


<s> rtx pa_return_addr_rtx ( int count , rtx frameaddr ) { rtx label ; rtx rp ; rtx saved_rp ; rtx ins ; HOST_WIDE_INT insns [ 4 ] ; int i , len ; if ( count != 0 ) return NULL_RTX ; rp = get_hard_reg_initial_val ( Pmode , 2 ) ; if ( TARGET_64BIT || TARGET_NO_SPACE_REGS ) return rp ; saved_rp = gen_reg_rtx ( Pmode ) ; emit_move_insn ( saved_rp , rp ) ; ins = copy_to_reg ( gen_rtx_AND ( Pmode , rp , MASK_RETURN_ADDR ) ) ; label = gen_label_rtx ( ) ; if ( TARGET_PA_20 ) { insns [ 0 ] = 0x4bc23fd1 ; insns [ 1 ] = - 398405630 ; len = 2 ; } else { insns [ 0 ] = 0x4bc23fd1 ; insns [ 1 ] = 0x004010a1 ; insns [ 2 ] = 0x00011820 ; insns [ 3 ] = - 532676606 ; len = 4 ; } for ( i = 0 ; i < len ; i ++ ) { rtx op0 = gen_rtx_MEM ( SImode , plus_constant ( Pmode , ins , i * 4 ) ) ; rtx op1 = GEN_INT ( insns [ i ] ) ; emit_cmp_and_jump_insns ( op0 , op1 , NE , NULL , SImode , 0 , label ) ; } emit_move_insn ( saved_rp , gen_rtx_MEM ( Pmode , memory_address ( Pmode , plus_constant ( Pmode , frameaddr , - 24 ) ) ) ) ; emit_label ( label ) ; return saved_rp ; } </s>

Fetch the return address for the frame COUNT steps up from the current frame , after the prologue . FRAMEADDR is the frame pointer of the COUNT frame . We want to ignore any export stub remnants here . To handle this , we examine the code at the return address , and if it is an export stub , we return a memory rtx for the stub return address stored at frame-24 . The value returned is used in two different ways : 1 . To find a function 's caller . 2 . To change the return address for a function . This function handles most instances of case 1 ; however , it will fail if there are two levels of stubs to execute on the return path . The only way I believe that can happen is if the return value needs a parameter relocation , which never happens for C code . This function handles most instances of case 2 ; however , it will fail if we did not originally have stub code on the return path but will need stub code on the new return path . This can happen if the caller & callee are both in the main program , but the new return location is in a shared library .


<s>
SDValue
SparcTargetLowering
::
LowerOperation
(
SDValue
Op
,
SelectionDAG
&
DAG
)
const
{
switch
(
Op
.
getOpcode
(
)
)
{
default
:
llvm_unreachable
(
"Should not custom lower this!"
)
;
case
ISD
::
RETURNADDR
:
return
SDValue
(
)
;
case
ISD
::
FRAMEADDR
:
return
SDValue
(
)
;
case
ISD
::
GlobalTLSAddress
:
llvm_unreachable
(
"TLS not implemented for Sparc."
)
;
case
ISD
::
GlobalAddress
:
return
LowerGlobalAddress
(
Op
,
DAG
)
;
case
ISD
::
ConstantPool
:
return
LowerConstantPool
(
Op
,
DAG
)
;
case
ISD
::
FP_TO_SINT
:
return
LowerFP_TO_SINT
(
Op
,
DAG
)
;
case
ISD
::
SINT_TO_FP
:
return
LowerSINT_TO_FP
(
Op
,
DAG
)
;
case
ISD
::
BR_CC
:
return
LowerBR_CC
(
Op
,
DAG
)
;
case
ISD
::
SELECT_CC
:
return
LowerSELECT_CC
(
Op
,
DAG
)
;
case
ISD
::
VASTART
:
return
LowerVASTART
(
Op
,
DAG
,
*
this
)
;
case
ISD
::
VAARG
:
return
LowerVAARG
(
Op
,
DAG
)
;
case
ISD
::
DYNAMIC_STACKALLOC
:
return
LowerDYNAMIC_STACKALLOC
(
Op
,
DAG
)
;
}
}
</s>

LowerOperation - Provide custom lowering hooks for some operations .

Sparc
Sparc
"Should not custom lower this!"
ISD::RETURNADDR
ISD::FRAMEADDR
ISD::GlobalTLSAddress
"TLS not implemented for Sparc."
ISD::GlobalAddress
ISD::ConstantPool
ISD::FP_TO_SINT
ISD::SINT_TO_FP
ISD::BR_CC
ISD::SELECT_CC
ISD::VASTART
ISD::VAARG
ISD::DYNAMIC_STACKALLOC


<s> bool HexagonFrameLowering :: hasFP ( const MachineFunction & MF ) const { if ( MF . getFunction ( ) . hasFnAttribute ( Attribute :: Naked ) ) return false ; auto & MFI = MF . getFrameInfo ( ) ; auto & HRI = * MF . getSubtarget < HexagonSubtarget > ( ) . getRegisterInfo ( ) ; bool HasExtraAlign = HRI . needsStackRealignment ( MF ) ; bool HasAlloca = MFI . hasVarSizedObjects ( ) ; if ( MF . getTarget ( ) . getOptLevel ( ) == CodeGenOpt :: None ) return true ; if ( HasAlloca || HasExtraAlign ) return true ; if ( MFI . getStackSize ( ) > 0 ) { const TargetMachine & TM = MF . getTarget ( ) ; if ( TM . Options . DisableFramePointerElim ( MF ) || ! EliminateFramePointer ) return true ; if ( EnableStackOVFSanitizer ) return true ; } const auto & HMFI = * MF . getInfo < HexagonMachineFunctionInfo > ( ) ; if ( ( MFI . hasCalls ( ) && ! enableAllocFrameElim ( MF ) ) || HMFI . hasClobberLR ( ) ) return true ; return false ; } </s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .


<s> static rtx sh_delegitimize_address ( rtx orig_x ) { orig_x = delegitimize_mem_from_attrs ( orig_x ) ; rtx x = orig_x ; if ( MEM_P ( x ) ) x = XEXP ( x , 0 ) ; if ( GET_CODE ( x ) == CONST ) { rtx y = XEXP ( x , 0 ) ; if ( GET_CODE ( y ) == UNSPEC ) { if ( XINT ( y , 1 ) == UNSPEC_GOT || XINT ( y , 1 ) == UNSPEC_GOTOFF || XINT ( y , 1 ) == UNSPEC_SYMOFF ) return XVECEXP ( y , 0 , 0 ) ; else if ( XINT ( y , 1 ) == UNSPEC_PCREL_SYMOFF ) { if ( GET_CODE ( XVECEXP ( y , 0 , 0 ) ) == CONST ) { rtx symplt = XEXP ( XVECEXP ( y , 0 , 0 ) , 0 ) ; if ( GET_CODE ( symplt ) == UNSPEC && ( XINT ( symplt , 1 ) == UNSPEC_PLT || XINT ( symplt , 1 ) == UNSPEC_PCREL ) ) return XVECEXP ( symplt , 0 , 0 ) ; } } } } return orig_x ; } </s>

In the name of slightly smaller debug output , and to cater to general assembler lossage , recognize various UNSPEC sequences and turn them back into a direct symbol reference .


<s> bool AArch64RegisterInfo :: regNeedsCFI ( unsigned Reg , unsigned & RegToUseForCFI ) const { if ( AArch64 :: PPRRegClass . contains ( Reg ) ) return false ; if ( AArch64 :: ZPRRegClass . contains ( Reg ) ) { RegToUseForCFI = getSubReg ( Reg , AArch64 :: dsub ) ; for ( int I = 0 ; CSR_AArch64_AAPCS_SaveList [ I ] ; ++ I ) { if ( CSR_AArch64_AAPCS_SaveList [ I ] == RegToUseForCFI ) return true ; } return false ; } RegToUseForCFI = Reg ; return true ; } </s>

Return whether the register needs a CFI entry .


<s> static bool signed_compare_p ( enum rtx_code code ) { return ( code == EQ || code == NE || code == LT || code == LE || code == GT || code == GE ) ; } </s>

Return whether CODE is a signed comparison .


<s>
rtx_code
m68k_output_compare_hi
(
rtx
op0
,
rtx
op1
,
rtx_code
code
)
{
rtx_code
tmp
=
m68k_find_flags_value
(
op0
,
op1
,
code
)
;
if
(
tmp
!=
UNKNOWN
)
return
tmp
;
remember_compare_flags
(
op0
,
op1
)
;
rtx
ops
[
2
]
;
ops
[
0
]
=
op0
;
ops
[
1
]
=
op1
;
if
(
op1
==
const0_rtx
)
output_asm_insn
(
"tst%.w %d0"
,
ops
)
;
else
if
(
GET_CODE
(
op0
)
==
MEM
&&
GET_CODE
(
op1
)
==
MEM
)
output_asm_insn
(
"cmpm%.w %1,%0"
,
ops
)
;
else
if
(
(
REG_P
(
op1
)
&&
!
ADDRESS_REG_P
(
op1
)
)
||
(
!
REG_P
(
op0
)
&&
GET_CODE
(
op0
)
!=
MEM
)
)
{
output_asm_insn
(
"cmp%.w %d0,%d1"
,
ops
)
;
std
::
swap
(
flags_compare_op0
,
flags_compare_op1
)
;
return
swap_condition
(
code
)
;
}
else
output_asm_insn
(
"cmp%.w %d1,%d0"
,
ops
)
;
return
code
;
}
</s>

Emit a comparison between OP0 and OP1 . CODE is the code of the comparison . It is returned , potentially modified if necessary .


<s> static bool rs6000_secondary_memory_needed ( machine_mode mode , reg_class_t from_class , reg_class_t to_class ) { enum rs6000_reg_type from_type , to_type ; bool altivec_p = ( ( from_class == ALTIVEC_REGS ) || ( to_class == ALTIVEC_REGS ) ) ; from_type = reg_class_to_reg_type [ ( int ) from_class ] ; to_type = reg_class_to_reg_type [ ( int ) to_class ] ; if ( rs6000_secondary_reload_move ( to_type , from_type , mode , ( secondary_reload_info * ) 0 , altivec_p ) ) return false ; if ( IS_FP_VECT_REG_TYPE ( from_type ) || IS_FP_VECT_REG_TYPE ( to_type ) ) return true ; return false ; } </s>

If we are copying between FP or AltiVec registers and anything else , we need a memory location . The exception is when we are targeting ppc64 and the move to/from fpr to gpr instructions are available . Also , under VSX , you can copy vector registers from the FP register set to the Altivec register set and vice versa .


<s> static bool aarch64_hard_regno_call_part_clobbered ( unsigned int abi_id , unsigned int regno , machine_mode mode ) { if ( FP_REGNUM_P ( regno ) && abi_id != ARM_PCS_SVE ) { poly_int64 per_register_size = GET_MODE_SIZE ( mode ) ; unsigned int nregs = hard_regno_nregs ( regno , mode ) ; if ( nregs > 1 ) per_register_size = exact_div ( per_register_size , nregs ) ; if ( abi_id == ARM_PCS_SIMD || abi_id == ARM_PCS_TLSDESC ) return maybe_gt ( per_register_size , 16 ) ; return maybe_gt ( per_register_size , 8 ) ; } return false ; } </s>

Implement TARGET_HARD_REGNO_CALL_PART_CLOBBERED . The callee only saves the lower 64 bits of a 128-bit register . Tell the compiler the callee clobbers the top 64 bits when restoring the bottom 64 bits .


<s> void ix86_expand_rint ( rtx operand0 , rtx operand1 ) { machine_mode mode = GET_MODE ( operand0 ) ; rtx res , xa , TWO52 , mask ; rtx_code_label * label ; TWO52 = ix86_gen_TWO52 ( mode ) ; res = copy_to_reg ( operand1 ) ; xa = ix86_expand_sse_fabs ( res , & mask ) ; label = ix86_expand_sse_compare_and_jump ( UNLE , TWO52 , xa , false ) ; if ( flag_rounding_math ) { ix86_sse_copysign_to_positive ( TWO52 , TWO52 , res , mask ) ; xa = res ; } xa = expand_simple_binop ( mode , PLUS , xa , TWO52 , NULL_RTX , 0 , OPTAB_DIRECT ) ; xa = expand_simple_binop ( mode , MINUS , xa , TWO52 , xa , 0 , OPTAB_DIRECT ) ; if ( HONOR_SIGNED_ZEROS ( mode ) && flag_rounding_math ) xa = ix86_expand_sse_fabs ( xa , NULL ) ; ix86_sse_copysign_to_positive ( res , xa , res , mask ) ; emit_label ( label ) ; LABEL_NUSES ( label ) = 1 ; emit_move_insn ( operand0 , res ) ; } </s>

Expand rint ( IEEE round to nearest ) rounding OPERAND1 and storing the result in OPERAND0 .


<s> bool MOSAsmPrinter :: PrintAsmMemoryOperand ( const MachineInstr * MI , unsigned OpNo , const char * ExtraCode , raw_ostream & OS ) { return PrintAsmOperand ( MI , OpNo , ExtraCode , OS ) ; } </s>

Print the specified operand of MI , an INLINEASM instruction , using the specified assembler variant as an address .


<s> static enum rtx_code ix86_fp_swap_condition ( enum rtx_code code ) { switch ( code ) { case GT : return TARGET_IEEE_FP ? UNKNOWN : UNLT ; case GE : return TARGET_IEEE_FP ? UNKNOWN : UNLE ; case UNLT : return TARGET_IEEE_FP ? UNKNOWN : GT ; case UNLE : return TARGET_IEEE_FP ? UNKNOWN : GE ; default : return swap_condition ( code ) ; } } </s>

Return a comparison we can do and that it is equivalent to swap_condition ( code ) apart possibly from orderedness . But , never change orderedness if TARGET_IEEE_FP , returning UNKNOWN in that case if necessary .


<s>
bool
MipsAsmParser
::
ParseInstruction
(
ParseInstructionInfo
&
Info
,
StringRef
Name
,
SMLoc
NameLoc
,
OperandVector
&
Operands
)
{
MCAsmParser
&
Parser
=
getParser
(
)
;
LLVM_DEBUG
(
dbgs
(
)
<<
"ParseInstruction\n"
)
;
getTargetStreamer
(
)
.
forbidModuleDirective
(
)
;
if
(
!
mnemonicIsValid
(
Name
,
0
)
)
{
FeatureBitset
FBS
=
ComputeAvailableFeatures
(
getSTI
(
)
.
getFeatureBits
(
)
)
;
std
::
string
Suggestion
=
MipsMnemonicSpellCheck
(
Name
,
FBS
)
;
return
Error
(
NameLoc
,
"unknown instruction"
+
Suggestion
)
;
}
Operands
.
push_back
(
MipsOperand
::
CreateToken
(
Name
,
NameLoc
,
*
this
)
)
;
if
(
getLexer
(
)
.
isNot
(
AsmToken
::
EndOfStatement
)
)
{
if
(
parseOperand
(
Operands
,
Name
)
)
{
SMLoc
Loc
=
getLexer
(
)
.
getLoc
(
)
;
return
Error
(
Loc
,
"unexpected token in argument list"
)
;
}
if
(
getLexer
(
)
.
is
(
AsmToken
::
LBrac
)
&&
parseBracketSuffix
(
Name
,
Operands
)
)
return
true
;
while
(
getLexer
(
)
.
is
(
AsmToken
::
Comma
)
)
{
Parser
.
Lex
(
)
;
if
(
parseOperand
(
Operands
,
Name
)
)
{
SMLoc
Loc
=
getLexer
(
)
.
getLoc
(
)
;
return
Error
(
Loc
,
"unexpected token in argument list"
)
;
}
if
(
getLexer
(
)
.
is
(
AsmToken
::
LBrac
)
)
{
if
(
parseBracketSuffix
(
Name
,
Operands
)
)
return
true
;
}
else
if
(
getLexer
(
)
.
is
(
AsmToken
::
LParen
)
&&
parseParenSuffix
(
Name
,
Operands
)
)
return
true
;
}
}
if
(
getLexer
(
)
.
isNot
(
AsmToken
::
EndOfStatement
)
)
{
SMLoc
Loc
=
getLexer
(
)
.
getLoc
(
)
;
return
Error
(
Loc
,
"unexpected token in argument list"
)
;
}
Parser
.
Lex
(
)
;
return
false
;
}
</s>

ParseInstruction - Parse one assembly instruction .

Mips
Mips
"ParseInstruction\n"
0
Mips
"unknown instruction"
MipsOperand::CreateToken
"unexpected token in argument list"
"unexpected token in argument list"
"unexpected token in argument list"


<s> RegisterRef RegisterAggr :: intersectWith ( RegisterRef RR ) const { RegisterAggr T ( PRI ) ; T . insert ( RR ) . intersect ( * this ) ; if ( T . empty ( ) ) return RegisterRef ( ) ; RegisterRef NR = T . makeRegRef ( ) ; assert ( NR ) ; return NR ; } </s>

Clear any flags in this flag set that are n't also set in Flags .


<s> static rtx xtensa_function_arg ( cumulative_args_t cum , machine_mode mode , const_tree type , bool named ATTRIBUTE_UNUSED ) { return xtensa_function_arg_1 ( cum , mode , type , false ) ; } </s>


<s> bool isCheapToSpeculateCttz ( ) const override { return true ; } </s>

Return true if it is cheap to speculate a call to intrinsic cttz .


<s> Register PPCIncomingValueHandler :: getStackAddress ( uint64_t Size , int64_t Offset , MachinePointerInfo & MPO , ISD :: ArgFlagsTy Flags ) { auto & MFI = MIRBuilder . getMF ( ) . getFrameInfo ( ) ; const bool IsImmutable = ! Flags . isByVal ( ) ; int FI = MFI . CreateFixedObject ( Size , Offset , IsImmutable ) ; MPO = MachinePointerInfo :: getFixedStack ( MIRBuilder . getMF ( ) , FI ) ; llvm :: LLT FramePtr = LLT :: pointer ( 0 , MIRBuilder . getMF ( ) . getDataLayout ( ) . getPointerSizeInBits ( ) ) ; MachineInstrBuilder AddrReg = MIRBuilder . buildFrameIndex ( FramePtr , FI ) ; StackUsed = std :: max ( StackUsed , Size + Offset ) ; return AddrReg . getReg ( 0 ) ; } </s>

Materialize a VReg containing the address of the specified stack-based object .


<s>
void
print
(
raw_ostream
&
OS
)
const
override
{
switch
(
Kind
)
{
case
IMMEDIATE
:
OS
<<
"Imm: "
<<
getImm
(
)
<<
"\n"
;
break
;
case
TOKEN
:
OS
<<
"Token: "
<<
getToken
(
)
<<
"\n"
;
break
;
case
REGISTER
:
OS
<<
"Reg: %r"
<<
getReg
(
)
<<
"\n"
;
break
;
case
MEMORY_IMM
:
OS
<<
"MemImm: "
<<
*
getMemOffset
(
)
<<
"\n"
;
break
;
case
MEMORY_REG_IMM
:
OS
<<
"MemRegImm: "
<<
getMemBaseReg
(
)
<<
"+"
<<
*
getMemOffset
(
)
<<
"\n"
;
break
;
case
MEMORY_REG_REG
:
assert
(
getMemOffset
(
)
==
nullptr
)
;
OS
<<
"MemRegReg: "
<<
getMemBaseReg
(
)
<<
"+"
<<
"%r"
<<
getMemOffsetReg
(
)
<<
"\n"
;
break
;
}
}
</s>

print - Print a debug representation of the operand to the given stream .

DLX
"Imm: "
"\n"
"Token: "
"\n"
"Reg: %r"
"\n"
"MemImm: "
"\n"
"MemRegImm: "
"+"
"\n"
"MemRegReg: "
"+"
"%r"
"\n"


<s> void SystemZXPLINKFrameLowering :: emitEpilogue ( MachineFunction & MF , MachineBasicBlock & MBB ) const { } </s>


<s> unsigned ARMBaseInstrInfo :: extraSizeToPredicateInstructions ( const MachineFunction & MF , unsigned NumInsts ) const { if ( ! Subtarget . isThumb2 ( ) ) return 0 ; unsigned MaxInsts = Subtarget . restrictIT ( ) ? 1 : 4 ; return divideCeil ( NumInsts , MaxInsts ) * 2 ; } </s>

Return the increase in code size needed to predicate a contiguous run of NumInsts instructions .


<s> static bool gprel_constant_p ( rtx op ) { if ( GET_CODE ( op ) == SYMBOL_REF && nios2_symbol_ref_in_small_data_p ( op ) ) return true ; else if ( GET_CODE ( op ) == CONST && GET_CODE ( XEXP ( op , 0 ) ) == PLUS ) return gprel_constant_p ( XEXP ( XEXP ( op , 0 ) , 0 ) ) ; return false ; } </s>

Return true if this is a GP-relative accessible reference .


<s> bool supportSwiftError ( ) const override { return true ; } </s>

Return true if the target supports swifterror attribute .


<s> function_sym_iterator HSACodeObject :: functions_end ( ) const { return function_sym_iterator ( symbol_end ( ) , symbol_end ( ) , [ ] ( const SymbolRef & ) { return true ; } ) ; } </s>


<s> void ARM64RegisterInfo :: materializeFrameBaseRegister ( MachineBasicBlock * MBB , unsigned BaseReg , int FrameIdx , int64_t Offset ) const { MachineBasicBlock :: iterator Ins = MBB -> begin ( ) ; DebugLoc DL ; if ( Ins != MBB -> end ( ) ) DL = Ins -> getDebugLoc ( ) ; const MCInstrDesc & MCID = TII -> get ( ARM64 :: ADDXri ) ; MachineRegisterInfo & MRI = MBB -> getParent ( ) -> getRegInfo ( ) ; const MachineFunction & MF = * MBB -> getParent ( ) ; MRI . constrainRegClass ( BaseReg , TII -> getRegClass ( MCID , 0 , this , MF ) ) ; unsigned Shifter = ARM64_AM :: getShifterImm ( ARM64_AM :: LSL , 0 ) ; BuildMI ( * MBB , Ins , DL , MCID , BaseReg ) . addFrameIndex ( FrameIdx ) . addImm ( Offset ) . addImm ( Shifter ) ; } </s>

Insert defining instruction ( s ) for a pointer to FrameIdx before insertion point I .


<s> AVRSubtarget :: AVRSubtarget ( const Triple & TT , const std :: string & CPU , const std :: string & FS , const AVRTargetMachine & TM ) : AVRGenSubtargetInfo ( TT , CPU , FS ) , ELFArch ( 0 ) , m_hasSRAM ( false ) , m_hasJMPCALL ( false ) , m_hasIJMPCALL ( false ) , m_hasEIJMPCALL ( false ) , m_hasADDSUBIW ( false ) , m_hasSmallStack ( false ) , m_hasMOVW ( false ) , m_hasLPM ( false ) , m_hasLPMX ( false ) , m_hasELPM ( false ) , m_hasELPMX ( false ) , m_hasSPM ( false ) , m_hasSPMX ( false ) , m_hasDES ( false ) , m_supportsRMW ( false ) , m_supportsMultiplication ( false ) , m_hasBREAK ( false ) , m_hasTinyEncoding ( false ) , m_FeatureSetDummy ( false ) , InstrInfo ( ) , FrameLowering ( ) , TLInfo ( TM , initializeSubtargetDependencies ( CPU , FS , TM ) ) , TSInfo ( ) { ParseSubtargetFeatures ( CPU , FS ) ; } </s>


"  Skipping pass: no machine model present.\n"

runOnMachineFunction - Emit the function body .


Write an ( optimal ) nop sequence of Count bytes to the given output .


<s> int PPCInstrInfo :: getOperandLatency ( const InstrItineraryData * ItinData , const MachineInstr & DefMI , unsigned DefIdx , const MachineInstr & UseMI , unsigned UseIdx ) const { int Latency = PPCGenInstrInfo :: getOperandLatency ( ItinData , DefMI , DefIdx , UseMI , UseIdx ) ; if ( ! DefMI . getParent ( ) ) return Latency ; const MachineOperand & DefMO = DefMI . getOperand ( DefIdx ) ; Register Reg = DefMO . getReg ( ) ; bool IsRegCR ; if ( Register :: isVirtualRegister ( Reg ) ) { const MachineRegisterInfo * MRI = & DefMI . getParent ( ) -> getParent ( ) -> getRegInfo ( ) ; IsRegCR = MRI -> getRegClass ( Reg ) -> hasSuperClassEq ( & PPC :: CRRCRegClass ) || MRI -> getRegClass ( Reg ) -> hasSuperClassEq ( & PPC :: CRBITRCRegClass ) ; } else { IsRegCR = PPC :: CRRCRegClass . contains ( Reg ) || PPC :: CRBITRCRegClass . contains ( Reg ) ; } if ( UseMI . isBranch ( ) && IsRegCR ) { if ( Latency < 0 ) Latency = getInstrLatency ( ItinData , DefMI ) ; unsigned Directive = Subtarget . getDarwinDirective ( ) ; switch ( Directive ) { default : break ; case PPC :: DIR_7400 : case PPC :: DIR_750 : case PPC :: DIR_970 : case PPC :: DIR_E5500 : case PPC :: DIR_PWR4 : case PPC :: DIR_PWR5 : case PPC :: DIR_PWR5X : case PPC :: DIR_PWR6 : case PPC :: DIR_PWR6X : case PPC :: DIR_PWR7 : case PPC :: DIR_PWR8 : Latency += 2 ; break ; } } return Latency ; } </s>

Compute and return the use operand latency of a given pair of def and use .


<s> int frv_acc_group ( rtx insn ) { if ( frv_cpu_type != FRV_CPU_FR550 ) return ACC_GROUP_NONE ; return for_each_rtx ( & PATTERN ( insn ) , frv_acc_group_1 , 0 ) ; } </s>

Return the value of INSN 's acc_group attribute .


"Merging loop %x [%d,%d] into %x [%d,%d]\n"

If PAR has a single inner parallel and PAR itself only contains empty entry and exit blocks , swallow the inner PAR .


"dynamic stack realignment without a FP!"

getFrameIndexReference - This method should return the base register and offset used to reference a frame index location .


<s> static void mips_emit_compare ( enum rtx_code * code , rtx * op0 , rtx * op1 , bool need_eq_ne_p ) { rtx cmp_op0 = * op0 ; rtx cmp_op1 = * op1 ; if ( GET_MODE_CLASS ( GET_MODE ( * op0 ) ) == MODE_INT ) { if ( ! need_eq_ne_p && * op1 == const0_rtx ) ; else if ( * code == EQ || * code == NE ) { if ( need_eq_ne_p ) { * op0 = mips_zero_if_equal ( cmp_op0 , cmp_op1 ) ; * op1 = const0_rtx ; } else * op1 = force_reg ( GET_MODE ( cmp_op0 ) , cmp_op1 ) ; } else if ( ! need_eq_ne_p && TARGET_CB_MAYBE ) { bool swap = false ; switch ( * code ) { case LE : swap = true ; * code = GE ; break ; case GT : swap = true ; * code = LT ; break ; case LEU : swap = true ; * code = GEU ; break ; case GTU : swap = true ; * code = LTU ; break ; case GE : case LT : case GEU : case LTU : break ; default : gcc_unreachable ( ) ; } * op1 = force_reg ( GET_MODE ( cmp_op0 ) , cmp_op1 ) ; if ( swap ) { rtx tmp = * op1 ; * op1 = * op0 ; * op0 = tmp ; } } else { bool invert = false ; * op0 = gen_reg_rtx ( GET_MODE ( cmp_op0 ) ) ; mips_emit_int_order_test ( * code , & invert , * op0 , cmp_op0 , cmp_op1 ) ; * code = ( invert ? EQ : NE ) ; * op1 = const0_rtx ; } } else if ( ALL_FIXED_POINT_MODE_P ( GET_MODE ( cmp_op0 ) ) ) { * op0 = gen_rtx_REG ( CCDSPmode , CCDSP_CC_REGNUM ) ; mips_emit_binary ( * code , * op0 , cmp_op0 , cmp_op1 ) ; * code = NE ; * op1 = const0_rtx ; } else { enum rtx_code cmp_code ; cmp_code = * code ; if ( ISA_HAS_CCF ) { * code = NE ; * op0 = gen_reg_rtx ( CCFmode ) ; } else { * code = mips_reversed_fp_cond ( & cmp_code ) ? EQ : NE ; if ( ISA_HAS_8CC ) * op0 = mips_allocate_fcc ( CCmode ) ; else * op0 = gen_rtx_REG ( CCmode , FPSW_REGNUM ) ; } * op1 = const0_rtx ; mips_emit_binary ( cmp_code , * op0 , cmp_op0 , cmp_op1 ) ; } } </s>

Convert a comparison into something that can be used in a branch or conditional move . On entry , * OP0 and * OP1 are the values being compared and * CODE is the code used to compare them . Update * CODE , * OP0 and * OP1 so that they describe the final comparison . If NEED_EQ_NE_P , then only EQ or NE comparisons against zero are possible , otherwise any standard branch condition can be used . The standard branch conditions are : - EQ or NE between two registers . - any comparison between a register and zero .


<s>
static
void
r10k_insert_cache_barriers
(
void
)
{
int
*
rev_post_order
;
unsigned
int
i
,
n
;
basic_block
bb
;
sbitmap
protected_bbs
;
rtx_insn
*
insn
,
*
end
;
rtx
unprotected_region
;
if
(
TARGET_MIPS16
)
{
sorry
(
"%qs does not support MIPS16 code"
,
"-mr10k-cache-barrier"
)
;
return
;
}
calculate_dominance_info
(
CDI_DOMINATORS
)
;
protected_bbs
=
sbitmap_alloc
(
last_basic_block_for_fn
(
cfun
)
)
;
bitmap_clear
(
protected_bbs
)
;
rev_post_order
=
XNEWVEC
(
int
,
last_basic_block_for_fn
(
cfun
)
)
;
n
=
pre_and_rev_post_order_compute
(
,
rev_post_order
,
false
)
;
for
(
i
=
0
;
i
<
n
;
i
++
)
{
bb
=
BASIC_BLOCK_FOR_FN
(
cfun
,
rev_post_order
[
i
]
)
;
if
(
r10k_protected_bb_p
(
bb
,
protected_bbs
)
)
unprotected_region
=
NULL_RTX
;
else
unprotected_region
=
pc_rtx
;
end
=
NEXT_INSN
(
BB_END
(
bb
)
)
;
for
(
insn
=
BB_HEAD
(
bb
)
;
insn
!=
end
;
insn
=
NEXT_INSN
(
insn
)
)
{
if
(
unprotected_region
&&
USEFUL_INSN_P
(
insn
)
)
{
if
(
recog_memoized
(
insn
)
==
CODE_FOR_mips_cache
)
unprotected_region
=
NULL_RTX
;
else
{
if
(
unprotected_region
==
pc_rtx
)
unprotected_region
=
insn
;
if
(
r10k_needs_protection_p
(
insn
)
)
{
emit_insn_before
(
gen_r10k_cache_barrier
(
)
,
as_a
<
rtx_insn
*
>
(
unprotected_region
)
)
;
unprotected_region
=
NULL_RTX
;
}
}
}
if
(
CALL_P
(
insn
)
)
unprotected_region
=
pc_rtx
;
}
if
(
unprotected_region
==
NULL_RTX
)
bitmap_set_bit
(
protected_bbs
,
bb
->
index
)
;
}
XDELETEVEC
(
rev_post_order
)
;
sbitmap_free
(
protected_bbs
)
;
free_dominance_info
(
CDI_DOMINATORS
)
;
}
</s>

Implement -mr10k-cache-barrier= for the current function .


<s> static bool avr_use_by_pieces_infrastructure_p ( unsigned HOST_WIDE_INT size , unsigned int align ATTRIBUTE_UNUSED , enum by_pieces_operation op , bool speed_p ) { if ( op != MOVE_BY_PIECES || ( speed_p && size > MOVE_MAX_PIECES ) ) return default_use_by_pieces_infrastructure_p ( size , align , op , speed_p ) ; return size <= MOVE_MAX_PIECES ; } </s>

Prefer sequence of loads/stores for moves of size upto two - two pairs of load/store instructions are always better than the 5 instruction sequence for a loop ( 1 instruction for loop counter setup , and 4 for the body of the loop ) .


"Callee saved registers requested for unknown architecture "


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const { AU . setPreservesAll ( ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> const uint32_t * AVRRegisterInfo :: getCallPreservedMask ( const MachineFunction & MF , CallingConv :: ID CC ) const { const AVRSubtarget & STI = MF . getSubtarget < AVRSubtarget > ( ) ; return STI . hasTinyEncoding ( ) ? CSR_NormalTiny_RegMask : CSR_Normal_RegMask ; } </s>

Return a mask of call-preserved registers for the given calling convention on the current function .


<s> TargetLoweringObjectFile * XtensaTargetMachine :: getObjFileLowering ( ) const { return 0 ; } </s>

Return information about object file lowering .


"insertBranch must not be told to insert a fallthrough"

"wrong number of m88k branch conditions"

Insert branch code into the end of the specified MachineBasicBlock .


<s> unsigned MandarinRegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { const TargetFrameLowering * TFI = MF . getTarget ( ) . getFrameLowering ( ) ; return TFI -> hasFP ( MF ) ? MD :: R31 : MD :: R30 ; } </s>


<s> bool MSP430PassConfig :: addPreEmitPass ( ) { addPass ( createMSP430BranchSelectionPass ( ) ) ; return false ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


"Can't store this register to stack slot"

Store the specified register of the given register class to the specified stack frame index .


<s> inline static MCDisassembler :: DecodeStatus addOperand ( MCInst & Inst , const MCOperand & Opnd ) { Inst . addOperand ( Opnd ) ; return Opnd . isValid ( ) ? MCDisassembler :: Success : MCDisassembler :: SoftFail ; } </s>


<s> MachineBasicBlock :: iterator AArch64InstrInfo :: insertOutlinedCall ( Module & M , MachineBasicBlock & MBB , MachineBasicBlock :: iterator & It , MachineFunction & MF , bool IsTailCall ) const { if ( IsTailCall ) { It = MBB . insert ( It , BuildMI ( MF , DebugLoc ( ) , get ( AArch64 :: B ) ) . addGlobalAddress ( M . getNamedValue ( MF . getName ( ) ) ) ) ; return It ; } MachineInstr * STRXpre = BuildMI ( MF , DebugLoc ( ) , get ( AArch64 :: STRXpre ) ) . addReg ( AArch64 :: SP , RegState :: Define ) . addReg ( AArch64 :: LR ) . addReg ( AArch64 :: SP ) . addImm ( - 16 ) ; It = MBB . insert ( It , STRXpre ) ; It ++ ; It = MBB . insert ( It , BuildMI ( MF , DebugLoc ( ) , get ( AArch64 :: BL ) ) . addGlobalAddress ( M . getNamedValue ( MF . getName ( ) ) ) ) ; It ++ ; MachineInstr * LDRXpost = BuildMI ( MF , DebugLoc ( ) , get ( AArch64 :: LDRXpost ) ) . addReg ( AArch64 :: SP , RegState :: Define ) . addReg ( AArch64 :: LR ) . addReg ( AArch64 :: SP ) . addImm ( 16 ) ; It = MBB . insert ( It , LDRXpost ) ; return It ; } </s>

Insert a call to an outlined function into the program .


<s> bool AMDGPUSymbolizer :: tryAddingSymbolicOperand ( MCInst & Inst , raw_ostream & , int64_t Value , uint64_t , bool IsBranch , uint64_t , uint64_t ) { typedef std :: tuple < uint64_t , StringRef , uint8_t > SymbolInfoTy ; typedef std :: vector < SymbolInfoTy > SectionSymbolsTy ; if ( ! IsBranch ) { return false ; } auto * Symbols = static_cast < SectionSymbolsTy * > ( DisInfo ) ; auto Result = std :: find_if ( Symbols -> begin ( ) , Symbols -> end ( ) , [ Value ] ( const SymbolInfoTy & Val ) { return std :: get < 0 > ( Val ) == static_cast < uint64_t > ( Value ) && std :: get < 2 > ( Val ) == ELF :: STT_NOTYPE ; } ) ; if ( Result != Symbols -> end ( ) ) { auto * Sym = Ctx . getOrCreateSymbol ( std :: get < 1 > ( * Result ) ) ; const auto * Add = MCSymbolRefExpr :: create ( Sym , Ctx ) ; Inst . addOperand ( MCOperand :: createExpr ( Add ) ) ; return true ; } return false ; } </s>

Try to add a symbolic operand instead of Value to the MCInst .


"flag setting instruction only valid outside IT block"

"instruction only valid inside IT block"

"instruction variant requires ARMv6 or later"

"immediate operand must be in the range [0,15]"

MatchAndEmitInstruction - Recognize a series of operands of a parsed instruction as an actual MCInst and emit it to the specified MCStreamer .


<s> bool ARMTargetLowering :: isDesirableToTransformToIntegerOp ( unsigned Opc , EVT VT ) const { return ( VT == MVT :: f32 ) && ( Opc == ISD :: LOAD || Opc == ISD :: STORE ) ; } </s>

Return true if it is profitable for dag combiner to transform a floating point op of specified opcode to a equivalent op of an integer type .


<s> void MSP430PassConfig :: addPreEmitPass ( ) { addPass ( createMSP430BranchSelectionPass ( ) ) ; } </s>