<s> static void expand_block_move_2 ( rtx dst , rtx dst_reg , rtx src , rtx src_reg , rtx bytes_rtx ) { unsigned HOST_WIDE_INT bytes = UINTVAL ( bytes_rtx ) ; unsigned int rem = bytes % 2 ; emit_library_call ( wrd_memcpy_libfunc , LCT_NORMAL , VOIDmode , 3 , dst_reg , Pmode , src_reg , Pmode , convert_to_mode ( TYPE_MODE ( sizetype ) , GEN_INT ( bytes >> 1 ) , TYPE_UNSIGNED ( sizetype ) ) , TYPE_MODE ( sizetype ) ) ; if ( rem == 0 ) return ; dst = replace_equiv_address_nv ( dst , dst_reg ) ; src = replace_equiv_address_nv ( src , src_reg ) ; bytes -= rem ; emit_move_insn ( adjust_address_nv ( dst , QImode , bytes ) , adjust_address_nv ( src , QImode , bytes ) ) ; } </s>

Generate a call to a library function to move BYTES_RTX bytes from SRC with address SRC_REG to DST with address DST_REG in 2-bytes chunks .


<s> MCELFStreamer & SparcTargetELFStreamer :: getStreamer ( ) { return static_cast < MCELFStreamer & > ( Streamer ) ; } </s>

Return the output streamer for the assembler .


<s> void MipsTargetELFStreamer :: finish ( ) { MCAssembler & MCA = getStreamer ( ) . getAssembler ( ) ; const MCObjectFileInfo & OFI = * MCA . getContext ( ) . getObjectFileInfo ( ) ; MCSection & TextSection = * OFI . getTextSection ( ) ; MCA . registerSection ( TextSection ) ; MCSection & DataSection = * OFI . getDataSection ( ) ; MCA . registerSection ( DataSection ) ; MCSection & BSSSection = * OFI . getBSSSection ( ) ; MCA . registerSection ( BSSSection ) ; TextSection . setAlignment ( Align ( std :: max ( 16u , TextSection . getAlignment ( ) ) ) ) ; DataSection . setAlignment ( Align ( std :: max ( 16u , DataSection . getAlignment ( ) ) ) ) ; BSSSection . setAlignment ( Align ( std :: max ( 16u , BSSSection . getAlignment ( ) ) ) ) ; if ( RoundSectionSizes ) { MCStreamer & OS = getStreamer ( ) ; for ( MCSection & S : MCA ) { MCSectionELF & Section = static_cast < MCSectionELF & > ( S ) ; unsigned Alignment = Section . getAlignment ( ) ; if ( Alignment ) { OS . SwitchSection ( & Section ) ; if ( Section . UseCodeAlign ( ) ) OS . EmitCodeAlignment ( Alignment , Alignment ) ; else OS . EmitValueToAlignment ( Alignment , 0 , 1 , Alignment ) ; } } } const FeatureBitset & Features = STI . getFeatureBits ( ) ; unsigned EFlags = MCA . getELFHeaderEFlags ( ) ; if ( getABI ( ) . IsO32 ( ) ) EFlags |= ELF :: EF_MIPS_ABI_O32 ; else if ( getABI ( ) . IsN32 ( ) ) EFlags |= ELF :: EF_MIPS_ABI2 ; if ( Features [ Mips :: FeatureGP64Bit ] ) { if ( getABI ( ) . IsO32 ( ) ) EFlags |= ELF :: EF_MIPS_32BITMODE ; } else if ( Features [ Mips :: FeatureMips64r2 ] || Features [ Mips :: FeatureMips64 ] ) EFlags |= ELF :: EF_MIPS_32BITMODE ; if ( ! Features [ Mips :: FeatureNoABICalls ] ) EFlags |= ELF :: EF_MIPS_CPIC ; if ( Pic ) EFlags |= ELF :: EF_MIPS_PIC | ELF :: EF_MIPS_CPIC ; MCA . setELFHeaderEFlags ( EFlags ) ; MipsELFStreamer & MEF = static_cast < MipsELFStreamer & > ( Streamer ) ; MEF . EmitMipsOptionRecords ( ) ; emitMipsAbiFlags ( ) ; } </s>

finish - after all the new live ranges have been created , compute the remaining live range , and rewrite instructions to use the new registers .


<s> const uint32_t * MCS51RegisterInfo :: getCallPreservedMask ( const MachineFunction & MF , CallingConv :: ID CC ) const { const MCS51MachineFunctionInfo * AFI = MF . getInfo < MCS51MachineFunctionInfo > ( ) ; return AFI -> isInterruptOrSignalHandler ( ) ? CSR_Interrupts_RegMask : CSR_Normal_RegMask ; } </s>

Return a mask of call-preserved registers for the given calling convention on the current function .


<s>
void
MMIXDAGToDAGISel
::
Select
(
SDNode
*
Node
)
{
unsigned
Opcode
=
Node
->
getOpcode
(
)
;
if
(
Node
->
isMachineOpcode
(
)
)
{
LLVM_DEBUG
(
dbgs
(
)
<<
"== "
;
Node
->
dump
(
CurDAG
)
;
dbgs
(
)
<<
"\n"
)
;
Node
->
setNodeId
(
1
)
;
return
;
}
if
(
Opcode
==
ISD
::
FrameIndex
)
{
SDLoc
DL
(
Node
)
;
SDValue
Imm
=
CurDAG
->
getTargetConstant
(
0
,
DL
,
MVT
::
i64
)
;
int
FI
=
dyn_cast
<
FrameIndexSDNode
>
(
Node
)
->
getIndex
(
)
;
EVT
VT
=
Node
->
getValueType
(
0
)
;
SDValue
TFI
=
CurDAG
->
getTargetFrameIndex
(
FI
,
VT
)
;
ReplaceNode
(
Node
,
CurDAG
->
getMachineNode
(
MMIX
::
ADD_I
,
DL
,
VT
,
TFI
,
Imm
)
)
;
return
;
}
SelectCode
(
Node
)
;
}
</s>

Main hook for targets to transform nodes into machine nodes .


<s> bool PPCAsmParser :: ParseInstruction ( ParseInstructionInfo & Info , StringRef Name , SMLoc NameLoc , OperandVector & Operands ) { std :: string NewOpcode ; if ( getLexer ( ) . is ( AsmToken :: Plus ) ) { getLexer ( ) . Lex ( ) ; NewOpcode = Name ; NewOpcode += '+' ; Name = NewOpcode ; } if ( getLexer ( ) . is ( AsmToken :: Minus ) ) { getLexer ( ) . Lex ( ) ; NewOpcode = Name ; NewOpcode += '-' ; Name = NewOpcode ; } size_t Dot = Name . find ( '.' ) ; StringRef Mnemonic = Name . slice ( 0 , Dot ) ; if ( ! NewOpcode . empty ( ) ) Operands . push_back ( PPCOperand :: CreateTokenWithStringCopy ( Mnemonic , NameLoc , isPPC64 ( ) ) ) ; else Operands . push_back ( PPCOperand :: CreateToken ( Mnemonic , NameLoc , isPPC64 ( ) ) ) ; if ( Dot != StringRef :: npos ) { SMLoc DotLoc = SMLoc :: getFromPointer ( NameLoc . getPointer ( ) + Dot ) ; StringRef DotStr = Name . slice ( Dot , StringRef :: npos ) ; if ( ! NewOpcode . empty ( ) ) Operands . push_back ( PPCOperand :: CreateTokenWithStringCopy ( DotStr , DotLoc , isPPC64 ( ) ) ) ; else Operands . push_back ( PPCOperand :: CreateToken ( DotStr , DotLoc , isPPC64 ( ) ) ) ; } if ( getLexer ( ) . is ( AsmToken :: EndOfStatement ) ) return false ; if ( ParseOperand ( Operands ) ) return true ; while ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) && getLexer ( ) . is ( AsmToken :: Comma ) ) { getLexer ( ) . Lex ( ) ; if ( ParseOperand ( Operands ) ) return true ; } return false ; } </s>

ParseInstruction - Parse one assembly instruction .

PowerPC PPC 0 PPC PPC PPC PPC PPC PPC PPC PPC


<s> bool Z80oldCallFrameOptimization :: runOnMachineFunction ( MachineFunction & MF ) { if ( skipFunction ( MF . getFunction ( ) ) || NoZ80oldCFOpt . getValue ( ) ) { return false ; } return false ; } </s>

runOnMachineFunction - Emit the function body .


<s> const Function * PatmosSPMark :: getCallTarget ( const MachineInstr * MI ) const { const MachineOperand & MO = MI -> getOperand ( 2 ) ; const Function * Target = NULL ; if ( MO . isGlobal ( ) ) { Target = dyn_cast < Function > ( MO . getGlobal ( ) ) ; } else if ( MO . isSymbol ( ) ) { const char * TargetName = MO . getSymbolName ( ) ; const Module * M = MI -> getParent ( ) -> getParent ( ) -> getFunction ( ) -> getParent ( ) ; Target = M -> getFunction ( TargetName ) ; } return Target ; } </s>

Return the target of the underlying call .


<s> bool HexagonPassConfig :: addPreSched2 ( ) { addPass ( IfConverterID ) ; return true ; } </s>

This method may be implemented by targets that want to run passes after prolog-epilog insertion and before the second instruction scheduling pass .


<s> void LC3FrameLowering :: emitPrologue ( MachineFunction & MF , MachineBasicBlock & MBB ) const { const TargetInstrInfo & TII = * MF . getSubtarget ( ) . getInstrInfo ( ) ; MachineBasicBlock :: iterator MBBI = MBB . begin ( ) ; DebugLoc dl = MBBI != MBB . end ( ) ? MBBI -> getDebugLoc ( ) : DebugLoc ( ) ; uint64_t StackSize = computeStackSize ( MF ) ; if ( ! StackSize ) { return ; } unsigned StackReg = LC3 :: SP ; unsigned OffsetReg = materializeOffset ( MF , MBB , MBBI , ( unsigned ) StackSize ) ; if ( OffsetReg ) { BuildMI ( MBB , MBBI , dl , TII . get ( LC3 :: SUBrr ) , StackReg ) . addReg ( StackReg ) . addReg ( OffsetReg ) . setMIFlag ( MachineInstr :: FrameSetup ) ; } else { BuildMI ( MBB , MBBI , dl , TII . get ( LC3 :: ADDri ) , StackReg ) . addReg ( StackReg ) . addImm ( - StackSize ) . setMIFlag ( MachineInstr :: FrameSetup ) ; } } </s>

emitProlog/emitEpilog - These methods insert prolog and epilog code into the function .


<s> SDValue AMDGPUTargetLowering :: LowerFREM ( SDValue Op , SelectionDAG & DAG ) const { SDLoc SL ( Op ) ; EVT VT = Op . getValueType ( ) ; SDValue X = Op . getOperand ( 0 ) ; SDValue Y = Op . getOperand ( 1 ) ; SDValue Div = DAG . getNode ( ISD :: FDIV , SL , VT , X , Y ) ; SDValue Floor = DAG . getNode ( ISD :: FTRUNC , SL , VT , Div ) ; SDValue Mul = DAG . getNode ( ISD :: FMUL , SL , VT , Floor , Y ) ; return DAG . getNode ( ISD :: FSUB , SL , VT , X , Mul ) ; } </s>

Split a vector store into multiple scalar stores .


<s> void SIInstrInfo :: legalizeOperandsVOP3 ( MachineRegisterInfo & MRI , MachineInstr * MI ) const { unsigned Opc = MI -> getOpcode ( ) ; int VOP3Idx [ 3 ] = { AMDGPU :: getNamedOperandIdx ( Opc , AMDGPU :: OpName :: src0 ) , AMDGPU :: getNamedOperandIdx ( Opc , AMDGPU :: OpName :: src1 ) , AMDGPU :: getNamedOperandIdx ( Opc , AMDGPU :: OpName :: src2 ) } ; unsigned SGPRReg = findUsedSGPR ( MI , VOP3Idx ) ; for ( unsigned i = 0 ; i < 3 ; ++ i ) { int Idx = VOP3Idx [ i ] ; if ( Idx == - 1 ) break ; MachineOperand & MO = MI -> getOperand ( Idx ) ; if ( ! MO . isReg ( ) ) continue ; if ( ! RI . isSGPRClass ( MRI . getRegClass ( MO . getReg ( ) ) ) ) continue ; if ( SGPRReg == AMDGPU :: NoRegister || SGPRReg == MO . getReg ( ) ) { SGPRReg = MO . getReg ( ) ; continue ; } legalizeOpWithMove ( MI , Idx ) ; } } </s>

Fix operands in MI to satisfy constant bus requirements .

AMDGPU SI 3 AMDGPU::getNamedOperandIdx AMDGPU::OpName AMDGPU::getNamedOperandIdx AMDGPU::OpName AMDGPU::getNamedOperandIdx AMDGPU::OpName 0 3 1 AMDGPU::NoRegister


<s> void AGCTargetLowering :: ReplaceNodeResults ( SDNode * N , SmallVectorImpl < SDValue > & Results , SelectionDAG & DAG ) const { switch ( N -> getOpcode ( ) ) { default : SDValue Res = LowerOperation ( SDValue ( N , 0 ) , DAG ) ; for ( unsigned I = 0 , E = Res -> getNumValues ( ) ; I != E ; ++ I ) Results . push_back ( Res . getValue ( I ) ) ; break ; } } </s>

ReplaceNodeResults - Replace the results of node with an illegal result type with new values built out of custom code .


<s>
GB
::
Fixups
GBZ80MCExpr
::
getFixupKind
(
)
const
{
GB
::
Fixups
Kind
=
GB
::
Fixups
::
LastTargetFixupKind
;
switch
(
getKind
(
)
)
{
case
VK_GBZ80_LO8
:
Kind
=
isNegated
(
)
GB
::
fixup_lo8_ldi_neg
:
GB
::
fixup_lo8_ldi
;
break
;
case
VK_GBZ80_HI8
:
Kind
=
isNegated
(
)
GB
::
fixup_hi8_ldi_neg
:
GB
::
fixup_hi8_ldi
;
break
;
case
VK_GBZ80_HH8
:
Kind
=
isNegated
(
)
GB
::
fixup_hh8_ldi_neg
:
GB
::
fixup_hh8_ldi
;
break
;
case
VK_GBZ80_HHI8
:
Kind
=
isNegated
(
)
GB
::
fixup_ms8_ldi_neg
:
GB
::
fixup_ms8_ldi
;
break
;
case
VK_GBZ80_PM_LO8
:
Kind
=
isNegated
(
)
GB
::
fixup_lo8_ldi_pm_neg
:
GB
::
fixup_lo8_ldi_pm
;
break
;
case
VK_GBZ80_PM_HI8
:
Kind
=
isNegated
(
)
GB
::
fixup_hi8_ldi_pm_neg
:
GB
::
fixup_hi8_ldi_pm
;
break
;
case
VK_GBZ80_PM_HH8
:
Kind
=
isNegated
(
)
GB
::
fixup_hh8_ldi_pm_neg
:
GB
::
fixup_hh8_ldi_pm
;
break
;
case
VK_GBZ80_None
:
llvm_unreachable
(
"Uninitialized expression"
)
;
}
return
Kind
;
}
</s>

getFixupKind - Get the fixup kind of this expression .


<s>
void
MipsCodeEmitter
::
emitInstruction
(
const
MachineInstr
&
MI
)
{
DEBUG
(
errs
(
)
<<
"JIT: "
<<
(
void
*
)
MCE
.
getCurrentPCValue
(
)
<<
":\t"
<<
MI
)
;
MCE
.
processDebugLoc
(
MI
.
getDebugLoc
(
)
,
true
)
;
if
(
(
MI
.
getDesc
(
)
.
TSFlags
&
MipsII
::
FormMask
)
==
MipsII
::
Pseudo
)
return
;
switch
(
MI
.
getOpcode
(
)
)
{
case
Mips
::
USW
:
NumEmitted
+=
emitUSW
(
MI
)
;
break
;
case
Mips
::
ULW
:
NumEmitted
+=
emitULW
(
MI
)
;
break
;
case
Mips
::
ULH
:
NumEmitted
+=
emitULH
(
MI
)
;
break
;
case
Mips
::
ULHu
:
NumEmitted
+=
emitULHu
(
MI
)
;
break
;
case
Mips
::
USH
:
NumEmitted
+=
emitUSH
(
MI
)
;
break
;
default
:
emitWordLE
(
getBinaryCodeForInstr
(
MI
)
)
;
++
NumEmitted
;
break
;
}
MCE
.
processDebugLoc
(
MI
.
getDebugLoc
(
)
,
false
)
;
}
</s>

Targets should implement this to emit instructions .

Mips
Mips
"JIT: "
":\t"
MipsII::FormMask
MipsII::Pseudo
Mips::USW
Mips::ULW
Mips::ULH
Mips::ULHu
Mips::USH


<s> static bool rs6000_cannot_copy_insn_p ( rtx_insn * insn ) { return recog_memoized ( insn ) >= 0 && get_attr_cannot_copy ( insn ) ; } </s>

Return true if INSN should not be copied .


<s> bool RISCVPassConfig :: addIRTranslator ( ) { addPass ( new IRTranslator ( getOptLevel ( ) ) ) ; return false ; } </s>

This method should install an IR translator pass , which converts from LLVM code to machine instructions with possibly generic opcodes .


<s> bool XCoreFTAOElim :: runOnMachineFunction ( MachineFunction & MF ) { const XCoreInstrInfo & TII = * static_cast < const XCoreInstrInfo * > ( MF . getSubtarget ( ) . getInstrInfo ( ) ) ; unsigned StackSize = MF . getFrameInfo ( ) . getStackSize ( ) ; for ( MachineBasicBlock & MBB : MF ) { for ( MachineBasicBlock :: iterator MBBI = MBB . begin ( ) , EE = MBB . end ( ) ; MBBI != EE ; ++ MBBI ) { if ( MBBI -> getOpcode ( ) == XCore :: FRAME_TO_ARGS_OFFSET ) { MachineInstr & OldInst = * MBBI ; Register Reg = OldInst . getOperand ( 0 ) . getReg ( ) ; MBBI = TII . loadImmediate ( MBB , MBBI , Reg , StackSize ) ; OldInst . eraseFromParent ( ) ; } } } return true ; } </s>

XCore XCore XCore XCore XCore::FRAME_TO_ARGS_OFFSET 0


<s> BitVector SIRegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s> void addExpr ( MCInst & Inst , const MCExpr * Expr ) const { if ( Expr == 0 ) Inst . addOperand ( MCOperand :: CreateImm ( 0 ) ) ; else if ( const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( Expr ) ) Inst . addOperand ( MCOperand :: CreateImm ( CE -> getValue ( ) ) ) ; else Inst . addOperand ( MCOperand :: CreateExpr ( Expr ) ) ; } </s>


<s> bool GCNPassConfig :: addPreRewrite ( ) { if ( EnableRegReassign ) { addPass ( & GCNNSAReassignID ) ; addPass ( & GCNRegBankReassignID ) ; } return true ; } </s>

addPreRewrite - Add passes to the optimized register allocation pipeline after register allocation is complete , but before virtual registers are rewritten to physical registers .


<s> bool MicroMipsSizeReduce :: runOnMachineFunction ( MachineFunction & MF ) { Subtarget = & static_cast < const MipsSubtarget & > ( MF . getSubtarget ( ) ) ; if ( ! Subtarget -> inMicroMipsMode ( ) || ! Subtarget -> hasMips32r2 ( ) || Subtarget -> hasMips32r6 ( ) ) return false ; MipsII = static_cast < const MipsInstrInfo * > ( Subtarget -> getInstrInfo ( ) ) ; bool Modified = false ; MachineFunction :: iterator I = MF . begin ( ) , E = MF . end ( ) ; for ( ; I != E ; ++ I ) Modified |= ReduceMBB ( * I ) ; return Modified ; } </s>


<s> static bool rs6000_need_ipa_fn_target_info ( const_tree decl , unsigned int & info ATTRIBUTE_UNUSED ) { tree target = DECL_FUNCTION_SPECIFIC_TARGET ( decl ) ; if ( ! target ) target = target_option_default_node ; struct cl_target_option * opts = TREE_TARGET_OPTION ( target ) ; if ( opts -> x_rs6000_isa_flags & OPTION_MASK_HTM ) return true ; return false ; } </s>

Hook to decide if we need to scan function gimple statements to collect target specific information for inlining , and update the corresponding RS6000_FN_TARGET_INFO_ * bit in INFO if we are able to predict which ISA feature is used at this time . Return true if we need to scan , otherwise return false .


<s> bool PPCAsmParser :: ParseDirective ( AsmToken DirectiveID ) { StringRef IDVal = DirectiveID . getIdentifier ( ) ; if ( ! isDarwin ( ) ) { if ( IDVal == ".word" ) return ParseDirectiveWord ( 2 , DirectiveID . getLoc ( ) ) ; if ( IDVal == ".llong" ) return ParseDirectiveWord ( 8 , DirectiveID . getLoc ( ) ) ; if ( IDVal == ".tc" ) return ParseDirectiveTC ( isPPC64 ( ) ? 8 : 4 , DirectiveID . getLoc ( ) ) ; if ( IDVal == ".machine" ) return ParseDirectiveMachine ( DirectiveID . getLoc ( ) ) ; if ( IDVal == ".abiversion" ) return ParseDirectiveAbiVersion ( DirectiveID . getLoc ( ) ) ; if ( IDVal == ".localentry" ) return ParseDirectiveLocalEntry ( DirectiveID . getLoc ( ) ) ; } else { if ( IDVal == ".machine" ) return ParseDarwinDirectiveMachine ( DirectiveID . getLoc ( ) ) ; } return true ; } </s>

ParseDirective - Parse a target specific assembler directive This method is deprecated , use 'parseDirective ' instead .


<s> PPCSubtarget :: PPCSubtarget ( const TargetMachine & tm , const Module & M , const std :: string & FS , bool is64Bit ) : TM ( tm ) , StackAlignment ( 16 ) , DarwinDirective ( PPC :: DIR_NONE ) , IsGigaProcessor ( false ) , Has64BitSupport ( false ) , Use64BitRegs ( false ) , IsPPC64 ( is64Bit ) , HasAltivec ( false ) , HasFSQRT ( false ) , HasSTFIWX ( false ) , HasLazyResolverStubs ( false ) , DarwinVers ( 0 ) { std :: string CPU = "generic" ; CPU = GetCurrentPowerPCCPU ( ) ; ParseSubtargetFeatures ( FS , CPU ) ; if ( is64Bit ) { Has64BitSupport = true ; Use64BitRegs = true ; } if ( use64BitRegs ( ) && ! has64BitSupport ( ) ) Use64BitRegs = false ; const std :: string & TT = M . getTargetTriple ( ) ; if ( TT . length ( ) > 7 ) { size_t DarwinPos = TT . find ( "-darwin" ) ; if ( DarwinPos != std :: string :: npos ) { if ( isdigit ( TT [ DarwinPos + 7 ] ) ) DarwinVers = atoi ( & TT [ DarwinPos + 7 ] ) ; else DarwinVers = 8 ; } } else if ( TT . empty ( ) ) { DarwinVers = 9 ; DarwinVers = 8 ; } if ( isDarwin ( ) ) { HasLazyResolverStubs = true ; AsmFlavor = NewMnemonic ; } else { AsmFlavor = OldMnemonic ; } } </s>

This constructor initializes the data members to match that of the specified triple .


<s>
MachineBasicBlock
*
SparcTargetLowering
::
EmitInstrWithCustomInserter
(
MachineInstr
&
MI
,
MachineBasicBlock
*
BB
)
const
{
switch
(
MI
.
getOpcode
(
)
)
{
default
:
llvm_unreachable
(
"Unknown SELECT_CC!"
)
;
case
SP
::
SELECT_CC_Int_ICC
:
case
SP
::
SELECT_CC_FP_ICC
:
case
SP
::
SELECT_CC_DFP_ICC
:
case
SP
::
SELECT_CC_QFP_ICC
:
return
expandSelectCC
(
MI
,
BB
,
SP
::
BCOND
)
;
case
SP
::
SELECT_CC_Int_FCC
:
case
SP
::
SELECT_CC_FP_FCC
:
case
SP
::
SELECT_CC_DFP_FCC
:
case
SP
::
SELECT_CC_QFP_FCC
:
return
expandSelectCC
(
MI
,
BB
,
SP
::
FBCOND
)
;
}
}
</s>

This method should be implemented by targets that mark instructions with the 'usesCustomInserter ' flag .


<s> static bool aarch64_return_in_memory_1 ( const_tree type ) { HOST_WIDE_INT size ; machine_mode ag_mode ; int count ; if ( ! AGGREGATE_TYPE_P ( type ) && TREE_CODE ( type ) != COMPLEX_TYPE && TREE_CODE ( type ) != VECTOR_TYPE ) return false ; if ( aarch64_vfp_is_call_or_return_candidate ( TYPE_MODE ( type ) , type , & ag_mode , & count , NULL , false ) ) return false ; size = int_size_in_bytes ( type ) ; return ( size < 0 || size > 2 * UNITS_PER_WORD ) ; } </s>

Subroutine for aarch64_return_in_memory for types that are not returned in SVE registers .


<s> void mapip_expand_prologue ( ) { long framesize ; long adjust ; rtx sp = NULL_RTX ; rtx fp = NULL_RTX ; framesize = ( frame_info . valid ? frame_info . total_size : compute_frame_size ( get_frame_size ( ) ) ) ; if ( framesize > 0 || frame_pointer_needed ) sp = gen_rtx_REG ( SImode , SP_REGNUM ) ; if ( frame_pointer_needed ) fp = gen_rtx_REG ( SImode , FP_REGNUM ) ; if ( SHOULD_COMBINE_STORE_RESTORE ) { emit_insn ( gen_store_regs ( gen_rtx_REG ( SImode , frame_info . first_reg ) , gen_rtx_REG ( SImode , frame_info . last_reg ) ) ) ; } else { int rmask = frame_info . rmask ; int i , j ; for ( i = 0 ; rmask != 0 ; ) { if ( rmask & 1 ) { for ( j = i ; rmask & 1 ; j ++ ) rmask >>= 1 ; emit_insn ( gen_store_regs ( gen_rtx_REG ( SImode , i ) , gen_rtx_REG ( SImode , j - 1 ) ) ) ; i = j ; } else { rmask >>= 1 ; i ++ ; } } } adjust = framesize - frame_info . regs ; if ( adjust != 0 ) { emit_insn ( gen_subsi3 ( sp , sp , GEN_INT ( adjust ) ) ) ; } if ( frame_pointer_needed ) { if ( framesize > 0 ) { emit_move_insn ( fp , sp ) ; emit_insn ( gen_addsi3 ( fp , fp , GEN_INT ( framesize ) ) ) ; } else { emit_move_insn ( fp , sp ) ; } } } </s>

Output assembler code for a function prologue


<s>
void
BTFDebug
::
beginFunctionImpl
(
const
MachineFunction
*
MF
)
{
auto
*
SP
=
MF
->
getFunction
(
)
.
getSubprogram
(
)
;
auto
*
Unit
=
SP
->
getUnit
(
)
;
if
(
Unit
->
getEmissionKind
(
)
==
DICompileUnit
::
NoDebug
)
{
SkipInstruction
=
true
;
return
;
}
SkipInstruction
=
false
;
if
(
MapDefNotCollected
)
{
processGlobals
(
true
)
;
MapDefNotCollected
=
false
;
}
std
::
unordered_map
<
uint32_t
,
StringRef
>
FuncArgNames
;
for
(
const
DINode
*
DN
:
SP
->
getRetainedNodes
(
)
)
{
if
(
const
auto
*
DV
=
dyn_cast
<
DILocalVariable
>
(
DN
)
)
{
uint32_t
Arg
=
DV
->
getArg
(
)
;
if
(
Arg
)
{
visitTypeEntry
(
DV
->
getType
(
)
)
;
FuncArgNames
[
Arg
]
=
DV
->
getName
(
)
;
}
}
}
uint32_t
ProtoTypeId
;
visitSubroutineType
(
SP
->
getType
(
)
,
true
,
FuncArgNames
,
ProtoTypeId
)
;
uint8_t
Scope
=
SP
->
isLocalToUnit
(
)
BTF
::
FUNC_STATIC
:
BTF
::
FUNC_GLOBAL
;
auto
FuncTypeEntry
=
std
::
make_unique
<
BTFTypeFunc
>
(
SP
->
getName
(
)
,
ProtoTypeId
,
Scope
)
;
uint32_t
FuncTypeId
=
addType
(
std
::
move
(
FuncTypeEntry
)
)
;
for
(
const
auto
&
TypeEntry
:
TypeEntries
)
TypeEntry
->
completeType
(
*
this
)
;
MCSymbol
*
FuncLabel
=
Asm
->
getFunctionBegin
(
)
;
BTFFuncInfo
FuncInfo
;
FuncInfo
.
Label
=
FuncLabel
;
FuncInfo
.
TypeId
=
FuncTypeId
;
if
(
FuncLabel
->
isInSection
(
)
)
{
MCSection
&
Section
=
FuncLabel
->
getSection
(
)
;
const
MCSectionELF
*
SectionELF
=
dyn_cast
<
MCSectionELF
>
(
&
Section
)
;
assert
(
SectionELF
&&
"Null section for Function Label"
)
;
SecNameOff
=
addString
(
SectionELF
->
getSectionName
(
)
)
;
}
else
{
SecNameOff
=
addString
(
".text"
)
;
}
FuncInfoTable
[
SecNameOff
]
.
push_back
(
FuncInfo
)
;
}
</s>


<s>
LLVM_DUMP_METHOD
void
Coloring
::
dump
(
)
const
{
dbgs
(
)
<<
"{ Order:   {"
;
for
(
unsigned
I
=
0
;
I
!=
Order
.
size
(
)
;
++
I
)
{
Node
P
=
Order
[
I
]
;
if
(
P
!=
Ignore
)
dbgs
(
)
<<
' '
<<
P
;
else
dbgs
(
)
<<
" -"
;
}
dbgs
(
)
<<
" }\n"
;
dbgs
(
)
<<
"  Needed: {"
;
for
(
Node
N
:
Needed
)
dbgs
(
)
<<
' '
<<
N
;
dbgs
(
)
<<
" }\n"
;
dbgs
(
)
<<
"  Edges: {\n"
;
for
(
auto
E
:
Edges
)
{
dbgs
(
)
<<
"    "
<<
E
.
first
<<
" -> {"
;
for
(
auto
N
:
E
.
second
)
dbgs
(
)
<<
' '
<<
N
;
dbgs
(
)
<<
" }\n"
;
}
dbgs
(
)
<<
"  }\n"
;
static
const
char
*
const
Names
[
]
=
{
"None"
,
"Red"
,
"Black"
}
;
dbgs
(
)
<<
"  Colors: {\n"
;
for
(
auto
C
:
Colors
)
dbgs
(
)
<<
"    "
<<
C
.
first
<<
" -> "
<<
Names
[
C
.
second
]
<<
"\n"
;
dbgs
(
)
<<
"  }\n}\n"
;
}
</s>

Dump the plan to stderr ( for debugging ) .


<s>
void
ARMMCCodeEmitter
::
encodeInstruction
(
const
MCInst
&
MI
,
raw_ostream
&
OS
,
SmallVectorImpl
<
MCFixup
>
&
Fixups
,
const
MCSubtargetInfo
&
STI
)
const
{
const
MCInstrDesc
&
Desc
=
MCII
.
get
(
MI
.
getOpcode
(
)
)
;
uint64_t
TSFlags
=
Desc
.
TSFlags
;
if
(
(
TSFlags
&
ARMII
::
FormMask
)
==
ARMII
::
Pseudo
)
return
;
int
Size
;
if
(
Desc
.
getSize
(
)
==
2
||
Desc
.
getSize
(
)
==
4
)
Size
=
Desc
.
getSize
(
)
;
else
llvm_unreachable
(
"Unexpected instruction size!"
)
;
uint32_t
Binary
=
getBinaryCodeForInstr
(
MI
,
Fixups
,
STI
)
;
if
(
isThumb
(
STI
)
&&
Size
==
4
)
{
EmitConstant
(
Binary
>>
16
,
2
,
OS
)
;
EmitConstant
(
Binary
&
0xffff
,
2
,
OS
)
;
}
else
EmitConstant
(
Binary
,
Size
,
OS
)
;
++
MCNumEmitted
;
}
</s>

Encode the given Inst to bytes and append to CB .


"SIInstrInfo::storeRegToStackSlot - Do not know how to"

Store the specified register of the given register class to the specified stack frame index .


<s> static int c4x_label_ref_used_p ( rtx x , rtx code_label ) { enum rtx_code code ; int i , j ; const char * fmt ; if ( x == 0 ) return 0 ; code = GET_CODE ( x ) ; if ( code == LABEL_REF ) return INSN_UID ( XEXP ( x , 0 ) ) == INSN_UID ( code_label ) ; fmt = GET_RTX_FORMAT ( code ) ; for ( i = GET_RTX_LENGTH ( code ) - 1 ; i >= 0 ; i -- ) { if ( fmt [ i ] == 'e' ) { if ( c4x_label_ref_used_p ( XEXP ( x , i ) , code_label ) ) return 1 ; } else if ( fmt [ i ] == 'E' ) for ( j = XVECLEN ( x , i ) - 1 ; j >= 0 ; j -- ) if ( c4x_label_ref_used_p ( XVECEXP ( x , i , j ) , code_label ) ) return 1 ; } return 0 ; } </s>

The C4x looping instruction needs to be emitted at the top of the loop . Emitting the true RTL for a looping instruction at the top of the loop can cause problems with flow analysis . So instead , a dummy doloop insn is emitted at the end of the loop . This routine checks for the presence of this doloop insn and then searches back to the top of the loop , where it inserts the true looping insn ( provided there are no instructions in the loop which would cause problems ) . Any additional labels can be emitted at this point . In addition , if the desired loop count register was not allocated , this routine does nothing . Before we can create a repeat block looping instruction we have to verify that there are no jumps outside the loop and no jumps outside the loop go into this loop . This can happen in the basic blocks reorder pass . The C4x cpu can not handle this .


<s> Value * PPCTargetLowering :: getSDagStackGuard ( const Module & M ) const { if ( Subtarget . isAIXABI ( ) ) return M . getGlobalVariable ( AIXSSPCanaryWordName ) ; return TargetLowering :: getSDagStackGuard ( M ) ; } </s>

Return the variable that 's previously inserted by insertSSPDeclarations , if any , otherwise return nullptr .


<s> static bool riscv_use_save_libcall ( const struct riscv_frame_info * frame ) { if ( ! TARGET_SAVE_RESTORE || crtl -> calls_eh_return || frame_pointer_needed || cfun -> machine -> interrupt_handler_p ) return false ; return frame -> save_libcall_adjustment != 0 ; } </s>

Determine whether to call GPR save/restore routines .


<s> bool mips_use_ins_ext_p ( rtx op , rtx size , rtx position ) { HOST_WIDE_INT len , pos ; if ( ! ISA_HAS_EXT_INS || ! register_operand ( op , VOIDmode ) || GET_MODE_BITSIZE ( GET_MODE ( op ) ) > BITS_PER_WORD ) return false ; len = INTVAL ( size ) ; pos = INTVAL ( position ) ; if ( len <= 0 || len >= GET_MODE_BITSIZE ( GET_MODE ( op ) ) || pos < 0 || pos + len > GET_MODE_BITSIZE ( GET_MODE ( op ) ) ) return false ; return true ; } </s>

Return true if ( zero_extract OP SIZE POSITION ) can be used as the source of an `` ext '' instruction or the destination of an `` ins '' instruction . OP must be a register operand and the following conditions must hold : 0 < = POSITION < GET_MODE_BITSIZE ( GET_MODE ( op ) ) 0 < SIZE < = GET_MODE_BITSIZE ( GET_MODE ( op ) ) 0 < POSITION + SIZE < = GET_MODE_BITSIZE ( GET_MODE ( op ) ) Also reject lengths equal to a word as they are better handled by the move patterns .


<s> static void arc_autovectorize_vector_sizes ( vector_sizes * sizes ) { if ( TARGET_PLUS_QMACW ) { sizes -> quick_push ( 8 ) ; sizes -> quick_push ( 4 ) ; } } </s>


<s> unsigned AArch64TTI :: getArithmeticInstrCost ( unsigned Opcode , Type * Ty , OperandValueKind Opd1Info , OperandValueKind Opd2Info ) const { std :: pair < unsigned , MVT > LT = TLI -> getTypeLegalizationCost ( Ty ) ; int ISD = TLI -> InstructionOpcodeToISD ( Opcode ) ; switch ( ISD ) { default : return TargetTransformInfo :: getArithmeticInstrCost ( Opcode , Ty , Opd1Info , Opd2Info ) ; case ISD :: ADD : case ISD :: MUL : case ISD :: XOR : case ISD :: OR : case ISD :: AND : return 1 * LT . first ; } } </s>

This is an approximation of reciprocal throughput of a math/logic op .


<s> int iq2000_can_use_return_insn ( void ) { if ( ! reload_completed ) return 0 ; if ( df_regs_ever_live_p ( 31 ) || profile_flag ) return 0 ; if ( cfun -> machine -> initialized ) return cfun -> machine -> total_size == 0 ; return compute_frame_size ( get_frame_size ( ) ) == 0 ; } </s>

Return nonzero if this function is known to have a null epilogue . This allows the optimizer to omit jumps to jumps if no stack was created .


<s>
void
RISCVTTIImpl
::
getUnrollingPreferences
(
Loop
*
L
,
ScalarEvolution
&
SE
,
TTI
::
UnrollingPreferences
&
UP
,
OptimizationRemarkEmitter
*
ORE
)
{
if
(
ST
->
enableDefaultUnroll
(
)
)
return
BasicTTIImplBase
::
getUnrollingPreferences
(
L
,
SE
,
UP
,
ORE
)
;
UP
.
UpperBound
=
true
;
UP
.
OptSizeThreshold
=
0
;
UP
.
PartialOptSizeThreshold
=
0
;
if
(
L
->
getHeader
(
)
->
getParent
(
)
->
hasOptSize
(
)
)
return
;
SmallVector
<
BasicBlock
*
,
4
>
ExitingBlocks
;
L
->
getExitingBlocks
(
ExitingBlocks
)
;
LLVM_DEBUG
(
dbgs
(
)
<<
"Loop has:\n"
<<
"Blocks: "
<<
L
->
getNumBlocks
(
)
<<
"\n"
<<
"Exit blocks: "
<<
ExitingBlocks
.
size
(
)
<<
"\n"
)
;
if
(
ExitingBlocks
.
size
(
)
>
2
)
return
;
if
(
L
->
getNumBlocks
(
)
>
4
)
return
;
if
(
getBooleanLoopAttribute
(
L
,
"llvm.loop.isvectorized"
)
)
return
;
InstructionCost
Cost
=
0
;
for
(
auto
*
BB
:
L
->
getBlocks
(
)
)
{
for
(
auto
&
I
:
*
BB
)
{
if
(
I
.
getType
(
)
->
isVectorTy
(
)
)
return
;
if
(
isa
<
CallInst
>
(
I
)
||
isa
<
InvokeInst
>
(
I
)
)
{
if
(
const
Function
*
F
=
cast
<
CallBase
>
(
I
)
.
getCalledFunction
(
)
)
{
if
(
!
isLoweredToCall
(
F
)
)
continue
;
}
return
;
}
SmallVector
<
const
Value
*
>
Operands
(
I
.
operand_values
(
)
)
;
Cost
+=
getUserCost
(
&
I
,
Operands
,
TargetTransformInfo
::
TCK_SizeAndLatency
)
;
}
}
LLVM_DEBUG
(
dbgs
(
)
<<
"Cost of loop: "
<<
Cost
<<
"\n"
)
;
UP
.
Partial
=
true
;
UP
.
Runtime
=
true
;
UP
.
UnrollRemainder
=
true
;
UP
.
UnrollAndJam
=
true
;
UP
.
UnrollAndJamInnerLoopThreshold
=
60
;
if
(
Cost
<
12
)
UP
.
Force
=
true
;
}
</s>

Get target-customized preferences for the generic loop unrolling transformation .


<s> Relocator :: Result none ( Relocation & pReloc , AArch64Relocator & pParent ) { return Relocator :: OK ; } </s>

Returns true if none of the bits are set .


<s>
void
Thumb1InstrInfo
::
storeRegToStackSlot
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
unsigned
SrcReg
,
bool
isKill
,
int
FI
,
const
TargetRegisterClass
*
RC
,
const
TargetRegisterInfo
*
TRI
)
const
{
assert
(
(
RC
==
&
ARM
::
tGPRRegClass
||
(
TargetRegisterInfo
::
isPhysicalRegister
(
SrcReg
)
&&
isARMLowRegister
(
SrcReg
)
)
)
&&
"Unknown regclass!"
)
;
if
(
RC
==
&
ARM
::
tGPRRegClass
||
(
TargetRegisterInfo
::
isPhysicalRegister
(
SrcReg
)
&&
isARMLowRegister
(
SrcReg
)
)
)
{
DebugLoc
DL
;
if
(
I
!=
MBB
.
end
(
)
)
DL
=
I
->
getDebugLoc
(
)
;
MachineFunction
&
MF
=
*
MBB
.
getParent
(
)
;
MachineFrameInfo
&
MFI
=
*
MF
.
getFrameInfo
(
)
;
MachineMemOperand
*
MMO
=
MF
.
getMachineMemOperand
(
MachinePointerInfo
::
getFixedStack
(
MF
,
FI
)
,
MachineMemOperand
::
MOStore
,
MFI
.
getObjectSize
(
FI
)
,
MFI
.
getObjectAlignment
(
FI
)
)
;
AddDefaultPred
(
BuildMI
(
MBB
,
I
,
DL
,
get
(
ARM
::
tSTRspi
)
)
.
addReg
(
SrcReg
,
getKillRegState
(
isKill
)
)
.
addFrameIndex
(
FI
)
.
addImm
(
0
)
.
addMemOperand
(
MMO
)
)
;
}
}
</s>

ARM
ARM::tGPRRegClass
ARM
"Unknown regclass!"
ARM::tGPRRegClass
ARM
ARM::tSTRspi
0


<s> static std :: unique_ptr < VEOperand > CreateReg ( unsigned RegNum , SMLoc S , SMLoc E ) { auto Op = std :: make_unique < VEOperand > ( k_Register ) ; Op -> Reg . RegNum = RegNum ; Op -> StartLoc = S ; Op -> EndLoc = E ; return Op ; } </s>

CreateReg - Allocate a single virtual register for the given type .


<s> static unsigned int aarch64_detect_scalar_stmt_subtype ( vec_info * vinfo , vect_cost_for_stmt kind , stmt_vec_info stmt_info , unsigned int stmt_cost ) { if ( kind == scalar_stmt && aarch64_extending_load_p ( vinfo , stmt_info ) ) return 0 ; return stmt_cost ; } </s>

STMT_COST is the cost calculated by aarch64_builtin_vectorization_cost for STMT_INFO , which has cost kind KIND . If this is a scalar operation , try to subdivide the target-independent categorization provided by KIND to get a more accurate cost .


<s> static void emitConstantPool ( MCStreamer & Streamer , const MCSection * Section , ConstantPool & CP ) { if ( ! CP . empty ( ) ) { Streamer . SwitchSection ( Section ) ; CP . emitEntries ( Streamer ) ; } } </s>

Print to the current output stream assembly representations of the constants in the constant pool MCP .


<s> MVT getScalarShiftAmountTy ( const DataLayout & , EVT ) const override { return MVT :: i32 ; } </s>

Return the type to use for a scalar shift opcode , given the shifted amount type .


<s> static bool mips_small_register_classes_for_mode_p ( machine_mode mode ATTRIBUTE_UNUSED ) { return TARGET_MIPS16 ; } </s>

Implement target hook small_register_classes_for_mode_p .


<s> bool TVMAsmPrinter :: runOnMachineFunction ( MachineFunction & MF ) { MFI = MF . getInfo < TVMFunctionInfo > ( ) ; return AsmPrinter :: runOnMachineFunction ( MF ) ; } </s>

runOnMachineFunction - Emit the function body .


<s> bool ARCompactInstrInfo :: isPredicable ( MachineInstr * MI ) const { if ( ! MI -> getDesc ( ) . isPredicable ( ) ) { return false ; } if ( MI -> getOperand ( 0 ) . getReg ( ) != MI -> getOperand ( 1 ) . getReg ( ) ) { return false ; } return true ; } </s>

Return true if the specified instruction can be predicated .


<s> bool CSKYAsmBackend :: writeNopData ( raw_ostream & OS , uint64_t Count , const MCSubtargetInfo * STI ) const { if ( Count % 2 ) return false ; while ( Count >= 4 ) { OS . write ( "\xc4\x00\x48\x20" , 4 ) ; Count -= 4 ; } if ( Count ) OS . write ( "\x6c\x03" , 2 ) ; return true ; } </s>

Write an ( optimal ) nop sequence of Count bytes to the given output .


"WebAssembly does not use MCFixupKindInfo flags"

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


<s> void assignValueToAddress ( Register ValVReg , Register Addr , uint64_t Size , MachinePointerInfo & MPO , CCValAssign & VA ) override { MachineFunction & MF = MIRBuilder . getMF ( ) ; auto * MMO = MF . getMachineMemOperand ( MPO , MachineMemOperand :: MOLoad | MachineMemOperand :: MOInvariant , Size , inferAlignFromPtrInfo ( MF , MPO ) ) ; MIRBuilder . buildLoad ( ValVReg , Addr , * MMO ) ; } </s>

An overload which takes an ArgInfo if additional information about the arg is needed .


"\t.word\t0x00000000\t\t# <static chain value>\n"

Worker for TARGET_ASM_TRAMPOLINE_TEMPLATE .


<s> bool mayNeedRelaxation ( const MCInst & , const MCSubtargetInfo & STI ) const override { return false ; } </s>

Check whether the given instruction may need relaxation .


<s> bool SIFoldOperands :: runOnMachineFunction ( MachineFunction & MF ) { if ( skipFunction ( MF . getFunction ( ) ) ) return false ; MRI = & MF . getRegInfo ( ) ; ST = & MF . getSubtarget < GCNSubtarget > ( ) ; TII = ST -> getInstrInfo ( ) ; TRI = & TII -> getRegisterInfo ( ) ; MFI = MF . getInfo < SIMachineFunctionInfo > ( ) ; bool IsIEEEMode = MFI -> getMode ( ) . IEEE ; bool HasNSZ = MFI -> hasNoSignedZerosFPMath ( ) ; for ( MachineBasicBlock * MBB : depth_first ( & MF ) ) { MachineBasicBlock :: iterator I , Next ; for ( I = MBB -> begin ( ) ; I != MBB -> end ( ) ; I = Next ) { Next = std :: next ( I ) ; MachineInstr & MI = * I ; tryFoldInst ( TII , & MI ) ; if ( ! TII -> isFoldableCopy ( MI ) ) { if ( IsIEEEMode || ( ! HasNSZ && ! MI . getFlag ( MachineInstr :: FmNsz ) ) || ! tryFoldOMod ( MI ) ) tryFoldClamp ( MI ) ; continue ; } MachineOperand & OpToFold = MI . getOperand ( 1 ) ; bool FoldingImm = OpToFold . isImm ( ) || OpToFold . isFI ( ) || OpToFold . isGlobal ( ) ; if ( ! FoldingImm && ! OpToFold . isReg ( ) ) continue ; if ( OpToFold . isReg ( ) && ! Register :: isVirtualRegister ( OpToFold . getReg ( ) ) ) continue ; MachineOperand & Dst = MI . getOperand ( 0 ) ; if ( Dst . isReg ( ) && ! Register :: isVirtualRegister ( Dst . getReg ( ) ) ) continue ; foldInstOperand ( MI , OpToFold ) ; } } return false ; } </s>


<s> static machine_mode get_mode_wider_vector ( machine_mode o ) { machine_mode n = GET_MODE_WIDER_MODE ( o ) . require ( ) ; gcc_assert ( GET_MODE_NUNITS ( o ) == GET_MODE_NUNITS ( n ) * 2 ) ; gcc_assert ( GET_MODE_SIZE ( o ) == GET_MODE_SIZE ( n ) ) ; return n ; } </s>

Get a vector mode of the same size as the original but with elements twice as wide . This is only guaranteed to apply to integral vectors .


<s> unsigned HexagonInstrInfo :: isLoadFromStackSlot ( const MachineInstr & MI , int & FrameIndex ) const { switch ( MI . getOpcode ( ) ) { default : break ; case Hexagon :: L2_loadrb_io : case Hexagon :: L2_loadrub_io : case Hexagon :: L2_loadrh_io : case Hexagon :: L2_loadruh_io : case Hexagon :: L2_loadri_io : case Hexagon :: L2_loadrd_io : case Hexagon :: V6_vL32b_ai : case Hexagon :: V6_vL32b_ai_128B : case Hexagon :: V6_vL32Ub_ai : case Hexagon :: V6_vL32Ub_ai_128B : case Hexagon :: LDriw_pred : case Hexagon :: LDriw_mod : case Hexagon :: LDriq_pred_V6 : case Hexagon :: LDriq_pred_vec_V6 : case Hexagon :: LDriv_pseudo_V6 : case Hexagon :: LDrivv_pseudo_V6 : case Hexagon :: LDriq_pred_V6_128B : case Hexagon :: LDriq_pred_vec_V6_128B : case Hexagon :: LDriv_pseudo_V6_128B : case Hexagon :: LDrivv_pseudo_V6_128B : { const MachineOperand OpFI = MI . getOperand ( 1 ) ; if ( ! OpFI . isFI ( ) ) return 0 ; const MachineOperand OpOff = MI . getOperand ( 2 ) ; if ( ! OpOff . isImm ( ) || OpOff . getImm ( ) != 0 ) return 0 ; FrameIndex = OpFI . getIndex ( ) ; return MI . getOperand ( 0 ) . getReg ( ) ; } case Hexagon :: L2_ploadrbt_io : case Hexagon :: L2_ploadrbf_io : case Hexagon :: L2_ploadrubt_io : case Hexagon :: L2_ploadrubf_io : case Hexagon :: L2_ploadrht_io : case Hexagon :: L2_ploadrhf_io : case Hexagon :: L2_ploadruht_io : case Hexagon :: L2_ploadruhf_io : case Hexagon :: L2_ploadrit_io : case Hexagon :: L2_ploadrif_io : case Hexagon :: L2_ploadrdt_io : case Hexagon :: L2_ploadrdf_io : { const MachineOperand OpFI = MI . getOperand ( 2 ) ; if ( ! OpFI . isFI ( ) ) return 0 ; const MachineOperand OpOff = MI . getOperand ( 3 ) ; if ( ! OpOff . isImm ( ) || OpOff . getImm ( ) != 0 ) return 0 ; FrameIndex = OpFI . getIndex ( ) ; return MI . getOperand ( 0 ) . getReg ( ) ; } } return 0 ; } </s>

isLoadFromStackSlot - If the specified machine instruction is a direct load from a stack slot , return the virtual or physical register number of the destination along with the FrameIndex of the loaded stack slot .


"Can't store this register to stack slot"

Store the specified register of the given register class to the specified stack frame index .


<s> static machine_mode aarch64_preferred_simd_mode ( scalar_mode mode ) { poly_int64 bits = TARGET_SVE ? BITS_PER_SVE_VECTOR : 128 ; return aarch64_simd_container_mode ( mode , bits ) ; } </s>

Return 128-bit container as the preferred SIMD mode for MODE .


<s> bool X86TargetLowering :: isLegalAddressingMode ( const DataLayout & DL , const AddrMode & AM , Type * Ty , unsigned AS , Instruction * I ) const { CodeModel :: Model M = getTargetMachine ( ) . getCodeModel ( ) ; if ( ! X86 :: isOffsetSuitableForCodeModel ( AM . BaseOffs , M , AM . BaseGV != nullptr ) ) return false ; if ( AM . BaseGV ) { unsigned GVFlags = Subtarget . classifyGlobalReference ( AM . BaseGV ) ; if ( isGlobalStubReference ( GVFlags ) ) return false ; if ( AM . HasBaseReg && isGlobalRelativeToPICBase ( GVFlags ) ) return false ; if ( ( M != CodeModel :: Small || isPositionIndependent ( ) ) && Subtarget . is64Bit ( ) && ( AM . BaseOffs || AM . Scale > 1 ) ) return false ; } switch ( AM . Scale ) { case 0 : case 1 : case 2 : case 4 : case 8 : break ; case 3 : case 5 : case 9 : if ( AM . HasBaseReg ) return false ; break ; default : return false ; } return true ; } </s>

isLegalAddressingMode - Return true if the addressing mode represented by AM is legal for this target , for a load/store of the specified type .


<s> bool tilegx_legitimate_pic_operand_p ( rtx x ) { if ( tilegx_pic_address_needs_scratch ( x ) ) return false ; if ( tilegx_tls_referenced_p ( x ) ) return false ; return true ; } </s>

Return true if the constant value X is a legitimate general operand when generating PIC code . It is given that flag_pic is on and that X satisfies CONSTANT_P .


<s> void MipsTargetELFStreamer :: emitLabel ( MCSymbol * S ) { auto * Symbol = cast < MCSymbolELF > ( S ) ; getStreamer ( ) . getAssembler ( ) . registerSymbol ( * Symbol ) ; uint8_t Type = Symbol -> getType ( ) ; if ( Type != ELF :: STT_FUNC ) return ; if ( isMicroMipsEnabled ( ) ) Symbol -> setOther ( ELF :: STO_MIPS_MICROMIPS ) ; } </s>

Emit a label for Symbol into the current section .


<s> bool MipsTargetELFStreamer :: emitDirectiveCpRestore ( int Offset , std :: function < unsigned ( ) > GetATReg , SMLoc IDLoc , const MCSubtargetInfo * STI ) { MipsTargetStreamer :: emitDirectiveCpRestore ( Offset , GetATReg , IDLoc , STI ) ; if ( ! Pic || ( getABI ( ) . IsN32 ( ) || getABI ( ) . IsN64 ( ) ) ) return true ; emitStoreWithImmOffset ( Mips :: SW , Mips :: GP , Mips :: SP , Offset , GetATReg , IDLoc , STI ) ; return true ; } </s>

Mips Mips Mips Mips::SW Mips::GP Mips::SP


<s> static bool avr_frame_pointer_required_p ( void ) { return ( cfun -> calls_alloca || cfun -> calls_setjmp || cfun -> has_nonlocal_label || crtl -> args . info . nregs == 0 || get_frame_size ( ) > 0 ) ; } </s>

Return 1 if frame pointer for current function required .


<s> unsigned HexagonTTIImpl :: getNumberOfRegisters ( bool Vector ) const { if ( Vector ) return HexagonAutoHVX && getST ( ) -> useHVXOps ( ) ? 32 : 0 ; return 32 ; } </s>


<s> virtual bool isUnconditionalBranch ( const MCInst & Inst ) const { if ( Inst . getOpcode ( ) == ARM :: Bcc && Inst . getOperand ( 1 ) . getImm ( ) == ARMCC :: AL ) return true ; return MCInstrAnalysis :: isUnconditionalBranch ( Inst ) ; } </s>

Return true if this is a branch which always transfers control flow to some other block .


<s>
const
CallLowering
*
getCallLowering
(
)
const
override
{
assert
(
GISel
&&
"Access to GlobalISel APIs not set"
)
;
return
GISel
->
getCallLowering
(
)
;
}
</s>

AMDGPU
"Access to GlobalISel APIs not set"


<s> Register SystemZRegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { const SystemZFrameLowering * TFI = getFrameLowering ( MF ) ; return TFI -> hasFP ( MF ) ? SystemZ :: R11D : SystemZ :: R15D ; } </s>


<s> void EmitInstruction ( uint64_t Val , unsigned Size , raw_ostream & OS ) const { for ( unsigned i = 0 ; i < Size ; ++ i ) { unsigned Shift = IsLittleEndian ? i * 8 : ( Size - 1 - i ) * 8 ; EmitByte ( ( Val >> Shift ) & 0xff , OS ) ; } } </s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s> void AArch64AsmPrinter :: emitStartOfAsmFile ( Module & M ) { const Triple & TT = TM . getTargetTriple ( ) ; if ( TT . isOSBinFormatCOFF ( ) ) { MCSymbol * S = MMI -> getContext ( ) . getOrCreateSymbol ( StringRef ( "@feat.00" ) ) ; OutStreamer -> BeginCOFFSymbolDef ( S ) ; OutStreamer -> EmitCOFFSymbolStorageClass ( COFF :: IMAGE_SYM_CLASS_STATIC ) ; OutStreamer -> EmitCOFFSymbolType ( COFF :: IMAGE_SYM_DTYPE_NULL ) ; OutStreamer -> EndCOFFSymbolDef ( ) ; int64_t Feat00Flags = 0 ; if ( M . getModuleFlag ( "cfguard" ) ) { Feat00Flags |= 0x800 ; } if ( M . getModuleFlag ( "ehcontguard" ) ) { Feat00Flags |= 0x4000 ; } OutStreamer -> emitSymbolAttribute ( S , MCSA_Global ) ; OutStreamer -> emitAssignment ( S , MCConstantExpr :: create ( Feat00Flags , MMI -> getContext ( ) ) ) ; } if ( ! TT . isOSBinFormatELF ( ) ) return ; unsigned Flags = 0 ; if ( const auto * BTE = mdconst :: extract_or_null < ConstantInt > ( M . getModuleFlag ( "branch-target-enforcement" ) ) ) if ( BTE -> getZExtValue ( ) ) Flags |= ELF :: GNU_PROPERTY_AARCH64_FEATURE_1_BTI ; if ( const auto * Sign = mdconst :: extract_or_null < ConstantInt > ( M . getModuleFlag ( "sign-return-address" ) ) ) if ( Sign -> getZExtValue ( ) ) Flags |= ELF :: GNU_PROPERTY_AARCH64_FEATURE_1_PAC ; if ( Flags == 0 ) return ; if ( auto * TS = static_cast < AArch64TargetStreamer * > ( OutStreamer -> getTargetStreamer ( ) ) ) TS -> emitNoteSection ( Flags ) ; } </s>

This virtual method can be overridden by targets that want to emit something at the start of their file .


<s> void MSP430RegisterInfo :: eliminateFrameIndex ( MachineBasicBlock :: iterator II , int SPAdj , unsigned FIOperandNum , RegScavenger * RS ) const { assert ( SPAdj == 0 && "Unexpected" ) ; MachineInstr & MI = * II ; MachineBasicBlock & MBB = * MI . getParent ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; const TargetFrameLowering * TFI = MF . getTarget ( ) . getFrameLowering ( ) ; DebugLoc dl = MI . getDebugLoc ( ) ; int FrameIndex = MI . getOperand ( FIOperandNum ) . getIndex ( ) ; unsigned BasePtr = ( TFI -> hasFP ( MF ) ? MSP430 :: FPW : MSP430 :: SPW ) ; int Offset = MF . getFrameInfo ( ) -> getObjectOffset ( FrameIndex ) ; Offset += 2 ; if ( ! TFI -> hasFP ( MF ) ) Offset += MF . getFrameInfo ( ) -> getStackSize ( ) ; else Offset += 2 ; Offset += MI . getOperand ( FIOperandNum + 1 ) . getImm ( ) ; if ( MI . getOpcode ( ) == MSP430 :: ADD16ri ) { const TargetInstrInfo & TII = * MF . getTarget ( ) . getInstrInfo ( ) ; MI . setDesc ( TII . get ( MSP430 :: MOV16rr ) ) ; MI . getOperand ( FIOperandNum ) . ChangeToRegister ( BasePtr , false ) ; if ( Offset == 0 ) return ; unsigned DstReg = MI . getOperand ( 0 ) . getReg ( ) ; if ( Offset < 0 ) BuildMI ( MBB , std :: next ( II ) , dl , TII . get ( MSP430 :: SUB16ri ) , DstReg ) . addReg ( DstReg ) . addImm ( - Offset ) ; else BuildMI ( MBB , std :: next ( II ) , dl , TII . get ( MSP430 :: ADD16ri ) , DstReg ) . addReg ( DstReg ) . addImm ( Offset ) ; return ; } MI . getOperand ( FIOperandNum ) . ChangeToRegister ( BasePtr , false ) ; MI . getOperand ( FIOperandNum + 1 ) . ChangeToImmediate ( Offset ) ; } </s>

This method must be overriden to eliminate abstract frame indices from instructions which may use them .


"Don't know how to handle that operation"


<s> bool NVPTXAsmPrinter :: doInitialization ( Module & M ) { SmallString < 128 > Str1 ; raw_svector_ostream OS1 ( Str1 ) ; MMI = getAnalysisIfAvailable < MachineModuleInfo > ( ) ; MMI -> AnalyzeModule ( M ) ; const_cast < TargetLoweringObjectFile & > ( getObjFileLowering ( ) ) . Initialize ( OutContext , TM ) ; Mang = new Mangler ( OutContext , & TM ) ; emitHeader ( M , OS1 ) ; OutStreamer . EmitRawText ( OS1 . str ( ) ) ; if ( nvptxSubtarget . getDrvInterface ( ) == NVPTX :: CUDA ) recordAndEmitFilenames ( M ) ; GlobalsEmitted = false ; return false ; } </s>

Set up the AsmPrinter when we are working on a new module .


<s> bool Thumb1RegisterInfo :: requiresRegisterScavenging ( const MachineFunction & MF ) const { return ThumbRegScavenging ; } </s>

Returns true if the target requires ( and can make use of ) the register scavenger .


<s> static bool rs6000_must_pass_in_stack ( enum machine_mode mode , tree type ) { if ( DEFAULT_ABI == ABI_AIX || TARGET_64BIT ) return must_pass_in_stack_var_size ( mode , type ) ; else return must_pass_in_stack_var_size_or_pad ( mode , type ) ; } </s>

Return true if TYPE must be passed on the stack and not in registers .


<s> const RegisterBankInfo :: InstructionMapping & MipsRegisterBankInfo :: getInstrMapping ( const MachineInstr & MI ) const { unsigned Opc = MI . getOpcode ( ) ; const RegisterBankInfo :: InstructionMapping & Mapping = getInstrMappingImpl ( MI ) ; if ( Mapping . isValid ( ) ) return Mapping ; using namespace TargetOpcode ; unsigned NumOperands = MI . getNumOperands ( ) ; const ValueMapping * OperandsMapping = & Mips :: ValueMappings [ Mips :: GPRIdx ] ; switch ( Opc ) { case G_TRUNC : case G_ADD : case G_SUB : case G_MUL : case G_LOAD : case G_STORE : case G_ZEXTLOAD : case G_SEXTLOAD : case G_GEP : case G_AND : case G_OR : case G_XOR : case G_SHL : case G_ASHR : case G_LSHR : case G_SDIV : case G_UDIV : case G_SREM : case G_UREM : OperandsMapping = & Mips :: ValueMappings [ Mips :: GPRIdx ] ; break ; case G_CONSTANT : case G_FRAME_INDEX : case G_GLOBAL_VALUE : case G_BRCOND : OperandsMapping = getOperandsMapping ( { & Mips :: ValueMappings [ Mips :: GPRIdx ] , nullptr } ) ; break ; case G_ICMP : OperandsMapping = getOperandsMapping ( { & Mips :: ValueMappings [ Mips :: GPRIdx ] , nullptr , & Mips :: ValueMappings [ Mips :: GPRIdx ] , & Mips :: ValueMappings [ Mips :: GPRIdx ] } ) ; break ; case G_SELECT : OperandsMapping = getOperandsMapping ( { & Mips :: ValueMappings [ Mips :: GPRIdx ] , & Mips :: ValueMappings [ Mips :: GPRIdx ] , & Mips :: ValueMappings [ Mips :: GPRIdx ] , & Mips :: ValueMappings [ Mips :: GPRIdx ] } ) ; break ; default : return getInvalidInstructionMapping ( ) ; } return getInstructionMapping ( DefaultMappingID , 1 , OperandsMapping , NumOperands ) ; } </s>

Get the mapping of the different operands of MI on the register bank .

Mips Mips Mips::ValueMappings Mips::GPRIdx Mips::ValueMappings Mips::GPRIdx Mips::ValueMappings Mips::GPRIdx Mips::ValueMappings Mips::GPRIdx Mips::ValueMappings Mips::GPRIdx Mips::ValueMappings Mips::GPRIdx Mips::ValueMappings Mips::GPRIdx Mips::ValueMappings Mips::GPRIdx Mips::ValueMappings Mips::GPRIdx Mips::ValueMappings Mips::GPRIdx 1


"Not all fixup kinds added to Infos array"


<s> static bool check_required_extensions ( location_t location , tree fndecl , uint64_t required_extensions ) { uint64_t missing_extensions = required_extensions & ~ aarch64_isa_flags ; if ( missing_extensions == 0 ) return check_required_registers ( location , fndecl ) ; static const struct { uint64_t flag ; const char * name ; } extensions [ ] = { SYNTHETIC , FEATURE_STRING ) \ { FLAG_CANONICAL , EXT_NAME } , } ; for ( unsigned int i = 0 ; i < ARRAY_SIZE ( extensions ) ; ++ i ) if ( missing_extensions & extensions [ i ] . flag ) { report_missing_extension ( location , fndecl , extensions [ i ] . name ) ; return false ; } gcc_unreachable ( ) ; } </s>

Check whether all the RVV_REQUIRE_ * values in REQUIRED_EXTENSIONS are enabled .


<s> static int microblaze_address_insns ( rtx x , machine_mode mode ) { struct microblaze_address_info addr ; if ( microblaze_classify_address ( & addr , x , mode , false ) ) { switch ( addr . type ) { case ADDRESS_REG : if ( SMALL_INT ( addr . offset ) ) return 1 ; else return 2 ; case ADDRESS_CONST_INT : if ( SMALL_INT ( x ) ) return 1 ; else return 2 ; case ADDRESS_REG_INDEX : return 1 ; case ADDRESS_SYMBOLIC : case ADDRESS_SYMBOLIC_TXT_REL : case ADDRESS_GOTOFF : return 2 ; case ADDRESS_TLS : switch ( addr . tls_type ) { case TLS_GD : return 2 ; case TLS_LDM : return 2 ; case TLS_DTPREL : return 1 ; default : abort ( ) ; } default : break ; } } return 0 ; } </s>

Return the number of instructions needed to load or store a value of mode MODE at X . Return 0 if X is n't valid for MODE .


<s> bool ix86_expand_pinsr ( rtx * operands ) { rtx dst = operands [ 0 ] ; rtx src = operands [ 3 ] ; unsigned int size = INTVAL ( operands [ 1 ] ) ; unsigned int pos = INTVAL ( operands [ 2 ] ) ; if ( SUBREG_P ( dst ) ) { pos += SUBREG_BYTE ( dst ) * BITS_PER_UNIT ; dst = SUBREG_REG ( dst ) ; } switch ( GET_MODE ( dst ) ) { case V16QImode : case V8HImode : case V4SImode : case V2DImode : case V1TImode : case TImode : { machine_mode srcmode , dstmode ; rtx ( * pinsr ) ( rtx , rtx , rtx , rtx ) ; rtx d ; srcmode = mode_for_size ( size , MODE_INT , 0 ) ; switch ( srcmode ) { case QImode : if ( ! TARGET_SSE4_1 ) return false ; dstmode = V16QImode ; pinsr = gen_sse4_1_pinsrb ; break ; case HImode : if ( ! TARGET_SSE2 ) return false ; dstmode = V8HImode ; pinsr = gen_sse2_pinsrw ; break ; case SImode : if ( ! TARGET_SSE4_1 ) return false ; dstmode = V4SImode ; pinsr = gen_sse4_1_pinsrd ; break ; case DImode : gcc_assert ( TARGET_64BIT ) ; if ( ! TARGET_SSE4_1 ) return false ; dstmode = V2DImode ; pinsr = gen_sse4_1_pinsrq ; break ; default : return false ; } if ( pos & ( size - 1 ) ) return false ; if ( SUBREG_P ( src ) ) { unsigned int srcpos = SUBREG_BYTE ( src ) ; if ( srcpos > 0 ) { rtx extr_ops [ 4 ] ; extr_ops [ 0 ] = gen_reg_rtx ( srcmode ) ; extr_ops [ 1 ] = gen_lowpart ( srcmode , SUBREG_REG ( src ) ) ; extr_ops [ 2 ] = GEN_INT ( size ) ; extr_ops [ 3 ] = GEN_INT ( srcpos * BITS_PER_UNIT ) ; if ( ! ix86_expand_pextr ( extr_ops ) ) return false ; src = extr_ops [ 0 ] ; } else src = gen_lowpart ( srcmode , SUBREG_REG ( src ) ) ; } if ( GET_MODE ( dst ) == dstmode ) d = dst ; else d = gen_reg_rtx ( dstmode ) ; emit_insn ( pinsr ( d , gen_lowpart ( dstmode , dst ) , gen_lowpart ( srcmode , src ) , GEN_INT ( 1 << ( pos / size ) ) ) ) ; if ( d != dst ) emit_move_insn ( dst , gen_lowpart ( GET_MODE ( dst ) , d ) ) ; return true ; } default : return false ; } } </s>

Expand an insert into a vector register through pinsr insn . Return true if successful .


<s> const uint32_t * SIRegisterInfo :: getCallPreservedMask ( const MachineFunction & MF , CallingConv :: ID CC ) const { switch ( CC ) { case CallingConv :: C : case CallingConv :: Fast : case CallingConv :: Cold : return MF . getSubtarget < GCNSubtarget > ( ) . hasGFX90AInsts ( ) ? CSR_AMDGPU_HighRegs_With_AGPRs_RegMask : CSR_AMDGPU_HighRegs_RegMask ; case CallingConv :: AMDGPU_Gfx : return MF . getSubtarget < GCNSubtarget > ( ) . hasGFX90AInsts ( ) ? CSR_AMDGPU_SI_Gfx_With_AGPRs_RegMask : CSR_AMDGPU_SI_Gfx_RegMask ; default : return nullptr ; } } </s>

Return a mask of call-preserved registers for the given calling convention on the current function .


<s> rtx aarch64_reverse_mask ( machine_mode mode , unsigned int nunits ) { rtx mask ; rtvec v = rtvec_alloc ( 16 ) ; unsigned int i , j ; unsigned int usize = GET_MODE_UNIT_SIZE ( mode ) ; gcc_assert ( BYTES_BIG_ENDIAN ) ; gcc_assert ( AARCH64_VALID_SIMD_QREG_MODE ( mode ) ) ; for ( i = 0 ; i < nunits ; i ++ ) for ( j = 0 ; j < usize ; j ++ ) RTVEC_ELT ( v , i * usize + j ) = GEN_INT ( ( i + 1 ) * usize - 1 - j ) ; mask = gen_rtx_CONST_VECTOR ( V16QImode , v ) ; return force_reg ( V16QImode , mask ) ; } </s>

Generate a byte permute mask for a register of mode MODE , which has NUNITS units .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s>
void
ARMTargetLowering
::
ReplaceNodeResults
(
SDNode
*
N
,
SmallVectorImpl
<
SDValue
>
&
Results
,
SelectionDAG
&
DAG
)
{
switch
(
N
->
getOpcode
(
)
)
{
default
:
llvm_unreachable
(
"Don't know how to custom expand this!"
)
;
return
;
case
ISD
::
BIT_CONVERT
:
Results
.
push_back
(
ExpandBIT_CONVERT
(
N
,
DAG
)
)
;
return
;
case
ISD
::
SRL
:
case
ISD
::
SRA
:
{
SDValue
Res
=
LowerShift
(
N
,
DAG
,
Subtarget
)
;
if
(
Res
.
getNode
(
)
)
Results
.
push_back
(
Res
)
;
return
;
}
}
}
</s>

ReplaceNodeResults - Replace the results of node with an illegal result type with new values built out of custom code .

ARM
ARM
"Don't know how to custom expand this!"
ISD::BIT_CONVERT
ISD::SRL
ISD::SRA


<s> bool AArch64CallLowering :: lowerFormalArguments ( MachineIRBuilder & MIRBuilder , const Function & F , ArrayRef < ArrayRef < Register >> VRegs ) const { MachineFunction & MF = MIRBuilder . getMF ( ) ; MachineBasicBlock & MBB = MIRBuilder . getMBB ( ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; auto & DL = F . getParent ( ) -> getDataLayout ( ) ; SmallVector < ArgInfo , 8 > SplitArgs ; unsigned i = 0 ; for ( auto & Arg : F . args ( ) ) { if ( DL . getTypeStoreSize ( Arg . getType ( ) ) . isZero ( ) ) continue ; ArgInfo OrigArg { VRegs [ i ] , Arg . getType ( ) } ; setArgFlags ( OrigArg , i + AttributeList :: FirstArgIndex , DL , F ) ; if ( Arg . hasAttribute ( Attribute :: SwiftAsync ) ) MF . getInfo < AArch64FunctionInfo > ( ) -> setHasSwiftAsyncContext ( true ) ; splitToValueTypes ( OrigArg , SplitArgs , DL , MRI , F . getCallingConv ( ) ) ; ++ i ; } if ( ! MBB . empty ( ) ) MIRBuilder . setInstr ( * MBB . begin ( ) ) ; const AArch64TargetLowering & TLI = * getTLI < AArch64TargetLowering > ( ) ; CCAssignFn * AssignFn = TLI . CCAssignFnForCall ( F . getCallingConv ( ) , false ) ; FormalArgHandler Handler ( MIRBuilder , MRI , AssignFn ) ; if ( ! handleAssignments ( MIRBuilder , SplitArgs , Handler ) ) return false ; AArch64FunctionInfo * FuncInfo = MF . getInfo < AArch64FunctionInfo > ( ) ; uint64_t StackOffset = Handler . StackUsed ; if ( F . isVarArg ( ) ) { auto & Subtarget = MF . getSubtarget < AArch64Subtarget > ( ) ; if ( ! Subtarget . isTargetDarwin ( ) ) { return false ; } StackOffset = alignTo ( Handler . StackUsed , Subtarget . isTargetILP32 ( ) ? 4 : 8 ) ; auto & MFI = MIRBuilder . getMF ( ) . getFrameInfo ( ) ; FuncInfo -> setVarArgsStackIndex ( MFI . CreateFixedObject ( 4 , StackOffset , true ) ) ; } if ( doesCalleeRestoreStack ( F . getCallingConv ( ) , MF . getTarget ( ) . Options . GuaranteedTailCallOpt ) ) { StackOffset = alignTo ( StackOffset , 16 ) ; FuncInfo -> setArgumentStackToRestore ( StackOffset ) ; } FuncInfo -> setBytesInStackArgArea ( StackOffset ) ; auto & Subtarget = MF . getSubtarget < AArch64Subtarget > ( ) ; if ( Subtarget . hasCustomCallingConv ( ) ) Subtarget . getRegisterInfo ( ) -> UpdateCustomCalleeSavedRegs ( MF ) ; handleMustTailForwardedRegisters ( MIRBuilder , AssignFn ) ; MIRBuilder . setMBB ( MBB ) ; return true ; } </s>

This hook must be implemented to lower the incoming ( formal ) arguments , described by VRegs , for GlobalISel .


<s>
bool
SystemZInstrInfo
::
PredicateInstruction
(
MachineInstr
*
MI
,
const
SmallVectorImpl
<
MachineOperand
>
&
Pred
)
const
{
assert
(
Pred
.
size
(
)
==
2
&&
"Invalid condition"
)
;
unsigned
CCValid
=
Pred
[
0
]
.
getImm
(
)
;
unsigned
CCMask
=
Pred
[
1
]
.
getImm
(
)
;
assert
(
CCMask
>
0
&&
CCMask
<
15
&&
"Invalid predicate"
)
;
unsigned
Opcode
=
MI
->
getOpcode
(
)
;
if
(
TM
.
getSubtargetImpl
(
)
->
hasLoadStoreOnCond
(
)
)
{
if
(
unsigned
CondOpcode
=
getConditionalMove
(
Opcode
)
)
{
MI
->
setDesc
(
get
(
CondOpcode
)
)
;
MachineInstrBuilder
(
*
MI
->
getParent
(
)
->
getParent
(
)
,
MI
)
.
addImm
(
CCValid
)
.
addImm
(
CCMask
)
.
addReg
(
SystemZ
::
CC
,
RegState
::
Implicit
)
;
return
true
;
}
}
return
false
;
}
</s>

Convert the instruction into a predicated instruction .


"function must have been generated already"

"should only be called once per function"

runOnModule - Virtual method overriden by subclasses to process the module being operated on .


<s> void SystemZPassConfig :: addIRPasses ( ) { if ( getOptLevel ( ) != CodeGenOpt :: None ) { addPass ( createSystemZTDCPass ( ) ) ; addPass ( createLoopDataPrefetchPass ( ) ) ; } TargetPassConfig :: addIRPasses ( ) ; } </s>

Add common target configurable passes that perform LLVM IR to IR transforms following machine independent optimization .


<s>
DEBUG_FUNCTION
char
*
rs6000_debug_addr_mask
(
addr_mask_type
mask
,
bool
keep_spaces
)
{
static
char
ret
[
8
]
;
char
*
p
=
ret
;
if
(
(
mask
&
RELOAD_REG_VALID
)
!=
0
)
*
p
++
=
'v'
;
else
if
(
keep_spaces
)
*
p
++
=
' '
;
if
(
(
mask
&
RELOAD_REG_MULTIPLE
)
!=
0
)
*
p
++
=
'm'
;
else
if
(
keep_spaces
)
*
p
++
=
' '
;
if
(
(
mask
&
RELOAD_REG_INDEXED
)
!=
0
)
*
p
++
=
'i'
;
else
if
(
keep_spaces
)
*
p
++
=
' '
;
if
(
(
mask
&
RELOAD_REG_OFFSET
)
!=
0
)
*
p
++
=
'o'
;
else
if
(
keep_spaces
)
*
p
++
=
' '
;
if
(
(
mask
&
RELOAD_REG_PRE_INCDEC
)
!=
0
)
*
p
++
=
'+'
;
else
if
(
keep_spaces
)
*
p
++
=
' '
;
if
(
(
mask
&
RELOAD_REG_PRE_MODIFY
)
!=
0
)
*
p
++
=
'+'
;
else
if
(
keep_spaces
)
*
p
++
=
' '
;
if
(
(
mask
&
RELOAD_REG_AND_M16
)
!=
0
)
*
p
++
=
'&'
;
else
if
(
keep_spaces
)
*
p
++
=
' '
;
*
p
=
'\0'
;
return
ret
;
}
</s>

Inner function printing just the address mask for a particular reload register class .


<s> static rtx microblaze_function_arg ( cumulative_args_t cum_v , const function_arg_info & arg ) { CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; rtx ret ; int regbase = - 1 ; int * arg_words = & cum -> arg_words ; cum -> last_arg_fp = 0 ; switch ( arg . mode ) { case E_SFmode : case E_DFmode : case E_VOIDmode : case E_QImode : case E_HImode : case E_SImode : case E_DImode : case E_TImode : regbase = GP_ARG_FIRST ; break ; default : gcc_assert ( GET_MODE_CLASS ( arg . mode ) == MODE_COMPLEX_INT || GET_MODE_CLASS ( arg . mode ) == MODE_COMPLEX_FLOAT ) ; case E_BLKmode : regbase = GP_ARG_FIRST ; break ; } if ( * arg_words >= MAX_ARGS_IN_REGISTERS ) ret = 0 ; else { gcc_assert ( regbase != - 1 ) ; ret = gen_rtx_REG ( arg . mode , regbase + * arg_words ) ; } if ( arg . end_marker_p ( ) ) { if ( cum -> num_adjusts > 0 ) ret = gen_rtx_PARALLEL ( ( machine_mode ) cum -> fp_code , gen_rtvec_v ( cum -> num_adjusts , cum -> adjust ) ) ; } return ret ; } </s>

Return an RTL expression containing the register for the given mode , or 0 if the argument is to be passed on the stack .


<s> unsigned SIInstrInfo :: readlaneVGPRToSGPR ( unsigned SrcReg , MachineInstr & UseMI , MachineRegisterInfo & MRI ) const { const TargetRegisterClass * VRC = MRI . getRegClass ( SrcReg ) ; const TargetRegisterClass * SRC = RI . getEquivalentSGPRClass ( VRC ) ; unsigned DstReg = MRI . createVirtualRegister ( SRC ) ; unsigned SubRegs = RI . getRegSizeInBits ( * VRC ) / 32 ; SmallVector < unsigned , 8 > SRegs ; for ( unsigned i = 0 ; i < SubRegs ; ++ i ) { unsigned SGPR = MRI . createVirtualRegister ( & AMDGPU :: SGPR_32RegClass ) ; BuildMI ( * UseMI . getParent ( ) , UseMI , UseMI . getDebugLoc ( ) , get ( AMDGPU :: V_READFIRSTLANE_B32 ) , SGPR ) . addReg ( SrcReg , 0 , RI . getSubRegFromChannel ( i ) ) ; SRegs . push_back ( SGPR ) ; } MachineInstrBuilder MIB = BuildMI ( * UseMI . getParent ( ) , UseMI , UseMI . getDebugLoc ( ) , get ( AMDGPU :: REG_SEQUENCE ) , DstReg ) ; for ( unsigned i = 0 ; i < SubRegs ; ++ i ) { MIB . addReg ( SRegs [ i ] ) ; MIB . addImm ( RI . getSubRegFromChannel ( i ) ) ; } return DstReg ; } </s>

Copy a value from a VGPR ( SrcReg ) to SGPR .


<s> TargetLowering :: AtomicExpansionKind HexagonTargetLowering :: shouldExpandAtomicLoadInIR ( LoadInst * LI ) const { return LI -> getType ( ) -> getPrimitiveSizeInBits ( ) > 64 ? AtomicExpansionKind :: LLSC : AtomicExpansionKind :: None ; } </s>

Returns how the given ( atomic ) load should be expanded by the IR-level AtomicExpand pass .


<s> const MCPhysReg * PPCRegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { if ( Subtarget . isDarwinABI ( ) ) return Subtarget . isPPC64 ( ) ? ( Subtarget . hasAltivec ( ) ? CSR_Darwin64_Altivec_SaveList : CSR_Darwin64_SaveList ) : ( Subtarget . hasAltivec ( ) ? CSR_Darwin32_Altivec_SaveList : CSR_Darwin32_SaveList ) ; return Subtarget . isPPC64 ( ) ? ( Subtarget . hasAltivec ( ) ? CSR_SVR464_Altivec_SaveList : CSR_SVR464_SaveList ) : ( Subtarget . hasAltivec ( ) ? CSR_SVR432_Altivec_SaveList : CSR_SVR432_SaveList ) ; } </s>


runOnMachineFunction - Emit the function body .


<s> MCObjectWriter * createObjectWriter ( raw_ostream & OS ) const override { return createARMELFObjectWriter ( OS , OSABI , isLittle ( ) ) ; } </s>

Create a new MCObjectWriter instance for use by the assembler backend to emit the final object file .


<s> bool X86TargetLowering :: isFMAFasterThanFMulAndFAdd ( EVT VT ) const { if ( ! Subtarget -> hasAnyFMA ( ) ) return false ; VT = VT . getScalarType ( ) ; if ( ! VT . isSimple ( ) ) return false ; switch ( VT . getSimpleVT ( ) . SimpleTy ) { case MVT :: f32 : case MVT :: f64 : return true ; default : break ; } return false ; } </s>

Return true if an FMA operation is faster than a pair of fmul and fadd instructions .


<s> bool spillCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , ArrayRef < CalleeSavedInfo > CSI , const TargetRegisterInfo * TRI ) const override { return true ; } </s>

spillCalleeSavedRegisters - Issues instruction ( s ) to spill all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of store instructions via storeRegToStackSlot ( ) .


<s> static rtx riscv_force_temporary ( rtx dest , rtx value , bool in_splitter ) { if ( can_create_pseudo_p ( ) && ! in_splitter ) return force_reg ( Pmode , value ) ; else { riscv_emit_move ( dest , value ) ; return dest ; } } </s>

Copy VALUE to a register and return that register . If new pseudos are allowed , copy it into a new register , otherwise use DEST .


<s>
StringRef
getPassName
(
)
const
override
{
return
"TPC Packetizer"
;
}
</s>

getPassName - Return a nice clean name for a pass .


"SIInstrInfo::storeRegToStackSlot - Do not know how to"

Store the specified register of the given register class to the specified stack frame index .


<s> static void aarch64_emit_unop ( rtx dest , optab unoptab , rtx op ) { rtx tmp = expand_unop ( GET_MODE ( dest ) , unoptab , op , dest , 0 ) ; if ( dest != tmp ) emit_move_insn ( dest , tmp ) ; } </s>

Apply UNOPTAB to OP and store the result in DEST .


<s> TargetTransformInfo AMDGPUTargetMachine :: getTargetTransformInfo ( const Function & F ) { return TargetTransformInfo ( AMDGPUTTIImpl ( this , F ) ) ; } </s>

Get a TargetTransformInfo implementation for the target .


"SystemZ DAG preprocessing replacing:\nOld:    "

PreprocessISelDAG - This hook allows targets to hack on the graph before instruction selection starts .


<s> DenseSet < unsigned > * LinearizedRegion :: getLiveOuts ( ) { return & LiveOuts ; } </s>

Search MBB for a definition of PhysReg and insert it into Defs .


"Can't store this register to stack slot"


<s>
bool
MSP430AsmPrinter
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
SetupMachineFunction
(
MF
)
;
O
<<
"\n\n"
;
emitFunctionHeader
(
MF
)
;
for
(
MachineFunction
::
const_iterator
I
=
MF
.
begin
(
)
,
E
=
MF
.
end
(
)
;
I
!=
E
;
++
I
)
{
if
(
!
VerboseAsm
&&
(
I
->
pred_empty
(
)
||
I
->
isOnlyReachableByFallthrough
(
)
)
)
{
}
else
{
printBasicBlockLabel
(
I
,
true
,
true
,
VerboseAsm
)
;
O
<<
'\n'
;
}
for
(
MachineBasicBlock
::
const_iterator
II
=
I
->
begin
(
)
,
E
=
I
->
end
(
)
;
II
!=
E
;
++
II
)
printMachineInstruction
(
II
)
;
}
if
(
TAI
->
hasDotTypeDotSizeDirective
(
)
)
O
<<
"\t.size\t"
<<
CurrentFnName
<<
", .-"
<<
CurrentFnName
<<
'\n'
;
O
.
flush
(
)
;
return
false
;
}
</s>


<s> static cpp_hashnode * s390_macro_to_expand ( cpp_reader * pfile , const cpp_token * tok ) { cpp_hashnode * expand_this = tok -> val . node . node ; cpp_hashnode * ident ; static bool expand_bool_p = false ; int idx = 0 ; enum rid rid_code ; if ( ! TARGET_ZVECTOR ) return NULL ; ident = s390_categorize_keyword ( tok ) ; if ( ident != expand_this ) expand_this = NULL ; if ( expand_bool_p && ident == C_CPP_HASHNODE ( __bool_keyword ) ) { expand_bool_p = false ; return ident ; } if ( ident != C_CPP_HASHNODE ( __vector_keyword ) ) return expand_this ; do tok = cpp_peek_token ( pfile , idx ++ ) ; while ( tok -> type == CPP_PADDING ) ; ident = s390_categorize_keyword ( tok ) ; if ( ! ident ) return expand_this ; if ( ident == C_CPP_HASHNODE ( __bool_keyword ) ) { expand_bool_p = true ; return C_CPP_HASHNODE ( __vector_keyword ) ; } if ( ident == C_CPP_HASHNODE ( __vector_keyword ) ) return expand_this ; rid_code = ( enum rid ) ( ident -> rid_code ) ; if ( ident -> type == NT_MACRO ) { do ( void ) cpp_get_token ( pfile ) ; while ( -- idx > 0 ) ; do tok = cpp_peek_token ( pfile , idx ++ ) ; while ( tok -> type == CPP_PADDING ) ; ident = s390_categorize_keyword ( tok ) ; if ( ident == C_CPP_HASHNODE ( __bool_keyword ) ) { expand_bool_p = true ; return C_CPP_HASHNODE ( __vector_keyword ) ; } else if ( ident ) rid_code = ( enum rid ) ( ident -> rid_code ) ; } if ( rid_code == RID_UNSIGNED || rid_code == RID_LONG || rid_code == RID_SHORT || rid_code == RID_SIGNED || rid_code == RID_INT || rid_code == RID_CHAR || rid_code == RID_DOUBLE ) { expand_this = C_CPP_HASHNODE ( __vector_keyword ) ; do tok = cpp_peek_token ( pfile , idx ++ ) ; while ( tok -> type == CPP_PADDING ) ; ident = s390_categorize_keyword ( tok ) ; if ( ident == C_CPP_HASHNODE ( __bool_keyword ) ) expand_bool_p = true ; else { do tok = cpp_peek_token ( pfile , idx ++ ) ; while ( tok -> type == CPP_PADDING ) ; ident = s390_categorize_keyword ( tok ) ; if ( ident == C_CPP_HASHNODE ( __bool_keyword ) ) expand_bool_p = true ; } } return expand_this ; } </s>

Called to decide whether a conditional macro should be expanded . Since we have exactly one such macro ( i.e , 'vector ' ) , we do not need to examine the 'tok ' parameter .


<s> bool BPFTargetLowering :: isOffsetFoldingLegal ( const GlobalAddressSDNode * GA ) const { return false ; } </s>

Return true if folding a constant offset with the given GlobalAddress is legal .


<s> const std :: string getName ( ) const override { return "AAAMDFlatWorkGroupSize" ; } </s>

Return a string with the name of the plan and the applicable VFs and UFs .


<s> std :: pair < unsigned , const TargetRegisterClass * > AArch64TargetLowering :: getRegForInlineAsmConstraint ( const std :: string & Constraint , MVT VT ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { case 'r' : if ( VT . getSizeInBits ( ) <= 32 ) return std :: make_pair ( 0U , & AArch64 :: GPR32RegClass ) ; else if ( VT == MVT :: i64 ) return std :: make_pair ( 0U , & AArch64 :: GPR64RegClass ) ; break ; case 'w' : if ( VT == MVT :: f16 ) return std :: make_pair ( 0U , & AArch64 :: FPR16RegClass ) ; else if ( VT == MVT :: f32 ) return std :: make_pair ( 0U , & AArch64 :: FPR32RegClass ) ; else if ( VT . getSizeInBits ( ) == 64 ) return std :: make_pair ( 0U , & AArch64 :: FPR64RegClass ) ; else if ( VT . getSizeInBits ( ) == 128 ) return std :: make_pair ( 0U , & AArch64 :: FPR128RegClass ) ; break ; } } return TargetLowering :: getRegForInlineAsmConstraint ( Constraint , VT ) ; } </s>

Given a physical register constraint ( e.g .


Set the cpu type and print out other fancy things , at the top of the file .


<s>
const
char
*
host_detect_local_cpu
(
int
argc
,
const
char
*
*
argv
)
{
const
char
*
val
=
;
char
buf
[
128
]
;
FILE
*
f
=
;
bool
arch
;
const
struct
vendor_cpu
*
cpu_table
=
;
char
*
fcpu_info
=
;
if
(
argc
<
1
)
goto
not_found
;
arch
=
strcmp
(
argv
[
0
]
,
"arch"
)
==
0
;
if
(
!
arch
&&
strcmp
(
argv
[
0
]
,
"cpu"
)
!=
0
&&
strcmp
(
argv
[
0
]
,
"tune"
)
)
goto
not_found
;
fcpu_info
=
getenv
(
"GCC_CPUINFO"
)
;
if
(
fcpu_info
)
f
=
fopen
(
fcpu_info
,
"r"
)
;
else
f
=
fopen
(
"/proc/cpuinfo"
,
"r"
)
;
if
(
f
==
)
goto
not_found
;
while
(
fgets
(
buf
,
sizeof
(
buf
)
,
f
)
!=
)
{
if
(
strncmp
(
buf
,
"CPU implementer"
,
sizeof
(
"CPU implementer"
)
1
)
==
0
)
{
int
i
;
for
(
i
=
0
;
vendors_table
[
i
]
.
vendor_no
!=
;
i
++
)
if
(
strstr
(
buf
,
vendors_table
[
i
]
.
vendor_no
)
!=
)
{
cpu_table
=
vendors_table
[
i
]
.
vendor_parts
;
break
;
}
}
if
(
strncmp
(
buf
,
"CPU part"
,
sizeof
(
"CPU part"
)
1
)
==
0
)
{
int
i
;
if
(
cpu_table
==
)
goto
not_found
;
for
(
i
=
0
;
cpu_table
[
i
]
.
part_no
!=
;
i
++
)
if
(
strstr
(
buf
,
cpu_table
[
i
]
.
part_no
)
!=
)
{
val
=
arch
cpu_table
[
i
]
.
arch_name
:
cpu_table
[
i
]
.
cpu_name
;
break
;
}
break
;
}
}
if
(
val
)
{
fclose
(
f
)
;
return
concat
(
"-m"
,
argv
[
0
]
,
"="
,
val
,
)
;
}
not_found
:
{
unsigned
int
i
;
unsigned
int
opt
;
const
char
*
search
[
]
=
{
,
"arch"
}
;
if
(
f
)
fclose
(
f
)
;
search
[
0
]
=
argv
[
0
]
;
for
(
opt
=
0
;
opt
<
ARRAY_SIZE
(
search
)
;
opt
++
)
for
(
i
=
0
;
i
<
ARRAY_SIZE
(
configure_default_options
)
;
i
++
)
if
(
strcmp
(
configure_default_options
[
i
]
.
name
,
search
[
opt
]
)
==
0
)
return
concat
(
"-m"
,
search
[
opt
]
,
"="
,
configure_default_options
[
i
]
.
value
,
)
;
return
;
}
}
</s>

This will be called by the spec parser in gcc.cc when it sees a % : local_cpu_detect ( args ) construct . Currently it will be called with either `` cpu '' or `` tune '' as argument depending on if -mcpu=native or -mtune=native is to be substituted . It returns a string containing new command line parameters to be put at the place of the above two options , depending on what CPU this is executed . E.g . `` -mcpu=ultrasparc3 '' on an UltraSPARC III for -mcpu=native . If the routine ca n't detect a known processor , the -mcpu or -mtune option is discarded . ARGC and ARGV are set depending on the actual arguments given in the spec .


<s> int rs6000_emit_vector_cond_expr ( rtx dest , rtx op_true , rtx op_false , rtx cond , rtx cc_op0 , rtx cc_op1 ) { machine_mode dest_mode = GET_MODE ( dest ) ; machine_mode mask_mode = GET_MODE ( cc_op0 ) ; enum rtx_code rcode = GET_CODE ( cond ) ; rtx mask ; bool invert_move = false ; if ( VECTOR_UNIT_NONE_P ( dest_mode ) ) return 0 ; gcc_assert ( GET_MODE_SIZE ( dest_mode ) == GET_MODE_SIZE ( mask_mode ) && GET_MODE_NUNITS ( dest_mode ) == GET_MODE_NUNITS ( mask_mode ) ) ; switch ( rcode ) { case NE : case UNLE : case UNLT : case UNGE : case UNGT : invert_move = true ; rcode = reverse_condition_maybe_unordered ( rcode ) ; if ( rcode == UNKNOWN ) return 0 ; break ; case GE : case LE : if ( GET_MODE_CLASS ( mask_mode ) == MODE_VECTOR_INT ) { invert_move = true ; rcode = reverse_condition ( rcode ) ; } break ; case GTU : case GEU : case LTU : case LEU : if ( rcode == GEU || rcode == LEU ) { invert_move = true ; rcode = reverse_condition ( rcode ) ; } break ; default : break ; } mask = rs6000_emit_vector_compare ( rcode , cc_op0 , cc_op1 , mask_mode ) ; if ( ! mask ) return 0 ; if ( mask_mode != dest_mode ) mask = simplify_gen_subreg ( dest_mode , mask , mask_mode , 0 ) ; if ( invert_move ) std :: swap ( op_true , op_false ) ; if ( GET_MODE_CLASS ( dest_mode ) == MODE_VECTOR_INT && ( GET_CODE ( op_true ) == CONST_VECTOR || GET_CODE ( op_false ) == CONST_VECTOR ) ) { rtx constant_0 = CONST0_RTX ( dest_mode ) ; rtx constant_m1 = CONSTM1_RTX ( dest_mode ) ; if ( op_true == constant_m1 && op_false == constant_0 ) { emit_move_insn ( dest , mask ) ; return 1 ; } else if ( op_true == constant_0 && op_false == constant_m1 ) { emit_insn ( gen_rtx_SET ( dest , gen_rtx_NOT ( dest_mode , mask ) ) ) ; return 1 ; } if ( op_true == constant_m1 ) op_true = mask ; if ( op_false == constant_0 ) op_false = mask ; } if ( ! REG_P ( op_true ) && ! SUBREG_P ( op_true ) ) op_true = force_reg ( dest_mode , op_true ) ; if ( ! REG_P ( op_false ) && ! SUBREG_P ( op_false ) ) op_false = force_reg ( dest_mode , op_false ) ; rtx tmp = gen_rtx_IOR ( dest_mode , gen_rtx_AND ( dest_mode , gen_rtx_NOT ( dest_mode , mask ) , op_false ) , gen_rtx_AND ( dest_mode , mask , op_true ) ) ; emit_insn ( gen_rtx_SET ( dest , tmp ) ) ; return 1 ; } </s>

Emit vector conditional expression . DEST is destination . OP1 and OP2 are two VEC_COND_EXPR operands . CC_OP0 and CC_OP1 are the two operands for the relation operation COND .


<s>
const
char
*
R600ClauseMergePass
::
getPassName
(
)
const
{
return
"R600 Merge Clause Markers Pass"
;
}
</s>


"Only 24-bit should have 3 byte stack slots"


<s> const MCSymbol * NVPTXAsmPrinter :: getFunctionFrameSymbol ( ) const { SmallString < 128 > Str ; raw_svector_ostream ( Str ) << DEPOTNAME << getFunctionNumber ( ) ; return OutContext . getOrCreateSymbol ( Str ) ; } </s>

Return symbol for the function pseudo stack if the stack frame is not a register based .


<s> static bool aarch64_symbol_binds_local_p ( const_rtx x ) { return ( SYMBOL_REF_DECL ( x ) ? targetm . binds_local_p ( SYMBOL_REF_DECL ( x ) ) : SYMBOL_REF_LOCAL_P ( x ) ) ; } </s>

Return true if SYMBOL_REF X binds locally .


<s> int floating_exact_log2 ( rtx x ) { REAL_VALUE_TYPE r , r1 ; int exp ; REAL_VALUE_FROM_CONST_DOUBLE ( r , x ) ; if ( REAL_VALUES_LESS ( r , dconst1 ) ) return 0 ; exp = real_exponent ( & r ) ; real_2expN ( & r1 , exp ) ; if ( REAL_VALUES_EQUAL ( r1 , r ) ) return exp ; return 0 ; } </s>

If X is a floating-point constant , return the logarithm of X base 2 , or 0 if X is not a power of 2 .


<s> static unsigned int mips_hard_regno_nregs ( unsigned int regno , machine_mode mode ) { if ( ST_REG_P ( regno ) ) return ( GET_MODE_SIZE ( mode ) + 3 ) / 4 ; if ( FP_REG_P ( regno ) ) { if ( MSA_SUPPORTED_MODE_P ( mode ) ) return 1 ; return ( GET_MODE_SIZE ( mode ) + UNITS_PER_FPREG - 1 ) / UNITS_PER_FPREG ; } return ( GET_MODE_SIZE ( mode ) + UNITS_PER_WORD - 1 ) / UNITS_PER_WORD ; } </s>


<s> static rtx ix86_function_arg ( cumulative_args_t cum_v , machine_mode omode , const_tree type , bool named ) { CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; machine_mode mode = omode ; HOST_WIDE_INT bytes , words ; rtx arg ; if ( ! cum -> caller && cfun -> machine -> func_type != TYPE_NORMAL ) { gcc_assert ( type != NULL_TREE ) ; if ( POINTER_TYPE_P ( type ) ) { gcc_assert ( TYPE_MODE ( type ) == Pmode ) ; arg = plus_constant ( Pmode , arg_pointer_rtx , - UNITS_PER_WORD ) ; } else { gcc_assert ( cfun -> machine -> func_type == TYPE_EXCEPTION && TREE_CODE ( type ) == INTEGER_TYPE && TYPE_MODE ( type ) == word_mode ) ; arg = gen_rtx_MEM ( word_mode , plus_constant ( Pmode , arg_pointer_rtx , - 2 * UNITS_PER_WORD ) ) ; } return arg ; } if ( mode == BLKmode ) bytes = int_size_in_bytes ( type ) ; else bytes = GET_MODE_SIZE ( mode ) ; words = CEIL ( bytes , UNITS_PER_WORD ) ; if ( type && TREE_CODE ( type ) == VECTOR_TYPE ) mode = type_natural_mode ( type , cum , false ) ; if ( TARGET_64BIT ) { enum calling_abi call_abi = cum ? cum -> call_abi : ix86_abi ; if ( call_abi == MS_ABI ) arg = function_arg_ms_64 ( cum , mode , omode , named , bytes ) ; else arg = function_arg_64 ( cum , mode , omode , type , named ) ; } else arg = function_arg_32 ( cum , mode , omode , type , bytes , words ) ; if ( arg == NULL_RTX && cum -> caller ) cfun -> machine -> outgoing_args_on_stack = true ; return arg ; } </s>

Return where to put the arguments to a function . Return zero to push the argument on the stack , or a hard register in which to store the argument . MODE is the argument 's machine mode . TYPE is the data type of the argument . It is null for libcalls where that information may not be available . CUM gives information about the preceding args and about the function being called . NAMED is nonzero if this argument is a named parameter ( otherwise it is an extra parameter matching an ellipsis ) .


<s> bool SparcDAGToDAGISel :: SelectInlineAsmMemoryOperand ( const SDValue & Op , unsigned ConstraintID , std :: vector < SDValue > & OutOps ) { SDValue Op0 , Op1 ; switch ( ConstraintID ) { default : return true ; case InlineAsm :: Constraint_i : case InlineAsm :: Constraint_m : if ( ! SelectADDRrr ( Op , Op0 , Op1 ) ) SelectADDRri ( Op , Op0 , Op1 ) ; break ; } OutOps . push_back ( Op0 ) ; OutOps . push_back ( Op1 ) ; return false ; } </s>

SelectInlineAsmMemoryOperand - Select the specified address as a target addressing mode , according to the specified constraint .


<s>
unsigned
char
M68kSubtarget
::
classifyLocalReference
(
const
GlobalValue
*
GV
)
const
{
switch
(
TM
.
getCodeModel
(
)
)
{
default
:
llvm_unreachable
(
"Unsupported code model"
)
;
case
CodeModel
::
Small
:
case
CodeModel
::
Kernel
:
{
return
M68kII
::
MO_PC_RELATIVE_ADDRESS
;
}
case
CodeModel
::
Medium
:
{
if
(
isPositionIndependent
(
)
)
{
if
(
atLeastM68020
(
)
)
{
return
M68kII
::
MO_PC_RELATIVE_ADDRESS
;
}
return
M68kII
::
MO_GOTOFF
;
}
else
{
if
(
atLeastM68020
(
)
)
{
return
M68kII
::
MO_PC_RELATIVE_ADDRESS
;
}
return
M68kII
::
MO_ABSOLUTE_ADDRESS
;
}
}
}
}
</s>

Classify a global variable reference for the current subtarget according to how we should reference it in a non-pcrel context .


<s> void MipsRegisterInfo :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { MBB . erase ( I ) ; } </s>

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .


<s> bool isUnknown ( ) const { return MF == NULL ; } </s>

Tests if this MemDepResult represents a query which can not and/or will not be computed .


<s> bool ARMBaseInstrInfo :: hasLowDefLatency ( const TargetSchedModel & SchedModel , const MachineInstr & DefMI , unsigned DefIdx ) const { const InstrItineraryData * ItinData = SchedModel . getInstrItineraries ( ) ; if ( ! ItinData || ItinData -> isEmpty ( ) ) return false ; unsigned DDomain = DefMI . getDesc ( ) . TSFlags & ARMII :: DomainMask ; if ( DDomain == ARMII :: DomainGeneral ) { unsigned DefClass = DefMI . getDesc ( ) . getSchedClass ( ) ; int DefCycle = ItinData -> getOperandCycle ( DefClass , DefIdx ) ; return ( DefCycle != - 1 && DefCycle <= 2 ) ; } return false ; } </s>

Compute operand latency of a def of 'Reg ' .

ARM ARM ARMII::DomainMask ARMII::DomainGeneral 1 2


<s> SDValue X86SelectionDAGInfo :: EmitTargetCodeForMemcpy ( SelectionDAG & DAG , const SDLoc & dl , SDValue Chain , SDValue Dst , SDValue Src , SDValue Size , Align Alignment , bool isVolatile , bool AlwaysInline , bool , MachinePointerInfo DstPtrInfo , MachinePointerInfo SrcPtrInfo ) const { if ( DstPtrInfo . getAddrSpace ( ) >= 256 || SrcPtrInfo . getAddrSpace ( ) >= 256 ) return SDValue ( ) ; const MCPhysReg ClobberSet [ ] = { X86 :: RCX , X86 :: RSI , X86 :: RDI , X86 :: ECX , X86 :: ESI , X86 :: EDI } ; if ( isBaseRegConflictPossible ( DAG , ClobberSet ) ) return SDValue ( ) ; const X86Subtarget & Subtarget = DAG . getMachineFunction ( ) . getSubtarget < X86Subtarget > ( ) ; if ( UseFSRMForMemcpy && Subtarget . hasFSRM ( ) ) return emitRepmovs ( Subtarget , DAG , dl , Chain , Dst , Src , Size , MVT :: i8 ) ; if ( ConstantSDNode * ConstantSize = dyn_cast < ConstantSDNode > ( Size ) ) return emitConstantSizeRepmov ( DAG , Subtarget , dl , Chain , Dst , Src , ConstantSize -> getZExtValue ( ) , Size . getValueType ( ) , Alignment . value ( ) , isVolatile , AlwaysInline , DstPtrInfo , SrcPtrInfo ) ; return SDValue ( ) ; } </s>

Emit target-specific code that performs a memcpy .


<s> virtual void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . addRequired < AAResultsWrapperPass > ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> bool X86FastISel :: tryToFoldLoadIntoMI ( MachineInstr * MI , unsigned OpNo , const LoadInst * LI ) { const Value * Ptr = LI -> getPointerOperand ( ) ; X86AddressMode AM ; if ( ! X86SelectAddress ( Ptr , AM ) ) return false ; const X86InstrInfo & XII = ( const X86InstrInfo & ) TII ; unsigned Size = DL . getTypeAllocSize ( LI -> getType ( ) ) ; unsigned Alignment = LI -> getAlignment ( ) ; if ( Alignment == 0 ) Alignment = DL . getABITypeAlignment ( LI -> getType ( ) ) ; SmallVector < MachineOperand , 8 > AddrOps ; AM . getFullAddress ( AddrOps ) ; MachineInstr * Result = XII . foldMemoryOperandImpl ( * FuncInfo . MF , MI , OpNo , AddrOps , Size , Alignment , true ) ; if ( ! Result ) return false ; Result -> addMemOperand ( * FuncInfo . MF , createMachineMemOperandFor ( LI ) ) ; FuncInfo . MBB -> insert ( FuncInfo . InsertPt , Result ) ; MI -> eraseFromParent ( ) ; return true ; } </s>

The specified machine instr operand is a vreg , and that vreg is being provided by the specified load instruction .


<s> bool HexagonTTIImpl :: isLegalMaskedStore ( Type * DataType , Align ) { return HexagonMaskedVMem && isTypeForHVX ( DataType ) ; } </s>

Return true if the target supports masked store .


<s> LLVM_DUMP_METHOD void ValueEnumerator :: dump ( ) const { print ( dbgs ( ) , ValueMap , "Default" ) ; dbgs ( ) << '\n' ; print ( dbgs ( ) , MetadataMap , "MetaData" ) ; dbgs ( ) << '\n' ; } </s>

Dump the plan to stderr ( for debugging ) .


<s> void arm_order_regs_for_local_alloc ( void ) { const int arm_reg_alloc_order [ ] = REG_ALLOC_ORDER ; memcpy ( reg_alloc_order , arm_reg_alloc_order , sizeof ( reg_alloc_order ) ) ; if ( TARGET_THUMB ) memcpy ( reg_alloc_order , thumb_core_reg_alloc_order , sizeof ( thumb_core_reg_alloc_order ) ) ; } </s>

Adjust register allocation order when compiling for Thumb .


<s> static struct machine_function * nds32_init_machine_status ( void ) { struct machine_function * machine ; machine = ggc_cleared_alloc < machine_function > ( ) ; machine -> use_eh_return_p = 0 ; machine -> naked_p = 0 ; machine -> fp_as_gp_p = 0 ; machine -> strict_aligned_p = 0 ; machine -> attr_naked_p = 0 ; machine -> attr_no_prologue_p = 0 ; return machine ; } </s>

Function to save and restore machine-specific function data .


<s>
SDValue
AMDGPUTargetLowering
::
LowerOperation
(
SDValue
Op
,
SelectionDAG
&
DAG
)
const
{
switch
(
Op
.
getOpcode
(
)
)
{
default
:
Op
->
print
(
errs
(
)
,
&
DAG
)
;
llvm_unreachable
(
"Custom lowering code for this"
"instruction is not implemented yet!"
)
;
break
;
case
ISD
::
SIGN_EXTEND_INREG
:
return
LowerSIGN_EXTEND_INREG
(
Op
,
DAG
)
;
case
ISD
::
CONCAT_VECTORS
:
return
LowerCONCAT_VECTORS
(
Op
,
DAG
)
;
case
ISD
::
EXTRACT_SUBVECTOR
:
return
LowerEXTRACT_SUBVECTOR
(
Op
,
DAG
)
;
case
ISD
::
INTRINSIC_WO_CHAIN
:
return
LowerINTRINSIC_WO_CHAIN
(
Op
,
DAG
)
;
case
ISD
::
UDIVREM
:
return
LowerUDIVREM
(
Op
,
DAG
)
;
case
ISD
::
SDIVREM
:
return
LowerSDIVREM
(
Op
,
DAG
)
;
case
ISD
::
FREM
:
return
LowerFREM
(
Op
,
DAG
)
;
case
ISD
::
FCEIL
:
return
LowerFCEIL
(
Op
,
DAG
)
;
case
ISD
::
FTRUNC
:
return
LowerFTRUNC
(
Op
,
DAG
)
;
case
ISD
::
FRINT
:
return
LowerFRINT
(
Op
,
DAG
)
;
case
ISD
::
FNEARBYINT
:
return
LowerFNEARBYINT
(
Op
,
DAG
)
;
case
ISD
::
FROUND
:
return
LowerFROUND
(
Op
,
DAG
)
;
case
ISD
::
FFLOOR
:
return
LowerFFLOOR
(
Op
,
DAG
)
;
case
ISD
::
SINT_TO_FP
:
return
LowerSINT_TO_FP
(
Op
,
DAG
)
;
case
ISD
::
UINT_TO_FP
:
return
LowerUINT_TO_FP
(
Op
,
DAG
)
;
case
ISD
::
FP_TO_FP16
:
return
LowerFP_TO_FP16
(
Op
,
DAG
)
;
case
ISD
::
FP_TO_SINT
:
return
LowerFP_TO_SINT
(
Op
,
DAG
)
;
case
ISD
::
FP_TO_UINT
:
return
LowerFP_TO_UINT
(
Op
,
DAG
)
;
case
ISD
::
CTLZ
:
case
ISD
::
CTLZ_ZERO_UNDEF
:
return
LowerCTLZ
(
Op
,
DAG
)
;
case
ISD
::
DYNAMIC_STACKALLOC
:
return
LowerDYNAMIC_STACKALLOC
(
Op
,
DAG
)
;
}
return
Op
;
}
</s>

LowerOperation - Provide custom lowering hooks for some operations .


"function_adv: words = %2d, mode = %4s, named = %d, size = %3d\n"

A C statement ( sans semicolon ) to update the summarizer variable CUM to advance past an argument in the argument list . The values MODE , TYPE and NAMED describe that argument . Once this is done , the variable CUM is suitable for analyzing the * following * argument with ` FUNCTION_ARG ' , etc . This macro need not do anything if the argument in question was passed on the stack . The compiler knows how to track the amount of stack space used for arguments without any special help .


<s>
void
ARMConstantIslands
::
verify
(
)
{
BBInfoVector
&
BBInfo
=
BBUtils
->
getBBInfo
(
)
;
assert
(
is_sorted
(
*
MF
,
[
&
BBInfo
]
(
const
MachineBasicBlock
&
LHS
,
const
MachineBasicBlock
&
RHS
)
{
return
BBInfo
[
LHS
.
getNumber
(
)
]
.
postOffset
(
)
<
BBInfo
[
RHS
.
getNumber
(
)
]
.
postOffset
(
)
;
}
)
)
;
LLVM_DEBUG
(
dbgs
(
)
<<
"Verifying "
<<
CPUsers
.
size
(
)
<<
" CP users.\n"
)
;
for
(
unsigned
i
=
0
,
e
=
CPUsers
.
size
(
)
;
i
!=
e
;
++
i
)
{
CPUser
&
U
=
CPUsers
[
i
]
;
unsigned
UserOffset
=
getUserOffset
(
U
)
;
if
(
isCPEntryInRange
(
U
.
MI
,
UserOffset
,
U
.
CPEMI
,
U
.
getMaxDisp
(
)
+
2
,
U
.
NegOk
,
true
)
)
{
LLVM_DEBUG
(
dbgs
(
)
<<
"OK\n"
)
;
continue
;
}
LLVM_DEBUG
(
dbgs
(
)
<<
"Out of range.\n"
)
;
dumpBBs
(
)
;
LLVM_DEBUG
(
MF
->
dump
(
)
)
;
llvm_unreachable
(
"Constant pool entry out of range!"
)
;
}
}
</s>

ARM
ARM
"Verifying "
" CP users.\n"
0
2
"OK\n"
"Out of range.\n"
"Constant pool entry out of range!"


<s> void EmitInstruction ( const MachineInstr * MI ) { printInstruction ( MI ) ; O << '\n' ; } </s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s> int fix_bit_operand ( rtx * operands , enum rtx_code code ) { if ( code == AND ? single_zero_operand ( operands [ 2 ] , QImode ) : single_one_operand ( operands [ 2 ] , QImode ) ) { if ( GET_CODE ( operands [ 0 ] ) == MEM && ! satisfies_constraint_U ( operands [ 0 ] ) ) { rtx mem = gen_rtx_MEM ( GET_MODE ( operands [ 0 ] ) , copy_to_mode_reg ( Pmode , XEXP ( operands [ 0 ] , 0 ) ) ) ; MEM_COPY_ATTRIBUTES ( mem , operands [ 0 ] ) ; operands [ 0 ] = mem ; } if ( GET_CODE ( operands [ 1 ] ) == MEM && ! satisfies_constraint_U ( operands [ 1 ] ) ) { rtx mem = gen_rtx_MEM ( GET_MODE ( operands [ 1 ] ) , copy_to_mode_reg ( Pmode , XEXP ( operands [ 1 ] , 0 ) ) ) ; MEM_COPY_ATTRIBUTES ( mem , operands [ 0 ] ) ; operands [ 1 ] = mem ; } return 0 ; } operands [ 1 ] = force_reg ( QImode , operands [ 1 ] ) ; { rtx res = gen_reg_rtx ( QImode ) ; switch ( code ) { case AND : emit_insn ( gen_andqi3_1 ( res , operands [ 1 ] , operands [ 2 ] ) ) ; break ; case IOR : emit_insn ( gen_iorqi3_1 ( res , operands [ 1 ] , operands [ 2 ] ) ) ; break ; case XOR : emit_insn ( gen_xorqi3_1 ( res , operands [ 1 ] , operands [ 2 ] ) ) ; break ; default : gcc_unreachable ( ) ; } emit_insn ( gen_movqi ( operands [ 0 ] , res ) ) ; } return 1 ; } </s>

Fix the operands of a gen_xxx so that it could become a bit operating insn .


<s>
unsigned
getReg
(
)
const
override
{
assert
(
Kind
==
KindTy
::
Register
&&
"Invalid type access!"
)
;
return
Reg
.
RegNum
.
id
(
)
;
}
</s>

Returns the register associated with this edge .


<s> static int mips_memory_move_cost ( machine_mode mode , reg_class_t rclass , bool in ) { return ( mips_cost -> memory_latency + memory_move_secondary_cost ( mode , rclass , in ) ) ; } </s>


<s> static bool s390_hard_regno_call_part_clobbered ( unsigned int , unsigned int regno , machine_mode mode ) { if ( ! TARGET_64BIT && TARGET_ZARCH && GET_MODE_SIZE ( mode ) > 4 && ( ! flag_pic || regno != PIC_OFFSET_TABLE_REGNUM ) && ( ( regno >= 6 && regno <= 15 ) || regno == 32 ) ) return true ; if ( TARGET_VX && GET_MODE_SIZE ( mode ) > 8 && ( ( ( TARGET_64BIT && regno >= 24 && regno <= 31 ) ) || ( ! TARGET_64BIT && ( regno == 18 || regno == 19 ) ) ) ) return true ; return false ; } </s>

Implement TARGET_HARD_REGNO_CALL_PART_CLOBBERED . When generating code that runs in z/Architecture mode , but conforms to the 31-bit ABI , GPRs can hold 8 bytes ; the ABI guarantees only that the lower 4 bytes are saved across calls , however .


<s> static int tilepro_saved_regs_size ( void ) { int reg_save_size = 0 ; int regno ; int offset_to_frame ; int align_mask ; for ( regno = 0 ; regno < FIRST_PSEUDO_REGISTER ; regno ++ ) if ( need_to_save_reg ( regno ) ) reg_save_size += UNITS_PER_WORD ; offset_to_frame = crtl -> args . pretend_args_size + reg_save_size ; align_mask = ( STACK_BOUNDARY / BITS_PER_UNIT ) - 1 ; reg_save_size += ( - offset_to_frame ) & align_mask ; return reg_save_size ; } </s>

Return the size of the register savev area . This function is only correct starting with local register allocation


<s> int X86InstrInfo :: getSPAdjust ( const MachineInstr & MI ) const { const MachineFunction * MF = MI . getParent ( ) -> getParent ( ) ; const TargetFrameLowering * TFI = MF -> getSubtarget ( ) . getFrameLowering ( ) ; if ( MI . getOpcode ( ) == getCallFrameSetupOpcode ( ) || MI . getOpcode ( ) == getCallFrameDestroyOpcode ( ) ) { unsigned StackAlign = TFI -> getStackAlignment ( ) ; int SPAdj = ( MI . getOperand ( 0 ) . getImm ( ) + StackAlign - 1 ) / StackAlign * StackAlign ; SPAdj -= MI . getOperand ( 1 ) . getImm ( ) ; if ( MI . getOpcode ( ) == getCallFrameSetupOpcode ( ) ) return SPAdj ; else return - SPAdj ; } if ( MI . isCall ( ) ) { const MachineBasicBlock * MBB = MI . getParent ( ) ; auto I = ++ MachineBasicBlock :: const_iterator ( MI ) ; for ( auto E = MBB -> end ( ) ; I != E ; ++ I ) { if ( I -> getOpcode ( ) == getCallFrameDestroyOpcode ( ) || I -> isCall ( ) ) break ; } if ( I -> getOpcode ( ) != getCallFrameDestroyOpcode ( ) ) return 0 ; return - ( I -> getOperand ( 1 ) . getImm ( ) ) ; } switch ( MI . getOpcode ( ) ) { default : return 0 ; case X86 :: PUSH32i8 : case X86 :: PUSH32r : case X86 :: PUSH32rmm : case X86 :: PUSH32rmr : case X86 :: PUSHi32 : return 4 ; case X86 :: PUSH64i8 : case X86 :: PUSH64r : case X86 :: PUSH64rmm : case X86 :: PUSH64rmr : case X86 :: PUSH64i32 : return 8 ; } } </s>

getSPAdjust - This returns the stack pointer adjustment made by this instruction .


<s> static bool signed_compare_p ( enum rtx_code code ) { return ( code == EQ || code == NE || code == LT || code == LE || code == GT || code == GE ) ; } </s>

Return whether CODE is a signed comparison .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . addRequired < MachineLoopInfo > ( ) ; AsmPrinter :: getAnalysisUsage ( AU ) ; } </s>


"Unhandled instruction encoding format!"

Targets should implement this to emit instructions .


<s> SDValue AArch64TargetLowering :: getTargetNode ( ExternalSymbolSDNode * N , EVT Ty , SelectionDAG & DAG , unsigned Flag ) const { return DAG . getTargetExternalSymbol ( N -> getSymbol ( ) , Ty , Flag ) ; } </s>

Retrieve the target node this edge connects to .


<s>
unsigned
PPCMIPeephole
::
lookThruCopyLike
(
unsigned
SrcReg
)
{
while
(
true
)
{
MachineInstr
*
MI
=
MRI
->
getVRegDef
(
SrcReg
)
;
if
(
!
MI
->
isCopyLike
(
)
)
return
SrcReg
;
unsigned
CopySrcReg
;
if
(
MI
->
isCopy
(
)
)
CopySrcReg
=
MI
->
getOperand
(
1
)
.
getReg
(
)
;
else
{
assert
(
MI
->
isSubregToReg
(
)
&&
"bad opcode for lookThruCopyLike"
)
;
CopySrcReg
=
MI
->
getOperand
(
2
)
.
getReg
(
)
;
}
if
(
!
TargetRegisterInfo
::
isVirtualRegister
(
CopySrcReg
)
)
return
CopySrcReg
;
SrcReg
=
CopySrcReg
;
}
}
</s>

Returns the original SrcReg unless it is the target of a copy-like operation , in which case we chain backwards through all such operations to the ultimate source register .


<s> void xstormy16_expand_andqi3 ( rtx * operands ) { rtx in , out , outsub , val ; out = operands [ 0 ] ; in = operands [ 1 ] ; val = operands [ 2 ] ; if ( xstormy16_onebit_clr_operand ( val , QImode ) ) { if ( ! xstormy16_below100_or_register ( in , QImode ) ) in = copy_to_mode_reg ( QImode , in ) ; if ( ! xstormy16_below100_or_register ( out , QImode ) ) out = gen_reg_rtx ( QImode ) ; emit_insn ( gen_andqi3_internal ( out , in , val ) ) ; if ( out != operands [ 0 ] ) emit_move_insn ( operands [ 0 ] , out ) ; return ; } if ( GET_CODE ( in ) != REG ) in = copy_to_mode_reg ( QImode , in ) ; if ( GET_CODE ( val ) != REG && GET_CODE ( val ) != CONST_INT ) val = copy_to_mode_reg ( QImode , val ) ; if ( GET_CODE ( out ) != REG ) out = gen_reg_rtx ( QImode ) ; in = simplify_gen_subreg ( HImode , in , QImode , 0 ) ; outsub = simplify_gen_subreg ( HImode , out , QImode , 0 ) ; if ( GET_CODE ( val ) != CONST_INT ) val = simplify_gen_subreg ( HImode , val , QImode , 0 ) ; emit_insn ( gen_andhi3 ( outsub , in , val ) ) ; if ( out != operands [ 0 ] ) emit_move_insn ( operands [ 0 ] , out ) ; } </s>


<s> TargetIRAnalysis X86TargetMachine :: getTargetIRAnalysis ( ) { return TargetIRAnalysis ( [ this ] ( const Function & F ) { return TargetTransformInfo ( X86TTIImpl ( this , F ) ) ; } ) ; } </s>

Get a TargetIRAnalysis appropriate for the target .


<s> rtx s390_expand_merge_perm_const ( machine_mode mode , bool high_p ) { int nelts = GET_MODE_NUNITS ( mode ) ; rtx perm [ 16 ] ; int addend = high_p ? 0 : nelts ; for ( int i = 0 ; i < nelts ; i ++ ) perm [ i ] = GEN_INT ( ( i + addend ) / 2 + ( i % 2 ) * nelts ) ; return gen_rtx_PARALLEL ( VOIDmode , gen_rtvec_v ( nelts , perm ) ) ; } </s>

Return a parallel of constant integers to be used as permutation vector for a vector merge operation in MODE . If HIGH_P is true the left-most elements of the source vectors are merged otherwise the right-most elements .


<s> SDValue AMDGPUTargetLowering :: SplitVectorStore ( SDValue Op , SelectionDAG & DAG ) const { StoreSDNode * Store = cast < StoreSDNode > ( Op ) ; SDValue Val = Store -> getValue ( ) ; EVT VT = Val . getValueType ( ) ; if ( VT . getVectorNumElements ( ) == 2 ) return scalarizeVectorStore ( Store , DAG ) ; EVT MemVT = Store -> getMemoryVT ( ) ; SDValue Chain = Store -> getChain ( ) ; SDValue BasePtr = Store -> getBasePtr ( ) ; SDLoc SL ( Op ) ; EVT LoVT , HiVT ; EVT LoMemVT , HiMemVT ; SDValue Lo , Hi ; std :: tie ( LoVT , HiVT ) = DAG . GetSplitDestVTs ( VT ) ; std :: tie ( LoMemVT , HiMemVT ) = DAG . GetSplitDestVTs ( MemVT ) ; std :: tie ( Lo , Hi ) = DAG . SplitVector ( Val , SL , LoVT , HiVT ) ; SDValue HiPtr = DAG . getObjectPtrOffset ( SL , BasePtr , LoMemVT . getStoreSize ( ) ) ; const MachinePointerInfo & SrcValue = Store -> getMemOperand ( ) -> getPointerInfo ( ) ; unsigned BaseAlign = Store -> getAlignment ( ) ; unsigned Size = LoMemVT . getStoreSize ( ) ; unsigned HiAlign = MinAlign ( BaseAlign , Size ) ; SDValue LoStore = DAG . getTruncStore ( Chain , SL , Lo , BasePtr , SrcValue , LoMemVT , BaseAlign , Store -> getMemOperand ( ) -> getFlags ( ) ) ; SDValue HiStore = DAG . getTruncStore ( Chain , SL , Hi , HiPtr , SrcValue . getWithOffset ( Size ) , HiMemVT , HiAlign , Store -> getMemOperand ( ) -> getFlags ( ) ) ; return DAG . getNode ( ISD :: TokenFactor , SL , MVT :: Other , LoStore , HiStore ) ; } </s>

Split a vector store into 2 stores of half the vector .

AMDGPU AMDGPU 2 ISD::TokenFactor MVT::Other


This adds a condition to the basic_block NEW_BB in function FUNCTION_DECL to return a pointer to VERSION_DECL if we are running on a machine that supports the index CLONE_ISA hardware architecture bits . This function will be called during version dispatch to decide which function version to execute . It returns the basic block at the end , to which more conditions can be added .


<s> MCSection * MipsTargetObjectFile :: getSectionForConstant ( const DataLayout & DL , SectionKind Kind , const Constant * C , unsigned & Align ) const { if ( IsConstantInSmallSection ( DL , C , * TM ) ) return SmallDataSection ; return TargetLoweringObjectFileELF :: getSectionForConstant ( DL , Kind , C , Align ) ; } </s>

Given a constant with the SectionKind , return a section that it should be placed in .


<s> bool SIRegisterInfo :: needsFrameBaseReg ( MachineInstr * MI , int64_t Offset ) const { if ( ! MI -> mayLoadOrStore ( ) ) return false ; int64_t FullOffset = Offset + getScratchInstrOffset ( MI ) ; if ( SIInstrInfo :: isMUBUF ( * MI ) ) return ! SIInstrInfo :: isLegalMUBUFImmOffset ( FullOffset ) ; const SIInstrInfo * TII = ST . getInstrInfo ( ) ; return TII -> isLegalFLATOffset ( FullOffset , AMDGPUAS :: PRIVATE_ADDRESS , true ) ; } </s>

Returns true if the instruction 's frame index reference would be better served by a base register other than FP or SP .


<s> void s390_narrow_logical_operator ( enum rtx_code code , rtx * memop , rtx * immop ) { int def = code == AND ? - 1 : 0 ; HOST_WIDE_INT mask ; int part ; gcc_assert ( GET_CODE ( * memop ) == MEM ) ; gcc_assert ( ! MEM_VOLATILE_P ( * memop ) ) ; mask = s390_extract_part ( * immop , QImode , def ) ; part = s390_single_part ( * immop , GET_MODE ( * memop ) , QImode , def ) ; gcc_assert ( part >= 0 ) ; * memop = adjust_address ( * memop , QImode , part ) ; * immop = gen_int_mode ( mask , QImode ) ; } </s>

Narrow logical operation CODE of memory operand MEMOP with immediate operand IMMOP to switch from SS to SI type instructions .


<s> int m32c_expand_cpymemhi ( rtx * operands ) { rtx desta , srca , count ; rtx desto , srco , counto ; desta = XEXP ( operands [ 0 ] , 0 ) ; srca = XEXP ( operands [ 1 ] , 0 ) ; count = operands [ 2 ] ; desto = gen_reg_rtx ( Pmode ) ; srco = gen_reg_rtx ( Pmode ) ; counto = gen_reg_rtx ( HImode ) ; if ( GET_CODE ( desta ) != REG || REGNO ( desta ) < FIRST_PSEUDO_REGISTER ) desta = copy_to_mode_reg ( Pmode , desta ) ; if ( GET_CODE ( srca ) != REG || REGNO ( srca ) < FIRST_PSEUDO_REGISTER ) srca = copy_to_mode_reg ( Pmode , srca ) ; if ( GET_CODE ( count ) == CONST_INT && ! ( INTVAL ( count ) & 1 ) && ( INTVAL ( count ) > 1 ) ) { count = copy_to_mode_reg ( HImode , GEN_INT ( INTVAL ( count ) / 2 ) ) ; if ( TARGET_A16 ) emit_insn ( gen_cpymemhi_whi_op ( desto , srco , counto , desta , srca , count ) ) ; else emit_insn ( gen_cpymemhi_wpsi_op ( desto , srco , counto , desta , srca , count ) ) ; return 1 ; } if ( GET_CODE ( count ) != REG || REGNO ( count ) < FIRST_PSEUDO_REGISTER ) count = copy_to_mode_reg ( HImode , count ) ; if ( TARGET_A16 ) emit_insn ( gen_cpymemhi_bhi_op ( desto , srco , counto , desta , srca , count ) ) ; else emit_insn ( gen_cpymemhi_bpsi_op ( desto , srco , counto , desta , srca , count ) ) ; return 1 ; } </s>

This is a memcpy ( ) opcode . All operands are implied , so we need to arrange for them to be in the right registers . The opcode wants addresses , not [ mem ] syntax . $ 0 is the destination ( MEM : BLK ) , $ 1 is the source ( MEM : BLK ) , and $ 2 the count ( HI ) .