<s> break ; } case G_FCONSTANT : { unsigned Size = MRI . getType ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) . getSizeInBits ( ) ; assert ( ( Size == <NUM_LIT> || Size == <NUM_LIT> ) && <STR_LIT> ) ; const RegisterBankInfo :: ValueMapping * FPRValueMapping = Size == <NUM_LIT> ? & <STR_LIT> [ <STR_LIT> ] : & <STR_LIT> [ <STR_LIT> ] ; OperandsMapping = getOperandsMapping ( { FPRValueMapping , nullptr } ) ; break ; } case G_FCMP : { unsigned Size = MRI . getType ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) . getSizeInBits ( ) ; assert ( ( Size == <NUM_LIT> || Size == <NUM_LIT> ) && <STR_LIT> ) ; const RegisterBankInfo :: ValueMapping * FPRValueMapping = Size == <NUM_LIT> ? & <STR_LIT> [ <STR_LIT> ] : & <STR_LIT> [ <STR_LIT> ] ; OperandsMapping = getOperandsMapping ( { & <STR_LIT> [ <STR_LIT> ] , nullptr , FPRValueMapping , FPRValueMapping } ) ; break ; } case G_FPEXT : OperandsMapping = getOperandsMapping ( { & <STR_LIT> [ <STR_LIT> ] , & <STR_LIT> [ <STR_LIT> ] } ) ; break ; case G_FPTRUNC : OperandsMapping = getOperandsMapping ( { & <STR_LIT> [ <STR_LIT> ] , & <STR_LIT> [ <STR_LIT> ] } ) ; break ; case G_CONSTANT : case G_FRAME_INDEX : case G_GLOBAL_VALUE : case G_BRCOND : OperandsMapping = getOperandsMapping ( { & <STR_LIT> [ <STR_LIT> ] , nullptr } ) ; break ; case G_ICMP : OperandsMapping = getOperandsMapping ( { & <STR_LIT> [ <STR_LIT> ] , nullptr , &


<s> int i , c_mask ; if ( cfun && cfun -> machine -> no_caller_saved_registers ) for ( i = <NUM_LIT> ; i < FIRST_PSEUDO_REGISTER ; i ++ ) if ( ! fixed_regs [ i ] && ! ix86_function_value_regno_p ( i ) ) call_used_regs [ i ] = <NUM_LIT> ; if ( ! TARGET_64BIT ) { for ( i = FIRST_REX_INT_REG ; i <= LAST_REX_INT_REG ; i ++ ) CLEAR_HARD_REG_BIT ( accessible_reg_set , i ) ; for ( i = FIRST_REX_SSE_REG ; i <= LAST_REX_SSE_REG ; i ++ ) CLEAR_HARD_REG_BIT ( accessible_reg_set , i ) ; for ( i = FIRST_EXT_REX_SSE_REG ; i <= LAST_EXT_REX_SSE_REG ; i ++ ) CLEAR_HARD_REG_BIT ( accessible_reg_set , i ) ; } c_mask = CALL_USED_REGISTERS_MASK ( TARGET_64BIT_MS_ABI ) ; CLEAR_HARD_REG_SET ( reg_class_contents [ ( int ) CLOBBERED_REGS ] ) ; for ( i = <NUM_LIT> ; i


<s> std :: string FuncName = Mang -> getValueName ( F ) ; const TargetData * TD = TM . getTargetData ( ) ; O << <STR_LIT> ; const char * SectionName = PAN :: getFrameSectionName ( CurrentFnName ) . c_str ( ) ; const Section * fPDataSection = TAI -> getNamedSection ( SectionName , SectionFlags :: Writeable ) ; SwitchToSection ( fPDataSection ) ; O << PAN :: getFrameLabel ( CurrentFnName ) << <STR_LIT> ; const Type * RetType = F -> getReturnType ( ) ; unsigned RetSize = <NUM_LIT> ; if ( RetType -> getTypeID ( ) != Type :: VoidTyID ) RetSize =


<s> for ( unsigned i = <NUM_LIT> , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) { const MachineOperand & MO = MI -> getOperand ( i ) ; MCOperand MCOp = LowerOperand ( MO ) ; if ( MCOp . isValid ( ) ) { OutMI . addOperand ( MCOp )


<s> static SDValue lowerVectorShuffleAsBitBlend ( const SDLoc & DL , MVT VT , SDValue V1 , SDValue V2 , ArrayRef < int > Mask , SelectionDAG & DAG ) { assert ( VT . isInteger ( ) && <STR_LIT> ) ; MVT EltVT = VT . getVectorElementType ( ) ; int NumEltBits = EltVT . getSizeInBits ( ) ; SDValue Zero = DAG . getConstant ( <NUM_LIT> , DL , EltVT ) ; SDValue AllOnes = DAG . getConstant ( APInt :: getAllOnesValue ( NumEltBits ) , DL , EltVT ) ; SmallVector < SDValue , <NUM_LIT> > MaskOps ; for ( int i = <NUM_LIT> , Size = Mask . size ( ) ; i < Size ; ++ i ) { if ( Mask [ i ] >= <NUM_LIT> && Mask [ i ] != i && Mask [ i ] != i + Size )


<s> if ( Subtarget . isABI_N64 ( ) ) return MachineJumpTableInfo :: EK_GPRel64BlockAddress ; return TargetLowering :: getJumpTableEncoding


<s> rtx store = gen_rtx_SET ( VOIDmode , op0 , tmp ) ; rtx stvx = gen_rtx_UNSPEC ( mode , gen_rtvec ( <NUM_LIT> , const0_rtx ) , unspec ) ; rtx par = gen_rtx_PARALLEL ( mode , gen_rtvec ( <NUM_LIT> , store , stvx ) ) ; rtx sel = swap_selector_for_mode ( mode ) ; rtx vperm ; gcc_assert ( REG_P ( op1 ) ) ; vperm = gen_rtx_UNSPEC ( mode , gen_rtvec ( <NUM_LIT> , op1 , op1 , sel ) , UNSPEC_VPERM ) ; emit_insn ( gen_rtx_SET ( VOIDmode , tmp , vperm ) ) ; emit_insn ( par )


<s> Value * <ISA_LIT>DCInstruction :: translateScaledImmediate ( unsigned MIOperandNo , unsigned Scale , unsigned Bits ) { APInt Val = APInt ( Bits ,


<s> MachineFunctionPass :: getAnalysisUsage ( AU )


<s> state_reset ( curr_state ) ; targetm . sched . init ( <NUM_LIT> , false , <NUM_LIT> ) ; advance_state ( curr_state


<s> extern __inline void __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) __TM_resume ( void ) { __builtin_tresume (


<s> assert ( ! I -> getOperand ( <NUM_LIT> ) . getImm ( ) && hasFP ( MF ) && <STR_LIT> ) ; const auto * TII = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getInstrInfo ( ) ; if ( I -> getOpcode ( ) == TII -> getCallFrameDestroyOpcode ( ) && needsSPWriteback ( MF , * MF . getFrameInfo ( ) ) ) { DebugLoc DL = I -> getDebugLoc


<s> if ( PredB != Latch ) { PN -> RemoveOperand ( i + <NUM_LIT> ) ; PN -> RemoveOperand ( i ) ; } } PN -> addOperand ( MachineOperand :: CreateReg ( NewPR , false ) ) ; PN -> addOperand ( MachineOperand :: CreateMBB ( NewPH ) ) ; } } else { assert ( Header -> pred_size ( ) == <NUM_LIT> ) ; for ( instr_iterator I = Header -> instr_begin ( ) , E = Header -> instr_end ( ) ; I != E && I -> isPHI ( ) ; ++ I ) { MachineInstr * PN = & * I ; for ( unsigned i = <NUM_LIT> , n = PN -> getNumOperands ( ) ; i < n ; i += <NUM_LIT> ) { MachineOperand & MO = PN -> getOperand ( i + <NUM_LIT> ) ; if ( MO . getMBB ( ) != Latch ) MO . setMBB ( NewPH ) ; } } } SmallVector < MachineOperand , <NUM_LIT> > Tmp2 ; SmallVector < MachineOperand , <NUM_LIT> > EmptyCond ; TB = FB = <NUM_LIT> ; for ( MBBVector :: iterator I = Preds . begin ( ) , E = Preds . end ( ) ; I != E ; ++ I ) { MachineBasicBlock * PB = * I ; if ( PB != Latch ) { Tmp2 . clear ( ) ; bool NotAnalyzed = TII -> AnalyzeBranch ( * PB , TB , FB , Tmp2 , false ) ; ( void ) NotAnalyzed ; assert ( ! NotAnalyzed && <STR_LIT> ) ; if ( TB != Header && ( Tmp2 . empty ( ) || FB != Header ) ) TII -> InsertBranch ( * PB , NewPH , <NUM_LIT> , EmptyCond , DL ) ; PB -> ReplaceUsesOfBlockWith ( Header , NewPH ) ; } } TB = FB = <NUM_LIT> ; bool LatchNotAnalyzed = TII -> AnalyzeBranch ( * Latch , TB , FB , Tmp2 , false ) ; ( void ) LatchNotAnalyzed ; assert ( ! LatchNotAnalyzed && <STR_LIT> ) ; if ( ! TB && ! FB ) TII -> InsertBranch ( * Latch , Header , <NUM_LIT> , EmptyCond , DL ) ; TII -> InsertBranch ( * NewPH , Header , <NUM_LIT> , EmptyCond , DL ) ; NewPH -> addSuccessor ( Header ) ; return NewPH


<s> for ( unsigned i = <NUM_LIT> , e = FnStoreVarArgs . size ( ) ; i != e ; ++ i ) MFI -> setObjectOffset ( FnStoreVarArgs [

i ] . FI , FnStoreVarArgs [ i ] . SPOffset ) ;


<s> long __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) __tzmsk_u64 ( unsigned long long __X ) { return ~ __X & ( __X


<s> MVT EVT = VT . getVectorElementType ( ) ; SDValue Addr = Load -> getOperand ( <NUM_LIT> ) ; SDValue NewAddr = DAG . getNode ( <STR_LIT> , dl , Addr . getSimpleValueType ( ) , Addr , DAG . getConstant ( Index * EVT . getStoreSize ( ) , Addr


<s> int Src1ModIdx = <STR_LIT> ( Opc , <STR_LIT> :: src1_modifiers ) ; int Src0ModIdx = <STR_LIT> ( Opc , <STR_LIT> :: src0_modifiers ) ; if ( Src1 -> isIdenticalTo ( * Src0 ) && ( Src1ModIdx == - <NUM_LIT> || ! MI -> getOperand ( Src1ModIdx ) . getImm ( ) ) && ( Src0ModIdx == - <NUM_LIT> || ! MI -> getOperand ( Src0ModIdx ) . getImm ( ) ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * MI << <STR_LIT> ) ; auto & NewDesc = TII -> get ( Src0 -> isReg ( ) ? ( unsigned ) <STR_LIT> : getMovOpc ( false ) ) ; int Src2Idx = <STR_LIT> ( Opc , <STR_LIT> :: src2 ) ; if ( Src2Idx != - <NUM_LIT> ) MI -> RemoveOperand ( Src2Idx ) ; MI -> RemoveOperand ( <STR_LIT> ( Opc ,


<s> TargetRegistry :: RegisterMCInstrInfo ( * T , create<ISA_LIT>MCInstrInfo ) ; TargetRegistry :: RegisterMCRegInfo ( * T , create<ISA_LIT>MCRegisterInfo ) ; TargetRegistry :: RegisterMCSubtargetInfo ( * T , create<ISA_LIT>MCSubtargetInfo ) ; TargetRegistry :: RegisterMCInstPrinter ( * T , create<ISA_LIT>MCInstPrinter ) ; TargetRegistry :: RegisterMCAsmBackend ( * T


<s> return DecodeMem ( Inst , insn , Address

, Decoder , true , DecodeIntPairRegisterClass ) ;


<s> const TargetFrameLowering * TFI = MF . getTarget ( ) . getFrameLowering ( ) ; return TFI -> hasFP ( MF ) ? <STR_LIT>


<s> machine_mode memory_vector_mode ( const function_instance & ) const override { return m_mode


<s> return new <ISA_LIT>MCCodeEmitter ( MCII , STI ,


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return


<s> unsigned Sube = ( size == <NUM_LIT> ) ? <STR_LIT> : <STR_LIT> ; unsigned Subo = ( size == <NUM_LIT> ) ? <STR_LIT> : <STR_LIT> ; unsigned Even = MRI . getSubReg


<s> const Thumb1InstrInfo & TII = * static_cast < const Thumb1InstrInfo * > ( STI . getInstrInfo ( ) ) ; const ThumbRegisterInfo * RegInfo = static_cast < const ThumbRegisterInfo * > ( STI . getRegisterInfo ( ) ) ; if ( ! hasReservedCallFrame ( MF ) ) { MachineInstr & Old = * I ; DebugLoc dl = Old . getDebugLoc ( ) ; unsigned Amount = TII . getFrameSize ( Old ) ; if ( Amount != <NUM_LIT>


<s> LLT Ty = MRI . getType ( DstReg ) ; Register LiveIn = getLiveInRegister ( MRI , Arg -> getRegister ( ) , Ty ) ; if ( Arg -> isMasked ( ) ) { const LLT S32 = LLT :: scalar ( <NUM_LIT> ) ; const unsigned Mask = Arg -> getMask ( ) ; const unsigned Shift = countTrailingZeros < unsigned > ( Mask ) ; auto ShiftAmt = B . buildConstant ( S32 , Shift ) ; auto LShr = B . buildLShr ( S32 , LiveIn , ShiftAmt ) ; B . buildAnd ( DstReg , LShr , B . buildConstant ( S32 , Mask >> Shift ) ) ; } else B . buildCopy ( DstReg , LiveIn ) ; if ( ! MRI . getVRegDef ( LiveIn ) ) { MachineBasicBlock & OrigInsBB = B . getMBB ( ) ; auto OrigInsPt = B . getInsertPt (


<s> if ( MO . getTargetFlags ( ) == <STR_LIT> || MO . getTargetFlags ( ) == <STR_LIT> ) GVStubs [ Name ] = Mang -> getMangledName ( GV ) ; else if ( MO . getTargetFlags ( ) == <STR_LIT> || MO . getTargetFlags ( ) == <STR_LIT> ) HiddenGVStubs [ Name ] = Mang -> getMangledName ( GV ) ; else if ( MO . getTargetFlags ( ) == <STR_LIT> ) FnStubs [ Name ] = Mang -> getMangledName ( GV ) ; if ( Name [ <NUM_LIT> ] == '$' ) O << '(' << Name << ')' ; else O << Name ; printOffset ( MO . getOffset ( ) ) ; break ; } case MachineOperand :: MO_ExternalSymbol : { std :: string Name = Mang -> makeNameProper ( MO . getSymbolName ( ) ) ; if ( MO . getTargetFlags ( ) == <STR_LIT> ) { FnStubs [ Name + <STR_LIT> ] = Name ; Name += <STR_LIT> ; } if ( Name [ <NUM_LIT> ] == '$' ) O << '(' << Name << ')' ; else O << Name ; break ; } } switch ( MO . getTargetFlags ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : break ; case <STR_LIT> : O << <STR_LIT> ; PrintPICBaseSymbol ( ) ; O << ']' ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : O << '-' ; PrintPICBaseSymbol ( ) ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O


<s> bool <ISA_LIT>CallLowering :: lowerReturn ( MachineIRBuilder & MIRBuilder , const Value * Val , ArrayRef < Register > VRegs , FunctionLoweringInfo & FLI , Register SwiftErrorVReg ) const { MachineFunction & MF = MIRBuilder . getMF ( ) ; const Function & F = MF . getFunction ( ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; const <ISA_LIT>Subtarget & STI = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; const <ISA_LIT>InstrInfo & TII = * STI . getInstrInfo ( ) ; auto & DL = F . getParent ( ) -> getDataLayout ( ) ; Register ReturnAddrVReg = getFunctionLiveInPhysReg ( MF , TII , <STR_LIT> , <STR_LIT> , MIRBuilder . getDebugLoc ( ) ) ; MRI . setType ( ReturnAddrVReg , LLT :: pointer ( <NUM_LIT> , <NUM_LIT> ) ) ; auto MIB = MIRBuilder . buildInstrNoInsert ( <STR_LIT> ) ; bool Success = true ; if ( ! VRegs . empty ( ) ) { SmallVector < ArgInfo , <NUM_LIT> > SplitArgs ; ArgInfo OrigArg { VRegs , Val -> getType ( ) , <NUM_LIT> } ; setArgFlags ( OrigArg , AttributeList :: ReturnIndex , DL , F ) ; splitToValueTypes ( OrigArg , SplitArgs , DL , F . getCallingConv ( ) ) ; OutgoingValueAssigner ArgAssigner ( RetCC_<ISA_LIT> ) ; OutgoingArgHandler ArgHandler ( MIRBuilder , MRI , MIB ) ; Success = determineAndHandleAssignments ( ArgHandler , ArgAssigner , SplitArgs , MIRBuilder , F . getCallingConv ( ) , F . isVarArg ( ) ) ; } MIRBuilder . buildCopy (


<s> bool <ISA_LIT>AsmParser :: ErrorMissingFeature ( SMLoc IDLoc , uint64_t ErrorInfo , bool MatchingInlineAsm ) { assert ( ErrorInfo && <STR_LIT> ) ; ArrayRef < SMRange > EmptyRanges = None ; SmallString < <NUM_LIT> > Msg ; raw_svector_ostream OS ( Msg ) ; OS <<


<s> auto CheckCopy = [ & ] ( ) { assert ( ( I . isCopy ( ) || ( ! TargetRegisterInfo :: isPhysicalRegister ( I . getOperand ( <NUM_LIT> ) . getReg ( ) ) && ! TargetRegisterInfo :: isPhysicalRegister ( I . getOperand ( <NUM_LIT> ) . getReg ( ) ) ) ) && <STR_LIT> ) ; assert ( KnownValid || isValidCopy ( I , DstRegBank , MRI , TRI , RBI ) ) ; return true ; } ; if ( I . isCopy ( ) ) { const TargetRegisterClass * SrcRC = getMinClassForRegBank ( SrcRegBank , RBI . getSizeInBits ( SrcReg , MRI , TRI ) , true ) ; if ( ! SrcRC ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } if ( DstRegBank . getID ( ) != SrcRegBank . getID ( ) ) { unsigned SrcSize = TRI . getRegSizeInBits ( * SrcRC ) ; unsigned DstSize = TRI . getRegSizeInBits ( * DstRC ) ; if ( SrcSize > DstSize ) { const TargetRegisterClass * SubregRC = getMinClassForRegBank ( DstRegBank , SrcSize , true ) ; assert ( SubregRC && <STR_LIT> ) ; unsigned SubReg = <NUM_LIT> ; if ( ! getSubRegForClass ( DstRC , TRI , SubReg ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false


<s> bool <ISA_LIT>DAGToDAGISel :: SelectAddrMode2OffsetReg ( SDNode * Op , SDValue N , SDValue & Offset , SDValue & Opc ) { unsigned Opcode = Op -> getOpcode ( ) ; <STR_LIT> AM = ( Opcode == <STR_LIT> ) ? cast < LoadSDNode > ( Op ) -> getAddressingMode ( ) : cast < StoreSDNode > ( Op ) -> getAddressingMode ( ) ; <STR_LIT> AddSub = ( AM == <STR_LIT> || AM == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; int Val ; if ( isScaledConstantInRange ( N , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , Val ) ) return false ; Offset = N ; <STR_LIT> ShOpcVal = <STR_LIT> ( N


<s> void <ISA_LIT>AsmParser :: printWarningWithFixIt ( const Twine & Msg , const Twine & FixMsg , SMRange Range , bool ShowColors ) { getSourceManager ( ) . PrintMessage ( Range . Start , SourceMgr :: DK_Warning , Msg , Range , SMFixIt ( Range , FixMsg )


<s> void <ISA_LIT>16InstrInfo :: adjustStackPtrBigUnrestricted ( unsigned SP , int64_t Amount ,

MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const {


<s> for ( const std :: pair < Register , <STR_LIT> > & LiveIn : LiveInAttrs ) if ( LiveIn . first == VReg ) return LiveIn . second . isSExt ( ) ; return false


<s> if ( ! isImm ( ) ) return false ; bool IsConstantImm = evaluateConstantImm ( getImm ( ) , Imm , VK ) ; if ( ! IsConstantImm ) IsValid = <ISA_LIT>AsmParser :: classifySymbolRef ( getImm (


<s> inline bool CC_<ISA_LIT>_32_VectorCallIndirect ( unsigned & ValNo , MVT & ValVT , MVT & LocVT , CCValAssign :: LocInfo & LocInfo , <STR_LIT> & ArgFlags , CCState & State ) { LocVT = <STR_LIT> ; LocInfo = CCValAssign :: Indirect ; ArgFlags . setInReg ( )


<s> if ( VTy -> getElementType ( ) == Type :: getInt64Ty ( VTy -> getContext ( ) ) ) return ScalableVectorType :: get ( VTy -> getElementType ( ) , <NUM_LIT> ) ; if ( VTy -> getElementType ( ) == Type :: getInt32Ty ( VTy -> getContext ( ) ) ) return ScalableVectorType :: get ( VTy -> getElementType ( ) , <NUM_LIT> ) ; if ( VTy -> getElementType ( ) == Type :: getInt16Ty ( VTy -> getContext ( ) ) ) return ScalableVectorType :: get ( VTy


<s> ret . val [ <NUM_LIT> ] = __builtin_aarch64_get_qregciv8hf ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = __builtin_aarch64_get_qregciv8hf ( __o


<s> unsigned MOHiFlag , MOLoFlag ; bool isPIC = GetLabelAccessInfo ( DAG . getTarget ( ) , MOHiFlag , MOLoFlag ) ; SDValue CPIHi = DAG . getTargetConstantPool ( C , PtrVT , CP -> getAlignment ( ) , <NUM_LIT> , MOHiFlag ) ; SDValue CPILo = DAG . getTargetConstantPool ( C , PtrVT , CP -> getAlignment ( ) , <NUM_LIT> , MOLoFlag ) ; return LowerLabelRef ( CPIHi , CPILo ,


<s> BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) ) . addReg ( EhHandlerReg ) ; MBB . erase ( MBBI ) ; return ; } bool restoreLR = XFI -> hasLRSpillSlot ( ) ; bool UseRETSP = restoreLR && RemainingAdj && ( MFI -> getObjectOffset ( XFI -> getLRSpillSlot ( ) ) == <NUM_LIT> ) ; if ( UseRETSP ) restoreLR = false ; bool FP = hasFP ( MF ) ; if ( FP ) BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) ) . addReg ( FramePtr ) ; SmallVector < StackSlotInfo , <NUM_LIT> > SpillList ; GetSpillList ( SpillList , MFI , XFI , restoreLR , FP ) ; RestoreSpillList ( MBB , MBBI , dl , TII , RemainingAdj , SpillList ) ; if ( RemainingAdj ) { IfNeededLDAWSP ( MBB , MBBI , dl , TII , <NUM_LIT> , RemainingAdj ) ; if ( UseRETSP


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( Op . getResNo ( ) == <NUM_LIT> ) break ; case <STR_LIT> : KnownZero |= APInt :: getHighBitsSet ( BitWidth , BitWidth - <NUM_LIT> ) ; break ; case <STR_LIT> : { unsigned IntId = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; unsigned NumLoBits = <NUM_LIT> ; switch ( IntId ) { default : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { switch ( IntId ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : NumLoBits = <NUM_LIT> ; break ; case <STR_LIT> : NumLoBits = <NUM_LIT> ; break ; case <STR_LIT> : NumLoBits = <NUM_LIT> ; break ; case <STR_LIT> : NumLoBits = <NUM_LIT> ; break ; case <STR_LIT> : NumLoBits = <NUM_LIT> ; break ; case <STR_LIT> : NumLoBits = <NUM_LIT>


<s> ArrayRef < std :: pair < int , const char * >> <ISA_LIT>InstrInfo :: getSerializableTargetIndices ( ) const { static const std :: pair < int , const char * > TargetIndices [ ] = { { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } } ; return makeArrayRef ( TargetIndices


<s> static bool xtensa_function_value_regno_p ( const unsigned int regno ) { return IN_RANGE ( regno , GP_RETURN_FIRST


<s> unsigned MLxExpansion :: getDefReg ( MachineInstr * MI ) const { Register Reg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( Register :: isPhysicalRegister ( Reg ) || ! MRI -> hasOneNonDBGUse ( Reg ) ) return Reg ; MachineBasicBlock * MBB = MI -> getParent ( ) ; MachineInstr * UseMI = & * MRI -> use_instr_nodbg_begin ( Reg ) ; if ( UseMI -> getParent ( ) != MBB )


<s> bool Lo = Mask . equals ( <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> ) ; unsigned Shuffle = Lo ? <STR_LIT> : <STR_LIT> ; MVT ShuffleVT = <STR_LIT> ; if ( Depth == <NUM_LIT> && Root -> getOpcode ( ) == Shuffle ) return false ; Op = DAG . getNode ( <STR_LIT> , DL , ShuffleVT , Input ) ; DCI . AddToWorklist ( Op . getNode ( ) ) ; Op = DAG . getNode ( Shuffle , DL , ShuffleVT , Op , Op ) ; DCI . AddToWorklist ( Op . getNode ( ) ) ; DCI . CombineTo ( Root . getNode ( ) , DAG . getNode ( <STR_LIT> , DL , RootVT , Op ) , true ) ; return true ; } } if ( ! FloatDomain && ( Mask . equals ( <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> ) || Mask . equals ( <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> ) || Mask . equals ( <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> ) || Mask . equals ( <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> ) ) ) { bool Lo = Mask [ <NUM_LIT> ] == <NUM_LIT> ; unsigned Shuffle = Lo ? <STR_LIT> : <STR_LIT> ; if ( Depth == <NUM_LIT> && Root -> getOpcode ( ) == Shuffle ) return false ; MVT ShuffleVT ; switch ( Mask . size ( ) ) { case <NUM_LIT> : ShuffleVT = <STR_LIT> ; break ; case <NUM_LIT> : ShuffleVT = <STR_LIT> ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } ; Op = DAG . getNode ( <STR_LIT> , DL , ShuffleVT , Input ) ; DCI . AddToWorklist ( Op . getNode ( ) ) ; Op = DAG . getNode ( Shuffle , DL , ShuffleVT , Op , Op ) ; DCI . AddToWorklist ( Op . getNode ( ) ) ; DCI . CombineTo ( Root . getNode ( ) , DAG . getNode ( <STR_LIT> , DL , RootVT , Op ) , true ) ; return true ; } if ( Depth < <NUM_LIT> ) return false ; if ( ( Depth >= <NUM_LIT> || HasPSHUFB )


<s> return & InstrInfo . getRegisterInfo (


<s> static __inline qword si_il ( signed short imm ) { return ( ( qword ) ( vec_splat ( ( vec_int4 ) ( si_from_int ( ( signed int ) (


<s> auto f = BBNumToRegMap . find ( MBB . getNumber ( ) ) ; if ( f != BBNumToRegMap . end ( ) ) return f -> second ; Register NewReg = Register :: index2VirtReg ( getNextID ( ) ) ; BBNumToRegMap [ MBB . getNumber ( ) ] = NewReg ; return NewReg


<s> if ( I . getFlag ( MachineInstr :: MIFlag :: FmArcp ) ) flags |= FPFastMathMode :: AllowRecip ; if ( I . getFlag ( MachineInstr :: MIFlag :: FmReassoc ) ) flags |= FPFastMathMode :: Fast ; return flags


<s> assert ( ( ! produceCompactUnwindFrame ( MF ) || CC == CallingConv :: PreserveMost || ( Count & <NUM_LIT> ) == <NUM_LIT> ) && <STR_LIT> ) ; int Offset = AFI -> getCalleeSavedStackSize ( ) ; unsigned GPRSaveSize = AFI -> getVarArgsGPRSize ( ) ; const <ISA_LIT>Subtarget & Subtarget = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( Subtarget . isTargetWindows ( ) ) Offset -= alignTo ( GPRSaveSize , <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i < Count ; ++ i ) { RegPairInfo RPI ; RPI . Reg1 = CSI [ i ] . getReg ( ) ; assert ( <STR_LIT> . contains ( RPI . Reg1 ) || <STR_LIT> . contains ( RPI . Reg1 ) ) ; RPI . IsGPR = <STR_LIT> . contains ( RPI . Reg1 ) ; if ( i + <NUM_LIT> < Count ) { unsigned NextReg = CSI [ i + <NUM_LIT> ] . getReg (


<s> default : return AMDGPUTargetLowering :: LowerOperation ( Op , DAG ) ; case <STR_LIT> : return LowerBRCOND ( Op , DAG ) ; case <STR_LIT> : return LowerLOAD ( Op , DAG ) ; case <STR_LIT> : return LowerSELECT_CC ( Op , DAG ) ; case <STR_LIT> : { unsigned IntrinsicID = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; EVT VT = Op . getValueType ( ) ; switch ( IntrinsicID ) { case <STR_LIT> : return CreateLiveInRegister ( DAG , & AMDGPU :: VReg_32RegClass , AMDGPU


<s> BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , DestReg ) . addReg ( DestReg ) . addImm ( NumBytes >> <NUM_LIT> ) . addImm ( ( unsigned ) Pred ) . addReg ( PredReg ) . setMIFlags ( MIFlags ) ; Fits = true ; } if ( Fits ) { if ( isSub ) { BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , DestReg ) . addReg ( BaseReg , RegState :: Kill ) . addReg ( DestReg , RegState :: Kill ) . addImm ( ( unsigned ) Pred ) . addReg ( PredReg ) . addReg ( <NUM_LIT> ) . setMIFlags ( MIFlags ) ; } else { BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , DestReg ) . addReg ( DestReg , RegState :: Kill ) . addReg ( BaseReg , RegState :: Kill ) . addImm ( ( unsigned ) Pred ) . addReg ( PredReg ) . addReg ( <NUM_LIT> ) . setMIFlags ( MIFlags ) ; } return ; } } while ( NumBytes ) { unsigned ThisVal = NumBytes ; unsigned Opc = <NUM_LIT> ; if ( DestReg == <STR_LIT> && BaseReg != <STR_LIT> ) { AddDefaultPred ( BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , DestReg ) . addReg ( BaseReg ) . setMIFlags ( MIFlags ) ) ; BaseReg = <STR_LIT> ; continue ; } bool HasCCOut = true ; if ( BaseReg == <STR_LIT> ) { if ( DestReg == <STR_LIT> && ( ThisVal < ( ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) * <NUM_LIT> ) ) { assert ( ( ThisVal & <NUM_LIT> ) == <NUM_LIT> && <STR_LIT> ) ; Opc = isSub ? <STR_LIT> : <STR_LIT> ; AddDefaultPred ( BuildMI ( MBB , MBBI , dl , TII . get ( Opc ) , DestReg ) . addReg ( BaseReg ) . addImm ( ThisVal / <NUM_LIT> ) . setMIFlags ( MIFlags ) ) ; NumBytes = <NUM_LIT> ; continue ; } Opc = isSub ? <STR_LIT> : <STR_LIT> ; if ( <STR_LIT> ( NumBytes ) != -


<s> virtual const <ISA_LIT>Z80SelectionDAGInfo * getSelectionDAGInfo ( ) const { return & TSInfo


<s> const <ISA_LIT>FrameLowering * getFrameLowering ( ) const override { return & FrameLowering


<s> ModulePass * create<ISA_LIT>OverlayPass


<s> const RegClassWeight & R600RegisterInfo :: getRegClassWeight ( const TargetRegisterClass * RC


<s> bool isLegalMaskedGather ( Type * DataType


<s> if ( Fast ) { * Fast = ! Subtarget -> isCyclone ( ) || VT . getStoreSize ( ) != <NUM_LIT> || Align


<s> return SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , Ops ) , <NUM_LIT> ) ; } if ( InstMaskEnd == <NUM_LIT> - RLAmt ) { SDValue Ops [ ] = { ExtendToInt64 ( Base , dl ) , ExtendToInt64 ( V , dl ) , getI32Imm ( RLAmt , dl ) , getI32Imm ( InstMaskStart , dl ) } ; return SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , Ops ) , <NUM_LIT> ) ; } if ( InstCnt ) * InstCnt += <NUM_LIT> ; unsigned RLAmt2 =


<s> else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opc = <STR_LIT> , BeginIdx = <STR_LIT> , SubRegs = <NUM_LIT> ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opc = <STR_LIT> , BeginIdx = <STR_LIT> , SubRegs = <NUM_LIT> ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opc = <STR_LIT> , BeginIdx = <STR_LIT> , SubRegs = <NUM_LIT> ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opc = <STR_LIT> , BeginIdx = <STR_LIT> , SubRegs = <NUM_LIT> ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opc = <STR_LIT> , BeginIdx = <STR_LIT> , SubRegs = <NUM_LIT> , Spacing = <NUM_LIT> ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opc = <STR_LIT> , BeginIdx = <STR_LIT> , SubRegs = <NUM_LIT> , Spacing = <NUM_LIT> ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opc = <STR_LIT> , BeginIdx = <STR_LIT> , SubRegs = <NUM_LIT> , Spacing = <NUM_LIT> ; if ( Opc ) { const TargetRegisterInfo * TRI = & getRegisterInfo ( ) ; MachineInstrBuilder Mov ; for ( unsigned i = <NUM_LIT> ;


<s> op [ arity ] = expand_expr ( arg , NULL_RTX , insn_op -> mode , EXPAND_NORMAL ) ; if ( CONST_INT_P ( op [ arity ] ) && SCALAR_INT_MODE_P ( insn_op -> mode ) && GET_MODE ( op [ arity ] ) != insn_op -> mode ) op [ arity ] = GEN_INT ( trunc_int_for_mode ( INTVAL ( op [ arity ] ) , insn_op -> mode ) ) ; if ( POINTER_TYPE_P ( TREE_TYPE ( arg ) ) && insn_op -> predicate != address_operand ) op [ arity ] = gen_rtx_MEM ( insn_op -> mode , op [ arity ] ) ; if ( op_flags == O_ELEM ) { gcc_assert ( last_vec_mode != VOIDmode ) ; op [ arity ] = simplify_expand_binop ( SImode , code_to_optab ( AND ) , op [ arity ] , GEN_INT ( GET_MODE_NUNITS ( last_vec_mode ) - <NUM_LIT> ) , NULL_RTX , <NUM_LIT> , OPTAB_DIRECT ) ; } if ( VECTOR_MODE_P ( insn_op -> mode ) ) last_vec_mode = insn_op -> mode ; if ( insn_op -> predicate ( op [ arity ] , insn_op -> mode ) ) { arity ++


<s> virtual const TargetData * getTargetData ( ) const { return & DataLayout


, ( __mmask8 ) __U , _MM_FROUND_CUR_DIRECTION ) ;


<s> CCValAssign & VA = ArgLocs [ i ] ; MVT RegVT = VA . getLocVT ( ) ; const TargetRegisterClass * RC = getRegClassFor ( RegVT ) ; unsigned Reg = MF . addLiveIn ( VA . getLocReg ( ) , RC ) ; SDValue ArgValue = DAG . getCopyFromReg ( Chain , DL , Reg , RegVT ) ; InVals . push_back ( ArgValue ) ; } return


<s> if ( Options . getABIName ( ) . startswith ( <STR_LIT> ) ) return <ISA_LIT>ABIInfo :: O32 ( ) ; if ( Options . getABIName ( ) . startswith ( <STR_LIT> ) ) return <ISA_LIT>ABIInfo :: N32 ( ) ; if ( Options . getABIName ( ) . startswith ( <STR_LIT> ) ) return <ISA_LIT>ABIInfo :: N64 ( ) ; if ( TT . getEnvironment ( ) == llvm :: Triple :: GNUABIN32 ) return <ISA_LIT>ABIInfo :: N32 ( ) ; assert ( Options . getABIName ( ) . empty ( ) && <STR_LIT> ) ; if ( TT . isMIPS64 ( ) ) return <ISA_LIT>ABIInfo :: N64 ( ) ; return <ISA_LIT>ABIInfo :: O32 (


<s> if ( FP . SplitB -> succ_size ( ) != <NUM_LIT> ) return ; MachineBasicBlock * SB = * FP . SplitB -> succ_begin ( ) ; if ( SB -> pred_size ( ) != <NUM_LIT> ) return ; if ( ! hasEHLabel ( SB ) || hasUncondBranch ( SB ) ) mergeBlocks ( FP . SplitB


<s> return ( ( qword ) ( vec_or ( ( vec_uchar16 ) ( a ) , vec_splat ( ( vec_uchar16 )

( si_from_uchar ( b ) ) , <NUM_LIT> ) ) ) ) ;


<s> I8Ptr = Builder . CreateBitCast ( AllocaAddr , Builder . getInt8PtrTy ( ) ) ; Stride = Builder . getInt64 ( <NUM_LIT> ) ; } ; if ( Bitcast -> getType ( ) -> is<ISA_LIT>_AMXTy ( ) ) { Use & U = * ( Bitcast -> use_begin ( ) ) ; unsigned OpNo = U . getOperandNo ( ) ; auto * II = dyn_cast < IntrinsicInst > ( U . getUser ( ) ) ; if ( ! II ) return false ; Prepare ( ) ; Builder . CreateStore ( Src , AllocaAddr ) ; Value * Row = nullptr , * Col = nullptr ; std :: tie ( Row , Col ) = getShape ( II , OpNo ) ; std :: array < Value * , <NUM_LIT> > Args = { Row , Col , I8Ptr , Stride } ; Value * NewInst = Builder . CreateIntrinsic ( <STR_LIT> , None , Args ) ; Bitcast -> replaceAllUsesWith ( NewInst ) ; } else { auto * II = dyn_cast < IntrinsicInst > ( Src ) ; if ( ! II ) return false ; Prepare ( ) ; Value * Row = II -> getOperand ( <NUM_LIT> ) ; Value * Col = II


<s> TargetLowering :: ArgListTy Args = getDivRemArgList ( Op . getNode ( ) , DAG . getContext ( ) ) ; SDValue Callee = DAG . getExternalSymbol ( getLibcallName ( LC ) , getPointerTy ( DAG . getDataLayout ( ) ) ) ; Type * RetTy = ( Type * ) StructType :: get ( Ty , Ty , nullptr ) ; SDLoc dl ( Op ) ; TargetLowering :: CallLoweringInfo CLI ( DAG ) ; CLI . setDebugLoc ( dl ) . setChain ( InChain ) . setCallee ( getLibcallCallingConv ( LC ) , RetTy , Callee , std :: move ( Args ) ) . setInRegister ( ) . setSExtResult ( isSigned ) . setZExtResult ( ! isSigned ) ; std :: pair < SDValue , SDValue > CallInfo = LowerCallTo ( CLI


<s> std :: vector < std :: string > mul_y0_r6 ( Mul3 op ,


<s> OperandMatchResultTy parseBDLAddr64 ( OperandVector & Operands ) { return parseAddress ( Operands ,


<s> return ( __m128i ) __builtin_ia32_cvttps2udq128_mask ( ( __v4sf ) __A , ( __v4si ) _mm_setzero_si128 ( ) , ( __mmask8


<s> if ( MayStore ) return ! Defs . insert ( V ) || Uses . count ( V ) || SeenNoObjStore || SeenNoObjLoad ; Uses . insert ( V


<s> bool isTgSplitEnabled ( ) const { return EnableTgSplit


<s> int i ; if ( GET_CODE ( x ) == SYMBOL_REF || GET_CODE ( x ) == LABEL_REF ) return <NUM_LIT> ; if ( GET_CODE ( x ) == UNSPEC && ( XINT ( x , <NUM_LIT> ) == UNSPEC_PIC || XINT ( x , <NUM_LIT> ) == UNSPEC_GOT || XINT ( x ,

<NUM_LIT> ) == UNSPEC_GOTOFF || XINT ( x , <NUM_LIT> ) == UNSPEC_PLT || XINT ( x , <NUM_LIT> ) == UNSPEC_GOTSYM_OFF ) ) return <NUM_LIT> ;


<s> void <ISA_LIT>InstPrinter :: printImmediate ( const MCInst * MI , unsigned opNum , raw_ostream & O ) { const MCOperand & MO = MI -> getOperand


<s> if ( STI . getFeatureBits ( ) [ llvm :: <STR_LIT> ] && MI . getOperand ( <NUM_LIT> ) . isImm ( ) && MI . getOperand ( <NUM_LIT> ) . getImm ( ) != <NUM_LIT> ) { Info = <STR_LIT> <STR_LIT> ; return true ; } return false


<s> Start = Lex ( ) . getLoc ( ) ; } IntelExprStateMachine SM ; if ( ParseIntelExpression ( SM , End ) ) return nullptr ; if ( isParsingInlineAsm ( ) ) RewriteIntelExpression ( SM , Start , Tok . getLoc ( ) ) ; int64_t Imm = SM . getImm ( ) ; const MCExpr * Disp = SM . getSym ( ) ; const MCExpr * ImmDisp = MCConstantExpr :: create ( Imm , getContext ( ) ) ; if ( Disp && Imm ) Disp = MCBinaryExpr :: createAdd ( Disp , ImmDisp , getContext ( ) ) ; if ( ! Disp ) Disp = ImmDisp ; if ( ! SM . isMemExpr ( ) && ! RegNo ) return <STR_LIT> ( Disp , Start , End ) ; StringRef ErrMsg ; unsigned BaseReg = SM . getBaseReg ( ) ; unsigned IndexReg = SM . getIndexReg ( ) ; unsigned Scale = SM . getScale ( ) ; if ( ( BaseReg || IndexReg ) && CheckBaseRegAndIndexRegAndScale ( BaseReg , IndexReg , Scale , ErrMsg ) ) return ErrorOperand ( Start , ErrMsg ) ; if ( isParsingInlineAsm ( ) ) return CreateMemForInlineAsm ( RegNo , Disp , BaseReg , IndexReg , Scale , Start , End , Size , SM . getSymName ( ) , SM . getIdentifierInfo ( ) ) ; if ( ! ( BaseReg || IndexReg || RegNo ) ) return <STR_LIT>

( getPointerWidth ( ) , Disp , Start , End , Size ) ;


<s> int not_rc_reg ( rtx op , enum machine_mode


<s> static void getIntOperandsFromRegisterString ( StringRef RegString , SelectionDAG * CurDAG , const SDLoc & DL , std :: vector < SDValue > & Ops ) { SmallVector < StringRef , <NUM_LIT> > Fields ; RegString . split ( Fields ,


<s> auto Op = llvm :: make_unique < <ISA_LIT>Operand > ( k_RegList , Parser ) ; Op -> RegList . List = new SmallVector < unsigned , <NUM_LIT> > ( Regs . begin ( ) , Regs . end ( ) ) ; Op -> StartLoc = StartLoc ; Op -> EndLoc = EndLoc ; return


<s> int NumBytes = ( int ) MFI . getStackSize ( ) ; unsigned SAVEri = <STR_LIT> ; unsigned SAVErr = <STR_LIT> ; if ( FuncInfo -> isLeafProc ( ) ) { if ( NumBytes == <NUM_LIT> ) return ; SAVEri = <STR_LIT> ; SAVErr = <STR_LIT> ; } if ( MFI . adjustsStack ( ) && hasReservedCallFrame ( MF ) ) NumBytes += MFI . getMaxCallFrameSize ( ) ; NumBytes = Subtarget . getAdjustedFrameSize ( NumBytes ) ; if ( MFI . getMaxAlignment ( ) > <NUM_LIT> ) { NumBytes = alignTo ( NumBytes , MFI . getMaxAlignment ( ) ) ; } MFI . setStackSize ( NumBytes ) ; emit<ISA_LIT>Adjustment ( MF , MBB , MBBI , - NumBytes , SAVErr , SAVEri ) ; unsigned regFP = RegInfo . getDwarfRegNum ( <STR_LIT> , true ) ; unsigned CFIIndex = MF . addFrameInst ( MCCFIInstruction :: createDefCfaRegister ( nullptr , regFP ) ) ; BuildMI ( MBB , MBBI , dl , TII . get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; CFIIndex = MF . addFrameInst ( MCCFIInstruction :: createWindowSave ( nullptr ) ) ; BuildMI ( MBB , MBBI , dl , TII . get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; unsigned regInRA = RegInfo . getDwarfRegNum ( <STR_LIT> , true ) ; unsigned regOutRA = RegInfo . getDwarfRegNum ( <STR_LIT> , true ) ; CFIIndex = MF . addFrameInst ( MCCFIInstruction :: createRegister ( nullptr , regOutRA , regInRA ) ) ; BuildMI ( MBB , MBBI , dl , TII . get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; if ( NeedsStackRealignment ) { int64_t Bias = Subtarget . getStackPointerBias ( ) ; unsigned regUnbiased


<s> } if ( TII -> isLDSRetInstr ( MI -> getOpcode ( ) ) ) return <NUM_LIT> ; if ( TII -> isVector ( * MI ) || TII -> isCubeOp ( MI -> getOpcode ( ) ) || TII -> isReductionOp ( MI -> getOpcode ( ) ) ) return <NUM_LIT> ; unsigned NumLiteral = <NUM_LIT> ; for ( MachineInstr :: mop_iterator It = MI -> operands_begin ( ) , E = MI -> operands_end ( ) ; It != E


<s> Str . getAsInteger ( <NUM_LIT> , ShaderType ) ; } if ( ShaderType == ShaderType :: COMPUTE ) return false ; visit ( F ) ; visit ( F ) ; return false


<s> SDLoc DL ( Op ) ; SmallVector < SDValue , <NUM_LIT> > VTBLMask ; for ( int I : ShuffleMask ) VTBLMask . push_back ( DAG . getConstant ( I , DL , <STR_LIT> ) ) ; if ( V2 . getNode ( ) -> isUndef ( ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , DAG . getBuildVector ( <STR_LIT> , DL , VTBLMask ) ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , V2 , DAG . getBuildVector ( <STR_LIT> , DL , VTBLMask


<s> Value * <ISA_LIT>IREmitter :: visitFSETCC ( const


<s> unsigned CPUBitmask = <NUM_LIT> ; int CPUTopSavedRegOff ; const MachineFrameInfo & MFI = MF -> getFrameInfo ( ) ; const TargetRegisterInfo * TRI = MF -> getSubtarget ( ) . getRegisterInfo ( ) ; const std :: vector < CalleeSavedInfo > & CSI = MFI . getCalleeSavedInfo ( ) ; unsigned CPURegSize = TRI -> getRegSizeInBits ( <STR_LIT>


<s> using namespace <ISA_LIT> ; static const unsigned Regs01 [ ] = { LC0 , SA0 , LC1 , SA1 } ; static const unsigned Regs1 [ ] = { LC1 , SA1 } ; auto CheckRegs = IsInnerHWLoop ? makeArrayRef ( Regs01 , array_lengthof ( Regs01 ) ) : makeArrayRef ( Regs1 , array_lengthof ( Regs1 ) ) ; for ( unsigned R : CheckRegs ) if ( MI -> modifiesRegister ( R , TRI ) ) return true ; return false


<s> void \ fini_section ( ) \ { \ if ( in_section != in_fini ) \ { \ fprintf ( asm_out_file , <STR_LIT> , FINI_SECTION_ASM_OP ) ; \ in_section =


<s> ScheduleDAGInstrs * createPostMachineScheduler ( MachineSchedContext * C ) const override { llvm_unreachable ( <STR_LIT> )


<s> SMRange getLocRange ( ) const { return SMRange ( StartLoc ,


<s> Function * <ISA_LIT>PropagateAttributes :: findFunction ( const FeatureBitset & FeaturesNeeded , Function * OrigF ) { for ( Clone & C : Clones ) if ( C . OrigF == OrigF && FeaturesNeeded == C . FeatureMask ) return C . NewF ; return nullptr


<s> if ( ( unsigned ) Fixup . getKind ( ) != <STR_LIT> && ( unsigned ) Fixup . getKind ( ) != <STR_LIT> && ( unsigned ) Fixup . getKind ( ) != <STR_LIT> && ( unsigned ) Fixup . getKind ( ) != <STR_LIT> && ( unsigned ) Fixup . getKind ( ) != <STR_LIT> && ( unsigned ) Fixup . getKind ( ) != <STR_LIT> ) { if ( A ) { const MCSymbol & Sym = A -> getSymbol ( ) ; if ( Asm . isThumbFunc ( & Sym ) ) Value |= <NUM_LIT> ; } } if ( A && ( unsigned ) Fixup . getKind ( ) == <STR_LIT> ) { const MCSymbol & Sym = A -> getSymbol


<s> const MCExpr * getMemOff ( ) const { assert ( Kind == Memory && <STR_LIT> ) ; return Mem . Off


<s> void setOffset ( int64_t Offset_ ) { assert ( Offset_ >= <NUM_LIT>


<s> unsigned Rn = fieldFromInstruction32 ( Val , <NUM_LIT> , <NUM_LIT> ) ; unsigned Rm = fieldFromInstruction32 ( Val , <NUM_LIT> , <NUM_LIT> ) ; if ( ! Check ( S , DecodetGPRRegisterClass ( Inst , Rn , Address , Decoder ) )


<s> unsigned <ISA_LIT>TTIImpl :: getBoolVecToIntConversionCost ( unsigned Opcode , Type * Dst , const Instruction * I ) { assert ( Dst -> isVectorTy ( ) ) ; unsigned VF = cast < VectorType > ( Dst ) -> getNumElements ( ) ; unsigned Cost = <NUM_LIT> ; Type * CmpOpTy = ( ( I != nullptr ) ? getCmpOpsType ( I , VF ) : nullptr ) ; if ( CmpOpTy != nullptr ) Cost = getVectorBitmaskConversionCost ( CmpOpTy ,


<s> bool mayNeedRelaxation ( const MCInst & Inst )


<s> std :: string getPredType ( ICmpInst :: Predicate Pred ) { std :: string type = <STR_LIT> ; if ( Pred == CmpInst


<s> getJumpTargetOpValueMM ( const MCInst & MI , unsigned OpNo , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { const MCOperand & MO = MI . getOperand ( OpNo ) ; if ( MO . isImm ( ) ) return MO . getImm ( ) >> <NUM_LIT> ; assert ( MO . isExpr ( )


<s> unsigned Opc = N -> getOpcode ( ) ; assert ( ( ( Opc >= <STR_LIT> && Opc <= <STR_LIT> ) || ( Opc >= <STR_LIT> && Opc <= <STR_LIT> ) ) && <STR_LIT> ) ; const bool Scaled = Opc == <STR_LIT> || Opc == <STR_LIT> ; const bool Signed = Opc == <STR_LIT> || Opc == <STR_LIT> ; const bool Extended = Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ; SDLoc DL ( N ) ; SDValue Chain = N -> getOperand ( <NUM_LIT> ) ; SDValue Pg = N -> getOperand ( <NUM_LIT> ) ; SDValue Base = N -> getOperand ( <NUM_LIT> ) ; SDValue Offset = N -> getOperand ( <NUM_LIT> ) ; SDValue Ty = N -> getOperand ( <NUM_LIT> ) ; EVT ResVT = N -> getValueType


<s> O << <STR_LIT> ; O << <STR_LIT> ; O << <STR_LIT> ; O << <STR_LIT> ; unsigned PTXVersion = nvptxSubtarget . getPTXVersion ( ) ; O << <STR_LIT> << ( PTXVersion / <NUM_LIT> ) << <STR_LIT> << ( PTXVersion % <NUM_LIT> ) << <STR_LIT> ; O << <STR_LIT> ; O << nvptxSubtarget . getTargetName ( ) ; if ( nvptxSubtarget . getDrvInterface ( ) == <STR_LIT> ) O << <STR_LIT> ; if ( nvptxSubtarget . getDrvInterface ( ) == <STR_LIT> ) { if ( ! nvptxSubtarget . hasDouble ( ) ) O << <STR_LIT> ; } if ( MAI -> doesSupportDebugInformation ( ) ) O << <STR_LIT> ; O << <STR_LIT> ; O << <STR_LIT> ; if ( nvptxSubtarget . is64Bit ( ) ) O << <STR_LIT> ; else O << <STR_LIT> ; O <<


<s> static SDValue PerformBUILD_VECTORCombine ( SDNode * N , SelectionDAG


<s> EVT VT = Op . getValueType ( ) ; EVT PtrVT = DAG . getTargetLoweringInfo ( ) . getPointerTy ( ) ; std :: vector < EVT > NodeTys ; SDValue MFFSreg , InFlag ; NodeTys . push_back ( <STR_LIT> ) ; NodeTys . push_back ( <STR_LIT> ) ; SDValue Chain = DAG . getNode ( <STR_LIT> , dl , NodeTys , & InFlag , <NUM_LIT> ) ; int SSFI = MF . getFrameInfo ( ) -> CreateStackObject ( <NUM_LIT> , <NUM_LIT> , false ) ; SDValue StackSlot = DAG . getFrameIndex ( SSFI , PtrVT ) ; SDValue Store = DAG . getStore ( DAG . getEntryNode ( ) , dl , Chain , StackSlot , MachinePointerInfo ( ) , false , false , <NUM_LIT> ) ; SDValue Four = DAG . getConstant ( <NUM_LIT> , PtrVT ) ; SDValue Addr = DAG . getNode ( <STR_LIT> , dl , PtrVT , StackSlot , Four ) ; SDValue CWD = DAG . getLoad ( <STR_LIT> , dl , Store , Addr , MachinePointerInfo ( ) , false , false , <NUM_LIT> ) ; SDValue CWD1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , CWD , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDValue CWD2 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> ,

CWD , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ;


<s> case <STR_LIT> : TargetBBInMI = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : TargetBBInMI = <NUM_LIT> ; IsNegativeBranch = true ; break ; case <STR_LIT> : case <STR_LIT> : TargetBBInMI = <NUM_LIT> ; IsTestAndBranch = true ; break ; case <STR_LIT> : case <STR_LIT> : TargetBBInMI = <NUM_LIT> ; IsNegativeBranch = true ; IsTestAndBranch = true ; break ; } if ( IsTestAndBranch && MI . getOperand ( <NUM_LIT> ) . getImm ( ) ) return false ; assert ( MI . getParent ( ) && <STR_LIT> ) ; MachineBasicBlock * MBB = MI . getParent ( ) ; MachineFunction * MF = MBB -> getParent ( ) ; MachineRegisterInfo * MRI = & MF -> getRegInfo ( ) ; Register VReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( ! Register :: isVirtualRegister ( VReg ) ) return false ; MachineInstr * DefMI = MRI -> getVRegDef ( VReg ) ; while ( DefMI -> isCopy ( ) ) { Register CopyVReg = DefMI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( ! MRI -> hasOneNonDBGUse ( CopyVReg ) ) return false ; if ( ! MRI -> hasOneDef ( CopyVReg ) ) return false ; DefMI = MRI -> getVRegDef ( CopyVReg ) ; } switch ( DefMI -> getOpcode ( ) ) { default : return false ; case <STR_LIT> : case <STR_LIT> : { if ( IsTestAndBranch ) return false ; if ( DefMI -> getParent ( ) != MBB ) return false ; if ( ! MRI -> hasOneNonDBGUse ( VReg ) ) return false ; bool Is32Bit = ( DefMI -> getOpcode ( ) == <STR_LIT> ) ; uint64_t Mask = <STR_LIT> ( DefMI -> getOperand ( <NUM_LIT> ) . getImm ( ) , Is32Bit ? <NUM_LIT> : <NUM_LIT> ) ; if ( ! isPowerOf2_64 ( Mask ) ) return false ; MachineOperand & MO = DefMI -> getOperand ( <NUM_LIT> ) ; Register NewReg = MO . getReg ( ) ; if ( ! Register :: isVirtualRegister ( NewReg ) ) return false ; assert ( ! MRI -> def_empty ( NewReg ) && <STR_LIT> ) ; MachineBasicBlock & RefToMBB = * MBB ; MachineBasicBlock * TBB = MI . getOperand ( <NUM_LIT> ) . getMBB ( ) ; DebugLoc DL = MI . getDebugLoc ( ) ; unsigned Imm = Log2_64 ( Mask ) ; unsigned Opc = ( Imm < <NUM_LIT> ) ? ( IsNegativeBranch ? <STR_LIT> : <STR_LIT> ) : ( IsNegativeBranch ? <STR_LIT> : <STR_LIT> ) ; MachineInstr * NewMI = BuildMI ( RefToMBB , MI , DL , get ( Opc ) ) . addReg ( NewReg ) . addImm ( Imm ) . addMBB ( TBB ) ; MO . setIsKill ( false ) ; if ( ! Is32Bit && Imm < <NUM_LIT> ) NewMI -> getOperand ( <NUM_LIT> ) . setSubReg ( <STR_LIT> ) ; MI . eraseFromParent (


<s> <ISA_LIT>InstrAnalyzer * PIA = new <ISA_LIT>InstrAnalyzer ( Ctx ) ; const MCSection * TS = Ctx . getELFSection ( <STR_LIT> , ELF :: SHT_PROGBITS , <NUM_LIT> , SectionKind :: getText ( ) ) ; PIA -> SwitchSection ( TS ) ; return PIA


<s> LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << <STR_LIT> ) ; MachineBasicBlock * Pred = nullptr ; for ( auto * MBB : ML -> getHeader ( ) -> predecessors ( ) ) { if ( ! ML -> contains ( MBB ) ) { if ( Pred ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; Start = nullptr ; break ; } Pred = MBB ; Start = SearchForStart ( MBB ) ; } } } for ( auto * MBB : reverse ( ML -> getBlocks ( ) ) ) { for ( auto & MI : * MBB ) { if ( MI . getOpcode ( ) == <STR_LIT> ) Dec = & MI ; else if ( MI . getOpcode ( ) == <STR_LIT> ) End = & MI ; else if ( MI . getDesc ( ) . isCall ( ) ) Revert = true ; if ( ! Dec ) continue ; if ( MI . mayLoad ( ) || MI . mayStore ( ) ) Revert = MI . getOperand ( <NUM_LIT> ) . isReg ( ) && MI . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ; } if ( Dec && End && Revert ) break ; } if ( ! Start && ! Dec && ! End ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return Changed ; } if ( ! ( Start && Dec && End


<s> for ( size_t I = <NUM_LIT> ; I < FoundLocalVars . size ( ) ; I ++ ) { GlobalVariable * FGV = FoundLocalVars [ I ] ; Align DataAlign = <STR_LIT> ( DL , FGV ) ; uint64_t DataAlignV = DataAlign . value ( ) ; if ( uint64_t Rem = CurrentOffset % DataAlignV ) { uint64_t Padding = DataAlignV - Rem ; Type * ATy = ArrayType :: get ( Type :: getInt8Ty ( Ctx ) , Padding ) ; LocalVars . push_back ( new GlobalVariable ( M , ATy , false , GlobalValue :: InternalLinkage , UndefValue :: get ( ATy ) , <STR_LIT> , nullptr , GlobalValue :: NotThreadLocal , <ISA_LIT>AS :: LOCAL_ADDRESS , false ) ) ; CurrentOffset += Padding ; } LocalVars . push_back ( FGV ) ; CurrentOffset += DL . getTypeAllocSize ( FGV -> getValueType ( ) ) ; } } std :: vector < Type * > LocalVarTypes ; LocalVarTypes . reserve ( LocalVars . size ( ) ) ; std :: transform ( LocalVars . cbegin ( ) , LocalVars . cend ( ) , std :: back_inserter ( LocalVarTypes ) , [ ] ( const GlobalVariable * V ) -> Type * { return V -> getValueType ( ) ; } ) ; std :: string VarName ( F ? ( Twine ( <STR_LIT> ) + F -> getName ( ) + <STR_LIT> ) . str ( ) : <STR_LIT> ) ; StructType * LDSTy = StructType :: create ( Ctx , LocalVarTypes , VarName + <STR_LIT> ) ; Align MaxAlign = <STR_LIT> ( DL , LocalVars [ <NUM_LIT> ] ) ; GlobalVariable * SGV = new GlobalVariable ( M , LDSTy , false , GlobalValue :: InternalLinkage , UndefValue :: get ( LDSTy ) , VarName , nullptr , GlobalValue :: NotThreadLocal , <ISA_LIT>AS :: LOCAL_ADDRESS , false ) ; SGV -> setAlignment ( MaxAlign ) ; if ( ! F ) { appendToCompilerUsed ( M , { static_cast < GlobalValue * > ( ConstantExpr :: getPointerBitCastOrAddrSpaceCast ( cast < Constant > ( SGV ) , Type :: getInt8PtrTy ( Ctx ) ) ) } ) ; } removeFromUsedLists ( M , LocalVars ) ; Type * I32 = Type :: getInt32Ty ( Ctx ) ; for ( size_t I = <NUM_LIT> ; I < LocalVars . size ( ) ; I ++ ) { GlobalVariable * GV = LocalVars [ I ] ; Constant * GEPIdx [ ] = { ConstantInt :: get ( I32 , <NUM_LIT> ) , ConstantInt :: get ( I32 , I ) } ; Constant * GEP = ConstantExpr :: getGetElementPtr ( LDSTy , SGV , GEPIdx ) ; if ( F ) { GV -> replaceUsesWithIf ( GEP , [ F ] ( Use & U ) { return <STR_LIT> ( U . getUser ( ) , F ) ; } ) ; } else { GV -> replaceAllUsesWith ( GEP


<s> int NumFound = <NUM_LIT> ; unsigned MemOp = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> ; i < MI . getNumOperands ( ) ; ) { if ( isMem ( & MI


<s> assert ( ! ( isa < ConstantSDNode > ( Op1 ) && Op0 . getValueType ( ) == <STR_LIT> ) && <STR_LIT> ) ; if ( ( Op0 . getValueType ( ) == <STR_LIT> || Op0 . getValueType ( ) == <STR_LIT> || Op0 . getValueType ( ) == <STR_LIT> || Op0 . getValueType ( ) == <STR_LIT> ) ) { if ( Op0 . getValueType ( ) != <STR_LIT> && Op0 . getValueType ( ) != <STR_LIT> && ! DAG . getMachineFunction ( ) . getFunction ( ) -> optForMinSize ( ) && ! Subtarget . isAtom ( ) ) { unsigned ExtendOp = is<ISA_LIT>CCUnsigned ( <ISA_LIT>CC ) ? <STR_LIT> : <STR_LIT> ; Op0 = DAG . getNode ( ExtendOp


<s> const TargetRegisterClass * <ISA_LIT>RegisterInfo :: getPointerRegClass ( const MachineFunction & MF , unsigned Kind ) const { return &


<s> unsigned <ISA_LIT>MCCodeEmitter :: getShiftRightImm8 ( const MCInst & MI , unsigned Op , SmallVectorImpl <


<s> return ( __m256d ) __builtin_ia32_minpd256 ( ( __v4df )


<s> if ( MultOpc != <STR_LIT> && MultOpc != <STR_LIT> ) return false ; if ( MultHi . getResNo ( ) != <NUM_LIT> || MultLo . getResNo ( ) != <NUM_LIT> ) return false ; if ( ! MultHi . hasOneUse ( ) || ! MultLo . hasOneUse ( ) ) return false ; SDValue Chain = CurDAG -> getEntryNode ( ) ; DebugLoc dl = SUBENode -> getDebugLoc ( ) ; MultOpc = MultOpc == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; SDValue MSub = CurDAG -> getNode ( MultOpc , dl , <STR_LIT> , MultNode -> getOperand ( <NUM_LIT> ) , MultNode

-> getOperand ( <NUM_LIT> ) , SUBCNode -> getOperand ( <NUM_LIT> ) , SUBENode -> getOperand ( <NUM_LIT> ) ) ;


<s> for ( auto & Arg : F . args ( ) ) { ArgInfo OrigArgInfo ( VRegs [ Idx ] , Arg . getType ( ) ) ; setArgFlags ( OrigArgInfo , Idx + AttributeList :: FirstArgIndex , DL , F ) ; splitToValueTypes ( OrigArgInfo , SplitArgInfos , MF ) ; Idx ++ ; } if ( ! MBB . empty ( ) ) MIRBuilder . setInstr ( * MBB . begin ( ) ) ; if ( ! handleAssignments ( MIRBuilder , SplitArgInfos , ArgHandler ) ) return false ; MIRBuilder . setMBB ( MBB )


<s> arg_reg = ROUND_REG ( * get_cumulative_args ( cum ) , mode ) ; if ( arg_reg < NPARM_REGS ) return handle_structs_in_regs ( mode , type , FIRST_PARM_REG + arg_reg ) ; return


<s> MCSymbol * EHInfoLabel = TargetLoweringObjectFileXCOFF :: getEHInfoTableSymbol ( MF ) ; OutStreamer -> emitLabel ( EHInfoLabel ) ; OutStreamer -> emitInt32 ( <NUM_LIT> ) ; const DataLayout & DL = MMI -> getModule ( ) -> getDataLayout ( ) ; const unsigned PointerSize = DL . getPointerSize


<s> void addExactFPImmOperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT> ) ; assert ( bool ( isExactFPImm < ImmIs0 , ImmIs1 > ( ) ) &&


<s> if ( selectCall ( I ) ) return true ; break ; case Instruction :: Select : return selectSelect ( I ) ; case Instruction :: Trunc : return selectTrunc ( I ) ; case Instruction :: ZExt : return selectZExt ( I ) ; case Instruction :: SExt : return selectSExt ( I ) ; case Instruction :: ICmp : return selectICmp ( I ) ; case Instruction :: FCmp : return selectFCmp ( I ) ; case Instruction :: BitCast : return selectBitCast (


<s> DAG ( <NUM_LIT> ) , TII ( <NUM_LIT> ) , TRI ( <NUM_LIT> ) , MRI (


<s> if ( & MF -> front ( ) == MBB ) return <STR_LIT> ; const <ISA_LIT>Subtarget & Subtarget = MF -> getSubtarget < <ISA_LIT>Subtarget > ( ) ; const <ISA_LIT>RegisterInfo & TRI = * Subtarget . getRegisterInfo ( ) ; LivePhysRegs LiveRegs ( TRI ) ; LiveRegs . addLiveIns ( * MBB ) ; const MCPhysReg * CSRegs = TRI . getCalleeSavedRegs ( MF ) ; for ( unsigned i = <NUM_LIT> ; CSRegs [ i ] ; ++ i ) LiveRegs . addReg ( CSRegs [ i ] ) ; const MachineRegisterInfo & MRI = MF -> getRegInfo (


<s> o << getTagName ( PREFIX_SYMBOL ) << prefix << <STR_LIT> << num << <STR_LIT> ; return o .


<s> <ISA_LIT>AsmParser :: OperandMatchResultTy <ISA_LIT>AsmParser :: parseInvNum ( SmallVectorImpl < MCParsedAsmOperand * > & Operands ) { const MCExpr * IdVal ; if ( Parser . getTok ( ) . is ( AsmToken :: Dollar ) ) return MatchOperand_NoMatch ; SMLoc S = Parser . getTok ( ) . getLoc ( ) ; if ( getParser ( ) . parseExpression ( IdVal ) ) return MatchOperand_ParseFail ; const MCConstantExpr * MCE = dyn_cast < MCConstantExpr > ( IdVal ) ; assert ( MCE && <STR_LIT> ) ; int64_t Val = MCE -> getValue ( ) ; SMLoc E = SMLoc :: getFromPointer ( Parser . getTok ( ) . getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; Operands . push_back ( <STR_LIT> ( MCConstantExpr :: Create ( <NUM_LIT> - Val , getContext ( ) )


<s> if ( totalsize == <NUM_LIT> || elementsize == <NUM_LIT> ) return false ; auto lane = wi :: to_widest ( arg2 ) ; auto high = wi :: udiv_trunc ( totalsize


<s> static void is_altivec_return_reg ( rtx reg , void * xyes ) { bool * yes = (


<s> <ISA_LIT>TargetMachine & get<ISA_LIT>TargetMachine ( ) const { return getTM < <ISA_LIT>TargetMachine


<s> static bool nios2_cannot_force_const_mem ( machine_mode mode ATTRIBUTE_UNUSED , rtx x


<s> const char * fmt ; int i ; if ( SYMBOL_REF_P ( x ) ) return <NUM_LIT> ; if ( GET_CODE ( x ) == UNSPEC && XINT ( x , <NUM_LIT> ) == UNSPEC_TLS ) return <NUM_LIT> ; fmt = GET_RTX_FORMAT ( GET_CODE ( x ) ) ; for ( i = GET_RTX_LENGTH ( GET_CODE ( x ) ) - <NUM_LIT> ; i >= <NUM_LIT> ; i -- ) { if ( fmt [ i ] == 'E' ) { int j ; for ( j = XVECLEN ( x , i ) - <NUM_LIT> ; j >= <NUM_LIT> ; j -- ) if ( symbol_mentioned_p ( XVECEXP ( x , i , j ) ) ) return <NUM_LIT> ; } else if ( fmt [ i ] == 'e' && symbol_mentioned_p ( XEXP ( x , i ) )


<s> bool <ISA_LIT>TargetLowering :: canCombineStoreAndExtract ( Type * VectorTy , Value * Idx , unsigned & Cost ) const { if ( ! Subtarget -> hasNEON ( ) ) return false ; if ( VectorTy -> isFPOrFPVectorTy ( ) ) return false ; if ( ! isa < ConstantInt > ( Idx ) ) return false ; assert ( VectorTy -> isVectorTy ( ) && <STR_LIT> ) ; unsigned BitWidth = cast < VectorType > ( VectorTy ) -> getBitWidth ( ) ; if ( BitWidth == <NUM_LIT> ||


<s> bool <ISA_LIT>AsmPrinter :: runOnMachineFunction ( MachineFunction & MF ) { <ISA_LIT>FI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; AsmPrinter :: runOnMachineFunction


<s> void setVarArgsFrameIndex ( int Index


<s> static const <ISA_LIT>MCExpr * CreateGOTTPREL ( const MCExpr * Expr , MCContext & Ctx ) { return Create ( VK_AARCH64_GOTTPREL , Expr


<s> assert ( TII -> getNamedOperand ( MI , <STR_LIT> :: soffset ) -> getReg ( ) == MF -> getInfo < <ISA_LIT>MachineFunctionInfo > ( ) -> getStackPtrOffsetReg ( ) && <STR_LIT> ) ; MachineOperand * OffsetOp = TII -> getNamedOperand ( MI , <STR_LIT> :: offset ) ; int64_t NewOffset = OffsetOp -> getImm ( ) + Offset ; assert ( isUInt < <NUM_LIT> > ( NewOffset ) && <STR_LIT> ) ; FIOp -> ChangeToRegister ( BaseReg


<s> bool <ISA_LIT>InstrInfo :: isTailCall ( const MachineInstr * MI ) const { if ( ! MI -> isBranch


<s> const MCOperand MO = MI . getOperand ( OpIdx ) ; if ( MO . isExpr ( ) ) return :: getBranchTargetOpValue ( MI , OpIdx , <STR_LIT> , Fixups , STI ) ; return ( MO . getImm (


<s> static bool nvptx_pass_by_reference ( cumulative_args_t , const function_arg_info & arg ) { return pass_in_memory ( arg . mode ,


<s> bool <ISA_LIT>InstrInfo :: readsLDSSrcReg ( const MachineInstr * MI ) const { if ( ! isALUInstr ( MI -> getOpcode ( ) ) ) { return false ; } for ( MachineInstr :: const_mop_iterator I = MI -> operands_begin ( ) , E = MI -> operands_end ( ) ; I


<s> rtx_code_label * neglab , * donelab ; rtx i0 , i1 , f0 , in , out ; machine_mode mode , inmode ; inmode = GET_MODE ( operands [ <NUM_LIT> ] ) ; gcc_assert ( inmode == SImode || inmode == DImode ) ; out = operands [ <NUM_LIT> ] ; in = force_reg ( inmode , operands [ <NUM_LIT> ] ) ; mode = GET_MODE ( out ) ; neglab = gen_label_rtx ( ) ; donelab = gen_label_rtx ( ) ; f0 = gen_reg_rtx ( mode ) ; emit_cmp_and_jump_insns ( in , const0_rtx , LT , const0_rtx , inmode , <NUM_LIT>


<s> OutStreamer . AddBlankLine ( ) ; } OutStreamer . EmitAssemblerFlag ( MCAF_SubsectionsViaSymbols ) ; } if ( Subtarget -> isTargetCOFF ( ) ) { <ISA_LIT>COFFMachineModuleInfo & COFFMMI = MMI -> getObjFileInfo < <ISA_LIT>COFFMachineModuleInfo > ( ) ; for ( <ISA_LIT>COFFMachineModuleInfo :: stub_iterator I = COFFMMI . stub_begin ( ) , E = COFFMMI . stub_end ( ) ; I != E ; ++ I ) { O << <STR_LIT> << I -> getKeyData ( ) << <STR_LIT> << COFF :: C_EXT << <STR_LIT> << ( COFF :: DT_FCN << COFF :: N_BTSHFT ) << <STR_LIT> ; } if ( Subtarget -> isTargetCygMing ( ) ) { std :: vector < const MCSymbol * > DLLExportedFns , DLLExportedGlobals ; TargetLoweringObjectFileCOFF & TLOFCOFF = static_cast < TargetLoweringObjectFileCOFF & > ( getObjFileLowering ( ) ) ; for ( Module :: const_iterator I = M . begin ( ) , E = M . end ( ) ; I != E ; ++ I ) if ( I -> hasDLLExportLinkage ( ) ) DLLExportedFns . push_back ( Mang -> getSymbol ( I ) ) ; for ( Module :: const_global_iterator I = M . global_begin ( ) , E = M . global_end ( ) ; I != E ; ++ I ) if ( I -> hasDLLExportLinkage ( ) ) DLLExportedGlobals . push_back ( Mang -> getSymbol ( I ) ) ; if ( ! DLLExportedGlobals . empty ( ) || ! DLLExportedFns . empty ( ) ) { OutStreamer . SwitchSection ( TLOFCOFF . getCOFFSection ( <STR_LIT> , true , SectionKind :: getMetadata ( ) ) ) ; for ( unsigned i = <NUM_LIT> , e = DLLExportedGlobals . size ( ) ; i != e ; ++ i ) O << <STR_LIT> << * DLLExportedGlobals [ i ] << <STR_LIT> ; for ( unsigned i = <NUM_LIT> , e = DLLExportedFns . size ( ) ; i != e ; ++ i ) O << <STR_LIT> << * DLLExportedFns [ i ] << <STR_LIT> ; } } } if ( Subtarget -> isTargetELF ( ) ) { TargetLoweringObjectFileELF & TLOFELF = static_cast < TargetLoweringObjectFileELF &


<s> const MCInstrDesc & II = TII . get ( MachineInstOpcode ) ; Op0 = constrainOperandRegClass ( II , Op0 , <NUM_LIT> ) ; Op1 = constrainOperandRegClass ( II , Op1 , <NUM_LIT> ) ; Op2 = constrainOperandRegClass ( II , Op1 , <NUM_LIT> ) ; if ( II . getNumDefs ( ) >= <NUM_LIT> ) { AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , II , ResultReg ) . addReg ( Op0 , Op0IsKill * RegState :: Kill

) . addReg ( Op1 , Op1IsKill * RegState :: Kill ) . addReg ( Op2 , Op2IsKill * RegState :: Kill ) ) ;


<s> bool fixupNeedsRelaxation ( const MCFixup & Fixup , uint64_t Value , const MCInstFragment * DF , const MCAsmLayout & Layout ) const { assert ( <NUM_LIT>


<s> assert ( C -> isStaticAlloca ( ) && <STR_LIT> ) ; <ISA_LIT>AddressMode AM ; if ( ! <ISA_LIT>SelectAddress ( C , AM ) ) return <NUM_LIT> ; unsigned Opc = TLI . getPointerTy ( DL ) == <STR_LIT> ? ( Subtarget -> isTarget64BitILP32 ( ) ? <STR_LIT> : <STR_LIT> ) : <STR_LIT> ; const TargetRegisterClass * RC = TLI . getRegClassFor ( TLI . getPointerTy ( DL ) ) ; Register ResultReg = createResultReg ( RC ) ; addFullAddress ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , ResultReg ) , AM ) ; return ResultReg


<s> void <ISA_LIT>InstPrinter :: printSysCROperand ( const MCInst * MI , unsigned OpNo ,


<s> static bool fitsIntoFixup ( const int64_t SignedValue , const bool IsPCRel16 ) { return SignedValue >= ( IsPCRel16 ? INT16_MIN : INT8_MIN ) && SignedValue


<s> auto OffR30 = MCCFIInstruction :: createOffset ( FrameLabel , DwFPReg , - <NUM_LIT> ) ; BuildMI ( MBB , At , DL , CFID ) . addCFIIndex ( MF . addFrameInst ( OffR30 ) ) ; } static unsigned int RegsToMove [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; const std :: vector < CalleeSavedInfo > & CSI = MFI . getCalleeSavedInfo ( ) ; for ( unsigned i = <NUM_LIT> ; RegsToMove [ i ] != <STR_LIT> ; ++ i ) { unsigned Reg = RegsToMove [ i ] ; auto IfR = [ Reg ] ( const CalleeSavedInfo & C ) -> bool { return C . getReg ( ) == Reg ; } ; auto F = find_if ( CSI , IfR ) ; if ( F == CSI . end ( ) ) continue ; int64_t Offset ; if ( HasFP ) { Offset = MFI . getObjectOffset ( F -> getFrameIdx ( ) ) ; } else { Register FrameReg ; Offset = getFrameIndexReference ( MF , F -> getFrameIdx ( ) , FrameReg ) ; } Offset -= <NUM_LIT> ; if ( Reg < <STR_LIT> || Reg > <STR_LIT>


<s> return B . buildBuildVector ( LLT :: fixed_vector ( <NUM_LIT> , S32 ) , PackedRegs ) . getReg ( <NUM_LIT> ) ; } if ( StoreVT . getNumElements ( ) == <NUM_LIT> ) { SmallVector < Register , <NUM_LIT> > PackedRegs ; auto Unmerge = B . buildUnmerge ( S16 , Reg ) ; for ( int I = <NUM_LIT> , E = Unmerge -> getNumOperands ( ) - <NUM_LIT> ; I != E ; ++ I ) PackedRegs . push_back ( Unmerge . getReg ( I ) ) ; PackedRegs . resize ( <NUM_LIT> , B . buildUndef ( S16 ) . getReg ( <NUM_LIT> ) ) ; Reg = B . buildBuildVector ( LLT :: fixed_vector ( <NUM_LIT> , S16 ) , PackedRegs ) . getReg ( <NUM_LIT> ) ; return B . buildBitcast ( LLT :: fixed_vector ( <NUM_LIT> , S32 ) , Reg ) . getReg ( <NUM_LIT> ) ; } if ( StoreVT . getNumElements ( ) == <NUM_LIT> ) { SmallVector < Register , <NUM_LIT> > PackedRegs ; Reg = B . buildBitcast ( LLT :: fixed_vector ( <NUM_LIT> , S32 ) , Reg ) . getReg ( <NUM_LIT> ) ; auto Unmerge = B . buildUnmerge ( S32 , Reg ) ; for ( int I = <NUM_LIT> , E = Unmerge -> getNumOperands ( ) - <NUM_LIT> ; I != E ; ++ I ) PackedRegs . push_back ( Unmerge . getReg ( I ) ) ; PackedRegs . resize ( <NUM_LIT> , B . buildUndef ( S32 ) . getReg ( <NUM_LIT> ) ) ; return B . buildBuildVector ( LLT :: fixed_vector ( <NUM_LIT> , S32 ) , PackedRegs ) . getReg ( <NUM_LIT> ) ; } llvm_unreachable ( <STR_LIT>


<s> unsigned BasePtr = ( TFI . hasFP ( MF ) && ! MI . getFlag ( MachineInstr :: FrameSetup ) ) ? <STR_LIT> : <STR_LIT> ; if ( isOnStackCache ) BasePtr = <STR_LIT> ; unsigned opcode = MI . getOpcode ( ) ; switch ( opcode ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : assert ( ( Offset & <NUM_LIT> ) == <NUM_LIT> ) ; Offset = ( Offset >> <NUM_LIT> ) + FrameDisplacement ; if ( ! isInt < <NUM_LIT> > ( Offset ) ) { computeLargeFIOffset ( MRI , Offset , BasePtr , II , <NUM_LIT> ) ; computedLargeOffset = true ; } break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : assert ( ( Offset & <NUM_LIT> ) == <NUM_LIT> ) ; Offset = ( Offset >> <NUM_LIT> ) + FrameDisplacement ; if ( ! isInt < <NUM_LIT> > ( Offset ) ) { computeLargeFIOffset ( MRI , Offset , BasePtr , II , <NUM_LIT> ) ; computedLargeOffset = true ; } break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Offset += FrameDisplacement ; if ( ! isInt < <NUM_LIT> > ( Offset ) ) { computeLargeFIOffset ( MRI , Offset , BasePtr , II , <NUM_LIT> ) ; computedLargeOffset = true ; } break ; case <STR_LIT> : Offset += FrameDisplacement ; if ( ! isUInt < <NUM_LIT> > ( Offset ) ) { const MCInstrDesc & newMCID = TII . get ( <STR_LIT> ) ; MI . setDesc ( newMCID ) ; } break ; case <STR_LIT> : case <STR_LIT> : Offset += FrameDisplacement ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } if ( opcode == <STR_LIT> || opcode == <STR_LIT> ) { expandPseudoPregInstr ( II , Offset , BasePtr , isOnStackCache ) ; return ; } switch ( opcode ) { case <STR_LIT> : case <STR_LIT> : opcode = <STR_LIT> ;


<s> static MachineBasicBlock :: iterator nextIfDebug ( MachineBasicBlock :: iterator I , MachineBasicBlock :: iterator End ) { for ( ; I != End ; ++ I ) { if ( ! I ->


<s> int ia32_multipass_dfa_lookahead ( void ) { if ( reload_completed ) return ix86_issue_rate ( ) ; return <NUM_LIT>


<s> Record . reserve ( N -> getElements ( ) . size ( ) + <NUM_LIT> ) ; Record . push_back ( N -> isDistinct (


<s> hi = ( ( ( delta - lo ) & <NUM_LIT> ) ^ <NUM_LIT> ) - <NUM_LIT> ; if ( hi + lo == delta ) { if ( hi ) emit_insn ( gen_adddi3 ( this_rtx , this_rtx , GEN_INT ( hi ) ) ) ; if ( lo ) emit_insn ( gen_adddi3 ( this_rtx , this_rtx , GEN_INT ( lo ) ) ) ; } else { rtx tmp = alpha_emit_set_long_const ( gen_rtx_REG ( Pmode , <NUM_LIT> ) , delta , - ( delta < <NUM_LIT> ) ) ; emit_insn ( gen_adddi3 ( this_rtx , this_rtx , tmp ) ) ; } if ( vcall_offset ) { rtx tmp , tmp2 ; tmp = gen_rtx_REG ( Pmode , <NUM_LIT> ) ; emit_move_insn ( tmp , gen_rtx_MEM ( Pmode , this_rtx ) ) ; lo = ( ( vcall_offset & <NUM_LIT> ) ^ <NUM_LIT> ) - <NUM_LIT> ; hi = ( ( ( vcall_offset - lo ) & <NUM_LIT> ) ^ <NUM_LIT> ) - <NUM_LIT> ; if ( hi + lo == vcall_offset ) { if ( hi ) emit_insn ( gen_adddi3 ( tmp , tmp , GEN_INT ( hi ) ) ) ; } else { tmp2 = alpha_emit_set_long_const ( gen_rtx_REG ( Pmode , <NUM_LIT> ) , vcall_offset , - ( vcall_offset < <NUM_LIT> ) ) ; emit_insn ( gen_adddi3 ( tmp , tmp , tmp2 ) ) ; lo = <NUM_LIT> ; } if ( lo ) tmp2 = gen_rtx_PLUS ( Pmode , tmp , GEN_INT ( lo ) ) ; else tmp2 = tmp ; emit_move_insn ( tmp , gen_rtx_MEM ( Pmode ,


__artificial__ ) ) _mm512_set1_ps ( float __A ) {


<s> tree prev_tree = target_option_current_node ; tree cur_tree ; struct cl_target_option * prev_opt ; struct cl_target_option * cur_opt ; if ( ! args ) { cur_tree = ( ( pop_target ) ? pop_target : target_option_default_node ) ; cl_target_option_restore ( & global_options , & global_options_set , TREE_TARGET_OPTION ( cur_tree ) ) ; } else { cur_tree = arm_valid_target_attribute_tree ( args , & global_options , & global_options_set ) ; if ( cur_tree == NULL_TREE ) { cl_target_option_restore ( & global_options , & global_options_set , TREE_TARGET_OPTION ( prev_tree ) ) ; return false ; } target_option_current_node = cur_tree ; arm_configure_build_target ( & arm_active_target , TREE_TARGET_OPTION ( cur_tree ) , false ) ; arm_option_reconfigure_globals ( ) ; } prev_opt = TREE_TARGET_OPTION


<s> std :: unique_ptr < MCObjectTargetWriter > createObjectTargetWriter ( ) const override { return create<ISA_LIT>ObjectWriter ( OSABI


<s> assert ( GISel && <STR_LIT> ) ; return GISel -> getMachineLegalizer


<s> void <ISA_LIT>AsmPrinter :: printMandatoryPredicateOperand ( const MachineInstr * MI , int OpNum ) { <STR_LIT> CC = ( <STR_LIT> ) MI -> getOperand ( OpNum )


<s> EVT LoadVT = N -> getValueType ( <NUM_LIT> ) ; if ( LoadVT == <STR_LIT> ) LoadVT = <STR_LIT> ; SDValue BSLoad = DAG . getMemIntrinsicNode ( <STR_LIT> , SDLoc ( N ) , DAG . getVTList ( LoadVT , <STR_LIT> ) , Ops , LD -> getMemoryVT ( ) , LD -> getMemOperand ( ) ) ; SDValue ResVal = BSLoad ; if ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT> ) ResVal = DAG . getNode ( <STR_LIT> , SDLoc ( N ) , <STR_LIT> , BSLoad ) ; DCI . CombineTo ( N , ResVal ) ; DCI . CombineTo ( Load . getNode ( ) , ResVal , BSLoad . getValue ( <NUM_LIT> ) ) ; return SDValue ( N


<s> LLVMContext & Context = M -> getContext ( ) ; bool LE = TM . isLittleEndian ( ) ; std :: string Name = F . getName ( ) ; std :: string SectionName = <STR_LIT> + Name ; std :: string StubName = <STR_LIT> + Name ; Function * FStub = M -> getFunction ( StubName ) ; if ( FStub && ! FStub -> isDeclaration ( ) ) return ; FStub = Function :: Create ( F . getFunctionType ( ) , Function :: InternalLinkage , StubName , M ) ; FStub -> addFnAttr ( <STR_LIT> ) ; FStub -> addFnAttr ( Attribute :: Naked ) ; FStub -> addFnAttr ( Attribute :: NoInline ) ; FStub -> addFnAttr ( Attribute :: NoUnwind ) ; FStub -> addFnAttr ( <STR_LIT> ) ; FStub -> setSection ( SectionName ) ; BasicBlock * BB = BasicBlock :: Create ( Context , <STR_LIT> , FStub ) ; FPReturnVariant RV = whichFPReturnVariant ( FStub -> getReturnType (


<s> CC = <STR_LIT> ( CC ) ; unsigned CCReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; MachineBasicBlock * MBB = MI -> getParent ( ) ; MachineInstr * BMI = & MBB -> back ( ) ; bool NeedSplit = ( BMI != MI ) || ! BBHasFallthrough ( MBB ) ; ++ NumCBrFixed ; if ( BMI != MI ) { if ( std :: next ( MachineBasicBlock :: iterator ( MI ) ) == std :: prev ( MBB -> end ( ) ) && BMI -> getOpcode ( ) == Br . UncondBr ) { MachineBasicBlock * NewDest = BMI -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; if ( isBBInRange ( MI , NewDest , Br . MaxDisp ) ) { DEBUG ( dbgs ( ) << <STR_LIT> << * BMI ) ; BMI -> getOperand ( <NUM_LIT> ) . setMBB ( DestBB ) ; MI -> getOperand ( <NUM_LIT> ) . setMBB ( NewDest ) ; MI -> getOperand ( <NUM_LIT> ) . setImm ( CC ) ; return true ; } } } if ( NeedSplit ) { splitBlockBeforeInstr ( MI ) ; int delta = TII -> GetInstSizeInBytes ( & MBB -> back ( ) ) ; BBInfo [ MBB -> getNumber ( ) ] . Size -= delta ; MBB -> back ( ) . eraseFromParent ( ) ; } MachineBasicBlock * NextBB = & * ++ MBB -> getIterator ( ) ; DEBUG ( dbgs ( ) << <STR_LIT> << DestBB -> getNumber ( ) << <STR_LIT> << NextBB -> getNumber ( ) << <STR_LIT> ) ; BuildMI ( MBB , DebugLoc ( ) , TII -> get ( MI -> getOpcode ( ) ) ) . addMBB ( NextBB ) . addImm ( CC ) . addReg ( CCReg ) ; Br . MI = & MBB -> back ( ) ; BBInfo [ MBB -> getNumber ( ) ] . Size += TII -> GetInstSizeInBytes ( & MBB -> back ( ) ) ; if ( isThumb ) BuildMI ( MBB , DebugLoc ( ) , TII -> get ( Br . UncondBr ) ) . addMBB ( DestBB ) . addImm ( <STR_LIT> ) . addReg ( <NUM_LIT> ) ; else BuildMI ( MBB , DebugLoc ( ) , TII -> get ( Br . UncondBr ) ) . addMBB ( DestBB ) ; BBInfo [ MBB -> getNumber ( ) ] . Size += TII -> GetInstSizeInBytes ( & MBB -> back ( ) ) ; unsigned MaxDisp = getUnconditionalBrDisp ( Br . UncondBr ) ; ImmBranches . push_back ( ImmBranch ( & MBB -> back ( ) , MaxDisp , false , Br . UncondBr ) ) ; BBInfo [ MI -> getParent ( ) -> getNumber ( ) ] . Size -= TII -> GetInstSizeInBytes ( MI ) ; MI -> eraseFromParent ( ) ; adjustBBOffsetsAfter ( MBB ) ; return true


<s> if ( MF -> getFunction ( ) . getCallingConv ( ) != CallingConv :: CXX_FAST_TLS ) return nullptr ; if ( ! MF -> getInfo < <ISA_LIT>FunctionInfo > ( ) -> isSplitCSR ( ) ) return nullptr ; bool SaveR2 = ! getReservedRegs ( * MF


<s> unsigned TySize = Func -> getParent ( ) -> getDataLayout ( ) . getTypeSizeInBits ( RootTy ) / <NUM_LIT> ; IRBuilder < > IRB ( CI ) ; if ( isa < ConstantInt > ( Size ) && TySize == cast < ConstantInt > ( Size ) -> getZExtValue ( ) ) { copyMemory ( Dst , Src , Ty , ValArr , IRB ) ; RemoveInstrs . push_back ( CI ) ; for ( auto Val : RemoveInstrs ) InsertIntoSet ( LazyRemovalSet , Val ) ; } else { llvm_unreachable ( <STR_LIT>


<s> return & <STR_LIT> ; case <NUM_LIT> : return & <STR_LIT> ; case <NUM_LIT> : return & <STR_LIT> ; case <NUM_LIT> : return & <STR_LIT> ; case <NUM_LIT> : return & <STR_LIT> ; case <NUM_LIT> : return & <STR_LIT>


<s> bool <ISA_LIT>AsmParser :: parseDirectiveSEHSetFP ( SMLoc L


<s> assert ( MI -> mayLoad ( ) && MI -> mayStore ( ) ) ; bool Changed = false ; if ( ( AddrSpace & <STR_LIT> ) != <STR_LIT> ) { switch ( Scope ) { case <STR_LIT> : Changed |= enableSC1Bit ( MI ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case


<s> static bool is_imported_p ( rtx x ) { if ( ! TARGET_DLLIMPORT_DECL_ATTRIBUTES || GET_CODE ( x ) != SYMBOL_REF ) return false ; return SYMBOL_REF_DLLIMPORT_P ( x ) || SYMBOL_REF_STUBVAR_P


<s> std :: string Ret ; Ret += <STR_LIT> ; Ret += DataLayout :: getManglingComponent ( TT ) ; Ret += <STR_LIT>


<s> raw_svector_ostream OSCFIInst ( CFIInst ) ; SmallString < <NUM_LIT> > Block ; raw_svector_ostream OSBlock ( Block ) ; OSCFIInst << uint8_t ( dwarf :: DW_CFA_expression ) ; encodeULEB128 ( DwarfSGPR , OSCFIInst ) ; for ( <ISA_LIT>MachineFunctionInfo :: SpilledReg Spill : VGPRSpills ) { encodeDwarfRegisterLocation ( MCRI . getDwarfRegNum ( Spill . VGPR , false ) , OSBlock ) ; OSBlock << uint8_t ( dwarf :: DW_OP_bit_piece ) ; const unsigned SGPRBitSize = <NUM_LIT> ; encodeULEB128 ( SGPRBitSize , OSBlock ) ; encodeULEB128 ( SGPRBitSize * Spill . Lane , OSBlock ) ; } encodeULEB128 ( Block . size ( ) ,


<s> addPass ( createLowerInvokePass ( ) ) ; addPass ( createUnreachableBlockEliminationPass ( ) ) ; } if ( EnableEmException || EnableEmSjLj ) addPass ( create<ISA_LIT>LowerEmscriptenEHSjLj ( EnableEmException , EnableEmSjLj ) ) ; TargetPassConfig :: addIRPasses ( )


<s> if ( CC == <STR_LIT> ) if ( SDValue Flags = combineCarryThroughADD ( EFLAGS , DAG ) ) return Flags ; if ( SDValue R = checkBoolTestSetCCCombine ( EFLAGS


<s> while ( MF . size ( ) > <NUM_LIT> ) MF . erase ( std :: next ( MF . begin ( ) ) ) ; MachineBasicBlock * CaptureSpec = MF . CreateMachineBasicBlock ( Entry -> getBasicBlock ( ) ) ; MachineBasicBlock * CallTarget = MF . CreateMachineBasicBlock ( Entry -> getBasicBlock ( ) ) ; MCSymbol * TargetSym = MF . getContext ( ) . createTempSymbol ( ) ; MF . push_back ( CaptureSpec ) ; MF . push_back ( CallTarget ) ; const unsigned CallOpc = Is64Bit ? <STR_LIT> : <STR_LIT> ; const unsigned RetOpc = Is64Bit ? <STR_LIT> : <STR_LIT> ; Entry -> addLiveIn ( Reg ) ; BuildMI ( Entry , DebugLoc ( ) , TII -> get ( CallOpc ) ) . addSym ( TargetSym ) ; Entry -> addSuccessor ( CaptureSpec ) ; BuildMI ( CaptureSpec , DebugLoc ( ) , TII -> get ( <STR_LIT> ) ) ; BuildMI ( CaptureSpec , DebugLoc ( ) , TII -> get ( <STR_LIT> ) ) ; BuildMI ( CaptureSpec , DebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addMBB ( CaptureSpec ) ; CaptureSpec -> setHasAddressTaken ( ) ; CaptureSpec -> addSuccessor ( CaptureSpec ) ; CallTarget -> addLiveIn ( Reg ) ; CallTarget -> setHasAddressTaken ( ) ; CallTarget -> setLogAlignment ( <NUM_LIT> ) ; insertRegReturnAddrClobber ( * CallTarget , Reg ) ; CallTarget -> back ( ) . setPreInstrSymbol ( MF , TargetSym ) ; BuildMI ( CallTarget , DebugLoc ( ) ,


<s> SDVTList NodeTys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SDLoc dl ( GA ) ; SDValue TGA = DAG . getTargetGlobalAddress ( GA -> getGlobal ( ) , dl , GA -> getValueType ( <NUM_LIT> ) , GA -> getOffset ( ) , OperandFlags ) ; unsigned CallType = LocalDynamic ? <STR_LIT> : <STR_LIT> ; if ( Opcode != <STR_LIT> ) CallType = Opcode ; if ( InFlag ) { SDValue Ops [ ] = { Chain , TGA , * InFlag } ; Chain = DAG . getNode ( CallType , dl , NodeTys , Ops ) ; } else { SDValue Ops [ ] = { Chain , TGA } ; Chain = DAG . getNode ( CallType , dl , NodeTys , Ops ) ; } MFI -> setAdjustsStack ( true ) ; SDValue Flag = Chain . getValue ( <NUM_LIT> ) ; return DAG . getCopyFromReg ( Chain , dl , ReturnReg ,


<s> <ISA_LIT>MachineFunctionInfo * FuncInfo = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; int ReturnAddrIndex = FuncInfo -> getRAIndex ( ) ; if ( ReturnAddrIndex == <NUM_LIT> ) { uint64_t SlotSize = TD -> getPointerSize (


<s> for ( i = <NUM_LIT> ; i < count - <NUM_LIT> ; i ++ ) XVECEXP ( vector , <NUM_LIT> , i + <NUM_LIT> ) = gen_rtx_SET ( VOIDmode , gen_rtx_MEM ( SImode , gen_rtx_MINUS (

SImode , stack_pointer_rtx , GEN_INT ( ( i + <NUM_LIT> ) * UNITS_PER_WORD ) ) ) , gen_rtx_REG ( SImode , high - i ) ) ;


<s> MCOperand ATReg = MCOperand :: CreateReg ( <STR_LIT> ) ; BaseReg = ATReg ; MCInsts . resize ( <NUM_LIT> ) ; CreateMCInst ( MCInsts [ <NUM_LIT> ] , <STR_LIT> , ATReg , ZEROReg , MCOperand :: CreateImm ( Hi ) ) ; CreateMCInst ( MCInsts [ <NUM_LIT> ] , <STR_LIT> , ATReg , ATReg , SPReg ) ; } MCInst St


<s> case <STR_LIT> : { Info . opc = <STR_LIT> ; uint64_t NumElts = getDataLayout ( ) -> getTypeAllocSize ( I . getType ( ) ) / <NUM_LIT> ; Info . memVT = EVT :: getVectorVT ( I . getType ( ) -> getContext ( ) , <STR_LIT> , NumElts ) ; Info . ptrVal = I . getArgOperand ( I . getNumArgOperands ( ) - <NUM_LIT> ) ; Info . offset = <NUM_LIT> ; Info . align = <NUM_LIT> ; Info . vol = false ; Info . readMem = true ; Info . writeMem = false ; return true ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { Info . opc = <STR_LIT> ; unsigned NumElts = <NUM_LIT> ; for ( unsigned ArgI = <NUM_LIT> , ArgE = I . getNumArgOperands ( ) ; ArgI < ArgE ; ++ ArgI ) { Type * ArgTy = I . getArgOperand ( ArgI ) -> getType ( ) ; if ( ! ArgTy -> isVectorTy ( ) ) break ; NumElts += getDataLayout ( ) -> getTypeAllocSize ( ArgTy ) / <NUM_LIT> ; } Info . memVT = EVT :: getVectorVT ( I . getType ( ) -> getContext ( ) , <STR_LIT> , NumElts ) ; Info . ptrVal = I . getArgOperand ( I . getNumArgOperands ( ) - <NUM_LIT> ) ; Info . offset = <NUM_LIT> ; Info . align = <NUM_LIT> ; Info . vol = false ; Info . readMem = false ; Info . writeMem = true ; return true ; } case <STR_LIT> : case <STR_LIT> : { PointerType * PtrTy = cast < PointerType > ( I . getArgOperand ( <NUM_LIT> ) -> getType ( ) ) ; Info . opc = <STR_LIT> ; Info . memVT = <STR_LIT> ( PtrTy -> getElementType ( ) ) ; Info . ptrVal = I . getArgOperand ( <NUM_LIT> ) ; Info . offset = <NUM_LIT> ; Info . align = getDataLayout ( ) -> getABITypeAlignment ( PtrTy -> getElementType ( ) ) ; Info . vol = true ; Info . readMem = true ; Info . writeMem = false ; return true ; } case <STR_LIT> : case <STR_LIT> : { PointerType * PtrTy = cast < PointerType > ( I . getArgOperand ( <NUM_LIT> ) -> getType ( ) ) ; Info . opc = <STR_LIT> ; Info . memVT = <STR_LIT> ( PtrTy -> getElementType (


<s> BuildMI ( LoopMBB , DL , TII -> get ( getLRForRMW ( Ordering , Width ) ) , DestReg ) . addReg ( AddrReg ) ; switch ( BinOp ) { default : llvm_unreachable ( <STR_LIT> ) ; case AtomicRMWInst :: Nand : BuildMI ( LoopMBB , DL , TII -> get ( <STR_LIT> ) , ScratchReg ) . addReg ( DestReg ) . addReg ( IncrReg ) ; BuildMI ( LoopMBB , DL , TII -> get ( <STR_LIT> ) , ScratchReg ) . addReg

( ScratchReg ) . addImm ( - <NUM_LIT> ) ;


<s> machine_mode elt_mode ; int n_elts ; rs6000_discover_homogeneous_aggregate ( mode , type , & elt_mode , & n_elts ) ; if ( DEFAULT_ABI == ABI_V4 && ( GET_MODE_SIZE ( mode ) == <NUM_LIT> || ( TARGET_HARD_FLOAT && ! is_complex_IBM_long_double ( mode ) && FLOAT128_2REG_P ( mode ) ) ) ) return <NUM_LIT> ; else if ( FLOAT128_VECTOR_P ( mode ) ) return <NUM_LIT> ; else if ( PAIRED_VECTOR_MODE ( mode ) || ( type && TREE_CODE ( type ) == VECTOR_TYPE && int_size_in_bytes ( type ) >= <NUM_LIT> && int_size_in_bytes ( type ) < <NUM_LIT>


<s> if ( Sym . getSection ( ) . getKind ( ) . isMergeableCString ( ) || Sym . getSection ( )

. getKind ( ) . isMergeableConst ( ) ) return & Sym ;


<s> LivePhysRegs LPR ( HRI ) ; LPR . addLiveIns ( B ) ; SmallVector < std :: pair < unsigned , const MachineOperand * > , <NUM_LIT> > Clobbers ; for ( auto R = B . begin ( ) ; R != It ; ++ R ) { Clobbers . clear ( ) ; LPR . stepForward ( * R , Clobbers ) ; for ( auto & C : Clobbers ) if ( C . second -> isReg ( ) && C . second -> isDead ( ) ) LPR . removeReg ( C . first ) ; } DebugLoc DL = MI -> getDebugLoc ( ) ; unsigned SrcR = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned SrcLo = HRI . getSubReg ( SrcR , <STR_LIT> ) ; unsigned SrcHi = HRI . getSubReg ( SrcR , <STR_LIT> ) ; bool IsKill = MI -> getOperand ( <NUM_LIT> ) . isKill ( ) ; int FI = MI -> getOperand ( <NUM_LIT> ) . getIndex


<s> else if ( ! ( Val & <NUM_LIT> ) ) imm *= - <NUM_LIT> ; if ( imm != INT32_MIN ) imm *= ( <NUM_LIT> << shift ) ; Inst . addOperand ( MCOperand :: createImm ( imm ) ) ; return MCDisassembler :: Success


<s> bool sh_cfun_trap_exit_p ( void ) { return ( lookup_attribute ( <STR_LIT> , DECL_ATTRIBUTES ( current_function_decl )


<s> BitVector Reserved ( getNumRegs ( ) ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set (


<s> if ( MI . getOpcode ( ) == <STR_LIT> ) { static const unsigned OpTable [ <NUM_LIT> ] [ <NUM_LIT> ] = { { <STR_LIT> :: src0_X , <STR_LIT> :: src0_sel_X } , { <STR_LIT> :: src0_Y , <STR_LIT> :: src0_sel_Y } , { <STR_LIT> :: src0_Z , <STR_LIT> :: src0_sel_Z } , { <STR_LIT> :: src0_W , <STR_LIT> :: src0_sel_W } , { <STR_LIT> :: src1_X , <STR_LIT> :: src1_sel_X } , { <STR_LIT> :: src1_Y , <STR_LIT> :: src1_sel_Y } , { <STR_LIT> :: src1_Z , <STR_LIT> :: src1_sel_Z } , { <STR_LIT> :: src1_W , <STR_LIT> :: src1_sel_W } , } ; for ( unsigned j = <NUM_LIT> ; j < <NUM_LIT> ; j ++ ) { MachineOperand & MO = MI . getOperand ( getOperandIdx ( MI . getOpcode ( ) , OpTable [ j ] [ <NUM_LIT> ] ) ) ; unsigned Reg = MO . getReg ( ) ; if ( Reg == <STR_LIT> ) { MachineOperand & Sel = MI . getOperand ( getOperandIdx ( MI . getOpcode ( ) , OpTable [ j ] [ <NUM_LIT> ] ) ) ; Result . push_back ( std :: make_pair ( & MO , Sel . getImm ( ) ) ) ; continue ; } } return Result ; } static const unsigned OpTable [ <NUM_LIT> ] [ <NUM_LIT> ] = { { <STR_LIT> :: src0 , <STR_LIT> :: src0_sel } , { <STR_LIT> :: src1 , <STR_LIT> :: src1_sel } , { <STR_LIT> :: src2 , <STR_LIT> :: src2_sel } , } ; for ( unsigned j = <NUM_LIT> ; j < <NUM_LIT> ; j ++ ) { int SrcIdx = getOperandIdx ( MI . getOpcode ( ) , OpTable [ j ] [ <NUM_LIT> ] ) ; if ( SrcIdx < <NUM_LIT> ) break ; MachineOperand & MO = MI . getOperand ( SrcIdx ) ; unsigned Reg = MO . getReg ( ) ; if ( Reg ==


<s> void <ISA_LIT>PassConfig :: addIRPasses ( ) { TargetPassConfig :: addIRPasses ( ) ; addPass ( createAtomicExpandPass ( & get<ISA_LIT>TargetMachine (


<s> return DAG . getNode ( <STR_LIT> , dl , PtrVT , Hi , Lo ) ; } if ( TM . getRelocationModel ( ) == Reloc :: PIC_ ) { Hi = DAG . getNode ( <STR_LIT> , dl , PtrVT , DAG . getNode ( <STR_LIT> , DebugLoc ( ) , PtrVT ) , Hi ) ; } Lo = DAG . getNode ( <STR_LIT> , dl , PtrVT , Hi


<s> static DecodeStatus DecodeShiftRightImm8 ( MCInst & Inst , unsigned Val , uint64_t Address , const void * Decoder ) { Inst . addOperand ( MCOperand :: CreateImm ( <NUM_LIT> - Val ) ) ; return MCDisassembler


<s> void LLVMInitialize<ISA_LIT>Target ( ) { RegisterTargetMachine < <ISA_LIT>TargetMachine > X ( getThe<ISA_LIT>Target ( ) ) ; PassRegistry & PR = * PassRegistry


<s> int64_t VTYPEImm = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( PrevVTYPEImm != VTYPEImm ) return false ; if ( MI . getOpcode ( ) == <STR_LIT> ) { if ( PrevVSETVLI -> getOpcode ( ) != <STR_LIT> ) return false ; return PrevVSETVLI -> getOperand ( <NUM_LIT> ) . getImm ( ) == MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; } assert ( MI . getOpcode ( ) == <STR_LIT> ) ; Register AVLReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register PrevOutVL = PrevVSETVLI -> getOperand (


<s> FirstNonZeroIdx = i ; } } assert ( FirstNonZero . getNode ( ) && <STR_LIT> ) ; SDValue V1 = FirstNonZero . getOperand ( <NUM_LIT> ) ; MVT VT = V1 . getSimpleValueType ( ) ; SDValue Elt ; unsigned EltMaskIdx , EltIdx ; int Mask [ <NUM_LIT> ] ; for ( EltIdx = <NUM_LIT> ; EltIdx < <NUM_LIT> ; ++ EltIdx ) { if ( Zeroable [ EltIdx ] ) { Mask [ EltIdx ] = EltIdx + <NUM_LIT> ; continue ; } Elt = Op -> getOperand ( EltIdx ) ; EltMaskIdx = cast < ConstantSDNode > ( Elt . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; if ( Elt . getOperand ( <NUM_LIT> ) != V1 || EltMaskIdx != EltIdx ) break ; Mask [ EltIdx ] = EltIdx ; } if ( EltIdx == <NUM_LIT> ) { SDValue VZero = getZeroVector ( VT , Subtarget , DAG , SDLoc ( Op ) ) ; if ( V1 . getSimpleValueType ( ) != VT ) V1 = DAG . getNode ( <STR_LIT> , SDLoc ( V1 ) , VT , V1 ) ; return DAG . getVectorShuffle ( VT , SDLoc ( V1 ) , V1 , VZero , & Mask [ <NUM_LIT> ] ) ; } if ( ! Subtarget . hasSSE41 ( ) ) return SDValue ( ) ; SDValue V2 = Elt . getOperand ( <NUM_LIT> ) ; if ( Elt == FirstNonZero && EltIdx == FirstNonZeroIdx ) V1 = SDValue ( ) ; bool CanFold = true ; for ( unsigned i = EltIdx + <NUM_LIT> ; i < <NUM_LIT> && CanFold ; ++ i ) { if ( Zeroable [ i ] ) continue ; SDValue Current = Op -> getOperand ( i ) ; SDValue SrcVector = Current -> getOperand ( <NUM_LIT> ) ; if ( ! V1 . getNode ( ) ) V1 = SrcVector ; CanFold = SrcVector == V1 && cast < ConstantSDNode > ( Current . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) == i ; } if ( ! CanFold ) return SDValue ( ) ; assert ( V1 . getNode ( ) && <STR_LIT> ) ; if ( V1 . getSimpleValueType ( ) != <STR_LIT> ) V1 = DAG . getNode ( <STR_LIT> , SDLoc ( V1 ) , <STR_LIT> , V1 ) ; if ( V2 . getSimpleValueType ( ) != <STR_LIT> ) V2 = DAG . getNode ( <STR_LIT> , SDLoc ( V2 ) , <STR_LIT> , V2 ) ; unsigned ZMask = Zeroable . to_ulong ( ) ; unsigned InsertPSMask = EltMaskIdx << <NUM_LIT> | EltIdx << <NUM_LIT> |


<s> static const MCSymbol * GetLazyPtr ( const MCSymbol * Sym , MCContext & Ctx ) { SmallString < <NUM_LIT> > TmpStr ( Sym -> getName ( ) . begin ( ) , Sym -> getName ( ) . end ( ) - <NUM_LIT> ) ; TmpStr += <STR_LIT> ; return Ctx . GetOrCreateSymbol ( TmpStr . str ( )


<s> OW -> WriteZeros ( Count % <NUM_LIT> ) ; Count /= <NUM_LIT> ; for ( uint64_t i = <NUM_LIT> ; i != Count ; ++ i ) OW -> write32


<s> PI != E ; ++ PI ) { if ( ( * PI ) != EndMBB ) { Succs . insert ( std :: pair < MachineBasicBlock * , MachineBasicBlock * > ( * PI , StartMBB ) ) ; } } for ( auto <ISA_LIT> : Succs ) { std :: pair < MachineBasicBlock * , MachineBasicBlock * > Edge = <ISA_LIT> ; DEBUG ( dbgs ( ) << <STR_LIT> << printMBBReference ( * Edge . first ) << <STR_LIT> << printMBBReference ( * Edge .


<s> SDValue <ISA_LIT>SETargetLowering :: PerformDAGCombine ( SDNode * N , DAGCombinerInfo & DCI ) const { SelectionDAG & DAG = DCI . DAG ; SDValue Val ; switch ( N -> getOpcode ( ) ) { case <STR_LIT> : Val = performANDCombine ( N , DAG , DCI , Subtarget ) ; break ; case <STR_LIT> : Val = performORCombine ( N , DAG , DCI , Subtarget ) ; break ; case <STR_LIT> : return performMULCombine ( N , DAG , DCI , this , Subtarget ) ; case <STR_LIT> : Val = performSHLCombine ( N , DAG , DCI , Subtarget ) ; break ; case <STR_LIT> : return performSRACombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return performSRLCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return performVSELECTCombine ( N , DAG ) ; case <STR_LIT> : Val = performXORCombine ( N , DAG , Subtarget ) ; break ; case <STR_LIT> : Val = performSETCCCombine ( N , DAG ) ; break ; } if ( Val . getNode ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; N -> printrWithDepth ( dbgs ( ) , & DAG ) ; dbgs ( ) << <STR_LIT> ; Val . getNode ( ) -> printrWithDepth ( dbgs ( ) , & DAG ) ; dbgs ( ) << <STR_LIT> ) ; return Val


<s> unsigned Binary = CTX . getRegisterInfo ( ) -> getEncodingValue ( MO . getReg ( ) ) ; unsigned SBits = <NUM_LIT> ; switch ( SOpc ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : SBits = <NUM_LIT> ; break ; case <STR_LIT> : SBits = <NUM_LIT> ; break ; case <STR_LIT> : SBits = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : SBits = <NUM_LIT> ; break ; } Binary |= SBits <<


<s> Mask . resize ( NumElts , SM_SentinelUndef ) ; for ( int i = <NUM_LIT> ; i != ( int ) NumElts ; ++ i ) { Mask [ i ] = i ; if ( UndefElts [ i ] || ( ! IsBLENDV && EltBits [ i ] . isZero ( ) ) || ( IsBLENDV && EltBits [ i ] . isNonNegative ( )


<s> static DecodeStatus decodeCondBrTarget ( MCInst & Inst , unsigned


<s> unsigned Size = getInstSizeInBytes ( MI ) ; if ( Subtarget . isThumb2 ( )


<s> SmallString < <NUM_LIT> > Name ; StringRef Prefix = <STR_LIT> ; Name += Prefix ; Name += I . first . first -> getName ( ) ; MCSymbol * S = OutContext . getOrCreateSymbol ( Name ) ; TCEntry = cast < MCSectionXCOFF > ( getObjFileLowering ( ) . getSectionForTOCEntry ( S , TM ) ) ; } else { TCEntry = cast < MCSectionXCOFF > ( getObjFileLowering ( ) . getSectionForTOCEntry ( I . first . first , TM ) ) ; } OutStreamer -> SwitchSection ( TCEntry ) ; OutStreamer -> emitLabel ( I . second ) ; if ( TS != nullptr ) TS -> emitTCEntry ( * I . first . first , I . first . second ) ; } for ( const auto * GV : TOCDataGlobalVars )


<s> uint32_t getSymbolicOperandMinVersion ( :: OperandCategory :: OperandCategory Category , uint32_t


<s> const <ISA_LIT>16InstrInfo & TII = * static_cast < const <ISA_LIT>16InstrInfo * > ( MF . getSubtarget ( ) . getInstrInfo ( ) ) ; DebugLoc dl = MBBI -> getDebugLoc ( ) ; uint64_t StackSize = MFI ->


<s> imm |= fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ; imm |= cmode << <NUM_LIT> ; imm |= fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ; if ( cmode == <NUM_LIT> && Inst . getOpcode ( ) == <STR_LIT> ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeMQPRRegisterClass ( Inst , Qd , Address , Decoder ) ) )


<s> MachineInstr * MI = Root . getParent ( ) ; MachineBasicBlock * MBB = MI -> getParent ( ) ; MachineRegisterInfo & MRI = MBB -> getParent ( ) -> getRegInfo ( ) ; InstructionSelector :: ComplexRendererFns Default = { { [ = ] ( MachineInstrBuilder & MIB ) { MIB . addReg ( Root . getReg ( ) ) ; } , [ = ] ( MachineInstrBuilder & MIB ) { MIB . addImm ( <NUM_LIT> ) ; } , [ = ] ( MachineInstrBuilder & MIB ) { MIB . addImm ( <NUM_LIT> ) ; } } } ; if ( ! STI . hasFlatInstOffsets ( ) ) return Default ; const MachineInstr * OpDef = MRI . getVRegDef ( Root . getReg ( ) ) ; if ( ! OpDef || OpDef -> getOpcode ( ) != <STR_LIT> ) return Default ; Optional < int64_t > Offset = getConstantVRegVal ( OpDef -> getOperand ( <NUM_LIT> ) . getReg ( ) , MRI ) ; if ( ! Offset . hasValue ( ) ) return Default ; unsigned AddrSpace = ( * MI -> memoperands_begin ( ) )


<s> return makeArrayRef ( MDs ) . slice ( NumModuleMDs


<s> assert ( ! AFI -> isThumb1OnlyFunction ( ) && <STR_LIT> ) ; if ( ! AFI -> isThumbFunction ( ) ) { if ( CanUseBFC ) { AddDefaultPred ( BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) , Reg ) . addReg ( Reg , RegState :: Kill ) . addImm ( ~ AlignMask ) ) ; } else if ( AlignMask <= <NUM_LIT> ) { AddDefaultCC ( AddDefaultPred ( BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) , Reg ) . addReg ( Reg , RegState :: Kill ) . addImm ( AlignMask ) ) ) ; } else { assert ( ! MustBeSingleInstruction && <STR_LIT> <STR_LIT> <STR_LIT> ) ; AddDefaultCC ( AddDefaultPred ( BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) , Reg ) . addReg ( Reg , RegState :: Kill ) . addImm ( <STR_LIT> ( <STR_LIT> , NrBitsToZero ) ) ) ) ; AddDefaultCC ( AddDefaultPred ( BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) , Reg ) . addReg ( Reg , RegState :: Kill ) . addImm ( <STR_LIT> ( <STR_LIT> , NrBitsToZero ) ) ) ) ; } } else


<s> } ; if ( ! Op . hasOneUse ( ) ) return <NUM_LIT> ; if ( isSupportedExtend ( Op ) ) return <NUM_LIT> ; unsigned Opc = Op . getOpcode ( ) ; if ( Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ) if ( ConstantSDNode * ShiftCst = dyn_cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) ) { uint64_t Shift = ShiftCst -> getZExtValue ( ) ; if ( isSupportedExtend ( Op . getOperand ( <NUM_LIT> ) ) ) return ( Shift <= <NUM_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; EVT VT = Op . getValueType ( ) ; if ( ( VT == <STR_LIT> && Shift <= <NUM_LIT> ) || ( VT == <STR_LIT> && Shift <= <NUM_LIT> ) ) return <NUM_LIT> ; } return


<s> unsigned DestReg = createResultReg ( RC ) ; CodeModel :: Model CModel = TM . getCodeModel ( ) ; const GlobalVariable * GVar = dyn_cast < GlobalVariable > ( GV ) ; if ( GV -> isThreadLocal ( ) ) return <NUM_LIT> ; if ( CModel == CodeModel :: Small || CModel == CodeModel :: JITDefault ) BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , DestReg ) . addGlobalAddress ( GV ) . addReg ( <STR_LIT> ) ; else { unsigned HighPartReg = createResultReg ( RC ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , HighPartReg )

. addReg ( <STR_LIT> ) . addGlobalAddress ( GV ) ;


<s> LoadSDNode * InputLoad = dyn_cast < LoadSDNode > ( Input ) ; if ( InputLoad && InputLoad -> getExtensionType ( ) == <STR_LIT> ) return Input ; ConstantSDNode * InputConst = dyn_cast < ConstantSDNode > ( Input ) ; if ( InputConst || Opc == <STR_LIT> || Opc == <STR_LIT> ||


<s> uint64_t <ISA_LIT>GOTPLT :: emit ( MemoryRegion & pRegion ) { uint32_t * buffer = reinterpret_cast < uint32_t * > ( pRegion . begin ( ) ) ; uint64_t result = <NUM_LIT> ; for ( iterator it = begin ( ) , ie = end ( ) ; it != ie ; ++ it , ++ buffer ) { GOTPLTEntry * got = & ( llvm :: cast < GOTPLTEntry > ( ( * it ) ) ) ; * buffer = static_cast < uint32_t > ( got -> getValue ( ) ) ; result += got -> size ( )


<s> unsigned NumElements = MemVT . getVectorNumElements ( ) ; if ( AS == <ISA_LIT>AS :: CONSTANT_ADDRESS || AS == <ISA_LIT>AS :: CONSTANT_ADDRESS_32BIT ) { if ( ! Op -> isDivergent ( ) && Alignment >= <NUM_LIT> && NumElements < <NUM_LIT> ) { if ( MemVT . isPow2VectorType ( ) ) return SDValue ( ) ; if ( NumElements == <NUM_LIT> ) return WidenVectorLoad ( Op , DAG ) ; return SplitVectorLoad ( Op , DAG ) ; } } if ( AS == <ISA_LIT>AS :: CONSTANT_ADDRESS || AS == <ISA_LIT>AS :: CONSTANT_ADDRESS_32BIT || AS == <ISA_LIT>AS :: GLOBAL_ADDRESS ) { if ( Subtarget -> getScalarizeGlobalBehavior ( ) && ! Op -> isDivergent ( ) && ! Load -> isVolatile ( ) && isMemOpHasNoClobberedMemOperand ( Load ) && Alignment >= <NUM_LIT> && NumElements < <NUM_LIT> ) { if ( MemVT . isPow2VectorType ( ) ) return SDValue ( ) ; if ( NumElements == <NUM_LIT> ) return WidenVectorLoad ( Op , DAG ) ; return SplitVectorLoad ( Op , DAG ) ; } } if ( AS == <ISA_LIT>AS :: CONSTANT_ADDRESS || AS == <ISA_LIT>AS :: CONSTANT_ADDRESS_32BIT || AS == <ISA_LIT>AS :: GLOBAL_ADDRESS || AS == <ISA_LIT>AS :: FLAT_ADDRESS ) { if ( NumElements > <NUM_LIT> ) return SplitVectorLoad ( Op , DAG ) ; if ( NumElements == <NUM_LIT> && ! Subtarget -> hasDwordx3LoadStores ( ) ) return WidenVectorLoad ( Op , DAG ) ; return SDValue ( ) ; } if ( AS == <ISA_LIT>AS :: PRIVATE_ADDRESS ) { switch ( Subtarget -> getMaxPrivateElementSize ( ) ) { case <NUM_LIT> : return scalarizeVectorLoad ( Load , DAG ) ; case <NUM_LIT> : if ( NumElements > <NUM_LIT> ) return SplitVectorLoad ( Op , DAG ) ; return SDValue ( ) ; case <NUM_LIT> : if ( NumElements > <NUM_LIT> ) return SplitVectorLoad ( Op , DAG ) ; if ( NumElements == <NUM_LIT> && ! Subtarget -> hasDwordx3LoadStores ( ) ) return WidenVectorLoad ( Op , DAG ) ; return SDValue ( ) ; default : llvm_unreachable ( <STR_LIT> ) ; } } else if ( AS == <ISA_LIT>AS :: LOCAL_ADDRESS || AS == <ISA_LIT>AS


<s> if ( ! TARGET_64BIT ) return <NUM_LIT> ; for ( i = <NUM_LIT> ; i <= <NUM_LIT> ; i ++ ) { if ( regs_ever_live [ i ] == <NUM_LIT> ) return <NUM_LIT> ; } return <NUM_LIT>


<s> bool Changed = false ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << FixupLocsForFn . size ( ) << <STR_LIT> ) ; for ( AESFixupLocation & FixupLoc : FixupLocsForFn ) { insertAESFixup ( FixupLoc , TII , TRI ) ; Changed |= true ; } return


<s> base = get_formal_tmp_var ( base_field , pre_p ) ; t = fold_convert ( build_nonstandard_integer_type ( <NUM_LIT> , <NUM_LIT> ) , offset_field ) ; offset = get_initialized_tmp_var ( t , pre_p , NULL ) ; indirect = pass_by_reference ( NULL , TYPE_MODE ( type ) , type , false ) ; if ( indirect ) type = build_pointer_type_for_mode ( type , ptr_mode , true ) ; r = alpha_gimplify_va_arg_1 ( type , base ,


<s> bool isSramEccOnOrAny ( ) const { return SramEccSetting == TargetIDSetting :: On || SramEccSetting ==


<s> inline vector signed short vec_vcmpequh ( vector unsigned short a1 , vector


<s> break ; case <STR_LIT> : adjust :: ldi :: lo8 ( Size , Fixup , Value , Ctx ) ; break ; case <STR_LIT> : case <STR_LIT> : adjust :: pm ( Value ) ; adjust :: ldi :: lo8 ( Size , Fixup , Value , Ctx ) ; break ; case <STR_LIT> : adjust :: ldi :: hi8 ( Size , Fixup , Value , Ctx ) ; break ; case <STR_LIT> : case <STR_LIT> : adjust :: pm ( Value ) ; adjust :: ldi :: hi8 ( Size , Fixup , Value , Ctx ) ; break ; case <STR_LIT> : case <STR_LIT> : if ( Kind == <STR_LIT> ) adjust :: pm ( Value ) ; adjust :: ldi :: hh8 ( Size , Fixup , Value , Ctx ) ; break ; case <STR_LIT> : adjust :: ldi :: ms8 ( Size , Fixup , Value , Ctx ) ; break ; case <STR_LIT> : case <STR_LIT> : if ( Kind == <STR_LIT> ) adjust :: pm ( Value ) ; adjust :: ldi :: neg ( Value ) ; adjust :: ldi :: lo8 ( Size , Fixup , Value , Ctx ) ; break ; case <STR_LIT> : case <STR_LIT> : if ( Kind == <STR_LIT> ) adjust :: pm ( Value ) ; adjust :: ldi :: neg ( Value ) ; adjust :: ldi :: hi8 ( Size , Fixup , Value , Ctx ) ; break ; case <STR_LIT> : case <STR_LIT> : if ( Kind == <STR_LIT> ) adjust :: pm ( Value ) ; adjust :: ldi :: neg ( Value ) ; adjust :: ldi :: hh8 ( Size , Fixup , Value , Ctx ) ; break ; case <STR_LIT> : adjust :: ldi :: neg ( Value ) ; adjust :: ldi :: ms8 ( Size , Fixup , Value , Ctx ) ; break ; case <STR_LIT> : adjust :: unsigned_width ( <NUM_LIT> , Value , std :: string ( <STR_LIT> ) , Fixup , Ctx ) ; Value &= <NUM_LIT> ; break ; case <STR_LIT> : Value >>= <NUM_LIT> ; adjust :: unsigned_width ( <NUM_LIT> , Value , std :: string ( <STR_LIT> ) , Fixup , Ctx ) ; Value &= <NUM_LIT> ; break ; case <STR_LIT> : adjust :: fixup_6 ( Fixup , Value , Ctx ) ; break ; case


<s> } if ( VT . isInteger ( ) && VT . getSizeInBits ( ) >= <NUM_LIT> ) { switch ( ISD ) { default : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; } } if ( ! VT . isFloatingPoint ( ) ) return false ; if ( TLI -> useSoftFloat ( ) ) { switch ( I . getOpcode ( ) ) { default : return true ; case Instruction :: Alloca : case Instruction :: Load : case Instruction :: Store : case Instruction :: Select : case Instruction :: PHI : return false ; } } if ( I . getType ( ) -> isDoubleTy ( ) && ! ST


<s> return DAG . getNode ( <STR_LIT> , DL , DAG . getVTList ( VT , <STR_LIT> ) , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) , DAG .

getConstant ( <NUM_LIT> , DL , <STR_LIT> ) , Flags ) ;


<s> if ( ( N . getOpcode ( ) != <STR_LIT> && N . getOpcode ( ) != <STR_LIT> && N . getOpcode ( ) != <STR_LIT> ) || ! isa < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) ) ) return false ; int64_t SplatImm = cast < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) ) -> getSExtValue ( ) ; if ( ! isUInt < <NUM_LIT> > (


<s> mem = gen_frame_mem ( mode , plus_constant ( Pmode , stack_pointer_rtx , offset


<s> switch ( Val ) { case <NUM_LIT> : return createRegOperand ( FLAT_SCR_LO ) ; case <NUM_LIT> : return createRegOperand ( FLAT_SCR_HI ) ; case <NUM_LIT> : case <NUM_LIT> : break ; case <NUM_LIT> : return createRegOperand ( VCC_LO ) ; case <NUM_LIT> : return createRegOperand ( VCC_HI ) ; case <NUM_LIT> : assert ( ! isGFX9 ( ) ) ; return createRegOperand ( TBA_LO ) ; case <NUM_LIT> : assert ( ! isGFX9 ( ) ) ; return


<s> while ( I != MBB . begin ( ) ) { -- I ; if ( I -> isDebugValue ( ) ) continue ; if ( I -> getOpcode ( ) != <STR_LIT> && I -> getOpcode ( ) != <STR_LIT> && I -> getOpcode ( ) != <STR_LIT> && I -> getOpcode ( ) != <STR_LIT> ) break ; I -> eraseFromParent ( ) ; I = MBB . end ( ) ; ++ Count ; } return


<s> const int NumOps = MI . getNumOperands ( ) ; SmallVector < const ValueMapping * , <NUM_LIT> > OpdsMapping ( NumOps ) ; for ( int I = <NUM_LIT> ; I != NumOps ; ++ I ) { if ( ! MI . getOperand ( I ) . isReg ( ) ) continue ; Register OpReg = MI . getOperand ( I