<s> void <ISA_LIT>FrameLowering :: emitEpilogue ( MachineFunction & MF , MachineBasicBlock & MBB ) const { MachineBasicBlock :: iterator MBBI = std :: prev ( MBB . end ( ) ) ; DebugLoc dl = MBBI -> getDebugLoc ( ) ; if ( hasFP ( MF ) || MF . getTarget ( ) . getOptLevel ( ) == CodeGenOpt :: None ) { MachineBasicBlock :: iterator MBBI = std :: prev ( MBB . end ( ) ) ; MachineBasicBlock :: iterator MBBI_end = MBB . end ( ) ; const TargetInstrInfo & TII = * MF . getSubtarget ( ) . getInstrInfo ( ) ; if ( MBBI -> getOpcode ( ) == <STR_LIT> ) { assert ( MBBI -> getOperand ( <NUM_LIT> ) . isReg ( ) && <STR_LIT> ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT>


<s> static bool isCondBranchOpcode ( int Opc ) { return Opc == <STR_LIT> || Opc


<s> for ( int i = LAST_VIRTUAL_REGISTER + <NUM_LIT> ; i < max_regs ; i ++ ) if ( REG_N_SETS ( i ) == <NUM_LIT> && REG_N_REFS ( i ) == <NUM_LIT> ) regno_reg_rtx [ i ] = const0_rtx ; tree attr = get_oacc_fn_attrib ( current_function_decl ) ; if ( attr ) { unsigned mask = <NUM_LIT> ; tree dims = TREE_VALUE ( attr ) ; unsigned ix ; for ( ix = <NUM_LIT> ; ix != GOMP_DIM_MAX ; ix ++ , dims = TREE_CHAIN ( dims ) ) { int size = TREE_INT_CST_LOW ( TREE_VALUE ( dims ) ) ; tree allowed = TREE_PURPOSE ( dims ) ; if ( size != <NUM_LIT> && ! ( allowed && integer_zerop ( allowed ) ) ) mask |= GOMP_DIM_MASK ( ix ) ; } gcc_assert ( ! ( mask & GOMP_DIM_MASK ( GOMP_DIM_WORKER ) ) || ( mask & GOMP_DIM_MASK ( GOMP_DIM_VECTOR ) ) ) ; parallel * pars = nvptx_discover_pars ( & bb_insn_map ) ; nvptx_process_pars ( pars ) ; nvptx_neuter_pars ( pars , mask , <NUM_LIT> ) ; delete pars ; } nvptx_reorg_subreg ( ) ; regstat_free_n_sets_and_refs (


<s> MachineMemOperand * MMO = FuncInfo . MF -> getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( FI , Offset ) , Flags , MFI . getObjectSize ( FI ) , MFI . getObjectAlignment ( FI ) ) ; MIB . addFrameIndex ( FI ) ; if ( useAM3 ) { signed Imm = ( Addr . Offset < <NUM_LIT> ) ? ( <NUM_LIT> | - Addr . Offset ) : Addr . Offset ; MIB . addReg ( <NUM_LIT> ) ; MIB . addImm ( Imm ) ; } else { MIB . addImm ( Addr . Offset ) ; } MIB . addMemOperand ( MMO )


<s> static DecodeStatus decodeS8ImmOperand ( MCInst & Inst , uint64_t Imm , uint64_t Address , const void * Decoder ) { return decodeSImmOperand < <NUM_LIT> > ( Inst , Imm


<s> SmallVector < MachineInstr * , <NUM_LIT> > DeadCopies ; for ( MachineBasicBlock & MBB : * MF ) { for ( MachineInstr & MI : MBB ) { if ( MI . getOpcode ( ) != <STR_LIT> ) continue ; unsigned DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( ! TargetRegisterInfo :: isVirtualRegister ( SrcReg ) || MRI -> getRegClass ( SrcReg ) != & <STR_LIT> ) continue ; if ( isLaneMaskReg ( DstReg ) || ( TargetRegisterInfo :: isVirtualRegister ( DstReg ) && MRI -> getRegClass ( DstReg ) == & <STR_LIT> ) ) continue ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << MI ) ; DebugLoc DL = MI . getDebugLoc ( ) ; assert ( TII -> getRegisterInfo ( ) . getRegSizeInBits ( DstReg , * MRI ) == <NUM_LIT> ) ; assert ( ! MI . getOperand ( <NUM_LIT> ) . getSubReg ( ) ) ; ConstrainRegs . insert ( SrcReg ) ; BuildMI ( MBB , MI , DL , TII -> get ( <STR_LIT> ) , DstReg ) . addImm ( <NUM_LIT> ) . addImm ( - <NUM_LIT> ) . addReg ( SrcReg ) ; DeadCopies . push_back ( & MI ) ; } for ( MachineInstr * MI : DeadCopies ) MI -> eraseFromParent ( ) ; DeadCopies . clear


<s> TSTInst . setOpcode ( <STR_LIT> ) ; TSTInst . addOperand ( MCOperand :: CreateReg ( Reg ) ) ; if ( FlagSfiZeroMask ) { TSTInst . addOperand ( MCOperand :: CreateImm ( <NUM_LIT> ) ) ; } else { TSTInst . addOperand ( MCOperand :: CreateImm (


<s> yaml :: MachineFunctionInfo * <ISA_LIT>TargetMachine :: createDefaultFuncInfoYAML ( ) const { return new yaml ::


<s> if ( ( Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ) && MI . getOperand ( <NUM_LIT> ) . getImm ( ) <= MI . getOperand ( <NUM_LIT> ) . getImm ( ) ) return true ; if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ) return true ; return


<s> if ( op_false == CONST0_RTX ( mode ) || op_true == CONST0_RTX ( mode ) || ( INTEGRAL_MODE_P ( mode ) && ( op_true == CONSTM1_RTX ( mode ) || op_false == CONSTM1_RTX ( mode ) ) ) ) return false ; return true


<s> Inst . addOperand ( MCOperand :: CreateImm ( CE -> getValue ( )


<s> mem = gen_frame_mem ( SImode , plus_constant ( Pmode , stack_pointer_rtx , offset ) ) ; reg = gen_rtx_REG ( SImode , regno ) ; if ( restore_p ) { mips_add_cfa_restore ( reg ) ; return gen_rtx_SET ( VOIDmode , reg , mem ) ; } if ( reg_parm_p ) return gen_rtx_SET ( VOIDmode , mem ,


<s> unsigned getInlineAsmMemConstraint ( const std :: string & ConstraintCode ) const override { return InlineAsm


<s> if ( RegNo % <NUM_LIT> ) return MCDisassembler :: Fail ; const <ISA_LIT>Disassembler * Dis = static_cast < const <ISA_LIT>Disassembler * > ( Decoder ) ; const MCRegisterInfo * RI = Dis -> getContext ( ) . getRegisterInfo ( ) ; MCRegister Reg = RI -> getMatchingSuperReg ( <STR_LIT> + RegNo , <STR_LIT> , & <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] ) ; Inst . addOperand ( MCOperand :: createReg ( Reg ) ) ; return MCDisassembler ::


<s> switch ( mode ) { case QImode : case HImode : case SImode : case DImode : case TImode : return


<s> unsigned <ISA_LIT>SEInstrInfo :: isStoreToStackSlot ( const MachineInstr * MI , int & FrameIndex ) const { unsigned Opc = MI -> getOpcode ( ) ; if ( ( Opc == <STR_LIT> ) || ( Opc == <STR_LIT> ) || ( Opc == <STR_LIT> ) || ( Opc == <STR_LIT> ) || ( Opc == <STR_LIT> ) ) { if ( ( MI -> getOperand ( <NUM_LIT> ) . isFI ( ) ) && ( MI -> getOperand ( <NUM_LIT> ) . isImm ( ) ) && ( isZeroImm ( MI -> getOperand ( <NUM_LIT> ) ) ) ) { FrameIndex = MI -> getOperand ( <NUM_LIT> ) . getIndex ( ) ; return MI -> getOperand ( <NUM_LIT> ) . getReg (


<s> FunctionPass * llvm :: create<ISA_LIT>PreAllocateWWMRegsPass ( ) { return new <ISA_LIT>PreAllocateWWMRegs


<s> if ( Specifier != 's' ) return false ; const PointerType * PT = dyn_cast < PointerType > ( OpType ) ; if ( ! PT || PT -> getAddressSpace ( ) != <ISA_LIT>AS :: CONSTANT_ADDRESS ) return false ; Type * ElemType = PT -> getContainedType


<s> const auto & MLI = getAnalysis < MachineLoopInfo > ( ) ; const auto & WEI = getAnalysis < <ISA_LIT>ExceptionInfo > ( ) ; auto & MDT = getAnalysis < MachineDominatorTree > ( ) ; MF . getRegInfo ( ) . invalidateLiveness ( ) ; SortBlocks ( MF , MLI , WEI , MDT ) ; return true


<s> MCDisassembler :: DecodeStatus <ISA_LIT>Disassembler :: getInstruction ( MCInst & Instr , uint64_t & Size , ArrayRef < uint8_t > Bytes , uint64_t Address , raw_ostream & vStream , raw_ostream & cStream ) const { MCDisassembler :: DecodeStatus Result ; if ( Bytes . size ( ) < <NUM_LIT> ) { Size = <NUM_LIT> ; return Fail ; } uint8_t DecodeByte = ( Bytes [ <NUM_LIT> ] & <NUM_LIT> ) >> <NUM_LIT> ; if ( DecodeByte < <NUM_LIT> ) { if ( Bytes . size ( ) < <NUM_LIT> ) { Size = <NUM_LIT> ; return Fail ; } if ( Bytes . size ( ) >= <NUM_LIT> ) { uint64_t Insn64 ; if ( ! readInstruction64 ( Bytes , Address , Size ,


<s> unsigned <ISA_LIT>MCCodeEmitter :: getMemEncodingMMImm9 ( const MCInst & MI , unsigned OpNo , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { assert ( MI . getOperand ( OpNo ) . isReg ( ) ) ; unsigned RegBits = getMachineOpValue ( MI , MI . getOperand ( OpNo ) , Fixups , STI ) << <NUM_LIT> ; unsigned OffBits = getMachineOpValue ( MI , MI . getOperand ( OpNo + <NUM_LIT> ) , Fixups , STI ) ; return ( OffBits & <NUM_LIT> )


<s> static CodeModel :: Model getEffectiveCodeModel ( Optional < CodeModel :: Model > CM , Reloc :: Model RM , bool JIT ) { if ( CM )


<s> return DebugFlag && isCurrentDebugType ( DEBUG_TYPE ) ; return false


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return


<s> case CmpInst :: Predicate :: ICMP_SLE : PredicateExtraCost = <NUM_LIT> ; break ; case CmpInst :: Predicate :: FCMP_ONE : case CmpInst :: Predicate :: FCMP_ORD : case CmpInst :: Predicate :: FCMP_UEQ : case CmpInst :: Predicate :: FCMP_UNO : PredicateExtraCost = <NUM_LIT> ; break ; default : break ; } } unsigned CmpCostPerVector = ( ValTy -> getScalarType ( ) -> isFloatTy ( ) ? <NUM_LIT> : <NUM_LIT> ) ; unsigned NumVecs_cmp = getNumberOfParts ( ValTy ) ; unsigned Cost = ( NumVecs_cmp * ( CmpCostPerVector + PredicateExtraCost ) ) ; return Cost ; } else { assert ( Opcode == Instruction :: Select ) ; unsigned PackCost = <NUM_LIT> ; Type * CmpOpTy = ( ( I != nullptr ) ? getCmpOpsType ( I , VF ) : nullptr ) ; if ( CmpOpTy != nullptr ) PackCost = getVectorBitmaskConversionCost ( CmpOpTy , ValTy ) ; return getNumberOfParts ( ValTy ) + PackCost ; } } else { switch ( Opcode ) { case Instruction :: ICmp : { unsigned Cost = <NUM_LIT> ; if ( ValTy -> isIntegerTy ( ) && ValTy -> getScalarSizeInBits ( ) <= <NUM_LIT> ) Cost += <NUM_LIT> ; return Cost ; } case Instruction


<s> return buildRSRC ( B , MRI , - <NUM_LIT> , Hi_32 ( DefaultFormat


<s> static enum riscv_symbol_type riscv_classify_symbol ( const_rtx x ) { if ( riscv_tls_symbol_p ( x ) )


<s> static int readPrefixes ( struct InternalInstruction * insn ) { BOOL isPrefix = TRUE ; BOOL prefixGroups [ <NUM_LIT> ] = { FALSE } ; uint64_t prefixLocation ; uint8_t byte = <NUM_LIT> ; BOOL hasAdSize = FALSE ; BOOL hasOpSize = FALSE ; dbgprintf ( insn , <STR_LIT> ) ; while ( isPrefix ) { prefixLocation = insn -> readerCursor ; if ( consumeByte ( insn , & byte ) ) return - <NUM_LIT> ; switch ( byte ) { case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : if ( prefixGroups [ <NUM_LIT> ] ) dbgprintf ( insn , <STR_LIT> ) ; prefixGroups [ <NUM_LIT> ] = TRUE ; setPrefixPresent ( insn , byte , prefixLocation ) ; break ; case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : switch ( byte ) { case <NUM_LIT> : insn -> segmentOverride = SEG_OVERRIDE_CS ; break ; case <NUM_LIT> : insn -> segmentOverride = SEG_OVERRIDE_SS ; break ; case <NUM_LIT> : insn -> segmentOverride = SEG_OVERRIDE_DS ; break ; case <NUM_LIT> : insn -> segmentOverride = SEG_OVERRIDE_ES ; break ; case <NUM_LIT> : insn -> segmentOverride = SEG_OVERRIDE_FS ; break ; case <NUM_LIT> : insn -> segmentOverride = SEG_OVERRIDE_GS ; break ; default : debug ( <STR_LIT> ) ; return - <NUM_LIT> ; } if ( prefixGroups [ <NUM_LIT> ] ) dbgprintf ( insn , <STR_LIT> ) ; prefixGroups [ <NUM_LIT> ] = TRUE ; setPrefixPresent ( insn , byte , prefixLocation ) ; break ; case <NUM_LIT> : if ( prefixGroups [ <NUM_LIT> ] ) dbgprintf ( insn , <STR_LIT> ) ; prefixGroups [ <NUM_LIT> ] = TRUE ; hasOpSize = TRUE ; setPrefixPresent ( insn , byte , prefixLocation ) ; break ; case <NUM_LIT> : if ( prefixGroups [ <NUM_LIT> ] ) dbgprintf ( insn , <STR_LIT> ) ; prefixGroups [ <NUM_LIT> ] = TRUE ; hasAdSize = TRUE ; setPrefixPresent ( insn , byte , prefixLocation ) ; break ; default : isPrefix = FALSE ; break ; } if ( isPrefix ) dbgprintf ( insn , <STR_LIT> , byte ) ; } if ( insn -> mode == MODE_64BIT ) { if ( ( byte & <NUM_LIT> ) == <NUM_LIT> ) { uint8_t opcodeByte ; if ( lookAtByte ( insn , & opcodeByte ) || ( ( opcodeByte & <NUM_LIT> ) == <NUM_LIT> ) ) { dbgprintf ( insn , <STR_LIT> ) ; return - <NUM_LIT> ; } insn -> rexPrefix = byte ; insn -> necessaryPrefixLocation = insn -> readerCursor - <NUM_LIT> ; dbgprintf ( insn , <STR_LIT> , byte ) ; } else { unconsumeByte ( insn ) ; insn -> necessaryPrefixLocation = insn -> readerCursor - <NUM_LIT> ; } } else { unconsumeByte ( insn ) ; insn -> necessaryPrefixLocation = insn -> readerCursor - <NUM_LIT> ; } if ( insn -> mode == MODE_16BIT ) { insn -> registerSize = ( hasOpSize ? <NUM_LIT> : <NUM_LIT> ) ; insn -> addressSize = ( hasAdSize ?


<s> BTFTypeDerived :: BTFTypeDerived ( unsigned NextTypeId , unsigned Tag , StringRef Name ) : DTy ( nullptr ) , NeedsFixup ( false ) , Name ( Name ) { Kind = <STR_LIT> ; BTFType . Info =


<s> unsigned DstSize = DstTy . getSizeInBits ( ) ; if ( CV -> isNullValue ( ) ) { if ( DstSize == <NUM_LIT> ) { auto Mov = MIRBuilder . buildInstr ( <STR_LIT> , { Dst } , { } ) . addImm ( <NUM_LIT> ) ; constrainSelectedInstRegOperands ( * Mov , TII , TRI , RBI ) ; return & * Mov ; } if ( DstSize == <NUM_LIT> ) { auto Mov = MIRBuilder . buildInstr ( <STR_LIT> , { & <STR_LIT> } , { } ) . addImm ( <NUM_LIT> ) ; auto Copy = MIRBuilder . buildInstr ( TargetOpcode :: COPY , { Dst } , { } ) . addReg ( Mov . getReg ( <NUM_LIT> ) , <NUM_LIT> , <STR_LIT> ) ; RBI . constrainGenericRegister ( Dst , <STR_LIT> , MRI ) ; return & * Copy ; } } auto * CPLoad = emitLoadFromConstantPool ( CV , MIRBuilder ) ; if ( ! CPLoad ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return nullptr ; } auto Copy = MIRBuilder . buildCopy ( Dst , CPLoad -> getOperand ( <NUM_LIT> ) ) ; RBI . constrainGenericRegister ( Dst , * MRI . getRegClass ( CPLoad -> getOperand


<s> if ( GET_CODE ( x ) == PLUS && CONSTANT_ADDRESS_P ( XEXP ( x , <NUM_LIT> ) ) && h8300_rtx_ok_for_base_p ( h8300_get_index ( XEXP ( x , <NUM_LIT> ) , mode ,

<NUM_LIT> ) , strict ) ) return <NUM_LIT> ;


<s> for ( u32 i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) { result |= ( ( value >> i ) & <NUM_LIT> ) << ( <NUM_LIT> - i ) ; } return result


<s> default : return SDValue ( ) ; case <STR_LIT> : { SDValue CountInput = IsRHSZero ? LHS : SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , LHS , RHS ) , <NUM_LIT> ) ; SDValue Cntlzw = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , CountInput ) , <NUM_LIT> ) ; SDValue SHLOps [ ] = { Cntlzw , getI32Imm ( <NUM_LIT> , dl ) , getI32Imm ( <NUM_LIT> , dl ) } ; SDValue Sldi = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , SHLOps ) , <NUM_LIT> ) ; return SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , Sldi , getI32Imm ( <NUM_LIT> , dl ) ) , <NUM_LIT> ) ; } case <STR_LIT> : { SDValue Xor = IsRHSZero ? LHS : SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , LHS , RHS ) , <NUM_LIT> ) ; SDValue Clz = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , Xor ) , <NUM_LIT> ) ; SDValue ShiftOps [ ] = { Clz , getI32Imm ( <NUM_LIT> , dl ) , getI32Imm ( <NUM_LIT> , dl ) , getI32Imm ( <NUM_LIT> , dl ) } ; SDValue Shift = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , ShiftOps ) , <NUM_LIT> ) ; SDValue Xori = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , Shift , getI32Imm ( <NUM_LIT> , dl ) ) , <NUM_LIT> ) ; return SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl


<s> FunctionPass * create<ISA_LIT>RelaxMemPass ( ) { return new <ISA_LIT>RelaxMem


<s> unsigned getModImmOpValue ( const MCInst & MI , unsigned Op , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & ST ) const { const MCOperand & MO = MI . getOperand ( Op ) ; if ( MO . isExpr ( ) ) { const MCExpr * Expr = MO . getExpr ( ) ; MCFixupKind Kind = MCFixupKind ( <STR_LIT> ) ; Fixups . push_back ( MCFixup :: create ( <NUM_LIT> , Expr , Kind , MI .


<s> target . the_registerFile = <STR_LIT> ; target . the_isVectorPipe = true ; target . the_slotID = <STR_LIT> ; } else { target . the_slotID = <STR_LIT> ; target . the_registerFile =


<s> unsigned <ISA_LIT>TTIImpl :: getCacheLineSize ( ) const { return ST . getL1CacheLineSize (


<s> SDValue Sad = createPSADBW ( DAG , SadOp0 , SadOp1 , DL , Subtarget ) ; MVT ResVT = <STR_LIT> ( <STR_LIT> , Sad . getValueSizeInBits ( ) / <NUM_LIT> ) ; Sad = DAG . getNode ( <STR_LIT> , DL , ResVT , Sad ) ; if ( VT . getSizeInBits ( ) > ResVT . getSizeInBits ( ) ) { assert ( VT . getSizeInBits ( ) % ResVT . getSizeInBits ( ) == <NUM_LIT> && <STR_LIT> ) ; unsigned NumConcats = VT . getSizeInBits ( ) / ResVT . getSizeInBits ( ) ; SmallVector < SDValue , <NUM_LIT> > Ops ( NumConcats , DAG . getConstant ( <NUM_LIT>


<s> * offset = const0_rtx ; return true ; } if ( GET_CODE ( addr ) == PLUS && REG_P ( XEXP ( addr , <NUM_LIT> ) ) && CONST_INT_P ( XEXP ( addr , <NUM_LIT> ) ) ) { * base = XEXP ( addr


<s> assert ( VT . isVector ( ) && InVT . isVector ( ) && <STR_LIT> ) ; if ( InVT . getSizeInBits ( ) > <NUM_LIT> ) { assert ( VT . getSizeInBits ( ) == InVT . getSizeInBits ( ) && <STR_LIT> ) ; unsigned Scale = VT . getScalarSizeInBits ( ) / InVT . getScalarSizeInBits ( ) ; In = extractSubVector ( In , <NUM_LIT> , DAG , DL , std :: max ( <NUM_LIT> , VT . getSizeInBits ( ) / Scale ) ) ; InVT = In . getValueType ( ) ; } if ( VT . getVectorNumElements ( ) == InVT . getVectorNumElements ( ) ) return DAG . getNode ( Signed ? <STR_LIT> : <STR_LIT>


<s> if ( VT . is64BitVector ( ) ) { SDValue Extended = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , BitCounts ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Extended ,

DAG . getIntPtrConstant ( <NUM_LIT> ) ) ;


<s> bool <ISA_LIT>TargetMachine :: addAssemblyEmitter ( PassManagerBase & PM , bool Fast , raw_ostream & Out ) { PM . add ( create<ISA_LIT>CodePrinterPass ( Out , * this , Fast ) ) ; return false


<s> } if ( MI . isDebugValue ( ) ) continue ; switch ( MI . getOpcode ( ) ) { default : break ; case <STR_LIT> : { int Immed = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( Immed != <NUM_LIT> ) { unsigned TrueReg1 = lookThruCopyLike ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; unsigned TrueReg2 = lookThruCopyLike ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; if ( TrueReg1 == TrueReg2 && TargetRegisterInfo :: isVirtualRegister ( TrueReg1 ) ) { MachineInstr * DefMI = MRI -> getVRegDef ( TrueReg1 ) ; if ( DefMI && DefMI -> getOpcode ( ) == <STR_LIT> ) { unsigned FeedImmed = DefMI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned FeedReg1 = lookThruCopyLike ( DefMI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; unsigned FeedReg2 = lookThruCopyLike ( DefMI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; if ( ( FeedImmed == <NUM_LIT> || FeedImmed == <NUM_LIT> ) && FeedReg1 == FeedReg2 ) { DEBUG ( dbgs ( ) << <STR_LIT> <STR_LIT> ) ; DEBUG ( MI . dump ( ) ) ; BuildMI ( MBB , & MI , MI . getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) . addOperand ( MI . getOperand ( <NUM_LIT> ) ) ; ToErase = & MI ; Simplified = true ; } else if ( ( Immed == <NUM_LIT> || Immed == <NUM_LIT> ) && FeedImmed == <NUM_LIT> && FeedReg1 == FeedReg2 ) { DEBUG ( dbgs ( ) <<


<s> NeedMask = false ; RLAmt . resize ( Bits . size ( ) ) ; for ( unsigned i = <NUM_LIT> ; i < Bits . size ( ) ; ++ i ) if ( Bits [ i ] . hasValue ( ) ) { unsigned VBI = Bits [ i ] . getValueBitIndex ( ) ; if ( i >= VBI ) RLAmt [ i ] = i - VBI ; else RLAmt [ i ] = Bits . size ( ) - ( VBI - i ) ; } else if ( Bits [ i ] . isZero ( ) ) { NeedMask = true ; RLAmt [ i ] = UINT32_MAX


<s> if ( REG_P ( addr_reg ) ) { reg = addr_reg ; } else if ( ( GET_CODE ( addr_reg ) == SUBREG && REG_P ( SUBREG_REG ( addr_reg ) ) && GET_MODE_SIZE ( GET_MODE ( SUBREG_REG ( addr_reg ) ) ) <= UNITS_PER_WORD ) ) { reg = SUBREG_REG ( addr_reg ) ; } else return FALSE ; if ( GET_MODE ( addr_reg ) != Pmode ) { return FALSE


<s> const MCOperand & DispSpec = MI -> getOperand ( Op + <NUM_LIT> ) ; const MCOperand & SegReg = MI -> getOperand ( Op + <NUM_LIT> ) ; O << markup ( <STR_LIT> ) ; if ( SegReg . getReg ( ) ) { printOperand ( MI , Op + <NUM_LIT> , O ) ; O << ':' ; } if ( DispSpec . isImm ( ) ) { int64_t DispVal = DispSpec . getImm ( ) ; if ( DispVal || ( ! IndexReg . getReg ( ) && ! BaseReg . getReg ( ) ) ) O << DispVal ; }


<s> bool <ISA_LIT>InstrInfo :: isReallyTriviallyReMaterializable ( const MachineInstr & MI ,


<s> void <ISA_LIT>ConstantPoolMBB :: print ( raw_ostream &


<s> unsigned flags = fieldFromInstruction16 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; Inst . addOperand ( MCOperand :: CreateImm ( imod )


<s> if ( RegInfo -> hasBasePointer ( MF ) ) FrameReg = RegInfo -> getBaseRegister ( ) ; else if ( RegInfo -> needsStackRealignment ( MF ) ) FrameReg = RegInfo ->


<s> initializeGCNPreRAOptimizationsPass ( * PassRegistry :: getPassRegistry


<s> StartLoc = Tok . getLoc ( ) ; EndLoc = Tok . getEndLoc ( ) ; RegNo = <NUM_LIT> ; int64_t IntVal ; if ( ! MatchRegisterName ( Tok , RegNo , IntVal ) ) { Parser . Lex ( ) ; return false


<s> assert ( MO . isReg ( ) && MO . getReg ( ) ) ; if ( MO . isUse ( ) ) UseMI . addOperand ( MO ) ; else DefMI . addOperand (


<s> static CodeModel :: Model getEffective<ISA_LIT>CodeModel ( Optional < CodeModel :: Model > CM , bool JIT , bool Is64Bit ) { if ( CM


<s> case <NUM_LIT> : return RB . getID ( ) == <STR_LIT> ? & <STR_LIT> : & <STR_LIT> ; case <NUM_LIT> : return RB . getID ( ) == <STR_LIT> ? & <STR_LIT> : & <STR_LIT> ; case <NUM_LIT> : return RB . getID ( ) == <STR_LIT> ? & <STR_LIT> : & <STR_LIT> ; case <NUM_LIT> : return RB . getID ( ) == <STR_LIT> ? & <STR_LIT> : & <STR_LIT> ; case <NUM_LIT> : return RB . getID ( ) == <STR_LIT> ? & <STR_LIT> : & <STR_LIT> ; case <NUM_LIT> : return RB . getID ( ) == <STR_LIT> ? & <STR_LIT> : & <STR_LIT> ; default : if ( Size < <NUM_LIT> ) return RB . getID ( ) == <STR_LIT>


<s> unsigned <ISA_LIT>CodeEmitter :: getBranchTargetOpValue ( const MachineInstr & MI , unsigned


<s> MachineBasicBlock :: iterator <ISA_LIT>FrameLowering :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { int64_t Amount = I -> getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( Amount == <NUM_LIT> ) return MBB . erase ( I ) ; const GCNSubtarget & ST = MF . getSubtarget < GCNSubtarget > ( ) ; const <ISA_LIT>InstrInfo * TII = ST . getInstrInfo ( ) ; const DebugLoc & DL = I -> getDebugLoc ( ) ; unsigned Opc = I -> getOpcode ( ) ; bool IsDestroy = Opc == TII -> getCallFrameDestroyOpcode ( ) ; uint64_t CalleePopAmount = IsDestroy ? I -> getOperand ( <NUM_LIT> ) . getImm ( ) : <NUM_LIT> ; if ( ! hasReservedCallFrame ( MF ) ) { Amount = alignTo ( Amount , getStackAlign ( ) ) ; assert ( isUInt < <NUM_LIT> > ( Amount ) && <STR_LIT> ) ; const <ISA_LIT>MachineFunctionInfo * MFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; Register SPReg = MFI -> getStackPtrOffsetReg ( ) ; Amount *= getScratchScaleFactor ( ST ) ; if ( IsDestroy ) Amount = - Amount ; BuildMI ( MBB , I , DL , TII -> get ( <STR_LIT> ) , SPReg ) . addReg ( SPReg ) . addImm ( Amount ) ; } else if ( CalleePopAmount != <NUM_LIT> ) { llvm_unreachable ( <STR_LIT> ) ; } return MBB . erase


<s> case MCSymbolRefExpr :: VK_<ISA_LIT>_HIGHER : case MCSymbolRefExpr :: VK_<ISA_LIT>_HIGHEST : break ; default : return false ; } if ( isa < MCBinaryExpr > ( BE -> getLHS ( ) ) ) { if ( ! isa < MCConstantExpr > ( BE -> getRHS ( ) ) ) return false ; BE = cast < MCBinaryExpr > ( BE -> getLHS ( ) ) ; } return ( isa < MCSymbolRefExpr > ( BE -> getLHS ( ) ) &&

isa < MCSymbolRefExpr > ( BE -> getRHS ( ) ) ) ;


<s> static MCDisassembler * create<ISA_LIT>Disassembler ( const Target & T , const MCSubtargetInfo & STI , MCContext


<s> uint64_t Init = <NUM_LIT> ; for ( MachineInstr & I : MRI -> def_instructions ( Reg ) ) { if ( I . getOpcode ( ) != <STR_LIT> || I . getOperand ( <NUM_LIT> ) . getReg ( ) != Reg || ! I . getOperand ( <NUM_LIT> ) . isImm ( ) || I . getNumOperands ( ) != <NUM_LIT> ) return false ; switch ( I . getOperand ( <NUM_LIT> ) . getSubReg ( ) ) { default : return false ; case <STR_LIT> : if ( Def0 ) return false ; Def0 = & I ; Init |= I . getOperand ( <NUM_LIT> ) . getImm ( ) & <NUM_LIT> ; break ; case <STR_LIT> : if ( Def1 ) return false ; Def1 = & I ; Init |= static_cast < uint64_t > ( I . getOperand ( <NUM_LIT> ) . getImm ( ) ) << <NUM_LIT> ; break ; } } if ( ! Def0 || ! Def1 || Def0 -> getParent ( ) != Def1 -> getParent ( ) ) return false ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * Def0 << <STR_LIT> << * Def1 << <STR_LIT> ) ; if ( SlotIndex :: isEarlierInstr ( LIS -> getInstructionIndex ( * Def1 ) , LIS -> getInstructionIndex ( * Def0 ) ) ) std :: swap ( Def0 , Def1 ) ; LIS -> RemoveMachineInstrFromMaps ( * Def0 ) ; LIS -> RemoveMachineInstrFromMaps ( * Def1 ) ; auto NewI = BuildMI ( * Def0 -> getParent ( ) , * Def0 , Def0 -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , Reg ) . addImm ( Init ) ; Def0 -> eraseFromParent ( ) ; Def1 -> eraseFromParent ( ) ; LIS -> InsertMachineInstrInMaps ( * NewI ) ; LIS -> removeInterval ( Reg ) ; LIS -> createAndComputeVirtRegInterval ( Reg ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * NewI


<s> return CreateReg ( Index , RegKind_FCC , RegInfo , S , E ,


<s> return ( int ) __builtin_loongarch_crc_w_h_w ( ( short ) _1 , ( int


<s> SDLoc DL ( Op ) ; MVT VecVT = Op . getSimpleValueType ( ) ; assert ( ! Subtarget . is64Bit ( ) && VecVT . getVectorElementType ( ) == <STR_LIT> && <STR_LIT> ) ; assert ( Op . getNumOperands ( ) == <NUM_LIT> && <STR_LIT> ) ; SDValue Lo = Op . getOperand ( <NUM_LIT> ) ; SDValue Hi = Op . getOperand ( <NUM_LIT> ) ; if ( VecVT . isFixedLengthVector ( ) ) { MVT ContainerVT = getContainerForFixedLengthVector ( VecVT ) ; SDLoc DL ( Op ) ; SDValue Mask , VL ; std :: tie ( Mask , VL ) = getDefaultVLOps ( VecVT , ContainerVT , DL , DAG , Subtarget ) ; SDValue Res = splatPartsI64WithVL ( DL , ContainerVT , Lo , Hi ,


<s> AU . addPreserved < DominatorTreeWrapperPass >


<s> static SDValue createPSADBW ( SelectionDAG & DAG , const SDValue & Zext0 , const SDValue & Zext1 , const SDLoc & DL , const <ISA_LIT>Subtarget & Subtarget ) { EVT InVT = Zext0 . getOperand ( <NUM_LIT> ) . getValueType ( ) ; unsigned RegSize = std :: max ( <NUM_LIT> , ( unsigned ) InVT . getSizeInBits ( ) ) ; unsigned NumConcat = RegSize / InVT . getSizeInBits ( ) ; SmallVector < SDValue , <NUM_LIT> > Ops ( NumConcat , DAG . getConstant ( <NUM_LIT> , DL , InVT ) ) ; Ops [ <NUM_LIT> ] = Zext0 . getOperand ( <NUM_LIT> ) ; MVT ExtendedVT = <STR_LIT> ( <STR_LIT> , RegSize / <NUM_LIT> ) ; SDValue SadOp0 = DAG . getNode ( <STR_LIT> , DL , ExtendedVT , Ops ) ; Ops [ <NUM_LIT> ] = Zext1 . getOperand ( <NUM_LIT> ) ; SDValue SadOp1 = DAG . getNode ( <STR_LIT> , DL , ExtendedVT , Ops ) ; auto PSADBWBuilder = [ ] ( SelectionDAG & DAG , const SDLoc &


<s> const <ISA_LIT>TargetLowering * getTargetLowering ( ) const override { return &


<s> size_t getRelaEntrySize ( ) { return <NUM_LIT>


<s> if ( Opc == <STR_LIT> || Opc == <STR_LIT> ) continue ; if ( HII -> isMemOp ( * MJ ) ) continue ; if ( MJ -> mayLoad ( ) ) FoundLoad = true ; if ( MJ -> mayStore ( ) && ! HII -> isNewValueStore ( * MJ ) ) FoundStore = true ; } return FoundLoad &&


<s> RegMap [ Stack [ -- StackTop ] ] = ~ <NUM_LIT> ; int Opcode = Lookup ( PopTable , array_lengthof ( PopTable ) , I -> getOpcode ( ) ) ; if ( Opcode != - <NUM_LIT> ) { I -> setDesc ( TII -> get ( Opcode ) ) ; if ( Opcode == <STR_LIT> ) I -> RemoveOperand ( <NUM_LIT> ) ; }


<s> fputs ( <STR_LIT> , asm_out_file ) ; fputs ( <STR_LIT> , asm_out_file ) ; fputs ( <STR_LIT> , asm_out_file ) ; fputs ( <STR_LIT> , asm_out_file ) ; fputs ( <STR_LIT> , asm_out_file ) ; fputs ( <STR_LIT> , asm_out_file ) ; fputs ( <STR_LIT> , asm_out_file ) ; unicosmk_output_default_externs ( asm_out_file


<s> initialize<ISA_LIT>OffsetAllocatorPass ( * PassRegistry ::


<s> void <ISA_LIT>LowerMemoryIntrinsics :: AddToLazyDeletionSet ( User * Elm ) { if ( DeletionSet . find ( Elm ) == DeletionSet . end (


<s> __ev64_opaque__ t ; t = __ev_mwhumi ( a , b ) ; return __ev_mwumiaa ( t , ( ( __ev64_s32__ ) { <NUM_LIT> , <NUM_LIT> }


<s> if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = <STR_LIT> ; else if ( RC -> hasType ( <STR_LIT> ) ) Opc = <STR_LIT> ; else if ( RC -> hasType ( <STR_LIT> ) || RC -> hasType ( <STR_LIT> ) ) Opc = <STR_LIT> ; else if ( RC -> hasType ( <STR_LIT> ) || RC -> hasType ( <STR_LIT> ) ) Opc = <STR_LIT> ; else if ( RC -> hasType ( <STR_LIT> ) || RC -> hasType ( <STR_LIT> ) ) Opc = <STR_LIT> ; assert ( Opc && <STR_LIT>


<s> if ( N . getOpcode ( ) == <STR_LIT> ) { if ( isIntS16Immediate ( N . getOperand ( <NUM_LIT> ) , imm ) ) return false ; if ( N . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) return false ; Base = N . getOperand ( <NUM_LIT> ) ; Index = N . getOperand ( <NUM_LIT> ) ; return true ; } else if ( N . getOpcode ( ) == <STR_LIT> ) { if ( isIntS16Immediate ( N . getOperand ( <NUM_LIT> ) , imm ) ) return false ; APInt LHSKnownZero ,


<s> if ( ( SD -> getAlignment ( ) >= MemVT . getSizeInBits ( ) / <NUM_LIT> ) || ( ( MemVT != <STR_LIT> ) && ( MemVT != <STR_LIT> ) ) ) return SDValue ( ) ; bool IsLittle = Subtarget -> isLittle ( ) ; SDValue Value = SD -> getValue ( ) , Chain = SD -> getChain ( ) ; EVT VT = Value . getValueType ( ) ; if ( ( VT == <STR_LIT> ) || SD -> isTruncatingStore ( ) ) { SDValue SWL = CreateStoreLR ( <STR_LIT> , DAG , SD , Chain , IsLittle ? <NUM_LIT> : <NUM_LIT> ) ; return CreateStoreLR ( <STR_LIT> , DAG , SD , SWL , IsLittle ? <NUM_LIT> : <NUM_LIT> ) ; } assert ( VT == <STR_LIT> ) ; SDValue SDL = CreateStoreLR ( <STR_LIT> , DAG , SD , Chain , IsLittle


<s> if ( ( fnmask & RS6000_BTM_CELL ) != <NUM_LIT> ) error ( <STR_LIT> , name ) ; else if ( ( fnmask & RS6000_BTM_VSX ) != <NUM_LIT> ) error ( <STR_LIT> , name ) ; else if ( ( fnmask & RS6000_BTM_HTM ) != <NUM_LIT> ) error ( <STR_LIT> , name ) ; else if ( ( fnmask & RS6000_BTM_ALTIVEC ) != <NUM_LIT> ) error ( <STR_LIT> , name ) ; else if ( ( fnmask & RS6000_BTM_PAIRED ) != <NUM_LIT> ) error ( <STR_LIT> , name ) ; else if ( ( fnmask & RS6000_BTM_SPE ) != <NUM_LIT> ) error ( <STR_LIT> , name ) ; else if ( ( fnmask & ( RS6000_BTM_DFP | RS6000_BTM_P8_VECTOR ) ) == ( RS6000_BTM_DFP | RS6000_BTM_P8_VECTOR ) ) error ( <STR_LIT> <STR_LIT> , name ) ; else if ( ( fnmask & RS6000_BTM_DFP ) != <NUM_LIT> ) error ( <STR_LIT> , name ) ; else if ( ( fnmask & RS6000_BTM_P8_VECTOR ) != <NUM_LIT> ) error


<s> EmitFrames ( nullptr ) ; MCWinCOFFStreamer :: FinishImpl (


<s> auto * RVFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; return ( ( MFI . hasVarSizedObjects ( ) || RVFI -> hasSpillVRs ( ) ) && TRI -> needsStackRealignment (


<s> unsigned <ISA_LIT>RegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { const TargetFrameLowering * TFI = MF . getTarget ( ) . getFrameLowering ( ) ; if ( TFI -> hasFP ( MF ) ) { return <STR_LIT>


<s> else if ( auto * Preheader = MLI -> findLoopPreheader ( ML , true , true ) ) dbgs ( ) << <STR_LIT> << printMBBReference ( * Preheader ) << <STR_LIT> ; for ( auto * MBB : ML -> getBlocks ( ) ) dbgs ( ) << <STR_LIT> << printMBBReference ( * MBB ) << <STR_LIT> ; } ) ; std :: function < MachineInstr * ( MachineBasicBlock * ) > SearchForStart = [ & SearchForStart ] ( MachineBasicBlock * MBB ) -> MachineInstr * { for ( auto & MI : * MBB ) { if ( isLoopStart ( MI ) ) return & MI ; } if ( MBB -> pred_size ( ) == <NUM_LIT> ) return SearchForStart ( * MBB -> pred_begin ( ) ) ; return nullptr ; } ; LowOverheadLoop LoLoop ( * ML , * MLI , * RDA , * TRI , * TII ) ; if ( LoLoop . Preheader ) LoLoop . Start = SearchForStart ( LoLoop . Preheader ) ; else return Changed ; for ( auto * MBB : reverse ( ML -> getBlocks ( ) ) ) { for ( auto & MI :


<s> } u ; u . v = a ; u . i [ pos ] = b ; return u


<s> SDValue Ops [ ] = { RegSeq , CurDAG -> getTargetConstant ( LaneNo , dl , <STR_LIT> ) , N -> getOperand ( NumVecs + <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) } ; SDNode * St = CurDAG -> getMachineNode ( Opc , dl , <STR_LIT> , Ops ) ; MachineSDNode :: mmo_iterator MemOp = MF -> allocateMemRefsArray ( <NUM_LIT> ) ; MemOp [ <NUM_LIT> ] = cast < MemIntrinsicSDNode > ( N ) -> getMemOperand ( ) ; cast < MachineSDNode > ( St ) -> setMemRefs ( MemOp , MemOp + <NUM_LIT> ) ; ReplaceNode ( N , St


<s> void <ISA_LIT>TTIImpl :: getUnrollingPreferences ( Loop * L , ScalarEvolution & SE , TTI :: UnrollingPreferences & UP ) { if ( ST -> getMcpu ( )


<s> static <ISA_LIT>Operand * CreateExpr ( const MCExpr * Val , SMLoc S , SMLoc


<s> return SDValue ( ) ; } ; if ( SDValue ExtSrc = IsAnyExt64 ( peekThroughOneUseBitcasts ( Src ) ) ) return DAG . getBitcast ( VT , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getAnyExtOrTrunc ( ExtSrc , DL , <STR_LIT> ) ) ) ; } if ( VT == <STR_LIT> && Src . getOpcode ( ) == <STR_LIT> && Src . getOperand ( <NUM_LIT> ) . getValueType ( ) == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , DL , VT , Src . getOperand ( <NUM_LIT> ) ) ; if ( VT . getScalarType ( ) == Src . getValueType ( ) ) for ( SDNode * User : Src -> uses ( ) ) if ( User -> getOpcode ( ) == <STR_LIT> && Src == User -> getOperand ( <NUM_LIT> ) ) { unsigned SizeInBits = VT . getFixedSizeInBits ( ) ; unsigned BroadcastSizeInBits = User -> getValueSizeInBits ( <NUM_LIT> ) . getFixedSize ( ) ; if ( BroadcastSizeInBits == SizeInBits ) return SDValue ( User , <NUM_LIT> ) ; if ( BroadcastSizeInBits > SizeInBits ) return extractSubVector ( SDValue ( User , <NUM_LIT> ) , <NUM_LIT> , DAG , DL , SizeInBits ) ; } return SDValue


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; } return false


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; PredicateOp Pred = getPredicate ( ) ; assert ( Pred . IsVector ) ; Inst . addOperand ( MCOperand :: createReg ( Pred . RegNum ) ) ; Inst . addOperand ( MCOperand :: createImm ( Pred


) _mm512_setzero_hi ( ) , ( __mmask32 ) - <NUM_LIT> ) ;


<s> MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; EVT LocVT = VA . getLocVT ( ) ; EVT ValVT = VA . getValVT ( ) ; EVT PtrVT = <STR_LIT> ( DAG . getDataLayout ( ) . getPointerSizeInBits ( <NUM_LIT> ) ) ; int FI = MFI . CreateFixedObject ( ValVT . getSizeInBits ( ) /

<NUM_LIT> , VA . getLocMemOffset ( ) , true ) ;


<s> DebugLoc DL = MI . getDebugLoc ( ) ; assert ( MI . getOpcode ( ) == <STR_LIT> && <STR_LIT> ) ; const BasicBlock * LLVM_BB = BB -> getBasicBlock ( ) ; MachineFunction :: iterator I = ++ BB -> getIterator ( ) ; MachineBasicBlock * HeadMBB = BB ; MachineFunction * F = BB -> getParent ( ) ; MachineBasicBlock * TailMBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * IfFalseMBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; F -> insert ( I , IfFalseMBB ) ; F -> insert ( I , TailMBB ) ; TailMBB -> splice ( TailMBB -> begin ( ) , HeadMBB , std :: next ( MachineBasicBlock :: iterator ( MI ) ) , HeadMBB -> end ( ) ) ; TailMBB -> transferSuccessorsAndUpdatePHIs ( HeadMBB ) ; HeadMBB -> addSuccessor ( IfFalseMBB ) ; HeadMBB -> addSuccessor


<s> unsigned Opc = MI -> getOpcode ( ) ; if ( Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ) { const MachineOperand * Src0 = TII -> getNamedOperand ( * MI , <STR_LIT> :: src0 ) ; const MachineOperand * Src1 = TII -> getNamedOperand ( * MI , <STR_LIT> :: src1 ) ; if ( Src1 -> isIdenticalTo ( * Src0 ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * MI << <STR_LIT> ) ; int Src2Idx = <STR_LIT> ( Opc , <STR_LIT> :: src2 ) ; if ( Src2Idx != - <NUM_LIT> ) MI -> RemoveOperand ( Src2Idx ) ; MI -> RemoveOperand ( <STR_LIT> ( Opc , <STR_LIT> :: src1 ) ) ; mutateCopyOp ( * MI , TII -> get ( Src0 -> isReg ( ) ? ( unsigned ) <STR_LIT> : getMovOpc ( false


<s> unsigned s1 = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned is32Bit = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; if ( ! is32Bit ) return MCDisassembler :: Fail ; DecodeStatus status = DecodeOperandRegister ( Inst , d , Address , Decoder ) ; if ( status != MCDisassembler :: Success ) return status ; status = DecodeOperandRegister ( Inst , s3 , Address , Decoder ) ; if ( status != MCDisassembler :: Success ) return status ; status = DecodeOperandRegister ( Inst , s2 , Address


<s> return ( llvm :: findOneNVVMAnnotation ( & F , llvm :: PropertyAnnotationNames [ llvm ::


<s> unsigned llvm :: getBLXOpcode ( const


<s> } else if ( RC == & <STR_LIT> ) { Opc = <STR_LIT> ; } else if ( RC == & <STR_LIT> ) { Opc = <STR_LIT> ; } else if ( RC == & <STR_LIT> ) { Opc = <STR_LIT> ; } else if ( RC == & <STR_LIT> ) { Opc = <STR_LIT> ; } else if ( RC == & <STR_LIT> ) { Opc = <STR_LIT> ; } else if ( RC == & <STR_LIT> ) { Opc = <STR_LIT> ; } else if ( RC == & <STR_LIT> ) { Opc = <STR_LIT> ; } else if ( RC == & <STR_LIT> ) { Opc = <STR_LIT> ; } else if ( RC == & <STR_LIT> ) { Opc = <STR_LIT> ; } else if ( RC == & <STR_LIT> ) { Opc = isStackAligned ? <STR_LIT> : <STR_LIT> ; } else if ( RC == & <STR_LIT> ) { Opc = <STR_LIT> ; } else { assert ( <NUM_LIT> && <STR_LIT> ) ; abort (


<s> if ( CurInfo . isCompatible ( Require ) ) return false ; if ( ! CurInfo . isUnknown ( ) && Require . hasAVLReg ( ) && Require . getAVLReg ( ) . isVirtual ( ) && ! CurInfo . hasSEWLMULRatioOnly ( ) && Require . hasSameVTYPE ( CurInfo ) ) { if ( MachineInstr * DefMI = MRI -> getVRegDef ( Require . getAVLReg ( ) ) ) { if ( DefMI -> getOpcode ( ) == <STR_LIT> || DefMI -> getOpcode ( ) == <STR_LIT> || DefMI -> getOpcode (


<s> assert ( Cond . size ( ) == <NUM_LIT> ) ; return true


<s> MachineFunction & MF = * MBB . getParent ( ) ; const TargetInstrInfo & TII = * MF . getSubtarget ( ) . getInstrInfo ( ) ; <ISA_LIT>Z80MachineFunctionInfo * MFI = MF . getInfo < <ISA_LIT>Z80MachineFunctionInfo > ( ) ; MFI -> setCalleeSavedFrameSize ( CSI . size ( ) * <NUM_LIT> ) ; for ( unsigned i = CSI . size ( ) ; i != <NUM_LIT> ; i


<s> HOST_WIDE_INT offset ; bool interrupt_save_prologue_temp = false ; unsigned int regno , i , num_x_saved = <NUM_LIT> , num_f_saved = <NUM_LIT> ; frame = & cfun -> machine -> frame ; if ( cfun -> machine -> interrupt_handler_p ) { HOST_WIDE_INT step1 = riscv_first_stack_step ( frame ) ; if ( ! SMALL_OPERAND ( frame -> total_size - step1 ) ) interrupt_save_prologue_temp = true ; } memset ( frame , <NUM_LIT> , sizeof ( * frame ) ) ; if ( ! cfun -> machine -> naked_p ) { for ( regno = GP_REG_FIRST ; regno <= GP_REG_LAST ; regno ++ ) if ( riscv_save_reg_p ( regno ) || ( interrupt_save_prologue_temp && ( regno == RISCV_PROLOGUE_TEMP_REGNUM ) ) ) frame -> mask |= <NUM_LIT> << ( regno - GP_REG_FIRST ) , num_x_saved ++ ; if ( crtl -> calls_eh_return ) for ( i = <NUM_LIT> ; ( regno = EH_RETURN_DATA_REGNO ( i ) ) != INVALID_REGNUM ; i ++ ) frame -> mask |= <NUM_LIT> << ( regno - GP_REG_FIRST ) , num_x_saved ++ ; if ( TARGET_HARD_FLOAT ) for ( regno = FP_REG_FIRST ; regno <= FP_REG_LAST ; regno ++ ) if ( riscv_save_reg_p ( regno ) ) frame -> fmask |= <NUM_LIT> << ( regno - FP_REG_FIRST ) , num_f_saved ++ ; } offset = RISCV_STACK_ALIGN ( crtl -> outgoing_args_size ) ; offset += RISCV_STACK_ALIGN ( get_frame_size ( ) ) ; frame -> frame_pointer_offset = offset ; if ( frame -> fmask ) offset += RISCV_STACK_ALIGN ( num_f_saved * UNITS_PER_FP_REG ) ; frame -> fp_sp_offset = offset - UNITS_PER_FP_REG ; if ( frame -> mask ) { unsigned x_save_size = RISCV_STACK_ALIGN ( num_x_saved * UNITS_PER_WORD ) ; unsigned num_save_restore = <NUM_LIT> + riscv_save_libcall_count ( frame -> mask ) ; if ( RISCV_STACK_ALIGN ( num_save_restore * UNITS_PER_WORD ) == x_save_size ) { if ( TARGET_RVE ) x_save_size = <NUM_LIT> * UNITS_PER_WORD ; frame -> save_libcall_adjustment = x_save_size ; } offset += x_save_size ; } frame -> gp_sp_offset = offset - UNITS_PER_WORD ; frame -> hard_frame_pointer_offset = offset ; offset += RISCV_STACK_ALIGN ( cfun -> machine -> varargs_size ) ; offset += RISCV_STACK_ALIGN ( crtl -> args . pretend_args_size ) ; frame -> arg_pointer_offset = offset - crtl ->


<s> PrivateGlobalPrefix = <STR_LIT> ; WeakRefDirective = <STR_LIT> ; SetDirective = <STR_LIT> ; PCSymbol = <STR_LIT> ; NonexecutableStackDirective =


<s> } case <STR_LIT> : if ( AM . BaseType == <ISA_LIT>ISelAddressMode :: RegBase && AM . Base . Reg . getNode ( ) == <NUM_LIT> ) { AM . BaseType = <ISA_LIT>ISelAddressMode :: FrameIndexBase ; AM . Base . FrameIndex = cast < FrameIndexSDNode > ( N ) -> getIndex ( ) ; return false ; } break ; case <STR_LIT> : { <ISA_LIT>ISelAddressMode Backup = AM ; if ( ! MatchAddress ( N . getNode ( ) -> getOperand ( <NUM_LIT> ) , AM ) && ! MatchAddress ( N . getNode ( ) -> getOperand ( <NUM_LIT> ) , AM ) ) return false ; AM = Backup ; if ( ! MatchAddress ( N . getNode ( ) -> getOperand ( <NUM_LIT> ) , AM ) && ! MatchAddress ( N . getNode ( ) -> getOperand ( <NUM_LIT> )


<s> return ; } SmallVector < unsigned , <NUM_LIT> > ArgsParts ; ParseFunctionArgs ( Args , ArgsParts ) ; unsigned RegsLeft = NbRegs ; bool UseStack = false ; unsigned ValNo = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> , e = ArgsParts . size ( ) ; i != e ; i ++ ) { MVT ArgVT = Args [ ValNo ] . VT ; <STR_LIT> ArgFlags = Args [ ValNo ] . Flags ; MVT LocVT = ArgVT ; CCValAssign :: LocInfo LocInfo = CCValAssign :: Full ; if ( LocVT == <STR_LIT> ) { LocVT = <STR_LIT> ; if ( ArgFlags . isSExt ( ) ) LocInfo = CCValAssign :: SExt ; else if ( ArgFlags . isZExt ( ) ) LocInfo = CCValAssign :: ZExt ; else LocInfo = CCValAssign :: AExt ; } if ( ArgFlags . isByVal ( ) ) { State . HandleByVal ( ValNo ++ , ArgVT , LocVT , LocInfo , <NUM_LIT> , <NUM_LIT> , ArgFlags ) ; continue ; } unsigned Parts = ArgsParts [ i ] ; if ( ! UseStack && Parts <= RegsLeft ) { unsigned FirstVal = ValNo ; for ( unsigned j = <NUM_LIT> ; j < Parts ; j ++ ) { unsigned Reg = State . AllocateReg ( RegList ) ; State . addLoc ( CCValAssign :: getReg ( ValNo ++ , ArgVT , Reg , LocVT , LocInfo ) ) ; RegsLeft -- ; } SmallVectorImpl < CCValAssign > :: iterator B = ArgLocs . begin ( ) + FirstVal ; std :: reverse ( B , B + Parts ) ; } else { UseStack = true ; for ( unsigned j = <NUM_LIT> ; j < Parts ; j ++ ) CC_<ISA_LIT>_AssignStack ( ValNo ++ , ArgVT

, LocVT , LocInfo , ArgFlags , State ) ;


<s> const TargetInstrInfo * TII = Subtarget . getInstrInfo ( ) ; const <ISA_LIT>FrameLowering & TFI = * Subtarget . getFrameLowering ( ) ; DebugLoc DL = MI . getDebugLoc ( ) ; const BasicBlock * LLVM_BB = MBB -> getBasicBlock ( ) ; const unsigned ProbeSize = getStackProbeSize ( * MF ) ; MachineRegisterInfo & MRI = MF -> getRegInfo ( ) ; MachineBasicBlock * testMBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * tailMBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * blockMBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineFunction :: iterator MBBIter = ++ MBB -> getIterator ( ) ; MF -> insert ( MBBIter , testMBB ) ; MF -> insert ( MBBIter , blockMBB ) ; MF -> insert ( MBBIter , tailMBB ) ; Register sizeVReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register physSPReg = TFI . Uses64BitFramePtr ? <STR_LIT> : <STR_LIT> ; Register TmpStackPtr = MRI . createVirtualRegister ( TFI . Uses64BitFramePtr ? & <STR_LIT> : & <STR_LIT> ) ; Register FinalStackPtr = MRI . createVirtualRegister ( TFI . Uses64BitFramePtr ? & <STR_LIT> : & <STR_LIT> ) ; BuildMI ( * MBB , { MI } , DL , TII -> get ( TargetOpcode :: COPY ) , TmpStackPtr ) . addReg ( physSPReg ) ; { const unsigned Opc = TFI . Uses64BitFramePtr ? <STR_LIT> : <STR_LIT> ; BuildMI ( * MBB , { MI } , DL , TII -> get ( Opc ) , FinalStackPtr ) . addReg ( TmpStackPtr ) . addReg ( sizeVReg ) ; } BuildMI ( testMBB , DL , TII -> get ( TFI . Uses64BitFramePtr ? <STR_LIT> : <STR_LIT> ) ) . addReg ( physSPReg ) . addReg ( FinalStackPtr ) ; BuildMI ( testMBB , DL , TII -> get ( <STR_LIT> ) ) . addMBB ( tailMBB ) . addImm ( <STR_LIT> ) ; testMBB -> addSuccessor ( blockMBB ) ; testMBB -> addSuccessor ( tailMBB ) ; BuildMI ( blockMBB , DL , TII -> get ( getSUBriOpcode ( TFI . Uses64BitFramePtr , ProbeSize ) ) , physSPReg ) . addReg ( physSPReg ) . addImm ( ProbeSize ) ; const unsigned MovMIOpc = TFI . Uses64BitFramePtr ? <STR_LIT> : <STR_LIT> ; addRegOffset ( BuildMI ( blockMBB , DL , TII -> get ( MovMIOpc ) ) , physSPReg , false , <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; BuildMI ( blockMBB , DL , TII -> get ( <STR_LIT> ) ) . addMBB ( testMBB ) ; blockMBB -> addSuccessor ( testMBB


<s> return ( __m256i ) __builtin_ia32_pternlogq256_mask ( ( __v4di ) __A , ( __v4di ) __B , ( __v4di ) __C , imm ,


<s> return ( __m256d ) __builtin_ia32_orpd256 ( ( __v4df )


<s> int64_t Fmt = UFMT_UNDEF ; if ( ! tryParseFmt ( <STR_LIT> , UFMT_MAX , Fmt ) ) return MatchOperand_ParseFail ; if ( Fmt == UFMT_UNDEF ) return MatchOperand_NoMatch ; Format = Fmt ; return


<s> bool <ISA_LIT>InstructionSelector :: selectUnmergeValues ( MachineInstr & I , MachineRegisterInfo & MRI , MachineFunction & MF ) const { if ( I . getOpcode ( ) != TargetOpcode :: G_UNMERGE_VALUES ) return false ; unsigned NumDefs = I . getNumOperands ( ) - <NUM_LIT> ; unsigned SrcReg = I . getOperand ( NumDefs ) . getReg ( ) ; unsigned DefSize = MRI . getType ( I . getOperand ( <NUM_LIT> ) . getReg ( ) ) . getSizeInBits ( ) ; for ( unsigned Idx = <NUM_LIT> ; Idx < NumDefs ; ++ Idx ) { MachineInstr & ExtrInst = * BuildMI ( * I . getParent ( ) , I , I . getDebugLoc ( ) , TII . get ( TargetOpcode :: G_EXTRACT ) , I . getOperand ( Idx ) . getReg ( ) ) . addReg ( SrcReg ) . addImm ( Idx * DefSize ) ; if ( ! select ( ExtrInst ) ) return false ; } I . eraseFromParent ( ) ; return true


<s> return checkType ( N -> getMemOperand ( ) ->


<s> return ( __m256 ) __builtin_ia32_roundps256 ( ( __v8sf )


<s> CCInfo . AllocateReg ( ImplicitBufferPtrReg ) ; } unsigned NumArgs = F . arg_size ( ) ; Function :: const_arg_iterator CurOrigArg = F . arg_begin ( ) ; const <ISA_LIT>TargetLowering & TLI = * getTLI < <ISA_LIT>TargetLowering > ( ) ; unsigned P<ISA_LIT>nputNum = <NUM_LIT> ; BitVector Skipped ( NumArgs ) ; for ( unsigned i = <NUM_LIT> ; i != NumArgs ; ++ i , ++ CurOrigArg ) { EVT ValEVT = TLI . getValueType ( DL , CurOrigArg -> getType ( ) ) ; <STR_LIT> Flags ; assert ( VRegs [ i ] . size ( ) == <NUM_LIT> && <STR_LIT> ) ; ArgInfo OrigArg { VRegs [ i ] [ <NUM_LIT> ] , CurOrigArg -> getType ( ) } ; setArgFlags ( OrigArg , i + <NUM_LIT> , DL , F ) ; Flags . setOrigAlign ( DL . getABITypeAlignment ( CurOrigArg -> getType ( ) ) ) ; if ( F . getCallingConv ( ) == CallingConv :: <ISA_LIT>_PS && ! OrigArg . Flags . isInReg ( ) && ! OrigArg . Flags . isByVal ( ) && P<ISA_LIT>nputNum <= <NUM_LIT> ) { if ( CurOrigArg -> use_empty ( ) && ! Info -> isP<ISA_LIT>nputAllocated ( P<ISA_LIT>nputNum ) ) { Skipped . set ( i ) ; ++ P<ISA_LIT>nputNum ; continue ; } Info -> markP<ISA_LIT>nputAllocated ( P<ISA_LIT>nputNum ) ; if ( ! CurOrigArg -> use_empty ( ) ) Info -> markP<ISA_LIT>nputEnabled ( P<ISA_LIT>nputNum ) ; ++ P<ISA_LIT>nputNum ; } CCAssignFn * AssignFn = CCAssignFnForCall ( F . getCallingConv ( ) , false ) ; if ( ValEVT . isVector ( ) ) { EVT ElemVT = ValEVT . getVectorElementType ( ) ; if ( ! ValEVT . isSimple ( ) ) return false ; MVT ValVT = ElemVT . getSimpleVT ( ) ; bool Res = AssignFn ( i , ValVT , ValVT , CCValAssign :: Full , OrigArg . Flags , CCInfo ) ; if ( ! Res ) return false ; } else { MVT ValVT = ValEVT . getSimpleVT ( ) ; if ( ! ValEVT . isSimple ( ) ) return false ; bool Res = AssignFn ( i , ValVT , ValVT , CCValAssign :: Full , OrigArg . Flags , CCInfo ) ; if ( Res ) return false ; } } Function :: const_arg_iterator Arg = F . arg_begin ( ) ; if ( F . getCallingConv ( ) == CallingConv :: <ISA_LIT>_VS || F . getCallingConv ( )


<s> void LLVMInitialize<ISA_LIT>Target ( ) { RegisterTargetMachine < <ISA_LIT>TargetMachine >


<s> static bool isEmscriptenInvokeName ( StringRef Name ) { if ( Name . front ( ) == '"' && Name . back ( ) == '"' ) Name = Name . substr ( <NUM_LIT> , Name . size ( ) - <NUM_LIT> ) ; return Name . startswith ( <STR_LIT>


<s> void LLVMInitialize<ISA_LIT>TargetMC ( ) { RegisterMCAsmInfo < <ISA_LIT>MCAsmInfo > X ( The<ISA_LIT>Target ) ; TargetRegistry :: RegisterMCCodeGenInfo ( The<ISA_LIT>Target , create<ISA_LIT>MCCodeGenInfo ) ; TargetRegistry :: RegisterMCInstrInfo ( The<ISA_LIT>Target , create<ISA_LIT>MCInstrInfo ) ; TargetRegistry :: RegisterMCRegInfo ( The<ISA_LIT>Target , create<ISA_LIT>MCRegisterInfo ) ; TargetRegistry :: RegisterMCSubtargetInfo ( The<ISA_LIT>Target , create<ISA_LIT>MCSubtargetInfo ) ; TargetRegistry :: RegisterMCCodeEmitter ( The<ISA_LIT>Target , llvm :: create<ISA_LIT>MCCodeEmitter ) ; TargetRegistry :: RegisterMCAsmBackend ( The<ISA_LIT>Target , create<ISA_LIT>AsmBackend ) ; TargetRegistry :: RegisterMCInstPrinter ( The<ISA_LIT>Target , create<ISA_LIT>MCInstPrinter ) ; TargetRegistry :: RegisterELFStreamer ( The<ISA_LIT>Target , createMCStreamer ) ; TargetRegistry :: RegisterMCRelocationInfo ( The<ISA_LIT>Target ,


<s> void <ISA_LIT>InstPrinter :: printSetendOperand ( const MCInst * MI , unsigned OpNum ,


<s> return ( Kind == k_Register && Reg .


<s> AddValueSymbolsImpl ( getSubExpr ( ) ,


<s> inline vector signed short vec_madds ( vector signed short a1 , vector signed short a2 ,


<s> return gen_rtx_REG ( mode , <NUM_LIT>


<s> explicit <ISA_LIT>FastISel ( FunctionLoweringInfo & funcInfo , const TargetLibraryInfo * libInfo ) : FastISel ( funcInfo , libInfo ) , M ( const_cast < Module & > ( * funcInfo . Fn -> getParent ( ) ) ) , TM ( funcInfo . MF -> getTarget (

) ) , TII ( * TM . getSubtargetImpl ( ) -> getInstrInfo ( ) ) , TLI ( * TM . getSubtargetImpl ( ) -> getTargetLowering ( ) ) {


<s> bool <ISA_LIT>ELFTargetObjectFile :: isInSmallSection ( uint64_t


<s> result = build_variant_type_copy ( result ) ; add_builtin_type ( name , result ) ; return result


<s> unsigned ArgBytes = ArgSizeInBits >> <NUM_LIT> ; EVT ArgVT ; if ( ArgSizeInBits < VT . getSizeInBits ( ) ) { assert ( ! ArgType -> isFloatTy ( ) && <STR_LIT> ) ; ArgVT = <STR_LIT> ( ArgSizeInBits ) ; } else { ArgVT = VT ; } PointerType * PtrTy = PointerType :: get ( VT . getTypeForEVT ( * DAG . getContext ( ) ) , <STR_LIT> ) ; SDValue Arg = DAG . getExtLoad ( <STR_LIT> , DL , VT , DAG . getRoot ( ) , DAG . getConstant ( ParamOffsetBytes , <STR_LIT> )

, MachinePointerInfo ( UndefValue :: get ( PtrTy ) ) , ArgVT , false , false , ArgBytes ) ;


<s> void <ISA_LIT>MCCodeEmitter :: encodeInstruction ( const MCInst & MI , raw_ostream & OS , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { const MCInstrDesc & Desc = MCII . get ( MI . getOpcode ( ) ) ; unsigned Size = Desc . getSize ( ) ; assert ( Size > <NUM_LIT> && <STR_LIT> ) ; uint64_t BinaryOpCode = getBinaryCodeForInstr ( MI , Fixups , STI ) ; emitInstruction ( BinaryOpCode , Size , STI ,


<s> return ( ( TARGET_VX_ABI && typelist == <NUM_LIT> && VECTOR_TYPE_P ( TREE_TYPE ( val ) ) && ( funcdecl == NULL_TREE || ( TREE_CODE ( funcdecl ) == FUNCTION_DECL && DECL_BUILT_IN_CLASS ( funcdecl ) != BUILT_IN_MD ) ) )


<s> else if ( mode == CC_FPmode ) { cr_class = FCR_REGS ; p_new_cr = & frv_ifcvt . extra_fp_cr ; } else goto fail ; new_cr = * p_new_cr ; if ( ! new_cr ) { new_cr = * p_new_cr = frv_alloc_temp_reg ( & frv_ifcvt . tmp_reg , cr_class , CC_CCRmode , TRUE , TRUE ) ; if ( ! new_cr ) goto fail ; } if ( ce_info -> and_and_p ) { old_test = old_false ; test_expr = true_expr ; logical_func = ( GET_CODE ( old_true ) == EQ ) ? gen_andcr : gen_andncr ; * p_true = gen_rtx_NE ( CC_CCRmode , cr , const0_rtx ) ; * p_false = gen_rtx_EQ ( CC_CCRmode , cr , const0_rtx ) ; } else { old_test = old_false ; test_expr = false_expr ; logical_func = ( GET_CODE ( old_false ) == EQ ) ? gen_orcr : gen_orncr ; * p_true = gen_rtx_EQ ( CC_CCRmode , cr , const0_rtx ) ; * p_false = gen_rtx_NE ( CC_CCRmode , cr , const0_rtx ) ; } frv_ifcvt_add_insn ( ( * logical_func ) ( cr , cr , new_cr ) , BB_END ( bb ) , TRUE ) ; cc = XEXP ( test_expr , <NUM_LIT> ) ; compare = gen_rtx_fmt_ee ( GET_CODE ( test_expr ) , CC_CCRmode , cc , const0_rtx ) ; if_else = gen_rtx_IF_THEN_ELSE ( CC_CCRmode , old_test , compare , const0_rtx ) ; check_insn = gen_rtx_SET ( new_cr , if_else ) ; frv_ifcvt_add_insn ( check_insn , BB_END ( bb ) , TRUE ) ; if ( TARGET_DEBUG_COND_EXEC ) { fputs ( <STR_LIT> , stderr ) ; debug_rtx ( * p_true ) ; fputs ( <STR_LIT> , stderr ) ; debug_rtx ( * p_false ) ; } return ; fail : * p_true = * p_false = NULL_RTX ; if ( new_cr ) { CLEAR_HARD_REG_BIT ( frv_ifcvt . tmp_reg . regs , REGNO ( new_cr ) ) ; * p_new_cr = NULL_RTX ; } if ( TARGET_DEBUG_COND_EXEC ) fputs ( <STR_LIT>


<s> bool isT2MemRegOffset ( ) const { if ( ! isMem ( ) || ! Memory . OffsetRegNum || Memory . isNegative || Memory . Alignment != <NUM_LIT> ) return false ; if ( Memory . ShiftType == <STR_LIT> ) return


<s> Result . push_back ( StringSwitch < StringRef > ( CPU ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) ) ; break ; } case <STR_LIT> :: NoArch : break ; } return join ( Result . begin ( ) , Result . end ( ) ,


<s> if ( MI . isDebugInstr ( ) ) return false ; if ( MI . isTerminator ( ) || MI . isPosition ( ) ) return true ; MachineBasicBlock :: const_iterator I = MI ; while ( ++ I != MBB -> end ( ) && I


<s> if ( ! isTypeLegal ( Ty , VT ) ) return false ; unsigned OpC = <NUM_LIT> ; if ( VT == <STR_LIT> ) OpC = <STR_LIT> ; else if ( VT == <STR_LIT> ) OpC = <STR_LIT> ; else return false ; unsigned ResultReg = createResultReg ( TLI . getRegClassFor ( VT ) ) ; BuildMI ( MBB , DL , TII . get ( OpC ) , ResultReg ) . addImm ( CI -> getZExtValue ( ) == <NUM_LIT> ? - <NUM_LIT> : <NUM_LIT> ) ; UpdateValueMap ( & I , ResultReg ) ; return true ; } case <STR_LIT> : { DbgDeclareInst * DI = cast < DbgDeclareInst > ( & I ) ; <ISA_LIT>AddressMode AM ; assert ( DI -> getAddress ( ) && <STR_LIT> ) ; if ( ! <ISA_LIT>SelectAddress ( DI -> getAddress ( ) , AM ) ) return false ; const TargetInstrDesc & II = TII . get ( TargetOpcode :: DBG_VALUE ) ; addFullAddress ( BuildMI ( MBB , DL , II ) , AM ) . addImm ( <NUM_LIT> ) . addMetadata ( DI -> getVariable ( ) ) ; return true ; } case <STR_LIT> : { BuildMI ( MBB , DL , TII . get ( <STR_LIT> ) ) ; return true ; } case <STR_LIT> : case <STR_LIT> : { const Function * Callee = I . getCalledFunction ( ) ; const Type * RetTy = cast < StructType > ( Callee -> getReturnType ( ) ) -> getTypeAtIndex ( unsigned ( <NUM_LIT> ) ) ; EVT VT ; if ( ! isTypeLegal ( RetTy , VT ) ) return false ; Value * Op1 = I . getOperand ( <NUM_LIT> ) ; Value * Op2 = I . getOperand ( <NUM_LIT> ) ; unsigned Reg1 = getRegForValue ( Op1 ) ; unsigned Reg2 = getRegForValue ( Op2 ) ; if ( Reg1 == <NUM_LIT> || Reg2 == <NUM_LIT> ) return false ; unsigned OpC = <NUM_LIT> ; if ( VT == <STR_LIT> ) OpC = <STR_LIT> ; else if ( VT == <STR_LIT> ) OpC = <STR_LIT> ; else return false ; unsigned ResultReg = createResultReg ( TLI . getRegClassFor ( VT ) ) ; BuildMI ( MBB , DL , TII . get ( OpC ) , ResultReg ) . addReg ( Reg1 ) . addReg ( Reg2 ) ; unsigned DestReg1 = UpdateValueMap ( & I , ResultReg ) ; if ( DestReg1 != ResultReg ) ResultReg = DestReg1 + <NUM_LIT> ; else ResultReg = createResultReg ( TLI . getRegClassFor ( <STR_LIT> ) ) ; unsigned Opc = <STR_LIT> ; if ( I . getIntrinsicID ( ) == <STR_LIT>


<s> addPass ( create<ISA_LIT>GlobalBaseRegPass ( ) ) ; return false


<s> static bool expandOffset ( <ISA_LIT>AddressingMode & AM , bool IsBase , SDValue Op0 , ConstantSDNode * Op1 ) { int64_t TestOffset = AM . Offset + Op1 -> getSExtValue ( ) ; if ( selectOffset ( AM . OffR , TestOffset ) ) { AM . Base = Op0 ; AM . Offset =


<s> const TargetInstrInfo & TII = * MF . getTarget ( ) . getInstrInfo ( ) ; DebugLoc dl = MI . getDebugLoc ( ) ; bool LP64 = Subtarget . is<ISA_LIT>64 ( ) ; const TargetRegisterClass * G8RC = & <STR_LIT> ; const TargetRegisterClass * GPRC = & <STR_LIT> ; unsigned Reg = MF . getRegInfo ( ) . createVirtualRegister ( LP64 ? G8RC : GPRC ) ; unsigned DestReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; assert ( MI . definesRegister ( DestReg ) && <STR_LIT> ) ; addFrameReference ( BuildMI ( MBB , II , dl , TII . get ( LP64 ? <STR_LIT> : <STR_LIT> ) , Reg ) , FrameIndex ) ; BuildMI ( MBB , II , dl , TII . get ( TargetOpcode :: IMPLICIT_DEF ) , DestReg ) ; unsigned RegO = MF . getRegInfo ( ) . createVirtualRegister ( LP64 ? G8RC : GPRC ) ; BuildMI ( MBB , II , dl , TII . get ( LP64 ? <STR_LIT> : <STR_LIT> ) , RegO ) . addReg ( getCRFromCRBit ( DestReg ) ) ; unsigned ShiftBits = getEncodingValue ( DestReg ) ; BuildMI ( MBB , II , dl , TII . get ( LP64 ? <STR_LIT> : <STR_LIT> ) , RegO ) . addReg ( RegO , RegState :: Kill ) . addReg ( Reg , RegState :: Kill ) . addImm ( ShiftBits ? <NUM_LIT> - ShiftBits : <NUM_LIT> ) . addImm ( ShiftBits ) . addImm ( ShiftBits ) ; BuildMI ( MBB , II , dl , TII . get ( LP64 ? <STR_LIT> : <STR_LIT> ) , getCRFromCRBit ( DestReg ) ) . addReg ( RegO , RegState :: Kill )

. addReg ( getCRFromCRBit ( DestReg ) , RegState :: Implicit ) ;


<s> return SelectADDRsi_imp ( OpNode , Addr , Base , Offset , <STR_LIT>


<s> SDLoc DL ( Op ) ; assert ( LHS . getSimpleValueType ( ) . isInteger ( ) && <STR_LIT> ) ; <STR_LIT> CC = TranslateInteger<ISA_LIT>CC ( cast < CondCodeSDNode > ( Cond ) -> get ( ) ) ; EVT CarryVT = Carry . getValueType ( ) ; APInt NegOne = APInt :: getAllOnesValue ( CarryVT . getScalarSizeInBits ( ) ) ; Carry = DAG . getNode ( <STR_LIT> , DL , DAG . getVTList ( CarryVT , <STR_LIT> ) , Carry , DAG . getConstant ( NegOne , DL , CarryVT ) ) ; SDVTList VTs = DAG . getVTList ( LHS . getValueType ( ) , <STR_LIT> ) ; SDValue Cmp = DAG . getNode ( <STR_LIT> , DL , VTs , LHS , RHS , Carry . getValue ( <NUM_LIT> ) ) ; SDValue SetCC = getSETCC ( CC , Cmp . getValue ( <NUM_LIT> ) , DL , DAG ) ; if ( Op . getSimpleValueType ( ) == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , DL ,


<s> n = riscv_flatten_aggregate_field ( TREE_TYPE ( f ) , fields , n , pos , ignore_zero_width_bit_field_p ) ; } if ( n < <NUM_LIT> ) return - <NUM_LIT> ; } return n ; case ARRAY_TYPE : { HOST_WIDE_INT n_elts ; riscv_aggregate_field subfields [ <NUM_LIT> ] ; tree index = TYPE_DOMAIN ( type ) ; tree elt_size = TYPE_SIZE_UNIT ( TREE_TYPE ( type ) ) ; int n_subfields = riscv_flatten_aggregate_field ( TREE_TYPE ( type ) , subfields , <NUM_LIT> , offset , ignore_zero_width_bit_field_p ) ; if ( n_subfields <= <NUM_LIT> || ! COMPLETE_TYPE_P ( type ) || TREE_CODE ( TYPE_SIZE ( type ) ) != INTEGER_CST || ! index || ! TYPE_MAX_VALUE ( index ) || ! tree_fits_uhwi_p ( TYPE_MAX_VALUE ( index ) ) || ! TYPE_MIN_VALUE ( index ) || ! tree_fits_uhwi_p ( TYPE_MIN_VALUE ( index ) ) || ! tree_fits_uhwi_p ( elt_size ) ) return - <NUM_LIT> ; n_elts = <NUM_LIT> + tree_to_uhwi ( TYPE_MAX_VALUE ( index ) ) - tree_to_uhwi ( TYPE_MIN_VALUE ( index ) ) ; gcc_assert ( n_elts >= <NUM_LIT> ) ; for ( HOST_WIDE_INT i = <NUM_LIT> ; i < n_elts ; i ++ ) for ( int j = <NUM_LIT> ; j < n_subfields ; j ++ ) { if ( n >= <NUM_LIT> ) return - <NUM_LIT> ; fields [ n ] = subfields [ j ] ; fields [ n ++ ] . offset += i * tree_to_uhwi ( elt_size ) ; } return n ; } case COMPLEX_TYPE : { if ( n != <NUM_LIT> ) return - <NUM_LIT> ; HOST_WIDE_INT elt_size = GET_MODE_SIZE ( TYPE_MODE ( TREE_TYPE ( type ) ) ) ; if ( elt_size <= UNITS_PER_FP_ARG ) { fields [ <NUM_LIT> ] . type = TREE_TYPE ( type ) ; fields [ <NUM_LIT> ] . offset = offset ; fields [ <NUM_LIT> ] . type = TREE_TYPE ( type ) ; fields [ <NUM_LIT> ] . offset


<s> const DataLayout & DL = DAG . getDataLayout ( ) ; Type * Ty = MemVT . getTypeForEVT ( * DAG . getContext ( ) ) ; PointerType * PtrTy = PointerType :: get ( Ty , AMDGPUA<ISA_LIT> . CONSTANT_ADDRESS ) ; MachinePointerInfo PtrInfo ( UndefValue :: get ( PtrTy ) ) ; unsigned Align = DL . getABITypeAlignment ( Ty ) ; SDValue Ptr = lowerKernArgParameterPtr ( DAG , SL , Chain , Offset ) ; SDValue Load = DAG . getLoad ( MemVT , SL , Chain , Ptr , PtrInfo , Align , MachineMemOperand :: MONonTemporal | MachineMemOperand :: MODereferenceable | MachineMemOperand :: MOInvariant ) ; SDValue Val = convertArgType ( DAG , VT , MemVT , SL , Load


<s> int arc_write_ext_corereg ( rtx insn ) { subrtx_iterator :: array_type array ; FOR_EACH_SUBRTX ( iter , array , PATTERN ( insn ) , NONCONST ) { const_rtx x = * iter ; switch ( GET_CODE ( x ) ) { case SET : case POST_INC : case POST_DEC : case PRE_INC :


<s> if ( TREE_CODE ( arg ) != INTEGER_CST ) { warning ( OPT_Wattributes , <STR_LIT> <STR_LIT> , name ) ; * no_add_attrs = true ; } } if ( TREE_CODE ( * node ) == VAR_DECL ) { tree fntype = TREE_TYPE ( * node ) ; if ( fntype && TREE_CODE ( fntype ) == POINTER_TYPE ) { tree attrs = tree_cons ( get_identifier ( <STR_LIT> ) , NULL_TREE , TYPE_ATTRIBUTES ( fntype ) ) ; TYPE_ATTRIBUTES ( fntype ) = attrs ; } } } return


<s> x = F ( emit_insn ( x ) , <NUM_LIT> ) ; add_reg_note ( x , REG_INC


<s> static std :: string computeDataLayout ( const Triple & TT ) { std :: string Ret = TT . isArch64Bit ( ) ? <STR_LIT> : <STR_LIT> <STR_LIT> ; return Ret


<s> return MatchOperand_Success ; } if ( ! getLexer ( ) . is ( AsmToken :: Comma ) ) return MatchOperand_NoMatch ; getLexer ( ) . Lex ( ) ; Name = getLexer ( ) . getTok ( ) . getIdentifier ( ) ; if ( ! Name . consume_front ( <STR_LIT> ) ) return MatchOperand_NoMatch ; APInt Lmul ( <NUM_LIT> , Name , <NUM_LIT> ) ; if ( Lmul != <NUM_LIT> && Lmul != <NUM_LIT> && Lmul != <NUM_LIT> && Lmul != <NUM_LIT> ) return MatchOperand_NoMatch ; getLexer ( ) . Lex


<s> case E_SFmode : cum -> arg_words ++ ; if ( ! cum -> gp_reg_found && cum -> arg_number <= <NUM_LIT> ) cum -> fp_code += <NUM_LIT> << ( ( cum -> arg_number - <NUM_LIT> ) * <NUM_LIT> ) ; break ; case E_DFmode : cum -> arg_words += <NUM_LIT> ; if ( ! cum -> gp_reg_found && cum -> arg_number <= <NUM_LIT> ) cum -> fp_code += <NUM_LIT> << ( ( cum -> arg_number - <NUM_LIT> ) * <NUM_LIT> ) ; break ; case E_DImode : cum -> gp_reg_found = <NUM_LIT> ; cum -> arg_words += <NUM_LIT>


<s> sri -> icode = ( in_p ? CODE_FOR_reload_noff_load : CODE_FOR_reload_noff_store ) ; sri -> extra_cost = <NUM_LIT> ; return NO_REGS ; } if ( mode == QImode && ( MAYBE_MASK_CLASS_P ( rclass ) || ( ! TARGET_64BIT && ! in_p && INTEGER_CLASS_P ( rclass ) && MAYBE_NON_Q_CLASS_P ( rclass ) ) ) ) { int


<s> return D ( <STR_LIT> , MemARPSJ ( xy , yjs ) , MemARPSI ( xy


<s> bool use_movml = false ; if ( TARGET_SH2A ) { unsigned int count = <NUM_LIT> ; for ( i = FIRST_BANKED_REG ; i <= LAST_BANKED_REG ; i ++ ) if ( TEST_HARD_REG_BIT ( * mask , i ) ) count ++ ; else break ; if ( count == LAST_BANKED_REG - FIRST_BANKED_REG + <NUM_LIT> ) use_movml = true ; } if ( sh_cfun_resbank_handler_p ( ) ) ; else if ( use_movml ) { rtx x , mem , reg , set ; rtx sp_reg = gen_rtx_REG ( SImode , STACK_POINTER_REGNUM ) ; emit_insn ( gen_blockage ( ) ) ; x = gen_movml_push_banked ( sp_reg ) ; x = frame_insn ( x ) ; for ( i = FIRST_BANKED_REG ; i <= LAST_BANKED_REG ; i ++ ) { mem = gen_rtx_MEM ( SImode , plus_constant ( Pmode , sp_reg , i * <NUM_LIT> ) ) ; reg = gen_rtx_REG ( SImode , i ) ; add_reg_note ( x , REG_CFA_OFFSET , gen_rtx_SET ( mem , reg ) ) ; } set = gen_rtx_SET ( sp_reg , plus_constant ( Pmode , sp_reg , - <NUM_LIT> ) ) ; add_reg_note ( x , REG_CFA_ADJUST_CFA , set ) ; emit_insn ( gen_blockage ( )


<s> MVT MaskVT = <STR_LIT> ( <STR_LIT> , ContainerVT . getVectorElementCount ( ) ) ; Mask = convertToScalableVector ( MaskVT , Mask , DAG , Subtarget ) ; } } if ( ! VL ) VL = getDefaultVLOps ( VT , ContainerVT , DL , DAG , Subtarget ) . second ; unsigned IntID = IsUnmasked ? <STR_LIT> : <STR_LIT> ; SmallVector < SDValue , <NUM_LIT> > Ops { Chain , DAG . getTargetConstant ( IntID , DL , XLenVT ) } ; Ops . push_back ( Val ) ; Ops . push_back ( BasePtr ) ; if ( ! IsUnmasked ) Ops . push_back ( Mask ) ; Ops . push_back ( VL ) ; return DAG . getMemIntrinsicNode ( <STR_LIT> , DL , DAG . getVTList ( <STR_LIT>


<s> return new <ISA_LIT>BranchCoalescing (


<s> return DAG . getNode ( minMaxOpcToMin3Max3Opc ( Opc ) , DL , N -> getValueType ( <NUM_LIT> ) , Op0 . getOperand ( <NUM_LIT> ) , Op0 . getOperand ( <NUM_LIT> ) , Op1 ) ; } if ( Op1 . getOpcode ( ) == Opc && Op1 . hasOneUse ( ) ) { SDLoc DL ( N ) ; return DAG . getNode ( minMaxOpcToMin3Max3Opc ( Opc ) , DL , N -> getValueType ( <NUM_LIT> ) , Op0 , Op1 . getOperand ( <NUM_LIT> ) , Op1 . getOperand


<s> static bool insn_can_be_in_speculative_p ( rtx insn ATTRIBUTE_UNUSED , ds_t ds


<s> bool <ISA_LIT>PassConfig :: addInstSelector (


<s> for ( i = half_elts , j = <NUM_LIT> ; j < half_elts ; ++ i , ++ j ) XVECEXP ( par , <NUM_LIT> , i ) = GEN_INT ( j ) ; rtx sel = gen_rtx_VEC_SELECT ( mode , src_reg , par ) ; SET_SRC ( body ) = sel ; INSN_CODE ( insn ) = - <NUM_LIT> ; df_insn_rescan ( insn


<s> rtx x = DF_REF_REG ( def ) ; if ( REG_P ( x ) && REGNO ( x ) ==


<s> static inline const MachineInstrBuilder & addOffset ( const MachineInstrBuilder & MIB , int Offset ) { return MIB . addImm (


<s> MachineBasicBlock * loopMBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * exitMBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; F -> insert ( It , loopMBB ) ; F -> insert ( It , exitMBB ) ; exitMBB -> splice ( exitMBB -> begin ( ) , BB , std :: next ( MachineBasicBlock :: iterator ( MI ) ) , BB -> end ( ) ) ; exitMBB -> transferSuccessorsAndUpdatePHIs ( BB ) ; MachineRegisterInfo & RegInfo = F -> getRegInfo ( ) ; unsigned TmpReg = ( ! BinOpcode ) ? incr : RegInfo . createVirtualRegister ( is64bit ? ( const TargetRegisterClass * ) & <STR_LIT> : ( const TargetRegisterClass * ) & <STR_LIT> ) ; BB -> addSuccessor ( loopMBB ) ; BB = loopMBB ; BuildMI ( BB , dl , TII -> get ( is64bit ? <STR_LIT> : <STR_LIT> ) , dest ) . addReg ( ptrA ) . addReg ( ptrB ) ; if ( BinOpcode ) BuildMI ( BB , dl , TII -> get ( BinOpcode ) , TmpReg ) . addReg ( incr ) . addReg ( dest ) ; BuildMI ( BB , dl , TII -> get ( is64bit ? <STR_LIT> : <STR_LIT> ) ) . addReg ( TmpReg ) . addReg ( ptrA ) . addReg ( ptrB ) ; BuildMI ( BB , dl , TII -> get ( <STR_LIT> ) ) . addImm ( <STR_LIT> ) . addReg ( <STR_LIT> ) .


<s> __inline__ static double sh_media_FMOV_QD ( long long mm ) { double res ; __asm__ ( <STR_LIT> : <STR_LIT> ( res ) : <STR_LIT> ( mm ) ) ; return


<s> bool <ISA_LIT>MCAsmBackend :: fixupNeedsRelaxation ( const MCFixup & Fixup , uint64_t Value , const MCRelaxableFragment *

Fragment , const MCAsmLayout & Layout ) const {


<s> EVT VT = Store -> getMemoryVT ( ) ; if ( VT == <STR_LIT> ) { return DAG . getTruncStore ( Store -> getChain ( ) , DL , DAG . getSExtOrTrunc ( Store -> getValue ( ) , DL , <STR_LIT> ) , Store -> getBasePtr ( ) , <STR_LIT> , Store -> getMemOperand ( ) ) ; } assert ( VT . isVector ( ) && Store -> getValue ( ) . getValueType ( ) . getScalarType ( ) == <STR_LIT> ) ; unsigned AS = Store -> getAddressSpace ( ) ; if ( ! allowsMemoryAccess ( * DAG . getContext ( ) , DAG . getDataLayout ( ) , VT , AS , Store -> getAlignment ( ) ) ) { return expandUnalignedStore ( Store , DAG ) ; } MachineFunction & MF = DAG . getMachineFunction ( ) ; <ISA_LIT>MachineFunctionInfo * MFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; if ( AS == AMDGPUA<ISA_LIT> . FLAT_ADDRESS ) AS = MFI -> hasFlatScratchInit ( ) ? AMDGPUA<ISA_LIT> . PRIVATE_ADDRESS : AMDGPUA<ISA_LIT> . GLOBAL_ADDRESS ; unsigned NumElements = VT . getVectorNumElements ( ) ; if ( AS == AMDGPUA<ISA_LIT> . GLOBAL_ADDRESS || AS == AMDGPUA<ISA_LIT> . FLAT_ADDRESS ) { if ( NumElements > <NUM_LIT> ) return SplitVectorStore ( Op , DAG ) ; return SDValue ( ) ; } else if ( AS == AMDGPUA<ISA_LIT> . PRIVATE_ADDRESS ) { switch ( Subtarget -> getMaxPrivateElementSize ( ) ) { case <NUM_LIT> : return scalarizeVectorStore ( Store , DAG ) ; case <NUM_LIT> : if ( NumElements > <NUM_LIT> ) return SplitVectorStore ( Op , DAG ) ; return SDValue ( ) ; case <NUM_LIT> : if ( NumElements > <NUM_LIT> ) return SplitVectorStore ( Op , DAG ) ; return SDValue


<s> if ( TARGET_OMIT_LEAF_FRAME_POINTER ) flag_omit_frame_pointer = <NUM_LIT> ; if ( bfin_lib_id_given && ! TARGET_ID_SHARED_LIBRARY ) error ( <STR_LIT> ) ; if ( TARGET_ID_SHARED_LIBRARY ) flag_pic = <NUM_LIT> ; flag_schedule_insns =


<s> static MCInstrInfo * create<ISA_LIT>MCInstrInfo ( ) { MCInstrInfo * X = new


<s> if ( ! Check ( S , DecodeGPRwithZRRegisterClass ( Inst , Rm , Address , Decoder ) ) ) return MCDisassembler :: Fail ; } else { fc = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> | fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) | fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ; unsigned Qm = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> | fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; if ( ! Check ( S , DecodeMQPRRegisterClass ( Inst , Qm , Address , Decoder ) ) ) return MCDisassembler :: Fail ; } if ( ! Check ( S , predicate_decoder ( Inst , fc , Address , Decoder ) )


<s> if ( MO . isImm ( ) ) O << ( unsigned short int ) MO . getImm ( ) ; else printOperand ( MI , opNum , O


<s> CCValAssign & VA = ArgLocs [ i ] ; SDValue ArgValue = OutVals [ i ] ; <STR_LIT> Flags = Outs [ i ] . Flags ; switch ( VA . getLocInfo ( ) ) { case CCValAssign :: Full : break ; case CCValAssign :: Indirect : { SDValue SpillSlot = DAG . CreateStackTemporary ( Outs [ i ] . ArgVT ) ; int FI = cast < FrameIndexSDNode > ( SpillSlot ) -> getIndex ( ) ; MemOpChains . push_back ( DAG . getStore ( Chain , DL , ArgValue , SpillSlot , MachinePointerInfo :: getFixedStack ( MF , FI ) ) ) ; unsigned ArgIndex = Outs [ i ] . OrigArgIndex ; assert ( Outs [ i ] . PartOffset == <NUM_LIT> ) ; while ( i + <NUM_LIT> != e && Outs [ i + <NUM_LIT> ] . OrigArgIndex == ArgIndex ) { SDValue PartValue = OutVals [ i + <NUM_LIT> ] ; unsigned PartOffset = Outs [ i + <NUM_LIT> ] . PartOffset ; SDValue Address = DAG . getNode ( <STR_LIT> , DL , PtrVT , SpillSlot , DAG . getIntPtrConstant ( PartOffset , DL ) ) ; MemOpChains . push_back ( DAG . getStore ( Chain , DL , PartValue , Address , MachinePointerInfo :: getFixedStack ( MF , FI ) ) ) ; ++ i ; } ArgValue = SpillSlot ; break ; } default : llvm_unreachable ( <STR_LIT> ) ; } if ( Flags . isByVal ( ) ) ArgValue = ByValArgs [ j ++ ] ; if ( VA . isRegLoc ( ) ) { RegsToPass . push_back ( std :: make_pair ( VA . getLocReg ( ) , ArgValue ) ) ; } else { assert ( VA . isMemLoc ( ) && <STR_LIT> ) ; if ( ! StackPtr . getNode ( ) ) StackPtr = DAG . getCopyFromReg ( Chain , DL , <STR_LIT> , PtrVT ) ; SDValue Address = DAG . getNode ( <STR_LIT> , DL , PtrVT , StackPtr , DAG . getIntPtrConstant ( VA . getLocMemOffset ( ) , DL ) ) ; MemOpChains . push_back ( DAG . getStore ( Chain , DL , ArgValue , Address , MachinePointerInfo ( ) ) ) ; } } if ( ! MemOpChains . empty ( ) ) Chain = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , MemOpChains ) ; SDValue Glue ; for ( auto & Reg : RegsToPass ) { Chain = DAG . getCopyToReg ( Chain , DL , Reg . first , Reg . second , Glue ) ; Glue = Chain . getValue ( <NUM_LIT>


<s> if ( Fractional ) { Lmul = <NUM_LIT> - Lmul ; Lmul = <NUM_LIT> << Lmul ; O << <STR_LIT> << Lmul ; } else { Lmul = <NUM_LIT> << Lmul ; O << <STR_LIT> << Lmul ; } bool TailAgnostic = Imm & <NUM_LIT> ; bool MaskedoffAgnostic = Imm & <NUM_LIT> ; if ( TailAgnostic ) O << <STR_LIT> ; else O << <STR_LIT> ; if ( MaskedoffAgnostic ) O << <STR_LIT> ; else O << <STR_LIT>


<s> vec_float4 msb = ( vec_float4 ) ( ( vec_uint4 ) { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ; return ( ( qword ) ( vec_cmpgt ( vec_andc ( ( vec_float4 ) ( a ) , msb

) , vec_andc ( ( vec_float4 ) ( b ) , msb ) ) ) ) ;


<s> bool <ISA_LIT>InstrInfo :: isVOPC ( uint16_t


<s> if ( optab_handler ( movmisalign_optab , mode ) == CODE_FOR_nothing ) return false ; if ( misalignment == - <NUM_LIT> ) { if ( rs6000_vector_alignment_reachable ( type


<s> u . i [ <NUM_LIT> ] = b ; u . i [ <NUM_LIT> ] = c ; u . i [ <NUM_LIT> ] = d ; return u .


<s> static int loongarch_zero_extend_cost ( rtx op ) { if ( MEM_P ( op ) ) return <NUM_LIT> ; return COSTS_N_INSNS (


<s> if ( ! tree_fits_uhwi_p ( nelts_minus_one ) ) return DOESNT_MATTER ; unsigned HOST_WIDE_INT count = tree_to_uhwi ( nelts_minus_one ) ; if ( count > MAX_PIECES ) return DOESNT_MATTER ; count += <NUM_LIT> ; if ( count * element_info . pieces . length ( ) > MAX_PIECES ) return DOESNT_MATTER ; poly_uint64 element_bytes ; if ( ! poly_int_tree_p ( TYPE_SIZE_UNIT ( TREE_TYPE ( type ) ) , & element_bytes ) ) gcc_unreachable ( ) ; gcc_assert ( ! element_info . pieces . is_empty ( ) ) ; for ( unsigned int i = <NUM_LIT> ; i < count ; ++ i ) for ( unsigned int j = <NUM_LIT> ; j < element_info . pieces . length ( ) ; ++ j ) { piece p = element_info . pieces [ j ] ; p . offset += i * element_bytes ; add_piece ( p


<s> unsigned Rt = fieldFromInstruction ( Val , <NUM_LIT> , <NUM_LIT> ) ; unsigned Rt2 = fieldFromInstruction ( Val , <NUM_LIT> , <NUM_LIT> ) ; if ( ( cop & ~ <NUM_LIT> ) == <NUM_LIT> ) return MCDisassembler :: Fail ; if ( Rt == Rt2 ) S = MCDisassembler :: SoftFail ; Inst . addOperand ( MCOperand :: CreateImm (


<s> switch ( V . getOpcode ( ) ) { default : return SDValue ( ) ; case <STR_LIT> : { if ( ! isSplatVector ( V . getNode ( ) ) ) return SDValue ( ) ; Ld = V . getOperand ( <NUM_LIT> ) ; if ( ! Ld -> hasNUsesOfValue ( VT . getVectorNumElements ( ) , <NUM_LIT> ) ) return SDValue ( ) ; break ; } case <STR_LIT> : { ShuffleVectorSDNode * SVOp = cast < ShuffleVectorSDNode > ( Op ) ; if ( ( ! SVOp -> isSplat ( ) ) || SVOp -> getMaskElt ( <NUM_LIT> ) != <NUM_LIT> ) return SDValue ( ) ; SDValue Sc = Op . getOperand ( <NUM_LIT> ) ; if ( Sc . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; Ld = Sc . getOperand ( <NUM_LIT> ) ; if ( ! Sc . hasOneUse ( ) || ! Ld . hasOneUse ( ) ) return SDValue ( ) ; break ; } } if ( ! <STR_LIT> ( Ld . getNode ( ) ) ) return SDValue ( ) ; bool Is256 = VT .


<s> static bool classof ( const MCExpr * E ) { return E -> getKind ( ) == MCExpr ::


<s> <ISA_LIT>ExpandSDMA ( ) : MachineFunctionPass ( ID ) { initialize<ISA_LIT>ExpandSDMAPass ( * PassRegistry :: getPassRegistry (


<s> FeatureBitset FB = ComputeAvailableFeatures ( STI . ToggleFeature ( OldMode . flip ( mode ) ) ) ; setAvailableFeatures ( FB ) ; assert ( FeatureBitset ( { mode } ) == ( STI .


<s> rtx p = PATTERN ( i ) ; return GET_CODE ( p ) == SET && GET_CODE ( XEXP


<s> assert ( TargetRegisterInfo :: isPhysicalRegister ( Reg ) ) ; for ( MCRegAliasIterator AI ( Reg , & TRI , false ) ; AI . isValid ( ) ; ++ AI ) AS . insert ( RegisterRef ( * AI ) ) ; return AS


<s> case <STR_LIT> : case <STR_LIT> : if ( isVShiftLImm ( N -> getOperand ( <NUM_LIT> ) , VT , false , Cnt ) ) { VShiftOpc = <STR_LIT> ; break ; } if ( isVShiftRImm ( N -> getOperand ( <NUM_LIT> ) , VT , false , true , Cnt ) ) { VShiftOpc = ( IntNo == <STR_LIT> ? <STR_LIT> : <STR_LIT> ) ; break ; } return SDValue ( ) ; case <STR_LIT> : case <STR_LIT> : if ( isVShiftRImm ( N -> getOperand ( <NUM_LIT> ) , VT , false , true , Cnt ) ) break ; return SDValue ( ) ; case <STR_LIT> : case <STR_LIT> : if ( isVShiftLImm ( N -> getOperand ( <NUM_LIT> ) , VT , false , Cnt ) ) break ; return SDValue ( ) ; case <STR_LIT> : if ( isVShiftLImm ( N -> getOperand ( <NUM_LIT> ) , VT , false , Cnt ) ) break ; llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( isVShiftRImm ( N -> getOperand ( <NUM_LIT> ) , VT , true , true , Cnt ) ) break ; llvm_unreachable ( <STR_LIT> <STR_LIT> ) ; default : llvm_unreachable ( <STR_LIT> ) ; } switch ( IntNo ) { case <STR_LIT> : case <STR_LIT> : break ; case <STR_LIT> : VShiftOpc = <STR_LIT> ; break ; case <STR_LIT> : VShiftOpc = <STR_LIT> ; break ; case <STR_LIT> : VShiftOpc = <STR_LIT> ; break ; case <STR_LIT> : VShiftOpc = <STR_LIT> ; break ; case <STR_LIT> : VShiftOpc = <STR_LIT> ; break ; case <STR_LIT> : VShiftOpc = <STR_LIT> ; break ; case <STR_LIT> : VShiftOpc = <STR_LIT> ; break ; case <STR_LIT> : VShiftOpc = <STR_LIT> ; break ; case <STR_LIT> : VShiftOpc = <STR_LIT> ; break ; case <STR_LIT> : VShiftOpc = <STR_LIT> ; break ; case <STR_LIT> : VShiftOpc = <STR_LIT> ; break ; case <STR_LIT> : VShiftOpc = <STR_LIT>


<s> static uint32_t getIntInlineImmEncoding ( IntTy Imm ) { if ( Imm >= <NUM_LIT> && Imm <= <NUM_LIT> ) return <NUM_LIT> + Imm ; if ( Imm >= - <NUM_LIT> && Imm <= - <NUM_LIT> ) return <NUM_LIT> + std :: abs ( Imm ) ; return <NUM_LIT>


<s> } if ( n_const == n_elts ) const_vec = gen_rtx_CONST_VECTOR ( mode , XVEC ( vals , <NUM_LIT> ) ) ; } else gcc_unreachable ( ) ; if ( const_vec != NULL_RTX && aarch64_simd_valid_immediate ( const_vec , NULL ) ) return const_vec ; else if ( ( const_dup = aarch64_simd_dup_constant ( vals ) ) != NULL_RTX ) return const_dup ; else if ( const_vec != NULL_RTX ) return const_vec ; else return NULL_RTX


<s> int GCNHazardRecognizer :: checkSoftClauseHazards ( MachineInstr * MEM ) { if ( ! ST . isXNACKEnabled ( ) ) return <NUM_LIT> ; bool IsSMRD = TII . isSMRD ( * MEM ) ; resetClause ( ) ; for ( MachineInstr * MI : EmittedInstrs ) { if ( ! MI ) break ; if ( IsSMRD ? breaksSMEMSoftClause ( MI ) : breaksVMEMSoftClause ( MI ) ) break ; addClauseInst ( * MI ) ; } if ( ClauseDefs . none ( ) ) return <NUM_LIT> ; if ( MEM -> mayStore ( ) ) return <NUM_LIT> ; addClauseInst ( * MEM )


<s> } else if ( ExternalSymbolSDNode * S = dyn_cast < ExternalSymbolSDNode > ( N0 ) ) { AM . ES = S -> getSymbol ( ) ; } else if ( JumpTableSDNode * J = dyn_cast < JumpTableSDNode > ( N0 ) ) { AM . JT = J -> getIndex ( ) ; } else { AM . BlockAddr = cast < BlockAddressSDNode > ( N0 ) -> getBlockAddress ( ) ; } return


<s> if ( GV ) { if ( Optional < ConstantRange > CR = GV -> getAbsoluteSymbolRange ( ) ) { if ( CR -> getUnsignedMax ( ) . ult ( <NUM_LIT> ) ) return <STR_LIT> ; else return <STR_LIT> ; } } if ( TM . shouldAssumeDSOLocal ( M , GV ) ) return classifyLocalReference ( GV ) ; if ( isTargetCOFF ( ) ) { if ( GV -> hasDLLImportStorageClass ( ) ) return <STR_LIT> ; return <STR_LIT> ; } if ( isOSWindows ( ) ) return <STR_LIT> ; if ( is64Bit ( ) ) { if ( TM . getCodeModel ( ) == CodeModel :: Large ) return isTargetELF ( ) ? <STR_LIT> : <STR_LIT> ; return


<s> assert ( isMyDuty ( pSrcFragRef ) ) ; std :: string sym_name ( <STR_LIT> ) ; sym_name . append ( name ( ) ) . append ( llvm :: utohexstr ( pIsland . numOfStubs ( ) ) ) . append ( <STR_LIT> ) . append ( pIsland . name ( ) ) ; LDSymbol * stub_sym = pBuilder . AddSymbol < IRBuilder :: Force , IRBuilder :: Unresolve > ( sym_name , ResolveInfo :: NoType , ResolveInfo :: Define , ResolveInfo :: Local , size ( ) , initSymValue ( ) , FragmentRef :: Create ( * this , initSymValue ( ) ) , ResolveInfo :: Default ) ; setSymInfo ( stub_sym -> resolveInfo ( ) ) ; FragmentRef * target = FragmentRef :: Create ( * pSrcFragRef . frag ( ) , pSrcFragRef . offset ( ) + getErratumInsnOffset ( ) + <ISA_LIT>InsnHelpers :: InsnSize ) ; ResolveInfo * target_info = pBuilder . CreateLocalSymbol ( * target ) ; fixup_iterator it = fixup_begin ( ) ; Relocation * reloc = Relocation :: Create ( ( * it ) -> type ( ) , * ( FragmentRef :: Create ( * this , ( * it ) -> offset ( ) ) ) , ( * it ) -> addend ( ) ) ; reloc -> setSymInfo ( target_info ) ; std :: unique_ptr < unsigned [ ] > code ( new unsigned [ getErratumSequenceSize ( ) / <NUM_LIT> ] ) ; pSrcFragRef . memcpy ( code . get ( ) , getErratumSequenceSize ( ) , <NUM_LIT> ) ; reloc -> target ( ) = code [ getErratumInsnOffset ( ) / <ISA_LIT>InsnHelpers :: InsnSize ] ; pIsland . addRelocation ( * reloc ) ; ++ it ; reloc = Relocation :: Create ( ( * it ) -> type ( ) , * ( FragmentRef :: Create ( * this , ( * it ) -> offset ( ) ) ) , ( * it ) -> addend ( ) ) ; reloc -> setSymInfo ( target_info ) ; reloc -> target ( ) = <ISA_LIT>InsnHelpers :: buildBranchInsn ( ) ; pIsland . addRelocation ( *


<s> Result = readJmpInstruction ( Bytes , Extra ) ; if ( Result == MCDisassembler :: Fail ) return MCDisassembler :: Fail ; if ( isFakePass ) { Instr . setOpcode ( <ISA_LIT>II :: spuJMPR ) ; int64_t * point = ( int64_t * ) Extra . Address ; * point = Extra . Imm ; return MCDisassembler :: Success ; } } if ( isFakePass ) { return MCDisassembler :: Success ; } Result = decodeInstruction ( DecoderTableScalarSlot64 , * SPUSubInst , InsnSPU , Address , this , STI ) ; if ( Result == MCDisassembler :: Fail ) return MCDisassembler :: Fail ; Instr . addOperand ( MCOperand :: createInst ( SPUSubInst ) ) ; MCInst * VPUSubInst = new ( getContext ( ) ) MCInst ; VPUSubInst -> setFlags ( FlagVPU ) ; Result = decodeInstruction ( DecoderTableVectorSlot64 , * VPUSubInst , InsnVPU , Address , this , STI ) ; if ( Result == MCDisassembler :: SoftFail ) Result = decodeInstruction ( DecoderTableVectorSlot64 , * VPUSubInst , InsnVPU , Address , this , STI ) ; if ( Result == MCDisassembler :: Fail ) return MCDisassembler :: Fail ; Instr . addOperand ( MCOperand :: createInst ( VPUSubInst ) ) ; MCInst * LDSubInst = new ( getContext ( ) ) MCInst ; LDSubInst -> setFlags ( FlagLDU ) ; Result = decodeInstruction ( DecoderTableLoadSlot64 , * LDSubInst , InsnLoad , Address , this , STI ) ; if ( Result == MCDisassembler :: Fail ) return MCDisassembler :: Fail ; Instr . addOperand ( MCOperand :: createInst ( LDSubInst ) ) ; MCInst * STSubInst = new ( getContext ( )


<s> assert ( V1 . getSimpleValueType ( ) == <STR_LIT> && <STR_LIT> ) ; assert ( V2 . getSimpleValueType ( ) == <STR_LIT> && <STR_LIT> ) ; ShuffleVectorSDNode * SVOp = cast < ShuffleVectorSDNode > ( Op ) ; ArrayRef < int > Mask = SVOp -> getMask ( ) ; assert ( Mask . size ( ) == <NUM_LIT> && <STR_LIT> ) ; assert ( Subtarget -> hasBWI ( ) &&


<s> static DecodeStatus DecodeThumbBROperand ( MCInst & Inst , unsigned Val , uint64_t Address , const void * Decoder ) { if ( ! tryAddingSymbolicOperand ( Address , Address + SignExtend32 < <NUM_LIT> > ( Val << <NUM_LIT> ) + <NUM_LIT> , true , <NUM_LIT> , Inst , Decoder ) ) Inst . addOperand ( MCOperand :: createImm ( SignExtend32 < <NUM_LIT> > ( Val << <NUM_LIT> ) ) ) ; return MCDisassembler ::


<s> if ( ! G . hasInitializer ( ) && G . hasExternalLinkage ( ) ) { if ( G . getValueType ( ) -> isSized ( ) ) { uint16_t Size = M . getDataLayout ( ) . getTypeAllocSize ( G . getValueType ( ) ) ; OutStreamer -> emitELFSize ( getSymbol ( & G ) , MCConstantExpr :: create ( Size , OutContext ) ) ; } } } if ( const NamedMDNode * Named = M . getNamedMetadata ( <STR_LIT> ) ) { for ( const Metadata * MD : Named -> operands ( ) ) { const MDTuple * Tuple = dyn_cast < MDTuple > ( MD ) ; if ( ! Tuple || Tuple -> getNumOperands ( ) != <NUM_LIT> ) continue ; const MDString * Name = dyn_cast < MDString > ( Tuple -> getOperand ( <NUM_LIT> ) ) ; const MDString * Contents = dyn_cast < MDString > ( Tuple -> getOperand ( <NUM_LIT> ) ) ; if ( ! Name || ! Contents ) continue ; OutStreamer -> PushSection ( ) ; std :: string SectionName = ( <STR_LIT> + Name -> getString ( ) ) . str ( ) ; MCSectionWasm * mySection = OutContext . getWasmSection ( SectionName , SectionKind :: getMetadata ( ) ) ; OutStreamer -> SwitchSection (


<s> else if ( IDVal == <STR_LIT> ) parseDirectiveCPU ( Loc ) ; else if ( IDVal == <STR_LIT> ) parseDirectiveTLSDescCall ( Loc ) ; else if ( IDVal == <STR_LIT> || IDVal == <STR_LIT> ) parseDirectiveLtorg ( Loc ) ; else if ( IDVal == <STR_LIT> ) parseDirectiveUnreq ( Loc ) ; else if ( IDVal == <STR_LIT>


<s> if ( <STR_LIT> . contains ( DestReg ) ) return <STR_LIT> ; } if ( <STR_LIT> . contains ( DestReg ) && <STR_LIT> . contains ( SrcReg ) ) return HasAVX512 ? <STR_LIT> : ( HasAVX ? <STR_LIT> : <STR_LIT> ) ; if ( <STR_LIT> . contains ( DestReg ) && <STR_LIT> . contains ( SrcReg )


<s> if ( RegNo > <NUM_LIT> ) return MCDisassembler :: Fail ; if ( ( RegNo & <NUM_LIT> ) || RegNo == <NUM_LIT> ) S =


<s> errs ( ) << <STR_LIT> << ABIName << <STR_LIT> ; } else if ( ABIName . startswith ( <STR_LIT> ) && IsRV64 ) { errs ( ) << <STR_LIT> <STR_LIT> ; TargetABI = ABI_Unknown ; } else if ( ABIName . startswith ( <STR_LIT> ) && ! IsRV64 ) { errs ( ) << <STR_LIT>


<s> static void mips_sim_wait_regs ( struct mips_sim


<s> if ( ! ( ( Subtarget . hasSSE1 ( ) && ( VT == <STR_LIT> || VT == <STR_LIT> ) ) || ( Subtarget . hasSSE2 ( ) && ( VT == <STR_LIT> || VT == <STR_LIT> ) ) || ( Subtarget . hasAVX ( ) && ( VT == <STR_LIT> || VT == <STR_LIT> ) ) ) ) return SDValue ( ) ; if ( ! VT . isVector ( ) && DAG . getMachineFunction ( ) . getFunction ( ) -> optForMinSize ( ) ) return SDValue ( ) ; SDValue Op0 = N -> getOperand ( <NUM_LIT>


<s> bool IsWin64 = Subtarget . isCallingConvWin64 ( MF . getFunction ( ) . getCallingConv ( ) ) ; unsigned FixedObject = getFixedObjectSize ( MF , AFI , IsWin64 , false ) ; unsigned FPAdjust = isTargetDarwin ( MF ) ? <NUM_LIT> : AFI -> getCalleeSavedStackSize ( MF .


<s> if ( ( val > - <NUM_LIT> ) && ( val < <NUM_LIT> ) ) fprintf ( file , <STR_LIT> ,


<s> SDValue Extract = LHS -> getOperand ( <NUM_LIT> ) ; if ( Extract -> getOpcode ( ) != <STR_LIT> || Extract -> getValueType ( <NUM_LIT> ) != N -> getValueType ( <NUM_LIT> ) || Extract -> getConstantOperandVal ( <NUM_LIT> ) != <NUM_LIT> ) return SDValue ( ) ; SDValue InnerSetCC = Extract -> getOperand ( <NUM_LIT> ) ; if ( InnerSetCC -> getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; SDValue InnerPred = InnerSetCC . getOperand ( <NUM_LIT> ) ; if ( Pred . getOpcode ( ) == <STR_LIT> && InnerPred . getOpcode ( ) == <STR_LIT> && Pred . getConstantOperandVal ( <NUM_LIT> ) == InnerPred . getConstantOperandVal ( <NUM_LIT> ) && Pred ->

getConstantOperandVal ( <NUM_LIT> ) >= <STR_LIT> && Pred -> getConstantOperandVal ( <NUM_LIT> ) <= <STR_LIT> ) return Extract ;


<s> const InlineAsmIdentifierInfo & getIdentifierInfo


<s> int64_t Imm ; <ISA_LIT>MCExpr :: VariantKind VK = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ; if ( ! isImm ( ) || evaluateConstantImm ( getImm (


<s> bool <ISA_LIT>InstrInfo :: getMemOpBaseRegImmOfs ( MachineInstr & LdSt , unsigned & BaseReg , int64_t & Offset , const TargetRegisterInfo * TRI ) const { unsigned AccessSize = <NUM_LIT>


<s> Value * <ISA_LIT>IREmitter :: visitPRELOAD ( const SDNode


<s> void <ISA_LIT>InstPrinter :: printS16X4ImmOperand ( const MCInst * MI , unsigned OpNo , raw_ostream & O ) { if ( MI -> getOperand ( OpNo ) . isImm ( ) ) O << ( short ) ( MI -> getOperand ( OpNo ) . getImm


<s> BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addMBB ( FBB ) ; count ++ ; return count ; } return InsertBranchAtInst ( MBB , MBB . end ( ) , TBB , Cond


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; const MCConstantExpr * MCE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; assert ( MCE && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: CreateImm ( MCE ->


<s> SwitchToCU ( DL . getScope ( MF . getFunction ( ) -> getContext ( ) ) ) ; SwitchToLine ( DL . getLine


<s> Entry . Ty = IntPtrTy ; Args . push_back ( Entry ) ; Entry . Node = Size ; Entry . Ty = IntPtrTy ; Entry . isSExt = false ; Args . push_back ( Entry ) ; if ( Src . getValueType ( ) . bitsGT ( <STR_LIT> ) ) Src = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Src ) ; else Src = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Src ) ; Entry . Node = Src ; Entry . Ty = Type :: getInt32Ty ( * DAG . getContext ( ) ) ; Entry . isSExt =


<s> void eraseMatchingBitGroups ( function_ref < bool ( const BitGroup & ) > F ) { erase_if ( BitGroups ,


<s> assert ( Cond . size ( ) == <NUM_LIT> && <STR_LIT> ) ; <STR_LIT> CC = static_cast < <STR_LIT> > ( Cond [ <NUM_LIT> ] . getImm ( ) ) ; Cond [ <NUM_LIT> ] . setImm ( getOppositeCondition


<s> MCSymbolELF * Symbol = cast < MCSymbolELF > ( getStreamer ( ) . getContext ( ) . getOrCreateSymbol ( GlobalName ) ) ; Symbol -> setType ( ELF :: STT_OBJECT ) ; Symbol -> setBinding ( ELF :: STB_LOCAL


<s> default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return


<s> unsigned Opcode = Val -> getOpcode ( ) ; if ( Opcode == <STR_LIT> ) { if ( Val -> getOperand ( <NUM_LIT> ) . getValueType ( ) == <STR_LIT> ) return false ; CanNegate = true ; return true ; } if ( Depth > <NUM_LIT> ) return false ; if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) { SDValue O0 = Val -> getOperand ( <NUM_LIT> ) ; SDValue O1 = Val -> getOperand ( <NUM_LIT> ) ; bool CanNegateL ; if ( ! isConjunctionDisjunctionTree ( O0 , CanNegateL , Depth + <NUM_LIT> ) ) return false ; bool CanNegateR ; if ( ! isConjunctionDisjunctionTree ( O1 , CanNegateR , Depth + <NUM_LIT> ) ) return false ; if ( Opcode == <STR_LIT> ) { if ( ! CanNegateL && ! CanNegateR ) return false ; CanNegate = CanNegateL && CanNegateR ; } else { bool NeedsNegOutL = O0 -> getOpcode ( ) == <STR_LIT> ; bool NeedsNegOutR = O1 -> getOpcode ( ) == <STR_LIT> ; if ( NeedsNegOutL && NeedsNegOutR ) return false ; CanNegate = false ; } return true


<s> return ELF :: R_<ISA_LIT>_64_32 ; case FK_Data_8 : return ELF :: R_<ISA_LIT>_64_64 ; case FK_Data_4 : if ( const MCSymbolRefExpr * A = Target . getSymA ( ) ) { if ( A -> getSymbol ( ) . isTemporary ( ) )


<s> initQueues ( TopRoots , BotRoots ) ; bool IsTopNode = false ; while ( true ) { DEBUG ( dbgs ( ) << <STR_LIT> ) ; SUnit * SU = SchedImpl -> pickNode ( IsTopNode ) ; if ( ! SU ) break ; if ( ! checkSchedLimit ( ) ) break ; scheduleMI ( SU , IsTopNode ) ; updateQueues ( SU , IsTopNode ) ; SchedImpl -> schedNode ( SU , IsTopNode ) ; } assert ( CurrentTop == CurrentBottom && <STR_LIT> ) ; placeDebugValues ( ) ; DEBUG ( { unsigned BBNum = begin ( ) -> getParent ( ) -> getNumber ( ) ; dbgs ( ) << <STR_LIT> << BBNum << <STR_LIT> ; dumpSchedule (


<s> SDValue FIN = DAG . getFrameIndex ( GPRIdx , PtrVT ) ; for ( unsigned i = FirstVariadicGPR ; i < NumGPRArgRegs ; ++ i ) { unsigned VReg = MF . addLiveIn ( GPRArgRegs [ i ] , & <STR_LIT> ) ; SDValue Val = DAG . getCopyFromReg ( Chain , DL , VReg , <STR_LIT> ) ; SDValue Store = DAG . getStore ( Val . getValue ( <NUM_LIT> ) , DL , Val , FIN , Subtarget -> isTargetWindows ( ) ? MachinePointerInfo :: getFixedStack ( DAG . getMachineFunction ( ) , GPRIdx , ( i - FirstVariadicGPR ) * <NUM_LIT> ) : MachinePointerInfo :: getStack ( DAG . getMachineFunction ( ) , i * <NUM_LIT> ) ) ; MemOps . push_back ( Store ) ; FIN = DAG . getNode ( <STR_LIT> , DL , PtrVT , FIN , DAG . getConstant ( <NUM_LIT> , DL , PtrVT ) ) ; } } FuncInfo -> setVarArgsGPRIndex ( GPRIdx ) ; FuncInfo -> setVarArgsGPRSize ( GPRSaveSize ) ; if ( Subtarget -> hasFPARMv8 ( ) && ! Subtarget -> isTargetWindows ( ) ) { static const MCPhysReg FPRArgRegs [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; static const unsigned NumFPRArgRegs = array_lengthof ( FPRArgRegs ) ; unsigned FirstVariadicFPR = CCInfo . getFirstUnallocated ( FPRArgRegs ) ; unsigned FPRSaveSize = <NUM_LIT> * ( NumFPRArgRegs - FirstVariadicFPR ) ; int FPRIdx = <NUM_LIT> ; if ( FPRSaveSize != <NUM_LIT> ) { FPRIdx = MFI . CreateStackObject ( FPRSaveSize , <NUM_LIT> , false ) ; SDValue FIN = DAG . getFrameIndex ( FPRIdx , PtrVT ) ; for ( unsigned i = FirstVariadicFPR ; i < NumFPRArgRegs ; ++ i ) { unsigned VReg = MF . addLiveIn ( FPRArgRegs [ i ] , & <STR_LIT> ) ; SDValue Val = DAG . getCopyFromReg ( Chain , DL , VReg ,


<s> vld1q_p16 ( const poly16_t * __a ) { return ( poly16x8_t ) __builtin_neon_vld1v8hi ( ( const __builtin_neon_hi *


<s> static bool doesDispFit ( <ISA_LIT>ISelAddressMode & AM , int64_t Val ) { if ( ! AM . isDispAddrType ( ) ) return false ; return isIntN ( AM . getDispSize ( ) ,


<s> if ( FoundScan ) break ; } assert ( FoundScan ) ; DEBUG ( { StringRef PP = ( PV . M ? <STR_LIT> : <STR_LIT> ) ; if ( ! PV . Inv ) dbgs ( ) << <STR_LIT> << PP << <STR_LIT> ; else dbgs ( ) << <STR_LIT> << PP << <STR_LIT> << PP << <STR_LIT> ; dbgs ( ) << <STR_LIT> << * PV . Res << <STR_LIT> << * PV . P << <STR_LIT> ; if ( PV . M ) dbgs ( ) << <STR_LIT> << * PV . M << <STR_LIT> ; dbgs ( ) << <STR_LIT> << * PV . Q << <STR_LIT> ; dbgs ( ) << <STR_LIT> << PV . IterCount << <STR_LIT> ; } ) ; BasicBlock :: iterator At ( EntryB -> getTerminator ( ) ) ; Value * PM = generate ( At , PV ) ; if ( PM == nullptr ) return false ; if ( PM -> getType ( ) != PV . Res -> getType ( ) ) PM = IRBuilder < > ( & * At ) . CreateIntCast ( PM , PV . Res -> getType ( ) , false ) ; PV . Res -> replaceAllUsesWith ( PM ) ; PV . Res -> eraseFromParent ( ) ; return true


<s> DEBUG ( errs ( ) << <STR_LIT> ; Node -> dump ( CurDAG ) ; errs ( ) << <STR_LIT> ) ; Node -> setNodeId ( - <NUM_LIT> ) ; return ; } EVT VT = Node -> getValueType ( <NUM_LIT> ) ; switch ( Node -> getOpcode ( ) ) { default : break ; ( void ) VT ; } SelectCode ( Node


<s> bool hasMOPS ( ) const { return HasMOPS


<s> SwitchToSection ( TAI -> SectionForGlobal ( GVar ) ) ; if ( C -> isNullValue ( ) && ! GVar -> hasSection ( ) && ( GVar -> hasLocalLinkage ( ) || GVar -> hasExternalLinkage ( ) || GVar -> isWeakForLinker ( ) ) && TAI -> SectionKindForGlobal ( GVar ) != SectionKind :: RODataMergeStr ) { if ( Size == <NUM_LIT> ) Size = <NUM_LIT> ; if ( GVar -> hasExternalLinkage ( ) ) { O << <STR_LIT> << name << '\n' ; O << <STR_LIT> << name << <STR_LIT> << Size << <STR_LIT> << Align ; } else if ( GVar -> hasLocalLinkage ( ) ) { O << TAI -> getLCOMMDirective ( ) << name << ',' << Size << ',' << Align ; } else if ( ! GVar -> hasCommonLinkage ( ) ) { O << <STR_LIT> << name << '\n' << TAI -> getWeakDefDirective ( ) << name << '\n' ; EmitAlignment ( Align , GVar ) ; O << name << <STR_LIT> ; if ( VerboseAsm ) { O << <STR_LIT> << TAI -> getCommentString ( ) << <STR_LIT> ; PrintUnmangledNameSafely ( GVar , O ) ; } O << '\n' ; EmitGlobalConstant ( C ) ; return ; } else { O << <STR_LIT> << name << ',' << Size ; if ( Subtarget . isDarwin9 ( ) ) O << ',' << Align ; } if ( VerboseAsm ) { O << <STR_LIT> << TAI -> getCommentString ( ) << <STR_LIT> ; PrintUnmangledNameSafely ( GVar , O ) ; O << <STR_LIT> ; } O <<


<s> int named_size = <NUM_LIT> ; if ( ! TYPE_NO_NAMED_ARGS_STDARG_P ( TREE_TYPE ( current_function_decl ) ) ) named_size = GET_MODE_SIZE ( SImode ) * ( * cum - FT32_R0 ) + GET_MODE_SIZE ( arg . mode ) ; if ( named_size < <NUM_LIT> ) *


<s> static int avr_signal_function_p ( tree func


<s> SmallVector < SDValue , <NUM_LIT> > Ops ; for ( unsigned i = <NUM_LIT> , e = N -> getNumOperands ( ) ; i != e ; ++ i ) Ops . push_back ( N -> getOperand ( i ) ) ; Ops . push_back


<s> else ofs += <NUM_LIT> ; } if ( to == SP_REGNO ) { ofs += m32c_pushm_popm ( PP_justcount ) ; ofs += get_frame_size ( ) ; } if ( TARGET_A24 ) ofs = ( ofs + <NUM_LIT>


<s> extern __inline long __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) __TM_is_failure_persistent ( void * const TM_buff ) { texasru_t texasru = * _TEXASRU_PTR ( TM_buff )


<s> if ( to_type == NO_REG_TYPE || from_type == NO_REG_TYPE ) return false ; if ( ( to_type == PSEUDO_REG_TYPE && from_type == PSEUDO_REG_TYPE ) || ( to_type == PSEUDO_REG_TYPE && IS_STD_REG_TYPE ( from_type ) ) || ( from_type == PSEUDO_REG_TYPE && IS_STD_REG_TYPE ( to_type ) ) ) return true ; if ( to_type == from_type && IS_STD_REG_TYPE ( to_type


<s> return ( x * ( y >> <NUM_LIT> ) + ( y


<s> <ISA_LIT>AsmParser :: OperandMatchResultTy <ISA_LIT>AsmParser :: parsePCRel ( SmallVectorImpl < MCParsedAsmOperand * > & Operands , int64_t MinVal , int64_t MaxVal ) { MCContext & Ctx = getContext ( ) ; MCStreamer & Out = getStreamer ( ) ; const MCExpr * Expr ; SMLoc StartLoc = Parser . getTok ( ) . getLoc ( ) ; if ( getParser ( ) . parseExpression ( Expr ) ) return MatchOperand_NoMatch ; if ( const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( Expr ) ) { int64_t Value = CE -> getValue ( ) ; if ( ( Value & <NUM_LIT> ) || Value < MinVal || Value > MaxVal ) { Error ( StartLoc , <STR_LIT> ) ; return MatchOperand_ParseFail ; } MCSymbol * Sym = Ctx . CreateTempSymbol ( ) ; Out . EmitLabel ( Sym ) ; const MCExpr * Base = MCSymbolRefExpr :: Create ( Sym , MCSymbolRefExpr :: VK_None , Ctx ) ; Expr = Value == <NUM_LIT> ? Base : MCBinaryExpr :: CreateAdd ( Base , Expr , Ctx ) ; } SMLoc EndLoc = SMLoc :: getFromPointer ( Parser . getTok ( ) . getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; Operands . push_back ( <ISA_LIT>Operand :: createImm ( Expr , StartLoc , EndLoc ) ) ; return MatchOperand_Success


<s> MachineRegisterInfo & MRI = MIRBuilder . getMF ( ) . getRegInfo ( ) ; static const unsigned OpcTable [ <NUM_LIT> ] [ <NUM_LIT> ] { { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } } ; bool Is32Bit = ( MRI . getType ( LHS . getReg ( ) ) . getSizeInBits ( ) == <NUM_LIT> ) ; auto ImmFns = selectArithImmed ( RHS ) ; unsigned Opc = OpcTable [ Is32Bit ] [ ImmFns . hasValue ( ) ] ; Register ZReg = Is32Bit ? <STR_LIT> : <STR_LIT> ; auto CmpMI = MIRBuilder . buildInstr ( Opc , { ZReg } , { LHS } ) ; if ( ImmFns ) { for ( auto & RenderFn : * ImmFns ) RenderFn ( CmpMI ) ; } else { CmpMI . addUse ( RHS . getReg ( ) ) ; } constrainSelectedInstRegOperands ( * CmpMI , TII , TRI , RBI ) ; return & * CmpMI


<s> static bool addToListsIfDependent ( MachineInstr & MI , DenseSet < unsigned > & RegDefs , DenseSet < unsigned > & PhysRegUses , SmallVectorImpl < MachineInstr * > & Insts ) { for ( MachineOperand & Use : MI . operands ( ) ) { if ( Use . isReg ( ) && ( ( Use . readsReg ( ) && RegDefs . count ( Use . getReg ( ) ) ) || ( Use . isDef ( ) && RegDefs . count ( Use . getReg ( ) ) ) || ( Use . isDef ( ) && TargetRegisterInfo :: isPhysicalRegister ( Use . getReg ( ) ) && PhysRegUses . count ( Use . getReg ( ) ) ) ) ) { Insts . push_back ( & MI ) ; addDefsUsesToList ( MI , RegDefs , PhysRegUses ) ; return true


<s> if ( imm < <NUM_LIT> && imm > std :: numeric_limits < int > :: min ( ) ) { SDLoc DL ( N ) ; RHS = DAG . getConstant ( - imm , DL , <STR_LIT> ) ; unsigned Opcode = ( N -> getOpcode ( ) == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; return DAG . getNode ( Opcode , DL , N -> getVTList ( ) ,


<s> } } } riscv_save_restore_reg ( word_mode , regno , offset , fn ) ; } offset = ( cfun -> machine -> frame . fp_sp_offset - sp_offset ) . to_constant ( ) ; for ( unsigned int regno = FP_REG_FIRST ; regno <= FP_REG_LAST ; regno ++ ) if ( BITSET_P ( cfun -> machine -> frame . fmask , regno - FP_REG_FIRST ) ) { bool handle_reg = ! cfun -> machine -> reg_is_wrapped_separately [ regno ] ; machine_mode mode = TARGET_DOUBLE_FLOAT ? DFmode : SFmode ; if ( handle_reg ) riscv_save_restore_reg ( mode , regno , offset , fn ) ; offset -= GET_MODE_SIZE ( mode ) . to_constant


<s> LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; MRI = & F . getRegInfo ( ) ; TRI = F . getRegInfo ( ) . getTargetRegisterInfo ( ) ; RCI . runOnMachineFunction ( F ) ; for ( auto & MBB


<s> initializeRegionInfoPass ( * PassRegistry ::


<s> lowerBRCOND ( SDValue Op , SelectionDAG