<s> if ( getGeneration ( ) >= <ISA_LIT>Subtarget :: VOLCANIC_ISLANDS ) return <NUM_LIT> ; if ( getGeneration ( ) == <ISA_LIT>Subtarget :: SEA_ISLANDS )


<s> Subtarget = & TM . getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( Subtarget -> in<ISA_LIT>16Mode ( ) ) return


<s> bool <ISA_LIT>AtomicExpandPass :: shouldExpand ( Instruction * Inst ) { if ( AtomicRMWInst * AI = dyn_cast < AtomicRMWInst > ( Inst ) ) return shouldExpandAtomicRMW ( AI ) ; if ( StoreInst * SI = dyn_cast < StoreInst > ( Inst ) ) return shouldExpandStore ( SI ) ; return


<s> error ( <STR_LIT> ) ; return NULL_RTX ; } c = INTVAL ( arg ) ; if ( HOST_BITS_PER_WIDE_INT > <NUM_LIT> ) { if ( c < <NUM_LIT> ) { error ( <STR_LIT> ) ; return NULL_RTX ; } } emit_insn ( gen_delay_cycles_start ( arg ) ) ; if ( c > <NUM_LIT> * <NUM_LIT> + CYCX ( <NUM_LIT> , <NUM_LIT> ) ) { n = c ; if ( c >= <NUM_LIT> * <NUM_LIT> + CYCX ( <NUM_LIT> , <NUM_LIT> ) ) { i = <NUM_LIT> ; c -= CYCX ( <NUM_LIT> , <NUM_LIT> ) + <NUM_LIT> * <NUM_LIT> ; i += c / <NUM_LIT> ; c %= <NUM_LIT> ; if ( ( unsigned long long ) i > <NUM_LIT> ) { error ( <STR_LIT> ) ; return NULL_RTX ; } } else { i = ( c - CYCX ( <NUM_LIT> , <NUM_LIT> ) ) / <NUM_LIT> ; c -= CYCX ( <NUM_LIT> , <NUM_LIT> ) + i * <NUM_LIT> ; } if ( cg_magic_constant ( i & <NUM_LIT> ) ) c ++ ; if ( cg_magic_constant ( ( i >> <NUM_LIT> ) & <NUM_LIT> ) ) c ++ ; if ( msp430x ) emit_insn ( gen_delay_cycles_32x ( GEN_INT ( i ) , GEN_INT ( n - c ) ) ) ; else emit_insn ( gen_delay_cycles_32 ( GEN_INT ( i ) , GEN_INT ( n - c


<s> unsigned FrontendSize = <NUM_LIT> ; void * Decl = nullptr ; bool IsGlobalLV = false ; if ( Info . isKind ( InlineAsmIdentifierInfo :: IK_Var ) ) { FrontendSize = Info . Var . Type * <NUM_LIT> ; Decl = Info . Var . Decl ; IsGlobalLV = Info . Var . IsGlobalLV ; } if ( IsGlobalLV && ( BaseReg || IndexReg ) ) { Operands . push_back ( <STR_LIT> ( getPointerWidth ( ) , Disp , Start , End , Size , Identifier , Decl , FrontendSize ) ) ; return false ; } BaseReg = BaseReg ? BaseReg : <NUM_LIT> ; Operands . push_back ( <STR_LIT> ( getPointerWidth ( ) , SegReg , Disp , BaseReg , IndexReg , Scale , Start , End , Size , <STR_LIT> , Identifier , Decl , FrontendSize ) ) ; return false


<s> void setDesc ( const MCInstrDesc & mcid ) { MCID


<s> BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , IntReg ) . addReg ( SrcReg ) ; BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addReg ( IntReg , getKillRegState ( true ) ) . addReg ( <STR_LIT> ) . addFrameIndex ( FI ) . addImm ( Offset ) . addMemOperand ( MMO ) ; return ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { Opc = <STR_LIT> ; MachineFrameInfo & MFI = MBB . getParent ( ) -> getFrameInfo ( ) ; MFI . setObjectAlignment ( FI , Subtarget . getCapAlignment ( ) ) ; } else { llvm_unreachable ( <STR_LIT> ) ; } BuildMI ( MBB , I , DL , get ( Opc ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addReg ( <STR_LIT> ) . addFrameIndex ( FI ) . addImm ( Offset ) . addMemOperand ( MMO ) ; return ; } if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = <STR_LIT> ; else if ( TRI -> isTypeLegalForClass ( * RC , <STR_LIT> ) ) Opc = <STR_LIT> ; else if ( TRI -> isTypeLegalForClass ( * RC , <STR_LIT> ) || TRI -> isTypeLegalForClass ( * RC , <STR_LIT> ) ) Opc = <STR_LIT> ; else if ( TRI -> isTypeLegalForClass ( * RC , <STR_LIT> ) || TRI -> isTypeLegalForClass ( * RC , <STR_LIT> ) ) Opc = <STR_LIT> ; else if ( TRI -> isTypeLegalForClass ( * RC , <STR_LIT> ) || TRI -> isTypeLegalForClass ( * RC , <STR_LIT> ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { Opc = <STR_LIT> ; MachineFrameInfo & MFI = MBB . getParent ( ) -> getFrameInfo ( ) ; MFI . setObjectAlignment ( FI , Subtarget . getCapAlignment ( ) ) ; BuildMI ( MBB , I , DL , get ( Opc ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addFrameIndex ( FI ) . addImm ( Offset ) . addMemOperand ( MMO ) . addReg ( <STR_LIT> ) ; return ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) )


<s> assert ( ( Kind == k_Register || Kind == k_Memri ) && <STR_LIT>


<s> bool isSoloInstruction ( MachineInstr * MI ) { if ( TII -> isVector ( * MI ) ) return true ; if ( ! TII -> isALUInstr ( MI -> getOpcode ( )


<s> static const MCPhysReg F64Regs [ ] = { <STR_LIT> , <STR_LIT> } ; return CC_<ISA_LIT>O32 ( ValNo , ValVT , LocVT , LocInfo , ArgFlags , State , F64Regs


<s> const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( ! ( ( Subtarget . hasSSE1 ( ) && VT == <STR_LIT> ) || ( Subtarget . hasSSE2 ( ) && VT == <STR_LIT> ) || ( VT . isVector ( ) && TLI . isTypeLegal ( VT ) ) ) ) return SDValue ( ) ; SDValue Op0 = N -> getOperand ( <NUM_LIT> ) ; SDValue Op1 = N -> getOperand ( <NUM_LIT> ) ; SDLoc DL ( N ) ; auto MinMaxOp = N -> getOpcode ( ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; if ( DAG . getTarget ( ) . Options . NoNaNsFPMath || N -> getFlags ( ) . hasNoNaNs ( ) ) return DAG . getNode ( MinMaxOp , DL , VT , Op0 , Op1 , N -> getFlags ( ) ) ; if ( ! VT . isVector ( ) && DAG . getMachineFunction ( ) . getFunction (

) . optForMinSize ( ) ) return SDValue ( ) ;


<s> } AttrEmitter -> MaybeSwitchVendor ( <STR_LIT> ) ; std :: string CPUString = Subtarget -> getCPUString ( ) ; if ( CPUString == <STR_LIT> || Subtarget -> isCortexA8 ( ) ) { AttrEmitter -> EmitTextAttribute ( <STR_LIT> , <STR_LIT> ) ; AttrEmitter -> EmitAttribute ( <STR_LIT> , <STR_LIT> ) ; AttrEmitter -> EmitAttribute ( <STR_LIT> , <STR_LIT> ) ; AttrEmitter -> EmitAttribute ( <STR_LIT> , <STR_LIT> ) ; AttrEmitter -> EmitAttribute ( <STR_LIT> , <STR_LIT> ) ; } else if ( CPUString == <STR_LIT> ) { AttrEmitter -> EmitAttribute ( <STR_LIT> , <STR_LIT> ) ; AttrEmitter -> EmitAttribute ( <STR_LIT> , <STR_LIT> ) ; AttrEmitter -> EmitAttribute ( <STR_LIT> , <STR_LIT> ) ; } else if ( CPUString == <STR_LIT> ) { AttrEmitter -> EmitAttribute ( <STR_LIT> , <STR_LIT> ) ; AttrEmitter -> EmitAttribute ( <STR_LIT> , <STR_LIT> ) ; AttrEmitter -> EmitAttribute ( <STR_LIT> , <STR_LIT> ) ; } if ( Subtarget -> hasNEON ( ) && emitFPU ) { AttrEmitter -> EmitTextAttribute ( <STR_LIT> , <STR_LIT> ) ; emitFPU = false ; } if ( Subtarget -> hasVFP3 ( ) ) { AttrEmitter -> EmitAttribute ( <STR_LIT> , <STR_LIT> ) ; if ( emitFPU ) AttrEmitter -> EmitTextAttribute ( <STR_LIT> , <STR_LIT> ) ; } else if ( Subtarget -> hasVFP2 ( ) ) { AttrEmitter -> EmitAttribute ( <STR_LIT> , <STR_LIT> ) ; if ( emitFPU ) AttrEmitter -> EmitTextAttribute ( <STR_LIT> , <STR_LIT> ) ; } if ( Subtarget -> hasNEON ( ) ) { AttrEmitter -> EmitAttribute ( <STR_LIT> , <STR_LIT> ) ; } if ( ! UnsafeFPMath ) { AttrEmitter -> EmitAttribute ( <STR_LIT> , <STR_LIT> ) ; AttrEmitter -> EmitAttribute ( <STR_LIT> , <STR_LIT> ) ; } if ( NoInfsFPMath && NoNaNsFPMath ) AttrEmitter -> EmitAttribute ( <STR_LIT> , <STR_LIT> ) ; else AttrEmitter -> EmitAttribute ( <STR_LIT> , <STR_LIT> ) ; AttrEmitter -> EmitAttribute ( <STR_LIT> , <NUM_LIT> ) ; AttrEmitter -> EmitAttribute ( <STR_LIT> ,


<s> assert ( ( SubMode == ia || SubMode == db ) && <STR_LIT> ) ; return ( ( int ) SubMode << <NUM_LIT> ) | ( ( int ) WB << <NUM_LIT>


<s> SDValue Op1 = U -> getOperand ( <NUM_LIT> ) ; if ( ConstantSDNode * Imm = dyn_cast < ConstantSDNode > ( Op1 ) ) if ( Imm -> getAPIntValue ( ) . isSignedIntN ( <NUM_LIT> ) ) return false ; if ( Op1 . getOpcode ( ) == <STR_LIT> ) { SDValue Val = Op1 . getOperand ( <NUM_LIT> ) ; if ( Val . getOpcode ( ) == <STR_LIT> ) return false ; } } } } return


<s> return isMesa3DOS ( ) && <STR_LIT> ( MF .

getFunction ( ) -> getCallingConv ( ) ) ;


<s> if ( TYPE_ARG_TYPES ( funtype ) == NULL_TREE && type != NULL_TREE && ! AGGREGATE_TYPE_P ( type ) ) { if ( mode == SFmode ) mode = DFmode ; mode = arg_promotion ( mode ) ; } return mode


<s> return <STR_LIT> ( GV ) || ( <STR_LIT> ( GV ) && GV -> hasSection ( ) && isAgentAllocationSection ( GV -> getSection


<s> case LSHIFTRT : if ( ! CONST_INT_P ( XEXP ( src , <NUM_LIT> ) ) || ! IN_RANGE ( INTVAL ( XEXP ( src , <NUM_LIT> ) ) , <NUM_LIT> , GET_MODE_BITSIZE ( mode ) - <NUM_LIT> ) ) return false ; break ; case SMAX : case SMIN : case UMAX : case UMIN : if ( ( mode == DImode && ! TARGET_AVX512VL ) || ( mode == SImode && ! TARGET_SSE4_1 ) ) return false ; case AND : case IOR : case XOR : case PLUS : case MINUS : if ( ! REG_P ( XEXP ( src , <NUM_LIT> ) ) && ! MEM_P ( XEXP ( src , <NUM_LIT> ) ) && ! CONST_INT_P ( XEXP ( src , <NUM_LIT> ) ) ) return false ; if ( GET_MODE ( XEXP ( src , <NUM_LIT> ) ) != mode && ! CONST_INT_P ( XEXP ( src , <NUM_LIT> ) ) ) return false ; if ( GET_CODE ( src ) != AND || GET_CODE ( XEXP ( src , <NUM_LIT> ) ) != NOT ) break ; src = XEXP ( src , <NUM_LIT> ) ; case NOT


<s> int frame_allocated = <NUM_LIT> ; int i ; if ( save_blink ) { reg = gen_rtx_REG ( Pmode , RETURN_ADDR_REGNUM ) ; frame_allocated += frame_save_reg ( reg , offset ) ; offset = <NUM_LIT> ; } if ( gmask ) for ( i = GMASK_LEN ; i >= <NUM_LIT> ; i -- ) { machine_mode save_mode = SImode ; if ( TARGET_LL64 && ( ( i - <NUM_LIT> ) % <NUM_LIT> == <NUM_LIT> ) && ( ( gmask & ( <NUM_LIT> << i ) ) != <NUM_LIT> ) && ( ( gmask & ( <NUM_LIT> << ( i - <NUM_LIT> ) ) ) != <NUM_LIT> ) ) { save_mode = DImode ; -- i ; } else if ( ( gmask & ( <NUM_LIT> << i ) ) == <NUM_LIT> ) continue ; reg = gen_rtx_REG (


<s> void <ISA_LIT>NaClRewritePass :: AlignAllJumpTargets ( MachineFunction & MF ) { MachineJumpTableInfo * jt_info = MF . getJumpTableInfo ( ) ; if ( jt_info ) { const std :: vector < MachineJumpTableEntry > & JT = jt_info -> getJumpTables ( ) ; for ( unsigned i = <NUM_LIT> ; i < JT . size ( ) ; ++ i ) { std :: vector < MachineBasicBlock * > MBBs = JT [ i ] . MBBs ; for ( unsigned j = <NUM_LIT> ; j < MBBs . size ( ) ; ++ j ) { MBBs [ j ] -> setAlignment ( <NUM_LIT> ) ; } } } for ( MachineFunction :: iterator I = MF . begin ( ) , E = MF . end ( ) ; I != E ; ++ I ) { MachineBasicBlock & MBB = *


<s> MCAsmParser & Parser = getParser ( ) ; SMLoc SS = getLoc ( ) ; const AsmToken & TokE = Parser . getTok ( ) ; if ( TokE . isNot ( AsmToken :: Identifier ) ) return MatchOperand_NoMatch ; if ( ! TokE . getString ( ) . equals_lower ( <STR_LIT> ) || Parser . getLexer ( ) . peekTok ( ) . isNot ( AsmToken :: Hash ) ) return MatchOperand_NoMatch ; Operands . push_back ( <ISA_LIT>Operand :: CreateToken ( <STR_LIT> , false , SS , getContext ( ) ) ) ; Parser . Lex ( ) ; Parser . Lex ( ) ; const MCExpr * ImmVal ; SS = getLoc ( ) ; if ( Parser . parseExpression ( ImmVal ) ) return MatchOperand_ParseFail ; const MCConstantExpr * MCE = dyn_cast < MCConstantExpr > ( ImmVal ) ; if ( ! MCE ) return MatchOperand_ParseFail ; int Val = MCE -> getValue ( ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateImm ( MCConstantExpr :: create ( Val , getContext ( ) ) , SS , getLoc (


<s> EmitComment ( ) ; OutStreamer -> emitIntValueInHexWithPadding ( ( SecondHalfOfMandatoryField & <NUM_LIT> ) >> <NUM_LIT> , <NUM_LIT> ) ; uint32_t GPRSaved = <NUM_LIT> ; unsigned GPRBegin = Subtarget -> is<ISA_LIT>64 ( ) ? <STR_LIT> : <STR_LIT> ; unsigned GPREnd = Subtarget -> is<ISA_LIT>64 ( ) ? <STR_LIT> : <STR_LIT> ; for ( unsigned Reg = GPRBegin ; Reg <= GPREnd ; ++ Reg ) { if ( MRI . isPhysRegModified ( Reg ) ) { GPRSaved = GPREnd - Reg + <NUM_LIT> ; break ; } } SecondHalfOfMandatoryField |= ( GPRSaved << TracebackTable :: GPRSavedShift ) & TracebackTable :: GPRSavedMask ; GENBOOLCOMMENT ( <STR_LIT> , SecondHalfOfMandatoryField , HasVectorInfo ) ; GENBOOLCOMMENT ( <STR_LIT> , SecondHalfOfMandatoryField , HasExtensionTable ) ; GENVALUECOMMENT ( <STR_LIT> , SecondHalfOfMandatoryField , GPRSaved ) ; EmitComment ( ) ; OutStreamer -> emitIntValueInHexWithPadding ( ( SecondHalfOfMandatoryField & <NUM_LIT> ) >> <NUM_LIT> , <NUM_LIT> ) ; uint32_t NumberOfFixedPara = FI -> getFixedParamNum ( ) ; SecondHalfOfMandatoryField |= ( NumberOfFixedPara << TracebackTable :: NumberOfFixedParmsShift ) & TracebackTable :: NumberOfFixedParmsMask ; GENVALUECOMMENT ( <STR_LIT> , SecondHalfOfMandatoryField , NumberOfFixedParms ) ; EmitComment ( ) ; OutStreamer -> emitIntValueInHexWithPadding ( ( SecondHalfOfMandatoryField & <NUM_LIT> ) >> <NUM_LIT> , <NUM_LIT> ) ; SecondHalfOfMandatoryField |= TracebackTable :: HasParmsOnStackMask ; uint32_t NumberOfFPPara = FI -> getFloatingPointParamNum ( ) ; SecondHalfOfMandatoryField |= ( NumberOfFPPara << TracebackTable :: NumberOfFloatingPointParmsShift ) & TracebackTable :: NumberOfFloatingPointParmsMask ; GENVALUECOMMENT ( <STR_LIT> , SecondHalfOfMandatoryField , NumberOfFloatingPointParms ) ; GENBOOLCOMMENT ( <STR_LIT> , SecondHalfOfMandatoryField , HasParmsOnStack ) ; EmitComment ( ) ; OutStreamer -> emitIntValueInHexWithPadding ( SecondHalfOfMandatoryField & <NUM_LIT> , <NUM_LIT> ) ; if ( NumberOfFixedPara || NumberOfFPPara ) { assert ( ( SecondHalfOfMandatoryField & TracebackTable :: HasVectorInfoMask ) == <NUM_LIT> && <STR_LIT> ) ; uint32_t ParaType = FI -> getParameterType ( ) ; CommentOS << <STR_LIT> << XCOFF :: parseParmsType ( ParaType , NumberOfFixedPara + NumberOfFPPara ) ; EmitComment ( ) ; OutStreamer -> emitIntValueInHexWithPadding ( ParaType , sizeof ( ParaType ) ) ; } OutStreamer -> AddComment ( <STR_LIT> ) ; if ( FirstHalfOfMandatoryField & TracebackTable :: HasTraceBackTableOffsetMask ) { MCSymbol * FuncSectSym = getObjFileLowering ( ) . getFunctionEntryPointSymbol ( & ( MF -> getFunction ( ) ) , TM ) ; OutStreamer -> emitAbsoluteSymbolDiff ( FuncEnd , FuncSectSym , <NUM_LIT> ) ; } if ( FirstHalfOfMandatoryField & TracebackTable :: IsInterruptHandlerMask ) report_fatal_error ( <STR_LIT> ) ; if ( FirstHalfOfMandatoryField & TracebackTable :: HasControlledStorageMask ) report_fatal_error ( <STR_LIT> ) ; if ( FirstHalfOfMandatoryField & TracebackTable :: IsFunctionNamePresentMask ) { StringRef Name = MF -> getName ( )


<s> LocalTypes . insert ( LocalTypes . end ( ) , Locals


<s> bool <ISA_LIT>TargetMachine :: addInstSelector ( PassManagerBase & PM , bool Fast ) { PM . add ( create<ISA_LIT>ISelDag ( *


<s> unsigned Reg = Worklist . pop_back_val ( ) ; if ( ! DoneRegs . insert ( Reg ) . second ) continue ; for ( auto & Use : MRI -> use_instructions ( Reg ) ) if ( Use . getOpcode ( ) == <STR_LIT> ) { MachineOperand & TrueMO = Use . getOperand ( <NUM_LIT> ) ; MachineOperand & FalseMO = Use . getOperand ( <NUM_LIT> ) ; const TargetRegisterClass * RC = TRI -> getCommonSubClass ( getRC32 ( FalseMO , VRM , MRI ) , getRC32 ( TrueMO , VRM , MRI ) ) ; if ( RC && RC != & <STR_LIT> ) { SmallSet < unsigned , <NUM_LIT> > CopyHints ; CopyHints . insert ( Hints . begin ( ) , Hints . end ( ) ) ; Hints . clear ( ) ; for ( MCPhysReg Reg : Order ) if ( CopyHints . count ( Reg ) && RC -> contains ( Reg ) && ! MRI -> isReserved ( Reg ) ) Hints . push_back ( Reg ) ; for ( MCPhysReg Reg : Order ) if ( ! CopyHints . count ( Reg ) && RC -> contains ( Reg ) && ! MRI -> isReserved ( Reg ) ) Hints . push_back ( Reg ) ; return true ; } unsigned OtherReg = ( TrueMO . getReg ( ) == Reg ? FalseMO . getReg ( ) : TrueMO . getReg ( ) ) ; if ( MRI -> getRegClass ( OtherReg ) ==

& <STR_LIT> ) Worklist . push_back ( OtherReg ) ;


<s> printOperand ( MI , opNum , O ) ; if ( Modifier && strcmp ( Modifier , <STR_LIT> ) == <NUM_LIT> ) { O << <STR_LIT> ; printOperand ( MI , opNum + <NUM_LIT> , O ) ; } else { if ( MI -> getOperand ( opNum + <NUM_LIT> ) . isImm ( ) && MI -> getOperand ( opNum + <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) return ; O <<


<s> SDValue Src = Op . getOperand ( <NUM_LIT> ) ; if ( Src . getValueType ( ) == <STR_LIT> ) return Op ; if ( Src . getValueType ( ) == <STR_LIT> ) { if ( Op . getValueType ( ) == <STR_LIT> ) { if ( Op . getOpcode ( ) == <STR_LIT> ) { SDValue Lo = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Src , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Src , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ; SDValue Res = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Lo , Hi ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Res ) ; } if ( Op . getOpcode ( ) == <STR_LIT> ) { const uint64_t TwoE31 [ ] = { <NUM_LIT> , <NUM_LIT> } ; APFloat APF = APFloat ( APFloat :: <ISA_LIT>DoubleDouble ( ) , APInt (


<s> Register BasePtr = TRI -> getBaseRegister ( ) ; if ( STI . isTarget64BitILP32 ( ) )

BasePtr = get<ISA_LIT>SubSuperRegister ( BasePtr , <NUM_LIT> ) ;


<s> bool evaluateConstantImm ( int64_t & Imm , <ISA_LIT>MCExpr :: VariantKind & VK ) const { const MCExpr * Val = getImm ( ) ; bool Ret = false ; if ( auto * RE = dyn_cast < <ISA_LIT>MCExpr >


<s> if ( targetm . calls . must_pass_in_stack ( arg ) ) return true ; if ( MMIX_FUNCTION_ARG_SIZE ( arg . mode , arg . type ) > <NUM_LIT> && ! TARGET_LIBFUNC && ( !

argsp || ! argsp -> lib ) ) return true ;


<s> case InlineAsm :: Constraint_m : OutOps . push_back ( Op ) ; return false ; } return true


<s> if ( Kind . isBSS ( ) && IsGlobalInSmallSection ( GV , TM , Kind ) ) return SmallBSSSection ; if ( Kind . isDataRel ( ) && IsGlobalInSmallSection ( GV , TM , Kind ) ) return SmallDataSection ; return TargetLoweringObjectFileELF :: SelectSectionForGlobal ( GV , Kind ,


<s> { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , } ; static const CostTblEntry SSE42CostTbl [ ] = { { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , } ; static const CostTblEntry AVX1CostTbl [ ] = { { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , } ; static const CostTblEntry AVX2CostTbl [ ] = { { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , } ; static const CostTblEntry AVX512CostTbl [ ] = { { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , } ; static const CostTblEntry AVX512BWCostTbl [ ] = { { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , } ; if ( ST -> hasBWI ( ) ) if ( const auto * Entry = CostTableLookup ( AVX512BWCostTbl , ISD , MTy ) ) return LT . first *


<s> PM . add ( create<ISA_LIT>TargetTransformInfoPass ( this


<s> case <NUM_LIT> : LoadMnemonic = <STR_LIT> ; StoreMnemonic = <STR_LIT> ; break ; case <NUM_LIT> : LoadMnemonic = <STR_LIT> ; StoreMnemonic = <STR_LIT> ; break ; } const BasicBlock * LLVM_BB = BB -> getBasicBlock ( ) ; MachineFunction * F = BB -> getParent ( ) ; MachineFunction :: iterator It = ++ BB -> getIterator ( ) ; Register dest = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register ptrA = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register ptrB = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register incr = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; DebugLoc dl = MI . getDebugLoc ( ) ; MachineBasicBlock * loopMBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * loop2MBB = CmpOpcode ? F -> CreateMachineBasicBlock ( LLVM_BB ) : nullptr ; MachineBasicBlock * exitMBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; F -> insert ( It , loopMBB ) ; if ( CmpOpcode ) F -> insert ( It , loop2MBB ) ; F -> insert ( It , exitMBB ) ; exitMBB -> splice ( exitMBB -> begin ( ) , BB , std :: next ( MachineBasicBlock :: iterator ( MI ) ) , BB -> end ( ) ) ; exitMBB -> transferSuccessorsAndUpdatePHIs ( BB ) ; MachineRegisterInfo & RegInfo = F -> getRegInfo ( ) ; Register TmpReg = ( ! BinOpcode ) ? incr : RegInfo . createVirtualRegister ( AtomicSize == <NUM_LIT> ? & <STR_LIT> : & <STR_LIT> ) ; BB -> addSuccessor ( loopMBB ) ; BB = loopMBB ; BuildMI ( BB , dl , TII -> get ( LoadMnemonic ) , dest ) . addReg ( ptrA ) . addReg ( ptrB ) ; if ( BinOpcode ) BuildMI ( BB , dl , TII -> get ( BinOpcode ) , TmpReg )


<s> if ( Occupancy < Limit ) Occupancy = Limit ; limitOccupancy ( MF


<s> bool m68k_use_return_insn ( void ) { if ( ! reload_completed || frame_pointer_needed || get_frame_size ( ) != <NUM_LIT> ) return false ; m68k_compute_frame_layout (


<s> <STR_LIT> ; const TargetRegisterClass * SuperRC = CI . IsX2 ? & <STR_LIT> : & <STR_LIT> ; unsigned DestReg = MRI -> createVirtualRegister ( SuperRC ) ; unsigned MergedOffset = std :: min ( CI . Offset0 , CI . Offset1 ) ; BuildMI ( * MBB , CI . Paired , DL , TII -> get ( Opcode ) , DestReg ) . add ( * TII -> getNamedOperand ( * CI . I , <STR_LIT> :: sbase ) ) . addImm ( MergedOffset ) . addImm ( CI . GLC0 ) . cloneMergedMemRefs ( { & * CI . I , & * CI . Paired } ) ; unsigned SubRegIdx0 = CI . IsX2 ? <STR_LIT> : <STR_LIT> ; unsigned SubRegIdx1 = CI . IsX2 ? <STR_LIT> : <STR_LIT> ; if ( CI . Offset0 > CI . Offset1 ) std :: swap ( SubRegIdx0 , SubRegIdx1 ) ; const MCInstrDesc & CopyDesc = TII -> get ( TargetOpcode :: COPY ) ; const auto * Dest0 = TII -> getNamedOperand ( * CI . I , <STR_LIT> :: sdst ) ; const auto * Dest1 = TII -> getNamedOperand ( * CI . Paired , <STR_LIT>


<s> Insn = ( Bytes [ <NUM_LIT> ] << <NUM_LIT> ) | ( Bytes [ <NUM_LIT> ] << <NUM_LIT> ) ; return MCDisassembler ::


<s> unsigned size = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; if ( size == <NUM_LIT> ) return MCDisassembler :: Fail ; unsigned type = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned align = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; if ( type == <NUM_LIT> && align == <NUM_LIT> ) return MCDisassembler :: Fail ; if ( type == <NUM_LIT> && align == <NUM_LIT> ) return MCDisassembler :: Fail ; unsigned load = fieldFromInstruction ( Insn , <NUM_LIT> ,


<s> bool <ISA_LIT>RegisterInfo :: requiresRegisterScavenging ( const MachineFunction & MF ) const { return true


<s> MCA . getOrCreateSymbolData ( * GP_Disp ) ; MCInst TmpInst ; TmpInst . setOpcode ( <STR_LIT> ) ; TmpInst . addOperand ( MCOperand :: CreateReg ( <STR_LIT> ) ) ; const MCSymbolRefExpr * LoSym = MCSymbolRefExpr :: Create ( <STR_LIT> , MCSymbolRefExpr :: VK_<ISA_LIT>_ABS_LO , MCA . getContext ( ) ) ; TmpInst . addOperand ( MCOperand :: CreateExpr ( LoSym ) ) ; getStreamer ( ) . EmitInstruction ( TmpInst , STI ) ; TmpInst . clear ( ) ; TmpInst . setOpcode ( <STR_LIT> ) ; const MCSymbolRefExpr * HiSym = MCSymbolRefExpr :: Create ( <STR_LIT> , MCSymbolRefExpr :: VK_<ISA_LIT>_ABS_HI , MCA . getContext ( ) ) ; TmpInst . addOperand ( MCOperand :: CreateExpr ( HiSym ) ) ; getStreamer ( ) . EmitInstruction ( TmpInst , STI ) ; TmpInst . clear (


<s> static void msp430_print_operand ( FILE * file , rtx op , int letter ) { rtx addr ; switch ( letter ) { case 'Z' : gcc_assert ( CONST_INT_P ( op ) ) ; fprintf ( file , <STR_LIT> , INTVAL ( op ) - <NUM_LIT> ) ; return ; case 'Y' : gcc_assert ( CONST_INT_P ( op ) ) ; fprintf ( file , <STR_LIT> , INTVAL ( op ) - <NUM_LIT> ) ; return ; case 'I' : if ( GET_CODE ( op ) == CONST_INT ) { int i = INTVAL ( op ) ; fprintf ( file , <STR_LIT> , ~ i ) ; return ; } op = XEXP ( op , <NUM_LIT> ) ; break ; case 'r' : switch ( GET_CODE ( op ) ) { case EQ : fprintf ( file , <STR_LIT> ) ; break ; case NE : fprintf ( file , <STR_LIT> ) ; break ; case GEU : fprintf ( file , <STR_LIT> ) ; break ; case LTU : fprintf ( file , <STR_LIT> ) ; break ; case GE : fprintf ( file , <STR_LIT> ) ; break ; case LT : fprintf ( file , <STR_LIT> ) ; break ; case GTU : fprintf ( file , <STR_LIT> ) ; break ; case LEU : fprintf ( file , <STR_LIT> ) ; break ; case GT : fprintf ( file , <STR_LIT> ) ; break ; case LE : fprintf ( file , <STR_LIT> ) ; break ; default : msp430_print_operand_raw ( file , op ) ; break ; } return ; case 'R' : switch ( GET_CODE ( op ) ) { case GTU : fprintf ( file , <STR_LIT> ) ; break ; case LEU : fprintf ( file , <STR_LIT> ) ; break ; case GT : fprintf ( file , <STR_LIT> ) ; break ; case LE : fprintf ( file , <STR_LIT> ) ; break ; default : msp430_print_operand_raw ( file , op ) ; break ; } return ; case 'p' : gcc_assert ( CONST_INT_P ( op ) ) ; fprintf ( file , <STR_LIT> , <NUM_LIT> << INTVAL ( op ) ) ; return ; case 'b' : switch ( GET_MODE ( op ) ) { case QImode : fprintf ( file , <STR_LIT> ) ; return ; case HImode : fprintf ( file , <STR_LIT> ) ; return ; case PSImode : fprintf ( file , <STR_LIT> ) ; return ; case SImode : fprintf ( file , <STR_LIT> ) ; return ; default : return ; } case 'A' : case 'L' : switch ( GET_CODE ( op ) ) { case MEM : op = adjust_address ( op , Pmode , <NUM_LIT> ) ; break ; case REG : break ; case CONST_INT : op = GEN_INT ( INTVAL ( op ) & <NUM_LIT> ) ; letter = <NUM_LIT> ; break ; default : gcc_unreachable ( ) ; } break ; case 'B' : case 'H' : switch ( GET_CODE ( op


<s> SDValue CPTmp0 ; SDValue CPTmp1 ; SDValue CPTmp2 ; if ( isThumb2 ) { if ( SelectImmShifterOperand ( N0 , CPTmp0 , CPTmp1 ) ) continue ; } else { if ( SelectImmShifterOperand ( N0 , CPTmp0 , CPTmp1 ) || SelectRegShifterOperand ( N0 , CPTmp0 , CPTmp1 , CPTmp2 ) ) continue ; } Srl = CurDAG -> getNode ( <STR_LIT> , SDLoc ( Srl ) , <STR_LIT> , Srl . getOperand ( <NUM_LIT> ) , CurDAG -> getConstant ( Srl_imm + TZ , SDLoc ( Srl ) , <STR_LIT> ) ) ; N1 = CurDAG -> getNode ( <STR_LIT> , SDLoc ( N1 ) , <STR_LIT> , Srl , CurDAG -> getConstant ( And_imm , SDLoc ( Srl )


<s> bool <ISA_LIT>AsmParser :: expandLoadAddressReg ( MCInst & Inst , bool Is32BitImm , SMLoc IDLoc , SmallVectorImpl < MCInst > & Instructions ) { const MCOperand & DstRegOp = Inst . getOperand ( <NUM_LIT> ) ; assert ( DstRegOp . isReg ( ) && <STR_LIT> ) ; const MCOperand & SrcRegOp = Inst . getOperand ( <NUM_LIT> ) ; assert ( SrcRegOp . isReg ( ) && <STR_LIT> ) ; const MCOperand & ImmOp = Inst . getOperand ( <NUM_LIT> ) ; assert ( ( ImmOp . isImm ( ) || ImmOp . isExpr ( ) ) && <STR_LIT> ) ; if ( ! ImmOp . isImm ( ) ) { if ( loadAndAddSymbolAddress ( ImmOp . getExpr ( ) , DstRegOp . getReg ( ) , SrcRegOp . getReg ( ) , Is32BitImm , IDLoc , Instructions ) ) return true ; return false ; } if ( loadImmediate ( ImmOp . getImm ( ) , DstRegOp . getReg ( ) , SrcRegOp . getReg (


<s> SmallPtrSet < BasicBlock * , <NUM_LIT> > ExceptBlocks ; for ( BasicBlock & BB : F ) { for ( auto I = BB . begin ( ) , E = BB . end ( ) ; I != E ; ++ I ) { if ( auto * CI = dyn_cast < CallInst > ( I ) ) { auto * Intrin = dyn_cast < IntrinsicInst > ( CI ) ; if ( Intrin ) { continue ; } insertStateNumberStore ( RegNode , CI , - <NUM_LIT> ) ; } else if ( auto * II = dyn_cast < InvokeInst > ( I ) ) { LandingPadInst * LPI = II -> getUnwindDest ( ) -> getLandingPadInst ( ) ; auto InsertionPair = FuncInfo . LandingPadStateMap . insert ( std :: make_pair ( LPI , CurState ) ) ; auto Iter = InsertionPair . first ; int & State = Iter -> second ; bool Inserted = InsertionPair . second ; if ( Inserted ) { auto * EHActions = cast < IntrinsicInst > ( LPI -> getNextNode ( ) ) ; SmallVector < std :: unique_ptr < ActionHandler > , <NUM_LIT> > ActionList ; parseEHActions ( EHActions , ActionList ) ; assert ( ! ActionList . empty ( ) ) ; CurState += ActionList . size ( ) ; State += ActionList . size ( ) - <NUM_LIT> ; for ( auto & Handler : ActionList ) { if ( auto * CH = dyn_cast < CatchHandler > ( Handler . get ( ) ) ) { auto * BA = cast < BlockAddress > ( CH -> getHandlerBlockOrFunc ( ) ) ; for ( BasicBlock * Pred : predecessors ( BA -> getBasicBlock ( ) ) ) assert ( Pred -> isLandingPad ( ) && <STR_LIT> ) ; ExceptBlocks . insert ( BA -> getBasicBlock ( ) ) ; } } } insertStateNumberStore ( RegNode , II , State ) ; } } } Function * RestoreFrame = <STR_LIT> ( TheModule , <STR_LIT> ) ; for ( BasicBlock * ExceptBB :


<s> builtin_decls_data bdda [ ] = { { double_type_node , <STR_LIT> , AARCH64_BUILTIN_RSQRT_DF } , { float_type_node , <STR_LIT> , AARCH64_BUILTIN_RSQRT_SF } , { V2DF_type_node , <STR_LIT> , AARCH64_BUILTIN_RSQRT_V2DF } , { V2SF_type_node , <STR_LIT> , AARCH64_BUILTIN_RSQRT_V2SF } , { V4SF_type_node , <STR_LIT> , AARCH64_BUILTIN_RSQRT_V4SF } } ; builtin_decls_data * bdd = bdda ; builtin_decls_data * bdd_end = bdd + ( sizeof ( bdda ) / sizeof ( builtin_decls_data ) ) ; for ( ; bdd < bdd_end ; bdd ++ ) { ftype = build_function_type_list ( bdd -> type_node , bdd -> type_node , NULL_TREE ) ; tree attrs = aarch64_get_attributes ( FLAG_FP , TYPE_MODE ( bdd -> type_node ) ) ; fndecl = aarch64_general_add_builtin ( bdd -> builtin_name , ftype , bdd -> function_code , attrs ) ; aarch64_builtin_decls [ bdd -> function_code ] = fndecl


<s> size_t SecondColon = AccessPattern . find_first_of ( ':' , FirstColon + <NUM_LIT> ) ; StringRef IndexPattern = AccessPattern . substr ( FirstDollar + <NUM_LIT> ) ; StringRef RelocKindStr = AccessPattern . substr ( FirstColon + <NUM_LIT> , SecondColon - FirstColon ) ; StringRef PatchImmStr = AccessPattern . substr ( SecondColon + <NUM_LIT> , FirstDollar - SecondColon ) ; BTFFieldReloc FieldReloc ; FieldReloc . Label = ORSym ; FieldReloc . OffsetNameOff = addString ( IndexPattern ) ; FieldReloc . TypeID


<s> if ( TT . isOSBinFormatELF ( ) ) return make_unique < TargetLoweringObjectFileELF > ( ) ; if ( TT . isKnownWindowsMSVCEnvironment ( ) ) return make_unique < <ISA_LIT>WindowsTargetObjectFile > ( ) ; if ( TT . isOSBinFormatCOFF ( ) ) return make_unique < TargetLoweringObjectFileCOFF > ( ) ; llvm_unreachable ( <STR_LIT>


<s> bool <ISA_LIT>Subtarget :: isLegalToCallImmediateAddr ( ) const { if ( In64BitMode || isTargetWin32 ( ) ) return false ; return isTargetELF ( ) || TM . getRelocationModel ( ) ==


<s> assert ( Tok . is ( AsmToken :: Identifier ) && <STR_LIT> ) ; StringRef Mask = Tok . getString ( ) ; if ( isMClass ( ) ) { std :: string Name = Mask . lower ( ) ; unsigned FlagsVal = StringSwitch < unsigned > ( Name ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Default ( ~ <NUM_LIT> ) ; if ( FlagsVal == ~ <NUM_LIT> ) return MatchOperand_NoMatch ; if ( ! hasV7Ops ( ) && FlagsVal >= <NUM_LIT> && FlagsVal <= <NUM_LIT> ) return MatchOperand_NoMatch ; Parser . Lex ( ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateMSRMask ( FlagsVal , S ) ) ; return MatchOperand_Success ; } size_t Start = <NUM_LIT> , Next = Mask . find ( '_' ) ; StringRef Flags = <STR_LIT> ; std :: string SpecReg = Mask . slice ( Start , Next ) . lower ( ) ; if ( Next != StringRef :: npos ) Flags = Mask . slice ( Next + <NUM_LIT> , Mask . size ( ) ) ; unsigned FlagsVal = <NUM_LIT> ; if ( SpecReg == <STR_LIT> ) { FlagsVal = StringSwitch < unsigned > ( Flags ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Default ( ~ <NUM_LIT> ) ; if ( FlagsVal == ~ <NUM_LIT> ) { if ( ! Flags . empty ( ) ) return MatchOperand_NoMatch ; else FlagsVal = <NUM_LIT> ; } } else if ( SpecReg == <STR_LIT> || SpecReg == <STR_LIT> ) { if ( Flags == <STR_LIT> || Flags == <STR_LIT> ) Flags = <STR_LIT> ; for ( int i = <NUM_LIT> , e = Flags . size ( ) ; i != e ; ++ i ) { unsigned Flag = StringSwitch < unsigned > ( Flags . substr ( i , <NUM_LIT> ) ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Default ( ~ <NUM_LIT> ) ; if ( FlagsVal == ~ <NUM_LIT> || ( FlagsVal & Flag ) ) return MatchOperand_NoMatch ; FlagsVal |= Flag ; } } else return MatchOperand_NoMatch ; if ( SpecReg == <STR_LIT> ) FlagsVal |= <NUM_LIT> ; Parser . Lex ( ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateMSRMask ( FlagsVal , S ) ) ; return


<s> } llvm_unreachable ( <STR_LIT> ) ; } namespace { class <ISA_LIT>MCAsmBackend : public MCAsmBackend { uint8_t OSABI ; public : <ISA_LIT>MCAsmBackend ( uint8_t osABI ) : MCAsmBackend ( <STR_LIT> ) , OSABI ( osABI ) { } unsigned getNumFixupKinds ( ) const override { return <STR_LIT> ; } const MCFixupKindInfo & getFixupKindInfo ( MCFixupKind Kind ) const override ; void applyFixup ( const MCAssembler & Asm , const MCFixup & Fixup , const MCValue & Target , MutableArrayRef < char > Data , uint64_t Value , bool IsResolved ) const override ; bool mayNeedRelaxation ( const MCInst & Inst ) const override { return false ; } bool fixupNeedsRelaxation ( const MCFixup & Fixup , uint64_t Value , const MCRelaxableFragment * Fragment , const MCAsmLayout & Layout ) const override { return false ; } void relaxInstruction ( const MCInst & Inst , const MCSubtargetInfo & STI , MCInst & Res ) const override { llvm_unreachable ( <STR_LIT> ) ; } bool writeNopData ( raw_ostream & OS , uint64_t Count ) const override ; std :: unique_ptr < MCObjectTargetWriter > createObjectTargetWriter ( ) const override { return create<ISA_LIT>ObjectWriter ( OSABI ) ; } } ; } const MCFixupKindInfo & <ISA_LIT>MCAsmBackend :: getFixupKindInfo ( MCFixupKind Kind ) const { const static MCFixupKindInfo Infos [ <STR_LIT> ] = { { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } } ; if ( Kind < FirstTargetFixupKind ) return MCAsmBackend :: getFixupKindInfo ( Kind ) ; assert ( unsigned ( Kind - FirstTargetFixupKind ) < getNumFixupKinds ( ) && <STR_LIT> ) ; return Infos [ Kind - FirstTargetFixupKind ] ; } void <ISA_LIT>MCAsmBackend :: applyFixup ( const MCAssembler & Asm , const MCFixup & Fixup , const MCValue & Target , MutableArrayRef < char > Data , uint64_t Value , bool IsResolved ) const { MCFixupKind Kind = Fixup . getKind ( ) ; unsigned Offset = Fixup . getOffset ( ) ; unsigned BitSize = getFixupKindInfo ( Kind ) . TargetSize ; unsigned Size = ( BitSize + <NUM_LIT> ) / <NUM_LIT> ; assert ( Offset + Size <= Data . size (


<s> __rv . __o = __builtin_neon_vld4v4si ( ( const __builtin_neon_si * ) __a ) ; return __rv .


<s> return infer_vector_or_tuple_type ( argno ,


<s> printMemOperand ( const MCInst * MI , int opNum , raw_ostream & O ) { O << <STR_LIT> ; printOperand ( MI , opNum , O ) ; MCOperand opnd2 = MI -> getOperand ( opNum + <NUM_LIT> ) ; if ( opnd2 . isImm ( ) && opnd2 . getImm ( ) < <NUM_LIT> ) { O << <STR_LIT> ; O << ( int ) opnd2 . getImm ( ) *


<s> static Optional < int64_t > getVectorShiftImm ( Register Reg , MachineRegisterInfo & MRI ) { assert ( MRI . getType ( Reg ) . isVector ( ) && <STR_LIT> ) ; MachineInstr * OpMI = MRI . getVRegDef ( Reg ) ; assert ( OpMI && <STR_LIT> ) ; return get<ISA_LIT>VectorSplatScalar ( * OpMI


<s> const BlockAddress * BA = cast < BlockAddressSDNode > ( Op ) -> getBlockAddress ( ) ; SDValue Result = DAG . getTargetBlockAddress (


<s> <ISA_LIT>HazardRecognizer ( const InstrItineraryData * ItinData , const <ISA_LIT>BaseInstrInfo & tii , const <ISA_LIT>BaseRegisterInfo & tri

, const <ISA_LIT>Subtarget & sti , const ScheduleDAG * DAG ) :


<s> Register SrcLoReg , SrcHiReg , DstLoReg , DstHiReg ; Register DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; bool DstIsDead = MI . getOperand ( <NUM_LIT> ) . isDead ( ) ; bool DstIsKill = MI . getOperand ( <NUM_LIT> ) . isKill ( ) ; bool SrcIsKill = MI . getOperand ( <NUM_LIT> ) . isKill ( ) ; bool ImpIsDead = MI . getOperand ( <NUM_LIT> ) . isDead ( ) ; TRI -> splitReg ( SrcReg , SrcLoReg , SrcHiReg ) ; TRI -> splitReg ( DstReg , DstLoReg , DstHiReg ) ; buildMI ( MBB , MBBI , OpLo ) . addReg ( DstLoReg , RegState :: Define | getDeadRegState ( DstIsDead ) ) . addReg ( DstLoReg , getKillRegState

( DstIsKill ) ) . addReg ( SrcLoReg , getKillRegState ( SrcIsKill ) ) ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { if ( Tail . getOperand ( <NUM_LIT> ) . isFI ( ) ) return false ; Register BaseAddrReg = Tail . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( DestReg != BaseAddrReg ) return false ; MachineOperand & TailImmOp = Tail . getOperand ( <NUM_LIT> ) ; int64_t Offset = TailImmOp . getImm ( ) ; HiLUI . getOperand ( <NUM_LIT> ) . setOffset ( Offset ) ; Tail . RemoveOperand ( <NUM_LIT> ) ; MachineOperand & ImmOp = LoADDI . getOperand ( <NUM_LIT> ) ; ImmOp . setOffset


<s> return MCDisassembler :: Fail ; } DstA = decodeAField ( Insn ) ; DecodeGPR32RegisterClass ( Inst , DstA , Address , Decoder ) ; LImm = ( Insn >> <NUM_LIT> ) ; Inst . addOperand ( MCOperand :: createImm ( LImm ) ) ; Inst . addOperand ( MCOperand :: createImm ( <NUM_LIT>


<s> __builtin_ia32_aadd64 ( ( long long * ) __A , __B


<s> static bool isHighReg ( unsigned int Reg ) { if ( <STR_LIT> . contains ( Reg ) ) return true ; assert ( <STR_LIT> . contains ( Reg ) && <STR_LIT> ) ; return


<s> return ix86_dep_by_shift_count_body ( PATTERN ( set_insn ) , PATTERN ( use_insn


<s> return get_hard_reg_initial_val ( Pmode , TP_REGNO


<s> return ( ( qword ) ( vec_rl ( ( vec_ushort8 ) ( a ) , vec_splat ( ( vec_ushort8 ) ( si_from_int ( b


<s> if ( Subtarget . hasAVX ( ) && N -> getOpcode ( ) == <STR_LIT> ) { SDValue Op ( N , <NUM_LIT> ) ; if ( TLI . isTypeLegal ( VT ) && TLI . isTypeLegal ( In . getValueType ( ) ) ) if (

SDValue Res = combine<ISA_LIT>ShufflesRecursively ( Op , DAG , Subtarget ) ) return Res ;


<s> static MCSubtargetInfo * create<ISA_LIT>MCSubtargetInfo ( StringRef TT , StringRef CPU , StringRef FS ) { MCSubtargetInfo * X = new MCSubtargetInfo (


<s> if ( MEM_P ( SET_SRC ( body ) ) ) return <NUM_LIT> ; if ( GET_CODE ( SET_SRC ( body ) ) == VEC_SELECT && MEM_P ( XEXP ( SET_SRC ( body ) , <NUM_LIT> ) ) ) return <NUM_LIT> ; if ( pattern_is_rotate64 ( body ) && MEM_P ( XEXP ( SET_SRC ( body )


<s> MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; MFI -> setFrameAddressIsTaken ( true ) ; bool is31 = ( DisableFramePointerElim ( MF ) || MFI -> hasVarSizedObjects ( ) ) && MFI -> getStackSize ( ) && ! MF . getFunction ( ) -> hasFnAttr ( Attribute :: Naked ) ; unsigned FrameReg = is<ISA_LIT>64 ? ( is31 ? <STR_LIT> : <STR_LIT> ) : ( is31 ? <STR_LIT> :


<s> if ( ! Desc . mayLoad ( ) || ! Desc . mayStore ( ) ) return true ; int DMaskIdx = <STR_LIT> ( Opc , <STR_LIT> :: dmask ) ; unsigned DMask = Inst . getOperand ( DMaskIdx ) . getImm ( )


<s> if ( TARGET_ADDRESSES ) { fprintf ( asm_out_file , <STR_LIT> , INSN_ADDRESSES ( uid ) , INSN_ADDRESSES ( uid ) - last_insn_address ) ; last_insn_address = INSN_ADDRESSES


<s> emit_label ( XEXP ( label , <NUM_LIT> ) ) ; before = scratch = gen_reg_rtx ( SImode ) ; emit_load_locked ( SImode , before , mem ) ; switch ( code ) { case IOR : case XOR : case AND : after = expand_simple_binop ( SImode , code , before , val , NULL_RTX , <NUM_LIT> , OPTAB_LIB_WIDEN ) ; scratch = after ; break ; case PLUS : case MINUS : before = expand_binop ( SImode , and_optab , scratch , mask , NULL_RTX , <NUM_LIT> , OPTAB_LIB_WIDEN ) ; scratch = expand_binop ( SImode , xor_optab , scratch , before , scratch , <NUM_LIT> , OPTAB_LIB_WIDEN ) ; after = expand_simple_binop ( SImode , code , before , val , NULL_RTX , <NUM_LIT> , OPTAB_LIB_WIDEN ) ; after = expand_binop ( SImode , and_optab , after , mask , after , <NUM_LIT> , OPTAB_LIB_WIDEN ) ; scratch = expand_binop ( SImode , ior_optab , scratch , after , scratch , <NUM_LIT> , OPTAB_LIB_WIDEN ) ; break ; case MULT : after = expand_binop ( SImode , and_optab , before , val , NULL_RTX , <NUM_LIT> , OPTAB_LIB_WIDEN ) ; after = expand_binop ( SImode , xor_optab , after , mask , after , <NUM_LIT> , OPTAB_LIB_WIDEN ) ; scratch = after ; break ; default : gcc_unreachable ( ) ; } emit_store_conditional ( SImode , mem , scratch ) ; emit_unlikely_jump ( EQ , label ) ; if ( orig_before ) or1k_finish_atomic_subword ( mode , orig_before , before , shift ) ; if ( orig_after ) or1k_finish_atomic_subword ( mode , orig_after , after


<s> MCCodeEmitter * llvm :: create<ISA_LIT>MCCodeEmitter ( const MCInstrInfo & MCII , const MCRegisterInfo

& MRI , const MCSubtargetInfo & STI , MCContext & Ctx ) {


<s> case CortexX1 : PrefFunctionLogAlignment = <NUM_LIT> ; break ; case A64FX : CacheLineSize = <NUM_LIT> ; PrefFunctionLogAlignment = <NUM_LIT> ; PrefLoopLogAlignment = <NUM_LIT> ; MaxInterleaveFactor = <NUM_LIT> ; PrefetchDistance = <NUM_LIT> ; MinPrefetchStride = <NUM_LIT> ; MaxPrefetchIterationsAhead = <NUM_LIT> ; break ; case AppleA7 : case AppleA10 : case AppleA11 : case AppleA12 : case AppleA13 : case AppleA14 : CacheLineSize = <NUM_LIT> ; PrefetchDistance = <NUM_LIT> ; MinPrefetchStride = <NUM_LIT> ; MaxPrefetchIterationsAhead = <NUM_LIT> ; break ; case ExynosM3 : MaxInterleaveFactor = <NUM_LIT> ; MaxJumpTableSize = <NUM_LIT> ; PrefFunctionLogAlignment = <NUM_LIT> ; PrefLoopLogAlignment = <NUM_LIT> ; break ; case Falkor : MaxInterleaveFactor = <NUM_LIT> ; MinVectorRegisterBitWidth = <NUM_LIT> ; CacheLineSize = <NUM_LIT> ; PrefetchDistance = <NUM_LIT> ; MinPrefetchStride = <NUM_LIT> ; MaxPrefetchIterationsAhead = <NUM_LIT> ; break ; case Kryo : MaxInterleaveFactor = <NUM_LIT> ; VectorInsertExtractBaseCost = <NUM_LIT> ; CacheLineSize = <NUM_LIT> ; PrefetchDistance = <NUM_LIT> ; MinPrefetchStride = <NUM_LIT> ; MaxPrefetchIterationsAhead = <NUM_LIT> ; MinVectorRegisterBitWidth = <NUM_LIT> ; break ; case NeoverseE1 : PrefFunctionLogAlignment = <NUM_LIT> ; break ; case NeoverseN1 : case NeoverseN2 : case NeoverseV1 : PrefFunctionLogAlignment = <NUM_LIT> ; break ; case Saphira : MaxInterleaveFactor = <NUM_LIT> ; MinVectorRegisterBitWidth = <NUM_LIT> ; break ; case ThunderX2T99 : CacheLineSize = <NUM_LIT> ; PrefFunctionLogAlignment = <NUM_LIT> ; PrefLoopLogAlignment = <NUM_LIT> ; MaxInterleaveFactor = <NUM_LIT> ; PrefetchDistance = <NUM_LIT> ; MinPrefetchStride = <NUM_LIT> ; MaxPrefetchIterationsAhead = <NUM_LIT> ; MinVectorRegisterBitWidth = <NUM_LIT> ; break ; case ThunderX : case ThunderXT88 : case ThunderXT81 : case ThunderXT83 : CacheLineSize = <NUM_LIT> ; PrefFunctionLogAlignment = <NUM_LIT> ; PrefLoopLogAlignment = <NUM_LIT> ; MinVectorRegisterBitWidth = <NUM_LIT> ; break ; case TSV110 : CacheLineSize = <NUM_LIT> ; PrefFunctionLogAlignment = <NUM_LIT> ; PrefLoopLogAlignment = <NUM_LIT> ; break ; case ThunderX3T110 : CacheLineSize = <NUM_LIT> ; PrefFunctionLogAlignment = <NUM_LIT> ; PrefLoopLogAlignment = <NUM_LIT>


<s> StringRef getPassName ( ) const override { return


<s> OperandMatchResultTy <ISA_LIT>AsmParser :: tryParseRegister ( unsigned & RegNo , SMLoc & StartLoc , SMLoc & EndLoc ) { StartLoc = Parser . getTok ( ) . getLoc ( ) ; RegNo = parseRegister ( true ) ; EndLoc = Parser . getTok ( ) . getLoc ( ) ; if ( RegNo ==


<s> if ( IsUsingAlloca ) Flags |= <NUM_LIT> ; uint32_t DSASize = MFFrame . getStackSize ( ) ; uint32_t DSAAndFlags = DSASize & <NUM_LIT> ; DSAAndFlags |= Flags ; OutStreamer -> AddComment ( <STR_LIT> ) ; OutStreamer -> emitLabel ( CurrentFnEPMarkerSym ) ; OutStreamer -> AddComment ( <STR_LIT> ) ; OutStreamer -> emitIntValueInHex ( <NUM_LIT> , <NUM_LIT> ) ; OutStreamer -> AddComment ( <STR_LIT> ) ; OutStreamer -> emitInt8 ( <NUM_LIT> ) ; OutStreamer -> AddComment ( <STR_LIT> ) ; OutStreamer -> emitAbsoluteSymbolDiff ( CurrentFnPPA1Sym , CurrentFnEPMarkerSym , <NUM_LIT> ) ; if ( OutStreamer -> isVerboseAsm ( ) ) { OutStreamer -> AddComment ( <STR_LIT> + Twine :: utohexstr ( DSASize ) ) ; OutStreamer -> AddComment ( <STR_LIT> ) ; if ( Flags & <NUM_LIT> ) OutStreamer -> AddComment ( <STR_LIT> ) ; else OutStreamer -> AddComment


<s> bool <ISA_LIT>CallEntry :: isConstant ( const MachineFrameInfo * ) const { return false


<s> Operands . push_back ( <ISA_LIT>Operand :: CreateToken ( ExtraToken , Loc ) ) ; } } if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) { if ( parseOperand ( Operands , Mnemonic ) ) { return true ; } while ( parseOptionalToken ( AsmToken :: Comma ) ) { if ( parseOperand ( Operands , Mnemonic ) ) { return true ; } } } if ( parseToken ( AsmToken :: EndOfStatement , <STR_LIT> ) ) return true ; tryConvertingToTwoOperandForm ( Mnemonic , CarrySetting , Operands ) ; if ( ! CarrySetting && shouldOmitCCOutOperand ( Mnemonic , Operands ) ) Operands . erase ( Operands . begin ( ) + <NUM_LIT> ) ; if ( PredicationCode == <STR_LIT> && shouldOmitPredicateOperand ( Mnemonic , Operands ) ) Operands . erase ( Operands . begin ( ) + <NUM_LIT> ) ; if ( ! isThumb ( ) && Mnemonic == <STR_LIT> && Operands . size ( ) == <NUM_LIT> && static_cast < <ISA_LIT>Operand & > ( * Operands [ <NUM_LIT> ] ) . isImm ( ) ) Operands . erase ( Operands . begin ( ) + <NUM_LIT> ) ; if ( ! isThumb ( ) && Operands . size ( ) > <NUM_LIT> && ( Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> ) ) { bool isLoad = ( Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> ) ; unsigned Idx = isLoad ? <NUM_LIT> : <NUM_LIT> ; <ISA_LIT>Operand & Op1 = static_cast < <ISA_LIT>Operand & > ( * Operands [ Idx ] ) ; <ISA_LIT>Operand & Op2 = static_cast < <ISA_LIT>Operand & > ( * Operands [ Idx + <NUM_LIT> ] ) ; const MCRegisterClass & MRC = MRI -> getRegClass ( <STR_LIT> ) ; if ( Op1 . isReg ( ) && Op2 . isReg ( ) && MRC . contains ( Op1 . getReg ( ) ) && MRC . contains ( Op2 . getReg ( ) ) ) { unsigned Reg1 = Op1 . getReg ( ) ; unsigned Reg2 = Op2 . getReg ( ) ; unsigned Rt = MRI -> getEncodingValue ( Reg1 ) ; unsigned Rt2 = MRI -> getEncodingValue ( Reg2 ) ; if ( Rt + <NUM_LIT> != Rt2 || ( Rt & <NUM_LIT> ) ) { return Error ( Op2 . getStartLoc ( ) , isLoad ? <STR_LIT> : <STR_LIT> ) ; } unsigned NewReg = MRI -> getMatchingSuperReg ( Reg1 , <STR_LIT> , & ( MRI -> getRegClass ( <STR_LIT> ) ) ) ; Operands [ Idx ] = <ISA_LIT>Operand :: CreateReg ( NewReg , Op1 . getStartLoc ( ) , Op2 . getEndLoc ( ) ) ; Operands . erase ( Operands . begin (


<s> bool <ISA_LIT>InstrInfo :: isTC1 ( const MachineInstr & MI ) const { unsigned SchedClass = MI . getDesc ( ) . getSchedClass ( ) ; return is_TC1 (


<s> void LLVMInitialize<ISA_LIT>TargetInfo ( ) { RegisterTarget < Triple :: hsail , false > Target32 ( The<ISA_LIT>_32Target , <STR_LIT> , <STR_LIT> ) ; RegisterTarget < Triple :: hsail64 , false > Target64 ( The<ISA_LIT>_64Target , <STR_LIT>


<s> * loop_reg = copy_addr_to_reg ( XEXP ( mem , <NUM_LIT> ) ) ; * loop_mem = change_address ( mem , BLKmode , * loop_reg


<s> Header . amd_machine_version_stepping = ISA . Stepping ; Header . kernel_code_entry_byte_offset = sizeof ( Header ) ; Header . wavefront_size = <NUM_LIT> ; Header . call_convention = - <NUM_LIT> ; Header . kernarg_segment_alignment = <NUM_LIT> ; Header . group_segment_alignment = <NUM_LIT> ; Header . private_segment_alignment = <NUM_LIT>


<s> if ( ! Subtarget . hasSSE2 ( ) ) return SDValue ( ) ; if ( ! N -> getValueType ( <NUM_LIT> ) . isVector ( ) || ! N -> getValueType ( <NUM_LIT> ) . isSimple ( ) ) return SDValue ( ) ; SDValue In = N -> getOperand ( <NUM_LIT> ) ; if ( ! In . getValueType ( ) . isSimple ( ) ) return SDValue ( ) ; MVT VT = N -> getValueType ( <NUM_LIT> ) . getSimpleVT ( ) ; MVT SVT = VT . getScalarType ( ) ; MVT InVT = In . getValueType ( ) . getSimpleVT ( ) ; MVT InSVT = InVT . getScalarType ( ) ; if ( ! isPowerOf2_32 ( VT . getVectorNumElements ( ) ) ) return SDValue ( ) ; if ( SVT != <STR_LIT> && SVT != <STR_LIT> && SVT != <STR_LIT> ) return SDValue ( ) ; if ( InSVT != <STR_LIT> && InSVT != <STR_LIT> && InSVT != <STR_LIT> ) return SDValue ( ) ; if ( SVT == <STR_LIT> && VT . getSizeInBits ( ) < <NUM_LIT> ) return SDValue ( ) ; if ( Subtarget . hasAVX512 ( ) && ! ( ! Subtarget . useAVX512Regs ( ) && VT . is256BitVector ( ) && InVT . is512BitVector ( ) ) ) return SDValue ( ) ; unsigned NumPackedSignBits = std :: min < unsigned > ( SVT . getSizeInBits ( ) , <NUM_LIT> ) ; unsigned NumPackedZeroBits = Subtarget . hasSSE41 ( ) ? NumPackedSignBits :


<s> const <STR_LIT> * Info = <STR_LIT> ( Inst . getOpcode ( ) ) ; const <STR_LIT> * BaseInfo = <STR_LIT> ( Info -> BaseOpcode


<s> if ( Version . Major >= <NUM_LIT> ) return ExtraSGPRs ; if ( Version . Major < <NUM_LIT> ) { if ( FlatScrUsed ) ExtraSGPRs = <NUM_LIT> ; } else { if ( XNACKUsed )


<s> const <ISA_LIT>InstrInfo * getInstrInfo ( ) const


<s> if ( ! isImm ( ) ) return false ; if ( ! evaluateConstantImm ( getImm ( ) , Imm , VK ) || VK != <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ) return false ; return ( isRV64 ( ) && isUInt < <NUM_LIT> > ( Imm )


<s> if ( ! OutStreamer . hasRawTextSupport ( ) ) return ; emitFrameDirective (


<s> <ISA_LIT>XCOFFMCAsmInfo :: <ISA_LIT>XCOFFMCAsmInfo ( bool Is64Bit , const Triple & T ) { if ( T . getArch ( ) == Triple :: ppc64le || T . getArch ( ) == Triple :: ppcle ) report_fatal_error ( <STR_LIT> ) ; CodePointerSize = CalleeSaveStackSlotSize = Is64Bit ? <NUM_LIT> : <NUM_LIT> ; Data64bitsDirective = Is64Bit ? <STR_LIT> :


<s> bool <ISA_LIT>TargetLowering :: isLegalFlatAddressingMode ( const AddrMode & AM ) const { if ( ! Subtarget -> hasFlatInstOffsets ( ) ) { return AM . BaseOffs == <NUM_LIT> &&


<s> Results . push_back ( RCW . getValue ( <NUM_LIT> ) ) ; break ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : assert ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT> && Subtarget . is64Bit ( ) && <STR_LIT> ) ; if ( N -> getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) return ; Results . push_back ( customLegalizeToWOp ( N , DAG ) ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : assert ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT> && Subtarget . is64Bit ( ) && Subtarget . hasStdExtM ( ) && <STR_LIT> ) ; if ( N -> getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> || N -> getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) return ; Results . push_back ( customLegalizeToWOp ( N , DAG ) ) ; break ; case <STR_LIT> : { assert ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT> && Subtarget . is64Bit ( )

&& Subtarget . hasStdExtF ( ) && <STR_LIT> ) ;


<s> DebugLoc dl = Op . getDebugLoc ( ) ; if ( TM . getRelocationModel ( ) == Reloc :: Static ) { if ( ! ST -> usingLargeMem ( ) ) { return DAG . getNode ( <STR_LIT> , dl , PtrVT , GA , Zero ) ; } else { SDValue Hi = DAG . getNode ( <STR_LIT> , dl , PtrVT , GA , Zero ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , dl , PtrVT , GA , Zero ) ; return DAG . getNode ( <STR_LIT> , dl , PtrVT , Hi , Lo ) ; } } else { llvm_report_error ( <STR_LIT>


<s> bool IsZeroExt = Op0 . getOpcode ( ) == <STR_LIT> ; bool IsVWMULSU = IsSignExt && Op1 . getOpcode ( ) == <STR_LIT> ; if ( ( ! IsSignExt && ! IsZeroExt ) || ! Op0 . hasOneUse ( ) ) return SDValue ( ) ; SDValue Mask = N -> getOperand ( <NUM_LIT> ) ; SDValue VL = N -> getOperand ( <NUM_LIT> ) ; if ( Op0 . getOperand ( <NUM_LIT> ) != Mask || Op0 . getOperand ( <NUM_LIT> ) != VL ) return SDValue ( ) ; MVT VT = N -> getSimpleValueType ( <NUM_LIT> ) ; unsigned NarrowSize = VT . getScalarSizeInBits ( ) / <NUM_LIT> ; MVT NarrowVT = <STR_LIT> ( <STR_LIT> ( NarrowSize ) , VT . getVectorElementCount ( ) ) ; SDLoc DL ( N ) ; if ( IsVWMULSU || Op0 . getOpcode ( ) == Op1 . getOpcode ( ) ) { if ( ! Op1 . hasOneUse ( ) ) return SDValue ( ) ; if ( Op1 . getOperand ( <NUM_LIT> ) != Mask || Op1 . getOperand ( <NUM_LIT> ) != VL ) return SDValue ( ) ; Op1 = Op1 . getOperand ( <NUM_LIT> ) ; } else if ( Op1 . getOpcode ( ) == <STR_LIT> ) { if ( Op1 . getOperand ( <NUM_LIT> ) != VL ) return SDValue ( ) ; Op1 = Op1 . getOperand ( <NUM_LIT> ) ; unsigned EltBits = VT . getScalarSizeInBits ( ) ; unsigned ScalarBits = Op1 . getValueSizeInBits ( ) ; if ( ScalarBits < EltBits ) return SDValue ( ) ; if ( IsSignExt ) { if ( DAG . ComputeNumSignBits ( Op1 ) <= ( ScalarBits - NarrowSize ) ) return SDValue ( ) ; } else { APInt Mask = APInt :: getBitsSetFrom ( ScalarBits , NarrowSize ) ; if ( ! DAG . MaskedValueIsZero ( Op1 , Mask ) ) return SDValue ( ) ; } Op1 = DAG . getNode ( <STR_LIT> , DL , NarrowVT , Op1 , VL ) ; } else return SDValue ( ) ; Op0 = Op0 . getOperand


<s> LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; Result = decodeInstruction ( DecoderTable32 , MI , Insn , Address , this , STI ) ; Size = <NUM_LIT> ; } else { Insn = <STR_LIT> :: read16le ( Bytes . data ( ) ) ; if ( ! STI . getFeatureBits ( ) [ <STR_LIT> ] ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; Result = decodeInstruction ( DecoderTable<ISA_LIT>32Only_16 , MI , Insn , Address , this , STI ) ; if ( Result != MCDisassembler :: Fail ) { Size = <NUM_LIT> ; return Result ; } } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; Result = decodeInstruction ( DecoderTable16 , MI , Insn , Address , this , STI ) ; Size = <NUM_LIT> ; } return Result


<s> return __builtin_ia32_cvttsd2si ( ( __v2df


? default_hidden_stack_protect_fail ( ) : default_external_stack_protect_fail ( ) ;


<s> if ( MI != MBB . end ( ) ) DL = MI -> getDebugLoc ( ) ; MachineInstrBuilder MIB = BuildMI ( MBB , MI , DL , TII . get ( <STR_LIT> ) ) ; AddDefaultPred ( MIB ) ; for ( unsigned i = CSI . size ( ) ; i != <NUM_LIT> ; -- i ) { unsigned Reg = CSI [ i - <NUM_LIT> ] .


<s> SDValue RHS = Op . getOperand ( <NUM_LIT> ) ; <STR_LIT> CC = cast < CondCodeSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> get ( ) ; SDValue TrueVal = Op . getOperand ( <NUM_LIT> ) ; SDValue FalseVal = Op . getOperand ( <NUM_LIT> ) ; unsigned ORIGCC = ~ <NUM_LIT> ; DebugLoc dl = Op .


<s> void <ISA_LIT>TargetAsmStreamer :: emitTextAttribute ( unsigned


<s> bool <ISA_LIT>Operand :: isToken ( ) const


<s> SOffset = MRI -> createVirtualRegister ( & <STR_LIT> ) ; B . buildInstr ( <STR_LIT> ) . addDef ( SOffset ) . addImm ( ImmOffset ) ; ImmOffset =


<s> case PLUS : return const_ok_for_arm ( ARM_SIGN_EXTEND ( - i ) ) ; case MINUS : case XOR : case IOR : return


<s> else Name = ( VT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; SDValue ES = DAG . getExternalFunctionSymbol ( Name ) ; <ISA_LIT>TargetLowering :: ArgListTy Args ; for ( auto AI : { <NUM_LIT> , <NUM_LIT> } ) { ArgListEntry Arg ; Arg . Node = Op . getOperand ( AI ) ; Arg . Ty = Arg . Node . getValueType ( ) . getTypeForEVT ( * DAG . getContext ( ) ) ; Args . push_back (


<s> ( void ) TRI ; RS -> setRegUsed ( BaseReg ) ; } unsigned AddOpc = isUInt < <NUM_LIT> > ( Offset ) ? <STR_LIT> : <STR_LIT> ; BuildMI ( MBB , II , dl , TII . get ( AddOpc ) ) . addReg ( BaseReg , RegState :: Define ) . addReg ( FrameReg ) . addImm ( Offset ) ; Offset = <NUM_LIT> ; KillState = RegState :: Kill ; } switch ( MI . getOpcode ( ) ) { case <STR_LIT> : assert ( ( Offset % <NUM_LIT> == <NUM_LIT> ) && <STR_LIT> ) ; LLVM_FALLTHROUGH ; case <STR_LIT> : case <STR_LIT> : assert ( ( Offset % <NUM_LIT> == <NUM_LIT> ) && <STR_LIT> ) ; LLVM_FALLTHROUGH ; case <STR_LIT> : case <STR_LIT> : LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; BuildMI ( MBB , II , dl , TII . get ( MI . getOpcode ( ) ) , Reg ) . addReg ( BaseReg , KillState ) . addImm ( Offset ) . addMemOperand ( * MI . memoperands_begin ( ) ) ; break ; case <STR_LIT> : assert ( ( Offset % <NUM_LIT> == <NUM_LIT> ) && <STR_LIT> ) ; LLVM_FALLTHROUGH ; case <STR_LIT> : assert ( ( Offset % <NUM_LIT> == <NUM_LIT> ) && <STR_LIT> ) ; LLVM_FALLTHROUGH ; case <STR_LIT> : LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; BuildMI ( MBB , II , dl , TII . get ( MI . getOpcode ( ) ) ) . addReg ( Reg , getKillRegState ( MI . getOperand ( <NUM_LIT> ) . isKill ( ) ) ) . addReg ( BaseReg , KillState ) . addImm ( Offset ) . addMemOperand ( * MI . memoperands_begin ( ) ) ; break ; case <STR_LIT> : LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; BuildMI ( MBB , II , dl , TII . get ( isUInt < <NUM_LIT> > ( Offset ) ? <STR_LIT> : <STR_LIT> ) ) . addReg ( Reg , RegState :: Define ) .


<s> void or1k_expand_atomic_exchange ( rtx operands [ ] ) { rtx retval , mem , val , label ; machine_mode mode ; retval = operands [ <NUM_LIT> ] ; mem = operands [ <NUM_LIT> ] ; val = operands [ <NUM_LIT> ] ; mode = GET_MODE ( mem ) ; if ( reg_overlap_mentioned_p ( retval , val ) ) val = copy_to_reg


<s> return ( __m128i ) vec_cmpeq ( ( __v2di ) __X ,


<s> static scalar_int_mode spu_unwind_word_mode ( void


<s> } DebugLoc DL = MBBI != MBB . end ( ) ? MBBI -> getDebugLoc ( ) : DebugLoc ( ) ; while ( Offset ) { uint64_t ThisVal = ( Offset > Chunk ) ? Chunk : Offset ; MachineInstr * MI = BuildMI ( MBB , MBBI , DL , TII . get ( Opc ) , <STR_LIT>

) . addReg ( <STR_LIT> ) . addImm ( isSub ? - ThisVal : ThisVal ) ;


<s> BasicBlock * IDom = DT -> getNode ( Parent ) -> getIDom ( ) -> getBlock ( ) ; for ( unsigned i = <NUM_LIT> , e = Phi -> getNumIncomingValues ( ) ; i != e ; ++ i ) { Value * Incoming = Phi -> getIncomingValue ( i ) ; if ( Incoming != BoolTrue ) continue ; BasicBlock * From = Phi -> getIncomingBlock ( i ) ; if ( From == IDom ) { CallInst * OldEnd = dyn_cast < CallInst > ( Parent -> getFirstInsertionPt ( ) ) ; if ( OldEnd && OldEnd -> getCalledFunction ( ) == EndCf ) { Value * Args [ ] = { OldEnd -> getArgOperand ( <NUM_LIT> ) , NewPhi } ; Ret = CallInst :: Create ( ElseBreak , Args , <STR_LIT> , OldEnd ) ; continue ; } } TerminatorInst * Insert = From -> getTerminator ( ) ; Value * PhiArg = CallInst :: Create ( Break ,


<s> inline static <STR_LIT> getVLMUL ( unsigned VType ) { unsigned VLMUL =


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . addRequired < <ISA_LIT>SinglePathInfo > ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU


<s> markSuperRegs ( Reserved , <STR_LIT> ) ; markSuperRegs ( Reserved , <STR_LIT> ) ; if ( TFI -> hasFP ( MF ) || STI . isTargetDarwin ( ) ) markSuperRegs ( Reserved , getFramePointerReg ( STI ) ) ; if ( hasBasePointer ( MF ) ) markSuperRegs ( Reserved , BasePtr ) ; if ( STI . isR9Reserved ( ) ) markSuperRegs ( Reserved , <STR_LIT> ) ; if ( ! STI . hasD32 ( ) ) { static_assert ( <STR_LIT> == <STR_LIT> + <NUM_LIT> , <STR_LIT> ) ; for ( unsigned R = <NUM_LIT> ; R < <NUM_LIT> ; ++ R ) markSuperRegs ( Reserved , <STR_LIT> + R ) ; } const TargetRegisterClass & RC = <STR_LIT> ; for ( unsigned Reg : RC ) for ( MCSubRegIterator SI ( Reg , this ) ; SI . isValid ( ) ; ++ SI ) if ( Reserved . test ( * SI ) ) markSuperRegs ( Reserved , Reg ) ; markSuperRegs ( Reserved , <STR_LIT> ) ; assert ( checkAllSuperRegsMarked ( Reserved )


<s> return ConstantPools -> addEntry ( Streamer ,


<s> MCSymbol * FrameLabel = MMI -> getContext ( ) . CreateTempSymbol ( ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) ) . addSym ( FrameLabel ) ; MachineLocation SPDst ( MachineLocation :: VirtualFP ) ; MachineLocation SPSrc ( MachineLocation :: VirtualFP , - FrameSize * <NUM_LIT> ) ; Moves . push_back ( MachineMove ( FrameLabel , SPDst , SPSrc ) ) ; if ( LRSavedOnEntry ) { MachineLocation CSDst ( MachineLocation :: VirtualFP , <NUM_LIT> ) ; MachineLocation CSSrc ( <STR_LIT> ) ; Moves . push_back ( MachineMove ( FrameLabel , CSDst , CSSrc ) ) ; } } if ( saveLR ) { int LRSpillOffset = MFI -> getObjectOffset ( XFI -> getLRSpillSlot ( ) ) ; storeToStack ( MBB , MBBI , <STR_LIT> , LRSpillOffset + FrameSize * <NUM_LIT> , dl , TII ) ; MBB . addLiveIn ( <STR_LIT> ) ; if ( emitFrameMoves ) { MCSymbol * SaveLRLabel = MMI -> getContext ( ) . CreateTempSymbol ( ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) ) . addSym ( SaveLRLabel ) ; MachineLocation CSDst ( MachineLocation :: VirtualFP , LRSpillOffset ) ; MachineLocation CSSrc ( <STR_LIT> ) ; MMI -> getFrameMoves ( ) . push_back ( MachineMove ( SaveLRLabel , CSDst , CSSrc ) ) ; } } } if ( FP ) { int FPSpillOffset = MFI -> getObjectOffset ( XFI -> getFPSpillSlot ( ) ) ; storeToStack ( MBB , MBBI , <STR_LIT> , FPSpillOffset + FrameSize * <NUM_LIT> , dl , TII ) ; MBB . addLiveIn ( <STR_LIT> ) ; if ( emitFrameMoves ) { MCSymbol * SaveR10Label = MMI -> getContext ( ) . CreateTempSymbol ( ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) ) . addSym ( SaveR10Label ) ; MachineLocation CSDst ( MachineLocation :: VirtualFP , FPSpillOffset ) ; MachineLocation CSSrc ( <STR_LIT> ) ; MMI -> getFrameMoves ( ) . push_back ( MachineMove ( SaveR10Label , CSDst , CSSrc ) ) ; } unsigned FramePtr = <STR_LIT> ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , FramePtr ) . addImm ( <NUM_LIT> ) ; if ( emitFrameMoves ) { MCSymbol * FrameLabel = MMI -> getContext ( ) . CreateTempSymbol ( ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) ) . addSym ( FrameLabel ) ; MachineLocation SPDst ( FramePtr ) ; MachineLocation SPSrc ( MachineLocation :: VirtualFP ) ; MMI -> getFrameMoves ( ) . push_back ( MachineMove ( FrameLabel , SPDst , SPSrc ) ) ; } } if ( emitFrameMoves ) { std :: vector < MachineMove > & Moves = MMI -> getFrameMoves ( ) ; std :: vector < std :: pair < MCSymbol * , CalleeSavedInfo > > & SpillLabels


<s> return MBB ; } if ( ! Invert ) CCMask ^= CCValid ; MachineBasicBlock * StartMBB = MBB ; MachineBasicBlock * JoinMBB = splitBlockBefore ( MI , MBB ) ; MachineBasicBlock * FalseMBB = emitBlockAfter ( StartMBB ) ; MBB = StartMBB ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) ) . addImm ( CCValid ) . addImm ( CCMask ) . addMBB ( JoinMBB ) ; MBB -> addSuccessor ( JoinMBB ) ; MBB -> addSuccessor ( FalseMBB ) ; MBB = FalseMBB ; BuildMI ( MBB , DL , TII -> get ( StoreOpcode ) ) . addReg ( SrcReg ) . addOperand ( Base ) . addImm ( Disp ) . addReg ( IndexReg ) ; MBB -> addSuccessor ( JoinMBB ) ; MI -> eraseFromParent


<s> void LLVMInitialize<ISA_LIT>TargetInfo ( ) { RegisterTarget < Triple :: sparc , true > X ( The<ISA_LIT>Target , <STR_LIT> , <STR_LIT> ) ; RegisterTarget < Triple :: sparcv9 , true > Y ( The<ISA_LIT>V9Target , <STR_LIT> , <STR_LIT> ) ; RegisterTarget < Triple :: sparcel , true > Z ( The<ISA_LIT>elTarget


<s> for ( auto T : SLSBLRThunks ) createThunkFunction (


<s> emit_move_insn ( mem , gen_const_mem ( HImode , fnaddr ) ) ; mem = adjust_address ( m_tramp , SImode , <NUM_LIT> ) ; emit_move_insn ( mem , cxt ) ; mem = adjust_address ( m_tramp , SImode


<s> Opc = UseGOTOFF ? <STR_LIT> : <STR_LIT> ; } else { DestReg1 = constrainOperandRegClass ( TII . get ( <STR_LIT> ) , DestReg1 , <NUM_LIT> ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( <STR_LIT> ) , DestReg1 ) . addConstantPoolIndex ( Idx ) . addImm ( <NUM_LIT> ) ) ; Opc = UseGOTOFF ? <STR_LIT> : <STR_LIT> ; } unsigned GlobalBaseReg = AFI -> getGlobalBaseReg ( ) ; if ( GlobalBaseReg == <NUM_LIT> ) { GlobalBaseReg = MRI . createVirtualRegister ( TLI . getRegClassFor ( VT ) ) ; AFI -> setGlobalBaseReg ( GlobalBaseReg ) ; } unsigned DestReg2 = createResultReg ( TLI . getRegClassFor ( VT ) ) ; DestReg2 = constrainOperandRegClass ( TII . get ( Opc ) , DestReg2 , <NUM_LIT> ) ; DestReg1 = constrainOperandRegClass ( TII . get ( Opc ) , DestReg1 , <NUM_LIT> ) ; GlobalBaseReg = constrainOperandRegClass ( TII . get ( Opc ) , GlobalBaseReg , <NUM_LIT> ) ; MachineInstrBuilder MIB = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( Opc ) , DestReg2 ) . addReg ( DestReg1 ) . addReg ( GlobalBaseReg ) ; if ( ! UseGOTOFF ) MIB . addImm (


<s> assert ( ( CC >= <STR_LIT> && CC <= <STR_LIT> ) && <STR_LIT> ) ; return


<s> unsigned Flags = GV -> hasDLLImportStorageClass ( ) ? <STR_LIT> : <STR_LIT> ; if ( ! TM . shouldAssumeDSOLocal ( * GV -> getParent ( ) , GV ) ) return <STR_LIT> | Flags ; if ( useSmallAddressing ( ) && GV ->

hasExternalWeakLinkage ( ) ) return <STR_LIT> | Flags ;


<s> int i , j , repeated , fsmbi , repeat ; gcc_assert ( CONSTANT_P ( op ) ) ; if ( GET_MODE ( op ) != VOIDmode ) mode = GET_MODE ( op ) ; if ( ! flag_pic && mode == V4SImode && GET_CODE ( op ) == CONST_VECTOR && GET_CODE ( CONST_VECTOR_ELT ( op , <NUM_LIT> ) ) != CONST_INT && GET_CODE ( CONST_VECTOR_ELT ( op , <NUM_LIT> ) ) != CONST_DOUBLE ) op = unwrap_const_vec_duplicate ( op ) ; switch ( GET_CODE ( op ) ) { case SYMBOL_REF : case LABEL_REF : return TARGET_LARGE_MEM ? IC_IL2s : IC_IL1s ; case CONST : if ( ! TARGET_LARGE_MEM && GET_CODE ( XEXP ( op , <NUM_LIT> ) ) == PLUS ) { rtx sym = XEXP ( XEXP ( op , <NUM_LIT> ) , <NUM_LIT> ) ; rtx cst = XEXP ( XEXP ( op , <NUM_LIT> ) , <NUM_LIT> ) ; if ( GET_CODE ( sym ) == SYMBOL_REF && GET_CODE ( cst ) == CONST_INT && satisfies_constraint_K ( cst ) ) return IC_IL1s ; } return IC_IL2s ; case HIGH : return IC_IL1s ; case CONST_VECTOR : for ( i = <NUM_LIT> ; i < GET_MODE_NUNITS ( mode ) ; i ++ ) if ( GET_CODE ( CONST_VECTOR_ELT ( op , i ) ) != CONST_INT && GET_CODE ( CONST_VECTOR_ELT ( op , i ) ) != CONST_DOUBLE ) return IC_POOL ; case CONST_INT


<s> unsigned SH = <NUM_LIT> - ME ; SDLoc Dl ( N ) ; SDValue Ops [ ] = { N -> getOperand ( <NUM_LIT> ) , SDValue ( selectI64Imm ( CurDAG , getI64Imm ( - <NUM_LIT> , Dl ) . getNode ( ) ) , <NUM_LIT> ) , getI32Imm ( SH , Dl ) , getI32Imm ( MB , Dl ) } ; CurDAG -> SelectNodeTo ( N , <STR_LIT>


<s> Subtarget . isAAPCS_ABI ( ) ? std :: string ( <STR_LIT> <STR_LIT> <STR_LIT> ) : std :: string ( <STR_LIT> <STR_LIT> <STR_LIT> ) ) , TLInfo ( * this ) , TSInfo ( * this ) , FrameLowering ( Subtarget . hasThumb2 ( ) ? new <ISA_LIT>FrameLowering ( Subtarget ) : ( <ISA_LIT>FrameLowering * ) new Thumb1FrameLowering ( Subtarget ) ) { initAsmInfo ( )


<s> const InstrItineraryData * getInstrItineraryData ( ) const override { return & InstrItins


<s> MVT WVT = <STR_LIT> ( <STR_LIT> , <NUM_LIT> * VT . getVectorNumElements ( ) ) ; if ( VT != <STR_LIT> && ! DAG . getTargetLoweringInfo ( ) . isTypeLegal ( WVT ) ) return SDValue ( ) ; SDValue N0 = N -> getOperand ( <NUM_LIT> ) ; SDValue N1 = N -> getOperand ( <NUM_LIT> ) ; if ( ! Subtarget . hasSSE41 ( ) && ( N0 . getOpcode ( ) == <STR_LIT> && N0 . getOperand ( <NUM_LIT> ) . getScalarValueSizeInBits ( ) <= <NUM_LIT> ) && ( N1 . getOpcode ( ) == <STR_LIT> && N1 . getOperand ( <NUM_LIT> ) . getScalarValueSizeInBits ( ) <= <NUM_LIT> ) ) return SDValue ( ) ; APInt Mask17 = APInt :: getHighBitsSet ( <NUM_LIT> , <NUM_LIT> ) ; if ( ! DAG . MaskedValueIsZero ( N1 , Mask17 ) || ! DAG . MaskedValueIsZero ( N0 , Mask17 ) )


<s> lowerLongBranchADDiu ( const MachineInstr * MI , MCInst & OutMI , int Opcode , MCSymbolRefExpr :: VariantKind Kind ) const { OutMI . setOpcode ( Opcode ) ; for ( unsigned I = <NUM_LIT> , E = <NUM_LIT> ; I != E ; ++ I ) { const MachineOperand & MO = MI -> getOperand ( I ) ; OutMI . addOperand ( LowerOperand ( MO ) ) ; } OutMI . addOperand ( createSub ( MI -> getOperand ( <NUM_LIT> ) . getMBB ( )

, MI -> getOperand ( <NUM_LIT> ) . getMBB ( ) , Kind ) ) ;


<s> IntrinsicInst * II = dyn_cast < IntrinsicInst > ( CI ) ; if ( ! II ) return false ; switch ( II -> getIntrinsicID ( ) ) { case


<s> if ( Subtarget . isTargetXPLINK64 ( ) ) return lowerDYNAMIC_STACKALLOC_XPLINK ( Op , DAG ) ; else return lowerDYNAMIC_STACKALLOC_ELF ( Op


<s> static void version ( const char * progname ) { printf ( <STR_LIT> VERSION_STRING <STR_LIT> , progname


<s> ParseSubtargetFeatures ( GPU , FullFS ) ; if ( getGeneration ( ) <= <ISA_LIT>Subtarget :: NORTHERN_ISLANDS ) { FP32Denormals = false ; FP64Denormals = false ; } if ( MaxPrivateElementSize == <NUM_LIT> )


<s> if ( AddrSpace == <NUM_LIT> ) AM . Segment = CurDAG -> getRegister ( <STR_LIT> , <STR_LIT> ) ; if ( AddrSpace == <NUM_LIT> ) AM . Segment = CurDAG -> getRegister ( <STR_LIT> , <STR_LIT> ) ; } if ( matchAddress ( N , AM ) ) return false ; MVT VT = N . getSimpleValueType ( ) ; if ( AM . BaseType == <ISA_LIT>ISelAddressMode :: RegBase ) { if ( ! AM . Base_Reg . getNode ( ) ) AM . Base_Reg = CurDAG ->


<s> do { FromBits *= <NUM_LIT> ; EVT OutVT = <STR_LIT> ( <STR_LIT> ( FromBits ) , <STR_LIT> / FromBits ) ; PackedOp = DAG . getNode ( UnpackHigh , SDLoc ( PackedOp ) , OutVT , PackedOp ) ; } while ( FromBits != ToBits ) ; return PackedOp


<s> src_lo = gen_lowpart ( word_mode , src ) ; src_hi = gen_highpart ( word_mode , src ) ; emit_insn ( gen_aarch64_movlow_di ( mode , dst , src_lo ) ) ; emit_insn ( gen_aarch64_movhigh_di ( mode , dst , src_hi ) ) ; return ; } else if ( GP_REGNUM_P ( dst_regno ) && FP_REGNUM_P ( src_regno ) ) { dst_lo = gen_lowpart ( word_mode , dst ) ; dst_hi = gen_highpart ( word_mode , dst ) ; emit_insn ( gen_aarch64_movdi_low ( mode , dst_lo , src ) ) ; emit_insn ( gen_aarch64_movdi_high ( mode , dst_hi , src ) ) ; return ; } } dst_lo = gen_lowpart ( word_mode , dst ) ; dst_hi = gen_highpart ( word_mode , dst ) ; src_lo = gen_lowpart ( word_mode , src )


<s> if ( imode == PSImode && mode == HImode && byte == <NUM_LIT> ) rv = gen_rtx_SUBREG ( mode , ireg , byte ) ; else rv = simplify_gen_subreg ( mode , ireg , imode , byte ) ; } else if ( GET_CODE ( r ) == MEM ) { if ( GET_CODE ( XEXP ( r , <NUM_LIT> ) ) == POST_INC && byte == <NUM_LIT> ) byte = <NUM_LIT> ; rv = adjust_address ( r , mode , byte ) ; } else if ( GET_CODE ( r ) == SYMBOL_REF && ( byte == <NUM_LIT> || byte == <NUM_LIT> ) && mode == HImode ) { rv = gen_rtx_ZERO_EXTRACT ( HImode , r , GEN_INT ( <NUM_LIT> ) , GEN_INT (


<s> bool <ISA_LIT>TargetLowering :: preferIncOfAddToSubOfNot ( EVT VT ) const { return VT . isScalarInteger


<s> set_optab_libfunc ( sdiv_optab , SFmode , <STR_LIT> ) ; set_optab_libfunc ( add_optab , DFmode , <STR_LIT> ) ; set_optab_libfunc ( sub_optab , DFmode , <STR_LIT> ) ; set_optab_libfunc ( smul_optab , DFmode , <STR_LIT> ) ; set_optab_libfunc ( sdiv_optab , DFmode , <STR_LIT> ) ; set_conv_libfunc ( sext_optab , DFmode , SFmode , <STR_LIT> ) ; set_conv_libfunc ( trunc_optab , SFmode , DFmode , <STR_LIT> ) ; set_conv_libfunc ( sfix_optab , SImode , SFmode , <STR_LIT> ) ; set_conv_libfunc ( sfix_optab , DImode , SFmode , <STR_LIT> ) ; set_conv_libfunc ( sfix_optab , SImode , DFmode , <STR_LIT> ) ; set_conv_libfunc ( sfix_optab , DImode , DFmode , <STR_LIT> ) ; set_conv_libfunc ( ufix_optab , SImode , SFmode , <STR_LIT> ) ; set_conv_libfunc ( ufix_optab , DImode , SFmode , <STR_LIT> ) ; set_conv_libfunc ( ufix_optab , SImode , DFmode , <STR_LIT> ) ; set_conv_libfunc ( ufix_optab , DImode , DFmode , <STR_LIT> ) ; set_conv_libfunc ( sfloat_optab , SFmode , SImode , <STR_LIT> ) ; set_conv_libfunc ( sfloat_optab , SFmode , DImode , <STR_LIT> ) ; set_conv_libfunc ( sfloat_optab , DFmode , SImode


<s> MVT SubVecVT = SubVec . getSimpleValueType ( ) ; if ( ( OpVT . is256BitVector ( ) || OpVT . is512BitVector ( ) ) && SubVecVT . is128BitVector ( ) && isa < ConstantSDNode > ( Idx ) ) { unsigned IdxVal = cast < ConstantSDNode > ( Idx ) -> getZExtValue ( ) ; return Insert128BitVector ( Vec , SubVec , IdxVal , DAG , dl ) ; } if ( OpVT . is512BitVector ( ) && SubVecVT . is256BitVector ( ) && isa < ConstantSDNode > ( Idx ) ) { unsigned IdxVal = cast < ConstantSDNode > ( Idx ) ->


<s> void ReverseVector ( SmallVectorImpl < NodeT * > & Src ) { size_t sz = Src . size ( ) ; for ( size_t i = <NUM_LIT> ; i < sz / <NUM_LIT> ; ++ i ) { NodeT * t = Src [ i ] ; Src [ i ] = Src [ sz - i - <NUM_LIT> ] ; Src [ sz - i - <NUM_LIT>


<s> bool IsRegCR ; if ( TargetRegisterInfo :: isVirtualRegister ( Reg ) ) { const MachineRegisterInfo * MRI = & DefMI -> getParent ( ) -> getParent ( ) -> getRegInfo ( ) ; IsRegCR = MRI -> getRegClass ( Reg ) -> hasSuperClassEq ( & <STR_LIT> ) || MRI -> getRegClass ( Reg ) -> hasSuperClassEq ( & <STR_LIT> ) ; } else { IsRegCR = <STR_LIT> . contains ( Reg ) || <STR_LIT> . contains ( Reg ) ; } if ( UseMI -> isBranch ( ) && IsRegCR ) { if ( Latency < <NUM_LIT> ) Latency = getInstrLatency ( ItinData , DefMI ) ; unsigned Directive = Subtarget . getDarwinDirective ( ) ; switch ( Directive ) { default : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Latency += <NUM_LIT> ; break ; } } return


<s> unsigned <ISA_LIT>TTIImpl :: getUserCost ( const User * U , ArrayRef < const Value * > Operands ) { if ( U -> getType ( ) -> isVectorTy ( ) ) { std :: pair < int , MVT > LT = TLI -> getTypeLegalizationCost ( DL , U -> getType


<s> bool seen_v_p = false ; for ( size_t i = <NUM_LIT> , c_len = strlen ( constraint ) ; i < c_len ; i += CONSTRAINT_LEN ( constraint [ i ] , constraint + i


<s> unsigned getThumbAddrModeRegRegOpValue ( const MachineInstr & MI ,


<s> void <ISA_LIT>InstPrinter :: printNeg ( const MCInst * MI , unsigned OpNo , const MCSubtargetInfo & STI , raw_ostream & O ) { printIfSet ( MI , OpNo , O , '-'


<s> void <ISA_LIT>AsmPrinter :: EmitEndOfAsmFile ( Module & M ) { if ( Subtarget -> isTargetDarwin ( ) ) { MachineModuleInfoMachO & MMIMacho = MMI -> getObjFileInfo < MachineModuleInfoMachO > ( ) ; MachineModuleInfoMachO :: SymbolListTy Stubs ; Stubs = MMIMacho . GetFnStubList ( ) ; if ( ! Stubs . empty ( ) ) { const MCSection * TheSection = OutContext . getMachOSection ( <STR_LIT> , <STR_LIT> , MCSectionMachO :: S_SYMBOL_STUBS | MCSectionMachO :: S_ATTR_SELF_MODIFYING_CODE | MCSectionMachO :: S_ATTR_PURE_INSTRUCTIONS , <NUM_LIT> , SectionKind :: getMetadata ( ) ) ; OutStreamer . SwitchSection ( TheSection ) ; for ( unsigned i = <NUM_LIT> , e = Stubs . size ( ) ; i != e ; ++ i ) { OutStreamer . EmitLabel ( Stubs [ i ] . first ) ; OutStreamer . EmitSymbolAttribute ( Stubs [ i ] . second . getPointer ( ) , MCSA_IndirectSymbol ) ; const char HltInsts [ ] = { - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> } ; OutStreamer . EmitBytes ( StringRef ( HltInsts , <NUM_LIT> ) , <NUM_LIT> ) ; } Stubs . clear ( ) ; OutStreamer . AddBlankLine ( ) ; } Stubs = MMIMacho . GetGVStubList ( ) ; if ( ! Stubs . empty ( ) ) { const MCSection * TheSection = OutContext . getMachOSection ( <STR_LIT> , <STR_LIT> , MCSectionMachO :: S_NON_LAZY_SYMBOL_POINTERS , SectionKind :: getMetadata ( ) ) ; OutStreamer . SwitchSection ( TheSection ) ; for ( unsigned i = <NUM_LIT> , e = Stubs . size ( ) ; i != e ; ++ i ) { OutStreamer . EmitLabel ( Stubs [ i ] . first ) ; MachineModuleInfoImpl :: StubValueTy & MCSym = Stubs [ i ] . second ; OutStreamer . EmitSymbolAttribute ( MCSym . getPointer ( ) , MCSA_IndirectSymbol ) ; if ( MCSym . getInt ( ) ) OutStreamer . EmitIntValue ( <NUM_LIT> , <NUM_LIT> , <NUM_LIT> ) ; else OutStreamer . EmitValue ( MCSymbolRefExpr :: Create ( MCSym . getPointer ( ) , OutContext ) , <NUM_LIT> , <NUM_LIT> ) ; } Stubs . clear ( ) ; OutStreamer . AddBlankLine ( ) ; } Stubs = MMIMacho . GetHiddenGVStubList ( ) ; if ( ! Stubs . empty ( ) ) { OutStreamer . SwitchSection ( getObjFileLowering ( ) . getDataSection (


<s> if ( VecWidth % RegWidth == <NUM_LIT> ) return VecWidth / RegWidth ; const Align RegAlign ( RegWidth / <NUM_LIT> ) ; if ( ! Alignment || * Alignment > RegAlign ) Alignment = RegAlign ; assert ( Alignment ) ; unsigned AlignWidth = <NUM_LIT> * Alignment -> value ( ) ; unsigned NumLoads = alignTo ( VecWidth , AlignWidth ) / AlignWidth ; return <NUM_LIT> * NumLoads ; } unsigned Cost = VecTy -> getElementType ( ) -> isFloatingPointTy ( ) ? FloatFactor : <NUM_LIT> ; const Align BoundAlignment = std :: min ( Alignment . valueOrOne ( ) , Align ( <NUM_LIT> ) ) ; unsigned AlignWidth = <NUM_LIT> * BoundAlignment . value ( ) ; unsigned NumLoads = alignTo ( VecWidth , AlignWidth )


<s> auto & Context = MF . getMMI ( ) . getContext ( ) ; MCSymbol * S = Context . getOrCreateSymbol ( Twine ( <STR_LIT> ) + Twine ( G -> getGlobal ( ) -> getName ( ) ) ) ; cast < MCSymbolXCOFF > ( S ) -> setGlobalValue ( GV ) ; Callee = DAG . getMCSymbol ( S , PtrVT ) ; } else { unsigned OpFlags = <NUM_LIT> ; if ( UsePlt ) OpFlags = <STR_LIT> ; Callee = DAG . getTargetGlobalAddress ( G -> getGlobal ( ) , dl , Callee . getValueType ( ) , <NUM_LIT> , OpFlags ) ; } needIndirectCall = false ; } if ( ExternalSymbolSDNode * S = dyn_cast < ExternalSymbolSDNode > ( Callee ) ) { unsigned char OpFlags = <NUM_LIT> ; if ( UsePlt ) OpFlags = <STR_LIT> ; Callee = DAG . getTargetExternalSymbol ( S -> getSymbol ( ) , Callee . getValueType ( ) , OpFlags ) ; needIndirectCall = false ; } if ( isPatchPoint ) { needIndirectCall = false ; } if ( needIndirectCall ) { SDValue MTCTROps [ ] = { Chain , Callee , InFlag } ; if ( isSVR4ABI && is<ISA_LIT>64 && ! isELFv2ABI ) { SDValue LDChain = CallSeqStart . getValue ( CallSeqStart -> getNumValues ( ) - <NUM_LIT> ) ; if ( LDChain . getValueType ( ) == <STR_LIT> ) LDChain = CallSeqStart . getValue ( CallSeqStart -> getNumValues ( ) - <NUM_LIT> ) ; auto MMOFlags = Subtarget . hasInvariantFunctionDescriptors ( ) ? ( MachineMemOperand :: MODereferenceable | MachineMemOperand :: MOInvariant ) : MachineMemOperand :: MONone ; MachinePointerInfo MPI ( CS ? CS . getCalledValue ( ) : nullptr ) ; SDValue LoadFuncPtr = DAG . getLoad ( <STR_LIT> , dl , LDChain , Callee , MPI , <NUM_LIT> , MMOFlags ) ; SDValue PtrOff = DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ; SDValue AddPtr = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Callee , PtrOff ) ; SDValue LoadEnvPtr = DAG . getLoad ( <STR_LIT> , dl , LDChain , AddPtr , MPI . getWithOffset ( <NUM_LIT> ) , <NUM_LIT> , MMOFlags ) ; SDValue TOCOff = DAG . getIntPtrConstant ( <NUM_LIT>


<s> SDLoc Dl ( N ) ; if ( isNullConstant ( Op2 ) ) { auto * CA = CurDAG -> getMachineNode ( Subtarget -> has2E3 ( ) ? <STR_LIT> : <STR_LIT> , Dl , Type1 ) ; NewNode = CurDAG -> getMachineNode ( Subtarget -> has2E3 ( ) ? <STR_LIT> : <STR_LIT> , Dl , { Type0 , Type1 } , { Op0 , Op1 , SDValue ( CA , <NUM_LIT> ) } ) ; } else if ( isOneConstant ( Op2 ) ) { auto * CA = CurDAG -> getMachineNode ( Subtarget -> has2E3 ( ) ? <STR_LIT> : <STR_LIT> , Dl , Type1 ) ; NewNode = CurDAG -> getMachineNode ( Subtarget -> has2E3 ( ) ? <STR_LIT> : <STR_LIT> , Dl , { Type0 , Type1 } , { Op0 , Op1 , SDValue ( CA , <NUM_LIT> ) } ) ; } else { auto CarryIn = InvertCarryFlag ( Subtarget , CurDAG , Dl , Op2 ) ; NewNode = CurDAG -> getMachineNode ( Subtarget -> has2E3 ( ) ? <STR_LIT> : <STR_LIT> , Dl , { Type0 , Type1 } , { Op0 , Op1 , CarryIn } ) ; } auto CarryOut = InvertCarryFlag ( Subtarget , CurDAG , Dl


<s> void <ISA_LIT>AsmPrinter :: EmitInstruction ( const MachineInstr * MI ) { MCInst


<s> SDValue Ops [ <NUM_LIT> ] ; size_t OpIdx = <NUM_LIT> ; Ops [ OpIdx ++ ] = Op . getOperand ( <NUM_LIT> ) ; Ops [ OpIdx ++ ] = Op . getOperand ( <NUM_LIT> ) ; for ( size_t I = <NUM_LIT> , Lanes = Mask . size ( ) ; I < Lanes ; ++ I ) { for ( size_t J = <NUM_LIT> ; J < LaneBytes ; ++ J ) { uint64_t ByteIndex = Mask [ I ] == - <NUM_LIT> ? <NUM_LIT> : ( uint64_t ) Mask [ I ] * LaneBytes + J ; Ops [ OpIdx ++ ] = DAG . getConstant ( ByteIndex , DL , <STR_LIT> ) ; } } return DAG . getNode ( <STR_LIT> , DL , Op . getValueType


<s> return getPCRelEncoding ( MI , OpNum , Fixups , <STR_LIT> , <NUM_LIT>


<s> return ( __mmask8 ) __builtin_ia32_ucmpq512_mask ( ( __v8di ) __X , ( __v8di )


<s> MachineBasicBlock :: iterator <ISA_LIT>FrameLowering :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { const <ISA_LIT>InstrInfo & TII = * static_cast < const <ISA_LIT>InstrInfo * > ( MF . getSubtarget ( ) . getInstrInfo ( ) ) ; MachineInstr & Old = * I ; DebugLoc DL = Old . getDebugLoc ( ) ; unsigned Amount = TII . getFrameSize ( Old ) ; if ( Amount != <NUM_LIT> ) { unsigned Opc = Old . getOpcode ( ) ; if ( Opc == <STR_LIT> ) { BuildMI ( MBB , I , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( Amount ) ; } else { assert ( Opc == <STR_LIT> ) ; BuildMI ( MBB , I , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( Amount ) ; } } return MBB . erase


<s> RegisterSubReg DR = MI . getOperand ( <NUM_LIT> ) ; RegisterSubReg SR = MI . getOperand ( <NUM_LIT> ) ; if ( ! DR . R . isVirtual ( ) ) continue ; if ( ! SR . R . isVirtual ( ) ) continue ; if ( MRI -> getRegClass ( DR . R ) != PredRC ) continue ; if ( MRI -> getRegClass ( SR . R ) != PredRC ) continue ; assert ( ! DR . S && ! SR . S && <STR_LIT> ) ; MRI -> replaceRegWith ( DR . R , SR . R ) ; Erase . insert ( & MI


<s> static void count_unit_reqs ( unit_req_table reqs , rtx_insn * head , rtx_insn * tail ) { rtx_insn * insn ; memset ( reqs , <NUM_LIT> , sizeof ( unit_req_table ) ) ; for ( insn = head ; insn != NEXT_INSN ( tail ) ; insn = NEXT_INSN ( insn ) ) { int side1 , side2 , req1 , req2 ; switch ( get_unit_reqs ( insn , & req1 , & side1 , & req2 , & side2 ) ) { case <NUM_LIT> : reqs [ side2 ] [ req2 ] ++ ; case


<s> void addMRSSystemRegisterOperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT>


<s> SDValue T = DAG . getNode ( <STR_LIT> , dl , RegVT , Copy , DAG . getConstant ( <NUM_LIT> , dl , RegVT ) ) ; Copy = DAG . getSetCC ( dl , <STR_LIT> , T , DAG . getConstant ( <NUM_LIT> , dl , RegVT ) , <STR_LIT> ) ; } else { unsigned RegSize = RegVT . getSizeInBits ( ) ; assert ( RegSize == <NUM_LIT> || RegSize == <NUM_LIT> || Subtarget . isHVXVectorType ( RegVT ) ) ; } InVals . push_back ( Copy ) ; MRI . addLiveIn ( VA . getLocReg ( ) , VReg ) ; } else { assert ( VA . isMemLoc ( ) && <STR_LIT> ) ; unsigned ObjSize = Flags . isByVal ( ) ? Flags . getByValSize ( ) : VA . getLocVT ( ) . getStoreSizeInBits ( ) / <NUM_LIT> ; int Offset = HEXAGON_LRFP_SIZE + VA . getLocMemOffset ( ) ; int FI = MFI . CreateFixedObject ( ObjSize , Offset , true ) ; SDValue FIN = DAG . getFrameIndex ( FI , <STR_LIT> ) ; if ( Flags . isByVal ( )


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const { AU . setPreservesAll ( ) ; AU . addRequired < MachineModuleInfo > ( ) ; AU . addRequired < DwarfWriter > (


<s> BlockMask = VPTMaskValue :: TTTT ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } ; MachineInstrBuilder MIBuilder ; unsigned NewOpcode ; MachineInstr * VCMP = findVCMPToFoldIntoVPST ( MI , RDA , NewOpcode ) ; if ( VCMP ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; VCMP -> dump ( ) ) ; MIBuilder = BuildMI ( Block , MI , dl , TII -> get ( NewOpcode ) ) ; MIBuilder . addImm ( BlockMask ) ; MIBuilder . add ( VCMP -> getOperand ( <NUM_LIT> ) ) ; MIBuilder . add ( VCMP -> getOperand ( <NUM_LIT> ) ) ; MIBuilder . add ( VCMP -> getOperand ( <NUM_LIT> ) ) ; VCMP -> eraseFromParent ( ) ; } else { MIBuilder = BuildMI ( Block , MI , dl , TII -> get ( <STR_LIT> ) ) ; MIBuilder . addImm ( BlockMask ) ; } finalizeBundle ( Block , MachineBasicBlock :: instr_iterator ( MIBuilder . getInstr ( ) ) ,


<s> EVT VT = Op . getValueType ( ) ; DebugLoc dl = Op . getDebugLoc ( ) ; unsigned FrameReg = <STR_LIT> ; uint64_t depth = Op . getConstantOperandVal ( <NUM_LIT> ) ; SDValue FrameAddr ; if ( depth == <NUM_LIT> ) FrameAddr = DAG . getCopyFromReg ( DAG . getEntryNode ( ) , dl , FrameReg , VT ) ; else { SDValue Chain = getFLUSHW ( Op , DAG ) ; FrameAddr = DAG . getCopyFromReg ( Chain , dl , FrameReg


<s> return true ; } tree func_optimize = DECL_FUNCTION_SPECIFIC_OPTIMIZATION ( fndecl ) ; old_optimize = build_optimization_node ( & global_options , & global_options_set ) ; func_optimize = DECL_FUNCTION_SPECIFIC_OPTIMIZATION ( fndecl ) ; if ( func_optimize && func_optimize != old_optimize ) cl_optimization_restore ( & global_options , & global_options_set , TREE_OPTIMIZATION ( func_optimize ) ) ; cl_target_option_save ( & cur_target , & global_options , & global_options_set ) ; if ( existing_target ) { struct cl_target_option * existing_options = TREE_TARGET_OPTION ( existing_target ) ; if ( existing_options ) cl_target_option_restore ( & global_options , & global_options_set , existing_options ) ; } else cl_target_option_restore ( & global_options , & global_options_set , TREE_TARGET_OPTION ( target_option_current_node ) ) ; ret = aarch64_process_target_attr ( args ) ; if ( ret ) { aarch64_override_options_internal ( & global_options ) ; if ( TARGET_SIMD ) { tree saved_current_target_pragma = current_target_pragma ; current_target_pragma = NULL ; aarch64_init_simd_builtins ( ) ; current_target_pragma = saved_current_target_pragma ; } new_target = build_target_option_node ( & global_options , & global_options_set ) ; } else new_target = NULL ; new_optimize = build_optimization_node ( & global_options , & global_options_set ) ; if ( fndecl && ret ) { DECL_FUNCTION_SPECIFIC_TARGET ( fndecl ) = new_target ; if ( old_optimize != new_optimize ) DECL_FUNCTION_SPECIFIC_OPTIMIZATION ( fndecl ) = new_optimize ; } cl_target_option_restore ( & global_options , & global_options_set , & cur_target ) ; if ( old_optimize != new_optimize ) cl_optimization_restore ( & global_options , & global_options_set , TREE_OPTIMIZATION ( old_optimize ) ) ; return ret


<s> bool <ISA_LIT>InstrInfo :: protectRegisterSpill ( unsigned Reg , const MachineFunction * MF ) const { const MachineRegisterInfo & MRI = MF -> getRegInfo ( ) ; const TargetRegisterInfo * TRI = MF -> getTarget ( )


<s> static bool msp430_check_index_not_high_mem ( rtx op ) { if ( CONST_INT_P ( op ) && IN_RANGE ( INTVAL ( op ) , HOST_WIDE_INT_M1U << <NUM_LIT> , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) ) return true ; return false


<s> for ( Instruction & I : instructions ( & F ) ) { for ( Value * Op : I . operand_values ( ) ) { Constant * Cst = dyn_cast < Constant


<s> const <ISA_LIT>InstrInfo * llvm :: create<ISA_LIT>SEInstrInfo ( <ISA_LIT>TargetMachine & TM ) { return new <ISA_LIT>SEInstrInfo ( TM


<s> unsigned <ISA_LIT>MCCodeEmitter :: encodeImm ( const MCInst & MI , unsigned OpNo , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { auto MO = MI . getOperand ( OpNo ) ; if ( MO . isExpr ( ) ) { if ( isa < <ISA_LIT>MCExpr > ( MO . getExpr ( ) ) ) { return getExprOpValue ( MO . getExpr ( ) , Fixups , STI ) ; } MCFixupKind FixupKind = static_cast < MCFixupKind > ( Fixup ) ; Fixups . push_back ( MCFixup :: create ( Offset , MO . getExpr ( ) , FixupKind , MI . getLoc ( ) ) ) ; return


<s> bool <ISA_LIT>Subtarget :: enablePostRAMachineScheduler ( ) const { if ( ! enableMachineScheduler ( ) ) return


<s> llvm_unreachable ( <STR_LIT> ) ; case CallingConv :: Fast : if ( Subtarget -> hasVFP2 ( ) && ! isVarArg ) { if ( ! Subtarget -> isAAPCS_ABI ( ) ) return ( Return ? RetFastCC_<ISA_LIT>_APCS : FastCC_<ISA_LIT>_APCS ) ; return ( Return ? RetCC_<ISA_LIT>_AAPCS_VFP : CC_<ISA_LIT>_AAPCS_VFP ) ; } case CallingConv :: C : case CallingConv :: CXX_FAST_TLS : if ( Subtarget -> isAAPCS_ABI ( ) ) { if ( Subtarget -> hasVFP2 ( ) && TM . Options . FloatABIType == FloatABI :: Hard && ! isVarArg ) return ( Return ? RetCC_<ISA_LIT>_AAPCS_VFP : CC_<ISA_LIT>_AAPCS_VFP ) ; else return ( Return ? RetCC_<ISA_LIT>_AAPCS : CC_<ISA_LIT>_AAPCS ) ; } else { return ( Return ? RetCC_<ISA_LIT>_APCS : CC_<ISA_LIT>_APCS ) ; } case CallingConv


<s> int label_num = constants ? CODE_LABEL_NUMBER ( constants -> label ) : <NUM_LIT> ; struct mips16_constant * c , * next ; int align ; align = <NUM_LIT> ; if ( constants ) insn = emit_insn_after ( gen_consttable ( GEN_INT ( label_num ) ) , insn ) ; for ( c = constants ; c != NULL ; c = next ) { if ( align < GET_MODE_SIZE ( c


<s> void onRParen ( ) { PrevState = State ; switch ( State ) { default : State = IES_ERROR ; break ; case IES_INTEGER : case IES_OFFSET : case IES_REGISTER : case


<s> return ( ( qword ) ( vec_ld ( si_to_uint ( ( qword ) ( vec_add ( ( vec_uint4 ) ( a ) , (

vec_uint4 ) ( b ) ) ) ) , ( vector unsigned char * ) ( <NUM_LIT> ) ) ) ) ;


<s> else Register = RegisterTableSPU [ RegNo ] ; if ( Register == ~ <NUM_LIT> ) return MCDisassembler :: Fail ; Inst . addOperand ( MCOperand :: createReg ( Register ) ) ; return MCDisassembler :: Success


<s> uint32_t Binary = getBinaryCodeForInstr ( TmpInst , Fixups , STI ) ; unsigned Opcode = TmpInst . getOpcode ( ) ; if ( ( Opcode != <STR_LIT> ) && ( Opcode != <STR_LIT> ) && ( Opcode != <STR_LIT> ) && ! Binary ) llvm_unreachable ( <STR_LIT> ) ; int NewOpcode = - <NUM_LIT> ; if ( isMicro<ISA_LIT> ( STI ) ) { if ( is<ISA_LIT>32r6 ( STI ) ) { NewOpcode = <STR_LIT> ( Opcode , <STR_LIT> ) ; if ( NewOpcode == - <NUM_LIT> ) NewOpcode = <STR_LIT> ( Opcode , <STR_LIT> ) ; } else NewOpcode = <STR_LIT> ( Opcode , <STR_LIT> ) ; if ( NewOpcode == - <NUM_LIT> ) NewOpcode = <STR_LIT> ( Opcode , <STR_LIT>


<s> explicit <ISA_LIT>FunctionInfo ( MachineFunction & MF ) : BytesInStackArgArea ( <NUM_LIT> ) , ArgumentStackToRestore ( <NUM_LIT> ) , HasStackFrame ( false ) , NumLocalDynamicTLSAccesses ( <NUM_LIT> ) , VarArgsStackIndex ( <NUM_LIT> ) , VarArgsGPRIndex ( <NUM_LIT> ) , VarArgsGPRSize ( <NUM_LIT> ) , VarArgsFPRIndex ( <NUM_LIT> ) , VarArgsFPRSize ( <NUM_LIT> ) { ( void


<s> assert ( ShlAmount < <NUM_LIT> && <STR_LIT> ) ; int ShrAmount = - ShlAmount ; ShiftNode = CurDAG -> getMachineNode ( UBFMOpc , SDLoc ( Op ) , VT , Op , CurDAG -> getTargetConstant ( ShrAmount , VT ) , CurDAG -> getTargetConstant ( BitWidth - <NUM_LIT> , VT ) ) ; } return SDValue ( ShiftNode ,


<s> static SDValue combineShuffle ( SDNode * N , SelectionDAG & DAG , TargetLowering :: DAGCombinerInfo & DCI , const <ISA_LIT>Subtarget & Subtarget ) { SDLoc dl ( N ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; if ( ! DCI . isBeforeLegalize ( ) && ! TLI . isTypeLegal ( VT . getVectorElementType ( ) ) ) return SDValue ( ) ; if ( TLI . isTypeLegal ( VT ) ) if ( SDValue AddSub = combineShuffleToAddSub ( N , Subtarget , DAG ) ) return AddSub ; if ( TLI . isTypeLegal ( VT ) && Subtarget . hasFp256 ( ) && VT . is256BitVector ( ) && N -> getOpcode ( ) == <STR_LIT> ) return combineShuffle256 ( N , DAG , DCI , Subtarget ) ; if ( ! DCI . isBeforeLegalize ( ) && DCI . isBeforeLegalizeOps ( ) && N -> getOpcode ( ) == <STR_LIT> && N -> getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> && N -> getOperand ( <NUM_LIT> ) . isUndef ( ) && N -> getOperand ( <NUM_LIT> ) . hasOneUse ( ) ) { SDValue N0 = N -> getOperand ( <NUM_LIT> ) ; SDValue N1 = N -> getOperand ( <NUM_LIT> ) ; SDValue BC0 = N0 . getOperand ( <NUM_LIT> ) ; EVT SVT = BC0 . getValueType ( ) ; unsigned Opcode = BC0 . getOpcode ( ) ; unsigned NumElts = VT . getVectorNumElements ( ) ; if ( BC0 . hasOneUse ( ) && SVT . isVector ( ) && SVT . getVectorNumElements ( ) * <NUM_LIT> == NumElts && TLI . isOperationLegal ( Opcode , VT ) ) { bool CanFold = false ; switch ( Opcode ) { default : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : CanFold = true ; } unsigned SVTNumElts = SVT . getVectorNumElements ( ) ; ShuffleVectorSDNode * SVOp = cast < ShuffleVectorSDNode > ( N ) ; for ( unsigned i = <NUM_LIT> , e = SVTNumElts ; i != e && CanFold ; ++ i ) CanFold = SVOp -> getMaskElt ( i ) == ( int ) ( i * <NUM_LIT> ) ; for ( unsigned i = SVTNumElts , e = NumElts ; i != e && CanFold ; ++ i ) CanFold = SVOp -> getMaskElt ( i ) < <NUM_LIT> ; if ( CanFold ) { SDValue BC00 = DAG . getBitcast ( VT , BC0 . getOperand ( <NUM_LIT> ) ) ; SDValue BC01 = DAG . getBitcast ( VT , BC0 . getOperand ( <NUM_LIT> ) ) ; SDValue NewBinOp = DAG . getNode ( BC0 . getOpcode ( ) , dl , VT , BC00 , BC01 ) ; return DAG . getVectorShuffle ( VT , dl , NewBinOp , N1 ,


<s> static bool isT1i32Load ( unsigned Opc )


<s> if ( EltVT . getSizeInBits ( ) == <NUM_LIT> && isa < ConstantSDNode > ( N2 ) ) { if ( N1 . getValueType ( ) != <STR_LIT> ) N1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N1 ) ; if ( N2 . getValueType ( ) != <STR_LIT> ) N2 = DAG . getIntPtrConstant ( cast < ConstantSDNode > ( N2 ) -> getZExtValue ( ) ) ; return DAG . getNode ( <STR_LIT> , dl , VT ,


<s> if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) { copyPhysReg ( MBB , MBBI , DL , RI . getSubReg ( DestReg , <STR_LIT> ) , RI . getSubReg ( SrcReg , <STR_LIT> ) , KillSrc ) ; copyPhysReg ( MBB , MBBI , DL , RI . getSubReg ( DestReg , <STR_LIT> ) , RI . getSubReg ( SrcReg , <STR_LIT> ) , KillSrc ) ; return ; } if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) { emitGRX32Move ( MBB , MBBI , DL , DestReg , SrcReg , <STR_LIT> , <NUM_LIT> , KillSrc ) ; return ; } unsigned Opcode ; if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opcode = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) )


<s> bool <ISA_LIT>TargetLowering :: isTruncateFree ( Type * Source , Type


<s> const MCOperand MO = MI . getOperand ( OpIdx ) ; if ( MO . isExpr ( ) ) return :: getBranchTargetOpValue ( MI , OpIdx , <STR_LIT> , Fixups ) ; int64_t offset = MO . getImm ( ) ; uint32_t Val = <NUM_LIT> ; int SoImmVal ; if ( offset == INT32_MIN ) { Val = <NUM_LIT> ; SoImmVal = <NUM_LIT> ; } else if ( offset < <NUM_LIT> ) { Val = <NUM_LIT> ; offset *= - <NUM_LIT> ; SoImmVal = <STR_LIT> ( offset ) ; if ( SoImmVal == - <NUM_LIT> ) { Val = <NUM_LIT> ; offset *= - <NUM_LIT> ; SoImmVal = <STR_LIT> ( offset ) ; } } else { SoImmVal = <STR_LIT> ( offset ) ; if ( SoImmVal == - <NUM_LIT> ) { Val = <NUM_LIT> ; offset *= - <NUM_LIT> ; SoImmVal = <STR_LIT> ( offset ) ; } } assert ( SoImmVal != - <NUM_LIT> && <STR_LIT>


<s> if ( Triple . getArch ( ) == Triple :: x86_64 ) { PrivateGlobalPrefix = <STR_LIT> ; PrivateLabelPrefix = <STR_LIT> ; PointerSize = <NUM_LIT> ; WinEHEncodingType = WinEH :: EncodingType :: Itanium ; ExceptionsType = ExceptionHandling


<s> int <ISA_LIT>FrameInfo :: getFrameIndexReference ( const MachineFunction & MF , int FI , unsigned & FrameReg ) const { return ResolveFrameIndexReference ( MF , FI , FrameReg , <NUM_LIT>


<s> assert ( Inst . getOperand ( <NUM_LIT> ) . isImm ( ) ) ; int64_t Shift = Inst . getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( Shift <= <NUM_LIT> ) return ; Shift -= <NUM_LIT> ; Inst . getOperand ( <NUM_LIT> ) . setImm ( Shift ) ; switch ( Inst . getOpcode (


<s> InstructionSelector :: ComplexRendererFns <ISA_LIT>InstructionSelector :: selectDS128Bit8ByteAligned ( MachineOperand & Root ) const { return selectDSReadWrite2 ( Root ,


<s> if ( code == MULT && CONST_INT_P ( XEXP ( op , <NUM_LIT> ) ) && exact_log2 ( INTVAL ( XEXP ( op , <NUM_LIT> ) ) ) > <NUM_LIT> ) return XEXP ( op , <NUM_LIT> ) ; else if ( code == ROTATE && CONST_INT_P ( XEXP ( op , <NUM_LIT> ) ) ) return XEXP ( op , <NUM_LIT> ) ; else if ( code == ROTATERT || code == ASHIFT || code == LSHIFTRT || code == ASHIFTRT ) { if ( ! CONST_INT_P ( XEXP ( op , <NUM_LIT> ) ) ) * shift_reg = XEXP ( op , <NUM_LIT> ) ; return XEXP ( op , <NUM_LIT> ) ; } return


<s> std :: set < MachineBasicBlock * > :: const_iterator It = MBBs . begin ( ) ; std :: set < MachineBasicBlock * > :: const_iterator E = MBBs . end ( ) ; for ( CommonDom = * It ; It != E && CommonDom


<s> unsigned HOST_WIDE_INT offset ; int extra ; rtx addr = XEXP ( op , <NUM_LIT> ) ; if ( ! offsettable_address_p ( false , mode , addr ) ) return false ; op = address_offset ( addr ) ; if ( op == NULL_RTX ) return true ; offset = INTVAL (


<s> unsigned SchedClass = TID . getSchedClass ( ) ; const InstrStage * IS = ResourceTracker -> getInstrItins ( ) -> beginStage ( SchedClass ) ; unsigned FuncUnits = IS -> getUnits


<s> StringRef String = Token . getString ( ) ; if ( Token . is ( AsmToken :: TokenKind :: LCurly ) || Token . is ( AsmToken :: TokenKind :: RCurly ) ) return false ; if ( String . lower ( ) == <STR_LIT> && Second . is ( AsmToken :: Colon ) && Third . getString ( ) . lower ( ) == <STR_LIT> ) return false ; if ( ! Token . is ( AsmToken :: TokenKind :: Identifier ) ) return true ; if ( ! matchRegister ( String . lower ( ) ) ) return true ; assert ( Second . is ( AsmToken ::


<s> for ( MachineBasicBlock * MBB : L -> getBlocks ( ) ) { for ( MachineBasicBlock :: iterator MII = MBB -> begin ( ) , E = MBB -> end ( ) ; MII !=


<s> if ( ! is32Bit ) return MCDisassembler :: Fail ; DecodeStatus status = DecodeDataRegsRegisterClass ( Inst , d , Address , Decoder ) ; if ( status != MCDisassembler :: Success ) return status ; status = DecodeDataRegsRegisterClass ( Inst , s1 , Address , Decoder ) ; if ( status != MCDisassembler :: Success ) return status ; Inst . addOperand ( MCOperand :: createImm ( const4 ) ) ; status = DecodeDataRegsRegisterClass ( Inst , s3 , Address , Decoder ) ; if ( status != MCDisassembler :: Success ) return


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Log2Size = llvm :: Log2_32 ( <NUM_LIT> ) ; switch ( Sym -> getKind ( ) ) { default : assert ( <NUM_LIT> && <STR_LIT> ) ; case MCSymbolRefExpr :: VK_PAGEOFF : RelocType = unsigned ( MachO :: ARM64_RELOC_PAGEOFF12 ) ; return true ; case MCSymbolRefExpr :: VK_GOTPAGEOFF : RelocType = unsigned ( MachO :: ARM64_RELOC_GOT_LOAD_PAGEOFF12 ) ; return true ; case MCSymbolRefExpr :: VK_TLVPPAGEOFF : RelocType = unsigned ( MachO :: ARM64_RELOC_TLVP_LOAD_PAGEOFF12 ) ; return true ; } case <STR_LIT> : Log2Size = llvm :: Log2_32 ( <NUM_LIT> ) ; switch ( Sym -> getKind ( ) ) { default : Asm . getContext ( ) . FatalError ( Fixup . getLoc ( ) , <STR_LIT> ) ; case MCSymbolRefExpr :: VK_PAGE : RelocType = unsigned ( MachO :: ARM64_RELOC_PAGE21 ) ; return true ; case MCSymbolRefExpr :: VK_GOTPAGE : RelocType = unsigned ( MachO :: ARM64_RELOC_GOT_LOAD_PAGE21 ) ; return true ; case MCSymbolRefExpr


<s> static std :: vector < uint32_t > getThreeInt32 ( MDNode * Node ) { assert ( Node -> getNumOperands ( ) == <NUM_LIT> ) ; std :: vector < uint32_t > V ; for ( const MDOperand & Op : Node -> operands ( ) ) { const ConstantInt * CI = mdconst :: extract < ConstantInt


<s> void prettyPrintAsm ( MCInstPrinter & InstPrinter , raw_ostream & OS , const MCInst & Inst , const MCSubtargetInfo & STI ) override { assert ( <ISA_LIT>MCInstrInfo :: isBundle ( Inst ) ) ; assert ( <ISA_LIT>MCInstrInfo :: bundleSize ( Inst ) <= HEXAGON_PACKET_SIZE ) ; std :: string Buffer ; { raw_string_ostream TempStream ( Buffer ) ; InstPrinter . printInst ( & Inst , TempStream , <STR_LIT> , STI ) ; } StringRef Contents ( Buffer ) ; auto PacketBundle = Contents . rsplit ( '\n' ) ; auto HeadTail = PacketBundle . first . split ( '\n' ) ; StringRef Separator = <STR_LIT> ; StringRef Indent = <STR_LIT> ; OS << <STR_LIT> ; while ( ! HeadTail . first . empty ( ) ) { StringRef


<s> if ( VT . isVector ( ) ) return scalarizeVectorLoad ( LN , DAG ) ; SDValue Ops [ <NUM_LIT> ] ; std :: tie ( Ops [ <NUM_LIT> ] , Ops [ <NUM_LIT> ] ) = expandUnalignedLoad ( LN , DAG ) ; return DAG . getMergeValues ( Ops , SDLoc ( N ) ) ; } if ( ! IsFast ) return SDValue ( ) ; } if ( ! shouldCombineMemoryType ( VT ) ) return SDValue ( ) ; EVT NewVT = getEquivalentMemType ( * DAG . getContext ( ) , VT ) ; SDValue NewLoad = DAG . getLoad ( NewVT , SL , LN -> getChain ( ) , LN -> getBasePtr ( ) , LN -> getMemOperand ( ) ) ; SDValue BC = DAG . getNode ( <STR_LIT> , SL , VT , NewLoad ) ; DCI . CombineTo ( N , BC , NewLoad . getValue ( <NUM_LIT> ) ) ; return SDValue ( N


<s> rtx insn ; if ( low == high ) insn = emit_insn ( gen_stack_push ( gen_rtx_REG ( SImode , low ) ) ) ; else insn = emit_insn ( gen_stack_pushm ( GEN_INT ( ( ( high - low ) + <NUM_LIT> ) * UNITS_PER_WORD ) , gen_rx_store_vector (


<s> return rs6000_hard_regno_nregs [ mode ] [ regno


<s> if ( I == MBB . end ( ) ) return <NUM_LIT> ; if ( ! isUncondBranchOpcode ( I -> getOpcode ( ) ) && ! isCondBranchOpcode ( I -> getOpcode ( ) ) ) return <NUM_LIT> ; I -> eraseFromParent ( ) ; I = MBB . end ( ) ; if ( I == MBB . begin ( ) ) return <NUM_LIT> ; -- I ; if ( ! isCondBranchOpcode ( I -> getOpcode (


<s> bool isBoundCtrl ( ) const { return isImmTy (


<s> unsigned getMaxWavesPerCU ( ) const { if ( getGeneration ( ) >= <ISA_LIT>Subtarget :: SOUTHERN_ISLANDS ) return <NUM_LIT> ; llvm_unreachable (