<s> virtual const <ISA_LIT>SelectionDAGInfo * getSelectionDAGInfo ( ) const { return &


<s> static bool hasSameArgumentList ( const Function * CallerFn , ImmutableCallSite * CS ) { if ( CS -> arg_size ( ) != CallerFn -> arg_size ( ) ) return false ; ImmutableCallSite :: arg_iterator CalleeArgIter = CS -> arg_begin (


<s> Init<ISA_LIT>MCRegisterInfo ( X , <STR_LIT> ) ; return


<s> for ( const Use & RootInstUse : RootInst -> uses ( ) ) { User * RootInstUser = RootInstUse . getUser ( ) ; if ( auto * InsertUserCast = dyn_cast < InsertElementInst > ( RootInstUser ) ) { processInsertElementNode ( InsertUserCast , CurrLoop , PHI , TensorId ) ; RootInst = InsertUserCast ; Nested_Ins = true ; break ; } else if ( auto * Intrins = dyn_cast < IntrinsicInst > ( RootInstUser ) ) { <STR_LIT> Inid = Intrins -> getIntrinsicID ( ) ; int index = - <NUM_LIT> ; if ( Inid == <STR_LIT> || Inid == <STR_LIT> ) { if ( Inid == <STR_LIT> ) { int OperandIndex = <NUM_LIT> ; if ( dyn_cast < llvm :: ConstantInt > ( Intrins -> getOperand ( OperandIndex ) ) ) { if ( dyn_cast < Instruction > ( Intrins -> getOperand ( <NUM_LIT> ) ) ) { if ( ! dyn_cast < ICmpInst > ( Intrins -> getOperand ( <NUM_LIT> ) ) ) FallBackVec . insert ( TensorId ) ; else { if ( auto * Icmp = dyn_cast < ICmpInst > ( Intrins -> getOperand ( <NUM_LIT> ) ) ) if ( ! dyn_cast < ConstantInt > ( Icmp -> getOperand ( <NUM_LIT> ) ) ) FallBackVec . insert ( TensorId ) ; } } index = dyn_cast < llvm :: ConstantInt > ( Intrins -> getOperand ( OperandIndex ) ) -> getZExtValue ( ) ; CurrLoop = compareStepValuesForAddMask ( PHI , CurrLoop ) ; int64_t AddMaskStep = getAddMaskStepVar ( Intrins ) ; if ( AddMaskStep != INVALID_STRIDE ) { unsigned Count = fetchIndexFromOperand ( index ) ; unsigned UnrollCount = <NUM_LIT> ; if ( getScevInfo ( CurrLoop ) ) { UnrollCount = getScevInfo ( CurrLoop ) -> getLoopUnrollCount ( CurrLoop ) ; } if ( UnrollCount ) AddMaskStep = AddMaskStep * UnrollCount ; UpdateDiffCoords ( TensorId , Count , AddMaskStep , <STR_LIT> , CurrLoop , PHI ) ; if ( ( <NUM_LIT> << Count ) < index ) { auto Remaining = fetchIndexFromOperand ( index - ( <NUM_LIT> << Count ) ) ; UpdateDiffCoords ( TensorId , Remaining , AddMaskStep , <STR_LIT> , CurrLoop , PHI ) ; } prepareLoopIvCoordMap ( TensorId , nullptr , Count ) ; RootInst = Intrins ; Nested_Ins = true ; break ; } } else { IncorrectIndexSpace = true ; return ; } if ( dyn_cast < llvm :: ConstantInt > (


<s> BasicBlockInfo & BBI = BBInfo [ MBB -> getNumber ( ) ] ; BBI . Size = <NUM_LIT> ; BBI . Unalign = <NUM_LIT> ; BBI . PostAlign = <NUM_LIT> ; for ( MachineInstr & I : * MBB ) { BBI . Size += TII -> getInstSizeInBytes ( I ) ; if ( I . isInlineAsm ( ) ) BBI . Unalign = isThumb ? <NUM_LIT> : <NUM_LIT> ; else if ( isThumb && mayOptimizeThumb2Instruction ( & I ) ) BBI . Unalign = <NUM_LIT> ; } if ( ! MBB -> empty ( ) && MBB -> back ( ) . getOpcode ( ) ==


<s> size_type getEdgeIndex ( const Edge & E ) const { return std :: distance ( edges_begin ( )


<s> case <STR_LIT> : { LoadSDNode * Ld = cast < LoadSDNode > ( N ) ; if ( Ld -> getValueType ( <NUM_LIT> ) != <STR_LIT> || Ld -> getMemoryVT ( ) != <STR_LIT> ) return ; SDLoc dl ( N ) ; SDValue LoadRes = DAG . getExtLoad ( Ld -> getExtensionType ( ) , dl , <STR_LIT> , Ld -> getChain ( ) , Ld -> getBasePtr ( ) , Ld -> getPointerInfo ( ) , <STR_LIT> , Ld -> getAlignment ( ) , Ld -> getMemOperand ( ) -> getFlags ( ) , Ld -> getAAInfo ( ) ) ; SDValue Res = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , LoadRes ) ; Results . push_back (


<s> if ( searchSymbolAlias ( Operands , <STR_LIT> ) ) return MatchOperand_Success ; return MatchOperand_NoMatch ; } if ( Parser . getTok ( ) . isNot ( AsmToken :: Dollar ) ) return MatchOperand_NoMatch ; Parser . Lex


<s> unsigned Opcode = Node -> getOpcode ( ) ; DebugLoc DL = Node -> getDebugLoc ( ) ; EVT NodeTy = Node -> getValueType ( <NUM_LIT> ) ; unsigned MultOpc ; switch ( Opcode ) { default : break ; case <STR_LIT> : case <STR_LIT> : { SDValue InFlag = Node -> getOperand ( <NUM_LIT> ) , CmpLHS ; unsigned Opc = InFlag . getOpcode ( ) ; ( void ) Opc ; assert ( ( ( Opc == <STR_LIT> || Opc == <STR_LIT> ) || ( Opc == <STR_LIT> || Opc == <STR_LIT> ) ) && <STR_LIT> ) ; unsigned MOp ; if ( Opcode == <STR_LIT> ) { CmpLHS = InFlag . getValue ( <NUM_LIT> ) ; MOp = <STR_LIT> ; } else { CmpLHS = InFlag . getOperand ( <NUM_LIT> ) ; MOp = <STR_LIT> ; } SDValue Ops [ ] = { CmpLHS , InFlag . getOperand ( <NUM_LIT> ) } ; SDValue LHS = Node -> getOperand ( <NUM_LIT> ) ; SDValue RHS = Node -> getOperand ( <NUM_LIT> ) ; EVT VT = LHS . getValueType ( ) ; unsigned Sltu_op = <STR_LIT> ; SDNode * Carry = CurDAG -> getMachineNode ( Sltu_op , DL , VT , Ops , <NUM_LIT> ) ; unsigned Addu_op = <STR_LIT> ; SDNode * AddCarry = CurDAG -> getMachineNode ( Addu_op , DL , VT , SDValue ( Carry , <NUM_LIT> ) , RHS ) ; SDNode * Result = CurDAG -> SelectNodeTo ( Node , MOp , VT , <STR_LIT> , LHS , SDValue ( AddCarry , <NUM_LIT> ) ) ; return std :: make_pair ( true , Result ) ; } case


<s> unsigned getT2SOImmOpValue ( const MCInst & MI , unsigned Op , SmallVectorImpl < MCFixup > & Fixups ) const { unsigned SoImm = MI . getOperand ( Op ) . getImm ( ) ; unsigned Encoded = <STR_LIT> (


<s> for ( const MachineInstr & MI : MBB . terminators ( ) ) for ( const MachineOperand & MO : MI . operands ( ) ) if ( MO . isMBB ( ) && MO . getMBB ( ) == Tgt ) return true ; return


<s> int check_use_sfunc_addr ( rtx insn , rtx reg ) { while ( ( insn = NEXT_INSN ( insn ) ) ) { if ( GET_CODE ( insn ) == CODE_LABEL || GET_CODE ( insn ) == JUMP_INSN ) break ; if ( ! INSN_P ( insn ) ) continue ; if ( GET_CODE ( PATTERN ( insn ) ) == SEQUENCE ) insn = XVECEXP ( PATTERN ( insn ) , <NUM_LIT> , <NUM_LIT> ) ; if ( GET_CODE ( PATTERN ( insn ) ) != PARALLEL

|| get_attr_type ( insn ) != TYPE_SFUNC ) continue ;


<s> return ( uint8x16_t ) __builtin_neon_vclzv16qi ( ( int8x16_t


<s> return make_range ( cbegin ( ) , cend ( )


) : default_external_stack_protect_fail ( ) ;


<s> void <ISA_LIT>InstrInfo :: copyPhysReg ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , DebugLoc DL , unsigned DestReg , unsigned SrcReg , bool KillSrc ) const { unsigned Opc ; if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opc = <STR_LIT> ; else llvm_unreachable ( <STR_LIT> ) ; BuildMI ( MBB , I , DL , get ( Opc ) , DestReg ) . addReg (

SrcReg , getKillRegState ( KillSrc ) ) ;


<s> break ; case SUBREG : if ( ! REG_P ( SUBREG_REG ( op ) ) ) return <NUM_LIT> ; case REG : if ( ! base ) base = op ; else if ( ! index ) index = op ; else return <NUM_LIT> ; break ; case CONST : case CONST_INT : case SYMBOL_REF : case LABEL_REF : if ( disp ) return <NUM_LIT> ; disp = op ; break ; default : return <NUM_LIT> ; } } } else if ( GET_CODE ( addr ) == MULT ) { index = XEXP ( addr , <NUM_LIT> ) ; scale_rtx = XEXP ( addr , <NUM_LIT> ) ; } else if ( GET_CODE ( addr ) == ASHIFT ) { index = XEXP ( addr , <NUM_LIT> ) ; tmp = XEXP ( addr , <NUM_LIT> ) ; if ( ! CONST_INT_P ( tmp ) ) return <NUM_LIT> ; scale = INTVAL ( tmp ) ; if ( ( unsigned HOST_WIDE_INT ) scale > <NUM_LIT> ) return <NUM_LIT> ; scale = <NUM_LIT> << scale ; retval = - <NUM_LIT> ; } else disp = addr ; if ( index ) { if ( REG_P ( index ) ) ; else if ( GET_CODE ( index ) == SUBREG && REG_P ( SUBREG_REG ( index ) ) ) ; else return <NUM_LIT> ; } if ( scale_rtx ) { if ( ! CONST_INT_P ( scale_rtx ) ) return <NUM_LIT> ; scale = INTVAL ( scale_rtx ) ; } base_reg = base && GET_CODE ( base ) == SUBREG ? SUBREG_REG ( base ) : base ; index_reg = index && GET_CODE ( index ) == SUBREG ? SUBREG_REG ( index ) : index ; if ( disp == const0_rtx && ( base || index ) ) disp = NULL_RTX ; if ( base_reg && index_reg && scale == <NUM_LIT> && ( index_reg == arg_pointer_rtx || index_reg == frame_pointer_rtx || ( REG_P ( index_reg ) && REGNO ( index_reg ) == STACK_POINTER_REGNUM ) ) ) { std :: swap ( base , index ) ; std :: swap ( base_reg , index_reg ) ; } if ( ! disp && base_reg && ( base_reg == hard_frame_pointer_rtx || base_reg == frame_pointer_rtx || base_reg == arg_pointer_rtx || ( REG_P ( base_reg ) && ( REGNO ( base_reg ) == HARD_FRAME_POINTER_REGNUM || REGNO ( base_reg ) == R13_REG ) ) ) ) disp = const0_rtx ; if ( TARGET_K6 && cfun && optimize_function_for_speed_p ( cfun ) && base_reg && ! index_reg && ! disp && REG_P ( base_reg ) && REGNO ( base_reg ) == SI_REG ) disp = const0_rtx ; if ( ! base && index && scale == <NUM_LIT> ) base = index , base_reg = index_reg , scale = <NUM_LIT> ; if ( ! base && ! disp && index && scale != <NUM_LIT> ) disp = const0_rtx ; out -> base = base ; out -> index = index ; out -> disp


<s> for ( const auto & Pair : Stack ) if ( Pair . first == MBB


<s> auto BlockIter = MBB . begin ( ) ; while ( BlockIter != MBB . end ( ) ) { auto & MI = * BlockIter ++ ; if ( isCVTAToLocalCombinationCandidate ( MI ) ) { CombineCVTAToLocal ( MI


<s> unsigned NF = Node -> getNumOperands ( ) - <NUM_LIT> ; if ( IsMasked ) -- NF ; MVT VT = Node -> getOperand ( <NUM_LIT> ) -> getSimpleValueType ( <NUM_LIT> ) ; unsigned Log2SEW = Log2_32 ( VT . getScalarSizeInBits ( ) ) ; <STR_LIT> LMUL = <ISA_LIT>TargetLowering :: getLMUL ( VT ) ; SmallVector < SDValue , <NUM_LIT> > Regs ( Node -> op_begin ( ) + <NUM_LIT> , Node -> op_begin ( ) + <NUM_LIT> + NF ) ; SDValue StoreVal = createTuple ( * CurDAG , Regs , NF , LMUL ) ; SmallVector < SDValue , <NUM_LIT> > Operands ; Operands . push_back ( StoreVal ) ; unsigned CurOp = <NUM_LIT> + NF ; MVT IndexVT ; addVectorLoadStoreOperands ( Node , Log2SEW , DL , CurOp , IsMasked , true , Operands , & IndexVT ) ; assert ( VT . getVectorElementCount ( ) == IndexVT . getVectorElementCount ( ) && <STR_LIT> ) ; <STR_LIT> IndexLMUL = <ISA_LIT>TargetLowering :: getLMUL ( IndexVT ) ; unsigned IndexLog2EEW = Log2_32 ( IndexVT . getScalarSizeInBits ( ) ) ; const <STR_LIT> * P = <STR_LIT> ( NF , IsMasked , IsOrdered , IndexLog2EEW , static_cast < unsigned > ( LMUL ) , static_cast < unsigned > ( IndexLMUL ) ) ; MachineSDNode * Store = CurDAG -> getMachineNode ( P -> Pseudo , DL , Node -> getValueType ( <NUM_LIT> ) , Operands ) ; if ( auto * MemOp = dyn_cast < MemSDNode > ( Node ) ) CurDAG -> setNodeMemRefs ( Store , { MemOp -> getMemOperand ( ) } ) ; ReplaceNode ( Node , Store


<s> void addACC64DSPAsmRegOperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: CreateReg ( getACC64DSPReg ( )


<s> assert ( ( RelTy == ELF :: R_MICROBLAZE_32_PCREL || RelTy == ELF :: R_MICROBLAZE_64_PCREL ) && <STR_LIT> ) ; return SymOffset - ( RelOffset +


<s> return frv_function_arg_1 ( cum , mode , type


<s> static bool spu_addr_space_legitimate_address_p ( machine_mode mode , rtx x , bool reg_ok_strict , addr_space_t as ) { if ( as == ADDR_SPACE_EA ) return ( REG_P ( x ) && ( GET_MODE ( x ) == EAmode ) ) ; else if ( as != ADDR_SPACE_GENERIC )


<s> bool <ISA_LIT>AsmPrinter :: doFinalization ( Module &


<s> SDLoc DL ( Op ) ; SDValue FrameAddr = DAG . getCopyFromReg ( DAG . getEntryNode ( ) , DL , ABI . IsN64 ( ) ? <STR_LIT> : <STR_LIT> , VT ) ; return


<s> LLVMContext & Context = M -> getContext ( ) ; bool LE = Subtarget . isLittle ( ) ; std :: string Name = F . getName ( ) ; std :: string SectionName = <STR_LIT> + Name ; std :: string StubName = <STR_LIT> + Name ; Function * FStub = M -> getFunction ( StubName ) ; if ( FStub && ! FStub -> isDeclaration ( ) ) return ; FStub = Function :: Create ( F . getFunctionType ( ) , Function :: InternalLinkage , StubName , M ) ; FStub -> addFnAttr ( <STR_LIT> ) ; FStub -> addFnAttr ( llvm :: Attribute :: Naked ) ; FStub -> addFnAttr ( llvm :: Attribute :: NoInline ) ; FStub -> addFnAttr ( llvm :: Attribute :: NoUnwind ) ; FStub -> addFnAttr ( <STR_LIT> ) ; FStub -> setSection ( SectionName ) ; BasicBlock * BB = BasicBlock :: Create ( Context , <STR_LIT> , FStub ) ; InlineAsmHelper IAH ( Context , BB ) ; IAH . Out ( <STR_LIT> ) ; FPReturnVariant RV = whichFPReturnVariant ( FStub -> getReturnType ( ) ) ; FPParamVariant PV = whichFPParamVariantNeeded ( F ) ; swapFPIntParams ( PV , M , IAH , LE , true ) ; if ( RV != NoFPRet ) { IAH . Out ( <STR_LIT> ) ; IAH . Out ( <STR_LIT> + Name )


<s> const Function & F = MF . getFunction ( ) ; if ( ! OutlineFromLinkOnceODRs && F . hasLinkOnceODRLinkage ( ) ) return false ; if ( F . hasSection ( ) ) return false ; return true


<s> const MachineDominanceFrontier & getDF ( ) const { return


<s> default : llvm_unreachable ( <STR_LIT> ) ; case FK_Data_1 : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case FK_Data_2 : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case FK_Data_4 : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> MCSubtargetInfo * X = new MCSubtargetInfo ( ) ; Init<ISA_LIT>MCSubtargetInfo ( X , TT , CPU , FS ) ; return X


<s> argument_list = TREE_CHAIN ( argument_list ) ; gcc_assert ( parameter ) ; if ( TREE_CODE ( parameter ) == ERROR_MARK ) return true ; type = TREE_TYPE ( parameter ) ; gcc_assert ( type ) ; mode = TYPE_MODE ( type ) ; gcc_assert ( mode ) ; if ( pass_by_reference ( & cum , mode , type , true ) ) { mode = Pmode ; type = build_pointer_type ( type ) ; } parm_rtx = s390_function_arg ( & cum , mode , type ,


<s> printDisp ( MI , opNum + <STR_LIT> , O ) ; O << ',' ; printOperand ( MI , opNum + <STR_LIT> , O ) ; O << ')'


<s> if ( M . getNamedGlobal ( <STR_LIT> ) ) report_fatal_error ( <STR_LIT> ) ; Type * Params [ ] = { IRB . getInt32Ty ( ) } ; FunctionType * FTy = FunctionType :: get ( IRB .


<s> bool IsLargeCodeModel = MF . getTarget ( ) . getCodeModel ( ) == CodeModel :: Large ; const <ISA_LIT>RegisterInfo * RegInfo = static_cast < const <ISA_LIT>RegisterInfo * > ( MF . getSubtarget ( ) . getRegisterInfo ( ) ) ; unsigned CallOp ; if ( Is64Bit ) CallOp = IsLargeCodeModel ? <STR_LIT> : <STR_LIT> ; else CallOp = <STR_LIT> ; const char * Symbol ; if ( Is64Bit ) { if ( STI . isTargetCygMing ( ) ) { Symbol = <STR_LIT> ; } else { Symbol = <STR_LIT> ; } } else if ( STI . isTargetCygMing ( ) ) Symbol = <STR_LIT> ; else Symbol = <STR_LIT> ; MachineInstrBuilder CI ; if ( Is64Bit && MF . getTarget ( ) . getCodeModel ( ) == CodeModel :: Large ) { BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addExternalSymbol ( Symbol ) ; CI = BuildMI ( MBB , MBBI , DL , TII . get ( CallOp ) ) . addReg ( <STR_LIT> ) ; } else { CI = BuildMI ( MBB , MBBI , DL , TII . get ( CallOp ) ) . addExternalSymbol ( Symbol ) ; } unsigned AX = Is64Bit ? <STR_LIT> : <STR_LIT> ; unsigned SP = Is64Bit ? <STR_LIT> : <STR_LIT> ; CI . addReg ( AX , RegState :: Implicit ) . addReg ( SP , RegState :: Implicit ) . addReg ( AX , RegState :: Define | RegState :: Implicit ) . addReg ( SP , RegState :: Define | RegState :: Implicit ) . addReg ( <STR_LIT> , RegState :: Define | RegState :: Implicit ) ; if ( Is64Bit )


<s> switch ( Op . getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerShifts ( Op , DAG ) ; case <STR_LIT> : return LowerGlobalAddress ( Op , DAG ) ; case <STR_LIT> : return LowerExternalSymbol ( Op , DAG ) ; case <STR_LIT> : return LowerSETCC ( Op , DAG ) ; case <STR_LIT> : return LowerBR_CC ( Op , DAG ) ; case <STR_LIT> : return LowerSELECT_CC ( Op , DAG ) ; case <STR_LIT> : return LowerSIGN_EXTEND ( Op , DAG ) ; case <STR_LIT> : return LowerRETURNADDR ( Op , DAG ) ; case <STR_LIT> : return LowerFRAMEADDR ( Op


<s> break ; case PLUS : x0 = XEXP ( x , <NUM_LIT> ) ; x1 = XEXP ( x , <NUM_LIT> ) ; if ( GET_CODE ( x0 ) == SUBREG ) x0 = SUBREG_REG ( x0 ) ; if ( GET_CODE ( x0 ) != REG ) break ; regno0 = REGNO ( x0 ) ; if ( ! frv_regno_ok_for_base_p ( regno0 , strict_p ) ) break ; switch ( GET_CODE ( x1 ) ) { default : break ; case SUBREG : x1 = SUBREG_REG ( x1 ) ; if ( GET_CODE ( x1 ) != REG ) break ; case REG : if ( ! allow_double_reg_p && GET_MODE_SIZE ( mode ) > UNITS_PER_WORD ) ret = FALSE ; else ret = frv_regno_ok_for_base_p ( REGNO ( x1 ) , strict_p ) ; break ; case CONST_INT : if ( condexec_p ) ret = FALSE ; else { value = INTVAL ( x1 ) ; ret = IN_RANGE ( value ,


<s> PM . add ( create<ISA_LIT>ISelDag ( get<ISA_LIT>TargetMachine ( ) ) ) ; return


<s> virtual const InstrItineraryData * getInstrItineraryData


<s> return ( __m512 ) __builtin_ia32_broadcastss512 ( ( __v4sf ) __A , ( __v16sf ) _mm512_undefined_ps ( ) , ( __mmask16 )


<s> bool HasAnyUndefs ; if ( ! BVN || ! BVN -> isConstantSplat ( SplatBits , SplatUndef , SplatBitSize , HasAnyUndefs , ElementBits ) || SplatBitSize > ElementBits ) return false ; Cnt = SplatBits . getSExtValue ( ) ; return


<s> const MCOperand & ImmOp = Inst . getOperand ( <NUM_LIT> ) ; assert ( ImmOp . isImm ( ) && <STR_LIT> ) ; const MCOperand & SrcRegOp = Inst . getOperand ( <NUM_LIT> ) ; assert ( SrcRegOp . isReg ( ) && <STR_LIT> ) ; const MCOperand & DstRegOp = Inst . getOperand ( <NUM_LIT> ) ; assert ( DstRegOp . isReg ( ) && <STR_LIT> ) ; int ImmValue = ImmOp . getImm ( ) ; if ( - <NUM_LIT> <= ImmValue && ImmValue <= <NUM_LIT> ) { tmpInst . setOpcode ( <STR_LIT> ) ; tmpInst . addOperand ( MCOperand :: CreateReg ( DstRegOp . getReg ( ) ) ) ; tmpInst . addOperand ( MCOperand :: CreateReg ( SrcRegOp . getReg ( ) ) ) ; tmpInst . addOperand ( MCOperand :: CreateImm ( ImmValue ) ) ; Instructions . push_back ( tmpInst ) ; } else { tmpInst . setOpcode ( <STR_LIT> ) ; tmpInst . addOperand ( MCOperand :: CreateReg ( DstRegOp . getReg ( ) ) ) ; tmpInst . addOperand ( MCOperand :: CreateImm ( (

ImmValue & <NUM_LIT> ) >> <NUM_LIT> ) ) ;


<s> bool isReg ( ) const { return Kind ==


<s> const <ISA_LIT>Subtarget & getSubtarget ( ) const { return Subtarget


<s> bool AMDGPUInstrInfo :: canFoldMemoryOperand ( const MachineInstr * MI , const SmallVectorImpl < unsigned > & Ops ) const { return false


<s> __builtin_neon_vst3_lanev2si ( ( __builtin_neon_si * ) __a ,


<s> void <ISA_LIT>InstPrinter :: printLdStmModeOperand ( const MCInst * MI , unsigned OpNum , raw_ostream & O ) { <STR_LIT> Mode = <STR_LIT> ( MI -> getOperand ( OpNum ) . getImm ( ) ) ; O << <STR_LIT> (


<s> TargetName = std :: string ( CPU . empty ( ) ? <STR_LIT> : CPU ) ; ParseSubtargetFeatures ( TargetName , TargetName , FS ) ; if ( PTXVersion ==


<s> RHS = DAG . getConstant ( <NUM_LIT> , LHS . getValueType ( ) ) ; CC = <STR_LIT> ; } } if ( LHS . getValueType ( ) == <STR_LIT> ) { if ( Subtarget -> hasFP<ISA_LIT>v8 ( ) && ( TrueVal . getValueType ( ) == <STR_LIT> || TrueVal . getValueType ( ) == <STR_LIT> ) ) { <STR_LIT> CondCode = IntCCTo<ISA_LIT>CC ( CC ) ; if ( CondCode == <STR_LIT> || CondCode == <STR_LIT> || CondCode == <STR_LIT> || CondCode == <STR_LIT> ) { CC = getInverseCCForVSEL ( CC ) ; std :: swap ( TrueVal , FalseVal ) ; } } SDValue <ISA_LIT>cc ; SDValue CCR = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; SDValue Cmp = get<ISA_LIT>Cmp ( LHS , RHS , CC , <ISA_LIT>cc , DAG , dl ) ; return getCMOV ( dl , VT , FalseVal , TrueVal , <ISA_LIT>cc , CCR , Cmp , DAG ) ; } <STR_LIT> CondCode , CondCode2 ; FPCCTo<ISA_LIT>CC ( CC , CondCode , CondCode2 ) ; if ( Subtarget -> hasFP<ISA_LIT>v8 ( ) && ( TrueVal . getValueType ( ) == <STR_LIT> || TrueVal . getValueType ( ) == <STR_LIT> ) ) { if ( getTargetMachine ( ) . Options . UnsafeFPMath ) { if ( LHS == TrueVal && RHS == FalseVal ) { if ( CC == <STR_LIT> || CC == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , dl , VT , TrueVal , FalseVal ) ; if ( CC == <STR_LIT> || CC == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , dl , VT , TrueVal , FalseVal ) ; } else if ( LHS == FalseVal && RHS == TrueVal ) { if ( CC == <STR_LIT> || CC == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , dl , VT , TrueVal , FalseVal ) ; if ( CC == <STR_LIT> || CC == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , dl , VT , TrueVal , FalseVal ) ; } } bool swpCmpOps = false ; bool swpVselOps = false ; checkVSELConstraints ( CC , CondCode , swpCmpOps , swpVselOps ) ; if ( CondCode == <STR_LIT> || CondCode == <STR_LIT> || CondCode == <STR_LIT> || CondCode == <STR_LIT> ) { if ( swpCmpOps ) std :: swap ( LHS , RHS ) ; if ( swpVselOps ) std :: swap ( TrueVal , FalseVal ) ; } } SDValue <ISA_LIT>cc = DAG . getConstant ( CondCode , <STR_LIT> ) ; SDValue Cmp = getVFPCmp ( LHS , RHS , DAG , dl ) ; SDValue CCR = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; SDValue Result = getCMOV ( dl , VT , FalseVal , TrueVal , <ISA_LIT>cc , CCR , Cmp


<s> static SDValue getOutFlag ( SDValue & Op ) { SDValue Flag = Op . getValue ( Op . getNode ( ) -> getNumValues ( ) - <NUM_LIT> ) ; assert ( Flag . getValueType ( ) == <STR_LIT> && <STR_LIT> ) ; return


<s> static ScheduleDAGInstrs * createGCNMaxOccupancyMachineScheduler ( MachineSchedContext * C ) { ScheduleDAGMILive * DAG = new ScheduleDAGMILive ( C , llvm :: make_unique < GCNMaxOccupancySchedStrategy > ( C ) ) ; DAG -> addMutation ( createLoadClusterDAGMutation ( DAG -> TII


<s> return ( ! getDesc ( ) . isPseudo ( ) && ! isPrefix ( ) && getType ( ) !=


<s> new_addr = scratch ; } break ; case REG : case SUBREG : if ( ! base_reg_operand ( addr , GET_MODE ( addr ) ) ) { emit_insn ( gen_rtx_SET ( scratch , addr ) ) ; new_addr = scratch ; } break ; case PLUS : op0 = XEXP ( addr , <NUM_LIT> ) ; op1 = XEXP ( addr , <NUM_LIT> ) ; if ( ! base_reg_operand ( op0 , Pmode ) ) rs6000_secondary_reload_fail ( __LINE__ , reg , mem , scratch , store_p ) ; else if ( int_reg_operand ( op1 , Pmode ) ) { if ( ( addr_mask & RELOAD_REG_INDEXED ) == <NUM_LIT> ) { emit_insn ( gen_rtx_SET ( scratch , addr ) ) ; new_addr = scratch ; } } else if ( mode_supports_vsx_dform_quad ( mode ) && CONST_INT_P ( op1 ) ) { if ( ( ( addr_mask & RELOAD_REG_QUAD_OFFSET ) == <NUM_LIT> ) || ! quad_address_p ( addr , mode , false ) ) { emit_insn ( gen_rtx_SET ( scratch , addr ) ) ; new_addr = scratch ; } } else if ( rs6000_legitimate_offset_address_p ( mode , addr , false , true ) ) { if ( ( addr_mask & RELOAD_REG_OFFSET ) == <NUM_LIT> ) { emit_insn ( gen_rtx_SET ( scratch , addr ) ) ; new_addr = scratch ; } } else rs6000_secondary_reload_fail ( __LINE__ , reg , mem , scratch , store_p ) ; break ; case LO_SUM : op0 = XEXP ( addr , <NUM_LIT> ) ; op1 = XEXP ( addr , <NUM_LIT> ) ; if ( ! base_reg_operand ( op0 , Pmode ) ) rs6000_secondary_reload_fail ( __LINE__ , reg , mem , scratch , store_p ) ; else if ( int_reg_operand ( op1 , Pmode ) ) { if ( ( addr_mask & RELOAD_REG_INDEXED ) == <NUM_LIT> ) { emit_insn ( gen_rtx_SET ( scratch , addr ) ) ; new_addr = scratch ; } } else if ( mode_supports_vsx_dform_quad ( mode ) ) { emit_insn ( gen_rtx_SET ( scratch , addr ) ) ; new_addr = scratch ; } else if ( legitimate_lo_sum_address_p ( mode , addr , false ) ) { if ( ( addr_mask & RELOAD_REG_OFFSET ) == <NUM_LIT> ) { emit_insn ( gen_rtx_SET ( scratch , addr ) ) ; new_addr = scratch ; } } else rs6000_secondary_reload_fail ( __LINE__ , reg , mem , scratch , store_p ) ; break ; case SYMBOL_REF : case CONST : case


<s> assert ( MI . getOperand ( OperandNo ) . getImm ( ) == <NUM_LIT> && <STR_LIT> ) ; assert ( MI . hasOneMemOperand ( ) && <STR_LIT> ) ; assert ( ( * MI . memoperands_begin ( ) ) -> getSize ( ) == ( UINT64_C ( <NUM_LIT> ) << <STR_LIT> ( MI . getOpcode ( ) ) ) && <STR_LIT> ) ; assert ( MI . getDesc ( ) . OpInfo [ OperandNo ] . OperandType == <STR_LIT> && <STR_LIT> ) ; uint64_t P2Align = Log2_64 ( ( * MI . memoperands_begin ( ) ) ->


<s> static void microblaze_elf_asm_destructor ( rtx symbol , int priority ) { microblaze_elf_asm_cdtor ( symbol ,


<s> case <STR_LIT> : if ( IsFunction ) return <STR_LIT> ; return <STR_LIT> ; case <STR_LIT> : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : if ( isGlobalType ( Target ) ) return <STR_LIT> ; if ( isFunctionType ( Target ) ) return <STR_LIT> ; if ( IsFunction ) return <STR_LIT> ; if ( isEventType ( Target ) ) return <STR_LIT> ; return <STR_LIT> ; case FK_Data_4 : if ( IsFunction


<s> PM . add ( create<ISA_LIT>CodeEmitterPass ( * this , MCE ) ) ; if ( DumpAsm ) PM . add ( create<ISA_LIT>CodePrinterPass ( errs ( ) , * this , Fast ) ) ; return


<s> const uint16_t * <ISA_LIT>RegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF )


<s> static SDValue LowerReverse_VECTOR_SHUFFLEv16i8_v8i16 ( SDValue Op , SelectionDAG & DAG ) { SDLoc DL ( Op ) ; SDValue OpLHS = Op . getOperand ( <NUM_LIT> ) ; EVT VT = OpLHS . getValueType


getParent ( ) -> getFnAttribute ( <STR_LIT> ) ;


<s> auto Op = make_unique < <ISA_LIT>Operand > ( Register ) ; Op -> Reg . RegNum = RegNo ; Op -> StartLoc = S ; Op -> EndLoc


<s> DataSecEntries [ std :: string ( SecName ) ] = std :: make_unique < BTFKindDataSec > ( Asm , std :: string ( SecName ) ) ; } } SmallVector < DIGlobalVariableExpression * , <NUM_LIT> > GVs ; Global . getDebugInfo ( GVs ) ; if ( GVs . size ( ) == <NUM_LIT> ) continue ; uint32_t GVTypeId = <NUM_LIT> ; for ( auto * GVE : GVs ) { if ( SecName . startswith ( <STR_LIT> ) ) visitMapDefType ( GVE -> getVariable ( ) -> getType ( ) , GVTypeId ) ; else visitTypeEntry ( GVE -> getVariable ( ) -> getType ( ) , GVTypeId , false , false ) ; break ; } auto Linkage = Global . getLinkage ( ) ; if ( Linkage != GlobalValue :: InternalLinkage && Linkage != GlobalValue :: ExternalLinkage && Linkage != GlobalValue :: WeakAnyLinkage && Linkage != GlobalValue :: ExternalWeakLinkage ) continue ; uint32_t GVarInfo ; if ( Linkage == GlobalValue :: InternalLinkage ) { GVarInfo = <STR_LIT> ; } else if ( Global . hasInitializer ( ) ) { GVarInfo = <STR_LIT> ; } else { GVarInfo = <STR_LIT> ; } auto VarEntry = std :: make_unique < BTFKindVar > ( Global . getName ( )


<s> bool requiresVirtualBaseRegisters ( const MachineFunction & MF )


<s> initLiveRegs ( LiveRegs , TRI , FuncInfo , MF , MBB , MBBI , true ) ; MCPhysReg TmpVGPR = findScratchNonCalleeSaveRegister ( MRI , LiveRegs , <STR_LIT> ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) , TmpVGPR ) . addReg ( TRI . getSubReg ( RetAddrReg , <STR_LIT> ) ) ; int DwordOff = <NUM_LIT> ; buildPrologSpill ( ST , TRI , * FuncInfo , LiveRegs , MF , MBB , MBBI , TmpVGPR , FI , DwordOff ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) , TmpVGPR ) . addReg ( TRI . getSubReg ( RetAddrReg , <STR_LIT> ) ) ; DwordOff = <NUM_LIT> ; buildPrologSpill ( ST , TRI , * FuncInfo , LiveRegs , MF , MBB , MBBI , TmpVGPR , FI , DwordOff ) ; buildCFI ( MBB , MBBI , DL , MCCFIInstruction :: createOffset ( nullptr , MCRI -> getDwarfRegNum ( <STR_LIT> , false ) , MFI . getObjectOffset ( FI ) * ST . getWavefrontSize ( ) ) ) ; } if ( EXECSaveIndex && spilledToMemory ( MF , * EXECSaveIndex ) ) { const int FI = * EXECSaveIndex ; assert ( ! MFI . isDeadObjectIndex ( FI ) ) ; initLiveRegs ( LiveRegs , TRI , FuncInfo , MF , MBB , MBBI , true ) ; MCPhysReg TmpVGPR = findScratchNonCalleeSaveRegister ( MRI , LiveRegs , <STR_LIT> ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) , TmpVGPR ) . addReg ( TRI . getSubReg ( <STR_LIT> , <STR_LIT> ) ) ; int DwordOff = <NUM_LIT> ; buildPrologSpill ( ST , TRI , * FuncInfo , LiveRegs , MF , MBB , MBBI , TmpVGPR , FI , DwordOff ) ; if ( ! ST . isWave32 ( ) ) { BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) , TmpVGPR ) . addReg ( TRI . getSubReg ( <STR_LIT> , <STR_LIT> ) ) ; DwordOff = <NUM_LIT> ; buildPrologSpill ( ST , TRI , * FuncInfo , LiveRegs , MF , MBB , MBBI , TmpVGPR , FI , DwordOff ) ; } buildCFI ( MBB , MBBI , DL , MCCFIInstruction :: createOffset ( nullptr , MCRI -> getDwarfRegNum ( <STR_LIT> , false ) , MFI . getObjectOffset ( FI ) * ST . getWavefrontSize ( ) ) ) ; } } if ( ! emitSpillsToMem ) { if ( RASaveIndex && ! spilledToMemory ( MF , * RASaveIndex ) ) { MCRegister RetAddrReg = TRI . getReturnAddressReg ( MF ) ; if ( ! MBB . isLiveIn ( RetAddrReg ) ) MBB . addLiveIn (


<s> res . as_short [ <NUM_LIT> ] = m1 . as_short [ <NUM_LIT> ] ; res . as_short [ <NUM_LIT> ] = m2 . as_short [ <NUM_LIT> ] ; return ( __m64 ) res .


<s> SDValue <ISA_LIT>TargetLowering :: LowerBlockAddress ( SDValue Op , SelectionDAG & DAG ) const { EVT PtrVT = Op . getValueType ( ) ; const BlockAddress * BA = cast < BlockAddressSDNode > ( Op ) -> getBlockAddress ( ) ; unsigned MOHiFlag , MOLoFlag ; bool isPIC = GetLabelAccessInfo ( DAG . getTarget ( ) , MOHiFlag , MOLoFlag ) ; SDValue TgtBAHi = DAG . getTargetBlockAddress ( BA , PtrVT , <NUM_LIT> , MOHiFlag ) ; SDValue TgtBALo = DAG . getTargetBlockAddress ( BA , PtrVT , <NUM_LIT> , MOLoFlag ) ; return LowerLabelRef ( TgtBAHi , TgtBALo


<s> llvm_unreachable ( <STR_LIT> ) ; return


<s> void <ISA_LIT>LowerControlFlow :: emitElseBreak ( MachineInstr


<s> return DA -> isUniform ( T ) || T ->


<s> return new <ISA_LIT>PassConfig ( this , PM )


<s> if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableAtomicTidy ) addPass ( createCFGSimplificationPass ( <NUM_LIT> , true , true , false , true ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None ) { if ( EnableLoopDataPrefetch ) addPass ( createLoopDataPrefetchPass ( ) ) ; if ( EnableFalkorHWPFFix ) addPass ( createFalkorMarkStridedAccessesPass ( ) ) ; } TargetPassConfig :: addIRPasses ( ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt


<s> return StringSwitch < Optional < MCFixupKind >> ( Name ) . Case ( <STR_LIT> , ( MCFixupKind ) <STR_LIT> ) .

Case ( <STR_LIT> , FK_Data_4 ) . Default ( MCAsmBackend :: getFixupKind ( Name ) ) ;


<s> bool nds32_n10_last_load_to_ex_p ( rtx_insn * producer ,


<s> RegisterMCAsmParser < <ISA_LIT>AsmParser > X ( The<ISA_LIT>Target


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> :


<s> printOperand ( MI , Op , OS ) ; OS << ')' << markup


<s> for ( int i = <NUM_LIT> ; i >= <NUM_LIT> ; i -- ) O << utohexstr ( ( Value & ( <NUM_LIT> << ( i * <NUM_LIT> )


<s> bool always_inline = lookup_attribute ( <STR_LIT> , DECL_ATTRIBUTES ( callee ) ) ; if ( always_inline ) return true ; if ( caller_opts -> x_aarch64_cmodel_var != callee_opts -> x_aarch64_cmodel_var ) return false ; if ( caller_opts -> x_aarch64_tls_dialect != callee_opts -> x_aarch64_tls_dialect ) return false ; if ( ! aarch64_tribools_ok_for_inlining_p ( caller_opts -> x_aarch64_fix_a53_err835769 , callee_opts -> x_aarch64_fix_a53_err835769 , <NUM_LIT> , TARGET_FIX_ERR_A53_835769_DEFAULT ) ) return false ; if ( ! aarch64_tribools_ok_for_inlining_p ( caller_opts -> x_aarch64_fix_a53_err843419 , callee_opts -> x_aarch64_fix_a53_err843419 , <NUM_LIT> , TARGET_FIX_ERR_A53_843419 )


<s> return parseMSARegs ( Operands , ( int ) <STR_LIT>


<s> SDValue Base = Node -> getOperand ( <NUM_LIT> ) ; SDValue VIdx = Node -> getOperand ( <NUM_LIT> ) ; SDValue VMask = Node -> getOperand ( <NUM_LIT> ) ; ConstantSDNode * Scale = dyn_cast < ConstantSDNode > ( Node -> getOperand ( <NUM_LIT> ) ) ; if ( ! Scale ) return nullptr ; SDVTList VTs = CurDAG -> getVTList ( VSrc . getValueType ( ) , VSrc . getValueType ( ) , <STR_LIT> ) ; SDLoc DL ( Node ) ; SDValue Disp = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; SDValue Segment = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; const SDValue Ops [ ] = { VSrc , Base , getI8Imm ( Scale -> getSExtValue ( ) , DL ) , VIdx , Disp , Segment , VMask , Chain } ; SDNode * ResNode = CurDAG -> getMachineNode ( Opc , DL , VTs , Ops ) ; ReplaceUses ( SDValue ( Node , <NUM_LIT> ) , SDValue ( ResNode , <NUM_LIT> ) ) ; ReplaceUses ( SDValue ( Node , <NUM_LIT> ) , SDValue ( ResNode , <NUM_LIT> ) ) ; return ResNode


<s> static MCDisassembler * create<ISA_LIT>Disassembler ( const Target & T , const MCSubtargetInfo & STI ) { return new <ISA_LIT>Disassembler ( STI , T


<s> unsigned OpNum = <NUM_LIT> ; unsigned Opc = MI . getOpcode ( ) ; if ( Opc != <STR_LIT> ) { OpNum = ( Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; } MI . getOperand ( OpNum ) . setMBB ( & NewDestBB


<s> static rtx riscv_pass_fpr_single ( enum machine_mode type_mode , unsigned regno , enum machine_mode value_mode ) { rtx x = gen_rtx_REG ( value_mode , regno


<s> bool <ISA_LIT>AsmParser :: parseOperand ( OperandVector & Operands , StringRef Name ) { if ( isParsingIntelSyntax ( ) ) return parseIntelOperand ( Operands , Name ) ; return parseATTOperand (


<s> static bool isVINSERTIndex ( SDNode * N , unsigned vecWidth ) { assert ( ( vecWidth == <NUM_LIT> || vecWidth == <NUM_LIT> ) && <STR_LIT> ) ; if ( ! isa < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) .


<s> static void iq2000_emit_frame_related_store ( rtx mem , rtx reg , HOST_WIDE_INT offset ) { rtx dwarf_address = plus_constant ( stack_pointer_rtx , offset ) ; rtx dwarf_mem = gen_rtx_MEM ( GET_MODE ( reg


<s> if ( I . getPointerAddressSpace ( ) == AMDGPUA<ISA_LIT> . CONSTANT_ADDRESS && canWidenScalarExtLoad ( I ) ) { IRBuilder < > Builder ( & I ) ; Builder . SetCurrentDebugLocation ( I . getDebugLoc ( ) ) ; Type * I32Ty = Builder . getInt32Ty ( ) ; Type * PT = PointerType :: get ( I32Ty , I . getPointerAddressSpace ( ) ) ; Value * BitCast = Builder . CreateBitCast ( I . getPointerOperand ( ) , PT ) ; Value * WidenLoad = Builder . CreateLoad ( BitCast ) ; int TySize = Mod -> getDataLayout ( ) . getTypeSizeInBits ( I . getType ( ) ) ; Type * IntNTy = Builder . getIntNTy ( TySize ) ; Value * ValTrunc = Builder . CreateTrunc ( WidenLoad , IntNTy ) ; Value * ValOrig = Builder . CreateBitCast ( ValTrunc , I . getType ( ) ) ; I . replaceAllUsesWith ( ValOrig ) ; I . eraseFromParent ( ) ; return true ; } return false


<s> bool GPRSrc = <STR_LIT> . contains ( SrcReg ) ; if ( GPRDest && GPRSrc ) { AddDefaultCC ( AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ) ) ; return ; } bool SPRDest = <STR_LIT> . contains ( DestReg ) ; bool SPRSrc = <STR_LIT> . contains ( SrcReg ) ; unsigned Opc = <NUM_LIT> ; if ( SPRDest && SPRSrc ) Opc = <STR_LIT> ; else if ( GPRDest && SPRSrc ) Opc = <STR_LIT> ; else if ( SPRDest && GPRSrc ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opc = <STR_LIT> ; if ( Opc ) { MachineInstrBuilder MIB = BuildMI ( MBB , I , DL , get ( Opc ) , DestReg ) ; MIB . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; if ( Opc == <STR_LIT> ) MIB . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; AddDefaultPred ( MIB ) ; return ; } if ( <STR_LIT> . contains ( DestReg , SrcReg ) || <STR_LIT> . contains ( DestReg , SrcReg ) ) { const TargetRegisterInfo * TRI = & getRegisterInfo ( ) ; assert ( <STR_LIT> + <NUM_LIT> == <STR_LIT> && <STR_LIT> ) ; unsigned EndSubReg = <STR_LIT> . contains ( DestReg , SrcReg ) ? <STR_LIT> : <STR_LIT> ; for ( unsigned i = <STR_LIT> , e = EndSubReg + <NUM_LIT> ; i != e


<s> assert ( N -> getNumOperands ( ) == <NUM_LIT> && <STR_LIT> ) ; unsigned SignBits [ <NUM_LIT> ] = { <NUM_LIT> , <NUM_LIT> } ; bool IsPositive [ <NUM_LIT> ] = { false , false } ; for ( unsigned i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) { SDValue Opd = N -> getOperand ( i ) ; if ( Opd . getOpcode ( ) == <STR_LIT> ) { if ( Opd . getOperand ( <NUM_LIT> ) . getValueType ( ) . getVectorElementType ( ) == <STR_LIT> ) SignBits [ i ] = <NUM_LIT> ; else if ( Opd . getOperand ( <NUM_LIT> ) . getValueType ( ) . getVectorElementType ( ) == <STR_LIT> ) SignBits [ i ] = <NUM_LIT> ; else return false ; IsPositive [ i ] = true ; } else { SignBits [ i ] = DAG . ComputeNumSignBits ( Opd ) ; if ( DAG . SignBitIsZero ( Opd ) ) IsPositive [ i ] = true ; } } bool AllPositive = IsPositive [ <NUM_LIT> ] && IsPositive [ <NUM_LIT> ] ; unsigned MinSignBits = std :: min ( SignBits [ <NUM_LIT> ] , SignBits [ <NUM_LIT> ] ) ; if ( MinSignBits >= <NUM_LIT> ) Mode = MULS8 ; else if ( AllPositive && MinSignBits >= <NUM_LIT> ) Mode = MULU8 ; else if ( MinSignBits >= <NUM_LIT> ) Mode = MULS16 ; else if ( AllPositive && MinSignBits >= <NUM_LIT> ) Mode = MULU16 ; else return


<s> MachineOperand Src ( AccMO ) ; MI . removeOperand ( <NUM_LIT> ) ; MI . removeOperand ( <NUM_LIT> ) ; MI . removeOperand ( <NUM_LIT> ) ; MI . setDesc ( TII -> get ( Opcode ) ) ; MachineInstrBuilder ( * MI . getParent ( ) -> getParent ( ) , & MI ) . add ( Src ) . add ( Lhs


<s> ndregs -- ; } } if ( total_consec != <NUM_LIT> ) { rtx pat = gen_rtx_PARALLEL ( VOIDmode , rtvec_alloc ( total_consec + <NUM_LIT> ) ) ; XVECEXP ( pat , <NUM_LIT> , <NUM_LIT> ) = gen_rtx_SET ( spreg , gen_rtx_PLUS ( Pmode , spreg , GEN_INT ( total_consec * <NUM_LIT> ) ) ) ; if ( npregs_consec > <NUM_LIT> ) regno = REG_P5 + <NUM_LIT> ; else regno = REG_R7 + <NUM_LIT> ; for ( i = <NUM_LIT> ; i < total_consec ; i ++ ) { rtx addr = ( i > <NUM_LIT> ? gen_rtx_PLUS ( Pmode , spreg , GEN_INT ( i * <NUM_LIT> ) ) : spreg ) ; rtx memref = gen_rtx_MEM ( word_mode , addr ) ; regno -- ; XVECEXP ( pat , <NUM_LIT> , i + <NUM_LIT> ) = gen_rtx_SET ( gen_rtx_REG ( word_mode , regno ) , memref ) ; if ( npregs_consec > <NUM_LIT> ) { if ( -- npregs_consec == <NUM_LIT> ) regno = REG_R7 + <NUM_LIT> ; } } insn = emit_insn ( pat ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; } if ( saveall || is_inthandler ) { for ( regno = REG_LB1 ; regno >= REG_LT0 ; regno -- ) if ( ! crtl -> is_leaf || cfun -> machine -> has_hardware_loops || cfun -> machine -> has_loopreg_clobber || ( ENABLE_WA_05000257 && ( regno == REG_LC0 || regno == REG_LC1 ) ) ) emit_move_insn ( gen_rtx_REG ( SImode , regno ) , postinc ) ; emit_move_insn ( gen_rtx_REG ( SImode , REG_ASTAT ) ,


<s> return create<ISA_LIT>ELFObjectWriter ( OSABI , Is64Bit


<s> break ; default : Opcode = <STR_LIT> ; break ; } LLT s128 = LLT :: scalar ( <NUM_LIT> ) ; auto CASDst = MRI . createGenericVirtualRegister ( s128 ) ; auto CASDesired = MRI . createGenericVirtualRegister ( s128 ) ; auto CASNew = MRI . createGenericVirtualRegister ( s128 ) ; MIRBuilder . buildInstr ( TargetOpcode :: REG_SEQUENCE , { CASDesired } , { } ) . addUse ( DesiredI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addImm ( <STR_LIT> ) . addUse ( DesiredI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addImm ( <STR_LIT> ) ; MIRBuilder . buildInstr ( TargetOpcode :: REG_SEQUENCE , { CASNew } , { } ) . addUse ( NewI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addImm ( <STR_LIT> ) . addUse ( NewI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addImm ( <STR_LIT> ) ; CAS = MIRBuilder . buildInstr ( Opcode , { CASDst } , { CASDesired , CASNew , Addr } ) ; MIRBuilder . buildExtract ( { DstLo } , { CASDst } , <NUM_LIT> ) ; MIRBuilder . buildExtract ( { DstHi } , { CASDst } , <NUM_LIT> ) ; } else { auto Scratch = MRI . createVirtualRegister ( & <STR_LIT> ) ; CAS = MIRBuilder . buildInstr ( <STR_LIT> , { DstLo , DstHi , Scratch } , { Addr , DesiredI -> getOperand ( <NUM_LIT> ) , DesiredI -> getOperand ( <NUM_LIT> ) , NewI -> getOperand ( <NUM_LIT> ) , NewI -> getOperand ( <NUM_LIT> ) } ) ; } CAS . cloneMemRefs ( MI ) ; constrainSelectedInstRegOperands ( * CAS , * ST -> getInstrInfo ( ) , * MRI . getTargetRegisterInfo ( ) , * ST -> getRegBankInfo ( ) ) ; MIRBuilder . buildMerge ( MI . getOperand ( <NUM_LIT>


<s> uint64_t StackSize = MFI -> getStackSize ( ) ; if ( ! StackSize ) return ; if ( isInt < <NUM_LIT> > ( StackSize ) ) BuildMI ( MBB , MBBI ,

dl , TII . get ( <STR_LIT> ) ) . addImm ( StackSize ) ;


<s> return __builtin_arm_crypto_aesimc (


<s> return SelectionDAGISel :: runOnMachineFunction ( MF )


<s> unsigned long total = IN_NAMED_SECTION_P ( cfun -> decl ) ? <NUM_LIT> : total_code_bytes ; if ( INSN_ADDRESSES_SET_P ( ) ) { distance = ( total + insn_current_reference_address ( insn ) ) ; if ( distance < total ) distance = - <NUM_LIT> ; } if ( TARGET_64BIT ) return <NUM_LIT> ; if ( TARGET_FAST_INDIRECT_CALLS || ( ! TARGET_PORTABLE_RUNTIME && ( ( TARGET_PA_20 && ! TARGET_SOM && distance < <NUM_LIT> ) || distance < <NUM_LIT> ) ) ) return <NUM_LIT> ; if ( flag_pic )


<s> NodeAddr < BlockNode * > FuncNode :: getEntryBlock ( const DataFlowGraph & G ) { MachineBasicBlock * EntryB = & getCode ( ) -> front ( ) ; return findBlock ( EntryB ,


<s> const Triple & TT = TM . getTargetTriple ( ) ; StringRef CPU = <STR_LIT> ( TT , TM . getTargetCPU ( ) ) ; StringRef FS = TM . getTargetFeatureString ( ) ; const <ISA_LIT>TargetMachine & MTM = static_cast < const <ISA_LIT>TargetMachine & > ( TM ) ; const <ISA_LIT>Subtarget STI ( TT , CPU , FS , MTM . isLittleEndian ( ) , MTM ) ; bool IsABICalls = STI . isABICalls ( ) ; const <ISA_LIT>ABIInfo & ABI = MTM . getABI ( ) ; if ( IsABICalls ) { TS . emitDirectiveAbiCalls ( ) ; Reloc :: Model RM = TM . getRelocationModel ( ) ; if ( RM == Reloc :: Static && ! ABI . IsN64 ( ) ) TS . emitDirectiveOptionPic0 ( ) ; } std :: string SectionName = std :: string ( <STR_LIT> ) + getCurrentABIString ( ) ; OutStreamer -> SwitchSection ( OutContext . getELFSection ( SectionName , ELF :: SHT_PROGBITS , <NUM_LIT> ) ) ; STI . isNaN2008 ( ) ? TS . emitDirectiveNaN2008 ( ) : TS . emitDirectiveNaNLegacy ( ) ; if ( ABI . IsEABI ( ) ) { if ( STI . isGP32bit ( ) ) OutStreamer -> SwitchSection ( OutContext . getELFSection ( <STR_LIT> , ELF :: SHT_PROGBITS , <NUM_LIT> ) ) ; else OutStreamer -> SwitchSection ( OutContext . getELFSection ( <STR_LIT>


<s> static SDValue performSTORECombine ( SDNode * N , TargetLowering :: DAGCombinerInfo & DCI , SelectionDAG & DAG , const <ISA_LIT>Subtarget * Subtarget ) { if ( SDValue Split = splitStores ( N , DCI , DAG , Subtarget ) ) return Split ; if ( Subtarget -> supportsAddressTopByteIgnored ( ) && performTBISimplification ( N -> getOperand ( <NUM_LIT>

) , DCI , DAG ) ) return SDValue ( N , <NUM_LIT> ) ;


<s> for ( auto * F : Functions ) { DominatorTree * DT = & getAnalysis < DominatorTreeWrapperPass > ( * F ) . getDomTree ( ) ; BasicBlock * Root = DT -> getRoot ( ) ; ReversePostOrderTraversal < BasicBlock * > RPOT ( Root ) ; for ( auto * BB : RPOT ) for ( Instruction & I : make_early_inc_range ( * BB ) ) Changed |= optimizeIntrinsic ( & I ) ; } return Changed


<s> if ( MI -> getNumMemOperands ( ) == <NUM_LIT> ) return <ISA_LIT>MemOpInfo ( SyncScope :: System , AtomicOrdering :: SequentiallyConsistent ) ; return <ISA_LIT>MemOpInfo :: constructFromMIWithMMO ( MI )


<s> return new <ISA_LIT>FastPreTileConfig (


<s> Subtarget = & MF . getSubtarget < <ISA_LIT>Z80Subtarget > ( ) ; return SelectionDAGISel :: runOnMachineFunction (


<s> if ( auto * E = dyn_cast < <ISA_LIT>MCExpr > ( X ) ) return getRegNo ( ) == E -> getRegNo ( ) ; return false


<s> void set_color ( auto_vec < unsigned > & color_counts ) { color = brackets . last ( ) . get_color ( color_counts , brackets . length


<s> static void core2i7_first_cycle_multipass_issue ( void * _data , signed char * ready_try , int n_ready , rtx_insn * insn , const void * _prev_data ) { ix86_first_cycle_multipass_data_t data = ( ix86_first_cycle_multipass_data_t ) _data ; const_ix86_first_cycle_multipass_data_t prev_data = ( const_ix86_first_cycle_multipass_data_t ) _prev_data ; int insn_size = ix86_min_insn_size ( insn ) ; data -> ifetch_block_len = prev_data -> ifetch_block_len + insn_size ; data -> ifetch_block_n_insns = prev_data -> ifetch_block_n_insns + <NUM_LIT> ; gcc_assert ( data -> ifetch_block_len <= core2i7_ifetch_block_size && data -> ifetch_block_n_insns <= core2i7_ifetch_block_max_insns ) ; if ( ! data -> ready_try_change ) { data -> ready_try_change = sbitmap_alloc ( n_ready


<s> SDValue DstPtr = Op . getOperand ( <NUM_LIT> ) ; SDValue SrcPtr = Op . getOperand ( <NUM_LIT> ) ; const Value * DstSV = cast < SrcValueSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getValue ( ) ; const Value * SrcSV = cast < SrcValueSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getValue ( ) ; SDLoc DL ( Op )


<s> void \ sdata2_section ( ) \ { \ if ( in_section != in_sdata2 ) \ { \ in_section = in_sdata2 ; \ fprintf ( asm_out_file , <STR_LIT>


<s> const <ISA_LIT>TargetLowering * getTargetLowering ( )


<s> return STI . getTargetTriple ( ) . startswith (


<s> unsigned <ISA_LIT>TargetLowering :: numBitsUnsigned ( SDValue Op , SelectionDAG & DAG ) { EVT VT = Op . getValueType ( ) ; KnownBits Known = DAG . computeKnownBits (


<s> MachineBasicBlock * Pred = * MBB -> pred_begin ( ) ; transferSuccessor ( Pred , MBB , newBB ) ; } newBB -> addSuccessor ( MBB , BranchProbability :: getOne ( ) ) ; MF -> insert ( MachineFunction :: iterator ( MBB ) , newBB ) ; return newBB


<s> } if ( ! isResourceAvailable ( SU ) ) { ResourcesModel -> clearResources ( ) ; Packet . clear ( ) ; TotalPackets ++ ; startNewCycle = true ; } switch ( SU -> getInstr ( ) -> getOpcode ( ) ) { default : ResourcesModel -> reserveResources ( SU -> getInstr ( ) ) ; break ; case TargetOpcode :: EXTRACT_SUBREG : case TargetOpcode :: INSERT_SUBREG : case TargetOpcode :: SUBREG_TO_REG : case TargetOpcode :: REG_SEQUENCE : case TargetOpcode :: IMPLICIT_DEF : case TargetOpcode :: KILL : case TargetOpcode :: PROLOG_LABEL : case TargetOpcode :: EH_LABEL : case TargetOpcode :: COPY : case TargetOpcode :: INLINEASM : break ; } Packet . push_back ( SU ) ; DEBUG ( dbgs ( ) << <STR_LIT> << TotalPackets << <STR_LIT>


<s> void <ISA_LIT>BitcodeWriter :: writeDIGlobalVariable ( const DIGlobalVariable * N , SmallVectorImpl < uint64_t > & Record , unsigned Abbrev ) { Record . push_back ( N -> isDistinct ( ) ) ; Record . push_back ( VE . getMetadataOrNullID ( N -> getScope ( ) ) ) ; Record . push_back ( VE . getMetadataOrNullID ( N -> getRawName ( ) ) ) ; Record . push_back ( VE . getMetadataOrNullID ( N -> getRawLinkageName ( ) ) ) ; Record . push_back ( VE . getMetadataOrNullID ( N -> getFile ( ) ) ) ; Record . push_back ( N -> getLine ( ) ) ; Record . push_back ( VE . getMetadataOrNullID ( N ->


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { MachineFunctionPass :: getAnalysisUsage (


<s> __builtin_loongarch_iocsrwr_h ( ( unsigned short ) _1 ,


<s> regno -- ) if ( ( ( regno != MMIX_FRAME_POINTER_REGNUM || ! frame_pointer_needed ) && df_regs_ever_live_p ( regno ) && ! call_used_or_fixed_reg_p ( regno ) ) || IS_MMIX_EH_RETURN_DATA_REG ( regno ) ) stack_space_to_deallocate += <NUM_LIT> ; if ( MMIX_CFUN_HAS_LANDING_PAD ) stack_space_to_deallocate += <NUM_LIT> ; else if ( MMIX_CFUN_NEEDS_SAVED_EH_RETURN_ADDRESS ) stack_space_to_deallocate += <NUM_LIT> ; if ( frame_pointer_needed ) stack_space_to_deallocate += <NUM_LIT> ; if ( ( stack_space_to_deallocate % <NUM_LIT> ) != <NUM_LIT> ) internal_error ( <STR_LIT> , stack_space_to_deallocate ) ; for ( regno = MMIX_FIRST_GLOBAL_REGNUM ; regno <= <NUM_LIT> ; regno ++ ) if ( ( ( regno != MMIX_FRAME_POINTER_REGNUM || ! frame_pointer_needed ) && df_regs_ever_live_p ( regno ) && ! call_used_or_fixed_reg_p ( regno ) ) || IS_MMIX_EH_RETURN_DATA_REG ( regno ) ) { if ( offset > <NUM_LIT> ) { mmix_emit_sp_add ( offset ) ; stack_space_to_deallocate -= offset ; offset = <NUM_LIT> ; } emit_move_insn ( gen_rtx_REG ( DImode , regno ) , gen_rtx_MEM ( DImode , plus_constant ( Pmode , stack_pointer_rtx , offset ) ) ) ; offset += <NUM_LIT> ; } offset += ( locals_size + <NUM_LIT> ) & ~ <NUM_LIT> ; if ( MMIX_CFUN_HAS_LANDING_PAD ) offset += <NUM_LIT> ; else if ( MMIX_CFUN_NEEDS_SAVED_EH_RETURN_ADDRESS ) offset += <NUM_LIT> ; if ( frame_pointer_needed ) { if ( offset > <NUM_LIT> ) { mmix_emit_sp_add ( offset ) ; stack_space_to_deallocate -= offset ; offset =


<s> void appendCandidate ( MachineInstr * MI ) { Candidates . push_back


<s> unsigned BitSize = getFixupKindInfo ( Kind ) . TargetSize ; unsigned Size = ( BitSize + <NUM_LIT> ) / <NUM_LIT> ; assert ( Offset + Size <= DataSize && <STR_LIT> ) ; Value = extractBitsForFixup ( Kind , Value ) ; if ( BitSize < <NUM_LIT> ) Value &= ( ( uint64_t ) <NUM_LIT> << BitSize ) - <NUM_LIT> ; unsigned ShiftValue = ( Size


<s> MachineBasicBlock :: iterator I = MBB . end ( ) , UnCondBrIter = I ; while ( I != MBB . begin ( ) ) { -- I ; if ( I -> isDebugValue ( ) ) { continue ; } if ( ! isUnpredicatedTerminator ( * I ) ) { break ; } if ( ! I -> isBranch ( ) ) { return true ; } if ( ! I -> getOperand ( <NUM_LIT> ) . isMBB ( ) ) { return true ; } if ( I -> getNumOperands ( ) == <NUM_LIT> ) { UnCondBrIter = I ; if ( ! AllowModify ) { TBB = I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; continue ; } while ( std :: next ( I ) != MBB . end ( ) ) { std :: next ( I ) -> eraseFromParent ( ) ; } Cond . clear ( ) ; FBB = nullptr ; if ( MBB . isLayoutSuccessor ( I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ) ) { TBB = nullptr ; I -> eraseFromParent ( ) ; I = MBB . end ( ) ; UnCondBrIter = I ; continue ; } TBB = I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; continue ; } assert ( I -> getNumExplicitOperands ( ) == <NUM_LIT> && <STR_LIT> ) ; <STR_LIT> BranchCode = <STR_LIT> ( I -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; if ( Cond . empty ( ) ) { MachineBasicBlock * TargetBB = I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; if ( AllowModify && UnCondBrIter != MBB . end ( ) && MBB . isLayoutSuccessor ( TargetBB ) ) { BranchCode = GetOppositeBranchCondition ( BranchCode ) ; MachineBasicBlock :: iterator OldInst = I ; BuildMI ( MBB , UnCondBrIter , MBB . findDebugLoc ( I ) , get ( <STR_LIT> ) ) . addMBB

( UnCondBrIter -> getOperand ( <NUM_LIT> ) . getMBB ( ) ) . addImm ( BranchCode ) ;


<s> <ISA_LIT>Operand * Op = new <ISA_LIT>Operand ( KindImm , StartLoc , EndLoc ) ; Op -> Imm = Expr ; return Op


<s> switch ( VT . getSimpleVT ( ) . SimpleTy ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; } unsigned Opc = Opcodes [ OpcodeIndex ] ; SmallVector < SDValue , <NUM_LIT> > Ops ; unsigned AddrOpIdx = isUpdating ? <NUM_LIT> : <NUM_LIT> ; Ops . push_back ( N -> getOperand ( AddrOpIdx ) ) ; if ( isUpdating ) { SDValue Inc = N -> getOperand ( AddrOpIdx + <NUM_LIT> ) ; if ( ! isa < ConstantSDNode > ( Inc . getNode ( ) ) ) Opc = getVLDSTRegisterUpdateOpcode ( Opc ) ; Ops . push_back ( Inc ) ; } Ops . push_back ( N -> getOperand ( <NUM_LIT> ) ) ; std :: vector < EVT > ResTys ; bool is64BitVector = VT . is64BitVector ( ) ; if ( NumVecs == <NUM_LIT> ) ResTys . push_back ( VT ) ; else if ( NumVecs == <NUM_LIT> ) ResTys . push_back ( <STR_LIT> ) ; else { EVT ResTy = EVT :: getVectorVT ( * CurDAG -> getContext ( ) , <STR_LIT> , is64BitVector ? NumVecs : NumVecs * <NUM_LIT> ) ; ResTys . push_back ( ResTy ) ; } if ( isUpdating ) ResTys . push_back ( <STR_LIT> ) ; ResTys . push_back ( <STR_LIT>


<s> CCInfo . AllocateStack ( ABI . GetCalleeAllocdArgSizeInBytes ( Info . CallConv ) , Align ( <NUM_LIT> ) ) ; const char * Call = Info . Callee . isSymbol ( ) ? Info . Callee . getSymbolName ( ) : nullptr ; CCInfo . AnalyzeCallOperands ( Outs , TLI . CCAssignFnForCall ( ) , FuncOrigArgs , Call ) ; setLocInfo ( ArgLocs , Outs ) ; OutgoingValueHandler RetHandler ( MIRBuilder , MF . getRegInfo ( ) , MIB ) ; if ( ! RetHandler . handle ( ArgLocs , ArgInfos ) ) { return false ; } unsigned NextStackOffset = CCInfo . getNextStackOffset ( ) ; const TargetFrameLowering * TFL = MF . getSubtarget ( ) . getFrameLowering ( ) ; unsigned StackAlignment = TFL -> getStackAlignment ( ) ; NextStackOffset = alignTo ( NextStackOffset , StackAlignment ) ; CallSeqStart . addImm ( NextStackOffset ) . addImm ( <NUM_LIT> ) ; if ( IsCalleeGlobalPIC ) { MIRBuilder . buildCopy ( Register ( <STR_LIT> ) , MF . getInfo < <ISA_LIT>FunctionInfo > ( ) -> getGlobalBaseRegForGlobalISel ( MF ) ) ; MIB . addDef ( <STR_LIT> , RegState :: Implicit ) ; } MIRBuilder . insertInstr ( MIB ) ; if ( MIB -> getOpcode ( ) == <STR_LIT> ) { const <ISA_LIT>Subtarget & STI = static_cast < const <ISA_LIT>Subtarget & > ( MIRBuilder . getMF ( ) . getSubtarget ( ) ) ; MIB . constrainAllUses ( MIRBuilder . getTII ( ) , * STI . getRegisterInfo ( ) , * STI . getRegBankInfo ( ) ) ; } if ( ! Info . OrigRet . Ty -> isVoidTy ( ) ) { ArgInfos . clear ( ) ; SmallVector < unsigned , <NUM_LIT> > OrigRetIndices ; splitToValueTypes ( DL , Info . OrigRet , <NUM_LIT> , ArgInfos , OrigRetIndices ) ; SmallVector < <STR_LIT> , <NUM_LIT> > Ins ; subTargetRegTypeForCallingConv ( F , ArgInfos , OrigRetIndices , Ins ) ; SmallVector < CCValAssign , <NUM_LIT> > ArgLocs ; <ISA_LIT>CCState CCInfo ( F . getCallingConv ( ) , F . isVarArg ( ) , MF , ArgLocs , F . getContext ( ) ) ; CCInfo . AnalyzeCallResult ( Ins , TLI . CCAssignFnForReturn ( )


<s> MachineBasicBlock * MBB = MI -> getParent ( ) ; MachineInstr * Last = & MBB -> back ( ) ; SmallPtrSet < MachineInstr * , <NUM_LIT> > Ignore ; if ( Last -> getOpcode ( ) == <STR_LIT> ) Ignore . insert ( Last ) ; bool SetFlags = RDA -> isSafeToDefRegAt ( MI , <STR_LIT> , Ignore ) ; MachineInstrBuilder MIB = BuildMI ( * MBB , MI , MI -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) ; MIB . addDef ( <STR_LIT> ) ; MIB . add ( MI -> getOperand ( <NUM_LIT> ) ) ; MIB . add ( MI -> getOperand ( <NUM_LIT> ) ) ; MIB . addImm ( <STR_LIT> ) ; MIB . addReg ( <NUM_LIT> ) ; if ( SetFlags )


<s> unsigned <ISA_LIT>RegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { const TargetFrameLowering * TFI = MF . getSubtarget ( ) . getFrameLowering ( ) ; if ( TFI -> hasFP ( MF ) ) { return <STR_LIT>


<s> AsmToken <STR_LIT> ( ) { const AsmToken & lexedToken = lexDefinite ( ) ; switch ( lexedToken . getKind ( ) ) { default : return lexedToken ; case AsmToken :: Error : SetError ( Lexer -> getErrLoc ( ) , Lexer -> getErr ( ) ) ; return lexedToken ; case AsmToken :: Identifier : { std :: string upperCase = lexedToken . getString ( ) . str ( ) ; std :: string lowerCase = LowercaseString ( upperCase ) ; StringRef lowerRef ( lowerCase ) ; unsigned regID = MatchRegisterName ( lowerRef ) ; if ( regID ) return AsmToken ( AsmToken :: Register , lexedToken . getString ( ) ,


<s> if ( isNegative ) { return - Contents . ImmVal ; } return Contents .


<s> if ( C . CallConstructionID == MachineOutlinerTailCall ) { Opc = isThumb ? Subtarget . isTargetMachO ( ) ? <STR_LIT> : <STR_LIT> : <STR_LIT> ; MIB = BuildMI ( MF , DebugLoc ( ) , get ( Opc ) ) . addGlobalAddress ( M . getNamedValue ( MF . getName ( ) ) ) ; if ( isThumb ) MIB . add ( predOps ( <STR_LIT> ) ) ; It = MBB . insert ( It , MIB ) ; return It ; } Opc = isThumb ? <STR_LIT> : <STR_LIT> ; MachineInstrBuilder CallMIB = BuildMI ( MF , DebugLoc ( ) , get ( Opc ) ) ; if ( isThumb ) CallMIB . add ( predOps ( <STR_LIT> ) ) ; CallMIB . addGlobalAddress ( M . getNamedValue ( MF . getName ( ) ) ) ; if ( C . CallConstructionID == MachineOutlinerNoLRSave || C . CallConstructionID == MachineOutlinerThunk ) { It = MBB . insert ( It , CallMIB ) ; return It ; } const <ISA_LIT>FunctionInfo & AFI = * C . getMF ( ) ->


<s> enum rtx_code code = GET_CODE ( op ) ; if ( code == SUBREG && ( GET_MODE_SIZE ( GET_MODE ( op ) ) < GET_MODE_SIZE ( GET_MODE ( XEXP ( op , <NUM_LIT> ) ) ) ) ) { unsigned int index = SUBREG_BYTE ( op ) ; if ( index < <NUM_LIT> ) index += <NUM_LIT> ; else index -= <NUM_LIT> ; SUBREG_BYTE ( op ) = index ; } const char * fmt = GET_RTX_FORMAT ( code ) ; int i ,


<s> } } for ( const MachineOperand & MO : MI . operands ( ) ) { if ( ! MO . isReg ( ) || ! MO . isDef ( ) ) continue ; RegisterRef RD ( MO ) ; assert ( RD . Sub == <NUM_LIT> && <STR_LIT> ) ; if ( ! Register :: isVirtualRegister ( RD . Reg ) ) continue ; bool Changed = false ; if ( ! Eval || ResMap . count ( RD . Reg ) == <NUM_LIT> ) { uint16_t DefBW = ME . getRegBitWidth ( RD ) ; RegisterCell RefC = RegisterCell :: self ( RD . Reg , DefBW ) ; if ( RefC != ME . getCell ( RD , Map ) ) { ME . putCell ( RD , RefC , Map ) ; Changed = true ; } } else { RegisterCell DefC = ME . getCell ( RD


<s> const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; if ( TLO . ShrinkDemandedConstant ( Op1 , DemandedMask ) || TLI . SimplifyDemandedBits ( Op1 , DemandedMask , KnownZero , KnownOne , TLO )

) DCI . CommitTargetLoweringOpt ( TLO ) ;


<s> Loop * CurrLoop = LI -> getLoopFor ( Phi -> getParent ( ) ) ; Optional < Loop :: LoopBounds > LB = CurrLoop -> getBounds ( * SE ) ; PHINode * LoopPHI = CurrLoop -> getInductionVariable ( * SE ) ; if ( LB && ( LoopPHI != nullptr ) ) { Value & Initial = LB -> getInitialIVValue ( ) ; Value & Final = LB -> getFinalIVValue ( ) ; if ( dyn_cast < llvm :: ExtractElementInst > ( & Initial ) ) { updateCoordFactor ( TensorId , index , INVALID_SCEV ,


<s> if ( Addr . getOpcode ( ) == <STR_LIT> ) { Base = Addr . getOperand ( <NUM_LIT> ) ; Offset = Addr . getOperand ( <NUM_LIT> ) ; return


<s> auto MIB = BuildMI ( BB , I , I . getDebugLoc ( ) , TII . get ( <STR_LIT> ) ) . addDef ( I . getOperand ( <NUM_LIT> ) . getReg ( ) ) . addUse ( I . getOperand ( <NUM_LIT> ) . getReg ( ) ) . addUse ( I . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; if ( I . getNumMemOperands ( ) ) addMemoryOperands ( * I . memoperands_begin ( ) , MIB ) ; bool Result = MIB . constrainAllUses ( TII , TRI


<s> MachineInstrBuilder MIB = BuildMI ( MBB , I , MBB . findDebugLoc ( I ) , get ( Opcode ) , DstReg ) ; if ( Src1Reg ) { MIB . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; } MIB . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( Src0Reg ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( - <NUM_LIT> ) ; if ( Src1Reg ) { MIB . addReg ( Src1Reg ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> )


<s> void relaxInstruction ( const MCInst & Inst , const MCSubtargetInfo & STI , MCInst & Res ) const override { llvm_unreachable ( <STR_LIT>


<s> const char * avr_out_reload_inpsi ( rtx * op


<s> Kern [ <STR_LIT> ] = Kern . getDocument ( ) -> getNode ( <STR_LIT> ) ; auto LanguageVersion = Kern . getDocument ( ) -> getArrayNode ( ) ; LanguageVersion . push_back ( Kern . getDocument ( ) -> getNode ( mdconst :: extract < ConstantInt > ( Op0 -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ) ) ; LanguageVersion . push_back ( Kern . getDocument ( ) -> getNode ( mdconst :: extract < ConstantInt > ( Op0 -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ) ) ; Kern [ <STR_LIT> ] =


<s> if ( ! fp_consts_inited ) init_fp_table ( ) ; gcc_assert ( real_equal ( r ,


<s> return __builtin_aarch64_lfrintnudfdi_us (


<s> static std :: string getArgsLabel ( const std :: string & Func ) { std :: string Func1 = addPrefix ( Func ) ; std :: string tag = getTagName


<s> if ( GET_CODE ( operands [ <NUM_LIT> ] ) == REG && GET_CODE ( operands [ <NUM_LIT> ] ) == REG && REGNO ( operands [ <NUM_LIT> ] ) == REGNO ( operands [ <NUM_LIT> ] ) + <NUM_LIT> ) swap = true ; if ( GET_CODE ( operands [ <NUM_LIT> ] ) == REG && GET_CODE ( operands [ <NUM_LIT> ] ) == MEM ) { rtx op = XEXP ( operands [ <NUM_LIT> ] , <NUM_LIT> ) ; if ( GET_CODE ( op ) == SUBREG ) op = SUBREG_REG ( op ) ; if ( GET_CODE ( op ) == REG && REGNO ( op ) == REGNO ( operands [ <NUM_LIT> ] ) ) swap = true ; if ( GET_CODE ( op ) == PLUS ) { rtx x = XEXP ( op , <NUM_LIT> ) ; rtx y = XEXP ( op , <NUM_LIT> ) ; if ( GET_CODE ( x ) == REG && REGNO ( x ) == REGNO ( operands [ <NUM_LIT> ] ) ) swap = true ; if ( GET_CODE ( y ) == REG && REGNO ( y ) == REGNO ( operands [ <NUM_LIT> ] ) ) swap = true ; } } if ( swap ) { operands [ <NUM_LIT> ] = operand_subword ( operands [ <NUM_LIT> ] , <NUM_LIT> , <NUM_LIT> ,


<s> } if ( const <ISA_LIT>MCExpr * SymbolRefExpr = dyn_cast < <ISA_LIT>MCExpr > ( Imm . Value ) ) return SymbolRefExpr -> getKind ( ) == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_ABS_LO ; if ( const MCBinaryExpr * BinaryExpr = dyn_cast < MCBinaryExpr > ( Imm . Value ) ) if ( const <ISA_LIT>MCExpr * SymbolRefExpr = dyn_cast < <ISA_LIT>MCExpr > ( BinaryExpr -> getLHS ( ) ) ) return SymbolRefExpr -> getKind ( ) == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_ABS_LO ; return false


) : default_hidden_stack_protect_fail ( ) ;


<s> int fromfloat = ( c1 == LOAD_FPU_REGS || c1 == NO_LOAD_FPU_REGS || c1 == FPU_REGS ) ; int tofloat = ( c2 == LOAD_FPU_REGS || c2 == NO_LOAD_FPU_REGS || c2 == FPU_REGS ) ; return ( fromfloat


<s> } for ( ; RegMaskStartIdx < MI . getNumOperands ( ) ; ++ RegMaskStartIdx ) OriginalCall -> addOperand ( MI . getOperand ( RegMaskStartIdx ) ) ; auto * Marker = BuildMI ( MBB , MBBI , MI . getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addReg ( <STR_LIT> , RegState :: Define ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . getInstr ( ) ; if ( MI . shouldUpdateCallSiteInfo ( ) ) MBB . getParent ( ) -> moveCallSiteInfo ( & MI


<s> break ; default : return false ; } materializeLoadStoreOperands ( Addr ) ; unsigned ValueReg = getRegForValue ( Store -> getValueOperand ( ) ) ; if ( VTIsi1 ) ValueReg = maskI1Value ( ValueReg , Store -> getValueOperand ( ) ) ; unsigned ResultReg = createResultReg ( RC ) ; auto MIB = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , ResultReg ) ; addLoadStoreOperands ( Addr , MIB , createMachineMemOperandFor ( Store ) ) ; MIB . addReg ( ValueReg ) ; return


<s> const <ISA_LIT>InstrInfo & TII = * STI . getInstrInfo ( ) ; if ( ! FrameSize && ! MF . getFrameInfo ( ) . hasVarSizedObjects ( ) ) { restoreStatusRegister ( MF , MBB ) ; return ; } while ( MBBI != MBB . begin ( ) ) { MachineBasicBlock :: iterator PI = std :: prev ( MBBI ) ; int Opc = PI -> getOpcode ( ) ; if ( Opc != <STR_LIT> && Opc != <STR_LIT> && ! PI -> isTerminator ( ) ) { break ; } -- MBBI ; } if ( FrameSize ) { unsigned Opcode ; if ( isUInt < <NUM_LIT> > ( FrameSize ) ) { Opcode = <STR_LIT>


<s> llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : setFeatureBits ( <STR_LIT> , <STR_LIT> ) ; getTargetStreamer ( ) . emitDirectiveSetDsp ( ) ; break ; case <STR_LIT> : getTargetStreamer ( ) . emitDirectiveSetMicro<ISA_LIT> ( ) ; break ; case <STR_LIT> : getTargetStreamer ( ) . emitDirectiveSet<ISA_LIT>16 ( ) ; break ; case <STR_LIT> : selectArch ( <STR_LIT> ) ; getTargetStreamer ( ) . emitDirectiveSet<ISA_LIT>1 ( ) ; break ; case <STR_LIT> : selectArch ( <STR_LIT> ) ; getTargetStreamer ( ) . emitDirectiveSet<ISA_LIT>2 ( ) ; break ; case <STR_LIT> : selectArch ( <STR_LIT> ) ; getTargetStreamer ( ) . emitDirectiveSet<ISA_LIT>3 ( ) ; break ; case <STR_LIT> : selectArch ( <STR_LIT> ) ; getTargetStreamer ( ) . emitDirectiveSet<ISA_LIT>4 ( ) ; break ; case <STR_LIT> : selectArch ( <STR_LIT> ) ; getTargetStreamer ( ) . emitDirectiveSet<ISA_LIT>5 ( ) ; break ; case <STR_LIT> : selectArch ( <STR_LIT> ) ; getTargetStreamer ( ) . emitDirectiveSet<ISA_LIT>32 ( ) ; break ; case <STR_LIT> : selectArch ( <STR_LIT> ) ; getTargetStreamer ( ) . emitDirectiveSet<ISA_LIT>32R2 ( ) ; break ; case <STR_LIT> : selectArch ( <STR_LIT> ) ; getTargetStreamer ( ) . emitDirectiveSet<ISA_LIT>32R6 ( ) ; break ; case <STR_LIT> : selectArch ( <STR_LIT> ) ; getTargetStreamer ( ) . emitDirectiveSet<ISA_LIT>64 ( ) ; break ; case


<s> break ; case MCK__35_24 : ExpectedVal = <NUM_LIT> ; break ; case MCK__35_3 : ExpectedVal = <NUM_LIT> ; break ; case MCK__35_32 : ExpectedVal = <NUM_LIT> ; break ; case MCK__35_4 : ExpectedVal = <NUM_LIT> ; break ; case MCK__35_48 : ExpectedVal = <NUM_LIT> ; break ; case MCK__35_6 : ExpectedVal = <NUM_LIT> ; break ; case MCK__35_64 : ExpectedVal = <NUM_LIT> ; break ; case MCK__35_8 : ExpectedVal = <NUM_LIT> ; break ; } if ( ! Op -> isImm ( ) ) return Match_InvalidOperand ; const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( Op -> getImm ( ) ) ; if ( ! CE ) return Match_InvalidOperand ; if ( CE -> getValue ( ) == ExpectedVal


<s> else if ( MemTy == <STR_LIT> ) Opcode = <STR_LIT> ; else if ( MemTy == <STR_LIT> ) Opcode = <STR_LIT> ; else llvm_unreachable ( <STR_LIT> ) ; SDValue Ops [ ] = { N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) } ; SDNode * CmpSwap = CurDAG -> getMachineNode ( Opcode , SDLoc ( N ) , CurDAG -> getVTList ( <STR_LIT> , <STR_LIT> , <STR_LIT> ) , Ops ) ; MachineMemOperand * MemOp = cast < MemSDNode > ( N )


<s> for ( unsigned i = <NUM_LIT> ; i < CSI . size ( ) ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; const uint16_t * SuperReg = TRI -> getSuperRegisters ( Reg ) ; assert ( SuperReg [ <NUM_LIT> ] && ! SuperReg [ <NUM_LIT> ] && <STR_LIT> ) ; bool CanUseDblStore = false ; const TargetRegisterClass * SuperRegClass = <NUM_LIT> ; if ( ContiguousRegs && ( i < CSI . size ( ) - <NUM_LIT> ) ) { const uint16_t * SuperRegNext = TRI -> getSuperRegisters ( CSI [ i + <NUM_LIT> ] . getReg ( ) ) ; assert ( SuperRegNext [ <NUM_LIT> ] && ! SuperRegNext [ <NUM_LIT> ] && <STR_LIT> ) ; SuperRegClass = TRI -> getMinimalPhysRegClass ( SuperReg [ <NUM_LIT> ] ) ; CanUseDblStore = ( SuperRegNext [ <NUM_LIT> ] == SuperReg [ <NUM_LIT> ] ) ; } if ( CanUseDblStore ) { TII . storeRegToStackSlot ( MBB , MI , SuperReg [ <NUM_LIT> ] , true , CSI [ i + <NUM_LIT> ] . getFrameIdx ( ) , SuperRegClass , TRI ) ; MBB . addLiveIn ( SuperReg [ <NUM_LIT> ] ) ; ++ i ; } else { ContiguousRegs = false ; const TargetRegisterClass * RC = TRI


<s> break ; case k_Token : Tok = o . Tok ; break ; case k_CCOut : case k_Register : Reg = o . Reg ; break ; case k_RegisterList : case k_DPRRegisterList : case k_SPRRegisterList : Registers = o . Registers ; break ; case k_VectorList : case k_VectorListAllLanes : case k_VectorListIndexed : VectorList = o . VectorList ; break ; case k_CoprocNum : case k_CoprocReg : Cop = o . Cop ; break ; case k_CoprocOption : CoprocOption = o . CoprocOption ; break ; case k_Immediate : Imm = o . Imm ; break ; case k_MemBarrierOpt : MBOpt = o . MBOpt ; break ; case k_InstSyncBarrierOpt : ISBOpt = o . ISBOpt ; case k_Memory : Memory = o . Memory ; break ; case k_PostIndexRegister : PostIdxReg = o . PostIdxReg ; break ; case k_MSRMask


<s> std :: vector < std :: string > mov_memsp_to ( Register b ) { return D ( <STR_LIT> , <STR_LIT> , R (


<s> MCContext & Ctx = getContext ( ) ; MCSymbol * Sym = Ctx . getOrCreateSymbol ( Twine ( <STR_LIT> ) ) ; Sym -> setVariableValue ( MCConstantExpr :: create ( ISA . Major , Ctx ) ) ; Sym = Ctx . getOrCreateSymbol ( Twine ( <STR_LIT> ) ) ; Sym -> setVariableValue ( MCConstantExpr :: create ( ISA . Minor , Ctx ) ) ; Sym = Ctx . getOrCreateSymbol ( Twine ( <STR_LIT> ) ) ; Sym -> setVariableValue ( MCConstantExpr :: create ( ISA . Stepping ,


<s> MDNode * V = N -> getOperand ( <NUM_LIT> ) ; VectorSz = readIntFromMetadata ( V ) ; } unsigned MaxScalarSz = Subtarget -> getFrameLowering ( ) -> getMaxScalarMemory ( ) ; if ( ScalarSz > MaxScalarSz ) { std :: ostringstream Msg ; Msg << <STR_LIT> << ScalarSz << <STR_LIT> << MaxScalarSz << <STR_LIT> ; if ( ! IgnoreMemOverflow ) { report_fatal_error ( Msg . str ( ) , false ) ; } else { errs ( ) << <STR_LIT> << Msg . str ( ) ; } } unsigned MaxVectorSz = Subtarget -> getFrameLowering ( ) -> getMaxVectorMemory


<s> while ( InsertionPt != MBB . begin ( ) ) { InsertionPt -- ; bool DefSCC , UseSCC ; instrDefsUsesSCC ( * InsertionPt , DefSCC , UseSCC ) ; if ( DefSCC ) return InsertionPt ; } llvm_unreachable (


<s> static rtx ix86_expand_int_compare ( enum rtx_code code , rtx op0 , rtx op1 ) { machine_mode cmpmode ; rtx tmp , flags ; cmpmode = SELECT_CC_MODE ( code , op0 , op1 ) ; flags = gen_rtx_REG ( cmpmode , FLAGS_REG ) ; tmp = gen_rtx_COMPARE ( cmpmode ,


<s> if ( HasVariant ) OS << '%' << getVariantKindName ( getKind ( ) ) << '(' ; Expr -> print ( OS , MAI ) ; if ( Kind == VK_<ISA_LIT>_CALL_PLT ) OS << <STR_LIT> ; if ( HasVariant ) OS <<


<s> return ( REG_P ( op0 ) && REG_P ( op1 ) && ( ( INT_REG_OK_FOR_BASE_P ( op0 , strict ) && INT_REG_OK_FOR_INDEX_P ( op1 , strict

) ) || ( INT_REG_OK_FOR_BASE_P ( op1 , strict ) && INT_REG_OK_FOR_INDEX_P ( op0 , strict ) ) ) ) ;


<s> SelectionDAG & DAG = DCI . DAG ; EVT VT = LN -> getMemoryVT ( ) ; unsigned Size = VT . getStoreSize ( ) ; unsigned Align = LN -> getAlignment ( ) ; if ( Align < Size && isTypeLegal ( VT ) ) { bool IsFast ; unsigned AS = LN -> getAddressSpace ( ) ; if ( ! allowsMisalignedMemoryAccesses ( VT , AS , Align , LN -> getMemOperand ( ) -> getFlags ( ) , & IsFast ) ) { SDValue Ops [ <NUM_LIT> ] ; if ( VT . isVector ( ) ) std :: tie ( Ops [ <NUM_LIT> ] , Ops [ <NUM_LIT> ] ) = scalarizeVectorLoad ( LN , DAG ) ; else std :: tie ( Ops [ <NUM_LIT> ] , Ops [ <NUM_LIT> ]


<s> IntID = <STR_LIT> ; break ; } if ( ( RecKind == RecurrenceDescriptor :: RK_FloatMinMax ) || ( RecKind == RecurrenceDescriptor :: RK_IntegerMinMax ) ) { switch ( Desc . getMinMaxRecurrenceKind ( ) ) { default : IntID = <STR_LIT> ; break ; case RecurrenceDescriptor :: MRK_SIntMax : IntID = <STR_LIT> ; break ; case RecurrenceDescriptor :: MRK_SIntMin : IntID = <STR_LIT> ; break ; case RecurrenceDescriptor :: MRK_UIntMax : IntID = <STR_LIT> ; break ; case RecurrenceDescriptor :: MRK_UIntMin : IntID = <STR_LIT> ; break ; case RecurrenceDescriptor :: MRK_FloatMin : IntID = NoNaN ? <STR_LIT> : <STR_LIT> ; break ; case RecurrenceDescriptor :: MRK_FloatMax : IntID = NoNaN ? <STR_LIT> : <STR_LIT> ; break ; } } if ( IntID == <STR_LIT> ) return nullptr ; Constant * Pred = ConstantInt :: getTrue ( VectorType :: getBool ( VTy ) ) ; if ( VTy -> getElementType ( ) -> isIntegerTy ( <NUM_LIT> ) ) { Type * SrcTy = VectorType :: get ( Builder . getInt8Ty ( ) , VTy -> getElementCount ( ) ) ; Src = Builder . CreateZExt ( Src , SrcTy ) ; } Module * M = Builder . GetInsertBlock ( ) -> getParent (


<s> } decl += <STR_LIT> ; decl += utostr ( PM . getParamSize ( * i ) ) ; decl += <STR_LIT> ; decl += PM . getParamName ( * i ) ; } } else { for ( <ISA_LIT>MachineFunctionInfo :: reg_iterator i = MFI -> retreg_begin ( ) , e = MFI -> retreg_end ( ) , b = i ; i != e ; ++ i ) { if ( i != b ) { decl += <STR_LIT> ; } decl += <STR_LIT> ; decl += getRegisterTypeName ( * i , MRI ) ; decl += <STR_LIT> ; decl += MFI -> getRegisterName ( * i ) ; } } decl += <STR_LIT> ; } decl += <STR_LIT> ; decl += CurrentFnSym -> getName ( ) . str ( ) ; decl += <STR_LIT> ; const Function * F = MF -> getFunction ( ) ; if ( isKernel || ST . useParamSpaceForDeviceArgs ( ) ) { int Counter = <NUM_LIT> ; for ( Function :: const_arg_iterator i = F -> arg_begin ( ) , e = F -> arg_end ( ) , b = i ; i != e ; ++ i ) { if ( i != b ) decl += <STR_LIT> ; const Type * ArgType = ( * i ) . getType ( ) ; decl += <STR_LIT> ; if ( ArgType -> isPointerTy ( ) ) { if ( ST . is64Bit ( ) ) decl += <STR_LIT> ; else decl += <STR_LIT> ; } else { decl += utostr ( ArgType -> getPrimitiveSizeInBits ( ) ) ; } if ( ArgType -> isPointerTy ( ) && ST . emitPtrAttribute ( ) ) { const PointerType * PtrType = dyn_cast < const PointerType > ( ArgType ) ; decl += <STR_LIT> ; switch ( PtrType -> getAddressSpace ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : decl += <STR_LIT> ; break ; case <STR_LIT> : decl += <STR_LIT>


<s> void <ISA_LIT>TargetELFStreamer :: emitDirectiveNaN2008 ( ) { MCAssembler & MCA = getStreamer ( ) . getAssembler ( ) ; unsigned Flags = MCA . getELFHeaderEFlags ( ) ; Flags |= ELF :: EF_MIPS_NAN2008 ; MCA . setELFHeaderEFlags


<s> assert ( NumOps == <NUM_LIT> && OpInfo [ <NUM_LIT> ] . RegClass < <NUM_LIT> && OpInfo [ <NUM_LIT> ] . isPredicate ( ) && OpInfo [ <NUM_LIT> ] . RegClass == <STR_LIT> && <STR_LIT> ) ; unsigned Imm8 = getT1Imm8 ( insn ) ; MI . addOperand ( MCOperand :: CreateImm ( Opcode == <STR_LIT> ? SignExtend32 < <NUM_LIT> > ( Imm8 << <NUM_LIT> ) + <NUM_LIT> : ( int ) Imm8 ) ) ; NumOpsAdded = <NUM_LIT> ; return true


<s> if ( ExtendedTy == LD -> getMemoryVT ( ) ) return DAG . getLoad ( LD -> getMemoryVT ( ) , LD -> getDebugLoc ( ) , LD -> getChain ( ) , LD -> getBasePtr ( ) , LD -> getPointerInfo ( ) , LD -> isVolatile ( )

, LD -> isNonTemporal ( ) , LD -> isInvariant ( ) , LD -> getAlignment ( ) ) ;


<s> static vector_insn_info get_hard_empty ( ) { vector_insn_info info


<s> InstrItins = getInstrItineraryForCPU ( CPUName ) ; ParseSubtargetFeatures ( CPUName , CPUName , FS ) ; if ( Is<ISA_LIT>64 && has64BitSupport ( ) ) Use64BitRegs = true ; if ( ( TargetTriple . isOSFreeBSD ( ) && TargetTriple . getOSMajorVersion ( ) >= <NUM_LIT> ) || TargetTriple . isOSNetBSD ( ) || TargetTriple . isOSOpenBSD ( ) || TargetTriple . isMusl ( ) ) SecurePlt = true ; if ( HasSPE && Is<ISA_LIT>64 ) report_fatal_error ( <STR_LIT> , false ) ; if ( HasSPE && ( HasAltivec || HasVSX || HasFPU ) ) report_fatal_error ( <STR_LIT> , false ) ; if ( ! HasSPE ) HasFPU


<s> SmallVector < int , <NUM_LIT> > MaskVec ; SVOp -> getMask ( MaskVec ) ; for ( unsigned i = <NUM_LIT> ; i != NumElems ; ++ i ) { if ( MaskVec [ i ] > ( int ) NumElems ) { MaskVec [ i ] = NumElems ; Changed = true ; } } if ( Changed ) return DAG . getVectorShuffle ( VT , SVOp -> getDebugLoc ( ) , SVOp ->

getOperand ( <NUM_LIT> ) , SVOp -> getOperand ( <NUM_LIT> ) , & MaskVec [ <NUM_LIT> ] ) ;


<s> return ( __m128i ) __builtin_ia32_pabsq128_mask ( ( __v2di ) __A , ( __v2di )

_mm_setzero_si128 ( ) , ( __mmask8 ) - <NUM_LIT> ) ;


<s> for ( const MachineLoop * L : LoopInfo ) L -> print ( dbgs (


<s> break ; case <STR_LIT> : { APInt KnownZero2 , KnownOne2 ; DAG . computeKnownBits ( Op -> getOperand ( <NUM_LIT> ) , KnownZero , KnownOne , Depth + <NUM_LIT> ) ; DAG . computeKnownBits ( Op -> getOperand ( <NUM_LIT> ) , KnownZero2 , KnownOne2 , Depth + <NUM_LIT> ) ; KnownZero &= KnownZero2 ; KnownOne &= KnownOne2 ; break ; } case <STR_LIT> : { ConstantSDNode * CN = cast < ConstantSDNode > ( Op -> getOperand ( <NUM_LIT> ) ) ; <STR_LIT> IntID = static_cast < <STR_LIT> > ( CN -> getZExtValue ( ) ) ; switch ( IntID ) { default : return ; case <STR_LIT> : case <STR_LIT> : { unsigned BitWidth = KnownOne . getBitWidth ( ) ; EVT VT = cast < MemIntrinsicSDNode > ( Op ) -> getMemoryVT ( ) ; unsigned MemBits = VT . getScalarType ( ) . getSizeInBits ( ) ; KnownZero |= APInt :: getHighBitsSet ( BitWidth , BitWidth - MemBits ) ; return ; } } break ; } case


<s> if ( pSym . isDyn ( ) || pSym . isUndef ( ) || pFactory . getTarget (

) . isSymbolPreemptible ( pSym ) ) return false ;


<s> if ( MI0 . getNumOperands ( ) != MI1 . getNumOperands ( ) ) return false ; const MachineOperand & MO0 = MI0 . getOperand ( <NUM_LIT> ) ; const MachineOperand & MO1 = MI1 . getOperand ( <NUM_LIT> ) ; if ( MO0 . getOffset ( ) != MO1 . getOffset ( ) ) return false ; if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ) return MO0 . getGlobal ( ) == MO1 . getGlobal ( ) ; const MachineFunction * MF = MI0 . getParent ( ) -> getParent ( ) ; const MachineConstantPool * MCP = MF -> getConstantPool ( ) ; int CPI0 = MO0 . getIndex ( ) ; int CPI1 = MO1 . getIndex ( ) ; const MachineConstantPoolEntry & MCPE0 = MCP -> getConstants ( ) [ CPI0 ] ; const MachineConstantPoolEntry & MCPE1 = MCP -> getConstants ( ) [ CPI1 ] ; bool is<ISA_LIT>CP0 = MCPE0 . isMachineConstantPoolEntry ( ) ; bool is<ISA_LIT>CP1 = MCPE1 . isMachineConstantPoolEntry ( ) ; if ( is<ISA_LIT>CP0 && is<ISA_LIT>CP1 ) { <ISA_LIT>ConstantPoolValue * ACPV0 = static_cast < <ISA_LIT>ConstantPoolValue * > ( MCPE0 . Val . MachineCPVal ) ; <ISA_LIT>ConstantPoolValue * ACPV1 = static_cast < <ISA_LIT>ConstantPoolValue * > ( MCPE1 . Val . MachineCPVal ) ; return ACPV0 -> hasSameValue ( ACPV1 ) ; } else if ( ! is<ISA_LIT>CP0 && ! is<ISA_LIT>CP1 ) { return MCPE0 . Val . ConstVal == MCPE1 . Val . ConstVal ; } return false ; } else if ( Opcode == <STR_LIT> ) { if ( MI1 . getOpcode ( ) != Opcode ) return false ; if ( MI0 . getNumOperands ( ) != MI1 . getNumOperands ( ) ) return false ; Register Addr0 = MI0 . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register Addr1 = MI1 . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( Addr0 !=


<s> MCCodeGenInfo * X = new MCCodeGenInfo ( ) ; X -> InitMCCodeGenInfo ( RM , CM , OL ) ; return


<s> void addImm1_31Operands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT>


<s> const TargetInstrInfo * TII = Subtarget . getInstrInfo ( ) ; BuildMI ( * BB , MI , dl , TII -> get ( TargetOpcode :: COPY ) , <STR_LIT> ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; BuildMI ( * BB , MI , dl , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) ; BuildMI ( * BB , MI , dl , TII -> get ( <STR_LIT> ) ,


<s> if ( ! MO . isReg ( ) || ! MO . isDef ( ) ) continue ; unsigned CurReg = MO . getReg ( ) ; MapRegToId :: const_iterator ItCurRegId = RegToId . find ( CurReg ) ; if ( ItCurRegId == RegToId . end ( ) ) continue ; for ( MCRegAliasIterator AI ( CurReg , TRI , true ) ; AI . isValid ( ) ; ++ AI ) { MapRegToId :: const_iterator ItRegId = RegToId . find ( * AI ) ; if ( ItRegId == RegToId . end ( ) ) continue ; BBKillSet . set ( ItRegId -> second ) ; BBGen [ ItRegId -> second ] = & MI ; } BBGen [ ItCurRegId -> second ] = & MI ; } } if ( ! ADRPMode && DummyOp && ! MBB . succ_empty ( ) ) for ( unsigned CurReg = <NUM_LIT> ; CurReg < NbReg ; ++ CurReg ) if (

BBGen [ CurReg ] ) getUses ( ColorOpToReachedUses , CurReg , * BBGen [ CurReg ] ) . insert ( DummyOp ) ;


<s> return __builtin_loongson_punpckhhw_u ( s


<s> unsigned <ISA_LIT>TTIImpl :: getNumberOfRegisters ( bool Vector ) const { if ( Vector ) return <NUM_LIT> ; return


<s> gcc_assert ( from == ARG_POINTER_REGNUM || from == FRAME_POINTER_REGNUM ) ; gcc_assert ( to == FRAME_POINTER_REGNUM || to == STACK_POINTER_REGNUM ) ; if ( to == STACK_POINTER_REGNUM ) diff = mn10300_frame_size (


<s> SDValue Mask ; if ( Store -> getMemoryVT ( ) == <STR_LIT> ) { assert ( Store -> getAlignment ( ) >= <NUM_LIT> ) ; Mask = DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; } else if ( Store -> getMemoryVT ( ) == <STR_LIT> ) { assert ( Store -> getAlignment ( ) >= <NUM_LIT> ) ; Mask = DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; ; } else { llvm_unreachable ( <STR_LIT> ) ; } SDValue OldChain = Store -> getChain ( ) ; bool VectorTrunc = ( OldChain . getOpcode ( ) == <STR_LIT> ) ; SDValue Chain = VectorTrunc ? OldChain -> getOperand ( <NUM_LIT> ) : OldChain ; SDValue BasePtr = Store -> getBasePtr ( ) ; SDValue Offset = Store -> getOffset ( ) ; EVT MemVT = Store -> getMemoryVT ( ) ; SDValue LoadPtr = BasePtr ; if ( ! Offset . isUndef ( ) ) { LoadPtr = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , BasePtr , Offset ) ; } SDValue Ptr = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , LoadPtr , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; SDValue Dst = DAG . getLoad ( <STR_LIT> , DL , Chain , Ptr , MachinePointerInfo ( ) ) ; Chain = Dst . getValue ( <NUM_LIT> ) ; SDValue ByteIdx = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , LoadPtr , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; SDValue ShiftAmt = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , ByteIdx , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; SDValue SExtValue = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Store -> getValue ( ) ) ; SDValue MaskedValue = DAG . getZeroExtendInReg ( SExtValue , DL , MemVT


<s> void <ISA_LIT>RegisterInfo :: eliminateFrameIndex ( MachineBasicBlock :: iterator II , int SPAdj , unsigned FIOperandNum , RegScavenger * RS ) const { MachineInstr & MI = * II ; MachineBasicBlock & MBB = * MI . getParent ( ) ; const MachineFunction & MF = * MBB . getParent ( ) ; const MachineFrameInfo MFI = MF . getFrameInfo ( ) ; MachineOperand & FIOp = MI . getOperand ( FIOperandNum ) ; unsigned FI = FIOp . getIndex ( ) ; unsigned ImmOpIdx = <NUM_LIT> ; switch ( MI . getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT>


<s> if ( ! isLoadInst ( MCInstD ) ) return false ; switch ( getSlotOpCode ( MCInstD ) ) { case LOOKUP_C1C2 : case LOOKUP_C0 : case LOOKUP : return true


<s> rtx prev_set = single_set ( prev ) ; rtx curr_set = single_set ( curr ) ; if ( ! prev_set || ! curr_set ) return false ; if ( any_condjump_p ( curr ) ) return false ; if ( ! arm_macro_fusion_p ( ) ) return false ; if ( current_tune -> fusible_ops & tune_params :: FUSE_MOVW_MOVT && arm_sets_movw_movt_fusible_p ( prev_set , curr_set ) ) return true ; return


<s> if ( GenerateSignBits ( V ) ) return false ; if ( ! isa < Instruction > ( V


<s> hwloops [ inu ] . spoiled = true ; inu = hwloops [ inu ] . UpLoop ; } while ( inu != EMPTYREF ) ; } if ( ForceUnHardwareLoops && ! nomorelimitcorrection && hwloops [ li ] . transform ) { unsigned son = hwloops [ li ] . DownLoop ; if ( son != EMPTYREF ) { if ( ! hwloops [ son ] . transform && hwloops [ son ] . RightLoop == EMPTYREF ) { if ( hwloops [ li ] . InstrNumber < <NUM_LIT> * limitsize ) { limitsize = hwloops [ li ] . InstrNumber ; hwloops [ li ] . transform = false ; nomorelimitcorrection = true ; } } } } CurrentTopLoop = hwloops [ li ] . UpLoop ; unsigned int grand = CurrentTopLoop ; while ( grand != EMPTYREF ) { if ( hwloops [ grand ] . LastClosedSon == EMPTYREF ) { hwloops [ grand ] . LastClosedSon


<s> switch ( MI . getOpcode ( ) ) { default : if ( MI . isMetaInstruction ( ) ) return <NUM_LIT> ; return <NUM_LIT> ; case <STR_LIT> : return MI . getOperand ( <NUM_LIT> ) . getImm ( ) + <NUM_LIT> ; case <STR_LIT>


<s> static Reloc :: Model getEffectiveRelocModel ( Optional < Reloc :: Model > RM ) { return RM . getValueOr ( Reloc :: Static


<s> std :: vector < std :: string > D ( T ... t ) { return std :: vector < std :: string > { Dsm ( t


<s> return Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT>

|| Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ;


<s> case AMDGPU :: S_LOAD_DWORDX4_SGPR : unsigned NewOpcode = getVALUOp ( * MI ) ; unsigned Offset = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned SRsrc = MRI . createVirtualRegister ( & AMDGPU :: SReg_128RegClass ) ; unsigned DWord0 = Offset ; unsigned DWord1 = MRI . createVirtualRegister ( & AMDGPU :: SGPR_32RegClass ) ; unsigned DWord2 = MRI . createVirtualRegister ( & AMDGPU :: SGPR_32RegClass ) ; unsigned DWord3 = MRI . createVirtualRegister ( & AMDGPU :: SGPR_32RegClass ) ; BuildMI ( * MBB , MI , MI -> getDebugLoc ( ) , get ( AMDGPU :: S_MOV_B32 ) , DWord1 ) . addImm ( <NUM_LIT> ) ; BuildMI ( * MBB , MI , MI -> getDebugLoc ( ) , get ( AMDGPU :: S_MOV_B32 ) , DWord2 ) . addImm ( AMDGPU :: RSRC_DATA_FORMAT & <NUM_LIT> ) ; BuildMI ( * MBB , MI , MI -> getDebugLoc ( ) , get ( AMDGPU :: S_MOV_B32 ) , DWord3 ) . addImm ( AMDGPU :: RSRC_DATA_FORMAT >> <NUM_LIT> ) ; BuildMI ( * MBB , MI , MI -> getDebugLoc ( ) , get ( AMDGPU :: REG_SEQUENCE ) , SRsrc ) . addReg ( DWord0 ) . addImm ( AMDGPU :: sub0 ) . addReg ( DWord1 ) . addImm ( AMDGPU :: sub1 ) . addReg ( DWord2 ) . addImm ( AMDGPU :: sub2 ) . addReg ( DWord3 ) . addImm ( AMDGPU :: sub3 ) ; MI -> setDesc ( get ( NewOpcode


<s> StringRef getSysReg ( ) const { assert ( Kind == k_SysReg &&


<s> unsigned <ISA_LIT>TTIImpl :: getArithmeticInstrCost ( unsigned Opcode , Type * Ty , TTI :: OperandValueKind Opd1Info , TTI :: OperandValueKind Opd2Info , TTI :: OperandValueProperties Opd1PropInfo , TTI :: OperandValueProperties Opd2PropInfo , ArrayRef < const Value * > Args ) { unsigned Cost = BasicTTIImplBase < <ISA_LIT>TTIImpl > :: getArithmeticInstrCost ( Opcode , Ty , Opd1Info , Opd2Info ,


<s> case <STR_LIT> : Tmp = DAG . getNode ( Op . getOpcode ( ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> , dl , <STR_LIT> , Src ) ; break ; case <STR_LIT> : Tmp = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Src ) ; break ; } SDValue FIPtr = DAG . CreateStackTemporary ( <STR_LIT> ) ; SDValue Chain = DAG . getStore ( DAG . getEntryNode ( ) , dl , Tmp , FIPtr , NULL , <NUM_LIT> , false , false , <NUM_LIT> ) ; if ( Op . getValueType ( ) == <STR_LIT> ) FIPtr = DAG . getNode ( <STR_LIT> , dl , FIPtr . getValueType ( ) , FIPtr , DAG . getConstant ( <NUM_LIT> , FIPtr


<s> bool ContNextScc = true ; if ( It == E || getSCCNum ( SccBeginMBB ) != getSCCNum ( * It ) ) { ++ SccNumIter ; int sccRemainedNumBlk = countActiveBlock ( SccBeginIter , It ) ; if ( sccRemainedNumBlk != <NUM_LIT> && sccRemainedNumBlk >= SccNumBlk ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << getSCCNum ( MBB ) << <STR_LIT> << SccNumIter ; dbgs ( ) << <STR_LIT> ; ) ; ContNextScc = true ; } else if ( sccRemainedNumBlk != <NUM_LIT> && sccRemainedNumBlk < SccNumBlk ) { SccNumBlk = sccRemainedNumBlk ; It = SccBeginIter ; ContNextScc = false ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << getSCCNum ( MBB ) << <STR_LIT> << SccNumIter << '\n' ; ) ; } else { ContNextScc = true ; } } else { ContNextScc = false ; } if ( ContNextScc ) SccBeginMBB = nullptr ; } MachineBasicBlock * EntryMBB = * GraphTraits < MachineFunction * > :: nodes_begin ( FuncRep ) ; if ( EntryMBB -> succ_size ( ) == <NUM_LIT> ) { Finish = true ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; ) ; } else { int NewnumRemainedBlk = countActiveBlock ( OrderedBlks . begin ( ) , OrderedBlks . end ( ) ) ; if ( NewnumRemainedBlk == <NUM_LIT> || NewnumRemainedBlk < NumRemainedBlk ) { MakeProgress = true ; NumRemainedBlk = NewnumRemainedBlk ; } else { MakeProgress = false ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; ) ; } } } while ( ! Finish && MakeProgress ) ; wrapup ( * GraphTraits < MachineFunction * > :: nodes_begin ( FuncRep ) ) ; for ( MBBInfoMap :: iterator It = BlockInfoMap . begin ( ) , E = BlockInfoMap . end ( ) ; It != E ; ++ It ) { if ( ( * It ) . second && ( * It ) . second -> IsRetired ) { assert ( ( ( * It ) . first ) -> getNumber ( ) != - <NUM_LIT> ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << ( ( * It ) . first ) -> getNumber ( ) << <STR_LIT> ; ) ; ( * It ) . first -> eraseFromParent ( ) ; } delete ( * It ) . second ; } BlockInfoMap . clear ( ) ; LLInfoMap . clear ( ) ; if ( ! Finish ) { LLVM_DEBUG ( FuncRep ->


<s> SDValue Lo64 = DAG . getLoad ( <STR_LIT> , dl , LdNode -> getChain ( ) , LoPtr , LdNode -> getPointerInfo ( ) . getWithOffset ( <NUM_LIT> ) , Alignment ) ; SDValue SubRegEven = DAG . getTargetConstant ( <STR_LIT> , dl , <STR_LIT> ) ; SDValue SubRegOdd = DAG . getTargetConstant ( <STR_LIT> , dl , <STR_LIT> ) ; SDNode * InFP128 = DAG . getMachineNode ( TargetOpcode :: IMPLICIT_DEF , dl , <STR_LIT> ) ; InFP128 = DAG . getMachineNode ( TargetOpcode :: INSERT_SUBREG , dl , <STR_LIT> , SDValue ( InFP128 , <NUM_LIT> ) , Hi64 , SubRegEven ) ; InFP128 = DAG . getMachineNode ( TargetOpcode :: INSERT_SUBREG , dl , <STR_LIT> , SDValue ( InFP128 , <NUM_LIT> ) , Lo64 , SubRegOdd ) ; SDValue OutChains [ <NUM_LIT> ] = { SDValue ( Hi64 . getNode ( ) , <NUM_LIT> ) , SDValue ( Lo64 . getNode ( ) , <NUM_LIT> ) } ; SDValue OutChain = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , OutChains ) ; SDValue Ops [ <NUM_LIT> ] = { SDValue (


<s> return ( vector float ) __builtin_altivec_vrsqrtefp ( ( vector


<s> unsigned <STR_LIT> ( SDNode * N ) { if ( ! isa < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) . getNode (


<s> auto MO1 = * MI1 . memoperands_begin ( ) ; auto MO2 = * MI2 . memoperands_begin ( ) ; if ( MO1 -> getAddrSpace ( ) != MO2 -> getAddrSpace ( ) ) return false ; auto Base1 = MO1 -> getValue ( ) ; auto Base2 = MO2 -> getValue ( ) ; if ( ! Base1 || ! Base2 ) return false ; const MachineFunction & MF = * MI1 . getParent ( ) -> getParent ( ) ; const DataLayout & DL = MF . getFunction ( ) . getParent ( ) -> getDataLayout ( ) ; Base1 = GetUnderlyingObject ( Base1 , DL ) ; Base2 = GetUnderlyingObject ( Base1 , DL ) ; if ( isa < UndefValue > ( Base1 ) || isa

< UndefValue > ( Base2 ) ) return false ;


<s> return <STR_LIT> ; case FpABIKind :: S32 : return <STR_LIT> ; case FpABIKind :: S64 : if ( Is32BitABI ) return OddSPReg


<s> if ( IdxN -> isNullValue ( ) && ValTy . getSizeInBits ( ) == <NUM_LIT> ) return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , VecV ) ; } if ( ValWidth == <NUM_LIT> ) { SDValue A0 = getInstr ( <STR_LIT> , dl , <STR_LIT> , { VecV } , DAG ) ; SDValue M0 = DAG . getConstant ( <NUM_LIT> / VecWidth , dl , <STR_LIT> ) ; SDValue I0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , IdxV , M0 ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , A0 , I0 ) ; } unsigned Scale = VecWidth / ValWidth ; assert ( ty ( IdxV ) == <STR_LIT> ) ; unsigned VecRep = <NUM_LIT> / VecWidth ; SDValue S0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , IdxV , DAG . getConstant ( <NUM_LIT> * VecRep , dl , <STR_LIT> ) ) ; SDValue T0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , VecV ) ; SDValue T1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , T0 , S0 ) ; while ( Scale > <NUM_LIT> ) { T1 = DAG . getTargetExtractSubreg ( <STR_LIT> , dl , <STR_LIT> , T1 ) ; T1 = expandPredicate ( T1 , dl , DAG ) ; Scale /= <NUM_LIT> ; } return DAG . getNode ( <STR_LIT> , dl , ResTy , T1 ) ; } assert ( VecWidth == <NUM_LIT> || VecWidth == <NUM_LIT> ) ; MVT ScalarTy = tyScalar ( VecTy ) ; VecV = DAG . getBitcast ( ScalarTy , VecV ) ; SDValue WidthV = DAG . getConstant ( ValWidth , dl , <STR_LIT> ) ; SDValue ExtV ; if ( IdxN ) { unsigned Off = IdxN -> getZExtValue ( ) * ElemWidth ; if ( VecWidth == <NUM_LIT> && ValWidth == <NUM_LIT> ) { assert ( Off == <NUM_LIT> || Off == <NUM_LIT> ) ; unsigned SubIdx = Off == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; ExtV = DAG . getTargetExtractSubreg ( SubIdx , dl , <STR_LIT> , VecV ) ; } else if ( Off == <NUM_LIT> && ( ValWidth % <NUM_LIT> ) == <NUM_LIT> ) { ExtV = DAG . getZeroExtendInReg ( VecV , dl , tyScalar ( ValTy ) ) ; } else { SDValue OffV = DAG . getConstant ( Off , dl , <STR_LIT> ) ; ExtV = DAG . getNode ( <STR_LIT> , dl , ScalarTy , { VecV , WidthV , OffV } ) ; } } else { if ( ty ( IdxV ) != <STR_LIT> ) IdxV = DAG . getZExtOrTrunc ( IdxV , dl , <STR_LIT> ) ; SDValue OffV = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , IdxV

, DAG . getConstant ( ElemWidth , dl , <STR_LIT> ) ) ;


<s> if ( MUST_SAVE_ACC_REGISTER && bit_count ( save_mask ) < <NUM_LIT> ) { save_mask |= ( <NUM_LIT> << <NUM_LIT> ) | ( <NUM_LIT> << <NUM_LIT> ) ; if ( low == <NUM_LIT> ) low = <NUM_LIT> ; if ( high == <NUM_LIT> || low == high ) high = low + <NUM_LIT> ; } pushed_mask = ( - <NUM_LIT> << low ) & ~ ( - <NUM_LIT> << ( high + <NUM_LIT> ) ) ; unneeded_pushes = ( pushed_mask & ( ~ save_mask ) ) & pushed_mask ; if ( ( fixed_reg && fixed_reg <= high ) || ( optimize_function_for_speed_p ( cfun ) && bit_count ( save_mask ) < bit_count ( unneeded_pushes ) ) ) { * lowest = <NUM_LIT> ; * highest = <NUM_LIT> ; * register_mask = save_mask ; } else { * lowest = low ; * highest = high ; * register_mask = <NUM_LIT>


<s> static DecodeStatus DecodeLO32DSPRegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t Address , const void * Decoder ) { if ( RegNo >= <NUM_LIT> ) return MCDisassembler :: Fail ; unsigned Reg = getReg ( Decoder , <STR_LIT> , RegNo ) ; Inst . addOperand ( MCOperand :: CreateReg ( Reg ) ) ; return MCDisassembler :: Success


<s> for ( unsigned I = <NUM_LIT> ; I != Blob . size ( ) / sizeof ( uint32_t ) / <NUM_LIT> ; ++ I ) setRegister ( Data [ I * <NUM_LIT> ] , Data [ I *


<s> else if ( isa < BitCastInst > ( & I ) ) { AddToLazyDeletionSet ( & I ) ; for ( auto * BCUser : cast < BitCastInst > ( & I ) -> users ( ) ) RetVal &=

ProcessUser ( MemOpOffsetMap , * BCUser , Offset , isStruct ) ;


<s> if ( GET_MODE_SIZE ( mode ) >= <NUM_LIT> ) return <NUM_LIT> ; if ( GET_CODE ( addr ) == SYMBOL_REF ) { tree decl = MEM_EXPR ( mem ) ; if ( decl && TREE_CODE ( decl ) == VAR_DECL && GET_MODE ( mem ) == TYPE_MODE ( TREE_TYPE ( decl ) ) ) return <NUM_LIT> ; decl = SYMBOL_REF_DECL


<s> const RegisterBank & EltRB = * RBI . getRegBank ( EltReg , MRI , TRI ) ; const RegisterBank & DstRB = * RBI . getRegBank ( Dst , MRI , TRI ) ; if ( EltRB != DstRB ) return false ; if ( any_of ( make_range ( I . operands_begin ( ) + <NUM_LIT> , I . operands_end ( ) ) , [ & MRI ] ( const MachineOperand & Op ) { return ! getOpcodeDef ( TargetOpcode :: G_IMPLICIT_DEF , Op . getReg ( ) , MRI ) ; } ) ) return false ; unsigned SubReg ; const TargetRegisterClass * EltRC = getRegClassForTypeOnBank ( EltTy , EltRB ) ; if ( ! EltRC ) return false


<s> return ( __mmask8 ) __builtin_ia32_cmpq128_mask ( ( __v2di ) __X , (


<s> <ISA_LIT>MachineFunctionInfo * FuncInfo = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; DebugLoc DL = Op . getDebugLoc ( ) ; SDValue Chain = Op . getOperand ( <NUM_LIT> ) ; SDValue VAList = Op . getOperand ( <NUM_LIT> ) ; const Value * SV = cast < SrcValueSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getValue ( ) ; SmallVector < SDValue , <NUM_LIT> > MemOps ; SDValue Stack = DAG . getFrameIndex ( FuncInfo -> getVariadicStackIdx ( ) , getPointerTy ( ) ) ; MemOps . push_back ( DAG . getStore ( Chain , DL , Stack , VAList , MachinePointerInfo ( SV ) , false , false , <NUM_LIT> ) ) ; int GPRSize = FuncInfo -> getVariadicGPRSize ( ) ; if ( GPRSize > <NUM_LIT> ) { SDValue GRTop , GRTopAddr ; GRTopAddr = DAG . getNode ( <STR_LIT> , DL , getPointerTy ( ) , VAList , DAG . getConstant ( <NUM_LIT> , getPointerTy ( ) ) ) ; GRTop = DAG . getFrameIndex ( FuncInfo -> getVariadicGPRIdx ( ) , getPointerTy ( ) ) ; GRTop = DAG . getNode ( <STR_LIT> , DL , getPointerTy ( ) , GRTop , DAG . getConstant ( GPRSize , getPointerTy ( ) ) ) ; MemOps . push_back ( DAG . getStore ( Chain , DL , GRTop , GRTopAddr , MachinePointerInfo ( SV , <NUM_LIT> )


<s> unsigned RegBits = getMachineOpValue ( MI , MI . getOperand ( OpNo ) , Fixups , STI ) << <NUM_LIT> ; unsigned OffBits = getMachineOpValue ( MI , MI . getOperand


<s> bool hasUnalignedScratchAccess ( ) const { return UnalignedScratchAccess


<s> SDValue Tmp3 = ST -> getValue ( ) ; assert ( Tmp3 . getValueType ( ) == <STR_LIT> && <STR_LIT> ) ; unsigned Alignment = ST -> getAlignment ( ) ; bool isVolatile = ST -> isVolatile ( ) ; bool isNonTemporal = ST -> isNonTemporal ( ) ; Tmp3 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Tmp3


<s> static const char * avr_out_movsi_mr_r_reg_disp_tiny ( rtx op [ ] , int * l ) { rtx dest = op [ <NUM_LIT> ] ; rtx src = op [ <NUM_LIT> ] ; rtx base = XEXP ( dest , <NUM_LIT> ) ; int reg_base = REGNO ( XEXP ( base , <NUM_LIT> ) ) ; int reg_src = true_regnum ( src ) ; if ( reg_base == reg_src ) { * l = <NUM_LIT> ; return ( <STR_LIT> CR_TAB <STR_LIT> CR_TAB TINY_ADIW ( % I0 , % J0 , % o0 ) CR_TAB <STR_LIT> CR_TAB <STR_LIT> CR_TAB <STR_LIT> CR_TAB <STR_LIT>


<s> const <ISA_LIT>Subtarget & STI = MBB . getParent ( ) -> getSubtarget < <ISA_LIT>Subtarget > ( ) ; const <ISA_LIT>InstrInfo * TII = STI . getInstrInfo ( ) ; unsigned NewOpcode = TII -> getEquivalentCompactForm ( Branch ) ; Branch = TII -> genInstrWithNewOpc ( NewOpcode , Branch ) ; std :: next ( Branch ) -> eraseFromParent ( ) ; return Branch


<s> reloc = hi_reloc ? <STR_LIT> : <STR_LIT> ; break ; default : output_operand_lossage ( <STR_LIT> , hi_reloc ? 'h' : 'R' ) ; return ; } fprintf ( file , <STR_LIT> , reloc ) ; output_addr_const ( file , riscv_strip_unspec_address ( op ) ) ; fputc ( ')'


<s> virtual StringRef getPassName ( ) const override


<s> symb = ( * targetm . strip_name_encoding ) ( symb ) ; length = strlen ( symb ) ; symbol_name = alloca ( length + <NUM_LIT> ) ; GEN_SYMBOL_NAME_FOR_SYMBOL ( symbol_name , symb , length ) ; lazy_ptr_name = alloca ( length + <NUM_LIT> ) ; GEN_LAZY_PTR_NAME_FOR_SYMBOL ( lazy_ptr_name , symb , length ) ; if ( flag_pic == <NUM_LIT> ) machopic_picsymbol_stub1_section ( ) ; else machopic_symbol_stub1_section ( ) ; if ( flag_pic == <NUM_LIT> ) { fprintf ( file , <STR_LIT> ) ; fprintf ( file , <STR_LIT> , stub ) ; fprintf ( file , <STR_LIT> , symbol_name ) ; label ++ ; local_label_0 = alloca ( sizeof ( <STR_LIT> ) ) ; sprintf ( local_label_0 , <STR_LIT> , label ) ; fprintf ( file , <STR_LIT> ) ; fprintf ( file , <STR_LIT> , local_label_0 ) ; fprintf ( file , <STR_LIT> , local_label_0 ) ; fprintf ( file , <STR_LIT> , lazy_ptr_name , local_label_0 ) ; fprintf ( file , <STR_LIT> ) ; fprintf ( file , <STR_LIT> , ( TARGET_64BIT ? <STR_LIT> : <STR_LIT> ) , lazy_ptr_name , local_label_0 ) ; fprintf ( file , <STR_LIT> ) ; fprintf ( file , <STR_LIT> ) ; } else { fprintf ( file , <STR_LIT> ) ; fprintf ( file , <STR_LIT> , stub ) ; fprintf ( file , <STR_LIT> , symbol_name ) ; fprintf ( file , <STR_LIT> , lazy_ptr_name ) ; fprintf ( file , <STR_LIT> , ( TARGET_64BIT


<s> * expandedp = false ; d = bdesc_dst ; for ( i = <NUM_LIT> ; i < ARRAY_SIZE ( bdesc_dst ) ; i ++ , d ++ ) if ( d -> code == fcode ) { arg0 = CALL_EXPR_ARG ( exp , <NUM_LIT> ) ; arg1 = CALL_EXPR_ARG ( exp , <NUM_LIT> ) ; arg2 = CALL_EXPR_ARG ( exp , <NUM_LIT> ) ; op0 = expand_normal ( arg0 ) ; op1 = expand_normal ( arg1 ) ; op2 = expand_normal ( arg2 ) ; mode0 = insn_data [ d -> icode ] . operand [ <NUM_LIT> ] . mode ; mode1 = insn_data [ d -> icode ] . operand [ <NUM_LIT> ] . mode ; if ( arg0 == error_mark_node || arg1 == error_mark_node || arg2 == error_mark_node ) return const0_rtx ; * expandedp = true ; STRIP_NOPS ( arg2 ) ; if ( TREE_CODE ( arg2 ) != INTEGER_CST || TREE_INT_CST_LOW ( arg2 ) & ~ <NUM_LIT> ) { error ( <STR_LIT> ,


<s> void <ISA_LIT>TargetLowering :: Lower<ISA_LIT>_KIL ( MachineInstr * MI , MachineBasicBlock & BB , MachineBasicBlock :: iterator I , MachineRegisterInfo & MRI ) const { BuildMI ( BB , I , BB . findDebugLoc ( I ) , TII -> get ( AMDGPU :: V_CMPX_LE_F32_e32 ) , AMDGPU :: VCC ) . addReg (

AMDGPU :: SREG_LIT_0 ) . addOperand ( MI -> getOperand ( <NUM_LIT> ) ) ;


<s> extern __inline __m128 __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) _mm_mul_ss ( __m128 __A , __m128 __B ) { __m128 a , b , c ; static const __vector unsigned int mask = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; a = vec_splat ( __A , <NUM_LIT> ) ; b = vec_splat ( __B , <NUM_LIT> ) ; c = a * b ; return ( vec_sel ( __A , c , mask ) ) ; __A [ <NUM_LIT> ] = __A [ <NUM_LIT> ] * __B [ <NUM_LIT> ] ; return (


<s> SmallVector < CCValAssign , <NUM_LIT> > ValLocs ; CCState CCInfo ( CC , F . isVarArg ( ) , TM , ValLocs , I -> getContext ( ) ) ; CCInfo . AnalyzeReturn ( Outs , RetCC_<ISA_LIT> ) ; const Value * RV = Ret -> getOperand ( <NUM_LIT> ) ; unsigned Reg = getRegForValue ( RV ) ; if ( Reg == <NUM_LIT> ) return false ; if ( ValLocs . size ( ) != <NUM_LIT> ) return false ; CCValAssign & VA = ValLocs [ <NUM_LIT> ] ; if ( VA . getLocInfo ( ) != CCValAssign :: Full ) return false ; if ( ! VA . isRegLoc ( ) ) return false ; if ( TLI . getValueType ( RV -> getType ( ) ) != VA . getValVT ( ) ) return false ; if ( VA . getLocReg ( ) == <STR_LIT> || VA . getLocReg ( ) == <STR_LIT> ) return false ; unsigned SrcReg = Reg + VA . getValNo ( ) ; unsigned DstReg = VA . getLocReg ( ) ; const TargetRegisterClass * SrcRC = MRI . getRegClass


<s> switch ( VT . getSimpleVT ( ) . SimpleTy ) { default : assert ( <STR_LIT> ) ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT>