<s> void LLVMInitialize<ISA_LIT>TargetMC ( ) { RegisterMCAsmInfoFn X ( The<ISA_LIT>Target , create<ISA_LIT>MCAsmInfo ) ; TargetRegistry :: RegisterMCInstrInfo ( The<ISA_LIT>Target , create<ISA_LIT>MCInstrInfo ) ; TargetRegistry :: RegisterMCRegInfo ( The<ISA_LIT>Target , create<ISA_LIT>MCRegisterInfo ) ; TargetRegistry :: RegisterMCSubtargetInfo ( The<ISA_LIT>Target , create<ISA_LIT>MCSubtargetInfoImpl


<s> __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) __blsi_u32 ( unsigned int __X ) { return ( __X & - __X )


<s> SDValue <ISA_LIT>SelectionDAGInfo :: EmitTargetCodeForMemset ( SelectionDAG & DAG , SDLoc DL , SDValue Chain , SDValue Dst , SDValue Byte , SDValue Size , unsigned Align , bool IsVolatile , MachinePointerInfo DstPtrInfo ) const { EVT PtrVT = Dst . getValueType ( ) ; if ( IsVolatile ) return SDValue ( ) ; if ( ConstantSDNode * CSize = dyn_cast < ConstantSDNode > ( Size ) ) { uint64_t Bytes = CSize -> getZExtValue ( ) ; if ( Bytes == <NUM_LIT> ) return SDValue ( ) ; if ( ConstantSDNode * CByte = dyn_cast < ConstantSDNode > ( Byte ) ) { uint64_t ByteVal = CByte -> getZExtValue ( ) ; if ( ByteVal == <NUM_LIT> || ByteVal == <NUM_LIT> ? Bytes <= <NUM_LIT> && CountPopulation_64 ( Bytes ) <= <NUM_LIT> : Bytes <= <NUM_LIT> ) { unsigned Size1 = Bytes == <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> << findLastSet ( Bytes ) ; unsigned Size2 = Bytes - Size1 ; SDValue Chain1 = memsetStore ( DAG , DL , Chain , Dst , ByteVal , Size1 , Align , DstPtrInfo ) ; if ( Size2 == <NUM_LIT> ) return Chain1 ; Dst = DAG . getNode ( <STR_LIT> , DL , PtrVT , Dst , DAG . getConstant ( Size1 , PtrVT ) ) ; DstPtrInfo = DstPtrInfo . getWithOffset ( Size1 ) ; SDValue Chain2 = memsetStore ( DAG , DL , Chain , Dst , ByteVal , Size2 , std :: min ( Align , Size1 ) , DstPtrInfo ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Chain1 , Chain2 ) ; } } else { if ( Bytes <= <NUM_LIT> ) { SDValue Chain1 = DAG . getStore ( Chain , DL , Byte , Dst , DstPtrInfo , false , false , Align ) ; if ( Bytes == <NUM_LIT> ) return Chain1 ; SDValue Dst2 = DAG . getNode ( <STR_LIT> , DL , PtrVT , Dst , DAG . getConstant


<s> default : return true ; case InlineAsm :: Constraint_m : if ( ! SelectAddr ( Op , Op0 , Op1 ) ) return true ; break ; } OutOps . push_back ( Op0


<s> while ( ! DirtySuccessors . empty ( ) ) { MachineBasicBlock & MBB = * DirtySuccessors . back ( ) ; DirtySuccessors . pop_back ( ) ; BlockState & BBState = BlockStates [ MBB . getNumber ( ) ] ; if ( BBState . FirstUnguardedCall != MBB . end ( ) ) insertVZeroUpper ( BBState . FirstUnguardedCall , MBB ) ; if ( BBState . ExitState == PASS_THROUGH ) { DEBUG ( dbgs ( ) << <STR_LIT> << MBB . getNumber ( ) << <STR_LIT> ) ; for ( MachineBasicBlock :: succ_iterator SI = MBB . succ_begin ( ) , SE = MBB . succ_end ( ) ; SI != SE ; ++ SI ) addDirtySuccessor ( * * SI ) ; } } BlockStates . clear


<s> static unsigned computeBytesPoppedByCalleeForSRet ( const <ISA_LIT>Subtarget * Subtarget , CallingConv :: ID CC , ImmutableCallSite * CS ) { if ( Subtarget -> is64Bit ( ) ) return <NUM_LIT> ; if ( Subtarget -> getTargetTriple ( ) . isOSMSVCRT ( ) ) return <NUM_LIT> ; if ( CC == CallingConv :: Fast || CC == CallingConv :: GHC

|| CC == CallingConv :: HiPE ) return <NUM_LIT> ;


<s> assert ( MI . getOpcode ( ) == TargetOpcode :: G_STORE || MI . getOpcode ( ) == TargetOpcode :: G_LOAD ) ; Register ValReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; const LLT ValTy = MRI . getType ( ValReg ) ; if ( ! ValTy . isVector ( ) || ! ValTy . getElementType ( ) . isPointer ( ) || ValTy . getElementType ( ) . getAddressSpace ( ) != <NUM_LIT> ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } MIRBuilder . setInstr ( MI ) ; unsigned PtrSize = ValTy . getElementType ( ) . getSizeInBits ( ) ; const LLT NewTy = LLT :: vector ( ValTy . getNumElements ( ) , PtrSize ) ; auto & MMO = * * MI . memoperands_begin ( ) ; if ( MI . getOpcode ( ) == TargetOpcode :: G_STORE ) { auto Bitcast = MIRBuilder . buildBitcast (


<s> unsigned Srl_imm = <NUM_LIT> ; if ( isOpcWithIntImmediate ( N -> getOperand ( <NUM_LIT> ) . getNode ( ) , <STR_LIT> , Srl_imm ) ) { assert ( Srl_imm > <NUM_LIT> && Srl_imm < <NUM_LIT> && <STR_LIT> ) ; unsigned Width = CountTrailingOnes_32 ( And_imm ) - <NUM_LIT> ; unsigned LSB = Srl_imm ; SDValue Reg0 = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; if ( ( LSB + Width + <NUM_LIT> ) == N -> getValueType ( <NUM_LIT> ) . getSizeInBits ( ) ) { if ( Subtarget -> isThumb ( ) ) { Opc = isSigned ? <STR_LIT> : <STR_LIT> ; SDValue Ops [ ] = { N -> getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) , CurDAG -> getTargetConstant ( LSB , <STR_LIT> ) , getAL ( CurDAG ) , Reg0 , Reg0 } ; return CurDAG -> SelectNodeTo ( N , Opc , <STR_LIT> , Ops , <NUM_LIT> ) ; } <STR_LIT> ShOpcVal = <STR_LIT> ( <STR_LIT> ) ; SDValue ShOpc = CurDAG -> getTargetConstant ( <STR_LIT> ( ShOpcVal , LSB ) , <STR_LIT> ) ; SDValue Ops [ ] = { N -> getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) , ShOpc , getAL ( CurDAG ) , Reg0 , Reg0 } ; return CurDAG -> SelectNodeTo ( N , <STR_LIT> , <STR_LIT> , Ops , <NUM_LIT> ) ; } SDValue Ops [ ] = { N -> getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) , CurDAG -> getTargetConstant ( LSB , <STR_LIT> ) , CurDAG -> getTargetConstant ( Width , <STR_LIT> ) , getAL ( CurDAG ) , Reg0 } ; return CurDAG -> SelectNodeTo ( N , Opc , <STR_LIT> , Ops , <NUM_LIT> ) ; } } return nullptr ; } unsigned Shl_imm = <NUM_LIT> ; if ( isOpcWithIntImmediate ( N -> getOperand ( <NUM_LIT> ) . getNode ( ) , <STR_LIT> , Shl_imm ) ) { assert ( Shl_imm > <NUM_LIT> && Shl_imm < <NUM_LIT> && <STR_LIT> ) ; unsigned Srl_imm = <NUM_LIT> ; if ( isInt32Immediate ( N -> getOperand ( <NUM_LIT> ) , Srl_imm ) ) { assert ( Srl_imm > <NUM_LIT> && Srl_imm < <NUM_LIT> && <STR_LIT> ) ; unsigned Width = <NUM_LIT> - Srl_imm - <NUM_LIT> ; int LSB = Srl_imm - Shl_imm ; if ( LSB < <NUM_LIT> ) return


<s> enum attr_type type ; if ( ! insn || ! NONDEBUG_INSN_P ( insn ) || GET_CODE ( PATTERN ( insn ) ) == USE || GET_CODE ( PATTERN ( insn ) ) == CLOBBER ) return false ; type = get_attr_type ( insn ) ; if ( type == TYPE_MUL || type == TYPE_DIV || type == TYPE_SDIV || type == TYPE_DDIV || type == TYPE_SSQRT || type == TYPE_DSQRT || type == TYPE_MFCR || type ==


<s> break ; case Immediate : getImm ( ) -> print ( OS ) ; break ; case Memory : OS << <STR_LIT> ; break ; case Register : OS << <STR_LIT> << getReg ( ) <<


<s> MCAsmBackend * llvm :: create<ISA_LIT>AsmBackend ( const Target & T , const MCSubtargetInfo &

STI , const MCRegisterInfo & MRI , const MCTargetOptions & Options ) {


<s> inline MachineInstrBuilder buildPACIA ( MachineBasicBlock & MBB , const DebugLoc & DL , unsigned Ptr , unsigned


<s> OffsetPos ++ ; } if ( ! MI . getOperand ( BasePos ) . isReg ( ) || ! MI . getOperand ( OffsetPos ) . isImm ( ) ) return false ; return true


<s> return SelectShiftedRegister ( N , true


<s> bool Changed = false ; if ( MOI . isAtomic ( ) ) { if ( MOI . getOrdering ( ) == AtomicOrdering :: Monotonic || MOI . getOrdering ( ) == AtomicOrdering :: Acquire || MOI . getOrdering ( ) == AtomicOrdering :: Release || MOI . getOrdering ( ) == AtomicOrdering :: AcquireRelease || MOI . getOrdering ( ) == AtomicOrdering :: SequentiallyConsistent ) { Changed |= CC -> enableRMWCacheBypass ( MI , MOI . getScope ( ) , MOI . getInstrAddrSpace ( ) ) ; } if ( MOI . getOrdering ( ) == AtomicOrdering :: Release || MOI . getOrdering ( ) == AtomicOrdering :: AcquireRelease || MOI . getOrdering ( ) == AtomicOrdering :: SequentiallyConsistent || MOI . getFailureOrdering ( ) == AtomicOrdering :: SequentiallyConsistent ) Changed |= CC -> insertRelease ( MI , MOI . getScope ( ) , MOI . getOrderingAddrSpace ( ) , MOI . getIsCrossAddressSpaceOrdering ( ) , Position :: BEFORE ) ; if ( MOI . getOrdering ( ) == AtomicOrdering :: Acquire || MOI . getOrdering ( ) == AtomicOrdering :: AcquireRelease || MOI . getOrdering ( ) == AtomicOrdering :: SequentiallyConsistent || MOI . getFailureOrdering ( ) == AtomicOrdering :: Acquire || MOI . getFailureOrdering ( ) == AtomicOrdering :: SequentiallyConsistent ) { Changed |= CC -> insertWait ( MI , MOI . getScope ( ) , MOI . getInstrAddrSpace ( ) , isAtomicRet


<s> unsigned getTargetConvertType ( const <ISA_LIT>Subtarget & Subtarget ) { if ( Subtarget . hasGaudiISA ( ) )


<s> ( ( <ISA_LIT>Operand & ) * Operands [ I - <NUM_LIT> ] ) . addRegOperands ( Inst , <NUM_LIT> ) ; } OptionalImmIndexMap OptionalIdx ; for ( unsigned E = Operands . size ( ) ; I != E ; ++ I ) { <ISA_LIT>Operand & Op = ( ( <ISA_LIT>Operand & ) * Operands [ I ] ) ; if ( Op . isReg ( ) ) { Op . addRegOperands ( Inst , <NUM_LIT> ) ; } else if ( Op . isImmModifier ( ) ) { OptionalIdx [ Op . getImmTy ( ) ] = I ; } else if ( ! Op . isToken ( ) ) { llvm_unreachable ( <STR_LIT> ) ; } } bool IsGFX10Plus = isGFX10Plus ( ) ; addOptionalImmOperand ( Inst , Operands , OptionalIdx , <ISA_LIT>Operand :: ImmTyDMask ) ; if ( IsGFX10Plus ) addOptionalImmOperand ( Inst , Operands , OptionalIdx , <ISA_LIT>Operand :: ImmTyDim , - <NUM_LIT> ) ; addOptionalImmOperand ( Inst , Operands , OptionalIdx , <ISA_LIT>Operand :: ImmTyUNorm ) ; if ( IsGFX10Plus ) addOptionalImmOperand ( Inst , Operands , OptionalIdx , <ISA_LIT>Operand :: ImmTyDLC ) ; addOptionalImmOperand ( Inst , Operands , OptionalIdx ,


<s> unsigned getBranchTargetOpValue ( const MachineInstr & MI , unsigned Op


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> :


<s> MCInst CInst ; bool Res = compressInst ( CInst , Inst , *

Subtarget , OutStreamer -> getContext ( ) ) ;


<s> unsigned <ISA_LIT>InstrInfo :: RemoveBranch ( MachineBasicBlock & MBB ) const { MachineBasicBlock :: iterator I = MBB . end ( ) ; unsigned Count = <NUM_LIT> ; while ( I != MBB . begin ( ) ) { --


<s> std :: vector < std :: string > add_sub_i_mov_j ( ArpRn1 a , ArpStep1 asi , ArpStep1 asj , Ab b ) { return D ( <STR_LIT> , MemARPSI ( a , asi ) , R ( b ) , <STR_LIT> , R ( b ) , MemARPSJ ( a ,


<s> void addArithmeticShifterOperands ( MCInst & Inst , unsigned N


<s> <ISA_LIT>FunctionInfo ( ) : isThumb ( false ) , hasThumb2 ( false ) , ArgRegsSaveSize ( <NUM_LIT> ) , ReturnRegsCount ( <NUM_LIT> ) , HasStackFrame ( false ) , RestoreSPFromFP ( false ) , LRSpilledForFarJump ( false ) , FramePtrSpillOffset ( <NUM_LIT> ) , GPRCS1Offset ( <NUM_LIT> ) , GPRCS2Offset ( <NUM_LIT> ) , DPRCSOffset ( <NUM_LIT> ) , GPRCS1Size ( <NUM_LIT> ) , GPRCS2Size ( <NUM_LIT> ) , DPRCSAlignGapSize ( <NUM_LIT> ) , DPRCSSize ( <NUM_LIT> ) , NumAlignedDPRCS2Regs ( <NUM_LIT> ) , PICLabelUId ( <NUM_LIT> ) , VarArgsFrameIndex

( <NUM_LIT> ) , HasITBlocks ( false ) , IsSplitCSR ( false ) {


<s> if ( * insn_ptr && r10k_needs_protection_p_1 ( x , *


<s> llvm_unreachable ( <STR_LIT> ) ; case AtomicOrdering :: Monotonic : return PtrIsCap ? <STR_LIT> : <STR_LIT> ; case AtomicOrdering :: Acquire : return PtrIsCap ? <STR_LIT> : <STR_LIT> ; case AtomicOrdering :: Release : return PtrIsCap ? <STR_LIT> : <STR_LIT> ; case AtomicOrdering :: AcquireRelease : return PtrIsCap ? <STR_LIT> :


<s> const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; if ( ! DCI . isBeforeLegalize ( ) && ! TLI . isTypeLegal ( VT . getVectorElementType ( ) ) ) return SDValue ( ) ; if ( TLI . isTypeLegal ( VT ) ) if ( SDValue AddSub = combineShuffleToAddSub ( N , Subtarget , DAG ) ) return AddSub ; if ( ! DCI . isBeforeLegalize ( ) && DCI . isBeforeLegalizeOps ( ) && N -> getOpcode ( ) == <STR_LIT> && N -> getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> && N -> getOperand ( <NUM_LIT> ) . isUndef ( ) && N -> getOperand ( <NUM_LIT> ) . hasOneUse ( ) ) { SDValue N0 = N -> getOperand ( <NUM_LIT> ) ; SDValue N1 = N -> getOperand ( <NUM_LIT> ) ; SDValue BC0 = N0 . getOperand ( <NUM_LIT> ) ; EVT SVT = BC0 . getValueType ( ) ; unsigned Opcode = BC0 . getOpcode ( ) ; unsigned NumElts = VT . getVectorNumElements ( ) ; if ( BC0 . hasOneUse ( ) && SVT . isVector ( ) && SVT . getVectorNumElements ( ) * <NUM_LIT> == NumElts && TLI . isOperationLegal ( Opcode , VT ) ) { bool CanFold = false ; switch ( Opcode ) { default : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> Data8bitsDirective = <STR_LIT> ; Data16bitsDirective = nullptr ; Data32bitsDirective = <STR_LIT> ; Data64bitsDirective = <STR_LIT> ; ZeroDirective = <STR_LIT> ; AsciiDirective = nullptr ; AscizDirective = nullptr ; SupportsQuotedNames = false ; SupportsExtendedDwarfLocDirective = false ; SupportsSignedData = false ; PrivateGlobalPrefix = <STR_LIT> ; PrivateLabelPrefix = PrivateGlobalPrefix ; WeakDirective = <STR_LIT> ; GlobalDirective =


<s> if ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) != <STR_LIT> ) { return Op ; } RTLIB :: Libcall LC ; if ( Op . getOpcode ( ) == <STR_LIT> ) LC = RTLIB :: getFPTOSINT ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) , Op . getValueType ( ) ) ; else LC = RTLIB :: getFPTOUINT ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) , Op . getValueType ( ) ) ; SmallVector < SDValue , <NUM_LIT> > Ops ( Op -> op_begin ( ) , Op -> op_end ( ) ) ; MakeLibCallOptions CallOptions ; return makeLibCall ( DAG , LC , Op . getValueType ( ) ,

Ops , CallOptions , SDLoc ( Op ) ) . first ;


<s> return ia64_function_arg_1 ( cum , arg


<s> return D ( <STR_LIT> , <STR_LIT> , MemARS ( b , bs )


<s> Type * Ty = V -> getType ( ) ; if ( Ty -> isVoidTy ( ) || Ty -> isPointerTy ( ) ) return true ; if ( auto * Ld = dyn_cast < LoadInst > ( V ) ) Ty = cast < PointerType > ( Ld -> getPointerOperandType ( ) ) -> getElementType ( ) ; const IntegerType * IntTy = dyn_cast <


<s> if ( UseDFAHazardRec ) { auto & HST = DAG -> MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; return new <ISA_LIT>HazardRecognizer ( II , this , HST ) ; } return TargetInstrInfo :: CreateTargetPostRAHazardRecognizer (


<s> if ( IsFixed || Info . hasWorkGroupIDX ( ) ) allocateSGPR32Input ( CCInfo , ArgInfo . WorkGroupIDX ) ; if ( IsFixed || Info . hasWorkGroupIDY ( ) ) allocateSGPR32Input ( CCInfo , ArgInfo . WorkGroupIDY ) ; if ( IsFixed || Info . hasWorkGroupIDZ ( ) ) allocateSGPR32Input ( CCInfo , ArgInfo


<s> return ( __m128i ) __builtin_ia32_pmovsdw128_mask ( ( __v4si ) __A , ( __v8hi ) _mm_setzero_si128 ( ) ,


<s> unsigned <ISA_LIT>LoadStoreOptimizer :: getNewOpcode ( const CombineInfo & CI ) { const unsigned Width = CI . Width0 + CI . Width1 ; switch ( CI . InstClass ) { default : assert ( CI . InstClass == BUFFER_LOAD || CI . InstClass == BUFFER_STORE ) ; return <STR_LIT> ( <STR_LIT> ( CI . I -> getOpcode ( ) ) , Width ) ; case


<s> bool <ISA_LIT>FrameLowering :: expandStoreVec ( MachineBasicBlock & B , MachineBasicBlock :: iterator It , MachineRegisterInfo & MRI , const <ISA_LIT>InstrInfo & HII , SmallVectorImpl < unsigned > & NewRegs ) const { MachineFunction & MF = * B . getParent ( ) ; auto & HST = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; auto & MFI = MF . getFrameInfo ( ) ; MachineInstr * MI = & * It ; DebugLoc DL = MI -> getDebugLoc ( ) ; unsigned SrcR = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; bool IsKill = MI -> getOperand ( <NUM_LIT> ) . isKill ( ) ; assert ( MI -> getOperand ( <NUM_LIT> ) . isFI ( ) && <STR_LIT> ) ; int FI = MI -> getOperand ( <NUM_LIT> ) . getIndex ( ) ; bool Is128B = HST . useHVXDblOps ( ) ; auto * RC = ! Is128B ? & <STR_LIT> : & <STR_LIT> ; unsigned NeedAlign = RC ->


<s> if ( ! isa < Constant > ( Icmp1Op1 ) ) return false ; isCandidate = true ; continue ; } if ( Inst -> getParent ( ) == I . getParent ( ) ) continue ; for ( auto & I2 : * Inst -> getParent ( ) ) { if ( dyn_cast < CallInst > ( & I2 ) ) return false ; if ( dyn_cast < LoadInst > ( & I2 ) || dyn_cast < StoreInst > ( & I2 ) ) return false ; if ( & I2 == Inst ) break ; } if ( Inst -> getOpcode ( ) == Instruction :: ZExt || Inst -> getOpcode ( ) == Instruction :: SExt ) { PassThroughInfo Info ( & I , Inst


<s> const GCNSubtarget & ST = TM . getSubtarget < GCNSubtarget > ( F ) ; return ST . supportsGetDoorbellID (


<s> rtx insn ; emit_move_insn ( regno_reg_rtx [ <NUM_LIT> ] , dst_reg ) ; emit_move_insn ( regno_reg_rtx [ <NUM_LIT> ] , src_reg ) ; emit_move_insn ( regno_reg_rtx [ <NUM_LIT> ] , bytes_rtx ) ; insn = gen_rtx_PARALLEL ( VOIDmode , rtvec_alloc ( <NUM_LIT> ) ) ; XVECEXP ( insn , <NUM_LIT> , <NUM_LIT> ) = gen_rtx_SET ( replace_equiv_address_nv ( dst , regno_reg_rtx [ <NUM_LIT> ] ) , replace_equiv_address_nv ( src , regno_reg_rtx [ <NUM_LIT> ] ) ) ; XVECEXP ( insn , <NUM_LIT> , <NUM_LIT> ) = gen_rtx_USE ( VOIDmode , regno_reg_rtx [ <NUM_LIT> ] ) ; for ( i = <NUM_LIT> ; i <= <NUM_LIT> ; i ++ ) XVECEXP ( insn , <NUM_LIT> , <NUM_LIT> + i ) = gen_rtx_CLOBBER (


<s> for ( p = mips_cpu_info_table ; p -> name != <NUM_LIT> ; p ++ ) if ( p -> isa == isa ) return p ; return


<s> void <ISA_LIT>ImageHandles :: clearImageArgs


<s> Inst . addOperand ( MCOperand :: CreateImm ( - ( CE -> getValue ( ) /


<s> if ( OffsetRB -> getID ( ) != <STR_LIT> ) return false ; MachineInstr * OffsetDef = getDefIgnoringCopies ( BaseOffset , * MRI ) ; assert ( OffsetDef ) ; unsigned ImmOffset ; MachineBasicBlock * MBB = MI . getParent ( ) ; const DebugLoc & DL = MI . getDebugLoc ( ) ; MachineInstr * Readfirstlane = nullptr ; if ( OffsetDef -> getOpcode ( ) == <STR_LIT> ) { Readfirstlane = OffsetDef ; BaseOffset = OffsetDef -> getOperand ( <NUM_LIT> ) . getReg ( ) ; OffsetDef = getDefIgnoringCopies ( BaseOffset , * MRI ) ; } if ( OffsetDef -> getOpcode ( ) == <STR_LIT> ) { ImmOffset = OffsetDef -> getOperand ( <NUM_LIT> ) . getCImm ( ) -> getZExtValue ( ) ; BuildMI ( * MBB , & MI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addImm ( <NUM_LIT> ) ; } else { std :: tie ( BaseOffset , ImmOffset , OffsetDef )


<s> unsigned <ISA_LIT>InstrInfo :: isLoadFromStackSlotPostFE ( const MachineInstr *


<s> const TargetRegisterClass * <ISA_LIT>RegisterInfo :: getPointerRegClass ( const MachineFunction & MF , unsigned Kind ) const { if ( Subtarget . is<ISA_LIT>64 ( ) ) return & <STR_LIT> ; return & <STR_LIT>


<s> if ( CM == CodeModel :: Large && STI . is64Bit ( ) ) { unsigned AddrReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * I . getParent ( ) , I , DbgLoc , TII . get ( <STR_LIT> ) , AddrReg ) . addConstantPoolIndex ( CPI , <NUM_LIT> , OpFlag ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getConstantPool ( MF ) , MachineMemOperand :: MOLoad , MF . getDataLayout ( ) . getPointerSize ( ) , Align ) ; LoadInst = addDirectMem ( BuildMI ( * I . getParent ( ) , I , DbgLoc , TII . get ( Opc ) , DstReg ) , AddrReg ) . addMemOperand ( MMO ) ; } else if ( CM == CodeModel :: Small || ! STI . is64Bit ( ) ) { unsigned PICBase = <NUM_LIT> ; if ( OpFlag == <STR_LIT> || OpFlag ==


<s> case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) { if ( Align >= <NUM_LIT> && getRegisterInfo ( ) . needsStackRealignment ( MF ) ) { AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addMemOperand ( MMO ) ) ; } else { AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addFrameIndex ( FI ) . addMemOperand ( MMO ) ) ; } } else llvm_unreachable ( <STR_LIT> ) ; break ; case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) { if ( Align >= <NUM_LIT> && getRegisterInfo ( ) . canRealignStack ( MF ) ) { AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addMemOperand ( MMO ) ) ; } else { MachineInstrBuilder MIB = AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) ) . addMemOperand ( MMO ) ; MIB = AddDReg ( MIB , SrcReg , <STR_LIT> , getKillRegState ( isKill ) , TRI ) ; MIB = AddDReg ( MIB , SrcReg , <STR_LIT>


<s> return CurDAG -> getTargetConstant ( Imm , DL ,


<s> } else if ( <STR_LIT> . contains ( Reg ) && Reg != <STR_LIT> ) { HiRegsToSave . insert ( Reg ) ; } else { llvm_unreachable ( <STR_LIT> ) ; } if ( ( <STR_LIT> . contains ( Reg ) || Reg == <STR_LIT> ) && ! MF . getRegInfo ( ) . isLiveIn ( Reg ) && ! ( hasFP ( MF ) && Reg == RegInfo -> getFrameRegister ( MF ) ) ) CopyRegs . insert ( Reg ) ; } for ( unsigned ArgReg : { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ) if ( ! MF . getRegInfo ( ) . isLiveIn ( ArgReg ) ) CopyRegs . insert ( ArgReg ) ; if ( ! LoRegsToSave . empty ( ) ) { MachineInstrBuilder MIB = BuildMI ( MBB , MI , DL , TII . get ( <STR_LIT> ) ) ; AddDefaultPred ( MIB ) ; for ( unsigned Reg : { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ) { if ( LoRegsToSave . count ( Reg ) ) { bool isKill = ! MF . getRegInfo ( ) . isLiveIn ( Reg ) ; if ( isKill ) MBB . addLiveIn ( Reg ) ; MIB . addReg ( Reg , getKillRegState ( isKill ) ) ; } } MIB . setMIFlags ( MachineInstr :: FrameSetup ) ; } static const unsigned AllCopyRegs [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; static const unsigned AllHighRegs [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; const unsigned * AllCopyRegsEnd = std :: end ( AllCopyRegs ) ; const unsigned * AllHighRegsEnd = std :: end ( AllHighRegs ) ; const unsigned * HiRegToSave = findNextOrderedReg ( std :: begin ( AllHighRegs ) , HiRegsToSave , AllHighRegsEnd ) ; while ( HiRegToSave != AllHighRegsEnd ) { const unsigned * CopyReg = findNextOrderedReg ( std :: begin ( AllCopyRegs ) , CopyRegs , AllCopyRegsEnd ) ; MachineInstrBuilder PushMIB = BuildMI ( MF , DL , TII . get ( <STR_LIT> ) ) ; AddDefaultPred ( PushMIB ) ; SmallVector < unsigned , <NUM_LIT> > RegsToPush ; while ( HiRegToSave != AllHighRegsEnd && CopyReg != AllCopyRegsEnd ) { if ( HiRegsToSave . count ( * HiRegToSave ) ) { bool isKill = ! MF . getRegInfo ( ) . isLiveIn (


<s> static rtx vax_builtin_setjmp_frame_value ( void )


<s> static DecodeStatus DecodeVCVTQ ( MCInst & Inst , unsigned Insn , uint64_t Address , const void * Decoder ) { const FeatureBitset & featureBits = ( ( const MCDisassembler * ) Decoder ) -> getSubtargetInfo ( ) . getFeatureBits ( ) ; bool hasFullFP16 = featureBits [ <STR_LIT> ] ; unsigned Vd = ( fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ) ; Vd |= ( fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ) ; unsigned Vm = ( fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ) ; Vm |= ( fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ) ; unsigned imm = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned cmode = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned op = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; DecodeStatus S = MCDisassembler :: Success ; if ( ! ( imm & <NUM_LIT> ) ) { if ( cmode == <NUM_LIT> ) { if ( op == <NUM_LIT> ) return MCDisassembler :: Fail ; Inst . setOpcode ( <STR_LIT> ) ; } if ( hasFullFP16 ) { if ( cmode == <NUM_LIT> ) { if ( op == <NUM_LIT> ) { Inst . setOpcode ( <STR_LIT> ) ; } else { Inst . setOpcode (


<s> bool <ISA_LIT>TargetLowering :: isFPImmLegal ( const APFloat & Imm , EVT VT ) const { if ( ! Subtarget -> hasVFP3 ( ) )


<s> bool <ISA_LIT>ATTAsmParser :: ParseRegister ( unsigned & RegNo , SMLoc & StartLoc , SMLoc & EndLoc ) { RegNo = <NUM_LIT> ; const AsmToken & TokPercent = Parser . getTok ( ) ; assert ( TokPercent . is ( AsmToken :: Percent ) && <STR_LIT> ) ; StartLoc = TokPercent . getLoc ( ) ; Parser . Lex ( ) ; const AsmToken & Tok = Parser . getTok ( ) ; if ( Tok . isNot ( AsmToken :: Identifier ) ) return Error ( StartLoc , <STR_LIT> , SMRange ( StartLoc , Tok . getEndLoc ( ) ) ) ; RegNo = MatchRegisterName ( Tok . getString ( ) ) ; if ( RegNo == <NUM_LIT> ) RegNo = MatchRegisterName ( LowercaseString ( Tok . getString ( ) ) ) ; if ( ! is64BitMode ( ) ) { if ( RegNo == <STR_LIT> || <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( RegNo ) || <STR_LIT> ( RegNo ) || <STR_LIT> ( RegNo ) ) return Error ( StartLoc , <STR_LIT> + Tok . getString ( ) + <STR_LIT> , SMRange ( StartLoc , Tok . getEndLoc ( ) ) ) ; } if ( RegNo == <NUM_LIT> && ( Tok . getString ( ) == <STR_LIT> ||


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { if ( DCI . isBeforeLegalize ( ) ) break ; return performMemSDNodeCombine ( cast < MemSDNode > ( N ) , DCI ) ; } case <STR_LIT> : return performAndCombine ( N , DCI ) ; case <STR_LIT> : return performOrCombine ( N , DCI ) ; case <STR_LIT> : return performXorCombine ( N , DCI ) ; case <STR_LIT> : return performClassCombine ( N , DCI ) ; case <STR_LIT> : return performFCanonicalizeCombine ( N , DCI ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { SDValue Src = N -> getOperand ( <NUM_LIT> ) ; if ( Src . isUndef ( ) ) return Src ; break ; } case <STR_LIT> : case <STR_LIT> : return performUCharToFloatCombine ( N , DCI ) ; case <STR_LIT> : case <STR_LIT>


) _mm512_undefined_epi32 ( ) , ( __mmask16 ) - <NUM_LIT> ) ;


<s> Hi32 = DAG . getNode ( opcode , dl , <STR_LIT> , Hi32 ) ; SDValue DstReg64 = SDValue ( DAG . getMachineNode ( TargetOpcode :: IMPLICIT_DEF , dl , <STR_LIT> ) , <NUM_LIT> ) ; DstReg64 = DAG . getTargetInsertSubreg ( <STR_LIT> , dl , <STR_LIT> , DstReg64 , Hi32 ) ; DstReg64 = DAG . getTargetInsertSubreg ( <STR_LIT> , dl , <STR_LIT> , DstReg64 , Lo32 ) ; return


<s> } else { if ( ( Addr . getOpcode ( ) == <STR_LIT> || Addr . getOpcode ( ) == <STR_LIT> ) ) return false ; } if ( CurDAG -> isBaseWithConstantOffset ( Addr ) ) { ConstantSDNode * CN = dyn_cast < ConstantSDNode > ( Addr . getOperand ( <NUM_LIT> ) ) ; if ( isInt < <NUM_LIT> > ( CN -> getSExtValue ( ) ) ) { if ( FrameIndexSDNode * FIN = dyn_cast < FrameIndexSDNode > ( Addr . getOperand ( <NUM_LIT> ) ) ) Base = CurDAG -> getTargetFrameIndex ( FIN -> getIndex ( ) , <STR_LIT> ) ; else Base = Addr . getOperand ( <NUM_LIT> ) ; Offset = CurDAG -> getTargetConstant ( CN -> getZExtValue ( ) , <STR_LIT> ) ; return true ; } } if ( Addr . getOpcode ( ) == <STR_LIT> ) { if ( ConstantSDNode * CN = dyn_cast < ConstantSDNode > ( Addr . getOperand ( <NUM_LIT> ) ) ) { if ( isUInt < <NUM_LIT> > ( CN -> getZExtValue ( ) ) ) { if ( FrameIndexSDNode * FIN = dyn_cast < FrameIndexSDNode > ( Addr . getOperand ( <NUM_LIT> ) ) ) { Base = CurDAG -> getTargetFrameIndex ( FIN -> getIndex ( ) , <STR_LIT> ) ; } else { Base = Addr .


<s> } SmallVector < CCValAssign , <NUM_LIT> > ArgLocs ; CCState CCInfo ( CallConv , isVarArg , DAG . getMachineFunction ( ) , ArgLocs , * DAG . getContext ( ) ) ; if ( Info -> getShaderType ( ) == ShaderType :: PIXEL && ( Info -> P<ISA_LIT>nputAddr & <NUM_LIT> ) == <NUM_LIT> ) { Info -> P<ISA_LIT>nputAddr |= <NUM_LIT> ; CCInfo . AllocateReg ( AMDGPU :: VGPR0 ) ; CCInfo . AllocateReg ( AMDGPU :: VGPR1 ) ; } if ( Info -> getShaderType ( ) == ShaderType :: COMPUTE ) { if ( Subtarget -> isAmdHsaOS ( ) ) Info -> NumUserSGPRs = <NUM_LIT> ; else Info -> NumUserSGPRs = <NUM_LIT> ; unsigned InputPtrReg = TRI -> getPreloadedValue ( MF , <ISA_LIT>RegisterInfo :: INPUT_PTR ) ; unsigned InputPtrRegLo = TRI -> getPhysRegSubReg ( InputPtrReg , & AMDGPU :: SReg_32RegClass , <NUM_LIT> ) ; unsigned InputPtrRegHi = TRI -> getPhysRegSubReg ( InputPtrReg , & AMDGPU :: SReg_32RegClass , <NUM_LIT> ) ; unsigned ScratchPtrReg = TRI -> getPreloadedValue ( MF , <ISA_LIT>RegisterInfo :: SCRATCH_PTR ) ; unsigned ScratchPtrRegLo = TRI -> getPhysRegSubReg ( ScratchPtrReg , & AMDGPU :: SReg_32RegClass , <NUM_LIT> ) ; unsigned ScratchPtrRegHi = TRI -> getPhysRegSubReg ( ScratchPtrReg , & AMDGPU :: SReg_32RegClass , <NUM_LIT> ) ; CCInfo . AllocateReg ( InputPtrRegLo ) ; CCInfo . AllocateReg ( InputPtrRegHi ) ; CCInfo . AllocateReg ( ScratchPtrRegLo ) ; CCInfo . AllocateReg ( ScratchPtrRegHi ) ; MF . addLiveIn ( InputPtrReg , & AMDGPU :: SReg_64RegClass ) ; MF . addLiveIn ( ScratchPtrReg , & AMDGPU :: SReg_64RegClass ) ; } if ( Info -> getShaderType ( ) == ShaderType :: COMPUTE ) { getOriginalFunctionArgs ( DAG , DAG . getMachineFunction ( ) . getFunction ( ) , Ins , Splits ) ; } AnalyzeFormalArguments ( CCInfo , Splits ) ; for ( unsigned i = <NUM_LIT> , e = Ins . size ( ) , ArgIdx = <NUM_LIT> ; i != e ; ++ i ) { const <STR_LIT> & Arg = Ins [ i ] ; if ( Skipped [ i ] ) { InVals . push_back ( DAG . getUNDEF ( Arg . VT ) ) ; continue ; } CCValAssign & VA = ArgLocs [ ArgIdx ++ ] ; MVT VT = VA . getLocVT ( ) ; if ( VA . isMemLoc (


<s> I . setDesc ( TII . get ( NewOpc ) ) ; MachineInstrBuilder MIB ( MF , I ) ; if ( Opc == TargetOpcode :: G_FRAME_INDEX ) { addOffset ( MIB , <NUM_LIT> ) ; } else { MachineOperand & InxOp = I . getOperand ( <NUM_LIT> ) ; I . addOperand ( InxOp ) ; InxOp . ChangeToImmediate ( <NUM_LIT> ) ; MIB . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) ; } return constrainSelectedInstRegOperands ( I , TII , TRI ,


<s> Value * <ISA_LIT>IREmitter :: visitHADD ( const SDNode * N ) { llvm_unreachable ( <STR_LIT> )


, const_tree type , bool named ATTRIBUTE_UNUSED ) {


<s> I . addOperand ( * MF , MachineOperand :: CreateImm ( <NUM_LIT> ) ) ; return constrainSelectedInstRegOperands ( I , TII , TRI , RBI ) ; } Register Src0Reg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register Src1Reg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( HasCarryIn ) { BuildMI ( * BB , & I , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( I . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; } unsigned NoCarryOpc = IsAdd ? <STR_LIT> : <STR_LIT> ; unsigned CarryOpc = IsAdd ? <STR_LIT> : <STR_LIT> ; BuildMI ( * BB , & I , DL , TII . get ( HasCarryIn ? CarryOpc : NoCarryOpc ) , Dst0Reg ) . add ( I . getOperand ( <NUM_LIT> ) ) . add ( I . getOperand ( <NUM_LIT> ) ) ; BuildMI ( * BB , & I , DL , TII . get ( <STR_LIT> ) , Dst1Reg ) . addReg ( <STR_LIT> ) ; if ( ! MRI -> getRegClassOrNull ( Dst1Reg ) ) MRI -> setRegClass ( Dst1Reg , & <STR_LIT> ) ; if ( ! RBI . constrainGenericRegister ( Dst0Reg , <STR_LIT> , * MRI ) || ! RBI . constrainGenericRegister ( Src0Reg , <STR_LIT> , *

MRI ) || ! RBI . constrainGenericRegister ( Src1Reg , <STR_LIT> , * MRI ) ) return false ;


<s> return ( Imm . Val <= <NUM_LIT> && Imm . Val >= - <NUM_LIT> ) || ( F == <NUM_LIT> || F == <NUM_LIT> || F == - <NUM_LIT> || F == <NUM_LIT>


<s> static std :: unique_ptr < <ISA_LIT>Operand >


<s> return ( __m512d ) __builtin_ia32_rndscalepd_mask ( ( __v8df ) __B , __imm , ( __v8df ) _mm512_setzero_pd ( ) , (


<s> __builtin_aarch64_simd_ci __o ; __o = __builtin_aarch64_ld3v2df ( ( const __builtin_aarch64_simd_df * ) __a ) ; ret . val [ <NUM_LIT> ] = ( float64x2_t ) __builtin_aarch64_get_qregciv2df ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( float64x2_t ) __builtin_aarch64_get_qregciv2df ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( float64x2_t ) __builtin_aarch64_get_qregciv2df ( __o , <NUM_LIT> ) ; return


<s> bool <ISA_LIT>TargetMachine :: symbolicAddressesAreRIPRel ( ) const { return getRelocationModel ( ) != Reloc :: Static


<s> } MVT ContainerVT = getContainerForFixedLengthVector ( VecVT ) ; MVT I1ContainerVT = <STR_LIT> ( <STR_LIT> , ContainerVT . getVectorElementCount ( ) ) ; SDValue CC = convertToScalableVector ( I1ContainerVT , Src , DAG , Subtarget ) ; SDValue Mask , VL ; std :: tie ( Mask , VL ) = getDefaultVLOps ( VecVT , ContainerVT , DL , DAG , Subtarget ) ; MVT XLenVT = Subtarget . getXLenVT ( ) ; SDValue SplatZero = DAG . getConstant ( <NUM_LIT> , DL , XLenVT ) ; SDValue SplatTrueVal = DAG . getConstant ( ExtTrueVal , DL , XLenVT ) ; SplatZero = DAG . getNode ( <STR_LIT> , DL , ContainerVT ,

DAG . getUNDEF ( ContainerVT ) , SplatZero , VL ) ;


<s> MachineBasicBlock * MBB = MI -> getParent ( ) ; if ( ! MFI -> isLRSpilled ( ) ) report_fatal_error ( <STR_LIT> ) ; Br . MaxDisp = ( ( <NUM_LIT> << ( <NUM_LIT> - <NUM_LIT> ) ) - <NUM_LIT> ) * <NUM_LIT> ; MI -> setDesc ( TII -> get ( <STR_LIT> ) ) ; BBInfo [ MBB -> getNumber ( ) ] . Size += <NUM_LIT> ; adjustBBOffsetsAfter ( MBB ) ; ++ NumUBrFixed ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> <<


<s> char ctrStr [ <NUM_LIT> ] = { '\0' } ; std :: string Name = <STR_LIT> ; Name += Prefix ; sprintf ( ctrStr , <STR_LIT> , ctr ++ ) ; Name +=


<s> <STR_LIT> SLT = LT . second . getScalarType ( ) . SimpleTy ; switch ( ISD ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( SLT == <STR_LIT> ) return get64BitInstrCost ( ) * LT . first * NElts ; return getFullRateInstrCost ( ) * LT . first * NElts ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( SLT == <STR_LIT> ) { return <NUM_LIT> * getFullRateInstrCost ( ) * LT . first * NElts ; } return LT . first * NElts * getFullRateInstrCost ( ) ; case <STR_LIT> : { const int QuarterRateCost = getQuarterRateInstrCost ( ) ; if ( SLT == <STR_LIT> ) { const int FullRateCost = getFullRateInstrCost ( ) ; return ( <NUM_LIT> * QuarterRateCost + ( <NUM_LIT> * <NUM_LIT> ) * FullRateCost ) * LT . first * NElts ; } return QuarterRateCost * NElts * LT . first ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( SLT == <STR_LIT> ) return LT . first * NElts * get64BitInstrCost ( ) ; if ( SLT == <STR_LIT> || SLT == <STR_LIT> ) return LT . first * NElts * getFullRateInstrCost ( ) ; break ; case <STR_LIT> : case <STR_LIT> : if ( SLT == <STR_LIT> ) { int Cost = <NUM_LIT> * get64BitInstrCost ( ) + <NUM_LIT> * getQuarterRateInstrCost ( ) ; if ( ! ST -> hasUsableDivScaleConditionOutput ( ) ) Cost += <NUM_LIT> * getFullRateInstrCost ( ) ; return LT . first * Cost * NElts ; } if ( ! Args . empty ( ) && match ( Args [ <NUM_LIT> ] , PatternMatch :: m_FPOne ( ) ) ) { if ( ( SLT == <STR_LIT> && ! HasFP32Denormals ) || ( SLT == <STR_LIT> && ST -> has16BitInsts ( ) ) ) { return LT . first * getQuarterRateInstrCost ( ) * NElts ; } } if ( SLT == <STR_LIT> && ST -> has16BitInsts ( ) ) { int Cost = <NUM_LIT> * getFullRateInstrCost ( ) + <NUM_LIT> * getQuarterRateInstrCost ( ) ; return LT . first * Cost * NElts ; } if ( SLT == <STR_LIT> || SLT == <STR_LIT> ) { int Cost = <NUM_LIT> * getFullRateInstrCost ( ) + <NUM_LIT> * getQuarterRateInstrCost ( ) ; if ( ! HasFP32Denormals ) { Cost += <NUM_LIT> * getFullRateInstrCost ( ) ; } return LT . first


<s> MachineBasicBlock * <ISA_LIT>SETargetLowering :: emitFILL_FD ( MachineInstr * MI , MachineBasicBlock * BB ) const { return


<s> RegisterAsmLexer < ThumbAsmLexer > Y (


<s> } unsigned Register = GPRDecoderTable [ RegNo ] ; Inst . addOperand ( MCOperand :: createReg ( Register ) ) ; if ( RegNo == <NUM_LIT> )


<s> assert ( isRegIdx ( ) && ( RegIdx . Kind & RegKind_ACC ) && <STR_LIT> ) ; unsigned ClassID =


<s> unsigned int n_insns = <NUM_LIT> ; if ( align > ( TARGET_64BIT ? <NUM_LIT> : <NUM_LIT> ) ) align = ( TARGET_64BIT ? <NUM_LIT> : <NUM_LIT> ) ; n_insns = <NUM_LIT> ; if ( n_bytes % ( <NUM_LIT> * align ) != <NUM_LIT> ) { if ( ( n_bytes % ( <NUM_LIT> * align ) ) >= align ) n_insns += <NUM_LIT> ; if ( ( n_bytes % align ) != <NUM_LIT> ) n_insns += <NUM_LIT> ; } return n_insns * <NUM_LIT>


<s> return Operand . isIdxen ( ) ? Match_Success : Match_InvalidOperand ; case MCK_offen : return Operand . isOffen ( ) ? Match_Success : Match_InvalidOperand ; case MCK_SSrcB32 : return Operand . isSSrcB32 ( ) ? Match_Success : Match_InvalidOperand ; case MCK_SSrcF32 : return Operand . isSSrcF32 ( ) ? Match_Success : Match_InvalidOperand ; case MCK_SoppBrTarget : return Operand . isSoppBrTarget ( ) ? Match_Success : Match_InvalidOperand ; case MCK_VReg32OrOff : return Operand . isVReg32OrOff ( ) ? Match_Success : Match_InvalidOperand ; case MCK_InterpSlot : return Operand . isInterpSlot ( ) ? Match_Success : Match_InvalidOperand ; case MCK_Attr : return Operand . isInterpAttr ( ) ? Match_Success : Match_InvalidOperand ; case MCK_AttrChan : return Operand . isAttrChan ( ) ? Match_Success : Match_InvalidOperand ; case MCK_ImmSMEMOffset : return Operand . isSMEMOffset ( ) ? Match_Success : Match_InvalidOperand ; case MCK_SReg_64 : case MCK_SReg_64_XEXEC : return Operand . isNull ( )


<s> uint32_t Value = <NUM_LIT> ; if ( OddSPReg ) Value |= ( uint32_t ) AFL_FLAGS1_ODDSPREG ; return Value


<s> if ( ! Flags . isSRet ( ) ) return NotStructReturn ; if ( Flags . isInReg ( ) ) return RegStructReturn ; return


<s> SDLoc DL ( Op ) ; assert ( V1 . getSimpleValueType ( ) == <STR_LIT> && <STR_LIT> ) ; assert ( V2 . getSimpleValueType ( ) == <STR_LIT> && <STR_LIT> ) ; ShuffleVectorSDNode * SVOp = cast < ShuffleVectorSDNode > ( Op ) ; ArrayRef < int > Mask = SVOp -> getMask ( ) ; assert ( Mask . size ( ) == <NUM_LIT> && <STR_LIT> ) ; assert ( Subtarget -> hasBWI ( ) &&


<s> void printHex32ImmOperand ( const MachineInstr * MI , int OpNum , raw_ostream &


<s> static bool mips_pass_by_reference ( cumulative_args_t cum ATTRIBUTE_UNUSED , machine_mode mode , const_tree type , bool named ATTRIBUTE_UNUSED ) { if ( mips_abi == ABI_EABI ) { int size ; if ( mode == DImode || mode == DFmode || mode == DQmode || mode == UDQmode || mode == DAmode || mode == UDAmode ) return <NUM_LIT> ; size = type ? int_size_in_bytes ( type ) : GET_MODE_SIZE ( mode ) ; return size == - <NUM_LIT> || size > UNITS_PER_WORD ; } else { return targetm . calls . must_pass_in_stack ( mode ,


<s> return GET_CODE ( op ) == CONST || GET_CODE ( op ) == SYMBOL_REF ||


<s> if ( ! isValidMsgOp ( Msg . Id , Op . Id , getSTI ( ) , Strict ) ) { Error ( Op . Loc , <STR_LIT> ) ; return false ; } if ( Strict && ! msgSupportsStream ( Msg . Id , Op . Id ) && Stream . IsDefined ) { Error ( Stream . Loc , <STR_LIT> ) ; return false ; } if ( ! isValidMsgStream ( Msg . Id , Op . Id , Stream . Id , getSTI ( ) , Strict ) ) { Error ( Stream . Loc , <STR_LIT> ) ; return false ; } return


<s> Regs . push_back ( Reg ) ; } if ( Regs . empty ( ) ) continue ; if ( Regs . size ( ) > <NUM_LIT> || LdrOpc == <NUM_LIT> ) { MachineInstrBuilder MIB = AddDefaultPred ( BuildMI ( MBB , MI , DL , TII . get ( LdmOpc ) , <STR_LIT> ) . addReg ( <STR_LIT> ) ) ; for ( unsigned i = <NUM_LIT> , e = Regs . size ( ) ; i < e ; ++ i ) MIB . addReg ( Regs [ i ] , getDefRegState ( true ) ) ; if ( DeleteRet ) { MIB -> copyImplicitOps ( & * MI ) ; MI -> eraseFromParent ( ) ; } MI = MIB ; } else if ( Regs . size ( ) == <NUM_LIT> ) { if ( Regs [ <NUM_LIT> ] == <STR_LIT> ) Regs [ <NUM_LIT> ] = <STR_LIT> ; MachineInstrBuilder MIB = BuildMI ( MBB , MI , DL , TII . get ( LdrOpc ) , Regs [ <NUM_LIT> ] ) . addReg ( <STR_LIT> , RegState :: Define ) . addReg ( <STR_LIT> ) ; if ( LdrOpc == <STR_LIT> || LdrOpc == <STR_LIT> ) { MIB . addReg ( <NUM_LIT>


<s> insertCall ( Op1 ) ; return true ; } default : break ; } errs ( ) << <STR_LIT> + utostr ( Opcode ) <<


<s> SrcVT = DstVT = <STR_LIT> ; return true ; } } if ( MaskVT . is256BitVector ( ) && AllowFloatDomain ) { assert ( Subtarget . hasAVX ( ) && <STR_LIT> ) ; if ( isTargetShuffleEquivalent ( Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) { Shuffle = <STR_LIT> ; SrcVT = DstVT = <STR_LIT> ; return true ; } if ( isTargetShuffleEquivalent ( Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) { Shuffle = <STR_LIT> ; SrcVT = DstVT = <STR_LIT> ; return true ; } if ( isTargetShuffleEquivalent ( Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) { Shuffle = <STR_LIT> ; SrcVT = DstVT = <STR_LIT> ; return true ; } } if ( MaskVT . is512BitVector ( ) && AllowFloatDomain ) { assert ( Subtarget . hasAVX512 ( ) && <STR_LIT> ) ; if ( isTargetShuffleEquivalent ( Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) { Shuffle = <STR_LIT> ; SrcVT = DstVT = <STR_LIT> ; return true ; } if ( isTargetShuffleEquivalent ( Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) { Shuffle = <STR_LIT> ; SrcVT = DstVT = <STR_LIT> ; return true ; } if ( isTargetShuffleEquivalent ( Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> ,


<s> void <ISA_LIT>InstrInfo :: copyPhysReg ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI , const DebugLoc & DL , unsigned DestReg , unsigned SrcReg , bool KillSrc ) const { if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) { copyPhysReg ( MBB , MBBI , DL , RI . getSubReg ( DestReg , <STR_LIT> ) , RI . getSubReg ( SrcReg , <STR_LIT> ) , KillSrc ) ; MachineInstrBuilder ( * MBB . getParent ( ) , std :: prev ( MBBI ) ) . addReg ( SrcReg , RegState :: Implicit ) ; copyPhysReg ( MBB , MBBI , DL , RI . getSubReg ( DestReg , <STR_LIT> ) , RI . getSubReg ( SrcReg , <STR_LIT> ) , KillSrc ) ; MachineInstrBuilder ( * MBB . getParent ( ) , std :: prev ( MBBI ) ) . addReg ( SrcReg , ( getKillRegState ( KillSrc ) | RegState :: Implicit ) ) ; return ; } if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) { emitGRX32Move ( MBB , MBBI , DL , DestReg , SrcReg , <STR_LIT> , <NUM_LIT> , KillSrc , false ) ; return ; } if ( <STR_LIT> . contains ( DestReg ) && <STR_LIT> . contains ( SrcReg ) ) { unsigned SrcRegHi = RI . getMatchingSuperReg ( RI . getSubReg ( SrcReg , <STR_LIT> ) , <STR_LIT> , & <STR_LIT> ) ; unsigned SrcRegLo = RI . getMatchingSuperReg ( RI . getSubReg ( SrcReg , <STR_LIT> ) , <STR_LIT> ,


<s> const struct mips_cpu_info * p ; const char * s ; for ( s = cpu_string ; * s != <NUM_LIT> ; s ++ ) if ( ISUPPER ( * s ) ) { warning ( <NUM_LIT> , <STR_LIT> )


<s> static bool CC_<ISA_LIT> ( unsigned ValNo , MVT ValVT , CCValAssign :: LocInfo LocInfo , CCState & State ) { Register Reg = State . AllocateReg ( ArgGPRs ) ; if ( Reg


<s> assert ( CI . I -> hasOneMemOperand ( ) && Paired . I -> hasOneMemOperand ( ) ) ; const MachineMemOperand * MMOa = * CI . I -> memoperands_begin ( ) ; const MachineMemOperand * MMOb = * Paired . I -> memoperands_begin ( ) ; MachineInstr * New = MIB . add ( * TII -> getNamedOperand ( * CI . I , <STR_LIT> :: srsrc ) ) . add ( * TII -> getNamedOperand ( * CI . I , <STR_LIT> :: soffset ) ) . addImm ( MergedOffset ) . addImm ( CI . GLC ) . addImm ( CI . SLC ) . addImm ( <NUM_LIT> ) . addImm ( CI . DLC ) . addImm ( <NUM_LIT> ) . addMemOperand ( combineKnownAdjacentMMOs ( * MBB -> getParent ( ) , MMOa , MMOb ) ) ; std :: pair < unsigned , unsigned > SubRegIdx = getSubRegIdxs ( CI , Paired ) ; const unsigned SubRegIdx0 = std :: get < <NUM_LIT> > ( SubRegIdx ) ; const unsigned SubRegIdx1 = std :: get < <NUM_LIT> > ( SubRegIdx ) ; const MCInstrDesc & CopyDesc = TII -> get ( TargetOpcode :: COPY ) ; const auto * Dest0 = TII -> getNamedOperand ( * CI . I , <STR_LIT> :: vdata ) ; const auto * Dest1 = TII -> getNamedOperand ( * Paired . I , <STR_LIT> :: vdata ) ; BuildMI ( * MBB , Paired . I , DL , CopyDesc ) . add ( * Dest0 ) . addReg ( DestReg , <NUM_LIT> , SubRegIdx0 ) ; MachineInstr * Copy1 = BuildMI ( * MBB , Paired . I , DL , CopyDesc ) . add ( * Dest1 ) . addReg ( DestReg , RegState :: Kill , SubRegIdx1 ) ; moveInstsAfter ( Copy1 , CI . InstsToMove


<s> static bool isV8M ( const <ISA_LIT>Subtarget * Subtarget ) { return ( Subtarget -> hasV8MBaselineOps ( ) && ! Subtarget -> hasV6T2Ops ( ) )


<s> bool <ISA_LIT>PassConfig :: addInstSelector ( ) { addPass ( create<ISA_LIT>ISelDag ( get<ISA_LIT>TargetMachine ( ) , getOptLevel (


<s> valist = build_simple_mem_ref ( valist ) ; args = build3 ( COMPONENT_REF , TREE_TYPE ( f_args ) , valist , f_args , NULL_TREE ) ; skip = build3 ( COMPONENT_REF , TREE_TYPE ( f_skip ) , valist , f_skip , NULL_TREE ) ; t = make_tree ( TREE_TYPE ( args ) , nextarg ) ; if ( crtl -> args . pretend_args_size > <NUM_LIT> ) t = fold_build_pointer_plus_hwi ( t , - STACK_POINTER_OFFSET ) ; t = build2 ( MODIFY_EXPR , TREE_TYPE ( args ) , args , t ) ; TREE_SIDE_EFFECTS ( t ) = <NUM_LIT> ; expand_expr ( t , const0_rtx , VOIDmode , EXPAND_NORMAL ) ; t = make_tree ( TREE_TYPE ( skip ) , virtual_incoming_args_rtx ) ; t = fold_build_pointer_plus_hwi ( t , ( crtl -> args . pretend_args_size - STACK_POINTER_OFFSET ) ) ; t = build2 ( MODIFY_EXPR , TREE_TYPE ( skip ) , skip ,


<s> } x ; x . q = q ; return ( x . l [ <NUM_LIT>


<s> O << <STR_LIT> ; printLeaMemReference ( MI , OpNo


<s> bool targetSchedulesPostRAScheduling ( ) const override { return


<s> MCSection * <ISA_LIT>ELFTargetObjectFile :: getSectionForConstant ( const DataLayout & DL , SectionKind Kind , const Constant * C , unsigned & Align ) const { if ( isConstantInSmallSection ( DL , C


<s> O << <ISA_LIT>mm ; return ; } if ( Imm == DoubleToBits ( <NUM_LIT> ) ) O << <STR_LIT> ; else if ( Imm == DoubleToBits ( <NUM_LIT> ) ) O << <STR_LIT> ; else if ( Imm == DoubleToBits ( - <NUM_LIT> ) ) O << <STR_LIT> ; else if ( Imm == DoubleToBits ( <NUM_LIT> ) ) O << <STR_LIT> ; else if ( Imm == DoubleToBits ( - <NUM_LIT> ) ) O << <STR_LIT> ; else if ( Imm == DoubleToBits ( <NUM_LIT> ) ) O << <STR_LIT> ; else if ( Imm == DoubleToBits (


<s> bool isMovWSymbol ( ArrayRef < <ISA_LIT>MCExpr :: VariantKind > AllowedModifiers ) const { if ( ! isImm ( ) ) return false ; <ISA_LIT>MCExpr :: VariantKind ELFRefKind ; MCSymbolRefExpr :: VariantKind DarwinRefKind ; int64_t Addend ; if ( ! <ISA_LIT>AsmParser :: classifySymbolRef ( getImm ( ) , ELFRefKind , DarwinRefKind , Addend ) ) { return false ; } if ( DarwinRefKind != MCSymbolRefExpr :: VK_None ) return false ; for ( unsigned i = <NUM_LIT> ; i != AllowedModifiers . size ( ) ; ++ i ) { if ( ELFRefKind == AllowedModifiers [ i ] ) return Addend ==


<s> <ISA_LIT>RI5CYIR ( ) : FunctionPass ( ID


<s> return ; case <STR_LIT> : SelectAdd ( N ) ; return ; case <STR_LIT> : SelectBitcast ( N ) ; return ; case <STR_LIT> : SelectSHL ( N ) ; return ; case <STR_LIT> : SelectLoad ( N ) ; return ; case <STR_LIT> : SelectStore ( N ) ; return ; case <STR_LIT> : SelectMul ( N ) ; return ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : SelectBitOp ( N ) ; return ; case <STR_LIT> : SelectZeroExtend ( N ) ; return ; case <STR_LIT> : SelectIntrinsicWChain ( N ) ; return ; case


<s> bool KillsOp0 = MI -> killsRegister ( <STR_LIT> + Op0 ) ; bool KillsOp1 = MI -> killsRegister ( <STR_LIT> + Op1 ) ; moveToTop ( Op0 , I ) ; MI -> getOperand ( <NUM_LIT> ) . setReg ( getSTReg ( Op1 ) ) ; MI -> RemoveOperand ( <NUM_LIT> ) ; MI -> setDesc ( TII -> get ( getConcreteOpcode ( MI -> getOpcode ( ) ) ) ) ; if ( KillsOp0 ) freeStackSlotAfter ( I


<s> <ISA_LIT>Z80SectionData Data ( N , T , A , B , Align , GO ) ; if ( Sections . count ( Data ) ) return Sections [ Data ] ; MCSection<ISA_LIT>Z80 * Section = new MCSection<ISA_LIT>Z80 (


<s> BuildMI ( * MBB , CI . Paired , DL , TII -> get ( Opcode ) , DestReg ) . add ( * TII -> getNamedOperand ( * CI . I , <STR_LIT> :: sbase ) ) . addImm ( MergedOffset ) . addImm ( CI . GLC0 ) . addImm ( CI . DLC0 ) . cloneMergedMemRefs ( { & * CI . I , & * CI . Paired } ) ; std :: pair < unsigned , unsigned > SubRegIdx = getSubRegIdxs ( CI ) ; const unsigned SubRegIdx0 = std :: get < <NUM_LIT> > ( SubRegIdx ) ; const unsigned SubRegIdx1 = std :: get < <NUM_LIT> > ( SubRegIdx ) ; const MCInstrDesc & CopyDesc = TII -> get ( TargetOpcode :: COPY ) ; const auto * Dest0 = TII -> getNamedOperand ( * CI . I , <STR_LIT> :: sdst ) ; const auto * Dest1 = TII -> getNamedOperand ( * CI . Paired , <STR_LIT> :: sdst


<s> Amount = ( Amount + Align - <NUM_LIT> ) / Align * Align ; <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; assert ( ! AFI -> isThumb1OnlyFunction ( ) && <STR_LIT> ) ; bool is<ISA_LIT> = ! AFI -> isThumbFunction ( ) ; unsigned Opc = Old -> getOpcode ( ) ; int PIdx = Old -> findFirstPredOperandIdx ( ) ; <STR_LIT> Pred = ( PIdx == - <NUM_LIT> ) ? <STR_LIT> : ( <STR_LIT> ) Old -> getOperand ( PIdx ) . getImm ( ) ; if ( Opc == <STR_LIT> || Opc == <STR_LIT> ) { unsigned PredReg = Old -> getOperand ( <NUM_LIT> ) . getReg ( ) ; emitSPUpdate ( is<ISA_LIT> , MBB , I , dl , TII , - Amount , Pred , PredReg ) ; }


<s> MachineFunction & MF = DAG . getMachineFunction ( ) ; <ISA_LIT>FunctionInfo * XFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; SDValue Addr = DAG . getFrameIndex ( XFI -> getVarArgsFrameIndex (


<s> static DecodeStatus DecodeSImmWithOffsetAndScale ( MCInst & Inst , unsigned Value , uint64_t Address , const void * Decoder ) { int32_t Imm = SignExtend32 < Bits > ( Value ) * ScaleBy ; Inst . addOperand ( MCOperand :: createImm ( Imm + Offset ) ) ; return MCDisassembler ::


<s> if ( MRI -> def_begin ( Reg ) == MRI -> def_end ( ) ) { DEBUG ( dbgs ( ) << <STR_LIT> << PrintReg ( Reg , MRI -> getTargetRegisterInfo ( ) ) << <STR_LIT> ) ; } else if ( ! MRI -> hasOneDef ( Reg ) ) { DEBUG ( dbgs ( ) << <STR_LIT> << PrintReg ( Reg , MRI -> getTargetRegisterInfo ( ) ) << <STR_LIT> ) ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; for ( auto DI = MRI -> def_begin ( Reg ) , DE = MRI -> def_end ( ) ; DI != DE


<s> else return <STR_LIT> ; } else { if ( TARGET_68020 ) { switch ( flag_pic ) { case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; default : return <STR_LIT> ; } } } gcc_unreachable ( ) ; case RELOC_TLSGD : return <STR_LIT> ; case RELOC_TLSLDM : return <STR_LIT> ; case RELOC_TLSLDO : return <STR_LIT> ; case RELOC_TLSIE


<s> case E_V8HImode : case E_V4SFmode : case E_V4SImode : case E_V2DFmode : case E_V2DImode : case E_V1TImode : case E_TImode : case E_TFmode : case E_KFmode : if ( VECTOR_MEM_ALTIVEC_OR_VSX_P ( mode ) ) return


<s> static std :: pair < OutputIt1 , OutputIt2 > copy_if_else ( InputIt First , InputIt

Last , OutputIt1 d1 , OutputIt2 d2 , UnaryPredicate Predicate ) {


<s> if ( ca -> start_reg >= CA_FIRST_REG ) for ( i = <NUM_LIT> ; i < ca -> reg_count ; i ++ ) ca -> reg_used [ i + ca -> start_reg - CA_FIRST_REG ] = <NUM_LIT> ; ca -> special_p =


<s> MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const <ISA_LIT>RegisterInfo * RI = STI . getRegisterInfo ( ) ; uint64_t FrameSize = MFI . getStackSize ( ) ; uint64_t StackAlign = RI -> needsStackRealignment ( MF ) ? MFI . getMaxAlignment ( ) : getStackAlignment ( ) ; FrameSize = alignTo ( FrameSize , StackAlign


<s> const <ISA_LIT>InstrInfo * getInstrInfo ( ) const override { return getSubtargetImpl ( ) ->


<s> break ; } for ( unsigned i = SIndex + <NUM_LIT> , e = MemOps . size ( ) ; i != e ; ++ i ) { int NewOffset = MemOps [ i ] . Offset ; const MachineOperand & MO = MemOps [ i ] . MBBI -> getOperand ( <NUM_LIT> ) ; unsigned Reg = MO . getReg ( ) ; unsigned RegNum = MO . isUndef ( ) ? UINT_MAX : TRI -> getEncodingValue ( Reg ) ; if ( Reg != <STR_LIT> && NewOffset == Offset + ( int ) Size && ( ( isNotVFP && RegNum > PRegNum ) || ( ( Count < Limit ) && RegNum == PRegNum + <NUM_LIT> ) ) && ( ! STI -> isSwift ( ) || isNotVFP || Count != <NUM_LIT> || ! ( PRegNum & <NUM_LIT> ) ) ) { Offset += Size ; PRegNum = RegNum ; ++ Count ; } else { MergeOpsUpdate ( MBB , MemOps , SIndex , i , insertAfter , SOffset , Base , false , Opcode , Pred , PredReg , Scratch , dl , Merges ) ; MergeLDR_STR ( MBB , i , Base , Opcode , Size , Pred , PredReg , Scratch , MemOps , Merges ) ; return ; } if ( MemOps [ i ] . Position > MemOps [ insertAfter ]


<s> icode = cc_mode == CCFPEmode ? CODE_FOR_fcmpedf : CODE_FOR_fcmpdf ; break ; default : end_sequence ( ) ; return NULL_RTX ; } op0 = prepare_operand ( icode , op0 , <NUM_LIT> , op_mode , cmp_mode , unsignedp ) ; op1 = prepare_operand ( icode , op1 , <NUM_LIT> , op_mode , cmp_mode , unsignedp ) ; if ( ! op0 || ! op1 ) { end_sequence ( ) ; return NULL_RTX ; } * prep_seq = get_insns ( ) ; end_sequence ( ) ; create_fixed_operand ( & ops [ <NUM_LIT> ] , op0 ) ; create_fixed_operand ( & ops [ <NUM_LIT> ] , op1 ) ; start_sequence ( ) ; if ( ! maybe_expand_insn ( icode , <NUM_LIT> , ops ) ) { end_sequence ( ) ; return


<s> ShufIdxs [ <NUM_LIT> ] = <NUM_LIT> ; ShufIdxs [ <NUM_LIT> ] = <NUM_LIT> ; ShufIdxs [ <NUM_LIT> ] = <NUM_LIT> ; ShufIdxs [ <NUM_LIT> ] = <NUM_LIT> ; ShufIdxs [ <NUM_LIT> ] = <NUM_LIT> ; ShufIdxs [ <NUM_LIT> ] = <NUM_LIT> ; ShufIdxs [ <NUM_LIT> ] = <NUM_LIT> ; ShufIdxs [ <NUM_LIT> ] = <NUM_LIT> ; ShufIdxs [ <NUM_LIT> ] = <NUM_LIT> ; ShufIdxs [ <NUM_LIT> ] = <NUM_LIT> ; ShufIdxs [ <NUM_LIT> ] = <NUM_LIT> ; ShufIdxs [ <NUM_LIT> ] = <NUM_LIT> ; break ; case OP_VSPLTISW0 : for ( unsigned i = <NUM_LIT> ; i != <NUM_LIT> ; ++ i ) ShufIdxs [ i ] = ( i & <NUM_LIT> ) + <NUM_LIT> ; break ; case OP_VSPLTISW1 : for ( unsigned i = <NUM_LIT> ; i != <NUM_LIT> ; ++ i ) ShufIdxs [ i ] = ( i & <NUM_LIT> ) + <NUM_LIT> ; break ; case OP_VSPLTISW2 : for ( unsigned i = <NUM_LIT> ; i != <NUM_LIT> ; ++ i ) ShufIdxs [ i ] = ( i & <NUM_LIT> ) + <NUM_LIT> ; break ; case OP_VSPLTISW3 : for ( unsigned i = <NUM_LIT> ; i != <NUM_LIT> ; ++ i ) ShufIdxs [ i ] = ( i & <NUM_LIT> ) + <NUM_LIT> ; break ; case OP_VSLDOI4 : return BuildVSLDOI ( OpLHS , OpRHS , <NUM_LIT> , OpLHS . getValueType ( )


<s> return ( __m64 ) __builtin_arm_wcmpeqb ( ( __v8qi ) __m1 , (


<s> if ( ! checkOneUse ( M1 ) ) return false ; return matchShiftAmt ( M1 ) ; } ; SDValue X ; auto matchPatternD = [ & checkOneUse , & checkTwoUse , matchShiftAmt , & X ] ( SDNode * Node ) -> bool { if ( Node -> getOpcode ( ) != <STR_LIT> ) return false ; SDValue N0 = Node -> getOperand ( <NUM_LIT> ) ; if ( N0 -> getOpcode ( ) != <STR_LIT> || ! checkOneUse ( N0 ) ) return false ; SDValue N1 = Node -> getOperand ( <NUM_LIT> ) ; SDValue N01 = N0 -> getOperand ( <NUM_LIT> ) ; if ( N1 != N01 || ! checkTwoUse ( N1 ) ) return false ; if ( ! matchShiftAmt ( N1 ) ) return false ; X = N0 -> getOperand ( <NUM_LIT> ) ; return true ; } ; auto matchLowBitMask = [ & matchPatternA , & matchPatternB , & matchPatternC ] ( SDValue Mask ) -> bool { return matchPatternA ( Mask ) || matchPatternB ( Mask ) || matchPatternC ( Mask ) ; } ; if ( Node -> getOpcode ( ) == <STR_LIT> ) { X = Node -> getOperand ( <NUM_LIT> ) ; SDValue Mask = Node -> getOperand ( <NUM_LIT> ) ; if ( matchLowBitMask ( Mask ) ) { } else { std :: swap ( X , Mask ) ; if ( ! matchLowBitMask ( Mask ) ) return false ; } } else if ( ! matchPatternD ( Node ) ) return false ; SDLoc DL ( Node ) ; SDValue OrigNBits = NBits ; if ( NBits . getValueType ( ) != NVT ) { NBits = CurDAG -> getNode ( <STR_LIT> , DL , <STR_LIT> , NBits ) ; insertDAGNode ( * CurDAG , OrigNBits , NBits ) ; SDValue ImplDef = SDValue ( CurDAG -> getMachineNode ( TargetOpcode :: IMPLICIT_DEF ,


<s> rtx xx = XEXP ( plus , <NUM_LIT> ) ; int regno = REGNO ( xx ) ; ok = ( regno >= FIRST_PSEUDO_REGISTER || regno == REG_Z || regno == REG_Y || xx == frame_pointer_rtx || xx == arg_pointer_rtx ) ; if ( avr_log . constraints ) avr_edump ( <STR_LIT> , ok , reload_completed , reload_in_progress , x ) ; } return ok


<s> unsigned Idx = State . getFirstUnallocated ( ArgRegs ) ; unsigned RegSizeInBytes = Subtarget . getGPRSizeInBytes ( ) ; MVT RegTy = <STR_LIT> ( RegSizeInBytes * <NUM_LIT> ) ; const TargetRegisterClass * RC = getRegClassFor ( RegTy ) ; MachineFunction & MF = DAG . getMachineFunction ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; <ISA_LIT>FunctionInfo * <ISA_LIT>FI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; int VaArgOffset ; if ( ArgRegs . size ( ) == Idx ) VaArgOffset = alignTo ( State . getNextStackOffset ( ) , RegSizeInBytes ) ; else { VaArgOffset = ( int ) ABI . GetCalleeAllocdArgSizeInBytes ( State . getCallingConv ( ) ) - ( int ) ( RegSizeInBytes * ( ArgRegs .


<s> } LiveMask |= ( <NUM_LIT> << getFPReg ( Op ) ) ; MI . RemoveOperand ( i ) ; -- i ; -- e ; } adjustLiveRegs ( LiveMask , MI ) ; if ( ! LiveMask ) return ; if ( SecondFPRegOp == ~ <NUM_LIT> ) { assert ( StackTop == <NUM_LIT> && FirstFPRegOp == getStackEntry ( <NUM_LIT> ) && <STR_LIT> ) ; StackTop = <NUM_LIT> ; return ; } if ( StackTop == <NUM_LIT> ) { assert ( FirstFPRegOp == SecondFPRegOp && FirstFPRegOp == getStackEntry ( <NUM_LIT> ) && <STR_LIT> ) ; unsigned NewReg = ScratchFPReg ; duplicateToTop ( FirstFPRegOp , NewReg , MI ) ; FirstFPRegOp = NewReg ; } assert ( StackTop == <NUM_LIT> && <STR_LIT> ) ; if ( getStackEntry ( <NUM_LIT> ) == SecondFPRegOp ) { assert ( getStackEntry ( <NUM_LIT> ) == FirstFPRegOp && <STR_LIT> ) ; moveToTop ( FirstFPRegOp , MI ) ; } assert ( getStackEntry ( <NUM_LIT> ) == FirstFPRegOp && <STR_LIT> ) ; assert ( getStackEntry ( <NUM_LIT> ) == SecondFPRegOp && <STR_LIT>


<s> Target & T = The<ISA_LIT>Target ; RegisterMCAsmInfoFn X ( T , create<ISA_LIT>MCAsmInfo ) ; TargetRegistry :: RegisterMCInstrInfo ( T , create<ISA_LIT>MCInstrInfo ) ; TargetRegistry :: RegisterMCRegInfo ( T , create<ISA_LIT>MCRegisterInfo ) ; TargetRegistry :: RegisterMCSubtargetInfo ( T ,


<s> if ( ! MCID ) { return ; } ScoreboardHazardRecognizer :: EmitInstruction ( SU


<s> Op0 = DAG . getNode ( Extend , DL , <STR_LIT> , Op0 ) ; Op1 = DAG . getNode ( Extend , DL , <STR_LIT> , Op1 ) ; SDValue Mul = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op0 , Op1 ) ; Hi = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Mul , DAG .

getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ;


& heap_region , HSA_REGION_GLOBAL_FLAG_COARSE_GRAINED ) ;


<s> AU . addPreservedID ( LiveVariablesID ) ; AU . addPreservedID ( MachineLoopInfoID ) ; AU . addPreservedID ( MachineDominatorsID ) ; AU . setPreservesCFG ( ) ; MachineFunctionPass :: getAnalysisUsage (


<s> LLT S32 = LLT :: scalar ( <NUM_LIT> ) ; auto LHSExt = B . buildFPExt ( S32 , LHS , Flags ) ; auto RHSExt = B . buildFPExt ( S32 , RHS , Flags ) ; auto RCP = B . buildIntrinsic ( <STR_LIT> , { S32 } , false ) . addUse ( RHSExt . getReg ( <NUM_LIT> ) ) . setMIFlags ( Flags ) ; auto QUOT = B . buildFMul ( S32 ,


<s> if ( ( from == FLOAT_REGS ) == ( to == FLOAT_REGS ) ) return <NUM_LIT> ; if ( TARGET_FIX ) return ( from


<s> output_asm_insn ( <STR_LIT> , & stub_label ) ; } else output_asm_insn ( <STR_LIT> , & addr ) ; return


<s> unsigned regno = aarch64_get_next_set_bit ( components , R0_REGNUM ) ; rtx_insn * insn = NULL ; while ( regno != last_regno ) { machine_mode mode = GP_REGNUM_P ( regno ) ? E_DImode : E_DFmode ; rtx reg = gen_rtx_REG ( mode , regno ) ; poly_int64 offset = cfun -> machine -> frame . reg_offset [ regno ] ; if ( ! frame_pointer_needed ) offset += cfun -> machine -> frame . frame_size - cfun -> machine -> frame . hard_fp_offset ; rtx addr = plus_constant ( Pmode , ptr_reg , offset ) ; rtx mem = gen_frame_mem ( mode , addr ) ; rtx set = prologue_p ? gen_rtx_SET ( mem , reg ) : gen_rtx_SET ( reg , mem ) ; unsigned regno2 = aarch64_get_next_set_bit ( components , regno + <NUM_LIT> ) ; if ( regno2 == last_regno ) { insn = emit_insn ( set ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; if ( prologue_p ) add_reg_note ( insn , REG_CFA_OFFSET , copy_rtx ( set ) ) ; else add_reg_note ( insn , REG_CFA_RESTORE , reg ) ; break ; } poly_int64 offset2 = cfun -> machine -> frame . reg_offset [ regno2 ] ; if ( ! satisfies_constraint_Ump ( mem ) || GP_REGNUM_P ( regno ) != GP_REGNUM_P ( regno2 ) || maybe_ne ( ( offset2 - cfun -> machine -> frame . reg_offset [ regno ] ) , GET_MODE_SIZE ( mode ) ) ) { insn = emit_insn ( set ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; if ( prologue_p ) add_reg_note ( insn , REG_CFA_OFFSET , copy_rtx ( set ) ) ; else add_reg_note ( insn , REG_CFA_RESTORE , reg ) ; regno = regno2 ; continue ; } rtx reg2 = gen_rtx_REG ( mode , regno2 ) ; if ( ! frame_pointer_needed ) offset2 += cfun -> machine -> frame . frame_size - cfun -> machine -> frame . hard_fp_offset ; rtx addr2 = plus_constant ( Pmode , ptr_reg , offset2 ) ; rtx mem2 = gen_frame_mem ( mode


<s> const MCOperand & MO = MI -> getOperand ( OpNo ) ; assert ( MO . isReg ( ) && <STR_LIT> ) ; O <<


<s> bool <ISA_LIT>FastISel :: SelectRet ( const Instruction * I ) { const ReturnInst * Ret = cast < ReturnInst > ( I ) ; const Function & F = * I -> getParent ( ) -> getParent ( ) ; if ( ! FuncInfo . CanLowerReturn ) return false ; if ( TLI . supportSplitCSR ( FuncInfo . MF ) ) return false ; SmallVector < unsigned , <NUM_LIT> > RetRegs ; CallingConv :: ID CC = F . getCallingConv ( ) ; if ( Ret -> getNumOperands ( ) > <NUM_LIT> ) { SmallVector < <STR_LIT> , <NUM_LIT> > Outs ; GetReturnInfo ( F . getReturnType ( ) , F . getAttributes ( ) , Outs , TLI , DL ) ; SmallVector < CCValAssign , <NUM_LIT> > ValLocs ; CCState CCInfo ( CC , F . isVarArg ( ) , * FuncInfo . MF , ValLocs , I -> getContext ( ) ) ; CCInfo . AnalyzeReturn ( Outs , CCAssignFnForCall ( CC , true , F . isVarArg ( ) ) ) ; const Value * RV = Ret -> getOperand ( <NUM_LIT> ) ; unsigned Reg = getRegForValue ( RV ) ; if ( Reg == <NUM_LIT>


<s> if ( HII -> isIndirectCall ( MI ) && ( DepType == SDep :: Data ) ) { const MachineOperand MO = MI . getOperand ( <NUM_LIT> ) ; if ( MO . isReg ( ) && MO . isUse ( ) && ( MO . getReg ( ) == DepReg ) ) return true ; } if ( HII -> isJumpR ( MI ) ) { const MachineOperand & MO = HII -> isPredicated ( MI ) ? MI . getOperand ( <NUM_LIT> ) : MI . getOperand


<s> hasFP ( const MachineFunction & MF ) const { const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; return DisableFramePointerElim ( MF ) || MFI -> hasVarSizedObjects


<s> t [ <NUM_LIT> ] = permute_selectors [ element_selector_76 ] + <NUM_LIT> ; t [ <NUM_LIT> ] = permute_selectors [ element_selector_10 ] + <NUM_LIT> ; t [ <NUM_LIT> ] = permute_selectors [ element_selector_32 ] + <NUM_LIT> ; t [ <NUM_LIT> ] = permute_selectors [ element_selector_54 ] ; t [ <NUM_LIT> ] = permute_selectors [ element_selector_76 ] ; return ( __m128i ) vec_perm ( ( __v4si ) __A , ( __v4si )


<s> peekTokens ( NextToken ) ; return isOperandModifier ( Tok , NextToken [ <NUM_LIT> ] ) || ( Tok . is ( AsmToken :: Minus ) && isRegOrOperandModifier (

NextToken [ <NUM_LIT> ] , NextToken [ <NUM_LIT> ] ) ) || isOpcodeModifierWithVal ( Tok , NextToken [ <NUM_LIT> ] ) ;


<s> unsigned <ISA_LIT>FastISel :: <ISA_LIT>MaterializeInt ( const Constant * C , MVT VT ) { if ( VT != <STR_LIT> && VT != <STR_LIT> && VT != <STR_LIT> && VT != <STR_LIT> && VT != <STR_LIT> ) return <NUM_LIT> ; const TargetRegisterClass * RC = ( ( VT == <STR_LIT> ) ? & <STR_LIT> : & <STR_LIT> ) ; const ConstantInt * CI = cast < ConstantInt > ( C ) ; if ( isInt < <NUM_LIT> > ( CI -> getSExtValue ( ) ) ) { unsigned Opc = ( VT == <STR_LIT> ) ? <STR_LIT> :


<s> case PLUS : if ( CONST_OK_FOR_I ( INTVAL ( x ) ) ) * total = <NUM_LIT> ; else if ( CONST_OK_FOR_J ( INTVAL ( x ) ) ) * total = <NUM_LIT> ; else * total = COSTS_N_INSNS ( <NUM_LIT> ) ; return true ; default : if ( CONST_OK_FOR_K ( INTVAL ( x ) ) || CONST_OK_FOR_L ( INTVAL ( x ) ) ) * total = <NUM_LIT> ; else * total = COSTS_N_INSNS ( <NUM_LIT> ) ; return true ; } case CONST_DOUBLE : * total = COSTS_N_INSNS ( <NUM_LIT> ) ; return true ; case CONST : case SYMBOL_REF : case LABEL_REF : * total = COSTS_N_INSNS ( <NUM_LIT> ) ; return true ; case MULT : if ( GET_MODE_SIZE ( GET_MODE ( x ) ) > <NUM_LIT> ) * total = COSTS_N_INSNS ( <NUM_LIT> ) ; else * total = COSTS_N_INSNS ( <NUM_LIT> ) ; return true ; case PLUS : case MINUS : case ASHIFT : case ASHIFTRT : case LSHIFTRT : * total = COSTS_N_INSNS ( <NUM_LIT> ) ; return


<s> rtx plus = XEXP ( x , <NUM_LIT> ) ; if ( GET_CODE ( plus ) == PLUS && REG_P ( XEXP ( plus , <NUM_LIT> ) ) && CONST_INT_P ( XEXP ( plus , <NUM_LIT> ) ) && ( INTVAL ( XEXP ( plus , <NUM_LIT> ) ) <= MAX_LD_OFFSET ( GET_MODE ( x ) ) ) ) { rtx xx = XEXP ( plus ,


<s> return ( __m128 ) __builtin_ia32_scalefss_round ( ( __v4sf ) __A , (


<s> uint64_t encodeMsg ( uint64_t MsgId , uint64_t OpId , uint64_t StreamId ) { return MsgId | ( OpId << OP_SHIFT_ ) | ( StreamId <<


<s> assemble_name ( stream , name ) ; fprintf ( stream , <STR_LIT> , size , align / BITS_PER_UNIT


<s> unsigned Reg0 = ChangeReg0 ? Reg2 : MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; bool Reg0IsDead = MI . getOperand ( <NUM_LIT> ) . isDead ( ) ; return BuildMI ( MF , MI . getDebugLoc ( ) , MI . getDesc ( ) ) . addReg ( Reg0 , RegState :: Define | getDeadRegState ( Reg0IsDead ) ) . addReg ( Reg2 , getKillRegState ( Reg2IsKill ) ) . addReg ( Reg1 , getKillRegState ( Reg1IsKill ) ) . addImm ( ( ME + <NUM_LIT> ) & <NUM_LIT> ) . addImm ( ( MB - <NUM_LIT> ) & <NUM_LIT> ) ; } if ( ChangeReg0 ) { MI . getOperand ( <NUM_LIT> ) . setReg ( Reg2 ) ; MI . getOperand ( <NUM_LIT> ) . setSubReg ( SubReg2 ) ; } MI . getOperand ( <NUM_LIT> ) . setReg ( Reg1 ) ; MI . getOperand ( <NUM_LIT> ) . setReg ( Reg2 ) ; MI . getOperand ( <NUM_LIT> ) . setSubReg ( SubReg1 ) ; MI . getOperand ( <NUM_LIT> ) . setSubReg ( SubReg2 ) ; MI . getOperand ( <NUM_LIT> ) . setIsKill ( Reg1IsKill ) ; MI . getOperand ( <NUM_LIT> ) . setIsKill ( Reg2IsKill ) ; MI . getOperand ( <NUM_LIT> ) . setImm ( (


<s> MCAsmInfo * MAI = new <ISA_LIT>MCAsmInfo ( TT ) ; MCRegister SP = MRI . getDwarfRegNum ( <STR_LIT> , true ) ; MCCFIInstruction Inst = MCCFIInstruction :: cfiDefCfa ( nullptr , SP , <NUM_LIT> ) ; MAI -> addInitialFrameState (


<s> return ( poly16x8_t ) __builtin_neon_vreinterpretv8hiv16qi ( (


<s> return ( __m64 ) __builtin_arm_wcmpgtsh ( ( __v4hi ) __m1 , ( __v4hi )


<s> if ( tryParseRegister ( RegNo , StartLoc , EndLoc ) != MatchOperand_Success ) return Error ( StartLoc , <STR_LIT> ) ; return false


<s> return ( ( MIaG == <STR_LIT> && MIbG == <STR_LIT> ) && ( MIa . getOperand ( <NUM_LIT> ) . getReg ( ) == MIb . getOperand ( <NUM_LIT> )


<s> if ( ! isUnpredicatedTerminator ( * I ) ) break ; if ( ! I -> isBranch ( ) || I -> isIndirectBranch ( ) ) return true ; if ( ! isPredicated ( * I ) ) { if ( ! I -> isUnconditionalBranch ( ) ) fixOpcodeForGuard ( * I ) ; TBB = getBranchTarget ( & * I ) ; if ( AllowModify ) { while ( std :: next ( I ) != MBB . end ( ) ) std :: next ( I ) -> eraseFromParent ( ) ; } continue ; } if ( isPredicated ( * I )


<s> LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; clearResources ( ) ; PacketNum =


<s> const char * getPassName ( ) const override { return


<s> <ISA_LIT>ebTargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) : <ISA_LIT>TargetMachine ( T , TT , CPU , FS , RM , CM , OL ,


<s> } unsigned NewOpc = IsVGPR ? <STR_LIT> : <STR_LIT> ; const TargetRegisterClass & RegRC = IsVGPR ? <STR_LIT> : <STR_LIT> ; const TargetRegisterClass * DstRC = TRI . getRegClassForTypeOnBank ( Ty , * DstRB ) ; const TargetRegisterClass * SrcRC = TRI . getRegClassForTypeOnBank ( Ty , * SrcRB ) ; const TargetRegisterClass * MaskRC = TRI . getRegClassForTypeOnBank ( MaskTy , * MaskRB ) ; if ( ! RBI . constrainGenericRegister ( DstReg , * DstRC , * MRI ) || ! RBI . constrainGenericRegister ( SrcReg , * SrcRC , * MRI ) || ! RBI . constrainGenericRegister ( MaskReg , * MaskRC , * MRI ) ) return false ; if ( Ty . getSizeInBits ( ) == <NUM_LIT> ) { assert ( MaskTy . getSizeInBits ( ) == <NUM_LIT> && <STR_LIT> ) ; BuildMI ( * BB , & I , DL , TII . get ( NewOpc ) , DstReg ) . addReg ( SrcReg ) . addReg ( MaskReg ) ; I . eraseFromParent ( ) ; return true ; } Register HiReg = MRI -> createVirtualRegister ( & RegRC ) ; Register LoReg = MRI -> createVirtualRegister ( & RegRC ) ; BuildMI ( * BB , & I , DL , TII . get ( <STR_LIT> ) , LoReg ) . addReg ( SrcReg , <NUM_LIT> , <STR_LIT> ) ; BuildMI ( * BB , & I , DL , TII . get ( <STR_LIT> ) , HiReg ) . addReg ( SrcReg , <NUM_LIT> , <STR_LIT> ) ; Register MaskedLo , MaskedHi ; if ( CanCopyLow32 ) { MaskedLo = LoReg ; } else { Register MaskLo = MRI -> createVirtualRegister ( & RegRC ) ; MaskedLo = MRI -> createVirtualRegister ( & RegRC ) ; BuildMI ( * BB , & I , DL , TII . get ( <STR_LIT> ) , MaskLo ) . addReg ( MaskReg , <NUM_LIT> , <STR_LIT> ) ; BuildMI ( * BB , & I , DL , TII . get ( NewOpc ) , MaskedLo ) . addReg ( LoReg ) . addReg ( MaskLo ) ; } if ( CanCopyHi32 ) { MaskedHi = HiReg ; } else { Register MaskHi = MRI -> createVirtualRegister ( & RegRC ) ; MaskedHi = MRI -> createVirtualRegister ( & RegRC ) ; BuildMI ( * BB , & I , DL , TII . get ( <STR_LIT> ) , MaskHi ) . addReg ( MaskReg , <NUM_LIT> , <STR_LIT> ) ; BuildMI ( * BB , & I , DL , TII . get ( NewOpc ) , MaskedHi ) . addReg ( HiReg ) . addReg ( MaskHi ) ; } BuildMI ( * BB , & I , DL , TII . get ( <STR_LIT> ) , DstReg ) . addReg ( MaskedLo ) . addImm ( <STR_LIT> ) . addReg ( MaskedHi )


<s> HOST_WIDE_INT ix86_initial_elimination_offset ( int from , int to ) { struct ix86_frame frame ; ix86_compute_frame_layout ( & frame ) ; if ( from == ARG_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM ) return frame . hard_frame_pointer_offset ; else if ( from == FRAME_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM ) return frame . hard_frame_pointer_offset -


<s> unsigned End = KillInst ? KillInstIdx : LastInstIdx ; unsigned OtherEnd = Other -> KillInst ? Other -> KillInstIdx : Other -> LastInstIdx ; return StartInstIdx <= OtherEnd && Other ->


<s> switch ( mode ) { case E_HImode : helper_name = ( code == ASHIFT ? <STR_LIT> : ( code == ASHIFTRT ? <STR_LIT> : ( code == LSHIFTRT ? <STR_LIT> : NULL ) ) ) ; break ; case E_PSImode : helper_name = ( code == ASHIFT ? <STR_LIT> : ( code == ASHIFTRT ? <STR_LIT> : ( code == LSHIFTRT ? <STR_LIT> : NULL ) ) ) ; const_variant = false ; break ; case E_SImode : helper_name = ( code == ASHIFT ? <STR_LIT> : ( code == ASHIFTRT ? <STR_LIT> : ( code == LSHIFTRT ? <STR_LIT> : NULL )


<s> ret . val [ <NUM_LIT> ] = ( float32x2_t ) __builtin_aarch64_get_dregoiv2sf ( __o , <NUM_LIT> ) ; return


<s> SDValue Tmp2 = DAG . getNode ( <STR_LIT> , dl , VT , ShOpHi , ShAmt ) ; SDValue Tmp3 = DAG . getNode ( <STR_LIT> , dl , VT , ShOpLo , ExtraShAmt ) ; SDValue FalseVal = DAG . getNode ( <STR_LIT> , dl , VT , Tmp1 , Tmp2 ) ; SDValue CCR = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; SDValue Cmp = get<ISA_LIT>Cmp ( ExtraShAmt , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) , <STR_LIT> , <ISA_LIT>CC , DAG , dl ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , dl , VT , ShOpLo , ShAmt ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , dl , VT

, FalseVal , Tmp3 , <ISA_LIT>CC , CCR , Cmp ) ;


<s> static MCInstrInfo * create<ISA_LIT>MCInstrInfo ( ) { MCInstrInfo * X = new MCInstrInfo ( ) ; Init<ISA_LIT>MCInstrInfo (


<s> RegisterAsmParser < <ISA_LIT>ATTAsmParser > X ( The<ISA_LIT>_32Target ) ; RegisterAsmParser < <ISA_LIT>ATTAsmParser > Y ( The<ISA_LIT>_64Target ) ; LLVMInitialize<ISA_LIT>AsmLexer ( )


<s> rtx insn , frame_off , cfa ; offset = area_bottom < <NUM_LIT> ? - area_bottom : <NUM_LIT> ; frame_off = GEN_INT ( cfun_frame_layout . frame_size - offset ) ; cfa = gen_rtx_SET ( frame_pointer , gen_rtx_PLUS ( Pmode , frame_pointer , frame_off ) ) ; if ( DISP_IN_RANGE ( INTVAL ( frame_off ) ) ) { insn = gen_rtx_SET ( frame_pointer , gen_rtx_PLUS ( Pmode , frame_pointer , frame_off ) ) ; insn = emit_insn ( insn ) ; } else { if ( ! CONST_OK_FOR_K ( INTVAL ( frame_off ) ) ) frame_off = force_const_mem ( Pmode , frame_off ) ; insn = emit_insn ( gen_add2_insn ( frame_pointer , frame_off ) ) ; annotate_constant_pool_refs ( & PATTERN ( insn ) ) ; } add_reg_note ( insn , REG_CFA_ADJUST_CFA , cfa ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; } if ( TARGET_64BIT ) { if ( cfun_save_high_fprs_p ) { next_offset = cfun_frame_layout . f8_offset ; for ( i = FPR8_REGNUM ; i <= FPR15_REGNUM ; i ++ ) { if ( cfun_fpr_save_p ( i ) ) { restore_fpr ( frame_pointer , offset + next_offset , i ) ; cfa_restores = alloc_reg_note ( REG_CFA_RESTORE , gen_rtx_REG ( DFmode , i ) , cfa_restores ) ; next_offset += <NUM_LIT> ; } } } } else { next_offset = cfun_frame_layout . f4_offset ; for ( i = FPR4_REGNUM ; i <= FPR4_REGNUM + <NUM_LIT> ; i ++ ) { if ( cfun_fpr_save_p ( i ) ) { restore_fpr ( frame_pointer , offset + next_offset , i ) ; cfa_restores = alloc_reg_note ( REG_CFA_RESTORE , gen_rtx_REG ( DFmode , i ) , cfa_restores ) ; next_offset += <NUM_LIT> ; } else if ( ! TARGET_PACKED_STACK ) next_offset += <NUM_LIT> ; } } return_reg = gen_rtx_REG ( Pmode , RETURN_REGNUM ) ; if ( cfun_frame_layout . first_restore_gpr != - <NUM_LIT> ) { rtx insn , addr ; int i ; for ( i = cfun_frame_layout . first_restore_gpr ; i <= cfun_frame_layout . last_restore_gpr ; i ++ ) { if ( global_not_special_regno_p ( i ) ) { addr = plus_constant ( Pmode , frame_pointer , offset + cfun_frame_layout . gprs_offset + ( i - cfun_frame_layout . first_save_gpr_slot ) * UNITS_PER_LONG ) ; addr = gen_rtx_MEM ( Pmode , addr ) ; set_mem_alias_set ( addr , get_frame_alias_set ( ) ) ; emit_move_insn ( addr , gen_rtx_REG ( Pmode , i ) ) ; } else cfa_restores = alloc_reg_note ( REG_CFA_RESTORE , gen_rtx_REG ( Pmode , i ) , cfa_restores ) ; } if ( ! sibcall ) { if ( cfun_gpr_save_slot ( RETURN_REGNUM ) == SAVE_SLOT_STACK ) { int return_regnum = find_unused_clobbered_reg ( ) ; if ( ! return_regnum ) return_regnum = <NUM_LIT> ; return_reg = gen_rtx_REG ( Pmode , return_regnum ) ; addr = plus_constant ( Pmode , frame_pointer , offset + cfun_frame_layout . gprs_offset + ( RETURN_REGNUM - cfun_frame_layout . first_save_gpr_slot ) * UNITS_PER_LONG ) ; addr = gen_rtx_MEM ( Pmode , addr


<s> if ( Opc == <STR_LIT> ) { int DestReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; MachineOperand & Symbol = MI -> getOperand ( <NUM_LIT> ) ; BuildMI ( * MBB , MII , MI -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , DestReg ) . addOperand ( Symbol ) ; MII = MBB -> erase ( MI ) ; continue ; } else if ( Opc == <STR_LIT> && MI -> getOperand ( <NUM_LIT> ) . isBlockAddress ( ) ) { int DestReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; MachineOperand & Symbol = MI -> getOperand ( <NUM_LIT> ) ; BuildMI ( * MBB , MII , MI -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , DestReg ) . addOperand ( Symbol ) ; BuildMI ( * MBB , MII , MI -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , DestReg ) . addOperand ( Symbol ) ; MII = MBB -> erase ( MI ) ; continue ; } else if ( Opc == <STR_LIT> || Opc == <STR_LIT> ) { int DestReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; int64_t ImmValue ; if ( Opc == <STR_LIT> ) { APFloat Val = MI -> getOperand ( <NUM_LIT> ) . getFPImm ( ) -> getValueAPF ( ) ; ImmValue = * Val . bitcastToAPInt ( ) . getRawData ( ) ; } else ImmValue = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; BuildMI ( * MBB , MII , MI -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , DestReg ) . addImm ( ImmValue ) ; MII = MBB -> erase ( MI ) ; continue ; } else if ( Opc == <STR_LIT> || Opc == <STR_LIT> ) { int DestReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; int64_t ImmValue ; if ( Opc == <STR_LIT> ) { APFloat Val = MI -> getOperand ( <NUM_LIT> ) . getFPImm ( ) -> getValueAPF ( ) ; ImmValue = * Val . bitcastToAPInt ( ) . getRawData


<s> return new Tile64PassConfig ( this , PM


<s> static DecodeStatus decodeMemRIHashOperands ( MCInst & Inst , uint64_t Imm , int64_t Address , const void * Decoder ) { const uint64_t Base = Imm >> <NUM_LIT> ; const int64_t Disp = SignExtend64 < <NUM_LIT> > ( ( Imm & <NUM_LIT> ) + <NUM_LIT> ) * <NUM_LIT> ; assert ( Base < <NUM_LIT> && <STR_LIT>


<s> MI . setOpcode ( <STR_LIT> ) ; HasRt = true ; } else if ( Rs == Rt ) { MI . setOpcode ( <STR_LIT> ) ; HasRs = true ; } else { MI . setOpcode ( <STR_LIT> ) ; HasRs = true ; HasRt = true ; } if ( HasRs ) MI . addOperand ( MCOperand :: createReg ( getReg ( Decoder , <STR_LIT> , Rs ) ) ) ; if ( HasRt ) MI . addOperand ( MCOperand :: createReg ( getReg ( Decoder , <STR_LIT> , Rt ) ) ) ; MI . addOperand ( MCOperand :: createImm ( Imm ) ) ; return MCDisassembler ::


<s> case TLSModel :: GeneralDynamic : RefFlags |= <ISA_LIT>MCExpr :: VK_TLSDESC ; break ; } } else { RefFlags |= <ISA_LIT>MCExpr :: VK_ABS ; } if ( ( MO . getTargetFlags ( ) & <STR_LIT> ) == <STR_LIT> ) RefFlags |= <ISA_LIT>MCExpr :: VK_PAGE ; else if ( ( MO . getTargetFlags ( ) & <STR_LIT> ) == <STR_LIT> ) RefFlags |= <ISA_LIT>MCExpr :: VK_PAGEOFF ; else if ( ( MO . getTargetFlags ( ) & <STR_LIT> ) == <STR_LIT> ) RefFlags |= <ISA_LIT>MCExpr :: VK_G3 ; else if ( ( MO . getTargetFlags ( ) & <STR_LIT> ) == <STR_LIT> ) RefFlags |= <ISA_LIT>MCExpr :: VK_G2 ; else if ( ( MO . getTargetFlags ( ) & <STR_LIT> ) == <STR_LIT> ) RefFlags |= <ISA_LIT>MCExpr :: VK_G1 ; else if ( ( MO . getTargetFlags ( ) & <STR_LIT> ) == <STR_LIT> ) RefFlags |= <ISA_LIT>MCExpr :: VK_G0 ; if ( MO . getTargetFlags ( ) & <STR_LIT> ) RefFlags |= <ISA_LIT>MCExpr :: VK_NC ; const MCExpr * Expr = MCSymbolRefExpr :: Create (

Sym , MCSymbolRefExpr :: VK_None , Ctx ) ;


<s> Relocator :: DWord A = helper_extract_movw_movt_addend ( pReloc . target ( ) ) + pReloc . addend ( ) ; LDSection & target_sect = pReloc . targetRef ( ) . frag ( ) -> getParent ( ) -> getSection ( ) ; if ( ( llvm :: ELF :: SHF_ALLOC & target_sect . flag ( ) ) != <NUM_LIT> ) { if ( rsym -> reserved ( ) & <ISA_LIT>Relocator :: ReservePLT ) { S = helper_get_PLT_address ( * rsym , pParent ) ; } } Relocator :: DWord X = S + A ; X >>=


<s> cum -> nbytes += ( ( arg . promoted_size_in_bytes ( ) +


<s> else emit_insn ( gen_addsi3 ( countreg , countreg , GEN_INT (


<s> if ( parseOperand ( Operands , ForceImmediate ) ) return true ; while ( getLexer ( ) . is ( AsmToken :: Comma ) ) { getLexer ( ) . Lex ( ) ; if ( parseOperand ( Operands , false ) ) return true ; } if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) { SMLoc Loc = getLexer ( ) . getLoc ( ) ; getParser ( ) . eatToEndOfStatement ( ) ; return Error ( Loc ,


<s> const char * ptx_type = nvptx_ptx_type_from_mode ( mode , false ) ; const char * pfx = <STR_LIT> ; const char * sfx = <STR_LIT> ; if ( for_proto ) pfx = <STR_LIT> ,


<s> if ( parseRegister ( Reg , Group , Regs ) ) return MatchOperand_ParseFail ; Operands . push_back ( <ISA_LIT>Operand :: createReg ( Kind , Reg . Num , Reg . StartLoc , Reg . EndLoc ) ) ; return MatchOperand_Success


<s> const TargetFrameLowering * TFI = MF . getTarget


<s> unsigned IntNo = cast < ConstantSDNode > ( Addr -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; if ( IntNo != <STR_LIT> ) return nullptr ; SDValue nextAddr = Addr -> getOperand ( <NUM_LIT> ) ; SDValue CheckEventChainOut ( Addr . getNode ( ) , <NUM_LIT> ) ; if ( ! CheckEventChainOut . use_empty ( ) ) { SDValue CheckEventChainIn = Addr -> getOperand ( <NUM_LIT> ) ; SDValue NewChain = replaceInChain ( CurDAG , Chain , CheckEventChainOut , CheckEventChainIn ) ; if ( ! NewChain . getNode ( ) ) return nullptr ; Chain = NewChain ; } SDValue constOne = getI32Imm (


<s> unsigned Opc = BBI -> getOpcode ( ) ; if ( Opc != <STR_LIT> && Opc != <STR_LIT> && Opc != <STR_LIT> && Opc != <STR_LIT> ) continue ; if ( ! BBI -> getOperand ( <NUM_LIT> ) . isImm ( ) ) continue ; assert ( BBI -> getOperand ( <NUM_LIT> ) . isReg ( ) && <STR_LIT> ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; BBI -> dump ( ) ; ) ; Register Reg = BBI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; int64_t Imm = BBI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; MachineOperand * DeadOrKillToUnset = nullptr ; if ( BBI -> getOperand ( <NUM_LIT> ) . isDead ( ) ) { DeadOrKillToUnset = & BBI -> getOperand ( <NUM_LIT> ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * DeadOrKillToUnset << <STR_LIT> << * BBI << <STR_LIT> ) ; } for ( auto AfterBBI = std :: next ( BBI ) ; AfterBBI != MBB . instr_end ( ) ; ++ AfterBBI ) { int KillIdx = AfterBBI -> findRegisterUseOperandIdx ( Reg , true , TRI ) ; if ( KillIdx != - <NUM_LIT> ) { assert ( ! DeadOrKillToUnset && <STR_LIT> ) ; DeadOrKillToUnset = & AfterBBI -> getOperand ( KillIdx ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * DeadOrKillToUnset << <STR_LIT> << * AfterBBI << <STR_LIT> ) ; } if ( ! AfterBBI -> modifiesRegister ( Reg , TRI ) ) continue ; assert ( DeadOrKillToUnset && <STR_LIT> ) ; if ( AfterBBI -> getOpcode ( ) != Opc ) break ; assert ( AfterBBI -> getOperand ( <NUM_LIT> ) . isReg ( ) && <STR_LIT> ) ; if ( ! AfterBBI -> getOperand ( <NUM_LIT> ) . isImm ( ) || AfterBBI -> getOperand ( <NUM_LIT> ) . getImm ( ) != Imm ) break ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * DeadOrKillToUnset << <STR_LIT> << * DeadOrKillToUnset -> getParent ( ) ) ; if ( DeadOrKillToUnset -> isDef ( ) ) DeadOrKillToUnset -> setIsDead ( false ) ; else DeadOrKillToUnset -> setIsKill ( false ) ; DeadOrKillToUnset = AfterBBI -> findRegisterDefOperand ( Reg , true , true , TRI ) ; if ( DeadOrKillToUnset ) LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * DeadOrKillToUnset << <STR_LIT> << * AfterBBI << <STR_LIT> ) ; InstrsToErase . insert ( & * AfterBBI ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; AfterBBI -> dump ( ) ) ; } } for ( MachineInstr * MI : InstrsToErase ) { MI -> eraseFromParent (


<s> Target & llvm :: getThe<ISA_LIT>64LETarget (


<s> unsigned Opcode = Op -> getOperand ( <NUM_LIT> ) . getOpcode ( ) ; for ( unsigned i = <NUM_LIT> ; i < NumElems ; ++ i ) if ( Opcode != Op -> getOperand ( i ) . getOpcode ( ) ) return SDValue ( ) ; switch ( Opcode ) { default : return SDValue ( ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( Op -> getSplatValue ( ) ) return SDValue ( ) ; if ( ! TLI . isOperationLegalOrPromote ( Opcode


<s> if ( type1 == NUM_TYPE_SUFFIXES ) return report_no_such_form ( type0 ) ; if ( type0 == type_suffix_ids [ <NUM_LIT> ] ) return report_no_such_form ( type1 ) ; gcc_unreachable ( ) ; } return res


<s> return parseOptionalOps ( FlatAtomicOptionalOps


<s> void <ISA_LIT>FrameLowering :: processFunctionBeforeFrameFinalized ( MachineFunction & MF ) const { if ( hasFP ( MF ) ) { int FrameIdx = MF . getFrameInfo ( ) -> CreateFixedObject ( <NUM_LIT> , - <NUM_LIT> , true ) ; ( void )


<s> SmallPtrSet < MachineBasicBlock * , <NUM_LIT> > BasicBlocks ; for ( auto * Dead : Killed ) BasicBlocks . insert ( Dead -> getParent ( ) ) ; std :: map < MachineInstr * , SmallPtrSet < MachineInstr * , <NUM_LIT> >> ITBlocks ; for ( auto * MBB : BasicBlocks ) { for ( auto & IT : * MBB ) { if ( IT . getOpcode ( ) != <STR_LIT> ) continue ; RDA . getReachingLocalUses ( & IT , MCRegister :: from ( <STR_LIT> ) , ITBlocks [ & IT ] ) ; } } SmallPtrSet < MachineInstr * , <NUM_LIT> > ModifiedITs ; SmallPtrSet < MachineInstr * , <NUM_LIT> > RemoveITs ; for ( auto * Dead : Killed ) { if ( MachineOperand * MO = Dead -> findRegisterUseOperand ( <STR_LIT> ) ) { MachineInstr * IT = RDA . getMIOperand ( Dead , * MO ) ; RemoveITs . insert ( IT ) ; auto & CurrentBlock = ITBlocks [ IT ] ; CurrentBlock . erase ( Dead ) ; if ( CurrentBlock . empty ( ) ) ModifiedITs . erase ( IT ) ; else ModifiedITs . insert ( IT ) ; } } if ( ! ModifiedITs . empty ( ) ) return false ; Killed . insert ( RemoveITs . begin ( ) , RemoveITs . end ( ) ) ; return true ; } ; SmallPtrSet < MachineInstr * , <NUM_LIT> > Uses ; if ( ! RDA . isSafeToRemove ( MI , Uses , Ignore ) ) return false ; if ( WontCorruptITs ( Uses , RDA ) ) { ToRemove . insert ( Uses . begin ( ) , Uses . end ( ) ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * MI << <STR_LIT> ; for ( auto * Use : Uses ) dbgs ( ) << <STR_LIT> << * Use ) ; SmallPtrSet < MachineInstr * , <NUM_LIT> > Killed ; RDA . collectKilledOperands (


<s> break ; case ORDERED : case UNORDERED : case UNGT : case UNLT : case UNEQ : case UNGE : case UNLE : case LTGT : qpfunc = ( TARGET_ARCH64 ? <STR_LIT> : <STR_LIT> ) ; break ; default : gcc_unreachable ( ) ; } if ( TARGET_ARCH64 ) { if ( MEM_P ( x ) ) { tree expr = MEM_EXPR ( x ) ; if ( expr ) mark_addressable ( expr ) ; slot0 = x ; } else { slot0 = assign_stack_temp ( TFmode , GET_MODE_SIZE ( TFmode ) ) ; emit_move_insn ( slot0 , x ) ; } if ( MEM_P ( y ) ) { tree expr = MEM_EXPR ( y ) ; if ( expr ) mark_addressable ( expr ) ; slot1 = y ; } else { slot1 = assign_stack_temp ( TFmode , GET_MODE_SIZE ( TFmode ) ) ; emit_move_insn ( slot1 , y ) ; } libfunc = gen_rtx_SYMBOL_REF ( Pmode , qpfunc ) ; emit_library_call ( libfunc , LCT_NORMAL , DImode , XEXP ( slot0 , <NUM_LIT> ) , Pmode , XEXP ( slot1 , <NUM_LIT> ) , Pmode ) ; mode = DImode ; } else { libfunc = gen_rtx_SYMBOL_REF (


<s> const TargetRegisterClass * Src0SubRC = RI . getSubRegClass ( Src0RC , <STR_LIT> ) ; MachineOperand SrcReg0Sub0 = buildExtractSubRegOrImm ( MII , MRI , Src0 , Src0RC , <STR_LIT> , Src0SubRC ) ; const TargetRegisterClass * DestRC = MRI . getRegClass ( Dest . getReg ( ) ) ; const TargetRegisterClass * NewDestRC = RI . getEquivalentVGPRClass ( DestRC ) ; const TargetRegisterClass * NewDestSubRC = RI . getSubRegClass ( NewDestRC , <STR_LIT> ) ; unsigned DestSub0 = MRI . createVirtualRegister ( NewDestSubRC ) ; BuildMI ( MBB , MII , DL , InstDesc , DestSub0 ) . add ( SrcReg0Sub0 ) ; MachineOperand SrcReg0Sub1 = buildExtractSubRegOrImm ( MII , MRI , Src0 , Src0RC , <STR_LIT> , Src0SubRC ) ; unsigned DestSub1 = MRI . createVirtualRegister ( NewDestSubRC ) ; BuildMI ( MBB , MII , DL , InstDesc ,


<s> if ( VT . isFloatingPoint ( ) || VT . isVector ( ) ) return Sched :: Latency ; } if ( ! N -> isMachineOpcode ( ) ) return Sched :: RegPressure ; const TargetInstrInfo * TII = getTargetMachine ( ) . getInstrInfo ( ) ; const TargetInstrDesc & TID = TII -> get ( N -> getMachineOpcode ( ) ) ; if ( TID . mayLoad ( ) ) return Sched :: Latency ; const InstrItineraryData & Itins = getTargetMachine ( ) . getInstrItineraryData ( ) ; if ( ! Itins . isEmpty ( ) && Itins . getStageLatency ( TID . getSchedClass ( ) ) > <NUM_LIT> ) return


<s> if ( Cand . CanMergeToLSDouble ) Merged = CreateLoadStoreDouble ( MBB , InsertBefore , Offset , Base , BaseKill , Opcode , Pred , PredReg , DL , Regs ) ; if ( ! Merged && Cand . CanMergeToLSMulti ) Merged = CreateLoadStoreMulti ( MBB , InsertBefore , Offset , Base , BaseKill , Opcode , Pred , PredReg , DL , Regs ) ; if ( ! Merged ) return nullptr ; iterator EarliestI ( Cand . Instrs [ Cand . EarliestMIIdx ] ) ; bool EarliestAtBegin = false ; if ( EarliestI == MBB . begin ( ) ) { EarliestAtBegin = true ; } else { EarliestI = std :: prev ( EarliestI ) ; } for ( MachineInstr * MI : Cand . Instrs ) MBB . erase ( MI ) ; if ( EarliestAtBegin ) EarliestI = MBB . begin ( ) ; else EarliestI = std :: next ( EarliestI ) ; auto FixupRange = make_range ( EarliestI , iterator ( Merged ) ) ; if ( isLoadSingle ( Opcode ) ) { for ( MachineInstr & MI : FixupRange ) { for ( unsigned & ImpDefReg : ImpDefs ) { for ( MachineOperand & MO : MI . implicit_operands ( ) ) { if ( ! MO . isReg ( ) || MO . getReg ( ) != ImpDefReg ) continue ; if ( MO . readsReg ( ) ) MO


<s> MachineInstr * ResInst ; if ( IsSgpr && TII . isInlineConstant ( Imm ) ) { ResInst = BuildMI ( * BB , & I , DL , TII . get ( <STR_LIT> ) , DstReg ) . addImm ( I . getOperand ( <NUM_LIT> ) . getImm ( ) ) ; } else { const TargetRegisterClass * RC = IsSgpr ? & <STR_LIT> : & <STR_LIT> ; Register LoReg = MRI -> createVirtualRegister ( RC ) ; Register HiReg = MRI -> createVirtualRegister ( RC ) ; BuildMI ( * BB , & I , DL , TII . get ( Opcode ) , LoReg ) . addImm ( Imm . trunc ( <NUM_LIT> ) . getZExtValue ( ) ) ; BuildMI ( * BB , & I , DL , TII . get ( Opcode ) , HiReg ) . addImm ( Imm . ashr ( <NUM_LIT> ) . getZExtValue ( ) ) ; ResInst = BuildMI ( * BB , & I , DL , TII . get ( <STR_LIT> ) , DstReg ) . addReg ( LoReg ) . addImm ( <STR_LIT> ) . addReg ( HiReg ) . addImm ( <STR_LIT> ) ; } I . eraseFromParent (


<s> auto Op = std :: make_unique < <ISA_LIT>Operand > ( Immediate ) ; Op -> Imm . Val = Val ; Op -> StartLoc =


<s> const uint64_t F = <ISA_LIT>MCInstrInfo :: getDesc ( MCII , MCI )


<s> if ( TypeName . empty ( ) ) return true ; auto Type = parseType ( TypeName ) ; if ( ! Type ) return error ( <STR_LIT> , TypeTok ) ; auto WasmSym = cast < MCSymbolWasm > ( Ctx . getOrCreateSymbol ( SymName ) ) ; WasmSym -> setType ( <STR_LIT> ) ; WasmSym -> setGlobalType ( <STR_LIT> { uint8_t ( Type . getValue ( ) ) , true } ) ; TOut . emitGlobalType ( WasmSym ) ; return expect ( AsmToken :: EndOfStatement , <STR_LIT> ) ; } if ( DirectiveID . getString ( ) == <STR_LIT> ) { auto SymName = expectIdent ( ) ; if ( SymName . empty ( ) ) return true ; auto WasmSym = cast < MCSymbolWasm > ( Ctx . getOrCreateSymbol ( SymName ) ) ; if ( CurrentState == Label && WasmSym == LastLabel ) { if ( ensureEmptyNestingStack ( ) ) return true ; CurrentState = FunctionStart ; LastFunctionLabel = LastLabel ; push ( Function ) ; } auto Signature = make_unique < <STR_LIT> > ( ) ; if ( parseSignature ( Signature . get ( ) ) ) return true ; WasmSym -> setSignature ( Signature . get ( ) ) ; addSignature ( std :: move ( Signature ) ) ; WasmSym -> setType ( <STR_LIT> ) ; TOut . emitFunctionType ( WasmSym ) ; return expect ( AsmToken :: EndOfStatement , <STR_LIT> ) ; } if ( DirectiveID . getString ( ) == <STR_LIT> ) { auto SymName = expectIdent ( ) ; if ( SymName . empty ( ) ) return true ; auto WasmSym = cast < MCSymbolWasm > ( Ctx . getOrCreateSymbol ( SymName ) ) ; auto Signature = make_unique < <STR_LIT> > ( ) ; if ( parseRegTypeList ( Signature -> Params ) ) return true ; WasmSym -> setSignature ( Signature . get ( ) ) ; addSignature ( std :: move ( Signature ) ) ; WasmSym -> setType ( <STR_LIT> ) ; TOut . emitEventType ( WasmSym ) ; return expect ( AsmToken :: EndOfStatement , <STR_LIT> ) ; } if ( DirectiveID . getString ( ) == <STR_LIT> ) { if ( CurrentState != FunctionStart ) return error ( <STR_LIT> , Lexer . getTok ( ) ) ; SmallVector < <STR_LIT> , <NUM_LIT> > Locals ; if ( parseRegTypeList ( Locals ) ) return true ; TOut . emitLocal ( Locals ) ; CurrentState = FunctionLocals ; return expect ( AsmToken :: EndOfStatement


<s> const MCExpr * OffsetExpr = MCConstantExpr :: create ( Offset , Ctx ) ; Expr = MCBinaryExpr :: createAdd ( Expr , OffsetExpr , Ctx ) ; } } Fixups . push_back ( MCFixup :: create ( Offset , Expr , ( MCFixupKind ) Kind , Loc ) ) ; if ( AllowTLS && OpNum + <NUM_LIT> < MI . getNumOperands ( ) ) { const MCOperand & MOTLS = MI . getOperand ( OpNum + <NUM_LIT> ) ; Fixups . push_back ( MCFixup :: create ( <NUM_LIT> , MOTLS . getExpr ( ) , ( MCFixupKind ) <STR_LIT> , Loc ) ) ; } return <NUM_LIT>


<s> unsigned nregs = REG_NREGS ( reg ) ; while ( nregs -- > <NUM_LIT> ) ss . reg_set_in_cycle [ regno + nregs ]


<s> bool <ISA_LIT>ArgumentUsageInfo :: doInitialization ( Module & M ) { return false


<s> for ( i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) clobbered_regs [ i ] = clobbered_regs [ i ] && ! global_regs [ i ] ; clobbered_regs [ RETURN_REGNUM ] |= ( TARGET_TPF_PROFILING || cfun_frame_layout . save_return_addr_p || crtl -> calls_eh_return ) ; memset ( cfun_frame_layout . gpr_save_slots , SAVE_SLOT_NONE ,


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT>


<s> bool <ISA_LIT>BranchRelaxation :: runOnMachineFunction ( MachineFunction & mf ) { MF = & mf ; if ( ! BranchRelaxation ) return false ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; TII = ( const <ISA_LIT>InstrInfo * ) MF -> getTarget ( ) . getSubtargetImpl ( ) -> getInstrInfo ( ) ; MF -> RenumberBlocks ( ) ; scanFunction ( ) ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; DEBUG ( dumpBBs ( ) ) ; bool MadeChange


<s> bool ix86_function_naked ( const_tree fn ) { if ( fn && lookup_attribute ( <STR_LIT> ,

DECL_ATTRIBUTES ( fn ) ) ) return true ;


<s> case MCSymbolRefExpr :: VK_<ISA_LIT>_TARGET2 : Type = ELF :: R_<ISA_LIT>_TARGET2 ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_PREL31 : Type = ELF :: R_<ISA_LIT>_PREL31 ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_SBREL : Type = ELF :: R_<ISA_LIT>_SBREL32 ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_TLSLDO : Type = ELF :: R_<ISA_LIT>_TLS_LDO32 ; break ; case MCSymbolRefExpr :: VK_TLSCALL : Type = ELF :: R_<ISA_LIT>_TLS_CALL ; break ; case MCSymbolRefExpr :: VK_TLSDESC : Type = ELF :: R_<ISA_LIT>_TLS_GOTDESC ; break ; case MCSymbolRefExpr :: VK_TLSLDM : Type = ELF :: R_<ISA_LIT>_TLS_LDM32 ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_TLSDESCSEQ : Type = ELF :: R_<ISA_LIT>_TLS_DESCSEQ ; break ; } break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : Type = ELF :: R_<ISA_LIT>_JUMP24 ; break ; case <STR_LIT> : switch ( Modifier ) { default : llvm_unreachable ( <STR_LIT> ) ; case MCSymbolRefExpr :: VK_None : Type = ELF :: R_<ISA_LIT>_MOVT_ABS ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_SBREL : Type = ELF :: R_<ISA_LIT>_MOVT_BREL ; break ; } break ; case <STR_LIT> : switch ( Modifier ) { default : llvm_unreachable ( <STR_LIT> ) ; case MCSymbolRefExpr :: VK_None : Type = ELF :: R_<ISA_LIT>_MOVW_ABS_NC ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_SBREL : Type = ELF :: R_<ISA_LIT>_MOVW_BREL_NC ; break ; } break ; case <STR_LIT> : switch ( Modifier ) { default : llvm_unreachable ( <STR_LIT> ) ; case MCSymbolRefExpr :: VK_None : Type = ELF :: R_<ISA_LIT>_THM_MOVT_ABS ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_SBREL : Type = ELF :: R_<ISA_LIT>_THM_MOVT_BREL ; break ; } break ; case <STR_LIT> : switch ( Modifier ) { default : llvm_unreachable ( <STR_LIT> ) ; case MCSymbolRefExpr :: VK_None : Type = ELF :: R_<ISA_LIT>_THM_MOVW_ABS_NC ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_SBREL : Type = ELF :: R_<ISA_LIT>_THM_MOVW_BREL_NC ; break ; } break ; } } return


<s> DecodeStatus status = DecodeOperandRegister ( Inst , s1_d , Address , Decoder ) ; if ( status != MCDisassembler :: Success ) return status ; return MCDisassembler


<s> SDValue <ISA_LIT>TargetLowering :: LowerBlockAddress ( SDValue Op , SelectionDAG & DAG ) const { unsigned char OpFlags = Subtarget -> ClassifyBlockAddressReference ( ) ; CodeModel :: Model M = getTargetMachine ( ) . getCodeModel ( ) ; const BlockAddress * BA = cast < BlockAddressSDNode > ( Op ) -> getBlockAddress ( ) ; int64_t Offset = cast < BlockAddressSDNode > ( Op ) -> getOffset ( ) ; SDLoc dl ( Op ) ; SDValue Result = DAG . getTargetBlockAddress ( BA , getPointerTy ( ) , Offset , OpFlags ) ; if ( Subtarget -> isPICStyleRIPRel ( ) && ( M == CodeModel :: Small || M == CodeModel :: Kernel ) ) Result =

DAG . getNode ( <STR_LIT> , dl , getPointerTy ( ) , Result ) ;


<s> return llvm :: make_unique < <ISA_LIT>MachObjectWriter > ( Is64Bit ,


<s> <ISA_LIT>Instr ( MCInst const * id , MCInst const * Extender , unsigned s , bool x = false ) : ID ( id ) , Extender ( Extender ) , Core ( s ) ,


<s> static void s390_override_options_after_change ( void ) { s390_default_align ( & global_options


<s> Constant * FSZero = Constant :: getNullValue ( LinkTy -> getPointerTo ( ) -> getPointerTo ( <NUM_LIT> ) ) ; Value * Next = Builder . CreateLoad ( FSZero ) ; Builder . CreateStore ( Next , Builder . CreateStructGEP ( LinkTy , Link , <NUM_LIT>


<s> bool <ISA_LIT>TTIImpl :: isLegalMaskedScatter ( Type * DataType , Align Alignment ) { if ( ! ST -> hasAVX512 ( )


<s> ScheduleDAGMI * DAG = createGenericSchedPostRA ( C ) ; const GCNSubtarget & ST = C -> MF -> getSubtarget < GCNSubtarget > ( ) ; DAG -> addMutation ( ST . createFillMFMAShadowMutation ( DAG ->


<s> const MCOperand & MO1 = MI . getOperand ( OpNum ) ; unsigned Value = <NUM_LIT> ; int32_t tmp = ( int32_t ) MO1 . getImm ( ) ; if ( tmp < <NUM_LIT> ) tmp = abs ( tmp ) ; else Value |=


<s> NodeAllocator ( uint32_t NPB = <NUM_LIT> ) : NodesPerBlock ( NPB ) , BitsPerIndex ( Log2_32 ( NPB ) ) , IndexMask ( ( <NUM_LIT> <<

BitsPerIndex ) - <NUM_LIT> ) , ActiveEnd ( nullptr ) {


<s> } assert ( ( ! RPI . isPaired ( ) || ( CSI [ i ] . getFrameIdx ( ) + <NUM_LIT> == CSI [ i + <NUM_LIT> ] . getFrameIdx ( ) ) ) && <STR_LIT> ) ; assert ( ( ! produceCompactUnwindFrame ( MF ) || CC == CallingConv :: PreserveMost || ( RPI . isPaired ( ) && ( ( RPI . Reg1 == <STR_LIT> && RPI . Reg2 == <STR_LIT> ) || RPI . Reg1 + <NUM_LIT> == RPI . Reg2 ) ) ) && <STR_LIT> ) ; RPI . FrameIdx = CSI [ i ] . getFrameIdx ( ) ; if ( Count * <NUM_LIT> != AFI -> getCalleeSavedStackSize ( ) && ! RPI . isPaired ( ) ) { Offset -= <NUM_LIT> ; assert ( MFI . getObjectAlignment ( RPI . FrameIdx ) <= <NUM_LIT> ) ; MFI . setObjectAlignment ( RPI . FrameIdx , <NUM_LIT> ) ; AFI -> setCalleeSaveStackHasFreeSpace ( true ) ; } else Offset -= RPI . isPaired ( ) ? <NUM_LIT> : <NUM_LIT> ; assert ( Offset % <NUM_LIT> == <NUM_LIT> ) ; RPI . Offset = Offset / <NUM_LIT> ; assert ( ( RPI . Offset >= - <NUM_LIT> && RPI . Offset <= <NUM_LIT> ) && <STR_LIT> ) ; RegPairs . push_back ( RPI ) ; if ( RPI . isPaired ( )


<s> const <ISA_LIT>Subtarget & Subtarget = DAG . getMachineFunction ( ) . getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( ConstantSDNode * ConstantSize = dyn_cast < ConstantSDNode > ( Size ) ) return emitConstantSizeRepmov ( DAG , Subtarget , dl , Chain , Dst , Src , ConstantSize -> getZExtValue ( ) , Size . getValueType ( ) , Alignment . value ( ) , isVolatile , AlwaysInline , DstPtrInfo , SrcPtrInfo ) ; return SDValue ( )


<s> if ( GET_CODE ( value ) == SYMBOL_REF && SYMBOL_REF_FUNCTION_P ( value ) ) { fputs ( <STR_LIT> , asm_out_file ) ; output_addr_const ( asm_out_file , value ) ; fputs ( <STR_LIT> , asm_out_file ) ; return true


<s> if ( GlobalVariable * GV = dyn_cast < GlobalVariable > ( V ) ) Globals . insert ( GV ) ; else { if ( User * U = dyn_cast < User > ( V ) ) { for ( unsigned i = <NUM_LIT> , e = U -> getNumOperands ( ) ; i != e ; ++ i ) { DiscoverDependentGlobals ( U -> getOperand ( i


<s> assert ( Op . getOpcode ( ) == <STR_LIT> && <STR_LIT> ) ; if ( ! isa < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) ) return SDValue ( ) ; EVT VT = Op . getOperand ( <NUM_LIT> ) . getValueType ( ) ; if ( VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> ) return Op ; if ( VT != <STR_LIT> && VT != <STR_LIT> && VT != <STR_LIT> && VT != <STR_LIT> && VT != <STR_LIT> ) return SDValue ( ) ; SDLoc DL ( Op


<s> return ( __m128i ) __builtin_ia32_vpdpbusd_v4si ( ( __v4si ) __A , (


<s> switch ( ClassID ) { default : llvm_unreachable ( <STR_LIT> ) ; return <STR_LIT> ; case GPRRC : return <STR_LIT> ; case FPRRC : return <STR_LIT> ; case VRRC : return <STR_LIT> ; case VSXRC : return


<s> <ISA_LIT>ABIFlagsSection & getABIFlagsSection ( ) { return


<s> int m16_simm8_8 ( rtx op , enum machine_mode mode ATTRIBUTE_UNUSED


<s> reportParseError ( <STR_LIT> ) ; return false ; } if ( Option == <STR_LIT> ) { getTargetStreamer ( ) . emitDirectiveModuleOddSPReg ( true , isABI_O32 ( ) ) ; clearFeatureBits ( <STR_LIT> , <STR_LIT> ) ; if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) { reportParseError ( <STR_LIT> ) ; return false ; } return false ; } else if ( Option == <STR_LIT> ) { if ( ! isABI_O32 ( ) ) { Error ( L , <STR_LIT> ) ; return false ; } getTargetStreamer ( ) . emitDirectiveModuleOddSPReg ( false , isABI_O32 ( ) ) ; setFeatureBits ( <STR_LIT> , <STR_LIT> ) ; if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) { reportParseError ( <STR_LIT> ) ; return false ; } return false ; } else if ( Option == <STR_LIT> ) { return parseDirectiveModuleFP (


<s> void EmitMappingSymbol ( StringRef Name ) { MCSymbol * Start = getContext ( ) . CreateTempSymbol ( ) ; EmitLabel ( Start ) ; MCSymbol * Symbol = getContext ( ) . GetOrCreateSymbol ( Name + <STR_LIT> + Twine ( MappingSymbolCounter ++ ) ) ; MCSymbolData & SD = getAssembler ( ) . getOrCreateSymbolData ( * Symbol ) ; MCELF :: SetType ( SD , ELF :: STT_NOTYPE ) ; MCELF :: SetBinding ( SD , ELF :: STB_LOCAL ) ; SD . setExternal ( false


<s> virtual bool trackLivenessAfterRegAlloc ( const MachineFunction & MF ) const { return true


<s> bool isLegalMaskedScatter ( Type * DataType


<s> void <ISA_LIT>InstPrinter :: printSystemPStateField ( const MCInst * MI , unsigned OpNo , raw_ostream & O ) { unsigned Val = MI -> getOperand ( OpNo ) . getImm ( ) ; bool Valid ; StringRef Name = <STR_LIT> ( ) . toString ( Val , Valid ) ; if ( Valid ) O << StringRef ( Name . str ( ) ) . upper ( ) ; else O << <STR_LIT>