<s> for ( MachineBasicBlock :: iterator I = MBB . begin ( ) , IE = MBB . end ( ) ; I != IE ; ) { MachineInstr & MI = * I ; if ( MI . getOpcode ( ) != <STR_LIT> && MI . getOpcode ( ) != <STR_LIT> && MI . getOpcode ( ) != <STR_LIT> && MI . getOpcode ( ) != <STR_LIT> ) { if ( MI . getOpcode ( ) == <STR_LIT> ) NeedFence = false ; else if ( MI . getOpcode ( ) == <STR_LIT> ) NeedFence = true ; ++ I ; continue ; } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << MI ) ; unsigned OutReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned InReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; DebugLoc DL = MI . getDebugLoc ( ) ; unsigned GPR3 = Is64Bit ? <STR_LIT> : <STR_LIT> ; unsigned Opc1 , Opc2 ; const unsigned OrigRegs [ ] = { OutReg , InReg , GPR3 } ; switch ( MI . getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : Opc1 = <STR_LIT> ; Opc2 = <STR_LIT> ; break ; case <STR_LIT> : Opc1 = <STR_LIT> ; Opc2 = <STR_LIT> ; break ; case <STR_LIT> : Opc1 = <STR_LIT> ; Opc2 = <STR_LIT> ; break ; case <STR_LIT> : Opc1 = <STR_LIT> ; Opc2 = <STR_LIT> ; break ; } if ( NeedFence ) BuildMI ( MBB , I , DL , TII -> get ( <STR_LIT> ) ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; MachineInstr * Addi = BuildMI ( MBB , I , DL , TII -> get ( Opc1 ) , GPR3 ) . addReg ( InReg ) ; Addi -> addOperand ( MI . getOperand ( <NUM_LIT> ) ) ; MachineBasicBlock :: iterator First


<s> } else if ( <STR_LIT> . contains ( SrcReg ) ) { if ( <STR_LIT> . contains ( DestReg ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg ) ) Opc = <STR_LIT> , DestReg = <NUM_LIT> ; else if ( <STR_LIT> . contains ( DestReg ) ) Opc = <STR_LIT> , DestReg = <NUM_LIT> ; else if ( <STR_LIT> . contains ( DestReg ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) . addImm ( <NUM_LIT> << <NUM_LIT> ) . addReg ( DestReg , RegState :: ImplicitDefine ) ; return ; } else if ( <STR_LIT> . contains ( DestReg ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addReg ( DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; return ; } } else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg ) ) { if ( <STR_LIT> . contains ( SrcReg ) ) Opc = <STR_LIT> , ZeroReg = <STR_LIT> ; else if ( <STR_LIT> . contains ( SrcReg ) ) Opc = <STR_LIT> , SrcReg = <NUM_LIT> ; else if ( <STR_LIT> . contains ( SrcReg ) ) Opc = <STR_LIT> , SrcReg = <NUM_LIT> ; else if ( <STR_LIT> . contains ( SrcReg ) ) Opc = <STR_LIT> ; } else if ( <STR_LIT> . contains ( SrcReg ) ) { if ( <STR_LIT> . contains ( DestReg ) ) Opc = <STR_LIT> , DestReg = <NUM_LIT> ; else if ( <STR_LIT> . contains ( DestReg ) ) Opc = <STR_LIT> , DestReg = <NUM_LIT> ; else if ( <STR_LIT> . contains ( DestReg ) ) Opc = <STR_LIT> ; } else if ( <STR_LIT> . contains ( DestReg ) ) { if ( <STR_LIT> . contains ( SrcReg ) ) Opc = <STR_LIT> ; } assert ( Opc && <STR_LIT> ) ; MachineInstrBuilder MIB = BuildMI ( MBB , I , DL ,


<s> return __builtin_mve_vcvttq_m_f32_f16v4sf ( __arm_vuninitializedq_f32 ( ) , __a ,


<s> bool intersects ( const RegisterSet & Rs ) const { return Bits . anyCommon ( Rs .


<s> static SDValue LowerDIV ( SDValue Op , SelectionDAG & DAG ) { assert ( Op . getOpcode ( ) == <STR_LIT> || Op . getOpcode ( ) == <STR_LIT> ) ; EVT VT = Op . getValueType ( ) ; if ( ( VT != <STR_LIT> ) && ( VT != <STR_LIT> ) ) return SDValue ( ) ; SDLoc DL ( Op ) ; bool isSigned = Op . getOpcode ( ) == <STR_LIT> ; unsigned ExtHiOpc = isSigned ? <STR_LIT> : <STR_LIT> ; unsigned ExtLoOpc = isSigned ? <STR_LIT> : <STR_LIT> ; unsigned MaxFactor = VT . getVectorNumElements ( ) / <NUM_LIT> ; SmallVector < SDValue , <NUM_LIT> > Res ( MaxFactor ) ; SmallVector < SDValue , <NUM_LIT> > Op0 ( MaxFactor ) ; SmallVector < SDValue , <NUM_LIT> > Op1 ( MaxFactor ) ; unsigned Factors = <NUM_LIT> ; Op0 [ <NUM_LIT> ] = Op . getOperand ( <NUM_LIT> ) ; Op1 [ <NUM_LIT> ] = Op . getOperand ( <NUM_LIT> ) ; for ( ; Factors < MaxFactor ; Factors *= <NUM_LIT> ) { VT = getDoubleWidthHalfCountVectorVT ( DAG , VT ) ; for ( unsigned i = Factors ; i > <NUM_LIT> ; -- i ) { Op0 [ <NUM_LIT> * i - <NUM_LIT> ] = DAG . getNode ( ExtHiOpc , DL , VT , Op0 [ i - <NUM_LIT> ] ) ; Op0 [ <NUM_LIT> * i - <NUM_LIT> ] = DAG . getNode ( ExtLoOpc , DL , VT , Op0 [ i - <NUM_LIT> ] ) ; Op1 [ <NUM_LIT> * i - <NUM_LIT> ] = DAG . getNode ( ExtHiOpc , DL , VT


<s> if ( ! s390_decompose_address ( addr , & ad ) || ( ad . base && ! REGNO_OK_FOR_BASE_P ( REGNO ( ad . base ) ) ) || ( ad . indx && ! REGNO_OK_FOR_INDEX_P ( REGNO ( ad . indx ) ) ) ) output_operand_lossage ( <STR_LIT> ) ; if ( ad . disp ) output_addr_const ( file , ad .


<s> FunctionPass * llvm :: create<ISA_LIT>MemIntrinsicResults ( ) { return new <ISA_LIT>MemIntrinsicResults (


<s> return RegIdx . RegInfo -> getRegClass ( ClassID


<s> const MachineOperand * Mods = getNamedOperand


<s> void printanymem ( const MCInst * MI , unsigned OpNo , raw_ostream & O ) { printMemReference ( MI , OpNo , O


<s> return Kind == Memory && ( ! Mem . Size || Mem .


<s> if ( lFromVEX2of2 ( insn -> vexPrefix [ <NUM_LIT> ] ) ) attrMask |= ATTR_VEXL ; } else { return - <NUM_LIT> ; } } else { if ( insn -> rexPrefix & <NUM_LIT> ) attrMask |= ATTR_REXW ; if ( isPrefixAtLocation ( insn , <NUM_LIT> , insn -> necessaryPrefixLocation ) ) attrMask |= ATTR_OPSIZE ; else if ( isPrefixAtLocation ( insn , <NUM_LIT> , insn -> necessaryPrefixLocation ) ) attrMask |= ATTR_XS ; else if ( isPrefixAtLocation ( insn , <NUM_LIT> , insn -> necessaryPrefixLocation ) ) attrMask |= ATTR_XD ; } if ( getIDWithAttrMask ( & instructionID , insn , attrMask ) ) return - <NUM_LIT> ; if ( ( attrMask & ATTR_XD ) && ( attrMask & ATTR_REXW ) ) { const struct InstructionSpecifier * spec ; uint16_t instructionIDWithREXw ; const struct InstructionSpecifier * specWithREXw ; spec = specifierForUID ( instructionID ) ; if ( getIDWithAttrMask ( & instructionIDWithREXw , insn , attrMask & ( ~ ATTR_XD ) ) ) { insn -> instructionID = instructionID ; insn -> spec = spec ; return <NUM_LIT> ; } specWithREXw = specifierForUID ( instructionIDWithREXw ) ; if ( is64BitEquivalent ( spec -> name , specWithREXw -> name ) ) { insn -> instructionID = instructionIDWithREXw ; insn -> spec = specWithREXw ; } else { insn -> instructionID = instructionID ; insn -> spec = spec ; } return <NUM_LIT> ; } if ( insn -> prefixPresent [ <NUM_LIT> ] && ! ( attrMask & ATTR_OPSIZE ) ) { const struct InstructionSpecifier * spec ; uint16_t instructionIDWithOpsize ; const struct InstructionSpecifier * specWithOpsize ; spec = specifierForUID ( instructionID ) ; if ( getIDWithAttrMask ( & instructionIDWithOpsize , insn , attrMask | ATTR_OPSIZE ) ) { insn -> instructionID = instructionID ; insn -> spec =


<s> __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> (


<s> switch ( insn . eaBase ) { case EA_BASE_NONE : llvm_unreachable ( <STR_LIT> ) ; break ; ALL_EA_BASES llvm_unreachable ( <STR_LIT> <STR_LIT> ) ; break ; case EA_REG_ ## x : \ mcInst . addOperand ( MCOperand :: CreateReg ( <STR_LIT> ) ) ; break ; ALL_REGS default


<s> int EdgeVal = ( * E . getCurrent ( ) ) . getValue


<s> static bool mips_far_type_p ( const_tree type ) { return ( lookup_attribute ( <STR_LIT> , TYPE_ATTRIBUTES ( type ) ) != NULL || lookup_attribute (

<STR_LIT> , TYPE_ATTRIBUTES ( type ) ) != NULL ) ;


<s> const TargetFrameLowering * TFI = MF . getTarget ( ) . getFrameLowering ( ) ; if ( TFI -> hasFP ( MF ) ) { Reserved . set ( <STR_LIT> ) ; Reserved . set


<s> auto Res = std :: make_unique < <ISA_LIT>Operand > (


<s> SDValue <ISA_LIT>TargetLowering :: LowerEXTRACT_SUBVECTOR_HVX ( SDValue Op , SelectionDAG & DAG ) const { EVT VT = Op . getOperand ( <NUM_LIT> ) . getValueType ( ) ; SDLoc dl ( Op ) ; bool UseHVX = Subtarget . useHVXOps ( ) ; bool UseHVXSgl = Subtarget . useHVXSglOps ( ) ; if ( ! VT . isVector ( ) || ! UseHVX ) return SDValue ( ) ; EVT ResVT = Op . getValueType ( ) ; unsigned ResSize = ResVT . getSizeInBits ( ) ; unsigned VectorSizeInBits = UseHVXSgl ? ( <NUM_LIT> * <NUM_LIT> ) : ( <NUM_LIT> * <NUM_LIT> ) ; unsigned OpSize = VT . getSizeInBits ( ) ; if ( ! ( ResVT . isByteSized ( ) && ResSize == VectorSizeInBits ) || ! ( VT . isByteSized ( ) && OpSize == <NUM_LIT> * VectorSizeInBits ) ) return SDValue ( ) ; ConstantSDNode * Cst = dyn_cast < ConstantSDNode > (


<s> return ! ( A -> mayStore ( ) || B -> mayStore ( ) ) || !


<s> static int n_pregs_to_save ( bool is_inthandler , bool consecutive ) { int count = <NUM_LIT> ; unsigned


<s> iq2000_annotate_frame_insn ( emit_move_insn ( mem , reg ) , gen_rtx_SET ( GET_MODE (


<s> decl = exp ; } else { type = exp ; decl = NULL ; } if ( ! TARGET_64BIT && align == <NUM_LIT> && ix86_preferred_stack_boundary < <NUM_LIT> && ( mode == DImode || ( type && TYPE_MODE ( type ) == DImode ) ) && ( ! type || ! TYPE_USER_ALIGN ( type ) ) && ( ! decl || ! DECL_USER_ALIGN ( decl ) ) ) align = <NUM_LIT> ; if ( ! type ) { if ( mode == XFmode && align < GET_MODE_ALIGNMENT ( DFmode ) ) align = GET_MODE_ALIGNMENT ( DFmode ) ; return align ; } if ( TARGET_IAMCU ) return align ; if ( TARGET_64BIT && optimize_function_for_speed_p ( cfun ) && TARGET_SSE ) { if ( AGGREGATE_TYPE_P ( type ) && ( va_list_type_node == NULL_TREE || ( TYPE_MAIN_VARIANT ( type ) != TYPE_MAIN_VARIANT ( va_list_type_node ) ) ) && TYPE_SIZE ( type ) && TREE_CODE ( TYPE_SIZE ( type ) ) == INTEGER_CST && wi :: geu_p ( TYPE_SIZE ( type ) , <NUM_LIT> ) && align < <NUM_LIT> ) return <NUM_LIT> ; } if ( TREE_CODE ( type ) == ARRAY_TYPE ) { if ( TYPE_MODE ( TREE_TYPE ( type ) ) == DFmode && align < <NUM_LIT> ) return <NUM_LIT> ; if ( ALIGN_MODE_128 ( TYPE_MODE ( TREE_TYPE ( type ) ) ) && align < <NUM_LIT> ) return <NUM_LIT> ; } else if ( TREE_CODE ( type ) == COMPLEX_TYPE ) { if ( TYPE_MODE ( type ) == DCmode && align < <NUM_LIT> ) return <NUM_LIT> ; if ( ( TYPE_MODE ( type ) == XCmode || TYPE_MODE ( type ) == TCmode ) && align < <NUM_LIT> ) return <NUM_LIT> ; } else if ( ( TREE_CODE ( type ) == RECORD_TYPE || TREE_CODE ( type ) == UNION_TYPE || TREE_CODE ( type ) == QUAL_UNION_TYPE ) && TYPE_FIELDS ( type ) ) { if ( DECL_MODE ( TYPE_FIELDS ( type ) ) == DFmode && align < <NUM_LIT> ) return <NUM_LIT> ; if ( ALIGN_MODE_128 ( DECL_MODE ( TYPE_FIELDS ( type ) ) )


<s> case <STR_LIT> : return EmitLoweredSelect ( MI , BB ) ; case <STR_LIT> : return EmitLoweredSegAlloca ( MI ,


<s> MachineInstrBuilder MIB = BuildMI ( MBB , MBBI , MI . getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . add ( MI . getOperand ( <NUM_LIT> ) ) . addReg ( <STR_LIT> ) . addImm ( Encoding ) ; const unsigned DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; const bool DstIsDead = MI . getOperand ( <NUM_LIT> ) . isDead ( ) ; unsigned ShiftAmt = <NUM_LIT> ; uint64_t Imm16 = <NUM_LIT> ; for ( ; ShiftAmt < <NUM_LIT> ; ShiftAmt += <NUM_LIT> ) { Imm16 = ( UImm >> ShiftAmt ) & <NUM_LIT> ; if ( Imm16 != ChunkVal ) break ; } MachineInstrBuilder MIB1 = BuildMI ( MBB , MBBI , MI . getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addReg ( DstReg , RegState :: Define | getDeadRegState ( DstIsDead && CountThree ) ) . addReg ( DstReg ) . addImm ( Imm16 ) . addImm ( <STR_LIT>


<s> bool IsCall = In . isCall ( ) , IsReturn = In . isReturn ( ) ; bool IsPredicated = TII . isPredicated ( & In ) ; unsigned NumOps = In . getNumOperands ( ) ; RegisterSet DoneDefs ; for ( unsigned OpN = <NUM_LIT> ; OpN < NumOps ; ++ OpN ) { MachineOperand & Op = In . getOperand ( OpN ) ; if ( ! Op . isReg ( ) || ! Op . isDef ( ) || Op . isImplicit ( ) ) continue ; RegisterRef RR = { Op . getReg ( ) , Op . getSubReg ( ) } ; uint16_t Flags = NodeAttrs :: None ; if ( TOI . isPreserving ( In , OpN ) ) Flags |= NodeAttrs :: Preserving ; if ( TOI . isClobbering ( In , OpN ) ) Flags |= NodeAttrs :: Clobbering ; if ( TOI . isFixedReg ( In , OpN ) ) Flags |= NodeAttrs :: Fixed ; NodeAddr < DefNode * > DA = newDef ( SA , Op , Flags ) ; SA . Addr -> addMember ( DA , * this ) ; DoneDefs . insert ( RR ) ; } for ( unsigned OpN = <NUM_LIT> ; OpN < NumOps ; ++ OpN ) { MachineOperand & Op = In . getOperand ( OpN ) ; if ( ! Op . isReg ( ) || ! Op . isDef ( ) || ! Op . isImplicit ( ) ) continue ; RegisterRef RR = { Op . getReg ( ) , Op . getSubReg ( ) } ; if ( ! IsCall && ! ImpDefs . count ( RR ) ) continue ; if ( DoneDefs . count ( RR ) ) continue ; uint16_t Flags = NodeAttrs :: None ; if ( TOI . isPreserving ( In , OpN ) ) Flags |= NodeAttrs :: Preserving ; if ( TOI . isClobbering ( In , OpN ) ) Flags |= NodeAttrs :: Clobbering ; if ( TOI . isFixedReg ( In , OpN ) ) Flags |= NodeAttrs :: Fixed ; NodeAddr < DefNode * > DA = newDef ( SA , Op , Flags ) ; SA . Addr -> addMember ( DA , * this ) ; DoneDefs . insert ( RR ) ; } for ( unsigned OpN = <NUM_LIT> ; OpN < NumOps ; ++ OpN ) { MachineOperand & Op = In . getOperand ( OpN ) ; if ( ! Op . isReg ( ) || ! Op . isUse ( ) ) continue ; RegisterRef RR = { Op . getReg ( ) , Op . getSubReg ( ) } ; bool Implicit = Op . isImplicit ( ) ; bool TakeImplicit = IsReturn || IsCall || IsPredicated ; if ( Implicit && ! TakeImplicit && ! ImpUses . count ( RR ) ) continue ; uint16_t Flags = NodeAttrs


<s> Len /= <NUM_LIT> ; Idx /= <NUM_LIT> ; for ( int i = <NUM_LIT> ; i != Len ; ++ i ) ShuffleMask . push_back ( i + Idx ) ; for ( int i = Len ; i != <NUM_LIT> ; ++

i ) ShuffleMask . push_back ( SM_SentinelZero ) ;


<s> return new <ISA_LIT>DAGToDAGISel ( TM


<s> static int rs6000_hard_regno_mode_ok ( int regno , enum machine_mode mode ) { if ( INT_REGNO_P ( regno ) ) return INT_REGNO_P ( regno + HARD_REGNO_NREGS ( regno , mode ) - <NUM_LIT> ) ; if ( FP_REGNO_P ( regno ) ) return ( GET_MODE_CLASS ( mode ) == MODE_FLOAT && FP_REGNO_P ( regno + HARD_REGNO_NREGS ( regno , mode ) - <NUM_LIT> ) ) || ( GET_MODE_CLASS ( mode ) == MODE_INT && GET_MODE_SIZE ( mode ) == UNITS_PER_FP_WORD ) ; if ( CR_REGNO_P ( regno ) ) return GET_MODE_CLASS ( mode ) == MODE_CC ; if ( XER_REGNO_P ( regno ) ) return mode == PSImode ; if ( ALTIVEC_REGNO_P ( regno ) ) return ALTIVEC_VECTOR_MODE


<s> case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT>


<s> static DecodeStatus DecodeGPR32RegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t Address , const MCDisassembler * Decoder ) { if ( RegNo > <NUM_LIT> ) return MCDisassembler :: Fail ; unsigned Reg = getReg ( Decoder , <STR_LIT> , RegNo ) ; Inst . addOperand ( MCOperand :: createReg (


<s> static void EmitComment ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI , DebugLoc dl , const <ISA_LIT>ompactInstrInfo & TII , std :: string Comment ) { MDNode * CommentMDNode = MDNode :: get ( getGlobalContext ( ) , ArrayRef < Value * > ( MDString :: get ( getGlobalContext ( ) , Comment ) ) ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) ) . addMetadata (


<s> static bool ix86_macro_fusion_pair_p ( rtx_insn * condgen , rtx_insn * condjmp ) { rtx src , dest ; enum rtx_code ccode ; rtx compare_set = NULL_RTX , test_if , cond ; rtx alu_set = NULL_RTX , addr = NULL_RTX ; if ( ! any_condjump_p ( condjmp ) ) return false ; if ( get_attr_type ( condgen ) != TYPE_TEST && get_attr_type ( condgen ) != TYPE_ICMP && get_attr_type ( condgen ) != TYPE_INCDEC && get_attr_type ( condgen ) != TYPE_ALU ) return false ; compare_set = single_set ( condgen ) ; if ( compare_set == NULL_RTX && ! TARGET_FUSE_ALU_AND_BRANCH ) return false ; if ( compare_set == NULL_RTX ) { int i ; rtx pat = PATTERN ( condgen ) ; for ( i = <NUM_LIT> ; i < XVECLEN ( pat , <NUM_LIT> ) ; i ++ ) if ( GET_CODE ( XVECEXP ( pat , <NUM_LIT> , i ) ) == SET ) { rtx set_src = SET_SRC ( XVECEXP ( pat , <NUM_LIT> , i ) ) ; if ( GET_CODE ( set_src ) == COMPARE ) compare_set = XVECEXP ( pat , <NUM_LIT> , i ) ; else alu_set = XVECEXP ( pat , <NUM_LIT> , i ) ; } } if ( compare_set == NULL_RTX ) return false ; src = SET_SRC ( compare_set ) ; if ( GET_CODE ( src ) != COMPARE ) return false ; if ( ( MEM_P ( XEXP ( src , <NUM_LIT> ) ) && CONST_INT_P ( XEXP ( src , <NUM_LIT> ) ) ) || ( MEM_P ( XEXP ( src , <NUM_LIT> ) ) && CONST_INT_P ( XEXP ( src , <NUM_LIT> ) ) ) ) return false ; if ( MEM_P ( XEXP ( src , <NUM_LIT> ) ) ) addr = XEXP ( XEXP ( src , <NUM_LIT> ) , <NUM_LIT> ) ; else if ( MEM_P ( XEXP ( src , <NUM_LIT> ) ) ) addr = XEXP ( XEXP ( src , <NUM_LIT> ) , <NUM_LIT> ) ; if ( addr ) { ix86_address parts ; int ok = ix86_decompose_address ( addr , & parts ) ; gcc_assert ( ok ) ; if ( rip_relative_addr_p ( & parts ) ) return false ; } test_if = SET_SRC ( pc_set ( condjmp ) ) ; cond = XEXP ( test_if , <NUM_LIT> ) ; ccode = GET_CODE ( cond ) ; if ( ! TARGET_FUSE_CMP_AND_BRANCH_SOFLAGS && ( ccode == GE || ccode == GT || ccode == LE || ccode == LT ) ) return false ; if ( get_attr_type ( condgen ) == TYPE_TEST || get_attr_type ( condgen ) == TYPE_ICMP ) return true ; if ( ! TARGET_FUSE_ALU_AND_BRANCH || ! alu_set ) return false ; dest = SET_DEST ( alu_set ) ; if ( MEM_P ( dest ) ) return false ; if ( get_attr_type ( condgen ) == TYPE_INCDEC && ( ccode == GEU || ccode == GTU || ccode == LEU


<s> const Value * SV = cast < SrcValueSDNode > ( op . getOperand ( <NUM_LIT> ) ) -> getValue ( ) ; return DAG . getStore ( op . getOperand ( <NUM_LIT> ) , op . getDebugLoc ( ) , Chain , op . getOperand ( <NUM_LIT> ) , MachinePointerInfo (


<s> pat = vec_sel ( ( ( vec_uchar16 ) { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) , vec_sr ( ( vec_uchar16 ) ( pattern ) , vec_splat_u8 ( <NUM_LIT> ) ) , vec_sra ( ( vec_uchar16 ) ( pattern ) , vec_splat_u8 ( <NUM_LIT> ) ) ) ; return ( ( qword ) ( vec_perm ( vec_perm ( a , b , pattern ) , ( ( vec_uchar16 ) { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> ,

<NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) , pat ) ) ) ;


<s> Optional < MCFixupKind > ELF<ISA_LIT>AsmBackend :: getFixupKind ( StringRef Name ) const { if ( TT . is<ISA_LIT>64 ( )


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . addRequired < TargetPassConfig > (


<s> MCInst Inst ; if ( MatchInstructionImpl ( Operands , Inst , ErrorInfo , MatchingInlineAsm ) ) { Out . EmitInstruction ( Inst ,


<s> switch ( code ) { case LE : case LEU : case GT : case GTU : std :: swap ( lo [ <NUM_LIT> ] , lo [ <NUM_LIT> ] ) ; std :: swap ( hi [ <NUM_LIT> ] , hi [ <NUM_LIT> ] ) ; code = swap_condition ( code ) ; case LT : case LTU : case GE : case GEU : { bool uns = ( code == LTU || code == GEU ) ; rtx ( * sbb_insn ) ( machine_mode , rtx , rtx , rtx ) = uns ? gen_sub3_carry_ccc : gen_sub3_carry_ccgz ; if ( ! nonimmediate_operand ( lo [ <NUM_LIT> ] , submode ) ) lo [ <NUM_LIT> ] = force_reg ( submode , lo [ <NUM_LIT> ] ) ; if ( ! x86_64_general_operand ( lo [ <NUM_LIT> ] , submode ) ) lo [ <NUM_LIT> ] = force_reg ( submode , lo [ <NUM_LIT> ] ) ; if ( ! register_operand ( hi [ <NUM_LIT> ] , submode ) ) hi [ <NUM_LIT> ] = force_reg ( submode , hi [ <NUM_LIT> ] ) ; if ( ( uns && ! nonimmediate_operand ( hi [ <NUM_LIT> ] , submode ) ) || ( ! uns && ! x86_64_general_operand ( hi [ <NUM_LIT> ] , submode ) ) ) hi [ <NUM_LIT> ] = force_reg ( submode , hi [ <NUM_LIT> ] ) ; emit_insn ( gen_cmp_1 ( submode , lo [ <NUM_LIT> ] , lo [ <NUM_LIT> ] ) ) ; tmp = gen_rtx_SCRATCH ( submode ) ; emit_insn ( sbb_insn ( submode , tmp , hi [ <NUM_LIT> ] , hi [ <NUM_LIT> ] ) ) ; tmp = gen_rtx_REG ( uns ? CCCmode : CCGZmode , FLAGS_REG ) ; ix86_expand_branch ( code , tmp , const0_rtx , label ) ; return ; } default : break ; } label2 = gen_label_rtx ( ) ; code1 = code ; code2 = swap_condition ( code ) ; code3 = unsigned_condition ( code ) ; switch ( code ) { case LT : case GT : case LTU : case GTU : break ; case LE : code1 = LT ; code2 = GT ; break ; case GE : code1 = GT ; code2 = LT ; break ; case LEU : code1 = LTU ; code2 = GTU ; break ; case GEU : code1 = GTU ; code2 = LTU ; break ; case EQ : code1 = UNKNOWN ; code2 = NE ; break ; case NE : code2 = UNKNOWN ; break ; default : gcc_unreachable ( ) ; } if ( code1 != UNKNOWN ) ix86_expand_branch ( code1 , hi [ <NUM_LIT> ] , hi [ <NUM_LIT> ] , label ) ; if ( code2 != UNKNOWN ) ix86_expand_branch ( code2 , hi [ <NUM_LIT> ] , hi [ <NUM_LIT> ] , label2 ) ; ix86_expand_branch ( code3 , lo [ <NUM_LIT> ]


<s> unsigned Shift1Reg = RegInfo . createVirtualRegister ( RC ) ; unsigned ShiftReg = RegInfo . createVirtualRegister ( RC ) ; unsigned Incr2Reg = RegInfo . createVirtualRegister ( RC ) ; unsigned MaskReg = RegInfo . createVirtualRegister ( RC ) ; unsigned Mask2Reg = RegInfo . createVirtualRegister ( RC ) ; unsigned Mask3Reg = RegInfo . createVirtualRegister ( RC ) ; unsigned Tmp2Reg = RegInfo . createVirtualRegister ( RC ) ; unsigned Tmp3Reg = RegInfo . createVirtualRegister ( RC ) ; unsigned Tmp4Reg = RegInfo . createVirtualRegister ( RC ) ; unsigned TmpDestReg = RegInfo . createVirtualRegister ( RC ) ; unsigned Ptr1Reg ; unsigned TmpReg = ( ! BinOpcode ) ? Incr2Reg : RegInfo . createVirtualRegister ( RC ) ; BB -> addSuccessor ( loopMBB ) ; if ( ptrA != ZeroReg ) { Ptr1Reg = RegInfo . createVirtualRegister ( RC ) ; BuildMI ( BB , dl , TII -> get ( is64bit ? <STR_LIT> : <STR_LIT> ) , Ptr1Reg ) . addReg ( ptrA ) . addReg ( ptrB ) ; } else { Ptr1Reg = ptrB ; } BuildMI ( BB , dl , TII -> get ( <STR_LIT> ) , Shift1Reg ) . addReg ( Ptr1Reg ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( is8bit ? <NUM_LIT> : <NUM_LIT> ) ; BuildMI ( BB , dl , TII -> get ( is64bit ? <STR_LIT> : <STR_LIT> ) , ShiftReg ) . addReg ( Shift1Reg ) . addImm ( is8bit ? <NUM_LIT> : <NUM_LIT> ) ; if ( is64bit ) BuildMI ( BB , dl , TII -> get ( <STR_LIT> ) , PtrReg ) . addReg ( Ptr1Reg ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; else BuildMI ( BB , dl , TII -> get ( <STR_LIT> ) , PtrReg ) . addReg ( Ptr1Reg ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; BuildMI ( BB , dl , TII -> get ( <STR_LIT> ) , Incr2Reg ) . addReg ( incr ) . addReg ( ShiftReg ) ; if ( is8bit ) BuildMI ( BB , dl , TII -> get ( <STR_LIT> ) , Mask2Reg ) . addImm ( <NUM_LIT> ) ; else { BuildMI ( BB , dl , TII -> get ( <STR_LIT> ) , Mask3Reg ) . addImm ( <NUM_LIT> ) ; BuildMI ( BB , dl , TII -> get ( <STR_LIT> ) , Mask2Reg ) . addReg ( Mask3Reg ) . addImm ( <NUM_LIT> ) ; } BuildMI ( BB , dl , TII -> get ( <STR_LIT> ) ,

MaskReg ) . addReg ( Mask2Reg ) . addReg ( ShiftReg ) ;


<s> void EmitDataMappingSymbol ( ) { if ( LastEMS == EMS_Data ) return ; EmitMappingSymbol ( <STR_LIT> ) ; LastEMS =


<s> assert ( MOImm8 . isImm ( ) && <STR_LIT> ) ; uint32_t Imm8 = MOImm8 . getImm ( ) ; uint32_t Fraction = Imm8 & <NUM_LIT> ; uint32_t Exponent = ( Imm8 >> <NUM_LIT> ) & <NUM_LIT> ; uint32_t Negative = ( Imm8 >> <NUM_LIT> ) & <NUM_LIT> ; float Val = <NUM_LIT> + Fraction / <NUM_LIT> ; if ( Exponent & <NUM_LIT> ) { Val /= <NUM_LIT> << ( <NUM_LIT> - Exponent ) ; } else


<s> if ( PrevElt ) { int64_t Diff = SignExtend64 ( Val - PrevElt -> first , EltSizeInBits ) ; if ( Diff % ( Idx - PrevElt -> second ) != <NUM_LIT> ) return None ; int64_t Step = Diff / ( Idx - PrevElt -> second ) ; if ( Step == <NUM_LIT> ) return None ; if ( ! SeqStep ) SeqStep = Step ; else if ( Step != SeqStep ) return None ; } if ( SeqStep ) { int64_t Addend = SignExtend64 ( Val - ( Idx * ( uint64_t ) * SeqStep ) , EltSizeInBits ) ; if ( ! SeqAddend ) SeqAddend = Addend ; else if ( SeqAddend != Addend ) return None ; } PrevElt = std :: make_pair ( Val


<s> CCRetInfo . AnalyzeCallResult ( Ins , RetCC_<ISA_LIT> ) ; for ( unsigned i = <NUM_LIT> , e = RVLocs . size ( ) ; i != e ; ++ i ) { CCValAssign & VA = RVLocs [ i ] ; assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; SDValue Val = DAG . getCopyFromReg ( Chain , dl , VA . getLocReg ( ) , VA . getLocVT ( ) , InFlag ) ; Chain = Val . getValue ( <NUM_LIT> ) ; InFlag = Val . getValue ( <NUM_LIT> ) ; switch ( VA . getLocInfo ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case CCValAssign :: Full : break ; case CCValAssign :: AExt : Val = DAG . getNode ( <STR_LIT> , dl , VA . getValVT ( ) , Val ) ; break ; case CCValAssign :: ZExt : Val = DAG . getNode ( <STR_LIT> , dl , VA . getLocVT ( ) , Val , DAG . getValueType ( VA . getValVT ( ) ) ) ; Val = DAG . getNode ( <STR_LIT> , dl , VA . getValVT ( ) , Val ) ; break ; case CCValAssign


<s> bool <ISA_LIT>DAGToDAGISel :: SelectPred ( SDValue N , SDValue & Reg , SDValue & Inv ) { SDLoc dl ( N ) ; if ( ConstantSDNode * Imm = dyn_cast < ConstantSDNode >


<s> <ISA_LIT>AsmParser ( const MCSubtargetInfo & STI , MCAsmParser & Parser , const MCInstrInfo & MII , const MCTargetOptions & Options ) : MCTargetAsmParser ( Options , STI , MII ) , Parser ( Parser ) , Lexer ( Parser . getLexer ( ) ) , is64 ( STI . getTargetTriple ( ) . isArch64Bit ( ) ) , TC ( Parser , MII , is64 ) , SkipTypeCheck ( Options . MCNoTypeCheck ) { setAvailableFeatures ( ComputeAvailableFeatures ( STI . getFeatureBits ( ) ) ) ; auto & SM = Parser . getSourceManager ( ) ; auto BufferName = SM . getBufferInfo ( SM . getMainFileID ( ) ) . Buffer


<s> if ( replaced_dots ) name = replaced_dots ; } if ( name [ <NUM_LIT> ] == '*' ) name ++ ; if ( is_defn ) write_fn_proto_1 ( s , false ,


<s> <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; int FrameIndex = StoreByValRegs ( CCInfo , DAG , dl , Chain , <NUM_LIT> , CCInfo . getInRegsParamsCount ( ) , <NUM_LIT> , ArgOffset , ForceMutable ) ; AFI -> setVarArgsFrameIndex (


<s> const MCOperand & MO = MI -> getOperand ( OpNo ) ; if ( MO . isReg ( ) ) { printRegName ( O , MO . getReg ( ) ) ; } else if ( MO . isExpr ( ) ) { MO . getExpr ( ) -> print


<s> fprintf ( asm_out_file , <STR_LIT> ) ; for ( int i = <NUM_LIT> ; i < pool_size ; i ++ ) { pool_node * p = & pool_vector [ i ] ; ( * targetm . asm_out . internal_label ) ( asm_out_file , <STR_LIT> , CODE_LABEL_NUMBER ( p -> label ) ) ; output_asm_insn ( <STR_LIT> , & p -> value ) ; } pool_size = <NUM_LIT> ; } return <STR_LIT>


<s> struct expand_vec_perm_d d ; rtx t1 ; bool ok ; if ( elt != const0_rtx ) elt = force_reg ( GET_MODE_INNER ( vmode ) , elt ) ; if ( REG_P ( elt ) ) elt = gen_lowpart ( DImode , elt ) ; t1 = gen_reg_rtx ( vmode ) ; switch ( vmode ) { case


<s> const <ISA_LIT>RegisterInfo * TRI = ST . getRegisterInfo ( ) ; MachineFrameInfo & FrameInfo = MF . getFrameInfo ( ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; unsigned WaveSize = ST . getWavefrontSize ( ) ; unsigned Size = FrameInfo . getObjectSize ( FI ) ; unsigned NumLanes = Size / <NUM_LIT> ; if ( NumLanes > WaveSize ) return false ; assert ( Size >= <NUM_LIT> && <STR_LIT> ) ; assert ( TRI -> spillSGPRToVGPR ( ) && <STR_LIT> ) ; for ( unsigned I = <NUM_LIT> ; I < NumLanes ; ++ I , ++ NumVGPRSpillLanes ) { Register LaneVGPR ; unsigned VGPRIndex = ( NumVGPRSpillLanes % WaveSize ) ; if ( VGPRIndex == <NUM_LIT> ) { LaneVGPR = TRI -> findUnusedRegister ( MRI , & <STR_LIT> , MF ) ; if ( LaneVGPR ==


<s> else base = high ? high_base : low_base ; for ( i = <NUM_LIT> ; i < nunits / <NUM_LIT> ; i ++ ) RTVEC_ELT ( v , i ) = GEN_INT ( base


<s> virtual uint64_t getMachineOpValue ( const MCInst & MI , const MCOperand & MO , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { return <NUM_LIT>


<s> return ( uint8_t ) __builtin_aarch64_uqmovnhi


<s> if ( ! decl || TREE_CODE ( fntype ) != FUNCTION_TYPE ) { warning ( OPT_Wattributes , <STR_LIT> <STR_LIT> , name ) ; * no_add_attrs = true ; return NULL_TREE ; } * no_add_attrs |= cmse_func_args_or_return_in_stack ( NULL , name , fntype ) ; if ( * no_add_attrs ) return NULL_TREE ; type = TREE_TYPE ( decl ) ; type = build_distinct_type_copy ( type ) ; TREE_TYPE ( decl ) = type ; fntype = type ; while ( TREE_CODE ( fntype ) != FUNCTION_TYPE ) { type = fntype


<s> MachineBasicBlock :: iterator MBBI = MBB . end ( ) ; while ( MBBI != MBB . begin ( ) ) { MachineInstr & MI = * -- MBBI ; if ( CompleteCCUsers && ( MI . isCompare ( ) || isLoadAndTestAsCmp ( MI ) ) && ( optimizeCompareZero ( MI , CCUsers ) || fuseCompareOperations ( MI , CCUsers ) ) ) { ++ MBBI ; MI . eraseFromParent ( ) ; Changed = true ; CCUsers . clear


<s> MCAsmInfo * MAI = new <ISA_LIT>MCAsmInfo ( TT ) ; MCCFIInstruction Inst = MCCFIInstruction :: createDefCfa ( nullptr , <STR_LIT> , <NUM_LIT> ) ; MAI -> addInitialFrameState ( Inst ) ; return MAI


<s> return new <ISA_LIT>PassConfig ( * this , PM


<s> SlotIndex UseIdx = LIS -> getInstructionIndex ( Use ) ; SlotIndex DefIdx ; if ( Reg . isVirtual ( ) ) { if ( ! LIS -> hasInterval ( Reg ) ) return nullptr ; LiveInterval & LI = LIS -> getInterval ( Reg ) ; LaneBitmask SubLanes = SubReg ? getSubRegIndexLaneMask ( SubReg ) : MRI . getMaxLaneMaskForVReg ( Reg ) ; VNInfo * V = nullptr ; if ( LI . hasSubRanges ( ) ) { for ( auto & S : LI . subranges ( ) ) { if ( ( S . LaneMask & SubLanes ) == SubLanes ) { V = S . getVNInfoAt ( UseIdx ) ; break ; } } }


<s> return ScopedHT . lookup ( Entry ) .


<s> if ( suffix == 'q' ) return TFmode ; if ( suffix == 'w'


<s> CAddr = dyn_cast < ConstantSDNode > ( Addr . getOperand ( <NUM_LIT> ) ) ; if ( ! CAddr || ! <ISA_LIT>InstrInfo :: isLegalMUBUFImmOffset ( CAddr -> getZExtValue ( ) ) ) return false ; if ( ! IsCopyFromSGPR ( * TRI , Addr . getOperand ( <NUM_LIT> ) ) ) return false ; SOffset = Addr . getOperand ( <NUM_LIT> ) ; } else if ( ( CAddr = dyn_cast < ConstantSDNode > ( Addr ) ) && <ISA_LIT>InstrInfo :: isLegalMUBUFImmOffset ( CAddr -> getZExtValue ( ) ) ) { SOffset = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; } else { return false ; } SRsrc = CurDAG -> getRegister ( Info -> getScratchRSrcReg ( ) , <STR_LIT> ) ; Offset = CurDAG -> getTargetConstant ( CAddr -> getZExtValue ( ) , DL , <STR_LIT>


<s> rtx nds32_return_addr_rtx ( int count , rtx frameaddr ATTRIBUTE_UNUSED ) { if ( count !=


<s> Fixups . push_back ( MCFixup :: create ( <NUM_LIT> , MCOp . getExpr ( ) , Kind ) ) ; return


<s> unsigned <ISA_LIT>ompactRegisterInfo :: getFrameRegister ( const MachineFunction &


<s> if ( riscv_compressed_reg_p ( regno ) )


<s> if ( ! CurDAG -> isBaseWithConstantOffset ( N ) ) { if ( N . getOpcode ( ) == <STR_LIT> && ! ( Subtarget -> useMovt ( ) && N . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) ) { Base = N . getOperand ( <NUM_LIT> ) ; } else { Base = N ; } OffImm = CurDAG -> getTargetConstant ( <NUM_LIT> , <STR_LIT> ) ; return true ; } RegisterSDNode * LHSR = dyn_cast < RegisterSDNode > ( N . getOperand ( <NUM_LIT> ) ) ; RegisterSDNode * RHSR = dyn_cast < RegisterSDNode > ( N . getOperand ( <NUM_LIT> ) ) ; if ( ( LHSR && LHSR -> getReg ( ) == <STR_LIT> ) || ( RHSR && RHSR -> getReg ( ) == <STR_LIT> ) ) { ConstantSDNode * LHS = dyn_cast < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) ) ; ConstantSDNode * RHS = dyn_cast < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) ) ; unsigned LHSC = LHS ? LHS -> getZExtValue ( ) : <NUM_LIT> ; unsigned RHSC = RHS ? RHS -> getZExtValue ( )


<s> unsigned Reg = Saved [ <NUM_LIT> ] . getOperand ( <NUM_LIT> ) . getReg ( ) ; int64_t Pred = Saved [ <NUM_LIT> ] . getOperand ( <NUM_LIT> ) . getImm ( ) ; Out . EmitBundleLock ( false ) ; EmitBICMask ( Out , Reg , Pred , <NUM_LIT> ) ; Out . EmitInstruction ( Saved [ <NUM_LIT> ]


<s> if ( TREE_READONLY ( decl ) ) return false ; if ( ! TARGET_VOLATILE_CACHE_SET && TREE_THIS_VOLATILE ( decl ) ) return false ; attr = TYPE_ATTRIBUTES ( TREE_TYPE ( decl ) ) ; if ( lookup_attribute ( <STR_LIT> , attr ) ) return false ; attr = DECL_ATTRIBUTES ( decl ) ; if ( lookup_attribute ( <STR_LIT> , attr ) ) return false ; if ( DECL_SECTION_NAME ( decl ) != <NUM_LIT> ) { const char * name = DECL_SECTION_NAME


<s> static MCInstPrinter * create<ISA_LIT>MCInstPrinter ( const Target & T , unsigned SyntaxVariant , const MCAsmInfo & MAI , const MCInstrInfo & MII , const MCRegisterInfo & MRI , const MCSubtargetInfo & STI ) { if ( SyntaxVariant == <NUM_LIT> ) return ( new <ISA_LIT>InstPrinter ( MAI , MII , MRI ) ) ; else return NULL


<s> if ( ! checkHighLaneIndex ( Op0 . getNode ( ) , LaneOp , LaneIdx ) ) return false ; } StdOp = Op1


<s> unsigned OpIdx = <NUM_LIT> ; if ( TableEntry -> isUpdating ) MIB . addOperand ( MI . getOperand ( OpIdx ++ ) ) ; MIB . addOperand ( MI . getOperand ( OpIdx ++ ) ) ; MIB . addOperand ( MI . getOperand ( OpIdx ++ ) ) ; if ( TableEntry -> hasWritebackOperand ) MIB . addOperand ( MI . getOperand ( OpIdx ++ ) ) ; bool SrcIsKill = MI . getOperand ( OpIdx ) . isKill ( ) ; bool SrcIsUndef = MI . getOperand ( OpIdx ) . isUndef ( ) ; unsigned SrcReg = MI . getOperand ( OpIdx ++ ) . getReg ( ) ; unsigned D0 , D1 , D2 , D3 ; GetDSubRegs ( SrcReg , RegSpc , TRI , D0 , D1 , D2 , D3 ) ; MIB . addReg ( D0 , getUndefRegState ( SrcIsUndef ) ) ; if ( NumRegs > <NUM_LIT> && TableEntry -> copyAllListRegs ) MIB . addReg ( D1 , getUndefRegState


<s> if ( ! isLoadStoreTypeLegal ( I -> getType ( ) , VT ) || cast < LoadInst > ( I ) -> isAtomic ( ) ) return false ; Address Addr ; if ( ! ComputeAddress ( I -> getOperand ( <NUM_LIT> ) , Addr ) ) return false ; unsigned ResultReg ; if ( ! EmitLoad ( VT , ResultReg , Addr ) ) return false ; UpdateValueMap ( I , ResultReg )


<s> case <STR_LIT> : case <STR_LIT> : assert ( MI . getDesc ( ) . getNumOperands ( ) >= <NUM_LIT> && MI . getOperand ( <NUM_LIT> ) . isReg ( ) && MI . getOperand ( <NUM_LIT> ) . isReg ( ) && <STR_LIT> ) ; SrcReg = MI . getOperand ( <NUM_LIT> ) .


<s> return __builtin_mve_vmulhq_m_uv16qi ( __arm_vuninitializedq_u8 ( ) , __a ,


<s> case 'H' : mode = HImode ; break ; case 'S' : mode = SImode ; break ; case 'D' : mode = DImode ; break ; default : return <NUM_LIT> ; } switch ( str [ <NUM_LIT> ] ) { case '0' : def = <NUM_LIT> ; break ; case 'F' : def = - <NUM_LIT> ; break ; default : return <NUM_LIT> ; } if ( GET_MODE_SIZE ( mode ) <= GET_MODE_SIZE ( part_mode ) ) return <NUM_LIT> ; part = s390_single_part ( GEN_INT ( value ) , mode , part_mode , def ) ; if ( part < <NUM_LIT> ) return <NUM_LIT> ; if ( part_goal != - <NUM_LIT> && part_goal != part ) return <NUM_LIT> ; break ; case 'O' : if ( ! TARGET_EXTIMM ) return <NUM_LIT> ; switch ( str [ <NUM_LIT> ] ) { case 's' : return trunc_int_for_mode ( value , SImode ) == value ; case 'p' : return value == <NUM_LIT> || s390_single_part ( GEN_INT ( value ) , DImode , SImode , <NUM_LIT> ) == <NUM_LIT> ; case 'n' : return value == - <NUM_LIT> || s390_single_part ( GEN_INT ( value ) , DImode , SImode , - <NUM_LIT> ) == <NUM_LIT> ; default : gcc_unreachable ( ) ; } break ; case


<s> unsigned LA = std :: max ( unsigned ( PostAlign ) , LogAlign ) ; if ( ! LA ) return PO ; return PO + UnknownPadding ( LA , internalKnownBits ( )


<s> if ( SrcRC == & <STR_LIT> ) return & <STR_LIT> ; if ( SrcRC == & <STR_LIT> ) return & <STR_LIT> ; llvm_unreachable ( <STR_LIT> ) ; return


<s> vec_float4 * p = ( vec_float4 * ) ( ( unsigned char * ) ( c ) + b ) ; shift = <NUM_LIT> - ( ( int ) p & <NUM_LIT> ) ; * p = spu_sel ( * p , spu_slqwbyte ( a , shift ) , spu_slqwbyte ( spu_splats ( ( unsigned int )


<s> MachineInstr * <ISA_LIT>InstrInfo :: emitFrameIndexDebugValue ( MachineFunction & MF , int FrameIx , uint64_t Offset , const MDNode * MDPtr , DebugLoc DL ) const { MachineInstrBuilder MIB = BuildMI ( MF , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FrameIx ) . addImm ( <NUM_LIT> ) . addImm ( Offset ) . addMetadata ( MDPtr ) ; return & * MIB


<s> void printARIPI8Mem ( const MCInst * MI , unsigned opNum


<s> SDValue NewAnd = DAG . getNode ( <STR_LIT> , DL , VT , X , NewMask ) ; SDValue NewShift = DAG . getNode ( <STR_LIT> , DL , VT , NewAnd , Shift . getOperand ( <NUM_LIT> ) ) ; InsertDAGNode ( DAG , N , NewMask ) ; InsertDAGNode ( DAG , N , NewAnd ) ; InsertDAGNode ( DAG , N , NewShift ) ; DAG . ReplaceAllUsesWith ( N , NewShift ) ; AM . Scale = <NUM_LIT> << ShiftAmt ; AM . IndexReg = NewAnd ; return


<s> if ( isTargetShuffle ( U -> getOpcode ( ) ) ) return true ; if ( U -> getOpcode ( ) == <STR_LIT> ) return isUseOfShuffle ( U ) ; } return false


<s> static bool isRegisterSize ( unsigned


<s> else if ( IDVal == <STR_LIT> ) return parseDirectiveFnStart ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) return parseDirectiveFnEnd ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) return parseDirectiveCantUnwind ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) return parseDirectivePersonality ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) return parseDirectiveHandlerData ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) return parseDirectiveSetFP ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) return parseDirectivePad ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) return parseDirectiveRegSave ( DirectiveID . getLoc ( ) , false ) ; else if ( IDVal == <STR_LIT> ) return parseDirectiveRegSave ( DirectiveID . getLoc ( ) , true ) ; else if ( IDVal == <STR_LIT> ) return parseDirectiveInst ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) return parseDirectiveInst ( DirectiveID . getLoc ( ) , 'n' ) ; else if ( IDVal == <STR_LIT> ) return parseDirectiveInst ( DirectiveID . getLoc ( ) , 'w' ) ; else if ( IDVal == <STR_LIT> || IDVal == <STR_LIT> ) return parseDirectiveLtorg ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) return parseDirectiveEven ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) return parseDirectivePersonalityIndex ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) return parseDirectiveUnwindRaw ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) return parseDirectiveTLSDescSeq ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) return parseDirectiveMovSP ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) return parseDirectiveObjectArch


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( ForceAllBaseRegAlloc ) return true ; break ; default : return false ; } MachineFunction & MF = * MI -> getParent ( ) -> getParent ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; int64_t FPOffset = Offset - <NUM_LIT> ; if ( ! AFI -> isThumbFunction ( ) || ! AFI -> isThumb1OnlyFunction ( ) ) FPOffset -= <NUM_LIT> ; Offset =


<s> unsigned HiSR = subreg_hireg ; if ( S == <NUM_LIT> ) { BuildMI ( B , MI , DL , TII -> get ( A2_or ) , LoR ) . addReg ( Op1 . getReg ( ) , RS1 & ~ RegState :: Kill , LoSR ) . addReg ( Op2 . getReg ( ) , RS2 & ~ RegState :: Kill , LoSR ) ; BuildMI ( B , MI , DL , TII -> get ( A2_or ) , HiR ) . addReg ( Op1 . getReg ( ) , RS1 , HiSR ) . addReg ( Op2 . getReg ( ) , RS2 , HiSR ) ; } else if ( S < <NUM_LIT> ) { BuildMI ( B , MI , DL , TII -> get ( S2_asl_i_r_or ) , LoR ) . addReg ( Op1 . getReg ( ) , RS1 & ~ RegState :: Kill , LoSR ) . addReg ( Op2 . getReg ( ) , RS2 & ~ RegState :: Kill , LoSR ) . addImm ( S ) ; unsigned TmpR1 = MRI -> createVirtualRegister ( IntRC ) ; BuildMI ( B , MI , DL , TII -> get ( S2_extractu ) , TmpR1 ) . addReg ( Op2 . getReg ( ) , RS2 & ~ RegState :: Kill , LoSR ) . addImm ( S ) . addImm ( <NUM_LIT> - S ) ; unsigned TmpR2 = MRI -> createVirtualRegister ( IntRC ) ; BuildMI ( B , MI , DL , TII -> get ( A2_or ) , TmpR2 ) . addReg ( Op1 . getReg ( ) , RS1 , HiSR ) . addReg ( TmpR1 ) ; BuildMI ( B , MI , DL , TII -> get ( S2_asl_i_r_or ) , HiR ) . addReg ( TmpR2 ) . addReg ( Op2 . getReg ( ) , RS2 , HiSR ) . addImm ( S ) ; } else if ( S == <NUM_LIT> ) { BuildMI ( B , MI , DL , TII -> get ( TargetOpcode :: COPY ) , LoR ) .

addReg ( Op1 . getReg ( ) , RS1 & ~ RegState :: Kill , LoSR ) ;


<s> if ( offsettable_p && ! rs6000_legitimate_offset_address_p ( mode , addr , strict_p , true ) ) stack = replace_equiv_address ( stack , copy_addr_to_reg ( addr ) ) ; else if ( reg_reg_p && ! legitimate_indexed_address_p ( addr , strict_p ) ) stack = replace_equiv_address ( stack , copy_addr_to_reg ( addr ) ) ; } return stack


<s> static SDValue getVShift ( bool isLeft , EVT VT , SDValue SrcOp , unsigned NumBits , SelectionDAG & DAG , const TargetLowering & TLI , SDLoc dl ) { assert ( VT . is128BitVector ( ) && <STR_LIT> ) ; MVT ShVT = <STR_LIT> ; unsigned Opc = isLeft ? <STR_LIT> : <STR_LIT> ; SrcOp = DAG . getBitcast ( ShVT ,


<s> bool llvm :: getAlign ( const CallInst & I , unsigned index , unsigned & align ) { if ( MDNode * alignNode = I . getMDNode ( <STR_LIT> ) ) { for ( int i = <NUM_LIT> , n = alignNode -> getNumOperands ( ) ; i < n


<s> string Reg = TRI -> getName ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; string RegOff = TRI -> getName ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; SExpr * offset = ctx -> select ( <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , ctx -> u_mul ( <NUM_LIT> , <NUM_LIT> , ctx -> load ( <NUM_LIT> , RegOff ) , ctx -> dec_unsigned ( <NUM_LIT> , <NUM_LIT> ) ) ) ; SExpr * bytes_to_bits = ctx -> select ( <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , ctx -> u_mul ( <NUM_LIT> , <NUM_LIT> , ctx -> load ( <NUM_LIT> , Reg ) , ctx -> dec_unsigned ( <NUM_LIT> , <NUM_LIT> ) ) ) ; SExpr * add = ctx -> add ( <NUM_LIT> , bytes_to_bits , offset , <NUM_LIT>


<s> inline vector signed char vec_srl ( vector signed char a1 ,


<s> static std :: map < StringRef , <STR_LIT> > CpuTable { { <STR_LIT> , <STR_LIT> :: V60 } , { <STR_LIT> , <STR_LIT> :: V5 } , { <STR_LIT> , <STR_LIT> :: V55 } , { <STR_LIT> , <STR_LIT> :: V60 } , { <STR_LIT> , <STR_LIT> :: V62 } , { <STR_LIT> , <STR_LIT> :: V65 } , } ; auto FoundIt = CpuTable . find ( CPUString ) ; if ( FoundIt != CpuTable . end ( ) ) <ISA_LIT>ArchVersion = FoundIt -> second ; else llvm_unreachable ( <STR_LIT> ) ; UseHVX128BOps = false ; UseHVX64BOps = false ; UseLongCalls = false ; UseBSBScheduling = hasV60Ops ( ) && EnableBSBSched ; ParseSubtargetFeatures ( CPUString , FS ) ; if ( OverrideLongCalls . getPosition ( ) ) UseLongCalls = OverrideLongCalls ; FeatureBitset Features =


<s> MachineInstr * Lo = BuildMI ( * MBB , MI , DL , get ( <STR_LIT> ) , LoDst ) . addImm ( Op . getImm ( ) & <NUM_LIT> ) ; MachineInstr * Hi = BuildMI ( * MBB , MI , DL , get ( <STR_LIT> ) , HiDst ) . addImm ( Op . getImm ( ) >> <NUM_LIT> ) ; BuildMI ( * MBB , MI , DL , get ( TargetOpcode :: REG_SEQUENCE ) , Dst ) . addReg ( LoDst ) . addImm ( <STR_LIT> ) . addReg ( HiDst ) . addImm ( <STR_LIT> ) ; Worklist . push_back ( Lo ) ; Worklist . push_back (


<s> vmovn_s16 ( int16x8_t a ) { int8x8_t result ; __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) : ) ; return result


<s> assert ( MO2 . isImm ( ) && <STR_LIT> ) ; <STR_LIT> ShOpc = <STR_LIT> ( MO2 . getImm ( ) ) ; O << <STR_LIT> << <STR_LIT> ( ShOpc ) ; if ( ShOpc != <STR_LIT> ) O << <STR_LIT> << translateShiftImm ( <STR_LIT> (


<s> if ( ! INSN_P ( cur_insn ) ) continue ; pat = PATTERN ( cur_insn ) ; if ( epilogue_completed && RTX_FRAME_RELATED_P ( cur_insn ) ) { if ( GET_CODE ( pat ) == SET && GENERAL_REG_P ( SET_DEST ( pat ) ) ) { if ( GET_MODE ( SET_SRC ( pat ) ) == DImode && FP_REG_P ( SET_SRC ( pat ) ) ) continue ; if ( GET_CODE ( SET_SRC ( pat ) ) == MEM ) continue ; } if ( GET_CODE ( pat ) == PARALLEL &&

load_multiple_operation ( pat , VOIDmode ) ) continue ;


<s> void <ISA_LIT>SEInstrInfo :: expandExtractElementF64 ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , bool FP64 ) const { unsigned DstReg = I -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned SrcReg = I -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned N = I -> getOperand ( <NUM_LIT> ) . getImm ( ) ; DebugLoc dl = I -> getDebugLoc ( ) ; assert ( N < <NUM_LIT> && <STR_LIT> ) ; unsigned SubIdx = N ? <STR_LIT> : <STR_LIT> ; unsigned SubReg = getRegisterInfo ( ) . getSubReg ( SrcReg , SubIdx ) ; if ( SubIdx == <STR_LIT>


<s> void setHasSpilledSGPRs ( bool Spill = true ) { HasSpilledSGPRs =


<s> MI -> dump ( ) ; ) ; RegSeqInfo CandidateR<ISA_LIT> ; std :: vector < std :: pair < unsigned , unsigned > > RemapChan ; DEBUG ( dbgs ( ) << <STR_LIT> ; ) ; if ( tryMergeUsingCommonSlot ( R<ISA_LIT> , CandidateR<ISA_LIT> , RemapChan ) ) { RemoveMI ( CandidateR<ISA_LIT> . Instr ) ; MII = RebuildVector ( & R<ISA_LIT> , & CandidateR<ISA_LIT> , RemapChan ) ; trackR<ISA_LIT> ( R<ISA_LIT> ) ; continue ; } DEBUG ( dbgs ( ) << <STR_LIT> ; ) ; RemapChan . clear ( ) ; if ( tryMergeUsingFreeSlot ( R<ISA_LIT> , CandidateR<ISA_LIT> , RemapChan ) ) { RemoveMI ( CandidateR<ISA_LIT> . Instr ) ; MII = RebuildVector ( & R<ISA_LIT> , & CandidateR<ISA_LIT> , RemapChan ) ; trackR<ISA_LIT> ( R<ISA_LIT> ) ; continue ; } trackR<ISA_LIT> ( R<ISA_LIT> ) ; } } return


<s> void LLVMInitialize<ISA_LIT>Target ( ) { RegisterTargetMachine < <ISA_LIT>TargetMachine > X


<s> static CodeModel :: Model getEffectiveCodeModel ( Optional < CodeModel :: Model > CM ) { if ( CM ) return * CM ; return CodeModel ::


<s> const uint32_t * <ISA_LIT>RegisterInfo :: getCallPreservedMask ( const MachineFunction & MF , CallingConv :: ID CC ) const { if ( CC == CallingConv :: GHC ) return CSR_<ISA_LIT>_NoRegs_RegMask ; if ( CC == CallingConv :: AnyReg ) return CSR_<ISA_LIT>_AllRegs_RegMask ; if ( CC == CallingConv :: CXX_FAST_TLS ) return CSR_<ISA_LIT>_CXX_TLS_Darwin_RegMask ; if ( MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getTargetLowering ( ) -> supportSwiftError ( ) && MF . getFunction ( ) -> getAttributes ( ) .

hasAttrSomewhere ( Attribute :: SwiftError ) ) return CSR_<ISA_LIT>_AAPCS_SwiftError_RegMask ;


<s> rtx rs6000_emit_eqne ( machine_mode mode , rtx op1 , rtx op2 , rtx scratch ) { if ( op2 == const0_rtx ) return op1 ; if ( GET_CODE ( scratch ) == SCRATCH ) scratch = gen_reg_rtx ( mode ) ; if ( logical_operand ( op2 , mode ) ) emit_insn ( gen_rtx_SET ( scratch , gen_rtx_XOR ( mode , op1 , op2 ) ) ) ; else emit_insn ( gen_rtx_SET ( scratch , gen_rtx_PLUS ( mode ,


<s> void DecodePSHUFMask ( unsigned NumElts , unsigned ScalarBits , unsigned Imm , SmallVectorImpl < int > & ShuffleMask ) { unsigned Size = NumElts * ScalarBits ; unsigned NumLanes = Size /


<s> EVT NewVT = getTypeToTransformTo ( * DAG . getContext ( ) , N -> getValueType ( <NUM_LIT> ) ) ; Lo = DAG . getNode ( <STR_LIT> , dl , NewVT , Op , DAG . getConstant


<s> const unsigned Opc = CI . I -> getOpcode ( ) ; const InstClassEnum InstClass = getInstClass ( Opc , * TII ) ; if ( InstClass == UNKNOWN ) { return false ; } const unsigned InstSubclass = getInstSubclass ( Opc , * TII ) ; int Swizzled = <STR_LIT> ( CI . I -> getOpcode ( ) , <STR_LIT> :: swz ) ; if ( Swizzled != - <NUM_LIT> && CI . I -> getOperand ( Swizzled ) . getImm ( ) ) return false ; ++ MBBI ; DenseSet < unsigned > RegDefsToMove ; DenseSet < unsigned > PhysRegUsesToMove ; addDefsUsesToList ( * CI . I , RegDefsToMove , PhysRegUsesToMove ) ; for ( ; MBBI != E ; ++ MBBI ) { if ( ( getInstClass ( MBBI -> getOpcode ( ) , * TII ) != InstClass ) || ( getInstSubclass ( MBBI -> getOpcode ( ) , * TII ) != InstSubclass ) ) { if ( MBBI -> hasUnmodeledSideEffects ( ) ) { return false ; } if ( MBBI -> mayLoadOrStore ( ) && ( ! memAccessesCanBeReordered ( * CI . I , * MBBI , AA ) || ! canMoveInstsAcrossMemOp ( * MBBI , CI . InstsToMove , AA ) ) ) { CI . InstsToMove . push_back ( & * MBBI ) ; addDefsUsesToList ( * MBBI , RegDefsToMove , PhysRegUsesToMove ) ; continue ; } addToListsIfDependent ( * MBBI , RegDefsToMove , PhysRegUsesToMove , CI . InstsToMove ) ; continue ; } if ( MBBI -> hasOrderedMemoryRef ( ) ) return false ; int Swizzled = <STR_LIT> ( MBBI -> getOpcode ( ) , <STR_LIT> :: swz ) ; if ( Swizzled != - <NUM_LIT> && MBBI -> getOperand ( Swizzled ) . getImm ( ) ) return false ; if ( addToListsIfDependent ( * MBBI , RegDefsToMove , PhysRegUsesToMove , CI . InstsToMove ) ) continue ; bool Match = CI . hasSameBaseAddress ( * MBBI ) ; if ( Match ) { CI . setPaired ( MBBI , * TII ) ; bool canBeCombined = CI . InstClass == MIMG ? dmasksCanBeCombined ( CI , * TII ) : widthsFit ( * STM , CI ) && offsetsCanBeCombined ( CI , * STI ) ; if ( canBeCombined && canMoveInstsAcrossMemOp ( * MBBI , CI . InstsToMove , AA


<s> } if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rn , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rm , Address , Decoder ) ) ) return MCDisassembler :: Fail ; unsigned shift ; if ( U ) shift = <STR_LIT> ( <STR_LIT> , imm , ShOp ) ; else shift = <STR_LIT> ( <STR_LIT> ,


<s> <STR_LIT> CC = ( <STR_LIT> ) MI -> getOperand ( OpNum ) . getImm (


<s> __asm__ ( <STR_LIT> : <STR_LIT> ( result )


<s> } bool FPNeedsSetting = hasFP ( MF ) ; for ( ; MBBI != MBB . end ( ) ; ++ MBBI ) { if ( FPNeedsSetting && MBBI -> getOpcode ( ) == <STR_LIT> && MBBI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) { int64_t X29FrameIdx = MBBI -> getOperand ( <NUM_LIT> ) . getIndex ( ) ; FuncInfo -> setFramePointerOffset ( MFI -> getObjectOffset ( X29FrameIdx ) ) ; ++ MBBI ; emitRegUpdate ( MBB , MBBI , DL , TII , <STR_LIT> , <STR_LIT> , <STR_LIT> , NumInitialBytes + MFI -> getObjectOffset ( X29FrameIdx ) , MachineInstr :: FrameSetup ) ; MFI -> setOffsetAdjustment ( - MFI -> getObjectOffset ( X29FrameIdx ) - MFI -> getStackSize ( ) ) ; if ( NeedsFrameMoves ) { unsigned Reg = MRI -> getDwarfRegNum ( <STR_LIT> , true ) ; unsigned Offset = MFI -> getObjectOffset ( X29FrameIdx ) ; unsigned CFIIndex = MMI . addFrameInst ( MCCFIInstruction :: createDefCfa ( nullptr , Reg , Offset ) ) ; BuildMI ( MBB , MBBI , DL , TII . get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; } FPNeedsSetting = false ; } if ( ! MBBI -> getFlag ( MachineInstr :: FrameSetup ) ) break ; } assert ( ! FPNeedsSetting && <STR_LIT> ) ; emitSPUpdate ( MBB , MBBI , DL , TII , <STR_LIT> , - NumResidualBytes , MachineInstr :: FrameSetup ) ; if ( ! NeedsFrameMoves ) return ; if ( ! hasFP ( MF ) && NumResidualBytes ) { MachineLocation Dst ( MachineLocation :: VirtualFP ) ; unsigned Reg = MRI -> getDwarfRegNum ( <STR_LIT> , true ) ; unsigned Offset = NumResidualBytes + NumInitialBytes


<s> Op . setReg ( NewReg ) ; MachineInstr * Clone = & * std :: prev ( MachineBasicBlock :: instr_iterator ( Insert ) ) ; LIS . InsertMachineInstrInMaps ( Clone ) ; LIS . createAndComputeVirtRegInterval ( NewReg ) ; MFI . stackifyVReg ( NewReg ) ; ImposeStackOrdering ( Clone ) ; if ( MRI . use_empty ( Reg ) ) { SlotIndex Idx = LIS . getInstructionIndex ( Def ) . getRegSlot ( ) ; LIS . removePhysRegDefAt ( <STR_LIT> , Idx ) ; LIS . removeVRegDefAt ( LIS . getInterval ( Reg ) , Idx ) ; LIS . removeInterval ( Reg ) ; LIS . RemoveMachineInstrFromMaps ( Def ) ; Def -> eraseFromParent ( ) ; } else { LIS . shrinkToUses ( & LIS .


<s> unsigned Opcode = MI . getOpcode ( ) ; switch ( Opcode ) { case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; } MI . setDesc ( MII . get ( Opcode ) ) ; return true


<s> bool hasExtractInsert ( ) const { return ! in<ISA_LIT>16Mode ( ) && has<ISA_LIT>32r2


<s> unsigned getPartialUpdateClearance (


<s> return sizeof ( * this ) + alignTo ( namesz , ALIGN )


<s> static void cris_operand_lossage ( const char * msgid , rtx op ) { debug_rtx ( op ) ; output_operand_lossage ( <STR_LIT>


<s> const GlobalValue * GV = cast < GlobalAddressSDNode > ( Op ) -> getGlobal ( ) ; if ( Subtarget -> useMovt ( ) ) ++ NumMovwMovt ; unsigned Wrapper = isPositionIndependent ( ) ? <STR_LIT> : <STR_LIT> ; SDValue G = DAG . getTargetGlobalAddress ( GV , dl , PtrVT , <NUM_LIT> , <STR_LIT> ) ; SDValue Result = DAG . getNode ( Wrapper , dl , PtrVT , G ) ; if ( Subtarget -> isGVIndirectSymbol ( GV ) ) Result = DAG . getLoad ( PtrVT , dl , DAG . getEntryNode ( ) , Result , MachinePointerInfo :: getGOT ( DAG . getMachineFunction ( ) ) ) ; return


<s> bool <ISA_LIT>RedundantCopyElimination :: runOnMachineFunction ( MachineFunction & MF ) { if ( skipFunction ( MF . getFunction ( ) ) ) return false ; TRI = MF . getSubtarget ( ) . getRegisterInfo ( ) ; MRI = & MF . getRegInfo ( ) ; bool Changed = false ; for ( MachineBasicBlock & MBB : MF ) Changed |= optimizeBlock ( MBB ) ; return


<s> unsigned high_part_offset = subreg_highpart_offset ( SImode , DImode ) ; return simplify_gen_subreg ( SImode , reg , DImode , high_part_offset


<s> unsigned getNumFixupKinds ( ) const override {


<s> static std :: unique_ptr < <ISA_LIT>Operand > createToken ( StringRef Str , SMLoc S ) { auto Op = std :: make_unique < <ISA_LIT>Operand > ( Token ) ; Op -> Tok


<s> bool <ISA_LIT>TargetLowering :: isLegalAddressImmediate ( llvm :: GlobalValue * GV


<s> Str += <STR_LIT> ; Str += nextTok . getIdentifier ( ) ; Parser . Lex ( ) ; if ( getLexer ( ) . getKind ( ) != AsmToken :: LParen ) return true ; } else break ; } if ( getParser ( ) . ParseParenExpression ( IdVal , EndLoc ) ) return true ; while ( getLexer ( ) . getKind ( ) == AsmToken :: RParen ) Parser . Lex ( ) ; } else return true ; if ( const MCConstantExpr * MCE = dyn_cast < MCConstantExpr > ( IdVal ) ) { int Val = MCE -> getValue ( ) ; if ( Str == <STR_LIT> ) { Val = Val & <NUM_LIT> ; } else if ( Str == <STR_LIT> ) { Val = ( Val & <NUM_LIT> ) >> <NUM_LIT> ; } Res = MCConstantExpr :: Create ( Val , getContext ( ) ) ; return false ; } if ( const MCSymbolRefExpr * MSRE = dyn_cast


<s> if ( NoABICalls && TM . isPositionIndependent ( ) ) report_fatal_error ( <STR_LIT> ) ; if ( isABI_N64 ( ) && ! TM . isPositionIndependent ( ) && ! hasSym32 ( ) ) NoABICalls = true ; UseSmallSection = GPOpt ; if ( ! NoABICalls && GPOpt ) { errs ( ) << <STR_LIT> << <STR_LIT> ; UseSmallSection = false ; } if ( hasDSPR2 ( ) && ! DspWarningPrinted ) { if ( has<ISA_LIT>64 ( ) && ! has<ISA_LIT>64r2 ( ) ) { errs ( ) << <STR_LIT> << <STR_LIT> ; DspWarningPrinted = true ; } else if ( has<ISA_LIT>32 ( ) && ! has<ISA_LIT>32r2 ( ) ) { errs ( ) << <STR_LIT> << <STR_LIT> ; DspWarningPrinted = true ; } } else if ( hasDSP ( ) && ! DspWarningPrinted ) { if ( has<ISA_LIT>64 ( ) && ! has<ISA_LIT>64r2 ( ) ) { errs ( ) << <STR_LIT> << <STR_LIT> ; DspWarningPrinted = true ; } else if ( has<ISA_LIT>32 ( ) && ! has<ISA_LIT>32r2 ( ) ) { errs ( ) << <STR_LIT> << <STR_LIT> ; DspWarningPrinted = true ; } } StringRef ArchName = has<ISA_LIT>64 ( ) ? <STR_LIT> : <STR_LIT> ; if ( ! has<ISA_LIT>32r5 ( ) && hasMSA ( ) && ! MSAWarningPrinted ) { errs ( ) << <STR_LIT> << ArchName << <STR_LIT> ; MSAWarningPrinted = true ; } if ( ! has<ISA_LIT>32r5 ( ) && hasVirt ( ) && ! VirtWarningPrinted ) { errs ( ) << <STR_LIT> << ArchName << <STR_LIT> ; VirtWarningPrinted = true ; } if ( ! has<ISA_LIT>32r6 ( ) && hasCRC ( ) && ! CRCWarningPrinted ) { errs ( ) << <STR_LIT> << ArchName << <STR_LIT> ; CRCWarningPrinted = true ; } if ( ! has<ISA_LIT>32r6 ( ) && hasGINV ( ) && ! GINVWarningPrinted ) { errs ( ) << <STR_LIT> << ArchName << <STR_LIT> ; GINVWarningPrinted = true ; } CallLoweringInfo . reset ( new <ISA_LIT>CallLowering ( * getTargetLowering ( ) ) ) ; Legalizer . reset ( new <ISA_LIT>LegalizerInfo


<s> break ; } } SmallSet < unsigned , <NUM_LIT> > Visited ; if ( phiHasVGPROperands ( MI , MRI , TRI , TII ) || ! phiHasBreakDef ( MI , MRI , Visited ) ) { DEBUG ( dbgs ( ) << <STR_LIT> << MI ) ; TII -> moveToVALU ( MI ) ; } break ; } case <STR_LIT> : { if ( TRI -> hasVGPRs ( TII -> getOpRegClass ( MI , <NUM_LIT> ) ) || ! hasVGPROperands ( MI , TRI ) ) { foldVGPRCopyIntoRegSequence ( MI , TRI , TII , MRI ) ; continue ; } DEBUG ( dbgs ( ) << <STR_LIT> << MI ) ; TII -> moveToVALU ( MI ) ; break ; } case <STR_LIT> : { const TargetRegisterClass * DstRC , * Src0RC , * Src1RC ; DstRC = MRI . getRegClass ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; Src0RC = MRI . getRegClass ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; Src1RC = MRI . getRegClass ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; if ( TRI -> isSGPRClass ( DstRC ) && ( TRI -> hasVGPRs ( Src0RC ) || TRI -> hasVGPRs ( Src1RC ) ) ) { DEBUG ( dbgs ( ) << <STR_LIT> << MI ) ; TII -> moveToVALU (


<s> DECL_FIELD_CONTEXT ( f_args ) = record ; DECL_FIELD_CONTEXT ( f_skip ) = record ; TREE_CHAIN ( record ) = type_decl ; TYPE_NAME ( record ) = type_decl ; TYPE_FIELDS ( record ) = f_args ; TREE_CHAIN ( f_args ) = f_skip ; owp =


<s> scalar_int_mode libval_mode = smallest_int_mode_for_size ( <NUM_LIT> * GET_MODE_BITSIZE ( mode ) ) ; rtx libval = emit_library_call_value ( libfunc , NULL_RTX , LCT_CONST , libval_mode , op0 , mode , op1 , mode ) ; rtx quotient = simplify_gen_subreg ( mode , libval , libval_mode , <NUM_LIT> ) ; rtx remainder = simplify_gen_subreg ( mode , libval , libval_mode , GET_MODE_SIZE ( mode ) ) ; gcc_assert ( quotient ) ; gcc_assert ( remainder ) ; * quot_p = quotient


<s> bool isScalarFPTypeInSSEReg ( MVT VT ) const { return ( VT == <STR_LIT> && <ISA_LIT>ScalarSSEf64 )

|| ( VT == <STR_LIT> && <ISA_LIT>ScalarSSEf32 ) ;


<s> MVT VMVT = TLI . getValueType ( V -> getType ( ) , true ) . getSimpleVT ( ) ; if ( ( VMVT == <STR_LIT> ) || ( VMVT == <STR_LIT> ) ) { unsigned TempReg = createResultReg (


<s> SDValue ShiftLeftHi = DAG . getNode ( <STR_LIT> , DL , VT , ShiftLeft1Hi , Not ) ; SDValue ShiftRightLo = DAG . getNode ( <STR_LIT> , DL , VT , Lo , Shamt ) ; SDValue Or = DAG . getNode ( <STR_LIT> , DL , VT , ShiftLeftHi , ShiftRightLo ) ; SDValue ShiftRightHi = DAG . getNode ( IsSRA ? <STR_LIT> : <STR_LIT> , DL , VT , Hi , Shamt ) ; SDValue Cond = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Shamt , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDValue Shift31 = DAG . getNode ( <STR_LIT> , DL , VT , Hi , DAG . getConstant ( <NUM_LIT> , VT ) ) ; Lo = DAG . getNode ( <STR_LIT> , DL , VT , Cond , ShiftRightHi , Or ) ; Hi = DAG . getNode ( <STR_LIT> , DL , VT , Cond , IsSRA ? Shift31 : DAG . getConstant ( <NUM_LIT> , VT ) , ShiftRightHi ) ; SDValue Ops [ <NUM_LIT> ] = { Lo , Hi } ; return DAG . getMergeValues ( Ops ,


<s> return IsConstantImm && isShiftedUInt < <NUM_LIT> , <NUM_LIT> > ( Imm ) && VK


<s> return gen_rtx_REG ( Pmode , MMIX_INCOMING_RETURN_ADDRESS_REGNUM )


<s> assert ( Reg >= <STR_LIT> && Reg <= <STR_LIT> && <STR_LIT> ) ; return Reg - <STR_LIT>


<s> return getTM < <ISA_LIT>TargetMachine > ( )


<s> if ( ! ( flags & SECTION_DEBUG ) ) fputs ( <STR_LIT> , asm_out_file ) ; if ( flags & SECTION_WRITE ) fputs ( <STR_LIT> , asm_out_file ) ; if ( flags & SECTION_TLS ) fputs ( <STR_LIT> , asm_out_file ) ; if ( flags & SECTION_CODE ) fputs ( <STR_LIT> , asm_out_file ) ; if ( HAVE_AS_SPARC_NOBITS ) { if ( flags & SECTION_BSS ) fputs ( <STR_LIT> , asm_out_file ) ; else fputs ( <STR_LIT> ,


<s> PreservedAnalyses <ISA_LIT>UnifyMetadataPass :: run ( Module & M , ModuleAnalysisManager


<s> bool <ISA_LIT>BaseInstrInfo :: isPredicated ( const MachineInstr * MI ) const { if ( MI -> isBundle ( ) ) { MachineBasicBlock :: const_instr_iterator I = MI ; MachineBasicBlock :: const_instr_iterator E = MI -> getParent ( ) -> instr_end ( ) ; while ( ++ I != E && I -> isInsideBundle ( ) ) { int PIdx = I -> findFirstPredOperandIdx ( ) ; if ( PIdx != - <NUM_LIT> && I -> getOperand ( PIdx )

. getImm ( ) != <STR_LIT> ) return true ;


<s> bool isMemOffs64_16 ( ) const { return isMemOffs ( ) && Mem . ModeSize == <NUM_LIT> && ( ! Mem . Size


<s> int Src1ModIdx = <STR_LIT> ( Opc , <STR_LIT> :: src1_modifiers ) ; int Src2ModIdx = <STR_LIT> ( Opc , <STR_LIT> :: src2_modifiers ) ; MI . RemoveOperand ( Src2ModIdx ) ; MI . RemoveOperand ( Src1ModIdx ) ; MI . RemoveOperand (


<s> if ( TARGET_64BIT ) if ( flag_pic ) { fprintf ( file , <STR_LIT> , LPREFIX , labelno ) ; fprintf ( file , <STR_LIT> , MCOUNT_NAME ) ; } else { fprintf ( file , <STR_LIT> , LPREFIX , labelno ) ; fprintf ( file , <STR_LIT> , MCOUNT_NAME ) ; } else if ( flag_pic ) { fprintf ( file , <STR_LIT> , LPREFIX , labelno , PROFILE_COUNT_REGISTER ) ; fprintf ( file , <STR_LIT> ,


<s> __o = __builtin_aarch64_set_qregxiv8hi ( __o , ( int16x8_t ) val . val [ <NUM_LIT> ] , <NUM_LIT> ) ; __o = __builtin_aarch64_set_qregxiv8hi ( __o , ( int16x8_t ) val . val [


<s> return MO . getImm ( ) ; } assert ( MO . isExpr ( ) && <STR_LIT> ) ; Fixups . push_back ( MCFixup :: create ( Offset , MO . getExpr ( ) , static_cast < MCFixupKind > ( <STR_LIT> ) , MI . getLoc ( ) ) ) ; Offset +=


<s> if ( Subtarget -> hasLSE ( ) ) return


<s> const LegalizerInfo * getLegalizerInfo ( ) const override


<s> switch ( RC -> getID ( ) ) { default : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { unsigned FP = TFI -> hasFP ( MF ) ? <NUM_LIT> : <NUM_LIT> ; return <NUM_LIT> - FP - DefaultSafety ; } case <STR_LIT> : case


<s> <ISA_LIT>CacheControl :: <ISA_LIT>CacheControl ( const GCNSubtarget & ST ) { TII = ST . getInstrInfo ( ) ; IV = getIsaVersion ( ST . getCPU ( )


<s> bool <ISA_LIT>Subtarget :: isPositionIndependent ( ) const { return TM . isPositionIndependent (


<s> Target & llvm :: getTheARM64Target ( ) { static Target


<s> unsigned MaskOpIdx = I -> MaskOpIdx ; if ( ! isa < RegisterSDNode > ( N -> getOperand ( MaskOpIdx ) ) || cast < RegisterSDNode > ( N -> getOperand ( MaskOpIdx ) ) -> getReg ( ) != <STR_LIT> ) return false ; const auto * Glued = N -> getGluedNode ( ) ; if ( ! Glued || Glued -> getOpcode ( ) != <STR_LIT> ) return false ; if ( ! isa < RegisterSDNode > ( Glued -> getOperand ( <NUM_LIT> ) ) || cast < RegisterSDNode > ( Glued -> getOperand ( <NUM_LIT> ) ) -> getReg ( ) != <STR_LIT> ) return false ; SDValue MaskSetter = Glued -> getOperand ( <NUM_LIT> ) ; const auto IsVMSet = [ ] ( unsigned Opc ) { return Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ; } ; if ( ! MaskSetter -> isMachineOpcode ( ) || ! IsVMSet ( MaskSetter . getMachineOpcode ( ) ) ) return false ; Optional < unsigned > TailPolicyOpIdx ; const <ISA_LIT>InstrInfo * TII = static_cast < const <ISA_LIT>InstrInfo * > ( CurDAG -> getSubtarget ( ) . getInstrInfo ( ) ) ; const MCInstrDesc & MaskedMCID = TII -> get ( N -> getMachineOpcode ( ) ) ; bool IsTA = true ; if ( <STR_LIT> ( MaskedMCID . TSFlags ) ) { TailPolicyOpIdx = N -> getNumOperands ( ) - <NUM_LIT> ; if ( N -> getOperand ( * TailPolicyOpIdx ) . getValueType ( ) == <STR_LIT> ) ( * TailPolicyOpIdx ) -- ; if ( N -> getOperand ( * TailPolicyOpIdx ) . getValueType ( ) == <STR_LIT> ) ( * TailPolicyOpIdx ) -- ; if ( ! ( N -> getConstantOperandVal ( * TailPolicyOpIdx ) & <STR_LIT> ) ) { if ( I -> UnmaskedTUPseudo == I -> MaskedPseudo && ! N -> getOperand ( <NUM_LIT> ) . isUndef ( ) ) return false ; if ( ! N -> getOperand ( <NUM_LIT> ) . isUndef ( ) ) IsTA = false ; } } if ( IsTA ) { uint64_t TSFlags = TII -> get ( I -> UnmaskedPseudo ) . TSFlags ; assert ( ! <STR_LIT> ( TSFlags ) && <STR_LIT> ( TSFlags ) && !


<s> Value * Cursor = II . getOperand ( <NUM_LIT> ) , * EarliestReplacement = nullptr ; const auto * IVTy = cast < VectorType > ( II . getType ( ) ) ; while ( Cursor ) { const auto * CursorVTy = cast < VectorType > ( Cursor -> getType ( ) ) ; if ( CursorVTy -> getElementCount ( ) . getKnownMinValue ( ) < IVTy -> getElementCount ( ) . getKnownMinValue


<s> if ( EnablePrefetch . getNumOccurrences ( ) > <NUM_LIT> ) UsePrefetching = EnablePrefetch ; if ( UsePrefetching ) addPass ( create<ISA_LIT>LoopDataPrefetchPass ( ) ) ; if ( TM -> getOptLevel ( ) == CodeGenOpt :: Aggressive && EnableGEPOpt ) { addPass ( createSeparateConstOffsetFromGEPPass ( TM ,


<s> void <ISA_LIT>CodeEmitter :: emitInstruction ( const MachineInstr & MI ) { DEBUG ( errs ( ) << <STR_LIT> << ( void * ) MCE . getCurrentPCValue ( ) << <STR_LIT> << MI ) ; MCE . processDebugLoc ( MI . getDebugLoc ( ) , true ) ; if ( ( MI . getDesc ( ) . TSFlags & <STR_LIT> ) == <STR_LIT> ) return ; emitWord ( getBinaryCodeForInstr ( MI ) ) ; ++ NumEmitted ; MCE . processDebugLoc ( MI . getDebugLoc ( ) ,


<s> void SVEIntrinsicOpts :: getAnalysisUsage ( AnalysisUsage & AU ) const { AU . addRequired < DominatorTreeWrapperPass >


<s> if ( GET_CODE ( x ) == PLUS ) { if ( GET_CODE ( XEXP ( x , <NUM_LIT> ) ) != CONST_INT ) return false ; x = XEXP ( x , <NUM_LIT> ) ; } if ( TARGET_MACHO && darwin_local_data_pic ( x ) ) return true ; if ( GET_CODE ( x ) == UNSPEC ) switch ( XINT ( x , <NUM_LIT>


<s> return unpackBits ( Waitcnt , getLgkmcntBitShift ( Version . Major ) , getLgkmcntBitWidth ( Version


<s> DebugLoc DL = MI . getDebugLoc ( ) ; MachineFunction & MF = * BB -> getParent ( ) ; unsigned AdjStackDown = TII . getCallFrameSetupOpcode ( ) ; MachineInstrBuilder CallseqStart = BuildMI ( MF , DL , TII . get ( AdjStackDown ) ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; BB -> insert ( MachineBasicBlock :: iterator ( MI ) ,


<s> if ( ( Seq . size ( ) < <NUM_LIT> ) || ( Seq [ <NUM_LIT> ] . Opc != ADDiu ) || ( Seq [ <NUM_LIT> ] . Opc != SHL ) || ( Seq [ <NUM_LIT> ] . ImmOperand < <NUM_LIT> ) ) return ; int64_t Imm = SignExtend64 < <NUM_LIT> > ( Seq [ <NUM_LIT> ] . ImmOperand ) ; int64_t ShiftedImm = ( uint64_t ) Imm << ( Seq [ <NUM_LIT> ] . ImmOperand - <NUM_LIT> ) ; if ( ! isInt < <NUM_LIT> > ( ShiftedImm ) ) return ; Seq [ <NUM_LIT> ] . Opc


<s> unsigned Offset = ( Is64Bit ? <NUM_LIT> : <NUM_LIT> ) + ( Uses64BitFramePtr ? <NUM_LIT> : <NUM_LIT> ) ; BuildCFI ( MBB , MBBI , DebugLoc { } , MCCFIInstruction :: createOffset ( nullptr , DwarfReg , - Offset ) ) ; emitCalleeSavedFrameMoves ( MBB , MBBI , DebugLoc {


<s> if ( STI . getFeatureBits ( ) [ <STR_LIT> ] ) return getThumbInstruction ( MI , Size , Bytes , Address , CS ) ; return get<ISA_LIT>Instruction ( MI , Size , Bytes ,


<s> unsigned TmpReg = MRI -> createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( BB , I , DL , TII -> get ( <STR_LIT> ) , TmpReg ) . addReg ( Reg , RegState :: Kill ) . addReg ( Reg


<s> return static_cast < const MCConstantExpr * > ( Val ) -> getValue (


<s> const uint32_t * <ISA_LIT>RegisterInfo :: getThisReturnPreservedMask ( CallingConv :: ID CC ) const { assert ( CC != CallingConv :: GHC && <STR_LIT> ) ; return


<s> return ( __m64 ) __builtin_ia32_pcmpeqd ( ( __v2si


<s> if ( CPU . empty ( ) || CPU == <STR_LIT> ) { return <STR_LIT> ; } return


<s> for ( unsigned i = <NUM_LIT> , e = StructT -> getNumElements ( ) ; i != e ; ++ i ) if ( StructT -> getElementType ( i ) != StructT -> getElementType ( <NUM_LIT> ) ) return false ; return true ; } EVT VT = TLI . getValueType ( DL , T , true ) ; if ( ! VT . isSimple ( ) || VT . isVector ( ) || ! ( VT . isInteger (

) || VT . isFloatingPoint ( ) ) ) return false ;


<s> bool hasJAVA ( ) const { return HasJAVA


<s> return ( __m64 ) __builtin_arm_wsadhz ( ( __v4hi )


<s> void ExpandPseudo :: expandLoadACC ( MachineBasicBlock & MBB , Iter I , unsigned RegSize ) { assert ( I -> getOperand ( <NUM_LIT> ) . isReg ( ) && I -> getOperand ( <NUM_LIT> ) . isFI ( ) ) ; const TargetRegisterClass * RC = RegInfo . intRegClass ( RegSize ) ; unsigned VR0 = MRI . createVirtualRegister ( RC ) ; unsigned VR1 = MRI . createVirtualRegister ( RC ) ; unsigned Dst = I -> getOperand ( <NUM_LIT> ) . getReg ( ) , FI = I -> getOperand ( <NUM_LIT> ) . getIndex ( ) ; unsigned Lo = RegInfo . getSubReg ( Dst , <STR_LIT> ) ; unsigned Hi = RegInfo . getSubReg ( Dst , <STR_LIT> ) ; DebugLoc DL = I -> getDebugLoc ( ) ; const MCInstrDesc & Desc = TII . get ( TargetOpcode :: COPY ) ; TII . loadRegFromStack ( MBB , I , VR0 , FI , RC , & RegInfo


<s> const MachineOperand & MO1 = MI -> getOperand ( OpNum ) ; const MachineOperand & MO2 = MI -> getOperand ( OpNum + <NUM_LIT> ) ; O << <STR_LIT> << TRI -> getAsmName (


<s> return getShuffleAlignrImmediate ( SVOp


<s> return SDValue ( ) ; } SDValue Chain = ST -> getChain ( ) ; SDValue BasePtr = ST -> getBasePtr ( ) ; SDValue Value = ST -> getValue ( ) ; DebugLoc dl = Op . getDebugLoc ( ) ; if ( ST -> getAlignment ( ) == <NUM_LIT> ) { SDValue Low = Value ; SDValue High = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Value , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDValue StoreLow = DAG . getTruncStore ( Chain , dl , Low , BasePtr , ST -> getPointerInfo ( ) , <STR_LIT> , ST -> isVolatile ( ) , ST -> isNonTemporal ( ) , <NUM_LIT> ) ; SDValue HighAddr = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , BasePtr , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDValue StoreHigh = DAG . getTruncStore ( Chain , dl , High , HighAddr , ST -> getPointerInfo ( ) . getWithOffset ( <NUM_LIT> ) , <STR_LIT> , ST -> isVolatile ( ) , ST -> isNonTemporal ( ) , <NUM_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , StoreLow , StoreHigh ) ; } Type * IntPtrTy = getTargetData ( ) -> getIntPtrType ( * DAG . getContext ( ) ) ; TargetLowering :: ArgListTy Args ; TargetLowering :: ArgListEntry Entry ; Entry . Ty = IntPtrTy ; Entry . Node = BasePtr ; Args . push_back ( Entry ) ; Entry . Node = Value ; Args . push_back ( Entry ) ; std :: pair < SDValue , SDValue > CallResult = LowerCallTo ( Chain , Type :: getVoidTy ( * DAG . getContext ( ) ) , false , false , false , false , <NUM_LIT> , CallingConv :: C , false , false , true , DAG

. getExternalSymbol ( <STR_LIT> , getPointerTy ( ) ) , Args , DAG , dl ) ;


<s> SmallVector < SDValue , <NUM_LIT> > OtherOps ; for ( unsigned i = <NUM_LIT> , e = N -> getNumOperands ( ) ; i != e ; ++ i ) OtherOps . push_back ( N -> getOperand ( i ) ) ; LoadSDNode * LD = cast < LoadSDNode > ( N ) ; OtherOps . push_back ( DAG . getIntPtrConstant ( LD -> getExtensionType ( ) ) ) ; SDValue NewLD = DAG . getMemIntrinsicNode ( Opcode , DL , LdResVTs , & OtherOps [ <NUM_LIT> ] , OtherOps . size ( ) , LD -> getMemoryVT ( ) , LD -> getMemOperand ( ) ) ; SmallVector < SDValue , <NUM_LIT> > ScalarRes ; for ( unsigned i = <NUM_LIT> ; i < NumElts ; ++ i ) { SDValue Res = NewLD . getValue ( i ) ; if ( NeedTrunc ) Res = DAG . getNode ( <STR_LIT> , DL , ResVT .


<s> if ( valtype_map [ i ] . valtype == VT ) { retval = valtype_map + i ; break ; } } if ( retval == <NUM_LIT> ) { cerr << <STR_LIT> << VT . getMVTString ( ) << <STR_LIT> ; abort ( ) ; } return retval


<s> int <ISA_LIT>FrameLowering :: getFrameIndexOffset ( const MachineFunction & MF , int FI ) const { const MachineFrameInfo * MFFrame = MF . getFrameInfo ( ) ; int64_t Offset = ( MFFrame -> getObjectOffset ( FI ) + MFFrame -> getOffsetAdjustment ( ) ) ; Offset -= getOffsetOfLocalArea ( ) ; Offset += getAllocatedStackSize ( MF ) ; return


<s> static const char * rs6000_call_template_1 ( rtx * operands , unsigned int funop , bool sibcall ) { gcc_assert ( funop <= MAX_RECOG_OPERANDS ) ; char arg [ <NUM_LIT> ] ; arg [ <NUM_LIT> ] = <NUM_LIT> ; if ( GET_CODE ( operands [ funop + <NUM_LIT> ] ) == UNSPEC ) { if ( XINT ( operands [ funop + <NUM_LIT> ] , <NUM_LIT> ) == UNSPEC_TLSGD ) sprintf ( arg , <STR_LIT> , funop + <NUM_LIT> ) ; else if ( XINT ( operands [ funop + <NUM_LIT> ] , <NUM_LIT> ) == UNSPEC_TLSLD ) sprintf ( arg , <STR_LIT> ) ; } char z [ <NUM_LIT> ] ; sprintf ( z , <STR_LIT> , funop , ( DEFAULT_ABI == ABI_V4 && TARGET_SECURE_PLT && flag_pic == <NUM_LIT> ? <STR_LIT> :


<s> const RegisterBank & RBFPR = getRegBank ( <STR_LIT> ) ; ( void ) RBFPR ; assert ( RBFPR . covers ( * TRI . getRegClass ( <STR_LIT> ) ) && <STR_LIT> ) ; assert ( RBFPR . covers ( * TRI . getRegClass ( <STR_LIT> ) ) && <STR_LIT> ) ; assert ( RBFPR . getSize ( ) == <NUM_LIT> && <STR_LIT> ) ; createRegisterBank ( <STR_LIT> , <STR_LIT> ) ; addRegBankCoverage ( <STR_LIT> , <STR_LIT> , TRI ) ; const RegisterBank & RBCCR = getRegBank ( <STR_LIT> ) ; ( void ) RBCCR ; assert ( RBCCR . covers ( * TRI . getRegClass ( <STR_LIT> ) ) && <STR_LIT> ) ; assert ( RBCCR . getSize ( ) == <NUM_LIT> &&


<s> Inst . addOperand ( Inst . getOperand ( <NUM_LIT> ) ) ; uint64_t UImm6 = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> | fieldFromInstruction ( Insn , <NUM_LIT>


<s> unsigned HwLen = Subtarget . getVectorLength ( ) ; unsigned WideOpLen = ( <NUM_LIT> * HwLen ) / ElemTy . getSizeInBits ( ) ; assert ( WideOpLen * ElemTy . getSizeInBits ( ) == <NUM_LIT> * HwLen ) ; MVT WideOpTy = <STR_LIT> ( ElemTy , WideOpLen ) ; if ( ! Subtarget . isHVXVectorType ( WideOpTy , true ) ) return SDValue ( ) ; SDValue WideOp0 = appendUndef ( Op0 , WideOpTy , DAG ) ; SDValue WideOp1 = appendUndef ( Op1 , WideOpTy , DAG ) ; EVT ResTy = getSetCCResultType ( DAG . getDataLayout ( ) , * DAG . getContext ( ) , WideOpTy ) ; SDValue SetCC = DAG . getNode ( <STR_LIT> , dl , ResTy , { WideOp0 , WideOp1 , Op . getOperand ( <NUM_LIT> ) } ) ; EVT RetTy = getTypeToTransformTo ( * DAG . getContext ( ) , ty ( Op ) ) ; return DAG . getNode ( <STR_LIT> , dl , RetTy , { SetCC , getZero ( dl , <STR_LIT> ,


<s> unsigned Opc = isThumb ? <STR_LIT> : <STR_LIT> ; AddDefaultCC ( AddDefaultPred ( BuildMI ( MBB , MI , DL , TII . get ( Opc ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> * NumAlignedDPRCS2Regs ) ) ) ; Opc = isThumb ? <STR_LIT> : <STR_LIT> ; unsigned MaxAlign = MF . getFrameInfo ( ) -> getMaxAlignment ( ) ; AddDefaultCC ( AddDefaultPred ( BuildMI ( MBB , MI , DL , TII . get ( Opc ) , <STR_LIT> ) . addReg ( <STR_LIT> , RegState :: Kill ) . addImm ( MaxAlign - <NUM_LIT> ) ) ) ; Opc = isThumb ? <STR_LIT> : <STR_LIT> ; MachineInstrBuilder MIB = BuildMI ( MBB , MI , DL , TII . get ( Opc ) , <STR_LIT> ) . addReg ( <STR_LIT> ) ; MIB = AddDefaultPred ( MIB ) ; if ( ! isThumb ) AddDefaultCC ( MIB ) ; unsigned NextReg = <STR_LIT> ; if ( NumAlignedDPRCS2Regs >= <NUM_LIT> ) { unsigned SupReg = TRI -> getMatchingSuperReg ( NextReg , <STR_LIT> , <STR_LIT> ) ; MBB . addLiveIn ( SupReg ) ; AddDefaultPred ( BuildMI ( MBB , MI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> , RegState :: Kill ) . addImm ( <NUM_LIT> ) . addReg ( NextReg ) . addReg ( SupReg , RegState :: ImplicitKill ) ) ; NextReg += <NUM_LIT> ; NumAlignedDPRCS2Regs -= <NUM_LIT> ; } unsigned R4BaseReg = NextReg ; if ( NumAlignedDPRCS2Regs >= <NUM_LIT> ) { unsigned SupReg = TRI -> getMatchingSuperReg ( NextReg , <STR_LIT> , <STR_LIT> ) ; MBB . addLiveIn ( SupReg ) ; AddDefaultPred ( BuildMI ( MBB , MI , DL , TII . get ( <STR_LIT> ) ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( NextReg ) . addReg ( SupReg , RegState :: ImplicitKill ) ) ; NextReg += <NUM_LIT> ; NumAlignedDPRCS2Regs -= <NUM_LIT> ; } if ( NumAlignedDPRCS2Regs >= <NUM_LIT> ) { unsigned SupReg = TRI -> getMatchingSuperReg ( NextReg , <STR_LIT> , <STR_LIT> ) ; MBB . addLiveIn ( SupReg ) ; AddDefaultPred ( BuildMI ( MBB , MI , DL , TII . get ( <STR_LIT> ) ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( NextReg ) . addReg ( SupReg , RegState :: ImplicitKill ) ) ; NextReg += <NUM_LIT> ; NumAlignedDPRCS2Regs -= <NUM_LIT> ; } if ( NumAlignedDPRCS2Regs ) { MBB . addLiveIn ( NextReg ) ; AddDefaultPred ( BuildMI ( MBB , MI , DL , TII . get ( <STR_LIT> ) ) . addReg ( NextReg ) . addReg ( <STR_LIT> ) . addImm ( ( NextReg - R4BaseReg ) * <NUM_LIT> ) ) ; } llvm :: prior ( MI ) -> addRegisterKilled ( <STR_LIT>


<s> __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT> ( b ) : ) ; return result


<s> assert ( SPAdj == <NUM_LIT> && <STR_LIT> ) ; MachineInstr & MI = * II ; MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; const <ISA_LIT>InstrInfo * TII = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getInstrInfo ( ) ; DebugLoc DL = MI . getDebugLoc ( ) ; int FrameIndex = MI . getOperand ( FIOperandNum ) . getIndex ( ) ; Register FrameReg ; int Offset = getFrameLowering ( MF ) -> getFrameIndexReference ( MF , FrameIndex , FrameReg ) + MI . getOperand ( FIOperandNum + <NUM_LIT> ) . getImm ( ) ; if ( ! isInt < <NUM_LIT> > ( Offset ) ) { report_fatal_error ( <STR_LIT> ) ; } MachineBasicBlock & MBB = * MI . getParent ( ) ; bool FrameRegIsKill = false ; if ( ! isInt < <NUM_LIT> > ( Offset ) ) { assert ( isInt < <NUM_LIT> > ( Offset ) && <STR_LIT> ) ; Register ScratchReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; TII -> movImm ( MBB , II , DL , ScratchReg , Offset ) ; BuildMI ( MBB , II , DL , TII -> get ( <STR_LIT> ) , ScratchReg ) . addReg ( FrameReg ) . addReg ( ScratchReg , RegState :: Kill ) ; Offset = <NUM_LIT> ; FrameReg = ScratchReg ; FrameRegIsKill = true


<s> SrcVT = <STR_LIT> ( ScalarTy , SrcSize / MaskEltSize ) ; if ( SrcVT . getSizeInBits ( ) != MaskVT . getSizeInBits ( ) ) V1 = extractSubVector ( V1 , <NUM_LIT> , DAG , DL , SrcSize ) ; Shuffle = unsigned ( MatchAny ? <STR_LIT> : <STR_LIT> ) ; if ( SrcVT . getVectorNumElements ( ) != NumDstElts ) Shuffle = getOpcode_EXTEND_VECTOR_INREG ( Shuffle ) ; DstVT = <STR_LIT> ( Scale * MaskEltSize ) ; DstVT = <STR_LIT> ( DstVT , NumDstElts ) ; return true ; } } } if ( ( ( MaskEltSize == <NUM_LIT> ) || ( MaskEltSize == <NUM_LIT> && Subtarget . hasSSE2 ( ) ) || ( MaskEltSize == <NUM_LIT> && Subtarget . hasFP16 ( ) ) ) && isUndefOrEqual ( Mask [ <NUM_LIT> ] , <NUM_LIT> ) && isUndefOrZeroInRange ( Mask , <NUM_LIT> , NumMaskElts - <NUM_LIT> ) ) { Shuffle = <STR_LIT> ; SrcVT = DstVT = MaskEltSize == <NUM_LIT> ? <STR_LIT> : ! Subtarget . hasSSE2 ( ) ? <STR_LIT> : MaskVT ; return true ; } if ( MaskVT . is128BitVector ( ) && Subtarget . hasSSE3 ( ) && AllowFloatDomain ) { if ( isTargetShuffleEquivalent ( MaskVT , Mask , { <NUM_LIT> , <NUM_LIT> } , V1 ) ) { Shuffle = <STR_LIT> ; SrcVT = DstVT = <STR_LIT> ; return true ; } if ( isTargetShuffleEquivalent ( MaskVT , Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , V1 ) ) { Shuffle = <STR_LIT> ; SrcVT = DstVT = <STR_LIT> ; return true ; } if ( isTargetShuffleEquivalent ( MaskVT , Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , V1 ) ) { Shuffle = <STR_LIT> ; SrcVT = DstVT = <STR_LIT> ; return true ; } } if ( MaskVT . is256BitVector ( ) && AllowFloatDomain ) { assert ( Subtarget . hasAVX ( ) && <STR_LIT> ) ; if ( isTargetShuffleEquivalent ( MaskVT , Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , V1 ) ) { Shuffle = <STR_LIT> ; SrcVT = DstVT = <STR_LIT> ; return true ; } if ( isTargetShuffleEquivalent ( MaskVT , Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> ,


<s> if ( const auto * Entry = ConvertCostTableLookup ( NEONVectorSelectTbl , ISD , SelCondTy . getSimpleVT ( ) , SelValTy . getSimpleVT ( ) ) ) return Entry -> Cost ; } std :: pair < int , MVT > LT = TLI -> getTypeLegalizationCost ( DL , ValTy ) ; return LT . first ; } int BaseCost = ST -> hasMVEIntegerOps ( ) && ValTy -> isVectorTy ( ) ? ST -> getMVEVectorCostFactor ( ) : <NUM_LIT> ; return BaseCost * BaseT :: getCmpSelInstrCost ( Opcode ,


<s> bool <ISA_LIT>AsmParser :: parseDirectiveFnEnd ( SMLoc L ) { if ( ! FnStartLoc . isValid ( ) ) return Error ( L , <STR_LIT> ) ; resetUnwindDirectiveParserState ( )


<s> return DAG . getNode ( <STR_LIT> , DL


<s> NewSrc = get<ISA_LIT>SubSuperRegister ( Src . getReg ( ) , <NUM_LIT> ) ; isKill = Src . isKill ( ) ; assert ( ! Src . isUndef ( ) && <STR_LIT> ) ; } else { NewSrc = MF . getRegInfo ( ) . createVirtualRegister ( RC ) ; MachineInstr * Copy = BuildMI ( * MI . getParent ( ) , MI , MI . getDebugLoc ( ) , get ( TargetOpcode :: COPY ) ) . addReg (

NewSrc , RegState :: Define | RegState :: Undef , <STR_LIT> ) . add ( Src ) ;


<s> Builder . buildNot ( MI . getOperand ( <NUM_LIT> ) , Sbc . getReg ( <NUM_LIT> ) ) ; } else { assert ( MI . getOpcode ( ) == <STR_LIT> ) ; auto Sbc = Builder . buildInstr ( <STR_LIT> , { S8 , S1 , S1 , S1 , S1 } , { MI . getOperand ( <NUM_LIT> ) , MI . getOperand ( <NUM_LIT> ) , CarryIn } ) ; Builder . setInsertPt ( Builder . getMBB ( ) , std :: next ( Builder . getInsertPt ( ) ) ) ; Builder . buildCopy ( MI . getOperand ( <NUM_LIT> ) , Sbc . getReg ( <NUM_LIT> ) ) ; Builder . buildCopy ( MI . getOperand ( <NUM_LIT> ) , Sbc . getReg ( <NUM_LIT> ) ) ; } MI . eraseFromParent ( ) ; return


<s> return ( getVecSize ( FInfo ) != <NUM_LIT> ) ? false : fold_recip ( CI , B , FInfo ) ; case <ISA_LIT>LibFunc :: EI_DIVIDE : assert ( ( FInfo . getPrefix ( ) == <ISA_LIT>LibFunc :: NATIVE || FInfo . getPrefix ( ) == <ISA_LIT>LibFunc :: HALF ) && <STR_LIT> ) ; return ( getVecSize ( FInfo ) != <NUM_LIT> ) ? false : fold_divide ( CI , B , FInfo ) ; case <ISA_LIT>LibFunc :: EI_POW : case <ISA_LIT>LibFunc :: EI_POWR : case <ISA_LIT>LibFunc :: EI_POWN : return fold_pow ( CI , B , FInfo ) ; case <ISA_LIT>LibFunc :: EI_ROOTN : return ( getVecSize ( FInfo ) != <NUM_LIT> ) ? false : fold_rootn ( CI , B , FInfo ) ; case <ISA_LIT>LibFunc :: EI_FMA : case <ISA_LIT>LibFunc :: EI_MAD : case <ISA_LIT>LibFunc :: EI_NFMA : return ( getVecSize ( FInfo ) != <NUM_LIT> ) ? false : fold_fma_mad (


<s> rtx cmp ; if ( GET_MODE ( * op0 ) == BImode ) { gcc_assert ( ( code == NE || code == EQ ) && * op1 == const0_rtx ) ; cmp = * op0 ; } else if ( TARGET_HPUX && GET_MODE ( * op0 ) == TFmode ) { enum qfcmp_magic { QCMP_INV = <NUM_LIT> , QCMP_UNORD = <NUM_LIT> , QCMP_EQ = <NUM_LIT> , QCMP_LT = <NUM_LIT> , QCMP_GT = <NUM_LIT> } ; int magic ; enum rtx_code ncode ; rtx ret , insns ; gcc_assert ( cmptf_libfunc && GET_MODE ( * op1 ) == TFmode ) ; switch ( code ) { case EQ : magic = QCMP_EQ ; ncode = NE ; break ; case NE : magic = QCMP_EQ ; ncode = EQ ; break ; case UNORDERED : magic = QCMP_UNORD ; ncode = NE ; break ; case ORDERED : magic = QCMP_UNORD ; ncode = EQ ; break ; case LT : magic = QCMP_LT | QCMP_INV ; ncode = NE ; break ; case LE : magic = QCMP_LT | QCMP_EQ | QCMP_INV ; ncode = NE ; break ; case GT : magic = QCMP_GT | QCMP_INV ; ncode = NE ; break ; case GE : magic = QCMP_GT | QCMP_EQ | QCMP_INV ; ncode = NE ; break ; case UNLT : magic = QCMP_LT | QCMP_UNORD ; ncode = NE ; break ; case UNLE : magic = QCMP_LT | QCMP_EQ | QCMP_UNORD ; ncode = NE ; break ; case UNGT : magic = QCMP_GT | QCMP_UNORD ; ncode = NE ; break ; case UNGE : magic = QCMP_GT | QCMP_EQ | QCMP_UNORD ; ncode = NE ; break ; case UNEQ : case LTGT : default : gcc_unreachable ( ) ; } start_sequence ( ) ; ret = emit_library_call_value ( cmptf_libfunc , <NUM_LIT> , LCT_CONST , DImode , <NUM_LIT> , * op0 , TFmode , * op1 , TFmode , GEN_INT ( magic ) , DImode ) ; cmp = gen_reg_rtx ( BImode ) ; emit_insn ( gen_rtx_SET ( cmp , gen_rtx_fmt_ee ( ncode , BImode , ret , const0_rtx ) ) ) ; insns = get_insns ( ) ; end_sequence ( ) ; emit_libcall_block ( insns , cmp , cmp , gen_rtx_fmt_ee ( code , BImode , * op0 , * op1 ) ) ; code = NE ; } else { cmp = gen_reg_rtx ( BImode ) ; emit_insn ( gen_rtx_SET ( cmp , gen_rtx_fmt_ee ( code , BImode , * op0 , * op1 ) ) ) ; code =


<s> const <ISA_LIT>InstrInfo * getInstrInfo ( ) const override { return & InstrInfo


<s> if ( Subtarget . isTargetWindowsMSVC ( ) && ! Subtarget . is64Bit ( ) && Arg . getSimpleValueType ( ) != <STR_LIT> ) Alignment = MaybeAlign ( <NUM_LIT> ) ; return DAG . getStore ( Chain , dl , Arg , PtrOff , MachinePointerInfo :: getStack

( DAG . getMachineFunction ( ) , LocMemOffset ) , Alignment ) ;


<s> regno = true_regnum ( x ) ; if ( GET_MODE_SIZE ( mode ) == <NUM_LIT> && reg_classes_intersect_p ( rclass , ADDR_REGS ) && ! ( INT_REGNO_P ( regno ) || CONSTANT_P (


<s> TargetPassConfig * <ISA_LIT>TargetMachine :: createPassConfig ( PassManagerBase & PM ) { return new <ISA_LIT>PassConfig ( this ,


<s> void cris_conditional_register_usage ( ) { if ( flag_pic ) fixed_regs [ PIC_OFFSET_TABLE_REGNUM ] = call_used_regs

[ PIC_OFFSET_TABLE_REGNUM ] = <NUM_LIT> ;


<s> if ( SubIdx == AMDGPU :: sub1 ) return MachineOperand :: CreateImm ( Op . getImm ( ) >> <NUM_LIT> ) ; llvm_unreachable ( <STR_LIT> ) ; } unsigned SubReg = buildExtractSubReg ( MII , MRI , Op , SuperRC , SubIdx


<s> Value * TIdZ = Builder . CreateCall ( ReadTIDIGZ , { } ) ; Value * Tmp0 = Builder . CreateMul ( TCntY , TCntZ ) ; Tmp0 = Builder . CreateMul ( Tmp0 , TIdX ) ; Value * Tmp1 = Builder . CreateMul ( TIdY , TCntZ ) ; Value * TID = Builder . CreateAdd ( Tmp0 , Tmp1 ) ; TID = Builder . CreateAdd ( TID , TIdZ ) ; std :: vector < Value * > Indices ; Indices . push_back ( Constant :: getNullValue ( Type :: getInt32Ty ( Mod -> getContext ( ) ) ) ) ; Indices . push_back ( TID ) ; Value * Offset = Builder . CreateGEP ( GVTy , GV , Indices ) ; I . mutateType ( Offset -> getType ( ) ) ; I . replaceAllUsesWith ( Offset ) ; I . eraseFromParent ( ) ; for ( std :: vector < Value * > :: iterator i = WorkList . begin ( ) , e = WorkList . end ( ) ; i != e ; ++ i ) { Value * V = * i ; CallInst * Call = dyn_cast < CallInst > ( V ) ; if ( ! Call ) { Type * EltTy = V -> getType ( ) -> getPointerElementType ( ) ; PointerType * NewTy = PointerType :: get ( EltTy , <ISA_LIT>AS :: LOCAL_ADDRESS ) ; if ( isa < AddrSpaceCastInst > ( V ) ) continue ; V -> mutateType ( NewTy ) ; continue ; } IntrinsicInst * Intr = dyn_cast < IntrinsicInst > ( Call ) ; if ( ! Intr ) { std :: vector < Type * > ArgTypes ; for ( unsigned ArgIdx = <NUM_LIT> , ArgEnd = Call -> getNumArgOperands ( ) ; ArgIdx != ArgEnd ; ++ ArgIdx ) { ArgTypes . push_back ( Call -> getArgOperand ( ArgIdx ) -> getType ( ) ) ; } Function * F = Call -> getCalledFunction ( ) ; FunctionType * NewType = FunctionType :: get ( Call -> getType ( ) , ArgTypes , F -> isVarArg ( ) ) ; Constant * C = Mod -> getOrInsertFunction ( ( F -> getName ( ) + <STR_LIT> ) . str ( ) , NewType , F -> getAttributes ( ) ) ; Function * NewF = cast < Function > ( C


<s> unsigned RegOut = get<ISA_LIT>SubSuperRegister ( RegIn , <STR_LIT> , false ) ; assert ( RegOut


<s> std :: vector < std :: string > cbs ( ArpRn1 a , ArpStep1 asi , ArpStep1 asj , CbsCond


<s> getParser ( ) . setAssemblerDialect ( <NUM_LIT> ) ; if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) { if ( Parser . getTok ( ) . getString ( ) == <STR_LIT> ) Parser . Lex ( ) ; else if ( Parser . getTok ( ) . getString ( ) == <STR_LIT> ) return Error ( DirectiveID . getLoc ( ) , <STR_LIT> <STR_LIT> <STR_LIT> ) ; } return false ; } return true


<s> return isSCSrcB64 ( ) || isLiteralImm


<s> ConstantFoldBinaryOpOperands ( BO . getOpcode ( ) , CT , CBO , * DL ) ; if ( isa < ConstantExpr > ( FoldedT ) ) return false ; Constant * FoldedF = SelOpNo ? ConstantFoldBinaryOpOperands ( BO . getOpcode ( ) , CBO , CF , * DL ) : ConstantFoldBinaryOpOperands ( BO . getOpcode ( ) , CF , CBO , * DL ) ; if ( isa < ConstantExpr > ( FoldedF ) ) return false ; IRBuilder < > Builder ( & BO ) ; Builder . SetCurrentDebugLocation ( BO . getDebugLoc ( ) ) ; if ( const FPMathOperator * FPOp = dyn_cast < const FPMathOperator > ( & BO ) ) Builder . setFastMathFlags ( FPOp -> getFastMathFlags ( ) ) ; Value * NewSelect = Builder . CreateSelect ( Sel -> getCondition ( ) , FoldedT , FoldedF ) ; NewSelect -> takeName ( & BO ) ; BO . replaceAllUsesWith


<s> assert ( Kind == k_VectorList && <STR_LIT> ) ; return VectorList .


<s> return ArgDescriptor ( Offset , Mask , true


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> unsigned getPrefetch ( ) const { assert ( Kind == k_Prefetch && <STR_LIT> ) ; return Prefetch .


<s> off = unw_decode_uleb128 ( & dp ) ; abreg = ( byte1 & <NUM_LIT> ) ; if ( byte1 & <NUM_LIT> ) UNW_DEC_SPILL_SPREL ( X1 , t


<s> BuildMI ( FirstMBB , MBBI , dl , TII . get ( <STR_LIT> ) , GlobalBaseReg ) ; unsigned TempReg = RegInfo -> createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( FirstMBB , MBBI , dl , TII . get ( <STR_LIT> ) , GlobalBaseReg ) . addReg ( TempReg , RegState :: Define ) . addReg ( GlobalBaseReg ) ; MF -> getInfo < <ISA_LIT>FunctionInfo > ( ) -> setUsesPICBase ( true ) ; } } else { GlobalBaseReg = RegInfo -> createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( FirstMBB , MBBI , dl , TII . get ( <STR_LIT> ) ) ; BuildMI ( FirstMBB , MBBI , dl , TII . get ( <STR_LIT> ) , GlobalBaseReg ) ; } } else { MF -> getInfo < <ISA_LIT>FunctionInfo > ( ) -> setShrinkWrapDisabled ( true ) ; GlobalBaseReg = RegInfo -> createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( FirstMBB , MBBI , dl , TII . get


<s> RegisterMCAsmParser < <ISA_LIT>AsmParser > X (


<s> rtx expand ( function_expander & e ) const override { int unspec = ( e . type_suffix ( <NUM_LIT> ) . unsigned_p ? m_unspec_for_uint : m_unspec_for_sint ) ; machine_mode pred_mode = e . vector_mode ( <NUM_LIT> ) ; scalar_mode reg_mode = GET_MODE_INNER ( e . vector_mode ( <NUM_LIT> ) ) ; return e . use_exact_insn ( code_for_while ( unspec , reg_mode ,


<s> if ( ! Subtarget -> isTargetDarwin ( ) ) return


<s> Register DestReg = MIIt -> getOperand ( <NUM_LIT> ) . getReg ( ) ; Register TrueReg = MIIt -> getOperand ( <NUM_LIT> ) . getReg ( ) ; Register FalseReg = MIIt -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( MIIt -> getOperand ( <NUM_LIT> ) . getImm ( ) == ( CCValid ^ CCMask ) ) std :: swap ( TrueReg , FalseReg ) ; if ( RegRewriteTable . find ( TrueReg ) != RegRewriteTable . end ( ) ) TrueReg = RegRewriteTable [ TrueReg ] . first ; if ( RegRewriteTable . find ( FalseReg ) != RegRewriteTable . end ( ) ) FalseReg = RegRewriteTable [


<s> return flatScratchIsArchitected ( ) || ( EnableFlatScratch && hasFlatScratchInsts (


<s> case <STR_LIT> : Reg = <STR_LIT> ; size = <NUM_LIT> ; break ; case <STR_LIT> : assert ( Subtarget -> is64Bit ( ) && <STR_LIT> ) ; Reg = <STR_LIT> ; size = <NUM_LIT> ; break ; } SDValue cpIn = DAG . getCopyToReg ( Op . getOperand ( <NUM_LIT> ) , DL , Reg , Op . getOperand ( <NUM_LIT> ) , SDValue ( ) ) ; SDValue Ops [ ] = { cpIn . getValue ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , DAG . getTargetConstant ( size , <STR_LIT>


<s> bool OptSize = Attr . hasFnAttr ( Attribute


<s> MDNode * CU = * DbgFinder . compile_unit_begin ( ) ; EmitDebugDirectives = true ; SwitchToCU ( CU )


<s> const DenseSet < StringRef > & getAttributes ( ) const override { return


<s> } } assert ( ( ( isFixed || isCSR ) || ! RegInfo -> needsStackRealignment ( MF ) || ! UseFP ) && <STR_LIT> <STR_LIT> ) ; if ( isSVE ) { int64_t OffsetToSVEArea = MFI . getStackSize ( ) - AFI -> getCalleeSavedStackSize ( ) ; StackOffset FPOffset = { ObjectOffset , <STR_LIT> } ; StackOffset SPOffset = SVEStackSize + StackOffset ( ObjectOffset , <STR_LIT> ) + StackOffset ( OffsetToSVEArea , <STR_LIT> ) ; if ( hasFP ( MF ) && ( SPOffset . getBytes ( ) || FPOffset . getScalableBytes ( ) < SPOffset . getScalableBytes ( ) || RegInfo -> needsStackRealignment ( MF ) ) ) { FrameReg = RegInfo -> getFrameRegister ( MF ) ; return FPOffset ; } FrameReg = RegInfo -> hasBasePointer ( MF ) ? RegInfo -> getBaseRegister ( ) : ( unsigned ) <STR_LIT> ; return SPOffset ; } StackOffset ScalableOffset = { } ; if ( UseFP && ! ( isFixed || isCSR ) ) ScalableOffset = - SVEStackSize ; if ( ! UseFP && ( isFixed || isCSR ) ) ScalableOffset = SVEStackSize ; if ( UseFP ) { FrameReg = RegInfo -> getFrameRegister ( MF ) ; return StackOffset ( FPOffset , <STR_LIT> ) + ScalableOffset ; } if ( RegInfo -> hasBasePointer ( MF ) ) FrameReg = RegInfo -> getBaseRegister ( ) ; else { assert ( ! MFI . hasVarSizedObjects ( ) && <STR_LIT> ) ; FrameReg = <STR_LIT> ; if ( canUseRedZone ( MF ) ) Offset -= AFI -> getLocalStackSize ( ) ; } return StackOffset ( Offset ,


<s> case <NUM_LIT> : break ; default : if ( AM . BaseOffs ) return false ; if ( ! VT . isSimple ( ) ) return false ; if ( Subtarget -> isThumb1Only ( ) ) return isLegalT1ScaledAddressingMode ( AM , VT ) ; if ( Subtarget -> isThumb2 ( ) ) return isLegalT2ScaledAddressingMode ( AM , VT ) ; int Scale = AM . Scale ; switch ( VT . getSimpleVT ( ) . SimpleTy ) { default : return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( Scale < <NUM_LIT> ) Scale = - Scale ; if ( Scale == <NUM_LIT> ) return true ; return isPowerOf2_32 ( Scale & ~ <NUM_LIT> ) ; case


<s> static void appendFoldCandidate ( SmallVectorImpl < FoldCandidate > & FoldList , MachineInstr * MI , unsigned OpNo , MachineOperand * FoldOp , bool Commuted = false , int ShrinkOp


<s> void <ISA_LIT>InstrInfo :: loadRegFromStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , unsigned DestReg , int FrameIdx , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { DebugLoc DL ; if ( MI != MBB . end ( ) ) DL = MI -> getDebugLoc ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( MF , FrameIdx ) , MachineMemOperand :: MOLoad , MFI . getObjectSize ( FrameIdx ) , MFI . getObjectAlignment ( FrameIdx ) ) ; BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) ) . addReg ( DestReg , getDefRegState ( true ) ) . addFrameIndex ( FrameIdx ) . addReg

( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ;


<s> bool <ISA_LIT>RegisterInfo :: hasReservedSpillSlot ( const MachineFunction & MF , Register Reg , int & FrameIdx ) const { if ( <STR_LIT> . contains ( Reg ) ) return true ; const <ISA_LIT>MachineFunctionInfo & PMFI = * MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; if ( Reg == <STR_LIT> && PMFI . getS0SpillReg ( ) ) return


<s> if ( ParseIntelExpression ( SM , End ) ) return nullptr ; int64_t Imm = SM . getImm ( ) ; if ( isParsingInlineAsm ( ) ) { unsigned Len = Tok . getLoc ( ) . getPointer ( ) - Start . getPointer ( ) ; if ( StartTok . getString ( ) . size ( ) == Len ) InstInfo -> AsmRewrites -> push_back ( AsmRewrite ( AOK_ImmPrefix , Start ) ) ; else InstInfo -> AsmRewrites -> push_back ( AsmRewrite ( AOK_Imm , Start , Len , Imm ) ) ; } if ( getLexer ( ) . isNot ( AsmToken :: LBrac ) ) { if ( SM . getSym ( ) ) return <STR_LIT> ( SM . getSym ( ) , Start , End , Size ) ; const MCExpr * ImmExpr = MCConstantExpr :: Create ( Imm , getContext ( ) ) ; return <STR_LIT> ( ImmExpr , Start , End ) ; } if ( Imm < <NUM_LIT> ) return ErrorOperand ( Start , <STR_LIT> <STR_LIT> ) ; return ParseIntelMemOperand ( Imm , Start , Size ) ; } unsigned RegNo = <NUM_LIT> ; if ( ! ParseRegister ( RegNo , Start , End ) ) { if ( getLexer ( ) . isNot ( AsmToken :: Colon ) ) return <STR_LIT> ( RegNo , Start , End ) ; return ParseIntelSegmentOverride ( RegNo ,


<s> L -> getLoopLatches ( Latches ) ; std :: vector < BasicBlock * > Preds ; for ( pred_iterator PI = pred_begin ( BB ) , PE = pred_end ( BB ) ; PI != PE ; ++ PI ) { if ( std :: find ( Latches . begin ( ) , Latches . end ( ) , * PI ) == Latches . end ( ) ) Preds . push_back ( * PI ) ; } BB = llvm :: SplitBlockPredecessors ( BB , Preds , <STR_LIT> , DT , LI , false ) ; } Value * Exec = popSaved ( ) ; if ( ! isa < UndefValue > ( Exec ) ) CallInst :: Create ( EndCf , Exec , <STR_LIT> , & *


<s> if ( S != MCDisassembler :: Success ) return Decode2OpInstructionFail ( Inst , Insn , Address , Decoder ) ; DecodeGRRegsRegisterClass ( Inst , Op1 , Address , Decoder ) ; DecodeGRRegsRegisterClass ( Inst , Op2 , Address , Decoder ) ; return S


<s> Triple TheTriple ( TT ) ; if ( TheTriple . isOSBinFormatMachO ( ) ) { MachO :: CPUSubType<ISA_LIT> CS = StringSwitch < MachO :: CPUSubType<ISA_LIT> > ( TheTriple . getArchName ( ) ) . Case ( <STR_LIT> , MachO :: CPU_SUBTYPE_<ISA_LIT>_64_H ) . Default ( MachO :: CPU_SUBTYPE_<ISA_LIT>_64_ALL ) ; return new Darwin<ISA_LIT>_64AsmBackend ( T , MRI , CPU , TheTriple . isMacOSX ( ) &&

! TheTriple . isMacOSXVersionLT ( <NUM_LIT> , <NUM_LIT> ) , CS ) ;


<s> vec < cl_deferred_option > * v = ( vec < cl_deferred_option > * ) mep_deferred_options ; if ( v ) FOR_EACH_VEC_ELT ( * v , i , opt ) { switch ( opt -> opt_index ) { case OPT_mivc2 : for ( j = <NUM_LIT> ; j < <NUM_LIT> ; j ++ ) fixed_regs [ j + <NUM_LIT> ] = <NUM_LIT> ; for ( j = <NUM_LIT> ; j < <NUM_LIT> ; j ++ ) call_used_regs [ j + <NUM_LIT> ] = <NUM_LIT> ; for ( j = <NUM_LIT> ; j < <NUM_LIT> ; j ++ ) call_used_regs [ j + <NUM_LIT> ] = <NUM_LIT> ; RN ( <NUM_LIT> , <STR_LIT> ) ; RN ( <NUM_LIT> , <STR_LIT> ) ; RN ( <NUM_LIT> , <STR_LIT> ) ; RN ( <NUM_LIT> , <STR_LIT> ) ; RN ( <NUM_LIT> , <STR_LIT> ) ; RN ( <NUM_LIT> , <STR_LIT> ) ; RN ( <NUM_LIT> , <STR_LIT> ) ; RN ( <NUM_LIT> , <STR_LIT> ) ; RN ( <NUM_LIT> , <STR_LIT> ) ; RN ( <NUM_LIT> , <STR_LIT> ) ; RN ( <NUM_LIT> , <STR_LIT> ) ; RN ( <NUM_LIT> , <STR_LIT> ) ; RN ( <NUM_LIT> , <STR_LIT> ) ; RN ( <NUM_LIT> , <STR_LIT> ) ; RN ( <NUM_LIT> , <STR_LIT> ) ; RN ( <NUM_LIT> , <STR_LIT> ) ; RN ( <NUM_LIT> , <STR_LIT> ) ; RN ( <NUM_LIT> , <STR_LIT> ) ; RN ( <NUM_LIT> , <STR_LIT> ) ; RN ( <NUM_LIT> , <STR_LIT> ) ; RN ( <NUM_LIT> , <STR_LIT> ) ; RN ( <NUM_LIT> , <STR_LIT> ) ; RN ( <NUM_LIT> , <STR_LIT> ) ; break ; default : gcc_unreachable ( ) ; } } if ( flag_pic == <NUM_LIT> ) warning ( OPT_fpic , <STR_LIT> ) ; if ( flag_pic == <NUM_LIT> ) warning ( OPT_fPIC , <STR_LIT> ) ; if ( TARGET_S && TARGET_M


<s> xa = ix86_expand_sse_fabs ( res , & mask ) ; label = ix86_expand_sse_compare_and_jump ( UNLE , TWO52 , xa , false ) ; xa2 = expand_simple_binop ( mode , PLUS , xa , TWO52 , NULL_RTX , <NUM_LIT> , OPTAB_DIRECT ) ; xa2 = expand_simple_binop ( mode , MINUS , xa2 , TWO52 , xa2 , <NUM_LIT> , OPTAB_DIRECT ) ; dxa = expand_simple_binop ( mode , MINUS , xa2 , xa , NULL_RTX , <NUM_LIT> , OPTAB_DIRECT ) ; half = force_reg ( mode , const_double_from_real_value ( dconsthalf , mode ) ) ; one = expand_simple_binop ( mode , PLUS , half , half , NULL_RTX , <NUM_LIT> , OPTAB_DIRECT ) ; mhalf = expand_simple_binop ( mode , MINUS , half , one , NULL_RTX , <NUM_LIT> , OPTAB_DIRECT ) ; tmp = gen_reg_rtx ( mode ) ; tmp = ix86_expand_sse_compare_mask ( UNGT , dxa , half , false ) ; emit_insn ( gen_rtx_SET ( VOIDmode , tmp , gen_rtx_AND ( mode , one , tmp ) ) ) ; xa2 = expand_simple_binop ( mode , MINUS , xa2 , tmp , NULL_RTX , <NUM_LIT> , OPTAB_DIRECT ) ; tmp = ix86_expand_sse_compare_mask ( UNGE , mhalf , dxa , false ) ; emit_insn ( gen_rtx_SET ( VOIDmode , tmp , gen_rtx_AND ( mode , one , tmp ) ) ) ; xa2 = expand_simple_binop ( mode , PLUS , xa2 , tmp , NULL_RTX , <NUM_LIT> , OPTAB_DIRECT ) ; ix86_sse_copysign_to_positive ( res , xa2 , force_reg ( mode ,


<s> int64_t getHwregId ( const StringRef Name ) { for ( int Id = ID_SYMBOLIC_FIRST_ ; Id < ID_SYMBOLIC_LAST_ ; ++ Id ) { if ( IdSymbolic [ Id ] && Name ==


<s> LiveInterval & LI = LIS -> getInterval ( Reg ) ; for ( LiveInterval :: iterator I = LI . begin ( ) , E = LI . end ( ) ; I != E ; ++ I ) { if ( ! I -> start . isRegister ( ) || ! I -> end . isBlock ( ) ) continue ; MachineInstr * MI = LIS -> getInstructionFromIndex ( I -> start ) ; Defs . push_back ( MI ) ; } } else if ( S . isRegister ( ) ) { MachineInstr * MI = LIS -> getInstructionFromIndex ( S ) ; Defs . push_back ( MI ) ; } for ( unsigned i = <NUM_LIT> , n = Defs . size ( ) ; i < n ; ++ i ) { MachineInstr * MI = Defs [ i ] ; for ( auto & Op : MI -> operands ( ) ) { if ( ! Op . isReg ( ) || ! Op . isDef ( ) ||