<s> MachineInstr * BaseHiDef = MRI -> getUniqueVRegDef ( BaseHi . getReg ( ) ) ; if ( ! BaseLoDef || BaseLoDef -> getOpcode ( ) != <STR_LIT> || ! BaseHiDef || BaseHiDef -> getOpcode ( ) != <STR_LIT> ) return ; const auto * Src0 = TII -> getNamedOperand ( * BaseLoDef , <STR_LIT> :: src0 ) ; const auto * Src1 = TII -> getNamedOperand ( * BaseLoDef , <STR_LIT> :: src1 ) ; auto Offset0P = extractConstOffset ( * Src0 ) ; if ( Offset0P ) BaseLo = * Src1 ; else { if ( ! ( Offset0P = extractConstOffset ( * Src1 ) ) ) return ; BaseLo = * Src0 ; } Src0 = TII -> getNamedOperand ( * BaseHiDef , <STR_LIT> :: src0 ) ; Src1 = TII -> getNamedOperand ( * BaseHiDef , <STR_LIT> :: src1 ) ; if ( Src0 -> isImm ( ) ) std :: swap ( Src0 , Src1 ) ; if ( ! Src1 -> isImm ( ) ) return ; uint64_t Offset1 = Src1 -> getImm


<s> SelectAndParts32 ( dl , Res , InstCnt ) ; if ( ( ! HasZeros || LateMask ) && ! Res ) { ValueRotInfo & VRI = ValueRotsVec [ <NUM_LIT> ] ; if ( VRI . RLAmt ) { if ( InstCnt ) * InstCnt += <NUM_LIT> ; SDValue Ops [ ] = { VRI . V , getI32Imm ( VRI . RLAmt ) , getI32Imm ( <NUM_LIT> ) , getI32Imm ( <NUM_LIT> ) } ; Res = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , Ops ) , <NUM_LIT> ) ; } else { Res = VRI . V ; } for ( auto I = BitGroups . begin ( ) ; I != BitGroups . end ( ) ; ) { if ( I -> V == VRI . V && I -> RLAmt == VRI . RLAmt ) I = BitGroups . erase ( I ) ; else ++ I ; } } if ( InstCnt ) * InstCnt += BitGroups . size ( ) ; for ( auto & BG : BitGroups ) { if ( ! Res ) { SDValue Ops [ ] = { BG . V , getI32Imm ( BG . RLAmt ) , getI32Imm ( Bits . size ( ) - BG . EndIdx - <NUM_LIT> ) , getI32Imm ( Bits . size ( ) - BG . StartIdx - <NUM_LIT> ) } ; Res = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , Ops ) , <NUM_LIT> ) ; } else { SDValue Ops [ ] = { Res , BG . V , getI32Imm ( BG . RLAmt ) , getI32Imm ( Bits . size ( ) - BG . EndIdx - <NUM_LIT> ) , getI32Imm ( Bits . size ( ) - BG . StartIdx - <NUM_LIT> ) } ; Res = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , Ops ) , <NUM_LIT> ) ; } } if ( LateMask ) { unsigned Mask = ( unsigned ) getZerosMask ( ) ; unsigned ANDIMask = ( Mask & UINT16_MAX ) , ANDISMask = Mask >> <NUM_LIT> ; assert ( ( ANDIMask != <NUM_LIT> || ANDISMask != <NUM_LIT> ) && <STR_LIT> ) ; if ( InstCnt ) * InstCnt += ( unsigned ) ( ANDIMask != <NUM_LIT> ) + ( unsigned ) ( ANDISMask != <NUM_LIT> ) + ( unsigned ) ( ANDIMask != <NUM_LIT> && ANDISMask != <NUM_LIT> ) ; SDValue ANDIVal


<s> code = GET_CODE ( x ) ; switch ( code ) { case REG : if ( REGNO ( x ) < <NUM_LIT> ) return ( ( ( <NUM_LIT> << hard_regno_nregs ( <NUM_LIT> , GET_MODE ( x ) ) ) - <NUM_LIT> ) << ( REGNO ( x ) + is_dest ) ) ; return <NUM_LIT> ; case SUBREG : { rtx y = SUBREG_REG ( x ) ; if ( ! REG_P ( y ) ) break ; if ( REGNO ( y ) < <NUM_LIT> ) return ( ( ( <NUM_LIT> << hard_regno_nregs ( <NUM_LIT> , GET_MODE ( x ) ) ) - <NUM_LIT> ) << ( REGNO ( y ) + subreg_regno_offset ( REGNO ( y ) , GET_MODE ( y ) , SUBREG_BYTE ( x ) , GET_MODE ( x ) ) + is_dest ) ) ; return <NUM_LIT> ; } case SET : return regs_used ( SET_SRC ( x ) , <NUM_LIT> ) | regs_used ( SET_DEST ( x ) , <NUM_LIT> ) ; case RETURN : return <NUM_LIT> ; case CLOBBER


<s> static int64_t getBaseAdjustForCompression ( int64_t Offset , unsigned Opcode ) { return Offset & ~ compressedLDSTOffsetMask ( Opcode


<s> return ( regno == <NUM_LIT> || regno == <NUM_LIT> || regno


<s> machine_mode inner_mode = GET_MODE_INNER ( mode ) ; rtx x ; if ( ! const_vec_duplicate_p ( vals , & x ) ) return NULL_RTX ; x = copy_to_mode_reg ( inner_mode , x ) ; return gen_rtx_VEC_DUPLICATE ( mode , x


<s> return ! Is64Bit && IsTailCall && getTargetMachine ( ) . getRelocationModel ( ) == Reloc

:: PIC_ && Subtarget -> isPICStyleGOT ( ) ;


<s> I != E ; ++ I ) { if ( ! MFI . isDeadObjectIndex ( I ) && MFI . getStackID ( I ) == TargetStackID :: SGPRSpill && ( I != FuncInfo -> FramePointerSaveIndex && I != FuncInfo -> BasePointerSaveIndex ) ) { return false ; } } return true


<s> delete static_cast < <ISA_LIT>Section * > ( DwarfFrameSection ) ; delete static_cast < <ISA_LIT>Section * > ( DwarfPubTypesSection ) ; delete static_cast < const <ISA_LIT>Section * > ( DwarfDebugInlineSection ) ; delete static_cast < <ISA_LIT>Section * > ( DwarfStrSection ) ; delete static_cast < <ISA_LIT>Section * > ( DwarfLocSection ) ; delete static_cast < <ISA_LIT>Section * >


<s> void <ISA_LIT>InstPrinter :: printBarrierOption ( const MCInst * MI , unsigned OpNo , raw_ostream & O ) { unsigned Val = MI -> getOperand ( OpNo ) . getImm ( ) ; unsigned Opcode = MI -> getOpcode ( ) ; bool Valid ; StringRef Name ; if ( Opcode == <STR_LIT> ) Name = <STR_LIT> ( ) . toString ( Val , Valid ) ; else Name = <STR_LIT> ( ) . toString ( Val ,


<s> assert ( ( Cond . size ( ) == <NUM_LIT> || Cond . size ( ) == <NUM_LIT> ) && <STR_LIT> ) ; if ( ! FBB ) { if ( Cond . empty ( ) ) BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addMBB ( TBB ) ; else BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addReg ( Cond [ <NUM_LIT> ] . getReg ( ) ) . addMBB ( TBB ) ; return <NUM_LIT> ; } BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addReg ( Cond [ <NUM_LIT> ] . getReg ( ) ) . addMBB ( TBB ) ; BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) .


<s> } if ( FalseC -> getAPIntValue ( ) == <NUM_LIT> && TrueC -> getAPIntValue ( ) . isPowerOf2 ( ) ) { SDValue Cond = N -> getOperand ( <NUM_LIT> ) ; Cond = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getConstant ( CC , <STR_LIT> ) , Cond ) ; Cond = DAG . getNode ( <STR_LIT> , DL , TrueC -> getValueType ( <NUM_LIT> ) , Cond ) ; unsigned ShAmt = TrueC -> getAPIntValue ( ) . logBase2 ( ) ; Cond = DAG . getNode ( <STR_LIT> , DL , Cond . getValueType ( ) , Cond , DAG . getConstant ( ShAmt , <STR_LIT> ) ) ; if ( N -> getNumValues ( ) == <NUM_LIT> ) return DCI . CombineTo ( N , Cond , SDValue ( ) ) ; return Cond ; } if ( FalseC -> getAPIntValue ( ) + <NUM_LIT> == TrueC -> getAPIntValue ( ) ) { SDValue Cond = N -> getOperand ( <NUM_LIT> ) ; Cond = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getConstant ( CC , <STR_LIT> ) , Cond ) ; Cond = DAG . getNode ( <STR_LIT> , DL , FalseC -> getValueType ( <NUM_LIT> ) , Cond ) ; Cond = DAG . getNode ( <STR_LIT> , DL , Cond . getValueType ( ) , Cond , SDValue ( FalseC , <NUM_LIT> ) ) ; if ( N -> getNumValues ( ) == <NUM_LIT> ) return DCI . CombineTo ( N , Cond , SDValue ( ) ) ; return Cond ; } if ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT> || N -> getValueType ( <NUM_LIT> ) == <STR_LIT> ) { uint64_t Diff = TrueC -> getZExtValue ( ) - FalseC -> getZExtValue ( ) ; if ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT> ) Diff = ( unsigned ) Diff ; bool isFastMultiplier = false ; if ( Diff < <NUM_LIT> ) { switch ( ( unsigned char ) Diff ) { default : break ; case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : isFastMultiplier =


<s> bool GCNSubtarget :: useVGPRIndexMode


<s> const unsigned MaxNonSmrdLoadSize = <NUM_LIT> ; if ( LoadSize <= MaxNonSmrdLoadSize ) return false ; SmallVector < unsigned , <NUM_LIT> > DefRegs ( OpdMapper . getVRegs ( <NUM_LIT> ) ) ; SmallVector < unsigned , <NUM_LIT> > SrcRegs ( OpdMapper . getVRegs ( <NUM_LIT> ) ) ; if ( SrcRegs . empty ( ) ) { const RegisterBank * PtrBank = OpdMapper . getInstrMapping ( ) . getOperandMapping ( <NUM_LIT> ) . BreakDown [ <NUM_LIT> ] . RegBank ; if ( PtrBank == & <STR_LIT> ) return false ; SrcRegs . push_back ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; } assert ( LoadSize % MaxNonSmrdLoadSize == <NUM_LIT> ) ; Register BasePtrReg = SrcRegs [ <NUM_LIT> ] ; LLT PtrTy = MRI . getType ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; MRI . setType ( BasePtrReg , PtrTy ) ; MachineIRBuilder B ( MI ) ; unsigned NumSplitParts = LoadTy . getSizeInBits ( ) / MaxNonSmrdLoadSize ; const LLT LoadSplitTy = LoadTy . divide ( NumSplitParts ) ; ApplyRegBankMapping O ( * this , MRI , & <STR_LIT> ) ; GISelObserverWrapper Observer ( & O ) ; B . setChangeObserver ( Observer ) ; LegalizerHelper Helper ( B . getMF ( ) ,


<s> if ( auto * Cast = dyn_cast < BitCastInst > ( Op0 ) ) { if ( ! Cast -> getSrcTy ( ) -> isFloatTy ( ) && ! Cast -> getSrcTy ( ) -> isDoubleTy ( ) && ! Cast -> getSrcTy ( ) -> isFP128Ty ( ) ) return ; Value * V = Cast -> getOperand ( <NUM_LIT> ) ; int Mask ; if ( Pred == CmpInst :: ICMP_SLT && Const -> isZero ( ) ) { Mask = <STR_LIT> ; } else if ( Pred == CmpInst :: ICMP_SGT && Const -> isMinusOne ( ) ) { Mask = <STR_LIT> ; } else { return ; } PossibleJunk . insert ( Cast ) ; converted ( & I , V , Mask , true ) ; } else if ( auto * CI = dyn_cast < CallInst > ( Op0 ) ) { Function * F = CI -> getCalledFunction ( ) ; if ( ! F || F -> getIntrinsicID ( ) != <STR_LIT> ) return ; if ( ! Const -> isZero ( ) ) return ; Value * V = CI -> getArgOperand ( <NUM_LIT> ) ; auto * MaskC = dyn_cast < ConstantInt > ( CI -> getArgOperand ( <NUM_LIT> ) ) ; if ( ! MaskC ) return ; int Mask = MaskC -> getZExtValue ( ) ; Mask &= <STR_LIT> ; if ( Pred == CmpInst :: ICMP_NE ) { } else if ( Pred == CmpInst :: ICMP_EQ ) { Mask ^=


<s> } if ( ! HasPads ) return false ; Type * Int8PtrType = Type :: getInt8PtrTy ( TheModule -> getContext ( ) ) ; SetJmp3 = TheModule -> getOrInsertFunction ( <STR_LIT> , FunctionType :: get ( Type :: getInt32Ty ( TheModule -> getContext ( ) ) , { Int8PtrType , Type :: getInt32Ty ( TheModule -> getContext ( ) ) } , true ) ) ; F . addFnAttr ( <STR_LIT> , <STR_LIT> ) ; emitExceptionRegistrationRecord ( & F ) ; WinEHFuncInfo FuncInfo ; addStateStores ( F , FuncInfo


<s> if ( VT . getSimpleVT ( ) == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , dl , VT , Val ) ; return SDValue (


<s> cum -> arg_words += ( ( int_size_in_bytes ( type ) + UNITS_PER_WORD - <NUM_LIT> ) / UNITS_PER_WORD ) ; break ; case E_SFmode : cum -> arg_words ++ ; if ( ! cum -> gp_reg_found && cum -> arg_number <= <NUM_LIT> ) cum -> fp_code += <NUM_LIT> << ( ( cum -> arg_number - <NUM_LIT> ) * <NUM_LIT> ) ; break ; case E_DFmode : cum -> arg_words += <NUM_LIT> ; if ( ! cum -> gp_reg_found && cum -> arg_number <= <NUM_LIT> ) cum -> fp_code += <NUM_LIT> << ( ( cum -> arg_number - <NUM_LIT> ) * <NUM_LIT> ) ; break ; case


<s> static __inline qword si_ilh ( signed short imm ) { return ( ( qword ) ( vec_splat ( ( vec_short8 ) ( si_from_short ( imm )


<s> static MCInstPrinter * create<ISA_LIT>MCInstPrinter ( const Triple & T , unsigned SyntaxVariant , const MCAsmInfo & MAI , const MCInstrInfo & MII , const MCRegisterInfo & MRI ) { assert ( SyntaxVariant == <NUM_LIT> ) ; return new <ISA_LIT>InstPrinter ( MAI , MII ,


<s> SDLoc SL ( N ) ; SDValue LHS = N -> getOperand ( <NUM_LIT> ) ; SDValue RHS = N -> getOperand ( <NUM_LIT> ) ; EVT VT = LHS . getValueType ( ) ; if ( VT != <STR_LIT> && VT != <STR_LIT> ) return SDValue ( ) ; <STR_LIT> CC = cast < CondCodeSDNode > ( N -> getOperand ( <NUM_LIT> ) ) -> get ( ) ; if ( CC == <STR_LIT> && LHS . getOpcode ( ) == <STR_LIT> ) { const ConstantFPSDNode * CRHS = dyn_cast < ConstantFPSDNode > ( RHS ) ; if ( ! CRHS ) return SDValue ( ) ; const APFloat & APF = CRHS -> getValueAPF ( ) ; if ( APF . isInfinity ( ) && ! APF . isNegative ( ) ) { unsigned Mask = <STR_LIT> | <STR_LIT> ; return DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , LHS . getOperand ( <NUM_LIT> ) , DAG . getConstant ( Mask , <STR_LIT>


<s> } else { if ( ( Addr . getOpcode ( ) == <STR_LIT> || Addr . getOpcode ( ) == <STR_LIT> ) ) return false ; } if ( Addr . getOpcode ( ) == <STR_LIT> ) { if ( ConstantSDNode * CN = dyn_cast < ConstantSDNode > ( Addr . getOperand ( <NUM_LIT> ) ) ) { if ( isUInt < <NUM_LIT> > ( CN -> getZExtValue ( ) ) ) { if ( FrameIndexSDNode * FIN = dyn_cast < FrameIndexSDNode > ( Addr . getOperand ( <NUM_LIT> ) ) ) { Base = CurDAG -> getTargetFrameIndex ( FIN -> getIndex ( ) , <STR_LIT> ) ; } else { Base = Addr . getOperand ( <NUM_LIT> ) ; } Offset = CurDAG -> getTargetConstant ( CN -> getZExtValue ( ) , <STR_LIT> ) ; return true ; } } } Base = Addr ; Offset = CurDAG -> getTargetConstant ( <NUM_LIT> , <STR_LIT> ) ; return true


<s> Arg = DAG . getNode ( <STR_LIT> , DL , VA . getLocVT ( ) , Arg ) ; break ; case CCValAssign :: AExt : Arg = DAG . getNode ( <STR_LIT> , DL , VA . getLocVT ( ) , Arg ) ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } Chain = DAG . getCopyToReg ( Chain , DL , VA . getLocReg ( ) , Arg , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( VA . getLocReg ( ) , VA . getLocVT ( ) ) ) ; } if ( ! Info -> isEntryFunction ( ) ) { const <ISA_LIT>RegisterInfo * TRI = Subtarget -> getRegisterInfo ( ) ; const MCPhysReg * I = TRI -> getCalleeSavedRegsViaCopy ( & DAG . getMachineFunction ( ) ) ; if ( I ) { for ( ; * I ; ++ I ) { if ( <STR_LIT> . contains ( * I ) ) RetOps . push_back ( DAG . getRegister ( * I , <STR_LIT> ) ) ; else if ( <STR_LIT> . contains ( * I ) ) RetOps . push_back ( DAG . getRegister ( * I , <STR_LIT> ) ) ; else llvm_unreachable ( <STR_LIT> ) ; } } } RetOps [ <NUM_LIT> ] = Chain ; if ( Flag . getNode ( ) ) RetOps . push_back ( Flag ) ; unsigned Opc =


<s> static MachineOperand & GetStoreValueOperand ( MachineInstr * MI


<s> int64_t encodeDfmtNfmt ( unsigned Dfmt , unsigned


<s> subrtx_iterator :: array_type array ; FOR_EACH_SUBRTX ( iter , array , PATTERN ( insn ) , NONCONST ) if ( MEM_P ( * iter ) ) return true ; return


<s> RegisterSet SRs ; if ( R . Sub != <NUM_LIT> ) { SRs . insert ( R ) ; return SRs ; } if ( Register :: isPhysicalRegister ( R . Reg ) ) { MCSubRegIterator I ( R . Reg , & TRI ) ; if ( ! I . isValid ( ) ) SRs . insert ( { R . Reg , <NUM_LIT> } ) ; for ( ; I . isValid ( ) ; ++ I ) SRs . insert ( { * I , <NUM_LIT> } ) ; } else { assert ( R . Reg . isVirtual ( ) ) ; auto & RC = * MRI . getRegClass ( R . Reg ) ; unsigned PReg = * RC . begin ( ) ; MCSubRegIndexIterator I ( PReg


<s> output_addr_const ( stream , plus_constant ( Pmode , unspec -> symbol , unspec -> offset


<s> return CreateReg ( Index , Str , RegKind_MSA128 , RegInfo


<s> MachineBasicBlock :: iterator <ISA_LIT>OptimizeExecMaskingPreRA :: skipIgnoreExecInsts ( MachineBasicBlock :: iterator I , MachineBasicBlock :: iterator E ) const { for ( ; I != E ; ++ I ) { if ( TII -> mayReadEXEC ( * MRI , *


<s> EVT ResTy = Op -> getValueType ( <NUM_LIT> ) ; SDLoc DL ( Op ) ; SDValue One = DAG . getConstant ( <NUM_LIT> , ResTy ) ; SDValue Bit = DAG . getNode ( <STR_LIT> , DL , ResTy , One , Op -> getOperand ( <NUM_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , DL , ResTy , Op -> getOperand ( <NUM_LIT> ) , DAG


<s> getBitfieldInvertedMaskOpValue ( const MCInst & MI , unsigned Op , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { const MCOperand & MO = MI . getOperand ( Op ) ; uint32_t v = ~ MO . getImm ( ) ; uint32_t lsb = countTrailingZeros ( v ) ; uint32_t msb = ( <NUM_LIT> - countLeadingZeros ( v ) ) - <NUM_LIT> ; assert ( v != <NUM_LIT> && lsb < <NUM_LIT> && msb < <NUM_LIT> && <STR_LIT> ) ; return lsb | ( msb <<


<s> emitGRX32Move ( * MI . getParent ( ) , MI , MI . getDebugLoc ( ) , DestReg , SrcReg , <STR_LIT> , <NUM_LIT> , MI . getOperand ( <NUM_LIT> ) . isKill ( ) , MI . getOperand ( <NUM_LIT> ) . isUndef ( ) ) ; MI . setDesc ( get ( DestIsHigh ? HighOpcode : LowOpcode ) ) ; MI . getOperand ( <NUM_LIT> ) . setReg ( DestReg ) ; MI . tieOperands ( <NUM_LIT> , <NUM_LIT>


<s> void addUImm2Operands ( MCInst & Inst , unsigned N ) const { addImmOperands ( Inst ,


<s> if ( rl78_far_p ( operands [ <NUM_LIT> ] ) ) { rtx temp_reg = gen_reg_rtx ( GET_MODE ( operands [ <NUM_LIT> ] ) ) ; emit_move_insn ( temp_reg , operands [ <NUM_LIT> ] ) ; operands [ <NUM_LIT> ] = temp_reg ; did = <NUM_LIT> ; } if ( rl78_far_p ( operands [ <NUM_LIT> ] ) ) { temp_reg = operands [ <NUM_LIT> ] ; operands [ <NUM_LIT> ] = gen_reg_rtx ( GET_MODE ( operands [ <NUM_LIT> ] ) ) ; did = <NUM_LIT> ; } if ( ! did ) return <NUM_LIT> ; emit_insn ( gen ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ) ; if ( temp_reg ) emit_move_insn ( temp_reg , operands [ <NUM_LIT> ] ) ; return


<s> DAG -> addMutation ( createLoadClusterDAGMutation ( DAG -> TII , DAG -> TRI ) ) ; DAG -> addMutation ( createStoreClusterDAGMutation ( DAG -> TII , DAG -> TRI ) ) ; return


<s> return StringRef ( Tok . Data , Tok .


<s> std :: string lowerCase = Tok . getString ( ) . lower ( ) ; RegNum = matchRegisterName ( lowerCase , is64BitReg ) ; } else if ( Tok . is ( AsmToken :: Integer ) ) RegNum = matchRegisterByNumber ( static_cast < unsigned > ( Tok . getIntVal ( ) ) , is64BitReg ? <STR_LIT> : <STR_LIT> ) ; return RegNum


<s> unsigned <ISA_LIT>RegisterInfo :: getEHHandlerRegister ( ) const { llvm_unreachable ( <STR_LIT> ) ; return <NUM_LIT>


<s> SDValue Op0 = N -> getOperand ( <NUM_LIT> ) ; SDValue Op1 = N -> getOperand ( <NUM_LIT> ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( ! VT . isVector ( ) ) return SDValue ( ) ; EVT EltVT = VT . getVectorElementType ( ) ; if ( ! ( Subtarget . hasSSE2 ( ) && ( EltVT == <STR_LIT> || EltVT == <STR_LIT> ) ) && ! ( Subtarget . hasSSSE3 ( ) && ( VT == <STR_LIT> || VT == <STR_LIT> ) ) && ! ( Subtarget . useBWIRegs ( ) && ( VT == <STR_LIT> ) ) ) return SDValue ( ) ; SDValue SubusLHS , SubusRHS ; if ( Op0 . getOpcode ( ) == <STR_LIT> ) { SubusRHS = Op1 ; SDValue MaxLHS = Op0 . getOperand ( <NUM_LIT> ) ; SDValue MaxRHS = Op0 . getOperand ( <NUM_LIT> ) ; if ( MaxLHS == Op1 ) SubusLHS = MaxRHS ; else if ( MaxRHS == Op1 ) SubusLHS = MaxLHS ; else return SDValue ( ) ; } else if ( Op1 . getOpcode ( ) == <STR_LIT> ) { SubusLHS = Op0 ; SDValue MinLHS = Op1 . getOperand ( <NUM_LIT> ) ; SDValue MinRHS = Op1 . getOperand ( <NUM_LIT> ) ; if ( MinLHS == Op0 ) SubusRHS = MinRHS ; else if ( MinRHS == Op0 ) SubusRHS = MinLHS ; else return SDValue ( ) ; } else if ( Op1 . getOpcode ( ) == <STR_LIT> && Op1 . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> && ( EltVT == <STR_LIT> || EltVT == <STR_LIT> ) ) { SubusLHS = Op0 ; SDValue MinLHS = Op1 . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ; SDValue MinRHS = Op1 . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ; EVT TruncVT = Op1 . getOperand ( <NUM_LIT> ) .


<s> MachineInstr * MI = & * MBBI ; <STR_LIT> CC = getPredicate ( MI , TII ) ; if ( CC == <STR_LIT> ) { ++ MBBI ; continue ; } DebugLoc dl = MI -> getDebugLoc ( ) ; MachineInstrBuilder MIB = BuildMI ( MBB , MBBI , dl , TII -> get ( <STR_LIT> ) ) . addImm ( CC ) ; ++ MBBI ; <STR_LIT> OCC = <STR_LIT> ( CC ) ; unsigned Mask = <NUM_LIT> , Pos = <NUM_LIT> ; while ( MBBI != E && Pos ) { <STR_LIT> NCC = getPredicate ( & * MBBI , TII ) ; if ( NCC == OCC ) { Mask |= ( <NUM_LIT> << Pos ) ; } else if ( NCC != CC ) break ; -- Pos ; ++ MBBI ; } Mask |= ( <NUM_LIT> << Pos ) ; MIB . addImm ( Mask ) ; Modified = true ; ++ NumITs


<s> } if ( TT . isOSFreeBSD ( ) ) return llvm :: make_unique < <ISA_LIT>FreeBSDTargetObjectFile > ( ) ; if ( TT . isOSLinux ( ) || TT . isOSNaCl ( ) || TT . isOSIAMCU ( ) ) return llvm :: make_unique < <ISA_LIT>LinuxNaClTargetObjectFile > ( ) ; if ( TT . isOSSolaris ( ) ) return llvm :: make_unique < <ISA_LIT>SolarisTargetObjectFile > ( ) ; if ( TT . isOSFuchsia ( ) ) return llvm :: make_unique < <ISA_LIT>FuchsiaTargetObjectFile > ( ) ; if ( TT . isOSBinFormatELF ( ) ) return llvm :: make_unique < <ISA_LIT>ELFTargetObjectFile > ( ) ; if ( TT . isOSBinFormatCOFF ( ) ) return llvm :: make_unique < TargetLoweringObjectFileCOFF > ( ) ; llvm_unreachable ( <STR_LIT>


<s> unsigned getMaxInlineSizeThreshold ( ) const { return MaxInlineSizeThreshold


<s> auto Subtarget = TLI . getSubtarget ( ) ; if ( Subtarget -> isThumb1Only ( ) ) return false ; if ( F . arg_empty ( ) ) return true ; if ( F . isVarArg ( ) ) return false ; auto & MF = MIRBuilder . getMF ( ) ; auto & MBB = MIRBuilder . getMBB ( ) ; auto DL = MF . getDataLayout ( ) ; for ( auto & Arg : F . args ( ) ) { if ( ! isSupportedType ( DL , TLI , Arg . getType ( ) ) ) return false ; if ( Arg . hasPassPointeeByValueAttr ( ) ) return false ; } CCAssignFn * AssignFn = TLI . CCAssignFnForCall ( F . getCallingConv ( ) , F . isVarArg ( ) ) ; FormalArgHandler ArgHandler ( MIRBuilder , MIRBuilder . getMF ( ) . getRegInfo ( ) , AssignFn ) ; SmallVector < ArgInfo , <NUM_LIT> > SplitArgInfos ; unsigned Idx =


<s> } if ( crtl -> limit_stack || ( TARGET_STACK_CHECK_L1 && ! DECL_NO_LIMIT_STACK ( current_function_decl ) ) ) { HOST_WIDE_INT offset = bfin_initial_elimination_offset ( ARG_POINTER_REGNUM , STACK_POINTER_REGNUM ) ; rtx lim = crtl -> limit_stack ? stack_limit_rtx : NULL_RTX ; rtx tmp = gen_rtx_REG ( Pmode , REG_R3 ) ; rtx p2reg = gen_rtx_REG ( Pmode , REG_P2 ) ; emit_move_insn ( tmp , p2reg ) ; if ( ! lim ) { emit_move_insn ( p2reg , gen_int_mode ( <NUM_LIT> , SImode ) ) ; emit_move_insn ( p2reg , gen_rtx_MEM ( Pmode , p2reg ) ) ; lim = p2reg ; } if ( GET_CODE ( lim ) == SYMBOL_REF ) { if ( TARGET_ID_SHARED_LIBRARY ) { rtx p1reg = gen_rtx_REG ( Pmode , REG_P1 ) ; rtx val ; pic_reg_loaded = bfin_load_pic_reg ( p2reg ) ; val = legitimize_pic_address ( stack_limit_rtx , p1reg , pic_reg_loaded ) ; emit_move_insn ( p1reg , val ) ; frame_related_constant_load ( p2reg , offset , FALSE ) ; emit_insn ( gen_addsi3 ( p2reg , p2reg , p1reg


<s> for ( unsigned i = <NUM_LIT> , e = ArgLocs . size ( ) ; i != e ; ++ i ) { CCValAssign & VA = ArgLocs [ i ] ; if ( VA . isRegLoc ( ) ) { unsigned VReg = MF . addLiveIn ( VA . getLocReg ( ) , getRegClassFor ( VA . getLocVT ( ) ) ) ; SDValue Arg = DAG . getCopyFromReg ( Chain , DL , VReg , VA . getLocVT ( ) ) ; if ( VA . getValVT ( ) == <STR_LIT> && VA . needsCustom ( ) ) Arg = DAG . getNode ( <STR_LIT> , DL , VA . getLocVT ( ) , Arg , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; switch ( VA . getLocInfo ( ) ) { case CCValAssign :: SExt : Arg = DAG . getNode ( <STR_LIT> , DL , VA . getLocVT ( ) , Arg , DAG . getValueType ( VA . getValVT ( ) ) ) ; break ; case CCValAssign :: ZExt : Arg = DAG . getNode ( <STR_LIT> , DL , VA . getLocVT ( ) , Arg , DAG . getValueType ( VA . getValVT ( ) ) ) ; break ; case CCValAssign :: BCvt : { assert ( VA . getLocVT ( ) == <STR_LIT> ) ; assert ( VA . getValVT ( ) == <STR_LIT> ) ; SDValue Sub_f32 = DAG . getTargetConstant ( <STR_LIT> , DL , <STR_LIT> ) ; Arg = SDValue ( DAG . getMachineNode ( TargetOpcode :: EXTRACT_SUBREG , DL , <STR_LIT> , Arg , Sub_f32 ) , <NUM_LIT> ) ; break ; } default : break ; } if ( VA . isExtInLoc ( ) ) Arg = DAG . getNode ( <STR_LIT> , DL , VA . getValVT ( ) , Arg ) ; InVals . push_back ( Arg ) ; continue ; } assert ( VA . isMemLoc ( ) ) ; unsigned Offset = VA . getLocMemOffset ( ) + ArgsBaseOffset ; unsigned ValSize = VA . getValVT ( ) . getSizeInBits ( ) / <NUM_LIT> ; if ( VA . getValVT ( ) == <STR_LIT> ) Offset += <NUM_LIT> ; int FI = MF . getFrameInfo ( ) . CreateFixedObject ( ValSize , Offset , true ) ; InVals . push_back ( DAG . getLoad ( VA . getValVT ( ) , DL , Chain , DAG . getFrameIndex ( FI , getPointerTy ( MF . getDataLayout ( ) ) ) , MachinePointerInfo :: getFixedStack ( MF , FI ) ) ) ; } if ( ! IsVarArg ) return Chain ; unsigned ArgOffset = ArgLocs . size ( ) * <NUM_LIT> ; <ISA_LIT>MachineFunctionInfo * FuncInfo = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; FuncInfo -> setVarArgsFrameOffset ( ArgOffset + ArgsBaseOffset ) ; return Chain


<s> int64_t getExprCRVal ( ) const { assert ( Kind == Expression && <STR_LIT> ) ; return Expr .


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : if ( canUseShortMicro<ISA_LIT>CTI ) return <STR_LIT> ; else if ( I -> getOperand ( <NUM_LIT> ) . getReg ( ) == I -> getOperand ( <NUM_LIT> ) . getReg ( ) ) return <NUM_LIT> ; return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : if ( canUseShortMicro<ISA_LIT>CTI ) return <STR_LIT> ; else if ( I -> getOperand ( <NUM_LIT> ) . getReg ( ) == I -> getOperand ( <NUM_LIT> ) . getReg ( ) ) return <NUM_LIT> ; return <STR_LIT> ; case <STR_LIT> : if ( I -> getOperand ( <NUM_LIT> ) . getReg ( ) == I -> getOperand ( <NUM_LIT> ) . getReg ( ) ) return <NUM_LIT> ; return <STR_LIT> ; case <STR_LIT> : if ( I -> getOperand ( <NUM_LIT> ) . getReg ( ) == I -> getOperand ( <NUM_LIT> ) . getReg ( ) ) return <NUM_LIT> ; return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : if ( I -> getOperand ( <NUM_LIT> ) . getReg ( ) == I -> getOperand ( <NUM_LIT> ) . getReg ( ) ) return <NUM_LIT> ; return <STR_LIT> ; case <STR_LIT> : if ( I -> getOperand ( <NUM_LIT> ) . getReg ( ) == I -> getOperand ( <NUM_LIT> ) . getReg ( ) ) return <NUM_LIT> ; return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : if ( I -> getOperand ( <NUM_LIT> ) . getReg ( ) == I -> getOperand ( <NUM_LIT> ) . getReg ( ) ) return <NUM_LIT> ; return <STR_LIT> ; case <STR_LIT> : if ( I -> getOperand ( <NUM_LIT> ) . getReg ( ) == I -> getOperand ( <NUM_LIT> ) . getReg ( ) ) return <NUM_LIT> ; return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( canUseShortMicro<ISA_LIT>CTI ) return <STR_LIT> ; return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return


<s> const AsmToken & Tok = Parser . getTok ( ) ; std :: string LowerID = Tok . getString ( ) . lower ( ) ; <STR_LIT> ShOp = StringSwitch < <STR_LIT> > ( LowerID ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( <STR_LIT> ) ; if ( ShOp == <STR_LIT> ) return MatchOperand_NoMatch ; SMLoc S = Tok . getLoc ( ) ; Parser . Lex ( ) ; bool Hash = getLexer ( ) . is


<s> void <ISA_LIT>InstPrinter :: printArgDeclAlignment ( const MCInst * MI , unsigned OpNo , raw_ostream & O ) { unsigned Align = MI -> getOperand ( OpNo ) . getImm ( ) ; int TypeLengthIdx = <STR_LIT> ( MI -> getOpcode ( ) , <STR_LIT> :: TypeLength ) ; BrigType BT = static_cast < BrigType > ( MI -> getOperand ( TypeLengthIdx ) . getImm ( ) ) ; if ( ! isNaturalAlignment ( BT , Align ) ) O << <STR_LIT> <<


<s> emit_insn ( gen_addxf3 ( e2 , e1 , cst2 ) ) ; emit_insn ( gen_divxf3 ( e2 , e1 , e2 ) ) ; emit_insn ( gen_testqi_ext_1_ccno ( scratch , GEN_INT ( <NUM_LIT> ) ) ) ; tmp = gen_rtx_IF_THEN_ELSE ( VOIDmode , gen_rtx_NE ( VOIDmode , flags , const0_rtx ) , gen_rtx_LABEL_REF ( VOIDmode , jump_label ) , pc_rtx ) ; insn = emit_jump_insn ( gen_rtx_SET ( pc_rtx , tmp ) ) ; predict_jump ( REG_BR_PROB_BASE * <NUM_LIT> / <NUM_LIT> ) ; JUMP_LABEL ( insn ) = jump_label ; emit_insn ( gen_negxf2 ( e2 , e2 ) ) ; emit_label ( jump_label ) ; LABEL_NUSES ( jump_label ) =


<s> x = in0 , in0 = in1 , in1 = x ; odd = ! odd ; } out = d -> target ; if ( odd ) { switch ( vmode ) { case V16QImode : gen = gen_aarch64_trn2v16qi ; break ; case V8QImode : gen = gen_aarch64_trn2v8qi ; break ; case V8HImode : gen = gen_aarch64_trn2v8hi ; break ; case V4HImode : gen = gen_aarch64_trn2v4hi ; break ; case V4SImode : gen = gen_aarch64_trn2v4si ; break ; case V2SImode : gen = gen_aarch64_trn2v2si ; break ; case V2DImode : gen = gen_aarch64_trn2v2di ; break ; case V4HFmode : gen = gen_aarch64_trn2v4hf ; break ; case V8HFmode : gen = gen_aarch64_trn2v8hf ; break ; case V4SFmode : gen = gen_aarch64_trn2v4sf ; break ; case V2SFmode : gen = gen_aarch64_trn2v2sf ; break ; case V2DFmode : gen = gen_aarch64_trn2v2df ; break ; default : return false ; } } else { switch ( vmode ) { case V16QImode : gen = gen_aarch64_trn1v16qi ; break ; case V8QImode : gen = gen_aarch64_trn1v8qi ; break ; case V8HImode : gen = gen_aarch64_trn1v8hi ; break ; case V4HImode : gen = gen_aarch64_trn1v4hi ; break ; case V4SImode : gen = gen_aarch64_trn1v4si ; break ; case V2SImode : gen = gen_aarch64_trn1v2si ; break ; case V2DImode : gen = gen_aarch64_trn1v2di ; break ; case V4HFmode : gen = gen_aarch64_trn1v4hf ; break ; case V8HFmode : gen = gen_aarch64_trn1v8hf ; break ; case V4SFmode : gen = gen_aarch64_trn1v4sf ; break ; case V2SFmode : gen = gen_aarch64_trn1v2sf ;


<s> if ( ByteOk && ( DstOffset - JTOffset ) > ( ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) * <NUM_LIT> ) ByteOk = false ; unsigned TBHLimit = ( ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) * <NUM_LIT> ; if ( HalfWordOk && ( DstOffset - JTOffset ) > TBHLimit ) HalfWordOk = false ; if ( ! ByteOk && ! HalfWordOk ) break ; } if ( ByteOk || HalfWordOk ) { MachineBasicBlock * MBB = MI -> getParent ( ) ; unsigned BaseReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; bool BaseRegKill = MI -> getOperand ( <NUM_LIT> ) . isKill ( ) ; if ( ! BaseRegKill ) continue ; unsigned IdxReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; bool IdxRegKill = MI -> getOperand ( <NUM_LIT> ) . isKill ( ) ; MachineBasicBlock :: iterator PrevI = MI ; MachineBasicBlock :: iterator B = MBB -> begin ( ) ; while ( PrevI != B && ! PrevI -> definesRegister ( BaseReg ) ) -- PrevI ; if ( ! PrevI -> definesRegister ( BaseReg ) ) continue ; MachineInstr * AddrMI = PrevI ; bool OptOk = true ; for ( unsigned k = <NUM_LIT> , eee = AddrMI -> getNumOperands ( ) ; k != eee ; ++ k ) { const MachineOperand & MO = AddrMI -> getOperand ( k ) ; if ( ! MO . isReg ( ) || ! MO . getReg ( ) ) continue ; if ( MO . isDef ( ) && MO . getReg ( ) != BaseReg ) { OptOk = false ; break ; } if ( MO . isUse ( ) && ! MO . isKill ( ) && MO . getReg (


<s> if ( ShiftName != LowerOp && ShiftName != UpperOp ) { Error ( Parser . getTok ( ) . getLoc ( ) , Op + <STR_LIT> ) ; return MatchOperand_ParseFail ; } Parser . Lex ( ) ; if ( Parser . getTok ( ) . isNot ( AsmToken :: Hash ) ) { Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ; } Parser . Lex ( ) ; const MCExpr * ShiftAmount ; SMLoc Loc = Parser . getTok ( ) . getLoc ( ) ; if ( getParser ( ) . ParseExpression ( ShiftAmount ) ) { Error ( Loc , <STR_LIT> ) ; return MatchOperand_ParseFail ; } const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( ShiftAmount ) ; if ( ! CE ) { Error ( Loc , <STR_LIT> ) ; return MatchOperand_ParseFail ; } int Val = CE -> getValue ( ) ; if ( Val < Low || Val


<s> break ; case <STR_LIT> : isCond = true ; UOpc = <STR_LIT> ; Bits = <NUM_LIT> ; Scale = <NUM_LIT> ; break ; case <STR_LIT> : Bits = <NUM_LIT> ; Scale = <NUM_LIT> ; break ; case <STR_LIT> : isCond = true ; UOpc = <STR_LIT> ; Bits = <NUM_LIT> ; Scale = <NUM_LIT> ; break ; case <STR_LIT> : Bits = <NUM_LIT> ; Scale = <NUM_LIT> ; break ; } unsigned MaxOffs = ( ( <NUM_LIT> << ( Bits - <NUM_LIT> ) ) - <NUM_LIT> ) * Scale ; ImmBranches . push_back ( ImmBranch ( & I , MaxOffs , isCond , UOpc ) ) ; } if ( Opc == <STR_LIT> || Opc == <STR_LIT> ) PushPopMIs . push_back ( & I ) ; if ( Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ) continue ; for ( unsigned op = <NUM_LIT> , e = I . getNumOperands ( ) ; op != e ; ++ op ) if ( I . getOperand ( op ) . isCPI ( ) || I . getOperand ( op ) . isJTI ( ) ) { unsigned Bits = <NUM_LIT> ; unsigned Scale = <NUM_LIT> ; bool NegOk = false ; bool IsSoImm = false ; switch ( Opc ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : Bits = <NUM_LIT> ; Scale = <NUM_LIT> ; NegOk = true ; IsSoImm = true ; break ; case <STR_LIT> : case <STR_LIT> : Bits = <NUM_LIT> ; NegOk = true ; break ; case <STR_LIT> : case <STR_LIT> : Bits = <NUM_LIT> ; Scale = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Bits = <NUM_LIT> ; NegOk = true ; break ; case <STR_LIT> : Bits = <NUM_LIT> ; Scale = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : Bits = <NUM_LIT> ; Scale = <NUM_LIT> ; NegOk = true ; break ; } unsigned CPI = I . getOperand ( op ) . getIndex ( ) ; if ( I . getOperand ( op ) . isJTI ( ) ) { JumpTableUserIndices . insert ( std :: make_pair ( CPI , CPUsers . size ( ) ) ) ; CPI = JumpTableEntryIndices [


<s> static tree tilepro_gimplify_va_arg_expr ( tree valist , tree type , gimple_seq * pre_p , gimple_seq * post_p ATTRIBUTE_UNUSED ) { tree f_args , f_skip ; tree args , skip ; HOST_WIDE_INT size , rsize ; tree addr , tmp ; bool pass_by_reference_p ; f_args = TYPE_FIELDS ( va_list_type_node ) ; f_skip = TREE_CHAIN ( f_args ) ; args = build3 ( COMPONENT_REF , TREE_TYPE ( f_args ) , valist , f_args , NULL_TREE ) ; skip = build3 ( COMPONENT_REF , TREE_TYPE ( f_skip ) , valist , f_skip , NULL_TREE ) ; addr = create_tmp_var ( ptr_type_node , <STR_LIT> ) ; pass_by_reference_p = pass_va_arg_by_reference ( type ) ; if ( pass_by_reference_p ) type = build_pointer_type ( type ) ; size = int_size_in_bytes ( type ) ; rsize = ( ( size + UNITS_PER_WORD - <NUM_LIT> ) / UNITS_PER_WORD ) * UNITS_PER_WORD ; if ( TYPE_ALIGN ( type ) > PARM_BOUNDARY ) { gcc_assert ( STACK_BOUNDARY == PARM_BOUNDARY * <NUM_LIT> ) ; tmp = build2 ( BIT_AND_EXPR , sizetype , fold_convert ( sizetype , unshare_expr ( args ) ) , size_int ( PARM_BOUNDARY / <NUM_LIT> ) ) ; tmp = build2 ( POINTER_PLUS_EXPR , ptr_type_node , unshare_expr ( args ) ,


<s> void <ISA_LIT>PassConfig :: addPreRegBankSelect ( ) { addPass ( create<ISA_LIT>PostLegalizerLowering


<s> bool isPacketStart ( ) const { return ( packetStart


<s> return __builtin_mve_vrmulhq_uv16qi ( __a ,


<s> unsigned Op = Bead & <NUM_LIT> ; switch ( Op ) { case <STR_LIT> : assert ( ( Ext == <STR_LIT> ) && <STR_LIT> ) ; break ; case <STR_LIT> : Builder . addBits ( <NUM_LIT> , Ext ) ; break ; case <STR_LIT> : Builder . addBits ( <NUM_LIT> , Ext ) ; break ; case <STR_LIT> : Builder . addBits ( <NUM_LIT> , Ext ) ; break ; case <STR_LIT> : Builder . addBits ( <NUM_LIT> , Ext ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( Op != <STR_LIT> ) Builder . skipBits ( <NUM_LIT> ) ; if ( Op != <STR_LIT> && Op != <STR_LIT> ) Builder . skipBits ( <NUM_LIT> ) ; break ; case <STR_LIT> : Builder . skipBits ( <NUM_LIT> ) ; break ; case <STR_LIT> : case <STR_LIT> : Builder . skipBits ( <NUM_LIT> ) ; break ; case <STR_LIT> : Builder . skipBits ( <NUM_LIT> ) ; break ; case <STR_LIT> : Builder . skipBits ( <NUM_LIT> ) ; break ; default : llvm_unreachable (


<s> inline bool sh_is_movrt_insn ( const rtx_insn * i ) { return sh_movrt_set_dest ( i


<s> return ( MI . getDesc ( ) . TSFlags & <STR_LIT> ) !=


<s> if ( Bytes || ( ! Offset && SrcReg != DestReg ) ) { assert ( ( DestReg != <STR_LIT> || Bytes % <NUM_LIT> == <NUM_LIT> ) && <STR_LIT> ) ; unsigned Opc = SetNZCV ? <STR_LIT> : <STR_LIT> ; if ( Bytes < <NUM_LIT> ) { Bytes = - Bytes ; Opc = SetNZCV ? <STR_LIT> : <STR_LIT> ; } emitFrameOffsetAdj ( MBB , MBBI , DL , DestReg , SrcReg , Bytes , Opc , TII , Flag , NeedsWinCFI , HasWinCFI ) ; SrcReg = DestReg ; } assert ( ! ( SetNZCV && ( NumPredicateVectors || NumDataVectors ) ) && <STR_LIT> ) ; assert ( ! ( NeedsWinCFI && ( NumPredicateVectors || NumDataVectors ) ) && <STR_LIT> ) ; if ( NumDataVectors ) { emitFrameOffsetAdj ( MBB , MBBI , DL , DestReg , SrcReg , NumDataVectors , <STR_LIT> , TII , Flag , NeedsWinCFI ,


<s> } } else if ( LocVT == <STR_LIT> ) { unsigned Req = HST . useHVX128BOps ( ) ? <STR_LIT> : <STR_LIT> ; if ( unsigned Reg = State . AllocateReg ( Req ) ) { State . addLoc ( CCValAssign :: getReg ( ValNo , ValVT , Reg , LocVT , LocInfo ) ) ; return false ; } } else if (


<s> const <ISA_LIT>InstrInfo * getInstrInfo ( ) const { return &


<s> MVT PVT = getPointerTy ( ) ; assert ( ( PVT == <STR_LIT> || PVT == <STR_LIT> ) && <STR_LIT> ) ; const TargetRegisterClass * RC = ( PVT == <STR_LIT> ) ? & <STR_LIT> : & <STR_LIT> ; unsigned Tmp = MRI . createVirtualRegister ( RC ) ; unsigned FP = ( PVT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; unsigned SP = ( PVT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; unsigned BP = ( PVT == <STR_LIT> ) ? <STR_LIT> : ( Subtarget . isSVR4ABI ( ) && MF -> getTarget ( ) . getRelocationModel ( ) == Reloc :: PIC_ ? <STR_LIT> : <STR_LIT> ) ; MachineInstrBuilder MIB ; const int64_t LabelOffset = <NUM_LIT> * PVT . getStoreSize ( ) ; const int64_t SPOffset = <NUM_LIT> * PVT . getStoreSize ( ) ; const int64_t TOCOffset = <NUM_LIT> * PVT . getStoreSize ( ) ; const int64_t BPOffset = <NUM_LIT> * PVT . getStoreSize ( ) ; unsigned BufReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( PVT == <STR_LIT> ) { MIB = BuildMI ( * MBB , MI , DL , TII -> get ( <STR_LIT> ) , FP ) . addImm ( <NUM_LIT> ) . addReg ( BufReg ) ; } else { MIB = BuildMI ( * MBB , MI , DL , TII -> get ( <STR_LIT> ) , FP ) . addImm ( <NUM_LIT> ) . addReg ( BufReg ) ; } MIB . setMemRefs ( MMOBegin , MMOEnd ) ; if ( PVT == <STR_LIT> ) { MIB = BuildMI ( * MBB , MI , DL , TII -> get ( <STR_LIT> ) , Tmp ) . addImm ( LabelOffset ) . addReg ( BufReg ) ; } else { MIB = BuildMI ( * MBB , MI , DL , TII -> get ( <STR_LIT> ) , Tmp ) . addImm ( LabelOffset ) . addReg ( BufReg ) ; } MIB . setMemRefs ( MMOBegin , MMOEnd ) ; if ( PVT == <STR_LIT> ) { MIB = BuildMI ( * MBB , MI , DL , TII -> get ( <STR_LIT> ) , SP ) . addImm ( SPOffset ) . addReg ( BufReg ) ; } else { MIB = BuildMI ( * MBB , MI , DL , TII -> get ( <STR_LIT> ) , SP ) . addImm ( SPOffset


<s> unsigned OpNo = IsStrict ? <NUM_LIT> : <NUM_LIT> ; SDValue Src = Op . getOperand ( OpNo ) ; SDValue Chain = IsStrict ? Op -> getOperand ( <NUM_LIT> ) : DAG . getEntryNode ( ) ; MVT SrcVT = Src . getSimpleValueType ( ) ; MVT VT = Op . getSimpleValueType ( ) ; SDLoc dl ( Op ) ; if ( SDValue Extract = vectorizeExtractedCast ( Op , DAG , Subtarget ) ) return Extract ; if ( SDValue R = lowerFPToIntToFP ( Op , DAG , Subtarget ) ) return R ; if ( SrcVT . isVector ( ) ) { if ( SrcVT == <STR_LIT> && VT == <STR_LIT> ) { if ( IsStrict ) return DAG . getNode ( <STR_LIT> , dl , { VT , <STR_LIT> } , { Chain , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Src , DAG . getUNDEF ( SrcVT ) ) } ) ; return DAG . getNode ( <STR_LIT> , dl , VT , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Src , DAG . getUNDEF ( SrcVT ) ) ) ; } if ( SrcVT == <STR_LIT> || SrcVT == <STR_LIT> ) return lowerINT_TO_FP_vXi64 ( Op , DAG , Subtarget ) ; return SDValue ( ) ; } assert ( SrcVT <= <STR_LIT> && SrcVT >= <STR_LIT> && <STR_LIT> ) ; bool UseSSEReg = isScalarFPTypeInSSEReg ( VT ) ; if ( SrcVT == <STR_LIT> && UseSSEReg ) return Op ; if ( SrcVT == <STR_LIT> && UseSSEReg && Subtarget . is64Bit ( ) ) return Op ; if ( SDValue V = LowerI64IntToFP_AVX512DQ ( Op , DAG , Subtarget ) ) return V ; if ( SrcVT == <STR_LIT> && ( UseSSEReg || VT == <STR_LIT> ) ) { SDValue Ext = DAG . getNode ( <STR_LIT>


<s> if ( ! first_exit_blocks_p ) return false ; exit_bb = e -> src ; first_exit_blocks_p = false


<s> void addMEMriOperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: CreateReg ( getMemBase ( ) ) ) ; const MCExpr * Expr = getMemOff ( ) ; addExpr ( Inst


<s> SDValue Chain = Node -> getOperand ( <NUM_LIT> ) ; SDValue In1 = Node -> getOperand ( <NUM_LIT> ) ; SDValue In2L = Node -> getOperand ( <NUM_LIT> ) ; SDValue In2H = Node -> getOperand ( <NUM_LIT> ) ; SDValue Tmp0 , Tmp1 , Tmp2 , Tmp3 ; if ( ! SelectAddr ( In1 , In1 , Tmp0 , Tmp1 , Tmp2 , Tmp3 ) ) return NULL ; SDValue LSI = Node ->


<s> Entry . Node = DAG . getConstant ( is<ISA_LIT>64 ? <NUM_LIT> : <NUM_LIT> , dl , is<ISA_LIT>64 ? <STR_LIT> : <STR_LIT> ) ; Args . push_back ( Entry ) ; Entry . Node = FPtr ; Args . push_back ( Entry ) ; Entry . Node = Nest ; Args . push_back ( Entry ) ; TargetLowering :: CallLoweringInfo CLI ( DAG ) ; CLI . setDebugLoc ( dl ) . setChain ( Chain ) . setLibCallee ( CallingConv :: C , Type :: getVoidTy ( * DAG . getContext ( ) ) , DAG . getExternalSymbol ( <STR_LIT> , PtrVT ) , std :: move ( Args ) ) ; std :: pair < SDValue , SDValue > CallResult = LowerCallTo ( CLI ) ; return CallResult


<s> return ( int32x2_t ) __builtin_neon_vnegv2si


<s> MachineInstr * BRCL = BuildMI ( * MBB , MI , DL , TII -> get ( <STR_LIT> ) ) . addImm ( <STR_LIT> ) . addOperand ( MI -> getOperand ( <NUM_LIT> ) ) . addOperand ( MI -> getOperand ( <NUM_LIT> ) ) ; BRCL -> addRegisterKilled ( <STR_LIT> , & TII -> getRegisterInfo ( ) ) ; MI -> eraseFromParent


<s> static SDValue lowerV32I8VectorShuffle ( const SDLoc & DL , ArrayRef < int > Mask , const APInt & Zeroable , SDValue V1 , SDValue V2 , const <ISA_LIT>Subtarget & Subtarget , SelectionDAG & DAG ) { assert ( V1 . getSimpleValueType ( ) == <STR_LIT> && <STR_LIT> ) ; assert ( V2 . getSimpleValueType ( ) == <STR_LIT> && <STR_LIT> ) ; assert ( Mask . size ( ) == <NUM_LIT> && <STR_LIT> ) ; assert ( Subtarget . hasAVX2 ( ) && <STR_LIT> ) ; if ( SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend ( DL , <STR_LIT> , V1 , V2 , Mask , Zeroable , Subtarget , DAG ) ) return ZExt ; if ( SDValue Broadcast = lowerVectorShuffleAsBroadcast ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return Broadcast ; if ( SDValue Blend = lowerVectorShuffleAsBlend ( DL , <STR_LIT> , V1 , V2 , Mask , Zeroable , Subtarget , DAG ) ) return Blend ; if ( SDValue V = lowerVectorShuffleWithUNPCK ( DL , <STR_LIT> , Mask , V1 , V2 , DAG ) ) return V ; if ( SDValue Shift = lowerVectorShuffleAsShift ( DL , <STR_LIT> , V1 , V2 , Mask ,

Zeroable , Subtarget , DAG ) ) return Shift ;


<s> return ( uint64x2_t ) __builtin_neon_vdup_nv2di ( ( __builtin_neon_di )


<s> BlockInfo . resize ( MF . getNumBlockIDs ( ) ) ; ReversePostOrderTraversal < MachineFunction * > RPOT ( & MF ) ; bool Modified = false ; for ( ReversePostOrderTraversal < MachineFunction * > :: rpo_iterator I = RPOT . begin ( ) , E = RPOT . end ( ) ; I != E ; ++ I ) Modified |=


<s> static Reloc :: Model getEffectiveRelocModel ( Optional


<s> if ( ! ThisReplaceable ) continue ; for ( std :: pair < ReturnInst * , StoreInst * > Store : ReplaceableStores ) { Value * ReplVal = Store . second -> getValueOperand ( ) ; auto & ValVec = Replacements [ Store . first ] ; if ( llvm :: find_if ( ValVec , [ OutArg ] ( const std :: pair < Argument * , Value * > & Entry ) { return Entry . first == OutArg ; } ) != ValVec . end ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * OutArg << '\n' ) ; ThisReplaceable = false ; break ; } ValVec . emplace_back ( OutArg , ReplVal ) ; Store . second -> eraseFromParent ( ) ; } if ( ThisReplaceable ) { ReturnTypes . push_back ( ArgTy ) ; OutArgIndexes . insert ( OutArg -> getArgNo ( ) ) ; ++ NumOutArgumentsReplaced ; Changing = true ; } } } while ( Changing ) ; if ( Replacements . empty ( ) ) return false ; LLVMContext & Ctx = F . getParent ( ) -> getContext ( ) ; StructType * NewRetTy = StructType :: create ( Ctx , ReturnTypes , F . getName ( ) ) ; FunctionType * NewFuncTy = FunctionType :: get ( NewRetTy , F . getFunctionType ( ) -> params ( ) , F . isVarArg ( ) ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * NewRetTy << '\n' ) ; Function * NewFunc = Function :: Create ( NewFuncTy , Function :: PrivateLinkage , F . getName ( ) + <STR_LIT> ) ; F . getParent ( ) -> getFunctionList ( ) . insert ( F . getIterator ( ) , NewFunc ) ; NewFunc -> copyAttributesFrom ( & F ) ; NewFunc -> setComdat ( F . getComdat ( ) ) ; NewFunc -> stealArgumentListFrom ( F ) ; AttrBuilder RetAttrs ; RetAttrs . addAttribute ( Attribute :: SExt ) ; RetAttrs . addAttribute ( Attribute :: ZExt ) ; RetAttrs . addAttribute ( Attribute :: NoAlias ) ; NewFunc -> removeAttributes ( AttributeList :: ReturnIndex , RetAttrs ) ; NewFunc -> getBasicBlockList ( ) . splice ( NewFunc -> begin ( ) , F . getBasicBlockList ( ) ) ; for ( std :: pair < ReturnInst * , ReplacementVec > & Replacement : Replacements ) { ReturnInst * RI = Replacement . first ; IRBuilder < > B ( RI ) ; B . SetCurrentDebugLocation ( RI -> getDebugLoc ( ) ) ; int RetIdx = <NUM_LIT> ; Value * NewRetVal = UndefValue :: get ( NewRetTy ) ; Value * RetVal = RI -> getReturnValue ( ) ; if ( RetVal ) NewRetVal = B . CreateInsertValue ( NewRetVal ,


<s> if ( LoadNode -> getExtensionType ( ) == <STR_LIT> ) ExtType = <STR_LIT> ; else if ( LoadNode -> getExtensionType ( ) == <STR_LIT> || LoadNode -> getExtensionType ( ) == <STR_LIT> ) ExtType = <STR_LIT> ; else return SDValue ( ) ; SDValue Load = DAG . getLoad ( <STR_LIT> , DL , LoadNode -> getChain ( ) , LoadNode -> getBasePtr ( ) , MachinePointerInfo ( ) ) ; SDValue Chain = Load . getValue ( <NUM_LIT> ) ; SDValue Vec = DAG . getNode ( <STR_LIT> ,


<s> r = sr -> curr . reg + decode_abreg ( abreg , <NUM_LIT> ) ; r -> where = UNW_WHERE_NONE ; r -> when = sr -> region_start + MIN ( ( int )


<s> switch ( CC ) { default : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case


<s> const MCOperand & MO = MI . getOperand ( OpNo ) ; if ( MO . isReg ( ) || MO . isImm ( ) ) return getMachineOpValue ( MI , MO , Fixups , STI ) ; Fixups . push_back ( MCFixup :: Create ( <NUM_LIT> , MO . getExpr ( ) , ( MCFixupKind ) <STR_LIT> ) ) ; return


<s> bool <ISA_LIT>DAGToDAGISel :: SelectFlatOffset ( SDNode * N , SDValue Addr , SDValue & VAddr , SDValue & Offset , SDValue & SLC ) const { return static_cast < const <ISA_LIT>TargetLowering * > ( getTargetLowering ( ) ) -> SelectFlatOffset ( IsSigned , * CurDAG , N , Addr , VAddr


<s> } else return ; } else return ; } gcc_assert ( ! arm_ccfsm_state || reverse ) ; if ( ! JUMP_P ( insn ) ) return ; if ( GET_CODE ( body ) == PARALLEL && XVECLEN ( body , <NUM_LIT> ) > <NUM_LIT> ) body = XVECEXP ( body , <NUM_LIT> , <NUM_LIT> ) ; if ( reverse || ( GET_CODE ( body ) == SET && GET_CODE ( SET_DEST ( body ) ) == PC && GET_CODE ( SET_SRC ( body ) ) == IF_THEN_ELSE ) ) { int insns_skipped ; int fail = FALSE , succeed = FALSE ; int then_not_else = TRUE ; rtx_insn * this_insn = start_insn ; rtx label = <NUM_LIT> ; if ( reverse ) { if ( ! seeking_return ) label = XEXP ( SET_SRC ( body ) , <NUM_LIT> ) ; } else if ( GET_CODE ( XEXP ( SET_SRC ( body ) , <NUM_LIT> ) ) == LABEL_REF ) label = XEXP ( XEXP ( SET_SRC ( body ) , <NUM_LIT> ) , <NUM_LIT> ) ; else if ( GET_CODE ( XEXP ( SET_SRC ( body ) , <NUM_LIT> ) ) == LABEL_REF ) { label = XEXP ( XEXP ( SET_SRC ( body ) , <NUM_LIT> ) , <NUM_LIT> ) ; then_not_else = FALSE ; } else if ( ANY_RETURN_P ( XEXP ( SET_SRC ( body ) , <NUM_LIT> ) ) ) { seeking_return = <NUM_LIT> ; return_code = GET_CODE ( XEXP ( SET_SRC ( body ) , <NUM_LIT> ) ) ; } else if ( ANY_RETURN_P ( XEXP ( SET_SRC ( body ) , <NUM_LIT> ) ) ) { seeking_return = <NUM_LIT> ; return_code = GET_CODE ( XEXP ( SET_SRC ( body ) , <NUM_LIT> ) ) ; then_not_else = FALSE ; } else gcc_unreachable ( ) ; for ( insns_skipped = <NUM_LIT> ; ! fail && ! succeed && insns_skipped ++ < max_insns_skipped ; ) { rtx scanbody ; this_insn = next_nonnote_insn ( this_insn ) ; if ( ! this_insn ) break ; switch ( GET_CODE ( this_insn ) ) { case CODE_LABEL : if ( this_insn == label ) { arm_ccfsm_state = <NUM_LIT> ; succeed = TRUE ; } else fail = TRUE ; break ; case BARRIER : this_insn = next_nonnote_insn ( this_insn ) ; if ( this_insn && this_insn == label ) { arm_ccfsm_state = <NUM_LIT> ; succeed = TRUE ; } else fail = TRUE ; break ; case CALL_INSN : if ( arm_arch5t ) { fail = TRUE ; break ; } this_insn = next_nonnote_insn ( this_insn ) ; if ( this_insn && BARRIER_P ( this_insn ) ) this_insn = next_nonnote_insn ( this_insn ) ; if ( this_insn && this_insn == label && insns_skipped < max_insns_skipped ) { arm_ccfsm_state = <NUM_LIT> ; succeed = TRUE ; } else fail = TRUE ; break ; case JUMP_INSN : scanbody = PATTERN ( this_insn ) ; if ( GET_CODE ( scanbody ) == SET && GET_CODE ( SET_DEST (


<s> if ( regno == MDB_REGNUM ) return CEIL ( GET_MODE_SIZE ( mode ) , <NUM_LIT> *


<s> static DecodeStatus DecodeHPRRegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t Address , const MCDisassembler * Decoder ) { return DecodeSPRRegisterClass ( Inst , RegNo , Address ,


<s> static unsigned riscv_save_libcall_count ( unsigned mask ) { for ( unsigned n = GP_REG_LAST ; n > GP_REG_FIRST ; n -- ) if ( BITSET_P

( mask , n ) ) return CALLEE_SAVED_REG_NUMBER ( n ) + <NUM_LIT> ;


<s> for ( MachineLoop :: iterator I = L -> begin ( ) , E = L -> end ( ) ; I != E ; ++ I ) Changed |= visitLoop ( * I ) ; } MachineBasicBlock * EntryB = GraphTraits < MachineFunction * > :: getEntryNode ( MFN ) ; Changed |= visitBlock ( L ? HB : EntryB ,


<s> Register Tmp = MRI . createVirtualRegister ( RC ) ; const <ISA_LIT>RegisterInfo * RegInfo = Subtarget . getRegisterInfo ( ) ; unsigned FP = ( PVT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; Register SP = RegInfo -> getStackRegister ( ) ; MachineInstrBuilder MIB ; const int64_t LabelOffset = <NUM_LIT> * PVT . getStoreSize ( ) ; const int64_t SPOffset = <NUM_LIT> * PVT . getStoreSize ( ) ; unsigned PtrLoadOpc = ( PVT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; unsigned IJmpOpc = ( PVT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; MachineBasicBlock * thisMBB = MBB ; if ( MF -> getMMI ( ) . getModule ( ) -> getModuleFlag ( <STR_LIT> ) ) { thisMBB = emitLongJmpShadowStackFix ( MI , thisMBB ) ; } MIB = BuildMI ( * thisMBB , MI , DL , TII -> get ( PtrLoadOpc ) , FP ) ; for ( unsigned i = <NUM_LIT> ; i < <STR_LIT> ; ++ i ) { const MachineOperand & MO = MI . getOperand ( i ) ; if ( MO . isReg ( ) ) MIB . addReg ( MO . getReg ( ) ) ; else MIB . add ( MO ) ; } MIB . setMemRefs ( MMOs ) ; MIB = BuildMI ( * thisMBB , MI , DL , TII -> get ( PtrLoadOpc ) , Tmp ) ; for ( unsigned i = <NUM_LIT> ; i < <STR_LIT> ; ++ i ) { const MachineOperand & MO = MI . getOperand ( i ) ; if ( i == <STR_LIT> ) MIB . addDisp ( MO ,


<s> } switch ( TSFlags & <STR_LIT> ) { default : break ; case <STR_LIT> : { if ( Inst . getOperand ( <NUM_LIT> ) . getReg ( ) != <STR_LIT> ) SegmentReg = Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ; break ; } case <STR_LIT> : { if ( Inst . getOperand ( <NUM_LIT> ) . getReg ( ) != <STR_LIT> ) SegmentReg = Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ; break ; } case <STR_LIT> : { SegmentReg = Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ; break ; } } if ( SegmentReg != <NUM_LIT> ) return <STR_LIT> ( SegmentReg ) ; if ( STI . hasFeature ( <STR_LIT> ) ) return <STR_LIT> ; if ( MemoryOperand >= <NUM_LIT>


<s> LLVM_DEBUG ( dbgs ( ) << <STR_LIT> <STR_LIT> ) ; return false ; } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * MI ) ; SecondaryVCTPs . insert ( MI ) ; } else { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * MI ) ; VCTP = MI ; } } else if ( isVPTOpcode ( MI -> getOpcode ( ) ) ) { if ( MI -> getOpcode ( ) != <STR_LIT> ) { assert ( MI -> findRegisterDefOperandIdx ( <STR_LIT> ) != - <NUM_LIT> && <STR_LIT> ) ; CurrentPredicate . insert ( MI ) ; } VPTBlocks . emplace_back ( MI , CurrentPredicate ) ; CurrentBlock = & VPTBlocks . back ( ) ; return true ; } else if ( MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> ) { return false ; } bool IsUse = false ; bool IsDef = false ; const MCInstrDesc & MCID = MI -> getDesc ( ) ; for ( int i = MI -> getNumOperands ( ) - <NUM_LIT> ; i >= <NUM_LIT> ; -- i ) { const MachineOperand & MO = MI -> getOperand ( i ) ; if ( ! MO . isReg ( ) || MO . getReg ( ) != <STR_LIT> ) continue ; if ( MO . isDef ( ) ) { CurrentPredicate . insert ( MI ) ; IsDef = true ; } else if ( <STR_LIT> ( MCID . OpInfo [ i ] . OperandType ) ) { CurrentBlock -> addInst ( MI , CurrentPredicate


<s> init_reg_tables ( ) ; memset ( m32r_punct_chars , <NUM_LIT> , sizeof ( m32r_punct_chars ) ) ; m32r_punct_chars [ '#' ] = <NUM_LIT> ; m32r_punct_chars [ '@' ] =


<s> MachineInstr * BranchMI ; while ( ( BranchMI = getLoopendBlockBranchInstr ( MBB ) ) && isUncondBranch


<s> unsigned numcopies = numCopiesNeeded ( Instr ) ; unsigned destregnum = Instr -> getOperand ( <NUM_LIT> ) . getReg ( ) ; SmallVector < unsigned , <NUM_LIT> > dest = getScalarRegisters ( destregnum ) ; DebugLoc DL = Instr -> getDebugLoc ( ) ; for ( unsigned i = <NUM_LIT> ; i < numcopies ; i ++ ) { MachineInstr * copy = BuildMI ( F , DL , InstrInfo -> get ( getScalarVersion ( Instr ) ) , dest [ i ] ) ; copy -> addOperand ( Instr -> getOperand (


<s> poly8x16x3_t temp ; temp . val [ <NUM_LIT> ] = vcombine_p8 ( val . val [ <NUM_LIT> ] , vcreate_p8 ( __AARCH64_UINT64_C ( <NUM_LIT> ) ) ) ; temp . val [ <NUM_LIT> ] = vcombine_p8 ( val . val [ <NUM_LIT> ] , vcreate_p8 ( __AARCH64_UINT64_C ( <NUM_LIT> ) ) ) ; temp . val [ <NUM_LIT> ] = vcombine_p8 ( val . val [ <NUM_LIT> ] , vcreate_p8 ( __AARCH64_UINT64_C ( <NUM_LIT> ) ) ) ; __o = __builtin_aarch64_set_qregciv16qi ( __o , ( int8x16_t ) temp . val [ <NUM_LIT> ] , <NUM_LIT> ) ; __o = __builtin_aarch64_set_qregciv16qi ( __o , ( int8x16_t ) temp . val [ <NUM_LIT> ] , <NUM_LIT> ) ; __o = __builtin_aarch64_set_qregciv16qi ( __o , ( int8x16_t ) temp


<s> return ( int32x4_t ) __builtin_aarch64_saddwv4hi (


<s> static bool isVectorAllOnes ( SDValue N ) { if ( N -> getOpcode ( ) == <STR_LIT> ) N = N -> getOperand ( <NUM_LIT> ) ; BuildVectorSDNode * BVN = dyn_cast < BuildVectorSDNode > ( N ) ; if ( ! BVN ) return


<s> inline void setSym ( std :: string str ) { mSym = str


<s> bool <ISA_LIT>InsertSkips :: skipMaskBranch ( MachineInstr & MI , MachineBasicBlock & SrcMBB ) { MachineBasicBlock * DestBB = MI . getOperand ( <NUM_LIT> ) . getMBB ( ) ; if ( ! shouldSkip ( * * SrcMBB . succ_begin ( ) , * DestBB ) ) return false ; const DebugLoc & DL = MI . getDebugLoc (


<s> bool unifyMetadataImpl ( Module & M ) { const char * Vers [ ] = { kOCLMD :: SpirVer , kOCLMD :: OCLVer } ; const char * Exts [ ] = { kOCLMD :: UsedExt , kOCLMD :: UsedOptCoreFeat , kOCLMD :: CompilerOptions , kOCLMD :: LLVMIdent } ; bool Changed =


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , Optional < CodeModel :: Model > CM , CodeGenOpt :: Level OL , bool JIT ) : LLVMTargetMachine ( T , computeDataLayout ( TT ) , TT , CPU , FS , Options , getEffectiveRelocModel ( TT , JIT , RM ) , getEffective<ISA_LIT>CodeModel ( CM , JIT , TT . getArch ( ) == Triple :: x86_64 ) , OL ) , TLOF ( createTLOF ( getTargetTriple ( ) ) ) , IsJIT ( JIT ) { if ( TT . isPS4 ( ) || TT . isOSBinFormatMachO ( ) ) { this -> Options . TrapUnreachable = true ; this -> Options . NoTrapAfterNoreturn = TT . isOSBinFormatMachO ( ) ; } setMachineOutliner ( true ) ; initAsmInfo ( )


<s> static bool needsFPHelperFromSig ( Function &


<s> AU . addPreserved < MachineDominatorTree > ( ) ; AU . addPreserved < MachinePostDominatorTree > ( ) ; MachineFunctionPass :: getAnalysisUsage (


<s> static inline uint64_t ror ( uint64_t elt ,


<s> return ( __m128i ) __builtin_ia32_pcmpgtw128 ( ( __v8hi ) __B ,


<s> if ( ! isa < Instruction > ( V ) ) return false ; unsigned Opc = cast < Instruction > (


<s> bool isSWZ ( ) const { return isImmTy (


<s> unsigned char <ISA_LIT>Subtarget :: classifyGlobalReference ( const GlobalValue * GV , const Module & M ) const { if ( TM . getCodeModel ( ) == CodeModel :: Large ) return <STR_LIT> ; if ( GV ) { if ( Optional < ConstantRange > CR = GV -> getAbsoluteSymbolRange ( ) ) { if ( CR -> getUnsignedMax ( ) . ult (


<s> SwitchMode ( <STR_LIT> ) ; getParser ( ) . getStreamer ( ) . EmitAssemblerFlag ( MCAF_Code32 ) ; } } else if ( IDVal == <STR_LIT> ) { Parser . Lex ( ) ; if ( ! is64BitMode ( ) ) { SwitchMode ( <STR_LIT> ) ; getParser ( ) . getStreamer ( ) . EmitAssemblerFlag ( MCAF_Code64 ) ; } } else


<s> return ( poly8x16_t ) __builtin_neon_vreinterpretv16qiv2di ( ( int64x2_t


<s> Entry . Node = Size ; Args . push_back ( Entry ) ; TargetLowering :: CallLoweringInfo CLI ( DAG ) ; CLI . setDebugLoc ( dl ) . setChain ( Chain ) . setLibCallee ( TLI . getLibcallCallingConv ( RTLIB :: MEMCPY ) , Type :: getVoidTy ( * DAG . getContext ( ) ) , DAG

. getExternalSymbol ( <STR_LIT> , TLI . getPointerTy ( DAG . getDataLayout ( ) ) ) , std :: move ( Args ) ) . setDiscardResult ( ) ;


<s> void addImm0_127Operands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT> ) ; const MCConstantExpr * MCE = cast < MCConstantExpr > ( getImm ( ) ) ; Inst . addOperand ( MCOperand :: createImm ( MCE -> getValue (


<s> TargetFrameLowering :: determineCalleeSaves ( MF ,


<s> if ( ! isa < GlobalAddressSDNode > ( Callee ) && ! isa < ExternalSymbolSDNode > ( Callee ) ) { return false ; } if ( ! CCMatch ) { bool R = ( CallerCC == CallingConv :: C || CallerCC == CallingConv :: Fast ) ; bool E = ( CalleeCC == CallingConv :: C || CalleeCC == CallingConv :: Fast ) ; if ( ! R || ! E ) return false ; } if ( isVarArg ) return


<s> return __builtin_mve_vrhaddq_uv4si ( __a ,


<s> DAG = static_cast < <ISA_LIT>MachineScheduler * > ( dag ) ; SchedModel = DAG -> getSchedModel ( ) ; Top . init ( DAG , SchedModel ) ; Bot . init ( DAG , SchedModel ) ; const InstrItineraryData * Itin = DAG -> getSchedModel ( ) -> getInstrItineraries ( ) ; const TargetSubtargetInfo & STI = DAG -> MF . getSubtarget ( ) ; const TargetInstrInfo * TII = STI . getInstrInfo ( ) ; if ( ! <ISA_LIT>UseFullSched ) { llvm :: ForceTopDown = true ; } delete Top . HazardRec ; delete Bot . HazardRec ; Top . HazardRec = TII -> CreateTargetMIHazardRecognizer ( Itin , DAG ) ; Bot . HazardRec = TII -> CreateTargetMIHazardRecognizer ( Itin , DAG ) ; delete Top . ResourceModel ; delete Bot . ResourceModel ; Top . ResourceModel = new <ISA_LIT>ResourceModel ( STI , DAG -> getSchedModel ( ) ) ; Bot . ResourceModel = new <ISA_LIT>ResourceModel ( STI , DAG ->


<s> void <ISA_LIT>InstPrinterCommon :: printInstFlags ( const MCInst * MI , raw_ostream & O ) { const MCInstrDesc & Desc = MII . get ( MI -> getOpcode ( ) ) ; uint64_t TSFlags = Desc . TSFlags ; unsigned Flags = MI -> getFlags ( ) ; if ( ( TSFlags & <STR_LIT> ) || ( Flags & <STR_LIT> ) ) O << <STR_LIT> ; if ( ( TSFlags & <STR_LIT> ) || ( Flags & <STR_LIT> ) ) O << <STR_LIT> ; if ( Flags & <STR_LIT>


<s> if ( const IntrinsicInst * Intrinsic = dyn_cast < IntrinsicInst > ( V ) ) return <STR_LIT> ( Intrinsic -> getIntrinsicID ( ) ) ; if ( isa < CallInst > ( V ) || isa < InvokeInst > (


<s> unsigned BytesPerElement = VT . getVectorElementType ( ) . getStoreSize ( ) ; for ( unsigned I = <NUM_LIT> ; I < BytesPerElement ; ++ I ) Bytes


__artificial__ ) ) _fxsave ( void * __P ) {


<s> assert ( ! I -> isTerminator ( ) && <STR_LIT> ) ; if ( I -> readsRegister ( <STR_LIT> ) ) return nullptr ; switch ( I -> getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { unsigned ShiftAmt = <STR_LIT> ( I -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; if ( ! I -> getOperand ( <NUM_LIT> ) . isImm ( ) ) { DEBUG ( dbgs ( ) << <STR_LIT> << * I << '\n' ) ; return nullptr ; } else if ( I -> getOperand ( <NUM_LIT> ) . getImm ( ) << ShiftAmt >= <NUM_LIT> ) { DEBUG ( dbgs ( ) << <STR_LIT> << * I << '\n' ) ; return nullptr ; } else if ( ! MRI -> use_empty ( I -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ) { DEBUG ( dbgs ( ) << <STR_LIT> << * I << '\n' ) ; return nullptr ; } return I ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return nullptr ; } } DEBUG ( dbgs ( ) << <STR_LIT> << MBB -> getNumber ( ) << '\n' ) ; return


<s> gcc_checking_assert ( GET_CODE ( SET_SRC ( op1 ) ) == COMPARE ) ; flags = SET_DEST ( op1 ) ; flags_mode = GET_MODE ( flags ) ; if ( GET_MODE ( SET_SRC ( op1 ) ) != flags_mode ) return


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> if ( UseVZeroUpper ) addPass ( create<ISA_LIT>IssueVZeroUpperPass ( ) ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) { addPass ( create<ISA_LIT>FixupBWInsts ( ) ) ; addPass ( create<ISA_LIT>PadShortFunctions ( ) ) ; addPass ( create<ISA_LIT>FixupLEAs ( )


<s> PointerType * PtrType = PointerType :: get ( VT . getTypeForEVT ( * DAG . getContext ( ) ) , <ISA_LIT>AS :: PARAM_I_ADDRESS ) ; assert ( isInt < <NUM_LIT> > ( ByteOffset ) ) ; return DAG . getLoad ( VT , DL , DAG . getEntryNode ( ) , DAG . getConstant ( ByteOffset ,

DL , <STR_LIT> ) , MachinePointerInfo ( ConstantPointerNull :: get ( PtrType ) ) ) ;


<s> unsigned getOccupancy ( const GCNSubtarget & ST ) const { return std :: min ( ST . getOccupancyWithNumSGPRs ( getSGPRNum ( ) ) , ST . getOccupancyWithNumVGPRs ( getVGPRNum ( ST . hasGFX90AInsts


<s> if ( BaseOp1 . isReg ( ) && BaseOp1 . getReg ( ) != BaseOp2 . getReg ( ) ) return false ; if ( NumLoads > <NUM_LIT> ) return false ; if ( ! isPairableLdStInst ( FirstLdSt ) || ! isPairableLdStInst ( SecondLdSt ) ) return false ; unsigned FirstOpc = FirstLdSt . getOpcode ( ) ; unsigned SecondOpc = SecondLdSt . getOpcode ( ) ; if ( ! canPairLdStOpc ( FirstOpc , SecondOpc ) ) return false ; if ( ! isCandidateToMergeOrPair ( FirstLdSt ) || ! isCandidateToMergeOrPair ( SecondLdSt ) ) return false ; int64_t Offset1 = FirstLdSt . getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( isUnscaledLdSt ( FirstOpc ) && ! scaleOffset ( FirstOpc , Offset1 ) ) return false ; int64_t Offset2 = SecondLdSt . getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( isUnscaledLdSt ( SecondOpc ) && ! scaleOffset ( SecondOpc , Offset2 ) )


<s> void <ISA_LIT>BaseInstrInfo :: breakPartialRegDependency ( MachineBasicBlock :: iterator MI , unsigned OpNum , const TargetRegisterInfo * TRI ) const { assert ( MI && OpNum < MI -> getDesc ( ) . getNumDefs ( ) && <STR_LIT> ) ; assert ( TRI && <STR_LIT> ) ; const MachineOperand & MO = MI -> getOperand ( OpNum ) ; unsigned Reg = MO . getReg ( ) ; assert ( TargetRegisterInfo :: isPhysicalRegister ( Reg ) && <STR_LIT> ) ; unsigned DReg = Reg ; if ( <STR_LIT> . contains ( Reg ) ) { DReg = <STR_LIT> + ( Reg - <STR_LIT> ) / <NUM_LIT> ; assert ( TRI -> isSuperRegister ( Reg , DReg ) && <STR_LIT> ) ; } assert ( <STR_LIT> . contains ( DReg ) &&


<s> } unsigned CopyFromExec = CopyFromExecInst -> getOperand ( <NUM_LIT> ) . getReg ( ) ; MachineInstr * SaveExecInst = nullptr ; SmallVector < MachineInstr * , <NUM_LIT> > OtherUseInsts ; for ( MachineBasicBlock :: iterator J = std :: next ( CopyFromExecInst -> getIterator ( ) ) , JE = I -> getIterator ( ) ; J != JE ; ++ J ) { if ( SaveExecInst && J -> readsRegister ( <STR_LIT> , TRI ) ) { DEBUG ( dbgs ( ) << <STR_LIT> << * J << '\n' ) ; SaveExecInst = nullptr ; break ; } bool ReadsCopyFromExec = J -> readsRegister ( CopyFromExec , TRI ) ; if ( J -> modifiesRegister ( CopyToExec , TRI ) ) { if ( SaveExecInst ) { DEBUG ( dbgs ( ) << <STR_LIT> << printReg ( CopyToExec , TRI ) << '\n' ) ; SaveExecInst = nullptr ; break ; } unsigned SaveExecOp = getSaveExecOp ( J -> getOpcode ( ) ) ; if ( SaveExecOp == <STR_LIT> ) break ; if ( ReadsCopyFromExec ) { SaveExecInst = & * J ; DEBUG ( dbgs ( ) << <STR_LIT> << * SaveExecInst << '\n' ) ; continue ; } else { DEBUG ( dbgs ( ) << <STR_LIT> << * J << '\n' ) ; break ; } } else if ( ReadsCopyFromExec && ! SaveExecInst ) { DEBUG ( dbgs ( ) << <STR_LIT> << * J << '\n' ) ; break ; } if ( SaveExecInst && J -> readsRegister ( CopyToExec , TRI ) ) { assert ( SaveExecInst != & * J ) ; OtherUseInsts . push_back ( & * J ) ; } } if ( ! SaveExecInst ) continue ; DEBUG ( dbgs ( ) << <STR_LIT> << * SaveExecInst << '\n' ) ; MachineOperand & Src0 = SaveExecInst -> getOperand ( <NUM_LIT> ) ; MachineOperand & Src1 = SaveExecInst -> getOperand ( <NUM_LIT> ) ; MachineOperand * OtherOp = nullptr ; if ( Src0 . isReg ( ) && Src0 . getReg ( ) == CopyFromExec ) { OtherOp = & Src1 ; } else if ( Src1 . isReg ( ) && Src1 . getReg ( ) == CopyFromExec ) { if ( ! SaveExecInst -> isCommutable ( ) ) break ; OtherOp = & Src0 ; } else llvm_unreachable ( <STR_LIT> ) ; CopyFromExecInst -> eraseFromParent ( ) ; auto InsPt = SaveExecInst -> getIterator ( ) ; const DebugLoc & DL = SaveExecInst ->


<s> if ( <STR_LIT> ( Opc ) == - <NUM_LIT> ) Opc = <STR_LIT> ( Opc ) ; if ( <STR_LIT> ( Opc ) == - <NUM_LIT> ) return false ; if ( ! ST . hasSDWAOmod ( ) && TII -> hasModifiersSet ( MI , <STR_LIT> :: omod ) ) return false ; if ( TII -> isVOPC ( Opc ) ) { if ( ! ST . hasSDWASdst ( ) ) { const MachineOperand * SDst = TII -> getNamedOperand ( MI , <STR_LIT> :: sdst ) ; if ( SDst && ( SDst -> getReg ( ) != <STR_LIT> && SDst -> getReg ( ) != <STR_LIT> )


<s> case <STR_LIT> : case <STR_LIT> : PointerType * PtrTy = cast < PointerType > ( I . getArgOperand ( <NUM_LIT> ) -> getType ( ) ) ; Info . opc = <STR_LIT> ; Info . memVT = <STR_LIT> ( PtrTy -> getElementType ( ) ) ; Info . ptrVal = I . getArgOperand ( <NUM_LIT> ) ; Info . offset = <NUM_LIT> ; Info . align = <NUM_LIT> ; Info . flags = MachineMemOperand :: MOLoad | MachineMemOperand :: MOStore


<s> bool isFLAT ( uint16_t Opcode ) const { return get ( Opcode ) . TSFlags &


<s> unsigned Bits = Ty . getSizeInBits ( ) ; unsigned Pow2Bits = <NUM_LIT> << Log2_32_Ceil ( Bits


<s> if ( kind1 != kind2 ) return <NUM_LIT> ; if ( ! lookup_attribute ( <STR_LIT> , TYPE_ATTRIBUTES ( type1 ) ) != ! lookup_attribute ( <STR_LIT> , TYPE_ATTRIBUTES ( type2 ) ) ) return <NUM_LIT> ; if ( ! lookup_attribute ( <STR_LIT> , TYPE_ATTRIBUTES ( type1 ) ) != ! lookup_attribute ( <STR_LIT> , TYPE_ATTRIBUTES ( type2 ) ) ) return <NUM_LIT> ; if ( ! lookup_attribute ( <STR_LIT> , TYPE_ATTRIBUTES ( type1 ) ) != ! lookup_attribute ( <STR_LIT> , TYPE_ATTRIBUTES ( type2 ) ) ) return <NUM_LIT> ; if ( ! lookup_attribute ( <STR_LIT> , TYPE_ATTRIBUTES ( type1 ) ) != ! lookup_attribute ( <STR_LIT> , TYPE_ATTRIBUTES ( type2 ) ) ) return <NUM_LIT> ; return


<s> if ( const auto & Loc = MI . getDebugLoc ( ) ) if ( const auto * Samples = TopSamples -> findFunctionSamples ( Loc ) ) return Samples -> findCallTargetMapAt ( FunctionSamples :: getOffset ( Loc ) , Loc -> getBaseDiscriminator ( ) ) ; return std :: error_code


<s> return createMacroFusionDAGMutation ( shouldScheduleAdjacent


<s> return ( poly8x8_t ) __builtin_neon_vdup_nv8qi ( ( __builtin_neon_qi


<s> if ( ! TARGET_LINK_STACK ) return ; get_ppc476_thunk_name ( name ) ; decl = build_decl ( BUILTINS_LOCATION , FUNCTION_DECL , get_identifier ( name ) , build_function_type_list ( void_type_node , NULL_TREE ) ) ; DECL_RESULT ( decl ) = build_decl ( BUILTINS_LOCATION , RESULT_DECL , NULL_TREE , void_type_node ) ; TREE_PUBLIC ( decl ) = <NUM_LIT> ; TREE_STATIC ( decl ) = <NUM_LIT> ; if ( USE_HIDDEN_LINKONCE ) { cgraph_node :: create ( decl ) -> set_comdat_group ( DECL_ASSEMBLER_NAME ( decl ) ) ; targetm . asm_out . unique_section ( decl , <NUM_LIT> ) ; switch_to_section ( get_named_section ( decl , NULL , <NUM_LIT> ) ) ; DECL_WEAK ( decl ) = <NUM_LIT> ; ASM_WEAKEN_DECL ( asm_out_file , decl , name , <NUM_LIT> ) ; targetm . asm_out . globalize_label ( asm_out_file , name ) ; targetm . asm_out . assemble_visibility ( decl , VISIBILITY_HIDDEN ) ; ASM_DECLARE_FUNCTION_NAME ( asm_out_file , name , decl ) ; } else { switch_to_section (


<s> const <ISA_LIT>FrameLowering * getFrameLowering ( ) const override { return &


<s> cmpReg1 = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( secondReg ) { cmpOp2 = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; if ( secondReg && ! TargetRegisterInfo :: isPhysicalRegister ( cmpOp2 ) ) { MachineInstr * def = MRI . getVRegDef ( cmpOp2 ) ; if ( def -> getOpcode ( ) == TargetOpcode :: COPY ) return false ; } } ++ II ; for ( MachineBasicBlock :: iterator localII = II ; localII != end ; ++ localII ) { if ( ! commonChecksToProhibitNewValueJump ( optLocation , localII ) ) return false ; if ( localII -> modifiesRegister ( pReg , TRI ) || localII -> readsRegister ( pReg , TRI ) ) return false ; if ( localII -> modifiesRegister ( cmpReg1 , TRI ) || ( secondReg && localII -> modifiesRegister ( cmpOp2


<s> else ++ slotsUsed ; } if ( slotsUsed > HEXAGON_PACKET_SIZE ) { <ISA_LIT>MCErrInfo errInfo ; errInfo . setError ( <STR_LIT> ) ; addErrInfo ( errInfo ) ; return false ; } return true


<s> if ( MI . modifiesRegister ( <STR_LIT> , & RI ) || MI . readsRegister ( <STR_LIT> , & RI ) || MI . getDesc ( ) . hasImplicitUseOfPhysReg ( <STR_LIT> ) || MI . getDesc ( ) . hasImplicitDefOfPhysReg ( <STR_LIT> ) ) return outliner :: InstrType :: Illegal ; if ( MI . readsRegister ( <STR_LIT> , & RI ) || MI . getDesc ( ) . hasImplicitUseOfPhysReg ( <STR_LIT> ) || MI . getDesc ( ) . hasImplicitDefOfPhysReg ( <STR_LIT> ) ) return outliner :: InstrType :: Illegal ; if ( MI . isPosition ( ) ) return outliner :: InstrType :: Illegal ; for ( const MachineOperand & MOP : MI . operands ( ) ) if ( MOP . isCPI ( ) || MOP . isJTI ( ) || MOP . isCFIIndex ( ) || MOP . isFI ( ) || MOP . isTargetIndex ( ) ) return outliner :: InstrType :: Illegal ; return outliner :: InstrType ::


<s> unsigned End = KillInst ? KillInstIdx : LastInstIdx ; unsigned OtherEnd = Other . KillInst ? Other . KillInstIdx : Other . LastInstIdx ; return StartInstIdx <= OtherEnd && Other . StartInstIdx <=


<s> if ( context -> br_loc [ <NUM_LIT> ] && * context -> br_loc [ <NUM_LIT> ] != context -> rp ) { fs -> curr . reg [ UNW_REG_RP ] . where = UNW_WHERE_BR ; fs -> curr . reg [ UNW_REG_RP ] . when = - <NUM_LIT> ; fs -> curr . reg [ UNW_REG_RP ] . val = <NUM_LIT> ; goto success ; } return _URC_END_OF_STACK ; success : return _URC_NO_REASON ; return _URC_END_OF_STACK ; } context -> region_start = ent -> start_offset + segment_base ; fs -> when_target = ( context -> rp - context -> region_start ) / <NUM_LIT> * <NUM_LIT> ; unw = ( unsigned long * ) ( ent -> info_offset + segment_base ) ; header = * unw ; length = UNW_LENGTH ( header ) ; if ( UNW_FLAG_EHANDLER ( header ) | UNW_FLAG_UHANDLER ( header ) ) { fs -> personality = * ( _Unwind_Personality_Fn * ) ( unw [ length + <NUM_LIT> ] + context -> gp ) ; context -> lsda = unw + length + <NUM_LIT> ; } insn = ( unsigned char * ) ( unw + <NUM_LIT> ) ; insn_end = ( unsigned char * ) ( unw + <NUM_LIT> + length ) ; while ( ! fs -> done && insn < insn_end ) insn = unw_decode ( insn , fs -> in_body , fs ) ; free_label_states ( fs -> labeled_states ) ; free_state_stack ( & fs -> curr ) ; if ( reg_state_alloced || labeled_state_alloced ) abort ( ) ; if ( fs -> when_target > fs -> epilogue_start ) { struct unw_reg_info * r ; fs -> curr . reg [ UNW_REG_PSP ] . where = UNW_WHERE_NONE ; fs -> curr . reg [ UNW_REG_PSP ] . val = <NUM_LIT> ; for ( r = fs -> curr . reg ; r < fs -> curr . reg + UNW_NUM_REGS ; ++ r ) if ( ( r -> where == UNW_WHERE_PSPREL && r -> val <=

<NUM_LIT> ) || r -> where == UNW_WHERE_SPREL ) r -> where = UNW_WHERE_NONE ;


<s> if ( ! NoOpt ) addPass ( create<ISA_LIT>NewValueJump ( ) , false ) ; addPass ( create<ISA_LIT>BranchRelaxation ( ) , false ) ; if ( ! NoOpt ) { if ( ! DisableHardwareLoops ) addPass ( create<ISA_LIT>FixupHwLoops ( ) , false ) ; if ( EnableGenMux ) addPass ( create<ISA_LIT>GenMux ( ) , false ) ; addPass ( create<ISA_LIT>Packetizer ( )


<s> IncomingValueHandler :: assignValueToReg ( ValVReg , PhysReg


<s> } for ( int i = MFI . getObjectIndexBegin ( ) , e = MFI . getObjectIndexEnd ( ) ; i != e ; ++ i ) if ( i != FramePointerSaveIndex ) MFI . setStackID ( i , TargetStackID :: Default ) ; for ( auto & R : VGPRToAGPRSpills ) { if ( R . second . FullyAllocated ) MFI .


<s> return getInsertVINSERTImmediate ( N ,


<s> CodeEmitter . reset ( TM . getTarget ( ) . createMCCodeEmitter ( * MF . getSubtarget ( ) . getInstrInfo ( ) , * MF . getSubtarget ( ) . getRegisterInfo ( ) , MF . getContext ( ) ) ) ; SetupMachineFunction ( MF


<s> MCSectionELF * EHSection = getContext ( ) . getELFSection ( EHSecName , Type , Flags , <NUM_LIT> , Group , true , FnSection . getUniqueID ( ) , static_cast < const MCSymbolELF * > ( FnSection . getBeginSymbol ( ) ) ) ; assert ( EHSection && <STR_LIT> ) ; SwitchSection ( EHSection ) ; emitValueToAlignment ( <NUM_LIT> , <NUM_LIT> , <NUM_LIT>


<s> if ( ! SrcTy . isSimple ( ) || ! DstTy . isSimple ( ) ) return TargetTransformInfo :: getCastInstrCost ( Opcode , Dst , Src ) ; static const TypeConversionCostTblEntry < MVT > AVXConversionTbl [ ] = { { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } , } ; if ( ST -> hasAVX ( ) ) { int Idx = ConvertCostTableLookup < MVT > ( AVXConversionTbl , array_lengthof ( AVXConversionTbl ) , ISD , DstTy . getSimpleVT ( ) , SrcTy . getSimpleVT ( ) ) ; if ( Idx != - <NUM_LIT> )

return AVXConversionTbl [ Idx ] . Cost ;


<s> const MachineOperand & MO = MI -> getOperand ( OpNum ) ; unsigned TF = MO . getTargetFlags ( ) ; switch ( MO . getType ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case MachineOperand :: MO_Register : { unsigned Reg = MO . getReg ( ) ; assert ( TargetRegisterInfo :: isPhysicalRegister ( Reg ) ) ; assert ( ! MO . getSubReg ( ) && <STR_LIT> ) ; if ( <STR_LIT> . contains ( Reg ) ) { const MachineFunction & MF = * MI -> getParent ( ) -> getParent ( ) ; const TargetRegisterInfo * TRI = MF . getTarget ( ) . getRegisterInfo ( ) ; Reg = TRI -> getSubReg ( Reg , <STR_LIT> ) ; } O << <ISA_LIT>InstPrinter :: getRegisterName ( Reg ) ; break ; } case MachineOperand :: MO_Immediate : { int64_t Imm = MO . getImm ( ) ; O << '#' ; if ( ( Modifier && strcmp ( Modifier , <STR_LIT> ) == <NUM_LIT> ) || ( TF == <STR_LIT> ) ) O << <STR_LIT> ; else if ( ( Modifier && strcmp ( Modifier , <STR_LIT> ) == <NUM_LIT> ) || ( TF == <STR_LIT> ) ) O << <STR_LIT> ; O << Imm ; break ; } case MachineOperand :: MO_MachineBasicBlock


<s> MachineBasicBlock :: iterator BeforeI = I ; if ( ! AtStart ) -- BeforeI ; if ( ! TFI -> restoreCalleeSavedRegisters ( * MBB , I , CSI , TRI ) ) { for ( unsigned i = <NUM_LIT> , e = CSI . size ( ) ; i != e ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ; TII . loadRegFromStackSlot ( * MBB , I , Reg , CSI [ i ] . getFrameIdx ( ) , RC , TRI ) ; assert ( I != MBB -> begin ( ) && <STR_LIT> ) ; if ( AtStart ) I =


<s> unsigned <ISA_LIT>BaseRegisterInfo :: getRARegister ( ) const { return <STR_LIT>


<s> MRI = & F . getRegInfo ( ) ; TRI = F . getRegInfo ( ) . getTargetRegisterInfo ( ) ; RCI . runOnMachineFunction ( F ) ; for ( auto & MBB : F ) { Changed |= runOnBasicBlock


<s> if ( expect ( AsmToken :: Comma , <STR_LIT> ) ) return true ; auto TypeTok = Lexer . getTok ( ) ; auto TypeName = expectIdent ( ) ; if ( TypeName . empty ( ) ) return true ; auto Type = <STR_LIT> ( TypeName ) ; if ( ! Type ) return error ( <STR_LIT> , TypeTok ) ; bool Mutable = true ; if ( isNext ( AsmToken :: Comma ) ) { TypeTok = Lexer . getTok ( ) ; auto Id = expectIdent ( ) ; if ( Id == <STR_LIT> ) Mutable = false ; else return error ( <STR_LIT> , TypeTok ) ; } auto WasmSym = cast < MCSymbolWasm > ( Ctx . getOrCreateSymbol ( SymName ) ) ; WasmSym -> setType ( <STR_LIT> ) ; WasmSym -> setGlobalType ( <STR_LIT> { uint8_t ( Type . getValue ( ) ) , Mutable } ) ; TOut . emitGlobalType ( WasmSym ) ; return expect ( AsmToken :: EndOfStatement , <STR_LIT> ) ; } if ( DirectiveID . getString ( ) == <STR_LIT> ) { auto SymName = expectIdent ( ) ; if ( SymName . empty ( ) ) return true ; if ( expect ( AsmToken :: Comma , <STR_LIT> ) ) return true ; auto ElemTypeTok = Lexer . getTok ( ) ; auto ElemTypeName = expectIdent ( ) ; if ( ElemTypeName . empty ( ) ) return true ; Optional < <STR_LIT> > ElemType = <STR_LIT> ( ElemTypeName ) ; if ( ! ElemType ) return error ( <STR_LIT> , ElemTypeTok ) ; <STR_LIT> Limits = DefaultLimits ( ) ; if ( isNext ( AsmToken :: Comma ) && parseLimits ( & Limits ) ) return true ; auto WasmSym = cast < MCSymbolWasm > ( Ctx . getOrCreateSymbol ( SymName ) ) ; WasmSym -> setType ( <STR_LIT> ) ; <STR_LIT> Type = { uint8_t ( ElemType . getValue ( ) ) , Limits } ; WasmSym -> setTableType ( Type ) ; TOut . emitTableType ( WasmSym ) ; return expect ( AsmToken :: EndOfStatement , <STR_LIT> ) ; } if ( DirectiveID . getString ( ) == <STR_LIT> ) { auto SymName = expectIdent ( ) ; if ( SymName . empty ( ) ) return true ; auto WasmSym = cast < MCSymbolWasm > ( Ctx . getOrCreateSymbol ( SymName ) ) ; if ( WasmSym -> isDefined ( ) ) { if ( ensureEmptyNestingStack ( )


<s> SDValue GlobalBase = DAG . getNode ( <STR_LIT> , dl , getPointerTy ( ) ) ; SDValue RelAddr = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Lo , Hi ) ; SDValue AbsAddr = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , GlobalBase , RelAddr ) ; return DAG . getLoad ( getPointerTy ( ) , dl , DAG . getEntryNode ( ) , AbsAddr , NULL , <NUM_LIT> , false , false


<s> const <ISA_LIT>InstrInfo * TII = static_cast < const <ISA_LIT>InstrInfo * > ( Subtarget . getInstrInfo ( ) ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; bool IsSubWord = ( BitSize < <NUM_LIT> ) ; Register Dest = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; MachineOperand Base = earlyUseOperand ( MI . getOperand ( <NUM_LIT> ) ) ; int64_t Disp = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; MachineOperand Src2 = earlyUseOperand ( MI . getOperand ( <NUM_LIT> ) ) ; Register BitShift = IsSubWord ? MI . getOperand ( <NUM_LIT> ) . getReg ( ) : Register ( ) ; Register NegBitShift = IsSubWord ? MI . getOperand ( <NUM_LIT> ) . getReg ( ) : Register ( ) ; DebugLoc DL = MI . getDebugLoc ( ) ; if ( IsSubWord ) BitSize = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; const TargetRegisterClass * RC = ( BitSize <= <NUM_LIT> ? & <STR_LIT> : & <STR_LIT> ) ; unsigned LOpcode = BitSize <= <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; unsigned CSOpcode = BitSize <= <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; LOpcode = TII -> getOpcodeForOffset ( LOpcode , Disp ) ; CSOpcode = TII -> getOpcodeForOffset ( CSOpcode , Disp ) ; assert ( LOpcode && CSOpcode && <STR_LIT> ) ; Register OrigVal = MRI . createVirtualRegister ( RC ) ; Register OldVal = MRI . createVirtualRegister ( RC ) ; Register NewVal = ( BinOpcode || IsSubWord ? MRI . createVirtualRegister ( RC ) : Src2 . getReg ( ) ) ; Register RotatedOldVal = ( IsSubWord ? MRI . createVirtualRegister ( RC ) : OldVal ) ; Register RotatedNewVal = ( IsSubWord ? MRI . createVirtualRegister ( RC ) : NewVal ) ; MachineBasicBlock * StartMBB = MBB ; MachineBasicBlock * DoneMBB = <STR_LIT> ( MI , MBB ) ; MachineBasicBlock * LoopMBB = <STR_LIT> ( StartMBB ) ; MBB = StartMBB ; BuildMI ( MBB , DL , TII -> get ( LOpcode ) , OrigVal ) . add ( Base ) . addImm ( Disp ) . addReg ( <NUM_LIT> ) ; MBB -> addSuccessor ( LoopMBB ) ; MBB = LoopMBB


<s> rtx dest = operands [ <NUM_LIT> ] ; enum rtx_code code = GET_CODE ( operands [ <NUM_LIT> ] ) ; rtx op0 = operands [ <NUM_LIT> ] ; rtx op1 = operands [ <NUM_LIT> ] ; rtx


<s> uint64_t RequiredAlign = std :: max ( AlignVal , StackAlign ) ; uint64_t ExtraAlignSpace = RequiredAlign - StackAlign ; unsigned SPReg = getStackPointerRegisterToSaveRestore ( ) ; SDValue NeededSpace = Size ; SDValue OldSP = DAG . getCopyFromReg ( Chain , DL , SPReg , <STR_LIT> ) ; SDValue Backchain ; if ( StoreBackchain ) Backchain = DAG . getLoad ( <STR_LIT> , DL , Chain , OldSP , MachinePointerInfo ( ) ) ; if ( ExtraAlignSpace ) NeededSpace = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , NeededSpace , DAG . getConstant ( ExtraAlignSpace , DL , <STR_LIT> ) ) ; SDValue NewSP = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , OldSP , NeededSpace ) ; Chain = DAG . getCopyToReg ( Chain , DL ,


<s> StoreOpcode = TII -> getOpcodeForOffset ( StoreOpcode , Disp ) ; if ( STOCOpcode && ! IndexReg && Subtarget . hasLoadStoreOnCond ( ) ) { if ( Invert ) CCMask ^= CCValid ; MachineMemOperand * MMO = nullptr ; for ( auto * I : MI . memoperands ( ) ) if ( I -> isStore ( ) ) { MMO = I ; break ; } BuildMI ( * MBB , MI , DL , TII -> get ( STOCOpcode ) ) . addReg ( SrcReg ) . add ( Base ) . addImm ( Disp ) . addImm ( CCValid ) . addImm ( CCMask ) . addMemOperand ( MMO ) ; MI . eraseFromParent ( ) ; return MBB ; } if ( ! Invert ) CCMask ^= CCValid ; MachineBasicBlock * StartMBB = MBB ; MachineBasicBlock * JoinMBB = <STR_LIT> ( MI , MBB ) ; MachineBasicBlock * FalseMBB = <STR_LIT> ( StartMBB ) ; if ( ! MI . killsRegister ( <STR_LIT> ) && ! checkCCKill ( MI , JoinMBB ) ) { FalseMBB -> addLiveIn ( <STR_LIT> ) ; JoinMBB -> addLiveIn ( <STR_LIT> ) ; } MBB = StartMBB ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) ) . addImm ( CCValid ) . addImm ( CCMask ) . addMBB ( JoinMBB ) ; MBB -> addSuccessor ( JoinMBB ) ; MBB -> addSuccessor ( FalseMBB ) ; MBB =


<s> } if ( UC . cantUnwind ( ) ) { Error ( L , <STR_LIT> ) ; UC . emitCantUnwindLocNotes ( ) ; return false ; } if ( UC . hasHandlerData ( ) ) { Error ( L , <STR_LIT> ) ; UC . emitHandlerDataLocNotes ( ) ; return false ; } if ( HasExistingPersonality ) { Parser . eatToEndOfStatement ( ) ; Error ( L , <STR_LIT> ) ; UC . emitPersonalityLocNotes ( ) ; return false ; } if ( Parser . getTok ( ) . isNot ( AsmToken :: Identifier ) ) { Parser . eatToEndOfStatement ( ) ; Error ( L , <STR_LIT> ) ; return


<s> MI . getOperand ( FIOperandNum ) . ChangeToRegister ( FrameReg , false , false , FrameRegIsKill ) ; if ( ! IsRVVSpill ) MI . getOperand ( FIOperandNum + <NUM_LIT> ) . ChangeToImmediate ( Offset . getFixed ( ) ) ; else { if ( Offset . getFixed ( ) ) { Register ScratchReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( MBB , II , DL , TII -> get ( <STR_LIT> ) , ScratchReg ) . addReg ( FrameReg , getKillRegState ( FrameRegIsKill ) ) . addImm ( Offset . getFixed ( ) ) ; MI . getOperand ( FIOperandNum ) . ChangeToRegister ( ScratchReg , false , false , true ) ; } } } else { assert ( ScalableFactorRegister && <STR_LIT> ) ; if ( MI . getOpcode ( ) == <STR_LIT> && ! Offset . getFixed ( ) ) { BuildMI ( MBB , II , DL , TII -> get ( ScalableAdjOpc ) , MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( FrameReg , getKillRegState ( FrameRegIsKill ) ) . addReg ( ScalableFactorRegister , RegState :: Kill ) ; MI . eraseFromParent ( ) ; return ; } Register VL = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( MBB , II , DL , TII -> get ( ScalableAdjOpc ) , VL ) . addReg ( FrameReg , getKillRegState ( FrameRegIsKill ) ) . addReg ( ScalableFactorRegister , RegState :: Kill ) ; if ( IsRVVSpill && Offset . getFixed ( ) ) { BuildMI ( MBB , II , DL , TII -> get ( <STR_LIT> ) , VL ) . addReg ( VL ) . addImm ( Offset . getFixed ( ) ) ; } MI . getOperand ( FIOperandNum ) . ChangeToRegister ( VL , false , false , true ) ; if ( ! IsRVVSpill ) MI . getOperand ( FIOperandNum + <NUM_LIT> ) . ChangeToImmediate ( Offset . getFixed ( ) ) ; } auto ZvlssegInfo = TII -> isRVVSpillForZvlsseg ( MI . getOpcode ( ) ) ; if ( ZvlssegInfo ) { Register VL = MRI . createVirtualRegister ( &


<s> if ( DCI . isBeforeLegalizeOps ( ) || ! Subtarget -> has<ISA_LIT>32r2 ( ) ) return SDValue ( ) ; SDValue And0 = N -> getOperand ( <NUM_LIT> ) , And1 = N -> getOperand ( <NUM_LIT> ) ; uint64_t SMPos0 , SMSize0 , SMPos1 , SMSize1 ; ConstantSDNode * CN ; if ( And0 . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; if ( ! ( CN = dyn_cast < ConstantSDNode > ( And0 . getOperand ( <NUM_LIT> ) ) ) || ! isShiftedMask ( ~ CN -> getSExtValue ( ) , SMPos0 , SMSize0 ) ) return SDValue ( ) ; if ( And1 . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; if ( ! ( CN = dyn_cast < ConstantSDNode > ( And1 . getOperand ( <NUM_LIT> ) ) ) || ! isShiftedMask ( CN -> getZExtValue ( ) , SMPos1 , SMSize1 ) ) return SDValue ( ) ; if ( SMPos0 != SMPos1 || SMSize0 != SMSize1


<s> return getSubExpr ( ) -> FindAssociatedSection


<s> if ( ! Arg -> isRegister ( ) || ! Arg -> getRegister ( ) . isValid ( ) ) return false ; Register SrcReg = Arg -> getRegister ( ) ; assert ( SrcReg . isPhysical ( ) && <STR_LIT> ) ; assert ( DstReg . isVirtual ( ) && <STR_LIT> ) ; MachineRegisterInfo & MRI = * B . getMRI ( ) ; LLT Ty = MRI . getType ( DstReg ) ; Register LiveIn = getLiveInRegister ( B , MRI , SrcReg , Ty ) ; if ( Arg -> isMasked ( ) ) { const LLT S32 = LLT :: scalar ( <NUM_LIT> ) ; const unsigned Mask = Arg -> getMask ( ) ; const unsigned Shift = countTrailingZeros < unsigned > ( Mask ) ; Register AndMaskSrc = LiveIn ; if ( Shift != <NUM_LIT> ) { auto ShiftAmt = B . buildConstant ( S32


<s> ~ <ISA_LIT>AsmBackend ( ) override { delete STI


<s> case CallingConv :: <ISA_LIT>_VS : case CallingConv :: <ISA_LIT>_GS : case CallingConv :: <ISA_LIT>_PS : case CallingConv :: <ISA_LIT>_CS : case CallingConv :: <ISA_LIT>_HS : case CallingConv :: <ISA_LIT>_ES : case CallingConv :: <ISA_LIT>_LS : return CC_<ISA_LIT>


<s> return ( __m128i ) __builtin_ia32_cvtps2uqq128_mask ( ( __v4sf ) __A , ( __v2di ) _mm_setzero_di ( ) ,


<s> return for_each_rtx ( & PATTERN ( insn ) ,


<s> FunctionPass * llvm :: create<ISA_LIT>ExpandPredSpillCode ( const <ISA_LIT>TargetMachine & TM ) { return new <ISA_LIT>ExpandPredSpillCode


<s> assert ( findPHIInfoElement ( DestReg ) == nullptr && <STR_LIT> ) ; PHISourcesT EmptySet ; PHIInfoElementT * NewElement = new PHIInfoElementT ( ) ; NewElement -> DestReg = DestReg ; NewElement -> DL = DL ; NewElement -> Sources = EmptySet ; PHIInfo . insert ( NewElement


<s> for ( i = <NUM_LIT> , num_regs = <NUM_LIT> ; i <= LAST_ARM_REGNUM ; i ++ ) if ( saved_regs_mask & ( <NUM_LIT> << i ) ) num_regs ++ ; if ( ! simple_return && saved_regs_mask ) { gcc_assert ( ! IS_CMSE_ENTRY ( arm_current_func_type ( ) ) ) ; if ( arm_current_function_pac_enabled_p ( ) ) { gcc_assert ( ! ( saved_regs_mask & ( <NUM_LIT> << PC_REGNUM ) ) ) ; arm_emit_multi_reg_pop ( saved_regs_mask ) ; emit_insn ( gen_aut_nop ( ) ) ; emit_jump_insn ( simple_return_rtx ) ; } else if ( num_regs == <NUM_LIT> ) { rtx par = gen_rtx_PARALLEL ( VOIDmode , rtvec_alloc ( <NUM_LIT> ) ) ; rtx reg = gen_rtx_REG ( SImode , PC_REGNUM ) ; rtx addr = gen_rtx_MEM ( SImode , gen_rtx_POST_INC ( SImode , stack_pointer_rtx ) ) ; set_mem_alias_set ( addr , get_frame_alias_set ( ) ) ; XVECEXP ( par , <NUM_LIT> , <NUM_LIT> ) = ret_rtx ; XVECEXP ( par , <NUM_LIT> , <NUM_LIT> ) = gen_rtx_SET ( reg , addr ) ; RTX_FRAME_RELATED_P ( XVECEXP ( par , <NUM_LIT> , <NUM_LIT> ) ) = <NUM_LIT> ; emit_jump_insn ( par ) ; } else { saved_regs_mask &= ~ ( <NUM_LIT> << LR_REGNUM ) ; saved_regs_mask |= ( <NUM_LIT> << PC_REGNUM ) ; arm_emit_multi_reg_pop ( saved_regs_mask ) ; } } else { if ( IS_CMSE_ENTRY ( arm_current_func_type ( )


<s> switch ( getTokenKind ( ) ) { case AsmToken :: Identifier : { StringRef Tok = getTokenStr ( ) ; if ( Tok == Name ) { if ( Tok == <STR_LIT> && ! hasMIMG_R128 ( ) ) Error ( S , <STR_LIT> ) ; if ( Tok == <STR_LIT> && ! isGFX9 ( ) && ! hasGFX10A16 ( ) ) Error ( S , <STR_LIT> ) ; Bit = <NUM_LIT> ; Parser . Lex ( ) ; } else if ( Tok . startswith ( <STR_LIT> ) && Tok . endswith ( Name ) ) { Bit = <NUM_LIT> ; Parser . Lex ( ) ; } else { return


<s> RegisterMCAsmParser < <ISA_LIT>AsmParser > Y


<s> static SDValue LowerSCALAR_TO_VECTOR ( SDValue Op , SelectionDAG & DAG ) { SDLoc dl ( Op ) ; MVT OpVT = Op . getSimpleValueType ( ) ; if ( ! OpVT . is128BitVector ( ) ) { unsigned SizeFactor = OpVT . getSizeInBits ( ) / <NUM_LIT> ; MVT VT128 = <STR_LIT> ( OpVT . getVectorElementType ( ) , OpVT . getVectorNumElements ( ) / SizeFactor ) ; Op = DAG . getNode ( <STR_LIT> , dl , VT128 , Op . getOperand ( <NUM_LIT> ) ) ; return insert128BitVector ( DAG . getUNDEF ( OpVT ) , Op , <NUM_LIT> , DAG , dl ) ; } SDValue AnyExt = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) ) ; assert ( OpVT . is128BitVector (


<s> } } case Instruction :: Mul : { Value * MulOp0 = I -> getOperand ( <NUM_LIT> ) ; Value * MulOp1 = I -> getOperand ( <NUM_LIT> ) ; if ( isa < SExtInst > ( MulOp0 ) && isa < SExtInst > ( MulOp1 ) ) { ValueList LHS ; ValueList RHS ; if ( IsNarrowSequence < <NUM_LIT> > ( MulOp0 , LHS ) && IsNarrowSequence < <NUM_LIT> > ( MulOp1 , RHS ) ) { R . InsertMul ( I , LHS , RHS ) ; return true ; } } return false ; } case Instruction :: SExt : return Search ( I -> getOperand ( <NUM_LIT> ) , BB , R ) ; } return false ; } ; bool Changed = false ; for ( auto & BB : F ) { SmallPtrSet < Instruction * , <NUM_LIT> > AllAdds ; if ( ! RecordMemoryOps ( & BB ) ) continue ; for ( Instruction & I : reverse ( BB ) ) { if ( I . getOpcode ( ) != Instruction :: Add ) continue ; if ( AllAdds . count ( & I ) ) continue ; const auto * Ty = I . getType ( ) ; if ( ! Ty -> isIntegerTy ( <NUM_LIT> ) && ! Ty -> isIntegerTy ( <NUM_LIT> ) ) continue ; Reduction R ( & I ) ; if ( ! Search ( & I , & BB , R ) ) continue ; if ( ! CreateParallelPairs ( R ) ) continue ; InsertParallelMACs ( R ) ; Changed = true ; AllAdds . insert ( R . getAdds ( ) . begin ( ) , R . getAdds ( ) . end ( ) ) ; } } return


<s> case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O <<


<s> int rv = m32c_hard_regno_nregs_1 ( regno , mode ) ; return rv ? rv


<s> UndefElts &= APInt :: getSplat ( NumElts , ! IsTop ? APInt :: getLowBitsSet ( <NUM_LIT> , <NUM_LIT> ) : APInt :: getHighBitsSet ( <NUM_LIT> , <NUM_LIT> ) ) ; return None ; } ; switch ( II . getIntrinsicID ( ) ) { default : break ; case <STR_LIT> : SimplifyNarrowInstrTopBottom ( <NUM_LIT> ) ; break ; case <STR_LIT> : SimplifyNarrowInstrTopBottom ( <NUM_LIT> ) ; break ; case <STR_LIT> : SimplifyNarrowInstrTopBottom ( <NUM_LIT>


<s> void <ISA_LIT>InstPrinter :: printPostIncOperand12 ( const MCInst * MI , unsigned OpNo


<s> static bool m32c_pass_by_reference ( cumulative_args_t


<s> SmallVectorImpl < MachineInstr * > & getDefUses ( ) { return


<s> assert ( ! RegInfo -> needsStackRealignment ( MF ) && <STR_LIT> ) ; return ( MFI -> hasCalls ( ) || MFI -> hasVarSizedObjects ( )


<s> case <STR_LIT> : return LowerShiftRightParts ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerCTTZ ( Op . getNode ( ) , DAG , Subtarget ) ; case <STR_LIT> : return LowerCTPOP ( Op . getNode ( ) , DAG , Subtarget ) ; case <STR_LIT> : return LowerVSETCC ( Op , DAG ) ; case <STR_LIT> : return LowerSETCCE ( Op , DAG ) ; case <STR_LIT> : return LowerConstantFP ( Op , DAG , Subtarget ) ; case <STR_LIT> : return LowerBUILD_VECTOR ( Op , DAG , Subtarget ) ; case <STR_LIT> : return LowerVECTOR_SHUFFLE ( Op , DAG ) ; case <STR_LIT> : return LowerINSERT_VECTOR_ELT ( Op , DAG ) ; case <STR_LIT> : return LowerEXTRACT_VECTOR_ELT ( Op , DAG ) ; case <STR_LIT> : return LowerCONCAT_VECTORS ( Op , DAG ) ; case <STR_LIT> : return LowerFLT_ROUNDS_ ( Op , DAG ) ; case <STR_LIT> : return LowerMUL ( Op , DAG ) ; case <STR_LIT> : if ( Subtarget -> isTargetWindows ( ) && ! Op . getValueType ( ) . isVector ( ) ) return LowerDIV_Windows ( Op , DAG , true ) ; return LowerSDIV ( Op , DAG ) ; case <STR_LIT> : if ( Subtarget -> isTargetWindows ( ) && ! Op . getValueType ( ) . isVector ( ) ) return LowerDIV_Windows ( Op , DAG , false ) ; return LowerUDIV ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerADDC_ADDE_SUBC_SUBE ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerADDSUBCARRY ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerSignedALUO ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerUnsignedALUO ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerAtomicLoadStore ( Op , DAG ) ; case <STR_LIT> : return LowerFSINCOS ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerDivRem ( Op , DAG ) ; case <STR_LIT> : if ( Subtarget -> getTargetTriple ( ) . isWindowsItaniumEnvironment ( ) ) return LowerDYNAMIC_STACKALLOC ( Op , DAG ) ; llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : return LowerFP_ROUND ( Op , DAG ) ; case <STR_LIT> : return LowerFP_EXTEND ( Op , DAG ) ; case <STR_LIT> : return LowerFPOWI ( Op


<s> static bool lessCVI ( const <ISA_LIT>Instr & A , const <ISA_LIT>Instr & B ) { return ( <STR_LIT> ( A . CVI , B .


<s> SDValue <ISA_LIT>TargetLowering :: storeStackInputValue ( SelectionDAG & DAG , const SDLoc & SL , SDValue Chain , SDValue ArgVal , int64_t Offset ) const { MachineFunction & MF = DAG . getMachineFunction ( ) ; MachinePointerInfo DstInfo = MachinePointerInfo :: getStack ( MF , Offset ) ; SDValue Ptr = DAG . getConstant ( Offset , SL , <STR_LIT> ) ; SDValue Store = DAG . getStore ( Chain , SL , ArgVal , Ptr , DstInfo , <NUM_LIT> , MachineMemOperand ::


<s> if ( Subtarget -> isTargetDarwin ( ) ) return getPointerTy ( DL ) . getSizeInBits


<s> for ( int i = <NUM_LIT> , e = Ty -> getVectorNumElements ( ) ; i < e ; ++ i ) { if ( Insert ) Cost += getVectorInstrCost ( Instruction :: InsertElement ,


<s> LPR . addLiveOuts ( MBB ) ; for ( MachineBasicBlock :: reverse_iterator I = MBB . rbegin ( ) , E = MBB . rend ( ) ; I != E ; ++ I ) { if ( I -> isDebugInstr ( ) ) continue ; std :: bitset < <NUM_LIT> > Defs ; SmallVector < MachineOperand * , <NUM_LIT> > Uses ; MachineInstr & MI = * I ; for ( auto & MO : I -> operands ( ) ) { if ( ! MO . isReg ( ) ) continue ; unsigned Reg = MO . getReg ( ) - <STR_LIT> ; if ( Reg >= <NUM_LIT> ) continue ; if ( MO . isDef ( ) ) { Defs . set


<s> const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; if ( IgnoreSPUpdates ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << FI << <STR_LIT> << MFI . getObjectOffset ( FI ) << <STR_LIT> ) ; FrameReg =


<s> case <NUM_LIT> : ldrOpc = isThumb2 ? <STR_LIT> : <STR_LIT> ; strOpc = isThumb2 ? <STR_LIT> : <STR_LIT> ; break ; } MachineBasicBlock * loopMBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * exitMBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MF -> insert ( It , loopMBB ) ; MF -> insert ( It , exitMBB ) ; exitMBB -> splice ( exitMBB -> begin ( ) , BB , llvm :: next ( MachineBasicBlock :: iterator ( MI ) ) , BB -> end ( ) ) ; exitMBB -> transferSuccessorsAndUpdatePHIs ( BB ) ; const TargetRegisterClass * TRC = isThumb2 ? <STR_LIT> : <STR_LIT> ; unsigned scratch = MRI . createVirtualRegister ( TRC ) ; unsigned scratch2 = ( ! BinOpcode ) ? incr : MRI . createVirtualRegister ( TRC ) ; BB -> addSuccessor ( loopMBB ) ; BB = loopMBB ; MachineInstrBuilder MIB = BuildMI ( BB , dl , TII -> get ( ldrOpc ) , dest ) . addReg ( ptr ) ; if ( ldrOpc == <STR_LIT> ) MIB . addImm ( <NUM_LIT> ) ; AddDefaultPred ( MIB ) ; if ( BinOpcode ) { if ( BinOpcode == <STR_LIT> || BinOpcode == <STR_LIT> ) AddDefaultPred ( BuildMI ( BB , dl , TII -> get ( BinOpcode ) , scratch2 ) . addReg ( incr ) . addReg ( dest ) ) . addReg ( <NUM_LIT> ) ; else AddDefaultPred ( BuildMI ( BB , dl , TII -> get ( BinOpcode ) , scratch2 ) . addReg ( dest ) . addReg ( incr ) ) . addReg ( <NUM_LIT> ) ; } MIB = BuildMI ( BB , dl , TII -> get ( strOpc ) , scratch ) . addReg ( scratch2 ) . addReg ( ptr ) ; if ( strOpc == <STR_LIT> ) MIB . addImm ( <NUM_LIT> ) ; AddDefaultPred ( MIB ) ; AddDefaultPred ( BuildMI ( BB , dl , TII -> get ( isThumb2 ? <STR_LIT> : <STR_LIT> ) ) . addReg ( scratch ) . addImm ( <NUM_LIT> ) ) ; BuildMI ( BB , dl , TII -> get ( isThumb2 ? <STR_LIT> : <STR_LIT> ) ) . addMBB ( loopMBB ) . addImm ( <STR_LIT> ) . addReg ( <STR_LIT> ) ; BB -> addSuccessor ( loopMBB ) ; BB -> addSuccessor ( exitMBB ) ; BB =


<s> return SelectAddrModeIndexed ( N , <NUM_LIT> , Base


<s> Register PredReg ; if ( getInstrPredicate ( * MI , PredReg ) == <STR_LIT> ) { switch ( Opc ) { default : break ; case <STR_LIT> : if ( ReduceTo2Addr ( MBB , MI , Entry , LiveCPSR , IsSelfLoop ) ) return true ; LLVM_FALLTHROUGH ; case <STR_LIT> : return ReduceToNarrow ( MBB , MI , Entry , LiveCPSR , IsSelfLoop ) ; } } break ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) return ReduceToNarrow ( MBB , MI , Entry , LiveCPSR , IsSelfLoop ) ; break ; case <STR_LIT> : if ( MI -> getOperand ( <NUM_LIT> ) . isImm ( ) ) return ReduceToNarrow ( MBB , MI , Entry , LiveCPSR , IsSelfLoop ) ; break ; case <STR_LIT> : { static const ReduceEntry NarrowEntry = { <STR_LIT> , <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; if ( ReduceToNarrow ( MBB , MI , NarrowEntry , LiveCPSR , IsSelfLoop ) ) return true ; return ReduceToNarrow ( MBB , MI , Entry , LiveCPSR , IsSelfLoop ) ; } case <STR_LIT> : { Register PredReg ; if ( getInstrPredicate ( * MI , PredReg ) != <STR_LIT> ) break ; if ( MI -> getOperand ( <NUM_LIT> ) . isKill ( ) ) return ReduceToNarrow ( MBB , MI , Entry , LiveCPSR , IsSelfLoop ) ; } } return false