<s> setIntDivIsCheap ( false ) ; setShiftAmountType ( <STR_LIT> ) ; setShiftAmountFlavor ( Extend ) ; setStackPointerRegisterToSaveRestore ( <STR_LIT> ) ; setSchedulingPreference ( SchedulingForRegPressure ) ; setBooleanContents ( ZeroOrOneBooleanContent ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; if ( ! Subtarget . isXS1A ( ) ) { setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; } if ( Subtarget . isXS1A ( ) ) { setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; } setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setLoadExtAction ( <STR_LIT> , <STR_LIT> , Promote ) ; setLoadExtAction ( <STR_LIT> , <STR_LIT> , Promote ) ; setLoadExtAction ( <STR_LIT> , <STR_LIT> , Promote ) ; setLoadExtAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setLoadExtAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom


<s> if ( cfun -> machine -> sibcall_blocked ) return false ; if ( TARGET_THUMB1 ) return false ; if ( TARGET_VXWORKS_RTP && flag_pic && decl && ! targetm . binds_local_p ( decl ) ) return false ; if ( TARGET_APCS_FRAME && TARGET_ARM && TARGET_HARD_FLOAT && decl && arm_is_long_call_p ( decl ) ) return false ; if ( TARGET_INTERWORK && decl && TREE_PUBLIC ( decl ) && ! TREE_ASM_WRITTEN ( decl ) ) return false ; func_type = arm_current_func_type ( ) ; if ( IS_INTERRUPT ( func_type ) ) return false ; if ( IS_CMSE_ENTRY ( arm_current_func_type ( ) ) ) return false ; if ( TREE_CODE ( exp ) == CALL_EXPR ) { tree fntype = TREE_TYPE ( TREE_TYPE ( CALL_EXPR_FN ( exp ) ) ) ; if ( lookup_attribute ( <STR_LIT> , TYPE_ATTRIBUTES ( fntype ) ) ) return false ; } if ( ! VOID_TYPE_P ( TREE_TYPE ( DECL_RESULT ( cfun -> decl ) ) ) ) { rtx a , b ; tree decl_or_type = decl ; if ( ! decl ) decl_or_type = TREE_TYPE ( TREE_TYPE ( CALL_EXPR_FN ( exp ) ) ) ; a = arm_function_value ( TREE_TYPE ( exp ) , decl_or_type , false ) ; b = arm_function_value ( TREE_TYPE ( DECL_RESULT ( cfun -> decl ) ) , cfun -> decl , false ) ; if ( ! rtx_equal_p ( a , b ) ) return false ; } if ( IS_STACKALIGN ( func_type ) ) return false ; if ( TARGET_AAPCS_BASED && arm_abi == ARM_ABI_AAPCS && decl && DECL_WEAK ( decl ) )


<s> initialize<ISA_LIT>LowerI1CopiesPass ( * PassRegistry :: getPassRegistry


<s> std :: pair < SDNode * , SDNode * > <ISA_LIT>16DAGToDAGISel :: selectMULT ( SDNode * N , unsigned Opc , SDLoc DL , EVT Ty , bool HasLo , bool HasHi ) { SDNode * Lo = nullptr , * Hi = nullptr ; SDNode * Mul = CurDAG -> getMachineNode ( Opc , DL , <STR_LIT> , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) ) ; SDValue InFlag = SDValue ( Mul


<s> else if ( GET_CODE ( x ) == UNSPEC && XINT ( x , <NUM_LIT> ) == UNSPEC_GOTSYM_OFF ) { assemble_name ( fp , <STR_LIT> ) ; if ( GOT_PCREL ) fputs ( <STR_LIT> , fp ) ; fputs ( <STR_LIT> , fp ) ; output_addr_const ( fp , XVECEXP ( x , <NUM_LIT> , <NUM_LIT> ) ) ; fputc ( ')' , fp ) ; return TRUE ; } else if ( GET_CODE ( x ) == UNSPEC && XINT ( x , <NUM_LIT> )


<s> virtual const char * getPassName ( )


<s> addPass ( create<ISA_LIT>ShrinkInstructionsPass ( ) , false


<s> auto * STy = dyn_cast < StructType > ( Ty ) ; if ( STy ) { unsigned int alignStruct = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> , e = STy -> getNumElements ( ) ; i != e ; i ++ ) { Type * ETy = STy -> getElementType ( i ) ; unsigned int align = getOpenCLAlignment ( DL , ETy ) ; if ( align > alignStruct ) alignStruct = align ; } return alignStruct ; } auto * FTy = dyn_cast < FunctionType > ( Ty ) ; if ( FTy ) return DL . getPointerPrefAlignment ( DL . getProgramAddressSpace ( )


<s> bool <ISA_LIT>CallLowering :: lowerFormalArguments ( MachineIRBuilder & MIRBuilder , const Function & F , ArrayRef < unsigned > VRegs ) const { if ( F . arg_empty ( ) ) return true ; if ( F . isVarArg ( ) ) return false ; MachineFunction & MF = MIRBuilder . getMF ( ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; auto DL = MF . getDataLayout ( ) ; SmallVector < ArgInfo , <NUM_LIT> > SplitArgs ; unsigned Idx = <NUM_LIT> ; for ( auto & Arg : F .


<s> if ( ImplicitSReg != <NUM_LIT> ) MIB . addReg ( ImplicitSReg , RegState :: Implicit ) ; break ; } case <STR_LIT> : { if ( Domain != ExeNEON ) break ; DstReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; SrcReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned DstLane = <NUM_LIT> , SrcLane = <NUM_LIT> , DDst , DSrc ; DDst = getCorrespondingDRegAndLane ( TRI , DstReg , DstLane ) ; DSrc = getCorrespondingDRegAndLane ( TRI , SrcReg , SrcLane ) ; unsigned ImplicitSReg ; if ( ! getImplicitSPRUseForDPRUse ( TRI , MI , DSrc , SrcLane , ImplicitSReg ) ) break ; for ( unsigned i = MI -> getDesc ( ) . getNumOperands ( ) ; i ; -- i ) MI -> RemoveOperand ( i - <NUM_LIT> ) ; if ( DSrc == DDst ) { MI -> setDesc ( get ( <STR_LIT> ) ) ; MIB . addReg ( DDst , RegState :: Define ) . addReg ( DDst , getUndefRegState ( ! MI -> readsRegister ( DDst , TRI ) ) ) . addImm ( SrcLane ) ; AddDefaultPred ( MIB ) ; MIB . addReg ( DstReg , RegState :: Implicit | RegState :: Define ) ; MIB . addReg ( SrcReg , RegState :: Implicit ) ; if ( ImplicitSReg != <NUM_LIT> ) MIB . addReg ( ImplicitSReg , RegState :: Implicit ) ; break ; } MachineInstrBuilder NewMIB ; NewMIB = BuildMI ( * MI -> getParent ( ) , MI , MI -> getDebugLoc ( ) , get ( <STR_LIT> ) , DDst ) ; unsigned CurReg = SrcLane == <NUM_LIT> && DstLane == <NUM_LIT> ? DSrc : DDst ; bool CurUndef = ! MI -> readsRegister ( CurReg , TRI ) ; NewMIB . addReg ( CurReg , getUndefRegState ( CurUndef ) ) ; CurReg = SrcLane == <NUM_LIT> && DstLane == <NUM_LIT> ? DSrc : DDst ; CurUndef = ! MI -> readsRegister ( CurReg , TRI ) ; NewMIB . addReg ( CurReg , getUndefRegState ( CurUndef ) ) ; NewMIB . addImm ( <NUM_LIT> ) ; AddDefaultPred ( NewMIB ) ; if ( SrcLane == DstLane ) NewMIB . addReg ( SrcReg , RegState :: Implicit ) ; MI -> setDesc ( get ( <STR_LIT> ) ) ; MIB . addReg ( DDst , RegState :: Define


<s> grtop = build3 ( COMPONENT_REF , TREE_TYPE ( f_grtop ) , valist , f_grtop , NULL_TREE ) ; vrtop = build3 ( COMPONENT_REF , TREE_TYPE ( f_vrtop ) , valist , f_vrtop , NULL_TREE ) ; groff = build3 ( COMPONENT_REF , TREE_TYPE ( f_groff ) , valist , f_groff , NULL_TREE ) ; vroff = build3 ( COMPONENT_REF , TREE_TYPE ( f_vroff ) , valist , f_vroff , NULL_TREE ) ; t = make_tree ( TREE_TYPE ( stack ) , virtual_incoming_args_rtx ) ; if ( cum -> aapcs_stack_size > <NUM_LIT> ) t = fold_build_pointer_plus_hwi ( t , cum -> aapcs_stack_size * UNITS_PER_WORD ) ; t = build2 ( MODIFY_EXPR , TREE_TYPE ( stack ) , stack , t ) ; expand_expr ( t , const0_rtx , VOIDmode , EXPAND_NORMAL ) ; t = make_tree ( TREE_TYPE ( grtop ) , virtual_incoming_args_rtx ) ; t = build2 ( MODIFY_EXPR , TREE_TYPE ( grtop ) , grtop , t ) ; expand_expr ( t , const0_rtx , VOIDmode , EXPAND_NORMAL ) ; t = make_tree ( TREE_TYPE ( vrtop ) , virtual_incoming_args_rtx ) ; vr_offset = ROUND_UP ( gr_save_area_size , STACK_BOUNDARY / BITS_PER_UNIT ) ; if ( vr_offset ) t = fold_build_pointer_plus_hwi ( t , - vr_offset ) ; t = build2 ( MODIFY_EXPR , TREE_TYPE ( vrtop ) , vrtop , t ) ; expand_expr ( t , const0_rtx , VOIDmode , EXPAND_NORMAL ) ; t = build2 ( MODIFY_EXPR , TREE_TYPE ( groff ) , groff , build_int_cst ( TREE_TYPE (


<s> bool HasStackObject = false ; for ( unsigned i = <NUM_LIT> , e = MFFrame . getObjectIndexEnd ( ) ; i != e ; ++ i ) if ( ! MFFrame . isDeadObjectIndex ( i ) ) { HasStackObject = true ; break ; } if ( HasStackObject || MFFrame . hasCalls ( ) ) StackSize += <STR_LIT> ; StackSize = StackSize > <STR_LIT> ? StackSize - <STR_LIT> : <NUM_LIT> ; MFFrame . setStackSize ( StackSize ) ; if ( StackSize ) { bool StoreBackchain = MF . getFunction ( ) . hasFnAttribute ( <STR_LIT> ) ; if ( StoreBackchain ) BuildMI ( MBB , MBBI , DL , ZII -> get ( <STR_LIT> ) ) . addReg ( <STR_LIT> , RegState :: Define ) . addReg ( <STR_LIT> ) ; int64_t Delta = - int64_t ( StackSize ) ; emitIncrement ( MBB , MBBI , DL , <STR_LIT> , Delta , ZII ) ; unsigned CFIIndex = MF . addFrameInst ( MCCFIInstruction :: createDefCfaOffset ( nullptr , SPOffsetFromCFA + Delta ) ) ; BuildMI ( MBB , MBBI , DL , ZII -> get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; SPOffsetFromCFA += Delta ; if ( StoreBackchain ) BuildMI ( MBB , MBBI , DL , ZII -> get ( <STR_LIT> ) ) . addReg ( <STR_LIT> , RegState :: Kill ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) ; } if ( HasFP ) { BuildMI ( MBB , MBBI , DL , ZII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) ; unsigned HardFP = MRI -> getDwarfRegNum ( <STR_LIT> , true ) ; unsigned CFIIndex = MF . addFrameInst ( MCCFIInstruction :: createDefCfaRegister ( nullptr , HardFP ) ) ; BuildMI ( MBB , MBBI , DL , ZII -> get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; for ( auto I = std :: next ( MF . begin ( ) ) , E = MF . end ( ) ; I != E ; ++ I ) I -> addLiveIn ( <STR_LIT> ) ; } SmallVector < unsigned , <NUM_LIT> > CFIIndexes ; for ( auto & Save : CSI ) { unsigned Reg = Save . getReg ( ) ; if ( <STR_LIT> . contains ( Reg ) ) { if ( MBBI != MBB . end ( ) && ( MBBI -> getOpcode ( ) == <STR_LIT> || MBBI -> getOpcode ( ) == <STR_LIT> ) ) ++ MBBI ; else llvm_unreachable ( <STR_LIT> ) ; } else if ( <STR_LIT> . contains ( Reg ) ) { if ( MBBI != MBB . end ( ) && MBBI -> getOpcode ( ) == <STR_LIT> ) ++ MBBI ; else llvm_unreachable ( <STR_LIT> ) ; } else continue ; unsigned DwarfReg = MRI -> getDwarfRegNum ( Reg , true ) ; unsigned IgnoredFrameReg ; int64_t Offset = getFrameIndexReference ( MF , Save


<s> int uid = INSN_UID ( within ) ; int this_rsrv , side ; int icode ; enum attr_units units ; enum attr_type type ; int j ; if ( ! NONDEBUG_INSN_P ( within ) ) continue ; icode = recog_memoized ( within ) ; if ( icode < <NUM_LIT> ) continue ; if ( INSN_INFO_ENTRY ( uid ) . reservation != <NUM_LIT> ) continue ; units = get_attr_units ( within ) ; type = get_attr_type ( within ) ; this_rsrv = get_reservation_flags ( units ) ; if ( this_rsrv == <NUM_LIT> ) continue ; side = get_insn_side ( within , units ) ; if ( ( type == TYPE_ADDDP || type == TYPE_FP4 ) && units == UNITS_LS ) { int test1_code = ( ( type == TYPE_FP4 ? UNIT_QID_FPL1 : UNIT_QID_ADDDPL1 ) + side * UNIT_QID_SIDE_OFFSET ) ; int test2_code = ( ( type == TYPE_FP4 ? UNIT_QID_FPS1 : UNIT_QID_ADDDPS1 ) + side * UNIT_QID_SIDE_OFFSET ) ; if ( ( sched_mask & ( <NUM_LIT> << test1_code ) ) != <NUM_LIT> ) { this_rsrv = RESERVATION_FLAG_L ; sched_mask &= ~ ( <NUM_LIT> << test1_code ) ; } else if ( ( sched_mask & ( <NUM_LIT> << test2_code ) ) != <NUM_LIT> ) { this_rsrv = RESERVATION_FLAG_S ; sched_mask &= ~ ( <NUM_LIT> << test2_code ) ; } } if ( ( this_rsrv & ( this_rsrv - <NUM_LIT> ) ) == <NUM_LIT> ) { int t = exact_log2 ( this_rsrv ) + side * UNIT_QID_SIDE_OFFSET ; rsrv [ side ] |= this_rsrv ; INSN_INFO_ENTRY ( uid ) . reservation = t ; continue ; } if ( pass == <NUM_LIT> ) { for ( j = <NUM_LIT> ; j < <NUM_LIT> ; j ++ ) if ( this_rsrv & ( <NUM_LIT> << j ) ) rsrv_count [ side ] [ j ] ++ ; continue ; } if ( ( pass == <NUM_LIT> && this_rsrv != RESERVATION_FLAG_DLS ) || ( pass ==


<s> case MachineOperand :: MO_Immediate : MCOp = MCOperand :: CreateImm ( MO . getImm ( ) ) ; break ; case MachineOperand :: MO_MachineBasicBlock : MCOp = MCOperand :: CreateExpr ( MCSymbolRefExpr :: Create ( MO . getMBB ( ) -> getSymbol ( ) , AP . OutContext ) ) ; break ; case MachineOperand :: MO_GlobalAddress : case MachineOperand :: MO_ExternalSymbol : MCOp = GetSymbolRef ( MO , GetSymbolFromOperand ( MO , AP ) , AP , isDarwin ) ; break ; case MachineOperand :: MO_JumpTableIndex : MCOp = GetSymbolRef ( MO , AP . GetJTISymbol ( MO . getIndex ( ) ) , AP , isDarwin ) ; break ; case MachineOperand :: MO_ConstantPoolIndex : MCOp = GetSymbolRef ( MO , AP . GetCPISymbol ( MO . getIndex ( ) ) , AP , isDarwin ) ; break ; case MachineOperand :: MO_BlockAddress : MCOp = GetSymbolRef ( MO , AP . GetBlockAddressSymbol ( MO . getBlockAddress ( )


<s> assert ( Dst && <STR_LIT> ( SDWAOpcode , <STR_LIT> :: sdst ) != - <NUM_LIT> ) ; SDWAInst . add ( * Dst ) ; } else { assert ( <STR_LIT> ( SDWAOpcode , <STR_LIT> :: sdst ) != - <NUM_LIT> ) ; SDWAInst . addReg ( <STR_LIT> , RegState :: Define ) ; } MachineOperand * Src0 = TII -> getNamedOperand ( MI , <STR_LIT> :: src0 ) ; assert ( Src0 && <STR_LIT> ( SDWAOpcode , <STR_LIT> :: src0 ) != - <NUM_LIT> && <STR_LIT> ( SDWAOpcode , <STR_LIT> :: src0_modifiers ) != - <NUM_LIT> ) ; if ( auto * Mod = TII -> getNamedOperand ( MI , <STR_LIT> :: src0_modifiers ) ) SDWAInst . addImm ( Mod -> getImm ( ) ) ; else SDWAInst . addImm ( <NUM_LIT> ) ; SDWAInst . add ( * Src0 ) ; MachineOperand * Src1 = TII -> getNamedOperand ( MI , <STR_LIT> :: src1 ) ; if ( Src1 ) { assert ( <STR_LIT> ( SDWAOpcode , <STR_LIT> :: src1 ) != - <NUM_LIT> && <STR_LIT> ( SDWAOpcode , <STR_LIT> :: src1_modifiers ) != - <NUM_LIT> ) ; if ( auto * Mod = TII -> getNamedOperand ( MI , <STR_LIT> :: src1_modifiers ) ) SDWAInst . addImm ( Mod -> getImm ( ) ) ; else SDWAInst . addImm ( <NUM_LIT> ) ; SDWAInst . add ( * Src1 ) ; } if ( SDWAOpcode == <STR_LIT> || SDWAOpcode == <STR_LIT> ) { MachineOperand * Src2 = TII -> getNamedOperand ( MI , <STR_LIT> :: src2 ) ; assert ( Src2 ) ; SDWAInst . add ( * Src2 ) ; } assert ( <STR_LIT> ( SDWAOpcode , <STR_LIT> :: clamp ) != - <NUM_LIT> ) ; MachineOperand * Clamp = TII -> getNamedOperand ( MI , <STR_LIT> :: clamp ) ; if ( Clamp ) { SDWAInst . add ( * Clamp ) ; } else { SDWAInst . addImm ( <NUM_LIT> ) ; } if ( <STR_LIT> ( SDWAOpcode , <STR_LIT> :: omod ) != - <NUM_LIT> ) { MachineOperand * OMod = TII -> getNamedOperand ( MI , <STR_LIT> :: omod ) ; if ( OMod ) { SDWAInst . add ( * OMod ) ; } else { SDWAInst . addImm ( <NUM_LIT> ) ; } } if ( <STR_LIT> ( SDWAOpcode , <STR_LIT> :: dst_sel ) != - <NUM_LIT>


<s> if ( N -> getOpcode ( ) != <STR_LIT> ) return false ; auto * GA = dyn_cast < GlobalAddressSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ; if ( ! GA ) return false ; Optional < ConstantRange > CR = GA -> getGlobal ( ) -> getAbsoluteSymbolRange


<s> bool getManipulatesSP ( ) const { return ManipulatesSP


<s> Inst . addOperand ( MCOperand :: createImm ( Imm ) ) ; return MCDisassembler ::


<s> bool isAddrMode2 ( ) const { if ( ! isMem ( ) || Memory

. Alignment != <NUM_LIT> ) return false ;


<s> B . setInstrAndDebugLoc ( MI ) ; B . buildInstr ( MatchInfo . Opc , { MI . getOperand ( <NUM_LIT> ) } , { MatchInfo . Val0 , MatchInfo . Val1 , MatchInfo . Val2 } , MI . getFlags ( ) ) ; MI . eraseFromParent (


<s> return ( uint16x4_t ) __builtin_neon_vmaxuv4hi ( ( int16x4_t ) __a , (


<s> bool isLegalSMRDImmOffset ( const MCSubtargetInfo & ST , int64_t ByteOffset ) { int64_t EncodedOffset = getSMRDEncodedOffset ( ST , ByteOffset ) ; return is<ISA_LIT> ( ST ) || isCI ( ST ) ? isUInt


<s> return & InstrInfo . getRegisterInfo (


<s> void <ISA_LIT>TargetWinCOFFStreamer :: EmitARM64WinCFISaveFReg ( unsigned Reg , int Offset ) { assert ( Offset >= <NUM_LIT> && Offset <= <NUM_LIT>


<s> static unsigned getPCRelReloc ( unsigned Kind ) { switch ( Kind ) { case FK_Data_2 : return ELF :: R_390_PC16 ; case FK_Data_4 : return ELF :: R_390_PC32 ; case FK_Data_8 : return ELF :: R_390_PC64 ; case <STR_LIT> : return ELF


<s> unsigned <ISA_LIT>PALMetadata :: getType ( ) const { return


<s> if ( getGeneration ( ) >= <ISA_LIT>Subtarget ::


<s> Definitions . insert ( Definitions . end ( )


<s> static rtx riscv_unspec_offset_high ( rtx temp , rtx addr , enum riscv_symbol_type symbol_type ) { addr = gen_rtx_HIGH ( Pmode , riscv_unspec_address


<s> initialize<ISA_LIT>BranchRelaxationPass ( * PassRegistry ::


<s> bool <ISA_LIT>MCInstrInfo :: prefersSlot3 ( MCInstrInfo const & MCII , MCInst const & MCI ) { const uint64_t F = <ISA_LIT>MCInstrInfo :: getDesc ( MCII , MCI


<s> MachineFunction & MF = MIRBuilder . getMF ( ) ; const TargetFrameLowering * TFL = MF . getSubtarget ( ) . getFrameLowering ( ) ; LLT p0 = LLT :: pointer ( <NUM_LIT> , <NUM_LIT> ) ; LLT s32 = LLT :: scalar ( <NUM_LIT> ) ; unsigned SPReg = MRI . createGenericVirtualRegister ( p0 ) ; MIRBuilder . buildCopy ( SPReg , <STR_LIT> ) ; unsigned OffsetReg = MRI . createGenericVirtualRegister ( s32 ) ; unsigned Offset = VA . getLocMemOffset ( ) ; MIRBuilder . buildConstant ( OffsetReg , Offset ) ; unsigned AddrReg = MRI . createGenericVirtualRegister ( p0 ) ; MIRBuilder . buildGEP ( AddrReg , SPReg , OffsetReg ) ; MachinePointerInfo MPO = MachinePointerInfo :: getStack ( MIRBuilder . getMF ( ) , Offset ) ; unsigned Size = alignTo ( VA . getValVT ( ) . getSizeInBits ( ) , <NUM_LIT> ) / <NUM_LIT> ; unsigned Align = MinAlign ( TFL -> getStackAlignment ( ) , Offset ) ; MMO = MF . getMachineMemOperand ( MPO , MachineMemOperand :: MOStore , Size , Align ) ; return


<s> bool ViableForN [ <NUM_LIT> ] = { true , true , true } ; for ( int i = <NUM_LIT> , e = Mask . size ( ) ; i < e ; ++ i ) { if ( Mask [ i ] < <NUM_LIT> ) continue ; bool IsAnyViable = false ; for ( unsigned j = <NUM_LIT> ; j != array_lengthof ( ViableForN ) ; ++ j ) if ( ViableForN [ j ] ) { uint64_t N = j + <NUM_LIT> ; if ( ( uint64_t ) Mask [ i ] == ( ( ( uint64_t

) i << N ) & ModMask ) ) IsAnyViable = true ;


<s> Instruction * Induction = nullptr ; if ( ! match ( I , m_ICmp ( Pred , m_Instruction ( Induction ) , m_Instruction ( Shuffle ) ) ) || Pred != ICmpInst :: ICMP_ULE || ! L -> isLoopInvariant ( Shuffle ) ) return false ; Instruction * Insert = nullptr ; if ( ! match ( Shuffle , m_ShuffleVector ( m_Instruction ( Insert ) , m_Undef ( ) , m_Zero ( ) ) ) ) return false ; Instruction * BECount = nullptr ; if ( ! match ( Insert , m_InsertElement ( m_Undef ( ) , m_Instruction ( BECount ) , m_Zero ( ) ) ) ) return false ; Value * TripCount = nullptr ; if ( ! match ( BECount , m_Add ( m_Value ( TripCount ) , m_AllOnes ( ) ) ) ) return false ; if ( TripCount != NumElements ) return false ; Instruction * BroadcastSplat = nullptr ; Constant * Const = nullptr ; if ( ! match ( Induction , m_Add ( m_Instruction ( BroadcastSplat ) , m_Constant ( Const ) ) ) ) return false ; if ( auto * CDS = dyn_cast < ConstantDataSequential > ( Const ) ) { for ( unsigned i = <NUM_LIT> ; i < CDS -> getNumElements ( ) ; ++ i ) { if ( CDS -> getElementAsInteger ( i ) != i ) return false ; } } else return false ; if ( ! match ( BroadcastSplat , m_ShuffleVector ( m_Instruction ( Insert ) , m_Undef ( ) , m_Zero ( ) ) ) ) return false ; Instruction * IV


<s> virtual <ISA_LIT>JITInfo * getJITInfo ( ) { return &


<s> unsigned getRegScavengingFI ( ) const { return RegScavengingFI


<s> DEBUG ( errs ( ) << <STR_LIT> ) ; return TargetTransformInfo ( F . getParent (


<s> if ( isLiteralConstantLike ( MI . getOperand ( Src1Idx ) , Desc . OpInfo [ Src1Idx ] ) ) return DescSize + <NUM_LIT> ; int Src2Idx = <STR_LIT> ( Opc , <STR_LIT> :: src2 ) ; if ( Src2Idx == - <NUM_LIT> ) return DescSize ; if ( isLiteralConstantLike ( MI . getOperand ( Src2Idx ) , Desc . OpInfo [ Src2Idx ] ) ) return DescSize + <NUM_LIT> ; return DescSize ; } switch ( Opc ) { case TargetOpcode :: IMPLICIT_DEF : case TargetOpcode :: KILL : case TargetOpcode :: DBG_VALUE : case TargetOpcode :: EH_LABEL : return <NUM_LIT> ; case TargetOpcode :: BUNDLE : return getInstBundleSize ( MI ) ; case TargetOpcode :: INLINEASM : { const MachineFunction * MF = MI . getParent ( ) -> getParent ( ) ; const char * AsmStr = MI . getOperand ( <NUM_LIT> )


<s> code = reverse_condition ( code ) ; std :: swap ( t , f ) ; diff = - diff ; } subtarget = target = dest ; if ( mode != DImode ) { target = gen_lowpart ( DImode , dest ) ; if ( can_create_pseudo_p ( ) ) subtarget = gen_reg_rtx ( DImode ) ; else subtarget = target ; } if ( f == <NUM_LIT> && exact_log2 ( diff ) > <NUM_LIT> && ( diff <= <NUM_LIT> || alpha_tune == PROCESSOR_EV6 ) ) { tmp = gen_rtx_fmt_ee ( code , DImode , cond , const0_rtx ) ; emit_insn ( gen_rtx_SET ( copy_rtx ( subtarget ) , tmp ) ) ; tmp = gen_rtx_ASHIFT ( DImode , copy_rtx ( subtarget ) , GEN_INT ( exact_log2 ( t ) ) ) ; emit_insn ( gen_rtx_SET ( target , tmp ) ) ; } else if ( f == <NUM_LIT> && t == - <NUM_LIT> ) { tmp = gen_rtx_fmt_ee ( code , DImode , cond , const0_rtx ) ; emit_insn ( gen_rtx_SET ( copy_rtx ( subtarget ) , tmp ) ) ; emit_insn ( gen_negdi2 ( target , copy_rtx ( subtarget ) ) ) ; } else if ( diff == <NUM_LIT> || diff == <NUM_LIT> || diff == <NUM_LIT> ) { rtx add_op ; tmp = gen_rtx_fmt_ee ( code , DImode , cond , const0_rtx ) ; emit_insn ( gen_rtx_SET ( copy_rtx ( subtarget ) , tmp ) ) ; if ( diff == <NUM_LIT> ) emit_insn ( gen_adddi3 ( target , copy_rtx ( subtarget ) , GEN_INT ( f ) ) ) ; else { add_op = GEN_INT ( f ) ; if ( sext_add_operand ( add_op , mode ) ) { tmp = gen_rtx_ASHIFT ( DImode , copy_rtx ( subtarget ) , GEN_INT ( exact_log2 ( diff ) ) ) ; tmp = gen_rtx_PLUS ( DImode , tmp , add_op ) ; emit_insn ( gen_rtx_SET ( target , tmp ) ) ; } else return <NUM_LIT> ; } } else return <NUM_LIT>


<s> MachineBasicBlock :: const_instr_iterator I = MI ; MachineBasicBlock :: const_instr_iterator E = MI -> getParent ( ) -> instr_end ( ) ; do { customEmitInstruction ( I


<s> const MachineOperand & MO1 = MI -> getOperand ( OpNum ) ; const MachineOperand & MO2 = MI -> getOperand ( OpNum + <NUM_LIT> ) ; O << <STR_LIT> << TRI -> getAsmName ( MO1 . getReg ( ) ) ; int32_t OffImm = ( int32_t ) MO2 . getImm ( ) / <NUM_LIT> ; if ( OffImm < <NUM_LIT> ) O << <STR_LIT> << - OffImm << <STR_LIT> ; else if ( OffImm > <NUM_LIT> ) O << <STR_LIT>


<s> if ( ! MI -> isDebugInstr ( ) ) LIS -> handleMove ( * MI , true ) ; } if ( ! MI -> isDebugInstr ( ) ) { for ( auto & Op : MI -> operands ( ) ) if ( Op . isReg ( ) && Op . isDef ( ) ) Op . setIsUndef ( false ) ; RegisterOperands RegOpers ; RegOpers . collect ( * MI , * TRI , MRI , true , false ) ; auto SlotIdx = LIS -> getInstructionIndex ( * MI ) . getRegSlot ( ) ; RegOpers . adjustLaneLiveness ( * LIS , MRI , SlotIdx , MI ) ; } Top = std :: next ( MI -> getIterator ( ) ) ; } RegionBegin = getMachineInstr ( Schedule . front ( ) ) ; if ( ! std :: is_same < decltype ( * Schedule . begin ( ) ) , MachineInstr * > :: value ) { placeDebugValues ( ) ; RegionEnd = R . End ; } R . Begin = RegionBegin ; R . MaxPressure = MaxRP ; const auto RegionMaxRP = getRegionPressure ( R ) ; const auto & ST = MF . getSubtarget <


<s> unsigned Opc = MI -> getOpcode ( ) ; if ( ( Opc == <STR_LIT> && MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ) return true ; else if ( ( Opc == <STR_LIT> && MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == MI -> getOperand ( <NUM_LIT>


<s> CallingConv :: ID CC = F . getCallingConv ( ) ; if ( CC == CallingConv :: <ISA_LIT>_KERNEL || CC == CallingConv :: SPIR_KERNEL ) { if ( ! F . arg_empty ( ) ) KernargSegmentPtr = true ; WorkGroupIDX = true ; WorkItemIDX = true ; } else if ( CC == CallingConv :: <ISA_LIT>_PS ) { P<ISA_LIT>nputAddr = <STR_LIT> ( F ) ; } if ( ! isEntryFunction ( ) ) { ScratchRSrcReg = <STR_LIT> ; ScratchWaveOffsetReg = <STR_LIT> ; FrameOffsetReg = <STR_LIT> ; StackPtrOffsetReg = <STR_LIT> ; ArgInfo . PrivateSegmentBuffer = ArgDescriptor :: createRegister ( ScratchRSrcReg ) ; ArgInfo . PrivateSegmentWaveByteOffset = ArgDescriptor :: createRegister ( ScratchWaveOffsetReg ) ; if ( F . hasFnAttribute ( <STR_LIT> ) ) ImplicitArgPtr = true ; } else { if ( F . hasFnAttribute ( <STR_LIT> ) ) { KernargSegmentPtr = true ; MaxKernArgAlign = std :: max ( ST . getAlignmentForImplicitArgPtr ( ) , MaxKernArgAlign ) ; } } if ( F . hasFnAttribute ( <STR_LIT> ) ) WorkGroupIDX = true ; if ( F . hasFnAttribute ( <STR_LIT> ) ) WorkGroupIDY = true ; if ( F . hasFnAttribute ( <STR_LIT> ) ) WorkGroupIDZ = true ; if ( F . hasFnAttribute ( <STR_LIT> ) ) WorkItemIDX = true ; if ( F . hasFnAttribute ( <STR_LIT> ) ) WorkItemIDY = true ; if ( F . hasFnAttribute ( <STR_LIT> ) ) WorkItemIDZ = true ; const MachineFrameInfo & FrameInfo = MF . getFrameInfo ( ) ; bool HasStackObjects = FrameInfo . hasStackObjects ( ) ; if ( isEntryFunction ( ) ) { if ( WorkItemIDZ ) WorkItemIDY = true ; PrivateSegmentWaveByteOffset = true ; if ( ST . getGeneration ( ) >= <ISA_LIT>Subtarget :: GFX9 && ( CC == CallingConv :: <ISA_LIT>_HS || CC == CallingConv :: <ISA_LIT>_GS ) ) ArgInfo . PrivateSegmentWaveByteOffset = ArgDescriptor :: createRegister ( <STR_LIT> ) ; } bool isAmdHsaOrMesa = ST . isAmdHsaOrMesa ( F ) ; if ( isAmdHsaOrMesa ) { PrivateSegmentBuffer = true ; if ( F . hasFnAttribute ( <STR_LIT> ) ) DispatchPtr = true ; if ( F . hasFnAttribute ( <STR_LIT> ) ) QueuePtr = true ; if ( F . hasFnAttribute ( <STR_LIT> ) ) DispatchID = true ; } else if ( ST . isMesaGfxShader ( F ) ) { ImplicitBufferPtr = true ; } if ( F . hasFnAttribute ( <STR_LIT> ) ) KernargSegmentPtr = true ; if ( ST . hasFlatAddressSpace ( ) && isEntryFunction ( ) && isAmdHsaOrMesa ) { auto hasNonSpillStackObjects = [ & ] ( ) { if ( ! HasStackObjects ) return false ; for ( auto OI = FrameInfo . getObjectIndexBegin ( ) , OE = FrameInfo . getObjectIndexEnd ( ) ; OI != OE ; ++ OI ) if ( ! FrameInfo . isSpillSlotObjectIndex ( OI ) ) return true ; return false ; } ; if ( hasNonSpillStackObjects ( ) || F . hasFnAttribute ( <STR_LIT> ) ) FlatScratchInit = true ; } Attribute A = F . getFnAttribute ( <STR_LIT> ) ; StringRef S = A .


<s> <STR_LIT> CC = static_cast < <STR_LIT> > ( Cond . back ( ) . getImm ( ) ) ; Cond . back ( ) = MachineOperand :: CreateImm ( Opposite<ISA_LIT>CC (


<s> MachineRegisterInfo & MRI = MF -> getRegInfo ( ) ; auto * TRI = static_cast < const <ISA_LIT>RegisterInfo * > ( MRI . getTargetRegisterInfo ( ) ) ; unsigned Dst = IsStore ? Reg : ValueReg ; unsigned Src = IsStore ? ValueReg : Reg ; unsigned Opc = ( IsStore ^ TRI -> isVGPR ( MRI , Reg )


<s> static int try_issue_insn ( struct bundle_state * curr_state


<s> bool <ISA_LIT>FrameLowering :: hasReservedCallFrame ( const MachineFunction & MF )


<s> t = make_tree ( ptr_type_node , virtual_incoming_args_rtx ) ; t = fold_build_pointer_plus_hwi ( t , offset ) ; t = build2 ( MODIFY_EXPR , TREE_TYPE ( base_field ) , base_field , t ) ; TREE_SIDE_EFFECTS ( t ) = <NUM_LIT> ; expand_expr ( t , const0_rtx , VOIDmode , EXPAND_NORMAL ) ; t = build_int_cst ( NULL_TREE , NUM_ARGS * UNITS_PER_WORD ) ; t = build2 ( MODIFY_EXPR , TREE_TYPE ( offset_field ) , offset_field , t ) ; TREE_SIDE_EFFECTS ( t


<s> unsigned int shift_cnt = <NUM_LIT> ; FOR_EACH_VEC_ELT ( LOOP_VINFO_LENS ( loop_vinfo ) , num_vectors_m1 , rgc ) if ( rgc -> type ) shift_cnt += num_vectors_m1 + <NUM_LIT> ; add_stmt_cost ( shift_cnt , scalar_stmt , NULL ,


<s> bool Ret = SelectionDAGISel :: runOnMachineFunction ( MF ) ; processFunctionAfterISel ( MF ) ; return Ret


<s> return isUImm < <NUM_LIT> , <NUM_LIT> > (


<s> static void DecodeSymbolicOperandOff ( MCInst & Inst , uint64_t Address , uint64_t Offset , const void * Decoder ) { uint64_t nextAddress = Address


<s> Arg -> replaceAllUsesWith ( AllocA ) ; Value * ArgInParam = new AddrSpaceCastInst ( Arg , PointerType :: get ( StructType , ADDRESS_SPACE_PARAM ) , Arg -> getName ( ) , FirstInst ) ; LoadInst * LI = new LoadInst ( ArgInParam , Arg -> getName ( ) , FirstInst ) ; new StoreInst ( LI , AllocA , FirstInst


<s> static SDValue checkBoolTestSetCCCombine ( SDValue Cmp


<s> bool <ISA_LIT>ompactDAGToDAGISel :: SelectADDRrli ( SDValue Addr , SDValue & R1 , SDValue


<s> static unsigned PrepareCall ( SelectionDAG & DAG , SDValue & Callee , SDValue & InFlag , SDValue & Chain , SDLoc dl , int SPDiff , bool isTailCall , SmallVectorImpl < std :: pair < unsigned , SDValue > > & RegsToPass , SmallVectorImpl < SDValue > & Ops , std :: vector < EVT > & NodeTys , const <ISA_LIT>Subtarget & Subtarget ) { bool is<ISA_LIT>64 = Subtarget . is<ISA_LIT>64 ( ) ; bool isSVR4ABI = Subtarget . isSVR4ABI ( ) ; EVT PtrVT = DAG . getTargetLoweringInfo ( ) . getPointerTy ( ) ; NodeTys . push_back ( <STR_LIT> ) ; NodeTys . push_back ( <STR_LIT> ) ; unsigned CallOpc = <STR_LIT> ; bool needIndirectCall = true ; if ( ! isSVR4ABI || ! is<ISA_LIT>64 ) if ( SDNode * Dest = isBLACompatibleAddress ( Callee , DAG ) ) { Callee = SDValue ( Dest , <NUM_LIT> ) ; needIndirectCall = false ; } if ( GlobalAddressSDNode * G = dyn_cast < GlobalAddressSDNode > ( Callee ) ) { if ( ! DAG . getTarget ( ) . getSubtarget < <ISA_LIT>Subtarget > ( ) . isJITCodeModel ( ) ) { unsigned OpFlags = <NUM_LIT> ; if ( DAG . getTarget ( ) . getRelocationModel ( ) != Reloc :: Static && ( Subtarget . getTargetTriple ( ) . isMacOSX ( ) && Subtarget . getTargetTriple ( ) . isMacOSXVersionLT ( <NUM_LIT> , <NUM_LIT> ) ) && ( G -> getGlobal ( ) -> isDeclaration ( ) || G -> getGlobal ( ) -> isWeakForLinker ( ) ) ) { OpFlags = <STR_LIT> ; } Callee = DAG . getTargetGlobalAddress ( G -> getGlobal ( ) , dl , Callee . getValueType ( ) , <NUM_LIT> , OpFlags ) ; needIndirectCall = false ; } } if ( ExternalSymbolSDNode * S = dyn_cast < ExternalSymbolSDNode > ( Callee ) ) { unsigned char OpFlags = <NUM_LIT> ; if ( DAG . getTarget ( ) . getRelocationModel ( ) != Reloc :: Static && ( Subtarget . getTargetTriple ( ) . isMacOSX ( ) && Subtarget . getTargetTriple ( ) . isMacOSXVersionLT ( <NUM_LIT> , <NUM_LIT> ) ) ) { OpFlags = <STR_LIT> ; } Callee = DAG . getTargetExternalSymbol ( S -> getSymbol ( ) , Callee . getValueType ( ) , OpFlags ) ; needIndirectCall = false ; } if ( needIndirectCall ) { SDValue MTCTROps [ ] = { Chain , Callee , InFlag } ; if ( isSVR4ABI && is<ISA_LIT>64 ) { SDVTList VTs = DAG . getVTList ( <STR_LIT> , <STR_LIT> , <STR_LIT> ) ; SDValue LoadFuncPtr = DAG . getNode ( <STR_LIT> , dl , VTs , makeArrayRef ( MTCTROps , InFlag . getNode ( ) ? <NUM_LIT> : <NUM_LIT> ) ) ; Chain = LoadFuncPtr . getValue ( <NUM_LIT> ) ; InFlag = LoadFuncPtr . getValue ( <NUM_LIT> ) ; SDValue PtrOff = DAG . getIntPtrConstant ( <NUM_LIT> ) ; SDValue AddPtr = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> ,


<s> return <ISA_LIT>SinglePathInfo :: isMaybe ( MF .


<s> static inline __ev64_opaque__ __internal_ev_mwhgsmfan ( __ev64_opaque__ a , __ev64_opaque__ b ) { __ev64_opaque__ t ; t = __ev_mwhsmf ( a , b ) ; return __ev_mwsmian ( t , ( ( __ev64_s32__ )


<s> MVT getScalarShiftAmountTy ( const DataLayout & , EVT )


<s> if ( Subtarget . hasStdExtD ( ) ) return Subtarget . hasCheri ( ) ? CSR_XLEN_CLEN_F64_Interrupt_SaveList : CSR_XLEN_F64_Interrupt_SaveList ; if ( Subtarget . hasStdExtF ( ) ) return Subtarget . hasCheri ( ) ? CSR_XLEN_CLEN_F32_Interrupt_SaveList : CSR_XLEN_F32_Interrupt_SaveList ; return Subtarget . hasCheri ( ) ? CSR_XLEN_CLEN_Interrupt_SaveList : CSR_Interrupt_SaveList ; } switch ( Subtarget . getTargetABI ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : return CSR_ILP32_LP64_SaveList ; case <STR_LIT> : case <STR_LIT> : return


<s> uint64_t encoding = <STR_LIT> ( Val , sizeof ( T ) * <NUM_LIT> ) ; Inst . addOperand ( MCOperand ::


<s> static CodeModel :: Model getEffectiveCodeModel ( Optional < CodeModel :: Model > CM , bool JIT , bool Is64Bit ) { if ( CM )


<s> static MachineInstr * getLoopBreakInstr ( MachineBasicBlock * blk ) { for ( MachineBasicBlock :: iterator iter = blk -> begin ( ) ; ( iter != blk -> end ( ) ) ; ++ iter ) { MachineInstr * instr = & ( * iter ) ; if ( instr -> getOpcode ( ) == AMDGPU :: PREDICATED_BREAK ) { return instr ; } } return


<s> unsigned getCalleeSavedFrameSize ( ) const { return


<s> assert ( ! ( NeedsWinCFI && ( NumPredicateVectors || NumDataVectors ) ) && <STR_LIT> ) ; if ( NumDataVectors ) { emitFrameOffsetAdj ( MBB , MBBI , DL , DestReg , SrcReg , NumDataVectors , <STR_LIT> , TII , Flag , NeedsWinCFI , nullptr ) ; SrcReg = DestReg ; } if ( NumPredicateVectors ) { assert ( DestReg != <STR_LIT> && <STR_LIT> ) ; emitFrameOffsetAdj ( MBB , MBBI , DL , DestReg , SrcReg , NumPredicateVectors , <STR_LIT> , TII , Flag ,


<s> void Thumb2RegisterInfo :: emitLoadConstPool ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator & MBBI , DebugLoc dl , unsigned DestReg , unsigned SubIdx , int Val , <STR_LIT> Pred , unsigned PredReg ) const { MachineFunction & MF = * MBB . getParent (


<s> const SelectionDAGTargetInfo * getSelectionDAGInfo (


<s> SDValue Ops64 [ ] = { Opd0 , CurDAG -> getTargetConstant ( LSB , <STR_LIT> ) , CurDAG -> getTargetConstant ( MSB , <STR_LIT> ) } ; SDNode * BFM = CurDAG -> getMachineNode ( Opc , SDLoc ( N ) , <STR_LIT> , Ops64 ) ; SDValue SubReg = CurDAG -> getTargetConstant ( <STR_LIT> , <STR_LIT> ) ; MachineSDNode * Node = CurDAG -> getMachineNode ( TargetOpcode :: EXTRACT_SUBREG , SDLoc ( N ) , <STR_LIT> , SDValue ( BFM , <NUM_LIT> ) , SubReg ) ; return Node ; } SDValue Ops [ ] = { Opd0 , CurDAG -> getTargetConstant ( LSB , VT ) , CurDAG -> getTargetConstant ( MSB ,


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; int32_t Val = Memory . OffsetImm ? Memory . OffsetImm -> getValue ( ) / <NUM_LIT> : <NUM_LIT> ; <STR_LIT> AddSub = Val < <NUM_LIT> ? <STR_LIT>


<s> bool GCNTTIImpl :: isLegalToVectorizeLoadChain ( unsigned ChainSizeInBytes , Align Alignment , unsigned AddrSpace ) const { return isLegalToVectorizeMemChain ( ChainSizeInBytes , Alignment ,


<s> Register ExtReg = extendRegisterMin32 ( ValVReg , VA ) ; MIRBuilder . buildCopy ( PhysReg ,


<s> SDValue Chain = N -> getOperand ( <NUM_LIT> ) ; SDValue Load = N -> getOperand ( <NUM_LIT> ) ; if ( ! isCalleeLoad ( Load , Chain , HasCallSeq ) ) continue ; MoveBelowOrigChain ( CurDAG , Load , SDValue ( N , <NUM_LIT> ) , Chain ) ; ++ NumLoadMoved ; continue ; } if ( N -> getOpcode ( ) != <STR_LIT> && N -> getOpcode ( ) != <STR_LIT> ) continue ; EVT SrcVT = N -> getOperand ( <NUM_LIT> ) . getValueType ( ) ; EVT DstVT = N -> getValueType ( <NUM_LIT> ) ; if ( SrcVT . isVector ( ) || DstVT . isVector ( ) ) continue ; bool SrcIsSSE = <ISA_LIT>Lowering . isScalarFPTypeInSSEReg ( SrcVT ) ; bool DstIsSSE = <ISA_LIT>Lowering . isScalarFPTypeInSSEReg ( DstVT ) ; if ( SrcIsSSE && DstIsSSE ) continue ; if ( ! SrcIsSSE && !


<s> PrintDebugValueComment ( MI , OS ) ; OutStreamer -> EmitRawText ( StringRef ( OS . str ( ) ) ) ; } return ; } case <STR_LIT> : { MCInst TmpInst ; TmpInst . setOpcode ( <STR_LIT> ) ; TmpInst . addOperand ( MCOperand :: createReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ) ; EmitToStreamer ( * OutStreamer , TmpInst ) ; return ; } case <STR_LIT> : { MCOperand Dest ; MCInstLowering . lowerOperand ( MI -> getOperand ( <NUM_LIT> ) , Dest ) ; MCInst TmpInst ; TmpInst . setOpcode ( <STR_LIT> ) ; TmpInst . addOperand ( Dest ) ; EmitToStreamer ( * OutStreamer , TmpInst ) ; return ; } case <STR_LIT> : { const MachineOperand & MO_Sym = MI -> getOperand ( <NUM_LIT> ) ; MachineOperand MO_TLSDESC_LO12 ( MO_Sym ) , MO_TLSDESC ( MO_Sym ) ; MCOperand Sym , SymTLSDescLo12 , SymTLSDesc ; MO_TLSDESC_LO12 . setTargetFlags ( <STR_LIT> | <STR_LIT> | <STR_LIT> ) ; MO_TLSDESC . setTargetFlags ( <STR_LIT> | <STR_LIT> ) ; MCInstLowering . lowerOperand ( MO_Sym , Sym ) ; MCInstLowering . lowerOperand ( MO_TLSDESC_LO12 , SymTLSDescLo12 ) ; MCInstLowering . lowerOperand ( MO_TLSDESC , SymTLSDesc ) ; MCInst Adrp ; Adrp . setOpcode ( <STR_LIT> ) ; Adrp . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ; Adrp . addOperand ( SymTLSDesc ) ; EmitToStreamer ( * OutStreamer , Adrp ) ; MCInst Ldr ; Ldr . setOpcode ( <STR_LIT> ) ; Ldr . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ; Ldr . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ; Ldr . addOperand ( SymTLSDescLo12 ) ; Ldr . addOperand ( MCOperand :: createImm ( <NUM_LIT> ) ) ; EmitToStreamer ( * OutStreamer , Ldr )


<s> bool <ISA_LIT>Subtarget :: isPositionIndependent ( ) const { return TM .


<s> TD = & Fn . getDataLayout ( ) ; STI = & static_cast < const <ISA_LIT>Subtarget & > ( Fn . getSubtarget ( ) ) ; TII = STI -> getInstrInfo ( ) ; TRI = STI -> getRegisterInfo ( )


<s> Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ; } Parser . Lex ( ) ; const MCExpr * ShiftAmount ; SMLoc Loc = Parser . getTok ( ) . getLoc ( ) ; SMLoc EndLoc ; if ( getParser ( ) . parseExpression ( ShiftAmount , EndLoc ) ) { Error ( Loc , <STR_LIT> ) ; return MatchOperand_ParseFail ; } const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( ShiftAmount ) ; if ( ! CE ) { Error ( Loc , <STR_LIT> ) ; return MatchOperand_ParseFail ; } int Val = CE -> getValue ( ) ; if ( Val < Low || Val > High ) { Error ( Loc


<s> Optional < int > getMaskPos ( unsigned Opc ) { auto PosOpt = <STR_LIT> ( Opc ) ; if ( PosOpt ) return * PosOpt ; if ( isVVPBinaryOp ( Opc ) ) return <NUM_LIT> ; switch ( Opc ) { case <STR_LIT>


<s> const <ISA_LIT>InstrInfo * getInstrInfo (


<s> return ( __m64 ) __builtin_arm_wsrlhi ( ( __v4hi


<s> if ( Expr == nullptr ) Inst . addOperand ( MCOperand :: createImm ( <NUM_LIT> ) ) ; else if ( const MCConstantExpr * ConstExpr = dyn_cast < MCConstantExpr > ( Expr ) ) Inst . addOperand

( MCOperand :: createImm ( static_cast < int32_t > ( ConstExpr -> getValue ( ) ) ) ) ;


<s> if ( ! ( mask & OPTION_MASK_ISA_64BIT ) || TARGET_64BIT ) { ix86_builtins_isa [ ( int ) code ] . isa = mask ; if ( mask & ix86_isa_flags & OPTION_MASK_ISA_AVX512VL ) mask &= ~ OPTION_MASK_ISA_AVX512VL ; mask &= ~ OPTION_MASK_ISA_64BIT ; if ( mask == <NUM_LIT> || ( mask & ix86_isa_flags ) != <NUM_LIT> || ( lang_hooks . builtin_function == lang_hooks . builtin_function_ext_scope ) ) { tree type = ix86_get_builtin_func_type ( tcode ) ; decl = add_builtin_function ( name , type , code , BUILT_IN_MD , NULL , NULL_TREE ) ; ix86_builtins [ ( int ) code ] = decl ; ix86_builtins_isa [ ( int ) code ] . set_and_not_built_p = false ; } else { deferred_isa_values |= mask ; ix86_builtins [ ( int ) code ] =


<s> MachineInstr & MI = * Op . getParent ( ) ; if ( MI . getOpcode ( ) == AMDGPU :: EXP ) return true ; if ( ! MI . getDesc ( ) . mayStore ( ) )


<s> SDValue <ISA_LIT>TargetLowering :: lowerRETURNADDR ( SDValue Op , SelectionDAG & DAG ) const { assert ( ( cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) == <NUM_LIT> ) && <STR_LIT> ) ; MachineFunction & MF = DAG .


<s> if ( ! FnStartLoc . isValid ( ) ) return Error ( L , <STR_LIT> ) ; if ( HandlerDataLoc . isValid ( ) ) return Error ( L , <STR_LIT> ) ; if ( Parser . getTok ( ) . isNot ( AsmToken :: Hash ) && Parser . getTok ( ) . isNot ( AsmToken :: Dollar ) ) { return Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; } Parser . Lex ( ) ; const MCExpr * OffsetExpr ; SMLoc ExLoc = Parser . getTok ( ) . getLoc ( ) ; SMLoc EndLoc ; if ( getParser ( ) . parseExpression ( OffsetExpr , EndLoc ) ) return Error ( ExLoc , <STR_LIT> ) ; const MCConstantExpr * CE = dyn_cast


<s> auto Test = [ = ] ( const <ISA_LIT>Operand & Op ) { return Op . isImmTy ( Type ) ; } ; return getOperandLoc ( Test , Operands


<s> if ( ! llvm :: isStoreCandidate ( * MI ) ) continue ; unsigned NumDefs = MI -> getDesc ( ) . getNumDefs ( ) ; if ( <NUM_LIT> != NumDefs ) continue ; MachineOperand & MO = MI -> getOperand ( <NUM_LIT> ) ; if ( ! MO . isReg ( ) || MO . isImplicit ( ) ) continue ; if ( ! MRI -> hasOneUse ( MO . getReg ( ) ) ) continue ; MachineInstr & UseMI = * MRI -> use_instr_begin ( MO . getReg ( ) ) ; if ( ! <STR_LIT> ( UseMI . getOpcode ( ) ) || &

UseMI != MI -> getNextNode ( ) ) continue ;


<s> bool <ISA_LIT>LegalizerInfo :: legalizeFDIV ( MachineInstr & MI , MachineRegisterInfo & MRI , MachineIRBuilder & B


<s> rtx mmix_get_hard_reg_initial_val ( enum machine_mode mode , int regno ) { return get_hard_reg_initial_val ( mode ,


<s> void override_options ( void ) { if ( TARGET_SEP_DATA && TARGET_ID_SHARED_LIBRARY ) error ( <STR_LIT> ) ; if ( TARGET_SEP_DATA || TARGET_ID_SHARED_LIBRARY ) flag_pic = <NUM_LIT> ; if ( ! TARGET_68020 && ! TARGET_COLDFIRE && ( flag_pic == <NUM_LIT> )


<s> Value * <ISA_LIT>IREmitter :: visitSFENCE ( const SDNode * N ) { llvm_unreachable ( <STR_LIT> )


<s> Mode = <STR_LIT> ; } else if ( isAM4 && Offset == - <NUM_LIT> * ( int ) NumRegs + <NUM_LIT> ) { if ( isThumb2 ) return false ; Mode = <STR_LIT> ; } else if ( isAM4 && Offset == - <NUM_LIT> * ( int ) NumRegs ) { Mode = <STR_LIT> ; } else if ( Offset != <NUM_LIT> ) { if ( NumRegs <= <NUM_LIT> ) return false ; unsigned NewBase ; if ( isi32Load ( Opcode ) ) NewBase = Regs [ NumRegs - <NUM_LIT> ] . first ; else { NewBase = Scratch ; if ( NewBase == <NUM_LIT> ) return false ; } int BaseOpc = ! isThumb2 ? <STR_LIT> : ( ( Base == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ) ; if ( Offset < <NUM_LIT> ) { BaseOpc = ! isThumb2 ? <STR_LIT> : ( ( Base == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ) ; Offset = - Offset ; } int ImmedOffset = isThumb2 ? <STR_LIT> ( Offset ) : <STR_LIT> ( Offset ) ; if ( ImmedOffset == - <NUM_LIT> ) return false ; BuildMI ( MBB , MBBI , dl , TII -> get ( BaseOpc ) , NewBase ) . addReg ( Base , getKillRegState ( BaseKill ) ) . addImm ( Offset ) . addImm ( Pred ) . addReg ( PredReg ) . addReg ( <NUM_LIT> ) ; Base = NewBase ; BaseKill = true ; } bool isDPR = Opcode == <STR_LIT> || Opcode == <STR_LIT> ; bool isDef = isi32Load ( Opcode ) || Opcode == <STR_LIT> || Opcode == <STR_LIT> ; Opcode = getLoadStoreMultipleOpcode ( Opcode ) ; MachineInstrBuilder MIB = ( isAM4 ) ? BuildMI ( MBB , MBBI , dl , TII -> get ( Opcode ) ) . addReg ( Base , getKillRegState ( BaseKill ) ) . addImm ( <STR_LIT> ( Mode ) ) . addImm ( Pred ) . addReg ( PredReg ) : BuildMI ( MBB , MBBI , dl , TII -> get ( Opcode )

) . addReg ( Base , getKillRegState ( BaseKill ) ) . addImm ( <STR_LIT> ( Mode , false , isDPR ? NumRegs << <NUM_LIT> : NumRegs ) ) . addImm ( Pred ) . addReg ( PredReg ) ;


<s> bool hasFP ( const MachineFunction & MF ) const { return


<s> TargetRegistry :: RegisterMCSubtargetInfo ( * T , create<ISA_LIT>MCSubtargetInfo ) ; TargetRegistry :: Register<ISA_LIT>Streamer ( * T , create<ISA_LIT>MCStreamer ) ; TargetRegistry :: RegisterMCInstPrinter ( * T , create<ISA_LIT>MCInstPrinter ) ; TargetRegistry :: RegisterMCInstrAnalysis ( * T , create<ISA_LIT>InstrAnalysis ) ; TargetRegistry :: RegisterMCCodeEmitter ( * T , create<ISA_LIT>MCCodeEmitter ) ; TargetRegistry :: RegisterMCAsmBackend ( * T


<s> const uint32_t * <ISA_LIT>RegisterInfo :: getCallPreservedMask ( CallingConv :: ID CC ) const { if ( CC == CallingConv :: GHC


<s> if ( isTargetELF ( ) && TM . isPositionIndependent ( ) && ! TM .

shouldAssumeDSOLocal ( * GV -> getParent ( ) , GV ) ) return <STR_LIT> ;


<s> addr = XEXP ( XEXP ( addr , <NUM_LIT> ) , <NUM_LIT> ) ; } emit_move_insn ( temp , addr ) ; if ( offset ) temp = gen_rtx_PLUS ( Pmode , temp , offset ) ; x = gen_rtx_MEM ( DImode , temp ) ; } return x


<s> tree fndecl = TREE_OPERAND ( CALL_EXPR_FN ( exp ) , <NUM_LIT> ) ; unsigned fcode = ( unsigned ) DECL_FUNCTION_CODE ( fndecl ) ; unsigned i ; struct builtin_description * d ; if ( fcode < FRV_BUILTIN_FIRST_NONMEDIA && ! TARGET_MEDIA ) { error ( <STR_LIT> ) ; return NULL_RTX ; } switch ( fcode ) { case FRV_BUILTIN_MCOP1 : case FRV_BUILTIN_MCOP2 : case FRV_BUILTIN_MDUNPACKH : case FRV_BUILTIN_MBTOHE : if ( ! TARGET_MEDIA_REV1 ) { error ( <STR_LIT> ) ; return NULL_RTX ; } break ; case FRV_BUILTIN_MQXMACHS : case FRV_BUILTIN_MQXMACXHS : case FRV_BUILTIN_MQMACXHS : case FRV_BUILTIN_MADDACCS : case FRV_BUILTIN_MSUBACCS : case FRV_BUILTIN_MASACCS : case FRV_BUILTIN_MDADDACCS : case FRV_BUILTIN_MDSUBACCS : case FRV_BUILTIN_MDASACCS : case FRV_BUILTIN_MABSHS : case FRV_BUILTIN_MDROTLI : case FRV_BUILTIN_MCPLHI : case FRV_BUILTIN_MCPLI : case FRV_BUILTIN_MDCUTSSI : case FRV_BUILTIN_MQSATHS : case FRV_BUILTIN_MHSETLOS : case FRV_BUILTIN_MHSETLOH : case FRV_BUILTIN_MHSETHIS : case FRV_BUILTIN_MHSETHIH : case FRV_BUILTIN_MHDSETS : case FRV_BUILTIN_MHDSETH : if ( ! TARGET_MEDIA_REV2 ) { error ( <STR_LIT> <STR_LIT> ) ; return NULL_RTX ; } break ; case FRV_BUILTIN_SMASS : case FRV_BUILTIN_SMSSS : case FRV_BUILTIN_SMU : case FRV_BUILTIN_ADDSS : case FRV_BUILTIN_SUBSS : case FRV_BUILTIN_SLASS : case FRV_BUILTIN_SCUTSS : case FRV_BUILTIN_IACCreadll : case FRV_BUILTIN_IACCreadl : case FRV_BUILTIN_IACCsetll : case FRV_BUILTIN_IACCsetl : if ( ! TARGET_FR405_BUILTINS ) { error ( <STR_LIT> <STR_LIT> ) ; return NULL_RTX ; } break ; case FRV_BUILTIN_PREFETCH : if ( ! TARGET_FR500_FR550_BUILTINS ) { error ( <STR_LIT> <STR_LIT> ) ; return NULL_RTX ; } break ; case FRV_BUILTIN_MQLCLRHS : case FRV_BUILTIN_MQLMTHS : case FRV_BUILTIN_MQSLLHI : case FRV_BUILTIN_MQSRAHI : if ( ! TARGET_MEDIA_FR450 ) { error ( <STR_LIT> ) ; return NULL_RTX ; } break ; default : break ; } switch ( fcode ) { case FRV_BUILTIN_MTRAP : return frv_expand_noargs_builtin ( CODE_FOR_mtrap ) ; case FRV_BUILTIN_MCLRACC : return frv_expand_mclracc_builtin ( exp ) ; case FRV_BUILTIN_MCLRACCA : if ( TARGET_ACC_8 ) return frv_expand_noargs_builtin ( CODE_FOR_mclracca8 ) ; else return frv_expand_noargs_builtin ( CODE_FOR_mclracca4 ) ; case FRV_BUILTIN_MRDACC : return frv_expand_mrdacc_builtin ( CODE_FOR_mrdacc , exp ) ; case FRV_BUILTIN_MRDACCG : return frv_expand_mrdacc_builtin ( CODE_FOR_mrdaccg , exp ) ; case FRV_BUILTIN_MWTACC : return frv_expand_mwtacc_builtin ( CODE_FOR_mwtacc , exp ) ; case FRV_BUILTIN_MWTACCG : return frv_expand_mwtacc_builtin ( CODE_FOR_mwtaccg , exp ) ; case FRV_BUILTIN_MDPACKH : return frv_expand_mdpackh_builtin ( exp , target ) ; case FRV_BUILTIN_IACCreadll : { rtx src = frv_read_iacc_argument ( DImode , exp , <NUM_LIT> ) ; if ( target == <NUM_LIT> || ! REG_P ( target ) ) target = gen_reg_rtx ( DImode ) ; frv_split_iacc_move ( target , src ) ; return target ; } case FRV_BUILTIN_IACCreadl : return frv_read_iacc_argument ( SImode , exp , <NUM_LIT> ) ; case FRV_BUILTIN_IACCsetll : { rtx dest = frv_read_iacc_argument ( DImode , exp


<s> assert ( ! Subtarget . has<ISA_LIT>32r6 ( ) && ! Subtarget . has<ISA_LIT>64r6 ( ) ) ; SDValue CondRes = createFPCmp ( DAG , Op . getOperand ( <NUM_LIT> ) ) ; if ( CondRes . getOpcode ( ) != <STR_LIT> ) return Op ; SDValue CCNode = CondRes . getOperand ( <NUM_LIT> ) ; <STR_LIT> CC = ( <STR_LIT> ) cast < ConstantSDNode > ( CCNode ) -> getZExtValue ( ) ; unsigned Opc = invertFPCondCodeUser ( CC ) ? <STR_LIT>


<s> <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; if ( AFI -> getGlobalBaseReg ( ) == <NUM_LIT> ) return false ; const <ISA_LIT>TargetMachine * TM = static_cast < const <ISA_LIT>TargetMachine * > ( & MF . getTarget ( ) ) ; if ( TM -> getRelocationModel ( ) != Reloc :: PIC_ ) return false ; LLVMContext * Context = & MF . getFunction ( ) -> getContext ( ) ; unsigned <ISA_LIT>PCLabelIndex = AFI -> createPICLabelUId ( ) ; unsigned PCAdj = TM -> getSubtarget < <ISA_LIT>Subtarget > ( ) . isThumb ( ) ? <NUM_LIT> : <NUM_LIT> ; <ISA_LIT>ConstantPoolValue * CPV = <ISA_LIT>ConstantPoolSymbol :: Create ( * Context , <STR_LIT>


<s> Modified = true ; break ; } ++ MBBI ; break ; } } } for ( MachineBasicBlock :: iterator MBBI = MBB . begin ( ) , E = MBB . end ( ) ; enableNarrowLdOpt && MBBI != E ; ) { MachineInstr * MI = MBBI ; unsigned Opc = MI -> getOpcode ( ) ; if ( isPromotableZeroStoreOpcode ( Opc ) || ( EnableNarrowLdMerge && isNarrowLoad ( Opc ) ) ) { if ( tryToMergeLdStInst ( MBBI ) ) { Modified = true ; } else ++ MBBI ; } else ++ MBBI ; } for ( MachineBasicBlock :: iterator MBBI = MBB . begin ( ) , E = MBB . end ( ) ; MBBI != E ; ) { MachineInstr * MI = MBBI ; switch ( MI -> getOpcode ( ) ) { default : ++ MBBI ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { if ( tryToPairLdStInst ( MBBI ) ) { Modified = true ; break ; } ++ MBBI ; break ; } } } for ( MachineBasicBlock :: iterator MBBI = MBB . begin ( ) , E = MBB . end ( ) ; MBBI != E ; ) { MachineInstr * MI = MBBI ; unsigned Opc = MI -> getOpcode ( ) ; switch ( Opc ) { default : ++ MBBI ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case


<s> if ( val == <NUM_LIT> || val == <NUM_LIT> || val == <NUM_LIT> ) return <NUM_LIT> ; else return


<s> ArgRegs . push_back ( Arg ) ; ArgVTs . push_back ( ArgVT ) ; ArgFlags . push_back ( Flags ) ; } SmallVector < unsigned , <NUM_LIT> > RegArgs ; unsigned NumBytes ; if ( ! processCallArgs ( Args , ArgRegs , ArgVTs , ArgFlags , RegArgs , CC , NumBytes , IsVarArg ) ) return false ; MachineInstrBuilder MIB ; const GlobalValue * GV = dyn_cast < GlobalValue > ( Callee ) ; if ( ! GV ) { if ( CLI . IsPatchPoint ) MIB = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) ) ; else return false ; } else { MIB = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) ) ; MIB . addGlobalAddress ( GV ) ; } for ( unsigned II = <NUM_LIT> , IE = RegArgs . size ( ) ; II != IE ; ++ II ) MIB . addReg ( RegArgs [ II ] , RegState :: Implicit ) ; MIB . addReg ( <STR_LIT> , RegState :: Implicit ) ; MIB . addRegMask ( TRI . getCallPreservedMask ( CC ) ) ; CLI . Call = MIB ; return finishCall ( RetVT , CLI ,


<s> Imm |= ( Mask [ <NUM_LIT> ] < <NUM_LIT> ? <NUM_LIT> : Mask [ <NUM_LIT> ] ) << <NUM_LIT> ; Imm |= ( Mask [ <NUM_LIT> ] < <NUM_LIT> ? <NUM_LIT> : Mask [ <NUM_LIT> ] ) << <NUM_LIT> ; Imm |= ( Mask [ <NUM_LIT> ] < <NUM_LIT> ? <NUM_LIT> : Mask [ <NUM_LIT>


<s> assert ( MI . getOperand ( OpNo ) . isImm ( ) ) ; unsigned Value = getMachineOpValue ( MI , MI . getOperand ( OpNo ) , Fixups , STI ) ; Value -= Offset ; return


<s> MachineInstr * Def = MRI -> getUniqueVRegDef ( Op . getReg ( ) ) ; if ( ! Def || Def -> getOpcode ( ) != <STR_LIT> || ! Def -> getOperand ( <NUM_LIT> ) . isImm ( ) ) return None ; return Def -> getOperand ( <NUM_LIT> ) . getImm (


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT>


<s> FullFS += FS ; ParseSubtargetFeatures ( GPU , FullFS ) ; if ( ! hasAddr64 ( ) && ! FS . contains ( <STR_LIT> ) ) { FlatForGlobal = true ; } if ( getGeneration ( ) <= <ISA_LIT>Subtarget :: NORTHERN_ISLANDS ) { FP16Denormals = false ; FP32Denormals = false ; FP64Denormals =


<s> tmp = gen_rtx_EXPR_LIST ( VOIDmode , tmp , const0_rtx ) ; tmp = gen_rtx_PARALLEL ( orig_mode , gen_rtvec ( <NUM_LIT> , tmp ) ) ; } return


<s> StringRef ModifierName = Parser . getTok ( ) . getString ( ) ; <ISA_LIT>MCExpr :: VariantKind ModifierKind = <ISA_LIT>MCExpr :: getKindByName ( ModifierName . str ( ) . c_str ( ) ) ; if ( ModifierKind != <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ) { Parser . Lex ( ) ; Parser . Lex ( ) ; } else { return Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; } MCSymbol * Symbol = getContext ( ) . getOrCreateSymbol ( Parser . getTok ( ) . getString ( ) ) ; <ISA_LIT>Streamer . EmitValueForModiferKind ( Symbol , SizeInBytes , L , ModifierKind ) ; return false ; } auto parseOne = [ & ] ( ) -> bool { const MCExpr *


<s> void addCCRAsmRegOperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> &&


<s> bool <ISA_LIT>InstrInfo :: expandPostRAPseudo ( MachineInstr & MI ) const { bool HasAVX = Subtarget . hasAVX ( ) ; MachineInstrBuilder MIB ( * MI . getParent ( ) -> getParent ( ) , MI ) ; switch ( MI . getOpcode ( ) ) { case <STR_LIT> : return Expand2AddrUndef ( MIB , get ( <STR_LIT> ) ) ; case <STR_LIT> : return expandMOV32r1 ( MIB , * this , false ) ; case <STR_LIT> : return expandMOV32r1 ( MIB , * this , true ) ; case <STR_LIT> : case <STR_LIT> : return ExpandMOVImmSExti8 ( MIB ) ; case <STR_LIT> : return Expand2AddrUndef ( MIB , get ( <STR_LIT> ) ) ; case <STR_LIT> : return Expand2AddrUndef ( MIB , get ( <STR_LIT> ) ) ; case <STR_LIT> : return Expand2AddrUndef ( MIB , get ( <STR_LIT> ) ) ; case <STR_LIT> : return Expand2AddrUndef ( MIB , get ( <STR_LIT> ) ) ; case <STR_LIT> : case <STR_LIT> : case


<s> } , { { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } } , { { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } } , { { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } } , } ; unsigned EltIdx = Log2_32 ( SrcEltSize / <NUM_LIT> ) ; unsigned NumEltsIdx = Log2_32 ( NumElts / <NUM_LIT> ) ; unsigned Opc = OpcTable [ EltIdx ] [ NumEltsIdx ] [ PredIdx ] ; if ( ! Opc ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } const RegisterBank & VecRB = * RBI . getRegBank ( SrcReg , MRI , TRI ) ; const TargetRegisterClass * SrcRC = getRegClassForTypeOnBank ( SrcTy , VecRB , RBI , true ) ; if ( ! SrcRC ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } unsigned NotOpc = Pred == ICmpInst :: ICMP_NE ? <STR_LIT> : <NUM_LIT> ; if ( SrcTy . getSizeInBits ( ) == <NUM_LIT> ) NotOpc = NotOpc ? <STR_LIT> : <NUM_LIT> ; if ( SwapOperands ) std :: swap ( SrcReg , Src2Reg ) ; MachineIRBuilder MIB ( I ) ; auto Cmp = MIB . buildInstr ( Opc , { SrcRC } , { SrcReg , Src2Reg } ) ; constrainSelectedInstRegOperands ( * Cmp , TII , TRI , RBI ) ; if ( NotOpc ) { Cmp = MIB . buildInstr ( NotOpc , { DstReg } ,


<s> if ( isGPRAsmReg ( ) && RegIdx . Index ==


<s> int group1_reg_operand ( rtx op , enum machine_mode mode ) { if ( mode != VOIDmode && mode != GET_MODE (


<s> getT2AddrModeImm0_1020s4OpValue ( const MCInst & MI , unsigned OpIdx , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { const MCOperand & MO = MI . getOperand ( OpIdx ) ; const MCOperand & MO1 = MI . getOperand ( OpIdx + <NUM_LIT> ) ; unsigned Reg = CTX . getRegisterInfo ( ) -> getEncodingValue ( MO . getReg


<s> <ISA_LIT>MCExpr :: VariantKind ELFRefKind ; MCSymbolRefExpr :: VariantKind DarwinRefKind ; int64_t Addend ; if ( ! <ISA_LIT>AsmParser :: classifySymbolRef ( getImm ( ) , ELFRefKind , DarwinRefKind , Addend ) ) { return false ; } if ( DarwinRefKind != MCSymbolRefExpr :: VK_None ) return false ; for ( unsigned i = <NUM_LIT> ; i != AllowedModifiers . size ( ) ; ++


<s> static inline unsigned int cr16_ret_register ( void ) { return <NUM_LIT>


<s> int getVarArgsFrameIndex ( ) const { return VarArgsFrameIndex


<s> if ( TID . isConditionalBranch ( ) || QII -> isConditionalTransfer ( MI ) || QII -> isConditionalALU32 ( MI ) || QII -> isConditionalLoad ( MI ) || QII -> isConditionalStore


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) : LLVMTargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL ) , Subtarget ( TT , CPU , FS , * this ) { initAsmInfo (


<s> rtx call , temp ; machine_mode mode ; gcc_assert ( MEM_P ( dest ) ) ; dest = XEXP ( dest , <NUM_LIT> ) ; if ( ! CONSTANT_P ( dest ) && ! REG_P ( dest ) ) dest = force_reg ( Pmode , dest ) ; if ( retval == NULL ) mode = VOIDmode ; else mode = GET_MODE ( retval ) ; call = gen_rtx_CALL ( mode , gen_rtx_MEM ( FUNCTION_MODE , dest ) , counter ) ; if ( retval ) call = gen_rtx_SET ( VOIDmode , retval , call ) ; if ( ! CONSTANT_P ( dest ) ) { temp = gen_reg_rtx ( HImode


<s> if ( MO . getTargetFlags ( ) == <STR_LIT> ) GVSym = P . OutContext . getOrCreateSymbol ( Twine ( <STR_LIT> ) + GVSym -> getName ( ) ) ; else if ( MO . getTargetFlags ( ) == <STR_LIT> ) GVSym = P . OutContext . getOrCreateSymbol ( Twine ( <STR_LIT> ) + GVSym -> getName ( ) ) ; if ( MO . getTargetFlags ( ) == <STR_LIT> || MO . getTargetFlags ( ) == <STR_LIT> ) { MCSymbol * Sym = P . getSymbolWithGlobalValueBase ( GV , <STR_LIT> ) ; MachineModuleInfoImpl :: StubValueTy & StubSym = P . MMI -> getObjFileInfo < MachineModuleInfoMachO > ( ) . getGVStubEntry ( Sym ) ; if ( ! StubSym . getPointer ( ) ) StubSym = MachineModuleInfoImpl :: StubValueTy ( P . getSymbol ( GV ) , ! GV -> hasInternalLinkage ( ) ) ; } if ( GVSym -> getName ( ) [ <NUM_LIT> ] != '$' ) GVSym -> print ( O , P . MAI ) ; else { O << '(' ; GVSym -> print ( O , P . MAI ) ; O << ')' ; } P . printOffset ( MO . getOffset ( ) , O ) ; break ; } } switch ( MO . getTargetFlags ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> return __builtin_ia32_rcpsh_mask ( __C , __B , _mm_setzero_ph ( ) ,


<s> if ( MF -> getFunction ( ) -> getCallingConv ( ) == CallingConv :: CXX_FAST_TLS ) return MF -> getInfo < <ISA_LIT>FunctionInfo


<s> return CONST_INT_P ( operand1 ) && CONST_INT_P ( operand2 ) && ( ( ( INTVAL ( operand1 ) == <NUM_LIT> ) && ( INTVAL ( operand2 ) == <NUM_LIT> ) ) || (

( INTVAL ( operand1 ) == <NUM_LIT> ) && ( INTVAL ( operand2 ) == <NUM_LIT> ) ) ) ;


<s> static inline void invertBccCondition ( MachineInstr * MI ) { assert ( MI -> getOpcode ( ) == <STR_LIT> && <STR_LIT> ) ; <STR_LIT> CC = ( <STR_LIT> ) MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; CC = <STR_LIT> (


<s> MCInstrInfo * X = new MCInstrInfo ( ) ; Init<ISA_LIT>MCInstrInfo ( X ) ; return X


<s> else OutStreamer . EmitRawText ( StringRef ( <STR_LIT> ) ) ; OutStreamer . EmitRawText ( <STR_LIT> + Twine ( CurrentFnSym -> getName ( ) )


<s> bool isIncomingArgumentHandler ( ) const override { return


<s> if ( CallingConv :: SPIR_KERNEL == F -> getCallingConv ( ) ) return true ; return isKernelFunc ( F -> getName ( )


<s> mode = v850_gen_float_compare ( cond , mode , op0 , op1 ) ; cc_reg = gen_rtx_REG ( mode , CC_REGNUM ) ; emit_insn ( gen_rtx_SET ( mode , cc_reg , gen_rtx_REG ( mode , FCC_REGNUM ) ) ) ; return gen_rtx_fmt_ee ( cond , mode


<s> int score = <NUM_LIT> ; switch ( s390_sched_state ) { case <NUM_LIT> : if ( ( mask & S390_SCHED_ATTR_MASK_CRACKED ) != <NUM_LIT> || ( mask & S390_SCHED_ATTR_MASK_EXPANDED ) != <NUM_LIT> ) score += <NUM_LIT> ; if ( ( mask & S390_SCHED_ATTR_MASK_GROUPALONE ) != <NUM_LIT> ) score += <NUM_LIT> ; case <NUM_LIT> : if ( ( mask & S390_SCHED_ATTR_MASK_CRACKED ) == <NUM_LIT> && ( mask & S390_SCHED_ATTR_MASK_EXPANDED ) == <NUM_LIT> && ( mask & S390_SCHED_ATTR_MASK_GROUPALONE ) == <NUM_LIT> ) score += <NUM_LIT> ; if ( ( mask & S390_SCHED_ATTR_MASK_ENDGROUP ) == <NUM_LIT> ) score += <NUM_LIT> ; break ; case <NUM_LIT> : if ( ( mask & S390_SCHED_ATTR_MASK_CRACKED ) == <NUM_LIT> && ( mask & S390_SCHED_ATTR_MASK_EXPANDED ) == <NUM_LIT> && ( mask & S390_SCHED_ATTR_MASK_GROUPALONE ) == <NUM_LIT> ) score += <NUM_LIT> ; if ( ( mask & S390_SCHED_ATTR_MASK_ENDGROUP ) != <NUM_LIT> ) score += <NUM_LIT> ; break ; case S390_SCHED_STATE_NORMAL : if ( ( mask & S390_SCHED_ATTR_MASK_CRACKED ) == <NUM_LIT> && ( mask & S390_SCHED_ATTR_MASK_EXPANDED ) == <NUM_LIT> ) score += <NUM_LIT> ; if ( ( mask & S390_SCHED_ATTR_MASK_GROUPALONE ) != <NUM_LIT> ) score += <NUM_LIT> ; break ; case


<s> if ( TARGET_DEBUG_ARG ) fprintf ( stderr , <STR_LIT> , * cum , GET_MODE_NAME ( mode ) , * pretend_size


<s> bool <ISA_LIT>InstrInfo :: isConstExtended ( MachineInstr * MI ) const { if ( ! Subtarget . hasV4TOps ( ) ) return false ; const uint64_t F = MI -> getDesc ( ) . TSFlags ; unsigned isExtended = ( F >> <STR_LIT> ) & <STR_LIT> ; if ( isExtended ) return true ; unsigned isExtendable = ( F >> <STR_LIT> ) & <STR_LIT> ; if ( ! isExtendable ) return false ; short ExtOpNum = getCExtOpNum ( MI ) ; const MachineOperand & MO = MI -> getOperand ( ExtOpNum ) ; if ( MO . getTargetFlags ( ) && <STR_LIT> ) return true ; if ( MO . isMBB ( ) ) return false ; if ( MO . isGlobal ( ) || MO . isSymbol ( ) ) return true ; assert ( MO . isImm ( ) && <STR_LIT> ) ; int MinValue = getMinValue ( MI ) ; int MaxValue = getMaxValue (


<s> bool <ISA_LIT>Subtarget :: isPC32DBLSymbol ( const GlobalValue * GV , Reloc :: Model RM , CodeModel :: Model CM ) const { if ( GV -> getAlignment ( ) == <NUM_LIT> ) return false ; if ( CM == CodeModel :: Small ) return bindsLocally ( GV , RM ) ; return


<s> int <ISA_LIT>TTIImpl :: getArithmeticInstrCost ( unsigned Opcode , Type * Ty , TTI :: OperandValueKind Op1Info , TTI :: OperandValueKind Op2Info , TTI :: OperandValueProperties Opd1PropInfo , TTI :: OperandValueProperties Opd2PropInfo , ArrayRef < const Value * > Args ) { assert ( TLI -> InstructionOpcodeToISD ( Opcode ) && <STR_LIT> ) ; return BaseT :: getArithmeticInstrCost ( Opcode , Ty ,


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; default : assert ( false && <STR_LIT> ) ; } return dFormOpcode


<s> rtx cmp ; if ( GET_MODE ( * op0 ) == BImode ) { gcc_assert ( ( code == NE || code == EQ ) && * op1 == const0_rtx ) ; cmp = * op0 ; } else if ( TARGET_HPUX && GET_MODE ( * op0 ) == TFmode ) { enum qfcmp_magic { QCMP_INV = <NUM_LIT> , QCMP_UNORD = <NUM_LIT> , QCMP_EQ = <NUM_LIT> , QCMP_LT = <NUM_LIT> , QCMP_GT = <NUM_LIT> } ; int magic ; enum rtx_code ncode ; rtx ret , insns ; gcc_assert ( cmptf_libfunc && GET_MODE ( * op1 ) == TFmode ) ; switch ( code ) { case EQ : magic = QCMP_EQ ; ncode = NE ; break ; case NE : magic = QCMP_EQ ; ncode = EQ ; break ; case UNORDERED : magic = QCMP_UNORD ; ncode = NE ; break ; case ORDERED : magic = QCMP_UNORD ; ncode = EQ ; break ; case LT : magic = QCMP_LT | QCMP_INV ; ncode = NE ; break ; case LE : magic = QCMP_LT | QCMP_EQ | QCMP_INV ; ncode = NE ; break ; case GT : magic = QCMP_GT | QCMP_INV ; ncode = NE ; break ; case GE : magic = QCMP_GT | QCMP_EQ | QCMP_INV ; ncode = NE ; break ; case UNLT : magic = QCMP_LT | QCMP_UNORD ; ncode = NE ; break ; case UNLE : magic = QCMP_LT | QCMP_EQ | QCMP_UNORD ; ncode = NE ; break ; case UNGT : magic = QCMP_GT | QCMP_UNORD ; ncode = NE ; break ; case UNGE : magic = QCMP_GT | QCMP_EQ | QCMP_UNORD ; ncode = NE ; break ; case UNEQ : case LTGT : default : gcc_unreachable ( ) ; } start_sequence ( ) ; ret = emit_library_call_value ( cmptf_libfunc , <NUM_LIT> , LCT_CONST , DImode , <NUM_LIT> , * op0 , TFmode , * op1 , TFmode , GEN_INT ( magic ) , DImode ) ; cmp = gen_reg_rtx ( BImode ) ; emit_insn ( gen_rtx_SET ( cmp , gen_rtx_fmt_ee ( ncode , BImode , ret , const0_rtx


<s> MachineBasicBlock * MBB = LoadInst -> getParent ( ) ; MachineMemOperand * LMMO = * LoadInst -> memoperands_begin ( ) ; MachineMemOperand * SMMO = * StoreInst -> memoperands_begin ( ) ; unsigned Reg1 = MRI -> createVirtualRegister ( TII -> getRegClass ( TII -> get ( NLoadOpcode ) , <NUM_LIT> , TRI , * ( MBB -> getParent ( ) ) ) ) ; MachineInstr * NewLoad = BuildMI ( * MBB , LoadInst , LoadInst -> getDebugLoc ( ) , TII -> get ( NLoadOpcode ) , Reg1 ) . add ( LoadBase ) . addImm ( <NUM_LIT> ) . addReg ( <STR_LIT> ) . addImm ( LoadDisp ) . addReg ( <STR_LIT> ) . addMemOperand ( MBB -> getParent ( ) -> getMachineMemOperand ( LMMO , LMMOffset , Size ) ) ; if ( LoadBase . isReg ( ) ) getBaseOperand ( NewLoad ) . setIsKill ( false ) ; LLVM_DEBUG ( NewLoad -> dump ( ) ) ; MachineInstr * StInst = StoreInst ; auto PrevInstrIt = skipDebugInstructionsBackward ( std :: prev ( MachineBasicBlock :: instr_iterator ( StoreInst ) ) , MBB -> instr_begin ( ) ) ; if ( PrevInstrIt . getNodePtr ( ) == LoadInst ) StInst = LoadInst ; MachineInstr * NewStore = BuildMI ( * MBB , StInst , StInst -> getDebugLoc ( ) , TII -> get ( NStoreOpcode ) ) . add ( StoreBase ) . addImm ( <NUM_LIT> ) . addReg ( <STR_LIT> ) . addImm ( StoreDisp ) .

addReg ( <STR_LIT> ) . addReg ( Reg1 ) . addMemOperand ( MBB -> getParent ( ) -> getMachineMemOperand ( SMMO , SMMOffset , Size ) ) ;


<s> if ( Cmp == APFloat :: cmpGreaterThan ) return SDValue ( ) ; EVT VT = K0 -> getValueType ( <NUM_LIT> ) ; if ( Subtarget -> enableDX10Clamp ( ) ) { if ( K1 -> isExactlyValue ( <NUM_LIT> ) && K0 -> isExactlyValue ( <NUM_LIT> ) ) return DAG . getNode ( <STR_LIT> , SL , VT , Op0 . getOperand ( <NUM_LIT> ) ) ; } if ( VT == <STR_LIT> || ( VT == <STR_LIT> && ! Subtarget -> hasMed3_16 (


<s> OutStreamer . BeginCOFFSymbolDef ( S ) ; OutStreamer . EmitCOFFSymbolStorageClass ( COFF :: IMAGE_SYM_CLASS_STATIC ) ; OutStreamer . EmitCOFFSymbolType ( COFF :: IMAGE_SYM_DTYPE_NULL ) ; OutStreamer . EndCOFFSymbolDef ( ) ; S -> setAbsolute ( ) ; OutStreamer . EmitSymbolAttribute ( S , MCSA_Global ) ; OutStreamer . EmitAssignment ( S , MCConstantExpr :: Create ( int64_t ( <NUM_LIT> ) , MMI


<s> emitRuntimeMDIntValue ( * OutStreamer , RuntimeMD :: KeyMDVersion , RuntimeMD :: MDVersion << <NUM_LIT> | RuntimeMD :: MDRevision , <NUM_LIT> ) ; if ( auto MD = M . getNamedMetadata ( <STR_LIT> ) ) { if ( MD -> getNumOperands ( ) != <NUM_LIT> ) { auto Node = MD -> getOperand ( <NUM_LIT> ) ; if ( Node -> getNumOperands ( ) > <NUM_LIT>


<s> bool <ISA_LIT>TargetLowering :: isCheapAddrSpaceCast ( unsigned SrcAS , unsigned DestAS ) const { if ( SrcAS == AMDGPUA<ISA_LIT> . FLAT_ADDRESS ) return true ; return isNoopAddrSpaceCast ( SrcAS , DestAS


<s> EVT VT ; for ( auto * Use : V . getNode ( ) -> uses ( ) ) if ( auto * MemNode = dyn_cast < MemSDNode > ( Use ) ) if (

MemNode -> getMemoryVT ( ) != VT && VT != EVT ( ) ) return false ;


<s> const int64_t SPOffset = <NUM_LIT> * PVT . getStoreSize ( ) ; unsigned PtrLoadOpc = ( PVT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; unsigned IJmpOpc = ( PVT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; MIB = BuildMI ( * MBB , MI , DL , TII -> get ( PtrLoadOpc ) , FP ) ; for ( unsigned i = <NUM_LIT> ; i < <STR_LIT> ; ++ i ) MIB . addOperand ( MI . getOperand ( i ) ) ; MIB . setMemRefs ( MMOBegin , MMOEnd ) ; MIB = BuildMI ( * MBB , MI , DL , TII -> get ( PtrLoadOpc ) , Tmp ) ; for ( unsigned i = <NUM_LIT> ; i < <STR_LIT> ; ++ i ) { if ( i == <STR_LIT> ) MIB . addDisp ( MI . getOperand ( i ) , LabelOffset ) ; else MIB . addOperand ( MI


<s> break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; } if ( NeedsWinCFI ) { auto SEH = std :: next ( MBBI ) ; if ( <ISA_LIT>InstrInfo :: isSEHInstruction ( * SEH ) ) SEH -> eraseFromParent ( ) ; } TypeSize Scale = TypeSize :: Fixed ( <NUM_LIT> ) ; unsigned Width ; int64_t MinOffset , MaxOffset ; bool Success = static_cast < const <ISA_LIT>InstrInfo * > ( TII ) -> getMemOpInfo ( NewOpc , Scale , Width , MinOffset , MaxOffset ) ; ( void ) Success ; assert ( Success && <STR_LIT> ) ; if ( MBBI -> getOperand ( MBBI -> getNumOperands ( ) - <NUM_LIT> ) . getImm ( ) != <NUM_LIT> || CSStackSizeInc < MinOffset || CSStackSizeInc > MaxOffset ) { emitFrameOffset ( MBB , MBBI , DL , <STR_LIT> , <STR_LIT> , StackOffset :: getFixed ( CSStackSizeInc ) , TII , InProlog ? MachineInstr :: FrameSetup : MachineInstr :: FrameDestroy ) ; return std :: prev ( MBBI ) ; } MachineInstrBuilder MIB = BuildMI ( MBB , MBBI , DL , TII -> get ( NewOpc ) ) ; MIB . addReg ( <STR_LIT> , RegState :: Define ) ; unsigned OpndIdx = <NUM_LIT> ; for ( unsigned OpndEnd = MBBI -> getNumOperands ( ) - <NUM_LIT> ; OpndIdx < OpndEnd ; ++ OpndIdx ) MIB . add ( MBBI -> getOperand ( OpndIdx ) ) ; assert ( MBBI -> getOperand ( OpndIdx ) . getImm ( ) == <NUM_LIT> && <STR_LIT> <STR_LIT> ) ; assert ( MBBI -> getOperand ( OpndIdx - <NUM_LIT> ) . getReg ( ) == <STR_LIT> && <STR_LIT> ) ; assert ( CSStackSizeInc % Scale == <NUM_LIT> ) ; MIB . addImm ( CSStackSizeInc / ( int )


<s> static DecodeStatus DecodeLogicalImmInstruction ( MCInst & Inst , uint32_t insn , uint64_t Addr , const void * Decoder ) { unsigned Rd = fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned Rn = fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned Datasize = fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned imm ; if ( Datasize ) { if ( Inst . getOpcode ( ) == <STR_LIT> ) DecodeGPR64RegisterClass ( Inst , Rd , Addr , Decoder ) ; else DecodeGPR64spRegisterClass ( Inst , Rd , Addr , Decoder ) ; DecodeGPR64RegisterClass ( Inst , Rn , Addr , Decoder ) ; imm = fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) ; if ( ! <STR_LIT> ( imm , <NUM_LIT> ) ) return


<s> SDValue Lo = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , In ) ; static const int Mask [ ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> } ; SDValue Hi = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getVectorShuffle ( <STR_LIT> , DL , In , DAG . getUNDEF ( <STR_LIT>


<s> bool hasFP ( const MachineFunction & MF ) const { return


<s> static bool cr16_class_likely_spilled_p ( reg_class_t rclass ) { if ( ( rclass ) == SHORT_REGS || ( rclass ) == DOUBLE_BASE_REGS || (

rclass ) == LONG_REGS || ( rclass ) == GENERAL_REGS ) return true ;


<s> OutMI . addOperand ( createSub ( MI -> getOperand ( <NUM_LIT> ) . getMBB ( ) , MI -> getOperand

( <NUM_LIT> ) . getMBB ( ) , MCSymbolRefExpr :: VK_<ISA_LIT>_ABS_HI ) ) ;


<s> No<ISA_LIT> = false ; PostRAScheduler = false ; IsR9Reserved = ReserveR9 ; UseMovt = false ; SupportsTailCall = false ; HasFP16 = false ; HasD16 = false ; HasHardwareDivide = false ; HasHardwareDivideIn<ISA_LIT> = false ; HasT2ExtractPack = false ; HasDataBarrier = false ; Pref32BitThumb = false ; AvoidCPSRPartialUpdate = false ; AvoidMOVsShifterOperand = false ; HasRAS = false ; HasMPExtension = false ; HasVirtualization = false ; FPOnlySP = false ; HasPerfMon = false ; HasTrustZone = false ; HasCrypto = false ; HasCRC = false ; HasZeroCycleZeroing =


<s> bool hasSDWAClampVOPC ( ) const { return


<s> if ( DestRC -> getSize ( ) != SrcRC -> getSize ( ) ) report_fatal_error ( <STR_LIT> ) ; unsigned Op ; if ( DestRC == & <STR_LIT> ) { Op = <STR_LIT> ; } else if ( DestRC == & <STR_LIT> ) { Op = <STR_LIT> ; } else if ( DestRC == & <STR_LIT> ) { Op = ( SrcRC == & <STR_LIT> ? <STR_LIT> : <STR_LIT> ) ; } else if ( DestRC == & <STR_LIT> ) { Op = ( SrcRC == & <STR_LIT> ? <STR_LIT> : <STR_LIT> ) ; } else if ( DestRC == & <STR_LIT> ) { Op = ( SrcRC == & <STR_LIT> ? <STR_LIT> : <STR_LIT> ) ; } else if ( DestRC == & <STR_LIT>


<s> const DataLayout & DL = F . getParent ( ) -> getDataLayout ( ) ; uint64_t ExplicitArgBytes = <NUM_LIT> ; MaxAlign = <NUM_LIT> ; for ( const Argument & Arg : F . args ( ) ) { Type * ArgTy = Arg . getType ( ) ; unsigned Align = DL . getABITypeAlignment (


<s> else lo |= cum . num_reg_words ; hi = ( cum . num_args << <NUM_LIT> ) | cum . num_arg_words ; lo = lo | ( ( HOST_WIDE_INT ) cum . num_args << <NUM_LIT> ) | ( ( HOST_WIDE_INT ) cum . num_arg_words << <NUM_LIT> ) ; hi = <NUM_LIT> ; ciw = immed_double_const ( lo , hi , DImode ) ; return gen_rtx_UNSPEC ( DImode , gen_rtvec ( <NUM_LIT> , ciw ) , UNSPEC_UMK_LOAD_CIW ) ; } size = ALPHA_ARG_SIZE ( mode , type , named ) ; num_args = cum . num_reg_words ; if ( cum . force_stack || cum . num_reg_words + size > <NUM_LIT> || targetm . calls . must_pass_in_stack ( mode , type ) ) return NULL_RTX ; else if ( type && TYPE_MODE ( type ) == BLKmode ) { rtx reg1 , reg2 ; reg1 = gen_rtx_REG ( DImode , num_args + <NUM_LIT> ) ; reg1 = gen_rtx_EXPR_LIST ( DImode , reg1 , const0_rtx ) ; if ( size == <NUM_LIT> ) return NULL_RTX ; else if ( size == <NUM_LIT> ) return gen_rtx_PARALLEL ( mode , gen_rtvec ( <NUM_LIT> , reg1 ) ) ; else { reg2 = gen_rtx_REG ( DImode , num_args + <NUM_LIT> ) ; reg2 = gen_rtx_EXPR_LIST ( DImode , reg2


<s> void addMem32Operands ( MCInst & Inst , unsigned N ) const { addMemOperands ( Inst ,


<s> void setShuffleError ( unsigned e ) { s .


<s> return Index < <ISA_LIT>Relocs . size ( ) && ! <ISA_LIT>Relocs [ Index ] . HasMatchingHi && ! isPrecededByMatchingHi ( Asm


<s> if ( ! RHS ) return false ; if ( RHS -> countTrailingOnes ( ) >= ShAmtBits ) return true ; const APInt & LHSKnownZeros = KnownBits -> getKnownZeroes ( MI .

getOperand ( <NUM_LIT> ) . getReg ( ) ) ;


<s> case <STR_LIT> : return LowerEH_SJLJ_LONGJMP ( Op , DAG ) ; case <STR_LIT> : return LowerEH_SJLJ_SETUP_DISPATCH ( Op , DAG ) ; case <STR_LIT> : return LowerINTRINSIC_WO_CHAIN ( Op , DAG , Subtarget ) ; case <STR_LIT> : return ExpandBITCAST ( Op . getNode ( ) , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerShift ( Op . getNode ( ) , DAG , Subtarget ) ; case <STR_LIT> : return LowerREM ( Op . getNode ( ) , DAG ) ; case <STR_LIT> : return LowerREM ( Op . getNode ( ) , DAG ) ; case <STR_LIT> : return LowerShiftLeftParts ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerShiftRightParts ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerCTTZ ( Op . getNode ( ) , DAG , Subtarget ) ; case <STR_LIT> : return LowerCTPOP ( Op . getNode ( ) , DAG , Subtarget ) ; case <STR_LIT> : return LowerVSETCC ( Op , DAG ) ; case <STR_LIT> : return LowerSETCCE ( Op , DAG ) ; case <STR_LIT> : return LowerConstantFP ( Op , DAG , Subtarget ) ; case <STR_LIT> : return LowerBUILD_VECTOR ( Op , DAG , Subtarget ) ; case <STR_LIT> : return LowerVECTOR_SHUFFLE ( Op , DAG ) ; case <STR_LIT> : return LowerINSERT_VECTOR_ELT ( Op , DAG ) ; case <STR_LIT> : return LowerEXTRACT_VECTOR_ELT ( Op , DAG ) ; case <STR_LIT> : return LowerCONCAT_VECTORS ( Op , DAG ) ; case <STR_LIT> : return LowerFLT_ROUNDS_ ( Op , DAG ) ; case <STR_LIT> : return LowerMUL ( Op , DAG ) ; case <STR_LIT> : if ( Subtarget -> isTargetWindows ( ) && ! Op . getValueType ( ) . isVector ( ) ) return LowerDIV_Windows ( Op , DAG , true ) ; return LowerSDIV ( Op , DAG ) ; case <STR_LIT> : if ( Subtarget -> isTargetWindows ( ) && ! Op . getValueType ( ) . isVector ( ) ) return LowerDIV_Windows ( Op , DAG , false ) ; return LowerUDIV ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerADDC_ADDE_SUBC_SUBE ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerXALUO ( Op , DAG ) ; case


<s> MCRegisterInfo * X = new MCRegisterInfo ( ) ; Init<ISA_LIT>MCRegisterInfo ( X ,


<s> ScheduleDAGMILive * DAG = new GCNScheduleDAGMILive ( C , make_unique < GCNMaxOccupancySchedStrategy > ( C ) ) ; DAG -> addMutation ( createLoadClusterDAGMutation ( DAG -> TII , DAG -> TRI ) ) ; DAG -> addMutation ( createStoreClusterDAGMutation ( DAG -> TII , DAG -> TRI


<s> return DAG -> getNode ( <STR_LIT> , dl , VT , Vec


<s> unsigned Opc = MI . getOpcode ( ) ; unsigned PredOpc = HII -> getCondOpcode ( Opc , ! Cond ) ; MachineInstrBuilder MB = BuildMI ( B , Where , DL , HII -> get ( PredOpc ) ) ; unsigned Ox = <NUM_LIT> , NP = MI . getNumOperands ( ) ; while ( Ox < NP ) { MachineOperand & MO = MI . getOperand ( Ox ) ; if ( ! MO . isReg ( ) || ! MO . isDef ( ) ) break ; Ox ++ ; } MB . addReg ( DefOp . getReg ( ) , getRegState ( DefOp ) , DefOp . getSubReg ( ) ) ; MB . addReg ( PredOp . getReg ( ) , PredOp . isUndef ( ) ? RegState :: Undef : <NUM_LIT> ,


<s> return hasTinyEncoding ( ) ? <NUM_LIT> : <NUM_LIT>


<s> case ExtInstSet :: OpenCL_std : return getOpenCL_stdName ( inst ) ; case ExtInstSet :: GLSL_std_450 : return getGLSL_std_450Name ( inst ) ; case ExtInstSet :: SPV_AMD_shader_trinary_minmax : return getSPV_AMD_shader_trinary_minmaxName ( inst )


<s> unsigned BitsSet = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) BitsSet += Writemask & ( <NUM_LIT> << i ) ? <NUM_LIT> : <NUM_LIT> ; const TargetRegisterClass * RC ; switch ( BitsSet ) { default : return ; case <NUM_LIT> : RC = & AMDGPU :: VReg_32RegClass ; break ; case <NUM_LIT> : RC = & AMDGPU :: VReg_64RegClass ; break ; case <NUM_LIT> : RC = &


<s> MIB . buildInstr ( NewOpc , { MI . getOperand ( <NUM_LIT> ) } , { MI . getOperand ( <NUM_LIT> ) , ImmDef } ) ; MI . eraseFromParent ( ) ; return


<s> <ISA_LIT>MCCodeEmitter ( const MCInstrInfo & mcii , const MCSubtargetInfo & sti ,


<s> case <STR_LIT> : return PerformSELECTCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformANDCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformORCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformADDCombine ( N , DAG , DCI ,


<s> LaneBitmask M = AR . Mask & BR . Mask ; return M . any ( ) ? RegisterRef ( AR . Reg , M ) : RegisterRef ( ) ; } RegisterRef NAR = normalizeRef ( AR


<s> MCSection * getSectionForConstant ( const DataLayout & DL , SectionKind Kind , const Constant * C ) const override { return


<s> if ( ! insn_entry [ uid2 ] . is_load || ! insn_entry [ uid2 ] . is_swap ) return false ; rtx body = PATTERN ( def_insn ) ; if ( GET_CODE ( body ) != SET || GET_CODE ( SET_SRC ( body ) ) != VEC_SELECT || GET_CODE ( XEXP ( SET_SRC ( body ) , <NUM_LIT> ) ) != MEM ) return false ; rtx mem = XEXP ( SET_SRC ( body ) , <NUM_LIT> ) ; rtx base_reg = XEXP ( mem , <NUM_LIT> ) ; df_ref base_use ; insn_info = DF_INSN_INFO_GET ( def_insn ) ; FOR_EACH_INSN_INFO_USE ( base_use , insn_info ) { if ( ! rtx_equal_p ( DF_REF_REG ( base_use ) , base_reg ) ) continue ; struct df_link * base_def_link = DF_REF_CHAIN ( base_use ) ; if ( ! base_def_link || base_def_link -> next ) return false ; rtx tocrel_insn = DF_REF_INSN ( base_def_link -> ref ) ; rtx tocrel_body = PATTERN ( tocrel_insn ) ; rtx base , offset ; if ( GET_CODE ( tocrel_body ) != SET ) return false ; rtx tocrel_expr = SET_SRC ( tocrel_body ) ; if ( GET_CODE ( tocrel_expr ) == MEM ) tocrel_expr = XEXP ( tocrel_expr , <NUM_LIT> ) ; if ( ! toc_relative_expr_p ( tocrel_expr , false ) ) return false ; split_const ( XVECEXP ( tocrel_base , <NUM_LIT> , <NUM_LIT> ) , & base , & offset ) ; if ( GET_CODE ( base ) != SYMBOL_REF || ! CONSTANT_POOL_ADDRESS_P ( base ) ) return false ; } } return true


<s> llvm_unreachable ( <STR_LIT> ) ; return


<s> int Src0Idx = <STR_LIT> ( MI . getOpcode ( ) , <STR_LIT> :: src0 ) ; const MachineOperand * Src0 = & MI . getOperand ( Src0Idx ) ; if ( Src0 -> isImm ( ) && ! isInlineConstant ( MI , Src0Idx , * Src0 ) ) return nullptr ; break ; } } const MachineOperand * Dst = getNamedOperand ( MI , <STR_LIT> :: vdst ) ; const MachineOperand * Src0 = getNamedOperand ( MI , <STR_LIT> :: src0 ) ; const MachineOperand * Src1 = getNamedOperand ( MI , <STR_LIT> :: src1 ) ; const MachineOperand * Src2 = getNamedOperand ( MI , <STR_LIT> :: src2 ) ; return BuildMI ( * MBB , MI , MI . getDebugLoc ( ) , get ( IsF16 ? <STR_LIT> : <STR_LIT> ) ) . addOperand ( * Dst ) . addImm ( <NUM_LIT> ) . addOperand ( * Src0 ) . addImm ( <NUM_LIT> ) . addOperand ( * Src1 ) . addImm ( <NUM_LIT> ) . addOperand ( * Src2 ) . addImm (


<s> const AsmToken & Tok = Parser . getTok ( ) ; if ( Tok . isNot ( AsmToken :: Identifier ) ) return MatchOperand_NoMatch ; StringRef Name = Tok . getString ( ) ; size_t Start = <NUM_LIT> , Next = Name . find ( '.' ) ; StringRef Head = Name . slice ( Start , Next ) ; unsigned RegNum = matchRegisterNameAlias ( Head , MatchKind ) ; if ( RegNum ) { if ( Next != StringRef :: npos ) { Kind = Name . slice ( Next , StringRef :: npos ) ; if ( ! isValidVectorKind ( Kind , MatchKind ) ) { TokError ( <STR_LIT> ) ; return MatchOperand_ParseFail ; } } Parser . Lex ( ) ; Reg = RegNum


<s> MCObjectWriter * <ISA_LIT>AsmBackend :: createObjectWriter ( raw_pwrite_stream & OS ) const { return create<ISA_LIT>ELFObjectWriter ( OS


<s> void setBytesToPopOnReturn ( unsigned


<s> static void emit_frame_store ( unsigned int regno , rtx base_reg , HOST_WIDE_INT frame_bias , HOST_WIDE_INT base_ofs ) { rtx reg = gen_rtx_REG ( DImode , regno ) ; emit_frame_store_1 ( reg , base_reg , frame_bias , base_ofs , reg


<s> <ISA_LIT>ImmToReg ( ) : MachineFunctionPass ( ID ) { initialize<ISA_LIT>ImmToRegPass ( * PassRegistry :: getPassRegistry ( ) ) ; registerInstructionsForXform (


<s> MF . getFrameInfo ( ) . setAdjustsStack ( true ) ; const GlobalValue & GV = * I . getOperand ( <NUM_LIT> ) . getGlobal ( ) ; MachineIRBuilder MIB ( I ) ; MIB . buildInstr ( <STR_LIT> , { <STR_LIT> } , { } ) . addGlobalAddress ( & GV , <NUM_LIT> , <STR_LIT> ) ; auto Load = MIB . buildInstr ( <STR_LIT> , { & <STR_LIT> } , { Register ( <STR_LIT> ) }


<s> __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT> ( b ) , <STR_LIT> ( c ) : ) ; return result


<s> SDValue Shift = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , In64 , Shift32 ) ; SDValue Out64 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Shift ) ; return DAG . getTargetExtractSubreg ( <STR_LIT> , DL , <STR_LIT> , Out64 ) ; } if ( InVT == <STR_LIT> && ResVT == <STR_LIT> ) { SDNode * U64 = DAG . getMachineNode ( TargetOpcode :: IMPLICIT_DEF , DL , <STR_LIT> ) ; SDValue In64 = DAG . getTargetInsertSubreg ( <STR_LIT> , DL , <STR_LIT> , SDValue ( U64 , <NUM_LIT> ) , In ) ; SDValue Out64 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , In64 ) ; SDValue Shift = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Out64 , Shift32 ) ; SDValue Out = DAG . getNode ( <STR_LIT> , DL , <STR_LIT>


<s> fputs ( DOUBLE_INT_ASM_OP , file ) ; rs6000_output_function_entry ( file , name ) ; fputs ( <STR_LIT> , file ) ; if ( DOT_SYMBOLS ) { fputs ( <STR_LIT> , file ) ; assemble_name ( file , name ) ; fputs ( <STR_LIT> , file ) ; assemble_name ( file , name ) ; fputs ( <STR_LIT> , file ) ; if ( TREE_PUBLIC ( decl ) && ! DECL_WEAK ( decl ) ) { fputs ( <STR_LIT> , file ) ; assemble_name ( file , name ) ; putc ( '\n' , file ) ; } } else ASM_OUTPUT_TYPE_DIRECTIVE ( file , name , <STR_LIT> ) ; ASM_DECLARE_RESULT ( file , DECL_RESULT ( decl ) ) ; rs6000_output_function_entry ( file , name ) ; fputs ( <STR_LIT> , file ) ; return ; } if ( DEFAULT_ABI == ABI_V4 && ( TARGET_RELOCATABLE || flag_pic > <NUM_LIT> ) && ! TARGET_SECURE_PLT && ( ! constant_pool_empty_p ( ) || crtl -> profile ) && uses_TOC ( ) ) { char buf [ <NUM_LIT> ] ; ( * targetm . asm_out . internal_label ) ( file , <STR_LIT> , rs6000_pic_labelno ) ; fprintf ( file , <STR_LIT> ) ; assemble_name ( file , toc_label_name ) ; need_toc_init = <NUM_LIT> ; putc ( '-' , file ) ; ASM_GENERATE_INTERNAL_LABEL ( buf , <STR_LIT> , rs6000_pic_labelno ) ; assemble_name ( file , buf ) ; putc ( '\n' , file ) ; } ASM_OUTPUT_TYPE_DIRECTIVE ( file , name , <STR_LIT> ) ; ASM_DECLARE_RESULT ( file , DECL_RESULT ( decl ) ) ; if ( TARGET_CMODEL == CMODEL_LARGE && rs6000_global_entry_point_needed_p ( ) ) { char buf [ <NUM_LIT> ] ; ( * targetm . asm_out . internal_label ) ( file , <STR_LIT> , rs6000_pic_labelno ) ; fprintf ( file , <STR_LIT> ) ; ASM_GENERATE_INTERNAL_LABEL ( buf , <STR_LIT> , rs6000_pic_labelno ) ; assemble_name ( file , buf ) ; putc ( '\n' , file ) ; } if ( DEFAULT_ABI == ABI_AIX ) { const char * desc_name , * orig_name ; orig_name = ( * targetm . strip_name_encoding ) ( name ) ; desc_name = orig_name ; while ( * desc_name ==


<s> return new <ISA_LIT>AsmBackend ( T , Triple ( TT )


<s> const MCConstantExpr * MCE = cast < MCConstantExpr > ( getImm ( ) ) ; Inst . addOperand ( MCOperand :: createImm ( MCE -> getValue ( )


<s> } else { assert ( ! AMDGPU :: R600_Reg128RegClass . contains ( DestReg ) && ! AMDGPU :: R600_Reg128RegClass . contains ( SrcReg ) ) ; MachineInstr * NewMI = buildDefaultInstruction ( MBB , MI , AMDGPU :: MOV , DestReg , SrcReg ) ; NewMI -> getOperand ( getOperandIdx ( * NewMI , AMDGPU :: OpName :: src0 ) ) . setIsKill (


<s> } } break ; } int FI = INT_MAX ; if ( Arg . getOpcode ( ) == <STR_LIT> ) { unsigned VR = cast < RegisterSDNode > ( Arg . getOperand ( <NUM_LIT> ) ) -> getReg ( ) ; if ( ! TargetRegisterInfo :: isVirtualRegister ( VR ) ) return false ; MachineInstr * Def = MRI -> getVRegDef ( VR ) ; if ( ! Def ) return false ; if ( ! Flags . isByVal ( ) ) { if ( ! TII -> isLoadFromStackSlot ( Def , FI ) ) return false ; } else { unsigned Opcode = Def -> getOpcode ( ) ; if ( ( Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ) && Def -> getOperand ( <NUM_LIT> ) . isFI ( ) ) { FI = Def -> getOperand ( <NUM_LIT> ) . getIndex ( ) ; Bytes = Flags . getByValSize ( ) ; } else return false ; } } else if ( LoadSDNode * Ld = dyn_cast < LoadSDNode > ( Arg ) ) { if ( Flags . isByVal ( ) ) return false ; SDValue Ptr = Ld -> getBasePtr ( ) ; FrameIndexSDNode * FINode = dyn_cast < FrameIndexSDNode > ( Ptr ) ; if ( ! FINode ) return false ; FI = FINode -> getIndex ( ) ; } else if ( Arg . getOpcode ( ) == <STR_LIT> && Flags


<s> } else if ( <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( Regs . front ( ) . second ) ) { if ( Regs . back ( ) . second == <STR_LIT> ) Kind = k_FPSRegisterListWithVPR ; else Kind = k_SPRRegisterList ; } if ( Kind == k_RegisterList && Regs . back ( ) . second == <STR_LIT> ) Kind = k_RegisterListWithAPSR ; assert ( std :: is_sorted ( Regs . begin ( ) , Regs . end ( ) ) && <STR_LIT> ) ; auto Op = std :: make_unique < <ISA_LIT>Operand > ( Kind ) ; for ( const auto & P : Regs ) Op -> Registers . push_back ( P . second ) ; Op -> StartLoc =


<s> AU . addRequired < MachinePostDominatorTree > ( ) ; AU . addRequired < MachineLoopInfo


<s> void AMDGPUCFGStructurizer :: mergeSerialBlock ( MachineBasicBlock * DstMBB , MachineBasicBlock * SrcMBB ) { DEBUG ( dbgs ( ) << <STR_LIT> << DstMBB -> getNumber ( ) << <STR_LIT> << SrcMBB -> getNumber ( ) << <STR_LIT> ; ) ; DstMBB -> splice ( DstMBB -> end ( ) , SrcMBB , SrcMBB -> begin ( ) , SrcMBB -> end ( ) ) ; DstMBB -> removeSuccessor ( SrcMBB ) ; cloneSuccessorList ( DstMBB , SrcMBB ) ; removeSuccessor ( SrcMBB ) ; MLI -> removeBlock ( SrcMBB ) ; retireBlock ( SrcMBB


<s> if ( TrueMBB == FalseMBB ) return <NUM_LIT> ; MigrateTrue = needMigrateBlock ( TrueMBB ) ; MigrateFalse = needMigrateBlock ( FalseMBB ) ; if ( ! MigrateTrue && ! MigrateFalse ) return <NUM_LIT> ; if ( ! MigrateTrue && TrueMBB && TrueMBB -> pred_size ( ) > <NUM_LIT> ) MigrateTrue = true ; if ( ! MigrateFalse && FalseMBB && FalseMBB -> pred_size ( ) > <NUM_LIT> ) MigrateFalse = true ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; showImproveSimpleJumpintoIf ( HeadMBB , TrueMBB , FalseMBB , LandBlk , <NUM_LIT> ) ; ) ; const TargetRegisterClass * I32RC = TRI -> getCFGStructurizerRegClass ( <STR_LIT> ) ; if ( ! MigrateTrue || ! MigrateFalse ) { return <NUM_LIT> ; } int NumNewBlk = <NUM_LIT> ; bool LandBlkHasOtherPred = ( LandBlk -> pred_size ( ) > <NUM_LIT> ) ; MachineBasicBlock :: iterator I = insertInstrBefore ( LandBlk , <STR_LIT> ) ; if ( LandBlkHasOtherPred ) { report_fatal_error ( <STR_LIT> ) ; Register CmpResReg = HeadMBB -> getParent ( ) -> getRegInfo ( ) . createVirtualRegister ( I32RC ) ; report_fatal_error ( <STR_LIT> ) ; insertCondBranchBefore ( LandBlk , I , <STR_LIT> , CmpResReg , DebugLoc ( ) ) ; } Register InitReg = HeadMBB -> getParent ( ) -> getRegInfo ( ) . createVirtualRegister ( I32RC ) ; insertCondBranchBefore ( LandBlk , I , <STR_LIT> , InitReg , DebugLoc ( ) ) ; if ( MigrateTrue ) { migrateInstruction ( TrueMBB , LandBlk , I ) ; report_fatal_error ( <STR_LIT> ) ; } insertInstrBefore ( I ,


<s> } if ( OpC == <STR_LIT> ) { lowerCRSpilling ( II , FrameIndex ) ; return ; } else if ( OpC == <STR_LIT> ) { lowerCRRestore ( II , FrameIndex ) ; return ; } else if ( OpC == <STR_LIT> ) { lowerCRBitSpilling ( II , FrameIndex ) ; return ; } else if ( OpC == <STR_LIT> ) { lowerCRBitRestore ( II , FrameIndex ) ; return ; } else if ( OpC == <STR_LIT> ) { lowerVRSAVESpilling ( II , FrameIndex ) ; return ; } else if ( OpC == <STR_LIT> ) { lowerVRSAVERestore ( II , FrameIndex ) ; return ; } MI . getOperand ( FIOperandNum ) . ChangeToRegister ( FrameIndex < <NUM_LIT> ? getBaseRegister ( MF ) : getFrameRegister ( MF ) , false ) ; bool noImmForm = ! MI . isInlineAsm ( ) && OpC != TargetOpcode :: STACKMAP && OpC != TargetOpcode :: PATCHPOINT && ! ImmToIdxMap . count ( OpC ) ; int Offset = MFI . getObjectOffset ( FrameIndex ) ; Offset += MI . getOperand ( OffsetOperandNo ) . getImm ( ) ; if ( ! MF . getFunction ( ) -> hasFnAttribute ( Attribute :: Naked ) ) { if ( ! ( hasBasePointer ( MF ) && FrameIndex < <NUM_LIT> ) ) Offset += MFI . getStackSize ( ) ; } assert ( OpC != <STR_LIT> && <STR_LIT> ) ; if ( ! noImmForm && ( ( isInt < <NUM_LIT> > ( Offset ) && ( ( Offset % offsetMinAlign ( MI ) ) == <NUM_LIT> ) ) || OpC == TargetOpcode :: STACKMAP || OpC == TargetOpcode :: PATCHPOINT ) ) { MI . getOperand ( OffsetOperandNo ) . ChangeToImmediate ( Offset ) ; return ; } bool is64Bit = TM . is<ISA_LIT>64 ( ) ; const TargetRegisterClass * G8RC = & <STR_LIT> ; const TargetRegisterClass * GPRC = & <STR_LIT> ; const TargetRegisterClass * RC = is64Bit ? G8RC : GPRC ; unsigned SRegHi = MF . getRegInfo ( ) . createVirtualRegister ( RC ) , SReg = MF . getRegInfo ( ) . createVirtualRegister ( RC ) ; BuildMI ( MBB , II , dl , TII . get ( is64Bit ? <STR_LIT> : <STR_LIT> ) , SRegHi ) . addImm ( Offset >> <NUM_LIT> ) ; BuildMI ( MBB , II , dl , TII . get ( is64Bit ? <STR_LIT> : <STR_LIT> ) , SReg

) . addReg ( SRegHi , RegState :: Kill ) . addImm ( Offset ) ;


<s> void <ISA_LIT>InstrInfo :: AnalyzeCondBr ( const MachineInstr * Inst , unsigned Opc , MachineBasicBlock * & BB , SmallVectorImpl < MachineOperand > & Cond ) const { assert ( getAnalyzableBrOpc ( Opc ) && <STR_LIT> ) ; int NumOp = Inst ->


<s> extern __inline int __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) _mm_cvtsi64_si32 ( __m64 __i ) { return ( ( int )


<s> bool IsVarArg = CLI . IsVarArg ; const Value * Callee = CLI . Callee ; MCSymbol * Symbol = CLI . Symbol ; if ( ! Callee && ! Symbol ) return false ; if ( IsTailCall ) return false ; CodeModel :: Model CM = TM . getCodeModel ( ) ; if ( CM != CodeModel :: Large && ! Subtarget -> useSmallAddressing ( ) ) return false ; if ( CM == CodeModel :: Large && ! Subtarget -> isTargetMachO ( ) ) return false ; if ( IsVarArg ) return false ; const Function * F = dyn_cast_or_null < Function > ( Callee ) ; if ( FuncInfo . MF -> getFunction ( ) . isPagerando ( ) || ( F && F -> isPagerando ( ) ) ) return false ; MVT RetVT ; if ( CLI . RetTy -> isVoidTy ( ) ) RetVT = <STR_LIT> ; else if ( ! isTypeLegal ( CLI . RetTy , RetVT ) ) return false ; for ( auto Flag : CLI . OutFlags ) if ( Flag . isInReg ( ) || Flag . isSRet ( ) || Flag . isNest ( ) || Flag . isByVal ( ) || Flag . isSwiftSelf ( ) || Flag . isSwiftError ( ) ) return false ; SmallVector < MVT , <NUM_LIT> > OutVTs ; OutVTs . reserve ( CLI . OutVals . size ( ) ) ; for ( auto * Val : CLI . OutVals ) { MVT VT ; if ( ! isTypeLegal ( Val -> getType ( ) , VT ) && ! ( VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> ) ) return false ; if ( VT . isVector ( ) || VT . getSizeInBits ( ) > <NUM_LIT> ) return false ; OutVTs . push_back ( VT ) ; } Address Addr ; if ( Callee && ! computeCallAddress ( Callee , Addr ) ) return false ; unsigned NumBytes ; if ( ! processCallArgs ( CLI , OutVTs , NumBytes ) ) return false ; const <ISA_LIT>RegisterInfo * RegInfo = Subtarget -> getRegisterInfo ( ) ; if ( RegInfo -> isAnyArgRegReserved ( * MF ) ) RegInfo -> emitReservedArgRegCallError ( * MF ) ; MachineInstrBuilder MIB ; if ( Subtarget -> useSmallAddressing ( ) ) { const MCInstrDesc & II = TII . get ( Addr . getReg ( ) ? <STR_LIT> : <STR_LIT> ) ; MIB = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , II ) ; if ( Symbol ) MIB . addSym ( Symbol , <NUM_LIT> ) ; else if ( Addr . getGlobalValue ( ) ) MIB . addGlobalAddress (

Addr . getGlobalValue ( ) , <NUM_LIT> , <NUM_LIT> ) ;


<s> unsigned NewVReg2 = MRI -> createVirtualRegister ( TRC ) ; BuildMI ( * MBB , MI , dl , TII -> get ( <STR_LIT> ) , NewVReg2 ) . addReg ( NewVReg1 , RegState :: Kill ) . addImm ( PCLabelId ) ; unsigned NewVReg3 = MRI -> createVirtualRegister ( TRC ) ; AddDefaultPred ( BuildMI ( * MBB , MI , dl , TII -> get ( <STR_LIT> ) , NewVReg3 ) . addReg ( <STR_LIT> , RegState :: Define ) . addImm ( <NUM_LIT> ) ) ; unsigned NewVReg4 = MRI -> createVirtualRegister ( TRC ) ; AddDefaultPred ( BuildMI ( * MBB , MI , dl , TII -> get ( <STR_LIT> ) , NewVReg4 ) . addReg ( <STR_LIT> , RegState :: Define ) . addReg ( NewVReg2 , RegState :: Kill ) . addReg ( NewVReg3 , RegState :: Kill ) ) ; unsigned NewVReg5 = MRI -> createVirtualRegister ( TRC ) ; BuildMI ( * MBB , MI , dl , TII -> get ( <STR_LIT> ) , NewVReg5 ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) ; AddDefaultPred ( BuildMI ( * MBB , MI , dl , TII -> get ( <STR_LIT> ) ) . addReg ( NewVReg4 , RegState :: Kill ) . addReg ( NewVReg5 , RegState :: Kill ) . addImm ( <NUM_LIT> ) . addMemOperand ( FIMMOSt ) ) ; } else { unsigned NewVReg1 = MRI -> createVirtualRegister ( TRC ) ; AddDefaultPred ( BuildMI ( * MBB , MI , dl , TII -> get ( <STR_LIT> ) , NewVReg1 ) . addConstantPoolIndex ( CPI ) . addImm (

<NUM_LIT> ) . addMemOperand ( CPMMO ) ) ;


<s> unsigned Reg = Info . addWorkGroupIDX ( ) ; MF . addLiveIn ( Reg , & <STR_LIT> ) ; CCInfo . AllocateReg ( Reg ) ; } if ( Info . hasWorkGroupIDY ( ) ) { unsigned Reg = Info . addWorkGroupIDY ( ) ; MF . addLiveIn ( Reg , & <STR_LIT> ) ; CCInfo . AllocateReg ( Reg ) ; } if ( Info . hasWorkGroupIDZ ( ) ) { unsigned Reg = Info . addWorkGroupIDZ ( ) ; MF . addLiveIn ( Reg , & <STR_LIT> ) ; CCInfo . AllocateReg ( Reg ) ; } if ( Info . hasWorkGroupInfo ( ) ) { unsigned Reg = Info . addWorkGroupInfo ( ) ; MF . addLiveIn ( Reg , & <STR_LIT> ) ; CCInfo . AllocateReg ( Reg ) ; } if ( Info . hasPrivateSegmentWaveByteOffset ( ) ) { unsigned PrivateSegmentWaveByteOffsetReg ; if (


<s> static Relocator :: DWord helper_thumb32_cond_branch_offset ( Relocator :: DWord pUpper16 , Relocator :: DWord pLower16 ) { uint32_t s = ( pUpper16 & <NUM_LIT> ) >> <NUM_LIT> ; uint32_t j1 = ( pLower16 & <NUM_LIT> ) >> <NUM_LIT> ; uint32_t j2 = ( pLower16 & <NUM_LIT> ) >> <NUM_LIT> ; uint32_t lower = (


<s> if ( ! isSupportedValue ( V ) || ( shouldPromote ( V ) && ! isLegalToPromote ( V ) ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * V << <STR_LIT> ) ; return false ; } WorkList . insert ( V ) ; return true ; } ; while ( ! WorkList . empty ( ) ) { Value * V = WorkList . back ( ) ; WorkList . pop_back ( ) ; if ( CurrentVisited . count ( V ) ) continue ; if ( ! isa < Instruction > ( V ) && ! isSource ( V ) ) continue ; if ( AllVisited . count ( V ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * V << <STR_LIT> ) ; return false ; } CurrentVisited . insert ( V ) ; AllVisited . insert ( V ) ; if ( isSink ( V ) ) Sinks . insert ( cast < Instruction > ( V ) ) ; if ( isSource ( V ) ) Sources . insert ( V ) ; else if ( auto * I = dyn_cast < Instruction > ( V ) ) { for ( auto & U : I -> operands ( ) ) { if ( ! AddLegalInst ( U ) ) return false ; } } if ( isSource ( V ) || shouldPromote ( V ) ) { for ( Use & U : V -> uses ( ) ) { if ( ! AddLegalInst ( U . getUser ( ) ) ) return false ; } } } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; for ( auto * I : CurrentVisited ) I -> dump ( ) ; ) ; unsigned ToPromote = <NUM_LIT> ; for ( auto * V : CurrentVisited ) { if ( Sources . count ( V ) ) continue ; if ( Sinks . count ( cast < Instruction > ( V ) ) ) continue ; ++ ToPromote ; } if ( ToPromote < <NUM_LIT> ) return false ; Promoter -> Mutate ( OrigTy , CurrentVisited , Sources , Sinks ) ; return true


<s> bool mips_split_move_p ( rtx dest , rtx src , enum mips_split_type split_type ) { if ( mips_mult_move_p ( dest , src , split_type ) ) return false ; unsigned int size = GET_MODE_SIZE ( GET_MODE ( dest ) ) ; if ( size == <NUM_LIT> && FP_REG_RTX_P ( src ) && FP_REG_RTX_P ( dest ) ) return false ; if ( size == <NUM_LIT> && ISA_HAS_LDC1_SDC1 ) { if ( FP_REG_RTX_P ( dest ) && MEM_P ( src ) ) return false ; if ( FP_REG_RTX_P ( src ) && MEM_P ( dest ) ) return false ; } if ( MSA_SUPPORTED_MODE_P ( GET_MODE ( dest ) ) ) return mips_split_128bit_move_p ( dest , src ) ; return size > UNITS_PER_WORD


<s> case <STR_LIT> : return LowerUDIVREM ( Op , DAG ) ; case <STR_LIT> : return LowerSDIVREM ( Op , DAG ) ; case <STR_LIT> : return LowerFREM ( Op , DAG ) ; case <STR_LIT> : return LowerFCEIL ( Op , DAG ) ; case <STR_LIT> : return LowerFTRUNC ( Op , DAG ) ; case <STR_LIT> : return LowerFRINT ( Op , DAG ) ; case <STR_LIT> : return LowerFNEARBYINT ( Op , DAG ) ; case <STR_LIT> : return LowerFROUND ( Op , DAG ) ; case <STR_LIT> : return LowerFFLOOR ( Op , DAG ) ; case <STR_LIT> : return LowerFLOG ( Op , DAG , <NUM_LIT> / numbers :: log2ef ) ; case <STR_LIT> : return LowerFLOG ( Op , DAG , numbers :: ln2f / numbers :: ln10f ) ; case <STR_LIT> : return lowerFEXP ( Op , DAG ) ; case <STR_LIT> : return Lower<ISA_LIT>NT_TO_FP ( Op , DAG ) ; case <STR_LIT> : return LowerUINT_TO_FP ( Op , DAG ) ; case <STR_LIT> : return LowerFP_TO_FP16 ( Op , DAG ) ; case <STR_LIT> : return LowerFP_TO_<ISA_LIT>NT ( Op , DAG ) ; case <STR_LIT> : return LowerFP_TO_UINT ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerCTLZ_CTTZ ( Op , DAG ) ; case <STR_LIT> : return LowerDYNAMIC_STACKALLOC ( Op , DAG ) ; } return


<s> enum reg_class alpha_preferred_reload_class ( rtx x , enum reg_class class ) { if ( x == CONST0_RTX ( GET_MODE ( x ) ) ) return class ; if ( GET_CODE ( x ) == CONST_INT || GET_CODE ( x ) == CONST_DOUBLE || GET_CODE ( x ) == CONST_VECTOR ) { if ( class == FLOAT_REGS ) return NO_REGS ; if ( class == ALL_REGS ) return GENERAL_REGS ; return class


<s> MachineBasicBlock :: iterator <ISA_LIT>InstrInfo :: nextNonPseudo ( MachineBasicBlock & MBB , const MachineBasicBlock


<s> const InstrStage * IS = II -> beginStage ( QII -> get ( this -> getOpcode ( ) ) . getSchedClass ( ) ) ; return ( IS ->


<s> static bool xtensa_return_in_msb ( tree


<s> SDValue <ISA_LIT>TargetLowering :: lowerFRAMEADDR ( SDValue Op , SelectionDAG & DAG ) const { assert ( ( cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) ->

getZExtValue ( ) == <NUM_LIT> ) && <STR_LIT> ) ;