<s> Truncated = DAG . getSelect ( DL , VT , NeedAdjust , Adjust , Truncated ) ; } Truncated = DAG . getNode ( <STR_LIT> , DL , VT , Truncated , Src ) ; const fltSemantics & FltSem = DAG . EVTToAPFloatSemantics ( VT ) ; unsigned Precision = APFloat :: semanticsPrecision ( FltSem ) ; APFloat MaxVal = APFloat ( FltSem ) ; MaxVal . convertFromAPInt ( APInt :: getOneBitSet ( Precision , Precision - <NUM_LIT> ) , false , APFloat :: rmNearestTiesToEven ) ; SDValue MaxValNode = DAG . getConstantFP ( MaxVal , DL , VT ) ; SDValue Abs = DAG . getNode ( <STR_LIT> , DL , VT , Src ) ; SDValue Setcc = DAG . getSetCC ( DL , SetccVT , Abs , MaxValNode


<s> __v4si mask = __extension__ ( __v4si ) { ~ <NUM_LIT> , ~ <NUM_LIT> , ~ <NUM_LIT> , ~ <NUM_LIT> } ; return ( __m128i ) __builtin_ia32_gatherdiv4si256 ( src , base ,


<s> case <STR_LIT> : if ( ! Subtarget -> hasAVX ( ) ) return SDValue ( ) ; if ( ! Subtarget -> hasAVX2 ( ) ) { int NumElems = VT . getVectorNumElements ( ) ; SDValue Idx0 = DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ; SDValue Idx1 = DAG . getConstant ( NumElems / <NUM_LIT> , <STR_LIT> ) ; SDValue LHS = Op . getOperand ( <NUM_LIT> ) ; SDValue LHS1 = Extract128BitVector ( LHS , Idx0 , DAG , dl ) ; SDValue LHS2 = Extract128BitVector ( LHS , Idx1 , DAG , dl ) ; MVT EltVT = VT . getVectorElementType ( ) . getSimpleVT ( ) ; EVT NewVT = <STR_LIT> ( EltVT , NumElems / <NUM_LIT> ) ; EVT ExtraEltVT = ExtraVT . getVectorElementType ( ) ; int ExtraNumElems = ExtraVT . getVectorNumElements ( ) ; ExtraVT = EVT :: getVectorVT ( * DAG . getContext ( ) , ExtraEltVT , ExtraNumElems / <NUM_LIT> ) ; SDValue Extra = DAG . getValueType ( ExtraVT ) ; LHS1 = DAG . getNode ( Op . getOpcode ( ) , dl , NewVT , LHS1 , Extra ) ; LHS2 = DAG . getNode ( Op . getOpcode ( ) , dl , NewVT , LHS2 , Extra ) ; return DAG . getNode ( <STR_LIT> , dl , VT , LHS1 , LHS2 ) ; ; } case <STR_LIT> : case <STR_LIT> : { SDValue Tmp1 = getTargetVShiftNode ( <STR_LIT> , dl , VT , Op . getOperand ( <NUM_LIT> ) ,


<s> void ix86_expand_sse2_abs ( rtx target , rtx input ) { machine_mode mode = GET_MODE ( target ) ; rtx tmp0 , tmp1 , x ; switch ( mode ) { case V4SImode : tmp0 = expand_simple_binop ( mode , ASHIFTRT , input , GEN_INT ( GET_MODE_UNIT_BITSIZE ( mode ) - <NUM_LIT> ) , NULL , <NUM_LIT>


<s> bool emit_nop = emit_cbcond_nop ( insn ) ; bool far = false ; const char * rval ; if ( delta < - <NUM_LIT> || delta > <NUM_LIT> ) far = true ; if ( far ) { if ( v9_form ) rval = <STR_LIT> ; else rval = <STR_LIT> ; } else { if ( emit_nop ) rval = <STR_LIT> ; else rval =


<s> unsigned Opc = <NUM_LIT> ; if ( RC == <STR_LIT> ) { Opc = <STR_LIT> ; } else if ( RC == <STR_LIT> ) { Opc = <STR_LIT> ; } else if ( RC == <STR_LIT> ) { Opc = <STR_LIT> ; } else { assert ( <NUM_LIT> && <STR_LIT> ) ; } DebugLoc DL = DebugLoc :: getUnknownLoc ( ) ; MachineInstrBuilder MIB = BuildMI ( MF , DL , get ( Opc ) , DestReg ) ; for ( unsigned i = <NUM_LIT> , e = Addr . size ( ) ; i != e ; ++ i ) MIB . addOperand ( Addr [


<s> } if ( UseI -> isPHI ( ) ) { const MachineBasicBlock * PB = UseI -> getParent ( ) ; const MachineLoop * L = MLI -> getLoopFor ( PB ) ; if ( L && L -> getHeader ( ) == PB ) LoopPhiNum ++ ; } int32_t P = profit ( UseI ) ; if ( P == std :: numeric_limits < int > :: min ( ) ) return false ; TotalP += P ; } } if ( FixedNum > <NUM_LIT> && LoopPhiNum > <NUM_LIT> ) TotalP -= <NUM_LIT>


<s> static int mcore_arg_partial_bytes ( cumulative_args_t cum , const function_arg_info & arg ) { int reg = ROUND_REG ( * get_cumulative_args ( cum )


<s> continue ; } MachineBasicBlock * DestBB = MI -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; int BlockDistance = BlockOffsets [ DestBB -> getNumber ( ) ] - BlockOffsets [ MBB -> getNumber ( ) ] ; int BranchDistance = BlockDistance - MBBStartOffset ; if ( isInRage ( BranchDistance ) ) { continue ; } DEBUG ( dbgs ( ) << <STR_LIT> << DestBB -> getNumber ( ) << <STR_LIT> << BranchDistance << <STR_LIT> ) ; if ( MI -> getOpcode ( ) == <STR_LIT> && std :: next ( MI ) != EE ) { DEBUG ( dbgs ( ) << <STR_LIT> << MBB -> getNumber ( ) << <STR_LIT> ) ; MachineBasicBlock * NewBB = MF -> CreateMachineBasicBlock ( MBB -> getBasicBlock ( ) ) ; MF -> insert ( std :: next ( MBB ) , NewBB ) ; NewBB -> splice ( NewBB -> end ( ) , & * MBB , std :: next ( MI ) , MBB -> end ( ) ) ; for ( MachineBasicBlock * Succ : MBB -> successors ( ) ) { if ( Succ == DestBB ) { continue ; } MBB -> replaceSuccessor ( Succ , NewBB ) ; NewBB -> addSuccessor ( Succ ) ; } measureFunction ( BlockOffsets , & * MBB ) ; ++ NumSplit ; return true ; } MachineInstr & OldBranch = * MI ; DebugLoc dl = OldBranch . getDebugLoc ( ) ; int InstrSizeDiff = - TII -> getInstSizeInBytes ( OldBranch ) ; if ( MI -> getOpcode ( ) == <STR_LIT> ) { MachineBasicBlock * NextMBB = & * std :: next ( MBB ) ; assert ( MBB -> isSuccessor ( NextMBB ) && <STR_LIT> ) ; SmallVector < MachineOperand , <NUM_LIT> > Cond ; Cond . push_back ( MI -> getOperand ( <NUM_LIT> ) ) ; TII -> reverseBranchCondition ( Cond ) ; MI = BuildMI ( * MBB , MI , dl , TII -> get ( <STR_LIT> ) ) . addMBB ( NextMBB


<s> RegisterMCAsmInfoFn Y ( The<ISA_LIT>elTarget , create<ISA_LIT>MCAsmInfo ) ; RegisterMCAsmInfoFn A ( The<ISA_LIT>64Target , create<ISA_LIT>MCAsmInfo ) ; RegisterMCAsmInfoFn B ( The<ISA_LIT>64elTarget , create<ISA_LIT>MCAsmInfo ) ; TargetRegistry :: RegisterMCCodeGenInfo ( The<ISA_LIT>Target , create<ISA_LIT>MCCodeGenInfo ) ; TargetRegistry :: RegisterMCCodeGenInfo ( The<ISA_LIT>elTarget , create<ISA_LIT>MCCodeGenInfo ) ; TargetRegistry :: RegisterMCCodeGenInfo ( The<ISA_LIT>64Target , create<ISA_LIT>MCCodeGenInfo ) ; TargetRegistry :: RegisterMCCodeGenInfo ( The<ISA_LIT>64elTarget , create<ISA_LIT>MCCodeGenInfo ) ; TargetRegistry :: RegisterMCInstrInfo ( The<ISA_LIT>Target , create<ISA_LIT>MCInstrInfo ) ; TargetRegistry :: RegisterMCInstrInfo ( The<ISA_LIT>elTarget , create<ISA_LIT>MCInstrInfo ) ; TargetRegistry :: RegisterMCInstrInfo ( The<ISA_LIT>64Target , create<ISA_LIT>MCInstrInfo ) ; TargetRegistry :: RegisterMCInstrInfo ( The<ISA_LIT>64elTarget , create<ISA_LIT>MCInstrInfo ) ; TargetRegistry :: RegisterMCRegInfo ( The<ISA_LIT>Target , create<ISA_LIT>MCRegisterInfo ) ; TargetRegistry :: RegisterMCRegInfo ( The<ISA_LIT>elTarget , create<ISA_LIT>MCRegisterInfo ) ; TargetRegistry :: RegisterMCRegInfo ( The<ISA_LIT>64Target , create<ISA_LIT>MCRegisterInfo ) ; TargetRegistry :: RegisterMCRegInfo ( The<ISA_LIT>64elTarget , create<ISA_LIT>MCRegisterInfo ) ; TargetRegistry :: RegisterMCCodeEmitter ( The<ISA_LIT>Target , create<ISA_LIT>MCCodeEmitter ) ; TargetRegistry :: RegisterMCCodeEmitter ( The<ISA_LIT>elTarget , create<ISA_LIT>MCCodeEmitter ) ; TargetRegistry :: RegisterMCCodeEmitter ( The<ISA_LIT>64Target , create<ISA_LIT>MCCodeEmitter ) ; TargetRegistry :: RegisterMCCodeEmitter ( The<ISA_LIT>64elTarget , create<ISA_LIT>MCCodeEmitter ) ; TargetRegistry :: RegisterMCObjectStreamer ( The<ISA_LIT>Target , createMCStreamer ) ; TargetRegistry :: RegisterMCObjectStreamer ( The<ISA_LIT>elTarget , createMCStreamer ) ; TargetRegistry :: RegisterMCObjectStreamer ( The<ISA_LIT>64Target , createMCStreamer ) ; TargetRegistry :: RegisterMCObjectStreamer ( The<ISA_LIT>64elTarget , createMCStreamer ) ; TargetRegistry :: RegisterMCAsmBackend ( The<ISA_LIT>Target , create<ISA_LIT>AsmBackend ) ; TargetRegistry :: RegisterMCAsmBackend ( The<ISA_LIT>elTarget , create<ISA_LIT>AsmBackend ) ; TargetRegistry :: RegisterMCAsmBackend ( The<ISA_LIT>64Target


<s> GlobalAddressSDNode * G = dyn_cast < GlobalAddressSDNode > ( SDValue ( N , <NUM_LIT> ) ) ; DebugLoc dl = G -> getDebugLoc ( ) ; SDValue TGA = DAG . getTargetGlobalAddress ( G -> getGlobal ( )


<s> unsigned DstReg = I -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned SrcReg = I -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned N = I -> getOperand ( <NUM_LIT> ) . getImm ( ) ; const MCInstrDesc & Mfc1Tdd = TII -> get ( <STR_LIT> ) ; DebugLoc dl = I -> getDebugLoc (


<s> MachineBasicBlock * JoinMBB = splitBlockAfter ( MI , MBB ) ; MachineBasicBlock * FalseMBB = emitBlockAfter ( StartMBB ) ; MBB = StartMBB ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) ) . addImm ( CCValid ) . addImm ( CCMask ) . addMBB ( JoinMBB ) ; MBB -> addSuccessor ( JoinMBB ) ; MBB -> addSuccessor ( FalseMBB ) ; MBB = FalseMBB ; MBB -> addSuccessor ( JoinMBB ) ; MBB = JoinMBB ; BuildMI ( * MBB , MBB -> begin ( ) , DL , TII -> get ( <STR_LIT> ) , DestReg ) . addReg ( TrueReg ) . addMBB ( StartMBB ) . addReg ( FalseReg ) . addMBB ( FalseMBB ) ; MI -> eraseFromParent (


<s> TII = mf . getSubtarget ( ) . getInstrInfo ( ) ; for ( MachineBasicBlock & MBB : mf ) if ( processMachineBasicBlock ( & MBB ) ) Changed = true ; return


<s> for ( unsigned i = memOpsEnd , e = memOps . size ( ) ; i != e ; ++ i ) { if ( memOps [ i ] . Position < insertPos && memOps [ i ] . isKill ) { unsigned Reg = memOps [ i ] . Reg ; KilledRegs . insert ( Reg ) ; Killer [ Reg ] = i ; } } SmallVector < std :: pair < unsigned , bool > , <NUM_LIT> > Regs ; for ( unsigned i = memOpsBegin ; i < memOpsEnd ; ++ i ) { unsigned Reg = memOps [ i ] . Reg ; if ( UnavailRegs . count ( Reg ) ) return ; bool isKill = memOps [ i ] . isKill || KilledRegs . count ( Reg ) ; Regs . push_back ( std :: make_pair ( Reg , isKill ) ) ; } MachineBasicBlock :: iterator Loc = memOps [ insertAfter ] . MBBI ; ++ Loc ; if ( ! MergeOps ( MBB , Loc , Offset , Base , BaseKill , Opcode , Pred , PredReg , Scratch , dl , Regs ) ) return ; Merges . push_back ( prior ( Loc ) ) ; for ( unsigned i = memOpsBegin ; i < memOpsEnd ; ++ i ) { if ( Regs [ i - memOpsBegin ] . second ) { unsigned Reg = Regs [ i - memOpsBegin ] . first ; if ( KilledRegs . count ( Reg ) ) { unsigned j = Killer [ Reg ] ; memOps [ j ] . MBBI -> getOperand ( <NUM_LIT> ) . setIsKill ( false ) ; memOps [ j ] . isKill = false ; } } MBB . erase ( memOps [ i ]


<s> return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; } return <NUM_LIT>


<s> unsigned VaListSize = ( Subtarget -> isTargetDarwin ( ) || Subtarget -> isTargetWindows ( ) ) ? PtrSize : <NUM_LIT> ; const Value * DestSV = cast < SrcValueSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getValue ( ) ; const Value * SrcSV = cast < SrcValueSDNode > ( Op . getOperand ( <NUM_LIT> ) ) ->


<s> int GCNTTIImpl :: get64BitInstrCost ( TTI :: TargetCostKind CostKind )


<s> while ( II != E && II -> isInsideBundle ( ) ) { Idx = II -> findRegisterUseOperandIdx ( Reg , false , TRI ) ; if ( Idx != - <NUM_LIT> ) break ; if ( II -> getOpcode ( ) != <STR_LIT> ) ++ Dist ; ++ II ; } if ( Idx == - <NUM_LIT> ) { Dist = <NUM_LIT> ; return nullptr ; } UseIdx = Idx ; return &


<s> return Opc == <STR_LIT> || isT2i32Load (


<s> llvm_unreachable ( <STR_LIT> ) ; case FK_Data_1 : return ELF :: R_<ISA_LIT>ARC_DI<ISA_LIT>8 ; case FK_Data_2 : return ELF :: R_<ISA_LIT>ARC_DI<ISA_LIT>16 ; case FK_Data_4 : return ELF :: R_<ISA_LIT>ARC_DI<ISA_LIT>32 ; case FK_Data_8 : return ELF :: R_<ISA_LIT>ARC_DI<ISA_LIT>64 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>ARC_WDI<ISA_LIT>30 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>ARC_WDI<ISA_LIT>22 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>ARC_WDI<ISA_LIT>19 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>ARC_PC22 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>ARC_PC10 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>ARC_WPLT30 ; } } switch ( Fixup . getTargetKind ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case FK_Data_1 : return ELF :: R_<ISA_LIT>ARC_8 ; case FK_Data_2 : return ( ( Fixup . getOffset ( ) % <NUM_LIT> ) ? ELF :: R_<ISA_LIT>ARC_UA16 : ELF :: R_<ISA_LIT>ARC_16 ) ; case FK_Data_4 : return ( ( Fixup . getOffset ( ) % <NUM_LIT> ) ? ELF :: R_<ISA_LIT>ARC_UA32 : ELF :: R_<ISA_LIT>ARC_32 ) ; case FK_Data_8 : return ( ( Fixup . getOffset ( ) % <NUM_LIT> ) ? ELF :: R_<ISA_LIT>ARC_UA64 : ELF :: R_<ISA_LIT>ARC_64 ) ; case <STR_LIT> : return ELF :: R_<ISA_LIT>ARC_13 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>ARC_HI22 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>ARC_LO10 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>ARC_H44 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>ARC_M44 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>ARC_L44 ; case <STR_LIT> : return


<s> static unsigned <ISA_LIT>16WhichOp8uOr16simm ( unsigned shortOp , unsigned longOp , int64_t Imm ) { if ( isUInt < <NUM_LIT> > ( Imm


<s> for ( auto & I : <ISA_LIT>MCInstrInfo :: bundleInstructions ( Inst ) ) { MCInst & CrntHMI = const_cast < MCInst & > ( * I . getInst ( ) ) ; if ( * RelaxTarget == & CrntHMI ) { Update = true ; assert ( ( <ISA_LIT>MCInstrInfo :: bundleSize ( Res ) < HEXAGON_PACKET_SIZE ) && <STR_LIT> ) ; MCInst * HMIx =


<s> O << TAI -> getLCOMMDirective ( ) << name << ',' << Size << ',' << Align ; } else if ( ! GVar -> hasCommonLinkage ( ) ) { O << <STR_LIT> << name << '\n' << TAI -> getWeakDefDirective ( ) << name << '\n' ; EmitAlignment ( Align , GVar ) ; O << name << <STR_LIT> ; if ( VerboseAsm ) { O << <STR_LIT> << TAI -> getCommentString ( ) << <STR_LIT> ; PrintUnmangledNameSafely ( GVar , O ) ; } O << '\n' ; EmitGlobalConstant ( C ) ; return ; } else { O << <STR_LIT> << name << ',' << Size ; if ( Subtarget . isDarwin9 ( ) ) O << ',' << Align ; } if ( VerboseAsm ) { O << <STR_LIT> << TAI -> getCommentString ( ) << <STR_LIT> ; PrintUnmangledNameSafely ( GVar , O ) ; O << <STR_LIT> ; } O << '\n' ; return ; } switch ( GVar -> getLinkage ( ) ) { case GlobalValue :: LinkOnceAnyLinkage : case GlobalValue :: LinkOnceODRLinkage : case GlobalValue :: WeakAnyLinkage : case GlobalValue :: WeakODRLinkage : case GlobalValue :: CommonLinkage : O << <STR_LIT> << name << '\n' << <STR_LIT> << name << '\n' ; break ; case GlobalValue :: AppendingLinkage : case GlobalValue :: ExternalLinkage : O << <STR_LIT> << name << '\n' ; case GlobalValue :: InternalLinkage : case GlobalValue ::


<s> const MCOperand & MO1 = MI . getOperand ( OpIdx + <NUM_LIT> ) ; bool isAdd = MO1 .


<s> if ( ! Op . isImm ( ) ) return printOperand ( MI , OpNo , O ) ; uint64_t Target = Op .


<s> bool enableAggressiveFMAFusion ( EVT VT )


<s> Sch . BaseClass :: startBlock ( BB ) ; Sch . BaseClass :: enterRegion ( BB , R . Begin , R . End , R . NumRegionInstrs ) ; Sch . buildSchedGraph ( Sch . AA , nullptr


<s> } if ( IndexReg . getReg ( ) ) { if ( NeedPlus ) O << <STR_LIT> ; if ( ScaleVal != <NUM_LIT> ) O << ScaleVal << '*' ; printOperand ( MI , Op + <STR_LIT> , O ) ; NeedPlus = true ; } if ( ! DispSpec . isImm ( ) ) { if ( NeedPlus ) O << <STR_LIT> ; assert ( DispSpec . isExpr ( ) && <STR_LIT> ) ; O << * DispSpec . getExpr ( ) ; } else { int64_t DispVal = DispSpec . getImm ( ) ; if ( DispVal || ( ! IndexReg . getReg ( ) && ! BaseReg . getReg


<s> return DAG . getZExtOrTrunc ( V , DL , VT ) ; } } bool IsTruncated = Src . getOpcode ( ) == <STR_LIT> && Src . hasOneUse ( ) && ( Src . getOperand ( <NUM_LIT> ) . getValueType ( ) == <STR_LIT> || Src . getOperand ( <NUM_LIT> ) . getValueType ( ) == <STR_LIT> || Src . getOperand ( <NUM_LIT> ) . getValueType ( ) == <STR_LIT> ) ; if ( ! Subtarget . hasSSE2 ( ) || ( Subtarget . hasAVX512 ( ) && ! IsTruncated ) ) return SDValue ( ) ; MVT SExtVT ; bool PropagateSExt = false ; switch ( SrcVT . getSimpleVT ( ) . SimpleTy ) { default : return SDValue ( ) ; case <STR_LIT> : SExtVT = <STR_LIT> ; break ; case <STR_LIT> : SExtVT = <STR_LIT> ; if ( Subtarget . hasAVX ( ) && checkBitcastSrcVectorSize ( Src , <NUM_LIT> ) ) { SExtVT = <STR_LIT> ; PropagateSExt = true ; } break ; case <STR_LIT> : SExtVT = <STR_LIT> ; if ( Subtarget . hasAVX ( ) && ( checkBitcastSrcVectorSize ( Src , <NUM_LIT> ) || checkBitcastSrcVectorSize ( Src , <NUM_LIT> ) ) ) { SExtVT = <STR_LIT> ; PropagateSExt = true ; } break ; case <STR_LIT> : SExtVT = <STR_LIT> ; break ; case <STR_LIT> : SExtVT = <STR_LIT> ; break ; case <STR_LIT> : if ( Subtarget . hasAVX512


<s> void \ rozdata_section ( ) \ { \ if ( in_section != in_rozdata ) \ { \ fprintf

( asm_out_file , <STR_LIT> , ROZDATA_SECTION_ASM_OP ) ; \ in_section = in_rozdata ; \ } \ }


<s> else if ( INSN_ADDRESSES ( INSN_UID ( pool -> emit_pool_after ) ) + pool -> size + <NUM_LIT> < <NUM_LIT> ) { rtx set = gen_main_base_31_small ( base_reg , pool -> label ) ; rtx_insn * insn = emit_insn_after ( set , pool -> pool_insn ) ; INSN_ADDRESSES_NEW ( insn , - <NUM_LIT> ) ; remove_insn ( pool -> pool_insn ) ; insn = emit_label_after ( pool -> label , insn ) ; INSN_ADDRESSES_NEW ( insn , - <NUM_LIT> ) ; insn = pool -> emit_pool_after ; pool -> pool_insn = emit_insn_after ( gen_pool ( const0_rtx ) , insn ) ; INSN_ADDRESSES_NEW ( pool -> pool_insn , - <NUM_LIT> ) ; s390_dump_pool ( pool , <NUM_LIT> ) ; } else { rtx_code_label * pool_end = gen_label_rtx ( ) ; rtx pat = gen_main_base_31_large ( base_reg , pool -> label , pool_end ) ; rtx_insn * insn = emit_jump_insn_after ( pat , pool -> pool_insn ) ; JUMP_LABEL ( insn ) = pool_end ; INSN_ADDRESSES_NEW ( insn , - <NUM_LIT> ) ; remove_insn ( pool -> pool_insn ) ; insn = emit_label_after ( pool -> label , insn ) ; INSN_ADDRESSES_NEW ( insn , - <NUM_LIT> ) ; pool -> pool_insn = emit_insn_after ( gen_pool ( const0_rtx ) , insn ) ; INSN_ADDRESSES_NEW ( pool -> pool_insn , - <NUM_LIT> ) ; insn = emit_label_after ( pool_end , pool -> pool_insn ) ; INSN_ADDRESSES_NEW ( insn , - <NUM_LIT> ) ; s390_dump_pool ( pool , <NUM_LIT> ) ; } for ( rtx_insn * insn = get_insns ( ) ; insn ; insn = NEXT_INSN ( insn ) ) { if ( INSN_P ( insn ) ) replace_ltrel_base ( & PATTERN ( insn ) ) ; if ( NONJUMP_INSN_P ( insn ) ||


<s> asm_fprintf ( file , <STR_LIT> ) ; } if ( GET_CODE ( op ) == REG ) { if ( letter == 'b' && S_REG_P ( op ) ) { asm_print_register ( file , REGNO ( op ) ) ; fprintf ( file , <STR_LIT> ) ; } else if ( letter == 'b' && D_REG_P ( op ) ) { asm_print_register ( file , HARD_B_REGNUM ) ; } else { asm_print_register ( file , REGNO ( op ) ) ; } return ; } if ( GET_CODE ( op ) == SYMBOL_REF && ( letter == 'b' || letter == 'h' ) ) { if ( letter == 'b' ) asm_fprintf ( file , <STR_LIT> ) ; else asm_fprintf ( file , <STR_LIT> ) ; output_addr_const ( file , op ) ; fprintf ( file , <STR_LIT> ) ; return ; } if ( GET_MODE ( op ) == HImode || GET_MODE ( op ) == VOIDmode ) { if ( letter == 'b' ) { op = m68hc11_gen_lowpart ( QImode , op ) ; } else if ( letter == 'h' ) { op = m68hc11_gen_highpart ( QImode , op ) ; } } if ( GET_CODE ( op ) == MEM ) { rtx base = XEXP ( op , <NUM_LIT> ) ; switch ( GET_CODE ( base ) ) { case PRE_DEC : gcc_assert ( TARGET_M6812 ) ; fprintf ( file , <STR_LIT> , GET_MODE_SIZE ( GET_MODE ( op ) ) ) ; asm_print_register ( file , REGNO ( XEXP ( base , <NUM_LIT> ) ) ) ; break ; case POST_DEC : gcc_assert ( TARGET_M6812 ) ; fprintf ( file , <STR_LIT> , GET_MODE_SIZE ( GET_MODE ( op ) ) ) ; asm_print_register ( file , REGNO ( XEXP ( base , <NUM_LIT> ) ) ) ; fprintf ( file , <STR_LIT> ) ; break ; case POST_INC : gcc_assert ( TARGET_M6812 ) ; fprintf ( file , <STR_LIT> , GET_MODE_SIZE ( GET_MODE ( op ) ) ) ; asm_print_register ( file , REGNO ( XEXP ( base , <NUM_LIT> ) ) ) ; fprintf ( file , <STR_LIT> ) ; break ; case PRE_INC : gcc_assert ( TARGET_M6812 ) ; fprintf ( file , <STR_LIT> , GET_MODE_SIZE ( GET_MODE ( op ) ) ) ; asm_print_register ( file , REGNO ( XEXP ( base , <NUM_LIT> ) ) ) ; break ; case MEM : gcc_assert ( TARGET_M6812 ) ; fprintf ( file , <STR_LIT> ) ; print_operand_address ( file , XEXP ( base , <NUM_LIT> )


<s> case <NUM_LIT> : return & <STR_LIT> ; case <NUM_LIT> : return & <STR_LIT> ; case <NUM_LIT> : return & <STR_LIT> ; case <NUM_LIT> : return & <STR_LIT> ; case <NUM_LIT> : return & <STR_LIT> ; default : llvm_unreachable ( <STR_LIT>


<s> unsigned bytes = unsigned ( CN -> getZExtValue ( ) ) >> <NUM_LIT> ; unsigned bits = unsigned ( CN -> getZExtValue ( ) ) & <NUM_LIT> ; if ( bytes > <NUM_LIT> ) { Shift = CurDAG -> getTargetNode ( <STR_LIT> , dl , VecVT , SDValue ( VecOp0 , <NUM_LIT> ) , CurDAG -> getTargetConstant ( bytes , ShiftAmtVT ) ) ; } if ( bits > <NUM_LIT> ) { Shift = CurDAG -> getTargetNode ( <STR_LIT> , dl , VecVT , SDValue ( ( Shift != <NUM_LIT> ? Shift : VecOp0 ) , <NUM_LIT> ) , CurDAG -> getTargetConstant ( bits , ShiftAmtVT ) ) ; } } else { SDNode * Bytes = CurDAG -> getTargetNode ( <STR_LIT> , dl , ShiftAmtVT , ShiftAmt , CurDAG -> getTargetConstant ( <NUM_LIT> , ShiftAmtVT ) ) ; SDNode * Bits = CurDAG -> getTargetNode ( <STR_LIT> , dl , ShiftAmtVT , ShiftAmt , CurDAG -> getTargetConstant ( <NUM_LIT> , ShiftAmtVT ) ) ; Bytes = CurDAG -> getTargetNode ( <STR_LIT> , dl , ShiftAmtVT , SDValue ( Bytes ,

<NUM_LIT> ) , CurDAG -> getTargetConstant ( <NUM_LIT> , ShiftAmtVT ) ) ;


<s> insn = emit_move_insn ( to , scratch ) ; } if ( IS_STACK_PUSH ( to ) ) { REG_NOTES ( insn ) = gen_rtx_EXPR_LIST ( REG_INC , XEXP ( XEXP ( to , <NUM_LIT> ) , <NUM_LIT> ) , REG_NOTES ( insn ) ) ; } else if ( IS_STACK_POP ( from ) ) { REG_NOTES ( insn ) = gen_rtx_EXPR_LIST ( REG_INC , XEXP ( XEXP ( from , <NUM_LIT> ) , <NUM_LIT> ) , REG_NOTES ( insn ) ) ; } else if ( TARGET_M6811 && SP_REG_P ( from ) ) { REG_NOTES ( insn ) = gen_rtx_EXPR_LIST ( REG_INC , from , REG_NOTES ( insn


<s> } else if ( ! printAliasInstr ( MI , OS ) && ! printVecCompareInstr ( MI , OS ) ) printInstruction ( MI , Address , OS ) ; printAnnotation ( OS , Annot ) ; if ( CommentStream ) EmitAny<ISA_LIT>InstComments ( MI


<s> struct df_link * link = DF_REF_CHAIN ( def ) ; if ( ! link || link -> next ) break ; rtx_insn * swap_insn = DF_REF_INSN ( link -> ref ) ; if ( ! insn_is_swap_p ( swap_insn ) || insn_is_load_p ( swap_insn ) || insn_is_store_p ( swap_insn ) ) break ; to_delete [ INSN_UID ( swap_insn ) ] . replace = true ; to_delete [ INSN_UID ( swap_insn ) ] . replace_insn = swap_insn ; XEXP ( mem , <NUM_LIT> ) =


<s> MachineBasicBlock * DestBB = MI -> getOperand ( TargetOperand ) . getMBB ( ) ; if ( isBBInRange ( MI , DestBB , Br . MaxDisp ) ) return false ; if ( ! Br . isCond ) return fixupUnconditionalBr ( Br ) ; return fixupConditionalBr (


<s> bool <ISA_LIT>RegisterInfo :: needsStackRealignment ( const MachineFunction & MF ) const { const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const Function * F = MF . getFunction (


<s> bool <ISA_LIT>PassConfig :: addPreSched2 ( ) { if ( get<ISA_LIT>Subtarget ( ) . hasVSX ( ) ) addPass ( create<ISA_LIT>VSXCopyCleanupPass ( ) ) ; if ( getOptLevel ( ) != CodeGenOpt :: None


<s> if ( MO . isImm ( ) ) < unsigned > ( MO . getImm ( ) ) ; assert ( MO . isExpr ( ) && MO . getExpr ( ) -> getKind ( ) == MCExpr :: SymbolRef ) ; <STR_LIT> FixupKind = <STR_LIT> ; switch ( MI . getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : FixupKind = <STR_LIT> ; break ; case <STR_LIT>


<s> MCCodeEmitter * llvm :: create<ISA_LIT>MCCodeEmitter ( const MCInstrInfo &


<s> } if ( ( V >> <NUM_LIT> ) & <NUM_LIT> ) { O << LS ; printRegName ( O , <STR_LIT> ) ; } if ( ( V >> <NUM_LIT> ) & <NUM_LIT> ) { O << LS ; printRegName ( O , <STR_LIT> ) ; auto Offset = ( ( V >> <NUM_LIT> ) & <NUM_LIT> ) - <NUM_LIT> ; if ( Offset ) { O << <STR_LIT> ; printRegName ( O , <STR_LIT> +


<s> Register DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( ! MRI . getType ( DstReg ) . isScalar ( ) ) return false ; Register AndReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register OfsReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; int64_t Offset ; if ( ! mi_match ( OfsReg , MRI , m_ICst ( Offset ) ) ) return false ; Register SrcReg ; int64_t Mask ; if ( ! mi_match ( AndReg , MRI , m_GAnd ( m_Reg ( SrcReg ) , m_ICst ( Mask ) ) ) ) return false ; uint64_t MaskWidth ,


<s> if ( load_p ) regindex = <NUM_LIT> , memindex = <NUM_LIT> , offset = ( nregs - index - <NUM_LIT> ) * <NUM_LIT> ; else memindex = <NUM_LIT> , regindex = <NUM_LIT> , offset = ( index + <NUM_LIT> ) * - <NUM_LIT> ; if ( GET_CODE ( x ) == SET && GET_CODE ( XEXP ( x , regindex ) ) == REG && GET_CODE ( XEXP ( x , memindex ) ) == MEM && h8300_stack_offset_p ( XEXP ( XEXP ( x , memindex ) , <NUM_LIT> )

, offset ) ) return REGNO ( XEXP ( x , regindex ) ) ;


<s> unsigned I2 = ! ( J2 ^ S ) ; unsigned tmp = ( Val & ~ <NUM_LIT> ) | ( I1 << <NUM_LIT> ) | ( I2 << <NUM_LIT> ) ; int imm32 = SignExtend32 < <NUM_LIT> > ( tmp << <NUM_LIT> ) ; if ( ! tryAddingSymbolicOperand ( Address , Address + imm32 + <NUM_LIT> , true , <NUM_LIT> , Inst

, Decoder ) ) Inst . addOperand ( MCOperand :: createImm ( imm32 ) ) ;


<s> if ( ! CSel0 -> hasOneUse ( ) || ! CSel1 -> hasOneUse ( ) ) return SDValue ( ) ; if ( ! isNullConstant ( CSel0 . getOperand ( <NUM_LIT> ) ) || ! isOneConstant ( CSel0 . getOperand ( <NUM_LIT> ) ) || ! isNullConstant ( CSel1 . getOperand ( <NUM_LIT> ) ) || ! isOneConstant ( CSel1 . getOperand ( <NUM_LIT> ) ) ) return SDValue ( ) ; SDValue Cmp0 = CSel0 . getOperand ( <NUM_LIT> ) ; SDValue Cmp1 = CSel1 . getOperand ( <NUM_LIT> ) ; <STR_LIT> CC0 = ( <STR_LIT> ) CSel0 . getConstantOperandVal ( <NUM_LIT> ) ; <STR_LIT> CC1 = ( <STR_LIT> ) CSel1 . getConstantOperandVal ( <NUM_LIT> ) ; if ( ! Cmp0 -> hasOneUse ( ) || ! Cmp1 -> hasOneUse ( ) ) return SDValue ( ) ; if ( Cmp1 . getOpcode ( ) != <STR_LIT> && Cmp0 . getOpcode ( ) == <STR_LIT> ) { std :: swap ( Cmp0 , Cmp1 ) ; std :: swap ( CC0 , CC1 ) ; } if ( Cmp1 . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; SDLoc DL ( N ) ; SDValue CCmp ; if ( N -> getOpcode ( ) == <STR_LIT> ) { <STR_LIT> InvCC0 = <STR_LIT> ( CC0 ) ; SDValue Condition = DAG . getConstant ( InvCC0 , DL , MVT_CC ) ; unsigned NZCV = <STR_LIT> ( CC1 ) ; SDValue NZCVOp = DAG . getConstant ( NZCV , DL , <STR_LIT> ) ; CCmp = DAG . getNode ( <STR_LIT> , DL , MVT_CC , Cmp1 . getOperand ( <NUM_LIT> ) , Cmp1 . getOperand ( <NUM_LIT> ) , NZCVOp , Condition , Cmp0 ) ; } else { SDLoc DL ( N


<s> static void rs6000_option_override (


<s> return ( __m128d ) __builtin_ia32_vextractf128_pd256 ( (


<s> explicit <ISA_LIT>AsmPrinter ( formatted_raw_ostream & O , TargetMachine & TM , MCContext & Ctx , MCStreamer & Streamer , const

MCAsmInfo * T ) : AsmPrinter ( O , TM , Ctx , Streamer , T ) {


<s> if ( MBB != Header ) LoopSize += MBB -> getAlignment ( ) . value ( ) / <NUM_LIT> ; for ( const MachineInstr & MI : * MBB ) { LoopSize += TII -> getInstSizeInBytes ( MI ) ; if ( LoopSize > <NUM_LIT> ) return PrefAlign ; } } if ( LoopSize <= <NUM_LIT> ) return PrefAlign ; if ( LoopSize <= <NUM_LIT> ) return CacheLineAlign ; for ( MachineLoop * P = ML -> getParentLoop ( ) ; P ; P = P -> getParentLoop ( ) ) { if ( MachineBasicBlock * Exit = P -> getExitBlock ( ) ) { auto I = Exit -> getFirstNonDebugInstr ( ) ; if ( I != Exit -> end ( ) && I -> getOpcode ( ) == <STR_LIT> ) return CacheLineAlign ; } } MachineBasicBlock * Pre = ML -> getLoopPreheader ( ) ; MachineBasicBlock * Exit = ML -> getExitBlock ( ) ; if ( Pre && Exit ) { BuildMI ( * Pre , Pre -> getFirstTerminator ( ) , DebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addImm ( <NUM_LIT> ) ; BuildMI ( * Exit , Exit -> getFirstNonDebugInstr ( ) , DebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addImm ( <NUM_LIT> ) ; } return


<s> if ( shift_amount_i == <NUM_LIT> ) return true ; return ( ashl_lshr_seq [ shift_amount_i ] . clobbers_t & ASHL_CLOBBERS_T )


<s> SDValue RHS = Op . getOperand ( <NUM_LIT> ) ; SDValue Zero = DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , dl , DAG . getVTList ( <STR_LIT> , <STR_LIT> ) , Zero , Zero ,


<s> unsigned off16_2 = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned off16 = ( off16_0 << <NUM_LIT> ) | ( off16_1 << <NUM_LIT> ) | ( off16_2 << <NUM_LIT> ) ; unsigned s2 = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned s1_d = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned is32Bit = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; if ( ! is32Bit ) return MCDisassembler :: Fail ; Inst . addOperand ( MCOperand :: createImm


<s> uint8_t OSABI = MCELFObjectTargetWriter :: getOSABI ( Triple (


( CLASSTYPE_TYPEINFO_VAR ( TYPE_MAIN_VARIANT ( ctype ) ) , attr_name ) ;


<s> Type * ScalarType = DataType -> getScalarType ( ) ; if ( ! TLI -> isLegalElementTypeForRVV ( ScalarType ) ) return false ; MaybeAlign MA = cast < ConstantInt > ( AlignOp


<s> return SYMBOL_REF_P ( x ) && SYMBOL_REF_TLS_MODEL ( x )


<s> if ( VT == <STR_LIT> ) return LowerFDIV64 ( Op , DAG ) ; if ( VT == <STR_LIT> ) return LowerFDIV16 ( Op ,


<s> static scalar_int_mode aarch64_sve_element_int_mode ( machine_mode mode ) { poly_uint64 vector_bits = ( GET_MODE_CLASS ( mode ) == MODE_VECTOR_BOOL ? BITS_PER_SVE_VECTOR : GET_MODE_BITSIZE ( mode ) ) ; unsigned int elt_bits = vector_element_size ( vector_bits , GET_MODE_NUNITS ( mode ) ) ; return int_mode_for_size ( elt_bits , <NUM_LIT> ) . require


<s> if ( GET_CODE ( x ) != PLUS ) return false ; if ( ! RTX_OK_FOR_BASE_P ( XEXP ( x , <NUM_LIT> ) , ( strict ) ) ) return false ; if ( ( ( index && RTX_OK_FOR_INDEX_P ( XEXP ( x , <NUM_LIT> ) , ( strict ) ) && GET_MODE_SIZE ( ( mode ) ) <= <NUM_LIT> ) || RTX_OK_FOR_OFFSET_P ( mode , XEXP ( x , <NUM_LIT> ) ) ) ) return true ; if ( ! flag_pic && ( GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == SYMBOL_REF ) && ( GET_MODE_SIZE ( mode ) <= <NUM_LIT> ) && ( ! SYMBOL_REF_SMALL_P ( XEXP ( x , <NUM_LIT> ) ) ) ) return true ; return


<s> } auto * Call = dyn_cast < CallInst > ( & I ) ; if ( ! Call ) continue ; auto * GV = dyn_cast < GlobalValue > ( Call -> getCalledOperand ( ) ) ; if ( ! GV ) continue ; if ( ! GV -> getName ( ) . startswith ( <STR_LIT> ) ) continue ; Changed = true ; Value * Arg0 = Call -> getArgOperand ( <NUM_LIT> ) ; Value * Arg1 = Call -> getArgOperand ( <NUM_LIT>


<s> static DecodeStatus DecodeF4RCRegisterClass ( MCInst & Inst , uint64_t RegNo , uint64_t Address , const MCDisassembler *


<s> case OImode : return aarch64_simd_intOI_type_node ; case CImode : return aarch64_simd_intCI_type_node ; case XImode : return aarch64_simd_intXI_type_node ; case HFmode : return aarch64_fp16_type_node ; case SFmode : return float_type_node ; case DFmode : return double_type_node ; default : gcc_unreachable (


<s> if ( N -> hasAnyUseOfValue ( <NUM_LIT> ) ) { SDValue CopyFromLo = DAG . getCopyFromReg ( InChain , DL , LO , Ty , InGlue ) ; DAG . ReplaceAllUsesOfValueWith ( SDValue ( N , <NUM_LIT> ) , CopyFromLo ) ; InChain = CopyFromLo . getValue ( <NUM_LIT> ) ; InGlue = CopyFromLo . getValue ( <NUM_LIT> ) ; } if ( N -> hasAnyUseOfValue ( <NUM_LIT> ) ) { SDValue CopyFromHi = DAG . getCopyFromReg ( InChain , DL , HI , Ty , InGlue ) ; DAG . ReplaceAllUsesOfValueWith ( SDValue ( N , <NUM_LIT> ) , CopyFromHi ) ; } return SDValue


<s> } } unsigned NumBytes = CCInfo . getAlignedCallFrameSize ( ) ; SDValue FINode ; if ( IsVarArg && NumBytes ) { int FI = MF . getFrameInfo ( ) . CreateStackObject ( NumBytes , Layout . getStackAlignment ( ) , false ) ; unsigned ValNo = <NUM_LIT> ; SmallVector < SDValue , <NUM_LIT> > Chains ; for ( SDValue Arg : make_range ( OutVals . begin ( ) + NumFixedArgs , OutVals . end ( ) ) ) { assert ( ArgLocs [ ValNo ] . getValNo ( ) == ValNo && <STR_LIT> ) ; unsigned Offset = ArgLocs [ ValNo ++ ] . getLocMemOffset ( ) ; FINode = DAG . getFrameIndex ( FI , getPointerTy ( Layout ) ) ; SDValue Add = DAG . getNode ( <STR_LIT> , DL , PtrVT , FINode , DAG . getConstant ( Offset , DL , PtrVT ) ) ; Chains . push_back ( DAG . getStore ( Chain , DL , Arg , Add , MachinePointerInfo :: getFixedStack ( MF , FI , Offset ) , <NUM_LIT> ) ) ; } if ( ! Chains . empty ( ) ) Chain = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Chains ) ; } else if ( IsVarArg ) { FINode = DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ; } if ( Callee -> getOpcode ( ) == <STR_LIT> ) { GlobalAddressSDNode * GA = cast < GlobalAddressSDNode > ( Callee ) ; Callee = DAG . getTargetGlobalAddress ( GA -> getGlobal ( ) , DL , getPointerTy ( DAG . getDataLayout ( ) ) , GA -> getOffset ( ) ) ; Callee = DAG . getNode ( <STR_LIT> , DL , getPointerTy ( DAG . getDataLayout ( ) ) , Callee ) ; } SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . push_back ( Chain ) ; Ops . push_back ( Callee ) ; Ops . append ( OutVals . begin ( ) , IsVarArg ? OutVals . begin ( ) + NumFixedArgs : OutVals . end ( ) ) ; if ( IsVarArg ) Ops . push_back ( FINode ) ; SmallVector < EVT , <NUM_LIT> > InTys ; for ( const auto & In : Ins ) { assert ( ! In . Flags . isByVal ( ) && <STR_LIT> ) ; assert ( ! In . Flags . isNest ( ) &&


<s> unsigned NumBytes = getFixupKindNumBytes ( Fixup . getKind ( ) ) ; Value = adjustFixupValue ( Fixup , Value , IsPCRel , Ctx , IsLittleEndian , true ) ; if ( ! Value ) return ; unsigned Offset = Fixup . getOffset ( ) ; assert ( Offset + NumBytes <= DataSize && <STR_LIT>


<s> static inline unsigned getADDrrFromLEA ( unsigned LEAOpcode ) { switch ( LEAOpcode ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT>


<s> uint64_t Idx = Elt . getConstantOperandVal ( <NUM_LIT> ) ; if ( ( Idx % <NUM_LIT> ) == <NUM_LIT> && findEltLoadSrc ( Elt . getOperand ( <NUM_LIT> ) , Ld , ByteOffset ) ) { ByteOffset += Idx / <NUM_LIT> ; return true ; } } break ; case <STR_LIT> : if ( isa < ConstantSDNode > ( Elt . getOperand ( <NUM_LIT> ) ) ) { SDValue Src = Elt . getOperand ( <NUM_LIT> ) ; unsigned SrcSizeInBits = Src . getScalarValueSizeInBits ( ) ; unsigned DstSizeInBits = Elt . getScalarValueSizeInBits


<s> if ( STI . dumpCode ( ) && ! isBlockOnlyReachableByFallthrough ( & MBB ) ) { DisasmLines . push_back ( ( Twine ( <STR_LIT> ) + Twine ( getFunctionNumber ( ) ) + <STR_LIT> + Twine ( MBB . getNumber ( ) ) + <STR_LIT> ) . str ( ) ) ; DisasmLineMaxLen = std :: max ( DisasmLineMaxLen , DisasmLines . back ( ) . size ( ) ) ; HexLines . push_back


<s> } if ( GO -> isDeclaration ( ) ) { return cast < MCSectionXCOFF > ( getObjFileLowering ( ) . getSectionForExternalReference ( GO , TM ) ) -> getQualNameSymbol ( ) ; } SectionKind GOKind = getObjFileLowering ( ) . getKindForGlobal ( GO , TM ) ; if ( GOKind . isText ( ) ) { return cast < MCSectionXCOFF > ( getObjFileLowering ( ) . getSectionForFunctionDescriptor ( cast < const Function > ( GO ) , TM ) ) -> getQualNameSymbol ( ) ; } else if ( GOKind . isCommon ( ) || GOKind . isBSSLocal ( ) ) { return cast < MCSectionXCOFF > ( getObjFileLowering ( ) . SectionForGlobal ( GO

, GOKind , TM ) ) -> getQualNameSymbol ( ) ;


<s> const char * <ISA_LIT>TargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( ( <STR_LIT> ) Opcode ) { case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return


<s> Register DstReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; const LLT Ty = MRI . getType ( DstReg ) ; Register Src1Reg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register Src2Reg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( ! Ty . isVector ( ) ) return false ; unsigned Opc = <NUM_LIT> ; if ( Ty == LLT :: vector ( <NUM_LIT> , <NUM_LIT> ) ) { Opc = <STR_LIT> ; } else if ( Ty == LLT :: vector ( <NUM_LIT> , <NUM_LIT> ) ) { Opc = <STR_LIT> ; } else if ( Ty == LLT :: vector ( <NUM_LIT> , <NUM_LIT> ) ) { Opc = <STR_LIT> ; } else { LLVM_DEBUG ( dbgs ( ) << <STR_LIT>


<s> for ( uint64_t i = <NUM_LIT> ; i < Count ; i += <NUM_LIT> ) OW -> Write32 ( <NUM_LIT> ) ; return true


<s> REAL_VALUE_FROM_CONST_DOUBLE ( r , op ) ; return REAL_VALUES_EQUAL ( r


<s> void <ISA_LIT>PassConfig :: addIRPasses ( ) { addPass ( createAtomicExpandPass ( ) ) ; TargetPassConfig :: addIRPasses


<s> FieldInit += IDStr ; if ( isa < StructType > ( ElmTy ) ) FieldInit += <STR_LIT> ; else FieldInit += <STR_LIT> ; FieldInit += ElmTyStr ; FieldInit += <STR_LIT> ; FieldInit += ClassName ; FieldInit += <STR_LIT> ; IDStr [ <NUM_LIT> ] = '\0' ; sprintf ( IDStr , <STR_LIT> , FieldID ) ; FieldInit += IDStr ; FieldInit += <STR_LIT> ; MFI -> getTypeDescriptor ( Ty , FieldInit ) ; if ( isa < StructType > ( ElmTy ) ) { for ( unsigned i = <NUM_LIT> ; i < NumElm ; i ++ ) { FieldInit += <STR_LIT> ; FieldInit += <STR_LIT> ; FieldInit += ClassName ; FieldInit += <STR_LIT> ; IDStr [ <NUM_LIT> ] = '\0' ; sprintf ( IDStr , <STR_LIT> , FieldID ) ; FieldInit += IDStr ; FieldInit += <STR_LIT> ; MFI -> getTypeDescriptor ( Ty , FieldInit ) ; if ( i < <NUM_LIT> ) FieldInit += <STR_LIT> ; else FieldInit += <STR_LIT> ; IDStr [ <NUM_LIT> ] = '\0' ; sprintf ( IDStr , <STR_LIT> , i ) ; FieldInit += IDStr ; FieldInit += <STR_LIT> ; FieldInit += ElmTyStr ; FieldInit += <STR_LIT> ; FieldInit += <STR_LIT> ; FieldInit += ElmTyStr ; FieldInit += <STR_LIT> ; FieldInit += <STR_LIT> ; } } } else if ( isa < StructType > ( Ty ) ) { char IDStr [ <NUM_LIT> ] = { '\0' } ; std :: string TypeStr = EmitTypeString ( Ty ) ; FieldInit += <STR_LIT> ; FieldInit += <STR_LIT> ; FieldInit += TypeStr ; FieldInit += <STR_LIT> ; FieldInit += <STR_LIT> ; FieldInit += TypeStr ; FieldInit += <STR_LIT> ; FieldInit += <STR_LIT> ; FieldInit += ClassName ; FieldInit += <STR_LIT> ; sprintf ( IDStr ,


<s> bool <ISA_LIT>LDBackend :: initBRIslandFactory ( ) { if ( m_pBRIslandFactory == NULL ) { m_pBRIslandFactory = new BranchIslandFactory ( maxFwdBranchOffset ( ) , maxBwdBranchOffset (


<s> virtual void getAnalysisUsage ( AnalysisUsage & AU ) const { AU . setPreservesCFG ( ) ; AU . addRequired < MachineDominatorTree


<s> unsigned GCNMinRegScheduler :: findMax ( unsigned Num , Calc C ) { assert ( ! RQ . empty ( ) && Num <= RQ . size ( ) ) ; typedef decltype ( C ( * RQ . begin ( ) ) ) T ; T Max = std :: numeric_limits < T > :: min ( ) ; unsigned NumMax = <NUM_LIT> ; for ( auto I = RQ . begin ( ) ; Num


<s> SDLoc DL ( Node ) ; EVT VT = Node -> getValueType ( <NUM_LIT> ) ; switch ( Opcode ) { case <STR_LIT> : { if ( auto * ConstOp = dyn_cast < ConstantSDNode > ( Node -> getOperand ( <NUM_LIT> ) ) ) { if ( ! ( ConstOp -> hasOneUse ( ) ) ) break ; int64_t Imm = ConstOp -> getSExtValue ( ) ; if ( ! ( - <NUM_LIT> <= Imm && Imm <= - <NUM_LIT> ) && ! ( <NUM_LIT> <= Imm && Imm <= <NUM_LIT> ) ) break ; SDLoc DL ( Node ) ; EVT VT = Node -> getValueType ( <NUM_LIT> ) ; const SDValue ImmOp0 = CurDAG -> getTargetConstant ( Imm - Imm / <NUM_LIT> , DL , VT ) ; const SDValue ImmOp1 = CurDAG -> getTargetConstant ( Imm / <NUM_LIT> , DL , VT ) ; auto * NodeAddi0 = CurDAG -> getMachineNode ( <STR_LIT> , DL , VT , Node -> getOperand ( <NUM_LIT> ) , ImmOp0 ) ; auto * NodeAddi1 = CurDAG -> getMachineNode ( <STR_LIT> , DL , VT , SDValue ( NodeAddi0 , <NUM_LIT> ) , ImmOp1 ) ; ReplaceNode ( Node , NodeAddi1 ) ; return ; } break ; } case <STR_LIT> : { auto ConstNode = cast < ConstantSDNode > ( Node ) ; if ( VT == XLenVT && ConstNode -> isNullValue ( ) ) { SDValue New = CurDAG -> getCopyFromReg ( CurDAG -> getEntryNode (

) , SDLoc ( Node ) , <STR_LIT> , XLenVT ) ;


<s> void <ISA_LIT>RegisterInfo :: eliminateFrameIndex ( MachineBasicBlock :: iterator II , int SPAdj

, unsigned FIOperandNum , RegScavenger * RS ) const {


<s> bool hasSoftFloat ( ) const { return HasSoftFloat


<s> for ( auto Val : typeValues [ Ty . first ] ) Val -> dump ( ) ; dbgs ( ) << <STR_LIT> ; if ( Ty . second ) Ty . second -> dump ( ) ; else dbgs ( ) << <STR_LIT> ; dbgs ( )


<s> return __builtin_aarch64_fix_trunchfdi (


<s> bool FixupLEAPass :: runOnMachineFunction ( MachineFunction & Func ) { TM = & Func . getTarget ( ) ; const <ISA_LIT>Subtarget & ST = TM -> getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( ! ST . LEAusesAG ( ) && ! ST . slowLEA ( ) ) return false ; TII = static_cast < const <ISA_LIT>InstrInfo * > ( TM -> getInstrInfo ( ) ) ; DEBUG ( dbgs ( ) << <STR_LIT> ; ) ; for ( MachineFunction :: iterator I = Func . begin ( ) , E = Func . end ( ) ; I != E ; ++ I ) processBasicBlock ( Func , I ) ; DEBUG ( dbgs ( ) << <STR_LIT> ; ) ; return


<s> return ( __m128i ) __builtin_ia32_pmovusqd256_mask ( ( __v4di ) __A , ( __v4si ) _mm_undefined_si128 ( ) , ( __mmask8


<s> unsigned getNumFixupKinds ( ) const override { return <STR_LIT>


<s> EVT <ISA_LIT>TargetLowering :: getSetCCResultType ( EVT VT ) const { if ( ! VT . isVector ( ) ) return getPointerTy ( ) ; return VT .


<s> AssemblerOptions . push_back ( llvm :: make_unique < <ISA_LIT>AssemblerOptions > ( getSTI ( ) . getFeatureBits ( ) ) ) ; getTargetStreamer ( ) . updateABIInfo ( * this ) ; if ( ! isABI_O32 ( ) && ! useOddSPReg ( ) != <NUM_LIT> ) report_fatal_error ( <STR_LIT> ) ; CurrentFn = nullptr ; IsPicEnabled = getContext ( ) . getObjectFileInfo ( ) -> isPositionIndependent ( ) ; IsCpRestoreSet = false ; CpRestoreOffset = - <NUM_LIT> ; const Triple & TheTriple = sti . getTargetTriple ( ) ; IsLittleEndian = TheTriple . isLittleEndian ( ) ; if ( getSTI ( ) . getCPU ( ) == <STR_LIT> && inMicro<ISA_LIT>Mode ( ) ) report_fatal_error ( <STR_LIT> , false ) ; if ( ! isABI_O32 ( ) && inMicro<ISA_LIT>Mode ( ) ) report_fatal_error ( <STR_LIT> , false


<s> return CurDAG -> getRegister ( GlobalBaseReg , TLI -> getPointerTy ( DL ) )


<s> std :: unique_ptr < MCObjectTargetWriter > llvm :: create<ISA_LIT>ObjectWriter ( uint8_t


<s> if ( ! getVShiftImm ( Op , ElementBits , Cnt ) ) return false ; if ( isIntrinsic ) Cnt = - Cnt ; return ( Cnt >= <NUM_LIT> && Cnt <= ( isNarrow ?

ElementBits / <NUM_LIT> : ElementBits ) ) ;


<s> Inst . addOperand ( MCOperand :: CreateImm ( <NUM_LIT>


<s> } MachineLoop * InnerLoop = MLI . getLoopFor ( Next ) ; if ( InnerLoop != Loop ) LoopWorklist . push_back ( SuccessorList ( InnerLoop ) ) ; else LoopWorklist . push_back ( SuccessorList ( Next ) ) ; } else { RewriteSuccs . insert ( Top . getBlock ( ) ) ; } continue ; } OnStack . erase ( Top . getBlock ( ) ) ; LoopWorklist . pop_back ( ) ; } if ( LLVM_LIKELY ( RewriteSuccs . empty ( ) ) ) return false ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; MachineBasicBlock * Dispatch = MF . CreateMachineBasicBlock ( ) ; MF . insert ( MF . end ( ) , Dispatch ) ; MLI . changeLoopFor ( Dispatch , Loop ) ; const auto & TII = * MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getInstrInfo ( ) ; MachineInstrBuilder MIB = BuildMI ( * Dispatch , Dispatch -> end ( ) , DebugLoc ( ) , TII . get ( <STR_LIT> ) ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; unsigned Reg = MRI . createVirtualRegister ( & <STR_LIT> ) ; MIB . addReg ( Reg ) ; DenseMap < MachineBasicBlock * , unsigned > Indices ; SmallVector < MachineBasicBlock * , <NUM_LIT> > SuccWorklist ( RewriteSuccs . begin ( ) , RewriteSuccs . end ( ) ) ; while ( ! SuccWorklist . empty ( ) ) { MachineBasicBlock * MBB = SuccWorklist . pop_back_val ( ) ; auto Pair = Indices . insert ( std :: make_pair ( MBB , <NUM_LIT> ) ) ; if ( ! Pair . second ) continue ; unsigned Index = MIB . getInstr ( ) -> getNumExplicitOperands ( ) - <NUM_LIT> ; LLVM_DEBUG ( dbgs ( ) << printMBBReference ( * MBB ) << <STR_LIT> << Index << <STR_LIT> ) ; Pair . first -> second = Index ; for ( auto Pred : MBB -> predecessors ( ) ) RewriteSuccs . insert ( Pred ) ; MIB . addMBB ( MBB ) ; Dispatch -> addSuccessor ( MBB ) ; MetaBlock Meta ( MBB ) ; for ( auto * Succ : Meta . successors ( ) ) if ( Succ != Header && ( ! Loop || Loop -> contains ( Succ ) ) ) SuccWorklist . push_back ( Succ ) ; } for ( MachineBasicBlock * MBB : RewriteSuccs ) { DenseMap < MachineBasicBlock * , MachineBasicBlock * > Map ; for ( auto * Succ : MBB


<s> addPass ( create<ISA_LIT>DelaySlotFillerPass ( get<ISA_LIT>TargetMachine ( ) ) ) ; return true


<s> switch ( I -> Opcode ) { default : llvm_unreachable ( <STR_LIT> ) ; break ; case <STR_LIT> : case <STR_LIT> : MIBS . push_back ( BuildMI ( MBB , MBBI , MI . getDebugLoc ( ) , TII -> get ( I -> Opcode ) ) . add ( MI . getOperand ( <NUM_LIT> ) ) . addReg ( BitSize == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ) . addImm ( I -> Op2 ) ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { bool DstIsDead = MI . getOperand ( <NUM_LIT> ) . isDead ( ) ; MIBS . push_back ( BuildMI ( MBB , MBBI , MI . getDebugLoc ( ) , TII -> get ( I -> Opcode ) ) . addReg ( DstReg , RegState

:: Define | getDeadRegState ( DstIsDead && LastItem ) ) . addImm ( I -> Op1 ) . addImm ( I -> Op2 ) ) ;


Zeroable , Subtarget , DAG ) ) return PSHUFB ;


<s> static SDValue convertValVTToLocVT ( SelectionDAG & DAG , SDValue Val , const CCValAssign & VA , const SDLoc & DL ) { EVT LocVT = VA . getLocVT ( ) ; switch ( VA . getLocInfo ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case CCValAssign :: Full : break ; case CCValAssign :: BCvt : Val = DAG . getNode ( <STR_LIT>


<s> fprintf ( init_file , <STR_LIT> ) ; fprintf ( init_file , <STR_LIT> ) ; fprintf ( init_file , <STR_LIT> ) ; write_bif_static_init ( ) ; write_ovld_static_init ( ) ; fprintf ( init_file , <STR_LIT> ) ; fprintf ( init_file , <STR_LIT> ) ; fprintf ( init_file , <STR_LIT> ) ; fprintf ( init_file , <STR_LIT> ) ; rbt_inorder_callback ( & fntype_rbt , fntype_rbt . rbt_root , write_fntype_init ) ; fprintf ( init_file , <STR_LIT> ) ; fprintf ( init_file , <STR_LIT> ) ; fprintf ( init_file , <STR_LIT> ) ; fprintf ( init_file , <STR_LIT> ) ; write_init_bif_table ( ) ; write_init_ovld_table ( ) ; fprintf ( init_file


<s> else { return BuildMI ( MBB , MBBI , DL , get ( LowLowOpcode ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) | getUndefRegState ( UndefSrc ) ) ; } unsigned Rotate = ( DestIsHigh != SrcIsHigh ? <NUM_LIT> : <NUM_LIT> ) ; return BuildMI ( MBB , MBBI , DL , get ( Opcode ) , DestReg ) . addReg ( DestReg , RegState :: Undef ) . addReg ( SrcReg , getKillRegState ( KillSrc ) | getUndefRegState (

UndefSrc ) ) . addImm ( <NUM_LIT> - Size ) . addImm ( <NUM_LIT> + <NUM_LIT> ) . addImm ( Rotate ) ;


) _mm_setzero_ps ( ) , ( __mmask8 ) - <NUM_LIT> ) ;


<s> switch ( OpSize ) { case <NUM_LIT> : return isStore ? <STR_LIT> : <STR_LIT> ; case <NUM_LIT> : return isStore ? <STR_LIT> : <STR_LIT> ; case <NUM_LIT> : return isStore ? <STR_LIT> : <STR_LIT> ; case <NUM_LIT> : return isStore ? <STR_LIT> : <STR_LIT> ; } } ; return GenericOpc


<s> Op -> SysCRImm . Val = Val ; Op -> StartLoc = S ; Op -> EndLoc = E ; return


<s> llvm_unreachable ( <NUM_LIT> ) ; } case <STR_LIT> : unsigned VReg = RegInfo . createVirtualRegister ( & <STR_LIT> ) ; RegInfo . addLiveIn ( VA . getLocReg ( ) , VReg ) ; SDValue ArgValue = DAG . getCopyFromReg ( Chain , dl , VReg , RegVT ) ; if ( VA . getLocInfo ( ) == CCValAssign :: SExt ) ArgValue = DAG . getNode ( <STR_LIT> , dl , RegVT , ArgValue , DAG . getValueType ( VA . getValVT ( ) ) ) ; else if ( VA . getLocInfo ( ) == CCValAssign :: ZExt ) ArgValue = DAG . getNode ( <STR_LIT> , dl , RegVT , ArgValue , DAG . getValueType ( VA . getValVT ( ) ) ) ; if ( VA . getLocInfo ( ) != CCValAssign :: Full ) ArgValue = DAG . getNode ( <STR_LIT> , dl , VA . getValVT ( ) , ArgValue ) ; InVals . push_back ( ArgValue ) ; } } else { assert ( VA . isMemLoc ( ) ) ; SDValue InVal ; <STR_LIT> Flags = Ins [ i ] . Flags ; if ( Flags . isByVal ( ) ) { int FI = MFI -> CreateFixedObject ( Flags . getByValSize ( ) , VA . getLocMemOffset ( ) , true ) ; InVal = DAG . getFrameIndex ( FI , getPointerTy ( ) ) ; } else { unsigned ObjSize = VA . getLocVT ( ) . getSizeInBits ( ) / <NUM_LIT> ; if ( ObjSize > <NUM_LIT> ) { errs ( ) << <STR_LIT> << EVT ( VA . getLocVT ( ) ) . getEVTString ( ) << <STR_LIT> ; } int FI = MFI -> CreateFixedObject ( ObjSize , VA . getLocMemOffset ( ) , true ) ; SDValue FIN = DAG . getFrameIndex ( FI , <STR_LIT> ) ; InVal = DAG . getLoad ( VA . getLocVT ( ) , dl , Chain , FIN , MachinePointerInfo :: getFixedStack ( FI ) , false , false ,


<s> OperandMatchResultTy parseFP128 ( OperandVector


<s> static bool isNot ( const MachineRegisterInfo & MRI , const MachineInstr & MI ) { if ( MI . getOpcode ( ) != TargetOpcode :: G_XOR ) return false ; auto ConstVal = getConstantVRegVal ( MI . getOperand ( <NUM_LIT> ) . getReg (


<s> SDValue Chain = N -> getOperand ( <NUM_LIT> ) ; SDValue Dest = N -> getOperand ( <NUM_LIT> ) ; SDValue EFLAGS = N -> getOperand ( <NUM_LIT> ) ; <STR_LIT> CC = <STR_LIT> ( N -> getConstantOperandVal ( <NUM_LIT> ) ) ; if ( SDValue Flags = checkBoolTestSetCCCombine ( EFLAGS , CC ) ) { SDValue Cond = DAG . getConstant ( CC , DL ,


<s> static MCAsmBackend * createAsmBackend ( const Target & , const MCSubtargetInfo & STI , const

MCRegisterInfo & , const MCTargetOptions & ) {


<s> InstructionCost <ISA_LIT>TTIImpl :: getShuffleCost ( TTI :: ShuffleKind Kind , Type * Tp , ArrayRef < int > Mask , int Index , Type * SubTp , ArrayRef < Value * > Args ) { InstructionCost CostFactor = vectorCostAdjustmentFactor ( Instruction :: ShuffleVector , Tp , nullptr ) ; if ( ! CostFactor . isValid ( ) ) return InstructionCost :: getMax


<s> { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , {


<s> TargetRegistry :: RegisterMCInstrInfo ( The<ISA_LIT>Target , create<ISA_LIT>MCInstrInfo ) ; TargetRegistry :: RegisterMCRegInfo ( The<ISA_LIT>Target , create<ISA_LIT>MCRegisterInfo ) ; TargetRegistry :: RegisterMCSubtargetInfo ( The<ISA_LIT>Target , create<ISA_LIT>MCSubtargetInfo ) ; TargetRegistry :: RegisterMCInstPrinter ( The<ISA_LIT>Target , create<ISA_LIT>MCInstPrinter ) ; TargetRegistry :: RegisterMCCodeEmitter ( The<ISA_LIT>Target , create<ISA_LIT>MCCodeEmitter ) ; TargetRegistry :: RegisterMCAsmBackend ( The<ISA_LIT>Target ,


<s> return RefA && RefA -> getKind ( ) == MCSymbolRefExpr ::


<s> unsigned CmpOpcode = Ty -> isFPOrFPVectorTy ( ) ? Instruction :: FCmp : Instruction :: ICmp ; LegalizationCost = getCmpSelInstrCost ( CmpOpcode , LegalVTy , LegalVTy , CmpInst :: BAD_ICMP_PREDICATE , CostKind ) + getCmpSelInstrCost ( Instruction :: Select , LegalVTy , LegalVTy , CmpInst :: BAD_ICMP_PREDICATE , CostKind ) ; LegalizationCost *= LT . first - <NUM_LIT> ; } return LegalizationCost + <NUM_LIT>


<s> static void MoveBelowOrigChain ( SelectionDAG * CurDAG , SDValue Load , SDValue Call , SDValue OrigChain ) { SmallVector < SDValue , <NUM_LIT> > Ops ; SDValue Chain = OrigChain . getOperand ( <NUM_LIT> ) ; if ( Chain . getNode ( ) == Load . getNode ( ) ) Ops . push_back ( Load . getOperand ( <NUM_LIT> ) ) ; else { assert ( Chain . getOpcode ( ) == <STR_LIT> && <STR_LIT> ) ; for ( unsigned i = <NUM_LIT> , e = Chain . getNumOperands ( ) ; i != e ; ++ i ) if ( Chain . getOperand ( i ) . getNode ( ) == Load . getNode ( ) ) Ops . push_back ( Load . getOperand ( <NUM_LIT> ) ) ; else Ops . push_back ( Chain .


<s> DebugLoc DL = MI . getDebugLoc ( ) ; unsigned LL , SC , AND , XOR , ZERO , BEQ ; LL = <STR_LIT> ; SC = <STR_LIT> ; AND = <STR_LIT> ; XOR = <STR_LIT> ; ZERO = <STR_LIT> ; BEQ = <STR_LIT> ; unsigned OldVal = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Ptr = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Incr = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned StoreVal = RegInfo . createVirtualRegister ( RC ) ; unsigned AndRes = RegInfo . createVirtualRegister ( RC ) ; unsigned AndRes2 = RegInfo . createVirtualRegister ( RC ) ; unsigned Success = RegInfo . createVirtualRegister ( RC ) ; const BasicBlock * LLVM_BB = BB -> getBasicBlock ( ) ; MachineBasicBlock * loopMBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * exitMBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineFunction :: iterator It = ++ BB -> getIterator ( ) ; MF -> insert ( It , loopMBB ) ; MF -> insert ( It , exitMBB ) ; exitMBB -> splice ( exitMBB -> begin ( ) , BB , std :: next ( MachineBasicBlock :: iterator ( MI ) ) , BB -> end ( ) ) ; exitMBB -> transferSuccessorsAndUpdatePHIs ( BB ) ; BB -> addSuccessor ( loopMBB ) ; loopMBB -> addSuccessor ( loopMBB ) ; loopMBB -> addSuccessor ( exitMBB ) ; BB = loopMBB ; BuildMI ( BB , DL , TII -> get ( LL ) , OldVal ) . addReg ( Ptr ) . addImm ( <NUM_LIT> ) ; if ( Nand ) { BuildMI ( BB , DL , TII -> get ( AND ) , AndRes ) . addReg ( OldVal ) . addReg ( Incr ) ; BuildMI ( BB , DL , TII -> get ( XOR ) , StoreVal ) . addReg ( ZERO ) . addReg ( AndRes ) ; BuildMI ( BB , DL , TII -> get ( XOR ) , AndRes2 ) . addReg ( ZERO ) . addReg ( AndRes ) ; } else if ( BinOpcode ) { BuildMI ( BB , DL , TII -> get ( BinOpcode ) , StoreVal ) . addReg ( OldVal ) . addReg ( Incr ) ; } else


<s> if ( extra_frame_size ) { complex_prologue = <NUM_LIT> ; if ( TARGET_A16 ) F ( emit_insn ( gen_addhi3 ( gen_rtx_REG ( HImode , SP_REGNO ) , gen_rtx_REG ( HImode , SP_REGNO ) , GEN_INT ( - extra_frame_size ) ) ) ) ; else F ( emit_insn ( gen_addpsi3 ( gen_rtx_REG ( PSImode , SP_REGNO ) , gen_rtx_REG ( PSImode , SP_REGNO ) , GEN_INT ( - extra_frame_size ) ) ) ) ; } complex_prologue += m32c_pushm_popm ( PP_pushm ) ; if ( complex_prologue ) emit_insn


<s> for ( unsigned i = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i ) { Chain = DAG . getCopyFromReg ( Chain , dl , RVLocs [ i ] . getLocReg ( ) , RVLocs [ i ] . getValVT ( ) , InFlag ) . getValue ( <NUM_LIT> ) ; InFlag = Chain . getValue ( <NUM_LIT>


<s> return isMem ( RegKind , HasIndex ) && inRange ( Mem . Disp , - <NUM_LIT> ,


<s> if ( a >= ( float ) <NUM_LIT> ) return (


<s> if ( AsmPieces . size ( ) == <NUM_LIT> || AsmPieces . size ( ) == <NUM_LIT> ) { if ( std :: count ( AsmPieces . begin ( ) , AsmPieces . end ( ) , <STR_LIT> ) && std :: count ( AsmPieces . begin ( ) , AsmPieces . end ( ) , <STR_LIT> ) && std :: count ( AsmPieces . begin ( )


<s> MVT ShufVT = V . getValueType ( ) . getSimpleVT ( ) ; unsigned NumElems = ShufVT . getVectorNumElements ( ) ; SmallVector < int , <NUM_LIT> > ShuffleMask ; SDValue ImmN ; bool IsUnary ; if ( ! getTargetShuffleMask ( N , ShufVT , ShuffleMask , IsUnary ) ) return SDValue ( ) ; int Elt = ShuffleMask [ Index ] ; if ( Elt < <NUM_LIT> ) return DAG . getUNDEF ( ShufVT . getVectorElementType ( ) ) ; SDValue NewV = ( Elt < ( int ) NumElems ) ? N -> getOperand ( <NUM_LIT> ) : N -> getOperand ( <NUM_LIT> ) ; return getShuffleScalarElt ( NewV . getNode ( ) , Elt % NumElems , DAG , Depth + <NUM_LIT> ) ; } if ( Opcode == <STR_LIT> ) { V = V . getOperand ( <NUM_LIT> ) ; EVT SrcVT = V . getValueType ( ) ; unsigned NumElems = VT .


<s> bool can_be_rotated_to_negative_15bits ( HOST_WIDE_INT c ) { int rot = <NUM_LIT> ; bool res = can_be_rotated_to_lowbits ( ~ c , <NUM_LIT> , & rot ) ; return res && rot >


<s> pic_ref = gen_const_mem ( Pmode , gen_rtx_PLUS ( Pmode , pic_offset_table_rtx , address ) ) ; insn = emit_move_insn ( reg , pic_ref ) ; } set_unique_reg_note ( insn , REG_EQUAL , orig ) ; return reg ; } else if ( GET_CODE ( orig ) == CONST ) { rtx base , offset ; if ( GET_CODE ( XEXP ( orig , <NUM_LIT> ) ) == PLUS && sparc_pic_register_p ( XEXP ( XEXP ( orig , <NUM_LIT> ) , <NUM_LIT> ) ) ) return orig ; if ( ! reg ) { gcc_assert ( can_create_pseudo_p ( ) ) ; reg = gen_reg_rtx ( Pmode ) ; } gcc_assert ( GET_CODE ( XEXP ( orig , <NUM_LIT> ) ) == PLUS ) ; base = sparc_legitimize_pic_address ( XEXP ( XEXP ( orig , <NUM_LIT> ) , <NUM_LIT> ) , reg ) ; offset = sparc_legitimize_pic_address ( XEXP ( XEXP ( orig , <NUM_LIT> ) , <NUM_LIT> ) , base == reg ? NULL_RTX : reg ) ; if ( GET_CODE ( offset


<s> not_to_clear_mask = comp_not_to_clear_mask_str_un ( arg_type , & regno , padding_bits_to_clear , <NUM_LIT> , & last_used_bit ) ; if ( last_used_bit != <NUM_LIT> ) padding_bits_to_clear [ regno ] |= ( ( uint32_t ) - <NUM_LIT> ) - ( ( uint32_t ) <NUM_LIT> << last_used_bit ) + <NUM_LIT> ; else not_to_clear_mask &= ~ ( HOST_WIDE_INT_1U << regno ) ; } else { not_to_clear_mask = <NUM_LIT> ; if ( GET_MODE ( arg_rtx ) == BLKmode ) { int i , arg_regs ; rtx reg ; gcc_assert ( TARGET_HARD_FLOAT_ABI ) ; for ( i = <NUM_LIT> ; i < XVECLEN ( arg_rtx , <NUM_LIT> ) ; i ++ ) { reg = XEXP ( XVECEXP ( arg_rtx , <NUM_LIT> , i ) , <NUM_LIT> ) ; gcc_assert ( REG_P ( reg ) ) ; not_to_clear_mask |= HOST_WIDE_INT_1U << REGNO ( reg ) ; arg_regs = ARM_NUM_REGS ( GET_MODE ( reg ) ) ; if ( arg_regs > <NUM_LIT> ) { unsigned HOST_WIDE_INT mask ; mask = HOST_WIDE_INT_1U << ( REGNO ( reg ) + arg_regs ) ; mask -= HOST_WIDE_INT_1U << REGNO ( reg ) ; not_to_clear_mask |= mask ; } } } else { int arg_regs = ARM_NUM_REGS ( GET_MODE ( arg_rtx ) ) ; not_to_clear_mask |= HOST_WIDE_INT_1U << REGNO


<s> setLeastSignificantFirst ( VRegs ) ; if ( ! assignVRegs ( VRegs , ArgLocs , ArgLocsStartIndex , VT ) ) return false ; return true


<s> if ( ConstraintCode [ <NUM_LIT> ] == 'U' ) { switch ( ConstraintCode [ <NUM_LIT> ] ) { default : break ; case 'm' : return InlineAsm :: Constraint_Um ; case 'n' : return InlineAsm :: Constraint_Un ; case 'q' : return InlineAsm :: Constraint_Uq ; case 's' : return InlineAsm :: Constraint_Us ; case 't' : return InlineAsm :: Constraint_Ut ; case 'v' : return InlineAsm :: Constraint_Uv ; case 'y'


<s> MachineBasicBlock :: iterator I = MBBI ; for ( unsigned i = <NUM_LIT> ; i < MFI -> getCalleeSavedInfo ( ) . size ( ) ; ++ i ) -- I ; BuildMI ( MBB , I , dl , TII . get ( ADDu ) , SP ) . addReg ( FP ) . addReg ( ZERO ) ; } if ( <ISA_LIT>FI -> callsEhReturn ( ) ) { const TargetRegisterClass * RC = STI . isABI_N64 ( ) ? & <STR_LIT> : & <STR_LIT> ; MachineBasicBlock :: iterator I = MBBI ; for ( unsigned i = <NUM_LIT> ; i < MFI -> getCalleeSavedInfo ( ) . size ( ) ; ++


<s> if ( GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == PLUS && REG_P ( XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) ) && GET_CODE ( XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) ) == CONST_INT && ( INTVAL ( XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) ) <= MAX_LD_OFFSET ( GET_MODE ( x ) ) ) ) { rtx xx = XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) ; int regno = REGNO ( xx ) ; ok = ( regno >= FIRST_PSEUDO_REGISTER || regno == REG_Z || regno

== REG_Y || xx == frame_pointer_rtx || xx == arg_pointer_rtx ) ;


<s> SDValue <ISA_LIT>TargetLowering :: lowerFABS ( SDValue Op , SelectionDAG & DAG ) const { if ( Subtarget -> has<ISA_LIT>64 ( ) && ( Op . getValueType ( ) == <STR_LIT> ) ) return lowerFABS64 ( Op , DAG , Subtarget -> hasExtractInsert ( ) ) ; return lowerFABS32 ( Op , DAG , Subtarget -> hasExtractInsert


<s> MCSubtargetInfo STI = getSubtargetInfo ( ) ; MCInst TmpInst ; MCInstLowering . Lower ( MI , TmpInst ) ; OutStreamer -> emitInstruction ( TmpInst , STI


<s> for ( unsigned int i = <NUM_LIT> ; i < TARGET_FPU_auto ; i ++ ) { arm_initialize_isa ( fpubits , all_fpus [ i ] . isa_bits ) ; bitmap_and_compl ( tmpset , isa_all_fpubits_internal , fpubits ) ; bitmap_clear ( isa_all_fpubits_internal ) ; bitmap_copy ( isa_all_fpubits_internal , tmpset ) ; } if ( ! bitmap_empty_p ( isa_all_fpubits_internal ) ) { fprintf ( stderr , <STR_LIT> <STR_LIT> <STR_LIT> ) ; ASSERT_TRUE ( bitmap_empty_p ( isa_all_fpubits_internal


<s> if ( const GlobalValue * GV = dyn_cast < GlobalValue > ( V ) ) { Addr . setGlobalValue ( GV ) ; return true ; } return false


<s> if ( InputLoad -> getOpcode ( ) == <STR_LIT> ) InputLoad = & InputLoad -> getOperand ( <NUM_LIT> ) ; if ( InputLoad -> getOpcode ( ) == <STR_LIT> || InputLoad -> getOpcode ( ) == <STR_LIT> ) InputLoad = & InputLoad -> getOperand ( <NUM_LIT> ) ; if ( InputLoad -> getOpcode ( ) != <STR_LIT> ) return nullptr ; LoadSDNode * LD = cast < LoadSDNode > ( * InputLoad ) ; return <STR_LIT> ( LD ) ? InputLoad :


<s> bool <ISA_LIT>InstrInfo :: isBranchOffsetInRange ( unsigned BranchOp , int64_t BrOffset ) const { switch ( BranchOp ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : assert ( BrOffset >= <NUM_LIT> && <STR_LIT>


<s> } else { assert ( ( - ( Offset + StackSize ) ) % MFI -> getObjectAlignment ( FI ) == <NUM_LIT> ) ; return Offset + StackSize ; } } else if ( RegInfo -> needsStackRealignment ( MF ) ) { if ( FI < <NUM_LIT> ) { return Offset + RegInfo -> getSlotSize ( ) ; } else { assert ( ( - ( Offset + StackSize ) ) % MFI -> getObjectAlignment ( FI ) == <NUM_LIT> ) ; return Offset


<s> const MachineOperand & MO = MI -> getOperand ( I ) ; unsigned Reg ; if ( ! MO . isReg ( ) || ! ( Reg = MO . getReg ( ) ) ) continue ; if ( MO . isDef ( ) ) RegDefs . insert ( Reg ) ; else if ( MO . isUse ( ) )


<s> LoopTailMBB -> addSuccessor ( DoneMBB ) ; LoopTailMBB -> addSuccessor ( LoopHeadMBB ) ; DoneMBB -> splice ( DoneMBB -> end ( ) , & MBB , MI , MBB . end ( ) ) ; DoneMBB -> transferSuccessors ( & MBB ) ; MBB . addSuccessor ( LoopHeadMBB ) ; unsigned DestReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned ScratchReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned AddrReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned CmpValReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned NewValReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; AtomicOrdering Ordering = static_cast < AtomicOrdering > ( MI . getOperand ( IsMasked ? <NUM_LIT> : <NUM_LIT> ) . getImm ( ) ) ; if ( ! IsMasked ) { BuildMI ( LoopHeadMBB , DL , TII -> get ( getLRForRMW32 ( Ordering ) ) , DestReg ) . addReg ( AddrReg ) ; BuildMI ( LoopHeadMBB , DL , TII -> get ( <STR_LIT> ) ) . addReg ( DestReg ) . addReg ( CmpValReg ) . addMBB ( DoneMBB ) ; BuildMI ( LoopTailMBB , DL , TII -> get ( getSCForRMW32 ( Ordering ) ) , ScratchReg ) . addReg ( AddrReg ) . addReg ( NewValReg ) ; BuildMI ( LoopTailMBB , DL , TII -> get ( <STR_LIT> ) ) . addReg ( ScratchReg ) . addReg ( <STR_LIT>


<s> static unsigned decodeSB ( uint32_t insn ) { switch ( ( insn >> <NUM_LIT> ) & <NUM_LIT> ) { default : return UNSUPPORTED ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return


<s> BuildMI ( * I . getParent ( ) , I , I . getDebugLoc ( ) , TII . get ( TargetOpcode :: COPY ) , SubRegCopy ) . addUse ( CopyReg , <NUM_LIT> , SubReg ) ; MachineOperand & RegOp = I . getOperand ( <NUM_LIT> ) ; RegOp . setReg ( SubRegCopy ) ; if ( ! TargetRegisterInfo :: isPhysicalRegister ( I . getOperand ( <NUM_LIT> ) . getReg ( ) ) ) RBI . constrainGenericRegister ( I . getOperand ( <NUM_LIT> ) . getReg ( ) , * To , MRI ) ; return true


<s> SDLoc dl ( Op ) ; bool isSRA = Op . getOpcode ( ) == <STR_LIT> ; SDValue ShOpLo = Op . getOperand ( <NUM_LIT> ) ; SDValue ShOpHi = Op . getOperand ( <NUM_LIT> ) ; SDValue ShAmt = Op . getOperand ( <NUM_LIT> ) ; SDValue SafeShAmt = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , ShAmt , DAG . getConstant ( VTBits - <NUM_LIT> , <STR_LIT> ) ) ; SDValue Tmp1 = isSRA ? DAG . getNode ( <STR_LIT> , dl , VT , ShOpHi , DAG . getConstant ( VTBits - <NUM_LIT> , <STR_LIT> ) ) : DAG . getConstant ( <NUM_LIT> , VT ) ; SDValue Tmp2 , Tmp3 ; if ( Op . getOpcode ( ) == <STR_LIT> ) { Tmp2 = DAG . getNode ( <STR_LIT> , dl , VT , ShOpHi , ShOpLo , ShAmt ) ; Tmp3 = DAG . getNode ( <STR_LIT> , dl , VT , ShOpLo , SafeShAmt ) ; } else { Tmp2 = DAG . getNode ( <STR_LIT> , dl , VT , ShOpLo , ShOpHi , ShAmt ) ; Tmp3 = DAG . getNode ( isSRA ? <STR_LIT> : <STR_LIT> , dl , VT , ShOpHi , SafeShAmt ) ; } SDValue AndNode = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , ShAmt , DAG . getConstant ( VTBits , <STR_LIT> ) ) ; SDValue Cond = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , AndNode , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDValue Hi , Lo ; SDValue CC = DAG . getConstant ( <STR_LIT> , <STR_LIT> ) ; SDValue Ops0 [ <NUM_LIT> ] = { Tmp2 , Tmp3 , CC , Cond } ; SDValue Ops1 [ <NUM_LIT> ] = { Tmp3 , Tmp1 , CC , Cond


<s> void printHex64ImmOperand ( const MachineInstr * MI


<s> if ( MO . isFI ( ) ) { const MachineFrameInfo & MFI = * MI -> getParent ( ) -> getParent ( ) -> getFrameInfo ( ) ; int Idx = MO . getIndex ( ) ; return MFI . isFixedObjectIndex ( Idx ) && MFI .


<s> bool <ISA_LIT>RegisterInfo :: isConstantPhysReg ( MCRegister PhysReg ) const { return PhysReg ==


<s> static int getLoadStoreMultipleOpcode ( int Opcode ) { switch ( Opcode ) { case <STR_LIT> : NumLDMGened ++ ; return <STR_LIT> ; case <STR_LIT> : NumSTMGened ++ ; return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : NumLDMGened ++ ; return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : NumSTMGened ++ ; return <STR_LIT> ; case <STR_LIT> : NumFLDMGened ++ ; return <STR_LIT> ; case <STR_LIT> : NumFSTMGened ++ ; return <STR_LIT> ; case <STR_LIT> : NumFLDMGened ++ ; return <STR_LIT> ; case <STR_LIT> : NumFSTMGened ++ ; return <STR_LIT>


<s> for ( unsigned i = <NUM_LIT> , e = CPUsers . size ( ) ; i != e ; ++ i ) CPChange |= handleConstantPoolUser ( i , NoCPIters >= CPMaxIteration / <NUM_LIT> ) ; if ( CPChange && ++ NoCPIters > CPMaxIteration ) report_fatal_error ( <STR_LIT> ) ; LLVM_DEBUG ( dumpBBs ( ) ) ; NewWaterList . clear ( ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << NoBRIters << '\n' ) ; bool BRChange = false ; for ( unsigned i = <NUM_LIT> , e = ImmBranches . size ( ) ; i != e ; ++ i ) BRChange |= fixupImmediateBr ( ImmBranches [ i ] ) ; if ( BRChange && ++ NoBRIters > <NUM_LIT> ) report_fatal_error ( <STR_LIT> ) ; LLVM_DEBUG ( dumpBBs ( ) ) ; if ( ! CPChange && ! BRChange ) break ; MadeChange = true ; } if ( isThumb2 && ! STI -> prefers32BitThumb ( ) ) MadeChange |= optimizeThumb2Instructions ( ) ; if ( isThumb && STI -> hasV8MBaselineOps ( ) ) MadeChange |= optimizeThumb2Branches ( ) ; if ( GenerateTBB && ! STI -> genExecuteOnly ( ) ) MadeChange |= optimizeThumb2JumpTables ( ) ; verify ( ) ; for ( unsigned i = <NUM_LIT> , e = CPEntries . size ( ) ; i != e ; ++ i ) { for ( unsigned j = <NUM_LIT> , je = CPEntries [ i ] . size ( ) ; j != je ; ++ j ) { const CPEntry & CPE = CPEntries [ i ] [ j ] ; if ( CPE . CPEMI && CPE . CPEMI -> getOperand ( <NUM_LIT> ) . isCPI ( ) ) AFI -> recordCPEClone ( i , CPE . CPI ) ; } } LLVM_DEBUG ( dbgs ( ) << '\n' ; dumpBBs ( ) ) ; BBUtils -> clear ( ) ; WaterList . clear ( ) ; CPUsers . clear ( ) ; CPEntries . clear ( ) ; JumpTableEntryIndices . clear ( ) ; JumpTableUserIndices . clear


<s> return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; case <NUM_LIT> : return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; } case 'v' : switch ( VT . getSizeInBits ( ) ) { default : return std :: make_pair ( <NUM_LIT> , nullptr ) ; case <NUM_LIT> : return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; case <NUM_LIT> : return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; case <NUM_LIT> : return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; case <NUM_LIT> : return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; case <NUM_LIT> : return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; case <NUM_LIT> : return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; } } } if ( Constraint . size ( ) > <NUM_LIT> ) { const TargetRegisterClass * RC = nullptr ; if ( Constraint [ <NUM_LIT> ] == 'v' ) { RC = & <STR_LIT> ; } else if ( Constraint [ <NUM_LIT> ] == 's' ) { RC = & <STR_LIT> ; } if ( RC ) { uint32_t Idx ; bool Failed = Constraint . substr ( <NUM_LIT> ) . getAsInteger ( <NUM_LIT> , Idx ) ; if ( ! Failed && Idx < RC -> getNumRegs ( ) ) return

std :: make_pair ( RC -> getRegister ( Idx ) , RC ) ;


<s> if ( I -> getOpcode ( ) != <STR_LIT> ) Latency += getInstrLatency ( ItinData , I , PredCost ) ; } return Latency ; } const MCInstrDesc & MCID = MI -> getDesc ( ) ; unsigned Class = MCID . getSchedClass ( ) ; unsigned UOps = ItinData -> Itineraries [ Class ] . NumMicroOps ; if ( PredCost && MCID . hasImplicitDefOfPhysReg ( <STR_LIT> ) ) * PredCost = <NUM_LIT> ; if ( UOps ) return ItinData -> getStageLatency


<s> static bool tilegx_return_in_msb ( const_tree valtype ) { return ( TARGET_BIG_ENDIAN && AGGREGATE_TYPE_P (


<s> int Offset = <NUM_LIT> ; const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; assert ( ! MFI -> hasVarSizedObjects ( ) ) ; if ( MFI -> getNumObjects ( ) == <NUM_LIT>


<s> for ( unsigned i = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i ) { Chain = DAG . getCopyFromReg ( Chain , dl , RVLocs [ i ] . getLocReg ( ) , RVLocs [ i ] . getValVT ( ) , InFlag ) . getValue ( <NUM_LIT> ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; InVals . push_back ( Chain . getValue ( <NUM_LIT> ) ) ; } return Chain


<s> <ISA_LIT>EnsureAlignment ( <ISA_LIT>TargetMachine & tm ) : MachineFunctionPass ( ID ) { const <ISA_LIT>Subtarget * PST = tm . getSubtargetImpl ( ) ; MinSubfunctionAlignment = PST -> getMinSubfunctionAlignment ( ) . value


<s> Width = <NUM_LIT> ; Scale = <NUM_LIT> ; MinOffset = - <NUM_LIT> ; MaxOffset = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Width = <NUM_LIT> ; Scale = <NUM_LIT> ; MinOffset = - <NUM_LIT> ; MaxOffset = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Scale = <NUM_LIT> ; Width = <NUM_LIT> ; MinOffset = - <NUM_LIT> ; MaxOffset = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : Scale = Width = <NUM_LIT> ; MinOffset = <NUM_LIT> ; MaxOffset = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Scale = <NUM_LIT> ; Width = <NUM_LIT> ; MinOffset = - <NUM_LIT> ; MaxOffset = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Scale = Width = <NUM_LIT> ; MinOffset = <NUM_LIT> ; MaxOffset = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Scale = <NUM_LIT> ; Width = <NUM_LIT> ; MinOffset = - <NUM_LIT> ; MaxOffset = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Scale = Width = <NUM_LIT> ; MinOffset = <NUM_LIT> ; MaxOffset = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Scale = Width = <NUM_LIT> ; MinOffset = <NUM_LIT> ; MaxOffset =


<s> if ( SUBTARGET_FRAME_POINTER_REQUIRED ) return true ; if ( TARGET_32BIT_MS_ABI && cfun -> calls_setjmp ) return true ; if ( TARGET_64BIT_MS_ABI && get_frame_size (


<s> eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { llvm_unreachable ( <STR_LIT>


<s> void <ISA_LIT>MCInstLower :: Lower ( const MachineInstr * MI , MCInst & OutMI ) const { OutMI . setOpcode ( MI


<s> <ISA_LIT>Operand * Op = new <ISA_LIT>Operand ( Memory ) ; Op -> Mem . Base = Base ; Op -> Mem . OffReg = Off ; Op -> Mem . Off = <NUM_LIT> ; Op -> StartLoc = S ; Op -> EndLoc = E


<s> if ( ! C ) return SDValue ( ) ; SDValue Scale = DAG . getTargetConstant ( C -> getZExtValue ( ) , dl , <STR_LIT> ) ; SDValue Disp = DAG . getTargetConstant ( <NUM_LIT> , dl , <STR_LIT> ) ; SDValue Segment = DAG . getRegister ( <NUM_LIT> , <STR_LIT> ) ; MVT MaskVT = <STR_LIT> ( <STR_LIT> , Index . getSimpleValueType ( ) . getVectorNumElements ( ) ) ; SDValue VMask = getMaskNode ( Mask , MaskVT , Subtarget , DAG , dl ) ; SDVTList VTs = DAG . getVTList ( MaskVT , <STR_LIT> ) ; SDValue Ops [ ] = { Base , Scale , Index , Disp , Segment , VMask , Src , Chain } ; SDNode * Res = DAG . getMachineNode ( Opc , dl , VTs , Ops ) ; return SDValue ( Res ,


<s> unsigned BaseReg ( <STR_LIT> . getRegister ( BaseIdx ) ) ; return getMatchingSuperReg ( BaseReg , <STR_LIT> , &


<s> unsigned getMaximumUnrollFactor ( ) const


<s> RegisterAsmPrinter < <ISA_LIT>AsmPrinter > X (


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> - <NUM_LIT> - ( TFI -> hasFP ( MF ) || TT . isOSDarwin ( ) ) - ( TT . isOSDarwin ( ) || ReserveX18 ) - hasBasePointer ( MF ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case


<s> initializeEnvironment ( ) ; initSubtargetFeatures ( CPU , FS )


<s> int64_t Val = Memory . OffsetImm -> getValue ( ) ; return Val >= <NUM_LIT> && Val <= <NUM_LIT> && ( Val &


<s> static std :: pair < const TargetRegisterClass * , const TargetRegisterClass * > getCopyRegClasses ( const MachineInstr & Copy , const <ISA_LIT>RegisterInfo & TRI , const MachineRegisterInfo & MRI ) { unsigned DstReg = Copy . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned SrcReg = Copy . getOperand ( <NUM_LIT> ) . getReg ( ) ; const TargetRegisterClass * SrcRC = TargetRegisterInfo :: isVirtualRegister ( SrcReg ) ? MRI . getRegClass ( SrcReg ) : TRI . getPhysRegClass (


<s> int32_t Imm = SignExtend32 < Bits > ( Value ) * ScaleBy ; Inst . addOperand ( MCOperand :: createImm ( Imm + Offset ) ) ; return MCDisassembler :: Success


<s> <ISA_LIT>Operand * Op = new <ISA_LIT>Operand ( Token ) ; Op -> Tok . Data = Str . data ( ) ; Op -> Tok . Length = Str . size ( ) ; Op -> StartLoc = S ; Op -> EndLoc = S


<s> bool shouldBuildLookupTablesForConstant ( Constant * C ) const { if ( ST -> isROPI ( ) || ST -> isRWPI ( ) ) return ! C -> needsDynamicRelocation


<s> Ild . the_slotID = <STR_LIT> ; Ild . the_operandID = <STR_LIT> ; Ild . the_idxDst0 = false ; Ild . the_isOpTypeFloat = false ; Ild . the_isIRFDest = false ; Ild . the_isVectorPipe =


<s> EVT <ISA_LIT>TargetLowering :: getSetCCResultType ( LLVMContext & , EVT VT ) const { if ( ! VT . isVector ( ) ) return Subtarget -> hasAVX512 ( ) ? <STR_LIT> : <STR_LIT> ; if ( Subtarget -> hasAVX512 ( ) ) switch ( VT . getVectorNumElements ( ) ) { case <NUM_LIT> : return


<s> void <ISA_LIT>InstPrinter :: printBTIHintOp ( const MCInst * MI , unsigned OpNum , const MCSubtargetInfo & STI , raw_ostream & O ) { unsigned btihintop = ( MI -> getOperand ( OpNum ) . getImm ( ) ^ <NUM_LIT> ) >> <NUM_LIT> ; auto BTI = <STR_LIT> ( btihintop ) ; if ( BTI ) O << BTI -> Name ; else O << '#' << formatImm ( btihintop


<s> } else if ( Op . getValueType ( ) == <STR_LIT> ) { if ( Src . getValueType ( ) == <STR_LIT> ) { if ( Subtarget -> hasGaudiISA ( ) ) { SDValue S0Val = helperExtractSubRegSDValue ( <STR_LIT> , DL , DAG , <STR_LIT> , Src ) ; SDValue S1Val = helperExtractSubRegSDValue ( <STR_LIT> , DL , DAG , <STR_LIT> , Src ) ; SDValue S2Val = helperExtractSubRegSDValue ( <STR_LIT> , DL , DAG , <STR_LIT> , Src ) ; SDValue S3Val = helperExtractSubRegSDValue ( <STR_LIT> , DL , DAG , <STR_LIT> , Src ) ; SDValue Src0 = helperConvertvvpNodeCreate ( S0Val , DL , DAG , <ISA_LIT>II :: OpType :: FP32 , InputSwitch | <ISA_LIT>II :: SW_TO_BF16 , <STR_LIT> ) ; SDValue Src1 = helperConvertvvpNodeCreate ( S1Val , DL , DAG , <ISA_LIT>II :: OpType :: FP32 , InputSwitch | <ISA_LIT>II :: SW_TO_BF16 , <STR_LIT> ) ; SDValue Src2 = helperConvertvvpNodeCreate ( S2Val , DL , DAG , <ISA_LIT>II :: OpType :: FP32 , InputSwitch | <ISA_LIT>II :: SW_TO_BF16 , <STR_LIT> ) ; SDValue Src3 = helperConvertvvpNodeCreate ( S3Val , DL , DAG , <ISA_LIT>II :: OpType :: FP32 , InputSwitch | <ISA_LIT>II :: SW_TO_BF16 , <STR_LIT> ) ; SDValue mdg0 , mdg1 ; if ( Subtarget -> hasGaudiISA ( ) ) { mdg0 = truncate_32_to_16 ( DAG , Src0 , Src1 , DL , <STR_LIT> , <ISA_LIT>II :: OpType :: BF16 ) ; mdg1 = truncate_32_to_16 ( DAG , Src2 , Src3 , DL , <STR_LIT> , <ISA_LIT>II :: OpType :: BF16 ) ; } else { mdg0 = truncate_32_to_16_goya ( DAG , Src0 , Src1 , DL , <STR_LIT> , <ISA_LIT>II :: OpType :: BF16 ) ; mdg1 = truncate_32_to_16_goya ( DAG , Src2 , Src3 , DL , <STR_LIT> , <ISA_LIT>II :: OpType :: BF16 ) ; } return createTuple ( { mdg0 , mdg1 } , DAG ) ; } else { llvm_unreachable ( <STR_LIT>


<s> static rtx rx_expand_int_builtin_1_arg ( rtx arg , rtx target , rtx ( * gen_func ) ( rtx , rtx ) , bool mem_ok ) { if ( ! REG_P ( arg ) ) if ( ! mem_ok || ! MEM_P ( arg ) ) arg = force_reg ( SImode , arg ) ; if ( target == NULL_RTX || ! REG_P ( target ) ) target = gen_reg_rtx ( SImode ) ; emit_insn ( gen_func ( target , arg


<s> } assert ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> && <STR_LIT> ) ; unsigned STOpc = ( Opcode == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; MI . setDesc ( TII . get ( STOpc ) ) ; MI . getOperand ( <NUM_LIT> ) . setReg ( FP ) ; I =


<s> if ( ExtraCode [ <NUM_LIT> ] != <NUM_LIT> ) return true ; switch ( ExtraCode [ <NUM_LIT> ] ) { default : return true ; case 'c' : break ; case 'L' : if ( ! MI -> getOperand ( OpNo ) . isReg ( ) || OpNo + <NUM_LIT> == MI -> getNumOperands ( ) || ! MI -> getOperand ( OpNo + <NUM_LIT> ) . isReg ( ) ) return true ; ++


<s> bool <ISA_LIT>FrameLowering :: hasFP ( const MachineFunction & MF ) const { if ( MF . getFunction ( ) -> hasFnAttribute ( Attribute :: Naked ) ) return false ; auto & MFI = MF . getFrameInfo ( ) ; auto & HRI = * MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getRegisterInfo ( ) ; bool HasExtraAlign = HRI . needsStackRealignment ( MF ) ; bool HasAlloca = MFI . hasVarSizedObjects ( ) ; if ( MF . getTarget ( ) . getOptLevel ( ) == CodeGenOpt :: None ) return true ; if ( HasAlloca || HasExtraAlign ) return true ; if ( MFI . getStackSize ( ) > <NUM_LIT> ) { const TargetMachine & TM = MF . getTarget ( ) ; if ( TM . Options . DisableFramePointerElim ( MF ) || ! EliminateFramePointer ) return true ; if ( EnableStackOVFSanitizer ) return true ; } const auto & HMFI = * MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; if ( MFI . hasCalls ( ) || HMFI . hasClobberLR ( ) )


<s> signedDecoder < <NUM_LIT> > ( MI , tmp , Decoder ) ; return MCDisassembler ::


<s> REAL_VALUE_FROM_CONST_DOUBLE ( r , op ) ; REAL_VALUE_TO_TARGET_SINGLE ( r , i ) ; return ! SPARC_SIMM13_P ( i )


directive , XCOFF_CSECT_DEFAULT_ALIGNMENT_STR ) ;


<s> static void addRegsToSet ( const <ISA_LIT>RegisterInfo & TRI , iterator_range < MachineInstr

:: const_mop_iterator > Ops , BitVector & Set ) {


<s> MachineFunction & MF = DAG . getMachineFunction ( ) ; EVT PtrVT = getPointerTy ( ) ; SmallVector < CCValAssign , <NUM_LIT> > ArgLocs ; CCState ArgCCInfo ( CallConv , IsVarArg , MF , TM , ArgLocs , * DAG . getContext ( ) ) ; ArgCCInfo . AnalyzeCallOperands ( Outs , CC_<ISA_LIT> ) ; if ( IsTailCall && ! canUseSiblingCall ( ArgCCInfo , ArgLocs ) ) IsTailCall = false ; unsigned NumBytes = ArgCCInfo . getNextStackOffset ( ) ; if ( ! IsTailCall ) Chain = DAG . getCALLSEQ_START ( Chain , DAG . getConstant ( NumBytes , PtrVT , true ) , DL ) ; SmallVector < std :: pair < unsigned , SDValue > , <NUM_LIT> > RegsToPass ; SmallVector < SDValue , <NUM_LIT> > MemOpChains ; SDValue StackPtr ; for ( unsigned I = <NUM_LIT> , E = ArgLocs . size ( ) ; I != E ; ++ I ) { CCValAssign & VA = ArgLocs [ I ] ; SDValue ArgValue = OutVals [ I ] ; if ( VA . getLocInfo ( ) == CCValAssign :: Indirect ) { SDValue SpillSlot = DAG . CreateStackTemporary ( VA . getValVT ( ) ) ; int FI = cast < FrameIndexSDNode > ( SpillSlot ) -> getIndex ( ) ; MemOpChains . push_back ( DAG . getStore ( Chain , DL , ArgValue , SpillSlot , MachinePointerInfo :: getFixedStack ( FI ) , false , false , <NUM_LIT> ) ) ; ArgValue = SpillSlot ; } else ArgValue = convertValVTToLocVT ( DAG , DL , VA , ArgValue ) ; if ( VA . isRegLoc ( ) ) RegsToPass . push_back ( std :: make_pair ( VA . getLocReg ( ) , ArgValue ) ) ; else { assert ( VA . isMemLoc ( ) && <STR_LIT> ) ; if ( ! StackPtr . getNode ( ) ) StackPtr = DAG . getCopyFromReg ( Chain , DL , <STR_LIT> , PtrVT ) ; unsigned Offset = <STR_LIT> + VA . getLocMemOffset ( ) ; if ( VA . getLocVT ( ) == <STR_LIT> || VA . getLocVT ( ) == <STR_LIT> ) Offset += <NUM_LIT> ; SDValue Address = DAG . getNode ( <STR_LIT> , DL , PtrVT , StackPtr , DAG . getIntPtrConstant ( Offset ) ) ; MemOpChains . push_back ( DAG . getStore ( Chain , DL , ArgValue , Address , MachinePointerInfo ( ) , false , false , <NUM_LIT> ) ) ; } } if ( ! MemOpChains . empty ( ) ) Chain = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , & MemOpChains [ <NUM_LIT> ] , MemOpChains . size ( ) ) ; SDValue Glue ; if ( GlobalAddressSDNode * G = dyn_cast < GlobalAddressSDNode > ( Callee ) ) { Callee = DAG . getTargetGlobalAddress ( G -> getGlobal (


<s> const char * name , * prefix ; char * string ; name = IDENTIFIER_POINTER ( DECL_ASSEMBLER_NAME ( decl ) ) ; name = i386_pe_strip_name_encoding_full ( name ) ; if ( TREE_CODE ( decl ) == FUNCTION_DECL ) prefix = <STR_LIT> ; else if ( decl_readonly_section ( decl , reloc ) ) prefix = <STR_LIT> ; else prefix = <STR_LIT> ; len = strlen ( name ) + strlen


<s> bool IsF8Reg ( unsigned Reg , MachineRegisterInfo & MRI ) { return IsRegInClass ( Reg , & <STR_LIT> ,


<s> SDLoc DL ( Op ) ; SDValue Ops [ ] = { Chain , DAG . getTargetConstant ( <STR_LIT> , DL , <STR_LIT> ) , DAG . getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) , DAG . getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) , DAG . getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) , DAG . getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) , DAG . getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) } ; SDValue CurrentTEB = DAG . getNode ( <STR_LIT> , DL , DAG . getVTList ( <STR_LIT> , <STR_LIT> ) , Ops ) ; SDValue TEB = CurrentTEB . getValue ( <NUM_LIT> ) ; Chain = CurrentTEB . getValue ( <NUM_LIT> ) ; SDValue TLSArray = DAG . getNode ( <STR_LIT> , DL , PtrVT , TEB , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; TLSArray = DAG . getLoad ( PtrVT , DL , Chain , TLSArray , MachinePointerInfo ( ) ) ; SDValue TLSIndex = DAG . getTargetExternalSymbol ( <STR_LIT> , PtrVT , <STR_LIT> ) ; TLSIndex = DAG . getNode ( <STR_LIT> , DL , PtrVT , TLSIndex ) ; TLSIndex = DAG . getLoad ( PtrVT , DL , Chain , TLSIndex , MachinePointerInfo ( ) ) ; SDValue Slot = DAG . getNode ( <STR_LIT> , DL , PtrVT , TLSIndex , DAG .

getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ;


<s> void <ISA_LIT>AsmPrinter :: printMemOperand ( const MachineInstr * MI , int opNum , raw_ostream &


<s> static std :: pair < unsigned , const TargetRegisterClass * > parseRegisterNumber ( StringRef Constraint , const TargetRegisterClass * RC , const unsigned * Map , unsigned Size ) { assert ( * ( Constraint . end ( ) - <NUM_LIT> )


<s> else gcc_unreachable ( ) ; } else if ( ARC_NORMAL_P ( fn_type ) || ARC_NAKED_P ( fn_type ) ) regno = RETURN_ADDR_REGNUM ; gcc_assert ( regno != <NUM_LIT>


<s> <ISA_LIT>Operand * Op = new <ISA_LIT>Operand ( k_Prefetch , Ctx ) ; Op -> Prefetch . Val = Val ; Op -> StartLoc = S ; Op -> EndLoc = S ; return Op


<s> mode [ <NUM_LIT> ] = insn_data [ icode ] . operand [ <NUM_LIT> ] . mode ; for ( i = <NUM_LIT> ; i < argcount ; i ++ ) { arg [ i ] = CALL_EXPR_ARG ( exp , i ) ; op [ i ] = expand_normal ( arg [ i ] ) ; mode [ i ] = insn_data [ icode ] . operand [ i ] . mode ; if ( code [ i ] == CONST_INT && GET_CODE ( op [ i ] ) != CONST_INT ) error ( <STR_LIT> , i + <NUM_LIT> ) ; if ( code [ i ] == REG && ! ( * insn_data [ icode ] . operand [ i ] . predicate ) ( op [ i ] , mode [ i ] ) ) op [ i ] = copy_to_mode_reg ( mode [ i ] , op [ i ] ) ; } if ( insn_data [ icode ] . operand [ <NUM_LIT> ] . constraint [ <NUM_LIT> ] == '=' ) { if ( target == <NUM_LIT> || GET_MODE ( target ) != mode [ <NUM_LIT> ] || ! ( * insn_data [ icode ] . operand [ <NUM_LIT> ] . predicate ) ( target , mode [ <NUM_LIT> ] ) ) target = gen_reg_rtx ( mode [ <NUM_LIT> ] ) ; } else target = <NUM_LIT> ; switch ( argcount ) { case <NUM_LIT> : pat = GEN_FCN ( icode ) ( target ) ; case <NUM_LIT> : if ( target ) pat = GEN_FCN ( icode ) ( target , op [ <NUM_LIT> ] ) ; else pat = GEN_FCN ( icode ) ( op [ <NUM_LIT> ] ) ; break ; case <NUM_LIT> : if ( target ) pat = GEN_FCN ( icode ) ( target , op [ <NUM_LIT> ] , op [ <NUM_LIT> ] ) ; else pat = GEN_FCN ( icode ) ( op [ <NUM_LIT> ] , op [ <NUM_LIT> ] ) ; break ; case <NUM_LIT> : if ( target ) pat = GEN_FCN ( icode ) ( target , op [ <NUM_LIT> ] , op [ <NUM_LIT> ] , op [ <NUM_LIT> ] ) ; else pat = GEN_FCN ( icode ) ( op [ <NUM_LIT> ] , op [ <NUM_LIT> ] , op [ <NUM_LIT> ] ) ; break ; case <NUM_LIT> : if ( target ) pat = GEN_FCN ( icode ) ( target , op [ <NUM_LIT> ] , op [ <NUM_LIT> ] , op [ <NUM_LIT> ] , op [ <NUM_LIT> ] ) ; else pat = GEN_FCN ( icode ) ( op [ <NUM_LIT> ] , op [ <NUM_LIT> ] , op [ <NUM_LIT> ] , op [ <NUM_LIT> ] ) ; break ; default : gcc_unreachable ( ) ; } if ( ! pat ) return <NUM_LIT> ; emit_insn ( pat


<s> BlockSet & getBlocks ( ) { return Blocks


<s> return __builtin_mve_veorq_m_uv8hi ( __arm_vuninitializedq_u16 ( ) , __a


<s> case MachineOperand :: MO_Immediate : return MCOperand :: createImm ( MO . getImm ( ) + offset ) ; case MachineOperand :: MO_MachineBasicBlock : case MachineOperand :: MO_GlobalAddress : case MachineOperand :: MO_ExternalSymbol : case MachineOperand :: MO_JumpTableIndex : case MachineOperand :: MO_ConstantPoolIndex : case MachineOperand :: MO_BlockAddress : return LowerSymbolOperand ( MO , MOTy , offset ) ; case MachineOperand :: MO_RegisterMask : break ; } return MCOperand (


<s> <ISA_LIT>TargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL , bool isLittle ) : LLVMTargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL ) , Subtarget ( TT , CPU , FS , isLittle , RM , this ) , DL ( computeDataLayout ( Subtarget ) ) , InstrInfo ( <ISA_LIT>InstrInfo :: create ( * this ) ) , FrameLowering ( <ISA_LIT>FrameLowering :: create ( * this , Subtarget ) ) , TLInfo ( <ISA_LIT>TargetLowering :: create ( * this ) ) , TSInfo (

* this ) , InstrItins ( Subtarget . getInstrItineraryData ( ) ) , JITInfo ( ) {


<s> const char * <ISA_LIT>Relocator :: getName ( Relocator :: Type pType ) const { return ApplyFunctions [ pType ]


<s> if ( Reloc == <STR_LIT> ) RelocCST = PICBaseOffset ; else if ( Reloc == <STR_LIT> ) RelocCST = PCAdj ; MCE . addRelocation ( MachineRelocation :: getJumpTable ( MCE . getCurrentPCOffset ( ) , Reloc , JTI , RelocCST ) ) ; if ( Reloc == <STR_LIT> ) MCE . emitDWordLE ( <NUM_LIT> ) ; else MCE . emitWordLE ( <NUM_LIT> )


<s> const MCOperand & MO1 = MI . getOperand ( OpIdx + <NUM_LIT> ) ; Reg = get<ISA_LIT>RegisterNumbering ( MO . getReg ( ) ) ; int32_t SImm = MO1 . getImm ( ) ; bool isAdd = true


<s> void <ISA_LIT>TargetStreamer :: emitPad ( int64_t Offset


<s> if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) { if ( Parser . getTok ( ) . getString ( ) == <STR_LIT> ) Parser . Lex ( ) ; else if ( Parser . getTok ( ) . getString ( ) == <STR_LIT> ) return Error ( DirectiveID . getLoc ( ) , <STR_LIT> <STR_LIT> <STR_LIT> ) ; } return false ; } else if ( IDVal == <STR_LIT> ) return parseDirectiveEven ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) return parseDirectiveFPOProc ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) return parseDirectiveFPOSetFrame ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) return parseDirectiveFPOPushReg ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) return parseDirectiveFPOStackAlloc ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) return parseDirectiveFPOEndPrologue ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) return parseDirectiveFPOEndProc ( DirectiveID . getLoc (


<s> SDValue Elt = DAG . getConstant ( Val , <STR_LIT> ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . assign ( CanonicalVT . getVectorNumElements ( ) , Elt ) ; SDValue Res = DAG . getNode ( <STR_LIT> , dl , CanonicalVT , & Ops [ <NUM_LIT> ] , Ops . size ( ) ) ; return DAG . getNode ( <STR_LIT> ,


<s> error ( <STR_LIT> , rs6000_builtin_info [ ( size_t ) fcode ] . name ) ; return const0_rtx ; } if ( fcode == RS6000_BUILTIN_CPU_IS ) { const char * cpu = TREE_STRING_POINTER ( arg ) ; rtx cpuid = NULL_RTX ; for ( size_t i = <NUM_LIT> ; i < ARRAY_SIZE ( cpu_is_info ) ; i ++ ) if ( strcmp ( cpu , cpu_is_info [ i ] . cpu ) == <NUM_LIT> ) { cpuid = GEN_INT ( cpu_is_info [ i ] . cpuid + _DL_FIRST_PLATFORM ) ; break ; } if ( cpuid == NULL_RTX ) { error ( <STR_LIT> , cpu , rs6000_builtin_info [ ( size_t ) fcode ] . name ) ; return const0_rtx ; } rtx platform = gen_reg_rtx ( SImode ) ; rtx tcbmem = gen_const_mem ( SImode , gen_rtx_PLUS ( Pmode , gen_rtx_REG ( Pmode , TLS_REGNUM ) , GEN_INT ( TCB_PLATFORM_OFFSET ) ) ) ; emit_move_insn ( platform , tcbmem ) ; emit_insn ( gen_eqsi3 ( target , platform , cpuid ) ) ; } else if ( fcode == RS6000_BUILTIN_CPU_SUPPORTS ) { const char * hwcap = TREE_STRING_POINTER ( arg ) ; rtx mask = NULL_RTX ; int hwcap_offset ; for ( size_t i = <NUM_LIT> ; i < ARRAY_SIZE ( cpu_supports_info ) ; i ++ ) if ( strcmp ( hwcap , cpu_supports_info [ i ] . hwcap ) == <NUM_LIT> ) { mask = GEN_INT ( cpu_supports_info [ i ] . mask ) ; hwcap_offset = TCB_HWCAP_OFFSET ( cpu_supports_info [ i ] . id


<s> if ( parseToken ( AsmToken :: EndOfStatement , <STR_LIT> ) )


<s> static inline bool save_global_or_fp_reg_p ( unsigned int regno

, int leaf_function ATTRIBUTE_UNUSED ) {


<s> if ( VA . getLocInfo ( ) == CCValAssign :: Indirect || ExtendedInMem ) ValVT = VA . getLocVT ( ) ; else ValVT = VA . getValVT ( ) ; if ( Flags . isByVal ( ) ) { unsigned Bytes = Flags . getByValSize ( ) ; if ( Bytes == <NUM_LIT> ) Bytes = <NUM_LIT> ; int FI = MFI . CreateFixedObject ( Bytes , VA . getLocMemOffset ( ) , isImmutable , true ) ; return DAG . getFrameIndex ( FI , PtrVT ) ; } EVT ArgVT = Ins [ i ] . ArgVT ; bool ScalarizedAndExtendedVector = ArgVT . isVector ( ) && ! VA . getLocVT ( ) . isVector ( ) && VA . getLocVT ( ) . getSizeInBits ( ) != ArgVT . getScalarSizeInBits ( ) ; if ( Flags . isCopyElisionCandidate ( ) && VA . getLocInfo ( ) != CCValAssign :: Indirect && ! ExtendedInMem && ! ScalarizedAndExtendedVector ) { SDValue PartAddr ; if ( Ins [ i ] . PartOffset == <NUM_LIT> ) { int FI = MFI . CreateFixedObject ( ArgVT . getStoreSize ( ) , VA . getLocMemOffset ( ) , false ) ; PartAddr = DAG . getFrameIndex ( FI , PtrVT ) ; return DAG . getLoad ( ValVT , dl , Chain , PartAddr , MachinePointerInfo :: getFixedStack ( DAG . getMachineFunction ( ) , FI ) ) ; } else { int64_t PartBegin = VA . getLocMemOffset ( ) ; int64_t PartEnd = PartBegin + ValVT . getSizeInBits ( ) / <NUM_LIT> ; int FI = MFI . getObjectIndexBegin ( ) ; for ( ; MFI . isFixedObjectIndex ( FI ) ; ++ FI ) { int64_t ObjBegin = MFI . getObjectOffset ( FI ) ; int64_t ObjEnd = ObjBegin + MFI . getObjectSize ( FI ) ; if ( ObjBegin <= PartBegin && PartEnd <= ObjEnd ) break ; } if ( MFI . isFixedObjectIndex ( FI ) ) { SDValue Addr = DAG . getNode ( <STR_LIT> , dl , PtrVT , DAG . getFrameIndex ( FI , PtrVT ) , DAG . getIntPtrConstant ( Ins [ i ] . PartOffset , dl ) ) ; return DAG . getLoad ( ValVT , dl , Chain , Addr , MachinePointerInfo :: getFixedStack ( DAG . getMachineFunction ( ) , FI , Ins [ i ] . PartOffset ) ) ; } } } int FI = MFI . CreateFixedObject ( ValVT . getSizeInBits ( ) / <NUM_LIT> , VA . getLocMemOffset ( ) , isImmutable ) ; if ( VA . getLocInfo ( ) == CCValAssign :: ZExt ) { MFI . setObjectZExt ( FI , true ) ; } else if ( VA . getLocInfo ( ) == CCValAssign :: SExt ) { MFI . setObjectSExt ( FI , true ) ; } MaybeAlign Alignment


<s> return LI -> getType ( ) -> getPrimitiveSizeInBits ( )


<s> } } } for ( unsigned i = CSI . size ( ) ; i != <NUM_LIT> ; -- i ) { unsigned Reg = CSI [ i - <NUM_LIT> ] . getReg ( ) ; if ( ! <STR_LIT> . contains ( Reg ) && ! <STR_LIT> . contains ( Reg ) ) continue ; SpillSlotOffset -= SlotSize ; CalleeSavedFrameSize += SlotSize ; int SlotIndex = MFI . CreateFixedSpillStackObject ( SlotSize , SpillSlotOffset ) ; CSI [ i - <NUM_LIT> ] . setFrameIdx ( SlotIndex ) ; } <ISA_LIT>FI -> setCalleeSavedFrameSize ( CalleeSavedFrameSize ) ; MFI . setCVBytesOfCalleeSavedRegisters ( CalleeSavedFrameSize ) ; for ( unsigned i = CSI . size ( ) ; i != <NUM_LIT> ; -- i ) { unsigned Reg = CSI [ i - <NUM_LIT> ] . getReg ( ) ; if ( <STR_LIT> . contains ( Reg ) || <STR_LIT> . contains ( Reg ) ) continue ; MVT VT = <STR_LIT> ; if ( <STR_LIT> . contains ( Reg ) ) VT = STI . hasBWI (


<s> bool rs6000_overloaded_builtin_p ( enum rs6000_builtins fncode ) { return ( rs6000_builtin_info [ ( int ) fncode ]

. attr & RS6000_BTC_OVERLOADED ) != <NUM_LIT> ;


<s> if ( ! RC ) return std :: make_pair ( <NUM_LIT> , nullptr ) ; break ; } break ; } if ( RC && ( isTypeLegal ( VT ) || VT . SimpleTy == <STR_LIT> || VT . SimpleTy == <STR_LIT> || VT . SimpleTy == <STR_LIT> ) ) return std :: make_pair ( <NUM_LIT> , RC ) ; } if ( Constraint . size ( ) > <NUM_LIT> ) { if ( Constraint [ <NUM_LIT> ] == 'v' ) { RC = & <STR_LIT> ; } else if ( Constraint [ <NUM_LIT> ] == 's' ) { RC = & <STR_LIT> ; } else if ( Constraint [ <NUM_LIT> ] == 'a' ) { RC = & <STR_LIT> ; } if ( RC ) { uint32_t Idx ; bool Failed = Constraint . substr ( <NUM_LIT> )


<s> default : return false ; case <STR_LIT> : Opc = & OpcTable [ <NUM_LIT> ] [ <NUM_LIT> ] ; break ; case <STR_LIT> : Opc = & OpcTable [ <NUM_LIT> ] [ <NUM_LIT> ] ; break ; } const Value * LHS = I -> getOperand ( <NUM_LIT> ) ; const Value * RHS = I -> getOperand ( <NUM_LIT> ) ; unsigned LHSReg = getRegForValue ( LHS ) ; bool LHSIsKill = hasTrivialKill ( LHS ) ; unsigned RHSReg = getRegForValue ( RHS ) ; bool RHSIsKill = hasTrivialKill ( RHS ) ; unsigned CmpLHSReg = getRegForValue ( CmpLHS ) ; bool CmpLHSIsKill = hasTrivialKill ( CmpLHS ) ; unsigned CmpRHSReg = getRegForValue ( CmpRHS ) ; bool CmpRHSIsKill = hasTrivialKill ( CmpRHS ) ; if ( ! LHSReg || ! RHSReg || ! CmpLHS || ! CmpRHS ) return false ; const TargetRegisterClass * RC = TLI . getRegClassFor ( RetVT ) ; unsigned ResultReg ; if ( Subtarget -> hasAVX512 ( ) ) { const TargetRegisterClass * VR128X = & <STR_LIT> ; const TargetRegisterClass * VK1 = & <STR_LIT> ; unsigned CmpOpcode = ( RetVT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; unsigned CmpReg = fastEmitInst_rri ( CmpOpcode , VK1 , CmpLHSReg , CmpLHSIsKill , CmpRHSReg , CmpRHSIsKill , CC ) ; unsigned ImplicitDefReg = createResultReg ( VR128X ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: IMPLICIT_DEF ) , ImplicitDefReg ) ; unsigned MovOpcode = ( RetVT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; unsigned MovReg = fastEmitInst_rrrr ( MovOpcode , VR128X , RHSReg , RHSIsKill , CmpReg , true , ImplicitDefReg , true , LHSReg , LHSIsKill ) ; ResultReg = createResultReg ( RC ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: COPY ) , ResultReg ) . addReg ( MovReg ) ; } else if ( Subtarget -> hasAVX ( ) ) { const TargetRegisterClass * VR128 = & <STR_LIT> ; unsigned CmpOpcode = ( RetVT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; unsigned BlendOpcode = ( RetVT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; unsigned CmpReg = fastEmitInst_rri ( CmpOpcode , RC , CmpLHSReg , CmpLHSIsKill , CmpRHSReg , CmpRHSIsKill , CC ) ; unsigned VBlendReg = fastEmitInst_rrr ( BlendOpcode , VR128 , RHSReg , RHSIsKill , LHSReg , LHSIsKill , CmpReg , true ) ; ResultReg = createResultReg ( RC ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: COPY ) , ResultReg ) . addReg ( VBlendReg ) ; } else { const TargetRegisterClass * VR128 = & <STR_LIT> ; unsigned CmpReg = fastEmitInst_rri ( Opc [ <NUM_LIT> ] , RC , CmpLHSReg , CmpLHSIsKill , CmpRHSReg , CmpRHSIsKill ,


<s> if ( TREE_CODE ( TREE_TYPE ( valist ) ) == ERROR_MARK ) return ; if ( NUM_ARGS < <NUM_LIT> ) offset = TARGET_ABI_OPEN_VMS ? UNITS_PER_WORD : <NUM_LIT> * UNITS_PER_WORD ; else offset = - <NUM_LIT> * UNITS_PER_WORD + crtl -> args . pretend_args_size ; if ( TARGET_ABI_OPEN_VMS ) { t = make_tree ( ptr_type_node , virtual_incoming_args_rtx ) ; t = fold_build_pointer_plus_hwi ( t , offset + NUM_ARGS * UNITS_PER_WORD ) ; t = build2 ( MODIFY_EXPR , TREE_TYPE ( valist ) , valist , t ) ; TREE_SIDE_EFFECTS ( t ) = <NUM_LIT> ; expand_expr ( t , const0_rtx , VOIDmode , EXPAND_NORMAL ) ; } else { base_field = TYPE_FIELDS ( TREE_TYPE ( valist ) ) ; offset_field = DECL_CHAIN ( base_field ) ; base_field = build3 ( COMPONENT_REF , TREE_TYPE ( base_field ) , valist , base_field , NULL_TREE ) ; offset_field = build3 ( COMPONENT_REF , TREE_TYPE ( offset_field ) , valist , offset_field , NULL_TREE ) ; t = make_tree ( ptr_type_node , virtual_incoming_args_rtx ) ; t = fold_build_pointer_plus_hwi ( t , offset ) ; t = build2 ( MODIFY_EXPR , TREE_TYPE ( base_field ) , base_field , t ) ; TREE_SIDE_EFFECTS ( t ) = <NUM_LIT> ; expand_expr ( t , const0_rtx , VOIDmode , EXPAND_NORMAL ) ; t = build_int_cst ( NULL_TREE


<s> break ; case <STR_LIT> : Opc = <STR_LIT> ; RC = & <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; RC = & <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; RC = & <STR_LIT> ; break ; case <STR_LIT> : if ( <ISA_LIT>ScalarSSEf32 ) { Opc = Subtarget -> hasAVX ( ) ? <STR_LIT> : <STR_LIT> ; RC = & <STR_LIT> ; } else { Opc = <STR_LIT> ; RC = & <STR_LIT> ; } break ; case <STR_LIT> : if ( <ISA_LIT>ScalarSSEf64 ) { Opc = Subtarget -> hasAVX ( ) ? <STR_LIT> : <STR_LIT> ; RC = & <STR_LIT> ; } else { Opc = <STR_LIT> ; RC = & <STR_LIT> ; } break ; case <STR_LIT> : return false ; case <STR_LIT> : if ( Alignment >= <NUM_LIT> ) Opc = Subtarget -> hasAVX ( ) ? <STR_LIT> : <STR_LIT> ; else Opc = Subtarget -> hasAVX ( ) ? <STR_LIT> : <STR_LIT> ; RC = & <STR_LIT> ; break ; case <STR_LIT>


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) : LLVMTargetMachine ( T , computeDataLayout ( TT , CPU , Options ) , TT , CPU , FS , Options , RM , CM , OL ) , Subtarget ( TT , CPU , FS , * this ) , TLOF ( make_unique < TargetLoweringObjectFileELF > ( ) ) { initAsmInfo (


<s> static std :: unique_ptr < <ISA_LIT>Operand > CreateCoprocOption ( unsigned Val , SMLoc S , SMLoc E ) { auto Op = std :: make_unique < <ISA_LIT>Operand > ( k_CoprocOption ) ; Op -> Cop . Val = Val ; Op -> StartLoc = S ; Op -> EndLoc = E ; return


<s> if ( getOptLevel ( ) != CodeGenOpt :: None ) addPass


<s> return Sym . isDefined ( ) ? Layout . getSymbolOffset ( Sym ) :


<s> static DecodeStatus DecodeQQQRegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t Addr , const MCDisassembler * Decoder ) { if ( RegNo > <NUM_LIT> ) return Fail ; unsigned Register = <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . getRegister ( RegNo ) ; Inst . addOperand ( MCOperand :: createReg


<s> if ( <ISA_LIT>ScalarSSEf64 && I -> getType ( ) -> isDoubleTy ( ) ) { const Value * V = I -> getOperand ( <NUM_LIT> ) ; if ( V -> getType ( ) -> isFloatTy ( ) ) { unsigned OpReg = getRegForValue ( V ) ; if ( OpReg == <NUM_LIT> ) return false ; unsigned ResultReg = createResultReg ( <STR_LIT>


<s> void <ISA_LIT>ELFStreamer :: Emit<ISA_LIT>OptionRecords (


<s> if ( ! ExTab && ! CantUnwind ) FlushUnwindOpcodes ( true ) ; SwitchToExIdxSection ( * FnStart ) ; if ( PersonalityIndex < NUM_PERSONALITY_INDEX ) EmitPersonalityFixup ( GetAEABIUnwindPersonalityName ( PersonalityIndex ) ) ; const MCSymbolRefExpr * FnStartRef = MCSymbolRefExpr :: Create ( FnStart , MCSymbolRefExpr :: VK_<ISA_LIT>_PREL31 , getContext ( ) ) ; EmitValue ( FnStartRef , <NUM_LIT> , <NUM_LIT> ) ; if ( CantUnwind ) { EmitIntValue ( EXIDX_CANTUNWIND , <NUM_LIT> , <NUM_LIT> ) ; } else if ( ExTab ) { const MCSymbolRefExpr * ExTabEntryRef = MCSymbolRefExpr :: Create ( ExTab , MCSymbolRefExpr :: VK_<ISA_LIT>_PREL31 , getContext ( ) ) ; EmitValue ( ExTabEntryRef , <NUM_LIT> , <NUM_LIT> ) ; } else { assert ( PersonalityIndex == AEABI_UNWIND_CPP_PR0 && <STR_LIT> ) ; assert ( Opcodes . size ( ) == <NUM_LIT> && <STR_LIT> ) ; EmitBytes ( StringRef ( reinterpret_cast < const char * > ( Opcodes . data ( ) ) , Opcodes . size (


<s> int pru_can_use_return_insn ( void ) { if ( ! reload_completed || crtl