<s> auto CASDesired = MRI . createGenericVirtualRegister ( s128 ) ; auto CASNew = MRI . createGenericVirtualRegister ( s128 ) ; MIRBuilder . buildInstr ( TargetOpcode :: REG_SEQUENCE , { CASDesired } , { } ) . addUse ( DesiredI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addImm ( <STR_LIT> ) . addUse ( DesiredI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addImm ( <STR_LIT> ) ; MIRBuilder . buildInstr ( TargetOpcode :: REG_SEQUENCE , { CASNew } , { } ) . addUse ( NewI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addImm ( <STR_LIT> ) . addUse ( NewI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addImm ( <STR_LIT> ) ; CAS = MIRBuilder . buildInstr ( Opcode , { CASDst } , { CASDesired , CASNew , Addr } ) ; MIRBuilder . buildExtract ( { DstLo } , { CASDst } , <NUM_LIT> ) ; MIRBuilder . buildExtract ( { DstHi } , { CASDst } , <NUM_LIT> ) ; } else { auto Ordering = ( * MI . memoperands_begin ( ) ) -> getMergedOrdering ( ) ; unsigned Opcode ; switch ( Ordering ) { case AtomicOrdering :: Acquire : Opcode = <STR_LIT>


<s> Br . MaxDisp = ( <NUM_LIT> << <NUM_LIT> ) * <NUM_LIT> ; MI -> setDesc ( TII -> get ( <STR_LIT> ) ) ; BBSizes [ MBB -> getNumber ( ) ] += <NUM_LIT> ; AdjustBBOffsetsAfter ( MBB , <NUM_LIT> ) ; HasFarJump = true ; ++ NumUBrFixed


<s> return sh_check_add_incdec_notes ( emit_move_insn ( dst , sh_remove_overlapping_post_inc (


<s> const MachineOperand & Src2 = MI . getOperand ( <NUM_LIT> ) ; bool Result ; unsigned Opc = MI . getOpcode ( ) ; bool Computed = evaluateHexCompare2 ( Opc , Src1 , Src2 , Inputs , Result ) ; if ( Computed ) { RegisterSubReg DefR ( MI . getOperand ( <NUM_LIT> ) ) ; LatticeCell L = Outputs . get ( DefR . Reg ) ; uint32_t P = Result ? ConstantProperties :: NonZero : ConstantProperties :: Zero ; L . add ( P ) ; Outputs . update ( DefR . Reg ,


) _mm_setr_pd ( double __W , double __X ) {


<s> return ( float32_t ) __builtin_neon_vget_lanev2sf ( __a ,


<s> SDValue Mul = DAG . getNode ( MultOpc , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; SDValue InChain = DAG . getEntryNode ( ) ; SDValue InGlue = Mul ; if ( ! Op . getValue ( <NUM_LIT> ) . use_empty ( ) ) { SDValue CopyFromLo = DAG . getCopyFromReg ( InChain , dl , <STR_LIT> , Ty , InGlue ) ; DAG . ReplaceAllUsesOfValueWith ( Op . getValue ( <NUM_LIT> ) , CopyFromLo ) ; InChain = CopyFromLo . getValue ( <NUM_LIT> ) ; InGlue = CopyFromLo . getValue ( <NUM_LIT> ) ; } if ( ! Op . getValue ( <NUM_LIT> ) . use_empty ( ) ) { SDValue CopyFromHi = DAG . getCopyFromReg ( InChain , dl , <STR_LIT> , Ty , InGlue ) ; DAG . ReplaceAllUsesOfValueWith ( Op . getValue ( <NUM_LIT>


<s> static bool r10k_needs_protection_p_call ( const_rtx x ) { subrtx_iterator :: array_type array ; FOR_EACH_SUBRTX ( iter , array , x , NONCONST ) { const_rtx mem =


<s> if ( ! OrigTy . isSimple ( ) ) { return BaseT :: getIntrinsicInstrCost ( ICA , CostKind ) ; } std :: pair < int , MVT > LT = TLI -> getTypeLegalizationCost ( DL , RetTy ) ; unsigned NElts = LT . second . isVector ( ) ? LT . second . getVectorNumElements ( ) : <NUM_LIT> ; <STR_LIT> SLT = LT . second . getScalarType ( ) . SimpleTy ; if ( SLT == <STR_LIT> ) return LT . first * NElts * get64BitInstrCost ( ) ; if ( ST -> has16BitInsts ( ) && SLT == <STR_LIT> ) NElts = ( NElts + <NUM_LIT> ) / <NUM_LIT> ; unsigned InstRate = getQuarterRateInstrCost ( ) ; if ( ICA . getID ( ) == <STR_LIT> ) { InstRate = ST -> hasFastFMAF32 ( ) ? getHalfRateInstrCost ( ) : getQuarterRateInstrCost


<s> OpRef P = packs ( SM , Va , Vb , Results , PackedMask ) ; if ( P . isValid ( ) ) return shuffs1 ( ShuffleMask ( PackedMask ) , P , Results ) ; SmallVector < int , <NUM_LIT> > MaskL ( VecLen ) , MaskR ( VecLen ) ; splitMask ( SM . Mask , MaskL , MaskR ) ; OpRef L = shuffs1 ( ShuffleMask ( MaskL ) , Va , Results ) ; OpRef R = shuffs1 ( ShuffleMask ( MaskR ) , Vb , Results ) ; if ( ! L . isValid ( ) || ! R . isValid ( ) ) return OpRef :: fail ( ) ; SmallVector < uint8_t , <NUM_LIT> > Bytes ( VecLen ) ; for ( int I = <NUM_LIT> ; I != VecLen ; ++ I ) { if ( MaskL [ I ] != - <NUM_LIT> ) Bytes [ I


<s> if ( I -> isDeclaration ( ) ) { continue ; } IRBuilder < > Builder ( I -> getEntryBlock ( ) . getFirstNonPHIOrDbg ( ) ) ; for ( Function :: iterator BBI = I -> begin ( ) , BBE = I -> end ( ) ; BBI != BBE ; ++ BBI ) { for ( BasicBlock :: iterator II = BBI -> begin ( ) , IE = BBI -> end ( ) ; II != IE ; ++ II ) { for ( unsigned i = <NUM_LIT> , e = II -> getNumOperands ( ) ; i < e ; ++ i ) { Value * Operand = II -> getOperand ( i ) ; if ( isa < Constant > ( Operand ) ) { II -> setOperand ( i , remapConstant ( & M , I , cast < Constant > ( Operand ) , Builder ) ) ; } } } } ConstantToValueMap . clear ( ) ; } for ( Module :: named_metadata_iterator I = M . named_metadata_begin ( ) , E = M . named_metadata_end ( ) ; I != E ; I ++ ) { remapNamedMDNode ( & M , I ) ; } for ( GVMapTy :: iterator I = GVMap . begin ( ) , E = GVMap . end ( ) ; I != E ; ) { GlobalVariable * GV = I -> first ; GlobalVariable * NewGV = I -> second ; ++ I ; Constant * BitCastNewGV = ConstantExpr :: getPointerCast ( NewGV , GV -> getType ( ) ) ; for ( Value :: use_iterator UI = GV -> use_begin ( ) , UE = GV -> use_end ( ) ; UI != UE ; ) ( UI ++ ) -> set ( BitCastNewGV ) ; std :: string Name = GV -> getName ( ) ; GV -> removeDeadConstantUsers ( ) ; GV -> eraseFromParent


<s> const MCOperand & Op2 = MI -> getOperand ( opNum + <NUM_LIT> ) ; bool PrintedFirstOperand = false ; if ( Op1 . isReg ( ) && Op1 . getReg ( ) != <STR_LIT> ) { printOperand ( MI , opNum , STI , O ) ; PrintedFirstOperand = true ; } const bool SkipSecondOperand = PrintedFirstOperand && ( ( Op2 . isReg ( ) && Op2 . getReg ( ) == <STR_LIT> ) || ( Op2 . isImm ( ) && Op2 . getImm ( ) == <NUM_LIT> ) ) ; if ( ! SkipSecondOperand ) { if ( PrintedFirstOperand ) O <<


<s> return StringSwitch < unsigned > ( STI . getCPU ( ) ) . Case ( <STR_LIT> , llvm :: ELF :: EF_HEXAGON_MACH_V5 ) . Case ( <STR_LIT> , llvm :: ELF :: EF_HEXAGON_MACH_V5 ) . Case ( <STR_LIT> , llvm :: ELF :: EF_HEXAGON_MACH_V55 ) . Case ( <STR_LIT> , llvm :: ELF :: EF_HEXAGON_MACH_V60 ) . Case ( <STR_LIT> , llvm :: ELF :: EF_HEXAGON_MACH_V62 ) . Case

( <STR_LIT> , llvm :: ELF :: EF_HEXAGON_MACH_V65 ) . Case ( <STR_LIT> , llvm :: ELF :: EF_HEXAGON_MACH_V66 ) . Case ( <STR_LIT> , llvm :: ELF :: EF_HEXAGON_MACH_V67 ) . Case ( <STR_LIT> , llvm :: ELF :: EF_HEXAGON_MACH_V67T ) . Case ( <STR_LIT> , llvm :: ELF :: EF_HEXAGON_MACH_V68 ) . Case ( <STR_LIT> , llvm :: ELF :: EF_HEXAGON_MACH_V69 ) ;


<s> MachineBasicBlock :: iterator I , Next ; for ( I = MBB -> begin ( ) ; I != MBB -> end ( ) ; I = Next ) { Next = std :: next ( I ) ; MachineInstr & MI = * I ; tryFoldInst ( TII , & MI ) ; if ( ! TII -> isFoldableCopy ( MI ) ) { if ( IsIEEEMode || ! tryFoldOMod ( MI ) ) tryFoldClamp ( MI ) ; continue ; } MachineOperand & OpToFold = MI . getOperand ( <NUM_LIT> ) ; bool FoldingImm = OpToFold . isImm ( ) || OpToFold . isFI ( ) ; if ( ! FoldingImm && ! OpToFold . isReg ( ) ) continue ; if ( OpToFold . isReg ( ) && ! TargetRegisterInfo :: isVirtualRegister ( OpToFold . getReg


<s> int RegNum = parseRegisterName ( & MatchRegisterName ) ; if ( RegNum == <STR_LIT> ) RegNum

= parseRegisterName ( & MatchRegisterAltName ) ;


<s> if ( Op . isOff ( ) ) { assert ( SrcIdx < <NUM_LIT> ) ; OperandIdx [ SrcIdx ] = Inst . size ( ) ; Inst . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ; ++ SrcIdx ; continue ; } if ( Op . isImm ( ) && Op . getImmTy ( ) == <ISA_LIT>Operand :: ImmTyExpTgt ) { Op . addImmOperands ( Inst , <NUM_LIT> ) ; continue ; } if ( Op . isToken ( ) && ( Op . getToken ( ) == <STR_LIT> || Op . getToken ( ) == <STR_LIT> ) ) continue ; OptionalIdx [ Op . getImmTy ( ) ] = i ; } assert ( SrcIdx == <NUM_LIT> ) ; bool Compr = false ; if ( OptionalIdx . find ( <ISA_LIT>Operand :: ImmTyExpCompr ) != OptionalIdx . end ( ) ) { Compr = true ; Inst . getOperand ( OperandIdx [ <NUM_LIT> ] ) = Inst . getOperand ( OperandIdx [ <NUM_LIT> ] ) ; Inst . getOperand ( OperandIdx [ <NUM_LIT> ] ) . setReg ( <STR_LIT> ) ; Inst . getOperand ( OperandIdx [ <NUM_LIT> ] ) . setReg


<s> ( ( <ISA_LIT>Operand * ) Operands [ <NUM_LIT> ] ) -> addRegOperands ( Inst , <NUM_LIT> ) ; ( ( <ISA_LIT>Operand * ) Operands [ <NUM_LIT> ] ) -> addMemImm8s4OffsetOperands ( Inst , <NUM_LIT> ) ; ( ( <ISA_LIT>Operand * ) Operands [ <NUM_LIT> ] ) -> addCondCodeOperands


<s> static bool loongarch_split_move_insn_p ( rtx dest , rtx src ) { return loongarch_split_move_p ( dest


<s> assert ( CPI < MCP -> getConstants ( ) . size ( ) && <STR_LIT> ) ; unsigned Align = MCP -> getConstants ( ) [


<s> __vector signed short w ; w = ( __vector signed short ) vec_splats ( __w ) ; return ( __m64 ) ( ( __vector long long ) w ) [ <NUM_LIT> ] ; __m64_union __res ; __res . as_short [ <NUM_LIT> ] = __w ; __res . as_short [ <NUM_LIT>


<s> unsigned CurOp = <NUM_LIT> ; if ( NumOps > <NUM_LIT> && Desc . getOperandConstraint ( <NUM_LIT> , MCOI :: TIED_TO ) == <NUM_LIT> ) ++ CurOp ; else if ( NumOps > <NUM_LIT> && Desc . getOperandConstraint ( <NUM_LIT> , MCOI :: TIED_TO ) == <NUM_LIT> && Desc . getOperandConstraint ( <NUM_LIT> , MCOI :: TIED_TO ) == <NUM_LIT> ) CurOp += <NUM_LIT> ; else if ( NumOps > <NUM_LIT> && Desc . getOperandConstraint ( <NUM_LIT> , MCOI :: TIED_TO ) == <NUM_LIT> && Desc . getOperandConstraint ( NumOps - <NUM_LIT> , MCOI :: TIED_TO ) == <NUM_LIT> ) CurOp += <NUM_LIT> ; else if ( NumOps > <NUM_LIT> && Desc . getOperandConstraint ( NumOps - <NUM_LIT> , MCOI :: TIED_TO ) == <NUM_LIT> ) ++ CurOp ; return


<s> if ( ! MO . isJTI ( ) && MO . getOffset ( ) ) ME = MCBinaryExpr :: createAdd ( ME , MCConstantExpr :: create ( MO . getOffset ( ) , Ctx ) , Ctx ) ; if ( Kind != <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ) ME = <ISA_LIT>MCExpr ::


<s> return ( __m256d ) __builtin_ia32_sqrtpd256 ( (


<s> return new <ISA_LIT>CallIndirectFixup


<s> void setCPR1SizeFromPredicates ( const PredicateLibrary & P ) { if ( P . mipsSEUsesSoftFloat ( ) ) CPR1Size = AFL_REG_NONE ; else if ( P . hasMSA ( ) ) CPR1Size = AFL_REG_128 ; else CPR1Size = P . isFP64bit ( )


<s> RegPressureTracker & TempTracker = const_cast < RegPressureTracker & > ( RPTracker ) ; std :: vector < unsigned > Pressure ; std :: vector < unsigned > MaxPressure ; if ( AtTop ) TempTracker . getDownwardPressure ( SU -> getInstr ( ) , Pressure , MaxPressure ) ; else { TempTracker . getUpwardPressure ( SU -> getInstr ( ) , Pressure , MaxPressure ) ; } int NewSGPRPressure = Pressure [ SRI -> getSGPRPressureSet ( ) ] ; int NewVGPRPressure = Pressure [ SRI -> getVGPRPressureSet ( ) ] ; const int MaxVGPRPressureInc = <NUM_LIT> ; bool ShouldTrackVGPRs = VGPRPressure + MaxVGPRPressureInc >= VGPRExcessLimit ; bool ShouldTrackSGPRs = ! ShouldTrackVGPRs && SGPRPressure >= SGPRExcessLimit ; const int ErrorMargin = <NUM_LIT> ; VGPRExcessLimit -= ErrorMargin ; SGPRExcessLimit -= ErrorMargin ; if ( ShouldTrackVGPRs && NewVGPRPressure >= VGPRExcessLimit ) { Cand . RPDelta . Excess = PressureChange ( SRI -> getVGPRPressureSet ( ) ) ; Cand . RPDelta . Excess . setUnitInc ( NewVGPRPressure - VGPRExcessLimit ) ; } if ( ShouldTrackSGPRs && NewSGPRPressure >= SGPRExcessLimit ) { Cand . RPDelta . Excess = PressureChange ( SRI -> getSGPRPressureSet ( ) ) ; Cand . RPDelta . Excess . setUnitInc ( NewSGPRPressure = SGPRExcessLimit ) ; } VGPRCriticalLimit -= ErrorMargin ; SGPRCriticalLimit -= ErrorMargin ; int SGPRDelta = NewSGPRPressure - SGPRCriticalLimit ; int VGPRDelta = NewVGPRPressure - VGPRCriticalLimit ; if ( SGPRDelta >= <NUM_LIT> || VGPRDelta >= <NUM_LIT> ) { if ( SGPRDelta > VGPRDelta


<s> case Instruction :: Mul : return false ; case Instruction :: Add : return ScalarBits * cast < FixedVectorType > ( VTy ) -> getNumElements ( ) >= <NUM_LIT> ; case Instruction :: ICmp : return ( ScalarBits < <NUM_LIT> ) && ( ScalarBits * cast < FixedVectorType > ( VTy ) -> getNumElements ( ) >= <NUM_LIT> ) ; case Instruction :: FCmp : return Flags . NoNaN ; default : llvm_unreachable ( <STR_LIT> ) ; } return


<s> return new <ISA_LIT>PassConfig ( this , PM


<s> if ( Addr . getOpcode ( ) == <STR_LIT> || Addr . getOpcode ( ) == <STR_LIT> ) return false ; if ( Addr . getOpcode ( ) == <STR_LIT> ) { if ( ConstantSDNode * CN = dyn_cast < ConstantSDNode > ( Addr . getOperand ( <NUM_LIT> ) ) ) if ( isInt < <NUM_LIT> > ( CN -> getSExtValue ( ) ) ) return false ; if ( Addr . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> || Addr . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) return false ; R1 = Addr . getOperand ( <NUM_LIT> ) ; R2 = Addr . getOperand ( <NUM_LIT> ) ; return true ; } R1 = Addr ; R2 = CurDAG -> getRegister ( <STR_LIT> , getTargetLowering ( ) -> getPointerTy ( ) ) ; return


<s> MachineBasicBlock * <ISA_LIT>SETargetLowering :: emitFEXP2_D_1 ( MachineInstr & MI , MachineBasicBlock * BB ) const { const TargetInstrInfo * TII = Subtarget . getInstrInfo ( ) ; MachineRegisterInfo & RegInfo = BB -> getParent ( ) -> getRegInfo ( ) ; const TargetRegisterClass * RC = & <STR_LIT> ; Register Ws1 = RegInfo . createVirtualRegister ( RC ) ; Register Ws2 = RegInfo . createVirtualRegister ( RC ) ; DebugLoc DL = MI . getDebugLoc ( ) ; BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) , Ws1 ) . addImm ( <NUM_LIT> ) ; BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) , Ws2 ) . addReg ( Ws1 ) ; BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) , MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( Ws2 ) . addReg ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; MI . eraseFromParent (


<s> TREE_PUBLIC ( decl ) = <NUM_LIT> ; TREE_STATIC ( decl ) = <NUM_LIT> ; DECL_IGNORED_P ( decl ) = <NUM_LIT> ; if ( TARGET_MACHO ) { switch_to_section ( darwin_sections [ text_coal_section ] ) ; fputs ( <STR_LIT> , asm_out_file ) ; assemble_name ( asm_out_file , name ) ; fputs ( <STR_LIT> , asm_out_file ) ; assemble_name ( asm_out_file , name ) ; putc ( '\n' , asm_out_file ) ; ASM_OUTPUT_LABEL ( asm_out_file , name ) ; DECL_WEAK ( decl ) = <NUM_LIT> ; } else if ( USE_HIDDEN_LINKONCE ) { cgraph_node :: create ( decl ) -> set_comdat_group ( DECL_ASSEMBLER_NAME ( decl ) ) ; targetm . asm_out . unique_section ( decl , <NUM_LIT> ) ; switch_to_section ( get_named_section ( decl , NULL ,


<s> } const MachineOperand * Dst = getNamedOperand ( MI , <STR_LIT> :: vdst ) ; const MachineOperand * Src0 = getNamedOperand ( MI , <STR_LIT> :: src0 ) ; const MachineOperand * Src0Mods = getNamedOperand ( MI , <STR_LIT> :: src0_modifiers ) ; const MachineOperand * Src1 = getNamedOperand ( MI , <STR_LIT> :: src1 ) ; const MachineOperand * Src1Mods = getNamedOperand ( MI , <STR_LIT> :: src1_modifiers ) ; const MachineOperand * Src2 = getNamedOperand ( MI , <STR_LIT> :: src2 ) ; const MachineOperand * Clamp = getNamedOperand ( MI , <STR_LIT> :: clamp ) ; const MachineOperand * Omod = getNamedOperand ( MI , <STR_LIT> :: omod ) ; if ( ! Src0Mods && ! Src1Mods && ! Clamp && ! Omod && ( ! Src0 -> isReg ( ) || ! RI . isSGPRReg ( MBB -> getParent ( ) -> getRegInfo ( ) , Src0 -> getReg ( ) ) ) ) { if ( auto Imm = getFoldableImm ( Src2 ) ) { return BuildMI ( * MBB , MI , MI . getDebugLoc ( ) , get ( IsF16 ? <STR_LIT> : <STR_LIT> ) ) . add ( * Dst ) . add ( * Src0 ) . add ( * Src1 ) . addImm ( Imm ) ; } if ( auto Imm = getFoldableImm ( Src1 ) ) { return BuildMI ( * MBB , MI , MI . getDebugLoc ( ) , get ( IsF16 ? <STR_LIT> : <STR_LIT> ) ) . add ( * Dst ) . add ( * Src0 ) . addImm ( Imm ) . add ( * Src2 ) ; } if ( auto Imm = getFoldableImm ( Src0 ) ) { if ( isOperandLegal ( MI , <STR_LIT> ( <STR_LIT> , <STR_LIT> :: src0 ) , Src1 ) ) return BuildMI ( * MBB , MI , MI . getDebugLoc ( ) , get ( IsF16 ? <STR_LIT> : <STR_LIT> ) ) . add ( * Dst ) . add ( * Src1 ) . addImm ( Imm )


<s> static <STR_LIT> getType ( const TargetRegisterClass * RC ) { if ( RC == & <STR_LIT> ) return <STR_LIT> :: I32 ; if ( RC == & <STR_LIT> ) return <STR_LIT> :: I64 ; if ( RC == & <STR_LIT> ) return <STR_LIT> :: F32 ; if ( RC == & <STR_LIT> ) return <STR_LIT> :: F64 ; if ( RC == & <STR_LIT> ) return <STR_LIT>


<s> TBB = I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; continue ; } assert ( I -> getOpcode ( ) == <STR_LIT> && <STR_LIT> ) ; <STR_LIT> BranchCode = static_cast < <STR_LIT> > ( I -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; if ( BranchCode == <STR_LIT> ) return true ; if ( Cond . empty ( ) ) { FBB = TBB ; TBB = I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; Cond . push_back ( MachineOperand :: CreateImm ( BranchCode ) ) ; continue ; } assert ( Cond . size ( ) == <NUM_LIT> ) ; assert ( TBB ) ; if ( TBB != I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ) return true ; <STR_LIT> OldBranchCode = ( <STR_LIT> ) Cond [ <NUM_LIT> ] .


<s> rtx to_add ; rtx imm_rtx = gen_int_si ( offset ) ; rtx_insn * insn ; if ( satisfies_constraint_J ( imm_rtx ) ) { to_add = imm_rtx ; } else { rtx tmp = gen_rtx_REG ( Pmode , ( * next_scratch_regno


<s> UseDataRegionDirectives = true ; HasSingleParameterDotFile = false ; HasDotTypeDotSizeDirective = false ; if ( Enable<ISA_LIT>Assembler ) { EnableInMemoryAsmEmit = true ; AsmMemoryBuffer = new std :: string ( <STR_LIT> ) ; } AlignmentIsInBytes = false ; COMMDirectiveAlignmentIsInBytes = false ; LCOMMDirectiveAlignmentType = LCOMM ::


<s> SDValue Size = Op . getOperand ( <NUM_LIT> ) ; DebugLoc dl = Op . getDebugLoc ( ) ; EVT PtrVT = DAG . getTargetLoweringInfo ( ) . getPointerTy ( ) ; SDValue NegSize = DAG . getNode ( <STR_LIT> , dl , PtrVT , DAG . getConstant ( <NUM_LIT> , PtrVT ) , Size ) ; SDValue FPSIdx = getFramePointerFrameIndex ( DAG ) ; SDValue Ops [ <NUM_LIT> ] = { Chain ,


<s> bool FixupLEAPass :: processBasicBlock ( MachineFunction & MF , MachineFunction :: iterator MFI ) { for ( MachineBasicBlock :: iterator I = MFI -> begin ( ) ; I != MFI -> end ( )

; ++ I ) processInstruction ( I , MFI ) ;


<s> assert ( ( isNarrowLoad ( * MBBI ) || isPromotableZeroStoreOpcode ( * MBBI ) ) && <STR_LIT> ) ; MachineInstr & MI = * MBBI ; MachineBasicBlock :: iterator E = MI . getParent ( ) -> end ( ) ; if ( ! TII -> isCandidateToMergeOrPair ( MI ) ) return false ; if ( isPromotableZeroStoreOpcode ( MI ) && getLdStRegOp ( MI ) . getReg


<s> bool <ISA_LIT>TargetLowering :: mayBeEmittedAsTailCall ( CallInst * CI ) const { if ( ! CI -> isTailCall ( ) ) return false ; return true


<s> const char startPacket = '{' , endPacket = '}' ; if ( MI -> getOpcode ( ) == <STR_LIT> ) { assert ( MI -> isPacketEnd ( ) && <STR_LIT> ) ; if ( MI -> isPacketStart ( ) ) { <ISA_LIT>MCInst Nop ; StringRef NoAnnot ; Nop . setOpcode ( <STR_LIT>


<s> return ; } } break ; case <STR_LIT> : { Known = DAG . computeKnownBits ( Op . getOperand ( <NUM_LIT> ) , Depth + <NUM_LIT> ) ; if ( Known . isUnknown ( ) ) return ; KnownBits KnownRHS = DAG . computeKnownBits ( Op . getOperand ( <NUM_LIT> ) , Depth + <NUM_LIT> ) ; Known . Zero &= KnownRHS . Zero ; Known . One &= KnownRHS . One ; return ; } case <STR_LIT> : { ConstantSDNode * CN = cast < ConstantSDNode > ( Op -> getOperand ( <NUM_LIT> ) ) ; <STR_LIT> IntID = static_cast < <STR_LIT> > ( CN -> getZExtValue ( ) ) ; switch ( IntID ) { default : return ; case <STR_LIT> : case <STR_LIT> : { EVT VT = cast < MemIntrinsicSDNode > ( Op ) -> getMemoryVT ( ) ; unsigned MemBits = VT . getScalarSizeInBits ( ) ; Known . Zero |= APInt :: getHighBitsSet (


<s> static MCRelocationInfo * create<ISA_LIT>MCRelocationInfo ( StringRef TT , MCContext & Ctx ) { Triple TheTriple ( TT ) ; if ( TheTriple . isEnvironmentMachO ( ) ) return create<ISA_LIT>MachORelocationInfo ( Ctx ) ; return llvm :: createMCRelocationInfo (


<s> const <ISA_LIT>Subtarget & Subtarget = DAG . getMachineFunction ( ) . getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( ! ConstantSize ) return SDValue ( ) ; uint64_t SizeVal = ConstantSize -> getZExtValue ( ) ; if ( ! AlwaysInline && SizeVal > Subtarget . getMaxInlineSizeThreshold ( ) ) return SDValue ( ) ; if ( ! AlwaysInline && ( Align & <NUM_LIT> ) != <NUM_LIT> ) return SDValue ( ) ; if ( DstPtrInfo . getAddrSpace ( ) >= <NUM_LIT> || SrcPtrInfo . getAddrSpace ( ) >= <NUM_LIT> ) return SDValue ( ) ; const unsigned ClobberSet [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; if ( isBaseRegConflictPossible ( DAG , ClobberSet ) ) return SDValue ( ) ; MVT AVT ; if ( Align & <NUM_LIT> ) AVT = <STR_LIT> ; else if ( Align & <NUM_LIT> ) AVT = <STR_LIT> ; else if ( Align & <NUM_LIT> ) AVT = <STR_LIT> ; else AVT = Subtarget . is64Bit ( ) ? <STR_LIT> : <STR_LIT> ; unsigned UBytes = AVT . getSizeInBits ( ) / <NUM_LIT> ; unsigned CountVal = SizeVal / UBytes ; SDValue Count = DAG . getIntPtrConstant ( CountVal ) ; unsigned BytesLeft = SizeVal % UBytes ; SDValue InFlag ; Chain = DAG . getCopyToReg ( Chain , dl , Subtarget . is64Bit ( ) ? <STR_LIT> : <STR_LIT> , Count , InFlag ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; Chain = DAG . getCopyToReg ( Chain , dl , Subtarget . is64Bit ( ) ? <STR_LIT> : <STR_LIT> , Dst , InFlag ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; Chain = DAG . getCopyToReg ( Chain , dl , Subtarget . is64Bit ( ) ? <STR_LIT> : <STR_LIT> , Src , InFlag ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; SDVTList Tys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SDValue Ops [ ] = { Chain , DAG . getValueType ( AVT ) , InFlag } ; SDValue RepMovs = DAG . getNode ( <STR_LIT> , dl , Tys , Ops ) ; SmallVector < SDValue , <NUM_LIT> > Results ; Results . push_back ( RepMovs ) ; if ( BytesLeft ) { unsigned Offset = SizeVal - BytesLeft


<s> if ( Src1 && ( ! isVGPR ( Src1 , TRI , MRI ) || ( Src1Mod && Src1Mod -> getImm ( ) != <NUM_LIT> ) ) ) return false ; if ( TII -> hasModifiersSet ( MI , AMDGPU :: OpName :: src0_modifiers ) ) return false ; if ( TII -> hasModifiersSet ( MI , AMDGPU :: OpName :: omod ) ) return false ; if ( TII -> hasModifiersSet ( MI , AMDGPU :: OpName :: clamp ) ) return false ; return true


<s> if ( GET_CODE ( addr ) == MEM ) addr = XEXP


<s> unsigned imm = Val << <NUM_LIT> ; Inst . addOperand ( MCOperand :: createImm ( imm ) ) ; tryAddingPcLoadReferenceComment ( Address , ( Address & ~ <NUM_LIT> ) + imm + <NUM_LIT> , Decoder ) ; return MCDisassembler ::


<s> const Triple & TT = STI . getTargetTriple ( ) ; if ( TT . isOSBinFormatELF ( ) ) return new <ISA_LIT>TargetELFStreamer ( S ) ; return new <ISA_LIT>TargetWasmStreamer (


<s> const <ISA_LIT>RegisterInfo * TRI = ST . getRegisterInfo ( ) ; const MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; const MachineOperand * LaneSelectOp = TII -> getNamedOperand ( * RWLane , <STR_LIT> :: src1 ) ; if ( ! LaneSelectOp -> isReg ( ) || ! TRI -> isSGPRReg ( MRI , LaneSelectOp -> getReg ( ) ) ) return <NUM_LIT> ; Register LaneSelectReg = LaneSelectOp -> getReg ( ) ; auto IsHazardFn = [ TII ] ( MachineInstr * MI ) { return TII -> isVALU (


<s> return new <ISA_LIT>SLSHardening ( )


<s> return isNarrowStore ( Opc ) || Opc == <STR_LIT> ||


<s> unsigned <ISA_LIT>TargetLowering :: getABIAlignmentForCallingConv ( Type * ArgTy , DataLayout DL ) const { if ( ! ArgTy -> isVectorTy ( ) ) return DL . getABITypeAlignment ( ArgTy ) ; return std :: min ( DL . getABITypeAlignment ( ArgTy ) , ( unsigned ) DL . getStackAlignment (


<s> const LLT p0 = LLT :: pointer ( <NUM_LIT> , <NUM_LIT> ) ; getActionDefinitionsBuilder ( { G_ADD , G_SUB , G_MUL } ) . legalFor ( { s32 } ) . clampScalar ( <NUM_LIT> , s32 , s32 ) ; getActionDefinitionsBuilder ( { G_UADDO , G_UADDE , G_USUBO , G_USUBE , G_UMULO } ) . lowerFor ( { { s32 , s1 } } ) ; getActionDefinitionsBuilder ( G_UMULH ) . legalFor ( { s32 } ) . maxScalar ( <NUM_LIT> , s32 ) ; getActionDefinitionsBuilder ( { G_LOAD , G_STORE } ) . legalForTypesWithMemDesc ( { { s32 , p0 , <NUM_LIT> , <NUM_LIT> } , { s32 , p0 , <NUM_LIT> , <NUM_LIT> } , { s32 , p0 , <NUM_LIT> , <NUM_LIT> } , { p0 , p0 , <NUM_LIT> , <NUM_LIT> } } ) . minScalar ( <NUM_LIT> , s32 ) ; getActionDefinitionsBuilder ( { G_ZEXTLOAD , G_SEXTLOAD } ) . legalForTypesWithMemDesc ( { { s32 , p0 , <NUM_LIT> , <NUM_LIT> } , { s32 , p0 , <NUM_LIT> , <NUM_LIT> } } ) . minScalar ( <NUM_LIT> , s32 ) ; getActionDefinitionsBuilder ( G_SELECT ) . legalForCartesianProduct ( { p0 , s32 } , { s32 } ) . minScalar ( <NUM_LIT> , s32 ) . minScalar ( <NUM_LIT> , s32 ) ; getActionDefinitionsBuilder ( G_BRCOND ) . legalFor ( { s32 } ) . minScalar ( <NUM_LIT> , s32 ) ; getActionDefinitionsBuilder ( G_PHI ) . legalFor ( { p0 , s32 } ) . minScalar ( <NUM_LIT> , s32 ) ; getActionDefinitionsBuilder ( { G_AND , G_OR , G_XOR } ) . legalFor ( { s32 } ) . clampScalar ( <NUM_LIT> , s32 , s32 ) ; getActionDefinitionsBuilder ( { G_SDIV , G_SREM , G_UREM , G_UDIV } ) . legalFor ( { s32 } ) . minScalar ( <NUM_LIT> , s32 ) . libcallFor ( { s64 } ) ; getActionDefinitionsBuilder ( { G_SHL , G_ASHR , G_LSHR } ) . legalFor ( { s32 , s32 } ) . minScalar ( <NUM_LIT> , s32 ) ; getActionDefinitionsBuilder ( G_ICMP ) . legalFor ( { { s32 , s32 } } ) . minScalar ( <NUM_LIT> , s32 ) ; getActionDefinitionsBuilder ( G_CONSTANT ) . legalFor ( { s32 } ) . clampScalar ( <NUM_LIT> , s32 , s32 ) ; getActionDefinitionsBuilder ( G_GEP ) . legalFor ( { { p0 , s32 } } ) ; getActionDefinitionsBuilder ( G_FRAME_INDEX ) . legalFor ( {


<s> Register SrcEvenReg = getSubReg ( SrcReg , <STR_LIT> ) ; Register SrcOddReg = getSubReg ( SrcReg , <STR_LIT> ) ; MachineInstr * StMI = BuildMI ( * MI . getParent ( ) , II , dl , TII . get ( <STR_LIT> ) ) . addReg ( FrameReg ) . addImm ( <NUM_LIT> ) . addReg ( SrcEvenReg ) ; replaceFI ( MF , * StMI , * StMI , dl , <NUM_LIT> , Offset , FrameReg ) ; MI . setDesc ( TII . get ( <STR_LIT> ) ) ; MI . getOperand ( <NUM_LIT> ) . setReg ( SrcOddReg ) ; Offset += <NUM_LIT> ; } else if ( MI . getOpcode ( ) == <STR_LIT> ) { const TargetInstrInfo & TII = * Subtarget . getInstrInfo ( ) ; Register DestReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register DestEvenReg = getSubReg ( DestReg , <STR_LIT> ) ; Register DestOddReg = getSubReg ( DestReg , <STR_LIT> ) ; MachineInstr * LdMI = BuildMI ( * MI . getParent ( ) , II , dl , TII . get ( <STR_LIT> ) , DestEvenReg ) . addReg (


<s> return getPCRelEncoding ( MI , OpNum , Fixups , <STR_LIT>


<s> bool <ISA_LIT>AsmParser :: expandLoadImm ( MCInst & Inst , bool Is32BitImm , SMLoc IDLoc , MCStreamer & Out , const MCSubtargetInfo * STI ) { const MCOperand & ImmOp = Inst . getOperand ( <NUM_LIT> ) ; assert ( ImmOp . isImm ( ) && <STR_LIT> ) ; const MCOperand & DstRegOp = Inst . getOperand ( <NUM_LIT> ) ; assert ( DstRegOp . isReg ( ) && <STR_LIT> ) ; if ( loadImmediate ( ImmOp . getImm ( ) , DstRegOp . getReg ( ) , <STR_LIT> , Is32BitImm , false , IDLoc , Out , STI ) ) return true ; return false


<s> const <ISA_LIT>RegisterInfo * RI = TM . getRegisterInfo ( ) ; MachineLocation Dst ( MachineLocation :: VirtualFP ) ; MachineLocation Src ( RI -> getStackRegister ( ) , stackGrowth ) ; Moves . push_back ( MachineMove ( <NUM_LIT> , Dst , Src ) ) ; MachineLocation CSDst ( RI -> getStackRegister ( ) , stackGrowth ) ; MachineLocation CSSrc ( RI -> getRARegister


<s> if ( ( mask & S390_SCHED_ATTR_MASK_ENDGROUP ) == <NUM_LIT> ) score += <NUM_LIT> ; if ( sched_state . group_of_two && ( mask & S390_SCHED_ATTR_MASK_GROUPOFTWO ) != <NUM_LIT> ) score += <NUM_LIT> ; break ; case <NUM_LIT> : if ( ( mask & S390_SCHED_ATTR_MASK_CRACKED ) == <NUM_LIT> && ( mask & S390_SCHED_ATTR_MASK_EXPANDED ) == <NUM_LIT> && ( mask & S390_SCHED_ATTR_MASK_GROUPALONE ) == <NUM_LIT> ) score += <NUM_LIT> ; if ( ( mask & S390_SCHED_ATTR_MASK_ENDGROUP ) != <NUM_LIT> ) score += <NUM_LIT> ; if ( ( mask & S390_SCHED_ATTR_MASK_GROUPOFTWO ) != <NUM_LIT> ) score = MAX ( <NUM_LIT> , score - <NUM_LIT> ) ; break ; } if ( s390_tune >= PROCESSOR_2964_Z13 ) { int units , i ; unsigned unit_mask , m = <NUM_LIT> ; unit_mask = s390_get_unit_mask ( insn , & units ) ; gcc_assert ( units <= MAX_SCHED_UNITS ) ; for ( i = <NUM_LIT> ; i < units ; i ++ , m <<= <NUM_LIT> ) if ( m & unit_mask ) score += ( last_scheduled_unit_distance [ i ] [

sched_state . side ] * MAX_SCHED_MIX_SCORE / MAX_SCHED_MIX_DISTANCE ) ;


<s> limit = gen_reg_rtx ( mode ) ; f0 = gen_reg_rtx ( mode ) ; emit_move_insn ( limit , CONST_DOUBLE_FROM_REAL_VALUE ( REAL_VALUE_ATOF ( <STR_LIT> , mode ) , mode ) ) ; emit_cmp_and_jump_insns ( in , limit , GE , NULL_RTX , mode , <NUM_LIT> , neglab ) ; emit_insn ( gen_rtx_SET ( VOIDmode , out , gen_rtx_FIX ( DImode , gen_rtx_FIX ( mode , in ) ) ) ) ; emit_jump_insn ( gen_jump ( donelab


<s> Function * Intr = <STR_LIT> ( F -> getParent ( ) , IntID , Types ) ; return CallInst :: Create ( Intr -> getFunctionType (


<s> if ( ! current_frame_info . initialized ) m32r_compute_frame_size ( get_frame_size ( ) ) ; return <NUM_LIT>


<s> bool decodeDepCtr ( unsigned Code , int & Id , StringRef & Name , unsigned & Val , bool & IsDefault


<s> if ( mode == QImode || ! is_virtual_register ( OP ( opno ) ) ) { OP ( opno ) = move_to_acc ( opno , before ) ; OP ( opno ) = move_acc_to_reg ( OP


<s> SDValue LoSmall = DAG . getNode ( <STR_LIT> , DL , VT , Lo , Shift ) ; LoSmall = DAG . getNode ( <STR_LIT> , DL , VT , LoSmall , Overflow ) ; SDValue LoBig = DAG . getNode ( SRA ? <STR_LIT> : <STR_LIT> , DL , VT , Hi , BigShift ) ; SDValue HiBig = SRA ? DAG . getNode ( <STR_LIT> , DL , VT , Hi , Width1 ) : Zero ; Hi = DAG . getSelectCC ( DL , Shift , Width , HiSmall , HiBig , <STR_LIT> ) ; Lo = DAG . getSelectCC ( DL , Shift , Width , LoSmall , LoBig , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , DL , DAG . getVTList ( VT , VT )


<s> return D ( <STR_LIT> , <STR_LIT> , R (


<s> return llvm :: make_unique < <ISA_LIT>ELFObjectWriter >


<s> const TargetInstrInfo & TII = * MF . getSubtarget ( ) . getInstrInfo ( ) ; MI . setDesc ( TII . get ( <STR_LIT> ) ) ; MI . getOperand ( FIOperandNum ) . ChangeToRegister ( BasePtr , false ) ; if ( Offset == <NUM_LIT> ) return ; unsigned DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( Offset < <NUM_LIT> ) BuildMI ( MBB , std :: next ( II ) , dl , TII . get ( <STR_LIT> ) , DstReg ) . addReg ( DstReg ) . addImm ( - Offset ) ; else BuildMI ( MBB , std :: next ( II ) , dl , TII . get ( <STR_LIT> ) , DstReg ) . addReg ( DstReg ) . addImm ( Offset ) ; return ; } MI . getOperand ( FIOperandNum ) . ChangeToRegister ( BasePtr , false ) ; MI . getOperand ( FIOperandNum + <NUM_LIT> ) . ChangeToImmediate


<s> vresult = vec_vpkswss ( vm1 , vm1 ) ; return ( ( __m64 ) __builtin_unpack_vector_int128 ( ( __vector __int128 )


<s> case Instruction :: FRem : case Instruction :: FPToUI : case Instruction :: FPToSI : case Instruction :: UIToFP : case Instruction :: SIToFP : case Instruction :: FPTrunc : case Instruction :: FPExt : case Instruction :: FCmp : return true ; default : ; } if ( const CallInst * CI = dyn_cast < CallInst > ( I ) ) { DEBUG ( dbgs ( ) << <STR_LIT> << <STR_LIT> ) ; Function & F_ = * CI -> getCalledFunction ( ) ; if ( needsFPFromSig ( F_ ) ) return true ; } } return false


<s> DecodeStatus S = MCDisassembler :: Success ; unsigned Vd = fieldFromInstruction32 ( Val , <NUM_LIT> , <NUM_LIT> ) ; unsigned regs = Val & <NUM_LIT> ; if ( ! Check ( S , DecodeSPRRegisterClass ( Inst , Vd , Address , Decoder ) ) ) return MCDisassembler :: Fail ; for ( unsigned i = <NUM_LIT> ; i < ( regs


<s> unsigned int rs6000_special_round_type_align ( tree type , unsigned int computed , unsigned int specified ) { unsigned int align = MAX ( computed , specified ) ; tree field = TYPE_FIELDS ( type ) ; while ( field != NULL && TREE_CODE ( field ) != FIELD_DECL ) field = DECL_CHAIN ( field ) ; if ( field != NULL && field != type ) { type = TREE_TYPE ( field ) ; while ( TREE_CODE ( type ) == ARRAY_TYPE ) type


<s> unsigned s2 = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned disp4 = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned is32Bit = fieldFromInstruction ( Insn , <NUM_LIT> ,


<s> unsigned NumElts = VT . getVectorNumElements ( ) ; bool In64BitMode = DAG . getTargetLoweringInfo ( ) . isTypeLegal ( <STR_LIT> ) ; if ( ! In64BitMode && VT . getScalarType ( ) == <STR_LIT> ) { ConstVecVT = <STR_LIT> ( <STR_LIT> , NumElts * <NUM_LIT> ) ; Split = true ; } EVT EltVT = ConstVecVT . getScalarType ( ) ; for ( unsigned i = <NUM_LIT> ; i < NumElts ; ++ i ) { bool IsUndef = Values [ i ] < <NUM_LIT> && IsMask ; SDValue OpNode = IsUndef ? DAG . getUNDEF ( EltVT ) : DAG . getConstant ( Values [ i ] , dl , EltVT ) ; Ops . push_back ( OpNode ) ; if ( Split ) Ops . push_back ( IsUndef ? DAG . getUNDEF ( EltVT ) : DAG . getConstant ( <NUM_LIT> , dl , EltVT


<s> Type * DstTy = I -> getType ( ) ; if ( ! isTypeLegal ( DstTy , DstVT ) ) return false ; if ( DstVT != <STR_LIT> ) return false ; Value * Src = I -> getOperand ( <NUM_LIT> ) ; Type * SrcTy = Src -> getType ( ) ; if ( ! isTypeLegal ( SrcTy , SrcVT ) ) return false ; if ( SrcVT != <STR_LIT> && SrcVT != <STR_LIT> ) return false ; unsigned SrcReg = getRegForValue ( Src


<s> rtx addr_rtx = ( XEXP ( mem , <NUM_LIT> ) ) ; if ( GET_CODE ( addr_rtx ) == PRE_MODIFY ) addr_rtx = XEXP ( addr_rtx , <NUM_LIT> ) ; while ( GET_CODE ( addr_rtx ) == PLUS && CONST_INT_P ( XEXP ( addr_rtx , <NUM_LIT> ) ) ) addr_rtx = XEXP ( addr_rtx , <NUM_LIT> ) ; if ( ! REG_P ( addr_rtx


<s> parseLiteralValues ( SIZE_LONG , DirectiveID . getLoc ( ) ) ; } else if ( IDVal . lower ( ) == <STR_LIT> || IDVal . lower ( ) == <STR_LIT> ) { parseLiteralValues ( SIZE_WORD , DirectiveID . getLoc ( ) ) ; } else if ( IDVal . lower


<s> MCCodeEmitter * llvm :: create<ISA_LIT>MCCodeEmitterEL ( const MCInstrInfo & MCII , const MCRegisterInfo & MRI , const MCSubtargetInfo & STI


<s> SDValue Op = N -> getOperand ( <NUM_LIT> ) ; unsigned OpOpcode = Op . getNode ( ) -> getOpcode ( ) ; if ( ! Subtarget -> hasNEON ( ) || ! N -> getValueType ( <NUM_LIT> ) . isVector ( ) || ( OpOpcode != <STR_LIT> && OpOpcode != <STR_LIT> ) ) return SDValue ( ) ; uint64_t C ; SDValue ConstVec = N -> getOperand ( <NUM_LIT> ) ; bool isSigned = OpOpcode == <STR_LIT> ; if ( ConstVec . getOpcode ( ) != <STR_LIT> || ! isConstVecPow2 ( ConstVec , isSigned , C ) ) return SDValue ( ) ; MVT FloatTy = N -> getSimpleValueType ( <NUM_LIT> ) . getVectorElementType ( ) ; MVT IntTy = Op . getOperand ( <NUM_LIT> ) . getSimpleValueType ( ) . getVectorElementType ( ) ; if ( FloatTy . getSizeInBits ( ) != <NUM_LIT> || IntTy . getSizeInBits ( ) > <NUM_LIT> ) { return SDValue ( ) ; } SDValue ConvInput = Op . getOperand ( <NUM_LIT> ) ; unsigned NumLanes = Op . getValueType ( ) .


<s> static const TargetRegisterClass * const SingleFloatOnlyCalleeSavedRC [ ] = { & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , &


<s> static bool isVectorShift ( SDValue Op , SDValue Mask , SelectionDAG & DAG , bool & isLeft , SDValue & ShVal , unsigned & ShAmt ) { unsigned NumElems = Mask . getNumOperands ( ) ; isLeft = true ; unsigned NumZeros = getNumOfConsecutiveZeros ( Op , Mask , NumElems , true , DAG ) ; if ( ! NumZeros ) { isLeft = false ; NumZeros = getNumOfConsecutiveZeros ( Op , Mask , NumElems , false , DAG ) ; if ( ! NumZeros ) return false ; } bool SeenV1 = false ; bool SeenV2 = false ; for ( unsigned i = NumZeros ; i < NumElems ; ++ i ) { unsigned Val = isLeft ? ( i - NumZeros ) : i ; SDValue Idx = Mask . getOperand ( isLeft ? i : ( i - NumZeros ) ) ; if ( Idx . getOpcode ( ) == <STR_LIT> ) continue ; unsigned Index = cast < ConstantSDNode > ( Idx ) -> getZExtValue ( ) ; if ( Index < NumElems ) SeenV1 = true ; else { Index -= NumElems


<s> void <ISA_LIT>InstPrinter :: printSBitModifierOperand ( const MCInst * MI , unsigned OpNum , raw_ostream & O ) { if ( MI -> getOperand ( OpNum ) . getReg ( ) ) { assert ( MI -> getOperand ( OpNum ) . getReg ( ) == <STR_LIT> && <STR_LIT> ) ; O <<


<s> int nds32_can_use_bclr_p ( int ival ) { int one_bit_count ; one_bit_count = popcount_hwi ( ( unsigned HOST_WIDE_INT ) ( ~ ival


<s> unsigned Type = ( unsigned ) ELF :: R_MIPS_NONE ; unsigned Kind = ( unsigned ) Fixup . getKind ( ) ; switch ( Kind ) { default : llvm_unreachable ( <STR_LIT> ) ; case FK_Data_4 : Type = ELF :: R_MIPS_32 ; break ; case FK_GPRel_4 : Type = ELF :: R_MIPS_GPREL32 ; break ; case <STR_LIT> : Type = ELF :: R_MIPS_GPREL16 ; break ; case <STR_LIT> : Type = ELF :: R_MIPS_26 ; break ; case <STR_LIT> : Type = ELF :: R_MIPS_CALL16 ; break ; case <STR_LIT> : case <STR_LIT> : Type = ELF :: R_MIPS_GOT16 ; break ; case <STR_LIT> : Type = ELF :: R_MIPS_HI16 ; break ; case <STR_LIT> : Type = ELF :: R_MIPS_LO16 ; break ; case <STR_LIT> : Type = ELF :: R_MIPS_TLS_GD ; break ; case <STR_LIT> : Type = ELF :: R_MIPS_TLS_GOTTPREL ; break ; case <STR_LIT> : Type = ELF :: R_MIPS_TLS_TPREL_HI16 ; break ; case <STR_LIT> : Type = ELF :: R_MIPS_TLS_TPREL_LO16 ; break ; case <STR_LIT> : Type = ELF ::


<s> bool isVoidFunc = ( F -> getReturnType ( ) -> getTypeID ( ) == Type :: VoidTyID ) ; if ( isVoidFunc ) FuncInfo -> setReservedFrameCount


<s> SmallVector < std :: pair < MachineOperand * , int64_t > , <NUM_LIT> > Result ; if ( MI . getOpcode ( ) == <STR_LIT> ) { static const unsigned OpTable [ <NUM_LIT> ] [ <NUM_LIT> ] = { { <STR_LIT> :: src0_X , <STR_LIT> :: src0_sel_X } , { <STR_LIT> :: src0_Y , <STR_LIT> :: src0_sel_Y } , { <STR_LIT> :: src0_Z , <STR_LIT> :: src0_sel_Z } , { <STR_LIT> :: src0_W , <STR_LIT> :: src0_sel_W } , { <STR_LIT> :: src1_X , <STR_LIT> :: src1_sel_X } , { <STR_LIT> :: src1_Y , <STR_LIT> :: src1_sel_Y } , { <STR_LIT> :: src1_Z , <STR_LIT> :: src1_sel_Z } , { <STR_LIT> :: src1_W , <STR_LIT> :: src1_sel_W } , } ; for ( const auto & Op : OpTable ) { MachineOperand & MO = MI . getOperand ( getOperandIdx ( MI . getOpcode ( ) , Op [ <NUM_LIT> ] ) ) ; Register Reg = MO . getReg ( ) ; if ( Reg == <STR_LIT> ) { MachineOperand & Sel = MI . getOperand ( getOperandIdx ( MI . getOpcode ( ) , Op [ <NUM_LIT> ] ) ) ; Result . push_back ( std :: make_pair ( & MO , Sel . getImm ( ) ) ) ; continue ; } } return Result ; } static const unsigned OpTable [ <NUM_LIT> ] [ <NUM_LIT> ] = { { <STR_LIT> :: src0 , <STR_LIT> :: src0_sel } , { <STR_LIT> :: src1 , <STR_LIT> :: src1_sel } , { <STR_LIT> :: src2 , <STR_LIT> :: src2_sel } , } ; for ( const auto & Op : OpTable ) { int SrcIdx = getOperandIdx ( MI . getOpcode ( ) , Op [ <NUM_LIT> ] ) ; if ( SrcIdx < <NUM_LIT> ) break ; MachineOperand & MO = MI . getOperand ( SrcIdx ) ; Register Reg = MO . getReg ( ) ; if ( Reg == <STR_LIT> ) { MachineOperand & Sel = MI . getOperand ( getOperandIdx ( MI . getOpcode ( ) , Op [ <NUM_LIT> ] ) ) ; Result . push_back ( std :: make_pair ( & MO , Sel . getImm ( ) ) ) ; continue ; } if ( Reg == <STR_LIT> ) { MachineOperand & Operand = MI . getOperand ( getOperandIdx ( MI . getOpcode ( ) , <STR_LIT> :: literal ) ) ; if ( Operand . isImm ( ) ) { Result . push_back ( std :: make_pair ( & MO , Operand . getImm ( ) ) ) ; continue ; } assert ( Operand . isGlobal ( ) ) ; } Result . push_back ( std :: make_pair ( & MO , <NUM_LIT> ) ) ; } return Result


<s> if ( NumVals != <NUM_LIT> ) return true ; unsigned RegOp = OpNo + <NUM_LIT> ; if ( RegOp >= MI -> getNumOperands ( ) ) return true ; const MachineOperand & MO = MI -> getOperand ( RegOp ) ; if ( ! MO . isReg ( ) ) return true ; Register Reg = MO . getReg ( ) ; O << <ISA_LIT>InstPrinter :: getRegisterName ( Reg ) ; return false ; } default : return AsmPrinter :: PrintAsmOperand ( MI , OpNo , ExtraCode , O ) ; } } printOperand ( MI , OpNo , O ) ; return


<s> if ( GET_CODE ( x ) != REG ) break ; case REG : ret = frv_regno_ok_for_base_p ( REGNO ( x ) , strict_p ) ; break ; case PRE_MODIFY : x0 = XEXP ( x , <NUM_LIT> ) ; x1 = XEXP ( x , <NUM_LIT> ) ; if ( GET_CODE ( x0 ) != REG || ! frv_regno_ok_for_base_p ( REGNO ( x0 ) , strict_p ) || GET_CODE ( x1 ) != PLUS || ! rtx_equal_p ( x0 , XEXP ( x1 , <NUM_LIT> ) ) || GET_CODE ( XEXP ( x1 , <NUM_LIT> ) ) != REG || ! frv_regno_ok_for_base_p ( REGNO ( XEXP ( x1 , <NUM_LIT> ) ) , strict_p ) ) break ; ret = <NUM_LIT> ; break ; case CONST_INT : if ( condexec_p ) ret = FALSE ; else { ret = IN_RANGE_P ( INTVAL ( x ) , - <NUM_LIT> , <NUM_LIT> ) ; if ( ret && GET_MODE_SIZE ( mode ) > UNITS_PER_WORD ) ret = IN_RANGE_P ( INTVAL ( x ) + GET_MODE_SIZE ( mode ) - <NUM_LIT> , - <NUM_LIT> , <NUM_LIT> ) ; } break ; case PLUS : x0 = XEXP ( x , <NUM_LIT> ) ; x1 = XEXP ( x , <NUM_LIT> ) ; if ( GET_CODE ( x0 ) == SUBREG ) x0 = SUBREG_REG ( x0 ) ; if ( GET_CODE ( x0 ) != REG ) break ; regno0 = REGNO ( x0 ) ; if ( ! frv_regno_ok_for_base_p ( regno0


<s> Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT>


<s> __ev64_opaque__ t ; t = __ev_mwhssf ( a , b ) ; return __ev_mwsmian ( t , ( ( __ev64_s32__ ) {


<s> uint64_t Value = MI -> getOperand ( OpNum ) . getImm ( ) ; assert ( Value < <NUM_LIT> &&


<s> bool <ISA_LIT>AsmParser :: ParseDirective


<s> if ( MaxLHS == Op1 ) SubusLHS = MaxRHS ; else if ( MaxRHS == Op1 ) SubusLHS = MaxLHS ; else return SDValue ( ) ; } else if ( Op1 . getOpcode ( ) == <STR_LIT> ) { SubusLHS = Op0 ; SDValue MinLHS = Op1 . getOperand ( <NUM_LIT> ) ; SDValue MinRHS = Op1 . getOperand ( <NUM_LIT> ) ; if ( MinLHS == Op0 ) SubusRHS = MinRHS ; else if ( MinRHS == Op0 ) SubusRHS = MinLHS ; else return SDValue ( ) ; } else return SDValue ( ) ; if ( VT != <STR_LIT> && VT != <STR_LIT> && VT != <STR_LIT> ) return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , VT , SubusLHS , SubusRHS ) ; KnownBits Known ; DAG . computeKnownBits ( SubusLHS , Known ) ; unsigned NumZeros = Known . countMinLeadingZeros ( ) ; if ( ( VT == <STR_LIT> && NumZeros < <NUM_LIT> ) || NumZeros < <NUM_LIT> ) return SDValue ( ) ; EVT ExtType = SubusLHS . getValueType ( ) ; EVT ShrinkedType ; if ( VT == <STR_LIT> || VT == <STR_LIT> ) ShrinkedType = <STR_LIT> ; else ShrinkedType = NumZeros >= <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; SDValue SaturationConst = DAG . getConstant ( APInt :: getLowBitsSet ( ExtType . getScalarSizeInBits ( ) , ShrinkedType . getScalarSizeInBits ( )


<s> riscv_move_integer ( dest , dest , INTVAL ( src ) , mode , FALSE ) ; return ; } if ( riscv_split_symbol ( dest , src , MAX_MACHINE_MODE , & src , FALSE ) ) { riscv_emit_set ( dest , src ) ; return ; } if ( riscv_tls_symbol_p ( src ) ) { riscv_emit_move ( dest , riscv_legitimize_tls_address ( src ) ) ; return ; } split_const ( src , & base , & offset ) ; if ( offset != const0_rtx && ( targetm . cannot_force_const_mem ( mode , src ) || can_create_pseudo_p ( ) ) ) { base = riscv_force_temporary ( dest , base , FALSE ) ; riscv_emit_move ( dest , riscv_add_offset ( NULL , base , INTVAL ( offset ) ) ) ; return ; } src = force_const_mem ( mode , src


<s> if ( ! SetHiMI -> getOperand ( <NUM_LIT> ) . isImm ( ) ) return false ; int64_t imm = SetHiMI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( ! isInt < <NUM_LIT> > ( imm ) ) return false ; imm = ( imm << <NUM_LIT> ) & <NUM_LIT> ; assert ( RestoreMI -> getOpcode ( ) == <STR_LIT> ) ; RestoreMI -> setDesc ( TII -> get ( <STR_LIT> ) ) ; RestoreMI -> getOperand ( <NUM_LIT> ) . setReg (


<s> SDValue FrameAddr = DAG . getCopyFromReg ( DAG . getEntryNode ( ) , dl , FrameReg , VT ) ; while ( Depth -- ) FrameAddr = DAG . getLoad ( VT , dl , DAG . getEntryNode ( ) , FrameAddr , MachinePointerInfo

( ) , false , false , false , <NUM_LIT> ) ;


<s> Waitcnt = packBits ( Vmcnt , Waitcnt , getVmcntBitShiftLo ( Version . Major ) , getVmcntBitWidthLo ( Version . Major ) ) ; return packBits ( Vmcnt >> getVmcntBitWidthLo ( Version . Major ) , Waitcnt , getVmcntBitShiftHi ( Version .

Major ) , getVmcntBitWidthHi ( Version . Major ) ) ;


<s> const <ISA_LIT>Subtarget & Subtarget = MF -> getSubtarget < <ISA_LIT>Subtarget > ( ) ; const Function * F = MF -> getFunction ( ) ; if ( F -> hasFnAttribute ( <STR_LIT> ) ) { if ( Subtarget . has<ISA_LIT>64 ( ) ) return Subtarget . has<ISA_LIT>64r6 ( ) ? CSR_Interrupt_64R6_SaveList : CSR_Interrupt_64_SaveList ; else return Subtarget . has<ISA_LIT>32r6 ( ) ? CSR_Interrupt_32R6_SaveList : CSR_Interrupt_32_SaveList ; } if ( Subtarget . isSingleFloat ( ) ) return CSR_SingleFloatOnly_SaveList ; if ( Subtarget . isABI_N64 ( ) )


<s> Operands . push_back ( <STR_LIT> ( <STR_LIT> , Parser . getTok ( ) . getLoc ( ) ) ) ; Parser . Lex ( ) ; return MatchOperand_Success ; } SMLoc VIdx = Parser . getTok ( ) . getLoc ( ) ; const MCExpr * ImmVal ; if ( getParser ( ) . parseExpression ( ImmVal ) ) return MatchOperand_ParseFail ; const MCConstantExpr * expr = dyn_cast < MCConstantExpr > ( ImmVal ) ; if ( ! expr || ! validateMSAIndex ( ( int ) expr -> getValue ( ) , Kind ) ) { Error ( VIdx , <STR_LIT> ) ; return MatchOperand_ParseFail ; } SMLoc E = Parser . getTok ( ) . getEndLoc ( ) ; if ( Parser . getTok ( ) . isNot ( AsmToken :: RBrac ) ) return MatchOperand_ParseFail ; bool insve = Mnemonic -> getToken ( ) == <STR_LIT> || Mnemonic -> getToken ( ) == <STR_LIT> || Mnemonic -> getToken ( ) == <STR_LIT> || Mnemonic -> getToken ( ) == <STR_LIT> ; if ( insve && Operands . size ( ) > <NUM_LIT> ) { if ( expr -> getValue ( ) != <NUM_LIT> ) { Error ( VIdx , <STR_LIT> ) ; return MatchOperand_ParseFail ; } Operands . push_back ( <STR_LIT> ( <STR_LIT> , VIdx ) ) ; } else Operands . push_back ( <STR_LIT> ( expr , VIdx , E ) ) ; Operands . push_back ( <STR_LIT> ( <STR_LIT> , Parser . getTok ( ) . getLoc ( ) ) ) ; Parser . Lex ( ) ; return MatchOperand_Success


<s> if ( Kind . isText ( ) ) return TextSection ; if ( UseCPRel ) { if ( Kind . isMergeable1ByteCString ( ) ) return CStringSection ; if ( Kind . isMergeableConst4 ( ) ) return MergeableConst4Section ; if ( Kind . isMergeableConst8 ( ) ) return MergeableConst8Section ; if ( Kind . isMergeableConst16 ( ) ) return MergeableConst16Section ; } Type * ObjType = GV -> getType ( ) -> getPointerElementType ( ) ; auto & DL = GV -> getParent ( ) -> getDataLayout ( ) ; if ( TM . getCodeModel ( ) == CodeModel :: Small || ! ObjType -> isSized ( ) || DL . getTypeAllocSize ( ObjType ) < CodeModelLargeSize ) { if ( Kind . isReadOnly ( ) ) return UseCPRel ? ReadOnlySection : DataRelROSection ; if ( Kind . isBSS ( ) || Kind . isCommon ( ) ) return BSSSection ; if ( Kind . isDataRel ( ) ) return DataSection ; if ( Kind . isReadOnlyWithRel ( ) ) return DataRelROSection ; } else { if ( Kind . isReadOnly ( ) ) return UseCPRel ? ReadOnlySectionLarge : DataRelROSectionLarge ; if ( Kind . isBSS ( ) || Kind

. isCommon ( ) ) return BSSSectionLarge ;


<s> } switch ( Ext ) { case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O <<


<s> if ( Flag == <NUM_LIT> ) return CC_<ISA_LIT>32_SVR4 ; else if ( Flag == <NUM_LIT> ) return CC_<ISA_LIT>32_SVR4_ByVal ; else if ( Flag == <NUM_LIT> )


<s> bool <ISA_LIT>FrameLowering :: hasReservedCallFrame ( const MachineFunction & MF ) const { return ! MF . getFrameInfo ( ) .


<s> UI != UE ; ) { MachineOperand & StoreMO = * UI ++ ; MachineInstr & StoreMI = * StoreMO . getParent ( ) ; if ( StoreMI . getParent ( ) == MI . getParent ( ) && isPotentialBlockedMemCpyPair ( MI . getOpcode ( ) , StoreMI . getOpcode ( ) ) && isRelevantAddressingMode ( & MI ) && isRelevantAddressingMode ( & StoreMI ) ) { assert ( MI . hasOneMemOperand ( ) && <STR_LIT> ) ; assert ( StoreMI . hasOneMemOperand ( ) && <STR_LIT>


<s> BuildMI ( * MBB , MI , DL , get ( AMDGPU :: S_MOV_B32 ) , OffsetSGPR ) . addImm ( HiOffset ) ; Hi = BuildMI ( * MBB , MI , DL , get ( HalfSGPROp ) , RegHi ) . addOperand ( * SBase ) . addReg ( OffsetSGPR ) ; } else { Hi = BuildMI ( * MBB , MI , DL , get ( HalfImmOp ) , RegHi ) . addOperand ( * SBase ) . addImm ( HiOffset / OffScale ) ; } } else { MachineOperand * SOff = getNamedOperand ( * MI , AMDGPU :: OpName :: soff ) ; Lo = BuildMI ( * MBB , MI , DL , get ( HalfSGPROp ) , RegLo ) . addOperand ( * SBase ) . addOperand ( * SOff ) ; unsigned OffsetSGPR = MRI . createVirtualRegister ( & AMDGPU :: SReg_32RegClass ) ; BuildMI ( * MBB , MI , DL , get ( AMDGPU :: S_ADD_I32 ) , OffsetSGPR ) . addOperand ( * SOff ) . addImm ( HalfSize ) ; Hi = BuildMI ( * MBB , MI , DL , get ( HalfSGPROp ) ) . addOperand ( * SBase ) . addReg ( OffsetSGPR ) ; } unsigned SubLo , SubHi ; switch ( HalfSize ) { case <NUM_LIT> : SubLo = AMDGPU :: sub0 ; SubHi = AMDGPU :: sub1 ; break ; case <NUM_LIT> : SubLo = AMDGPU :: sub0_sub1 ; SubHi = AMDGPU :: sub2_sub3 ; break ; case <NUM_LIT> : SubLo = AMDGPU :: sub0_sub1_sub2_sub3 ; SubHi = AMDGPU :: sub4_sub5_sub6_sub7 ; break ; case <NUM_LIT>


<s> SDValue <ISA_LIT>TargetLowering :: LowerOperation ( SDValue Op , SelectionDAG & DAG ) const { switch ( Op . getOpcode ( ) ) { case <STR_LIT> : return lowerBRCOND ( Op , DAG ) ; case <STR_LIT> : return lowerBlockAddress ( Op , DAG ) ; case <STR_LIT> : return lowerJumpTable ( Op , DAG ) ; case <STR_LIT> : return lowerGlobalAddress ( Op , DAG ) ; case <STR_LIT> : return lowerSELECT ( Op , DAG ) ; } return SDValue


<s> MachineFunction * MF = MI -> getParent ( ) -> getParent ( ) ; <ISA_LIT>MachineFunctionInfo * MFI = MF -> getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; const <ISA_LIT>InstrInfo * TII = ST . getInstrInfo ( ) ; MCPhysReg Reg = MFI -> getVGPRToAGPRSpill ( Index , Lane ) ; if ( Reg == <STR_LIT> ) return MachineInstrBuilder ( ) ; bool IsStore = MI -> mayStore ( ) ; MachineRegisterInfo & MRI = MF -> getRegInfo ( ) ; auto * TRI = static_cast < const <ISA_LIT>RegisterInfo * > ( MRI . getTargetRegisterInfo ( ) ) ; unsigned Dst = IsStore ? Reg : ValueReg ; unsigned Src = IsStore ? ValueReg : Reg ; unsigned Opc = ( IsStore ^ TRI -> isVGPR ( MRI , Reg


<s> if ( ! TARGET_AVX ) return - <NUM_LIT> ; return TARGET_AVX512F ? <NUM_LIT> : TARGET_AVX2 ? <NUM_LIT> : <NUM_LIT> ; case 'd' : if ( ! TARGET_AVX2 ) return - <NUM_LIT> ; return TARGET_AVX512F ? <NUM_LIT> : <NUM_LIT> ; case 'e' : if ( ! TARGET_AVX512F ) return - <NUM_LIT> ; return <NUM_LIT>


<s> SDValue Result = DAG . getBuildVector ( ViaVecTy , DL , makeArrayRef ( Ops , ViaVecTy . getVectorNumElements ( ) ) ) ; if ( ViaVecTy != ResVecTy ) { SDValue One = DAG . getConstant ( <NUM_LIT> , DL , ViaVecTy ) ; Result = DAG . getNode ( <STR_LIT> , DL , ResVecTy , DAG . getNode ( <STR_LIT> , DL , ViaVecTy , Result , One ) ) ; } return Result


<s> int64_t getConstantImm ( ) const { const MCExpr * Val =


<s> else { avr_asm_len ( <STR_LIT> CR_TAB <STR_LIT> CR_TAB <STR_LIT> , op , plen , - <NUM_LIT> ) ; if ( reg_dest != reg_base - <NUM_LIT> && ! reg_unused_after ( insn , base ) ) { avr_asm_len ( TINY_SBIW ( % E1 , % F1 , <NUM_LIT> ) , op , plen


<s> for ( unsigned i = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i ) DAG . getMachineFunction ( ) . getRegInfo ( ) . addLiveOut ( RVLocs [ i ] . getLocReg ( ) ) ; } assert ( ( ( Callee . getOpcode ( ) == <STR_LIT> && cast < RegisterSDNode > ( Callee ) -> getReg ( ) == <STR_LIT> ) || Callee . getOpcode ( ) == <STR_LIT> || Callee . getOpcode ( ) == <STR_LIT> || isa < ConstantSDNode > ( Callee ) ) && <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , & Ops [ <NUM_LIT> ] , Ops . size ( ) ) ; } Chain = DAG . getNode ( CallOpc , dl , NodeTys , & Ops [ <NUM_LIT> ] , Ops . size ( ) ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; if ( ! isTailCall && <ISA_LIT>SubTarget . isSVR4ABI ( ) && <ISA_LIT>SubTarget . is<ISA_LIT>64 ( ) ) { SDVTList VTs = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; if ( CallOpc == <STR_LIT> ) { Chain = DAG . getNode ( <STR_LIT> , dl , VTs , Chain , InFlag ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; } else { InFlag = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , InFlag ) ; } } Chain = DAG . getCALLSEQ_END ( Chain , DAG . getIntPtrConstant ( NumBytes , true ) , DAG . getIntPtrConstant


<s> bool <ISA_LIT>FrameLowering :: hasReservedCallFrame ( const MachineFunction & MF ) const { return ! MF . getFrameInfo ( ) -> hasVarSizedObjects


<s> return TargetIRAnalysis ( [ this ] ( const


<s> SDValue Segment = DAG . getRegister ( <NUM_LIT> , <STR_LIT> ) ; if ( Src . getOpcode ( ) == <STR_LIT> ) Src = getZeroVector ( Op . getValueType ( ) , Subtarget , DAG , dl ) ; SDValue Ops [ ] = { Src , MaskInReg , Base , Scale , Index , Disp , Segment , Chain } ; SDNode * Res = DAG . getMachineNode ( Opc , dl , VTs , Ops ) ; SDValue RetOps [ ] = { SDValue ( Res , <NUM_LIT> ) , SDValue ( Res , <NUM_LIT> ) } ; return DAG . getMergeValues ( RetOps , array_lengthof ( RetOps )


<s> const TargetData * TD = TM -> getTargetData ( ) ; const Type * Ty = C -> getType ( ) ; unsigned ValSize = TD -> getTypeAllocSize ( Ty ) ; <ISA_LIT>Section * Found = NULL ; for ( unsigned i = <NUM_LIT> ; i < IDATASections_ . size ( ) ; i ++ ) { if ( DataBankSize - IDATASections_ [ i ] -> getSize ( ) >= ValSize ) { Found = IDATASections_ [ i ] ; break ; } } if ( ! Found ) { std :: string name = PAN :: getIdataSectionName ( IDATASections_ . size ( ) ) ; Found = get<ISA_LIT>DataSection ( name . c_str ( ) , IDATA ) ; } Found -> Items . push_back (


<s> static void nvptx_asm_declare_constant_name ( FILE * file , const char * name , const_tree exp , HOST_WIDE_INT obj_size ) { write_var_marker ( file , true , false , name ) ; fprintf ( file , <STR_LIT> ) ; tree type = TREE_TYPE ( exp ) ; nvptx_assemble_decl_begin ( file , name , <STR_LIT> , type


<s> O << <STR_LIT> << <STR_LIT> ; return AsmPrinter :: doFinalization (


<s> DataSectionData . setAlignment ( std :: max ( <NUM_LIT> , DataSectionData . getAlignment ( ) ) ) ; BSSSectionData . setAlignment ( std :: max ( <NUM_LIT> , BSSSectionData . getAlignment ( ) ) ) ; if ( T . isArch64Bit ( ) && ( Features & <STR_LIT> ) ) { const MCSectionELF * Sec = Context . getELFSection ( <STR_LIT> , ELF :: SHT_MIPS_OPTIONS , ELF :: SHF_ALLOC | ELF :: SHF_MIPS_NOSTRIP , SectionKind :: getMetadata ( ) , <NUM_LIT> , <STR_LIT> ) ; MCA . getOrCreateSectionData ( * Sec ) . setAlignment ( <NUM_LIT> ) ; OS . SwitchSection ( Sec ) ; OS . EmitIntValue ( <NUM_LIT> , <NUM_LIT> ) ; OS . EmitIntValue ( <NUM_LIT> , <NUM_LIT> ) ; OS . EmitIntValue ( <NUM_LIT> , <NUM_LIT> ) ; OS . EmitIntValue ( <NUM_LIT> , <NUM_LIT> ) ; OS . EmitIntValue ( <NUM_LIT> , <NUM_LIT> ) ; OS . EmitIntValue ( <NUM_LIT> , <NUM_LIT> ) ; OS . EmitIntValue ( <NUM_LIT>


<s> for ( int I = MFI . getObjectIndexBegin ( ) ; I != <NUM_LIT> ; ++ I ) Offset = std :: max ( Offset , - MFI . getObjectOffset ( I ) ) ; for ( const MCPhysReg * R = TRI . getCalleeSavedRegs ( & MF ) ; * R ; ++ R ) { unsigned Size = TRI . getMinimalPhysRegClass ( * R ) ->


<s> } case <STR_LIT> :: offset16_8 : Res = translateMemOffset ( MIOpNo , <STR_LIT> ) ; break ; case <STR_LIT> :: offset32_8 : Res = translateMemOffset ( MIOpNo , <STR_LIT> ) ; break ; case <STR_LIT> :: offset64_8 : Res = translateMemOffset ( MIOpNo , <STR_LIT> ) ; break ; case <STR_LIT> :: offset16_16 : Res = translateMemOffset ( MIOpNo , <STR_LIT> ) ; break ; case <STR_LIT> :: offset32_16 : Res = translateMemOffset ( MIOpNo , <STR_LIT> ) ; break ; case <STR_LIT> :: offset64_16 : Res = translateMemOffset ( MIOpNo , <STR_LIT> ) ; break ; case <STR_LIT> :: offset16_32 : Res = translateMemOffset ( MIOpNo , <STR_LIT> ) ; break ; case <STR_LIT> :: offset32_32 : Res = translateMemOffset ( MIOpNo , <STR_LIT> ) ; break ; case <STR_LIT> :: offset64_32 : Res = translateMemOffset ( MIOpNo , <STR_LIT> ) ; break ; case <STR_LIT> :: offset32_64 : Res = translateMemOffset ( MIOpNo , <STR_LIT> ) ; break ; case <STR_LIT> :: offset64_64 : Res = translateMemOffset ( MIOpNo , <STR_LIT> ) ; break ; case <STR_LIT> :: SSECC : case <STR_LIT> :: u8imm : case <STR_LIT> :: i1imm : case <STR_LIT> :: i8imm : case <STR_LIT> :: i16imm : case <STR_LIT> :: i16i8imm : case <STR_LIT> :: i32imm : case <STR_LIT> :: i32i8imm : case <STR_LIT> :: i32u8imm : case <STR_LIT> :: i64i8imm : case <STR_LIT> :: i64i32imm : case <STR_LIT> :: i64imm : { Res = ConstantInt :: get ( cast < IntegerType > ( getResultTy ( <NUM_LIT> ) ) , getImmOp ( MIOpNo ) ) ; break ; } case <STR_LIT> :: i64i32imm_pcrel : case <STR_LIT> :: brtarget : case <STR_LIT> :: brtarget8 : case <STR_LIT> :: brtarget16 : case <STR_LIT> ::


<s> return ( ( AM2Opc >> <NUM_LIT> ) & <NUM_LIT> ) ? sub :


<s> PrintDebugValueComment ( MI , OS ) ; OutStreamer . EmitRawText ( StringRef ( OS . str ( ) ) ) ; } return ; case <STR_LIT> : if ( OutStreamer . hasRawTextSupport ( ) ) OutStreamer . EmitRawText ( StringRef ( <STR_LIT> ) ) ; return ; case <STR_LIT> : case <STR_LIT> : { unsigned Reg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; OutStreamer . AddComment ( StringRef ( <STR_LIT> ) + <ISA_LIT>ATTInstPrinter :: getRegisterName ( Reg ) ) ; break ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : OutStreamer . AddComment ( <STR_LIT> ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerTlsAddr ( OutStreamer , MCInstLowering , * MI ) ; case <STR_LIT> : { MCSymbol * PICBase = MF -> getPICBaseSymbol ( ) ; OutStreamer . EmitInstruction ( MCInstBuilder ( <STR_LIT> ) . addExpr ( MCSymbolRefExpr :: Create ( PICBase , OutContext ) ) ) ; OutStreamer . EmitLabel (


<s> reportParseError ( <STR_LIT> ) ; return false ; } if ( AssemblerOptions . back ( ) -> isReorder ( ) ) { reportParseError ( <STR_LIT> ) ; return false ; } AssemblerOptions . back ( ) -> setNoMacro ( ) ; getTargetStreamer ( ) . emitDirectiveSetNoMacro ( ) ; Parser . Lex ( ) ; return false


<s> EVT CopyVT = VA . getValVT ( ) ; if ( ( CopyVT == <STR_LIT> || CopyVT == <STR_LIT> ) && ( ( Is64Bit || Ins [ i ] . Flags . isInReg ( ) ) && ! Subtarget -> hasSSE1 ( ) ) ) { report_fatal_error ( <STR_LIT> ) ; } SDValue Val ; if ( VA . getLocReg ( ) == <STR_LIT> || VA . getLocReg ( ) == <STR_LIT> ) { if ( isScalarFPTypeInSSEReg ( VA . getValVT ( ) ) ) CopyVT = <STR_LIT> ; SDValue Ops [ ] = { Chain , InFlag } ; Chain = SDValue ( DAG . getMachineNode ( <STR_LIT> , dl , CopyVT , <STR_LIT> , <STR_LIT> , Ops ) , <NUM_LIT> ) ; Val = Chain . getValue ( <NUM_LIT> ) ; if ( CopyVT != VA . getValVT ( ) ) Val = DAG . getNode ( <STR_LIT> , dl , VA . getValVT ( ) , Val , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; } else


<s> if ( ! BucketChain . Elements [ j ] . Offset ) RemainderOffsetInfo [ <NUM_LIT> ] = std :: make_pair ( <NUM_LIT> , <NUM_LIT> ) ; else { unsigned Remainder = cast < SCEVConstant > ( BucketChain . Elements [ j ] . Offset ) -> getAPInt ( ) . urem ( Form ) ; if ( RemainderOffsetInfo . find ( Remainder ) == RemainderOffsetInfo . end ( ) ) RemainderOffsetInfo [ Remainder ] = std :: make_pair ( j , <NUM_LIT> ) ; else RemainderOffsetInfo [ Remainder ] . second ++ ; } } unsigned MaxCountRemainder = <NUM_LIT> ; for ( unsigned j = <NUM_LIT> ; j < ( unsigned ) Form ; j ++ ) if ( ( RemainderOffsetInfo . find ( j ) != RemainderOffsetInfo . end ( ) ) && RemainderOffsetInfo [ j ] . second > RemainderOffsetInfo

[ MaxCountRemainder ] . second ) MaxCountRemainder = j ;


<s> AddInst = RI . getUniqueVRegDef ( vreg ) ; if ( AddInst == <NUM_LIT> ) return false ; unsigned reg ; int64_t off ; switch ( AddInst -> getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : if ( ! AddInst -> getOperand ( <NUM_LIT> ) . isImm ( ) ) return false ; reg = AddInst -> getOperand ( <NUM_LIT> ) . getReg ( ) ; off = AddInst -> getOperand ( <NUM_LIT> ) . getImm ( ) ; break ; default : return


<s> for ( offset = <NUM_LIT> , chainp = & aof_pic_chain ; * chainp ; offset += <NUM_LIT> , chainp = & ( * chainp ) -> next ) if ( ( * chainp ) -> symname == XSTR ( x , <NUM_LIT> ) ) return plus_constant ( aof_pic_label , offset ) ; * chainp = ( struct pic_chain * ) xmalloc ( sizeof ( struct pic_chain ) ) ; ( * chainp ) -> next = NULL ; ( * chainp ) -> symname = XSTR ( x , <NUM_LIT> ) ; return plus_constant ( aof_pic_label ,


<s> return <STR_LIT> ; case LT : return <STR_LIT> ; case GE : return <STR_LIT> ; case LE : return <STR_LIT> ; case ORDERED : return <STR_LIT> ; case UNORDERED : return <STR_LIT> ; case UNEQ : return <STR_LIT> ; case UNGE : return <STR_LIT> ; case UNGT : return <STR_LIT> ; case UNLE : return <STR_LIT> ; case UNLT : return <STR_LIT> ; case LTGT : return


<s> EmitLabel ( Symbol , Loc , F ) ; Symbol -> setType ( ELF :: STT_NOTYPE ) ; Symbol -> setBinding ( ELF :: STB_LOCAL


<s> bool AMDGPUDAGToDAGISel :: SelectGlobalValueVariableOffset ( SDValue Addr , SDValue & BaseReg , SDValue & Offset ) { if ( ! isa < ConstantSDNode > ( Addr ) ) { BaseReg =


<s> Immediate |= ( cast < ConstantSDNode > ( In ) -> getZExtValue ( ) & <NUM_LIT> ) << idx ; HasConstElts = true ; } if ( SplatIdx < <NUM_LIT> ) SplatIdx = idx ; else if ( In != Op . getOperand ( SplatIdx ) ) IsSplat = false ; } if ( IsSplat ) { SDValue Cond = Op . getOperand ( SplatIdx ) ; assert ( Cond . getValueType ( ) == <STR_LIT> && <STR_LIT> ) ; if ( Cond . getOpcode ( ) != <STR_LIT> ) Cond = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Cond , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; return DAG . getSelect ( dl , VT , Cond , DAG . getConstant ( <NUM_LIT> , dl , VT ) , DAG . getConstant ( <NUM_LIT> , dl , VT ) ) ; } SDValue DstVec ; if ( HasConstElts ) { if ( VT == <STR_LIT> && ! Subtarget . is64Bit ( ) ) { SDValue ImmL = DAG . getConstant ( Lo_32 ( Immediate ) , dl , <STR_LIT> ) ; SDValue ImmH = DAG . getConstant ( Hi_32 ( Immediate ) , dl , <STR_LIT> ) ; ImmL = DAG . getBitcast ( <STR_LIT> , ImmL ) ; ImmH = DAG . getBitcast ( <STR_LIT> , ImmH ) ; DstVec = DAG . getNode ( <STR_LIT> , dl ,


<s> static inline SlotWithTag getTombstoneKey


<s> if ( ! CONSTANT_ADDRESS_P ( x ) ) return false ; if ( flag_pic && ! ( strict_p && TARGET_PCREL ) && symbolic_operand ( x , VOIDmode ) ) return false ; if ( M68K_OFFSETS_MUST_BE_WITHIN_SECTIONS_P && reach


<s> if ( ! ( I -> isBranch ( ) ) && ! ( I -> mayLoad ( ) ) && ! ( I -> mayStore ( ) ) && ! ( I -> isCall ( ) ) && ! ( I -> isReturn ( ) ) && ! ( I -> isCompare ( ) ) && ! ( I -> getOpcode ( ) == <STR_LIT> || ( I -> getOpcode ( ) > <NUM_LIT> && I -> getOpcode ( ) < <NUM_LIT> ) ) ) { MachineInstr * slaveinst1 = MF . CloneMachineInstr ( & * I ) ; MachineInstr * slaveinst2 = MF . CloneMachineInstr ( & * I ) ; slaveinst1 -> setFlags ( <NUM_LIT> ) ; slaveinst2 -> setFlags ( <NUM_LIT> ) ; for ( unsigned int opcount = <NUM_LIT> ; opcount < I -> getNumOperands ( ) ; opcount ++ ) { if ( I -> getOperand ( opcount ) . isReg ( ) ) { slaveinst1 -> getOperand ( opcount ) . setReg ( getSlaveReg1 ( I -> getOperand ( opcount ) . getReg ( ) ) ) ; slaveinst2 -> getOperand ( opcount ) . setReg ( getSlaveReg2 ( I


<s> static rtx find_addr_reg ( rtx addr ) { while ( GET_CODE ( addr ) == PLUS ) { if ( GET_CODE ( XEXP ( addr , <NUM_LIT> ) ) == REG ) addr = XEXP ( addr , <NUM_LIT> ) ; else if ( GET_CODE ( XEXP ( addr , <NUM_LIT> ) ) == REG ) addr = XEXP ( addr ,


<s> case <STR_LIT> : Opc8 = <STR_LIT> ; ShiftAmount = ShiftAmount % VT . getSizeInBits ( ) ; break ; case <STR_LIT> : Opc8 = <STR_LIT> ; break ; case <STR_LIT> : Opc8 = <STR_LIT> ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } if ( VT . getSizeInBits ( ) == <NUM_LIT> ) { if ( Op . getOpcode ( ) == <STR_LIT> && <NUM_LIT> <= ShiftAmount && ShiftAmount < <NUM_LIT> ) { Victim = DAG . getNode ( <STR_LIT> , dl , VT , Victim ) ; Victim = DAG . getNode ( <STR_LIT> , dl , VT , Victim , DAG . getConstant ( <NUM_LIT> , dl , VT ) ) ; ShiftAmount -= <NUM_LIT> ; } else if ( Op . getOpcode ( ) == <STR_LIT> && <NUM_LIT> <= ShiftAmount && ShiftAmount < <NUM_LIT> ) { Victim = DAG . getNode ( <STR_LIT> , dl , VT , Victim ) ; Victim = DAG . getNode ( <STR_LIT> , dl , VT , Victim , DAG . getConstant ( <NUM_LIT> , dl , VT ) ) ; ShiftAmount -= <NUM_LIT> ; } else if ( Op . getOpcode ( ) == <STR_LIT> && ShiftAmount == <NUM_LIT> ) { Victim = DAG . getNode ( <STR_LIT> , dl , VT , Victim ) ; ShiftAmount = <NUM_LIT> ; } else if ( Op . getOpcode ( ) == <STR_LIT> && ShiftAmount == <NUM_LIT> ) { Victim = DAG . getNode ( <STR_LIT> , dl , VT , Victim ) ; ShiftAmount = <NUM_LIT> ; } else if ( Op . getOpcode ( ) == <STR_LIT> && ShiftAmount == <NUM_LIT> ) { Victim = DAG . getNode ( <STR_LIT> , dl , VT , Victim ) ; ShiftAmount = <NUM_LIT> ; } } while ( ShiftAmount -- ) { Victim = DAG . getNode ( Opc8 , dl , VT , Victim ) ; } return


<s> case FK_PCRel_1 : case FK_Data_1 : return <NUM_LIT> ; case FK_PCRel_2 : case FK_Data_2 : return <NUM_LIT> ; case FK_PCRel_4 : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case FK_Data_4 :


<s> uint64_t StackSize = MFI . getStackSize ( ) ; uint64_t MaxAlign = calculateMaxStackAlign ( MF ) ; unsigned CSSize = <ISA_LIT>FI -> getCalleeSavedFrameSize ( ) ; uint64_t NumBytes = <NUM_LIT> ; if ( RetOpcode && * RetOpcode == <STR_LIT> ) { assert ( ! isAsynchronousEHPersonality ( classifyEHPersonality ( MF . getFunction ( ) -> getPersonalityFn ( ) ) ) && <STR_LIT> ) ; NumBytes = getWinEHFuncletFrameSize ( MF ) ; assert ( hasFP ( MF ) && <STR_LIT> ) ; TargetMBB = MBBI -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; BuildMI ( MBB , MBBI , DL , TII . get ( Is64Bit ? <STR_LIT> : <STR_LIT> ) , MachineFramePtr ) . setMIFlag ( MachineInstr :: FrameDestroy ) ; } else if ( RetOpcode && * RetOpcode == <STR_LIT> ) { NumBytes = getWinEHFuncletFrameSize ( MF ) ; assert ( hasFP ( MF ) && <STR_LIT> ) ; BuildMI ( MBB , MBBI , DL , TII . get ( Is64Bit ? <STR_LIT> : <STR_LIT> ) , MachineFramePtr ) . setMIFlag ( MachineInstr :: FrameDestroy ) ; } else if ( hasFP ( MF ) ) { uint64_t FrameSize = StackSize - SlotSize ; NumBytes = FrameSize - CSSize ; if ( TRI -> needsStackRealignment ( MF ) && ! IsWin64Prologue ) NumBytes = alignTo ( FrameSize , MaxAlign ) ; BuildMI ( MBB , MBBI , DL , TII . get ( Is64Bit ? <STR_LIT> : <STR_LIT> ) , MachineFramePtr ) . setMIFlag ( MachineInstr :: FrameDestroy ) ; } else { NumBytes = StackSize - CSSize ; } uint64_t SEHStackAllocAmt = NumBytes ; while ( MBBI != MBB . begin ( ) ) { MachineBasicBlock :: iterator PI = std :: prev ( MBBI ) ; unsigned Opc = PI -> getOpcode (


<s> auto SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned LoadOpcode = ( Width == <NUM_LIT> ) ? <STR_LIT> : <STR_LIT> ; unsigned StoreOpcode = ( Width == <NUM_LIT> ) ? <STR_LIT> : <STR_LIT> ; buildMI ( MBB , MBBI , LoadOpcode , DstReg ) . addReg ( PtrOp . getReg ( ) ) ; buildMI ( MBB , MBBI , ArithOpcode , DstReg ) . addReg ( DstReg ) .


<s> auto MovMI = MIB . buildInstr ( <STR_LIT> , { DstReg } , { } ) . addJumpTableIndex ( JTI , <STR_LIT> ) . addJumpTableIndex ( JTI , <STR_LIT> | <STR_LIT> ) ; I . eraseFromParent ( ) ; return constrainSelectedInstRegOperands ( * MovMI , TII ,


<s> bool <ISA_LIT>TargetMachine :: addPreEmitPass ( PassManagerBase & PM , CodeGenOpt :: Level OptLevel ) { PM . add ( create<ISA_LIT>FPMoverPass ( * this ) ) ; PM . add ( create<ISA_LIT>DelaySlotFillerPass ( *


<s> bool isPIC = ( TM . getRelocationModel ( ) == Reloc :: PIC_ ) ; bool isCodeLarge = ( TM . getCodeModel ( ) == CodeModel :: Large ) ; if ( MI -> getOpcode ( ) == <STR_LIT> && ! MO . isReg ( ) && ! MO . isImm ( ) ) { if ( ( isPIC ) && ( isCodeLarge ) ) O << <STR_LIT> ; else O << <STR_LIT> ; closeP = true ; } else if ( ( MI -> getOpcode ( ) == <STR_LIT> ) && ! MO . isReg ( ) && ! MO . isImm ( ) ) { const MachineOperand & firstMO = MI -> getOperand ( opNum - <NUM_LIT> ) ; if ( firstMO . getReg ( ) == <STR_LIT> ) O << <STR_LIT> ; else O << <STR_LIT> ; closeP = true ; } else if ( ( isPIC ) && ( MI -> getOpcode ( ) == <STR_LIT> ) && ( ! MO . isReg


<s> MCAsmParser & Parser = getParser ( ) ; Parser . Lex ( ) ; SMLoc SRegLoc = getLoc ( ) ; int RegNum = tryParseRegister ( ) ; RegKind RegisterKind = RegKind :: Scalar ; if ( RegNum == - <NUM_LIT> ) { StringRef Kind ; RegisterKind = RegKind :: NeonVector ; OperandMatchResultTy Res = tryParseVectorRegister ( RegNum , Kind , RegKind :: NeonVector ) ; if ( Res == MatchOperand_ParseFail ) return true ; if ( Res == MatchOperand_Success && ! Kind . empty ( ) ) return Error ( SRegLoc , <STR_LIT> ) ; } if ( RegNum == - <NUM_LIT> ) { StringRef Kind ; RegisterKind = RegKind :: SVEDataVector ; OperandMatchResultTy Res = tryParseVectorRegister ( RegNum , Kind , RegKind :: SVEDataVector ) ; if ( Res == MatchOperand_ParseFail ) return true ; if ( Res == MatchOperand_Success && ! Kind . empty ( ) ) return Error ( SRegLoc , <STR_LIT> ) ; } if ( RegNum == - <NUM_LIT> ) { StringRef Kind


<s> value0 = expand_normal ( arg0 ) ; create_input_operand ( & ops [ <NUM_LIT> ] , value0 , TYPE_MODE ( TREE_TYPE ( arg0 ) ) ) ; if ( ! maybe_expand_insn ( icode , <NUM_LIT> , ops ) ) error ( <STR_LIT> ) ; return target


<s> if ( ! Subtarget . hasAVX512 ( ) && Super -> getSize ( ) == RC -> getSize ( ) ) return Super ; break ; case <STR_LIT> : case <STR_LIT> : if ( ! Subtarget . hasVLX ( ) && Super -> getSize ( ) == RC -> getSize ( ) ) return Super ; break ; case <STR_LIT> : case <STR_LIT> : if ( ! Subtarget . hasVLX ( ) ) break ; LLVM_FALLTHROUGH ; case <STR_LIT> : case <STR_LIT> : if ( ! Subtarget . hasAVX512 ( ) ) break ; LLVM_FALLTHROUGH ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> return isThumb1 ? Align ( <NUM_LIT> ) : Align ( <NUM_LIT> ) ; case <STR_LIT> : return isThumb1 ? Align ( <NUM_LIT> ) : Align ( <NUM_LIT> ) ; case <STR_LIT> : return Align ( <NUM_LIT> ) ; case <STR_LIT>


<s> unsigned Reg = CSI [ i - <NUM_LIT> ] . getReg ( ) ; MBB . addLiveIn ( Reg ) ; BuildMI ( MBB , MI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( Reg ) .


<s> if ( I >= VRegStackified . size ( ) ) VRegStackified . resize ( I + <NUM_LIT> ) ; VRegStackified . set (


<s> bool hasAbsoluteCall ( ) const { return


<s> [ = ] ( MachineInstrBuilder & MIB ) { MIB . addReg ( Src ) ; } , [ = ] ( MachineInstrBuilder & MIB ) { MIB . addImm ( Mods ) ; } } }


<s> SDValue N0 = N -> getOperand ( <NUM_LIT> ) ; SDValue N1 = N -> getOperand ( <NUM_LIT> ) ; SDLoc DL ( N ) ; if ( VT . isInteger ( ) && N -> getOpcode ( ) == <STR_LIT> && N0 . getOpcode ( ) == <STR_LIT> && N0 . getOperand ( <NUM_LIT> ) == N1 && N1 . getOpcode ( ) == <STR_LIT> && N1 . getOperand ( <NUM_LIT> ) == N0 . getOperand ( <NUM_LIT> ) ) if ( ConstantSDNode * Y1C = dyn_cast < ConstantSDNode > ( N1 . getOperand ( <NUM_LIT> ) ) ) if ( Y1C -> getAPIntValue ( ) == VT . getSizeInBits ( ) - <NUM_LIT> ) { SDValue Neg = DAG . getNode ( <STR_LIT> , DL , DAG . getVTList ( VT , <STR_LIT> ) , DAG . getConstant ( <NUM_LIT> , VT )


<s> unsigned i ; for ( i = <NUM_LIT> ; i < count ; ++ i ) { gcc_assert ( i < MAX_REGS ) ; if ( REG_ORDER [ i ] == BP_REG && hfp


<s> void <ISA_LIT>InstPrinter :: printLdStmModeOperand ( const MCInst * MI , unsigned OpNum , const MCSubtargetInfo & STI , raw_ostream & O ) { <STR_LIT> Mode = <STR_LIT> ( MI -> getOperand ( OpNum ) . getImm ( )


<s> inline hashval_t wrapped_symbol_hasher :: hash ( const value_type * v ) { return htab_hash_string ( v


<s> auto Offset = MI . getOperand ( OpNo ) . getImm ( ) ; assert ( ! <STR_LIT> ( STI ) || isUInt < <NUM_LIT>


<s> unsigned HOST_WIDE_INT temp ; if ( op_const == <NUM_LIT> ) return NULL ; temp = opint [ <NUM_LIT> ] & <NUM_LIT> ; temp |= ( opint [ <NUM_LIT> ] >> <NUM_LIT> ) & <NUM_LIT> ; return build_int_cst ( alpha_dimode_u


<s> SDLoc & DL = CLI . DL ; SmallVectorImpl < <STR_LIT> > & Outs = CLI . Outs ; SmallVectorImpl < SDValue > & OutVals = CLI . OutVals ; SmallVectorImpl < <STR_LIT> > & Ins = CLI . Ins ; SDValue Chain = CLI . Chain ; SDValue Callee = CLI . Callee ; bool & IsTailCall = CLI . IsTailCall ; CallingConv :: ID CallConv = CLI . CallConv ; bool IsVarArg = CLI . IsVarArg ; IsTailCall =


<s> if ( ! getMemOperandsWithOffsetWidth ( MIa , BaseOps0 , Offset0 , Offset0IsScalable , Dummy0 , & RI ) || ! getMemOperandsWithOffsetWidth ( MIb , BaseOps1 , Offset1 , Offset1IsScalable , Dummy1 , & RI ) ) return false ; if ( ! memOpsHaveSameBaseOperands ( BaseOps0 , BaseOps1


<s> int getIntImmCostIntrin ( <STR_LIT> IID , unsigned Idx , const APInt & Imm

, Type * Ty , TTI :: TargetCostKind CostKind ) {


<s> PreservedAnalyses <ISA_LIT>AbstractMemberAccessPass :: run ( Function & F , FunctionAnalysisManager & AM ) { return <ISA_LIT>AbstractMemberAccess ( TM ) . run ( F ) ?

PreservedAnalyses :: none ( ) : PreservedAnalyses :: all ( ) ;


<s> if ( SVT != <STR_LIT> && SVT != <STR_LIT> && SVT != <STR_LIT> && SVT != <STR_LIT> && SVT != <STR_LIT> && SVT != <STR_LIT> ) return SDValue ( ) ; if ( N0 . getOperand ( <NUM_LIT> ) . getValueType ( ) . getVectorElementType ( ) == <STR_LIT> ) return SDValue ( ) ; unsigned Size = VT . getSizeInBits ( ) ; if ( Size > <NUM_LIT> && Subtarget . useAVX512Regs ( ) ) return SDValue ( ) ; <STR_LIT> CC = cast < CondCodeSDNode > ( N0 . getOperand ( <NUM_LIT> ) ) -> get ( ) ; if ( <STR_LIT> ( CC ) ) return SDValue ( ) ; EVT N00VT = N0 . getOperand ( <NUM_LIT> ) . getValueType ( ) ; EVT MatchingVecType = N00VT . changeVectorElementTypeToInteger ( ) ; if ( Size != MatchingVecType . getSizeInBits


<s> LiveRegs . addReg ( SpillReg ) ; MCPhysReg OffsetReg = findScratchNonCalleeSaveRegister ( MF -> getRegInfo ( ) , LiveRegs , <STR_LIT> ) ; BuildMI ( MBB , I , DebugLoc ( ) , TII -> get ( <STR_LIT> ) , OffsetReg ) . addImm ( Offset ) ; BuildMI ( MBB , I , DebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addReg ( SpillReg , RegState :: Kill ) . addReg ( OffsetReg , RegState :: Kill ) . addReg ( ScratchRsrcReg ) . addReg ( SPReg ) . addImm ( <NUM_LIT> ) . addImm

( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ;


<s> void arc_set_default_type_attributes ( tree


<s> MCRegister Reg = <STR_LIT> + RegNo ; Inst . addOperand ( MCOperand :: createReg ( Reg )


<s> inline bool isPCREL ( unsigned Opcode ) { return Opcode == PCREL_WRAPPER || Opcode


<s> assert ( Res || Def -> getOpcode ( ) == TargetOpcode :: G_CONSTANT ) ; if ( Res ) return Res ; } MRI -> replaceRegWith ( I . getOperand ( <NUM_LIT> ) . getReg ( ) , I . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; I . removeFromParent ( ) ; } else if ( I . getNumDefs ( ) == <NUM_LIT> ) { MRI -> setType ( I . getOperand ( <NUM_LIT> ) . getReg ( ) , LLT :: scalar ( <NUM_LIT> ) ) ; } return true ; } if ( I . getNumOperands ( ) !=


<s> unsigned Idx = ( FullSize - <NUM_LIT> - i ) ; CurVal |= static_cast < uint64_t > ( static_cast < uint8_t > ( Data [ Offset + Idx ] ) ) << ( i * <NUM_LIT> ) ; } uint64_t Mask = ( static_cast < uint64_t > ( - <NUM_LIT> ) >> ( <NUM_LIT> - getFixupKindInfo ( Kind ) . TargetSize ) ) ; CurVal |= Value


<s> p = ggc_alloc < extern_list > ( ) ; p -> next


<s> } } int MCOp = <STR_LIT> ( Opcode , Gen ) ; if ( MCOp == - <NUM_LIT> ) return Opcode ; if ( ST . hasGFX90AInsts ( ) ) { uint16_t NMCOp = ( uint16_t ) - <NUM_LIT> ; NMCOp = <STR_LIT> ( Opcode , <STR_LIT> ) ; if ( NMCOp == ( uint16_t ) - <NUM_LIT> ) NMCOp = <STR_LIT> ( Opcode , <STR_LIT> ) ; if ( NMCOp != ( uint16_t ) - <NUM_LIT> ) MCOp = NMCOp ; } if ( MCOp == ( uint16_t ) - <NUM_LIT> ) return - <NUM_LIT> ; if ( isAsmOnlyOpcode ( MCOp ) ) return -


<s> static DecodeStatus decodeRVCInstrRdRs1UImm ( MCInst & Inst , unsigned Insn , uint64_t Address , const MCDisassembler * Decoder ) { DecodeGPRRegisterClass ( Inst , <NUM_LIT> , Address , Decoder ) ; Inst . addOperand ( Inst . getOperand ( <NUM_LIT> ) ) ; uint64_t UImm6 = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> | fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; DecodeStatus Result = decodeUImmOperand < <NUM_LIT> > ( Inst , UImm6 , Address , Decoder ) ; ( void ) Result ; assert ( Result == MCDisassembler :: Success && <STR_LIT> ) ; return MCDisassembler ::


<s> SmallVector < CCValAssign , <NUM_LIT> > ArgLocs ; CCState CCInfo ( CallConv , isVarArg , getTargetMachine ( ) , ArgLocs , * DAG . getContext ( ) ) ; CCInfo . AllocateStack ( <NUM_LIT> , <NUM_LIT> ) ; CCInfo . AnalyzeFormalArguments ( Ins , CC_Blackfin ) ; for ( unsigned i = <NUM_LIT> , e = ArgLocs . size ( ) ; i != e ; ++ i ) { CCValAssign & VA = ArgLocs [ i ] ; if ( VA . isRegLoc ( ) ) { EVT RegVT = VA . getLocVT ( ) ; TargetRegisterClass * RC = VA . getLocReg ( ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; assert ( RC -> contains ( VA . getLocReg ( ) ) && <STR_LIT> ) ; assert ( RC -> hasType ( RegVT ) && <STR_LIT> ) ; unsigned Reg = MF . getRegInfo ( ) . createVirtualRegister ( RC ) ; MF . getRegInfo ( ) . addLiveIn ( VA . getLocReg ( ) , Reg ) ; SDValue ArgValue = DAG . getCopyFromReg ( Chain , dl , Reg , RegVT ) ; if ( VA . getLocInfo ( ) == CCValAssign :: SExt ) ArgValue = DAG . getNode ( <STR_LIT> , dl , RegVT , ArgValue , DAG . getValueType ( VA . getValVT ( ) ) ) ; else if ( VA . getLocInfo ( ) == CCValAssign :: ZExt ) ArgValue = DAG . getNode ( <STR_LIT> , dl , RegVT , ArgValue , DAG . getValueType ( VA . getValVT ( ) ) ) ; if ( VA . getLocInfo ( ) != CCValAssign :: Full ) ArgValue = DAG . getNode ( <STR_LIT> , dl , VA . getValVT ( ) , ArgValue ) ; InVals . push_back ( ArgValue ) ; } else


<s> } } if ( N . getOpcode ( ) != <STR_LIT> && N . getOpcode ( ) != <STR_LIT> && ! CurDAG -> isBaseWithConstantOffset ( N ) ) return false ; if ( N . getOpcode ( ) == <STR_LIT> || N . getOpcode ( ) == <STR_LIT> ) { int RHSC ; if ( isScaledConstantInRange ( N . getOperand ( <NUM_LIT> ) , <NUM_LIT> , - <NUM_LIT> + <NUM_LIT> , <NUM_LIT> , RHSC ) ) return false ; } if ( Subtarget -> isCortexA9 ( ) && ! N . hasOneUse ( ) ) return false ; <STR_LIT> AddSub = N . getOpcode ( ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; <STR_LIT> ShOpcVal = <STR_LIT> ( N . getOperand ( <NUM_LIT> ) ) ; unsigned ShAmt = <NUM_LIT> ; Base = N . getOperand ( <NUM_LIT> ) ; Offset = N . getOperand ( <NUM_LIT> ) ; if ( ShOpcVal != <STR_LIT> ) { if ( ConstantSDNode * Sh = dyn_cast < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ) ) { ShAmt = Sh -> getZExtValue ( ) ; if ( isShifterOpProfitable ( Offset , ShOpcVal , ShAmt ) ) Offset = N . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ; else { ShAmt = <NUM_LIT> ; ShOpcVal = <STR_LIT> ; } } else { ShOpcVal = <STR_LIT> ; } } if ( N . getOpcode ( ) != <STR_LIT> && ShOpcVal == <STR_LIT> && ! ( Subtarget -> isCortexA9 ( ) || N . getOperand ( <NUM_LIT> ) . hasOneUse ( ) ) ) { ShOpcVal = <STR_LIT> ( N . getOperand ( <NUM_LIT> ) ) ; if ( ShOpcVal != <STR_LIT>


<s> return handleSlot ( [ this ] ( auto & I ) -> bool { return TII -> HasFPUDelaySlot ( I ) ;

} , [ this ] ( auto & IInSlot , auto & I ) -> bool {


<s> return ( GV -> getType ( ) -> getAddressSpace ( ) == AMDGPUA<ISA_LIT> . GLOBAL_ADDRESS || GV -> getType ( ) -> getAddressSpace ( ) == AMDGPUA<ISA_LIT> . CONSTANT_ADDRESS ) && !

shouldEmitFixup ( GV ) && ! getTargetMachine ( ) . shouldAssumeDSOLocal ( * GV -> getParent ( ) , GV ) ;


<s> SDLoc dl ( N ) ; MVT IntScalar = <STR_LIT> ( VT . getScalarSizeInBits ( ) ) ; MVT IntVT = <STR_LIT> ( IntScalar , VT . getVectorNumElements ( ) ) ; SDValue Op0 = DAG . getNode ( <STR_LIT> , dl , IntVT , N -> getOperand ( <NUM_LIT> ) ) ; SDValue Op1 = DAG . getNode ( <STR_LIT> , dl , IntVT , N -> getOperand ( <NUM_LIT> ) ) ; unsigned IntOpcode = <NUM_LIT> ; switch ( N -> getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : IntOpcode = <STR_LIT> ; break ; case <STR_LIT> : IntOpcode = <STR_LIT> ; break ; case <STR_LIT> : IntOpcode = <STR_LIT> ; break ; case <STR_LIT> : IntOpcode = <STR_LIT> ; break ; } SDValue IntOp = DAG . getNode ( IntOpcode , dl , IntVT , Op0 , Op1 ) ; return DAG . getNode ( <STR_LIT> , dl , VT , IntOp ) ; } return SDValue (


<s> RHSC >>= <NUM_LIT> ; if ( RHSC >= <NUM_LIT> && RHSC < <NUM_LIT> ) { Base = N . getOperand ( <NUM_LIT> ) ; if ( Base . getOpcode ( ) == <STR_LIT> ) { int FI = cast < FrameIndexSDNode > ( Base ) -> getIndex ( ) ; Base = CurDAG -> getTargetFrameIndex ( FI , TLI . getPointerTy ( ) ) ; } OffImm = CurDAG -> getTargetConstant ( RHSC , <STR_LIT> ) ; return true ; } } } } return false


<s> void addMRSOperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT>


<s> return SelectGlobalAddress ( N , R , false , <NUM_LIT>


<s> LLVMContext * Context = DAG . getContext ( ) ; std :: vector < Constant * > CV0 ; CV0 . push_back ( ConstantInt :: get ( * Context , APInt ( <NUM_LIT> , <NUM_LIT> ) ) ) ; CV0 . push_back ( ConstantInt :: get ( * Context , APInt ( <NUM_LIT> , <NUM_LIT> ) ) ) ; CV0 . push_back ( ConstantInt :: get ( * Context , APInt ( <NUM_LIT> , <NUM_LIT> ) ) ) ; CV0 . push_back ( ConstantInt :: get ( * Context , APInt ( <NUM_LIT> , <NUM_LIT> ) ) ) ; Constant * C0 = ConstantVector :: get ( CV0 ) ; SDValue CPIdx0 = DAG . getConstantPool ( C0 , getPointerTy ( ) , <NUM_LIT> ) ; std :: vector < Constant * > CV1 ; CV1 . push_back ( ConstantFP :: get ( * Context , APFloat ( APInt ( <NUM_LIT> , <NUM_LIT> ) ) ) ) ; CV1 . push_back ( ConstantFP :: get ( * Context , APFloat ( APInt ( <NUM_LIT> ,


<s> } switch_to_section ( bss_section ) ; assemble_name ( stream , name ) ; fprintf ( stream , <STR_LIT> HOST_WIDE_INT_PRINT_UNSIGNED <STR_LIT> , MAX ( size ,


<s> } RegionBegin = Region . first ; RegionEnd = Region . second ; if ( RegionBegin -> getParent ( ) != MBB ) { if ( MBB ) finishBlock ( ) ; MBB = RegionBegin -> getParent ( ) ; startBlock ( MBB ) ; if ( Stage == InitialSchedule ) computeBlockPressure ( MBB ) ; } unsigned NumRegionInstrs = std :: distance ( begin ( ) , end ( ) ) ; enterRegion ( MBB , begin ( ) , end ( ) , NumRegionInstrs ) ; if ( begin ( ) == end ( ) || begin ( ) == std :: prev ( end ( ) ) ) { exitRegion ( ) ; continue ; } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( dbgs ( ) << MF . getName ( ) << <STR_LIT> << printMBBReference ( * MBB ) << <STR_LIT> << MBB -> getName ( ) << <STR_LIT> << * begin ( ) << <STR_LIT> ; if ( RegionEnd != MBB -> end ( ) ) dbgs ( ) << * RegionEnd ; else dbgs ( ) << <STR_LIT> ; dbgs ( ) << <STR_LIT> << NumRegionInstrs << '\n' ) ; schedule ( ) ; exitRegion ( ) ; ++


<s> Triple triple ( TT ) ; bool isThumb = triple . getArch ( ) == Triple :: thumb || triple . getArch ( ) == Triple :: thumbeb ; bool NoCPU = CPU == <STR_LIT> || CPU . empty ( ) ; std :: string <ISA_LIT>ArchFeature ; switch ( triple . getSubArch ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case Triple :: <ISA_LIT>SubArch_v8 : if ( NoCPU ) <ISA_LIT>ArchFeature = <STR_LIT> <STR_LIT> ; else <ISA_LIT>ArchFeature = <STR_LIT> ; break ; case Triple :: <ISA_LIT>SubArch_v8_1a : if ( NoCPU ) <ISA_LIT>ArchFeature = <STR_LIT> <STR_LIT> ; else <ISA_LIT>ArchFeature = <STR_LIT> ; break ; case Triple :: <ISA_LIT>SubArch_v7m : isThumb = true ; if ( NoCPU ) <ISA_LIT>ArchFeature = <STR_LIT> ; else <ISA_LIT>ArchFeature = <STR_LIT> ; break ; case Triple :: <ISA_LIT>SubArch_v7em : if ( NoCPU ) <ISA_LIT>ArchFeature =


<s> array_pod_sort ( Regs . begin ( ) , Regs . end ( ) ) ; if ( Kind == k_RegisterList && Regs . back ( ) . second == <STR_LIT> ) Kind = k_RegisterListWithAPSR ; auto Op = make_unique < <ISA_LIT>Operand > ( Kind ) ; for ( SmallVectorImpl < std :: pair < unsigned , unsigned >> :: const_iterator I = Regs . begin ( ) , E = Regs . end ( ) ; I != E ; ++

I ) Op -> Registers . push_back ( I -> second ) ;


<s> if ( MRI . getRegClass ( CondReg ) == & <STR_LIT> ) { unsigned KCondReg = CondReg ; CondReg = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: COPY ) , CondReg ) . addReg ( KCondReg ) ; CondReg = fastEmitInst_extractsubreg ( <STR_LIT> , CondReg , <STR_LIT> ) ; } BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) ) . addReg ( CondReg ) . addImm ( <NUM_LIT> ) ; } const Value * LHS = I -> getOperand ( <NUM_LIT> ) ; const Value * RHS = I -> getOperand ( <NUM_LIT> ) ; Register LHSReg = getRegForValue ( LHS ) ; Register RHSReg = getRegForValue ( RHS ) ; if ( ! LHSReg || ! RHSReg ) return false ; const TargetRegisterClass * RC = TLI . getRegClassFor ( RetVT ) ; Register ResultReg = fastEmitInst_rri ( Opc , RC , RHSReg ,


<s> static rtx aarch64_struct_value_rtx ( tree fndecl ATTRIBUTE_UNUSED ,


<s> const <ISA_LIT>MachineFunctionInfo * <ISA_LIT>FI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; const auto & WinEHXMMSlotInfo = <ISA_LIT>FI -> getWinEHXMMSlotInfo ( ) ; const auto it = WinEHXMMSlotInfo . find ( FI ) ; if ( it == WinEHXMMSlotInfo . end ( ) ) return getFrameIndexReference ( MF , FI , FrameReg ) ; FrameReg = TRI -> getStackRegister (


<s> ar = shift_alg_si [ cpu ] [ SHIFT_ASHIFTRT ] [ count ] ; break ; default : gcc_unreachable ( ) ; } if ( type == CLOBBER ) return ( a == SHIFT_LOOP || lr == SHIFT_LOOP || ar == SHIFT_LOOP || ( TARGET_H8300H && mode == SImode && count == <NUM_LIT> ) ) ; else if ( type == ASHIFT ) return ( a == SHIFT_LOOP || ( TARGET_H8300H && mode == SImode && count == <NUM_LIT> ) ) ; else if ( type == LSHIFTRT ) return ( lr == SHIFT_LOOP || ( TARGET_H8300H && mode == SImode && count == <NUM_LIT> ) ) ; else if ( type == ASHIFTRT ) return ( ar == SHIFT_LOOP || ( TARGET_H8300H && mode ==


<s> unsigned Reg ; if ( ( Reg = isLoadFromStackSlot ( MI , FrameIndex ) ) ) return Reg ; const MachineMemOperand * Dummy ; return hasLoadFromStackSlot ( MI , Dummy


<s> const auto * MFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; return new yaml :: <ISA_LIT>MachineFunctionInfo ( * MFI


<s> if ( ! isShifter ( ) ) return false ; <STR_LIT> ST = getShiftExtendType ( ) ; return ( ST == <STR_LIT> || ST == <STR_LIT> || ST == <STR_LIT>

|| ST == <STR_LIT> ) && getShiftExtendAmount ( ) < width ;


<s> } else { beyond = next_active_insn ( XEXP ( XEXP ( SET_SRC ( PATTERN ( insn ) ) , <NUM_LIT> ) , <NUM_LIT> ) ) ; if ( beyond && ( GET_CODE ( beyond ) == JUMP_INSN || ( ( beyond = next_active_insn ( beyond ) ) && GET_CODE ( beyond ) == JUMP_INSN ) ) && GET_CODE ( PATTERN ( beyond ) ) == SET && recog_memoized ( beyond ) == CODE_FOR_jump_compact && ( ( INSN_ADDRESSES ( INSN_UID ( XEXP ( SET_SRC ( PATTERN ( beyond ) ) , <NUM_LIT> ) ) ) - INSN_ADDRESSES ( INSN_UID ( insn ) ) + ( unsigned ) <NUM_LIT> ) > <NUM_LIT> + <NUM_LIT> + <NUM_LIT> ) ) gen_block_redirect ( beyond , INSN_ADDRESSES ( INSN_UID ( beyond ) ) , <NUM_LIT> ) ; } next = next_active_insn ( insn ) ; if ( ( GET_CODE ( next ) == JUMP_INSN || ( ( next = next_active_insn ( next ) ) && GET_CODE ( next ) == JUMP_INSN ) ) && GET_CODE ( PATTERN ( next ) ) == SET && recog_memoized ( next ) == CODE_FOR_jump_compact && ( ( INSN_ADDRESSES ( INSN_UID ( XEXP ( SET_SRC ( PATTERN ( next ) ) , <NUM_LIT> ) ) ) - INSN_ADDRESSES ( INSN_UID ( insn ) ) + ( unsigned ) <NUM_LIT> ) > <NUM_LIT> + <NUM_LIT> + <NUM_LIT> ) ) gen_block_redirect ( next , INSN_ADDRESSES ( INSN_UID ( next ) ) , <NUM_LIT> ) ; } else if ( type == TYPE_JUMP || type == TYPE_RETURN ) { int addr = INSN_ADDRESSES ( INSN_UID ( insn ) ) ; rtx far_label = <NUM_LIT> ; int dest_uid = <NUM_LIT> ; struct far_branch * bp ; if ( type == TYPE_JUMP ) { far_label = XEXP ( SET_SRC ( PATTERN ( insn ) ) , <NUM_LIT> ) ; dest_uid = get_dest_uid ( far_label , max_uid ) ; if ( ! dest_uid ) { if ( ! NEXT_INSN ( far_label ) ) continue ; if ( ! optimize ) { JUMP_LABEL ( insn ) =


<s> return DAG . getNode ( <STR_LIT> , SDLoc ( Op ) , Op . getValueType ( ) , Op . getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return DAG . getNode ( <STR_LIT> , SDLoc ( Op ) , Op . getValueType ( ) , Op . getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return DAG . getNode ( <STR_LIT> , SDLoc ( Op ) , Op . getValueType ( ) , Op . getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return DAG . getNode ( <STR_LIT> , SDLoc ( Op ) , Op . getValueType ( ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; } return SDValue


<s> void printASROperand ( const MCInst * MI , unsigned OpNum , raw_ostream & O ) { printShiftOperand ( <STR_LIT> , MI , OpNum , O


<s> case ADJUST_LEN_UFRACT : avr_out_fract ( insn , op , false , & len ) ; break ; case ADJUST_LEN_ROUND : avr_out_round ( insn , op , & len ) ; break ; case ADJUST_LEN_TSTHI : avr_out_tsthi ( insn , op , & len ) ; break ; case ADJUST_LEN_TSTPSI : avr_out_tstpsi ( insn , op , & len ) ; break ; case ADJUST_LEN_TSTSI : avr_out_tstsi ( insn , op , & len ) ; break ; case ADJUST_LEN_COMPARE : avr_out_compare ( insn , op , & len ) ; break ; case ADJUST_LEN_COMPARE64 : avr_out_compare64 ( insn , op , & len ) ; break ; case ADJUST_LEN_LSHRQI : lshrqi3_out ( insn , op , & len ) ; break ; case ADJUST_LEN_LSHRHI : lshrhi3_out ( insn , op , & len ) ; break ; case ADJUST_LEN_LSHRSI : lshrsi3_out ( insn , op , & len ) ; break ; case ADJUST_LEN_ASHRQI : ashrqi3_out ( insn , op , & len ) ; break ; case ADJUST_LEN_ASHRHI : ashrhi3_out ( insn , op , & len ) ; break ; case ADJUST_LEN_ASHRSI : ashrsi3_out ( insn , op , & len ) ; break ; case ADJUST_LEN_ASHLQI : ashlqi3_out ( insn , op , & len ) ; break ; case ADJUST_LEN_ASHLHI : ashlhi3_out ( insn , op , & len ) ; break ; case ADJUST_LEN_ASHLSI : ashlsi3_out ( insn , op , & len ) ; break ; case ADJUST_LEN_ASHLPSI : avr_out_ashlpsi3 ( insn , op , & len ) ; break ; case ADJUST_LEN_ASHRPSI : avr_out_ashrpsi3 ( insn , op , & len ) ; break ; case ADJUST_LEN_LSHRPSI : avr_out_lshrpsi3 ( insn , op , & len ) ; break ; case ADJUST_LEN_CALL : len = AVR_HAVE_JMP_CALL ? <NUM_LIT> : <NUM_LIT> ; break ; case ADJUST_LEN_INSERT_BITS : avr_out_insert_bits ( op , & len ) ; break ; case ADJUST_LEN_INSV_NOTBIT : avr_out_insert_notbit ( insn , op , NULL_RTX , & len ) ; break ; case ADJUST_LEN_INSV_NOTBIT_0 : avr_out_insert_notbit ( insn , op , const0_rtx , & len ) ; break ; case ADJUST_LEN_INSV_NOTBIT_7 : avr_out_insert_notbit ( insn , op , GEN_INT ( <NUM_LIT> ) , & len ) ; break ; default : gcc_unreachable ( ) ; } return


<s> void <ISA_LIT>AsmPrinter :: printAddrMode2OffsetOperand ( const MachineInstr * MI , int Op , raw_ostream & O ) { const MachineOperand & MO1 = MI -> getOperand ( Op ) ; const MachineOperand & MO2 = MI -> getOperand ( Op + <NUM_LIT> ) ; if ( ! MO1 . getReg


<s> bool <ISA_LIT>DAGToDAGISel :: SelectMUBUF ( SDValue Addr , SDValue & Ptr , SDValue & VAddr , SDValue & SOffset , SDValue & Offset , SDValue & Offen , SDValue & Idxen , SDValue & Addr64 , SDValue & GLC , SDValue & SLC , SDValue & TFE ) const { if ( Subtarget -> useFlatForGlobal ( ) ) return false ; SDLoc DL ( Addr ) ; if ( ! GLC . getNode ( ) ) GLC = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; if ( ! SLC . getNode ( ) ) SLC = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; TFE = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; Idxen = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; Offen = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; Addr64 = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; SOffset = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; if ( CurDAG -> isBaseWithConstantOffset ( Addr ) ) { SDValue N0 = Addr . getOperand ( <NUM_LIT> ) ; SDValue N1 = Addr . getOperand ( <NUM_LIT> ) ; ConstantSDNode * C1 = cast < ConstantSDNode > ( N1 ) ; if ( N0 . getOpcode ( ) == <STR_LIT> ) { SDValue N2 = N0 . getOperand ( <NUM_LIT>


<s> static unsigned findScratchRegister ( RegScavenger * RS , const TargetRegisterClass * RC , <ISA_LIT>FunctionInfo * AFI ) { unsigned Reg = RS ? RS -> FindUnusedReg ( RC ) : ( unsigned ) <STR_LIT> ; assert ( ! AFI -> isThumb1OnlyFunction ( ) ) ; return


<s> AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , DestReg ) . addGlobalAddress ( GV , <NUM_LIT> , TF ) ) ; } else { Align Alignment = DL . getPrefTypeAlign ( GV -> getType ( ) ) ; if ( Subtarget -> isTargetELF ( ) && IsPositionIndependent ) return <ISA_LIT>LowerPICELF ( GV , VT ) ; unsigned PCAdj = IsPositionIndependent ? ( Subtarget -> isThumb ( ) ? <NUM_LIT> : <NUM_LIT> ) : <NUM_LIT> ; unsigned Id = AFI -> createPICLabelUId ( ) ; <ISA_LIT>ConstantPoolValue * CPV = <ISA_LIT>ConstantPoolConstant :: Create ( GV , Id , <STR_LIT> , PCAdj ) ; unsigned Idx = MCP . getConstantPoolIndex ( CPV , Alignment ) ; MachineInstrBuilder MIB ; if ( isThumb2 ) { unsigned Opc = IsPositionIndependent ? <STR_LIT> : <STR_LIT> ; MIB = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , DestReg ) . addConstantPoolIndex ( Idx ) ; if ( IsPositionIndependent ) MIB . addImm ( Id ) ; AddOptionalDefs ( MIB ) ; } else { DestReg = constrainOperandRegClass ( TII . get ( <STR_LIT> ) , DestReg , <NUM_LIT> ) ; MIB = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , DestReg ) . addConstantPoolIndex ( Idx ) . addImm ( <NUM_LIT> ) ; AddOptionalDefs ( MIB ) ; if ( IsPositionIndependent )


<s> MCInstrInfo * X = new MCInstrInfo ( ) ; Init<ISA_LIT>MCInstrInfo (


<s> if ( ! TLI . isTypeLegal ( SrcVT ) ) return false ; unsigned InputReg = getRegForValue ( I -> getOperand ( <NUM_LIT> ) ) ; if ( ! InputReg ) return false ; if ( SrcVT == <STR_LIT> ) { updateValueMap ( I , InputReg ) ; return true ; } if ( ! Subtarget -> is64Bit ( ) ) { const TargetRegisterClass * CopyRC = ( SrcVT == <STR_LIT> ) ? ( const TargetRegisterClass * ) & <STR_LIT> : ( const TargetRegisterClass * ) & <STR_LIT> ; unsigned CopyReg = createResultReg (


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const { AU . addRequired < DataLayoutPass > ( ) ; AU . addPreserved


<s> SDLoc DL ( Op ) ; assert ( V1 . getSimpleValueType ( ) == <STR_LIT> && <STR_LIT> ) ; assert ( V2 . getSimpleValueType ( ) == <STR_LIT> && <STR_LIT> ) ; ShuffleVectorSDNode * SVOp = cast < ShuffleVectorSDNode > ( Op ) ; ArrayRef < int > Mask = SVOp -> getMask ( ) ; assert ( Mask . size ( ) == <NUM_LIT> && <STR_LIT> ) ; if ( SDValue Blend = lowerVectorShuffleAsBlend ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return Blend ; if ( SDValue Broadcast = lowerVectorShuffleAsBroadcast ( <STR_LIT> , DL , V1 , Mask , Subtarget , DAG ) ) return Broadcast ; SmallVector < int , <NUM_LIT> > RepeatedMask ; if ( is128BitLaneRepeatedShuffleMask ( <STR_LIT> , Mask , RepeatedMask ) ) { assert ( RepeatedMask . size ( ) == <NUM_LIT> && <STR_LIT> ) ; if ( isSingleInputShuffleMask ( Mask ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , getV4<ISA_LIT>ShuffleImm8ForMask ( RepeatedMask , DAG ) ) ; if ( isShuffleEquivalent ( Mask , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , V2 ) ; if ( isShuffleEquivalent ( Mask , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , V2 ) ; for ( int i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) if ( RepeatedMask [ i ] >= <NUM_LIT> ) RepeatedMask [ i ] -= <NUM_LIT> ; return lowerVectorShuffleWithSHUFPS ( DL , <STR_LIT> , RepeatedMask ,


<s> tree minus_one_vec = build_minus_one_cst ( type ) ; tree temp = create_tmp_reg_or_ssa_name ( cmp_type ) ; gimple * g = gimple_build_assign ( temp , code , arg0 , arg1 ) ; gsi_insert_before ( gsi , g , GSI_SAME_STMT


<s> MachineFunctionProperties getRequiredProperties ( ) const override { return MachineFunctionProperties ( ) . set ( MachineFunctionProperties :: Property :: NoVRegs


<s> int regno ; unsigned int func_type ; unsigned long saved_int_regs ; unsigned HOST_WIDE_INT stack_adjust ; arm_stack_offsets * offsets ; if ( ! reload_completed ) return <NUM_LIT> ; func_type = arm_current_func_type ( ) ; if ( func_type & ( ARM_FT_VOLATILE | ARM_FT_NAKED | ARM_FT_STACKALIGN ) ) return <NUM_LIT> ; if ( IS_INTERRUPT ( func_type ) && ( frame_pointer_needed || TARGET_THUMB ) ) return <NUM_LIT> ; if ( TARGET_LDRD && current_tune -> prefer_ldrd_strd && ! optimize_function_for_size_p ( cfun ) ) return <NUM_LIT> ; offsets = arm_get_frame_offsets ( ) ; stack_adjust = offsets -> outgoing_args - offsets -> saved_regs ; if ( crtl -> args . pretend_args_size || cfun -> machine -> uses_anonymous_args || crtl -> calls_eh_return || cfun -> calls_alloca || ! ( stack_adjust == <NUM_LIT> || ( TARGET_APCS_FRAME && frame_pointer_needed && stack_adjust == <NUM_LIT> ) ) || ( ! ( TARGET_APCS_FRAME && frame_pointer_needed ) && arm_compute_static_chain_stack_bytes ( ) != <NUM_LIT> ) ) return <NUM_LIT> ; saved_int_regs = offsets -> saved_regs_mask ; if ( stack_adjust == <NUM_LIT> && ! arm_arch5t && TARGET_ARM ) { if ( ! call_used_or_fixed_reg_p ( <NUM_LIT> ) ) return <NUM_LIT> ; if ( arm_size_return_regs ( ) >= ( <NUM_LIT> * UNITS_PER_WORD ) ) return <NUM_LIT> ; if ( sibling


<s> PredMBB -> addSuccessor ( CloneMBB ) ; cloneSuccessorList ( CloneMBB , MBB ) ; numClonedInstr += MBB -> size ( ) ; DEBUG ( dbgs ( ) << <STR_LIT> << <STR_LIT> << MBB -> getNumber ( ) << <STR_LIT> << MBB -> size ( ) << <STR_LIT> ; ) ; SHOWNEWBLK ( CloneMBB , <STR_LIT> ) ; return CloneMBB


<s> break ; case <STR_LIT> : Opc = <STR_LIT> ; RC = <STR_LIT> ; break ; case <STR_LIT> : if ( Subtarget -> hasSSE1 ( ) ) { Opc = <STR_LIT> ; RC = <STR_LIT> ; } else { Opc = <STR_LIT> ; RC = <STR_LIT> ; } break ; case <STR_LIT> : if ( Subtarget -> hasSSE2 ( ) ) { Opc = <STR_LIT> ; RC = <STR_LIT> ; } else { Opc = <STR_LIT> ; RC =


<s> assert ( MBBI -> getOpcode ( ) == <STR_LIT> && <STR_LIT> ) ; if ( ! FuncInfo -> isLeafProc ( ) ) { BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) ; return ; } MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; int NumBytes = ( int ) MFI -> getStackSize


<s> <STR_LIT> CC = ( <STR_LIT> ) MI -> getOperand ( OpNum ) . getImm ( ) ; if ( CC != <STR_LIT> ) O << <ISA_LIT>CondCodeToString


<s> } else if ( i == <NUM_LIT> ) { if ( ( firstMVT == <STR_LIT> ) || ( firstMVT == <STR_LIT> ) ) { if ( ArgVT == <STR_LIT> ) { VA . convertToReg ( <STR_LIT> ) ; } else if ( ArgVT == <STR_LIT> ) { VA . convertToReg ( <STR_LIT> ) ; } } } if ( ( ( ArgVT == <STR_LIT> ) || ( ArgVT == <STR_LIT> ) || ( ArgVT == <STR_LIT> ) || ( ArgVT == <STR_LIT> ) ) && VA . isMemLoc ( ) ) { switch ( VA . getLocMemOffset ( ) ) { case <NUM_LIT> : VA . convertToReg ( <STR_LIT> ) ; break ; case <NUM_LIT> : VA . convertToReg ( <STR_LIT> ) ; break ; case <NUM_LIT> : VA . convertToReg ( <STR_LIT> ) ; break ; case <NUM_LIT> : VA . convertToReg ( <STR_LIT> ) ; break ; default : break ; } } unsigned ArgReg = getRegForValue ( ArgVal ) ; if ( ! ArgReg ) return false ; switch ( VA . getLocInfo ( ) ) { case CCValAssign :: Full : break ; case CCValAssign :: AExt : case CCValAssign :: SExt : { MVT DestVT = VA . getLocVT ( ) ; MVT SrcVT = ArgVT ; ArgReg = emitIntExt ( SrcVT , ArgReg , DestVT , false ) ; if ( ! ArgReg ) return false ; break ; } case CCValAssign :: ZExt : { MVT DestVT = VA . getLocVT ( ) ; MVT SrcVT = ArgVT ; ArgReg = emitIntExt ( SrcVT , ArgReg , DestVT , true ) ; if ( ! ArgReg ) return false ; break ; } default : llvm_unreachable ( <STR_LIT> ) ; } if ( VA . isRegLoc ( ) && ! VA . needsCustom ( ) ) { BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: COPY ) , VA . getLocReg ( ) ) . addReg ( ArgReg ) ; CLI . OutRegs . push_back ( VA . getLocReg ( ) ) ; } else if ( VA . needsCustom ( ) ) { llvm_unreachable ( <STR_LIT> ) ; return false ; } else { assert ( VA . isMemLoc ( ) && <STR_LIT> ) ; if ( isa < UndefValue > ( ArgVal ) ) continue ; unsigned ArgSize = RoundUpToAlignment ( ArgVT . getSizeInBits ( ) , <NUM_LIT> ) ; unsigned BEAlign = <NUM_LIT> ; if ( ArgSize < <NUM_LIT> && ! Subtarget -> isLittle ( ) ) BEAlign = <NUM_LIT> - ArgSize ; Address Addr ; Addr . setKind ( Address :: RegBase ) ; Addr . setReg ( <STR_LIT> ) ; Addr . setOffset ( VA . getLocMemOffset ( ) + BEAlign ) ; unsigned Alignment = DL . getABITypeAlignment ( ArgVal


<s> uint8_t bytes [ <NUM_LIT> ] ; int ret = region . readBytes ( address , <NUM_LIT> , (