<s> unsigned <ISA_LIT>RegisterBankInfo :: getBreakDownCost ( const ValueMapping & ValMapping , const RegisterBank * CurBank ) const { assert ( ValMapping . NumBreakDowns == <NUM_LIT> && ValMapping . BreakDown [ <NUM_LIT> ] . Length == <NUM_LIT> && ValMapping . BreakDown [ <NUM_LIT> ] . StartIdx == <NUM_LIT> && ValMapping . BreakDown [ <NUM_LIT> ] . Length == <NUM_LIT> && ValMapping . BreakDown [ <NUM_LIT> ] . StartIdx == <NUM_LIT> && ValMapping . BreakDown [ <NUM_LIT> ] . RegBank == ValMapping . BreakDown [ <NUM_LIT> ] . RegBank ) ; return


<s> if ( isPassEnabled ( EnableSDWAPeephole ) ) { addPass ( & <ISA_LIT>PeepholeSDWAID ) ; addPass ( & EarlyMachineLICMID ) ; addPass ( & MachineCSEID ) ; addPass ( & <ISA_LIT>FoldOperandsID )


<s> if ( BaseType != RegBase ) return false ; if ( RegisterSDNode * RegNode = dyn_cast_or_null < RegisterSDNode > ( Base_Reg . getNode (

) ) ) return RegNode -> getReg ( ) == <STR_LIT> ;


<s> extern __inline void __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) __TM_suspend ( void ) { __builtin_tsuspend ( )


<s> bool <ISA_LIT>AsmParser :: parseDirectiveUnreq ( SMLoc L ) { MCAsmParser & Parser = getParser ( ) ; if ( Parser . getTok ( ) . isNot ( AsmToken :: Identifier ) ) return Error ( L , <STR_LIT> ) ; RegisterReqs . erase ( Parser . getTok ( ) . getIdentifier ( ) . lower ( ) ) ; Parser . Lex ( )


<s> } EVT VT = Op . getValueType ( ) ; SDValue One = DAG . getConstant ( <NUM_LIT> , dl , VT ) ; if ( Convert ) { SDValue SR = DAG . getCopyFromReg ( DAG . getEntryNode ( ) , dl , <STR_LIT> , <STR_LIT> , Flag ) ; if ( Shift ) SR = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , SR , One ) ; SR = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , SR , One ) ; if ( Invert ) SR = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , SR , One ) ; return SR ; } else { SDValue Zero = DAG . getConstant ( <NUM_LIT> , dl , VT ) ; SDValue Ops [ ] = { One , Zero , TargetCC


<s> bool useSoftFloat ( ) const { return


<s> MachineInstr * InsertPt = Start ; for ( auto & I : MRI -> def_instructions ( <STR_LIT> ) ) { if ( I . getParent ( ) != MBB ) continue ; if ( ! I . getOperand ( <NUM_LIT> ) . isImm ( ) || I . getOperand ( <NUM_LIT> ) . getImm ( ) != <STR_LIT> ) continue ; if ( ! I . getDesc ( ) . isMoveReg ( ) || ! I . getOperand ( <NUM_LIT> ) . isIdenticalTo ( Start -> getOperand ( <NUM_LIT> ) ) ) continue ; InsertPt = & I ; break ; } unsigned Opc = Start -> getOpcode ( ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; MachineInstrBuilder MIB = BuildMI ( * MBB , InsertPt , InsertPt -> getDebugLoc ( ) , TII -> get ( Opc ) ) ; MIB . addDef ( <STR_LIT> ) ; MIB . add ( Start -> getOperand ( <NUM_LIT> ) ) ; if ( Opc == <STR_LIT> ) MIB . add ( Start -> getOperand ( <NUM_LIT> ) ) ; if ( InsertPt != Start ) InsertPt -> eraseFromParent ( ) ; Start -> eraseFromParent ( ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * MIB ) ; return & * MIB ; } ; auto ExpandLoopEnd = [ this ] ( MachineLoop * ML , MachineInstr * Dec , MachineInstr * End ) { MachineBasicBlock * MBB = End -> getParent ( ) ; MachineInstrBuilder MIB = BuildMI ( * MBB , End , End -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) ; MIB . addDef ( <STR_LIT> ) ; MIB . add ( End -> getOperand ( <NUM_LIT> ) ) ; MIB . add ( End -> getOperand ( <NUM_LIT> ) ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * MIB ) ; End -> eraseFromParent ( ) ; Dec -> eraseFromParent ( ) ; return & * MIB ; } ; auto RemoveDeadBranch = [ ] ( MachineInstr * I ) { MachineBasicBlock * BB = I -> getParent ( ) ; MachineInstr * Terminator = & BB -> instr_back ( ) ; if ( Terminator -> isUnconditionalBranch ( ) && I != Terminator ) { MachineBasicBlock * Succ = Terminator -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; if ( BB -> isLayoutSuccessor ( Succ ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * Terminator ) ; Terminator -> eraseFromParent


<s> unsigned AluCode = MI -> getOperand ( <NUM_LIT> )


<s> bool <ISA_LIT>TargetLowering :: isFMAFasterThanFMulAndFAdd ( const Function & F , Type * Ty ) const { switch ( Ty -> getScalarType ( ) -> getTypeID ( ) ) { case Type :: FloatTyID : case Type


<s> addPass ( & FinalizeISelID ) ; addPass ( create<ISA_LIT>FixupVectorISelPass ( ) ) ; addPass ( create<ISA_LIT>AddIMGInitPass ( ) ) ; return false


<s> if ( IsBlendSupported ) if ( SDValue Blend = lowerShuffleAsBlend ( DL , <STR_LIT> , V1 , V2 , Mask , Zeroable , Subtarget , DAG ) ) return Blend ; if ( SDValue Masked = lowerShuffleAsBitMask ( DL , <STR_LIT> , V1 , V2 , Mask , Zeroable , Subtarget , DAG ) ) return Masked ; if ( SDValue V = lowerShuffleWithUNPCK ( DL , <STR_LIT> , Mask , V1 , V2 , DAG ) ) return V ; if ( SDValue V = lowerShuffleWithPACK ( DL , <STR_LIT> , Mask , V1 , V2 , DAG , Subtarget ) ) return V ; if ( SDValue V = lowerShuffleAsVTRUNC ( DL , <STR_LIT> , V1 , V2 , Mask , Zeroable , Subtarget , DAG ) ) return V ; if ( SDValue Rotate = lowerShuffleAsByteRotate ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return Rotate ; if ( SDValue BitBlend = lowerShuffleAsBitBlend ( DL , <STR_LIT> , V1 , V2 , Mask , DAG ) ) return BitBlend ; if ( SDValue V = lowerShuffleAsByteShiftMask ( DL , <STR_LIT> , V1 , V2 , Mask , Zeroable , Subtarget , DAG ) ) return V ; int NumEvenDrops = canLowerByDroppingEvenElements ( Mask , false ) ; if ( ( NumEvenDrops == <NUM_LIT> || NumEvenDrops == <NUM_LIT> ) && Subtarget . hasSSE41 ( ) && ! Subtarget . hasVLX ( ) ) { SmallVector < SDValue , <NUM_LIT> > DWordClearOps ( <NUM_LIT> , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; for ( unsigned i = <NUM_LIT> ; i != <NUM_LIT> ; i += <NUM_LIT> << ( NumEvenDrops - <NUM_LIT> ) ) DWordClearOps [ i ] = DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; SDValue DWordClearMask = DAG . getBuildVector ( <STR_LIT> , DL , DWordClearOps ) ; V1 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getBitcast ( <STR_LIT> , V1 ) , DWordClearMask ) ; V2 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getBitcast ( <STR_LIT> , V2 ) , DWordClearMask ) ; SDValue Result = DAG . getNode ( <STR_LIT> , DL , <STR_LIT>


<s> assert ( <ISA_LIT>MCInstrInfo :: isBundle ( HMB ) ) ; DEBUG ( dbgs ( ) << <STR_LIT> ; ) ; * Addend = <NUM_LIT> ; * Extended = false ; * CurrentBundle = & MI ; * CurrentIndex = <NUM_LIT> ; size_t Last = <ISA_LIT>MCInstrInfo :: bundleSize ( HMB ) - <NUM_LIT> ; for ( auto & I : <ISA_LIT>MCInstrInfo :: bundleInstructions ( HMB ) ) { MCInst & HMI = const_cast < MCInst & > ( * I . getInst ( ) ) ; verifyInstructionPredicates ( HMI , computeAvailableFeatures ( STI . getFeatureBits ( ) ) ) ; EncodeSingleInstruction ( HMI , OS , Fixups , STI , parseBits (


<s> void <ISA_LIT>MCCodeEmitter :: emitRegModRMByte ( const MCOperand & ModRMReg , unsigned RegOpcodeFld , raw_ostream & OS


<s> else rshift = vec_splats ( ( unsigned short ) __B ) ; } result = vec_vsrah ( ( __v8hi ) __A , rshift ) ; return ( __m128i ) result


<s> CacheLineSize = <NUM_LIT> ; PrefetchDistance = <NUM_LIT> ; MinPrefetchStride = <NUM_LIT> ; MaxPrefetchIterationsAhead = <NUM_LIT> ; break ; case ExynosM3 : MaxInterleaveFactor = <NUM_LIT> ; MaxJumpTableSize = <NUM_LIT> ; PrefFunctionLogAlignment = <NUM_LIT> ; PrefLoopLogAlignment = <NUM_LIT> ; break ; case Falkor : MaxInterleaveFactor = <NUM_LIT> ; MinVectorRegisterBitWidth = <NUM_LIT> ; CacheLineSize = <NUM_LIT> ; PrefetchDistance = <NUM_LIT> ; MinPrefetchStride = <NUM_LIT> ; MaxPrefetchIterationsAhead = <NUM_LIT> ; break ; case Kryo : MaxInterleaveFactor = <NUM_LIT> ; VectorInsertExtractBaseCost = <NUM_LIT> ; CacheLineSize = <NUM_LIT> ; PrefetchDistance = <NUM_LIT> ; MinPrefetchStride = <NUM_LIT> ; MaxPrefetchIterationsAhead = <NUM_LIT> ; MinVectorRegisterBitWidth = <NUM_LIT> ; break ; case NeoverseE1 : PrefFunctionLogAlignment = <NUM_LIT> ; break ; case NeoverseN1 : PrefFunctionLogAlignment = <NUM_LIT> ; break ; case Saphira : MaxInterleaveFactor = <NUM_LIT> ; MinVectorRegisterBitWidth = <NUM_LIT> ; break ; case ThunderX2T99 : CacheLineSize = <NUM_LIT> ; PrefFunctionLogAlignment = <NUM_LIT> ; PrefLoopLogAlignment = <NUM_LIT> ; MaxInterleaveFactor = <NUM_LIT> ; PrefetchDistance = <NUM_LIT> ; MinPrefetchStride = <NUM_LIT> ; MaxPrefetchIterationsAhead = <NUM_LIT> ; MinVectorRegisterBitWidth = <NUM_LIT> ; break ; case ThunderX : case ThunderXT88 : case ThunderXT81 : case ThunderXT83 : CacheLineSize = <NUM_LIT> ; PrefFunctionLogAlignment = <NUM_LIT> ; PrefLoopLogAlignment = <NUM_LIT> ; MinVectorRegisterBitWidth = <NUM_LIT> ; break ; case TSV110 : CacheLineSize = <NUM_LIT> ; PrefFunctionLogAlignment = <NUM_LIT> ; PrefLoopLogAlignment =


<s> LoadSDNode * Ld = cast < LoadSDNode > ( N ) ; EVT RegVT = Ld -> getValueType ( <NUM_LIT> ) ; EVT MemVT = Ld -> getMemoryVT ( ) ; SDLoc dl ( Ld ) ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; <STR_LIT> Ext = Ld -> getExtensionType ( ) ; bool Fast ; unsigned AddressSpace = Ld -> getAddressSpace ( ) ; unsigned Alignment = Ld -> getAlignment ( ) ; if ( RegVT . is256BitVector ( ) && ! DCI . isBeforeLegalizeOps ( ) && Ext == <STR_LIT> && ( ( Ld -> isNonTemporal ( ) && ! Subtarget . hasInt256 ( ) && Alignment >= <NUM_LIT> ) || ( TLI . allowsMemoryAccess ( * DAG . getContext ( ) ,

DAG . getDataLayout ( ) , RegVT , AddressSpace , Alignment , & Fast ) && ! Fast ) ) ) {


<s> SDValue <ISA_LIT>TargetLowering :: LowerFRAMEADDR ( SDValue Op , SelectionDAG & DAG ) const { MachineFrameInfo * MFI = DAG . getMachineFunction ( ) . getFrameInfo ( ) ; MFI -> setFrameAddressIsTaken ( true ) ; EVT VT = Op . getValueType ( ) ; DebugLoc dl = Op . getDebugLoc ( ) ; unsigned Depth = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; SDValue FrameAddr = DAG . getCopyFromReg ( DAG . getEntryNode ( ) , dl , <STR_LIT> , VT ) ; while ( Depth -- ) FrameAddr = DAG . getLoad ( VT , dl , DAG . getEntryNode

( ) , FrameAddr , MachinePointerInfo ( ) , false , false , false , <NUM_LIT> ) ;


<s> assert ( MI . definesRegister ( DestReg ) && <STR_LIT> ) ; addFrameReference ( BuildMI ( MBB , II , dl , TII . get ( LP64 ? <STR_LIT> : <STR_LIT> ) , Reg ) , FrameIndex ) ; BuildMI ( MBB , II , dl , TII . get ( TargetOpcode :: IMPLICIT_DEF ) , DestReg ) ; Register RegO = MF . getRegInfo ( ) . createVirtualRegister ( LP64 ? G8RC : GPRC ) ; BuildMI ( MBB , II , dl , TII . get ( LP64 ? <STR_LIT> : <STR_LIT> ) , RegO ) . addReg ( getCRFromCRBit ( DestReg ) ) ; unsigned ShiftBits = getEncodingValue ( DestReg ) ; BuildMI ( MBB , II , dl , TII . get ( LP64 ? <STR_LIT> : <STR_LIT> ) , RegO ) . addReg ( RegO , RegState :: Kill ) . addReg ( Reg , RegState :: Kill ) . addImm ( ShiftBits ? <NUM_LIT> - ShiftBits : <NUM_LIT> ) . addImm ( ShiftBits ) . addImm ( ShiftBits ) ; BuildMI ( MBB , II , dl , TII . get ( LP64 ? <STR_LIT> : <STR_LIT> ) , getCRFromCRBit ( DestReg ) ) . addReg ( RegO , RegState :: Kill ) . addReg ( getCRFromCRBit ( DestReg ) , RegState :: Implicit ) ; MBB . erase (


<s> unsigned <ISA_LIT>WinCOFFObjectWriter :: getRelocType ( MCContext & Ctx , const MCValue & Target , const MCFixup & Fixup , bool IsCrossSection , const MCAsmBackend & MAB ) const { unsigned FixupKind = Fixup . getKind ( ) ; if ( IsCrossSection ) { if ( FixupKind != FK_Data_4 && FixupKind != llvm :: <STR_LIT> ) { Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; return COFF :: IMAGE_REL_AMD64_ADDR32 ; } FixupKind = FK_PCRel_4 ; } MCSymbolRefExpr :: VariantKind Modifier = Target . isAbsolute ( ) ? MCSymbolRefExpr :: VK_None : Target . getSymA ( ) -> getKind ( ) ; if ( getMachine ( ) == COFF :: IMAGE_FILE_MACHINE_AMD64 ) { switch ( FixupKind ) { case FK_PCRel_4 : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return COFF :: IMAGE_REL_AMD64_REL32 ; case FK_Data_4 : case <STR_LIT> : case <STR_LIT> : if ( Modifier == MCSymbolRefExpr :: VK_COFF_IMGREL32 ) return COFF :: IMAGE_REL_AMD64_ADDR32NB ; if ( Modifier == MCSymbolRefExpr :: VK_SECREL ) return COFF :: IMAGE_REL_AMD64_SECREL ; return COFF :: IMAGE_REL_AMD64_ADDR32 ; case FK_Data_8 : return COFF ::


<s> return __builtin_aarch64_reduc_smin_scal_v8qi (


<s> for ( i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) { int x = <NUM_LIT> << i ; bool ok ; real_from_integer ( & s , mode , x , SIGNED ) ; if ( real_equal ( r , & s ) ) return true ; ok = exact_real_inverse ( mode , & s


<s> printSysRegOperand ( <STR_LIT> ( ) ,


<s> return ( h8300_interrupt_function_p ( current_function_decl ) ||

h8300_monitor_function_p ( current_function_decl ) ) ;


<s> HasNopl = CPU != <STR_LIT> && CPU != <STR_LIT> && CPU != <STR_LIT> && CPU != <STR_LIT> && CPU != <STR_LIT> && CPU != <STR_LIT> && CPU != <STR_LIT> && CPU != <STR_LIT> && CPU != <STR_LIT> && CPU != <STR_LIT> && CPU != <STR_LIT> && CPU !=

<STR_LIT> && CPU != <STR_LIT> && CPU != <STR_LIT> && CPU != <STR_LIT> && CPU != <STR_LIT> ;


<s> if ( mcu -> name == NULL ) { error ( <STR_LIT> , avr_mmcu , <STR_LIT> ) ; avr_inform_core_architectures ( ) ; break ; } else if ( strcmp ( mcu -> name , avr_mmcu ) == <NUM_LIT> && mcu -> macro == NULL ) { avr_arch = & avr_arch_types [ mcu -> arch_id ] ; if ( avr_n_flash < <NUM_LIT> ) avr_n_flash = <NUM_LIT> + ( mcu


<s> SDValue Mask = DAG . getConstant ( MaskVal , dl , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , ResultVT , Result , Vec256 , Mask ) ; } const <ISA_LIT>Subtarget & Subtarget = static_cast < const <ISA_LIT>Subtarget & > ( DAG . getSubtarget ( ) ) ; MVT CastVT = Subtarget . hasAVX2 ( ) ? <STR_LIT> : <STR_LIT> ; SDValue Mask = DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ; Vec256 = DAG . getBitcast ( CastVT , Vec256 ) ; Vec256 = DAG . getNode ( <STR_LIT> , dl , CastVT , Result , Vec256 , Mask ) ; return DAG . getBitcast ( ResultVT ,


<s> static bool contains_core_p ( unsigned * arr , unsigned core ) { if ( arr [ <NUM_LIT>


<s> if ( ! printAliasInstr ( MI , O ) ) printInstruction ( MI , Address , O ) ; printAnnotation ( O ,


<s> bool arm_vector_mode_supported_p ( machine_mode mode ) { if ( TARGET_NEON && ( mode == V2SFmode || mode == V4SImode || mode == V8HImode || mode == V4HFmode || mode == V16QImode || mode == V4SFmode || mode == V2DImode || mode == V8HFmode || mode == V4BFmode || mode == V8BFmode ) ) return true ; if ( ( TARGET_NEON || TARGET_IWMMXT ) && ( ( mode == V2SImode ) || ( mode ==

V4HImode ) || ( mode == V8QImode ) ) ) return true ;


<s> unsigned int __i = ( unsigned short ) __w << <NUM_LIT> | ( unsigned short ) __w ; return _mm_set1_pi32 ( __i )


<s> EVT WidenedVT = VT . widenIntegerVectorElementType ( * DAG . getContext ( ) ) ; if ( DAG . getTargetLoweringInfo ( ) . isTypeLegal ( WidenedVT ) ) { unsigned ExtendOpcode = Signed ? <STR_LIT> : <STR_LIT> ; SDValue Op0 = DAG . getNode ( ExtendOpcode , dl , WidenedVT , Op . getOperand ( <NUM_LIT> ) ) ; SDValue Op1 = DAG . getNode ( ExtendOpcode , dl , WidenedVT , Op . getOperand ( <NUM_LIT> ) ) ; SDValue Div = DAG . getNode ( Op . getOpcode ( ) , dl , WidenedVT , Op0 , Op1 ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Div ) ; } SDValue Op0 = convertToScalableVector ( DAG , ContainerVT , Op . getOperand ( <NUM_LIT> ) ) ; SDValue Op1 = convertToScalableVector ( DAG , ContainerVT , Op . getOperand ( <NUM_LIT> ) ) ; unsigned UnpkLo = Signed ? <STR_LIT> : <STR_LIT> ; unsigned UnpkHi = Signed ? <STR_LIT> : <STR_LIT> ; SDValue Op0Lo = DAG . getNode ( UnpkLo , dl , ScalableWidenedVT , Op0 ) ; SDValue Op1Lo = DAG . getNode ( UnpkLo , dl , ScalableWidenedVT , Op1 ) ; SDValue Op0Hi = DAG . getNode ( UnpkHi , dl , ScalableWidenedVT , Op0 ) ; SDValue Op1Hi = DAG . getNode ( UnpkHi , dl , ScalableWidenedVT , Op1 ) ; Op0Lo = convertFromScalableVector ( DAG , FixedWidenedVT , Op0Lo ) ; Op1Lo = convertFromScalableVector ( DAG , FixedWidenedVT , Op1Lo ) ; Op0Hi = convertFromScalableVector ( DAG , FixedWidenedVT , Op0Hi ) ; Op1Hi = convertFromScalableVector ( DAG , FixedWidenedVT , Op1Hi ) ; SDValue ResultLo = DAG . getNode ( Op . getOpcode ( ) , dl , FixedWidenedVT , Op0Lo , Op1Lo ) ; SDValue ResultHi = DAG . getNode ( Op . getOpcode ( ) , dl , FixedWidenedVT , Op0Hi , Op1Hi ) ; ResultLo = convertToScalableVector ( DAG , ScalableWidenedVT


<s> static void report_missing_extension ( location_t location , tree fndecl , const char * extension ) { if ( reported_missing_extension_p ) return ; error_at ( location , <STR_LIT> , fndecl , extension ) ; inform ( location , <STR_LIT> <STR_LIT> <STR_LIT> , extension ) ; reported_missing_extension_p = true


<s> MachineOperand & Src0 = Inst . getOperand ( <NUM_LIT> ) ; MachineOperand & Src1 = Inst . getOperand ( <NUM_LIT> ) ; MachineOperand & Cond = Inst . getOperand ( <NUM_LIT> ) ; Register SCCSource = Cond . getReg ( ) ; bool IsSCC = ( SCCSource == <STR_LIT> ) ; if ( ! IsSCC && Src0 . isImm ( ) && ( Src0 . getImm ( ) == - <NUM_LIT> ) && Src1 . isImm ( ) && ( Src1 . getImm ( ) == <NUM_LIT> ) ) { MRI . replaceRegWith ( Dest . getReg ( ) , SCCSource ) ; return ; } const TargetRegisterClass * TC = RI . getRegClass ( <STR_LIT> ) ; Register CopySCC = MRI . createVirtualRegister ( TC ) ; if ( IsSCC ) { bool CopyFound = false ; for ( MachineInstr & CandI : make_range ( std :: next ( MachineBasicBlock :: reverse_iterator ( Inst ) ) , Inst . getParent ( ) -> rend ( ) ) ) { if ( CandI . findRegisterDefOperandIdx ( <STR_LIT> , false , false , & RI ) != - <NUM_LIT> ) { if ( CandI . isCopy ( ) && CandI . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) { BuildMI ( MBB , MII , DL , get ( <STR_LIT> ) , CopySCC ) . addReg ( CandI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; CopyFound = true ; } break ; } } if ( ! CopyFound ) { unsigned Opcode = ( ST . getWavefrontSize ( ) == <NUM_LIT> ) ? <STR_LIT> : <STR_LIT> ; auto NewSelect = BuildMI ( MBB , MII , DL , get ( Opcode ) , CopySCC ) . addImm ( - <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; NewSelect -> getOperand ( <NUM_LIT> ) . setIsUndef ( Cond . isUndef (


<s> if ( GET_CODE ( op0 ) == ASHIFT && GET_CODE ( op1 )


<s> case <STR_LIT> : if ( ! Subtarget . hasVLX ( ) && Super -> getSize ( ) == RC -> getSize ( ) ) return Super ; break ; case <STR_LIT> : case <STR_LIT> : if ( ! Subtarget . hasVLX ( ) ) break ; case <STR_LIT> : case <STR_LIT> : if ( ! Subtarget . hasAVX512 ( ) ) break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( Super -> getSize ( ) == RC -> getSize ( ) ) return Super ; } Super = * I ++ ; } while ( Super ) ; return


<s> Candidate . RPDelta = RPDelta ; Candidate . SCost = CurrentCost ; FoundCandidate = BestCost ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; continue ; } else if ( InstrLatency > CandLatency && ! TopUseShorterTie ) { Candidate . SU = * I ; Candidate . RPDelta = RPDelta ; Candidate . SCost = CurrentCost ; FoundCandidate = BestCost ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; continue ; } } else if ( Q . getID ( ) == BotQID && CurrentCost == Candidate . SCost ) { if ( InstrLatency < CandLatency && BotUseShorterTie ) { Candidate . SU = * I ; Candidate . RPDelta = RPDelta ; Candidate . SCost = CurrentCost ; FoundCandidate = BestCost ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; continue ; } else if ( InstrLatency > CandLatency && ! BotUseShorterTie ) { Candidate . SU = * I ; Candidate . RPDelta = RPDelta ; Candidate . SCost = CurrentCost ; FoundCandidate = BestCost ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; continue ; } } } if ( CurrentCost == Candidate . SCost ) { if ( ( Q . getID ( ) == TopQID && ( * I ) -> Succs . size ( ) > Candidate . SU -> Succs . size ( ) ) || ( Q . getID ( ) == BotQID && ( * I ) -> Preds . size ( ) < Candidate . SU -> Preds . size ( ) ) ) { DEBUG ( traceCandidate ( <STR_LIT> , Q , * I , CurrentCost ) ) ; Candidate . SU =


<s> MCOperand <ISA_LIT>Disassembler :: decodeOperand_VS_128 ( unsigned Val


<s> void addImm0_7Operands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT> ) ; const MCConstantExpr * MCE = cast < MCConstantExpr > (


<s> if ( Range -> second == <NUM_LIT> ) { NewN = EmitShift ( <STR_LIT> , X , <NUM_LIT> - Range -> first ) ; ReplaceNode ( And . getNode ( ) , NewN ) ; } else if ( Range -> first == <NUM_LIT> ) { NewN = EmitShift ( <STR_LIT> , X , Range -> second ) ; ReplaceNode ( And . getNode ( ) , NewN ) ; } else if ( Range -> first == Range -> second ) { NewN = EmitShift ( <STR_LIT> , X , <NUM_LIT> - Range -> first ) ; ReplaceNode ( And . getNode ( ) , NewN ) ; SwitchEQNEToPLMI = true ; } else if ( ! Subtarget -> hasV6T2Ops ( ) ) { NewN = EmitShift ( <STR_LIT> , X , <NUM_LIT> - Range -> first ) ; NewN = EmitShift ( <STR_LIT> , SDValue ( NewN , <NUM_LIT> ) , Range -> second + ( <NUM_LIT> - Range -> first ) ) ; ReplaceNode ( And . getNode (


<s> KnownZero = KnownOne = APInt ( KnownZero . getBitWidth ( ) , <NUM_LIT> ) ; switch ( Op . getOpcode ( ) ) { default : break ; case <STR_LIT> : { if ( cast < VTSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getVT ( ) == <STR_LIT> ) KnownZero = <NUM_LIT> ; break ; } case <STR_LIT> : { switch ( cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ) { default : break ; case <STR_LIT>


<s> default : return AMDGPUTargetLowering :: EmitInstrWithCustomInserter ( MI , BB ) ; case AMDGPU :: BRANCH : return BB ; case AMDGPU :: <ISA_LIT>_RegisterStorePseudo : { MachineRegisterInfo & MRI = BB -> getParent ( ) -> getRegInfo ( ) ; unsigned Reg = MRI . createVirtualRegister ( & AMDGPU :: SReg_64RegClass ) ; MachineInstrBuilder MIB = BuildMI ( * BB , I , MI -> getDebugLoc ( )

, TII -> get ( AMDGPU :: <ISA_LIT>_RegisterStore ) , Reg ) ;


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> :


<s> static MCDisassembler * create<ISA_LIT>Disassembler ( const Target & T , const MCSubtargetInfo


<s> SmallVector < SDValue , <NUM_LIT> > Args ; unsigned Start = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; EVT VT = Op . getValueType ( ) ; EVT SrcVT = Op . getOperand ( <NUM_LIT> ) . getValueType ( ) ; if ( ( ( SrcVT == <STR_LIT> && VT == <STR_LIT> ) || ( SrcVT == <STR_LIT> && VT == <STR_LIT> ) ) && Start != <NUM_LIT> ) return Op ; if ( ( ( SrcVT == <STR_LIT> && VT == <STR_LIT> ) || ( SrcVT == <STR_LIT> && VT == <STR_LIT> ) ) && ( Start == <NUM_LIT> || Start == <NUM_LIT> ) ) return Op ; DAG . ExtractVectorElements ( Op . getOperand ( <NUM_LIT> ) , Args , Start , VT . getVectorNumElements ( ) ) ; return DAG . getBuildVector ( Op . getValueType ( ) , SDLoc


<s> if ( TARGET_GENERAL_REGS_ONLY ) if ( FLOAT_MODE_P ( mode ) ) error ( <STR_LIT> , <STR_LIT> ) ; else error ( <STR_LIT> , <STR_LIT> ) ; else if ( FLOAT_MODE_P ( mode ) ) error ( <STR_LIT> <STR_LIT> , <STR_LIT> ) ; else error ( <STR_LIT> <STR_LIT> ,


<s> std :: string AccessKey ; MDNode * TypeMeta = nullptr ; Value * Base = computeBaseAndAccessKey ( Call , AccessKey , Kind , TypeMeta ) ; if ( ! Base ) return false ; BasicBlock * BB = Call -> getParent ( ) ; GlobalVariable * GV ; if ( GEPGlobals . find ( AccessKey ) == GEPGlobals . end ( ) ) { GV = new GlobalVariable ( M , Type :: getInt64Ty ( BB -> getContext ( ) ) , false , GlobalVariable :: ExternalLinkage , NULL , AccessKey ) ; GV -> addAttribute ( <STR_LIT> ) ; if ( TypeMeta ) GV -> setMetadata ( LLVMContext :: MD_preserve_access_index , TypeMeta ) ; GEPGlobals [ AccessKey ] = GV ; } else { GV = GEPGlobals


<s> <ISA_LIT>PacketizerList ( MachineFunction & MF , MachineLoopInfo & MLI ) : VLIWPacketizerList ( MF , MLI ) , TII ( static_cast < const <ISA_LIT>InstrInfo * > ( MF . getSubtarget ( ) . getInstrInfo ( ) ) ) , TRI ( TII -> getRegisterInfo ( ) ) { VLIW5 = ! MF . getSubtarget < <ISA_LIT>Subtarget > ( )


<s> break ; case <STR_LIT> : if ( ! CuMode ) { if ( ( Op & <STR_LIT> ) != <STR_LIT> ) VMCnt |= true ; if ( ( Op & <STR_LIT> ) != <STR_LIT> ) VSCnt |= true ; } break ; case <STR_LIT> : case <STR_LIT> : break ; default : llvm_unreachable ( <STR_LIT> ) ; } } if ( ( AddrSpace & <STR_LIT> ) != <STR_LIT> ) { switch ( Scope ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : LGKMCnt |= IsCrossAddrSpaceOrdering ; break ; case <STR_LIT> : case <STR_LIT> : break ; default : llvm_unreachable ( <STR_LIT> ) ; } } if ( ( AddrSpace & <STR_LIT> ) != <STR_LIT> ) { switch ( Scope ) { case <STR_LIT> : case <STR_LIT> : LGKMCnt |= IsCrossAddrSpaceOrdering ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : break ; default : llvm_unreachable ( <STR_LIT> ) ; } } if ( VMCnt || LGKMCnt ) { unsigned WaitCntImmediate = <STR_LIT> ( IV , VMCnt ? <NUM_LIT> : getVmcntBitMask ( IV ) , getExpcntBitMask ( IV ) , LGKMCnt ? <NUM_LIT> : getLgkmcntBitMask ( IV ) ) ; BuildMI ( MBB , MI , DL , TII -> get ( <STR_LIT> ) ) . addImm ( WaitCntImmediate ) ; Changed = true ; } if ( VSCnt ) { BuildMI ( MBB , MI , DL , TII -> get ( <STR_LIT> ) ) . addReg ( <STR_LIT> , RegState :: Undef ) . addImm ( <NUM_LIT> ) ; Changed = true ; } if ( Pos == Position :: AFTER ) -- MI ; return Changed


<s> if ( ! Preheader ) { return false ; } for ( MachineInstr & MI : * Preheader ) { if ( MI . getOpcode ( ) == <STR_LIT> ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; MI . removeFromParent


<s> unsigned Offset = AFI -> getCalleeSavedStackSize ( ) ; for ( unsigned i = <NUM_LIT> ; i < Count ; ++ i ) { RegPairInfo RPI ; RPI . Reg1 = CSI [ i ] . getReg ( ) ; assert ( <STR_LIT> . contains ( RPI . Reg1 ) || <STR_LIT> . contains ( RPI . Reg1 ) ) ; RPI . IsGPR = <STR_LIT> . contains ( RPI . Reg1 ) ; if ( i + <NUM_LIT> < Count ) { unsigned NextReg = CSI [ i + <NUM_LIT> ] . getReg ( ) ; if ( ( RPI . IsGPR && <STR_LIT> . contains ( NextReg ) ) || ( ! RPI . IsGPR && <STR_LIT> . contains ( NextReg ) ) ) RPI . Reg2 = NextReg ; } assert ( ( ! RPI . isPaired ( ) || ( CSI [ i ] . getFrameIdx ( ) + <NUM_LIT> == CSI [ i + <NUM_LIT> ] . getFrameIdx ( ) ) ) && <STR_LIT> ) ; assert ( ( ! produceCompactUnwindFrame ( MF ) || CC == CallingConv :: PreserveMost || ( RPI . isPaired ( ) && ( ( RPI . Reg1 == <STR_LIT> && RPI . Reg2 == <STR_LIT> ) || RPI . Reg1 + <NUM_LIT> == RPI . Reg2 ) ) ) && <STR_LIT> ) ; RPI . FrameIdx = CSI [ i ] . getFrameIdx ( ) ; if ( Count * <NUM_LIT> != AFI -> getCalleeSavedStackSize ( ) && ! RPI . isPaired ( ) ) { Offset -= <NUM_LIT>


<s> static void aarch64_emit_load_exclusive ( machine_mode mode , rtx rval , rtx mem , rtx model_rtx ) { emit_insn ( gen_aarch64_load_exclusive ( mode , rval ,


<s> if ( MI . getOpcode ( ) == <STR_LIT> ) Offset = - Offset ; int64_t AbsPostOffset = std :: abs ( Offset - Size ) ; const int64_t kMaxOffset = <NUM_LIT> ; if ( AbsPostOffset <= kMaxOffset && AbsPostOffset % <NUM_LIT> == <NUM_LIT> ) { * TotalOffset = Offset ; return true ; } } return


<s> Op -> Mem . OffsetRegShifted = OffsetRegShifted ; Op -> Mem . ShiftType = ShiftType ; Op -> Mem . ShiftAmount = ShiftAmount ; Op -> Mem . Preindexed = Preindexed ; Op -> Mem . Postindexed = Postindexed ; Op -> Mem . Negative = Negative ; Op -> Mem . Writeback = Writeback ; Op -> StartLoc = S ; Op -> EndLoc = E


<s> const BasicBlock * LLVM_BB = BB -> getBasicBlock ( ) ; MachineFunction :: iterator It = BB ; ++ It ; MachineBasicBlock * thisMBB = BB ; MachineFunction * F = BB -> getParent ( ) ; MachineBasicBlock * copy0MBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * sinkMBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; F -> insert ( It , copy0MBB ) ; F -> insert ( It , sinkMBB ) ; sinkMBB -> splice ( sinkMBB -> begin ( ) , BB , llvm :: next ( MachineBasicBlock :: iterator ( MI ) ) , BB -> end ( ) ) ; sinkMBB -> transferSuccessorsAndUpdatePHIs ( BB ) ; BB -> addSuccessor ( copy0MBB ) ; BB -> addSuccessor ( sinkMBB ) ; BuildMI ( BB , dl , TII . get ( <STR_LIT> ) ) . addMBB ( sinkMBB ) . addImm ( CC ) ; BB = copy0MBB


<s> MCCFIInstruction llvm :: createDefCFA ( const TargetRegisterInfo & TRI , unsigned FrameReg , unsigned Reg , const StackOffset & Offset , bool LastAdjustmentWasScalable ) { if ( Offset . getScalable ( ) ) return createDefCFAExpression ( TRI , Reg , Offset ) ; if ( FrameReg == Reg && ! LastAdjustmentWasScalable ) return MCCFIInstruction :: cfiDefCfaOffset ( nullptr , int ( Offset . getFixed ( ) ) ) ; unsigned DwarfReg = TRI . getDwarfRegNum ( Reg


<s> ++ It , ++ SccNum ) { const std :: vector < MachineBasicBlock * > & SccNext = * It ; for ( std :: vector < MachineBasicBlock * > :: const_iterator blockIter = SccNext . begin ( ) , blockEnd = SccNext . end ( ) ; blockIter != blockEnd ; ++ blockIter ) { MBB = * blockIter ; OrderedBlks . push_back ( MBB ) ; recordSccnum ( MBB , SccNum ) ; } } for ( auto * MBB : nodes ( MF ) ) { SccNum = getSCCNum ( MBB


<s> MVT <ISA_LIT>TargetLowering :: getScalarShiftAmountTy ( const DataLayout & DL


<s> const TargetFrameLowering * getFrameLowering (


<s> EVT LdVT = LoadNode -> getMemoryVT ( ) ; if ( LdVT != <STR_LIT> && LdVT != <STR_LIT> && LdVT != <STR_LIT> && LdVT != <STR_LIT> ) return false ; SDValue Undef = StoreNode -> getOffset ( ) ; if ( Undef -> getOpcode ( ) != <STR_LIT> ) return false ; if ( StoredVal . getResNo ( ) != <NUM_LIT> ) return false ; if ( ! StoredVal . getNode ( ) -> hasNUsesOfValue ( <NUM_LIT> , <NUM_LIT> ) ) return false ; if ( ! LoadNode -> hasNUsesOfValue ( <NUM_LIT> , <NUM_LIT> ) ) return false ; if ( StoredVal -> getOperand ( <NUM_LIT> ) . getNode ( ) != LoadNode ) return false ; if ( StoreNode -> isNonTemporal ( ) ) return false ; SDValue Address = StoreNode


<s> if ( code == EQ || code == NE ) { rtx zie = mips_zero_if_equal ( cmp_operands [ <NUM_LIT> ] , cmp_operands [ <NUM_LIT> ] ) ; mips_emit_binary ( code , target , zie


<s> if ( label_align && n >= min_labelno && n <= max_labelno ) return MAX ( label_align [ n - min_labelno ] , align_labels . levels [ <NUM_LIT> ] . log ) ; return align_labels . levels [


<s> assert ( model == TLSModel :: LocalExec ) ; SDValue TGAHi = DAG . getTargetGlobalAddress ( GV , DL , PtrVT , <NUM_LIT> , <STR_LIT> ) ; SDValue TGALo = DAG . getTargetGlobalAddress ( GV , DL , PtrVT , <NUM_LIT> , <STR_LIT> ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , DL , PtrVT , TGAHi ) ; SDValue Lo = DAG . getNode ( <STR_LIT>


<s> static SDValue CreateCopyOfByValArgument ( SDValue Src , SDValue Dst , SDValue Chain , <STR_LIT> Flags , SelectionDAG


<s> int RegNum = parseRegisterName ( & MatchRegisterName ) ; if ( RegNum == <STR_LIT> ) RegNum = parseRegisterName ( & MatchRegisterAltName


<s> static int getFPOffsetInPrologue ( MachineInstr * MBBI ) { assert ( ( ( MBBI -> getOpcode ( ) == <STR_LIT> || MBBI -> getOpcode ( ) == <STR_LIT> ) && MBBI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> && MBBI -> getOperand ( <NUM_LIT> ) . getImm ( ) < <NUM_LIT> && ( MBBI -> getOperand ( <NUM_LIT> ) . getImm ( ) & <NUM_LIT> ) == <NUM_LIT> ) ) ; int FPOffset = - ( MBBI -> getOperand ( <NUM_LIT> ) . getImm ( ) + <NUM_LIT> ) * <NUM_LIT> ; assert ( FPOffset >= <NUM_LIT> && <STR_LIT> ) ; return FPOffset


<s> MCInst tmpInst ; const MCOperand & ImmOp = Inst . getOperand ( <NUM_LIT> ) ; assert ( ImmOp . isImm ( ) && <STR_LIT> ) ; const MCOperand & RegOp = Inst . getOperand ( <NUM_LIT> ) ; assert ( RegOp . isReg ( ) && <STR_LIT> ) ; int ImmValue = ImmOp . getImm ( ) ; tmpInst . setLoc ( IDLoc ) ; if ( <NUM_LIT> <= ImmValue && ImmValue <= <NUM_LIT> ) { tmpInst . setOpcode ( is<ISA_LIT>64 ( ) ? <STR_LIT> : <STR_LIT> ) ; tmpInst . addOperand ( MCOperand :: CreateReg ( RegOp . getReg ( ) ) ) ; tmpInst . addOperand ( MCOperand :: CreateReg ( is<ISA_LIT>64 ( ) ? <STR_LIT> : <STR_LIT> ) ) ; tmpInst . addOperand ( MCOperand :: CreateImm ( ImmValue ) ) ; Instructions . push_back ( tmpInst ) ; } else if ( ImmValue < <NUM_LIT>


<s> return ( uint64x2_t ) __builtin_aarch64_usublv2si ( ( int32x2_t )


<s> auto Cst = MIB . buildConstant ( MRI . cloneVirtualRegister ( RHS . getReg ( ) ) , MatchInfo . first ) ; Observer . changingInstr ( MI ) ; RHS . setReg ( Cst -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; MI . getOperand ( <NUM_LIT> ) . setPredicate ( MatchInfo . second ) ; Observer . changedInstr ( MI ) ; return true


<s> static void get_scratch_register_on_entry ( struct scratch_reg * sr , unsigned int regno1 , unsigned long live_regs ) { int regno = - <NUM_LIT> ; sr -> saved = false ; if ( regno1 != LR_REGNUM && ( live_regs & ( <NUM_LIT> << LR_REGNUM ) ) != <NUM_LIT> ) regno = LR_REGNUM ; else { unsigned int i ; for ( i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) if ( regno1 != i && ( live_regs & ( <NUM_LIT> << i ) ) != <NUM_LIT> ) { regno = i ; break ; } if ( regno < <NUM_LIT> ) { if ( regno1 == IP_REGNUM && IS_NESTED ( arm_current_func_type ( ) ) ) regno1 = <NUM_LIT> ; regno = ( regno1 == <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ) ; sr -> saved = REGNO_REG_SET_P ( df_get_live_out ( ENTRY_BLOCK_PTR_FOR_FN ( cfun ) ) , regno ) ; } } sr -> reg = gen_rtx_REG ( SImode , regno ) ; if ( sr -> saved ) { rtx addr = gen_rtx_PRE_DEC ( Pmode , stack_pointer_rtx ) ; rtx insn = emit_set_insn ( gen_frame_mem ( SImode , addr ) , sr -> reg ) ; rtx x = gen_rtx_SET ( stack_pointer_rtx , plus_constant ( Pmode


<s> setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Promote ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Promote ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Promote ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Promote ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Promote ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Promote ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Promote ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> ,


<s> SDValue NewST1 = DAG . getStore ( St -> getChain ( ) , DL , StVal . getNode ( ) -> getOperand ( isBigEndian ? <NUM_LIT> : <NUM_LIT> ) , BasePtr , St -> getPointerInfo ( ) , St -> getAlignment ( ) , St -> getMemOperand ( ) -> getFlags ( ) ) ; SDValue OffsetPtr = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , BasePtr , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; return DAG . getStore ( NewST1 . getValue ( <NUM_LIT> ) , DL , StVal . getNode ( ) -> getOperand ( isBigEndian ? <NUM_LIT> : <NUM_LIT> ) , OffsetPtr , St -> getPointerInfo ( ) , std :: min ( <NUM_LIT> , St -> getAlignment ( ) / <NUM_LIT> ) , St -> getMemOperand ( ) -> getFlags ( ) ) ; } if ( StVal . getValueType ( ) == <STR_LIT> && StVal . getNode ( ) -> getOpcode ( ) == <STR_LIT> ) { SelectionDAG & DAG = DCI . DAG ; SDLoc dl ( StVal ) ; SDValue IntVec = StVal . getOperand


<s> return getTM < <ISA_LIT>TargetMachine


<s> <ISA_LIT>MCAsmInfoMicrosoft :: <ISA_LIT>MCAsmInfoMicrosoft ( const Triple & Triple ) { if ( Triple . getArch ( ) == Triple :: x86_64 ) { PrivateGlobalPrefix = <STR_LIT> ; PointerSize = <NUM_LIT> ; ExceptionsType = ExceptionHandling :: WinEH ; } AssemblerDialect = AsmWriterFlavor ; TextAlignFillValue = <NUM_LIT>


<s> const MCPhysReg * <ISA_LIT>RegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { assert ( MF && <STR_LIT> ) ; if ( MF -> getFunction ( ) -> getCallingConv ( ) == CallingConv

:: AnyReg ) return CSR_<ISA_LIT>_AllRegs_SaveList ;


<s> else { gpr_reg_base = <NUM_LIT> ; fpr_reg_base = <NUM_LIT> ; } if ( mode == BLKmode || ( type && ( AGGREGATE_TYPE_P ( type ) || TREE_CODE ( type ) == COMPLEX_TYPE || TREE_CODE ( type ) == VECTOR_TYPE ) ) ) { rtx loc = gen_rtx_EXPR_LIST ( VOIDmode , gen_rtx_REG ( DImode , gpr_reg_base ) , const0_rtx ) ; return gen_rtx_PARALLEL ( BLKmode , gen_rtvec ( <NUM_LIT> , loc ) ) ; } } else { gpr_reg_base = <NUM_LIT> - cum -> words ; fpr_reg_base = <NUM_LIT> + <NUM_LIT> * cum -> words ; } } if ( ( ( TARGET_PORTABLE_RUNTIME || TARGET_64BIT || TARGET_ELF32 ) && ! TARGET_SOFT_FLOAT && GET_MODE_CLASS ( mode ) == MODE_FLOAT && cum -> nargs_prototype <= <NUM_LIT> && type != NULL_TREE && ! cum -> incoming ) || ( ! TARGET_64BIT && ! TARGET_GAS && ! cum -> incoming && cum -> indirect && GET_MODE_CLASS ( mode ) == MODE_FLOAT ) ) { retval = gen_rtx_PARALLEL ( mode , gen_rtvec ( <NUM_LIT> , gen_rtx_EXPR_LIST ( VOIDmode , gen_rtx_REG ( mode , fpr_reg_base ) , const0_rtx ) , gen_rtx_EXPR_LIST ( VOIDmode , gen_rtx_REG ( mode , gpr_reg_base ) , const0_rtx ) ) ) ; } else { if ( TARGET_SOFT_FLOAT || ( ! TARGET_PORTABLE_RUNTIME && ! TARGET_64BIT && ! TARGET_ELF32 && cum -> indirect ) || GET_MODE_CLASS ( mode ) != MODE_FLOAT || ( type && AGGREGATE_TYPE_P (

type ) ) ) retval = gen_rtx_REG ( mode , gpr_reg_base ) ;


<s> static const IntrinsicData * getIntrinsicWithoutChain ( unsigned IntNo ) { const IntrinsicData * Data = lower_bound ( IntrinsicsWithoutChain , IntNo ) ; if ( Data != std :: end ( IntrinsicsWithoutChain ) && Data -> Id == IntNo ) return Data ; return nullptr


<s> void <ISA_LIT>PassConfig :: addIRPasses ( ) { addPass ( createAtomicExpandPass ( ) ) ; TargetPassConfig :: addIRPasses (


<s> IsQRegs = false ; } else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) { SubRegs = <NUM_LIT> ; IsQRegs = false ; } else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) { SubRegs = <NUM_LIT> ; IsQRegs = true ; } else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) { SubRegs = <NUM_LIT> ; IsQRegs = true ; } else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) { SubRegs = <NUM_LIT> ; IsQRegs = true ; } else llvm_unreachable ( <STR_LIT> ) ; unsigned BeginIdx = IsQRegs ? <STR_LIT> : <STR_LIT> ; int Spacing = <NUM_LIT> ; const TargetRegisterInfo * TRI = & getRegisterInfo ( ) ; if ( TRI -> regsOverlap ( SrcReg , TRI -> getSubReg ( DestReg , BeginIdx ) ) ) { BeginIdx = BeginIdx + ( SubRegs - <NUM_LIT> ) ; Spacing = - <NUM_LIT> ; } unsigned Opc = IsQRegs ? <STR_LIT> : <STR_LIT> ; for ( unsigned i = <NUM_LIT> ; i != SubRegs ; ++ i ) { unsigned Dst = TRI -> getSubReg ( DestReg , BeginIdx + i * Spacing ) ; unsigned Src = TRI -> getSubReg ( SrcReg , BeginIdx + i * Spacing ) ; assert ( Dst && Src && <STR_LIT> ) ; BuildMI ( MBB , I , I -> getDebugLoc ( ) , get ( Opc )

, Dst ) . addReg ( Src ) . addReg ( Src ) ;


<s> std :: unique_ptr < MCObjectWriter > llvm :: create<ISA_LIT>OMFObjectWriter ( raw_pwrite_stream & OS ) { return createOMFObjectWriter ( OS )


<s> return ( MCII . get ( MCI . getOpcode (


<s> unsigned Lg2 = Divisor . countTrailingZeros ( ) ; SDValue Zero = DAG . getConstant ( <NUM_LIT> , DL , VT ) ; SDValue Pow2MinusOne = DAG . getConstant ( ( <NUM_LIT> << Lg2 ) - <NUM_LIT> , DL , VT ) ; SDValue CCVal ; SDValue Cmp = get<ISA_LIT>Cmp ( N0 , Zero , <STR_LIT> , CCVal , DAG , DL ) ; SDValue Add = DAG . getNode ( <STR_LIT> , DL , VT , N0 , Pow2MinusOne ) ; SDValue CSel = DAG . getNode ( <STR_LIT> , DL , VT , Add , N0 , CCVal , Cmp ) ; if ( Created ) { Created -> push_back ( Cmp . getNode ( ) ) ; Created -> push_back ( Add .


<s> TargetPassConfig * <ISA_LIT>TargetMachine :: createPassConfig ( PassManagerBase


<s> } auto BTI = <STR_LIT> ( Tok . getString ( ) ) ; if ( ! BTI ) { TokError ( <STR_LIT> ) ; return MatchOperand_ParseFail ; } Operands . push_back ( <ISA_LIT>Operand :: CreateBTIHint ( BTI -> Encoding , Tok . getString ( ) , S , getContext ( ) ) ) ; Parser . Lex (


<s> bool sh_lshrsi_clobbers_t_reg_p ( rtx shift_amount ) { gcc_assert ( CONST_INT_P ( shift_amount ) ) ; const int shift_amount_i = std :: abs ( INTVAL ( shift_amount ) ) & <NUM_LIT> ; if ( shift_amount_i == <NUM_LIT> ) return true ; return ( ashl_lshr_seq [ shift_amount_i ] . clobbers_t & LSHR_CLOBBERS_T


<s> const MCOperand & MO1 = MI . getOperand ( OpIdx + <NUM_LIT> ) ; unsigned Reg = CTX . getRegisterInfo ( ) -> getEncodingValue ( MO . getReg ( ) ) ; unsigned Imm8 = MO1 . getImm ( ) ; return ( Reg << <NUM_LIT>


<s> void setVectorDataSize ( unsigned Sz )


<s> SDValue Ops [ ] = { N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) } ; SDNode * CmpSwap = CurDAG -> getMachineNode ( Opcode , SDLoc ( N ) , CurDAG -> getVTList ( <STR_LIT> , <STR_LIT> , <STR_LIT> ) , Ops ) ; MachineMemOperand * MemOp = cast < MemSDNode > ( N ) -> getMemOperand ( ) ; CurDAG -> setNodeMemRefs ( cast < MachineSDNode > ( CmpSwap ) , { MemOp } ) ; ReplaceUses ( SDValue ( N , <NUM_LIT> ) , SDValue ( CmpSwap , <NUM_LIT> ) ) ; ReplaceUses ( SDValue ( N , <NUM_LIT> ) , SDValue ( CmpSwap ,


<s> bool <ISA_LIT>DAGToDAGISel :: SelectADDRsi64 ( SDNode * OpNode , SDValue Addr , SDValue & Base


<s> return ( __m128d ) __builtin_ia32_vfmaddsubpd ( ( __v2df ) __A , (


<s> unsigned Opc = Cond [ <NUM_LIT> ] . getImm ( ) ; const MCInstrDesc & MCID = get ( Opc ) ; MachineInstrBuilder MIB = BuildMI ( & MBB , DL , MCID ) ; for ( unsigned i = <NUM_LIT> ; i < Cond . size ( ) ; ++ i ) { if ( Cond [ i ] . isReg ( ) ) MIB . addReg ( Cond [ i ] . getReg ( ) ) ; else if ( Cond [ i ] . isImm ( ) ) MIB . addImm ( Cond [ i ] . getImm ( ) ) ; else assert ( false && <STR_LIT> ) ; } MIB . addMBB


<s> if ( is_end ) emit_jump_insn ( gen_doloop_end_internal ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] , tag ) ) ; else emit_insn ( gen_doloop_begin_internal ( operands [ <NUM_LIT> ] ,


<s> return __builtin_aarch64_cmeqhf_uss ( __a ,


<s> if ( StoredVal . hasOneUse ( ) && collectConcatOps ( StoredVal . getNode ( ) , CatOps ) ) return splitVectorStore ( St , DAG ) ; return SDValue ( ) ; } const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; assert ( StoreVT . isVector ( ) && StoreVT . getSizeInBits ( ) == <NUM_LIT> && <STR_LIT> ) ; assert ( TLI . getTypeAction ( * DAG . getContext ( ) , StoreVT ) == TargetLowering :: TypeWidenVector && <STR_LIT> ) ; EVT WideVT = TLI . getTypeToTransformTo ( * DAG . getContext ( ) , StoreVT ) ; StoredVal = DAG . getNode ( <STR_LIT> , dl , WideVT , StoredVal , DAG . getUNDEF ( StoreVT ) ) ; if ( Subtarget . hasSSE2 ( ) ) { MVT StVT = Subtarget . is64Bit ( ) && StoreVT . isInteger ( ) ? <STR_LIT> : <STR_LIT> ; MVT CastVT = <STR_LIT> ( StVT , <NUM_LIT> ) ; StoredVal = DAG . getBitcast ( CastVT , StoredVal ) ; StoredVal = DAG . getNode ( <STR_LIT> , dl , StVT , StoredVal , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ; return DAG . getStore ( St -> getChain ( ) , dl , StoredVal , St -> getBasePtr ( ) , St -> getPointerInfo ( ) , St -> getOriginalAlign ( ) , St -> getMemOperand ( ) -> getFlags ( ) ) ; } assert ( Subtarget . hasSSE1 ( ) && <STR_LIT> ) ; SDVTList Tys = DAG .


<s> SmallString < <NUM_LIT> > Msg ; raw_svector_ostream OS ( Msg ) ; OS << <STR_LIT> ; for ( unsigned i = <NUM_LIT> ; i != NumMatches ; ++ i ) { if ( i != <NUM_LIT> ) OS << <STR_LIT> ; if ( i + <NUM_LIT> == NumMatches ) OS << <STR_LIT> ; OS << <STR_LIT> << Base << MatchChars [ i ] << <STR_LIT> ; } OS << <STR_LIT> ; Error ( IDLoc , OS . str ( ) , EmptyRange , MatchingInlineAsm ) ; return true ; } if ( std :: count ( std :: begin ( Match ) , std :: end ( Match ) , Match_MnemonicFail ) == <NUM_LIT> ) { if ( ! WasOriginallyInvalidOperand ) { return Error ( IDLoc , <STR_LIT> + Base + <STR_LIT> , Op . getLocRange ( ) , MatchingInlineAsm ) ; } if ( ErrorInfo != ~ <NUM_LIT> ) { if ( ErrorInfo >= Operands . size ( ) ) return Error ( IDLoc , <STR_LIT> , EmptyRange , MatchingInlineAsm ) ; <ISA_LIT>Operand & Operand = ( <ISA_LIT>Operand & ) * Operands [ ErrorInfo ] ; if ( Operand . getStartLoc ( ) . isValid ( ) ) { SMRange OperandRange = Operand . getLocRange ( ) ; return Error ( Operand . getStartLoc ( ) , <STR_LIT> , OperandRange , MatchingInlineAsm ) ; } } return Error ( IDLoc , <STR_LIT> , EmptyRange , MatchingInlineAsm ) ; } if ( std :: count ( std :: begin ( Match ) , std :: end ( Match ) , Match_MissingFeature ) == <NUM_LIT> ) { ErrorInfo = ErrorInfoMissingFeature ; return ErrorMissingFeature ( IDLoc , ErrorInfoMissingFeature , MatchingInlineAsm ) ; } if ( std :: count ( std :: begin ( Match ) , std :: end ( Match ) , Match_InvalidOperand


<s> CCInfo . clearWas<ISA_LIT>F128 ( ) ; for ( unsigned i = <NUM_LIT> , e = ArgLocs . size ( ) ; i != e ; ++ i ) { CCValAssign & VA = ArgLocs [ i ] ; if ( VA . isRegLoc ( ) ) { const TargetRegisterClass * RC ; EVT ValVT = VA . getValVT ( ) ; switch ( ValVT . getSimpleVT ( ) . SimpleTy ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : RC = & <STR_LIT> ; break ; case <STR_LIT> : if ( Subtarget . hasP8Vector ( ) ) RC = & <STR_LIT> ; else RC = & <STR_LIT> ; break ; case <STR_LIT> : if ( Subtarget . hasVSX ( ) ) RC = & <STR_LIT> ; else RC = & <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : RC = & <STR_LIT> ; break ; case <STR_LIT> : RC = Subtarget . hasQPX ( ) ? & <STR_LIT> : & <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : RC = & <STR_LIT> ; break ; case <STR_LIT> : RC = & <STR_LIT> ; break ; case <STR_LIT> : RC = & <STR_LIT> ; break ; } unsigned Reg = MF . addLiveIn ( VA . getLocReg ( ) , RC ) ; SDValue ArgValue = DAG . getCopyFromReg ( Chain , dl , Reg , ValVT == <STR_LIT> ? <STR_LIT> : ValVT ) ; if ( ValVT == <STR_LIT> ) ArgValue = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , ArgValue ) ; InVals . push_back ( ArgValue ) ; } else { assert ( VA . isMemLoc ( ) ) ; unsigned ArgSize = VA . getLocVT ( ) . getStoreSize ( ) ; int FI = MFI -> CreateFixedObject ( ArgSize , VA . getLocMemOffset ( ) , isImmutable ) ; SDValue FIN = DAG . getFrameIndex ( FI , PtrVT ) ; InVals . push_back ( DAG . getLoad ( VA . getValVT ( ) , dl , Chain , FIN , MachinePointerInfo ( ) ) ) ; } } SmallVector < CCValAssign , <NUM_LIT> > ByValArgLocs ; CCState CCByValInfo ( CallConv , isVarArg , DAG . getMachineFunction ( ) , ByValArgLocs , * DAG . getContext ( ) ) ; CCByValInfo . AllocateStack ( CCInfo . getNextStackOffset ( ) , PtrByteSize ) ; CCByValInfo . AnalyzeFormalArguments ( Ins , CC_<ISA_LIT>32_SVR4_ByVal ) ; unsigned MinReservedArea = CCByValInfo .


<s> assert ( VecTy . getVectorElementType ( ) == <STR_LIT> ) ; unsigned HwLen = Subtarget . getVectorLength ( ) ; assert ( isPowerOf2_32 ( NumOp ) && HwLen % NumOp == <NUM_LIT> ) ; SDValue Op0 = Op . getOperand ( <NUM_LIT> ) ; if ( Subtarget . isHVXVectorType ( ty ( Op0 ) , true ) ) { if ( NumOp == <NUM_LIT> ) return DAG . getNode ( <STR_LIT> , dl , VecTy , Op0 , Op . getOperand ( <NUM_LIT> ) ) ; ArrayRef < SDUse > U ( Op . getNode ( ) -> ops ( ) ) ; SmallVector < SDValue , <NUM_LIT> > SV ( U . begin ( ) , U . end ( ) ) ; ArrayRef < SDValue > Ops ( SV ) ; MVT HalfTy = typeSplit ( VecTy ) . first ; SDValue V0 = DAG . getNode ( <STR_LIT> , dl , HalfTy , Ops . take_front ( NumOp / <NUM_LIT> ) ) ; SDValue V1 = DAG . getNode ( <STR_LIT> , dl , HalfTy , Ops . take_back ( NumOp / <NUM_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , dl , VecTy , V0 , V1 ) ; } unsigned BitBytes = HwLen / VecTy . getVectorNumElements ( ) ; SmallVector < SDValue , <NUM_LIT> > Prefixes ; for ( SDValue V : Op . getNode ( ) -> op_values ( ) ) { SDValue P = createHvxPrefixPred ( V , dl , BitBytes , true , DAG ) ; Prefixes . push_back ( P ) ; } unsigned InpLen = ty ( Op . getOperand ( <NUM_LIT> ) ) . getVectorNumElements ( ) ; MVT ByteTy = <STR_LIT> ( <STR_LIT> , HwLen ) ; SDValue S = DAG . getConstant ( InpLen * BitBytes , dl , <STR_LIT> ) ; SDValue Res = getZero ( dl , ByteTy , DAG ) ; for ( unsigned i = <NUM_LIT> , e = Prefixes . size ( ) ; i != e ; ++ i ) { Res = DAG . getNode ( <STR_LIT> , dl , ByteTy , Res , S ) ; Res = DAG . getNode ( <STR_LIT> , dl , ByteTy , Res , Prefixes [ e - i - <NUM_LIT> ] ) ; } return DAG . getNode ( <STR_LIT> , dl , VecTy , Res


<s> Update = findMatchingUpdateInsnBackward ( MBBI , UpdateLimit ) ; if ( Update != E ) { MBBI = mergeUpdateInsn ( MBBI , Update , true ) ; return true ; } int UnscaledOffset = getLdStOffsetOp ( MI ) . getImm ( ) * TII -> getMemScale ( MI ) ; Update = findMatchingUpdateInsnForward ( MBBI , UnscaledOffset , UpdateLimit ) ; if ( Update != E ) { MBBI = mergeUpdateInsn ( MBBI , Update , true ) ; return true ; } return false


<s> return ( __m512i ) __builtin_ia32_vplzcntq_512_mask ( ( __v8di ) __A , ( __v8di ) _mm512_setzero_si512 ( ) ,


<s> rtx cc_reg = gen_rtx_REG ( mode , CC_REGNUM ) ; emit_insn ( gen_rtx_SET ( VOIDmode , cc_reg , gen_rtx_COMPARE ( mode , x , y ) ) ) ; return


<s> Binary |= II -> getPredicate ( & MI ) << <STR_LIT> ; unsigned OpIdx = <NUM_LIT> ; assert ( ( Binary & <STR_LIT> ) == <NUM_LIT> && ( Binary & <STR_LIT> ) == <NUM_LIT> && ( Binary & <STR_LIT> ) == <NUM_LIT> && <STR_LIT> ) ; Binary |= encodeVFPRd ( MI , OpIdx ++ ) ; if ( MCID . getOperandConstraint ( OpIdx , MCOI :: TIED_TO ) != - <NUM_LIT> ) ++ OpIdx ; if ( ( MCID . TSFlags & <STR_LIT> ) == <STR_LIT> ) Binary |= encodeVFPRn ( MI , OpIdx ++ ) ; if ( OpIdx == MCID . getNumOperands ( ) || MCID . OpInfo [ OpIdx ] . isPredicate ( ) || MCID . OpInfo [ OpIdx ] . isOptionalDef ( ) ) { emitWordLE (


<s> if ( DstVT != <STR_LIT> ) return SDValue ( ) ; SDValue Op0 = Op -> getOperand ( <NUM_LIT> ) ; SmallVector < SDValue , <NUM_LIT> > Elts ; SDLoc dl ( Op ) ; unsigned NumElts ; MVT SVT ; if ( SrcVT . isVector ( ) ) { NumElts = SrcVT . getVectorNumElements ( ) ; SVT = SrcVT . getVectorElementType ( ) ; for ( unsigned i = <NUM_LIT> , e = NumElts ; i != e ; ++ i ) Elts . push_back ( DAG . getNode ( <STR_LIT> , dl , SVT , Op0 , DAG . getIntPtrConstant ( i , dl ) ) ) ; } else { assert ( SrcVT == <STR_LIT> && ! Subtarget . is64Bit ( ) && <STR_LIT> ) ; Elts . push_back ( DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op0 , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ) ; Elts . push_back ( DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op0 , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ) ; NumElts = <NUM_LIT> ; SVT = <STR_LIT> ; } Elts . append ( NumElts , DAG . getUNDEF ( SVT ) ) ; EVT NewVT = EVT :: getVectorVT ( * DAG . getContext ( ) , SVT , NumElts * <NUM_LIT> ) ; SDValue BV = DAG . getBuildVector ( NewVT , dl , Elts ) ; SDValue ToV2F64 = DAG . getBitcast ( <STR_LIT> , BV ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , ToV2F64 , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ; } assert ( Subtarget . is64Bit ( ) && ! Subtarget . hasSSE2 ( ) && Subtarget . hasMMX ( ) && <STR_LIT> ) ; assert ( ( DstVT == <STR_LIT> || ( DstVT . isVector ( ) && DstVT . getSizeInBits ( ) == <NUM_LIT> ) ) && <STR_LIT> ) ; if ( SrcVT == <STR_LIT> && DstVT . isVector


<s> Value * <ISA_LIT>IREmitter :: visitFMINC ( const SDNode * N ) { llvm_unreachable ( <STR_LIT> )


<s> MachineFunction * MF = MI -> getParent ( ) -> getParent ( ) ; MachineFrameInfo * FrameInfo = MF -> getFrameInfo ( ) ; const <ISA_LIT>InstrInfo * TII = static_cast < const <ISA_LIT>InstrInfo * > ( ST . getInstrInfo ( ) ) ; MachineOperand & FIOp = MI -> getOperand ( FIOperandNum ) ; int Index = MI -> getOperand ( FIOperandNum ) .


<s> BuildMI ( MBB , & MI , DL , TII -> get ( AMDGPU :: V_CMPX_LE_F32_e32 ) , AMDGPU :: VCC ) . addImm ( <NUM_LIT> ) . addOperand ( MI .


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case


<s> SDValue ConstVec ; SDValue Arg ; MVT VT = Op . getValueType ( ) ; DebugLoc dl = Op . getDebugLoc ( ) ; ConstVec = Op . getOperand ( <NUM_LIT> ) ; Arg = Op . getOperand ( <NUM_LIT> ) ; if ( ConstVec . getNode ( ) -> getOpcode ( ) != <STR_LIT> ) { if ( ConstVec . getNode ( ) -> getOpcode ( ) == <STR_LIT> ) { ConstVec = ConstVec . getOperand ( <NUM_LIT> ) ; } else { ConstVec = Op . getOperand ( <NUM_LIT> ) ; Arg = Op . getOperand ( <NUM_LIT> ) ; if ( ConstVec . getNode ( ) -> getOpcode ( ) == <STR_LIT> ) { ConstVec = ConstVec . getOperand ( <NUM_LIT> ) ; } } } if ( ConstVec . getNode ( ) -> getOpcode ( ) == <STR_LIT> ) { BuildVectorSDNode * BCN = dyn_cast < BuildVectorSDNode > ( ConstVec . getNode ( ) ) ; assert ( BCN != <NUM_LIT> && <STR_LIT> ) ; APInt APSplatBits , APSplatUndef ; unsigned SplatBitSize ; bool HasAnyUndefs ; unsigned minSplatBits = VT . getVectorElementType ( ) . getSizeInBits ( ) ; if ( BCN -> isConstantSplat ( APSplatBits , APSplatUndef , SplatBitSize , HasAnyUndefs , minSplatBits ) && minSplatBits <= SplatBitSize ) { uint64_t SplatBits = APSplatBits . getZExtValue ( ) ; SDValue tc = DAG . getTargetConstant ( SplatBits


<s> void addRegWithInputModsOperands ( MCInst & Inst , unsigned N ) const { Inst . addOperand ( MCOperand :: createImm ( Reg . Modifiers == - <NUM_LIT> ? <NUM_LIT> : Reg . Modifiers ) ) ; addRegOperands ( Inst ,


<s> if ( ! isMMThreeBitGPRegister ( MI -> getOperand ( <NUM_LIT> ) ) || ! isMMThreeBitGPRegister ( MI -> getOperand (

<NUM_LIT> ) ) || ! isMMThreeBitGPRegister ( MI -> getOperand ( <NUM_LIT> ) ) ) return false ;


<s> static bool AreAliased ( AliasAnalysis * AA , Instructions AliasCandidates , ParallelMACList & MACCandidates ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; for ( auto * I : AliasCandidates ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; I -> dump ( ) ) ; for ( auto & MAC : MACCandidates ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; MAC . Mul -> dump ( ) ) ; assert ( MAC . MemLocs . size ( ) >= <NUM_LIT> && <STR_LIT> ) ; for ( auto & MemLoc : MAC . MemLocs ) { if ( isModOrRefSet ( intersectModRef ( AA -> getModRefInfo ( I , MemLoc ) , ModRefInfo :: ModRef ) ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return


<s> void LLVMInitialize<ISA_LIT>AsmPrinter (


<s> const <ISA_LIT>Subtarget & get<ISA_LIT>Subtarget ( ) const { return * get<ISA_LIT>TargetMachine ( )


<s> assert ( ( Cond . size ( ) == <NUM_LIT> ) && <STR_LIT> ) ; Cond [ <NUM_LIT> ] . setImm ( getOppositeBranchOpcode ( Cond [ <NUM_LIT> ] . getImm ( ) ) ) ; return false


<s> int consecutive_zeros = <NUM_LIT> ; if ( ! ( val & ( <NUM_LIT> << i ) ) ) { while ( ( i < <NUM_LIT> ) && ! ( val & ( <NUM_LIT> << i ) ) ) { consecutive_zeros += <NUM_LIT> ; i += <NUM_LIT> ; } if ( consecutive_zeros > best_consecutive_zeros ) { best_consecutive_zeros = consecutive_zeros ; best_start = i - consecutive_zeros ; } i -= <NUM_LIT> ; } } } insns1 = optimal_immediate_sequence_1 ( code , val , return_sequence , best_start ) ; if ( best_start != <NUM_LIT> && ( ( ( ( unsigned HOST_WIDE_INT ) <NUM_LIT> ) << best_start ) < val ) ) { insns2 = optimal_immediate_sequence_1 ( code , val , & tmp_sequence , <NUM_LIT> ) ; if ( insns2 <= insns1


<s> return true ; } unsigned LaneSize = <NUM_LIT> ; SmallVector < int , <NUM_LIT> > MaskVal ( LaneSize , - <NUM_LIT> ) ; for ( unsigned l = <NUM_LIT> ; l != NumElts ; l += LaneSize ) { for ( unsigned i = <NUM_LIT> ; i != LaneSize ; ++ i ) { if ( ! isUndefOrInRange ( Mask [ i + l ] , l , l + LaneSize ) ) return false ; if ( Mask [ i + l ] <


<s> } bool Result = Parser . Error ( L , Msg , Range ) ; eatToEndOfLine ( ) ; CurrentSlot = SlotParser :: Unknown ; Bundle . clear ( ) ; Bundle . setOpcode ( <NUM_LIT> ) ; Bundle . setLoc ( SMLoc


<s> if ( MCDisableArithRelaxation ) return false ; if ( getRelaxedOpcodeArith ( Inst . getOpcode ( ) ) == Inst . getOpcode ( ) ) return false ; bool hasExp = false ; bool hasRIP = false ; for ( unsigned i = <NUM_LIT> ; i <


<s> int sh2a_get_function_vector_number ( rtx x ) { int num ; tree list , t ; if ( ( GET_CODE ( x ) == SYMBOL_REF ) && ( SYMBOL_REF_FLAGS ( x ) & SYMBOL_FLAG_FUNCVEC_FUNCTION ) ) { t = SYMBOL_REF_DECL ( x ) ; if ( TREE_CODE ( t ) != FUNCTION_DECL ) return <NUM_LIT> ; list = SH_ATTRIBUTES (


<s> if ( ( BaseReg . getReg ( ) != <NUM_LIT> && <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( BaseReg . getReg ( ) ) ) || ( IndexReg . getReg ( ) != <NUM_LIT> && <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( IndexReg . getReg ( ) ) ) ) return true ; return


<s> assert ( ! BytesRemoved && <STR_LIT> ) ; MachineBasicBlock :: iterator I = MBB . end ( ) ; unsigned Count = <NUM_LIT> ; while ( I != MBB . begin ( ) ) { -- I ; if ( I -> getOpcode (


<s> const MachineFunction * MF = MI -> getParent ( ) -> getParent ( ) ; const char * AsmStr = MI -> getOperand ( <NUM_LIT> ) . getSymbolName ( ) ; return getInlineAsmLength ( AsmStr , * MF -> getTarget ( ) . getMCAsmInfo ( ) ) ; } case <STR_LIT> : case <STR_LIT> : case


<s> SDValue ExtVec1 = N1 -> getOperand ( i ) ; if ( V != ExtVec0 -> getOperand ( <NUM_LIT> ) . getNode ( ) || V != ExtVec1 -> getOperand ( <NUM_LIT> ) . getNode ( ) ) return SDValue ( ) ; ConstantSDNode * C0 = dyn_cast < ConstantSDNode > ( ExtVec0 -> getOperand ( <NUM_LIT> ) ) ; ConstantSDNode * C1 = dyn_cast < ConstantSDNode > ( ExtVec1 -> getOperand ( <NUM_LIT> ) ) ; if ( ! C0 || ! C1 || C0 -> getZExtValue ( ) != nextIndex || C1 -> getZExtValue ( ) != nextIndex + <NUM_LIT> ) return SDValue ( ) ; nextIndex += <NUM_LIT> ; } else return SDValue ( ) ; } SelectionDAG & DAG = DCI . DAG ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; SDLoc dl ( N ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . push_back ( DAG . getConstant ( <STR_LIT> , dl , TLI . getPointerTy ( ) ) ) ; Ops . push_back ( Vec ) ; MVT widenType ; unsigned numElem = VT . getVectorNumElements ( ) ; EVT inputLaneType = Vec . getValueType ( ) . getVectorElementType ( ) ; switch ( inputLaneType . getSimpleVT ( ) . SimpleTy ) { case <STR_LIT> : widenType = <STR_LIT> ( <STR_LIT> , numElem ) ; break ; case <STR_LIT> : widenType = <STR_LIT> ( <STR_LIT> , numElem ) ; break ; case <STR_LIT> : widenType = <STR_LIT> ( <STR_LIT> , numElem ) ; break ; default : llvm_unreachable ( <STR_LIT>


<s> void <ISA_LIT>AsmParser :: expandStoreInst ( MCInst & Inst , SMLoc IDLoc , MCStreamer & Out , const MCSubtargetInfo * STI , bool IsImmOpnd ) { <ISA_LIT>TargetStreamer & TOut = getTargetStreamer ( ) ; unsigned SrcReg = Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned BaseReg = Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( IsImmOpnd )


<s> ++ i ; assert ( i < MI . getNumOperands ( ) && <STR_LIT> ) ; } bool Done = rewriteFrameIndex ( MI , i , BaseReg , Off , TII ) ; assert ( Done && <STR_LIT> ) ; ( void )


<s> MachineOperand & Dest = Inst . getOperand ( <NUM_LIT> ) ; uint32_t Imm = Inst . getOperand ( <NUM_LIT> ) . getImm ( ) ; uint32_t Offset = Imm & <NUM_LIT> ; uint32_t BitWidth = ( Imm & <NUM_LIT> ) >> <NUM_LIT> ; ( void ) Offset ; assert ( Inst . getOpcode ( ) == <STR_LIT> && BitWidth <= <NUM_LIT> && Offset == <NUM_LIT> && <STR_LIT> ) ; if ( BitWidth < <NUM_LIT> ) { unsigned MidRegLo = MRI . createVirtualRegister ( & <STR_LIT> ) ; unsigned MidRegHi = MRI . createVirtualRegister ( & <STR_LIT> ) ; unsigned ResultReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( MBB , MII , DL , get ( <STR_LIT> ) , MidRegLo ) . addReg ( Inst . getOperand ( <NUM_LIT> ) . getReg ( ) , <NUM_LIT> , <STR_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( BitWidth ) ; BuildMI ( MBB , MII , DL , get ( <STR_LIT> ) , MidRegHi )

. addImm ( <NUM_LIT> ) . addReg ( MidRegLo ) ;


<s> bool <STR_LIT> ( SDNode * N , bool isUnary ) { if ( ! isUnary ) { for ( unsigned i = <NUM_LIT> ; i != <NUM_LIT> ; ++ i ) if ( ! isConstantOrUndef ( N -> getOperand ( i ) , i * <NUM_LIT> + <NUM_LIT> ) ) return false ; } else { for ( unsigned i = <NUM_LIT> ; i != <NUM_LIT> ; ++ i ) if ( ! isConstantOrUndef ( N -> getOperand ( i ) , i * <NUM_LIT> + <NUM_LIT> )

|| ! isConstantOrUndef ( N -> getOperand ( i + <NUM_LIT> ) , i * <NUM_LIT> + <NUM_LIT> ) ) return false ;


<s> extern __inline void __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) _mm256_zeroupper ( void ) { __builtin_ia32_vzeroupper (


<s> gcc_checking_assert ( ! ( ( TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE ( mode ) ) || ( TARGET_VSX && ALTIVEC_OR_VSX_VECTOR_MODE ( mode ) ) || ( TARGET_E500_DOUBLE && mode == DFmode ) || ( TARGET_SPE_ABI && SPE_VECTOR_MODE ( mode ) && ! SPE_CONST_OFFSET_OK ( offset ) ) ) ) ; reg = gen_rtx_REG ( mode , regno ) ; rtx_insn * insn = emit_insn ( gen_frame_store ( reg , frame_reg , offset ) ) ; return rs6000_frame_related ( insn , frame_reg , frame_reg_to_sp


<s> SDValue <ISA_LIT>TargetLowering :: LowerBITCAST ( SDValue Op , SelectionDAG & DAG ) const { MVT ResTy = ty ( Op ) ; SDValue InpV = Op . getOperand ( <NUM_LIT> ) ; MVT InpTy = ty ( InpV ) ; assert ( ResTy . getSizeInBits ( ) == InpTy . getSizeInBits ( ) ) ; const SDLoc & dl ( Op ) ; if ( ResTy == <STR_LIT> ) { SDValue Sc = DAG . getBitcast (


<s> SDLoc DL ( Op ) ; if ( ! Subtarget -> getTargetTriple ( ) . isOSEmscripten ( ) ) { fail ( DL , DAG , <STR_LIT> <STR_LIT> ) ; return SDValue ( ) ; } if ( verifyReturnAddressArgumentIsConstant ( Op , DAG ) ) return SDValue ( ) ; unsigned Depth = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; return makeLibCall ( DAG , RTLIB :: RETURN_ADDRESS , Op . getValueType ( ) , { DAG . getConstant

( Depth , DL , <STR_LIT> ) } , false , DL ) . first ;


<s> uint32_t C = isC ? cast < ConstantSDNode > ( Size ) -> getZExtValue ( ) : ~ <NUM_LIT> ; if ( C <= <NUM_LIT> && ( ( C & <NUM_LIT> ) == <NUM_LIT> ) ) return CurDAG -> SelectNodeTo ( N , <STR_LIT> , VT , <STR_LIT> , SP , CurDAG -> getTargetConstant ( C / <NUM_LIT> , <STR_LIT> ) , Chain ) ; if ( Subtarget -> isThumb1Only ( ) ) { return CurDAG -> SelectNodeTo ( N , <STR_LIT> , VT , <STR_LIT> , SP , Size , Chain ) ; } else if ( Subtarget -> isThumb2 ( ) ) { if ( isC && Predicate_t2_so_imm ( Size . getNode ( ) ) ) { SDValue Ops [ ] = { SP , CurDAG -> getTargetConstant ( C , <STR_LIT> ) , Chain } ; return CurDAG -> SelectNodeTo ( N , <STR_LIT> , VT , <STR_LIT> , Ops , <NUM_LIT> ) ; } else if ( isC && Predicate_imm0_4095 ( Size . getNode ( ) ) ) { SDValue Ops [ ] = { SP , CurDAG -> getTargetConstant ( C , <STR_LIT> ) , Chain } ; return CurDAG -> SelectNodeTo ( N , <STR_LIT> , VT , <STR_LIT> , Ops , <NUM_LIT> ) ; } else { SDValue Ops [ ] = { SP , Size , getI32Imm ( <STR_LIT> ( <STR_LIT> ,


<s> for ( uint64_t i = <NUM_LIT> ; i != NumNops ;


<s> if ( T . getArch ( ) == Triple :: ppc64le || T . getArch ( ) == Triple :: ppcle ) Ret = <STR_LIT> ; else Ret = <STR_LIT> ; Ret += DataLayout :: getManglingComponent ( T ) ; if ( ! is64Bit || T . getOS ( ) == Triple :: Lv2 ) Ret += <STR_LIT> ; Ret += <STR_LIT> ; if ( is64Bit ) Ret += <STR_LIT> ; else Ret += <STR_LIT> ; if ( ( T . getArch ( ) == Triple :: ppc64le || T . getArch ( ) == Triple :: ppc64 ) && ( T . isOSAIX ( ) || T . isOSLinux ( ) )


<s> SDValue <ISA_LIT>TargetLowering :: getTargetNode ( ConstantPoolSDNode * N , EVT Ty , SelectionDAG & DAG , unsigned Flag


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; unsigned RegNo = getRegPair ( ) ; Inst . addOperand ( MCOperand :: CreateReg


<s> struct unw_reg_info * r ; if ( ! desc_is_active ( qp , t , sr ) ) return ; if ( x ) where = UNW_WHERE_BR ; else if ( ytreg & <NUM_LIT> ) where = UNW_WHERE_FR ; r = sr -> curr . reg + decode_abreg


<s> const bool MinSize = ST . hasMinSize ( ) ; const bool HasDivide = ST . isThumb ( ) ? ST . hasDivideInThumbMode ( ) : ST . hasDivideIn<ISA_LIT>Mode ( ) ; if ( N -> getOperand ( <NUM_LIT> ) . getValueType ( ) . isVector ( ) ) return


<s> bool <ISA_LIT>TargetLowering :: isFNegFree ( EVT VT ) const { assert ( VT . isFloatingPoint


<s> return isInt < <NUM_LIT> > ( CN -> getSExtValue


<s> assert ( ! BytesRemoved && <STR_LIT> ) ; MachineBasicBlock :: reverse_iterator I = MBB . rbegin ( ) , REnd = MBB . rend ( ) ; unsigned removed = <NUM_LIT> ; while ( I != REnd && removed < <NUM_LIT> ) { if ( I -> isDebugInstr ( ) ) { ++ I ; continue ; } if ( ! getAnalyzableBrOpc ( I -> getOpcode ( ) ) ) break ; I -> eraseFromParent ( ) ; I = MBB . rbegin ( ) ; ++


<s> SDNode * N = I ++ ; if ( OptLevel != CodeGenOpt :: None && ( N -> getOpcode ( ) == <STR_LIT> || ( N -> getOpcode ( ) == <STR_LIT> && ( Subtarget -> is64Bit ( ) || getTargetMachine ( ) . getRelocationModel ( ) != Reloc :: PIC_ ) ) ) ) { bool HasCallSeq = N -> getOpcode ( ) == <STR_LIT> ; SDValue Chain = N -> getOperand ( <NUM_LIT> ) ; SDValue Load = N -> getOperand ( <NUM_LIT> ) ; if ( ! isCalleeLoad ( Load , Chain , HasCallSeq ) ) continue ; MoveBelowOrigChain ( CurDAG , Load , SDValue ( N , <NUM_LIT> ) , Chain ) ; ++ NumLoadMoved ; continue ; } if ( N -> getOpcode ( ) != <STR_LIT> && N -> getOpcode ( ) != <STR_LIT> ) continue ; EVT SrcVT = N -> getOperand ( <NUM_LIT> ) . getValueType ( ) ; EVT DstVT = N -> getValueType ( <NUM_LIT> ) ; if ( SrcVT . isVector ( ) || DstVT . isVector ( ) ) continue ; bool SrcIsSSE = <ISA_LIT>Lowering . isScalarFPTypeInSSEReg ( SrcVT ) ; bool DstIsSSE = <ISA_LIT>Lowering . isScalarFPTypeInSSEReg ( DstVT ) ; if ( SrcIsSSE && DstIsSSE ) continue ; if ( ! SrcIsSSE && ! DstIsSSE ) { if ( N -> getOpcode ( ) == <STR_LIT> ) continue ; if ( N -> getConstantOperandVal ( <NUM_LIT> ) ) continue ; } EVT MemVT ; if ( N -> getOpcode ( ) == <STR_LIT> ) MemVT = DstVT ; else MemVT = SrcIsSSE ? SrcVT : DstVT ; SDValue MemTmp = CurDAG -> CreateStackTemporary ( MemVT ) ; DebugLoc dl = N -> getDebugLoc ( ) ; SDValue Store = CurDAG -> getTruncStore ( CurDAG -> getEntryNode ( ) , dl , N -> getOperand ( <NUM_LIT> ) , MemTmp , MachinePointerInfo ( ) , MemVT , false , false , <NUM_LIT> ) ; SDValue Result = CurDAG -> getExtLoad ( <STR_LIT> , dl , DstVT , Store , MemTmp , MachinePointerInfo ( ) , MemVT , false , false , <NUM_LIT> ) ; --


<s> DebugLoc dl ; const <ISA_LIT>InstrInfo & TII = * static_cast < const <ISA_LIT>InstrInfo * > ( MF . getSubtarget ( ) . getInstrInfo ( ) ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ; if ( hasBP ( MF ) ) BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT>


<s> SmallVector < CCValAssign , <NUM_LIT> > ArgLocs ; CCState CCInfo ( CallConv , isVarArg , DAG . getMachineFunction ( ) , getTargetMachine ( ) , ArgLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeFormalArguments ( Ins , CC_<ISA_LIT> ) ; assert ( ! isVarArg && <STR_LIT> ) ; for ( unsigned i = <NUM_LIT> , e = ArgLocs . size ( ) ; i != e ; ++ i ) { CCValAssign & VA = ArgLocs [ i ] ; if ( VA . isRegLoc ( ) ) { EVT RegVT = VA . getLocVT ( ) ; switch ( RegVT . getSimpleVT ( ) . SimpleTy ) { default : { errs ( ) << <STR_LIT> << RegVT . getSimpleVT ( ) . SimpleTy << <STR_LIT> ; llvm_unreachable ( <NUM_LIT> ) ; } case <STR_LIT> : unsigned VReg = RegInfo . createVirtualRegister ( <STR_LIT> ) ; RegInfo . addLiveIn ( VA . getLocReg ( ) , VReg ) ; SDValue ArgValue = DAG . getCopyFromReg ( Chain , dl , VReg , RegVT ) ; if ( VA . getLocInfo ( ) == CCValAssign :: SExt ) ArgValue = DAG . getNode ( <STR_LIT> , dl , RegVT , ArgValue , DAG . getValueType ( VA . getValVT ( ) ) ) ; else if ( VA . getLocInfo ( ) == CCValAssign :: ZExt ) ArgValue = DAG . getNode ( <STR_LIT> , dl , RegVT , ArgValue , DAG . getValueType ( VA . getValVT ( ) ) ) ; if ( VA . getLocInfo ( ) != CCValAssign :: Full ) ArgValue = DAG . getNode ( <STR_LIT> , dl , VA . getValVT ( ) , ArgValue ) ; InVals . push_back ( ArgValue ) ; } } else { assert ( VA . isMemLoc ( ) ) ; unsigned ObjSize = VA . getLocVT ( ) . getSizeInBits ( ) / <NUM_LIT> ; if ( ObjSize > <NUM_LIT> ) { errs ( ) << <STR_LIT> << EVT ( VA . getLocVT ( ) ) . getEVTString ( )


<s> int n_const = <NUM_LIT> ; int i ; if ( GET_CODE ( vals ) == CONST_VECTOR ) const_vec = vals ; else if ( GET_CODE ( vals ) == PARALLEL ) { for ( i = <NUM_LIT> ; i < n_elts ; ++ i ) { rtx x = XVECEXP ( vals , <NUM_LIT> , i ) ; if ( CONST_INT_P ( x ) || CONST_DOUBLE_P ( x ) ) n_const ++ ; } if ( n_const == n_elts ) const_vec = gen_rtx_CONST_VECTOR ( mode , XVEC ( vals , <NUM_LIT> ) ) ; } else gcc_unreachable ( ) ; if ( const_vec != NULL && simd_immediate_valid_for_move ( const_vec , mode , NULL , NULL ) ) return const_vec ; else if ( TARGET_HAVE_MVE && VALID_MVE_PRED_MODE ( mode ) ) return mve_bool_vec_to_const ( const_vec ) ; else if ( ( target = neon_vdup_constant ( vals

, generate ) ) != NULL_RTX ) return target ;


) _mm512_setzero_hi ( ) , ( __mmask32 ) - <NUM_LIT> ) ;


<s> else llvm_unreachable ( <STR_LIT> ) ; I . setDesc ( TII . get ( NewOpc ) ) ; MachineInstrBuilder MIB ( MF , I ) ; if ( Opc == TargetOpcode :: G_FRAME_INDEX ) { addOffset ( MIB , <NUM_LIT> ) ; } else { MachineOperand & InxOp = I . getOperand ( <NUM_LIT> ) ; I . addOperand ( InxOp ) ; InxOp . ChangeToImmediate ( <NUM_LIT> ) ; MIB . addImm ( <NUM_LIT> ) . addReg (


<s> for ( NodeAddr < InstrNode * > IA : BA . Addr -> members ( DFG ) ) { if ( DFG . IsCode < NodeAttrs :: Stmt > ( IA ) ) { NodeAddr < StmtNode * > SA = IA ; EqualityMap EM ; if ( interpretAsCopy ( SA . Addr -> getCode ( ) , EM ) ) recordCopy ( SA , EM ) ; } updateMap ( IA ) ; DFG . pushDefs ( IA , DefM ) ; } MachineDomTreeNode * N = MDT . getNode ( B


<s> void ELF<ISA_LIT>AsmBackend :: processFixupValue ( const MCAssembler & Asm , const MCAsmLayout & Layout , const MCFixup & Fixup , const MCFragment * DF , const MCValue & Target , uint64_t


<s> RefFlags |= <ISA_LIT>MCExpr :: VK_TPREL ; break ; case TLSModel :: LocalDynamic : RefFlags |= <ISA_LIT>MCExpr :: VK_DTPREL ; break ; case TLSModel :: GeneralDynamic : RefFlags |= <ISA_LIT>MCExpr :: VK_TLSDESC ; break ; } } else if ( PlatformFlag == <STR_LIT> ) { RefFlags |= <ISA_LIT>MCExpr :: VK_SEC ; } else { RefFlags |= <ISA_LIT>MCExpr :: VK_ABS ; } if ( FragmentFlag == <STR_LIT> ) RefFlags |= <ISA_LIT>MCExpr :: VK_PAGE ; else if ( FragmentFlag == <STR_LIT> ) RefFlags |= <ISA_LIT>MCExpr :: VK_PAGEOFF ; else if ( FragmentFlag == <STR_LIT> ) RefFlags |= <ISA_LIT>MCExpr :: VK_G3 ; else if ( FragmentFlag == <STR_LIT> ) RefFlags |= <ISA_LIT>MCExpr :: VK_G2 ; else if ( FragmentFlag == <STR_LIT> ) RefFlags |= <ISA_LIT>MCExpr :: VK_G1 ; else if ( FragmentFlag == <STR_LIT> ) RefFlags |= <ISA_LIT>MCExpr :: VK_G0 ; else if ( FragmentFlag == <STR_LIT> ) RefFlags |= <ISA_LIT>MCExpr :: VK_HI12 ; if ( MO . getTargetFlags ( ) & <STR_LIT> ) RefFlags |= <ISA_LIT>MCExpr :: VK_NC ; const MCExpr * Expr = MCSymbolRefExpr :: create ( Sym , MCSymbolRefExpr :: VK_None , Ctx ) ; if ( ! MO . isJTI ( ) && MO . getOffset ( ) ) Expr = MCBinaryExpr :: createAdd ( Expr , MCConstantExpr :: create ( MO . getOffset ( ) , Ctx ) , Ctx ) ; if ( PlatformFlag


<s> MachineInstr * AndN2 = BuildMI ( MBB , & MI , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addOperand ( MI . getOperand ( <NUM_LIT> ) ) ; MachineInstr * Branch = BuildMI ( MBB , & MI , DL , TII -> get ( <STR_LIT> ) ) . addOperand ( MI . getOperand ( <NUM_LIT> ) ) ; if ( LIS ) { LIS -> ReplaceMachineInstrInMaps ( MI , * AndN2 ) ; LIS -> InsertMachineInstrInMaps ( *


<s> bool <ISA_LIT>AsmParser :: validateOpSel ( const MCInst & Inst ) { const unsigned Opc = Inst . getOpcode ( ) ; if ( Opc == <STR_LIT> || Opc == <STR_LIT> ) { int OpSelIdx = <STR_LIT> ( Opc , <STR_LIT> :: op_sel ) ; unsigned OpSel = Inst . getOperand ( OpSelIdx ) . getImm ( ) ; if ( OpSel & ~ <NUM_LIT> ) return false ; } if ( isGFX940 ( ) && ( MII . get ( Opc ) . TSFlags & <STR_LIT> ) ) { int OpSelIdx = <STR_LIT> ( Opc , <STR_LIT> :: op_sel ) ; if ( OpSelIdx != - <NUM_LIT> ) { if ( Inst . getOperand ( OpSelIdx ) . getImm ( ) != <NUM_LIT> ) return false ; } int OpSelHiIdx = <STR_LIT> ( Opc


<s> void <ISA_LIT>InstPrinter :: printInstSyncBOption ( const MCInst * MI , unsigned OpNum ,

const MCSubtargetInfo & STI , raw_ostream & O ) {


<s> static void alpha_align_insns ( void ) { if ( alpha_tune == PROCESSOR_EV4 ) alpha_align_insns_1 ( <NUM_LIT> , alphaev4_next_group , alphaev4_next_nop ) ; else if ( alpha_tune == PROCESSOR_EV5 ) alpha_align_insns_1 ( <NUM_LIT> , alphaev5_next_group ,


<s> return mips_split_move_p ( dest , src ,


<s> <ISA_LIT>AS get<ISA_LIT>AS ( ) const { return


<s> unsigned Depth = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; SDValue FrameAddr = DAG . getCopyFromReg ( DAG . getEntryNode ( ) , DL , <STR_LIT> , <STR_LIT> ) ; while ( Depth -- ) FrameAddr = DAG . getLoad ( VT , DL , DAG . getEntryNode ( ) , FrameAddr , MachinePointerInfo ( ) ) ; if ( Subtarget -> isTargetILP32 ( ) ) FrameAddr = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , FrameAddr , DAG . getValueType (


<s> return ( __m256 ) __builtin_ia32_fixupimmps256_maskz ( ( __v8sf ) __A , ( __v8sf ) __B , (


<s> void <ISA_LIT>TargetLowering :: getOpndList ( SmallVectorImpl < SDValue > & Ops , std :: deque < std :: pair < unsigned , SDValue > > & RegsToPass , bool IsPICCall , bool GlobalOrExternal , bool InternalLinkage , CallLoweringInfo & CLI , SDValue Callee , SDValue Chain ) const { if ( IsPICCall && ! InternalLinkage ) { unsigned GPReg = IsN64 ? <STR_LIT> : <STR_LIT> ; EVT Ty = IsN64 ? <STR_LIT> : <STR_LIT> ; RegsToPass . push_back ( std :: make_pair ( GPReg , getGlobalReg ( CLI . DAG , Ty ) ) ) ; } SDValue InFlag ; for ( unsigned i = <NUM_LIT> , e = RegsToPass . size ( ) ; i != e ; ++ i ) { Chain = CLI . DAG . getCopyToReg ( Chain , CLI . DL , RegsToPass [ i ] .

first , RegsToPass [ i ] . second , InFlag ) ;


<s> void eatThatToken ( OperandVector & Operands ) { Operands . push_back ( <STR_LIT> ( getLexer ( ) . getTok ( ) . getString ( ) ,


<s> if ( MO . isGlobal ( ) ) return isGVStub ( MO . getGlobal ( ) , TM ) ; if ( MO . isFI ( ) ) { const MachineFrameInfo & MFI = * MI -> getParent ( ) -> getParent ( ) -> getFrameInfo ( ) ; int Idx = MO . getIndex ( ) ; return MFI . isFixedObjectIndex ( Idx ) && MFI . isImmutableObjectIndex ( Idx ) ; } } return


<s> MVT VT = A . getSimpleValueType ( ) ; return DAG -> getNode ( <STR_LIT> , dl , VT , A ,


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . addRequired < ProfileSummaryInfoWrapperPass > ( ) ; AU . addRequired < LazyMachineBlockFrequencyInfoPass > ( ) ; AU . addPreserved < LazyMachineBlockFrequencyInfoPass


<s> <STR_LIT> From = getSimpleType ( V -> getType ( ) ) ; <STR_LIT> To = getLegalType ( From ) ; Register VReg = getRegForValue ( V )


<s> if ( ! isa < ConstantSDNode > ( Idx ) ) return SDValue ( ) ; SDValue ExtractedFromVec = I -> getOperand ( <NUM_LIT> ) ; DenseMap < SDValue , unsigned > :: iterator M = VecInMap . find ( ExtractedFromVec ) ; if ( M == VecInMap . end ( ) ) { VT = ExtractedFromVec . getValueType ( ) ; if ( ! VT . is128BitVector ( ) && ! VT . is256BitVector ( ) ) return SDValue ( ) ; if ( VecInMap . begin ( ) != VecInMap . end ( ) && VT != VecInMap . begin ( ) -> first . getValueType ( ) ) return SDValue ( ) ; M = VecInMap . insert ( std :: make_pair ( ExtractedFromVec , <NUM_LIT> ) ) . first ; VecIns . push_back ( ExtractedFromVec ) ; } M -> second |= <NUM_LIT> << cast < ConstantSDNode > ( Idx ) -> getZExtValue ( ) ; } assert ( ( VT . is128BitVector ( ) || VT . is256BitVector ( ) ) && <STR_LIT> ) ; unsigned FullMask = ( <NUM_LIT> << VT . getVectorNumElements ( ) ) - <NUM_LIT> ; for ( DenseMap < SDValue , unsigned > :: const_iterator I = VecInMap . begin ( ) , E = VecInMap . end ( ) ; I != E ; ++ I ) { if ( I -> second != FullMask ) return SDValue ( ) ; } EVT TestVT = VT . is128BitVector ( ) ? <STR_LIT> : <STR_LIT> ; for ( unsigned i = <NUM_LIT> , e = VecIns . size ( ) ; i < e ; ++ i ) VecIns [ i ] = DAG . getBitcast ( TestVT , VecIns [ i ] ) ; for ( unsigned Slot = <NUM_LIT> , e = VecIns . size ( ) ; e - Slot > <NUM_LIT> ; Slot += <NUM_LIT> , e += <NUM_LIT> ) { SDValue LHS = VecIns [ Slot ] ; SDValue RHS = VecIns [ Slot + <NUM_LIT> ] ; VecIns . push_back ( DAG . getNode ( <STR_LIT> ,


<s> bool ImpIsDead = MI . getOperand ( <NUM_LIT> ) . isDead ( ) ; buildMI ( MBB , MBBI , <STR_LIT> ) . addReg ( DstReg , RegState :: Define | getDeadRegState ( DstIsDead ) ) . addReg ( DstReg , RegState :: Kill ) -> getOperand ( <NUM_LIT> ) . setIsUndef ( true ) ; buildMI ( MBB , MBBI , <STR_LIT> ) . addReg ( DstReg , RegState :: Define | getDeadRegState ( DstIsDead ) ) . addReg ( DstReg , RegState :: Kill ) . addReg ( DstReg , RegState :: Kill ) ; auto MIRRC = buildMI ( MBB , MBBI , <STR_LIT> ) . addReg ( DstReg , RegState :: Define | getDeadRegState ( DstIsDead ) ) . addReg ( DstReg , getKillRegState ( DstIsKill ) ) ; if ( ImpIsDead ) MIRRC -> getOperand ( <NUM_LIT> ) . setIsDead ( ) ; MIRRC -> getOperand ( <NUM_LIT> ) . setIsKill ( ) ; MI . eraseFromParent (


<s> if ( MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> ) { if ( MI -> getOperand ( <NUM_LIT> ) . isFI ( ) && MI -> getOperand ( <NUM_LIT> ) . isImm ( ) && MI -> getOperand ( <NUM_LIT> ) . getImm ( )


<s> SDValue False = N -> getOperand ( <NUM_LIT> ) ; if ( LHS . getOperand ( <NUM_LIT> ) . getNode ( ) != True . getNode ( ) || LHS . getOperand ( <NUM_LIT> ) . getNode ( ) != False . getNode ( ) || RHS . getNode ( ) != False . getNode ( ) || cast < CondCodeSDNode > ( N -> getOperand ( <NUM_LIT> ) ) -> get ( ) != <STR_LIT> ) { return SDValue ( ) ; } <STR_LIT> CCOpcode = cast < CondCodeSDNode > ( LHS -> getOperand ( <NUM_LIT> ) ) -> get ( ) ; CCOpcode = <STR_LIT> ( CCOpcode , LHS . getOperand ( <NUM_LIT> ) . getValueType ( ) . isInteger ( ) ) ; return DAG . getSelectCC ( N -> getDebugLoc ( ) , LHS . getOperand ( <NUM_LIT> ) , LHS . getOperand ( <NUM_LIT> ) , LHS . getOperand ( <NUM_LIT> ) , LHS . getOperand ( <NUM_LIT> ) , CCOpcode ) ; } case <STR_LIT> : { SDValue Arg = N -> getOperand ( <NUM_LIT> ) ; if ( Arg . getOpcode ( ) != <STR_LIT> ) break ; SDValue NewBldVec [ <NUM_LIT> ] = { DAG . getUNDEF ( <STR_LIT> ) , DAG . getUNDEF ( <STR_LIT> ) , DAG . getUNDEF ( <STR_LIT> ) , DAG . getUNDEF ( <STR_LIT> ) } ; SDValue NewArgs [ <NUM_LIT> ] = { N -> getOperand ( <NUM_LIT> ) , SDValue ( ) , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) } ; for ( unsigned i = <NUM_LIT> ; i < Arg . getNumOperands ( ) ; i ++ ) { if ( ConstantFPSDNode * C = dyn_cast < ConstantFPSDNode > ( Arg . getOperand ( i ) ) ) { if ( C -> isZero ( ) ) { NewArgs [ <NUM_LIT> + i ] = DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ; } else if ( C -> isExactlyValue ( <NUM_LIT> ) ) { NewArgs [ <NUM_LIT> + i ] = DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ; } else { NewBldVec [ i ] = Arg . getOperand ( i ) ; } } else { NewBldVec [ i ] = Arg . getOperand ( i ) ; } } DebugLoc DL = N -> getDebugLoc ( ) ; NewArgs [ <NUM_LIT> ] = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , NewBldVec , <NUM_LIT> ) ; return DAG . getNode ( <STR_LIT> , DL , N -> getVTList ( ) , NewArgs , <NUM_LIT> ) ; } } return SDValue (


<s> for ( unsigned i = <NUM_LIT> , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) { const MachineOperand & MO = MI -> getOperand ( i ) ; if ( ! MO . isReg ( ) || ! MO . isDef ( ) ) continue ; unsigned Reg = MO . getReg ( ) ; MachineRegisterInfo :: use_iterator nextI ; for ( MachineRegisterInfo :: use_iterator I = MRI -> use_begin ( Reg ) , E = MRI -> use_end ( ) ; I != E ; I = nextI ) { nextI = std :: next ( I ) ; MachineOperand & Use = * I ; MachineInstr * UseMI = I -> getParent (


<s> switch ( Kind ) { case Immediate : OS << * getImm ( ) ; break ; case Register : OS << <STR_LIT> << getReg ( ) << <STR_LIT> ; break ; case Token


<s> Value * <ISA_LIT>IREmitter :: visitCMPFPw0 ( const SDNode * N ) { llvm_unreachable ( <STR_LIT> )


<s> void <ISA_LIT>TargetStreamer :: emitMovSP ( unsigned Reg , int64_t Offset ) { llvm_unreachable ( <STR_LIT>


<s> SDValue Chain = Op . getOperand ( <NUM_LIT> ) ; <STR_LIT> CC = cast < CondCodeSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> get ( ) ; SDValue LHS = Op . getOperand ( <NUM_LIT> ) ; SDValue RHS = Op . getOperand ( <NUM_LIT> ) ; SDValue Dest = Op . getOperand ( <NUM_LIT> ) ; SDLoc DL ( Op ) ; if ( ! getHasJmpExt ( ) ) NegateCC ( LHS , RHS , CC ) ; return DAG . getNode ( <STR_LIT> , DL , Op . getValueType ( ) , Chain , LHS , RHS , DAG . getConstant ( CC , DL , <STR_LIT>


<s> bool <ISA_LIT>TargetLowering :: shouldExpandAtomicCmpXchgInIR ( AtomicCmpXchgInst * AI ) const { return


<s> return DAG . getNode ( <STR_LIT> , SL , VT , NewVec ) ; } if ( convertBuildVectorCastElt ( DAG , Hi , Lo ) ) { SDValue NewVec = DAG . getBuildVector ( <STR_LIT> , SL , { Hi , Lo } ) ; return DAG . getNode ( <STR_LIT> , SL ,


<s> if ( Addr . getOpcode ( ) == <STR_LIT> || Addr . getOpcode ( ) == <STR_LIT> ) return false ; if ( Addr . getOpcode ( ) == <STR_LIT> ) { if ( ConstantSDNode * CN = dyn_cast < ConstantSDNode > ( Addr . getOperand ( <NUM_LIT> ) ) ) if ( isInt < <NUM_LIT> > ( CN -> getSExtValue ( ) ) ) return false ; if ( Addr . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> || Addr . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) return false ; R1 = Addr . getOperand ( <NUM_LIT> ) ; R2 = Addr . getOperand ( <NUM_LIT> ) ; return true ; } R1 = Addr ; R2 = CurDAG -> getRegister ( <STR_LIT> , <STR_LIT>


<s> Triple TheTriple ( TT ) ; if ( TheTriple . isOSDarwin ( ) || TheTriple . getEnvironment ( ) == Triple :: MachO )

return createMachOStreamer ( Ctx , MAB , _OS , _Emitter , RelaxAll ) ;


<s> if ( NaClDontBreakABI ) { PointerSize = ( is64Bit && ! isX32 ) ? <NUM_LIT> : <NUM_LIT> ; } CalleeSaveStackSlotSize = is64Bit ? <NUM_LIT> : <NUM_LIT> ; AssemblerDialect = AsmWriterFlavor ; TextAlignFillValue = <NUM_LIT> ; SupportsDebugInformation = true ; ExceptionsType = ExceptionHandling :: DwarfCFI ; UseIntegratedAssembler = true


<s> explicit <ISA_LIT>DAGToDAGISel ( <ISA_LIT>TargetMachine & tm ) : SelectionDAGISel ( tm ) , TM ( tm ) , Subtarget ( tm .

getSubtarget < <ISA_LIT>Subtarget > ( ) ) {


<s> if ( skipFunction ( F ) ) return false ; bool Changed = false ; for ( auto & BB : F ) for ( auto & I : BB ) { if ( auto allocaInst = dyn_cast < AllocaInst > ( & I ) ) { Changed = true ; auto ETy = allocaInst -> getAllocatedType ( ) ; auto LocalAddrTy = PointerType :: get ( ETy , ADDRESS_SPACE_LOCAL ) ; auto NewASCToLocal = new AddrSpaceCastInst ( allocaInst , LocalAddrTy , <STR_LIT> ) ; auto GenericAddrTy = PointerType :: get ( ETy , ADDRESS_SPACE_GENERIC ) ; auto NewASCToGeneric = new AddrSpaceCastInst ( NewASCToLocal , GenericAddrTy , <STR_LIT> ) ; NewASCToLocal -> insertAfter ( allocaInst ) ; NewASCToGeneric -> insertAfter ( NewASCToLocal ) ; for ( Value :: use_iterator UI = allocaInst -> use_begin ( ) , UE = allocaInst -> use_end ( ) ; UI != UE ; ) { const auto & AllocaUse = * UI ++ ; auto LI = dyn_cast < LoadInst > ( AllocaUse . getUser ( ) ) ; if ( LI && LI -> getPointerOperand ( ) == allocaInst && ! LI -> isVolatile ( ) ) { LI -> setOperand ( LI -> getPointerOperandIndex ( ) , NewASCToGeneric ) ; continue ; } auto SI = dyn_cast < StoreInst > ( AllocaUse . getUser ( ) ) ; if ( SI && SI -> getPointerOperand ( ) == allocaInst && ! SI -> isVolatile ( ) ) { SI -> setOperand ( SI -> getPointerOperandIndex ( ) , NewASCToGeneric ) ; continue ; } auto GI = dyn_cast < GetElementPtrInst > ( AllocaUse . getUser ( ) ) ; if ( GI && GI -> getPointerOperand ( ) == allocaInst ) { GI -> setOperand ( GI -> getPointerOperandIndex ( ) , NewASCToGeneric ) ; continue ; } auto BI = dyn_cast < BitCastInst > ( AllocaUse . getUser ( ) ) ; if ( BI && BI -> getOperand ( <NUM_LIT> ) == allocaInst


<s> assert ( Desc . getNumOperands ( ) == <NUM_LIT> && <STR_LIT> ) ; Register DstReg = MBBI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; bool DstIsDead = MBBI -> getOperand ( <NUM_LIT> ) . isDead ( ) ; BuildMI ( MBB , MBBI , DL , Desc ) . addReg ( DstReg , RegState :: Define | getDeadRegState ( DstIsDead

) ) . add ( MBBI -> getOperand ( <NUM_LIT> ) ) . add ( MBBI -> getOperand ( <NUM_LIT> ) ) ;


<s> return getSubtargetImpl ( ) -> getFrameLowering


<s> Register Reg = MIB . getReg ( <NUM_LIT> ) ; BuildMI ( MBB , MIB . getInstr ( ) , DL , TII . get ( <STR_LIT> ) , Reg ) . addReg ( Reg , RegState :: Undef ) . addReg ( Reg , RegState :: Undef ) ; MIB -> setDesc ( TII . get ( MinusOne ? <STR_LIT> : <STR_LIT> ) ) ; MIB . addReg ( Reg


<s> auto AddrTy = Addr -> getValueType ( <NUM_LIT> ) ; if ( FrameIndexSDNode * FIN = dyn_cast < FrameIndexSDNode > ( Addr ) ) { Base = CurDAG -> getTargetFrameIndex ( FIN -> getIndex ( ) , AddrTy ) ; Offset = CurDAG -> getTargetConstant ( <NUM_LIT> , SDLoc ( Addr ) , <STR_LIT> ) ; return true ; } if ( Addr . getOpcode ( ) == <STR_LIT> || Addr . getOpcode ( ) == <STR_LIT> || Addr . getOpcode ( ) == <STR_LIT> ) return false ; if ( CurDAG -> isBaseWithConstantOffset ( Addr ) ) { ConstantSDNode * CN = cast < ConstantSDNode > ( Addr . getOperand ( <NUM_LIT> ) ) ; if ( isInt < <NUM_LIT> > ( CN -> getSExtValue ( ) ) ) { if ( FrameIndexSDNode * FIN = dyn_cast < FrameIndexSDNode > ( Addr . getOperand ( <NUM_LIT> ) ) ) { Base = CurDAG -> getTargetFrameIndex ( FIN -> getIndex ( ) , AddrTy ) ; } else { Base = Addr . getOperand ( <NUM_LIT> ) ; } Offset = CurDAG -> getTargetConstant ( CN -> getZExtValue ( ) , SDLoc ( Addr ) ,


<s> unsigned <ISA_LIT>FrameLowering :: getPSPSlotOffsetFromSP ( const MachineFunction & MF ) const { const WinEHFuncInfo & Info = * MF . getWinEHFuncInfo ( ) ; Register SPReg ; int Offset = getFrameIndexReferencePreferSP ( MF , Info . PSPSymFrameIdx , SPReg ,


<s> TargetRegistry :: RegisterMCInstrInfo ( getThe<ISA_LIT>Target ( ) , create<ISA_LIT>MCInstrInfo ) ; TargetRegistry :: RegisterMCRegInfo ( getThe<ISA_LIT>Target ( )


<s> SrcOp = DAG . getBitcast ( ShVT , SrcOp ) ; assert ( NumBits % <NUM_LIT> == <NUM_LIT> && <STR_LIT> ) ; SDValue ShiftVal = DAG . getTargetConstant ( NumBits / <NUM_LIT> , dl , <STR_LIT> ) ; return DAG . getBitcast ( VT , DAG . getNode ( Opc , dl , ShVT , SrcOp


<s> split_const ( x , & base , & offset ) ; if ( riscv_symbolic_constant_p ( base , & type ) ) { if ( SMALL_OPERAND ( INTVAL ( offset ) ) && riscv_symbol_insns ( type ) > <NUM_LIT> ) return true ; if ( flag_pic ) return true ; } if ( tls_referenced_p ( x


<s> if ( RegWidth == <NUM_LIT> && Shift > <NUM_LIT> ) return MCDisassembler :: Fail ; Inst . addOperand ( MCOperand ::


<s> if ( Op . isDef ( ) ) return true ; MachineInstr & MI = * Op . getParent ( ) ; if ( MI . getOpcode ( ) == AMDGPU :: EXP ) return true ; if ( ! MI . getDesc ( ) . mayStore ( ) ) return false ; if ( TII -> isDS ( MI . getOpcode ( ) ) ) { MachineOperand * Data = TII -> getNamedOperand ( MI , AMDGPU :: OpName :: data ) ; if ( Data && Op . isIdenticalTo ( * Data ) ) return true ; MachineOperand * Data0 = TII -> getNamedOperand ( MI , AMDGPU :: OpName :: data0 ) ; if ( Data0 && Op . isIdenticalTo ( * Data0 ) ) return true ; MachineOperand * Data1 = TII -> getNamedOperand ( MI , AMDGPU :: OpName


<s> const TargetInstrInfo * TII = Subtarget -> getInstrInfo ( ) ; BuildMI ( * BB , MI , dl , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) ; BuildMI ( * BB , MI , dl , TII -> get ( <STR_LIT> ) ) ; BuildMI ( * BB , MI , dl , TII -> get ( TargetOpcode :: COPY ) , MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( <STR_LIT> ) ; MI -> eraseFromParent


<s> LocVT = <STR_LIT> ; LocInfo = CCValAssign :: BCvt ; } else if ( LocVT == <STR_LIT> || LocVT == <STR_LIT> || LocVT == <STR_LIT> || LocVT == <STR_LIT> || LocVT == <STR_LIT> ) { LocVT = <STR_LIT> ; ValVT = <STR_LIT> ; LocInfo = CCValAssign :: Full ; } else if ( LocVT == <STR_LIT> || LocVT == <STR_LIT> || LocVT == <STR_LIT> || LocVT == <STR_LIT> || ( LocVT == <STR_LIT> && UseHVX && UseHVXDbl ) ) { LocVT = <STR_LIT> ; ValVT = <STR_LIT> ; LocInfo = CCValAssign :: Full ; } else if ( LocVT == <STR_LIT> || LocVT == <STR_LIT> || LocVT == <STR_LIT> || LocVT == <STR_LIT> ) { LocVT = <STR_LIT> ; ValVT = <STR_LIT> ; LocInfo = CCValAssign :: Full ; } if ( LocVT == <STR_LIT> || LocVT == <STR_LIT> ) { if ( ! RetCC_<ISA_LIT>32 ( ValNo , ValVT , LocVT , LocInfo , ArgFlags , State ) ) return false ; } if ( LocVT == <STR_LIT> || LocVT == <STR_LIT> ) { if ( ! RetCC_<ISA_LIT>64 ( ValNo , ValVT , LocVT , LocInfo , ArgFlags , State ) ) return false ; } if ( LocVT == <STR_LIT> || LocVT == <STR_LIT> || LocVT == <STR_LIT> ) { if ( ! RetCC_<ISA_LIT>Vector ( ValNo , ValVT , LocVT , LocInfo


<s> CI != CE ; ++ CI ) { SPScope * CN = * CI ; RI . Priv -> unifyWithChild ( * ( RAInfos . at ( CN ) . Priv ) ) ; } } unsigned spillLocCnt = <NUM_LIT> ; for ( auto iter = df_begin ( rootScope ) , end = df_end ( rootScope ) ; iter != end ; ++ iter ) { auto scope = * iter ; RAInfo & RI = RAInfos . at ( scope ) ; if ( ! scope -> isTopLevel ( ) ) { RI . Priv -> unifyWithParent ( * ( RAInfos . at ( scope -> getParent ( ) ) . Priv ) , spillLocCnt , scope -> isTopLevel ( ) ) ; if ( ! RI . needsScopeSpill ( ) ) NoSpillScopes ++ ; } spillLocCnt += RI . neededSpillLocs ( ) ; DEBUG ( RI . dump (


<s> MBB -> insert ( MI , Ear1MI ) ; Ear1MI -> setDesc ( get ( <STR_LIT> ) ) ; MachineInstrBuilder ( MF , Ear1MI ) . addReg ( <STR_LIT> ) ; MachineInstr * SllgMI = MF . CloneMachineInstr ( MI ) ; MBB -> insert ( MI , SllgMI ) ; SllgMI -> setDesc ( get ( <STR_LIT> ) ) ; MachineInstrBuilder ( MF , SllgMI ) . addReg ( Reg ) . addReg ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; MachineInstr * Ear2MI = MF .


<s> reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; const GCNSubtarget & ST = MF . getSubtarget < GCNSubtarget > ( ) ; unsigned MaxNumSGPRs = ST . getMaxNumSGPRs ( MF ) ; unsigned TotalNumSGPRs = <STR_LIT> . getNumRegs


<s> unsigned Lg2 = SplatValue . countTrailingZeros ( ) ; SmallVector < SDValue , <NUM_LIT> > Sz ( NumElts , DAG . getConstant ( EltTy . getSizeInBits ( ) - <NUM_LIT> , EltTy ) ) ; SDValue SGN = DAG . getNode ( <STR_LIT> , dl , VT , N0 , DAG . getNode ( <STR_LIT> , dl , VT , & Sz [ <NUM_LIT> ] , NumElts ) ) ; SmallVector < SDValue , <NUM_LIT> > Amt ( NumElts , DAG . getConstant ( EltTy . getSizeInBits ( ) - Lg2 , EltTy ) ) ; SDValue SRL = DAG . getNode ( <STR_LIT> , dl , VT , SGN , DAG . getNode ( <STR_LIT> , dl , VT , & Amt [ <NUM_LIT> ] , NumElts ) ) ; SDValue ADD = DAG . getNode ( <STR_LIT> , dl , VT , N0 , SRL ) ; SmallVector < SDValue , <NUM_LIT> > Lg2Amt ( NumElts , DAG . getConstant ( Lg2 , EltTy ) ) ; SDValue SRA = DAG . getNode ( <STR_LIT> , dl , VT , ADD , DAG . getNode ( <STR_LIT> , dl , VT , & Lg2Amt [ <NUM_LIT> ] , NumElts ) ) ; if ( SplatValue . isNonNegative ( ) ) return SRA ; SmallVector < SDValue , <NUM_LIT> > V ( NumElts , DAG . getConstant ( <NUM_LIT> , EltTy ) ) ; SDValue Zero = DAG . getNode ( <STR_LIT> , dl , VT , & V [ <NUM_LIT> ] , NumElts ) ; return DAG . getNode ( <STR_LIT> , dl ,


<s> if ( GET_CODE ( op5 ) == REG ) regs ++ ; if ( regs != <NUM_LIT> ) return <NUM_LIT> ; if ( GET_CODE ( op0 ) == REG && ( ( GET_CODE ( op4 ) == MEM && reg_mentioned_p ( op0 , XEXP ( op4 , <NUM_LIT> ) ) ) || ( GET_CODE ( op5 ) == MEM && reg_mentioned_p ( op0 , XEXP ( op5 , <NUM_LIT> ) )


<s> static CodeModel :: Model getEffectiveCodeModel ( Optional < CodeModel :: Model > CM ) { if ( CM ) return


<s> const TargetInstrInfo & TII = * MF . getSubtarget ( ) . getInstrInfo ( ) ; for ( unsigned i = <NUM_LIT> , e = CSI . size ( ) ; i != e ; ++ i ) BuildMI ( MBB , MI , DL , TII . get ( <STR_LIT> ) , CSI [ i ] . getReg ( ) ) . addReg ( <STR_LIT> ) ; return true


<s> static MCAsmInfo * create<ISA_LIT>MCAsmInfo ( const MCRegisterInfo & MRI , const Triple & TT , const MCTargetOptions & Options ) { MCAsmInfo * MAI = new <ISA_LIT>MCAsmInfo ( TT ) ; MCRegister SP = MRI . getDwarfRegNum


<s> switch ( Inst . getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : Inst . setOpcode ( <STR_LIT> ) ; break ; case <STR_LIT> : case <STR_LIT> : Inst . setOpcode ( <STR_LIT> ) ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } if ( ! Check ( S , DecoderGPRRegisterClass ( Inst , Rda , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecoderGPRRegisterClass ( Inst , Rda , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecoderGPRRegisterClass ( Inst , Rm , Address , Decoder ) ) ) return MCDisassembler :: Fail ; return S ; } if ( ! Check ( S , DecodetGPREvenRegisterClass ( Inst , RdaLo , Address , Decoder ) )


<s> if ( ! match ( GetTuple , m_Intrinsic < <STR_LIT> > ( m_Value ( SetTuple ) , m_Value ( SetIndex ) , m_Value ( SetValue ) ) ) || SetValue -> getType ( ) != II . getType ( ) ) return None ; if ( GetIndex == SetIndex ) return IC . replaceInstUsesWith ( II ,


<s> if ( DestReg == <STR_LIT> ) assert ( BaseReg == <STR_LIT> && <STR_LIT> ) ; if ( ! is<ISA_LIT>LowRegister ( DestReg ) && ! MRI . isVirtualRegister ( DestReg ) ) LdReg = MF . getRegInfo ( ) . createVirtualRegister ( & <STR_LIT> ) ; if ( NumBytes <= <NUM_LIT> && NumBytes >= <NUM_LIT> && CanChangeCC ) { AddDefaultT1CC ( BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , LdReg ) ) . addImm ( NumBytes ) . setMIFlags ( MIFlags ) ; } else if ( NumBytes < <NUM_LIT> && NumBytes >= - <NUM_LIT> && CanChangeCC ) { AddDefaultT1CC ( BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , LdReg ) ) . addImm ( NumBytes )


<s> void <ISA_LIT>InstPrinter :: printUImm12Offset ( const MCInst * MI , unsigned OpNum , unsigned Scale , raw_ostream & O ) { const MCOperand MO = MI -> getOperand ( OpNum ) ; if ( MO . isImm ( ) ) { O << <STR_LIT> << formatImm ( MO . getImm ( ) * Scale ) ; } else { assert ( MO . isExpr ( ) && <STR_LIT> ) ; MO . getExpr ( ) -> print


<s> if ( ParentNode -> getValueType ( <NUM_LIT> ) . isVector ( ) ) return false ; int SrcIndices [ ] = { TII -> getOperandIdx ( Opcode , AMDGPU :: OpName :: src0 ) , TII -> getOperandIdx ( Opcode , AMDGPU :: OpName :: src1 ) , TII -> getOperandIdx ( Opcode , AMDGPU :: OpName :: src2 ) , TII -> getOperandIdx ( Opcode , AMDGPU :: OpName :: src0_X ) , TII -> getOperandIdx ( Opcode , AMDGPU :: OpName :: src0_Y ) , TII -> getOperandIdx ( Opcode , AMDGPU :: OpName :: src0_Z ) , TII -> getOperandIdx ( Opcode , AMDGPU :: OpName :: src0_W ) , TII -> getOperandIdx ( Opcode , AMDGPU :: OpName :: src1_X ) , TII -> getOperandIdx ( Opcode , AMDGPU :: OpName :: src1_Y ) , TII -> getOperandIdx ( Opcode , AMDGPU :: OpName :: src1_Z ) , TII -> getOperandIdx ( Opcode , AMDGPU :: OpName :: src1_W ) } ; std :: vector < unsigned > Consts ; for ( int OtherSrcIdx : SrcIndices ) { int OtherSelIdx = TII -> getSelIdx ( Opcode , OtherSrcIdx ) ; if ( OtherSrcIdx < <NUM_LIT> || OtherSelIdx < <NUM_LIT> ) continue ; if ( HasDst ) { OtherSrcIdx -- ; OtherSelIdx -- ; } if ( RegisterSDNode * Reg = dyn_cast < RegisterSDNode > ( ParentNode -> getOperand ( OtherSrcIdx ) ) ) { if ( Reg -> getReg ( ) == AMDGPU :: ALU_CONST ) { ConstantSDNode * Cst = cast < ConstantSDNode > ( ParentNode -> getOperand ( OtherSelIdx ) ) ; Consts . push_back ( Cst -> getZExtValue ( ) ) ; } } } ConstantSDNode * Cst = cast < ConstantSDNode > ( CstOffset ) ; Consts . push_back ( Cst -> getZExtValue ( ) ) ; if ( ! TII -> fitsConstReadLimitations ( Consts ) ) { return false ; } Sel =


<s> static DecodeStatus DecodeF8RCRegisterClass ( MCInst & Inst , uint64_t RegNo , uint64_t Address , const MCDisassembler * Decoder ) { return decodeRegisterClass ( Inst ,


<s> void printMemRegReg ( const MachineInstr * MI , unsigned OpNo ) { const MachineOperand & MO = MI -> getOperand ( OpNo ) ; O << TM . getRegisterInfo ( ) -> get ( MO . getReg ( ) ) . AsmName ; O << <STR_LIT> ; printOperand ( MI , OpNo + <NUM_LIT>


<s> return ( vector signed int ) __builtin_altivec_vupkhsh ( ( vector signed short )


<s> BuildMI ( FirstMBB , MBBI , dl , TII . get ( <STR_LIT> ) , GlobalBaseReg ) ; } else { GlobalBaseReg = RegInfo -> createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( FirstMBB , MBBI , dl , TII . get ( <STR_LIT> ) ) ; BuildMI ( FirstMBB , MBBI , dl , TII . get ( <STR_LIT> ) , GlobalBaseReg ) ; } } return CurDAG -> getRegister ( GlobalBaseReg , <ISA_LIT>Lowering -> getPointerTy ( ) ) .