<s> MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; unsigned FrameSize = UseEstimate ? MFI -> estimateStackSize ( MF ) : MFI -> getStackSize ( ) ; unsigned TargetAlign = getStackAlignment ( ) ; unsigned MaxAlign = MFI -> getMaxAlignment ( ) ; unsigned AlignMask = std :: max ( MaxAlign , TargetAlign ) - <NUM_LIT> ; const <ISA_LIT>RegisterInfo * RegInfo = static_cast < const <ISA_LIT>RegisterInfo * > ( MF . getSubtarget ( ) . getRegisterInfo ( ) ) ; bool DisableRedZone = MF . getFunction ( ) -> getAttributes ( ) . hasAttribute ( AttributeSet :: FunctionIndex , Attribute :: NoRedZone ) ; if ( ! DisableRedZone && ( Subtarget . is<ISA_LIT>64 ( ) || ! Subtarget . isSVR4ABI ( ) || FrameSize == <NUM_LIT> ) && FrameSize <= <NUM_LIT> && ! MFI -> hasVarSizedObjects ( ) && ! MFI -> adjustsStack ( ) && ! RegInfo -> hasBasePointer ( MF ) ) { if ( UpdateMF ) MFI -> setStackSize ( <NUM_LIT> ) ; return <NUM_LIT> ; } unsigned maxCallFrameSize = MFI -> getMaxCallFrameSize ( ) ; unsigned minCallFrameSize = getLinkageSize ( Subtarget . is<ISA_LIT>64 ( ) , Subtarget . isDarwinABI ( )


<s> const AttributeList & InvokeAL = CI -> getAttributes ( ) ; ArgAttributes . push_back ( AttributeSet ( ) ) ; for ( unsigned I = <NUM_LIT> , E = CI -> getNumArgOperands ( ) ; I < E ; ++ I ) ArgAttributes . push_back ( InvokeAL . getParamAttributes ( I ) ) ; AttrBuilder FnAttrs ( InvokeAL . getFnAttributes ( ) ) ; if ( FnAttrs . contains ( Attribute :: AllocSize ) ) { unsigned SizeArg ; Optional < unsigned > NEltArg ; std :: tie ( SizeArg , NEltArg ) = FnAttrs . getAllocSizeArgs ( ) ; SizeArg += <NUM_LIT> ; if ( NEltArg . hasValue ( ) ) NEltArg = NEltArg . getValue ( ) + <NUM_LIT> ; FnAttrs . addAllocSizeAttr ( SizeArg , NEltArg ) ; } AttributeList NewCallAL = AttributeList :: get ( C , AttributeSet :: get (

C , FnAttrs ) , InvokeAL . getRetAttributes ( ) , ArgAttributes ) ;


<s> const <ISA_LIT>RegisterInfo * TRI = static_cast < const <ISA_LIT>RegisterInfo * > ( MF -> getTarget ( ) . getSubtarget < AMDGPUSubtarget > ( ) . getRegisterInfo ( ) ) ; MachineRegisterInfo & MRI = MF -> getRegInfo ( ) ; int64_t Offset = FrameInfo -> getObjectOffset ( FrameIndex ) ; Offset += SubIdx * <NUM_LIT> ; unsigned LaneVGPRIdx = Offset / ( <NUM_LIT> * <NUM_LIT> ) ; unsigned Lane = ( Offset / <NUM_LIT> ) % <NUM_LIT> ; struct SpilledReg Spill ; if ( ! LaneVGPRs . count ( LaneVGPRIdx ) ) { unsigned LaneVGPR = TRI -> findUnusedRegister ( MRI , & AMDGPU :: VGPR_32RegClass ) ; LaneVGPRs [ LaneVGPRIdx ] = LaneVGPR ; MRI . setPhysRegUsed ( LaneVGPR ) ; for ( MachineFunction :: iterator BI = MF -> begin ( ) ,


<s> return ELF :: R_<ISA_LIT>_PCREL_HI20 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_PCREL_LO12_I ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_PCREL_LO12_S ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_GOT_HI20 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_TLS_GOT_HI20 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_TLS_GD_HI20 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_JAL ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_BRANCH ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_RVC_JUMP ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_RVC_BRANCH ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_CALL ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_CALL_PLT ; } } switch ( Kind ) { default : llvm_unreachable ( <STR_LIT> ) ; case FK_Data_4 : return ELF :: R_<ISA_LIT>_32 ; case FK_Data_8 : return ELF :: R_<ISA_LIT>_64 ; case FK_Data_Add_1 : return ELF :: R_<ISA_LIT>_ADD8 ; case FK_Data_Add_2 : return ELF :: R_<ISA_LIT>_ADD16 ; case FK_Data_Add_4 : return ELF :: R_<ISA_LIT>_ADD32 ; case


<s> unsigned POTReg = getPOTBaseRegister ( ) ; if ( MF . getFunction ( ) . isPagerando ( ) ) { return DAG . getCopyFromReg ( DAG . getEntryNode ( ) , dl , POTReg , PtrVT ) ; } else { SDValue POTAddress = DAG . getTargetExternalSymbol ( <STR_LIT> , PtrVT , <STR_LIT> ) ; POTAddress = DAG . getNode ( <STR_LIT> , dl , PtrVT , POTAddress ) ; SDValue Chain = DAG . getCopyToReg ( DAG . getEntryNode ( ) , dl , POTReg , POTAddress ) ; SDValue Ops [ <NUM_LIT> ] = { POTAddress , Chain } ; return DAG . getMergeValues ( Ops , dl


<s> void <ISA_LIT>AsmBackend :: applyFixup ( const MCAssembler & Asm , const MCFixup & Fixup , const MCValue & Target , MutableArrayRef < char > Data , uint64_t Value , bool IsResolved , const MCSubtargetInfo * STI ) const { unsigned NumBytes = getFixupKindNumBytes ( Fixup . getKind ( ) ) ; if ( ! Value ) return ; MCFixupKindInfo Info = getFixupKindInfo ( Fixup . getKind ( ) ) ; MCContext & Ctx = Asm . getContext ( ) ; Value = adjustFixupValue ( Fixup , Target , Value , Ctx , TheTriple , IsResolved ) ; Value <<= Info . TargetOffset ; unsigned Offset = Fixup . getOffset ( ) ; assert ( Offset + NumBytes <= Data . size ( ) && <STR_LIT> ) ; unsigned FulleSizeInBytes = getFixupKindContainereSizeInBytes ( Fixup . getKind ( ) ) ; if ( FulleSizeInBytes == <NUM_LIT> ) { for ( unsigned i = <NUM_LIT> ; i != NumBytes ; ++ i ) { Data [ Offset + i ] |= uint8_t ( ( Value >> ( i *


<s> if ( op == virtual_incoming_args_rtx || op == virtual_stack_vars_rtx || op == virtual_stack_dynamic_rtx || op ==

virtual_outgoing_args_rtx || op == virtual_cfa_rtx ) return <NUM_LIT> ;


<s> break ; case 'd' : case 'y' : if ( type -> isIntegerTy ( ) ) weight = CW_Register ; break ; case 'f' : if ( type -> isFloatTy (


<s> if ( GLC ) { * GLC = DAG . getTargetConstant ( ( Value & <NUM_LIT> ) ? <NUM_LIT> : <NUM_LIT> , DL , <STR_LIT> ) ; Value &= ~ ( uint64_t ) <NUM_LIT> ; } if ( SLC ) { * SLC = DAG . getTargetConstant ( ( Value & <NUM_LIT> ) ? <NUM_LIT> : <NUM_LIT> , DL


<s> MachineRegisterInfo * MRI = & MF -> getRegInfo ( ) ; bool PostRA = ! MRI -> isSSA ( ) ; if ( ! PostRA ) return false ; unsigned ToBeDeletedReg = <NUM_LIT> ; int64_t OffsetImm = <NUM_LIT> ; unsigned XFormOpcode = <NUM_LIT> ; ImmInstrInfo III ; if ( ! isImmInstrEligibleForFolding ( MI , ToBeDeletedReg , XFormOpcode , OffsetImm , III ) ) return false ; bool OtherIntermediateUse = false ; MachineInstr * ADDMI = getDefMIPostRA ( ToBeDeletedReg , MI , OtherIntermediateUse ) ; if ( OtherIntermediateUse || ! ADDMI ) return false ; if ( ! isADDInstrEligibleForFolding ( * ADDMI ) ) return false ; unsigned ScaleRegIdx = <NUM_LIT> ; int64_t OffsetAddi = <NUM_LIT> ; MachineInstr * ADDIMI = nullptr ; if ( isValidToBeChangedReg ( ADDMI , <NUM_LIT> , ADDIMI , OffsetAddi , OffsetImm ) ) ScaleRegIdx = <NUM_LIT> ; else if ( isValidToBeChangedReg ( ADDMI , <NUM_LIT> , ADDIMI , OffsetAddi , OffsetImm ) ) ScaleRegIdx = <NUM_LIT> ; else return false ; assert ( ADDIMI && <STR_LIT> ) ; unsigned ToBeChangedReg = ADDIMI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned ScaleReg = ADDMI -> getOperand ( ScaleRegIdx ) . getReg ( ) ; auto NewDefFor = [ & ] ( unsigned Reg , MachineBasicBlock :: iterator Start , MachineBasicBlock :: iterator End ) { for ( auto It = ++ Start ; It != End ; It ++ ) if ( It -> modifiesRegister ( Reg , & getRegisterInfo ( ) ) ) return true ; return false ; } ; if ( NewDefFor ( ToBeChangedReg , * ADDMI , MI ) || NewDefFor ( ScaleReg , * ADDMI , MI ) ) return false ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << <STR_LIT> ) ; LLVM_DEBUG ( ADDIMI -> dump ( ) ) ; LLVM_DEBUG ( ADDMI -> dump ( ) ) ; LLVM_DEBUG ( MI . dump ( ) ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << <STR_LIT> ) ; ADDIMI -> getOperand ( <NUM_LIT> ) . setImm ( OffsetAddi + OffsetImm ) ; MI . setDesc ( get ( XFormOpcode ) ) ; MI . getOperand ( III . ImmOpNo ) . ChangeToRegister ( ScaleReg , false , false

, ADDMI -> getOperand ( ScaleRegIdx ) . isKill ( ) ) ;


<s> const TargetRegisterClass * RC ; if ( RegVT == <STR_LIT> ) { RC = & <STR_LIT> ; } else if ( RegVT == <STR_LIT> ) { RC = & <STR_LIT> ; } else { llvm_unreachable ( <STR_LIT> ) ; } unsigned Reg = MF . addLiveIn ( VA . getLocReg ( ) , RC ) ; ArgValue = DAG . getCopyFromReg ( Chain , dl , Reg , RegVT ) ; switch ( VA . getLocInfo ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case CCValAssign :: Full : break ; case CCValAssign :: BCvt : ArgValue = DAG . getNode ( <STR_LIT> , dl , VA . getValVT ( ) , ArgValue ) ; break ; case CCValAssign :: SExt : ArgValue = DAG . getNode ( <STR_LIT> , dl , RegVT , ArgValue , DAG . getValueType ( VA . getValVT ( ) ) ) ; ArgValue = DAG . getNode ( <STR_LIT> , dl , VA . getValVT ( ) , ArgValue ) ; break ; case CCValAssign :: ZExt : ArgValue = DAG . getNode ( <STR_LIT> , dl , RegVT , ArgValue , DAG . getValueType ( VA . getValVT ( ) ) ) ; ArgValue = DAG . getNode ( <STR_LIT> , dl , VA . getValVT ( ) , ArgValue ) ; break ; } InVals . push_back ( ArgValue ) ; } else { assert ( VA . isMemLoc ( ) ) ; EVT LocVT = VA . getLocVT ( ) ; int FI = MFI . CreateFixedObject ( LocVT . getSizeInBits ( ) / <NUM_LIT> , VA . getLocMemOffset ( ) , true ) ; SDValue FIN = DAG . getFrameIndex ( FI , getPointerTy ( DL ) ) ; InVals . push_back ( DAG . getLoad ( LocVT , dl , Chain , FIN , MachinePointerInfo :: getFixedStack ( MF , FI ) , <NUM_LIT> ) ) ; } } if (


<s> StringRef getPassName ( ) const override { return <STR_LIT>


<s> switch ( Ord ) { case AtomicOrdering :: NotAtomic : case AtomicOrdering :: Unordered : llvm_unreachable ( <STR_LIT> ) ; case AtomicOrdering :: Monotonic : case AtomicOrdering :: Release : return nullptr ; case AtomicOrdering


<s> <ISA_LIT>_32TargetMachine :: <ISA_LIT>_32TargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) : <ISA_LIT>TargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL ) { if ( TT . getArch ( ) == Triple ::


<s> SmallVector < SDValue , <NUM_LIT> > MaskOps ; for ( int i = <NUM_LIT> , Size = Mask . size ( ) ; i < Size ; ++ i ) { if ( Mask [ i ] >= <NUM_LIT> && Mask [ i ] != i && Mask [ i ] != i + Size ) return SDValue ( ) ; MaskOps . push_back ( Mask [ i ] < Size ? AllOnes : Zero ) ; } SDValue V1Mask = DAG . getBuildVector ( VT , DL , MaskOps ) ; V1 = DAG . getNode ( <STR_LIT> , DL ,


<s> bool <ISA_LIT>TargetLowering :: allowsMisalignedMemoryAccesses ( EVT VT , unsigned AddrSpace , unsigned Align , bool * IsFast ) const { if ( IsFast ) * IsFast = false ; if ( ! VT . isSimple ( ) || VT == <STR_LIT> ) return false ; if ( AddrSpace == <ISA_LIT>AS :: LOCAL_ADDRESS || AddrSpace == <ISA_LIT>AS :: REGION_ADDRESS ) { bool AlignedBy4 = ( Align % <NUM_LIT> == <NUM_LIT> ) ; if ( IsFast ) * IsFast = AlignedBy4 ; return AlignedBy4 ; } if ( Subtarget -> hasUnalignedBufferAccess ( ) ) { if (


<s> static bool CC_<ISA_LIT>_Assign_SRet ( unsigned & ValNo , MVT & ValVT , MVT & LocVT , CCValAssign :: LocInfo & LocInfo , <STR_LIT> & ArgFlags , CCState & State ) { assert ( ArgFlags . isSRet ( ) ) ; State . addLoc ( CCValAssign :: getCustomMem ( ValNo , ValVT , <NUM_LIT> , LocVT , LocInfo ) ) ; return


<s> extern __inline __m128i __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) _mm_i64gather_epi64 ( long long int const * base , __m128i index , const int scale ) { __v2di src = __extension__ ( __v2di ) {


<s> BitVector <ISA_LIT>RegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set (


<s> assert ( VT . isVector ( ) && <STR_LIT> ) ; unsigned ElementBits = VT . getVectorElementType ( ) . getSizeInBits ( ) ; if ( ! getVShiftImm ( Op , ElementBits , Cnt ) ) return false ; if ( isIntrinsic ) Cnt


<s> } } SmallVector < MachineBasicBlock * , <NUM_LIT> > SFBlocks ; BitVector CSR ( <STR_LIT> ) ; for ( const MCPhysReg * P = HRI . getCalleeSavedRegs ( & MF ) ; * P ; ++ P ) for ( MCSubRegIterator S ( * P , & HRI , true ) ; S . isValid ( ) ; ++ S ) CSR [ * S ] = true ; for ( auto & I : MF ) if ( needsStackFrame ( I , CSR , HRI ) ) SFBlocks . push_back ( & I ) ; DEBUG ( { dbgs ( ) << <STR_LIT> ; for ( auto & B : SFBlocks ) dbgs (


<s> MVT ExtVT = VT ; MVT EltVT = VT . getVectorElementType ( ) ; int V2Index = std :: find_if ( Mask . begin ( ) , Mask . end ( ) , [ & Mask ] ( int M ) { return M >= ( int ) Mask . size ( ) ; } ) - Mask . begin ( ) ; bool IsV1Zeroable = true ; for ( int i = <NUM_LIT> , Size = Mask . size ( ) ; i < Size ; ++ i ) if ( i != V2Index && ! Zeroable [ i ] ) { IsV1Zeroable = false ; break ; } if ( SDValue V2S = getScalarValueForVectorElement ( V2 , Mask [ V2Index ] - Mask . size ( ) , DAG ) ) { V2S = DAG . getNode ( <STR_LIT> , DL , EltVT , V2S ) ; if ( EltVT == <STR_LIT> || EltVT == <STR_LIT> ) { if ( ! IsV1Zeroable ) return SDValue ( ) ; ExtVT = <STR_LIT> ; V2S = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V2S ) ; } V2 = DAG . getNode ( <STR_LIT> , DL , ExtVT , V2S ) ; } else if ( Mask [ V2Index ] != ( int ) Mask . size ( ) || EltVT == <STR_LIT> || EltVT == <STR_LIT> ) { return SDValue ( ) ; } if ( ! IsV1Zeroable ) { assert ( VT == ExtVT && <STR_LIT> ) ; if ( ! VT . isFloatingPoint ( ) || V2Index != <NUM_LIT> ) return SDValue ( ) ; SmallVector < int , <NUM_LIT> > V1Mask ( Mask . begin ( ) , Mask . end ( ) ) ; V1Mask [ V2Index ] = - <NUM_LIT> ; if ( ! isNoopShuffleMask ( V1Mask ) ) return SDValue ( ) ; if ( Subtarget -> hasSSE41 ( ) ) return SDValue ( ) ; assert ( ( EltVT == <STR_LIT> || EltVT == <STR_LIT> ) && <STR_LIT> ) ; return DAG . getNode ( EltVT == <STR_LIT> ? <STR_LIT> : <STR_LIT> , DL , ExtVT , V1 , V2 ) ; } if ( VT . isFloatingPoint ( ) && V2Index != <NUM_LIT> ) return SDValue ( ) ; V2 = DAG . getNode ( <STR_LIT> , DL , ExtVT , V2 ) ; if ( ExtVT != VT ) V2 = DAG . getNode ( <STR_LIT> , DL , VT , V2 ) ; if ( V2Index != <NUM_LIT> ) { if ( VT . isFloatingPoint ( ) || VT . getVectorNumElements ( ) <= <NUM_LIT> ) { SmallVector < int , <NUM_LIT> > V2Shuffle ( Mask . size ( ) , <NUM_LIT> ) ; V2Shuffle [ V2Index ] =


<s> StoreSDNode & Nd = * cast < StoreSDNode > ( Op ) ; if ( Nd . getMemoryVT ( ) != <STR_LIT> || ! NoDPLoadStore ) return <ISA_LIT>TargetLowering :: lowerSTORE ( Op , DAG ) ; SDLoc DL ( Op ) ; SDValue Val = Nd . getValue ( ) , Ptr = Nd . getBasePtr ( ) , Chain = Nd . getChain ( ) ; EVT PtrVT = Ptr . getValueType ( ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Val , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Val , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; if ( ! Subtarget . isLittle ( ) ) std :: swap ( Lo , Hi ) ; Chain = DAG . getStore ( Chain , DL , Lo , Ptr , MachinePointerInfo ( ) , Nd . isVolatile ( ) , Nd . isNonTemporal (

) , Nd . getAlignment ( ) , Nd . getAAInfo ( ) ) ;


<s> static void force_into_acc ( rtx src , rtx_insn * before ) { machine_mode mode = GET_MODE ( src ) ; rtx move ; if ( REG_P ( src ) && REGNO ( src ) < <NUM_LIT> ) return ; move = mode == QImode ? gen_movqi ( A ,


<s> if ( N -> getOpcode ( ) == <STR_LIT> ) return true ; if ( isExtendedBUILD_VECTOR ( N , DAG , false ) ) return true ; return false


<s> return TargetTransformInfo ( <ISA_LIT>TTIImpl ( this , F ) ) ; }


<s> static rtx add_crlr_cfa_restore ( const rs6000_stack_t * info , rtx cfa_restores ) { if ( DEFAULT_ABI == ABI_ELFv2 ) { int i ; for ( i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) if ( save_reg_p ( CR0_REGNO + i ) ) { rtx cr = gen_rtx_REG ( SImode , CR0_REGNO + i ) ; cfa_restores = alloc_reg_note ( REG_CFA_RESTORE , cr , cfa_restores ) ; } } else if ( info -> cr_save_p ) cfa_restores = alloc_reg_note ( REG_CFA_RESTORE , gen_rtx_REG ( SImode ,


<s> return __builtin_mve_vrhaddq_m_sv8hi ( __arm_vuninitializedq_s16 ( ) , __a


<s> SDValue LoadVal = DAG . getLoad ( RegTy , DL , Chain , LoadPtr , MachinePointerInfo ( ) , false , false , false , Alignment ) ; MemOpChains . push_back ( LoadVal . getValue ( <NUM_LIT> ) ) ; unsigned ArgReg = ArgRegs [ FirstReg + I ] ; RegsToPass . push_back ( std :: make_pair ( ArgReg , LoadVal ) ) ; } if ( ByValSizeInBytes == OffsetInBytes ) return ; if ( LeftoverBytes ) { SDValue Val ; for ( unsigned LoadSizeInBytes = RegSizeInBytes / <NUM_LIT> , TotalBytesLoaded = <NUM_LIT> ; OffsetInBytes < ByValSizeInBytes ; LoadSizeInBytes /= <NUM_LIT> ) { unsigned RemainingSizeInBytes = ByValSizeInBytes - OffsetInBytes ; if ( RemainingSizeInBytes < LoadSizeInBytes ) continue ; SDValue LoadPtr = DAG . getNode ( <STR_LIT> , DL , PtrTy , Arg , DAG . getConstant ( OffsetInBytes , PtrTy ) ) ; SDValue LoadVal = DAG . getExtLoad ( <STR_LIT> , DL , RegTy , Chain , LoadPtr , MachinePointerInfo ( ) , <STR_LIT> ( LoadSizeInBytes * <NUM_LIT> ) , false , false , false , Alignment ) ; MemOpChains . push_back ( LoadVal . getValue ( <NUM_LIT> ) ) ; unsigned Shamt ; if ( isLittle ) Shamt = TotalBytesLoaded * <NUM_LIT> ; else Shamt = ( RegSizeInBytes - ( TotalBytesLoaded + LoadSizeInBytes ) ) * <NUM_LIT> ; SDValue Shift = DAG . getNode ( <STR_LIT> , DL , RegTy , LoadVal , DAG . getConstant ( Shamt , <STR_LIT> ) ) ; if ( Val . getNode ( ) ) Val = DAG . getNode ( <STR_LIT> , DL , RegTy , Val , Shift ) ; else Val =


<s> assert ( MO . isGlobal ( ) ) ; const auto * F = dyn_cast < Function > ( MO . getGlobal ( ) ) ; if ( ! F ) return true ; if ( F -> doesNotThrow ( ) ) return false ; if ( F -> getName ( ) == CxaBeginCatchFn || F -> getName ( ) == PersonalityWrapperFn || F -> getName ( ) == ClangCallTerminateFn || F -> getName ( ) == StdTerminateFn ) return false ; return true


<s> static MachineInstr * insertCopy ( const <ISA_LIT>InstrInfo * TII , MachineInstr * MI , unsigned Dst , unsigned Src , bool IsKill ) { MachineInstrBuilder MIB = BuildMI ( * MI -> getParent ( ) , MI , MI -> getDebugLoc ( ) ,

TII -> get ( <STR_LIT> ) , Dst ) . addReg ( Src , getKillRegState ( IsKill ) ) ;


<s> if ( ! strict_p && GET_CODE ( x ) == SUBREG ) x = SUBREG_REG (


<s> Op -> VectorList . isDoubleSpaced = isDoubleSpaced ; Op -> StartLoc = S ; Op -> EndLoc = E ; return Op


<s> DEBUG ( errs ( ) << <STR_LIT> ) ; return <NUM_LIT> ; } return new <ISA_LIT>BasicMCBuilder ( Opcode , Format , <ISA_LIT>Insts


<s> SDValue Ops [ <NUM_LIT> ] = { Hi , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) , Data_Lo . getValue ( <NUM_LIT> ) } ; Data_Hi = DAG . getNode ( <STR_LIT> , dl , VTList , Ops , <NUM_LIT> ) ; SDValue PCLATH = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Data_Hi ) ; Callee = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Data_Lo , PCLATH ) ; SDValue Call = DAG . getNode ( <STR_LIT> , dl , Tys , Chain , Callee , OperFlag ) ; Chain = getChain ( Call ) ; OperFlag = getOutFlag ( Call ) ; SDValue SeqEnd = DAG . getCALLSEQ_END ( Chain , ZeroOperand , ZeroOperand , OperFlag ) ; Chain = getChain ( SeqEnd ) ; OperFlag = getOutFlag ( SeqEnd ) ; DataAddr_Lo = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Call , OperFlag ) ; SeqStart = DAG . getCALLSEQ_START ( Chain , ZeroOperand ) ; Chain = getChain ( SeqStart ) ; OperFlag = getOutFlag ( SeqStart ) ; Data_Lo = DAG . getNode ( <STR_LIT> , dl , VTList , Lo

, DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ;


<s> SDValue <ISA_LIT>TargetLowering :: opCastElem ( SDValue Vec , MVT ElemTy , SelectionDAG & DAG ) const { if ( ty ( Vec ) . getVectorElementType ( ) == ElemTy ) return Vec ; MVT CastTy = tyVector ( Vec . getValueType ( ) . getSimpleVT


<s> if ( getSTI ( ) . getTargetTriple ( ) . getOS ( ) != Triple :: AMDPAL ) { return Error ( getParser ( ) . getTok ( ) . getLoc ( ) , ( Twine ( PALMD :: AssemblerDirective ) + Twine ( <STR_LIT> <STR_LIT> ) ) . str ( ) ) ; } auto PALMetadata = getTargetStreamer ( ) . getPALMetadata ( ) ; PALMetadata -> setLegacy ( ) ; for ( ; ; ) { uint32_t Key , Value ; if ( ParseAsAbsoluteExpression (


<s> Data . Type = ST_NONE ; Data . Address = <NUM_LIT> ; Data . Bank = ~ <NUM_LIT> ; Data . Alignment


<s> } else { NonclearedFPRegs . push_back ( Reg ) ; } } } } bool passesFPReg = ( ! NonclearedFPRegs . empty ( ) || ! ClearedFPRegs . empty ( ) ) ; if ( passesFPReg ) assert ( STI -> hasFPRegs ( ) && <STR_LIT> ) ; MachineInstrBuilder VLSTM = BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) ) . addReg ( <STR_LIT> ) . add ( predOps ( <STR_LIT> ) ) ; for ( auto R : { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ) VLSTM . addReg ( R , RegState :: Implicit | ( LiveRegs . contains ( R ) ? <NUM_LIT> : RegState :: Undef ) ) ; for ( const auto & Regs : ClearedFPRegs ) { unsigned Reg , SaveReg1 , SaveReg2 ; std :: tie ( Reg , SaveReg1 , SaveReg2 ) = Regs ; if ( <STR_LIT> . contains ( Reg ) ) BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) , Reg ) . addReg ( SaveReg1 ) . addReg ( SaveReg2 ) . add ( predOps ( <STR_LIT> ) ) ; else if ( <STR_LIT> . contains ( Reg ) ) BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) , Reg ) . addReg ( SaveReg1 ) . add ( predOps ( <STR_LIT> ) ) ; } for ( unsigned Reg : NonclearedFPRegs ) { if ( <STR_LIT> . contains ( Reg ) ) { if ( STI -> isLittle ( ) ) { BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) , Reg ) . addReg ( <STR_LIT> ) . addImm ( ( Reg - <STR_LIT> ) * <NUM_LIT> ) . add ( predOps ( <STR_LIT> ) ) ; } else { unsigned SReg0 = TRI -> getSubReg ( Reg , <STR_LIT> ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) , SReg0 ) . addReg ( <STR_LIT> ) . addImm ( ( Reg - <STR_LIT> ) * <NUM_LIT> ) .


<s> Value * Cond = Builder . CreateICmpEQ ( Mbcnt , Builder . getInt32 ( <NUM_LIT> ) ) ; Instruction * WB = cast < Instruction > ( Builder . CreateIntrinsic ( <STR_LIT> , { } , { } ) ) ; BasicBlock * NBB = SplitBlockAndInsertIfThen ( Cond ,


<s> int64_t Val = CE -> getValue ( ) ; return ( Val > - <NUM_LIT> && Val < <NUM_LIT> ) || ( Val == std :: numeric_limits < int32_t > :: min ( ) ) ; } return


<s> int i ; int firstloop = <NUM_LIT> ; if ( code == NEG ) emit_move_insn ( src0 , const0_rtx ) ; for ( i = <NUM_LIT> ; i < num_words ; i ++ ) { rtx w_src0 , w_src1 , w_dest ; rtx insn ; w_src0 = simplify_gen_subreg ( word_mode , src0 , mode , i * UNITS_PER_WORD ) ; w_src1 = simplify_gen_subreg ( word_mode , src1 , mode , i * UNITS_PER_WORD ) ; w_dest = simplify_gen_subreg ( word_mode , dest , mode , i * UNITS_PER_WORD ) ; switch ( code ) { case PLUS : if ( firstloop && CONST_INT_P ( w_src1 ) && INTVAL ( w_src1 ) == <NUM_LIT> ) continue ; if ( firstloop ) insn = gen_addchi4 ( w_dest , w_src0 , w_src1 ) ; else insn = gen_addchi5 ( w_dest , w_src0 , w_src1 ) ; break ; case NEG : case MINUS : case COMPARE : if ( code == COMPARE && i == num_words - <NUM_LIT> ) { rtx branch , sub , clobber , sub_1 ; sub_1 = gen_rtx_MINUS ( HImode , w_src0 , gen_rtx_ZERO_EXTEND ( HImode , gen_rtx_REG ( BImode , CARRY_REGNUM ) ) ) ; sub = gen_rtx_SET ( VOIDmode , w_dest , gen_rtx_MINUS ( HImode , sub_1 , w_src1 ) ) ; clobber = gen_rtx_CLOBBER ( VOIDmode , gen_rtx_REG ( BImode , CARRY_REGNUM ) ) ; branch = gen_rtx_SET ( VOIDmode , pc_rtx , gen_rtx_IF_THEN_ELSE ( VOIDmode , gen_rtx_EQ ( HImode , sub_1 , w_src1 ) , pc_rtx , pc_rtx ) ) ; insn = gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( <NUM_LIT> , branch , sub , clobber ) ) ; } else if ( firstloop && code != COMPARE && CONST_INT_P ( w_src1 ) && INTVAL ( w_src1 ) == <NUM_LIT> ) continue ; else if ( firstloop ) insn = gen_subchi4 ( w_dest , w_src0 , w_src1 ) ; else insn = gen_subchi5 ( w_dest , w_src0 ,


<s> machine_mode mode ; rtx addr , align , wdst ; rtx ( * gen ) ( rtx , rtx , rtx , rtx , rtx , rtx , rtx , rtx , rtx ) ; cond = operands [ <NUM_LIT> ] ; dst = operands [ <NUM_LIT> ] ; mem = operands [ <NUM_LIT> ] ; oldval = operands [ <NUM_LIT> ] ; newval = operands [ <NUM_LIT> ] ; is_weak = operands [ <NUM_LIT> ] ; mod_s = operands [ <NUM_LIT> ] ; mod_f = operands


<s> std :: tie ( Value , Overflow ) = get<ISA_LIT>XALUOOp ( CC , Op , DAG ) ; SDValue TVal = DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ; SDValue FVal = DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ; SDValue CCVal = DAG . getConstant ( getInvertedCondCode ( CC ) , dl , <STR_LIT> ) ; Overflow = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , FVal , TVal , CCVal , Overflow ) ; SDVTList VTs = DAG . getVTList ( Op . getValueType


<s> unsigned Dst = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Src = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; BuildMI ( MBB , MBB . getFirstNonPHI ( ) , DL , TII -> get ( <STR_LIT> ) , Dst ) . addReg ( Src ) ; BuildMI ( MBB , & MI , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> )

. addReg ( <STR_LIT> ) . addReg ( Dst ) ;


<s> unsigned HOST_WIDE_INT ival ; if ( GET_CODE ( x ) == CONST_DOUBLE && SCALAR_FLOAT_MODE_P ( mode ) && aarch64_reinterpret_float_as_int ( x , & ival ) ) { scalar_int_mode imode = ( mode == HFmode ? SImode : int_mode_for_mode ( mode ) . require ( ) ) ; int num_instr = aarch64_internal_mov_immediate ( NULL_RTX , gen_int_mode ( ival , imode ) , false , imode ) ; return num_instr < <NUM_LIT> ; } return


<s> const <ISA_LIT>Subtarget & Subtarget = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; AttributeList Attrs = MF . getFunction ( ) . getAttributes ( ) ; return Subtarget . isTargetMachO ( ) && ! ( Subtarget . getTargetLowering ( ) -> supportSwiftError ( ) && Attrs . hasAttrSomewhere (


<s> int total_size = compute_total_frame_size ( ) ; if ( from == FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM ) { return ( total_size - crtl -> args . pretend_args_size - tilegx_saved_regs_size ( ) ) ; } else if ( from == FRAME_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM ) { return - ( crtl -> args . pretend_args_size + tilegx_saved_regs_size ( ) ) ; } else if ( from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM ) { return STACK_POINTER_OFFSET + total_size ; } else if ( from == ARG_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM ) { return STACK_POINTER_OFFSET ; } else gcc_unreachable (


<s> } if ( LastCMOV == & MI && NextMIIt != ThisMBB -> end ( ) && NextMIIt -> getOpcode ( ) == MI . getOpcode ( ) && NextMIIt -> getOperand ( <NUM_LIT> ) . getReg ( ) == MI . getOperand ( <NUM_LIT> ) . getReg ( ) && NextMIIt -> getOperand ( <NUM_LIT> ) . getReg ( ) == MI . getOperand ( <NUM_LIT> ) . getReg ( ) && NextMIIt -> getOperand ( <NUM_LIT> ) . isKill ( ) ) { return EmitLoweredCascadedSelect ( MI , * NextMIIt , ThisMBB ) ; } const BasicBlock * LLVM_BB = ThisMBB -> getBasicBlock ( ) ; MachineFunction * F = ThisMBB -> getParent ( ) ; MachineBasicBlock * FalseMBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * SinkMBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineFunction :: iterator It = ++ ThisMBB -> getIterator ( ) ; F -> insert ( It , FalseMBB ) ; F -> insert ( It , SinkMBB ) ; const TargetRegisterInfo * TRI = Subtarget . getRegisterInfo ( ) ; if ( ! LastCMOV -> killsRegister ( <STR_LIT> ) && ! checkAndUpdateEFLAGSKill ( LastCMOV , ThisMBB , TRI ) ) { FalseMBB -> addLiveIn ( <STR_LIT> ) ; SinkMBB -> addLiveIn ( <STR_LIT> ) ; } SinkMBB -> splice ( SinkMBB -> begin ( ) , ThisMBB , std :: next ( MachineBasicBlock :: iterator ( LastCMOV ) ) , ThisMBB -> end ( ) ) ; SinkMBB -> transferSuccessorsAndUpdatePHIs ( ThisMBB ) ; ThisMBB -> addSuccessor ( FalseMBB ) ; ThisMBB -> addSuccessor (


<s> format ( <STR_LIT> , FixupOffset ) . print ( Buffer , sizeof ( Buffer ) ) ; Asm . getContext ( ) . reportFatalError ( Fixup . getLoc ( ) , Twine ( <STR_LIT> <STR_LIT> ) + Buffer + <STR_LIT> <STR_LIT> ) ; llvm_unreachable ( <STR_LIT> ) ; } MachO :: any_relocation_info MRE ; MRE . r_word0 = ( ( <NUM_LIT> << <NUM_LIT> ) | ( MachO :: GENERIC_RELOC_PAIR << <NUM_LIT> ) | ( Log2Size << <NUM_LIT> ) | ( IsPCRel << <NUM_LIT> ) | MachO :: R_SCATTERED ) ; MRE . r_word1 = Value2 ; Writer -> addRelocation ( nullptr , Fragment -> getParent ( ) , MRE ) ; } else { if ( FixupOffset > <NUM_LIT> ) { FixedValue = OriginalFixedValue ; return false ; } } MachO :: any_relocation_info MRE ; MRE . r_word0 = ( ( FixupOffset << <NUM_LIT> ) | ( Type << <NUM_LIT> ) | ( Log2Size << <NUM_LIT> ) | ( IsPCRel << <NUM_LIT> ) | MachO :: R_SCATTERED ) ; MRE . r_word1 = Value ; Writer -> addRelocation ( nullptr , Fragment -> getParent


<s> if ( ! VT . isScalableVector ( ) ) return false ; EVT ElemVT = VT . getVectorElementType ( ) ; if ( Alignment >= ElemVT . getStoreSize ( ) ) { if ( Fast ) * Fast = true ; return true ; } return


<s> SDValue OuFlag = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; SDNode * DSPCtrlField = CurDAG -> getMachineNode ( <STR_LIT> , DL , <STR_LIT> , <STR_LIT> , CstOne , InFlag ) ; SDNode * Carry = CurDAG -> getMachineNode ( <STR_LIT> , DL , <STR_LIT> , SDValue ( DSPCtrlField , <NUM_LIT> ) , OuFlag , CstOne ) ; SDValue Ops [ <NUM_LIT> ] = { SDValue ( DSPCtrlField , <NUM_LIT> ) , CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) , CstOne , SDValue ( Carry , <NUM_LIT> ) } ; SDNode * DSPCFWithCarry = CurDAG -> getMachineNode ( <STR_LIT> , DL , <STR_LIT> , Ops ) ; SDValue Zero = CurDAG -> getRegister ( <STR_LIT> , <STR_LIT> ) ; SDValue InsOps [ <NUM_LIT> ] = { Zero , OuFlag , CstOne , SDValue ( DSPCFWithCarry , <NUM_LIT> ) } ; SDNode * DSPCtrlFinal = CurDAG -> getMachineNode ( <STR_LIT> , DL , <STR_LIT> , InsOps ) ; SDNode * WrDSP = CurDAG -> getMachineNode ( <STR_LIT> , DL , <STR_LIT> , SDValue ( DSPCtrlFinal , <NUM_LIT> ) , CstOne ) ; SDValue Operands [ <NUM_LIT> ] = { LHS , RHS , SDValue ( WrDSP , <NUM_LIT> ) } ; CurDAG -> SelectNodeTo ( Node , <STR_LIT> , VT , <STR_LIT> , Operands


<s> return IsConstantImm && isShiftedUInt < <NUM_LIT> , <NUM_LIT> > ( Imm ) && VK


<s> return ( CONST_INT_P ( op1 ) && satisfies_constraint_eI ( op1 ) && ! satisfies_constraint_I ( op1 ) && ! satisfies_constraint_L ( op1 ) ) ; } if ( ! TARGET_PCREL || GET_MODE ( dest ) != Pmode ) return false ; if ( ! SYMBOL_REF_P ( src ) && ! LABEL_REF_P ( src ) &&

GET_CODE ( src ) != CONST ) return false ;


<s> const TargetRegisterClass * UseRC = ( RC == & <STR_LIT> ? & <STR_LIT> : ( RC == & <STR_LIT> ? & <STR_LIT> : RC


<s> Parser . Lex ( ) ; if ( ! parsePtrReg ( Operands , RegKind ) ) return MatchOperand_NoMatch ; if ( Parser . getTok ( ) . isNot ( AsmToken :: RParen ) ) return MatchOperand_NoMatch ; Operands . push_back ( <STR_LIT> ( <STR_LIT> , getLexer ( ) . getLoc ( ) ) ) ; Parser . Lex


<s> HasFRSQRTES = false ; HasRecipPrec = false ; HasSTFIWX = false ; HasLFIWAX = false ; HasFPRND = false ; HasFPCVT = false ; HasISEL = false ; HasBPERMD = false ; HasExtDiv = false ; HasCMPB = false ; HasLDBRX = false ; IsBookE = false ; HasOnlyMSYNC = false ; Is<ISA_LIT>4xx = false ; Is<ISA_LIT>6xx = false ; IsE500 = false ; FeatureMFTB = false ; DeprecatedDST =


<s> bool <ISA_LIT>DAGToDAGISel :: SelectMUBUFAddr64 ( SDValue Addr , SDValue & SRsrc , SDValue & VAddr , SDValue & SOffset , SDValue & Offset , SDValue & GLC , SDValue & SLC , SDValue & TFE ) const { SDValue Ptr , Offen , Idxen , Addr64 ; if ( Subtarget -> getGeneration ( ) >= <ISA_LIT>Subtarget :: VOLCANIC_ISLANDS ) return


<s> <ISA_LIT>Subtarget :: <ISA_LIT>Subtarget ( const Triple & TT , const std :: string & CPU , const std :: string & FS , const <ISA_LIT>TargetMachine & TM ) : <ISA_LIT>GenSubtargetInfo ( TT , CPU , FS ) , InstrInfo ( ) , FrameLowering ( ) , TLInfo ( TM , initializeSubtargetDependencies ( CPU , FS , TM ) ) , TSInfo ( ) , m_hasSRAM ( false ) , m_hasJMPCALL ( false ) , m_hasIJMPCALL ( false ) , m_hasEIJMPCALL ( false ) , m_hasADDSUBIW ( false ) , m_hasSmallStack ( false ) , m_hasMOVW ( false ) , m_hasLPM ( false ) , m_hasLPMX ( false ) , m_hasELPM ( false ) , m_hasELPMX ( false ) , m_hasSPM ( false ) , m_hasSPMX ( false ) , m_hasDES ( false ) , m_supportsRMW ( false ) , m_supportsMultiplication ( false ) , m_hasBREAK ( false ) , m_hasTinyEncoding ( false ) , ELFArch ( false ) , m_FeatureSetDummy ( false ) { ParseSubtargetFeatures ( CPU


<s> static Constant * SegmentOffset ( IRBuilder < > & IRB , int Offset , unsigned AddressSpace ) { return ConstantExpr :: getIntToPtr ( ConstantInt :: get ( Type :: getInt32Ty ( IRB . getContext ( ) ) , Offset ) ,

Type :: getInt8PtrTy ( IRB . getContext ( ) ) -> getPointerTo ( AddressSpace ) ) ;


<s> ret . val [ <NUM_LIT> ] = ( uint32x2_t ) __builtin_aarch64_get_dregoiv2si ( __o , <NUM_LIT> ) ; return


<s> assert ( Kind != VK_<ISA_LIT>Z80_None ) ; if ( isNegated ( ) ) OS << '-' ; OS << getName ( ) << '(' ; getSubExpr ( ) -> print ( OS , MAI ) ; OS <<


<s> } if ( ( Opcode == Instruction :: ZExt || Opcode == Instruction :: SExt ) && Src -> isIntegerTy ( <NUM_LIT> ) ) { if ( ST -> hasLoadStoreOnCond2 ( ) ) return <NUM_LIT> ; unsigned Cost = <NUM_LIT> ; if ( Opcode == Instruction :: SExt ) Cost = ( DstScalarBits < <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ) ; if ( Opcode == Instruction :: ZExt ) Cost = <NUM_LIT> ; Type * CmpOpTy = ( ( I != nullptr ) ? getCmpOpsType ( I ) : nullptr ) ; if ( CmpOpTy != nullptr && CmpOpTy -> isFloatingPointTy ( ) ) Cost ++ ; return Cost ; } } else if ( ST -> hasVector ( ) ) { auto * SrcVecTy = cast < FixedVectorType > ( Src ) ; auto * DstVecTy = cast < FixedVectorType > ( Dst ) ; unsigned VF = SrcVecTy -> getNumElements ( ) ; unsigned NumDstVectors = getNumVectorRegs ( Dst ) ; unsigned NumSrcVectors = getNumVectorRegs ( Src ) ; if ( Opcode == Instruction :: Trunc ) { if ( Src -> getScalarSizeInBits ( ) == Dst -> getScalarSizeInBits ( ) ) return <NUM_LIT> ; return getVectorTruncCost ( Src , Dst ) ; } if ( Opcode == Instruction :: ZExt || Opcode == Instruction :: SExt ) { if ( SrcScalarBits >= <NUM_LIT> ) { unsigned NumUnpacks = getElSizeLog2Diff ( Src , Dst ) ; unsigned NumSrcVectorOps = ( NumUnpacks > <NUM_LIT> ? ( NumDstVectors - NumSrcVectors ) : ( NumDstVectors / <NUM_LIT> ) ) ; return ( NumUnpacks * NumDstVectors ) + NumSrcVectorOps ; } else if ( SrcScalarBits == <NUM_LIT> ) return getBoolVecToIntConversionCost ( Opcode , Dst , I ) ; } if ( Opcode == Instruction :: SIToFP || Opcode == Instruction :: UIToFP || Opcode == Instruction :: FPToSI || Opcode == Instruction :: FPToUI ) { if ( DstScalarBits == <NUM_LIT> || ST -> hasVectorEnhancements2 ( ) ) { if ( SrcScalarBits == DstScalarBits ) return NumDstVectors ; if ( SrcScalarBits == <NUM_LIT> ) return getBoolVecToIntConversionCost ( Opcode , Dst , I ) + NumDstVectors ; } unsigned ScalarCost = getCastInstrCost ( Opcode , Dst -> getScalarType ( ) , Src -> getScalarType ( ) , CostKind ) ; unsigned TotCost = VF * ScalarCost ; bool NeedsInserts = true , NeedsExtracts = true ; if ( DstScalarBits == <NUM_LIT> && ( Opcode == Instruction :: SIToFP || Opcode == Instruction :: UIToFP ) ) NeedsInserts = false ; if ( SrcScalarBits == <NUM_LIT> && ( Opcode == Instruction :: FPToSI || Opcode == Instruction :: FPToUI ) ) NeedsExtracts = false ; TotCost += getScalarizationOverhead ( SrcVecTy , false , NeedsExtracts ) ; TotCost += getScalarizationOverhead ( DstVecTy , NeedsInserts , false ) ; if ( VF == <NUM_LIT> && SrcScalarBits == <NUM_LIT>

&& DstScalarBits == <NUM_LIT> ) TotCost *= <NUM_LIT> ;


<s> const TargetInstrInfo * TII = MF -> getSubtarget ( ) . getInstrInfo ( ) ; MachineRegisterInfo & RegInfo = MF -> getRegInfo ( ) ; * TLSBaseAddrReg = RegInfo . createVirtualRegister ( & <STR_LIT> ) ; MachineInstr * Copy = BuildMI ( * I . getParent ( ) , ++ I . getIterator ( ) , I . getDebugLoc ( ) , TII -> get (

TargetOpcode :: COPY ) , * TLSBaseAddrReg ) . addReg ( <STR_LIT> ) ;


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: createReg (


<s> bool inRegion ( MachineBasicBlock * MBB ) const { return Blocks . count


<s> std :: unique_ptr < MCObjectWriter > llvm :: create<ISA_LIT>ELFObjectWriter ( raw_pwrite_stream & OS , bool IsELF64 , uint8_t OSABI


<s> static DecodeStatus DecodetGPREvenRegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t


<s> if ( rs6000_sched_costly_dep == store_to_load_dep_costly && is_load_insn ( next , & load_mem ) && is_store_insn ( insn , & str_mem ) ) return true ; if ( rs6000_sched_costly_dep == true_store_to_load_dep_costly && is_load_insn ( next , & load_mem ) && is_store_insn ( insn , & str_mem ) && DEP_TYPE ( dep ) == REG_DEP_TRUE && mem_locations_overlap ( str_mem , load_mem ) ) return true ; if ( rs6000_sched_costly_dep <= max_dep_latency && ( ( cost - distance ) >= ( int ) rs6000_sched_costly_dep ) ) return true ; return false


<s> switch ( Opc ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; } return false


<s> MachineBasicBlock :: iterator Insert = Entry . front ( ) ; DebugLoc DL = Insert -> getDebugLoc ( ) ; TIDReg = RI . findUnusedRegister ( MF -> getRegInfo ( ) , & <STR_LIT> , * MF ) ; if ( TIDReg == <STR_LIT> ) return TIDReg ; if ( ! <STR_LIT> ( MF -> getFunction ( ) -> getCallingConv ( ) ) && WorkGroupSize > WavefrontSize ) { unsigned TIDIGXReg = TRI -> getPreloadedValue ( * MF , <ISA_LIT>RegisterInfo :: WORKGROUP_ID_X ) ; unsigned TIDIGYReg = TRI -> getPreloadedValue ( * MF , <ISA_LIT>RegisterInfo :: WORKGROUP_ID_Y ) ; unsigned TIDIGZReg = TRI -> getPreloadedValue ( * MF , <ISA_LIT>RegisterInfo :: WORKGROUP_ID_Z ) ; unsigned InputPtrReg = TRI -> getPreloadedValue ( * MF , <ISA_LIT>RegisterInfo :: KERNARG_SEGMENT_PTR ) ; for ( unsigned Reg : { TIDIGXReg , TIDIGYReg , TIDIGZReg } ) { if ( ! Entry . isLiveIn ( Reg ) ) Entry . addLiveIn ( Reg ) ; } RS -> enterBasicBlock ( Entry ) ; unsigned STmp0 = RS -> scavengeRegister ( & <STR_LIT> , <NUM_LIT> ) ; unsigned STmp1 = RS -> scavengeRegister ( & <STR_LIT> , <NUM_LIT> ) ; BuildMI ( Entry , Insert , DL , get ( <STR_LIT> ) , STmp0 ) . addReg ( InputPtrReg ) . addImm ( <STR_LIT> :: NGROUPS_Z ) ; BuildMI ( Entry , Insert , DL , get ( <STR_LIT> ) , STmp1 ) . addReg ( InputPtrReg ) . addImm ( <STR_LIT> :: NGROUPS_Y ) ; BuildMI ( Entry , Insert , DL , get ( <STR_LIT> ) , STmp1 ) . addReg ( STmp1 ) . addReg ( STmp0 ) ; BuildMI ( Entry , Insert , DL , get ( <STR_LIT> ) , TIDReg ) . addReg ( STmp1 ) . addReg ( TIDIGXReg ) ; BuildMI ( Entry , Insert , DL , get ( <STR_LIT> ) , TIDReg ) . addReg ( STmp0 ) . addReg ( TIDIGYReg ) . addReg ( TIDReg ) ; BuildMI ( Entry , Insert , DL , get ( <STR_LIT> ) , TIDReg ) . addReg ( TIDReg ) . addReg ( TIDIGZReg ) ; } else { BuildMI ( Entry , Insert , DL , get ( <STR_LIT> ) , TIDReg ) . addImm ( - <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; BuildMI ( Entry , Insert , DL , get ( <STR_LIT> ) , TIDReg ) . addImm ( - <NUM_LIT> ) . addReg ( TIDReg ) ; } BuildMI ( Entry , Insert , DL , get ( <STR_LIT> ) , TIDReg ) . addImm ( <NUM_LIT> ) . addReg ( TIDReg ) ; MFI -> setTIDReg ( TIDReg ) ; } unsigned LDSOffset = MFI -> LDSSize + ( FrameOffset * WorkGroupSize ) ; BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , TmpReg ) .

addImm ( LDSOffset ) . addReg ( TIDReg ) ;


<s> ArgInfo . PrivateSegmentWaveByteOffset = ArgDescriptor ::


<s> return new <ISA_LIT>MCCodeEmitter ( MCII , Ctx , false


<s> static std :: string getEdgeAttributes ( const SUnit * Node , SUnitIterator EI , const ScheduleDAG * Graph ) { if ( EI . isArtificialDep ( ) ) return <STR_LIT> ; if ( EI . isCtrlDep ( )


<s> if ( Op . isImm ( ) ) { int64_t Imm = Op . getImm ( ) * <NUM_LIT> + <NUM_LIT> ; O << <STR_LIT> ; if ( Imm >= <NUM_LIT> ) O << '+' ; O << Imm


<s> unsigned getDefaultFormatEncoding ( const MCSubtargetInfo & STI ) { if ( isGFX10 ( STI ) ) return UFMT_DEFAULT ; return DFMT_NFMT_DEFAULT


<s> int GCNHazardRecognizer :: getWaitStatesSinceSetReg ( IsHazardFn IsHazard , int Limit ) { auto IsHazardFn = [ IsHazard ] ( const MachineInstr & MI ) { return isSSetReg ( MI . getOpcode ( ) ) &&


<s> bool <ISA_LIT>TargetLowering :: isZExtFree ( SDValue Val , EVT VT2 ) const { if ( Val . getOpcode ( ) != <STR_LIT> ) return false ; EVT VT1 = Val . getValueType ( ) ; if ( ! VT1 . isSimple ( ) || ! VT1 . isInteger ( ) || ! VT2 . isSimple ( ) || ! VT2 . isInteger ( ) ) return false ; switch ( VT1 . getSimpleVT ( ) . SimpleTy ) { default : break ; case <STR_LIT> : return true ; } return


<s> bool fixupNeedsRelaxation ( const MCFixup & Fixup , uint64_t Value , const MCRelaxableFragment * DF , const MCAsmLayout & Layout ) const override { return false


<s> StartLoc = Tok . getLoc ( ) ; EndLoc = Tok . getEndLoc ( ) ; RegNo = <NUM_LIT> ; if ( getLexer ( ) . getKind ( ) != AsmToken :: Percent ) return MatchOperand_NoMatch ; Parser . Lex ( ) ; RegNo = parseRegisterName ( & MatchRegisterName ) ; if ( RegNo == <STR_LIT> ) RegNo = parseRegisterName ( & MatchRegisterAltName ) ; if ( RegNo != <STR_LIT> ) { Parser . Lex ( ) ; return MatchOperand_Success ; } getLexer ( ) . UnLex ( Tok ) ; return


<s> MCFixupKindInfo Info = getFixupKindInfo ( Fixup . getKind ( ) ) ; if ( ! Value ) return ; Value = adjustFixupValue ( Fixup , Value , Ctx ) ; Value <<= Info . TargetOffset ; unsigned Offset = Fixup . getOffset ( ) ; unsigned NumBytes = ( Info . TargetSize + <NUM_LIT> ) / <NUM_LIT> ; assert ( Offset + NumBytes <= Data . size ( ) && <STR_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i != <NUM_LIT> ; ++ i ) { Data [ Offset + i ] |= uint8_t ( ( Value >>


<s> void addRegOperands ( MCInst & Inst , unsigned N


<s> AU . addRequired < MachineModuleInfo > ( ) ; MachineFunctionPass :: getAnalysisUsage


<s> if ( from == ARG_POINTER_REGNUM ) offset = n_regs_saved_by_prologue ( ) * <NUM_LIT> ; if ( to == STACK_POINTER_REGNUM ) { if ( crtl -> outgoing_args_size >= FIXED_STACK_AREA ) offset += crtl -> outgoing_args_size ; else if ( crtl -> outgoing_args_size ) offset += FIXED_STACK_AREA ; offset += get_frame_size ( ) ; } return offset


<s> printS16ImmOperand ( MI , OpNo ) ; } else { if ( Subtarget . isDarwin ( ) ) O << <STR_LIT> ; printOp ( MI -> getOperand (


<s> if ( fun -> machine -> base_reg ) emit_insn_at_entry ( gen_main_pool ( fun -> machine -> base_reg ) ) ; for ( insn = get_insns ( ) ; insn ; insn = NEXT_INSN ( insn ) ) if (


<s> double getCriticality ( const MachineBasicBlock * MBB , double Default = - <NUM_LIT>


<s> bool <ISA_LIT>AsmParser :: parseSwizzleOffset ( int64_t & Imm ) { SMLoc OffsetLoc = getLoc ( ) ; if ( ! parseExpr ( Imm , <STR_LIT> ) ) { return false ; } if ( ! isUInt < <NUM_LIT> > ( Imm ) ) { Error ( OffsetLoc , <STR_LIT>


<s> bool <ISA_LIT>Subtarget :: GVIsIndirectSymbol ( GlobalValue * GV , Reloc :: Model RelocM ) const { if ( RelocM == Reloc :: Static ) return false ; bool isDecl = GV -> isDeclaration ( ) && ! GV -> isMaterializable ( ) ; if ( ! isTargetDarwin ( ) ) { if ( GV -> hasLocalLinkage ( ) || GV -> hasHiddenVisibility ( ) ) return false ; return true ; }


<s> Value * opr1 = CI -> getArgOperand ( <NUM_LIT> ) ; ConstantFP * CF0 = dyn_cast < ConstantFP > ( opr0 ) ; ConstantFP * CF1 = dyn_cast < ConstantFP > ( opr1 ) ; if ( ( CF0 && CF1 ) || ( CF1 && ( getArgType ( FInfo ) == <ISA_LIT>LibFunc :: F32 ) ) ) { Value * nval1 = B . CreateFDiv ( ConstantFP :: get ( opr1 -> getType ( ) , <NUM_LIT> ) , opr1 , <STR_LIT> ) ; Value * nval = B . CreateFMul ( opr0 , nval1 , <STR_LIT> ) ; replaceCall ( nval ) ; return true ; } return


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) : LLVMTargetMachine ( T , TT , CPU , computeFSAdditions ( FS , OL , TT ) , Options , RM , CM , OL ) , TLOF ( createTLOF ( Triple ( getTargetTriple ( ) ) ) ) , Subtarget ( TT , CPU , TargetFS , * this ) { initAsmInfo (


<s> return ( __m256i ) __builtin_ia32_vpdpbssds256 ( ( __v8si ) __W , ( __v8si )


<s> void <ISA_LIT>RegisterInfo :: lowerVRSAVERestore ( MachineBasicBlock :: iterator II , unsigned FrameIndex ) const { MachineInstr & MI = * II ; MachineBasicBlock & MBB = * MI . getParent ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; const TargetInstrInfo & TII = * Subtarget . getInstrInfo ( ) ; DebugLoc dl = MI . getDebugLoc ( ) ; const TargetRegisterClass * GPRC = & <STR_LIT> ; unsigned Reg = MF . getRegInfo ( ) . createVirtualRegister ( GPRC ) ; unsigned DestReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; assert ( MI . definesRegister ( DestReg ) && <STR_LIT>


<s> if ( ABI == <STR_LIT> && ( Type == <STR_LIT> ) ) return false ; return


<s> static SDValue combineFaddFsub ( SDNode * N , SelectionDAG & DAG , const <ISA_LIT>Subtarget & Subtarget ) { EVT VT = N -> getValueType ( <NUM_LIT> ) ; SDValue LHS = N -> getOperand ( <NUM_LIT> ) ; SDValue RHS = N -> getOperand ( <NUM_LIT> ) ; bool IsFadd = N ->


<s> return ( spu_sel ( a , b , spu_cmpgt ( a , b


<s> } const TargetRegisterClass * RC = & <STR_LIT> ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; EHSpillSlot [ <NUM_LIT> ] = MFI -> CreateStackObject ( RC -> getSize ( ) , RC -> getAlignment ( ) , true ) ; EHSpillSlot [ <NUM_LIT> ] = MFI -> CreateStackObject ( RC -> getSize ( ) ,


<s> write ( <NUM_LIT> , msg , sizeof ( msg ) - <NUM_LIT> ) ; _exit ( - <NUM_LIT> ) ; } monitor ( & stext , & etext , monitor_buffer , len , <NUM_LIT> ) ; atexit (


<s> return false ; } auto Addr = selectFlatOffsetImpl ( AddrOp , <STR_LIT> ) ; Register Data = DataOp . getReg ( ) ; const unsigned Opc = MRI -> getType ( Data ) . isVector ( ) ? <STR_LIT> : <STR_LIT> ; auto MIB = BuildMI ( * MBB , & MI , DL , TII . get ( Opc ) ) . addReg ( Addr . first ) . addReg ( Data ) . addImm ( Addr . second ) . addImm ( <NUM_LIT> ) . cloneMemRefs ( MI ) ; MI . eraseFromParent ( ) ; return constrainSelectedInstRegOperands ( * MIB , TII ,


<s> return true ; case ELF :: R_MIPS_CHERI_SETTAG : case ELF :: R_MIPS_CHERI_SETTAG_LOADADDR : case ELF :: R_MIPS_CHERI_LOCAL_CAPABILITY : case ELF :: R_MIPS_CHERI_GLOBALS_TABLE : llvm_unreachable ( <STR_LIT> ) ; return true ; case ELF :: R_MIPS_CHERI_CAPTABLEREL16 : return true ; case ELF :: R_MIPS_REL32 : case ELF :: R_MIPS_LITERAL : case ELF :: R_MIPS_CALL16 : case ELF :: R_MIPS_SHIFT5 : case ELF :: R_MIPS_SHIFT6 : case ELF :: R_MIPS_GOT_DISP : case ELF :: R_MIPS_GOT_HI16 : case ELF :: R_MIPS_GOT_LO16 : case ELF :: R_MIPS_INSERT_A : case ELF :: R_MIPS_INSERT_B : case ELF :: R_MIPS_DELETE : case ELF :: R_MIPS_CALL_HI16 : case ELF :: R_MIPS_CALL_LO16 : case ELF :: R_MIPS_SCN_DISP : case ELF :: R_MIPS_REL16 : case ELF :: R_MIPS_ADD_IMMEDIATE : case ELF :: R_MIPS_PJUMP : case ELF :: R_MIPS_RELGOT : case ELF :: R_MIPS_JALR : case ELF :: R_MIPS_TLS_DTPMOD32 : case ELF :: R_MIPS_TLS_DTPREL32 : case ELF :: R_MIPS_TLS_DTPMOD64 : case ELF :: R_MIPS_TLS_DTPREL64 : case ELF :: R_MIPS_TLS_GD : case ELF :: R_MIPS_TLS_LDM : case ELF :: R_MIPS_TLS_DTPREL_HI16 : case ELF :: R_MIPS_TLS_DTPREL_LO16 : case ELF :: R_MIPS_TLS_GOTTPREL : case ELF :: R_MIPS_TLS_TPREL32 : case ELF :: R_MIPS_TLS_TPREL64 : case ELF :: R_MIPS_TLS_TPREL_HI16 : case ELF :: R_MIPS_TLS_TPREL_LO16 : case ELF :: R_MIPS_GLOB_DAT : case ELF :: R_MIPS_PC21_S2 : case ELF :: R_MIPS_PC26_S2 : case ELF :: R_MIPS_PC18_S3 : case ELF :: R_MIPS_PC19_S2 : case ELF :: R_MIPS_PCHI16 : case ELF :: R_MIPS_PCLO16 : case ELF :: R_MIPS_COPY : case ELF :: R_MIPS_JUMP_SLOT : case ELF :: R_MIPS_NUM : case ELF :: R_MIPS_PC32 : case ELF :: R_MIPS_EH : case ELF :: R_MICROMIPS_26_S1 : case ELF :: R_MICROMIPS_GPREL16 : case ELF :: R_MICROMIPS_LITERAL : case ELF :: R_MICROMIPS_PC7_S1 : case ELF :: R_MICROMIPS_PC10_S1 : case ELF :: R_MICROMIPS_PC16_S1 : case ELF :: R_MICROMIPS_CALL16 : case ELF :: R_MICROMIPS_GOT_DISP : case ELF :: R_MICROMIPS_GOT_HI16 : case ELF :: R_MICROMIPS_GOT_LO16 : case ELF :: R_MICROMIPS_SUB : case ELF :: R_MICROMIPS_HIGHER : case ELF :: R_MICROMIPS_HIGHEST : case ELF :: R_MICROMIPS_CALL_HI16 : case ELF :: R_MICROMIPS_CALL_LO16 : case ELF :: R_MICROMIPS_SCN_DISP : case ELF :: R_MICROMIPS_JALR : case ELF :: R_MICROMIPS_HI0_LO16 : case ELF :: R_MICROMIPS_TLS_GD : case ELF :: R_MICROMIPS_TLS_LDM : case ELF ::


<s> return ( TARGET_ISA_V3 && ( ival < <NUM_LIT> ) && satisfies_constraint_Iu15 ( gen_int_mode (


<s> static bool spillsVRSAVE ( const MachineFunction & MF ) { const <ISA_LIT>FunctionInfo * FuncInfo = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; return FuncInfo ->


<s> case <STR_LIT> : { if ( cast < VTSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getVT ( ) == <STR_LIT> ) KnownZero = <NUM_LIT> ; break ; } case <STR_LIT> : { switch ( cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ) { default : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case


&& INT_REG_OK_FOR_BASE_P ( x , strict ) ;


<s> static SDValue PerformShiftCombine ( SDNode * N , SelectionDAG & DAG , TargetLowering :: DAGCombinerInfo & DCI , const <ISA_LIT>Subtarget * Subtarget ) { if ( N -> getOpcode ( ) == <STR_LIT> ) if ( SDValue V = PerformSHLCombine ( N , DAG ) ) return V ; if ( N -> getOpcode ( ) == <STR_LIT> ) if ( SDValue V = PerformSRACombine ( N , DAG ) ) return V ; if ( N -> getOpcode ( ) != <STR_LIT> ) if ( SDValue V =

performShiftToAllZeros ( N , DAG , Subtarget ) ) return V ;


<s> <ISA_LIT>Gfx7CacheControl ( const GCNSubtarget & ST ) :


<s> void setShouldRestoreSPFromFP ( bool


<s> MIB . addReg ( Addr . getReg ( ) ) . add ( predOps ( <STR_LIT> ) ) ; unsigned CMPrr = IsThumb ? <STR_LIT> : <STR_LIT> ; BuildMI ( LoadCmpBB , DL , TII -> get ( CMPrr ) ) . addReg ( DestLo , getKillRegState ( Dest . isDead ( ) ) ) . addReg ( DesiredLo , getKillRegState ( Desired . isDead ( ) ) ) . add ( predOps ( <STR_LIT> ) ) ; BuildMI ( LoadCmpBB , DL , TII -> get ( CMPrr ) ) . addReg ( DestHi , getKillRegState ( Dest . isDead ( ) ) ) . addReg ( DesiredHi , getKillRegState ( Desired . isDead ( ) ) ) . addImm ( <STR_LIT> ) . addReg ( <STR_LIT> , RegState :: Kill ) ; unsigned Bcc = IsThumb ? <STR_LIT> : <STR_LIT> ; BuildMI ( LoadCmpBB , DL , TII -> get ( Bcc ) ) . addMBB ( DoneBB ) . addImm ( <STR_LIT> ) . addReg ( <STR_LIT> , RegState :: Kill ) ; LoadCmpBB -> addSuccessor ( DoneBB ) ; LoadCmpBB -> addSuccessor ( StoreBB ) ; StoreBB -> addLiveIn ( Addr . getReg ( ) ) ; StoreBB -> addLiveIn ( New . getReg ( ) ) ; addPostLoopLiveIns ( StoreBB , LiveRegs ) ; unsigned STREXD = IsThumb ? <STR_LIT> : <STR_LIT> ; MIB = BuildMI ( StoreBB , DL , TII -> get ( STREXD ) , StatusReg ) ; addExclusiveRegPair ( MIB , New , <NUM_LIT> , IsThumb , TRI ) ; MIB . add ( Addr ) . add ( predOps ( <STR_LIT> ) ) ; unsigned CMPri = IsThumb ? <STR_LIT> : <STR_LIT> ; BuildMI ( StoreBB , DL , TII -> get ( CMPri ) ) . addReg ( StatusReg , RegState :: Kill ) . addImm ( <NUM_LIT> ) . add ( predOps ( <STR_LIT> ) ) ; BuildMI ( StoreBB , DL , TII -> get ( Bcc ) ) . addMBB ( LoadCmpBB ) . addImm ( <STR_LIT> ) . addReg ( <STR_LIT> , RegState :: Kill ) ; StoreBB -> addSuccessor ( LoadCmpBB ) ; StoreBB -> addSuccessor ( DoneBB ) ; DoneBB -> splice ( DoneBB -> end ( ) , & MBB , MI , MBB . end ( ) ) ; DoneBB -> transferSuccessors ( & MBB


<s> lowerADD ( SDValue Op , SelectionDAG & DAG )


<s> StringRef getPassName ( ) const override { return <STR_LIT>


<s> VectorEntry . getOperand ( <NUM_LIT> ) , VectorEntry . getOperand ( <NUM_LIT> ) , VectorEntry . getOperand ( <NUM_LIT> ) , VectorEntry . getOperand ( <NUM_LIT> ) } ; for ( unsigned i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) { if ( ConstantFPSDNode * C = dyn_cast < ConstantFPSDNode > ( NewBldVec [ i ] ) ) { if ( C -> isZero ( ) ) { RemapSwizzle [ i ] = <NUM_LIT> ; NewBldVec [ i ] = DAG . getUNDEF ( <STR_LIT> ) ; } else if ( C -> isExactlyValue


<s> Expr = ShiftedImm . Val ; if ( Shift != <NUM_LIT> && Shift != <NUM_LIT> ) return false ; } else { Expr = getImm ( ) ; } <ISA_LIT>MCExpr :: VariantKind ELFRefKind ; MCSymbolRefExpr :: VariantKind DarwinRefKind ; int64_t Addend ; if ( <ISA_LIT>AsmParser :: classifySymbolRef ( Expr , ELFRefKind , DarwinRefKind , Addend ) ) { return DarwinRefKind == MCSymbolRefExpr :: VK_PAGEOFF || DarwinRefKind == MCSymbolRefExpr :: VK_TLVPPAGEOFF || ( DarwinRefKind == MCSymbolRefExpr :: VK_GOTPAGEOFF && Addend == <NUM_LIT> ) || ELFRefKind == <ISA_LIT>MCExpr :: VK_LO12 || ELFRefKind == <ISA_LIT>MCExpr :: VK_DTPREL_HI12 || ELFRefKind == <ISA_LIT>MCExpr :: VK_DTPREL_LO12 || ELFRefKind == <ISA_LIT>MCExpr :: VK_DTPREL_LO12_NC || ELFRefKind == <ISA_LIT>MCExpr :: VK_TPREL_HI12 || ELFRefKind == <ISA_LIT>MCExpr :: VK_TPREL_LO12 ||

ELFRefKind == <ISA_LIT>MCExpr :: VK_TPREL_LO12_NC || ELFRefKind == <ISA_LIT>MCExpr :: VK_TLSDESC_LO12 || ELFRefKind == <ISA_LIT>MCExpr :: VK_SECREL_HI12 || ELFRefKind == <ISA_LIT>MCExpr :: VK_SECREL_LO12 ;


<s> static void initializePassOnce ( PassRegistry & Registry ) { const char * Name = <STR_LIT> ; PassInfo * PI = new PassInfo ( Name , <STR_LIT> , & SelectionDAGISel :: ID , <NUM_LIT> , false , false ) ; Registry . registerPass ( * PI , true


<s> const <ISA_LIT>InstrInfo * TII = ST . getInstrInfo ( ) ; unsigned SuperReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; bool IsKill = MI -> getOperand ( <NUM_LIT> ) . isKill ( ) ; const DebugLoc & DL = MI -> getDebugLoc ( ) ; MachineFrameInfo & FrameInfo = MF -> getFrameInfo ( ) ; bool SpillToSMEM = spillSGPRToSMEM ( ) ; if ( SpillToSMEM && OnlyToVGPR ) return false ; assert ( SuperReg != <STR_LIT> && <STR_LIT> ) ; unsigned OffsetReg = <STR_LIT> ; unsigned M0CopyReg = <STR_LIT> ; if ( SpillToSMEM ) { if ( RS -> isRegUsed ( <STR_LIT> ) ) { M0CopyReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * MBB , MI , DL , TII -> get ( <STR_LIT> ) , M0CopyReg ) . addReg ( <STR_LIT> ) ; } } unsigned ScalarStoreOp ; unsigned EltSize = <NUM_LIT> ; const TargetRegisterClass * RC = getPhysRegClass ( SuperReg ) ; if ( SpillToSMEM && isSGPRClass ( RC ) ) { std :: tie ( EltSize , ScalarStoreOp ) = getSpillEltSize ( RC -> getSize ( ) , true ) ; } ArrayRef < int16_t > SplitParts = getRegSplitParts ( RC , EltSize ) ; unsigned NumSubRegs = SplitParts . empty ( ) ? <NUM_LIT> : SplitParts . size ( ) ; unsigned SubKillState = getKillRegState ( ( NumSubRegs == <NUM_LIT> ) && IsKill ) ; for ( unsigned i = <NUM_LIT> , e = NumSubRegs ; i < e ; ++ i ) { unsigned SubReg = NumSubRegs == <NUM_LIT> ? SuperReg : getSubReg ( SuperReg , SplitParts [ i ] ) ; if ( SpillToSMEM ) { int64_t FrOffset = FrameInfo . getObjectOffset ( Index ) ; unsigned Align = FrameInfo .


<s> if ( AS != <ISA_LIT>AS :: CONSTANT_ADDRESS && AS != <ISA_LIT>AS :: CONSTANT_ADDRESS_32BIT ) return false ; if ( ! LI . isSimple ( ) ) return false ; auto * Ty = LI . getType ( ) ; if ( Ty -> isAggregateType ( ) ) return false ; unsigned TySize = DL -> getTypeStoreSize ( Ty ) ; if ( TySize >= <NUM_LIT> )


<s> static unsigned int nvptx_hard_regno_nregs ( unsigned int , machine_mode ) { return <NUM_LIT>


<s> SDValue <ISA_LIT>cc ; SDValue CCR = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; assert ( Op . getOpcode ( ) == <STR_LIT> ) ; SDValue RevShAmt = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getConstant ( VTBits , dl , <STR_LIT> ) , ShAmt ) ; SDValue Tmp1 = DAG . getNode ( <STR_LIT> , dl , VT , ShOpLo , RevShAmt ) ; SDValue Tmp2 = DAG . getNode ( <STR_LIT> , dl , VT , ShOpHi , ShAmt ) ; SDValue HiSmallShift = DAG . getNode ( <STR_LIT> , dl , VT , Tmp1 , Tmp2 ) ; SDValue ExtraShAmt = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , ShAmt , DAG

. getConstant ( VTBits , dl , <STR_LIT> ) ) ;


<s> return CmpMode :: EQ ; case <STR_LIT> : return CmpMode :: GT ; case <STR_LIT> : return CmpMode :: GE ; case <STR_LIT> : return CmpMode :: LT ; case <STR_LIT> : return CmpMode :: LE ; case <STR_LIT> : return CmpMode :: NE ; case <STR_LIT> : return CmpMode :: NUM ; case <STR_LIT> : return CmpMode :: NotANumber ; case <STR_LIT> : return CmpMode :: EQU ; case <STR_LIT> : return CmpMode :: GTU ; case <STR_LIT> : return CmpMode :: GEU ; case <STR_LIT> : return CmpMode :: LTU ; case <STR_LIT> : return CmpMode :: LEU ; case <STR_LIT> : return CmpMode :: NEU ; case <STR_LIT> : return CmpMode :: EQ ; case <STR_LIT> : return CmpMode :: GT ; case <STR_LIT> : return CmpMode :: GE ; case <STR_LIT> : return CmpMode :: LT ; case <STR_LIT>


<s> if ( ET == <STR_LIT> && ( Op . getOpcode ( ) == <STR_LIT> || Op . getOpcode ( ) == <STR_LIT> ) && isOperationLegalOrCustom ( Op . getOpcode ( ) , Op . getOperand ( <NUM_LIT> ) . getValueType ( ) ) ) { LowerFP_TO_INTForReuse ( Op , RLI , DAG , dl ) ; return true ; } LoadSDNode * LD = dyn_cast < LoadSDNode > ( Op ) ; if ( ! LD || LD -> getExtensionType ( ) != ET || LD -> isVolatile ( ) || LD -> isNonTemporal ( ) ) return false ; if ( LD -> getMemoryVT ( ) != MemVT ) return false ; RLI . Ptr = LD -> getBasePtr ( ) ; if ( LD -> isIndexed ( ) && ! LD -> getOffset ( ) . isUndef ( ) ) { assert ( LD -> getAddressingMode ( ) == <STR_LIT> && <STR_LIT> ) ; RLI . Ptr = DAG . getNode ( <STR_LIT> , dl , RLI . Ptr . getValueType ( ) , RLI . Ptr , LD -> getOffset ( ) ) ; } RLI . Chain = LD -> getChain ( ) ; RLI . MPI = LD -> getPointerInfo ( ) ; RLI . IsDereferenceable = LD -> isDereferenceable ( ) ; RLI . IsInvariant = LD -> isInvariant ( ) ; RLI . Alignment = LD


<s> unsigned FirstGPR = ZFI -> getVarArgsFirstGPR ( ) ; if ( FirstGPR < <STR_LIT> ) { unsigned Reg = <STR_LIT> [ FirstGPR ] ; unsigned Offset = RegSpillOffsets [ Reg ] ; if ( StartOffset > Offset ) { LowGPR = Reg ; StartOffset = Offset ; } } } if ( LowGPR ) { assert ( LowGPR != HighGPR && <STR_LIT> ) ; MachineInstrBuilder MIB = BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) ) ; addSavedGPR ( MBB , MIB , LowGPR , false ) ; addSavedGPR ( MBB , MIB , HighGPR , false ) ; MIB . addReg ( <STR_LIT> ) . addImm ( StartOffset ) ; for ( unsigned I = <NUM_LIT> , E = CSI . size ( ) ; I != E ; ++ I ) { unsigned Reg = CSI [ I ] . getReg ( ) ; if ( <STR_LIT> . contains ( Reg ) ) addSavedGPR ( MBB , MIB , Reg , true ) ; } if ( IsVarArg ) for ( unsigned I = ZFI -> getVarArgsFirstGPR ( ) ; I < <STR_LIT> ; ++ I ) addSavedGPR ( MBB , MIB , <STR_LIT> [ I ] , true ) ; } for ( unsigned I = <NUM_LIT> , E = CSI . size ( ) ; I != E ; ++ I ) { unsigned Reg = CSI [ I ] . getReg ( ) ; if ( <STR_LIT> . contains ( Reg ) ) { MBB . addLiveIn (


<s> bool iss30_2Imm ( ) const { return true


<s> assert ( Begin != nullptr ) ; return


<s> rmap_ty :: iterator iter = RegisterMap . find ( Name . str ( ) ) ; if ( iter != RegisterMap . end ( ) ) return iter -> second ; else return


<s> case GK_REDWOOD : return ELF :: EF_AMDGPU_MACH_<ISA_LIT>_REDWOOD ; case GK_SUMO : return ELF :: EF_AMDGPU_MACH_<ISA_LIT>_SUMO ; case GK_BARTS : return ELF :: EF_AMDGPU_MACH_<ISA_LIT>_BARTS ; case GK_CAICOS : return ELF :: EF_AMDGPU_MACH_<ISA_LIT>_CAICOS ; case GK_CAYMAN : return ELF :: EF_AMDGPU_MACH_<ISA_LIT>_CAYMAN ; case GK_TURKS : return ELF :: EF_AMDGPU_MACH_<ISA_LIT>_TURKS ; case GK_GFX600 : return ELF :: EF_<ISA_LIT>_MACH_AMDGCN_GFX600 ; case GK_GFX601 : return ELF :: EF_<ISA_LIT>_MACH_AMDGCN_GFX601 ; case GK_GFX700 : return ELF :: EF_<ISA_LIT>_MACH_AMDGCN_GFX700 ; case GK_GFX701 : return ELF :: EF_<ISA_LIT>_MACH_AMDGCN_GFX701 ; case GK_GFX702 : return ELF :: EF_<ISA_LIT>_MACH_AMDGCN_GFX702 ; case GK_GFX703 : return ELF :: EF_<ISA_LIT>_MACH_AMDGCN_GFX703 ; case GK_GFX704 : return ELF :: EF_<ISA_LIT>_MACH_AMDGCN_GFX704 ; case GK_GFX801 : return ELF :: EF_<ISA_LIT>_MACH_AMDGCN_GFX801 ; case GK_GFX802 : return ELF


, ( __mmask16 ) __U , _MM_FROUND_CUR_DIRECTION ) ;


<s> unsigned getFramePtr ( ) const { return


<s> if ( width_source == SVE_SCALABLE ) return default_estimated_poly_value ( val ) ; HOST_WIDE_INT over_128 = width_source - <NUM_LIT> ; return val . coeffs [ <NUM_LIT> ] + val . coeffs [ <NUM_LIT> ] * over_128 /


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> bool Filler :: searchRange ( MachineBasicBlock & MBB , IterTy Begin , IterTy End , RegDefsUses & RegDU , InspectMemInstr & IM , Iter Slot , IterTy & Filler ) const { bool IsReverseIter = std :: is_convertible < IterTy , ReverseIter > :: value ; for ( IterTy I = Begin ; I != End ; ) { IterTy CurrI = I ; ++ I ; if ( CurrI -> isDebugValue ( ) ) continue ; if ( terminateSearch ( * CurrI ) ) break ; assert ( ( ! CurrI -> isCall ( ) && ! CurrI -> isReturn ( ) && ! CurrI -> isBranch ( ) ) && <STR_LIT> ) ; if ( CurrI -> isKill ( ) ) { CurrI -> eraseFromParent ( ) ; if ( IsReverseIter && I != End ) I = CurrI ; continue ; } if ( delayHasHazard ( * CurrI , RegDU , IM ) ) continue ; const <ISA_LIT>Subtarget & STI = MBB . getParent ( ) -> getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( STI . isTargetNaCl ( ) ) { unsigned AddrIdx ; if ( ( isBasePlusOffsetMemoryAccess ( CurrI -> getOpcode ( ) , & AddrIdx ) && baseRegNeedsLoadStoreMask ( CurrI -> getOperand ( AddrIdx ) . getReg ( ) ) ) || CurrI -> modifiesRegister ( <STR_LIT> , STI . getRegisterInfo ( ) ) ) continue ; } bool InMicro<ISA_LIT>Mode = STI .


<s> if ( hasFP ( MF ) ) { SavedRegs . set ( <STR_LIT> ) ; SavedRegs . set ( <STR_LIT>


<s> if ( STACK_REGNO_P ( regno ) ) return VALID_FP_MODE_P ( mode ) ; if ( MASK_REGNO_P ( regno ) ) return ( VALID_MASK_REG_MODE ( mode ) || ( TARGET_AVX512BW && VALID_MASK_AVX512BW_MODE ( mode ) ) ) ; if ( BND_REGNO_P ( regno ) ) return VALID_BND_REG_MODE ( mode ) ; if ( SSE_REGNO_P ( regno ) ) { if ( TARGET_AVX512F && ( mode == XImode || VALID_AVX512F_REG_MODE ( mode ) || VALID_AVX512F_SCALAR_MODE ( mode ) ) ) return true ; if ( ( TARGET_AVX5124FMAPS || TARGET_AVX5124VNNIW ) && MOD4_SSE_REGNO_P ( regno ) && mode == V64SFmode ) return true ; if ( ( TARGET_AVX5124FMAPS || TARGET_AVX5124VNNIW ) && MOD4_SSE_REGNO_P ( regno ) && mode == V64SImode ) return true ; if ( TARGET_AVX512VL && ( mode == OImode || mode == TImode || VALID_AVX256_REG_MODE ( mode ) || VALID_AVX512VL_128_REG_MODE ( mode ) ) ) return true ; if ( EXT_REX_SSE_REGNO_P ( regno ) ) return false ; return ( ( TARGET_AVX && VALID_AVX256_REG_OR_OI_MODE ( mode ) ) || VALID_SSE_REG_MODE ( mode ) || VALID_SSE2_REG_MODE ( mode ) || VALID_MMX_REG_MODE ( mode ) || VALID_MMX_REG_MODE_3DNOW ( mode ) ) ; } if ( MMX_REGNO_P ( regno ) ) { return ( VALID_MMX_REG_MODE ( mode ) || VALID_MMX_REG_MODE_3DNOW ( mode ) ) ; } if ( mode == QImode ) { if ( ANY_QI_REGNO_P ( regno ) ) return true ; if ( ! TARGET_PARTIAL_REG_STALL ) return true ; if ( lra_in_progress ) return true ; return ! can_create_pseudo_p ( ) ; } else if ( VALID_INT_MODE_P ( mode ) ) return true ; else if ( VALID_FP_MODE_P ( mode ) ) return true ; else if ( VALID_DFP_MODE_P ( mode ) ) return true ; else if ( VALID_MMX_REG_MODE_3DNOW ( mode ) || VALID_MMX_REG_MODE ( mode ) ) return true ; return false


<s> case TargetOpcode :: G_SITOFP : case TargetOpcode :: G_UITOFP : case TargetOpcode :: G_EXTRACT_VECTOR_ELT : case TargetOpcode :: G_INSERT_VECTOR_ELT : return true ; default : break ; } return hasFPConstraints ( MI , MRI , TRI , Depth


<s> unsigned getReg ( ) const override { assert ( ( Kind == k_Register ) && <STR_LIT> ) ; return Reg .


<s> Register R = Add -> getOperand ( <NUM_LIT> ) . getReg (


<s> unsigned <ISA_LIT>InstrInfo :: RemoveBranch ( MachineBasicBlock & MBB ) const { MachineBasicBlock :: iterator I = MBB . end ( ) ; if ( I == MBB . begin ( ) ) return <NUM_LIT> ; -- I ; if ( ! isCondBranch ( I ) &&

! isUncondBranch ( I ) ) return <NUM_LIT> ;


<s> bool <ISA_LIT>Subtarget :: hasLibcall ( const char * name )


<s> <ISA_LIT>Operand :: ImmTy OffsetType = ( Inst . getOpcode ( ) == <STR_LIT> || Inst . getOpcode ( ) == <STR_LIT> || Inst . getOpcode ( ) == <STR_LIT> ) ? <ISA_LIT>Operand :: ImmTySwizzle : <ISA_LIT>Operand :: ImmTyOffset ; addOptionalImmOperand ( Inst , Operands , OptionalIdx , OffsetType ) ; if ( ! IsGdsHardcoded ) { addOptionalImmOperand ( Inst , Operands ,

OptionalIdx , <ISA_LIT>Operand :: ImmTyGDS ) ;


<s> unsigned UseOpc = UseMI -> getOpcode ( ) ; unsigned NewUseOpc = <NUM_LIT> ; uint32_t ImmVal = ( uint32_t ) DefMI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; uint32_t SOImmValV1 = <NUM_LIT> , SOImmValV2 = <NUM_LIT> ; bool Commute = false ; switch ( UseOpc ) { default : return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { Commute = UseMI -> getOperand ( <NUM_LIT> ) . getReg ( ) != Reg ; switch ( UseOpc ) { default : break ; case <STR_LIT> : { if ( Commute ) return false ; ImmVal = - ImmVal ; NewUseOpc = <STR_LIT> ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { if ( ! <STR_LIT> ( ImmVal ) ) return false ; SOImmValV1 = ( uint32_t ) <STR_LIT> ( ImmVal ) ; SOImmValV2 = ( uint32_t ) <STR_LIT> ( ImmVal ) ; switch ( UseOpc ) { default : break ; case <STR_LIT> : NewUseOpc = <STR_LIT> ; break ; case <STR_LIT> : NewUseOpc = <STR_LIT> ; break ; case <STR_LIT> : NewUseOpc = <STR_LIT> ; break ; } break ; } case <STR_LIT> :


<s> DecodeStatus Result = readInstruction32 ( Bytes , Address , Size , Insn , IsBigEndian , false ) ; if ( Result == MCDisassembler :: Fail ) return MCDisassembler :: Fail ; Result = decodeInstruction ( DecoderTable<ISA_LIT>32 , Instr , Insn ,


<s> case ALTIVEC_BUILTIN_ST_INTERNAL_2df : icode = CODE_FOR_vector_altivec_store_v2df ; break ; case ALTIVEC_BUILTIN_ST_INTERNAL_2di : icode = CODE_FOR_vector_altivec_store_v2di ; case ALTIVEC_BUILTIN_ST_INTERNAL_1ti : icode = CODE_FOR_vector_altivec_store_v1ti ; break ; default : * expandedp = false ; return NULL_RTX ; } arg0 = CALL_EXPR_ARG ( exp , <NUM_LIT> ) ; arg1 = CALL_EXPR_ARG ( exp , <NUM_LIT> ) ; op0 = expand_normal ( arg0 ) ; op1 = expand_normal ( arg1 ) ; mode0 = insn_data [ icode ] . operand [ <NUM_LIT> ] . mode ; mode1 = insn_data [ icode ] . operand [ <NUM_LIT> ] . mode ; if ( ! ( * insn_data [ icode ] . operand [ <NUM_LIT> ] . predicate ) ( op0 , mode0 ) ) op0 = gen_rtx_MEM ( mode0 , copy_to_mode_reg ( Pmode , op0 ) ) ; if ( ! ( * insn_data [ icode ] . operand [ <NUM_LIT> ] . predicate ) ( op1 , mode1 ) ) op1 = copy_to_mode_reg ( mode1 , op1 ) ; pat = GEN_FCN ( icode ) ( op0 , op1 ) ; if ( pat ) emit_insn ( pat ) ; * expandedp = true ; return


<s> SDValue <ISA_LIT>TargetLowering :: LowerToTLSGeneralDynamicModel ( GlobalAddressSDNode * GA , SelectionDAG & DAG ) const { DebugLoc dl = GA -> getDebugLoc ( ) ; EVT PtrVT = getPointerTy ( ) ; unsigned char PCAdj = Subtarget -> isThumb ( ) ? <NUM_LIT> : <NUM_LIT> ; MachineFunction & MF = DAG . getMachineFunction ( ) ; <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; unsigned <ISA_LIT>PCLabelIndex = AFI -> createPICLabelUId ( ) ; <ISA_LIT>ConstantPoolValue * CPV = new <ISA_LIT>ConstantPoolValue ( GA -> getGlobal ( ) , <ISA_LIT>PCLabelIndex , <STR_LIT> , PCAdj , <STR_LIT> , true ) ; SDValue Argument = DAG . getTargetConstantPool ( CPV , PtrVT , <NUM_LIT> ) ; Argument = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Argument ) ; Argument = DAG . getLoad ( PtrVT , dl , DAG . getEntryNode ( ) , Argument , MachinePointerInfo :: getConstantPool ( ) , false , false , <NUM_LIT> ) ; SDValue Chain = Argument . getValue ( <NUM_LIT> ) ; SDValue PICLabel = DAG . getConstant ( <ISA_LIT>PCLabelIndex , <STR_LIT> ) ; Argument = DAG . getNode ( <STR_LIT> , dl , PtrVT , Argument , PICLabel ) ; ArgListTy Args ; ArgListEntry Entry ; Entry . Node = Argument ; Entry . Ty = ( const Type * ) Type :: getInt32Ty ( * DAG . getContext ( ) ) ; Args . push_back ( Entry ) ; std :: pair < SDValue , SDValue > CallResult = LowerCallTo ( Chain , ( const Type * ) Type :: getInt32Ty ( * DAG . getContext ( ) ) , false ,

false , false , false , <NUM_LIT> , CallingConv :: C , false , true , DAG . getExternalSymbol ( <STR_LIT> , PtrVT ) , Args , DAG , dl ) ;


<s> Val &= <NUM_LIT> ; return createRegOperand ( <STR_LIT> ,


<s> const MCConstantExpr * BranchTarget = dyn_cast < MCConstantExpr > ( Op . getExpr ( ) ) ; int64_t Address ; if ( BranchTarget && BranchTarget -> EvaluateAsAbsolute ( Address ) ) { O << <STR_LIT> ; O . write_hex ( Address ) ; } else { O << * Op . getExpr (


<s> for ( unsigned i = <NUM_LIT> , e = Outs . size ( ) ; i != e ; ++ i ) { MVT VT = Outs [ i ] . VT ; <STR_LIT> ArgFlags = Outs [ i ] . Flags ; <STR_LIT> ABI = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getTargetABI ( ) ; if ( CC_<ISA_LIT> ( MF . getDataLayout ( ) , ABI , i , VT , VT , CCValAssign :: Full , ArgFlags , CCInfo , true , true , nullptr , * this , FirstMaskArgument ) ) return false ; } return true


<s> return ( __m128i ) __builtin_ia32_cvtps2dq (


<s> void <ISA_LIT>InstPrinter :: printAddrMode2OffsetOperand ( const MCInst * MI , unsigned OpNum , raw_ostream & O ) { const MCOperand & MO1 = MI -> getOperand ( OpNum ) ; const MCOperand & MO2 = MI -> getOperand ( OpNum + <NUM_LIT> ) ; if ( ! MO1 . getReg ( ) ) { unsigned ImmOffs = <STR_LIT> ( MO2 . getImm ( ) ) ; O << markup ( <STR_LIT> ) << '#' << <STR_LIT> ( <STR_LIT> ( MO2 . getImm ( ) ) ) << ImmOffs << markup ( <STR_LIT> ) ; return ; } O << <STR_LIT> ( <STR_LIT> ( MO2 . getImm ( ) ) ) ; printRegName ( O , MO1 . getReg ( )


<s> return ( __m256 ) __builtin_ia32_loadaps256_mask ( ( __v8sf * ) __P , (


<s> static MCCodeGenInfo * create<ISA_LIT>MCCodeGenInfo ( const Triple & TT , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) { MCCodeGenInfo * X = new MCCodeGenInfo ( ) ; if ( RM == Reloc :: Default ) { RM = Reloc :: Static ; } if ( CM == CodeModel :: Default ) { CM = CodeModel :: Small ; } if ( CM != CodeModel :: Small && CM != CodeModel :: Large ) report_fatal_error ( <STR_LIT> ) ; X -> initMCCodeGenInfo ( RM , CM , OL ) ; return


<s> offset = CONST_LOW_PART ( offset ) ; high = riscv_force_temporary ( temp , high , FALSE ) ; reg = riscv_force_temporary ( temp , gen_rtx_PLUS ( Pmode , high ,


<s> case MCSymbolRefExpr :: VK_<ISA_LIT>_ABS_LO : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_TLSGD : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_TLSLDM : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_DTPREL_HI : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_DTPREL_LO : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOTTPREL : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_TPREL_HI : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_TPREL_LO : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GPOFF_HI : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GPOFF_LO : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_DISP : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_PAGE : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_OFST : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_HIGHER : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_HIGHEST : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_HI16 : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_LO16 : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_CALL_HI16 : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_CALL_LO16 : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_PCREL_HI16 : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_PCREL_LO16 : OS << <STR_LIT> ; break ; } SRE -> getSymbol ( ) . print ( OS , MAI ) ; if ( Offset ) { if ( Offset > <NUM_LIT> ) OS << '+' ; OS << Offset


<s> unsigned Op1 = getFPReg ( MI . getOperand ( <NUM_LIT> ) ) ; bool KillsOp1 = MI . killsRegister ( <STR_LIT> + Op1 ) ; moveToTop ( Op0 , I ) ; MI . RemoveOperand ( <NUM_LIT> ) ; MI . RemoveOperand ( <NUM_LIT> ) ; MI . getOperand ( <NUM_LIT> ) . setReg ( getSTReg


<s> if ( TARGET_MIPS16 ) { if ( ! mips16_rdhwr_stub ) mips16_rdhwr_stub = new mips16_rdhwr_one_only_stub ( ) ; fn = mips16_stub_call_address ( mips16_rdhwr_stub ) ; emit_insn ( PMODE_INSN ( gen_tls_get_tp_mips16 , ( tp , fn ) ) ) ; } else emit_insn ( PMODE_INSN ( gen_tls_get_tp , ( tp ) ) ) ; return tp


<s> if ( ! getBranchInfo ( * I ) . hasMBBTarget ( ) ) break ; I -> eraseFromParent ( ) ; I = MBB . end ( ) ; ++ Count ; } return Count


<s> static inline void __ev_clr_spefscr_field ( int mask ) { int i ; i = __builtin_spe_mfspefscr (


<s> static std :: unique_ptr < <ISA_LIT>Operand > CreateMSRMask ( unsigned MMask , SMLoc S ) { auto Op = make_unique < <ISA_LIT>Operand > ( k_MSRMask ) ; Op -> MMask . Val = MMask ; Op -> StartLoc = S ; Op -> EndLoc


<s> bool IsStore = Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ; if ( IsLoad || IsStore ) { MachineOperand & MO = MBBI -> getOperand ( MBBI -> getDesc ( ) . getNumOperands ( ) - <NUM_LIT> ) ; Offset = MO . getImm ( ) - WordOffset * getImmScale ( Opc ) ; unsigned InstrSrcReg = MBBI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( Offset >= <NUM_LIT> && ! ( IsStore && InstrSrcReg == Base ) ) MO . setImm ( Offset ) ; else InsertSub = true ; } else if ( ( Opc == <STR_LIT> || Opc == <STR_LIT> ) && ! definesCPSR ( MBBI ) ) { MachineOperand & MO = MBBI -> getOperand ( MBBI -> getDesc ( ) . getNumOperands ( ) - <NUM_LIT> ) ; Offset = ( Opc == <STR_LIT> ) ? MO . getImm ( ) + WordOffset * <NUM_LIT> : MO . getImm ( ) - WordOffset * <NUM_LIT> ; if ( Offset >= <NUM_LIT> && TL -> isLegalAddImmediate ( Offset ) ) { MO . setImm ( Offset ) ; return ; } else { InsertSub = true ; } } else { InsertSub = true ; } } else if ( definesCPSR ( MBBI ) || MBBI -> isCall ( ) || MBBI -> isBranch ( ) ) { InsertSub = true ; } if ( InsertSub )


<s> DebugLoc dl = Op . getDebugLoc ( ) ; unsigned Depth = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; SDValue FrameAddr = DAG . getCopyFromReg ( DAG . getEntryNode ( ) , dl , <STR_LIT> , VT ) ; while ( Depth -- ) FrameAddr = DAG . getLoad ( VT , dl , DAG . getEntryNode ( ) , FrameAddr , MachinePointerInfo ( ) , false , false , false , <NUM_LIT> ) ; return


<s> SDValue OpsY3 [ ] = { TmpY2 , TmpE2 , TmpY2 , TmpPR } ; TmpY3 = SDValue ( CurDAG -> getTargetNode ( <STR_LIT> , dl , <STR_LIT> , OpsY3 , <NUM_LIT> ) , <NUM_LIT> ) ; Chain = TmpY3 . getValue ( <NUM_LIT> ) ; SDValue OpsQ0 [ ] = { Tmp1 , TmpY3 , F0 , TmpPR } ; TmpQ0 = SDValue ( CurDAG -> getTargetNode ( <STR_LIT> , dl , <STR_LIT> , OpsQ0 , <NUM_LIT> ) , <NUM_LIT> ) ; Chain = TmpQ0 . getValue ( <NUM_LIT> ) ; SDValue OpsR0 [ ] = { Tmp2 , TmpQ0 , Tmp1 , TmpPR } ; TmpR0 = SDValue ( CurDAG -> getTargetNode ( <STR_LIT> , dl , <STR_LIT> , OpsR0 , <NUM_LIT> ) , <NUM_LIT> ) ; Chain = TmpR0 . getValue ( <NUM_LIT> ) ; SDValue Ops [ ] = { TmpF5 , TmpY3 , TmpR0 , TmpQ0 , TmpPR } ; Result = CurDAG -> getTargetNode ( <STR_LIT> , dl , <STR_LIT> , Ops , <NUM_LIT> ) ; Chain = SDValue ( Result , <NUM_LIT> ) ; return Result ; } else { SDValue TmpQ2 , TmpR2 , TmpQ3 , TmpQ ; SDValue OpsQ2 [ ] = { TmpF3 , TmpY2 , F0 , TmpPR } ; TmpQ2 = SDValue ( CurDAG -> getTargetNode ( <STR_LIT> , dl , <STR_LIT> , OpsQ2 , <NUM_LIT> ) , <NUM_LIT> ) ; Chain = TmpQ2 . getValue ( <NUM_LIT> ) ; SDValue OpsR2 [ ] = { TmpF4 , TmpQ2 , TmpF3 , TmpPR } ; TmpR2 = SDValue ( CurDAG -> getTargetNode ( <STR_LIT> , dl , <STR_LIT> , OpsR2 , <NUM_LIT> ) , <NUM_LIT> ) ; Chain = TmpR2 . getValue ( <NUM_LIT> ) ; SDValue OpsQ3 [ ] = { TmpF5 , TmpR2 , TmpY2 , TmpQ2 , TmpPR } ; TmpQ3 = SDValue ( CurDAG -> getTargetNode ( <STR_LIT> , dl , <STR_LIT> , OpsQ3 , <NUM_LIT> ) , <NUM_LIT> ) ; Chain = TmpQ3 . getValue ( <NUM_LIT> ) ; if ( isSigned ) TmpQ = SDValue ( CurDAG -> getTargetNode ( <STR_LIT> , dl , <STR_LIT> , TmpQ3 ) , <NUM_LIT> ) ; else TmpQ = SDValue ( CurDAG -> getTargetNode ( <STR_LIT> , dl , <STR_LIT> , TmpQ3 ) , <NUM_LIT> ) ; Chain = TmpQ . getValue ( <NUM_LIT> ) ; if ( isModulus ) { SDValue FPminusB = SDValue ( CurDAG -> getTargetNode ( <STR_LIT> , dl , <STR_LIT> , minusB ) , <NUM_LIT> ) ; Chain = FPminusB . getValue ( <NUM_LIT> ) ; SDValue Remainder = SDValue ( CurDAG -> getTargetNode ( <STR_LIT> , dl , <STR_LIT> , TmpQ , FPminusB , TmpF1 ) , <NUM_LIT> ) ; Chain = Remainder . getValue ( <NUM_LIT> ) ; Result = CurDAG -> getTargetNode ( <STR_LIT> , dl , <STR_LIT> , Remainder ) ; Chain = SDValue ( Result , <NUM_LIT> ) ; } else


<s> return MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; case <STR_LIT> : FrameIndex = MI . getOperand ( <NUM_LIT> ) . getIndex ( ) ; return MI . getOperand ( <NUM_LIT> ) .


<s> kernel_md_iterator kernel_md_end ( ) { return mMetadataKernel . end (


<s> void addGPRMM16AsmRegMovePPairFirstOperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT>


<s> for ( i = FIRST_SSE_REG ; i <= LAST_SSE_REG ; i ++ ) reg_alloc_order [ pos ++ ] = i ; for ( i = FIRST_REX_SSE_REG ; i <= LAST_REX_SSE_REG ; i ++ ) reg_alloc_order [ pos ++ ] = i ; for ( i = FIRST_EXT_REX_SSE_REG ; i <= LAST_EXT_REX_SSE_REG ; i ++ ) reg_alloc_order [ pos ++ ] = i ; for ( i = FIRST_MASK_REG ; i <= LAST_MASK_REG ; i ++ ) reg_alloc_order [ pos ++ ] = i ; for ( i = FIRST_BND_REG ; i <= LAST_BND_REG ; i ++ ) reg_alloc_order [ pos ++ ] = i ; if ( TARGET_SSE_MATH ) for ( i = FIRST_STACK_REG ; i <= LAST_STACK_REG ; i ++ ) reg_alloc_order [ pos ++ ] = i ; for ( i = FIRST_MMX_REG ; i <= LAST_MMX_REG ; i


<s> if ( ! checkForImmediate ( S1 , V1 ) || ! checkForImmediate ( S3 , V3 ) ) return false ; unsigned Sub2 = DI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned Sub4 = DI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( Sub2 == <STR_LIT> && Sub4 == <STR_LIT> ) TV = V1 | ( V3 << <NUM_LIT> ) ; else if ( Sub2 == <STR_LIT> && Sub4 == <STR_LIT> ) TV = V3 | ( V1 << <NUM_LIT> ) ; else llvm_unreachable ( <STR_LIT> ) ; break ; } default : return false ; } switch ( MO . getSubReg ( ) ) { case <STR_LIT> : Val = TV & <NUM_LIT> ; break ; case <STR_LIT> : Val = ( TV >> <NUM_LIT> ) & <NUM_LIT> ; break ; default : Val = TV ; break ; } return


<s> bool <ISA_LIT>PassConfig :: addPostRegAlloc ( ) { const <ISA_LIT>TargetMachine & TM = get<ISA_LIT>TargetMachine (


<s> if ( Bytes <= <NUM_LIT> ) return <NUM_LIT> ; if ( Bytes <= <NUM_LIT> ) return <NUM_LIT> ; if ( Bytes <= <NUM_LIT> ) return <NUM_LIT> ; if ( Bytes <= <NUM_LIT> ) return <NUM_LIT> ; if ( Bytes <= <NUM_LIT> ) return <NUM_LIT> ; if ( Bytes <= <NUM_LIT> ) return <NUM_LIT> ; if ( Bytes <=


<s> mcInst . addOperand ( MCOperand :: CreateReg ( <STR_LIT> + ( immediate >> <NUM_LIT> ) ) ) ; return ; case TYPE_XMM512 : mcInst . addOperand ( MCOperand :: CreateReg ( <STR_LIT> + ( immediate >> <NUM_LIT> ) ) ) ; return ; case TYPE_REL8 : isBranch = true ; pcrel = insn . startLocation + insn . immediateOffset + insn . immediateSize ; if ( immediate & <NUM_LIT> ) immediate |= ~ ( <NUM_LIT> ) ; break ; case TYPE_REL32 : case TYPE_REL64 : isBranch = true ; pcrel = insn . startLocation + insn . immediateOffset + insn . immediateSize ; if ( immediate & <NUM_LIT> ) immediate |= ~ ( <NUM_LIT> ) ; break ; default : break ; } if ( ! tryAddingSymbolicOperand ( immediate + pcrel , isBranch , insn . startLocation , insn . immediateOffset , insn . immediateSize , mcInst , Dis ) ) mcInst . addOperand ( MCOperand :: CreateImm ( immediate ) ) ; if ( type == TYPE_MOFFS8 || type == TYPE_MOFFS16 || type

== TYPE_MOFFS32 || type == TYPE_MOFFS64 ) {


<s> if ( EltTy -> isPointerTy ( ) ) VecTy = VectorType :: get ( DL . getIntPtrType ( EltTy ) , VecTy -> getVectorNumElements ( ) ) ; Type * PtrTy = VecTy -> getPointerTo ( LI -> getPointerAddressSpace ( ) ) ; Type * Tys [ <NUM_LIT> ] = { VecTy , PtrTy } ; static const <STR_LIT> LoadInts [ <NUM_LIT> ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> } ; Function * LdNFunc = <STR_LIT> ( LI -> getModule ( ) , LoadInts [ Factor - <NUM_LIT> ] , Tys ) ; IRBuilder < > Builder ( LI ) ; Value * Ptr = Builder . CreateBitCast ( LI -> getPointerOperand ( ) , PtrTy ) ; CallInst * LdN = Builder . CreateCall ( LdNFunc , Ptr , <STR_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i < Shuffles . size ( ) ; i ++ ) { ShuffleVectorInst * SVI = Shuffles [


<s> if ( i > M || M >= HalfSize ) return SDValue ( ) ; if ( Idx < <NUM_LIT> || ( Src == V && Idx == ( M - i ) ) ) { Src = V ; Idx = M - i ; continue ; } return SDValue ( ) ; } if ( Idx < <NUM_LIT> ) return SDValue ( ) ; assert ( ( Idx + Len ) <= HalfSize && <STR_LIT> ) ; int BitLen = ( Len * VT . getScalarSizeInBits ( ) ) & <NUM_LIT> ; int BitIdx = ( Idx * VT . getScalarSizeInBits ( ) ) & <NUM_LIT> ; return DAG . getNode ( <STR_LIT> , DL , VT , Src , DAG . getConstant ( BitLen , DL , <STR_LIT> ) , DAG . getConstant ( BitIdx , DL , <STR_LIT> ) ) ; } ; if ( SDValue ExtrQ = LowerAsEXTRQ ( ) ) return ExtrQ ; auto LowerAsInsertQ = [ & ] ( ) { for ( int Idx = <NUM_LIT> ; Idx != HalfSize ; ++ Idx ) { SDValue Base ; if ( isUndefInRange ( Mask , <NUM_LIT> , Idx ) ) { } else if ( isSequentialOrUndefInRange ( Mask , <NUM_LIT> , Idx , <NUM_LIT> ) ) { Base = V1 ; } else if ( isSequentialOrUndefInRange ( Mask , <NUM_LIT> , Idx , Size ) ) { Base = V2 ; } else { continue ; } for ( int Hi = Idx + <NUM_LIT> ; Hi <= HalfSize


<s> int _U_Qfle ( long double a , long double b ) { return ( _U_Qfcmp ( a , b , QCMP_INV | QCMP_EQ | QCMP_LT ) != <NUM_LIT>


<s> unsigned Opc = Op . getOpcode ( ) ; assert ( VT . isVector ( ) && InVT . isVector ( ) && <STR_LIT> ) ; assert ( ( Opc == <STR_LIT> || Opc == <STR_LIT> ) && <STR_LIT> ) ; assert ( VT . getVectorNumElements ( ) == VT . getVectorNumElements ( ) && <STR_LIT> ) ; assert ( ( VT . getVectorElementType ( ) == <STR_LIT> || VT . getVectorElementType ( ) == <STR_LIT> || VT . getVectorElementType ( ) == <STR_LIT> ) && <STR_LIT> ) ; assert ( ( InVT . getVectorElementType ( ) == <STR_LIT> || InVT . getVectorElementType ( ) == <STR_LIT> || InVT . getVectorElementType ( ) == <STR_LIT> ) && <STR_LIT> ) ; unsigned ExtendInVecOpc = getOpcode_EXTEND_VECTOR_INREG ( Opc ) ; if ( InVT == <STR_LIT> ) { if ( ! ExperimentalVectorWideningLegalization || VT != <STR_LIT> ) return SDValue ( ) ; In = DAG . getNode ( <STR_LIT> , SDLoc ( Op ) , <STR_LIT> , In , DAG . getUNDEF ( <STR_LIT> ) ) ; return DAG . getNode ( ExtendInVecOpc , dl , VT , In ) ; } if ( Subtarget . hasInt256 ( ) ) return Op ; MVT HalfVT = <STR_LIT> ( VT . getVectorElementType ( ) , VT . getVectorNumElements ( ) / <NUM_LIT> ) ; SDValue OpLo = DAG . getNode ( ExtendInVecOpc , dl , HalfVT , In ) ; if ( auto * Shuf = dyn_cast < ShuffleVectorSDNode > ( In ) ) if ( hasIdenticalHalvesShuffleMask ( Shuf -> getMask ( ) ) ) return DAG . getNode ( <STR_LIT> , dl , VT , OpLo , OpLo ) ; SDValue ZeroVec = DAG . getConstant ( <NUM_LIT> , dl , InVT ) ; SDValue Undef = DAG . getUNDEF ( InVT ) ; bool NeedZero = Opc == <STR_LIT> ; SDValue OpHi = getUnpackh ( DAG , dl , InVT , In , NeedZero ? ZeroVec : Undef ) ; OpHi = DAG . getBitcast ( HalfVT , OpHi


<s> LLVM_EXTERNAL_VISIBILITY void LLVMInitialize<ISA_LIT>AsmPrinter ( ) { RegisterAsmPrinter < <ISA_LIT>AsmPrinter > X ( getThe<ISA_LIT>32Target (


<s> rtx insn ; if ( low == high ) insn = emit_insn ( gen_stack_push ( gen_rtx_REG ( SImode , low ) ) ) ; else insn = emit_insn ( gen_stack_pushm ( GEN_INT ( ( ( high - low ) + <NUM_LIT> ) * UNITS_PER_WORD

) , gen_rx_store_vector ( low , high ) ) ) ;


<s> tree op0 = fold_convert ( vtype , op [ <NUM_LIT> ] ) ; tree op1 = fold_convert ( vtype , op [ <NUM_LIT> ] ) ; tree val = fold_build2 ( code , vtype , op0 ,


<s> DebugLoc DL = MI . getDebugLoc ( ) ; unsigned Dst = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Src = MI . getOperand ( <NUM_LIT> )


<s> } else if ( Subtarget -> getGeneration ( ) == <ISA_LIT>Subtarget :: SEA_ISLANDS ) { if ( ! isUInt < <NUM_LIT> > ( AM . BaseOffs / <NUM_LIT> ) ) return false ; } else if ( Subtarget -> getGeneration ( ) == <ISA_LIT>Subtarget :: VOLCANIC_ISLANDS ) { if ( ! isUInt < <NUM_LIT> > ( AM . BaseOffs ) ) return false ; } else llvm_unreachable ( <STR_LIT> ) ; if ( AM . Scale == <NUM_LIT> ) return true ; if ( AM . Scale == <NUM_LIT> && AM . HasBaseReg ) return true ; return false ; case <ISA_LIT>AS :: PRIVATE_ADDRESS : return isLegalMUBUFAddressingMode ( AM ) ; case <ISA_LIT>AS :: LOCAL_ADDRESS : case <ISA_LIT>AS :: REGION_ADDRESS : if ( ! isUInt < <NUM_LIT> > ( AM . BaseOffs ) ) return false ; if ( AM . Scale == <NUM_LIT> ) return


<s> if ( ST . isAmdHsaOrMesa ( F ) ) { PreloadedScratchRsrcReg = MFI -> getPreloadedReg ( <STR_LIT> ) ; if ( ScratchRsrcReg && PreloadedScratchRsrcReg ) { MRI . addLiveIn ( PreloadedScratchRsrcReg ) ; MBB . addLiveIn ( PreloadedScratchRsrcReg ) ; } } Register ScratchWaveOffsetReg ; if ( TRI -> isSubRegisterEq ( ScratchRsrcReg , PreloadedScratchWaveOffsetReg ) ) { ArrayRef < MCPhysReg > AllSGPRs = TRI -> getAllSGPR32 ( MF ) ; unsigned NumPreloaded = MFI -> getNumPreloadedSGPRs ( ) ; AllSGPRs = AllSGPRs . slice ( std :: min ( static_cast < unsigned > ( AllSGPRs . size ( ) ) , NumPreloaded ) ) ; Register GITPtrLoReg = MFI -> getGITPtrLoReg ( MF ) ; for ( MCPhysReg Reg : AllSGPRs ) { if ( ! MRI . isPhysRegUsed ( Reg ) && MRI . isAllocatable ( Reg ) && ! TRI -> isSubRegisterEq ( ScratchRsrcReg , Reg ) && GITPtrLoReg != Reg ) { ScratchWaveOffsetReg = Reg ; BuildMI ( MBB , I , DL , TII -> get ( <STR_LIT> ) , ScratchWaveOffsetReg ) . addReg ( PreloadedScratchWaveOffsetReg , RegState :: Kill ) ; break ; } } } else { ScratchWaveOffsetReg = PreloadedScratchWaveOffsetReg ; } assert ( ScratchWaveOffsetReg ) ; if ( requiresStackPointerReference ( MF ) ) { Register SPReg = MFI -> getStackPtrOffsetReg ( ) ; assert ( SPReg != <STR_LIT> ) ; BuildMI ( MBB , I , DL , TII -> get ( <STR_LIT> ) , SPReg ) . addImm ( FrameInfo . getStackSize ( ) * getScratchScaleFactor ( ST ) ) ; } if ( hasFP ( MF ) ) { Register FPReg = MFI -> getFrameOffsetReg ( ) ; assert ( FPReg != <STR_LIT> ) ; BuildMI ( MBB , I , DL , TII -> get ( <STR_LIT> ) , FPReg ) . addImm ( <NUM_LIT> ) ; } bool NeedsFlatScratchInit = MFI -> hasFlatScratchInit ( ) && ( MRI . isPhysRegUsed ( <STR_LIT> ) || FrameInfo . hasCalls ( ) || ( ! allStackObjectsAreDead ( MF ) && ST . enableFlatScratch ( ) ) ) ; if ( ( NeedsFlatScratchInit || ScratchRsrcReg ) && ! ST . flatScratchIsArchitected ( ) ) { MRI . addLiveIn ( PreloadedScratchWaveOffsetReg ) ; MBB . addLiveIn ( PreloadedScratchWaveOffsetReg ) ; } if ( NeedsFlatScratchInit ) { emitEntryFunctionFlatScratchInit ( MF , MBB , I , DL , ScratchWaveOffsetReg ) ; } if ( ScratchRsrcReg ) { emitEntryFunctionScratchRsrcRegSetup ( MF , MBB , I , DL

, PreloadedScratchRsrcReg , ScratchRsrcReg , ScratchWaveOffsetReg ) ;


<s> switch ( prefix ) { case <NUM_LIT> : case <NUM_LIT> : if ( lookAtByte ( insn , & nextByte ) ) break ; if ( isREX ( insn , nextByte ) || nextByte == <NUM_LIT> || nextByte == <NUM_LIT> ) insn -> mandatoryPrefix = prefix ; insn -> repeatPrefix = prefix ; break ; case <NUM_LIT> : if ( lookAtByte ( insn , &


<s> if ( <ISA_LIT>FrameLowering :: FItoStackOffset ( FI ) < maxOffset ) { Base = CurDAG -> getTargetConstant ( offset , PtrTy ) ; Index = CurDAG -> getTargetFrameIndex ( FI , PtrTy ) ; return true ; } } else if ( offset > minOffset && offset < maxOffset ) { Base = CurDAG -> getTargetConstant ( offset , PtrTy ) ; Index = Op1 ; return true ; } } } else if ( Opc == <STR_LIT> ) { const SDValue Op0 = N . getOperand ( <NUM_LIT> ) ; const SDValue Op1 = N . getOperand ( <NUM_LIT> ) ; if ( Op0 . getOpcode ( ) == <STR_LIT> && Op1 . getOpcode ( ) == <STR_LIT> ) { Base = CurDAG -> getTargetConstant ( <NUM_LIT> , PtrTy ) ; Index = N ; return true ; } else if ( isa < ConstantSDNode > ( Op0 ) || isa < ConstantSDNode > ( Op1 ) ) { int32_t offset = <NUM_LIT> ; SDValue idxOp ; if ( isa < ConstantSDNode > ( Op1 ) ) { ConstantSDNode * CN = cast < ConstantSDNode > ( Op1 ) ; offset = int32_t ( CN -> getSExtValue ( ) ) ; idxOp = Op0 ; } else if ( isa < ConstantSDNode > ( Op0 ) ) { ConstantSDNode * CN = cast < ConstantSDNode > ( Op0 ) ; offset = int32_t ( CN -> getSExtValue ( ) ) ; idxOp = Op1 ; } if ( offset >= minOffset && offset <= maxOffset ) { Base = CurDAG -> getTargetConstant ( offset , PtrTy ) ; Index = idxOp ; return true ; } } } else if ( Opc == <STR_LIT> ) { Base = CurDAG -> getTargetConstant ( <NUM_LIT> , N . getValueType ( ) ) ; Index = N ; return true ; } else if ( Opc == <STR_LIT> ) { Base = CurDAG -> getTargetConstant ( <NUM_LIT> , N . getValueType ( ) ) ; Index = N ; return true ; } else if ( Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ) { unsigned OpOpc = Op -> getOpcode ( ) ; if ( OpOpc == <STR_LIT> || OpOpc == <STR_LIT> ) { SDValue Offs ; Offs = ( ( OpOpc == <STR_LIT> ) ? Op -> getOperand ( <NUM_LIT> ) : Op -> getOperand ( <NUM_LIT> ) ) ; if ( Offs . getOpcode ( ) == <STR_LIT> || Offs . getOpcode ( ) == <STR_LIT> ) { if ( Offs . getOpcode ( ) == <STR_LIT> ) Offs = CurDAG -> getTargetConstant ( <NUM_LIT> , Offs . getValueType ( ) ) ; Base = Offs ; Index = N ; return


<s> static SDValue PerformVDUPLANECombine ( SDNode * N , TargetLowering :: DAGCombinerInfo & DCI ) { SDValue Op = N -> getOperand ( <NUM_LIT> ) ; if ( CombineVLDDUP ( N , DCI ) ) return SDValue ( N , <NUM_LIT> ) ; while ( Op . getOpcode ( ) == <STR_LIT> ) Op = Op . getOperand ( <NUM_LIT> ) ; if ( Op . getOpcode ( ) != <STR_LIT> && Op .

getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ;


<s> if ( NewOpcode >= <NUM_LIT> ) return NewOpcode ; switch ( MI -> getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : return getDotNewPredJumpOp ( MI , MBPI ) ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case


<s> SDValue <ISA_LIT>TargetLowering :: LowerMemArgument ( SDValue Chain , CallingConv :: ID CallConv , const SmallVectorImpl < <STR_LIT> > & Ins , SDLoc dl , SelectionDAG & DAG , const CCValAssign & VA , MachineFrameInfo * MFI , unsigned i ) const { <STR_LIT> Flags = Ins [ i ] . Flags ; bool AlwaysUseMutable = shouldGuaranteeTCO ( CallConv , DAG . getTarget ( ) . Options . GuaranteedTailCallOpt ) ; bool isImmutable = ! AlwaysUseMutable && ! Flags . isByVal ( ) ; EVT ValVT ; bool ExtendedInMem = VA . isExtInLoc ( ) && VA . getValVT ( ) . getScalarType ( ) == <STR_LIT> ; if ( VA . getLocInfo ( ) == CCValAssign :: Indirect || ExtendedInMem ) ValVT = VA . getLocVT ( ) ; else ValVT = VA . getValVT ( ) ; int Offset = <NUM_LIT> ; if ( CallConv == CallingConv :: <ISA_LIT>_INTR ) { const <ISA_LIT>Subtarget & Subtarget = static_cast < const <ISA_LIT>Subtarget & > ( DAG . getSubtarget ( ) ) ; Offset = ( Subtarget . is64Bit ( ) ? <NUM_LIT> : <NUM_LIT> ) * ( ( i + <NUM_LIT> ) % Ins . size ( ) - <NUM_LIT> ) ; } if ( Flags . isByVal ( ) ) { unsigned Bytes = Flags . getByValSize ( ) ; if ( Bytes == <NUM_LIT> ) Bytes = <NUM_LIT> ; int FI = MFI -> CreateFixedObject ( Bytes , VA . getLocMemOffset ( ) , isImmutable ) ; if ( CallConv == CallingConv :: <ISA_LIT>_INTR ) { MFI -> setObjectOffset ( FI , Offset ) ; } return DAG . getFrameIndex ( FI , getPointerTy ( DAG .


<s> Addr . Base . Reg = getRegForValue ( Obj ) ; return Addr . Base . Reg


<s> const TargetRegisterClass * <ISA_LIT>RegisterInfo :: getPhysRegClass ( unsigned Reg ) const { assert ( ! TargetRegisterInfo :: isVirtualRegister ( Reg ) ) ; static const TargetRegisterClass * const BaseClasses [ ] = { & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT>

, & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , } ;


<s> return GV != <NUM_LIT> || CP != <NUM_LIT> || ES != <NUM_LIT> || JT !=


<s> int sh_hard_regno_rename_ok ( unsigned int old_reg ATTRIBUTE_UNUSED , unsigned int new_reg


<s> BuildMI ( MBB , DL , TII -> get ( LOpcode ) , OrigOldVal ) . addOperand ( Base ) . addImm ( Disp ) . addReg ( <NUM_LIT> ) ; MBB -> addSuccessor ( LoopMBB ) ; MBB = LoopMBB ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) , OldVal ) . addReg ( OrigOldVal ) . addMBB ( StartMBB ) . addReg ( RetryOldVal ) . addMBB ( SetMBB ) ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) , CmpVal ) . addReg ( OrigCmpVal ) . addMBB ( StartMBB ) . addReg ( RetryCmpVal ) . addMBB ( SetMBB ) ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) , SwapVal ) . addReg ( OrigSwapVal ) . addMBB ( StartMBB ) . addReg ( RetrySwapVal ) . addMBB ( SetMBB ) ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) , Dest ) . addReg ( OldVal ) . addReg ( BitShift ) . addImm ( BitSize ) ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) , RetryCmpVal ) . addReg ( CmpVal ) . addReg ( Dest ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> - BitSize ) . addImm ( <NUM_LIT> ) ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) ) . addReg ( Dest ) . addReg ( RetryCmpVal ) ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) ) . addImm ( <STR_LIT> ) . addImm ( <STR_LIT> ) . addMBB ( DoneMBB ) ; MBB -> addSuccessor ( DoneMBB ) ; MBB -> addSuccessor ( SetMBB ) ; MBB = SetMBB ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) , RetrySwapVal ) . addReg ( SwapVal ) . addReg ( Dest ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> - BitSize ) . addImm ( <NUM_LIT> ) ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) , StoreVal ) . addReg ( RetrySwapVal ) . addReg ( NegBitShift ) . addImm


addPass ( createThumb2ITBlockPass ( ) ) ;


<s> __inline__ static float sh_media_FMOV_LS ( int mm ) { float res ; __asm__ ( <STR_LIT> : <STR_LIT> ( res ) : <STR_LIT> ( mm ) ) ; return res


<s> SDValue Hi = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , CP ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , CP ) ; if ( getTargetMachine ( ) . getRelocationModel ( ) != Reloc :: PIC_ ) return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Lo , Hi ) ; SDValue GlobalBase = DAG . getNode ( <STR_LIT> , dl , getPointerTy ( ) ) ; SDValue RelAddr = DAG . getNode ( <STR_LIT> , dl , <STR_LIT>


<s> unsigned <ISA_LIT>MachOTargetObjectFile :: getTTypeEncoding ( ) const { return DW_EH_PE_indirect | DW_EH_PE_pcrel


<s> int ISD = TLI -> InstructionOpcodeToISD ( Opcode ) ; switch ( ISD ) { default : return Cost + BaseT :: getArithmeticInstrCost ( Opcode , Ty , CostKind , Opd1Info , Opd2Info , Opd1PropInfo , Opd2PropInfo ) ; case <STR_LIT> : if ( Opd2Info == TargetTransformInfo :: OK_UniformConstantValue && Opd2PropInfo == TargetTransformInfo :: OP_PowerOf2 ) { Cost += getArithmeticInstrCost ( Instruction :: Add , Ty , CostKind , Opd1Info , Opd2Info , TargetTransformInfo :: OP_None , TargetTransformInfo :: OP_None ) ; Cost += getArithmeticInstrCost ( Instruction :: Sub , Ty , CostKind , Opd1Info , Opd2Info , TargetTransformInfo :: OP_None , TargetTransformInfo :: OP_None ) ; Cost += getArithmeticInstrCost ( Instruction :: Select , Ty , CostKind , Opd1Info , Opd2Info , TargetTransformInfo :: OP_None , TargetTransformInfo :: OP_None ) ; Cost += getArithmeticInstrCost ( Instruction :: AShr , Ty , CostKind , Opd1Info , Opd2Info , TargetTransformInfo :: OP_None , TargetTransformInfo :: OP_None ) ; return Cost ; } LLVM_FALLTHROUGH ; case <STR_LIT> : if ( Opd2Info == TargetTransformInfo :: OK_UniformConstantValue ) { auto VT = TLI -> getValueType ( DL , Ty ) ; if ( TLI -> isOperationLegalOrCustom ( <STR_LIT> , VT ) ) { int MulCost = getArithmeticInstrCost ( Instruction :: Mul , Ty , CostKind , Opd1Info , Opd2Info , TargetTransformInfo :: OP_None , TargetTransformInfo :: OP_None ) ; int AddCost = getArithmeticInstrCost ( Instruction :: Add , Ty , CostKind , Opd1Info , Opd2Info , TargetTransformInfo :: OP_None , TargetTransformInfo :: OP_None ) ; int ShrCost = getArithmeticInstrCost ( Instruction :: AShr , Ty , CostKind , Opd1Info , Opd2Info , TargetTransformInfo :: OP_None , TargetTransformInfo :: OP_None ) ; return MulCost * <NUM_LIT> + AddCost * <NUM_LIT> + ShrCost * <NUM_LIT> + <NUM_LIT> ; } } Cost += BaseT :: getArithmeticInstrCost ( Opcode , Ty , CostKind , Opd1Info


<s> bool RetVal = true ; bool AllConstantIndices = I . hasAllConstantIndices ( ) ; if ( isStruct && ! AllConstantIndices ) return false ; Offset = ComputeOffsetForGEP ( IRB , I , Offset ) ; AddToLazyDeletionSet ( & I ) ; for ( auto * User : I . users ( ) ) RetVal &= ProcessUser ( MemOpOffsetMap , * User , Offset ,


<s> if ( TM -> getOptLevel ( ) != CodeGenOpt :: None ) { addPass ( create<ISA_LIT>MergeBaseOffsetOptPass ( ) ) ; addPass ( create<ISA_LIT>CleanupVSETVLIPass (


<s> bool <ISA_LIT>LoadStoreOpt :: MergeOps ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI , int Offset , unsigned Base , bool BaseKill , int Opcode , <STR_LIT> Pred , unsigned PredReg , unsigned Scratch , DebugLoc dl , SmallVector < std :: pair < unsigned , bool > , <NUM_LIT> > & Regs ) { unsigned NumRegs = Regs . size ( ) ; if ( NumRegs <= <NUM_LIT> ) return false ; <STR_LIT> Mode = <STR_LIT> ; bool isNotVFP = isi32Load ( Opcode ) || isi32Store ( Opcode ) ; bool haveIBAndDA = isNotVFP && ! isThumb2 ; if ( Offset == <NUM_LIT> && haveIBAndDA ) Mode = <STR_LIT> ; else if ( Offset == - <NUM_LIT> * ( int ) NumRegs + <NUM_LIT> && haveIBAndDA ) Mode = <STR_LIT> ; else if ( Offset == - <NUM_LIT> * ( int ) NumRegs && isNotVFP ) Mode = <STR_LIT> ; else if ( Offset != <NUM_LIT> ) { if ( NumRegs <= <NUM_LIT> ) return false ; unsigned NewBase ; if ( isi32Load ( Opcode ) ) NewBase = Regs [ NumRegs - <NUM_LIT> ] . first ; else { NewBase = Scratch ; if ( NewBase == <NUM_LIT> ) return false ; } int BaseOpc = ! isThumb2 ? <STR_LIT> : ( ( Base == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ) ; if ( Offset < <NUM_LIT> ) { BaseOpc = ! isThumb2 ? <STR_LIT> : ( ( Base == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ) ; Offset = - Offset ; } int ImmedOffset = isThumb2 ? <STR_LIT> ( Offset ) : <STR_LIT> ( Offset ) ; if ( ImmedOffset == - <NUM_LIT> ) return false ; BuildMI ( MBB , MBBI , dl , TII -> get ( BaseOpc ) , NewBase ) . addReg ( Base , getKillRegState ( BaseKill ) ) . addImm ( Offset ) . addImm ( Pred ) . addReg ( PredReg ) . addReg ( <NUM_LIT> ) ; Base = NewBase


<s> tree ix86_handle_shared_attribute ( tree * node , tree name , tree args ATTRIBUTE_UNUSED , int flags ATTRIBUTE_UNUSED , bool * no_add_attrs ) { if ( TREE_CODE ( * node


<s> std :: vector < unsigned > :: iterator search_begin = GPR64DeadDefs . begin ( ) ; std :: vector < unsigned > :: iterator search_end = GPR64DeadDefs . end ( ) ; for ( auto I : GPR32LiveDefs ) for ( MCSuperRegIterator SR ( I , TRI ) ; SR . isValid ( ) ; ++ SR ) if ( std :: find ( search_begin , search_end , * SR ) == search_end ) return true ; return


<s> const <ISA_LIT>Subtarget * getSubtargetImpl ( )


<s> else if ( const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( Expr ) ) Inst . addOperand ( MCOperand :: CreateImm ( CE -> getValue ( ) ) ) ; else Inst . addOperand ( MCOperand :: CreateExpr


<s> if ( isVALU ( MI ) || isSALU ( MI ) ) { if ( isFixedSize ( MI ) ) return DescSize ; int Src0Idx = <STR_LIT> ( Opc , <STR_LIT> :: src0 ) ; if ( Src0Idx == - <NUM_LIT> ) return <NUM_LIT> ; if ( isLiteralConstantLike ( MI . getOperand ( Src0Idx ) , Desc . OpInfo [ Src0Idx ] ) ) return <NUM_LIT> ; int Src1Idx = <STR_LIT> ( Opc , <STR_LIT> :: src1 ) ; if ( Src1Idx == - <NUM_LIT> ) return <NUM_LIT> ; if ( isLiteralConstantLike ( MI . getOperand ( Src1Idx ) , Desc . OpInfo [ Src1Idx ] ) ) return <NUM_LIT> ; return <NUM_LIT> ; } if ( DescSize == <NUM_LIT> ) return <NUM_LIT> ; switch ( Opc


<s> SmallVector < CCValAssign , <NUM_LIT> > RVLocs ; CCState CCInfo ( CallConv , isVarArg , DAG . getMachineFunction ( ) , getTargetMachine ( ) , RVLocs , * DAG . getContext ( ) ) ; AnalyzeReturnValues ( CCInfo , RVLocs , Ins ) ; for ( unsigned i = <NUM_LIT> ; i != RVLocs . size ( )


<s> bool hasCondMov ( ) const { return HasCondMov


<s> vmovn_high_u32 ( uint16x4_t a , uint32x4_t b ) { uint16x8_t result = vcombine_u16 ( a , vcreate_u16 ( __AARCH64_UINT64_C ( <NUM_LIT> ) ) ) ; __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> (


<s> assert ( ! IsStrict && <STR_LIT> ) ; softenSetCCOperands ( DAG , <STR_LIT> , Op0 , Op1 , CC , dl , Op0 , Op1 ) ; if ( ! Op1 . getNode ( ) ) { assert ( Op0 . getValueType ( ) == Op . getValueType ( ) && <STR_LIT> ) ; return Op0 ; } } SDValue <ISA_LIT>CC ; SDValue EFLAGS = emitFlagsForSetcc ( Op0 , Op1 , CC , dl , DAG , <ISA_LIT>CC , Chain , Op . getOpcode ( ) == <STR_LIT> ) ; if ( ! EFLAGS ) return SDValue ( ) ; SDValue Res = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , <ISA_LIT>CC , EFLAGS ) ; if ( IsStrict ) return DAG . getMergeValues ( { Res


<s> HOST_WIDE_INT value = INTVAL ( op2 ) & mask ; if ( code == AND ) { if ( value == <NUM_LIT> ) { emit_insn ( gen_rtx_SET ( dest , const0_rtx ) ) ; return ; } else if ( value == mask ) { if ( ! rtx_equal_p ( dest , op1 ) ) emit_insn ( gen_rtx_SET ( dest , op1 ) ) ; return ; } } else if ( code == IOR || code == XOR ) { if ( value == <NUM_LIT> ) { if ( ! rtx_equal_p ( dest , op1 ) ) emit_insn ( gen_rtx_SET ( dest , op1