<s> if ( ! SawChainSeparater ) ChainNum = ( unsigned ) sqrt ( ( double ) EleNum ) ; CBucket . ChainSize = ( unsigned ) ( EleNum / ChainNum ) ; if ( CBucket . ChainSize * ChainNum != EleNum ) return false ; if ( SawChainSeparater ) { for ( unsigned i = <NUM_LIT> ; i < CBucket . ChainSize ; i ++ ) for ( unsigned j = <NUM_LIT> ; j < ChainNum ; j ++ ) if ( CBucket . Elements [ i ] . Offset != SE -> getMinusSCEV ( CBucket . Elements [ i + j * CBucket . ChainSize ] . Offset , CBucket . Elements [ j * CBucket . ChainSize ] . Offset ) ) return false ; } for ( unsigned i = <NUM_LIT> ; i < ChainNum ; i ++ ) CBucket . ChainBases . push_back ( CBucket . Elements [ i * CBucket . ChainSize ] ) ; LLVM_DEBUG ( dbgs ( ) <<


<s> StackOffset Offset ; if ( MI . getOpcode ( ) == <STR_LIT> ) { const <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; FrameReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Offset = { MFI . getObjectOffset ( FrameIndex ) + AFI -> getTaggedBasePointerOffset ( ) , <STR_LIT> } ; } else if ( Tagged ) { StackOffset SPOffset = { MFI . getObjectOffset ( FrameIndex ) + ( int64_t ) MFI . getStackSize ( ) , <STR_LIT> } ; if ( MFI . hasVarSizedObjects ( ) || is<ISA_LIT>FrameOffsetLegal ( MI , SPOffset , nullptr , nullptr , nullptr ) != ( <ISA_LIT>FrameOffsetCanUpdate | <ISA_LIT>FrameOffsetIsLegal ) ) { Offset = TFI -> resolveFrameIndexReference ( MF , FrameIndex , FrameReg , false , true ) ; Register ScratchReg = MF . getRegInfo ( ) . createVirtualRegister ( & <STR_LIT> ) ; emitFrameOffset ( MBB , II , MI . getDebugLoc ( ) , ScratchReg , FrameReg , Offset , TII ) ; BuildMI ( MBB , MI , MI . getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , ScratchReg ) . addReg ( ScratchReg ) . addReg ( ScratchReg ) . addImm ( <NUM_LIT> ) ; MI . getOperand ( FIOperandNum ) . ChangeToRegister ( ScratchReg , false , false , true ) ; return ; } FrameReg = <STR_LIT> ; Offset = { MFI . getObjectOffset ( FrameIndex ) + ( int64_t ) MFI . getStackSize ( ) , <STR_LIT> } ; } else { Offset = TFI -> resolveFrameIndexReference ( MF , FrameIndex , FrameReg , false , true ) ; } if ( rewrite<ISA_LIT>FrameIndex ( MI , FIOperandNum , FrameReg , Offset , TII ) ) return ; assert ( ( ! RS || ! RS -> isScavengingFrameIndex (


<s> __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) : ) ; return


<s> const MCPhysReg * <ISA_LIT>RegisterInfo :: getCalleeSavedRegsViaCopy ( const MachineFunction * MF ) const { assert ( MF && <STR_LIT>


<s> CCState CCInfo ( CallConv , IsVarArg , MF , ArgLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeFormalArguments ( Ins , CC_<ISA_LIT> ) ; for ( auto & VA : ArgLocs ) { if ( ! VA . isRegLoc ( ) ) report_fatal_error ( <STR_LIT> ) ; EVT RegVT = VA . getLocVT ( ) ; if ( RegVT != <STR_LIT> ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << RegVT . getEVTString ( ) << <STR_LIT> ) ; report_fatal_error ( <STR_LIT> ) ; } const unsigned VReg = RegInfo . createVirtualRegister ( &


<s> return std :: make_unique < <ISA_LIT>WinCOFFObjectWriter > (


<s> int Offset = MFI -> getObjectOffset ( FI ) + MFI -> getOffsetAdjustment ( ) ; uint64_t StackSize = MFI -> getStackSize ( ) ; if ( FI < <NUM_LIT> ) StackSize -= <ISA_LIT>MFI -> getCalleeSavedFrameSize ( ) ; Offset += StackSize - getOffsetOfLocalArea ( ) ; if ( StackSize || MFI -> hasCalls ( ) ) Offset -= getOffsetOfLocalArea ( ) ; return Offset


<s> case MCSymbolRefExpr :: VK_None : Type = ELF :: R_<ISA_LIT>_64_32S ; break ; case MCSymbolRefExpr :: VK_GOT : Type = ELF :: R_<ISA_LIT>_64_GOT32 ; break ; case MCSymbolRefExpr :: VK_GOTPCREL : Type = ELF :: R_<ISA_LIT>_64_GOTPCREL ; break ; case MCSymbolRefExpr :: VK_TPOFF : Type = ELF :: R_<ISA_LIT>_64_TPOFF32 ; break ; case MCSymbolRefExpr :: VK_DTPOFF : Type = ELF :: R_<ISA_LIT>_64_DTPOFF32 ; break ; } break ; case FK_Data_4 : Type = ELF :: R_<ISA_LIT>_64_32 ; break ; case FK_Data_2 : Type = ELF :: R_<ISA_LIT>_64_16 ; break ; case FK_PCRel_1 : case FK_Data_1 : Type = ELF :: R_<ISA_LIT>_64_8 ; break ; } } } else if ( getEMachine ( ) == ELF :: EM_386 ) { if ( IsPCRel ) { switch ( ( unsigned ) Fixup . getKind ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : Type = ELF :: R_386_GOTPC ; break ; case <STR_LIT> : case FK_PCRel_4 : case FK_Data_4 : switch ( Modifier ) { default : llvm_unreachable ( <STR_LIT> ) ; case MCSymbolRefExpr :: VK_None : Type = ELF :: R_386_PC32 ; break ; case MCSymbolRefExpr :: VK_PLT : Type = ELF :: R_386_PLT32 ; break ; } break ; } } else { switch ( ( unsigned ) Fixup . getKind ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : Type = ELF :: R_386_GOTPC ; break ; case <STR_LIT> : case FK_PCRel_4 : case FK_Data_4 : switch ( Modifier ) { default : llvm_unreachable ( <STR_LIT> ) ; case MCSymbolRefExpr :: VK_None : Type = ELF :: R_386_32 ; break ; case MCSymbolRefExpr :: VK_GOT : Type = ELF :: R_386_GOT32 ; break ; case MCSymbolRefExpr :: VK_GOTOFF : Type = ELF :: R_386_GOTOFF ; break ; case MCSymbolRefExpr :: VK_TLSGD : Type = ELF :: R_386_TLS_GD ; break ; case MCSymbolRefExpr :: VK_TPOFF : Type = ELF :: R_386_TLS_LE_32 ; break ; case MCSymbolRefExpr :: VK_INDNTPOFF : Type = ELF :: R_386_TLS_IE ; break ; case MCSymbolRefExpr :: VK_NTPOFF : Type = ELF :: R_386_TLS_LE ; break ; case MCSymbolRefExpr :: VK_GOTNTPOFF


<s> unsigned Opcode = Instruction :: UserOp1 ; if ( const Instruction * I = dyn_cast < Instruction > ( Obj ) ) { if ( FuncInfo . StaticAllocaMap . count ( static_cast < const AllocaInst * > ( Obj ) ) || FuncInfo . MBBMap [ I -> getParent ( ) ] == FuncInfo . MBB ) { Opcode = I -> getOpcode ( ) ; U = I ; } } else if ( const ConstantExpr * C = dyn_cast < ConstantExpr > ( Obj ) ) { Opcode = C -> getOpcode ( ) ; U = C ; } switch ( Opcode ) { default : break ; case Instruction :: BitCast : return <ISA_LIT>ComputeAddress ( U -> getOperand ( <NUM_LIT> ) , Addr ) ; case Instruction :: IntToPtr : if ( TLI . getValueType ( DL , U -> getOperand ( <NUM_LIT> ) -> getType ( ) ) == TLI . getPointerTy ( DL ) ) return <ISA_LIT>ComputeAddress ( U -> getOperand ( <NUM_LIT> ) , Addr ) ; break ; case Instruction :: PtrToInt : if ( TLI . getValueType ( DL , U -> getType ( ) ) == TLI . getPointerTy ( DL ) ) return <ISA_LIT>ComputeAddress ( U -> getOperand ( <NUM_LIT> ) , Addr ) ; break ; case Instruction :: GetElementPtr : { Address SavedAddr = Addr ; long TmpOffset = Addr . Offset ; gep_type_iterator GTI = gep_type_begin ( U ) ; for ( User :: const_op_iterator II = U -> op_begin ( ) + <NUM_LIT> , IE = U -> op_end ( ) ; II != IE ; ++ II , ++ GTI ) { const Value * Op = * II ; if ( StructType * STy = dyn_cast < StructType > ( * GTI ) ) { const StructLayout * SL = DL . getStructLayout ( STy ) ; unsigned Idx = cast < ConstantInt >


<s> SDValue <ISA_LIT>TargetLowering :: LowerBlockAddress ( SDValue Op , SelectionDAG & DAG ) const { const BlockAddress * BA = cast < BlockAddressSDNode > ( Op ) -> getBlockAddress ( ) ; SDValue BA_SD = DAG . getTargetBlockAddress


<s> bool <ISA_LIT>AsmParser :: parseOperand ( OperandVector & Operands , StringRef Mnemonic ) { OperandMatchResultTy Result = MatchOperandParserImpl ( Operands , Mnemonic , true ) ; if ( Result == MatchOperand_Success ) return false ; if ( Result == MatchOperand_ParseFail ) return true ; if ( Mnemonic . str ( ) == <STR_LIT> || Mnemonic . str ( ) == <STR_LIT> || Mnemonic . str ( ) == <STR_LIT> || Mnemonic . str ( ) == <STR_LIT> || Mnemonic . str ( ) == <STR_LIT> || Mnemonic . str ( ) == <STR_LIT> || Mnemonic . str ( ) == <STR_LIT> || Mnemonic . str ( ) == <STR_LIT> || Mnemonic . str ( ) == <STR_LIT> || Mnemonic . str ( ) == <STR_LIT> || Mnemonic . str ( ) == <STR_LIT> || Mnemonic . str ( ) == <STR_LIT> || Mnemonic . str ( ) == <STR_LIT> || Mnemonic . str ( ) == <STR_LIT> ) { if ( parseRegisterV0asV0T ( Operands , true ) == MatchOperand_Success ) return false ; } if ( parseRegister ( Operands , true ) == MatchOperand_Success ) return false ; if ( parseImmediate ( Operands ) == MatchOperand_Success ) { if ( getLexer ( ) . is ( AsmToken :: LParen ) ) return parseMemOpBaseReg ( Operands ) != MatchOperand_Success ; return false ; } Error ( getLoc (


<s> SmallVector < unsigned , <NUM_LIT> > DefsA ; SmallVector < unsigned , <NUM_LIT> > DefsB ; SmallVector < unsigned , <NUM_LIT> > UsesA ; SmallVector < unsigned , <NUM_LIT> > UsesB ; parseOperands ( ProdMI , DefsA , UsesA ) ; parseOperands ( ConsMI , DefsB , UsesB ) ; for ( auto & RegA : DefsA ) for ( auto & RegB : UsesB ) { if ( RegA == RegB ) return true ; if ( <STR_LIT> . contains ( RegA ) ) for ( MCSubRegIterator SubRegs ( RegA , & HRI ) ; SubRegs . isValid ( ) ; ++ SubRegs ) if ( RegB == * SubRegs ) return true ; if ( <STR_LIT> . contains ( RegB ) ) for ( MCSubRegIterator SubRegs ( RegB , & HRI ) ; SubRegs . isValid ( ) ; ++ SubRegs ) if ( RegA == * SubRegs ) return true ; } return false


<s> const MCConstantExpr * CE = cast < MCConstantExpr > ( getImm ( ) ) ; assert ( CE -> getValue ( ) >= <NUM_LIT> && CE

-> getValue ( ) <= <NUM_LIT> && <STR_LIT> ) ;


<s> static bool memAccessesCanBeReordered ( MachineBasicBlock :: iterator A , MachineBasicBlock :: iterator B , AliasAnalysis * AA ) { return ! ( A -> mayStore ( ) || B -> mayStore ( ) ) || ! A -> mayAlias ( AA , * B


<s> virtual const <ISA_LIT>RegisterInfo & getRegisterInfo ( ) const { return


<s> uint32_t get<ISA_LIT>Version ( ) const { return <ISA_LIT>Version


<s> if ( ( TSFlags & <STR_LIT> ) || ( Flags & <STR_LIT> ) ) O << <STR_LIT> ; if ( ( TSFlags & <STR_LIT> ) || ( Flags & <STR_LIT> ) ) O << <STR_LIT> ; if ( Flags & <STR_LIT>


<s> bool isInlineConstant ( const APFloat & Imm ) const { return isInlineConstant ( Imm . bitcastToAPInt ( )


<s> static unsigned int rs6000_hard_regno_nregs_hook ( unsigned int regno , machine_mode mode ) { return rs6000_hard_regno_nregs [ mode ] [ regno


<s> b -> addInit ( <STR_LIT> , <NUM_LIT> , b -> dec_unsigned ( <NUM_LIT> , <NUM_LIT> ) , false ) ; b -> addInit ( <STR_LIT> , <NUM_LIT> , b -> dec_unsigned ( <NUM_LIT> , <NUM_LIT> ) , false ) ; b -> addInit ( <STR_LIT> , <NUM_LIT> , b -> dec_unsigned ( <NUM_LIT> , <NUM_LIT> ) , false ) ; b -> addInit ( <STR_LIT> , <NUM_LIT> , b -> dec_unsigned ( <NUM_LIT> , <NUM_LIT> ) , false ) ; b -> addInit ( <STR_LIT> , <NUM_LIT> , b -> dec_unsigned ( <NUM_LIT> , <NUM_LIT> ) , false ) ; b -> addInit ( <STR_LIT> , <NUM_LIT> , b -> dec_unsigned ( <NUM_LIT> , <NUM_LIT> ) , false ) ; b -> addInit ( <STR_LIT> , <NUM_LIT> , b -> dec_unsigned ( <NUM_LIT> , <NUM_LIT> ) , false ) ; b -> addInit ( <STR_LIT> , <NUM_LIT> , b -> dec_unsigned ( <NUM_LIT> , <NUM_LIT> ) , false ) ; b -> addInit ( <STR_LIT> , <NUM_LIT> , b -> dec_unsigned ( <NUM_LIT> , <NUM_LIT>


<s> } if ( getLexer ( ) . is ( AsmToken :: LBrac ) ) return ParseIntelBracExpression ( SegReg , Start , ImmDisp , Size ) ; const MCExpr * Val ; SMLoc End ; if ( ! isParsingInlineAsm ( ) ) { if ( getParser ( ) . parsePrimaryExpr ( Val , End ) ) return ErrorOperand ( Tok . getLoc ( ) , <STR_LIT> ) ; return <STR_LIT> ( getPointerWidth ( ) , Val , Start , End , Size ) ; } InlineAsmIdentifierInfo Info ; StringRef Identifier = Tok . getString ( ) ; if ( ParseIntelIdentifier ( Val , Identifier , Info ,


<s> gcc_assert ( ptr -> arch < PROCESSOR_max ) ; fprintf ( file , <STR_LIT> , indent , <STR_LIT> , ptr -> arch , processor_target_table [ ptr -> arch ] . name ) ; gcc_assert ( ptr -> tune < PROCESSOR_max ) ; fprintf ( file , <STR_LIT> , indent , <STR_LIT> , ptr -> tune , processor_target_table [ ptr -> tune ] . name ) ; fprintf ( file , <STR_LIT> , indent , <STR_LIT> , ptr -> branch_cost ) ; if ( target_string


<s> DebugLoc DL ; if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) . add ( predOps ( <STR_LIT> ) ) ; return ; } if ( <STR_LIT> . hasSubClassEq ( RC ) ) { if ( TargetRegisterInfo :: isVirtualRegister ( DestReg ) ) { MachineRegisterInfo * MRI = & MF


<s> unsigned postKnownBits ( Align Align = Align :: None ( ) ) const { return std :: max ( Log2 ( std :: max ( PostAlign ,


<s> } Parser . Lex ( ) ; SMLoc ExLoc = Parser . getTok ( ) . getLoc ( ) ; const MCExpr * ShiftAmount ; SMLoc EndLoc ; if ( getParser ( ) . parseExpression ( ShiftAmount , EndLoc ) ) { Error ( ExLoc , <STR_LIT> ) ; return MatchOperand_ParseFail ; } const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( ShiftAmount ) ; if ( ! CE ) { Error ( ExLoc , <STR_LIT> ) ; return MatchOperand_ParseFail ; } int64_t Val = CE -> getValue ( ) ; if ( Val != <NUM_LIT> && Val != <NUM_LIT> && Val != <NUM_LIT> && Val != <NUM_LIT> ) { Error ( ExLoc , <STR_LIT> ) ; return MatchOperand_ParseFail ; } Operands . push_back ( <ISA_LIT>Operand :: CreateRotImm ( Val , S , EndLoc ) ) ; return MatchOperand_Success


<s> RC = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; RC = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; RC = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; RC = <STR_LIT> ; break ; case <STR_LIT> : if ( Subtarget -> hasSSE1 ( ) ) { Opc = <STR_LIT> ; RC = <STR_LIT> ; } else { Opc = <STR_LIT> ; RC = <STR_LIT> ; } break ; case <STR_LIT> : if ( Subtarget -> hasSSE2 ( ) ) { Opc = <STR_LIT> ; RC = <STR_LIT> ; } else { Opc = <STR_LIT> ; RC = <STR_LIT> ; } break ; case <STR_LIT> : return false ; } if ( isa < GlobalValue > ( C ) ) { <ISA_LIT>AddressMode AM ; if ( <ISA_LIT>SelectAddress ( C , AM , false ) ) { if ( TLI . getPointerTy ( ) == <STR_LIT> ) Opc = <STR_LIT> ; else Opc = <STR_LIT> ; unsigned ResultReg = createResultReg ( RC ) ; addFullAddress ( BuildMI ( MBB , DL , TII . get ( Opc ) , ResultReg ) , AM ) ; return ResultReg ; } return <NUM_LIT> ; } unsigned Align = TD . getPrefTypeAlignment ( C -> getType ( ) ) ; if ( Align ==


<s> ModulePass * llvm :: create<ISA_LIT>AbstractMemberAccess ( <ISA_LIT>TargetMachine * TM ) { return new <ISA_LIT>AbstractMemberAccess (


<s> MCAsmBackend * llvm :: create<ISA_LIT>AsmBackend ( const Target & T , const MCSubtargetInfo & STI , const MCRegisterInfo & MRI , const MCTargetOptions & Options ) { const Triple & TT = STI .


<s> bool <ISA_LIT>RegisterInfo :: trackLivenessAfterRegAlloc ( const MachineFunction & MF ) const { return true


<s> bool IsPredicatedOn ( MachineInstr * MI ) const { return VPST -> Predicates .


<s> if ( lookup_attribute ( <STR_LIT> , attrs ) ) return INTERRUPT_HANDLER ; else if ( lookup_attribute ( <STR_LIT> , attrs ) ) return EXCPT_HANDLER ; else if ( lookup_attribute ( <STR_LIT> , attrs )


<s> return CurDAG -> getConstant ( MulFactor , SDLoc ( N ) , N -> getOperand ( <NUM_LIT> )


<s> const IntrinsicVector & getMax ( ) const { return Max


<s> case S2_storerhabs : case S4_storeirh_io : case S2_storerhgp : case S2_storerf_io : case S4_storerf_rr : case S2_storerfabs : case S2_storerfgp : case S2_storeri_io : case S4_storeri_rr : case S2_storeriabs : case S4_storeiri_io : case S2_storerigp : case S2_storerd_io : case S4_storerd_rr : case S2_storerdabs : case S2_storerdgp : return true ; } return false


<s> void addLoImm16AndOperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT>


<s> bool Error ( SMLoc L , const Twine & Msg ) { return Parser . Error ( L


<s> return new <ISA_LIT>Disassembler :: <ISA_LIT>GenericDisassembler ( STI , MODE_32BIT , T


<s> return ( int64x1_t ) __builtin_neon_vld1_lanedi ( ( const __builtin_neon_di * ) __a ,


<s> bool <ISA_LIT>RegisterInfo :: canRealignStack ( const


<s> const MCOperand MO = MI . getOperand ( Op ) ; if ( MO . isImm ( ) ) { unsigned value = MO . getImm ( ) ; return static_cast < unsigned > ( value - <NUM_LIT> ) ; } assert ( MO . isExpr ( ) ) ; <STR_LIT> FixupKind = <STR_LIT> ; Fixups . push_back ( MCFixup :: create ( <NUM_LIT> , MO . getExpr ( ) , MCFixupKind ( FixupKind ) ) ) ; return <NUM_LIT>


<s> SDValue <ISA_LIT>TargetLowering :: LowerATOMIC_CMP_SWAP ( SDValue Op , SelectionDAG & DAG ) const { assert ( Op . getOpcode ( ) == <STR_LIT> && <STR_LIT> ) ; SDLoc dl ( Op ) ; auto * AtomicNode = cast < AtomicSDNode > ( Op . getNode ( ) ) ; EVT MemVT = AtomicNode -> getMemoryVT ( ) ; if ( MemVT . getSizeInBits ( ) >= <NUM_LIT> ) return Op ; SDValue CmpOp = Op . getOperand ( <NUM_LIT> ) ; auto HighBits = APInt :: getHighBitsSet ( <NUM_LIT> , <NUM_LIT> - MemVT . getSizeInBits ( ) ) ; if ( DAG . MaskedValueIsZero ( CmpOp , HighBits ) ) return Op ; unsigned MaskVal = ( <NUM_LIT> << MemVT . getSizeInBits ( ) ) - <NUM_LIT> ; SDValue NewCmpOp = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , CmpOp , DAG . getConstant ( MaskVal , dl , <STR_LIT> ) ) ; SmallVector < SDValue , <NUM_LIT> >


<s> if ( Reg == <STR_LIT> ) return MCDisassembler :: Fail ; Inst . addOperand ( MCOperand :: createReg ( Reg )


<s> if ( TREE_CODE ( exp ) == STRING_CST || TREE_CODE ( exp ) == CONSTRUCTOR ) return MAX ( align , BITS_PER_WORD ) ; return align


<s> } else if ( STI . hasFeature ( <STR_LIT> ) ) emitFPU ( <STR_LIT> ) ; else emitFPU ( STI . hasFeature ( <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ) ; if ( STI . hasFeature ( <STR_LIT> ) ) emitAttribute ( <STR_LIT> , STI . hasFeature ( <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ) ; } else { if ( STI . hasFeature ( <STR_LIT> ) ) emitFPU ( STI . hasFeature ( <STR_LIT> ) ? <STR_LIT> : ( STI . hasFeature ( <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ) ) ; else if ( STI . hasFeature ( <STR_LIT> ) ) emitFPU ( STI . hasFeature ( <STR_LIT> ) ? <STR_LIT> : ( STI . hasFeature ( <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ) ) ; else if ( STI . hasFeature ( <STR_LIT> ) ) emitFPU ( STI . hasFeature ( <STR_LIT> ) ? ( STI . hasFeature ( <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ) : ( STI . hasFeature ( <STR_LIT> ) ? ( STI . hasFeature ( <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ) : ( STI . hasFeature ( <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ) ) ) ; else if ( STI . hasFeature ( <STR_LIT> ) ) emitFPU ( <STR_LIT> ) ; } if ( STI . hasFeature ( <STR_LIT> ) && ! STI . hasFeature ( <STR_LIT> ) ) emitAttribute ( <STR_LIT> , <STR_LIT> ) ; if ( STI . hasFeature ( <STR_LIT> ) ) emitAttribute ( <STR_LIT> , <STR_LIT> ) ; if ( STI . hasFeature ( <STR_LIT> ) ) emitAttribute ( <STR_LIT> , <STR_LIT> ) ; if ( STI . hasFeature ( <STR_LIT> ) ) emitAttribute ( <STR_LIT> , <STR_LIT> ) ; else if ( STI . hasFeature ( <STR_LIT> ) ) emitAttribute ( <STR_LIT> , <STR_LIT> ) ; if ( STI . hasFeature ( <STR_LIT> ) && ! STI . hasFeature ( <STR_LIT> ) ) emitAttribute ( <STR_LIT> , <STR_LIT> ) ; if ( STI . hasFeature ( <STR_LIT> ) && isV8M ( STI )


<s> static MCStreamer * createMCAsmStreamer ( MCContext & Ctx , formatted_raw_ostream & OS , bool isVerboseAsm , bool useLoc , bool useCFI , bool useDwarfDirectory , MCInstPrinter * InstPrint , MCCodeEmitter * CE , MCAsmBackend * TAB , bool ShowInst ) { <ISA_LIT>TargetStreamer * S = new <ISA_LIT>TargetAsmStreamer


<s> assert ( Size >= <NUM_LIT> ) ; RegInterval Result ; Result . first = TRI -> getEncodingValue ( Reg . getReg ( ) ) ; Result . second = Result . first + Size / <NUM_LIT> ; return


<s> bool FirstFeature = true ; std :: string Msg = <STR_LIT> ; for ( unsigned i = <NUM_LIT> , e = MissingFeatures . size ( ) ; i != e ; ++ i ) { if ( MissingFeatures [ i ] ) { Msg += FirstFeature ? <STR_LIT> : <STR_LIT> ; Msg += getSubtargetFeatureName ( i ) ; FirstFeature = false ; } } return Error ( IDLoc , Msg ) ; } case Match_MnemonicFail : { FeatureBitset FBS = ComputeAvailableFeatures ( getSTI ( ) . getFeatureBits ( ) ) ; std :: string Suggestion = <ISA_LIT>MnemonicSpellCheck ( ( ( <ISA_LIT>Operand & ) * Operands [ <NUM_LIT> ] ) . getToken ( ) , FBS , <NUM_LIT> ) ; return Error ( IDLoc , <STR_LIT> + Suggestion ) ; } case Match_InvalidOperand : { SMLoc ErrorLoc = IDLoc ; if ( ErrorInfo != ~ <NUM_LIT> ) { if ( ErrorInfo >= Operands . size ( ) ) return Error ( ErrorLoc , <STR_LIT> ) ; ErrorLoc = ( ( <ISA_LIT>Operand & ) * Operands [ ErrorInfo ] ) . getStartLoc ( ) ; if ( ErrorLoc == SMLoc ( ) ) ErrorLoc = IDLoc ; } return Error ( ErrorLoc , <STR_LIT> ) ; } } if ( Result > FIRST_TARGET_MATCH_RESULT_TY ) { SMLoc ErrorLoc = IDLoc ; if ( ErrorInfo != ~ <NUM_LIT> && ErrorInfo >= Operands . size ( ) ) return Error ( ErrorLoc , <STR_LIT> ) ; } switch ( Result ) { default : break ; case Match_InvalidUImm2 : return generateImmOutOfRangeError ( Operands , ErrorInfo , <NUM_LIT> , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) ; case Match_InvalidUImm2plus1 : return generateImmOutOfRangeError ( Operands , ErrorInfo , <NUM_LIT> , ( <NUM_LIT> << <NUM_LIT> ) ) ; case Match_InvalidUImm3 : return generateImmOutOfRangeError ( Operands , ErrorInfo , <NUM_LIT> , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) ; case Match_InvalidUImm5 : return generateImmOutOfRangeError ( Operands , ErrorInfo , <NUM_LIT> , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) ; case Match_InvalidUImm6 : return generateImmOutOfRangeError ( Operands , ErrorInfo , <NUM_LIT> , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) ; case Match_InvalidUImm12 : return generateImmOutOfRangeError ( Operands , ErrorInfo , <NUM_LIT> , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) ; case Match_InvalidUImm15 : return generateImmOutOfRangeError ( Operands , ErrorInfo , <NUM_LIT> , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) ; case Match_InvalidSImm12 : return generateImmOutOfRangeError ( Operands , ErrorInfo , - ( <NUM_LIT> << <NUM_LIT> ) , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) ; case Match_InvalidSImm14lsl2 : return generateImmOutOfRangeError ( Operands , ErrorInfo , - ( <NUM_LIT> << <NUM_LIT> ) , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> , <STR_LIT> ) ; case Match_InvalidSImm16 : return generateImmOutOfRangeError ( Operands , ErrorInfo , - ( <NUM_LIT> << <NUM_LIT> ) , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) ; case Match_InvalidSImm16lsl2 : return generateImmOutOfRangeError ( Operands , ErrorInfo , - ( <NUM_LIT> << <NUM_LIT> ) , (


<s> static inline int getFP64Imm ( const APFloat &


<s> default : report_fatal_error ( <STR_LIT> ) ; case CallingConv :: C : case CallingConv :: Fast : break ; } MachineFunction & MF = DAG . getMachineFunction ( ) ; MachineRegisterInfo & RegInfo = MF . getRegInfo ( ) ; if ( IsVarArg ) report_fatal_error ( <STR_LIT> ) ; SmallVector < CCValAssign , <NUM_LIT> > ArgLocs ; CCState CCInfo ( CallConv , IsVarArg , MF , ArgLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeFormalArguments ( Ins , CC_<ISA_LIT> ) ; for ( auto & VA : ArgLocs ) { SDValue ArgVal ; if ( VA . isRegLoc ( ) ) { EVT RegVT = VA . getLocVT ( ) ; if ( RegVT != <STR_LIT> ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << RegVT . getEVTString (


<s> __v8hu rshift = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; __v8hi result ; if ( __B < <NUM_LIT> ) { if ( __builtin_constant_p ( __B ) ) rshift = ( __v8hu ) vec_splat_s16 ( __B ) ; else rshift = vec_splats ( ( unsigned short ) __B ) ; } result = vec_sra ( ( __v8hi ) __A , rshift ) ; return ( __m128i ) result


<s> inline bool isImmSExti32i8Value ( uint64_t Value ) { return ( ( Value <= <NUM_LIT> ) || ( <NUM_LIT> <= Value && Value <= <NUM_LIT> ) || ( <NUM_LIT>


<s> virtual const <ISA_LIT>TargetLowering * getTargetLowering (


<s> for ( auto & Arg : F . args ( ) ) { if ( DL . getTypeStoreSize ( Arg . getType ( ) ) == <NUM_LIT> ) continue ; const bool InReg = Arg . hasAttribute ( Attribute :: InReg ) ; if ( ! IsShader && InReg ) return false ; if ( Arg . hasAttribute ( Attribute :: SwiftSelf ) || Arg . hasAttribute ( Attribute :: SwiftError ) || Arg . hasAttribute ( Attribute :: Nest ) ) return false ; if ( CC == CallingConv :: <ISA_LIT>_PS && ! InReg && P<ISA_LIT>nputNum <= <NUM_LIT> ) { const bool ArgUsed = ! Arg . use_empty ( ) ; bool SkipArg = ! ArgUsed && ! Info -> isP<ISA_LIT>nputAllocated ( P<ISA_LIT>nputNum ) ; if ( ! SkipArg ) { Info -> markP<ISA_LIT>nputAllocated ( P<ISA_LIT>nputNum ) ; if ( ArgUsed ) Info -> markP<ISA_LIT>nputEnabled ( P<ISA_LIT>nputNum ) ; } ++ P<ISA_LIT>nputNum ; if ( SkipArg ) { for ( int I = <NUM_LIT> , E = VRegs [ Idx ] . size ( ) ; I != E ; ++ I ) B . buildUndef ( VRegs [ Idx ] [ I ] ) ; ++ Idx ; continue ; } } ArgInfo OrigArg ( VRegs [ Idx ] , Arg . getType ( ) ) ; const unsigned OrigArgIdx = Idx + AttributeList :: FirstArgIndex ; setArgFlags ( OrigArg , OrigArgIdx , DL , F ) ; splitToValueTypes ( B , OrigArg , OrigArgIdx , SplitArgs , DL , CC , [ & ] ( ArrayRef < Register > Regs , Register DstReg , LLT LLTy , LLT PartLLT , int VTSplitIdx ) { assert ( DstReg == VRegs [ Idx ] [ VTSplitIdx ] ) ; packSplitRegsToOrigType ( B , VRegs [ Idx ] [ VTSplitIdx ] , Regs , LLTy , PartLLT ) ; } ) ; ++ Idx ; } if ( CC == CallingConv :: <ISA_LIT>_PS ) { if ( ( Info -> getP<ISA_LIT>nputAddr ( ) & <NUM_LIT> ) == <NUM_LIT> || ( ( Info -> getP<ISA_LIT>nputAddr ( ) & <NUM_LIT> ) == <NUM_LIT> && Info -> isP<ISA_LIT>nputAllocated ( <NUM_LIT> ) ) ) { CCInfo . AllocateReg ( <STR_LIT> ) ; CCInfo . AllocateReg ( <STR_LIT> ) ; Info -> markP<ISA_LIT>nputAllocated (


<s> switch ( N -> getOpcode ( ) ) { case <STR_LIT> : { if ( const ConstantSDNode * C = dyn_cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ) { SDValue Sub = DAG . getNode ( <STR_LIT> , DL , N -> getValueType ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , DAG . getConstant ( - C -> getAPIntValue ( ) , DL , C -> getValueType ( <NUM_LIT> ) ) ) ; Results . push_back ( Sub )


<s> return __builtin_mve_vclsq_m_sv4si ( __inactive ,


<s> if ( Filled ) { MachineBasicBlock :: instr_iterator DSI = I . getInstrIterator ( ) ; if ( InMicro<ISA_LIT>Mode && TII -> getInstSizeInBytes ( * std :: next ( DSI ) ) == <NUM_LIT> && DSI -> isCall ( ) ) { DSI -> setDesc ( TII -> get ( getEquivalentCallShort ( DSI -> getOpcode ( ) ) ) ) ; } ++ FilledSlots ; Changed = true ; continue ; } } if ( ( InMicro<ISA_LIT>Mode || ( STI . has<ISA_LIT>32r6 ( ) && <ISA_LIT>CompactBranchPolicy != CB_Never ) ) && TII -> getEquivalentCompactForm ( I ) ) { I = replaceWithCompactBranch ( MBB , I , I -> getDebugLoc ( ) ) ; Changed = true ; continue ; } LLVM_DEBUG ( dbgs ( ) << DEBUG_TYPE << <STR_LIT> ; I -> dump ( ) ) ; TII -> insertNop ( MBB , std :: next ( I


<s> unsigned <ISA_LIT>MCCodeEmitter :: getShiftRightImm64 ( const MCInst & MI , unsigned Op , SmallVectorImpl <

MCFixup > & Fixups , const MCSubtargetInfo & STI ) const {


<s> return ( uint8x8_t ) __builtin_neon_vreinterpretv8qiv8qi ( ( int8x8_t


<s> Lexer . Lex ( ) ; if ( Lexer . isNot ( AsmToken :: Integer ) ) { Err << <STR_LIT> ; return


<s> TargetPassConfig * <ISA_LIT>TargetMachine :: createPassConfig ( PassManagerBase & PM


<s> bool rs6000_keep_leaf_when_profiled ( void


<s> case <STR_LIT> : return SelectConstantFP ( N ) ; case <STR_LIT> : return SelectFrameIndex ( N ) ; case <STR_LIT> : return SelectAdd ( N ) ; case <STR_LIT> : return SelectSHL ( N ) ; case <STR_LIT> : return SelectLoad ( N ) ; case <STR_LIT> : return SelectStore ( N ) ; case <STR_LIT> : return SelectMul ( N ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return SelectBitOp ( N ) ; case <STR_LIT> : return SelectZeroExtend ( N ) ; case <STR_LIT>


<s> const uint32_t * <ISA_LIT>RegisterInfo :: getCallPreservedMask ( CallingConv :: ID CC ) const { bool HasAVX = Subtarget . hasAVX ( ) ; bool HasAVX512 = Subtarget . hasAVX512 ( ) ; switch ( CC ) { case CallingConv :: GHC : case CallingConv :: HiPE : return CSR_NoRegs_RegMask ; case CallingConv :: AnyReg : if ( HasAVX ) return CSR_64_AllRegs_AVX_RegMask ; return CSR_64_AllRegs_RegMask ; case CallingConv :: PreserveMost : return CSR_64_RT_MostRegs_RegMask ; case CallingConv :: PreserveAll : if ( HasAVX ) return CSR_64_RT_AllRegs_AVX_RegMask ; return CSR_64_RT_AllRegs_RegMask ; case CallingConv :: Intel_OCL_BI : { if ( HasAVX512 && IsWin64 ) return CSR_Win64_Intel_OCL_BI_AVX512_RegMask ; if ( HasAVX512 && Is64Bit ) return CSR_64_Intel_OCL_BI_AVX512_RegMask ; if ( HasAVX && IsWin64

) return CSR_Win64_Intel_OCL_BI_AVX_RegMask ;


<s> return create<ISA_LIT>MCSubtargetInfoImpl ( TT , CPU , FS


<s> unsigned <ISA_LIT>AsmParser :: IdentifyIntelInlineAsmOperator ( StringRef Name ) { return StringSwitch < unsigned > ( Name ) . Cases ( <STR_LIT> , <STR_LIT> , IOK_TYPE ) . Cases ( <STR_LIT> , <STR_LIT> , IOK_SIZE ) . Cases ( <STR_LIT> , <STR_LIT> , IOK_LENGTH ) . Cases ( <STR_LIT> , <STR_LIT> , IOK_OFFSET


<s> buildMovInstr ( MBB , MI , MI -> getOperand ( DstOpIdx ) . getReg ( ) , getIndirectAddrRegClass ( ) -> getRegister ( Address ) ) ; } else { buildIndirectRead ( MBB , MI , MI -> getOperand ( DstOpIdx ) . getReg ( ) , Address , OffsetReg ) ; } } else if ( isRegisterStore ( * MI ) ) { int ValOpIdx = <STR_LIT> ( MI -> getOpcode ( ) , <STR_LIT> :: val ) ; unsigned RegIndex = MI -> getOperand ( RegOpIdx ) . getImm ( ) ; unsigned Channel = MI -> getOperand ( ChanOpIdx ) . getImm ( ) ; unsigned Address = calculateIndirectAddress ( RegIndex , Channel ) ; unsigned OffsetReg = MI -> getOperand ( OffsetOpIdx ) . getReg ( ) ; if ( OffsetReg == <STR_LIT> ) { buildMovInstr ( MBB , MI , getIndirectAddrRegClass ( ) -> getRegister ( Address ) , MI -> getOperand ( ValOpIdx ) . getReg ( ) ) ; } else { buildIndirectWrite ( MBB , MI , MI -> getOperand ( ValOpIdx ) . getReg ( ) , calculateIndirectAddress ( RegIndex , Channel ) , OffsetReg ) ; } } else


<s> bool Modified = false ; for ( MachineBasicBlock & MBB : MF ) { for ( auto MBBI = MBB . begin ( ) , E = MBB . end ( ) ; MBBI != E ; ++ MBBI ) { MachineInstr & MI = * MBBI ; unsigned Opcode = MI . getOpcode ( ) ; if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) { for ( int InsertedCount = <NUM_LIT> ; InsertedCount < <NUM_LIT> ; InsertedCount ++ ) BuildMI (

MBB , MBBI , DL , TII . get ( <STR_LIT> ) ) ;


<s> unsigned reportPackets ( ) { return Top . ResourceModel -> getTotalPackets ( ) +

Bot . ResourceModel -> getTotalPackets ( ) ;


<s> SDNode * <ISA_LIT>SEDAGToDAGISel :: selectAddESubE ( unsigned MOp , SDValue InFlag , SDValue CmpLHS , DebugLoc DL , SDNode * Node ) const { unsigned Opc = InFlag . getOpcode ( ) ; ( void ) Opc ; assert ( ( ( Opc == <STR_LIT> || Opc == <STR_LIT> ) || ( Opc == <STR_LIT> || Opc == <STR_LIT> ) ) && <STR_LIT> ) ; SDValue Ops [ ] = { CmpLHS , InFlag . getOperand ( <NUM_LIT> ) } ; SDValue LHS = Node -> getOperand ( <NUM_LIT> ) , RHS = Node -> getOperand ( <NUM_LIT> ) ; EVT VT = LHS . getValueType ( ) ; SDNode * Carry = CurDAG -> getMachineNode ( <STR_LIT> , DL , VT , Ops ) ; SDNode * AddCarry = CurDAG -> getMachineNode ( <STR_LIT> , DL , VT , SDValue ( Carry , <NUM_LIT> ) , RHS ) ; return CurDAG -> SelectNodeTo ( Node , MOp , VT , <STR_LIT>

, LHS , SDValue ( AddCarry , <NUM_LIT> ) ) ;


<s> mips_reorg_process_insns ( ) ; if ( ! TARGET_MIPS16 && TARGET_EXPLICIT_RELOCS && TUNE_MIPS4130 && TARGET_VR4130_ALIGN ) vr4130_align_insns ( ) ; if ( mips_expand_ghost_gp_insns ( ) ) mips_reorg_process_insns


<s> if ( Constraint . size ( ) == <NUM_LIT> ) { switch ( Constraint [ <NUM_LIT> ] ) { case 'r' : if ( VT . getSizeInBits ( ) == <NUM_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; case 'w' : if ( VT == <STR_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; if ( VT . getSizeInBits ( ) == <NUM_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; if ( VT . getSizeInBits ( ) == <NUM_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; break ; case 'x' : if ( VT . getSizeInBits ( ) == <NUM_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; break ; } } if ( StringRef ( <STR_LIT> ) . equals_lower ( Constraint ) ) return std :: make_pair ( unsigned ( <STR_LIT> ) , & <STR_LIT> ) ; std :: pair < unsigned , const TargetRegisterClass * > Res ; Res = TargetLowering :: getRegForInlineAsmConstraint (


<s> if ( IsABICalls ) { TS . emitDirectiveAbiCalls ( ) ; if ( ! isPositionIndependent ( ) && ! ABI . IsN64 ( ) ) TS . emitDirectiveOptionPic0 ( ) ; } std :: string SectionName = std :: string ( <STR_LIT> ) + getCurrentABIString ( ) ; OutStreamer -> SwitchSection ( OutContext . getELFSection ( SectionName , ELF :: SHT_PROGBITS , <NUM_LIT> ) ) ; STI . isNaN2008 ( ) ? TS . emitDirectiveNaN2008 ( ) : TS . emitDirectiveNaNLegacy ( ) ; TS . updateABIInfo ( STI ) ; if ( ABI . IsO32 ( ) && ( STI . isABI_FPXX ( ) ||

STI . isFP64bit ( ) ) ) TS . emitDirectiveModuleFP ( ) ;


<s> case <STR_LIT> : return true ; case <STR_LIT> : return true ; case <STR_LIT> : return true ; case <STR_LIT> : return true ; case <STR_LIT> : return true ; case <STR_LIT> : return true ; case <STR_LIT> : return true ; case <STR_LIT> : return true ; case <STR_LIT> : return true ; case <STR_LIT> : return true ; case <STR_LIT> : return true ; case <STR_LIT> : return true ; case <STR_LIT> : return true ; case <STR_LIT> : return


<s> if ( __builtin_expect ( __builtin_tbegin ( <NUM_LIT> ) , <NUM_LIT> )


<s> void <ISA_LIT>AsmPrinter :: printOperand ( const MachineInstr * MI , unsigned OpNum , raw_ostream & O ) { const MachineOperand & MO = MI -> getOperand ( OpNum ) ; switch ( MO . getType ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case MachineOperand :: MO_Register : { unsigned Reg = MO . getReg ( ) ; assert ( TargetRegisterInfo :: isPhysicalRegister ( Reg ) ) ; assert ( ! MO . getSubReg ( ) && <STR_LIT> ) ; O << <ISA_LIT>InstPrinter :: getRegisterName ( Reg ) ; break ; } case MachineOperand :: MO_Immediate : { O << MO . getImm ( ) ; break ; } case MachineOperand :: MO_GlobalAddress : { PrintSymbolOperand ( MO , O ) ; break ; } case MachineOperand :: MO_BlockAddress


<s> case L2_loadbzw4_pcr : case L2_loadbzw4_pi : case L2_loadrbgp : case L2_loadrb_io : case L2_loadrb_pbr : case L2_loadrb_pci : case L2_loadrb_pcr : case L2_loadrb_pi : case PS_loadrbabs : case L4_loadrb_ap : case L4_loadrb_rr : case L4_loadrb_ur : BitNum = <NUM_LIT> ; SignEx = true ; break ; case L2_loadrubgp : case L2_loadrub_io : case L2_loadrub_pbr : case L2_loadrub_pci : case L2_loadrub_pcr : case L2_loadrub_pi : case PS_loadrubabs : case L4_loadrub_ap : case L4_loadrub_rr : case L4_loadrub_ur : BitNum = <NUM_LIT> ; SignEx = false ; break ; case L2_loadrhgp : case L2_loadrh_io : case L2_loadrh_pbr : case L2_loadrh_pci : case L2_loadrh_pcr : case L2_loadrh_pi : case PS_loadrhabs : case L4_loadrh_ap : case L4_loadrh_rr : case L4_loadrh_ur : BitNum = <NUM_LIT> ; SignEx = true ; break ; case L2_loadruhgp : case L2_loadruh_io : case L2_loadruh_pbr : case L2_loadruh_pci : case L2_loadruh_pcr : case L2_loadruh_pi : case L4_loadruh_rr : case PS_loadruhabs : case L4_loadruh_ap : case L4_loadruh_ur : BitNum = <NUM_LIT> ; SignEx = false ; break ; case L2_loadrigp : case L2_loadri_io : case L2_loadri_pbr : case L2_loadri_pci : case L2_loadri_pcr : case L2_loadri_pi : case L2_loadw_locked : case PS_loadriabs : case L4_loadri_ap : case L4_loadri_rr : case L4_loadri_ur : case LDriw_pred : BitNum = <NUM_LIT> ; SignEx = true ; break ; case L2_loadrdgp : case L2_loadrd_io : case L2_loadrd_pbr : case L2_loadrd_pci : case L2_loadrd_pcr : case L2_loadrd_pi : case L4_loadd_locked : case PS_loadrdabs : case L4_loadrd_ap : case L4_loadrd_rr : case L4_loadrd_ur : BitNum = <NUM_LIT> ; SignEx = true ; break ; } const MachineOperand & MD = MI . getOperand ( <NUM_LIT> ) ; assert ( MD . isReg ( ) && MD . isDef ( ) ) ; RegisterRef RD = MD ; uint16_t W = getRegBitWidth ( RD ) ; assert ( W >= BitNum && BitNum > <NUM_LIT> ) ; RegisterCell Res ( W ) ; for ( uint16_t i = <NUM_LIT> ; i < BitNum ; ++ i ) Res [ i ] = BT :: BitValue :: self ( BT :: BitRef ( RD . Reg , i ) ) ; if ( SignEx ) { const BT :: BitValue & Sign = Res [ BitNum - <NUM_LIT> ] ; for ( uint16_t i = BitNum ; i < W ; ++ i ) Res [ i ] = BT :: BitValue :: ref ( Sign ) ; }


<s> int GCNHazardRecognizer :: checkSMRDHazards ( MachineInstr * SMRD ) { const <ISA_LIT>Subtarget & ST = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; int WaitStatesNeeded = <NUM_LIT> ; WaitStatesNeeded = checkSMEMSoftClauseHazards ( SMRD ) ; if ( ST . getGeneration ( )

!= <ISA_LIT>Subtarget :: SOUTHERN_ISLANDS ) return WaitStatesNeeded ;


<s> APFloat RealVal ( APFloat :: IEEEdouble ( ) , ImmOp64 ) ; ImmOp64 = RealVal . bitcastToAPInt ( ) . getZExtValue


<s> if ( AFI -> isThumb1OnlyFunction ( ) ) return false ; if ( ! MRI -> canReserveReg ( FramePtr ) ) return false ; if ( MF . getTarget ( ) . getFrameLowering ( ) -> hasReservedCallFrame ( MF ) )


<s> static SDValue splitIntVSETCC ( EVT VT , SDValue LHS , SDValue RHS , <STR_LIT> Cond , SelectionDAG & DAG , const SDLoc & dl ) { assert ( VT . isInteger ( ) && VT == LHS . getValueType ( ) && VT == RHS . getValueType ( ) && <STR_LIT> ) ; SDValue CC = DAG . getCondCode ( Cond ) ; SDValue LHS1 , LHS2 ; std :: tie ( LHS1 , LHS2 ) = splitVector ( LHS , DAG , dl ) ; SDValue RHS1 , RHS2 ; std :: tie ( RHS1 , RHS2 ) = splitVector ( RHS , DAG , dl ) ; EVT LoVT , HiVT ; std :: tie ( LoVT , HiVT ) = DAG


<s> MCELFObjectTargetWriter * MOTW = new AMDGPUELFObjectWriter ( ) ; return createELFObjectWriter ( MOTW , OS , true


<s> accessor . base = stack_pointer_rtx ; accessor . base_offset = <NUM_LIT> ; } { rtx asm_offset = frv_frame_offset_rtx ( - info -> total_size ) ; rtx dwarf_offset = GEN_INT ( - info -> total_size ) ; frv_frame_insn ( gen_stack_adjust ( sp , sp , asm_offset ) , gen_rtx_SET ( sp , gen_rtx_PLUS ( Pmode , sp , dwarf_offset ) ) ) ; } if ( frame_pointer_needed ) { int fp_offset = info -> reg_offset [ FRAME_POINTER_REGNUM ] ; rtx asm_src = plus_constant ( Pmode , accessor . base , fp_offset - accessor . base_offset ) ; rtx dwarf_src = plus_constant ( Pmode , sp , fp_offset ) ; frv_frame_access ( & accessor , fp , fp_offset ) ; frv_frame_insn ( gen_rtx_SET ( fp , asm_src ) , gen_rtx_SET ( fp , dwarf_src ) ) ; accessor . base = fp ; accessor . base_offset =


<s> AU . setPreservesCFG ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU


<s> case SwitchError :: OK : return <STR_LIT> ; case SwitchError :: UnknownSwitch : return <STR_LIT> ; case SwitchError :: UnsupportedByHardware : return <STR_LIT> ; case SwitchError :: UnapplicableForType


<s> bool <ISA_LIT>GNULDBackend :: mergeSection ( Module & pModule ,

const Input & pInput , LDSection & pSection ) {


<s> ScheduleDAGInstrs * createMachineScheduler ( MachineSchedContext * C ) const override { return create<ISA_LIT>MachineScheduler (


<s> return AltMappings ; } case TargetOpcode :: G_ICMP : { unsigned Size = getSizeInBits ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) , MRI , * TRI ) ; const InstructionMapping & SSMapping = getInstructionMapping ( <NUM_LIT> , <NUM_LIT> , getOperandsMapping ( { <STR_LIT> ( <STR_LIT> , <NUM_LIT> ) , nullptr , <STR_LIT> ( <STR_LIT> , Size ) , <STR_LIT> ( <STR_LIT> , Size ) } ) , <NUM_LIT> ) ; AltMappings . push_back ( & SSMapping ) ; const InstructionMapping & SVMapping = getInstructionMapping ( <NUM_LIT> , <NUM_LIT> , getOperandsMapping ( { <STR_LIT> ( <STR_LIT> , <NUM_LIT> ) , nullptr , <STR_LIT> ( <STR_LIT> , Size ) , <STR_LIT> ( <STR_LIT> , Size ) } ) , <NUM_LIT> ) ; AltMappings . push_back ( & SVMapping ) ; const InstructionMapping & VSMapping = getInstructionMapping ( <NUM_LIT> , <NUM_LIT> , getOperandsMapping ( { <STR_LIT> ( <STR_LIT> , <NUM_LIT> ) , nullptr , <STR_LIT> ( <STR_LIT> , Size ) , <STR_LIT> ( <STR_LIT> , Size ) } ) , <NUM_LIT> ) ; AltMappings . push_back ( & VSMapping ) ; const InstructionMapping & VVMapping = getInstructionMapping ( <NUM_LIT> , <NUM_LIT> , getOperandsMapping ( { <STR_LIT> ( <STR_LIT> , <NUM_LIT> ) , nullptr , <STR_LIT> ( <STR_LIT> , Size ) , <STR_LIT> ( <STR_LIT> , Size ) } ) , <NUM_LIT> ) ; AltMappings . push_back ( & VVMapping ) ; return AltMappings ; } case TargetOpcode :: G_SELECT : { unsigned Size = getSizeInBits ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) , MRI , * TRI ) ; const InstructionMapping & SSMapping = getInstructionMapping ( <NUM_LIT> , <NUM_LIT> , getOperandsMapping ( { <STR_LIT> ( <STR_LIT> , Size ) , <STR_LIT> ( <STR_LIT> , <NUM_LIT> ) , <STR_LIT> ( <STR_LIT>


<s> RegisterTargetMachine < <ISA_LIT>TargetMachine > X ( getThe<ISA_LIT>Target


<s> if ( NumArg != <NUM_LIT> && NumArg != <NUM_LIT> ) return false ; auto * PacketSize = CI -> getArgOperand ( NumArg - <NUM_LIT> ) ; auto * PacketAlign = CI -> getArgOperand ( NumArg - <NUM_LIT> ) ; if ( ! isa < ConstantInt > ( PacketSize ) || ! isa < ConstantInt > ( PacketAlign ) ) return false ; unsigned Size = cast < ConstantInt > ( PacketSize ) -> getZExtValue ( ) ; unsigned Align = cast < ConstantInt > ( PacketAlign ) -> getZExtValue ( ) ; if ( Size != Align || ! isPowerOf2_32 ( Size ) ) return false ; Type * PtrElemTy ; if ( Size <= <NUM_LIT> ) PtrElemTy = Type :: getIntNTy ( Ctx , Size * <NUM_LIT> ) ; else PtrElemTy = VectorType :: get ( Type :: getInt64Ty ( Ctx ) , Size / <NUM_LIT> ) ; unsigned PtrArgLoc = CI -> getNumArgOperands ( ) - <NUM_LIT> ; auto PtrArg = CI -> getArgOperand ( PtrArgLoc ) ; unsigned PtrArgAS = PtrArg -> getType ( ) -> getPointerAddressSpace ( ) ; auto * PtrTy = llvm :: PointerType :: get ( PtrElemTy , PtrArgAS ) ; SmallVector < llvm :: Type * , <NUM_LIT> > ArgTys ; for ( unsigned I = <NUM_LIT> ; I != PtrArgLoc ; ++ I ) ArgTys . push_back ( CI -> getArgOperand ( I ) -> getType ( ) ) ; ArgTys . push_back ( PtrTy ) ; Name = Name + <STR_LIT> + std :: to_string ( Size ) ; auto * FTy = FunctionType :: get ( Callee -> getReturnType ( ) , ArrayRef < Type * > ( ArgTys ) , false ) ; <ISA_LIT>LibFunc NewLibFunc ( Name , FTy ) ; FunctionCallee F = <ISA_LIT>LibFunc :: getOrInsertFunction ( M , NewLibFunc ) ; if ( ! F ) return false ; auto * BCast = B . CreatePointerCast ( PtrArg , PtrTy ) ; SmallVector < Value * , <NUM_LIT> > Args ; for ( unsigned I = <NUM_LIT> ; I != PtrArgLoc ; ++ I ) Args . push_back ( CI -> getArgOperand ( I ) ) ; Args . push_back ( BCast


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { SmallVector < std :: pair < MachineOperand * , <STR_LIT> > , <NUM_LIT> > OperandsToUpdate ; bool isSafe = false ; I = CmpInstr ; E = CmpInstr -> getParent ( ) -> end ( ) ; while ( ! isSafe && ++ I != E ) { const MachineInstr & Instr = * I ; for ( unsigned IO = <NUM_LIT> , EO = Instr . getNumOperands ( ) ; ! isSafe && IO != EO ; ++ IO ) { const MachineOperand & MO = Instr . getOperand ( IO ) ; if ( MO . isRegMask ( ) && MO . clobbersPhysReg ( <STR_LIT> ) ) { isSafe = true ; break ; } if ( ! MO . isReg ( ) || MO . getReg ( ) != <STR_LIT> ) continue ; if ( MO . isDef ( ) ) { isSafe = true ; break ; } <STR_LIT> CC = ( <STR_LIT> ) Instr . getOperand ( IO - <NUM_LIT> ) . getImm ( ) ; if ( Sub ) { <STR_LIT> NewCC = getSwappedCondition ( CC ) ; if ( NewCC == <STR_LIT> ) return false ; if ( SrcReg2 != <NUM_LIT> && Sub -> getOperand ( <NUM_LIT> ) . getReg ( ) == SrcReg2 && Sub -> getOperand ( <NUM_LIT> ) . getReg ( ) == SrcReg ) OperandsToUpdate . push_back ( std :: make_pair ( & ( ( * I ) . getOperand ( IO - <NUM_LIT> ) ) , NewCC ) ) ; } else switch ( CC ) { default : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return false ; } } } if ( ! isSafe ) { MachineBasicBlock * MBB = CmpInstr -> getParent ( ) ; for ( MachineBasicBlock :: succ_iterator SI = MBB -> succ_begin ( ) , SE = MBB -> succ_end ( ) ; SI != SE ; ++ SI ) if ( ( * SI ) -> isLiveIn ( <STR_LIT> ) ) return false ; } MI -> getOperand ( <NUM_LIT> ) . setReg ( <STR_LIT> ) ; MI -> getOperand ( <NUM_LIT> ) . setIsDef ( true ) ; CmpInstr -> eraseFromParent ( ) ; for ( unsigned i = <NUM_LIT> , e = OperandsToUpdate . size ( ) ; i < e ; i ++ ) OperandsToUpdate [ i ] . first -> setImm ( OperandsToUpdate [ i ] . second ) ; return true


<s> Inst . addOperand ( MCOperand :: createReg


<s> for ( MachineBasicBlock :: reverse_instr_iterator I = ++ Slot . getReverse ( ) ; I != MBB . instr_rend ( ) ; ++ I ) { if ( I -> isDebugValue ( ) ) continue ; MachineBasicBlock :: instr_iterator FI = I . getReverse ( ) ; if ( I -> hasUnmodeledSideEffects ( ) || I -> isInlineAsm ( ) || I -> isLabel (

) || FI == LastFiller || I -> isPseudo ( ) ) break ;


<s> switch ( MO . getType ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case MachineOperand :: MO_Register : O << <ISA_LIT>InstPrinter :: getRegisterName ( MO . getReg ( ) ) ; return ; case MachineOperand :: MO_Immediate : if ( ! Modifier || strcmp ( Modifier , <STR_LIT> ) ) O << '#' ; O << MO . getImm ( ) ; return ; case MachineOperand ::


<s> SDValue Chain = N -> getOperand ( <NUM_LIT> ) ; SDValue Addr = N -> getOperand ( <NUM_LIT> ) ; SDValue InFlag = N -> getOperand ( N -> getNumOperands ( ) - <NUM_LIT> ) ; DebugLoc dl = N -> getDebugLoc ( ) ; if ( Addr . getOpcode ( ) == <STR_LIT> ) { SDValue GOT = SDValue ( getGlobalBaseReg ( ) , <NUM_LIT> ) ; Chain = CurDAG -> getCopyToReg ( Chain , dl , <STR_LIT> , GOT


<s> oldval = operands [ <NUM_LIT> ] ; newval = operands [ <NUM_LIT> ] ; is_weak = ( operands [ <NUM_LIT> ] != const0_rtx ) ; mod_s = ( enum memmodel ) INTVAL ( operands [ <NUM_LIT> ] ) ; mod_f = ( enum memmodel ) INTVAL ( operands [ <NUM_LIT> ] ) ; mode = GET_MODE ( mem ) ; alpha_pre_atomic_barrier ( mod_s ) ; label1 = NULL_RTX ; if ( ! is_weak ) { label1 = gen_rtx_LABEL_REF ( DImode , gen_label_rtx ( ) ) ; emit_label ( XEXP ( label1 , <NUM_LIT> ) ) ; } label2 = gen_rtx_LABEL_REF ( DImode , gen_label_rtx ( ) ) ; emit_load_locked ( mode , retval , mem ) ; x = gen_lowpart ( DImode , retval ) ; if ( oldval == const0_rtx ) { emit_move_insn ( cond , const0_rtx ) ; x = gen_rtx_NE ( DImode , x , const0_rtx ) ; } else { x = gen_rtx_EQ ( DImode , x , oldval ) ; emit_insn ( gen_rtx_SET ( VOIDmode , cond , x ) ) ; x = gen_rtx_EQ ( DImode , cond , const0_rtx ) ; } emit_unlikely_jump ( x , label2 ) ; emit_move_insn ( cond , newval ) ; emit_store_conditional ( mode , cond , mem , gen_lowpart ( mode , cond ) ) ; if ( ! is_weak ) { x = gen_rtx_EQ ( DImode , cond , const0_rtx ) ; emit_unlikely_jump ( x


<s> New = SDValue ( CurDAG -> getMachineNode ( NewOpc , dl , NVT , New ) , <NUM_LIT> ) ; } MachineSDNode * NewNode ; SDValue Input = N0 -> getOperand ( <NUM_LIT> ) ; SDValue Tmp0 , Tmp1 , Tmp2 , Tmp3 , Tmp4 ; if ( tryFoldLoad ( Node , N0 . getNode ( ) , Input , Tmp0 , Tmp1 , Tmp2 , Tmp3 , Tmp4 ) ) { SDValue Ops [ ] = { Tmp0 , Tmp1 , Tmp2 , Tmp3 , Tmp4 , New , Input . getOperand ( <NUM_LIT> ) } ; SDVTList VTs = CurDAG -> getVTList ( NVT , <STR_LIT> , <STR_LIT> ) ; NewNode = CurDAG -> getMachineNode ( MOpc , dl , VTs , Ops ) ; ReplaceUses ( Input . getValue ( <NUM_LIT> ) , SDValue ( NewNode , <NUM_LIT> ) ) ; CurDAG -> setNodeMemRefs ( NewNode , { cast < LoadSDNode > ( Input ) -> getMemOperand ( ) } ) ; } else { NewNode = CurDAG -> getMachineNode ( ROpc , dl , NVT , <STR_LIT> , Input


<s> Register RHS = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; uint16_t Flags = MI . getFlags ( ) ; LLT S64 = LLT :: scalar ( <NUM_LIT> ) ; LLT S1 = LLT :: scalar ( <NUM_LIT> ) ; auto One = B . buildFConstant ( S64 , <NUM_LIT> ) ; auto DivScale0 = B . buildIntrinsic ( <STR_LIT> , { S64 , S1 } , false ) . addUse ( LHS ) . addUse ( RHS ) . addImm ( <NUM_LIT> ) . setMIFlags ( Flags ) ; auto NegDivScale0 = B . buildFNeg ( S64 , DivScale0 . getReg ( <NUM_LIT> ) , Flags ) ; auto Rcp = B . buildIntrinsic ( <STR_LIT> , { S64 } , false ) . addUse ( DivScale0 . getReg ( <NUM_LIT> ) ) . setMIFlags ( Flags ) ; auto Fma0 = B . buildFMA ( S64 , NegDivScale0 , Rcp , One , Flags ) ; auto Fma1 = B . buildFMA ( S64 , Rcp , Fma0 , Rcp , Flags ) ; auto Fma2 = B . buildFMA ( S64 , NegDivScale0 , Fma1 , One , Flags ) ; auto DivScale1 = B . buildIntrinsic ( <STR_LIT> , { S64 , S1 } , false ) . addUse ( LHS ) . addUse ( RHS ) . addImm ( <NUM_LIT> ) . setMIFlags ( Flags ) ; auto Fma3 = B . buildFMA ( S64 , Fma1 , Fma2 , Fma1 , Flags ) ; auto Mul = B . buildFMul ( S64 , DivScale1 . getReg ( <NUM_LIT> ) , Fma3 , Flags ) ; auto Fma4 = B . buildFMA ( S64 , NegDivScale0 , Mul , DivScale1 . getReg ( <NUM_LIT> ) , Flags ) ; Register Scale ; if ( ! ST . hasUsableDivScaleConditionOutput ( ) ) { LLT S32 = LLT :: scalar ( <NUM_LIT> ) ; auto NumUnmerge = B . buildUnmerge ( S32 , LHS ) ; auto DenUnmerge = B . buildUnmerge ( S32 , RHS ) ; auto Scale0Unmerge = B . buildUnmerge (


<s> int NewReturnAddrFI = MF . getFrameInfo ( ) -> CreateFixedObject ( SlotSize , ( int64_t ) FPDiff - SlotSize , false ) ; SDValue NewRetAddrFrIdx = DAG . getFrameIndex ( NewReturnAddrFI


<s> List . resize ( NewTop + <NUM_LIT> ) ; return NewTop


<s> if ( <ISA_LIT>FI -> hasPreallocatedCall ( ) ) return true ; const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; if ( ! EnableBasePointer ) return false ; bool CantUseFP = hasStackRealignment ( MF


<s> void <ISA_LIT>InstPrinter :: printU8ImmOperand ( const MCInst * MI , int OpNum , raw_ostream


<s> case <STR_LIT> : return LowerConstantPool ( Op , DAG ) ; case <STR_LIT> : return LowerJumpTable ( Op , DAG ) ; case <STR_LIT> : return LowerLOAD ( Op , DAG ) ; case <STR_LIT> : return LowerSTORE ( Op , DAG ) ; case <STR_LIT> : return LowerSELECT_CC ( Op , DAG ) ; case <STR_LIT> : return LowerVAARG ( Op , DAG ) ; case <STR_LIT> : return LowerVASTART ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return ExpandADDSUB ( Op . getNode ( ) , DAG ) ; case <STR_LIT> : return LowerFRAMEADDR ( Op , DAG ) ; default : llvm_unreachable (


<s> Use & U = * UI ; ++ UI ; SSA . Initialize ( I . getType ( ) , I . getName ( ) ) ; SSA . AddAvailableValue ( & BB , & I ) ; auto * User = cast < Instruction > ( U . getUser ( ) ) ; if ( User -> getParent ( ) == & BB ) continue ; if ( auto * UserPN = dyn_cast < PHINode > ( User ) ) if ( UserPN -> getIncomingBlock ( U ) == & BB ) continue ; if ( DT . dominates ( & I , User )


<s> MachineFrameInfo & FrameInfo = MF . getFrameInfo ( ) ; assert ( MFI -> isEntryFunction ( ) ) ; Register PreloadedScratchWaveOffsetReg = MFI -> getPreloadedReg ( <STR_LIT> ) ; Register ScratchRsrcReg ; if ( ! ST . enableFlatScratch ( ) ) ScratchRsrcReg = getEntryFunctionReservedScratchRsrcReg ( MF ) ; if ( ScratchRsrcReg ) { for ( MachineBasicBlock & OtherBB : MF ) { if ( & OtherBB != & MBB ) { OtherBB . addLiveIn ( ScratchRsrcReg ) ; } } } Register PreloadedScratchRsrcReg ; if ( ST . isAmdHsaOrMesa ( F ) ) { PreloadedScratchRsrcReg = MFI -> getPreloadedReg ( <STR_LIT> ) ; if ( ScratchRsrcReg && PreloadedScratchRsrcReg ) { MRI . addLiveIn ( PreloadedScratchRsrcReg ) ; MBB . addLiveIn ( PreloadedScratchRsrcReg ) ; } } DebugLoc DL ; MachineBasicBlock :: iterator I = MBB . begin ( ) ; Register ScratchWaveOffsetReg ; if ( PreloadedScratchWaveOffsetReg && TRI -> isSubRegisterEq ( ScratchRsrcReg , PreloadedScratchWaveOffsetReg ) ) { ArrayRef < MCPhysReg > AllSGPRs = TRI -> getAllSGPR32 ( MF ) ; unsigned NumPreloaded = MFI -> getNumPreloadedSGPRs ( ) ; AllSGPRs = AllSGPRs . slice ( std :: min ( static_cast < unsigned > ( AllSGPRs . size ( ) ) , NumPreloaded ) ) ; Register GITPtrLoReg = MFI -> getGITPtrLoReg ( MF ) ; for ( MCPhysReg Reg : AllSGPRs ) { if ( ! MRI . isPhysRegUsed ( Reg ) && MRI . isAllocatable ( Reg ) && ! TRI -> isSubRegisterEq ( ScratchRsrcReg , Reg ) && GITPtrLoReg != Reg ) { ScratchWaveOffsetReg = Reg ; BuildMI ( MBB , I , DL , TII -> get ( <STR_LIT> ) , ScratchWaveOffsetReg ) . addReg

( PreloadedScratchWaveOffsetReg , RegState :: Kill ) ;


<s> void \ tdata_section ( ) \ { \ if ( in_section != in_tdata ) \ { \ fprintf

( asm_out_file , <STR_LIT> , TDATA_SECTION_ASM_OP ) ; \ in_section = in_tdata ; \ } \ }


<s> static bool isHorizontalReduction ( const MachineInstr & MI ) { const MCInstrDesc & MCID = MI . getDesc ( ) ; uint64_t Flags = MCID .


<s> static bool buildMUBUFOffsetLoadStore ( const <ISA_LIT>InstrInfo * TII , MachineFrameInfo & MFI , MachineBasicBlock :: iterator MI , int Index , int64_t Offset ) { MachineBasicBlock * MBB = MI -> getParent ( ) ; const DebugLoc & DL = MI -> getDebugLoc ( ) ; bool IsStore = MI -> mayStore ( ) ; unsigned Opc = MI -> getOpcode ( ) ; int LoadStoreOp = IsStore ? getOffsetMUBUFStore ( Opc ) : getOffsetMUBUFLoad ( Opc ) ; if ( LoadStoreOp == - <NUM_LIT> ) return false ; const MachineOperand * Reg = TII -> getNamedOperand ( * MI , <STR_LIT> :: vdata ) ; MachineInstrBuilder NewMI = BuildMI ( * MBB , MI , DL , TII -> get ( LoadStoreOp ) ) . add ( * Reg ) . add ( * TII -> getNamedOperand ( * MI , <STR_LIT> :: srsrc ) ) . add ( * TII -> getNamedOperand

( * MI , <STR_LIT> :: soffset ) ) . addImm ( Offset ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . cloneMemRefs ( * MI ) ;


<s> case OPT_m3dnow : if ( ! value ) { target_flags &= ~ MASK_3DNOW_A ; target_flags_explicit |= MASK_3DNOW_A ; } return true ; case OPT_mmmx : if ( ! value ) { target_flags &= ~ ( MASK_3DNOW | MASK_3DNOW_A ) ; target_flags_explicit |= MASK_3DNOW | MASK_3DNOW_A ; } return true ; case OPT_msse : if ( ! value ) { target_flags &= ~ (


<s> return ( cfun -> calls_alloca || crtl -> calls_eh_return || cfun -> has_nonlocal_label


<s> unsigned Depth = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; SDValue FrameAddr = DAG . getCopyFromReg ( DAG . getEntryNode ( ) , dl , <STR_LIT>


<s> emit_label ( XEXP ( label , <NUM_LIT> ) ) ; emit_load_locked ( mode , retval , mem ) ; emit_store_conditional ( mode , mem , val ) ; emit_unlikely_jump ( EQ ,


<s> if ( I -> getOpcode ( ) == <STR_LIT> || I -> getOpcode ( ) == <STR_LIT> ) { MBB . erase ( I


<s> SDValue PtrOff = DAG . getIntPtrConstant ( LocMemOffset , dl ) ; PtrOff = DAG . getNode ( <STR_LIT> , dl , getPointerTy ( MF . getDataLayout ( ) ) , StackPtr , PtrOff ) ; SDValue MemcpyCall = CreateCopyOfByValArgument ( Arg , PtrOff , CallSeqStart . getNode ( ) -> getOperand ( <NUM_LIT> ) , Flags , DAG , dl ) ; SDValue NewCallSeqStart = DAG . getCALLSEQ_START ( MemcpyCall , CallSeqStart . getNode ( ) -> getOperand ( <NUM_LIT> ) , SDLoc ( MemcpyCall ) ) ; DAG . ReplaceAllUsesWith ( CallSeqStart . getNode ( ) , NewCallSeqStart . getNode ( ) ) ; Chain = CallSeqStart = NewCallSeqStart ; Arg = PtrOff ; } if ( VA . isRegLoc ( ) ) { if ( Arg . getValueType ( ) == <STR_LIT> ) Arg = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Arg ) ; seenFloatArg |= VA . getLocVT ( ) . isFloatingPoint ( ) ; RegsToPass . push_back ( std :: make_pair ( VA . getLocReg ( ) , Arg ) ) ; } else { assert ( VA . isMemLoc ( ) ) ; unsigned LocMemOffset = VA . getLocMemOffset ( ) ; if ( ! isTailCall ) { SDValue PtrOff = DAG . getIntPtrConstant ( LocMemOffset , dl ) ; PtrOff = DAG . getNode ( <STR_LIT> , dl , getPointerTy ( MF . getDataLayout ( ) ) , StackPtr , PtrOff ) ; MemOpChains . push_back ( DAG . getStore ( Chain , dl , Arg , PtrOff , MachinePointerInfo ( ) , false , false , <NUM_LIT> ) ) ; } else { CalculateTailCallArgDest ( DAG , MF , false , Arg , SPDiff , LocMemOffset , TailCallArguments ) ; } } } if ( ! MemOpChains . empty ( ) ) Chain = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , MemOpChains ) ; SDValue InFlag ; for ( unsigned i = <NUM_LIT> , e = RegsToPass . size ( ) ; i != e ; ++ i ) { Chain = DAG . getCopyToReg ( Chain , dl , RegsToPass [ i ] . first , RegsToPass [ i ] . second , InFlag ) ; InFlag = Chain . getValue (


<s> assert ( ! WroteStrtab ) ; std :: vector < char > Strtab ; StrtabBuilder . finalizeInOrder ( ) ; Strtab . resize ( StrtabBuilder . getSize (


<s> else if ( IntrData -> Type == TRUNCATE_TO_MEM_VI32 ) ScalarVT = <STR_LIT> ; Info . memVT = <STR_LIT> ( ScalarVT , VT . getVectorNumElements ( ) ) ; Info . align = Align ( <NUM_LIT> ) ; Info . flags |= MachineMemOperand :: MOStore ; break ; } case GATHER : case GATHER_AVX2 : { Info . opc = <STR_LIT> ; Info . ptrVal = nullptr ; MVT DataVT = <STR_LIT> ( I . getType ( ) ) ; MVT IndexVT = <STR_LIT> ( I . getArgOperand ( <NUM_LIT> ) -> getType ( ) ) ; unsigned NumElts = std :: min ( DataVT . getVectorNumElements ( ) , IndexVT . getVectorNumElements ( ) ) ; Info . memVT = <STR_LIT> ( DataVT . getVectorElementType ( ) , NumElts ) ; Info . align = Align ( <NUM_LIT> ) ; Info . flags |= MachineMemOperand :: MOLoad ; break ; } case SCATTER : { Info . opc = <STR_LIT> ; Info . ptrVal = nullptr ; MVT DataVT = <STR_LIT> ( I . getArgOperand ( <NUM_LIT> ) -> getType ( ) ) ; MVT IndexVT = <STR_LIT> ( I . getArgOperand ( <NUM_LIT> ) -> getType ( ) ) ; unsigned NumElts = std :: min ( DataVT . getVectorNumElements ( ) , IndexVT . getVectorNumElements ( ) ) ; Info . memVT = <STR_LIT> ( DataVT . getVectorElementType ( ) , NumElts ) ; Info . align = Align ( <NUM_LIT> ) ; Info . flags |= MachineMemOperand :: MOStore ; break ; } default : return false ; } return true


<s> hasAddend = true ; Expr = MCSymbolRefExpr :: Create ( Sym , Ctx ) ; break ; case R_<ISA_LIT>_64_GOT32 : case R_<ISA_LIT>_64_GOT64 : case R_<ISA_LIT>_64_GOTPC32 : case R_<ISA_LIT>_64_GOTPC64 : case R_<ISA_LIT>_64_GOTPLT64 : hasAddend = true ; Expr = MCSymbolRefExpr :: Create ( Sym , MCSymbolRefExpr :: VK_GOT , Ctx ) ; break ; case R_<ISA_LIT>_64_PLT32 : hasAddend = true ; Expr = MCSymbolRefExpr :: Create ( Sym , MCSymbolRefExpr :: VK_PLT , Ctx ) ; break ; case R_<ISA_LIT>_64_GLOB_DAT : case R_<ISA_LIT>_64_JUMP_SLOT : Expr = MCSymbolRefExpr :: Create ( Sym , Ctx ) ; break ; case R_<ISA_LIT>_64_GOTPCREL : case R_<ISA_LIT>_64_GOTPCREL64 : hasAddend = true ; Expr = MCSymbolRefExpr :: Create ( Sym , MCSymbolRefExpr :: VK_GOTPCREL , Ctx ) ; break ; case


<s> return ( __m256d ) __builtin_ia32_blendmpd_256_mask ( ( __v4df ) __A ,


<s> Value * <ISA_LIT>IREmitter :: visitWrapper ( const SDNode * N ) { llvm_unreachable ( <STR_LIT> ) ;


<s> ra_mem = gen_rtx_MEM ( mode , plus_constant ( Pmode , gen_rtx_REG ( Pmode , FP_REGNO ) , offset ) ) ; return copy_to_mode_reg ( mode ,


<s> enum attr_type type ; if ( ! insn || ! NONDEBUG_INSN_P ( insn ) || GET_CODE ( PATTERN ( insn ) ) == USE || GET_CODE ( PATTERN ( insn ) ) == CLOBBER ) return false ; type = get_attr_type ( insn ) ; if ( type == TYPE_MUL || type == TYPE_DIV || type == TYPE_SDIV || type == TYPE_DDIV || type == TYPE_SSQRT || type == TYPE_DSQRT || type ==

TYPE_MFCR || type == TYPE_MFCRF || type == TYPE_MFJMPR ) {


<s> static bool is_store_insn ( rtx insn ) { if ( ! insn || ! INSN_P (


<s> return __builtin_mve_uqshll_di ( value


<s> void <ISA_LIT>AssemblerImpl :: freeClassObjectBuffer ( ) { if ( classObjectBuffer ) free ( classObjectBuffer


<s> static reg_class_t nios2_preferred_reload_class ( rtx x ATTRIBUTE_UNUSED ,


<s> static unsigned getDepthOfOptCmov ( unsigned TrueOpDepth , unsigned FalseOpDepth ) { return std :: max ( divideCeil ( TrueOpDepth * <NUM_LIT> + FalseOpDepth , <NUM_LIT> ) , divideCeil

( FalseOpDepth * <NUM_LIT> + TrueOpDepth , <NUM_LIT> ) ) ;


<s> TargetPassConfig * <ISA_LIT>TargetMachine :: createPassConfig ( PassManagerBase


<s> NameDecorationStyle getDecorationStyle ( )


<s> while ( insn != BB_HEAD ( bb ) && ! NONDEBUG_INSN_P ( insn ) ) insn = PREV_INSN ( insn ) ; if ( insn == BB_HEAD ( bb ) || INSN_CODE ( insn ) != CODE_FOR_cbranchsi4_insn ) continue ; cmp = XEXP ( SET_SRC ( PATTERN ( insn ) ) , <NUM_LIT> ) ; op0 = XEXP ( cmp , <NUM_LIT> ) ; op1 = XEXP ( cmp , <NUM_LIT> ) ; if ( ! CONST_INT_P ( op1 ) || INTVAL ( op1 ) != <NUM_LIT> ) continue ; gcc_assert ( insn != BB_HEAD ( bb ) ) ; for ( prev = PREV_INSN ( insn ) ; ( ! insn_clobbered && prev != BB_HEAD ( bb ) && ( NOTE_P ( prev ) || DEBUG_INSN_P ( prev ) || ( ( set = single_set ( prev ) ) != NULL && get_attr_conds ( prev ) == CONDS_NOCOND ) ) ) ; prev = PREV_INSN ( prev ) ) { if ( reg_set_p ( op0 , prev ) ) insn_clobbered = true ; } if ( insn_clobbered )


<s> auto Unmerge = B . buildUnmerge ( S32 , WideDstReg ) ; int NumOps = Unmerge -> getNumOperands ( ) - <NUM_LIT> ; SmallVector < Register , <NUM_LIT> > RemergeParts ( NumOps ) ; for ( int I = <NUM_LIT> ; I != NumOps ; ++ I ) RemergeParts [ I ] = B . buildTrunc ( S16 , Unmerge . getReg ( I ) ) . getReg ( <NUM_LIT> ) ; B . buildBuildVector (


<s> <STR_LIT> getMemBarrierOpt ( ) const { assert ( Kind == k_MemBarrierOpt && <STR_LIT>


<s> ArrayRef < int16_t > SubRegs = TRI . getRegSplitParts ( SuperRC , EltSize ) ; if ( static_cast < unsigned > ( Offset ) >= SubRegs . size ( ) ) return std :: make_pair ( IdxReg , SubRegs [ <NUM_LIT> ] ) ; return std :: make_pair ( IdxBaseReg , SubRegs [ Offset ]


<s> OpcodeIndex = SOK_CRSpill ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { OpcodeIndex = SOK_CRBitSpill ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { OpcodeIndex = SOK_VRVectorSpill ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { OpcodeIndex = SOK_VSXVectorSpill ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { OpcodeIndex = SOK_VectorFloat8Spill ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { OpcodeIndex = SOK_VectorFloat4Spill ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { OpcodeIndex = SOK_VRSaveSpill ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { OpcodeIndex = SOK_QuadFloat8Spill ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { OpcodeIndex = SOK_QuadFloat4Spill ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { OpcodeIndex = SOK_QuadBitSpill ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { OpcodeIndex = SOK_SpillToVSR ; } else { llvm_unreachable ( <STR_LIT> ) ; } } else { if ( <STR_LIT> . contains ( Reg ) || <STR_LIT> . contains ( Reg ) ) { OpcodeIndex = SOK_Int4Spill ; } else if ( <STR_LIT> . contains ( Reg ) || <STR_LIT> . contains ( Reg ) ) { OpcodeIndex = SOK_Int8Spill ; } else if ( <STR_LIT> . contains ( Reg ) ) { OpcodeIndex = SOK_Float8Spill ; } else if ( <STR_LIT> . contains ( Reg ) ) { OpcodeIndex = SOK_Float4Spill ; } else if ( <STR_LIT> . contains ( Reg ) ) { OpcodeIndex = SOK_CRSpill ; } else if ( <STR_LIT> . contains ( Reg ) ) { OpcodeIndex = SOK_CRBitSpill ; } else if ( <STR_LIT> . contains ( Reg ) ) { OpcodeIndex = SOK_VRVectorSpill ; } else if ( <STR_LIT> . contains ( Reg )


<s> return __builtin_aarch64_lfrintnuv2dfv2di_us ( __a )


<s> return MI -> getDesc ( ) . getSize ( ) ; case TargetOpcode :: INLINEASM : { const MachineFunction * MF = MI -> getParent ( ) -> getParent ( ) ; const char * AsmStr = MI -> getOperand ( <NUM_LIT> ) . getSymbolName ( ) ; return getInlineAsmLength ( AsmStr , * MF -> getTarget (


<s> <ISA_LIT>Subtarget & <ISA_LIT>Subtarget :: initializeSubtargetDependencies ( StringRef CPU , StringRef FS , const TargetMachine & TM ) { StringRef CPUName = <STR_LIT> ( TM . getTargetTriple ( ) , CPU ) ; ParseSubtargetFeatures ( CPUName , CPUName , FS ) ; InstrItins = getInstrItineraryForCPU ( CPUName ) ; if ( In<ISA_LIT>16Mode && ! IsSoftFloat ) In<ISA_LIT>16HardFloat = true ; if ( StackAlignOverride ) stackAlignment =


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { return allocateCCRegs ( ValNo , ValVT , LocVT , LocInfo , ArgFlags , State , &


<s> static const MachineOperand & getLdStOffsetOp ( const MachineInstr * MI ) { unsigned Idx = isPairedLdSt ( MI ) ?


<s> rtx tmp ; if ( reg == NULL_RTX ) reg = gen_reg_rtx ( Pmode ) ; tmp = gen_rtx_CONST ( Pmode , x ) ; emit_insn ( gen_rtx_SET ( reg , gen_rtx_PLUS ( Pmode , pic_offset_table_rtx , tmp )


<s> virtual const MCObjectFormat & getObjectFormat ( )


<s> case <STR_LIT> : return <STR_LIT> ; default : llvm_unreachable (


<s> if ( ( ext_code == SIGN_EXTEND || ext_code == ZERO_EXTEND ) && ( from_mode == QImode || from_mode == HImode ) && set_src != NULL )

return arith_reg_operand ( XEXP ( set_src , <NUM_LIT> ) , from_mode ) ;


<s> assert ( MI . getDesc ( ) . isBranch ( ) && <STR_LIT> ) ; int NumOp = MI . getNumExplicitOperands


<s> static void core2i7_first_cycle_multipass_fini ( void * _data ) { ix86_first_cycle_multipass_data_t data = ( ix86_first_cycle_multipass_data_t ) _data ; if ( data -> ready_try_change ) { sbitmap_free ( data -> ready_try_change ) ; data -> ready_try_change


<s> MCInstLowering . Lower ( MI , TmpInst ) ; EmitToStreamer ( OutStreamer , TmpInst )


<s> word1 = force_reg ( DImode , gen_const_mem ( DImode , fnaddr ) ) ; word1 = expand_and ( DImode , word1 , GEN_INT ( HOST_WIDE_INT_C ( <NUM_LIT> ) ) , NULL ) ; } else { word1 = GEN_INT ( HOST_WIDE_INT_C ( <NUM_LIT> ) ) ; word2 = GEN_INT ( HOST_WIDE_INT_C ( <NUM_LIT> ) ) ; } mem = adjust_address ( m_tramp , DImode , <NUM_LIT> ) ; emit_move_insn ( mem , word1 ) ; mem = adjust_address ( m_tramp , DImode , <NUM_LIT> ) ; emit_move_insn ( mem , word2 ) ; mem = adjust_address ( m_tramp , Pmode


<s> if ( MI -> getOperand ( OpNum ) . isImm ( ) ) { int64_t Value = MI -> getOperand ( OpNum ) .


<s> for ( auto & N : IdenticalOpNums ) if ( ! isIdenticalOp ( MI1 . getOperand ( N1 + N ) , MI2 . getOperand ( N2 + N ) ) ) return false ; const MachineOperand * Op1 = & MI1 . getOperand ( N1 + <STR_LIT> ) ; const MachineOperand * Op2 = & MI2 . getOperand ( N2 + <STR_LIT> ) ; if ( ! isIdenticalOp ( * Op1


<s> UseMI = MRI -> use_instr_nodbg_begin ( NextExecReg ) ; } if ( UseMI -> getOpcode ( ) == <STR_LIT> ) { if ( hasKill ( MI . getParent ( ) , UseMI -> getParent ( ) , TII ) ) { NeedsKillCleanup . insert ( & * UseMI ) ; SimpleIf = false ; } } } else if ( SimpleIf ) { auto UseMI = MRI -> use_instr_nodbg_begin ( SaveExecReg ) ; SimpleIf = ! hasKill ( MI . getParent ( ) , UseMI -> getParent ( ) , TII ) ; } Register CopyReg = SimpleIf ? SaveExecReg : MRI -> createVirtualRegister ( BoolRC ) ; MachineInstr * CopyExec = BuildMI ( MBB , I , DL , TII -> get ( <STR_LIT> ) , CopyReg ) . addReg ( Exec ) . addReg ( Exec , RegState :: ImplicitDefine ) ; LoweredIf . insert ( CopyReg ) ; Register Tmp = MRI -> createVirtualRegister ( BoolRC ) ; MachineInstr * And = BuildMI ( MBB , I , DL , TII -> get ( AndOpc ) , Tmp ) . addReg ( CopyReg ) . add ( Cond ) ; setImpSCCDefDead ( * And , true ) ; MachineInstr * Xor = nullptr ; if ( ! SimpleIf ) { Xor = BuildMI ( MBB , I , DL , TII -> get ( XorOpc ) , SaveExecReg ) . addReg ( Tmp ) . addReg ( CopyReg ) ; setImpSCCDefDead ( * Xor , ImpDefSCC . isDead ( ) ) ; } MachineInstr * SetExec = BuildMI ( MBB , I , DL , TII -> get ( MovTermOpc ) , Exec ) . addReg ( Tmp , RegState :: Kill ) ; MachineInstr * NewBr = BuildMI ( MBB , I , DL , TII -> get ( <STR_LIT> ) ) . add ( MI . getOperand ( <NUM_LIT> ) ) ; if ( ! LIS ) { MI . eraseFromParent ( ) ; return ; } LIS -> InsertMachineInstrInMaps ( * CopyExec ) ; LIS -> ReplaceMachineInstrInMaps ( MI , *


<s> MIRBuilder . buildConstant ( OffsetReg , Offset ) ; Register AddrReg = MRI . createGenericVirtualRegister ( p0 ) ; MIRBuilder . buildPtrAdd ( AddrReg , SPReg , OffsetReg ) ; MPO = MachinePointerInfo :: getStack ( MIRBuilder . getMF ( ) ,


<s> MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; MachineModuleInfo & MMI = MF . getMMI ( ) ; const std :: vector < CalleeSavedInfo > & CSI = MFI -> getCalleeSavedInfo ( ) ; if ( CSI . empty ( ) ) return ; std :: vector < MachineMove > & Moves = MMI . getFrameMoves ( ) ; const TargetData * TD = TM . getTargetData ( ) ; bool HasFP = hasFP ( MF ) ; int stackGrowth = ( TM . getFrameInfo ( ) -> getStackGrowthDirection ( ) == TargetFrameInfo :: StackGrowsUp ? TD -> getPointerSize ( ) : - TD -> getPointerSize ( ) ) ; int64_t MaxOffset = <NUM_LIT> ; for ( std :: vector < CalleeSavedInfo > :: const_iterator I = CSI . begin ( ) , E = CSI . end ( ) ; I != E ; ++ I ) MaxOffset = std :: min ( MaxOffset , MFI -> getObjectOffset ( I -> getFrameIdx ( ) ) ) ; int64_t saveAreaOffset = ( HasFP ? <NUM_LIT> : <NUM_LIT> ) * stackGrowth ; for ( std :: vector < CalleeSavedInfo > :: const_iterator I = CSI . begin ( ) , E = CSI . end ( ) ; I != E ; ++ I ) { int64_t Offset = MFI -> getObjectOffset ( I -> getFrameIdx ( ) ) ; unsigned Reg = I -> getReg ( ) ; Offset = MaxOffset - Offset + saveAreaOffset ; if ( HasFP && FramePtr == Reg ) continue ; MachineLocation CSDst ( MachineLocation :: VirtualFP


<s> auto Res = tryParseSVERegister ( RegNum , Kind , RegKind :: SVEPredicateVector ) ; if ( Res != MatchOperand_Success ) return Res ; unsigned ElementWidth = StringSwitch < unsigned > ( Kind . lower ( ) ) . Case ( <STR_LIT> , - <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Default ( <NUM_LIT> ) ; if ( ! ElementWidth ) return MatchOperand_NoMatch ; Operands . push_back ( <ISA_LIT>Operand :: CreateReg ( RegNum , RegKind :: SVEPredicateVector , ElementWidth , S , getLoc ( ) , getContext ( ) ) ) ; MCAsmParser & Parser = getParser ( ) ; if ( Parser . getTok ( ) . isNot ( AsmToken :: Slash ) ) return MatchOperand_Success ; if ( ! Kind . empty ( ) ) { Error ( S , <STR_LIT> ) ; return MatchOperand_ParseFail ; } Operands . push_back ( <ISA_LIT>Operand :: CreateToken ( <STR_LIT> , false , getLoc ( ) , getContext ( ) ) ) ; Parser . Lex ( ) ; auto Pred = Parser . getTok ( ) . getString ( ) . lower ( ) ; if ( Pred != <STR_LIT> && Pred != <STR_LIT> ) { Error ( getLoc ( )


<s> auto CallSeqStart = MIRBuilder . buildInstr ( <STR_LIT> ) ; auto MIB = MIRBuilder . buildInstrNoInsert ( Callee . isReg ( ) ? <STR_LIT> : <STR_LIT> ) ; MIB . add ( Callee ) ; auto TRI = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getRegisterInfo ( ) ; const uint32_t * Mask = TRI -> getCallPreservedMask ( MF , F . getCallingConv ( ) ) ; if ( MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . hasCustomCallingConv ( ) ) TRI -> UpdateCustomCallPreservedMask ( MF , & Mask ) ; MIB . addRegMask ( Mask ) ; if ( TRI -> isAnyArgRegReserved ( MF ) ) TRI -> emitReservedArgRegCallError ( MF ) ; SmallVector < unsigned , <NUM_LIT> > PhysRegs ; OutgoingArgHandler Handler ( MIRBuilder , MRI , MIB , AssignFnFixed , AssignFnVarArg ) ; if ( ! handleAssignments ( MIRBuilder , SplitArgs , Handler ) ) return false ; MIRBuilder . insertInstr ( MIB ) ; if ( Callee . isReg ( ) ) MIB -> getOperand ( <NUM_LIT> ) . setReg ( constrainOperandRegClass ( MF , * TRI , MRI , * MF . getSubtarget ( ) . getInstrInfo ( ) , * MF . getSubtarget ( ) . getRegBankInfo ( ) , * MIB , MIB -> getDesc ( ) , Callee , <NUM_LIT> ) ) ; CCAssignFn * RetAssignFn = TLI . CCAssignFnForReturn ( F . getCallingConv ( ) ) ; if ( OrigRet . Reg ) { SplitArgs . clear ( ) ; SmallVector < uint64_t , <NUM_LIT> > RegOffsets ; SmallVector < unsigned , <NUM_LIT>


<s> SDValue PtrOff = DAG . getNode ( <STR_LIT> , dl , getPointerTy ( DAG . getDataLayout ( ) ) , StackPtr , SOffset ) ; SDValue Store = DAG . getStore ( Chain , dl , Arg , PtrOff , MachinePointerInfo ( ) ) ; MemOpChains . push_back ( Store ) ; IsTailCall = false ; } } if ( ! MemOpChains . empty ( ) ) Chain = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , MemOpChains ) ; SDValue Glue ; for ( unsigned i = <NUM_LIT> , e = RegsToPass . size ( ) ; i != e ; ++ i ) { Chain = DAG . getCopyToReg ( Chain , dl , RegsToPass [ i ] . first , RegsToPass [ i ] . second , Glue ) ; Glue = Chain . getValue ( <NUM_LIT> ) ; } bool IsDirect = true ; if ( auto * G = dyn_cast < GlobalAddressSDNode > ( Callee ) ) Callee = DAG . getTargetGlobalAddress ( G -> getGlobal ( ) , dl , <STR_LIT> ) ; else if ( auto * E = dyn_cast < ExternalSymbolSDNode > ( Callee ) ) Callee = DAG . getTargetExternalSymbol ( E -> getSymbol ( ) , <STR_LIT> ) ; else IsDirect = false ; SDVTList NodeTys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . push_back ( Chain ) ; Ops . push_back ( Callee ) ; for ( unsigned i = <NUM_LIT> , e = RegsToPass . size ( ) ; i != e ; ++ i ) Ops . push_back ( DAG . getRegister ( RegsToPass [ i ]

. first , RegsToPass [ i ] . second . getValueType ( ) ) ) ;


<s> MVT VT = Op -> getSimpleValueType ( <NUM_LIT> ) ; SDValue In = Op -> getOperand ( <NUM_LIT> ) ; MVT InVT = In . getSimpleValueType ( ) ; SDLoc dl ( Op ) ; if ( InVT . getVectorElementType ( ) == <STR_LIT> ) return LowerSIGN_EXTEND_Mask ( Op , Subtarget , DAG ) ; assert ( VT . isVector ( ) && InVT . isVector ( ) && <STR_LIT> ) ; assert ( VT . getVectorNumElements ( ) == VT . getVectorNumElements ( ) && <STR_LIT> ) ; assert ( ( VT . getVectorElementType ( ) == <STR_LIT> || VT . getVectorElementType ( ) == <STR_LIT> || VT . getVectorElementType ( ) == <STR_LIT> ) && <STR_LIT> ) ; assert ( ( InVT . getVectorElementType ( ) == <STR_LIT> || InVT . getVectorElementType ( ) == <STR_LIT> || InVT . getVectorElementType ( ) == <STR_LIT> ) && <STR_LIT> ) ; if ( Subtarget . hasInt256 ( ) ) return DAG . getNode ( <STR_LIT> , dl , VT , In ) ; unsigned NumElems = InVT . getVectorNumElements ( ) ; SDValue Undef = DAG . getUNDEF ( InVT ) ; SmallVector < int , <NUM_LIT> > ShufMask1 ( NumElems , - <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i != NumElems / <NUM_LIT> ; ++ i ) ShufMask1 [ i ] = i ; SDValue OpLo = DAG . getVectorShuffle ( InVT , dl , In , Undef , ShufMask1 ) ; SmallVector < int , <NUM_LIT> > ShufMask2 ( NumElems , - <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i != NumElems / <NUM_LIT> ; ++ i ) ShufMask2 [ i ] = i + NumElems / <NUM_LIT> ; SDValue OpHi = DAG . getVectorShuffle ( InVT , dl , In ,


<s> TRI = Subtarget . getRegisterInfo ( ) ; for ( MachineBasicBlock & MBB : F ) Changed |= runOnMachineBasicBlock ( MBB ) ; if ( Changed ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( F . dump


<s> return create ( VK_<ISA_LIT>_HI , Expr ,


<s> const AMDGPUSubtarget & ST = TM -> getSubtarget < AMDGPUSubtarget > ( ) ; if ( ST . getGeneration ( ) <= AMDGPUSubtarget :: NORTHERN_ISLANDS ) { addPass ( createAMDGPUCFGStructurizerPass ( ) , false ) ; addPass ( createR600ExpandSpecialInstrsPass ( * TM ) , false ) ; addPass ( & FinalizeMachineBundlesID , false ) ; addPass ( createR600Packetizer ( * TM )


<s> } } } else { unsigned Reg = <NUM_LIT> ; if ( getInstrVecReg ( MI , Reg ) ) { VecPrintList . push_back ( & MI ) ; DEBUG ( dbgs ( ) << <STR_LIT> ; MI . dump ( ) ) ; } } } Changed = VecPrintList . size ( ) > <NUM_LIT> ; if ( ! Changed ) return Changed ; for ( auto * I : VecPrintList ) { DebugLoc DL = I -> getDebugLoc ( ) ; MachineBasicBlock * MBB = I -> getParent ( ) ; DEBUG ( dbgs ( ) << <STR_LIT> ; I -> dump ( ) ) ; unsigned Reg = <NUM_LIT> ; if ( ! getInstrVecReg ( * I , Reg ) ) llvm_unreachable ( <STR_LIT> ) ; MachineBasicBlock :: instr_iterator MII = I -> getIterator ( ) ; if ( I -> isInsideBundle ( ) ) { DEBUG ( dbgs ( ) << <STR_LIT> ; I -> dump ( ) ) ; while ( MII -> isInsideBundle ( ) ) ++ MII ; } else { DEBUG ( dbgs ( ) << <STR_LIT> ; I -> dump ( ) ) ; MII ++ ; } if ( Reg >= <STR_LIT> && Reg <= <STR_LIT> ) { DEBUG ( dbgs ( ) << <STR_LIT> << Reg - <STR_LIT> << '\n' ) ; addAsmInstr ( MBB , Reg , MII , DL , QII , Fn ) ; } else if ( Reg >= <STR_LIT> && Reg <= <STR_LIT> ) { DEBUG ( dbgs ( ) << <STR_LIT> << Reg - <STR_LIT> << '\n' ) ; addAsmInstr ( MBB , <STR_LIT> + ( Reg - <STR_LIT> ) * <NUM_LIT> + <NUM_LIT> , MII , DL , QII , Fn ) ; addAsmInstr ( MBB , <STR_LIT> + ( Reg - <STR_LIT> ) * <NUM_LIT> , MII , DL , QII , Fn ) ; } else if ( Reg >= <STR_LIT> && Reg <= <STR_LIT> ) { DEBUG ( dbgs ( ) << <STR_LIT> << Reg - <STR_LIT> << '\n' ) ; addAsmInstr ( MBB , Reg , MII , DL , QII , Fn ) ; } else llvm_unreachable (


<s> static MCInstPrinter * create<ISA_LIT>MCInstPrinter ( const Target & T , TargetMachine & TM , unsigned SyntaxVariant , const MCAsmInfo & MAI ) { if ( SyntaxVariant == <NUM_LIT> ) return new


<s> const auto * Dest0 = TII -> getNamedOperand ( * CI . I , <STR_LIT> :: sdst ) ; const auto * Dest1 = TII -> getNamedOperand ( * Paired . I , <STR_LIT> :: sdst ) ; BuildMI ( * MBB , Paired . I , DL , CopyDesc ) . add ( * Dest0 ) . addReg ( DestReg , <NUM_LIT> , SubRegIdx0 ) ; MachineInstr * Copy1 = BuildMI ( * MBB , Paired . I , DL , CopyDesc ) . add ( * Dest1 ) . addReg ( DestReg , RegState :: Kill , SubRegIdx1 ) ; moveInstsAfter ( Copy1 , CI . InstsToMove ) ; CI . I -> eraseFromParent ( ) ; Paired . I -> eraseFromParent (


<s> return false ; } if ( getFrameIndexAddress ( AM , SDLoc ( N ) , Disp , Base ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return true ; } if ( AM . hasIndexReg ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } if ( ! AM . hasBaseReg ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } if ( getSymbolicDisplacement ( AM , SDLoc ( N ) , Disp ) ) { assert ( ! AM . Disp && <STR_LIT> ) ; LLVM_DEBUG ( dbgs ( )


<s> unsigned <ISA_LIT>FastISel :: materializeExternalCallSym ( MCSymbol * Sym ) { const TargetRegisterClass * RC = & <STR_LIT> ; unsigned DestReg = createResultReg ( RC ) ; emitInst ( <STR_LIT> , DestReg ) . addReg ( MFI -> getGlobalBaseReg ( * MF ) ) . addSym ( Sym , <STR_LIT> ) ; return


<s> <STR_LIT> getModifier ( ) const { return Modifier


<s> unsigned HasAlign = MFI . getObjectAlignment ( FI ) ; unsigned LoadOpc ; if ( NeedAlign <= HasAlign ) LoadOpc = ! Is128B ? <STR_LIT> : <STR_LIT> ; else LoadOpc = ! Is128B ? <STR_LIT> : <STR_LIT> ; BuildMI ( B , It , DL , HII . get ( LoadOpc ) , DstR ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . setMemRefs ( MI -> memoperands_begin ( ) , MI -> memoperands_end ( ) ) ; B . erase ( It ) ; return true


<s> rtx lane ; if ( d -> vec_flags == VEC_SVE_PRED || d -> perm . encoding ( ) . encoded_nelts ( ) != <NUM_LIT> || ! d -> perm [ <NUM_LIT> ] . is_constant ( & elt ) ) return false ; if ( ( d -> vec_flags & VEC_SVE_DATA ) && elt * ( aarch64_sve_container_bits ( vmode ) / <NUM_LIT> ) >= <NUM_LIT> ) return false ; if ( d -> testing_p ) return true ; in0 = d -> op0 ; lane = GEN_INT ( elt ) ; rtx parallel = gen_rtx_PARALLEL ( vmode , gen_rtvec ( <NUM_LIT> , lane ) ) ; rtx select = gen_rtx_VEC_SELECT ( GET_MODE_INNER ( vmode ) , in0 , parallel ) ; emit_set_insn ( out , gen_rtx_VEC_DUPLICATE ( vmode , select ) ) ; return


<s> return LowerF128Call ( Op , DAG , RTLIB :: ADD_F128 ) ; case <STR_LIT> : return LowerF128Call ( Op , DAG , RTLIB :: SUB_F128 ) ; case <STR_LIT> : return LowerF128Call ( Op , DAG , RTLIB :: MUL_F128 ) ; case <STR_LIT> : return LowerF128Call ( Op , DAG , RTLIB :: DIV_F128 ) ; case <STR_LIT> : return LowerFP_ROUND ( Op , DAG ) ; case <STR_LIT> : return LowerFP_EXTEND ( Op , DAG ) ; case <STR_LIT> : return LowerFRAMEADDR ( Op , DAG ) ; case <STR_LIT> : return LowerRETURNADDR ( Op , DAG ) ; case <STR_LIT> : return LowerINSERT_VECTOR_ELT ( Op , DAG ) ; case <STR_LIT> : return LowerEXTRACT_VECTOR_ELT ( Op , DAG ) ; case <STR_LIT> : return LowerBUILD_VECTOR ( Op , DAG ) ; case <STR_LIT> : return LowerVECTOR_SHUFFLE ( Op , DAG ) ; case <STR_LIT> : return LowerEXTRACT_SUBVECTOR ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerVectorSRA_SRL_SHL ( Op , DAG ) ; case <STR_LIT> : return LowerShiftLeftParts ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerShiftRightParts ( Op , DAG ) ; case <STR_LIT> : return LowerCTPOP ( Op , DAG ) ; case <STR_LIT> : return LowerFCOPYSIGN ( Op , DAG ) ; case <STR_LIT> : return LowerAND ( Op , DAG ) ; case <STR_LIT> : return LowerOR ( Op , DAG ) ; case <STR_LIT> : return LowerXOR ( Op , DAG ) ; case <STR_LIT> : return LowerPREFETCH ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerINT_TO_FP ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerFP_TO_INT ( Op , DAG ) ; case <STR_LIT> : return LowerFSINCOS ( Op , DAG ) ; case <STR_LIT>


<s> bool AMDGPUOperand :: isSWaitCnt ( ) const { return isImm (


<s> void <ISA_LIT>AsmInstCompress :: rmOpcodeFromBundle ( MCInst & MI , unsigned opcode ) const { for ( auto & I : <ISA_LIT>MCInstrInfo :: bundleInstructions ( MI ) ) { MCInst & BMI = const_cast < MCInst & > ( * I . getInst ( ) ) ; if ( BMI . getOpcode ( )


<s> unsigned ID = MI -> getOperand ( OpNo ) . getImm ( ) ; O << TAI -> getPrivateGlobalPrefix ( ) << <STR_LIT> << getFunctionNumber ( ) << '_' << ID << <STR_LIT> ; } else { assert ( ! strcmp ( Modifier , <STR_LIT> ) && <STR_LIT> ) ; unsigned CPI = MI -> getOperand ( OpNo )


<s> memset ( m32r_punct_chars , <NUM_LIT> , sizeof ( m32r_punct_chars ) ) ; m32r_punct_chars [ '#' ] = <NUM_LIT> ; m32r_punct_chars [ '@' ]


<s> int WaitStates = <NUM_LIT> ; if ( <ISA_LIT>InstrInfo :: isSMRD ( * MI ) ) return std :: max ( WaitStates , checkSMRDHazards ( MI ) ) ; if ( ST . hasNSAtoVMEMBug ( ) ) WaitStates = std :: max ( WaitStates , checkNSAtoVMEMHazard ( MI ) ) ; WaitStates = std :: max ( WaitStates , checkFPAtomicToDenormModeHazard ( MI ) ) ; if ( ST . hasNoDataDepHazard ( ) ) return WaitStates ; if ( <ISA_LIT>InstrInfo :: isVMEM ( * MI ) || <ISA_LIT>InstrInfo :: isFLAT ( * MI ) ) WaitStates = std :: max ( WaitStates , checkVMEMHazards ( MI ) ) ; if ( <ISA_LIT>InstrInfo :: isVALU ( * MI ) ) WaitStates = std :: max ( WaitStates , checkVALUHazards ( MI ) ) ; if ( <ISA_LIT>InstrInfo :: isDPP ( * MI ) ) WaitStates = std :: max ( WaitStates , checkDPPHazards ( MI ) ) ; if ( isDivFMas ( MI -> getOpcode ( ) ) ) WaitStates = std :: max ( WaitStates , checkDivFMasHazards ( MI ) ) ; if ( isRWLane ( MI -> getOpcode ( ) ) ) WaitStates = std

:: max ( WaitStates , checkRWLaneHazards ( MI ) ) ;


<s> const <ISA_LIT>BaseInstrInfo & TII = * static_cast < const <ISA_LIT>BaseInstrInfo * > ( MF . getTarget ( ) . getInstrInfo ( ) ) ; <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; DebugLoc dl = MI . getDebugLoc ( ) ; MachineInstrBuilder MIB ( * MBB . getParent ( ) , & MI ) ; unsigned FrameReg = <STR_LIT> ; int FrameIndex = MI . getOperand ( FIOperandNum ) . getIndex ( ) ; int Offset = MF . getFrameInfo ( ) -> getObjectOffset ( FrameIndex ) + MF . getFrameInfo ( ) -> getStackSize ( ) + SPAdj ; if ( MF . getFrameInfo ( ) -> hasVarSizedObjects ( ) ) { assert ( SPAdj == <NUM_LIT> && MF . getTarget ( ) . getFrameLowering ( ) -> hasFP ( MF ) && <STR_LIT> ) ; if ( ! hasBasePointer ( MF ) ) { FrameReg = getFrameRegister ( MF ) ; Offset -= AFI -> getFramePtrSpillOffset ( ) ; } else FrameReg = BasePtr ; } if ( RS && FrameReg == <STR_LIT> && RS -> isScavengingFrameIndex ( FrameIndex ) ) { assert ( MF . getTarget ( ) . getFrameLowering ( ) -> hasReservedCallFrame ( MF ) && <STR_LIT> <STR_LIT> ) ; assert ( ! MF . getFrameInfo ( ) -> hasVarSizedObjects ( ) && <STR_LIT> <STR_LIT> ) ; } if ( MI . isDebugValue ( ) ) { MI . getOperand ( FIOperandNum ) . ChangeToRegister ( FrameReg , false ) ; MI . getOperand ( FIOperandNum + <NUM_LIT> ) . ChangeToImmediate ( Offset ) ; return ; } assert ( AFI -> isThumbFunction ( ) &&


<s> if ( Src . getOpcode ( ) != N -> getOpcode ( ) ) return SDValue ( ) ; if ( ! isa < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) || ! isa < ConstantSDNode > ( Src . getOperand ( <NUM_LIT> ) ) ) return SDValue ( ) ; unsigned ShAmt1 = N -> getConstantOperandVal ( <NUM_LIT> ) ; unsigned ShAmt2 = Src . getConstantOperandVal ( <NUM_LIT> ) ; Src = Src . getOperand ( <NUM_LIT> ) ; unsigned CombinedShAmt


<s> void EmitRawByte ( unsigned char C , unsigned & CurByte , raw_ostream & OS ) const { OS << ( char ) C ; ++ CurByte


<s> static bool signed_compare_p ( enum rtx_code code ) { return ( code == EQ || code == NE || code == LT || code ==


<s> break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } const GCNSubtarget & ST = MBB . getParent ( ) -> getSubtarget < GCNSubtarget > ( ) ; if ( ST . hasNoSdstCMPX ( ) ) Opcode = <STR_LIT> ( Opcode ) ; assert ( MI . getOperand ( <NUM_LIT> ) . isReg ( ) ) ; if ( TRI -> isVGPR ( MBB . getParent ( ) -> getRegInfo ( ) , MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ) { Opcode = <STR_LIT> ( Opcode ) ; BuildMI ( MBB , & MI , DL , TII -> get ( Opcode ) ) . add ( MI . getOperand ( <NUM_LIT> ) ) . add ( MI . getOperand ( <NUM_LIT> ) ) ; } else { auto I = BuildMI ( MBB , & MI , DL , TII -> get ( Opcode ) ) ; if ( ! ST . hasNoSdstCMPX ( ) ) I . addReg ( <STR_LIT> , RegState :: Define ) ; I . addImm ( <NUM_LIT> ) . add ( MI . getOperand ( <NUM_LIT> ) ) . addImm ( <NUM_LIT> ) . add ( MI . getOperand ( <NUM_LIT> ) ) ; I . addImm ( <NUM_LIT> ) ; } return true ; } case <STR_LIT> : { const MachineFunction * MF = MI . getParent ( ) -> getParent ( ) ; const GCNSubtarget & ST = MF -> getSubtarget < GCNSubtarget > ( ) ; unsigned Exec = ST . isWave32 ( ) ? <STR_LIT> : <STR_LIT> ; const MachineOperand & Op = MI . getOperand ( <NUM_LIT> ) ; int64_t KillVal = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; assert ( KillVal == <NUM_LIT> ||


<s> static bool isi32Store ( unsigned Opc ) { return Opc == <STR_LIT> || isT1i32Store ( Opc ) ||


<s> SelectionDAG & DAG = DCI . DAG ; if ( <STR_LIT> ( N -> getOperand ( <NUM_LIT> ) . getNode ( ) ) && N -> getOperand ( <NUM_LIT> ) . hasOneUse ( ) && ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT> || N -> getValueType ( <NUM_LIT> ) == <STR_LIT> || N -> getValueType ( <NUM_LIT> ) == <STR_LIT> ) ) { SDValue Load = N -> getOperand ( <NUM_LIT> ) ; LoadSDNode * LD = cast < LoadSDNode > ( Load ) ; SDValue Ops [ ] = { LD -> getChain ( ) , LD -> getBasePtr ( ) , DAG . getValueType ( N -> getValueType ( <NUM_LIT> ) ) } ; SDValue BSLoad = DAG . getMemIntrinsicNode ( <STR_LIT> , SDLoc ( N ) , DAG . getVTList ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> , <STR_LIT> ) , Ops , LD

-> getMemoryVT ( ) , LD -> getMemOperand ( ) ) ;


<s> SDValue Arg0 = Op . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ; SDValue Arg1 = Op . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ; if ( Arg0 . getValueType ( ) != <STR_LIT> || Arg1 . getValueType

( ) != <STR_LIT> ) report_fatal_error ( <STR_LIT> ) ;


<s> if ( ! isBitfieldExtractOp ( CurDAG , N , Opc , Opd0 , Immr , Imms ) ) return nullptr ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; SDLoc dl ( N ) ; if ( ( Opc == <STR_LIT> || Opc == <STR_LIT> ) && VT == <STR_LIT> ) { SDValue Ops64 [ ] = { Opd0 , CurDAG -> getTargetConstant ( Immr , dl , <STR_LIT> ) , CurDAG -> getTargetConstant ( Imms , dl , <STR_LIT> ) } ; SDNode * BFM = CurDAG -> getMachineNode ( Opc , dl , <STR_LIT> , Ops64 ) ; SDValue SubReg = CurDAG -> getTargetConstant ( <STR_LIT> , dl , <STR_LIT> ) ; MachineSDNode * Node = CurDAG -> getMachineNode ( TargetOpcode :: EXTRACT_SUBREG , dl , <STR_LIT> , SDValue ( BFM , <NUM_LIT> ) , SubReg ) ; return Node ; } SDValue Ops [ ] = { Opd0 , CurDAG -> getTargetConstant ( Immr , dl , VT ) , CurDAG -> getTargetConstant ( Imms


<s> unsigned <ISA_LIT>MCCodeEmitter :: getSizeInsEncoding ( const MCInst & MI , unsigned OpNo , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { assert ( MI . getOperand ( OpNo - <NUM_LIT> ) . isImm ( ) ) ; assert ( MI . getOperand ( OpNo ) . isImm ( ) ) ; unsigned Position = getMachineOpValue ( MI , MI . getOperand ( OpNo - <NUM_LIT>


<s> <ISA_LIT>PostRASchedStrategy ( ) : <ISA_LIT>SchedStrategy ( ) { isPostRA =


<s> case <STR_LIT> : { assert ( ! N -> getValueType ( <NUM_LIT> ) . isVector ( ) && <STR_LIT> ) ; ConstantSDNode * Width = dyn_cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ; if ( ! Width ) break ; uint32_t WidthVal = Width -> getZExtValue ( ) & <NUM_LIT> ; if ( WidthVal == <NUM_LIT> ) return DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; ConstantSDNode * Offset = dyn_cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ; if ( ! Offset ) break ; SDValue BitsFrom = N -> getOperand ( <NUM_LIT> ) ; uint32_t OffsetVal = Offset -> getZExtValue ( ) & <NUM_LIT> ; bool Signed = N -> getOpcode ( ) == <STR_LIT> ; if ( OffsetVal == <NUM_LIT> ) { unsigned SignBits = Signed ? ( <NUM_LIT> - WidthVal + <NUM_LIT> ) : ( <NUM_LIT> - WidthVal ) ; unsigned OpSignBits = DAG . ComputeNumSignBits ( BitsFrom ) ; if ( OpSignBits >= SignBits ) return BitsFrom ; EVT SmallVT = EVT :: getIntegerVT ( * DAG . getContext ( ) , WidthVal ) ; if ( Signed ) { return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , BitsFrom , DAG . getValueType ( SmallVT ) ) ; } return DAG . getZeroExtendInReg ( BitsFrom , DL , SmallVT ) ; } if ( ConstantSDNode * CVal = dyn_cast < ConstantSDNode > ( BitsFrom ) ) { if ( Signed ) { return constantFoldBFE < int32_t > ( DAG , CVal -> getSExtValue ( ) , OffsetVal , WidthVal , DL ) ; } return constantFoldBFE < uint32_t > ( DAG , CVal -> getZExtValue ( ) , OffsetVal , WidthVal , DL ) ; } if ( ( OffsetVal + WidthVal ) >= <NUM_LIT> ) { SDValue ShiftVal = DAG . getConstant ( OffsetVal , DL , <STR_LIT> ) ; return DAG . getNode ( Signed ? <STR_LIT> : <STR_LIT> , DL , <STR_LIT> , BitsFrom , ShiftVal ) ; } if ( BitsFrom . hasOneUse ( ) ) { APInt Demanded = APInt :: getBitsSet ( <NUM_LIT> , OffsetVal , OffsetVal + WidthVal ) ; APInt KnownZero , KnownOne ; TargetLowering :: TargetLoweringOpt TLO ( DAG , ! DCI . isBeforeLegalize ( ) , ! DCI . isBeforeLegalizeOps ( ) ) ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; if ( TLI . ShrinkDemandedConstant ( BitsFrom , Demanded , TLO ) || TLI . SimplifyDemandedBits ( BitsFrom , Demanded , KnownZero , KnownOne , TLO ) ) { DCI . CommitTargetLoweringOpt ( TLO ) ; } } break ; } case <STR_LIT> : return performLoadCombine ( N , DCI ) ; case <STR_LIT> : return performStoreCombine ( N , DCI ) ; case


<s> static MCInstPrinter * create<ISA_LIT>MCInstPrinter ( const Target & T , unsigned SyntaxVariant , const MCAsmInfo & MAI , const MCInstrInfo & MII , const MCRegisterInfo & MRI , const MCSubtargetInfo & STI ) { if ( SyntaxVariant == <NUM_LIT> ) return new <ISA_LIT>InstPrinter ( MAI , MII , MRI ) ; return <NUM_LIT>


<s> RegisterMCAsmInfoFn X ( The<ISA_LIT>Target , create<ISA_LIT>MCAsmInfo ) ; RegisterMCAsmInfoFn Y ( The<ISA_LIT>V9Target , create<ISA_LIT>V9MCAsmInfo ) ; for ( Target * T : { & The<ISA_LIT>Target , & The<ISA_LIT>V9Target } ) { TargetRegistry :: RegisterMCInstrInfo ( * T , create<ISA_LIT>MCInstrInfo ) ; TargetRegistry :: RegisterMCRegInfo ( * T , create<ISA_LIT>MCRegisterInfo ) ; TargetRegistry :: RegisterMCSubtargetInfo ( * T


<s> void <ISA_LIT>TargetLowering :: LowerAsmOperandForConstraint ( SDValue Op , std :: string & Constraint , std :: vector < SDValue > & Ops , SelectionDAG & DAG ) const { TargetLowering :: LowerAsmOperandForConstraint ( Op , Constraint , Ops


<s> MCSymbol * <ISA_LIT>_64MachoTargetObjectFile :: getCFIPersonalitySymbol ( const GlobalValue * GV , Mangler * Mang


<s> unsigned Register = <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . getRegister ( RegNo ) ; Inst . addOperand ( MCOperand :: createReg


<s> if ( ! I . isShift ( ) ) continue ; if ( I . getType ( ) != Type :: getInt32Ty ( Ctx ) ) continue ; if ( isa < ConstantInt > ( I . getOperand ( <NUM_LIT> ) ) ) continue ; ShiftInsts . push_back ( cast < BinaryOperator > ( & I ) ) ; } for ( auto * I : ShiftInsts ) { expand ( I ) ; } return ShiftInsts . size ( ) >


<s> void emitDataMappingSymbol ( ) { if ( LastEMS == EMS_Data ) return ; EmitMappingSymbol ( <STR_LIT> ) ; LastEMS = EMS_Data


<s> void Thumb2InstrInfo :: ReplaceTailWithBranchTo ( MachineBasicBlock :: iterator Tail , MachineBasicBlock * NewDest ) const { MachineBasicBlock * MBB = Tail -> getParent ( ) ; <ISA_LIT>FunctionInfo * AFI = MBB -> getParent ( ) -> getInfo < <ISA_LIT>FunctionInfo > ( ) ; if ( ! AFI -> hasITBlocks ( ) || Tail -> isBranch ( ) ) { TargetInstrInfo :: ReplaceTailWithBranchTo ( Tail , NewDest ) ; return ; } unsigned PredReg = <NUM_LIT> ; <STR_LIT> CC = getInstrPredicate ( * Tail , PredReg ) ; MachineBasicBlock :: iterator MBBI = Tail ; if ( CC != <STR_LIT> ) -- MBBI ; TargetInstrInfo :: ReplaceTailWithBranchTo ( Tail , NewDest ) ; if ( CC != <STR_LIT> ) { MachineBasicBlock :: iterator E = MBB -> begin ( ) ; unsigned Count = <NUM_LIT> ; while ( Count && MBBI != E ) { if ( MBBI -> isDebugInstr ( ) ) { -- MBBI ; continue ; } if ( MBBI -> getOpcode ( ) == <STR_LIT> ) { unsigned Mask = MBBI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( Count == <NUM_LIT> ) MBBI -> eraseFromParent ( ) ; else { unsigned MaskOn =


<s> default : return <NUM_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT>


<s> MachineInstr * MI = Arguments -> MI ; const ReduceEntry & Entry = Arguments -> Entry ; if ( ! isMMThreeBitGPRegister ( MI -> getOperand ( <NUM_LIT> ) ) || ! isMMThreeBitGPRegister ( MI -> getOperand ( <NUM_LIT> ) ) || ! isMMThreeBitGPRegister ( MI -> getOperand ( <NUM_LIT> ) ) ) return false ; return ReplaceInstruction ( MI , Entry


<s> TargetLDBackend * create<ISA_LIT>LDBackend ( const LinkerConfig & pConfig ) { if ( pConfig . targets ( ) . triple ( ) . isOSDarwin ( ) ) { assert ( <NUM_LIT> && <STR_LIT> ) ; } if ( pConfig . targets ( ) . triple ( ) . isOSWindows ( ) ) { assert ( <NUM_LIT> &&


<s> if ( ! is32Bit ) return MCDisassembler :: Fail ; DecodeStatus status = DecodeOperandRegister ( Inst , s1_d , Address , Decoder ) ; if ( status != MCDisassembler :: Success ) return status ; return MCDisassembler


<s> if ( ! trySkipId ( Prefix , AsmToken :: Colon ) ) return MatchOperand_NoMatch ; return parseId ( Value ) ? MatchOperand_Success :


<s> unsigned <ISA_LIT>AsmParser :: matchRegisterNameAlias ( StringRef Name , bool isVector ) { unsigned RegNum = isVector ? matchVectorRegName ( Name ) : MatchRegisterName ( Name ) ; RegKind Kind = isVector ? RegKind :: NeonVector : RegKind


<s> return BuildMI ( * MBB , I , DL , get ( AMDGPU :: <ISA_LIT>_INDIRECT_DST_V1 ) ) . addReg ( IndirectBaseReg , RegState :: Define ) . addOperand ( I -> getOperand ( <NUM_LIT> ) ) . addReg ( IndirectBaseReg ) . addReg ( OffsetReg

) . addImm ( <NUM_LIT> ) . addReg ( ValueReg ) ;


<s> if ( I -> isDebugValue ( ) ) continue ; if ( I -> getOpcode ( ) != <STR_LIT> && I -> getOpcode ( ) != <STR_LIT> ) break ; I -> eraseFromParent ( ) ; I = MBB . end ( ) ; ++ Count ; } return Count


<s> static bool second_sew_less_than_first_sew_p ( const vector_insn_info & info1 , const vector_insn_info & info2 ) { return info2 . get_sew ( ) < info1 . get_sew (


<s> uint16x8_t result ; __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) : ) ; return result


<s> if ( ( ! reload_completed || ! safe_group_barrier_needed ( insn ) ) && ( ! mflag_sched_mem_insns_hard_limit || ! is_load_p ( insn ) || mem_ops_in_group [ current_cycle % <NUM_LIT> ] < ia64_max_memory_insns ) ) return <NUM_LIT> ; return <NUM_LIT>


<s> MCFixupKind Kind = MCFixupKind ( FIXUP ) ; if ( MO . getExpr ( ) -> getKind ( ) == MCExpr :: Target ) Kind = getTargetFixup ( MO . getExpr ( ) ) ; Fixups . push_back ( MCFixup :: create ( <NUM_LIT> , MO . getExpr ( ) , Kind , MI . getLoc ( ) ) ) ; return


<s> unsigned getStackEntry ( unsigned STi ) const { assert ( STi < StackTop &&


<s> void LLVMInitialize<ISA_LIT>TargetInfo ( ) { RegisterTarget < Triple :: hexagon , false > X ( getThe<ISA_LIT>Target


<s> SDValue <ISA_LIT>SelectionDAGInfo :: EmitTargetCodeForMemset ( SelectionDAG & DAG , const SDLoc & dl , SDValue Chain , SDValue Dst , SDValue Src , SDValue Size , Align Alignment , bool isVolatile , MachinePointerInfo DstPtrInfo ) const { ConstantSDNode * V = dyn_cast < ConstantSDNode > ( Src ) ; ConstantSDNode * SizeValue = dyn_cast < ConstantSDNode > ( Size ) ; const <ISA_LIT>Subtarget & STI = DAG . getMachineFunction ( ) . getSubtarget < <ISA_LIT>Subtarget > ( ) ; const char * bzeroName = ( V && V -> isZero ( ) ) ? DAG . getTargetLoweringInfo ( ) . getLibcallName ( RTLIB :: BZERO ) : nullptr ; if ( bzeroName && ( ! SizeValue || SizeValue -> getZExtValue ( ) > <NUM_LIT> ) ) { const <ISA_LIT>TargetLowering & TLI = * STI . getTargetLowering ( ) ; EVT IntPtr = TLI . getPointerTy ( DAG . getDataLayout ( ) ) ; Type * IntPtrTy = Type :: getInt8PtrTy ( * DAG . getContext ( ) ) ; TargetLowering :: ArgListTy Args ; TargetLowering :: ArgListEntry Entry ; Entry . Node = Dst ; Entry . Ty = IntPtrTy ; Args . push_back ( Entry ) ; Entry . Node = Size ; Args . push_back ( Entry ) ; TargetLowering :: CallLoweringInfo CLI ( DAG ) ; CLI . setDebugLoc ( dl ) . setChain ( Chain ) . setLibCallee ( CallingConv :: C , Type :: getVoidTy ( * DAG . getContext ( ) ) , DAG . getExternalSymbol ( bzeroName , IntPtr ) , std :: move ( Args ) ) . setDiscardResult ( ) ; std :: pair < SDValue , SDValue > CallResult = TLI . LowerCallTo ( CLI ) ; return CallResult . second ; } return SDValue (


<s> auto UnmergeDefs = unmergeDefsSplitHigh ( Unmerge ) ; SmallVector < Register > RestParts ; for ( MachineOperand & Op : UnmergeDefs . Lows ) RestParts . push_back ( Op . getReg ( ) ) ; Register Rest = ( RestParts . size ( ) > <NUM_LIT> ) ? Builder . buildMerge ( LLT :: scalar ( RestParts . size ( ) * <NUM_LIT> ) , RestParts ) . getReg ( <NUM_LIT> ) : RestParts [ <NUM_LIT> ] ; return { UnmergeDefs . High . getReg ( ) ,


<s> unsigned DestOffset = BBInfo [ DestBB -> getNumber ( ) ] . Offset ; if ( BrOffset < DestOffset && ( DestOffset - BrOffset ) <= <NUM_LIT> ) { MachineBasicBlock :: iterator CmpMI = Br . MI ; if ( CmpMI != Br . MI -> getParent ( ) -> begin ( ) ) { -- CmpMI ; if ( CmpMI -> getOpcode ( ) == <STR_LIT> ) { unsigned Reg = CmpMI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; Pred = getInstrPredicate ( * CmpMI , PredReg ) ; if ( Pred == <STR_LIT> && CmpMI -> getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> && is<ISA_LIT>LowRegister ( Reg ) ) { MachineBasicBlock * MBB = Br . MI -> getParent ( ) ; DEBUG ( dbgs ( ) << <STR_LIT> << * CmpMI << <STR_LIT> << * Br . MI ) ; MachineInstr * NewBR = BuildMI ( * MBB , CmpMI , Br . MI -> getDebugLoc ( ) , TII -> get ( NewOpc ) ) .

addReg ( Reg ) . addMBB ( DestBB , Br . MI -> getOperand ( <NUM_LIT> ) . getTargetFlags ( ) ) ;