<s> warning_at ( DECL_SOURCE_LOCATION ( node -> decl ) , <NUM_LIT> , <STR_LIT> , ret_type ) ; return <NUM_LIT> ; } tree t ; int i ; tree type_arg_types = TYPE_ARG_TYPES ( TREE_TYPE ( node -> decl ) ) ; bool decl_arg_p = ( node -> definition || type_arg_types == NULL_TREE ) ; for ( t = ( decl_arg_p ? DECL_ARGUMENTS ( node -> decl ) : type_arg_types ) , i = <NUM_LIT> ; t && t != void_list_node ; t = TREE_CHAIN ( t ) , i ++ ) { tree arg_type = decl_arg_p ? TREE_TYPE ( t ) : TREE_VALUE ( t ) ; switch ( TYPE_MODE ( arg_type ) ) { case E_QImode : case E_HImode : case E_SImode : case E_DImode : case E_SFmode : case E_DFmode : if ( ! AGGREGATE_TYPE_P ( arg_type ) ) break ; default : if ( clonei -> args [ i ] . arg_type == SIMD_CLONE_ARG_TYPE_UNIFORM ) break ; warning_at ( DECL_SOURCE_LOCATION ( node -> decl ) , <NUM_LIT> , <STR_LIT> , arg_type ) ; return <NUM_LIT> ; } } if ( ! TREE_PUBLIC ( node -> decl ) ) { if ( TARGET_AVX512F ) clonei ->


<s> AliasResult <ISA_LIT>AAResult :: alias ( const MemoryLocation & LocA , const MemoryLocation & LocB , AAQueryInfo & AAQI ) { unsigned asA = LocA . Ptr -> getType ( ) -> getPointerAddressSpace ( ) ; unsigned asB = LocB . Ptr -> getType ( ) -> getPointerAddressSpace ( ) ; AliasResult Result = getAliasResult ( asA , asB ) ; if ( Result == NoAlias ) return Result ; MemoryLocation A = LocA ; MemoryLocation B = LocB ; if ( asA != <ISA_LIT>AS :: FLAT_ADDRESS ) { std :: swap ( asA , asB ) ; std :: swap ( A , B ) ; } if ( asA == <ISA_LIT>AS :: FLAT_ADDRESS && ( asB == <ISA_LIT>AS :: LOCAL_ADDRESS || asB == <ISA_LIT>AS :: PRIVATE_ADDRESS ) ) { const auto * ObjA = getUnderlyingObject ( A . Ptr -> stripPointerCastsAndInvariantGroups ( ) ) ; if ( const LoadInst * LI = dyn_cast < LoadInst >


<s> if ( TARGET_ELF && RS6000_SYMBOL_REF_TLS_P ( x ) ) return <NUM_LIT> ; if ( legitimate_indirect_address_p ( x , reg_ok_strict ) ) return <NUM_LIT> ; if ( TARGET_UPDATE && ( GET_CODE ( x ) == PRE_INC || GET_CODE ( x ) == PRE_DEC ) && mode_supports_pre_incdec_p ( mode ) && legitimate_indirect_address_p ( XEXP ( x , <NUM_LIT> ) , reg_ok_strict ) ) return <NUM_LIT> ; if ( virtual_stack_registers_memory_p ( x ) ) return <NUM_LIT> ; if ( reg_offset_p && legitimate_small_data_p ( mode , x ) ) return <NUM_LIT> ; if ( reg_offset_p && legitimate_constant_pool_address_p ( x , mode , reg_ok_strict || lra_in_progress ) ) return <NUM_LIT> ; if ( reg_offset_p && reg_addr [ mode ] . fused_toc && GET_CODE ( x ) == UNSPEC && XINT ( x , <NUM_LIT> ) == UNSPEC_FUSION_ADDIS ) return <NUM_LIT> ; if ( mode == TImode && TARGET_QUAD_MEMORY && TARGET_VSX_TIMODE )


<s> assert ( BCN != <NUM_LIT> && <STR_LIT> ) ; unsigned minSplatBits = EltVT . getSizeInBits ( ) ; if ( minSplatBits < <NUM_LIT> ) minSplatBits = <NUM_LIT> ; APInt APSplatBits , APSplatUndef ; unsigned SplatBitSize ; bool HasAnyUndefs ; if ( ! BCN -> isConstantSplat ( APSplatBits , APSplatUndef , SplatBitSize , HasAnyUndefs , minSplatBits ) || minSplatBits < SplatBitSize ) return SDValue ( ) ; uint64_t SplatBits = APSplatBits . getZExtValue ( ) ; switch ( VT . getSimpleVT ( ) ) { default : cerr << <STR_LIT> << VT . getMVTString ( ) << <STR_LIT> ; abort ( ) ; case <STR_LIT> : { uint32_t Value32 = uint32_t ( SplatBits ) ; assert ( SplatBitSize == <NUM_LIT> && <STR_LIT> ) ; SDValue T = DAG . getConstant ( Value32 , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , T , T , T , T ) ) ; break ; } case <STR_LIT> : { uint64_t f64val = uint64_t ( SplatBits ) ; assert ( SplatBitSize == <NUM_LIT> && <STR_LIT> ) ; SDValue T = DAG . getConstant ( f64val , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , T , T ) ) ; break ; } case <STR_LIT> : { unsigned short Value16 = SplatBits ; SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . assign ( <NUM_LIT> , DAG . getConstant ( Value16 , <STR_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , dl , VT , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , & Ops [ <NUM_LIT> ] , Ops . size ( ) ) ) ; } case <STR_LIT> : { unsigned short Value16 = SplatBits ; SDValue T = DAG . getConstant ( Value16 , EltVT ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . assign ( <NUM_LIT> , T ) ; return DAG . getNode ( <STR_LIT> , dl , VT , & Ops [ <NUM_LIT> ] , Ops . size ( ) ) ; } case <STR_LIT> : { SDValue T = DAG . getConstant ( unsigned ( SplatBits )


<s> } else { rtx offset ; offset = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( <NUM_LIT> , got_symbol ) , UNSPEC_LTREL_OFFSET ) ; offset = gen_rtx_CONST ( Pmode , offset ) ; offset = force_const_mem ( Pmode , offset ) ; emit_move_insn ( got_rtx , offset ) ; offset = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( <NUM_LIT> , XEXP ( offset , <NUM_LIT> ) ) , UNSPEC_LTREL_BASE ) ; offset = gen_rtx_PLUS ( Pmode , got_rtx , offset ) ; emit_move_insn ( got_rtx ,


<s> static bool isVGPRToSGPRCopy ( const TargetRegisterClass * SrcRC , const TargetRegisterClass * DstRC , const <ISA_LIT>RegisterInfo & TRI ) { return SrcRC != & <STR_LIT> && TRI . isSGPRClass (

DstRC ) && TRI . hasVectorRegisters ( SrcRC ) ;


<s> MFI -> setFrameAddressIsTaken ( true ) ; EVT PtrVT = getPointerTy ( MF . getDataLayout ( ) ) ; bool is<ISA_LIT>64 = PtrVT == <STR_LIT> ; unsigned FrameReg ; if ( MF . getFunction ( ) -> hasFnAttribute ( Attribute :: Naked ) ) FrameReg = is<ISA_LIT>64 ? <STR_LIT> : <STR_LIT> ; else FrameReg = is<ISA_LIT>64 ? <STR_LIT> : <STR_LIT> ; SDValue FrameAddr = DAG . getCopyFromReg ( DAG . getEntryNode ( ) , dl , FrameReg ,


<s> continue ; } if ( I -> isBranch ( ) ) { if ( TBB ) return nullptr ; CC = <STR_LIT> ( * I ) ; switch ( CC ) { default : return nullptr ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : break ; } TBB = I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; BrInstr = & * I ; continue ; } if ( analyzeCompare ( * I , SrcReg , CmpValue ) ) { if ( CmpInstr ) return nullptr ; CmpInstr = & * I ; continue ; } CmpBrOnly = false ; break ; } if ( ! TBB || ! FBB || ! CmpInstr ) return nullptr ; switch ( CC ) { case <STR_LIT> : CC = <STR_LIT>


<s> bool <ISA_LIT>TargetLowering :: isShuffleMaskLegal ( ArrayRef < int


<s> return true ; default : return false ; } } if ( VT == <STR_LIT> && Op == <STR_LIT> ) return false ; return TargetLowering :: isTypeDesirableForOp ( Op , VT


<s> while ( I != MBB -> instr_end ( ) && I -> isInsideBundle ( ) ) { EmitInstruction ( & * I ) ; ++ I ; } } else { if ( MI -> getOpcode ( ) == <STR_LIT> ) { if ( isVerbose ( ) ) { SmallVector < char , <NUM_LIT> > BBStr ; raw_svector_ostream Str ( BBStr ) ; const MachineBasicBlock * MBB = MI -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; const MCSymbolRefExpr * Expr = MCSymbolRefExpr :: create ( MBB -> getSymbol ( ) , OutContext ) ; Expr -> print ( Str , MAI ) ; OutStreamer -> emitRawComment ( <STR_LIT> + BBStr ) ; } return ; } if ( MI -> getOpcode ( ) == <STR_LIT> ) { if ( isVerbose ( ) ) OutStreamer -> emitRawComment ( <STR_LIT> ) ; return ; } MCInst TmpInst ; MCInstLowering . lower ( MI , TmpInst ) ; EmitToStreamer ( * OutStreamer , TmpInst ) ; if ( STI . dumpCode ( )


<s> SDValue NewBV = DAG . getBitcast ( <STR_LIT> , DAG . getBuildVector ( VT , DL , Ops ) ) ; SDValue Dup = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , NewBV ) ; return DAG . getBitcast ( VT , Dup ) ; } std :: bitset < <NUM_LIT> > Zeroable , Undefs ; for ( int i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) { SDValue Elt = Op . getOperand ( i ) ; Undefs [ i ] = Elt . isUndef ( ) ; Zeroable [ i ] = ( Elt . isUndef ( ) || <STR_LIT> ( Elt ) ) ; } assert ( Zeroable . size ( ) - Zeroable . count ( ) > <NUM_LIT> && <STR_LIT> ) ; SDValue FirstNonZero ; unsigned FirstNonZeroIdx ; for ( unsigned i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) { if ( Zeroable [ i ] ) continue ; SDValue Elt = Op . getOperand ( i ) ; if ( Elt . getOpcode ( ) != <STR_LIT> || ! isa < ConstantSDNode > ( Elt . getOperand ( <NUM_LIT> ) ) ) return SDValue ( ) ; MVT VT = Elt . getOperand ( <NUM_LIT> ) . getSimpleValueType ( ) ; if ( ! VT . is128BitVector ( ) ) return SDValue ( ) ; if ( ! FirstNonZero . getNode ( ) ) { FirstNonZero = Elt ; FirstNonZeroIdx = i ; } } assert ( FirstNonZero . getNode ( ) && <STR_LIT> ) ; SDValue V1 = FirstNonZero . getOperand ( <NUM_LIT> ) ; MVT VT = V1 . getSimpleValueType ( ) ; SDValue Elt ; unsigned EltMaskIdx , EltIdx ; int Mask [ <NUM_LIT> ]


<s> void setOffset ( int64_t O ) { Offset =


<s> return ( ( MI -> getOpcode ( ) == <STR_LIT> ) || ( MI -> getOpcode ( )


<s> case CallingConv :: <ISA_LIT>_Device : assert ( Outs . size ( ) <= <NUM_LIT> && <STR_LIT> ) ; break ; } if ( Outs . size ( ) == <NUM_LIT> ) return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Chain ) ; assert ( Outs [ <NUM_LIT> ] . VT == <STR_LIT> && <STR_LIT> ) ; SDValue Flag ; unsigned reg = <STR_LIT> ; MachineFunction & MF = DAG . getMachineFunction ( ) ; <ISA_LIT>MachineFunctionInfo * MFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; MFI -> setRetReg ( reg ) ; if ( DAG . getMachineFunction ( ) . getRegInfo ( ) . liveout_empty ( ) ) DAG . getMachineFunction ( )


<s> static uint64_t clearUnusedBits ( uint64_t Val , unsigned Size ) { if ( ! <STR_LIT> ( Val


<s> bool hasFlatScratchSVSMode ( ) const { return GFX940Insts


<s> cvtVOP3 ( Inst , Operands , OptionalIdx


<s> MCObjectWriter * llvm :: create<ISA_LIT>ELFObjectWriter ( raw_pwrite_stream & OS , uint8_t OSABI ) { MCELFObjectTargetWriter * MOTW = new <ISA_LIT>ELFObjectWriter ( OSABI ) ; return createELFObjectWriter ( MOTW ,


<s> static const SDValue * getNormalLoadInput ( const SDValue & Op , bool & IsPermuted ) { const SDValue * InputLoad = & Op ; if ( InputLoad -> getOpcode ( ) == <STR_LIT> ) InputLoad = & InputLoad -> getOperand ( <NUM_LIT> ) ; if ( InputLoad -> getOpcode ( ) == <STR_LIT> || InputLoad -> getOpcode ( ) == <STR_LIT> ) { IsPermuted = InputLoad -> getOpcode ( ) == <STR_LIT> ; InputLoad = & InputLoad -> getOperand ( <NUM_LIT> ) ; } if ( InputLoad -> getOpcode ( )


<s> void <ISA_LIT>TargetID :: setTargetIDFromTargetIDStream ( StringRef TargetID ) { SmallVector < StringRef , <NUM_LIT> > TargetIDSplit ; TargetID . split ( TargetIDSplit


<s> for ( const SDUse & U : Op -> ops ( ) ) DAG . ExtractVectorElements ( U . get ( ) , Args ) ; return DAG . getBuildVector ( Op . getValueType ( ) , SDLoc ( Op


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; addExpr ( Inst , getImm (


<s> const SmallVectorImpl < Register > & getMustSaveCRs (


<s> return MI . getFlags ( ) & <STR_LIT>


<s> default : llvm_unreachable ( <STR_LIT> ) ; case InlineAsm :: Constraint_i : case InlineAsm :: Constraint_m : case InlineAsm :: Constraint_Q : case InlineAsm :: Constraint_Um : case InlineAsm :: Constraint_Un : case InlineAsm :: Constraint_Uq : case InlineAsm :: Constraint_Us : case InlineAsm :: Constraint_Ut : case InlineAsm :: Constraint_Uv : case InlineAsm :: Constraint_Uy : OutOps . push_back ( Op ) ; return false ; } return


<s> return CreateReg ( Index , RegKind_ACC , RegInfo , S ,


<s> unsigned tmp = ( S << <NUM_LIT> ) | ( I1 << <NUM_LIT> ) | ( I2 << <NUM_LIT> ) | ( imm10 << <NUM_LIT> ) | imm11 ; int imm32 = SignExtend32 < <NUM_LIT> > ( tmp << <NUM_LIT> ) ; if ( ! tryAddingSymbolicOperand ( Address , Address + imm32 + <NUM_LIT> , true , <NUM_LIT> , Inst ,

Decoder ) ) Inst . addOperand ( MCOperand :: CreateImm ( imm32 ) ) ;


<s> static inline void desc_spill_base ( unw_word pspoff , struct unw_state_record * sr ) { sr -> spill_offset = <NUM_LIT>


<s> void <ISA_LIT>MachineCFGStructurizer :: replaceInstrUseOfBlockWith ( MachineBasicBlock * SrcMBB , MachineBasicBlock * OldMBB , MachineBasicBlock *


<s> assert ( ! F || isKernelCC ( F ) ) ; while ( ! Stack . empty ( ) ) { const User * V = Stack . pop_back_val ( ) ; Visited . insert ( V ) ; if ( auto * G = dyn_cast < GlobalValue > ( V -> stripPointerCasts ( ) ) ) { if ( UsedList . contains ( G ) ) { continue ; } } if ( auto * I = dyn_cast < Instruction > ( V ) ) { const Function * UF = I -> getFunction ( ) ; if ( UF == F ) { Ret = true ; } else if ( ! F ) { Ret |= ! isKernelCC ( UF ) ; } continue ; } if ( auto * E = dyn_cast < ConstantExpr > ( V ) ) { if ( F ) { if ( ! isUsedOnlyFromFunction ( E , F ) ) return false ; } for ( const User * U : E -> users ( ) ) { if ( Visited . insert ( U ) . second ) { Stack . push_back ( U ) ; } } continue ; } return !


<s> static StringRef computeDataLayout ( const Triple & TT ) { if ( TT . getArch ( ) == Triple :: r600 ) { return <STR_LIT>


<s> void EncodeInstruction ( const MCInst & MI , raw_ostream & OS , SmallVectorImpl < MCFixup > & Fixups ) const { unsigned Bits = getBinaryCodeForInstr ( MI , Fixups ) ; for ( unsigned i = <NUM_LIT> ; i != <NUM_LIT> ; ++ i ) { OS << ( char ) ( Bits >> <NUM_LIT> ) ; Bits <<= <NUM_LIT> ; } ++ MCNumEmitted


<s> MI -> setDesc ( TII -> get ( UseCopy ? <STR_LIT> : <STR_LIT> ) ) ; return true ; } } if ( Src0 -> isImm ( ) && Src1 -> isImm ( ) ) { int32_t NewImm ; if ( ! evalBinaryInstruction ( Opc , NewImm , Src0 -> getImm ( ) , Src1 -> getImm ( ) ) ) return false ; const <ISA_LIT>RegisterInfo & TRI = TII -> getRegisterInfo ( ) ; bool IsSGPR = TRI . isSGPRReg ( MRI , MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; MI -> getOperand ( Src0Idx ) . ChangeToImmediate ( NewImm ) ; MI -> RemoveOperand ( Src1Idx ) ; mutateCopyOp ( * MI , TII -> get ( getMovOpc ( IsSGPR ) ) ) ; return true ; } if ( ! MI -> isCommutable ( ) ) return false ; if ( Src0 -> isImm ( ) && ! Src1 -> isImm ( ) ) { std :: swap ( Src0 , Src1 ) ; std :: swap ( Src0Idx , Src1Idx ) ; } int32_t Src1Val = static_cast < int32_t > ( Src1 -> getImm ( ) ) ; if ( Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ) { if ( Src1Val == <NUM_LIT> ) { MI -> RemoveOperand ( Src1Idx ) ; mutateCopyOp ( * MI , TII -> get ( <STR_LIT> ) ) ; } else if ( Src1Val == - <NUM_LIT> ) { MI -> RemoveOperand ( Src1Idx ) ; mutateCopyOp ( * MI , TII -> get ( getMovOpc ( Opc == <STR_LIT> ) ) ) ; } else return false ; return true ; } if ( MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> ) { if ( Src1Val == <NUM_LIT> ) { MI -> RemoveOperand ( Src0Idx ) ; mutateCopyOp ( * MI , TII -> get (


<s> Inst . addOperand ( MCOperand :: createReg ( CRRegs [ getCRBitMask (


<s> const <ISA_LIT>InstrInfo & TII = * STI . getInstrInfo ( ) ; assert ( STI . isTargetWin64 ( ) && <STR_LIT> ) ; if ( ! MF . hasWinCFI ( ) ) return false ; bool Changed = false ; for ( MachineBasicBlock & MBB : MF ) { MachineBasicBlock * NextMBB = MBB . getNextNode ( ) ; if ( NextMBB && ! NextMBB -> isEHFuncletEntry ( ) ) continue ; auto LastRealInstr = llvm :: find_if ( reverse ( MBB ) , isRealInstruction ) ; bool IsEmpty = LastRealInstr == MBB . rend ( ) ; bool IsCall = ! IsEmpty && isCallInstruction ( * LastRealInstr ) ; if ( IsEmpty || IsCall ) { LLVM_DEBUG ( { if ( IsCall ) { dbgs ( ) << <STR_LIT> ; LastRealInstr -> dump ( ) ; dbgs ( ) << '\n' ; } else { dbgs ( ) << <STR_LIT> ; MBB . dump ( ) ; } } ) ; MachineBasicBlock :: iterator MBBI =


<s> { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } } ; if ( Kind < FirstTargetFixupKind ) return TargetAsmBackend :: getFixupKindInfo (


<s> } SmallVector < int , <NUM_LIT> > OptimizeShuf ; Value * Temp [ <NUM_LIT> ] ; for ( unsigned i = <NUM_LIT> ; i < ( VecElems / <NUM_LIT> ) * Stride ; i += <NUM_LIT> ) { genShuffleBland ( VT , VPShuf , OptimizeShuf , ( i / Stride ) * <NUM_LIT> , ( i + <NUM_LIT> ) / Stride * <NUM_LIT> ) ; Temp [ i / <NUM_LIT> ] = Builder . CreateShuffleVector ( Vec [ i % Stride ] , Vec [ ( i + <NUM_LIT> ) % Stride ] , OptimizeShuf ) ; OptimizeShuf . clear ( ) ; } if ( VecElems == <NUM_LIT> ) { std :: copy ( Temp , Temp + Stride , TransposedMatrix . begin ( ) ) ; return ; } else for ( unsigned i = <NUM_LIT> ; i < Stride ; i ++ ) TransposedMatrix [ i ] = Builder . CreateShuffleVector ( Temp [ <NUM_LIT> * i ] ,

Temp [ <NUM_LIT> * i + <NUM_LIT> ] , Concat ) ;


<s> bool <ISA_LIT>PacketizerList :: canReserveResourcesForConstExt ( MachineInstr * MI ) { const <ISA_LIT>InstrInfo * QII = ( const <ISA_LIT>InstrInfo * ) TII ; assert ( QII -> isExtended ( MI ) && <STR_LIT> ) ; MachineFunction * MF = MI -> getParent ( ) -> getParent ( ) ; MachineInstr * PseudoMI = MF -> CreateMachineInstr ( QII -> get ( <STR_LIT> ) , MI -> getDebugLoc


<s> return false ; case ELF :: R_<ISA_LIT>_REL24 : unsigned Other = MCELF :: getOther ( SD


<s> <ISA_LIT>MachineFunctionInfo :: <ISA_LIT>MachineFunctionInfo ( const MachineFunction & MF ) : <ISA_LIT>MachineFunction ( MF ) , TIDReg ( <STR_LIT> ) , ScratchRSrcReg ( <STR_LIT> ) , ScratchWaveOffsetReg ( <STR_LIT> ) , FrameOffsetReg ( <STR_LIT> ) , StackPtrOffsetReg ( <STR_LIT> ) , PrivateSegmentBufferUserSGPR ( <STR_LIT> ) , DispatchPtrUserSGPR ( <STR_LIT> ) , QueuePtrUserSGPR ( <STR_LIT> ) , KernargSegmentPtrUserSGPR ( <STR_LIT> ) , DispatchIDUserSGPR ( <STR_LIT> ) , FlatScratchInitUserSGPR ( <STR_LIT> ) , PrivateSegmentSizeUserSGPR ( <STR_LIT> ) , GridWorkGroupCountXUserSGPR ( <STR_LIT> ) , GridWorkGroupCountYUserSGPR ( <STR_LIT> ) , GridWorkGroupCountZUserSGPR ( <STR_LIT> ) , WorkGroupIDXSystemSGPR ( <STR_LIT> ) , WorkGroupIDYSystemSGPR ( <STR_LIT> ) , WorkGroupIDZSystemSGPR ( <STR_LIT> ) , WorkGroupInfoSystemSGPR ( <STR_LIT> ) , PrivateSegmentWaveByteOffsetSystemSGPR ( <STR_LIT> ) , WorkItemIDXVGPR ( <STR_LIT> ) , WorkItemIDYVGPR ( <STR_LIT> ) , WorkItemIDZVGPR ( <STR_LIT> ) , P<ISA_LIT>nputAddr ( <NUM_LIT> ) , P<ISA_LIT>nputEnable ( <NUM_LIT> ) , ReturnsVoid ( true ) , FlatWorkGroupSizes ( <NUM_LIT> , <NUM_LIT> ) , WavesPerEU ( <NUM_LIT> , <NUM_LIT> ) , DebuggerWorkGroupIDStackObjectIndices ( { { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } } ) , DebuggerWorkItemIDStackObjectIndices ( { { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } } ) , LDSWaveSpillSize ( <NUM_LIT> ) , NumUserSGPRs ( <NUM_LIT> ) , NumSystemSGPRs ( <NUM_LIT> ) , HasSpilledSGPRs ( false ) , HasSpilledVGPRs ( false ) , HasNonSpillStackObjects ( false ) , NumSpilledSGPRs ( <NUM_LIT> ) , NumSpilledVGPRs ( <NUM_LIT> ) , PrivateSegmentBuffer ( false ) , DispatchPtr ( false ) , QueuePtr ( false ) , KernargSegmentPtr ( false ) , DispatchID ( false ) , FlatScratchInit ( false ) , GridWorkgroupCountX ( false ) , GridWorkgroupCountY ( false ) , GridWorkgroupCountZ ( false ) , WorkGroupIDX ( false ) , WorkGroupIDY ( false ) , WorkGroupIDZ ( false ) , WorkGroupInfo ( false ) , PrivateSegmentWaveByteOffset ( false ) , WorkItemIDX ( false ) , WorkItemIDY ( false ) , WorkItemIDZ ( false ) , ImplicitBufferPtr ( false ) { const <ISA_LIT>Subtarget & ST = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; const Function * F = MF . getFunction ( ) ; FlatWorkGroupSizes = ST . getFlatWorkGroupSizes ( * F ) ; WavesPerEU = ST . getWavesPerEU ( * F ) ; if ( ! isEntryFunction ( ) ) { ScratchRSrcReg = <STR_LIT> ; ScratchWaveOffsetReg = <STR_LIT> ; FrameOffsetReg = <STR_LIT> ; StackPtrOffsetReg = <STR_LIT> ; PrivateSegmentWaveByteOffsetSystemSGPR = ScratchWaveOffsetReg ; } CallingConv :: ID CC =


<s> void <ISA_LIT>InstrInfo :: insertNoop ( MachineBasicBlock & MBB

, MachineBasicBlock :: iterator MI ) const {


<s> static __inline qword si_nor ( qword a


<s> MachineFunction & MF = DAG . getMachineFunction ( ) ; <ISA_LIT>FunctionInfo * FuncInfo = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; DebugLoc dl = Op . getDebugLoc ( ) ; SDValue FI = DAG . getFrameIndex ( FuncInfo -> getVarArgsFrameIndex (


<s> DeadInstrs . insert ( & Tail ) ; MRI -> replaceRegWith ( Tail . getOperand ( <NUM_LIT> ) . getReg ( ) , LoADDI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << Offset << <STR_LIT> << <STR_LIT> << HiLUI


<s> return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case


<s> kb != ke ; ++ kb ) { <ISA_LIT>Kernel * ptr = kb -> getValue ( ) ; delete


<s> LoadSDNode * LD = cast < LoadSDNode > ( Op ) ; EVT MemVT = LD -> getMemoryVT ( ) ; if ( ( LD -> getAlignment ( ) >= MemVT . getSizeInBits ( ) / <NUM_LIT> ) || ( ( MemVT != <STR_LIT> ) && ( MemVT != <STR_LIT> ) ) ) return SDValue ( ) ; bool IsLittle = Subtarget -> isLittle ( ) ; EVT VT = Op . getValueType ( ) ; <STR_LIT> ExtType = LD -> getExtensionType ( ) ; SDValue Chain = LD -> getChain ( ) , Undef = DAG . getUNDEF ( VT ) ; assert ( ( VT == <STR_LIT> ) || ( VT == <STR_LIT> ) ) ; if ( ( VT == <STR_LIT> ) && ( ExtType == <STR_LIT> ) ) { SDValue LDL = createLoadLR ( <STR_LIT> , DAG , LD , Chain , Undef , IsLittle ? <NUM_LIT> : <NUM_LIT> ) ; return createLoadLR ( <STR_LIT> , DAG , LD , LDL . getValue ( <NUM_LIT> ) , LDL , IsLittle ? <NUM_LIT> : <NUM_LIT> ) ; } SDValue LWL = createLoadLR ( <STR_LIT> , DAG , LD , Chain , Undef , IsLittle ? <NUM_LIT> : <NUM_LIT> ) ; SDValue LWR = createLoadLR ( <STR_LIT> , DAG , LD , LWL . getValue ( <NUM_LIT> ) , LWL , IsLittle ? <NUM_LIT> : <NUM_LIT> ) ; if ( ( VT == <STR_LIT> ) || ( ExtType == <STR_LIT> ) || (


<s> void addu7ExtOperands ( MCInst & Inst , unsigned N ) const { addImmOperands ( Inst ,


<s> FunctionPass * llvm :: create<ISA_LIT>ISelDag ( <ISA_LIT>TargetMachine & TM ) { return new <ISA_LIT>DAGToDAGISel


<s> else if ( STI -> hasV8MMainlineOps ( ) ) CMSERestoreFPRegsV8 ( MBB , MBBI , DL


<s> if ( DEFAULT_ABI == ABI_ELFv2 && type && AGGREGATE_TYPE_P ( type ) ) { machine_mode field_mode = VOIDmode ; int field_count = rs6000_aggregate_candidate ( type , & field_mode ) ; if ( field_count > <NUM_LIT> ) { int n_regs = ( SCALAR_FLOAT_MODE_P ( field_mode ) ? ( GET_MODE_SIZE ( field_mode ) + <NUM_LIT> ) >> <NUM_LIT> : <NUM_LIT> ) ; if ( field_count * n_regs <= AGGR_ARG_NUM_REG ) { if ( elt_mode ) * elt_mode = field_mode ; if ( n_elts ) * n_elts = field_count ; return true ; } } } if ( elt_mode ) *


<s> SDValue <ISA_LIT>TargetLowering :: getSqrtEstimate ( SDValue Operand , SelectionDAG & DAG , int Enabled , int & RefinementSteps , bool & UseOneConstNR , bool Reciprocal ) const { EVT VT = Operand . getValueType ( ) ; if ( ( VT == <STR_LIT> && Subtarget . hasFRSQRTES ( ) ) || ( VT == <STR_LIT> && Subtarget . hasFRSQRTE ( ) ) || ( VT == <STR_LIT> && Subtarget . hasAltivec ( ) ) || ( VT == <STR_LIT> && Subtarget . hasVSX ( ) ) || ( VT == <STR_LIT> && Subtarget . hasQPX ( ) ) || ( VT == <STR_LIT> && Subtarget . hasQPX ( ) ) ) { if ( RefinementSteps == ReciprocalEstimate :: Unspecified ) RefinementSteps = getEstimateRefinementSteps ( VT , Subtarget ) ; UseOneConstNR = ! Subtarget . needsTwoConstNR ( ) ; return DAG . getNode ( <STR_LIT> , SDLoc ( Operand ) , VT , Operand ) ; } return SDValue (


<s> const uint16_t * <ISA_LIT>RegisterInfo :: getCalleeSavedRegs ( const MachineFunction


<s> <STR_LIT> Int = IsRelease ? <STR_LIT> : <STR_LIT> ; Function * Strex = <STR_LIT> ( M , Int ) ; Type * Int32Ty = Type :: getInt32Ty ( M -> getContext ( ) ) ; Value * Lo = Builder . CreateTrunc ( Val , Int32Ty , <STR_LIT> ) ; Value * Hi = Builder . CreateTrunc ( Builder . CreateLShr ( Val , <NUM_LIT> ) , Int32Ty , <STR_LIT> ) ; if ( ! Subtarget -> isLittle ( ) ) std :: swap ( Lo , Hi ) ; Addr = Builder . CreateBitCast ( Addr , Type :: getInt8PtrTy ( M -> getContext ( ) ) ) ; return Builder . CreateCall ( Strex , { Lo , Hi , Addr } ) ; } <STR_LIT> Int = IsRelease ? <STR_LIT> : <STR_LIT> ; Type * Tys [ ] = {


<s> ScratchSizeKey = PALMD :: Key :: GS_SCRATCH_<ISA_LIT>ZE ; break ; case CallingConv :: <ISA_LIT>_ES : ScratchSizeKey = PALMD :: Key :: ES_SCRATCH_<ISA_LIT>ZE ; break ; case CallingConv :: <ISA_LIT>_HS : ScratchSizeKey = PALMD :: Key :: HS_SCRATCH_<ISA_LIT>ZE ; break ; case CallingConv :: <ISA_LIT>_LS : ScratchSizeKey = PALMD :: Key :: LS_SCRATCH_<ISA_LIT>ZE ; break ; } unsigned NumUsedVgprsKey = ScratchSizeKey + PALMD :: Key :: VS_NUM_USED_VGPRS - PALMD :: Key :: VS_SCRATCH_<ISA_LIT>ZE ; unsigned NumUsedSgprsKey = ScratchSizeKey + PALMD :: Key :: VS_NUM_USED_SGPRS - PALMD :: Key :: VS_SCRATCH_<ISA_LIT>ZE ; PALMetadataMap [ NumUsedVgprsKey ] = CurrentProgramInfo . NumVGPRsForWavesPerEU ; PALMetadataMap [ NumUsedSgprsKey ] = CurrentProgramInfo . NumSGPRsForWavesPerEU ; if ( <STR_LIT> ( MF . getFunction ( ) -> getCallingConv ( ) ) ) { PALMetadataMap [ Rsrc1Reg ] |= CurrentProgramInfo . ComputePGMRSrc1 ; PALMetadataMap [ Rsrc2Reg ] |= CurrentProgramInfo . ComputePGMRSrc2 ; PALMetadataMap [ ScratchSizeKey ] |= alignTo ( CurrentProgramInfo . ScratchSize , <NUM_LIT> ) ; } else { PALMetadataMap [ Rsrc1Reg ] |= S_00B028_VGPRS ( CurrentProgramInfo . VGPRBlocks ) | S_00B028_SGPRS ( CurrentProgramInfo . SGPRBlocks ) ; if ( CurrentProgramInfo . ScratchBlocks > <NUM_LIT> ) PALMetadataMap [ Rsrc2Reg ] |= S_00B84C_SCRATCH_EN ( <NUM_LIT> ) ; PALMetadataMap [ ScratchSizeKey ] |= alignTo ( CurrentProgramInfo


<s> Val = std :: numeric_limits < double > :: quiet_NaN ( ) ; } else { return true ; } if ( IsNegative ) Val = - Val ; Operands . push_back ( std :: make_unique < <ISA_LIT>Operand > ( <STR_LIT> , Flt . getLoc ( ) , Flt . getEndLoc ( ) , <STR_LIT> { Val } ) ) ; Parser . Lex ( ) ; return false


<s> <ISA_LIT>AsmParser :: OperandMatchResultTy <ISA_LIT>AsmParser :: parseMSA128HRegs ( SmallVectorImpl < MCParsedAsmOperand * > & Operands ) { return parseMSARegs ( Operands , (


<s> break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; default : return false ; } unsigned Reg ; if ( FuncInfo . Fn -> getAttributes ( ) . hasAttribute ( <NUM_LIT> , Attribute :: SExt


<s> UCB_SAVED_CALLSITE_ADDR ( ucbp ) = vrs -> core . r [ R_PC ] ; pr_result = ( ( personality_routine ) UCB_PR_ADDR ( ucbp ) ) ( _US_UNWIND_FRAME_STARTING , ucbp , ( _Unwind_Context * ) vrs ) ; } while ( pr_result ==


<s> switch ( Opcode ) { default : return NULL ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> :


<s> unsigned Opc = N -> getOpcode ( ) ; MVT VT = N -> getSimpleValueType ( <NUM_LIT> ) ; SDLoc DL ( N ) ; if ( N -> hasAnyUseOfValue ( <NUM_LIT> ) ) { if ( Opc == <STR_LIT> ) { RHS = DAG . getNode ( <STR_LIT> , DL , VT , DAG . getConstant ( <NUM_LIT> , DL , VT ) , RHS ) ; return DAG . getAtomic ( <STR_LIT> , DL , VT , Chain , LHS , RHS , AN -> getMemOperand ( ) ) ; } assert ( Opc == <STR_LIT> && <STR_LIT> ) ; return N ; } if ( Opc == <STR_LIT> && isNullConstant ( RHS ) ) { if ( AN -> getOrdering ( ) == AtomicOrdering :: SequentiallyConsistent && AN -> getSyncScopeID ( ) == SyncScope :: System ) { SDValue NewChain = emitLockedStackOp ( DAG , Subtarget , Chain , DL ) ; assert ( ! N -> hasAnyUseOfValue ( <NUM_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , DL , N -> getVTList ( ) , DAG . getUNDEF ( VT ) , NewChain ) ; } SDValue NewChain = DAG . getNode ( <STR_LIT> ,


<s> FunctionPass * llvm :: create<ISA_LIT>BranchDelayReducer


<s> N = N . getOperand ( <NUM_LIT> ) ; } if ( N . getOpcode ( ) != <STR_LIT> ) return false ; unsigned Opc = N . getOperand ( <NUM_LIT> ) -> getOpcode ( ) ; if ( Opc != <STR_LIT> || ! WasTruncated ) { Op = N . getOperand ( <NUM_LIT> ) ; return ! WasTruncated ; } auto * GA = cast < GlobalAddressSDNode > ( N .


<s> void ELF<ISA_LIT>AsmBackend :: processFixupValue ( const MCAssembler & Asm , const MCAsmLayout & Layout , const MCFixup & Fixup , const MCFragment * DF , const MCValue & Target , uint64_t & Value , bool & IsResolved ) { if ( ( uint32_t ) Fixup . getKind ( ) == <STR_LIT> ) IsResolved = false ; if ( IsResolved ) ( void ) adjustFixupValue ( Fixup , Value , & Asm .


<s> bool isMachineVerifierClean ( ) const override { return


<s> bool <ISA_LIT>RegisterInfo :: hasReservedCallFrame ( const MachineFunction & MF ) const { return ! MF . getFrameInfo ( )


<s> if ( args_so_farp -> regs + <NUM_LIT> < MMIX_MAX_ARGS_IN_REGS ) * pretend_sizep = ( MMIX_MAX_ARGS_IN_REGS - ( args_so_farp -> regs + <NUM_LIT> ) ) * <NUM_LIT> ; if ( ( <NUM_LIT> + ( MMIX_FUNCTION_ARG_SIZE ( mode , vartype ) ) )


<s> <ISA_LIT>AsmParser ( const MCSubtargetInfo & sti , MCAsmParser & Parser , const MCInstrInfo & mii , const MCTargetOptions & Options ) : MCTargetAsmParser ( Options , sti , mii ) , Parser ( Parser ) , Lexer ( Parser . getLexer ( ) ) , LastLabel ( nullptr ) { setAvailableFeatures ( ComputeAvailableFeatures ( sti . getFeatureBits ( )


<s> static DecodeStatus DecodeHIRegsDSPRegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t Address , const void * Decoder ) { if ( RegNo >= <NUM_LIT> ) return MCDisassembler :: Fail ; unsigned Reg = getReg ( Decoder ,


<s> if ( Imm . bitwiseIsEqual ( LegalFPImmediates [ i ] ) ) return true ; } return


<s> MachineBasicBlock * UserBB = U . MI -> getParent ( ) ; unsigned MinNoSplitDisp = BBInfo [ UserBB -> getNumber ( ) ] . postOffset ( getCPELogAlign ( U . CPEMI ) ) ; if ( CloserWater && MinNoSplitDisp > U . getMaxDisp ( ) / <NUM_LIT> ) return false ; for ( water_iterator IP = std :: prev ( WaterList . end ( ) ) , B = WaterList . begin ( ) ; ; -- IP ) { MachineBasicBlock * WaterBB = * IP ; unsigned Growth ; if ( isWaterInRange ( UserOffset , WaterBB , U , Growth ) && ( WaterBB -> getNumber ( ) < U . HighWaterMark -> getNumber ( ) || NewWaterList . count ( WaterBB ) || WaterBB == U . MI -> getParent ( ) ) && Growth < BestGrowth ) { BestGrowth = Growth ; WaterIter = IP ; DEBUG ( dbgs ( ) << <STR_LIT> << printMBBReference ( * WaterBB ) << <STR_LIT> << Growth << '\n' ) ; if ( CloserWater && WaterBB == U . MI -> getParent ( ) ) return true ; if ( ! CloserWater && BestGrowth == <NUM_LIT> ) return true ; } if ( IP == B )


<s> unsigned long long res ; __asm__ ( <STR_LIT> : <STR_LIT> ( res ) : <STR_LIT> ( mm ) , <STR_LIT> ( mn ) ) ; return