<s> int i ; rtx par ; int shift ; aapcs_vfp_is_call_or_return_candidate ( pcs_variant , mode , type , & ag_mode , & count ) ; if ( ! TARGET_NEON ) { if ( ag_mode == V2SImode ) ag_mode = DImode ; else if ( ag_mode == V4SImode ) { ag_mode = DImode ; count *= <NUM_LIT> ; } } shift = GET_MODE_SIZE ( ag_mode ) / GET_MODE_SIZE ( SFmode ) ; par = gen_rtx_PARALLEL ( mode , rtvec_alloc ( count ) ) ; for ( i = <NUM_LIT> ; i < count ; i ++ ) { rtx tmp = gen_rtx_REG ( ag_mode , FIRST_VFP_REGNUM + i


<s> static bool isSuitableForMask ( MachineInstr * & MI , unsigned SrcReg , int CmpMask , bool CommonUse ) { switch ( MI -> getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : if ( CmpMask != MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) return false ; if ( SrcReg == MI -> getOperand ( CommonUse ? <NUM_LIT> : <NUM_LIT> ) . getReg ( ) ) return true ; break ; case <STR_LIT> : { const MachineInstr & Copy = * MI ; MachineBasicBlock :: iterator AND ( std :: next ( MachineBasicBlock :: iterator ( MI )


<s> unsigned Opcode = I -> getOpcode ( ) ; if ( Opcode != <STR_LIT> && Opcode != <STR_LIT> ) return true ; <STR_LIT> BranchCode = ( <STR_LIT> ) I -> getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( Cond . empty ( ) ) { MachineBasicBlock * TargetBB = I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; if ( AllowModify && UnCondBrIter != MBB . end ( ) && MBB . isLayoutSuccessor ( TargetBB ) ) { BranchCode = GetOppositeBranchCondition ( BranchCode ) ; MachineBasicBlock :: iterator OldInst = I ; BuildMI ( MBB , UnCondBrIter , MBB . findDebugLoc ( I ) , get ( Opcode ) ) . addMBB ( UnCondBrIter -> getOperand ( <NUM_LIT> ) . getMBB ( ) ) . addImm ( BranchCode ) ; BuildMI ( MBB , UnCondBrIter , MBB . findDebugLoc ( I ) , get ( <STR_LIT> ) ) . addMBB ( TargetBB ) ; OldInst -> eraseFromParent ( ) ; UnCondBrIter -> eraseFromParent ( ) ; UnCondBrIter = MBB . end ( ) ; I = MBB . end ( ) ; continue ; } FBB = TBB ; TBB = I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; Cond . push_back ( MachineOperand :: CreateImm ( BranchCode ) ) ; continue ; } return true ; } return false


<s> return ( __m128 ) __builtin_ia32_movss ( ( __v4sf ) __A , ( __v4sf )


<s> assert ( <NUM_LIT> < MaxStages && MaxStages <= <NUM_LIT> && ( BitSize << MaxStages ) <= <NUM_LIT> && <STR_LIT> ) ; auto MatchPACK = [ & ] ( SDValue N1 , SDValue N2 , MVT PackVT ) { unsigned NumSrcBits = PackVT . getScalarSizeInBits ( ) ; unsigned NumPackedBits = NumSrcBits - BitSize ; N1 = peekThroughBitcasts ( N1 ) ; N2 = peekThroughBitcasts ( N2 ) ; unsigned NumBits1 = N1 . getScalarValueSizeInBits ( ) ; unsigned NumBits2 = N2 . getScalarValueSizeInBits ( ) ; bool IsZero1 = llvm :: isNullOrNullSplat ( N1 , false ) ; bool IsZero2 = llvm :: isNullOrNullSplat ( N2 , false ) ; if ( ( ! N1 . isUndef ( ) && ! IsZero1 && NumBits1 != NumSrcBits ) || ( ! N2 . isUndef ( ) && ! IsZero2 && NumBits2 != NumSrcBits ) ) return false ; if ( Subtarget . hasSSE41 ( ) || BitSize == <NUM_LIT> ) { APInt ZeroMask = APInt :: getHighBitsSet ( NumSrcBits , NumPackedBits ) ; if ( ( N1 . isUndef ( ) || IsZero1 || DAG . MaskedValueIsZero ( N1 , ZeroMask ) ) && ( N2 . isUndef ( ) || IsZero2 || DAG . MaskedValueIsZero ( N2 , ZeroMask ) ) ) { V1 = N1 ; V2 = N2 ; SrcVT = PackVT ; PackOpcode = <STR_LIT> ; return true ; } } bool IsAllOnes1 = llvm :: isAllOnesOrAllOnesSplat ( N1 , false ) ; bool IsAllOnes2 = llvm :: isAllOnesOrAllOnesSplat ( N2 , false ) ; if ( ( N1 . isUndef ( ) || IsZero1 || IsAllOnes1 || DAG . ComputeNumSignBits ( N1 ) > NumPackedBits ) && ( N2 . isUndef ( ) || IsZero2 || IsAllOnes2 || DAG . ComputeNumSignBits ( N2 ) > NumPackedBits ) ) { V1 = N1 ; V2 = N2 ; SrcVT = PackVT ; PackOpcode = <STR_LIT> ; return true ; } return false ; } ; for ( unsigned NumStages = <NUM_LIT> ; NumStages <= MaxStages ; ++ NumStages ) { MVT PackSVT = <STR_LIT> ( BitSize << NumStages ) ; MVT PackVT = <STR_LIT> ( PackSVT , NumElts >> NumStages ) ; SmallVector < int , <NUM_LIT> > BinaryMask ; createPackShuffleMask ( VT , BinaryMask , false


<s> void <ISA_LIT>FrameLowering :: emitEpilogue ( MachineFunction & MF , MachineBasicBlock & MBB ) const { if ( ! hasFP ( MF ) ) { report_fatal_error ( <STR_LIT> ) ; } MachineBasicBlock :: iterator MBBI = MBB . getLastNonDebugInstr ( ) ; const <ISA_LIT>RegisterInfo * RI = STI . getRegisterInfo ( ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; DebugLoc DL = MBBI -> getDebugLoc ( ) ; unsigned FPReg = getFPReg ( STI ) ; unsigned SPReg = getSPReg ( STI ) ; MachineBasicBlock :: iterator LastFrameDestroy = MBBI ; std :: advance ( LastFrameDestroy , - MFI . getCalleeSavedInfo ( ) . size ( ) ) ; uint64_t StackSize = MFI .


<s> <ISA_LIT>Operand * <ISA_LIT>AsmParser :: ParseImmediate ( ) { SMLoc S = Parser . getTok ( ) . getLoc ( ) ; SMLoc E = Parser . getTok ( ) . getEndLoc ( ) ; const MCExpr * EVal ; switch ( getLexer ( ) . getKind ( ) ) { default : return <NUM_LIT> ; case AsmToken ::


<s> if ( ! OutlineFromLinkOnceODRs && F . hasLinkOnceODRLinkage ( ) ) return false ; if ( F . hasSection ( ) ) return


<s> void LLVMInitialize<ISA_LIT>TargetInfo ( ) { RegisterTarget < Triple :: systemz , true > X ( getThe<ISA_LIT>Target ( ) , <STR_LIT> , <STR_LIT> ,


<s> if ( ! ( I -> getType ( ) -> isFloatTy ( ) && V -> getType ( ) -> isDoubleTy ( ) ) ) return false ; unsigned Op = getRegForValue ( V ) ; if ( Op == <NUM_LIT> ) return false ; unsigned Result = createResultReg ( & <STR_LIT> ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , Result ) . addReg ( Op ) ) ; updateValueMap ( I , Result ) ; return true


<s> for ( SUnit :: succ_iterator I = SU -> Succs . begin ( ) , E = SU -> Succs . end ( ) ; I != E ; ++ I ) { unsigned SuccReadyCycle = I -> getSUnit ( ) -> BotReadyCycle ; unsigned MinLatency = I -> getMinLatency ( ) ; Bot . MaxMinLatency = std :: max ( MinLatency , Bot .


<s> static void arc_asm_trampoline_template ( FILE * f ) { asm_fprintf ( f , <STR_LIT> , ARC_TEMP_SCRATCH_REG ) ; asm_fprintf ( f , <STR_LIT> , reg_names [ STATIC_CHAIN_REGNUM ] ) ; asm_fprintf ( f , <STR_LIT> , ARC_TEMP_SCRATCH_REG ) ; assemble_aligned_integer ( UNITS_PER_WORD , const0_rtx ) ; assemble_aligned_integer ( UNITS_PER_WORD


<s> bool isGLC ( ) const { return isImmTy ( ImmTyGLC


<s> bool isLabelImm16 ( ) const { if ( isConstantImm ( ) ) { return isUInt < <NUM_LIT> > ( getConstantImm ( ) ) ; } return isImm ( ) && isAcceptableSymbolRef ( getImm


<s> bool <ISA_LIT>PassConfig :: addInstSelector ( ) { PM -> add ( create<ISA_LIT>ISelDag ( get<ISA_LIT>TargetMachine ( ) ,


<s> for ( int val : Mask ) { if ( val > <NUM_LIT>


<s> if ( Op != TargetOpcode :: COPY && ! MI . isPHI ( ) ) return false ; return getRegBank ( MI . getOperand ( <NUM_LIT> ) . getReg ( )


<s> if ( RegNo >= <NUM_LIT> || RegNo & <NUM_LIT> ) return MCDisassembler :: Fail ; MCRegister Reg = <STR_LIT> + RegNo ; Inst . addOperand ( MCOperand ::


<s> static void EmitRet ( const MCOperand * AmtOp , bool Is64Bit , MCStreamer & Out ) { MCInst POPInst ; POPInst . setOpcode ( Is64Bit ? <STR_LIT> : <STR_LIT> ) ; POPInst . addOperand ( MCOperand :: CreateReg ( Is64Bit ? <STR_LIT> : <STR_LIT> ) ) ; Out . EmitInstruction ( POPInst ) ; if ( AmtOp ) { assert ( ! Is64Bit ) ; MCInst ADDInst ; unsigned ADDReg = <STR_LIT> ; ADDInst . setOpcode (


<s> rtx x , cond ; rval = operands [ <NUM_LIT> ] ; mem = operands [ <NUM_LIT> ] ; oldval = operands [ <NUM_LIT> ] ; newval = operands [ <NUM_LIT> ] ; is_weak = ( operands [ <NUM_LIT> ] != const0_rtx ) ; scratch = operands [ <NUM_LIT> ] ; mode = GET_MODE ( mem ) ; label1 = NULL ; if ( ! is_weak ) { label1 = gen_label_rtx ( ) ; emit_label ( label1 ) ; } label2 = gen_label_rtx ( ) ; aarch64_emit_load_exclusive ( mode , rval , mem , operands [ <NUM_LIT> ] ) ; cond = aarch64_gen_compare_reg ( NE , rval , oldval ) ; x = gen_rtx_NE ( VOIDmode , cond , const0_rtx ) ; x = gen_rtx_IF_THEN_ELSE ( VOIDmode , x , gen_rtx_LABEL_REF ( Pmode , label2 ) , pc_rtx ) ; aarch64_emit_unlikely_jump ( gen_rtx_SET ( VOIDmode , pc_rtx , x ) ) ; aarch64_emit_store_exclusive ( mode , scratch , mem , newval , operands [ <NUM_LIT> ] ) ; if ( ! is_weak ) { x = gen_rtx_NE ( VOIDmode , scratch , const0_rtx ) ; x = gen_rtx_IF_THEN_ELSE ( VOIDmode , x , gen_rtx_LABEL_REF ( Pmode , label1 ) , pc_rtx ) ; aarch64_emit_unlikely_jump ( gen_rtx_SET ( VOIDmode , pc_rtx , x ) ) ; } else { cond = gen_rtx_REG ( CCmode , CC_REGNUM ) ; x = gen_rtx_COMPARE ( CCmode , scratch , const0_rtx ) ; emit_insn ( gen_rtx_SET ( VOIDmode , cond , x


<s> const MCOperand & Op = MI -> getOperand ( OpNo ) ; if ( Op . isImm ( ) ) O << Op . getImm ( ) ; else { assert ( Op . isExpr ( ) && <STR_LIT>


<s> if ( ShrunkMask == <NUM_LIT> ) return false ; if ( ExpandedMask == ~ <NUM_LIT> ) return TLO . CombineTo ( Op , Op . getOperand ( <NUM_LIT> ) ) ; auto IsLegalMask = [ ShrunkMask , ExpandedMask ] ( unsigned Mask ) -> bool { return ( ShrunkMask & Mask ) == ShrunkMask && ( ~ ExpandedMask & Mask ) == <NUM_LIT> ; } ; auto UseMask = [ Mask , Op , VT , & TLO ] ( unsigned NewMask ) -> bool { if ( NewMask == Mask ) return true ; SDLoc DL ( Op ) ; SDValue NewC = TLO . DAG . getConstant ( NewMask , DL , VT ) ; SDValue NewOp = TLO . DAG . getNode ( <STR_LIT> , DL , VT , Op . getOperand ( <NUM_LIT> ) , NewC ) ; return TLO . CombineTo ( Op , NewOp ) ; } ; if ( IsLegalMask ( <NUM_LIT> ) ) return UseMask ( <NUM_LIT> ) ; if ( IsLegalMask ( <NUM_LIT> )


<s> return ( <ISA_LIT>Target >= <ISA_LIT>_SM_1_3 && <ISA_LIT>Target < <ISA_LIT>_LAST_SM ) || ( <ISA_LIT>Target >=


<s> if ( getParser ( ) . parseIdentifier ( Name ) ) return TokError ( <STR_LIT> ) ; MCSymbol * Symbol = getContext ( ) . getOrCreateSymbol ( Name ) ; if ( parseToken ( AsmToken :: Comma , <STR_LIT> ) ) return true ; unsigned LocalMemorySize = <STR_LIT> :: getLocalMemorySize ( & getSTI ( ) ) ; int64_t Size ; SMLoc SizeLoc = getLexer ( ) . getLoc ( ) ; if ( getParser ( ) . parseAbsoluteExpression ( Size ) ) return true ; if ( Size < <NUM_LIT> ) return Error ( SizeLoc , <STR_LIT> ) ; if ( Size > LocalMemorySize ) return Error ( SizeLoc , <STR_LIT> ) ; int64_t Align = <NUM_LIT> ; if ( getLexer ( ) . is ( AsmToken :: Comma ) ) { Lex ( ) ; SMLoc AlignLoc = getLexer ( ) . getLoc ( ) ; if ( getParser ( ) . parseAbsoluteExpression ( Align ) ) return true ; if ( Align < <NUM_LIT> || ! isPowerOf2_64 ( Align ) ) return Error ( AlignLoc , <STR_LIT> ) ; if ( Align >= <NUM_LIT> << <NUM_LIT> ) return Error ( AlignLoc , <STR_LIT> ) ; } if ( parseToken ( AsmToken :: EndOfStatement , <STR_LIT> ) ) return true ; Symbol -> redefineIfPossible


<s> assert ( ( MIb . mayLoad ( ) || MIb . mayStore ( ) ) && <STR_LIT> ) ; if ( MIa . hasUnmodeledSideEffects ( ) || MIb . hasUnmodeledSideEffects ( ) ) return false ; if ( MIa . hasOrderedMemoryRef ( ) || MIb . hasOrderedMemoryRef ( ) ) return false ; if ( isDS ( MIa ) ) { if ( isDS ( MIb ) ) return checkInstOffsetsDoNotOverlap ( MIa , MIb ) ; return ! isFLAT ( MIb ) || isSegmentSpecificFLAT ( MIb ) ; } if ( isMUBUF ( MIa ) || isMTBUF ( MIa ) ) { if ( isMUBUF ( MIb ) || isMTBUF ( MIb ) ) return checkInstOffsetsDoNotOverlap ( MIa , MIb ) ; return ! isFLAT ( MIb ) && ! isSMRD ( MIb ) ; } if ( isSMRD ( MIa ) ) { if ( isSMRD ( MIb ) ) return checkInstOffsetsDoNotOverlap ( MIa , MIb ) ; return ! isFLAT ( MIb ) && ! isMUBUF ( MIa ) && ! isMTBUF ( MIa ) ; } if ( isFLAT ( MIa )


<s> } if ( Value . isAbsolute ( ) ) { Result = evaluateAsInt64 ( Value . getConstant ( ) ) ; return true


<s> bool <ISA_LIT>SinglePathInfo :: isReachable ( const MachineFunction


<s> SDValue N1 = N -> getOperand ( <NUM_LIT> ) ; SDLoc DL ( N ) ; if ( VT . isInteger ( ) && N -> getOpcode ( ) == <STR_LIT> && N0 . getOpcode ( ) == <STR_LIT> && N0 . getOperand ( <NUM_LIT> ) == N1 && N1 . getOpcode ( ) == <STR_LIT> && N1 . getOperand ( <NUM_LIT> ) == N0 . getOperand ( <NUM_LIT> ) ) if ( ConstantSDNode * Y1C = dyn_cast < ConstantSDNode > ( N1 . getOperand (

<NUM_LIT> ) ) ) if ( Y1C -> getAPIntValue ( ) == VT . getSizeInBits ( ) - <NUM_LIT> ) {


<s> if ( isThumb ( ) ) return <STR_LIT> ; if ( hasV4TOps ( ) ) return <STR_LIT> ; return <STR_LIT>


<s> if ( ! Inst . getOperand ( <NUM_LIT> ) . isImm ( ) || ! isImmSExti64i8Value ( Inst .

getOperand ( <NUM_LIT> ) . getImm ( ) ) ) return false ;


<s> return SelectShiftedRegister ( N , true ,


<s> unsigned CondMovOpc ; const TargetRegisterClass * RC ; if ( VT . isInteger ( ) && ! VT . isVector ( ) && VT . getSizeInBits ( ) <= <NUM_LIT> ) { CondMovOpc = <STR_LIT> ; RC = & <STR_LIT> ; } else if ( VT == <STR_LIT> ) { CondMovOpc = <STR_LIT> ; RC = & <STR_LIT> ; } else if ( VT == <STR_LIT> ) { CondMovOpc = <STR_LIT> ; RC = & <STR_LIT> ; } else return false ; const SelectInst * SI = cast < SelectInst > ( I ) ; const Value * Cond = SI -> getCondition ( ) ; unsigned Src1Reg = getRegForValue ( SI -> getTrueValue ( ) ) ; unsigned Src2Reg = getRegForValue ( SI -> getFalseValue (


<s> static bool rl78_return_in_memory ( const_tree type , const_tree fntype ATTRIBUTE_UNUSED ) { const HOST_WIDE_INT size = int_size_in_bytes


<s> bool requiresRegisterScavenging ( const MachineFunction & MF ) const override { return


<s> const TargetRegisterClass * getMatchingSuperRegClass ( const TargetRegisterClass * A , const TargetRegisterClass * B , unsigned Idx ) const { return


<s> void <ISA_LIT>DbgInfo :: EmitAuxEntry ( const std :: string VarName , int Aux [ ] , int Num , std


<s> pdp11_gen_int_label ( buf , <STR_LIT> , value ) ; if ( ! TARGET_UNIX_ASM ) fprintf ( file , <STR_LIT> ) ; fprintf ( file , <STR_LIT> ,


<s> return ( uint32x4_t ) __builtin_aarch64_umaxpv4si ( ( int32x4_t ) a , ( int32x4_t )


<s> ArgInfo . KernargSegmentPtr = ArgDescriptor :: createRegister ( TRI . getMatchingSuperReg ( getNextUserSGPR (


<s> MF -> insert ( ++ MBB . getIterator ( ) , LoadCmpBB ) ; MF -> insert ( ++ LoadCmpBB -> getIterator ( ) , StoreBB ) ; MF -> insert ( ++ StoreBB -> getIterator ( ) , DoneBB ) ; LoadCmpBB -> addLiveIn ( Addr . getReg ( ) ) ; LoadCmpBB -> addLiveIn ( Dest . getReg ( ) ) ; LoadCmpBB -> addLiveIn ( Desired . getReg ( ) ) ; addPostLoopLiveIns ( LoadCmpBB , LiveRegs ) ; BuildMI ( LoadCmpBB , DL , TII -> get ( LdarOp ) , Dest . getReg ( ) ) . addReg ( Addr . getReg ( ) ) ; BuildMI ( LoadCmpBB , DL , TII -> get ( CmpOp ) , ZeroReg ) . addReg ( Dest . getReg ( ) , getKillRegState ( Dest . isDead ( ) ) ) . addOperand ( Desired ) . addImm ( ExtendImm ) ; BuildMI ( LoadCmpBB , DL , TII -> get ( <STR_LIT> ) ) . addImm ( <STR_LIT> ) . addMBB ( DoneBB ) . addReg ( <STR_LIT> , RegState :: Implicit | RegState :: Kill ) ; LoadCmpBB -> addSuccessor ( DoneBB ) ; LoadCmpBB -> addSuccessor ( StoreBB ) ; StoreBB -> addLiveIn ( Addr . getReg ( ) ) ; StoreBB -> addLiveIn ( New . getReg ( ) ) ; addPostLoopLiveIns ( StoreBB , LiveRegs ) ; BuildMI ( StoreBB , DL , TII -> get ( StlrOp ) ,

StatusReg ) . addOperand ( New ) . addOperand ( Addr ) ;


<s> static DecodeStatus DecodeFGR32RegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t Address , const void * Decoder ) { if ( RegNo > <NUM_LIT> ) return MCDisassembler :: Fail ; unsigned Reg = getReg ( Decoder , <STR_LIT> , RegNo ) ; Inst . addOperand ( MCOperand :: CreateReg ( Reg ) ) ; return MCDisassembler ::


<s> F -> setVisibility ( GlobalValue :: HiddenVisibility ) ; F -> setComdat ( M . getOrInsertComdat ( Name ) ) ; AttrBuilder B ; B . addAttribute ( llvm :: Attribute :: NoUnwind ) ; B . addAttribute ( llvm :: Attribute :: Naked ) ; F -> addAttributes ( llvm :: AttributeList :: FunctionIndex , B ) ; BasicBlock * Entry = BasicBlock :: Create ( Ctx , <STR_LIT> , F ) ; IRBuilder < > Builder ( Entry ) ; Builder . CreateRetVoid ( ) ; MachineFunction & MF = MMI -> getOrCreateMachineFunction ( * F ) ; MachineBasicBlock * EntryMBB = MF


<s> void <ISA_LIT>ATTAsmPrinter :: printPICLabel ( const MCInst * MI , unsigned Op ) { llvm_unreachable ( <STR_LIT>


<s> static bool aarch64_could_trap_p ( unsigned int f , machine_mode mode ) { unsigned int flags = aarch64_call_properties ( f , mode ) ; if ( flags & FLAG_RAISE_FP_EXCEPTIONS ) return


<s> std :: map < unsigned , bool > VecInstElemTable ; SmallVector < MachineInstr * , <NUM_LIT> > RemoveMIs ; for ( MachineBasicBlock & MBB : MF ) { for ( MachineBasicBlock :: iterator MII = MBB . begin ( ) , MIE = MBB . end ( ) ; MII != MIE ; ) { MachineInstr & MI = * MII ; if ( optimizeVectElement ( MI , & VecInstElemTable ) ) { RemoveMIs . push_back ( & MI ) ; Changed = true ; } ++ MII ; } } for ( MachineInstr * MI : RemoveMIs ) MI -> eraseFromParent


<s> cost [ vect_prologue ] = cost [ vect_body ] = cost [ vect_epilogue ] = <NUM_LIT> ; return cost


<s> if ( ! ST -> hasVscnt ( ) ) ScoreBrackets -> updateByEvent ( TII , TRI , MRI , VMEM_ACCESS , Inst ) ; else if ( ( Inst . mayLoad ( ) && <STR_LIT> ( Inst . getOpcode ( ) ) == - <NUM_LIT> ) || ( TII -> isMIMG ( Inst ) && ! Inst . mayLoad ( ) && ! Inst . mayStore ( ) ) ) ScoreBrackets -> updateByEvent ( TII , TRI , MRI , VMEM_READ_ACCESS , Inst ) ; else if ( Inst . mayStore ( ) ) ScoreBrackets -> updateByEvent ( TII , TRI , MRI , VMEM_WRITE_ACCESS , Inst ) ; if ( ST -> vmemWriteNeedsExpWaitcnt ( ) && ( Inst . mayStore ( ) || <STR_LIT> ( Inst . getOpcode ( ) ) != - <NUM_LIT> ) ) { ScoreBrackets -> updateByEvent ( TII , TRI , MRI , VMW_GPR_LOCK , Inst ) ; } } else if ( TII -> isSMRD ( Inst ) ) { ScoreBrackets -> updateByEvent ( TII , TRI , MRI , SMEM_ACCESS , Inst ) ; } else if ( Inst . isCall ( ) ) { if ( callWaitsOnFunctionReturn ( Inst ) ) { ScoreBrackets -> applyWaitcnt ( <STR_LIT> :: allZero ( ST -> hasVscnt ( ) ) ) ; } else { ScoreBrackets -> applyWaitcnt ( <STR_LIT> ( ) ) ; } } else { switch ( Inst . getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT>


<s> SDValue <ISA_LIT>TargetLowering :: EmitTailCallLoadRetAddr ( SelectionDAG & DAG , SDValue & OutRetAddr , SDValue Chain , bool IsTailCall , bool Is64Bit , int FPDiff , DebugLoc dl ) const { EVT VT = getPointerTy ( ) ; OutRetAddr = getReturnAddressFrameIndex ( DAG ) ; OutRetAddr = DAG . getLoad ( VT , dl , Chain , OutRetAddr , MachinePointerInfo (


<s> if ( auto Const = dyn_cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) ) return Const -> getZExtValue ( ) == <NUM_LIT> ; return


<s> const std :: vector < MachineDomTreeNode * > & Children = Node -> getChildren ( ) ; OpenChildren [ Node ] = Children . size ( ) ; for ( MachineDomTreeNode * Child : Children ) WorkList . push_back ( Child ) ; } while ( ! WorkList . empty (


<s> break ; case CODE_FOR_doloop_end_internal : insn_extract ( insn ) ; loop = & loops [ INTVAL ( recog_data . operand [ <NUM_LIT> ] ) ] ; end = ( struct mep_doloop_end * ) alloca ( sizeof ( struct mep_doloop_end ) ) ; end -> insn = insn ; end -> fallthrough = next_real_insn ( insn ) ; end -> counter = recog_data . operand [ <NUM_LIT> ] ; end -> label = recog_data . operand [ <NUM_LIT> ] ; end -> scratch = recog_data . operand [ <NUM_LIT> ] ; if ( loop -> end != <NUM_LIT> && simplejump_p ( end -> fallthrough ) ) { end -> next = loop -> end -> next ; loop -> end -> next = end ; } else { end -> next = loop -> end ; loop -> end = end ; } break ; } for ( loop = loops ; loop < loops + cfun -> machine -> doloop_tags ; loop ++ ) if ( mep_repeat_loop_p ( loop ) ) { rtx_code_label * repeat_label ; rtx label_ref ; repeat_label = gen_label_rtx ( ) ; label_ref = gen_rtx_LABEL_REF ( VOIDmode , repeat_label ) ; emit_insn_before ( gen_repeat ( loop -> begin -> counter , label_ref ) , loop -> begin -> insn ) ; delete_insn ( loop -> begin -> insn ) ; mep_insert_repeat_label_last ( loop -> end -> insn , repeat_label , false , loop -> end -> next != <NUM_LIT> ) ; emit_insn_before ( gen_repeat_end ( ) , loop -> end -> insn ) ; delete_insn ( loop -> end -> insn ) ; for ( end = loop -> end -> next ; end != <NUM_LIT> ; end = end -> next ) { emit_jump_insn_before ( gen_jump ( repeat_label ) , end -> insn ) ; delete_insn ( end -> insn ) ; delete_insn ( end ->


<s> if ( CC == CallingConv :: <ISA_LIT>_SVE_VectorCall ) return CSR_<ISA_LIT>_SVE_AAPCS_RegMask ; if ( MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getTargetLowering ( ) -> supportSwiftError ( ) && MF . getFunction ( ) -> getAttributes ( ) . hasAttrSomewhere (

Attribute :: SwiftError ) ) return CSR_<ISA_LIT>_AAPCS_SwiftError_RegMask ;


<s> for ( Loop * L : LI ) for ( Loop * LIt : depth_first ( L ) ) MadeChange |= runOnLoop ( * LIt ) ; return


<s> OutStreamer . EmitAssemblerFlag ( MCAF_SubsectionsViaSymbols ) ; } if ( Subtarget -> isTargetKnownWindowsMSVC ( ) && MMI -> usesVAFloatArgument ( ) ) { StringRef SymbolName = Subtarget -> is64Bit ( ) ? <STR_LIT> : <STR_LIT> ; MCSymbol * S = MMI -> getContext ( ) . GetOrCreateSymbol ( SymbolName ) ; OutStreamer . EmitSymbolAttribute ( S , MCSA_Global ) ; } if ( Subtarget -> isTargetCOFF ( ) ) { std :: vector < const MCSymbol * > DLLExportedFns , DLLExportedGlobals ; for ( const auto & Function : M ) if ( Function . hasDLLExportStorageClass ( ) ) DLLExportedFns . push_back ( getSymbol ( & Function ) ) ; for ( const auto & Global : M . globals ( ) ) if ( Global . hasDLLExportStorageClass ( ) ) DLLExportedGlobals . push_back ( getSymbol ( & Global ) ) ; for ( const auto & Alias : M . aliases ( ) ) { const GlobalValue * GV = & Alias ; if ( ! GV -> hasDLLExportStorageClass ( ) ) continue ; while ( const GlobalAlias * A = dyn_cast < GlobalAlias > ( GV ) ) GV = A -> getAliasedGlobal ( ) ; if ( isa < Function > ( GV ) ) DLLExportedFns . push_back ( getSymbol ( & Alias ) ) ; else if ( isa < GlobalVariable > ( GV ) ) DLLExportedGlobals . push_back ( getSymbol ( & Alias ) ) ; } if ( ! DLLExportedGlobals . empty ( ) || ! DLLExportedFns . empty ( ) ) { const TargetLoweringObjectFileCOFF & TLOFCOFF = static_cast < const TargetLoweringObjectFileCOFF & > ( getObjFileLowering ( ) ) ; OutStreamer . SwitchSection ( TLOFCOFF . getDrectveSection ( ) ) ; for ( auto & Symbol : DLLExportedGlobals ) GenerateExportDirective (


<s> void SparcFrameLowering :: processFunctionBeforeCalleeSavedScan ( MachineFunction & MF , RegScavenger * RS ) const { if ( ! DisableLeafProc && isLeafProc ( MF ) ) { SparcMachineFunctionInfo * MFI = MF . getInfo < SparcMachineFunctionInfo > ( ) ; MFI -> setLeafProc ( true


<s> MachineFunction & MF = DAG . getMachineFunction ( ) ; const Function * Func = MF . getFunction ( ) ; const std :: string FuncName = Func -> getName ( ) ; int FI = MF . getFrameInfo ( ) -> CreateStackObject ( <NUM_LIT> , <NUM_LIT> , false ) ; const char * tmpName = ESNames :: createESName ( PAN :: getTempdataLabel ( FuncName ) ) ; SDValue ES = DAG . getTargetExternalSymbol ( tmpName , <STR_LIT> ) ; SDValue Store = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getEntryNode ( ) , Op , ES , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) , DAG . getConstant ( GetTmpOffsetForFI ( FI , <NUM_LIT> ) , <STR_LIT> ) ) ; SDVTList Tys = DAG . getVTList


<s> unsigned getDarwinDirective ( ) const


<s> AARCH64_FOR_SVPATTERN ( CASE ) case AARCH64_NUM_SVPATTERNS : break ; } gcc_unreachable ( )


<s> if ( isUndef ( Vec32 ) ) return DAG . getUNDEF ( <STR_LIT> ) ; return getNode ( <STR_LIT> , dl , <STR_LIT> , { Vec32


<s> int getDebuggerWorkGroupIDStackObjectIndex ( unsigned Dim ) const { assert ( Dim < <NUM_LIT> ) ; return DebuggerWorkGroupIDStackObjectIndices [


<s> LaneA = DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ; ViaVecTy = <STR_LIT> ; } else LaneA = LaneB ; SDValue Ops [ <NUM_LIT> ] = { LaneA , LaneB , LaneA , LaneB , LaneA , LaneB , LaneA , LaneB , LaneA , LaneB , LaneA , LaneB , LaneA , LaneB , LaneA , LaneB } ; SDValue Result = DAG . getNode ( <STR_LIT> , DL , ViaVecTy , Ops , ViaVecTy . getVectorNumElements ( ) ) ; if ( ViaVecTy != ResVecTy ) Result = DAG . getNode ( <STR_LIT> , DL , ResVecTy , Result ) ; return


<s> int64_t Offset ; if ( parseRegisterInRange ( Reg , <STR_LIT> , <STR_LIT> , <STR_LIT> ) || parseComma ( ) || parseImmExpr ( Offset ) ) return true ; getTargetStreamer ( ) . EmitARM64WinCFISaveReg ( Reg , Offset ) ; return


<s> void addu6_0ImmOperands ( MCInst & Inst , unsigned N


<s> if ( TARGET_HARD_FLOAT ) abi = <STR_LIT> ; else if ( TARGET_SOFT_FLOAT ) abi = <STR_LIT> ; else abi = <STR_LIT>


<s> BB -> setAlignment ( MaxAlign ) ; Align FuncAlign = MaxAlign ; if ( MaxAlign == <NUM_LIT> ) FuncAlign = Align ( <NUM_LIT> ) ; MF -> ensureAlignment ( FuncAlign ) ; SmallVector < MachineBasicBlock :: iterator , <NUM_LIT> > InsPoint ( MaxLogAlign + <NUM_LIT> , BB -> end ( ) ) ; const std :: vector < MachineConstantPoolEntry > & CPs = MCP -> getConstants ( ) ; const DataLayout & TD = MF -> getDataLayout ( ) ; for ( unsigned i = <NUM_LIT> , e = CPs . size ( ) ; i != e ; ++ i ) { unsigned Size = CPs [ i ] . getSizeInBytes ( TD ) ; Align Alignment = CPs [ i ] . getAlign ( ) ; assert ( isAligned ( Alignment , Size ) && <STR_LIT> ) ; unsigned LogAlign = Log2 ( Alignment


<s> return ( __m512i ) __builtin_ia32_pmovzxbq512_mask ( ( __v16qi ) __A , ( __v8di )

_mm512_undefined_epi32 ( ) , ( __mmask8 ) - <NUM_LIT> ) ;


<s> unsigned Alignment = <NUM_LIT> ; if ( LSBaseSDNode * LSN = dyn_cast < LSBaseSDNode > ( Parent ) ) { unsigned LSNAlign = LSN -> getAlignment ( ) ; unsigned MemSize = LSN -> getMemoryVT ( ) .


<s> void printymmwordmem ( const MCInst * MI , unsigned OpNo , raw_ostream & O ) { O << <STR_LIT> ; printMemReference ( MI , OpNo


<s> bool hasXMMInt ( ) const { return hasSSE2 ( ) ||


<s> if ( isWaterInRange ( UserOffset , WaterBB , U , Growth ) && ( WaterBB -> getNumber ( ) < U . HighWaterMark -> getNumber ( ) || NewWaterList . count ( WaterBB ) ) && Growth < BestGrowth ) { BestGrowth = Growth ; WaterIter = IP ; DEBUG ( dbgs ( ) << <STR_LIT> << WaterBB -> getNumber ( ) << <STR_LIT> << Growth << '\n' ) ; if ( BestGrowth == <NUM_LIT> ) return true ; } if ( IP == B ) break ; } return BestGrowth !=


<s> static bool isRIPRelative ( const MCInst & MI , const MCInstrInfo & MCII ) { unsigned Opcode = MI . getOpcode ( ) ; const MCInstrDesc & Desc = MCII . get ( Opcode ) ; uint64_t TSFlags = Desc . TSFlags ; unsigned CurOp = <STR_LIT> ( Desc ) ; int MemoryOperand = <STR_LIT> ( TSFlags ) ; if ( MemoryOperand < <NUM_LIT> ) return false ; unsigned BaseRegNum = MemoryOperand +


<s> } else if ( GET_CODE ( addr ) == PRE_MODIFY ) { rtx reg = XEXP ( addr , <NUM_LIT> ) ; rtx expr = XEXP ( addr , <NUM_LIT> ) ; gcc_assert ( REG_P ( reg ) ) ; gcc_assert ( GET_CODE ( expr ) == PLUS ) ; emit_insn ( gen_add3_insn ( reg , XEXP ( expr , <NUM_LIT> ) , XEXP ( expr , <NUM_LIT> ) ) ) ; addr =


<s> if ( ! Dis -> tryAddingSymbolicOperand ( Inst , imm * <NUM_LIT> , Addr , true , <NUM_LIT> , <NUM_LIT> ) ) Inst . addOperand ( MCOperand :: createImm ( imm ) ) ; return Success


<s> struct rtx_def * m88k_builtin_saveregs ( ) { rtx addr ; tree fntype = TREE_TYPE ( current_function_decl ) ; int argadj = ( ( ! ( TYPE_ARG_TYPES ( fntype ) != <NUM_LIT> && ( TREE_VALUE ( tree_last ( TYPE_ARG_TYPES ( fntype ) ) ) != void_type_node ) ) ) ? - UNITS_PER_WORD : <NUM_LIT> ) + UNITS_PER_WORD - <NUM_LIT> ; int fixed ; variable_args_p = <NUM_LIT> ; fixed = <NUM_LIT> ; if ( GET_CODE ( current_function_arg_offset_rtx ) == CONST_INT ) fixed = ( ( INTVAL ( current_function_arg_offset_rtx ) + argadj ) / UNITS_PER_WORD ) ; addr = assign_stack_local ( BLKmode , <NUM_LIT> * UNITS_PER_WORD , - <NUM_LIT> ) ; set_mem_alias_set ( addr , get_varargs_alias_set ( ) ) ; RTX_UNCHANGING_P ( addr ) = <NUM_LIT> ; RTX_UNCHANGING_P ( XEXP ( addr , <NUM_LIT> ) ) = <NUM_LIT> ; if ( fixed < <NUM_LIT> ) move_block_from_reg ( <NUM_LIT> + fixed , adjust_address ( addr , Pmode , fixed * UNITS_PER_WORD ) , <NUM_LIT> - fixed ,

UNITS_PER_WORD * ( <NUM_LIT> - fixed ) ) ;


<s> const <ISA_LIT>TargetLowering * getTargetLowering ( ) const override { return getSubtargetImpl ( ) -> getTargetLowering


<s> return gen_rtx_SET ( VOIDmode , arg , gen_rtx_MEM ( word_mode

, gen_rtx_POST_INC ( Pmode , stack_pointer_rtx ) ) ) ;


<s> void <ISA_LIT>TargetStreamer :: EmitKernelCodeObjectMetadata ( const Function & Func , const amd_kernel_code_t & KernelCode ) { CodeObjectMetadataStreamer . emitKernel ( Func ,


<s> if ( Size != MemSizeInBits ) return Size <= <NUM_LIT> && Ty . isVector ( ) ; if ( loadStoreBitcastWorkaround ( Ty ) && isRegisterType ( Ty ) ) return true ; return Ty . isVector ( ) && ( ! MemTy . isVector ( ) || MemTy == Ty ) &&

( Size <= <NUM_LIT> || isRegisterSize ( Size ) ) && ! isRegisterVectorElementType ( Ty . getElementType ( ) ) ;


<s> return ( __m512i ) __builtin_ia32_pbroadcastb512_gpr_mask ( __A , (


<s> <ISA_LIT>MCAsmInfo :: <ISA_LIT>MCAsmInfo ( const Triple & TT ) { Data16bitsDirective = <STR_LIT> ; Data32bitsDirective = <STR_LIT> ; Data64bitsDirective = nullptr ; ZeroDirective = <STR_LIT> ; CommentString = <STR_LIT> ; LCOMMDirectiveAlignmentType = LCOMM :: ByteAlignment ; InlineAsmStart = <STR_LIT> ; InlineAsmEnd = <STR_LIT> ; ZeroDirective = <STR_LIT> ; AscizDirective = <STR_LIT> ; SupportsDebugInformation = true


<s> case <STR_LIT> : return LowerMEMBARRIER ( Op , DAG , Subtarget ) ; case <STR_LIT> : return LowerPREFETCH ( Op , DAG , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : return LowerINT_TO_FP ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerFP_TO_INT ( Op , DAG ) ; case <STR_LIT> : return LowerFCOPYSIGN ( Op , DAG ) ; case <STR_LIT> : return LowerRETURNADDR ( Op , DAG ) ; case <STR_LIT> : return LowerFRAMEADDR ( Op , DAG ) ; case <STR_LIT> : return LowerGLOBAL_OFFSET_TABLE ( Op , DAG ) ; case <STR_LIT> : return LowerEH_SJLJ_SETJMP ( Op , DAG ) ; case <STR_LIT> : return LowerEH_SJLJ_LONGJMP ( Op , DAG ) ; case <STR_LIT> : return LowerEH_SJLJ_DISPATCHSETUP ( Op , DAG ) ; case <STR_LIT> : return LowerINTRINSIC_WO_CHAIN ( Op , DAG , Subtarget ) ; case <STR_LIT> : return ExpandBITCAST ( Op . getNode ( ) , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerShift ( Op . getNode ( ) , DAG , Subtarget ) ; case <STR_LIT> : return LowerShiftLeftParts ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerShiftRightParts ( Op , DAG ) ; case <STR_LIT> : return LowerCTTZ ( Op . getNode ( ) , DAG , Subtarget ) ; case <STR_LIT> : return LowerVSETCC ( Op , DAG ) ; case <STR_LIT> : return LowerBUILD_VECTOR ( Op , DAG , Subtarget ) ; case <STR_LIT> : return LowerVECTOR_SHUFFLE ( Op , DAG ) ; case <STR_LIT> : return LowerEXTRACT_VECTOR_ELT (


<s> if ( ! B_SD -> getFragment ( ) ) report_fatal_error ( <STR_LIT> + B -> getSymbol ( ) . getName ( ) + <STR_LIT> , false ) ; Type = A_SD -> isExternal ( ) ? ( unsigned ) MachO :: GENERIC_RELOC_SECTDIFF : ( unsigned ) MachO :: GENERIC_RELOC_LOCAL_SECTDIFF ; Value2 = Writer -> getSymbolAddress ( B_SD , Layout ) ; FixedValue -= Writer -> getSectionAddress ( B_SD -> getFragment ( ) -> getParent ( ) ) ; } if ( Type == MachO :: GENERIC_RELOC_SECTDIFF || Type == MachO :: GENERIC_RELOC_LOCAL_SECTDIFF ) { if ( FixupOffset > <NUM_LIT> ) { char Buffer [ <NUM_LIT> ] ; format ( <STR_LIT> , FixupOffset ) . print ( Buffer , sizeof ( Buffer ) ) ; Asm . getContext ( ) . FatalError ( Fixup . getLoc ( ) , Twine ( <STR_LIT> <STR_LIT> ) + Buffer + <STR_LIT> <STR_LIT> ) ; llvm_unreachable ( <STR_LIT> ) ; } MachO :: any_relocation_info MRE ; MRE . r_word0 = ( ( <NUM_LIT> << <NUM_LIT> ) | ( MachO :: GENERIC_RELOC_PAIR << <NUM_LIT> ) | ( Log2Size << <NUM_LIT> ) | ( IsPCRel << <NUM_LIT> ) | MachO :: R_SCATTERED ) ; MRE . r_word1 = Value2 ; Writer -> addRelocation ( nullptr , Fragment -> getParent ( ) , MRE ) ; } else { if ( FixupOffset > <NUM_LIT> ) { FixedValue = OriginalFixedValue ; return false ; } } MachO :: any_relocation_info MRE ; MRE . r_word0 = ( ( FixupOffset << <NUM_LIT> ) | ( Type << <NUM_LIT> ) | ( Log2Size << <NUM_LIT> ) | ( IsPCRel << <NUM_LIT> ) | MachO :: R_SCATTERED ) ; MRE . r_word1 = Value


<s> } SDValue Lo = extract128BitVector ( In , <NUM_LIT> , DAG , DL ) ; SDValue Hi = extract128BitVector ( In , <NUM_LIT> , DAG , DL ) ; Lo = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Lo ) ; Hi = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Hi ) ; return DAG . getNode ( <STR_LIT> , DL , VT , Lo , Hi ) ; } MVT EltVT = Subtarget . hasVLX ( ) ? <STR_LIT> : <STR_LIT> ( <NUM_LIT> / NumElts ) ; MVT ExtVT = <STR_LIT> ( EltVT , NumElts ) ; In = DAG . getNode ( <STR_LIT> , DL , ExtVT , In ) ; InVT = ExtVT ; ShiftInx = InVT . getScalarSizeInBits ( ) - <NUM_LIT> ; } if ( DAG . ComputeNumSignBits ( In ) < InVT . getScalarSizeInBits ( ) ) { In = DAG . getNode ( <STR_LIT> , DL , InVT , In

, DAG . getConstant ( ShiftInx , DL , InVT ) ) ;


<s> if ( canFlattenType ( VT ) ) { if ( typeDefs . find ( VT ) == typeDefs . end ( ) ) typeDefs [ VT ] = nullptr ; typeValues [ VT ] . push_back ( V


<s> MVT RegisterVT ; unsigned NumRegisters ; std :: tie ( RegisterVT , NumRegisters ) = handleMaskRegisterForCallingConv ( NumElts , CC , Subtarget ) ; if ( RegisterVT != <STR_LIT> ) return RegisterVT ; } if ( VT == <STR_LIT> && Subtarget . hasFP16 ( ) ) return <STR_LIT> ; if ( ( VT == <STR_LIT> || VT == <STR_LIT> ) && ! Subtarget . is64Bit ( ) && ! Subtarget . hasX87 ( ) ) return <STR_LIT> ; return TargetLowering :: getRegisterTypeForCallingConv ( Context


<s> if ( cfun -> machine -> naked_p ) return false ; if ( cfun -> machine -> interrupt_handler_p ) return false ; return true


<s> ReadOnlySection = new <ISA_LIT>Section ( MCSection :: SV_ELF , SectionKind :: getReadOnly ( ) ) ; StaticCtorSection = new <ISA_LIT>Section ( MCSection :: SV_ELF , SectionKind :: getMetadata ( ) ) ; StaticDtorSection = new <ISA_LIT>Section ( MCSection :: SV_ELF , SectionKind :: getMetadata ( ) ) ; LSDASection = new <ISA_LIT>Section ( MCSection :: SV_ELF , SectionKind :: getMetadata ( ) ) ; EHFrameSection = new <ISA_LIT>Section ( MCSection :: SV_ELF , SectionKind :: getMetadata ( ) ) ; DwarfAbbrevSection = new <ISA_LIT>Section ( MCSection :: SV_ELF , SectionKind :: getMetadata ( ) ) ; DwarfInfoSection = new <ISA_LIT>Section ( MCSection :: SV_ELF , SectionKind :: getMetadata ( ) ) ; DwarfLineSection = new <ISA_LIT>Section ( MCSection :: SV_ELF , SectionKind :: getMetadata ( ) ) ; DwarfFrameSection = new <ISA_LIT>Section ( MCSection :: SV_ELF , SectionKind :: getMetadata ( ) ) ; DwarfPubTypesSection = new <ISA_LIT>Section ( MCSection :: SV_ELF , SectionKind :: getMetadata ( ) ) ; DwarfDebugInlineSection = new <ISA_LIT>Section ( MCSection :: SV_ELF , SectionKind :: getMetadata ( ) ) ; DwarfStrSection = new <ISA_LIT>Section ( MCSection :: SV_ELF , SectionKind :: getMetadata ( ) ) ; DwarfLocSection = new <ISA_LIT>Section ( MCSection :: SV_ELF ,


<s> unsigned rd = ( insn >> <NUM_LIT> ) & <NUM_LIT> ; if ( DecodeIntRegRegisterClass ( MI , rd , Address , Decoder ) == MCDisassembler :: Fail ) return MCDisassembler :: Fail ; unsigned rs = ( insn >> <NUM_LIT> ) & <NUM_LIT> ; if ( DecodeIntRegRegisterClass ( MI , rs , Address , Decoder ) == MCDisassembler :: Fail ) return MCDisassembler :: Fail ; signed int offset = (


<s> static __inline__ float __fabsf ( float x ) { float r ; __asm__ ( <STR_LIT> : <STR_LIT> ( r ) : <STR_LIT> (


<s> StringRef <STR_LIT> ( const Triple & TT , StringRef CPU ) { if ( CPU . empty ( ) || CPU


<s> const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; for ( int I = <NUM_LIT> , E = MFI . getObjectIndexEnd ( ) ; I != E ; ++ I ) if ( MFI . getStackID ( I ) == TargetStackID :: ScalableVector ) return true ; return false


<s> SDNode * R = CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , C ) ; SDNode * T = CurDAG -> getMachineNode ( <STR_LIT> , dl , ResTy , N -> getOperand ( <NUM_LIT> ) , SDValue (


<s> InstructionCost <ISA_LIT>TTIImpl :: getMemoryOpCost ( unsigned Opcode , Type * Src , MaybeAlign Alignment , unsigned AddressSpace , TTI :: TargetCostKind CostKind , const Instruction * I ) { if ( CostKind != TTI :: TCK_RecipThroughput ) { if ( auto * SI = dyn_cast_or_null < StoreInst > ( I ) ) { if ( auto * GEP = dyn_cast < GetElementPtrInst > ( SI -> getPointerOperand ( ) ) ) { if ( ! all_of ( GEP -> indices ( ) , [ ] ( Value * V ) { return isa < Constant > ( V ) ; } ) ) return TTI :: TCC_Basic * <NUM_LIT> ; } } return TTI :: TCC_Basic ; } assert ( ( Opcode == Instruction :: Load || Opcode == Instruction :: Store ) && <STR_LIT> ) ; if ( TLI -> getValueType ( DL , Src , true ) == <STR_LIT> ) return BaseT :: getMemoryOpCost ( Opcode , Src , Alignment , AddressSpace , CostKind ) ; if ( auto * VTy = dyn_cast < FixedVectorType > ( Src ) ) { const unsigned NumElem = VTy -> getNumElements ( ) ; if ( ! isPowerOf2_32 ( NumElem ) ) { InstructionCost Cost = <NUM_LIT> ; unsigned NumElemDone = <NUM_LIT> ; for ( unsigned NumElemLeft = NumElem , Factor ; Factor = PowerOf2Floor ( NumElemLeft ) , NumElemLeft > <NUM_LIT> ; NumElemLeft -= Factor ) { Type * SubTy = FixedVectorType :: get ( VTy -> getScalarType ( ) , Factor ) ; unsigned SubTyBytes = SubTy -> getPrimitiveSizeInBits ( ) / <NUM_LIT> ; Cost += getMemoryOpCost ( Opcode , SubTy , Alignment , AddressSpace , CostKind ) ; std :: pair < InstructionCost , MVT > LST = TLI -> getTypeLegalizationCost ( DL , SubTy ) ; if ( ! LST . second . isVector ( ) ) { APInt DemandedElts = APInt :: getBitsSet ( NumElem , NumElemDone , NumElemDone + Factor ) ; Cost += getScalarizationOverhead ( VTy , DemandedElts , Opcode == Instruction :: Load , Opcode == Instruction :: Store ) ; } NumElemDone += Factor ; Alignment = commonAlignment ( Alignment . valueOrOne ( ) , SubTyBytes ) ; } assert ( NumElemDone == NumElem && <STR_LIT> ) ; return Cost ; } } std :: pair < InstructionCost , MVT > LT = TLI -> getTypeLegalizationCost ( DL , Src ) ; InstructionCost Cost = LT . first * <NUM_LIT> ; if ( LT . second . getStoreSize ( ) == <NUM_LIT> && ST -> isUnalignedMem32Slow ( ) ) Cost *= <NUM_LIT> ; return Cost


<s> switch ( Inst . getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : return expandLoadImm ( Inst , IDLoc , Instructions ) ; case <STR_LIT> : return expandLoadAddressImm ( Inst , IDLoc , Instructions ) ; case <STR_LIT> : return expandLoadAddressReg ( Inst , IDLoc


<s> return D ( <STR_LIT> , <STR_LIT> , R ( b )


<s> cum -> arg_words += ( ( int_size_in_bytes ( type ) + UNITS_PER_WORD - <NUM_LIT> ) / UNITS_PER_WORD ) ; break ; case E_SFmode : cum -> arg_words ++ ; if ( ! cum -> gp_reg_found && cum -> arg_number <= <NUM_LIT> ) cum -> fp_code += <NUM_LIT> << ( ( cum -> arg_number - <NUM_LIT> ) * <NUM_LIT> ) ; break ; case E_DFmode : cum -> arg_words += <NUM_LIT> ; if ( ! cum -> gp_reg_found && cum -> arg_number <= <NUM_LIT> ) cum -> fp_code += <NUM_LIT> << ( ( cum -> arg_number - <NUM_LIT> ) * <NUM_LIT> ) ; break ; case E_DImode


<s> std :: string err ; raw_fd_ostream f ( s . str ( ) . c_str ( ) , err ) ; WriteGraph ( f , * this ) ; f . close


<s> static SDValue getAllOnesMask ( MVT VecVT , SDValue VL ,


<s> switch ( In ) { case MCDisassembler :: Success : return true ; case MCDisassembler :: SoftFail : Out = In ; return true ; case MCDisassembler :: Fail : Out =


<s> if ( ! LocalSData && GVA -> hasLocalLinkage ( ) ) return false ; if ( ! ExternSData && ( ( GVA -> hasExternalLinkage ( ) && GVA -> isDeclaration ( ) ) || GVA ->


<s> unsigned rr = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) + <NUM_LIT> ; if ( DecodeGPR8RegisterClass ( Inst , rd , Address , Decoder ) == MCDisassembler :: Fail ) return MCDisassembler :: Fail ; if ( DecodeGPR8RegisterClass ( Inst , rr , Address , Decoder )


<s> rtx d = const_double_from_real_value ( dconst , mode ) ; reg = force_reg ( mode , d ) ; } else if ( mode == V4SFmode ) { rtx d = const_double_from_real_value ( dconst , SFmode ) ; rtvec v = gen_rtvec ( <NUM_LIT> , d , d , d , d ) ; reg = gen_reg_rtx ( mode ) ; rs6000_expand_vector_init ( reg , gen_rtx_PARALLEL ( mode , v ) ) ; } else if ( mode == V2DFmode ) { rtx d = const_double_from_real_value ( dconst , DFmode ) ; rtvec v = gen_rtvec ( <NUM_LIT>


<s> MachineBasicBlock * DestBB = getDestBlock ( MI ) ; MachineBasicBlock * MBB = MI -> getParent ( ) ; MachineInstr * BMI = & MBB -> back ( ) ; bool NeedSplit = ( BMI != MI ) || ! BBHasFallthrough ( MBB ) ; if ( BMI != MI ) { if ( std :: next ( MachineBasicBlock :: iterator ( MI ) ) == std :: prev ( MBB -> getLastNonDebugInstr ( ) ) && BMI -> getOpcode ( ) == <STR_LIT> ) { MachineBasicBlock * NewDest = BMI -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; if ( isBlockInRange ( MI , NewDest , getBranchDisplacementBits ( MI -> getOpcode ( ) ) ) ) { DEBUG ( dbgs ( ) << <STR_LIT> << * BMI ) ; BMI -> getOperand ( <NUM_LIT> ) . setMBB ( DestBB ) ; unsigned OpNum = ( MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; MI -> getOperand ( OpNum ) . setMBB ( NewDest ) ; MI -> setDesc ( TII -> get ( getOppositeConditionOpcode ( MI -> getOpcode ( ) ) ) ) ; if ( MI -> getOpcode ( ) == <STR_LIT> ) invertBccCondition ( MI ) ; return true ; } } } if ( NeedSplit ) { MachineBasicBlock * TBB , * FBB ; SmallVector < MachineOperand , <NUM_LIT> > Cond ; TII -> AnalyzeBranch ( * MBB , TBB , FBB , Cond , false ) ; MachineBasicBlock * NewBB = splitBlockBeforeInstr ( MI ) ; int delta = TII -> GetInstSizeInBytes ( MBB -> back ( ) ) ; BlockInfo [ MBB -> getNumber ( ) ] . Size -= delta ; MBB -> back ( ) . eraseFromParent ( ) ; MBB -> replaceSuccessor ( FBB , NewBB ) ; NewBB -> addSuccessor ( FBB ) ; } MachineBasicBlock * NextBB = & * std :: next ( MachineFunction :: iterator ( MBB ) ) ; DEBUG ( dbgs ( ) << <STR_LIT> << DestBB -> getNumber ( ) << <STR_LIT> << NextBB -> getNumber ( ) << <STR_LIT> ) ; MachineInstrBuilder MIB = BuildMI ( MBB , DebugLoc ( ) , TII -> get ( getOppositeConditionOpcode ( MI

-> getOpcode ( ) ) ) ) . addOperand ( MI -> getOperand ( <NUM_LIT> ) ) ;


<s> unsigned <ISA_LIT>RegisterInfo :: findUnusedRegister ( const MachineRegisterInfo & MRI , const TargetRegisterClass * RC ) const { for ( TargetRegisterClass :: iterator I = RC -> begin ( ) , E = RC -> end ( ) ; I != E ; ++ I ) { if ( ! MRI . isPhysRegUsed ( * I ) ) return * I ; } return


<s> void ReplaceInstruction ( MCCodeEmitter & E , MCRelaxableFragment & RF , MCInst & HMB ) const { SmallVector < MCFixup , <NUM_LIT> > Fixups ; SmallString < <NUM_LIT> > Code ; raw_svector_ostream VecOS ( Code ) ; E . encodeInstruction ( HMB , VecOS , Fixups , * RF .


<s> if ( ! ( TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS ) ) return false ; if ( d -> vmode != V8QImode ) return false ; if ( ! d -> one_vector_p ) return false ; elt = d -> perm [ <NUM_LIT> ] ; for ( i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) if ( d -> perm [ i ] != elt ) return false ; if ( d ->


<s> static void getVGPRSpillLaneOrTempRegister ( MachineFunction & MF , LivePhysRegs & LiveRegs , Register & TempSGPR , Optional < int > & FrameIndex , bool IsFP ) { <ISA_LIT>MachineFunctionInfo * MFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; MachineFrameInfo & FrameInfo = MF . getFrameInfo ( ) ; const GCNSubtarget & ST = MF . getSubtarget < GCNSubtarget > ( ) ; const <ISA_LIT>RegisterInfo * TRI = ST . getRegisterInfo ( ) ; if ( MFI -> haveFreeLanesForSGPRSpill ( MF , <NUM_LIT> ) ) { int NewFI = FrameInfo . CreateStackObject ( <NUM_LIT> , Align ( <NUM_LIT> ) , true , nullptr , TargetStackID :: SGPRSpill ) ; if ( ! MFI -> allocateSGPRSpillToVGPR ( MF ,

NewFI ) ) llvm_unreachable ( <STR_LIT> ) ;


<s> unsigned <ISA_LIT>MCCodeEmitter :: getBranchTargetOpValue ( const MCInst & Inst , unsigned OpNo , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & SubtargetInfo ) const { const MCOperand & MCOp = Inst . getOperand ( OpNo ) ; MCFixupKind Kind = static_cast <


<s> PrefFunctionLogAlignment = <NUM_LIT> ; break ; case A64FX : CacheLineSize = <NUM_LIT> ; PrefFunctionLogAlignment = <NUM_LIT> ; PrefLoopLogAlignment = <NUM_LIT> ; MaxInterleaveFactor = <NUM_LIT> ; PrefetchDistance = <NUM_LIT> ; MinPrefetchStride = <NUM_LIT> ; MaxPrefetchIterationsAhead = <NUM_LIT> ; break ; case AppleA7 : case AppleA10 : case AppleA11 : case AppleA12 : case AppleA13 : case AppleA14 : CacheLineSize = <NUM_LIT> ; PrefetchDistance = <NUM_LIT> ; MinPrefetchStride = <NUM_LIT> ; MaxPrefetchIterationsAhead = <NUM_LIT> ; break ; case ExynosM3 : MaxInterleaveFactor = <NUM_LIT> ; MaxJumpTableSize = <NUM_LIT> ; PrefFunctionLogAlignment = <NUM_LIT> ; PrefLoopLogAlignment = <NUM_LIT> ; break ; case Falkor : MaxInterleaveFactor = <NUM_LIT> ; MinVectorRegisterBitWidth = <NUM_LIT> ; CacheLineSize = <NUM_LIT> ; PrefetchDistance = <NUM_LIT> ; MinPrefetchStride = <NUM_LIT> ; MaxPrefetchIterationsAhead = <NUM_LIT> ; break ; case Kryo : MaxInterleaveFactor = <NUM_LIT> ; VectorInsertExtractBaseCost = <NUM_LIT> ; CacheLineSize = <NUM_LIT> ; PrefetchDistance = <NUM_LIT>


<s> static int rid_int128 ( void ) { int i ; for ( i = <NUM_LIT> ; i < NUM_INT_N_ENTS ; i ++ ) if ( int_n_enabled_p [ i ] && int_n_data

[ i ] . bitsize == <NUM_LIT> ) return RID_INT_N_0 + i ;


<s> rtx loc [ <NUM_LIT> ] ; int i , offset = <NUM_LIT> ; int ub = valsize <= UNITS_PER_WORD ? <NUM_LIT> : <NUM_LIT> ; for ( i = <NUM_LIT> ; i < ub ; i ++ ) { loc [ i ] = gen_rtx_EXPR_LIST ( VOIDmode , gen_rtx_REG ( DImode , <NUM_LIT> + i ) , GEN_INT ( offset ) ) ; offset += <NUM_LIT> ; } return gen_rtx_PARALLEL ( BLKmode , gen_rtvec_v ( ub , loc ) ) ; } else if ( valsize > UNITS_PER_WORD ) { rtx loc = gen_rtx_EXPR_LIST ( VOIDmode , gen_rtx_REG ( DImode , <NUM_LIT> ) , const0_rtx ) ; return gen_rtx_PARALLEL ( BLKmode , gen_rtvec ( <NUM_LIT> , loc ) ) ; } } if ( ( INTEGRAL_TYPE_P ( valtype ) && GET_MODE_BITSIZE ( TYPE_MODE ( valtype ) ) < BITS_PER_WORD ) || POINTER_TYPE_P ( valtype ) ) valmode = word_mode ; else valmode = TYPE_MODE (


<s> static DecodeStatus DecodeLD8RegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t Address , const MCDisassembler * Decoder ) { if ( RegNo > <NUM_LIT> ) return MCDisassembler :: Fail ; unsigned Register = GPRDecoderTable [ RegNo + <NUM_LIT> ] ; Inst . addOperand ( MCOperand :: createReg


<s> bool <ISA_LIT>RegisterInfo :: requiresFrameIndexReplacementScavenging ( const MachineFunction & MF ) const { return MF . getFrameInfo ( ) . hasStackObjects ( ) && MF . getSubtarget < GCNSubtarget > ( ) . hasScalarStores ( )

&& MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) -> hasSpilledSGPRs ( ) ;


<s> if ( GET_CODE ( * ptr ) == REG ) { int regno = REGNO ( * ptr ) ; HARD_REG_SET * p_regs = ( HARD_REG_SET * ) data ; if ( regno < FIRST_PSEUDO_REGISTER ) { int reg_max = regno + HARD_REGNO_NREGS ( regno , GET_MODE ( * ptr ) ) ; while ( regno < reg_max ) { CLEAR_HARD_REG_BIT ( * p_regs , regno ) ; regno ++


<s> static unsigned getFixupKindLog2Size ( unsigned Kind ) { switch ( Kind ) { default : llvm_unreachable ( <STR_LIT> ) ; case FK_PCRel_1 : case FK_SecRel_1 : case FK_Data_1 : return <NUM_LIT> ; case FK_PCRel_2 : case FK_SecRel_2 : case FK_Data_2 : return <NUM_LIT> ; case FK_PCRel_4 : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case


<s> bool hasStdExtZvfh ( ) const { return


<s> } else return SDValue ( ) ; } if ( nextIndex != Vec . getValueType ( ) . getVectorNumElements ( ) || Vec . getValueType ( ) . getVectorElementType ( ) == VT . getVectorElementType ( ) ) return SDValue ( ) ; SelectionDAG & DAG = DCI . DAG ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; SDLoc dl ( N ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . push_back ( DAG . getConstant ( <STR_LIT> , dl , TLI . getPointerTy ( DAG . getDataLayout ( ) ) ) ) ; Ops . push_back ( Vec ) ; MVT widenType ; unsigned numElem = VT . getVectorNumElements ( ) ; EVT inputLaneType = Vec . getValueType ( ) . getVectorElementType ( ) ; switch ( inputLaneType . getSimpleVT ( ) . SimpleTy ) { case <STR_LIT> : widenType = <STR_LIT> ( <STR_LIT> , numElem ) ; break ; case <STR_LIT> : widenType = <STR_LIT> ( <STR_LIT> , numElem ) ; break ; case <STR_LIT> : widenType = <STR_LIT> ( <STR_LIT> , numElem ) ; break ; default : llvm_unreachable (


<s> while ( ! MI . getOperand ( i ) . isFI ( ) ) ++ i ; assert ( i < MI . getNumOperands ( ) && <STR_LIT> ) ; frame_index = MI . getOperand ( i ) . getIndex ( ) ; offs = MF . getFrameInfo ( ) -> getObjectOffset ( frame_index ) ; const TargetInstrDesc tid = MI . getDesc ( ) ; access_alignment = ( tid . TSFlags & <STR_LIT> ) >> <STR_LIT> ; if ( ! ( MI . getDesc ( ) . TSFlags & <STR_LIT> ) ) { if ( <ISA_LIT>InstrInfo :: check_sconst_fits ( offs , <NUM_LIT> ) ) { MI . getOperand ( i ) . ChangeToImmediate ( offs ) ; return ; } access_alignment = <NUM_LIT> ; } else if ( <ISA_LIT>InstrInfo :: check_uconst_fits ( abs ( offs ) , <NUM_LIT> + access_alignment ) ) { MI . getOperand ( i ) . ChangeToImmediate ( offs >> access_alignment ) ; return ; } if ( offs & ( ( <NUM_LIT> << access_alignment ) - <NUM_LIT> ) ) llvm_unreachable ( <STR_LIT> ) ; offs >>= access_alignment ; const TargetRegisterClass * c ; if ( tid . TSFlags & <STR_LIT> ) c = <STR_LIT> ; else c = <STR_LIT> ; reg = r -> FindUnusedReg ( c ) ; if ( reg == <NUM_LIT> ) { reg = r -> scavengeRegister ( c , MBBI , <NUM_LIT> ) ; } unsigned side_a = ( c == <STR_LIT> ) ; if ( <ISA_LIT>InstrInfo :: check_sconst_fits ( offs , <NUM_LIT> ) ) { <ISA_LIT>InstrInfo :: addFormOp ( <ISA_LIT>InstrInfo :: addDefaultPred ( BuildMI ( MBB , MBBI , dl , TII . get ( side_a ? mvk_1 : mvk_2 ) ) . addReg ( reg , RegState :: Define ) . addImm ( offs ) ) , <STR_LIT> , false ) ; } else { <ISA_LIT>InstrInfo :: addFormOp ( <ISA_LIT>InstrInfo :: addDefaultPred ( BuildMI ( MBB , MBBI , dl , TII . get ( side_a ? mvkl_1 : mvkl_2 ) ) . addReg ( reg , RegState :: Define ) . addImm ( offs ) ) , <STR_LIT> , false ) ; <ISA_LIT>InstrInfo :: addFormOp ( <ISA_LIT>InstrInfo :: addDefaultPred ( BuildMI ( MBB , MBBI , dl , TII . get ( side_a ? mvkh_1 : mvkh_2 ) ) . addReg ( reg , RegState :: Define ) . addImm ( offs ) . addReg ( reg ) ) , <STR_LIT> , false ) ; } MI . getOperand ( i ) . ChangeToRegister ( reg


<s> auto * I = dyn_cast < Instruction > ( V ) ; if ( ! I ) return false ; switch ( I -> getOpcode ( ) ) { case Instruction :: Add : if ( Match ( I -> getOperand ( <NUM_LIT> ) ) || ( Match ( I -> getOperand ( <NUM_LIT> ) ) ) ) return true ; break ; case Instruction :: Mul : { Value * MulOp0 = I -> getOperand ( <NUM_LIT> ) ; Value * MulOp1 = I -> getOperand ( <NUM_LIT> ) ; if ( isa < SExtInst > ( MulOp0 ) && isa < SExtInst > ( MulOp1 ) ) AddMACCandidate ( Candidates , I


<s> if ( EmitFPOData ) { <ISA_LIT>TargetStreamer * XTS = static_cast < <ISA_LIT>TargetStreamer * > ( OutStreamer -> getTargetStreamer ( ) ) ; switch ( MI -> getOpcode ( ) ) { case <STR_LIT> : XTS -> emitFPOPushReg ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; break ; case <STR_LIT> : XTS -> emitFPOStackAlloc ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; break ; case <STR_LIT> : assert ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> && <STR_LIT> ) ; XTS -> emitFPOSetFrame ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; break ; case <STR_LIT> : XTS -> emitFPOEndPrologue ( ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : llvm_unreachable ( <STR_LIT> ) ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } return ; } switch ( MI -> getOpcode ( ) ) { case <STR_LIT> : OutStreamer -> EmitWinCFIPushReg ( RI -> getSEHRegNum ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ) ; break ; case <STR_LIT> : OutStreamer -> EmitWinCFISaveReg ( RI -> getSEHRegNum ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) , MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; break ; case <STR_LIT> : OutStreamer -> EmitWinCFISaveXMM ( RI -> getSEHRegNum ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) , MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; break ; case <STR_LIT> : OutStreamer -> EmitWinCFIAllocStack ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; break ; case <STR_LIT> : OutStreamer -> EmitWinCFISetFrame ( RI -> getSEHRegNum ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) , MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; break ; case <STR_LIT>


<s> void <ISA_LIT>AsmPrinter :: EmitFunctionEntryLabel ( ) { <ISA_LIT>TargetStreamer & TS = getTargetStreamer ( ) ; if ( Subtarget -> isTargetNaCl ( ) ) EmitAlignment ( std :: max ( MF -> getAlignment ( ) , MIPS_NACL_BUNDLE_ALIGN ) ) ; if ( Subtarget -> inMicro<ISA_LIT>Mode ( ) ) { TS . emitDirectiveSetMicro<ISA_LIT> (


<s> bool isMove = false ; unsigned TSFlags = ( MI . getDesc ( ) . TSFlags & <STR_LIT> ) >> <STR_LIT> ; isMove = ( TSFlags == <NUM_LIT> ) ; if ( isMove ) { MachineOperand dest = MI . getOperand ( <NUM_LIT> ) ; MachineOperand src = MI . getOperand ( <NUM_LIT> ) ; assert ( dest . isReg ( ) && <STR_LIT>


<s> else if ( litmsk == <NUM_LIT> ) result = vec_xxpermdi ( __B , __A , <NUM_LIT> ) ; else if ( litmsk == <NUM_LIT> ) result = vec_xxpermdi ( __B , __A , <NUM_LIT> ) ; else if ( litmsk == <NUM_LIT> ) result = vec_xxpermdi ( __A , __B


<s> bool <ISA_LIT>InstPrinter :: isV9 ( )


<s> unsigned Offset = Fixup . getOffset ( ) ; unsigned NumBytes = alignTo ( Info . TargetSize + Info . TargetOffset , <NUM_LIT> ) / <NUM_LIT> ; assert ( Offset + NumBytes <= Data . size ( ) && <STR_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i != NumBytes


<s> assert ( FirstNonZero . getNode ( ) && <STR_LIT> ) ; SDValue V1 = FirstNonZero . getOperand ( <NUM_LIT> ) ; MVT VT = V1 . getSimpleValueType ( ) ; SDValue Elt ; unsigned EltMaskIdx , EltIdx ; int Mask [ <NUM_LIT> ] ; for ( EltIdx = <NUM_LIT> ; EltIdx < <NUM_LIT> ; ++ EltIdx ) { if ( Zeroable [ EltIdx ] ) { Mask [ EltIdx ] = EltIdx + <NUM_LIT> ; continue ; } Elt = Op -> getOperand ( EltIdx ) ; EltMaskIdx = cast < ConstantSDNode > ( Elt . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; if ( Elt . getOperand ( <NUM_LIT> ) != V1 || EltMaskIdx != EltIdx ) break ; Mask [ EltIdx ] = EltIdx ; } if ( EltIdx == <NUM_LIT> ) { SDValue VZero = getZeroVector ( VT , Subtarget , DAG , SDLoc ( Op ) ) ; if ( V1 . getSimpleValueType ( ) != VT ) V1 = DAG . getNode ( <STR_LIT> , SDLoc ( V1 ) , VT , V1 ) ; return DAG . getVectorShuffle ( VT , SDLoc ( V1 ) , V1 , VZero , & Mask [ <NUM_LIT> ] ) ; } if ( ! Subtarget -> hasSSE41 ( ) ) return SDValue ( ) ; SDValue V2 = Elt . getOperand ( <NUM_LIT> ) ; if ( Elt == FirstNonZero && EltIdx == FirstNonZeroIdx ) V1 = SDValue ( ) ; bool CanFold = true ; for ( unsigned i = EltIdx + <NUM_LIT> ; i < <NUM_LIT> && CanFold ; ++ i ) { if ( Zeroable [ i ] ) continue ; SDValue Current = Op -> getOperand ( i ) ; SDValue SrcVector = Current -> getOperand ( <NUM_LIT> ) ; if ( ! V1 . getNode ( ) ) V1 = SrcVector ; CanFold = SrcVector == V1 && cast < ConstantSDNode > ( Current . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) == i ; } if ( ! CanFold )


<s> if ( StoreSize <= <NUM_LIT> ) return EVT :: getIntegerVT ( Ctx , <NUM_LIT> ) ; return EVT :: getVectorVT ( Ctx , <STR_LIT> , StoreSize


<s> if ( InterlEarlyExit . find ( Subtarget ) != InterlEarlyExit . end ( ) ) return InterlEarlyExit [ Subtarget ] ; for ( auto & I : IRT ) { OriginalMCID = & TII -> get ( I . OrigOpc ) ; for ( auto & Repl : I . ReplOpc ) ReplInstrMCID . push_back ( & TII -> get ( Repl ) ) ; if ( shouldReplaceInst ( MF , OriginalMCID , ReplInstrMCID ) ) { InterlEarlyExit [ Subtarget ] = false ; return false ; } ReplInstrMCID . clear ( ) ; } InterlEarlyExit [ Subtarget ] = true ; break ; } return true


<s> for ( Argument & Arg : F . args ( ) ) { if ( Arg . getType ( ) -> isPointerTy ( ) ) { if ( Arg . hasByValAttr ( ) ) handleByValParam ( & Arg ) ; else if ( TM && TM -> getDrvInterface ( ) == <STR_LIT> ) markPointerAsGlobal ( & Arg ) ; } } return true


<s> SDNode * OrOpd1 = N -> getOperand ( <NUM_LIT> ) . getNode ( ) ; for ( int i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i , std :: swap ( OrOpd0 , OrOpd1 ) , OrOpd1Val = N -> getOperand ( <NUM_LIT> ) ) { unsigned BFXOpc ; int DstLSB , Width ; if ( isBitfieldExtractOp ( CurDAG , OrOpd0 , BFXOpc , Src , ImmR , ImmS , NumberOfIgnoredLowBits , true ) ) { if ( ( BFXOpc != <STR_LIT> && VT == <STR_LIT> ) || ( BFXOpc != <STR_LIT> && VT == <STR_LIT> ) ) continue ; DstLSB = <NUM_LIT> ; Width = ImmS - ImmR + <NUM_LIT> ; if ( Width <= <NUM_LIT> ) continue ; } else if ( isBitfieldPositioningOp ( CurDAG , SDValue ( OrOpd0 , <NUM_LIT> ) , Src , DstLSB , Width ) ) { ImmR = ( VT . getSizeInBits ( ) - DstLSB ) % VT . getSizeInBits ( ) ; ImmS = Width - <NUM_LIT> ; } else continue ; EVT VT = OrOpd1 -> getValueType ( <NUM_LIT> ) ; assert ( ( VT == <STR_LIT> || VT == <STR_LIT> ) && <STR_LIT> ) ; APInt KnownZero , KnownOne ; CurDAG -> computeKnownBits ( OrOpd1Val , KnownZero , KnownOne ) ; APInt BitsToBeInserted = APInt :: getBitsSet ( KnownZero . getBitWidth ( ) , DstLSB , DstLSB + Width ) ; if ( ( BitsToBeInserted & ~ KnownZero ) != <NUM_LIT> ) continue ; uint64_t Imm ; if ( isOpcWithIntImmediate ( OrOpd1 , <STR_LIT> , Imm ) && isBitfieldDstMask ( Imm , BitsToBeInserted , NumberOfIgnoredHighBits , VT ) ) Dst = OrOpd1 -> getOperand ( <NUM_LIT> ) ; else Dst =


<s> if ( TT . isOSBinFormatMachO ( ) ) { MachineModuleInfoMachO & MMIMacho = MMI -> getObjFileInfo < MachineModuleInfoMachO > ( ) ; MachineModuleInfoMachO :: SymbolListTy Stubs ; Stubs = MMIMacho . GetFnStubList ( ) ; if ( ! Stubs . empty ( ) ) { MCSection * TheSection = OutContext . getMachOSection ( <STR_LIT> , <STR_LIT> , MachO :: S_SYMBOL_STUBS | MachO :: S_ATTR_SELF_MODIFYING_CODE | MachO :: S_ATTR_PURE_INSTRUCTIONS , <NUM_LIT> , SectionKind :: getMetadata ( ) ) ; OutStreamer -> SwitchSection ( TheSection ) ; for ( const auto & Stub : Stubs ) { OutStreamer -> EmitLabel ( Stub . first ) ; OutStreamer -> EmitSymbolAttribute ( Stub . second . getPointer ( ) , MCSA_IndirectSymbol ) ; const char HltInsts [ ] = <STR_LIT> ; OutStreamer -> EmitBytes ( StringRef ( HltInsts , <NUM_LIT> ) ) ; } Stubs . clear ( ) ; OutStreamer -> AddBlankLine ( ) ; } Stubs = MMIMacho . GetGVStubList ( ) ; if ( ! Stubs . empty ( ) ) { MCSection * TheSection = OutContext . getMachOSection ( <STR_LIT> , <STR_LIT> , MachO :: S_NON_LAZY_SYMBOL_POINTERS , SectionKind :: getMetadata ( ) ) ; OutStreamer -> SwitchSection ( TheSection ) ; for ( auto & Stub : Stubs ) emitNonLazySymbolPointer ( * OutStreamer , Stub . first , Stub . second ) ; Stubs . clear ( ) ; OutStreamer -> AddBlankLine ( ) ; } Stubs = MMIMacho . GetHiddenGVStubList ( ) ; if ( ! Stubs . empty


<s> if ( ! STI . getInstrInfo ( ) -> verifyInstruction ( MI , Err ) ) { errs ( ) << <STR_LIT> << Err << <STR_LIT> ; MI -> dump ( ) ; } if ( MI -> isBundle ( ) ) { const MachineBasicBlock * MBB = MI -> getParent ( ) ; MachineBasicBlock :: const_instr_iterator I = MI ; ++ I ; while ( I != MBB -> end ( ) && I -> isInsideBundle ( ) ) { EmitInstruction ( I ) ; ++ I ; } } else { MCInst TmpInst ; MCInstLowering . lower ( MI , TmpInst ) ; EmitToStreamer ( OutStreamer , TmpInst ) ; if ( STI . dumpCode ( ) ) { DisasmLines . resize ( DisasmLines . size ( ) + <NUM_LIT> ) ; std :: string & DisasmLine = DisasmLines . back ( ) ; raw_string_ostream DisasmStream ( DisasmLine ) ; AMDGPUInstPrinter InstPrinter ( * TM . getMCAsmInfo ( ) , * MF -> getSubtarget ( ) . getInstrInfo ( ) , * MF -> getSubtarget ( ) . getRegisterInfo ( ) ) ; InstPrinter . printInst ( & TmpInst , DisasmStream , StringRef ( ) , MF -> getSubtarget ( ) ) ; SmallVector < MCFixup , <NUM_LIT> > Fixups ; SmallVector < char , <NUM_LIT> > CodeBytes ; raw_svector_ostream CodeStream ( CodeBytes ) ; MCObjectStreamer & ObjStreamer = ( MCObjectStreamer & ) OutStreamer ; MCCodeEmitter & InstEmitter = ObjStreamer . getAssembler ( ) . getEmitter ( ) ; InstEmitter . EncodeInstruction ( TmpInst , CodeStream , Fixups , MF -> getSubtarget < MCSubtargetInfo > ( ) ) ; CodeStream . flush (


<s> rs6000_output_symbol_ref ( FILE , SYM ) { char * buffer = ( char * ) alloca ( strlen ( NAME ) + <NUM_LIT> ) ; \ char * p ; \ int dollar_inside = <NUM_LIT> ; \ strcpy ( buffer , NAME ) ; \ p = strchr ( buffer , '$' ) ; \ while ( p ) { \ * p = '_' ; \ dollar_inside ++ ; \ p = strchr ( p + <NUM_LIT> , '$' ) ; \ } \ if ( dollar_inside ) { \ fputs ( <STR_LIT> , FILE ) ; \ RS6000_OUTPUT_BASENAME ( FILE ,

buffer ) ; \ putc ( '\n' , FILE ) ; \ fprintf ( FILE , <STR_LIT> , buffer , NAME ) ; \ } \ }


<s> Register Result = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register Base = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register Offset = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; MachineInstr * GlobalBase = getOpcodeDef ( G_GLOBAL_VALUE , Base , MRI ) ; auto ConstOffset = getIConstantVRegValWithLookThrough ( Offset , MRI ) ; if ( GlobalBase && ConstOffset ) { const MachineOperand & Op = GlobalBase -> getOperand ( <NUM_LIT> ) ; Builder . buildInstr ( G_GLOBAL_VALUE ) . addDef ( Result ) . addGlobalAddress ( Op . getGlobal ( ) , Op . getOffset ( ) + ConstOffset -> Value . getSExtValue ( ) ) ; MI . eraseFromParent ( ) ; return true ; } LLT S16 = LLT :: scalar ( <NUM_LIT> ) ; auto PtrVal = Builder . buildPtrToInt ( S16 , Base ) ; auto Sum = Builder . buildAdd ( S16 , PtrVal , Offset ) ; Builder . buildIntToPtr ( Result , Sum ) ; MI . eraseFromParent ( ) ; return


<s> RegisterTarget < Triple :: cpu0 , true > X ( getThe<ISA_LIT>Target ( ) , <STR_LIT> , <STR_LIT> , <STR_LIT> ) ; RegisterTarget < Triple :: cpu0el , true > Y ( getThe<ISA_LIT>elTarget ( ) , <STR_LIT> ,


<s> unsigned Opc ; if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg ,


<s> Cond . push_back ( MachineOperand :: CreateImm ( LastInst -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ) ; Cond . push_back ( LastInst -> getOperand ( <NUM_LIT> ) ) ; Cond . push_back ( LastInst -> getOperand


<s> auto * CCI = IRB -> CreateIntrinsic ( <STR_LIT> , { } , { Args } ) ; Worklist . push ( CCI ) ; I -> replaceUsesOfWith ( Op , CCI ) ; KeepInst = true ; AggrConsts [ CCI ] = AggrC ; } ; if ( auto * AggrC = dyn_cast < ConstantAggregate > ( Op ) ) { SmallVector < Value * > Args ( AggrC -> op_begin ( ) , AggrC -> op_end ( ) ) ; BuildCompositeIntrinsic ( AggrC , Args ) ; } else if ( auto * AggrC = dyn_cast < ConstantDataArray > ( Op ) ) { SmallVector < Value * > Args ; for ( unsigned i = <NUM_LIT> ; i < AggrC -> getNumElements ( ) ; ++ i ) Args . push_back ( AggrC -> getElementAsConstant ( i ) ) ; BuildCompositeIntrinsic ( AggrC , Args ) ; } else if ( isa < ConstantAggregateZero > ( Op ) && ! Op -> getType ( ) -> isVectorTy ( ) ) { auto * AggrC = cast < ConstantAggregateZero > ( Op ) ; SmallVector < Value * > Args ( AggrC -> op_begin ( ) , AggrC -> op_end (


<s> SDLoc DL ( Op ) ; unsigned Reg = <NUM_LIT> ; unsigned size = <NUM_LIT> ; switch ( T . SimpleTy ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : Reg = <STR_LIT> ; size = <NUM_LIT> ; break ; case <STR_LIT> : Reg = <STR_LIT> ; size = <NUM_LIT> ; break ; case <STR_LIT> : Reg = <STR_LIT> ; size = <NUM_LIT> ; break ; case <STR_LIT> : assert ( Subtarget . is64Bit ( ) && <STR_LIT> ) ; Reg = <STR_LIT> ; size = <NUM_LIT> ; break ; } SDValue cpIn = DAG . getCopyToReg ( Op . getOperand ( <NUM_LIT> ) , DL , Reg , Op . getOperand ( <NUM_LIT> ) , SDValue ( ) ) ; SDValue Ops [ ] = { cpIn . getValue ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , DAG . getTargetConstant ( size , DL , <STR_LIT> ) , cpIn . getValue ( <NUM_LIT> ) } ; SDVTList Tys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; MachineMemOperand * MMO = cast < AtomicSDNode > ( Op ) -> getMemOperand ( ) ; SDValue Result = DAG . getMemIntrinsicNode ( <STR_LIT> , DL , Tys , Ops , T , MMO ) ; SDValue cpOut = DAG . getCopyFromReg ( Result . getValue ( <NUM_LIT> ) , DL , Reg , T , Result . getValue ( <NUM_LIT> ) ) ; SDValue EFLAGS = DAG . getCopyFromReg ( cpOut . getValue ( <NUM_LIT> ) , DL , <STR_LIT> , <STR_LIT> , cpOut . getValue ( <NUM_LIT> ) ) ; SDValue Success = getSETCC ( <STR_LIT> , EFLAGS , DL , DAG ) ; DAG . ReplaceAllUsesOfValueWith ( Op . getValue ( <NUM_LIT> ) , cpOut ) ; DAG . ReplaceAllUsesOfValueWith ( Op . getValue ( <NUM_LIT> ) , Success ) ; DAG . ReplaceAllUsesOfValueWith ( Op . getValue ( <NUM_LIT> ) , EFLAGS . getValue ( <NUM_LIT> ) ) ; return SDValue (


<s> void printSymbolLSA ( const MachineInstr * MI , unsigned


<s> SDValue Arg = OutVals [ realRVLocIdx ] ; switch ( VA . getLocInfo ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case CCValAssign :: Full : if ( Outs [ i ] . ArgVT == <STR_LIT> ) { Arg = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Arg ) ; Arg = DAG . getNode ( <STR_LIT> , DL , VA . getLocVT ( ) , Arg ) ; } break ; case CCValAssign :: BCvt : Arg = DAG . getNode ( <STR_LIT> , DL , VA . getLocVT ( ) , Arg ) ; break ; } Chain = DAG . getCopyToReg ( Chain , DL , VA . getLocReg ( ) , Arg , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( VA . getLocReg ( ) , VA . getLocVT ( ) ) ) ; } const <ISA_LIT>RegisterInfo * TRI = Subtarget -> getRegisterInfo ( ) ; const MCPhysReg * I = TRI -> getCalleeSavedRegsViaCopy ( & DAG . getMachineFunction ( ) ) ; if ( I ) { for ( ; * I ; ++ I ) { if ( <STR_LIT> . contains ( * I ) ) RetOps . push_back ( DAG . getRegister ( * I , <STR_LIT> ) ) ; else if ( <STR_LIT> . contains ( * I ) ) RetOps . push_back ( DAG . getRegister ( * I , <STR_LIT> ( <NUM_LIT> ) ) ) ; else llvm_unreachable ( <STR_LIT> ) ; } } RetOps [ <NUM_LIT> ]


<s> MachineInstr * Branch = & ( * TI ) ; MachineFunction * MF = IfEntry -> getParent ( ) ; MachineRegisterInfo & MRI = IfEntry -> getParent ( ) -> getRegInfo ( ) ; if ( Branch -> getOpcode ( ) == <STR_LIT> ) { unsigned DstReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; MachineInstr * <ISA_LIT>IF = BuildMI ( * MF , Branch -> getDebugLoc ( ) , get ( <STR_LIT> ) , DstReg ) . add ( Branch -> getOperand ( <NUM_LIT> ) ) . add ( Branch -> getOperand ( <NUM_LIT> ) ) ; MachineInstr * <ISA_LIT>END = BuildMI ( * MF , Branch -> getDebugLoc ( ) , get ( <STR_LIT> ) ) . addReg ( DstReg ) ; IfEntry -> erase (


<s> if ( ! S . isValid ( ) ) { LV . set ( I . PhysReg ) ; continue ; } do { LaneBitmask M = TRI . getSubRegIndexLaneMask ( S . getSubRegIndex ( ) ) ; if ( ( M & I . LaneMask ) . any ( ) ) LV . set ( S . getSubReg ( ) ) ; ++ S ; } while ( S . isValid ( ) ) ; } } ; BitVector LiveIn ( TRI . getNumRegs ( ) ) , Live ( TRI . getNumRegs ( ) ) ; CopyLiveIns ( B , LiveIn ) ; for ( auto SI : B -> successors ( ) ) CopyLiveIns ( SI , Live ) ; for ( auto I = B -> rbegin ( ) , E = B -> rend ( ) ; I != E ; ++ I ) { MachineInstr * MI = & * I ; if ( MI -> isDebugValue ( ) ) continue ; MI -> clearKillInfo


<s> static SDValue buildPCRelGlobalAddress ( SelectionDAG & DAG , const GlobalValue * GV , const SDLoc & DL , unsigned Offset , EVT PtrVT , unsigned GAFlags = <ISA_LIT>InstrInfo :: MO_NONE ) { SDValue PtrLo = DAG . getTargetGlobalAddress ( GV , DL , <STR_LIT> , Offset + <NUM_LIT> , GAFlags ) ; SDValue PtrHi = DAG . getTargetGlobalAddress ( GV , DL , <STR_LIT> , Offset + <NUM_LIT>

, GAFlags == <ISA_LIT>InstrInfo :: MO_NONE ? GAFlags : GAFlags + <NUM_LIT> ) ;


<s> unsigned MappingID = <NUM_LIT> ; for ( const auto & Entry : Table ) { for ( unsigned I = <NUM_LIT> ; I < NumOps ; ++ I ) { int OpIdx = RegSrcOpIdx [ I ] ; Operands [ OpIdx ] = <STR_LIT> ( Entry . RegBanks [ I ] , Sizes [ I ] ) ; } AltMappings . push_back ( & getInstructionMapping ( MappingID ++ , Entry . Cost , getOperandsMapping ( Operands ) , Operands . size ( ) ) ) ; } return AltMappings


<s> bool hasDFPPackedConversion ( ) const { return HasDFPPackedConversion


<s> insertPass ( & <ISA_LIT>LowerControlFlowID , & <ISA_LIT>FixWWMLivenessID , false ) ; TargetPassConfig :: addFastRegAlloc (


<s> unsigned <ISA_LIT>Subtarget :: getOccupancyWithNumSGPRs ( unsigned SGPRs ) const { if ( getGeneration ( ) >= <ISA_LIT>Subtarget :: VOLCANIC_ISLANDS ) { if ( SGPRs <= <NUM_LIT> ) return <NUM_LIT> ; if ( SGPRs <= <NUM_LIT> ) return <NUM_LIT> ; if ( SGPRs <= <NUM_LIT> ) return <NUM_LIT> ; return <NUM_LIT> ; } if ( SGPRs <= <NUM_LIT> ) return <NUM_LIT> ; if ( SGPRs <= <NUM_LIT> )


<s> return ( __m256d ) __builtin_ia32_vfmaddpd256_maskz ( ( __v4df ) __A , ( __v4df )


<s> RTLIB :: Libcall LC ; if ( N -> getOpcode ( ) == <STR_LIT> || N -> getOpcode ( ) == <STR_LIT> ) LC = RTLIB :: getFPTOSINT ( Op0 . getValueType ( ) , N -> getValueType ( <NUM_LIT> ) ) ; else LC = RTLIB :: getFPTOUINT ( Op0 . getValueType ( ) , N -> getValueType ( <NUM_LIT> ) ) ; MakeLibCallOptions CallOptions ; EVT OpVT = Op0 . getValueType ( ) ; CallOptions . setTypeListBeforeSoften ( OpVT , N -> getValueType ( <NUM_LIT> ) , true ) ; SDValue Chain = IsStrict ? N -> getOperand ( <NUM_LIT> ) : SDValue ( ) ; SDValue Result ; std :: tie ( Result , Chain ) = makeLibCall ( DAG , LC , N -> getValueType ( <NUM_LIT> ) , Op0 , CallOptions , DL , Chain ) ; Results . push_back ( Result ) ; if ( IsStrict ) Results . push_back ( Chain ) ; break ; } case <STR_LIT> : { assert ( ! Subtarget . is64Bit ( ) && <STR_LIT> ) ; SDVTList VTs = DAG . getVTList ( <STR_LIT> , <STR_LIT> , <STR_LIT> ) ; SDValue RCW = DAG . getNode ( <STR_LIT> , DL , VTs , N -> getOperand ( <NUM_LIT> ) ) ; Results . push_back ( DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , RCW , RCW . getValue ( <NUM_LIT> ) ) ) ; Results . push_back ( RCW . getValue ( <NUM_LIT> ) ) ; break ; } case <STR_LIT>


<s> static void block_move_call ( rtx dest_reg , rtx src_reg , rtx bytes_rtx ) { if ( GET_MODE ( bytes_rtx ) != VOIDmode && GET_MODE ( bytes_rtx ) != Pmode ) bytes_rtx = convert_to_mode ( Pmode , bytes_rtx , <NUM_LIT> ) ; emit_library_call ( m32r_function_symbol ( <STR_LIT> ) , <NUM_LIT> , VOIDmode , <NUM_LIT> , dest_reg , Pmode , src_reg , Pmode , convert_to_mode ( TYPE_MODE ( sizetype ) ,

bytes_rtx , TYPE_UNSIGNED ( sizetype ) ) , TYPE_MODE ( sizetype ) ) ;


<s> else if ( bytes == GET_MODE_SIZE ( SImode ) ) return SImode ; else if ( bytes == GET_MODE_SIZE ( HImode ) ) return HImode ; else if ( bytes == GET_MODE_SIZE ( QImode ) ) return QImode ; else if ( bytes < GET_MODE_SIZE ( SImode ) && offset >= GET_MODE_SIZE ( SImode ) - bytes ) return SImode ; else if ( word_mode_ok && bytes < UNITS_PER_WORD && offset >= UNITS_PER_WORD - bytes ) return word_mode ; else if ( word_mode_ok && maxread >= UNITS_PER_WORD ) return word_mode ; else if ( maxread >= GET_MODE_SIZE ( SImode ) ) return SImode ; else if ( bytes > GET_MODE_SIZE ( SImode ) ) return


<s> case PLUS : { register rtx plus0 = XEXP ( addr , <NUM_LIT> ) ; register rtx plus1 = XEXP ( addr , <NUM_LIT> ) ; if ( GET_CODE ( plus0 ) != REG && ( GET_CODE ( plus0 ) != MULT || ! CONST_INT_P ( XEXP ( plus0 , <NUM_LIT> ) ) || ( INTVAL ( XEXP ( plus0 , <NUM_LIT> ) ) != <NUM_LIT> && INTVAL ( XEXP ( plus0 , <NUM_LIT> ) ) != <NUM_LIT> ) ) ) break ; switch ( GET_CODE ( plus1 ) ) { case CONST_INT : return ( ! RTX_OK_FOR_OFFSET_P ( SImode , plus1 ) ? COSTS_N_INSNS ( <NUM_LIT> ) : speed ? <NUM_LIT> : ( satisfies_constraint_Rcq ( plus0 ) && satisfies_constraint_O ( plus1 ) ) ? <NUM_LIT> : <NUM_LIT> ) ; case REG


<s> static const char * const CPUDirectives [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; unsigned Directive = <STR_LIT> ; for ( const Function & F : M ) { const <ISA_LIT>Subtarget & STI = TM . getSubtarget < <ISA_LIT>Subtarget > ( F ) ; unsigned FDir = STI . getDarwinDirective ( ) ; Directive = Directive > FDir ? FDir : STI . getDarwinDirective ( ) ; if ( STI . hasMFOCRF ( ) && Directive < <STR_LIT> ) Directive = <STR_LIT> ; if ( STI . hasAltivec ( ) && Directive < <STR_LIT> ) Directive = <STR_LIT> ; if ( STI . is<ISA_LIT>64 ( ) && Directive < <STR_LIT> ) Directive = <STR_LIT> ; } assert ( Directive <= <STR_LIT> && <STR_LIT> ) ; assert ( Directive < array_lengthof ( CPUDirectives ) && <STR_LIT>


<s> void addSysCROperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> &&


<s> Sig = OS . str ( ) ; erase_if ( Sig , isSpace ) ; std :: replace ( Sig . begin ( ) , Sig . end ( ) , ','


<s> const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; if ( ! CE ) return false ; int64_t Value = CE -> getValue ( ) ; return Value > <NUM_LIT>


<s> static int stackSlotSize ( ) { return


<s> MFI -> setReturnAddressIsTaken ( true ) ; if ( verifyReturnAddressArgumentIsConstant ( Op , DAG ) ) return SDValue ( ) ; unsigned Depth = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; SDLoc dl ( Op ) ; auto PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; if ( Depth > <NUM_LIT> ) { SDValue FrameAddr = LowerFRAMEADDR ( Op , DAG


<s> getLexer ( ) . Lex ( ) ; WithPostInc = true ; } if ( ! getLexer ( ) . is ( AsmToken :: Comma ) ) { Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; return nullptr ; } Parser . Lex ( ) ; std :: unique_ptr < <ISA_LIT>Operand > ImmOp = ParseImmediate ( ) ; if ( ! ImmOp ) { Error ( Parser . getTok ( ) . getLoc


<s> case <NUM_LIT> : break ; } unsigned NumOps = Desc -> getNumOperands ( ) ; unsigned CurOp = <NUM_LIT> ; if ( NumOps > <NUM_LIT> && Desc -> getOperandConstraint ( <NUM_LIT> , MCOI :: TIED_TO ) == <NUM_LIT> ) ++ CurOp ; else if ( NumOps > <NUM_LIT> && Desc -> getOperandConstraint ( <NUM_LIT> , MCOI :: TIED_TO ) == <NUM_LIT> ) { assert ( Desc -> getOperandConstraint ( NumOps - <NUM_LIT> , MCOI :: TIED_TO ) == <NUM_LIT> ) ; CurOp += <NUM_LIT> ; } switch ( TSFlags & <STR_LIT> ) { case <STR_LIT> : if ( <STR_LIT> ( MI . getOperand ( CurOp ) . getReg ( ) ) ) VEX_R = <NUM_LIT> ; if ( HasVEX_4V ) VEX_4V = getVEXRegisterEncoding ( MI , CurOp ) ; if ( <STR_LIT> ( MI . getOperand ( CurOp ) . getReg ( ) ) ) VEX_B = <NUM_LIT> ; if ( HasVEX_4VOp3 ) VEX_4V = getVEXRegisterEncoding ( MI , CurOp ) ; break ; case <STR_LIT> : { if ( <STR_LIT> ( MI . getOperand ( <STR_LIT> ) . getReg ( ) ) ) VEX_B = <NUM_LIT> ; if ( <STR_LIT> ( MI . getOperand ( <STR_LIT> ) . getReg ( ) ) ) VEX_X = <NUM_LIT> ; CurOp = <STR_LIT> ; if ( HasVEX_4V ) VEX_4V = getVEXRegisterEncoding ( MI , CurOp ++ ) ; const MachineOperand & MO = MI . getOperand ( CurOp ) ; if ( MO . isReg ( ) && <STR_LIT> ( MO . getReg ( ) ) ) VEX_R = <NUM_LIT> ; break ; } case <STR_LIT> : if ( <STR_LIT> ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ) VEX_R = <NUM_LIT> ; if ( HasVEX_4V ) VEX_4V = getVEXRegisterEncoding ( MI , <NUM_LIT> ) ; if ( <STR_LIT> ( MI . getOperand ( MemOperand + <STR_LIT> ) . getReg ( ) ) ) VEX_B = <NUM_LIT> ; if ( <STR_LIT> ( MI . getOperand ( MemOperand + <STR_LIT> ) . getReg ( ) ) ) VEX_X = <NUM_LIT> ; if ( HasVEX_4VOp3 ) VEX_4V = getVEXRegisterEncoding ( MI , <STR_LIT> + <NUM_LIT> ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case


<s> const TargetInstrInfo * TII = MF . getSubtarget ( ) . getInstrInfo ( ) ; <ISA_LIT>MachineFunctionInfo * ZFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; bool IsVarArg = MF . getFunction ( ) . isVarArg ( ) ; DebugLoc DL ; <STR_LIT> SpillGPRs = ZFI -> getSpillGPRRegs ( ) ; if ( SpillGPRs . LowGPR ) { assert ( SpillGPRs . LowGPR != SpillGPRs . HighGPR && <STR_LIT> ) ; MachineInstrBuilder MIB = BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) ) ; addSavedGPR ( MBB , MIB , SpillGPRs . LowGPR , false ) ; addSavedGPR ( MBB , MIB , SpillGPRs . HighGPR , false ) ; MIB . addReg ( <STR_LIT> ) . addImm ( SpillGPRs . GPROffset ) ; for ( unsigned I = <NUM_LIT> , E = CSI . size ( ) ; I != E ; ++ I ) { unsigned Reg = CSI [ I ] . getReg ( ) ; if ( <STR_LIT> . contains ( Reg ) ) addSavedGPR ( MBB , MIB , Reg , true ) ; } if ( IsVarArg ) for ( unsigned I = ZFI -> getVarArgsFirstGPR ( ) ; I < <STR_LIT> ; ++ I ) addSavedGPR (


<s> case <STR_LIT> : return getRegBank ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return getRegBank ( <STR_LIT> ) ; case <STR_LIT>


<s> int64_t Offset = MFI -> getObjectOffset ( Info . getFrameIdx ( ) ) - getOffsetOfLocalArea ( ) + saveAreaOffset ; if ( HasFP && ( FramePtr == Reg || Reg == <STR_LIT> ) ) { TotalSkipped += stackGrowth ; continue ; } unsigned DwarfReg = MRI -> getDwarfRegNum ( Reg , true ) ; unsigned CFIIndex = MMI . addFrameInst ( MCCFIInstruction :: createOffset ( nullptr , DwarfReg , Offset - TotalSkipped ) ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( TargetOpcode :: CFI_INSTRUCTION )


<s> bool CPChange = false ; for ( unsigned i = <NUM_LIT> , e = CPUsers . size ( ) ; i != e ; ++ i ) CPChange |= HandleConstantPoolUser ( MF , i ) ; if ( CPChange && ++ NoCPIters > <NUM_LIT> ) llvm_unreachable ( <STR_LIT> ) ; DEBUG ( dumpBBs ( ) ) ; NewWaterList . clear ( ) ; bool BRChange = false ; for ( unsigned i = <NUM_LIT> , e = ImmBranches . size ( ) ; i != e ; ++ i ) BRChange |= FixUpImmediateBr ( MF , ImmBranches [ i ] ) ; if ( BRChange && ++ NoBRIters > <NUM_LIT> ) llvm_unreachable ( <STR_LIT> ) ; DEBUG ( dumpBBs ( ) ) ; if ( ! CPChange && ! BRChange ) break ; MadeChange = true ; } if ( isThumb2 && ! STI -> prefers32BitThumb ( ) ) MadeChange |= OptimizeThumb2Instructions ( MF ) ; verify ( MF ) ; if ( isThumb && ! HasFarJump && AFI -> isLRSpilledForFarJump ( ) ) MadeChange |= UndoLRSpillRestore ( ) ; DEBUG ( errs ( ) << '\n' ; dumpBBs ( ) ) ; BBSizes . clear ( ) ; BBOffsets . clear ( ) ; WaterList . clear ( ) ; CPUsers . clear (


<s> RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; add_reg_note ( insn , REG_CFA_REGISTER , gen_rtx_SET ( VOIDmode , gen_rtx_REG ( Pmode , RETURN_ADDR_REGNUM ) , gen_rtx_REG ( Pmode , INCOMING_RETURN_ADDR_REGNUM ) ) ) ; add_reg_note ( insn ,


<s> unsigned PredI = ( OpI > - <NUM_LIT> ) ? MII -> getOperand ( OpI ) . getReg ( ) : <NUM_LIT> , PredJ = ( OpJ > - <NUM_LIT> ) ? MIJ -> getOperand ( OpJ ) . getReg ( ) : <NUM_LIT> ; if ( PredI != PredJ ) return false ; if ( SUJ -> isSucc ( SUI ) ) { for ( unsigned i = <NUM_LIT> , e = SUJ -> Succs . size ( ) ; i < e ;


<s> <STR_LIT> CC = ( <STR_LIT> ) MI -> getOperand ( OpNo ) . getImm ( ) ; O << <ISA_LIT>CCToString (


<s> rtx addr = XEXP ( m_tramp , <NUM_LIT> ) ; emit_move_insn ( gen_rtx_MEM ( SImode , plus_constant ( Pmode , addr , <NUM_LIT> ) ) , plus_constant ( SImode , expand_shift ( RSHIFT_EXPR , SImode , fnaddr , <NUM_LIT> , NULL_RTX , <NUM_LIT> ) , <NUM_LIT> ) ) ; emit_move_insn ( gen_rtx_MEM ( SImode , plus_constant ( Pmode , addr , <NUM_LIT> ) ) , plus_constant ( SImode , expand_and ( SImode , fnaddr , GEN_INT ( <NUM_LIT> ) , NULL_RTX ) , <NUM_LIT> ) ) ; emit_move_insn ( gen_rtx_MEM ( SImode , plus_constant ( Pmode , addr , <NUM_LIT> ) ) , plus_constant ( SImode , expand_shift ( RSHIFT_EXPR , SImode , static_chain , <NUM_LIT> , NULL_RTX , <NUM_LIT> ) , <NUM_LIT> ) ) ; emit_move_insn ( gen_rtx_MEM ( SImode , plus_constant ( Pmode , addr , <NUM_LIT> ) ) , gen_int_mode ( <NUM_LIT> , SImode ) ) ; emit_move_insn ( gen_rtx_MEM ( SImode , plus_constant ( Pmode , addr , <NUM_LIT> ) ) , plus_constant ( SImode , expand_and ( SImode , static_chain , GEN_INT ( <NUM_LIT> ) , NULL_RTX ) , <NUM_LIT> ) ) ; emit_library_call ( set_trampoline_parity_libfunc , LCT_NORMAL , VOIDmode , <NUM_LIT>


<s> static DecodeStatus DecodeVecShiftR16Imm ( MCInst & Inst , unsigned Imm , uint64_t Addr , const void * Decoder ) { return DecodeVecShiftRImm ( Inst , Imm , <NUM_LIT>


<s> SDVTList Tys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SDValue LO , HI ; SDValue Chain = DAG . getCopyToReg ( N -> getOperand ( <NUM_LIT> ) , DL , <STR_LIT> , N -> getOperand ( <NUM_LIT> ) ) ; SDValue rd = DAG . getNode ( <STR_LIT> , DL , Tys , Chain ) ; if ( Subtarget . is64Bit ( ) ) { LO = DAG . getCopyFromReg ( rd , DL , <STR_LIT> , <STR_LIT> , rd . getValue ( <NUM_LIT> ) ) ; HI = DAG . getCopyFromReg ( LO . getValue ( <NUM_LIT> ) , DL , <STR_LIT> , <STR_LIT> , LO . getValue ( <NUM_LIT> ) ) ; } else { LO = DAG . getCopyFromReg ( rd , DL , <STR_LIT> , <STR_LIT> , rd . getValue ( <NUM_LIT> ) ) ; HI = DAG . getCopyFromReg ( LO . getValue ( <NUM_LIT> ) , DL , <STR_LIT> , <STR_LIT> , LO . getValue ( <NUM_LIT> ) ) ; } Chain = HI . getValue ( <NUM_LIT> ) ; if ( Subtarget . is64Bit ( ) ) { SDValue Tmp = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , HI , DAG .

getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ;


<s> void <ISA_LIT>CFGStackify :: rewriteDepthImmediates ( MachineFunction & MF ) { const auto & TII = * MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getInstrInfo ( ) ; SmallVector < const MachineBasicBlock * , <NUM_LIT> > Stack ; SmallVector < const MachineBasicBlock * , <NUM_LIT> > EHPadStack ; for ( auto & MBB : reverse ( MF ) ) { for ( auto I = MBB . rbegin ( ) , E = MBB . rend ( ) ; I != E ; ++ I ) { MachineInstr & MI = * I ; switch ( MI . getOpcode ( ) ) { case <STR_LIT> : assert ( ScopeTops [ Stack . back ( ) -> getNumber ( ) ] -> getNumber ( ) <= MBB . getNumber ( ) && <STR_LIT> ) ; Stack . pop_back ( ) ; break ; case <STR_LIT> : assert ( ScopeTops [ Stack . back ( ) -> getNumber ( ) ] -> getNumber ( ) <= MBB . getNumber ( ) && <STR_LIT> ) ; Stack . pop_back ( ) ; EHPadStack . pop_back ( ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : EHPadStack . push_back ( & MBB ) ; break ; case <STR_LIT> : assert ( Stack . back ( ) == & MBB && <STR_LIT> ) ; Stack . pop_back ( ) ; break ; case <STR_LIT>


<s> } SrcC = decodeCField ( Insn ) ; DecodeGPR32RegisterClass ( Inst , SrcC , Address , Decoder ) ; LImm = ( Insn >> <NUM_LIT> ) ; Inst . addOperand ( MCOperand :: createImm ( LImm ) ) ; Inst . addOperand ( MCOperand :: createImm ( <NUM_LIT> ) ) ; return MCDisassembler :: Success


<s> void <ISA_LIT>InstPrinter :: printRegName ( raw_ostream & OS , unsigned RegNo )


<s> if ( NumLanes == <NUM_LIT> ) NumLanes = <NUM_LIT> ; unsigned NumLaneElts = NumElts / NumLanes ; for ( unsigned l = <NUM_LIT> ; l != NumElts ; l += NumLaneElts ) { for ( unsigned i = l , e = l + NumLaneElts / <NUM_LIT> ; i != e ; ++ i ) { ShuffleMask . push_back (


<s> assert ( <NUM_LIT> && <STR_LIT> ) ; unsigned GlobalBaseReg = getInstrInfo ( ) -> getGlobalBaseReg ( MF ) ; return CurDAG -> getRegister ( GlobalBaseReg , TLI . getPointerTy (


<s> void <ISA_LIT>AsmPrinter :: printOperand ( const MachineInstr * MI , int opNum , raw_ostream & O ) { const DataLayout & DL = getDataLayout ( ) ; const MachineOperand & MO = MI -> getOperand ( opNum ) ; <ISA_LIT>MCExpr :: VariantKind TF = ( <ISA_LIT>MCExpr :: VariantKind ) MO . getTargetFlags ( ) ; if ( MO . isGlobal ( ) || MO . isSymbol ( ) || MO . isCPI ( ) ) { if ( MI -> getOpcode ( ) == <STR_LIT> ) assert ( TF == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None && <STR_LIT> ) ; else if ( MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> ) assert ( ( TF == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_HI || TF == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_H44 || TF == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_HH || TF == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_GD_HI22 || TF == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_LDM_HI22 || TF == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_LDO_HIX22 || TF == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_IE_HI22 || TF == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_LE_HIX22 ) && <STR_LIT> ) ; else if ( MI -> getOpcode ( ) == <STR_LIT> ) assert ( ( TF == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None || TF == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_GD_CALL || TF == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_LDM_CALL ) && <STR_LIT> ) ; else if ( MI -> getOpcode ( ) == <STR_LIT> ) assert ( ( TF == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_GD_ADD || TF == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_LDM_ADD || TF == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_LDO_ADD || TF == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_IE_ADD ) && <STR_LIT> ) ; else if ( MI -> getOpcode ( ) == <STR_LIT> ) assert ( TF == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_IE_LD && <STR_LIT> ) ; else if ( MI -> getOpcode ( ) == <STR_LIT> ) assert ( TF == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_IE_LDX && <STR_LIT> ) ; else if ( MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> ) assert ( ( TF == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_LDO_LOX10 || TF == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_LE_LOX10 ) && <STR_LIT> ) ; else assert ( ( TF == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_LO || TF == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_M44 || TF == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_L44 || TF == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_HM || TF == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_GD_LO10 || TF == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_LDM_LO10 || TF == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_IE_LO10 ) && <STR_LIT> ) ; } bool CloseParen = <ISA_LIT>MCExpr :: printVariantKind ( O , TF ) ; switch ( MO . getType ( ) ) { case MachineOperand :: MO_Register : O << <STR_LIT> << StringRef ( getRegisterName ( MO . getReg ( ) ) ) . lower ( ) ; break ; case MachineOperand :: MO_Immediate : O << ( int ) MO . getImm ( ) ; break ; case MachineOperand :: MO_MachineBasicBlock : MO . getMBB ( ) -> getSymbol ( ) -> print ( O , MAI ) ; return ; case MachineOperand :: MO_GlobalAddress : PrintSymbolOperand ( MO , O ) ; break ; case MachineOperand :: MO_BlockAddress : O << GetBlockAddressSymbol ( MO . getBlockAddress ( )


<s> Reg = getReg ( Decoder , <STR_LIT> , Reg ) ; Inst . addOperand ( MCOperand :: createReg ( Reg ) ) ; Inst . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ; Inst . addOperand ( MCOperand :: createImm ( Offset << <NUM_LIT> ) ) ; return MCDisassembler ::


<s> for ( unsigned i = Inst -> getNumOperands ( ) - <NUM_LIT> ; i > <NUM_LIT> ; -- i ) { MachineOperand & Op = Inst -> getOperand ( i ) ; if ( Op . isReg ( ) && Op . getReg ( ) == AMDGPU :: SCC ) Inst -> RemoveOperand ( i ) ; } if ( Opcode == AMDGPU :: S_SEXT_I32_I8 || Opcode == AMDGPU :: S_SEXT_I32_I16 ) { unsigned Size = ( Opcode == AMDGPU :: S_SEXT_I32_I8 ) ? <NUM_LIT> : <NUM_LIT> ; Inst -> addOperand ( MachineOperand :: CreateImm ( <NUM_LIT> ) ) ; Inst -> addOperand ( MachineOperand :: CreateImm ( Size ) ) ; } else if ( Opcode == AMDGPU :: S_BCNT1_I32_B32 ) { Inst -> addOperand ( MachineOperand :: CreateImm ( <NUM_LIT> ) ) ; } addDescImplicitUseDef ( NewDesc , Inst ) ; if ( Opcode == AMDGPU :: S_BFE_I32 || Opcode == AMDGPU :: S_BFE_U32 ) { const MachineOperand & OffsetWidthOp = Inst -> getOperand ( <NUM_LIT> ) ; assert ( OffsetWidthOp . isImm ( ) && <STR_LIT> ) ; uint32_t Imm = OffsetWidthOp . getImm ( ) ; uint32_t Offset = Imm & <NUM_LIT> ; uint32_t BitWidth = ( Imm & <NUM_LIT> ) >> <NUM_LIT> ; Inst -> RemoveOperand ( <NUM_LIT> ) ; Inst -> addOperand ( MachineOperand :: CreateImm ( Offset ) ) ; Inst -> addOperand ( MachineOperand :: CreateImm ( BitWidth ) ) ; } const TargetRegisterClass * NewDstRC = getOpRegClass ( * Inst , <NUM_LIT> ) ; switch ( Opcode ) { case AMDGPU :: COPY : case AMDGPU :: PHI : case AMDGPU :: REG_SEQUENCE : case AMDGPU :: INSERT_SUBREG : if ( RI . hasVGPRs ( NewDstRC ) ) continue ; NewDstRC = RI . getEquivalentVGPRClass ( NewDstRC ) ; if ( ! NewDstRC ) continue ; break ; default : break ; } unsigned DstReg = Inst -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned NewDstReg = MRI . createVirtualRegister ( NewDstRC ) ; MRI . replaceRegWith ( DstReg ,


<s> if ( ! A ) return nullptr ; } return <ISA_LIT>GenRegisterInfo :: getMatchingSuperRegClass ( A ,


<s> return ( Reg >= <STR_LIT> && Reg <= <STR_LIT> ) || ( Reg


<s> TargetPassConfig :: addCodeGenPrepare


<s> } if ( ! EarlyTermInstrs . empty ( ) ) { MachineBasicBlock * EarlyExitBlock = MF . CreateMachineBasicBlock ( ) ; DebugLoc DL ; MF . insert ( MF . end ( ) , EarlyExitBlock ) ; BuildMI ( * EarlyExitBlock , EarlyExitBlock -> end ( ) , DL , TII -> get ( MovOpc ) , ExecReg ) . addImm ( <NUM_LIT> ) ; generateEndPgm ( * EarlyExitBlock , EarlyExitBlock -> end ( ) , DL , TII , MF ) ; for ( MachineInstr * Instr : EarlyTermInstrs ) { if ( MF . getFunction ( ) . getCallingConv ( ) != CallingConv :: <ISA_LIT>_GS ) earlyTerm ( * Instr , EarlyExitBlock ) ; Instr -> eraseFromParent ( ) ; } EarlyTermInstrs . clear ( ) ; MadeChange = true ; } if ( ! EpilogInstrs . empty ( ) ) { MachineBasicBlock * EmptyMBBAtEnd = nullptr ; assert ( ! MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) -> returnsVoid ( ) ) ; if ( EpilogInstrs . size ( ) > <NUM_LIT> ) { EmptyMBBAtEnd = MF . CreateMachineBasicBlock ( ) ; MF . insert ( MF . end ( ) , EmptyMBBAtEnd ) ; } for ( auto MI : EpilogInstrs ) { auto MBB = MI -> getParent ( ) ; if ( MBB == & MF . back ( ) && MI == & MBB -> back ( ) ) continue ; if ( ! EmptyMBBAtEnd ) { EmptyMBBAtEnd = MF . CreateMachineBasicBlock ( ) ; MF . insert ( MF . end ( ) , EmptyMBBAtEnd ) ; } MBB -> addSuccessor ( EmptyMBBAtEnd ) ; MDT -> getBase ( ) . insertEdge ( MBB , EmptyMBBAtEnd ) ; BuildMI ( * MBB , MI , MI -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addMBB ( EmptyMBBAtEnd ) ; MI -> eraseFromParent (


<s> NewMIs . push_back ( addFrameReference ( BuildMI ( MF , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) , FrameIdx ) ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) || <STR_LIT> . hasSubClassEq ( RC ) ) { NewMIs . push_back ( addFrameReference ( BuildMI ( MF , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) , FrameIdx ) ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { NewMIs . push_back ( addFrameReference ( BuildMI ( MF , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) , FrameIdx ) ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { NewMIs . push_back ( addFrameReference ( BuildMI ( MF , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) , FrameIdx ) ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { NewMIs . push_back ( addFrameReference ( BuildMI ( MF , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) , FrameIdx ) ) ; return true ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { NewMIs . push_back ( addFrameReference ( BuildMI ( MF , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) , FrameIdx ) ) ; return true ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { NewMIs . push_back ( addFrameReference ( BuildMI ( MF , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg


<s> break ; case <STR_LIT> : if ( <ISA_LIT>ScalarSSEf64 ) { Opc = HasAVX512 ? <STR_LIT> : HasAVX ? <STR_LIT> : <STR_LIT> ; RC = & <STR_LIT> ; } else { Opc = <STR_LIT> ; RC = & <STR_LIT> ; } break ; case <STR_LIT> : return false ; case <STR_LIT> : if ( IsNonTemporal && Alignment >= <NUM_LIT> && HasSSE41 ) Opc = HasVLX ? <STR_LIT> : HasAVX ? <STR_LIT> : <STR_LIT> ; else if ( Alignment >= <NUM_LIT> ) Opc = HasVLX ? <STR_LIT> : HasAVX ? <STR_LIT> : <STR_LIT> ; else Opc = HasVLX ? <STR_LIT> : HasAVX ? <STR_LIT> : <STR_LIT> ; RC = & <STR_LIT> ; break ; case <STR_LIT> : if ( IsNonTemporal && Alignment >= <NUM_LIT> && HasSSE41 ) Opc = HasVLX ? <STR_LIT> : HasAVX ? <STR_LIT> : <STR_LIT> ; else if ( Alignment >= <NUM_LIT> ) Opc = HasVLX ? <STR_LIT> : HasAVX ? <STR_LIT> : <STR_LIT> ; else Opc = HasVLX ? <STR_LIT> : HasAVX ? <STR_LIT> : <STR_LIT> ; RC = & <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( IsNonTemporal && Alignment >= <NUM_LIT> ) Opc = HasVLX ? <STR_LIT> : HasAVX ? <STR_LIT> : <STR_LIT> ; else if ( Alignment >= <NUM_LIT> ) Opc = HasVLX ? <STR_LIT> : HasAVX ? <STR_LIT> : <STR_LIT> ; else Opc = HasVLX ? <STR_LIT> : HasAVX ? <STR_LIT> : <STR_LIT> ; RC = & <STR_LIT> ; break ; case <STR_LIT> : assert ( HasAVX ) ; if ( IsNonTemporal && Alignment >= <NUM_LIT> && HasAVX2 ) Opc = HasVLX ? <STR_LIT> : <STR_LIT> ; else if ( Alignment >= <NUM_LIT> ) Opc = HasVLX ? <STR_LIT> : <STR_LIT> ; else Opc = HasVLX ? <STR_LIT> : <STR_LIT> ; RC = & <STR_LIT> ; break ; case <STR_LIT> : assert ( HasAVX ) ; if ( IsNonTemporal && Alignment >= <NUM_LIT> && HasAVX2 ) Opc = <STR_LIT> ; else if ( Alignment >= <NUM_LIT> ) Opc = HasVLX ? <STR_LIT> : <STR_LIT> ; else Opc = HasVLX ? <STR_LIT> : <STR_LIT> ; RC = &


<s> bool <ISA_LIT>AsmBackend :: mayNeedRelaxation ( const MCInst & Inst , const MCSubtargetInfo &


<s> const MachineBasicBlock * MBB = MI . getParent ( ) ; MachineBasicBlock :: const_instr_iterator MII = MI . getIterator ( ) ; for ( ++ MII ; MII != MBB -> instr_end ( ) && MII -> isInsideBundle ( ) ; ++ MII ) if ( TargetInstrInfo :: hasStoreToStackSlot ( * MII , MMO , FrameIndex ) ) return true ; return false ; } return TargetInstrInfo :: hasStoreToStackSlot ( MI , MMO


<s> TargetRegistry :: RegisterMCObjectStreamer ( The<ISA_LIT>Target , create<ISA_LIT>MCObjStreamer ) ; TargetRegistry :: RegisterMCInstrInfo ( The<ISA_LIT>Target , create<ISA_LIT>MCInstrInfo ) ; TargetRegistry :: RegisterMCRegInfo ( The<ISA_LIT>Target


<s> return Kind == Register && ( Reg . IsForcedVOP3 || Reg .


<s> HasFRSQRTE = false ; HasFRSQRTES = false ; HasRecipPrec = false ; HasSTFIWX = false ; HasLFIWAX = false ; HasFPRND = false ; HasFPCVT = false ; HasISEL = false ; HasPOPCNTD = false ; HasBPERMD = false ; HasExtDiv = false ; HasCMPB = false ; HasLDBRX = false ; IsBookE = false ; HasOnlyMSYNC = false ; Is<ISA_LIT>4xx = false ; Is<ISA_LIT>6xx = false ; IsE500 = false ; FeatureMFTB = false ; DeprecatedDST = false ; HasLazyResolverStubs = false ; HasICBT = false ; HasInvariantFunctionDescriptors = false ; HasPartwordAtomics = false ; HasDirectMove = false ; IsQPXStackUnaligned = false ; HasHTM = false ; HasFusion = false ; HasFloat128 =


<s> } if ( save_fp_p ) { reg = gen_rtx_REG ( SImode , FP_REGNUM ) ; mem = gen_frame_mem ( SImode , plus_constant ( Pmode , stack_pointer_rtx , offset ) ) ; pop_rtx = gen_rtx_SET ( reg , mem ) ; XVECEXP ( parallel_insn , <NUM_LIT> , par_index ) = pop_rtx ; RTX_FRAME_RELATED_P ( pop_rtx ) = <NUM_LIT> ; offset = offset + <NUM_LIT> ; par_index ++ ; dwarf = alloc_reg_note ( REG_CFA_RESTORE , reg , dwarf ) ; } if ( save_gp_p ) { reg = gen_rtx_REG ( SImode , GP_REGNUM ) ; mem = gen_frame_mem ( SImode , plus_constant ( Pmode , stack_pointer_rtx , offset ) ) ; pop_rtx = gen_rtx_SET ( reg , mem ) ; XVECEXP ( parallel_insn , <NUM_LIT> , par_index ) = pop_rtx ; RTX_FRAME_RELATED_P ( pop_rtx ) = <NUM_LIT> ; offset = offset + <NUM_LIT> ; par_index ++ ; dwarf = alloc_reg_note ( REG_CFA_RESTORE , reg , dwarf ) ; } if ( save_lp_p ) { reg = gen_rtx_REG ( SImode , LP_REGNUM ) ; mem = gen_frame_mem ( SImode , plus_constant ( Pmode , stack_pointer_rtx , offset ) ) ; pop_rtx = gen_rtx_SET ( reg , mem ) ; XVECEXP ( parallel_insn , <NUM_LIT>


<s> if ( ! TARGET_POWERPC64 ) { rtx hi , lo ; hi = operand_subword_force ( copy_rtx ( dest ) , WORDS_BIG_ENDIAN == <NUM_LIT> , DImode ) ; lo = operand_subword_force ( dest , WORDS_BIG_ENDIAN != <NUM_LIT> , DImode ) ; emit_move_insn ( hi , GEN_INT ( c >> <NUM_LIT> ) ) ; c = ( ( c & <NUM_LIT> ) ^ <NUM_LIT> ) - <NUM_LIT> ; emit_move_insn ( lo , GEN_INT ( c ) ) ; } else rs6000_emit_set_long_const ( dest , c ) ; break ; default : gcc_unreachable ( ) ; } insn = get_last_insn ( ) ; set = single_set ( insn ) ; if ( ! CONSTANT_P ( SET_SRC ( set ) ) ) set_unique_reg_note


<s> SDValue <ISA_LIT>TargetLowering :: LowerToBT ( SDValue Op , <STR_LIT> CC , const SDLoc & dl , SelectionDAG & DAG ) const { if ( Op . getOpcode ( ) == <STR_LIT> ) return LowerAndToBT ( Op , CC , dl , DAG ) ; if ( Op . getOpcode ( ) == <STR_LIT> && Op . getValueType ( ) == <STR_LIT> ) return LowerTruncateToBT (


<s> unsigned Complexity = <NUM_LIT> ; if ( AM . BaseType == <ISA_LIT>ISelAddressMode :: RegBase ) if ( AM . Base . Reg . getNode ( ) ) Complexity = <NUM_LIT> ; else AM . Base . Reg = CurDAG -> getRegister ( <NUM_LIT> , VT ) ; else if ( AM . BaseType == <ISA_LIT>ISelAddressMode :: FrameIndexBase ) Complexity = <NUM_LIT> ; if ( AM . IndexReg . getNode ( ) ) Complexity ++ ; else AM . IndexReg = CurDAG -> getRegister ( <NUM_LIT> , VT ) ; if ( AM . Scale > <NUM_LIT> ) Complexity ++ ; if ( AM . hasSymbolicDisplacement ( ) ) { if ( Subtarget -> is64Bit ( ) ) Complexity = <NUM_LIT> ; else Complexity +=


<s> if ( ( ( FlagI . getOpcode ( ) == <STR_LIT> && OI . getOpcode ( ) == <STR_LIT> ) || ( FlagI . getOpcode ( ) == <STR_LIT> && OI . getOpcode ( ) == <STR_LIT> ) || ( FlagI . getOpcode ( ) == <STR_LIT> && OI . getOpcode ( ) == <STR_LIT> ) || ( FlagI . getOpcode ( ) == <STR_LIT> && OI . getOpcode ( ) == <STR_LIT> ) ) && ( ( OI . getOperand ( <NUM_LIT> ) . getReg ( ) == SrcReg && OI . getOperand ( <NUM_LIT> ) . getReg ( ) == SrcReg2 ) || ( OI . getOperand ( <NUM_LIT> ) . getReg ( ) == SrcReg2 && OI . getOperand ( <NUM_LIT> ) . getReg ( ) == SrcReg ) ) ) return true ; if ( ImmMask != <NUM_LIT> && ( ( FlagI . getOpcode ( ) == <STR_LIT> && OI . getOpcode ( ) == <STR_LIT> ) || ( FlagI . getOpcode ( ) == <STR_LIT> && OI . getOpcode ( ) == <STR_LIT> ) || ( FlagI . getOpcode ( ) == <STR_LIT> && OI . getOpcode ( ) == <STR_LIT> ) || ( FlagI . getOpcode ( ) == <STR_LIT> && OI . getOpcode ( ) == <STR_LIT> ) || ( FlagI . getOpcode ( ) == <STR_LIT> && OI . getOpcode ( ) == <STR_LIT> ) || ( FlagI . getOpcode ( ) == <STR_LIT> && OI . getOpcode ( ) == <STR_LIT> ) || ( FlagI . getOpcode ( ) == <STR_LIT> && OI . getOpcode ( ) == <STR_LIT> ) ) && OI . getOperand ( <NUM_LIT> ) . getReg ( ) == SrcReg && OI . getOperand ( <NUM_LIT> ) . getImm ( ) == ImmValue ) return true ; return false


<s> printGVStub ( ( * I ) -> getNameStart ( ) , <STR_LIT> ) ; } } if ( ! InStubSection && ! GVStubs . empty ( ) ) SwitchToDataSection ( <STR_LIT> ) ; for ( StringSet < > :: iterator i = GVStubs . begin ( ) , e = GVStubs . end ( ) ; i != e ; ++ i ) printGVStub ( i -> getKeyData ( ) ) ; if ( ! HiddenGVStubs . empty ( ) ) { SwitchToSection ( TAI -> getDataSection ( ) ) ; for ( StringSet < > :: iterator i = HiddenGVStubs . begin ( ) , e = HiddenGVStubs . end ( ) ; i != e ; ++ i ) printHiddenGVStub ( i -> getKeyData ( ) ) ; } DwarfWriter * DW = getAnalysisIfAvailable < DwarfWriter > ( ) ; DW -> EndModule ( ) ; O << <STR_LIT> ; } else if ( Subtarget -> isTargetCygMing ( ) ) { for ( StringSet < > :: iterator i = FnStubs . begin ( ) , e = FnStubs . end ( ) ; i != e ; ++ i ) { O << <STR_LIT> << i -> getKeyData ( ) << <STR_LIT> << COFF :: C_EXT << <STR_LIT> << ( COFF :: DT_FCN << COFF :: N_BTSHFT ) << <STR_LIT> ; } DwarfWriter * DW = getAnalysisIfAvailable < DwarfWriter > ( ) ; DW -> EndModule ( ) ; } else if ( Subtarget -> isTargetELF ( ) ) { DwarfWriter * DW = getAnalysisIfAvailable < DwarfWriter > ( ) ; DW -> EndModule ( ) ; } return AsmPrinter :: doFinalization


<s> void <ISA_LIT>VectorLoopCarriedReuse :: findValueToReuse ( ) { for ( auto * D : Dependences ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * ( D -> front ( ) ) << <STR_LIT> ) ; if ( D -> iterations ( ) > <ISA_LIT>VLCRIterationLim ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; continue ; } PHINode * PN = cast < PHINode > ( D -> front ( ) ) ; Instruction * BEInst = D -> back ( ) ; int Iters = D -> iterations ( ) ; BasicBlock * BB = PN -> getParent ( ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * PN << <STR_LIT> ) ; SmallVector < Instruction * , <NUM_LIT> > PNUsers ; for ( auto UI = PN -> use_begin ( ) , E = PN -> use_end ( ) ; UI != E ; ++ UI ) { Use & U = * UI ; Instruction * User = cast < Instruction > ( U . getUser ( ) ) ; if ( User -> getParent ( ) != BB ) continue ; if ( ReplacedInsts . count ( User ) ) { LLVM_DEBUG ( dbgs ( ) << * User << <STR_LIT> ) ; continue ; } if ( isa < PHINode > ( User ) ) continue ; if ( User -> mayHaveSideEffects ( ) ) continue ; if ( ! canReplace ( User ) ) continue ; PNUsers . push_back ( User ) ; } LLVM_DEBUG ( dbgs ( ) << PNUsers . size ( ) << <STR_LIT> ) ; for ( Instruction * I : PNUsers ) { for ( auto UI = BEInst -> use_begin ( ) , E = BEInst -> use_end ( ) ; UI != E ; ++ UI ) { Use & U = * UI ; Instruction * BEUser = cast < Instruction > ( U . getUser ( ) ) ; if ( BEUser -> getParent ( ) != BB ) continue ; if ( ! isEquivalentOperation ( I , BEUser ) ) continue ; int NumOperands = I -> getNumOperands ( ) ; for ( int OpNo = <NUM_LIT> ; OpNo < NumOperands ; ++ OpNo ) { Value * Op = I -> getOperand ( OpNo ) ; Value * BEOp = BEUser -> getOperand ( OpNo ) ; Instruction * OpInst = dyn_cast < Instruction > ( Op ) ; if ( ! OpInst ) { if ( Op == BEOp ) continue ; BEUser = nullptr ; break ; } Instruction * BEOpInst = dyn_cast < Instruction > ( BEOp ) ; if ( ! isDepChainBtwn ( OpInst , BEOpInst , Iters ) ) { BEUser = nullptr ; break ; } } if ( BEUser ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; ReuseCandidate . Inst2Replace = I ; ReuseCandidate . BackedgeInst