<s> while ( ! MI . getOperand ( FIOperandNo ) . isFI ( ) ) { ++ FIOperandNo ; assert ( FIOperandNo != MI . getNumOperands ( ) && <STR_LIT> ) ; } unsigned OffsetOperandNo = ( FIOperandNo == <NUM_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; if ( MI . isInlineAsm ( ) ) OffsetOperandNo = FIOperandNo - <NUM_LIT> ; int FrameIndex = MI . getOperand ( FIOperandNo ) . getIndex ( ) ; <ISA_LIT>FunctionInfo * FI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; int FPSI = FI -> getFramePointerSaveIndex ( ) ; unsigned OpC = MI . getOpcode ( ) ; if ( FPSI && FrameIndex == FPSI && ( OpC == <STR_LIT> || OpC == <STR_LIT> ) ) { lowerDynamicAlloc ( II , SPAdj , RS ) ; return ; } if ( requiresRegisterScavenging ( MF ) ) { if ( OpC == <STR_LIT> ) { lowerCRSpilling ( II , FrameIndex , SPAdj , RS ) ; return ; } else if ( OpC == <STR_LIT> ) { lowerCRRestore ( II , FrameIndex , SPAdj , RS ) ; return ; } } bool is64Bit = Subtarget . is<ISA_LIT>64 ( ) ; MI . getOperand ( FIOperandNo ) . ChangeToRegister ( TFI -> hasFP ( MF ) ? ( is64Bit ? <STR_LIT> : <STR_LIT> ) : ( is64Bit ? <STR_LIT> : <STR_LIT> ) , false ) ; bool isIXAddr = false ; switch ( OpC ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : isIXAddr = true ; break ; } int Offset = MFI -> getObjectOffset ( FrameIndex ) ; if ( ! isIXAddr ) Offset += MI . getOperand ( OffsetOperandNo ) . getImm ( ) ; else Offset += MI . getOperand ( OffsetOperandNo ) . getImm ( ) << <NUM_LIT> ; if ( ! MF . getFunction ( ) -> getFnAttributes ( ) . hasAttribute ( Attributes :: Naked ) ) Offset += MFI -> getStackSize ( ) ; if ( OpC == <STR_LIT> || ( isInt < <NUM_LIT> > ( Offset ) && ( ! isIXAddr || ( Offset & <NUM_LIT> ) == <NUM_LIT> ) ) ) { if ( isIXAddr ) Offset >>= <NUM_LIT> ; MI . getOperand ( OffsetOperandNo )


<s> return getTM < <ISA_LIT>TargetMachine >


<s> if ( BV -> isConstant ( ) && IndexWidth > <NUM_LIT> && DAG . ComputeNumSignBits ( Index ) > ( IndexWidth - <NUM_LIT> ) ) { unsigned NumElts = Index . getValueType ( ) . getVectorNumElements ( ) ; EVT NewVT = EVT :: getVectorVT ( * DAG . getContext ( ) , <STR_LIT> , NumElts ) ; Index = DAG . getNode ( <STR_LIT> , DL , NewVT , Index ) ; return rebuildGatherScatter ( GorS , Index , Base , Scale , DAG ) ; } } if ( ( Index . getOpcode ( ) == <STR_LIT> || Index . getOpcode ( ) == <STR_LIT> ) && IndexWidth > <NUM_LIT> && Index . getOperand ( <NUM_LIT> ) . getScalarValueSizeInBits ( ) <= <NUM_LIT> && DAG . ComputeNumSignBits ( Index ) > ( IndexWidth - <NUM_LIT> ) ) { unsigned NumElts = Index . getValueType ( ) . getVectorNumElements ( ) ; EVT NewVT = EVT :: getVectorVT ( * DAG . getContext ( ) , <STR_LIT> , NumElts ) ; Index = DAG . getNode ( <STR_LIT> , DL , NewVT , Index ) ; return rebuildGatherScatter ( GorS , Index , Base , Scale , DAG ) ; } } if ( DCI . isBeforeLegalizeOps ( ) ) { unsigned IndexWidth = Index . getScalarValueSizeInBits ( ) ; if ( IndexWidth != <NUM_LIT> && IndexWidth != <NUM_LIT> ) { MVT EltVT = IndexWidth > <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; EVT IndexVT = EVT :: getVectorVT ( * DAG . getContext ( ) , EltVT , Index . getValueType ( ) . getVectorNumElements ( ) ) ; Index = DAG . getSExtOrTrunc ( Index , DL , IndexVT ) ; return rebuildGatherScatter ( GorS , Index , Base , Scale , DAG ) ; } } SDValue Mask = GorS -> getMask ( ) ; if ( Mask . getScalarValueSizeInBits ( ) != <NUM_LIT> ) { const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; APInt DemandedMask ( APInt :: getSignMask ( Mask . getScalarValueSizeInBits ( ) ) ) ; if ( TLI . SimplifyDemandedBits ( Mask , DemandedMask , DCI ) ) { if ( N -> getOpcode ( ) != <STR_LIT> ) DCI . AddToWorklist ( N ) ; return SDValue ( N , <NUM_LIT> ) ; } } return SDValue (


<s> MCAsmParser & getParser ( ) const { return


<s> for ( i = <NUM_LIT> ; i < XVECLEN ( parallel , <NUM_LIT> ) ; ++ i ) { const_rtx x ; x = XEXP ( XVECEXP ( parallel , <NUM_LIT> , i ) , <NUM_LIT> ) ; if ( REG_P ( x ) && REGNO ( x ) == regno


<s> const <ISA_LIT>Subtarget * getSubtargetImpl ( ) const override { return &


<s> return D ( <STR_LIT> , R ( a ) , <STR_LIT>


<s> Rm |= fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ; if ( Rt == <NUM_LIT> || Rt2 == <NUM_LIT> || Rm == <NUM_LIT> ) S = MCDisassembler :: SoftFail ; if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rt , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rt2 , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeSPRRegisterClass ( Inst , Rm , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeSPRRegisterClass ( Inst , Rm +

<NUM_LIT> , Address , Decoder ) ) ) return MCDisassembler :: Fail ;


<s> static MachineBasicBlock * insertDivByZeroTrap ( MachineInstr & MI , MachineBasicBlock & MBB , const TargetInstrInfo & TII , bool Is64Bit , bool IsMicro<ISA_LIT> ) { if ( NoZeroDivCheck ) return & MBB ; MachineBasicBlock :: iterator I ( MI ) ; MachineInstrBuilder MIB ; MachineOperand & Divisor = MI . getOperand ( <NUM_LIT> ) ; MIB = BuildMI ( MBB , std :: next ( I ) , MI . getDebugLoc ( ) , TII . get ( IsMicro<ISA_LIT> ? <STR_LIT> : <STR_LIT> ) ) . addReg ( Divisor . getReg ( ) , getKillRegState ( Divisor . isKill ( ) )

) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ;


<s> void addTLSRegOperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT>


<s> return <STR_LIT> ; case VK_<ISA_LIT>_PCREL_LO : return <STR_LIT> ; case VK_<ISA_LIT>_PCREL_HI : return <STR_LIT> ; case VK_<ISA_LIT>_GOT_HI : return <STR_LIT> ; case VK_<ISA_LIT>_TPREL_LO : return <STR_LIT> ; case VK_<ISA_LIT>_TPREL_HI : return <STR_LIT> ; case VK_<ISA_LIT>_TPREL_ADD : return


<s> if ( STI . isTargetDarwin ( ) && CC == CallingConv :: CXX_FAST_TLS ) return CSR_iOS_CXX_TLS_RegMask ; return STI . isTargetDarwin (


<s> unsigned NormalizedIdxVal = ( ( ( IdxVal * ElVT . getSizeInBits ( ) ) / <NUM_LIT> ) * ElemsPerChunk ) ; SDValue VecIdx = DAG . getConstant ( NormalizedIdxVal , <STR_LIT> ) ; Result = DAG . getNode ( <STR_LIT> , dl


<s> const InstrItineraryData * getInstrItineraryData ( ) const override { return &


<s> return ( ( mode == HFmode && TARGET_SSE2 ) ?


<s> for ( MachineBasicBlock & MBB : * MF ) { for ( MachineInstr & MI : MBB ) { if ( isCRLogical ( MI ) ) { AllCRLogicalOps . push_back ( createCRLogicalOpInfo ( MI ) ) ; TotalCRLogicals ++ ; if ( AllCRLogicalOps . back ( ) . IsNullary ) TotalNullaryCRLogicals ++ ; else if ( AllCRLogicalOps . back ( ) . IsBinary ) TotalBinaryCRLogicals ++ ; else TotalUnaryCRLogicals


<s> return new yaml :: <ISA_LIT>MachineFunctionInfo (


<s> return ( uint32x2_t ) ( ( __a & __b ) != <NUM_LIT>


<s> rtx tmpconst ; int tmpwidth ; int retval = simd_valid_immediate ( op , mode , inverse , & tmpconst , & tmpwidth ) ; if ( retval < <NUM_LIT> || retval > <NUM_LIT> ) return <NUM_LIT> ; if ( modconst ) * modconst = tmpconst ; if ( elementwidth ) * elementwidth = tmpwidth ; return <NUM_LIT>


<s> void CopyPropagation :: recordCopy ( NodeAddr < StmtNode * > SA , EqualityMap


<s> unsigned align = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; if ( size == <NUM_LIT> ) { if ( align == <NUM_LIT> ) return MCDisassembler :: Fail ; align = <NUM_LIT> ; } else { if ( size == <NUM_LIT> ) { align *= <NUM_LIT> ; } else { size = <NUM_LIT> << size ; align *= <NUM_LIT> * size ; } } if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , Rd , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , ( Rd + inc ) % <NUM_LIT> , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , ( Rd + <NUM_LIT> * inc ) % <NUM_LIT> , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , ( Rd + <NUM_LIT> * inc


<s> NEONRegSpacing RegSpc = TableEntry -> RegSpacing ; unsigned NumRegs = TableEntry -> NumRegs ; MachineInstrBuilder MIB = BuildMI ( MBB , MBBI , MI . getDebugLoc ( ) , TII -> get ( TableEntry -> RealOpc ) ) ; unsigned OpIdx = <NUM_LIT> ; bool DstIsDead = MI . getOperand ( OpIdx ) . isDead ( ) ; unsigned DstReg = MI . getOperand ( OpIdx ++ ) . getReg ( ) ; unsigned D0 , D1 , D2 , D3 ; GetDSubRegs ( DstReg , RegSpc , TRI , D0 , D1 , D2 , D3 ) ; MIB . addReg ( D0 , RegState :: Define | getDeadRegState ( DstIsDead ) ) . addReg ( D1 , RegState :: Define | getDeadRegState ( DstIsDead ) ) ; if ( NumRegs > <NUM_LIT> ) MIB . addReg ( D2 , RegState :: Define | getDeadRegState ( DstIsDead ) ) ; if ( NumRegs > <NUM_LIT> ) MIB . addReg ( D3 , RegState :: Define | getDeadRegState ( DstIsDead ) ) ; if ( TableEntry -> HasWriteBack ) MIB . addOperand ( MI . getOperand ( OpIdx ++ ) ) ; MIB . addOperand ( MI . getOperand ( OpIdx ++ ) ) ; MIB . addOperand ( MI . getOperand ( OpIdx ++ ) ) ; if ( TableEntry -> HasWriteBack ) MIB . addOperand ( MI . getOperand ( OpIdx ++ ) ) ; unsigned SrcOpIdx = <NUM_LIT> ; if ( RegSpc == EvenDblSpc || RegSpc == OddDblSpc ) SrcOpIdx = OpIdx ++ ; MIB . addOperand ( MI . getOperand ( OpIdx ++ ) ) ; MIB . addOperand ( MI . getOperand ( OpIdx ++ ) ) ; if ( SrcOpIdx != <NUM_LIT> ) { MachineOperand MO = MI . getOperand ( SrcOpIdx ) ; MO . setImplicit ( true


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ! hasShiftedReg ( Second ) ; } } } if ( Subtarget . hasArithmeticCbzFusion ( ) ) { unsigned SecondOpcode = Second . getOpcode ( ) ; if ( SecondOpcode == <STR_LIT> || SecondOpcode == <STR_LIT> || SecondOpcode == <STR_LIT> || SecondOpcode == <STR_LIT> ) { switch ( First . getOpcode ( ) ) { default : return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case


<s> t = build2 ( BIT_AND_EXPR , integer_type_node , t , build_int_cst ( integer_type_node , - align ) ) ; gimplify_assign ( unshare_expr ( orig_ndx ) , t , pre_p ) ; } t = fold_convert ( integer_type_node , va_size ) ; t = build2 ( PLUS_EXPR , integer_type_node , orig_ndx , t ) ; gimplify_assign ( unshare_expr ( ndx ) , t , pre_p ) ; array = create_tmp_var ( ptr_type_node ) ; lab_over = NULL ; if ( ! must_pass_va_arg_in_stack ( type ) ) { lab_false = create_artificial_label ( UNKNOWN_LOCATION ) ; lab_over = create_artificial_label ( UNKNOWN_LOCATION ) ; t = build2 ( GT_EXPR , boolean_type_node , unshare_expr ( ndx ) , build_int_cst ( integer_type_node , MAX_ARGS_IN_REGISTERS * UNITS_PER_WORD ) ) ; t = build3 ( COND_EXPR , void_type_node , t , build1 ( GOTO_EXPR , void_type_node , lab_false ) , NULL_TREE ) ; gimplify_and_add ( t , pre_p ) ; gimplify_assign ( unshare_expr ( array ) , reg , pre_p ) ; t = build1 ( GOTO_EXPR , void_type_node , lab_over ) ; gimplify_and_add ( t , pre_p ) ; t = build1 ( LABEL_EXPR , void_type_node , lab_false ) ; gimplify_and_add ( t , pre_p ) ; } lab_false2 = create_artificial_label ( UNKNOWN_LOCATION ) ; t = build2 ( GT_EXPR , boolean_type_node , unshare_expr ( orig_ndx ) , build_int_cst ( integer_type_node , MAX_ARGS_IN_REGISTERS * UNITS_PER_WORD ) ) ; t = build3 ( COND_EXPR , void_type_node , t , build1 ( GOTO_EXPR , void_type_node , lab_false2 ) , NULL_TREE ) ; gimplify_and_add ( t , pre_p ) ; t = size_binop ( PLUS_EXPR , unshare_expr ( va_size ) , size_int ( <NUM_LIT> ) ) ; t = fold_convert ( integer_type_node , t ) ; gimplify_assign ( unshare_expr ( ndx ) , t , pre_p ) ; t = build1 ( LABEL_EXPR , void_type_node , lab_false2 ) ; gimplify_and_add ( t , pre_p ) ; gimplify_assign ( array , stk , pre_p ) ; if ( lab_over ) { t = build1 ( LABEL_EXPR , void_type_node , lab_over ) ; gimplify_and_add ( t , pre_p ) ; } if ( BYTES_BIG_ENDIAN && TREE_CODE ( type_size ) == INTEGER_CST ) { t = fold_build2 ( GE_EXPR , boolean_type_node , unshare_expr ( type_size ) , size_int ( PARM_BOUNDARY / BITS_PER_UNIT ) ) ; t = fold_build3 ( COND_EXPR , sizetype , t , unshare_expr ( va_size ) , unshare_expr ( type_size ) ) ; size =


<s> <ISA_LIT>Operand * Op = new <ISA_LIT>Operand ( k_Extend , Ctx ) ; Op -> Extend . Val = <STR_LIT> ( ExtOp , Val ) ; Op -> StartLoc = S ; Op -> EndLoc =


<s> assert ( ( OpNo < MII . get ( MI -> getOpcode ( ) ) . getNumOperands ( ) || MII . get ( MI -> getOpcode ( ) ) . TSFlags == <NUM_LIT> ) && <STR_LIT> ) ; unsigned WAReg = Op . getReg ( ) ; if ( int ( WAReg ) >= <NUM_LIT> ) printRegName ( O , WAReg ) ; else if ( OpNo >= MII . get ( MI -> getOpcode ( ) ) . getNumDefs ( ) ) O << <STR_LIT> << <ISA_LIT>FunctionInfo :: getWARegStackId ( WAReg ) ; else if ( WAReg != <ISA_LIT>FunctionInfo :: UnusedReg ) O << <STR_LIT> << <ISA_LIT>FunctionInfo :: getWARegStackId ( WAReg ) ; else O << <STR_LIT> ; if ( OpNo < MII . get ( MI -> getOpcode ( ) ) . getNumDefs ( ) ) O << '=' ; } else if ( Op . isImm ( ) ) { assert ( ( OpNo < MII . get ( MI -> getOpcode ( ) ) . getNumOperands ( ) || ( MII . get ( MI -> getOpcode ( ) ) . TSFlags & <STR_LIT> ) ) && <STR_LIT> <STR_LIT> ) ; O << Op . getImm ( ) ; } else if ( Op . isFPImm ( ) ) { const MCInstrDesc & Desc = MII . get ( MI -> getOpcode ( ) ) ; assert ( OpNo < Desc . getNumOperands ( ) && <STR_LIT> ) ; assert ( Desc . TSFlags == <NUM_LIT> && <STR_LIT> ) ; const MCOperandInfo & Info = Desc . OpInfo [


<s> if ( OffsetRelocLen ) OffsetRelocLen += <NUM_LIT> ; if ( ExternRelocLen ) ExternRelocLen += <NUM_LIT> ; OS . EmitIntValue ( <NUM_LIT> , <NUM_LIT> ) ; OS . EmitIntValue ( FuncLen , <NUM_LIT> ) ; OS . EmitIntValue ( FuncLen , <NUM_LIT> ) ; OS . EmitIntValue ( LineLen , <NUM_LIT> ) ; OS . EmitIntValue ( FuncLen + LineLen , <NUM_LIT> ) ; OS . EmitIntValue ( OffsetRelocLen , <NUM_LIT> ) ; OS . EmitIntValue ( FuncLen + LineLen + OffsetRelocLen , <NUM_LIT> ) ; OS . EmitIntValue ( ExternRelocLen , <NUM_LIT> ) ; OS . AddComment ( <STR_LIT> ) ; OS . EmitIntValue ( <STR_LIT> , <NUM_LIT> ) ; for ( const auto & FuncSec : FuncInfoTable ) { OS . AddComment ( <STR_LIT> + std :: to_string ( FuncSec . first ) ) ; OS . EmitIntValue ( FuncSec . first , <NUM_LIT> ) ; OS . EmitIntValue ( FuncSec . second . size ( ) , <NUM_LIT> ) ; for ( const auto & FuncInfo : FuncSec . second ) { Asm -> EmitLabelReference ( FuncInfo . Label , <NUM_LIT> ) ; OS . EmitIntValue ( FuncInfo . TypeId , <NUM_LIT> ) ; } } OS . AddComment ( <STR_LIT> ) ; OS . EmitIntValue ( <STR_LIT> , <NUM_LIT> ) ; for ( const auto & LineSec : LineInfoTable ) { OS . AddComment ( <STR_LIT> + std :: to_string ( LineSec . first ) ) ; OS . EmitIntValue ( LineSec . first , <NUM_LIT> ) ; OS . EmitIntValue ( LineSec . second .


<s> SDValue <ISA_LIT>TargetLowering :: LowerVAARG ( SDValue Op , SelectionDAG & DAG , const <ISA_LIT>Subtarget & Subtarget


<s> FunctionPass * llvm :: create<ISA_LIT>ISelDag ( <ISA_LIT>BaseTargetMachine & TM ) { return new <ISA_LIT>DAGToDAGISel ( TM


<s> auto & MBB = * MI . getParent ( ) ; auto & MF = * MBB . getParent ( ) ; auto & MRI = MF . getRegInfo ( ) ; uint64_t Immed ; if ( Root . isImm ( ) ) Immed = Root . getImm ( ) ; else if ( Root . isCImm ( ) ) Immed = Root . getCImm ( ) -> getZExtValue ( ) ; else if ( Root . isReg ( ) ) { auto ValAndVReg = getConstantVRegValWithLookThrough ( Root . getReg ( ) , MRI , true ) ; if ( ! ValAndVReg ) return None ; Immed = ValAndVReg -> Value ; } else return None ; return Immed


<s> return __builtin_mve_vsubq_n_sv8hi ( __a ,


<s> } if ( loongarch_valid_base_register_p ( XEXP ( x , <NUM_LIT> ) , mode , strict_p ) && loongarch_valid_index_p ( info , XEXP ( x , <NUM_LIT> ) , mode , strict_p ) ) { info -> reg = XEXP ( x , <NUM_LIT> ) ; return true ; } info -> type = ADDRESS_REG ; info -> reg = XEXP ( x , <NUM_LIT> ) ; info -> offset = XEXP (


<s> case InlineAsm :: Constraint_o : case InlineAsm :: Constraint_Q : case InlineAsm :: Constraint_Um : case InlineAsm :: Constraint_Un : case InlineAsm :: Constraint_Uq : case InlineAsm :: Constraint_Us : case InlineAsm :: Constraint_Ut : case InlineAsm :: Constraint_Uv : case InlineAsm :: Constraint_Uy : OutOps . push_back ( Op ) ; return


<s> case InlineAsm :: Constraint_Q : case InlineAsm :: Constraint_Um : case InlineAsm :: Constraint_Un : case InlineAsm :: Constraint_Uq : case InlineAsm :: Constraint_Us : case InlineAsm :: Constraint_Ut : case InlineAsm :: Constraint_Uv : case InlineAsm :: Constraint_Uy : OutOps . push_back ( Op ) ; return false ; } return


<s> Ops . push_back ( Callee ) ; unsigned NumArgs = TheCall -> getNumArgs ( ) ; for ( i = <NUM_LIT> ; i < NumArgs ; i ++ ) { Ops . push_back ( TheCall -> getArg ( i ) ) ; Ops . push_back ( TheCall -> getArgFlagsVal ( i ) ) ; } std :: vector < MVT > NodeTys ; unsigned NumRets = TheCall -> getNumRetVals ( ) ; for ( i = <NUM_LIT> ; i < NumRets ; i ++ ) NodeTys . push_back ( TheCall -> getRetValType ( i ) ) ; NodeTys . push_back ( <STR_LIT> ) ; SDVTList VTs = DAG . getVTList ( & NodeTys [ <NUM_LIT> ] , NodeTys . size ( ) ) ; return DAG . getCall ( TheCall -> getCallingConv ( ) , dl , TheCall -> isVarArg ( ) , TheCall -> isTailCall ( ) , TheCall -> isInreg ( ) , VTs ,

& Ops [ <NUM_LIT> ] , Ops . size ( ) ) ;


<s> SDValue SplatValue = N -> getOperand ( <NUM_LIT> ) ; for ( auto Lane : N -> op_values ( ) ) if ( Lane != SplatValue ) return false ; return


<s> void <ISA_LIT>TargetWinCOFFStreamer :: EmitARM64WinCFISaveFPLRX ( int Offset ) { EmitARM64WinUnwindCode ( Win64EH :: UOP_SaveFPLRX , - <NUM_LIT> ,


<s> assert ( ( RC == & <STR_LIT> || ( TargetRegisterInfo :: isPhysicalRegister ( SrcReg ) && is<ISA_LIT>LowRegister ( SrcReg ) ) ) && <STR_LIT> ) ; if ( RC == & <STR_LIT> || ( TargetRegisterInfo :: isPhysicalRegister ( SrcReg ) && is<ISA_LIT>LowRegister ( SrcReg ) ) ) { DebugLoc DL ; if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; MachineFrameInfo & MFI = MF .


<s> SDValue Result = DAG . getNode ( <STR_LIT> , dl , CanonicalVT , N0 -> getOperand ( <NUM_LIT> ) , N0 -> getOperand ( <NUM_LIT> ) , N1 -> getOperand ( <NUM_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Result ) ; } } } if ( Subtarget -> isThumb1Only ( ) || ! Subtarget -> hasV6T2Ops ( ) ) return SDValue ( ) ; DebugLoc DL = N -> getDebugLoc ( ) ; if ( VT != <STR_LIT> ) return SDValue ( ) ; SDValue N00 = N0 . getOperand ( <NUM_LIT> ) ; SDValue MaskOp = N0 . getOperand ( <NUM_LIT> ) ; ConstantSDNode * MaskC = dyn_cast < ConstantSDNode > ( MaskOp ) ; if ( ! MaskC ) return SDValue ( ) ; unsigned Mask = MaskC -> getZExtValue ( ) ; if ( Mask == <NUM_LIT> ) return SDValue ( ) ; SDValue Res ; ConstantSDNode * N1C = dyn_cast < ConstantSDNode > ( N1 ) ; if ( N1C ) { unsigned Val = N1C -> getZExtValue ( ) ; if ( ( Val & ~ Mask ) != Val ) return SDValue ( ) ; if ( <STR_LIT> ( Mask ) ) { Val >>= CountTrailingZeros_32 ( ~ Mask ) ; Res = DAG . getNode ( <STR_LIT> , DL , VT , N00 , DAG . getConstant ( Val , <STR_LIT> ) , DAG . getConstant ( Mask , <STR_LIT> ) ) ; DCI . CombineTo ( N , Res , false ) ; return SDValue ( ) ; } } else if ( N1 . getOpcode ( ) == <STR_LIT> ) { ConstantSDNode * N11C = dyn_cast < ConstantSDNode > ( N1 . getOperand ( <NUM_LIT> ) ) ; if ( ! N11C ) return SDValue ( ) ; unsigned Mask2 = N11C -> getZExtValue ( ) ; if ( <STR_LIT> ( Mask ) && ( Mask == ~ Mask2 ) ) { if ( Subtarget -> hasT2ExtractPack ( ) && ( Mask == <NUM_LIT> || Mask == <NUM_LIT> ) ) return SDValue ( ) ; unsigned amt = CountTrailingZeros_32 ( Mask2 ) ; Res = DAG . getNode ( <STR_LIT> , DL , VT , N1 . getOperand ( <NUM_LIT> ) , DAG . getConstant ( amt , <STR_LIT> ) ) ; Res = DAG . getNode ( <STR_LIT> , DL , VT , N00 , Res , DAG . getConstant ( Mask , <STR_LIT> ) ) ; DCI . CombineTo ( N , Res , false ) ; return SDValue


<s> DebugLoc dl = I == MBB -> end ( ) ? DebugLoc ( ) : I -> getDebugLoc ( ) ; unsigned STReg = getSTReg ( RegNo ) ; pushReg (


<s> setAttributeItem ( Virtualization_use , AllowTZ , false ) ; break ; case <STR_LIT> :: <ISA_LIT>V6M : setAttributeItem ( THUMB_ISA_use , Allowed , false ) ; break ; case <STR_LIT> :: <ISA_LIT>V7A : setAttributeItem ( CPU_arch_profile , ApplicationProfile , false ) ; setAttributeItem ( <ISA_LIT>_ISA_use , Allowed , false ) ; setAttributeItem ( THUMB_ISA_use , AllowThumb32 , false ) ; break ; case <STR_LIT> :: <ISA_LIT>V7R : setAttributeItem ( CPU_arch_profile , RealTimeProfile , false ) ; setAttributeItem ( <ISA_LIT>_ISA_use , Allowed , false ) ; setAttributeItem ( THUMB_ISA_use , AllowThumb32 , false ) ; break ; case <STR_LIT> :: <ISA_LIT>V7M : setAttributeItem ( CPU_arch_profile , MicroControllerProfile , false ) ; setAttributeItem ( THUMB_ISA_use , AllowThumb32 , false ) ; break ; case <STR_LIT> :: <ISA_LIT>V8A : case <STR_LIT> :: <ISA_LIT>V8_1A : case <STR_LIT> :: <ISA_LIT>V8_2A : setAttributeItem ( CPU_arch_profile , ApplicationProfile , false ) ; setAttributeItem ( <ISA_LIT>_ISA_use , Allowed , false ) ; setAttributeItem ( THUMB_ISA_use , AllowThumb32 , false ) ; setAttributeItem ( MPextension_use , Allowed , false ) ; setAttributeItem ( Virtualization_use , AllowTZVirtualization , false ) ; break ; case <STR_LIT>


<s> void printMemRegReg ( const MachineInstr * MI , unsigned OpNo ) { const MachineOperand & MO = MI -> getOperand ( OpNo ) ; printRegister ( MO , true ) ; O <<


<s> const MILOHContainer & getLOHContainer ( )


<s> void addConstantSImmOperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT>


<s> bool AMDGPUSubtarget :: isOverride ( <STR_LIT> caps ) const { assert ( caps < <STR_LIT> && <STR_LIT> ) ; return CapsOverride [ caps ]


<s> if ( RegNum != <NUM_LIT> ) return - <NUM_LIT> ; return <STR_LIT> ; } if ( RegNum > <NUM_LIT> ) return - <NUM_LIT> ; return getReg ( <STR_LIT> , RegNum ) + is<ISA_LIT>64


<s> bool ParseDirective ( AsmToken DirectiveID ) override { StringRef IDVal = DirectiveID . getIdentifier ( ) ; if ( IDVal . startswith ( <STR_LIT> ) ) return parseAddrAsciz ( DirectiveID . getLoc (


<s> case BRIG_CHANNEL_TYPE_SNORM_INT16 : O << <STR_LIT> ; break ; case BRIG_CHANNEL_TYPE_UNORM_INT8 : O << <STR_LIT> ; break ; case BRIG_CHANNEL_TYPE_UNORM_INT16 : O << <STR_LIT> ; break ; case BRIG_CHANNEL_TYPE_UNORM_INT24 : O << <STR_LIT> ; break ; case BRIG_CHANNEL_TYPE_UNORM_SHORT_555 : O << <STR_LIT> ; break ; case BRIG_CHANNEL_TYPE_UNORM_SHORT_565 : O << <STR_LIT> ; break ; case BRIG_CHANNEL_TYPE_UNORM_INT_101010 : O << <STR_LIT> ; break ; case BRIG_CHANNEL_TYPE_SIGNED_INT8 : O <<


<s> SDValue A2 = b . BITCAST ( Op . getOperand ( <NUM_LIT> ) , FullVT ) ; SDValue Tmp = b . OR ( b . AND ( A1 , b . NOT ( A2 ) ) , b . AND ( b . SRL < <NUM_LIT> > ( A1 ) , A2 ) ) ; return b . IFH1 ( b . HiMask ( <NUM_LIT> , <NUM_LIT> ) , b . AND ( A1 , b . NOT ( b . SHL < <NUM_LIT> > ( A2 ) ) ) , Tmp ) ; } llvm_unreachable ( <STR_LIT>


<s> if ( ! TARGET_64BIT && flag_pic && decl && ! targetm . binds_local_p ( decl ) ) return false ; return ! s390_call_saved_register_used ( exp


<s> unsigned <ISA_LIT>InstrInfo :: isStoreToStackSlot ( const MachineInstr & MI , int & FrameIndex ) const { switch ( MI . getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> rtx sign = gen_reg_rtx ( mode ) ; bool neg ; neg = ia64_expand_vecint_compare ( LT , mode , sign , vec , zero ) ; gcc_assert ( ! neg


<s> void addVectorIndexHOperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: createImm


<s> static DecodeStatus DecodeT2AddrModeSOReg ( MCInst & Inst , unsigned Val , uint64_t Address , const void * Decoder ) { DecodeStatus S = MCDisassembler :: Success ; unsigned Rn = fieldFromInstruction ( Val , <NUM_LIT> , <NUM_LIT> ) ; unsigned Rm = fieldFromInstruction ( Val , <NUM_LIT> , <NUM_LIT> ) ; unsigned imm = fieldFromInstruction ( Val , <NUM_LIT> , <NUM_LIT> ) ; switch ( Inst . getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> const TargetRegisterInfo & TRI = * STI . getRegisterInfo ( ) ; int64_t Offset = <NUM_LIT> ; for ( int I = MFI -> getObjectIndexBegin ( ) ; I != <NUM_LIT> ; ++ I ) Offset = std :: max ( Offset , - MFI -> getObjectOffset ( I ) ) ; for ( const MCPhysReg * R = TRI . getCalleeSavedRegs ( & MF ) ; * R ; ++ R ) { unsigned Size = TRI . getMinimalPhysRegClass ( * R ) -> getSize ( ) ; Offset = alignTo ( Offset + Size , Size ) ; } unsigned MaxAlign = MFI -> getMaxAlignment ( ) ; assert ( ! MFI -> getObjectIndexEnd ( ) || MaxAlign ) ; for ( unsigned I = <NUM_LIT> , E = MFI -> getObjectIndexEnd ( ) ; I != E ; ++ I ) Offset = alignTo ( Offset + MFI -> getObjectSize


<s> assert ( <STR_LIT> . contains ( Reg ) && <STR_LIT> ) ; LoReg = getSubReg ( Reg , <STR_LIT> ) ; HiReg = getSubReg ( Reg ,


<s> if ( verbose ) fprintf ( stderr , <STR_LIT> , string ) ; putenv ( CONST_CAST ( char * , string )


<s> void \ const_section ( ) \ { \ if ( ! USE_CONST_SECTION ) \ text_section ( ) ; \ else if ( in_section != in_const ) \ { \

fprintf ( asm_out_file , <STR_LIT> , CONST_SECTION_ASM_OP ) ; \ in_section = in_const ; \ } \ }


<s> EVT Ty = Op . getValueType ( ) ; GlobalAddressSDNode * N = cast < GlobalAddressSDNode > ( Op ) ; const GlobalValue * GV = N -> getGlobal ( ) ; if ( ! isPositionIndependent ( ) ) { const <ISA_LIT>TargetObjectFile * TLOF = static_cast < const <ISA_LIT>TargetObjectFile * > ( getTargetMachine ( ) . getObjFileLowering ( ) ) ; const GlobalObject * GO = GV -> getBaseObject ( ) ; if ( GO && TLOF -> IsGlobalInSmallSection ( GO , getTargetMachine ( ) ) ) return getAddrGPRel ( N , SDLoc ( N ) , Ty , DAG ) ; return Subtarget . hasSym32 ( ) ? getAddrNonPIC ( N , SDLoc ( N ) , Ty , DAG ) : getAddrNonPICSym64 ( N , SDLoc ( N ) , Ty , DAG ) ; } if ( GV -> hasLocalLinkage ( ) ) return getAddrLocal ( N , SDLoc ( N ) , Ty , DAG , ABI . IsN32 ( ) || ABI . IsN64 ( ) ) ; if ( LargeGOT ) return getAddrGlobalLargeGOT ( N , SDLoc ( N ) , Ty , DAG , <STR_LIT> , <STR_LIT> , DAG . getEntryNode ( ) , MachinePointerInfo :: getGOT ( DAG . getMachineFunction ( ) ) ) ; return getAddrGlobal ( N , SDLoc ( N ) , Ty , DAG , ( ABI . IsN32 ( ) || ABI . IsN64 ( ) ) ? <STR_LIT> : <STR_LIT> , DAG . getEntryNode ( ) , MachinePointerInfo


<s> if ( isGlobalStubReference ( GVFlags ) ) return false ; if ( AM . HasBaseReg && isGlobalRelativeToPICBase ( GVFlags ) ) return false ; if ( ( M != CodeModel :: Small || R != Reloc :: Static ) && Subtarget -> is64Bit ( ) && ( AM . BaseOffs || AM . Scale > <NUM_LIT> ) ) return false ; } switch ( AM . Scale ) { case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : break ; case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : if ( AM . HasBaseReg ) return false ; break ; default : return false


<s> static bool rs6000_elf_in_small_data_p ( tree decl ) { if ( rs6000_sdata == SDATA_NONE ) return false ; if ( TREE_CODE ( decl ) == STRING_CST ) return false ; if ( TREE_CODE ( decl ) == FUNCTION_DECL ) return false ; if ( TREE_CODE ( decl ) == VAR_DECL && DECL_SECTION_NAME ( decl ) ) { const char * section = TREE_STRING_POINTER ( DECL_SECTION_NAME ( decl ) ) ; if ( strcmp ( section , <STR_LIT> ) == <NUM_LIT> || strcmp ( section , <STR_LIT> ) == <NUM_LIT> || strcmp ( section , <STR_LIT> ) == <NUM_LIT> || strcmp ( section , <STR_LIT> ) == <NUM_LIT> || strcmp ( section , <STR_LIT> ) == <NUM_LIT> || strcmp ( section , <STR_LIT> ) == <NUM_LIT> ) return true ; } else { HOST_WIDE_INT size = int_size_in_bytes ( TREE_TYPE ( decl )


<s> for ( auto & Terminator : Terminators ) if ( mustRelaxBranch ( Terminator , Terminator . Address ) ) return true ; return false


<s> XMMSaveMBB -> addSuccessor ( EndMBB ) ; const TargetInstrInfo * TII = getTargetMachine ( ) . getInstrInfo ( ) ; DebugLoc DL = MI -> getDebugLoc ( ) ; unsigned CountReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; int64_t RegSaveFrameIndex = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; int64_t VarArgsFPOffset = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( ! Subtarget -> isTargetWin64 ( ) ) { BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) ) . addReg ( CountReg ) . addReg ( CountReg ) ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) ) . addMBB ( EndMBB ) ; MBB -> addSuccessor ( EndMBB ) ; } for ( int i = <NUM_LIT> , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) { int64_t Offset = ( i - <NUM_LIT> ) * <NUM_LIT> + VarArgsFPOffset ; MachineMemOperand * MMO = F -> getMachineMemOperand ( PseudoSourceValue :: getFixedStack ( RegSaveFrameIndex ) , MachineMemOperand :: MOStore , Offset , <NUM_LIT> ,


<s> TentativelyCommuting = false ; Declined =


<s> if ( get<ISA_LIT>Subtarget ( ) . isThumb2 ( ) ) addPass ( & UnpackMachineBundlesID ) ; addPass ( create<ISA_LIT>OptimizeBarriersPass ( ) ) ; addPass ( create<ISA_LIT>ConstantIslandPass (


<s> if ( ! GV ) { if ( const auto * CV = dyn_cast < Constant > ( MemAddr ) ) for ( const auto & CO : CV -> operands ( ) ) if ( memAddrUsesCTR ( TM , CO ) ) return true ; return false ; } if ( ! GV -> isThreadLocal ( ) ) return false ; TLSModel :: Model Model = TM .


<s> } return Error ( Tok . getLoc ( ) , <STR_LIT> ) ; } case AsmToken :: Integer : { StringRef ErrMsg ; if ( isParsingInlineAsm ( ) && SM . getAddImmPrefix ( ) ) InstInfo -> AsmRewrites -> push_back ( AsmRewrite ( AOK_ImmPrefix , Tok . getLoc ( ) ) ) ; SMLoc Loc = getTok ( ) . getLoc ( ) ; int64_t IntVal = getTok ( ) . getIntVal ( ) ; End = consumeToken ( ) ; UpdateLocLex = false ; if ( getLexer ( ) . getKind ( ) == AsmToken :: Identifier ) { StringRef IDVal = getTok ( ) . getString ( ) ; if ( IDVal == <STR_LIT> || IDVal == <STR_LIT> ) { MCSymbol * Sym = getContext ( ) . GetDirectionalLocalSymbol ( IntVal , IDVal == <STR_LIT> ? <NUM_LIT> : <NUM_LIT> ) ; MCSymbolRefExpr :: VariantKind Variant = MCSymbolRefExpr :: VK_None ; const MCExpr * Val = MCSymbolRefExpr :: Create ( Sym , Variant , getContext ( ) ) ; if ( IDVal == <STR_LIT> && Sym -> isUndefined ( ) ) return Error ( Loc , <STR_LIT> ) ; StringRef Identifier = Sym -> getName ( ) ; SM . onIdentifierExpr ( Val , Identifier ) ; End = consumeToken ( ) ; } else { if ( SM . onInteger ( IntVal , ErrMsg ) ) return Error ( Loc , ErrMsg ) ; } } else { if ( SM . onInteger ( IntVal , ErrMsg ) ) return Error ( Loc , ErrMsg ) ; } break ; } case AsmToken :: Plus : SM . onPlus ( ) ; break ; case AsmToken :: Minus : SM . onMinus ( ) ; break ; case AsmToken :: Star : SM . onStar ( ) ; break ; case AsmToken :: Slash : SM . onDivide ( ) ; break ; case AsmToken :: Pipe : SM . onOr ( ) ; break ; case AsmToken :: Amp : SM . onAnd ( ) ; break ; case AsmToken :: LessLess : SM . onLShift ( ) ; break ; case AsmToken :: GreaterGreater : SM . onRShift ( ) ; break ; case AsmToken :: LBrac : SM . onLBrac ( ) ; break ; case AsmToken :: RBrac : SM . onRBrac ( ) ; break ; case AsmToken :: LParen : SM . onLParen ( ) ;


<s> * instructionID = decode ( insn -> opcodeType , instructionClass , insn -> opcode , insn -> modRM ) ; } else { * instructionID = decode ( insn -> opcodeType , instructionClass , insn -> opcode , <NUM_LIT> ) ; } return <NUM_LIT>


<s> } if ( Subtarget . isELFv2ABI ( ) ) return AsmPrinter :: EmitFunctionEntryLabel ( ) ; MCSectionSubPair Current = OutStreamer . getCurrentSection ( ) ; const MCSectionELF * Section = OutStreamer . getContext ( ) . getELFSection ( <STR_LIT> , ELF :: SHT_PROGBITS , ELF :: SHF_WRITE | ELF :: SHF_ALLOC , SectionKind :: getReadOnly ( ) ) ; OutStreamer . SwitchSection ( Section ) ; OutStreamer . EmitLabel ( CurrentFnSym ) ; OutStreamer . EmitValueToAlignment ( <NUM_LIT> ) ; MCSymbol * Symbol1 = OutContext . GetOrCreateSymbol ( <STR_LIT> + Twine ( CurrentFnSym -> getName ( ) ) ) ; OutStreamer . EmitValue ( MCSymbolRefExpr :: Create ( Symbol1 , OutContext ) , <NUM_LIT> ) ; MCSymbol * Symbol2 = OutContext . GetOrCreateSymbol ( StringRef ( <STR_LIT> ) ) ; OutStreamer . EmitValue ( MCSymbolRefExpr :: Create ( Symbol2 , MCSymbolRefExpr :: VK_<ISA_LIT>_TOCBASE , OutContext ) , <NUM_LIT> ) ; OutStreamer . EmitIntValue ( <NUM_LIT> ,


<s> void <ISA_LIT>FrameInfo :: emitPushInst ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI , unsigned StmOpc , unsigned StrOpc , bool NoGap , bool ( * Func ) ( unsigned , bool ) ) const { MachineFunction & MF = * MBB . getParent ( ) ; const TargetInstrInfo & TII = * MF . getTarget ( ) . getInstrInfo ( ) ; DebugLoc DL ; if ( MI != MBB . end ( ) ) DL = MI -> getDebugLoc ( ) ; SmallVector < std :: pair < unsigned , bool > , <NUM_LIT> > Regs ; unsigned i = CSI . size ( ) ; while ( i != <NUM_LIT> ) { unsigned LastReg = <NUM_LIT> ; for ( ; i != <NUM_LIT> ; -- i ) { unsigned Reg = CSI [ i - <NUM_LIT> ] . getReg ( ) ; if ( ! ( Func ) ( Reg , STI . isTargetDarwin ( ) ) ) continue ; bool isKill = true ; if ( Reg == <STR_LIT> ) { if ( MF . getFrameInfo ( ) -> isReturnAddressTaken ( ) && MF . getRegInfo ( ) . isLiveIn ( Reg ) ) isKill = false ; } if ( isKill ) MBB . addLiveIn ( Reg ) ; if ( NoGap && LastReg && LastReg != Reg - <NUM_LIT> ) break ; LastReg = Reg ; Regs . push_back ( std :: make_pair ( Reg , isKill ) ) ; } if ( Regs . empty ( ) ) continue ; if ( Regs . size ( ) > <NUM_LIT> || StrOpc == <NUM_LIT> ) { MachineInstrBuilder MIB = AddDefaultPred ( BuildMI ( MBB , MI , DL , TII . get ( StmOpc ) , <STR_LIT> )


<s> SDValue NewShift = DAG . getNode ( <STR_LIT> , DL , VT , NewAnd , Shift . getOperand ( <NUM_LIT> ) ) ; InsertDAGNode ( DAG , N , NewMask ) ; InsertDAGNode ( DAG , N , NewAnd ) ; InsertDAGNode ( DAG , N , NewShift ) ; DAG . ReplaceAllUsesWith ( N , NewShift ) ; AM . Scale = <NUM_LIT> << ShiftAmt ; AM . IndexReg


<s> if ( GET_MODE_CLASS ( mode ) == MODE_INT && GET_MODE_SIZE ( mode ) < ( TARGET_32BIT ? <NUM_LIT> : <NUM_LIT> ) ) mode = TARGET_32BIT ? SImode : DImode ; return


<s> printAMIndexed ( MI , OpNum , <NUM_LIT> ,


<s> IInSlot = Res . first ; } if ( LastInstInFunction || ! SafeInSlot ( * IInSlot , * I ) ) { MachineBasicBlock :: instr_iterator Iit = I -> getIterator ( ) ; if ( std :: next ( Iit ) == FI -> end ( ) || std :: next ( Iit ) -> getOpcode ( ) != <STR_LIT> ) { Changed = true ; TII -> insertNop ( * ( I -> getParent ( ) ) , std :: next ( I ) , I -> getDebugLoc ( ) ) -> bundleWithPred ( ) ; NumInsertedNops ++ ; } } } } return


<s> emit_insn ( gen_insll_be ( insh , gen_lowpart ( SImode , src ) , addr ) ) ; break ; case <NUM_LIT> : emit_insn ( gen_insql_be ( insh , gen_lowpart ( DImode , src ) , addr ) ) ; break ; } emit_insn ( gen_insxh ( insl , gen_lowpart ( DImode , src ) , GEN_INT ( size * <NUM_LIT> ) , addr ) ) ; } switch ( ( int ) size ) { case <NUM_LIT> : emit_insn ( gen_mskxl_be ( dsth , dsth , GEN_INT ( <NUM_LIT> ) , addr ) ) ; break ; case <NUM_LIT> : { rtx msk = immed_double_const ( <NUM_LIT> , <NUM_LIT> , DImode ) ; emit_insn ( gen_mskxl_be ( dsth , dsth , msk , addr ) ) ; break ; } case <NUM_LIT> : emit_insn ( gen_mskxl_be ( dsth , dsth , constm1_rtx , addr ) ) ; break ; } emit_insn ( gen_mskxh ( dstl , dstl , GEN_INT ( size * <NUM_LIT> ) , addr ) ) ; } else { addr = copy_addr_to_reg ( plus_constant ( dsta , ofs ) ) ; if ( src != CONST0_RTX ( GET_MODE ( src ) ) ) { emit_insn ( gen_insxh ( insh , gen_lowpart ( DImode , src ) , GEN_INT ( size * <NUM_LIT> ) , addr ) ) ; switch ( ( int ) size ) { case <NUM_LIT> : emit_insn ( gen_inswl_le ( insl , gen_lowpart ( HImode , src ) , addr ) ) ; break ; case <NUM_LIT> : emit_insn ( gen_insll_le ( insl , gen_lowpart ( SImode , src ) , addr ) ) ; break ; case <NUM_LIT> : emit_insn ( gen_insql_le ( insl , src , addr ) ) ; break ; } } emit_insn ( gen_mskxh ( dsth , dsth , GEN_INT ( size * <NUM_LIT> ) , addr ) ) ; switch ( ( int ) size ) { case <NUM_LIT> : emit_insn ( gen_mskxl_le ( dstl , dstl , GEN_INT ( <NUM_LIT> ) , addr ) ) ; break ; case <NUM_LIT> : { rtx msk = immed_double_const ( <NUM_LIT> , <NUM_LIT> , DImode ) ; emit_insn ( gen_mskxl_le ( dstl , dstl ,


<s> vmulxq_f32 ( float32x4_t a , float32x4_t b ) { float32x4_t result


<s> return ( int8x8_t ) __builtin_neon_vget_highv16qi


<s> uint64_t Size = TM . getSubtargetImpl ( ) -> getDataLayout ( ) -> getTypeAllocSize ( ZCPV -> getType ( ) ) ; OutStreamer . EmitValue (


<s> return new <ISA_LIT>PromoteConstant (


<s> static DecodeStatus DecodeMemBarrierOption ( MCInst & Inst , unsigned Val , uint64_t Address , const void * Decoder ) { if ( Val & ~ <NUM_LIT> ) return MCDisassembler :: Fail ; Inst . addOperand ( MCOperand :: CreateImm


<s> switch ( oldOpcode ) { case AMDGPU :: JUMP_COND : case AMDGPU :: JUMP : return AMDGPU :: CONTINUE_LOGICALZ_i32 ; default : assert ( <NUM_LIT> && <STR_LIT> ) ; } return - <NUM_LIT>


<s> return ( ( vec_double2 ) ( si_dfnms ( ( qword ) ( a ) , ( qword ) ( b ) , ( qword ) ( c


<s> VLIWResourceModel ( const TargetMachine & TM , const TargetSchedModel * SM ) : SchedModel ( SM ) , TotalPackets ( <NUM_LIT> ) { ResourcesModel = TM . getSubtargetImpl ( ) -> getInstrInfo ( ) -> CreateTargetScheduleState ( & TM , nullptr ) ; assert ( ResourcesModel && <STR_LIT> )


<s> bool <ISA_LIT>LegalizerInfo :: legalizeLoadStore ( MachineInstr & MI , MachineRegisterInfo & MRI , MachineIRBuilder & MIRBuilder , GISelChangeObserver & Observer ) const { assert ( MI . getOpcode ( ) == TargetOpcode :: G_STORE || MI . getOpcode ( ) == TargetOpcode :: G_LOAD ) ; Register ValReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; const LLT ValTy = MRI . getType ( ValReg ) ; if ( ! ValTy . isVector ( ) || ! ValTy . getElementType ( ) . isPointer ( ) || ValTy . getElementType ( ) . getAddressSpace ( ) != <NUM_LIT> ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } unsigned PtrSize = ValTy . getElementType ( ) . getSizeInBits ( ) ; const LLT NewTy = LLT :: vector ( ValTy . getNumElements ( ) ,


<s> void fixup_7_pcrel ( unsigned Size , const MCFixup & Fixup , uint64_t & Value , MCContext * Ctx = nullptr ) { adjustRelativeBranch ( Size , Fixup , Value


<s> SDValue WidthMinusOne = DAG . getConstant ( NumBits - <NUM_LIT> , dl , VT ) ; return DAG . getNode ( <STR_LIT> , dl , VT , WidthMinusOne , DAG . getNode ( <STR_LIT> , dl , VT , LSB ) ) ; } SDValue One = DAG . getConstant ( <NUM_LIT> , dl , VT ) ; return DAG . getNode ( <STR_LIT> , dl , VT , DAG . getNode ( <STR_LIT> , dl , VT , LSB , One ) ) ; } assert ( Op . getOpcode ( ) == <STR_LIT> && <STR_LIT> ) ; SDVTList VTs = DAG . getVTList ( VT , <STR_LIT> ) ; Op = DAG . getNode ( <STR_LIT> , dl , VTs , Op .


<s> return TargetTransformInfo ( <ISA_LIT>TTIImpl ( this , F )


<s> bool <ISA_LIT>PassConfig :: addILPOpts ( ) { if ( EnableCCMP ) addPass ( create<ISA_LIT>ConditionalCompares ( ) ) ; addPass ( &


<s> insn -> mode = mode ; insn -> numImmediatesConsumed = <NUM_LIT> ; if ( readPrefixes ( insn ) || readOpcode ( insn ) || getID ( insn ) || insn -> instructionID == <NUM_LIT> || readOperands ( insn ) ) return - <NUM_LIT> ; insn -> length = insn -> readerCursor - insn


<s> O << TAI -> getGlobalDirective ( ) << name ; O <<


<s> shmask . v = ( ( vec_uint4 ) { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ; shmask . i [ ( si_to_uint ( ( qword ) ( vec_add ( ( vec_uint4 ) ( a ) , ( vec_uint4 ) ( b ) ) ) ) >> <NUM_LIT> ) & <NUM_LIT> ] = <NUM_LIT> ; return ( ( qword ) (


<s> Parser . Lex ( ) ; } else { SMLoc LParenLoc = Parser . getTok ( ) . getLoc ( ) ; Parser . Lex ( ) ; if ( getLexer ( ) . is ( AsmToken :: Percent ) || getLexer ( ) . is ( AsmToken :: Comma ) ) { } else { SMLoc ExprEnd ; if ( getParser ( ) . ParseParenExpression ( Disp , ExprEnd ) ) return <NUM_LIT> ; if ( getLexer ( ) . isNot ( AsmToken :: LParen ) ) { if ( SegReg == <NUM_LIT> ) return <STR_LIT> ( Disp , LParenLoc , ExprEnd ) ; return <STR_LIT> ( SegReg , Disp , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , MemStart , ExprEnd ) ; } Parser . Lex ( ) ; } } unsigned BaseReg = <NUM_LIT> , IndexReg = <NUM_LIT> , Scale = <NUM_LIT> ; if ( getLexer ( ) . is ( AsmToken :: Percent ) ) { SMLoc StartLoc , EndLoc ; if ( ParseRegister ( BaseReg , StartLoc , EndLoc ) ) return <NUM_LIT> ; if ( BaseReg == <STR_LIT> || BaseReg == <STR_LIT> ) { Error ( StartLoc , <STR_LIT> , SMRange ( StartLoc , EndLoc ) ) ; return <NUM_LIT> ; } } if ( getLexer ( ) . is ( AsmToken :: Comma ) ) { Parser . Lex ( ) ; if ( getLexer ( ) . is ( AsmToken :: Percent ) ) { SMLoc L ; if ( ParseRegister ( IndexReg , L , L ) ) return <NUM_LIT> ; if ( getLexer ( ) . isNot ( AsmToken :: RParen ) ) { if ( getLexer ( ) . isNot ( AsmToken :: Comma ) ) { Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; return <NUM_LIT> ; } Parser . Lex ( ) ; if ( getLexer ( ) . isNot ( AsmToken :: RParen ) ) { SMLoc Loc = Parser . getTok ( ) . getLoc ( ) ; int64_t ScaleVal ; if ( getParser ( ) . ParseAbsoluteExpression ( ScaleVal ) ) return <NUM_LIT> ; if ( ScaleVal != <NUM_LIT> && ScaleVal != <NUM_LIT> && ScaleVal != <NUM_LIT> && ScaleVal != <NUM_LIT> ) { Error ( Loc , <STR_LIT> ) ; return <NUM_LIT> ; } Scale = ( unsigned ) ScaleVal ; } } } else if ( getLexer ( ) .


<s> if ( CostKind == TTI :: TCK_RecipThroughput && ( ST -> hasNEON ( ) || ST -> hasMVEIntegerOps ( ) ) ) { return <NUM_LIT>


<s> createNewWater ( CPUserIndex , UserOffset , NewMBB ) ; MachineBasicBlock * WaterBB = & * -- NewMBB -> getIterator ( ) ; IP = find ( WaterList , WaterBB ) ; if ( IP != WaterList . end ( ) ) NewWaterList . erase ( WaterBB ) ; NewWaterList . insert ( NewIsland ) ; } const Align Alignment = isThumb ? Align ( <NUM_LIT> ) : Align ( <NUM_LIT> ) ; if ( NewMBB -> getAlignment ( ) < Alignment ) NewMBB -> setAlignment ( Alignment ) ; if ( IP != WaterList . end ( ) ) WaterList . erase ( IP ) ; MF -> insert ( NewMBB -> getIterator ( ) , NewIsland ) ; updateForInsertedWaterBlock ( NewIsland ) ; U . HighWaterMark = NewIsland ; U . CPEMI = BuildMI ( NewIsland , DebugLoc ( ) , CPEMI -> getDesc ( ) ) . addImm ( ID ) . add ( CPEMI -> getOperand ( <NUM_LIT> ) ) . addImm ( Size ) ; CPEntries [ CPI ] . push_back ( CPEntry ( U . CPEMI , ID , <NUM_LIT> ) ) ; ++ NumCPEs ; decrementCPEReferenceCount ( CPI , CPEMI ) ; NewIsland -> setAlignment ( getCPEAlign ( U


<s> BBInfoVector & BBInfo = BBUtils -> getBBInfo ( ) ; unsigned CPELogAlign = getCPELogAlign ( U . CPEMI ) ; unsigned CPEOffset = BBInfo [ Water -> getNumber ( ) ] . postOffset ( CPELogAlign ) ; unsigned NextBlockOffset , NextBlockLogAlignment ; MachineFunction :: const_iterator NextBlock = Water -> getIterator ( ) ; if ( ++ NextBlock == MF -> end ( ) ) { NextBlockOffset = BBInfo [ Water -> getNumber ( ) ] . postOffset ( ) ; NextBlockLogAlignment = <NUM_LIT> ; } else { NextBlockOffset = BBInfo [ NextBlock -> getNumber ( ) ] .


<s> cc0_user = next_cc0_user ( insn ) ; if ( cc0_user == NULL ) return false ; body = PATTERN ( cc0_user ) ; set = single_set ( cc0_user ) ; if ( JUMP_P ( cc0_user ) && GET_CODE ( body ) == SET && SET_DEST ( body ) == pc_rtx && GET_CODE ( SET_SRC ( body ) ) == IF_THEN_ELSE && XEXP ( XEXP ( SET_SRC ( body

) , <NUM_LIT> ) , <NUM_LIT> ) == cc0_rtx ) {


<s> AM . Disp += G -> getOffset ( ) ; AM . SymbolFlags = G -> getTargetFlags ( ) ; } else if ( ConstantPoolSDNode * CP = dyn_cast < ConstantPoolSDNode > ( N0 ) ) { AM . CP = CP -> getConstVal ( ) ; AM . Align = CP -> getAlignment ( ) ; AM . Disp += CP -> getOffset ( ) ; AM . SymbolFlags = CP -> getTargetFlags ( ) ; } else if ( ExternalSymbolSDNode * S = dyn_cast < ExternalSymbolSDNode > ( N0 ) ) { AM . ES = S -> getSymbol ( ) ; AM . SymbolFlags = S -> getTargetFlags ( ) ; } else if ( auto * S = dyn_cast < MCSymbolSDNode > ( N0 ) ) { AM . MCSym = S -> getMCSymbol ( ) ; } else if ( JumpTableSDNode * J = dyn_cast < JumpTableSDNode > ( N0 ) ) { AM . JT = J -> getIndex ( ) ; AM . SymbolFlags = J -> getTargetFlags ( ) ; } else if ( BlockAddressSDNode * BA = dyn_cast < BlockAddressSDNode > ( N0 ) ) { AM . BlockAddr = BA -> getBlockAddress ( ) ; AM . Disp += BA -> getOffset ( ) ; AM . SymbolFlags = BA -> getTargetFlags ( ) ; } else llvm_unreachable ( <STR_LIT>


<s> case LABEL_REF : return flag_pic ? cris_rel_symbol : cris_offsettable_symbol ; case CONST : return cris_symbol_type_of ( XEXP ( x , <NUM_LIT> ) ) ; case PLUS : case MINUS : { enum cris_symbol_type t1 = cris_symbol_type_of ( XEXP ( x , <NUM_LIT> ) ) ; enum cris_symbol_type t2 = cris_symbol_type_of ( XEXP ( x , <NUM_LIT> ) ) ; gcc_assert ( t1 == cris_no_symbol || t2 == cris_no_symbol ) ; if ( t1 == cris_got_symbol || t2 == cris_got_symbol ) return


<s> if ( Subtarget -> hasAddr64 ( ) ) { SDValue SRsrc , VAddr , SOffset , Offset , SLC ; if ( SelectMUBUFAddr64 ( Mem -> getBasePtr ( ) , SRsrc , VAddr , SOffset , Offset , SLC ) ) { unsigned Opcode = Is32 ? <STR_LIT> : <STR_LIT> ; SDValue CmpVal = Mem -> getOperand ( <NUM_LIT> ) ; SDValue GLC = CurDAG -> getTargetConstant ( <NUM_LIT> , SL , <STR_LIT> ) ; SDValue Ops [ ] = { CmpVal , VAddr , SRsrc , SOffset , Offset , GLC , SLC , Mem -> getChain ( ) } ; CmpSwap = CurDAG -> getMachineNode ( Opcode , SL , Mem -> getVTList ( ) , Ops ) ; } } if ( ! CmpSwap ) { SDValue SRsrc , SOffset , Offset , SLC ; if ( SelectMUBUFOffset ( Mem -> getBasePtr ( ) , SRsrc , SOffset , Offset , SLC ) ) { unsigned Opcode = Is32 ? <STR_LIT> : <STR_LIT> ; SDValue CmpVal = Mem -> getOperand ( <NUM_LIT> ) ; SDValue GLC = CurDAG -> getTargetConstant ( <NUM_LIT> , SL , <STR_LIT> ) ; SDValue Ops [ ] = { CmpVal , SRsrc , SOffset , Offset , GLC , SLC , Mem -> getChain ( ) } ; CmpSwap = CurDAG -> getMachineNode ( Opcode , SL , Mem -> getVTList ( ) , Ops ) ; } } if ( !


<s> <ISA_LIT>Subtarget :: <ISA_LIT>Subtarget ( const std :: string & TT , const std :: string & CPU , const std :: string & FS ) : <ISA_LIT>GenSubtargetInfo ( TT , CPU , FS ) , HasMul ( false ) , HasDiv ( false )

, HasRor ( false ) , HasCmov ( false ) {


<s> explicit <ISA_LIT>AsmPrinter ( formatted_raw_ostream & O , TargetMachine & TM , MCStreamer & Streamer ) : AsmPrinter ( O , TM , Streamer ) { Subtarget = & TM . getSubtarget < <ISA_LIT>Subtarget


<s> void LLVMInitialize<ISA_LIT>Target ( )


<s> virtual const TargetFrameLowering * getFrameLowering ( ) const { return & FrameLowering


<s> MachineFunction & MF = * MBB . getParent ( ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( MF , FI ) , MachineMemOperand :: MOStore , MFI . getObjectSize ( FI ) , MFI . getObjectAlign ( FI ) ) ; if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) . add ( predOps ( <STR_LIT> ) ) ; return ; } if ( <STR_LIT> . hasSubClassEq ( RC


<s> unsigned Size = getSizeInBits ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) , MRI , * TRI ) ; LLT LoadTy = MRI . getType ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; Register PtrReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; LLT PtrTy = MRI . getType ( PtrReg ) ; unsigned AS = PtrTy . getAddressSpace ( ) ; unsigned PtrSize = PtrTy . getSizeInBits ( ) ; const ValueMapping * ValMapping ; const ValueMapping * PtrMapping ; const RegisterBank * PtrBank = getRegBank ( PtrReg , MRI , * TRI ) ; if ( PtrBank == & <STR_LIT> && <ISA_LIT>TargetLowering :: isFlatGlobalAddrSpace ( AS ) ) { if ( isScalarLoadLegal ( MI ) ) { ValMapping = <STR_LIT> ( <STR_LIT> , Size ) ; PtrMapping = <STR_LIT> ( <STR_LIT> , PtrSize ) ; } else { ValMapping = <STR_LIT> ( <STR_LIT> , Size ) ; unsigned PtrBankID = Subtarget . useFlatForGlobal ( ) ? <STR_LIT> : <STR_LIT> ; PtrMapping = <STR_LIT> ( PtrBankID , PtrSize ) ; ValMapping = <STR_LIT> ( <STR_LIT> , LoadTy ) ; } } else { ValMapping = <STR_LIT> ( <STR_LIT> , LoadTy ) ; PtrMapping = <STR_LIT> ( <STR_LIT> , PtrSize ) ; } OpdsMapping [ <NUM_LIT> ] = ValMapping ; OpdsMapping [ <NUM_LIT> ] = PtrMapping ; const RegisterBankInfo :: InstructionMapping & Mapping = getInstructionMapping ( <NUM_LIT> , <NUM_LIT> , getOperandsMapping ( OpdsMapping ) , MI . getNumOperands ( ) ) ; return Mapping


<s> static void mips_insert_insn_pseudos ( void ) { bool insn_pseudo_needed = TRUE ; rtx_insn * insn ; for ( insn = get_last_insn ( ) ; insn != NULL_RTX ; insn = PREV_INSN

( insn ) ) switch ( GET_CODE ( insn ) ) {


<s> addPass ( create<ISA_LIT>DelaySlotFillerPass ( ) ) ; addPass ( create<ISA_LIT>BranchExpansion ( ) ) ; addPass ( create<ISA_LIT>ConstantIslandPass ( )


<s> float foo = __truncdfsf2 ( __truncxfdf2 ( ld )


<s> assert ( SetCCI . getOperand ( <NUM_LIT> ) . isReg ( ) && <STR_LIT> ) ; MRI -> replaceRegWith ( SetCCI . getOperand ( <NUM_LIT> ) . getReg ( ) , CondReg ) ; SetCCI . eraseFromParent ( ) ; return ; } auto MIB = BuildMI ( * SetCCI . getParent ( ) , SetCCI . getIterator ( ) , SetCCI . getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) ; for ( int i = <NUM_LIT> ; i < <STR_LIT> ; ++ i ) MIB . add ( SetCCI . getOperand ( i ) ) ; MIB . addReg ( CondReg


<s> SDValue Undef = DAG . getUNDEF ( SveVT ) ; if ( VT . isFloatingPoint ( ) ) Src0 = DAG . getNode ( <STR_LIT> , DL , VT . changeTypeToInteger ( ) , Src0 ) ; Src0 = DAG . getNode ( <STR_LIT> , DL , NeonVT , Src0 ) ; Mask = DAG . getNode ( <STR_LIT> , DL , NeonVT , Mask ) ; Idxs = DAG . getNode ( <STR_LIT> , DL , NeonVT , Idxs ) ; Src0 = DAG . getTargetInsertSubreg ( <STR_LIT> , DL , SveVT , Undef , Src0 ) ; Mask = DAG . getTargetInsertSubreg ( <STR_LIT> , DL , SveVT , Undef , Mask ) ; Idxs = DAG . getTargetInsertSubreg ( <STR_LIT> , DL , SveVT , Undef , Idxs ) ; EVT PredVT = SveVT . changeVectorElementType ( <STR_LIT> ) ; SDValue Pg = getPTrue ( DAG , DL , PredVT , ( NumEls == <NUM_LIT> ) ? VL2 : VL4 ) ; Mask = DAG . getNode ( <STR_LIT> , DL , PredVT , Mask ) ; Mask = DAG . getNode ( <STR_LIT> , DL , PredVT , Mask , Pg ) ; EVT MemVT = MGN -> getMemoryVT ( ) . changeTypeToInteger ( ) ; <STR_LIT> Ext = MGN -> getExtensionType


<s> for ( unsigned i = <NUM_LIT> , e = MI . getNumOperands ( ) ; i != e ; ++ i ) { MachineOperand & MO = MI . getOperand ( i ) ; if ( i == OpNo ) { assert ( MO . isReg ( ) && <STR_LIT> ) ; addOperands ( MIB , MOs , PtrOffset ) ; } else { MIB . add ( MO ) ; } } updateOperandRegConstraints ( MF , * NewMI , TII ) ; if ( MI . getFlag ( MachineInstr :: MIFlag :: NoFPExcept ) ) NewMI -> setFlag ( MachineInstr :: MIFlag :: NoFPExcept ) ; MachineBasicBlock * MBB = InsertPt -> getParent ( ) ; MBB -> insert ( InsertPt , NewMI


<s> std :: unique_ptr < ScheduleDAGMutation > createPowerPCMacroFusionDAGMutation ( ) { return createMacroFusionDAGMutation (


<s> static unsigned int arm_autovectorize_vector_modes ( vector_modes * modes , bool ) { if ( ! TARGET_NEON_VECTORIZE_DOUBLE ) { modes -> safe_push ( V16QImode ) ; modes -> safe_push ( V8QImode )


<s> return __builtin_mve_vabdq_m_fv8hf ( __arm_vuninitializedq_f16 ( ) , __a , __b ,


<s> if ( TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . isTargetDarwin ( ) ) return new


<s> operands [ <NUM_LIT> ] = force_reg ( mode , operands [ <NUM_LIT> ] ) ; debug_rtx ( operands [ <NUM_LIT> ] ) ; } parts = <NUM_LIT> ; fprintf ( stderr , <STR_LIT> , ! can_create_pseudo_p ( ) , split_all ) ; debug_rtx ( operands [ <NUM_LIT> ] ) ; debug_rtx ( operands [ <NUM_LIT> ] ) ; if ( satisfies_constraint_Ss ( operands [ <NUM_LIT> ] ) ) split_all = <NUM_LIT> ; if ( TARGET_A16 && ( far_addr_space_p ( operands [ <NUM_LIT> ] ) || far_addr_space_p ( operands [ <NUM_LIT> ] ) ) ) split_all |= <NUM_LIT> ; if ( TARGET_A24 && split_all != <NUM_LIT> && ( mode == SImode || mode == PSImode ) && ! ( GET_CODE ( operands [ <NUM_LIT> ] ) == MEM && GET_CODE ( XEXP ( operands [ <NUM_LIT> ] , <NUM_LIT> ) ) == POST_INC ) ) return <NUM_LIT> ; for ( si = <NUM_LIT> ; si < parts ; si ++ ) { d [ si ] = m32c_subreg ( submode , operands [ <NUM_LIT> ] , mode , si * GET_MODE_SIZE ( submode ) ) ; s [ si ] = m32c_subreg ( submode , operands [ <NUM_LIT> ] , mode , si * GET_MODE_SIZE ( submode ) ) ; } if ( GET_CODE ( d [ <NUM_LIT> ] ) == MEM && GET_CODE ( XEXP ( d [ <NUM_LIT> ] , <NUM_LIT> ) ) == PRE_DEC ) { for ( si = parts - <NUM_LIT> ; si >= <NUM_LIT> ; si -- ) { ops [ opi ++ ] = gen_rtx_MEM ( submode , gen_rtx_PRE_DEC ( Pmode , gen_rtx_REG ( Pmode , SP_REGNO ) ) ) ; ops [ opi ++ ] = s [ si ] ; } rv = <NUM_LIT> ; } else if ( GET_CODE ( s [ <NUM_LIT> ] ) == MEM && GET_CODE ( XEXP ( s [ <NUM_LIT> ] , <NUM_LIT> ) ) == POST_INC ) { for ( di = <NUM_LIT> ; di < parts ; di ++ ) { ops [ opi ++ ] = d [ di ] ; ops [ opi ++ ] = gen_rtx_MEM ( submode , gen_rtx_POST_INC ( Pmode , gen_rtx_REG ( Pmode , SP_REGNO ) ) ) ; } rv = <NUM_LIT>


<s> bool IsS32 ( ) const { return ThisABI ==


<s> const <ISA_LIT>InstrInfo & TII = * static_cast < const <ISA_LIT>InstrInfo * > ( MF . getTarget ( ) . getInstrInfo ( ) ) ; DebugLoc dl = MBBI -> getDebugLoc ( ) ; int FPOffset = TFI -> getFPStackOffset ( ) ; int RAOffset = TFI -> getRAStackOffset ( ) ; if ( hasFP ( MF ) ) { BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( FPOffset ) ; } if ( MFI -> adjustsStack ( ) ) { BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( RAOffset ) ; } int StackSize = ( int ) MFI ->


<s> std :: vector < GlobalVariable * > LDSGlobals = <STR_LIT> ( M ) ; llvm :: erase_if ( LDSGlobals , [ & ] ( GlobalVariable * GV ) { return shouldIgnorePointerReplacement ( GV ) ; }


<s> static MCInstrInfo * create<ISA_LIT>MCInstrInfo ( ) { MCInstrInfo * X = new MCInstrInfo ( ) ; Init<ISA_LIT>MCInstrInfo ( X


<s> if ( Src0 -> isReg ( ) ) { unsigned Reg = Src0 -> getReg ( ) ; MachineInstr * Def = MRI . getUniqueVRegDef ( Reg ) ; if ( Def && Def -> isMoveImmediate ( ) ) { MachineOperand & MovSrc = Def -> getOperand ( <NUM_LIT> ) ; bool ConstantFolded = false ; if ( MovSrc . isImm ( ) && isUInt < <NUM_LIT> > ( MovSrc . getImm ( ) ) ) { Src0 -> ChangeToImmediate ( MovSrc . getImm ( ) ) ; ConstantFolded = true


<s> default : llvm_unreachable ( <STR_LIT> ) ; case AtomicRMWInst :: Xchg : return <STR_LIT> ; case AtomicRMWInst :: Add : return <STR_LIT> ; case AtomicRMWInst :: Sub : return <STR_LIT> ; case AtomicRMWInst :: Nand : return <STR_LIT> ; case AtomicRMWInst :: Max : return <STR_LIT> ; case AtomicRMWInst :: Min : return <STR_LIT> ; case AtomicRMWInst :: UMax : return <STR_LIT> ; case AtomicRMWInst :: UMin : return <STR_LIT> ; } } if ( XLen == <NUM_LIT> ) { switch ( BinOp ) { default : llvm_unreachable ( <STR_LIT> ) ; case AtomicRMWInst :: Xchg : return <STR_LIT> ; case AtomicRMWInst :: Add : return <STR_LIT> ; case AtomicRMWInst :: Sub : return <STR_LIT> ; case AtomicRMWInst :: Nand : return <STR_LIT> ; case AtomicRMWInst ::


<s> assert ( ( VT . is128BitVector ( ) && ( VT . getScalarSizeInBits ( ) == <NUM_LIT> || VT . getScalarSizeInBits ( ) == <NUM_LIT> ) ) && <STR_LIT> ) ; if ( ! N0 . hasOneUse ( ) || ! N1 . hasOneUse ( ) || N0 . getOpcode ( ) != <STR_LIT> || N1 . getOpcode ( ) != <STR_LIT> || N0 . getOperand ( <NUM_LIT> ) != N1 . getOperand ( <NUM_LIT> ) ) return SDValue ( ) ; SDValue WideVec = N0 . getOperand ( <NUM_LIT> ) ; MVT WideVT = WideVec . getSimpleValueType ( ) ; if ( ! WideVT . is256BitVector ( ) || ! isa < ConstantSDNode > ( N0 . getOperand ( <NUM_LIT> ) ) || ! isa < ConstantSDNode > ( N1 . getOperand ( <NUM_LIT> ) ) ) return SDValue ( ) ; unsigned NumElts = VT . getVectorNumElements ( ) ; SmallVector < int , <NUM_LIT> > NewMask ( Mask . begin ( ) , Mask . end ( ) ) ; const APInt & ExtIndex0 = N0 . getConstantOperandAPInt ( <NUM_LIT>


<s> unsigned width = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned const4 = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned s1 = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned is32Bit = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; if ( ! is32Bit ) return MCDisassembler :: Fail ; DecodeStatus status = DecodeDataRegsRegisterClass ( Inst , d , Address , Decoder ) ; if ( status != MCDisassembler :: Success ) return status ; status = DecodeDataRegsRegisterClass ( Inst , s1 , Address , Decoder ) ; if ( status != MCDisassembler :: Success ) return status ; Inst . addOperand ( MCOperand :: createImm ( const4 ) ) ; status = DecodeDataRegsRegisterClass ( Inst , s3 , Address


<s> const <ISA_LIT>BaseInstrInfo * TII = static_cast < const <ISA_LIT>BaseInstrInfo * > ( getTargetMachine ( ) . getInstrInfo ( ) ) ; MCID = & TII -> get ( NewOpc ) ; assert ( MCID -> getNumOperands ( ) == MI -> getDesc ( ) . getNumOperands ( ) + <NUM_LIT> && <STR_LIT> ) ; MI -> setDesc ( * MCID ) ; MI -> addOperand ( MachineOperand :: CreateReg ( <NUM_LIT> , true ) ) ; } unsigned ccOutIdx = MCID -> getNumOperands ( ) - <NUM_LIT> ; if ( ! MCID -> hasOptionalDef ( ) || ! MCID -> OpInfo [ ccOutIdx ] . isOptionalDef ( ) ) { assert ( ! NewOpc && <STR_LIT> ) ; return ; } bool definesCPSR = false ; bool deadCPSR = false ; for ( unsigned i = MCID -> getNumOperands ( ) , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) { const MachineOperand & MO = MI -> getOperand ( i ) ; if ( MO . isReg ( ) && MO . isDef ( ) && MO . getReg ( ) ==


<s> else { rtx v0 , v1 ; if ( ( regno - SPARC_FP_ARG_FIRST ) < SPARC_INT_ARG_MAX * <NUM_LIT> ) { int intreg ; if ( incoming ) return reg ; intreg = ( SPARC_OUTGOING_INT_ARG_FIRST + ( regno - SPARC_FP_ARG_FIRST ) / <NUM_LIT> ) ; v0 = gen_rtx_EXPR_LIST ( VOIDmode , reg , const0_rtx ) ; v1 = gen_rtx_EXPR_LIST ( VOIDmode , gen_rtx_REG ( mode , intreg ) , const0_rtx ) ; return gen_rtx_PARALLEL ( mode , gen_rtvec ( <NUM_LIT> , v0 , v1 ) ) ; } else { v0 = gen_rtx_EXPR_LIST ( VOIDmode , NULL_RTX , const0_rtx ) ; v1 = gen_rtx_EXPR_LIST ( VOIDmode , reg , const0_rtx ) ; return gen_rtx_PARALLEL ( mode , gen_rtvec ( <NUM_LIT> , v0 , v1 ) ) ; } } } else if ( type && AGGREGATE_TYPE_P ( type ) ) { HOST_WIDE_INT size = int_size_in_bytes ( type ) ; gcc_assert ( size <=


<s> for ( cpu = & cpu_table [ <NUM_LIT> ] ; cpu -> name ; ++ cpu ) if ( ! strcmp ( sel -> string , cpu -> name ) ) { if ( sel -> set_tune_p ) sparc_cpu = cpu -> processor ; if ( sel -> set_arch_p ) { target_flags &= ~ cpu -> disable ; target_flags |= cpu -> enable ; } break ; } if ( ! cpu -> name ) error ( <STR_LIT> , sel -> string , sel -> name ) ; } } if ( fpu_option_set ) target_flags = ( target_flags & ~ MASK_FPU ) | fpu ; if ( ! TARGET_FPU ) target_flags &= ~ MASK_VIS ; if ( TARGET_VIS || TARGET_ARCH64 ) { target_flags |= MASK_V9 ; target_flags &= ~ ( MASK_V8 | MASK_SPARCLET | MASK_SPARCLITE ) ; } if ( TARGET_V9 && TARGET_ARCH32 ) target_flags |= MASK_DEPRECATED_V8_INSNS ; if ( ! TARGET_V9 || TARGET_ARCH64 ) target_flags &= ~ MASK_V8PLUS ; if ( TARGET_ARCH32 ) target_flags &= ~ MASK_STACK_BIAS ; if ( align_functions == <NUM_LIT> && ( sparc_cpu == PROCESSOR_ULTRASPARC || sparc_cpu == PROCESSOR_ULTRASPARC3 ) ) align_functions = <NUM_LIT> ; if ( flag_pcc_struct_return == DEFAULT_PCC_STRUCT_RETURN ) flag_pcc_struct_return = ( TARGET_ARCH64 ? <NUM_LIT> : <NUM_LIT> ) ; if ( ! TARGET_ARCH64 ) targetm . asm_out . unaligned_op . di = NULL ; sparc_init_modes ( ) ; sparc_sr_alias_set = new_alias_set ( ) ; struct_value_alias_set = new_alias_set ( ) ; init_machine_status = sparc_init_machine_status ; switch ( sparc_cpu ) { case PROCESSOR_V7 : case PROCESSOR_CYPRESS : sparc_costs = & cypress_costs ; break ; case PROCESSOR_V8 : case PROCESSOR_SPARCLITE : case PROCESSOR_SUPERSPARC : sparc_costs = & supersparc_costs ; break ; case PROCESSOR_F930 : case PROCESSOR_F934 : case PROCESSOR_HYPERSPARC : case PROCESSOR_SPARCLITE86X : sparc_costs = & hypersparc_costs ; break ; case PROCESSOR_SPARCLET : case PROCESSOR_TSC701 : sparc_costs = & sparclet_costs ; break ; case PROCESSOR_V9 : case PROCESSOR_ULTRASPARC : sparc_costs = & ultrasparc_costs ; break ; case PROCESSOR_ULTRASPARC3 : sparc_costs = & ultrasparc3_costs


<s> RegisterTargetMachine < <ISA_LIT>TargetMachine > X ( getThe<ISA_LIT>leTarget ( ) ) ; RegisterTargetMachine < <ISA_LIT>TargetMachine > Y ( getThe<ISA_LIT>beTarget ( ) ) ; RegisterTargetMachine < <ISA_LIT>TargetMachine > Z ( getThe<ISA_LIT>Target ( ) ) ; PassRegistry & PR = * PassRegistry ::


<s> return new <ISA_LIT>SETargetLowering ( TM


<s> SDValue <ISA_LIT>TargetLowering :: SaveC0 ( SDValue Chain , const SDLoc & DL , SelectionDAG & DAG ) const { MachineFunction & MF = DAG . getMachineFunction ( ) ; auto * FI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; SDValue GetC0Ops [ ] = { DAG . getTargetConstant ( <STR_LIT> , DL , <STR_LIT> ) , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) } ; SDValue GetC0 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , GetC0Ops ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; unsigned C0VirtReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; SDValue C0VirtRegNode = DAG . getCopyToReg ( Chain


<s> return StringSwitch < <ISA_LIT>MCExpr :: VariantKind > ( name ) . Case ( <STR_LIT> , VK_<ISA_LIT>_LO ) . Case ( <STR_LIT> , VK_<ISA_LIT>_HI ) . Case (

<STR_LIT> , VK_<ISA_LIT>_PCREL_LO ) . Case ( <STR_LIT> , VK_<ISA_LIT>_PCREL_HI ) . Case ( <STR_LIT> , VK_<ISA_LIT>_GOT_HI ) . Default ( VK_<ISA_LIT>_Invalid ) ;


<s> static std :: unique_ptr < <ISA_LIT>Operand > CreateShiftedImm ( const MCExpr * Val , unsigned ShiftAmount , SMLoc S , SMLoc E , MCContext & Ctx ) { auto Op = make_unique < <ISA_LIT>Operand > ( k_ShiftedImm , Ctx ) ; Op -> ShiftedImm . Val = Val ; Op -> ShiftedImm . ShiftAmount = ShiftAmount ; Op -> StartLoc = S ; Op -> EndLoc = E ; return Op


<s> if ( C . Chain ) return ; auto * C1 = dyn_cast < ConstantFPSDNode > ( C . Op1 ) ; if ( C1 && C1 -> isZero ( ) ) { for ( auto I = C . Op0 -> use_begin ( ) , E = C . Op0 -> use_end ( ) ; I != E ; ++ I ) { SDNode * N =


<s> if ( PAN :: isLocalName ( DIGV . getGlobal ( ) -> getName ( ) ) ) { ClassNo = <STR_LIT> ; } else if ( DIGV . isLocalToUnit ( ) ) ClassNo = <STR_LIT> ; else ClassNo = <STR_LIT> ; return


<s> p -> next = extern_head ; p -> decl = decl ; p -> name


<s> emit_move_insn ( gpos , gen_rtx_SUBREG ( SImode , gpos_qi , <NUM_LIT> ) ) ; emit_cmp_and_jump_insns ( gpos , loadlen , GE , NULL_RTX , SImode , <NUM_LIT> , full_label ) ; emit_insn ( gen_vstlv16qi ( vsrc , gpos , dst ) ) ; force_expand_binop ( Pmode , add_optab , dst_addr , gpos , result , <NUM_LIT> , OPTAB_DIRECT ) ; emit_jump ( exit_label ) ; emit_barrier ( ) ; emit_label ( full_label ) ; LABEL_NUSES ( full_label ) = <NUM_LIT> ; force_expand_binop ( Pmode , and_optab , src_addr , GEN_INT ( <NUM_LIT> ) , temp , <NUM_LIT> , OPTAB_DIRECT ) ; emit_move_insn ( offset , GEN_INT ( <NUM_LIT> ) ) ; force_expand_binop ( Pmode , sub_optab , offset , temp , offset , <NUM_LIT> , OPTAB_DIRECT ) ; emit_insn ( gen_vstlv16qi ( vsrc , gen_lowpart ( SImode , offset ) , dst ) ) ; force_expand_binop ( Pmode , add_optab , offset , const1_rtx , offset , <NUM_LIT> , OPTAB_DIRECT ) ; emit_move_insn ( src_addr_reg , src_addr ) ; emit_move_insn ( dst_addr_reg , dst_addr ) ; emit_label ( loop_label ) ; LABEL_NUSES ( loop_label ) = <NUM_LIT> ; emit_move_insn ( vsrc , gen_rtx_MEM ( V16QImode , gen_rtx_PLUS ( Pmode , src_addr_reg , offset ) ) ) ; emit_insn ( gen_vec_vfenesv16qi ( vpos , vsrc , vsrc , GEN_INT ( VSTRING_FLAG_ZS | VSTRING_FLAG_CS ) ) ) ; add_int_reg_note ( s390_emit_ccraw_jump ( <NUM_LIT> , EQ , done_label ) , REG_BR_PROB , profile_probability :: very_unlikely ( ) . to_reg_br_prob_note ( ) ) ; emit_move_insn ( gen_rtx_MEM ( V16QImode , gen_rtx_PLUS ( Pmode , dst_addr_reg , offset ) ) , vsrc ) ; force_expand_binop ( Pmode , add_optab , offset , GEN_INT ( <NUM_LIT> ) , offset , <NUM_LIT> , OPTAB_DIRECT ) ; emit_jump ( loop_label ) ; emit_barrier ( ) ; emit_label ( done_label ) ; LABEL_NUSES ( done_label ) = <NUM_LIT> ; force_expand_binop ( Pmode , add_optab , dst_addr_reg , offset , dst_addr_reg , <NUM_LIT> , OPTAB_DIRECT ) ; emit_insn ( gen_vec_extractv16qiqi ( gpos_qi , vpos , GEN_INT ( <NUM_LIT> ) )


<s> auto Fma0 = B . buildFMA ( S32 , NegDivScale0 , ApproxRcp , One , Flags ) ; auto Fma1 = B . buildFMA ( S32 , Fma0 , ApproxRcp , ApproxRcp , Flags ) ; auto Mul = B . buildFMul ( S32 , NumeratorScaled , Fma1 , Flags ) ; auto Fma2 = B . buildFMA ( S32 , NegDivScale0 , Mul , NumeratorScaled , Flags ) ; auto Fma3 = B . buildFMA ( S32 , Fma2 , Fma1 , Mul , Flags ) ; auto Fma4 = B . buildFMA ( S32 , NegDivScale0 , Fma3 , NumeratorScaled , Flags ) ; if ( ! Mode . allFP32Denormals ( ) ) toggleSPDenormMode ( false , B , ST , Mode ) ; auto Fmas = B . buildIntrinsic ( <STR_LIT> , { S32 } , false ) . addUse ( Fma4 . getReg ( <NUM_LIT> ) ) . addUse ( Fma1 . getReg ( <NUM_LIT> ) ) . addUse ( Fma3 .

getReg ( <NUM_LIT> ) ) . addUse ( NumeratorScaled . getReg ( <NUM_LIT> ) ) . setMIFlags ( Flags ) ;


<s> assert ( V2 . getSimpleValueType ( ) == <STR_LIT> && <STR_LIT> ) ; ShuffleVectorSDNode * SVOp = cast < ShuffleVectorSDNode > ( Op ) ; ArrayRef < int > Mask = SVOp -> getMask ( ) ; assert ( Mask . size ( ) == <NUM_LIT> && <STR_LIT> ) ; if ( SDValue Shuf128 = lowerV4X128VectorShuffle ( DL , <STR_LIT> , Mask , V1 , V2 , DAG ) ) return Shuf128 ; if ( SDValue Unpck = lowerVectorShuffleWithUNPCK ( DL , <STR_LIT> , Mask , V1 , V2 , DAG ) ) return Unpck ; return lowerVectorShuffleWithPERMV ( DL , <STR_LIT> , Mask , V1 ,


<s> void <ISA_LIT>RegisterInfo :: processFunctionBeforeFrameFinalized ( MachineFunction &


<s> SDValue <ISA_LIT>TargetLowering :: LowerLibCall ( RTLIB :: Libcall LC8 , RTLIB :: Libcall LC16 , RTLIB :: Libcall LC24 , RTLIB :: Libcall LC32 , SDValue Op , SelectionDAG & DAG ) const { RTLIB :: Libcall LC ; assert ( Op . getSimpleValueType ( ) . isInteger ( ) && <STR_LIT> ) ; switch ( Op . getValueSizeInBits ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <NUM_LIT> : LC = LC8 ; break ; case <NUM_LIT> : LC = LC16 ; break ; case <NUM_LIT> : LC = LC24 ; break ; case <NUM_LIT> : LC = LC32 ; break ; } SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . reserve ( Op .


<s> LLVMTargetMachine ( T , <STR_LIT> , TT , CPU , FS , Options , RM . getValueOr ( Reloc :: Model :: Static ) , CM . getValueOr ( CodeModel :: Model :: Tiny ) , OL ) , TLOF ( std :: make_unique < TargetLoweringObjectFileELF > ( ) ) , DefaultSubtarget ( TT , CPU , FS , * this ) { initAsmInfo ( )


<s> int s390_label_align ( rtx_insn * label ) { rtx_insn * prev_insn = prev_active_insn ( label ) ; rtx set , src ; if ( prev_insn == NULL_RTX ) goto old ; set = single_set ( prev_insn ) ; if ( set == NULL_RTX ) goto


<s> if ( RegNo & <NUM_LIT> ) return Fail ; unsigned Register = GPR64x8DecoderTable [ RegNo >> <NUM_LIT> ] ; Inst . addOperand ( MCOperand :: createReg ( Register ) ) ; return Success


<s> gcc_assert ( GET_CODE ( dest ) == MEM ) ; dest = XEXP ( dest , <NUM_LIT> ) ; if ( ! CONSTANT_P ( dest ) && GET_CODE ( dest ) != REG ) dest = force_reg ( Pmode , dest ) ; if ( retval == NULL ) mode = VOIDmode ; else mode = GET_MODE ( retval ) ; call = gen_rtx_CALL ( mode , gen_rtx_MEM ( FUNCTION_MODE , dest ) , counter ) ; if ( retval ) call = gen_rtx_SET ( VOIDmode , retval , call ) ; if ( ! CONSTANT_P ( dest ) ) { temp = gen_reg_rtx ( HImode ) ; emit_move_insn ( temp , const0_rtx ) ; } else temp = const0_rtx ; call = gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( <NUM_LIT> , call , gen_rtx_USE ( VOIDmode , temp )


<s> case TargetOpcode :: COPY : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case


<s> return ; } if ( ! vector_config_insn_p ( insn -> rtl ( ) ) && ! has_vtype_op ( insn -> rtl ( ) ) && ( find_access ( insn -> defs ( ) , VL_REGNUM ) || find_access ( insn -> defs ( ) , VTYPE_REGNUM ) ) ) { set_unknown ( ) ; return ; } if ( ! vector_config_insn_p ( insn -> rtl ( ) ) && ! has_vtype_op ( insn -> rtl ( ) ) ) return ; vl_vtype_info :: operator = ( get_vl_vtype_info ( insn ) ) ; m_insn = insn ; m_state = VALID ; if ( vector_config_insn_p ( insn -> rtl ( ) ) ) { m_demands [ DEMAND_AVL ] = true ; m_demands [ DEMAND_RATIO ] = true ; return ; } if ( has_vl_op ( insn -> rtl ( ) ) ) m_demands [ DEMAND_AVL ] = true ; if ( get_attr_ratio ( insn -> rtl ( ) ) != INVALID_ATTRIBUTE ) m_demands [ DEMAND_RATIO ] = true ; else { m_demands [ DEMAND_SEW ] = true ; if ( ! ignore_vlmul_insn_p ( insn -> rtl ( ) ) ) m_demands [ DEMAND_LMUL ] = true ; } if ( get_attr_ta ( insn -> rtl ( ) ) != INVALID_ATTRIBUTE ) m_demands [ DEMAND_TAIL_POLICY ] = true ; if ( get_attr_ma ( insn -> rtl ( ) ) != INVALID_ATTRIBUTE ) m_demands [ DEMAND_MASK_POLICY ] = true ; if ( vector_config_insn_p ( insn -> rtl ( ) ) ) return ; if ( scalar_move_insn_p ( insn ->


<s> MCOperand MCOp ; if ( Lower<ISA_LIT>MachineOperandToMCOperand ( MI -> getOperand ( i ) , MCOp , AP , isDarwin


<s> MIB . setMIFlags ( MachineInstr :: FrameSetup ) ; } static const unsigned AllCopyRegs [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; static const unsigned AllHighRegs [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; const unsigned * AllCopyRegsEnd = std :: end ( AllCopyRegs ) ; const unsigned * AllHighRegsEnd = std :: end ( AllHighRegs ) ; const unsigned * HiRegToSave = findNextOrderedReg ( std :: begin ( AllHighRegs ) , HiRegsToSave , AllHighRegsEnd ) ; while ( HiRegToSave != AllHighRegsEnd ) { const unsigned * CopyReg = findNextOrderedReg ( std :: begin ( AllCopyRegs ) , CopyRegs , AllCopyRegsEnd ) ; MachineInstrBuilder PushMIB = BuildMI ( MF , DL , TII . get ( <STR_LIT> ) ) . add ( predOps ( <STR_LIT> ) ) ; SmallVector < unsigned , <NUM_LIT> > RegsToPush ; while ( HiRegToSave != AllHighRegsEnd && CopyReg != AllCopyRegsEnd ) { if ( HiRegsToSave [ * HiRegToSave ] ) { bool isKill = ! MRI . isLiveIn ( * HiRegToSave ) ; if ( isKill && ! MRI . isReserved ( * HiRegToSave ) ) MBB . addLiveIn ( * HiRegToSave ) ; BuildMI ( MBB , MI , DL , TII . get ( <STR_LIT> ) ) . addReg ( * CopyReg , RegState :: Define ) . addReg ( * HiRegToSave , getKillRegState ( isKill ) ) . add ( predOps ( <STR_LIT> ) ) ; RegsToPush . push_back ( * CopyReg ) ; CopyReg = findNextOrderedReg ( ++ CopyReg , CopyRegs ,


<s> static DecodeStatus DecodeAVLdSt_128RegisterClass ( MCInst & Inst , unsigned Imm , uint64_t Addr , const void * Decoder ) { return decodeOperand_AVLdSt_Any ( Inst , Imm , <ISA_LIT>Disassembler ::


<s> MCRegisterInfo * X = new MCRegisterInfo ( ) ; Init<ISA_LIT>MCRegisterInfo ( X , <STR_LIT> ) ; <ISA_LIT>_MC :: initLLVMToCVRegMapping ( X ) ; return


<s> SDVTList VTs = DAG . getVTList ( <STR_LIT> ) ; EVT MemVT = MSC -> getMemoryVT ( ) ; SDValue InputVT = DAG . getValueType ( MemVT ) ; if ( VT . getVectorElementType ( ) == <STR_LIT> && ! static_cast < const <ISA_LIT>Subtarget & > ( DAG . getSubtarget ( ) ) . hasBF16 ( ) ) return SDValue ( ) ; if ( IsFixedLength ) { assert ( Subtarget -> useSVEForFixedLengthVectors ( ) && <STR_LIT> ) ; IndexVT = getContainerForFixedLengthVector ( DAG , IndexVT ) ; MemVT = IndexVT . changeVectorElementType ( MemVT . getVectorElementType ( ) ) ; InputVT = DAG . getValueType ( MemVT . changeTypeToInteger ( ) ) ; StoreVal = DAG . getNode ( <STR_LIT> , DL , VT . changeTypeToInteger ( ) , StoreVal ) ; StoreVal = DAG . getNode ( <STR_LIT> , DL , VT . changeVectorElementType ( IndexVT . getVectorElementType ( ) ) , StoreVal ) ; StoreVal = convertToScalableVector ( DAG , IndexVT , StoreVal ) ; } else if ( VT . isFloatingPoint ( ) ) { EVT StoreValVT = getPackedSVEVectorVT ( VT . getVectorElementCount ( ) ) ; StoreVal = getSVESafeBitCast ( StoreValVT , StoreVal , DAG ) ; InputVT = DAG . getValueType ( MemVT . changeVectorElementTypeToInteger ( ) ) ; } if ( getGatherScatterIndexIsExtended ( Index ) ) Index = Index . getOperand ( <NUM_LIT> ) ; unsigned Opcode = getScatterVecOpcode ( IsScaled , IsSigned , NeedsExtend ) ; selectGatherScatterAddrMode ( BasePtr , Index , MemVT , Opcode , false , DAG ) ; if ( IsFixedLength ) { if ( Index . getSimpleValueType ( ) . isFixedLengthVector ( ) ) Index = convertToScalableVector ( DAG , IndexVT , Index ) ; if ( BasePtr . getSimpleValueType ( ) . isFixedLengthVector ( ) ) BasePtr = convertToScalableVector (


<s> static const MCPhysReg PredRegDecoderTable [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; return DecodeRegisterClass ( Inst , RegNo ,


<s> EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( ! VT . isVector ( ) || N -> getOperand ( <NUM_LIT> ) -> getOpcode ( ) != <STR_LIT> || N -> getOperand ( <NUM_LIT> ) -> getOperand ( <NUM_LIT> ) -> getOpcode ( ) != <STR_LIT> || VT . getSizeInBits ( ) != N -> getOperand ( <NUM_LIT> ) -> getValueType ( <NUM_LIT> ) . getSizeInBits ( ) ) return SDValue ( ) ; if ( BuildVectorSDNode * BV = dyn_cast < BuildVectorSDNode > ( N -> getOperand ( <NUM_LIT> ) -> getOperand ( <NUM_LIT> ) ) ) { if ( ! BV -> isConstant ( ) ) return SDValue ( ) ; SDLoc DL ( N ) ; EVT IntVT = BV -> getValueType ( <NUM_LIT> ) ; SDValue SourceConst = DAG . getNode ( N -> getOpcode ( ) , DL , VT , SDValue ( BV , <NUM_LIT> ) ) ; SDValue MaskConst = DAG . getNode ( <STR_LIT>


<s> addPass ( new InstructionSelect ( ) ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) addPass (

create<ISA_LIT>PostSelectOptimize ( ) ) ;


<s> } else if ( BoundCtrl == - <NUM_LIT> ) { BoundCtrl =


<s> DEBUG ( BB -> dump ( ) ) ; SelectRoot ( * CurDAG


<s> void EmitConstant ( uint64_t Val , unsigned Size , unsigned & CurByte , raw_ostream & OS ) const { for ( unsigned i = <NUM_LIT> ; i != Size ; ++ i ) { EmitByte ( Val & <NUM_LIT> , CurByte ,


<s> return decodeUImmOperand < <NUM_LIT> >


<s> if ( TM . is<ISA_LIT>64 ( ) && MF -> getInfo < <ISA_LIT>FunctionInfo > ( ) -> isSplitCSR ( ) ) return CSR_SRV464_TLS_PE_SaveList ; bool SaveR2 = MF -> getRegInfo ( ) . isAllocatable ( <STR_LIT> ) && ! Subtarget . isUsingPCRelativeCalls ( ) ; if ( MF -> getFunction ( ) . getCallingConv ( ) == CallingConv :: Cold ) { if ( TM . is<ISA_LIT>64 ( ) ) { if ( Subtarget . hasAltivec ( ) ) return SaveR2 ? CSR_SVR64_ColdCC_R2_Altivec_SaveList : CSR_SVR64_ColdCC_Altivec_SaveList ; return SaveR2 ? CSR_SVR64_ColdCC_R2_SaveList : CSR_SVR64_ColdCC_SaveList ; } if ( Subtarget . hasAltivec ( ) ) return CSR_SVR32_ColdCC_Altivec_SaveList ; else if ( Subtarget . hasSPE ( ) ) return CSR_SVR32_ColdCC_SPE_SaveList ; return CSR_SVR32_ColdCC_SaveList ; } if ( TM . is<ISA_LIT>64 (


<s> SDVTList VTs = DAG . getVTList ( VT , <STR_LIT> ) ; SDValue Result = DAG . getNode ( BaseOp , DL , VTs , LHS , RHS , Carry ) ; SDValue SetCC = emitSETCC ( DAG , DL , Result . getValue ( <NUM_LIT> ) , CCValid , CCMask ) ; if ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT> ) SetCC = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , SetCC ) ; return DAG . getNode ( <STR_LIT> , DL , N -> getVTList ( ) , Result ,


<s> bbs = get_loop_body ( loop ) ; for ( i = <NUM_LIT> ; i < loop -> num_nodes ; i ++ ) FOR_BB_INSNS ( bbs [ i ] , insn ) if ( NONDEBUG_INSN_P ( insn ) ) FOR_EACH_SUBRTX ( iter , array , PATTERN ( insn ) ,

NONCONST ) if ( const_rtx x = * iter ) if ( MEM_P ( x ) ) {


<s> bool <ISA_LIT>TargetLowering :: CanLowerReturn ( CallingConv :: ID CallConv , MachineFunction & MF , bool isVarArg , const SmallVectorImpl < <STR_LIT> > & Outs , LLVMContext & Context ) const { if ( Subtarget . hasVector ( ) ) VerifyVectorTypes ( Outs ) ; for ( auto & Out : Outs ) if ( Out . ArgVT == <STR_LIT> ) return false ; SmallVector < CCValAssign , <NUM_LIT> > RetLocs ; CCState RetCCInfo ( CallConv , isVarArg , MF , RetLocs , Context ) ; return RetCCInfo . CheckReturn ( Outs ,


<s> return strncmp ( DLL_IMPORT_PREFIX , symbol , strlen (


<s> if ( aarch64_vector_data_mode_p ( mode1 ) && aarch64_vector_data_mode_p ( mode2 ) ) return true ; if ( aarch64_vector_mode_supported_p ( mode1 ) || aarch64_vector_mode_supported_p ( mode2 ) )


<s> break ; default : OffsetIdx = InvalidOffsetIdx ; break ; } if ( OffsetIdx != InvalidOffsetIdx ) { DemandedElts &= ~ ( ( <NUM_LIT> << UnusedComponentsAtFront ) - <NUM_LIT> ) ; auto * Offset = II . getArgOperand ( OffsetIdx ) ; unsigned SingleComponentSizeInBits = IC . getDataLayout ( ) . getTypeSizeInBits ( II . getType ( ) -> getScalarType ( ) ) ; unsigned OffsetAdd = UnusedComponentsAtFront * SingleComponentSizeInBits / <NUM_LIT> ; auto * OffsetAddVal = ConstantInt :: get ( Offset -> getType ( ) , OffsetAdd ) ; Args [ OffsetIdx ] = IC . Builder . CreateAdd ( Offset , OffsetAddVal ) ; } } } else { ConstantInt * DMask = cast < ConstantInt > ( II . getArgOperand ( DMaskIdx ) ) ; unsigned DMaskVal = DMask -> getZExtValue ( ) & <NUM_LIT> ; DemandedElts &= ( <NUM_LIT> << countPopulation ( DMaskVal ) ) - <NUM_LIT> ; unsigned NewDMaskVal = <NUM_LIT> ; unsigned OrigLoadIdx = <NUM_LIT> ; for ( unsigned SrcIdx = <NUM_LIT> ; SrcIdx < <NUM_LIT> ; ++ SrcIdx ) { const unsigned Bit = <NUM_LIT> << SrcIdx ; if ( ! ! ( DMaskVal & Bit ) ) { if ( ! ! DemandedElts [ OrigLoadIdx ] ) NewDMaskVal |= Bit ; OrigLoadIdx ++ ; } } if ( DMaskVal != NewDMaskVal ) Args [ DMaskIdx ] = ConstantInt :: get ( DMask -> getType ( ) , NewDMaskVal ) ; } unsigned NewNumElts = DemandedElts . countPopulation ( ) ; if ( ! NewNumElts ) return UndefValue :: get ( II . getType ( ) ) ; if ( NewNumElts >= VWidth && DemandedElts . isMask ( ) ) { if ( DMaskIdx >= <NUM_LIT> ) II . setArgOperand ( DMaskIdx , Args [ DMaskIdx


<s> rtx base , offset ; if ( splittable_const_int_operand ( src , mode ) ) { mips_move_integer ( dest , dest , INTVAL ( src ) ) ; return ; } if ( mips_split_symbol ( dest , src , MAX_MACHINE_MODE , & src ) ) { emit_insn ( gen_rtx_SET ( VOIDmode , dest , src ) ) ; return ; } if ( mips_tls_symbol_p ( src ) ) { mips_emit_move ( dest , mips_legitimize_tls_address ( src ) ) ; return ; } split_const ( src , & base , & offset ) ; if ( offset != const0_rtx && ( targetm . cannot_force_const_mem ( mode , src ) || ( ! TARGET_MIPS16 && can_create_pseudo_p ( )


<s> unsigned off18 = ( off18_0 << <NUM_LIT> ) | ( off18_1 << <NUM_LIT> ) | ( off18_2 << <NUM_LIT> ) | ( off18_3 << <NUM_LIT> ) ; unsigned s1_d = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned is32Bit = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; if ( ! is32Bit ) return MCDisassembler ::


<s> rtx label = operands [ <NUM_LIT> ] ; emit_insn ( gen_rtx_SET ( gen_rtx_REG ( CCFPmode , <NUM_LIT> ) , gen_rtx_fmt_ee ( code , CCFPmode , operand0 , operand1 ) ) ) ; emit_jump_insn ( gen_rtx_SET ( pc_rtx , gen_rtx_IF_THEN_ELSE ( VOIDmode , gen_rtx_fmt_ee ( NE , VOIDmode , gen_rtx_REG ( CCFPmode , <NUM_LIT> ) , const0_rtx

) , gen_rtx_LABEL_REF ( VOIDmode , label ) , pc_rtx ) ) ) ;


<s> case <STR_LIT> : case <STR_LIT> : return getUsefulBitsFromAndWithImmediate ( SDValue ( UserNode , <NUM_LIT> ) , UsefulBits , Depth ) ; case <STR_LIT> : case <STR_LIT> : return getUsefulBitsFromUBFM ( SDValue ( UserNode , <NUM_LIT> ) , UsefulBits , Depth ) ; case <STR_LIT> : case <STR_LIT> : if ( UserNode -> getOperand ( <NUM_LIT> ) != Orig && UserNode -> getOperand ( <NUM_LIT> ) == Orig ) getUsefulBitsFromOrWithShiftedReg ( SDValue ( UserNode , <NUM_LIT> ) , UsefulBits , Depth ) ; return ; case <STR_LIT> : case <STR_LIT>


<s> unsigned Opc = TFL -> getStackGrowthDirection ( ) == TargetFrameLowering :: StackGrowsUp ? <STR_LIT> : <STR_LIT> ; SDValue ScaledSize = DAG . getNode ( <STR_LIT> , dl , VT , Size , DAG . getConstant ( ST . getWavefrontSizeLog2 ( ) , dl , <STR_LIT> ) ) ; unsigned StackAlign = TFL -> getStackAlignment ( ) ; Tmp1 = DAG . getNode ( Opc , dl , VT , SP , ScaledSize ) ; if ( Align > StackAlign ) { Tmp1 = DAG . getNode ( <STR_LIT> , dl , VT , Tmp1 , DAG . getConstant ( - ( uint64_t ) Align << ST . getWavefrontSizeLog2


<s> unsigned <ISA_LIT>RegisterInfo :: getRARegister


<s> case <STR_LIT> : return true ; case <STR_LIT> : switch ( Def -> getOperand ( <NUM_LIT> ) . getType ( ) ) { default : return false ; case MachineOperand :: MO_GlobalAddress : case MachineOperand :: MO_JumpTableIndex : case MachineOperand :: MO_ConstantPoolIndex : case MachineOperand :: MO_BlockAddress : return true ; } case <STR_LIT>


<s> Value * opr0 = CI -> getArgOperand ( <NUM_LIT> ) ; if ( ConstantFP * CF = dyn_cast < ConstantFP > ( opr0 ) ) { Value * nval = B . CreateFDiv ( ConstantFP :: get ( CF -> getType ( ) , <NUM_LIT> ) , opr0 , <STR_LIT> ) ; DEBUG ( errs ( ) << <STR_LIT> << * CI << <STR_LIT> << * nval << <STR_LIT> ) ; replaceCall ( nval


<s> bool <ISA_LIT>InstrInfo :: isHighLatencyDef ( int Opc ) const { return get ( Opc ) . mayLoad ( ) && ( isMUBUF ( Opc ) ||

isMTBUF ( Opc ) || isMIMG ( Opc ) || isFLAT ( Opc ) ) ;


<s> switch ( ( insn >> <NUM_LIT> ) & <NUM_LIT> ) { default :


<s> Type * Ty = FDiv . getType ( ) ; if ( ! Ty -> getScalarType ( ) -> isFloatTy ( ) ) return false ; MDNode * FPMath = FDiv . getMetadata ( LLVMContext :: MD_fpmath ) ; if ( ! FPMath ) return false ; const FPMathOperator * FPOp = cast < const FPMathOperator > ( & FDiv ) ; float ULP = FPOp -> getFPAccuracy ( ) ; if ( ULP < <NUM_LIT> ) return false ; FastMathFlags FMF = FPOp -> getFastMathFlags ( ) ; bool UnsafeDiv = HasUnsafeFPMath || FMF . isFast ( ) || FMF . allowReciprocal ( ) ; if ( UnsafeDiv ) return false ; IRBuilder < > Builder ( FDiv . getParent ( ) , std :: next ( FDiv . getIterator ( ) ) , FPMath ) ; Builder . setFastMathFlags ( FMF ) ; Builder . SetCurrentDebugLocation ( FDiv . getDebugLoc ( ) ) ; Function * Decl = <STR_LIT> ( Mod , <STR_LIT> ) ; Value * Num = FDiv . getOperand


<s> <STR_LIT> AM = LD -> getAddressingMode ( ) ; if ( LD -> getExtensionType ( ) != <STR_LIT> || AM != <STR_LIT> ) { return <NUM_LIT> ; } unsigned Opcode = <NUM_LIT> ; int Offs = cast < ConstantSDNode > ( LD -> getOffset ( ) ) -> getSExtValue ( ) ; switch ( VT . SimpleTy ) { case <STR_LIT> : { if ( Offs != <NUM_LIT> ) { return <NUM_LIT> ; } Opcode = <STR_LIT> ; break ; } case <STR_LIT> : { if ( Offs != <NUM_LIT> )


<s> unsigned tmpReg = GuardsReg ; int bitpos = TRI -> getS0Index ( predReg ) ; assert ( bitpos > <NUM_LIT> ) ; AddDefaultPred ( BuildMI ( MBB , MI , DL , TII -> get ( <STR_LIT> ) , tmpReg ) ) . addFrameIndex ( fi ) . addImm ( <NUM_LIT> ) ; BuildMI ( MBB , MI , DL , TII -> get ( <STR_LIT> ) , tmpReg ) . addReg ( guard ) . addImm ( <NUM_LIT> ) . addReg ( tmpReg ) . addImm ( bitpos ) . addOperand ( Cond [ <NUM_LIT> ] ) . addOperand ( Cond [ <NUM_LIT> ] ) ; InsertedInstrs ++ ; uint32_t or_bitmask = <NUM_LIT> << bitpos ; AddDefaultPred ( BuildMI ( MBB , MI , DL , TII -> get ( <STR_LIT> ) , PRTmp ) ) . addReg ( guard ) . addImm ( <NUM_LIT> ) . addOperand ( Cond [ <NUM_LIT> ] ) . addOperand ( Cond [ <NUM_LIT> ] ) ; assert ( isUInt < <NUM_LIT> > ( or_bitmask ) ; BuildMI ( MBB , MI , DL , TII -> get ( <STR_LIT> ) , tmpReg ) . addReg ( PRTmp ) . addImm ( <NUM_LIT> )

. addReg ( tmpReg ) . addImm ( or_bitmask ) ;


<s> void <ISA_LIT>AsmInstCompress :: EmitInstruction ( MCInst & Inst , MCStreamer & Out


<s> label = ix86_expand_sse_compare_and_jump ( UNLE , TWO52 , xa , false ) ; if ( flag_rounding_math ) { ix86_sse_copysign_to_positive ( TWO52 , TWO52 , res , mask ) ; xa = res ; } xa = expand_simple_binop ( mode , PLUS , xa , TWO52 , NULL_RTX , <NUM_LIT> , OPTAB_DIRECT ) ; xa = expand_simple_binop ( mode , MINUS , xa , TWO52 , xa , <NUM_LIT> , OPTAB_DIRECT ) ; if ( HONOR_SIGNED_ZEROS ( mode ) && flag_rounding_math ) xa = ix86_expand_sse_fabs ( xa , NULL ) ; ix86_sse_copysign_to_positive ( res , xa , res , mask ) ; emit_label (


<s> unsigned RegClassID = G -> getStart ( ) -> getDesc ( ) . OpInfo [ <NUM_LIT> ] . RegClass ; BitVector AvailableRegs = RS . getRegsAvailable ( TRI -> getRegClass ( RegClassID ) ) ; for ( MachineBasicBlock :: iterator I = G -> begin ( ) , E = G -> end ( ) ; I != E ; ++ I ) { RS . forward ( I ) ; AvailableRegs &= RS . getRegsAvailable ( TRI -> getRegClass ( RegClassID ) ) ; for ( auto J : I -> operands (


<s> if ( MO . isReg ( ) ) O << '%' << getRegisterName ( MO . getReg ( ) ) ; else if ( MO . isImm ( ) ) O << MO . getImm ( ) ; else if ( MO . isExpr ( ) ) MO . getExpr ( ) -> print ( O , MAI ) ; else llvm_unreachable ( <STR_LIT> )


<s> SmallVector < EVT , <NUM_LIT> > VTs ; SmallVector < uint64_t , <NUM_LIT> > Offsets ; ComputePTXValueVTs ( * this , DL , RetTy , VTs , & Offsets ) ; assert ( VTs . size ( ) == OutVals . size ( ) && <STR_LIT> ) ; auto VectorInfo = VectorizePTXValueVTs ( VTs , Offsets , RetTy -> isSized ( ) ? DL . getABITypeAlignment ( RetTy ) : <NUM_LIT> ) ; bool ExtendIntegerRetVal = RetTy -> isIntegerTy ( ) && DL . getTypeAllocSizeInBits ( RetTy ) < <NUM_LIT> ; SmallVector < SDValue , <NUM_LIT> > StoreOperands ; for ( unsigned i = <NUM_LIT> , e = VTs . size ( ) ; i != e ; ++ i ) { if ( VectorInfo [ i ] & PVF_FIRST ) { assert ( StoreOperands . empty ( ) && <STR_LIT> ) ; StoreOperands . push_back ( Chain ) ; StoreOperands . push_back ( DAG . getConstant ( Offsets [ i ] , dl , <STR_LIT> ) ) ; } SDValue RetVal = OutVals [ i ] ; if ( ExtendIntegerRetVal ) { RetVal = DAG . getNode ( Outs [ i ] . Flags . isSExt ( ) ? <STR_LIT> : <STR_LIT> , dl , <STR_LIT> , RetVal ) ; } else if ( RetVal . getValueSizeInBits ( ) < <NUM_LIT> ) { RetVal = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , RetVal ) ; } StoreOperands . push_back ( RetVal ) ; if ( VectorInfo [ i ] & PVF_LAST ) { <STR_LIT> Op ; unsigned NumElts = StoreOperands . size (


<s> return ( from == RETURN_ADDRESS_POINTER_REGNUM && ( ! leaf_function_p ( ) || ( to == GP_REG_FIRST + <NUM_LIT> && leaf_function_p ( ) ) ) ) || ( from != RETURN_ADDRESS_POINTER_REGNUM && (

to == HARD_FRAME_POINTER_REGNUM || ( to == STACK_POINTER_REGNUM && ! frame_pointer_needed ) ) ) ;


<s> unsigned idx = Count - i - <NUM_LIT> ; unsigned Reg1 = CSI [ idx ] . getReg ( ) ; unsigned Reg2 = CSI [ idx + <NUM_LIT> ] . getReg ( ) ; assert ( CSI [ idx ] . getFrameIdx ( ) + <NUM_LIT> == CSI [ idx + <NUM_LIT> ] . getFrameIdx ( ) && <STR_LIT> ) ; unsigned StrOpc ; assert ( ( Count & <NUM_LIT> ) == <NUM_LIT> && <STR_LIT> ) ; assert ( ( i & <NUM_LIT> ) == <NUM_LIT> && <STR_LIT> ) ; if ( <STR_LIT> . contains ( Reg1 ) ) { assert ( <STR_LIT> . contains ( Reg2 ) && <STR_LIT> ) ; if ( i == <NUM_LIT> ) StrOpc = <STR_LIT> ; else StrOpc = <STR_LIT> ; } else if ( <STR_LIT> . contains ( Reg1 ) ) { assert ( <STR_LIT> . contains ( Reg2 ) && <STR_LIT> ) ; if ( i == <NUM_LIT> )


<s> auto ListTmp = MIRBuilder . buildPtrAdd ( PtrTy , List , AlignMinus1 . getReg ( <NUM_LIT> ) ) ; DstPtr = MIRBuilder . buildPtrMask ( PtrTy , ListTmp , Log2_64 ( Align ) ) ; } else DstPtr = List ; uint64_t ValSize = MRI . getType ( Dst ) . getSizeInBits ( ) / <NUM_LIT> ; MIRBuilder . buildLoad ( Dst , DstPtr , * MF . getMachineMemOperand ( MachinePointerInfo ( ) , MachineMemOperand :: MOLoad , ValSize , std :: max ( Align , PtrSize ) ) ) ; auto Size = MIRBuilder . buildConstant ( IntPtrTy , alignTo ( ValSize , PtrSize ) ) ; auto NewList = MIRBuilder . buildPtrAdd ( PtrTy , DstPtr , Size . getReg ( <NUM_LIT> ) ) ; MIRBuilder . buildStore ( NewList , ListPtr , * MF . getMachineMemOperand ( MachinePointerInfo (

) , MachineMemOperand :: MOStore , PtrSize , PtrSize ) ) ;


<s> MachineInstr * DefI = MRI -> getVRegDef ( Reg . R ) ; DefI -> eraseFromParent ( ) ; return ; } for ( ; I != E ; ++ I ) { MachineInstr * UseI = I -> getParent ( ) ; if ( isConvertibleToPredForm ( UseI ) ) PUsers . insert (


<s> if ( C && isUInt < <NUM_LIT> > ( C -> getZExtValue ( ) ) ) VL = CurDAG -> getTargetConstant ( C -> getZExtValue ( )

, SDLoc ( N ) , N -> getValueType ( <NUM_LIT> ) ) ;


<s> unsigned Result = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , Result )


<s> inline bool is_so_imm ( unsigned Imm


<s> static section * loongarch_function_rodata_section ( tree decl ,


<s> static DecodeStatus DecodeCtrRegsRegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t , const void * Decoder ) { static const uint16_t CtrlRegDecoderTable [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; if ( RegNo >= sizeof ( CtrlRegDecoderTable ) / sizeof ( CtrlRegDecoderTable [ <NUM_LIT> ] ) ) return MCDisassembler :: Fail ; if ( CtrlRegDecoderTable [ RegNo ] == <STR_LIT> ) return MCDisassembler :: Fail ; unsigned Register = CtrlRegDecoderTable [


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , Optional < CodeModel :: Model > CM , CodeGenOpt :: Level OL , bool JIT ) : LLVMTargetMachine ( T , TT . isArch64Bit ( ) ? <STR_LIT> : <STR_LIT> , TT , CPU , FS , Options , getEffectiveRelocModel ( RM , TT ) , getEffectiveCodeModel ( CM , CodeModel :: Large ) , OL ) , TLOF ( new <ISA_LIT>TargetObjectFile ( ) ) { this -> Options . TrapUnreachable = true ; this -> Options . FunctionSections = true ; this -> Options . DataSections = true ; this -> Options . UniqueSectionNames = true ; initAsmInfo ( )


<s> SAVErr = <STR_LIT> ; } NumBytes = - SubTarget . getAdjustedFrameSize ( NumBytes ) ; if ( NumBytes >= - <NUM_LIT> ) { BuildMI ( MBB , MBBI , dl , TII . get ( SAVEri ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( NumBytes ) ; } else { unsigned OffHi = ( unsigned ) NumBytes >> <NUM_LIT> ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addImm ( OffHi ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( NumBytes & ( ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) ) ; BuildMI ( MBB , MBBI , dl , TII . get ( SAVErr ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) ; } MachineModuleInfo & MMI = MF . getMMI ( ) ; const MCRegisterInfo * MRI = MMI . getContext ( )


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . setPreservesCFG ( ) ; AU . addRequired < MachineDominatorTree > ( ) ; AU . addRequired < MachinePostDominatorTree > ( ) ; MachineFunctionPass :: getAnalysisUsage


<s> mips_va_start ( valist , nextarg ) { \ if ( TARGET_MIPS16 ) \ sorry ( <STR_LIT> ) ; \ fprintf ( FILE , <STR_LIT> ) ; \ fprintf ( FILE , <STR_LIT> , \ reg_names [ GP_REG_FIRST + <NUM_LIT> ] , reg_names [ GP_REG_FIRST + <NUM_LIT> ] ) ; \ if ( ! TARGET_NEWABI ) \ { \ fprintf ( FILE , \ <STR_LIT> , \ TARGET_64BIT ? <STR_LIT> : <STR_LIT> , \ reg_names [ STACK_POINTER_REGNUM ]

, \ reg_names [ STACK_POINTER_REGNUM ] , \ Pmode == DImode ? <NUM_LIT> : <NUM_LIT> ) ; \ } \ fprintf ( FILE , <STR_LIT> ) ; \ fprintf ( FILE , <STR_LIT> ) ; \ }


<s> static void imposeStackOrdering ( MachineInstr * MI ) { if ( ! MI -> definesRegister ( <STR_LIT> ) ) MI -> addOperand ( MachineOperand :: CreateReg ( <STR_LIT> , true , true ) ) ; if ( ! MI -> readsRegister ( <STR_LIT> ) ) MI -> addOperand ( MachineOperand

:: CreateReg ( <STR_LIT> , false , true ) ) ;


<s> unsigned ConstCount ; BankSwizzle TransBS = ALU_VEC_012_SCL_210 ; for ( unsigned i = <NUM_LIT> , e = IG . size ( ) ; i < e ; ++ i ) { IGSrcs . push_back ( ExtractSrcs ( * IG [ i ] , PV , ConstCount ) ) ; unsigned Op = getOperandIdx ( IG [ i ] -> getOpcode ( ) , <STR_LIT> :: bank_swizzle ) ; ValidSwizzle . push_back ( ( <ISA_LIT>InstrInfo :: BankSwizzle ) IG [ i ] -> getOperand ( Op ) . getImm ( ) ) ; } std :: vector < std :: pair < int , unsigned >> TransOps ; if ( ! isLastAluTrans ) return FindSwizzleForVectorSlot ( IGSrcs , ValidSwizzle , TransOps , TransBS ) ; TransOps = std :: move ( IGSrcs . back ( ) ) ; IGSrcs . pop_back ( ) ; ValidSwizzle . pop_back ( ) ; static const <ISA_LIT>InstrInfo :: BankSwizzle TransSwz [ ] = { ALU_VEC_012_SCL_210 , ALU_VEC_021_SCL_122 , ALU_VEC_120_SCL_212 , ALU_VEC_102_SCL_221 } ; for ( unsigned i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) { TransBS = TransSwz [ i


<s> MachineBasicBlock :: const_iterator MI ( To ) , ME ( Ldst ) , End ( Ldst -> getParent ( ) -> end ( ) ) ; bool IsStore = Ldst -> mayStore ( ) ; for ( ; MI != ME && MI != End ; ++ MI ) { if ( MI -> isDebugValue ( ) ) continue ; if ( MI -> mayStore ( ) || MI -> isCall ( ) || MI -> isInlineAsm ( ) || MI -> hasUnmodeledSideEffects ( ) ) return false ; if ( IsStore && MI -> mayLoad ( ) ) return false ; } for ( auto & O : Ldst -> explicit_operands ( ) ) { if ( ! O . isReg ( ) || ! O . isUse ( ) ) continue ; MachineInstr * OpDef = MRI -> getVRegDef ( O . getReg ( ) ) ; if ( ! OpDef || ! MDT -> dominates ( OpDef , To ) ) return false ; } return true


<s> if ( ! TM || skipFunction ( F ) ) return false ; const <ISA_LIT>Subtarget & ST = TM -> getSubtarget < <ISA_LIT>Subtarget > ( F ) ; if ( ! ST . isPromoteAllocaEnabled ( ) ) return false ; FunctionType * FTy = F . getFunctionType ( ) ; for ( Type * ParamTy : FTy -> params ( ) ) { PointerType * PtrTy = dyn_cast < PointerType > ( ParamTy ) ; if ( PtrTy && PtrTy -> getAddressSpace ( ) == <ISA_LIT>AS :: LOCAL_ADDRESS ) { LocalMemLimit = <NUM_LIT> ; DEBUG ( dbgs ( ) << <STR_LIT> <STR_LIT> ) ; return false ; } } LocalMemLimit = ST . getLocalMemorySize ( ) ; if ( LocalMemLimit == <NUM_LIT> ) return false ; const DataLayout & DL = Mod -> getDataLayout ( ) ; CurrentLocalMemUsage = <NUM_LIT> ; for ( GlobalVariable & GV : Mod -> globals ( ) ) { if ( GV . getType ( ) -> getAddressSpace ( ) != <ISA_LIT>AS :: LOCAL_ADDRESS ) continue ; for ( const User * U : GV . users ( ) ) { const Instruction * Use = dyn_cast < Instruction > ( U ) ; if ( ! Use ) continue ; if ( Use -> getParent ( ) -> getParent ( ) == & F ) { unsigned Align = GV . getAlignment ( ) ; if ( Align == <NUM_LIT> ) Align = DL . getABITypeAlignment ( GV . getValueType ( ) ) ; uint64_t AllocSize = DL . getTypeAllocSize ( GV . getValueType ( ) ) ; CurrentLocalMemUsage = alignTo ( CurrentLocalMemUsage , Align ) ; CurrentLocalMemUsage += AllocSize ; break ; } } } unsigned MaxOccupancy = ST . getOccupancyWithLocalMemSize ( CurrentLocalMemUsage , F ) ; unsigned OccupancyHint = ST . getWavesPerEU ( F ) . second ; if ( OccupancyHint == <NUM_LIT>


<s> inline rtx base_reg_disp :: reg ( void ) const { return


<s> unsigned MaxPrivateBits = <NUM_LIT> * getSubtarget ( ) -> getMaxPrivateElementSize ( ) ; return ( MemVT . getSizeInBits ( ) <= MaxPrivateBits ) ; } else if ( AS == <ISA_LIT>AS :: LOCAL_ADDRESS || AS


<s> if ( Ret . getNode ( ) ) return Ret ; if ( VT . isVector ( ) && VT . getVectorNumElements ( ) >= <NUM_LIT> ) return SplitVectorStore ( Op , DAG ) ; if ( VT == <STR_LIT> ) return DAG . getTruncStore ( Store -> getChain ( ) , DL , DAG . getSExtOrTrunc ( Store -> getValue ( ) , DL , <STR_LIT> ) , Store -> getBasePtr ( ) , <STR_LIT> , Store -> getMemOperand ( ) ) ; return SDValue (


<s> bool isPKHASRImm ( ) const { if ( ! isImm ( ) ) return false ; const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; if ( ! CE ) return false ; int64_t Value = CE -> getValue


<s> if ( IsCall ) { CCInfo . AnalyzeCallOperands ( * Outs , ArgCC_<ISA_LIT>_Vararg ) ; } else { CCInfo . AnalyzeFormalArguments ( * Ins , ArgCC_<ISA_LIT>_Vararg ) ; } return ; } SmallVector < unsigned , <NUM_LIT> > Args ; if ( IsCall ) { parseExternFuncCallArgs ( * Outs , Args ) ; } else { assert ( F != nullptr && <STR_LIT> ) ; parseFunctionArgs ( * Ins , Args ) ; } unsigned RegsLeft = array_lengthof ( RegList8 ) , ValNo = <NUM_LIT> ; bool UsesStack = false ; for ( unsigned i = <NUM_LIT> , pos = <NUM_LIT> , e = Args . size ( ) ; i != e ; ++ i ) { unsigned Size = Args [ i ] ; if ( Size == <NUM_LIT> ) continue ; MVT LocVT = ( IsCall ) ? ( * Outs ) [ pos ] . VT : ( * Ins ) [ pos ] . VT ; if ( ! UsesStack && ( Size <= RegsLeft ) ) { const MCPhysReg * RegList = ( LocVT == <STR_LIT> ) ? RegList16 : RegList8 ; for ( unsigned j = <NUM_LIT> ; j != Size ; ++ j ) { unsigned Reg = CCInfo . AllocateReg ( ArrayRef < MCPhysReg > ( RegList , array_lengthof ( RegList8


<s> std :: string ArchFS = <ISA_LIT>_MC :: Parse<ISA_LIT>Triple ( TT ) ; if ( ! FS . empty ( ) ) { if ( ! ArchFS . empty ( ) ) ArchFS = ( Twine ( ArchFS ) + <STR_LIT>


<s> case <STR_LIT> : Cmp = IRB -> CreateICmpSGE ( LHS , RHS ) ; break ; case <STR_LIT> : Cmp = IRB -> CreateICmpSLT ( LHS , RHS ) ; break ; case <STR_LIT> : Cmp = IRB -> CreateICmpSGT ( LHS , RHS ) ; break ; case <STR_LIT> : Cmp = IRB -> CreateICmpSLE ( LHS , RHS ) ; break ; } ( dyn_cast < Instruction > ( Cmp ) ) -> setDebugLoc ( N -> getOperand ( <NUM_LIT> ) -> getDebugLoc ( ) ) ; BasicBlock * NextBB = NULL ; Function :: iterator BI = F -> begin ( ) , BE = F -> end ( ) ; while ( BI != BE && BI -> getName ( ) != CurBB -> getName ( ) ) ++ BI ; ++ BI ; if ( BI == BE ) { NextBB = Dec -> getOrCreateBasicBlock ( <STR_LIT> , F ) ; } else { NextBB = & ( * BI ) ; } Instruction * Br = IRB -> CreateCondBr ( Cmp , BBTgt , NextBB ) ; Br -> setDebugLoc ( N -> getDebugLoc ( ) ) ; return


<s> unsigned <ISA_LIT>ELFObjectWriter :: getRelocType ( MCContext & Ctx , const MCValue & Target , const MCFixup & Fixup , bool IsPCRel ) const { return GetRelocTypeInner ( Target , Fixup , IsPCRel


<s> DEBUG ( dbgs ( ) << <STR_LIT> ) ; IsTopNode = false ; return SU ; } if ( SUnit * SU = Top . pickOnlyChoice ( ) ) { DEBUG ( dbgs ( ) << <STR_LIT> ) ; IsTopNode = true ; return SU ; } SchedCandidate BotCand ; CandResult BotResult = pickNodeFromQueue ( Bot , DAG -> getBotRPTracker ( ) , BotCand ) ; assert ( BotResult != NoCand && <STR_LIT> ) ; if ( BotResult == SingleExcess || BotResult == SingleCritical ) { DEBUG ( dbgs ( ) << <STR_LIT> ) ; IsTopNode = false ; return BotCand . SU ; } SchedCandidate TopCand ; CandResult TopResult = pickNodeFromQueue ( Top , DAG -> getTopRPTracker ( ) , TopCand ) ; assert ( TopResult != NoCand && <STR_LIT> ) ; if ( TopResult == SingleExcess || TopResult == SingleCritical ) { DEBUG ( dbgs ( ) << <STR_LIT> ) ; IsTopNode =


<s> static unsigned first_sew ( const vector_insn_info & info1 , const vector_insn_info &


<s> const MCOperand & MOUImm = MI -> getOperand ( OpNum ) ; assert ( MOUImm . isImm ( )


<s> FunctionPass * llvm :: create<ISA_LIT>ISelDag ( <ISA_LIT>TargetMachine & TM ) { return new <ISA_LIT>DAGToDAGISel


<s> if ( convertToBRCT ( MI , Compare , CCUsers ) ) { BranchOnCounts += <NUM_LIT> ; return true ; } if ( convertToLoadAndTrap ( MI , Compare , CCUsers ) ) { LoadAndTraps += <NUM_LIT> ; return true ; } } if ( ( ! CCRefs && convertToLoadAndTest ( MI , Compare , CCUsers ) ) || ( ! CCRefs . Def && ( adjustCCMasksForInstr ( MI , Compare , CCUsers ) || convertToLogical ( MI , Compare , CCUsers ) ) ) ) { EliminatedComparisons += <NUM_LIT> ; return true ; } } SrcRefs |= getRegReferences ( MI , SrcReg ) ; if ( SrcRefs . Def ) break ; CCRefs |= getRegReferences ( MI , <STR_LIT> ) ; if ( CCRefs . Use && CCRefs . Def ) break ; if ( Compare . mayRaiseFPException ( ) && ( MI . isCall ( ) || MI . hasUnmodeledSideEffects ( ) ) ) break ; } for ( MachineBasicBlock :: iterator MBBI = std :: next ( MachineBasicBlock :: iterator ( & Compare ) ) , MBBE = MBB . end ( ) ; MBBI != MBBE


<s> setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Custom ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Custom ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Custom ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Expand ) ; if ( VT . isInteger ( ) ) { setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Custom ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Custom ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Custom ) ; } if ( VT . isInteger ( ) && VT != PromotedBitwiseVT ) { setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Promote ) ; AddPromotedToType ( <STR_LIT> , VT . getSimpleVT ( ) , PromotedBitwiseVT . getSimpleVT ( ) ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Promote ) ; AddPromotedToType ( <STR_LIT> , VT . getSimpleVT ( ) , PromotedBitwiseVT . getSimpleVT ( ) ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Promote ) ; AddPromotedToType ( <STR_LIT> , VT . getSimpleVT ( ) , PromotedBitwiseVT .


<s> bool isBDAddr32Disp20 ( ) const { return isMemDisp20 ( ADDR32Reg