<s> bool <ISA_LIT>FrameLowering :: restoreCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo * TRI ) const { MachineFunction & MF = * MBB . getParent ( ) ; const TargetInstrInfo & TII = * MF . getSubtarget ( ) . getInstrInfo ( ) ; DebugLoc DL ; SmallVector < RegPairInfo , <NUM_LIT> > RegPairs ; bool NeedsWinCFI = needsWinCFI ( MF ) ; if ( MI != MBB . end ( ) ) DL = MI -> getDebugLoc ( ) ; bool NeedShadowCallStackProlog = false ; computeCalleeSaveRegisterPairs ( MF , CSI , TRI , RegPairs , NeedShadowCallStackProlog , hasFP ( MF ) ) ; auto EmitMI = [ & ] ( const RegPairInfo & RPI ) { unsigned Reg1 = RPI . Reg1 ; unsigned Reg2 = RPI . Reg2 ; unsigned LdrOpc ; unsigned Size , Align ; switch ( RPI . Type ) { case RegPairInfo :: GPR : LdrOpc = RPI . isPaired ( ) ? <STR_LIT> : <STR_LIT> ; Size = <NUM_LIT> ; Align = <NUM_LIT> ; break ; case RegPairInfo :: FPR64 : LdrOpc = RPI . isPaired ( ) ? <STR_LIT> : <STR_LIT> ; Size = <NUM_LIT> ; Align = <NUM_LIT> ; break ; case RegPairInfo :: FPR128 : LdrOpc = RPI . isPaired ( ) ? <STR_LIT> : <STR_LIT> ; Size = <NUM_LIT> ; Align = <NUM_LIT> ; break ; case RegPairInfo :: ZPR : LdrOpc = <STR_LIT> ; Size = <NUM_LIT> ; Align =


<s> return isThumb ( ) && ! getSTI ( ) . getFeatureBits ( )


<s> if ( ! isImm ( ) ) return false ; <ISA_LIT>MCExpr :: VariantKind VK = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ; int64_t Imm ; bool IsConstantImm = evaluateConstantImm ( getImm ( ) , Imm , VK ) ; return IsConstantImm && isInt < <NUM_LIT> > ( Imm ) && VK


<s> if ( a_is_memory && m -> getDesc ( ) . mayStore ( ) ) return true ; } for ( unsigned aop = <NUM_LIT> , aend = a -> getNumOperands ( ) ; aop < aend ; ++ aop ) { if ( a -> getOperand ( aop ) . isReg ( ) ) { unsigned aop_reg = a -> getOperand ( aop ) . getReg ( ) ; for ( unsigned bop = <NUM_LIT> , bend = b -> getNumOperands ( ) ; bop < bend ; ++ bop ) { if ( b -> getOperand ( bop ) . isReg ( ) && ( ! b -> getOperand ( bop ) . isImplicit ( ) ) ) { unsigned bop_reg = b -> getOperand ( bop


<s> MachinePointerInfo <ISA_LIT>FunctionInfo :: callPtrInfo ( const GlobalValue * GV ) { return MachinePointerInfo ( MF . getPSVManager (


<s> CallInfoStack CallStack ; while ( Call ) { CallStack . push ( std :: make_pair ( Call , CInfo ) ) ; CInfo = AIChain [ Call ] . second ; Call = AIChain [ Call ] . first ; } uint32_t FirstIndex = <NUM_LIT> ; uint32_t PatchImm = <NUM_LIT> ; uint32_t InfoKind = <STR_LIT> ; while ( CallStack . size ( ) ) { auto StackElem = CallStack . top ( ) ; Call = StackElem . first ; CInfo = StackElem . second ; if ( ! Base ) Base = CInfo . Base ; DIType * PossibleTypeDef = stripQualifiers ( cast < DIType > ( CInfo . Metadata ) , false ) ; DIType * Ty = stripQualifiers ( PossibleTypeDef ) ; if ( CInfo . Kind == <ISA_LIT>PreserveUnionAI || CInfo . Kind == <ISA_LIT>PreserveStructAI ) { TypeName = std :: string ( PossibleTypeDef -> getName ( ) ) ; TypeMeta = PossibleTypeDef ; PatchImm += FirstIndex * ( Ty -> getSizeInBits ( ) >> <NUM_LIT> ) ; break ; } assert ( CInfo . Kind == <ISA_LIT>PreserveArrayAI ) ; CallStack . pop ( ) ; uint64_t AccessIndex = CInfo . AccessIndex ; DIType * BaseTy = nullptr ; bool CheckElemType = false ; if ( const auto * CTy = dyn_cast < DICompositeType > ( Ty ) ) { assert ( CTy -> getTag ( ) == dwarf :: DW_TAG_array_type ) ; FirstIndex += AccessIndex * calcArraySize ( CTy , <NUM_LIT> ) ; BaseTy = stripQualifiers ( CTy -> getBaseType ( ) ) ; CheckElemType = CTy -> getElements ( ) . size ( ) == <NUM_LIT> ; } else { auto * DTy = cast < DIDerivedType > ( Ty ) ; assert ( DTy -> getTag ( ) == dwarf :: DW_TAG_pointer_type ) ; BaseTy = stripQualifiers ( DTy -> getBaseType ( ) ) ; CTy = dyn_cast < DICompositeType > ( BaseTy ) ; if ( ! CTy ) { CheckElemType = true ; } else if ( CTy -> getTag ( ) != dwarf :: DW_TAG_array_type ) { FirstIndex += AccessIndex ; CheckElemType = true ; }


<s> bool <ISA_LIT>FrameLowering :: canUseAsPrologue ( const MachineBasicBlock & MBB ) const { const MachineFunction * MF = MBB . getParent ( ) ; MachineBasicBlock * TmpMBB = const_cast < MachineBasicBlock * > ( & MBB ) ; const <ISA_LIT>Subtarget & Subtarget = MF -> getSubtarget < <ISA_LIT>Subtarget > ( ) ; const <ISA_LIT>RegisterInfo * RegInfo = Subtarget . getRegisterInfo ( ) ; if ( ! RegInfo -> hasStackRealignment ( * MF ) ) return true ; return findScratchNonCalleeSaveRegister ( TmpMBB )


<s> void <ISA_LIT>AsmPrinter :: PrintDebugValueComment ( const MachineInstr * MI , raw_ostream & OS ) { OS <<


<s> return get<ISA_LIT>ArchVersion ( ) == <STR_LIT> :: V68


<s> const TargetInstrDesc & TID = MI -> getDesc ( ) ; for ( unsigned i = <NUM_LIT> , e = TID . getNumOperands ( ) ; i != e ; ++ i ) { if ( TID . OpInfo [ i ] . isPredicate ( ) ) continue ; const MachineOperand & MO = MI -> getOperand ( i ) ; if ( MO . isReg ( ) ) { unsigned Reg = MO . getReg ( ) ; if ( ! Reg || Reg == <STR_LIT> ) continue ; if ( Entry . WideOpc == <STR_LIT> && Reg == <STR_LIT> ) continue ; if ( Entry . LowRegs1 && ! is<ISA_LIT>LowRegister ( Reg ) ) return false ; } else if ( MO . isImm ( ) && ! TID . OpInfo [ i ] . isPredicate ( ) ) { if ( MO . getImm ( ) > Limit || ( MO . getImm ( ) & ( Scale - <NUM_LIT> ) ) != <NUM_LIT> ) return false ; } } const TargetInstrDesc & NewTID = TII -> get ( Entry . NarrowOpc1 ) ; unsigned PredReg = <NUM_LIT> ; <STR_LIT> Pred = getInstrPredicate ( MI , PredReg ) ; bool SkipPred = false ; if ( Pred != <STR_LIT> ) { if ( ! NewTID . isPredicable ( ) ) return false ; } else { SkipPred = ! NewTID . isPredicable ( ) ; } bool HasCC = false ; bool CCDead = false ; if ( TID . hasOptionalDef ( ) ) { unsigned NumOps = TID . getNumOperands ( ) ; HasCC = ( MI -> getOperand ( NumOps - <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) ; if ( HasCC && MI -> getOperand ( NumOps - <NUM_LIT> ) . isDead ( ) ) CCDead = true ; } if ( ! VerifyPredAndCC ( MI , Entry , false , Pred , LiveCPSR , HasCC , CCDead ) ) return false ; DebugLoc dl = MI -> getDebugLoc ( ) ; MachineInstrBuilder MIB = BuildMI ( MBB , * MI , dl , NewTID ) ; MIB . addOperand ( MI -> getOperand ( <NUM_LIT> ) ) ; if ( NewTID . hasOptionalDef ( ) ) { if ( HasCC ) AddDefaultT1CC ( MIB ,


<s> if ( ! strict_p && GET_CODE ( x ) == SUBREG ) x = SUBREG_REG


<s> OperandMatchResultTy parseADDR128 ( OperandVector & Operands


<s> case SHValues :: SH_SPLAT : { MachineInstr * MI = SwapVector [ EntryIdx ] . VSEMI ; unsigned NElts ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; DEBUG ( MI -> dump ( ) ) ; switch ( MI -> getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : NElts = <NUM_LIT> ; break ; case <STR_LIT> : NElts = <NUM_LIT> ; break ; case <STR_LIT> : NElts = <NUM_LIT> ; break ; } unsigned EltNo = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; EltNo = ( EltNo + NElts / <NUM_LIT> ) % NElts ; MI -> getOperand ( <NUM_LIT> ) . setImm ( EltNo ) ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; DEBUG ( MI -> dump ( ) ) ; break ; } case SHValues :: SH_XXPERMDI : { MachineInstr * MI = SwapVector [ EntryIdx ] . VSEMI ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; DEBUG ( MI -> dump ( ) ) ; unsigned Selector = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( Selector == <NUM_LIT> || Selector == <NUM_LIT> ) Selector = <NUM_LIT> - Selector ; MI -> getOperand ( <NUM_LIT> ) . setImm ( Selector ) ; unsigned Reg1 = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Reg2 = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; MI -> getOperand ( <NUM_LIT> ) . setReg ( Reg2 ) ; MI -> getOperand ( <NUM_LIT> ) . setReg ( Reg1 ) ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; DEBUG ( MI -> dump ( ) ) ; break ; } case SHValues :: SH_COPYWIDEN : { MachineInstr * MI = SwapVector [ EntryIdx ] . VSEMI ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; DEBUG ( MI -> dump ( ) ) ; unsigned DstReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; const TargetRegisterClass * DstRC = MRI -> getRegClass ( DstReg ) ; unsigned NewVReg = MRI -> createVirtualRegister ( DstRC ) ; MI -> getOperand ( <NUM_LIT> ) . setReg ( NewVReg ) ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; DEBUG ( MI -> dump ( ) ) ; auto InsertPoint = ++ MachineBasicBlock :: iterator ( MI ) ; if ( DstRC ==


<s> const char * output_probe_stack_range ( rtx reg1 , rtx reg2 ) { static int labelno = <NUM_LIT> ; char loop_lab [ <NUM_LIT> ] ; rtx xops [ <NUM_LIT> ] ; ASM_GENERATE_INTERNAL_LABEL ( loop_lab , <STR_LIT> , labelno ++ ) ; ASM_OUTPUT_INTERNAL_LABEL ( asm_out_file , loop_lab ) ; xops [ <NUM_LIT> ] = reg1 ; xops [ <NUM_LIT> ] = GEN_INT ( - PROBE_INTERVAL ) ; output_asm_insn ( <STR_LIT> , xops ) ; xops [ <NUM_LIT> ] = gen_rtx_REG ( Pmode , <NUM_LIT> ) ; output_asm_insn ( <STR_LIT> , xops ) ; xops [ <NUM_LIT> ] = reg2 ; if ( TARGET_64BIT ) output_asm_insn ( <STR_LIT> , xops ) ; else output_asm_insn ( <STR_LIT> , xops


<s> unsigned getCalleeSavedFrameSize ( )


<s> } if ( ! TM ) return true ; const TargetLowering * TLI = TM -> getSubtargetImpl ( ) -> getTargetLowering ( ) ; if ( Function * F = CI -> getCalledFunction ( ) ) { unsigned Opcode ; if ( F -> getIntrinsicID ( ) != <STR_LIT> ) { switch ( F -> getIntrinsicID ( ) ) { default : continue ; ! defined ( setjmp_undefined_for_msvc ) case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; case <STR_LIT> : if ( CI -> getArgOperand ( <NUM_LIT> ) -> getType ( ) -> getScalarType ( ) -> is<ISA_LIT>_FP128Ty ( ) ) return true ; else continue ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; } } LibFunc :: Func Func ; if ( ! F -> hasLocalLinkage ( ) && F -> hasName ( ) && LibInfo && LibInfo -> getLibFunc ( F -> getName ( ) , Func ) && LibInfo -> hasOptimizedCodeGen ( Func ) ) { if ( ! CI -> onlyReadsMemory ( ) ) return true ; if ( ! CI -> getArgOperand ( <NUM_LIT> ) -> getType ( ) -> isFloatingPointTy ( ) ) return true ; switch ( Func ) { default : return true ; case LibFunc :: copysign : case LibFunc :: copysignf : continue ; case LibFunc :: copysignl : return true ; case LibFunc :: fabs : case LibFunc :: fabsf : case LibFunc :: fabsl : continue ; case LibFunc :: sqrt : case LibFunc :: sqrtf : case LibFunc :: sqrtl : Opcode = <STR_LIT> ; break ; case LibFunc :: floor : case LibFunc :: floorf : case LibFunc :: floorl : Opcode = <STR_LIT> ; break ; case LibFunc :: nearbyint : case LibFunc :: nearbyintf : case LibFunc :: nearbyintl : Opcode = <STR_LIT> ; break ; case LibFunc ::


<s> void <ISA_LIT>TargetELFStreamer :: emitDirectiveSetNoMicro<ISA_LIT> ( ) { Micro<ISA_LIT>Enabled =


<s> if ( ! MFI -> isEntryFunction ( ) ) { SDLoc DL ( Op ) ; const Function & Fn = DAG . getMachineFunction ( ) . getFunction ( ) ; DiagnosticInfoUnsupported BadLDSDecl ( Fn , <STR_LIT> , DL . getDebugLoc ( ) , DS_Warning ) ; DAG . getContext ( ) -> diagnose ( BadLDSDecl ) ; SDValue Trap = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getEntryNode ( ) ) ; SDValue OutputChain = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Trap ,


<s> assert ( Subtarget -> isTargetDarwin ( ) && <STR_LIT> ) ; SDLoc DL ( Op ) ; SDValue DescAddr = LowerGlobalAddressDarwin ( Op , DAG ) ; SDValue Chain = DAG . getEntryNode ( ) ; SDValue FuncTLVGet = DAG . getLoad ( <STR_LIT> , DL , Chain , DescAddr , MachinePointerInfo :: getGOT ( DAG . getMachineFunction ( ) ) , <NUM_LIT> , MachineMemOperand :: MONonTemporal | MachineMemOperand :: MODereferenceable | MachineMemOperand :: MOInvariant ) ; Chain = FuncTLVGet . getValue ( <NUM_LIT> ) ; MachineFunction & F = DAG . getMachineFunction ( ) ; MachineFrameInfo & MFI = F . getFrameInfo ( ) ; MFI . setAdjustsStack ( true ) ; auto TRI = getTargetMachine ( ) . getSubtargetImpl ( * F . getFunction ( ) ) -> getRegisterInfo ( ) ; auto ARI = static_cast < const <ISA_LIT>RegisterInfo * > ( TRI ) ; const uint32_t * Mask = ARI -> getTLSCallPreservedMask ( DAG . getMachineFunction ( ) ) ; Chain = DAG . getCopyToReg ( Chain , DL , <STR_LIT> , DescAddr , SDValue ( ) ) ; Chain = DAG . getNode ( <STR_LIT> , DL , DAG . getVTList ( <STR_LIT> , <STR_LIT> ) , Chain , FuncTLVGet , DAG . getRegister ( <STR_LIT> , <STR_LIT> ) , DAG . getRegisterMask ( Mask ) , Chain . getValue ( <NUM_LIT> ) ) ; return DAG . getCopyFromReg ( Chain , DL , <STR_LIT> , <STR_LIT> , Chain . getValue (


<s> } const DebugLoc & DL = MI . getDebugLoc ( ) ; unsigned Exec = ST . isWave32 ( ) ? <STR_LIT> : <STR_LIT> ; unsigned MovExecOpc = ST . isWave32 ( ) ? <STR_LIT> : <STR_LIT> ; const auto * BoolXExecRC = TRI -> getRegClass ( <STR_LIT> ) ; Register SaveExec = MRI . createVirtualRegister ( BoolXExecRC ) ; BuildMI ( MBB , Begin , DL , TII . get ( MovExecOpc ) , SaveExec ) . addReg ( Exec ) ; MachineBasicBlock :: iterator AfterMI = MI ; ++ AfterMI ; for ( auto I = Begin ; I != AfterMI ; I ++ ) { for ( auto & MO : I -> uses ( ) ) { if ( MO . isReg ( ) && MO . isUse ( ) ) { MRI . clearKillFlags ( MO . getReg ( ) ) ; } } } MachineBasicBlock * LoopBB = MF . CreateMachineBasicBlock ( ) ; MachineBasicBlock * BodyBB = MF . CreateMachineBasicBlock ( ) ; MachineBasicBlock * RemainderBB = MF . CreateMachineBasicBlock ( ) ; MachineFunction :: iterator MBBI ( MBB ) ; ++ MBBI ; MF . insert ( MBBI , LoopBB ) ; MF . insert ( MBBI , BodyBB ) ; MF . insert ( MBBI , RemainderBB ) ; LoopBB -> addSuccessor ( BodyBB ) ; BodyBB -> addSuccessor ( LoopBB ) ; BodyBB -> addSuccessor ( RemainderBB ) ; RemainderBB -> transferSuccessorsAndUpdatePHIs ( & MBB ) ; RemainderBB -> splice ( RemainderBB -> begin ( ) , & MBB , End , MBB .


<s> Target & llvm :: getThe<ISA_LIT>32Target


WaitStatesNeeded , WaitStatesNeededForUse ) ;


<s> auto MOTW = llvm :: make_unique < <ISA_LIT>ELFObjectWriter > ( MCELFObjectTargetWriter :: getOSABI ( OSType


<s> OS << '$' << StringRef ( getRegisterName ( RegNo ) ) . lower


<s> setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setTargetDAGCombine ( <STR_LIT> ) ; setTargetDAGCombine ( <STR_LIT> ) ; setBooleanContents ( ZeroOrOneBooleanContent ) ; setBooleanVectorContents ( ZeroOrNegativeOneBooleanContent ) ; for ( MVT VT : <STR_LIT> ( ) ) { setLoadExtAction ( <STR_LIT> , VT , <STR_LIT> , Promote ) ; setLoadExtAction ( <STR_LIT> , VT , <STR_LIT> , Promote ) ; setLoadExtAction ( <STR_LIT> , VT , <STR_LIT> , Promote ) ; } AddPromotedToType ( <STR_LIT> , <STR_LIT> , <STR_LIT>


<s> void addRegF4RCOperands ( MCInst & Inst , unsigned


<s> assert ( CC == <STR_LIT> && <STR_LIT> ) ; } if ( Op1 -> getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; ConstantSDNode * OrC = dyn_cast < ConstantSDNode > ( Op1 -> getOperand ( <NUM_LIT> ) ) ; if ( ! OrC ) return SDValue ( ) ; SDValue Y = Op1 -> getOperand ( <NUM_LIT> ) ; if ( Op0 != Y ) return SDValue ( ) ; APInt OrCI = OrC -> getAPIntValue ( ) ; unsigned Heuristic = Subtarget -> isThumb ( ) ? <NUM_LIT> : <NUM_LIT> ; if ( OrCI . countPopulation ( ) > Heuristic ) return SDValue ( ) ; APInt KnownZero , KnownOne ; DAG . computeKnownBits ( Y , KnownZero , KnownOne ) ; if ( ( OrCI & KnownZero ) != OrCI ) return SDValue ( ) ; SDValue V = Y ; SDLoc dl ( X ) ; EVT VT = X . getValueType ( ) ; unsigned BitInX = AndC -> getAPIntValue ( ) . logBase2 ( ) ; if ( BitInX != <NUM_LIT> ) { X = DAG . getNode ( <STR_LIT> , dl , VT , X

, DAG . getConstant ( BitInX , dl , VT ) ) ;


<s> bool <ISA_LIT>InstrInfo :: isBasicBlockPrologue ( const MachineInstr & MI ) const { return ! MI . isTerminator ( ) && MI . getOpcode ( ) != <STR_LIT> &&

MI . modifiesRegister ( <STR_LIT> , & RI ) ;


<s> const DebugLoc & DL = MI . getDebugLoc ( ) ; Register DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; MachineBasicBlock :: iterator Start = MBB . begin ( ) ; Register SaveReg = MRI -> createVirtualRegister ( BoolRC ) ; MachineInstr * OrSaveExec = BuildMI ( MBB , Start , DL , TII -> get ( OrSaveExecOpc ) , SaveReg ) . add ( MI . getOperand ( <NUM_LIT> ) ) ; MachineBasicBlock * DestBB = MI . getOperand ( <NUM_LIT> ) . getMBB ( ) ; MachineBasicBlock :: iterator ElsePt ( MI ) ; MachineInstr * And = BuildMI ( MBB , ElsePt , DL , TII -> get ( AndOpc ) , DstReg ) . addReg ( Exec ) . addReg ( SaveReg ) ; if ( LIS ) LIS -> InsertMachineInstrInMaps ( * And ) ; MachineInstr * Xor = BuildMI ( MBB , ElsePt , DL , TII -> get ( XorTermrOpc ) , Exec ) . addReg ( Exec ) . addReg ( DstReg ) ; ElsePt = skipToUncondBrOrEnd ( MBB , ElsePt ) ; MachineInstr * Branch = BuildMI ( MBB , ElsePt , DL , TII -> get ( <STR_LIT> ) ) . addMBB ( DestBB ) ; if ( ! LIS ) { MI . eraseFromParent ( ) ; return ; } LIS -> RemoveMachineInstrFromMaps ( MI ) ; MI . eraseFromParent ( ) ; LIS -> InsertMachineInstrInMaps ( * OrSaveExec ) ; LIS -> InsertMachineInstrInMaps ( * Xor ) ; LIS -> InsertMachineInstrInMaps ( * Branch ) ; LIS -> removeInterval ( DstReg )


<s> SDValue <ISA_LIT>TargetLowering :: LowerFormalArguments ( SDValue Chain , CallingConv :: ID CallConv , bool IsVarArg , const SmallVectorImpl < <STR_LIT> > & Ins , const SDLoc & DL ,

SelectionDAG & DAG , SmallVectorImpl < SDValue > & InVals ) const {


<s> unsigned <ISA_LIT>TTIImpl :: getLoadStoreVecRegBitWidth ( unsigned


<s> } } if ( ! Subtarget -> isThumb1Only ( ) ) { if ( SDValue Result = combineSelectAndUseCommutative ( N , false , DCI ) ) return Result ; if ( SDValue Result = PerformORCombineToSMULWBT ( N , DCI , Subtarget ) ) return Result ; } SDValue N0 = N -> getOperand ( <NUM_LIT> ) ; SDValue N1 = N -> getOperand ( <NUM_LIT> ) ; if ( Subtarget -> hasNEON ( ) && N1 . getOpcode ( ) == <STR_LIT> && VT . isVector ( ) && DAG . getTargetLoweringInfo ( ) . isTypeLegal ( VT ) ) { if ( N0 . getOpcode ( ) != <STR_LIT> || ! N0 . hasOneUse ( ) ) return SDValue ( ) ; APInt SplatUndef ; unsigned SplatBitSize ; bool HasAnyUndefs ; APInt SplatBits0 , SplatBits1 ; BuildVectorSDNode * BVN0 = dyn_cast < BuildVectorSDNode > ( N0 -> getOperand ( <NUM_LIT> ) ) ; BuildVectorSDNode * BVN1 = dyn_cast < BuildVectorSDNode > ( N1 -> getOperand ( <NUM_LIT> ) ) ; if ( BVN0 && BVN0 -> isConstantSplat ( SplatBits0 , SplatUndef , SplatBitSize , HasAnyUndefs ) && ! HasAnyUndefs ) { if ( BVN1 && BVN1 -> isConstantSplat ( SplatBits1 , SplatUndef , SplatBitSize , HasAnyUndefs ) && ! HasAnyUndefs ) { if ( SplatBits0 . getBitWidth ( ) == SplatBits1 . getBitWidth ( ) &&


Zeroable , Subtarget , DAG ) ) return PSHUFB ;


<s> bool is_cb ( unsigned a , unsigned b , unsigned c ) { return arg0 ( c ) && arg1 ( b ) && noArg (


<s> static int ix86_mode_entry ( int entity ) { switch ( entity ) { case AVX_U128 : return ix86_avx_u128_mode_entry ( ) ; case I387_TRUNC : case I387_FLOOR : case


<s> Register AddOp1Reg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; const LLT PtrTy = MRI . getType ( DstReg ) ; if ( PtrTy . getAddressSpace ( ) != <NUM_LIT> ) return false ; const LLT CastPtrTy = PtrTy . isVector ( ) ? LLT :: fixed_vector ( <NUM_LIT> , <NUM_LIT> ) : LLT :: scalar ( <NUM_LIT> ) ; auto PtrToInt = MIB . buildPtrToInt ( CastPtrTy , AddOp1Reg ) ; if ( PtrTy . isVector ( ) ) MRI . setRegBank ( PtrToInt . getReg ( <NUM_LIT> ) , RBI . getRegBank ( <STR_LIT> ) ) ; else MRI . setRegBank ( PtrToInt . getReg ( <NUM_LIT> ) , RBI . getRegBank ( <STR_LIT> ) ) ; I . setDesc ( TII . get ( TargetOpcode :: G_ADD ) ) ; MRI . setType ( DstReg , CastPtrTy ) ; I . getOperand ( <NUM_LIT> ) . setReg ( PtrToInt . getReg ( <NUM_LIT> ) ) ; if ( ! select ( * PtrToInt )


<s> unsigned Opcode = <NUM_LIT> ; if ( LHS . getValueType ( ) . isFloatingPoint ( ) ) Opcode = <STR_LIT> ; else if ( RHS . getOpcode ( ) == <STR_LIT> ) { SDValue SubOp0 = RHS . getOperand ( <NUM_LIT> ) ; if ( isNullConstant ( SubOp0 ) && ( CC == <STR_LIT> || CC == <STR_LIT> ) ) { Opcode = <STR_LIT> ; RHS = RHS . getOperand ( <NUM_LIT> ) ; } } if ( Opcode == <NUM_LIT> ) Opcode = <STR_LIT> ; SDValue Condition = DAG . getConstant ( Predicate


<s> static void aarch64_emit_binop ( rtx dest , optab binoptab , rtx op0 , rtx op1 ) { rtx tmp = expand_binop ( GET_MODE ( dest ) , binoptab , op0 , op1 , dest , <NUM_LIT>


<s> while ( I != MBB . begin ( ) ) { -- I ; if ( I -> isDebugValue ( ) ) continue ; if ( ! I -> isBranch ( ) ) return Count ; if ( Count && ( I -> getOpcode ( ) == <STR_LIT> ) ) llvm_unreachable ( <STR_LIT> ) ; MBB . erase ( & MBB . back ( ) ) ; I = MBB . end ( ) ; ++ Count


<s> if ( ! isBundled ( MI ) && InBundle ) { O << <STR_LIT> ; InBundle = false ; } printAnnotation ( O , Annot


<s> } else { StrOpc = <STR_LIT> ; } break ; case <STR_LIT> : if ( Alignment && Alignment < <NUM_LIT> && ! Subtarget -> allowsUnalignedMem ( ) ) return false ; if ( isThumb2 ) { if ( Addr . Offset < <NUM_LIT> && Addr . Offset > - <NUM_LIT> && Subtarget -> hasV6T2Ops ( ) ) StrOpc = <STR_LIT> ; else StrOpc = <STR_LIT> ; } else { StrOpc = <STR_LIT> ; useAM3 = true ; } break ; case <STR_LIT> : if ( Alignment && Alignment < <NUM_LIT> && ! Subtarget -> allowsUnalignedMem ( ) ) return false ; if ( isThumb2 ) { if ( Addr . Offset < <NUM_LIT> && Addr . Offset > - <NUM_LIT> && Subtarget -> hasV6T2Ops ( ) ) StrOpc = <STR_LIT> ; else StrOpc = <STR_LIT> ; } else { StrOpc = <STR_LIT> ; } break ; case <STR_LIT> : if ( ! Subtarget -> hasVFP2 ( ) ) return false ; if ( Alignment && Alignment < <NUM_LIT> ) { unsigned MoveReg = createResultReg ( TLI . getRegClassFor ( <STR_LIT> ) ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , MoveReg ) . addReg ( SrcReg ) ) ; SrcReg = MoveReg ; VT = <STR_LIT> ; StrOpc = isThumb2 ? <STR_LIT> : <STR_LIT> ; } else { StrOpc = <STR_LIT> ; } break ; case <STR_LIT> : if ( ! Subtarget -> hasVFP2 ( ) ) return false ; if ( Alignment && Alignment < <NUM_LIT> ) return false ; StrOpc = <STR_LIT> ; break ; } <ISA_LIT>SimplifyAddress ( Addr , VT , useAM3 ) ; SrcReg = constrainOperandRegClass ( TII . get ( StrOpc ) , SrcReg , <NUM_LIT> ) ; MachineInstrBuilder MIB = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc ,

TII . get ( StrOpc ) ) . addReg ( SrcReg ) ;


<s> for ( unsigned i = <NUM_LIT> ; i < Bits . size


<s> const MachineOperand * FirstDst = nullptr ; const MachineOperand * SecondDst = nullptr ; if ( ( isMUBUF ( FirstLdSt ) && isMUBUF ( SecondLdSt ) ) || ( isMTBUF ( FirstLdSt ) && isMTBUF ( SecondLdSt ) ) || ( isFLAT ( FirstLdSt ) && isFLAT ( SecondLdSt ) ) ) { const unsigned MaxGlobalLoadCluster = <NUM_LIT> ; if ( NumLoads > MaxGlobalLoadCluster ) return false ; FirstDst = getNamedOperand ( FirstLdSt , <STR_LIT> :: vdata ) ; if ( ! FirstDst ) FirstDst = getNamedOperand ( FirstLdSt , <STR_LIT> :: vdst ) ; SecondDst = getNamedOperand ( SecondLdSt , <STR_LIT> :: vdata ) ; if ( ! SecondDst ) SecondDst = getNamedOperand ( SecondLdSt , <STR_LIT> :: vdst ) ; } else if ( isSMRD ( FirstLdSt ) && isSMRD ( SecondLdSt ) ) { FirstDst = getNamedOperand ( FirstLdSt , <STR_LIT> :: sdst ) ; SecondDst = getNamedOperand ( SecondLdSt , <STR_LIT> :: sdst ) ; } else if ( isDS ( FirstLdSt ) && isDS


<s> } else { assert ( Stack . size ( ) >= <NUM_LIT> ) ; Stack . pop_back ( ) ; } for ( auto & MI : MBB ) switch ( MI . getOpcode ( ) ) { case <STR_LIT> : Stack . push_back ( std :: make_pair ( & MBB , false ) ) ; Stack . push_back ( std :: make_pair ( MI . getOperand ( <NUM_LIT> ) . getMBB ( ) , true ) ) ; break ; case <STR_LIT> : Stack . push_back ( std :: make_pair ( MI . getOperand ( <NUM_LIT> ) . getMBB ( ) , false ) ) ; break ; default : for ( const MachineOperand & MO : MI . explicit_operands ( ) ) if ( MO . isMBB ( ) && MO . getMBB ( ) -> getNumber ( ) >= <NUM_LIT> ) assert ( IsOnStack ( Stack , MO . getMBB ( ) ) ) ; break ; } } assert ( Stack . empty


<s> static SDValue combineSetCCCCR ( SDValue CCR , <STR_LIT> & CC , SelectionDAG & DAG , const <ISA_LIT>Subtarget & Subtarget ) { if ( CC == <STR_LIT> ) if ( SDValue Flags = combineCarryThroughADD ( CCR ) ) return Flags ; if ( SDValue R = checkBoolTestSetCCCombine ( CCR , CC ) ) return


<s> void <ISA_LIT>ELFStreamer :: emitIntValue ( uint64_t


<s> MVT VT = Op . getSimpleValueType ( ) ; if ( ! <STR_LIT> ( Cond . getNode ( ) ) ) return SDValue ( ) ; auto * CondBV = cast < BuildVectorSDNode > ( Cond ) ; SmallVector < int , <NUM_LIT> > Mask ; for ( int i = <NUM_LIT> , Size = VT . getVectorNumElements ( ) ; i < Size ; ++ i ) { SDValue CondElt = CondBV -> getOperand ( i ) ; Mask . push_back ( isa < ConstantSDNode > ( CondElt ) ? i + ( isNullConstant ( CondElt ) ? Size : <NUM_LIT> )


<s> switch ( MI . getOpcode ( ) ) { default : break ; case <STR_LIT> : ++ Depth ; If ( MI ) ; break ; case <STR_LIT> : Else ( MI , ExecModified ) ; break ; case <STR_LIT> : Break ( MI ) ; break ; case <STR_LIT> : IfBreak ( MI ) ; break ; case <STR_LIT> : ElseBreak ( MI ) ; break ; case <STR_LIT> : ++ Depth ; Loop ( MI ) ; break ; case <STR_LIT> : if ( -- Depth == <NUM_LIT> && HaveKill ) { HaveKill = false ; if ( skipIfDead ( MI , * NextBB ) ) { NextBB = std :: next ( BI ) ; BE = MF . end ( ) ; Next = MBB . end ( ) ; } } EndCf ( MI ) ; break ; case <STR_LIT> : if ( Depth == <NUM_LIT> ) { if ( skipIfDead ( MI , * NextBB ) ) { NextBB = std :: next ( BI ) ; BE = MF . end ( ) ; Next = MBB . end ( ) ; } } else HaveKill = true ; Kill ( MI ) ; break ; case <STR_LIT> : Branch ( MI ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( indirectSrc ( MI ) ) { NextBB = std :: next ( BI ) ; BE = MF . end ( ) ; Next = MBB . end ( ) ; } break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( indirectDst ( MI ) ) { NextBB = std :: next ( BI ) ; BE = MF . end ( ) ; Next = MBB . end ( ) ; } break ; case <STR_LIT> : { assert ( ! MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) -> returnsVoid ( ) ) ; if ( BI != -- MF . end ( ) || I != MBB . getFirstTerminator ( ) ) { if ( ! EmptyMBBAtEnd ) { EmptyMBBAtEnd = MF . CreateMachineBasicBlock ( ) ; MF . insert ( MF . end ( ) , EmptyMBBAtEnd ) ; } MBB . addSuccessor ( EmptyMBBAtEnd ) ; BuildMI ( * BI , I , MI . getDebugLoc ( ) , TII ->

get ( <STR_LIT> ) ) . addMBB ( EmptyMBBAtEnd ) ;


<s> return Create ( VK_AARCH64_DTPREL_G0_NC ,


<s> auto IsZext = [ & DAG ] ( SDValue V ) { return DAG . computeKnownBits ( V ) . countMaxActiveBits ( ) <= <NUM_LIT> ; } ; bool IsSigned = IsSext ( LHS ) && IsSext ( RHS ) ; bool IsUnsigned = IsZext ( LHS ) && IsZext ( RHS ) ; if ( ! IsSigned && ! IsUnsigned ) return SDValue ( ) ; bool IsTruncateFree = ( LHS . getOpcode ( ) == <STR_LIT> || LHS . getOpcode ( ) == <STR_LIT> ) && ( RHS . getOpcode ( ) == <STR_LIT> || RHS . getOpcode ( ) == <STR_LIT> ) && LHS . getOperand ( <NUM_LIT> ) . getScalarValueSizeInBits ( ) <= <NUM_LIT> && RHS . getOperand ( <NUM_LIT> ) . getScalarValueSizeInBits ( ) <= <NUM_LIT> ; unsigned InSizeInBits = InVT . getSizeInBits ( ) ; if ( IsUnsigned && ! IsTruncateFree && Subtarget . hasInt256 ( ) && ! ( Subtarget . hasAVX512 ( ) && ! Subtarget . hasBWI ( ) && VT . is256BitVector ( ) ) && ( InSizeInBits % <NUM_LIT> ) == <NUM_LIT> ) { EVT BCVT = EVT :: getVectorVT ( * DAG . getContext ( ) , <STR_LIT> , InVT . getSizeInBits ( ) / <NUM_LIT> ) ; SDValue Res = DAG . getNode ( <STR_LIT> , DL , BCVT , DAG . getBitcast ( BCVT , LHS ) , DAG . getBitcast ( BCVT , RHS ) ) ; return DAG . getNode ( <STR_LIT> , DL , VT , DAG . getBitcast ( InVT , Res ) ) ; } LHS = DAG . getNode ( <STR_LIT> , DL


<s> MCSymbol * OffsetSym = MF . getMMI ( ) . getContext ( ) . getOrCreateParentFrameOffsetSymbol ( GlobalValue :: dropLLVMManglingEscape ( Fn -> getName ( ) ) ) ; SDValue OffsetSymVal = DAG . getMCSymbol ( OffsetSym , PtrVT ) ; SDValue ParentFrameOffset = DAG . getNode ( <STR_LIT> , dl , PtrVT , OffsetSymVal ) ; const <ISA_LIT>Subtarget & Subtarget = DAG . getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( Subtarget . is64Bit ( ) ) return DAG . getNode ( <STR_LIT> , dl , PtrVT , EntryEBP , ParentFrameOffset ) ; int RegNodeSize = getSEHRegistrationNodeSize (


<s> bool <ISA_LIT>DAGToDAGISel :: SelectThumbAddrModeRI5 ( SDNode * Op , SDValue N , unsigned Scale , SDValue & Base , SDValue & OffImm , SDValue & Offset ) { if ( Scale == <NUM_LIT> ) { SDValue TmpBase , TmpOffImm ; if ( SelectThumbAddrModeSP ( Op , N , TmpBase , TmpOffImm ) ) return false ; if ( N . getOpcode ( ) == <STR_LIT> && N . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) return false ; } if ( N . getOpcode ( ) != <STR_LIT> ) { if ( N . getOpcode ( ) == <STR_LIT> && ! ( Subtarget -> useMovt ( ) && N . getOperand ( <NUM_LIT>


<s> struct constant_pool * pool , * * prev ; pool = s390_alloc_pool ( ) ; pool -> first_insn = insn ; for ( prev = pool_list ; * prev ; prev = & ( * prev


<s> for ( unsigned I = <NUM_LIT> , E = ArgLocs . size ( ) ; I != E ; ++ I ) { CCValAssign & VA = ArgLocs [ I ] ; if ( VA . getLocInfo ( ) == CCValAssign :: Indirect ) return false ; if ( ! VA . isRegLoc ( ) )


<s> void <ISA_LIT>InstPrinter :: printRegName ( raw_ostream & O , unsigned RegNo ) const { O << getRegisterName ( RegNo )


<s> RegisterTargetMachine < <ISA_LIT>TargetMachine > registered_target ( getThe<ISA_LIT>Target ( )


<s> bool <ISA_LIT>ShortenInst :: shortenFPConv ( MachineInstr & MI , unsigned Opcode ) { if ( <STR_LIT> ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) < <NUM_LIT> && <STR_LIT> ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) < <NUM_LIT> ) { MachineOperand Dest ( MI . getOperand ( <NUM_LIT> ) ) ; MachineOperand Src ( MI . getOperand ( <NUM_LIT> )


<s> static void get_pc_thunk_name ( char name [ <NUM_LIT> ] , unsigned int regno ) { gcc_assert ( ! TARGET_64BIT ) ; if ( USE_HIDDEN_LINKONCE ) sprintf ( name , <STR_LIT> , reg_names [ regno ] ) ; else ASM_GENERATE_INTERNAL_LABEL ( name , <STR_LIT> ,


<s> gcc_assert ( ( GET_CODE ( body ) == SET ) && ( GET_CODE ( SET_SRC ( body ) ) == VEC_SELECT || pattern_is_rotate64 ( body ) ) && MEM_P ( XEXP ( SET_SRC ( body ) , <NUM_LIT> ) ) ) ; rtx src_exp = XEXP ( SET_SRC ( body ) , <NUM_LIT> ) ; enum machine_mode mode = GET_MODE ( src_exp ) ; rtx lvx = rs6000_gen_lvx ( mode , SET_DEST ( body ) , src_exp ) ; rtx_insn * new_insn = emit_insn_before ( lvx , def_insn ) ; rtx new_body = PATTERN ( new_insn ) ; gcc_assert ( ( GET_CODE ( new_body ) == SET ) && MEM_P ( SET_SRC ( new_body ) ) ) ; set_block_for_insn ( new_insn , BLOCK_FOR_INSN ( def_insn ) ) ; df_insn_rescan ( new_insn ) ; df_insn_delete ( def_insn ) ; remove_insn ( def_insn ) ; def_insn -> set_deleted


<s> if ( isa < ConstantSDNode > ( Size ) ) return lowerDYNAMIC_STACKALLOCImpl ( Op , DAG ) ; return <ISA_LIT>TargetLowering :: LowerDYNAMIC_STACKALLOC (


<s> SDValue V1 = N -> getOperand ( <NUM_LIT> ) ; SDValue V2 = N -> getOperand ( <NUM_LIT> ) ; unsigned ShiftElts = <NUM_LIT> , InsertAtByte = <NUM_LIT> ; bool Swap = false ; unsigned LittleEndianShifts [ ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; unsigned BigEndianShifts [ ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; ArrayRef < int > Mask = N -> getMask ( ) ; int OriginalOrder [ ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; bool FoundCandidate = false ; unsigned VINSERTBSrcElem = IsLE ? <NUM_LIT> : <NUM_LIT> ; for ( unsigned i = <NUM_LIT> ; i < BytesInVector ; ++ i ) { unsigned CurrentElement = Mask [ i ] ; if ( V2 . isUndef ( ) && CurrentElement != VINSERTBSrcElem ) continue ; bool OtherElementsInOrder


<s> bool <ISA_LIT>CallLowering :: lowerFormalArguments ( MachineIRBuilder & MIRBuilder , const Function & F , ArrayRef < unsigned > VRegs ) const { if ( F . arg_empty ( ) ) return true ; if ( F . isVarArg ( ) ) return false ; MachineFunction & MF = MIRBuilder . getMF ( ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; auto DL = MF . getDataLayout ( ) ; SmallVector < ArgInfo , <NUM_LIT> > SplitArgs ; unsigned Idx = <NUM_LIT> ; for ( auto & Arg : F . args ( ) ) { if ( Arg . hasAttribute ( Attribute :: ByVal ) || Arg . hasAttribute ( Attribute :: InReg ) || Arg . hasAttribute ( Attribute :: StructRet ) || Arg . hasAttribute ( Attribute :: SwiftSelf ) || Arg . hasAttribute ( Attribute :: SwiftError ) || Arg . hasAttribute ( Attribute :: Nest ) ) return false ; ArgInfo OrigArg ( VRegs [ Idx ] , Arg . getType


<s> MCValue Val ; bool Res = Expr -> evaluateAsRelocatable ( Val , nullptr , nullptr ) ; ( void ) Res ; assert ( Res && <STR_LIT> ) ; assert ( ! Val . getSymB ( ) && <STR_LIT> ) ; O << <STR_LIT> << VarName << ':' << BaseOffset << ':' << EltSize << ':' ; if ( const MCSymbolRefExpr * SymA = Val . getSymA ( ) ) { const MCSymbol & Sym = SymA


<s> static DecodeStatus DecodePTRREGSRegisterClass ( MCInst & Inst , unsigned RegNo ,

uint64_t Address , const void * Decoder ) {


<s> SDValue Hi = DAG . getVectorShuffle ( InVT , dl , In , DAG . getUNDEF ( InVT ) , HiMask ) ; Hi = DAG . getNode ( Opc , dl , HalfVT , Hi ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Lo , Hi ) ; } assert ( Opc == <STR_LIT> && <STR_LIT> ) ; assert ( VT . is128BitVector ( ) && InVT . is128BitVector ( ) && <STR_LIT> ) ; SDValue Curr = In ; SDValue SignExt = Curr ; if ( InVT != <STR_LIT> ) { MVT DestVT = VT == <STR_LIT> ? <STR_LIT> : VT ; unsigned DestWidth = DestVT . getScalarSizeInBits ( ) ; unsigned Scale = DestWidth / InSVT . getSizeInBits ( ) ; unsigned InNumElts = InVT . getVectorNumElements ( ) ; unsigned DestElts = DestVT . getVectorNumElements ( ) ; SmallVector < int , <NUM_LIT> > Mask ( InNumElts , SM_SentinelUndef ) ; for ( unsigned i = <NUM_LIT> ; i != DestElts ; ++ i ) Mask [ i * Scale + ( Scale - <NUM_LIT> ) ] = i ; Curr = DAG . getVectorShuffle ( InVT , dl , In , In , Mask ) ; Curr = DAG . getBitcast ( DestVT , Curr ) ; unsigned SignExtShift = DestWidth - InSVT . getSizeInBits ( ) ; SignExt = DAG . getNode ( <STR_LIT> , dl , DestVT , Curr , DAG . getTargetConstant ( SignExtShift , dl , <STR_LIT> ) ) ; } if ( VT == <STR_LIT> ) { assert ( Curr . getValueType ( ) == <STR_LIT> && <STR_LIT> ) ; SDValue Zero = DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ; SDValue Sign = DAG . getSetCC ( dl , <STR_LIT> , Zero , Curr , <STR_LIT> ) ; SignExt = DAG . getVectorShuffle ( <STR_LIT> , dl , SignExt , Sign , { <NUM_LIT> , <NUM_LIT> ,


<s> void addMemSrc10Operands ( MCInst & Inst , unsigned N ) const { addMemSrcOperands ( Inst ,


<s> BasicBlock * IDom = DT -> getNode ( Parent ) -> getIDom ( ) -> getBlock ( ) ; for ( unsigned i = <NUM_LIT> , e = Phi -> getNumIncomingValues ( ) ; i != e ; ++ i ) { Value * Incoming = Phi -> getIncomingValue ( i ) ; if ( Incoming != BoolTrue ) continue ; BasicBlock * From = Phi -> getIncomingBlock ( i ) ; if ( From == IDom ) { CallInst * OldEnd = dyn_cast < CallInst > ( Parent -> getFirstInsertionPt ( ) ) ; if ( OldEnd && OldEnd -> getCalledFunction ( ) == EndCf ) { Value * Args [ ] = { OldEnd -> getArgOperand ( <NUM_LIT> ) , NewPhi } ; Ret = CallInst :: Create ( ElseBreak , Args , <STR_LIT> , OldEnd ) ; continue ; } } TerminatorInst * Insert = From -> getTerminator ( ) ; Value * PhiArg = CallInst :: Create ( Break , Broken , <STR_LIT> , Insert ) ; NewPhi -> setIncomingValue ( i , PhiArg ) ; } eraseIfUnused ( Phi ) ; return Ret ; } else if ( Instruction * Inst = dyn_cast < Instruction > ( Cond ) ) { BasicBlock * Parent = Inst -> getParent ( ) ; Instruction * Insert ; if ( L -> contains ( Inst ) ) { Insert = Parent -> getTerminator ( ) ; } else { Insert = L -> getHeader ( ) -> getFirstNonPHIOrDbgOrLifetime ( ) ; } Value * Args [ ] = { Cond , Broken } ; return CallInst :: Create ( IfBreak , Args , <STR_LIT> , Insert ) ; } else { llvm_unreachable ( <STR_LIT> )


<s> return create<ISA_LIT>MCSubtargetInfoImpl ( TT , CPU , FS


<s> Inst . addOperand ( MCOperand :: CreateImm (


<s> case <ISA_LIT>_VERSION_1_4 : return <STR_LIT> ; case <ISA_LIT>_VERSION_2_0 : return <STR_LIT> ; case <ISA_LIT>_VERSION_2_1 : return


<s> if ( ! MCE ) return isSymbolicUImm12Offset ( getImm ( ) , Scale ) ; int64_t Val = MCE -> getValue ( ) ; return ( Val % Scale ) == <NUM_LIT> && Val >= <NUM_LIT> && ( Val /


<s> if ( ConstantSDNode * Idx = dyn_cast < ConstantSDNode > ( In . getOperand ( <NUM_LIT> ) ) ) { if ( Idx -> isZero ( ) && In . getValueSizeInBits ( ) <=

<NUM_LIT> ) return In . getOperand ( <NUM_LIT> ) ;


<s> unsigned Reg = TargetRegisterInfo :: index2VirtReg ( i ) ; const TargetRegisterClass * TRC = MRI . getRegClass ( Reg ) ; unsigned RegType ; if ( TRC == <STR_LIT> ) RegType = <STR_LIT> ; else if ( TRC == <STR_LIT> ) RegType = <STR_LIT> ; else if ( TRC == <STR_LIT> ) RegType = <STR_LIT> ; else if ( TRC == <STR_LIT> ) RegType = <STR_LIT> ; else if ( TRC == <STR_LIT> ) RegType = <STR_LIT> ; else if ( TRC == <STR_LIT> ) RegType = <STR_LIT> ; else llvm_unreachable ( <STR_LIT> ) ; MFI -> addRegister ( Reg , RegType , <STR_LIT> ) ; } return


<s> unsigned EncodedImm = MI -> getOperand ( OpNum ) . getImm ( ) ; unsigned EltBits ; uint64_t Val = <STR_LIT> ( EncodedImm , EltBits ) ; O << markup ( <STR_LIT> ) <<


<s> bool <STR_LIT> ( CallingConv :: ID CallingConv , bool is64Bit , bool IsVarArg , bool TailCallOpt ) { if ( IsVarArg ) return false ; switch ( CallingConv )


<s> void addu16_3ImmOperands ( MCInst & Inst , unsigned N ) const { addImmOperands ( Inst


<s> InstructionSelector :: ComplexRendererFns <ISA_LIT>InstructionSelector :: selectDS128Bit8ByteAligned ( MachineOperand & Root ) const { return selectDSReadWrite2 ( Root , true


<s> SmallVector < SDValue , <NUM_LIT> > ULTOp1 ; for ( unsigned i = <NUM_LIT> ; i < n ; ++ i ) { ConstantSDNode * Elt = dyn_cast < ConstantSDNode > ( BV -> getOperand ( i ) ) ; if ( ! Elt || Elt -> isOpaque ( ) || Elt -> getValueType ( <NUM_LIT> ) != EVT ) return SDValue ( ) ; APInt Val = Elt -> getAPIntValue ( ) ; if ( Val == <NUM_LIT> ) return SDValue ( ) ; ULTOp1 . push_back ( DAG . getConstant ( Val - <NUM_LIT> , EVT ) ) ; } return DAG . getNode ( <STR_LIT> , dl , VT ,


<s> bool ValidLDType = MemoryType == <STR_LIT> || MemoryType == <STR_LIT> || MemoryType == <STR_LIT> || MemoryType == <STR_LIT> ; if ( ! ValidLDType || ( LD -> getExtensionType ( ) != <STR_LIT> && LD -> getExtensionType ( ) != <STR_LIT> ) ) return SDValue ( ) ; SDValue LoadOps [ ] = { LD -> getChain ( ) , LD -> getBasePtr ( ) , DAG . getIntPtrConstant (

MemoryType . getScalarSizeInBits ( ) , DL ) } ;


<s> RegisterMCAsmParser < <ISA_LIT>AsmParser > Y ( getThe<ISA_LIT>beTarget ( ) ) ; RegisterMCAsmParser < <ISA_LIT>AsmParser > Z (


<s> bool wasVisited ( const MachineInstr * MI ) const { return Types .


<s> bool hasV66Ops ( ) const { return get<ISA_LIT>ArchVersion ( ) >=


<s> TargetTransformInfo <ISA_LIT>TargetMachine :: getTargetTransformInfo ( const Function & F ) { return TargetTransformInfo ( <ISA_LIT>TTIImpl ( this ,


<s> if ( RegNo >= <NUM_LIT> ) return MCDisassembler :: Fail ; if ( RegNo % <NUM_LIT> ) return MCDisassembler :: Fail ; const <ISA_LIT>Disassembler * Dis = static_cast < const <ISA_LIT>Disassembler * > ( Decoder ) ; const MCRegisterInfo * RI = Dis -> getContext ( ) . getRegisterInfo ( ) ; MCRegister Reg = RI -> getMatchingSuperReg ( <STR_LIT> + RegNo , <STR_LIT> , & <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] ) ; Inst . addOperand ( MCOperand :: createReg (


<s> SDValue EltVal = StVal . getOperand ( I ) ; if ( ! isNullConstant ( EltVal ) && ! isNullFPConstant ( EltVal ) ) return SDValue ( ) ; } SDLoc DL ( & St ) ; unsigned ZeroReg ; EVT ZeroVT ; if ( VT . getVectorElementType ( ) . getSizeInBits ( ) == <NUM_LIT> ) { ZeroReg = <STR_LIT> ; ZeroVT = <STR_LIT> ; } else { ZeroReg = <STR_LIT> ; ZeroVT = <STR_LIT> ; } SDValue SplatVal = DAG . getCopyFromReg ( DAG . getEntryNode ( ) , DL , ZeroReg , ZeroVT ) ; return splitStoreSplat ( DAG , St , SplatVal


<s> FunctionPass * create<ISA_LIT>ExpandPseudoPass ( )


<s> return true ; } assert ( N -> getOpcode ( ) == <STR_LIT> && <STR_LIT> ) ; N = N . getOperand ( <NUM_LIT> ) ; if ( N -> getOpcode ( ) != <STR_LIT> && N -> getOpcode ( ) != <STR_LIT> && N -> getOpcode ( ) != <STR_LIT> && N -> getOpcode ( ) != <STR_LIT> && N -> getOpcode ( ) != <STR_LIT> &&

N -> getOpcode ( ) != <STR_LIT> ) return false ;


<s> for ( MachineInstr * MI : LoweredEndCf ) { MachineBasicBlock & MBB = * MI -> getParent ( ) ; auto Next = skipIgnoreExecInstsTrivialSucc ( MBB , std :: next ( MI -> getIterator ( ) ) ) ; if ( Next == MBB . end ( ) || ! LoweredEndCf . count ( &


<s> unsigned NumElems = HwLen / ( ElemTy


<s> else CC = StringSwitch < unsigned > ( Name ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( - <NUM_LIT> ) ; if ( CC != - <NUM_LIT> ) return CC ; if ( Name [ <NUM_LIT> ] == 'f' ) { StringRef NumString = Name . substr ( <NUM_LIT> ) ; unsigned IntVal ; if ( NumString . getAsInteger ( <NUM_LIT> , IntVal ) ) return - <NUM_LIT> ; if ( IntVal > <NUM_LIT> ) return - <NUM_LIT> ; FpFormatTy Format = getFpFormat


<s> virtual void getAnalysisUsage ( AnalysisUsage & AU ) const { AU . setPreservesCFG ( ) ; AU . addRequired < MachineDominatorTree > (


<s> LLVMContext * Context = DAG . getContext ( ) ; DebugLoc dl = Op . getDebugLoc ( ) ; EVT VT = Op . getValueType ( ) ; EVT EltVT = VT ; if ( VT . isVector ( ) ) EltVT = VT . getVectorElementType ( ) ; Constant * C ; if ( EltVT == <STR_LIT> ) { C = ConstantVector :: getSplat ( <NUM_LIT> , ConstantFP :: get ( * Context , APFloat ( APInt ( <NUM_LIT> , ~ ( <NUM_LIT> << <NUM_LIT> ) ) ) ) ) ; } else { C = ConstantVector :: getSplat ( <NUM_LIT> , ConstantFP :: get ( * Context , APFloat ( APInt ( <NUM_LIT>


<s> F -> insert ( MBBIter , XMMSaveMBB ) ; F -> insert ( MBBIter , EndMBB ) ; EndMBB -> splice ( EndMBB -> begin ( ) , MBB , llvm :: next ( MachineBasicBlock :: iterator ( MI ) ) , MBB -> end ( ) ) ; EndMBB -> transferSuccessorsAndUpdatePHIs ( MBB ) ; MBB -> addSuccessor ( XMMSaveMBB ) ; XMMSaveMBB -> addSuccessor ( EndMBB ) ; const TargetInstrInfo * TII = getTargetMachine ( ) . getInstrInfo ( ) ; DebugLoc DL = MI -> getDebugLoc ( ) ; unsigned CountReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; int64_t RegSaveFrameIndex = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; int64_t VarArgsFPOffset = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( ! Subtarget -> isTargetWin64 ( ) ) { BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) ) . addReg ( CountReg ) . addReg ( CountReg ) ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) ) . addMBB ( EndMBB ) ; MBB -> addSuccessor ( EndMBB ) ; } unsigned MOVOpc = Subtarget -> hasAVX


<s> BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addMBB ( TBB ) ; return <NUM_LIT> ; } llvm_unreachable ( <STR_LIT> ) ; return


<s> Uses . clear ( ) ; TrackDefUses ( MI , Defs , Uses , TRI ) ; MachineInstrBuilder MIB = BuildMI ( MBB , MBBI , dl , TII -> get ( <STR_LIT> ) ) . addImm ( CC ) ; MI -> addOperand ( MachineOperand :: CreateReg ( <STR_LIT> , false , true , false ) ) ; MachineInstr * LastITMI = MI ; MachineBasicBlock :: iterator InsertPos = MIB . getInstr ( ) ; ++ MBBI ; <STR_LIT> OCC = <STR_LIT> ( CC ) ; unsigned Mask = <NUM_LIT> , Pos = <NUM_LIT> ; if ( ! restrictIT ) { for ( ; MBBI != E && Pos && ( ! MI -> isBranch ( ) && ! MI -> isReturn ( ) ) ; ++ MBBI ) { if ( MBBI -> isDebugValue ( ) ) continue ; MachineInstr * NMI = & * MBBI ; MI = NMI ; unsigned NPredReg = <NUM_LIT> ; <STR_LIT> NCC = getITInstrPredicate ( * NMI , NPredReg ) ; if ( NCC == CC || NCC == OCC ) { Mask |= ( NCC & <NUM_LIT> ) << Pos ; NMI -> addOperand ( MachineOperand :: CreateReg ( <STR_LIT> , false , true , false ) ) ; LastITMI = NMI ; } else { if ( NCC == <STR_LIT> && MoveCopyOutOfITBlock ( NMI , CC , OCC , Defs , Uses ) ) { -- MBBI ; MBB . remove ( NMI ) ; MBB . insert ( InsertPos , NMI ) ; ClearKillFlags ( MI , Uses ) ; ++ NumMovedInsts ; continue ; } break ; } TrackDefUses ( NMI , Defs , Uses , TRI ) ; -- Pos ; } } Mask |= ( <NUM_LIT> << Pos ) ; Mask |= ( CC & <NUM_LIT> ) << <NUM_LIT> ; MIB . addImm ( Mask ) ; LastITMI -> findRegisterUseOperand ( <STR_LIT> ) -> setIsKill ( ) ; finalizeBundle ( MBB , InsertPos . getInstrIterator ( ) , ++ LastITMI -> getIterator ( ) ) ; Modified = true ; ++ NumITs


<s> Inst . addOperand ( MCOperand :: createImm ( Reg . Modifiers == - <NUM_LIT>


<s> unsigned LFS = MFI -> getLocalFrameSize ( ) ; int Offset = - LFS ; for ( int i = <NUM_LIT> , e = MFI -> getObjectIndexEnd ( ) ; i != e ; ++ i ) { if ( ! MFI -> isSpillSlotObjectIndex ( i ) || MFI -> isDeadObjectIndex ( i ) ) continue ; int S = MFI -> getObjectSize ( i ) ; LFS += S ; Offset -= S ; MFI -> mapLocalFrameObject ( i , Offset ) ; } MFI -> setLocalFrameSize ( LFS ) ; unsigned A = MFI -> getLocalFrameMaxAlign ( ) ; assert ( A <=


<s> } } emit_insn ( gen_force_register_use ( stack_pointer_rtx ) ) ; if ( crtl -> profile || ! TARGET_SCHED_PROLOG ) emit_insn ( gen_blockage ( ) ) ; for ( regno = <NUM_LIT> ; regno < <NUM_LIT> ; regno ++ ) if ( reg_needs_saving_p ( regno ) ) emit_clobber ( gen_rtx_REG ( SImode , regno ) ) ; if ( ! df_regs_ever_live_p ( LR_REGNUM ) ) emit_use ( gen_rtx_REG ( SImode , LR_REGNUM ) ) ; if ( IS_CMSE_ENTRY ( arm_current_func_type ( ) ) )


<s> typedef std :: vector < unsigned > SortableVectorType ; SortableVectorType VRs ; for ( RegisterOrdering :: iterator I = RB . begin ( ) , E = RB . end ( ) ; I != E ; ++ I ) VRs . push_back ( I -> first ) ; std :: sort ( VRs . begin ( ) , VRs


<s> if ( ST -> hasPOPCNTD ( ) && TyWidth <= <NUM_LIT> ) return PSK_FastHardware ; return PSK_Software


<s> void printTOCEntryLabel ( const MachineInstr * MI , unsigned OpNo , raw_ostream & O ) { const MachineOperand & MO = MI -> getOperand ( OpNo ) ; assert ( MO . getType ( ) == MachineOperand :: MO_GlobalAddress


<s> const char * oldname ; char * newname ; tree idp ; rtx rtlname ; rtx newrtl ; rtlname = XEXP ( DECL_RTL ( decl ) , <NUM_LIT> ) ; if ( GET_CODE ( rtlname ) == MEM ) rtlname = XEXP ( rtlname , <NUM_LIT> ) ; gcc_assert ( GET_CODE ( rtlname ) == SYMBOL_REF ) ; oldname = XSTR ( rtlname , <NUM_LIT> ) ; gcc_assert ( ! mcore_dllexport_name_p ( oldname ) ) ; if ( mcore_dllimport_name_p ( oldname ) ) return ; if ( TREE_CODE ( decl ) == VAR_DECL && ! DECL_VIRTUAL_P ( decl ) && DECL_INITIAL ( decl ) ) { error ( <STR_LIT> , decl ) ; return ; } if ( TREE_CODE ( decl ) == VAR_DECL && ! DECL_VIRTUAL_P ( decl ) ) { DECL_EXTERNAL ( decl ) = <NUM_LIT> ; TREE_PUBLIC ( decl ) = <NUM_LIT> ; } newname = XALLOCAVEC ( char , strlen ( oldname ) + <NUM_LIT> ) ; sprintf ( newname , <STR_LIT> , oldname ) ; idp = get_identifier ( newname )


<s> RegisterAsmPrinter < <ISA_LIT>AsmPrinter > X ( getThe<ISA_LIT>Target ( )


<s> ArrayRef < int > Mask = SVOp -> getMask ( ) ; assert ( Mask . size ( ) == <NUM_LIT> && <STR_LIT> ) ; if ( isSingleInputShuffleMask ( Mask ) ) { unsigned SHUFPDMask = ( Mask [ <NUM_LIT> ] == <NUM_LIT> ) | ( ( Mask [ <NUM_LIT> ] == <NUM_LIT> ) << <NUM_LIT> ) ; return DAG . getNode ( <STR_LIT> , SDLoc ( Op ) , <STR_LIT> , V1 , V1 , DAG . getConstant ( SHUFPDMask , <STR_LIT> ) ) ; } assert ( Mask [ <NUM_LIT> ] >= <NUM_LIT> && Mask [ <NUM_LIT> ] < <NUM_LIT> && <STR_LIT> ) ; assert ( Mask [ <NUM_LIT> ] >= <NUM_LIT> && <STR_LIT> ) ; if ( isShuffleEquivalent ( Mask , <NUM_LIT> , <NUM_LIT> ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , V2 ) ; if ( isShuffleEquivalent ( Mask , <NUM_LIT> , <NUM_LIT> ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , V2 ) ; unsigned SHUFPDMask = ( Mask [ <NUM_LIT> ] == <NUM_LIT> ) | ( (

( Mask [ <NUM_LIT> ] - <NUM_LIT> ) == <NUM_LIT> ) << <NUM_LIT> ) ;


<s> if ( PassThru -> isUndef ( ) || isZerosVector ( PassThru . getNode ( ) ) ) return Op ; SDValue Load = DAG . getMaskedLoad ( VT , DL , LoadNode -> getChain ( ) , LoadNode -> getBasePtr ( ) , LoadNode -> getOffset ( ) , Mask , DAG . getUNDEF ( VT ) , LoadNode -> getMemoryVT ( ) , LoadNode -> getMemOperand ( ) , LoadNode -> getAddressingMode ( ) , LoadNode -> getExtensionType ( ) ) ; SDValue Result = DAG . getSelect ( DL , VT , Mask , Load , PassThru ) ; return DAG . getMergeValues ( { Result , Load . getValue ( <NUM_LIT> ) } ,


<s> bool AMDGPUSubtarget :: hasCaymanISA ( )


<s> bool OptSize = Attr . hasAttribute ( AttributeList :: FunctionIndex ,


<s> if ( GlobalAddressSDNode * N = dyn_cast < GlobalAddressSDNode > ( Op ) ) return DAG . getTargetGlobalAddress ( N -> getGlobal ( ) , Op . getDebugLoc ( ) , Ty , <NUM_LIT> , Flag ) ; if ( ExternalSymbolSDNode * N = dyn_cast < ExternalSymbolSDNode > ( Op ) ) return DAG . getTargetExternalSymbol ( N -> getSymbol ( ) , Ty , Flag ) ; if ( BlockAddressSDNode * N = dyn_cast < BlockAddressSDNode > ( Op ) ) return DAG . getTargetBlockAddress ( N -> getBlockAddress (


<s> MVT InterVT = <STR_LIT> ( <STR_LIT> , VT . getVectorElementCount ( ) * <NUM_LIT> ) ; auto InterVec = DAG . getNode ( <STR_LIT> , DL , InterVT , Lo , VL ) ; return DAG . getNode ( <STR_LIT> , DL , VT , InterVec ) ; } } return DAG . getNode ( <STR_LIT> , DL ,


<s> return __builtin_aarch64_sqdmlal2_nv4si ( __a ,


<s> uint64_t TSFlags = Desc . TSFlags ; if ( ( TSFlags & <STR_LIT> ) == ( STI . hasFeature ( <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ) ) emitByte ( <NUM_LIT> , OS ) ; if ( TSFlags & <STR_LIT> || MI . getFlags ( ) & <STR_LIT> ) emitByte ( <NUM_LIT> , OS ) ; if ( TSFlags & <STR_LIT> || MI . getFlags ( ) & <STR_LIT> ) emitByte ( <NUM_LIT> , OS ) ; switch ( TSFlags & <STR_LIT> ) { case <STR_LIT> : emitByte ( <NUM_LIT> , OS ) ; break ; case <STR_LIT> : emitByte ( <NUM_LIT> , OS ) ; break ; case <STR_LIT> : emitByte ( <NUM_LIT> , OS ) ; break ; } assert ( ( STI . hasFeature ( <STR_LIT> ) || ! ( TSFlags & <STR_LIT> ) ) && <STR_LIT> ) ; bool HasREX = STI . hasFeature ( <STR_LIT> ) ? emitREXPrefix ( MemOperand , MI , STI , OS ) : false ; switch ( TSFlags & <STR_LIT> ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : emitByte ( <NUM_LIT> , OS ) ; break ; } switch ( TSFlags & <STR_LIT> ) { case <STR_LIT> : emitByte ( <NUM_LIT> , OS


<s> unsigned ADDri = getADDriOpcode ( false , EndOffset ) ; BuildMI ( MBB , MBBI , DL , TII . get ( ADDri ) , FramePtr ) . addReg ( FramePtr ) . addImm ( EndOffset ) . setMIFlag ( MachineInstr :: FrameSetup ) -> getOperand ( <NUM_LIT> ) . setIsDead ( ) ; assert ( EndOffset >= <NUM_LIT> && <STR_LIT> ) ; } else if ( UsedReg == BasePtr ) { addRegOffset ( BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) , BasePtr ) , FramePtr , false , EndOffset ) . setMIFlag ( MachineInstr :: FrameSetup ) ; assert ( <ISA_LIT>FI -> getHasSEHFramePtrSave ( ) ) ; int Offset = getFrameIndexReference ( MF , <ISA_LIT>FI -> getSEHFramePtrSaveIndex ( ) , UsedReg ) ; assert ( UsedReg == BasePtr ) ; addRegOffset ( BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) , FramePtr ) , UsedReg , true , Offset ) . setMIFlag ( MachineInstr :: FrameSetup ) ; }


<s> ExtOp2 = Builder . CreateZExt ( I . getOperand ( <NUM_LIT> ) , I32Ty ) ; } ExtRes = Builder . CreateSelect ( I . getOperand ( <NUM_LIT> ) , ExtOp1 , ExtOp2 ) ; TruncRes = Builder . CreateTrunc ( ExtRes , I . getType ( ) ) ; I . replaceAllUsesWith ( TruncRes ) ; I . eraseFromParent ( ) ; return true


<s> uint64_t MaxVal = ( ( uint64_t ( <NUM_LIT> ) << Bits ) - <NUM_LIT> ) * Scale ; return Val <= MaxVal && ( Val %


<s> switch ( mode ) { case Pmode : case QImode : return IS_INT_REGNO ( regno ) ; case QFmode : case HFmode : return IS_EXT_REGNO ( regno ) ; case CCmode : case CC_NOOVmode : return IS_ST_REGNO ( regno )


<s> Type * Ty = MemVT . getTypeForEVT ( * DAG . getContext ( ) ) ; PointerType * PtrTy = PointerType :: get ( Ty , AMDGPUA<ISA_LIT> . CONSTANT_ADDRESS ) ; MachinePointerInfo PtrInfo ( UndefValue :: get ( PtrTy ) ) ; if ( MemVT . getStoreSize ( ) < <NUM_LIT> && Align < <NUM_LIT> ) { int64_t AlignDownOffset = alignDown ( Offset , <NUM_LIT> ) ; int64_t OffsetDiff = Offset - AlignDownOffset ; EVT IntVT = MemVT . changeTypeToInteger ( ) ; SDValue Ptr = lowerKernArgParameterPtr ( DAG , SL , Chain , AlignDownOffset ) ; SDValue Load = DAG . getLoad ( <STR_LIT> , SL , Chain , Ptr , PtrInfo , <NUM_LIT> , MachineMemOperand :: MODereferenceable | MachineMemOperand :: MOInvariant ) ; SDValue ShiftAmt = DAG . getConstant ( OffsetDiff * <NUM_LIT> , SL , <STR_LIT> ) ; SDValue Extract = DAG . getNode ( <STR_LIT> , SL ,


<s> case <STR_LIT> : return LowerUDIVREM ( Op , DAG ) ; case <STR_LIT> : return LowerSDIVREM ( Op , DAG ) ; case <STR_LIT> : return LowerFREM ( Op , DAG ) ; case <STR_LIT> : return LowerFCEIL ( Op , DAG ) ; case <STR_LIT> : return LowerFTRUNC ( Op , DAG ) ; case <STR_LIT> : return LowerFRINT ( Op , DAG ) ; case <STR_LIT> : return LowerFNEARBYINT ( Op , DAG ) ; case <STR_LIT> : return LowerFROUND ( Op , DAG ) ; case <STR_LIT> : return LowerFFLOOR ( Op , DAG ) ; case <STR_LIT> : return Lower<ISA_LIT>NT_TO_FP ( Op , DAG ) ; case <STR_LIT> : return LowerUINT_TO_FP ( Op , DAG ) ; case <STR_LIT> : return LowerFP_TO_FP16 ( Op , DAG ) ; case <STR_LIT> : return LowerFP_TO_<ISA_LIT>NT ( Op , DAG


<s> return ; } SectionKind GVKind = getObjFileLowering ( ) . getKindForGlobal ( GV , TM ) ; if ( ! GVKind . isGlobalWriteableData ( ) && ! GVKind . isReadOnly ( ) && ! GVKind . isThreadLocal ( ) ) report_fatal_error ( <STR_LIT> <STR_LIT> ) ; if ( isVerbose ( ) ) { if ( GV -> hasInitializer ( ) ) { GV -> printAsOperand ( OutStreamer -> GetCommentOS ( ) , false , GV -> getParent ( ) ) ; OutStreamer -> GetCommentOS ( ) << '\n' ; } } MCSectionXCOFF * Csect = cast < MCSectionXCOFF > ( getObjFileLowering ( ) . SectionForGlobal ( GV , GVKind , TM ) ) ; OutStreamer -> SwitchSection ( Csect ) ; const DataLayout & DL = GV -> getParent ( ) -> getDataLayout ( ) ; if ( GV -> hasCommonLinkage ( ) || GVKind . isBSSLocal ( ) || GVKind . isThreadBSSLocal ( ) ) { Align Alignment = GV -> getAlign ( ) . getValueOr ( DL . getPreferredAlign ( GV ) ) ; uint64_t Size = DL . getTypeAllocSize ( GV -> getType ( ) -> getElementType ( ) ) ; GVSym -> setStorageClass ( TargetLoweringObjectFileXCOFF :: getStorageClassForGlobal ( GV ) ) ; if ( GVKind . isBSSLocal ( ) || GVKind . isThreadBSSLocal ( ) ) OutStreamer -> emitXCOFFLocalCommonSymbol ( OutContext . getOrCreateSymbol ( GVSym -> getSymbolTableName ( ) ) , Size , GVSym , Alignment . value ( ) ) ; else OutStreamer -> emitCommonSymbol ( GVSym , Size , Alignment . value ( ) ) ; return ; } MCSymbol * EmittedInitSym = GVSym ; emitLinkage ( GV , EmittedInitSym ) ; emitAlignment ( getGVAlignment ( GV , DL ) , GV ) ; if ( ! TM . getDataSections ( ) || GV -> hasSection ( ) ) { OutStreamer -> emitLabel ( EmittedInitSym ) ; } llvm :: for_each ( GOAliasMap [ GV ] , [ this ] ( const GlobalAlias * Alias ) { OutStreamer -> emitLabel ( getSymbol ( Alias )


<s> const <STR_LIT> InvCC = changeICMPPredTo<ISA_LIT>CC ( CmpInst :: getInversePredicate ( ( CmpInst :: Predicate ) Pred ) ) ; auto I = MIRBuilder . buildInstr ( <STR_LIT> , { DefReg } , { Register ( <STR_LIT> ) , Register ( <STR_LIT> ) } ) . addImm ( InvCC ) ; constrainSelectedInstRegOperands ( * I , TII


<s> const MCInstrDesc & II = TII . get ( MachineInstOpcode ) ; Op0 = constrainOperandRegClass ( II , Op0 , <NUM_LIT> ) ; if ( II . getNumDefs ( ) >= <NUM_LIT> ) { AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , II , ResultReg ) . addReg ( Op0 , Op0IsKill * RegState :: Kill ) . addImm ( Imm ) ) ; } else { AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , II ) . addReg ( Op0 , Op0IsKill * RegState :: Kill ) . addImm ( Imm ) ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( TargetOpcode :: COPY ) , ResultReg ) . addReg ( II .


<s> MachineBasicBlock * DestBB = MI -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; if ( BBIsInRange ( MI , DestBB , Br . MaxDisp ) ) return false ; if ( ! Br . isCond ) return


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return


<s> MachineFunction :: iterator NextBB ; MachineBasicBlock * EmptyMBBAtEnd = nullptr ; for ( MachineFunction :: iterator BI = MF . begin ( ) , BE = MF . end ( ) ; BI != BE ; BI = NextBB ) { NextBB = std :: next ( BI ) ; MachineBasicBlock & MBB = * BI ; bool HaveSkipBlock = false ; if ( ! ExecBranchStack . empty ( ) && ExecBranchStack . back ( ) == & MBB ) { ExecBranchStack . pop_back ( ) ; } if ( HaveKill && ExecBranchStack . empty ( ) ) { HaveKill = false ; } MachineBasicBlock :: iterator I , Next ; for ( I = MBB . begin ( ) ; I != MBB . end ( ) ; I = Next ) { Next = std :: next ( I ) ; MachineInstr & MI = * I ; switch ( MI . getOpcode ( ) ) { case <STR_LIT> : ExecBranchStack . push_back ( MI . getOperand ( <NUM_LIT> ) . getMBB ( ) ) ; MadeChange |= skipMaskBranch ( MI , MBB ) ; break ; case <STR_LIT> : if ( MBB . isLayoutSuccessor ( MI . getOperand ( <NUM_LIT> ) . getMBB ( ) ) ) { MI . eraseFromParent ( ) ; } else if ( HaveSkipBlock ) { MI . eraseFromParent ( ) ; } break ; case <STR_LIT> : MadeChange = true ; kill ( MI ) ; if ( ExecBranchStack . empty ( ) ) { if ( skipIfDead ( MI , * NextBB ) ) { HaveSkipBlock = true ; NextBB = std :: next ( BI ) ; BE = MF . end ( ) ; } } else { HaveKill = true ; } MI . eraseFromParent (


<s> BuildMI ( MBB , & MI , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( Idx ) . addImm ( Offset ) ; } else { BuildMI ( MBB , & MI , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( Idx ) ; } MBB . insert ( I , MovRel ) ; } else { assert ( <STR_LIT> . contains ( Save ) ) ; assert ( <STR_LIT> . contains ( Idx ) ) ; BuildMI ( MBB , & MI , DL , TII -> get ( <STR_LIT> ) , Save ) . addReg ( <STR_LIT> ) ; BuildMI ( MBB , & MI , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( Idx ) ; BuildMI ( MBB , & MI , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) ; BuildMI ( MBB , & MI , DL , TII -> get ( <STR_LIT> ) ) . addReg ( <STR_LIT> ) . addReg ( Idx ) ; BuildMI ( MBB , & MI , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) ; if ( Offset ) { BuildMI ( MBB , & MI , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( Offset ) ; } MBB . insert ( I , MovRel ) ; BuildMI ( MBB , & MI , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) ; BuildMI ( MBB , & MI , DL , TII -> get ( <STR_LIT> ) ) . addImm ( - <NUM_LIT> ) ; BuildMI ( MBB , & MI , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg


<s> const <ISA_LIT>Disassembler * Dis = static_cast < const <ISA_LIT>Disassembler * > ( D ) ; const MCRegisterInfo * RegInfo = Dis -> getContext ( ) . getRegisterInfo ( ) ; return RegInfo -> getRegClass ( RC ) . getRegister


<s> for ( unsigned i = <NUM_LIT> , e = mi -> getDesc ( ) . getNumDefs ( ) ; i != e ; ++ i ) { MachineOperand & mo = mi -> getOperand ( i ) ; if ( ! mo . isReg ( ) ) continue ; int rx = RegIndex ( mo . getReg (


<s> LoopBlocks ( MachineBasicBlock * Entry , const BlockSet & Enterers ) : Entry ( Entry ) , Enterers ( Enterers ) { calculate (


<s> const <ISA_LIT>TargetLowering * getTargetLowering ( ) const override { return & TLInfo


<s> return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT>


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) : LLVMTargetMachine ( T , getDataLayoutString ( TT ) , TT , CPU , computeFSAdditions ( FS ,

OL , TT ) , Options , getEffectiveRelocModel ( TT , RM ) , CM , OL ) , TLOF ( createTLOF ( getTargetTriple ( ) ) ) , TargetABI ( computeTargetABI ( TT , Options ) ) , Subtarget ( TargetTriple , CPU , computeFSAdditions ( FS , OL , TT ) , * this ) {


<s> StringRef getPassName ( ) const override


<s> PM . add ( createBlackfinISelDag ( * this , OptLevel


<s> unsigned Stalls ; } ; SmallVector < BankStall , <NUM_LIT> > BankStalls ; for ( int Bank = <NUM_LIT> ; Bank < NUM_BANKS ; ++ Bank ) { if ( C . FreeBanks & ( <NUM_LIT> << Bank ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << printBank ( Bank ) << '\n' ) ; unsigned Stalls = computeStallCycles ( C . Reg , C . Reg , Bank ) ; if ( Stalls < OrigStalls ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << printBank ( Bank ) << <STR_LIT> << Stalls << '\n' ) ; BankStalls . push_back ( BankStall ( ( unsigned ) Bank , Stalls ) ) ; } } } std :: sort ( BankStalls . begin ( ) , BankStalls . end ( ) ) ; Register OrigReg = VRM -> getPhys ( C . Reg ) ; LRM -> unassign ( LI ) ; while ( ! BankStalls . empty ( ) ) { BankStall BS = BankStalls . pop_back_val ( ) ; unsigned Reg = scavengeReg ( LI , BS .


<s> SelectionDAG & DAG = DCI . DAG ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; EVT StVT = St -> getMemoryVT ( ) ; unsigned NumElems = VT . getVectorNumElements ( ) ; assert ( StVT != VT && <STR_LIT> ) ; unsigned FromEltSz = VT . getVectorElementType ( ) . getSizeInBits ( ) ; unsigned ToEltSz = StVT . getVectorElementType ( ) . getSizeInBits ( ) ; if ( ! isPowerOf2_32 ( NumElems * FromEltSz * ToEltSz ) ) return SDValue ( ) ; if ( <NUM_LIT> != ( NumElems * FromEltSz ) % ToEltSz ) return SDValue ( ) ; unsigned SizeRatio = FromEltSz / ToEltSz ; assert ( SizeRatio * NumElems * ToEltSz == VT . getSizeInBits ( ) ) ; EVT WideVecVT = EVT :: getVectorVT ( * DAG . getContext ( ) , StVT . getScalarType ( ) , NumElems * SizeRatio ) ; assert ( WideVecVT . getSizeInBits ( ) == VT . getSizeInBits ( ) ) ; SDLoc DL ( St ) ; SDValue WideVec = DAG . getNode ( <STR_LIT> , DL , WideVecVT , StVal ) ; SmallVector < int , <NUM_LIT> > ShuffleVec ( NumElems * SizeRatio , - <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i < NumElems ; ++ i ) ShuffleVec [ i ] = TLI . isBigEndian ( ) ? ( i + <NUM_LIT> ) * SizeRatio - <NUM_LIT> : i * SizeRatio ; if ( ! TLI . isTypeLegal ( WideVecVT ) ) return SDValue ( ) ; SDValue Shuff = DAG . getVectorShuffle ( WideVecVT , DL , WideVec , DAG . getUNDEF ( WideVec . getValueType ( ) ) , ShuffleVec . data ( ) ) ; MVT StoreType = <STR_LIT> ; for ( MVT Tp : <STR_LIT> ( ) ) { if ( TLI . isTypeLegal ( Tp ) && Tp . getSizeInBits ( ) <= NumElems * ToEltSz ) StoreType = Tp ; } if ( ! TLI . isTypeLegal ( StoreType ) ) return SDValue ( ) ; EVT StoreVecVT = EVT :: getVectorVT ( * DAG . getContext ( ) , StoreType , VT . getSizeInBits ( ) / EVT ( StoreType ) . getSizeInBits ( ) ) ; assert ( StoreVecVT . getSizeInBits ( ) == VT . getSizeInBits ( ) ) ; SDValue ShuffWide = DAG . getNode ( <STR_LIT> , DL , StoreVecVT , Shuff ) ; SmallVector < SDValue , <NUM_LIT> > Chains ; SDValue Increment = DAG . getConstant ( StoreType . getSizeInBits ( ) / <NUM_LIT> , DL , TLI . getPointerTy ( ) ) ; SDValue BasePtr = St -> getBasePtr ( ) ; unsigned E = ( ToEltSz * NumElems ) / StoreType . getSizeInBits ( ) ; for ( unsigned I = <NUM_LIT> ; I < E ; I ++ ) { SDValue SubVec = DAG . getNode ( <STR_LIT> , DL , StoreType , ShuffWide , DAG


<s> assert ( Width == <NUM_LIT> && <STR_LIT> ) ; unsigned DestReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned ScratchReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned AddrReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned IncrReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned MaskReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; AtomicOrdering Ordering = static_cast < AtomicOrdering > ( MI . getOperand ( <NUM_LIT> ) . getImm ( ) ) ; BuildMI ( LoopMBB , DL , TII -> get ( getLRForRMW32 ( Ordering ) ) , DestReg ) . addReg ( AddrReg ) ; switch ( BinOp ) { default : llvm_unreachable ( <STR_LIT> )


<s> if ( VT . isFloatingPoint ( ) ) { assert ( ( ScalarSize == <NUM_LIT> || ScalarSize == <NUM_LIT> ) && <STR_LIT> ) ; if ( ScalarSize == <NUM_LIT> ) Const = ConstantFP :: get ( Type :: getFloatTy ( C ) , Val . bitsToFloat ( ) ) ; else Const = ConstantFP :: get ( Type :: getDoubleTy ( C ) , Val . bitsToDouble ( ) ) ; } else Const = Constant :: getIntegerValue ( Type :: getIntNTy ( C , ScalarSize


<s> } break ; } case MachineOperand :: MO_Immediate : { int64_t Imm = MO . getImm ( ) ; O << '#' ; if ( ( Modifier && strcmp ( Modifier , <STR_LIT> ) == <NUM_LIT> ) || ( TF & <STR_LIT> ) ) O << <STR_LIT> ; else if ( ( Modifier && strcmp ( Modifier , <STR_LIT> ) == <NUM_LIT> ) || ( TF & <STR_LIT> ) ) O << <STR_LIT> ; O << Imm ; break ; } case MachineOperand :: MO_MachineBasicBlock : O << * MO . getMBB ( ) -> getSymbol ( ) ; return ; case MachineOperand :: MO_GlobalAddress : { bool isCallOp = Modifier && ! strcmp ( Modifier , <STR_LIT> ) ; GlobalValue * GV = MO . getGlobal ( ) ; if ( ( Modifier && strcmp ( Modifier , <STR_LIT> ) == <NUM_LIT> ) || ( TF & <STR_LIT> ) ) O << <STR_LIT> ; else if ( ( Modifier && strcmp ( Modifier , <STR_LIT> ) == <NUM_LIT> ) || ( TF & <STR_LIT> ) ) O << <STR_LIT> ; O << * Mang -> getSymbol ( GV ) ; printOffset ( MO . getOffset ( ) ) ; if ( isCallOp && Subtarget -> isTargetELF ( ) && TM . getRelocationModel ( ) == Reloc :: PIC_ ) O << <STR_LIT> ; break ; } case MachineOperand :: MO_ExternalSymbol : { bool isCallOp = Modifier && ! strcmp ( Modifier , <STR_LIT> ) ; O << * GetExternalSymbolSymbol ( MO . getSymbolName ( ) ) ; if ( isCallOp && Subtarget -> isTargetELF ( ) && TM . getRelocationModel ( ) == Reloc :: PIC_ ) O << <STR_LIT> ; break ; } case MachineOperand ::


<s> RegisterAsmPrinter < <ISA_LIT>AsmPrinter > Y ( getThe<ISA_LIT>elTarget ( ) ) ; RegisterAsmPrinter < <ISA_LIT>AsmPrinter > A ( getThe<ISA_LIT>64Target ( )


<s> std :: vector < std :: pair < uint64_t , uint64_t >> Result ; for ( uint64_t Byte = <NUM_LIT> , End = PltContents . size ( ) ; Byte + <NUM_LIT> < End ; ) { if ( PltContents [ Byte ] == <NUM_LIT> && PltContents [ Byte + <NUM_LIT> ] == <NUM_LIT> ) { uint32_t Imm = <STR_LIT> :: read32le ( PltContents . data ( ) + Byte + <NUM_LIT> ) ; Result . push_back ( std :: make_pair ( PltSectionVA + Byte , GotPltSectionVA + Imm ) ) ; Byte += <NUM_LIT> ; } else if ( PltContents [ Byte ] == <NUM_LIT> && PltContents [ Byte + <NUM_LIT> ] == <NUM_LIT> ) { uint32_t Imm = <STR_LIT> :: read32le ( PltContents . data


<s> bool enableUnalignedScalarMem ( ) const { return


<s> case <STR_LIT> : return expandDiv ( Inst , IDLoc , Out , STI , true , false ) ? MER_Fail : MER_Success ; case <STR_LIT> : return expandTrunc ( Inst , false , false , IDLoc , Out , STI ) ? MER_Fail : MER_Success ; case <STR_LIT> : return expandTrunc ( Inst , true , false , IDLoc , Out , STI ) ? MER_Fail : MER_Success ; case <STR_LIT> : return expandTrunc ( Inst , true , true , IDLoc , Out , STI ) ? MER_Fail : MER_Success ; case <STR_LIT> : return expandUlh ( Inst , true , IDLoc , Out , STI ) ? MER_Fail : MER_Success ; case <STR_LIT> : return expandUlh ( Inst , false , IDLoc , Out , STI ) ? MER_Fail : MER_Success ; case <STR_LIT> : return expandUlw ( Inst , IDLoc , Out , STI ) ? MER_Fail : MER_Success ; case <STR_LIT> : return expandAliasImmediate ( Inst , IDLoc , Out , STI ) ? MER_Fail : MER_Success ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( ( Inst . getNumOperands ( ) == <NUM_LIT> ) && Inst . getOperand ( <NUM_LIT> ) . isReg ( ) && Inst . getOperand ( <NUM_LIT> ) . isReg ( ) && Inst . getOperand ( <NUM_LIT> ) . isImm ( ) ) { int64_t ImmValue = Inst . getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( isInt < <NUM_LIT> > ( ImmValue ) ) return MER_NotAMacro ; return expandAliasImmediate ( Inst , IDLoc , Out , STI ) ? MER_Fail : MER_Success ; } return MER_NotAMacro ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( ( Inst . getNumOperands ( ) == <NUM_LIT> ) && Inst . getOperand ( <NUM_LIT> ) . isReg ( ) && Inst . getOperand ( <NUM_LIT> ) . isReg ( ) && Inst . getOperand ( <NUM_LIT> ) . isImm ( ) ) { int64_t ImmValue = Inst . getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( isUInt < <NUM_LIT> > ( ImmValue ) ) return MER_NotAMacro ; return expandAliasImmediate ( Inst , IDLoc , Out , STI ) ? MER_Fail : MER_Success ; } return MER_NotAMacro ; case <STR_LIT> : case <STR_LIT> : return expandRotation ( Inst , IDLoc , Out , STI ) ? MER_Fail : MER_Success ; case <STR_LIT> : case


<s> unsigned <ISA_LIT>ompactRegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { return


<s> bool containsVCTP ( ) const { return llvm :: any_of ( Insts , isVCTP


<s> MCSymbolRefExpr :: VariantKind RefKind = MCSymbolRefExpr :: VK_None ; switch ( MO . getTargetFlags ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : break ; case <STR_LIT> : RefKind = MCSymbolRefExpr :: VK_TLVP ; break ; case <STR_LIT> : Expr = MCSymbolRefExpr :: Create ( Sym , MCSymbolRefExpr :: VK_TLVP , Ctx ) ; Expr = MCBinaryExpr :: CreateSub ( Expr , MCSymbolRefExpr :: Create ( MF . getPICBaseSymbol ( ) , Ctx ) , Ctx ) ; break ; case <STR_LIT> : RefKind = MCSymbolRefExpr :: VK_SECREL ; break ; case <STR_LIT> : RefKind = MCSymbolRefExpr :: VK_TLSGD ; break ; case <STR_LIT> : RefKind = MCSymbolRefExpr :: VK_TLSLD ; break ; case <STR_LIT> : RefKind = MCSymbolRefExpr :: VK_TLSLDM ; break ; case <STR_LIT> : RefKind = MCSymbolRefExpr :: VK_GOTTPOFF ; break ; case <STR_LIT> : RefKind = MCSymbolRefExpr :: VK_INDNTPOFF ; break ; case <STR_LIT> : RefKind = MCSymbolRefExpr :: VK_TPOFF ; break ; case <STR_LIT> : RefKind = MCSymbolRefExpr ::


<s> <STR_LIT> <ISA_LIT>InstrInfo :: getCompoundCandidateGroup ( const MachineInstr & MI ) const { unsigned DstReg , SrcReg , Src1Reg , Src2Reg ; switch ( MI . getOpcode ( ) ) { default : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Src1Reg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Src2Reg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( <STR_LIT> . contains ( DstReg ) && ( <STR_LIT> == DstReg || <STR_LIT> == DstReg ) && isIntRegForSubInst ( Src1Reg ) && isIntRegForSubInst ( Src2Reg ) ) return <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( <STR_LIT> . contains ( DstReg ) && ( <STR_LIT> == DstReg || <STR_LIT> == DstReg ) && isIntRegForSubInst ( SrcReg ) && MI . getOperand ( <NUM_LIT> ) . isImm ( ) && ( ( isUInt < <NUM_LIT> > ( MI . getOperand ( <NUM_LIT> ) . getImm ( ) ) ) || ( MI . getOperand ( <NUM_LIT> ) . getImm ( ) == - <NUM_LIT> ) ) ) return <STR_LIT> ; break ; case <STR_LIT> : DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( isIntRegForSubInst ( DstReg ) && isIntRegForSubInst ( SrcReg ) ) return <STR_LIT> ; break ; case <STR_LIT> : DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( isIntRegForSubInst ( DstReg ) ) return <STR_LIT> ; break ; case <STR_LIT> : DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Src1Reg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( <STR_LIT> . contains ( DstReg ) && ( <STR_LIT> == DstReg || <STR_LIT> == DstReg ) && MI . getOperand ( <NUM_LIT> ) . isImm ( ) && isIntRegForSubInst ( Src1Reg ) && ( MI . getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) ) return <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Src1Reg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( <STR_LIT> . contains ( Src1Reg ) && ( <STR_LIT> ==


<s> static bool rs6000_vector_mode_supported_p ( machine_mode mode ) { if ( TARGET_PAIRED_FLOAT && PAIRED_VECTOR_MODE ( mode ) ) return true ; else if ( VECTOR_MEM_ALTIVEC_OR_VSX_P ( mode ) && ! FLOAT128_IEEE_P


<s> TargetLowering :: ArgListEntry Entry ; Entry . Ty = DAG . getDataLayout ( ) . getIntPtrType ( * DAG . getContext ( ) ) ; Entry . Node = Dst ; Args . push_back ( Entry ) ; Entry . Node = Src ; Args . push_back ( Entry ) ; Entry . Node = Size ; Args . push_back ( Entry ) ; TargetLowering :: CallLoweringInfo CLI ( DAG ) ; CLI . setDebugLoc ( dl ) . setChain ( Chain ) . setCallee ( TLI . getLibcallCallingConv ( RTLIB :: MEMCPY ) , Type :: getVoidTy ( * DAG . getContext ( ) ) , DAG . getExternalSymbol ( <STR_LIT> , TLI . getPointerTy ( DAG . getDataLayout ( ) ) ) , std :: move ( Args ) , <NUM_LIT> ) . setDiscardResult ( ) ; std :: pair < SDValue , SDValue > CallResult = TLI . LowerCallTo ( CLI ) ; return CallResult .


<s> return DAG . getVectorShuffle ( OpVT , dl , Vec , SubVec . getOperand ( <NUM_LIT> ) , Mask ) ; } } if ( ( Vec . isUndef ( ) || Vec . getOpcode ( ) == <STR_LIT> ) && SubVec . getOpcode ( ) == <STR_LIT> ) { SDValue VecSrc = peekThroughBitcasts ( Vec ) ; SDValue SubVecSrc = peekThroughBitcasts ( SubVec ) ; MVT VecSrcSVT = VecSrc . getSimpleValueType ( ) . getScalarType ( ) ; MVT SubVecSrcSVT = SubVecSrc . getSimpleValueType ( ) . getScalarType ( ) ; if ( Vec . isUndef ( ) || VecSrcSVT == SubVecSrcSVT ) { MVT NewOpVT ; SDValue NewIdx ; unsigned NumElts = OpVT . getVectorNumElements ( ) ; unsigned EltSizeInBits = OpVT . getScalarSizeInBits ( ) ; if ( ( EltSizeInBits % SubVecSrcSVT . getSizeInBits ( ) ) == <NUM_LIT> ) { unsigned Scale = EltSizeInBits / SubVecSrcSVT . getSizeInBits ( ) ; NewOpVT = <STR_LIT> ( SubVecSrcSVT , NumElts * Scale ) ; NewIdx = DAG . getIntPtrConstant ( IdxVal * Scale , dl ) ; } else if ( ( SubVecSrcSVT . getSizeInBits ( ) % EltSizeInBits ) == <NUM_LIT> ) { unsigned Scale = SubVecSrcSVT . getSizeInBits ( ) / EltSizeInBits ; if ( ( IdxVal % Scale ) == <NUM_LIT> ) { NewOpVT = <STR_LIT> ( SubVecSrcSVT , NumElts / Scale ) ; NewIdx = DAG . getIntPtrConstant ( IdxVal / Scale , dl ) ; } } if ( NewIdx && DAG . getTargetLoweringInfo ( ) . isOperationLegal ( <STR_LIT> , NewOpVT ) ) { SDValue Res = DAG . getBitcast ( NewOpVT , VecSrc ) ; Res = DAG . getNode ( <STR_LIT> , dl , NewOpVT , Res , SubVecSrc , NewIdx ) ; return DAG . getBitcast ( OpVT , Res ) ; } } } if ( ( IdxVal == OpVT . getVectorNumElements ( ) / <NUM_LIT> ) && Vec . getOpcode ( ) == <STR_LIT> && OpVT . getSizeInBits ( ) == SubVecVT . getSizeInBits ( ) * <NUM_LIT> ) { if ( isNullConstant ( Vec . getOperand ( <NUM_LIT> ) ) ) { SDValue SubVec2 = Vec . getOperand ( <NUM_LIT> ) ; SDValue Ops [ ] = { SubVec2 , SubVec } ; if ( SDValue Fold = combineConcatVectorOps ( dl , OpVT , Ops , DAG , DCI , Subtarget ) ) return Fold ; if ( ! Vec . getOperand ( <NUM_LIT> ) . isUndef ( ) && Vec . hasOneUse ( ) ) { Vec = DAG . getNode ( <STR_LIT> , dl , OpVT , DAG . getUNDEF

( OpVT ) , SubVec2 , Vec . getOperand ( <NUM_LIT> ) ) ;


<s> static bool c6x_function_value_regno_p ( const unsigned int


<s> unsigned getMinVectorRegisterBitWidth ( )


<s> CallTargetMCOp = MCOperand :: createReg ( CallTarget . getReg ( ) ) ; CallOpcode = <STR_LIT> ; break ; default : llvm_unreachable ( <STR_LIT> ) ; break ; } EmitToStreamer ( OutStreamer , MCInstBuilder ( CallOpcode ) . addOperand ( CallTargetMCOp ) ) ; } auto & Ctx = OutStreamer . getContext ( ) ; MCSymbol * MILabel = Ctx . createTempSymbol ( ) ; OutStreamer . emitLabel ( MILabel ) ; SM . recordStatepoint ( * MILabel , MI


<s> return ( __m128i ) __builtin_ia32_cvttpd2dq128_mask ( ( __v2df ) __A , ( __v4si ) __W , (


<s> Worklist . push_back ( N -> getOperand ( <NUM_LIT> ) . getNode ( ) ) ; Worklist . push_back ( N -> getOperand ( <NUM_LIT> ) . getNode ( ) ) ; if ( N -> hasOneUse ( ) && Opcode == N -> use_begin ( ) -> getOpcode ( ) ) continue ; if ( RootWeights . count ( N ) ) continue ; RootWeights [ N ] = - <NUM_LIT> ; } RootWeights [ BasePtr . getNode ( ) ] = - <NUM_LIT> ; SDValue NewBasePtr = balanceSubTree ( BasePtr . getNode ( ) , true ) ; if ( N -> getOpcode ( ) == <STR_LIT> ) N = CurDAG -> UpdateNodeOperands ( N , N -> getOperand ( <NUM_LIT> ) , NewBasePtr , N -> getOperand ( <NUM_LIT> ) ) ; else N = CurDAG -> UpdateNodeOperands ( N , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , NewBasePtr , N -> getOperand ( <NUM_LIT> ) ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT>


<s> unsigned LaneStart = l * NumLaneElems ; for ( unsigned i = <NUM_LIT> ; i != NumLaneElems ; ++ i ) { int Idx = SVOp -> getMaskElt ( i + LaneStart ) ; if ( Idx < <NUM_LIT> ) { Mask . push_back ( - <NUM_LIT> ) ; continue ; } int Input = Idx / NumLaneElems ; Idx -= Input * NumLaneElems ; unsigned OpNo ; for ( OpNo = <NUM_LIT> ; OpNo < array_lengthof ( InputUsed ) ; ++ OpNo ) { if ( InputUsed [ OpNo ] == Input ) break ; if ( InputUsed [ OpNo ] < <NUM_LIT> ) { InputUsed [ OpNo ] = Input ; break ; } } if ( OpNo >= array_lengthof ( InputUsed ) ) { UseBuildVector = true ; break ; } Mask . push_back ( Idx + OpNo * NumLaneElems ) ; } if ( UseBuildVector ) { SmallVector < SDValue , <NUM_LIT> > SVOps ; for ( unsigned i = <NUM_LIT> ; i != NumLaneElems ; ++ i ) { int Idx = SVOp -> getMaskElt ( i + LaneStart ) ; if ( Idx < <NUM_LIT> ) { SVOps . push_back ( DAG . getUNDEF ( EltVT ) ) ; continue ; } int Input = Idx / NumElems ; Idx -= Input * NumElems ; SVOps . push_back ( DAG . getNode ( <STR_LIT> , dl , EltVT , SVOp -> getOperand ( Input ) , DAG . getIntPtrConstant ( Idx ) ) ) ; } Output [ l ] = DAG . getNode ( <STR_LIT> , dl , NVT , SVOps ) ; } else if ( InputUsed [ <NUM_LIT> ] < <NUM_LIT> ) { Output [ l ] = DAG . getUNDEF ( NVT ) ; } else { SDValue Op0 = Extract128BitVector ( SVOp -> getOperand ( InputUsed [ <NUM_LIT> ] / <NUM_LIT> ) , ( InputUsed [ <NUM_LIT> ] % <NUM_LIT> ) * NumLaneElems , DAG , dl ) ; SDValue Op1 = ( InputUsed [ <NUM_LIT> ] < <NUM_LIT> ) ? DAG . getUNDEF ( NVT ) : Extract128BitVector ( SVOp -> getOperand ( InputUsed [ <NUM_LIT> ] / <NUM_LIT> ) , ( InputUsed [ <NUM_LIT> ] % <NUM_LIT> ) * NumLaneElems , DAG , dl ) ; Output [ l ] = DAG . getVectorShuffle ( NVT , dl , Op0 , Op1 , & Mask


<s> Register <ISA_LIT>RegisterInfo :: getFrameRegister ( const MachineFunction


<s> SDValue N1 = N -> getOperand ( <NUM_LIT> ) ; unsigned BitWidth = N1 . getValueSizeInBits ( ) ; APInt DemandedMask = APInt :: getLowBitsSet ( BitWidth , Log2_32 ( BitWidth ) ) ; if ( DAG . getTargetLoweringInfo ( ) . SimplifyDemandedBits ( N1 , DemandedMask , DCI ) ) { DCI . AddToWorklist ( N ) ; return SDValue ( N , <NUM_LIT> ) ; } return SDValue (


<s> <ISA_LIT>Operand ( unsigned Reg , MCExpr const * Imm , SMLoc const & S , SMLoc const & E ) : Kind ( k_Memri ) , RegImm ( { Reg , Imm ) , Start ( S ) ,


<s> SmallVector < SDValue , <NUM_LIT> > Regs ( N -> op_begin ( ) + <NUM_LIT> , N -> op_begin ( ) + <NUM_LIT> + NumVecs ) ; SDValue RegSeq = Is128Bit ? createQTuple ( Regs ) : createDTuple ( Regs ) ; SDValue Ops [ ] = { RegSeq , N -> getOperand ( NumVecs + <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) } ; SDNode * St = CurDAG -> getMachineNode ( Opc , dl , N -> getValueType ( <NUM_LIT> ) , Ops ) ; MachineMemOperand * MemOp = cast < MemIntrinsicSDNode > ( N ) ->


<s> if ( Reg == <STR_LIT> && Reg1 == <STR_LIT> ) { Reg = <STR_LIT> ; RegWidth = <NUM_LIT> ; return true ; } if ( Reg == <STR_LIT> && Reg1 == <STR_LIT> ) { Reg = <STR_LIT> ; RegWidth = <NUM_LIT> ; return true ; } if ( Reg == <STR_LIT> && Reg1 == <STR_LIT> ) { Reg = <STR_LIT> ; RegWidth = <NUM_LIT> ; return true ; } if ( Reg == <STR_LIT> && Reg1 == <STR_LIT> ) { Reg = <STR_LIT> ; RegWidth = <NUM_LIT> ; return true ; } if ( Reg == <STR_LIT> && Reg1 == <STR_LIT> ) { Reg = <STR_LIT> ; RegWidth = <NUM_LIT> ; return true ; } if ( Reg == <STR_LIT> && Reg1 == <STR_LIT> ) { Reg = <STR_LIT> ; RegWidth = <NUM_LIT> ; return true ; } return false ; case IS_VGPR : case IS_SGPR : case IS_AGPR : case IS_TTMP : if ( Reg1 != Reg + RegWidth ) { return false ; } RegWidth ++


<s> bool <ISA_LIT>MCExpr :: evaluateAsRelocatableImpl ( MCValue & Res , const MCAsmLayout * Layout , const MCFixup * Fixup ) const { if ( Kind == VK_<ISA_LIT>_PCREL_LO && evaluatePCRelLo ( Res , Layout , Fixup ) ) return true ; if ( ! getSubExpr ( ) -> evaluateAsRelocatable ( Res , Layout , Fixup ) ) return false ; if ( Res . getSymA ( ) && Res . getSymB ( ) ) { switch ( getKind ( ) ) { default : return true ; case VK_<ISA_LIT>_LO : case VK_<ISA_LIT>_HI : case VK_<ISA_LIT>_PCREL_LO : case VK_<ISA_LIT>_PCREL_HI


<s> AttrEmitter = new AsmAttributeEmitter ( OutStreamer ) ; emitFPU = true ; } else { MCObjectStreamer & O = static_cast < MCObjectStreamer & > ( OutStreamer ) ; AttrEmitter = new ObjectAttributeEmitter ( O ) ; } AttrEmitter -> MaybeSwitchVendor ( <STR_LIT> ) ; std :: string CPUString = Subtarget -> getCPUString ( ) ; if ( CPUString == <STR_LIT> || Subtarget -> isCortexA8 ( ) ) { AttrEmitter -> EmitTextAttribute ( <STR_LIT> , <STR_LIT> ) ; AttrEmitter -> EmitAttribute ( <STR_LIT> , <STR_LIT> ) ; AttrEmitter -> EmitAttribute ( <STR_LIT> , <STR_LIT> ) ; AttrEmitter -> EmitAttribute ( <STR_LIT> , <STR_LIT> ) ; AttrEmitter -> EmitAttribute ( <STR_LIT> , <STR_LIT> ) ; } else if ( CPUString == <STR_LIT> ) { AttrEmitter -> EmitAttribute ( <STR_LIT> , <STR_LIT> ) ; AttrEmitter -> EmitAttribute ( <STR_LIT> , <STR_LIT> ) ; AttrEmitter -> EmitAttribute ( <STR_LIT> , <STR_LIT> ) ; } if ( Subtarget -> hasNEON ( ) && emitFPU


<s> Attribute A = Set . getAttribute ( AttributeSet :: FunctionIndex , <STR_LIT> ) ; unsigned ShaderType = ShaderType :: COMPUTE ; if ( A . isStringAttribute ( ) ) { StringRef Str = A . getValueAsString ( ) ; Str . getAsInteger ( <NUM_LIT>


<s> MachineInstr & MI = * II ; MachineBasicBlock & MB = * MI . getParent ( ) ; MachineFunction & MF = * MB . getParent ( ) ; auto & HST = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; auto & HII = * HST . getInstrInfo ( ) ; auto & HFI = * HST . getFrameLowering ( ) ; unsigned BP = <NUM_LIT> ; int FI = MI . getOperand ( FIOp ) . getIndex ( ) ; int Offset = HFI . getFrameIndexReference ( MF , FI , BP ) ; int RealOffset = Offset + MI . getOperand ( FIOp + <NUM_LIT> ) . getImm ( ) ; bool IsKill = false ; unsigned Opc = MI


<s> NewImm = ~ Imm ; Opc = <STR_LIT> ; } } else if ( Opc == <STR_LIT> ) { if ( isPowerOf2_32 ( Imm ) ) { NewImm = countTrailingZeros ( Imm ) ; Opc = <STR_LIT> ; } else if ( <STR_LIT> ( ~ Imm , ST . hasInv2PiInlineImm ( ) ) ) { NewImm = ~ Imm ; Opc = <STR_LIT> ; } } else if ( Opc == <STR_LIT> ) { if ( <STR_LIT> ( ~ Imm , ST . hasInv2PiInlineImm ( ) ) ) { NewImm = ~ Imm ; Opc = <STR_LIT> ; } } else { llvm_unreachable ( <STR_LIT> ) ; } if ( ( Opc == <STR_LIT> || Opc == <STR_LIT> ) && SrcImm == Src0 ) { if ( ! TII -> commuteInstruction ( MI , false , <NUM_LIT> , <NUM_LIT> ) ) NewImm = <NUM_LIT> ; } if ( NewImm != <NUM_LIT> ) { if ( Register :: isVirtualRegister ( Dest -> getReg ( ) ) && SrcReg -> isReg ( ) ) { MRI . setRegAllocationHint ( Dest -> getReg ( ) , <NUM_LIT> , SrcReg -> getReg ( ) ) ; MRI . setRegAllocationHint ( SrcReg -> getReg ( ) , <NUM_LIT> , Dest -> getReg ( ) ) ; return true ; } if ( SrcReg -> isReg ( ) && SrcReg -> getReg ( ) == Dest -> getReg ( ) ) { MI . setDesc ( TII -> get ( Opc ) ) ; if ( Opc == <STR_LIT> || Opc == <STR_LIT> ) { Src0 -> ChangeToImmediate ( NewImm ) ; MI . getOperand ( <NUM_LIT> ) . ChangeToRegister ( Dest -> getReg ( ) , false ) ; MI . tieOperands ( <NUM_LIT> , <NUM_LIT> ) ; } else { SrcImm -> setImm ( NewImm


<s> __o = __builtin_aarch64_set_qregoiv16qi ( __o , ( int8x16_t ) tab . val [ <NUM_LIT> ] , <NUM_LIT> ) ; __o = __builtin_aarch64_set_qregoiv16qi ( __o , ( int8x16_t ) tab . val [


( SImode , validize_mem ( adjust_address ( m_tramp , SImode , <NUM_LIT> ) ) ) ) ;


<s> if ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) == <STR_LIT> ) { SDValue Bits = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) ) ; SDValue FP = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Bits ) ; if ( Op . getValueType ( ) == <STR_LIT> ) FP = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , FP , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; return FP ; } assert ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) == <STR_LIT> && <STR_LIT> ) ; MachineFunction & MF = DAG . getMachineFunction ( ) ; MachineFrameInfo * FrameInfo = MF . getFrameInfo ( ) ; int FrameIdx = FrameInfo -> CreateStackObject ( <NUM_LIT> , <NUM_LIT> , false ) ; EVT PtrVT = DAG . getTargetLoweringInfo ( ) . getPointerTy ( ) ; SDValue FIdx = DAG . getFrameIndex


<s> static int tilepro_issue_rate ( void ) { return


<s> if ( TT . isOSBinFormatMachO ( ) ) { OutStreamer -> EmitAssemblerFlag ( MCAF_SubsectionsViaSymbols ) ; } emitStackMaps ( SM


<s> void <ISA_LIT>AsmPrinter :: printFU ( const MachineInstr * MI , int opNum , raw_ostream & OS ) { int fuOp = MI -> getOperand ( opNum ) . getImm ( ) ; OS << UnitStrings [ fuOp >> <NUM_LIT> ] ; OS << ( IS_BSIDE ( MI -> getDesc ( ) . TSFlags ) ? <STR_LIT> : <STR_LIT> ) ; if ( MI -> getDesc ( ) . TSFlags & <STR_LIT> ) { if ( ST . enablePostRAScheduler ( ) ) { if ( fuOp & <NUM_LIT> ) OS << <STR_LIT> ; else OS << <STR_LIT> ; } return ; } if ( fuOp & <NUM_LIT> ) OS <<


<s> static Reloc :: Model getEffectiveRelocModel ( const Triple & TT ,


<s> <ISA_LIT>AsmParser :: OperandMatchResultTy <ISA_LIT>AsmParser :: ParseOperand ( SmallVectorImpl < MCParsedAsmOperand * > & Operands , StringRef Mnemonic ) { OperandMatchResultTy ResTy = MatchOperandParserImpl ( Operands , Mnemonic ) ; if ( ResTy != MatchOperand_NoMatch ) return ResTy ; switch ( getLexer ( ) . getKind ( ) ) { default : Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ; case AsmToken :: Identifier : { OperandMatchResultTy GotShift = ParseShiftExtend ( Operands ) ; if ( GotShift != MatchOperand_NoMatch ) return GotShift ; uint32_t NumLanes = <NUM_LIT> ; OperandMatchResultTy GotReg = ParseRegister ( Operands , NumLanes ) ; assert ( GotReg != MatchOperand_ParseFail && <STR_LIT> ) ; if ( GotReg == MatchOperand_Success ) { if ( Parser . getTok ( ) . is ( AsmToken :: LBrac ) ) return ParseNEONLane ( Operands , NumLanes ) ; else return MatchOperand_Success ; } } case AsmToken :: LParen : case AsmToken :: Integer : case AsmToken :: String : case AsmToken :: Dot : case AsmToken :: Dollar : case AsmToken :: Colon : { SMLoc StartLoc = Parser . getTok ( ) . getLoc ( ) ; SMLoc EndLoc ; const MCExpr * ImmVal = <NUM_LIT> ; if ( ParseImmediate ( ImmVal ) != MatchOperand_Success ) return MatchOperand_ParseFail ; EndLoc = SMLoc :: getFromPointer ( Parser . getTok ( ) . getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateImm ( ImmVal , StartLoc , EndLoc ) ) ; return MatchOperand_Success ; } case AsmToken :: Hash : { SMLoc StartLoc = Parser . getTok ( ) . getLoc ( ) ; SMLoc EndLoc ; const MCExpr * ImmVal = <NUM_LIT> ; Parser . Lex ( ) ; if ( ParseImmediate ( ImmVal ) != MatchOperand_Success ) return MatchOperand_ParseFail ; EndLoc = SMLoc :: getFromPointer ( Parser . getTok ( ) . getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateImm ( ImmVal , StartLoc , EndLoc ) ) ; return MatchOperand_Success ; } case AsmToken :: LBrac : { SMLoc Loc = Parser . getTok ( ) . getLoc ( ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateToken ( <STR_LIT> , Loc ) ) ; Parser . Lex ( ) ; return ParseOperand ( Operands


<s> if ( ! MI . getMF ( ) -> getFunction ( ) . doesNotRecurse ( ) ) return TargetInstrInfo :: canFoldCopy ( MI , FoldIdx ) ; Register FoldReg = MI . getOperand ( FoldIdx ) . getReg ( ) ; if ( <STR_LIT> . contains ( FoldReg ) || <STR_LIT> . contains ( FoldReg ) ) return TargetInstrInfo :: canFoldCopy ( MI , FoldIdx ) ; if ( FoldReg . isVirtual ( ) ) { const auto * RC = MI . getMF ( ) -> getRegInfo ( ) .


<s> if ( Ty -> isVectorTy ( ) && AM . BaseOffs != <NUM_LIT> && ! Subtarget . hasP9Vector ( ) ) return false ; if ( AM . BaseOffs <= - ( <NUM_LIT> << <NUM_LIT> ) || AM . BaseOffs >= ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) return false ; if ( AM . BaseGV ) return false ; switch ( AM . Scale


<s> return getSubtargetImpl ( ) -> getInstrInfo (


<s> for ( uint16_t i = <NUM_LIT> ; i < W ; ++ i ) { const BitTracker :: BitValue & BV = RC [ i ] ; if ( BV . is ( <NUM_LIT> ) || BV . is ( <NUM_LIT> ) ) continue ; return false ; } return


<s> if ( ! CSD ) return false ; ShiftVal = CSD -> getZExtValue ( ) ; if ( ShiftVal > <NUM_LIT> ) return false ; Ext = getExtendTypeForNode ( N . getOperand ( <NUM_LIT> ) ) ; if ( Ext == <STR_LIT> ) return false ; Reg = N . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ; } else { Ext = getExtendTypeForNode ( N ) ; if ( Ext == <STR_LIT> ) return false ; Reg = N .


<s> unsigned Opc = IsAdd ? <STR_LIT> : <STR_LIT> ; unsigned CarryOpc = IsAdd ? <STR_LIT> : <STR_LIT> ; SDNode * AddLo ; if ( ! ConsumeCarry ) { SDValue Args [ ] = { SDValue ( Lo0 , <NUM_LIT> ) , SDValue ( Lo1 , <NUM_LIT> ) } ; AddLo = CurDAG -> getMachineNode ( Opc , DL , VTList , Args ) ; } else { SDValue Args [ ] = { SDValue ( Lo0 , <NUM_LIT> ) , SDValue ( Lo1 , <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) } ; AddLo = CurDAG -> getMachineNode ( CarryOpc , DL , VTList , Args ) ; } SDValue AddHiArgs [ ] = { SDValue ( Hi0 , <NUM_LIT> ) , SDValue ( Hi1 , <NUM_LIT> ) , SDValue ( AddLo , <NUM_LIT> ) } ; SDNode * AddHi = CurDAG -> getMachineNode ( CarryOpc , DL , VTList ,


<s> } const StackOffset & SVEStackSize = getSVEStackSize ( MF ) ; if ( CombineSPBump ) { assert ( ! SVEStackSize && <STR_LIT> ) ; emitFrameOffset ( MBB , MBB . getFirstTerminator ( ) , DL , <STR_LIT> , <STR_LIT> , { NumBytes + ( int64_t ) AfterCSRPopSize , <STR_LIT> } , TII , MachineInstr :: FrameDestroy , false , NeedsWinCFI , & HasWinCFI ) ; if ( NeedsWinCFI && HasWinCFI ) BuildMI ( MBB , MBB . getFirstTerminator ( ) , DL , TII -> get ( <STR_LIT> ) ) . setMIFlag ( MachineInstr :: FrameDestroy ) ; return ; } NumBytes -= PrologueSaveSize ; assert ( NumBytes >= <NUM_LIT> && <STR_LIT> ) ; StackOffset DeallocateBefore = { } , DeallocateAfter = SVEStackSize ; MachineBasicBlock :: iterator RestoreBegin = LastPopI , RestoreEnd = LastPopI ; if ( AFI -> getSVECalleeSavedStackSize ( ) ) { RestoreBegin = std :: prev ( RestoreEnd ) ; ; while ( IsSVECalleeSave ( RestoreBegin ) && RestoreBegin != MBB . begin ( ) ) -- RestoreBegin ; ++ RestoreBegin ; assert ( IsSVECalleeSave ( RestoreBegin ) && IsSVECalleeSave ( std :: prev ( RestoreEnd ) ) && <STR_LIT> ) ; int64_t OffsetToFirstCalleeSaveFromSP = MFI . getObjectOffset ( AFI -> getMaxSVECSFrameIndex ( ) ) ; StackOffset OffsetToCalleeSavesFromSP = StackOffset ( OffsetToFirstCalleeSaveFromSP , <STR_LIT> ) + SVEStackSize ; DeallocateBefore = OffsetToCalleeSavesFromSP ; DeallocateAfter = SVEStackSize - DeallocateBefore ; } if ( SVEStackSize ) { if ( AFI -> isStackRealigned ( ) ) { if ( AFI -> getSVECalleeSavedStackSize ( ) ) emitFrameOffset ( MBB , RestoreBegin , DL , <STR_LIT> , <STR_LIT> , - SVEStackSize , TII , MachineInstr :: FrameDestroy ) ; } else { if ( AFI -> getSVECalleeSavedStackSize ( ) ) { emitFrameOffset ( MBB , RestoreBegin , DL , <STR_LIT> , <STR_LIT> , { NumBytes , <STR_LIT> } , TII , MachineInstr :: FrameDestroy ) ; NumBytes = <NUM_LIT> ; } emitFrameOffset ( MBB , RestoreBegin , DL , <STR_LIT> , <STR_LIT> , DeallocateBefore , TII , MachineInstr :: FrameDestroy ) ; emitFrameOffset ( MBB , RestoreEnd , DL , <STR_LIT> , <STR_LIT> , DeallocateAfter , TII , MachineInstr :: FrameDestroy ) ; } } if ( ! hasFP ( MF ) ) { bool RedZone = canUseRedZone ( MF ) ; if ( RedZone && AfterCSRPopSize == <NUM_LIT> ) return ; bool NoCalleeSaveRestore = PrologueSaveSize == <NUM_LIT> ; int64_t StackRestoreBytes = RedZone ? <NUM_LIT> : NumBytes ; if ( NoCalleeSaveRestore ) StackRestoreBytes += AfterCSRPopSize ; bool Done = NoCalleeSaveRestore || AfterCSRPopSize == <NUM_LIT> ; if ( Done ) adaptForLdStOpt ( MBB , MBB . getFirstTerminator ( ) , LastPopI ) ; emitFrameOffset ( MBB , LastPopI , DL , <STR_LIT> , <STR_LIT> , { StackRestoreBytes , <STR_LIT> } , TII , MachineInstr :: FrameDestroy , false , NeedsWinCFI , & HasWinCFI ) ; if ( Done )


<s> emitRRR ( Is64Bit ? <STR_LIT> : <STR_LIT> , DstReg , SrcReg , TrgReg , SMLoc ( )


<s> bool Use32BitInsts = isUInt < <NUM_LIT> > ( Mask ) ; unsigned ANDIMask = ( Mask & UINT16_MAX ) , ANDISMask = ( Mask >> <NUM_LIT> ) & UINT16_MAX ; if ( Use32BitInsts ) { assert ( ( ANDIMask != <NUM_LIT> || ANDISMask != <NUM_LIT> ) && <STR_LIT> ) ; if ( InstCnt ) * InstCnt += ( unsigned ) ( ANDIMask != <NUM_LIT> ) + ( unsigned ) ( ANDISMask != <NUM_LIT> ) + ( unsigned ) ( ANDIMask != <NUM_LIT> && ANDISMask != <NUM_LIT> ) ; SDValue ANDIVal , ANDISVal ; if ( ANDIMask != <NUM_LIT> ) ANDIVal = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , ExtendToInt64 ( Res , dl ) , getI32Imm ( ANDIMask , dl ) ) , <NUM_LIT> ) ; if ( ANDISMask != <NUM_LIT> ) ANDISVal = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , ExtendToInt64 ( Res , dl ) , getI32Imm ( ANDISMask , dl ) ) , <NUM_LIT> ) ; if ( ! ANDIVal ) Res = ANDISVal ; else if ( ! ANDISVal ) Res = ANDIVal ; else Res = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , ExtendToInt64 ( ANDIVal , dl ) , ANDISVal ) , <NUM_LIT> ) ; } else { if ( InstCnt ) * InstCnt += selectI64ImmInstrCount ( Mask ) + <NUM_LIT> ; SDValue MaskVal = SDValue ( selectI64Imm ( CurDAG , dl , Mask ) , <NUM_LIT> ) ; Res = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , ExtendToInt64 ( Res , dl )


<s> SDNode * Copy = * N -> use_begin ( ) ; if ( Copy -> getOpcode ( ) == <STR_LIT> ) { if ( Copy -> getOperand ( Copy -> getNumOperands ( ) - <NUM_LIT> ) . getValueType ( ) == <STR_LIT> ) return false ; TCChain = Copy -> getOperand ( <NUM_LIT> ) ; } else if ( Copy -> getOpcode ( ) != <STR_LIT> ) return false ; bool HasRet = false ; for ( SDNode * Node : Copy -> uses ( ) ) { if ( Node -> getOpcode ( )


<s> auto Tag = CTy -> getTag ( ) ; if ( Tag != dwarf :: DW_TAG_structure_type || CTy -> isForwardDecl ( ) ) return ; const DINodeArray Elements = CTy -> getElements ( ) ; for ( const auto * Element : Elements ) { const auto * MemberType = cast < DIDerivedType > ( Element ) ; visitTypeEntry ( MemberType -> getBaseType ( ) ) ; } visitTypeEntry ( OrigTy , TypeId , false ,


<s> for ( auto * I : Incomings ) { User * Store = createTileStore ( I , I8Ptr ) ; for ( Use & U : I -> uses ( ) ) { User * V = U . getUser ( ) ; if ( isa < PHINode > ( V ) || V == Store ) continue ; replaceWithTileLoad ( U ,


<s> MF . setHasWinCFI ( false ) ; const Function & F = MF . getFunction ( ) ; if ( ! STI . is64Bit ( ) || ! MF . hasEHFunclets ( ) || classifyEHPersonality ( F . getPersonalityFn ( ) ) != EHPersonality :: MSVC_CXX ) return ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; WinEHFuncInfo & EHInfo = * MF . getWinEHFuncInfo ( ) ; int64_t MinFixedObjOffset = - SlotSize ; for ( int I = MFI . getObjectIndexBegin ( ) ; I < <NUM_LIT> ; ++ I ) MinFixedObjOffset = std :: min ( MinFixedObjOffset , MFI . getObjectOffset ( I ) ) ; for ( WinEHTryBlockMapEntry & TBME


<s> bool isRegNumber ( ) const { return Kind == Immediate && isUInt < <NUM_LIT> > ( getImm


<s> return SignExtend < <NUM_LIT> , u32 > (


<s> if ( TARGET_WINDOWED_ABI ) emit_library_call ( gen_rtx_SYMBOL_REF ( Pmode , <STR_LIT>

) , LCT_NORMAL , VOIDmode , <NUM_LIT> ) ;


<s> unsigned NumInstr = <NUM_LIT> ; const MachineFunction * MF = From . getParent ( ) ; for ( MachineFunction :: const_iterator MBBI ( & From ) , ToI ( & To ) , End = MF -> end ( ) ; MBBI != End && MBBI != ToI ; ++ MBBI ) { const MachineBasicBlock & MBB = * MBBI ; for ( MachineBasicBlock :: const_iterator I = MBB . begin ( ) , E = MBB . end ( ) ; NumInstr < SkipThreshold && I != E ; ++ I ) { if ( opcodeEmitsNoInsts ( I -> getOpcode ( ) ) ) continue ; if ( I -> getOpcode ( ) == <STR_LIT> || I -> getOpcode ( ) == <STR_LIT> ) return true ; if ( ( I -> getOpcode ( ) == <STR_LIT> ) || ( I -> getOpcode ( ) == <STR_LIT> ) ) { return true ; } if ( I -> isInlineAsm ( ) ) { const MCAsmInfo * MAI = MF -> getTarget (