<s> PointerType * PtrTy = dyn_cast < PointerType > ( ParamTy ) ; if ( PtrTy && PtrTy -> getAddressSpace ( ) == <ISA_LIT>AS :: LOCAL_ADDRESS ) { LocalMemLimit = <NUM_LIT> ; DEBUG ( dbgs ( ) << <STR_LIT> <STR_LIT> ) ; return false ; } } LocalMemLimit = ST . getLocalMemorySize ( ) ; if ( LocalMemLimit == <NUM_LIT> ) return false ; const DataLayout & DL = Mod -> getDataLayout ( ) ; CurrentLocalMemUsage = <NUM_LIT> ; for ( GlobalVariable & GV : Mod -> globals ( ) ) { if ( GV . getType ( ) -> getAddressSpace ( ) != <ISA_LIT>AS :: LOCAL_ADDRESS ) continue ; for ( const User * U : GV . users ( ) ) { const Instruction * Use = dyn_cast < Instruction > ( U ) ; if ( ! Use ) continue ; if ( Use -> getParent ( ) -> getParent ( ) == & F ) { unsigned Align = GV . getAlignment ( ) ; if ( Align == <NUM_LIT> ) Align = DL . getABITypeAlignment ( GV . getValueType ( ) ) ; uint64_t AllocSize = DL . getTypeAllocSize ( GV . getValueType ( ) ) ; CurrentLocalMemUsage = alignTo ( CurrentLocalMemUsage , Align ) ; CurrentLocalMemUsage += AllocSize ; break ; } } } unsigned MaxOccupancy = ST . getOccupancyWithLocalMemSize ( CurrentLocalMemUsage ) ; unsigned OccupancyHint = <STR_LIT> ( F , <STR_LIT> , <NUM_LIT> ) ; if ( OccupancyHint == <NUM_LIT> ) OccupancyHint = <NUM_LIT> ; OccupancyHint = std :: min ( OccupancyHint , ST . getMaxWavesPerCU ( ) ) ; MaxOccupancy = std :: min ( OccupancyHint


<s> void <ISA_LIT>RegisterInfo :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { if ( ! hasReservedCallFrame ( MF ) ) { MachineInstr * Old = I ; uint64_t Amount = Old -> getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( Amount != <NUM_LIT> ) { Amount = ( Amount + StackAlign - <NUM_LIT> ) / StackAlign * StackAlign ; MachineInstr * New = <NUM_LIT> ; if ( Old -> getOpcode ( ) == getCallFrameSetupOpcode ( ) ) { New = BuildMI ( MF , Old -> getDebugLoc ( ) , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( Amount ) ; } else { assert ( Old -> getOpcode ( ) == getCallFrameDestroyOpcode ( ) ) ; uint64_t CalleeAmt = Old -> getOperand ( <NUM_LIT> ) . getImm (


<s> Value * <ISA_LIT>IREmitter :: visitBR_JT ( const SDNode * N ) { llvm_unreachable ( <STR_LIT> ) ; return


<s> for ( auto * BB : MBB -> successors ( ) )

if ( BB -> isLiveIn ( <STR_LIT> ) ) return true ;


<s> if ( frame_off != <NUM_LIT> ) return emit_insn ( gen_add3_insn ( updt_reg_rtx , frame_reg_rtx , GEN_INT ( frame_off ) ) ) ; else if ( REGNO ( frame_reg_rtx ) != updt_regno ) return emit_move_insn ( updt_reg_rtx


<s> SDValue <ISA_LIT>TargetLowering :: LowerGlobalAddress ( SDValue Op , SelectionDAG & DAG ) { const GlobalValue * GV = cast < GlobalAddressSDNode


<s> assert ( Subtarget . hasStdExtZbkb ( ) && <STR_LIT> ) ; SDValue Src = N -> getOperand ( <NUM_LIT> ) ; if ( Src . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( ! VT . isScalarInteger ( ) || VT . getSizeInBits ( ) >= Subtarget . getXLen ( ) || ! isPowerOf2_32 ( VT . getSizeInBits ( ) ) ) return SDValue ( ) ; SDLoc DL ( N


<s> void <ISA_LIT>_32Relocator :: convertTLSIEtoLE ( Relocation & pReloc , LDSection & pSection ) { assert ( pReloc . type ( ) == llvm :: ELF :: R_386_TLS_IE ) ; assert ( pReloc . targetRef ( ) . frag ( ) != NULL ) ; Relocation * reloc = Relocation :: Create ( <ISA_LIT>_32Relocator :: R_386_TLS_OPT , * FragmentRef :: Create ( * pReloc . targetRef ( ) . frag ( ) , pReloc . targetRef ( ) . offset ( ) - <NUM_LIT> ) , <NUM_LIT> ) ; reloc -> setSymInfo ( pReloc . symInfo ( ) ) ; uint8_t * op = ( reinterpret_cast < uint8_t * > ( & reloc -> target ( ) ) ) ; if ( op [ <NUM_LIT> ] == <NUM_LIT> ) { op [ <NUM_LIT> ] = <NUM_LIT> ; } else { reloc = Relocation :: Create ( <ISA_LIT>_32Relocator :: R_386_TLS_OPT , * FragmentRef :: Create ( * pReloc . targetRef ( ) . frag ( ) , pReloc . targetRef ( ) . offset ( ) - <NUM_LIT> ) , <NUM_LIT> ) ; reloc -> setSymInfo ( pReloc . symInfo ( ) ) ; op = ( reinterpret_cast < uint8_t * > ( & reloc -> target ( ) ) ) ; switch ( op [ <NUM_LIT> ] ) { case <NUM_LIT> : assert ( ( op [ <NUM_LIT> ] & <NUM_LIT> ) == <NUM_LIT> ) ; op [ <NUM_LIT> ] = <NUM_LIT> ; op [ <NUM_LIT> ] = <NUM_LIT> | ( ( op [ <NUM_LIT> ] >> <NUM_LIT> ) & <NUM_LIT> ) ; break ; case <NUM_LIT> : assert ( ( op [ <NUM_LIT> ] & <NUM_LIT> )


<s> bool <ISA_LIT>FrameLowering :: hasFP ( const MachineFunction & MF ) const { return


<s> <ISA_LIT>_32GNULDBackend :: ~ <ISA_LIT>_32GNULDBackend (


<s> gcc_assert ( id < AVR_BUILTIN_COUNT ) ; switch ( id ) { case AVR_BUILTIN_NOP : emit_insn ( gen_nopv ( GEN_INT ( <NUM_LIT> ) ) ) ; return <NUM_LIT> ; case AVR_BUILTIN_DELAY_CYCLES : { arg0 = CALL_EXPR_ARG ( exp , <NUM_LIT> ) ; op0 = expand_expr ( arg0 , NULL_RTX , VOIDmode , EXPAND_NORMAL ) ; if ( ! CONST_INT_P ( op0 ) ) error ( <STR_LIT> , bname ) ; else avr_expand_delay_cycles ( op0 ) ; return NULL_RTX ; } case AVR_BUILTIN_NOPS : { arg0 = CALL_EXPR_ARG ( exp , <NUM_LIT> ) ; op0 = expand_expr ( arg0 , NULL_RTX , VOIDmode , EXPAND_NORMAL ) ; if ( ! CONST_INT_P ( op0 ) ) error ( <STR_LIT> , bname ) ; else avr_expand_nops ( op0 ) ; return NULL_RTX ; } case AVR_BUILTIN_INSERT_BITS : { arg0 = CALL_EXPR_ARG ( exp , <NUM_LIT> ) ; op0 = expand_expr ( arg0 , NULL_RTX , VOIDmode , EXPAND_NORMAL ) ; if ( ! CONST_INT_P ( op0 ) ) { error ( <STR_LIT> <STR_LIT> , bname ) ; return target ; } break ; } case AVR_BUILTIN_ROUNDHR : case AVR_BUILTIN_ROUNDUHR : case AVR_BUILTIN_ROUNDR :


<s> if ( fn_level <= GOMP_DIM_VECTOR && fn_level >= - <NUM_LIT> && dims [ GOMP_DIM_VECTOR ] >= <NUM_LIT> && dims [ GOMP_DIM_VECTOR ] != PTX_VECTOR_LENGTH ) { if ( fn_level < <NUM_LIT> && dims [ GOMP_DIM_VECTOR ] >= <NUM_LIT> ) warning_at ( decl ? DECL_SOURCE_LOCATION ( decl ) : UNKNOWN_LOCATION , <NUM_LIT> , dims [ GOMP_DIM_VECTOR ] ? G_ ( <STR_LIT> ) : G_ ( <STR_LIT> ) , PTX_VECTOR_LENGTH , dims [ GOMP_DIM_VECTOR ] ) ; dims [ GOMP_DIM_VECTOR ] = PTX_VECTOR_LENGTH ; changed = true ; } if ( dims [ GOMP_DIM_WORKER ] > PTX_WORKER_LENGTH ) { warning_at ( decl ? DECL_SOURCE_LOCATION ( decl ) : UNKNOWN_LOCATION , <NUM_LIT> , <STR_LIT>

, PTX_WORKER_LENGTH , dims [ GOMP_DIM_WORKER ] ) ;


<s> else if ( Inst -> isFullCopy ( ) ) NextReg = Inst -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( NextReg == SrcReg || ! Register :: isVirtualRegister ( NextReg ) ) break ; SrcReg = NextReg ; } return SrcReg


<s> std :: vector < MachineInstr * > ToRemove ; int64_t DMBType = - <NUM_LIT> ; for ( auto & MBB : MF ) { bool IsRemovableNextDMB = false ; for ( auto & MI : MBB ) { if ( MI . getOpcode ( ) == <STR_LIT> ) { if ( IsRemovableNextDMB ) { if ( MI . getOperand ( <NUM_LIT> ) . getImm ( ) == DMBType ) { ToRemove . push_back ( & MI ) ; } else { DMBType = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; } } else


<s> const MCOperand & Op = MI -> getOperand ( OpNo ) ; if ( Size == <NUM_LIT> ) O << <STR_LIT> << formatImm ( ( signed char ) Op . getImm ( ) ) ; else if ( Size == <NUM_LIT> ) O << <STR_LIT> << formatImm ( ( signed short ) Op . getImm ( ) ) ; else O << <STR_LIT> << formatImm ( Op . getImm ( )


<s> if ( ST . hasAddNoCarry ( ) ) return BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) ; Register UnusedCarry = RS . scavengeRegister ( RI . getBoolRC


<s> if ( I == MBB . end ( ) || I -> getOpcode ( ) != EndbrOpcode ) { BuildMI ( MBB , I , MBB . findDebugLoc ( I )


<s> if ( ! Subtarget -> isTargetDarwin ( ) ) return CC_<ISA_LIT>_AAPCS ; return IsVarArg ? CC_<ISA_LIT>_DarwinPCS_VarArg : CC_<ISA_LIT>_DarwinPCS ; case CallingConv :: Win64 : return IsVarArg ? CC_<ISA_LIT>_Win64_VarArg : CC_<ISA_LIT>_AAPCS ; case CallingConv :: Mono : if ( Subtarget -> isTargetDarwin ( ) ) return CC_<ISA_LIT>_Mono_DarwinPCS ; else if ( Subtarget -> isTargetWindows ( ) ) report_fatal_error ( <STR_LIT> ) ; else return


<s> SDValue callFunction ( SelectionDAG & DAG , SDLoc dl , SDValue Chain , const char * fnName , SDValue Dst , SDValue Src , SDValue Size ) { auto & Ctx = * DAG . getContext ( ) ; auto & STI = get<ISA_LIT>Subtarget ( DAG ) ; TargetLowering :: ArgListTy Args ; auto pushArg = [ & ] ( SDValue & Op ) { TargetLowering :: ArgListEntry Entry ; Entry . Node = Op ; Entry . Ty = Op . getValueType ( ) . getTypeForEVT ( Ctx ) ; Args . push_back (


<s> int Count = <NUM_LIT> ; for ( MachineBasicBlock :: iterator E = MBB -> end ( ) ; NextI != E && Count < kScanLimit ; ++ NextI ) { MachineInstr & MI = * NextI ; bool ZeroData ; int64_t Size , Offset ; if ( isMergeableStackTaggingInstruction ( MI , Offset , Size , ZeroData ) ) { if ( ZeroData != FirstZeroData ) break ; Instrs . emplace_back ( & MI , Offset , Size ) ; continue ; } if ( ! MI . isTransient ( ) ) ++ Count ; if ( MI . getFlag ( MachineInstr :: FrameSetup ) || MI . getFlag ( MachineInstr :: FrameDestroy ) ) break ; if ( MI . mayLoadOrStore ( ) || MI . hasUnmodeledSideEffects ( ) ) break ; } MachineBasicBlock :: iterator InsertI = Instrs . back ( ) . MI ; InsertI ++ ; llvm :: stable_sort ( Instrs , [ ] ( const TagStoreInstr & Left , const TagStoreInstr & Right ) { return Left . Offset < Right . Offset ; } ) ; int64_t CurOffset = Instrs [ <NUM_LIT> ] . Offset ; for ( auto & Instr : Instrs ) { if ( CurOffset > Instr . Offset ) return NextI ; CurOffset = Instr . Offset + Instr . Size ; } TagStoreEdit TSE ( MBB , FirstZeroData ) ; Optional < int64_t > EndOffset ; for ( auto & Instr : Instrs ) { if ( EndOffset && * EndOffset != Instr . Offset ) { TSE . emitCode ( InsertI , TFI , false ) ; TSE . clear ( ) ; } TSE . addInstruction ( Instr ) ; EndOffset = Instr . Offset


<s> if ( ! CE ) return true ; int64_t Value = CE -> getValue ( ) ; return Value >= <NUM_LIT> &&


<s> MCObjectWriter * llvm :: create<ISA_LIT>MachObjectWriter ( raw_ostream & OS , bool Is64Bit , uint32_t CPUType , uint32_t CPUSubtype ) { return createMachObjectWriter ( new <ISA_LIT>MachObjectWriter ( Is64Bit , CPUType ,


<s> if ( kind == scalar_stmt && aarch64_extending_load_p ( vinfo , stmt_info ) ) return <NUM_LIT> ; return stmt_cost


<s> SDValue NewPtr = DAG . getNode ( <STR_LIT> , Op . getDebugLoc ( ) , PtrType , Ptr , DAG . getConstant ( <NUM_LIT> , PtrType ) ) ; RetVal2 = DAG . getLoad ( <STR_LIT> , Op . getDebugLoc ( ) , Ld -> getChain ( ) , NewPtr , Ld -> getPointerInfo ( ) . getWithOffset ( <NUM_LIT> ) , Ld -> isVolatile ( ) , Ld ->


<s> bool isUImm12 ( ) const { return isUImm < <NUM_LIT> > (


<s> bool <ISA_LIT>BSel :: runOnMachineFunction ( MachineFunction & Fn ) { const <ISA_LIT>InstrInfo * TII = static_cast < const <ISA_LIT>InstrInfo * > ( Fn . getSubtarget ( ) . getInstrInfo ( ) ) ; Fn . RenumberBlocks ( ) ; BlockSizes . resize ( Fn . getNumBlockIDs ( ) ) ; unsigned FuncSize = <NUM_LIT> ; for ( MachineFunction :: iterator MFI = Fn . begin ( ) , E = Fn . end ( ) ; MFI != E ; ++ MFI ) { MachineBasicBlock * MBB = MFI ; unsigned BlockSize = <NUM_LIT> ; for ( MachineBasicBlock :: iterator MBBI = MBB -> begin ( ) , EE = MBB -> end ( ) ; MBBI != EE ; ++ MBBI ) BlockSize += TII -> GetInstSizeInBytes ( MBBI ) ; BlockSizes [ MBB -> getNumber ( ) ] = BlockSize ; FuncSize += BlockSize ; } if ( FuncSize < ( <NUM_LIT> << <NUM_LIT> ) ) { BlockSizes . clear ( ) ; return false ; } bool MadeChange = true ; bool EverMadeChange = false ; while ( MadeChange ) { MadeChange = false ; for ( MachineFunction :: iterator MFI = Fn . begin ( ) , E = Fn . end ( ) ; MFI != E ; ++ MFI ) { MachineBasicBlock & MBB = * MFI ; unsigned MBBStartOffset = <NUM_LIT> ; for ( MachineBasicBlock :: iterator I = MBB . begin ( ) , E = MBB . end ( ) ; I != E ; ++ I ) { if ( ( I -> getOpcode ( ) != <STR_LIT> || I -> getOperand ( <NUM_LIT> ) . isImm ( ) ) && I -> getOpcode ( ) != <STR_LIT> ) { MBBStartOffset += TII -> GetInstSizeInBytes ( I ) ; continue ; } MachineBasicBlock * Dest = I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; int BranchSize ; if ( Dest -> getNumber ( ) <= MBB . getNumber ( ) ) { BranchSize = MBBStartOffset ; for ( unsigned i = Dest -> getNumber ( ) , e = MBB . getNumber ( ) ; i != e ; ++ i ) BranchSize += BlockSizes [ i ] ; } else { BranchSize = - MBBStartOffset


<s> return create ( VK_<ISA_LIT>_HA , Expr ,


<s> Inst . addOperand ( MCOperand :: CreateImm ( <NUM_LIT> - Imm ) ) ; return


<s> bool <ISA_LIT>FastISel :: <ISA_LIT>SelectLoad ( const Instruction * I ) { if ( cast < LoadInst > ( I ) -> isAtomic ( ) ) return false ; MVT VT ; if ( ! isTypeLegal ( I -> getType ( ) , VT , true ) ) return false ; <ISA_LIT>AddressMode AM ; if ( ! <ISA_LIT>SelectAddress ( I -> getOperand ( <NUM_LIT> )


<s> SDValue Index = Op . getOperand ( <NUM_LIT> ) ; if ( isa < ConstantSDNode > ( Index ) || Vector . getOpcode ( ) == <STR_LIT> ) return Op ; Vector = vectorToVerticalVector ( DAG ,


<s> CurDAG -> SelectNodeTo ( N , <STR_LIT> , <STR_LIT> , Ops ) ; return true ; } if ( Imm == <NUM_LIT> ) { ReplaceUses ( SDValue ( N , <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) ) ; return true ; } if ( N -> getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> && isInt32Immediate ( N -> getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) , Imm2 ) ) { unsigned MB , ME ; if ( isRunOfOnes ( ~ ( Imm ^ Imm2 ) , MB , ME ) && ! ( ~ Imm & Imm2 ) ) { SDValue Ops [ ] = { N -> getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) , getI32Imm ( <NUM_LIT> , dl ) , getI32Imm ( MB , dl ) , getI32Imm ( ME , dl ) } ; ReplaceNode ( N , CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , Ops ) ) ; return true ; } } } else if ( isInt64Immediate ( N -> getOperand ( <NUM_LIT> ) . getNode ( ) , Imm64 ) ) { if ( isMask_64 ( Imm64 ) ) { MB = <NUM_LIT> - countTrailingOnes ( Imm64 ) ; SH = <NUM_LIT> ; if ( Val . getOpcode ( ) == <STR_LIT> ) { auto Op0 = Val . getOperand ( <NUM_LIT> ) ; if ( Op0 . getOpcode ( ) == <STR_LIT> && isInt32Immediate ( Op0 . getOperand ( <NUM_LIT> )


<s> setAction ( { G_PHI , s64 } , Legal ) ; for ( unsigned BinOp : { G_ADD , G_SUB , G_MUL , G_AND , G_OR , G_XOR } ) setAction ( { BinOp , s64 } , Legal ) ; for ( unsigned MemOp : { G_LOAD , G_STORE } ) setAction ( { MemOp , s64 } , Legal ) ; setAction ( { G_GEP , <NUM_LIT> , s64 } , Legal ) ; getActionDefinitionsBuilder ( G_PTRTOINT ) . legalForCartesianProduct ( { s1 , s8 , s16 , s32 , s64 } , { p0 } ) . maxScalar ( <NUM_LIT> , s64 ) . widenScalarToNextPow2 ( <NUM_LIT> , <NUM_LIT> ) ; getActionDefinitionsBuilder ( G_INTTOPTR ) . legalFor ( { { p0 , s64 } } ) ; setAction ( { TargetOpcode :: G_CONSTANT , s64 } , Legal ) ; for ( unsigned extOp : { G_ZEXT , G_SEXT , G_ANYEXT }


<s> unsigned getNumFixupKinds ( ) const override { return


<s> Instruction * <ISA_LIT>PromoteConstant :: findInsertionPoint ( Instruction & User , unsigned OpNo ) { if ( PHINode * PhiInst = dyn_cast < PHINode > ( & User ) )

return PhiInst -> getIncomingBlock ( OpNo ) -> getTerminator ( ) ;


<s> if ( MCID . mayStore ( ) ) Flags |= MachineMemOperand :: MOStore ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( MF , FI , Offset ) , Flags , MFI . getObjectSize ( FI ) , MFI . getObjectAlign ( FI ) ) ; return addOffset ( MIB . addFrameIndex ( FI ) , Offset )


<s> return ( uint16x4_t ) __builtin_neon_vshrn_nv4si ( (


<s> const MCOperand & MO = MI . getOperand ( OpNo ) ; if ( MO . isReg ( ) ) return getMachineOpValue ( MI , MO , Fixups ) ; Fixups . push_back ( MCFixup :: Create ( <NUM_LIT> , MO . getExpr (


<s> if ( stack_limit_rtx && TARGET_FDPIC ) { warning ( <NUM_LIT> , <STR_LIT> ) ; stack_limit_rtx = NULL_RTX ; } if ( stack_limit_rtx && TARGET_STACK_CHECK_L1 ) error ( <STR_LIT> ) ; if ( TARGET_ID_SHARED_LIBRARY && TARGET_FDPIC ) error ( <STR_LIT> ) ; if ( TARGET_SEP_DATA && TARGET_ID_SHARED_LIBRARY ) error ( <STR_LIT> ) ; if ( TARGET_SEP_DATA ) target_flags |= MASK_ID_SHARED_LIBRARY | MASK_LEAF_ID_SHARED_LIBRARY ; if ( TARGET_ID_SHARED_LIBRARY && flag_pic == <NUM_LIT> ) flag_pic = <NUM_LIT> ; if ( TARGET_FDPIC ) targetm . asm_out . unaligned_op . si = <NUM_LIT> ; if ( flag_pic && ! TARGET_FDPIC && ! TARGET_ID_SHARED_LIBRARY ) flag_pic = <NUM_LIT> ; if ( TARGET_MULTICORE && bfin_cpu_type != BFIN_CPU_BF561 ) error ( <STR_LIT> ) ; if ( TARGET_COREA && ! TARGET_MULTICORE ) error ( <STR_LIT> ) ; if ( TARGET_COREB && ! TARGET_MULTICORE ) error ( <STR_LIT> ) ; if ( TARGET_COREA && TARGET_COREB ) error ( <STR_LIT> ) ; flag_schedule_insns =


<s> bool <ISA_LIT>ConditionOptimizer :: adjustTo ( MachineInstr * CmpMI , <STR_LIT> Cmp , MachineInstr * To , int ToImm ) { CmpInfo Info = adjustCmp ( CmpMI , Cmp ) ; if ( std :: get < <NUM_LIT> > ( Info ) == ToImm && std :: get < <NUM_LIT> > ( Info ) == To -> getOpcode ( ) ) { modifyCmp ( CmpMI , Info ) ; return


<s> <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; const SmallVector < std :: pair < MachineOperand * , int64_t > , <NUM_LIT> > Srcs = TII -> getSrcs ( MI ) ; for ( const auto & Src : Srcs ) { if ( Src . first -> getReg ( ) != <STR_LIT> ) continue ; int64_t Imm = Src . second ; std :: vector < MachineOperand * > :: iterator It = std :: find_if ( Lits . begin ( ) , Lits . end ( ) , [ & ] ( MachineOperand * val ) { return val -> isImm ( ) && ( val -> getImm ( ) == Imm ) ; } ) ; MachineOperand & Operand = MI . getOperand ( TII -> getOperandIdx ( MI . getOpcode ( ) , <STR_LIT> :: literal ) ) ; if ( It != Lits . end ( ) ) { unsigned Index = It - Lits . begin ( ) ; Src . first -> setReg ( LiteralRegs [ Index ] ) ; } else { assert ( Lits . size ( ) < <NUM_LIT> && <STR_LIT> ) ; Src . first -> setReg ( LiteralRegs [ Lits . size ( ) ] ) ; Lits . push_back ( & Operand


<s> MVT VT = A . getSimpleValueType ( ) ; int NumElts = VT . getVectorNumElements ( ) ; SmallVector < SDValue , <NUM_LIT> > Pool ; SDValue Cst = Constant ( sh , VT


<s> RegisterMCAsmInfoFn C ( * T , create<ISA_LIT>MCAsmInfo ) ; TargetRegistry :: RegisterMCInstrInfo ( * T , create<ISA_LIT>MCInstrInfo ) ; TargetRegistry :: RegisterMCRegInfo ( * T , create<ISA_LIT>MCRegisterInfo ) ; TargetRegistry :: RegisterMCSubtargetInfo ( * T , create<ISA_LIT>MCSubtargetInfo ) ; TargetRegistry :: RegisterMCCodeEmitter ( * T , create<ISA_LIT>MCCodeEmitter ) ; TargetRegistry :: RegisterMCAsmBackend ( * T


<s> call_used_regs [ PIC_OFFSET_TABLE_REGNUM ] = <NUM_LIT> ; } if ( TARGET_FDPIC ) { fixed_regs [ PIC_REG ] = <NUM_LIT> ; call_used_regs [ PIC_REG ] = <NUM_LIT> ; call_really_used_regs [ PIC_REG ] = <NUM_LIT> ; } if ( TARGET_HITACHI && ! TARGET_NOMACSAVE ) { call_really_used_regs [ MACH_REG ] = <NUM_LIT> ; call_really_used_regs [ MACL_REG ] = <NUM_LIT> ; } if ( TARGET_SHMEDIA ) { for ( regno = FIRST_TARGET_REG ; regno <= LAST_TARGET_REG ; regno ++ ) if ( ! fixed_regs [ regno ] && call_really_used_regs [ regno ] ) SET_HARD_REG_BIT ( reg_class_contents [ SIBCALL_REGS ] , regno ) ; } else for ( regno = FIRST_GENERAL_REG ; regno <= LAST_GENERAL_REG ; regno ++ ) if ( ! fixed_regs [ regno ] && call_really_used_regs [ regno ] ) SET_HARD_REG_BIT ( reg_class_contents [ SIBCALL_REGS ] , regno ) ; call_really_used_regs [ FPSCR_MODES_REG ]


<s> bool <ISA_LIT>PreTileConfig :: runOnMachineFunction ( MachineFunction & mf ) { MF = & mf ; MRI = & mf . getRegInfo ( ) ; ST = & mf . getSubtarget < <ISA_LIT>Subtarget > ( ) ; TRI = ST -> getRegisterInfo ( ) ; TII = mf . getSubtarget ( ) . getInstrInfo ( ) ; DomTree = & getAnalysis < MachineDominatorTree > ( ) ; MachineInstr * MI = getTileConfigPoint ( ) ; if ( ! MI )


<s> bool shouldInsertFencesForAtomic ( const Instruction *


<s> return true ; default : return false ; } } switch ( I -> getOpcode ( ) ) { case Instruction :: Sub : case Instruction :: Add : { if ( ! areExtractExts ( I -> getOperand ( <NUM_LIT> ) , I -> getOperand ( <NUM_LIT> ) ) ) return false ; auto Ext1 = cast < Instruction > ( I -> getOperand ( <NUM_LIT> ) ) ; auto Ext2 = cast < Instruction > ( I -> getOperand ( <NUM_LIT> ) ) ; if ( areExtractShuffleVectors ( Ext1 , Ext2 ) ) { Ops . push_back ( & Ext1 -> getOperandUse ( <NUM_LIT> ) ) ; Ops . push_back ( & Ext2 -> getOperandUse ( <NUM_LIT> ) ) ; } Ops . push_back ( & I -> getOperandUse ( <NUM_LIT> ) ) ; Ops . push_back ( & I -> getOperandUse ( <NUM_LIT> ) ) ; return true ; } case Instruction :: Mul : { bool IsProfitable = false ; for ( auto & Op : I -> operands ( ) ) { if ( any_of ( Ops , [ & ] ( Use * U ) { return U -> get ( ) == Op ; } ) ) continue ; ShuffleVectorInst * Shuffle = dyn_cast < ShuffleVectorInst > ( Op ) ; if ( ! Shuffle || ! Shuffle -> isZeroEltSplat ( ) ) continue ; Value * ShuffleOperand = Shuffle -> getOperand ( <NUM_LIT> ) ; InsertElementInst * Insert = dyn_cast < InsertElementInst > ( ShuffleOperand ) ; if ( ! Insert ) continue ; Instruction * OperandInstr = dyn_cast < Instruction > ( Insert -> getOperand ( <NUM_LIT> ) ) ; if ( ! OperandInstr ) continue ; ConstantInt * ElementConstant = dyn_cast < ConstantInt > ( Insert -> getOperand ( <NUM_LIT> ) ) ; if ( ! ElementConstant || ElementConstant -> getZExtValue ( ) != <NUM_LIT> ) continue ; unsigned Opcode = OperandInstr


<s> loadRegFromStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned DestReg , int FI , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { DebugLoc DL ; if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; MachineFrameInfo & MFI = * MF . getFrameInfo ( ) ; unsigned Align = MFI . getObjectAlignment ( FI ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( FI ) , MachineMemOperand :: MOLoad , MFI . getObjectSize ( FI ) , Align ) ; switch ( RC -> getSize ( ) ) { case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) { AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ) ; } else llvm_unreachable ( <STR_LIT> ) ; break ; case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) { AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ) ; } else llvm_unreachable ( <STR_LIT> ) ; break ; case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) { if ( Align >= <NUM_LIT> && getRegisterInfo ( ) . needsStackRealignment ( MF ) ) { AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ) ; } else { AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addMemOperand ( MMO ) ) ; } } else llvm_unreachable ( <STR_LIT> ) ; break ; case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) { if ( Align >= <NUM_LIT> && getRegisterInfo ( ) . canRealignStack ( MF ) ) { AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand


<s> unsigned get<ISA_LIT>RegNum ( const MCOperand


<s> break ; default : { if ( InCPMode && AFI -> isThumbFunction ( ) ) InCPMode = false ; } } printInstruction ( MI )


<s> SmallVector < Constant * , <NUM_LIT> > CV1 ; CV1 . push_back ( ConstantFP :: get ( * Context , APFloat ( APFloat :: IEEEdouble , APInt ( <NUM_LIT> , <NUM_LIT> ) ) ) ) ; CV1 . push_back ( ConstantFP :: get ( * Context , APFloat ( APFloat :: IEEEdouble , APInt ( <NUM_LIT> , <NUM_LIT> ) ) ) ) ; Constant * C1 = ConstantVector :: get ( CV1 ) ; SDValue CPIdx1 = DAG . getConstantPool ( C1 , getPointerTy ( ) , <NUM_LIT> ) ; SDValue XR1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) ) ; SDValue CLod0 = DAG . getLoad ( <STR_LIT> , dl , DAG . getEntryNode ( ) , CPIdx0 , MachinePointerInfo :: getConstantPool ( ) , false , false , false , <NUM_LIT> ) ; SDValue Unpck1 = getUnpackl ( DAG , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , XR1 ) , CLod0 ) ; SDValue CLod1 = DAG . getLoad ( <STR_LIT> , dl , CLod0 . getValue ( <NUM_LIT> ) , CPIdx1 , MachinePointerInfo :: getConstantPool ( ) , false , false , false , <NUM_LIT> ) ; SDValue XR2F = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Unpck1 ) ; SDValue Sub = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , XR2F , CLod1 ) ; SDValue Result ; if ( Subtarget -> hasSSE3 ( ) ) { Result = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Sub , Sub ) ; } else { SDValue S2F = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Sub ) ; SDValue Shuffle = getTargetShuffleNode ( <STR_LIT> , dl , <STR_LIT> , S2F , <NUM_LIT> , DAG ) ; Result = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode

( <STR_LIT> , dl , <STR_LIT> , Shuffle ) , Sub ) ;


<s> temp . val [ <NUM_LIT> ] = vcombine_s64 ( val . val [ <NUM_LIT> ] , vcreate_s64 ( __AARCH64_INT64_C ( <NUM_LIT> ) ) ) ; __o = __builtin_aarch64_set_qregoiv2di ( __o , ( int64x2_t )

temp . val [ <NUM_LIT> ] , <NUM_LIT> ) ;


<s> bool IsSubWord = ( BitSize < <NUM_LIT> ) ; unsigned Dest = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; MachineOperand Base = earlyUseOperand ( MI -> getOperand ( <NUM_LIT> ) ) ; int64_t Disp = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; MachineOperand Src2 = earlyUseOperand ( MI -> getOperand ( <NUM_LIT> ) ) ; unsigned BitShift = ( IsSubWord ? MI -> getOperand ( <NUM_LIT> ) . getReg ( ) : <NUM_LIT> ) ; unsigned NegBitShift = ( IsSubWord ? MI -> getOperand ( <NUM_LIT> ) . getReg ( ) : <NUM_LIT> ) ; DebugLoc DL = MI -> getDebugLoc ( ) ; if ( IsSubWord ) BitSize = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; const TargetRegisterClass * RC = ( BitSize <= <NUM_LIT> ? & <STR_LIT> : & <STR_LIT> ) ; unsigned LOpcode = BitSize <= <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; unsigned CSOpcode = BitSize <= <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; LOpcode = TII -> getOpcodeForOffset ( LOpcode , Disp ) ; CSOpcode = TII -> getOpcodeForOffset ( CSOpcode , Disp ) ; assert ( LOpcode && CSOpcode && <STR_LIT> ) ; unsigned OrigVal = MRI . createVirtualRegister ( RC ) ; unsigned OldVal = MRI . createVirtualRegister ( RC ) ; unsigned NewVal = ( BinOpcode || IsSubWord ? MRI . createVirtualRegister ( RC ) : Src2 . getReg ( ) ) ; unsigned RotatedOldVal = ( IsSubWord ? MRI . createVirtualRegister ( RC ) : OldVal ) ; unsigned RotatedNewVal = ( IsSubWord ? MRI . createVirtualRegister ( RC ) : NewVal ) ; MachineBasicBlock * StartMBB = MBB ; MachineBasicBlock * DoneMBB = splitBlockAfter ( MI ,


<s> LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << MI << <STR_LIT> << TargetMBB . getNumber ( ) << <STR_LIT> ) ; for ( auto & Use : MI . uses ( ) ) { if ( Use . isReg ( ) && Register :: isVirtualRegister ( Use . getReg ( ) ) ) { MachineInstr * DefInst = MRI -> getVRegDef ( Use . getReg ( ) ) ; if ( DefInst -> isPHI ( ) && DefInst -> getParent ( ) == MI . getParent ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } else { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; } } } LLVM_DEBUG ( dbgs ( )


<s> for ( MachineFunction :: iterator B = MF -> begin ( ) , E = MF -> end ( ) ; B != E ; ++ B ) { for ( MachineBasicBlock :: instr_iterator I = B -> instr_begin ( ) , EB = B -> instr_end ( ) ; I != EB ; ++ I ) { switch ( I -> getDesc ( ) . getOpcode ( ) ) { case <STR_LIT> : { DEBUG ( dbgs ( ) << <STR_LIT> << * I << <STR_LIT> ) ; J = I -> getNumOperands ( ) ; DEBUG ( dbgs ( ) << <STR_LIT> << J << <STR_LIT> ) ; MachineOperand & Literal = I -> getOperand ( <NUM_LIT> ) ; if ( Literal . isImm ( ) ) { int64_t V = Literal . getImm ( ) ; DEBUG ( dbgs ( ) << <STR_LIT> << V


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , Optional < CodeModel :: Model > CM , CodeGenOpt :: Level OL , bool JIT ) : LLVMTargetMachine ( T , <STR_LIT> <STR_LIT> , TT , CPU , FS , Options , getRelocModel ( RM ) , getEffectiveCodeModel ( CM , CodeModel :: Small ) , OL )

, TLOF ( std :: make_unique < TargetLoweringObjectFileELF > ( ) ) , Subtarget ( TT , std :: string ( CPU ) , std :: string ( FS ) , * this ) {


<s> Inst . addOperand ( MCOperand :: CreateReg ( Reg


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> - <NUM_LIT> - ( TFI -> hasFP ( MF ) || STI -> isTargetDarwin ( ) ) - STI -> isTargetDarwin ( ) - hasBasePointer ( MF ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case


<s> if ( ( ! NeedMask || LateMask ) && ! Res ) { ValueRotInfo & VRI = ValueRotsVec [ <NUM_LIT> ] ; if ( VRI . RLAmt ) { if ( InstCnt ) * InstCnt += <NUM_LIT> ; SDValue Ops [ ] = { VRI . V , getI32Imm ( VRI . RLAmt , dl ) , getI32Imm ( <NUM_LIT> , dl ) , getI32Imm ( <NUM_LIT> , dl ) } ; Res = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , Ops ) , <NUM_LIT> ) ; } else { Res = VRI . V ; } eraseMatchingBitGroups ( [ VRI ] ( const BitGroup & BG ) { return BG . V == VRI . V && BG . RLAmt == VRI . RLAmt ; } ) ; } if ( InstCnt ) * InstCnt += BitGroups . size ( ) ; for ( auto & BG : BitGroups ) { if ( ! Res ) { SDValue Ops [ ] = { BG . V , getI32Imm ( BG . RLAmt , dl ) , getI32Imm ( Bits . size ( ) - BG . EndIdx - <NUM_LIT> , dl ) , getI32Imm ( Bits . size ( ) - BG . StartIdx - <NUM_LIT> , dl ) } ; Res = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , Ops ) , <NUM_LIT> ) ; } else { SDValue Ops [ ] = { Res , BG . V , getI32Imm ( BG . RLAmt , dl ) , getI32Imm ( Bits . size ( ) - BG . EndIdx - <NUM_LIT> , dl ) , getI32Imm ( Bits . size ( ) - BG . StartIdx - <NUM_LIT> , dl ) } ; Res = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl ,


<s> SDValue LHS3 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , LHS_1 , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; SDValue RHS_0 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , RHS , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; SDValue RHS_1 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , RHS , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; SDValue RHS0 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , RHS_0 , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; SDValue RHS1 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , RHS_0 , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; SDValue RHS2 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , RHS_1 , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; SDValue RHS3 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , RHS_1 , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; if ( UseTest ) { SDValue Top = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , LHS3 , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; Cmp = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Top ) ; } else { Cmp = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , LHS0 , RHS0 ) ; Cmp = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , LHS1 , RHS1 , Cmp ) ; Cmp = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , LHS2 , RHS2 , Cmp ) ; Cmp = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , LHS3 , RHS3 , Cmp ) ; } } else if ( VT == <STR_LIT> || VT == <STR_LIT> ) { if ( UseTest ) { Cmp = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , ( VT == <STR_LIT> ) ? LHS : DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , LHS , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ) ; } else { Cmp = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , LHS , RHS ) ; } } else { llvm_unreachable ( <STR_LIT> ) ; } if ( ! UseTest ) { <ISA_LIT>cc = DAG . getConstant ( intCCTo<ISA_LIT>CC ( CC )


<s> if ( VT . isVector ( ) ) { assert ( Subtarget . hasVBMI2 ( ) && <STR_LIT> ) ; if ( IsFSHR ) std :: swap ( Op0 , Op1 ) ; APInt APIntShiftAmt ; if ( isConstantSplat ( Amt , APIntShiftAmt ) ) { uint64_t ShiftAmt = APIntShiftAmt . getZExtValue ( ) ; return DAG . getNode ( IsFSHR ? <STR_LIT> : <STR_LIT> , DL , VT , Op0 , Op1 , DAG . getConstant ( ShiftAmt , DL , <STR_LIT> ) ) ; } return DAG . getNode ( IsFSHR ? <STR_LIT> : <STR_LIT> , DL , VT , Op0 , Op1 , Amt ) ; } assert ( ( VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> ) && <STR_LIT> ) ; bool OptForSize = DAG . getMachineFunction ( ) . getFunction ( ) . optForSize ( ) ; if ( ! OptForSize && Subtarget . isSHLDSlow ( ) ) return SDValue


<s> const <ISA_LIT>InstrInfo * getInstrInfo ( ) const override { return &


<s> static void ix86_function_arg_advance ( cumulative_args_t cum_v , machine_mode mode , const_tree type , bool named ) { CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; HOST_WIDE_INT bytes , words ; int nregs ; if ( mode == BLKmode ) bytes = int_size_in_bytes ( type ) ; else bytes = GET_MODE_SIZE ( mode ) ; words = CEIL ( bytes , UNITS_PER_WORD ) ; if ( type ) mode = type_natural_mode ( type , NULL , false ) ; if ( ( type && POINTER_BOUNDS_TYPE_P ( type ) ) || POINTER_BOUNDS_MODE_P ( mode ) ) { if ( cum -> bnds_in_bt ) { cum -> bnds_in_bt -- ; return ; } if ( cum -> force_bnd_pass ) cum -> force_bnd_pass -- ; cum -> bnd_regno ++ ; return ; } cum -> bnds_in_bt = <NUM_LIT> ; if ( cum -> force_bnd_pass ) { cum -> bnd_regno += cum -> force_bnd_pass ; cum -> force_bnd_pass = <NUM_LIT> ; } if ( TARGET_64BIT ) { enum calling_abi call_abi = cum ? cum -> call_abi : ix86_abi ; if ( call_abi == MS_ABI ) nregs = function_arg_advance_ms_64 ( cum , bytes , words ) ; else nregs = function_arg_advance_64 ( cum , mode , type , words , named ) ; } else nregs = function_arg_advance_32 ( cum , mode ,


<s> unsigned VectorSize = VT . getVectorNumElements ( ) * <NUM_LIT> ; if ( VectorSize < <NUM_LIT> || VectorSize > RegSize ) return SDValue ( ) ; SDLoc DL ( N ) ; EVT ReducedVT = EVT :: getVectorVT ( * DAG . getContext ( ) , <STR_LIT> , VT . getVectorNumElements ( ) ) ; EVT MAddVT = EVT :: getVectorVT ( * DAG . getContext ( ) , <STR_LIT> , VT . getVectorNumElements ( ) / <NUM_LIT> ) ; SDValue N0 = DAG . getNode ( <STR_LIT> , DL , ReducedVT , MulOp -> getOperand ( <NUM_LIT> ) ) ; SDValue N1 = DAG . getNode ( <STR_LIT> , DL , ReducedVT , MulOp -> getOperand ( <NUM_LIT> ) ) ; auto PMADDWDBuilder = [ ] ( SelectionDAG & DAG , const SDLoc & DL , ArrayRef < SDValue > Ops ) { MVT VT = <STR_LIT> ( <STR_LIT> , Ops [ <NUM_LIT> ] . getValueSizeInBits ( ) / <NUM_LIT> ) ; return DAG . getNode ( <STR_LIT> , DL , VT , Ops ) ; } ; SDValue Madd = SplitOpsAndApply ( DAG , Subtarget , DL , MAddVT , { N0 , N1 } , PMADDWDBuilder ) ; SDValue Zero = getZeroVector ( Madd . getSimpleValueType ( ) , Subtarget , DAG , DL ) ; SDValue Concat = DAG . getNode ( <STR_LIT> , DL , VT , Madd , Zero ) ; return DAG . getNode ( <STR_LIT> , DL , VT , Concat


<s> if ( Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic . startswith ( <STR_LIT> ) || Mnemonic . startswith ( <STR_LIT> ) || Mnemonic . startswith ( <STR_LIT> ) || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic . startswith ( <STR_LIT> ) || Mnemonic . startswith ( <STR_LIT> ) || Mnemonic . startswith ( <STR_LIT> ) || ( FullInst . startswith ( <STR_LIT> ) && FullInst . endswith ( <STR_LIT> ) ) ) { CanAcceptPredicationCode = false ; } else if ( ! isThumb ( ) ) { CanAcceptPredicationCode = Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && ! Mnemonic . startswith ( <STR_LIT> ) && ! Mnemonic . startswith ( <STR_LIT> ) ; } else if ( isThumbOne ( )


<s> int OffsetStride = IsScaled ? <NUM_LIT> : getMemScale ( * I ) ; bool MergeForward = Flags . getMergeForward ( ) ; MachineBasicBlock :: iterator InsertionPoint = MergeForward ? MergeMI : I ; const MachineOperand & BaseRegOp = MergeForward ? getLdStBaseOp ( * MergeMI ) : getLdStBaseOp ( * I ) ; MachineInstr * RtMI ; if ( getLdStOffsetOp ( * I ) . getImm ( ) == getLdStOffsetOp ( * MergeMI ) . getImm ( ) + OffsetStride ) RtMI = & * MergeMI ; else RtMI = & * I ; int OffsetImm = getLdStOffsetOp ( * RtMI ) . getImm ( ) ; if ( IsScaled ) { assert ( ( ( OffsetImm & <NUM_LIT> ) == <NUM_LIT> ) && <STR_LIT> ) ; OffsetImm /= <NUM_LIT> ; } DebugLoc DL = I -> getDebugLoc ( ) ; MachineBasicBlock * MBB = I -> getParent ( ) ; MachineInstrBuilder MIB ; MIB = BuildMI ( * MBB , InsertionPoint , DL , TII -> get ( getMatchingWideOpcode ( Opc ) ) ) . addReg ( isNarrowStore ( Opc ) ? <STR_LIT> : <STR_LIT> ) . add ( BaseRegOp ) . addImm ( OffsetImm ) . cloneMergedMemRefs ( { & * I , & * MergeMI } ) . setMIFlags ( I -> mergeFlagsWith ( * MergeMI ) ) ; ( void ) MIB ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( I -> print ( dbgs ( ) ) ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( MergeMI -> print ( dbgs ( ) ) ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( ( ( MachineInstr * ) MIB ) -> print ( dbgs ( ) ) ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; I -> eraseFromParent ( ) ; MergeMI -> eraseFromParent (


<s> static reg_class_t mn10300_preferred_reload_class ( rtx x , reg_class_t rclass ) { if ( x == stack_pointer_rtx && rclass != SP_REGS ) return ( TARGET_AM33 ? GENERAL_REGS : ADDRESS_REGS ) ; else if ( MEM_P ( x ) || ( REG_P ( x ) && ! HARD_REGISTER_P ( x ) ) || ( GET_CODE ( x ) == SUBREG && REG_P ( SUBREG_REG ( x )

) && ! HARD_REGISTER_P ( SUBREG_REG ( x ) ) ) ) return LIMIT_RELOAD_CLASS ( GET_MODE ( x ) , rclass ) ;


<s> return NeedsCFI ? <STR_LIT> : <STR_LIT> ; case <NUM_LIT> : return NeedsCFI ? <STR_LIT> : <STR_LIT> ; case <NUM_LIT> : return NeedsCFI ? <STR_LIT> : <STR_LIT> ; case <NUM_LIT> : return NeedsCFI ? <STR_LIT> : <STR_LIT> ; case <NUM_LIT> : return NeedsCFI ? <STR_LIT> : <STR_LIT> ; case


<s> int num_imm32_operand ; int num_imm64_operand ; if ( insn ) return get_num_immediates ( insn , & num_imm_operand , & num_imm32_operand , & num_imm64_operand ) ; return false


<s> nvptxSubtarget = & F . getSubtarget < <ISA_LIT>Subtarget > ( ) ; return AsmPrinter :: runOnMachineFunction ( F


<s> bool <ISA_LIT>RegisterInfo :: hasVGPRs ( const TargetRegisterClass * RC ) const { return getCommonSubClass ( & AMDGPU :: VGPR_32RegClass , RC ) || getCommonSubClass ( & AMDGPU :: VReg_64RegClass , RC ) || getCommonSubClass ( & AMDGPU :: VReg_96RegClass , RC ) || getCommonSubClass ( & AMDGPU :: VReg_128RegClass , RC ) || getCommonSubClass ( & AMDGPU ::

VReg_256RegClass , RC ) || getCommonSubClass ( & AMDGPU :: VReg_512RegClass , RC ) ;


<s> EXECUTE_IF_SET_IN_BITMAP ( insns , <NUM_LIT> , id , bi ) { convert_insn ( DF_INSN_UID_GET ( id ) -> insn ) ; converted_insns ++


<s> Target = & MI -> getOperand ( <NUM_LIT> ) ; return true ; case <STR_LIT> : case <STR_LIT> : Cond [ <NUM_LIT> ] . setImm ( <STR_LIT> ) ; Target = & MI -> getOperand ( <NUM_LIT> ) ; return true ; case <STR_LIT> : case <STR_LIT> : Cond [ <NUM_LIT> ] . setImm ( <STR_LIT> ) ; Target = & MI -> getOperand ( <NUM_LIT> ) ; return true ; case <STR_LIT> : case <STR_LIT> : Cond [ <NUM_LIT> ] . setImm ( <STR_LIT> ) ; Target = & MI -> getOperand ( <NUM_LIT> ) ; return true ; case <STR_LIT> : case <STR_LIT> : Cond [ <NUM_LIT> ] . setImm ( <STR_LIT> | <STR_LIT> ) ; Target = & MI -> getOperand ( <NUM_LIT> ) ; return true ; case <STR_LIT> : case <STR_LIT> : Cond [ <NUM_LIT> ] . setImm ( <STR_LIT> ) ; Target = & MI -> getOperand ( <NUM_LIT> ) ; return true ; case <STR_LIT> : case <STR_LIT> : Cond [ <NUM_LIT> ] . setImm ( <STR_LIT> | <STR_LIT> ) ; Target = & MI -> getOperand ( <NUM_LIT> ) ; return true ; case <STR_LIT> : case <STR_LIT> : Cond [ <NUM_LIT> ] . setImm ( <STR_LIT> ) ; Target = & MI -> getOperand ( <NUM_LIT> ) ; return true ; case <STR_LIT> : case <STR_LIT> : Cond [ <NUM_LIT> ] . setImm ( <STR_LIT> | <STR_LIT> ) ; Target = & MI -> getOperand ( <NUM_LIT> ) ; return true ; case <STR_LIT> : case <STR_LIT> : Cond [ <NUM_LIT> ] . setImm ( <STR_LIT> ) ; Target = & MI -> getOperand


<s> if ( REG_P ( pliw2 -> src ) && REGNO ( pliw2 -> src ) == REGNO ( pliw1 -> dest ) ) { if ( pliw1 -> op == LIW_OP_MOV && REG_P ( pliw1 -> src ) ) { if ( ! REG_P ( pliw1 -> src ) && ( pliw2 -> op == LIW_OP_AND || pliw2 -> op == LIW_OP_OR || pliw2 -> op == LIW_OP_XOR ) ) return false ; pliw2 -> src = pliw1 -> src ; return true ; } return false ; } return true


<s> bool <ISA_LIT>DAGToDAGISel :: tryT2IndexedLoad ( SDNode * N ) { LoadSDNode * LD = cast < LoadSDNode > ( N ) ; <STR_LIT> AM = LD -> getAddressingMode ( ) ; if ( AM == <STR_LIT> ) return false ; EVT LoadedVT = LD -> getMemoryVT ( ) ; bool isSExtLd = LD -> getExtensionType ( ) == <STR_LIT> ; SDValue Offset ; bool isPre = ( AM == <STR_LIT> ) || ( AM == <STR_LIT> ) ; unsigned Opcode = <NUM_LIT> ; bool Match = false ; if ( SelectT2AddrModeImm8Offset ( N , LD -> getOffset ( ) , Offset ) ) { switch ( LoadedVT . getSimpleVT ( ) . SimpleTy ) { case <STR_LIT> : Opcode = isPre ? <STR_LIT> : <STR_LIT> ; break ; case <STR_LIT> : if ( isSExtLd ) Opcode = isPre ? <STR_LIT> : <STR_LIT> ; else Opcode = isPre ? <STR_LIT> : <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : if ( isSExtLd ) Opcode = isPre ? <STR_LIT>


<s> else if ( orig_tune_defaulted ) opts -> x_ix86_tune_string = NULL ; if ( enum_opts_set . x_ix86_fpmath ) opts_set -> x_ix86_fpmath = ( enum fpmath_unit ) <NUM_LIT> ; if ( enum_opts_set . x_prefer_vector_width_type ) opts_set -> x_prefer_vector_width_type = ( enum prefer_vector_width ) <NUM_LIT> ; bool r = ix86_option_override_internal ( false , opts , opts_set ) ; if ( ! r ) { release_options_strings ( option_strings ) ; return error_mark_node ; } ix86_add_new_builtins ( opts -> x_ix86_isa_flags , opts -> x_ix86_isa_flags2 ) ; enum excess_precision orig_ix86_excess_precision = opts -> x_ix86_excess_precision ; bool orig_ix86_unsafe_math_optimizations = opts -> x_ix86_unsafe_math_optimizations ; opts -> x_ix86_excess_precision = opts -> x_flag_excess_precision ; opts -> x_ix86_unsafe_math_optimizations = opts -> x_flag_unsafe_math_optimizations ; t = build_target_option_node ( opts , opts_set ) ; opts -> x_ix86_arch_string = orig_arch_string ; opts -> x_ix86_tune_string = orig_tune_string ; opts_set -> x_ix86_fpmath = orig_fpmath_set ; opts_set -> x_prefer_vector_width_type = orig_pvw_set ; opts -> x_ix86_excess_precision = orig_ix86_excess_precision ; opts -> x_ix86_unsafe_math_optimizations = orig_ix86_unsafe_math_optimizations ; release_options_strings ( option_strings


<s> unsigned Val = ( MO . getImm ( ) & <NUM_LIT> ) ; assert ( Val == MO . getImm ( ) && <STR_LIT> ) ; unsigned Shift = <STR_LIT> ( MI -> getOperand ( OpNum + <NUM_LIT> ) . getImm ( ) ) ; O << '#' << Val ; if ( Shift != <NUM_LIT> ) printShifter ( MI , OpNum + <NUM_LIT> , O ) ; if ( CommentStream ) * CommentStream << <STR_LIT> << ( Val <<


<s> ret . val [ <NUM_LIT> ] = ( poly8x8_t ) __builtin_aarch64_get_dregciv8qi ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( poly8x8_t ) __builtin_aarch64_get_dregciv8qi ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( poly8x8_t ) __builtin_aarch64_get_dregciv8qi ( __o ,


<s> bool <ISA_LIT>TargetLowering :: allowsMisalignedMemoryAccesses ( EVT VT , unsigned AS , unsigned Align , bool * Fast ) const { if ( Fast ) * Fast = false ; return Subtarget . isHVXVectorType ( VT . getSimpleVT


<s> FunctionPass * llvm :: create<ISA_LIT>AnnotateUniformValues ( ) { return new <ISA_LIT>AnnotateUniformValues


<s> OS << <STR_LIT> << Twine ( RegNo ) <<


<s> bool <ISA_LIT>AsmBackend :: writeNopData ( uint64_t Count , MCObjectWriter * OW ) const { if ( ( Count % <NUM_LIT> ) != <NUM_LIT> ) return false ; for ( uint64_t i = <NUM_LIT> ; i < Count ; i += <NUM_LIT> ) OW -> write32 ( <NUM_LIT> ) ; return true


<s> return ( ( vec_int4 ) ( si_mpys ( ( qword ) ( a ) , ( qword ) ( b


<s> if ( ! REG_P ( reg1 ) || ! REG_P ( reg2 ) ) return false ; regno1 = REGNO ( reg1 ) ; regno2 = REGNO ( reg2 ) ; if ( ! GP_REG_P ( regno1 ) || ! GP_REG_P ( regno2 ) ) return false ; pair = ( <NUM_LIT> << regno1 ) | ( <NUM_LIT> << regno2 ) ; for ( i = <NUM_LIT> ; i < ARRAY_SIZE ( match ) ; i ++ ) if ( pair == match [ i ] ) return true ; return


<s> rtx nvptx_maybe_convert_symbolic_operand ( rtx orig_op ) { if ( GET_MODE ( orig_op ) != Pmode ) return orig_op ; rtx op = orig_op ; while ( GET_CODE ( op ) == PLUS || GET_CODE ( op ) == CONST ) op = XEXP ( op , <NUM_LIT> ) ; if ( GET_CODE ( op ) != SYMBOL_REF ) return orig_op ; tree decl = SYMBOL_REF_DECL ( op ) ; if ( decl && TREE_CODE ( decl ) == FUNCTION_DECL ) { nvptx_record_needed_fndecl ( decl ) ; return orig_op ; } addr_space_t as = nvptx_addr_space_from_address ( op ) ; if ( as == ADDR_SPACE_GENERIC ) return orig_op ; enum unspec code


<s> const unsigned * <ISA_LIT>RegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { static const unsigned CalleeSavedRegs [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } ; return CalleeSavedRegs


<s> if ( Subtarget . isDarwinABI ( ) ) { FPOpOut = getFramePointerFrameIndex ( DAG ) ; FPOpOut = DAG . getLoad ( VT , dl , Chain , FPOpOut , MachinePointerInfo ( ) ) ; Chain = SDValue ( FPOpOut . getNode ( ) ,


<s> } else if ( VT . getSizeInBits ( ) == <NUM_LIT> ) { SDValue Cst = DAG . getTargetConstantFP ( + <NUM_LIT> , <STR_LIT> ) ; SDValue Ops [ ] = { Cst , Cst , Cst , Cst , Cst , Cst , Cst , Cst } ; Vec = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Ops , <NUM_LIT> ) ; } return DAG . getNode ( <STR_LIT> , dl ,


<s> HOST_WIDE_INT size = <NUM_LIT> ; if ( mode == BLKmode ) { if ( type && TREE_CODE ( TYPE_SIZE ( type ) ) == INTEGER_CST ) size = int_size_in_bytes ( type ) ; } else size = GET_MODE_SIZE (


<s> unsigned Reg = getVectorListStart ( ) ; for ( unsigned i = <NUM_LIT> , e = getVectorListCount ( ) ; i != e ; ++ i ) OS << Reg + i << <STR_LIT> ; OS << <STR_LIT> ; break ; } case k_VectorIndex : OS << <STR_LIT> << getVectorIndex ( ) << <STR_LIT> ; break ; case k_SysReg : OS << <STR_LIT> << getSysReg ( ) << '>' ; break ; case k_Token : OS << <STR_LIT> << getToken ( ) << <STR_LIT> ; break ; case k_SysCR : OS << <STR_LIT> << getSysCR ( ) ; break ; case k_Prefetch : { StringRef Name = getPrefetchName ( ) ; if ( ! Name . empty ( ) ) OS << <STR_LIT> << Name << <STR_LIT> ; else OS << <STR_LIT> << getPrefetch ( ) << <STR_LIT> ; break ; } case k_PSBHint : OS << getPSBHintName ( ) ; break ; case k_BTIHint


<s> unsigned SuperReg = TRI -> getMatchingSuperReg ( DestReg , <STR_LIT> , & <STR_LIT> ) ; if ( VSXSelfCopyCrash && SrcReg == SuperReg ) llvm_unreachable ( <STR_LIT> ) ; DestReg = SuperReg ; } else if ( <STR_LIT> . contains ( SrcReg ) && <STR_LIT> . contains ( DestReg ) ) { unsigned SuperReg = TRI -> getMatchingSuperReg ( SrcReg , <STR_LIT> , & <STR_LIT> ) ; if ( VSXSelfCopyCrash && DestReg == SuperReg ) llvm_unreachable ( <STR_LIT> ) ; SrcReg = SuperReg ; } if ( <STR_LIT> . contains ( SrcReg ) && <STR_LIT> . contains ( DestReg ) ) { unsigned CRReg = getCRFromCRBit ( SrcReg ) ; BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( CRReg ) ; getKillRegState ( KillSrc ) ; BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( DestReg , RegState :: Kill ) . addImm ( TRI -> getEncodingValue ( CRReg ) * <NUM_LIT> + ( <NUM_LIT> - getCRBitValue ( SrcReg ) ) ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; return ; } else if ( <STR_LIT> . contains ( SrcReg ) && <STR_LIT> . contains ( DestReg ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg ) ; getKillRegState ( KillSrc ) ; return ; } else if ( <STR_LIT> . contains ( SrcReg ) && <STR_LIT> . contains ( DestReg ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg ) ; getKillRegState ( KillSrc ) ; return ; } else if ( <STR_LIT> . contains ( SrcReg ) && <STR_LIT> . contains ( DestReg ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg ) ; NumGPRtoVSRSpill ++ ; getKillRegState ( KillSrc ) ; return ; } else if ( <STR_LIT> . contains ( SrcReg ) && <STR_LIT> . contains ( DestReg ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg ) ; getKillRegState (


<s> int i , regno ; rtx op ; op = frv_read_argument ( call , index ) ; if ( GET_CODE ( op ) != CONST_INT || INTVAL ( op ) < <NUM_LIT> || INTVAL ( op ) > IACC_LAST - IACC_FIRST || ( ( INTVAL ( op ) * <NUM_LIT> ) & ( GET_MODE_SIZE ( mode ) - <NUM_LIT> ) ) != <NUM_LIT> ) { error ( <STR_LIT> ) ; op = const0_rtx ; } regno = INTVAL ( op ) + IACC_FIRST ; for ( i = <NUM_LIT> ; i < HARD_REGNO_NREGS ( regno , mode ) ; i ++ )


<s> aarch64_layout_frame ( ) ; return cfun -> machine -> frame


<s> rtx base , offset ; if ( CONST_INT_P ( x ) && loongarch_legitimate_constant_p ( mode , x ) ) return true ; split_const ( x , & base , & offset ) ; if ( loongarch_symbolic_constant_p ( base , & type ) ) { if ( IMM12_INT ( offset ) && loongarch_symbol_insns ( type , MAX_MACHINE_MODE ) > <NUM_LIT> ) return true ; } if ( tls_referenced_p ( x


<s> unsigned PtrArgAS = PtrArg -> getType ( ) -> getPointerAddressSpace ( ) ; auto * PtrTy = llvm :: PointerType :: get ( PtrElemTy , PtrArgAS ) ; SmallVector < llvm :: Type * , <NUM_LIT> > ArgTys ; for ( unsigned I = <NUM_LIT> ; I != PtrArgLoc ; ++ I ) ArgTys . push_back ( CI -> getArgOperand ( I ) -> getType ( ) ) ; ArgTys . push_back ( PtrTy ) ; Name = Name + <STR_LIT> + std :: to_string ( Size ) ; auto * FTy = FunctionType :: get ( Callee -> getReturnType ( ) , ArrayRef < Type * > ( ArgTys ) , false ) ; <ISA_LIT>LibFunc NewLibFunc ( Name , FTy ) ; FunctionCallee F = <ISA_LIT>LibFunc :: getOrInsertFunction ( M , NewLibFunc ) ; if ( ! F ) return false ; auto * BCast = B . CreatePointerCast ( PtrArg , PtrTy ) ; SmallVector < Value * , <NUM_LIT> > Args ; for ( unsigned I = <NUM_LIT> ; I != PtrArgLoc ; ++ I ) Args . push_back ( CI -> getArgOperand ( I ) ) ; Args . push_back ( BCast ) ; auto * NCI = B . CreateCall ( F , Args ) ; NCI -> setAttributes ( CI -> getAttributes ( ) ) ; CI -> replaceAllUsesWith ( NCI ) ; CI -> dropAllReferences ( ) ; CI -> eraseFromParent ( ) ; return true


<s> if ( ! TargetRegisterInfo :: isVirtualRegister ( OldR ) || ! TargetRegisterInfo :: isVirtualRegister ( NewR ) ) return false ; if ( OldSR != NewSR && hasTiedUse ( OldR , MRI , NewSR ) ) return false ; auto Begin = MRI . use_begin ( OldR ) , End = MRI . use_end ( ) ; decltype ( End ) NextI ; for ( auto I = Begin ; I != End ; I


<s> const <ISA_LIT>Z80InstrInfo * getInstrInfo ( ) const


<s> RegisterClassInfo * getRegClassInfo (


<s> if ( ! hasUndefRegUpdate ( MI . getOpcode ( ) ) ) return <NUM_LIT> ; OpNum = <NUM_LIT> ; const MachineOperand & MO = MI .


<s> std :: string DataLayout = std :: string ( <STR_LIT> <STR_LIT> <STR_LIT> <STR_LIT> <STR_LIT> ) ; if ( hasHWFP64 ( ) ) { DataLayout . append ( <STR_LIT> ) ; } if ( is64bit ( ) ) { DataLayout . append ( <STR_LIT> ) ; } else { DataLayout . append ( <STR_LIT> ) ; } if ( Gen >=


<s> static std :: pair < Value * , Value * > matchStridedStart ( Value * Start , IRBuilder < > & Builder ) { auto * StartC = dyn_cast < Constant > ( Start ) ; if ( StartC ) return matchStridedConstant ( StartC ) ; auto * BO = dyn_cast < BinaryOperator > ( Start ) ; if ( ! BO || BO -> getOpcode ( ) != Instruction :: Add ) return std :: make_pair ( nullptr , nullptr ) ; unsigned OtherIndex = <NUM_LIT> ; Value * Splat = getSplatValue ( BO -> getOperand ( <NUM_LIT> ) ) ; if ( ! Splat ) { Splat = getSplatValue ( BO -> getOperand ( <NUM_LIT> ) ) ; OtherIndex = <NUM_LIT> ; } if ( ! Splat ) return std :: make_pair ( nullptr


<s> } unsigned MOHiFlag , MOLoFlag ; bool IsPIC = isPositionIndependent ( ) ; getLabelAccessInfo ( IsPIC , Subtarget , MOHiFlag , MOLoFlag ) ; if ( IsPIC && Subtarget . isSVR4ABI ( ) ) { SDValue GA = DAG . getTargetJumpTable ( JT -> getIndex ( ) , PtrVT , <STR_LIT> ) ; return getTOCEntry ( DAG , SDLoc ( GA ) , false , GA ) ; } SDValue JTIHi = DAG . getTargetJumpTable ( JT -> getIndex ( ) , PtrVT ,


<s> DebugLoc dl = Node -> getDebugLoc ( ) ; SDValue VAList = DAG . getLoad ( <STR_LIT> , dl , InChain , VAListPtr , SV , <NUM_LIT> ) ; SDValue NextPtr = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , VAList , DAG . getConstant ( VT . getSizeInBits ( ) / <NUM_LIT> , <STR_LIT> ) ) ; InChain = DAG . getStore ( VAList . getValue ( <NUM_LIT> ) , dl , NextPtr , VAListPtr , SV , <NUM_LIT> ) ; if ( VT != <STR_LIT> ) return DAG . getLoad ( VT , dl , InChain , VAList , NULL , <NUM_LIT> ) ; SDValue V = DAG . getLoad ( <STR_LIT> , dl , InChain , VAList , NULL , <NUM_LIT> ) ; SDValue Ops [ <NUM_LIT> ] = { DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , V ) , V . getValue ( <NUM_LIT> ) } ; return DAG . getMergeValues ( Ops


<s> } else if ( ( Imm >= DppCtrl :: ROW_ROR_FIRST ) && ( Imm <= DppCtrl :: ROW_ROR_LAST ) ) { O << <STR_LIT> ; printU4ImmDecOperand ( MI , OpNo , O ) ; } else if ( Imm == DppCtrl :: WAVE_SHL1 ) { if ( ! <STR_LIT> ( STI ) && ! <STR_LIT> ( STI ) ) { O << <STR_LIT> ; return ; } O << <STR_LIT> ; } else if ( Imm == DppCtrl :: WAVE_ROL1 ) { if ( ! <STR_LIT> ( STI ) && ! <STR_LIT> ( STI ) ) { O << <STR_LIT> ; return ; } O << <STR_LIT> ; } else if ( Imm == DppCtrl :: WAVE_SHR1 ) { if ( ! <STR_LIT> ( STI ) && ! <STR_LIT> ( STI ) ) { O << <STR_LIT> ; return ; } O << <STR_LIT> ; } else if ( Imm == DppCtrl :: WAVE_ROR1 ) { if ( ! <STR_LIT> ( STI ) && ! <STR_LIT> ( STI ) ) { O << <STR_LIT> ; return ; } O << <STR_LIT> ; } else if ( Imm == DppCtrl :: ROW_MIRROR ) { O << <STR_LIT> ; } else if ( Imm == DppCtrl :: ROW_HALF_MIRROR ) { O << <STR_LIT> ; } else if ( Imm == DppCtrl :: BCAST15 ) { if ( ! <STR_LIT> ( STI ) && ! <STR_LIT> ( STI ) ) { O << <STR_LIT> ; return ; } O << <STR_LIT> ; } else if ( Imm == DppCtrl :: BCAST31 ) { if ( ! <STR_LIT> ( STI ) && ! <STR_LIT> ( STI ) ) { O << <STR_LIT> ; return ; } O << <STR_LIT> ; } else if ( ( Imm >= DppCtrl :: ROW_SHARE_FIRST ) && ( Imm <= DppCtrl :: ROW_SHARE_LAST ) ) { if ( ! <STR_LIT> ( STI ) ) { O << <STR_LIT> ; return ; } O << <STR_LIT> ; printU4ImmDecOperand ( MI , OpNo , O ) ; } else if ( ( Imm >= DppCtrl :: ROW_XMASK_FIRST ) && ( Imm <= DppCtrl :: ROW_XMASK_LAST ) ) { if ( ! <STR_LIT> ( STI ) ) { O <<


<s> ThisVal = MaxEncodableValue ; } else { ThisVal = Offset & MaxEncodableValue ; } assert ( ( ThisVal >> ShiftSize ) <= MaxEncoding && <STR_LIT> ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( Opc ) , DestReg ) . addReg ( SrcReg ) . addImm ( ThisVal >> ShiftSize ) . addImm ( <STR_LIT> ( <STR_LIT> , ShiftSize ) ) . setMIFlag ( Flag ) ; if ( NeedsWinCFI && SrcReg == <STR_LIT> && DestReg == <STR_LIT> ) { if ( HasWinCFI ) * HasWinCFI = true ; BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) ) . addImm ( ThisVal ) . setMIFlag ( Flag ) ; } SrcReg = DestReg ; Offset -= ThisVal ; if ( Offset == <NUM_LIT> ) return ; } BuildMI ( MBB , MBBI , DL , TII -> get ( Opc ) , DestReg ) . addReg ( SrcReg ) . addImm ( Offset ) . addImm ( <STR_LIT> ( <STR_LIT> , <NUM_LIT> ) ) . setMIFlag ( Flag ) ; if ( NeedsWinCFI ) { if ( ( DestReg == <STR_LIT> && SrcReg == <STR_LIT> ) || ( SrcReg == <STR_LIT> && DestReg == <STR_LIT> ) ) { if ( HasWinCFI ) * HasWinCFI


<s> const <ISA_LIT>TargetLowering * TLI = static_cast < const

<ISA_LIT>TargetLowering * > ( getTargetLowering ( ) ) ;


<s> O << <STR_LIT> ; printRegName ( O , MI -> getOperand ( OpNum ) . getReg ( ) ) ; O << <STR_LIT> ; printRegName ( O , MI -> getOperand ( OpNum ) . getReg ( ) + <NUM_LIT> ) ; O <<


<s> if ( VECTOR_MODE_P ( mode0 ) ) op0 = safe_vector_operand ( op0 , mode0 ) ; if ( VECTOR_MODE_P ( mode1 ) ) op1 = safe_vector_operand ( op1 , mode1 ) ; if ( optimize || ! target || GET_MODE ( target ) != tmode || ! insn_data [ icode ] . operand [ <NUM_LIT> ] . predicate ( target , tmode ) ) target = gen_reg_rtx ( tmode ) ; if ( GET_MODE ( op1 ) == SImode && mode1 == TImode ) { rtx x = gen_reg_rtx ( V4SImode ) ; emit_insn ( gen_sse2_loadd ( x , op1 ) ) ; op1 = gen_lowpart ( TImode , x ) ; } if ( ! insn_data [ icode ] . operand [ <NUM_LIT> ] . predicate ( op0 , mode0 ) ) op0 = copy_to_mode_reg ( mode0 , op0 ) ; if ( ! insn_data [ icode ] . operand [ <NUM_LIT> ] . predicate ( op1 , mode1 ) ) op1 = copy_to_mode_reg ( mode1 , op1 ) ; pat = GEN_FCN ( icode ) ( target , op0


<s> cvtLdWriteBackRegAddrMode3 ( MCInst & Inst , unsigned Opcode , const SmallVectorImpl < MCParsedAsmOperand * > & Operands ) { ( ( <ISA_LIT>Operand * ) Operands [ <NUM_LIT> ] ) -> addRegOperands ( Inst , <NUM_LIT> ) ; Inst . addOperand ( MCOperand :: CreateImm ( <NUM_LIT> ) ) ; ( ( <ISA_LIT>Operand * ) Operands [ <NUM_LIT> ] )

-> addAddrMode3Operands ( Inst , <NUM_LIT> ) ;


<s> void addMVEVectorIndexOperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> &&


<s> InLastByte += MFI . getObjectSize ( FI -> getIndex ( ) ) - <NUM_LIT> ; if ( ( InFirstByte <= FirstByte && FirstByte <= InLastByte ) || ( FirstByte <= InFirstByte && InFirstByte <= LastByte ) ) ArgChains . push_back ( SDValue ( L , <NUM_LIT> ) ) ; } return DAG . getNode ( <STR_LIT> , SDLoc ( Chain ) ,


<s> case MULT : op2_l = gen_reg_rtx ( qimode ) ; op2_h = gen_reg_rtx ( qimode ) ; emit_insn ( gen_il ( op2_l , op2 , op2 ) ) ; emit_insn ( gen_ih ( op2_h , op2 , op2 ) ) ; op1_l = gen_reg_rtx ( qimode ) ; op1_h = gen_reg_rtx ( qimode ) ; emit_insn ( gen_il ( op1_l , op1 , op1 ) ) ; emit_insn ( gen_ih ( op1_h , op1 , op1 ) ) ; full_interleave = qimode == V16QImode ; break ; case ASHIFT : case LSHIFTRT : uns_p = true ; case ASHIFTRT : op1_l = gen_reg_rtx ( himode ) ; op1_h = gen_reg_rtx ( himode ) ; ix86_expand_sse_unpack ( op1_l , op1 , uns_p , false ) ; ix86_expand_sse_unpack ( op1_h , op1 , uns_p , true ) ; full_interleave = true ; break ; default : gcc_unreachable ( ) ; } res_l = expand_simple_binop ( himode , code , op1_l , op2_l , NULL_RTX , <NUM_LIT> , OPTAB_DIRECT ) ; res_h = expand_simple_binop ( himode , code , op1_h , op2_h , NULL_RTX , <NUM_LIT> , OPTAB_DIRECT ) ; gcc_assert ( res_l && res_h ) ; d . target = dest ; d . op0 = gen_lowpart ( qimode , res_l ) ; d . op1 = gen_lowpart ( qimode , res_h ) ; d . vmode = qimode ; d . nelt = GET_MODE_NUNITS ( qimode ) ; d . one_operand_p = false ; d . testing_p = false ; if ( full_interleave


<s> const <ISA_LIT>RegisterInfo & getRegisterInfo ( ) const { return RI


<s> if ( hasFP ( MF ) ) { BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addImm ( FPOffset ) . addReg ( <STR_LIT> ) ; } if ( MFI -> adjustsStack ( ) ) { BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addImm ( RAOffset ) . addReg ( <STR_LIT> ) ; } if ( NumBytes ) { BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) ,

<STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( NumBytes ) ;


<s> if ( Section -> useCodeAlign ( ) ) getStreamer ( ) . emitCodeAlignment ( <NUM_LIT> , & getSTI ( ) , <NUM_LIT> ) ; else getStreamer ( ) . emitValueToAlignment ( <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> ) ; return false


<s> if ( RegNo > <NUM_LIT> ) return Fail ; unsigned Register = GPR64DecoderTable [ RegNo ] ; if ( Register == <STR_LIT> ) Register = <STR_LIT> ; Inst . addOperand ( MCOperand :: createReg ( Register ) ) ; return


<s> return ( __mmask8 ) __builtin_ia32_cvtw2mask128 ( ( __v8hi )


<s> return MI . findRegisterDefOperandIdx (


<s> void <ISA_LIT>TargetStreamer :: outputDwarfFileDirectives ( ) { for ( const std :: string & S : DwarfFiles ) getStreamer ( ) . emitRawText (


<s> if ( isMicro<ISA_LIT> ( STI ) && hasShortDelaySlot ) { Opc = is<ISA_LIT>32r6 ( STI ) ? <STR_LIT> : <STR_LIT> ; emitRR ( Opc , <STR_LIT> , <STR_LIT> , IDLoc , STI ) ; return ; } if ( isMicro<ISA_LIT> ( STI ) ) Opc = is<ISA_LIT>32r6 ( STI ) ? <STR_LIT> : <STR_LIT> ; emitRRI ( Opc , <STR_LIT> , <STR_LIT> ,


<s> void printU6ImmOperand ( const MachineInstr * MI , unsigned OpNo ) { unsigned char value = MI -> getOperand ( OpNo ) . getImm ( ) ; assert ( value <= <NUM_LIT> && <STR_LIT> ) ; O << ( unsigned int )


<s> static SDValue LowerREADCYCLECOUNTER ( SDValue Op , const <ISA_LIT>Subtarget & Subtarget , SelectionDAG & DAG ) { SmallVector < SDValue , <NUM_LIT> > Results ; SDLoc DL ( Op )


<s> if ( FoldOp -> isImm ( ) ) { ImmToFold = FoldOp -> getImm ( ) ; } else if ( FoldOp -> isFI ( ) ) { FrameIndexToFold = FoldOp -> getIndex ( ) ; } else


<s> for ( MachineInstr & MI : MBB ) if ( MI . definesRegister

( <STR_LIT> ) || MI . definesRegister ( <STR_LIT> ) ) return true ;


<s> rtx fn , insn , retval ; tree return_type ; machine_mode return_mode ; const char * name ; return_type = DECL_RESULT ( current_function_decl ) ; return_mode = DECL_MODE ( return_type ) ; name = ACONCAT ( ( <STR_LIT> , mips16_call_stub_mode_suffix ( return_mode ) , NULL ) ) ; fn = mips16_stub_function ( name


<s> for ( auto * Succ : MBB . successors ( ) ) { if ( Succ -> isEHPad ( ) ) { UnwindDest = Succ ; break ; } } if ( EHPadStack . back ( ) == UnwindDest ) continue ; MachineInstr * RangeBegin = & MI , * RangeEnd = & MI ; if ( RangeBegin -> getIterator ( ) != MBB . begin ( ) && std :: prev ( RangeBegin -> getIterator ( ) ) -> isEHLabel ( ) ) RangeBegin = & * std :: prev ( RangeBegin -> getIterator ( ) ) ; if ( std :: next ( RangeEnd -> getIterator ( ) ) != MBB . end ( ) && std :: next ( RangeEnd -> getIterator ( ) ) -> isEHLabel ( ) ) RangeEnd = & * std :: next ( RangeEnd -> getIterator ( ) ) ; UnwindDestToTryRanges [ UnwindDest ] . push_back ( TryRange ( RangeBegin , RangeEnd ) ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << MBB . getName ( ) << <STR_LIT> << MI << <STR_LIT> << UnwindDest -> getName ( ) << <STR_LIT> << EHPadStack . back ( ) -> getName ( ) << <STR_LIT> ) ; } } assert ( EHPadStack . empty ( ) ) ; MachineInstr * RangeBegin = nullptr , * RangeEnd = nullptr ; auto RecordCallerMismatchRange = [ & ] ( const MachineBasicBlock * CurrentDest ) { UnwindDestToTryRanges [ getFakeCallerBlock ( MF ) ] . push_back ( TryRange ( RangeBegin , RangeEnd ) ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << RangeBegin -> getParent ( ) -> getName ( ) << <STR_LIT> << * RangeBegin << <STR_LIT> << * RangeEnd << <STR_LIT> << CurrentDest -> getName ( ) << <STR_LIT> ) ; RangeBegin = RangeEnd = nullptr ; } ; for ( auto & MBB : reverse (


<s> NewPNodes [ OldPN ] = NewPN ; } for ( auto * OldPN : OldPhiNodes ) { PHINode * NewPN = NewPNodes [ OldPN ] ; for ( unsigned j = <NUM_LIT> , e = OldPN -> getNumOperands ( ) ; j != e ; ++ j ) { Value * V = OldPN -> getOperand ( j ) ; Value * NewV = nullptr ; Instruction * ACI = dyn_cast < Instruction > ( V ) ; if ( ACI && isAMXCast ( ACI ) ) NewV = ACI -> getOperand ( <NUM_LIT> ) ; else if ( auto * PrevPN = dyn_cast < PHINode > ( V ) ) NewV = NewPNodes [ PrevPN ] ; assert ( NewV ) ; NewPN -> addIncoming ( NewV , OldPN -> getIncomingBlock ( j ) ) ; } } for ( auto * OldPN : OldPhiNodes ) { PHINode * NewPN = NewPNodes [ OldPN ] ; for ( User * V : make_early_inc_range ( OldPN -> users ( ) ) ) { Instruction * ACI = dyn_cast < Instruction > ( V ) ; if ( ACI && isAMXCast ( ACI ) ) { Type * TyB = ACI -> getOperand ( <NUM_LIT> ) -> getType ( ) ; Type * TyA = ACI -> getType ( ) ; assert ( TyA == DestTy && TyB == SrcTy ) ; ( void ) TyA ; ( void ) TyB ; ACI -> replaceAllUsesWith ( NewPN ) ; DeadInst . insert ( ACI


<s> if ( ! <ISA_LIT>SubTarget -> isSVR4ABI ( ) ) InsertVRSaveCode ( MF ) ; return


<s> LowerSELECT ( SDValue Op , SelectionDAG & DAG ) const { SDValue Cond = CreateFPCmp ( DAG , Op .


<s> return RC . hasSuperClassEq ( & <STR_LIT> ) || RC . hasSuperClassEq ( & <STR_LIT> ) || RC . hasSuperClassEq ( & <STR_LIT> ) || RC . hasSuperClassEq ( &

<STR_LIT> ) || RC . hasSuperClassEq ( & <STR_LIT> ) || RC . hasSuperClassEq ( & <STR_LIT> ) ;


<s> static int parse_devices_csv ( const char * mcu_name ) { if ( msp430_devices_csv_loc != NULL ) return parse_devices_csv_1 ( msp430_devices_csv_loc , mcu_name ) ; else if ( derived_devices_csv_loc != NULL ) return parse_devices_csv_1 ( derived_devices_csv_loc , mcu_name ) ; if ( msp430_check_env_var_for_devices ( & derived_devices_csv_loc ) ) return <NUM_LIT> ; return parse_devices_csv_1 ( derived_devices_csv_loc ,


<s> bool HasAVX = Subtarget . hasAVX ( ) ; bool HasAVX512 = Subtarget . hasAVX512 ( ) ; if ( <STR_LIT> . contains ( DestReg ) ) { if ( <STR_LIT> . contains ( SrcReg ) ) return HasAVX512 ? <STR_LIT> : HasAVX ? <STR_LIT> : <STR_LIT> ; if ( <STR_LIT> . contains ( SrcReg ) ) return <STR_LIT> ; } else if ( <STR_LIT> . contains ( SrcReg ) ) { if ( <STR_LIT> . contains ( DestReg ) ) return HasAVX512 ? <STR_LIT> : HasAVX ? <STR_LIT> : <STR_LIT> ; if ( <STR_LIT> . contains ( DestReg ) )


<s> bool <ISA_LIT>TTIImpl :: enableAggressiveInterleaving ( bool LoopHasReductions ) { return


<s> void HSACodeObject :: InitMarkers ( ) const { auto TextSecOr = getTextSection ( ) ; if ( ! TextSecOr ) return ; auto TextSec = TextSecOr . get ( ) ; FunctionMarkers . push_back ( TextSec -> sh_size ) ; for ( const auto & Sym : functions ( ) ) { auto ExpectedFunction = FunctionSym :: asFunctionSym ( getSymbol ( Sym . getRawDataRefImpl ( ) ) ) ; if ( ! ExpectedFunction ) { consumeError ( ExpectedFunction . takeError (


<s> rtx_insn * insn , * next ; rtx_insn * last_condjump = NULL ; int cycles_since_jump = INT_MAX ; int delay_added = <NUM_LIT> ; if ( ! ENABLE_WA_SPECULATIVE_LOADS && ! ENABLE_WA_SPECULATIVE_SYNCS && ! ENABLE_WA_INDIRECT_CALLS ) return ; for ( insn = get_insns ( ) ; insn ; insn = next ) { rtx pat ; int delay_needed = <NUM_LIT> ; next = find_next_insn_start ( insn ) ; if ( NOTE_P ( insn ) || BARRIER_P ( insn ) ) continue ; if ( JUMP_TABLE_DATA_P ( insn ) ) continue ; if ( LABEL_P ( insn ) ) { np_check_regno = - <NUM_LIT> ; continue ; } pat = PATTERN ( insn ) ; if ( GET_CODE ( pat ) == USE || GET_CODE ( pat ) == CLOBBER ) continue ; if ( GET_CODE ( pat ) == ASM_INPUT || asm_noperands ( pat ) >= <NUM_LIT> ) { np_check_regno = - <NUM_LIT> ; continue ; } if ( JUMP_P ( insn ) ) { if ( np_check_regno != - <NUM_LIT> && recog_memoized ( insn ) == CODE_FOR_cbranchbi4 ) { rtx op = XEXP ( SET_SRC ( PATTERN ( insn ) ) , <NUM_LIT> ) ; gcc_assert ( GET_CODE ( op ) == EQ || GET_CODE ( op ) == NE ) ; if ( GET_CODE ( op ) == NE ) np_after_branch = true ; } if ( any_condjump_p ( insn ) && ! cbranch_predicted_taken_p ( insn ) ) { last_condjump = insn ; delay_added = <NUM_LIT> ; cycles_since_jump = <NUM_LIT> ; } else cycles_since_jump = INT_MAX ; } else if ( CALL_P ( insn ) ) { np_check_regno = - <NUM_LIT> ; if ( cycles_since_jump < INT_MAX ) cycles_since_jump ++ ; if ( indirect_call_p ( pat ) && ENABLE_WA_INDIRECT_CALLS ) { delay_needed = <NUM_LIT> ; } } else if ( NONDEBUG_INSN_P ( insn ) ) { rtx_insn * load_insn = find_load ( insn ) ; enum attr_type type = type_for_anomaly ( insn ) ; if ( cycles_since_jump < INT_MAX ) cycles_since_jump ++ ; if ( recog_memoized ( insn ) == CODE_FOR_compare_eq ) { rtx src = SET_SRC ( PATTERN ( insn ) ) ; if ( REG_P ( XEXP ( src , <NUM_LIT> ) ) && P_REGNO_P ( REGNO ( XEXP ( src , <NUM_LIT> ) ) ) && XEXP ( src , <NUM_LIT> ) == const0_rtx ) { np_check_regno = REGNO ( XEXP ( src , <NUM_LIT> ) ) ; np_after_branch = false ; } else np_check_regno = - <NUM_LIT> ; } if ( load_insn &&


<s> for ( unsigned i = <NUM_LIT> , e = array_lengthof ( ReplaceableInstrs ) ; i != e ; ++ i ) if ( ReplaceableInstrs [ i ] [ domain - <NUM_LIT> ] == opcode ) return ReplaceableInstrs [ i ] ; return


<s> if ( NeedFence ) BuildMI ( MBB , I , DL , TII -> get ( <STR_LIT> ) ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; MachineInstr * Addi = BuildMI ( MBB , I , DL , TII -> get ( Opc1 ) , GPR3 ) . addReg ( InReg ) ; Addi -> addOperand ( MI . getOperand ( <NUM_LIT> ) ) ; MachineBasicBlock :: iterator First = I ; -- First ; MachineInstr * Call = ( BuildMI ( MBB , I , DL , TII -> get ( Opc2 ) , GPR3 ) . addReg ( GPR3 ) ) ; Call -> addOperand ( MI . getOperand ( <NUM_LIT> ) ) ; if ( NeedFence ) BuildMI ( MBB , I , DL , TII -> get ( <STR_LIT> ) ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; BuildMI ( MBB , I , DL , TII -> get ( TargetOpcode :: COPY ) , OutReg ) . addReg ( GPR3 ) ; MachineBasicBlock :: iterator Last = I ; -- Last ; ++ I


<s> bool is16BitMode ( ) const { return ( STI . getFeatureBits (


<s> if ( ST -> isThumb2 ( ) ) { if ( ( SImmVal >= <NUM_LIT> && SImmVal < <NUM_LIT> ) || ( <STR_LIT> ( ZImmVal ) != - <NUM_LIT> ) || ( <STR_LIT> ( ~ ZImmVal ) != - <NUM_LIT> ) ) return <NUM_LIT> ; return ST -> hasV6T2Ops ( ) ? <NUM_LIT> : <NUM_LIT> ; } if ( SImmVal >= <NUM_LIT> && SImmVal < <NUM_LIT> ) return <NUM_LIT> ; if ( ( ~ ZImmVal < <NUM_LIT> ) ||

<STR_LIT> ( ZImmVal ) ) return <NUM_LIT> ;


<s> if ( ! CONST_INT_P ( element ) ) return false ; value = INTVAL ( element ) ; if ( ! IN_RANGE ( value , - <NUM_LIT> , <NUM_LIT> ) ) return false ; for ( i = <NUM_LIT> ; i < nunits ; i ++ ) { element = CONST_VECTOR_ELT ( op , i ) ; if ( ! CONST_INT_P ( element ) ) return false ; if ( value != INTVAL ( element ) ) return false ; } } else if ( CONST_INT_P ( op ) ) { if ( ! SCALAR_INT_MODE_P ( mode ) ) return false ; value = INTVAL ( op ) ; if ( ! IN_RANGE ( value , - <NUM_LIT> , <NUM_LIT> ) ) return false ; if ( ! IN_RANGE ( value , - <NUM_LIT> , <NUM_LIT> ) ) { if ( ! ( reg_addr [ mode ] . addr_mask [ RELOAD_REG_VMX ] & RELOAD_REG_VALID ) ) return false ; if ( EASY_VECTOR_15 ( value ) ) return false ; } } else return false ; if ( ( mode == V4SImode || mode == V8HImode ) && ! IN_RANGE ( value , - <NUM_LIT> , <NUM_LIT> ) && EASY_VECTOR_15 ( value ) ) return false ; if ( mode == V16QImode ) * num_insns_ptr = <NUM_LIT> ; else if ( IN_RANGE ( value , - <NUM_LIT> , <NUM_LIT> ) ) * num_insns_ptr = <NUM_LIT> ; else * num_insns_ptr


<s> if ( ! arm_get_set_operands ( producer , consumer , & value , & addr ) ) return <NUM_LIT> ; return reg_overlap_mentioned_p ( value , addr


<s> static void alpha_expand_unaligned_load_words ( rtx * out_regs , rtx smem , HOST_WIDE_INT words , HOST_WIDE_INT ofs ) { rtx const im8 = GEN_INT ( - <NUM_LIT> ) ; rtx const i64 = GEN_INT ( <NUM_LIT> ) ; rtx ext_tmps [ MAX_MOVE_WORDS ] , data_regs [ MAX_MOVE_WORDS + <NUM_LIT> ] ; rtx sreg , areg , tmp , smema ; HOST_WIDE_INT i ; smema = XEXP ( smem , <NUM_LIT> ) ; if ( GET_CODE ( smema ) == LO_SUM ) smema = force_reg ( Pmode , smema ) ; for ( i = <NUM_LIT> ; i < words ; ++ i ) { data_regs [ i ] = out_regs [ i ] ; ext_tmps [ i ] = gen_reg_rtx ( DImode ) ; } data_regs [ words ] = gen_reg_rtx ( DImode ) ; if ( ofs != <NUM_LIT> ) smem = adjust_address ( smem , GET_MODE ( smem ) , ofs ) ; for ( i = <NUM_LIT> ; i < words ; ++ i ) { tmp = change_address ( smem , DImode , gen_rtx_AND ( DImode , plus_constant ( smema , <NUM_LIT> * i ) , im8 ) ) ; set_mem_alias_set ( tmp


<s> else if ( CurrCycleInstr -> isDebugInstr ( ) ) return ; unsigned NumWaitStates = TII . getNumWaitStates ( * CurrCycleInstr ) ; EmittedInstrs . push_front ( CurrCycleInstr ) ; for ( unsigned i = <NUM_LIT> , e = std :: min ( NumWaitStates , getMaxLookAhead ( ) ) ; i < e ; ++ i ) { EmittedInstrs . push_front (


<s> return ( __m128i ) __builtin_ia32_cvtps2uqq128_mask ( ( __v4sf ) __A , ( __v2di ) _mm_setzero_si128 ( ) , (


<s> bool isSOPP ( uint16_t Opcode ) const { return get ( Opcode ) . TSFlags


<s> MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B


<s> return EmitTargetCodeForMemOp ( DAG , dl , Chain , Dst , Src , Size , Alignment ,

isVolatile , AlwaysInline , MustPreserveCheriCapabilities , DstPtrInfo , SrcPtrInfo , true ) ;


<s> if ( SDValue ZExt = lowerShuffleAsZeroOrAnyExtend ( DL , <STR_LIT> , V1 , V2 , Mask , Zeroable , Subtarget , DAG ) ) return ZExt ; SmallVector < int , <NUM_LIT> > RepeatedMask ; bool Is128BitLaneRepeatedShuffle = is128BitLaneRepeatedShuffleMask ( <STR_LIT> , Mask , RepeatedMask ) ; if ( Is128BitLaneRepeatedShuffle ) { assert ( RepeatedMask . size ( ) == <NUM_LIT> && <STR_LIT> ) ; if ( V2 . isUndef ( ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , getV4<ISA_LIT>ShuffleImm8ForMask ( RepeatedMask , DL , DAG ) ) ; if ( SDValue V = lowerShuffleWithUNPCK ( DL , <STR_LIT> , Mask , V1 , V2 , DAG ) ) return V ; } if ( SDValue Shift = lowerShuffleAsShift ( DL , <STR_LIT> , V1 , V2 , Mask , Zeroable , Subtarget , DAG ) ) return Shift ; if ( SDValue Rotate = lowerShuffleAsVALIGN ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return Rotate ; if ( Subtarget . hasBWI ( ) ) if ( SDValue Rotate = lowerShuffleAsByteRotate ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG


<s> using namespace <STR_LIT> ; unsigned TTmpMin = isGFX9Plus ( ) ? TTMP_GFX9PLUS_MIN : TTMP_VI_MIN ; unsigned TTmpMax = isGFX9Plus ( ) ?


<s> SDValue Op0 , Op1 ; switch ( ConstraintCode ) { default : return true ; case 'm' : if ( ! SelectADDRrr ( Op , Op0 , Op1 ) )


<s> if ( Outs . empty ( ) ) return NotStructReturn ; const <STR_LIT> & Flags = Outs [ <NUM_LIT> ] . Flags ; if ( ! Flags . isSRet ( ) ) return NotStructReturn ; if ( Flags . isInReg ( ) ||


<s> static bool arc_vector_mode_supported_p ( machine_mode mode ) { switch ( mode ) { case E_V2HImode : return TARGET_PLUS_DMPY ; case E_V4HImode : case E_V2SImode : return TARGET_PLUS_QMACW ; case E_V4SImode : case E_V8HImode


<s> case <STR_LIT> : case <STR_LIT> : return true ; default : return false


<s> Value * Args [ ] = { NewLd0 , NewLd1 , Acc } ; Function * SMLAD = nullptr ; if ( Exchange ) SMLAD = Acc -> getType ( ) -> isIntegerTy ( <NUM_LIT> ) ? <STR_LIT> ( M , <STR_LIT> ) : <STR_LIT> ( M , <STR_LIT> ) ; else SMLAD = Acc -> getType ( ) -> isIntegerTy ( <NUM_LIT> ) ? <STR_LIT> ( M , <STR_LIT> ) : <STR_LIT> ( M , <STR_LIT> ) ; CallInst * Call = Builder . CreateCall ( SMLAD , Args


<s> SDValue <ISA_LIT>TargetLowering :: LowerHvxBuildVector ( SDValue Op , SelectionDAG & DAG ) const { const SDLoc & dl ( Op ) ; MVT VecTy = ty ( Op ) ; unsigned Size = Op . getNumOperands ( ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; for ( unsigned i = <NUM_LIT> ; i != Size ; ++ i ) Ops . push_back ( Op . getOperand ( i ) ) ; if ( VecTy . getSizeInBits ( ) == <NUM_LIT> * Subtarget . getVectorLength ( ) ) { ArrayRef < SDValue > A ( Ops ) ; MVT SingleTy = typeSplit ( VecTy ) . first ; SDValue V0 = buildHvxVectorReg ( A . take_front ( Size / <NUM_LIT> ) , dl , SingleTy , DAG ) ; SDValue V1 = buildHvxVectorReg ( A . drop_front ( Size / <NUM_LIT> ) , dl , SingleTy , DAG ) ; return DAG . getNode ( <STR_LIT> , dl , VecTy , V0 , V1 ) ; } if ( VecTy . getVectorElementType ( ) == <STR_LIT> ) return buildHvxVectorPred ( Ops , dl , VecTy , DAG ) ; if ( VecTy . getVectorElementType ( ) == <STR_LIT> ) { SmallVector < SDValue , <NUM_LIT> > NewOps ; for ( unsigned i = <NUM_LIT> ; i != Size ; i ++ ) NewOps . push_back ( DAG . getBitcast ( <STR_LIT> , Ops [ i ] ) ) ; SDValue T0 = DAG . getNode ( <STR_LIT> , dl , tyVector ( VecTy , <STR_LIT> ) , NewOps ) ; return DAG . getBitcast ( tyVector ( VecTy , <STR_LIT> ) , T0 ) ; } return buildHvxVectorReg ( Ops , dl , VecTy ,


<s> switch ( CallConv ) { case CallingConv :: C : case CallingConv :: Fast : return LowerCCCArguments ( Chain , CallConv , IsVarArg , Ins , DL


<s> const MCRegisterInfo * MRI = MF . getMMI ( ) . getContext ( ) . getRegisterInfo ( ) ; MachineBasicBlock :: iterator MBBI = MBB . begin ( ) ; DebugLoc dl = MBBI != MBB . end ( ) ? MBBI -> getDebugLoc ( ) : DebugLoc ( ) ; uint64_t StackSize = computeStackSize ( MF ) ; if ( ! StackSize ) { return ; } unsigned StackReg = <STR_LIT> ; unsigned OffsetReg = materializeOffset ( MF , MBB , MBBI , ( unsigned ) StackSize ) ; if ( OffsetReg ) { BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , StackReg ) . addReg ( StackReg ) . addReg ( OffsetReg ) . setMIFlag ( MachineInstr :: FrameSetup ) ; } else { BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , StackReg ) . addReg ( StackReg ) . addImm ( StackSize ) . setMIFlag ( MachineInstr :: FrameSetup ) ; } if ( CSI . size ( ) ) { for ( unsigned i = <NUM_LIT> ; i < CSI . size ( ) ; ++ i ) ++ MBBI ; for ( std :: vector < CalleeSavedInfo > :: const_iterator I = CSI . begin ( ) , E = CSI . end ( ) ; I != E ; ++ I ) { int64_t Offset = MFI . getObjectOffset ( I -> getFrameIdx ( ) ) ; unsigned CFIIndex = MF . addFrameInst ( MCCFIInstruction :: createOffset ( nullptr , MRI -> getDwarfRegNum ( I -> getReg ( ) , <NUM_LIT> ) , Offset ) ) ; BuildMI ( MBB , MBBI , dl , TII . get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; } } uint64_t StackSize = <NUM_LIT> * <NUM_LIT> ; MF . getFrameInfo ( ) . setStackSize ( StackSize ) ; unsigned StackReg = <STR_LIT> ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , StackReg ) . addReg ( <STR_LIT> ) .


<s> unsigned ScalarSize = VT . getScalarSizeInBits ( ) ; MVT XLenVT = Subtarget -> getXLenVT ( ) ; <ISA_LIT>VLMUL LMUL = getLMUL ( VT ) ; SDValue SEW = CurDAG -> getTargetConstant ( ScalarSize , DL , XLenVT ) ; SmallVector < SDValue , <NUM_LIT> > Regs ( Node -> op_begin ( ) + <NUM_LIT> , Node -> op_begin ( ) + <NUM_LIT> + NF ) ; SDValue MaskedOff = createTuple ( * CurDAG , Regs , NF , LMUL ) ; SmallVector < SDValue , <NUM_LIT> > Operands ; Operands . push_back ( MaskedOff ) ; Operands . push_back ( Node -> getOperand ( NF + <NUM_LIT> ) ) ; if ( IsStrided ) { Operands . push_back ( Node -> getOperand ( NF + <NUM_LIT> ) ) ; Operands . push_back ( Node -> getOperand ( NF + <NUM_LIT> ) ) ; Operands . push_back ( Node -> getOperand ( NF + <NUM_LIT> ) ) ; } else { Operands . push_back ( Node -> getOperand (


<s> __builtin_aarch64_simd_oi __o ; __o = __builtin_aarch64_ld2v16qi ( ( const __builtin_aarch64_simd_qi * ) __a ) ; ret . val [ <NUM_LIT> ] = ( poly8x16_t ) __builtin_aarch64_get_qregoiv16qi ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( poly8x16_t ) __builtin_aarch64_get_qregoiv16qi ( __o , <NUM_LIT> ) ; return ret


<s> if ( ! isCFProtectionSupported && ! IndirectBranchTracking ) return false ; bool Changed = false ; TII = SubTarget . getInstrInfo ( ) ; EndbrOpcode = SubTarget . is64Bit ( ) ? <STR_LIT> : <STR_LIT> ; if ( MF . getFunction ( ) . hasAddressTaken ( ) || ! MF . getFunction ( ) . hasLocalLinkage ( ) ) { auto MBB = MF . begin ( ) ; addENDBR ( * MBB ) ; Changed = true


<s> explicit <ISA_LIT>MachineFunctionInfo ( MachineFunction & MF ) : HasSpills ( false ) , HasAllocas ( false ) , HasStackArgs ( false ) , CalleeSavedFrameSize ( <NUM_LIT> ) , VarArgsFrameIndex ( <NUM_LIT> ) { unsigned CallConv = MF . getFunction ( ) .


<s> for ( unsigned Reg : RegList ) Inst .

addOperand ( MCOperand :: createReg ( Reg ) ) ;


<s> if ( Depth > <NUM_LIT> ) return matchAddressBase ( N , AM ) ; switch ( N . getOpcode ( ) ) { case <STR_LIT> : { uint64_t Val = cast < ConstantSDNode > ( N ) -> getSExtValue ( ) ; if ( ! foldOffsetIntoAddress ( Val , AM ) ) return false ; break ; } case <STR_LIT> : if ( ! matchWrapper ( N , AM ) ) return false ; break ; case <STR_LIT> : { HandleSDNode Handle ( N ) ; <ISA_LIT>ISelAddressMode Backup = AM ; if ( ! matchVectorAddressRecursively ( N . getOperand ( <NUM_LIT> ) , AM , Depth + <NUM_LIT> ) && ! matchVectorAddressRecursively ( Handle . getValue ( ) . getOperand ( <NUM_LIT> ) , AM , Depth + <NUM_LIT> ) ) return false ; AM =


<s> SmallVector < RegDomain , <NUM_LIT> > getLegalDstDomains ( )


<s> unsigned getNumberOfRegisters ( unsigned ClassID ) const { bool VectorRegs = ( ClassID == <NUM_LIT> ) ; if ( VectorRegs ) { return <NUM_LIT> ; } return <NUM_LIT>


<s> } else { DestReg1 = constrainOperandRegClass ( TII . get ( <STR_LIT> ) , DestReg1 , <NUM_LIT> ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( <STR_LIT> ) , DestReg1 ) . addConstantPoolIndex ( Idx ) . addImm ( <NUM_LIT> ) ) ; Opc = UseGOTOFF ? <STR_LIT> : <STR_LIT> ; } unsigned GlobalBaseReg = AFI -> getGlobalBaseReg ( ) ; if ( GlobalBaseReg == <NUM_LIT> ) { GlobalBaseReg = MRI . createVirtualRegister ( TLI . getRegClassFor ( VT ) ) ; AFI -> setGlobalBaseReg ( GlobalBaseReg ) ; } unsigned DestReg2 = createResultReg ( TLI . getRegClassFor ( VT ) ) ; DestReg2 = constrainOperandRegClass ( TII . get ( Opc ) , DestReg2 , <NUM_LIT> ) ; DestReg1 = constrainOperandRegClass ( TII . get ( Opc ) , DestReg1 , <NUM_LIT> ) ; GlobalBaseReg = constrainOperandRegClass ( TII . get ( Opc ) , GlobalBaseReg , <NUM_LIT> ) ; MachineInstrBuilder MIB = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( Opc ) , DestReg2 ) . addReg ( DestReg1 ) . addReg ( GlobalBaseReg ) ; if ( ! UseGOTOFF ) MIB . addImm


<s> if ( cum -> float_in_sse < <NUM_LIT> ) break ; case E_SFmode : if ( cum -> float_in_sse == - <NUM_LIT> ) error_p = true ; if ( cum -> float_in_sse < <NUM_LIT> ) break ; case E_V16HFmode : case E_V16BFmode : case E_V8SFmode : case E_V8SImode : case E_V64QImode : case E_V32HImode : case E_V16SImode : case E_V8DImode : case E_V32HFmode : case E_V32BFmode : case E_V16SFmode : case E_V8DFmode : case E_V32QImode : case E_V16HImode : case E_V4DFmode : case E_V4DImode : case E_TImode : case E_V16QImode : case E_V8HImode : case E_V4SImode : case E_V2DImode : case E_V8HFmode : case E_V8BFmode : case E_V4SFmode : case E_V2DFmode : if ( ! type || ! AGGREGATE_TYPE_P ( type ) ) { cum -> sse_words += words ; cum -> sse_nregs -= <NUM_LIT> ; cum -> sse_regno += <NUM_LIT>


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; if ( Kind == Immediate ) Inst . addOperand ( MCOperand :: createImm ( getImm ( ) / <NUM_LIT> ) ) ; else Inst . addOperand ( MCOperand :: createExpr (


<s> if ( Op1 -> isDivergent ( ) ) std :: swap ( Op1 , Op2 ) ; if ( DAG . isConstantIntBuildVectorOrConstantInt ( Op0 ) || DAG . isConstantIntBuildVectorOrConstantInt ( Op1 ) ) return SDValue ( ) ; SDLoc SL ( N ) ; SDValue Add1 = DAG . getNode ( Opc , SL , VT , Op0 , Op1 ) ; return DAG . getNode ( Opc , SL , VT


<s> break ; case <STR_LIT> : selectArch ( <STR_LIT> ) ; getTargetStreamer ( ) . emitDirectiveSet<ISA_LIT>32 ( ) ; break ; case <STR_LIT> : selectArch ( <STR_LIT> ) ; getTargetStreamer ( ) . emitDirectiveSet<ISA_LIT>32R2 ( ) ; break ; case <STR_LIT> : selectArch ( <STR_LIT> ) ; getTargetStreamer ( ) . emitDirectiveSet<ISA_LIT>32R6 ( ) ; break ; case <STR_LIT> : selectArch ( <STR_LIT> ) ; getTargetStreamer ( ) . emitDirectiveSet<ISA_LIT>64 ( ) ; break ; case <STR_LIT> : selectArch ( <STR_LIT> ) ; getTargetStreamer ( ) . emitDirectiveSet<ISA_LIT>64R2 ( ) ; break ; case <STR_LIT> : selectArch ( <STR_LIT> ) ; getTargetStreamer ( ) . emitDirectiveSet<ISA_LIT>64R6 ( ) ; break ; } return false


<s> const TargetInstrInfo * TII = getTargetMachine ( ) . getSubtargetImpl ( ) -> getInstrInfo ( ) ; DebugLoc DL = MI -> getDebugLoc ( ) ; unsigned LL , SC , ZERO , BNE , BEQ ; LL = <STR_LIT> ; SC = <STR_LIT> ; ZERO = <STR_LIT> ; BNE = <STR_LIT> ; BEQ = <STR_LIT> ; unsigned Dest = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Ptr = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned OldVal = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned NewVal = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Success = RegInfo . createVirtualRegister ( RC ) ; const BasicBlock * LLVM_BB = BB -> getBasicBlock ( ) ; MachineBasicBlock * loop1MBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * loop2MBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * exitMBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineFunction :: iterator It = BB ; ++ It ; MF -> insert ( It , loop1MBB ) ; MF -> insert ( It , loop2MBB ) ; MF -> insert ( It , exitMBB ) ; exitMBB -> splice ( exitMBB -> begin ( ) , BB , std :: next ( MachineBasicBlock :: iterator ( MI ) ) , BB -> end ( ) ) ; exitMBB -> transferSuccessorsAndUpdatePHIs ( BB ) ; BB -> addSuccessor ( loop1MBB ) ; loop1MBB -> addSuccessor ( exitMBB ) ; loop1MBB -> addSuccessor ( loop2MBB ) ; loop2MBB -> addSuccessor ( loop1MBB ) ; loop2MBB -> addSuccessor ( exitMBB ) ; BB = loop1MBB ; BuildMI ( BB , DL , TII -> get ( LL ) , Dest ) . addReg ( Ptr ) . addImm ( <NUM_LIT> ) ; BuildMI ( BB , DL , TII -> get ( BNE ) ) . addReg ( Dest ) . addReg ( OldVal ) . addMBB ( exitMBB ) ; BB = loop2MBB ; BuildMI ( BB , DL , TII -> get ( SC ) , Success ) . addReg ( NewVal ) . addReg ( Ptr ) . addImm ( <NUM_LIT> ) ; BuildMI ( BB , DL , TII -> get ( BEQ ) ) . addReg ( Success ) . addReg ( ZERO ) . addMBB ( loop1MBB ) ; MI -> eraseFromParent


<s> if ( ! isInt < <NUM_LIT> > ( AM . BaseOffs ) ) return false ; switch ( AM . Scale ) { case <NUM_LIT> : break ; case <NUM_LIT> : if ( ! AM . HasBaseReg ) break ; return false ; default : return


<s> const TargetInstrInfo * TII = Fn . getTarget ( ) . getInstrInfo ( ) ; MachineLoopInfo & MLI = getAnalysis < MachineLoopInfo > ( ) ; MachineDominatorTree & MDT = getAnalysis < MachineDominatorTree > ( ) ; Tile64VLIWPacketizerList Packetizer ( Fn , MLI , MDT ) ; assert ( Packetizer . getResourceTracker ( ) && <STR_LIT> ) ; for ( MachineFunction :: iterator MBB = Fn . begin ( ) , MBBe = Fn . end


<s> bool hasV7Ops ( ) const { return getSTI ( ) . getFeatureBits ( ) [


<s> FM . serializeToFaultMapSection ( ) ; OutStreamer -> EmitAssemblerFlag ( MCAF_SubsectionsViaSymbols ) ; } if ( TT . isKnownWindowsMSVCEnvironment ( ) && MMI -> usesVAFloatArgument ( ) ) { StringRef SymbolName = ( TT . getArch ( ) == Triple :: x86_64 ) ? <STR_LIT> : <STR_LIT> ; MCSymbol * S = MMI -> getContext ( ) . getOrCreateSymbol ( SymbolName ) ; OutStreamer -> EmitSymbolAttribute ( S , MCSA_Global ) ; } if ( TT . isOSBinFormatCOFF ( ) ) { const TargetLoweringObjectFileCOFF & TLOFCOFF = static_cast < const TargetLoweringObjectFileCOFF & > ( getObjFileLowering ( ) ) ; std :: string Flags ; raw_string_ostream FlagsOS ( Flags ) ; for ( const auto & Function : M ) TLOFCOFF . emitLinkerFlagsForGlobal ( FlagsOS , & Function , * Mang ) ; for ( const auto & Global : M . globals ( ) ) TLOFCOFF . emitLinkerFlagsForGlobal ( FlagsOS , & Global , * Mang ) ; for ( const auto & Alias : M . aliases ( ) ) TLOFCOFF . emitLinkerFlagsForGlobal ( FlagsOS , & Alias , * Mang ) ; FlagsOS . flush ( ) ; if ( ! Flags . empty ( ) ) { OutStreamer -> SwitchSection ( TLOFCOFF . getDrectveSection ( ) ) ; OutStreamer -> EmitBytes (


<s> MachineBasicBlock * MBB = MI -> getParent ( ) ; MachineFunction * MF = MI -> getParent ( ) -> getParent ( ) ; const <ISA_LIT>InstrInfo * TII = static_cast < const <ISA_LIT>InstrInfo * > ( MF -> getSubtarget ( ) . getInstrInfo ( ) ) ; DebugLoc DL = MI -> getDebugLoc ( ) ; bool IsStore = TII -> get ( LoadStoreOp ) . mayStore ( ) ; bool RanOutOfSGPRs = false ; bool Scavenged = false ; unsigned SOffset = ScratchOffset ; unsigned OriginalImmOffset = Offset ; unsigned NumSubRegs = getNumSubRegsForSpillOp ( MI -> getOpcode ( ) ) ; unsigned Size = NumSubRegs * <NUM_LIT> ; if ( ! isUInt < <NUM_LIT> > ( Offset + Size ) ) { SOffset = <STR_LIT> ; if ( RS ) SOffset = RS -> FindUnusedReg ( & <STR_LIT> ) ; if ( SOffset == <STR_LIT> ) { RanOutOfSGPRs = true ; SOffset = ScratchOffset ; } else { Scavenged = true ; } BuildMI ( * MBB , MI , DL , TII -> get ( <STR_LIT> ) , SOffset ) . addReg ( ScratchOffset ) . addImm ( Offset ) ; Offset = <NUM_LIT> ; } for ( unsigned i = <NUM_LIT> , e = NumSubRegs ; i != e ; ++ i , Offset += <NUM_LIT> ) { unsigned SubReg = NumSubRegs > <NUM_LIT> ? getPhysRegSubReg ( Value


<s> iterator begin ( ) const { return SubExceptions .


<s> ErrorLoc = IdLoc ; if ( ErrorInfo != ~ <NUM_LIT> ) { if ( ErrorInfo >= Operands . size ( ) ) return Error ( IdLoc , <STR_LIT> ) ; ErrorLoc = ( ( <ISA_LIT>Operand & ) * Operands [ ErrorInfo ] ) . getStartLoc ( ) ; if ( ErrorLoc == SMLoc ( ) ) ErrorLoc = IdLoc ; } return Error ( ErrorLoc , <STR_LIT> ) ; } default : break ; } llvm_unreachable (


<s> return isInSmallSection ( DL . getTypeAllocSize ( CN -> getType ( )


<s> const <ISA_LIT>MCExpr * Expr = cast < <ISA_LIT>MCExpr > ( ImmOp . getExpr ( ) ) ; unsigned FixupKind ; switch ( Expr -> getKind ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <ISA_LIT>MCExpr :: VK_AARCH64_LO12 : { unsigned FixupsBySize [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; assert ( MemSize <= <NUM_LIT> && <STR_LIT> ) ; FixupKind = FixupsBySize [ Log2_32 ( MemSize ) ] ; break ; } case <ISA_LIT>MCExpr :: VK_AARCH64_GOT_LO12 : assert ( MemSize == <NUM_LIT> && <STR_LIT> ) ; FixupKind = <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: VK_AARCH64_DTPREL_LO12 : { unsigned FixupsBySize [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; assert ( MemSize <= <NUM_LIT> && <STR_LIT> ) ; FixupKind = FixupsBySize [ Log2_32 ( MemSize ) ] ; break ; } case <ISA_LIT>MCExpr :: VK_AARCH64_DTPREL_LO12_NC : { unsigned FixupsBySize [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; assert ( MemSize <= <NUM_LIT> && <STR_LIT> ) ; FixupKind = FixupsBySize [ Log2_32 ( MemSize ) ] ; break ; } case <ISA_LIT>MCExpr :: VK_AARCH64_GOTTPREL_LO12 : assert ( MemSize == <NUM_LIT> && <STR_LIT>


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . setPreservesCFG ( ) ; AU . addPreserved < ScalarEvolutionWrapperPass > (


<s> bool IsSigned = Op . getOpcode ( ) == <STR_LIT> ; MVT VT = Op . getSimpleValueType ( ) ; if ( VT . isVector ( ) ) { assert ( Subtarget . hasDQI ( ) && Subtarget . hasVLX ( ) && <STR_LIT> ) ; SDValue Src = Op . getOperand ( <NUM_LIT> ) ; SDLoc dl ( Op ) ; if ( VT == <STR_LIT> && Src . getSimpleValueType ( ) == <STR_LIT> ) { return DAG . getNode ( IsSigned ? <STR_LIT> : <STR_LIT> , dl , VT , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Src , DAG . getUNDEF ( <STR_LIT> ) ) ) ; } return SDValue ( ) ; } assert ( ! VT . isVector ( ) ) ; std :: pair < SDValue , SDValue > Vals = FP_TO_INTHelper ( Op , DAG , IsSigned , false ) ; SDValue FIST = Vals . first , StackSlot


<s> DenseSet < unsigned > * LiveOuts = InnerRegion -> getLiveOuts ( ) ; SmallVector < unsigned , <NUM_LIT> > OldLiveOuts ; bool IsSingleBB = InnerRegion -> getEntry ( ) == InnerRegion -> getExit ( ) ; for ( auto OLI : * LiveOuts ) { OldLiveOuts . push_back ( OLI ) ; } for ( auto LI : OldLiveOuts ) { DEBUG ( dbgs ( ) << <STR_LIT> << PrintReg ( LI , TRI ) ) ; if ( ! containsDef ( CodeBB , InnerRegion , LI ) || ( ! IsSingleBB && ( getDefInstr ( LI ) -> getParent ( ) == LRegion -> getExit ( ) ) ) ) { DEBUG ( dbgs ( ) << <STR_LIT> ) ; continue ; } DEBUG ( dbgs ( ) << <STR_LIT> ) ; unsigned Reg = LI ; if ( Reg != InnerRegion -> getBBSelectRegOut (


<s> DAG . getContext ( ) -> diagnose ( NoTrap ) ; return DAG . getNode ( <STR_LIT> , SDLoc ( Op ) , <STR_LIT>


<s> int h8300_eightbit_data_p ( tree decl ) { tree a ; if ( TREE_CODE ( decl ) != VAR_DECL


<s> enum x86_64_reg_class alt_classes [ MAX_CLASSES ] ; zero_width_bitfields = <NUM_LIT> ; if ( classify_argument ( mode , type , alt_classes , bit_offset , zero_width_bitfields ) != n ) zero_width_bitfields = <NUM_LIT> ; else for ( int i = <NUM_LIT> ; i < n ; i ++ ) if ( classes [ i ] != alt_classes [ i ] ) { zero_width_bitfields = <NUM_LIT> ; break ; } if ( zero_width_bitfields


<s> unsigned Opcode = ( ! IsSigned || ! Subtarget -> hasSSE41 ( ) ) ? <STR_LIT> : <STR_LIT> ; SDValue Mul1 = DAG . getBitcast ( VT , DAG . getNode ( Opcode , dl , MulVT , Op0 , Op1 ) ) ; SDValue Mul2 = DAG . getBitcast ( VT , DAG . getNode ( Opcode , dl , MulVT , Odd0 , Odd1 ) ) ; SDValue Highs , Lows ; if ( VT == <STR_LIT> ) { const int HighMask [ ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; Highs = DAG . getVectorShuffle ( VT , dl , Mul1 , Mul2 , HighMask ) ; const int LowMask [ ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; Lows = DAG . getVectorShuffle ( VT , dl , Mul1 , Mul2 , LowMask ) ; } else { const int HighMask [ ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; Highs = DAG . getVectorShuffle ( VT , dl , Mul1 , Mul2 , HighMask ) ; const int LowMask [ ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; Lows = DAG . getVectorShuffle ( VT , dl , Mul1 , Mul2 , LowMask ) ; } if ( IsSigned && ! Subtarget -> hasSSE41 ( ) ) { SDValue ShAmt = DAG . getConstant ( <NUM_LIT> , dl , DAG . getTargetLoweringInfo ( ) . getShiftAmountTy ( VT ) ) ; SDValue T1 = DAG . getNode ( <STR_LIT> , dl , VT , DAG . getNode ( <STR_LIT> , dl , VT , Op0 , ShAmt ) , Op1 ) ; SDValue T2 = DAG . getNode ( <STR_LIT> , dl , VT , DAG . getNode ( <STR_LIT> , dl , VT , Op1 , ShAmt ) , Op0 ) ; SDValue Fixup = DAG . getNode ( <STR_LIT> , dl , VT , T1 , T2 ) ; Highs = DAG . getNode ( <STR_LIT> , dl , VT ,


<s> APInt A ; for ( unsigned i = <NUM_LIT> ; i < LS2 . size ( ) ; ++ i ) { LatticeCell RC ; bool Eval = constToInt ( LS2 . Values [ i ] , A ) && evaluateANDri ( R1 , A , Inputs , RC ) ; if ( ! Eval ) return false ; Result . meet ( RC ) ; } return ! Result .


<s> rtx neg_src ; if ( short_mode ) src = gen_lowpart ( wmode , src ) ; neg_src = gen_rtx_NEG ( wmode , src ) ; emit_insn ( gen_rtx_SET ( src , neg_src ) ) ; if ( short_mode ) src = gen_lowpart ( mode , src ) ; } case PLUS : ldop_code = AARCH64_LDOP_PLUS ; break ; case IOR : ldop_code = AARCH64_LDOP_OR ; break ; case XOR : ldop_code = AARCH64_LDOP_XOR ; break ; case AND : { rtx not_src ; if ( short_mode ) src = gen_lowpart ( wmode , src ) ; not_src = gen_rtx_NOT ( wmode , src ) ; emit_insn ( gen_rtx_SET ( src , not_src ) ) ; if ( short_mode ) src = gen_lowpart ( mode , src ) ; } ldop_code = AARCH64_LDOP_BIC ; break ; default : gcc_unreachable ( ) ; } aarch64_emit_atomic_load_op ( ldop_code , mode , out_data , src , mem , model_rtx ) ; if ( ! out_result ) return ; if ( short_mode ) { src = gen_lowpart ( wmode , src ) ; out_data = gen_lowpart ( wmode , out_data ) ; out_result = gen_lowpart ( wmode , out_result ) ; } x = NULL_RTX ; switch ( code ) { case MINUS : case PLUS : x = gen_rtx_PLUS ( wmode , out_data , src ) ; break ; case IOR : x = gen_rtx_IOR ( wmode , out_data , src ) ; break ; case XOR : x = gen_rtx_XOR ( wmode , out_data , src ) ; break ; case AND : aarch64_emit_bic ( wmode , out_result , out_data , src , <NUM_LIT> ) ; return ; default : gcc_unreachable ( )


<s> if ( MRI . getType ( ExtReg ) . getSizeInBits ( ) == <NUM_LIT> ) return ExtReg ; Register NarrowReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; auto Copy = MIB . buildCopy ( { NarrowReg } , { ExtReg } ) ; selectCopy ( * Copy , TII , MRI , TRI , RBI ) ; return Copy . getReg (


<s> unsigned <ISA_LIT>RegisterInfo :: getFrameRegister ( const MachineFunction &


<s> static int sparc_adjust_cost ( rtx insn , rtx link , rtx dep , int cost ) { switch ( sparc_cpu ) { case PROCESSOR_SUPERSPARC : cost = supersparc_adjust_cost ( insn , link , dep , cost ) ; break ; case PROCESSOR_HYPERSPARC : case PROCESSOR_SPARCLITE86X : cost = hypersparc_adjust_cost ( insn , link , dep , cost ) ; break ; default : break ; } return cost


<s> PICStyles :: Style getPICStyle ( ) const { return PICStyle


<s> case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; } abort ( )


<s> Streamer . visitUsedExpr ( * getSubExpr (


<s> if ( Inactive . isUndef ( ) ) { LowerToCopyInstrs . push_back ( & MI ) ; } else { unsigned Reg = Inactive . getReg ( ) ; if ( TargetRegisterInfo :: isVirtualRegister ( Reg ) ) { for ( MachineInstr & DefMI : MRI -> def_instructions ( Reg ) ) markInstruction ( DefMI , StateWWM , Worklist ) ; } } } SetInactiveInstrs . push_back ( & MI ) ; continue ; } else if ( TII -> isDisableWQM ( MI ) ) { BBI . Needs |= StateExact ; if ( ! ( BBI . InNeeds & StateExact ) ) { BBI . InNeeds |= StateExact ; Worklist . push_back ( & MBB ) ; } GlobalFlags |= StateExact ; III . Disabled = StateWQM | StateWWM ; continue ; } else { if ( Opcode == <STR_LIT> ) { LiveMaskQueries . push_back ( & MI ) ; } else if ( WQMOutputs ) { for ( const MachineOperand & MO : MI . defs ( ) ) { if ( ! MO . isReg ( ) ) continue ; unsigned Reg = MO . getReg ( ) ; if ( ! TRI -> isVirtualRegister ( Reg ) && TRI -> hasVectorRegisters ( TRI -> getPhysRegClass ( Reg ) ) ) { Flags = StateWQM ; break ; } } } if ( ! Flags ) continue ; } markInstruction ( MI , Flags , Worklist ) ; GlobalFlags |= Flags ; } } if ( GlobalFlags & StateWQM


<s> args_so_far = pack_cumulative_args ( & args_so_far_v ) ; regno = GP_ARG_FIRST ; for ( cur_arg = fnargs ; cur_arg != <NUM_LIT> ; cur_arg = next_arg ) { tree passed_type = DECL_ARG_TYPE ( cur_arg ) ; machine_mode passed_mode = TYPE_MODE ( passed_type ) ; rtx entry_parm ; if ( TREE_ADDRESSABLE ( passed_type ) ) { passed_type = build_pointer_type ( passed_type ) ; passed_mode = Pmode ; } entry_parm = iq2000_function_arg ( args_so_far , passed_mode , passed_type , true ) ; iq2000_function_arg_advance ( args_so_far , passed_mode , passed_type , true ) ; next_arg = DECL_CHAIN ( cur_arg ) ; if ( entry_parm && store_args_on_stack ) { if ( next_arg == <NUM_LIT> && DECL_NAME ( cur_arg ) && ( strcmp ( IDENTIFIER_POINTER ( DECL_NAME ( cur_arg ) ) , <STR_LIT> ) == <NUM_LIT> || strcmp ( IDENTIFIER_POINTER ( DECL_NAME ( cur_arg ) ) , <STR_LIT> ) == <NUM_LIT> ) ) { last_arg_is_vararg_marker = <NUM_LIT> ; break ; } else { int words ; gcc_assert ( GET_CODE ( entry_parm ) == REG ) ; if ( GET_MODE ( entry_parm ) == BLKmode ) words = ( int_size_in_bytes ( passed_type ) + <NUM_LIT> ) / <NUM_LIT> ; else words = ( GET_MODE_SIZE ( GET_MODE ( entry_parm ) ) + <NUM_LIT> ) / <NUM_LIT> ; regno = REGNO ( entry_parm ) + words - <NUM_LIT> ; } } else { regno = GP_ARG_LAST + <NUM_LIT> ; break ; } } next_arg_reg = iq2000_function_arg ( args_so_far , VOIDmode , void_type_node , true ) ; if ( next_arg_reg != <NUM_LIT> && GET_CODE ( next_arg_reg ) == PARALLEL ) { rtvec adjust = XVEC ( next_arg_reg , <NUM_LIT> ) ; int num = GET_NUM_ELEM ( adjust ) ; for ( i = <NUM_LIT> ; i < num ; i ++ ) { rtx pattern ; pattern = RTVEC_ELT ( adjust , i ) ; if ( GET_CODE ( pattern ) != SET || GET_CODE ( SET_SRC ( pattern ) ) != ASHIFT ) abort_with_insn ( pattern , <STR_LIT> ) ; PUT_CODE ( SET_SRC ( pattern ) , ASHIFTRT ) ; emit_insn ( pattern ) ; } } tsize = compute_frame_size ( get_frame_size ( ) ) ; if ( store_args_on_stack && ( stdarg_p ( fntype ) || last_arg_is_vararg_marker ) ) { int offset = ( regno - GP_ARG_FIRST ) * UNITS_PER_WORD ; rtx ptr = stack_pointer_rtx ; for ( ; regno <= GP_ARG_LAST ; regno ++ ) { if ( offset != <NUM_LIT> ) ptr = gen_rtx_PLUS ( Pmode , stack_pointer_rtx , GEN_INT ( offset ) ) ; emit_move_insn ( gen_rtx_MEM ( gpr_mode , ptr ) , gen_rtx_REG ( gpr_mode , regno ) ) ; offset += GET_MODE_SIZE ( gpr_mode ) ; } } if ( tsize > <NUM_LIT> ) { rtx tsize_rtx = GEN_INT ( tsize ) ; rtx adjustment_rtx , dwarf_pattern ; rtx_insn * insn ; if ( tsize


<s> const <ISA_LIT>TargetLowering * getTargetLowering ( ) const


<s> { rtx tmp = gen_reg_rtx ( SImode ) ; start_sequence ( ) ; if ( pm & PM_read ) emit_insn ( gen_sel_truesi ( tmp , reg , GEN_INT ( <NUM_LIT> ) , const0_rtx ) ) ; emit_insn ( nvptx_gen_wcast ( tmp , pm , rep , data ) ) ; if ( pm & PM_write ) emit_insn ( gen_rtx_SET ( reg , gen_rtx_NE ( BImode , tmp , const0_rtx ) ) ) ; res = get_insns ( ) ; end_sequence ( ) ; } break ; default : { rtx addr = data -> ptr ; if ( ! addr ) { unsigned align = GET_MODE_ALIGNMENT ( mode ) / BITS_PER_UNIT ; if ( align > worker_bcast_align ) worker_bcast_align = align ; data -> offset = ( data -> offset + align - <NUM_LIT> ) & ~ ( align - <NUM_LIT> ) ; addr = data -> base ; if ( data -> offset ) addr = gen_rtx_PLUS ( Pmode , addr , GEN_INT ( data -> offset ) ) ; } addr = gen_rtx_MEM ( mode , addr )


<s> auto Res = std :: make_unique < <ISA_LIT>Operand > ( OpKind ::


<s> context -> bsp = context -> regstk_top = ( unsigned long ) bsp ; context -> psp = ( unsigned long ) psp ; context -> rp = ( unsigned long ) rp ; asm ( <STR_LIT> : <STR_LIT> ( context -> sp ) ) ; asm ( <STR_LIT> : <STR_LIT> ( context -> pr ) ) ; context -> pri_unat_loc = & context -> initial_unat ; if ( uw_frame_state_for ( context , & fs ) != _URC_NO_REASON ) abort


<s> return __builtin_mve_vdupq_n_sv8hi (