<s> Type * OpPtrTy = PointerType :: getUnqual ( II . getArgOperand ( <NUM_LIT> ) -> getType ( ) ) ; Value * Ptr = IC . Builder . CreateBitCast ( II . getArgOperand ( <NUM_LIT> ) , OpPtrTy ) ; return new StoreInst ( II . getArgOperand ( <NUM_LIT> ) , Ptr , false , Align ( <NUM_LIT> ) ) ; } break ; case <STR_LIT> : case <STR_LIT> : { Type * OpPtrTy = PointerType :: getUnqual ( II . getArgOperand ( <NUM_LIT> ) -> getType ( ) ) ; Value * Ptr = IC . Builder . CreateBitCast ( II . getArgOperand ( <NUM_LIT> ) , OpPtrTy ) ; return new StoreInst ( II . getArgOperand ( <NUM_LIT> ) , Ptr , false , Align ( <NUM_LIT> ) ) ; } case <STR_LIT> : if ( Constant * Mask = dyn_cast < Constant > ( II . getArgOperand ( <NUM_LIT> ) ) ) { assert ( cast < FixedVectorType > ( Mask -> getType ( ) ) -> getNumElements ( ) == <NUM_LIT> && <STR_LIT> ) ; bool AllEltsOk = true ; for ( unsigned i = <NUM_LIT> ; i != <NUM_LIT> ; ++ i ) { Constant * Elt = Mask -> getAggregateElement ( i ) ; if ( ! Elt || ! ( isa < ConstantInt > ( Elt ) || isa < UndefValue > ( Elt ) ) ) { AllEltsOk = false ; break ; } } if ( AllEltsOk ) { Value * Op0 = IC . Builder . CreateBitCast ( II . getArgOperand ( <NUM_LIT> ) , Mask -> getType ( ) ) ; Value * Op1 = IC . Builder . CreateBitCast ( II . getArgOperand ( <NUM_LIT> ) , Mask -> getType ( ) ) ; Value * Result = UndefValue :: get ( Op0 -> getType ( ) ) ; Value * ExtractedElts [ <NUM_LIT> ] ; memset ( ExtractedElts , <NUM_LIT> , sizeof ( ExtractedElts ) ) ; for ( unsigned i = <NUM_LIT> ; i != <NUM_LIT> ;


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: CreateImm ( CoprocOption . Val


<s> const MachineFrameInfo & MFI = MF -> getFrameInfo ( ) ; const TargetRegisterInfo * TRI = MF -> getSubtarget ( ) . getRegisterInfo ( ) ; const std :: vector < CalleeSavedInfo > & CSI = MFI . getCalleeSavedInfo ( ) ; unsigned CPURegSize = TRI -> getRegSizeInBits ( <STR_LIT> ) / <NUM_LIT> ; for ( const auto & I : CSI ) { unsigned Reg = I . getReg ( ) ; unsigned RegNum = TRI -> getEncodingValue ( Reg


<s> tmp1 = simplify_gen_subreg ( HImode , operands [ <NUM_LIT> ] , mode , <NUM_LIT> ) ; tmp2 = simplify_gen_subreg ( QImode , operands [ <NUM_LIT> ] , mode , <NUM_LIT> ) ; emit_insn ( gen_udivmodhiqi3 ( tmp0 , tmp1 , tmp2 ) ) ; if ( signed_p ) { div = gen_rtx_DIV ( SImode , operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ; mod = gen_rtx_MOD ( SImode , operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ; } else { div = gen_rtx_UDIV ( SImode , operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ; mod = gen_rtx_UMOD ( SImode , operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ; } tmp1 = gen_rtx_ZERO_EXTRACT ( mode , tmp0 , GEN_INT ( <NUM_LIT> ) , GEN_INT ( <NUM_LIT> ) ) ; if ( REG_P ( operands [ <NUM_LIT> ] ) ) insn = emit_move_insn ( operands [ <NUM_LIT> ] , tmp1 ) ; else { scratch = gen_reg_rtx ( mode ) ; emit_move_insn ( scratch , tmp1


<s> x = gen_rtx_AND ( mode , before , val ) ; emit_insn ( gen_rtx_SET ( val , x ) ) ; x = gen_rtx_NOT ( mode , val ) ; } else x = gen_rtx_fmt_ee ( code , mode , before , val ) ; if ( after ) emit_insn ( gen_rtx_SET ( after , copy_rtx ( x ) ) ) ; emit_insn ( gen_rtx_SET ( scratch , x ) ) ; emit_store_conditional ( mode , cond , mem , scratch ) ; x = gen_rtx_EQ ( DImode , cond ,


<s> machine_mode mode ; int unsigned_p ; mode = TYPE_MODE ( valtype ) ; mode = promote_function_mode ( valtype , mode , & unsigned_p ,


<s> MCAsmParser & Parser = getParser ( ) ; const AsmToken & Tok = Parser . getTok ( ) ; if ( ! Tok . is ( AsmToken :: Identifier ) ) return MatchOperand_NoMatch ; unsigned RegNum = matchRegisterNameAlias ( Tok . getString ( ) . lower ( ) , false ) ; MCContext & Ctx = getContext ( ) ; const MCRegisterInfo * RI = Ctx . getRegisterInfo ( ) ; if ( ! RI -> getRegClass ( <STR_LIT> ) . contains ( RegNum ) ) return MatchOperand_NoMatch ; SMLoc S = getLoc ( )


<s> return IsConstantImm && isShiftedUInt < <NUM_LIT> , <NUM_LIT> > ( Imm ) && ( Imm != <NUM_LIT> )

&& VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ;


<s> Policy . OnlyBottomUp = false ; Policy . ShouldTrackPressure


<s> return <ISA_LIT>ProcFamily == IntelGLM || <ISA_LIT>ProcFamily == IntelGLP


<s> virtual const TargetSubtargetInfo * getSubtargetImpl ( const Function & ) const override { return & Subtarget


<s> if ( Value != <NUM_LIT> && Value != <NUM_LIT> ) { reportParseError ( <STR_LIT> ) ; return false ; } if ( Value == <NUM_LIT> ) { if ( ! isABI_O32 ( ) ) { reportParseError ( <STR_LIT> + Directive + <STR_LIT> ) ; return false ; } FpABI = <STR_LIT> :: S32 ; if ( ModuleLevelOptions ) { clearModuleFeatureBits ( <STR_LIT> , <STR_LIT> ) ; clearModuleFeatureBits ( <STR_LIT> , <STR_LIT> ) ; } else { clearFeatureBits ( <STR_LIT> , <STR_LIT> ) ; clearFeatureBits ( <STR_LIT> , <STR_LIT> ) ; } } else { FpABI = <STR_LIT> :: S64 ; if ( ModuleLevelOptions ) { clearModuleFeatureBits ( <STR_LIT> ,


<s> int reverse_regs ; int invert_const ; int invert_reg ; int unsignedp ; } ; static struct cmp_info info [ ( int ) ITEST_MAX ] = { { EQ , xtensa_b4const_or_zero , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { NE , xtensa_b4const_or_zero , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { LT , xtensa_b4const_or_zero , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { GE , xtensa_b4const_or_zero , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { LT , xtensa_b4const_or_zero , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { GE , xtensa_b4const_or_zero , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { LTU , xtensa_b4constu , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { GEU , xtensa_b4constu , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { LTU , xtensa_b4constu , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { GEU , xtensa_b4constu , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , } ; enum internal_test test ; machine_mode mode ; struct cmp_info * p_info ; test = map_test_to_internal_test ( test_code ) ; gcc_assert ( test != ITEST_MAX ) ; p_info = & info [ ( int ) test ] ; mode = GET_MODE ( cmp0 ) ; if ( mode == VOIDmode ) mode = GET_MODE ( cmp1 ) ; if ( GET_CODE ( cmp1 ) == CONST_INT ) { HOST_WIDE_INT value = INTVAL ( cmp1 ) ; unsigned HOST_WIDE_INT uvalue = ( unsigned HOST_WIDE_INT ) value ; if ( ( p_info -> unsignedp ? ( uvalue + p_info -> const_add > uvalue ) : ( value + p_info -> const_add > value ) ) != ( p_info -> const_add > <NUM_LIT> ) ) { cmp1 = force_reg ( mode , cmp1 ) ; } else if ( ! ( p_info -> const_range_p ) ( value


<s> RegisterRef SrcR = { Op1 . getReg ( ) , Op1 . getSubReg ( ) } ; auto FS = DefM . find ( SrcR ) ; if ( FS == DefM . end ( ) || FS -> second . empty ( ) ) return ; Copies . push_back ( SA . Id ) ; RDefMap [ SrcR ] [ SA . Id ] =


<s> <ISA_LIT>Shuffler :: <ISA_LIT>Shuffler ( MCInstrInfo const & MCII , MCSubtargetInfo const & STI ) : MCII (


<s> VA . convertToReg ( <STR_LIT> ) ; } else if ( ! Subtarget . hasSSE2 ( ) && <STR_LIT> . contains ( VA . getLocReg ( ) ) && ValVT == <STR_LIT> ) { errorUnsupported ( DAG , dl , <STR_LIT> ) ; VA . convertToReg ( <STR_LIT> ) ; } if ( VA . getLocReg ( ) == <STR_LIT> || VA . getLocReg ( ) == <STR_LIT> ) { if ( isScalarFPTypeInSSEReg ( VA . getValVT ( ) ) ) ValToCopy = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , ValToCopy ) ; RetVals . push_back ( std :: make_pair ( VA . getLocReg ( ) , ValToCopy ) ) ; continue ; } if ( Subtarget . is64Bit ( ) ) { if ( ValVT == <STR_LIT> ) { if ( VA . getLocReg ( ) == <STR_LIT> || VA . getLocReg ( ) == <STR_LIT> ) { ValToCopy = DAG . getBitcast ( <STR_LIT> , ValToCopy ) ; ValToCopy = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , ValToCopy ) ; if ( ! Subtarget . hasSSE2 ( ) ) ValToCopy = DAG . getBitcast ( <STR_LIT> , ValToCopy ) ; } } } if ( VA . needsCustom ( ) ) { assert ( VA . getValVT ( ) == <STR_LIT> && <STR_LIT> ) ; Passv64i1ArgInRegs ( dl , DAG , ValToCopy , RetVals , VA , RVLocs [ ++ I ] , Subtarget ) ; if ( ShouldDisableCalleeSavedRegister ) MF . getRegInfo ( ) . disableCalleeSavedRegister ( RVLocs [ I ] . getLocReg ( ) ) ; } else { RetVals . push_back ( std :: make_pair ( VA . getLocReg ( ) , ValToCopy ) ) ; } } SDValue Flag ; SmallVector < SDValue , <NUM_LIT> > RetOps ; RetOps . push_back ( Chain ) ; RetOps . push_back ( DAG . getTargetConstant ( FuncInfo -> getBytesToPopOnReturn ( ) , dl , <STR_LIT> ) ) ; for ( auto & RetVal : RetVals ) { if ( RetVal . first == <STR_LIT> || RetVal . first == <STR_LIT> ) { RetOps . push_back ( RetVal . second ) ; continue ; } Chain = DAG . getCopyToReg ( Chain , dl , RetVal . first , RetVal . second , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( RetVal . first , RetVal . second . getValueType (


<s> rtx func_rtx = current_function_decl ; register enum rtx_code code ; char * mtype = <STR_LIT> ; if ( x ) { code = GET_CODE ( x ) ; if ( code == SIGN_EXTEND ) x = XEXP ( x , <NUM_LIT> ) , code = GET_CODE ( x ) ; switch ( GET_MODE ( x ) ) { case SFmode : mtype = <STR_LIT>


<s> if ( SelectAddressRegReg ( N , Disp , Base , DAG ) ) return false ; if ( N . getOpcode ( ) == <STR_LIT> ) { short imm = <NUM_LIT> ; if ( isIntS16Immediate ( N . getOperand ( <NUM_LIT> ) , imm ) && ( ! Aligned || ( imm & <NUM_LIT> ) == <NUM_LIT> ) ) { Disp = DAG . getTargetConstant ( imm , N . getValueType ( ) ) ; if ( FrameIndexSDNode * FI = dyn_cast < FrameIndexSDNode > ( N . getOperand ( <NUM_LIT> ) ) ) { Base = DAG . getTargetFrameIndex ( FI -> getIndex ( ) , N . getValueType ( ) ) ; fixupFuncForFI ( DAG , FI -> getIndex ( ) , N . getValueType ( ) ) ; } else { Base = N . getOperand ( <NUM_LIT> ) ; } return true ; } else if ( N . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) { assert ( ! cast < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) && <STR_LIT> ) ; Disp = N . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ; assert ( Disp . getOpcode ( ) == <STR_LIT> || Disp . getOpcode ( ) == <STR_LIT> || Disp . getOpcode ( ) == <STR_LIT> || Disp . getOpcode ( ) == <STR_LIT> ) ; Base = N . getOperand ( <NUM_LIT> ) ; return true


<s> machine_mode mode = GET_MODE ( dst ) ; machine_mode int_mode = mode_for_size ( GET_MODE_BITSIZE ( mode ) , MODE_INT , <NUM_LIT> ) ; rtx reg ; gcc_assert ( GET_MODE ( src ) == TImode ) ; reg = int_mode != mode ? gen_reg_rtx ( int_mode ) : dst ; emit_insn ( gen_rtx_SET ( reg , gen_rtx_TRUNCATE ( int_mode , gen_rtx_LSHIFTRT ( TImode , src , GEN_INT ( int_mode == DImode ? <NUM_LIT> : <NUM_LIT> ) ) ) ) ) ; if ( int_mode != mode ) { reg = simplify_gen_subreg ( mode , reg , int_mode , <NUM_LIT> ) ; emit_move_insn ( dst


<s> return new Emitter < JITCodeEmitter > ( TM


<s> const char * getPassName ( ) const override { return <STR_LIT>


<s> while ( link ) { if ( DF_REF_IS_ARTIFICIAL ( link -> ref ) ) insn_entry [ INSN_UID ( insn ) ] . is_live_out = <NUM_LIT> ; if ( DF_REF_INSN_INFO ( link -> ref ) ) { rtx use_insn = DF_REF_INSN ( link


<s> static scalar_int_mode sparc_cstore_mode ( enum insn_code icode ATTRIBUTE_UNUSED ) { return ( TARGET_ARCH64 ? DImode


<s> static void ia64_output_function_end_prologue ( FILE * file ) { if ( ! flag_unwind_tables && ( ! flag_exceptions || USING_SJLJ_EXCEPTIONS ) )


<s> unsigned Op = i ; for ( unsigned e = MI . getNumOperands ( ) ; i

!= e ; ++ i ) MI . RemoveOperand ( Op ) ;


<s> return <ISA_LIT>Operand :: CreateImm ( <NUM_LIT> , SMLoc (

) , <ISA_LIT>Operand :: ImmTyDppBankMask ) ;


<s> bool <ISA_LIT>InstrInfo :: reverseBranchCondition ( SmallVectorImpl < MachineOperand > & Cond ) const { <STR_LIT> CC = static_cast < <STR_LIT> > ( Cond [ <NUM_LIT> ] .


<s> void <ISA_LIT>InstPrinter :: printT2AddrModeImm8OffsetOperand ( const MCInst * MI , unsigned OpNum , raw_ostream & O ) { const MCOperand & MO1 = MI -> getOperand (


<s> const MCConstantExpr * MCE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; if ( ! MCE )


<s> if ( GET_CODE ( unspec ) == UNSPEC && ! nios2_large_offset_p ( XINT ( unspec , <NUM_LIT> ) ) && offset != const0_rtx ) { rtx reg = force_reg ( Pmode , XEXP ( x , <NUM_LIT> ) ) ; unspec = copy_rtx ( unspec ) ; XVECEXP ( unspec , <NUM_LIT> , <NUM_LIT> ) = plus_constant ( Pmode , XVECEXP ( unspec , <NUM_LIT> , <NUM_LIT> ) , INTVAL ( offset ) ) ; x = gen_rtx_PLUS ( Pmode , reg , gen_rtx_CONST ( Pmode ,


<s> RegisterAsmInfo < <ISA_LIT>MCAsmInfo > Y (


<s> reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; if ( MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . hasSGPRInitBug ( ) ) { unsigned NumSGPRs = <STR_LIT> . getNumRegs ( ) ; unsigned Limit = <ISA_LIT>Subtarget :: FIXED_SGPR_COUNT_FOR_INIT_BUG -


<s> for ( MachineBasicBlock :: instr_iterator it = BB -> begin ( ) ; it != BB -> end ( ) ; it ++ ) { MachineInstr * insn =


<s> static enum loongarch_symbol_type loongarch_classify_symbol ( const_rtx x ) { if ( LABEL_REF_P ( x ) ) return SYMBOL_GOT_DISP ; gcc_assert ( SYMBOL_REF_P ( x ) ) ; if ( SYMBOL_REF_TLS_MODEL ( x ) ) return SYMBOL_TLS ; if ( SYMBOL_REF_P ( x )


<s> setAttributeItems ( Attribute , IntValue , StringValue , true


<s> return ( __m128 ) vec_vmrghw ( ( __v4sf


<s> static Target The<ISA_LIT>Target ; return The<ISA_LIT>Target


<s> int FI = PFI -> getFramePointerSaveIndex ( ) ; assert ( FI && <STR_LIT> ) ; MFI . setObjectOffset ( FI , LowerBound + MFI . getObjectOffset ( FI ) ) ; } if ( PFI -> usesPICBase ( ) ) { HasGPSaveArea = true ; int FI = PFI -> getPICBasePointerSaveIndex ( ) ; assert ( FI && <STR_LIT> ) ; MFI . setObjectOffset ( FI , LowerBound + MFI . getObjectOffset ( FI ) ) ; } const <ISA_LIT>RegisterInfo * RegInfo = Subtarget . getRegisterInfo ( ) ; if ( RegInfo -> hasBasePointer ( MF ) ) { HasGPSaveArea = true ; int FI = PFI -> getBasePointerSaveIndex ( ) ; assert ( FI && <STR_LIT> ) ; MFI . setObjectOffset ( FI , LowerBound + MFI . getObjectOffset ( FI ) ) ; } if ( HasGPSaveArea || HasG8SaveArea ) { for ( unsigned i = <NUM_LIT> , e = GPRegs . size ( ) ; i != e ; ++ i ) { int FI = GPRegs [ i ] . getFrameIdx ( ) ; MFI . setObjectOffset ( FI , LowerBound + MFI . getObjectOffset ( FI ) ) ; } for ( unsigned i = <NUM_LIT> , e = G8Regs . size ( ) ; i != e ; ++ i ) { int FI = G8Regs [ i ] . getFrameIdx ( ) ; MFI . setObjectOffset ( FI , LowerBound + MFI . getObjectOffset ( FI ) ) ; } unsigned MinReg = std :: min < unsigned > ( TRI -> getEncodingValue ( MinGPR ) , TRI -> getEncodingValue ( MinG8R ) ) ; if ( Subtarget . is<ISA_LIT>64 ( ) ) { LowerBound -= ( <NUM_LIT> - MinReg + <NUM_LIT> ) * <NUM_LIT> ; } else { LowerBound -= ( <NUM_LIT> - MinReg + <NUM_LIT> ) * <NUM_LIT> ; } } if ( spillsCR ( MF ) && ! ( Subtarget . is<ISA_LIT>64 ( ) && Subtarget . isSVR4ABI ( ) ) ) { for ( unsigned i = <NUM_LIT> , e = CSI . size ( ) ; i != e ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; if ( ( Subtarget . isSVR4ABI ( ) && Reg == <STR_LIT> ) || ( ! Subtarget . isSVR4ABI ( ) && ( <STR_LIT> . contains ( Reg ) || <STR_LIT> . contains ( Reg ) ) ) ) { int FI = CSI [ i ] . getFrameIdx ( ) ; MFI . setObjectOffset ( FI , LowerBound + MFI . getObjectOffset ( FI ) ) ; } } LowerBound -=


<s> <ISA_LIT>ELFStreamer ( MCContext & Context , MCAsmBackend & TAB , raw_pwrite_stream & OS , MCCodeEmitter * Emitter , bool IsThumb ) : MCELFStreamer ( Context , TAB , OS , Emitter ) , IsThumb ( IsThumb ) , MappingSymbolCounter ( <NUM_LIT> ) , LastEMS ( EMS_None ) { Reset (


<s> return __builtin_mve_vmulq_m_n_uv16qi ( __arm_vuninitializedq_u8 ( ) , __a ,


<s> Offset = CurDAG -> getTargetConstant ( <NUM_LIT> , ValTy ) ; get<ISA_LIT>16SPRefReg ( Parent , Alias ) ; return true ; } if ( Addr . getOpcode ( ) == <STR_LIT> ) { Base = Addr . getOperand ( <NUM_LIT> ) ; Offset = Addr . getOperand ( <NUM_LIT> ) ; return true ; } if ( TM . getRelocationModel ( ) != Reloc :: PIC_ ) { if ( ( Addr . getOpcode ( ) == <STR_LIT> || Addr . getOpcode ( ) == <STR_LIT> ) ) return false ; } if ( CurDAG -> isBaseWithConstantOffset ( Addr ) ) { ConstantSDNode * CN = dyn_cast < ConstantSDNode > ( Addr . getOperand ( <NUM_LIT> ) ) ; if ( isInt < <NUM_LIT> > ( CN -> getSExtValue ( ) ) ) { if ( FrameIndexSDNode * FIN = dyn_cast < FrameIndexSDNode > ( Addr . getOperand ( <NUM_LIT> ) ) ) { Base = CurDAG -> getTargetFrameIndex ( FIN -> getIndex ( ) , ValTy ) ; get<ISA_LIT>16SPRefReg ( Parent , Alias ) ; } else Base = Addr . getOperand ( <NUM_LIT> ) ; Offset = CurDAG -> getTargetConstant ( CN -> getZExtValue ( ) , ValTy ) ; return true ; } } if ( Addr . getOpcode ( ) == <STR_LIT>


<s> return ; case <STR_LIT> : O << <STR_LIT> ; return ; case <STR_LIT> : O << <STR_LIT> ; return ; case <STR_LIT> : O << <STR_LIT> ; return ; case <STR_LIT> : O << <STR_LIT> ; return ; case <STR_LIT> : O << <STR_LIT> ; return ; case <STR_LIT> : O << <STR_LIT> ; return ; case <STR_LIT> : O << <STR_LIT> ; return ; case <STR_LIT> : O << <STR_LIT> ; return ; case <STR_LIT> : O << <STR_LIT> ; return ; case <STR_LIT> : O << <STR_LIT> ; return ; default : break ; } char Type ; unsigned NumRegs ; if ( MRI . getRegClass ( <STR_LIT> ) . contains ( reg ) ) { Type = 'v' ; NumRegs = <NUM_LIT> ; } else if ( MRI . getRegClass ( <STR_LIT> ) . contains ( reg ) ) { Type = 's' ; NumRegs = <NUM_LIT> ; } else if ( MRI . getRegClass ( <STR_LIT> ) . contains ( reg ) ) { Type = 'v' ; NumRegs = <NUM_LIT> ; } else if ( MRI . getRegClass ( <STR_LIT> ) . contains ( reg ) ) { Type = 's' ; NumRegs = <NUM_LIT> ; } else if ( MRI . getRegClass ( <STR_LIT> ) . contains ( reg ) ) { Type = 'v' ; NumRegs = <NUM_LIT> ; } else if ( MRI . getRegClass ( <STR_LIT> ) . contains ( reg ) ) { Type = 's' ; NumRegs = <NUM_LIT> ; } else if ( MRI . getRegClass ( <STR_LIT> ) . contains ( reg ) ) { Type =


<s> bool isS16ImmX16 ( ) const { return Kind == Expression || ( Kind == Immediate && isInt < <NUM_LIT> > (

getImm ( ) ) && ( getImm ( ) & <NUM_LIT> ) == <NUM_LIT> ) ; }


<s> Opcode_t BccOpc = <STR_LIT> ; assert ( TBB && <STR_LIT> ) ; if ( ! Cond . empty ( ) && Cond [ <NUM_LIT> ] . isImm ( ) ) BccOpc = Cond [ <NUM_LIT> ] . getImm ( ) ; if ( ! FBB ) { if ( Cond . empty ( ) ) { MachineBasicBlock * NewTBB , * NewFBB ; SmallVector < MachineOperand , <NUM_LIT> > Cond ; MachineInstr * Term = MBB . getFirstTerminator ( ) ; if ( Term != MBB . end ( ) && isPredicated ( Term ) && ! AnalyzeBranch ( MBB , NewTBB , NewFBB , Cond , false ) ) { MachineBasicBlock * NextBB = std :: next ( MachineFunction :: iterator ( & MBB ) ) ; if ( NewTBB == NextBB ) { ReverseBranchCondition ( Cond ) ; RemoveBranch ( MBB ) ; return InsertBranch ( MBB , TBB , nullptr , Cond , DL ) ; } } BuildMI ( & MBB , DL , get ( BOpc ) ) . addMBB ( TBB ) ; } else if ( isEndLoopN ( Cond [ <NUM_LIT> ] . getImm ( ) ) ) { int EndLoopOp = Cond [ <NUM_LIT> ] . getImm ( ) ; assert ( Cond [ <NUM_LIT> ] . isMBB ( ) ) ; SmallPtrSet < MachineBasicBlock * , <NUM_LIT> > VisitedBBs ; MachineInstr * Loop = findLoopInstr ( TBB , EndLoopOp , VisitedBBs ) ; assert ( Loop != <NUM_LIT> && <STR_LIT> ) ; Loop -> getOperand ( <NUM_LIT> ) . setMBB ( TBB ) ; BuildMI ( & MBB , DL , get ( EndLoopOp ) ) . addMBB ( TBB ) ; } else if ( isNewValueJump ( Cond [ <NUM_LIT> ] . getImm ( )


<s> std :: pair < SDValue , SDValue > Vals = FP_TO_INTHelper ( Op , DAG , false , false ) ; SDValue FIST = Vals . first , StackSlot = Vals . second ; assert ( FIST . getNode ( ) && <STR_LIT> ) ; if ( StackSlot . getNode ( ) ) return DAG . getLoad ( Op . getValueType ( ) , Op . getDebugLoc ( ) , FIST , StackSlot , MachinePointerInfo ( )


<s> static std :: unique_ptr < <ISA_LIT>Operand > createToken


<s> if ( ! isOpcWithIntImmediate ( N -> getOperand ( <NUM_LIT> ) . getNode ( ) , <STR_LIT> , And_mask ) ) return false ; Opd0 = N -> getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ; uint64_t Srl_imm = <NUM_LIT> ; if ( ! isIntImmediate ( N -> getOperand ( <NUM_LIT> ) , Srl_imm ) ) return false ; unsigned BitWide = <NUM_LIT> - CountLeadingOnes_64 ( ~ ( And_mask >> Srl_imm ) ) ; if ( BitWide && isMask_64 ( And_mask >> Srl_imm ) ) { if ( N -> getValueType ( <NUM_LIT> )


<s> BuildMI ( * BB , Pos , dl , TII -> get ( LdOpc ) , Data ) . addReg ( AddrOut , RegState :: Define ) . addReg ( AddrIn ) . addImm ( <NUM_LIT> ) . add ( predOps ( <STR_LIT> ) ) ; } else if ( IsThumb1 ) { BuildMI ( * BB , Pos , dl , TII -> get ( LdOpc ) , Data ) . addReg ( AddrIn ) . addImm ( <NUM_LIT> ) . add ( predOps ( <STR_LIT> ) ) ; BuildMI ( * BB , Pos , dl , TII -> get ( <STR_LIT> ) , AddrOut ) . add ( t1CondCodeOp ( ) ) . addReg ( AddrIn ) . addImm ( LdSize ) . add ( predOps ( <STR_LIT> ) ) ; } else if


<s> EmitIMM ( const MCInst & MI , unsigned & CurByte , raw_ostream & OS ) const { switch ( MI . getOpcode ( ) ) { default : break


<s> StringRef getPassName ( ) const override { return


<s> if ( IsWin64 || ( F && F -> getCallingConv ( ) == CallingConv :: Win64 ) ) return & <STR_LIT> ; else if ( Is64Bit ) return & <STR_LIT> ; bool hasHipeCC = ( F ? F -> getCallingConv ( ) == CallingConv :: HiPE : false ) ; if ( hasHipeCC )


<s> return DecodeRegisterClass ( Inst , RegNo | <NUM_LIT> , Address


<s> } addPass ( create<ISA_LIT>NewValueJump ( ) ) ; addPass ( create<ISA_LIT>ExpandPredSpillCode ( get<ISA_LIT>TargetMachine ( ) ) ) ; addPass ( create<ISA_LIT>SplitTFRCondSets ( get<ISA_LIT>TargetMachine ( ) ) ) ; addPass ( create<ISA_LIT>Packetizer (


<s> <ISA_LIT>Subtarget & <ISA_LIT>Subtarget :: initializeSubtargetDependencies ( StringRef CPU , StringRef FS ) { if ( CPUString . empty ( ) ) CPUString = <STR_LIT> ; if ( CPUString == <STR_LIT> ) { <ISA_LIT>ArchVersion = V4 ; } else if ( CPUString


<s> if ( const RegisterBank * RB = RCOrRB . dyn_cast < const RegisterBank * > ( ) ) return

getRegClassForTypeOnBank ( MRI . getType ( MO . getReg ( ) ) , * RB ) ;


<s> if ( insn -> is_real ( ) && ( types & REAL_SET ) ) return true ; if ( insn -> is_phi ( ) && ( types & PHI_SET ) ) return true ; if ( insn -> is_bb_head ( ) &&


<s> assert ( VT . isFloatingPoint ( ) ) ; return


<s> SmallVector < CCValAssign , <NUM_LIT> > ArgLocs ; CCState CCInfo ( CallConv , isVarArg , DAG . getMachineFunction ( ) , ArgLocs , * DAG . getContext ( ) ) ; if ( Info -> getShaderType ( ) == ShaderType :: PIXEL && ( Info -> P<ISA_LIT>nputAddr & <NUM_LIT> ) == <NUM_LIT> ) { Info -> P<ISA_LIT>nputAddr |= <NUM_LIT> ; CCInfo . AllocateReg ( AMDGPU :: VGPR0 ) ; CCInfo . AllocateReg ( AMDGPU :: VGPR1 ) ; } if ( Info -> getShaderType ( ) == ShaderType :: COMPUTE ) { Info -> NumUserSGPRs = <NUM_LIT> ; unsigned InputPtrReg = TRI -> getPreloadedValue ( MF , <ISA_LIT>RegisterInfo :: INPUT_PTR ) ; unsigned InputPtrRegLo = TRI -> getPhysRegSubReg ( InputPtrReg , & AMDGPU :: SReg_32RegClass , <NUM_LIT> ) ; unsigned InputPtrRegHi = TRI -> getPhysRegSubReg ( InputPtrReg , & AMDGPU :: SReg_32RegClass , <NUM_LIT> ) ; unsigned ScratchPtrReg = TRI -> getPreloadedValue ( MF , <ISA_LIT>RegisterInfo :: SCRATCH_PTR ) ; unsigned ScratchPtrRegLo = TRI -> getPhysRegSubReg ( ScratchPtrReg , & AMDGPU :: SReg_32RegClass , <NUM_LIT> ) ; unsigned ScratchPtrRegHi = TRI -> getPhysRegSubReg ( ScratchPtrReg , & AMDGPU :: SReg_32RegClass , <NUM_LIT> ) ; CCInfo . AllocateReg ( InputPtrRegLo ) ; CCInfo . AllocateReg ( InputPtrRegHi ) ; CCInfo . AllocateReg ( ScratchPtrRegLo ) ; CCInfo . AllocateReg ( ScratchPtrRegHi ) ; MF . addLiveIn ( InputPtrReg , & AMDGPU :: SReg_64RegClass ) ; MF . addLiveIn ( ScratchPtrReg , & AMDGPU :: SReg_64RegClass ) ; } if ( Info -> getShaderType ( ) == ShaderType :: COMPUTE ) { getOriginalFunctionArgs ( DAG , DAG . getMachineFunction ( ) . getFunction ( ) , Ins , Splits ) ; } AnalyzeFormalArguments ( CCInfo , Splits ) ; for ( unsigned i = <NUM_LIT> , e = Ins . size ( ) , ArgIdx = <NUM_LIT> ; i != e ; ++ i ) { const <STR_LIT> & Arg = Ins [ i ] ; if ( Skipped [ i ] ) { InVals . push_back ( DAG . getUNDEF ( Arg . VT ) ) ; continue ; } CCValAssign & VA = ArgLocs [ ArgIdx ++ ] ; EVT VT = VA . getLocVT ( ) ; if ( VA . isMemLoc ( ) ) { VT = Ins [ i ] . VT ; EVT MemVT = Splits [ i ] . VT ; const unsigned Offset = <NUM_LIT> + VA . getLocMemOffset ( ) ; SDValue Arg = LowerParameter ( DAG , VT , MemVT , DL , DAG . getRoot ( ) , Offset , Ins [ i ] . Flags . isSExt ( ) ) ; const PointerType * ParamTy = dyn_cast < PointerType > ( FType -> getParamType ( Ins [ i ] . OrigArgIndex ) ) ; if ( Subtarget -> getGeneration ( ) == AMDGPUSubtarget :: SOUTHERN_ISLANDS && ParamTy && ParamTy -> getAddressSpace ( ) == <STR_LIT> ) { Arg = DAG . getNode ( <STR_LIT> , DL , Arg . getValueType (

) , Arg , DAG . getValueType ( <STR_LIT> ) ) ;


<s> using namespace llvm :: <STR_LIT> ; SMLoc Loc ; int64_t GroupSize ; if ( ! parseSwizzleOperand ( GroupSize , <NUM_LIT> , <NUM_LIT> , <STR_LIT> , Loc ) ) { return false ; } if ( ! isPowerOf2_64 ( GroupSize ) ) { Error ( Loc , <STR_LIT> ) ; return


<s> return LowerNeonVSTIntrinsic ( Op , DAG , <STR_LIT> , <NUM_LIT> ) ; case <STR_LIT> : return LowerNeonVSTIntrinsic ( Op , DAG , <STR_LIT> , <NUM_LIT> ) ; case <STR_LIT> : return LowerNeonVSTIntrinsic ( Op , DAG , <STR_LIT> , <NUM_LIT> ) ; default : return


<s> MCObjectWriter * llvm :: create<ISA_LIT>ELFObjectWriter ( raw_pwrite_stream & OS , uint8_t OSABI , bool Is64Bit ) { MCELFObjectTargetWriter * MOTW = new <ISA_LIT>ELFObjectWriter ( OSABI , Is64Bit ) ; return createELFObjectWriter ( MOTW , OS ,


<s> if ( TARGET_64BIT ) fprintf ( asm_out_file , <STR_LIT> , direction , reg_names [ gpreg ] , reg_names [ fpreg ] ) ; else if ( ISA_HAS_MXHC1 ) { fprintf ( asm_out_file , <STR_LIT> , direction , reg_names [ gpreg + TARGET_BIG_ENDIAN ] , reg_names [ fpreg ] ) ; fprintf ( asm_out_file , <STR_LIT> , direction , reg_names [ gpreg + TARGET_LITTLE_ENDIAN ] , reg_names [ fpreg ] ) ; } else if ( TARGET_FLOATXX && direction == 't' ) { fprintf ( asm_out_file , <STR_LIT> , reg_names [ gpreg ] ) ; fprintf ( asm_out_file , <STR_LIT> , reg_names [ gpreg + <NUM_LIT> ] ) ; fprintf ( asm_out_file , <STR_LIT> , reg_names [ fpreg ] ) ; } else if ( TARGET_FLOATXX && direction == 'f' ) { fprintf ( asm_out_file , <STR_LIT> , reg_names [ fpreg ] ) ; fprintf ( asm_out_file , <STR_LIT> , reg_names [ gpreg ] ) ; fprintf ( asm_out_file , <STR_LIT> , reg_names [ gpreg + <NUM_LIT> ] ) ; } else { fprintf ( asm_out_file , <STR_LIT> , direction , reg_names [ gpreg


<s> void addAbsMemOperands ( MCInst & Inst , unsigned N ) const { assert ( ( N == <NUM_LIT> ) &&


<s> bool hasExtXfalthalf ( ) const { return HasExtXfalthalf


<s> Ops . push_back ( CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ) ; Ops . push_back ( CurDAG -> getRegister ( <NUM_LIT> ,


<s> const Function & F = MF . getFunction ( ) ; unsigned StackProbeSize = <NUM_LIT> ; if ( F . hasFnAttribute ( <STR_LIT> ) ) F . getFnAttribute ( <STR_LIT> ) . getValueAsString ( ) .

getAsInteger ( <NUM_LIT> , StackProbeSize ) ;


<s> return DAG . getStore ( SD -> getChain ( ) , SDLoc ( SD ) , Tr , SD -> getBasePtr ( ) , SD -> getPointerInfo ( ) , SD -> getAlignment (

) , SD -> getMemOperand ( ) -> getFlags ( ) ) ;


<s> unsigned Idx = WhichResult ; for ( unsigned i = <NUM_LIT> ; i != Half ; ++ i ) { int MIdx = M [ i + j * Half ] ; if ( MIdx >= <NUM_LIT> && ( unsigned ) MIdx != Idx )


<s> if ( mode == SFmode ) vmode = V4SFmode ; else if ( mode == DFmode ) vmode = V2DFmode ; else vmode = mode ; mask = ix86_build_signbit_mask ( vmode , VECTOR_MODE_P ( mode ) , false ) ; if ( ! VECTOR_MODE_P ( mode ) ) { rtx tmp = gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( <NUM_LIT> , const0_rtx ) ) ; tmp = gen_rtx_VEC_SELECT ( mode , mask , tmp ) ; mask = gen_reg_rtx ( mode


<s> static void ReplaceINTRINSIC_W_CHAIN ( SDNode * N , SelectionDAG & DAG , SmallVectorImpl < SDValue > & Results ) { SDValue Chain = N -> getOperand ( <NUM_LIT> ) ; SDValue Intrin = N -> getOperand ( <NUM_LIT> ) ; DebugLoc DL = N -> getDebugLoc ( ) ; unsigned IntrinNo = cast < ConstantSDNode > ( Intrin . getNode ( ) ) -> getZExtValue ( ) ; switch ( IntrinNo ) { default : return ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { EVT ResVT = N -> getValueType ( <NUM_LIT> ) ; if ( ResVT . isVector ( ) ) { unsigned NumElts = ResVT . getVectorNumElements ( ) ; EVT EltVT = ResVT . getVectorElementType ( ) ; bool NeedTrunc = false ; if ( EltVT . getSizeInBits ( ) < <NUM_LIT> ) { EltVT = <STR_LIT> ; NeedTrunc = true ; } unsigned Opcode = <NUM_LIT> ; SDVTList LdResVTs ; switch ( NumElts ) { default : return ; case <NUM_LIT> : switch ( IntrinNo ) { default : return ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Opcode = <STR_LIT> ; break ; } LdResVTs = DAG . getVTList ( EltVT , EltVT , <STR_LIT> ) ; break ; case <NUM_LIT> : { switch ( IntrinNo ) { default : return ; case <STR_LIT> : case <STR_LIT>


<s> testreg = SET_DEST ( XVECEXP ( PATTERN ( loop -> loop_end ) , <NUM_LIT> , <NUM_LIT> ) ) ; if ( GET_CODE ( testreg ) == SCRATCH ) testreg = loop -> iter_reg ; else emit_insn_before ( gen_movsi ( testreg , loop -> iter_reg ) , loop -> loop_end ) ; test = gen_rtx_NE ( VOIDmode , testreg , const0_rtx ) ; insn = emit_jump_insn_before ( gen_cbranchsi4 ( test , testreg , const0_rtx ,

loop -> start_label ) , loop -> loop_end ) ;


<s> case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : SSECC = <NUM_LIT> ; Unsigned = true ; break ; case <STR_LIT> : Swap = true ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : SSECC = <NUM_LIT> ; Unsigned = true ; break ; case <STR_LIT> : SSECC = <NUM_LIT> ; Unsigned = true ; break ; case <STR_LIT> : Swap = true ; SSECC = <NUM_LIT> ; break ; case <STR_LIT> : Unsigned = true ; case <STR_LIT> : SSECC = <NUM_LIT> ; break ; } if ( Swap ) std :: swap ( Op0


<s> bool isAligned = MMOBegin != MMOEnd && ( * MMOBegin ) -> getAlignment ( ) >= Alignment ; unsigned Opc = getStoreRegOpcode ( SrcReg , RC , isAligned , Subtarget ) ; DebugLoc DL ; MachineInstrBuilder MIB = BuildMI ( MF , DL , get ( Opc ) ) ; for ( unsigned i = <NUM_LIT> , e = Addr . size ( ) ; i != e ; ++ i ) MIB . add ( Addr [ i ] ) ; MIB . addReg ( SrcReg , getKillRegState


<s> TargetLowering :: ConstraintWeight <ISA_LIT>TargetLowering :: getSingleConstraintMatchWeight ( AsmOperandInfo &

info , const char * constraint ) const {


<s> int <ISA_LIT>FrameLowering :: getNonLocalFrameIndexReference ( const MachineFunction & MF , int FI ) const { return getSEHFrameIndexOffset ( MF ,


<s> ++ MemOpsEmitted ; return static_cast < uint64_t > ( MO . getImm ( ) ) ; } if ( MO . isExpr ( ) ) { unsigned ByteOffs = MemOpsEmitted ++ == <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ; Fixups . push_back ( MCFixup :: create ( ByteOffs , MO . getExpr ( ) , ( MCFixupKind ) Kind , MI . getLoc ( ) ) ) ; assert ( Fixups . size ( ) <= <NUM_LIT>


<s> if ( Reg == <STR_LIT> ) return MachineInstrBuilder ( ) ; bool IsStore = MI -> mayStore ( ) ; MachineRegisterInfo & MRI = MF -> getRegInfo ( ) ; auto * TRI = static_cast < const <ISA_LIT>RegisterInfo * > ( MRI . getTargetRegisterInfo ( ) ) ; unsigned Dst = IsStore ? Reg : ValueReg ; unsigned Src = IsStore ? ValueReg : Reg ; unsigned Opc = ( IsStore ^ TRI -> isVGPR ( MRI , Reg ) ) ? <STR_LIT> : <STR_LIT> ; auto MIB = BuildMI ( MBB , MI , MI -> getDebugLoc ( ) , TII -> get ( Opc ) , Dst ) . addReg


<s> if ( TARGET_SPE && SPE_VECTOR_MODE ( mode ) ) return true ; else if ( VECTOR_MEM_ALTIVEC_OR_VSX_P ( mode ) && ! FLOAT128_IEEE_P ( mode )


<s> <ISA_LIT>II :: OpType getDataType ( ) const { assert ( Kind == OpKind :: DataType


<s> MCELFStreamer :: EmitValueImpl ( Value , Size , AddrSpace


<s> SDNode * U = * ExtVal -> use_begin ( ) ; if ( ( U -> getOpcode ( ) == <STR_LIT> || U -> getOpcode ( ) == <STR_LIT> || U -> getOpcode ( ) == <STR_LIT> || U -> getOpcode ( ) == <STR_LIT> ) ) return false ; return true


<s> unsigned AluInstCount = <NUM_LIT> ; for ( MachineBasicBlock :: iterator E = MBB . end ( ) ; I != E ; ++ I ) { if ( IsTrivialInst ( I ) ) continue ; if ( ! isALU ( I ) ) break ; if ( AluInstCount > TII -> getMaxAlusPerClause ( ) ) break ; if ( I -> getOpcode ( ) == AMDGPU :: PRED_X ) { if ( AluInstCount > <NUM_LIT> ) break ; if ( TII -> getFlagOp ( I ) . getImm ( ) & MO_FLAG_PUSH ) PushBeforeModifier = true ; AluInstCount ++ ; continue ; } if ( TII -> mustBeLastInClause ( I -> getOpcode ( ) ) ) { I ++ ; break ; } if ( ! canClauseLocalKillFitInClause ( AluInstCount , KCacheBanks , I , E ) ) break ; if ( ! SubstituteKCacheBank ( I , KCacheBanks ) ) break ; AluInstCount += OccupiedDwords ( I ) ; } unsigned Opcode = PushBeforeModifier ? AMDGPU ::


<s> static std :: unique_ptr < <ISA_LIT>Operand > CreateRegList ( SmallVectorImpl < unsigned > & Regs , SMLoc StartLoc , SMLoc EndLoc , <ISA_LIT>AsmParser & Parser ) { assert ( Regs . size ( ) > <NUM_LIT> && <STR_LIT> ) ; auto Op = std :: make_unique < <ISA_LIT>Operand > ( k_RegList


<s> static bool isKImmOperand ( const <ISA_LIT>InstrInfo * TII , const MachineOperand & Src ) { return isInt < <NUM_LIT> > ( Src . getImm ( ) )

&& ! TII -> isInlineConstant ( Src , <NUM_LIT> ) ;


<s> SDValue ValV = Op . getOperand ( <NUM_LIT> ) ; SDValue IdxV = Op . getOperand ( <NUM_LIT> ) ; MVT ElemTy = ty ( VecV ) . getVectorElementType ( ) ; unsigned ElemWidth = ElemTy . getSizeInBits ( ) ; assert ( ElemWidth >= <NUM_LIT> && ElemWidth <= <NUM_LIT> ) ; ( void ) ElemWidth ; auto InsertWord = [ & DAG , & dl , this ] ( SDValue VecV , SDValue ValV , SDValue ByteIdxV ) { MVT VecTy = ty ( VecV ) ; unsigned HwLen = Subtarget . getVectorLength ( ) ; SDValue MaskV = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , { ByteIdxV , DAG . getConstant ( - <NUM_LIT> , dl , <STR_LIT> ) } ) ; SDValue RotV = DAG . getNode ( <STR_LIT> , dl , VecTy , { VecV , MaskV } ) ; SDValue InsV = DAG . getNode ( <STR_LIT> , dl , VecTy , { RotV , ValV } ) ; SDValue SubV = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , { DAG . getConstant ( HwLen / <NUM_LIT> , dl , <STR_LIT> ) , MaskV } ) ; SDValue TorV = DAG . getNode ( <STR_LIT> , dl , VecTy , { InsV , SubV } ) ; return TorV ; } ; SDValue ByteIdx = convertToByteIndex ( IdxV , ElemTy , DAG ) ; if ( ElemTy == <STR_LIT> ) return InsertWord ( VecV , ValV , ByteIdx ) ; SDValue WordIdx = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , { ByteIdx , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) } ) ; SDValue Ex0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , { opCastElem ( VecV , <STR_LIT> , DAG ) , WordIdx } ) ; SDValue Ext = LowerHvxExtractElement ( Ex0 , DAG ) ; SDValue SubIdx = getIndexInWord32 ( IdxV , ElemTy ,


<s> const <ISA_LIT>SelectionDAGInfo * getSelectionDAGInfo (


<s> static inline int vec_any_nle ( vec_float4


<s> gcc_assert ( preferred_alignment >= STACK_BOUNDARY / BITS_PER_UNIT ) ; gcc_assert ( preferred_alignment <= stack_alignment_needed ) ; if ( TARGET_SEH ) cfun -> machine -> use_fast_prologue_epilogue = false ; else if ( ! optimize_bb_for_size_p ( ENTRY_BLOCK_PTR_FOR_FN ( cfun ) ) && cfun -> machine -> use_fast_prologue_epilogue_nregs != frame -> nregs ) { int count = frame -> nregs ; struct cgraph_node * node = cgraph_node :: get ( current_function_decl ) ; cfun -> machine -> use_fast_prologue_epilogue_nregs = count ; if ( count ) count = ( count - <NUM_LIT> ) * FAST_PROLOGUE_INSN_COUNT ; if ( node -> frequency < NODE_FREQUENCY_NORMAL || ( flag_branch_probabilities && node -> frequency < NODE_FREQUENCY_HOT ) ) cfun -> machine -> use_fast_prologue_epilogue = false ; else cfun -> machine -> use_fast_prologue_epilogue = ! expensive_function_p ( count ) ; } frame -> save_regs_using_mov = ( TARGET_PROLOGUE_USING_MOVE && cfun -> machine -> use_fast_prologue_epilogue && flag_stack_check != STATIC_BUILTIN_STACK_CHECK ) ; offset = UNITS_PER_WORD ; if ( ix86_static_chain_on_stack ) offset += UNITS_PER_WORD ; if ( frame_pointer_needed ) offset += UNITS_PER_WORD ; frame -> hfp_save_offset = offset ; frame -> hard_frame_pointer_offset = offset ; offset += frame -> nregs * UNITS_PER_WORD ; frame -> reg_save_offset = offset ; if ( TARGET_SEH ) frame -> hard_frame_pointer_offset = offset ; if ( frame -> nsseregs ) { if ( ix86_incoming_stack_boundary >= <NUM_LIT> ) offset = ROUND_UP ( offset , <NUM_LIT> ) ; offset += frame -> nsseregs * <NUM_LIT> ; } frame -> sse_reg_save_offset = offset ; if ( stack_realign_fp ) offset = ROUND_UP ( offset , stack_alignment_needed ) ; frame -> va_arg_size = ix86_varargs_gpr_size + ix86_varargs_fpr_size ; offset += frame ->


<s> if ( invertCondCode ) CC = <STR_LIT> ( <STR_LIT> ( CC ) ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateCondCode ( CC , S , getLoc ( ) , getContext ( ) ) ) ; return


<s> vld3q_s16 ( const int16_t * __a ) { int16x8x3_t ret ; __builtin_aarch64_simd_ci __o ; __o = __builtin_aarch64_ld3v8hi ( ( const __builtin_aarch64_simd_hi * ) __a ) ; ret . val [ <NUM_LIT> ] = ( int16x8_t ) __builtin_aarch64_get_qregciv8hi ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( int16x8_t


<s> BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) ; } else { report_fatal_error ( <STR_LIT> + Twine ( FrameSize ) ) ; } if ( hasDebugInfo ) { std :: vector < MachineMove > & Moves = MMI . getFrameMoves ( ) ; MachineLocation SPDst ( MachineLocation :: VirtualFP ) ; MachineLocation SPSrc ( MachineLocation :: VirtualFP , - FrameSize ) ; Moves . push_back ( MachineMove ( FrameLabel , SPDst , SPSrc ) ) ; const std :: vector < CalleeSavedInfo > & CSI = MFI -> getCalleeSavedInfo ( ) ; for ( unsigned I = <NUM_LIT> , E = CSI . size ( ) ; I != E ; ++ I ) { int Offset = MFI -> getObjectOffset ( CSI [ I ] . getFrameIdx ( ) ) ; unsigned Reg = CSI [ I ] . getReg ( ) ; if ( Reg == <STR_LIT> ) continue ; MachineLocation CSDst ( MachineLocation :: VirtualFP


<s> if ( MI . getOpcode ( ) == <STR_LIT> ) { const MCInstrDesc & Desc = MI . getDesc ( ) ; return MI . getOperand ( Desc . getNumOperands ( ) - <NUM_LIT> ) . getImm ( ) == <NUM_LIT> && MI . getOperand ( Desc . getNumOperands ( ) - <NUM_LIT> ) . getReg ( ) == <STR_LIT> ; } return


<s> assert ( isUInt < <NUM_LIT> > ( Base ) && isUInt < <NUM_LIT> > ( Disp ) && isUInt < <NUM_LIT> > ( Len ) ) ; return ( Len << <NUM_LIT> ) | ( Base << <NUM_LIT> ) |


<s> static int m32r_issue_rate ( void ) { return ( ( TARGET_LOW_ISSUE_RATE ) ? <NUM_LIT> :


<s> DebugLoc dl = DebugLoc :: getUnknownLoc ( ) ; assert ( Cond . empty ( ) &&


<s> SDValue Tmp = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , dl , Op .


<s> O << <STR_LIT> ; printLeaMemReference ( MI , OpNo


<s> Optional < bool > llvm :: isPartOfGOTToPCRelPair ( const MCInst & Inst , const MCSubtargetInfo & STI ) { if ( Inst . getNumOperands ( ) < <NUM_LIT> ) return None ; unsigned LastOp = Inst . getNumOperands ( ) - <NUM_LIT> ; const MCOperand & Operand = Inst . getOperand ( LastOp ) ; if ( ! Operand . isExpr ( ) ) return None ; const MCExpr * Expr = Operand . getExpr


<s> std :: pair < int , MVT > LT = TLI -> getTypeLegalizationCost ( DL , VecTy ) ; int Cost = getMemoryOpCost ( Opcode , VecTy , Alignment , AddressSpace ) ; Cost += Factor * ( LT . first -


<s> const <ISA_LIT>TargetLowering * getTargetLowering


<s> MCContext & contextFromDecoder ( void const


<s> <STR_LIT> <ISA_LIT>CC ; MachineInstr * ConjMI = emitConjunction ( SelI . getCondReg ( ) , <ISA_LIT>CC , MIB ) ; if ( ! ConjMI ) return false ; emitSelect ( SelI . getReg ( <NUM_LIT> ) , SelI . getTrueReg ( ) , SelI . getFalseReg ( ) , <ISA_LIT>CC , MIB ) ; SelI . eraseFromParent (


<s> MCObjectWriter * llvm :: create<ISA_LIT>WinCOFFObjectWriter ( raw_pwrite_stream & OS , bool Is64Bit ) { MCWinCOFFObjectTargetWriter * MOTW = new <ISA_LIT>WinCOFFObjectWriter ( Is64Bit ) ; return createWinCOFFObjectWriter ( MOTW ,


<s> MFI -> setStackSize ( NumBytes ) ; unsigned GPRCS1Size = <NUM_LIT> , GPRCS2Size = <NUM_LIT> , DPRCSSize = <NUM_LIT> ; int FramePtrSpillFI = <NUM_LIT> ; if ( ArgRegsSaveSize ) { emitSPUpdate ( MBB , MBBI , TII , dl , * RegInfo , - ArgRegsSaveSize , MachineInstr :: FrameSetup ) ; CFAOffset -= ArgRegsSaveSize ; unsigned CFIIndex = MMI . addFrameInst ( MCCFIInstruction :: createDefCfaOffset ( nullptr , CFAOffset ) ) ; BuildMI ( MBB , MBBI , dl , TII . get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) . setMIFlags ( MachineInstr :: FrameSetup ) ; } if ( ! AFI -> hasStackFrame ( ) ) { if ( NumBytes - ArgRegsSaveSize != <NUM_LIT> ) { emitSPUpdate ( MBB , MBBI , TII , dl , * RegInfo , - ( NumBytes - ArgRegsSaveSize ) , MachineInstr :: FrameSetup ) ; CFAOffset -= NumBytes - ArgRegsSaveSize ; unsigned CFIIndex = MMI . addFrameInst ( MCCFIInstruction :: createDefCfaOffset ( nullptr , CFAOffset ) ) ; BuildMI ( MBB , MBBI , dl , TII . get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) . setMIFlags ( MachineInstr :: FrameSetup ) ; } return ; } for ( unsigned i = <NUM_LIT> , e = CSI . size ( ) ; i != e ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; int FI = CSI [ i ] . getFrameIdx ( ) ; switch ( Reg ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( STI . splitFramePushPop ( ) ) { GPRCS2Size += <NUM_LIT> ; break ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( Reg == FramePtr ) FramePtrSpillFI = FI ; GPRCS1Size += <NUM_LIT> ; break ; default : DPRCSSize += <NUM_LIT> ; } } if ( MBBI != MBB . end ( ) && MBBI -> getOpcode ( ) == <STR_LIT> ) { ++ MBBI ; } unsigned DPRCSOffset = NumBytes - ArgRegsSaveSize - ( GPRCS1Size + GPRCS2Size + DPRCSSize ) ; unsigned GPRCS2Offset = DPRCSOffset + DPRCSSize ; unsigned GPRCS1Offset = GPRCS2Offset + GPRCS2Size ; bool HasFP = hasFP ( MF ) ; if ( HasFP ) AFI -> setFramePtrSpillOffset ( MFI -> getObjectOffset ( FramePtrSpillFI ) + NumBytes ) ; AFI -> setGPRCalleeSavedArea1Offset ( GPRCS1Offset ) ; AFI -> setGPRCalleeSavedArea2Offset ( GPRCS2Offset ) ; AFI -> setDPRCalleeSavedAreaOffset ( DPRCSOffset ) ; NumBytes = DPRCSOffset ; int FramePtrOffsetInBlock = <NUM_LIT> ; unsigned adjustedGPRCS1Size = GPRCS1Size ; if ( tryFoldSPUpdateIntoPushPop ( STI , MF , & * std :: prev ( MBBI ) , NumBytes ) ) { FramePtrOffsetInBlock = NumBytes ; adjustedGPRCS1Size += NumBytes ; NumBytes = <NUM_LIT> ; } if ( adjustedGPRCS1Size


<s> if ( ! <ISA_LIT>FI -> globalBaseRegSet ( ) ) return ; MachineBasicBlock & MBB = MF . front ( ) ; MachineBasicBlock :: iterator I = MBB . begin ( ) ; MachineRegisterInfo & RegInfo = MF . getRegInfo ( ) ; const TargetInstrInfo & TII = * Subtarget -> getInstrInfo ( ) ; DebugLoc DL ; unsigned V0 , V1 , GlobalBaseReg = <ISA_LIT>FI -> getGlobalBaseReg ( ) ; const TargetRegisterClass * RC ; const <ISA_LIT>ABIInfo & ABI = static_cast < const <ISA_LIT>TargetMachine & > ( TM ) . getABI ( ) ; RC = ( ABI . IsN64 ( ) ) ? & <STR_LIT> : & <STR_LIT> ; V0 = RegInfo . createVirtualRegister ( RC ) ; V1 = RegInfo . createVirtualRegister ( RC ) ; if ( ABI . IsN64 ( ) ) { MF . getRegInfo ( ) . addLiveIn ( <STR_LIT> ) ; MBB . addLiveIn ( <STR_LIT> ) ; const GlobalValue * FName = & MF . getFunction ( ) ; BuildMI ( MBB , I , DL , TII . get ( <STR_LIT> ) , V0 ) . addGlobalAddress ( FName , <NUM_LIT> , <STR_LIT> ) ; BuildMI ( MBB , I , DL , TII . get ( <STR_LIT> ) , V1 ) . addReg ( V0 ) . addReg ( <STR_LIT> ) ; BuildMI ( MBB , I , DL , TII . get ( <STR_LIT> ) , GlobalBaseReg ) . addReg ( V1 ) . addGlobalAddress ( FName , <NUM_LIT> , <STR_LIT> ) ; return ; } if ( ! MF . getTarget ( ) .


<s> void LLVMInitializeCell<ISA_LIT>Target (


<s> bool <ISA_LIT>InstrInfo :: areMemAccessesTriviallyDisjoint ( MachineInstr & MIa , MachineInstr & MIb , AliasAnalysis * AA ) const { assert ( ( MIa . mayLoad ( ) || MIa . mayStore ( ) ) && <STR_LIT> ) ; assert ( ( MIb . mayLoad ( ) || MIb . mayStore ( ) ) && <STR_LIT> ) ; if ( MIa . hasUnmodeledSideEffects ( ) || MIb . hasUnmodeledSideEffects ( ) ) return false ; if ( MIa . hasOrderedMemoryRef ( ) || MIb . hasOrderedMemoryRef ( ) ) return false ; if ( isDS ( MIa ) ) { if ( isDS ( MIb ) ) return checkInstOffsetsDoNotOverlap ( MIa , MIb ) ; return ! isFLAT ( MIb ) || isSegmentSpecificFLAT ( MIb ) ; } if ( isMUBUF ( MIa ) || isMTBUF ( MIa ) ) { if ( isMUBUF ( MIb ) || isMTBUF ( MIb


<s> case 'm' : if ( ! SelectADDRrr ( Op . getNode ( ) , Op , Op0 , Op1 ) ) SelectADDRri ( Op . getNode ( ) , Op , Op0 , Op1 ) ; break ; } OutOps . push_back ( Op0


<s> if ( ( MI -> getOperand ( <NUM_LIT> ) . isFI ( ) ) && ( MI -> getOperand ( <NUM_LIT> ) . isImm ( ) ) && ( isZeroImm ( MI -> getOperand ( <NUM_LIT> ) ) ) ) { FrameIndex = MI -> getOperand ( <NUM_LIT> ) . getIndex ( ) ; return MI -> getOperand ( <NUM_LIT> ) .


<s> static int mep_address_cost ( rtx addr ATTRIBUTE_UNUSED , machine_mode mode ATTRIBUTE_UNUSED , addr_space_t as


) _mm_undefined_si128 ( ) , ( __mmask8 ) - <NUM_LIT> ) ;


<s> for ( unsigned i = <NUM_LIT> , e = Values . size ( ) ; i != e ; ++ i ) { SDValue V = Values [ i ] ; if ( V . isUndef ( ) ) { Consts [ i ] = ConstantInt :: get ( IntTy , <NUM_LIT> ) ; continue ; } if ( auto * CN = dyn_cast < ConstantSDNode > ( V . getNode ( ) ) ) { const ConstantInt * CI = CN -> getConstantIntValue ( ) ; Consts [ i ] = ConstantInt :: get ( IntTy , CI -> getValue ( ) . getSExtValue ( ) ) ; } else if ( auto * CN = dyn_cast < ConstantFPSDNode > ( V .


<s> Register DR = MD . getReg ( ) , DSR = MD . getSubReg ( ) ; bool ReadUndef = MD . isUndef ( ) ; MachineBasicBlock :: iterator At = MI ; auto updateRegs = [ & UpdRegs ] ( const MachineInstr & MI ) -> void { for ( auto & Op : MI . operands ( ) ) if ( Op . isReg ( ) ) UpdRegs . insert ( Op . getReg ( ) ) ; } ; MachineOperand & ST = MI . getOperand ( <NUM_LIT> ) ; MachineOperand & SF = MI . getOperand ( <NUM_LIT> ) ; if ( ST . isReg ( ) && SF . isReg ( ) ) { RegisterRef RT ( ST ) ; if ( RT == RegisterRef ( SF ) ) { updateRegs ( MI ) ; MI . setDesc ( HII -> get ( TargetOpcode :: COPY ) ) ; unsigned S = getRegState


<s> bool isInstAtomic ( uint16_t Opcode ) const { return get ( Opcode )


<s> MachineFunction & MF = MIRBuilder . getMF ( ) ; const Function & F = * MF . getFunction ( ) ; auto MIB = MIRBuilder . buildInstrNoInsert ( <STR_LIT> ) ; assert ( ( ( Val && VReg ) || ( ! Val && ! VReg ) ) && <STR_LIT> ) ; bool Success = true ; if ( VReg ) { const <ISA_LIT>TargetLowering & TLI = * getTLI < <ISA_LIT>TargetLowering > ( ) ; CCAssignFn * AssignFn = TLI . CCAssignFnForReturn ( F . getCallingConv ( ) ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; auto & DL = F . getParent ( ) -> getDataLayout ( ) ; ArgInfo OrigArg { VReg , Val -> getType ( ) } ; setArgFlags ( OrigArg , AttributeList :: ReturnIndex , DL , F ) ; SmallVector < ArgInfo , <NUM_LIT> > SplitArgs ; splitToValueTypes ( OrigArg , SplitArgs , DL , MRI , [ & ] ( unsigned Reg , uint64_t Offset ) { MIRBuilder . buildExtract ( Reg , VReg , Offset ) ; } ) ; OutgoingArgHandler Handler ( MIRBuilder , MRI , MIB , AssignFn , AssignFn ) ; Success = handleAssignments ( MIRBuilder , SplitArgs


<s> op1 = crx_compare_op1 ; cc_reg = gen_rtx_REG ( CCmode , CC_REGNUM ) ; ret = gen_rtx_COMPARE ( CCmode , op0


<s> return ( __m128i ) __builtin_ia32_vphadduwq ( ( __v8hi )


<s> Register DestSub0 = MRI -> createVirtualRegister ( & <STR_LIT> ) ; Register DestSub1 = MRI -> createVirtualRegister ( & <STR_LIT> ) ; MachineInstr * LoHalf = BuildMI ( * MBB , MBBI , DL , TII -> get ( <STR_LIT> ) , DestSub0 ) . addReg ( CarryReg , RegState :: Define ) . addReg ( Addr . Base . LoReg , <NUM_LIT> , Addr . Base . LoSubReg ) . add ( OffsetLo ) . addImm ( <NUM_LIT> ) ; ( void ) LoHalf ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; LoHalf -> dump ( ) ; ) ; MachineInstr * HiHalf = BuildMI ( * MBB , MBBI , DL , TII -> get ( <STR_LIT> ) , DestSub1 ) . addReg ( DeadCarryReg , RegState :: Define | RegState :: Dead ) . addReg ( Addr . Base . HiReg , <NUM_LIT> , Addr . Base . HiSubReg ) . add ( OffsetHi ) . addReg ( CarryReg , RegState :: Kill ) . addImm ( <NUM_LIT> ) ; ( void ) HiHalf ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; HiHalf -> dump ( ) ; ) ; Register FullDestReg = MRI -> createVirtualRegister ( TRI -> getVGPR64Class ( ) ) ; MachineInstr * FullBase = BuildMI ( * MBB , MBBI , DL , TII -> get ( TargetOpcode :: REG_SEQUENCE ) , FullDestReg ) . addReg ( DestSub0 )

. addImm ( <STR_LIT> ) . addReg ( DestSub1 ) . addImm ( <STR_LIT> ) ;


<s> static DecodeStatus DecodeDSPRRegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t Address , const MCDisassembler *


<s> } } } else if ( Imm == ~ <NUM_LIT> ) { SDValue Op = N -> getOperand ( <NUM_LIT> ) ; switch ( CC ) { default : break ; case <STR_LIT> : if ( is<ISA_LIT>64 ) break ; Op = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , <STR_LIT> , Op , getI32Imm ( <NUM_LIT> , dl ) ) , <NUM_LIT> ) ; return CurDAG -> SelectNodeTo ( N , <STR_LIT> , <STR_LIT> , SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , getI32Imm ( <NUM_LIT> , dl ) ) , <NUM_LIT> ) , Op . getValue ( <NUM_LIT> ) ) ; case <STR_LIT> : { if ( is<ISA_LIT>64 ) break ; Op = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , Op , Op ) , <NUM_LIT> ) ; SDNode * AD = CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , <STR_LIT> , Op , getI32Imm ( ~ <NUM_LIT> , dl ) ) ; return CurDAG -> SelectNodeTo ( N , <STR_LIT> , <STR_LIT> , SDValue ( AD , <NUM_LIT> ) , Op , SDValue ( AD , <NUM_LIT> ) ) ; } case <STR_LIT> : { SDValue AD = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , Op , getI32Imm ( <NUM_LIT> , dl ) ) , <NUM_LIT> ) ; SDValue AN = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , AD , Op ) , <NUM_LIT> ) ; SDValue Ops [ ] = { AN , getI32Imm ( <NUM_LIT> , dl ) , getI32Imm ( <NUM_LIT> , dl ) , getI32Imm ( <NUM_LIT> , dl ) } ; return CurDAG -> SelectNodeTo ( N , <STR_LIT> , <STR_LIT> , Ops ) ; } case <STR_LIT> : { SDValue Ops [ ] = { Op , getI32Imm ( <NUM_LIT> , dl ) , getI32Imm ( <NUM_LIT> , dl ) , getI32Imm ( <NUM_LIT> , dl ) } ; Op = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , Ops ) , <NUM_LIT> ) ; return CurDAG -> SelectNodeTo ( N , <STR_LIT> , <STR_LIT> , Op , getI32Imm ( <NUM_LIT> , dl ) ) ; } } } } SDValue LHS = N -> getOperand ( <NUM_LIT> ) ; SDValue RHS = N -> getOperand ( <NUM_LIT> ) ; if ( LHS . getValueType ( ) . isVector ( ) ) { if ( <ISA_LIT>SubTarget -> hasQPX ( ) ) return nullptr ; EVT VecVT = LHS . getValueType ( ) ; bool Swap , Negate


<s> if ( far_addr_space_p ( operands [ <NUM_LIT> ] ) && CONSTANT_P ( operands [ <NUM_LIT> ] ) ) { operands [ <NUM_LIT> ] = force_reg ( GET_MODE ( operands [ <NUM_LIT> ] ) , operands [ <NUM_LIT> ] ) ; } if ( TARGET_A16 && mode == PSImode ) return m32c_split_move ( operands , mode , <NUM_LIT> ) ; if ( ( GET_CODE ( operands [ <NUM_LIT> ] ) == MEM ) && ( GET_CODE ( XEXP ( operands [ <NUM_LIT> ] , <NUM_LIT> ) )


<s> Worklist . push_back ( PreHeader ) ; Visited . insert ( LoopStart -> getParent ( ) ) ; while ( ! Worklist . empty ( ) ) { MachineBasicBlock * MBB = Worklist . pop_back_val ( ) ; if ( Visited . count ( MBB ) ) continue ; for ( MachineInstr & MI : * MBB ) { if ( ! IsInvalidTPInstruction ( MI ) ) continue ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << MI ) ; MachineInstrBuilder MIB = BuildMI ( * PreHeader , PreHeader -> getFirstTerminator ( ) , LoopStart -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) ; MIB . add ( LoopStart -> getOperand ( <NUM_LIT> ) ) ; MIB . add ( LoopStart -> getOperand ( <NUM_LIT> ) ) ; LoopStart -> getOperand ( <NUM_LIT> ) . setIsKill ( false ) ; RevertWhileLoopStartLR ( LoopStart , TII , <STR_LIT> , true ) ; return MIB ; } Visited . insert ( MBB ) ; for ( auto * Pred : MBB -> predecessors ( ) ) Worklist . push_back ( Pred ) ; } return


<s> const tree decl2 = default_version_info -> this_node -> decl ; if ( is_function_default_version ( decl2 ) ) break ; default_version_info = default_version_info -> next ; } if ( default_version_info == NULL ) return NULL ; if ( first_v != default_version_info ) { default_version_info -> prev -> next = default_version_info -> next ; if ( default_version_info -> next ) default_version_info -> next -> prev = default_version_info -> prev ; first_v -> prev = default_version_info ; default_version_info -> next = first_v ; default_version_info -> prev = NULL ; } default_node = default_version_info -> this_node ; error_at ( DECL_SOURCE_LOCATION ( default_node -> decl ) , <STR_LIT> <STR_LIT> ) ; if ( targetm . has_ifunc_p ( ) ) { struct cgraph_function_version_info * it_v = NULL ; struct cgraph_node * dispatcher_node = NULL ; struct cgraph_function_version_info * dispatcher_version_info = NULL ; dispatch_decl = make_dispatcher_decl ( default_node -> decl ) ; dispatcher_node = cgraph_node :: get_create ( dispatch_decl ) ; gcc_assert ( dispatcher_node != NULL ) ; dispatcher_node -> dispatcher_function = <NUM_LIT> ; dispatcher_version_info = dispatcher_node -> insert_new_function_version ( ) ; dispatcher_version_info -> next = default_version_info ; dispatcher_node -> definition = <NUM_LIT> ; it_v = default_version_info ; while ( it_v != NULL ) { it_v -> dispatcher_resolver = dispatch_decl ; it_v = it_v ->


<s> auto Op = make_unique < <ISA_LIT>Operand > ( KindToken , Loc , Loc ) ; Op -> Token . Data = Str . data ( ) ; Op -> Token . Length = Str . size


<s> unsigned NumElems = VT . getVectorNumElements ( ) ; if ( ( VT . is128BitVector ( ) && NumElems != <NUM_LIT> ) || ( VT . is256BitVector ( ) && NumElems != <NUM_LIT> ) ) return false ; for ( unsigned i = <NUM_LIT> ; i != NumElems ; i += <NUM_LIT> ) if ( ! isUndefOrEqual ( Mask [ i

] , i ) || ! isUndefOrEqual ( Mask [ i + <NUM_LIT> ] , i ) ) return false ;


<s> static DecodeStatus DecodeUImm6Lsl2 ( MCInst & Inst , unsigned Value , uint64_t Address , const void * Decoder ) { Inst . addOperand ( MCOperand :: CreateImm ( Value << <NUM_LIT> ) ) ; return MCDisassembler


<s> MachineBasicBlock * MBB = MI -> getParent ( ) ; assert ( MI -> getOpcode ( ) == <STR_LIT> && <STR_LIT> ) ; if ( UseCmp ) { MachineInstrBuilder MIB = BuildMI ( * MBB , MI , MI -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) ; MIB . add ( MI -> getOperand ( <NUM_LIT> ) ) ; MIB . addImm ( <NUM_LIT> ) ; MIB . addImm ( <STR_LIT> ) ; MIB . addReg ( <STR_LIT> ) ; } else { MachineInstrBuilder MIB = BuildMI ( * MBB , MI , MI -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) ; MIB . add ( MI -> getOperand ( <NUM_LIT>


<s> static bool check_mduc_usage ( void ) { rtx_insn * insn ; basic_block bb ; FOR_EACH_BB_FN ( bb , cfun ) { FOR_BB_INSNS ( bb


<s> if ( ! mem -> getMemoryVT ( ) . isInteger ( ) ) llvm_unreachable ( <STR_LIT> ) ; else if ( ! mem -> getMemoryVT ( ) . isSimple ( ) ) llvm_unreachable ( <STR_LIT> ) ; else { want_align = mem -> getMemoryVT ( ) . getSimpleVT ( ) . getSizeInBits ( ) ; want_align /= <NUM_LIT> ; if ( align < want_align ) llvm_unreachable ( <STR_LIT> ) ; } FIN = dyn_cast < FrameIndexSDNode > ( addr ) ; assert ( FIN ) ; base = CurDAG -> getCopyFromReg ( CurDAG -> getEntryNode ( ) , dl , <STR_LIT> , <STR_LIT> ) ; offs = CurDAG -> getTargetFrameIndex ( FIN -> getIndex ( ) , <STR_LIT> ) ; return true


<s> Value * Ret = CallInst :: Create ( If , Term -> getCondition ( ) , <STR_LIT> , Term ) ; Term -> setCondition ( ExtractValueInst :: Create ( Ret , <NUM_LIT>


<s> bool hasZeroMoveFusion ( ) const { return HasZeroMoveFusion


<s> SDValue NewPtr = DAG . getNode ( <STR_LIT> , Op . getDebugLoc ( ) , PtrType , Ptr , DAG . getConstant ( <NUM_LIT> , PtrType ) ) ; RetVal2 = DAG . getLoad ( <STR_LIT> , Op . getDebugLoc ( ) , Ld -> getChain ( ) , NewPtr , Ld -> getSrcValue ( ) , Ld -> getSrcValueOffset ( ) + <NUM_LIT> , Ld -> isVolatile (

) , Ld -> isNonTemporal ( ) , NewAlign ) ;


<s> bool <ISA_LIT>FrameLowering :: hasGOT ( const MachineFunction & MF )


<s> if ( Type == ELF :: R_MIPS16_HI16 ) return ELF :: R_MIPS16_LO16 ; if ( Reloc . Symbol -> getBinding ( ) != ELF :: STB_LOCAL ) return ELF :: R_MIPS_NONE ; if ( Type == ELF :: R_MIPS_GOT16 ) return ELF :: R_MIPS_LO16 ; if ( Type == ELF :: R_MICROMIPS_GOT16 ) return ELF :: R_MICROMIPS_LO16 ; if ( Type == ELF :: R_MIPS16_GOT16 ) return ELF :: R_MIPS16_LO16 ; return ELF :: R_MIPS_NONE


<s> const Function * <ISA_LIT>SPMark :: getCallTarget ( const MachineInstr * MI ) const { const MachineOperand & MO = MI -> getOperand ( <NUM_LIT> ) ; const Function * Target = NULL ; if ( MO . isGlobal ( ) ) { Target = dyn_cast < Function > ( MO .


<s> MCSymbolRefExpr :: VariantKind Modifier = Target . isAbsolute ( ) ? MCSymbolRefExpr :: VK_None : Target . getSymA ( ) -> getKind ( ) ; switch ( static_cast < unsigned > ( Fixup . getKind ( ) ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case FK_Data_4 : switch ( Modifier ) { case MCSymbolRefExpr :: VK_COFF_IMGREL32 : return COFF :: IMAGE_REL_<ISA_LIT>_ADDR32NB ; case MCSymbolRefExpr :: VK_SECREL : return COFF :: IMAGE_REL_<ISA_LIT>_SECREL ; default : return COFF :: IMAGE_REL_<ISA_LIT>_ADDR32 ; } case FK_SecRel_4 : return COFF :: IMAGE_REL_<ISA_LIT>_SECREL ; case <STR_LIT> : return COFF :: IMAGE_REL_<ISA_LIT>_BRANCH20T ; case <STR_LIT> : return COFF :: IMAGE_REL_<ISA_LIT>_BRANCH24T ; case <STR_LIT> : case <STR_LIT> : return COFF :: IMAGE_REL_<ISA_LIT>_BLX23T ; case <STR_LIT> : return COFF :: IMAGE_REL_<ISA_LIT>_MOV32T ; case <STR_LIT> : llvm_unreachable ( <STR_LIT>


<s> return BuildSignatureCall ( <STR_LIT> ,


<s> src = XEXP ( src , <NUM_LIT> ) ; if ( GET_CODE ( src ) != MEM || GET_MODE ( src ) != SImode ) return SCHED_FUSION_NONE ; } else if ( GET_CODE ( src ) == ZERO_EXTEND ) { fusion = SCHED_FUSION_LD_ZERO_EXTEND ; src = XEXP ( src , <NUM_LIT> ) ; if ( GET_CODE ( src ) != MEM || GET_MODE ( src ) != SImode ) return SCHED_FUSION_NONE ; } if ( GET_CODE ( src ) == MEM && REG_P ( dest ) ) extract_base_offset_in_addr ( src , base , offset ) ; else if ( GET_CODE ( dest ) == MEM && ( REG_P ( src ) || src == const0_rtx ) ) { fusion = SCHED_FUSION_ST ; extract_base_offset_in_addr ( dest , base , offset ) ; } else return SCHED_FUSION_NONE ; if ( * base == NULL_RTX || * offset == NULL_RTX ) fusion


<s> fma_forest :: ~ fma_forest ( ) { delete this


<s> bool Carry = ( Value & <NUM_LIT> ) ; Value = ( ( Value & <NUM_LIT> ) >> <NUM_LIT> ) + Carry ; if ( Value & <NUM_LIT> ) Value


<s> static inline unsigned getUnconditionalBrDisp ( int Opc ) { unsigned Bits , Scale ; switch ( Opc ) { case <STR_LIT> : Bits = <NUM_LIT> ; Scale = <NUM_LIT> ; break ; case <STR_LIT>


<s> for ( MachineBasicBlock :: iterator I = MFI -> begin ( ) ; I


<s> __v2df a , b , c ; a = vec_splats ( __A [ <NUM_LIT> ] ) ; b = vec_splats ( __B [ <NUM_LIT> ] ) ; c = ( __v2df ) vec_cmplt ( a ,


<s> bool has<ISA_LIT>2Ops ( ) const { return <ISA_LIT>ArchVersion >=


<s> if ( getTargetMachine ( ) . shouldAssumeDSOLocal ( * GV -> getParent ( ) , GV ) ) { MachineFunction & MF = DAG . getMachineFunction ( ) ; MVT PtrVT = getPointerTy ( MF . getDataLayout ( ) ) ; const char * BaseName ; if ( GV -> getValueType ( ) -> isFunctionTy ( ) ) { BaseName = MF . createExternalSymbolName ( <STR_LIT> ) ; OperandFlags = <STR_LIT> ; } else { BaseName = MF . createExternalSymbolName ( <STR_LIT> ) ; OperandFlags = <STR_LIT> ; } SDValue BaseAddr = DAG . getNode ( <STR_LIT> , DL , PtrVT , DAG . getTargetExternalSymbol


<s> MachineBasicBlock :: iterator BundleStart = BuildMI ( MBB , I , DL , TII -> get ( <STR_LIT> ) ) . addImm ( ClearMask >> <NUM_LIT> ) ; BuildMI ( MBB , I , DL , TII -> get ( <STR_LIT> ) , <STR_LIT>

) . addReg ( I -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ;


<s> SDValue SignMask2x64 ( SDValue A ) { assert ( A . getSimpleValueType ( ) . getSizeInBits ( ) == <NUM_LIT> && <STR_LIT> ) ; if ( A . getSimpleValueType ( ) != <STR_LIT> )


<s> MachineBasicBlock :: iterator <ISA_LIT>LoadStoreOptimizer :: mergeBufferStorePair ( CombineInfo & CI , CombineInfo & Paired ) { MachineBasicBlock * MBB = CI . I -> getParent ( ) ; DebugLoc DL = CI . I -> getDebugLoc ( ) ; const unsigned Opcode = getNewOpcode ( CI , Paired ) ; std :: pair < unsigned , unsigned > SubRegIdx = getSubRegIdxs ( CI , Paired ) ; const unsigned SubRegIdx0 = std :: get < <NUM_LIT> > ( SubRegIdx ) ; const unsigned SubRegIdx1 = std :: get < <NUM_LIT> > ( SubRegIdx ) ; const TargetRegisterClass * SuperRC = getTargetRegisterClass ( CI , Paired ) ; Register SrcReg = MRI -> createVirtualRegister ( SuperRC ) ; const auto * Src0 = TII -> getNamedOperand ( * CI . I , <STR_LIT> :: vdata ) ; const auto * Src1 = TII -> getNamedOperand ( * Paired . I , <STR_LIT> :: vdata ) ; BuildMI ( * MBB , Paired . I , DL , TII -> get ( <STR_LIT> ) , SrcReg ) . add ( * Src0 ) . addImm ( SubRegIdx0 ) . add ( * Src1 ) . addImm ( SubRegIdx1 ) ; auto MIB = BuildMI ( * MBB , Paired . I , DL , TII -> get ( Opcode ) ) . addReg ( SrcReg , RegState :: Kill ) ; const unsigned Regs = getRegs ( Opcode , * TII ) ; if ( Regs & VADDR ) MIB . add ( * TII -> getNamedOperand ( * CI . I , <STR_LIT> :: vaddr ) ) ; assert ( CI . I -> hasOneMemOperand ( ) && Paired . I -> hasOneMemOperand ( ) ) ; const MachineMemOperand * MMOa = * CI . I -> memoperands_begin ( ) ; const MachineMemOperand * MMOb = * Paired . I -> memoperands_begin ( ) ; MachineInstr * New = MIB . add ( * TII -> getNamedOperand ( * CI . I , <STR_LIT> :: srsrc ) ) . add ( * TII -> getNamedOperand ( * CI . I , <STR_LIT> :: soffset ) ) . addImm ( std :: min ( CI . Offset , Paired . Offset ) ) . addImm ( CI . GLC ) . addImm ( CI . SLC ) . addImm ( <NUM_LIT> ) . addImm ( CI . DLC ) . addImm ( <NUM_LIT> ) . addMemOperand ( combineKnownAdjacentMMOs ( * MBB -> getParent ( ) , MMOa , MMOb ) ) ; moveInstsAfter ( MIB , CI .


<s> if ( ! UseAddressTopByteIgnored ) return false ; if ( TargetTriple . isiOS ( ) ) { unsigned Major , Minor , Micro ; TargetTriple . getiOSVersion ( Major , Minor , Micro ) ; return Major >= <NUM_LIT> ; } return


<s> MachineBasicBlock & MBB = MF . front ( ) ; MachineBasicBlock :: iterator I = MBB . begin ( ) ; const TargetInstrInfo & TII = * MF . getSubtarget ( ) . getInstrInfo ( ) ; DebugLoc DL = I != MBB . end ( ) ? I -> getDebugLoc ( ) : DebugLoc ( ) ; unsigned <ISA_LIT>16SPAliasReg = <ISA_LIT>FI -> get<ISA_LIT>16SPAliasReg ( ) ; BuildMI ( MBB , I , DL , TII . get

( <STR_LIT> ) , <ISA_LIT>16SPAliasReg ) . addReg ( <STR_LIT> ) ;


<s> void <ISA_LIT>WholeQuadMode :: lowerCopyInstrs ( ) { for ( MachineInstr * MI : LowerToMovInstrs ) { assert ( MI -> getNumExplicitOperands ( ) == <NUM_LIT> ) ; const Register Reg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( TRI -> isVGPR ( * MRI , Reg ) ) { const TargetRegisterClass * regClass = Register :: isVirtualRegister ( Reg ) ? MRI -> getRegClass ( Reg ) : TRI -> getPhysRegClass ( Reg ) ; const unsigned MovOp = TII -> getMovOpcode ( regClass ) ; MI -> setDesc ( TII -> get ( MovOp ) ) ; MI -> addOperand ( MachineOperand :: CreateReg ( <STR_LIT> , false , true ) ) ; } else { MI -> setDesc ( TII -> get ( <STR_LIT> ) ) ; } } for ( MachineInstr * MI : LowerToCopyInstrs ) { if ( MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> ) { assert ( MI -> getNumExplicitOperands ( ) == <NUM_LIT>


<s> CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; * cum += ( mode != BLKmode ? ( GET_MODE_SIZE ( mode ) + <NUM_LIT> ) & ~

<NUM_LIT> : ( int_size_in_bytes ( type ) + <NUM_LIT> ) & ~ <NUM_LIT> ) ;


<s> bool addPassesToEmitMC ( PassManagerBase & , MCContext * & , raw_pwrite_stream & , bool = true ) override { return true


<s> for ( unsigned i = <NUM_LIT> , w = OutC . width ( ) ; i < w ; ++ i ) { const BitTracker :: BitValue & V = OutC [ i ] ; if ( V . Type != BitTracker :: BitValue :: Ref )


<s> return LowerSymbolOperand ( MI , MO , AP . GetBlockAddressSymbol ( MO . getBlockAddress ( ) ) , AP ) ; case MachineOperand :: MO_ConstantPoolIndex : return LowerSymbolOperand ( MI , MO , AP . GetCPISymbol ( MO . getIndex ( ) ) , AP ) ; case MachineOperand :: MO_ExternalSymbol : return LowerSymbolOperand ( MI , MO , AP . GetExternalSymbolSymbol ( MO . getSymbolName ( ) ) , AP ) ; case MachineOperand :: MO_GlobalAddress


<s> uws . next = ptr + <NUM_LIT> ; uws . bytes_left = <NUM_LIT> ; uws . words_left = ( ( * ptr ) >> <NUM_LIT> ) & <NUM_LIT> ; return __gnu_unwind_execute ( context , &


<s> MCOperand <ISA_LIT>Disassembler :: decodeOperand_SReg_256 ( unsigned Val ) const { return createSRegOperand ( <STR_LIT>


<s> short s [ <NUM_LIT> ] ; } x ; x . s [ <NUM_LIT> ] =


<s> SDValue <ISA_LIT>TargetLowering :: getRecipEstimate ( SDValue Operand , SelectionDAG & DAG , int Enabled , int & RefinementSteps ) const { EVT VT = Operand . getValueType ( ) ; if ( ( VT == <STR_LIT> && Subtarget . hasFRES ( ) ) || ( VT == <STR_LIT> && Subtarget . hasFRE ( ) ) || ( VT == <STR_LIT> && Subtarget . hasAltivec ( ) ) || ( VT == <STR_LIT> && Subtarget . hasVSX ( ) ) ) { if ( RefinementSteps == ReciprocalEstimate :: Unspecified ) RefinementSteps = getEstimateRefinementSteps ( VT , Subtarget ) ; return DAG . getNode ( <STR_LIT> , SDLoc ( Operand ) , VT , Operand ) ; } return SDValue ( )


<s> for ( unsigned i = <NUM_LIT> ; i < NumArgs ; ++ i ) MIB . addOperand ( MI -> getOperand ( i ) ) ; MIB -> setMemRefs ( MI -> memoperands_begin ( ) , MI -> memoperands_end ( ) ) ; return MIB


<s> do { switch ( Super -> getID ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return Super ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . hasNEON ( ) )


<s> ( ( <ISA_LIT>Operand * ) Operands [ <NUM_LIT> ] ) -> addMemNoOffsetOperands ( Inst , <NUM_LIT> ) ; ( ( <ISA_LIT>Operand * ) Operands [ <NUM_LIT> ] ) -> addPostIdxRegOperands ( Inst , <NUM_LIT> ) ; ( ( <ISA_LIT>Operand * ) Operands [ <NUM_LIT> ] ) -> addCondCodeOperands ( Inst


<s> unsigned Reg = CSI [ i ] . getReg ( ) ; unsigned RegNum = <ISA_LIT>RegisterInfo :: getRegisterNumbering ( Reg ) ; if ( <STR_LIT> -> contains ( Reg ) ) CPUBitmask |= ( <NUM_LIT> << RegNum ) ; else FPUBitmask |= ( <NUM_LIT> << RegNum ) ; } if ( RI . hasFP ( * MF ) ) CPUBitmask |= ( <NUM_LIT> << <ISA_LIT>RegisterInfo :: getRegisterNumbering ( RI . getFrameRegister ( * MF ) ) ) ; if ( MFI -> adjustsStack ( ) ) CPUBitmask |= ( <NUM_LIT> << <ISA_LIT>RegisterInfo :: getRegisterNumbering ( RI . getRARegister ( ) ) ) ; O << <STR_LIT> ; printHex32 ( CPUBitmask , O ) ; O << ',' << <ISA_LIT>FI -> getCPUTopSavedRegOff


<s> const <ISA_LIT>TargetLowering * getTargetLowering ( ) const override { return & TLInfo


<s> unsigned getNumFixupKinds ( ) const override {

return AMDGPU :: NumTargetFixupKinds ; }


<s> ATS . emitAttribute ( <STR_LIT> , Subtarget -> has<ISA_LIT>Ops ( ) ? <STR_LIT> : <STR_LIT> ) ; if ( Subtarget -> isThumb1Only ( ) ) { ATS . emitAttribute ( <STR_LIT> , <STR_LIT> ) ; } else if ( Subtarget -> hasThumb2 ( ) ) { ATS . emitAttribute ( <STR_LIT> , <STR_LIT> ) ; } if ( Subtarget -> hasNEON ( ) ) { if ( Subtarget -> hasFP<ISA_LIT>v8 ( ) ) { if ( Subtarget -> hasCrypto ( ) ) ATS . emitFPU ( <STR_LIT> ) ; else ATS . emitFPU ( <STR_LIT> ) ; } else if ( Subtarget -> hasVFP4 ( ) ) ATS . emitFPU ( <STR_LIT> ) ; else ATS . emitFPU ( <STR_LIT> ) ; if ( Subtarget -> hasV8Ops ( ) ) ATS . emitAttribute ( <STR_LIT> , <STR_LIT> ) ; } else { if ( Subtarget -> hasFP<ISA_LIT>v8 ( ) ) ATS . emitFPU ( <STR_LIT> ) ; else if ( Subtarget -> hasVFP4 ( ) ) ATS . emitFPU ( Subtarget -> hasD16 ( ) ? <STR_LIT> : <STR_LIT> ) ; else if ( Subtarget -> hasVFP3 ( ) ) ATS . emitFPU ( Subtarget -> hasD16 ( ) ? <STR_LIT> : <STR_LIT> ) ; else if ( Subtarget -> hasVFP2 ( ) ) ATS . emitFPU ( <STR_LIT> ) ; } if ( ! TM . Options . UnsafeFPMath ) { ATS . emitAttribute ( <STR_LIT> , <STR_LIT> ) ; ATS . emitAttribute ( <STR_LIT> , <STR_LIT> ) ; } if ( TM . Options . NoInfsFPMath && TM . Options . NoNaNsFPMath ) ATS . emitAttribute ( <STR_LIT> , <STR_LIT> ) ; else ATS . emitAttribute ( <STR_LIT> , <STR_LIT> ) ; ATS . emitAttribute ( <STR_LIT> , <NUM_LIT> ) ; ATS . emitAttribute ( <STR_LIT> , <NUM_LIT> ) ; if ( Subtarget -> isAAPCS_ABI ( ) && TM . Options . FloatABIType == FloatABI :: Hard ) { ATS . emitAttribute ( <STR_LIT> , <NUM_LIT> ) ; ATS . emitAttribute ( <STR_LIT>


<s> if ( DECL_STATIC_CHAIN ( decl ) || cfun -> machine -> has_chain ) write_arg_type ( s , STATIC_CHAIN_REGNUM , DECL_STATIC_CHAIN ( decl ) ? argno : - <NUM_LIT> , ptr_type_node , true ) ; fprintf ( file , <STR_LIT> , s . str ( ) . c_str ( ) ) ; if ( ! crtl -> is_leaf ) crtl -> is_leaf = leaf_function_p ( ) ; HOST_WIDE_INT sz = get_frame_size ( ) ; bool need_frameptr = sz || cfun -> machine -> has_chain ; int alignment = crtl -> stack_alignment_needed / BITS_PER_UNIT ; if ( ! TARGET_SOFT_STACK ) { if ( cfun -> machine -> has_varadic ) init_frame ( file , STACK_POINTER_REGNUM , UNITS_PER_WORD , crtl -> outgoing_args_size ) ; if ( need_frameptr ) init_frame ( file , FRAME_POINTER_REGNUM , alignment , ROUND_UP ( sz , GET_MODE_SIZE ( DImode ) ) ) ; } else if ( need_frameptr || cfun -> machine -> has_varadic || cfun -> calls_alloca || ( cfun -> machine -> has_simtreg && ! crtl -> is_leaf ) ) init_softstack_frame ( file , alignment , sz ) ; if ( cfun -> machine -> has_simtreg ) { unsigned HOST_WIDE_INT & simtsz = cfun -> machine -> simt_stack_size ; unsigned HOST_WIDE_INT & align = cfun -> machine -> simt_stack_align ; align = MAX ( align , GET_MODE_SIZE ( DImode ) ) ; if ( ! crtl -> is_leaf || cfun -> calls_alloca ) simtsz = HOST_WIDE_INT_M1U ; if ( simtsz == HOST_WIDE_INT_M1U ) simtsz = nvptx_softstack_size ; if ( cfun -> machine -> has_softstack ) simtsz += POINTER_SIZE / <NUM_LIT> ; simtsz = ROUND_UP ( simtsz , GET_MODE_SIZE ( DImode ) ) ; if ( align > GET_MODE_SIZE ( DImode ) ) simtsz += align - GET_MODE_SIZE ( DImode ) ; if ( simtsz ) fprintf ( file , <STR_LIT> HOST_WIDE_INT_PRINT_DEC <STR_LIT> , simtsz ) ; } int maxregs = max_reg_num ( ) ; for ( int i = LAST_VIRTUAL_REGISTER + <NUM_LIT> ; i < maxregs ; i ++ ) { if ( regno_reg_rtx [ i ] != const0_rtx ) { machine_mode mode = PSEUDO_REGNO_MODE ( i ) ; machine_mode split = maybe_split_mode ( mode ) ; if ( split != VOIDmode ) mode =


<s> HOST_WIDE_INT pa_compute_frame_size ( poly_int64 size , int * fregs_live ) { int freg_saved = <NUM_LIT> ; int i , j ; size = ( size + UNITS_PER_WORD - <NUM_LIT> ) & ~ ( UNITS_PER_WORD - <NUM_LIT> ) ; if ( size || frame_pointer_needed ) size += pa_starting_frame_offset ( ) ; if ( DO_FRAME_NOTES && crtl -> calls_eh_return ) { unsigned int i ; for ( i = <NUM_LIT> ; EH_RETURN_DATA_REGNO ( i ) != INVALID_REGNUM ; ++ i ) continue ; size += i * UNITS_PER_WORD ; } for ( i = <NUM_LIT> , j = frame_pointer_needed ? <NUM_LIT> : <NUM_LIT> ; i >= j ; i -- ) if ( df_regs_ever_live_p ( i ) ) size += UNITS_PER_WORD ; for ( i = FP_SAVED_REG_LAST ; i >= FP_SAVED_REG_FIRST ; i -= FP_REG_STEP ) if ( df_regs_ever_live_p ( i ) || ( ! TARGET_64BIT && df_regs_ever_live_p ( i + <NUM_LIT> ) ) ) { freg_saved = <NUM_LIT> ; size += <NUM_LIT> ; } if ( freg_saved )


<s> Instruction * Root = I ; Value * Load = tryCreateMaskedGatherOffset ( I , Ptr , Root , Builder ) ; if ( ! Load ) Load = tryCreateMaskedGatherBase ( I , Ptr , Builder ) ; if ( ! Load ) return nullptr ; if ( ! isa < UndefValue > ( PassThru ) && ! match ( PassThru , m_Zero ( ) ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << <STR_LIT> ) ; Load = Builder . CreateSelect ( Mask , Load , PassThru


<s> unsigned RegNum = <ISA_LIT>RegisterInfo :: getRegisterNumbering ( CSI [ i ] . getReg ( ) ) ; if ( CSI [ i ] . getRegClass ( ) == <STR_LIT> ) CPUBitmask |= ( <NUM_LIT> << RegNum ) ; else FPUBitmask |= ( <NUM_LIT> << RegNum ) ; } if ( RI . hasFP ( * MF ) ) CPUBitmask |= ( <NUM_LIT> << <ISA_LIT>RegisterInfo :: getRegisterNumbering ( RI . getFrameRegister ( * MF ) ) ) ; if ( MFI -> hasCalls ( ) ) CPUBitmask |= ( <NUM_LIT> << <ISA_LIT>RegisterInfo :: getRegisterNumbering ( RI . getRARegister ( ) ) ) ; O << <STR_LIT> ; printHex32 ( CPUBitmask ,


<s> addPass ( create<ISA_LIT>ISelDag ( get<ISA_LIT>TargetMachine ( ) , getOptLevel ( ) ) ) ; return false


<s> rtl_opt_pass * make_pass_shorten_memrefs ( gcc :: context * ctxt ) { return new pass_shorten_memrefs ( ctxt


<s> bool isValid ( ) const { return Valid


<s> bool <ISA_LIT>InstrInfo :: AnalyzeBranch ( MachineBasicBlock & MBB , MachineBasicBlock * & TBB , MachineBasicBlock * & FBB , SmallVectorImpl < MachineOperand > & Cond , bool AllowModify ) const { SmallVector < MachineInstr * , <NUM_LIT> > CondBranches ; return AnalyzeBranchImpl ( MBB , TBB , FBB , Cond ,


<s> if ( OpNo >= array_lengthof ( InputUsed ) ) { UseBuildVector = true ; break ; } Mask . push_back ( Idx + OpNo * NumLaneElems ) ; } if ( UseBuildVector ) { SmallVector < SDValue , <NUM_LIT> > SVOps ; for ( unsigned i = <NUM_LIT> ; i != NumLaneElems ; ++ i ) { int Idx = SVOp -> getMaskElt ( i + LaneStart ) ; if ( Idx < <NUM_LIT> ) { SVOps . push_back ( DAG . getUNDEF ( EltVT ) ) ; continue ; } int Input = Idx / NumElems ; Idx -= Input * NumElems ; SVOps . push_back ( DAG . getNode ( <STR_LIT> , dl , EltVT , SVOp -> getOperand ( Input ) , DAG . getIntPtrConstant ( Idx ) ) ) ; } Output [ l ] = DAG . getNode ( <STR_LIT> , dl , NVT , & SVOps [ <NUM_LIT> ] , SVOps . size ( ) ) ; } else if ( InputUsed [ <NUM_LIT> ] < <NUM_LIT> ) { Output [ l ] = DAG . getUNDEF ( NVT ) ; } else { SDValue Op0 = Extract128BitVector ( SVOp -> getOperand ( InputUsed [ <NUM_LIT> ] / <NUM_LIT> ) , ( InputUsed [ <NUM_LIT> ] % <NUM_LIT> ) * NumLaneElems , DAG , dl ) ; SDValue Op1 = ( InputUsed [ <NUM_LIT> ] < <NUM_LIT> ) ? DAG . getUNDEF ( NVT ) : Extract128BitVector ( SVOp -> getOperand ( InputUsed [ <NUM_LIT> ] / <NUM_LIT> ) , ( InputUsed [ <NUM_LIT> ] % <NUM_LIT> ) * NumLaneElems , DAG


<s> unsigned <ISA_LIT>RegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { const TargetFrameLowering * TFI = MF . getTarget ( ) . getFrameLowering ( ) ; return TFI -> hasFP ( MF ) ? FramePtr :


<s> if ( N00 . getOpcode ( ) == <STR_LIT> ) { if ( ! isOneConstant ( N0 . getOperand ( <NUM_LIT> ) ) ) return SDValue ( ) ; return DAG . getNode ( <STR_LIT> , dl , VT , DAG . getNode ( <STR_LIT> , dl , VT , N00 . getOperand ( <NUM_LIT> ) , N00 . getOperand ( <NUM_LIT> ) ) , DAG . getConstant ( <NUM_LIT> , dl , VT ) ) ; } } if ( N0 . getOpcode ( ) == <STR_LIT> && N0 . hasOneUse ( ) && N0 . getOperand ( <NUM_LIT> ) . hasOneUse ( ) ) { SDValue N00 = N0 . getOperand ( <NUM_LIT> ) ; if ( N00 . getOpcode ( ) == <STR_LIT> ) { return DAG . getNode ( <STR_LIT> , dl , VT , DAG . getNode ( <STR_LIT> , dl , VT , N00 . getOperand ( <NUM_LIT> ) , N00 . getOperand ( <NUM_LIT> ) ) , DAG . getConstant ( <NUM_LIT> , dl , VT ) ) ; } } if ( SDValue NewCMov = combineToExtendCMOV ( N , DAG ) ) return NewCMov ; if ( DCI . isBeforeLegalizeOps ( ) ) if ( SDValue V = combineExtSetcc ( N , DAG , Subtarget ) ) return V ; if ( SDValue V = combineToExtendVectorInReg ( N , DAG , DCI , Subtarget ) ) return V ; if ( SDValue V = combineToExtendBoolVectorInReg ( N , DAG , DCI , Subtarget ) ) return V ; if ( VT . isVector ( ) ) if ( SDValue R = PromoteMaskArithmetic ( N , DAG , Subtarget ) ) return R ; if ( SDValue NewAdd = promoteExtBeforeAdd ( N , DAG , Subtarget ) ) return NewAdd ; if ( SDValue R = combineOrCmpEqZeroToCtlzSrl ( N , DAG , DCI , Subtarget ) ) return R ; if ( N0 . getOpcode ( ) == <STR_LIT> && N0 . getValueSizeInBits ( ) == <NUM_LIT> && VT . getScalarSizeInBits ( ) == N0 . getOperand ( <NUM_LIT> ) . getScalarValueSizeInBits ( ) ) { SDValue N00 = N0 . getOperand


<s> return std :: make_unique < <ISA_LIT>ELFObjectWriter > (


<s> for ( auto Use : Prev -> uses ( ) ) if ( Use . isKill ( ) ) { BuildMI ( MBB , MBBI , MBBI -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addReg ( Use . getReg ( ) , RegState :: Kill ) . add ( predOps ( <STR_LIT> ) ) . copyImplicitOps ( * MBBI ) ; MBB . erase ( MBBI ) ; MBB . erase ( Prev )


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT>


<s> bool lowerOperand ( const MachineOperand & MO


<s> static int unspec_fcmla ( int rot ) { switch ( rot ) { case <NUM_LIT> :


<s> EVT VT = N -> getOperand ( <NUM_LIT> ) -> getValueType ( <NUM_LIT> ) ; bool Is128Bit = VT . getSizeInBits ( ) == <NUM_LIT> ; SmallVector < SDValue , <NUM_LIT> > Regs ( N -> op_begin ( ) + <NUM_LIT> , N -> op_begin ( ) +


<s> void get_aligned_mem ( rtx ref , rtx * paligned_mem , rtx * pbitnum ) { rtx base ; HOST_WIDE_INT disp , offset ; gcc_assert ( GET_CODE ( ref ) == MEM ) ; if ( reload_in_progress && ! memory_address_p ( GET_MODE ( ref ) , XEXP ( ref , <NUM_LIT> ) ) ) { base = find_replacement ( & XEXP ( ref , <NUM_LIT> ) ) ; gcc_assert ( memory_address_p ( GET_MODE ( ref ) , base ) ) ; } else base = XEXP ( ref , <NUM_LIT> ) ; if ( GET_CODE ( base ) == PLUS ) disp = INTVAL ( XEXP ( base , <NUM_LIT> ) ) , base = XEXP ( base , <NUM_LIT> ) ; else disp = <NUM_LIT> ; if ( MEM_ALIGN ( ref ) >= <NUM_LIT> ) offset = <NUM_LIT> ; else offset = disp & <NUM_LIT> ; * paligned_mem = widen_memory_access ( ref ,


<s> bool Ignored ; unsigned NumHex ; APFloat APF = getAPFloat ( ) ; switch ( Kind ) { default : llvm_unreachable ( <STR_LIT> ) ; case VK_<ISA_LIT>_HALF_PREC_FLOAT : OS << <STR_LIT> ; NumHex = <NUM_LIT> ; APF . convert ( APFloat :: IEEEhalf ( ) , APFloat :: rmNearestTiesToEven , & Ignored ) ; break ; case VK_<ISA_LIT>_SINGLE_PREC_FLOAT : OS << <STR_LIT> ; NumHex = <NUM_LIT> ; APF . convert ( APFloat :: IEEEsingle ( ) , APFloat :: rmNearestTiesToEven , & Ignored ) ; break ; case VK_<ISA_LIT>_DOUBLE_PREC_FLOAT : OS << <STR_LIT> ; NumHex = <NUM_LIT> ; APF . convert ( APFloat :: IEEEdouble ( ) , APFloat :: rmNearestTiesToEven , & Ignored ) ; break ; } APInt API = APF . bitcastToAPInt ( ) ; std :: string HexStr ( utohexstr ( API . getZExtValue ( ) ) ) ; if ( HexStr . length ( ) < NumHex ) OS << std :: string ( NumHex - HexStr . length ( ) , '0' ) ; OS << utohexstr ( API .


<s> for ( ; * template ; template ++ ) if ( * template == '\n' ) count ++ ; return


<s> void <ISA_LIT>AsmPrinter :: EmitInstruction ( const MachineInstr * MI ) { MCInst TmpInst


<s> assert ( <ISA_LIT>MCInstrInfo :: isExtendable ( MCII , MCI ) || <ISA_LIT>MCInstrInfo :: isExtended ( MCII , MCI ) ) ; if ( <ISA_LIT>MCInstrInfo :: isExtentSigned ( MCII , MCI ) ) return - ( <NUM_LIT> << ( <ISA_LIT>MCInstrInfo :: getExtentBits ( MCII , MCI ) - <NUM_LIT> ) ) ; return <NUM_LIT>


<s> void <ISA_LIT>InstPrinter :: print<ISA_LIT>P2AlignOperand ( const MCInst * MI , unsigned


<s> if ( DCI . isBeforeLegalizeOps ( ) || ! Subtarget -> hasExtractInsert ( ) ) return SDValue ( ) ; SDValue ShiftRight = N -> getOperand ( <NUM_LIT> ) , Mask = N -> getOperand ( <NUM_LIT> ) ; unsigned ShiftRightOpc = ShiftRight . getOpcode ( ) ; if ( ShiftRightOpc != <STR_LIT> && ShiftRightOpc != <STR_LIT> ) return SDValue ( ) ; ConstantSDNode * CN ; if ( ! ( CN = dyn_cast < ConstantSDNode > ( ShiftRight . getOperand ( <NUM_LIT> ) ) ) ) return SDValue ( ) ; uint64_t Pos = CN -> getZExtValue ( ) ; uint64_t SMPos , SMSize ; if ( ! ( CN = dyn_cast < ConstantSDNode > ( Mask ) ) || ! isShiftedMask ( CN -> getZExtValue ( ) , SMPos , SMSize ) ) return SDValue ( ) ; EVT ValTy = N -> getValueType ( <NUM_LIT> ) ; if ( SMPos != <NUM_LIT> || Pos + SMSize > ValTy .

getSizeInBits ( ) ) return SDValue ( ) ;


<s> } if ( current_frame_info . save_lr ) emit_insn ( gen_movsi_push ( stack_pointer_rtx , gen_rtx_REG ( Pmode , RETURN_ADDR_REGNUM ) ) ) ; frame_size = ( current_frame_info . total_size - ( current_frame_info . pretend_size + current_frame_info . reg_size ) ) ; if ( frame_size == <NUM_LIT> ) ; else if ( frame_size <= <NUM_LIT> ) emit_insn ( gen_addsi3 ( stack_pointer_rtx , stack_pointer_rtx , GEN_INT ( - frame_size ) ) ) ; else { rtx tmp = gen_rtx_REG ( Pmode , PROLOGUE_TMP_REGNUM ) ; emit_insn ( gen_movsi ( tmp , GEN_INT ( frame_size ) ) ) ; emit_insn ( gen_subsi3 ( stack_pointer_rtx , stack_pointer_rtx , tmp ) ) ; } if ( frame_pointer_needed ) emit_insn ( gen_movsi ( frame_pointer_rtx , stack_pointer_rtx ) ) ; if ( crtl -> profile ) emit_insn ( gen_movsi_push ( stack_pointer_rtx , gen_rtx_REG ( Pmode , RETURN_ADDR_REGNUM ) ) ) ; if ( pic_reg_used ) { m32r_load_pic_register ( )


<s> } RTLIB :: Libcall LC ; LC = RTLIB :: getFPROUND ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) , Op . getValueType ( ) ) ; SDValue SrcVal = Op . getOperand ( <NUM_LIT> ) ; MakeLibCallOptions CallOptions


<s> if ( MFI . isVRegStackified ( MI . getOperand ( OpIdx1 ) . getReg ( ) ) || MFI . isVRegStackified ( MI . getOperand ( OpIdx2 ) . getReg ( ) ) ) return nullptr ; return TargetInstrInfo :: commuteInstructionImpl ( MI , NewMI , OpIdx1


<s> EVT VT = N -> getValueType ( <NUM_LIT> ) ; SDLoc dl ( N ) ; unsigned EltSize = VT . getScalarSizeInBits ( ) / <NUM_LIT> ; unsigned NumElts = VT . getVectorNumElements ( ) ; MVT TruncVT = <STR_LIT> ( EltSize ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; for ( unsigned i = <NUM_LIT> ; i != NumElts ; ++ i ) { ConstantSDNode * C = cast < ConstantSDNode > ( N -> getOperand ( i ) ) ; const APInt & CInt = C


<s> unsigned LaneWidth = getVectorTyFromPredicateVector ( VecVT ) . getScalarSizeInBits ( ) / <NUM_LIT> ; SDValue Shift = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Conv , DAG . getConstant ( Lane * LaneWidth , dl , <STR_LIT> ) ) ; return Shift


<s> unsigned <ISA_LIT>ELFObjectWriter :: getRelocType ( MCContext & Ctx , const MCValue &

Target , const MCFixup & Fixup , bool IsPCRel ) const {


<s> int first_reg = crtl -> args . info . words ; rtx address ; int regno ; for ( regno = first_reg ; regno < SPARC_INT_ARG_MAX ; regno ++ ) emit_move_insn ( gen_rtx_MEM ( word_mode , gen_rtx_PLUS ( Pmode , frame_pointer_rtx , GEN_INT ( FIRST_PARM_OFFSET ( <NUM_LIT> ) + ( UNITS_PER_WORD * regno ) ) ) ) , gen_rtx_REG ( word_mode , SPARC_INCOMING_INT_ARG_FIRST + regno ) ) ; address = gen_rtx_PLUS ( Pmode , frame_pointer_rtx , GEN_INT ( FIRST_PARM_OFFSET ( <NUM_LIT> ) + UNITS_PER_WORD * first_reg ) ) ; return


<s> bool isDoneAddArg ( void ) { return _isDoneAddArg


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { getLoopAnalysisUsage ( AU )


<s> int regs = MT_NUM_ARG_REGS - * cum ; * pretend_size = regs < <NUM_LIT> ? <NUM_LIT> : GET_MODE_SIZE ( SImode ) * regs ; if ( no_rtl ) return ; for ( regno = * cum ; regno < MT_NUM_ARG_REGS ; regno ++ ) { rtx reg = gen_rtx_REG ( SImode , FIRST_ARG_REGNUM +


<s> switch ( VT . SimpleTy ) { case <STR_LIT> : Shift = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; Imm = CurDAG -> getTargetConstant ( ImmVal & <NUM_LIT> , DL , <STR_LIT> ) ; return true ; case <STR_LIT> : if ( ( ImmVal & <NUM_LIT> ) == ImmVal ) { Shift = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; Imm = CurDAG -> getTargetConstant ( ImmVal , DL , <STR_LIT> ) ; return true ; } else if ( ( ImmVal & <NUM_LIT> ) == <NUM_LIT> ) { Shift = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; Imm = CurDAG -> getTargetConstant ( ( ImmVal >> <NUM_LIT> ) & <NUM_LIT> , DL , <STR_LIT> ) ; return true ; } break ; case <STR_LIT> : case <STR_LIT> : if ( ( ImmVal & <NUM_LIT> ) == ImmVal ) { Shift = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; Imm = CurDAG -> getTargetConstant ( ImmVal , DL , <STR_LIT> ) ; return true ; } else if ( ( ImmVal & <NUM_LIT> ) == ImmVal ) { Shift = CurDAG -> getTargetConstant ( <NUM_LIT> ,


<s> bool <ISA_LIT>InstrInfo :: mayBeCurLoad ( const MachineInstr & MI ) const { auto & HST = MI . getParent ( ) -> getParent

( ) -> getSubtarget < <ISA_LIT>Subtarget > ( ) ;


<s> SDValue Victim = N -> getOperand ( <NUM_LIT> ) ; switch ( Op . getOpcode ( ) ) { case <STR_LIT> : Opc8 = <STR_LIT> ; break ; case <STR_LIT> : Opc8 = <STR_LIT> ; ShiftAmount = ShiftAmount % VT . getSizeInBits ( ) ; break ; case <STR_LIT> : Opc8 = <STR_LIT> ; ShiftAmount = ShiftAmount % VT . getSizeInBits ( ) ; break ; case <STR_LIT> : Opc8 = <STR_LIT> ; break ; case <STR_LIT> : Opc8 = <STR_LIT> ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } if ( VT . getSizeInBits ( ) == <NUM_LIT> ) { if ( Op . getOpcode ( ) == <STR_LIT> && <NUM_LIT> <= ShiftAmount && ShiftAmount < <NUM_LIT> ) { Victim = DAG . getNode ( <STR_LIT> , dl , VT , Victim ) ; Victim = DAG . getNode ( <STR_LIT> , dl , VT , Victim , DAG . getConstant ( <NUM_LIT> , dl , VT ) ) ; ShiftAmount -= <NUM_LIT> ; } else if ( Op . getOpcode ( ) == <STR_LIT> && <NUM_LIT> <= ShiftAmount && ShiftAmount < <NUM_LIT> ) { Victim = DAG . getNode ( <STR_LIT> , dl , VT , Victim ) ; Victim = DAG . getNode ( <STR_LIT> , dl , VT , Victim , DAG . getConstant ( <NUM_LIT> , dl , VT ) ) ; ShiftAmount -= <NUM_LIT> ; } else if ( Op . getOpcode ( ) == <STR_LIT> && ShiftAmount == <NUM_LIT> ) { Victim = DAG . getNode ( <STR_LIT> , dl , VT , Victim ) ; ShiftAmount = <NUM_LIT> ; } else if ( Op . getOpcode ( ) == <STR_LIT> && ShiftAmount == <NUM_LIT> ) { Victim = DAG . getNode ( <STR_LIT> , dl , VT , Victim ) ; ShiftAmount = <NUM_LIT> ; } else if ( Op . getOpcode ( ) == <STR_LIT> && ShiftAmount == <NUM_LIT> ) { Victim = DAG . getNode ( <STR_LIT> , dl , VT , Victim ) ; ShiftAmount = <NUM_LIT> ; } } else if ( VT . getSizeInBits ( ) == <NUM_LIT> ) { if ( <NUM_LIT> <= ShiftAmount && ShiftAmount < <NUM_LIT> ) switch ( Op . getOpcode ( ) ) { case <STR_LIT> : Victim = DAG . getNode ( <STR_LIT> , dl , VT ,


<s> bool <ISA_LIT>DAGToDAGISel :: selectAddr16 ( SDNode * Parent , SDValue N , SDValue &

Base , SDValue & Offset , SDValue & Alias ) {


<s> bool Signed = N -> getOpcode ( ) == <STR_LIT> ; unsigned Opc = Signed ? <STR_LIT> : <STR_LIT> ; SDValue Clamp = CurDAG -> getTargetConstant ( <NUM_LIT> , SL , <STR_LIT> ) ; SDValue Ops [ ] = { N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , Clamp } ; CurDAG -> SelectNodeTo ( N , Opc , N


<s> if ( DCI . isBeforeLegalize ( ) ) return SDValue ( ) ; if ( Subtarget -> has<ISA_LIT>32 ( ) && N -> getValueType ( <NUM_LIT> ) == <STR_LIT> && SelectMsub ( N , & DAG ) ) return SDValue ( N , <NUM_LIT> ) ; return SDValue


<s> extern __inline int __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) __crc_w_w_w ( int _1 , int _2 ) { return ( int ) __builtin_loongarch_crc_w_w_w ( ( int


<s> return __builtin_mve_vrev32q_m_sv16qi ( __arm_vuninitializedq_s8 ( ) , __a


<s> return ( uint32x2_t ) __builtin_aarch64_lflooruv2sfv2si


<s> SDValue <ISA_LIT>SelectionDAGInfo :: EmitTargetCodeForMemmove ( SelectionDAG & DAG , const SDLoc & DL , SDValue Chain , SDValue Op1 , SDValue Op2 , SDValue Op3 , unsigned Align , bool IsVolatile , MachinePointerInfo

DstPtrInfo , MachinePointerInfo SrcPtrInfo ) const {


<s> static rtx xtensa_function_arg ( cumulative_args_t cum , const function_arg_info


<s> uint64_t MaxAlign = MFI -> getMaxAlignment ( ) ; unsigned StackAlign = getStackAlignment ( ) ; if ( MF . getFunction ( ) -> hasFnAttribute ( <STR_LIT> ) ) { if ( MFI -> hasCalls ( ) ) MaxAlign = ( StackAlign > MaxAlign ) ? StackAlign : MaxAlign ; else if ( MaxAlign < SlotSize ) MaxAlign = SlotSize ; } return


<s> mclass = GET_MODE_CLASS ( mode ) ; if ( type && TREE_CODE ( type ) == VECTOR_TYPE ) { if ( TREE_CODE ( TREE_TYPE ( type ) ) == REAL_TYPE ) { gcc_assert ( mode == BLKmode ) ; } else { gcc_assert ( mode != BLKmode ) ; mclass = MODE_FLOAT ; } } switch ( mclass ) { case MODE_FLOAT : case MODE_COMPLEX_FLOAT : case MODE_VECTOR_INT : if ( TARGET_ARCH64 && TARGET_FPU && named ) { if ( slotno >= SPARC_FP_ARG_MAX ) return - <NUM_LIT> ; regno = SPARC_FP_ARG_FIRST + slotno * <NUM_LIT> ; if ( GET_MODE_SIZE ( mode ) <= <NUM_LIT> ) regno ++ ; break ; } case MODE_INT : case MODE_COMPLEX_INT : if ( slotno >= SPARC_INT_ARG_MAX ) return - <NUM_LIT> ; regno = regbase + slotno ; break ; case MODE_RANDOM : if ( mode == VOIDmode ) return - <NUM_LIT> ; gcc_assert ( mode == BLKmode ) ; if ( TARGET_ARCH32 || ! type || ( TREE_CODE ( type ) != VECTOR_TYPE && TREE_CODE ( type ) != RECORD_TYPE ) ) { if ( slotno >= SPARC_INT_ARG_MAX ) return - <NUM_LIT> ; regno = regbase + slotno ; } else { int intregs_p = <NUM_LIT> , fpregs_p = <NUM_LIT> , packed_p = <NUM_LIT> ; if ( TREE_CODE ( type ) == VECTOR_TYPE ) fpregs_p = <NUM_LIT> ; else scan_record_type ( type , & intregs_p , & fpregs_p , & packed_p ) ; if ( packed_p || ! named ) fpregs_p = <NUM_LIT> ,


<s> BuildMI ( MBB , InsertBefore , DL , TII -> get ( <STR_LIT> ) , Out ) . addReg ( Ssub0 ) . addReg ( Ssub1 ) . addImm ( <NUM_LIT> ) . add ( predOps ( <STR_LIT> ) ) ; return Out


<s> case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case


<s> <ISA_LIT>PostAllocationFixups ( ) : MachineFunctionPass ( ID


<s> unsigned sx = fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) ; DecodeStatus status ; if ( isLoad ) { status = DecodeSX ( MI , sx , Address , Decoder ) ; if ( status != MCDisassembler :: Success ) return status ; } status = DecodeAS ( MI , insn , Address , Decoder ) ; if ( status != MCDisassembler :: Success ) return status ; if ( ! isLoad ) { status = DecodeSX ( MI , sx , Address , Decoder ) ; if ( status != MCDisassembler :: Success ) return status ; } return MCDisassembler ::


<s> return isSingleSpacedVectorList ( ) && VectorList . Count == <NUM_LIT> && <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] .


<s> __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT> ( b ) , <STR_LIT> ( c ) : ) ; return


<s> const TargetRegisterClass * TRC = isThumb2 ? ( const TargetRegisterClass * ) & <STR_LIT> : ( const TargetRegisterClass * ) & <STR_LIT> ; unsigned storesuccess = MRI . createVirtualRegister ( TRC ) ; BB -> addSuccessor ( loopMBB ) ; BB = loopMBB ; if ( isThumb2 ) { AddDefaultPred ( BuildMI ( BB , dl , TII -> get ( <STR_LIT> ) ) . addReg ( destlo , RegState :: Define ) . addReg ( desthi , RegState :: Define ) . addReg ( ptr ) ) ; } else { unsigned GPRPair0 = MRI . createVirtualRegister ( & <STR_LIT> ) ; AddDefaultPred ( BuildMI ( BB , dl , TII -> get ( <STR_LIT> ) ) . addReg ( GPRPair0 , RegState :: Define ) . addReg ( ptr ) ) ; BuildMI ( BB , dl , TII -> get ( TargetOpcode :: COPY ) , destlo ) . addReg ( GPRPair0 , <NUM_LIT> , <STR_LIT> ) ; BuildMI ( BB , dl , TII -> get ( TargetOpcode :: COPY ) , desthi ) . addReg ( GPRPair0 , <NUM_LIT> , <STR_LIT> ) ; } unsigned StoreLo , StoreHi ; if ( IsCmpxchg ) { for ( unsigned i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) { AddDefaultPred ( BuildMI ( BB , dl , TII -> get ( isThumb2 ? <STR_LIT> : <STR_LIT> ) ) . addReg ( i == <NUM_LIT> ? destlo : desthi ) . addReg ( i == <NUM_LIT> ? vallo : valhi ) ) ; BuildMI ( BB , dl , TII -> get ( isThumb2 ? <STR_LIT> : <STR_LIT> ) ) . addMBB ( exitMBB ) . addImm ( <STR_LIT> ) . addReg ( <STR_LIT> ) ; BB -> addSuccessor ( exitMBB ) ; BB -> addSuccessor ( i == <NUM_LIT> ? contBB : cont2BB ) ; BB = ( i == <NUM_LIT> ? contBB : cont2BB ) ; } StoreLo = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; StoreHi = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; } else if ( Op1 ) { unsigned tmpRegLo = MRI . createVirtualRegister ( TRC ) ; AddDefaultPred ( BuildMI ( BB , dl , TII -> get ( Op1 ) , tmpRegLo ) . addReg ( destlo ) . addReg ( vallo ) ) . addReg ( NeedsCarry ? <STR_LIT> : <NUM_LIT> , getDefRegState ( NeedsCarry ) ) ; unsigned tmpRegHi = MRI . createVirtualRegister ( TRC ) ; AddDefaultPred ( BuildMI ( BB , dl , TII -> get ( Op2 ) , tmpRegHi ) . addReg ( desthi ) . addReg ( valhi ) ) . addReg ( IsMinMax ? <STR_LIT> : <NUM_LIT> , getDefRegState ( IsMinMax ) ) ; StoreLo =


<s> bool <ISA_LIT>DAGToDAGISel :: matchAddressRecursively ( SDValue N , <ISA_LIT>ISelAddressMode & AM , unsigned Depth ) { SDLoc dl ( N


<s> SmallVector < CCValAssign , <NUM_LIT> > RVLocs ; MachineFunction & MF = DAG . getMachineFunction ( ) ; CCState CCInfo ( CallConv , IsVarArg , MF , RVLocs , * DAG . getContext ( ) ) ; CCInfo . CheckReturn ( Outs , RetCC_<ISA_LIT>EABI ) ; SDValue Flag ; SmallVector < SDValue , <NUM_LIT> > RetOps ( <NUM_LIT> , Chain ) ; for ( unsigned i = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i ) { SDValue Val = OutVals [ i ] ; CCValAssign & VA = RVLocs [ i ] ; assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; if ( RVLocs [ i ] . getValVT ( ) != RVLocs [ i ] . getLocVT ( ) ) Val = DAG . getNode ( <STR_LIT> , DL , RVLocs [ i ] . getLocVT ( ) , Val ) ; Chain = DAG . getCopyToReg ( Chain , DL , VA . getLocReg ( )


<s> bool <ISA_LIT>AsmParser :: classifySymbolRef ( const MCExpr * Expr , <ISA_LIT>MCExpr :: VariantKind & Kind , int64_t & Addend ) { Kind = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ; Addend = <NUM_LIT> ; if ( const <ISA_LIT>MCExpr * RE = dyn_cast < <ISA_LIT>MCExpr > ( Expr ) ) { Kind = RE -> getKind ( ) ; Expr = RE -> getSubExpr ( ) ; } if ( isa < MCConstantExpr > ( Expr ) || isa < MCSymbolRefExpr > ( Expr ) ) return true ; const MCBinaryExpr * BE = dyn_cast < MCBinaryExpr > ( Expr ) ; if ( ! BE


<s> TargetTransformInfo <ISA_LIT>TargetMachine :: getTargetTransformInfo ( const Function & F )


<s> } else { NopInst . setOpcode ( <STR_LIT> ) ; NopInst . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ; NopInst . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ; NopInst . addOperand ( MCOperand :: createImm ( <STR_LIT> ) ) ; NopInst . addOperand ( MCOperand :: createReg ( <NUM_LIT> ) ) ; NopInst . addOperand ( MCOperand ::


<s> SDNode * <ISA_LIT>DAGToDAGISel :: getGlobalBaseReg ( ) { unsigned GlobalBaseReg = Subtarget -> getInstrInfo ( ) -> getGlobalBaseReg


<s> SDLoc DL ( Op ) ; EVT VT = Op . getValueType ( ) ; APInt SplatBits , SplatUndef ; unsigned SplatBitSize ; bool HasAnyUndefs ; if ( BVN -> isConstantSplat ( SplatBits , SplatUndef , SplatBitSize , HasAnyUndefs ) ) { if ( SplatBitSize <= <NUM_LIT> ) { EVT NeonMovVT ; unsigned Imm = <NUM_LIT> ; unsigned OpCmode = <NUM_LIT> ; if ( isNeonModifiedImm ( SplatBits . getZExtValue ( ) , SplatUndef . getZExtValue ( ) , SplatBitSize , DAG , VT . is128BitVector ( ) , Neon_Mov_Imm , NeonMovVT , Imm , OpCmode ) ) { SDValue ImmVal = DAG . getTargetConstant ( Imm , <STR_LIT> ) ; SDValue OpCmodeVal = DAG . getConstant ( OpCmode , <STR_LIT> ) ; if ( ImmVal . getNode ( ) && OpCmodeVal . getNode ( ) ) { SDValue NeonMov = DAG . getNode ( <STR_LIT> , DL , NeonMovVT , ImmVal , OpCmodeVal ) ; return DAG . getNode ( <STR_LIT> , DL , VT , NeonMov ) ; } } uint64_t NegatedImm = ( ~ SplatBits ) . getZExtValue ( ) ; if ( isNeonModifiedImm ( NegatedImm , SplatUndef . getZExtValue ( ) , SplatBitSize , DAG , VT . is128BitVector ( ) , Neon_Mvn_Imm , NeonMovVT , Imm , OpCmode ) ) { SDValue ImmVal = DAG . getTargetConstant ( Imm , <STR_LIT> ) ; SDValue OpCmodeVal = DAG . getConstant ( OpCmode , <STR_LIT> ) ; if ( ImmVal . getNode ( ) && OpCmodeVal . getNode ( ) ) { SDValue NeonMov = DAG . getNode ( <STR_LIT> , DL , NeonMovVT , ImmVal , OpCmodeVal ) ; return DAG . getNode ( <STR_LIT> , DL , VT , NeonMov ) ; } } if ( ( ( VT == <STR_LIT> || VT == <STR_LIT> ) && SplatBitSize == <NUM_LIT> ) || ( VT == <STR_LIT> && SplatBitSize == <NUM_LIT> ) ) { APFloat RealVal ( SplatBitSize == <NUM_LIT> ? APFloat :: IEEEsingle : APFloat :: IEEEdouble , SplatBits ) ; uint32_t ImmVal ; if ( A64Imms :: isFPImm ( RealVal ,


<s> return ( __m64 ) __builtin_arm_wsadhz ( ( __v4hi )


<s> const <ISA_LIT>TargetObjectFile * TLOF = static_cast < const <ISA_LIT>TargetObjectFile * > ( getTargetMachine ( ) . getObjFileLowering ( ) ) ; if ( TLOF -> IsGlobalInSmallSection ( GV , getTargetMachine ( ) ) ) return getAddrGPRel ( N , SDLoc ( N ) , Ty , DAG ) ; return getAddrNonPIC ( N , SDLoc ( N ) , Ty , DAG ) ; } if ( GV -> hasInternalLinkage ( ) || ( GV -> hasLocalLinkage ( ) && ! isa < Function > ( GV ) ) ) return getAddrLocal ( N , SDLoc ( N ) , Ty , DAG , ABI . IsN32 ( ) ||


<s> MF -> RenumberBlocks ( ) ; bool MadeChange = false ; std :: vector < MachineInstr * > CPEMIs ; if ( ! MCP -> isEmpty ( ) ) doInitialPlacement ( CPEMIs ) ; initPICLabelUId ( CPEMIs . size ( ) ) ; initializeFunctionInfo ( CPEMIs ) ; CPEMIs . clear ( ) ; LLVM_DEBUG ( dumpBBs ( ) ) ; MadeChange |= removeUnusedCPEntries ( ) ; unsigned NoCPIters = <NUM_LIT> , NoBRIters = <NUM_LIT> ; ( void ) NoBRIters ; while ( true ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << NoCPIters << '\n' ) ; bool CPChange = false ; for ( unsigned I = <NUM_LIT> , E = CPUsers . size ( ) ; I !=

E ; ++ I ) CPChange |= handleConstantPoolUser ( I ) ;