<s> MachineBasicBlock * StartMBB = MBB ; MachineBasicBlock * DoneMBB = splitBlockBefore ( MI , MBB ) ; MachineBasicBlock * LoopMBB = emitBlockAfter ( StartMBB ) ; MBB -> addSuccessor ( LoopMBB ) ; MBB = LoopMBB ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) , This1Reg ) . addReg ( Start1Reg ) . addMBB ( StartMBB ) . addReg ( End1Reg ) . addMBB ( LoopMBB ) ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) , This2Reg ) . addReg ( Start2Reg ) . addMBB ( StartMBB ) . addReg ( End2Reg ) . addMBB ( LoopMBB ) ; BuildMI ( MBB , DL , TII -> get ( TargetOpcode :: COPY ) , <STR_LIT> ) . addReg ( CharReg ) ; BuildMI ( MBB , DL , TII -> get ( Opcode ) ) . addReg ( End1Reg , RegState :: Define ) . addReg ( End2Reg , RegState :: Define ) . addReg ( This1Reg ) . addReg ( This2Reg ) ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) ) . addImm ( <STR_LIT> ) . addImm ( <STR_LIT> ) . addMBB ( LoopMBB ) ; MBB -> addSuccessor ( LoopMBB ) ; MBB -> addSuccessor ( DoneMBB ) ; DoneMBB -> addLiveIn ( <STR_LIT> ) ; MI -> eraseFromParent


<s> GCNSubtarget :: Generation Generation = ST . getGeneration ( ) ; if ( Generation <= <ISA_LIT>Subtarget :: SOUTHERN_ISLANDS ) return make_unique < <ISA_LIT>Gfx6CacheControl > ( ST ) ; if ( Generation < <ISA_LIT>Subtarget :: GFX10 )

return make_unique < <ISA_LIT>Gfx7CacheControl > ( ST ) ;


<s> FunctionPass * <ISA_LIT>PassConfig :: createTargetRegisterAllocator


<s> if ( is256BitLaneRepeatedShuffleMask ( <STR_LIT> , Mask , Repeated256Mask ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , getV4<ISA_LIT>ShuffleImm8ForMask ( Repeated256Mask , DL , DAG ) ) ; } if ( SDValue Shuf128 = lowerV4X128VectorShuffle ( DL , <STR_LIT> , Mask , Zeroable , V1 , V2 , Subtarget , DAG ) ) return Shuf128 ; if ( SDValue Shift = lowerVectorShuffleAsShift ( DL , <STR_LIT> , V1 , V2 , Mask , Zeroable , Subtarget , DAG ) ) return Shift ; if ( SDValue Rotate = lowerVectorShuffleAsRotate ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return Rotate ; if ( SDValue Rotate = lowerVectorShuffleAsByteRotate ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return Rotate ; if ( SDValue Unpck = lowerVectorShuffleWithUNPCK ( DL , <STR_LIT> , Mask , V1 , V2 , DAG ) ) return Unpck ; if ( SDValue V = lowerVectorShuffleToEXPAND ( DL , <STR_LIT> , Zeroable , Mask , V1 , V2 , DAG , Subtarget ) ) return V ; if ( SDValue Blend = lowerVectorShuffleAsBlend ( DL , <STR_LIT> , V1 , V2 , Mask

, Zeroable , Subtarget , DAG ) ) return Blend ;


<s> virtual StringRef getPassName ( ) const override { return StringRef ( <STR_LIT>


<s> int thumb_shiftable_const ( unsigned HOST_WIDE_INT val ) { unsigned HOST_WIDE_INT mask = <NUM_LIT> ; int i ; val = val & ( unsigned HOST_WIDE_INT ) <NUM_LIT> ; if ( val == <NUM_LIT> ) return <NUM_LIT> ; for ( i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) if ( ( val & ( mask << i ) ) == val ) return <NUM_LIT> ; return <NUM_LIT>


<s> const MCOperand & MO = MI . getOperand ( OpNo ) ; if ( MO . isReg ( ) || MO . isImm ( ) )

return getMachineOpValue ( MI , MO , Fixups , STI ) ;


<s> return IRB . CreatePointerCast ( IRB . CreateConstGEP1_32 ( IRB . CreateCall ( ThreadPointerFunc ) , TlsOffset ) , Type :: getInt8PtrTy ( IRB . getContext ( ) ) -> getPointerTo


<s> static SDValue lowerV16I32VectorShuffle ( SDValue Op , SDValue V1 , SDValue V2 , const <ISA_LIT>Subtarget * Subtarget , SelectionDAG & DAG ) { SDLoc DL ( Op ) ; assert ( V1 . getSimpleValueType ( ) == <STR_LIT> && <STR_LIT> ) ; assert ( V2 . getSimpleValueType ( ) == <STR_LIT> && <STR_LIT>


<s> return ( __m512i ) __builtin_ia32_compresssi512_mask ( ( __v16si ) __A , ( __v16si ) _mm512_setzero_si512 ( ) , (


<s> case PLUS : if ( satisfies_constraint_I ( x ) ) * total = <NUM_LIT> ; else if ( satisfies_constraint_J ( x ) ) * total = <NUM_LIT> ; else * total = COSTS_N_INSNS ( <NUM_LIT> ) ; return true ; default : if ( satisfies_constraint_K ( x ) || satisfies_constraint_L ( x ) ) * total = <NUM_LIT> ; else * total = COSTS_N_INSNS ( <NUM_LIT> ) ; return true ; } case CONST_DOUBLE : * total = COSTS_N_INSNS ( <NUM_LIT> ) ; return true ; case CONST : case SYMBOL_REF : case LABEL_REF : * total = COSTS_N_INSNS ( <NUM_LIT> ) ; return true ; case FMA : * total = COSTS_N_INSNS ( <NUM_LIT> ) ; return true ; case MULT : if ( FLOAT_MODE_P ( mode ) ) * total = COSTS_N_INSNS ( <NUM_LIT> ) ; else if ( GET_MODE_SIZE ( mode ) > <NUM_LIT> ) * total = COSTS_N_INSNS ( <NUM_LIT> ) ; else * total = COSTS_N_INSNS ( <NUM_LIT> ) ; return true ; case PLUS : case MINUS : if ( FLOAT_MODE_P ( mode ) ) { * total = COSTS_N_INSNS ( <NUM_LIT> ) ; return true ; } case ASHIFT : case ASHIFTRT : case LSHIFTRT : * total = COSTS_N_INSNS ( <NUM_LIT> ) ; return true ; case


<s> HasV5TEOps = false ; HasV6Ops = false ; HasV6MOps = false ; HasV6KOps = false ; HasV6T2Ops = false ; HasV7Ops = false ; HasV8Ops = false ; HasV8_1aOps = false ; HasVFPv2 = false ; HasVFPv3 = false ; HasVFPv4 = false ; HasFP<ISA_LIT>v8 = false ; HasNEON = false ; UseNEONForSinglePrecisionFP = false ; UseMulOps = UseFusedMulOps ; SlowFPVMLx = false ; HasVMLxForwarding = false ; SlowFPBrcc = false ; InThumbMode = false ; UseSoftFloat = false ; HasThumb2 = false ; No<ISA_LIT> = false ; IsR9Reserved = ReserveR9 ; UseMovt = false ; SupportsTailCall = false ; HasFP16 = false ; HasD16 = false ; HasHardwareDivide = false ; HasHardwareDivideIn<ISA_LIT> = false ; HasT2ExtractPack = false ; HasDataBarrier = false ; Pref32BitThumb = false ; AvoidCPSRPartialUpdate = false ; AvoidMOVsShifterOperand = false ; HasRAS = false ; HasMPExtension = false ; HasVirtualization = false ; FPOnlySP = false ; HasPerfMon = false ; HasTrustZone = false ; HasCrypto = false ; HasCRC = false ; HasZeroCycleZeroing = false ; AllowsUnalignedMem =


<s> if ( Directive == <STR_LIT> || Directive == <STR_LIT> ) return <NUM_LIT> ; if ( Directive == <STR_LIT> || Directive == <STR_LIT> || Directive == <STR_LIT> || Directive == <STR_LIT> )


<s> Register <ISA_LIT>TargetLowering :: getExceptionSelectorRegister ( const Constant * PersonalityFn ) const { return Subtarget . is<ISA_LIT>64 ( ) ?


<s> RHS_LO = DAG . getConstant ( CN -> getZExtValue ( ) & <NUM_LIT> , HalfVT ) ; RHS_HI = DAG . getConstant ( CN -> getZExtValue ( ) >> <NUM_LIT> & <NUM_LIT> , HalfVT ) ; } else { RHS_LO = DAG . getTargetExtractSubreg ( <STR_LIT> , dl , HalfVT , RHS ) ; RHS_HI = DAG . getTargetExtractSubreg ( <STR_LIT> , dl , HalfVT , RHS ) ; } LO = DAG . getNode ( Opc , dl , HalfVT , LHS_LO , RHS_LO ) ; HI = DAG . getNode ( Opc , dl , HalfVT , LHS_HI , RHS_HI ) ; Res = DAG . getTargetInsertSubreg ( <STR_LIT> , dl , VT


<s> if ( ! getSubExpr ( ) -> evaluateAsRelocatable ( Res , Layout , Fixup ) ) return false ; if ( Res . getSymA ( ) && Res . getSymB ( ) ) { switch ( getKind ( ) ) { default : return true ; case VK_<ISA_LIT>_LO : case VK_<ISA_LIT>_HI : case VK_<ISA_LIT>_PCREL_LO : case


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : replaceMachineInstructionUsage ( MF , MI ) ; RemoveList . push_back ( & MI ) ; break ; } } } for ( auto * MI :


<s> if ( TARGET_VXWORKS_RTP ) return false ; if ( LABEL_REF_NONLOCAL_P ( label ) ) return false ; if ( flag_reorder_blocks_and_partition ) return false ; return true


<s> const MCPhysReg * <ISA_LIT>RegisterInfo :: getCalleeSavedRegsViaCopy ( const MachineFunction * MF )


<s> void neg ( uint64_t & Value ) { Value *= -


<s> CPAddr = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , CPAddr ) ; SDValue Result = DAG . getLoad ( PtrVT , dl , DAG . getEntryNode ( ) , CPAddr , NULL , <NUM_LIT> ) ; SDValue Chain = Result . getValue ( <NUM_LIT> ) ; if ( RelocM == Reloc :: PIC_ ) { SDValue PICLabel = DAG . getConstant ( <ISA_LIT>PCLabelIndex ++ , <STR_LIT> ) ; Result = DAG . getNode ( <STR_LIT> , dl , PtrVT , Result , PICLabel ) ; } if ( Subtarget -> GVIsIndirectSymbol ( GV , RelocM == Reloc :: Static ) ) Result = DAG . getLoad ( PtrVT , dl , Chain , Result , NULL , <NUM_LIT> ) ; return


<s> SDValue Val = Nd . getValue ( ) , Ptr = Nd . getBasePtr ( ) , Chain = Nd . getChain ( ) ; EVT PtrVT = Ptr . getValueType ( ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Val , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Val , DAG .


<s> static int write_header_file ( void ) { write_autogenerated_header ( header_file ) ; fprintf ( header_file , <STR_LIT> ) ; fprintf ( header_file , <STR_LIT> ) ; write_decls ( ) ; fprintf ( header_file , <STR_LIT> ) ; fprintf ( header_file , <STR_LIT> ) ; return <NUM_LIT>


<s> if ( ! AlwaysInline && ( Align & <NUM_LIT> ) != <NUM_LIT> ) return SDValue ( ) ; if ( DstPtrInfo . getAddrSpace ( ) >= <NUM_LIT> || SrcPtrInfo . getAddrSpace ( ) >= <NUM_LIT> ) return SDValue ( ) ; MVT AVT ; if ( Align & <NUM_LIT> ) AVT = <STR_LIT> ; else if ( Align & <NUM_LIT> ) AVT = <STR_LIT> ; else if ( Align & <NUM_LIT> ) AVT = <STR_LIT> ; else AVT = Subtarget -> is64Bit ( ) ? <STR_LIT> : <STR_LIT> ; unsigned UBytes = AVT . getSizeInBits ( ) / <NUM_LIT> ; unsigned CountVal = SizeVal / UBytes ; SDValue Count = DAG . getIntPtrConstant ( CountVal ) ; unsigned BytesLeft = SizeVal % UBytes ; SDValue InFlag ( <NUM_LIT> , <NUM_LIT> ) ; Chain = DAG . getCopyToReg ( Chain , dl , Subtarget -> is64Bit ( ) ? <STR_LIT> : <STR_LIT> , Count , InFlag ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; Chain = DAG . getCopyToReg ( Chain , dl , Subtarget -> is64Bit ( ) ? <STR_LIT> : <STR_LIT> , Dst , InFlag ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; Chain = DAG . getCopyToReg ( Chain , dl , Subtarget -> is64Bit ( ) ? <STR_LIT> : <STR_LIT> , Src , InFlag ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; SDVTList Tys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SDValue Ops [ ] = { Chain , DAG . getValueType ( AVT ) , InFlag } ; SDValue RepMovs = DAG . getNode ( <STR_LIT> , dl , Tys , Ops


<s> } assert ( TBB && Cond [ <NUM_LIT> ] . isImm ( ) ) ; unsigned Opcode = getBranchOpcode ( static_cast < BranchPredicate > ( Cond [ <NUM_LIT> ] . getImm ( ) ) ) ; if ( ! FBB ) { BuildMI ( & MBB , DL , get ( Opcode ) ) . addMBB ( TBB ) ; return <NUM_LIT> ; } assert ( TBB && FBB ) ; BuildMI ( & MBB , DL , get ( Opcode ) ) . addMBB ( TBB ) ; BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addMBB ( FBB ) ; return <NUM_LIT>


<s> bool hasGFX10_3Insts ( ) const { return


<s> if ( VT == <STR_LIT> && Amt . getOpcode ( ) == <STR_LIT> && Amt . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) { Amt = Amt . getOperand ( <NUM_LIT> ) ; unsigned Ratio = <NUM_LIT> / Amt . getScalarValueSizeInBits ( ) ; std :: vector < SDValue > Vals ( Ratio ) ; for ( unsigned i = <NUM_LIT> ; i != Ratio ; ++ i ) Vals [ i ] = Amt . getOperand ( i ) ; for ( unsigned i = Ratio , e = Amt . getNumOperands ( ) ; i != e ; i += Ratio ) { for ( unsigned j = <NUM_LIT> ; j != Ratio ; ++ j ) if ( Vals [ j ] != Amt . getOperand ( i + j ) ) return SDValue ( ) ; } if ( SupportedVectorShiftWithBaseAmnt ( VT , Subtarget , Op . getOpcode ( ) ) ) return DAG . getNode (

<ISA_LIT>OpcV , dl , VT , R , Op . getOperand ( <NUM_LIT> ) ) ;


<s> Type * Tys [ <NUM_LIT> ] = { VecTy , PtrTy } ; static const <STR_LIT> LoadInts [ <NUM_LIT> ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> } ; Function * LdNFunc = <STR_LIT> ( LI -> getModule ( ) , LoadInts [ Factor - <NUM_LIT> ] , Tys ) ; IRBuilder < > Builder ( LI ) ; Value * Ptr = Builder . CreateBitCast ( LI -> getPointerOperand ( ) , PtrTy ) ; CallInst * LdN = Builder . CreateCall ( LdNFunc , Ptr , <STR_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i < Shuffles . size ( ) ; i ++ ) { ShuffleVectorInst * SVI = Shuffles [ i ] ; unsigned Index = Indices [ i ]


<s> ScheduleDAGMILive * DAG = createGenericSchedLive ( C ) ; DAG -> addMutation ( createLoadClusterDAGMutation ( DAG -> TII , DAG


<s> tree attrs = get_attributes ( instance ) ; registered_function & rfn = add_function ( instance , name , fntype , attrs , required_extensions , false , false ) ; hashval_t hash = instance . hash ( ) ; registered_function * * rfn_slot = function_table -> find_slot_with_hash ( instance , hash , INSERT ) ; gcc_assert ( ! * rfn_slot ) ; * rfn_slot = & rfn ; char * overload_name = get_name ( instance , true ) ; if ( strcmp ( name , overload_name ) != <NUM_LIT> ) { tree attrs = get_attributes ( instance ) ; bool placeholder_p = ! ( m_direct_overloads || force_direct_overloads ) ; add_function ( instance , overload_name , fntype , attrs , required_extensions


<s> unsigned Align = inferAlignmentFromPtrInfo ( MF , MPO ) ; auto MMO = MF . getMachineMemOperand ( MPO , MachineMemOperand :: MOLoad | MachineMemOperand :: MOInvariant , Size , Align ) ; MIRBuilder . buildLoad ( ValVReg ,


<s> NodeList CodeNode :: members_if ( Predicate P , const DataFlowGraph & G ) const { NodeList MM ; auto M = getFirstMember ( G ) ; if ( M . Id == <NUM_LIT> )


<s> bool hasGFX10_3Insts ( const MCSubtargetInfo & STI ) { return STI . getFeatureBits ( ) [ <STR_LIT>


<s> last_insn = emit_insn_after ( gen_nopv ( ) , last_insn ) ; } add_reg_note ( last_insn , REG_SAVE_NOTE , GEN_INT ( <NUM_LIT> ) ) ; loop -> last_insn = last_insn ; iter_reg = loop -> iter_reg ; gcc_assert ( REG_P ( iter_reg ) ) ; entry_edge = NULL ; FOR_EACH_VEC_SAFE_ELT ( loop -> incoming , i , entry_edge ) if ( entry_edge -> flags & EDGE_FALLTHRU ) break ; if ( entry_edge == NULL ) { if ( dump_file ) fprintf ( dump_file , <STR_LIT> <STR_LIT> , loop -> loop_no ) ; return false ; } end_label = gen_label_rtx ( ) ; loop -> end_label = end_label ; entry_bb = entry_edge -> src ; start_sequence ( ) ; if ( need_fix ) { emit_insn ( gen_rtx_SET ( lp_reg , iter_reg ) ) ; SET_HARD_REG_BIT ( loop -> regs_set_in_loop , LP_COUNT ) ; iter_reg = lp_reg ; if ( dump_file ) { fprintf ( dump_file , <STR_LIT> , loop -> loop_no ) ; } } insn = emit_insn ( gen_arc_lp ( loop -> start_label , loop -> end_label ) ) ; seq = get_insns ( ) ; end_sequence ( ) ; entry_after = BB_END ( entry_bb ) ; if ( ! single_succ_p ( entry_bb ) || vec_safe_length ( loop -> incoming ) > <NUM_LIT> || ! entry_after ) { basic_block new_bb ; edge e ; edge_iterator ei ; emit_insn_before ( seq , BB_HEAD ( loop -> head ) ) ; seq = emit_label_before ( gen_label_rtx ( ) , seq ) ; new_bb = create_basic_block ( seq , insn , entry_bb ) ; FOR_EACH_EDGE ( e , ei , loop -> incoming ) { if ( ! ( e -> flags & EDGE_FALLTHRU ) ) redirect_edge_and_branch_force ( e , new_bb ) ; else redirect_edge_succ ( e , new_bb ) ; } make_edge ( new_bb , loop -> head , <NUM_LIT> ) ; } else { while ( DEBUG_INSN_P ( entry_after ) || ( NOTE_P ( entry_after ) && NOTE_KIND ( entry_after ) != NOTE_INSN_BASIC_BLOCK && NOTE_KIND ( entry_after ) != NOTE_INSN_CALL_ARG_LOCATION ) ) entry_after = NEXT_INSN ( entry_after ) ; entry_after = next_nonnote_insn_bb ( entry_after ) ; gcc_assert ( entry_after


<s> unsigned <ISA_LIT>MCCodeEmitter :: getTLSRegEncoding ( const MCInst & MI , unsigned OpNo , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { const MCOperand & MO = MI . getOperand ( OpNo ) ; if ( MO . isReg ( ) ) return getMachineOpValue ( MI , MO , Fixups , STI ) ; Fixups . push_back ( MCFixup :: Create ( <NUM_LIT> , MO . getExpr ( ) , (


<s> if ( ! Inst ) continue ; if ( auto * BI = dyn_cast < BitCastInst > ( Inst ) ) { traceBitCast ( BI , Parent , ParentInfo ) ; } else if ( auto * CI = dyn_cast < CallInst > ( Inst ) ) { CallInfo ChildInfo ; if ( IsPreserveDIAccessIndexCall ( CI , ChildInfo ) && IsValidAIChain ( ParentInfo . Metadata , ParentInfo . AccessIndex , ChildInfo . Metadata ) ) { AIChain [ CI ] = std :: make_pair ( Parent , ParentInfo ) ; traceAICall ( CI , ChildInfo ) ; } else { BaseAICalls [ Parent ] = ParentInfo ; } } else if ( auto * GI = dyn_cast < GetElementPtrInst > ( Inst ) ) { if ( GI -> hasAllZeroIndices ( ) ) traceGEP ( GI , Parent , ParentInfo ) ; else BaseAICalls [ Parent ] = ParentInfo ; } else { BaseAICalls [ Parent ] =


<s> static bool m32c_promote_prototypes ( tree fntype ATTRIBUTE_UNUSED ) { return <NUM_LIT>


<s> if ( LHSID == ( <NUM_LIT> * <NUM_LIT> + <NUM_LIT> ) * <NUM_LIT> + <NUM_LIT> ) return LHS ; assert ( LHSID == ( ( <NUM_LIT> * <NUM_LIT> + <NUM_LIT> ) * <NUM_LIT> + <NUM_LIT> ) * <NUM_LIT> + <NUM_LIT> && <STR_LIT> ) ; return RHS ; } SDValue OpLHS , OpRHS ; OpLHS = GeneratePerfectShuffle ( PerfectShuffleTable [ LHSID ] , LHS , RHS , DAG , dl ) ; OpRHS = GeneratePerfectShuffle ( PerfectShuffleTable [ RHSID ] , LHS , RHS , DAG , dl ) ; EVT VT = OpLHS . getValueType ( ) ; switch ( OpNum ) { default : llvm_unreachable ( <STR_LIT> ) ; case OP_VREV : if ( VT . getVectorElementType ( ) == <STR_LIT> || VT . getVectorElementType ( ) == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , dl , VT , OpLHS ) ; if ( VT . getVectorElementType ( ) == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , dl , VT , OpLHS ) ; assert ( VT . getVectorElementType ( ) == <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , VT , OpLHS ) ; case OP_VDUP0 : case OP_VDUP1 : case OP_VDUP2 : case OP_VDUP3 : return DAG . getNode ( <STR_LIT> , dl , VT , OpLHS , DAG . getConstant ( OpNum - OP_VDUP0 , dl , <STR_LIT> ) ) ; case OP_VEXT1 : case OP_VEXT2 : case OP_VEXT3 : return DAG . getNode ( <STR_LIT> , dl , VT , OpLHS , OpRHS , DAG . getConstant ( OpNum - OP_VEXT1 + <NUM_LIT> , dl , <STR_LIT> ) ) ; case OP_VUZPL : case OP_VUZPR : return DAG . getNode ( <STR_LIT> , dl , DAG . getVTList ( VT , VT ) , OpLHS

, OpRHS ) . getValue ( OpNum - OP_VUZPL ) ;


<s> return __builtin_mve_vrshlq_m_sv8hi ( __arm_vuninitializedq_s16 ( ) , __a ,


<s> if ( mFuncNames . find ( func ) == mFuncNames . end ( ) ) { id = mFuncNames . size ( ) + RESERVED_FUNCS + mFuncPtrNames . size ( ) ; mFuncNames [ func ] = id ; } else { id = mFuncNames [ func


<s> const std :: pair < unsigned , int > * <ISA_LIT>FrameLowering ::

getCalleeSaveSpillSlots ( unsigned & NumEntries ) const {


<s> const <ISA_LIT>RegisterInfo * RegInfo = static_cast < const <ISA_LIT>RegisterInfo * > ( MF . getTarget ( ) . getRegisterInfo ( ) ) ; FrameReg = ( RegInfo -> needsStackRealignment ( MF ) ) ? RegInfo -> getStackRegister ( ) : RegInfo -> getFrameRegister ( MF ) ; return getFrameIndexOffset ( MF


<s> static void m68hc11_asm_out_destructor ( rtx symbol , int priority ) { default_dtor_section_asm_out_destructor ( symbol ,


<s> return ( __m128d ) __builtin_ia32_vfnmaddpd128_mask ( ( __v2df ) __A , ( __v2df ) __B , (


<s> if ( RelocM == Reloc :: Static ) return false ; bool isDecl = GV -> isDeclarationForLinker ( ) ; if ( ! isTargetMachO ( ) ) { if ( GV -> hasLocalLinkage ( ) || GV -> hasHiddenVisibility ( ) ) return false ; return true ; } else { if ( RelocM == Reloc :: PIC_ ) { if ( ! isDecl && ! GV -> isWeakForLinker ( ) ) return false ; if ( ! GV -> hasHiddenVisibility ( ) ) return true ; if ( isDecl || GV -> hasCommonLinkage ( ) ) return true ; return false ; } else { if ( ! isDecl && ! GV -> isWeakForLinker ( )


<s> if ( STI . isTargetDarwin ( ) || STI . isThumb1Only ( ) ) FramePtr = <STR_LIT> ; else FramePtr = <STR_LIT> ; } else if ( STI . isTargetWindows ( ) ) FramePtr = <STR_LIT> ; else FramePtr = STI . isThumb


<s> static inline uint8_t encodeAdvSIMDModImmType7 (


<s> for ( regno = <NUM_LIT> ; regno < FIRST_PSEUDO_REGISTER ; regno ++ ) if ( ! SSE_REGNO_P (

regno ) && ix86_save_reg ( regno , true ) ) {


<s> enum reg_class ret ; switch ( rclass ) { default : ret = NO_REGS ; break ; case QUAD_REGS : case GPR_REGS : ret = NO_REGS ; if ( x && GET_CODE ( x ) == REG ) { int regno = REGNO ( x ) ; if ( ACC_P ( regno ) || ACCG_P ( regno ) ) ret = FPR_REGS ; } break ; case QUAD_FPR_REGS : if ( x && CONSTANT_P ( x ) && ! ZERO_P ( x ) ) ret = GPR_REGS ; else ret = NO_REGS ; break ; case ICC_REGS : case FCC_REGS : case CC_REGS : case ICR_REGS : case FCR_REGS : case CR_REGS : case LCR_REG : case LR_REG : ret = GPR_REGS ; break ; case QUAD_ACC_REGS : case ACCG_REGS : ret = FPR_REGS


<s> getMnemonicAcceptInfo ( StringRef Mnemonic , StringRef FullInst , bool & CanAcceptCarrySet , bool & CanAcceptPredicationCode ) { if ( Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || ( ! isThumb ( ) && ( Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> ) ) ) { CanAcceptCarrySet = true ; } else CanAcceptCarrySet = false


<s> SDValue ShiftRight1Lo = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Lo , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDValue ShiftRightLo = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , ShiftRight1Lo , Not ) ; SDValue ShiftLeftHi = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Hi , Shamt ) ; SDValue Or = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , ShiftLeftHi , ShiftRightLo ) ; SDValue ShiftLeftLo = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Lo , Shamt ) ; SDValue Cond = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Shamt , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; Lo = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Cond , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) , ShiftLeftLo ) ; Hi = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Cond , ShiftLeftLo , Or ) ; SDValue Ops [ <NUM_LIT> ] = { Lo , Hi } ; return DAG . getMergeValues ( Ops ,


<s> extern __inline void __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) _mm512_prefetch_i64scatter_ps ( void * addr , __m512i index , int scale , int hint ) { __builtin_ia32_scatterpfqps ( ( __mmask8 ) <NUM_LIT> , ( __v8di ) index , ( int const * ) addr ,


<s> unsigned imod = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned M = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned iflags = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned mode = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; DecodeStatus S = MCDisassembler :: Success ; if ( fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) != <NUM_LIT> || fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) != <NUM_LIT> || fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) != <NUM_LIT> ) return MCDisassembler :: Fail ; if ( imod == <NUM_LIT> ) return MCDisassembler :: Fail ; if ( imod && M ) { Inst . setOpcode ( <STR_LIT> ) ; Inst . addOperand ( MCOperand :: CreateImm (


<s> for ( int i = <NUM_LIT> , e = sizeof ( map ) / sizeof ( map [ <NUM_LIT> ] ) ;

i != e ; ++ i ) if ( <STR_LIT> . contains ( DstReg , SrcReg ) ) {


<s> static struct machine_function * rs6000_init_machine_status


<s> unsigned NumElts = VT . getVectorNumElements ( ) ; for ( unsigned i = <NUM_LIT> ; i < NumElts ; ++ i ) { if ( M [ i


<s> SDValue <ISA_LIT>TargetLowering :: LowerVASTART ( SDValue Op , SelectionDAG & DAG ) const { MachineFunction & MF = DAG . getMachineFunction ( ) ; auto PtrVT = getPointerTy ( MF . getDataLayout ( ) ) ; <ISA_LIT>MachineFunctionInfo * FuncInfo = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; const Value * SV = cast < SrcValueSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getValue ( ) ; SDLoc DL ( Op ) ; if ( ! Subtarget . is64Bit ( ) || Subtarget . isCallingConvWin64 ( MF . getFunction ( ) . getCallingConv ( ) ) ) { SDValue FR = DAG . getFrameIndex ( FuncInfo -> getVarArgsFrameIndex ( ) , PtrVT ) ; return DAG . getStore ( Op . getOperand ( <NUM_LIT> ) , DL , FR , Op . getOperand ( <NUM_LIT> ) , MachinePointerInfo ( SV ) ) ; } SmallVector < SDValue , <NUM_LIT> > MemOps ; SDValue FIN = Op . getOperand ( <NUM_LIT> ) ; SDValue Store = DAG . getStore ( Op . getOperand ( <NUM_LIT> ) , DL , DAG . getConstant ( FuncInfo -> getVarArgsGPOffset ( ) , DL , <STR_LIT> ) , FIN , MachinePointerInfo ( SV ) ) ; MemOps . push_back ( Store ) ; FIN = DAG . getMemBasePlusOffset ( FIN , TypeSize :: Fixed ( <NUM_LIT> ) , DL ) ; Store = DAG . getStore ( Op . getOperand ( <NUM_LIT> ) , DL , DAG . getConstant ( FuncInfo -> getVarArgsFPOffset ( ) , DL , <STR_LIT> ) , FIN , MachinePointerInfo ( SV , <NUM_LIT> ) ) ; MemOps . push_back ( Store ) ; FIN = DAG . getNode ( <STR_LIT> , DL , PtrVT , FIN , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; SDValue OVFIN = DAG . getFrameIndex ( FuncInfo -> getVarArgsFrameIndex ( ) , PtrVT ) ; Store = DAG . getStore ( Op . getOperand ( <NUM_LIT> ) , DL , OVFIN ,


<s> static unsigned getHashValue ( <STR_LIT> Val ) { return Val .


<s> return ( __m64 ) __builtin_ia32_pmulhw ( ( __v4hi ) __m1 , (


<s> static_cast < <ISA_LIT>InstPrinter * > ( this ) -> printUpdatePred ( MI , OpNo , O


<s> if ( TARGET_64BIT || TARGET_VXWORKS_RTP ) fprintf ( file , <STR_LIT> , directive , LPREFIX , value , LPREFIX , rel ) ; else if ( HAVE_AS_GOTOFF_IN_DATA ) fprintf ( file , ASM_LONG <STR_LIT> , LPREFIX , value ) ; else if ( TARGET_MACHO ) { fprintf ( file , ASM_LONG <STR_LIT> , LPREFIX , value ) ; machopic_output_function_base_name ( file ) ; putc ( '\n' , file ) ; } else asm_fprintf ( file , ASM_LONG <STR_LIT> , GOT_SYMBOL_NAME , LPREFIX ,


<s> return ( float32x4_t ) __builtin_neon_vld1v4sf ( ( const __builtin_neon_sf *


<s> bool IsIEEEMode = Info -> getMode ( ) . IEEE ; if ( IsIEEEMode ) return expandFMINNUM_FMAXNUM ( Op . getNode ( ) , DAG ) ; if ( VT == <STR_LIT> ) return splitBinaryVectorOp ( Op , DAG ) ; return Op


<s> rtx op0 = operands [ <NUM_LIT> ] , op1 =


<s> static const char * const CPUDirectives [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; unsigned Directive = Subtarget . getDarwinDirective ( ) ; if ( Subtarget . hasMFOCRF ( ) && Directive < <STR_LIT> ) Directive = <STR_LIT> ; if ( Subtarget . hasAltivec ( ) && Directive < <STR_LIT> ) Directive = <STR_LIT> ; if ( Subtarget . is<ISA_LIT>64 ( ) && Directive < <STR_LIT> ) Directive = <STR_LIT> ; assert ( Directive <= <STR_LIT> && <STR_LIT> ) ; assert ( Directive < array_lengthof ( CPUDirectives ) && <STR_LIT> ) ; <ISA_LIT>TargetStreamer & TStreamer = * static_cast < <ISA_LIT>TargetStreamer * > ( OutStreamer . getTargetStreamer ( ) ) ; TStreamer . emitMachine ( CPUDirectives [ Directive ] ) ; const TargetLoweringObjectFileMachO & TLOFMacho = static_cast < const TargetLoweringObjectFileMachO & > ( getObjFileLowering ( ) ) ; OutStreamer . SwitchSection ( TLOFMacho . getTextCoalSection ( ) ) ; if ( TM . getRelocationModel ( )


<s> llvm_unreachable ( <STR_LIT> ) ; return


<s> unsigned getBytesToPopOnReturn ( ) const { return BytesToPopOnReturn


<s> const DataLayout & DL = F . getParent ( ) -> getDataLayout ( ) ; const <ISA_LIT>TargetLowering & TLI = * getTLI < <ISA_LIT>TargetLowering > ( ) ; unsigned ArgNo = <NUM_LIT> ; for ( auto & Arg : Args ) { EVT VT = TLI . getValueType ( DL , Arg . Ty ) ; MVT RegisterVT = TLI . getRegisterTypeForCallingConv ( F . getContext ( )


<s> uint64_t Size = DL . getTypeAllocSize ( GV -> getType ( ) -> getElementType ( ) ) ; if ( GVKind . isBSSLocal ( ) ) OutStreamer -> EmitXCOFFLocalCommonSymbol ( GVSym , Size , Align ) ; else OutStreamer -> EmitCommonSymbol ( GVSym , Size , Align ) ; return ; } const unsigned AlignLog = getGVAlignmentLog2 ( GV , DL ) ; MCSymbol * EmittedInitSym = GVSym ; EmitLinkage ( GV , EmittedInitSym ) ; EmitAlignment ( AlignLog , GV ) ; OutStreamer -> EmitLabel ( EmittedInitSym ) ; EmitGlobalConstant ( GV -> getParent ( ) -> getDataLayout ( ) , GV


<s> auto Expr = MCBinaryExpr :: create ( MCBinaryExpr :: Sub , End , Start , getContext ( ) ) ; getStreamer ( ) . emitELFSize ( LastFunctionLabel , Expr


<s> for ( MachineBasicBlock * MBB : L -> getBlocks ( ) ) { for ( MachineInstr & MI : * MBB ) { if ( isInvalidLoopOperation ( & MI ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; MI


<s> unsigned GlobalBaseReg = <ISA_LIT>FI -> getGlobalBaseReg ( ) ; if ( GlobalBaseReg != <NUM_LIT> ) return GlobalBaseReg ; MachineRegisterInfo & RegInfo = MF -> getRegInfo ( ) ; GlobalBaseReg = RegInfo . createVirtualRegister


<s> static bool lowerVectorFCMP ( MachineInstr & MI , MachineRegisterInfo & MRI , MachineIRBuilder & MIB ) { assert ( MI . getOpcode ( ) == TargetOpcode :: G_FCMP ) ; const auto & ST = MI . getMF ( ) -> getSubtarget < <ISA_LIT>Subtarget > ( ) ; Register Dst = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; LLT DstTy = MRI . getType ( Dst ) ; if ( ! DstTy . isVector ( ) || ! ST . hasNEON ( ) ) return false ; const auto Pred = static_cast < CmpInst :: Predicate > ( MI . getOperand ( <NUM_LIT> ) . getPredicate ( ) ) ; Register LHS = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned EltSize = MRI . getType ( LHS ) . getScalarSizeInBits ( ) ; if ( EltSize != <NUM_LIT> && EltSize != <NUM_LIT> ) return false ; Register RHS = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; auto Splat = get<ISA_LIT>VectorSplat ( * MRI . getVRegDef ( RHS ) , MRI ) ; bool IsZero = Splat && Splat -> isCst ( ) && Splat -> getCst ( ) == <NUM_LIT> ; bool Invert ; <STR_LIT> CC , CC2 ; changeVectorFCMPPredTo<ISA_LIT>CC ( Pred , CC , CC2 , Invert ) ; bool NoNans = ST . getTargetLowering ( ) -> getTargetMachine ( ) . Options . NoNaNsFPMath ; MIB . setInstrAndDebugLoc ( MI ) ; auto Cmp = getVectorFCMP ( CC , LHS , RHS , IsZero , NoNans , MRI ) ; Register CmpRes ; if ( CC2 == <STR_LIT> ) CmpRes = Cmp ( MIB ) ; else { auto Cmp2 = getVectorFCMP ( CC2 , LHS , RHS , IsZero , NoNans , MRI ) ; auto Cmp2Dst = Cmp2 (


<s> bool Is128B = HST . useHVXDblOps ( ) ; auto * RC = ! Is128B ? & <STR_LIT> : & <STR_LIT> ; unsigned NeedAlign = RC -> getAlignment ( ) ; unsigned HasAlign = MFI . getObjectAlignment ( FI ) ; unsigned StoreOpc ; if ( NeedAlign <= HasAlign ) StoreOpc = ! Is128B ? <STR_LIT> : <STR_LIT> ; else StoreOpc = ! Is128B ? <STR_LIT> : <STR_LIT> ; BuildMI ( B , It , DL , HII . get ( StoreOpc ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcR , getKillRegState ( IsKill ) ) . setMemRefs ( MI -> memoperands_begin ( ) , MI -> memoperands_end ( ) ) ; B . erase ( It ) ; return


<s> return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , IPM , DAG . getConstant (


<s> case Match_MissingFeature : return Parser . Error ( IDLoc , <STR_LIT> ) ; case Match_MnemonicFail : return Parser . Error ( IDLoc , <STR_LIT> ) ; case Match_NearMisses : return Parser . Error ( IDLoc , <STR_LIT> ) ; case Match_InvalidTiedOperand : case Match_InvalidOperand : { SMLoc ErrorLoc = IDLoc ; if ( ErrorInfo != ~ <NUM_LIT> ) { if ( ErrorInfo >= Operands . size ( ) ) return Parser . Error ( IDLoc , <STR_LIT> ) ; ErrorLoc = Operands [ ErrorInfo ] -> getStartLoc ( ) ; if ( ErrorLoc == SMLoc ( ) )


<s> if ( TII . isMIMG ( MI ) ) { uint64_t DMaskImm = TII . getNamedOperand ( MI , <STR_LIT> :: dmask ) -> getImm ( ) ; return countPopulation ( DMaskImm ) ; } if ( TII . isMTBUF ( Opc ) ) { return <STR_LIT> ( Opc ) ; } switch ( Opc ) { case <STR_LIT> : return <NUM_LIT> ; case


<s> MachineBasicBlock :: iterator MBBI = FirstMBB . begin ( ) ; const Module * M = MF -> getFunction ( ) . getParent ( ) ; DebugLoc dl ; if ( <ISA_LIT>Lowering -> getPointerTy ( CurDAG -> getDataLayout ( ) ) == <STR_LIT> ) { if ( Subtarget -> isTargetELF ( ) ) { GlobalBaseReg = <STR_LIT> ; if ( ! Subtarget -> isSecurePlt ( ) && M -> getPICLevel ( ) == PICLevel :: SmallPIC ) { BuildMI ( FirstMBB , MBBI , dl , TII . get ( <STR_LIT> ) ) ; BuildMI ( FirstMBB , MBBI , dl , TII . get ( <STR_LIT> ) , GlobalBaseReg ) ; MF -> getInfo < <ISA_LIT>FunctionInfo > ( ) -> setUsesPICBase ( true ) ; } else { BuildMI ( FirstMBB , MBBI , dl , TII . get ( <STR_LIT> ) ) ; BuildMI ( FirstMBB , MBBI , dl , TII . get ( <STR_LIT> ) , GlobalBaseReg ) ; Register TempReg = RegInfo -> createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( FirstMBB , MBBI , dl , TII . get ( <STR_LIT> ) , GlobalBaseReg ) . addReg ( TempReg , RegState :: Define ) . addReg ( GlobalBaseReg ) ; MF -> getInfo < <ISA_LIT>FunctionInfo > ( ) -> setUsesPICBase ( true ) ; } } else { GlobalBaseReg = RegInfo -> createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( FirstMBB , MBBI , dl , TII . get ( <STR_LIT> ) ) ; BuildMI ( FirstMBB , MBBI , dl , TII . get ( <STR_LIT> ) , GlobalBaseReg ) ; } } else { MF -> getInfo < <ISA_LIT>FunctionInfo > ( ) -> setShrinkWrapDisabled ( true ) ; GlobalBaseReg = RegInfo -> createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( FirstMBB , MBBI , dl , TII . get ( <STR_LIT> ) ) ; BuildMI ( FirstMBB , MBBI , dl , TII . get


<s> if ( ! isImm ( ) ) return false ; int64_t Imm ; <ISA_LIT>MCExpr :: VariantKind VK = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ; bool IsConstantImm = evaluateConstantImm ( getImm ( ) , Imm ,


<s> static int loongarch_arg_partial_bytes ( cumulative_args_t cum , const function_arg_info & generic_arg ) { struct loongarch_arg_info arg ; loongarch_get_arg_info ( & arg , get_cumulative_args ( cum ) , generic_arg . mode , generic_arg .


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : break ; case <STR_LIT> : RefKind = MCSymbolRefExpr :: VK_TLVP ; break ; case <STR_LIT> : Expr = MCSymbolRefExpr :: create ( Sym , MCSymbolRefExpr :: VK_TLVP , Ctx ) ; Expr = MCBinaryExpr :: createSub ( Expr , MCSymbolRefExpr :: create ( MF . getPICBaseSymbol ( ) , Ctx ) , Ctx ) ; break ; case <STR_LIT> : RefKind = MCSymbolRefExpr :: VK_SECREL ; break ; case <STR_LIT> : RefKind = MCSymbolRefExpr :: VK_TLSGD ; break ; case <STR_LIT> : RefKind = MCSymbolRefExpr :: VK_TLSLD ; break ; case <STR_LIT> : RefKind = MCSymbolRefExpr :: VK_TLSLDM ; break ; case <STR_LIT> : RefKind = MCSymbolRefExpr :: VK_GOTTPOFF ; break ; case <STR_LIT> : RefKind = MCSymbolRefExpr :: VK_INDNTPOFF ; break ; case <STR_LIT> : RefKind = MCSymbolRefExpr :: VK_TPOFF ; break ; case <STR_LIT> : RefKind = MCSymbolRefExpr :: VK_DTPOFF ; break ; case <STR_LIT> : RefKind = MCSymbolRefExpr :: VK_NTPOFF ; break ; case <STR_LIT> : RefKind = MCSymbolRefExpr :: VK_GOTNTPOFF ; break ; case <STR_LIT> : RefKind = MCSymbolRefExpr :: VK_GOTPCREL ; break ; case <STR_LIT> : RefKind = MCSymbolRefExpr :: VK_GOT ; break ; case <STR_LIT> : RefKind = MCSymbolRefExpr :: VK_GOTOFF ; break ; case <STR_LIT> : RefKind = MCSymbolRefExpr :: VK_PLT ; break ; case <STR_LIT> : case <STR_LIT> : Expr = MCSymbolRefExpr :: create ( Sym , Ctx ) ; Expr = MCBinaryExpr :: createSub ( Expr , MCSymbolRefExpr :: create ( MF . getPICBaseSymbol ( ) , Ctx ) , Ctx ) ; if ( MO . isJTI ( ) ) { assert ( MAI . doesSetDirectiveSuppressReloc ( ) ) ; MCSymbol * Label = Ctx . createTempSymbol ( ) ; AsmPrinter . OutStreamer -> EmitAssignment ( Label , Expr ) ; Expr = MCSymbolRefExpr :: create ( Label , Ctx ) ; } break ; } if ( ! Expr ) Expr = MCSymbolRefExpr :: create ( Sym , RefKind , Ctx ) ; if ( ! MO . isJTI ( ) && ! MO . isMBB ( ) && MO . getOffset ( ) ) Expr = MCBinaryExpr :: createAdd ( Expr , MCConstantExpr :: create ( MO . getOffset ( ) , Ctx ) , Ctx ) ; return MCOperand :: createExpr


<s> if ( ! regs_ever_live [ GLOBAL_POINTER_REGNUM ] && ! current_function_uses_const_pool && ! mips_function_has_gp_insn ( ) ) return <NUM_LIT> ; if ( TARGET_NEWABI && current_function_is_leaf ) for ( regno = GP_REG_FIRST ; regno <= GP_REG_LAST ; regno ++ ) if ( ! regs_ever_live [ regno ] && call_used_regs [ regno ] && ! fixed_regs [ regno ] && regno != PIC_FUNCTION_ADDR_REGNUM ) return regno ; return GLOBAL_POINTER_REGNUM


<s> initialize<ISA_LIT>Z80PreRAPass ( * PassRegistry :: getPassRegistry (


<s> static SDValue getMOVL ( SelectionDAG & DAG , const SDLoc & dl , MVT VT , SDValue V1 , SDValue V2 ) { unsigned NumElems = VT . getVectorNumElements ( ) ; SmallVector < int , <NUM_LIT> > Mask


<s> StringRef <ISA_LIT>RegisterInfo :: getRegAsmName ( unsigned Reg ) const { if ( Reg >= BeginReg && Reg <= EndReg ) { \ unsigned Index = Reg - BeginReg ; \ assert ( Index < array_lengthof ( RegTable ) ) ; \ return RegTable [ Index ] ; \ } REG_RANGE ( <STR_LIT> , <STR_LIT> , VGPR32RegNames ) ; REG_RANGE ( <STR_LIT> , <STR_LIT> , SGPR32RegNames ) ; REG_RANGE ( <STR_LIT> , <STR_LIT> , VGPR64RegNames ) ; REG_RANGE ( <STR_LIT> , <STR_LIT> , SGPR64RegNames ) ; REG_RANGE ( <STR_LIT> , <STR_LIT> , VGPR96RegNames ) ; REG_RANGE ( <STR_LIT> , <STR_LIT> , VGPR128RegNames ) ; REG_RANGE ( <STR_LIT> , <STR_LIT> , SGPR128RegNames ) ; REG_RANGE ( <STR_LIT> , <STR_LIT>


<s> SDValue Val = OutVals [ i ] ; CCValAssign & VA = RVLocs [ i ] ; assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; if ( RVLocs [ i ] . getValVT ( ) != RVLocs [ i ] . getLocVT ( ) ) Val = DAG . getNode ( <STR_LIT> , DL , RVLocs [ i ] . getLocVT ( ) , Val ) ; Chain = DAG . getCopyToReg ( Chain , DL , VA . getLocReg ( ) , Val , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( VA . getLocReg ( ) , VA . getLocVT ( ) ) ) ; } if ( MF . getFunction ( ) -> hasStructRetAttr ( ) ) { <ISA_LIT>FunctionInfo * <ISA_LIT>FI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; unsigned Reg = <ISA_LIT>FI ->


<s> <ISA_LIT>CallFrameInformation ( ) : MachineFunctionPass ( ID ) { PassRegistry & PR = * PassRegistry


<s> printOperand ( MI , <NUM_LIT> , O ) ; O << <STR_LIT> ; printOperand ( MI , <NUM_LIT> , O ) ; O << <STR_LIT> ; printOperand ( MI , <NUM_LIT> , O ) ; O << <STR_LIT> ; return ; } if ( MI -> getOpcode ( ) == <STR_LIT> ) { unsigned char SH = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned char MB = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned char ME = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; bool useSubstituteMnemonic = false ; if ( SH <= <NUM_LIT> && MB == <NUM_LIT> && ME == ( <NUM_LIT> - SH ) ) { O << <STR_LIT> ; useSubstituteMnemonic = true ; } if ( SH <= <NUM_LIT> && MB == ( <NUM_LIT> - SH ) && ME == <NUM_LIT> ) { O << <STR_LIT> ; useSubstituteMnemonic = true ; SH = <NUM_LIT> - SH ; } if ( useSubstituteMnemonic ) { printOperand ( MI , <NUM_LIT> , O ) ; O << <STR_LIT> ; printOperand ( MI , <NUM_LIT> , O ) ; O << <STR_LIT> << ( unsigned int ) SH ; printAnnotation ( O , Annot ) ; return ; } } if ( MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> ) { unsigned char SH = MI -> getOperand


<s> SDValue <ISA_LIT>TargetLowering :: lowerEXTRACT_VECTOR_ELT ( SDValue Op , SelectionDAG & DAG ) const { SDLoc DL ( Op ) ; SDValue Idx = Op . getOperand ( <NUM_LIT> ) ; if ( isNullConstant ( Idx ) ) return Op ; SDValue Vec = Op . getOperand ( <NUM_LIT> ) ; EVT EltVT = Op


<s> if ( MI -> isInlineAsm ( ) || is<ISA_LIT>SoloInstruction ( MI ) ) { return true


<s> rtl_opt_pass * make_pass_arc_ifcvt ( gcc :: context * ctxt ) { return new pass_arc_ifcvt ( ctxt


<s> unsigned CC = I -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned regX = I -> getOperand ( <NUM_LIT> ) . getReg ( ) ; int64_t Imm = I -> getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned SltOpc = whichOp8u_or_16simm ( SltiOpc , SltiXOpc , Imm ) ; BuildMI ( MBB , I , I -> getDebugLoc ( ) , get ( SltOpc ) ) . addReg ( regX ) . addImm ( Imm ) ; BuildMI ( MBB , I , I -> getDebugLoc ( ) , get ( <STR_LIT> )


<s> Defs &= ~ ( <NUM_LIT> << DReg ) ; } if ( Kills && I != MBB -> begin ( ) ) { MachineBasicBlock :: iterator I2 = std :: prev ( I ) ; while ( StackTop ) { unsigned KReg = getStackEntry ( <NUM_LIT> ) ; if ( ! ( Kills & ( <NUM_LIT> << KReg ) ) ) break ; DEBUG ( dbgs ( ) << <STR_LIT> << KReg << <STR_LIT> ) ; popStackAfter ( I2 ) ; Kills &= ~ ( <NUM_LIT> << KReg ) ; } } while ( Kills ) { unsigned KReg = countTrailingZeros ( Kills ) ; DEBUG ( dbgs ( ) << <STR_LIT> << KReg << <STR_LIT> ) ; freeStackSlotBefore ( I , KReg ) ; Kills &= ~ ( <NUM_LIT> << KReg


<s> ToggleFeature ( <STR_LIT> ) ; FlatForGlobal = true ; } if ( ! hasFlat ( ) && ! FS . contains ( <STR_LIT> ) && FlatForGlobal ) { ToggleFeature ( <STR_LIT> ) ; FlatForGlobal = false ; } if ( MaxPrivateElementSize == <NUM_LIT> ) MaxPrivateElementSize = <NUM_LIT> ; if ( LDSBankCount == <NUM_LIT> ) LDSBankCount = <NUM_LIT> ; if ( TT . getArch ( ) == Triple :: amdgcn ) { if ( LocalMemorySize == <NUM_LIT> ) LocalMemorySize = <NUM_LIT> ; if ( ! HasMovrel && ! HasVGPRIndexMode ) HasMovrel = true ; } if ( WavefrontSizeLog2 == <NUM_LIT> ) WavefrontSizeLog2 = <NUM_LIT> ; HasFminFmaxLegacy = getGeneration ( ) < <ISA_LIT>Subtarget :: VOLCANIC_ISLANDS ; TargetID . setTargetIDFromFeaturesString ( FS ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << TargetID .


<s> virtual void * getAdjustedAnalysisPointer ( const


<s> Relocator :: DWord A = pReloc . target ( ) + pReloc . addend ( ) ; Relocator :: DWord S = pReloc . symValue ( ) ; Relocation * dyn_rel = pParent . getRelRelMap ( ) . lookUp ( pReloc ) ; bool has_dyn_rel = ( dyn_rel != NULL ) ; LDSection & target_sect = pReloc . targetRef ( ) . frag ( ) -> getParent ( ) -> getSection ( ) ; if ( <NUM_LIT> == ( llvm :: ELF :: SHF_ALLOC & target_sect . flag ( ) ) ) { pReloc . target ( ) = S + A ; return Relocator :: OK ; } if ( rsym -> isLocal ( ) && has_dyn_rel ) { dyn_rel -> setAddend ( S + A ) ; } if ( ! rsym -> isLocal ( ) ) { if ( rsym -> reserved ( ) & <ISA_LIT>Relocator :: ReservePLT ) { S = helper_get_PLT_address ( * rsym , pParent ) ; } if ( has_dyn_rel ) { if ( llvm :: ELF :: R_AARCH64_ABS64 == pReloc . type ( ) && llvm :: ELF :: R_AARCH64_RELATIVE == dyn_rel -> type ( ) ) { dyn_rel -> setAddend ( S + A ) ; } else { dyn_rel -> setAddend ( A ) ; return Relocator ::


<s> static SDValue lowerMSASplatZExt ( SDValue Op , unsigned OpNr , SelectionDAG & DAG ) { EVT ResVecTy = Op -> getValueType ( <NUM_LIT> ) ; EVT ViaVecTy = ResVecTy ; SDLoc DL ( Op ) ; SDValue LaneA ; SDValue LaneB = Op -> getOperand ( <NUM_LIT> ) ; if ( ResVecTy == <STR_LIT>


<s> return ( vector unsigned int ) __builtin_altivec_vspltw ( ( vector signed int )


<s> unsigned Offset = ( Insn & <NUM_LIT> ) ; Inst . addOperand ( MCOperand :: createImm ( SignExtend32 < <NUM_LIT> > ( Offset ) ) ) ; return MCDisassembler :: Success


<s> return __builtin_aarch64_crypto_sha1hsi_uu (


<s> const ConstantInt * CI = cast < ConstantInt > ( C ) ; if ( CI -> isZero ( ) ) return Zero | PosOrZero | NegOrZero | Finite ; uint32_t Props = ( NonZero | Finite ) ; if ( CI -> isNegative ( ) ) return Props | NegOrZero ; return Props | PosOrZero ; } if ( isa < ConstantFP > ( C ) ) { const ConstantFP * CF = cast < ConstantFP > ( C ) ; uint32_t Props = CF -> isNegative ( ) ? ( NegOrZero | NonZero ) : PosOrZero ; if ( CF -> isZero ( ) ) return ( Props & ~ NumericProperties ) | ( Zero | Finite ) ; Props = ( Props & ~ NumericProperties ) | NonZero ; if ( CF -> isNaN ( ) ) return ( Props & ~ NumericProperties ) | NaN ; const APFloat & Val = CF -> getValueAPF ( ) ; if ( Val . isInfinity ( ) ) return ( Props & ~ NumericProperties ) | Infinity ; Props |= Finite ; return Props ; } return Unknown


<s> if ( FP_REG_P ( regno ) ) return ( GET_MODE_SIZE ( mode ) + UNITS_PER_FP_REG - <NUM_LIT> )


<s> SDValue Lo = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , BALo ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Hi , Lo ) ; } EVT ValTy = Op . getValueType ( ) ; unsigned GOTFlag = Has<ISA_LIT>64 ? <STR_LIT> : <STR_LIT> ; unsigned OFSTFlag = Has<ISA_LIT>64 ? <STR_LIT> : <STR_LIT> ; SDValue BAGOTOffset = DAG . getTargetBlockAddress ( BA , ValTy , <NUM_LIT> , GOTFlag ) ; BAGOTOffset = DAG . getNode ( <STR_LIT> , dl , ValTy , GetGlobalReg ( DAG , ValTy ) , BAGOTOffset ) ; SDValue BALOOffset = DAG . getTargetBlockAddress ( BA , ValTy , <NUM_LIT> , OFSTFlag ) ; SDValue Load = DAG . getLoad ( ValTy , dl , DAG . getEntryNode ( ) , BAGOTOffset , MachinePointerInfo ( )


<s> BlackfinMCAsmInfo :: BlackfinMCAsmInfo ( const Target &


<s> switch ( getLexer ( ) . getKind ( ) ) { default : return ParseMemOperand ( ) ; case AsmToken :: Percent : { unsigned RegNo ; SMLoc Start , End ; if ( ParseRegister ( RegNo , Start , End ) ) return <NUM_LIT> ; return <STR_LIT> ( RegNo , Start , End ) ; } case AsmToken :: Dollar : { SMLoc Start = Parser . getTok ( ) . getLoc ( )


<s> EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( VT != <STR_LIT> ) return SDValue ( ) ; SDValue Src = N -> getOperand ( <NUM_LIT>


<s> const <ISA_LIT>RegisterInfo * RegInfo = Subtarget . getRegisterInfo ( ) ; unsigned LR = RegInfo -> getRARegister ( ) ; bool DisableRedZone = MF . getFunction ( ) . hasFnAttribute ( Attribute :: NoRedZone ) ; bool CanUseRedZone = ! MFI . hasVarSizedObjects ( ) && ! MFI . adjustsStack ( ) && ! MustSaveLR ( MF , LR ) && ! FI -> mustSaveTOC ( ) && ! RegInfo -> hasBasePointer ( MF ) ; bool FitsInRedZone = FrameSize <= Subtarget . getRedZoneSize ( ) ; if ( ! DisableRedZone && CanUseRedZone && FitsInRedZone ) { return <NUM_LIT> ; } unsigned maxCallFrameSize = MFI . getMaxCallFrameSize ( ) ; unsigned minCallFrameSize = getLinkageSize ( ) ; maxCallFrameSize = std :: max ( maxCallFrameSize , minCallFrameSize ) ; if ( MFI . hasVarSizedObjects ( ) ) maxCallFrameSize = ( maxCallFrameSize + AlignMask ) &


<s> bool trackLivenessAfterRegAlloc ( const MachineFunction & MF ) const override { return true


<s> if ( CM != CodeModel :: Small && CM != CodeModel :: Large ) return <NUM_LIT> ; unsigned Opc = <NUM_LIT> ; const TargetRegisterClass * RC = nullptr ; switch ( VT . SimpleTy ) { default : return <NUM_LIT> ; case <STR_LIT> : if ( <ISA_LIT>ScalarSSEf32 ) { Opc = Subtarget -> hasAVX ( ) ? <STR_LIT> : <STR_LIT> ; RC = & <STR_LIT> ; } else { Opc = <STR_LIT> ; RC = & <STR_LIT> ; } break ; case <STR_LIT> : if ( <ISA_LIT>ScalarSSEf64 ) { Opc = Subtarget -> hasAVX ( ) ? <STR_LIT> : <STR_LIT> ; RC = & <STR_LIT> ; } else { Opc = <STR_LIT> ; RC = & <STR_LIT> ; } break ; case <STR_LIT> : return <NUM_LIT> ; } unsigned Align = DL . getPrefTypeAlignment ( CFP -> getType ( ) ) ; if ( Align == <NUM_LIT> ) { Align = DL . getTypeAllocSize ( CFP -> getType ( ) ) ; } unsigned PICBase = <NUM_LIT> ; unsigned char OpFlag = <NUM_LIT> ; if ( Subtarget -> isPICStyleStubPIC ( ) ) { OpFlag = <STR_LIT>


<s> bool <ISA_LIT>InstrInfo :: SubsumesPredicate ( ArrayRef < MachineOperand > Pred1 , ArrayRef < MachineOperand > Pred2 ) const { assert ( Pred1 . size ( ) == <NUM_LIT> && <STR_LIT> ) ; assert ( Pred2 . size ( ) == <NUM_LIT> && <STR_LIT> ) ; if ( Pred1 [ <NUM_LIT> ] . getReg ( ) == <STR_LIT> || Pred1 [ <NUM_LIT>

] . getReg ( ) == <STR_LIT> ) return false ;


<s> if ( Subtarget -> getTargetTriple ( ) . isWindowsMSVCEnvironment ( ) ) return M . getFunction (


<s> TargetRegistry :: RegisterMCDisassembler ( getThe<ISA_LIT>Target ( ) , create<ISA_LIT>Disassembler ) ; TargetRegistry :: RegisterMCDisassembler ( getThe<ISA_LIT>elTarget


<s> if ( * pcum < CSKY_NPARM_REGS ) return gen_rtx_REG (

mode , CSKY_FIRST_PARM_REGNUM + * pcum ) ;


<s> rtx data_addr = gen_reg_rtx ( Pmode ) ; rtx new_mem ; ea_addr = force_reg ( EAmode , XEXP ( mem , <NUM_LIT> ) ) ; if ( optimize_size || optimize == <NUM_LIT> ) ea_load_store ( mem , is_store , ea_addr , data_addr ) ; else ea_load_store_inline ( mem , is_store , ea_addr , data_addr ) ; if ( ea_alias_set == - <NUM_LIT> ) ea_alias_set = new_alias_set ( ) ; new_mem = gen_rtx_MEM ( GET_MODE ( mem ) , data_addr ) ; set_mem_alias_set ( new_mem , ea_alias_set ) ; set_mem_align ( new_mem , MIN ( MEM_ALIGN ( mem ) ,


<s> unsigned R = getRelaxedOpcodeArith ( Inst ) ; if ( R != Inst . getOpcode ( ) ) return R ; return getRelaxedOpcodeBranch ( Inst


<s> df_ref ref = DF_REG_DEF_CHAIN ( REGNO (


<s> assert ( N -> getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) ; assert ( isa < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ) ; assert ( isa < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT>


<s> return ( float32x2_t ) __builtin_neon_vset_lanev2sf ( ( __builtin_neon_sf


<s> llvm_unreachable ( <STR_LIT> ) ; return


<s> void <ISA_LIT>Z80AsmPrinter :: EmitFunctionBodyStart ( ) { const MachineRegisterInfo & MRI = MF -> getRegInfo ( ) ; SmallString < <NUM_LIT> > C ; raw_svector_ostream O ( C ) ; O << <STR_LIT> << MF -> getName ( ) << <STR_LIT> ; OutStreamer -> emitRawComment ( C , false ) ; C . clear ( ) ; O << <STR_LIT> ; if ( ! MRI . livein_empty ( ) ) { for ( MachineRegisterInfo :: livein_iterator I = MRI . livein_begin ( ) , E = MRI . livein_end ( ) ; I != E ; ++ I ) { O << printReg ( I -> first , MRI . getTargetRegisterInfo ( ) ) ; if ( std :: next ( I )


<s> return Mod . VariantKind == Kind ; } ) ; if ( Modifier != std :: end


<s> eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { MBB . erase ( I )


<s> auto matchAsInsertPS = [ & ] ( SDValue VA , SDValue VB , ArrayRef < int > CandidateMask ) { unsigned ZMask = <NUM_LIT> ; int VADstIndex = - <NUM_LIT> ; int VBDstIndex = - <NUM_LIT> ; bool VAUsedInPlace = false ; for ( int i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) { if ( Zeroable [ i ] ) { ZMask |= <NUM_LIT> << i ; continue ; } if ( i == CandidateMask [ i ] ) { VAUsedInPlace = true ; continue ; } if ( VADstIndex >= <NUM_LIT> || VBDstIndex >= <NUM_LIT> ) return false ; if ( CandidateMask [ i ] < <NUM_LIT> ) { VADstIndex = i ; } else { VBDstIndex = i ; } } if ( VADstIndex < <NUM_LIT> && VBDstIndex < <NUM_LIT> ) return false ; unsigned VBSrcIndex = <NUM_LIT> ; if ( VADstIndex >= <NUM_LIT> ) { VBSrcIndex = CandidateMask [ VADstIndex ] ; VBDstIndex = VADstIndex ; VB = VA ; } else { VBSrcIndex = CandidateMask [ VBDstIndex ] - <NUM_LIT> ; } if ( ! VAUsedInPlace ) VA = DAG . getUNDEF ( <STR_LIT> ) ; V1 = VA ; V2 = VB ; InsertPSMask = VBSrcIndex << <NUM_LIT> | VBDstIndex << <NUM_LIT> | ZMask ; assert ( ( InsertPSMask & ~ <NUM_LIT> ) == <NUM_LIT> && <STR_LIT> ) ; return true ; } ; if ( matchAsInsertPS ( V1 , V2 , Mask ) ) return true ; SmallVector < int , <NUM_LIT> > CommutedMask ( Mask . begin ( ) , Mask .


<s> auto UsePos = MachineBasicBlock :: iterator ( UseMI ) ; MachineBasicBlock :: instr_iterator InsertPt = UsePos . getInstrIterator ( ) ; short NewOpCode = getBaseWithLongOffset ( * UseMI ) ; assert ( NewOpCode >= <NUM_LIT> && <STR_LIT> ) ; unsigned OpStart ; unsigned OpEnd = UseMI -> getNumOperands ( ) ; MachineBasicBlock * BB = UseMI -> getParent ( ) ; MachineInstrBuilder MIB = BuildMI ( * BB , InsertPt , UseMI -> getDebugLoc ( ) , HII -> get ( NewOpCode ) ) ; if ( UseMID . mayLoad ( ) ) { MIB . add ( UseMI -> getOperand ( <NUM_LIT> ) ) ; MIB . add ( AddAslMI -> getOperand ( <NUM_LIT> ) ) ; MIB . add ( AddAslMI -> getOperand ( <NUM_LIT> ) ) ; const GlobalValue * GV = ImmOp . getGlobal ( ) ; MIB . addGlobalAddress ( GV , UseMI -> getOperand ( <NUM_LIT> ) . getImm ( ) + ImmOp . getOffset ( ) , ImmOp . getTargetFlags ( ) ) ; OpStart = <NUM_LIT> ; } else if ( UseMID . mayStore ( ) ) { MIB . add ( AddAslMI -> getOperand ( <NUM_LIT> ) ) ; MIB . add ( AddAslMI -> getOperand ( <NUM_LIT> ) ) ; const GlobalValue * GV = ImmOp . getGlobal ( ) ; MIB . addGlobalAddress ( GV , UseMI -> getOperand ( <NUM_LIT> ) . getImm ( ) + ImmOp . getOffset ( ) , ImmOp . getTargetFlags ( ) ) ; MIB . add ( UseMI -> getOperand ( <NUM_LIT> ) ) ; OpStart = <NUM_LIT> ; } else llvm_unreachable ( <STR_LIT> ) ; for ( unsigned i = OpStart ; i < OpEnd ; ++ i ) MIB . add ( UseMI -> getOperand ( i ) ) ; Deleted . insert (


<s> static void AnalyzeVarArgs ( CCState & State , const


<s> virtual const <ISA_LIT>Subtarget * getSubtargetImpl ( ) const { return &


<s> if ( GlobalAddressSDNode * G = dyn_cast < GlobalAddressSDNode > ( Callee ) ) { if ( Callee . getOpcode ( ) == <STR_LIT> || Callee

. getOpcode ( ) == <STR_LIT> ) return false ;


<s> int getIORegSPL ( void ) const { return


<s> return false ; } RTLIB :: Libcall LC = RTLIB :: UNKNOWN_LIBCALL ; if ( VT == <STR_LIT> ) LC = isSigned ? RTLIB :: SREM_I8 : RTLIB :: UREM_I8 ; else if ( VT == <STR_LIT> ) LC = isSigned ? RTLIB :: SREM_I16 : RTLIB :: UREM_I16 ; else if ( VT == <STR_LIT> ) LC =

isSigned ? RTLIB :: SREM_I32 : RTLIB :: UREM_I32 ;


<s> static inline bool isSVECpyImmByte ( int64_t


<s> static MCRegisterInfo * create<ISA_LIT>MCRegisterInfo ( StringRef TT ) { MCRegisterInfo * X = new MCRegisterInfo ( ) ; Init<ISA_LIT>MCRegisterInfo ( X , <NUM_LIT> ) ; return X


<s> int bitpos = TRI -> getS0Index ( predReg ) ; assert ( bitpos > <NUM_LIT> ) ; AddDefaultPred ( BuildMI ( MBB , MI , DL , TII -> get ( <STR_LIT> ) , tmpReg ) ) . addFrameIndex ( fi ) . addImm ( <NUM_LIT> ) ; BuildMI ( MBB , MI , DL , TII -> get ( <STR_LIT> ) , tmpReg ) . addReg ( guard ) . addImm ( <NUM_LIT> ) . addReg ( tmpReg ) . addImm ( bitpos ) . add ( Cond [ <NUM_LIT> ] ) . add ( Cond [ <NUM_LIT> ] ) ; InsertedInstrs ++ ; uint32_t or_bitmask = <NUM_LIT> << bitpos ; AddDefaultPred ( BuildMI ( MBB , MI , DL , TII -> get ( <STR_LIT> ) , PRTmp ) ) . addReg ( guard ) . addImm ( <NUM_LIT> ) . addOperand ( Cond [ <NUM_LIT> ] ) . addOperand ( Cond [ <NUM_LIT> ] ) ; assert ( isUInt < <NUM_LIT> > ( or_bitmask ) ; BuildMI ( MBB , MI , DL , TII -> get ( <STR_LIT> ) , tmpReg ) . addReg ( PRTmp ) . addImm ( <NUM_LIT> ) . addReg ( tmpReg ) . addImm ( or_bitmask ) ; InsertedInstrs += <NUM_LIT> ; AddDefaultPred ( BuildMI ( MBB , MI , DL , TII -> get ( <STR_LIT> ) ) ) . addFrameIndex ( fi ) . addImm ( <NUM_LIT> ) . addReg ( tmpReg , RegState :: Kill ) ; InsertedInstrs += <NUM_LIT>


<s> bool <ISA_LIT>PassConfig :: addGlobalInstructionSelect ( ) { addPass ( new InstructionSelect ( getOptLevel ( ) ) ) ; return false


<s> return DAG . getTargetJumpTable ( N -> getIndex ( ) , Ty ,


<s> rtx * regs ; bits = BITS_PER_WORD ; mode = int_mode_for_size ( bits , <NUM_LIT> ) . require ( ) ; delta = bits / BITS_PER_UNIT ; regs = XALLOCAVEC ( rtx , length / delta ) ; for ( offset = <NUM_LIT> , i = <NUM_LIT> ; offset + delta <= length ; offset += delta , i ++ ) { regs [ i ] = gen_reg_rtx ( mode ) ; emit_move_insn ( regs [ i ] , adjust_address ( src , mode , offset ) ) ; } for ( offset = <NUM_LIT> , i = <NUM_LIT> ; offset + delta <= length ; offset += delta , i ++ ) emit_move_insn ( adjust_address ( dest , mode , offset ) , regs [ i ] ) ; if ( offset < length ) { src = adjust_address ( src , BLKmode ,


<s> uint16x4_t result ; __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT> ( b ) , <STR_LIT> (


<s> bool <ISA_LIT>MCExpr :: evaluateAsRelocatableImpl ( MCValue & Res , const MCAsmLayout * Layout , const MCFixup * Fixup ) const { return getSubExpr ( ) -> evaluateAsRelocatable ( Res


<s> void initialize ( Attributor & A ) override { Function * F = getAssociatedFunction ( ) ; auto & InfoCache = static_cast < <ISA_LIT>InformationCache & > ( A . getInfoCache ( ) ) ; unsigned MinGroupSize , MaxGroupSize ; std :: tie ( MinGroupSize , MaxGroupSize ) = InfoCache . getFlatWorkGroupSizes


<s> else FrameReg = getFrameRegister ( MF ) ; int64_t Offset ; Offset = SPOffset + ( int64_t ) StackSize ; Offset += MI . getOperand ( OpNo + <NUM_LIT> ) . getImm ( ) ; DEBUG ( errs ( ) << <STR_LIT> << Offset << <STR_LIT> << <STR_LIT> ) ; MI . getOperand ( OpNo ) . ChangeToRegister ( FrameReg , false ) ; MI . getOperand ( OpNo + <NUM_LIT> )


<s> bool <ISA_LIT>DAGToDAGISel :: SelectADDRrr ( SDValue Addr , SDValue & R1 , SDValue & R2 ) { if ( Addr . getOpcode ( ) == <STR_LIT> ) return false ; if ( Addr . getOpcode ( ) == <STR_LIT> || Addr . getOpcode ( ) == <STR_LIT> ) return false ; if ( Addr . getOpcode ( ) == <STR_LIT>


<s> MCOp = lowerSymbolOperand ( MO , Printer . getSymbol ( MO . getGlobal ( ) ) ) ; break ; case MachineOperand :: MO_ExternalSymbol : MCOp = lowerSymbolOperand ( MO , Printer . GetExternalSymbolSymbol ( MO . getSymbolName ( ) ) ) ; break ; case MachineOperand :: MO_MachineBasicBlock : MCOp = MCOperand :: createExpr ( MCSymbolRefExpr :: create ( MO . getMBB ( ) -> getSymbol ( ) , Ctx ) ) ; break ; case MachineOperand :: MO_RegisterMask : continue ; case MachineOperand :: MO_BlockAddress : MCOp = lowerSymbolOperand ( MO , Printer . GetBlockAddressSymbol ( MO . getBlockAddress ( ) ) ) ; break ; case MachineOperand :: MO_JumpTableIndex : MCOp = lowerSymbolOperand ( MO , Printer . GetJTISymbol ( MO . getIndex ( ) ) ) ; break ; case MachineOperand :: MO_ConstantPoolIndex : MCOp = lowerSymbolOperand ( MO , Printer . GetCPISymbol ( MO . getIndex (


<s> static bool different_mask_policy_p ( const vector_insn_info & info1 , const


<s> MCFixupKind Kind = MCFixupKind ( <STR_LIT> ) ; Fixups . push_back ( MCFixup :: Create ( <NUM_LIT> , Expr , Kind ) ) ; ++ MCNumCPRelocations ; } else isAdd = EncodeAddrModeOpValues ( MI , OpIdx , Reg , Imm8 , Fixups ) ; uint32_t Binary = ( Imm8 >> <NUM_LIT> ) & <NUM_LIT> ; if ( isAdd ) Binary |= ( <NUM_LIT> << <NUM_LIT> ) ; Binary |= ( Reg << <NUM_LIT> ) ; return Binary


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( MI -> getOperand ( <NUM_LIT> ) . getSubReg ( ) == <NUM_LIT> && MI -> getOperand ( <NUM_LIT> ) . isFI ( ) && MI -> getOperand ( <NUM_LIT> ) . isImm ( ) && MI -> getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) { FrameIndex = MI -> getOperand ( <NUM_LIT>


<s> const TargetInstrInfo & TII = * BB -> getParent ( ) -> getSubtarget ( ) . getInstrInfo ( ) ; DebugLoc dl = MI . getDebugLoc ( ) ; assert ( Opc == <STR_LIT> && <STR_LIT> ) ; const BasicBlock * LLVM_BB = BB -> getBasicBlock ( ) ; MachineFunction :: iterator I = ++ BB -> getIterator ( ) ; MachineBasicBlock * thisMBB = BB ; MachineFunction * F = BB -> getParent ( ) ; MachineBasicBlock * copy0MBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * copy1MBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; F -> insert ( I , copy0MBB ) ; F -> insert ( I , copy1MBB ) ; copy1MBB -> splice ( copy1MBB -> begin ( ) , BB , std :: next ( MachineBasicBlock :: iterator ( MI


<s> unsigned BPReg = HasBP ? ( unsigned ) RegInfo -> getBaseRegister ( MF ) : FPReg ; unsigned BP8Reg = HasBP ? ( unsigned ) <STR_LIT> : FPReg ; for ( MachineFunction :: iterator BI = MF . begin ( ) , BE = MF . end ( ) ; BI != BE ; ++ BI ) for ( MachineBasicBlock :: iterator MBBI = BI -> end ( ) ; MBBI != BI -> begin ( ) ; ) { -- MBBI ; for ( unsigned I = <NUM_LIT> , E = MBBI -> getNumOperands ( ) ; I != E ; ++ I ) { MachineOperand & MO = MBBI -> getOperand ( I ) ; if ( ! MO . isReg ( ) ) continue ; switch ( MO . getReg ( ) ) { case <STR_LIT> : MO . setReg ( FPReg ) ; break ; case <STR_LIT> : MO . setReg ( FP8Reg ) ; break ; case <STR_LIT> : MO . setReg ( BPReg ) ; break ; case


<s> return <STR_LIT> ( Op , LogicalOpIdx


<s> return ( __m64 ) __builtin_ia32_pavgb ( ( __v8qi


<s> if ( IsSubWord ) BitSize = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; const TargetRegisterClass * RC = ( BitSize <= <NUM_LIT> ? & <STR_LIT> : & <STR_LIT> ) ; unsigned LOpcode = BitSize <= <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; unsigned CSOpcode = BitSize <= <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; LOpcode = TII -> getOpcodeForOffset ( LOpcode , Disp ) ; CSOpcode = TII -> getOpcodeForOffset ( CSOpcode , Disp ) ; assert ( LOpcode && CSOpcode && <STR_LIT> ) ; unsigned OrigVal = MRI . createVirtualRegister ( RC ) ; unsigned OldVal = MRI . createVirtualRegister ( RC ) ; unsigned NewVal = MRI . createVirtualRegister ( RC ) ; unsigned RotatedOldVal = ( IsSubWord ? MRI . createVirtualRegister ( RC ) : OldVal ) ; unsigned RotatedAltVal = ( IsSubWord ? MRI . createVirtualRegister ( RC ) : Src2 ) ; unsigned RotatedNewVal = ( IsSubWord ? MRI . createVirtualRegister ( RC ) : NewVal ) ; MachineBasicBlock * StartMBB = MBB ; MachineBasicBlock * DoneMBB = splitBlockBefore ( MI , MBB ) ; MachineBasicBlock * LoopMBB = emitBlockAfter ( StartMBB ) ; MachineBasicBlock * UseAltMBB = emitBlockAfter ( LoopMBB ) ; MachineBasicBlock * UpdateMBB = emitBlockAfter ( UseAltMBB ) ; MBB = StartMBB ; BuildMI ( MBB , DL , TII -> get ( LOpcode ) , OrigVal ) . addOperand ( Base ) . addImm ( Disp ) . addReg ( <NUM_LIT> ) ; MBB -> addSuccessor ( LoopMBB ) ; MBB =


<s> MCAsmBackend * llvm :: create<ISA_LIT>AsmBackendEL32 ( const Target & T , const MCSubtargetInfo & STI , const

MCRegisterInfo & MRI , const MCTargetOptions & Options ) {


<s> if ( VT . getSizeInBits ( ) / <NUM_LIT> > LS -> getAlignment ( ) ) { assert ( <STR_LIT> ) ; if ( VT == <STR_LIT> ) return false ; } } if ( FrameIndexSDNode * FIN = dyn_cast < FrameIndexSDNode > ( Addr ) ) { Base = CurDAG -> getTargetFrameIndex ( FIN -> getIndex ( ) , ValTy ) ; Offset = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , ValTy ) ; return true ; } if ( Addr . getOpcode ( ) == <STR_LIT> ) { Base = Addr . getOperand ( <NUM_LIT> ) ; Offset = Addr . getOperand ( <NUM_LIT>


<s> GrpCount = <NUM_LIT> ; LastFPdOpCycleIdx = UINT_MAX ; LastEmittedMI = nullptr ; LLVM_DEBUG ( CurGroupDbg = <STR_LIT>


<s> ++ Position ; while ( Position != CurDAG -> allnodes_begin ( ) ) { SDNode * N = & * -- Position ; if ( N -> use_empty ( ) || ! N -> isMachineOpcode ( ) ) continue ; if ( N -> getMachineOpcode ( ) != TargetOpcode :: SUBREG_TO_REG ) continue ; unsigned SubRegIdx = N -> getConstantOperandVal ( <NUM_LIT> ) ; if ( SubRegIdx != <STR_LIT> && SubRegIdx != <STR_LIT> ) continue ; SDValue Move = N -> getOperand ( <NUM_LIT> ) ; if ( ! Move . isMachineOpcode ( ) ) continue ; switch ( Move . getMachineOpcode ( ) ) { default : continue ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> TargetLowering :: CallLoweringInfo CLI ( DAG ) ; CLI . setDebugLoc ( dl ) . setChain ( DAG . getEntryNode ( ) ) . setCallee ( CallingConv :: Fast , RetTy , Callee , std :: move ( Args ) ) ; std :: pair < SDValue , SDValue > CallResult = LowerCallTo ( CLI ) ; return CallResult . first


<s> else regno = REG_R7 + <NUM_LIT> ; for ( i = <NUM_LIT> ; i < total ; i ++ ) { rtx addr = ( i > <NUM_LIT> ? gen_rtx_PLUS ( Pmode , spreg , GEN_INT ( i * <NUM_LIT> ) ) : spreg ) ; rtx memref = gen_rtx_MEM ( word_mode , addr ) ; regno -- ; XVECEXP ( pat , <NUM_LIT> , i + <NUM_LIT> ) = gen_rtx_SET ( VOIDmode , gen_rtx_REG ( word_mode , regno ) , memref ) ; if ( npregs > <NUM_LIT>


<s> ix86_first_cycle_multipass_data_t data = ( ix86_first_cycle_multipass_data_t ) _data ; data -> ifetch_block_len =


<s> } return false ; } ; if ( ! Disp ) { if ( ! isAtMemOperand ( ) ) { if ( Parser . parseTokenLoc ( Loc ) || Parser . parseExpression ( Disp , EndLoc ) ) return true ; assert ( ! isa < <ISA_LIT>MCExpr > ( Disp ) && <STR_LIT> ) ; } else { Disp = MCConstantExpr :: create ( <NUM_LIT> , Parser . getContext ( ) ) ; } } if ( ! parseOptionalToken ( AsmToken :: LParen ) ) { if ( SegReg == <NUM_LIT> ) Operands . push_back ( <STR_LIT> ( getPointerWidth ( ) , Disp , StartLoc , EndLoc ) ) ; else Operands . push_back ( <STR_LIT> ( getPointerWidth ( ) , SegReg , Disp , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , StartLoc , EndLoc ) ) ; return false ; } unsigned BaseReg = <NUM_LIT> , IndexReg = <NUM_LIT> , Scale = <NUM_LIT> ; SMLoc BaseLoc = getLexer ( ) . getLoc ( ) ; const MCExpr * E ; StringRef ErrMsg ; if ( getLexer ( ) . isNot ( AsmToken :: Comma ) && getLexer ( ) . isNot ( AsmToken :: RParen ) ) { if ( Parser . parseExpression ( E , EndLoc ) || check ( ! isa < <ISA_LIT>MCExpr > ( E ) , BaseLoc , <STR_LIT> ) ) return true ; BaseReg = cast < <ISA_LIT>MCExpr > ( E ) -> getRegNo ( ) ; if ( BaseReg == <STR_LIT> || BaseReg == <STR_LIT> ) return Error ( BaseLoc , <STR_LIT> , SMRange ( BaseLoc , EndLoc ) ) ; } if ( parseOptionalToken ( AsmToken :: Comma ) ) { if ( getLexer ( ) . isNot ( AsmToken :: RParen ) ) { if ( Parser . parseTokenLoc ( Loc ) || Parser . parseExpression ( E , EndLoc ) ) return true ; if ( ! isa < <ISA_LIT>MCExpr > ( E ) ) { int64_t ScaleVal ; if ( ! E -> evaluateAsAbsolute ( ScaleVal , getStreamer ( ) . getAssemblerPtr ( ) ) ) return Error ( Loc , <STR_LIT> ) ; if ( ScaleVal != <NUM_LIT> ) Warning ( Loc , <STR_LIT> ) ; Scale = <NUM_LIT> ; } else { IndexReg = cast < <ISA_LIT>MCExpr > ( E ) -> getRegNo ( ) ; if ( BaseReg == <STR_LIT> ) return Error ( Loc , <STR_LIT> ) ; if ( IndexReg == <STR_LIT> ) return Error ( Loc , <STR_LIT> ) ; if ( parseOptionalToken ( AsmToken :: Comma ) ) { if ( getLexer ( ) . isNot ( AsmToken :: RParen ) ) { int64_t


<s> } else if ( NeedFP ) { BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) , FramePtrReg ) . addReg ( StackPtrReg ) . setMIFlag ( MachineInstr :: FrameSetup ) ; } if ( RoundedSize != <NUM_LIT> && hasSP ( MF ) ) { BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) , StackPtrReg ) . addReg ( StackPtrReg ) . addImm ( RoundedSize * ST . getWavefrontSize ( ) ) . setMIFlag ( MachineInstr :: FrameSetup ) ; } unsigned ScratchExecCopy = <STR_LIT> ; for ( const <ISA_LIT>MachineFunctionInfo :: SGPRSpillVGPRCSR & Reg : FuncInfo -> getSGPRSpillVGPRs ( ) ) { if ( ! Reg . FI . hasValue ( ) ) continue ; if ( ScratchExecCopy == <STR_LIT> ) { if ( LiveRegs . empty ( ) ) { LiveRegs . init ( TRI ) ; LiveRegs . addLiveIns ( MBB ) ; } ScratchExecCopy = findScratchNonCalleeSaveRegister ( MF , LiveRegs , <STR_LIT> ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) , ScratchExecCopy ) . addImm ( - <NUM_LIT> ) ; } TII -> storeRegToStackSlot ( MBB , MBBI , Reg . VGPR , true , Reg . FI .

getValue ( ) , & <STR_LIT> , & TII -> getRegisterInfo ( ) ) ;


<s> return new <ISA_LIT>AsmBackend ( T , TT . getOS ( ) , true


<s> VecOp0 = CurDAG -> getMachineNode ( <STR_LIT> , dl , VecVT , Op0 ) ; if ( ConstantSDNode * CN = dyn_cast < ConstantSDNode > ( ShiftAmt ) ) { unsigned bytes = unsigned ( CN -> getZExtValue ( ) ) >> <NUM_LIT> ; unsigned bits = unsigned ( CN -> getZExtValue ( ) ) & <NUM_LIT> ; if ( bytes > <NUM_LIT> ) { Shift = CurDAG -> getMachineNode ( <STR_LIT> , dl , VecVT , SDValue ( VecOp0 , <NUM_LIT> ) , CurDAG -> getTargetConstant ( bytes , ShiftAmtVT ) ) ; } if ( bits > <NUM_LIT> ) { Shift = CurDAG -> getMachineNode ( <STR_LIT> , dl , VecVT , SDValue ( ( Shift != <NUM_LIT> ? Shift : VecOp0 ) , <NUM_LIT> ) , CurDAG -> getTargetConstant ( bits , ShiftAmtVT ) ) ; } } else


<s> const MCExpr * Val = <NUM_LIT> ; InlineAsmIdentifierInfo Info ; SMLoc Start = Tok . getLoc ( ) , End ; StringRef Identifier = Tok . getString ( ) ; if ( ParseIntelIdentifier ( Val , Identifier , Info , true , End ) ) return <NUM_LIT> ; if ( ! Info . OpDecl ) return ErrorOperand ( Start , <STR_LIT> ) ; unsigned CVal = <NUM_LIT> ; switch (


<s> static bool ia64_vectorize_vec_perm_const ( machine_mode vmode , rtx target , rtx op0 , rtx op1 , const vec_perm_indices & sel ) { struct expand_vec_perm_d d ; unsigned char perm [ MAX_VECT_LEN ] ; unsigned int i , nelt , which ; d . target = target ; if ( op0 ) { rtx nop0 = force_reg ( vmode , op0 ) ; if ( op0 == op1 ) op1 = nop0 ; op0 = nop0 ; } if ( op1 ) op1 = force_reg ( vmode , op1 ) ; d . op0 = op0 ; d . op1 = op1 ; d . vmode = vmode ; gcc_assert ( VECTOR_MODE_P ( d . vmode ) ) ; d . nelt = nelt = GET_MODE_NUNITS ( d . vmode ) ; d . testing_p = ! target ; gcc_assert ( sel . length ( ) == nelt ) ; gcc_checking_assert ( sizeof ( d . perm ) == sizeof ( perm ) ) ; for ( i = which = <NUM_LIT> ; i < nelt ; ++ i ) { unsigned int ei = sel [ i ] & ( <NUM_LIT> * nelt - <NUM_LIT> ) ; which |= ( ei < nelt ? <NUM_LIT> : <NUM_LIT> ) ; d . perm [ i ] = ei ; perm [ i ] = ei ; } switch ( which ) { default : gcc_unreachable ( ) ; case <NUM_LIT> : if ( d . testing_p || ! rtx_equal_p ( d . op0 , d . op1 ) ) { d . one_operand_p = false ; break ; } for ( i = <NUM_LIT> ; i < nelt ; ++ i ) if ( d . perm [ i ] >= nelt ) d . perm [ i ] -= nelt ; case <NUM_LIT>


<s> unsigned Reg1 = MRI . getSubReg ( Reg , <STR_LIT> ) ; O << <STR_LIT> ; printRegName ( O , Reg0 ) ; O << <STR_LIT>


<s> bool BranchDelayBase :: runOnMachineFunction ( MachineFunction & F ) { bool Changed = false ; for ( MachineFunction :: iterator FI = F . begin ( ) , FE = F .


<s> void <ISA_LIT>GNULDBackend :: preMergeSections ( Module


<s> assert ( Size + Offset <= <NUM_LIT> && <STR_LIT> ) ; assert ( uintDoesFit ( Size , Val ) ) ; Size += Pad ; Buffer |= Val << Offset ; return


<s> for ( SUnit * SU : ScheduledSUnits ) { RPTracker . setPos ( SU -> getInstr ( ) ) ; RPTracker . advance ( ) ; } RPTracker . closeRegion ( ) ; TopRPTracker . addLiveRegs ( RPTracker . getPressure ( ) . LiveInRegs ) ; BotRPTracker . addLiveRegs ( RPTracker . getPressure ( ) . LiveOutRegs ) ; for ( const auto & RegMaskPair : RPTracker . getPressure ( ) . LiveInRegs ) { if ( TargetRegisterInfo :: isVirtualRegister ( RegMaskPair . RegUnit ) ) LiveInRegs . insert ( RegMaskPair . RegUnit ) ; } LiveOutRegs . clear ( ) ; for ( const auto & RegMaskPair : RPTracker . getPressure ( ) . LiveOutRegs ) { unsigned Reg = RegMaskPair . RegUnit ; if ( TargetRegisterInfo :: isVirtualRegister ( Reg ) && isDefBetween ( Reg , LIS -> getInstructionIndex ( * BeginBlock ) . getRegSlot ( ) , LIS -> getInstructionIndex ( * EndBlock ) . getRegSlot ( ) , MRI , LIS ) ) { LiveOutRegs . insert ( Reg ) ; } } LiveInPressure = TopPressure . MaxSetPressure ; LiveOutPressure = BotPressure .


<s> static SDValue PromoteMVEPredVector ( SDLoc dl , SDValue Pred , EVT VT , SelectionDAG & DAG ) { SDValue AllOnes = DAG . getTargetConstant ( <STR_LIT> ( <NUM_LIT> , <NUM_LIT> ) , dl , <STR_LIT> ) ; AllOnes = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , AllOnes ) ; SDValue AllZeroes = DAG . getTargetConstant ( <STR_LIT> ( <NUM_LIT> , <NUM_LIT> ) , dl , <STR_LIT> ) ; AllZeroes = DAG . getNode ( <STR_LIT> ,


<s> setStackPointerRegisterToSaveRestore ( <STR_LIT> ) ; setSchedulingPreference ( Sched :: Source ) ; setBooleanContents ( ZeroOrOneBooleanContent ) ; setBooleanVectorContents ( ZeroOrOneBooleanContent ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom


<s> if ( isCalleeStructRet || isCallerStructRet ) return false ; if ( GlobalAddressSDNode * G = dyn_cast < GlobalAddressSDNode > ( Callee ) ) { const GlobalValue * GV = G -> getGlobal ( ) ; const Triple & TT = getTargetMachine ( ) . getTargetTriple ( ) ; if ( GV -> hasExternalWeakLinkage ( ) && ( ! TT . isOSWindows ( ) || TT . isOSBinFormatELF ( ) || TT . isOSBinFormatMachO ( ) ) ) return false ; } LLVMContext & C = * DAG . getContext ( ) ; if ( ! CCState :: resultsCompatible ( CalleeCC , CallerCC , MF , C , Ins , CCAssignFnForNode ( CalleeCC , true , isVarArg ) , CCAssignFnForNode ( CallerCC , true , isVarArg ) ) ) return false ; const <ISA_LIT>BaseRegisterInfo * TRI = Subtarget -> getRegisterInfo ( ) ; const uint32_t * CallerPreserved = TRI -> getCallPreservedMask ( MF , CallerCC ) ; if ( CalleeCC != CallerCC ) { const uint32_t * CalleePreserved = TRI -> getCallPreservedMask ( MF , CalleeCC ) ; if ( ! TRI -> regmaskSubsetEqual ( CallerPreserved , CalleePreserved ) ) return false ; } const <ISA_LIT>FunctionInfo * AFI_Caller = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; if ( AFI_Caller -> getArgRegsSaveSize ( ) ) return false ; if ( ! Outs . empty ( ) ) { SmallVector < CCValAssign , <NUM_LIT> > ArgLocs ; <ISA_LIT>CCState CCInfo ( CalleeCC , isVarArg , MF , ArgLocs , C , Call ) ; CCInfo . AnalyzeCallOperands ( Outs , CCAssignFnForNode ( CalleeCC , false , isVarArg ) ) ; if ( CCInfo . getNextStackOffset ( ) ) { MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const MachineRegisterInfo * MRI = & MF . getRegInfo ( ) ; const TargetInstrInfo * TII = Subtarget -> getInstrInfo ( ) ; for ( unsigned i = <NUM_LIT> , realArgIdx = <NUM_LIT> , e = ArgLocs . size ( ) ; i != e ; ++ i , ++ realArgIdx ) { CCValAssign & VA = ArgLocs [ i ] ; EVT RegVT = VA . getLocVT ( ) ; SDValue Arg = OutVals [ realArgIdx ] ; <STR_LIT> Flags = Outs [ realArgIdx ] . Flags ; if ( VA . getLocInfo ( ) == CCValAssign :: Indirect ) return false ; if ( VA . needsCustom (


<s> assert ( V1 . getValueType ( ) == V2 . getValueType ( ) && <STR_LIT> ) ; EVT SubVT = V1 . getValueType ( ) ; EVT SubSVT = SubVT . getScalarType ( ) ; unsigned SubNumElts = SubVT . getVectorNumElements ( ) ; unsigned SubVectorWidth = SubVT . getSizeInBits ( ) ; EVT VT = EVT :: getVectorVT ( * DAG . getContext ( ) , SubSVT , <NUM_LIT> * SubNumElts ) ; SDValue V = insertSubVector ( DAG . getUNDEF ( VT ) ,

V1 , <NUM_LIT> , DAG , dl , SubVectorWidth ) ;


<s> for ( const auto & I : B ) { if ( const auto * RetInst = dyn_cast_or_null < ReturnInst > ( & I ) ) { Type * NewRetTy = classifyPointerType ( RetInst -> getReturnValue ( ) ) ; if ( ! RetTy ) RetTy = NewRetTy ; else if ( RetTy != NewRetTy ) RetTy = TypedPointerType :: get ( Type :: getInt8Ty ( I . getContext ( ) ) , F . getReturnType ( ) -> getPointerAddressSpace ( ) ) ; } } } } for ( auto & A : F . args ( ) ) { Type * ArgTy = A . getType ( ) ; if ( ArgTy -> isOpaquePointerTy ( ) ) { TypedPointerType * NewTy = classifyPointerType ( & A ) ; Map [ & A ] = NewTy ; ArgTy = NewTy ; HasOpaqueTy =


<s> void <ISA_LIT>InstPrinter :: printNamedOpOrImm ( const MCInst * MI , unsigned OpNum , const MCSubtargetInfo & STI , raw_ostream & O ) { unsigned Val = MI -> getOperand ( OpNum ) . getImm ( ) ; bool Valid


<s> SDLoc DL ( Op ) ; SDValue Mult = DAG . getNode ( NewOpc , DL , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; SDValue Lo , Hi ; if ( HasLo ) Lo = DAG . getNode (


<s> return NoFramePointerElim || MF . getFrameInfo ( ) ->


<s> rtx cond = XEXP ( XEXP ( pc_set_rtx , <NUM_LIT> ) , <NUM_LIT> ) ; bool branch_if ; if ( GET_CODE ( cond ) == NE && REG_P ( XEXP ( cond , <NUM_LIT> ) ) && REGNO ( XEXP ( cond , <NUM_LIT> ) ) == REGNO ( m_ccreg ) && XEXP ( cond , <NUM_LIT> ) == const0_rtx ) branch_if = true ; else if ( GET_CODE ( cond ) == EQ && REG_P ( XEXP ( cond , <NUM_LIT> ) ) && REGNO ( XEXP ( cond , <NUM_LIT> ) ) == REGNO ( m_ccreg ) && XEXP ( cond , <NUM_LIT> ) == const0_rtx ) branch_if = false ; else gcc_unreachable ( ) ; if ( branch_target_bb == BRANCH_EDGE ( cbranch_insn_bb ) -> dest ) return branch_if ; else if ( branch_target_bb == FALLTHRU_EDGE ( cbranch_insn_bb ) -> dest ) return ! branch_if ; else gcc_unreachable (


<s> SDValue Cmp ; if ( LHS . getValueType ( ) == <STR_LIT> ) { Cmp = geti8CC ( LHS , RHS , CC , TargetCC , DAG , dl ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , TrueV , FalseV , TargetCC , Cmp ) ; } assert ( LHS . getValueType ( ) == <STR_LIT>


<s> emit_insn ( gen_rtx_SET ( ptr , frame_pointer_rtx ) ) ; if ( fs ) { idx = gen_reg_rtx ( SImode ) ; pred = gen_reg_rtx ( BImode ) ; label = gen_label_rtx ( ) ; emit_insn ( gen_rtx_SET ( idx , GEN_INT ( fs ) ) ) ; rtx init = fn ( tmp , PM_loop_begin , fs , data ) ; if ( init ) emit_insn ( init ) ; emit_label ( label ) ; LABEL_NUSES ( label ) ++ ; emit_insn ( gen_addsi3 ( idx , idx , GEN_INT ( - <NUM_LIT> ) ) ) ; } if ( rw & PM_read ) emit_insn ( gen_rtx_SET ( tmp , gen_rtx_MEM ( DImode , ptr ) ) ) ; emit_insn ( fn ( tmp , rw , fs , data ) ) ; if ( rw & PM_write ) emit_insn ( gen_rtx_SET ( gen_rtx_MEM ( DImode , ptr ) , tmp ) ) ; if ( fs ) { emit_insn ( gen_rtx_SET ( pred , gen_rtx_NE ( BImode , idx , const0_rtx ) ) ) ; emit_insn ( gen_adddi3 ( ptr , ptr , GEN_INT ( GET_MODE_SIZE ( DImode ) ) ) ) ; emit_insn ( gen_br_true_uni ( pred , label ) ) ; rtx fini = fn ( tmp , PM_loop_end , fs , data ) ; if ( fini ) emit_insn ( fini )


<s> BuildMI ( * MBB , MBB -> begin ( ) , MI . getDebugLoc ( ) , TII -> get ( IsWave32 ? <STR_LIT> : <STR_LIT> ) , Exec ) . addImm ( MI . getOperand ( <NUM_LIT> ) . getImm ( ) ) ; if ( LIS ) LIS -> RemoveMachineInstrFromMaps ( MI ) ; MI . eraseFromParent ( ) ; return ; } Register InputReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; MachineInstr * FirstMI = & * MBB -> begin ( ) ; if ( InputReg . isVirtual ( ) ) { MachineInstr * DefInstr = MRI -> getVRegDef ( InputReg ) ; assert ( DefInstr && DefInstr -> isCopy ( ) ) ; if ( DefInstr -> getParent ( ) == MBB ) { if ( DefInstr != FirstMI ) { DefInstr -> removeFromParent ( ) ; MBB -> insert ( FirstMI , DefInstr ) ; if ( LIS ) LIS -> handleMove ( * DefInstr ) ; } else { FirstMI = & * std :: next ( FirstMI -> getIterator ( ) ) ; } } } const DebugLoc DL = MI . getDebugLoc ( ) ; const unsigned WavefrontSize = ST . getWavefrontSize ( ) ; const unsigned Mask = ( WavefrontSize << <NUM_LIT> ) - <NUM_LIT> ; Register CountReg = MRI -> createVirtualRegister ( & <STR_LIT> ) ; auto BfeMI = BuildMI ( * MBB , FirstMI , DL , TII -> get ( <STR_LIT> ) , CountReg ) . addReg ( InputReg ) . addImm ( ( MI . getOperand ( <NUM_LIT> ) . getImm ( ) & Mask ) | <NUM_LIT> ) ; if ( LV ) LV -> recomputeForSingleDefVirtReg ( InputReg ) ; auto BfmMI = BuildMI ( * MBB , FirstMI , DL , TII -> get ( IsWave32 ? <STR_LIT> : <STR_LIT> ) , Exec ) . addReg ( CountReg ) . addImm ( <NUM_LIT> ) ; auto CmpMI = BuildMI ( * MBB , FirstMI , DL , TII -> get ( <STR_LIT> ) ) . addReg ( CountReg , RegState :: Kill ) . addImm ( WavefrontSize ) ; if ( LV ) LV -> getVarInfo ( CountReg ) . Kills . push_back ( CmpMI ) ; auto CmovMI = BuildMI ( * MBB , FirstMI , DL , TII -> get ( IsWave32 ? <STR_LIT> : <STR_LIT> ) , Exec ) . addImm ( - <NUM_LIT> ) ; if ( ! LIS ) { MI . eraseFromParent ( ) ; return ; } LIS -> RemoveMachineInstrFromMaps ( MI ) ; MI . eraseFromParent ( ) ; LIS -> InsertMachineInstrInMaps ( * BfeMI ) ; LIS -> InsertMachineInstrInMaps (


<s> PULPFixupHwLoops ( ) : MachineFunctionPass ( ID ) { initializePULPFixupHwLoopsPass ( * PassRegistry ::


<s> inline static bool classof ( const MCStreamer * streamer ) { return


<s> return GuaranteedTailCallOpt && canGuaranteeTCO ( CC


<s> StringRef Name = getLexer ( ) . getTok ( ) . getIdentifier ( ) ; Register RegNo = MatchRegisterName ( Name ) ; getLexer ( ) . Lex ( ) ; Operands . push_back ( <ISA_LIT>Operand :: createVecReg ( RegNo ,


<s> if ( Ord == AtomicOrdering :: SequentiallyConsistent ) return callIntrinsic ( Builder , <STR_LIT> ) ; if ( isReleaseOrStronger ( Ord ) ) return callIntrinsic


<s> addPass ( create<ISA_LIT>RetpolineThunksPass ( )


<s> if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Op1 ) ) if ( C -> getAPIntValue ( ) == <NUM_LIT>

) return EmitTest ( Op0 , <ISA_LIT>CC , DAG ) ;


<s> MCContext & Context = Streamer . getContext ( ) ; const MCExpr * Res = MCSymbolRefExpr :: create ( Sym , MCSymbolRefExpr :: VK_GOT , Context ) ; MCSymbol * PCSym = Context . createTempSymbol ( ) ; Streamer . EmitLabel


<s> for ( unsigned i = <NUM_LIT> ; i < IDATASections . size ( ) ; i ++ ) delete IDATASections [ i ] ; for ( unsigned i = <NUM_LIT> ; i < AutosSections . size ( ) ; i ++ ) delete AutosSections [ i ] ; for ( unsigned i = <NUM_LIT> ; i < ROSections . size ( ) ; i ++ ) delete ROSections [ i ] ; delete ExternalVarDecls


<s> O << <STR_LIT> ; printLeaMemReference ( MI , OpNo ,


<s> assert ( VT == <STR_LIT> && <STR_LIT> ) ; SDValue Op0 = Op . getOperand ( <NUM_LIT> ) ; SDValue Op1 = Op . getOperand ( <NUM_LIT> ) ; SDLoc dl ( Op ) ; <STR_LIT> CC = cast < CondCodeSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> get ( ) ; if ( Op0 . getOpcode ( ) == <STR_LIT> && Op0 . hasOneUse ( ) && isNullConstant ( Op1 ) && ( CC == <STR_LIT> || CC == <STR_LIT> ) ) { if ( SDValue NewSetCC = LowerAndToBT ( Op0 , CC , dl , DAG ) ) return NewSetCC ; } if ( ( isOneConstant ( Op1 ) || isNullConstant ( Op1 ) ) && ( CC == <STR_LIT> || CC == <STR_LIT> ) ) { if ( Op0 . getOpcode ( ) == <STR_LIT> ) { <STR_LIT> CCode = ( <STR_LIT> ) Op0 . getConstantOperandVal ( <NUM_LIT> ) ; bool Invert = ( CC == <STR_LIT> ) ^ isNullConstant ( Op1 ) ; if ( ! Invert ) return Op0 ; CCode = <STR_LIT> ( CCode ) ; return getSETCC ( CCode , Op0 . getOperand ( <NUM_LIT> ) , dl , DAG ) ; } } bool IsFP = Op1 . getSimpleValueType ( ) . isFloatingPoint ( ) ; <STR_LIT> <ISA_LIT>CC = Translate<ISA_LIT>CC ( CC , dl , IsFP


<s> if ( LABEL_P ( lab ) && LABEL_NUSES ( lab ) < uses_threshold ) return <NUM_LIT> ; if ( optimize_size ) return <NUM_LIT> ; if ( rx_cpu_type == RX100 || rx_cpu_type == RX200 ) return


<s> PM . add ( createConstantPropagationPass ( ) ) ; PM . add ( createLoopSimplifyPass ( ) ) ; PM . add ( createDeadCodeEliminationPass ( ) ) ; PM . add ( createConstantPropagationPass ( )


<s> static const char * toString ( const Type * Ty , bool hasAddr64 ) { switch ( Ty -> getTypeID ( ) ) { default : break ; case Type :: PointerTyID : return hasAddr64 ? <STR_LIT> : <STR_LIT> ; case Type :: FloatTyID : return <STR_LIT> ; case Type :: DoubleTyID : return <STR_LIT> ; case Type :: IntegerTyID : switch ( Ty -> getIntegerBitWidth ( ) ) { case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; default : break ; } } DEBUG ( dbgs ( ) << <STR_LIT> ; Ty -> print ( dbgs ( ) ) ; dbgs ( ) << '\n' ) ; llvm_unreachable (


<s> inline int vec_all_ge ( vector float a1 , vector float


<s> bool <ISA_LIT>InstrInfo :: useMachineCombiner ( ) const { return


<s> if ( IsIndirect ) assert ( MI . getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> && <STR_LIT> ) ; return BuildMI ( * MBB , MBB -> erase ( & MI ) , DL , TII -> get ( TargetOpcode :: DBG_VALUE ) ,


<s> MachineFunction * MF = MI -> getParent ( ) -> getParent ( ) ; MachineInstr * PseudoMI = MF -> CreateMachineInstr ( QII -> get ( <STR_LIT> ) , MI -> getDebugLoc ( ) ) ; if ( ResourceTracker -> canReserveResources ( PseudoMI ) ) { ResourceTracker -> reserveResources ( PseudoMI ) ; MI -> getParent ( ) -> getParent ( )


<s> const MCRegisterInfo * MRI = getMRI ( ) ; const MCRegisterClass & VGRP32 = MRI -> getRegClass ( <STR_LIT> ) ; const MCRegisterClass & AGRP32 = MRI -> getRegClass ( <STR_LIT> ) ; for ( unsigned I = <NUM_LIT> , E = Inst . getNumOperands ( ) ; I != E ; ++ I ) { const MCOperand & Op = Inst . getOperand ( I ) ; if ( ! Op . isReg ( ) ) continue ; unsigned Sub = MRI -> getSubReg ( Op . getReg ( ) , <STR_LIT> ) ; if ( ! Sub ) continue ; if ( VGRP32 . contains ( Sub ) && ( ( Sub - <STR_LIT> ) & <NUM_LIT> ) ) return false ; if ( AGRP32 . contains ( Sub ) && ( ( Sub - <STR_LIT> ) &


<s> __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT>


<s> std :: vector < std :: string > mov_x1


<s> if ( x == pic_offset_table_rtx ) return true ; if ( ! HARD_REGISTER_P ( pic_offset_table_rtx ) && ( HARD_REGISTER_P ( x ) || lra_in_progress || reload_in_progress ) && ORIGINAL_REGNO ( x

) == REGNO ( pic_offset_table_rtx ) ) return true ;


<s> static <ISA_LIT>Operand CreateReg ( unsigned RegNo ) { <ISA_LIT>Operand Res ; Res . Kind = Register


<s> int64_t Imm ; <ISA_LIT>MCExpr :: VariantKind VK = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ; if ( ! isImm ( ) ) return false ; if ( ! evaluateConstantImm ( getImm ( ) , Imm , VK ) || VK != <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ) return false ; return ( isRV64 ( ) && isUInt < <NUM_LIT> > ( Imm ) ) || isUInt <


<s> static const uint16_t * lookupAVX512 ( unsigned opcode , unsigned domain ) { for ( const uint16_t ( & Row ) [ <NUM_LIT> ] : ReplaceableInstrsAVX512 ) if ( Row [ domain - <NUM_LIT> ] == opcode || ( domain == <NUM_LIT>

&& Row [ <NUM_LIT> ] == opcode ) ) return Row ;


<s> bool BlackfinFrameInfo :: hasFP ( const MachineFunction & MF ) const { const MachineFrameInfo * MFI = MF . getFrameInfo (


<s> int nregs ; if ( ! cum -> caller && cfun -> machine -> func_type != TYPE_NORMAL ) return ; if ( mode == BLKmode ) bytes = int_size_in_bytes ( type ) ; else bytes = GET_MODE_SIZE ( mode ) ; words = CEIL ( bytes , UNITS_PER_WORD ) ; if ( type ) mode = type_natural_mode ( type , NULL , false ) ; if ( TARGET_64BIT ) { enum calling_abi call_abi = cum ? cum -> call_abi : ix86_abi ; if ( call_abi == MS_ABI ) nregs = function_arg_advance_ms_64 ( cum , bytes


<s> unsigned Rd = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned Rm = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned Rn = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned pred = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; if ( pred == <NUM_LIT> ) return DecodeCPSInstruction ( Inst , Insn , Address , Decoder ) ; if ( ! Check ( S , DecodeGPRnopcRegisterClass ( Inst , Rd , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeGPRnopcRegisterClass ( Inst , Rm , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeGPRnopcRegisterClass ( Inst , Rn , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodePredicateOperand ( Inst , pred , Address , Decoder


<s> void <ISA_LIT>TargetLowering :: ReplaceNodeResults ( SDNode * N , SmallVectorImpl < SDValue > & Results , SelectionDAG & DAG ) const { SDValue Res ; switch ( N -> getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : ExpandREAD_REGISTER ( N , Results , DAG ) ; break ; case <STR_LIT> : Res = ExpandBITCAST ( N , DAG , Subtarget ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Res = Expand64BitShift ( N , DAG , Subtarget ) ; break ; case <STR_LIT> : case <STR_LIT> : Res = LowerREM ( N , DAG ) ; break ; case <STR_LIT> : case <STR_LIT> : Res = LowerDivRem ( SDValue ( N , <NUM_LIT> ) , DAG ) ; assert ( Res . getNumOperands ( ) == <NUM_LIT> && <STR_LIT> ) ; Results . push_back ( Res . getValue ( <NUM_LIT> ) ) ; Results . push_back ( Res . getValue ( <NUM_LIT> ) ) ; return ; case <STR_LIT> : case <STR_LIT>


<s> if ( ! Addr . hasOneUse ( ) ) { unsigned Opcode = Addr . getOpcode ( ) ; if ( Opcode != <STR_LIT> && Opcode != <STR_LIT> ) { for ( SDNode :: use_iterator UI = Addr . getNode ( ) -> use_begin ( ) , UE = Addr . getNode ( ) -> use_end ( ) ; UI != UE ; ++ UI ) { if ( UI -> getOpcode ( ) == <STR_LIT> ) { MatchAddressBase ( Addr , AM12 ) ; Done = true ; break ; } } } } if ( ! Done && MatchAddress ( Addr , AM12


<s> const SDep & Dep = SUI -> Preds [ i ] ; if ( Dep . getKind ( ) == SDep :: Data ) { int nopsNeeded = Dep . getLatency ( ) - ( PacketNum - Dep . getSUnit ( ) -> TopReadyCycle ) ; if ( nopsNeeded > <NUM_LIT> ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << I


<s> return ( GET_CODE ( disp ) == UNSPEC && XINT ( disp , <NUM_LIT>


<s> static unsigned int frv_hard_regno_nregs ( unsigned int regno , machine_mode mode ) { if ( ACCG_P ( regno ) ) return GET_MODE_SIZE ( mode


<s> unsigned MaxCallFrameSize = MF . getFrameInfo ( ) . getMaxCallFrameSize ( ) ; for ( MachineFunction :: iterator MBB = MF . begin ( ) , E = MF . end ( ) ; MBB != E ; ++ MBB ) { MachineBasicBlock :: iterator MBBI = MBB -> begin ( ) ; while ( MBBI != MBB -> end ( ) ) { MachineInstr & MI = * MBBI ++ ; if ( MI . getOpcode ( ) == <STR_LIT> ) { DebugLoc DL = MI . getDebugLoc ( ) ; Register Dst = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register Src = MI . getOperand ( <NUM_LIT> ) .


<s> std :: string getStringImm ( const MachineInstr


<s> bool isEntryFunctionCC ( CallingConv ::


<s> case PROCESSOR_BDVER3 : case PROCESSOR_BDVER4 : return <NUM_LIT> ; case PROCESSOR_CORE2 : case PROCESSOR_NEHALEM : case PROCESSOR_SANDYBRIDGE : case PROCESSOR_HASWELL : case PROCESSOR_BONNELL : case PROCESSOR_SILVERMONT : case


<s> assert ( OffsetImmOp . isImm ( ) && <STR_LIT> ) ; <ISA_LIT>TargetStreamer & TOut = getTargetStreamer ( ) ; unsigned DstReg = DstRegOp . getReg ( ) ; unsigned SrcReg = SrcRegOp . getReg ( ) ; int64_t OffsetValue = OffsetImmOp . getImm ( ) ; warnIfNoMacro ( IDLoc ) ; unsigned ATReg = getATReg ( IDLoc ) ; if ( ! ATReg ) return true ; bool IsLargeOffset = ! ( isInt < <NUM_LIT> > ( OffsetValue + <NUM_LIT> ) && isInt < <NUM_LIT> > ( OffsetValue ) ) ; if ( IsLargeOffset ) { if ( loadImmediate ( OffsetValue , ATReg , SrcReg , ! ABI . ArePtrs64bit ( ) , true , IDLoc , Out , STI ) ) return true ; } int64_t FirstOffset = IsLargeOffset ? <NUM_LIT> : OffsetValue ; int64_t SecondOffset = IsLargeOffset ? <NUM_LIT> : ( OffsetValue + <NUM_LIT> ) ; if ( isLittle ( ) ) std :: swap ( FirstOffset , SecondOffset ) ; unsigned FirstLbuDstReg = IsLargeOffset ? DstReg : ATReg ; unsigned SecondLbuDstReg = IsLargeOffset ? ATReg : DstReg ; unsigned LbuSrcReg = IsLargeOffset ? ATReg


<s> if ( Token . is ( AsmToken :: Identifier ) ) { if ( searchSymbolAlias ( Operands ) ) return MatchOperand_Success ; } DEBUG ( dbgs ( ) << <STR_LIT> ) ; return MatchOperand_NoMatch ; } DEBUG ( dbgs ( ) << <STR_LIT> ) ; OperandMatchResultTy ResTy = matchAnyRegisterWithoutDollar ( Operands , S ) ; if ( ResTy == MatchOperand_Success ) { Parser . Lex ( ) ; Parser . Lex ( ) ; } return


<s> return <STR_LIT> ( <STR_LIT> , <STR_LIT> , <STR_LIT> , & MI . getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ( <STR_LIT> , MI . getOperand ( <NUM_LIT> ) . getImm ( ) , MI . getOperand ( <NUM_LIT> ) . getImm ( ) , & MI . getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ( <STR_LIT> , <STR_LIT> , <STR_LIT> , & MI . getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : return <STR_LIT> ( <STR_LIT> , <STR_LIT> , <STR_LIT> , & MI . getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ( <STR_LIT> , <STR_LIT> , MI . getOperand ( <NUM_LIT> ) . getImm ( ) , & MI . getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ( <STR_LIT> , <STR_LIT> , MI . getOperand ( <NUM_LIT> ) . getImm ( ) , & MI . getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ( <STR_LIT> , <STR_LIT> , MI . getOperand ( <NUM_LIT> ) . getImm ( ) , & MI . getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ( <STR_LIT> , <STR_LIT> , MI . getOperand ( <NUM_LIT> ) . getImm ( ) , & MI .


<s> TargetRegistry :: RegisterMCDisassembler ( getThe<ISA_LIT>Target32 ( )


<s> if ( VT != <STR_LIT> && VT != <STR_LIT> && VT != <STR_LIT> ) return SDValue ( ) ; auto commuteSHUFP = [ & VT , & DL , & DAG ] ( SDValue Parent , SDValue V ) { if ( V . getOpcode ( ) != <STR_LIT> || ! Parent -> isOnlyUserOf ( V . getNode ( ) ) ) return SDValue ( ) ; SDValue N0 = V . getOperand ( <NUM_LIT> ) ; SDValue N1 = V . getOperand ( <NUM_LIT> ) ; unsigned Imm = V . getConstantOperandVal ( <NUM_LIT> ) ; const <ISA_LIT>Subtarget & Subtarget = DAG . getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( ! <STR_LIT> ( peekThroughOneUseBitcasts ( N0 ) , Subtarget ) || <STR_LIT> ( peekThroughOneUseBitcasts ( N1 ) , Subtarget ) ) return SDValue ( ) ; Imm = ( ( Imm & <NUM_LIT> ) << <NUM_LIT> ) | ( ( Imm & <NUM_LIT> ) >> <NUM_LIT> ) ; return DAG . getNode ( <STR_LIT> , DL , VT , N1 , N0 , DAG . getTargetConstant ( Imm , DL , <STR_LIT> ) ) ; } ; switch ( N . getOpcode ( ) ) { case <STR_LIT> : if ( SDValue NewSHUFP = commuteSHUFP ( N , N . getOperand ( <NUM_LIT> ) ) ) { unsigned Imm = N . getConstantOperandVal ( <NUM_LIT> ) ; return DAG . getNode ( <STR_LIT> , DL , VT , NewSHUFP , DAG . getTargetConstant ( Imm ^ <NUM_LIT> , DL , <STR_LIT> ) ) ; } break ; case <STR_LIT> : { SDValue N0 = N . getOperand ( <NUM_LIT> ) ; SDValue N1 = N . getOperand ( <NUM_LIT> ) ; unsigned Imm = N . getConstantOperandVal ( <NUM_LIT> ) ; if ( N0 == N1 ) { if ( SDValue NewSHUFP = commuteSHUFP ( N , N0 ) ) return DAG . getNode ( <STR_LIT> , DL , VT , NewSHUFP , NewSHUFP , DAG . getTargetConstant ( Imm ^ <NUM_LIT> , DL , <STR_LIT> ) ) ; } else if ( SDValue NewSHUFP = commuteSHUFP ( N , N0 ) ) { return DAG . getNode ( <STR_LIT> , DL , VT , NewSHUFP , N1 , DAG


<s> NumBytes = CCInfo . getNextStackOffset ( ) ; unsigned AdjStackDown = TII . getCallFrameSetupOpcode ( ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( AdjStackDown ) ) . addImm ( NumBytes ) ) ; for ( unsigned i = <NUM_LIT> , e = ArgLocs . size ( ) ; i != e ; ++ i ) { CCValAssign & VA = ArgLocs [ i ] ; unsigned Arg = ArgRegs [ VA . getValNo ( ) ] ; MVT ArgVT = ArgVTs [ VA . getValNo ( ) ] ; assert ( ( ! ArgVT . isVector ( ) && ArgVT . getSizeInBits ( ) <= <NUM_LIT> ) && <STR_LIT> ) ; switch ( VA . getLocInfo ( ) ) { case CCValAssign :: Full : break ; case CCValAssign :: SExt : { MVT DestVT = VA . getLocVT ( ) ; Arg = <ISA_LIT>EmitIntExt ( ArgVT , Arg , DestVT , false ) ; assert ( Arg != <NUM_LIT> && <STR_LIT> ) ; ArgVT = DestVT ; break ; } case CCValAssign :: AExt : case CCValAssign :: ZExt : { MVT DestVT = VA . getLocVT ( ) ; Arg = <ISA_LIT>EmitIntExt ( ArgVT , Arg , DestVT , true ) ; assert ( Arg != <NUM_LIT> && <STR_LIT> ) ; ArgVT = DestVT ; break ; } case CCValAssign :: BCvt : { unsigned BC = FastEmit_r ( ArgVT , VA . getLocVT ( ) , <STR_LIT> , Arg , false ) ; assert ( BC != <NUM_LIT> && <STR_LIT>


<s> if ( RegNo > <NUM_LIT> ) return MCDisassembler :: Fail ; unsigned Reg = I32RegDecoderTable [ RegNo ] ; Inst . addOperand ( MCOperand ::


<s> uint16_t KindA = A . Addr -> getKind ( ) , KindB = B . Addr -> getKind ( ) ; if ( KindA == NodeAttrs :: Use && KindB == NodeAttrs :: Def ) return true ; if ( KindA == NodeAttrs :: Def && KindB == NodeAttrs :: Use ) return false ; return A . Id < B . Id ; } ; std :: sort ( DRNs . begin ( ) , DRNs . end ( ) , UsesFirst ) ; if ( trace ( ) ) dbgs ( ) << <STR_LIT> ; for ( NodeAddr < RefNode * > RA : DRNs ) { if ( trace ( ) ) dbgs ( ) << <STR_LIT> << PrintNode < RefNode * > ( RA , DFG ) << '\n' ; if ( DFG . IsUse ( RA ) ) DFG . unlinkUse ( RA ) ; else if ( DFG . IsDef ( RA ) ) DFG . unlinkDef ( RA ) ; } for ( NodeAddr < InstrNode * > IA : DINs ) { NodeAddr < BlockNode * > BA = IA . Addr -> getOwner ( DFG ) ; BA . Addr -> removeMember ( IA , DFG ) ; if ( ! DFG . IsCode < NodeAttrs :: Stmt > ( IA ) ) continue ; MachineInstr * MI = NodeAddr < StmtNode * > (


<s> <ISA_LIT>ResourceModel ( const TargetSubtargetInfo & STI , const TargetSchedModel * SM ) : SchedModel ( SM ) , TotalPackets ( <NUM_LIT> ) { ResourcesModel = STI . getInstrInfo ( ) -> CreateTargetScheduleState ( STI ) ; assert ( ResourcesModel && <STR_LIT> ) ; Packet . resize ( SchedModel -> getIssueWidth ( ) ) ; Packet . clear ( ) ; OldPacket . resize ( SchedModel -> getIssueWidth ( ) ) ; OldPacket . clear ( ) ; ResourcesModel -> clearResources


<s> if ( Opcode == <STR_LIT> ) return { <STR_LIT> , <STR_LIT> , <STR_LIT> } ; llvm_unreachable ( <STR_LIT> ) ; } ( ) ; const bool IsSet = Opcode == <STR_LIT> || Opcode == <STR_LIT> ; for ( auto Op : Ops ) { int i = <NUM_LIT> ; auto MCIB = MCInstBuilder ( Op ) ; MCIB . addReg ( MI . getOperand ( i ++ ) . getReg ( ) ) ; MCIB . addReg ( MI . getOperand ( i ++ ) . getReg ( ) ) ; if ( ! IsSet ) MCIB . addReg ( MI . getOperand ( i ++ ) . getReg ( ) ) ; MCIB . addReg ( MI . getOperand ( i ++ ) . getReg ( ) ) ; MCIB . addReg ( MI . getOperand ( i ++ ) . getReg ( ) ) ; MCIB . addReg ( MI . getOperand ( i ++ ) . getReg ( ) ) ; EmitToStreamer ( OutStreamer , MCIB


<s> <ISA_LIT>Subtarget :: <ISA_LIT>Subtarget ( const Triple & TT , StringRef CPU , StringRef FS , const TargetMachine & TM ) : <ISA_LIT>GenSubtargetInfo ( TT , CPU , FS ) , CPUString ( <ISA_LIT>_MC :: select<ISA_LIT>CPU ( TT , CPU ) ) , InstrInfo ( initializeSubtargetDependencies ( CPU , FS ) ) , RegInfo ( getHwMode ( ) ) , TLInfo ( TM , * this ) , InstrItins ( getInstrItineraryForCPU ( CPUString ) ) { assert ( InstrItins . Itineraries !=


<s> count ++ ; } stack_bytes += count * <NUM_LIT> ; if ( ( ! TARGET_DISABLE_CALLT ) && ( use_callt || stack_bytes == <NUM_LIT> ) ) { if ( use_callt ) { sprintf ( buff , <STR_LIT> , ( mask & ( <NUM_LIT> << <NUM_LIT> ) ) ? <NUM_LIT> : <NUM_LIT> ) ; return buff ; } for ( i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) if ( mask & ( <NUM_LIT> << i ) ) break ; if ( i == <NUM_LIT> ) sprintf ( buff , <STR_LIT> ) ; else sprintf ( buff , <STR_LIT> , i , ( mask & ( <NUM_LIT> << <NUM_LIT> ) ) ? <STR_LIT> : <STR_LIT> ) ; } else { static char regs [ <NUM_LIT> ] ; int done_one ; regs [ <NUM_LIT> ] = <NUM_LIT> ; done_one = <NUM_LIT> ; for ( i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) { if ( mask & ( <NUM_LIT> << i ) ) { int first ; if ( done_one ) strcat


<s> SDValue Op0 = Op . getOperand ( <NUM_LIT> ) ; if ( Subtarget . hasVPOPCNTDQ ( ) ) { unsigned NumElems = VT . getVectorNumElements ( ) ; assert ( ( VT . getVectorElementType ( ) == <STR_LIT> || VT . getVectorElementType ( ) == <STR_LIT> ) && <STR_LIT> ) ; if ( NumElems < <NUM_LIT> || ( NumElems == <NUM_LIT> && Subtarget . canExtendTo512DQ ( ) ) ) { MVT NewVT = <STR_LIT> ( <STR_LIT> , NumElems ) ; Op = DAG . getNode ( <STR_LIT> , DL , NewVT , Op0 ) ; Op = DAG . getNode ( <STR_LIT> , DL , NewVT , Op ) ; return DAG . getNode ( <STR_LIT> , DL , VT , Op ) ; } } if ( VT . is256BitVector ( ) && ! Subtarget . hasInt256 ( ) ) return Lower256IntUnary ( Op , DAG ) ; if ( VT . is512BitVector ( ) && ! Subtarget . hasBWI ( ) ) return Lower512IntUnary ( Op , DAG ) ; if ( VT . getScalarType ( ) != <STR_LIT> ) { MVT ByteVT = <STR_LIT> ( <STR_LIT> , VT . getSizeInBits ( ) / <NUM_LIT> ) ; SDValue ByteOp = DAG . getBitcast ( ByteVT , Op0 ) ; SDValue PopCnt8 = DAG . getNode ( <STR_LIT> , DL , ByteVT , ByteOp ) ; return LowerHorizontalByteSum ( PopCnt8 , VT , Subtarget , DAG ) ; } if ( ! Subtarget . hasSSSE3 (


<s> MCStreamer * create<ISA_LIT>AsmStreamer ( MCContext & Context , formatted_raw_ostream & OS , bool isVerboseAsm , bool useLoc , bool useCFI

, bool useDwarfDirectory , MCInstPrinter * IP , MCCodeEmitter * CE , MCAsmBackend * MAB , bool ShowInst ) {


<s> assert ( Subtarget -> useMovt ( DAG . getMachineFunction ( ) ) && <STR_LIT> ) ; const GlobalValue * GV = cast < GlobalAddressSDNode > ( Op ) -> getGlobal ( ) ; const <STR_LIT> TargetFlags = ( GV -> hasDLLImportStorageClass ( ) ? <STR_LIT> : <STR_LIT> ) ; EVT PtrVT = getPointerTy ( DAG .


__v2di ) _mm_setzero_si128 ( ) , ( __mmask8 ) - <NUM_LIT> ) ;


<s> if ( ! crtl -> is_leaf ) if ( r == LP_REGNO || IVC2_ISAVED_REG ( r ) ) return true ; if ( ! crtl -> is_leaf || cfun -> machine -> doloop_tags > <NUM_LIT> ) if ( r == RPB_REGNO || r == RPE_REGNO || r == RPC_REGNO ) return true ; if ( crtl -> is_leaf && call_used_regs [ r ] && ! df_regs_ever_live_p ( r ) ) return false ; if ( call_used_regs [ r ] && ! fixed_regs [ r ] )


<s> __builtin_aarch64_simd_xi __o ; __o = __builtin_aarch64_ld4rv8hi ( ( const __builtin_aarch64_simd_hi * ) __a ) ; ret . val [ <NUM_LIT> ] = ( int16x8_t ) __builtin_aarch64_get_qregxiv8hi ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( int16x8_t ) __builtin_aarch64_get_qregxiv8hi ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( int16x8_t ) __builtin_aarch64_get_qregxiv8hi ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( int16x8_t ) __builtin_aarch64_get_qregxiv8hi ( __o , <NUM_LIT> ) ; return


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : DecodeGPR32RegisterClass ( Inst , Rs , Addr , Decoder ) ; LLVM_FALLTHROUGH ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : DecodeGPR32RegisterClass ( Inst , Rt , Addr , Decoder ) ; break ; case <STR_LIT> : case <STR_LIT> : DecodeGPR32RegisterClass ( Inst , Rs , Addr , Decoder ) ; LLVM_FALLTHROUGH ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : DecodeGPR64RegisterClass ( Inst , Rt , Addr , Decoder ) ; break ; case <STR_LIT> : case <STR_LIT> : DecodeGPR32RegisterClass ( Inst , Rs , Addr , Decoder ) ; LLVM_FALLTHROUGH ; case <STR_LIT>