<s> SDLoc dl ( N ) ; SDValue N0 = N -> getOperand ( <NUM_LIT> ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( N0 . getOpcode ( ) == <STR_LIT> && N0 . hasOneUse ( ) && N0 . getOperand ( <NUM_LIT> ) . hasOneUse ( ) ) { SDValue N00 = N0 . getOperand ( <NUM_LIT> ) ; if ( N00 . getOpcode ( ) == <STR_LIT> ) { if ( ! isOneConstant ( N0 . getOperand ( <NUM_LIT> ) ) ) return SDValue ( ) ; return DAG . getNode ( <STR_LIT> , dl , VT , DAG . getNode ( <STR_LIT> , dl , VT , N00 . getOperand ( <NUM_LIT> ) , N00 . getOperand ( <NUM_LIT> ) ) , DAG . getConstant ( <NUM_LIT> , dl , VT ) ) ; } } if ( N0 . getOpcode ( ) == <STR_LIT> && N0 . hasOneUse ( ) && N0 . getOperand ( <NUM_LIT> ) . hasOneUse ( ) ) { SDValue N00 = N0 . getOperand ( <NUM_LIT> ) ; if ( N00 . getOpcode ( ) == <STR_LIT> ) { return DAG . getNode ( <STR_LIT> , dl , VT , DAG . getNode ( <STR_LIT> , dl , VT , N00 . getOperand ( <NUM_LIT> ) , N00 . getOperand ( <NUM_LIT> ) ) , DAG . getConstant ( <NUM_LIT> , dl , VT ) ) ; } } if ( VT . is256BitVector ( ) ) if ( SDValue R = WidenMaskArithmetic ( N , DAG , DCI , Subtarget ) ) return R ; if ( N0 . getOpcode ( ) == <STR_LIT> && N0 . getResNo ( ) == <NUM_LIT> && N0 . getValueType ( ) == <STR_LIT> &&

( VT == <STR_LIT> || VT == <STR_LIT> ) ) {


<s> if ( REG_P ( dest ) || SUBREG_P ( dest ) ) { int d_regno = regno_or_subregno ( dest ) ; rtx scalar1 = operands [ <NUM_LIT> ] ; rtx scalar2 = operands [ <NUM_LIT> ] ; rtx scalar3 = operands [ <NUM_LIT> ] ; rtx scalar4 = operands [ <NUM_LIT> ] ; rtx tmp1 = operands


<s> break ; } if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rn , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecoderGPRRegisterClass ( Inst , Rm , Address , Decoder ) ) ) return MCDisassembler :: Fail ; Inst . addOperand ( MCOperand :: createImm ( imm ) ) ; return S


<s> bool iss10_6Imm ( ) const { return CheckImmRange ( <NUM_LIT> , <NUM_LIT> , true ,


<s> return ( __a + ( __b * __aarch64_vget_lane_any


<s> Data16bitsDirective = <STR_LIT> ; Data32bitsDirective = <STR_LIT> ; Data64bitsDirective = <STR_LIT> ; CommentString = <STR_LIT> ; ZeroDirective = <STR_LIT> ; GPRel32Directive = <STR_LIT> ; GPRel64Directive = <STR_LIT> ; DTPRel32Directive = <STR_LIT> ; DTPRel64Directive = <STR_LIT> ; TPRel32Directive = <STR_LIT> ; TPRel64Directive = <STR_LIT> ; UseAssignmentForEHBegin = true ; SupportsDebugInformation = true ; ExceptionsType = ExceptionHandling :: DwarfCFI ; DwarfRegNumForCFI = true ; Has<ISA_LIT>Expressions = true ; if ( TheTriple . isMIPS32 ( ) )


<s> virtual const <ISA_LIT>Subtarget * getSubtargetImpl (


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ( MI -> getNumOperands ( ) - MI -> getDesc ( ) . getNumOperands ( ) + <NUM_LIT> ) * <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : return ( MI -> getNumOperands ( ) - MI -> getDesc ( ) . getNumOperands (


<s> set<ISA_LIT>16LibcallName ( RTLIB :: OEQ_F64 , <STR_LIT> ) ; set<ISA_LIT>16LibcallName ( RTLIB :: UNE_F32 , <STR_LIT> ) ; set<ISA_LIT>16LibcallName ( RTLIB :: UNE_F64 , <STR_LIT> ) ; set<ISA_LIT>16LibcallName ( RTLIB :: OGE_F32 , <STR_LIT> ) ; set<ISA_LIT>16LibcallName ( RTLIB :: OGE_F64 , <STR_LIT> ) ; set<ISA_LIT>16LibcallName ( RTLIB :: OLT_F32 , <STR_LIT> ) ; set<ISA_LIT>16LibcallName ( RTLIB :: OLT_F64 , <STR_LIT> ) ; set<ISA_LIT>16LibcallName ( RTLIB :: OLE_F32 , <STR_LIT> ) ; set<ISA_LIT>16LibcallName ( RTLIB :: OLE_F64 , <STR_LIT> ) ; set<ISA_LIT>16LibcallName ( RTLIB :: OGT_F32 , <STR_LIT> ) ; set<ISA_LIT>16LibcallName ( RTLIB :: OGT_F64 , <STR_LIT> ) ; set<ISA_LIT>16LibcallName ( RTLIB :: UO_F32 , <STR_LIT> ) ; set<ISA_LIT>16LibcallName ( RTLIB :: UO_F64 , <STR_LIT> ) ; set<ISA_LIT>16LibcallName ( RTLIB :: O_F32 , <STR_LIT> )


<s> return getSTI ( ) . getFeatureBits ( )


<s> bool <ISA_LIT>InstrInfo :: isZeroImm ( const MachineOperand & op ) const { return op . isImm ( ) && op . getImm ( )


<s> static bool nios2_rtx_costs ( rtx x , int code , int outer_code ATTRIBUTE_UNUSED , int opno ATTRIBUTE_UNUSED , int * total , bool speed ATTRIBUTE_UNUSED ) { switch ( code ) { case CONST_INT : if ( INTVAL ( x ) == <NUM_LIT> ) { * total = COSTS_N_INSNS ( <NUM_LIT> ) ; return true ; } else if ( nios2_simple_const_p ( x ) ) { * total = COSTS_N_INSNS ( <NUM_LIT> ) ; return true ; } else { * total = COSTS_N_INSNS ( <NUM_LIT> ) ; return true ; } case LABEL_REF : case SYMBOL_REF : case CONST : case CONST_DOUBLE : { * total = COSTS_N_INSNS ( <NUM_LIT> ) ; return true ; } case


<s> EVT VT = N -> getValueType ( <NUM_LIT> ) ; SDValue Op0 = N -> getOperand ( <NUM_LIT> ) ; SDValue Op1 = N -> getOperand ( <NUM_LIT> ) ; if ( ( ( Subtarget -> hasSSSE3 ( ) && ( VT == <STR_LIT> || VT == <STR_LIT> ) ) || ( Subtarget -> hasInt256 ( ) && ( VT == <STR_LIT> || VT == <STR_LIT> ) ) ) && isHorizontalBinOp (

Op0 , Op1 , true ) ) return DAG . getNode ( <STR_LIT> , N -> getDebugLoc ( ) , VT , Op0 , Op1 ) ;


<s> MVT VT = Subtarget . isGP64bit ( ) ? <STR_LIT> : <STR_LIT> ; SDValue Lo = Op . getOperand ( <NUM_LIT> ) , Hi = Op . getOperand ( <NUM_LIT> ) ; SDValue Shamt = Op . getOperand ( <NUM_LIT> ) ; SDValue Not = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Shamt , DAG . getConstant ( - <NUM_LIT> , <STR_LIT> ) ) ; SDValue ShiftRight1Lo = DAG . getNode ( <STR_LIT> , DL , VT , Lo , DAG . getConstant ( <NUM_LIT> , VT ) ) ; SDValue ShiftRightLo = DAG . getNode ( <STR_LIT> , DL , VT , ShiftRight1Lo , Not ) ; SDValue ShiftLeftHi = DAG . getNode ( <STR_LIT> , DL ,


<s> if ( Subtarget -> isTargetMachO ( ) && TM . getCodeModel ( ) == CodeModel :: Large ) { unsigned Opc1 = Is64Bit ? <STR_LIT> : <STR_LIT> ; const TargetRegisterClass * RC = Is64Bit ? & <STR_LIT> : & <STR_LIT> ; unsigned TmpReg = createResultReg ( RC ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc1 ) , TmpReg ) . addImm ( CFP -> getValueAPF ( ) . bitcastToAPInt ( ) . getZExtValue ( ) ) ; unsigned ResultReg = createResultReg ( TLI . getRegClassFor ( VT ) ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: COPY ) , ResultReg ) . addReg ( TmpReg , getKillRegState ( true ) ) ; return ResultReg ; } unsigned Align = DL . getPrefTypeAlignment ( CFP -> getType ( ) ) ; if ( Align == <NUM_LIT> ) Align = DL . getTypeAllocSize ( CFP -> getType ( ) ) ; unsigned CPI = MCP . getConstantPoolIndex ( cast < Constant > ( CFP ) , Align ) ; unsigned ADRPReg = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , ADRPReg ) . addConstantPoolIndex ( CPI , <NUM_LIT> , <STR_LIT> ) ; unsigned Opc = Is64Bit ?


<s> void <ISA_LIT>LowerArgs :: handleByValParam ( Argument * Arg ) { Function * Func = Arg -> getParent ( ) ; Instruction * FirstInst = & ( Func -> getEntryBlock ( ) . front ( ) ) ; PointerType * PType = dyn_cast < PointerType > ( Arg -> getType ( ) ) ; assert ( PType && <STR_LIT> ) ; Type * StructType = PType -> getElementType ( ) ; unsigned AS = Func -> getParent ( ) -> getDataLayout ( ) . getAllocaAddrSpace ( ) ; AllocaInst * AllocA = new AllocaInst ( StructType , AS , Arg -> getName ( ) , FirstInst ) ; AllocA -> setAlignment ( Func -> getParamAlignment ( Arg -> getArgNo ( ) + <NUM_LIT> ) ) ; Arg -> replaceAllUsesWith ( AllocA ) ; Value * ArgInParam = new AddrSpaceCastInst ( Arg , PointerType :: get ( StructType , ADDRESS_SPACE_PARAM ) , Arg -> getName ( ) , FirstInst ) ; LoadInst * LI = new LoadInst ( ArgInParam , Arg -> getName ( ) ,


<s> const TargetRegisterClass * <ISA_LIT>InstrInfo :: getOpRegClass ( const MachineInstr & MI , unsigned OpNo ) const { const MachineRegisterInfo & MRI = MI . getParent ( ) -> getParent ( ) -> getRegInfo ( ) ; const MCInstrDesc & Desc = get ( MI . getOpcode ( ) ) ; if ( MI . isVariadic ( ) || OpNo >= Desc . getNumOperands ( ) || Desc . OpInfo [ OpNo ] . RegClass == - <NUM_LIT> ) { Register Reg = MI . getOperand ( OpNo ) . getReg ( ) ; if ( Reg . isVirtual ( ) ) return MRI . getRegClass ( Reg ) ; return RI . getPhysRegClass ( Reg ) ; } unsigned RCID = Desc . OpInfo [ OpNo ] . RegClass ; RCID = adjustAllocatableRegClass ( ST , MRI


<s> const <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; if ( ! MF . getTarget ( ) . Options . RealignStack ) return false ; if ( AFI -> isThumb1OnlyFunction ( ) ) return false ; if ( ! MRI -> canReserveReg ( FramePtr ) )


<s> Opnds [ <NUM_LIT> ] = N ; return DAG . getNode ( <STR_LIT> , DL , OutVT , Opnds ) ; } ; if ( VT . getSizeInBits ( ) < <NUM_LIT> && ! ( <NUM_LIT> % VT . getSizeInBits ( ) ) && ( SVT == <STR_LIT> || SVT == <STR_LIT> || SVT == <STR_LIT> ) && ( InSVT == <STR_LIT> || InSVT == <STR_LIT> || InSVT == <STR_LIT> ) ) { unsigned Scale = <NUM_LIT> / VT . getSizeInBits ( ) ; EVT ExVT = EVT :: getVectorVT ( * DAG . getContext ( ) , SVT , <NUM_LIT> / SVT . getSizeInBits ( ) ) ; SDValue Ex = ExtendVecSize ( DL , N0 , Scale * InVT . getSizeInBits ( ) ) ; SDValue SExt = DAG . getNode ( <STR_LIT> , DL , ExVT , Ex ) ; return DAG . getNode ( <STR_LIT> , DL , VT , SExt , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; } if ( VT . getSizeInBits ( ) == <NUM_LIT> && ( SVT == <STR_LIT> || SVT == <STR_LIT> || SVT == <STR_LIT> ) && ( InSVT == <STR_LIT> || InSVT == <STR_LIT> || InSVT == <STR_LIT> ) ) { SDValue ExOp = ExtendVecSize ( DL , N0 , <NUM_LIT> ) ; return DAG . getSignExtendVectorInReg ( ExOp , DL , VT ) ; } if ( ! Subtarget -> hasInt256 ( ) && ! ( VT . getSizeInBits ( ) % <NUM_LIT> ) && ( SVT == <STR_LIT> || SVT == <STR_LIT> || SVT == <STR_LIT> ) && ( InSVT == <STR_LIT> || InSVT == <STR_LIT> || InSVT == <STR_LIT> ) ) { unsigned NumVecs = VT . getSizeInBits ( ) / <NUM_LIT> ; unsigned NumSubElts = <NUM_LIT> / SVT . getSizeInBits ( ) ; EVT SubVT = EVT :: getVectorVT ( * DAG . getContext ( ) , SVT , NumSubElts ) ; EVT InSubVT = EVT :: getVectorVT ( * DAG . getContext ( ) , InSVT , NumSubElts ) ; SmallVector < SDValue , <NUM_LIT> > Opnds ; for ( unsigned i = <NUM_LIT> , Offset = <NUM_LIT> ; i


<s> if ( CostKind == TTI :: TCK_RecipThroughput && ( ST -> hasNEON ( ) || ST -> hasMVEIntegerOps ( ) ) ) { return <NUM_LIT> ; } return BaseT :: getCFInstrCost ( Opcode , CostKind


<s> static __inline qword si_lqd ( qword a , unsigned int imm ) { return ( ( qword ) ( vec_ld ( si_to_uint ( a ) & ~ <NUM_LIT> , ( vector unsigned char * )


<s> if ( Op . isImm ( ) ) { O << <STR_LIT> ; O . write_hex ( ( unsigned short ) Op . getImm ( ) ) ; return ; } assert ( Op . isExpr ( ) && <STR_LIT> ) ; printExpr ( Op . getExpr (


<s> if ( from == current_frame_info . reg_fp || from == current_frame_info . reg_save_b0 || from == current_frame_info . reg_save_pr || from == current_frame_info . reg_save_ar_pfs || from == current_frame_info . reg_save_ar_unat || from == current_frame_info . reg_save_ar_lc ) return <NUM_LIT> ; if ( OUT_REGNO_P ( to ) && to >= OUT_REG (


<s> if ( ( Count % MinNopLen ) != <NUM_LIT> ) return false ; for ( ; Count >= <NUM_LIT> ; Count -= <NUM_LIT>

) OS . write ( <STR_LIT> , <NUM_LIT> ) ;


<s> return isInt < <NUM_LIT> > ( Value ) || ( isUInt < <NUM_LIT> > ( Value ) &&

isInt < <NUM_LIT> > ( static_cast < int32_t > ( Value ) ) ) ;


<s> rtx this_arg = operands [ i ] ; rtx this_slot ; if ( GET_MODE ( this_arg ) == TFmode ) { int force_stack_temp ; force_stack_temp = <NUM_LIT> ; if ( TARGET_BUGGY_QP_LIB && i == <NUM_LIT> ) force_stack_temp = <NUM_LIT> ; if ( GET_CODE ( this_arg ) == MEM && ! force_stack_temp ) { tree expr = MEM_EXPR ( this_arg ) ; if ( expr ) mark_addressable ( expr ) ; this_arg = XEXP ( this_arg , <NUM_LIT> ) ; } else if ( CONSTANT_P ( this_arg ) && ! force_stack_temp ) { this_slot = force_const_mem ( TFmode , this_arg ) ; this_arg = XEXP ( this_slot , <NUM_LIT> ) ; } else { this_slot = assign_stack_temp ( TFmode , GET_MODE_SIZE ( TFmode ) ) ; if ( i > <NUM_LIT> ) emit_move_insn ( this_slot , this_arg ) ; else ret_slot = this_slot ; this_arg = XEXP ( this_slot , <NUM_LIT> ) ; } } arg [ i ] = this_arg ; } func_sym = gen_rtx_SYMBOL_REF ( Pmode , func_name ) ; if ( GET_MODE ( operands [


<s> rtx op00 , op02 , op10 , op12 ; op00 = msp430_subreg ( HImode , operands [ <NUM_LIT> ] , SImode , <NUM_LIT> ) ; op02 = msp430_subreg ( HImode , operands [ <NUM_LIT> ] , SImode , <NUM_LIT> ) ; if ( GET_CODE ( operands [ <NUM_LIT> ] ) == CONST || GET_CODE ( operands [ <NUM_LIT> ] ) == SYMBOL_REF ) { op10 = gen_rtx_ZERO_EXTRACT ( HImode , operands [ <NUM_LIT> ] , GEN_INT ( <NUM_LIT> ) , GEN_INT ( <NUM_LIT> ) ) ; op10 = gen_rtx_CONST ( HImode , op10 ) ; op12 = gen_rtx_ZERO_EXTRACT ( HImode , operands [ <NUM_LIT> ] , GEN_INT ( <NUM_LIT> ) , GEN_INT ( <NUM_LIT> ) ) ; op12 = gen_rtx_CONST ( HImode , op12 ) ; } else { op10 = msp430_subreg ( HImode , operands [ <NUM_LIT> ] , SImode , <NUM_LIT> ) ; op12 = msp430_subreg ( HImode , operands [ <NUM_LIT> ] , SImode , <NUM_LIT> ) ; } if ( rtx_equal_p ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ) { operands [ <NUM_LIT> ] = op02 ; operands [ <NUM_LIT> ] = op12 ; operands [ <NUM_LIT> ] = op00 ; operands [ <NUM_LIT> ] = op10 ; } else if ( rtx_equal_p ( op00 , op12 ) || ( REG_P ( op00 ) && reg_mentioned_p ( op00 , op10 ) ) || (


<s> if ( cost > maxPathCost ) { maxPathCost = cost ; indexPath = route . size ( ) - <NUM_LIT> ; setMaxPath ( route . at ( indexPath )


<s> else { opcode = <NUM_LIT> ; size = <NUM_LIT> ; } mem = adjust_address ( m_tramp , HImode , offset ) ; emit_move_insn ( mem , gen_int_mode ( opcode , HImode ) ) ; mem = adjust_address ( m_tramp , ptr_mode , offset + <NUM_LIT> ) ; emit_move_insn ( mem , chain_value ) ; offset += size ; mem = adjust_address ( m_tramp , SImode , offset ) ; emit_move_insn ( mem , gen_int_mode ( <NUM_LIT> , SImode ) ) ; offset += <NUM_LIT> ; } else { rtx disp , chain ; chain = ix86_static_chain ( fndecl , true ) ; if ( REG_P ( chain ) ) { switch ( REGNO ( chain ) ) { case AX_REG : opcode = <NUM_LIT> ; break ; case CX_REG : opcode = <NUM_LIT> ; break ; default : gcc_unreachable ( ) ; } } else opcode = <NUM_LIT> ; mem = adjust_address ( m_tramp , QImode , offset ) ; emit_move_insn ( mem , gen_int_mode ( opcode , QImode ) ) ; mem = adjust_address ( m_tramp , SImode , offset + <NUM_LIT> ) ; emit_move_insn ( mem


<s> bool hasReservedCallFrame ( const MachineFunction &


<s> <ISA_LIT>MemOpInfo ( AtomicOrdering Ordering = AtomicOrdering :: SequentiallyConsistent , <ISA_LIT>AtomicScope Scope = <STR_LIT> , <ISA_LIT>AtomicAddrSpace OrderingAddrSpace = <STR_LIT> , <ISA_LIT>AtomicAddrSpace InstrAddrSpace = <STR_LIT> , bool IsCrossAddressSpaceOrdering = true , AtomicOrdering FailureOrdering = AtomicOrdering :: SequentiallyConsistent , bool IsVolatile = false , bool IsNonTemporal = false ) : Ordering ( Ordering ) , FailureOrdering ( FailureOrdering ) , Scope ( Scope ) , OrderingAddrSpace ( OrderingAddrSpace ) , InstrAddrSpace ( InstrAddrSpace ) , IsCrossAddressSpaceOrdering ( IsCrossAddressSpaceOrdering ) , IsVolatile ( IsVolatile ) , IsNonTemporal ( IsNonTemporal ) { if ( ( OrderingAddrSpace == InstrAddrSpace ) && isPowerOf2_32 ( uint32_t ( InstrAddrSpace ) )

) this -> IsCrossAddressSpaceOrdering = false ;


<s> return static_cast < const <ISA_LIT>TargetMachine


<s> std :: swap ( Op0Opc , Op1Opc ) ; std :: swap ( TargetMask , InsertMask ) ; } } unsigned MB , ME ; if ( InsertMask && isRunOfOnes ( InsertMask , MB , ME ) ) { SDValue Tmp1 , Tmp2 ; if ( ( Op1Opc == <STR_LIT> || Op1Opc == <STR_LIT> ) && isInt32Immediate ( Op1 . getOperand ( <NUM_LIT> ) , Value ) ) { Op1 = Op1 . getOperand ( <NUM_LIT> ) ; SH = ( Op1Opc == <STR_LIT> ) ? Value : <NUM_LIT> - Value ; } if ( Op1Opc == <STR_LIT> ) { unsigned SHOpc = Op1 . getOperand ( <NUM_LIT> ) . getOpcode ( ) ; if ( ( SHOpc == <STR_LIT> || SHOpc == <STR_LIT> ) && isInt32Immediate ( Op1 . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) , Value ) ) { Op1 = Op1 . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ; SH = ( SHOpc == <STR_LIT> ) ?


<s> case <STR_LIT> : if ( ! useAM3 ) { needsLowering = ( ( Addr . Offset & <NUM_LIT> ) != Addr . Offset ) ; if ( needsLowering && isThumb2 ) needsLowering = ! ( Subtarget -> hasV6T2Ops ( ) && Addr . Offset < <NUM_LIT> && Addr . Offset > - <NUM_LIT> ) ; } else { needsLowering = ( Addr . Offset > <NUM_LIT> || Addr . Offset < - <NUM_LIT> ) ; } break ; case <STR_LIT> : case <STR_LIT> : needsLowering = ( ( Addr . Offset & <NUM_LIT> ) != Addr . Offset ) ; break ; } if ( needsLowering && Addr . BaseType == Address :: FrameIndexBase ) { const TargetRegisterClass * RC = isThumb2 ? ( const TargetRegisterClass * ) & <STR_LIT> : ( const TargetRegisterClass * ) & <STR_LIT> ; unsigned ResultReg = createResultReg ( RC ) ; unsigned Opc = isThumb2 ? <STR_LIT> : <STR_LIT> ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , ResultReg ) . addFrameIndex ( Addr . Base . FI ) . addImm ( <NUM_LIT> ) ) ; Addr . Base . Reg = ResultReg ; Addr . BaseType = Address


<s> unsigned long type = ARM_FT_UNKNOWN ; tree a ; tree attr ; gcc_assert ( TREE_CODE ( current_function_decl ) == FUNCTION_DECL ) ; if ( optimize > <NUM_LIT> && ( TREE_NOTHROW ( current_function_decl ) || ! ( flag_unwind_tables || ( flag_exceptions && arm_except_unwind_info ( & global_options ) != UI_SJLJ ) ) ) && TREE_THIS_VOLATILE ( current_function_decl ) ) type |= ARM_FT_VOLATILE ; if ( cfun -> static_chain_decl != NULL ) type |= ARM_FT_NESTED ; attr = DECL_ATTRIBUTES ( current_function_decl ) ; a = lookup_attribute ( <STR_LIT> , attr ) ; if ( a != NULL_TREE ) type |= ARM_FT_NAKED ; a = lookup_attribute ( <STR_LIT> , attr ) ; if ( a == NULL_TREE ) a =


<s> while ( isa < CastInst > ( V ) ) V = cast < CastInst > ( V ) -> getOperand ( <NUM_LIT> ) ; return V


<s> void <ISA_LIT>InstPrinter :: printClamp ( const MCInst * MI , unsigned OpNo , const MCSubtargetInfo & STI , raw_ostream & O ) { printIfSet ( MI , OpNo , O ,


<s> if ( ! SAddr || RI . isSGPRClass ( MRI . getRegClass ( SAddr -> getReg ( ) ) ) ) return ; if ( moveFlatAddrToVGPR ( MI


<s> default : if ( dbr_sequence_length ( ) == <NUM_LIT> || ( nullify && forward_branch_p ( insn ) ) ) { nullify = <NUM_LIT> ; xdelay = <NUM_LIT> ; operands [ <NUM_LIT> ] = GEN_INT ( length ) ; } else { xdelay = <NUM_LIT> ; operands [ <NUM_LIT> ] = GEN_INT ( length + <NUM_LIT> ) ; } if ( nullify ) output_asm_insn ( <STR_LIT> , operands ) ; else output_asm_insn ( <STR_LIT> , operands ) ; return pa_output_lbranch ( operands [ <NUM_LIT> ] , insn , xdelay ) ; } } else if ( which_alternative == <NUM_LIT> ) { output_asm_insn ( <STR_LIT> , operands ) ; if ( length == <NUM_LIT> ) return <STR_LIT> ; else if ( length == <NUM_LIT> ) return <STR_LIT> ; else { operands [ <NUM_LIT> ] = GEN_INT ( length - <NUM_LIT> ) ; output_asm_insn ( <STR_LIT> , operands ) ; output_asm_insn ( <STR_LIT> , operands ) ; return pa_output_lbranch ( operands [ <NUM_LIT> ] , insn , <NUM_LIT> ) ; } } else if ( which_alternative == <NUM_LIT> ) { if ( length == <NUM_LIT> ) return <STR_LIT> ; else if ( length == <NUM_LIT> ) return <STR_LIT> ; else { operands [ <NUM_LIT> ] = GEN_INT ( length ) ; output_asm_insn ( <STR_LIT> , operands ) ; return pa_output_lbranch ( operands [ <NUM_LIT> ] , insn , <NUM_LIT> ) ; } } else { if ( length == <NUM_LIT> ) return <STR_LIT> ; else if ( length == <NUM_LIT> ) return <STR_LIT> ; else { operands [ <NUM_LIT> ] = GEN_INT ( length


<s> if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; unsigned Opcode ; if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opcode = <STR_LIT> ; else llvm_unreachable ( <STR_LIT>


<s> unsigned CalleeCC = TheCall -> getCallingConv ( ) ; if ( CalleeCC == CallingConv :: Fast && CallerCC == CalleeCC ) { SDValue Callee = TheCall -> getCallee ( ) ; if ( getTargetMachine ( ) . getRelocationModel ( ) != Reloc :: PIC_ || !

Subtarget -> isPICStyleGOT ( ) || ! Subtarget -> is64Bit ( ) ) return true ;


<s> unsigned int <ISA_LIT>InstrInfo :: getTailDuplicateSize ( CodeGenOpt :: Level OptLevel ) const { return OptLevel >= CodeGenOpt ::


<s> if ( NumString . getAsInteger ( <NUM_LIT> , IntVal ) ) return MatchOperand_NoMatch ; unsigned Reg = matchRegisterByNumber ( IntVal , <STR_LIT> ) ; <ISA_LIT>Operand * Op = <STR_LIT> ( Reg , S , Parser . getTok ( ) . getLoc ( ) ) ; Op -> setRegKind ( <STR_LIT> ) ; Operands . push_back (


<s> else if ( isa < UndefValue > ( C ) ) { unsigned Opc = <NUM_LIT> ; switch ( VT . SimpleTy ) { default : break ; case <STR_LIT> : if ( ! <ISA_LIT>ScalarSSEf32 ) Opc = <STR_LIT> ; break ; case <STR_LIT> : if ( ! <ISA_LIT>ScalarSSEf64 ) Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; } if ( Opc ) { Register ResultReg = createResultReg ( TLI . getRegClassFor ( VT ) ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , ResultReg ) ; return ResultReg ; } } return <NUM_LIT>


<s> const auto * AddrReg = TII -> getNamedOperand ( * CI . I , <STR_LIT> :: addr ) ; const auto * Dest0 = TII -> getNamedOperand ( * CI . I , <STR_LIT> :: vdst ) ; const auto * Dest1 = TII -> getNamedOperand ( * CI . Paired , <STR_LIT> :: vdst ) ; unsigned NewOffset0 = CI . Offset0 ; unsigned NewOffset1 = CI . Offset1 ; unsigned Opc = CI . UseST64 ? read2ST64Opcode ( CI . EltSize ) : read2Opcode ( CI . EltSize ) ; unsigned SubRegIdx0 = ( CI . EltSize == <NUM_LIT> ) ? <STR_LIT> : <STR_LIT> ; unsigned SubRegIdx1 = ( CI . EltSize == <NUM_LIT> ) ? <STR_LIT> : <STR_LIT> ; if ( NewOffset0 > NewOffset1 ) { std :: swap ( NewOffset0 , NewOffset1 ) ; std :: swap ( SubRegIdx0 , SubRegIdx1 ) ; } assert ( ( isUInt < <NUM_LIT> > ( NewOffset0 ) && isUInt < <NUM_LIT> > ( NewOffset1 ) ) && ( NewOffset0 != NewOffset1 ) && <STR_LIT> ) ; const MCInstrDesc & Read2Desc = TII -> get ( Opc ) ; const TargetRegisterClass * SuperRC = ( CI . EltSize == <NUM_LIT> ) ?


<s> bool <ISA_LIT>CallLowering :: lowerFormalArguments ( MachineIRBuilder & MIRBuilder , const Function & F , ArrayRef

< ArrayRef < Register >> VRegs , FunctionLoweringInfo & FLI ) const {


<s> if ( <STR_LIT> :: getIsaVersion ( getFeatureBits ( ) ) . Major < <NUM_LIT> ) return true ; auto SymbolName = getGprCountSymbolName ( RegKind ) ; if ( ! SymbolName ) return true ; MCSymbol * Sym = getContext ( ) . getOrCreateSymbol ( * SymbolName ) ; int64_t NewMax = DwordRegIndex + RegWidth


<s> return RBI . getRegBank ( Reg , * MRI , TRI ) -> getID


<s> if ( Rs >= Rt ) { MI . setOpcode ( <STR_LIT> ) ; HasRs = true ; } else if ( Rs != <NUM_LIT> && Rs < Rt ) { MI . setOpcode ( <STR_LIT> ) ; HasRs = true ; } else MI . setOpcode ( <STR_LIT> ) ; if ( HasRs ) MI . addOperand ( MCOperand :: CreateReg ( getReg ( Decoder , <STR_LIT> , Rs ) ) ) ; MI . addOperand ( MCOperand :: CreateReg ( getReg ( Decoder , <STR_LIT> , Rt ) ) ) ; MI . addOperand ( MCOperand :: CreateImm ( Imm


<s> else if ( * Offset == <NUM_LIT> && * Width == <NUM_LIT> ) SrcSel = WORD_0 ; else if ( * Offset == <NUM_LIT> && * Width == <NUM_LIT> ) SrcSel = DWORD ; else if ( * Offset == <NUM_LIT> && * Width == <NUM_LIT> ) SrcSel = BYTE_1 ; else if ( * Offset == <NUM_LIT> && * Width == <NUM_LIT> ) SrcSel = BYTE_2 ; else if ( * Offset == <NUM_LIT> && * Width == <NUM_LIT> ) SrcSel = WORD_1 ; else if ( * Offset == <NUM_LIT> && * Width == <NUM_LIT> ) SrcSel = BYTE_3 ; else break ; MachineOperand * Src0 = TII -> getNamedOperand ( MI , <STR_LIT> :: src0 ) ; MachineOperand * Dst = TII -> getNamedOperand ( MI , <STR_LIT> :: vdst ) ; if ( TRI -> isPhysicalRegister ( Src0 -> getReg ( ) ) || TRI -> isPhysicalRegister ( Dst -> getReg ( ) ) ) break ; auto SDWASrc = make_unique < SDWASrcOperand > ( Src0 , Dst , SrcSel , false , false , Opcode == <STR_LIT> ? false : true ) ; DEBUG ( dbgs ( ) << <STR_LIT> << MI << <STR_LIT> << * SDWASrc << '\n' ) ; SDWAOperands [ & MI ] = std :: move ( SDWASrc ) ; ++ NumSDWAPatternsFound ; break ; } case <STR_LIT> : { MachineOperand * Src0 = TII -> getNamedOperand ( MI , <STR_LIT> :: src0 ) ; auto Imm = foldToImm ( * Src0 ) ; if ( ! Imm ) break ; if ( * Imm != <NUM_LIT> && * Imm != <NUM_LIT> ) break ; MachineOperand * Src1 = TII -> getNamedOperand ( MI , <STR_LIT> :: src1 ) ; MachineOperand * Dst = TII -> getNamedOperand ( MI , <STR_LIT> :: vdst ) ; if ( TRI -> isPhysicalRegister ( Src1 -> getReg ( ) ) || TRI -> isPhysicalRegister ( Dst -> getReg ( ) ) ) break ; auto SDWASrc = make_unique < SDWASrcOperand > ( Src1 , Dst , * Imm ==


<s> if ( N . getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> ) return false ; SDValue Mask = N . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ; if ( Mask . getOpcode ( ) != <STR_LIT> ) return false ; SplatVal = dyn_cast < ConstantSDNode > ( Mask . getOperand ( <NUM_LIT> ) ) ; if ( ! SplatVal ) return false ; if ( SplatVal -> getZExtValue ( )


<s> void <ISA_LIT>AnalyzeImmediate :: GetInstSeqLsADDiu ( uint64_t Imm , unsigned RemSize , InstSeqLs & SeqLs ) { GetInstSeqLs ( ( Imm + <NUM_LIT> ) & <NUM_LIT> , RemSize , SeqLs ) ; AddInstr ( SeqLs , Inst ( ADDiu ,


<s> return & InstrInfo . getRegisterInfo


<s> if ( ! Subtarget . isUsingPCRelativeCalls ( ) ) return SDValue ( ) ; SDValue LHS = N -> getOperand ( <NUM_LIT> ) ; SDValue RHS = N -> getOperand ( <NUM_LIT> ) ; if ( LHS . getOpcode ( ) != <STR_LIT> ) std :: swap ( LHS , RHS ) ; if ( LHS . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; GlobalAddressSDNode * GSDN = dyn_cast < GlobalAddressSDNode > ( LHS . getOperand ( <NUM_LIT>


<s> InstructionSelector :: ComplexRendererFns <ISA_LIT>InstructionSelector :: selectMUBUFScratchOffset ( MachineOperand & Root ) const { Register Reg = Root . getReg ( ) ; const <ISA_LIT>MachineFunctionInfo * Info = MF -> getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; const MachineInstr * Def = MRI -> getVRegDef ( Reg ) ; if ( Register WaveBase = getWaveAddress ( Def ) ) { return { { [ = ] ( MachineInstrBuilder & MIB ) { MIB . addReg ( Info -> getScratchRSrcReg ( ) ) ; } , [ = ] ( MachineInstrBuilder & MIB ) { MIB . addReg ( WaveBase ) ; } , [ = ] ( MachineInstrBuilder & MIB ) { MIB . addImm ( <NUM_LIT> ) ; } } } ; } int64_t Offset = <NUM_LIT> ; Register BasePtr ; if ( mi_match ( Reg , * MRI , m_GPtrAdd ( m_Reg ( BasePtr ) , m_Copy ( m_ICst ( Offset ) ) ) ) ) { if ( ! <ISA_LIT>InstrInfo :: isLegalMUBUFImmOffset ( Offset ) ) return { } ; const MachineInstr * BasePtrDef = MRI -> getVRegDef ( BasePtr ) ; Register WaveBase = getWaveAddress ( BasePtrDef ) ; if ( ! WaveBase ) return


<s> bool allowPositionIndependentMovt ( ) const { return isROPI ( ) ||


<s> void <ISA_LIT>UnifyDivergentExitNodes :: getAnalysisUsage ( AnalysisUsage & AU ) const { AU . addRequired < PostDominatorTreeWrapperPass > ( ) ; AU . addRequired < LegacyDivergenceAnalysis > ( ) ; AU . addPreserved < LegacyDivergenceAnalysis > ( ) ; AU . addPreservedID ( BreakCriticalEdgesID ) ; AU . addPreservedID ( LowerSwitchID ) ; FunctionPass :: getAnalysisUsage ( AU


<s> } if ( ExternalSymbolSDNode * S = dyn_cast < ExternalSymbolSDNode > ( Callee ) ) { unsigned char OpFlags = <NUM_LIT> ; if ( DAG . getTarget ( ) . getRelocationModel ( ) != Reloc :: Static && ( <ISA_LIT>SubTarget . getTargetTriple ( ) . isMacOSX ( ) && <ISA_LIT>SubTarget . getTargetTriple ( ) . isMacOSXVersionLT ( <NUM_LIT> , <NUM_LIT> ) ) ) { OpFlags = <STR_LIT> ; } Callee = DAG . getTargetExternalSymbol ( S -> getSymbol ( ) , Callee . getValueType ( ) , OpFlags ) ; needIndirectCall = false ; } if ( needIndirectCall ) { SDValue MTCTROps [ ] = { Chain , Callee , InFlag } ; if ( isSVR4ABI && is<ISA_LIT>64 ) { SDVTList VTs = DAG . getVTList ( <STR_LIT> , <STR_LIT> , <STR_LIT> ) ; SDValue LoadFuncPtr = DAG . getNode ( <STR_LIT> , dl , VTs , ArrayRef < SDValue > ( MTCTROps , InFlag . getNode ( ) ? <NUM_LIT> : <NUM_LIT> ) ) ; Chain = LoadFuncPtr . getValue ( <NUM_LIT> ) ; InFlag = LoadFuncPtr . getValue ( <NUM_LIT> ) ; SDValue PtrOff = DAG . getIntPtrConstant ( <NUM_LIT> ) ; SDValue AddPtr = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Callee , PtrOff ) ; SDValue LoadEnvPtr = DAG . getNode ( <STR_LIT> , dl , VTs , Chain , AddPtr , InFlag ) ; Chain = LoadEnvPtr . getValue ( <NUM_LIT> ) ; InFlag = LoadEnvPtr . getValue ( <NUM_LIT> ) ; SDValue EnvVal = DAG . getCopyToReg ( Chain , dl , <STR_LIT> , LoadEnvPtr , InFlag ) ; Chain = EnvVal . getValue ( <NUM_LIT> ) ; InFlag = EnvVal . getValue ( <NUM_LIT> ) ; VTs = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SDValue LoadTOCPtr = DAG . getNode ( <STR_LIT> , dl , VTs , Chain , Callee , InFlag ) ; Chain = LoadTOCPtr . getValue ( <NUM_LIT> ) ; InFlag = LoadTOCPtr . getValue ( <NUM_LIT> ) ; MTCTROps [ <NUM_LIT> ] = Chain ; MTCTROps [ <NUM_LIT> ]


<s> return __builtin_ia32_vcvtph2psx512_mask_round ( __B , _mm512_setzero_ps ( ) ,


<s> data . segment_base = segment_base ; data . gp = gp ; data . ret = NULL ; if ( dl_iterate_phdr ( _Unwind_IteratePhdrCallback , & data


<s> if ( IsSMRD != <ISA_LIT>InstrInfo :: isSMRD ( * MI ) ) break ; addClauseInst ( * MI ) ; } if ( ClauseDefs . none ( ) ) return <NUM_LIT> ; if ( MEM -> mayStore


<s> static void finitReachingDef ( BlockToSetOfInstrsPerColor & In , BlockToSetOfInstrsPerColor & Out , BlockToInstrPerColor & Gen , BlockToSetOfInstrsPerColor & ReachableUses ) { for ( auto & IT : Out ) delete [ ] IT . second ; for ( auto & IT : In ) delete [ ] IT . second ; for ( auto & IT : ReachableUses ) delete [ ] IT . second ; for ( auto & IT : Gen ) delete [ ] IT


<s> int64_t pos = InstIn . getOperand ( <NUM_LIT> ) . getImm ( ) ; assert ( InstIn . getOperand ( <NUM_LIT> ) . isImm ( ) ) ; int64_t size = InstIn . getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( size <= <NUM_LIT> ) { if ( pos < <NUM_LIT> ) return ; InstIn . getOperand ( <NUM_LIT> ) . setImm ( pos - <NUM_LIT> ) ; InstIn . setOpcode ( <STR_LIT> ) ; return ; } assert ( pos < <NUM_LIT> && <STR_LIT> ) ; InstIn . getOperand ( <NUM_LIT> ) . setImm ( size - <NUM_LIT> ) ; InstIn . setOpcode ( <STR_LIT>


<s> int <ISA_LIT>InstrInfo :: getIndirectIndexBegin ( const MachineFunction & MF ) const { const MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; int Offset = - <NUM_LIT> ; if ( MFI . getNumObjects ( ) == <NUM_LIT> ) { return - <NUM_LIT> ; } if ( MRI . livein_empty ( ) ) { return <NUM_LIT> ; } const TargetRegisterClass * IndirectRC = getIndirectAddrRegClass ( ) ; for ( std :: pair < unsigned , unsigned > LI : MRI . liveins ( ) ) { unsigned Reg = LI . first ; if ( Register :: isVirtualRegister ( Reg ) || ! IndirectRC -> contains ( Reg ) ) continue ; unsigned RegIndex ; unsigned RegEnd ; for ( RegIndex = <NUM_LIT> , RegEnd = IndirectRC -> getNumRegs ( ) ; RegIndex != RegEnd ; ++ RegIndex ) { if ( IndirectRC -> getRegister ( RegIndex ) == Reg ) break ; } Offset = std :: max ( Offset , ( int ) RegIndex ) ; } return Offset +


<s> bool Modified = false ; for ( auto & MBB : MF ) Modified |= ExpandMBB ( MBB ) ; return


<s> bool isBrTarget ( ) { return isBrImm ( ) || isToken (


<s> static void ix86_override_options_after_change (


<s> static __inline qword si_xor ( qword a , qword b


<s> inline int vec_any_ge ( vector float a1 , vector float a2 ) { return __builtin_altivec_vcmpgefp_p ( __CR6_EQ_REV , a1


<s> MCObjectWriter * createObjectWriter ( raw_ostream


<s> const TargetInstrInfo & TII = * MF . getSubtarget ( ) . getInstrInfo ( ) ; if ( NumBytes >= ALLOCFRAME_MAX ) { BuildMI ( MBB , InsertPt , dl , TII . get ( <STR_LIT> ) ) . addImm ( <NUM_LIT> ) ; BuildMI ( MBB , InsertPt , dl , TII . get ( <STR_LIT> ) , HEXAGON_RESERVED_REG_1 ) . addImm ( NumBytes ) ; BuildMI ( MBB , InsertPt , dl , TII . get ( <STR_LIT> ) , QRI -> getStackRegister ( ) ) . addReg ( QRI -> getStackRegister ( ) ) . addReg ( HEXAGON_RESERVED_REG_1 ) ; } else { BuildMI ( MBB , InsertPt , dl , TII . get (


<s> if ( ! is32Bit ) return MCDisassembler :: Fail ; DecodeStatus status = DecodeDataRegsRegisterClass ( Inst , d , Address , Decoder ) ; if ( status != MCDisassembler :: Success ) return status ; status = DecodeDataRegsRegisterClass ( Inst , s1 , Address , Decoder ) ; if ( status != MCDisassembler :: Success ) return status ; status = DecodeDataRegsRegisterClass ( Inst , s2 , Address , Decoder ) ; if ( status != MCDisassembler :: Success )


<s> SDValue Imm ; SDLoc DL ( N ) ; switch ( IID ) { default : llvm_unreachable ( <STR_LIT> ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { if ( auto * CN = dyn_cast < ConstantSDNode > ( Comparator . getOperand ( <NUM_LIT> ) ) ) { int64_t ImmVal = CN -> getSExtValue ( ) ; if ( ImmVal >= - <NUM_LIT> && ImmVal <= <NUM_LIT> ) Imm = DAG . getConstant ( ImmVal , DL , <STR_LIT> ) ; else return SDValue ( ) ; } break ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> static unsigned getRegOperandNumElts ( const MCInst * MI , unsigned ScalarSize , unsigned OperandIndex ) { unsigned OpReg = MI -> getOperand ( OperandIndex ) . getReg ( ) ; return getVectorRegSize ( OpReg


<s> if ( Dep . getReg ( ) != SrcInst -> getOperand ( <NUM_LIT> ) . getReg ( ) ) return ; } else if ( QII -> isPostIncrement ( * DstInst ) && Dep . getKind ( ) == SDep :: Anti ) { if ( DstInst -> mayStore ( ) ) return ; if ( Dep . getReg ( ) != DstInst -> getOperand ( <NUM_LIT> ) . getReg ( ) ) return ; } else if ( QII -> isPostIncrement ( * DstInst ) && DstInst -> mayStore ( ) && Dep . isAssignedRegDep ( ) ) { MachineOperand & Op = DstInst -> getOperand ( DstInst -> getNumOperands ( ) - <NUM_LIT> ) ; if ( Op . isReg ( ) && Dep . getReg ( ) != Op . getReg ( ) ) return ; } if ( useBSBScheduling ( ) && SrcInst -> isPHI ( ) ) { changePhiLatency ( * SrcInst , Dst , Dep ) ; return ; } if ( DstInst -> isRegSequence ( ) && Dst -> NumSuccs == <NUM_LIT> ) DstInst = Dst -> Succs [ <NUM_LIT> ] . getSUnit ( ) -> getInstr ( ) ; if ( EnableDotCurSched && QII -> isToBeScheduledASAP ( * SrcInst , * DstInst ) &&

isBestZeroLatency ( Src , Dst , QII ) ) {


<s> } ; bool UsePlt = Subtarget . is32BitELFABI ( ) && ! isLocalCallee ( ) && Subtarget . getTargetMachine ( ) . getRelocationModel ( ) == Reloc :: PIC_ ; const auto getAIXFuncEntryPointSymbolSDNode = [ & ] ( const GlobalValue * GV ) { const TargetMachine & TM = Subtarget . getTargetMachine ( ) ; const TargetLoweringObjectFile * TLOF = TM . getObjFileLowering ( ) ; MCSymbolXCOFF * S = cast < MCSymbolXCOFF > ( TLOF -> getFunctionEntryPointSymbol ( GV , TM ) ) ; MVT PtrVT = DAG . getTargetLoweringInfo ( ) . getPointerTy ( DAG . getDataLayout ( ) ) ; return DAG . getMCSymbol ( S , PtrVT ) ; } ; if ( isFunctionGlobalAddress ( Callee ) ) { const GlobalValue * GV = cast < GlobalAddressSDNode > ( Callee ) -> getGlobal ( ) ; if ( Subtarget . isAIXABI ( ) ) { assert ( ! isa < GlobalIFunc > ( GV ) && <STR_LIT> ) ; return getAIXFuncEntryPointSymbolSDNode (


<s> } if ( IndexReg . getReg ( ) || BaseReg . getReg ( ) ) { O << '(' ; if ( BaseReg . getReg ( ) ) printOperand ( MI , Op + <STR_LIT> , O ) ; if ( IndexReg . getReg ( ) ) { O << ',' ; printOperand ( MI , Op + <STR_LIT> , O ) ; unsigned ScaleVal = MI -> getOperand ( Op + <STR_LIT> ) . getImm ( ) ; if ( ScaleVal != <NUM_LIT> ) { O << ',' << markup ( <STR_LIT> ) << ScaleVal << markup (


<s> AU . addPreserved < MachineTraceMetrics > ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU


<s> int64_t Offset = <NUM_LIT> ; if ( IdxOp . getOpcode ( ) != <STR_LIT> ) { ConstantSDNode * CN = cast < ConstantSDNode > ( IdxOp ) ; assert ( CN != <NUM_LIT> && <STR_LIT> ) ; Offset = ( CN -> getSExtValue ( ) ) * eltVT . getSizeInBits ( ) / <NUM_LIT> ; } EVT PtrVT = DAG . getTargetLoweringInfo ( ) . getPointerTy ( ) ; SDValue Pointer = DAG . getNode ( <STR_LIT> , dl , PtrVT , DAG . getRegister ( <STR_LIT> , PtrVT ) , DAG . getConstant ( Offset , PtrVT ) ) ; EVT maskVT = EVT :: getVectorVT ( * ( DAG . getContext ( ) ) , VT . getVectorElementType ( ) , <NUM_LIT> / VT . getVectorElementType ( ) . getSizeInBits ( ) ) ; SDValue ShufMask = DAG . getNode ( <STR_LIT> , dl


<s> return new <ISA_LIT>OpLoweringLegacy (


<s> ArrayRef < int > GoodInputs = MoveToLo ? LoInputs : HiInputs ; ArrayRef < int > BadInputs = MoveToLo ? HiInputs : LoInputs ; if ( BadInputs . empty ( ) ) return V ; int MoveMask [ ] = { - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> } ; int MoveOffset = MoveToLo ? <NUM_LIT> : <NUM_LIT> ; if ( GoodInputs . empty ( ) ) { for ( int BadInput : BadInputs ) { MoveMask [ Mask [ BadInput ] % <NUM_LIT> + MoveOffset ] = Mask [ BadInput ] - MaskOffset ; Mask [ BadInput ] = Mask [ BadInput ] % <NUM_LIT> + MoveOffset + MaskOffset ; } } else { if ( GoodInputs . size ( ) == <NUM_LIT> ) { MoveMask [ Mask [ GoodInputs [ <NUM_LIT> ] ] % <NUM_LIT> + MoveOffset ] = Mask [ GoodInputs [ <NUM_LIT> ] ] - MaskOffset ; MoveMask [ Mask [ GoodInputs [ <NUM_LIT> ] ] % <NUM_LIT> + MoveOffset ] = Mask [ GoodInputs [ <NUM_LIT> ] ] - MaskOffset ; Mask [ GoodInputs [ <NUM_LIT> ] ] = Mask [ GoodInputs [ <NUM_LIT> ] ] % <NUM_LIT> + MoveOffset + MaskOffset ; Mask [ GoodInputs [ <NUM_LIT> ] ] = Mask [ GoodInputs [ <NUM_LIT> ] ] % <NUM_LIT> + MoveOffset + MaskOffset ; } else { for ( int GoodInput : GoodInputs ) MoveMask [ Mask [ GoodInput ] - MaskOffset ] = Mask [ GoodInput ] - MaskOffset ; } int MoveMaskIdx = std :: find ( std :: begin ( MoveMask ) + MoveOffset , std :: end ( MoveMask ) , - <NUM_LIT> ) - std :: begin ( MoveMask ) ; assert ( MoveMaskIdx >= MoveOffset && <STR_LIT> ) ; if ( BadInputs . size ( ) == <NUM_LIT> ) { assert ( MoveMask [ MoveMaskIdx ] == - <NUM_LIT> && <STR_LIT> ) ; assert ( MoveMask [ MoveMaskIdx + <NUM_LIT> ] == - <NUM_LIT> && <STR_LIT> ) ; MoveMask [ MoveMaskIdx + Mask [ BadInputs [ <NUM_LIT> ] ] % <NUM_LIT> ] = Mask [ BadInputs [ <NUM_LIT> ] ] - MaskOffset ; MoveMask [ MoveMaskIdx + Mask [ BadInputs [ <NUM_LIT> ] ] % <NUM_LIT> ] = Mask [ BadInputs [ <NUM_LIT> ] ] - MaskOffset ; Mask [ BadInputs [ <NUM_LIT> ] ] = MoveMaskIdx + Mask [ BadInputs [ <NUM_LIT> ] ] % <NUM_LIT> + MaskOffset ; Mask [ BadInputs [ <NUM_LIT> ] ] = MoveMaskIdx + Mask [ BadInputs [ <NUM_LIT> ] ] % <NUM_LIT> + MaskOffset ; } else { assert ( BadInputs . size ( ) == <NUM_LIT> && <STR_LIT> ) ; MoveMask [ MoveMaskIdx ] = Mask [ BadInputs [ <NUM_LIT> ] ] - MaskOffset ; Mask [ BadInputs [ <NUM_LIT> ] ] = MoveMaskIdx + MaskOffset ; } } return DAG . getVectorShuffle ( <STR_LIT> , DL , V , DAG . getUNDEF


<s> for ( SUnit :: pred_iterator I = ExitSU . Preds . begin ( ) , E = ExitSU . Preds . end ( ) ; I != E ; ++ I ) SUnits [ <NUM_LIT> ] . addPred ( SDep ( I -> getSUnit ( ) , SDep :: Order , <NUM_LIT> ) ) ; ExitSU . addPred ( SDep ( & SUnits [ <NUM_LIT> ] , SDep :: Order , <NUM_LIT> ) ) ; } for ( unsigned i = <NUM_LIT> , e = SUnits . size ( ) ; i != e ; ++ i ) { if ( SUnits [ i ] . getInstr ( ) -> getOpcode ( ) == <STR_LIT> ) continue ; if ( SUnits [ i ] . Succs . empty ( ) ) { int lat = SUnits [ i ] . Latency ; if ( firstTerm ) firstTerm -> addPred ( SDep ( & SUnits


<s> MCObjectWriter * createObjectWriter ( raw_ostream & OS ) const { return create<ISA_LIT>ELFObjectWriter ( OS , OSABI


<s> case VK_<ISA_LIT>_M44 : OS << <STR_LIT> ; return true ; case VK_<ISA_LIT>_L44 : OS << <STR_LIT> ; return true ; case VK_<ISA_LIT>_HH : OS << <STR_LIT> ; return true ; case VK_<ISA_LIT>_HM : OS << <STR_LIT> ; return true ; case VK_<ISA_LIT>_PC22 : OS << <STR_LIT> ; return true ; case VK_<ISA_LIT>_PC10 : OS << <STR_LIT> ; return true ; case VK_<ISA_LIT>_GOT22 : OS << <STR_LIT> ; return true ; case VK_<ISA_LIT>_GOT10 : OS << <STR_LIT> ; return true ; case VK_<ISA_LIT>_GOT13 : return false ; case VK_<ISA_LIT>_13 : return false ; case VK_Sparc_WDI<ISA_LIT>30 : return false ; case VK_<ISA_LIT>_WPLT30 : return false ; case VK_Sparc_R_DI<ISA_LIT>32 : OS << <STR_LIT> ; return true ; case VK_<ISA_LIT>_TLS_GD_HI22 : OS << <STR_LIT> ; return true ; case VK_<ISA_LIT>_TLS_GD_LO10 : OS << <STR_LIT> ; return true ; case VK_<ISA_LIT>_TLS_GD_ADD : OS << <STR_LIT> ; return true ; case VK_<ISA_LIT>_TLS_GD_CALL : OS << <STR_LIT> ; return true ; case VK_<ISA_LIT>_TLS_LDM_HI22 : OS << <STR_LIT> ; return true ; case VK_<ISA_LIT>_TLS_LDM_LO10 : OS << <STR_LIT> ; return true ; case VK_<ISA_LIT>_TLS_LDM_ADD : OS <<


<s> return TYPE_MODE ( op_info -> args [ <NUM_LIT> ] . get_tree_type ( type


<s> unsigned MovInst ; switch ( SrcVT . SimpleTy ) { case <STR_LIT> : MovInst = <STR_LIT> ; break ; case <STR_LIT> : MovInst = <STR_LIT> ; break ; case <STR_LIT> : MovInst = <STR_LIT> ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } unsigned Result32 = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( MovInst ) , Result32 ) . addReg ( ResultReg ) ; ResultReg = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( TargetOpcode :: SUBREG_TO_REG ) , ResultReg ) . addImm ( <NUM_LIT> ) . addReg (


<s> return Info ? Info -> BaseOpcode : -


<s> case LTU : rtx geu ; if ( GET_CODE ( op0 ) == PLUS && ( rtx_equal_p ( op1 , XEXP ( op0 , <NUM_LIT> ) ) || rtx_equal_p ( op1 , XEXP ( op0 , <NUM_LIT> ) ) ) ) return CCCmode ; else if ( code == LTU && GET_CODE ( op0 ) == NEG && GET_CODE ( geu = XEXP ( op0 , <NUM_LIT> ) ) == GEU && REG_P ( XEXP ( geu , <NUM_LIT> ) ) && ( GET_MODE ( XEXP ( geu , <NUM_LIT> ) ) == CCCmode || GET_MODE ( XEXP ( geu , <NUM_LIT> ) ) == CCmode ) && REGNO ( XEXP ( geu , <NUM_LIT> ) ) == FLAGS_REG && XEXP ( geu , <NUM_LIT> ) == const0_rtx && GET_CODE ( op1 ) == LTU && REG_P ( XEXP ( op1 , <NUM_LIT> ) ) && GET_MODE ( XEXP ( op1 , <NUM_LIT> ) ) == GET_MODE ( XEXP ( geu , <NUM_LIT> ) ) && REGNO ( XEXP ( op1 , <NUM_LIT> ) ) == FLAGS_REG && XEXP ( op1 , <NUM_LIT> ) == const0_rtx ) return CCCmode ; else return CCmode ; case GTU : case LEU : return CCmode ; case


<s> LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; NewMI -> dump ( ) ) ; FalseMBB -> insert ( FalseInsertionPoint , NewMI ) ; for ( auto & MOp : NewMI -> uses ( ) ) { if ( ! MOp . isReg ( ) ) continue ; auto It = FalseBBRegRewriteTable . find ( MOp . getReg ( ) ) ; if ( It == FalseBBRegRewriteTable . end ( ) ) continue ; MOp . setReg ( It -> second ) ; MOp . setIsKill ( false ) ; } } MBB -> erase ( MachineBasicBlock :: iterator ( MI ) , std :: next ( MachineBasicBlock :: iterator ( MI ) ) ) ; FalseBBRegRewriteTable [ NewCMOV -> getOperand ( <NUM_LIT> ) . getReg ( ) ] = TmpReg ; } DenseMap < unsigned , std :: pair < unsigned , unsigned >> RegRewriteTable ; for ( MachineBasicBlock :: iterator MIIt = MIItBegin ; MIIt != MIItEnd ; ++ MIIt ) { Register DestReg = MIIt -> getOperand ( <NUM_LIT> ) . getReg ( ) ; Register Op1Reg = MIIt -> getOperand ( <NUM_LIT> ) . getReg ( ) ; Register Op2Reg = MIIt -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( <STR_LIT> ( * MIIt ) == OppCC ) std :: swap ( Op1Reg , Op2Reg ) ; auto Op1Itr = RegRewriteTable . find ( Op1Reg ) ; if ( Op1Itr != RegRewriteTable . end ( ) ) Op1Reg = Op1Itr -> second . first ; auto Op2Itr = RegRewriteTable . find ( Op2Reg ) ; if ( Op2Itr != RegRewriteTable . end ( ) ) Op2Reg = Op2Itr -> second . second ; MIB = BuildMI ( * SinkMBB , SinkInsertionPoint , DL , TII -> get ( <STR_LIT> ) , DestReg ) . addReg ( Op1Reg ) . addMBB ( FalseMBB ) . addReg ( Op2Reg ) . addMBB ( MBB ) ; ( void ) MIB ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; MIIt -> dump ( ) ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; MIB -> dump ( ) ) ; RegRewriteTable [ DestReg ] = std :: make_pair ( Op1Reg , Op2Reg ) ; } MBB -> erase ( MIItBegin , MIItEnd ) ; if ( MachineLoop * L = MLI -> getLoopFor ( MBB ) ) { L -> addBasicBlockToLoop ( FalseMBB , MLI -> getBase ( ) ) ; L -> addBasicBlockToLoop ( SinkMBB , MLI -> getBase ( )


<s> if ( ! <ISA_LIT>MCInstrInfo :: isBundle ( MCI ) ) return false ; for ( const auto & I : <ISA_LIT>MCInstrInfo :: bundleInstructions ( MCI ) ) { if ( isImmext ( * I . getInst ( ) ) )


<s> ThumbTargetMachine :: ThumbTargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) : <ISA_LIT>BaseTargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL ) , InstrInfo ( Subtarget . hasThumb2 ( ) ? ( ( <ISA_LIT>BaseInstrInfo * ) new Thumb2InstrInfo ( Subtarget ) ) : ( ( <ISA_LIT>BaseInstrInfo * ) new Thumb1InstrInfo ( Subtarget ) ) ) , DataLayout ( Subtarget . isAPCS_ABI ( ) ? std :: string ( <STR_LIT> <STR_LIT> <STR_LIT> ) : Subtarget . isAAPCS_ABI ( ) ? std :: string ( <STR_LIT> <STR_LIT> <STR_LIT> ) : std :: string ( <STR_LIT> <STR_LIT> <STR_LIT> ) ) , ELFWriterInfo ( * this ) , TLInfo ( * this ) , TSInfo ( * this ) , FrameLowering ( Subtarget . hasThumb2 ( ) ? new <ISA_LIT>FrameLowering ( Subtarget ) :

( <ISA_LIT>FrameLowering * ) new Thumb1FrameLowering ( Subtarget ) ) {


<s> SelectionDAG & DAG = DCI . DAG ; if ( Subtarget -> isThumb1Only ( ) ) return SDValue ( ) ; if ( DCI . isBeforeLegalize ( ) || DCI . isCalledByLegalizer ( ) ) return SDValue ( ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( VT . is64BitVector ( ) || VT . is128BitVector ( ) ) return PerformVMULCombine ( N , DCI , Subtarget ) ; if ( VT != <STR_LIT> ) return SDValue ( ) ; ConstantSDNode * C = dyn_cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ; if ( ! C ) return SDValue ( ) ; int64_t MulAmt = C -> getSExtValue ( ) ; unsigned ShiftAmt = countTrailingZeros < uint64_t > ( MulAmt ) ; ShiftAmt = ShiftAmt & ( <NUM_LIT> - <NUM_LIT> ) ; SDValue V = N -> getOperand ( <NUM_LIT> ) ; SDLoc DL ( N ) ; SDValue Res ; MulAmt >>= ShiftAmt ; if ( MulAmt >= <NUM_LIT> ) { if ( isPowerOf2_32 ( MulAmt - <NUM_LIT> ) ) { Res = DAG . getNode ( <STR_LIT> , DL , VT , V , DAG . getNode ( <STR_LIT> , DL , VT , V , DAG . getConstant ( Log2_32 ( MulAmt - <NUM_LIT> ) , <STR_LIT> ) ) ) ; } else if ( isPowerOf2_32 ( MulAmt + <NUM_LIT> ) ) { Res = DAG . getNode ( <STR_LIT> , DL , VT , DAG . getNode ( <STR_LIT> , DL , VT , V , DAG . getConstant ( Log2_32 ( MulAmt + <NUM_LIT> ) , <STR_LIT> ) ) , V ) ; } else return SDValue ( ) ; } else { uint64_t MulAmtAbs = - MulAmt ; if ( isPowerOf2_32 ( MulAmtAbs + <NUM_LIT> ) ) { Res = DAG . getNode ( <STR_LIT> , DL , VT , V , DAG . getNode ( <STR_LIT> , DL , VT , V , DAG . getConstant ( Log2_32 ( MulAmtAbs + <NUM_LIT> ) , <STR_LIT> ) ) ) ; } else if ( isPowerOf2_32 ( MulAmtAbs - <NUM_LIT> ) ) { Res = DAG . getNode ( <STR_LIT> , DL , VT , V , DAG . getNode ( <STR_LIT> , DL , VT , V , DAG . getConstant ( Log2_32 ( MulAmtAbs - <NUM_LIT> ) , <STR_LIT> ) ) ) ; Res = DAG . getNode ( <STR_LIT> , DL , VT , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) , Res ) ; } else return SDValue ( ) ; } if ( ShiftAmt != <NUM_LIT> ) Res = DAG . getNode ( <STR_LIT> , DL , VT , Res , DAG . getConstant ( ShiftAmt , <STR_LIT> ) ) ; DCI . CombineTo ( N , Res , false ) ; return SDValue ( )


<s> bool <ISA_LIT>BasicBlockUtils :: isBBInRange ( MachineInstr * MI , MachineBasicBlock * DestBB , unsigned MaxDisp ) const { unsigned PCAdj = isThumb ? <NUM_LIT> : <NUM_LIT> ; unsigned BrOffset = getOffsetOf ( MI ) + PCAdj ; unsigned DestOffset = BBInfo [ DestBB -> getNumber ( ) ] . Offset ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << printMBBReference ( * DestBB ) << <STR_LIT> << printMBBReference ( * MI -> getParent ( ) ) << <STR_LIT> << MaxDisp << <STR_LIT> << getOffsetOf ( MI ) << <STR_LIT> << DestOffset << <STR_LIT> << int ( DestOffset - BrOffset ) << <STR_LIT> << * MI ) ; if ( BrOffset <= DestOffset ) { if ( DestOffset - BrOffset <= MaxDisp ) return true ; }


<s> static bool IsInSmallSection ( uint64_t Size


<s> Result = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Result , DAG . getConstant ( <NUM_LIT> , SL , <STR_LIT> ) ) ; } else { assert ( CIdx -> getZExtValue ( ) == <NUM_LIT> ) ; } if ( ResultVT . bitsLT ( <STR_LIT> ) ) Result = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Result ) ; return DAG . getNode ( <STR_LIT> , SL , ResultVT , Result ) ; } SDValue Sixteen = DAG . getConstant ( <NUM_LIT> , SL , <STR_LIT> ) ; SDValue ScaledIdx = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Idx , Sixteen ) ; SDValue BC = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Vec ) ; SDValue Elt = DAG . getNode ( <STR_LIT> , SL , <STR_LIT>


<s> return ( __m512i ) __builtin_ia32_cvttps2qq512_mask ( ( __v8sf ) __A , ( __v8di ) _mm512_setzero_si512 ( )


<s> bool isRegOrImmWithFP64InputMods ( ) const { return isRegOrImmWithInputMods (


<s> return ( int ) __builtin_ia32_vcvttsd2si32 ( ( __v2df


<s> void <ISA_LIT>InterleavedAccessGroup :: interleave8bitStride3 ( ArrayRef < Instruction * > InVec , SmallVectorImpl < Value * > & TransposedMatrix , unsigned VecElems ) { TransposedMatrix . resize ( <NUM_LIT> ) ; SmallVector < int , <NUM_LIT> > GroupSize ; SmallVector < int , <NUM_LIT> > VPShuf ; SmallVector < int , <NUM_LIT> > VPAlign [ <NUM_LIT> ] ; SmallVector < int , <NUM_LIT> > VPAlign2 ; SmallVector < int , <NUM_LIT> > VPAlign3 ; Value * Vec [ <NUM_LIT> ] , * TempVector [ <NUM_LIT> ] ; MVT VT = <STR_LIT> ( <STR_LIT> , VecElems ) ; setGroupSize ( VT , GroupSize ) ; for ( int i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) DecodePALIGNRMask ( VT , GroupSize [ i ] , VPAlign [ i ] ) ; DecodePALIGNRMask ( VT , GroupSize [ <NUM_LIT> ] + GroupSize [ <NUM_LIT> ] , VPAlign2


<s> return ( _U_Qfcmp ( a , b , QCMP_EQ )


<s> { <STR_LIT> CR_TAB <STR_LIT> , <STR_LIT> } , { <STR_LIT> CR_TAB <STR_LIT> , <STR_LIT> } , { <STR_LIT> CR_TAB <STR_LIT> , <STR_LIT> } , { <STR_LIT> CR_TAB <STR_LIT> , <STR_LIT> } } ; xop [ <NUM_LIT> ] = xdest [ n ] ; xop [ <NUM_LIT> ] = src ; xop [ <NUM_LIT> ] = clobber_reg ; avr_asm_len ( asm_code [ n ] [ ldreg_p ] , xop , len , ldreg_p ? <NUM_LIT> : <NUM_LIT> ) ; continue ; } xval = simplify_gen_subreg ( QImode , src , mode , n ) ; ival [ n ] = INTVAL ( xval ) ; if ( n == <NUM_LIT> && n_bytes >= <NUM_LIT> && AVR_HAVE_MOVW ) { rtx lo16 = simplify_gen_subreg ( HImode , src , mode , <NUM_LIT> ) ; rtx hi16 = simplify_gen_subreg ( HImode , src , mode , <NUM_LIT> ) ; if ( INTVAL ( lo16 ) == INTVAL ( hi16 ) ) { if ( <NUM_LIT> != INTVAL ( lo16 ) || ! clear_p ) { avr_asm_len ( <STR_LIT> , & op [ <NUM_LIT> ] , len , <NUM_LIT> ) ; } break ; } } if ( ival [ n ] == <NUM_LIT> ) { if ( ! clear_p ) avr_asm_len ( ldreg_p ? <STR_LIT> : AVR_ZERO_REGNO == REGNO ( xdest [ n ] ) ? <STR_LIT> : <STR_LIT> , & xdest [ n ] , len , <NUM_LIT> ) ; continue ; } if ( clobber_val == ival [ n ] && REGNO ( clobber_reg ) == REGNO ( xdest [ n ] ) ) { continue ; } if ( ldreg_p ) { xop [ <NUM_LIT> ] = xdest [ n ] ; xop [ <NUM_LIT> ] = xval ; avr_asm_len ( <STR_LIT> , xop , len , <NUM_LIT> ) ; continue ; } for ( j = <NUM_LIT> ; j < n ; j ++ ) if ( ival [ j ] == ival [ n ] ) { xop [ <NUM_LIT> ] = xdest [ n ] ; xop [ <NUM_LIT> ] = xdest [ j ] ; avr_asm_len ( <STR_LIT> , xop , len , <NUM_LIT> ) ; done_byte = true ; break ; } if ( done_byte )


<s> bool is32BitMode ( const MCSubtargetInfo &


<s> unsigned InReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; DebugLoc DL = MI . getDebugLoc ( ) ; unsigned GPR3 = Is64Bit ? <STR_LIT> : <STR_LIT> ; unsigned Opc1 , Opc2 ; const unsigned OrigRegs [ ] = { OutReg , InReg , GPR3 } ; switch ( MI . getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : Opc1 = <STR_LIT> ; Opc2 = <STR_LIT> ; break ; case <STR_LIT> : Opc1 = <STR_LIT> ; Opc2 = <STR_LIT> ; break ; case <STR_LIT> : Opc1 = <STR_LIT> ; Opc2 = <STR_LIT> ; break ; case <STR_LIT> : Opc1 = <STR_LIT> ; Opc2 = <STR_LIT> ; break ; } BuildMI ( MBB , I , DL , TII -> get ( <STR_LIT> ) ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; MachineInstr * Addi = BuildMI ( MBB , I , DL , TII -> get ( Opc1 ) , GPR3 ) . addReg ( InReg ) ; Addi -> addOperand ( MI . getOperand ( <NUM_LIT> ) ) ; MachineBasicBlock :: iterator First = I ; -- First ; MachineInstr * Call = ( BuildMI ( MBB , I , DL , TII -> get ( Opc2 ) , GPR3 ) . addReg ( GPR3 ) ) ; Call -> addOperand ( MI . getOperand ( <NUM_LIT> ) ) ; BuildMI ( MBB , I , DL , TII -> get ( <STR_LIT> ) ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; BuildMI ( MBB , I , DL , TII -> get ( TargetOpcode :: COPY ) , OutReg ) . addReg ( GPR3 ) ; MachineBasicBlock :: iterator Last = I ; -- Last ; ++ I ; MI . removeFromParent ( ) ; LIS -> repairIntervalsInRange ( & MBB ,


<s> if ( mode != V4SFmode && all_const_zero ) { emit_insn ( gen_rtx_SET ( VOIDmode , target , gen_rtx_XOR ( mode , target , target ) ) ) ; return ; } else if ( mode != V4SFmode && easy_vector_constant ( vals , mode ) ) { emit_insn ( gen_rtx_SET ( VOIDmode , target , vals ) ) ; return ; } else if ( all_same ) ; else { emit_move_insn ( target , gen_rtx_CONST_VECTOR ( mode , XVEC ( vals , <NUM_LIT> ) ) ) ; return ; } } if ( all_same ) { mem = assign_stack_temp ( mode , GET_MODE_SIZE ( inner_mode ) , <NUM_LIT> ) ; emit_move_insn ( adjust_address_nv ( mem , inner_mode , <NUM_LIT> ) , XVECEXP ( vals , <NUM_LIT> , <NUM_LIT> ) ) ; x = gen_rtx_UNSPEC ( VOIDmode , gen_rtvec ( <NUM_LIT> , const0_rtx ) , UNSPEC_LVE ) ; emit_insn ( gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( <NUM_LIT> , gen_rtx_SET ( VOIDmode , target , mem ) , x ) ) ) ; x = gen_rtx_VEC_SELECT ( inner_mode , target , gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( <NUM_LIT> , const0_rtx ) ) ) ; emit_insn ( gen_rtx_SET ( VOIDmode , target , gen_rtx_VEC_DUPLICATE ( mode , x ) ) ) ; return ; } if ( n_var == <NUM_LIT> ) { rtx copy = copy_rtx ( vals ) ; XVECEXP ( copy , <NUM_LIT> , one_var ) = XVECEXP ( vals , <NUM_LIT> , ( one_var + <NUM_LIT> ) % n_elts ) ; rs6000_expand_vector_init ( target , copy ) ; rs6000_expand_vector_set ( target , XVECEXP ( vals , <NUM_LIT> , one_var ) , one_var ) ; return ; } mem = assign_stack_temp ( mode , GET_MODE_SIZE ( mode ) , <NUM_LIT> ) ; for ( i = <NUM_LIT> ; i < n_elts ; i ++ ) emit_move_insn ( adjust_address_nv ( mem , inner_mode , i

* GET_MODE_SIZE ( inner_mode ) ) , XVECEXP ( vals , <NUM_LIT> , i ) ) ;


<s> auto decoder = Decode < Disassembler >


<s> static void AliasCandidates ( BasicBlock * Header , Instructions & Reads , Instructions & Writes ) { for ( auto & I


<s> const_iterator end ( ) const { return Blocks . end (


<s> if ( Target . getSymA ( ) ) SD = & Asm . getSymbolData ( Target . getSymA ( ) -> getSymbol ( ) ) ; const uint32_t FixupOffset = getFixupOffset ( Layout , Fragment , Fixup ) ; unsigned Index = <NUM_LIT> ; unsigned Type = RelocType ; const MCSymbolData * RelSymbol = nullptr ; if ( Target . isAbsolute ( ) ) { report_fatal_error ( <STR_LIT> <STR_LIT> ) ; } else { if ( SD -> getSymbol ( ) . isVariable ( ) ) { int64_t Res ; if ( SD -> getSymbol ( ) . getVariableValue ( ) -> EvaluateAsAbsolute ( Res , Layout , Writer -> getSectionAddressMap ( ) ) ) { FixedValue = Res ; return ; } } if ( Writer -> doesSymbolRequireExternRelocation ( SD ) ) { RelSymbol = SD ; if ( ! SD -> getSymbol ( ) . isUndefined ( ) ) FixedValue -= Layout . getSymbolOffset ( SD ) ; } else { const MCSectionData & SymSD = Asm . getSectionData ( SD -> getSymbol ( ) . getSection ( ) ) ; Index = SymSD . getOrdinal ( ) + <NUM_LIT> ; FixedValue += Writer -> getSectionAddress ( & SymSD ) ; } if ( IsPCRel ) FixedValue -= Writer -> getSectionAddress ( Fragment


<s> TargetLoweringObjectFile * getObjFileLowering (


<s> addPass ( createAMDGPUISelDag ( getAMDGPUTargetMachine ( ) ) ) ; return


<s> static SDValue combine<ISA_LIT>GatherScatter ( SDNode * N , SelectionDAG & DAG , TargetLowering :: DAGCombinerInfo & DCI , const <ISA_LIT>Subtarget & Subtarget ) { auto * MemOp = cast < <ISA_LIT>MaskedGatherScatterSDNode > ( N ) ; SDValue BasePtr = MemOp -> getBasePtr ( ) ; SDValue Index = MemOp -> getIndex ( ) ; SDValue Scale = MemOp -> getScale ( ) ; SDValue Mask = MemOp -> getMask ( ) ; if ( ( Index . getOpcode ( ) == <STR_LIT> || ( Index . getOpcode ( ) == <STR_LIT> && Index . getOperand ( <NUM_LIT> ) == Index . getOperand ( <NUM_LIT> ) ) ) && isa < ConstantSDNode > ( Scale ) && BasePtr . getScalarValueSizeInBits ( ) == Index . getScalarValueSizeInBits ( ) ) { unsigned ShiftAmt = Index . getOpcode ( ) == <STR_LIT> ? <NUM_LIT> : Index . getConstantOperandVal ( <NUM_LIT> ) ; uint64_t ScaleAmt = cast < ConstantSDNode > ( Scale ) -> getZExtValue ( ) ; uint64_t NewScaleAmt = ScaleAmt * ( <NUM_LIT> << ShiftAmt ) ; if ( isPowerOf2_64 ( NewScaleAmt ) && NewScaleAmt <= <NUM_LIT> ) { SDValue NewIndex = Index . getOperand ( <NUM_LIT> ) ; SDValue NewScale = DAG . getTargetConstant ( NewScaleAmt , SDLoc ( N ) , Scale . getValueType ( ) ) ; if ( N -> getOpcode ( ) == <STR_LIT> ) return getAVX2GatherNode ( N -> getOpcode ( ) , SDValue ( N , <NUM_LIT> ) , DAG , MemOp -> getOperand ( <NUM_LIT> ) , Mask , MemOp -> getBasePtr ( ) , NewIndex , NewScale , MemOp -> getChain ( ) , Subtarget ) ; if ( N -> getOpcode ( ) == <STR_LIT> ) return getScatterNode ( N -> getOpcode ( ) , SDValue ( N , <NUM_LIT> ) , DAG , MemOp -> getOperand ( <NUM_LIT> ) , Mask , MemOp -> getBasePtr ( ) , NewIndex , NewScale , MemOp -> getChain ( ) , Subtarget ) ; } } if ( Mask . getScalarValueSizeInBits ( ) != <NUM_LIT> ) { const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; APInt DemandedMask ( APInt :: getSignMask ( Mask . getScalarValueSizeInBits ( ) ) ) ; if ( TLI . SimplifyDemandedBits ( Mask , DemandedMask , DCI ) ) { if ( N -> getOpcode ( ) != <STR_LIT> ) DCI . AddToWorklist (


<s> std :: vector < MachineInstr * > CPEMIs ; if ( ! MCP -> isEmpty ( ) ) doInitialPlacement ( CPEMIs ) ; initPICLabelUId ( CPEMIs . size ( ) ) ; initializeFunctionInfo ( CPEMIs ) ; CPEMIs . clear ( ) ; DEBUG ( dumpBBs ( ) ) ; MadeChange |= removeUnusedCPEntries ( ) ; unsigned NoCPIters = <NUM_LIT> , NoBRIters = <NUM_LIT> ; ( void ) NoBRIters ; while ( true ) { DEBUG ( dbgs ( ) << <STR_LIT> << NoCPIters << '\n' ) ; bool CPChange = false ; for ( unsigned i = <NUM_LIT> , e = CPUsers . size ( ) ; i != e ; ++ i ) CPChange |= handleConstantPoolUser ( i ) ; if ( CPChange && ++ NoCPIters > <NUM_LIT> ) report_fatal_error ( <STR_LIT> ) ; DEBUG ( dumpBBs ( ) ) ; NewWaterList . clear ( ) ; DEBUG ( dbgs ( ) << <STR_LIT> << NoBRIters << '\n' ) ; bool BRChange


<s> ConstantSDNode * N = cast < ConstantSDNode > ( S ) ; int64_t v = ( int64_t ) N ->


<s> const StoreInst * S = cast < StoreInst > ( I ) ; if ( S -> isAtomic ( ) ) return false ; unsigned SABIAlignment = TD . getABITypeAlignment ( S -> getValueOperand ( ) -> getType ( ) ) ; if ( S -> getAlignment ( ) != <NUM_LIT> && S -> getAlignment ( ) < SABIAlignment ) return false ; MVT VT ; if ( ! isTypeLegal ( I -> getOperand ( <NUM_LIT> ) -> getType ( ) , VT , true ) ) return false ; <ISA_LIT>AddressMode AM


<s> <ISA_LIT>AsmPrinter :: <ISA_LIT>AsmPrinter ( TargetMachine & TM , std :: unique_ptr < MCStreamer > Streamer ) : AsmPrinter ( TM , std :: move ( Streamer ) ) , AFI ( nullptr ) , MCP ( nullptr ) , InConstantPool ( false ) { Subtarget = & TM . getSubtarget


<s> int64_t <ISA_LIT>mm = static_cast < int64_t > ( Imm ) ; if ( <ISA_LIT>mm >= - <NUM_LIT> && <ISA_LIT>mm <= <NUM_LIT> ) { O << <ISA_LIT>mm ; return ; } if ( Imm == DoubleToBits ( <NUM_LIT> ) ) O << <STR_LIT> ; else if ( Imm == DoubleToBits ( <NUM_LIT> ) ) O << <STR_LIT> ; else if ( Imm == DoubleToBits ( - <NUM_LIT> ) ) O << <STR_LIT> ; else if ( Imm == DoubleToBits ( <NUM_LIT> ) ) O << <STR_LIT> ; else if ( Imm == DoubleToBits ( - <NUM_LIT> ) ) O << <STR_LIT> ; else if ( Imm == DoubleToBits ( <NUM_LIT> )


<s> return Kind == k_VectorList && VectorList . Count == NumRegs


<s> void <ISA_LIT>FrameLowering :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB ,

MachineBasicBlock :: iterator I ) const {


<s> decltype ( End ) NextI ; for ( auto I = Begin ; I != End ; I = NextI ) { NextI = std :: next ( I ) ; if ( I -> getSubReg ( ) != OldSR ) continue ; I -> setReg (


<s> switch ( VA . getLocInfo ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case CCValAssign :: Full : break ; case CCValAssign :: SExt : Arg = DAG . getNode ( <STR_LIT> , CLI . DL , VA . getLocVT ( ) , Arg ) ; break ; case CCValAssign :: ZExt : Arg = DAG . getNode ( <STR_LIT> , CLI . DL , VA . getLocVT ( ) , Arg ) ; break ; case CCValAssign :: AExt : Arg = DAG . getNode ( <STR_LIT> , CLI . DL , VA . getLocVT ( ) , Arg ) ; break ; } if ( VA . isRegLoc ( ) ) RegsToPass . push_back ( std :: make_pair ( VA . getLocReg ( ) , Arg ) ) ; else llvm_unreachable ( <STR_LIT> ) ; } SDValue InFlag ; for ( auto & Reg : RegsToPass ) { Chain = DAG . getCopyToReg ( Chain , CLI . DL , Reg . first , Reg . second , InFlag ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; } if ( GlobalAddressSDNode * G = dyn_cast < GlobalAddressSDNode > ( Callee ) ) Callee = DAG . getTargetGlobalAddress ( G -> getGlobal ( ) , CLI . DL , getPointerTy ( ) , G -> getOffset ( ) , <NUM_LIT> ) ; else if ( ExternalSymbolSDNode * E = dyn_cast < ExternalSymbolSDNode > ( Callee ) ) Callee = DAG . getTargetExternalSymbol ( E -> getSymbol ( ) , getPointerTy ( ) , <NUM_LIT> ) ; SDVTList NodeTys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . push_back ( Chain ) ; Ops . push_back ( Callee ) ; for ( auto & Reg : RegsToPass ) Ops . push_back ( DAG . getRegister ( Reg . first , Reg . second . getValueType ( ) ) ) ; if ( InFlag . getNode ( ) )


<s> return true ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Result = LHS ^ RHS ; return true ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Result = LHS << ( RHS & <NUM_LIT> ) ; return true ; case <STR_LIT> : case <STR_LIT> : Result = RHS << ( LHS & <NUM_LIT> ) ; return true ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Result = LHS >> ( RHS & <NUM_LIT> ) ; return true ; case <STR_LIT> : case <STR_LIT> : Result = RHS >> ( LHS & <NUM_LIT> ) ; return true ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Result = static_cast < int32_t > ( LHS ) >> ( RHS & <NUM_LIT> ) ; return true ; case <STR_LIT>


<s> SDValue Ops [ ] = { Chain , In1 , In2L , In2H } ; SDVTList Tys = DAG . getVTList ( <STR_LIT> , <STR_LIT> , <STR_LIT> ) ; SDValue Result = DAG . getMemIntrinsicNode ( NewOp , dl , Tys , Ops , <NUM_LIT> , <STR_LIT> , cast < MemSDNode > ( Node ) -> getMemOperand ( ) ) ; SDValue OpsF [ ] = { Result . getValue ( <NUM_LIT> ) , Result .


<s> sign = SIGNBIT ; a1 = ( long ) - ( unsigned long ) a1 ; if ( a1 < <NUM_LIT> ) { dl . l . upper = SIGNBIT | ( ( <NUM_LIT> + EXCESSD ) << <NUM_LIT> ) ; dl . l . lower = <NUM_LIT> ; return dl . d ; } } while ( a1 < <NUM_LIT> ) { a1 <<= <NUM_LIT> ; exp -= <NUM_LIT> ; } while ( a1 < <NUM_LIT> ) { a1 <<= <NUM_LIT> ; exp --


<s> EVT EltTy = N -> getValueType ( <NUM_LIT> ) . getVectorElementType ( ) ; if ( N -> getOpcode ( ) == <STR_LIT> ) N = N -> getOperand ( <NUM_LIT> ) ; if ( selectVSplat ( N . getNode ( ) , ImmValue , EltTy . getSizeInBits ( ) ) && ImmValue . getBitWidth ( ) == EltTy . getSizeInBits ( ) ) { if ( ImmValue == ( ImmValue & ~ ( ImmValue +


<s> static MCDisassembler * create<ISA_LIT>Disassembler ( const Target & T , const

MCSubtargetInfo & STI , MCContext & Ctx ) {


<s> if ( Tp -> getScalarType ( ) -> isFP128Ty ( ) ) return ( Kind == TargetTransformInfo :: SK_Broadcast ? NumVectors - <NUM_LIT> : <NUM_LIT> ) ; switch ( Kind ) { case TargetTransformInfo :: SK_ExtractSubvector : return ( Index == <NUM_LIT> ? <NUM_LIT> : NumVectors ) ; case TargetTransformInfo :: SK_Broadcast : return NumVectors - <NUM_LIT> ; default : return NumVectors


<s> <ISA_LIT>BaseTargetMachine :: <ISA_LIT>BaseTargetMachine ( const Target & T , const std :: string & TT , const std :: string & FS , bool isThumb ) : LLVMTargetMachine ( T , TT ) , Subtarget ( TT , FS , isThumb ) , FrameInfo ( Subtarget ) , JITInfo ( ) , InstrItins

( Subtarget . getInstrItineraryData ( ) ) {


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return


<s> bool isCSR = ! isFixed && ObjectOffset >= - ( ( int ) AFI -> getCalleeSavedStackSize ( ) ) ; const StackOffset & SVEStackSize = getSVEStackSize ( MF ) ; if ( SVEStackSize ) llvm_unreachable ( <STR_LIT> <STR_LIT> ) ; bool UseFP = false ; if ( AFI -> hasStackFrame ( ) ) { if ( isFixed ) { UseFP = hasFP ( MF ) ; } else if ( isCSR && RegInfo -> needsStackRealignment ( MF ) ) { assert ( hasFP ( MF ) && <STR_LIT> ) ; UseFP = true ; } else if ( hasFP ( MF ) && ! RegInfo -> needsStackRealignment ( MF ) ) { bool FPOffsetFits = ! ForSimm || FPOffset >= - <NUM_LIT> ; PreferFP |= Offset > - FPOffset ; if ( MFI . hasVarSizedObjects ( ) ) { bool CanUseBP = RegInfo -> hasBasePointer ( MF ) ; if ( FPOffsetFits && CanUseBP ) UseFP = PreferFP ; else if ( ! CanUseBP ) UseFP = true ; } else if ( FPOffset >= <NUM_LIT> ) { UseFP = true ; } else if ( MF . hasEHFunclets ( ) && ! RegInfo -> hasBasePointer ( MF ) ) { ( void )


<s> switch ( MI -> getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case


<s> reg = load_tls_operand ( sum , reg ) ; if ( TARGET_ARM ) emit_insn ( gen_pic_add_dot_plus_eight ( reg , reg , labelno ) ) ; else emit_insn ( gen_pic_add_dot_plus_four ( reg , reg , labelno ) ) ; * valuep = emit_library_call_value ( get_tls_get_addr ( ) , NULL_RTX , LCT_PURE , Pmode , <NUM_LIT> , reg , Pmode ) ; insns = get_insns ( ) ; end_sequence ( ) ; return insns


<s> SDValue <ISA_LIT>TargetLowering :: lowerJumpTable ( SDValue Op , SelectionDAG & DAG ) const { JumpTableSDNode * N = cast < JumpTableSDNode > ( Op ) ; EVT Ty = Op . getValueType ( ) ; if ( ! isPositionIndependent ( ) && ! ABI . IsN64 ( ) ) return getAddrNonPIC ( N ,


<s> if ( I . getFlag ( MachineInstr :: MIFlag :: NoSWrap ) && canUseNSW ( NewOpcode ) && getSymbolicOperandRequirements ( OperandCategory :: DecorationOperand , Decoration :: NoSignedWrap , ST ) . isSatisfiable ) buildOpDecorate ( Target , I , TII , Decoration ::


<s> unsigned NumHalfElts = NumElts / <NUM_LIT> ; for ( unsigned l = <NUM_LIT> ; l != NumHalfElts ; ++ l ) ShuffleMask . push_back ( l + NumHalfElts ) ; for ( unsigned h = <NUM_LIT> ; h != NumHalfElts ; ++ h ) ShuffleMask . push_back


<s> OffImm = CurDAG -> getTargetConstant ( <NUM_LIT> , <STR_LIT> ) ; return true ; } if ( ConstantSDNode * RHS = dyn_cast < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) ) ) { int RHSC = ( int ) RHS -> getZExtValue ( ) ; if ( N . getOpcode ( ) == <STR_LIT> ) RHSC = - RHSC ; if ( RHSC >= <NUM_LIT> && RHSC < <NUM_LIT> ) { Base = N . getOperand ( <NUM_LIT> ) ; if ( Base . getOpcode ( ) == <STR_LIT> ) { int FI = cast < FrameIndexSDNode > ( Base ) -> getIndex ( ) ; Base = CurDAG -> getTargetFrameIndex ( FI , TLI -> getPointerTy ( ) ) ; } OffImm = CurDAG -> getTargetConstant ( RHSC , <STR_LIT> ) ; return true ; } } Base = N ; OffImm = CurDAG -> getTargetConstant ( <NUM_LIT> , <STR_LIT> ) ; return


<s> if ( MO . isReg ( ) && MO . getReg ( ) != <NUM_LIT> && ! MO . isDef ( ) && ! Register :: isVirtualRegister ( MO . getReg ( ) ) ) Candidates . reset ( MO . getReg ( ) ) ; } BitVector Available = RS . getRegsAvailable ( & <STR_LIT> ) ; Available &= Candidates ; signed Reg = Available .


<s> return DAG . getNode ( <STR_LIT> , dl , VT , V1 , V2 , DAG . getConstant ( Imm , <STR_LIT> ) ) ; } if ( isVREVMask ( ShuffleMask , VT , <NUM_LIT> ) ) return DAG . getNode ( <STR_LIT> , dl , VT , V1 ) ; if ( isVREVMask ( ShuffleMask , VT , <NUM_LIT> ) ) return DAG . getNode ( <STR_LIT> , dl , VT , V1 ) ; if ( isVREVMask ( ShuffleMask , VT , <NUM_LIT> ) ) return DAG . getNode ( <STR_LIT> , dl , VT , V1 ) ; if ( V2 -> getOpcode ( ) == <STR_LIT> && isSingletonVEXTMask ( ShuffleMask , VT , Imm ) ) { return DAG . getNode ( <STR_LIT> , dl , VT , V1 , V1 , DAG . getConstant ( Imm , <STR_LIT> ) ) ; } unsigned WhichResult ; if ( isVTRNMask ( ShuffleMask , VT , WhichResult ) ) return DAG . getNode ( <STR_LIT> , dl , DAG . getVTList ( VT , VT ) , V1 , V2 ) . getValue ( WhichResult ) ; if ( isVUZPMask ( ShuffleMask , VT , WhichResult ) ) return DAG . getNode ( <STR_LIT> , dl , DAG . getVTList ( VT , VT ) , V1 , V2 ) . getValue ( WhichResult ) ; if ( isVZIPMask ( ShuffleMask , VT , WhichResult ) ) return DAG . getNode ( <STR_LIT> , dl , DAG . getVTList ( VT , VT ) , V1 , V2 ) . getValue ( WhichResult ) ; if ( isVTRN_v_undef_Mask ( ShuffleMask , VT , WhichResult ) ) return DAG . getNode ( <STR_LIT> , dl , DAG . getVTList ( VT , VT ) , V1 , V1 ) . getValue ( WhichResult ) ; if ( isVUZP_v_undef_Mask ( ShuffleMask , VT , WhichResult ) ) return DAG . getNode ( <STR_LIT> , dl , DAG . getVTList ( VT , VT ) , V1 , V1 ) . getValue ( WhichResult ) ; if ( isVZIP_v_undef_Mask ( ShuffleMask , VT , WhichResult ) ) return DAG . getNode ( <STR_LIT> , dl , DAG . getVTList ( VT , VT ) , V1 , V1 ) . getValue ( WhichResult ) ; } unsigned NumElts = VT . getVectorNumElements ( ) ; if ( NumElts == <NUM_LIT> ) { unsigned PFIndexes [ <NUM_LIT>


<s> unsigned M = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned iflags = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned mode = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; DecodeStatus S = MCDisassembler :: Success ; if ( imod == <NUM_LIT> ) return MCDisassembler :: Fail ; if ( imod && M ) { Inst . setOpcode ( <STR_LIT> ) ; Inst . addOperand ( MCOperand :: CreateImm ( imod ) ) ; Inst . addOperand ( MCOperand :: CreateImm ( iflags ) ) ; Inst . addOperand ( MCOperand :: CreateImm ( mode ) ) ; } else if ( imod && ! M ) { Inst . setOpcode ( <STR_LIT> ) ; Inst . addOperand ( MCOperand :: CreateImm ( imod ) ) ; Inst . addOperand ( MCOperand :: CreateImm ( iflags ) ) ; if ( mode ) S = MCDisassembler :: SoftFail ; } else if ( ! imod && M ) { Inst . setOpcode ( <STR_LIT> ) ; Inst . addOperand ( MCOperand :: CreateImm ( mode ) ) ; if ( iflags ) S = MCDisassembler :: SoftFail ; } else { Inst . setOpcode ( <STR_LIT> ) ; Inst . addOperand ( MCOperand :: CreateImm (


<s> unsigned getMaxFlatWorkGroupSize ( ) const { return


<s> MachineBasicBlock * MBB = MI . getParent ( ) ; if ( MI . isImplicitDef ( ) ) { unsigned R = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( <STR_LIT> . contains ( R ) ) { MCSuperRegIterator S ( R , HRI , false ) ; MI . addOperand ( MachineOperand :: CreateReg ( * S , true , true ) ) ; } return MII ; } assert ( ResourceTracker -> canReserveResources ( MI ) ) ; bool ExtMI = HII -> isExtended ( MI ) || HII -> isConstExtended ( MI ) ; bool Good = true ; if ( GlueToNewValueJump ) { MachineInstr & NvjMI = * ++ MII ; ResourceTracker -> reserveResources ( MI ) ; if ( ExtMI ) Good = tryAllocateResourcesForConstExt ( true ) ; bool ExtNvjMI = HII -> isExtended ( NvjMI ) || HII -> isConstExtended ( NvjMI ) ; if ( Good ) { if ( ResourceTracker -> canReserveResources ( NvjMI ) ) ResourceTracker -> reserveResources ( NvjMI ) ; else Good = false ; } if ( Good && ExtNvjMI ) Good = tryAllocateResourcesForConstExt ( true ) ; if ( ! Good ) { endPacket ( MBB , MI ) ; assert ( ResourceTracker -> canReserveResources ( MI ) ) ; ResourceTracker -> reserveResources ( MI ) ; if ( ExtMI ) { assert ( canReserveResourcesForConstExt ( ) ) ; tryAllocateResourcesForConstExt ( true ) ; } assert ( ResourceTracker -> canReserveResources ( NvjMI ) ) ; ResourceTracker -> reserveResources ( NvjMI ) ; if ( ExtNvjMI


<s> unsigned getBaseRegister ( ) const { return


<s> return ( uint32x4_t ) __builtin_neon_vcgeuv4si ( ( int32x4_t ) __b , ( int32x4_t )


<s> TargetLowering :: CallLoweringInfo CLI ( DAG . getEntryNode ( ) , PtrTy , false , false , false , false , <NUM_LIT> , CallingConv :: C , false , false , true , TlsReadTp , Args , DAG , DL ) ; std :: pair < SDValue , SDValue > CallResult = LowerCallTo ( CLI ) ; ThreadPointer = CallResult . first ; } else { ThreadPointer = DAG . getCopyFromReg ( DAG . getEntryNode ( ) , DL , <STR_LIT> , PtrVT ) ; } return ThreadPointer


<s> const unsigned SubRegIdx1 = std :: get < <NUM_LIT> > ( SubRegIdx ) ; const TargetRegisterClass * SuperRC = getTargetRegisterClass ( CI , Paired ) ; Register SrcReg = MRI -> createVirtualRegister ( SuperRC ) ; const auto * Src0 = TII -> getNamedOperand ( * CI . I , <STR_LIT> :: vdata ) ; const auto * Src1 = TII -> getNamedOperand ( * Paired . I , <STR_LIT> :: vdata ) ; BuildMI ( * MBB , InsertBefore , DL , TII -> get ( <STR_LIT> ) , SrcReg ) . add ( * Src0 ) . addImm ( SubRegIdx0 ) . add ( * Src1 ) . addImm ( SubRegIdx1 ) ; auto MIB = BuildMI ( * MBB , InsertBefore , DL , TII -> get ( Opcode ) ) . addReg ( SrcReg , RegState :: Kill ) ; AddressRegs Regs = getRegs ( Opcode , * TII ) ; if ( Regs . VAddr ) MIB . add ( * TII -> getNamedOperand ( * CI . I , <STR_LIT> :: vaddr ) ) ; unsigned JoinedFormat = getBufferFormatWithCompCount ( CI . Format , CI . Width + Paired . Width , * STM ) ; assert ( CI . I -> hasOneMemOperand ( ) && Paired . I ->


<s> for ( int Shift = <NUM_LIT> ; Shift <= RegWidth - <NUM_LIT> ; Shift += <NUM_LIT> ) if ( ( Value & ~ ( <NUM_LIT>

<< Shift ) ) == <NUM_LIT> ) return true ;


<s> bool isLegalMaskedStore ( Type * DataType , Align Alignment ) { return isLegalMaskedLoadStore ( DataType , Alignment


<s> if ( ! NewOpcode ) { uint64_t NumBytes = Offset - <NUM_LIT> ; emitIncrement ( MBB , MBBI , DL , MBBI -> getOperand ( AddrOpNo ) . getReg ( ) , NumBytes , ZII ) ; Offset -= NumBytes ; NewOpcode = ZII -> getOpcodeForOffset ( Opcode , Offset ) ; assert ( NewOpcode && <STR_LIT> ) ; } MBBI -> setDesc ( ZII -> get ( NewOpcode ) ) ; MBBI -> getOperand ( AddrOpNo + <NUM_LIT> ) . ChangeToImmediate ( Offset ) ; } else if ( StackSize ) { DebugLoc DL = MBBI -> getDebugLoc ( ) ; emitIncrement ( MBB , MBBI , DL , <STR_LIT> , StackSize , ZII


<s> <STR_LIT> getSimpleType ( Type * Ty ) { EVT VT = TLI . getValueType (


<s> const unsigned HOST_WIDE_INT b0 = ( det >> <NUM_LIT> ) & <NUM_LIT> ; const unsigned HOST_WIDE_INT b1 = ( det >> <NUM_LIT> ) & <NUM_LIT> ; const unsigned HOST_WIDE_INT w0 = ( det >> <NUM_LIT> ) & <NUM_LIT> ; const unsigned HOST_WIDE_INT w1 = ( det >> <NUM_LIT> ) & <NUM_LIT> ; int lower_half_easy_p = <NUM_LIT> ; int upper_half_easy_p = <NUM_LIT> ; enum attr_old_cc cc = OLD_CC_CLOBBER ; switch ( mode ) { case E_HImode : if ( b0 != <NUM_LIT> && b1 != <NUM_LIT> ) { cc = OLD_CC_SET_ZNV ; } break ; case E_SImode


<s> int PBPSI = FI -> getPICBasePointerSaveIndex ( ) ; PBPSI = MFI -> CreateFixedObject ( <NUM_LIT> , - <NUM_LIT> , true ) ; FI -> setPICBasePointerSaveIndex ( PBPSI ) ; } int TCSPDelta = <NUM_LIT> ; if ( MF . getTarget ( ) . Options . GuaranteedTailCallOpt && ( TCSPDelta = FI -> getTailCallSPDelta ( ) ) < <NUM_LIT> ) { MFI -> CreateFixedObject ( - <NUM_LIT> * TCSPDelta , TCSPDelta , true ) ; } if ( ! is<ISA_LIT>64 && ! isDarwinABI && ( MRI . isPhysRegUsed ( <STR_LIT> ) || MRI . isPhysRegUsed ( <STR_LIT> ) || MRI . isPhysRegUsed ( <STR_LIT> ) ) ) { int FrameIdx = MFI -> CreateFixedObject ( ( uint64_t ) <NUM_LIT> , ( int64_t ) - <NUM_LIT> , true ) ; FI -> setCRSpillFrameIndex (


<s> uint32_t getTarget<ISA_LIT>Version ( ) const { return


<s> if ( TheTriple . isOSWindows ( ) && TheTriple . isOSBinFormatCOFF ( ) ) return new Windows<ISA_LIT>AsmBackend ( T , false , STI ) ; uint8_t OSABI = MCELFObjectTargetWriter :: getOSABI ( TheTriple . getOS ( ) ) ; if ( TheTriple . isOSIAMCU ( ) ) return new ELF<ISA_LIT>_IAMCUAsmBackend ( T , OSABI , STI ) ; return new ELF<ISA_LIT>_32AsmBackend ( T , OSABI


<s> else { HOST_WIDE_INT rounded_size ; rtx r3 = MIPS_PROLOGUE_TEMP ( Pmode ) ; rtx r12 = MIPS_PROLOGUE_TEMP2 ( Pmode ) ; gcc_assert ( first <= <NUM_LIT> ) ; rounded_size = ROUND_DOWN ( size , PROBE_INTERVAL ) ; emit_insn ( gen_rtx_SET ( r3 , plus_constant ( Pmode , stack_pointer_rtx , - first ) ) ) ; if ( rounded_size > <NUM_LIT> ) { emit_move_insn ( r12 , GEN_INT


<s> void <ISA_LIT>InstPrinter :: printPostIndRegOperand ( const MCInst * MI , unsigned OpNo , raw_ostream & O ) { const MCOperand & Base = MI -> getOperand ( OpNo ) ; O << <STR_LIT> << getRegisterName ( Base . getReg


<s> static bool IsDirectBranch ( const MachineInstr


<s> RegisterMCAsmInfoFn X ( The<ISA_LIT>Target , create<ISA_LIT>MCAsmInfo ) ; TargetRegistry :: RegisterMCInstrInfo ( The<ISA_LIT>Target , create<ISA_LIT>MCInstrInfo ) ; TargetRegistry :: RegisterMCRegInfo ( The<ISA_LIT>Target , create<ISA_LIT>MCRegisterInfo ) ; TargetRegistry :: RegisterMCSubtargetInfo ( The<ISA_LIT>Target , create<ISA_LIT>MCSubtargetInfo ) ; TargetRegistry :: RegisterMCInstPrinter ( The<ISA_LIT>Target , create<ISA_LIT>MCInstPrinter


<s> if ( ! DisableCTRLoops && getOptLevel ( ) != CodeGenOpt :: None ) addPass (

create<ISA_LIT>CTRLoops ( get<ISA_LIT>TargetMachine ( ) ) ) ;


<s> void <ISA_LIT>GNULDBackend :: initTargetSymbols ( IRBuilder & pBuilder , Module & pModule ) { if ( LinkerConfig :: Object != config ( ) . codeGenType ( ) ) { m_pGOTSymbol = pBuilder . AddSymbol < IRBuilder :: AsReferred , IRBuilder :: Resolve > ( <STR_LIT> , ResolveInfo :: Object , ResolveInfo :: Define , ResolveInfo :: Local , <NUM_LIT> , <NUM_LIT> , FragmentRef :: Null ( ) ,


<s> return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return


<s> SDValue <ISA_LIT>TargetLowering :: PerformDAGCombine ( SDNode * N , DAGCombinerInfo & DCI ) const { CodeGenOpt :: Level OptLevel = getTargetMachine ( ) . getOptLevel ( ) ; switch ( N -> getOpcode ( ) ) { default : break ; case <STR_LIT> : case <STR_LIT> : return PerformADDCombine ( N , DCI , nvptxSubtarget , OptLevel ) ; case


<s> if ( TARGET_THUMB ) memcpy ( reg_alloc_order , thumb_core_reg_alloc_order

, sizeof ( thumb_core_reg_alloc_order ) ) ;


<s> if ( getSTI ( ) . getTargetTriple ( ) . getOS ( ) != Triple :: AMDPAL ) { return Error ( getLoc ( ) , ( Twine ( PALMD :: AssemblerDirective ) + Twine ( <STR_LIT> <STR_LIT> ) ) . str ( ) ) ; } auto PALMetadata = getTargetStreamer ( ) . getPALMetadata ( ) ; PALMetadata -> setLegacy ( ) ; for ( ; ; ) { uint32_t Key , Value ; if ( ParseAsAbsoluteExpression ( Key ) ) { return TokError ( Twine ( <STR_LIT> ) + Twine ( PALMD ::


<s> NumIntermediates = VT . getSizeInBits ( ) < RegisterVT . getSizeInBits ( ) ? VT . getVectorNumElements ( ) : VT . getSizeInBits ( ) / RegisterVT . getSizeInBits ( ) ; return NumIntermediates


<s> static int forward_branch_p ( rtx insn ) { rtx label = JUMP_LABEL ( insn ) ; while ( insn ) { if ( insn == label


<s> return ( __m512 ) __builtin_ia32_expandloadsf512_maskz ( ( const __v16sf * ) __P ,


<s> const char * name ; FILE * f = asm_out_file ; gcc_assert ( MEM_P ( DECL_RTL ( current_function_decl ) ) ) ; gcc_assert ( GET_CODE ( XEXP ( DECL_RTL ( current_function_decl ) , <NUM_LIT> ) ) == SYMBOL_REF ) ; name = XSTR ( XEXP ( DECL_RTL ( current_function_decl )


<s> if ( candidate == MBB . begin ( ) ) return false ; if ( candidate -> getOpcode ( ) == <STR_LIT> ) return true ; const MCInstrDesc & prevdesc = ( -- candidate ) -> getDesc ( ) ; return prevdesc .


<s> return createMachObjectWriter ( llvm :: make_unique < <ISA_LIT>MachObjectWriter > ( Is64Bit ,


<s> if ( ! ST -> hasMVEIntegerOps ( ) ) return false ; if ( L -> getNumBlocks ( ) > <NUM_LIT> ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> <STR_LIT> ) ; return false ; } assert ( L -> empty ( ) && <STR_LIT> ) ; HardwareLoopInfo HWLoopInfo ( L ) ; if ( ! HWLoopInfo . canAnalyze ( * LI ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> <STR_LIT> ) ; return false


<s> bool <ISA_LIT>AsmParser :: ParseRegister ( unsigned & RegNo , SMLoc & StartLoc


<s> virtual const <ISA_LIT>TargetLowering * getTargetLowering ( ) const { return &


<s> file_format -> getRelaPlt ( ) . setSize ( m_pRelaPLT -> numOfRelocs (


<s> SDValue Hi = Op . getOperand ( <NUM_LIT> ) ; if ( VecVT . isFixedLengthVector ( ) ) { MVT ContainerVT = getContainerForFixedLengthVector ( VecVT ) ; SDLoc DL ( Op ) ; SDValue Mask , VL ; std :: tie ( Mask , VL ) = getDefaultVLOps ( VecVT , ContainerVT , DL , DAG , Subtarget ) ; SDValue Res = splatPartsI64WithVL ( DL , ContainerVT , SDValue ( ) , Lo , Hi , VL , DAG ) ; return convertFromScalableVector ( VecVT , Res , DAG , Subtarget ) ; } if ( isa < ConstantSDNode > ( Lo ) && isa < ConstantSDNode > ( Hi ) ) { int32_t LoC = cast < ConstantSDNode > ( Lo ) -> getSExtValue ( ) ; int32_t HiC = cast < ConstantSDNode > ( Hi ) -> getSExtValue ( ) ; if ( ( LoC >> <NUM_LIT> ) == HiC ) return DAG . getNode ( <STR_LIT> , DL , VecVT , DAG . getUNDEF ( VecVT ) , Lo , DAG . getRegister


<s> if ( TT . isArch64Bit ( ) && FeatureBits [ <STR_LIT> ] ) report_fatal_error (


<s> unsigned <ISA_LIT>InstrInfo :: getFiFromFiMalkrz ( unsigned Opc ) const { switch ( Opc ) { default : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> return In64BitMode && ( ! TargetTriple . isX32 ( ) &&


<s> const Value * SV = cast < SrcValueSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getValue ( ) ; return DAG . getStore ( Op . getOperand ( <NUM_LIT> ) , dl , FI , Op . getOperand ( <NUM_LIT>

) , MachinePointerInfo ( SV ) , false , false , <NUM_LIT> ) ;


<s> if ( ! MemOp . isUnordered ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } if ( MemOp . getAlign ( ) < Ty . getSizeInBits ( ) / <NUM_LIT> ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } } unsigned NewOpc = getLoadStoreOp ( Ty , RB , Opc , MemOp . getAlign ( ) ) ; if ( NewOpc == Opc ) return false ; <ISA_LIT>AddressMode AM ; <ISA_LIT>SelectAddress ( * MRI . getVRegDef ( I . getOperand ( <NUM_LIT> ) . getReg ( ) ) , MRI , AM ) ; I . setDesc ( TII . get ( NewOpc ) ) ; MachineInstrBuilder MIB ( MF , I ) ; if ( Opc == TargetOpcode ::


<s> Reg = mapper . fromString ( RegString -> getString ( ) , Subtarget -> getFeatureBits ( ) , IsValidSpecialReg ) ; if ( IsValidSpecialReg ) return CurDAG -> getMachineNode ( <STR_LIT> , DL , N -> getSimpleValueType ( <NUM_LIT> ) , <STR_LIT> , CurDAG -> getTargetConstant ( Reg , DL , <STR_LIT> ) , N -> getOperand ( <NUM_LIT> ) ) ; return


<s> BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) ) ; BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) ) . addReg ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; MI . eraseFromParent ( ) ; LLVM_DEBUG ( BB -> dump ( ) ) ; return


<s> SDValue GOT = DAG . getGLOBAL_OFFSET_TABLE ( <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , GOT , GPRelNode ) ; } SDValue GA = DAG . getTargetGlobalAddress ( GV , <STR_LIT> , <NUM_LIT> , <STR_LIT> ) ; SDValue HiPart = DAG . getNode ( <STR_LIT> , dl , VTs , & GA , <NUM_LIT> ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , GA ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , HiPart , Lo ) ; } else { SDValue GA = DAG . getTargetGlobalAddress ( GV , <STR_LIT> , <NUM_LIT> , <STR_LIT> ) ; SDValue ResNode = DAG . getLoad ( <STR_LIT> , dl , DAG . getEntryNode ( ) , GA , NULL , <NUM_LIT> , false


<s> void setPriority ( PriorityFunction p ) { PF =


<s> OS << <STR_LIT> << getSGPRNum ( ) ; if ( ST ) OS << <STR_LIT> << ST -> getOccupancyWithNumSGPRs ( getSGPRNum ( ) ) << ')' ; OS << <STR_LIT> << getVGPRTuplesWeight ( ) << <STR_LIT> << getSGPRTuplesWeight ( ) ; if ( ST ) OS << <STR_LIT> << getOccupancy ( * ST


<s> rtx reg = XEXP ( src , <NUM_LIT> ) ; rtx prev_dest = SET_DEST ( prev_set ) ; rtx prev_src = SET_SRC ( prev_set ) ; bool src_same = rtx_equal_p ( prev_src , reg ) ; if ( REG_P ( prev_dest ) && ! reg_set_p ( reg , prev_src ) && ! reg_set_between_p ( reg , prev_cc_outer , outer_insn ) && ( src_same || rtx_equal_p ( prev_dest , reg ) ) ) { machine_mode ccmode = GET_MODE ( src ) ; rtx modeadjusted_dccr = ( ccmode == CCmode ? dccr : gen_rtx_REG ( CCmode , CRIS_CC0_REGNUM ) ) ; rtx compare = ( src_same ? pat : gen_rtx_SET ( modeadjusted_dccr , gen_rtx_COMPARE ( ccmode , copy_rtx ( prev_src ) , const0_rtx ) ) ) ; validate_change ( prev_cc_setter , & XVECEXP ( PATTERN ( prev_cc_setter ) , <NUM_LIT> , <NUM_LIT> ) , compare ,


<s> StringRef getPassName ( ) const override { return FIXUPBW_DESC


<s> pat = PATTERN ( insn ) ; if ( GET_CODE ( pat ) == PARALLEL ) pat = XVECEXP ( pat , <NUM_LIT> , <NUM_LIT> ) ; if ( GET_CODE ( pat ) != SET || SET_DEST ( pat ) != pc_rtx ) continue ; if ( GET_CODE ( SET_SRC ( pat ) ) == LABEL_REF ) { label = & SET_SRC ( pat ) ; } else if ( GET_CODE ( SET_SRC ( pat ) ) == IF_THEN_ELSE ) { if ( GET_CODE ( XEXP ( SET_SRC ( pat ) , <NUM_LIT> ) ) == LABEL_REF ) label = & XEXP ( SET_SRC ( pat ) , <NUM_LIT> ) ; else if ( GET_CODE ( XEXP ( SET_SRC ( pat ) , <NUM_LIT> ) ) == LABEL_REF ) label = & XEXP ( SET_SRC ( pat ) , <NUM_LIT> ) ; else continue ; } else continue ; if ( get_attr_length ( insn ) <= <NUM_LIT> ) continue ; cfun_frame_layout . save_return_addr_p = <NUM_LIT> ; if ( ! flag_pic ) { new_literal = <NUM_LIT> ; rtx mem = force_const_mem ( Pmode , * label ) ; rtx_insn * set_insn = emit_insn_before ( gen_rtx_SET ( temp_reg , mem ) , insn ) ; INSN_ADDRESSES_NEW ( set_insn , -


<s> if ( RegNo > <NUM_LIT> ) return MCDisassembler :: Fail ; unsigned Reg = DFPRegDecoderTable [ RegNo ] ; Inst . addOperand ( MCOperand :: createReg ( Reg


<s> inline int vec_any_nan ( vector float a1


<s> if ( <ISA_LIT>ArchVersion == <ISA_LIT>5 ) report_fatal_error ( <STR_LIT> , false ) ; assert ( <ISA_LIT>ABI != UnknownABI ) ; assert ( ( ( ( getFeatureBits ( ) & <STR_LIT> ) != <NUM_LIT> ) + ( ( getFeatureBits ( ) & <STR_LIT> ) != <NUM_LIT> ) + ( ( getFeatureBits ( ) & <STR_LIT> ) != <NUM_LIT> ) + ( ( getFeatureBits ( ) & <STR_LIT> ) != <NUM_LIT> ) ) == <NUM_LIT> ) ; assert ( ( ( ! isGP64bit ( ) && ( isABI_O32 ( ) || isABI_EABI ( ) ) ) || ( isGP64bit ( ) && ( isABI_N32 ( ) || isABI_N64 ( ) ) ) ) && <STR_LIT> ) ; if ( hasMSA ( ) && ! isFP64bit ( ) ) report_fatal_error ( <STR_LIT> <STR_LIT> , false ) ; if ( ! isABI_O32 ( ) && ! useOddSPReg ( ) ) report_fatal_error ( <STR_LIT> , false ) ; if ( IsFPXX && ( isABI_N32 ( ) || isABI_N64 ( )


<s> bool isBGP ( ) const { return TargetTriple . getVendor ( ) == Triple ::


<s> const std :: string & <ISA_LIT>LongBranchStub :: name ( ) const { return


<s> const GCNSubtarget & ST = DAGInstrs -> MF . getSubtarget < GCNSubtarget > ( ) ; TII = ST . getInstrInfo ( ) ; if ( ! ST . hasMAIInsts ( ) ) return ; DAG = static_cast < ScheduleDAGMI * > ( DAGInstrs ) ; const TargetSchedModel * TSchedModel = DAGInstrs -> getSchedModel ( ) ; if ( ! TSchedModel || DAG -> SUnits . empty ( ) ) return ; const IsInstructionType isMFMAFn = [ this ] ( const MachineInstr & MI ) { if ( TII -> isMAI ( MI ) && MI . getOpcode ( ) != <STR_LIT> && MI . getOpcode ( ) != <STR_LIT> ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; ) ; return true ; } return false ; } ; InstructionClass MFMASUnits ( isMFMAFn , MFMAGroupMaxSize ) ; const IsInstructionType isVMEMReadFn = [ this ] ( const MachineInstr & MI ) { if ( ( ( TII -> isFLAT ( MI ) && ! TII -> isDS ( MI ) ) || TII -> isVMEM ( MI ) ) && MI . mayLoad ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; ) ; return true ; } return false ; } ; InstructionClass VMEMReadSUnits ( isVMEMReadFn , VMEMGroupMaxSize ) ; const IsInstructionType isDSWriteFn = [ this ] ( const MachineInstr & MI ) { if ( TII -> isDS ( MI ) && MI . mayStore ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; ) ; return true ; } return false ; } ; InstructionClass DSWriteSUnits ( isDSWriteFn , LDWGroupMaxSize ) ; const IsInstructionType isDSReadFn = [ this ] ( const


<s> const MCSubtargetInfo & STI = Dis -> getSubtargetInfo ( ) ; Imm |= <NUM_LIT> ; Inst . addOperand ( MCOperand :: CreateImm ( Imm ) ) ; bool ValidNamed ; ( void ) <STR_LIT> ( STI . getFeatureBits ( ) ) . toString ( Imm


<s> assert ( ! isSoloInstruction ( MI ) && <STR_LIT> ) ; if ( MI -> isDebugValue ( ) ) { return true ; } else { assert ( ResourceTracker -> getInstrItins ( ) -> beginStage ( MI -> getDesc (

) . getSchedClass ( ) ) -> getUnits ( ) && <STR_LIT> ) ;


<s> for ( unsigned i = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i ) { CCValAssign & VA = RVLocs [ i ] ; assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; Chain = DAG . getCopyToReg ( Chain , DL , VA . getLocReg ( ) , OutVals [ i ] , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( VA . getLocReg ( ) , VA . getLocVT ( ) ) ) ; } if ( DAG . getMachineFunction ( ) . getFunction ( ) . hasStructRetAttr ( ) ) { MachineFunction & MF = DAG . getMachineFunction ( ) ; <ISA_LIT>MachineFunctionInfo * <ISA_LIT>MFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; Register Reg = <ISA_LIT>MFI -> getSRetReturnReg ( ) ; assert ( Reg && <STR_LIT>


<s> unsigned MaxDisp = getUnconditionalBrDisp ( UncondBr ) ; ImmBranches . push_back ( ImmBranch ( & UserMBB -> back ( ) , MaxDisp , false , UncondBr ) ) ; computeBlockSize ( UserMBB ) ; adjustBBOffsetsAfter ( UserMBB ) ; return ; } } unsigned LogAlign = MF -> getAlignment ( ) ; assert ( LogAlign >= CPELogAlign && <STR_LIT> ) ; unsigned KnownBits = UserBBI . internalKnownBits ( ) ; unsigned UPad = UnknownPadding ( LogAlign , KnownBits ) ; unsigned BaseInsertOffset = UserOffset + U . getMaxDisp ( ) - UPad ; DEBUG ( dbgs ( ) << format ( <STR_LIT> , BaseInsertOffset ) ) ; BaseInsertOffset -= <NUM_LIT> ; DEBUG ( dbgs ( ) << format ( <STR_LIT> , BaseInsertOffset ) << <STR_LIT> << LogAlign << <STR_LIT> << KnownBits << <STR_LIT> << UPad << '\n' ) ; if ( BaseInsertOffset + <NUM_LIT> >= UserBBI . postOffset ( ) ) { BaseInsertOffset = std :: max ( UserBBI . postOffset ( ) - UPad - <NUM_LIT> , UserOffset + TII -> GetInstSizeInBytes ( UserMI ) + <NUM_LIT> ) ; DEBUG ( dbgs ( ) << format ( <STR_LIT> , BaseInsertOffset ) ) ; } unsigned EndInsertOffset = BaseInsertOffset + <NUM_LIT> + UPad + CPEMI -> getOperand (


<s> else if ( ClUncheckedLdSt == UncheckedAlways ) return true ; unsigned FrameSize = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> , e = MFI -> getObjectIndexEnd ( ) ; i != e ;

++ i ) FrameSize += MFI -> getObjectSize ( i ) ;


<s> MaxInterleaveFactor = <NUM_LIT> ; MinVectorRegisterBitWidth = <NUM_LIT> ; CacheLineSize = <NUM_LIT> ; PrefetchDistance = <NUM_LIT> ; MinPrefetchStride = <NUM_LIT> ; MaxPrefetchIterationsAhead = <NUM_LIT> ; break ; case Kryo : MaxInterleaveFactor = <NUM_LIT> ; VectorInsertExtractBaseCost = <NUM_LIT> ; CacheLineSize = <NUM_LIT> ; PrefetchDistance = <NUM_LIT> ; MinPrefetchStride = <NUM_LIT> ; MaxPrefetchIterationsAhead = <NUM_LIT> ; MinVectorRegisterBitWidth = <NUM_LIT> ; break ; case NeoverseE1 : PrefFunctionLogAlignment = <NUM_LIT> ; break ; case NeoverseN1 : PrefFunctionLogAlignment = <NUM_LIT> ; break ; case Saphira : MaxInterleaveFactor = <NUM_LIT> ; MinVectorRegisterBitWidth = <NUM_LIT> ; break ; case ThunderX2T99 : CacheLineSize = <NUM_LIT> ; PrefFunctionLogAlignment = <NUM_LIT> ; PrefLoopLogAlignment = <NUM_LIT> ; MaxInterleaveFactor = <NUM_LIT> ; PrefetchDistance = <NUM_LIT> ; MinPrefetchStride = <NUM_LIT> ; MaxPrefetchIterationsAhead =


<s> Register dm_off_reg = MBBI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; Register addr_bound = MRI . createVirtualRegister ( & <STR_LIT> ) ; Register addr_stride = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) , addr_bound ) . addReg ( dm_off_reg ) . addImm ( ( ( <NUM_LIT> + ( dim - <NUM_LIT> ) ) << <NUM_LIT> ) ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) , addr_stride ) . addReg ( dm_off_reg ) . addImm ( ( ( <NUM_LIT> + ( dim - <NUM_LIT> ) ) << <NUM_LIT> ) ) ; Register BoundReg = MBBI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) ) . addReg ( BoundReg ) . addReg ( addr_bound , RegState :: Kill ) ; Register StrideReg = MBBI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) ) . addReg ( StrideReg ) . addReg ( addr_stride , RegState :: Kill ) ; MBBI -> eraseFromParent ( ) ; return


<s> term = XEXP ( x , <NUM_LIT> ) ; if ( has_hard_reg_initial_val ( Pmode , TP_REGNO ) && base == mep_tp_rtx ( ) ) unspec = UNS_TPREL ; else if ( has_hard_reg_initial_val ( Pmode , GP_REGNO ) && base == mep_gp_rtx ( ) ) unspec = UNS_GPREL ; else return x ; if ( GET_CODE ( term ) != CONST ) return x ; term = XEXP ( term , <NUM_LIT> ) ; if ( GET_CODE ( term ) != UNSPEC || XINT ( term , <NUM_LIT> ) != unspec ) return x ; return XVECEXP ( term , <NUM_LIT> ,


<s> if ( sh_symbian_dllexport_p ( decl ) ) sh_symbian_mark_dllexport ( decl ) ; else if ( sh_symbian_dllimport_p ( decl ) ) sh_symbian_mark_dllimport ( decl ) ; else if ( ( TREE_CODE ( decl ) == FUNCTION_DECL || TREE_CODE ( decl ) == VAR_DECL ) && DECL_RTL ( decl ) != NULL_RTX && GET_CODE ( DECL_RTL ( decl ) ) == MEM && GET_CODE ( XEXP ( DECL_RTL ( decl ) , <NUM_LIT> ) ) == MEM && GET_CODE ( XEXP ( XEXP ( DECL_RTL ( decl ) , <NUM_LIT> ) , <NUM_LIT> ) ) == SYMBOL_REF && sh_symbian_dllimport_name_p (

XSTR ( XEXP ( XEXP ( DECL_RTL ( decl ) , <NUM_LIT> ) , <NUM_LIT> ) , <NUM_LIT> ) ) ) {


<s> static const unsigned RegClassIDs [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> } ; static const unsigned SubRegs [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT>


<s> const unsigned Imm16 = getChunk ( UImm , ChunkIdx ) ; const unsigned DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; const bool DstIsDead = MI . getOperand ( <NUM_LIT> ) . isDead ( ) ; MachineInstrBuilder MIB1 = BuildMI ( MBB , MBBI , MI . getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addReg ( DstReg , RegState :: Define | getDeadRegState ( DstIsDead ) ) . addReg ( DstReg ) . addImm ( Imm16 ) . addImm ( <STR_LIT> ( <STR_LIT> , ShiftAmt ) ) ; transferImpOps ( MI , MIB , MIB1 ) ; MI . eraseFromParent ( )


<s> void <ISA_LIT>WinCOFFStreamer :: emitWinEHHandlerData ( SMLoc Loc ) { MCStreamer :: emitWinEHHandlerData


<s> bool <ISA_LIT>CallLowering :: lowerReturn ( MachineIRBuilder & MIRBuilder , const Value * Val , unsigned VReg ) const { assert ( ! Val == ! VReg && <STR_LIT> ) ; auto Ret = AddDefaultPred ( MIRBuilder . buildInstrNoInsert ( <STR_LIT>


<s> EVT PtrVT = getTargetLowering ( ) -> getPointerTy ( CurDAG -> getDataLayout ( ) ) ; Base = CurDAG -> getTargetFrameIndex ( FIN -> getIndex ( ) , PtrVT ) ; Offset = CurDAG -> getTargetConstant ( <NUM_LIT>


<s> static bool signBitIsZero ( const MachineOperand &

Op , const MachineRegisterInfo & MRI ) {


<s> static bool isSignExtended ( SDNode * N , SelectionDAG & DAG ) { return N -> getOpcode ( ) == <STR_LIT> || isExtendedBUILD_VECTOR ( N ,


<s> return CheckImmRange ( <NUM_LIT> + <NUM_LIT> , <NUM_LIT> , true ,


<s> const TargetRegisterClass * RC = RI . getCommonSubClass ( MRI . getRegClass ( TrueReg ) , MRI . getRegClass ( FalseReg ) ) ; if ( ! RC ) return false ; unsigned ExtraCondLat = Cond . size ( ) != <NUM_LIT> ; if ( <STR_LIT> . hasSubClassEq ( RC ) || <STR_LIT> . hasSubClassEq ( RC ) ) { CondCycles = <NUM_LIT> + ExtraCondLat ; TrueCycles = FalseCycles = <NUM_LIT> ; if ( canFoldIntoCSel ( MRI , TrueReg ) ) TrueCycles = <NUM_LIT> ; else if ( canFoldIntoCSel ( MRI , FalseReg ) ) FalseCycles = <NUM_LIT> ; return true


<s> if ( ! Match ) continue ; if ( Match . getScalarValueSizeInBits ( ) != BitWidth ) continue ; unsigned MatchSizeInBits = Match . getValueSizeInBits ( ) ; if ( ! ( MatchSizeInBits == <NUM_LIT> || ( MatchSizeInBits == <NUM_LIT> && ( ( Subtarget . hasAVX ( ) && BitWidth >= <NUM_LIT> ) || Subtarget . hasAVX2 ( ) ) ) ) ) return SDValue ( ) ; if ( Match . getValueType ( ) . getVectorNumElements ( ) <= <NUM_LIT> ) return SDValue ( ) ; if ( DAG . ComputeNumSignBits ( Match ) != BitWidth ) return SDValue ( ) ; MVT MaskVT ; if ( <NUM_LIT> == BitWidth || <NUM_LIT> == BitWidth ) MaskVT = <STR_LIT> ( <STR_LIT> ( BitWidth ) , MatchSizeInBits / BitWidth ) ; else MaskVT = <STR_LIT> ( <STR_LIT> , MatchSizeInBits / <NUM_LIT> ) ; APInt CompareBits ; <STR_LIT> CondCode ; if ( Op == <STR_LIT> ) { CompareBits = APInt :: getNullValue ( <NUM_LIT> ) ; CondCode = <STR_LIT> :: SETNE ; } else { CompareBits = APInt :: getLowBitsSet ( <NUM_LIT> , MaskVT . getVectorNumElements ( ) ) ; CondCode = <STR_LIT> :: SETEQ ; } unsigned ResWidth = std :: max ( BitWidth , <NUM_LIT> ) ; APInt ResOnes = APInt :: getAllOnesValue ( ResWidth ) ; APInt ResZero = APInt :: getNullValue ( ResWidth ) ; EVT ResVT = EVT :: getIntegerVT ( * DAG . getContext ( ) , ResWidth ) ; SDLoc DL ( Extract ) ; SDValue Res = DAG . getBitcast


<s> bool FourReg = NumOps > <NUM_LIT> && OpInfo [ <NUM_LIT> ] . RegClass == <STR_LIT> ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , decodeRs ( insn ) ) ) ) ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , decodeRn ( insn ) ) ) ) ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , decodeRm ( insn ) ) ) ) ; if ( FourReg ) MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , decodeRd ( insn ) ) ) ) ; NumOpsAdded = FourReg ? <NUM_LIT> : <NUM_LIT> ; return


<s> if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rm , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! align ) Inst . addOperand ( MCOperand :: createImm ( <NUM_LIT> ) ) ; else Inst . addOperand ( MCOperand :: createImm ( <NUM_LIT> << align


<s> insertDAGNode ( * CurDAG , OrigShiftAmt , X ) ; } else return false ; SDValue Zero = CurDAG -> getConstant ( <NUM_LIT> , DL , SubVT ) ; SDValue Neg = CurDAG -> getNode ( <STR_LIT> , DL , SubVT , Zero , X ) ; NewShiftAmt = Neg ; insertDAGNode ( * CurDAG , OrigShiftAmt , Zero ) ; insertDAGNode ( * CurDAG , OrigShiftAmt , Neg ) ; } else return false ; } else return false ; if ( NewShiftAmt . getValueType ( ) != <STR_LIT> ) { NewShiftAmt = CurDAG -> getNode ( <STR_LIT> , DL , <STR_LIT> , NewShiftAmt ) ; insertDAGNode ( * CurDAG , OrigShiftAmt , NewShiftAmt ) ; } NewShiftAmt = CurDAG -> getNode ( <STR_LIT> , DL , <STR_LIT> , NewShiftAmt , CurDAG -> getConstant ( Size - <NUM_LIT> , DL , <STR_LIT> ) ) ; insertDAGNode ( * CurDAG , OrigShiftAmt , NewShiftAmt ) ; SDNode * UpdatedNode = CurDAG -> UpdateNodeOperands ( N , N -> getOperand ( <NUM_LIT> ) , NewShiftAmt ) ; if ( UpdatedNode != N ) { ReplaceNode ( N , UpdatedNode ) ; return true ; } if ( OrigShiftAmt . getNode ( ) -> use_empty ( ) ) CurDAG -> RemoveDeadNode ( OrigShiftAmt . getNode ( ) ) ; SelectCode ( N ) ; return true