<s> if ( const auto * ZExt = dyn_cast < ZExtInst > ( Op0 ) ) { MVT TmpVT ; if ( isValueAvailable ( ZExt ) && isTypeSupported ( ZExt -> getSrcTy ( ) , TmpVT ) ) { SrcVT = TmpVT ; IsZExt = true ; Op0 = ZExt -> getOperand ( <NUM_LIT> ) ; } } else if ( const auto * SExt = dyn_cast < SExtInst > ( Op0 ) ) { MVT TmpVT ; if ( isValueAvailable ( SExt ) && isTypeSupported ( SExt -> getSrcTy ( ) , TmpVT ) ) { SrcVT = TmpVT ; IsZExt = false ; Op0 = SExt -> getOperand ( <NUM_LIT> ) ; } } unsigned Op0Reg = getRegForValue ( Op0 ) ; if ( ! Op0Reg ) return false ; bool Op0IsKill = hasTrivialKill ( Op0 ) ; switch ( I -> getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case Instruction :: Shl : ResultReg = emitLSL_ri ( RetVT , SrcVT , Op0Reg , Op0IsKill , ShiftVal , IsZExt ) ; break ; case Instruction :: AShr : ResultReg = emitASR_ri ( RetVT , SrcVT , Op0Reg , Op0IsKill , ShiftVal , IsZExt ) ; break ; case Instruction :: LShr : ResultReg = emitLSR_ri ( RetVT , SrcVT , Op0Reg , Op0IsKill , ShiftVal , IsZExt ) ; break ; } if ( ! ResultReg ) return false ; updateValueMap ( I , ResultReg ) ; return true ; } unsigned Op0Reg = getRegForValue ( I -> getOperand ( <NUM_LIT> ) ) ; if ( ! Op0Reg ) return false ; bool Op0IsKill = hasTrivialKill ( I -> getOperand ( <NUM_LIT> ) ) ; unsigned Op1Reg = getRegForValue ( I -> getOperand ( <NUM_LIT> ) ) ; if ( ! Op1Reg ) return false ; bool Op1IsKill = hasTrivialKill ( I -> getOperand ( <NUM_LIT> ) ) ; unsigned ResultReg = <NUM_LIT> ; switch ( I -> getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case Instruction :: Shl : ResultReg = emitLSL_rr ( RetVT , Op0Reg , Op0IsKill , Op1Reg ,


<s> PreAnalyzeCallOperands ( Outs , FuncArgs , Func ) ; CCState :: AnalyzeCallOperands ( Outs , Fn ) ; OriginalArgWasF128 . clear ( ) ; OriginalArgWasFloat . clear (


<s> if ( skipFunction ( F ) ) return false ; if ( auto * TPC = getAnalysisIfAvailable < TargetPassConfig > ( ) ) { return promoteAllocasToVector ( F , TPC ->


<s> static bool bpf_rtx_costs ( rtx x ATTRIBUTE_UNUSED , enum machine_mode mode ATTRIBUTE_UNUSED , int outer_code ATTRIBUTE_UNUSED , int opno ATTRIBUTE_UNUSED , int * total ATTRIBUTE_UNUSED , bool speed ATTRIBUTE_UNUSED ) { return


<s> bool fixupNeedsRelaxation ( const MCFixup & Fixup , uint64_t Value , const MCRelaxableFragment * DF , const MCAsmLayout


<s> void <ISA_LIT>InstPrinter :: printAddrMode7Operand ( const MCInst * MI ,


<s> SDValue Chain = Node -> getOperand ( <NUM_LIT> ) ; SDValue VAListPtr = Node -> getOperand ( <NUM_LIT> ) ; unsigned Align = Node -> getConstantOperandVal ( <NUM_LIT> ) ; const Value * SV = cast < SrcValueSDNode > ( Node -> getOperand ( <NUM_LIT> ) ) -> getValue ( ) ; SDLoc DL ( Node ) ; unsigned ArgSlotSizeInBytes = ( ABI . IsN32 ( ) || ABI . IsN64 ( ) ) ? <NUM_LIT> : <NUM_LIT> ; SDValue VAListLoad = DAG . getLoad ( getPointerTy ( DAG . getDataLayout ( ) ) , DL , Chain , VAListPtr , MachinePointerInfo ( SV ) ) ; SDValue VAList = VAListLoad ; if ( Align > getMinStackArgumentAlignment ( ) ) { assert ( ( ( Align & ( Align - <NUM_LIT> ) ) == <NUM_LIT> ) && <STR_LIT> ) ; VAList = DAG . getNode ( <STR_LIT> , DL , VAList . getValueType ( ) , VAList , DAG . getConstant ( Align - <NUM_LIT> , DL , VAList . getValueType ( ) ) ) ; VAList = DAG . getNode ( <STR_LIT> , DL , VAList . getValueType ( ) , VAList , DAG . getConstant ( - ( int64_t ) Align , DL , VAList . getValueType ( ) ) ) ; } auto & TD = DAG . getDataLayout ( ) ; unsigned ArgSizeInBytes = TD . getTypeAllocSize ( VT . getTypeForEVT ( * DAG . getContext ( ) ) ) ; SDValue Tmp3 = DAG . getNode ( <STR_LIT> , DL , VAList . getValueType ( ) , VAList , DAG . getConstant ( alignTo ( ArgSizeInBytes , ArgSlotSizeInBytes ) , DL


<s> EVT ExtraVT = cast < VTSDNode > ( N1 ) -> getVT ( ) ; if ( ExtraVT != <STR_LIT> ) return SDValue ( ) ; if ( N0 . getOpcode ( ) == <STR_LIT> && N0 . hasOneUse ( ) ) N0 = N0 . getOperand ( <NUM_LIT> ) ; if ( N0 . getOpcode ( ) != <STR_LIT> || ! N0 . hasOneUse ( ) ) return SDValue ( ) ; SDValue CMovOp0 = N0 . getOperand ( <NUM_LIT> ) ; SDValue CMovOp1 = N0 . getOperand ( <NUM_LIT> ) ; if ( ! isa < ConstantSDNode > ( CMovOp0 . getNode ( ) ) || ! isa

< ConstantSDNode > ( CMovOp1 . getNode ( ) ) ) return SDValue ( ) ;


<s> return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> switch ( GET_MODE_CLASS ( mode ) ) { case MODE_PARTIAL_INT : case MODE_INT : if ( precision == CHAR_TYPE_SIZE ) return true ; if ( precision == SHORT_TYPE_SIZE ) return true ; if ( precision == INT_TYPE_SIZE )


<s> <ISA_LIT>FunctionInfo * AFI = const_cast < MachineFunction * > ( & MF ) -> getInfo < <ISA_LIT>FunctionInfo > ( ) ; if ( AFI -> getArgRegsSaveSize ( ) ) return true ; bool IsV4PopReturn = false ; for ( const CalleeSavedInfo & CSI : MF . getFrameInfo ( ) -> getCalleeSavedInfo ( ) ) if ( CSI . getReg ( ) == <STR_LIT> ) IsV4PopReturn = true ; return IsV4PopReturn && STI . hasV4TOps ( ) && ! STI .


<s> void <ISA_LIT>PassConfig :: addPreEmitPass ( ) { if ( getOptLevel ( ) != CodeGenOpt :: None ) addPass ( create<ISA_LIT>EarlyReturnPass ( ) , false ) ; addPass ( create<ISA_LIT>BranchSelectionPass ( )


<s> tree idp ; rtx rtlname , newrtl ; rtx symref ; rtlname = XEXP ( DECL_RTL ( decl ) , <NUM_LIT> ) ; if ( GET_CODE ( rtlname ) == MEM ) rtlname = XEXP ( rtlname , <NUM_LIT> ) ; gcc_assert ( GET_CODE ( rtlname ) == SYMBOL_REF ) ; oldname = XSTR ( rtlname , <NUM_LIT> ) ; if ( i386_pe_dllexport_name_p ( oldname ) ) { error ( <STR_LIT> , IDENTIFIER_POINTER ( DECL_NAME ( decl ) ) ) ; return ; } else if ( i386_pe_dllimport_name_p ( oldname ) ) { gcc_assert ( DECL_EXTERNAL ( decl ) && TREE_PUBLIC ( decl ) && DECL_DLLIMPORT_P ( decl ) ) ; return ; } newname = alloca ( strlen ( DLL_IMPORT_PREFIX ) + strlen ( oldname ) +


<s> return false ; case InlineAsm :: Constraint_ZC : if ( Subtarget -> inMicro<ISA_LIT>Mode ( ) ) { if ( selectAddrRegImm12 ( Op , Base , Offset ) ) { OutOps . push_back ( Base ) ; OutOps . push_back ( Offset ) ; return false ; } } else if ( Subtarget -> has<ISA_LIT>32r6 ( ) ) { if ( selectAddrRegImm9 ( Op , Base , Offset ) ) { OutOps . push_back ( Base ) ; OutOps . push_back ( Offset ) ; return false ; } } else if ( selectAddrRegImm16 ( Op , Base , Offset ) ) { OutOps . push_back ( Base ) ; OutOps . push_back ( Offset ) ; return false ; } OutOps . push_back ( Op ) ; OutOps . push_back ( CurDAG -> getTargetConstant ( <NUM_LIT> , <STR_LIT> ) ) ; return false ; } return true


<s> float32x4_t result ; __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT> ( b ) : ) ; return result


<s> Relocator :: Size <ISA_LIT>_64Relocator :: getSize ( Relocation :: Type pType ) const { return <ISA_LIT>_64ApplyFunctions [ pType ] .


<s> if ( ! MO . isReg ( ) || ! MO . isDef ( ) || ! MO . isDead ( ) ) continue ; unsigned R = MO . getReg ( ) ; if ( DeadDefs [ R ] ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << I << <STR_LIT> << J << <STR_LIT> ) ; return true ; } } return false


<s> return isTargetDarwin ( ) || ( ! isTargetWindows


<s> if ( CondCodes ) { unsigned TmpReg1 = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , TmpReg1 ) . addReg ( <STR_LIT> , getKillRegState ( true ) ) . addReg ( <STR_LIT> , getKillRegState ( true ) ) . addImm ( CondCodes [ <NUM_LIT> ] ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , ResultReg ) . addReg ( TmpReg1 , getKillRegState ( true ) ) . addReg ( <STR_LIT> , getKillRegState ( true ) ) . addImm ( CondCodes [ <NUM_LIT> ] ) ; updateValueMap ( I , ResultReg ) ; return true ; } <STR_LIT> CC = getCompareCC ( Predicate ) ; assert ( ( CC != <STR_LIT> ) && <STR_LIT> ) ; <STR_LIT> invertedCC = getInvertedCondCode ( CC ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , ResultReg ) . addReg ( <STR_LIT> , getKillRegState ( true ) ) . addReg (

<STR_LIT> , getKillRegState ( true ) ) . addImm ( invertedCC ) ;


<s> LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; dbgs ( ) << <STR_LIT> ; Ld0 -> dump ( ) ; dbgs ( ) << <STR_LIT> ; Ld1 -> dump ( ) ; ) ; VecMem . clear ( ) ; VecMem . push_back ( Ld0 ) ; VecMem . push_back ( Ld1 ) ; return


<s> MCStreamer * S = llvm :: createAsmStreamer ( Ctx , OS , isVerboseAsm , useDwarfDirectory , InstPrint , CE , TAB , ShowInst ) ; new <ISA_LIT>TargetAsmStreamer ( * S , OS ) ; return S


<s> static __inline qword si_eqv ( qword a , qword b ) { vec_uchar16 d ; d = vec_xor ( ( vec_uchar16 ) ( a ) , ( vec_uchar16 ) ( b


<s> if ( crtl -> args . pops_args && crtl -> args . size >= <NUM_LIT> ) return <NUM_LIT> ; ix86_compute_frame_layout ( &


<s> FunctionPass * llvm :: create<ISA_LIT>Packetizer (


<s> case <STR_LIT> : return lowerBRCOND ( Op , DAG ) ; case <STR_LIT> : return lowerConstantPool ( Op , DAG ) ; case <STR_LIT> : return lowerGlobalAddress ( Op , DAG ) ; case <STR_LIT> : return lowerBlockAddress ( Op , DAG ) ; case <STR_LIT> : return lowerGlobalTLSAddress ( Op , DAG ) ; case <STR_LIT> : return lowerJumpTable ( Op , DAG ) ; case <STR_LIT> : return lowerSELECT ( Op , DAG ) ; case <STR_LIT> : return lowerSELECT_CC ( Op , DAG ) ; case <STR_LIT> : return lowerSETCC ( Op , DAG ) ; case <STR_LIT> : return lowerVASTART ( Op , DAG ) ; case <STR_LIT> : return lowerFCOPYSIGN ( Op , DAG ) ; case <STR_LIT> : return lowerFABS ( Op , DAG ) ; case <STR_LIT> : return lowerFRAMEADDR ( Op , DAG ) ; case <STR_LIT> : return lowerRETURNADDR ( Op , DAG ) ; case <STR_LIT> : return lowerEH_RETURN


<s> unsigned getVGPREncodingGranule ( const MCSubtargetInfo * STI , Optional


<s> MachineOperand * getPreservedOperand ( ) const { return Preserve


<s> return ( char * ) obstack_finish ( & m_string_obstack


<s> if ( I == MBB . begin ( ) ) return <NUM_LIT> ; -- I ; } if ( I -> getOpcode ( ) != <STR_LIT> && GetCondFromBranchOpc ( I -> getOpcode ( ) ) == <STR_LIT> ) return <NUM_LIT> ; I -> eraseFromParent ( ) ; I = MBB . end ( ) ; if ( I == MBB . begin


<s> void <ISA_LIT>TargetELFStreamer :: emitIndIdx ( const MCExpr * Value ) { Streamer . EmitIntValue ( <STR_LIT> , sizeof ( uint64_t ) ) ; Streamer . EmitValue ( Value , sizeof ( uint64_t )


<s> return create<ISA_LIT>MachObjectWriter ( OS , false ,

MachO :: CPU_TYPE_<ISA_LIT> , Subtype ) ;


<s> if ( ConstExpr ) { int64_t Value = ConstExpr -> getValue ( ) ; return ( ( Value & ~ <NUM_LIT> ) == <NUM_LIT> ) ; } return false


<s> if ( RVVVectorBitsMax == <NUM_LIT> ) return <NUM_LIT> ; assert ( RVVVectorBitsMax >= <NUM_LIT> && RVVVectorBitsMax <= <NUM_LIT> && isPowerOf2_32 ( RVVVectorBitsMax ) && <STR_LIT> <STR_LIT> ) ; assert ( RVVVectorBitsMax >= RVVVectorBitsMin && <STR_LIT> <STR_LIT> ) ; unsigned Max = std :: max ( RVVVectorBitsMin


<s> CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; struct loongarch_arg_info info ; loongarch_get_arg_info ( & info , cum , arg . mode , arg . type , arg . named , false ) ; cum -> num_fprs = info . fpr_offset + info .


<s> DEBUG ( dbgs ( ) << <STR_LIT> ) ; Resources -> clearResources ( ) ; PacketNum = <NUM_LIT> ; UsesDotCur = nullptr ; DotCurPNum = - <NUM_LIT> ; UsesLoad = false ; PrefVectorStoreNew = nullptr


<s> bool <ISA_LIT>MachineLateOptimization :: runOnMachineFunction ( MachineFunction & MF ) { bool Changed = false ; return Changed


<s> PI != E ; ++ PI ) { if ( ( * PI ) != EndMBB ) { Succs . insert ( std :: pair < MachineBasicBlock * , MachineBasicBlock * > ( * PI , StartMBB ) ) ; } } for ( auto <ISA_LIT> : Succs ) { std :: pair < MachineBasicBlock * , MachineBasicBlock * > Edge = <ISA_LIT> ; DEBUG ( dbgs ( ) << <STR_LIT> << printMBBReference ( * Edge . first ) << <STR_LIT> <<

printMBBReference ( * Edge . second ) << <STR_LIT> ) ;


<s> static bool isPreISelGenericFloatingPointOpcode ( unsigned Opc ) { switch ( Opc ) { case TargetOpcode :: G_FADD : case TargetOpcode :: G_FSUB : case TargetOpcode :: G_FMUL : case TargetOpcode :: G_FDIV : case TargetOpcode :: G_FCONSTANT : case TargetOpcode :: G_FPEXT : case TargetOpcode :: G_FPTRUNC : case TargetOpcode :: G_FCEIL : case TargetOpcode :: G_FNEG : case TargetOpcode :: G_FCOS : case TargetOpcode :: G_FSIN : case TargetOpcode :: G_FLOG10 : case TargetOpcode :: G_FLOG : case TargetOpcode


<s> if ( From == IDom ) { CallInst * OldEnd = dyn_cast < CallInst > ( Parent -> getFirstInsertionPt ( ) ) ; while ( OldEnd && OldEnd -> getCalledFunction ( ) != EndCf ) OldEnd = dyn_cast < CallInst > ( OldEnd -> getNextNode ( ) ) ; if ( OldEnd && OldEnd -> getCalledFunction ( ) == EndCf ) { Value * Args [ ] = { OldEnd -> getArgOperand ( <NUM_LIT> ) , NewPhi } ; Ret = CallInst :: Create ( ElseBreak , Args , <STR_LIT> , OldEnd ) ; continue ; } } TerminatorInst * Insert = From -> getTerminator ( ) ; Value * PhiArg = CallInst :: Create ( Break , Broken , <STR_LIT> , Insert ) ; NewPhi -> setIncomingValue ( i , PhiArg ) ; } LoopPhiConditions . push_back ( WeakVH ( Phi ) ) ; return Ret ; } if ( Instruction * Inst = dyn_cast < Instruction > ( Cond ) ) { BasicBlock * Parent = Inst -> getParent ( ) ; Instruction * Insert ; if ( L -> contains ( Inst ) ) { Insert = Parent -> getTerminator ( ) ; } else { Insert = L -> getHeader ( ) -> getFirstNonPHIOrDbgOrLifetime ( ) ; } Value * Args [ ] = { Cond , Broken } ; return CallInst :: Create ( IfBreak , Args , <STR_LIT> , Insert ) ; } if ( isa < Constant > ( Cond ) ) { Instruction * Insert = Cond == BoolTrue ? Term : L -> getHeader ( ) -> getTerminator ( ) ; Value * Args [ ] = { Cond , Broken } ; return CallInst :: Create ( IfBreak , Args


<s> const FeatureBitset & getFeatureBits (


<s> if ( SrcVT == <STR_LIT> && UseSSEReg ) return Op ; if ( SrcVT == <STR_LIT> && UseSSEReg && Subtarget . is64Bit ( ) ) return Op ; if ( SDValue V = LowerI64IntToFP_AVX512DQ ( Op , DAG , Subtarget ) ) return V ; if ( SDValue V = LowerI64IntToFP16 ( Op , DAG , Subtarget ) ) return V ; if ( SrcVT == <STR_LIT> && ( UseSSEReg || VT == <STR_LIT> ) ) { SDValue Ext = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Src ) ; if ( IsStrict ) return DAG . getNode ( <STR_LIT> , dl , { VT , <STR_LIT> } , { Chain , Ext } ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Ext ) ; } if ( VT == <STR_LIT> ) return SDValue ( ) ; SDValue ValueToStore = Src ; if ( SrcVT == <STR_LIT> && Subtarget . hasSSE2 ( ) && ! Subtarget . is64Bit ( ) ) ValueToStore = DAG . getBitcast ( <STR_LIT> , ValueToStore ) ; unsigned Size = SrcVT . getStoreSize ( ) ; Align Alignment ( Size ) ; MachineFunction & MF = DAG . getMachineFunction ( ) ; auto PtrVT = getPointerTy ( MF . getDataLayout ( ) ) ; int SSFI = MF . getFrameInfo ( ) . CreateStackObject ( Size , Alignment , false ) ; MachinePointerInfo MPI = MachinePointerInfo :: getFixedStack ( DAG . getMachineFunction ( ) , SSFI ) ; SDValue StackSlot = DAG . getFrameIndex ( SSFI , PtrVT ) ; Chain = DAG . getStore ( Chain , dl , ValueToStore , StackSlot , MPI , Alignment ) ; std :: pair < SDValue , SDValue > Tmp = BuildFILD ( VT , SrcVT , dl , Chain


<s> SDValue Ops [ ] = { Op , DAG . getConstant ( NumBits , dl , VT ) , DAG . getTargetConstant ( <STR_LIT> , dl , <STR_LIT> ) , Op . getValue ( <NUM_LIT> ) } ; return DAG . getNode ( <STR_LIT> , dl , VT , Ops


<s> const InstrItineraryData * getInstrItineraryData ( ) const override { return & InstrItins


<s> MaxValue = APInt :: getSignedMaxValue ( DstScalarSizeInBits ) . sext ( SrcScalarSizeInBits ) ; } else { MinValue = APInt :: getNullValue ( SrcScalarSizeInBits ) ; MaxValue = APInt :: getLowBitsSet ( SrcScalarSizeInBits , DstScalarSizeInBits ) ; } auto * MinC = Constant :: getIntegerValue ( ArgTy , MinValue ) ; auto * MaxC = Constant :: getIntegerValue ( ArgTy , MaxValue ) ; Arg0 = Builder . CreateSelect ( Builder . CreateICmpSLT ( Arg0 , MinC ) , MinC , Arg0 ) ; Arg1 = Builder . CreateSelect ( Builder . CreateICmpSLT ( Arg1 , MinC ) , MinC , Arg1 ) ; Arg0 = Builder . CreateSelect ( Builder . CreateICmpSGT ( Arg0 , MaxC ) , MaxC , Arg0 ) ; Arg1 = Builder . CreateSelect ( Builder . CreateICmpSGT ( Arg1 , MaxC ) , MaxC , Arg1 ) ; SmallVector < int , <NUM_LIT> > PackMask ; for ( unsigned Lane = <NUM_LIT> ; Lane !=


<s> auto const & ST = MIRBuilder . getMF ( ) . getSubtarget < <ISA_LIT>Subtarget > ( ) ; unsigned Opcode = ST . getReturnOpcode ( ) ; auto Ret = MIRBuilder . buildInstrNoInsert ( Opcode ) . add ( predOps ( <STR_LIT> ) ) ; if ( ! lowerReturnVal ( MIRBuilder , Val , VReg , Ret ) ) return false ; MIRBuilder . insertInstr ( Ret ) ; return


<s> void addu10_0ExtOperands ( MCInst & Inst , unsigned N


<s> return MFI . getStackSize ( ) != <NUM_LIT> ; } return frameTriviallyRequiresSP ( MFI ) || MFI . isFrameAddressTaken ( ) || MF . getSubtarget < GCNSubtarget > ( ) . getRegisterInfo ( ) -> hasStackRealignment ( MF ) ||

MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) ;


<s> if ( INSN_CODE ( insn ) == CODE_FOR_iprefetch && INSN_CODE ( dep_insn ) == CODE_FOR_iprefetch ) return <NUM_LIT> ; if ( ( INSN_CODE ( insn ) == CODE_FOR_iprefetch || INSN_CODE ( insn ) == CODE_FOR_hbr ) && ( INSN_CODE ( dep_insn ) == CODE_FOR_iprefetch || INSN_CODE ( dep_insn ) == CODE_FOR_hbr ) ) return <NUM_LIT> ; if ( INSN_CODE ( insn ) == CODE_FOR_iprefetch || INSN_CODE ( dep_insn ) == CODE_FOR_iprefetch ) return <NUM_LIT> ; if ( CALL_P ( insn ) ) { rtx target = get_branch_target ( insn ) ; if ( GET_CODE ( target ) != REG || ! set_of ( target , insn ) ) return cost - <NUM_LIT> ; return cost ; } if ( CALL_P ( dep_insn ) ) return


<s> unsigned LinearizedRegion :: getBBSelectRegOut ( ) { return getRegionMRT ( ) ->


<s> MachineInstr * DeallocCall = nullptr ; if ( HasTC ) { unsigned ROpc = <STR_LIT> ; DeallocCall = BuildMI ( MBB , MI , DL , HII . get ( ROpc ) ) . addExternalSymbol ( RestoreFn ) ; } else { MachineBasicBlock :: iterator It = MBB . getFirstTerminator ( ) ; assert ( It -> isReturn ( ) && std :: next ( It ) == MBB . end ( ) ) ; unsigned ROpc = <STR_LIT> ; DeallocCall = BuildMI ( MBB , It , DL , HII . get ( ROpc ) ) . addExternalSymbol ( RestoreFn ) ; DeallocCall -> copyImplicitOps ( MF , * It ) ; } addCalleeSaveRegistersAsImpOperand ( DeallocCall , MaxR , true ) ; return


<s> const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; if ( ! CE ) return false ; return CE -> getValue ( ) >= - ( <NUM_LIT> << ( BitWidth - <NUM_LIT> ) )

&& CE -> getValue ( ) < ( <NUM_LIT> << ( BitWidth - <NUM_LIT> ) ) ;


<s> if ( m32r_rtx_ok_for_base_p ( x , strict ) || m32r_legitimate_offset_addres_p ( mode , x , strict ) || m32r_legitimate_lo_sum_addres_p ( mode , x , strict ) || m32r_load_postinc_p ( mode , x , strict ) || m32r_store_preinc_predec_p ( mode , x , strict ) ) return true ; return false


<s> static machine_mode rs6000_c_mode_for_suffix ( char suffix ) { if ( TARGET_FLOAT128 ) { if ( suffix == 'q' || suffix == 'Q' ) return ( FLOAT128_IEEE_P (


<s> if ( SubRegIdx == <STR_LIT> ) { auto & MII = getTranslator ( ) . getMII ( ) ; const MCInstrDesc & MCID = MII . get ( TheMCInst . Inst .


<s> addPass ( create<ISA_LIT>Z80PostRAPass (


<s> return __builtin_aarch64_lceiluv2dfv2di_us ( __a )


<s> } for ( const MachineBasicBlock * Pred : MBB . predecessors ( ) ) { BlockInfo & PredBI = Blocks [ Pred ] ; if ( ( PredBI . OutNeeds | BI . InNeeds ) == PredBI . OutNeeds ) continue ; PredBI . OutNeeds |= BI . InNeeds ; PredBI . InNeeds |= BI . InNeeds ; Worklist . push_back ( Pred ) ; } for ( const MachineBasicBlock * Succ : MBB . successors ( ) ) { BlockInfo & SuccBI = Blocks [ Succ ] ; if ( ( SuccBI . InNeeds | BI . OutNeeds ) ==


<s> if ( ! getLexer ( ) . is ( AsmToken :: Comma ) ) return MatchOperand_NoMatch ; getLexer ( ) . Lex ( ) ; Name = getLexer ( ) . getTok ( ) . getIdentifier ( ) ; if ( ! Name . consume_front ( <STR_LIT> ) ) return MatchOperand_NoMatch ; bool Fractional = false ; if ( Name . consume_front ( <STR_LIT> ) ) { Fractional = true ; } APInt Lmul ( <NUM_LIT> , Name , <NUM_LIT> ) ; if ( Lmul != <NUM_LIT> && Lmul != <NUM_LIT> && Lmul != <NUM_LIT> && Lmul != <NUM_LIT> ) return MatchOperand_NoMatch ; getLexer ( ) . Lex ( ) ; if ( ! getLexer ( ) . is ( AsmToken :: Comma ) ) return MatchOperand_NoMatch ; getLexer ( ) . Lex ( ) ; Name = getLexer ( ) . getTok ( ) . getIdentifier ( ) ; bool TailAgnostic ; if ( Name . consume_front ( <STR_LIT>


<s> Pass . TII -> copyPhysReg ( * PrehdrMBB , PrehdrMBB -> end ( ) , DL , Pass . GuardsReg , <STR_LIT> , false ) ; MachineInstr * Dummy = AddDefaultPred ( BuildMI ( * PrehdrMBB , PrehdrMBB -> end ( ) , DL , Pass . TII -> get ( <STR_LIT> ) , Pass . GuardsReg ) ) . addFrameIndex ( fi ) . addImm ( <NUM_LIT> ) ; Pass . GuardsLdStElim -> addRemovableInst ( Dummy ) ; AddDefaultPred ( BuildMI ( * PrehdrMBB , PrehdrMBB -> end ( ) , DL , Pass . TII -> get ( <STR_LIT> ) ) ) . addFrameIndex ( fi ) . addImm ( <NUM_LIT> ) . addReg ( Pass . GuardsReg , RegState :: Kill ) ; InsertedInstrs += <NUM_LIT> ; } insertHeaderPredLoadOrCopy ( S , PrehdrMBB , DL ) ; if ( S -> hasLoopBound ( ) ) { unsigned tmpReg = Pass . GuardsReg ; uint32_t loop = S -> getLoopBound ( ) ; AddDefaultPred ( BuildMI ( * PrehdrMBB , PrehdrMBB -> end ( ) , DL , Pass . TII -> get ( ( isUInt < <NUM_LIT> > ( loop ) ) ? <STR_LIT> : <STR_LIT> ) , tmpReg ) ) . addImm ( loop ) ; int fi = Pass . PMFI -> getSinglePathLoopCntFI ( S -> getDepth ( ) - <NUM_LIT> ) ; MachineInstr * Dummy = AddDefaultPred ( BuildMI ( * PrehdrMBB , PrehdrMBB -> end ( ) , DL , Pass . TII -> get ( <STR_LIT> ) , Pass . GuardsReg ) ) . addFrameIndex ( fi ) . addImm ( <NUM_LIT> ) ; Pass . GuardsLdStElim -> addRemovableInst


<s> bool <ISA_LIT>IndexMap :: runOnFunction ( Function & F ) { p_func = & F ; p_SE = & getAnalysis < ScalarEvolutionWrapperPass > ( ) . getSE ( ) ; p_LI = & getAnalysis < LoopInfoWrapperPass > ( ) . getLoopInfo ( ) ; collectDataLoop ( F , p_SE , p_LI ) ; sort ( ) ; print_data (


<s> RDFCount ++ ; } MDT = & getAnalysis < MachineDominatorTree > ( ) ; const auto & MDF = getAnalysis < MachineDominanceFrontier > ( ) ; const auto & HII = * MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getInstrInfo ( ) ; const auto & HRI = * MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getRegisterInfo ( ) ; MRI = & MF . getRegInfo ( ) ; bool Changed ; if ( RDFDump ) MF . print ( dbgs ( ) << <STR_LIT> << getPassName ( ) << <STR_LIT> , nullptr ) ; <ISA_LIT>RegisterAliasInfo HAI ( HRI ) ; TargetOperandInfo TOI ( HII ) ; DataFlowGraph G ( MF , HII , HRI , * MDT , MDF , HAI , TOI ) ; G . build ( BuildOptions :: KeepDeadPhis ) ; if ( RDFDump ) dbgs ( ) << <STR_LIT> << MF . getName ( ) << '\n' << PrintNode < FuncNode * > ( G . getFunc ( ) , G ) << '\n' ; <ISA_LIT>CP CP ( G ) ; CP . trace ( RDFDump ) ; Changed = CP . run ( ) ; if ( RDFDump ) dbgs ( ) << <STR_LIT> << MF . getName ( ) << '\n' << PrintNode < FuncNode * > ( G . getFunc ( ) , G ) << '\n' ; <ISA_LIT>DCE DCE ( G , * MRI ) ; DCE . trace ( RDFDump ) ; Changed |= DCE . run ( ) ; if ( Changed )


<s> case MachineOperand :: MO_MachineBasicBlock : printBasicBlockLabel ( MO . getMBB ( ) , false , false , VerboseAsm ) ; return ; case MachineOperand :: MO_GlobalAddress : { const GlobalValue * GV = MO . getGlobal ( ) ; std :: string Name = Mang -> getMangledName ( GV ) ; O << Name ; if ( TM . getRelocationModel ( ) == Reloc :: PIC_ && ! GV -> hasHiddenVisibility ( ) &&

! GV -> hasProtectedVisibility ( ) && ! GV -> hasLocalLinkage ( ) ) O << <STR_LIT> ;


<s> return isIntRegForSubInst ( HRI . getSubReg ( Reg , <STR_LIT> ) ) &&

isIntRegForSubInst ( HRI . getSubReg ( Reg , <STR_LIT> ) ) ;


<s> FunctionPass * llvm :: create<ISA_LIT>DiscriminateMemOpsPass


<s> if ( ! ArchFS . empty ( ) ) ArchFS = ( Twine ( ArchFS ) + <STR_LIT> + FS ) . str ( ) ; else ArchFS = std :: string ( FS ) ; } return create<ISA_LIT>MCSubtargetInfoImpl ( TT , CPU


<s> if ( MF -> getFunction ( ) . getCallingConv ( ) == CallingConv :: <ISA_LIT>_VectorCall || MF -> getFunction ( ) . getCallingConv ( ) == CallingConv :: <ISA_LIT>_SVE_VectorCall || STI -> getRegisterInfo ( ) -> hasSVEArgsOrReturn ( MF ) ) { auto * TS = static_cast < <ISA_LIT>TargetStreamer * > ( OutStreamer -> getTargetStreamer ( ) ) ; TS -> emitDirectiveVariantPCS ( CurrentFnSym


<s> float32_t result ; __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> (


<s> SDLoc dl ( GA ) ; EVT PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; unsigned char PCAdj = Subtarget -> isThumb ( ) ? <NUM_LIT> : <NUM_LIT> ; MachineFunction & MF = DAG . getMachineFunction ( ) ; <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; unsigned <ISA_LIT>PCLabelIndex = AFI -> createPICLabelUId ( ) ; <ISA_LIT>ConstantPoolValue * CPV = <ISA_LIT>ConstantPoolConstant :: Create ( GA -> getGlobal ( ) , <ISA_LIT>PCLabelIndex , <STR_LIT> , PCAdj , <STR_LIT> , true ) ; SDValue Argument = DAG . getTargetConstantPool ( CPV , PtrVT , <NUM_LIT> ) ; Argument = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Argument ) ; Argument = DAG . getLoad ( PtrVT , dl , DAG . getEntryNode ( ) , Argument , MachinePointerInfo :: getConstantPool ( DAG . getMachineFunction ( ) ) , false , false , false , <NUM_LIT> ) ; SDValue Chain = Argument . getValue ( <NUM_LIT> ) ; SDValue PICLabel = DAG . getConstant ( <ISA_LIT>PCLabelIndex , dl , <STR_LIT> ) ; Argument = DAG . getNode ( <STR_LIT> , dl ,


<s> case <STR_LIT> : if ( ( ImmVal & <NUM_LIT> ) == ImmVal ) { Shift = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; Imm = CurDAG -> getTargetConstant ( ImmVal , DL , <STR_LIT> ) ; return true ; } else if ( ( ImmVal & <NUM_LIT> ) == <NUM_LIT> ) { assert ( ( ImmVal >= - <NUM_LIT> ) && ( ImmVal <= <NUM_LIT> ) ) ; Shift = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; Imm = CurDAG -> getTargetConstant ( ( ImmVal >> <NUM_LIT> ) & <NUM_LIT> , DL , <STR_LIT> ) ; return true ; } break ; case <STR_LIT> : case


<s> case Op : \ return expand < Op > ( MBB , MI ) switch ( Opcode ) { EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; case <STR_LIT> : EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> )


<s> MachineFunctionPass ( ID ) , TII ( nullptr ) ,


<s> } ScheduledSUnits = Best . SUs ; ScheduledSUnitsInv . resize ( SUnits . size ( ) ) ; for ( unsigned i = <NUM_LIT> , e = ( unsigned ) SUnits . size ( ) ; i != e ; ++ i ) { ScheduledSUnitsInv [ ScheduledSUnits [ i ] ] = i ; } moveLowLatencies ( ) ; assert ( TopRPTracker . getPos ( ) == RegionBegin && <STR_LIT> ) ; TopRPTracker . setPos ( CurrentTop ) ; for ( std :: vector < unsigned > :: iterator I = ScheduledSUnits . begin ( ) , E = ScheduledSUnits . end ( ) ; I != E ; ++ I ) { SUnit * SU = & SUnits [ * I ] ; scheduleMI ( SU , true ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << SU -> NodeNum << <STR_LIT> << * SU -> getInstr ( ) ) ; } assert ( CurrentTop == CurrentBottom && <STR_LIT> ) ; placeDebugValues ( ) ; LLVM_DEBUG ( { dbgs ( ) << <STR_LIT> << printMBBReference ( * begin ( ) -> getParent ( ) ) << <STR_LIT> ; dumpSchedule ( ) ; dbgs ( ) <<


<s> assert ( MI && <STR_LIT> ) ; StackOffset SaveOffset ( Offset


<s> RegisterAsmPrinter < <ISA_LIT>AsmPrinter > X ( getThe<ISA_LIT>Target (


<s> auto & TPC = getAnalysis < TargetPassConfig > ( ) ; M = F . getParent ( ) ; DL = & M -> getDataLayout ( ) ; auto & TM = TPC . getTM < TargetMachine > ( ) ; auto * ST = & TM . getSubtarget < <ISA_LIT>Subtarget > ( F ) ; if ( ! ST -> allowsUnalignedMem ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> <STR_LIT> ) ; return false ; } if ( ! ST -> hasDSP ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> <STR_LIT> ) ; return


<s> AU . addRequired < TargetPassConfig > ( ) ; AU . setPreservesAll ( )


<s> Base = getReg ( Decoder , <STR_LIT> , Base ) ; Inst . addOperand ( MCOperand :: CreateReg ( Base ) ) ; Inst . addOperand ( MCOperand :: CreateImm ( Offset


<s> int32_t OffImm = ( int32_t ) MO2 . getImm ( ) ; bool isSub = OffImm < <NUM_LIT> ; if ( OffImm == INT32_MIN ) OffImm = <NUM_LIT> ; if ( isSub ) { O << <STR_LIT> << markup ( <STR_LIT> ) << <STR_LIT> << - OffImm << markup ( <STR_LIT> ) ; } else if ( AlwaysPrintImm0 ||


<s> assert ( RestoreGPRs . LowGPR != RestoreGPRs . HighGPR && <STR_LIT> ) ; MachineInstrBuilder MIB = BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) ) ; MIB . addReg ( RestoreGPRs . LowGPR , RegState :: Define ) ; MIB . addReg ( RestoreGPRs . HighGPR , RegState :: Define ) ; MIB . addReg ( HasFP ? <STR_LIT> : <STR_LIT> ) ; MIB . addImm ( RestoreGPRs . GPROffset ) ; for ( unsigned I = <NUM_LIT> , E = CSI . size ( ) ; I != E ; ++ I ) { unsigned Reg = CSI [ I ] . getReg ( ) ; if ( Reg != RestoreGPRs . LowGPR && Reg != RestoreGPRs . HighGPR && <STR_LIT> . contains ( Reg ) ) MIB

. addReg ( Reg , RegState :: ImplicitDefine ) ;


<s> struct df_link * link = DF_REF_CHAIN ( use ) ; if ( ! link ) insn_entry [ INSN_UID ( insn ) ] . is_live_in = <NUM_LIT> ; while ( link ) { if ( DF_REF_IS_ARTIFICIAL ( link -> ref ) ) insn_entry [ INSN_UID ( insn )


<s> bool <ISA_LIT>LegalizerInfo :: legalizeShuffleVector ( MachineInstr & MI , MachineRegisterInfo & MRI , MachineIRBuilder & B ) const { const LLT V2S16 = LLT :: fixed_vector ( <NUM_LIT> , <NUM_LIT> ) ; Register Dst = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register Src0 = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; LLT DstTy = MRI . getType ( Dst ) ; LLT SrcTy = MRI . getType ( Src0 ) ; if ( SrcTy == V2S16 && DstTy == V2S16 && <STR_LIT> ( MI . getOperand ( <NUM_LIT> ) . getShuffleMask ( ) ) ) return true ; MachineIRBuilder HelperBuilder ( MI ) ; GISelObserverWrapper DummyObserver ; LegalizerHelper Helper ( B . getMF ( ) , DummyObserver , HelperBuilder ) ; return Helper . lowerShuffleVector ( MI ) ==


<s> int64_t Imm ; <ISA_LIT>MCExpr :: VariantKind VK = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ; if ( ! isImm ( ) ) return false ; bool IsConstantImm = evaluateConstantImm ( getImm ( ) , Imm , VK ) ; bool IsValid ; if ( ! IsConstantImm ) IsValid = <ISA_LIT>AsmParser :: classifySymbolRef ( getImm ( ) , VK , Imm ) ; else IsValid = isShiftedUInt < <NUM_LIT> , <NUM_LIT> > ( Imm ) ; return IsValid && VK == <ISA_LIT>MCExpr ::


<s> inline bool <ISA_LIT>DAGToDAGISel :: SelectAddrGP ( SDValue & N , SDValue & R ) { return SelectGlobalAddress ( N , R


<s> old_reg = head -> regno ; best_reg = find_rename_reg ( head , superclass , & unavailable , old_reg , false ) ; bool ok = regrename_do_replace ( head , best_reg ) ; gcc_assert ( ok ) ; if ( dump_file ) fprintf ( dump_file , <STR_LIT> , head -> id , reg_names

[ best_reg ] , reg_class_names [ superclass ] ) ;


<s> return ( Value >> <NUM_LIT> ) & <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : if ( TheTriple . isOSBinFormatCOFF ( ) && ! IsResolved ) Value &= <NUM_LIT> ; if ( Value >= <NUM_LIT> ) Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; return Value ; case <STR_LIT> : if ( TheTriple . isOSBinFormatCOFF ( ) && ! IsResolved ) Value &= <NUM_LIT> ; if ( Value >= <NUM_LIT> ) Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; if ( Value & <NUM_LIT> ) Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; return Value >> <NUM_LIT> ; case <STR_LIT> : if ( TheTriple . isOSBinFormatCOFF ( ) && ! IsResolved ) Value &= <NUM_LIT> ; if ( Value >= <NUM_LIT> ) Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; if ( Value & <NUM_LIT> ) Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; return Value >> <NUM_LIT> ; case <STR_LIT> : if ( TheTriple . isOSBinFormatCOFF ( ) && ! IsResolved ) Value &= <NUM_LIT> ; if ( Value >= <NUM_LIT> ) Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; if ( Value & <NUM_LIT> ) Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; return Value >> <NUM_LIT> ; case <STR_LIT> : if ( TheTriple . isOSBinFormatCOFF ( ) && ! IsResolved ) Value &= <NUM_LIT> ; if ( Value >= <NUM_LIT> ) Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; if ( Value & <NUM_LIT> ) Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; return Value >> <NUM_LIT> ; case <STR_LIT> : { <ISA_LIT>MCExpr :: VariantKind RefKind = static_cast < <ISA_LIT>MCExpr :: VariantKind > ( Target . getRefKind ( ) ) ; if ( <ISA_LIT>MCExpr :: getSymbolLoc ( RefKind ) != <ISA_LIT>MCExpr :: VK_ABS && <ISA_LIT>MCExpr :: getSymbolLoc ( RefKind ) != <ISA_LIT>MCExpr :: VK_SABS ) { Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> <STR_LIT> ) ; return Value ; } if ( ! IsResolved ) { Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> <STR_LIT> ) ; return Value ; } if ( <ISA_LIT>MCExpr :: getSymbolLoc ( RefKind ) == <ISA_LIT>MCExpr :: VK_SABS ) { switch ( <ISA_LIT>MCExpr :: getAddressFrag ( RefKind ) ) { case <ISA_LIT>MCExpr :: VK_G0 : break ; case <ISA_LIT>MCExpr :: VK_G1 : SignedValue = SignedValue >> <NUM_LIT> ; break ; case <ISA_LIT>MCExpr :: VK_G2 : SignedValue = SignedValue >> <NUM_LIT> ; break ; case <ISA_LIT>MCExpr


<s> return Kind == k_VectorIndex && VectorIndex


<s> void <ISA_LIT>MCInstLower :: LowerCPLOAD ( SmallVector < MCInst , <NUM_LIT> > & MCInsts ) { MCOperand GPReg = MCOperand :: CreateReg ( <STR_LIT> ) ; MCOperand T9Reg = MCOperand :: CreateReg ( <STR_LIT> ) ; MCOperand ZEROReg = MCOperand :: CreateReg ( <STR_LIT> ) ; StringRef SymName ( <STR_LIT> ) ; const MCSymbol * Sym = Ctx -> GetOrCreateSymbol ( SymName ) ; const MCSymbolRefExpr * MCSym ; MCSym = MCSymbolRefExpr :: Create ( Sym , MCSymbolRefExpr :: VK_<ISA_LIT>_ABS_HI , * Ctx ) ; MCOperand SymHi = MCOperand :: CreateExpr ( MCSym


<s> return __builtin_loongson_psubb_s ( s ,


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: createImm


<s> } SmallVector < uint64_t , <NUM_LIT> > BitOffsets ; SmallVector < unsigned , <NUM_LIT> > SplitRegs ; EVT PartVT = TLI . getRegisterType ( Context , VT ) ; Type * PartTy = PartVT . getTypeForEVT ( Context ) ; for ( unsigned i = <NUM_LIT> ; i < NumParts ; ++ i ) { ArgInfo Info = ArgInfo { MRI . createGenericVirtualRegister ( getLLTForType ( * PartTy , DL ) ) , PartTy , OrigArg . Flags } ; SplitArgs . push_back ( Info ) ; PerformArgSplit ( Info . Reg , PartVT . getSizeInBits ( )


<s> unsigned FirstOpcode = FirstMI ? FirstMI -> getOpcode ( ) : static_cast < unsigned > ( <STR_LIT> ) ; unsigned SecondOpcode = SecondMI . getOpcode ( ) ; if ( ST . hasFuseAES ( ) )


<s> if ( get<ISA_LIT>Subtarget ( ) . os16 ( ) ) addPass

( create<ISA_LIT>Os16Pass ( get<ISA_LIT>TargetMachine ( ) ) ) ;


<s> const MachineOperand * BaseOpA = nullptr , * BaseOpB = nullptr ; int64_t OffsetA = <NUM_LIT> , OffsetB = <NUM_LIT> ; unsigned int WidthA = <NUM_LIT> , WidthB = <NUM_LIT> ; if ( getMemOperandWithOffsetWidth ( MIa , BaseOpA , OffsetA , WidthA , TRI ) && getMemOperandWithOffsetWidth ( MIb , BaseOpB , OffsetB , WidthB , TRI ) ) { if ( BaseOpA -> isIdenticalTo ( * BaseOpB


<s> bool checkVLDnAccessAlignment ( ) const { return CheckVLDnAlign


<s> <ISA_LIT>ABIInfo ABI = Subtarget . getABI ( ) ; DebugLoc DL = I != MBB . end ( ) ? I -> getDebugLoc ( ) : DebugLoc ( ) ; unsigned ADDu = ABI . GetPtrAdduOp ( ) ; unsigned ADDiu = ABI . GetPtrAddiuOp ( ) ; if ( Amount == <NUM_LIT> ) return ; if ( isInt < <NUM_LIT> > ( Amount ) ) BuildMI ( MBB , I , DL , get (

ADDiu ) , SP ) . addReg ( SP ) . addImm ( Amount ) ;


<s> inline SDValue getI32Imm ( unsigned Imm ) { return CurDAG -> getTargetConstant ( Imm ,


<s> if ( RegNo > <NUM_LIT> ) return MCDisassembler :: Fail ; unsigned Reg = getReg ( Decoder , <STR_LIT> , RegNo ) ; Inst . addOperand ( MCOperand :: CreateReg


<s> InstructionCost <ISA_LIT>TTIImpl :: getShuffleCost ( TTI :: ShuffleKind Kind , Type * Tp , ArrayRef < int > Mask , int Index , Type * SubTp , ArrayRef < const Value * > Args ) { InstructionCost CostFactor = vectorCostAdjustmentFactor ( Instruction :: ShuffleVector , Tp , nullptr ) ; if ( ! CostFactor . isValid ( ) ) return InstructionCost ::


<s> unsigned flags = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; Inst . addOperand ( MCOperand :: createImm ( imod )


<s> bool <ISA_LIT>AsmParser :: handleNoncontigiousRegister ( bool Contigious , SMLoc & Loc ) { if ( ! Contigious && ErrorNoncontigiousRegister ) { Error ( Loc , <STR_LIT> ) ; return true


<s> MCInstrDesc const & <ISA_LIT>MCInstrInfo :: getDesc ( MCInstrInfo const & MCII , MCInst const & MCI ) { return MCII . get ( MCI . getOpcode


<s> const TargetInstrInfo * TII = getTargetMachine ( ) . getInstrInfo ( ) ; DebugLoc DL = MI -> getDebugLoc ( ) ; if ( Subtarget . has<ISA_LIT>32r2 ( ) && Size == <NUM_LIT> ) { BuildMI ( BB , DL , TII -> get ( <STR_LIT> ) , DstReg ) . addReg ( SrcReg ) ; return BB ; } if ( Subtarget . has<ISA_LIT>32r2 ( ) && Size == <NUM_LIT> ) { BuildMI ( BB , DL , TII -> get ( <STR_LIT> ) , DstReg ) . addReg ( SrcReg ) ; return BB ; } MachineFunction * MF = BB -> getParent ( ) ; MachineRegisterInfo & RegInfo = MF -> getRegInfo ( ) ; const TargetRegisterClass * RC = getRegClassFor ( <STR_LIT> ) ; unsigned ScrReg = RegInfo . createVirtualRegister ( RC ) ; assert ( Size < <NUM_LIT> ) ; int64_t ShiftImm = <NUM_LIT> - ( Size * <NUM_LIT> ) ; BuildMI ( BB , DL , TII -> get ( <STR_LIT> ) , ScrReg ) . addReg ( SrcReg ) . addImm ( ShiftImm ) ; BuildMI ( BB , DL , TII -> get ( <STR_LIT> ) , DstReg ) .

addReg ( ScrReg ) . addImm ( ShiftImm ) ;


<s> dbgs ( ) << <STR_LIT> << getSCCNum ( * iterBlk ) << <STR_LIT> << ( * iterBlk ) -> size ( ) << <STR_LIT> ; if ( i != <NUM_LIT> && i % <NUM_LIT>


<s> Chain = CLI . DAG . getCopyToReg ( Chain , CLI . DL , RegsToPass [ i ] . first , RegsToPass [ i ] . second , InFlag ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; } for ( unsigned i = <NUM_LIT> , e = RegsToPass . size ( ) ; i != e ; ++ i ) Ops . push_back ( CLI . DAG . getRegister ( RegsToPass [ i ] . first , RegsToPass [ i ] . second . getValueType ( ) ) ) ; const TargetRegisterInfo * TRI = getTargetMachine ( ) . getRegisterInfo ( ) ; const uint32_t * Mask = TRI -> getCallPreservedMask ( CLI . CallConv ) ; assert ( Mask && <STR_LIT> ) ; if ( Subtarget ->


<s> BuildMI ( B , At , DL , HII . get ( <STR_LIT> ) , Reg ) . addImm ( C ) ; return Reg ; } unsigned Lo = Lo_32 ( C ) , Hi = Hi_32 ( C ) ; if ( isInt < <NUM_LIT> > ( Lo ) || isInt < <NUM_LIT> > ( Hi ) ) { unsigned Opc = isInt < <NUM_LIT> > ( Lo ) ? <STR_LIT> : <STR_LIT> ; BuildMI ( B , At , DL , HII . get ( Opc ) , Reg ) . addImm ( int32_t ( Hi ) ) . addImm ( int32_t ( Lo ) ) ; return Reg ; } BuildMI ( B , At , DL , HII . get ( <STR_LIT> ) , Reg ) . addImm ( C ) ; return Reg ; } if ( RC == & <STR_LIT> ) { unsigned Opc ; if ( C == <NUM_LIT> ) Opc = <STR_LIT> ; else if ( ( C & <NUM_LIT> ) == <NUM_LIT> ) Opc = <STR_LIT> ; else return <NUM_LIT> ; BuildMI ( B , At , DL , HII . get ( Opc ) , Reg ) ; return


<s> for ( unsigned j = <NUM_LIT> ; j != array_lengthof ( ViableForN ) ; ++ j ) if ( ViableForN [ j ] ) { uint64_t N = j + <NUM_LIT> ; if ( ( uint64_t ) Mask [ i ] == ( ( ( uint64_t ) i << N ) & ModMask ) ) IsAnyViable = true ; else ViableForN [ j ] = false ; } if ( ! IsAnyViable ) break ; } for ( unsigned j = <NUM_LIT> ; j != array_lengthof ( ViableForN ) ; ++ j ) if ( ViableForN


<s> Inst . addOperand ( MCOperand :: createImm ( SignExtend64 < N


<s> std :: tie ( CPU , ExtensionString ) = getParser ( ) . parseStringToEndOfStatement ( ) . trim ( ) . split ( '+' ) ; if ( parseToken ( AsmToken :: EndOfStatement ) ) return true ; SmallVector < StringRef , <NUM_LIT> > RequestedExtensions ; if ( ! ExtensionString . empty ( ) ) ExtensionString . split ( RequestedExtensions , '+' ) ; if ( ! getSTI ( ) . isCPUStringValid ( CPU ) ) { Error ( CurLoc , <STR_LIT> ) ; return false ; } MCSubtargetInfo & STI = copySTI ( ) ; STI . setDefaultFeatures ( CPU , CPU , <STR_LIT> ) ; CurLoc = incrementLoc ( CurLoc , CPU . size ( ) ) ; ExpandCryptoAEK ( llvm :: <STR_LIT> ( CPU ) , RequestedExtensions ) ; FeatureBitset Features = STI . getFeatureBits ( ) ; for ( auto Name : RequestedExtensions ) { CurLoc = incrementLoc ( CurLoc , <NUM_LIT> ) ; bool EnableFeature = true ; if ( Name . startswith_insensitive ( <STR_LIT> ) ) { EnableFeature = false ; Name = Name . substr ( <NUM_LIT> ) ; } bool FoundExtension = false ; for ( const auto & Extension : ExtensionMap ) { if ( Extension . Name != Name ) continue ; if ( Extension . Features . none ( ) ) report_fatal_error ( <STR_LIT> + Name ) ; FeatureBitset ToggleFeatures = EnableFeature ? ( ~ Features & Extension . Features ) : ( Features & Extension . Features ) ; FeatureBitset Features = ComputeAvailableFeatures ( STI . ToggleFeature ( ToggleFeatures ) ) ; setAvailableFeatures (


<s> bool <ISA_LIT>MCInstrInfo :: isPrefix ( MCInstrInfo const & MCII , MCInst const & MCI ) { return <STR_LIT> == <ISA_LIT>MCInstrInfo :: getType


<s> if ( CmpInGPR == ICGPR_I32 || CmpInGPR == ICGPR_SextI32 || CmpInGPR == ICGPR_ZextI32 || CmpInGPR == ICGPR_Zext ) return SDValue ( ) ; bool IsRHSZero = RHSValue == <NUM_LIT> ; bool IsRHSOne = RHSValue == <NUM_LIT> ; bool IsRHSNegOne = RHSValue == - <NUM_LIT> ; switch ( CC ) { default : return SDValue ( ) ; case <STR_LIT> : { SDValue AddInput = IsRHSZero ? LHS : SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , LHS , RHS ) , <NUM_LIT> ) ; SDValue Addic = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , <STR_LIT> , AddInput , S -> getI32Imm ( ~ <NUM_LIT> , dl ) ) , <NUM_LIT> ) ; return SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , Addic , Addic , Addic . getValue ( <NUM_LIT> ) ) , <NUM_LIT> ) ; } case <STR_LIT> : { SDValue Xor = IsRHSZero ? LHS : SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , LHS , RHS ) , <NUM_LIT> ) ; SDValue SC = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , <STR_LIT> , Xor , S -> getI32Imm ( <NUM_LIT> , dl ) ) , <NUM_LIT> ) ; return SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , SC , SC , SC . getValue ( <NUM_LIT> ) ) , <NUM_LIT> ) ; } case <STR_LIT> : { if ( IsRHSZero ) return getCompoundZeroComparisonInGPR ( LHS , dl , ZeroCompare :: GESExt ) ; std :: swap ( LHS , RHS ) ; ConstantSDNode * RHSConst = dyn_cast < ConstantSDNode > ( RHS ) ; IsRHSZero = RHSConst && RHSConst -> isZero ( ) ; LLVM_FALLTHROUGH ; } case <STR_LIT> : { if ( IsRHSZero ) return getCompoundZeroComparisonInGPR ( LHS , dl , ZeroCompare :: LESExt ) ; SDValue ShiftR = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , RHS , S -> getI64Imm ( <NUM_LIT> , dl ) ) , <NUM_LIT> ) ; SDValue ShiftL = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , LHS , S -> getI64Imm ( <NUM_LIT> , dl ) , S -> getI64Imm ( <NUM_LIT> , dl ) ) , <NUM_LIT> ) ; SDValue SubtractCarry = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , <STR_LIT> , LHS , RHS ) , <NUM_LIT> ) ; SDValue Adde = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , <STR_LIT> , ShiftR , ShiftL , SubtractCarry ) , <NUM_LIT> ) ; return SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , Adde ) , <NUM_LIT> ) ; } case <STR_LIT> : { if ( IsRHSNegOne ) return getCompoundZeroComparisonInGPR ( LHS , dl , ZeroCompare :: GESExt ) ; if ( IsRHSZero ) { SDValue Add = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> ,

LHS , S -> getI64Imm ( - <NUM_LIT> , dl ) ) , <NUM_LIT> ) ;


<s> MCAsmParser & getParser ( ) const { return


<s> inline static bool isValidLMUL ( unsigned


<s> const MCOperand & MO = MI . getOperand ( OpNo ) ; if ( MO . isImm ( ) ) return MO . getImm ( ) ; assert ( MO . isExpr ( ) && <STR_LIT> ) ; Fixups . push_back ( MCFixup :: create ( <NUM_LIT> , MO . getExpr ( ) , MCFixupKind


<s> int NumOp = Inst -> getNumExplicitOperands ( ) ; BB = Inst -> getOperand ( NumOp - <NUM_LIT> ) . getMBB ( ) ; Cond . push_back ( MachineOperand :: CreateImm ( Opc ) ) ; for ( int i = <NUM_LIT> ; i < NumOp - <NUM_LIT> ; i

++ ) Cond . push_back ( Inst -> getOperand ( i ) ) ;


<s> case MachineOperand :: MO_Register : if ( MO . isImplicit ( ) ) break ; return MCOperand :: CreateReg ( MO . getReg ( ) ) ; case MachineOperand :: MO_Immediate : return MCOperand :: CreateImm ( MO . getImm ( )


<s> static DecodeStatus DecodeHvxQRRegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t , const void * Decoder ) { static const MCPhysReg HvxQRDecoderTable [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; return DecodeRegisterClass ( Inst ,


<s> if ( GET_CODE ( op2 ) == SUBREG ) op2 = SUBREG_REG ( op2 ) ; if ( GET_CODE ( op3 ) == SUBREG ) op3 = SUBREG_REG ( op3 ) ; if ( GET_CODE ( op0 ) == REG && ( ( GET_CODE ( op2 ) == MEM && reg_mentioned_p ( op0 , XEXP ( op2 , <NUM_LIT> ) ) ) || ( GET_CODE ( op3 ) == MEM && reg_mentioned_p ( op0 , XEXP ( op3 , <NUM_LIT> ) ) ) ) ) return <NUM_LIT> ; if ( GET_CODE ( op0 ) == REG && GET_CODE ( op2 ) == REG ) return ( REGNO ( op0 ) != REGNO ( op2 ) ) && GET_CODE ( op1 ) == MEM && GET_CODE ( op3 ) == MEM && ! c4x_address_conflict ( op1 , op3 , <NUM_LIT> , <NUM_LIT> ) ; if ( GET_CODE ( op1 ) == REG && GET_CODE ( op3 ) == REG ) return GET_CODE ( op0 ) == MEM && GET_CODE ( op2 ) == MEM && ! c4x_address_conflict ( op0 , op2 , <NUM_LIT> , <NUM_LIT> ) ; if ( GET_CODE ( op0 ) == REG && GET_CODE ( op3 ) == REG ) return GET_CODE ( op1 ) == MEM && GET_CODE ( op2 ) == MEM && ! c4x_address_conflict ( op1 , op2 , <NUM_LIT> , <NUM_LIT> ) ; if ( GET_CODE ( op1 ) == REG && GET_CODE ( op2 ) == REG ) return GET_CODE ( op0 ) == MEM && GET_CODE ( op3 ) == MEM && !


<s> SDValue Flag ; SmallVector < SDValue , <NUM_LIT> > RetOps ( <NUM_LIT> , Chain ) ; RetOps . push_back ( SDValue ( ) ) ; for ( unsigned i = <NUM_LIT> , realRVLocIdx = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i , ++ realRVLocIdx ) { CCValAssign & VA = RVLocs [ i ] ; assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; SDValue Arg = OutVals [ realRVLocIdx ] ; if ( VA . needsCustom ( ) ) { assert ( VA . getLocVT ( ) == <STR_LIT> ) ; SDValue Part0 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Arg , DAG . getConstant ( <NUM_LIT> , DL , getVectorIdxTy ( DAG . getDataLayout ( ) ) ) ) ; SDValue Part1 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Arg , DAG . getConstant ( <NUM_LIT> , DL , getVectorIdxTy ( DAG . getDataLayout ( ) ) ) ) ; Chain = DAG . getCopyToReg ( Chain , DL , VA . getLocReg ( ) , Part0


<s> unsigned getPrefLoopAlignment ( ) const { return PrefLoopAlignment


<s> machine_mode mode0 = insn_data [ d -> icode ] . operand [ <NUM_LIT> ] . mode ; machine_mode mode1 = insn_data [ d -> icode ] . operand [ <NUM_LIT> ] . mode ; enum rtx_code comparison = d -> comparison ; if ( VECTOR_MODE_P ( mode0 ) ) op0 = safe_vector_operand ( op0 , mode0 ) ; if ( VECTOR_MODE_P ( mode1 ) ) op1 = safe_vector_operand ( op1 , mode1 ) ; target = gen_reg_rtx ( SImode ) ; emit_move_insn ( target , const0_rtx ) ; target = gen_rtx_SUBREG ( QImode , target , <NUM_LIT> ) ; if ( ( optimize && ! register_operand ( op0 , mode0 ) ) || ! insn_data [ d -> icode ] . operand [ <NUM_LIT> ] . predicate ( op0 , mode0 ) ) op0 = copy_to_mode_reg ( mode0 , op0 ) ; if ( ( optimize && ! register_operand ( op1 , mode1 ) ) || ! insn_data [ d -> icode ] . operand [ <NUM_LIT> ] . predicate ( op1 , mode1 ) ) op1 = copy_to_mode_reg ( mode1 , op1 ) ; pat = GEN_FCN ( d -> icode ) ( op0 , op1 ) ; if ( ! pat ) return <NUM_LIT> ; emit_insn ( pat ) ; emit_insn ( gen_rtx_SET ( gen_rtx_STRICT_LOW_PART ( VOIDmode , target ) , gen_rtx_fmt_ee ( comparison , QImode , SET_DEST ( pat ) , const0_rtx )


<s> Opc = <STR_LIT> ; RC = & <STR_LIT> ; } else { Opc = <STR_LIT> ; RC = & <STR_LIT> ; } break ; case <STR_LIT> : return <NUM_LIT> ; } unsigned ResultReg = createResultReg ( RC ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , ResultReg ) ; return ResultReg


<s> bool <ISA_LIT>InstrInfo :: copyRegToReg ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned DestReg , unsigned SrcReg , const TargetRegisterClass * DestRC , const


<s> if ( current_tune -> sched_adjust_cost != NULL ) { if ( ! current_tune -> sched_adjust_cost ( insn , link , dep , & cost ) ) return cost ; } if ( REG_NOTE_KIND ( link ) == REG_DEP_ANTI || REG_NOTE_KIND ( link ) == REG_DEP_OUTPUT ) return <NUM_LIT> ; if ( REG_NOTE_KIND ( link ) == <NUM_LIT> && CALL_P ( insn ) ) return <NUM_LIT> ; if ( ( i_pat = single_set ( insn ) ) != NULL && MEM_P ( SET_SRC ( i_pat ) ) && ( d_pat = single_set ( dep ) ) != NULL && MEM_P ( SET_DEST ( d_pat ) ) ) { rtx src_mem = XEXP ( SET_SRC ( i_pat ) , <NUM_LIT> ) ; if ( ( GET_CODE ( src_mem ) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P ( src_mem ) ) || reg_mentioned_p ( stack_pointer_rtx , src_mem ) || reg_mentioned_p ( frame_pointer_rtx , src_mem )


<s> } uint32_t Inst = ( Bytes [ <NUM_LIT> ] << <NUM_LIT> ) | ( Bytes [ <NUM_LIT> ] << <NUM_LIT> ) | ( Bytes [ <NUM_LIT> ] << <NUM_LIT> ) | ( Bytes [ <NUM_LIT> ] << <NUM_LIT> ) ; return decodeInstruction ( DecoderTable32 , MI , Inst , Address , this ,


<s> llvm :: RegisterAsmPrinter < llvm :: <ISA_LIT>AsmPrinter > X ( llvm ::


<s> if ( ! validateIntClampSupported ( Inst ) ) { Error ( getImmLoc ( <ISA_LIT>Operand :: ImmTyClamp<ISA_LIT> , Operands ) , <STR_LIT> ) ; return false ; } if ( ! validateOpSel ( Inst ) ) { Error ( getImmLoc ( <ISA_LIT>Operand :: ImmTyOpSel , Operands ) , <STR_LIT> ) ; return false ; } if ( ! validateDPP ( Inst , Operands ) ) { return false ; } if ( ! validateMIMGD16 ( Inst ) ) { Error ( getImmLoc ( <ISA_LIT>Operand :: ImmTyD16 , Operands ) , <STR_LIT> ) ; return false ; } if ( ! validateMIMGDim ( Inst ) ) { Error ( IDLoc , <STR_LIT> ) ; return false ; } if ( ! validateMIMGMSAA ( Inst ) ) { Error ( getImmLoc ( <ISA_LIT>Operand :: ImmTyDim , Operands ) , <STR_LIT> ) ; return false ; } if ( ! validateMIMGDataSize ( Inst ) ) { Error ( IDLoc , <STR_LIT> ) ; return false ; } if ( ! validateMIMGAddrSize ( Inst ) ) { Error ( IDLoc , <STR_LIT> ) ; return false ; } if ( ! validateMIMGAtomicDMask ( Inst ) ) { Error ( getImmLoc ( <ISA_LIT>Operand :: ImmTyDMask , Operands ) , <STR_LIT> ) ; return false ; } if ( ! validateMIMGGatherDMask ( Inst ) ) { Error ( getImmLoc ( <ISA_LIT>Operand :: ImmTyDMask , Operands ) , <STR_LIT> ) ; return false ; } if ( ! validateMovrels ( Inst ,


<s> MinCSFI = CSI [ <NUM_LIT> ] . getFrameIdx ( ) ; MaxCSFI = CSI [ CSI . size ( ) - <NUM_LIT> ] . getFrameIdx ( ) ; } FrameReg = RI -> getFrameRegister ( MF ) ; if ( ( FI >= MinCSFI && FI <= MaxCSFI ) || ! hasFP ( MF ) ) { FrameReg = <STR_LIT>


<s> if ( ei >= <NUM_LIT> * nelt ) return <NUM_LIT> ; ipar [ i ] = ei ; } for ( i = <NUM_LIT> ; i < nelt2 - <NUM_LIT> ; ++ i ) if ( ipar [ i ] + <NUM_LIT> != ipar [ i + <NUM_LIT> ] ) return <NUM_LIT> ; for ( i = nelt2 ; i < nelt - <NUM_LIT> ; ++ i ) if ( ipar [ i ] + <NUM_LIT> != ipar [ i + <NUM_LIT> ] ) return <NUM_LIT> ; for ( i = <NUM_LIT> ; i < <NUM_LIT>


<s> UseFastISel |= Subtarget -> isTargetMachO ( ) && ! Subtarget -> isThumb1Only ( ) ; UseFastISel |= Subtarget -> isTargetLinux ( ) && ! Subtarget -> isThumb ( ) ; UseFastISel |= Subtarget -> isTargetNaCl ( ) && !


<s> if ( MO . isFPImm ( ) ) { APFloat FpImm = MO . getFPImm ( ) -> getValueAPF ( ) ; return isInlineConstant ( FpImm . bitcastToAPInt ( ) ) ; } return


<s> LaneBitmask <ISA_LIT>ExpandCondsets :: getLaneMask ( unsigned Reg , unsigned Sub ) { assert ( TargetRegisterInfo :: isVirtualRegister ( Reg ) ) ; return Sub != <NUM_LIT> ? TRI -> getSubRegIndexLaneMask ( Sub

) : MRI -> getMaxLaneMaskForVReg ( Reg ) ;


<s> tree return_type = TREE_TYPE ( fntype ) ; pure_scalable_type_info pst_info ; switch ( pst_info . analyze ( return_type ) ) { case pure_scalable_type_info :: IS_PST : return ( pst_info . num_zr ( ) <= NUM_FP_ARG_REGS && pst_info . num_pr ( ) <= NUM_PR_ARG_REGS ) ; case pure_scalable_type_info :: DOESNT_MATTER : gcc_assert ( aarch64_return_in_memory_1 ( return_type ) ) ; return false ; case pure_scalable_type_info :: NO_ABI_IDENTITY : case pure_scalable_type_info :: ISNT_PST : return false


<s> uint32_t BitWidth = ( Imm & <NUM_LIT> ) >> <NUM_LIT> ; ( void ) Offset ; assert ( Inst . getOpcode ( ) == <STR_LIT> && BitWidth <= <NUM_LIT> && Offset == <NUM_LIT> && <STR_LIT> ) ; if ( BitWidth < <NUM_LIT> ) { unsigned MidRegLo = MRI . createVirtualRegister ( & <STR_LIT> ) ; unsigned MidRegHi = MRI . createVirtualRegister ( & <STR_LIT> ) ; unsigned ResultReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( MBB , MII , DL , get ( <STR_LIT> ) , MidRegLo ) . addReg ( Inst . getOperand ( <NUM_LIT> ) . getReg ( ) , <NUM_LIT> , <STR_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( BitWidth ) ; BuildMI ( MBB , MII , DL , get ( <STR_LIT> ) , MidRegHi ) . addImm ( <NUM_LIT> ) . addReg ( MidRegLo ) ; BuildMI ( MBB , MII , DL , get ( TargetOpcode :: REG_SEQUENCE ) , ResultReg ) . addReg ( MidRegLo ) . addImm ( <STR_LIT> ) . addReg ( MidRegHi ) . addImm ( <STR_LIT> ) ; MRI . replaceRegWith ( Dest . getReg ( ) , ResultReg ) ; addUsersToMoveToVALUWorklist ( ResultReg , MRI , Worklist ) ; return ; } MachineOperand & Src = Inst . getOperand ( <NUM_LIT> ) ; unsigned TmpReg = MRI . createVirtualRegister


<s> __b = ( __vector signed short ) vec_splats ( __m2 ) ; __c = __a * __b ; return ( __m64 ) ( ( __vector long long ) __c


<s> if ( Subtarget . hasAltivec ( ) || Subtarget . hasQPX ( ) ) getMaxByValAlign ( Ty , Align , Subtarget . hasQPX ( ) ? <NUM_LIT> : <NUM_LIT> ) ; return Align


<s> static unsigned getType ( const TargetRegisterClass * RC ) { if ( RC == & <STR_LIT> ) return unsigned ( <STR_LIT> :: I32 ) ; if ( RC == & <STR_LIT> ) return unsigned ( <STR_LIT> :: I64 ) ; if ( RC == & <STR_LIT> ) return unsigned ( <STR_LIT> :: F32 ) ; if ( RC == & <STR_LIT> ) return unsigned ( <STR_LIT> :: F64 ) ; llvm_unreachable ( <STR_LIT>


<s> return __builtin_aarch64_simd_bslv2df_suss ( __a ,


<s> unsigned InstOffset = <NUM_LIT> ; DenseMap < const MachineBasicBlock * , unsigned > BlockToInstOffset ; const <ISA_LIT>InstrInfo * HII = static_cast < const <ISA_LIT>InstrInfo * > ( MF . getSubtarget ( ) . getInstrInfo ( ) ) ; for ( const MachineBasicBlock & MBB : MF ) { if ( MBB . getLogAlignment ( ) ) { int ByteAlign = ( <NUM_LIT> << MBB . getLogAlignment ( ) ) - <NUM_LIT> ; InstOffset = ( InstOffset + ByteAlign ) & ~ ( ByteAlign ) ; } BlockToInstOffset [ & MBB ]


<s> regno >= mmix_first_vararg_reg ; regno -- ) { if ( offset < <NUM_LIT> ) { HOST_WIDE_INT stack_chunk = stack_space_to_allocate > ( <NUM_LIT> - <NUM_LIT> ) ? ( <NUM_LIT> - <NUM_LIT> ) : stack_space_to_allocate ; mmix_emit_sp_add ( - stack_chunk ) ; offset += stack_chunk ; stack_space_to_allocate -= stack_chunk ; } emit_move_insn ( gen_rtx_MEM ( DImode , plus_constant ( stack_pointer_rtx , offset ) ) , gen_rtx_REG ( DImode , regno ) ) ; offset -= <NUM_LIT> ; } } if ( frame_pointer_needed ) { rtx insn ; if ( offset < <NUM_LIT> ) { HOST_WIDE_INT stack_chunk = stack_space_to_allocate > ( <NUM_LIT> - <NUM_LIT> - <NUM_LIT> ) ? ( <NUM_LIT> - <NUM_LIT> - <NUM_LIT> ) : stack_space_to_allocate ; mmix_emit_sp_add ( - stack_chunk ) ; offset += stack_chunk ; stack_space_to_allocate -= stack_chunk ; } insn = emit_move_insn ( gen_rtx_MEM ( DImode , plus_constant ( stack_pointer_rtx , offset ) ) , hard_frame_pointer_rtx ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; insn = emit_insn ( gen_adddi3 ( hard_frame_pointer_rtx , stack_pointer_rtx , GEN_INT ( offset + <NUM_LIT> ) ) ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; offset -= <NUM_LIT> ; } if ( MMIX_CFUN_NEEDS_SAVED_EH_RETURN_ADDRESS ) { rtx tmpreg , retreg ; rtx insn ; if ( offset < <NUM_LIT> ) { HOST_WIDE_INT stack_chunk = stack_space_to_allocate > ( <NUM_LIT> - <NUM_LIT> - <NUM_LIT> ) ? ( <NUM_LIT> - <NUM_LIT> - <NUM_LIT> ) : stack_space_to_allocate ; mmix_emit_sp_add ( - stack_chunk ) ; offset += stack_chunk ; stack_space_to_allocate -= stack_chunk ; } tmpreg = gen_rtx_REG ( DImode , <NUM_LIT> ) ; retreg = gen_rtx_REG ( DImode , MMIX_rJ_REGNUM ) ; emit_move_insn ( tmpreg , retreg ) ; insn = emit_move_insn ( gen_rtx_MEM ( DImode , plus_constant ( stack_pointer_rtx , offset ) ) , tmpreg ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; REG_NOTES ( insn ) = gen_rtx_EXPR_LIST ( REG_FRAME_RELATED_EXPR , gen_rtx_SET ( VOIDmode , gen_rtx_MEM ( DImode , plus_constant ( stack_pointer_rtx , offset ) ) , retreg ) , REG_NOTES ( insn ) ) ; offset -= <NUM_LIT> ; } else if ( MMIX_CFUN_HAS_LANDING_PAD ) offset -= <NUM_LIT> ; if ( MMIX_CFUN_HAS_LANDING_PAD ) { if ( offset < <NUM_LIT> ) { HOST_WIDE_INT stack_chunk = stack_space_to_allocate > ( <NUM_LIT> - <NUM_LIT> - <NUM_LIT> ) ? ( <NUM_LIT> - <NUM_LIT> - <NUM_LIT> ) : stack_space_to_allocate ; mmix_emit_sp_add ( - stack_chunk ) ; offset += stack_chunk ; stack_space_to_allocate -= stack_chunk ; } emit_move_insn ( gen_rtx_REG ( DImode , <NUM_LIT> ) , gen_rtx_REG ( DImode , MMIX_rO_REGNUM ) ) ; emit_move_insn ( gen_rtx_MEM ( DImode , plus_constant ( stack_pointer_rtx , offset ) ) , gen_rtx_REG ( DImode , <NUM_LIT> ) ) ; offset -=


<s> if ( GET_CODE ( x ) == LABEL_REF ) { switch ( aarch64_cmodel ) { case AARCH64_CMODEL_LARGE : return SYMBOL_FORCE_TO_MEM ; case AARCH64_CMODEL_TINY_PIC : case AARCH64_CMODEL_TINY : return SYMBOL_TINY_ABSOLUTE ; case AARCH64_CMODEL_SMALL_PIC : case AARCH64_CMODEL_SMALL : return SYMBOL_SMALL_ABSOLUTE ; default : gcc_unreachable ( ) ; } } if ( GET_CODE ( x ) == SYMBOL_REF ) { if ( aarch64_cmodel == AARCH64_CMODEL_LARGE ) return SYMBOL_FORCE_TO_MEM ; if ( aarch64_tls_symbol_p ( x ) ) return aarch64_classify_tls_symbol ( x ) ; switch ( aarch64_cmodel ) { case AARCH64_CMODEL_TINY : if ( SYMBOL_REF_WEAK ( x ) || INTVAL ( offset ) < - <NUM_LIT> || INTVAL ( offset ) > <NUM_LIT> ) return SYMBOL_FORCE_TO_MEM ; return SYMBOL_TINY_ABSOLUTE ; case AARCH64_CMODEL_SMALL : if ( SYMBOL_REF_WEAK ( x ) || ! IN_RANGE ( INTVAL ( offset ) , HOST_WIDE_INT_C ( - <NUM_LIT> ) , HOST_WIDE_INT_C ( <NUM_LIT> ) ) ) return SYMBOL_FORCE_TO_MEM ; return SYMBOL_SMALL_ABSOLUTE


<s> int16x8_t result ; __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT> ( b ) : ) ; return result


<s> SDValue VecOp = ScalarOp . getOperand ( <NUM_LIT> ) ; EVT SrcVT = VecOp . getValueType ( ) ; if ( useSVEForFixedLengthVectorVT ( SrcVT , true ) ) { EVT ContainerVT = getContainerForFixedLengthVector ( DAG , SrcVT ) ; VecOp = convertToScalableVector ( DAG , ContainerVT , VecOp ) ; } EVT ResVT = ( Opcode == <STR_LIT> ) ? <STR_LIT> : SrcVT . getVectorElementType ( ) ; EVT RdxVT = SrcVT ; if ( SrcVT . isFixedLengthVector ( ) || Opcode == <STR_LIT> ) RdxVT = getPackedSVEVectorVT ( ResVT ) ; SDValue Pg = getPredicateForVector ( DAG , DL , SrcVT


<s> return TargetTransformInfo ( <ISA_LIT>TTIImpl ( this ,


<s> InConstantPool = false ; OutStreamer . EmitDataRegion ( MCDR_DataRegionEnd


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case


<s> return FS ; case DFmode : return FT ; default : return I64


<s> default : break ; case <STR_LIT> : if ( isa < ConstantSDNode > ( V . getOperand ( <NUM_LIT> ) ) ) { unsigned RotAmt = V . getConstantOperandVal ( <NUM_LIT> ) ; SmallVector < ValueBit , <NUM_LIT> > LHSBits ( Bits . size ( ) ) ; getValueBits ( V . getOperand ( <NUM_LIT> ) , LHSBits ) ; for ( unsigned i = <NUM_LIT> ; i < Bits . size ( ) ; ++ i ) Bits [ i ] = LHSBits [ i < RotAmt ? i + ( Bits . size ( ) - RotAmt ) : i - RotAmt ] ; return true ; } break ; case <STR_LIT> : if ( isa < ConstantSDNode > ( V . getOperand ( <NUM_LIT> ) ) ) { unsigned ShiftAmt = V . getConstantOperandVal ( <NUM_LIT> ) ; SmallVector < ValueBit , <NUM_LIT> > LHSBits ( Bits . size ( ) ) ; getValueBits ( V . getOperand ( <NUM_LIT> ) , LHSBits ) ; for ( unsigned i = ShiftAmt ; i < Bits . size ( ) ; ++ i ) Bits [ i ] = LHSBits [ i - ShiftAmt ] ; for ( unsigned i = <NUM_LIT> ; i < ShiftAmt ; ++ i ) Bits [ i ] = ValueBit ( ValueBit :: ConstZero ) ; return true ; } break ; case <STR_LIT> : if ( isa < ConstantSDNode > ( V . getOperand (


<s> const MachineOperand & Src = MI -> getOperand ( <NUM_LIT> ) ; const MachineOperand & Dest = MI -> getOperand ( <NUM_LIT> ) ; NewMI = BuildMI ( * MF , MI -> getDebugLoc ( ) , TII -> get ( MI -> getOpcode ( ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> ) ) . addOperand ( Dest ) . addOperand ( Src ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) ; MFI -> insert ( MBBI , NewMI ) ; return NewMI ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> bool Is128 = VecIntVT == <STR_LIT> ; EVT VecFloatVT = Is128 ? <STR_LIT> : <STR_LIT> ; if ( VecFloatVT != Op -> getValueType ( <NUM_LIT> ) ) return SDValue ( ) ; unsigned NumElts = VecIntVT . getVectorNumElements ( ) ; assert ( ( VecIntVT == <STR_LIT> || VecIntVT == <STR_LIT> ) && <STR_LIT> ) ; assert ( NumElts <= <NUM_LIT> && <STR_LIT> ) ; SDValue CstLow = DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; SDValue CstLowArray [ ] = { CstLow , CstLow , CstLow , CstLow , CstLow , CstLow , CstLow , CstLow } ; SDValue VecCstLow = DAG . getNode ( <STR_LIT> , DL , VecIntVT , makeArrayRef ( & CstLowArray [ <NUM_LIT> ] , NumElts ) ) ; SDValue CstHigh = DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; SDValue CstHighArray [ ] = { CstHigh , CstHigh , CstHigh , CstHigh , CstHigh , CstHigh , CstHigh , CstHigh } ; SDValue VecCstHigh = DAG . getNode ( <STR_LIT> , DL , VecIntVT , makeArrayRef ( & CstHighArray [ <NUM_LIT> ] , NumElts ) ) ; SDValue CstShift = DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; SDValue CstShiftArray [ ] = { CstShift , CstShift , CstShift , CstShift , CstShift , CstShift , CstShift , CstShift } ; SDValue VecCstShift = DAG . getNode ( <STR_LIT> , DL , VecIntVT , makeArrayRef ( & CstShiftArray [ <NUM_LIT> ] , NumElts ) ) ; SDValue HighShift = DAG . getNode ( <STR_LIT> , DL , VecIntVT , V , VecCstShift ) ; SDValue Low , High ; if ( Subtarget . hasSSE41 ( ) ) { EVT VecI16VT = Is128 ?


<s> bool <ISA_LIT>AsmPrinter :: runOnMachineFunction ( MachineFunction & MF ) { Subtarget = & MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; <ISA_LIT>FI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; if ( Subtarget -> in<ISA_LIT>16Mode ( ) ) for ( const auto & I : <ISA_LIT>FI -> StubsNeeded ) { const char * Symbol = I . first ; const <STR_LIT> * Signature = I .


<s> if ( ! insn_entry [ uid2 ] . is_load || ! insn_entry [ uid2 ] . is_swap ) return false ; rtx body = PATTERN ( def_insn ) ; if ( GET_CODE ( body ) != SET || GET_CODE ( SET_SRC ( body ) ) != VEC_SELECT || GET_CODE ( XEXP ( SET_SRC ( body ) , <NUM_LIT> ) ) != MEM ) return false ; rtx mem = XEXP ( SET_SRC ( body )


<s> <STR_LIT> CC = cast < CondCodeSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> get ( ) ; SDValue LHS = Op . getOperand ( <NUM_LIT> ) ; SDValue RHS = Op . getOperand ( <NUM_LIT> ) ; EVT CmpVT = LHS . getValueType ( ) . changeVectorElementTypeToInteger ( ) ; SDLoc dl ( Op ) ; if ( LHS . getValueType ( ) . getVectorElementType ( ) . isInteger ( ) ) { assert ( LHS . getValueType ( ) == RHS . getValueType ( ) ) ; <STR_LIT> <ISA_LIT>CC = changeIntCCTo<ISA_LIT>CC ( CC ) ; SDValue Cmp = EmitVectorComparison ( LHS , RHS , <ISA_LIT>CC , false , CmpVT , dl , DAG ) ; return DAG . getSExtOrTrunc ( Cmp , dl , Op . getValueType ( ) ) ; } const bool FullFP16 = static_cast < const <ISA_LIT>Subtarget & > ( DAG . getSubtarget ( ) ) . hasFullFP16 ( ) ; if ( ! FullFP16 && LHS . getValueType ( ) . getVectorElementType ( ) == <STR_LIT> ) { if ( LHS . getValueType ( ) . getVectorNumElements ( ) == <NUM_LIT> ) { LHS = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , LHS ) ; RHS = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , RHS ) ; SDValue NewSetcc = DAG . getSetCC ( dl , <STR_LIT> , LHS , RHS , CC ) ; DAG . ReplaceAllUsesWith ( Op , NewSetcc ) ; CmpVT = <STR_LIT> ; } else return SDValue ( ) ; } assert ( ( ! FullFP16 && LHS . getValueType ( ) . getVectorElementType ( ) != <STR_LIT> ) || LHS . getValueType ( ) . getVectorElementType ( ) != <STR_LIT> ) ; <STR_LIT> CC1 , CC2 ; bool ShouldInvert ; changeVectorFPCCTo<ISA_LIT>CC ( CC , CC1 , CC2 , ShouldInvert ) ; bool NoNaNs = getTargetMachine ( ) . Options . NoNaNsFPMath ; SDValue Cmp = EmitVectorComparison ( LHS , RHS , CC1 , NoNaNs , CmpVT , dl , DAG ) ; if ( ! Cmp . getNode ( ) ) return SDValue ( ) ; if ( CC2 != <STR_LIT> ) { SDValue Cmp2 = EmitVectorComparison ( LHS , RHS , CC2 , NoNaNs , CmpVT , dl , DAG ) ; if ( ! Cmp2 . getNode (


<s> if ( STI . hasFeature ( <STR_LIT> ) ) Arch = <STR_LIT> ; if ( STI . hasFeature ( <STR_LIT> ) ) Arch += <STR_LIT> ; else Arch += <STR_LIT> ; if ( STI . hasFeature ( <STR_LIT> ) ) Arch += <STR_LIT> ; if ( STI . hasFeature ( <STR_LIT> ) ) Arch += <STR_LIT> ; if ( STI . hasFeature ( <STR_LIT> ) ) Arch += <STR_LIT> ; if ( STI . hasFeature ( <STR_LIT>


<s> Inst . addOperand ( MCOperand :: createImm ( Val ) ) ; return MCDisassembler


<s> default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT>


<s> break ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT>


<s> const_rtx dest = XEXP ( x , <NUM_LIT> ) ; if ( REG_P ( dest ) && REGNO ( dest ) >= <NUM_LIT> && REGNO ( dest ) < <NUM_LIT> )


<s> initialize<ISA_LIT>AvoidSFBPassPass ( * PassRegistry :: getPassRegistry


<s> if ( isSCC ( CCReg , MRI ) ) { int Opcode = getS_CMPOpcode ( Pred , Size ) ; if ( Opcode == - <NUM_LIT> ) return false ; MachineInstr * ICmp = BuildMI ( * BB , & I , DL , TII . get ( Opcode ) ) . add ( I . getOperand ( <NUM_LIT> ) ) . add ( I . getOperand ( <NUM_LIT> ) ) ; BuildMI ( * BB , & I , DL , TII . get ( <STR_LIT> ) , CCReg ) . addReg ( <STR_LIT> ) ; bool Ret = constrainSelectedInstRegOperands ( * ICmp , TII , TRI , RBI ) && RBI . constrainGenericRegister ( CCReg , <STR_LIT> , MRI ) ; I . eraseFromParent ( ) ; return Ret


<s> emit_insn ( gen_andhi3 ( temp , temp , GEN_INT ( <NUM_LIT> ) ) ) ; emit_insn ( gen_iorhi3 ( temp , temp , GEN_INT ( <NUM_LIT> ) ) ) ; emit_move_insn ( reg_addr_mem , temp ) ; emit_insn ( gen_addhi3 ( reg_addr , reg_addr , const2_rtx ) ) ; reg_addr_mem = adjust_automodify_address ( reg_addr_mem , VOIDmode , NULL , <NUM_LIT> ) ; emit_insn ( gen_lshrhi3 ( reg_fnaddr , reg_fnaddr , GEN_INT (


<s> if ( Kind . isBSS ( ) && IsGlobalInSmallSection ( GV , TM , Kind ) ) return SmallBSSSection ; if ( Kind . isDataNoRel ( ) && IsGlobalInSmallSection ( GV , TM , Kind


<s> MCSubtargetInfo * X = create<ISA_LIT>MCSubtargetInfoImpl ( TT , CPUName , ArchFS ) ; if ( X -> getFeatureBits ( ) [ <STR_LIT> ] ) { llvm :: FeatureBitset Features = X -> getFeatureBits ( ) ; X -> setFeatureBits ( Features . set ( <STR_LIT> ) ) ; } return


<s> x = PATTERN ( insn ) ; if ( GET_CODE ( x ) != SET ) return SCHED_FUSION_NONE ; src = SET_SRC ( x ) ; dest = SET_DEST ( x ) ; machine_mode dest_mode = GET_MODE ( dest ) ; if ( ! aarch64_mode_valid_for_sched_fusion_p ( dest_mode ) ) return SCHED_FUSION_NONE ; if ( GET_CODE ( src ) == SIGN_EXTEND ) { fusion = SCHED_FUSION_LD_SIGN_EXTEND ; src = XEXP ( src , <NUM_LIT> ) ; if ( GET_CODE ( src ) != MEM || GET_MODE ( src ) != SImode ) return SCHED_FUSION_NONE ; } else if ( GET_CODE ( src ) == ZERO_EXTEND ) { fusion = SCHED_FUSION_LD_ZERO_EXTEND ; src = XEXP ( src , <NUM_LIT> ) ; if ( GET_CODE ( src ) != MEM || GET_MODE ( src ) != SImode ) return SCHED_FUSION_NONE ; } if ( GET_CODE ( src ) == MEM && REG_P ( dest ) ) extract_base_offset_in_addr ( src , base , offset ) ; else if ( GET_CODE ( dest ) == MEM && ( REG_P ( src ) || src == const0_rtx ) ) { fusion = SCHED_FUSION_ST ; extract_base_offset_in_addr ( dest , base , offset ) ; } else return SCHED_FUSION_NONE ; if ( * base == NULL_RTX || * offset == NULL_RTX ) fusion = SCHED_FUSION_NONE ; return


<s> else { return false ; } SmallVectorImpl < CCValAssign > & PendingMembers = State . getPendingLocs ( ) ; PendingMembers . push_back ( CCValAssign :: getPending ( ValNo , ValVT , LocVT , LocInfo ) ) ; if ( ! ArgFlags . isInConsecutiveRegsLast ( ) ) return true ; unsigned RegResult = State . AllocateRegBlock ( RegList , PendingMembers . size ( ) ) ; if ( RegResult ) { for ( auto & It : PendingMembers ) { It . convertToReg ( RegResult ) ; State . addLoc ( It


<s> bool <ISA_LIT>TargetLowering :: isOffsetFoldingLegal ( const GlobalAddressSDNode * GA ) const { return


<s> auto ceil = [ ] ( unsigned A , unsigned B ) { return ( A + B - <NUM_LIT> ) / B ; } ; unsigned NumElts = cast < FixedVectorType > ( VecTy ) -> getNumElements ( ) ; assert ( Factor > <NUM_LIT> && NumElts % Factor == <NUM_LIT> && <STR_LIT> ) ; unsigned VF = NumElts / Factor ; unsigned NumEltsPerVecReg = ( <NUM_LIT> / getScalarSizeInBits ( VecTy ) ) ; unsigned NumVectorMemOps = getNumVectorRegs ( VecTy ) ; unsigned NumPermutes = <NUM_LIT> ; if ( Opcode == Instruction :: Load ) { BitVector UsedInsts ( NumVectorMemOps , false ) ; std :: vector < BitVector > ValueVecs ( Factor , BitVector ( NumVectorMemOps , false ) ) ; for ( unsigned Index : Indices ) for ( unsigned Elt = <NUM_LIT> ; Elt < VF ; ++ Elt ) { unsigned Vec = ( Index + Elt * Factor ) / NumEltsPerVecReg ; UsedInsts . set ( Vec ) ; ValueVecs [ Index ] . set ( Vec ) ; } NumVectorMemOps = UsedInsts . count ( ) ; for ( unsigned Index : Indices ) { unsigned NumSrcVecs = ValueVecs [ Index ] . count ( ) ; unsigned NumDstVecs = ceil ( VF * getScalarSizeInBits ( VecTy )


<s> void markPhysRegUsed ( unsigned PhysReg


<s> for ( _Iterator RegI = First ; RegI != End ; ++ RegI ) { Register Reg = * RegI ; if ( ! Reg . isVirtual ( ) ) continue ; PSetIterator PSetI = MRI . getPressureSets ( Reg ) ; for ( ; PSetI . isValid ( ) ; ++ PSetI ) { if ( * PSetI == <STR_LIT> :: VGPR_32 ) VgprUsage += PSetI . getWeight ( ) ; else if ( * PSetI == <STR_LIT> :: SReg_32 ) SgprUsage += PSetI


<s> assert ( OldOpc != NewOpc && <STR_LIT> ) ; unsigned OrigSrc0 = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned OrigSrc1 = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Src0 = <NUM_LIT> , SubReg0 ; unsigned Src1 = <NUM_LIT> , SubReg1 ; bool KillSrc0 = false , KillSrc1 = false ; if ( ! MRI -> def_empty ( OrigSrc0 ) ) { MachineRegisterInfo :: def_instr_iterator Def = MRI -> def_instr_begin ( OrigSrc0 ) ; assert ( std :: next ( Def ) == MRI -> def_instr_end ( ) && <STR_LIT> ) ; MachineOperand * MOSrc0 = getSrcFromCopy ( & * Def , MRI , SubReg0 ) ; if ( MOSrc0 ) { Src0 = MOSrc0 -> getReg ( ) ; KillSrc0 = MOSrc0 -> isKill ( ) ; MOSrc0 -> setIsKill ( false ) ; if ( MRI -> hasOneNonDBGUse ( OrigSrc0 ) ) { assert ( MOSrc0 && <STR_LIT> ) ; Def -> eraseFromParent ( ) ; ++ NumCopiesDeleted ; } } } if ( ! MRI -> def_empty ( OrigSrc1 ) ) { MachineRegisterInfo :: def_instr_iterator Def = MRI -> def_instr_begin ( OrigSrc1 ) ; assert ( std :: next ( Def ) == MRI -> def_instr_end ( ) && <STR_LIT> ) ; MachineOperand * MOSrc1 = getSrcFromCopy ( & * Def , MRI , SubReg1 ) ; if ( MOSrc1 ) { Src1 = MOSrc1 -> getReg ( ) ; KillSrc1 = MOSrc1 -> isKill ( ) ; MOSrc1 -> setIsKill ( false ) ; if ( MRI -> hasOneNonDBGUse ( OrigSrc1 ) ) { assert ( MOSrc1 && <STR_LIT> ) ; Def -> eraseFromParent ( ) ; ++ NumCopiesDeleted ; } } } if ( ! Src0 ) { SubReg0 = <NUM_LIT> ; Src0 = MRI -> createVirtualRegister ( & <STR_LIT> ) ; insertCopy ( TII , MI , Src0 , OrigSrc0 , KillSrc0 ) ; KillSrc0 = true ; } if ( ! Src1 ) { SubReg1 = <NUM_LIT> ; Src1 = MRI -> createVirtualRegister ( & <STR_LIT> ) ; insertCopy ( TII , MI , Src1 , OrigSrc1 , KillSrc1 ) ; KillSrc1 =


<s> bool <ISA_LIT>InstrInfo :: ReverseBranchCondition ( SmallVectorImpl < MachineOperand > & Cond ) const { assert ( Cond . size ( ) == <NUM_LIT>


<s> const unsigned PtrByteSize = Is<ISA_LIT>64 ? <NUM_LIT> : <NUM_LIT> ; static const MCPhysReg GPR_32 [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; static const MCPhysReg GPR_64 [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; switch ( ValVT . SimpleTy ) { default : report_fatal_error ( <STR_LIT> ) ; case <STR_LIT> : assert ( Is<ISA_LIT>64 && <STR_LIT> ) ; LLVM_FALLTHROUGH ; case <STR_LIT> : case <STR_LIT> : State . AllocateStack ( PtrByteSize , PtrByteSize ) ; if ( unsigned Reg = State . AllocateReg ( Is<ISA_LIT>64 ? GPR_64 : GPR_32 ) ) { MVT RegVT = Is<ISA_LIT>64 ? <STR_LIT> : <STR_LIT> ; if ( ValVT . getSizeInBits ( ) < RegVT . getSizeInBits ( ) ) LocInfo = ArgFlags . isSExt ( ) ? CCValAssign :: LocInfo :: SExt : CCValAssign :: LocInfo :: ZExt ; State . addLoc ( CCValAssign :: getReg ( ValNo , ValVT , Reg , RegVT , LocInfo ) ) ; } else report_fatal_error ( <STR_LIT> <STR_LIT> ) ; return false ; case <STR_LIT> : case <STR_LIT> : { const unsigned StoreSize = LocVT . getStoreSize ( ) ; State . AllocateStack ( Is<ISA_LIT>64 ? <NUM_LIT> : StoreSize , <NUM_LIT> ) ; if ( unsigned Reg = State . AllocateReg ( FPR ) ) State . addLoc ( CCValAssign :: getReg ( ValNo , ValVT , Reg , <STR_LIT> , LocInfo ) ) ; else report_fatal_error ( <STR_LIT> <STR_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i < StoreSize ; i += PtrByteSize

) State . AllocateReg ( Is<ISA_LIT>64 ? GPR_64 : GPR_32 ) ;


<s> return MF . getTarget ( ) . Options . DisableFramePointerElim ( MF

) || MF . getFrameInfo ( ) . hasVarSizedObjects ( ) ;


<s> return ( ET == <STR_LIT> || ET == <STR_LIT> || ET == <STR_LIT> || ET == <STR_LIT> || ET == <STR_LIT> || ET == <STR_LIT> || ET == <STR_LIT> || ET

== <STR_LIT> || ET == <STR_LIT> ) && getShiftExtendAmount ( ) <= <NUM_LIT> ;


<s> const Function & F = MF . getFunction ( ) ; if ( ! OutlineFromLinkOnceODRs && F . hasLinkOnceODRLinkage ( ) ) return false ; if ( F . hasSection ( ) ) return


<s> if ( NeedTrunc ) { Op0Reg = emitAND_ri ( <STR_LIT> , Op0Reg , Op0IsKill , Mask ) ; Op1Reg = emitAND_ri ( <STR_LIT> , Op1Reg , Op1IsKill , Mask ) ; Op0IsKill = Op1IsKill = true ; } unsigned ResultReg = FastEmitInst_rr ( Opc , RC , Op0Reg , Op0IsKill , Op1Reg , Op1IsKill ) ; if ( NeedTrunc ) ResultReg = emitAND_ri ( <STR_LIT> , ResultReg , true , Mask ) ; return ResultReg


<s> Type * Tys [ ] = { Op1 -> getArgOperand ( <NUM_LIT> ) -> getType ( ) } ; Module * M = I -> getParent ( ) -> getParent ( ) -> getParent ( ) ; auto Fn = <STR_LIT> ( M , I -> getIntrinsicID ( ) , Tys ) ; auto CI = CallInst :: Create ( Fn , Ops , I -> getName ( ) , I ) ; I -> replaceAllUsesWith ( CI ) ; I -> eraseFromParent ( ) ; if ( Op1 -> use_empty ( ) ) Op1 -> eraseFromParent ( ) ; if ( Op2 -> use_empty ( )


<s> static rtx F ( rtx x ) { RTX_FRAME_RELATED_P ( x ) = <NUM_LIT> ; return


<s> return CreateReg ( Index , RegKind_MSACtrl , RegInfo , S , E


<s> EmitBranchToAt ( CameFromStub , Target ) ; } else { DOUT ( llvm :: dbgs ( ) << <STR_LIT> << CameFromStub << <STR_LIT> << oldpv <<


<s> } if ( ! ST . isVGPRSpillingEnabled ( * MF -> getFunction ( ) ) ) { LLVMContext & Ctx = MF -> getFunction ( ) -> getContext ( ) ; Ctx . emitError ( <STR_LIT> <STR_LIT> ) ; BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , DestReg ) ; return ; } assert ( RI . hasVGPRs ( RC ) && <STR_LIT> ) ; unsigned Opcode = getVGPRSpillRestoreOpcode ( SpillSize ) ; BuildMI ( MBB , MI , DL , get ( Opcode ) , DestReg ) . addFrameIndex ( FrameIndex ) . addReg ( MFI -> getScratchRSrcReg ( ) ) . addReg ( MFI -> getFrameOffsetReg (

) ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ;


<s> std :: vector < const GlobalVariable * > Items = ExternalVarDefs ; if ( ! Items . size ( ) ) return ; O << <STR_LIT> << MAI -> getCommentString ( ) << <STR_LIT> << <STR_LIT> ; for ( unsigned j = <NUM_LIT> ; j < Items . size ( ) ; j ++ ) O << MAI -> getGlobalDirective (

) << * GetGlobalValueSymbol ( Items [ j ] ) << <STR_LIT> ;


<s> if ( ( ! SVOp -> isSplat ( ) ) || SVOp -> getMaskElt ( <NUM_LIT> ) != <NUM_LIT> ) return SDValue ( ) ; SDValue Sc = Op . getOperand ( <NUM_LIT> ) ; if ( Sc . getOpcode ( ) != <STR_LIT> && Sc . getOpcode ( ) != <STR_LIT> ) { if ( ! Subtarget -> hasInt256 ( ) ) return SDValue ( ) ; if ( VT . getSizeInBits ( ) >= <NUM_LIT> ) Sc = Extract128BitVector ( Sc , <NUM_LIT> , DAG , dl ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Sc ) ; } Ld = Sc . getOperand ( <NUM_LIT> ) ; ConstSplatVal = ( Ld . getOpcode ( ) == <STR_LIT> || Ld . getOpcode ( ) == <STR_LIT> ) ; bool hasRegVer = Subtarget -> hasAVX512 ( ) && VT . is512BitVector ( ) && Ld . getValueType ( ) . getSizeInBits ( ) >= <NUM_LIT> ; if ( ! ConstSplatVal && ( ( ! Sc . hasOneUse ( ) || ! Ld . hasOneUse ( ) ) && ! hasRegVer ) ) return SDValue ( ) ; break ; } } bool IsGE256 = ( VT . getSizeInBits ( ) >= <NUM_LIT> ) ; if ( ConstSplatVal && Subtarget -> hasInt256 ( ) ) { EVT CVT = Ld . getValueType ( ) ; assert ( ! CVT . isVector ( ) && <STR_LIT> ) ; unsigned ScalarSize = CVT . getSizeInBits ( ) ; if ( ScalarSize == <NUM_LIT> || ( IsGE256 && ScalarSize == <NUM_LIT> ) ) { const Constant * C = nullptr ; if ( ConstantSDNode * CI = dyn_cast < ConstantSDNode > ( Ld ) ) C = CI -> getConstantIntValue ( ) ; else if ( ConstantFPSDNode * CF = dyn_cast < ConstantFPSDNode > ( Ld ) ) C = CF -> getConstantFPValue ( ) ; assert ( C && <STR_LIT> ) ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; SDValue CP = DAG . getConstantPool ( C , TLI . getPointerTy ( ) ) ; unsigned Alignment = cast < ConstantPoolSDNode > ( CP ) -> getAlignment ( ) ; Ld = DAG . getLoad ( CVT , dl , DAG . getEntryNode ( ) , CP , MachinePointerInfo :: getConstantPool ( ) ,


<s> int visium_interrupt_function_p ( void ) { return lookup_attribute ( <STR_LIT> , DECL_ATTRIBUTES ( current_function_decl )


<s> copyByValRegs ( SDValue Chain , DebugLoc DL , std :: vector < SDValue > & OutChains , SelectionDAG & DAG , const <STR_LIT> & Flags , SmallVectorImpl < SDValue > & InVals , const Argument * FuncArg , const <ISA_LIT>CC & CC , const ByValArgInfo & ByVal ) const { MachineFunction & MF = DAG . getMachineFunction ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; unsigned RegAreaSize = ByVal . NumRegs * CC . regSize ( ) ; unsigned FrameObjSize = std :: max ( Flags . getByValSize ( ) , RegAreaSize ) ; int FrameObjOffset ; if ( RegAreaSize ) FrameObjOffset = ( int ) CC . reservedArgArea ( ) - ( int ) ( ( CC . numIntArgRegs ( ) - ByVal . FirstIdx ) * CC . regSize ( ) ) ; else FrameObjOffset = ByVal . Address ; EVT PtrTy = getPointerTy ( ) ; int FI = MFI -> CreateFixedObject ( FrameObjSize , FrameObjOffset , true ) ; SDValue FIN = DAG . getFrameIndex ( FI , PtrTy ) ; InVals . push_back ( FIN ) ; if ( ! ByVal . NumRegs ) return ; EVT RegTy = <STR_LIT> ( CC . regSize ( ) * <NUM_LIT> ) ; const TargetRegisterClass * RC = getRegClassFor ( RegTy ) ; for ( unsigned I = <NUM_LIT> ; I < ByVal . NumRegs ; ++ I ) { unsigned ArgReg = CC . intArgRegs ( ) [ ByVal . FirstIdx + I ] ; unsigned VReg = AddLiveIn ( MF , ArgReg ,


<s> else if ( I . getOpcode ( ) == Instruction :: ICmp ) convertICmp ( cast < CmpInst > ( I ) ) ; } if ( ConvertedInsts . empty ( ) ) return false ; while ( ! LogicOpsWorklist . empty ( ) ) { BinaryOperator * Op = LogicOpsWorklist . back ( ) ; LogicOpsWorklist . pop_back ( ) ; if ( ConvertedInsts . count ( dyn_cast < Instruction > ( Op -> getOperand ( <NUM_LIT> ) ) ) && ConvertedInsts . count ( dyn_cast < Instruction > ( Op -> getOperand ( <NUM_LIT> ) ) ) && ! ConvertedInsts . count ( Op ) ) convertLogicOp ( * Op ) ; } Module & M = * F . getParent ( ) ; auto & Ctx = M . getContext ( ) ; Value * Zero32 = ConstantInt :: get ( Type :: getInt32Ty ( Ctx ) , <NUM_LIT> ) ; bool MadeChange = false ; for ( auto & It : reverse ( ConvertedInsts ) ) { Instruction * I = It . first ; Value * V ; int Mask ; bool Worthy ; std :: tie ( V , Mask , Worthy ) = It . second ; if ( ! I -> user_empty ( ) ) { if ( ! Worthy ) continue ; Function * TDCFunc = <STR_LIT> ( & M , <STR_LIT> , V -> getType ( ) ) ; IRBuilder < > IRB ( I ) ; Value * MaskVal = ConstantInt :: get ( Type :: getInt64Ty ( Ctx ) , Mask ) ; Instruction * TDC = IRB . CreateCall ( TDCFunc , { V , MaskVal } ) ; Value * ICmp = IRB . CreateICmp ( CmpInst :: ICMP_NE , TDC , Zero32 ) ; I -> replaceAllUsesWith ( ICmp ) ; } I -> eraseFromParent


<s> MachineInstr & MI = * I ; const DebugLoc & dl = MI . getDebugLoc ( ) ; ASSERT_SORTED ( PopTable ) ; if ( StackTop == <NUM_LIT> ) report_fatal_error ( <STR_LIT> ) ; RegMap [ Stack [ -- StackTop ] ] = ~ <NUM_LIT> ; int Opcode = Lookup ( PopTable , I -> getOpcode ( ) ) ; if ( Opcode != - <NUM_LIT> ) { I -> setDesc ( TII -> get ( Opcode ) ) ; if ( Opcode == <STR_LIT> ) I -> RemoveOperand


<s> void MetadataStreamerV3 :: emitKernelAttrs ( const Function & Func , msgpack :: MapDocNode Kern ) { if ( auto Node = Func . getMetadata ( <STR_LIT> ) ) Kern [ <STR_LIT> ] = getWorkGroupDimensions ( Node ) ; if ( auto Node = Func . getMetadata ( <STR_LIT> ) ) Kern [ <STR_LIT> ] = getWorkGroupDimensions ( Node ) ; if ( auto Node = Func . getMetadata ( <STR_LIT> ) ) { Kern [ <STR_LIT> ] = Kern . getDocument ( ) -> getNode ( getTypeName ( cast < ValueAsMetadata > ( Node -> getOperand ( <NUM_LIT> ) ) -> getType ( ) , mdconst :: extract < ConstantInt > ( Node -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ) , true ) ; } if ( Func . hasFnAttribute ( <STR_LIT> ) ) { Kern [ <STR_LIT> ] = Kern . getDocument ( ) -> getNode ( Func . getFnAttribute ( <STR_LIT> ) . getValueAsString ( ) . str (


<s> MCInstrInfo * X = new MCInstrInfo ( ) ; Init<ISA_LIT>MCInstrInfo ( X ) ; return X


<s> static __inline vec_double2 spu_slqwbytebc ( vec_double2 a , unsigned int count ) { return ( ( vec_double2 ) ( si_shlqbybi ( ( qword ) ( a ) , si_from_uint (


<s> if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = <STR_LIT> ; assert ( Opc && <STR_LIT> ) ; BuildMI ( MBB , I , DL , get ( Opc ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) .


<s> assert ( Width == <NUM_LIT> && <STR_LIT> ) ; MachineInstr & MI = * MBBI ; DebugLoc DL = MI . getDebugLoc ( ) ; MachineFunction * MF = MBB . getParent ( ) ; auto LoopHeadMBB = MF -> CreateMachineBasicBlock ( MBB . getBasicBlock ( ) ) ; auto LoopIfBodyMBB = MF -> CreateMachineBasicBlock ( MBB . getBasicBlock ( ) ) ; auto LoopTailMBB = MF -> CreateMachineBasicBlock ( MBB . getBasicBlock ( ) ) ; auto DoneMBB = MF -> CreateMachineBasicBlock ( MBB . getBasicBlock ( ) ) ; MF -> insert ( ++ MBB . getIterator ( ) , LoopHeadMBB ) ; MF -> insert ( ++ LoopHeadMBB -> getIterator ( ) , LoopIfBodyMBB ) ; MF -> insert ( ++ LoopIfBodyMBB -> getIterator ( ) , LoopTailMBB ) ; MF -> insert ( ++ LoopTailMBB -> getIterator ( ) , DoneMBB ) ; LoopHeadMBB -> addSuccessor ( LoopIfBodyMBB ) ; LoopHeadMBB -> addSuccessor ( LoopTailMBB ) ; LoopIfBodyMBB -> addSuccessor ( LoopTailMBB ) ; LoopTailMBB -> addSuccessor ( LoopHeadMBB ) ; LoopTailMBB -> addSuccessor ( DoneMBB ) ; DoneMBB -> splice ( DoneMBB -> end ( ) , & MBB , MI , MBB . end ( ) ) ; DoneMBB -> transferSuccessors ( & MBB ) ; MBB . addSuccessor ( LoopHeadMBB ) ; Register DestReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register Scratch1Reg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register Scratch2Reg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register AddrReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register IncrReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register MaskReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; bool IsSigned = BinOp == AtomicRMWInst :: Min || BinOp == AtomicRMWInst :: Max ; AtomicOrdering Ordering = static_cast < AtomicOrdering > ( MI . getOperand ( IsSigned ? <NUM_LIT> : <NUM_LIT>


<s> } if ( ! noepilogue ) { unsigned int var_size = current_frame_info . var_size ; unsigned int args_size = current_frame_info . args_size ; unsigned int gmask = current_frame_info . gmask ; int can_trust_sp_p = ! current_function_calls_alloca ; const char * sp_str = reg_names [ STACK_POINTER_REGNUM ] ; const char * fp_str = reg_names [ FRAME_POINTER_REGNUM ] ; if ( can_trust_sp_p ) { unsigned int reg_offset = var_size + args_size ; if ( reg_offset == <NUM_LIT> ) ; else if ( reg_offset < <NUM_LIT> ) fprintf ( file , <STR_LIT> , sp_str , IMMEDIATE_PREFIX , reg_offset ) ; else if ( reg_offset < <NUM_LIT> ) fprintf ( file , <STR_LIT> , sp_str , sp_str , IMMEDIATE_PREFIX , reg_offset ) ; else if ( reg_offset < ( <NUM_LIT> << <NUM_LIT> ) ) fprintf ( file , <STR_LIT> , reg_names [ PROLOGUE_TMP_REGNUM ] , IMMEDIATE_PREFIX , reg_offset , sp_str , reg_names [ PROLOGUE_TMP_REGNUM ] ) ; else fprintf ( file , <STR_LIT> , reg_names [ PROLOGUE_TMP_REGNUM ] , IMMEDIATE_PREFIX , reg_offset >> <NUM_LIT> , reg_names [ PROLOGUE_TMP_REGNUM ] , reg_names [ PROLOGUE_TMP_REGNUM ] , IMMEDIATE_PREFIX , reg_offset & <NUM_LIT> , sp_str , reg_names [ PROLOGUE_TMP_REGNUM ] ) ; } else if ( frame_pointer_needed ) { unsigned int reg_offset = var_size + args_size ; if ( reg_offset == <NUM_LIT> ) fprintf ( file , <STR_LIT> , sp_str , fp_str ) ; else if ( reg_offset < <NUM_LIT> ) fprintf ( file , <STR_LIT> , sp_str , fp_str , IMMEDIATE_PREFIX , reg_offset ) ; else if ( reg_offset < ( <NUM_LIT> << <NUM_LIT> ) ) fprintf ( file , <STR_LIT> , reg_names [ PROLOGUE_TMP_REGNUM ] , IMMEDIATE_PREFIX , reg_offset , sp_str , reg_names [ PROLOGUE_TMP_REGNUM ] ) ; else fprintf ( file , <STR_LIT> , reg_names [ PROLOGUE_TMP_REGNUM ] , IMMEDIATE_PREFIX , reg_offset >> <NUM_LIT> , reg_names [ PROLOGUE_TMP_REGNUM ] , reg_names [ PROLOGUE_TMP_REGNUM ] , IMMEDIATE_PREFIX , reg_offset & <NUM_LIT> , sp_str , reg_names [ PROLOGUE_TMP_REGNUM ] ) ; } else gcc_unreachable ( ) ; if ( current_frame_info . save_lr ) fprintf ( file , <STR_LIT> , reg_names [ RETURN_ADDR_REGNUM ] ) ; gmask &= ~ ( FRAME_POINTER_MASK | RETURN_ADDR_MASK ) ; for ( regno = M32R_MAX_INT_REGS - <NUM_LIT> ; regno >= <NUM_LIT> ; -- regno ) { if ( ( gmask & ( <NUM_LIT> << regno ) ) != <NUM_LIT> ) fprintf ( file , <STR_LIT> , reg_names [ regno ] ) ; } if ( current_frame_info . save_fp ) fprintf ( file , <STR_LIT> , fp_str


<s> else { update_base_p = true ; base_reg = XEXP ( XEXP ( base_addr , <NUM_LIT> ) , <NUM_LIT> ) ; } const char * update_base = update_base_p ? <STR_LIT> : <STR_LIT> ; regno = REGNO ( operands [ <NUM_LIT> ] ) ; otherops [ <NUM_LIT> ] = base_reg ; otherops [ <NUM_LIT> ] = operands [ <NUM_LIT> ] ; if ( regno >= <NUM_LIT> ) { enable4 = nds32_regno_to_enable4 ( regno ) ; sprintf ( buff , <STR_LIT> , update_base , enable4


<s> case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return


<s> gen_neg = gen_negsi2 ; break ; case DImode : gen_neg = gen_negdi2 ; break ; default : gcc_unreachable ( ) ; } e1 = gen_reg_rtx ( inmode ) ; e2 = gen_reg_rtx ( inmode ) ; res = gen_reg_rtx ( outmode ) ; half = CONST_DOUBLE_FROM_REAL_VALUE ( dconsthalf , inmode ) ; emit_insn ( gen_rtx_SET ( VOIDmode , scratch , gen_rtx_UNSPEC ( HImode , gen_rtvec ( <NUM_LIT> , op1 ) , UNSPEC_FXAM ) ) ) ; emit_insn ( gen_abs ( e1 , op1 ) ) ; half = force_reg ( inmode , half ) ; emit_insn ( gen_rtx_SET ( VOIDmode , e2 , gen_rtx_PLUS ( inmode , e1 , half ) ) ) ; if ( inmode != XFmode ) { tmp1 = gen_reg_rtx ( XFmode ) ; emit_insn ( gen_rtx_SET ( VOIDmode , tmp1 , gen_rtx_FLOAT_EXTEND ( XFmode , e2 ) ) ) ; } else tmp1 = e2 ; switch ( outmode ) { case SFmode : case DFmode : { rtx tmp0 = gen_reg_rtx ( XFmode ) ; emit_insn ( gen_frndintxf2_floor ( tmp0 , tmp1 ) ) ; emit_insn ( gen_rtx_SET ( VOIDmode , res , gen_rtx_UNSPEC ( outmode , gen_rtvec ( <NUM_LIT> , tmp0 ) , UNSPEC_TRUNC_NOOP ) ) ) ; } break ; case XFmode : emit_insn ( gen_frndintxf2_floor ( res , tmp1 ) ) ; break ; case HImode


<s> } int64_t Offset ; if ( Def -> getOpcode ( ) == <STR_LIT> ) { if ( mi_match ( Def -> getOperand ( <NUM_LIT> ) . getReg ( ) , MRI , m_ICst ( Offset ) ) ) return std :: make_tuple ( Def -> getOperand ( <NUM_LIT> ) . getReg ( ) , Offset , Def ) ; if ( mi_match ( Def -> getOperand ( <NUM_LIT> ) . getReg ( ) , MRI , m_Copy ( m_ICst ( Offset ) ) ) ) return std :: make_tuple ( Def -> getOperand ( <NUM_LIT> ) . getReg


<s> RegisterTargetMachine < <ISA_LIT>TargetMachine >


<s> void <ISA_LIT>InstPrinter :: printNeonUImm64MaskOperand ( const MCInst * MI , unsigned OpNum , raw_ostream & O ) { const MCOperand & MOUImm8 = MI -> getOperand ( OpNum ) ; assert ( MOUImm8 . isImm ( ) && <STR_LIT> ) ; uint32_t UImm8 = MOUImm8 . getImm ( ) ; uint64_t Mask = <NUM_LIT> ; for ( unsigned ByteNum = <NUM_LIT> ; ByteNum < <NUM_LIT> ; ++ ByteNum ) { if ( ( UImm8 >> ByteNum ) & <NUM_LIT> ) Mask |= ( uint64_t ) <NUM_LIT> << ( <NUM_LIT> * ByteNum ) ; } O <<


<s> return DAG . getNode ( <STR_LIT> , dl , VT , P ) ; } if ( InVT . getScalarSizeInBits ( ) > <NUM_LIT> && ! Subtarget . hasDQI ( ) ) { unsigned BitWidth = InVT . getScalarSizeInBits ( ) ; unsigned NumSignBits = DAG . ComputeNumSignBits ( Op0 ) ; if ( NumSignBits >= ( BitWidth - <NUM_LIT> ) ) { EVT TruncVT = EVT :: getIntegerVT ( * DAG . getContext ( ) , <NUM_LIT> ) ; if ( InVT . isVector ( ) ) TruncVT = EVT :: getVectorVT ( * DAG . getContext ( ) , TruncVT , InVT . getVectorNumElements ( ) ) ; SDLoc dl ( N ) ; SDValue Trunc = DAG . getNode ( <STR_LIT> , dl , TruncVT , Op0 ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Trunc ) ; } } if ( ! Subtarget . useSoftFloat ( ) && Op0 . getOpcode ( )


<s> assert ( SymExpr -> getSymbol ( ) . getName ( ) == <STR_LIT> && <STR_LIT> ) ; return <NUM_LIT> ; } MCFixupKind fixupKind = ( MCFixupKind ) <STR_LIT> ; if ( const <ISA_LIT>MCExpr * SExpr = dyn_cast < <ISA_LIT>MCExpr > ( MO . getExpr ( ) ) ) { if ( SExpr -> getKind ( ) == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_WPLT30 ) fixupKind = ( MCFixupKind ) <STR_LIT> ; } Fixups . push_back ( MCFixup :: create ( <NUM_LIT> , MO . getExpr ( ) , fixupKind ) ) ; return


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , Optional < CodeModel :: Model > CM , CodeGenOpt :: Level OL , bool JIT ) : LLVMTargetMachine ( T , <ISA_LIT>DataLayout , TT , getCPU ( CPU ) , FS , Options , getEffectiveRelocModel (

RM ) , getEffectiveCodeModel ( CM , CodeModel :: Small ) , OL ) , SubTarget ( TT , getCPU ( CPU ) , FS , * this ) {


<s> virtual const <ISA_LIT>Subtarget * getSubtarget ( ) { return


<s> if ( msp430_hwmult_type == MSP430_HWMULT_LARGE ) return true ; if ( target_mcu == NULL || msp430_hwmult_type != MSP430_HWMULT_AUTO ) return false ; if ( target_mcu == cached_match ) return


<s> virtual const TargetFrameInfo * getFrameInfo (


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return


__v2di ) _mm_setzero_di ( ) , ( __mmask8 ) __U ) ;


<s> static void nios2_set_fpu_custom_code ( enum n2fpu_code code , int n , bool override_p ) { if ( override_p || N2FPU_N ( code ) == -


<s> static ScheduleDAGInstrs * create<ISA_LIT>MachineScheduler ( MachineSchedContext * C ) { const <ISA_LIT>Subtarget & ST = C -> MF -> getSubtarget < <ISA_LIT>Subtarget > ( ) ; ScheduleDAGMILive * DAG = new ScheduleDAGMILive ( C , ST . use<ISA_LIT>PreRASchedStrategy ( ) ? std :: make_unique < <ISA_LIT>PreRASchedStrategy > ( C ) : std :: make_unique < GenericScheduler > ( C ) ) ; DAG -> addMutation ( createCopyConstrainDAGMutation ( DAG -> TII , DAG ->


<s> if ( MO . isImm ( ) ) return MO . getImm ( ) >> <NUM_LIT> ; assert ( MO . isExpr ( ) && <STR_LIT> ) ; const MCExpr * Expr =


<s> I = std :: find_if ( B , E , isdigit ) ; Prefix . assign ( B , I - B ) ; if ( I == E ) return std :: make_pair ( true , false ) ; return std :: make_pair ( ! getAsUnsignedInteger ( StringRef ( I , E - I ) , <NUM_LIT> , Reg )


<s> void emitLocalEntry ( MCSymbolELF * S ,


<s> InitI = BuildMI ( MBB , At , dl , HII -> get ( <STR_LIT> ) , DefR ) . add ( ExtOp ) . add ( MachineOperand ( Ex . Rs ) ) ; } else { InitI = BuildMI ( MBB , At , dl , HII -> get ( <STR_LIT> ) , DefR ) . add ( MachineOperand ( Ex . Rs ) ) . add ( ExtOp ) ; } } else { unsigned NewOpc = Ex . Neg ? <STR_LIT> : <STR_LIT> ; InitI = BuildMI ( MBB , At , dl , HII -> get ( NewOpc ) , DefR ) . add ( ExtOp ) . add ( MachineOperand ( Ex . Rs ) ) . addImm ( Ex . S ) ; } } assert ( InitI ) ; ( void ) InitI ; DEBUG ( dbgs ( ) << <STR_LIT> << MBB . getNumber ( ) << <STR_LIT> << PrintInit ( ExtI


<s> return ( __mmask8 ) __builtin_ia32_ucmpd256_mask ( ( __v8si ) __X , ( __v8si )


<s> static bool computeOpenCLImageSupport ( const Triple & TT ) { return


<s> LLVMContext & Context = M . getContext ( ) ; Void = Type :: getVoidTy ( Context ) ; Boolean = Type :: getInt1Ty ( Context ) ; IntMask = ST . isWave32 ( ) ? Type :: getInt32Ty ( Context ) : Type :: getInt64Ty ( Context ) ; ReturnStruct = StructType :: get ( Boolean , IntMask ) ; BoolTrue = ConstantInt :: getTrue ( Context ) ; BoolFalse = ConstantInt :: getFalse ( Context ) ; BoolUndef = UndefValue :: get ( Boolean ) ; IntMaskZero = ConstantInt :: get ( IntMask , <NUM_LIT> ) ; If = <STR_LIT> ( & M , <STR_LIT> , { IntMask } ) ; Else = <STR_LIT> ( & M , <STR_LIT> , { IntMask , IntMask } ) ; IfBreak = <STR_LIT> ( & M , <STR_LIT>


<s> } Stubs . clear ( ) ; OutStreamer . AddBlankLine ( ) ; } Stubs = MMIMacho . GetGVStubList ( ) ; if ( ! Stubs . empty ( ) ) { const MCSection * TheSection = OutContext . getMachOSection ( <STR_LIT> , <STR_LIT> , MachO :: S_NON_LAZY_SYMBOL_POINTERS , SectionKind :: getMetadata ( ) ) ; OutStreamer . SwitchSection ( TheSection ) ; for ( auto & Stub : Stubs ) emitNonLazySymbolPointer ( OutStreamer , Stub . first , Stub . second ) ; Stubs . clear ( ) ; OutStreamer . AddBlankLine ( ) ; } Stubs = MMIMacho . GetHiddenGVStubList ( ) ; if ( ! Stubs . empty ( ) ) { const MCSection * TheSection = OutContext . getMachOSection ( <STR_LIT> , <STR_LIT> , MachO :: S_NON_LAZY_SYMBOL_POINTERS , SectionKind :: getMetadata ( ) ) ; OutStreamer . SwitchSection ( TheSection ) ; for ( auto & Stub : Stubs ) emitNonLazySymbolPointer ( OutStreamer , Stub . first , Stub . second ) ; Stubs . clear ( ) ; OutStreamer . AddBlankLine ( ) ; } SM . serializeToStackMapSection ( ) ; OutStreamer . EmitAssemblerFlag ( MCAF_SubsectionsViaSymbols ) ; } if ( TT . isKnownWindowsMSVCEnvironment ( ) && MMI -> usesVAFloatArgument ( ) ) { StringRef SymbolName = ( TT . getArch ( ) == Triple :: x86_64 ) ? <STR_LIT> : <STR_LIT> ; MCSymbol * S = MMI -> getContext ( ) . GetOrCreateSymbol ( SymbolName ) ; OutStreamer . EmitSymbolAttribute ( S , MCSA_Global ) ; } if ( TT . isOSBinFormatCOFF ( ) ) { std :: vector < const MCSymbol * > DLLExportedFns , DLLExportedGlobals ; for ( const auto & Function : M ) if ( Function . hasDLLExportStorageClass ( ) && ! Function . isDeclaration ( ) ) DLLExportedFns . push_back ( getSymbol ( & Function ) ) ; for ( const auto & Global : M . globals ( ) ) if ( Global . hasDLLExportStorageClass ( ) && ! Global . isDeclaration ( ) ) DLLExportedGlobals . push_back ( getSymbol ( & Global ) ) ; for ( const auto & Alias : M . aliases ( ) ) { if ( ! Alias . hasDLLExportStorageClass ( ) ) continue ; if ( Alias . getType ( ) -> getElementType ( ) -> isFunctionTy ( ) ) DLLExportedFns . push_back ( getSymbol ( & Alias ) ) ; else DLLExportedGlobals . push_back ( getSymbol ( & Alias ) ) ; } if ( ! DLLExportedGlobals . empty ( ) || ! DLLExportedFns . empty ( ) ) { const TargetLoweringObjectFileCOFF & TLOFCOFF = static_cast < const TargetLoweringObjectFileCOFF & > ( getObjFileLowering ( ) ) ; OutStreamer . SwitchSection ( TLOFCOFF . getDrectveSection ( ) ) ; for ( auto & Symbol : DLLExportedGlobals ) GenerateExportDirective ( Symbol , true ) ; for ( auto & Symbol : DLLExportedFns ) GenerateExportDirective ( Symbol , false ) ; } } if ( TT . isOSBinFormatELF ( ) ) SM . serializeToStackMapSection (