<s> switch ( Inst . getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : imm |= <NUM_LIT> ; break ; default : break ; } if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rn , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeT2Imm8 ( Inst , imm ,


<s> int64_t Offset = <NUM_LIT> ; for ( int I = MFI . getObjectIndexBegin ( ) ; I != <NUM_LIT> ; ++ I ) Offset = std :: max ( Offset , - MFI . getObjectOffset ( I ) ) ; for ( const MCPhysReg * R = TRI . getCalleeSavedRegs ( & MF ) ; * R ; ++ R ) { unsigned Size = TRI . getSpillSize ( * TRI . getMinimalPhysRegClass ( * R ) ) ; Offset = alignTo ( Offset + Size , Size ) ; } unsigned MaxAlign = MFI . getMaxAlignment ( ) ; assert ( ! MFI . getObjectIndexEnd ( ) || MaxAlign ) ; for ( unsigned I = <NUM_LIT> , E = MFI . getObjectIndexEnd ( ) ; I != E ; ++ I ) Offset = alignTo ( Offset + MFI . getObjectSize ( I ) , MaxAlign ) ; if ( MFI . adjustsStack ( ) && hasReservedCallFrame ( MF ) ) Offset = alignTo ( Offset + MFI . getMaxCallFrameSize ( ) , std :: max ( MaxAlign , getStackAlignment ( ) ) ) ; return alignTo ( Offset , getStackAlignment


<s> IsCheriPurecapABI = ABI != <STR_LIT> && <STR_LIT> ( ABI ) ; CommentString = <STR_LIT> ; AlignmentIsInBytes = false ; SupportsDebugInformation = true ; ExceptionsType = ExceptionHandling ::


<s> OperandMatchResultTy parseVector ( SmallVectorImpl < MCParsedAsmOperand * > & Operands ) { llvm_unreachable ( <STR_LIT>


<s> return ( vector unsigned short ) __builtin_altivec_vmuloub ( ( vector signed char ) a1


<s> AU . setPreservesCFG ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; AU . addRequired < MachineDominatorTree > (


<s> inline static std :: string addPrefix ( const std :: string & Name ) { std :: string prefix = getTagName ( PREFIX_SYMBOL ) ; if ( Name . compare ( <NUM_LIT> , prefix . size ( ) , prefix )


<s> assert ( VT . isFixedLengthVector ( ) && <STR_LIT> ) ; MVT ContainerVT = getContainerForFixedLengthVector ( VT ) ; X = convertToScalableVector ( ContainerVT , X , DAG , Subtarget ) ; SDValue Mask , VL ; std :: tie ( Mask , VL ) = getDefaultVLOps ( VT , ContainerVT , DL , DAG , Subtarget ) ; SDValue SplatZero = DAG . getNode ( <STR_LIT> , DL , ContainerVT , DAG . getUNDEF ( ContainerVT ) , DAG . getConstant ( <NUM_LIT> , DL , Subtarget . getXLenVT ( ) ) ) ; SDValue NegX = DAG . getNode ( <STR_LIT> , DL , ContainerVT , SplatZero , X , Mask


<s> static __inline__ void \ NAME ( TYPE * _PTR , TYPE _VALUE ) \ { \ __asm__ volatile ( OPCODE <STR_LIT> \ : <STR_LIT> ( _PTR [ <NUM_LIT> ]

) \ : <STR_LIT> ( _VALUE ) , <STR_LIT> ( FC ) ) ; \ return ; \ }


<s> bool isFloatRoundMode ( ) const { if ( ! isConstantImm ( ) ) return


<s> label = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( <NUM_LIT> , labelno ) , UNSPEC_TLS_LABEL ) ; unspec = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( <NUM_LIT> , x , GEN_INT ( reloc ) , label ) , UNSPEC_TLS ) ; tmp = gen_reg_rtx ( SImode ) ; emit_move_insn ( reg , unspec ) ; emit_move_insn ( tmp , label ) ; emit_insn ( gen_addsi3 ( reg , reg , tmp ) ) ; * valuep = emit_library_call_value ( get_tls_get_addr ( ) , NULL_RTX , LCT_PURE , Pmode , reg , Pmode ) ; insns = get_insns ( ) ; end_sequence ( ) ; return


<s> static Kind getNegatedComparison ( Kind Cmp ) { if ( ( Cmp & L ) || ( Cmp & G ) ) return ( Kind ) ( ( Cmp ^ ( L | G ) ) ^ EQ ) ; if ( ( Cmp & NE ) || ( Cmp & EQ ) ) return ( Kind ) ( Cmp ^ ( EQ | NE ) ) ; return ( Kind ) <NUM_LIT>


<s> bool hasMBC1 ( ) const { return m_MBC1


<s> bool isValidForTie ( const <ISA_LIT>Operand & Other ) const { if ( Kind != Other . Kind ) return false ; switch ( Kind ) { default : llvm_unreachable ( <STR_LIT> ) ; return false ; case k_RegisterIndex


<s> } bool OnlyUsesV1 = isShuffleEquivalent ( V1 , V2 , Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ; if ( OnlyUsesV1 || isShuffleEquivalent ( V1 , V2 , Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) { MVT SubVT = <STR_LIT> ( VT . getVectorElementType ( ) , <NUM_LIT> ) ; SDValue SubVec = DAG . getNode ( <STR_LIT> , DL , SubVT , OnlyUsesV1 ? V1 : V2 , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; return DAG . getNode ( <STR_LIT> , DL , VT , V1 , SubVec , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; } assert ( WidenedMask . size ( ) == <NUM_LIT> ) ; bool IsInsert = true ; int V2Index = - <NUM_LIT> ; for ( int i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) { assert ( WidenedMask [ i ] >= - <NUM_LIT> ) ; if ( WidenedMask [ i ] < <NUM_LIT> ) continue ; if ( WidenedMask [ i ] < <NUM_LIT> ) { if ( WidenedMask [ i ] != i ) { IsInsert = false ; break ; } } else { if ( V2Index >= <NUM_LIT> || WidenedMask [ i ] != <NUM_LIT> ) { IsInsert = false ; break ; } V2Index = i ; } } if ( IsInsert && V2Index >= <NUM_LIT> ) { MVT SubVT = <STR_LIT> ( VT . getVectorElementType ( ) , <NUM_LIT> ) ; SDValue Subvec = DAG . getNode ( <STR_LIT> , DL , SubVT , V2 , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; return insert128BitVector ( V1 , Subvec , V2Index * <NUM_LIT> , DAG , DL ) ; } SDValue Ops [ <NUM_LIT> ] = { DAG . getUNDEF ( VT ) , DAG . getUNDEF ( VT ) } ; unsigned PermMask = <NUM_LIT> ; for ( int i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) { assert ( WidenedMask [ i ] >= - <NUM_LIT> ) ; if ( WidenedMask [ i


<s> if ( Regs . VAddr ) MIB . add ( * TII -> getNamedOperand ( * CI . I , <STR_LIT> :: vaddr ) ) ; assert ( CI . I -> hasOneMemOperand ( ) && Paired . I -> hasOneMemOperand ( ) ) ; const MachineMemOperand * MMOa = * CI . I -> memoperands_begin ( ) ; const MachineMemOperand * MMOb = * Paired . I -> memoperands_begin ( ) ; MachineInstr * New = MIB . add ( * TII -> getNamedOperand ( * CI . I , <STR_LIT> :: srsrc ) ) . add ( * TII -> getNamedOperand ( * CI . I , <STR_LIT> :: soffset ) ) . addImm ( MergedOffset ) . addImm ( CI . GLC ) . addImm ( CI . SLC ) . addImm ( <NUM_LIT> ) . addImm ( CI . DLC ) . addImm ( <NUM_LIT> ) . addMemOperand ( combineKnownAdjacentMMOs ( * MBB -> getParent ( ) , MMOa , MMOb ) ) ; std :: pair < unsigned , unsigned > SubRegIdx = getSubRegIdxs ( CI , Paired ) ; const unsigned SubRegIdx0 = std :: get < <NUM_LIT> > ( SubRegIdx ) ; const unsigned SubRegIdx1 = std :: get < <NUM_LIT> > ( SubRegIdx ) ; const MCInstrDesc & CopyDesc = TII -> get ( TargetOpcode :: COPY ) ; const auto * Dest0 = TII -> getNamedOperand ( * CI . I , <STR_LIT> :: vdata ) ; const auto * Dest1 = TII -> getNamedOperand ( * Paired . I , <STR_LIT> :: vdata ) ; BuildMI ( * MBB , Paired . I , DL , CopyDesc ) . add ( * Dest0 ) . addReg ( DestReg , <NUM_LIT> , SubRegIdx0 ) ; MachineInstr * Copy1 = BuildMI ( * MBB , Paired . I , DL , CopyDesc ) . add ( * Dest1 ) . addReg ( DestReg , RegState :: Kill , SubRegIdx1 ) ; moveInstsAfter ( Copy1 , InstsToMove ) ; CI . I ->


<s> case ImmTyOffset1 : OS << <STR_LIT> ; break ; case ImmTyGLC : OS << <STR_LIT> ; break ; case ImmTySLC : OS << <STR_LIT> ; break ; case ImmTyTFE : OS << <STR_LIT> ; break ; case ImmTyD16 : OS << <STR_LIT> ; break ; case ImmTyFORMAT : OS << <STR_LIT> ; break ; case ImmTyClamp<ISA_LIT> : OS << <STR_LIT> ; break ; case ImmTyOMod<ISA_LIT> : OS << <STR_LIT> ; break ; case ImmTyDppCtrl : OS << <STR_LIT> ; break ; case ImmTyDppRowMask : OS << <STR_LIT> ; break ; case ImmTyDppBankMask : OS << <STR_LIT> ; break ; case ImmTyDppBoundCtrl : OS << <STR_LIT> ; break ; case ImmTySdwaDstSel : OS << <STR_LIT> ; break ; case ImmTySdwaSrc0Sel : OS << <STR_LIT> ; break ; case ImmTySdwaSrc1Sel : OS << <STR_LIT> ; break ; case ImmTySdwaDstUnused : OS << <STR_LIT> ; break ; case ImmTyDMask : OS << <STR_LIT> ; break ; case ImmTyUNorm : OS << <STR_LIT> ; break ; case ImmTyDA : OS << <STR_LIT> ; break ; case ImmTyR128 : OS << <STR_LIT> ; break ; case ImmTyLWE : OS << <STR_LIT> ; break ; case ImmTyOff : OS << <STR_LIT> ; break ; case ImmTyExpTgt : OS << <STR_LIT> ; break ; case ImmTyExpCompr : OS << <STR_LIT> ; break ; case ImmTyExpVM : OS << <STR_LIT> ; break ; case ImmTyHwreg : OS << <STR_LIT> ; break ; case ImmTySendMsg : OS << <STR_LIT> ; break ; case ImmTyInterpSlot : OS <<


<s> FunctionPass * create<ISA_LIT>PostLegalizeCombiner ( bool IsOptNone


<s> opcode = <STR_LIT> ; break ; case <STR_LIT> : opcode = <STR_LIT> ; break ; case <STR_LIT> : opcode = <STR_LIT> ; break ; case <STR_LIT> : opcode = <STR_LIT> ; break ; case <STR_LIT> : opcode = <STR_LIT> ; break ; case <STR_LIT> : opcode = <STR_LIT> ; break ; case <STR_LIT> : opcode = <STR_LIT> ; break ; case <STR_LIT> : opcode = <STR_LIT> ; break ; case <STR_LIT> : opcode = <STR_LIT> ; break ; case <STR_LIT> : opcode = <STR_LIT> ; break ; case <STR_LIT> : opcode = <STR_LIT> ; break ; case <STR_LIT>


<s> BuildMI ( * MI -> getParent ( ) , MI , MI -> getDebugLoc ( ) , get ( <STR_LIT> ) ) .


<s> return ( DEFAULT_ABI == ABI_V4 && ! flag_pic && ! TARGET_TOC && ( GET_CODE ( x ) == SYMBOL_REF || GET_CODE ( x ) == CONST ) &&


<s> EVT VT = Op . getValueType ( ) ; assert ( VT . is256BitVector ( ) && VT . isInteger ( ) && <STR_LIT> ) ; unsigned NumElems = VT . getVectorNumElements ( ) ; DebugLoc dl = Op . getDebugLoc ( ) ; SDValue LHS = Op . getOperand ( <NUM_LIT> ) ; SDValue LHS1 = Extract128BitVector ( LHS , <NUM_LIT> , DAG , dl ) ; SDValue LHS2 = Extract128BitVector ( LHS , NumElems / <NUM_LIT> , DAG , dl ) ; SDValue RHS = Op . getOperand ( <NUM_LIT> ) ; SDValue RHS1 = Extract128BitVector ( RHS , <NUM_LIT> , DAG , dl ) ; SDValue RHS2 = Extract128BitVector ( RHS , NumElems / <NUM_LIT> , DAG , dl ) ; MVT EltVT = VT . getVectorElementType ( ) . getSimpleVT ( ) ; EVT NewVT = <STR_LIT> ( EltVT , NumElems / <NUM_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , VT , DAG . getNode ( Op . getOpcode ( ) , dl , NewVT , LHS1 , RHS1 ) , DAG . getNode ( Op . getOpcode ( ) , dl , NewVT


<s> unsigned GCNRegPressure :: getRegKind ( Register Reg , const MachineRegisterInfo & MRI ) { assert ( Reg . isVirtual ( ) ) ; const auto RC = MRI . getRegClass ( Reg ) ; auto STI = static_cast < const <ISA_LIT>RegisterInfo * > ( MRI . getTargetRegisterInfo ( ) ) ; return STI -> isSGPRClass ( RC ) ? ( STI -> getRegSizeInBits ( * RC ) == <NUM_LIT> ? SGPR32 : SGPR_TUPLE ) : STI -> isAGPRClass ( RC ) ? ( STI -> getRegSizeInBits ( * RC ) ==

<NUM_LIT> ? AGPR32 : AGPR_TUPLE ) : ( STI -> getRegSizeInBits ( * RC ) == <NUM_LIT> ? VGPR32 : VGPR_TUPLE ) ;


<s> unsigned <ISA_LIT>MCInst :: getType ( ) const { const uint64_t F = MCID -> TSFlags ; return ( ( F >> <STR_LIT> )


<s> static struct machine_function * cris_init_machine_status (


<s> return std :: unique_ptr < MCObjectWriter > (

create<ISA_LIT>ELFObjectWriter ( OS , OSABI ) ) ;


<s> bool IsWrite = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; unsigned Code = IsWrite ? <STR_LIT> : <STR_LIT> ; auto * Node = cast < MemIntrinsicSDNode > ( Op . getNode ( ) ) ; SDValue Ops [ ] = { Op . getOperand ( <NUM_LIT> ) , DAG . getTargetConstant ( Code , DL , <STR_LIT> ) , Op


<s> return new <ISA_LIT>PassConfig ( this ,


<s> bool hasFlatScratchSTMode ( ) const { return hasFlatScratchInsts ( ) && ( hasGFX10_3Insts (


<s> decl = add_builtin_function ( <STR_LIT> , ftype , IX86_BUILTIN_NANSQ , BUILT_IN_MD , <STR_LIT> , NULL_TREE ) ; TREE_READONLY ( decl ) = <NUM_LIT> ; ix86_builtins [ ( int ) IX86_BUILTIN_NANSQ ] = decl ; ftype = ix86_get_builtin_func_type ( FLOAT128_FTYPE_FLOAT128 ) ; decl = add_builtin_function ( <STR_LIT> , ftype , IX86_BUILTIN_FABSQ , BUILT_IN_MD , <STR_LIT> , NULL_TREE ) ; TREE_READONLY ( decl ) = <NUM_LIT> ; ix86_builtins [ ( int ) IX86_BUILTIN_FABSQ ] =


<s> switch ( CC ) { case <STR_LIT> : BuildMI ( BB , dl , TII . get ( <STR_LIT> ) ) . addReg ( LHS ) . addReg ( RHS ) . addMBB ( copy1MBB ) ; break ; case <STR_LIT> : BuildMI ( BB , dl , TII . get ( <STR_LIT> ) ) . addReg ( LHS ) . addReg ( RHS ) . addMBB ( copy1MBB ) ; break ; case <STR_LIT> : BuildMI ( BB , dl , TII . get ( <STR_LIT> ) ) . addReg ( LHS ) . addReg ( RHS ) . addMBB ( copy1MBB ) ; break ; case <STR_LIT> : BuildMI ( BB , dl , TII . get ( <STR_LIT> ) ) . addReg ( LHS ) . addReg ( RHS ) . addMBB ( copy1MBB ) ; break ; case <STR_LIT> : BuildMI ( BB , dl , TII . get ( <STR_LIT> ) ) . addReg ( LHS ) . addReg ( RHS ) . addMBB ( copy1MBB ) ; break ; case <STR_LIT> : BuildMI ( BB , dl , TII . get ( <STR_LIT> ) ) . addReg ( LHS ) . addReg ( RHS ) . addMBB ( copy1MBB ) ; break ; default : report_fatal_error ( <STR_LIT> + Twine ( CC ) ) ; } BB = copy0MBB ; BB -> addSuccessor ( copy1MBB ) ; BB = copy1MBB ; BuildMI ( * BB , BB -> begin ( ) , dl , TII . get ( <STR_LIT> ) , MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addMBB ( copy0MBB ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addMBB ( thisMBB ) ; MI -> eraseFromParent (


<s> static SDValue Concat256BitVectors ( SDValue V1 , SDValue V2 , EVT VT , unsigned NumElems , SelectionDAG & DAG , SDLoc dl ) { SDValue V = Insert256BitVector ( DAG . getUNDEF ( VT ) , V1 , <NUM_LIT> ,


<s> MCStreamer * S ; if ( ! Triple ( TT ) . isOSNaCl ( ) ) S = createELFStreamer ( Context , MAB , OS ,


<s> Subtarget = & static_cast < const <ISA_LIT>Subtarget & > ( MF . getSubtarget ( ) ) ; return SelectionDAGISel :: runOnMachineFunction


<s> bool <ISA_LIT>BaseInstrInfo :: getInsertSubregLikeInputs ( const MachineInstr & MI , unsigned DefIdx , RegSubRegPair & BaseReg , RegSubRegPairAndIdx & InsertedReg ) const { assert ( DefIdx < MI . getDesc ( ) . getNumDefs ( ) && <STR_LIT> ) ; assert ( MI . isInsertSubregLike ( ) && <STR_LIT> ) ; switch ( MI . getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : const MachineOperand & MOBaseReg = MI . getOperand ( <NUM_LIT> ) ; const MachineOperand & MOInsertedReg = MI . getOperand ( <NUM_LIT> ) ; if ( MOInsertedReg . isUndef ( ) ) return false ; const MachineOperand & MOIndex = MI . getOperand ( <NUM_LIT> ) ; BaseReg . Reg = MOBaseReg . getReg ( ) ; BaseReg . SubReg = MOBaseReg . getSubReg ( ) ; InsertedReg . Reg = MOInsertedReg . getReg ( ) ; InsertedReg . SubReg = MOInsertedReg . getSubReg ( ) ; InsertedReg . SubIdx = <STR_LIT> + MOIndex .


<s> MVT XLenVT = Subtarget -> getXLenVT ( ) ; SDLoc DL ( Node ) ; EVT VT = Node -> getValueType ( <NUM_LIT> ) ; switch ( Opcode ) { case <STR_LIT> : { auto ConstNode = cast < ConstantSDNode > ( Node ) ; if ( VT == XLenVT && ConstNode -> isNullValue ( ) ) { SDValue New = CurDAG -> getCopyFromReg ( CurDAG -> getEntryNode ( ) , SDLoc ( Node ) , <STR_LIT> , XLenVT ) ; ReplaceNode ( Node , New . getNode ( ) ) ; return ; } break ; } case <STR_LIT> : { SDValue Imm = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , XLenVT


Other . ShAmt && IsSHL != Other . IsSHL ;


<s> unsigned Reg = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned Base = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; Reg = getReg ( Decoder , <STR_LIT> , Reg ) ; Base = getReg ( Decoder , <STR_LIT> , Base ) ; Inst . addOperand ( MCOperand :: createReg ( Reg ) ) ; Inst . addOperand ( MCOperand :: createReg ( Base


<s> PM . add ( create<ISA_LIT>UnifyMetadataPass (


<s> if ( isMAI ( MI ) && ST . hasMFMAInlineLiteralBug ( ) && OpNo == ( unsigned ) <STR_LIT> ( MI . getOpcode ( ) , <STR_LIT> :: src2 ) ) return false ; return RI . opCanUseInlineConstant ( OpInfo . OperandType ) ; } if ( ! RI . opCanUseLiteralConstant ( OpInfo . OperandType ) ) return false ; if ( ! isVOP3 ( MI ) || ! <STR_LIT> ( InstDesc , OpNo ) ) return true ; return ST . hasVOP3Literal (


<s> unsigned MemOpCost = getMemoryOpCost ( Opcode , SingleMemOpTy , Alignment , AddressSpace ) ; VectorType * VT = VectorType :: get ( ScalarTy , VF ) ; EVT ETy = TLI -> getValueType ( DL , VT ) ; if ( ! ETy . isSimple ( ) ) return BaseT :: getInterleavedMemoryOpCost ( Opcode , VecTy , Factor , Indices , Alignment , AddressSpace ) ; static const CostTblEntry AVX2InterleavedLoadTbl [ ] = { { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } } ; static const CostTblEntry AVX2InterleavedStoreTbl [ ] = { { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } } ; if ( Opcode == Instruction :: Load ) { if ( const auto * Entry = CostTableLookup ( AVX2InterleavedLoadTbl , Factor , ETy . getSimpleVT ( ) ) ) return NumOfMemOps * MemOpCost + Entry -> Cost ; } else { assert ( Opcode == Instruction :: Store && <STR_LIT> ) ; if ( const auto * Entry = CostTableLookup ( AVX2InterleavedStoreTbl , Factor , ETy . getSimpleVT ( ) ) ) return NumOfMemOps * MemOpCost + Entry -> Cost ; } return BaseT :: getInterleavedMemoryOpCost ( Opcode , VecTy , Factor , Indices


<s> Type = <STR_LIT> ; break ; case <STR_LIT> : Type = <STR_LIT> ; break ; case <STR_LIT> : Type = <STR_LIT> ; break ; default : return false ; } unsigned FusedOpcode = TII -> getFusedCompare ( Compare -> getOpcode ( ) , Type , Compare ) ; if ( ! FusedOpcode ) return false ; unsigned SrcReg = Compare -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned SrcReg2 = ( Compare -> getOperand ( <NUM_LIT> ) . isReg ( ) ? Compare -> getOperand ( <NUM_LIT> ) . getReg ( ) : <NUM_LIT> ) ; MachineBasicBlock :: iterator MBBI = Compare , MBBE = Branch ; for ( ++ MBBI ; MBBI != MBBE ; ++ MBBI ) if ( MBBI -> modifiesRegister ( SrcReg , TRI ) || ( SrcReg2 && MBBI -> modifiesRegister ( SrcReg2 , TRI ) ) ) return false ; MachineOperand CCMask ( MBBI -> getOperand ( <NUM_LIT> ) ) ; assert ( ( CCMask . getImm ( ) & ~ <STR_LIT> ) == <NUM_LIT> && <STR_LIT> ) ; MachineOperand Target ( MBBI -> getOperand ( Type == <STR_LIT> ? <NUM_LIT> : <NUM_LIT> ) ) ; const uint32_t * RegMask ; if ( Type == <STR_LIT> ) RegMask = MBBI -> getOperand ( <NUM_LIT> ) . getRegMask ( ) ; int CCUse = MBBI -> findRegisterUseOperandIdx ( <STR_LIT> , false , TRI ) ; assert ( CCUse >= <NUM_LIT> && <STR_LIT> ) ; Branch -> RemoveOperand ( CCUse ) ; if ( Type == <STR_LIT> || Type == <STR_LIT> ) Branch -> RemoveOperand ( <NUM_LIT> ) ; Branch -> RemoveOperand ( <NUM_LIT> ) ; Branch -> RemoveOperand ( <NUM_LIT> ) ; Branch -> setDesc ( TII -> get ( FusedOpcode ) ) ; MachineInstrBuilder MIB ( * Branch -> getParent ( ) -> getParent ( ) , Branch ) ; MIB . addOperand ( Compare -> getOperand ( <NUM_LIT> ) ) . addOperand ( Compare -> getOperand ( <NUM_LIT> ) ) . addOperand ( CCMask ) ; if ( Type == <STR_LIT> ) { MIB . addOperand ( Target ) . addReg ( <STR_LIT> , RegState :: ImplicitDefine | RegState :: Dead ) ; } if ( Type == <STR_LIT> ) MIB . addRegMask ( RegMask ) ; MBBI = Compare ; for ( ++ MBBI ; MBBI != MBBE ; ++ MBBI


<s> LaneInputs [ <NUM_LIT> ] . resize ( LaneCount , false ) ; for ( int i = <NUM_LIT> ; i < Size ; ++ i ) if ( Mask [ i ] >= <NUM_LIT> ) LaneInputs [ Mask [ i ] / Size ] [ ( Mask [ i ] % Size ) / LaneSize ] = true ; if ( LaneInputs [ <NUM_LIT> ] . count ( ) <= <NUM_LIT> && LaneInputs [ <NUM_LIT> ] . count ( ) <= <NUM_LIT> ) return

splitAndLowerVectorShuffle ( DL , VT , V1 , V2 , Mask , DAG ) ;


<s> TargetRegistry :: RegisterMCDisassembler ( The<ISA_LIT>Target , create<ISA_LIT>Disassebler


<s> const InstructionSelector * getInstructionSelector (


<s> if ( MO . isImm ( ) ) return isInlineConstant ( APInt ( <NUM_LIT> , MO . getImm ( )


<s> setStackPointerRegisterToSaveRestore ( Subtarget -> hasAddr64 ( ) ? <STR_LIT> : <STR_LIT> ) ; addRegisterClass ( <STR_LIT> , & <STR_LIT> ) ; addRegisterClass ( <STR_LIT> , & <STR_LIT> ) ; addRegisterClass ( <STR_LIT> , & <STR_LIT> ) ; addRegisterClass ( <STR_LIT> , & <STR_LIT> ) ; if ( Subtarget -> hasSIMD128 ( ) ) { addRegisterClass ( <STR_LIT> , & <STR_LIT> ) ; addRegisterClass ( <STR_LIT> , & <STR_LIT> ) ; addRegisterClass ( <STR_LIT> , & <STR_LIT> ) ; addRegisterClass ( <STR_LIT> , & <STR_LIT> ) ; } computeRegisterProperties ( Subtarget -> getRegisterInfo ( ) ) ; setOperationAction ( <STR_LIT> , MVTPtr , Custom ) ; setOperationAction ( <STR_LIT> , MVTPtr , Custom ) ; setOperationAction ( <STR_LIT> , MVTPtr , Custom ) ; setOperationAction ( <STR_LIT> , MVTPtr , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; for ( auto T : { <STR_LIT> , <STR_LIT> } ) { setOperationAction ( <STR_LIT> , T , Legal ) ; for ( auto CC : { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ) setCondCodeAction ( CC , T , Expand ) ; for ( auto Op : { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ) setOperationAction ( Op , T , Expand ) ; for ( auto Op : { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ) setOperationAction ( Op , T , Legal ) ; setOperationAction ( <STR_LIT> , T , Legal ) ; setOperationAction ( <STR_LIT> , T , Legal ) ; setOperationAction ( <STR_LIT> , T , Expand ) ; setOperationAction ( <STR_LIT> , T ,


<s> if ( llvm :: any_of ( CSI , [ ] ( const CalleeSavedInfo & C ) { return C . getReg ( ) == <STR_LIT> ; } ) ) { BuildMI ( MBB , MI , DebugLoc ( ) , STI . getInstrInfo ( ) -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( - <NUM_LIT> ) . add ( predOps ( <STR_LIT> ) ) ; } emitPushInst ( MBB , MI , CSI , PushOpc , PushOneOpc , false , &

is<ISA_LIT>Area1Register , <NUM_LIT> , MachineInstr :: FrameSetup ) ;


<s> assert ( ( ( ! Subtarget -> hasAVX512 ( ) && VT == <STR_LIT> ) || ( VT == <STR_LIT> ) ) && <STR_LIT> ) ; SDValue Op0 = Op . getOperand ( <NUM_LIT> ) ; SDValue Op1 = Op . getOperand ( <NUM_LIT> ) ; SDLoc dl ( Op ) ; <STR_LIT> CC = cast < CondCodeSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> get ( ) ; if ( Op0 . getOpcode ( ) == <STR_LIT> && Op0 . hasOneUse ( ) && isNullConstant ( Op1 ) && ( CC == <STR_LIT> || CC == <STR_LIT> ) ) { if ( SDValue NewSetCC = LowerToBT ( Op0 , CC , dl , DAG ) ) { if ( VT == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , NewSetCC ) ; return NewSetCC ; } } if ( ( isOneConstant ( Op1 ) || isNullConstant ( Op1 ) ) && ( CC == <STR_LIT> || CC == <STR_LIT> ) ) { if ( Op0 . getOpcode ( ) == <STR_LIT> ) { <STR_LIT> CCode = ( <STR_LIT> ) Op0 . getConstantOperandVal ( <NUM_LIT> ) ; bool Invert = ( CC == <STR_LIT> ) ^ isNullConstant ( Op1 ) ; if ( ! Invert ) return Op0 ; CCode = <STR_LIT> ( CCode ) ; SDValue SetCC = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getConstant ( CCode , dl , <STR_LIT> ) , Op0 . getOperand ( <NUM_LIT> ) ) ; if ( VT == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , SetCC ) ; return SetCC ; } } if ( ( Op0 . getValueType ( ) == <STR_LIT> ) && isOneConstant ( Op1 ) && ( CC == <STR_LIT> || CC == <STR_LIT> ) ) { <STR_LIT> NewCC = <STR_LIT> ( CC , true ) ; return DAG . getSetCC ( dl , VT , Op0 , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) , NewCC ) ; } bool isFP = Op1 . getSimpleValueType ( ) . isFloatingPoint ( ) ; unsigned <ISA_LIT>CC = Translate<ISA_LIT>CC ( CC , dl , isFP , Op0 , Op1 , DAG ) ; if ( <ISA_LIT>CC == <STR_LIT> )


<s> bool <ISA_LIT>DAGToDAGISel :: SelectInlineAsmMemoryOperand ( const SDValue & Op , unsigned ConstraintID , std :: vector < SDValue > & OutOps ) { switch ( ConstraintID ) { case InlineAsm :: Constraint_i : case InlineAsm


<s> static unsigned encodeNEONRd ( const MachineInstr & MI , unsigned OpIdx ) { unsigned RegD = MI . getOperand ( OpIdx ) . getReg ( ) ; unsigned Binary = <NUM_LIT> ; RegD = get<ISA_LIT>RegisterNumbering ( RegD ) ; Binary |= ( RegD & <NUM_LIT> ) << <STR_LIT> ; Binary |= ( ( RegD >> <NUM_LIT> ) & <NUM_LIT> )


<s> static bool isFrameAccessInstr ( MachineInstr * MI ) { switch ( MI -> getOpcode ( ) ) { default : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; } return


<s> function_args_iterator args_iter ; tree type ; int nvreg = <NUM_LIT> ; FOREACH_FUNCTION_ARGS ( fntype , type , args_iter ) if ( TREE_CODE ( type ) == VECTOR_TYPE && ALTIVEC_OR_VSX_VECTOR_MODE ( TYPE_MODE ( type ) ) ) nvreg ++ ; FOREACH_FUNCTION_ARGS ( TREE_TYPE ( current_function_decl ) , type , args_iter ) if ( TREE_CODE ( type ) == VECTOR_TYPE && ALTIVEC_OR_VSX_VECTOR_MODE ( TYPE_MODE ( type ) ) ) nvreg -- ; if ( nvreg > <NUM_LIT> )


<s> return DAG . getTargetGlobalAddress ( GV , dl , Callee . getValueType ( ) , <NUM_LIT> , UsePlt ? <STR_LIT> : <NUM_LIT> ) ; } if ( ExternalSymbolSDNode * S = dyn_cast < ExternalSymbolSDNode > ( Callee ) ) { const char * SymName = S -> getSymbol ( ) ; if ( Subtarget . isAIXABI ( ) ) { const Module * Mod = DAG . getMachineFunction ( ) . getFunction ( ) . getParent ( ) ; if ( const Function * F = dyn_cast_or_null < Function > ( Mod -> getNamedValue ( SymName ) ) ) return getAIXFuncEntryPointSymbolSDNode ( F ) ; const auto getExternalFunctionEntryPointSymbol = [ & ] ( StringRef SymName ) { auto & Context = DAG . getMachineFunction ( ) . getMMI ( ) . getContext ( ) ; MCSectionXCOFF * Sec = Context . getXCOFFSection ( ( Twine ( <STR_LIT> ) + Twine ( SymName ) ) . str ( ) , SectionKind :: getMetadata ( ) , XCOFF :: CsectProperties ( XCOFF :: XMC_PR , XCOFF :: XTY_ER ) ) ; return Sec -> getQualNameSymbol ( ) ; } ; SymName = getExternalFunctionEntryPointSymbol ( SymName ) -> getName ( ) . data ( ) ; } return DAG . getTargetExternalSymbol ( SymName , Callee . getValueType ( ) ,


<s> static tree gcn_reduction_update ( location_t loc , gimple_stmt_iterator * gsi , tree ptr , tree var , tree_code op ) { tree type = TREE_TYPE


<s> if ( ! HasAlloca || ! NeedsAlign ) return ; unsigned LFS = MFI . getLocalFrameSize ( ) ; for ( int i = <NUM_LIT> , e = MFI . getObjectIndexEnd ( ) ; i != e ; ++ i ) { if ( ! MFI . isSpillSlotObjectIndex ( i ) || MFI . isDeadObjectIndex ( i ) ) continue ; unsigned S = MFI . getObjectSize ( i ) ; unsigned A = std :: max ( MFI . getObjectAlignment ( i ) , <NUM_LIT> ) ; MFI . setObjectAlignment ( i , <NUM_LIT> ) ; LFS = alignTo ( LFS +


<s> unsigned getGlobalBaseReg ( ) const {


<s> else { if ( partial_subreg_p ( int_mode , SImode ) ) { gcc_assert ( base == const0_rtx ) ; dest = gen_lowpart ( SImode , dest ) ; int_mode = SImode ; } if ( base != const0_rtx ) { base = aarch64_force_temporary ( int_mode , dest , base ) ; aarch64_add_offset ( int_mode , dest , base , offset , NULL_RTX , NULL_RTX , false ) ; } else aarch64_add_offset ( int_mode , dest , base , offset , dest , NULL_RTX , false ) ; } return ; } sty = aarch64_classify_symbol ( base , const_offset ) ; switch ( sty ) { case SYMBOL_FORCE_TO_MEM : if ( const_offset != <NUM_LIT> && targetm . cannot_force_const_mem ( int_mode , imm ) ) { gcc_assert ( can_create_pseudo_p ( ) ) ; base = aarch64_force_temporary ( int_mode , dest , base ) ; aarch64_add_offset ( int_mode , dest , base , const_offset , NULL_RTX , NULL_RTX , false ) ; return ; } mem = force_const_mem ( ptr_mode , imm ) ; gcc_assert ( mem ) ; if ( ! aarch64_pcrelative_literal_loads ) { gcc_assert ( can_create_pseudo_p ( ) ) ; base = gen_reg_rtx ( ptr_mode ) ; aarch64_expand_mov_immediate ( base , XEXP ( mem , <NUM_LIT> ) ) ; if ( ptr_mode != Pmode ) base = convert_memory_address ( Pmode , base ) ; mem = gen_rtx_MEM ( ptr_mode , base ) ; } if ( int_mode != ptr_mode ) mem = gen_rtx_ZERO_EXTEND ( int_mode , mem ) ; emit_insn ( gen_rtx_SET ( dest , mem ) ) ; return ; case SYMBOL_SMALL_TLSGD : case SYMBOL_SMALL_TLSDESC : case SYMBOL_SMALL_TLSIE : case SYMBOL_SMALL_GOT_28K : case SYMBOL_SMALL_GOT_4G : case SYMBOL_TINY_GOT : case SYMBOL_TINY_TLSIE : if ( const_offset != <NUM_LIT> ) { gcc_assert ( can_create_pseudo_p ( ) ) ; base = aarch64_force_temporary ( int_mode ,


<s> return create<ISA_LIT>MCSubtargetInfoImpl ( TT , CPU


<s> if ( selectAddrFrameIndex ( Addr , Base , Offset ) ) return true ; if ( selectAddrFrameIndexOffset ( Addr , Base , Offset


<s> const MachineJumpTableInfo * MJTI = MF -> getJumpTableInfo ( ) ; const std :: vector < MachineJumpTableEntry > & JT = MJTI -> getJumpTables ( ) ; const std :: vector < MachineBasicBlock * > & JTBBs = JT [ JTI ] . MBBs ; unsigned OffsetWidth = <NUM_LIT> ; if ( MI -> getOpcode ( ) == <STR_LIT> ) { OffsetWidth = <NUM_LIT> ; OutStreamer . EmitDataRegion ( MCDR_DataRegionJT8 ) ; } else if ( MI -> getOpcode ( ) == <STR_LIT> ) { OffsetWidth = <NUM_LIT> ; OutStreamer . EmitDataRegion ( MCDR_DataRegionJT16 ) ; } for ( unsigned i = <NUM_LIT> , e = JTBBs . size ( ) ; i != e ; ++ i ) { MachineBasicBlock * MBB = JTBBs [ i ] ; const MCExpr * MBBSymbolExpr = MCSymbolRefExpr :: Create ( MBB -> getSymbol ( ) , OutContext ) ; if ( OffsetWidth ==


<s> assert ( <NUM_LIT> <= MsgId && MsgId < ID_GAPS_LAST_ ) ; return IdSymbolic [


<s> return <ISA_LIT>AsmParser :: classifySymbolRef ( getImm ( ) , VK , Imm ) && ( VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_CALL || VK == <ISA_LIT>MCExpr


<s> bool <ISA_LIT>InvISelDAG :: SelectAddrMode2OffsetReg ( SDNode * Op , SDValue N


<s> bool need_address_override ; uint64_t AdSize = TSFlags & <STR_LIT> ; if ( ( STI . hasFeature ( <STR_LIT> ) && AdSize == <STR_LIT> ) || ( STI . hasFeature ( <STR_LIT> ) && AdSize == <STR_LIT> ) || ( STI . hasFeature ( <STR_LIT> ) && AdSize == <STR_LIT> ) ) { need_address_override = true ; } else if ( MemoryOperand < <NUM_LIT> ) { need_address_override = false ; } else if ( STI . hasFeature ( <STR_LIT> ) ) { assert ( ! is16BitMemOperand ( MI , MemoryOperand , STI ) ) ; need_address_override = is32BitMemOperand ( MI , MemoryOperand ) ; } else if ( STI . hasFeature ( <STR_LIT> ) ) { assert ( ! is64BitMemOperand ( MI , MemoryOperand ) ) ; need_address_override = is16BitMemOperand ( MI , MemoryOperand , STI ) ; } else { assert ( STI . hasFeature ( <STR_LIT> ) ) ; assert ( ! is64BitMemOperand ( MI , MemoryOperand ) ) ; need_address_override = ! is16BitMemOperand ( MI , MemoryOperand , STI ) ; } if ( need_address_override ) emitByte ( <NUM_LIT> , CurByte , OS ) ; uint64_t Encoding = TSFlags & <STR_LIT> ; if ( Encoding == <NUM_LIT> ) Rex = emitOpcodePrefix ( TSFlags , CurByte , MemoryOperand , MI , Desc , STI , OS ) ; else emitVEXOpcodePrefix ( TSFlags , CurByte , MemoryOperand , MI , Desc , OS ) ; uint64_t Form = TSFlags & <STR_LIT> ; switch ( Form ) { default : break ; case <STR_LIT> :


<s> emit_insn ( gen_andqi3 ( ret , gen_lowpart ( QImode , tag ) , gen_int_mode ( and_imm , QImode ) ) ) ; } else emit_move_insn ( ret , gen_lowpart ( QImode , tag ) ) ; return ret


<s> assert ( V1 . getSimpleValueType ( ) == <STR_LIT> && <STR_LIT> ) ; assert ( V2 . getSimpleValueType ( ) == <STR_LIT> && <STR_LIT> ) ; assert ( Mask . size ( ) == <NUM_LIT> && <STR_LIT> ) ; assert ( Subtarget . hasAVX2 ( ) && <STR_LIT> ) ; SmallVector < int , <NUM_LIT> > WidenedMask ; if ( canWidenShuffleElements ( Mask , WidenedMask ) ) if ( SDValue V = lowerV2X128VectorShuffle ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return V ; if ( SDValue Blend = lowerVectorShuffleAsBlend ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return Blend ; if ( SDValue Broadcast = lowerVectorShuffleAsBroadcast ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return Broadcast ; if ( V2 . isUndef ( ) ) { SmallVector < int , <NUM_LIT> > RepeatedMask ; if ( is128BitLaneRepeatedShuffleMask ( <STR_LIT> , Mask , RepeatedMask ) ) { SmallVector < int ,


<s> static bool classof ( const <ISA_LIT>MCExpr * ) { return


<s> unsigned PtrStoreOpc = <NUM_LIT> ; unsigned LabelReg = <NUM_LIT> ; const int64_t LabelOffset = <NUM_LIT> * PVT . getStoreSize ( ) ; Reloc :: Model RM = MF -> getTarget ( ) . getRelocationModel ( ) ; bool UseImmLabel = ( MF -> getTarget ( ) . getCodeModel ( ) == CodeModel :: Small ) && ( RM == Reloc :: Static || RM == Reloc :: DynamicNoPIC ) ; if ( ! UseImmLabel ) { PtrStoreOpc = ( PVT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; const TargetRegisterClass * PtrRC = getRegClassFor ( PVT ) ; LabelReg = MRI . createVirtualRegister ( PtrRC ) ; if ( Subtarget -> is64Bit ( ) ) { MIB = BuildMI ( * thisMBB , MI , DL , TII -> get ( <STR_LIT> ) , LabelReg ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) . addMBB ( restoreMBB ) . addReg ( <NUM_LIT> ) ; } else { const <ISA_LIT>InstrInfo * XII = static_cast < const <ISA_LIT>InstrInfo * > ( TII ) ; MIB = BuildMI ( * thisMBB , MI , DL , TII -> get ( <STR_LIT> ) , LabelReg ) . addReg ( XII -> getGlobalBaseReg ( MF ) ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) . addMBB ( restoreMBB , Subtarget -> ClassifyBlockAddressReference ( ) ) . addReg ( <NUM_LIT> ) ; } } else PtrStoreOpc = ( PVT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; MIB = BuildMI ( * thisMBB , MI , DL , TII -> get ( PtrStoreOpc ) ) ; for ( unsigned i = <NUM_LIT> ; i < <STR_LIT> ; ++ i ) { if ( i == <STR_LIT> ) MIB . addDisp ( MI -> getOperand ( MemOpndSlot + i ) , LabelOffset ) ; else MIB . addOperand ( MI -> getOperand ( MemOpndSlot + i ) ) ; } if ( ! UseImmLabel ) MIB . addReg ( LabelReg ) ; else MIB . addMBB (


<s> } else { unsigned NewReg = MRI . createVirtualRegister ( MRI . getRegClass ( Reg ) ) ; Def -> getOperand ( <NUM_LIT> ) . setReg ( NewReg ) ; Op . setReg ( NewReg ) ; LIS . createAndComputeVirtRegInterval ( NewReg ) ; LiveInterval & LI = LIS . getInterval ( Reg ) ; LI . removeSegment ( LIS . getInstructionIndex ( * Def ) . getRegSlot ( ) , LIS . getInstructionIndex ( * Op . getParent ( ) ) . getRegSlot ( ) , true ) ; MFI . stackifyVReg ( NewReg ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; Def -> dump


<s> static int getStackOffset ( const MachineFunction & MF , int ObjectOffset ) { const auto & MFI =


<s> case <STR_LIT> : SelectOpc = <STR_LIT> ; RC = & <STR_LIT> ; break ; } const Value * Cond = SI -> getCondition ( ) ; bool NeedTest = true ; <STR_LIT> CC = <STR_LIT> ; if ( foldXALUIntrinsic ( CC , I , Cond ) ) NeedTest = false ; unsigned CondReg = getRegForValue ( Cond ) ; if ( ! CondReg ) return false ; bool CondIsKill = hasTrivialKill ( Cond ) ; if ( NeedTest ) { unsigned ANDReg = emitAnd_ri ( <STR_LIT> , CondReg , CondIsKill , <NUM_LIT> ) ; assert ( ANDReg && <STR_LIT> ) ; emitICmp_ri ( <STR_LIT> , ANDReg , true , <NUM_LIT> ) ; } unsigned TrueReg = getRegForValue ( SI -> getTrueValue ( ) ) ; bool TrueIsKill = hasTrivialKill ( SI ->


<s> virtual const <ISA_LIT>SelectionDAGInfo * getSelectionDAGInfo ( )


<s> Begin = <NUM_LIT> ; Width = MRI . getTargetRegisterInfo ( ) -> getRegSizeInBits ( * RC ) ; return true ; } Begin = <NUM_LIT> ; switch ( RC -> getID ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Width = MRI . getTargetRegisterInfo ( ) -> getRegSizeInBits ( * RC ) / <NUM_LIT> ; if ( RR . Sub == <STR_LIT> || RR . Sub == <STR_LIT> ) Begin = Width ; break ; default : return


<s> return inline_secondary_memory_needed ( class1 , class2 , mode ,


<s> for ( MachineBasicBlock * MBB = From ; MBB != To && ! MBB -> succ_empty ( ) ; MBB = * MBB -> succ_begin ( ) ) { for ( MachineBasicBlock :: iterator I = MBB -> begin ( ) , E = MBB -> end ( ) ; NumInstr < SkipThreshold && I != E ; ++


<s> unsigned OpSubReg = Op . getSubReg ( ) ; const TargetRegisterClass * OpRC = RI . getSubClassWithSubReg ( RI . getRegClassForReg ( MRI , OpReg ) , OpSubReg ) ; if ( DstRC == OpRC ) return ; unsigned DstReg = MRI . createVirtualRegister ( DstRC ) ; MachineInstr * Copy = BuildMI ( InsertMBB , I , DL , get ( <STR_LIT> ) , DstReg ) . add ( Op ) ; Op . setReg ( DstReg ) ; Op . setSubReg ( <NUM_LIT> ) ; MachineInstr * Def = MRI . getVRegDef ( OpReg ) ; if ( ! Def ) return ; if ( Def -> isMoveImmediate ( ) && DstRC != & <STR_LIT> ) FoldImmediate ( * Copy , *


<s> } switch ( CE -> getOpcode ( ) ) { default : if ( Constant * C = ConstantFoldConstant ( CE , getDataLayout ( ) ) ) if ( C && C != CE ) return lowerConstantForGV ( C , ProcessingGeneric ) ; { std :: string S ; raw_string_ostream OS ( S ) ; OS << <STR_LIT> ; CE -> printAsOperand ( OS , false , ! MF ? nullptr : MF -> getFunction ( ) -> getParent ( ) ) ; report_fatal_error ( OS . str ( ) ) ; } case Instruction :: AddrSpaceCast : { PointerType * DstTy = cast < PointerType > ( CE -> getType ( ) ) ; if ( DstTy -> getAddressSpace ( ) == <NUM_LIT> ) { return lowerConstantForGV ( cast < const Constant > ( CE -> getOperand ( <NUM_LIT> ) ) , true ) ; } std :: string S ; raw_string_ostream OS ( S ) ; OS << <STR_LIT> ; CE -> printAsOperand ( OS , false , ! MF ? <NUM_LIT> : MF -> getFunction ( ) -> getParent ( ) ) ; report_fatal_error ( OS . str ( ) ) ; } case Instruction :: GetElementPtr : { const DataLayout & DL = getDataLayout ( ) ; APInt OffsetAI ( DL . getPointerTypeSizeInBits ( CE -> getType ( ) ) , <NUM_LIT> ) ; cast < GEPOperator > ( CE ) -> accumulateConstantOffset ( DL , OffsetAI ) ; const MCExpr * Base = lowerConstantForGV ( CE -> getOperand ( <NUM_LIT> ) , ProcessingGeneric ) ; if ( ! OffsetAI ) return Base ; int64_t Offset = OffsetAI . getSExtValue ( ) ; return MCBinaryExpr :: createAdd ( Base , MCConstantExpr :: create ( Offset , Ctx ) , Ctx ) ; } case Instruction :: Trunc : case Instruction :: BitCast : return lowerConstantForGV ( CE -> getOperand ( <NUM_LIT> ) , ProcessingGeneric ) ; case Instruction :: IntToPtr : { const DataLayout & DL = getDataLayout ( ) ; Constant * Op = CE -> getOperand ( <NUM_LIT> ) ; Op = ConstantExpr :: getIntegerCast ( Op , DL . getIntPtrType ( CV -> getType ( ) ) , false ) ; return lowerConstantForGV ( Op


<s> const uint32_t * <ISA_LIT>RegisterInfo ::


<s> assert ( N -> getOpcode ( ) == <STR_LIT> && <STR_LIT> ) ; uint64_t Imm64 ; if ( ! isInt64Immediate ( N -> getOperand ( <NUM_LIT> ) . getNode ( ) , Imm64 ) ) return false ; if ( isUInt < <NUM_LIT> > ( Imm64 ) ) return false ; SDLoc Loc ( N ) ; SDValue Val = N -> getOperand ( <NUM_LIT> ) ; unsigned NumOfLeadingZeros = countLeadingZeros ( Imm64 ) ; if ( NumOfLeadingZeros != <NUM_LIT> ) Imm64 |= maskLeadingOnes < uint64_t > ( NumOfLeadingZeros ) ; unsigned MB , ME ; if ( ! isRunOfOnes64 ( Imm64 , MB , ME ) ) return false ; unsigned OnesOnLeft = ME


<s> vec_uchar16 x ; x = vec_splat ( ( vec_uchar16 ) ( count ) , <NUM_LIT> ) ; return ( ( qword ) ( vec_sll ( ( vec_uchar16 ) ( a ) , x


<s> uint64_t getPC16DBLEncoding ( const MCInst & MI , unsigned OpNum , SmallVectorImpl < MCFixup > & Fixups , const


<s> unsigned rs1 = fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned isImm = fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned rs2 = <NUM_LIT> ; unsigned simm13 = <NUM_LIT> ; if ( isImm ) simm13 = SignExtend32 < <NUM_LIT> > ( fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) ) ; else rs2 = fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) ; DecodeStatus status = DecodeIntRegsRegisterClass ( MI , rd , Address , Decoder ) ; if ( status != MCDisassembler :: Success ) return status ; status = DecodeIntRegsRegisterClass ( MI , rs1 ,


<s> switch ( MI -> getOpcode ( ) ) { default : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : SrcReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; CmpValue = MI -> getOperand ( <NUM_LIT> ) . getImm


<s> int64_t Offset = IsMulVL ? SOffset . getScalable ( ) : SOffset . getFixed ( ) ; const MachineOperand & ImmOpnd = MI . getOperand ( <ISA_LIT>InstrInfo :: getLoadStoreImmIdx ( MI . getOpcode ( ) ) ) ; Offset += ImmOpnd . getImm ( ) * Scale ; Optional < unsigned > UnscaledOp = <ISA_LIT>InstrInfo :: getUnscaledLdSt ( MI . getOpcode ( ) ) ; bool useUnscaledOp = UnscaledOp && ( Offset % Scale || Offset < <NUM_LIT> ) ; if ( useUnscaledOp && ! <ISA_LIT>InstrInfo :: getMemOpInfo ( * UnscaledOp , ScaleValue , Width , MinOff , MaxOff ) ) llvm_unreachable ( <STR_LIT> ) ; Scale = ScaleValue . getKnownMinSize ( ) ; assert ( IsMulVL == ScaleValue . isScalable ( ) && <STR_LIT> ) ; int64_t Remainder = Offset % Scale ; assert ( ! ( Remainder && useUnscaledOp ) && <STR_LIT> ) ; assert ( MinOff <


<s> enum FCInstr instr ; switch ( MI . getOpcode ( ) ) { case AMDGPU :: PREDICATED_BREAK : instr = FC_BREAK_PREDICATE ; break ; case AMDGPU :: CONTINUE : instr = FC_CONTINUE ; break ; case AMDGPU :: IF_PREDICATE_SET : instr = FC_IF_PREDICATE ; break ; case AMDGPU :: ELSE : instr = FC_ELSE ; break ; case AMDGPU :: ENDIF : instr = FC_ENDIF ; break ; case AMDGPU :: ENDLOOP : instr = FC_ENDLOOP ; break ; case AMDGPU :: WHILELOOP : instr = FC_BGNLOOP


<s> static DecodeStatus DecodeUImmWithOffsetAndScale ( MCInst & Inst , unsigned Value , uint64_t Address , const MCDisassembler * Decoder ) { Value &= ( ( <NUM_LIT> << Bits ) - <NUM_LIT> ) ; Value *= Scale ; Inst . addOperand ( MCOperand :: createImm ( Value + Offset ) ) ; return MCDisassembler


<s> SDValue NewOp0 = DAG . getNode ( ExtOpc , DL , <STR_LIT> , N -> getOperand ( <NUM_LIT> ) ) ; SDValue NewOp1 = DAG . getNode ( ExtOpc , DL , <STR_LIT> , N -> getOperand ( <NUM_LIT> ) ) ; SDValue NewRes = DAG . getNode ( WOpcode , DL , <STR_LIT> , NewOp0 , NewOp1 ) ; return DAG . getNode ( <STR_LIT> , DL ,

N -> getValueType ( <NUM_LIT> ) , NewRes ) ;


<s> case <STR_LIT> : MCE . emitByte ( <NUM_LIT> ) ; break ; case <STR_LIT> : MCE . emitByte ( <NUM_LIT> ) ; break ; case <STR_LIT> : MCE . emitByte ( <NUM_LIT> ) ; break ; case <STR_LIT> : MCE . emitByte ( <NUM_LIT> ) ; break ; case <STR_LIT> : MCE . emitByte ( <NUM_LIT> ) ;


<s> assert ( VT . getSizeInBits ( ) == InVT . getSizeInBits ( ) ) ; MVT SVT = VT . getVectorElementType ( ) ; MVT InSVT = InVT . getVectorElementType ( ) ; assert ( SVT . getSizeInBits ( ) > InSVT . getSizeInBits ( ) ) ; if ( SVT != <STR_LIT> && SVT != <STR_LIT> && SVT != <STR_LIT> ) return SDValue ( ) ; if ( InSVT != <STR_LIT> && InSVT != <STR_LIT> && InSVT != <STR_LIT> ) return SDValue ( ) ; if ( ! ( VT . is128BitVector ( ) && Subtarget . hasSSE2 ( ) ) && ! ( VT . is256BitVector ( ) && Subtarget . hasInt256 ( ) ) && ! ( VT . is512BitVector ( ) && Subtarget . hasAVX512 ( ) ) ) return SDValue ( ) ; SDLoc dl ( Op ) ; if ( VT . getSizeInBits ( ) > <NUM_LIT> ) { int InSize = InSVT . getSizeInBits ( ) * VT . getVectorNumElements ( ) ; In = extractSubVector ( In , <NUM_LIT> , DAG , dl , std :: max ( InSize , <NUM_LIT> ) ) ; } assert ( ( Op . getOpcode ( ) != <STR_LIT> || InVT == <STR_LIT> ) && <STR_LIT> ) ; if ( Subtarget . hasInt256 ( ) ) { assert ( VT . getSizeInBits ( ) > <NUM_LIT> && <STR_LIT> ) ; unsigned ExtOpc = Op . getOpcode ( ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; return DAG . getNode ( ExtOpc , dl , VT , In ) ; } assert ( Op . getOpcode ( ) == <STR_LIT> && <STR_LIT> ) ; SDValue Curr = In ; MVT CurrVT = InVT ; while ( CurrVT != VT && CurrVT . getVectorElementType


<s> MachineInstrBuilder MI = BuildMI ( MBB , MBBI , DL , TII . get ( Opc ) , StackPtr ) . addReg ( StackPtr ) . addImm ( AbsOffset ) ; MI -> getOperand ( <NUM_LIT> ) . setIsDead (


<s> DebugLoc DL = DebugLoc :: getUnknownLoc ( ) ; MachineInstrBuilder MIB = BuildMI ( MF , DL , get ( Opc ) , DestReg ) ; for ( unsigned i = <NUM_LIT> , e = Addr . size ( ) ; i != e ; ++ i ) MIB . addOperand ( Addr [ i ] ) ; NewMIs . push_back ( MIB )


<s> return ( __m128i ) __builtin_ia32_pmovsxbw128_mask ( ( __v16qi ) __A , ( __v8hi ) __W , (


<s> static bool rs6000_debug_can_change_mode_class ( machine_mode from , machine_mode to , reg_class_t rclass ) { bool ret = rs6000_can_change_mode_class ( from , to , rclass ) ; fprintf ( stderr , <STR_LIT> <STR_LIT> , ret ? <STR_LIT> : <STR_LIT> , GET_MODE_NAME ( from ) ,

GET_MODE_NAME ( to ) , reg_class_names [ rclass ] ) ;


<s> bool <ISA_LIT>FrameLowering :: hasFP ( const MachineFunction & MF ) const { const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const TargetRegisterInfo * RI = MF . getTarget ( ) . getRegisterInfo ( ) ; if ( MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) && MFI -> hasCalls ( ) ) return true ; return ( RI -> needsStackRealignment ( MF ) || MFI -> hasVarSizedObjects ( ) || MFI -> isFrameAddressTaken


<s> ++ It ; MachineBasicBlock * thisMBB = BB ; MachineFunction * F = BB -> getParent ( ) ; MachineBasicBlock * copy0MBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * sinkMBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; F -> insert ( It , copy0MBB ) ; F -> insert ( It , sinkMBB ) ; sinkMBB -> splice ( sinkMBB -> begin ( ) , BB , llvm :: next ( MachineBasicBlock :: iterator ( MI ) ) , BB -> end ( ) ) ; sinkMBB -> transferSuccessorsAndUpdatePHIs ( BB ) ; BB -> addSuccessor ( copy0MBB ) ; BB -> addSuccessor ( sinkMBB ) ; BuildMI ( BB , dl , TII -> get ( Opc2 ) ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addImm ( MI

-> getOperand ( <NUM_LIT> ) . getImm ( ) ) ;


<s> bool <ISA_LIT>InstructionSelector :: select ( MachineInstr & I , CodeGenCoverage & CoverageInfo ) const { if ( ! isPreISelGenericOpcode ( I . getOpcode ( ) ) ) { if ( I . isCopy ( ) ) return selectCOPY ( I ) ; return true ; } switch ( I . getOpcode ( ) ) { default : return selectImpl ( I , CoverageInfo ) ; case TargetOpcode :: G_ADD : return selectG_ADD ( I ) ; case TargetOpcode :: G_INTTOPTR : case TargetOpcode :: G_BITCAST : return selectCOPY ( I ) ; case TargetOpcode :: G_CONSTANT : case TargetOpcode :: G_FCONSTANT : return selectG_CONSTANT ( I ) ; case TargetOpcode :: G_GEP : return selectG_GEP ( I ) ; case TargetOpcode :: G_IMPLICIT_DEF : return selectG_IMPLICIT_DEF ( I ) ; case TargetOpcode :: G_INTRIN<ISA_LIT>C : return selectG_INTRIN<ISA_LIT>C ( I , CoverageInfo ) ; case TargetOpcode ::


<s> unsigned getVectorDataSize ( ) const { return


<s> assert ( N == <NUM_LIT> && isMemorySIMDNoIndex ( ) && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: CreateReg ( Mem .


<s> FOR_EACH_EDGE ( e , ei , edges ) { basic_block target = * ( basic_block * ) ( ( char * ) e + offset ) ; if ( bb_sese * t_sese = BB_GET_SESE ( target ) ) { if ( t_sese -> node < sese -> node + dir && ! ( dir < <NUM_LIT> && sese -> parent == t_sese -> node ) ) sese -> push ( pseudo_node_t ( target , usd * t_sese -> dir ) ) ; } else { sese -> push ( pseudo_node_t ( nullptr , <NUM_LIT> )


<s> void setMachineBB ( MachineBasicBlock * value


<s> State = IES_ERROR ; break ; case IES_INTEGER : case IES_REGISTER : case IES_RPAREN : State =


<s> if ( ! current_frame_info . initialized ) m32r_compute_frame_size ( get_frame_size ( ) ) ; return


<s> SDValue TrueV = DAG . getConstant ( <NUM_LIT> , DL , Op . getValueType ( ) ) ; SDValue FalseV = DAG . getConstant ( <NUM_LIT> , DL , Op . getValueType ( ) ) ; SDVTList VTs = DAG . getVTList ( Op . getValueType (


<s> const TargetInstrDesc & Desc = MI -> getDesc ( ) ; bool IsPIC = TM . getRelocationModel ( ) == Reloc :: PIC_ ; bool Is64BitMode = TM . getSubtargetImpl ( ) -> is64Bit ( ) ; unsigned Size = GetInstSizeWithDesc ( * MI , & Desc


<s> switch ( code ) { case OPT_mabi_ : if ( strcmp ( arg , <STR_LIT> ) == <NUM_LIT> ) mips_abi = ABI_32 ; else if ( strcmp ( arg , <STR_LIT> ) == <NUM_LIT> ) mips_abi = ABI_O64 ; else if ( strcmp ( arg , <STR_LIT> ) == <NUM_LIT>


<s> void <ISA_LIT>IRDecorator :: ReplaceConstantGlobsRefs ( GlobalVariable * GV , GlobalVariable * GCStruct , GlobFieldOffsetMap & GlobOffsetMap ) { LLVMContext & Cxt = Func -> getContext ( ) ; const DataLayout & DL = Func -> getParent ( ) -> getDataLayout ( ) ; Type * TargetIdxTy = GetTargetIndexType ( DL , Cxt ) ; SmallVector < Instruction * , <NUM_LIT> > RemoveList ; SmallVector < std :: pair < Instruction * , Value * > , <NUM_LIT> > UserGEPClonePairVec ; for ( auto Use = GV -> use_begin ( ) ; Use != GV -> use_end ( ) ; Use ++ ) { SmallVector < Value * , <NUM_LIT> > Indices ; unsigned FldIndex = GlobOffsetMap [ GV ] ; Indices . push_back ( ConstantInt :: get ( TargetIdxTy , <NUM_LIT> ) ) ; Indices . push_back ( ConstantInt :: get ( TargetIdxTy , FldIndex )


<s> if ( Subtarget . hasVInstructions ( ) && ( VT . isScalableVector ( ) || Subtarget . useRVVForFixedLengthVectors ( ) ) ) return EVT :: getVectorVT ( Context , <STR_LIT> , VT . getVectorElementCount ( ) ) ; return VT . changeVectorElementTypeToInteger


<s> int SSFI = MF . getFrameInfo ( ) -> CreateStackObject ( <NUM_LIT> , <NUM_LIT> ) ; SDValue StackSlot = DAG . getFrameIndex ( SSFI , PtrVT ) ; SDValue Store = DAG . getStore ( DAG . getEntryNode ( ) , dl , Chain , StackSlot , NULL , <NUM_LIT> ) ; SDValue Four = DAG . getConstant ( <NUM_LIT> , PtrVT ) ; SDValue Addr = DAG . getNode ( <STR_LIT> , dl , PtrVT , StackSlot , Four ) ; SDValue CWD = DAG . getLoad ( <STR_LIT> , dl , Store , Addr , NULL , <NUM_LIT> ) ; SDValue CWD1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , CWD , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDValue CWD2 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> ,

CWD , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ;


<s> std :: swap ( V1 , V2 ) ; } else if ( V1 . getOpcode ( ) != ExpectedOpcode || V2 . getOpcode ( ) != NextExpectedOpcode ) return false ; if ( ! V1 -> hasOneUse ( ) || ! V2 -> hasOneUse ( ) ) return false ; SDValue LHS = V1 -> getOperand ( <NUM_LIT> ) , RHS = V1 -> getOperand ( <NUM_LIT> ) ; if ( ( V2 -> getOperand ( <NUM_LIT> ) != LHS || V2 -> getOperand ( <NUM_LIT> ) != RHS ) && ( V2 -> getOperand ( <NUM_LIT> ) != RHS || V2 -> getOperand ( <NUM_LIT> ) != LHS ) ) return false ; if ( ! ( isShuffleEquivalent ( V1 , V2 , Mask , { <NUM_LIT> , <NUM_LIT> } ) || isShuffleEquivalent ( V1 , V2 , Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) || isShuffleEquivalent ( V1 , V2 , Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) || isShuffleEquivalent ( V1 , V2 , Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) ) return false ; Opnd0 = LHS


<s> unsigned Threshold = isOptSize ( MF ) ? SpillFuncThresholdOs - <NUM_LIT> : SpillFuncThreshold ; return Threshold


<s> Value * <ISA_LIT>TargetLowering :: emitStoreConditional ( IRBuilder < > & Builder , Value * Val , Value * Addr , AtomicOrdering Ord ) const { Module * M = Builder . GetInsertBlock ( ) -> getParent ( ) -> getParent ( ) ; bool IsRelease = Ord == Release || Ord == AcquireRelease || Ord == SequentiallyConsistent ; if ( Val -> getType ( ) -> getPrimitiveSizeInBits ( ) == <NUM_LIT> ) { <STR_LIT> Int = IsRelease ? <STR_LIT> : <STR_LIT> ; Function * Strex = <STR_LIT> ( M , Int ) ; Type * Int32Ty = Type :: getInt32Ty ( M -> getContext ( ) ) ; Value * Lo = Builder . CreateTrunc ( Val , Int32Ty , <STR_LIT> ) ; Value * Hi = Builder . CreateTrunc ( Builder . CreateLShr ( Val , <NUM_LIT> ) , Int32Ty , <STR_LIT> ) ; Addr = Builder . CreateBitCast ( Addr , Type :: getInt8PtrTy ( M -> getContext ( ) ) ) ; return Builder . CreateCall3 ( Strex , Lo , Hi , Addr ) ; } <STR_LIT> Int = IsRelease ? <STR_LIT> : <STR_LIT> ; Type * Tys [ ] = { Addr -> getType ( )


<s> BuildMI ( * MBB , CI . Paired , DL , TII -> get ( <STR_LIT> ) , ImmReg ) . addImm ( CI . BaseOff ) ; BaseReg = MRI -> createVirtualRegister ( & <STR_LIT> ) ; BaseRegFlags = RegState :: Kill ; TII -> getAddNoCarry ( * MBB , CI . Paired , DL , BaseReg ) . addReg ( ImmReg ) . addReg ( AddrReg -> getReg ( ) , <NUM_LIT> , BaseSubReg ) ; BaseSubReg = <NUM_LIT> ; } MachineInstrBuilder Write2 = BuildMI ( * MBB , CI . Paired , DL , Write2Desc ) . addReg ( BaseReg , BaseRegFlags , BaseSubReg ) . add ( * Data0 ) . add ( * Data1 ) . addImm ( NewOffset0 ) . addImm ( NewOffset1 ) . addImm ( <NUM_LIT> ) . cloneMergedMemRefs ( { & * CI . I , & * CI . Paired } ) ; moveInstsAfter ( Write2 , CI . InstsToMove ) ; MachineBasicBlock :: iterator Next = std :: next ( CI . I ) ; CI . I -> eraseFromParent ( ) ; CI . Paired ->


<s> if ( I -> getOpcode ( ) != <STR_LIT> && I -> getOpcode ( ) != <STR_LIT> && I -> getOpcode ( ) != <STR_LIT> && I -> getOpcode ( ) != <STR_LIT> && I -> getOpcode ( ) != <STR_LIT> && I -> getOpcode ( ) != <STR_LIT> && I -> getOpcode ( ) != <STR_LIT> && I -> getOpcode ( ) != <STR_LIT> ) return <NUM_LIT> ; I -> eraseFromParent ( ) ; I = MBB . end ( ) ; if ( I == MBB . begin ( ) ) return <NUM_LIT> ; -- I


<s> <ISA_LIT>MCAsmInfo :: <ISA_LIT>MCAsmInfo ( const Triple


<s> SDVTList CompareVT = CurDAG -> getVTList ( CompareTys ) ; SDValue CompareOps [ ] = { LHS , RHS , Chain } ; SDNode * Compare = CurDAG -> getMachineNode ( <STR_LIT> , N , CompareVT , CompareOps ) ; CondCodeSDNode * CC = cast < CondCodeSDNode > ( Cond . getNode ( ) ) ; uint64_t TargetCCode ; switch ( CC -> get ( ) ) { case <STR_LIT> :: SETOEQ : case <STR_LIT> :: SETUEQ : case <STR_LIT> :: SETEQ : TargetCCode = <STR_LIT> ; break ; case <STR_LIT> :: SETONE : case <STR_LIT> :: SETUNE : case <STR_LIT> :: SETNE : TargetCCode = <STR_LIT> ; break ; case <STR_LIT> :: SETOLT : case <STR_LIT> :: SETULT : case <STR_LIT> :: SETLT : TargetCCode = <STR_LIT> ; break ; case <STR_LIT> :: SETOLE : case <STR_LIT> :: SETULE : case <STR_LIT> :: SETLE : TargetCCode = <STR_LIT> ; break ; case <STR_LIT> :: SETOGT : case <STR_LIT> :: SETUGT : case <STR_LIT> :: SETGT : TargetCCode = <STR_LIT> ; break ; case <STR_LIT> :: SETOGE : case <STR_LIT> :: SETUGE : case <STR_LIT> :: SETGE :


<s> return ( uint64x1_t ) __builtin_neon_vqshl_u_ndi ( ( int64x1_t


<s> for ( auto & useDef : regInfo . reg_operands ( virtReg ) ) { ( void ) useDef ; ++


<s> if ( UniquedVals [ i ] . getNode ( ) == <NUM_LIT> ) continue ; LeadingZero &= cast < ConstantSDNode > ( UniquedVals [ i ] ) -> isNullValue ( ) ; LeadingOnes &= cast < ConstantSDNode > ( UniquedVals [ i ] ) -> isAllOnesValue ( ) ; } if ( LeadingZero ) { if ( UniquedVals [ Multiple - <NUM_LIT> ] . getNode ( ) == <NUM_LIT> ) return DAG . getTargetConstant ( <NUM_LIT> , <STR_LIT> ) ; int Val = cast < ConstantSDNode > ( UniquedVals [ Multiple - <NUM_LIT> ] ) -> getZExtValue ( ) ; if ( Val < <NUM_LIT> ) return DAG . getTargetConstant ( Val , <STR_LIT> ) ; } if ( LeadingOnes ) { if ( UniquedVals [ Multiple - <NUM_LIT> ] . getNode ( ) == <NUM_LIT> ) return DAG . getTargetConstant ( ~ <NUM_LIT> , <STR_LIT> ) ; int Val = cast < ConstantSDNode > ( UniquedVals [ Multiple - <NUM_LIT> ] ) -> getSExtValue ( ) ; if ( Val >= - <NUM_LIT> ) return DAG . getTargetConstant ( Val , <STR_LIT> ) ; } return SDValue ( ) ; } for ( unsigned i = <NUM_LIT> , e = N -> getNumOperands ( ) ; i != e ; ++ i ) { if ( N -> getOperand ( i ) .


<s> const <STR_LIT> * II = <STR_LIT> ( IntNo ) ; if ( ! II ) return SDValue ( ) ; return Op . getOperand ( II -> VLOperand + <NUM_LIT> +


<s> REAL_VALUE_TYPE r_pow ; rtvec v = rtvec_alloc ( <NUM_LIT> ) ; rtx elt ; rtx scale_vec = gen_reg_rtx ( V2DFmode ) ; ( void ) real_powi ( & r_pow , DFmode , & dconst2 , hwi_scale ) ; elt = CONST_DOUBLE_FROM_REAL_VALUE ( r_pow , DFmode ) ; RTVEC_ELT ( v , <NUM_LIT> ) = elt ; RTVEC_ELT ( v , <NUM_LIT> ) = elt ; rs6000_expand_vector_init ( scale_vec , gen_rtx_PARALLEL ( V2DFmode , v ) ) ; emit_insn ( gen_mulv2df3 ( tgt ,


<s> getBufferStoreOpcode ( Ty , MemSize , Offen ) ; if ( Opc == - <NUM_LIT> ) return false ; MachineInstrBuilder MIB = B . buildInstr ( Opc ) . addUse ( VData ) ; if ( Offen ) MIB . addUse ( VOffset ) ; MIB . addUse ( RSrc ) . addUse ( SOffset ) . addImm ( ImmOffset ) . addImm ( extractGLC ( AuxiliaryData ) ) . addImm ( extractSLC ( AuxiliaryData ) ) . addImm ( <NUM_LIT> ) . addImm ( extractDLC ( AuxiliaryData ) ) . addImm ( extractSWZ ( AuxiliaryData ) ) . addMemOperand ( MMO ) ; MI . eraseFromParent ( ) ; return constrainSelectedInstRegOperands ( * MIB , TII


<s> bool <ISA_LIT>InstrInfo :: analyzeBranch ( MachineBasicBlock & MBB , MachineBasicBlock * & TBB , MachineBasicBlock * & FBB , SmallVectorImpl < MachineOperand > & Cond , bool AllowModify ) const { MachineBasicBlock :: iterator I = MBB . end ( ) ; while ( I != MBB . begin ( ) ) { -- I ; if ( I -> isDebugValue ( ) ) continue ; if ( ! isUnpredicatedTerminator ( * I ) ) break ; SmallVector < MachineOperand , <NUM_LIT> > ThisCond ; ThisCond . push_back ( MachineOperand :: CreateImm ( <NUM_LIT> ) ) ; const MachineOperand * ThisTarget ; if ( ! isBranch ( I , ThisCond , ThisTarget ) ) return true ; if ( ! ThisTarget -> isMBB ( ) ) return true ; if ( ThisCond [ <NUM_LIT> ] . getImm ( ) == <STR_LIT> ) { if ( ! AllowModify ) { TBB = ThisTarget -> getMBB ( ) ; continue ; } while ( std :: next ( I ) != MBB . end ( ) ) std :: next ( I ) -> eraseFromParent ( ) ; Cond . clear ( ) ; FBB = <NUM_LIT> ; TBB = ThisTarget -> getMBB ( ) ; continue ; } if ( Cond . empty ( ) ) { FBB = TBB ; TBB = ThisTarget -> getMBB ( ) ; Cond . push_back ( MachineOperand :: CreateImm ( ThisCond [ <NUM_LIT> ] . getImm ( ) ) ) ; for ( unsigned int i = <NUM_LIT> ; i < ( I -> getNumExplicitOperands ( ) ) ; i ++ )

Cond . push_back ( I -> getOperand ( i ) ) ;


<s> getTargetStreamer ( ) . EmitARM64WinCFIEpilogStart ( ) ; return false


<s> SDValue Val = N -> getOperand ( <NUM_LIT> ) ; EVT ValVT = Val . getValueType ( ) ; if ( VT == <STR_LIT> && ValVT == <STR_LIT> ) { if ( SDValue Res = implicitlyClearTop ( Val , DAG ) ) { DCI . CombineTo ( N -> getOperand ( <NUM_LIT>


<s> return ( ( isa < ConstantSDNode > ( Elt ) && cast < ConstantSDNode > ( Elt ) -> getZExtValue ( ) == <NUM_LIT> ) || ( isa < ConstantFPSDNode > ( Elt

) && cast < ConstantFPSDNode > ( Elt ) -> getValueAPF ( ) . isPosZero ( ) ) ) ;


<s> BlockPosition Position ( MF -> getAlignment ( ) ) ; for ( SmallVector < MBBInfo , <NUM_LIT> > :: iterator BI = MBBs . begin ( ) , BE = MBBs . end ( ) ; BI != BE ;


<s> LiveMask &= ~ getDefRegMask ( MO , * MRI ) ; CurPressure . inc ( Reg , PrevMask , LiveMask , * MRI ) ; if ( LiveMask . none ( ) ) LiveRegs . erase ( I ) ; } for ( const auto & U : RegUses ) { auto & LiveMask = LiveRegs [ U . RegUnit ] ; auto PrevMask = LiveMask ; LiveMask |= U . LaneMask ; CurPressure . inc ( U . RegUnit , PrevMask , LiveMask , * MRI ) ; } assert ( CurPressure == getRegPressure ( *


<s> static void nios2_option_save ( struct cl_target_option * ptr , struct gcc_options * opts ATTRIBUTE_UNUSED , struct gcc_options * opts_set ATTRIBUTE_UNUSED ) { unsigned int i


<s> if ( ! getParser ( ) . parseExpression ( Value ) ) { const MCConstantExpr * MCE = dyn_cast < MCConstantExpr > ( Value ) ; uint64_t IntValue = MCE -> getValue ( ) ; if ( ! isUIntN ( Size , IntValue ) && ! isIntN ( Size , IntValue ) ) return Error ( ExprLoc , <STR_LIT> ) ; MaxBytesToFill = IntValue ; Lex ( ) ; } else { return Error ( ExprLoc , <STR_LIT> ) ; } } getTargetStreamer ( ) . emitFAlign ( <NUM_LIT> , MaxBytesToFill ) ; Lex ( ) ; return false


<s> return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; default : llvm_unreachable ( <STR_LIT>


<s> void <ISA_LIT>InstPrinter :: printBDAddrOperand ( const MCInst * MI , int OpNum , raw_ostream & O ) { printAddress ( & MAI , MI -> getOperand ( OpNum ) . getReg ( ) , MI ->

getOperand ( OpNum + <NUM_LIT> ) . getImm ( ) , <NUM_LIT> , O ) ;


<s> if ( Res . getNode ( ) ) { APInt KnownZero , KnownOne ; DAG . ComputeMaskedBits ( SDValue ( N , <NUM_LIT> ) , KnownZero , KnownOne ) ; if ( KnownZero == <NUM_LIT> ) Res = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Res , DAG . getValueType ( <STR_LIT> ) ) ; else if ( KnownZero == <NUM_LIT> ) Res = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Res , DAG . getValueType ( <STR_LIT> ) ) ; else if ( KnownZero == <NUM_LIT> ) Res = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Res , DAG . getValueType ( <STR_LIT> ) ) ; } return


<s> const MachineOperand * Src1 = getNamedOperand ( MI , <STR_LIT> :: src1 ) ; const MachineOperand * Src2 = getNamedOperand ( MI , <STR_LIT> :: src2 ) ; return BuildMI ( * MBB , MI , MI . getDebugLoc ( ) , get ( <STR_LIT> ) ) . addOperand ( * Dst ) . addImm ( <NUM_LIT> ) . addOperand ( * Src0 ) . addImm (

<NUM_LIT> ) . addOperand ( * Src1 ) . addImm ( <NUM_LIT> ) . addOperand ( * Src2 ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ;


<s> <ISA_LIT>InstrInfo :: <ISA_LIT>InstrInfo ( <ISA_LIT>Subtarget & st ) : <ISA_LIT>GenInstrInfo ( ) , RI ( st


<s> V0 , V1 , V2 , V3 , V4 , V5 , V6 , V7 , V8 , V9 , V10 , V11 , V12 , V13 , V14 , V15 , V16 , V17 , V18 , V19 , V20 , V21 , V22 , V23 , V24 , V25 , V26 , V27 , V28 , V29 , V30 , V31 , <NUM_LIT> } ; static const MCPhysReg VecDbl [ ] = { W0 , W1 , W2 , W3 , W4 , W5 , W6 , W7 , W8 , W9 , W10 , W11 , W12 , W13 , W14 , W15 , <NUM_LIT> } ; static const MCPhysReg VecPred [ ] = { Q0 , Q1 , Q2 , Q3 , <NUM_LIT> } ; switch ( RC -> getID ( ) ) { case IntRegsRegClassID : return Int32 ; case DoubleRegsRegClassID : return Int64 ; case PredRegsRegClassID : return Pred ; case HvxVRRegClassID : return VecSgl ; case HvxWRRegClassID : return VecDbl ; case HvxQRRegClassID : return VecPred ; default : break ; } static const MCPhysReg Empty [ ] = { <NUM_LIT> } ; dbgs ( ) << <STR_LIT> << getRegClassName ( RC ) <<


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: CreateImm ( unsigned ( getBankedReg ( ) ) )


<s> else assert ( <NUM_LIT> && <STR_LIT> ) ; } else if ( ( MO . getTargetFlags ( ) & <STR_LIT> ) != <NUM_LIT> ) { if ( ( MO . getTargetFlags ( ) & <STR_LIT> ) == <STR_LIT> ) RefKind = MCSymbolRefExpr :: VK_TLVPPAGE ; else if ( ( MO . getTargetFlags ( ) & <STR_LIT> ) == <STR_LIT> ) RefKind = MCSymbolRefExpr :: VK_TLVPPAGEOFF ; else llvm_unreachable ( <STR_LIT> ) ; } else { if ( ( MO . getTargetFlags ( ) & <STR_LIT> ) == <STR_LIT> ) RefKind = MCSymbolRefExpr :: VK_PAGE ; else if ( ( MO . getTargetFlags ( ) & <STR_LIT> ) == <STR_LIT> ) RefKind =


<s> SDLoc DL ( Node ) ; const BlockAddress * BA = Node -> getBlockAddress ( ) ; int64_t Offset = Node -> getOffset ( ) ; EVT PtrVT = getPointerTy ( ) ; SDValue Result = DAG . getTargetBlockAddress ( BA , PtrVT , Offset ) ; Result = DAG . getNode ( <STR_LIT> , DL , PtrVT , Result ) ; return Result


<s> } else MRSReg = MSRReg = <STR_LIT> ( Tok . getString ( ) ) ; auto PState = <STR_LIT> ( Tok . getString ( ) ) ; unsigned PStateImm = - <NUM_LIT> ; if ( PState && PState -> haveFeatures ( getSTI ( ) . getFeatureBits ( ) ) ) PStateImm = PState -> Encoding ; Operands . push_back ( <ISA_LIT>Operand :: CreateSysReg ( Tok . getString ( ) , getLoc ( ) , MRSReg , MSRReg , PStateImm , getContext


<s> MCOp = MCOperand :: createImm ( MO . getImm ( ) ) ; break ; case MachineOperand :: MO_MachineBasicBlock : MCOp = MCOperand :: createExpr ( MCSymbolRefExpr :: create ( MO . getMBB ( ) -> getSymbol ( ) , Ctx ) ) ; break ; case MachineOperand :: MO_GlobalAddress : MCOp = LowerSymbolOperand ( MO , GetGlobalAddressSymbol ( MO ) ) ; break ; case MachineOperand :: MO_ExternalSymbol : MCOp = LowerSymbolOperand ( MO , GetExternalSymbolSymbol ( MO ) ) ; break ; case MachineOperand :: MO_JumpTableIndex : MCOp = LowerSymbolOperand ( MO , GetJumpTableSymbol ( MO ) ) ; break ; case MachineOperand ::


<s> StringMap < int > Map ( array_lengthof ( manglingRules ) ) ; int Id = <NUM_LIT> ; for ( auto Rule : manglingRules ) Map . insert ( { Rule . Name , Id ++ } ) ; return


<s> <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; assert ( ! AFI -> isThumb1OnlyFunction ( ) && <STR_LIT> ) ; bool is<ISA_LIT> = ! AFI -> isThumbFunction ( ) ; unsigned VARegSaveSize = AFI -> getVarArgsRegSaveSize ( ) ; int NumBytes = ( int ) MFI -> getStackSize ( ) ; if ( ! AFI -> hasStackFrame ( ) ) { if ( NumBytes != <NUM_LIT> ) emitSPUpdate ( is<ISA_LIT> , MBB , MBBI , dl , TII , NumBytes ) ; } else { const unsigned * CSRegs = getCalleeSavedRegs ( ) ; if ( MBBI != MBB . begin ( ) ) { do -- MBBI ; while ( MBBI != MBB . begin ( ) && isCSRestore ( MBBI , TII , CSRegs ) ) ; if ( ! isCSRestore ( MBBI , TII , CSRegs ) ) ++ MBBI ; } NumBytes -= ( AFI -> getGPRCalleeSavedArea1Size ( ) + AFI -> getGPRCalleeSavedArea2Size ( ) + AFI -> getDPRCalleeSavedAreaSize ( ) ) ; bool HasFP = hasFP ( MF ) ; if ( ( STI . isTargetDarwin ( ) && NumBytes ) || HasFP ) { NumBytes = AFI -> getFramePtrSpillOffset ( ) - NumBytes ; if ( HasFP || AFI -> getGPRCalleeSavedArea2Size ( ) || AFI -> getDPRCalleeSavedAreaSize ( ) || AFI -> getDPRCalleeSavedAreaOffset ( ) ) { if ( NumBytes ) { if ( is<ISA_LIT> ) emit<ISA_LIT>RegPlusImmediate ( MBB , MBBI , dl , <STR_LIT> , FramePtr , - NumBytes , <STR_LIT> , <NUM_LIT> , TII ) ; else emitT2RegPlusImmediate ( MBB , MBBI , dl , <STR_LIT> , FramePtr , - NumBytes , <STR_LIT> , <NUM_LIT> , TII ) ; } else { if ( is<ISA_LIT> ) BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( FramePtr ) . addImm ( ( unsigned ) <STR_LIT> ) . addReg ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) ; else BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( FramePtr ) ; } } } else if ( NumBytes ) emitSPUpdate ( is<ISA_LIT> , MBB , MBBI , dl , TII , NumBytes ) ; movePastCSLoadStoreOps ( MBB , MBBI , <STR_LIT> , <NUM_LIT> , <NUM_LIT> , STI ) ; emitSPUpdate ( is<ISA_LIT> , MBB , MBBI , dl , TII , AFI -> getDPRCalleeSavedAreaSize ( ) ) ; movePastCSLoadStoreOps ( MBB , MBBI , <STR_LIT> , <STR_LIT> , <NUM_LIT> , STI ) ; emitSPUpdate ( is<ISA_LIT> , MBB , MBBI , dl , TII , AFI -> getGPRCalleeSavedArea2Size ( ) ) ; movePastCSLoadStoreOps ( MBB , MBBI , <STR_LIT> , <STR_LIT> , <NUM_LIT> , STI ) ; emitSPUpdate ( is<ISA_LIT> , MBB , MBBI , dl , TII , AFI -> getGPRCalleeSavedArea1Size ( ) ) ; } if ( VARegSaveSize ) emitSPUpdate ( is<ISA_LIT> , MBB , MBBI


<s> bool <STR_LIT> ( SDValue Elt ) { return isNullConstant ( Elt ) || isNullFPConstant (


<s> return legalizeFPTOI ( MI , MRI , B , false ) ; case TargetOpcode :: G_FMINNUM : case TargetOpcode :: G_FMAXNUM : case TargetOpcode :: G_FMINNUM_IEEE : case TargetOpcode :: G_FMAXNUM_IEEE : return legalizeMinNumMaxNum ( Helper , MI ) ; case TargetOpcode :: G_EXTRACT_VECTOR_ELT : return legalizeExtractVectorElt ( MI , MRI , B ) ; case TargetOpcode :: G_INSERT_VECTOR_ELT : return legalizeInsertVectorElt ( MI , MRI , B ) ; case TargetOpcode :: G_SHUFFLE_VECTOR : return legalizeShuffleVector ( MI , MRI , B ) ; case TargetOpcode :: G_F<ISA_LIT>N : case TargetOpcode :: G_FCOS : return legalizeSinCos ( MI , MRI , B ) ; case TargetOpcode :: G_GLOBAL_VALUE : return legalizeGlobalValue ( MI , MRI , B ) ; case TargetOpcode :: G_LOAD : return legalizeLoad ( MI , MRI , B , Observer ) ; case TargetOpcode :: G_FMAD : return legalizeFMad ( MI , MRI , B ) ; case TargetOpcode :: G_FDIV : return legalizeFDIV ( MI , MRI , B ) ; case TargetOpcode :: G_UDIV : case TargetOpcode :: G_UREM : return legalizeUDIV_UREM ( MI , MRI , B ) ; case TargetOpcode :: G_SDIV : case TargetOpcode :: G_SREM : return legalizeSDIV_SREM ( MI , MRI , B ) ; case TargetOpcode :: G_ATOMIC_CMPXCHG : return legalizeAtomicCmpXChg ( MI , MRI , B ) ; case TargetOpcode :: G_FLOG : return legalizeFlog ( MI , B , numbers :: ln2f ) ; case TargetOpcode :: G_FLOG10 : return legalizeFlog ( MI , B , numbers :: ln2f / numbers :: ln10f ) ; case TargetOpcode :: G_FEXP : return legalizeFExp ( MI , B ) ; case TargetOpcode :: G_FPOW : return legalizeFPow ( MI , B ) ; case TargetOpcode :: G_FFLOOR : return legalizeFFloor ( MI , MRI , B ) ; case TargetOpcode :: G_BUILD_VECTOR : return legalizeBuildVector ( MI , MRI , B ) ; default : return false ; } llvm_unreachable ( <STR_LIT> )


<s> MVT VecVT = <STR_LIT> ; if ( Subtarget . useAVX512Regs ( ) && ( is64Bit ( ) || ( CallConv == CallingConv :: <ISA_LIT>_VectorCall || CallConv == CallingConv :: Intel_OCL_BI ) ) ) VecVT = <STR_LIT> ; else if ( Subtarget . hasAVX ( ) ) VecVT = <STR_LIT> ; else if ( Subtarget . hasSSE2 ( ) ) VecVT = <STR_LIT> ; SmallVector < MVT , <NUM_LIT> > RegParmTypes ; MVT IntVT = is64Bit ( ) ? <STR_LIT> : <STR_LIT> ; RegParmTypes . push_back ( IntVT ) ; if ( VecVT != <STR_LIT> ) RegParmTypes . push_back ( VecVT ) ; SmallVectorImpl < ForwardedRegister > & Forwards = FuncInfo -> getForwardedMustTailRegParms ( ) ; CCInfo . analyzeMustTailForwardedRegisters ( Forwards , RegParmTypes , CC_<ISA_LIT> ) ; if ( is64Bit ( ) && ! isWin64 ( )

&& ! CCInfo . isAllocated ( <STR_LIT> ) ) {


<s> return DAG . getNode ( <STR_LIT> , DL , VT , DAG . getConstant ( Pattern ,


<s> result . insert ( result . end ( ) , Definitions . begin ( ) ,


<s> if ( ! isThumb && ( RelocM == Reloc :: PIC_ ) ) return <NUM_LIT> ; unsigned Align = TD . getPrefTypeAlignment ( GV -> getType ( ) ) ; if ( Align == <NUM_LIT> ) { Align = TD . getTypeAllocSize ( GV -> getType ( ) ) ; } unsigned PCAdj = ( RelocM != Reloc :: PIC_ ) ? <NUM_LIT> : ( Subtarget -> isThumb ( ) ? <NUM_LIT> : <NUM_LIT> ) ; unsigned Id = AFI -> createConstPoolEntryUId ( ) ; <ISA_LIT>ConstantPoolValue * CPV = new <ISA_LIT>ConstantPoolValue ( GV , Id , <STR_LIT> , PCAdj ) ; unsigned Idx = MCP . getConstantPoolIndex ( CPV , Align ) ; MachineInstrBuilder MIB ; unsigned DestReg = createResultReg ( TLI . getRegClassFor ( VT ) ) ; if ( isThumb ) { unsigned Opc = ( RelocM != Reloc :: PIC_ ) ? <STR_LIT> : <STR_LIT> ; MIB = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( Opc ) , DestReg ) . addConstantPoolIndex ( Idx ) ; if ( RelocM == Reloc :: PIC_ ) MIB . addImm ( Id ) ; }


<s> for ( int i = <NUM_LIT> , n = Phi -> getNumOperands ( ) ; i < n ; i += <NUM_LIT> ) if ( isLoopFeeder ( L , MBB , Phi , & ( Phi -> getOperand ( i ) ) , LoopFeederPhi ) ) if ( loopCountMayWrapOrUnderFlow ( & ( Phi -> getOperand ( i ) ) , EndVal , Phi -> getParent ( ) , L , LoopFeederPhi ) ) return true ; return


<s> rtx reg ; if ( GET_CODE ( set ) == SET && REG_P ( reg = SET_DEST ( set ) ) && find_reg_note ( insn , REG_UNUSED , reg ) == NULL_RTX ) { emit_insn_after ( nvptx_gen_shuffle ( reg , reg , master , SHUFFLE_IDX ) , insn ) ; return


<s> SDValue <ISA_LIT>TargetLowering :: LowerBR_CC ( SDValue Op , SelectionDAG & DAG ) const { SDValue Chain = Op . getOperand ( <NUM_LIT> ) ; <STR_LIT> CC = cast < CondCodeSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> get ( ) ; SDValue LHS = Op . getOperand ( <NUM_LIT> ) ; SDValue RHS = Op . getOperand ( <NUM_LIT> ) ; SDValue Dest = Op . getOperand ( <NUM_LIT> ) ; SDLoc dl ( Op ) ; if ( isUnsupportedFloatingType ( LHS . getValueType ( ) ) ) { DAG . getTargetLoweringInfo ( ) . softenSetCCOperands ( DAG , LHS . getValueType ( ) , LHS , RHS , CC , dl , LHS , RHS ) ; if ( ! RHS . getNode ( ) ) { RHS = DAG . getConstant ( <NUM_LIT> , dl , LHS . getValueType ( ) ) ; CC = <STR_LIT> ; } } unsigned Opc = LHS . getOpcode ( ) ; bool OptimizeMul = ( Opc == <STR_LIT> || Opc == <STR_LIT> ) && ! Subtarget -> isThumb1Only ( ) ; if ( LHS . getResNo ( ) == <NUM_LIT> && ( isOneConstant ( RHS ) || isNullConstant ( RHS ) ) && ( Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || OptimizeMul ) && ( CC == <STR_LIT> || CC == <STR_LIT> ) ) { if ( ! DAG . getTargetLoweringInfo ( ) . isTypeLegal ( LHS -> getValueType ( <NUM_LIT> ) ) ) return SDValue ( ) ; SDValue Value , OverflowCmp ; SDValue <ISA_LIT>cc ; std :: tie ( Value , OverflowCmp ) = get<ISA_LIT>XALUOOp ( LHS . getValue ( <NUM_LIT> ) , DAG , <ISA_LIT>cc ) ; if ( ( CC == <STR_LIT> ) != isOneConstant ( RHS ) ) { <STR_LIT> CondCode = ( <STR_LIT> ) cast < const ConstantSDNode > ( <ISA_LIT>cc ) -> getZExtValue ( ) ; CondCode = <STR_LIT> ( CondCode ) ; <ISA_LIT>cc = DAG . getConstant ( CondCode , SDLoc ( <ISA_LIT>cc ) , <STR_LIT> ) ; } SDValue CCR = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Chain , Dest ,


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case


<s> unsigned <ISA_LIT>FastISel :: emitAnd_ri ( MVT RetVT , unsigned LHSReg , bool LHSIsKill , uint64_t Imm ) { return emitLogicalOp_ri ( <STR_LIT> , RetVT , LHSReg


<s> if ( ( * annotationCache ) . find ( m ) == ( * annotationCache ) . end ( ) ) cacheAnnotationFromMD ( m , gv ) ; else if ( ( * annotationCache ) [ m ] . find ( gv ) == ( * annotationCache ) [ m ] . end ( ) ) cacheAnnotationFromMD ( m , gv ) ; if ( ( * annotationCache ) [ m ] [ gv ] . find ( prop ) == ( * annotationCache ) [ m ]


<s> } if ( GET_CODE ( operands [ <NUM_LIT> ] ) != CONST_INT ) return <NUM_LIT> ; value = INTVAL ( operands [ <NUM_LIT> ] ) & <NUM_LIT> ; if ( value == <NUM_LIT> ) { if ( currently_expanding_to_rtl ) { emit_insn ( gen_cmpgtsi_t ( force_reg ( SImode , CONST0_RTX ( SImode ) ) , operands [ <NUM_LIT> ] ) ) ; emit_insn ( gen_mov_neg_si_t ( operands [ <NUM_LIT> ] ) ) ; return <NUM_LIT> ; } emit_insn ( gen_ashrsi2_31 ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ) ; return <NUM_LIT> ; } else if ( value >= <NUM_LIT> && value <= <NUM_LIT> ) { wrk = gen_reg_rtx ( SImode ) ; emit_insn ( gen_ashrsi2_16 ( wrk , operands [ <NUM_LIT> ] ) ) ; value -= <NUM_LIT> ; while ( value -- ) gen_ashift ( ASHIFTRT , <NUM_LIT> , wrk ) ; emit_move_insn ( operands [ <NUM_LIT> ] , wrk ) ; return <NUM_LIT> ; } else if ( value <= <NUM_LIT> ) { wrk = gen_reg_rtx ( SImode ) ; emit_move_insn ( wrk , operands [ <NUM_LIT> ] ) ; while ( value -- ) gen_ashift ( ASHIFTRT , <NUM_LIT> , wrk ) ; emit_move_insn ( operands [ <NUM_LIT> ] , wrk ) ; return <NUM_LIT> ; } wrk = gen_reg_rtx ( Pmode ) ; emit_move_insn ( gen_rtx_REG ( SImode , <NUM_LIT> ) , operands [ <NUM_LIT> ] ) ; sprintf ( func , <STR_LIT> ,


<s> AU . addRequired < MachineDominatorTree > ( ) ; AU . addPreserved < MachineDominatorTree > ( ) ; AU . addRequired < MachinePostDominatorTree > ( ) ; AU . addPreserved < MachinePostDominatorTree > ( ) ; MachineFunctionPass :: getAnalysisUsage (


<s> return SelectAddrModeRO ( N , <NUM_LIT> , Base


<s> _Unwind_Word _Unwind_GetCFA ( _Unwind_Context * context ) { return ( ( phase1_vrs * ) context )


<s> if ( static_cast < int > ( RCID ) == - <NUM_LIT> )


<s> BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) ) . addReg ( DemoteRegTo32 ( SrcReg ) ) . addReg ( FlagUseZeroBasedSandbox ? <NUM_LIT> : <STR_LIT> ) ; MI . eraseFromParent ( ) ; return true ; } if ( Opc == <STR_LIT> ) { assert ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) ; if ( FlagUseZeroBasedSandbox ) return false ; BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) ) . addOperand ( MI . getOperand ( <NUM_LIT> ) ) . addOperand ( MI . getOperand ( <NUM_LIT> ) ) . addOperand ( MI . getOperand ( <NUM_LIT> ) ) . addOperand ( MI . getOperand ( <NUM_LIT> ) ) . addOperand ( MI . getOperand ( <NUM_LIT> ) ) . addReg ( FlagUseZeroBasedSandbox ? <NUM_LIT> : <STR_LIT> ) ; MI . eraseFromParent ( ) ; return true ; } if ( Opc == <STR_LIT> ) { assert ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) . addReg ( FlagUseZeroBasedSandbox ? <NUM_LIT> : <STR_LIT> ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) ) . addImm (


<s> auto AlignVectors :: getAddrInfo ( Instruction & In ) const -> Optional < AddrInfo > { if ( auto * L = isCandidate < LoadInst > ( & In ) ) return AddrInfo ( HVC , L , L -> getPointerOperand ( ) , L -> getType ( ) , L -> getAlign ( ) ) ; if ( auto * S = isCandidate < StoreInst > ( & In ) ) return AddrInfo ( HVC , S , S -> getPointerOperand ( ) , S -> getValueOperand ( ) -> getType ( ) , S -> getAlign ( ) ) ; if ( auto * II = isCandidate < IntrinsicInst > ( & In ) ) { <STR_LIT> ID = II -> getIntrinsicID ( ) ; switch ( ID


<s> case <STR_LIT> : return SetBlendDomain ( <NUM_LIT> , false ) ; case <STR_LIT> : case <STR_LIT> : return SetBlendDomain ( <NUM_LIT> , true ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { if ( Subtarget . hasDQI ( ) ) return false ; const uint16_t * table = lookupAVX512 ( MI . getOpcode ( ) , dom , ReplaceableCustomAVX512LogicInstrs ) ; assert ( table && <STR_LIT> ) ; if ( Domain == <NUM_LIT> && ( dom == <NUM_LIT> || table [ <NUM_LIT> ] == MI . getOpcode ( ) ) ) Domain = <NUM_LIT> ; MI . setDesc ( get ( table [ Domain - <NUM_LIT> ] ) ) ; return true ; } case <STR_LIT> : case <STR_LIT> : if ( Domain != dom && Domain != <NUM_LIT> && MI . getOperand ( <NUM_LIT> ) . getReg ( ) == MI . getOperand ( <NUM_LIT> ) . getReg ( ) && MI . getOperand ( <NUM_LIT> ) . getSubReg ( ) == <NUM_LIT> && MI . getOperand ( <NUM_LIT> ) . getSubReg ( ) == <NUM_LIT> && MI . getOperand ( <NUM_LIT> ) . getSubReg ( ) == <NUM_LIT> ) { commuteInstruction ( MI , false ) ; return true ; } if ( Opcode == <STR_LIT> ) return true ; break ; case <STR_LIT> : { if ( Domain ==


<s> j ++ ) { if ( j -> isCall ( ) ) { MachineBasicBlock :: iterator p ( llvm :: next ( j ) ) ; emitSTC ( MF , * i , p , <STR_LIT>


<s> if ( Chain . getOpcode ( ) == <STR_LIT> ) { SDValue PrevChain = Chain -> getOperand ( <NUM_LIT> ) , Cond = Chain -> getOperand ( <NUM_LIT> ) , ThenBr = Chain -> getOperand ( <NUM_LIT> ) , ElseBr = Dest ; ThenBr = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , ThenBr , Zero ) ; ElseBr = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , ElseBr , Zero ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , PrevChain , Cond


<s> MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; <ISA_LIT>MachineFunctionInfo * FuncInfo = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; const bool SpillVGPRToAGPR = ST . hasMAIInsts ( ) && FuncInfo -> hasSpilledVGPRs ( ) && EnableSpillVGPRToAGPR ; if ( SpillVGPRToAGPR ) { BitVector SpillFIs ( MFI . getObjectIndexEnd ( ) , false ) ; bool SeenDbgInstr = false ; for ( MachineBasicBlock & MBB : MF ) { MachineBasicBlock :: iterator Next ; for ( auto I = MBB . begin ( ) , E = MBB . end ( ) ; I != E ; I = Next ) { MachineInstr & MI = * I ; Next = std :: next ( I ) ; if ( MI . isDebugInstr ( ) ) SeenDbgInstr = true ; if ( TII -> isVGPRSpill ( MI ) ) { unsigned FIOp = <STR_LIT> ( MI . getOpcode ( ) , <STR_LIT> :: vaddr ) ; int FI = MI . getOperand ( FIOp ) . getIndex ( ) ; Register VReg = TII -> getNamedOperand ( MI , <STR_LIT> :: vdata ) -> getReg ( ) ; if ( FuncInfo -> allocateVGPRSpillToAGPR ( MF , FI , TRI -> isAGPR ( MRI , VReg ) ) ) { RS -> enterBasicBlock ( MBB ) ; TRI -> eliminateFrameIndex ( MI ,


<s> extern __inline __m512i __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) _mm512_maskz_loadu_epi32 ( __mmask16 __U , void const * __P ) { return ( __m512i ) __builtin_ia32_loaddqusi512_mask ( ( const int * ) __P , (


<s> if ( ! addr ) return FALSE ; tree fntype = TREE_TYPE


<s> Inst . addOperand ( MCOperand :: CreateReg ( CRRegs [


<s> int64_t imm = fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ; imm |= fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) ; if ( imm & ( <NUM_LIT> << ( <NUM_LIT> - <NUM_LIT> ) ) ) imm |= ~ ( ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) ; DecodeGPR64RegisterClass ( Inst , Rd


<s> return new <ISA_LIT>DAGToDAGISel ( TM )


<s> if ( Ty . second ) Ty . second -> dump ( ) ; else dbgs ( ) << <STR_LIT> ; dbgs ( ) << <STR_LIT> ; } )


<s> o << getTagName ( PREFIX_SYMBOL ) << prefix << <STR_LIT> << num << <STR_LIT> ; return o .


<s> Offset -= Anchor ; if ( Offset != <NUM_LIT> && ( Offset & <NUM_LIT> ) == <NUM_LIT> ) { SDValue Full = DAG . getTargetGlobalAddress ( GV , DL , PtrVT , Anchor + Offset ) ; Result = DAG . getNode ( <STR_LIT> , DL , PtrVT , Full , Result ) ; Offset = <NUM_LIT> ; } } else { Result = DAG . getTargetGlobalAddress ( GV , DL , PtrVT , <NUM_LIT> , <STR_LIT> ) ; Result = DAG . getNode ( <STR_LIT> , DL , PtrVT , Result ) ; Result = DAG . getLoad ( PtrVT , DL , DAG . getEntryNode ( ) , Result , MachinePointerInfo ::

getGOT ( DAG . getMachineFunction ( ) ) ) ;


<s> const TargetRegisterClass * <ISA_LIT>RegisterInfo :: getPointerRegClass ( const MachineFunction & MF , unsigned Kind ) const { switch ( Kind )


<s> SDValue AddrOp ; if ( LDN ) AddrOp = LDN -> getOperand ( <NUM_LIT> ) ; else if ( STN ) AddrOp = STN -> getOperand ( <NUM_LIT> ) ; short Imm = <NUM_LIT> ; if ( AddrOp . getOpcode ( ) == <STR_LIT> ) { if ( FrameIndexSDNode * FI = dyn_cast < FrameIndexSDNode > ( AddrOp . getOperand ( <NUM_LIT> ) ) ) { const MachineFrameInfo & MFI = CurDAG -> getMachineFunction ( ) . getFrameInfo ( ) ; unsigned SlotAlign = MFI . getObjectAlignment ( FI -> getIndex ( ) ) ; if ( ( SlotAlign % Val ) != <NUM_LIT> ) return false ; } return isIntS16Immediate ( AddrOp . getOperand ( <NUM_LIT> ) , Imm )


<s> maybeUpdateTerminator ( MBB ) ; break ; } for ( ; ; ) { Next = Ready . top ( ) ; Ready . pop ( ) ; if ( ! Entries . empty ( ) && ! MDT . dominates ( Entries . back ( ) . TheRegion -> getHeader ( ) , Next ) ) { Entries . back ( ) . Deferred . push_back ( Next ) ; continue ; } break ; } } Next -> moveAfter ( MBB ) ; maybeUpdateTerminator ( MBB ) ; MBB = Next ; } assert ( Entries . empty ( ) && <STR_LIT> ) ; MF . RenumberBlocks ( ) ; SmallSetVector < const Region * , <NUM_LIT> > OnStack ; OnStack . insert ( nullptr ) ; for ( auto & MBB : MF ) { assert ( MBB . getNumber ( ) >= <NUM_LIT> && <STR_LIT> ) ; const Region * Region = RI . getRegionFor ( & MBB ) ; if ( Region && & MBB == Region -> getHeader ( ) ) { if ( Region -> isLoop ( ) ) { for ( auto Pred : MBB . predecessors ( ) ) assert ( ( Pred -> getNumber ( ) < MBB . getNumber ( ) || Region -> contains ( Pred ) ) && <STR_LIT> <STR_LIT> ) ; } else { for ( auto Pred : MBB . predecessors ( ) ) assert ( Pred -> getNumber ( ) < MBB . getNumber ( ) && <STR_LIT> ) ; } assert ( OnStack . insert ( Region ) && <STR_LIT> ) ; } else { for ( auto Pred : MBB . predecessors ( ) ) assert ( Pred -> getNumber ( ) < MBB . getNumber ( ) && <STR_LIT> ) ; assert ( OnStack . count ( RI . getRegionFor ( & MBB


<s> DebugLoc dl = Op . getDebugLoc ( ) ; SDValue A = Op . getOperand ( <NUM_LIT> ) ; SDValue B = Op . getOperand ( <NUM_LIT> ) ; if ( VT == <STR_LIT> ) { assert ( Subtarget -> hasAVX2 ( ) && <STR_LIT> ) ; SDValue Ahi = DAG . getNode ( <STR_LIT> , dl , VT , DAG . getConstant ( <STR_LIT> , <STR_LIT> ) , A , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDValue Bhi = DAG . getNode ( <STR_LIT> , dl , VT , DAG . getConstant ( <STR_LIT> , <STR_LIT> ) , B , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDValue AloBlo = DAG . getNode ( <STR_LIT> , dl , VT , DAG . getConstant ( <STR_LIT> , <STR_LIT> ) , A , B ) ; SDValue AloBhi = DAG . getNode ( <STR_LIT> , dl , VT , DAG . getConstant ( <STR_LIT> , <STR_LIT> ) , A , Bhi ) ; SDValue AhiBlo = DAG . getNode ( <STR_LIT> , dl , VT , DAG . getConstant ( <STR_LIT> , <STR_LIT> ) , Ahi , B ) ; AloBhi = DAG . getNode ( <STR_LIT> , dl , VT , DAG . getConstant ( <STR_LIT> , <STR_LIT> ) , AloBhi , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; AhiBlo = DAG . getNode ( <STR_LIT> , dl , VT , DAG . getConstant ( <STR_LIT> , <STR_LIT> ) , AhiBlo , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDValue Res = DAG . getNode ( <STR_LIT> , dl , VT , AloBlo , AloBhi ) ; Res = DAG . getNode ( <STR_LIT> , dl , VT , Res , AhiBlo ) ; return Res


<s> state -> insns_left = state -> issue_rate ; advance_state ( curr_state )


<s> if ( current_frame_info . total_size == <NUM_LIT> && current_frame_info . gmask ) abort ( ) ; if ( current_frame_info . pretend_size ) { int regs_to_save = current_frame_info . pretend_size / UNITS_PER_WORD ; for ( regno = FIRST_ARG_REGNUM + FR30_NUM_ARG_REGS ; regno -- , regs_to_save -- ; ) { insn = emit_insn ( gen_movsi_push ( gen_rtx_REG ( Pmode , regno ) ) ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; } } if ( current_frame_info . gmask ) { for ( regno = STACK_POINTER_REGNUM ; regno -- ; ) { if ( ( current_frame_info . gmask & ( <NUM_LIT> << regno ) ) != <NUM_LIT> ) { insn = emit_insn ( gen_movsi_push ( gen_rtx_REG ( Pmode , regno ) ) ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; } } } if ( current_frame_info . save_rp ) { insn = emit_insn ( gen_movsi_push ( gen_rtx_REG ( Pmode , RETURN_POINTER_REGNUM ) ) ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; } if ( current_frame_info . save_fp ) { if ( current_frame_info . frame_size < ( ( <NUM_LIT> << <NUM_LIT> ) - UNITS_PER_WORD ) ) { int enter_size = current_frame_info . frame_size + UNITS_PER_WORD ; rtx pattern ; insn = emit_insn ( gen_enter_func ( GEN_INT ( enter_size ) ) ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; pattern = PATTERN ( insn ) ; if ( GET_CODE ( pattern ) == PARALLEL ) { int x ; for ( x = XVECLEN ( pattern , <NUM_LIT> ) ; x -- ; ) { rtx part = XVECEXP ( pattern , <NUM_LIT> , x ) ; if ( ! frame_pointer_needed && GET_CODE ( part ) == SET && REGNO ( SET_DEST ( part ) ) == HARD_FRAME_POINTER_REGNUM ) RTX_FRAME_RELATED_P ( part ) = <NUM_LIT> ; else RTX_FRAME_RELATED_P ( part ) = <NUM_LIT> ; } } } else { insn = emit_insn ( gen_movsi_push ( frame_pointer_rtx ) ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; if ( frame_pointer_needed ) { insn = emit_insn ( gen_movsi ( frame_pointer_rtx , stack_pointer_rtx


<s> else if ( SignExtend32 < <NUM_LIT> > ( Lo12 >> <NUM_LIT> ) == SignExtend32 < <NUM_LIT> > ( Hi20 ) ) Insts . push_back ( Inst ( <STR_LIT> , SignExtend64 < <NUM_LIT> > ( Lo12 ) ) ) ; else { Insts . push_back ( Inst ( <STR_LIT> , SignExtend64 < <NUM_LIT> > ( Hi20 ) ) ) ; if ( Lo12 != <NUM_LIT> ) Insts . push_back ( Inst ( <STR_LIT> , Lo12 ) ) ; } if ( SignExtend32 < <NUM_LIT> > ( Hi20 >> <NUM_LIT> ) != SignExtend32 < <NUM_LIT> > ( Higher20 ) ) Insts . push_back ( Inst ( <STR_LIT> , SignExtend64 < <NUM_LIT> > ( Higher20 ) ) ) ; if ( SignExtend32 < <NUM_LIT> > ( Higher20 >> <NUM_LIT> ) != SignExtend32 < <NUM_LIT> > ( Highest12 ) ) Insts . push_back ( Inst ( <STR_LIT> , SignExtend64 < <NUM_LIT> > ( Highest12 ) ) ) ; return Insts


<s> if ( ! isIntrinsic ) return ( Cnt >= <NUM_LIT> && Cnt <= ( isNarrow ? ElementBits / <NUM_LIT> : ElementBits ) ) ; if ( Cnt >= - ( isNarrow ? ElementBits / <NUM_LIT> : ElementBits ) && Cnt <=


<s> TargetTransformInfo <ISA_LIT>BaseTargetMachine :: getTargetTransformInfo ( const Function


<s> } if ( Target . getSymB ( ) ) { recordScatteredRelocation ( Writer , Asm , Layout , Fragment , Fixup , Target , Log2Size , FixedValue ) ; return ; } const MCSymbol * A = nullptr ; if ( Target . getSymA ( ) ) A = & Target . getSymA ( ) -> getSymbol ( ) ; uint32_t Offset = Target . getConstant ( ) ; if ( IsPCRel ) Offset += <NUM_LIT> << Log2Size ; if ( Offset && A && ! Writer -> doesSymbolRequireExternRelocation ( * A ) && recordScatteredRelocation ( Writer , Asm , Layout , Fragment , Fixup , Target , Log2Size , FixedValue ) ) return ; uint32_t FixupOffset = Layout . getFragmentOffset ( Fragment ) + Fixup . getOffset ( ) ; unsigned Index = <NUM_LIT> ; unsigned Type = <NUM_LIT> ; const MCSymbol * RelSymbol


<s> switch ( BranchOpc ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : return <STR_LIT> ( BrOffset ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> UseDataRegionDirectives = true ; ZeroDirective = <STR_LIT> ; Data8bitsDirective = <STR_LIT> ; Data16bitsDirective = <STR_LIT> ; Data32bitsDirective = <STR_LIT> ; Data64bitsDirective = <STR_LIT> ; AlignmentIsInBytes = false ; COMMDirectiveAlignmentIsInBytes = false ; LCOMMDirectiveAlignmentType = LCOMM :: Log2Alignment ; SupportsDebugInformation =


<s> if ( align > MOVE_MAX ) align = MOVE_MAX ; move_ratio = <NUM_LIT> ; if ( optimize > <NUM_LIT> ) move_ratio = LARGEST_MOVE_RATIO ; num_pieces = ( bytes / align ) + ( ( bytes % align + <NUM_LIT> ) / <NUM_LIT> ) ; if ( num_pieces > move_ratio ) return <NUM_LIT> ; x = XEXP ( dst_mem , <NUM_LIT> ) ; if ( ! REG_P ( x ) ) { x = force_reg ( Pmode , x ) ; dst_mem = replace_equiv_address ( dst_mem , x ) ; } x = XEXP ( src_mem , <NUM_LIT> ) ; if ( ! REG_P ( x ) ) { x = force_reg ( Pmode , x ) ; src_mem = replace_equiv_address ( src_mem , x ) ; } active [ <NUM_LIT> ] = active [ <NUM_LIT> ] = false ; do { next = phase ; phase ^= <NUM_LIT> ; if ( bytes > <NUM_LIT> ) { int next_amount ; next_amount = ( bytes >= <NUM_LIT> ? <NUM_LIT> : ( bytes >= <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ) ) ; next_amount = MIN ( next_amount , align ) ; amount [ next ] = next_amount ; mode [ next ] = mode_from_align [ next_amount


<s> if ( MO . readsReg ( ) || MI . readsVirtualRegister ( Reg ) ) return <NUM_LIT> ; } else { if ( MI . readsRegister ( Reg , TRI ) ) return <NUM_LIT> ; } return


<s> i2 = prev_nonnote_insn ( i3 ) ; if ( i2 == NULL_RTX ) return <NUM_LIT> ; i1 = prev_nonnote_insn ( i2 ) ; if ( i1 == NULL_RTX ) return <NUM_LIT> ; return ( INSN_P ( i1 ) && rtx_equal_p ( PATTERN ( i1 ) , PATTERN ( i3 ) )

&& any_condjump_p ( i2 ) && onlyjump_p ( i2 ) ) ;


<s> SDValue N00 = N0 -> getOperand ( <NUM_LIT> ) ; if ( N00 . getValueType ( ) == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , SDLoc ( N00 ) , VT , N00 ) ; } unsigned FPOpcode ; switch ( N0 . getOpcode ( ) ) { case <STR_LIT> : FPOpcode = <STR_LIT> ; break ; case <STR_LIT> : FPOpcode = <STR_LIT> ; break ; case <STR_LIT> : FPOpcode = <STR_LIT> ; break ; default : return SDValue ( ) ; } if ( ! ( ( Subtarget . hasSSE1 ( ) && VT == <STR_LIT> ) || ( Subtarget . hasSSE2 ( ) && VT == <STR_LIT> ) ) ) return SDValue ( ) ; SDValue LogicOp0 = N0 . getOperand ( <NUM_LIT> ) ; SDValue LogicOp1 = N0 . getOperand ( <NUM_LIT> ) ; SDLoc DL0 ( N0


<s> if ( FenceOrdering == AtomicOrdering :: SequentiallyConsistent && FenceSSID == SyncScope :: System ) { if ( Subtarget . hasMFence ( ) ) return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) ) ; SDValue Chain = Op . getOperand ( <NUM_LIT> ) ; SDValue Zero = DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ; SDValue Ops [ ] = { DAG . getRegister ( <STR_LIT> , <STR_LIT> ) , DAG . getTargetConstant ( <NUM_LIT> , dl , <STR_LIT> ) , DAG . getRegister ( <NUM_LIT> , <STR_LIT> ) , DAG . getTargetConstant ( <NUM_LIT> , dl , <STR_LIT> ) , DAG . getRegister ( <NUM_LIT> , <STR_LIT> ) , Zero , Chain } ; SDNode * Res = DAG . getMachineNode ( <STR_LIT> , dl , <STR_LIT> , Ops ) ; return SDValue ( Res , <NUM_LIT>


<s> if ( MI . getDesc ( ) . isCall ( ) ) break ; PotentialBlockers . push_back ( & MI ) ; } if ( BlockLimit < LIMIT ) { MachineBasicBlock * MBB = LoadInst -> getParent ( ) ; int LimitLeft = LIMIT - BlockLimit ; for ( MachineBasicBlock :: pred_iterator PB = MBB -> pred_begin ( ) , PE = MBB -> pred_end ( ) ; PB != PE ; ++ PB ) { MachineBasicBlock * PMBB


<s> } for ( MachineFunction :: iterator MBB = Fn . begin ( ) , MBBe = Fn . end ( ) ; MBB != MBBe ; ++ MBB ) { unsigned RemainingCount = MBB -> size ( ) ; for ( MachineBasicBlock :: iterator RegionEnd = MBB -> end ( ) ; RegionEnd != MBB -> begin ( ) ; ) { MachineBasicBlock :: iterator I = RegionEnd ; for ( ; I != MBB -> begin ( ) ; -- I , -- RemainingCount ) { if ( TII -> isSchedulingBoundary ( llvm :: prior ( I ) , MBB , Fn ) ) break ; } I = MBB -> begin ( ) ; if ( I == RegionEnd ) { RegionEnd = llvm :: prior ( RegionEnd ) ; --


<s> bool MadeChange = false ; for ( unsigned i = <NUM_LIT> , e = PushPopMIs . size ( ) ; i != e ; ++ i ) { MachineInstr * MI = PushPopMIs [ i ] ; if ( MI -> getOpcode ( ) == <STR_LIT> && MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> && MI -> getNumExplicitOperands ( ) == <NUM_LIT> ) { BuildMI ( MI -> getParent ( ) , MI -> getDebugLoc ( ) , TII ->


<s> EVT VT = Op . getValueType ( ) ; SDLoc dl ( Op ) ; unsigned Depth = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; const <ISA_LIT>RegisterInfo * RegInfo = static_cast < const <ISA_LIT>RegisterInfo * > ( DAG . getTarget ( ) . getRegisterInfo ( ) ) ; unsigned FrameReg = RegInfo -> getPtrSizedFrameRegister ( DAG . getMachineFunction ( ) ) ; assert ( ( ( FrameReg == <STR_LIT> && VT == <STR_LIT> ) || ( FrameReg == <STR_LIT> && VT == <STR_LIT>


<s> compression_flags = mips_get_compress_on_flags ( * attributes ) ; nocompression_flags = mips_get_compress_off_flags ( * attributes ) ; if ( TREE_CODE ( decl ) != FUNCTION_DECL ) { if ( nocompression_flags ) error ( <STR_LIT> , mips_get_compress_off_name ( nocompression_flags ) ) ; if ( compression_flags ) error ( <STR_LIT> , mips_get_compress_on_name ( nocompression_flags ) ) ; } else { compression_flags |= mips_get_compress_on_flags ( DECL_ATTRIBUTES ( decl ) ) ; nocompression_flags |= mips_get_compress_off_flags ( DECL_ATTRIBUTES ( decl ) ) ; if ( compression_flags && nocompression_flags ) error ( <STR_LIT> , DECL_NAME ( decl ) , mips_get_compress_on_name ( compression_flags ) , mips_get_compress_off_name ( nocompression_flags ) ) ; if ( compression_flags & MASK_MIPS16 && compression_flags & MASK_MICROMIPS ) error ( <STR_LIT> , DECL_NAME ( decl ) , <STR_LIT> , <STR_LIT> ) ; if ( TARGET_FLIP_MIPS16 && ! DECL_ARTIFICIAL ( decl ) && compression_flags == <NUM_LIT> && nocompression_flags == <NUM_LIT> ) { name = mflip_mips16_use_mips16_p ( decl ) ? <STR_LIT> : <STR_LIT> ; * attributes = tree_cons ( get_identifier ( name ) , NULL , *


<s> for ( ; M != E ; ++ M ) { if ( M -> definesRegister ( SReg , TRI ) ) break ; if ( M -> modifiesRegister ( SReg , TRI ) ) return Changed ; ReadsSreg |= M -> readsRegister ( SReg , TRI ) ; } if ( M == E || ! M -> isMoveImmediate ( ) || ! M -> getOperand ( <NUM_LIT> ) . isImm ( ) || M -> getOperand ( <NUM_LIT> ) . getImm ( ) != - <NUM_LIT> ) return Changed ; if ( ! ReadsSreg && Op2 . isKill ( ) ) { A -> getOperand ( <NUM_LIT> ) . ChangeToImmediate ( - <NUM_LIT> ) ; M -> eraseFromParent ( ) ; } } if ( ! ReadsCond && A -> registerDefIsDead ( <STR_LIT> ) && MI . killsRegister ( CondReg , TRI ) ) A -> eraseFromParent ( ) ; bool IsVCCZ = MI . getOpcode ( ) == <STR_LIT> ; if ( SReg == ExecReg ) { if ( IsVCCZ ) { MI . eraseFromParent ( ) ; return true ; } MI . setDesc ( TII -> get ( <STR_LIT> ) ) ; } else


<s> void dump ( ) { dbgs ( ) << <STR_LIT> << this << '\n' ; dbgs ( ) << <STR_LIT> ; if ( Base_Reg . getNode ( ) ) Base_Reg . getNode ( ) -> dump ( ) ; else dbgs ( ) << <STR_LIT> ; if ( BaseType == FrameIndexBase ) dbgs ( ) << <STR_LIT> << Base_FrameIndex << '\n' ; dbgs ( ) << <STR_LIT> << Scale << '\n' << <STR_LIT> ; if ( IndexReg . getNode ( ) ) IndexReg . getNode ( ) -> dump ( ) ; else dbgs ( ) << <STR_LIT> ; dbgs ( ) << <STR_LIT> << Disp << '\n' << <STR_LIT> ; if ( GV ) GV -> dump ( ) ; else dbgs ( ) << <STR_LIT> ; dbgs ( ) << <STR_LIT> ; if ( CP ) CP -> dump ( ) ; else dbgs ( ) << <STR_LIT> ; dbgs ( ) << '\n' << <STR_LIT> ; if ( ES ) dbgs ( ) << ES ; else dbgs ( ) << <STR_LIT> ; dbgs ( ) << <STR_LIT> ; if ( MCSym ) dbgs ( ) << MCSym ; else dbgs (


<s> ++ NumLFENCEsInserted ; return ; } unsigned StateReg = PS -> SSA . GetValueAtEndOfBlock ( & MBB ) ; mergePredStateIntoSP ( MBB , InsertPt , Loc , StateReg ) ; if ( MI . isReturn ( ) || ( std :: next ( InsertPt ) == MBB . end ( ) && MBB . succ_empty ( ) ) ) return ; MCSymbol * RetSymbol = MF . getContext ( ) . createTempSymbol ( <STR_LIT> , true ) ; MI . setPostInstrSymbol ( MF , RetSymbol ) ; const TargetRegisterClass * AddrRC = & <STR_LIT> ; unsigned ExpectedRetAddrReg = <NUM_LIT> ; if ( ! Subtarget -> getFrameLowering ( ) -> has128ByteRedZone ( MF ) || MF . exposesReturnsTwice ( ) ) { ExpectedRetAddrReg = MRI -> createVirtualRegister ( AddrRC ) ; if ( MF . getTarget ( ) . getCodeModel ( ) == CodeModel :: Small && ! Subtarget -> isPositionIndependent ( ) ) { BuildMI ( MBB , InsertPt , Loc , TII -> get ( <STR_LIT> ) , ExpectedRetAddrReg ) . addSym ( RetSymbol ) ; } else { BuildMI ( MBB , InsertPt , Loc , TII -> get ( <STR_LIT> ) , ExpectedRetAddrReg ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) . addSym ( RetSymbol ) . addReg ( <NUM_LIT> ) ; } } ++ InsertPt


<s> void GCNSubtarget :: getPostRAMutations ( std :: vector < std :: unique_ptr < ScheduleDAGMutation >> & Mutations ) const { Mutations . push_back ( std :: make_unique < MemOpClusterMutation > ( & InstrInfo ) ) ; Mutations . push_back ( std :: make_unique < FillMFMAShadowMutation >


<s> * no_add_attrs = true ; } else if ( ( is_attribute_p ( <STR_LIT> , name ) && lookup_attribute ( <STR_LIT> , TYPE_ATTRIBUTES ( * type ) ) ) || ( ( is_attribute_p ( <STR_LIT> , name ) && lookup_attribute ( <STR_LIT> , TYPE_ATTRIBUTES ( * type ) ) ) ) ) { warning ( OPT_Wattributes , <STR_LIT> , IDENTIFIER_POINTER ( name


<s> Value * <ISA_LIT>IREmitter :: visitVLD3DUP_UPD ( const SDNode * N ) { llvm_unreachable ( <STR_LIT> )