<s> if ( getChunk ( UImm , <NUM_LIT> ) == getChunk ( UImm , <NUM_LIT> ) ) { uint64_t OrrImm = replicateChunk ( UImm , <NUM_LIT> , <NUM_LIT> ) ; if ( tryOrrMovk ( UImm , OrrImm , MI , MBB , MBBI , TII , <NUM_LIT> ) ) return true ; OrrImm = replicateChunk ( UImm , <NUM_LIT> , <NUM_LIT> ) ; if ( tryOrrMovk ( UImm , OrrImm , MI , MBB , MBBI , TII , <NUM_LIT> ) ) return true ; } else if ( getChunk ( UImm , <NUM_LIT> ) == getChunk ( UImm , <NUM_LIT> ) ) { uint64_t OrrImm = replicateChunk ( UImm , <NUM_LIT> , <NUM_LIT> ) ; if ( tryOrrMovk ( UImm , OrrImm , MI , MBB , MBBI , TII , <NUM_LIT> ) ) return true ; OrrImm = replicateChunk ( UImm , <NUM_LIT> , <NUM_LIT> ) ; if ( tryOrrMovk ( UImm , OrrImm , MI , MBB , MBBI , TII , <NUM_LIT> ) ) return true ; } } if ( BitSize == <NUM_LIT> && tryToreplicateChunks ( UImm , MI , MBB , MBBI , TII ) ) return true ; if ( BitSize == <NUM_LIT> && trySequenceOfOnes ( UImm , MI , MBB , MBBI , TII ) ) return true ; bool isNeg = false ; if ( OneChunks > ZeroChunks ) { isNeg = true ; Imm = ~ Imm ; } unsigned FirstOpc ; if ( BitSize == <NUM_LIT> ) { Imm &= ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ; FirstOpc = ( isNeg ? <STR_LIT> : <STR_LIT> ) ; } else { FirstOpc = ( isNeg ? <STR_LIT> : <STR_LIT> ) ; } unsigned Shift = <NUM_LIT> ; unsigned LastShift = <NUM_LIT> ; if ( Imm != <NUM_LIT> ) { unsigned LZ = countLeadingZeros ( Imm ) ; unsigned TZ = countTrailingZeros ( Imm


<s> SMLoc S = Tok . getLoc ( ) ; if ( Tok . isNot ( AsmToken :: Identifier ) ) { Error ( S , <STR_LIT> ) ; return MatchOperand_ParseFail ; } int Val = StringSwitch < int > ( Tok . getString ( ) . lower ( ) ) . Case ( <STR_LIT> , <NUM_LIT>

) . Case ( <STR_LIT> , <NUM_LIT> ) . Default ( - <NUM_LIT> ) ;


<s> return CC_FP_GTEmode ; } return CC_FPmode ; } else if ( ( op == EQ || op == NE ) && GET_CODE ( x ) == ZERO_EXTRACT && XEXP ( x , <NUM_LIT> ) == const1_rtx && CONST_INT_P ( XEXP ( x , <NUM_LIT> ) ) ) return CC_N_NEmode ; else if ( ( op == GEU || op == LTU ) && GET_CODE ( x ) == PLUS ) return CC_C_LTUmode ; else if ( ( op == LEU || op == GTU ) &&

GET_CODE ( x ) == MINUS ) return CC_C_GTUmode ;


<s> if ( ! T || T -> getBitWidth ( ) > DestTy -> getBitWidth ( ) ) return false ; if ( T -> getBitWidth ( ) == DestTy -> getBitWidth ( ) ) return true ; Instruction * In = dyn_cast < Instruction > ( Val ) ; if ( ! In ) return true ; switch ( In -> getOpcode ( ) ) { case Instruction :: PHI : case Instruction :: ZExt : case Instruction ::


<s> if ( hasFP ( MF ) ) MRI . setPhysRegUsed ( FP ) ; if ( hasBP ( MF ) ) MRI . setPhysRegUsed ( BP ) ; if ( <ISA_LIT>FI -> callsEhReturn ( ) ) <ISA_LIT>FI -> createEhDataRegsFI ( ) ; if ( ExpandPseudo ( MF ) . expand ( ) ) { const TargetRegisterClass * RC = STI . has<ISA_LIT>64 ( ) ? & <STR_LIT> : & <STR_LIT> ; int FI = MF . getFrameInfo ( ) -> CreateStackObject ( RC -> getSize ( ) , RC -> getAlignment ( ) , false ) ; RS -> addScavengingFrameIndex (


<s> return __builtin_aarch64_usqaddv8qi_uus ( __a ,


<s> Tile64Type Tile64VLIWPacketizerList :: Tile64TypeOf ( const MachineInstr * MI ) const { const uint64_t F = MI -> getDesc


<s> int NonInlineUseOpNo = - <NUM_LIT> ; MachineRegisterInfo :: use_iterator NextUse ; for ( MachineRegisterInfo :: use_iterator Use = MRI -> use_begin ( Dst . getReg ( ) ) , E = MRI -> use_end ( ) ; Use != E ; Use = NextUse ) { NextUse = std :: next ( Use ) ; MachineInstr * UseMI = Use -> getParent ( ) ; unsigned OpNo = Use . getOperandNo ( ) ; if ( OpToFold . isImm ( ) && tryConstantFoldOp ( * MRI , TII , UseMI , & OpToFold ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * UseMI << '\n' ) ; NextUse = MRI -> use_begin ( Dst . getReg ( ) ) ; FoldList . clear ( ) ; continue ; } if ( isInlineConstantIfFolded ( TII , * UseMI , OpNo , OpToFold ) ) { foldOperand ( OpToFold , UseMI , OpNo , FoldList , CopiesToReplace ) ; } else { if ( ++ NumLiteralUses == <NUM_LIT> ) { NonInlineUse = & * Use ; NonInlineUseOpNo =


<s> uint64_t encoding = <STR_LIT> ( MCE -> getValue ( ) & <NUM_LIT> , <NUM_LIT> ) ; Inst . addOperand ( MCOperand :: createImm ( encoding )


<s> const char * getPassName ( ) const override { return <STR_LIT>


<s> { errs ( ) << <STR_LIT> << RegVT . getSimpleVT ( ) . SimpleTy << <STR_LIT> ; llvm_unreachable ( <NUM_LIT> ) ; } case <STR_LIT> : VReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; MRI . addLiveIn ( VA . getLocReg ( ) , VReg ) ; ArgValue = DAG . getCopyFromReg ( Chain , dl , VReg , RegVT ) ; InVals . push_back ( ArgValue ) ; break ; case <STR_LIT> : VReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; MRI . addLiveIn ( VA . getLocReg ( ) , VReg ) ; ArgValue = DAG . getCopyFromReg ( Chain , dl , VReg , RegVT ) ; InVals . push_back ( ArgValue ) ; break ; } } else { assert ( VA . isMemLoc ( ) ) ; <ISA_LIT>FI -> setNeedFP ( ) ; SDValue InVal ; unsigned Size = VA . getLocVT ( ) . getStoreSize ( ) ; if ( Size > <NUM_LIT> ) errs ( ) << <STR_LIT> << EVT ( VA . getLocVT ( ) ) . getEVTString ( ) << <STR_LIT> ; int FI = MFI -> CreateFixedObject ( Size , VA . getLocMemOffset ( ) , true ) ; SDValue FIN = DAG . getFrameIndex ( FI


<s> int i , nunits = GET_MODE_NUNITS ( mode ) ; if ( GET_CODE ( op ) != CONST_VECTOR || nunits != CONST_VECTOR_NUNITS ( op ) ) return false ; for ( i = <NUM_LIT> ; i < nunits ; i += <NUM_LIT> ) if ( CONST_VECTOR_ELT ( op , i ) != CONST_VECTOR_ELT (


<s> if ( InstMaskEnd == <NUM_LIT> - RLAmt ) { SDValue Ops [ ] = { ExtendToInt64 ( Base , dl ) , ExtendToInt64 ( V , dl ) , getI32Imm ( RLAmt , dl ) , getI32Imm ( InstMaskStart , dl ) } ; return SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , Ops ) , <NUM_LIT> ) ; } if ( InstCnt ) * InstCnt += <NUM_LIT> ; unsigned RLAmt2 = MaskStart ; unsigned RLAmt1 = ( <NUM_LIT> + RLAmt - RLAmt2 )


<s> SDValue Src = Op . getOperand ( <NUM_LIT> ) ; unsigned Tmp = DAG . ComputeNumSignBits ( Src , Depth + <NUM_LIT> ) ; APInt ShiftVal = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getAPIntValue ( ) ; ShiftVal += Tmp ; return ShiftVal . uge ( VTBits ) ? VTBits : ShiftVal


<s> SDLoc dl ( N ) ; SDValue N0 = N -> getOperand ( <NUM_LIT> ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( N0 . getOpcode ( ) == <STR_LIT> && N0 . hasOneUse ( ) && N0 . getOperand ( <NUM_LIT> ) . hasOneUse ( ) ) { SDValue N00 = N0 . getOperand ( <NUM_LIT> ) ; if ( N00 . getOpcode ( ) == <STR_LIT> ) { if ( ! isOneConstant ( N0 . getOperand ( <NUM_LIT> ) ) ) return SDValue ( ) ; return DAG . getNode ( <STR_LIT> , dl , VT , DAG . getNode ( <STR_LIT> , dl , VT , N00 . getOperand ( <NUM_LIT> ) , N00 . getOperand ( <NUM_LIT> ) ) , DAG . getConstant ( <NUM_LIT> , dl , VT ) ) ; } } if ( N0 . getOpcode ( ) == <STR_LIT> && N0 . hasOneUse ( ) && N0 . getOperand ( <NUM_LIT> ) . hasOneUse ( ) ) { SDValue N00 = N0 . getOperand ( <NUM_LIT>


<s> std :: string * SymNamePtr = nvTM . getManagedStrPool ( ) -> getManagedString ( Sym ) ; MCOp = GetSymbolRef ( OutContext . getOrCreateSymbol ( StringRef (


<s> bool <ISA_LIT>FastISel :: SelectIToFP ( const Instruction * I , bool IsSigned ) { MVT DstVT ; Type * DstTy = I -> getType ( ) ; if ( ! isTypeLegal ( DstTy , DstVT ) ) return false ; if ( DstVT != <STR_LIT> && DstVT != <STR_LIT> ) return false ; Value * Src = I -> getOperand ( <NUM_LIT> ) ; EVT SrcEVT = TLI . getValueType ( Src -> getType ( ) , true ) ; if ( ! SrcEVT . isSimple ( ) ) return false ; MVT SrcVT = SrcEVT . getSimpleVT ( ) ; if ( SrcVT != <STR_LIT> && SrcVT != <STR_LIT> && SrcVT != <STR_LIT> && SrcVT != <STR_LIT> ) return false ; unsigned SrcReg = getRegForValue ( Src ) ; if ( SrcReg == <NUM_LIT> ) return false ; if ( ! IsSigned && ! <ISA_LIT>SubTarget . hasFPCVT ( ) ) return false ; if ( DstVT == <STR_LIT> && ! <ISA_LIT>SubTarget . hasFPCVT ( ) ) return false ; if ( SrcVT == <STR_LIT> || SrcVT == <STR_LIT> ) { unsigned TmpReg = createResultReg ( & <STR_LIT> ) ; if ( ! <ISA_LIT>EmitIntExt ( SrcVT , SrcReg , <STR_LIT> , TmpReg , ! IsSigned ) ) return false ; SrcVT = <STR_LIT> ; SrcReg = TmpReg ; } unsigned FPReg = <ISA_LIT>MoveToFPReg ( SrcVT , SrcReg , IsSigned ) ; if ( FPReg == <NUM_LIT> ) return false ; const TargetRegisterClass * RC = & <STR_LIT> ; unsigned DestReg = createResultReg ( RC )


<s> } if ( RegName . size ( ) > RegNumIndex ) { if ( RegName . substr ( RegNumIndex ) . getAsInteger ( <NUM_LIT> , RegNum ) ) return false ; Parser . Lex ( ) ; RegWidth = <NUM_LIT> ; } else { Parser . Lex ( ) ; int64_t RegLo , RegHi ; if ( getLexer ( ) . isNot ( AsmToken :: LBrac ) ) return false ; Parser . Lex ( ) ; if ( getParser ( ) . parseAbsoluteExpression ( RegLo ) ) return false ; const bool isRBrace = getLexer ( ) . is ( AsmToken :: RBrac ) ; if ( ! isRBrace && getLexer ( ) . isNot ( AsmToken :: Colon ) ) return false ; Parser . Lex ( ) ; if ( isRBrace ) { RegHi = RegLo ; } else { if ( getParser ( ) . parseAbsoluteExpression ( RegHi ) ) return false ; if ( getLexer ( ) . isNot ( AsmToken :: RBrac ) ) return false ; Parser . Lex ( ) ; } RegNum = ( unsigned ) RegLo ; RegWidth = ( RegHi - RegLo ) + <NUM_LIT> ; } } } else if ( getLexer ( ) . is ( AsmToken :: LBrac ) ) { Parser . Lex ( ) ; if ( ! Parse<ISA_LIT>Register ( RegKind , Reg , RegNum , RegWidth , nullptr ) ) return false ; if ( RegWidth != <NUM_LIT> ) return false ; RegisterKind RegKind1 ; unsigned Reg1 , RegNum1 , RegWidth1 ; do { if ( getLexer ( ) . is ( AsmToken :: Comma ) ) { Parser . Lex ( ) ; } else if ( getLexer ( ) . is ( AsmToken :: RBrac ) ) { Parser . Lex ( ) ; break ; } else if ( Parse<ISA_LIT>Register ( RegKind1 , Reg1 , RegNum1 , RegWidth1 , nullptr ) ) { if ( RegWidth1 != <NUM_LIT> ) { return false ; } if ( RegKind1 != RegKind ) { return false ; } if ( ! AddNextRegisterToList ( Reg , RegWidth , RegKind1 , Reg1 , RegNum1 ) ) { return false ; } } else { return false ; } } while ( true ) ; } else { return false ; } switch ( RegKind ) { case IS_SPECIAL : RegNum = <NUM_LIT> ; RegWidth = <NUM_LIT> ; break ; case IS_VGPR : case IS_SGPR : case


<s> StringRef getPassName ( ) const override { return <ISA_LIT>_MERGE_BASE_OFFSET_NAME


<s> static int getIDWithAttrMask ( uint16_t * instructionID , struct InternalInstruction * insn , uint16_t attrMask ) { bool hasModRMExtension ; InstructionContext instructionClass = contextForAttrs ( attrMask ) ; hasModRMExtension = modRMRequired ( insn -> opcodeType , instructionClass , insn -> opcode ) ; if ( hasModRMExtension ) { if ( readModRM ( insn ) ) return - <NUM_LIT> ; * instructionID = decode ( insn -> opcodeType , instructionClass , insn -> opcode , insn -> modRM ) ; } else { * instructionID = decode ( insn -> opcodeType , instructionClass


<s> if ( TARGET_SVE && known_eq ( nbytes , BYTES_PER_SVE_VECTOR ) ) { unsigned int elem_nbytes = vector_element_size ( nbytes , nunits ) ; machine_mode pred_mode


<s> int mask_low_and_shift_len ( machine_mode mode , rtx mask , rtx shift ) { HOST_WIDE_INT shval ; shval = INTVAL ( shift ) & ( GET_MODE_BITSIZE ( mode )


<s> const MCBinaryExpr * BinaryExpr = dyn_cast < MCBinaryExpr > ( getImm ( ) ) ; assert ( dyn_cast < <ISA_LIT>MCExpr > ( BinaryExpr -> getLHS ( ) ) && dyn_cast < <ISA_LIT>MCExpr > ( BinaryExpr -> getLHS ( ) ) -> getKind ( ) == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_ABS_HI ) ; Inst . addOperand ( MCOperand :: createExpr ( getImm ( ) ) ) ; } else assert ( false &&


<s> if ( DEFAULT_ABI == ABI_ELFv2 && AGGREGATE_TYPE_P ( type ) && ( unsigned HOST_WIDE_INT ) int_size_in_bytes ( type ) <= <NUM_LIT> ) return false ; if ( AGGREGATE_TYPE_P ( type ) && ( aix_struct_return || ( unsigned HOST_WIDE_INT ) int_size_in_bytes ( type ) > <NUM_LIT> ) ) return true ; if ( TARGET_32BIT && ! TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE ( TYPE_MODE ( type ) ) ) return false ; if ( TREE_CODE ( type ) == VECTOR_TYPE && int_size_in_bytes ( type ) > ( TARGET_ALTIVEC_ABI ? <NUM_LIT> : <NUM_LIT> ) ) { static bool warned_for_return_big_vectors = false ; if ( ! warned_for_return_big_vectors ) { warning ( <NUM_LIT> , <STR_LIT>


<s> const MCInstrDesc & Desc = MII . get ( MI -> getOpcode ( ) ) ; uint64_t TSFlags = Desc . TSFlags ; if ( CommentStream ) HasCustomInstComment = EmitAny<ISA_LIT>InstComments ( MI , * CommentStream , getRegisterName ) ; if ( TSFlags & <STR_LIT> ) OS << <STR_LIT> ; if ( MI -> getOpcode ( ) == <STR_LIT> && ( STI . getFeatureBits ( ) [ <STR_LIT>


<s> bool IsRAAndRetAddrIsTaken = ( Reg == <STR_LIT> || Reg == <STR_LIT> ) && MF -> getFrameInfo ( ) -> isReturnAddressTaken ( ) ; if ( ! IsRAAndRetAddrIsTaken ) EntryBlock -> addLiveIn ( Reg ) ; bool IsKill = ! IsRAAndRetAddrIsTaken ; const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ; TII . storeRegToStackSlot ( * EntryBlock , MI , Reg , IsKill ,

CSI [ i ] . getFrameIdx ( ) , RC , TRI ) ;


<s> static void ready_reorder ( rtx * ready , int nready ) { SCHED_REORDER ( ready , nready


<s> unsigned swapCPClass ( unsigned Class ) const { return ( ( Class & <NUM_LIT> ) << <NUM_LIT> ) | ( ( Class &

<NUM_LIT> ) >> <NUM_LIT> ) | ( Class & <NUM_LIT> ) ;


<s> return isRegSeqTemplate < <STR_LIT> , <STR_LIT>


<s> } switch ( Opcode ) { default : break ; case Instruction :: BitCast : if ( InMBB ) return <ISA_LIT>SelectCallAddress ( U -> getOperand ( <NUM_LIT> ) , AM ) ; break ; case Instruction :: IntToPtr : if ( InMBB && TLI . getValueType ( DL , U -> getOperand ( <NUM_LIT> ) -> getType ( ) ) == TLI . getPointerTy ( DL ) ) return <ISA_LIT>SelectCallAddress ( U -> getOperand ( <NUM_LIT> ) , AM ) ; break ; case Instruction :: PtrToInt : if ( InMBB && TLI . getValueType ( DL , U -> getType ( ) ) == TLI . getPointerTy ( DL ) ) return <ISA_LIT>SelectCallAddress ( U -> getOperand ( <NUM_LIT> ) , AM ) ; break ; } if ( const GlobalValue * GV = dyn_cast < GlobalValue > ( V ) ) { if ( TM . getCodeModel ( ) != CodeModel :: Small ) return false ; if ( Subtarget -> isPICStyleRIPRel ( ) && ( AM . Base . Reg != <NUM_LIT> || AM . IndexReg != <NUM_LIT> ) ) return false ; if ( GV -> hasDLLImportStorageClass ( ) ) return false ; if ( const GlobalVariable * GVar = dyn_cast < GlobalVariable > ( GV ) ) if ( GVar -> isThreadLocal ( ) ) return false ; AM . GV = GV ; if ( Subtarget -> isPICStyleRIPRel ( ) ) { assert ( AM . Base . Reg == <NUM_LIT> && AM . IndexReg == <NUM_LIT> ) ; AM . Base . Reg = <STR_LIT> ; } else if ( Subtarget -> isPICStyleStubPIC ( ) ) { AM . GVOpFlags = <STR_LIT> ; } else if ( Subtarget -> isPICStyleGOT ( ) ) { AM . GVOpFlags = <STR_LIT> ; } return true ; } if ( ! AM . GV || !


<s> unsigned Rm = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned Rd = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; Rd |= fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ; unsigned size = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned align = <NUM_LIT> ; unsigned index = <NUM_LIT> ; unsigned inc = <NUM_LIT> ; switch ( size ) { default : return MCDisassembler :: Fail ; case <NUM_LIT> : index = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; if ( fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ) align = <NUM_LIT> ; break ; case <NUM_LIT> : index = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; if ( fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ) align = <NUM_LIT> ; if ( fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ) inc = <NUM_LIT> ; break ; case <NUM_LIT> : if ( fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ) return MCDisassembler :: Fail ; index = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; if ( fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) != <NUM_LIT> ) align = <NUM_LIT> ; if ( fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ) inc = <NUM_LIT> ; break ; } if ( Rm != <NUM_LIT> ) { if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rn , Address , Decoder ) ) ) return MCDisassembler :: Fail ; } if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rn , Address , Decoder ) ) ) return MCDisassembler :: Fail ; Inst . addOperand ( MCOperand :: CreateImm ( align ) ) ; if ( Rm != <NUM_LIT> ) { if ( Rm != <NUM_LIT> ) { if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rm , Address , Decoder ) ) ) return MCDisassembler :: Fail ; } else Inst . addOperand ( MCOperand :: CreateReg ( <NUM_LIT> ) ) ; } if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , Rd


<s> static SDValue LowerVectorFP_TO_INT ( SDValue Op , SelectionDAG & DAG ) { assert ( Op . getValueType ( ) .

getVectorElementType ( ) == <STR_LIT> && <STR_LIT> ) ;


<s> int i ; for ( i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) sh_media_FVSUB_S ( & g [ i ] , & h [ i ] , & f [ i ] ) ; sh_media_FVSUB_S ( & g [ <NUM_LIT> ] , & h [ <NUM_LIT> ] , &


<s> if ( Modifier && strcmp ( Modifier , <STR_LIT> ) == <NUM_LIT> ) { if ( reg == <STR_LIT> || ( ( reg == <STR_LIT> ) && ! flag ) ) { printDefaultGuard ( O , false ) ; } else { O << <STR_LIT> << ( ( flag ) ? <STR_LIT> : <STR_LIT> ) ; printRegisterName ( reg , O ) ; O << <STR_LIT> ; } } else { O << ( ( flag ) ? <STR_LIT> : <STR_LIT> ) ; if ( reg == <STR_LIT> ) { printRegisterName ( <STR_LIT> , O ) ; } else { printRegisterName ( reg , O


<s> <ISA_LIT>Subtarget :: <ISA_LIT>Subtarget ( const Triple & TT , StringRef CPU , StringRef FS , const TargetMachine & TM ) : <ISA_LIT>GenSubtargetInfo ( TT , CPU , FS ) , CPUString ( CPU )

, InstrInfo ( initializeSubtargetDependencies ( CPU , FS ) ) , TLInfo ( TM , * this ) {


<s> if ( fndecl == NULL_TREE ) return true ; if ( DECL_EXTERNAL ( fndecl ) ) return true ; c_node = cgraph_node :: get ( fndecl ) ; c_node = c_node -> ultimate_alias_target ( ) ; return ! c_node -> only_called_directly_p ( ) ; } return false


<s> case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : case <NUM_LIT> : O << <STR_LIT> ; return ; } } if ( ! SpecRegRBit && ( Mask == <NUM_LIT> || Mask == <NUM_LIT> || Mask == <NUM_LIT> ) ) { O << <STR_LIT> ; switch ( Mask ) { default : llvm_unreachable ( <STR_LIT> ) ; case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : O << <STR_LIT> ; return ; } } if ( SpecRegRBit ) O << <STR_LIT> ; else O << <STR_LIT> ; if ( Mask ) { O << '_' ; if ( Mask & <NUM_LIT> ) O


<s> if ( Inst -> hasAtomicLoad ( ) && isAcquireOrStronger ( Ord ) ) { if ( isa < LoadInst > ( Inst ) && Subtarget . is<ISA_LIT>64 ( ) ) return Builder . CreateCall ( <STR_LIT> ( Builder . GetInsertBlock ( ) -> getParent ( ) ->

getParent ( ) , <STR_LIT> , { Inst -> getType ( ) } ) , { Inst } ) ;


<s> return StringSwitch < <STR_LIT> > ( CC ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Cases ( <STR_LIT> , <STR_LIT> , <STR_LIT> ) . Cases ( <STR_LIT> , <STR_LIT> , <STR_LIT> ) . Cases ( <STR_LIT> , <STR_LIT> , <STR_LIT> ) . Cases ( <STR_LIT> , <STR_LIT> , <STR_LIT> ) . Cases ( <STR_LIT> , <STR_LIT> , <STR_LIT> ) . Cases ( <STR_LIT> , <STR_LIT> , <STR_LIT> ) . Case

( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Cases ( <STR_LIT> , <STR_LIT> , <STR_LIT> ) . Cases ( <STR_LIT> , <STR_LIT> , <STR_LIT> ) . Cases ( <STR_LIT> , <STR_LIT> , <STR_LIT> ) . Cases ( <STR_LIT> , <STR_LIT> , <STR_LIT> ) . Cases ( <STR_LIT> , <STR_LIT> , <STR_LIT> ) . Cases ( <STR_LIT> , <STR_LIT> , <STR_LIT> ) . Default ( <STR_LIT> ) ;


<s> DenseMap < unsigned , std :: pair < unsigned , unsigned >> RegRewriteTable ; for ( MachineBasicBlock :: iterator MIIt = MIItBegin ; MIIt != MIItEnd ; MIIt = skipDebugInstructionsForward ( ++ MIIt , MIItEnd ) ) { unsigned DestReg = MIIt -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned TrueReg = MIIt -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned FalseReg = MIIt -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( MIIt -> getOperand ( <NUM_LIT> ) . getImm ( ) == ( CCValid ^ CCMask ) ) std :: swap ( TrueReg , FalseReg ) ; if ( RegRewriteTable . find ( TrueReg ) != RegRewriteTable . end ( ) ) TrueReg = RegRewriteTable [ TrueReg ] . first ; if ( RegRewriteTable . find ( FalseReg ) != RegRewriteTable . end ( ) ) FalseReg = RegRewriteTable [ FalseReg ]


<s> Offset = AddrData . Offset ; Register SRDPtr ; if ( N2 ) { if ( RBI . getRegBank ( N2 , * MRI , TRI ) -> getID ( ) == <STR_LIT> ) { assert ( N3 ) ; if ( RBI . getRegBank ( N3 , * MRI , TRI ) -> getID ( ) == <STR_LIT> ) { VAddr = N0 ; } else { SRDPtr = N3 ; VAddr = N2 ; } } else { SRDPtr =


<s> return ! MF . getTarget ( ) . getMCAsmInfo ( ) -> usesWindowsCFI ( ) ||


<s> unsigned Shift = ShiftedImm . ShiftAmount ; Expr = ShiftedImm . Val ; if ( Shift != <NUM_LIT> && Shift != <NUM_LIT> ) return false ; } else Expr = getImm ( ) ; const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( Expr ) ; return CE != nullptr && CE -> getValue ( ) < <NUM_LIT> && - CE


<s> if ( mode == SImode && inner_mode == SFmode ) { emit_insn ( gen_movsi_from_sf ( dest , inner_source ) ) ; return true ; } if ( mode == SFmode && inner_mode == SImode ) { emit_insn ( gen_movsf_from_si ( dest , inner_source )


<s> bool IsN64 = Subtarget . isABI_N64 ( ) ; return TFI -> hasFP ( MF ) ? ( IsN64 ? <STR_LIT> : <STR_LIT> ) : ( IsN64 ? <STR_LIT> : <STR_LIT>


<s> assert ( XLenVT == N . getOperand ( <NUM_LIT> ) . getSimpleValueType ( ) && <STR_LIT> ) ; auto EltVT = N . getValueType ( ) . getVectorElementType ( ) ; if ( EltVT . bitsLT ( XLenVT ) ) { SplatImm = SignExtend64 ( SplatImm , EltVT . getSizeInBits ( ) ) ; } if ( ! isInt < <NUM_LIT> > ( SplatImm ) ) return false ; SplatVal = CurDAG -> getTargetConstant ( SplatImm , SDLoc


<s> if ( VT . getSizeInBits ( ) >= RegisterVT . getSizeInBits ( ) ) return CCValAssign :: LocInfo :: Full ; if ( Flags . isSExt ( ) ) return CCValAssign :: LocInfo :: SExt ; if ( Flags . isZExt ( ) ) return CCValAssign


<s> Inst . addOperand ( MCOperand :: createExpr ( getImm ( ) ) ) ; } else if ( isa < MCBinaryExpr > ( getImm ( ) ) ) { const MCBinaryExpr * BinaryExpr = dyn_cast < MCBinaryExpr > ( getImm ( ) ) ; assert ( isa < <ISA_LIT>MCExpr > ( BinaryExpr -> getLHS ( ) ) && cast < <ISA_LIT>MCExpr > ( BinaryExpr -> getLHS ( ) ) -> getKind ( ) ==


<s> initialize_aarch64_code_model ( opts ) ; initialize_aarch64_tls_size ( opts ) ; int queue_depth = <NUM_LIT> ; switch ( aarch64_tune_params . autoprefetcher_model ) { case tune_params :: AUTOPREFETCHER_OFF : queue_depth = - <NUM_LIT> ; break ; case tune_params :: AUTOPREFETCHER_WEAK : queue_depth = <NUM_LIT> ; break ; case tune_params :: AUTOPREFETCHER_STRONG : queue_depth = max_insn_queue_index + <NUM_LIT> ; break ; default : gcc_unreachable ( ) ; } maybe_set_param_value ( PARAM_SCHED_AUTOPREF_QUEUE_DEPTH , queue_depth , opts ->


<s> if ( MoveF64FrameIndex == - <NUM_LIT> ) MoveF64FrameIndex = MF . getFrameInfo ( ) . CreateStackObject ( <NUM_LIT> , <NUM_LIT> , false ) ; return MoveF64FrameIndex


<s> if ( ! MFI . isDeadObjectIndex ( I ) && MFI . getStackID ( I ) == TargetStackID :: SGPRSpill && ( ( FramePointerSaveIndex && I != FramePointerSaveIndex ) || ( BasePointerSaveIndex && I != BasePointerSaveIndex ) ) ) { return false


<s> for ( unsigned MaybeReg : AvailableRegs ) { if ( MaybeReg ) { AvailableReg = MaybeReg ; break ; } } if ( ! AvailableReg ) report_fatal_error ( <STR_LIT> <STR_LIT> ) ; const char * Symbol = getIndirectThunkSymbol ( Subtarget , AvailableReg ) ; BuildMI ( * BB , MI , DL , TII -> get ( TargetOpcode :: COPY ) , AvailableReg ) . addReg ( CalleeVReg ) ; MI . getOperand ( <NUM_LIT> ) . ChangeToES ( Symbol ) ; MI . setDesc ( TII -> get ( Opc ) ) ; MachineInstrBuilder ( * BB -> getParent ( ) , & MI ) . addReg ( AvailableReg , RegState :: Implicit | RegState :: Kill ) ; return BB


<s> bool <ISA_LIT>TargetLowering :: isLegalAddressingMode ( const DataLayout & DL , const AddrMode & AM , Type * Ty , unsigned AS , Instruction * I ) const { return AM . Scale ==


<s> return ( __m64 ) __builtin_ia32_pfmul ( ( __v2sf ) __A , (


<s> inline static bool isMinSize ( const


<s> return new <ISA_LIT>FastISel ( FuncInfo


<s> for ( unsigned j = <NUM_LIT> , NumOps = I -> getNumOperands ( ) ; j != NumOps ; ++ j ) { MachineOperand & MO = I -> getOperand ( j ) ; if ( ! MO . isReg ( ) ) continue ; unsigned Reg = MO . getReg ( ) ; if ( MO . isDef ( ) && TRI -> regsOverlap ( Reg , Base ) ) return false ; if ( Reg != Base && ! MemRegs . count ( Reg ) ) AddedRegPressure . insert (


<s> bytes = ( mode == BLKmode ) ? int_size_in_bytes ( type ) : GET_MODE_SIZE ( mode ) ; words = ( bytes + UNITS_PER_WORD - <NUM_LIT> ) / UNITS_PER_WORD ; cum -> words += words ; cum -> nregs -= words ; if ( cum -> nregs <= <NUM_LIT> ) { cum -> nregs =


<s> <ISA_LIT>TargetObjectFile & TLOF = ( <ISA_LIT>TargetObjectFile & ) getObjFileLowering ( ) ; if ( TLOF . IsGlobalInSmallSection ( GV , getTargetMachine ( ) ) ) { SDValue GA = DAG . getTargetGlobalAddress ( GV , dl , <STR_LIT> , <NUM_LIT> , <STR_LIT> ) ; SDValue GPRelNode = DAG . getNode ( <STR_LIT> , dl , VTs , & GA , <NUM_LIT> ) ; SDValue GOT = DAG . getGLOBAL_OFFSET_TABLE ( <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , GOT , GPRelNode ) ; } SDValue GA = DAG . getTargetGlobalAddress ( GV , dl , <STR_LIT> , <NUM_LIT> , <STR_LIT> ) ; SDValue HiPart = DAG . getNode ( <STR_LIT> , dl , VTs , & GA , <NUM_LIT> ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , GA ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , HiPart , Lo ) ; } else { SDValue GA = DAG . getTargetGlobalAddress ( GV , dl , <STR_LIT> , <NUM_LIT> , <STR_LIT> ) ; SDValue ResNode = DAG . getLoad ( <STR_LIT> , dl , DAG . getEntryNode ( ) , GA , NULL , <NUM_LIT> ,


<s> if ( isTypeLegal ( Ty , VT ) ) return true ; if ( VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> ) { return


<s> static bool spu_vector_alignment_reachable ( const_tree type ATTRIBUTE_UNUSED , bool is_packed ) { if ( is_packed ) return


<s> void <ISA_LIT>AsmParser :: cvtMIMGAtomic ( MCInst & Inst , const OperandVector & Operands ) { cvtMIMG ( Inst , Operands , true


<s> static SDValue ConvertBooleanCarryToCarryFlag ( SDValue BoolCarry , SelectionDAG & DAG ) { SDLoc DL ( BoolCarry ) ; EVT CarryVT = BoolCarry .


<s> if ( AI -> use_empty ( ) ) return AtomicExpansionKind :: None ; auto * C1 = dyn_cast < ConstantInt > ( AI -> getValOperand ( ) ) ; Instruction * I = AI -> user_back ( ) ; if ( ! C1 || ! AI -> hasOneUse ( ) || I -> getOpcode ( ) != Instruction :: And || AI -> getParent ( ) != I -> getParent ( ) ) return AtomicExpansionKind :: CmpXChg ; auto * C2 = dyn_cast < ConstantInt > ( I -> getOperand ( <NUM_LIT> ) ) ; unsigned Bits = AI -> getType ( ) -> getPrimitiveSizeInBits ( ) ; if ( ! C2 || Bits == <NUM_LIT> || ! isPowerOf2_64 ( C2

-> getZExtValue ( ) ) ) return AtomicExpansionKind :: CmpXChg ;


<s> if ( GET_CODE ( reg1 ) != REG ) return <NUM_LIT> ; const int regno1 = REGNO ( reg1 ) ; if ( GET_CODE ( reg2 ) == SUBREG ) reg2 = SUBREG_REG ( reg2 ) ; if ( GET_CODE ( reg2 ) != REG ) return <NUM_LIT> ; const int regno2 = REGNO ( reg2 ) ; if ( SPARC_INT_REG_P ( regno1 ) && SPARC_INT_REG_P ( regno2 ) ) return <NUM_LIT> ; if ( TARGET_VIS3 ) { if ( ( SPARC_INT_REG_P ( regno1 ) && SPARC_FP_REG_P ( regno2 ) ) || ( SPARC_FP_REG_P ( regno1 ) && SPARC_INT_REG_P ( regno2 ) ) ) return <NUM_LIT> ; } return


<s> MachineInstr * MI = SU -> getInstr ( ) ; if ( MI -> isDebugInstr ( ) ) return NoHazard ; unsigned Opcode = MI -> getOpcode ( ) ; bool isFirst , isSingle , isCracked , isLoad , isStore ; <STR_LIT> InstrType = GetInstrType ( Opcode , isFirst , isSingle , isCracked , isLoad , isStore ) ; if ( InstrType == <STR_LIT> ) return NoHazard ; if ( NumIssued != <NUM_LIT> && (


<s> Sew . ashrInPlace ( <NUM_LIT> ) ; unsigned SewLog2 = Sew . logBase2 ( ) ; unsigned LmulLog2 = Lmul . logBase2 ( ) ; Op -> VType . Sew = static_cast < VSEW > ( SewLog2 ) ; if ( Fractional ) { unsigned Flmul = <NUM_LIT> - LmulLog2 ; Op -> VType . Lmul = static_cast < VLMUL > ( Flmul ) ; Op -> VType . Encoding = ( ( Flmul & <NUM_LIT> ) << <NUM_LIT> ) | ( ( SewLog2 & <NUM_LIT>

) << <NUM_LIT> ) | ( Flmul & <NUM_LIT> ) ;


<s> <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } ; static const MCPhysReg CalleeSavedRegsIntrFP [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } ; if ( TFI -> hasFP ( * MF ) ) return ( F -> getCallingConv ( )

== CallingConv :: <ISA_LIT>_INTR ? CalleeSavedRegsIntrFP : CalleeSavedRegsFP ) ;


<s> static HOST_WIDE_INT aarch64_constant_alignment ( const_tree exp , HOST_WIDE_INT align ) { if ( TREE_CODE ( exp ) == STRING_CST && ! optimize_size ) return MAX ( align , BITS_PER_WORD ) ; return align


<s> case <STR_LIT> : case <STR_LIT> : PointerType * PtrTy = cast < PointerType > ( I . getArgOperand ( <NUM_LIT> ) -> getType ( ) ) ; Info . opc = <STR_LIT> ; Info . memVT = <STR_LIT> ( PtrTy -> getElementType ( ) ) ; Info . ptrVal = I . getArgOperand


<s> void <ISA_LIT>Subtarget :: initializeEnvironment ( ) { HasV4TOps = false ; HasV5TOps = false ; HasV5TEOps = false ; HasV6Ops = false ; HasV6MOps = false ; HasV6KOps = false ; HasV6T2Ops = false ; HasV7Ops = false ; HasV8Ops = false ; HasV8_1aOps = false ; HasVFPv2 = false ; HasVFPv3 = false ; HasVFPv4 = false ; HasFP<ISA_LIT>v8 = false ; HasNEON = false ; UseNEONForSinglePrecisionFP = false ; UseMulOps = UseFusedMulOps ; SlowFPVMLx = false ; HasVMLxForwarding = false ; SlowFPBrcc = false ; InThumbMode = false ; UseSoftFloat = false ; HasThumb2 = false ; No<ISA_LIT> = false ; ReserveR9 = false ; NoMovt = false ; SupportsTailCall = false ; HasFP16 = false ; HasD16 = false ; HasHardwareDivide = false ; HasHardwareDivideIn<ISA_LIT> = false ; HasT2ExtractPack =


<s> unsigned getNumFixupKinds ( ) const override {

return AMDGPU :: NumTargetFixupKinds ; }


<s> SDValue Entry = Op . getOperand ( <NUM_LIT> ) ; int JTI = cast < JumpTableSDNode > ( JT . getNode ( ) ) -> getIndex ( ) ; if ( DAG . getMachineFunction ( ) . getFunction ( ) . hasFnAttribute ( <STR_LIT> ) || Subtarget -> getTargetTriple ( ) . getArchName ( ) == <STR_LIT> ) { if ( getTargetMachine ( ) . getCodeModel ( ) != CodeModel :: Small ) report_fatal_error ( <STR_LIT> ) ; SDValue Chain = DAG . getCopyToReg ( DAG . getEntryNode ( ) , DL , <STR_LIT> , Entry , SDValue ( ) ) ; SDNode * B = DAG . getMachineNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getTargetJumpTable ( JTI , <STR_LIT> ) , Chain . getValue ( <NUM_LIT> ) , Chain . getValue ( <NUM_LIT> ) ) ; return SDValue ( B , <NUM_LIT> ) ; } SDNode * Dest = DAG . getMachineNode ( <STR_LIT> , DL , <STR_LIT> , <STR_LIT> , JT , Entry , DAG . getTargetJumpTable ( JTI


<s> return ( MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) ==


<s> unsigned at = CountLeadingZeros_64 ( x ) ; uint64_t complow = <NUM_LIT> << ( <NUM_LIT> - at ) ; uint64_t comphigh = <NUM_LIT> << ( <NUM_LIT> -


<s> if ( Subtarget . hasAltivec ( ) ) getMaxByValAlign ( Ty , Alignment , Align


<s> void rs6000_secondary_reload_gpr ( rtx reg , rtx mem , rtx scratch , bool store_p ) { int regno = true_regnum ( reg ) ; enum reg_class rclass ; rtx addr ; rtx scratch_or_premodify = scratch ; if ( TARGET_DEBUG_ADDR ) { fprintf ( stderr , <STR_LIT> , store_p ? <STR_LIT> : <STR_LIT> ) ; fprintf ( stderr , <STR_LIT> ) ; debug_rtx ( reg ) ; fprintf ( stderr , <STR_LIT> ) ; debug_rtx ( mem ) ; fprintf ( stderr , <STR_LIT> ) ; debug_rtx ( scratch ) ; } gcc_assert ( regno >= <NUM_LIT> && HARD_REGISTER_NUM_P ( regno ) ) ; gcc_assert ( MEM_P ( mem )


<s> SDLoc DL ( N ) ; SDValue Op0 = N -> getOperand ( <NUM_LIT> ) ; SDValue Op1 = N -> getOperand ( <NUM_LIT> ) ; EVT ResVT = N -> getValueType ( <NUM_LIT> ) ; if ( Op0 . getOpcode ( ) == <STR_LIT> ) { if ( Op0 . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) { SDValue X = Op0 . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ; return DAG . getNode ( <STR_LIT> , DL , ResVT , X , Op1 ) ; } } if ( Op1 . getOpcode ( ) == <STR_LIT> ) { if ( Op1 . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) { SDValue Z = Op1 . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ; return DAG . getNode ( <STR_LIT> , DL , ResVT ,


<s> TargetPassConfig * <ISA_LIT>TargetMachine :: createPassConfig ( PassManagerBase & PM ) { return new TargetPassConfig ( * this


<s> while ( ! MI . getOperand ( FIOperandNum ) . isFI ( ) ) { ++ FIOperandNum ; assert ( FIOperandNum < MI . getNumOperands ( ) && <STR_LIT> ) ; } MI . getOperand ( FIOperandNum ) . ChangeToRegister ( BaseReg , false ) ; unsigned OffsetOperandNo = getOffsetONFromFION ( MI , FIOperandNum ) ; Offset += MI . getOperand ( OffsetOperandNo ) . getImm ( ) ; MI . getOperand ( OffsetOperandNo ) . ChangeToImmediate ( Offset ) ; MachineBasicBlock & MBB = * MI . getParent ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; const <ISA_LIT>Subtarget & Subtarget = MF . getSubtarget


<s> unsigned FirstOpc = FirstLdSt . getOpcode ( ) ; unsigned SecondOpc = SecondLdSt . getOpcode ( ) ; if ( ! canPairLdStOpc ( FirstOpc , SecondOpc ) ) return false ; if ( ! isCandidateToMergeOrPair ( FirstLdSt ) || ! isCandidateToMergeOrPair ( SecondLdSt ) ) return false ; int64_t Offset1 = FirstLdSt . getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( isUnscaledLdSt ( FirstOpc ) && ! scaleOffset ( FirstOpc , Offset1 ) ) return false ; int64_t Offset2 = SecondLdSt . getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( isUnscaledLdSt ( SecondOpc ) && ! scaleOffset ( SecondOpc , Offset2 ) ) return false ; if ( Offset1 > <NUM_LIT> || Offset1 < - <NUM_LIT> ) return false ; assert ( Offset1 <= Offset2


<s> void DecodeSubVectorBroadcast ( MVT DstVT , MVT SrcVT , SmallVectorImpl < int > & ShuffleMask ) { assert ( SrcVT . getScalarType ( ) == DstVT . getScalarType ( ) && <STR_LIT> ) ; unsigned NumElts = SrcVT . getVectorNumElements (


<s> bool SelectAddrIdxX16 ( SDValue N , SDValue & Base ,


<s> bool ix86_target_stack_probe ( void ) { if ( flag_stack_check == STATIC_BUILTIN_STACK_CHECK ) return false ; return TARGET_STACK_PROBE


<s> assert ( N -> getOpcode ( ) == <STR_LIT> && <STR_LIT> ) ; N = N . getOperand ( <NUM_LIT> ) ; if ( N -> getOpcode ( ) != <STR_LIT> && N -> getOpcode ( ) != <STR_LIT> && N -> getOpcode ( ) != <STR_LIT> &&

N -> getOpcode ( ) != <STR_LIT> && N -> getOpcode ( ) != <STR_LIT> && N -> getOpcode ( ) != <STR_LIT> ) return false ;


<s> if ( RegName [ <NUM_LIT> ] == 'q' ) { std :: string RN ( RegName ) ; RN [ <NUM_LIT> ] = 'f' ; OS <<


<s> for ( unsigned op = <NUM_LIT> , e = I -> getNumOperands ( ) ; op != e ; ++ op ) if ( I -> getOperand ( op ) . isCPI ( ) ) { unsigned Bits = <NUM_LIT> ; unsigned Scale = <NUM_LIT> ; bool NegOk = false ; bool IsSoImm = false ; switch ( Opc ) { default : llvm_unreachable ( <STR_LIT> ) ; break ; case <STR_LIT> : Bits = <NUM_LIT> ; Scale = <NUM_LIT> ; NegOk = true ; IsSoImm = true ; break ; case <STR_LIT> : Bits = <NUM_LIT> ; NegOk = true ; break ; case <STR_LIT> : Bits = <NUM_LIT> ; Scale = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Bits = <NUM_LIT> ; NegOk = true ; break ; case <STR_LIT> : case <STR_LIT> : Bits = <NUM_LIT> ; Scale = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : Bits = <NUM_LIT> ; Scale = <NUM_LIT> ; NegOk = true ; break ; } unsigned CPI = I -> getOperand ( op ) . getIndex ( ) ; MachineInstr * CPEMI = CPEMIs [ CPI ] ; unsigned MaxOffs = ( ( <NUM_LIT> << Bits ) - <NUM_LIT> ) * Scale ; CPUsers . push_back ( CPUser ( I , CPEMI , MaxOffs , NegOk , IsSoImm ) ) ; CPEntry * CPE = findConstPoolEntry ( CPI , CPEMI ) ; assert ( CPE && <STR_LIT> ) ; CPE -> RefCount ++ ; break ; } } if ( isThumb && ! MBB . empty ( ) && MBB . begin ( ) -> getOpcode ( ) == <STR_LIT> && ( ( Offset % <NUM_LIT> ) != <NUM_LIT> || HasInlineAsm


<s> addRegisterClass ( <STR_LIT> , & AMDGPU :: VReg_64RegClass ) ; addRegisterClass ( <STR_LIT> , & AMDGPU :: VReg_64RegClass ) ; addRegisterClass ( <STR_LIT> , & AMDGPU :: VReg_128RegClass ) ; addRegisterClass ( <STR_LIT> , & AMDGPU :: VReg_128RegClass ) ; addRegisterClass ( <STR_LIT> , & AMDGPU :: VReg_256RegClass ) ; addRegisterClass ( <STR_LIT> , & AMDGPU :: VReg_256RegClass ) ; addRegisterClass ( <STR_LIT> , & AMDGPU :: VReg_512RegClass ) ; addRegisterClass ( <STR_LIT> , & AMDGPU :: VReg_512RegClass ) ; computeRegisterProperties ( ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT>


<s> void <ISA_LIT>RegisterInfo :: lowerVRSAVESpilling ( MachineBasicBlock :: iterator II , unsigned FrameIndex ) const { MachineInstr & MI = * II ; MachineBasicBlock & MBB = * MI . getParent ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; const TargetInstrInfo & TII = * Subtarget . getInstrInfo ( ) ; DebugLoc dl = MI . getDebugLoc ( ) ; const TargetRegisterClass * GPRC =


<s> unsigned Opcode = TII -> getLoadAndTest ( MI . getOpcode ( ) ) ; if ( ! Opcode || ! adjustCCMasksForInstr ( MI , Compare , CCUsers , Opcode ) ) return false ; auto MIB = BuildMI ( * MI . getParent ( ) , MI , MI . getDebugLoc ( ) , TII -> get ( Opcode ) ) ; for ( const auto & MO : MI . operands ( ) )


<s> return true ; case <ISA_LIT>LibFunc :: EI_ATAN : Res0 = atan ( opr0 ) ; return true ; case <ISA_LIT>LibFunc :: EI_ATANH : Res0 = ( log ( opr0 + <NUM_LIT> ) - log ( opr0 - <NUM_LIT> ) ) / <NUM_LIT> ; return true ; case <ISA_LIT>LibFunc :: EI_ATANPI : Res0 = atan ( opr0 ) / MATH_PI ; return true ; case <ISA_LIT>LibFunc :: EI_CBRT : Res0 = ( opr0 < <NUM_LIT> ) ? - pow ( - opr0 , <NUM_LIT> / <NUM_LIT> ) : pow ( opr0 , <NUM_LIT> / <NUM_LIT> ) ; return true ; case <ISA_LIT>LibFunc :: EI_COS : Res0 = cos ( opr0 ) ; return true ; case <ISA_LIT>LibFunc :: EI_COSH : Res0 = cosh ( opr0 ) ; return true ; case <ISA_LIT>LibFunc :: EI_COSPI : Res0 = cos ( MATH_PI * opr0 ) ; return true ; case <ISA_LIT>LibFunc :: EI_EXP : Res0 = exp ( opr0 ) ; return true ; case <ISA_LIT>LibFunc :: EI_EXP2 : Res0 = pow ( <NUM_LIT> , opr0 ) ; return true ; case <ISA_LIT>LibFunc :: EI_EXP10 : Res0 = pow ( <NUM_LIT> , opr0 ) ; return true ; case <ISA_LIT>LibFunc :: EI_EXPM1 : Res0 = exp ( opr0 ) - <NUM_LIT> ; return true ; case <ISA_LIT>LibFunc :: EI_LOG : Res0 = log ( opr0 ) ; return true ; case <ISA_LIT>LibFunc :: EI_LOG2 : Res0 = log ( opr0 ) / log ( <NUM_LIT> ) ; return true ; case <ISA_LIT>LibFunc :: EI_LOG10 : Res0 = log ( opr0 ) / log ( <NUM_LIT> ) ; return true ; case <ISA_LIT>LibFunc :: EI_RSQRT : Res0 = <NUM_LIT> / sqrt ( opr0 ) ; return true ; case <ISA_LIT>LibFunc :: EI_<ISA_LIT>N : Res0 = sin ( opr0 ) ; return true ; case <ISA_LIT>LibFunc :: EI_<ISA_LIT>NH : Res0 = sinh ( opr0 ) ; return true ; case <ISA_LIT>LibFunc :: EI_<ISA_LIT>NPI : Res0 = sin ( MATH_PI * opr0 ) ; return true ; case <ISA_LIT>LibFunc :: EI_SQRT : Res0 = sqrt ( opr0 ) ; return true ; case <ISA_LIT>LibFunc :: EI_TAN : Res0 = tan ( opr0 ) ; return true ; case <ISA_LIT>LibFunc :: EI_TANH : Res0 = tanh ( opr0 ) ; return true ; case <ISA_LIT>LibFunc :: EI_TANPI : Res0 = tan ( MATH_PI * opr0 ) ; return true


<s> unsigned int found_flags = initial_state ; while ( ( ntoken = strchr ( specs , separator ) ) ) { size_t token_length = ntoken - specs ; unsigned token_ops = aarch64_parse_one_option_token ( specs , token_length , flags , option_name ) ; if ( ! token_ops ) found_flags =


<s> if ( MayFoldLoad && N1 -> getOpcode ( ) == <STR_LIT> && N1 -> hasOneUse ( ) && tryFoldVecLoad ( Node , N1 . getNode ( ) , N1 . getOperand ( <NUM_LIT> ) , Tmp0 , Tmp1 , Tmp2 , Tmp3 , Tmp4 ) ) { SDValue Load = N1 . getOperand ( <NUM_LIT> ) ; SDValue Ops [ ] = { N0 , Tmp0 , Tmp1 , Tmp2 , Tmp3 , Tmp4 , Imm , Load . getOperand ( <NUM_LIT> ) } ; SDVTList VTs = CurDAG -> getVTList ( VT , <STR_LIT> , <STR_LIT> ) ; MachineSDNode * CNode = CurDAG -> getMachineNode ( MOpc , dl , VTs , Ops ) ; ReplaceUses ( Load . getValue ( <NUM_LIT> ) , SDValue ( CNode , <NUM_LIT> ) ) ; MachineSDNode :: mmo_iterator MemOp = MF -> allocateMemRefsArray ( <NUM_LIT> ) ; MemOp [ <NUM_LIT> ] = cast < LoadSDNode > ( Load ) -> getMemOperand ( ) ; CNode -> setMemRefs ( MemOp , MemOp +


<s> riscv_set_frame_expr ( riscv_frame_set ( mem


<s> bool hasBMI ( ) const { return HasBMI


<s> return MIB . addImm ( Offset ) . addReg ( Reg , getKillRegState (


<s> if ( this -> <ISA_LIT>SubTarget . is<ISA_LIT>64 ( ) ) { return <STR_LIT> ; } else


<s> Op -> Tok . Data = Str . data ( ) ; Op -> Tok . Length = Str .


<s> SDValue PopOpnd = InIdx . getOperand ( <NUM_LIT> ) ; if ( PopOpnd . getOpcode ( ) == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , DL , Op . getValueType ( ) , PopOpnd , InVec ) ; } if ( isTypeLegal ( VT ) ) return Op ; EVT IntVT = VT . changeVectorElementTypeToInteger ( ) ; SDValue SplatIdx = DAG . getNode ( <STR_LIT> , DL , IntVT , DAG . getZExtOrTrunc ( InIdx , DL , <STR_LIT> ) ) ; SDValue Zero = DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; SDValue One = DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; SDValue Seq = DAG . getNode ( <STR_LIT> , DL , IntVT , Zero , One ) ; EVT BoolVT = EVT :: getIntegerVT ( * DAG . getContext ( ) , <NUM_LIT> ) ; EVT PredVT = Seq . getValueType ( ) . changeVectorElementType ( BoolVT ) ; SDValue Pred = DAG . getNode ( <STR_LIT> , DL , PredVT , Seq , SplatIdx ,


<s> } for ( unsigned i = <NUM_LIT> , e = Shuffles . size ( ) ; i < e ; ++ i ) Shuffles [ i ] -> replaceAllUsesWith ( TransposedVectors [ Indices [ i ] ] ) ; return true ; } Type * ShuffleEltTy = ShuffleTy -> getVectorElementType ( ) ; unsigned NumSubVecElems = ShuffleTy -> getVectorNumElements ( ) / Factor ; decompose ( Shuffles [ <NUM_LIT> ] , Factor , VectorType :: get ( ShuffleEltTy , NumSubVecElems ) , DecomposedVectors ) ; switch ( NumSubVecElems ) { case <NUM_LIT> : transpose_4x4 ( DecomposedVectors , TransposedVectors ) ; break ; case <NUM_LIT> : interleave8bitStride4VF8 ( DecomposedVectors , TransposedVectors ) ; break ; case <NUM_LIT> : case


<s> int32x4_t result ; __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT> (


<s> return DAG . getBitcast ( <STR_LIT> , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , getV4<ISA_LIT>ShuffleImm8ForMask ( WidenedMask , DL , DAG ) ) ) ; } assert ( Mask [ <NUM_LIT> ] != - <NUM_LIT> && <STR_LIT> ) ; assert ( Mask [ <NUM_LIT> ] != - <NUM_LIT> && <STR_LIT> ) ; assert ( Mask [ <NUM_LIT> ] < <NUM_LIT> && <STR_LIT> ) ; assert ( Mask [ <NUM_LIT> ] >= <NUM_LIT> && <STR_LIT> ) ; if ( Subtarget . hasAVX2 ( ) ) if ( SDValue Extract = lowerShuffleOfExtractsAsVperm ( DL , V1 , V2 , Mask , DAG ) ) return Extract ; if ( SDValue Shift = lowerShuffleAsShift ( DL , <STR_LIT> , V1 , V2 , Mask , Zeroable , Subtarget , DAG ) ) return Shift ; if ( SDValue Insertion = lowerShuffleAsElementInsertion ( DL , <STR_LIT> , V1 , V2 , Mask , Zeroable , Subtarget , DAG ) ) return Insertion ; int InverseMask [ <NUM_LIT> ] = { Mask [ <NUM_LIT> ] ^ <NUM_LIT> , Mask [ <NUM_LIT> ] ^ <NUM_LIT> } ; if ( SDValue Insertion = lowerShuffleAsElementInsertion ( DL , <STR_LIT> , V2 , V1 , InverseMask , Zeroable , Subtarget , DAG ) ) return Insertion ; bool IsBlendSupported = Subtarget . hasSSE41


<s> SDValue <ISA_LIT>TargetLowering :: LowerToPredicatedOp ( SDValue Op , SelectionDAG & DAG , unsigned NewOp , bool OverrideNEON ) const { EVT VT = Op . getValueType ( ) ; SDLoc DL ( Op ) ; auto Pg = getPredicateForVector ( DAG , DL , VT ) ; if ( useSVEForFixedLengthVectorVT ( VT , OverrideNEON ) ) { EVT ContainerVT = getContainerForFixedLengthVector ( DAG , VT ) ; SmallVector < SDValue , <NUM_LIT> > Operands = { Pg } ; for ( const SDValue & V : Op -> op_values ( ) ) { if ( isa < CondCodeSDNode > ( V ) ) { Operands . push_back ( V ) ; continue ; } if ( const VTSDNode * VTNode = dyn_cast < VTSDNode > ( V ) ) { EVT VTArg = VTNode -> getVT ( ) . getVectorElementType ( ) ; EVT NewVTArg = ContainerVT . changeVectorElementType ( VTArg ) ; Operands . push_back ( DAG . getValueType ( NewVTArg ) ) ; continue ; } assert ( useSVEForFixedLengthVectorVT ( V . getValueType ( )


<s> SDValue <ISA_LIT>TargetLowering :: LowerINSERT_VECTOR_ELT ( SDValue Op , SelectionDAG & DAG ) const { MVT VT = Op . getSimpleValueType ( ) ; MVT EltVT = VT . getVectorElementType ( ) ; if ( EltVT == <STR_LIT> ) return InsertBitToMaskVector ( Op , DAG ) ; SDLoc dl ( Op ) ; SDValue N0 = Op . getOperand ( <NUM_LIT> ) ; SDValue N1 = Op . getOperand ( <NUM_LIT> ) ; SDValue N2 = Op . getOperand ( <NUM_LIT> ) ; if ( ! isa < ConstantSDNode > ( N2 ) ) return SDValue ( ) ; auto * N2C = cast < ConstantSDNode > ( N2 ) ; unsigned IdxVal = N2C -> getZExtValue ( ) ; if ( VT . is256BitVector ( ) || VT . is512BitVector ( ) ) { if ( VT . is256BitVector ( ) && IdxVal == <NUM_LIT> ) { if ( ( Subtarget -> hasAVX ( ) && ( EltVT == <STR_LIT> || EltVT == <STR_LIT> ) ) || ( Subtarget -> hasAVX2 ( ) && EltVT == <STR_LIT> ) ) { SDValue N1Vec = DAG . getNode ( <STR_LIT> , dl , VT , N1 ) ; N2 = DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ; return DAG . getNode ( <STR_LIT> , dl , VT , N0 , N1Vec , N2 ) ; } } SDValue V = Extract128BitVector ( N0 , IdxVal , DAG , dl ) ; unsigned NumEltsIn128 = <NUM_LIT> / EltVT . getSizeInBits ( ) ; unsigned IdxIn128 = IdxVal - ( IdxVal / NumEltsIn128 ) * NumEltsIn128 ; V = DAG . getNode ( <STR_LIT> , dl , V . getValueType ( ) , V , N1 , DAG . getConstant ( IdxIn128 , dl , <STR_LIT> ) ) ; return Insert128BitVector ( N0 , V , IdxVal , DAG , dl ) ; } assert ( VT . is128BitVector ( ) && <STR_LIT> ) ; if ( Subtarget -> hasSSE41 ( ) ) { if ( EltVT . getSizeInBits ( ) == <NUM_LIT> || EltVT . getSizeInBits ( ) == <NUM_LIT> ) { unsigned Opc ; if ( VT == <STR_LIT> ) { Opc =


<s> bool <ISA_LIT>SEDAGToDAGISel :: runOnMachineFunction ( MachineFunction & MF ) { Subtarget = & static_cast < const <ISA_LIT>Subtarget & > (


<s> if ( MI . isCall ( ) ) return true ; if ( ! isTargetSpecificOpcode ( MI . getOpcode ( ) ) ) return true ; return ! isSALU ( MI ) || MI .


<s> bool isSubtargetV2 ( ) const { return <ISA_LIT>ArchVersion ==


<s> static inline bool isDef32 ( const SDNode & N ) { unsigned Opc = N . getOpcode ( ) ; return Opc != <STR_LIT> && Opc != TargetOpcode :: EXTRACT_SUBREG && Opc


<s> static rtx pa_internal_arg_pointer ( void ) { if ( TARGET_64BIT ) return copy_to_reg ( virtual_incoming_args_rtx ) ; else return


<s> return ( __m128i ) __builtin_ia32_pmovsqd128_mask ( ( __v2di ) __A , ( __v4si ) _mm_undefined_si128 ( )


<s> else { fprintf ( dump_file , <STR_LIT> , INSN_UID ( BB_HEAD ( loop -> header ) ) , INSN_UID ( BB_END ( loop -> latch ) ) ) ; if ( pc_set ( BB_END ( loop -> latch ) ) == NULL_RTX ) fprintf ( dump_file , <STR_LIT> ) ; else fprintf ( dump_file , <STR_LIT> ) ; } } } else { rtx_insn * new_insn ; if ( dump_file ) fprintf ( dump_file , <STR_LIT> ) ; new_insn = emit_insn_before ( gen_osc_break ( ) , BB_END ( loop


<s> static const struct cc_conv cc_di_convs [ ] = { { NE , <STR_LIT> , <STR_LIT> } , { EQ , <STR_LIT> , <STR_LIT> } , { GE , <STR_LIT> , <STR_LIT> } , { GT , <STR_LIT> , <STR_LIT> } , { LE , <STR_LIT> , <STR_LIT> } , { LT , <STR_LIT> , <STR_LIT> } , { GTU , <STR_LIT> , <STR_LIT> } , { LEU , <STR_LIT> , <STR_LIT> } , CCEND } ; static const struct cc_type_conv cc_convs [ ] = { { CC_FUNmode , cc_fun_convs } , { CC_FPmode , cc_fp_convs } , { CC_FPEQmode , cc_fpeq_convs } , { CC_UNSmode , cc_uns_convs } , { CCmode , cc_signed_convs } , { DImode , cc_di_convs } } ; size_t i ; int j ; machine_mode mode = GET_MODE ( XEXP ( x , <NUM_LIT> ) ) ; RTX_CODE cc = GET_CODE ( x ) ; for ( i = <NUM_LIT> ; i < ARRAY_SIZE ( cc_convs ) ; i ++ ) { if ( mode == cc_convs [ i ] . cc_mode ) { for ( j = <NUM_LIT> ; cc_convs [ i ] . convs [ j ] . cc != UNKNOWN ; j ++ ) if ( cc == cc_convs [ i ] . convs [ j ] . cc ) { const char * mmix_cc = ( reversed ? cc_convs [ i ] . convs [ j ] . reversed : cc_convs [ i ] . convs [ j ] . normal ) ; if ( mmix_cc == NULL ) fatal_insn ( <STR_LIT> , x ) ; fprintf ( stream , <STR_LIT> , mmix_cc ) ; return ; } fatal_insn ( <STR_LIT> , x ) ; } } fatal_insn ( <STR_LIT>


<s> return ( __m128d ) __builtin_ia32_vfmaddsd3_mask3 ( ( __v2df ) __W , - ( __v2df )


<s> __o = __builtin_aarch64_set_qregxiv2di ( __o , ( int64x2_t ) temp . val [ <NUM_LIT> ] , <NUM_LIT> ) ; __o = __builtin_aarch64_set_qregxiv2di ( __o , ( int64x2_t ) temp . val [ <NUM_LIT> ] , <NUM_LIT> ) ; __o = __builtin_aarch64_set_qregxiv2di ( __o , ( int64x2_t ) temp . val [ <NUM_LIT> ] , <NUM_LIT> ) ; __o = __builtin_aarch64_set_qregxiv2di ( __o , ( int64x2_t ) temp


<s> static unsigned toIndex ( ID Id ) { assert ( static_cast < unsigned > ( Id ) > static_cast

< unsigned > ( <ISA_LIT>LibFunc :: EI_LAST_MANGLED ) && <STR_LIT> ) ;


<s> } for ( BasicBlock * BB : RPOT ) { int SuccState = getSuccState ( InitialStates , F , ParentBaseState , BB ) ; if ( SuccState == OverdefinedState ) continue ; FinalStates . insert ( { BB , SuccState } ) ; } for ( BasicBlock * BB : RPOT ) { auto & BBColors = BlockColors [ BB ] ; BasicBlock * FuncletEntryBB = BBColors . front ( ) ; if ( isa < CleanupPadInst > ( FuncletEntryBB -> getFirstNonPHI ( ) ) ) continue ; int PrevState = getPredState ( FinalStates , F , ParentBaseState , BB ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << BB -> getName ( ) << <STR_LIT> << PrevState << '\n' ) ; for ( Instruction & I : * BB ) { auto * Call = dyn_cast < CallBase > ( & I ) ; if ( ! Call || ! isStateStoreNeeded ( Personality , * Call ) ) continue ; int State = getStateForCall ( BlockColors , FuncInfo , * Call ) ; if ( State != PrevState ) insertStateNumberStore ( & I , State ) ; PrevState = State ; } auto EndState = FinalStates . find ( BB ) ; if ( EndState != FinalStates . end ( ) ) if ( EndState -> second != PrevState ) insertStateNumberStore ( BB -> getTerminator ( ) , EndState -> second ) ; } SmallVector < CallBase * , <NUM_LIT> > SetJmp3Calls ; for ( BasicBlock * BB : RPOT ) { for ( Instruction & I : * BB ) { auto * Call = dyn_cast < CallBase > ( & I ) ; if ( ! Call ) continue ; if ( Call -> getCalledOperand ( ) -> stripPointerCasts ( ) != SetJmp3 . getCallee ( ) -> stripPointerCasts ( ) ) continue ; SetJmp3Calls . push_back ( Call ) ; } } for ( CallBase * Call :


<s> bool <ISA_LIT>MCAsmBackend :: writeNopData ( raw_ostream & OS , uint64_t Count , const MCSubtargetInfo * STI ) const { for ( uint64_t I = <NUM_LIT> ; I != Count ; ++ I ) OS


<s> int Offset = MFI -> getObjectOffset ( FrameIndex ) ; Offset += MI . getOperand ( OffsetOperandNo ) . getImm ( ) ; if ( ! MF . getFunction ( ) -> getAttributes ( ) . hasAttribute ( AttributeSet :: FunctionIndex , Attribute :: Naked ) ) { if ( ! ( hasBasePointer ( MF ) && FrameIndex < <NUM_LIT> ) ) Offset += MFI -> getStackSize ( ) ; } assert ( OpC != <STR_LIT> && <STR_LIT> ) ; if ( ! noImmForm && isInt < <NUM_LIT> > ( Offset ) && ( ! isIXAddr || ( Offset & <NUM_LIT> ) == <NUM_LIT> ) ) { MI . getOperand ( OffsetOperandNo ) . ChangeToImmediate ( Offset ) ; return ; } bool is64Bit = Subtarget . is<ISA_LIT>64 ( ) ; const TargetRegisterClass * G8RC = & <STR_LIT> ; const TargetRegisterClass * GPRC = & <STR_LIT> ; const TargetRegisterClass * RC = is64Bit ? G8RC : GPRC ; unsigned SRegHi = MF . getRegInfo ( ) . createVirtualRegister ( RC ) , SReg = MF . getRegInfo ( ) . createVirtualRegister ( RC ) ; BuildMI ( MBB , II , dl , TII . get ( is64Bit ? <STR_LIT> : <STR_LIT> ) , SRegHi ) . addImm ( Offset >> <NUM_LIT> ) ; BuildMI ( MBB , II , dl , TII . get ( is64Bit ? <STR_LIT> : <STR_LIT> ) ,

SReg ) . addReg ( SRegHi , RegState :: Kill ) . addImm ( Offset ) ;


<s> if ( ! MayClobberFrom && ! MayClobberTo ) return false ; if ( ( MayClobberFrom && ! MayClobberTo ) || ( ! MayClobberFrom && MayClobberTo ) ) return true ; return ! ( ( MBBFrom == MBBTo && MDT . dominates ( Clobber , & * From ) && MDT . dominates ( Clobber , & * To ) ) || MDT . properlyDominates ( Clobber -> getParent ( ) , MBBTo ) ) ; } ; return ( llvm :: any_of ( Clobbers , interferes ) ) || ( llvm :: any_of ( Inits , [ & ] ( InitListMap :: value_type & C ) { return C . first != Init . first && llvm :: any_of ( C . second , interferes ) ; } ) ) ; } ; if ( MDT . dominates ( MI1 , MI2 ) ) { if ( ! intereferes ( MI2 , MI1 ) ) { DEBUG ( dbgs ( ) << <STR_LIT> << MI2 -> getParent ( ) -> getNumber ( ) << <STR_LIT> << * MI2 ) ; MI2 -> eraseFromParent ( ) ; Defs . erase ( I2 ++ ) ; Changed = true ; continue ; } } else if ( MDT . dominates ( MI2 , MI1 ) ) { if ( ! intereferes ( MI1 , MI2 ) ) { DEBUG ( dbgs ( ) << <STR_LIT> << MI1 -> getParent ( ) -> getNumber ( ) << <STR_LIT> << * MI1 ) ; MI1 -> eraseFromParent ( ) ; Defs . erase ( I1 ++ ) ; Changed = true ; break ; } } else


<s> FunctionPass * llvm :: create<ISA_LIT>PrepareForLiveIntervals ( ) { return new <ISA_LIT>PrepareForLiveIntervals (


<s> const <ISA_LIT>Subtarget & STI = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; const <ISA_LIT>FrameLowering * TFI = getFrameLowering ( MF ) ; if ( TFI -> hasFP ( MF ) ) return


<s> return ! ( PersonalityLocs . empty ( ) && PersonalityIndexLocs .


<s> const char * name = TREE_STRING_POINTER ( DECL_SECTION_NAME ( decl ) ) ; if ( streq ( name , <STR_LIT> ) || streq ( name , <STR_LIT> ) ) v850_set_data_area ( decl , DATA_AREA_ZDA ) ; else if ( streq ( name , <STR_LIT> ) || streq ( name , <STR_LIT> ) ) v850_set_data_area ( decl , DATA_AREA_SDA ) ; else if ( streq ( name , <STR_LIT> ) ) v850_set_data_area ( decl , DATA_AREA_TDA ) ; } else { int size = int_size_in_bytes ( TREE_TYPE ( decl


<s> WeakRefDirective = <STR_LIT> ; HasLCOMMDirective = true ; DwarfRequiresFrameSection = false ; SupportsDebugInformation =


<s> case TCTX_POINTER_ARITH : if ( ! silent_p ) error_at ( loc , <STR_LIT> , type ) ; return false ; case TCTX_FIELD : if ( silent_p ) ; else if ( lang_GNU_CXX ( ) ) error_at ( loc , <STR_LIT> , type ) ; else error_at ( loc , <STR_LIT> , type ) ; return false ; case TCTX_ARRAY_ELEMENT : if ( ! silent_p ) error_at ( loc , <STR_LIT> , type ) ; return false ; case TCTX_ALLOCATION : if ( ! silent_p ) error_at ( loc , <STR_LIT> , type ) ; return false ; case


<s> assert ( TheModule == & M ) ; TheModule = nullptr ; EHLinkRegistrationTy = nullptr ; CXXEHRegistrationTy = nullptr ; SEHRegistrationTy = nullptr ; SetJmp3 = nullptr ; CxxLongjmpUnwind = nullptr ; SehLongjmpUnwind = nullptr ; Cookie = nullptr ; return false


<s> if ( std :: next ( I ) == I -> getParent ( ) -> end ( ) ) return false ; return std :: next ( I ) -> getOpcode (


<s> return new <ISA_LIT>DAGToDAGISel ( TM , OptLevel


<s> return new <ISA_LIT>VectorRegMerger ( tm


<s> bool hasFusion ( ) const { return hasArithmeticBccFusion ( ) || hasArithmeticCbzFusion ( ) || hasFuseAES ( ) || hasFuseCCSelect ( )


<s> REAL_VALUE_TO_TARGET_SINGLE ( * CONST_DOUBLE_REAL_VALUE ( x ) , value_long [ <NUM_LIT> ] ) ; if ( HOST_BITS_PER_LONG > <NUM_LIT> ) value_long [ <NUM_LIT> ] &= <NUM_LIT> ; fprintf ( file , <STR_LIT> , value_long [ <NUM_LIT> ] ) ; break ; case DFmode : REAL_VALUE_TO_TARGET_DOUBLE ( * CONST_DOUBLE_REAL_VALUE ( x ) , value_long ) ; if ( HOST_BITS_PER_LONG > <NUM_LIT> ) { value_long [ <NUM_LIT> ] &= <NUM_LIT> ; value_long [ <NUM_LIT> ] &= <NUM_LIT> ; } fprintf ( file , <STR_LIT> , value_long [ <NUM_LIT> ] , value_long [ <NUM_LIT> ] ) ; break ; default : gcc_unreachable ( ) ; } break ; case MODE_INT : case MODE_PARTIAL_INT : size = GET_MODE_SIZE ( mode ) ; switch ( size ) { case <NUM_LIT>


<s> MachineBasicBlock & MBB = * MI . getParent ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; DebugLoc dl = MI . getDebugLoc ( ) ; unsigned FIOperandNo = <NUM_LIT> ; while ( ! MI . getOperand ( FIOperandNo ) . isFI ( ) ) { ++ FIOperandNo ; assert ( FIOperandNo != MI . getNumOperands ( ) && <STR_LIT> ) ; } unsigned OffsetOperandNo = ( FIOperandNo == <NUM_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; if ( MI . isInlineAsm ( ) ) OffsetOperandNo = FIOperandNo - <NUM_LIT> ; int FrameIndex = MI . getOperand ( FIOperandNo ) . getIndex ( ) ; <ISA_LIT>FunctionInfo * FI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; int FPSI = FI -> getFramePointerSaveIndex ( ) ; unsigned OpC = MI . getOpcode ( ) ; if ( FPSI && FrameIndex == FPSI && ( OpC == <STR_LIT> || OpC == <STR_LIT> ) ) { lowerDynamicAlloc ( II , SPAdj , RS ) ; return <NUM_LIT> ; } if ( EnableRegisterScavenging ) if ( OpC == <STR_LIT> ) { lowerCRSpilling ( II , FrameIndex , SPAdj , RS ) ; return <NUM_LIT> ; } MI . getOperand ( FIOperandNo ) . ChangeToRegister ( hasFP ( MF ) ? <STR_LIT> : <STR_LIT> , false ) ; bool isIXAddr = false ; switch ( OpC ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : isIXAddr = true ; break ; } int Offset = MFI -> getObjectOffset ( FrameIndex ) ; if ( ! isIXAddr ) Offset += MI . getOperand ( OffsetOperandNo ) . getImm ( ) ; else Offset += MI . getOperand ( OffsetOperandNo ) . getImm ( ) << <NUM_LIT> ; Offset += MFI -> getStackSize ( ) ; if ( isInt16 ( Offset ) && ( ! isIXAddr || ( Offset & <NUM_LIT> ) == <NUM_LIT> ) ) { if ( isIXAddr ) Offset >>= <NUM_LIT> ; MI . getOperand ( OffsetOperandNo ) . ChangeToImmediate ( Offset ) ; return


<s> const TargetFrameLowering * TFI = MF . getTarget ( ) . getFrameLowering ( ) ; const unsigned DefaultSafety = <NUM_LIT> ; switch ( RC -> getID ( ) ) { default : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { unsigned FP = TFI -> hasFP ( MF ) ? <NUM_LIT> : <NUM_LIT> ; return <NUM_LIT> - FP - DefaultSafety ; } case <STR_LIT> : case <STR_LIT>


<s> if ( ElemWidth == <NUM_LIT> ) { assert ( VecWidth == VecTy . getVectorNumElements ( ) && <STR_LIT> ) ; assert ( VecWidth == <NUM_LIT> || VecWidth == <NUM_LIT> || VecWidth == <NUM_LIT> ) ; if ( IdxN ) { if ( IdxN -> isNullValue ( ) && ValTy . getSizeInBits ( ) == <NUM_LIT> ) return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , VecV ) ; } if ( ValWidth == <NUM_LIT> ) { SDValue A0 = getInstr ( <STR_LIT> , dl , <STR_LIT> , { VecV } , DAG ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , A0 , IdxV ) ; } unsigned Scale = VecWidth / ValWidth ; assert ( ty ( IdxV ) == <STR_LIT> ) ; SDValue S0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , IdxV , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; SDValue T0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , VecV ) ; SDValue T1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , T0 , S0 ) ; while ( Scale > <NUM_LIT> ) { T1 = DAG . getTargetExtractSubreg ( <STR_LIT> , dl , <STR_LIT> , T1 ) ; T1 = expandPredicate ( T1 , dl , DAG ) ; Scale /= <NUM_LIT> ; } return DAG . getNode ( <STR_LIT> , dl , ResTy


<s> ExtractSubReg = <STR_LIT> ; break ; case <NUM_LIT> : CopyOpc = <STR_LIT> ; ExtractSubReg = <STR_LIT> ; break ; default : LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << EltSize


<s> bool <ISA_LIT>InstrInfo :: shouldClusterLoads ( MachineInstr * FirstLdSt , MachineInstr * SecondLdSt , unsigned NumLoads ) const { if ( NumLoads > <NUM_LIT> ) return false ; if ( FirstLdSt -> getOpcode ( ) != SecondLdSt -> getOpcode ( ) ) return false ; unsigned Ofs1 = FirstLdSt -> getOperand ( <NUM_LIT> ) .


<s> static TargetLowering :: ArgListTy getDivRemArgList ( const SDNode * N , LLVMContext * Context , const <ISA_LIT>Subtarget * Subtarget ) { assert ( ( N -> getOpcode ( ) == <STR_LIT> || N -> getOpcode ( ) == <STR_LIT> || N -> getOpcode ( ) == <STR_LIT> || N -> getOpcode ( ) == <STR_LIT> ) && <STR_LIT> ) ; bool isSigned = N -> getOpcode ( ) == <STR_LIT> || N -> getOpcode ( ) == <STR_LIT> ; TargetLowering :: ArgListTy Args ; TargetLowering :: ArgListEntry Entry ; for ( unsigned i = <NUM_LIT> , e = N -> getNumOperands ( ) ; i != e ; ++ i ) { EVT ArgVT = N -> getOperand ( i ) . getValueType ( ) ; Type * ArgTy = ArgVT . getTypeForEVT ( * Context ) ; Entry . Node = N -> getOperand ( i ) ; Entry . Ty = ArgTy ; Entry . isSExt = isSigned ; Entry . isZExt = ! isSigned ; Args . push_back ( Entry ) ; } if ( Subtarget -> isTargetWindows ( ) && Args . size ( ) >= <NUM_LIT> ) std :: swap ( Args [ <NUM_LIT> ] , Args [ <NUM_LIT> ] ) ; return


<s> rtx untagged_base = expand_simple_binop ( Pmode , AND , tagged_pointer , tag_mask , target , true , OPTAB_DIRECT ) ; gcc_assert ( untagged_base


<s> static DecodeStatus DecodeVLD3DupInstruction ( llvm :: MCInst & Inst , unsigned Insn , uint64_t Address , const void * Decoder ) { DecodeStatus S = MCDisassembler :: Success ; unsigned Rd = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; Rd |= fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ; unsigned Rn = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned Rm = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned inc = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) + <NUM_LIT> ; if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , Rd , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , ( Rd + inc ) % <NUM_LIT> , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , ( Rd + <NUM_LIT> * inc ) % <NUM_LIT> , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( Rm != <NUM_LIT> ) { if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rn , Address , Decoder ) ) ) return MCDisassembler :: Fail ; } if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rn , Address , Decoder ) ) ) return MCDisassembler :: Fail ; Inst . addOperand ( MCOperand :: CreateImm ( <NUM_LIT>


<s> static struct machine_function * s390_init_machine_status


<s> return __builtin_aarch64_floatdihf (


<s> static inline vec_uint4 vec_sra ( vec_uint4 a ,


<s> EVT VT = N -> getValueType ( <NUM_LIT> ) ; SDValue Val = N -> getOperand ( <NUM_LIT>


<s> if ( NoAliases || ! printAliasInstr ( MI , STI , O ) ) printInstruction ( MI , STI , O ) ; printAnnotation ( O , Annot


<s> unsigned Align = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; EVT VT = Op . getNode ( ) -> getValueType ( <NUM_LIT> ) ; bool Has64BitPointers = Subtarget -> has64BitPointers ( ) ; EVT SPTy = Has64BitPointers ? <STR_LIT> : <STR_LIT> ; if ( getTargetMachine ( ) . Options . EnableSegmentedStacks ) { MachineFunction & MF = DAG . getMachineFunction ( ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; if ( Subtarget -> is64Bit ( ) ) { const Function * F = MF . getFunction ( ) ; for ( Function :: const_arg_iterator I = F -> arg_begin ( ) , E = F -> arg_end ( ) ; I != E ; ++ I ) if ( I -> hasNestAttr ( ) ) report_fatal_error ( <STR_LIT> <STR_LIT> ) ; } const TargetRegisterClass * AddrRegClass = getRegClassFor ( Has64BitPointers ? <STR_LIT> : <STR_LIT> ) ; unsigned Vreg = MRI . createVirtualRegister ( AddrRegClass ) ; Chain = DAG . getCopyToReg ( Chain , dl , Vreg , Size ) ; SDValue Value = DAG . getNode ( <STR_LIT> , dl , SPTy , Chain , DAG . getRegister ( Vreg , SPTy ) ) ; SDValue Ops1 [ <NUM_LIT> ] = { Value , Chain } ; return DAG . getMergeValues ( Ops1 , <NUM_LIT> , dl ) ; } else { SDValue Flag ; unsigned Reg = ( Has64BitPointers ? <STR_LIT> : <STR_LIT> ) ; Chain = DAG . getCopyToReg ( Chain , dl , Reg , Size , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; SDVTList NodeTys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; Chain = DAG . getNode ( <STR_LIT> , dl , NodeTys , Chain


<s> SmallVector < int , <NUM_LIT> > MaskHigh ; SmallVector < int , <NUM_LIT> > MaskLow ; SmallVector < int , <NUM_LIT> > LowHighMask [ <NUM_LIT> ] ; SmallVector < int , <NUM_LIT> > MaskHighTemp ; SmallVector < int , <NUM_LIT> > MaskLowTemp ; createUnpackShuffleMask ( VT , MaskLow , true , false ) ; createUnpackShuffleMask ( VT , MaskHigh , false , false ) ; createUnpackShuffleMask ( HalfVT , MaskLowTemp , true , false ) ; createUnpackShuffleMask ( HalfVT , MaskHighTemp , false , false ) ; narrowShuffleMaskElts ( <NUM_LIT> , MaskLowTemp , LowHighMask [ <NUM_LIT> ] ) ; narrowShuffleMaskElts ( <NUM_LIT> , MaskHighTemp , LowHighMask [ <NUM_LIT> ] ) ; Value * IntrVec [ <NUM_LIT> ] ; IntrVec [ <NUM_LIT> ] = Builder . CreateShuffleVector ( Matrix [

<NUM_LIT> ] , Matrix [ <NUM_LIT> ] , MaskLow ) ;


<s> if ( M . size ( ) != static_cast < size_t > ( NumInputElements ) ) return false ; int NumLHSMatch = <NUM_LIT> , NumRHSMatch = <NUM_LIT> ; int LastLHSMismatch = - <NUM_LIT> , LastRHSMismatch = - <NUM_LIT> ; for ( int i = <NUM_LIT> ; i < NumInputElements ; ++ i ) { if ( M [ i ] == - <NUM_LIT> ) { ++ NumLHSMatch


<s> virtual const <ISA_LIT>SelectionDAGInfo * getSelectionDAGInfo ( ) const { return &


<s> unsigned IsExtern = <NUM_LIT> ; unsigned Type = <NUM_LIT> ; if ( Target . isAbsolute ( ) ) { Type = macho :: RIT_Vanilla ; } else { if ( SD -> getSymbol ( ) . isVariable ( ) ) { int64_t Res ; if ( SD -> getSymbol ( ) . getVariableValue ( ) -> EvaluateAsAbsolute ( Res , Layout , Writer -> getSectionAddressMap ( ) ) ) { FixedValue = Res ; return ; } } if ( Writer -> doesSymbolRequireExternRelocation ( SD ) ) { IsExtern = <NUM_LIT> ; Index = SD -> getIndex ( ) ; if ( ! SD -> Symbol -> isUndefined ( ) ) FixedValue -= Layout . getSymbolOffset ( SD ) ; } else { const MCSectionData & SymSD = Asm . getSectionData ( SD -> getSymbol ( ) . getSection ( ) ) ; Index = SymSD . getOrdinal ( ) + <NUM_LIT> ; FixedValue += Writer -> getSectionAddress ( & SymSD ) ; } if ( IsPCRel ) FixedValue -= Writer -> getSectionAddress


<s> if ( isFence ( Dest -> getValue ( ) ) ) { ElimNodes . insert ( * Dest ) ; ElimEdges . insert ( E ) ; for ( const Edge & DE : Dest -> edges ( ) ) ElimEdges . insert ( DE ) ; } } } int MitigatedGadgets = <NUM_LIT> , RemainingGadgets = <NUM_LIT> ; NodeSet ReachableNodes { G } ; for ( const Node & RootN : G . nodes ( ) ) { if ( llvm :: none_of ( RootN . edges ( ) , MachineGadgetGraph :: isGadgetEdge ) ) continue ; ReachableNodes . clear ( ) ; std :: function < void ( const Node * , bool ) > FindReachableNodes = [ & ] ( const Node * N , bool FirstNode ) { if ( ! FirstNode ) ReachableNodes . insert ( * N ) ; for ( const Edge & E : N -> edges ( ) ) { const Node * Dest = E . getDest ( ) ; if ( MachineGadgetGraph :: isCFGEdge ( E ) && ! ElimEdges . contains ( E ) && ! ReachableNodes . contains ( * Dest ) ) FindReachableNodes ( Dest , false ) ; } } ; FindReachableNodes ( & RootN , true ) ; for ( const Edge & E : RootN . edges ( ) ) { if ( MachineGadgetGraph :: isGadgetEdge ( E ) ) { if ( ReachableNodes . contains ( * E . getDest ( ) ) ) { ++ RemainingGadgets ; } else { ++ MitigatedGadgets


<s> uint8_t Sign = ( Imm >> <NUM_LIT> ) & <NUM_LIT> ; uint8_t Exp = ( Imm >> <NUM_LIT> ) & <NUM_LIT> ; uint8_t Mantissa = Imm & <NUM_LIT> ; FPUnion . I = <NUM_LIT> ; FPUnion . I |= Sign << <NUM_LIT> ; FPUnion . I |= ( ( Exp & <NUM_LIT> ) != <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> )


<s> if ( ! F . hasPersonalityFn ( ) ) return false ; PersonalityFn = dyn_cast < Function > ( F . getPersonalityFn ( ) -> stripPointerCasts ( ) ) ; if ( ! PersonalityFn ) return false ; Personality = classifyEHPersonality ( PersonalityFn ) ; if ( ! isFuncletEHPersonality ( Personality ) ) return false ; bool HasPads = false ; for ( BasicBlock & BB : F ) { if ( BB . isEHPad ( ) ) { HasPads = true ; break ; } } if ( ! HasPads ) return false ; Type * Int8PtrType = Type :: getInt8PtrTy ( TheModule ->


<s> rtx addr , align , wdst ; cond = operands [ <NUM_LIT> ] ; dst = operands [ <NUM_LIT> ] ; mem = operands [ <NUM_LIT> ] ; oldval = operands [ <NUM_LIT> ] ; newval = operands [ <NUM_LIT> ] ; is_weak = operands [ <NUM_LIT> ] ; mod_s = operands [ <NUM_LIT> ] ; mod_f = operands [ <NUM_LIT> ] ; mode = GET_MODE ( mem ) ; addr = XEXP ( mem , <NUM_LIT> ) ; gcc_assert ( register_operand ( addr , DImode ) ) ; align = expand_simple_binop ( Pmode , AND , addr , GEN_INT ( -


<s> bool BitSimplification :: genExtractHalf ( MachineInstr * MI , BitTracker :: RegisterRef RD , const BitTracker :: RegisterCell & RC ) { RegHalf L ; if ( ! matchHalf ( RD . Reg , RC , <NUM_LIT> , L ) || ! HBS :: isZero ( RC , <NUM_LIT> , <NUM_LIT> ) ) return false ; unsigned Opc = MI -> getOpcode ( ) ; MachineBasicBlock & B = * MI -> getParent ( ) ; DebugLoc DL = MI -> getDebugLoc ( ) ; unsigned NewR = <NUM_LIT> ; if ( L . Low && Opc != <STR_LIT> ) { NewR = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( B , MI , DL , HII . get ( <STR_LIT> ) , NewR ) . addReg ( L . Reg , <NUM_LIT> , L . Sub ) ; } else if ( ! L . Low && Opc != <STR_LIT> ) { NewR = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( B , MI , DL , HII . get ( <STR_LIT> ) , NewR ) . addReg ( L . Reg , <NUM_LIT> , L . Sub ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; } if ( NewR == <NUM_LIT> ) return false ; HBS :: replaceSubWithSub ( RD . Reg , RD . Sub , NewR


<s> C . CCMask = CCMaskForCondCode ( Cond ) ; if ( C . Op0 . getValueType ( ) . isFloatingPoint ( ) ) { C . CCValid = <STR_LIT> ; C . Opcode = <STR_LIT> ; adjustForFNeg ( C ) ; } else { C . CCValid = <STR_LIT> ; C . Opcode = <STR_LIT> ; if ( C . CCMask == <STR_LIT> || C . CCMask == <STR_LIT> || ( DAG . SignBitIsZero ( C . Op0 ) && DAG . SignBitIsZero ( C . Op1 ) ) ) C . ICmpType = <STR_LIT> ; else if ( C . CCMask & <STR_LIT> ) C . ICmpType = <STR_LIT> ; else C . ICmpType = <STR_LIT> ; C . CCMask &= ~ <STR_LIT> ; adjustZeroCmp ( DAG , C ) ; adjustSubwordCmp ( DAG , C ) ; adjustForSubtraction ( DAG , C ) ; adjustForLTGFR ( C ) ; adjustICmpTruncate ( DAG


<s> const Triple & TT = TM -> getTargetTriple ( ) ; const MCAsmInfo * MAI = TM -> getMCAsmInfo ( ) ; addPass ( create<ISA_LIT>RetpolineThunksPass ( ) ) ; if ( TT . isOSWindows ( ) && TT . getArch ( ) == Triple :: x86_64 ) addPass ( create<ISA_LIT>AvoidTrailingCallPass ( ) ) ; if ( ! TT . isOSDarwin ( ) && ( ! TT . isOSWindows ( ) || MAI -> getExceptionHandlingType ( ) == ExceptionHandling :: DwarfCFI ) ) addPass ( createCFIInstrInserter ( ) ) ; if ( TT . isOSWindows ( )

) addPass ( createCFGuardLongjmpPass ( ) ) ;


<s> static bool hasAGPRs ( const TargetRegisterClass * RC ) { return RC -> TSFlags &


<s> if ( VA . isRegLoc ( ) ) { EVT RegVT = VA . getLocVT ( ) ; switch ( RegVT . getSimpleVT ( ) . SimpleTy ) { case <STR_LIT> : { const unsigned VReg = RegInfo . createVirtualRegister ( & <STR_LIT> ) ; RegInfo . addLiveIn ( VA . getLocReg ( ) , VReg ) ; SDValue ArgIn = DAG . getCopyFromReg ( Chain , DL , VReg , RegVT ) ; InVals . push_back ( ArgIn ) ; break ; } default : DEBUG ( dbgs ( ) << <STR_LIT> << RegVT . getEVTString (


<s> const TargetInstrInfo * TII = MF . getSubtarget ( ) . getInstrInfo ( ) ; MachineInstr * cmpInst = BuildMI ( MF , DL3 , TII -> get ( <STR_LIT> ) ) . addReg ( reg ) . addReg ( getSlaveReg1 ( reg ) ) ; lastCheck -> insert ( CI , cmpInst ) ; MachineInstr * copyMoveM = BuildMI ( MF , DL3 , TII -> get ( <STR_LIT> ) ) . addReg ( reg ) . addReg ( getSlaveReg2 ( reg ) ) . addReg ( reg ) ; lastCheck -> insert ( CI , copyMoveM ) ; MachineInstr * copyMoveD = BuildMI ( MF , DL3 , TII -> get ( <STR_LIT> ) ) . addReg ( getSlaveReg1 ( reg ) ) . addReg ( getSlaveReg2 ( reg ) ) . addReg ( getSlaveReg1 ( reg ) ) ; lastCheck -> insert ( CI , copyMoveD ) ; return


<s> MachineBasicBlock * TmpMBB = const_cast < MachineBasicBlock * > ( & MBB ) ; return findScratchRegister ( TmpMBB , true


<s> Offset += <NUM_LIT> ; Offset += <NUM_LIT> ; emitKernelArg ( DL , Int64Ty , Align ( <NUM_LIT> ) , <STR_LIT> , Offset , Args ) ; emitKernelArg ( DL , Int64Ty , Align ( <NUM_LIT> ) , <STR_LIT> , Offset , Args ) ; emitKernelArg ( DL , Int64Ty , Align ( <NUM_LIT> ) , <STR_LIT> , Offset , Args ) ; emitKernelArg ( DL , Int16Ty , Align ( <NUM_LIT> ) , <STR_LIT> , Offset , Args ) ; Offset += <NUM_LIT> ; auto Int8PtrTy = Type :: getInt8PtrTy ( Func . getContext ( ) , <ISA_LIT>AS :: GLOBAL_ADDRESS ) ; if ( M -> getNamedMetadata ( <STR_LIT> ) ) { emitKernelArg ( DL , Int8PtrTy , Align ( <NUM_LIT> ) , <STR_LIT> , Offset , Args ) ; } else Offset += <NUM_LIT> ; if ( ! Func . hasFnAttribute ( <STR_LIT> ) ) { emitKernelArg ( DL , Int8PtrTy , Align ( <NUM_LIT> ) , <STR_LIT> , Offset , Args ) ; } else Offset += <NUM_LIT> ; emitKernelArg ( DL , Int8PtrTy , Align ( <NUM_LIT> ) , <STR_LIT> , Offset , Args ) ; if ( ! Func . hasFnAttribute ( <STR_LIT> ) ) emitKernelArg ( DL , Int8PtrTy ,


<s> static void ix86_encode_section_info ( tree decl , rtx rtl , int first ) { default_encode_section_info ( decl , rtl ,


<s> HasSTFIWX = false ; HasLFIWAX = false ; HasFPRND = false ; HasFPCVT = false ; HasISEL = false ; HasPOPCNTD = false ; HasCMPB = false ; HasLDBRX = false ; IsBookE = false ; HasOnlyMSYNC = false ; Is<ISA_LIT>4xx = false ; Is<ISA_LIT>6xx = false ; IsE500 = false ; DeprecatedMFTB = false ; DeprecatedDST = false ; HasLazyResolverStubs = false ; HasICBT = false ; HasInvariantFunctionDescriptors =


<s> bool <ISA_LIT>InstrInfo :: isNewValue ( unsigned Opcode ) const { const uint64_t F = get ( Opcode


<s> if ( Callee == <NUM_LIT> ) return false ; BasicBlock * BB = CI -> getParent ( ) ; LLVMContext & Context = CI -> getParent ( ) -> getContext ( ) ; IRBuilder < > B ( Context ) ; B . SetInsertPoint ( BB , CI -> getIterator ( ) ) ; if ( const FPMathOperator * FPOp = dyn_cast < const FPMathOperator > ( CI ) ) B . setFastMathFlags ( FPOp -> getFastMathFlags ( ) ) ; switch ( Callee -> getIntrinsicID ( ) ) { default : break ; case <STR_LIT> : return ! EnablePreLink && fold_wavefrontsize ( CI , B ) ; } FuncInfo FInfo ; if ( ! parseFunctionName ( Callee -> getName ( ) , FInfo ) ) return false ; if ( CI -> arg_size ( ) != FInfo . getNumArgs ( ) ) return false ; if ( TDOFold ( CI , FInfo ) ) return true ; if ( isUnsafeMath ( CI ) && evaluateCall ( CI , FInfo ) ) return true ; switch ( FInfo . getId ( ) ) { case <ISA_LIT>LibFunc :: EI_RECIP : assert ( ( FInfo . getPrefix ( ) == <ISA_LIT>LibFunc :: NATIVE || FInfo . getPrefix ( ) == <ISA_LIT>LibFunc :: HALF ) && <STR_LIT> ) ; return ( getVecSize ( FInfo ) != <NUM_LIT> ) ? false : fold_recip ( CI , B , FInfo ) ; case <ISA_LIT>LibFunc :: EI_DIVIDE : assert ( ( FInfo . getPrefix ( ) == <ISA_LIT>LibFunc :: NATIVE || FInfo . getPrefix ( ) == <ISA_LIT>LibFunc :: HALF ) && <STR_LIT> ) ; return ( getVecSize ( FInfo ) != <NUM_LIT> ) ? false : fold_divide ( CI , B , FInfo ) ; case <ISA_LIT>LibFunc :: EI_POW : case <ISA_LIT>LibFunc :: EI_POWR : case <ISA_LIT>LibFunc :: EI_POWN : return fold_pow ( CI , B , FInfo ) ; case <ISA_LIT>LibFunc :: EI_ROOTN : return ( getVecSize ( FInfo ) != <NUM_LIT> ) ? false : fold_rootn ( CI , B , FInfo ) ; case <ISA_LIT>LibFunc :: EI_FMA : case <ISA_LIT>LibFunc :: EI_MAD : case <ISA_LIT>LibFunc :: EI_NFMA : return ( getVecSize ( FInfo ) != <NUM_LIT> ) ? false : fold_fma_mad ( CI , B , FInfo ) ; case <ISA_LIT>LibFunc


<s> static int mt_arg_partial_bytes ( CUMULATIVE_ARGS * pcum , enum machine_mode mode , tree type , bool named ATTRIBUTE_UNUSED ) { int cum = * pcum ; int words ; if ( mode == BLKmode ) words = ( ( int_size_in_bytes ( type ) + UNITS_PER_WORD - <NUM_LIT> ) / UNITS_PER_WORD ) ; else words = ( GET_MODE_SIZE ( mode ) + UNITS_PER_WORD - <NUM_LIT> ) / UNITS_PER_WORD ; if ( ! targetm . calls . pass_by_reference ( & cum , mode , type , named ) && cum <

MT_NUM_ARG_REGS && ( cum + words ) > MT_NUM_ARG_REGS ) {


<s> RetTyABI = Type :: getVoidTy ( * DAG . getContext ( ) ) ; } assert ( Op -> getNumOperands ( ) >= numArgs && <STR_LIT> ) ; for ( unsigned i = <NUM_LIT> , e = numArgs ; i != e ; ++ i ) { Chain = LowerF128_LibCallArg ( Chain , Args , Op . getOperand ( i ) , SDLoc ( Op ) , DAG ) ; } TargetLowering :: CallLoweringInfo CLI ( DAG ) ; CLI . setDebugLoc ( SDLoc ( Op ) ) . setChain ( Chain ) . setCallee ( CallingConv :: C , RetTyABI , Callee , std :: move ( Args ) ) ; std :: pair < SDValue , SDValue > CallInfo = LowerCallTo ( CLI ) ; if ( RetTyABI == RetTy ) return CallInfo . first ; assert ( RetTy -> isFP128Ty ( ) && <STR_LIT> ) ; Chain = CallInfo


<s> void <ISA_LIT>InstPrinter :: printInst ( const MCInst * MI , uint64_t Address , StringRef Annot , const MCSubtargetInfo &


<s> assert ( Result >= <NUM_LIT> && <STR_LIT> ) ; return


<s> Info . memVT = <STR_LIT> ( CI . getType ( ) , true ) ; if ( Info . memVT == <STR_LIT> ) { Info . memVT = memVTFromAggregate ( CI . getType ( ) ) ; } Info . flags |= MachineMemOperand :: MOLoad ; } else if ( Attr . hasFnAttribute ( Attribute :: WriteOnly ) ) { Info . opc = <STR_LIT> ; Info . memVT = <STR_LIT> ( CI . getArgOperand ( <NUM_LIT> ) -> getType ( ) ) ; Info . flags |= MachineMemOperand :: MOStore ; } else { Info . opc = <STR_LIT> ; Info . memVT = <STR_LIT> ( CI . getType ( ) ) ; Info . flags = MachineMemOperand :: MOLoad | MachineMemOperand :: MOStore | MachineMemOperand :: MODereferenceable ; Info . flags |= MachineMemOperand :: MOVolatile ; } return true ; } switch ( IntrID ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { Info . opc =


<s> bool BTFDebug :: InstLower ( const MachineInstr * MI , MCInst & OutMI ) { if ( MI -> getOpcode ( ) == <STR_LIT> ) { const MachineOperand & MO = MI -> getOperand ( <NUM_LIT> ) ; if ( MO . isGlobal ( ) ) { const GlobalValue * GVal = MO . getGlobal ( ) ; auto * GVar = dyn_cast < GlobalVariable > ( GVal ) ; if ( GVar && GVar -> hasAttribute ( <STR_LIT> ) ) { MDNode * MDN = GVar -> getMetadata ( LLVMContext :: MD_preserve_access_index ) ; DIType * Ty = dyn_cast < DIType > ( MDN ) ; std :: string TypeName = Ty -> getName ( ) ; int64_t Imm = AccessOffsets [ GVar -> getName ( ) . str (


<s> const LLT S64 = LLT :: scalar ( <NUM_LIT> ) ; const LLT S32 = LLT :: scalar ( <NUM_LIT> ) ; const LLT SrcLT = MRI . getType ( Src ) ; assert ( ( SrcLT == S32 || SrcLT == S64 ) && MRI . getType ( Dst ) == S64 ) ; unsigned Flags = MI . getFlags ( ) ; auto Trunc = B . buildIntrinsicTrunc ( SrcLT , Src , Flags ) ; MachineInstrBuilder Sign ; if ( Signed && SrcLT == S32 ) { Sign = B . buildAShr ( S32 , Src , B . buildConstant ( S32 , <NUM_LIT> ) ) ; Trunc = B . buildFAbs ( S32 , Trunc , Flags ) ; } MachineInstrBuilder K0 , K1 ; if ( SrcLT == S64 ) { K0 = B . buildFConstant ( S64 , BitsToDouble ( UINT64_C ( <NUM_LIT> ) ) ) ; K1 = B . buildFConstant ( S64 , BitsToDouble ( UINT64_C ( <NUM_LIT> ) ) ) ; } else { K0 = B . buildFConstant ( S32 , BitsToFloat ( UINT32_C ( <NUM_LIT> ) ) ) ; K1 = B . buildFConstant ( S32 , BitsToFloat ( UINT32_C ( <NUM_LIT> ) ) ) ; } auto Mul = B . buildFMul ( SrcLT , Trunc , K0 , Flags ) ; auto FloorMul = B . buildFFloor ( SrcLT , Mul , Flags ) ; auto Fma = B . buildFMA ( SrcLT , FloorMul , K1 ,


<s> Entry . isSExt = isSigned ; Entry . isZExt = ! isSigned ; Args . push_back ( Entry ) ; } SDValue Callee = DAG . getExternalSymbol ( TLI . getLibcallName ( LC ) , TLI . getPointerTy ( ) ) ; Type * RetTy = Op . getNode ( ) -> getValueType ( <NUM_LIT> ) . getTypeForEVT ( * DAG . getContext ( ) ) ; TargetLowering :: CallLoweringInfo CLI ( InChain , RetTy , isSigned , ! isSigned , false , false , <NUM_LIT> , TLI . getLibcallCallingConv (

LC ) , false , false , true , Callee , Args , DAG , Op . getDebugLoc ( ) ) ;


<s> alias_set_type set = get_varargs_alias_set ( ) ; if ( argadj ) offset = plus_constant ( Pmode , crtl -> args . arg_offset_rtx , argadj ) ; else offset = crtl -> args . arg_offset_rtx ; mem = gen_rtx_MEM ( SImode , crtl -> args . internal_arg_pointer ) ; set_mem_alias_set ( mem , set


<s> bool hasStdExtZba ( ) const { return HasStdExtZba


<s> SDValue <ISA_LIT>TargetLowering :: getSegmentAperture ( unsigned AS , SelectionDAG & DAG ) const { SDLoc SL ; MachineFunction & MF = DAG . getMachineFunction ( ) ; <ISA_LIT>MachineFunctionInfo * Info = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; unsigned UserSGPR = Info -> getQueuePtrUserSGPR ( ) ; assert ( UserSGPR != <STR_LIT> ) ; SDValue QueuePtr = CreateLiveInRegister ( DAG , & <STR_LIT> , UserSGPR


<s> BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , TmpReg ) . addReg ( <STR_LIT> ) . addConstantPoolIndex ( Idx ) ; if ( CModel == CodeModel :: Large ) { unsigned TmpReg2 = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , TmpReg2 ) . addConstantPoolIndex ( Idx ) . addReg ( TmpReg ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , DestReg ) . addImm ( <NUM_LIT> ) . addReg ( TmpReg2 ) ; } else BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , DestReg ) . addConstantPoolIndex ( Idx , <NUM_LIT> , <STR_LIT> ) . addReg ( TmpReg )


<s> return get<ISA_LIT>ArchVersion ( ) == <STR_LIT> ::


<s> if ( post_update_insn_p ( producer ) ) return false ; rtx def_reg = SET_DEST ( PATTERN ( producer ) ) ; return n8_consumed_by_ex_p ( consumer , def_reg


<s> const StructType * STy = cast < const StructType > ( Ty ) ; for ( auto & E : STy -> elements ( ) ) { unsigned AtomicSize = getSmallestAddressableSize ( E , GV , TM ) ; if ( AtomicSize < SmallestElement ) SmallestElement = AtomicSize ; } return ( STy -> getNumElements ( ) == <NUM_LIT> ) ? <NUM_LIT> : SmallestElement ; } case Type :: ArrayTyID : { const ArrayType * ATy = cast < const ArrayType > ( Ty ) ; return getSmallestAddressableSize ( ATy -> getElementType ( ) , GV , TM ) ; } case Type :: FixedVectorTyID : case Type :: ScalableVectorTyID : { const VectorType * PTy = cast < const VectorType > ( Ty ) ; return getSmallestAddressableSize ( PTy -> getElementType ( ) , GV , TM ) ; } case Type :: PointerTyID : case Type :: HalfTyID : case Type :: FloatTyID : case Type :: DoubleTyID : case Type :: IntegerTyID : { const DataLayout & DL = GV -> getParent ( ) -> getDataLayout ( ) ; return DL . getTypeAllocSize ( const_cast < Type * > ( Ty ) ) ; } case Type :: FunctionTyID : case Type :: VoidTyID : case Type :: BFloatTyID : case Type :: X86_FP80TyID : case Type :: FP128TyID : case Type :: PPC_FP128TyID : case Type :: LabelTyID : case Type :: MetadataTyID : case Type :: X86_MMXTyID : case Type


<s> assert ( V2 . getSimpleValueType ( ) == <STR_LIT> && <STR_LIT> ) ; assert ( Mask . size ( ) == <NUM_LIT> && <STR_LIT> ) ; if ( V2 . isUndef ( ) ) { if ( SDValue Broadcast = lowerShuffleAsBroadcast ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return Broadcast ; V1 = DAG . getBitcast ( <STR_LIT> , V1 ) ; int WidenedMask [ <NUM_LIT> ] = { std :: max ( Mask [ <NUM_LIT> ] , <NUM_LIT> ) * <NUM_LIT> , std :: max ( Mask [ <NUM_LIT> ] , <NUM_LIT> ) * <NUM_LIT> + <NUM_LIT> , std :: max ( Mask [ <NUM_LIT> ] , <NUM_LIT> ) * <NUM_LIT> , std :: max ( Mask [ <NUM_LIT> ] , <NUM_LIT> ) * <NUM_LIT> + <NUM_LIT> } ; return DAG . getBitcast ( <STR_LIT> , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , getV4<ISA_LIT>ShuffleImm8ForMask ( WidenedMask , DL , DAG ) ) ) ; } assert ( Mask [ <NUM_LIT> ] != - <NUM_LIT> && <STR_LIT> ) ; assert ( Mask [ <NUM_LIT> ] != - <NUM_LIT> && <STR_LIT> ) ; assert ( Mask [ <NUM_LIT> ] < <NUM_LIT> && <STR_LIT>


<s> if ( ( * iptr & <NUM_LIT> ) == <NUM_LIT> ) break ; } if ( i == NOFFSETS ) return ~ <NUM_LIT> ; iptr += SIGN_EXTEND ( GET_FIELD ( * iptr , <NUM_LIT> , <NUM_LIT> ) | GET_FIELD ( * iptr , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> | GET_FIELD ( * iptr , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> | GET_FIELD ( * iptr , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> , <NUM_LIT> ) ; fixup_plabel [ <NUM_LIT> ] = ( unsigned int ) iptr + <NUM_LIT> ; fixup_plabel [ <NUM_LIT> ] = got [


<s> bool SelectInlineAsmMemoryOperand ( const SDValue & Op , char ConstraintCode , std :: vector < SDValue > & OutOps ) override { const TargetRegisterInfo * TRI = TM . getRegisterInfo ( ) ; const TargetRegisterClass * TRC = TRI -> getPointerRegClass ( * MF , <NUM_LIT> ) ; SDValue RC = CurDAG -> getTargetConstant ( TRC -> getID ( ) , <STR_LIT> ) ; SDValue NewOp = SDValue ( CurDAG -> getMachineNode ( TargetOpcode :: COPY_TO_REGCLASS , SDLoc ( Op ) , Op . getValueType ( ) , Op ,


<s> case FK_Data_1 : return <NUM_LIT> ; case FK_PCRel_2 : case FK_Data_2 : return <NUM_LIT> ; case FK_PCRel_4 : case FK_Data_4 :


<s> LLVM_EXTERNAL_VISIBILITY void LLVMInitialize<ISA_LIT>Target ( ) { RegisterTargetMachine < <ISA_LIT>TargetMachine > X ( getThe<ISA_LIT>_32Target ( ) ) ; RegisterTargetMachine < <ISA_LIT>TargetMachine > Y ( getThe<ISA_LIT>_64Target ( ) ) ; PassRegistry & PR = * PassRegistry :: getPassRegistry ( ) ; initializeGlobalISel ( PR ) ; initializeWinEHStatePassPass ( PR ) ; initializeFixupBWInstPassPass ( PR )


<s> MIB = BuildMI ( MBB , std :: next ( I ) , MI -> getDebugLoc ( ) , TII . get ( <STR_LIT> ) ) . addReg ( Divisor . getReg ( ) , getKillRegState ( Divisor . isKill ( ) ) ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ; if ( Is64Bit ) MIB -> getOperand ( <NUM_LIT> ) . setSubReg ( <STR_LIT> ) ; Divisor . setIsKill ( false ) ; return & MBB


<s> FunctionPass * llvm :: create<ISA_LIT>DebuggerInsertNopsPass ( ) { return new <ISA_LIT>DebuggerInsertNops (


<s> ModulePass * create<ISA_LIT>ClonerPass ( ) { return new <ISA_LIT>Cloner


<s> void getAnalysisUsage ( AnalysisUsage & AU )


<s> for ( const std :: pair < unsigned , RegisterCell > P : Map ) dbgs ( ) << printReg ( P . first , & ME . TRI ) << <STR_LIT>


<s> static MCDisassembler * create<ISA_LIT>Disassebler ( const Target & T , const MCSubtargetInfo & STI , MCContext & Ctx ) { return new <ISA_LIT>Disassembler ( STI , Ctx


<s> if ( ( ( VT != <STR_LIT> ) || ( InVT != <STR_LIT> ) ) && ( ( VT != <STR_LIT> ) || ( InVT != <STR_LIT> ) ) ) return SDValue ( ) ; if ( Subtarget -> hasInt256 ( ) ) return DAG . getNode ( <STR_LIT> , dl , VT , In ) ; SDValue ZeroVec = getZeroVector ( InVT , Subtarget , DAG , dl ) ; SDValue Undef = DAG . getUNDEF ( InVT ) ; bool NeedZero = Op . getOpcode ( ) == <STR_LIT> ; SDValue OpLo = getUnpackl ( DAG , dl , InVT , In , NeedZero ? ZeroVec : Undef ) ; SDValue OpHi = getUnpackh ( DAG , dl , InVT , In , NeedZero ? ZeroVec : Undef ) ; EVT HVT = EVT :: getVectorVT ( * DAG . getContext ( ) , VT . getVectorElementType ( ) , VT . getVectorNumElements ( ) / <NUM_LIT> ) ; OpLo = DAG . getNode ( <STR_LIT> , dl , HVT , OpLo ) ; OpHi = DAG . getNode ( <STR_LIT> , dl , HVT , OpHi ) ; return DAG . getNode ( <STR_LIT> , dl


<s> switch ( Op . getOpcode ( ) ) { case <STR_LIT> : return LowerFixedLengthReductionToSVE ( <STR_LIT> , Op , DAG ) ; case <STR_LIT> : return LowerFixedLengthReductionToSVE ( <STR_LIT> , Op , DAG ) ; case <STR_LIT> : return LowerFixedLengthReductionToSVE ( <STR_LIT> , Op , DAG ) ; case <STR_LIT> : return LowerFixedLengthReductionToSVE ( <STR_LIT> , Op , DAG ) ; case <STR_LIT> : return LowerFixedLengthReductionToSVE ( <STR_LIT> , Op , DAG ) ; case <STR_LIT> : return LowerFixedLengthReductionToSVE ( <STR_LIT> , Op , DAG ) ; case <STR_LIT> : return LowerFixedLengthReductionToSVE ( <STR_LIT> , Op , DAG ) ; case <STR_LIT> : return LowerFixedLengthReductionToSVE ( <STR_LIT> , Op , DAG ) ; case <STR_LIT> : return LowerFixedLengthReductionToSVE ( <STR_LIT> , Op , DAG ) ; default : llvm_unreachable ( <STR_LIT> ) ; } } SDLoc dl ( Op ) ; switch ( Op . getOpcode ( ) ) { case <STR_LIT> : return getReductionSDNode ( <STR_LIT> , dl ,


<s> unsigned getExplicitKernelArgOffset ( const MachineFunction & MF ) const { return isAmdCodeObjectV2 ( MF )


<s> const char * getPassName ( ) const override { return <STR_LIT>


<s> Mask = DAG . getNode ( <STR_LIT> , DL , MaskVT , X , Mask . getOperand ( <NUM_LIT> ) ) ; return DAG . getBitcast ( VT , Mask ) ; } if ( ! Subtarget -> hasSSE41 ( ) ) return SDValue ( ) ; MVT BlendVT = ( VT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; X = DAG . getBitcast ( BlendVT , X ) ; Y = DAG . getBitcast ( BlendVT , Y ) ; Mask = DAG . getBitcast ( BlendVT , Mask ) ; Mask = DAG . getNode ( <STR_LIT> , DL , BlendVT , Mask , Y , X ) ; return DAG . getBitcast ( VT , Mask ) ; } } if ( VT != <STR_LIT> && VT != <STR_LIT> && VT != <STR_LIT> ) return SDValue ( ) ; bool OptForSize = DAG . getMachineFunction ( ) . getFunction ( ) -> optForSize ( ) ; if ( ! OptForSize && Subtarget -> isSHLDSlow ( ) ) return SDValue ( ) ; if ( N0 . getOpcode ( ) == <STR_LIT> && N1 . getOpcode ( ) == <STR_LIT> ) std :: swap ( N0 , N1 ) ; if ( N0 . getOpcode ( ) != <STR_LIT> || N1 . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; if ( ! N0 . hasOneUse ( ) || ! N1 . hasOneUse ( ) ) return SDValue ( ) ; SDValue ShAmt0 = N0 . getOperand ( <NUM_LIT> ) ; if ( ShAmt0 . getValueType ( ) != <STR_LIT> ) return SDValue ( ) ; SDValue ShAmt1 = N1 . getOperand ( <NUM_LIT> ) ; if ( ShAmt1 . getValueType ( ) != <STR_LIT> ) return SDValue ( ) ; if ( ShAmt0 . getOpcode ( ) == <STR_LIT> ) ShAmt0 = ShAmt0 . getOperand ( <NUM_LIT> ) ; if ( ShAmt1 . getOpcode ( ) == <STR_LIT> ) ShAmt1 = ShAmt1 . getOperand ( <NUM_LIT> ) ; SDLoc DL ( N ) ; unsigned Opc = <STR_LIT> ; SDValue Op0 = N0 . getOperand ( <NUM_LIT> ) ; SDValue Op1 = N1 . getOperand ( <NUM_LIT> ) ; if ( ShAmt0 . getOpcode ( ) == <STR_LIT> ) { Opc = <STR_LIT>


<s> unsigned getMinPrefetchStride ( unsigned NumMemAccesses , unsigned NumStridedMemAccesses , unsigned NumPrefetches , bool HasCall ) const override { return MinPrefetchStride


<s> ConstantInt * ValConst = dyn_cast_or_null < ConstantInt > ( NodeVal -> getValue ( ) ) ; if ( ValConst && NodeName -> getString ( ) == LiteralName ) { return ValConst -> getZExtValue ( ) ; } } report_fatal_error ( <STR_LIT> + LiteralName


<s> bool <ISA_LIT>CallLowering :: lowerFormalArguments ( MachineIRBuilder & MIRBuilder , const Function & F , ArrayRef <

ArrayRef < Register >> VRegs , FunctionLoweringInfo & FLI ) const {


<s> static DecodeStatus DecodeVecShiftL32Imm ( llvm :: MCInst & Inst , unsigned Imm , uint64_t


<s> if ( WavesPerEU >= getMaxWavesPerEU ( ) ) return <NUM_LIT> ; unsigned MinNumSGPRs = getTotalNumSGPRs ( Features ) / ( WavesPerEU + <NUM_LIT> ) ; if ( Features . test ( FeatureTrapHandler ) ) MinNumSGPRs -= std :: min ( MinNumSGPRs , ( unsigned ) TRAP_NUM_SGPRS ) ; MinNumSGPRs = alignDown ( MinNumSGPRs , getSGPRAllocGranule (


<s> } rtx ccset = gen_rtx_SET ( ccreg , gen_rtx_COMPARE ( CCmode , src , const0_rtx ) ) ; if ( dot == <NUM_LIT> ) { rtx clobber = gen_rtx_CLOBBER ( VOIDmode , dst ) ; emit_insn ( gen_rtx_PARALLEL ( VOIDmode , gen_rtvec (


<s> MachineInstr * BMI = & MBB -> back ( ) ; bool NeedSplit = ( BMI != MI ) || ! BBHasFallthrough ( MBB ) ; ++ NumCBrFixed ; if ( BMI != MI ) { if ( llvm :: next ( MachineBasicBlock :: iterator ( MI ) ) == prior ( MBB -> end ( ) ) && BMI -> getOpcode ( ) == Br . UncondBr ) { MachineBasicBlock * NewDest = BMI -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; if ( BBIsInRange ( MI , NewDest , Br . MaxDisp ) ) { DEBUG ( dbgs ( ) << <STR_LIT> << * BMI ) ; BMI -> getOperand ( <NUM_LIT> ) . setMBB ( DestBB ) ; MI -> getOperand ( <NUM_LIT> ) . setMBB ( NewDest ) ; MI -> getOperand ( <NUM_LIT> ) . setImm ( CC ) ; return true ; } } } if ( NeedSplit ) { SplitBlockBeforeInstr ( MI ) ; int delta = TII -> GetInstSizeInBytes ( & MBB -> back ( ) ) ; BBInfo [ MBB -> getNumber ( ) ] . Size -= delta ; MBB -> back ( ) . eraseFromParent ( ) ; } MachineBasicBlock * NextBB = llvm :: next ( MachineFunction :: iterator ( MBB ) ) ; DEBUG ( dbgs ( ) << <STR_LIT> << DestBB -> getNumber ( ) << <STR_LIT> << NextBB -> getNumber ( ) << <STR_LIT> ) ; BuildMI ( MBB , DebugLoc ( ) , TII -> get ( MI -> getOpcode ( ) ) ) . addMBB ( NextBB ) . addImm ( CC ) . addReg ( CCReg ) ; Br . MI = & MBB -> back ( ) ; BBInfo [ MBB -> getNumber ( ) ] . Size += TII -> GetInstSizeInBytes ( & MBB -> back ( ) ) ; if ( isThumb ) BuildMI ( MBB , DebugLoc ( ) , TII -> get ( Br . UncondBr ) ) . addMBB ( DestBB ) . addImm ( <STR_LIT> ) . addReg ( <NUM_LIT> ) ; else BuildMI ( MBB , DebugLoc ( ) , TII -> get ( Br . UncondBr ) ) . addMBB ( DestBB ) ; BBInfo [ MBB -> getNumber ( ) ] . Size += TII -> GetInstSizeInBytes ( & MBB -> back ( ) ) ; unsigned MaxDisp = getUnconditionalBrDisp ( Br . UncondBr ) ; ImmBranches . push_back ( ImmBranch ( & MBB -> back ( ) , MaxDisp , false , Br . UncondBr ) ) ; BBInfo [ MI -> getParent ( ) -> getNumber ( ) ] . Size -= TII -> GetInstSizeInBytes ( MI ) ; MI -> eraseFromParent ( )


<s> if ( ! Cond [ <NUM_LIT> ] . isImm ( ) ) return true ; <STR_LIT> CC = static_cast < <STR_LIT> > ( Cond [ <NUM_LIT> ] . getImm ( ) ) ; switch ( CC ) { default : return true ; case <STR_LIT> : CC = <STR_LIT> ; break ; case <STR_LIT> : CC = <STR_LIT> ; break ; case <STR_LIT>


<s> bool IsStrict = Op -> isStrictFPOpcode ( ) ; SDValue In = Op . getOperand ( IsStrict ? <NUM_LIT> : <NUM_LIT> ) ; if ( In . getSimpleValueType ( ) != <STR_LIT>


<s> else OutStreamer . EmitRawText ( StringRef ( <STR_LIT> ) ) ; } } if ( OutStreamer . hasRawTextSupport ( ) ) OutStreamer .


<s> PredicateInstruction ( MachineInstr * MI , const SmallVectorImpl < MachineOperand > & Pred ) const { assert ( Pred . size ( ) == <NUM_LIT> && <STR_LIT> ) ; unsigned CCValid = Pred [ <NUM_LIT> ] . getImm ( ) ; unsigned CCMask = Pred [ <NUM_LIT> ] . getImm ( ) ; assert ( CCMask > <NUM_LIT> && CCMask < <NUM_LIT> && <STR_LIT> ) ; unsigned Opcode = MI -> getOpcode ( ) ; if ( STI . hasLoadStoreOnCond (


<s> unsigned Dest = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Src1 = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( ( ( Dest == <STR_LIT> || Src1 == <STR_LIT> ) && ExtType == <STR_LIT> ) || ( (

Dest == <STR_LIT> || Src1 == <STR_LIT> ) && ExtType == <STR_LIT> ) ) {


<s> void <ISA_LIT>DAGToDAGISel :: SelectPostLoadLane ( SDNode * N , unsigned NumVecs , unsigned Opc ) { SDLoc dl ( N ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; bool Narrow = VT . getSizeInBits ( ) == <NUM_LIT> ; SmallVector < SDValue , <NUM_LIT> > Regs ( N -> op_begin ( ) + <NUM_LIT> , N -> op_begin ( ) + <NUM_LIT> + NumVecs ) ; if ( Narrow ) transform ( Regs , Regs . begin ( ) , WidenVector ( * CurDAG ) ) ; SDValue RegSeq = createQTuple ( Regs ) ; const EVT ResTys [ ] = { <STR_LIT> , RegSeq -> getValueType ( <NUM_LIT> ) , <STR_LIT> } ; unsigned LaneNo = cast < ConstantSDNode > ( N -> getOperand ( NumVecs + <NUM_LIT> ) ) -> getZExtValue ( ) ; SDValue Ops [ ] = { RegSeq , CurDAG -> getTargetConstant ( LaneNo , dl , <STR_LIT> ) , N -> getOperand ( NumVecs + <NUM_LIT> ) , N -> getOperand ( NumVecs + <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) } ; SDNode * Ld = CurDAG -> getMachineNode ( Opc , dl , ResTys , Ops ) ; ReplaceUses ( SDValue ( N , NumVecs ) , SDValue ( Ld , <NUM_LIT> ) ) ; SDValue SuperReg = SDValue ( Ld , <NUM_LIT> ) ; if ( NumVecs == <NUM_LIT> ) { ReplaceUses ( SDValue ( N , <NUM_LIT> ) , Narrow ? NarrowVector ( SuperReg , * CurDAG ) : SuperReg ) ; } else { EVT WideVT = RegSeq . getOperand ( <NUM_LIT> ) -> getValueType ( <NUM_LIT> ) ; static const unsigned QSubs [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; for ( unsigned i = <NUM_LIT> ; i < NumVecs ; ++ i ) { SDValue NV = CurDAG -> getTargetExtractSubreg ( QSubs [ i ] , dl , WideVT , SuperReg ) ; if ( Narrow ) NV = NarrowVector ( NV , * CurDAG ) ; ReplaceUses ( SDValue ( N , i ) , NV ) ; } } ReplaceUses ( SDValue ( N , NumVecs + <NUM_LIT> ) , SDValue ( Ld , <NUM_LIT> ) ) ; CurDAG -> RemoveDeadNode ( N


<s> __v4sf a , b , c ; a = vec_splat ( ( __v4sf ) __A , <NUM_LIT> ) ; b = vec_splat ( ( __v4sf ) __B


<s> if ( ! HBS :: isTransparentCopy ( R , Inp , MRI ) ) continue ; if ( ! HBS :: isEqual ( InpRC , B , RC , <NUM_LIT> , W ) ) continue ; Out . Reg = R ; Out . Sub = <NUM_LIT> ; return true ; } if ( W * <NUM_LIT> != RW ) continue ; if ( MRI . getRegClass ( R ) != & <STR_LIT> ) continue ; if ( HBS :: isEqual ( InpRC , B , RC , <NUM_LIT> , W ) ) Out . Sub = <STR_LIT> ; else if ( HBS :: isEqual ( InpRC , B , RC , W , W ) ) Out . Sub = <STR_LIT> ; else continue ; Out . Reg


<s> MachineFunction & MF = * BB -> getParent ( ) ; DebugLoc DL = MI . getDebugLoc ( ) ; const TargetInstrInfo & TII = * MF . getSubtarget ( ) . getInstrInfo ( ) ; const TargetRegisterInfo * RI = MF . getSubtarget ( ) . getRegisterInfo ( ) ; Register DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register LoReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register HiReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; const TargetRegisterClass * DstRC = & <STR_LIT> ; int FI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) -> getMoveF64FrameIndex ( ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( MF , FI ) , MachineMemOperand :: MOStore , <NUM_LIT> , Align ( <NUM_LIT> ) ) ; BuildMI ( * BB , MI , DL , TII . get ( <STR_LIT> ) ) . addReg ( LoReg , getKillRegState ( MI . getOperand ( <NUM_LIT> ) . isKill ( ) ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ; BuildMI ( * BB , MI , DL , TII . get ( <STR_LIT> ) ) . addReg ( HiReg , getKillRegState ( MI . getOperand ( <NUM_LIT> ) . isKill ( ) ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ; TII . loadRegFromStackSlot ( * BB , MI , DstReg , FI ,


<s> if ( Rs >= Rt ) { MI . setOpcode ( <STR_LIT> ) ; MI . addOperand ( MCOperand :: createReg ( getReg ( Decoder , <STR_LIT> , Rt ) ) ) ; MI . addOperand ( MCOperand :: createReg ( getReg ( Decoder , <STR_LIT> , Rs ) ) ) ; } else if ( Rs != <NUM_LIT> && Rs < Rt ) { MI . setOpcode ( <STR_LIT> ) ; MI . addOperand ( MCOperand :: createReg ( getReg ( Decoder , <STR_LIT> , Rs ) ) ) ; MI . addOperand ( MCOperand :: createReg ( getReg ( Decoder , <STR_LIT> , Rt ) ) ) ; } else { MI . setOpcode ( <STR_LIT>


<s> static tree visium_handle_interrupt_attr ( tree * node , tree name , tree args ATTRIBUTE_UNUSED , int flags ATTRIBUTE_UNUSED , bool * no_add_attrs ) { if ( TREE_CODE ( * node ) != FUNCTION_DECL ) { warning ( OPT_Wattributes , <STR_LIT> , name ) ; * no_add_attrs = true ; } else if ( ! TARGET_SV_MODE ) { error ( <STR_LIT> ) ; * no_add_attrs = true ; } return NULL_TREE


<s> if ( ! strict_p ) return true ; regno = reg_renumber [ regno ] ; } if ( regno == ARG_POINTER_REGNUM || regno


<s> mips_va_arg ( valist , type ) { \ if ( TARGET_MIPS16 ) \ sorry ( <STR_LIT> ) ; \ fprintf ( FILE , <STR_LIT> ) ; \ fprintf ( FILE , <STR_LIT> , \ reg_names [ GP_REG_FIRST + <NUM_LIT> ] , reg_names [ GP_REG_FIRST + <NUM_LIT> ] ) ; \ fprintf ( FILE , \ <STR_LIT> , \ TARGET_64BIT ? <STR_LIT> : <STR_LIT> , \ reg_names [ STACK_POINTER_REGNUM ] , \ reg_names [ STACK_POINTER_REGNUM ] , \ Pmode

== DImode ? <NUM_LIT> : <NUM_LIT> ) ; \ fprintf ( FILE , <STR_LIT> ) ; \ fprintf ( FILE , <STR_LIT> ) ; \ }


<s> <ISA_LIT>MCExpr :: VariantKind VK = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ; int64_t Imm ; bool IsValid ; if ( ! isImm ( ) ) return false ; bool IsConstantImm = evaluateConstantImm ( getImm ( ) , Imm , VK ) ; if ( ! IsConstantImm ) IsValid = <ISA_LIT>AsmParser :: classifySymbolRef ( getImm ( )


<s> getMachineOpValue ( const MCInst & MI , const MCOperand & MO , SmallVectorImpl < MCFixup > & Fixups ) const { if ( MO . isReg ( ) ) return Ctx . getRegisterInfo ( ) -> getEncodingValue ( MO . getReg ( ) ) ; if ( MO . isImm ( ) ) return static_cast < uint64_t > ( MO . getImm ( ) ) ; llvm_unreachable ( <STR_LIT> )


<s> Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; if ( ReserveAppRegisters ) Reserved . set ( <STR_LIT> ) ; if ( ReserveAppRegisters || ! Subtarget . is64Bit ( ) ) Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set