<s> break ; case <STR_LIT> : case <STR_LIT> : if ( ( VT == <STR_LIT> && C != <NUM_LIT> && isLegalArithImmed ( ( uint32_t ) ( C + <NUM_LIT> ) ) ) || ( VT == <STR_LIT> && C != <NUM_LIT> && isLegalArithImmed ( C + <NUM_LIT> ) ) ) { CC = ( CC == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; C = ( VT == <STR_LIT> ) ? ( uint32_t ) ( C + <NUM_LIT> ) : C + <NUM_LIT> ; RHS = DAG . getConstant ( C , VT ) ; } break ; case <STR_LIT> : case <STR_LIT> : if ( ( VT == <STR_LIT> && C != <NUM_LIT> && isLegalArithImmed ( ( uint32_t ) ( C + <NUM_LIT> ) ) ) || ( VT == <STR_LIT> && C != <NUM_LIT> && isLegalArithImmed ( C + <NUM_LIT> ) ) ) { CC = ( CC == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; C = ( VT == <STR_LIT> ) ? ( uint32_t ) ( C + <NUM_LIT> ) : C + <NUM_LIT> ; RHS = DAG . getConstant ( C , VT ) ; } break ; } } } if ( ( CC == <STR_LIT> || CC == <STR_LIT> ) && isa < ConstantSDNode > ( RHS ) ) { if ( ( cast < ConstantSDNode > ( RHS ) -> getZExtValue ( ) >> <NUM_LIT> == <NUM_LIT> ) && isa < LoadSDNode > ( LHS ) ) { if ( cast < LoadSDNode > ( LHS ) -> getExtensionType ( ) == <STR_LIT> && cast < LoadSDNode > ( LHS ) -> getMemoryVT ( ) == <STR_LIT> && LHS . getNode ( ) -> hasNUsesOfValue ( <NUM_LIT> , <NUM_LIT> ) ) { int16_t ValueofRHS = cast < ConstantSDNode > ( RHS ) -> getZExtValue ( ) ; if ( ValueofRHS < <NUM_LIT> && isLegalArithImmed ( - ValueofRHS ) ) { SDValue SExt = DAG . getNode ( <STR_LIT> , dl , LHS . getValueType ( ) , LHS , DAG . getValueType ( <STR_LIT> ) ) ; Cmp = emitComparison ( SExt , DAG . getConstant ( ValueofRHS , RHS . getValueType ( ) ) , CC , dl , DAG ) ; <ISA_LIT>CC = changeIntCCTo<ISA_LIT>CC ( CC ) ; <ISA_LIT>cc = DAG . getConstant ( <ISA_LIT>CC , <STR_LIT> ) ; return Cmp ; } } } } Cmp = emitComparison ( LHS , RHS , CC , dl , DAG ) ; <ISA_LIT>CC = changeIntCCTo<ISA_LIT>CC ( CC ) ; <ISA_LIT>cc = DAG . getConstant ( <ISA_LIT>CC ,


<s> } const TargetRegisterClass * RegClass = MRI -> getRegClass ( PHIDest ) ; unsigned NewDestReg = MRI -> createVirtualRegister ( RegClass ) ; LRegion -> replaceRegisterInsideRegion ( PHIDest , NewDestReg , false , MRI ) ; MachineInstrBuilder MIB = BuildMI ( * EntrySucc , EntrySucc -> instr_begin ( ) , PHI . getDebugLoc ( ) , TII -> get ( TargetOpcode :: PHI ) , NewDestReg ) ; DEBUG ( dbgs ( ) << <STR_LIT> << PrintReg ( NewDestReg , TRI ) << <STR_LIT> ) ; MIB . addReg ( PHISource ) ; MIB . addMBB ( Entry ) ; DEBUG ( dbgs ( ) << PrintReg ( PHISource , TRI ) << <STR_LIT> << Entry -> getNumber ( ) ) ; MIB . addReg ( RegionSourceReg ) ; MIB . addMBB (


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { if ( SNaN ) return true ; return false ; } case <STR_LIT> : case <STR_LIT> : { if ( SNaN ) return true ; return DAG . isKnownNeverNaN ( Op . getOperand ( <NUM_LIT> ) , SNaN , Depth + <NUM_LIT> ) ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return SNaN ; case <STR_LIT> : case <STR_LIT> : { return SNaN ; } case <STR_LIT> : { unsigned IntrinsicID = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; switch ( IntrinsicID ) { case <STR_LIT> : return true ; case <STR_LIT> : { if ( SNaN ) return true ; return DAG . isKnownNeverNaN ( Op . getOperand ( <NUM_LIT> ) , SNaN , Depth + <NUM_LIT> ) ; } case <STR_LIT> : { if ( SNaN )


<s> bool Filler :: runOnMachineBasicBlock ( MachineBasicBlock & MBB ) { bool Changed = false ; for ( MachineBasicBlock :: iterator I = MBB . begin ( ) ; I != MBB . end ( ) ; ++ I ) if ( I -> getDesc ( ) . hasDelaySlot ( ) ) { MachineBasicBlock :: iterator J


<s> const char * directive = I -> isDeclaration ( ) ? TAI -> getExternDirective ( ) : TAI -> getGlobalDirective ( ) ; O << directive << Name << <STR_LIT> ; O << directive << PAN :: getRetvalLabel ( Name ) << <STR_LIT> ; O << directive << PAN :: getArgsLabel ( Name ) << <STR_LIT> ; } O << TAI -> getCommentString ( ) << <STR_LIT>


<s> if ( Subtarget -> hasMVEIntegerOps ( ) ) { SDValue N0 = N -> getOperand ( <NUM_LIT> ) ; SDValue N1 = N -> getOperand ( <NUM_LIT> ) ; const TargetLowering * TLI = Subtarget -> getTargetLowering ( ) ; if ( TLI -> isConstTrueVal ( N1 . getNode ( ) ) && ( N0 -> getOpcode ( ) == <STR_LIT> || N0 -> getOpcode ( ) == <STR_LIT> ) ) { if ( CanInvertMVEVCMP ( N0 ) ) { SDLoc DL ( N0 ) ; <STR_LIT> CC = <STR_LIT> ( getVCMPCondCode ( N0 ) ) ; SmallVector < SDValue , <NUM_LIT> >


<s> if ( MI . memoperands_empty ( ) ) return true ; for ( const MachineMemOperand * Memop : MI . memoperands ( ) ) { unsigned AS = Memop -> getAddrSpace


<s> unsigned SplatBitSize ; bool HasAnyUndefs ; if ( BVN && BVN -> isConstantSplat ( SplatBits , SplatUndef , SplatBitSize , HasAnyUndefs ) ) { if ( SplatBitSize <= <NUM_LIT> ) { EVT VbicVT ; SDValue Val = isNEONModifiedImm ( ( ~ SplatBits ) . getZExtValue ( ) , SplatUndef . getZExtValue ( ) , SplatBitSize , DAG , VbicVT , VT . is128BitVector ( ) , OtherModImm ) ; if ( Val . getNode ( ) ) { SDValue Input = DAG . getNode ( <STR_LIT> , dl , VbicVT , N -> getOperand ( <NUM_LIT> ) ) ; SDValue Vbic = DAG . getNode ( <STR_LIT> , dl , VbicVT


<s> if ( IsVarArg ) { report_fatal_error ( <STR_LIT> ) ; } SmallVector < CCValAssign , <NUM_LIT> > RVLocs ; CCState CCInfo ( CallConv , IsVarArg , DAG . getMachineFunction ( ) , RVLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeReturn ( Outs , RetCC_<ISA_LIT> ) ; SDValue Flag ; SmallVector < SDValue , <NUM_LIT> > RetOps ( <NUM_LIT> , Chain ) ; for ( unsigned i = <NUM_LIT> , e = RVLocs . size ( ) ; i < e ; ++ i ) { CCValAssign & VA = RVLocs [ i


<s> if ( KnownBits < LogAlign ) return ( <NUM_LIT> << LogAlign ) - ( <NUM_LIT> << KnownBits ) ; return


<s> static const MCPhysReg RegList1 [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; static const MCPhysReg RegList2 [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; static const MCPhysReg WebKitRegList1 [ ] = { <STR_LIT> } ; static const MCPhysReg WebKitRegList2 [ ] = { <STR_LIT> } ; const MCPhysReg * List1 = IsWebKitJS ? WebKitRegList1 : RegList1 ; const MCPhysReg * List2 = IsWebKitJS ? WebKitRegList2 : RegList2 ; if ( unsigned Reg = State . AllocateReg ( List1 , List2 , <NUM_LIT> ) ) { if ( ValVT != <STR_LIT> ) { if ( ArgFlags . isSExt ( ) ) LocInfo = CCValAssign :: SExt ; else if ( ArgFlags . isZExt ( ) ) LocInfo = CCValAssign :: ZExt ; else LocInfo = CCValAssign :: AExt ; ValVT = <STR_LIT> ; } LocVT = <STR_LIT> ; State . addLoc ( CCValAssign :: getReg ( ValNo , ValVT , Reg , LocVT ,


<s> else if ( mode == TImode || ( TARGET_NEON && VALID_NEON_STRUCT_MODE ( mode ) ) ) return <NUM_LIT> ; else if ( code == PLUS ) { rtx xop0 = XEXP ( x , <NUM_LIT> ) ; rtx xop1 = XEXP ( x , <NUM_LIT> ) ; return ( ( arm_address_register_rtx_p ( xop0 , strict_p ) && ( thumb2_legitimate_index_p ( mode , xop1 , strict_p ) || ( ! strict_p && will_be_in_index_register ( xop1 ) ) ) ) || ( arm_address_register_rtx_p ( xop1 , strict_p ) && thumb2_legitimate_index_p ( mode , xop0 , strict_p ) ) ) ; } else if ( can_avoid_literal_pool_for_label_p ( x ) ) return <NUM_LIT> ; else if ( GET_MODE_CLASS ( mode ) != MODE_FLOAT && code == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P ( x ) && ! ( flag_pic && symbol_mentioned_p ( get_pool_constant ( x ) )

&& ! pcrel_constant_p ( get_pool_constant ( x ) ) ) ) return <NUM_LIT> ;


<s> VT = LD -> getMemoryVT ( ) ; Alignment = LD -> getAlign ( ) ; isSEXTLoad = LD -> getExtensionType ( ) == <STR_LIT> ; } else if ( StoreSDNode * ST = dyn_cast < StoreSDNode > ( N ) ) { Ptr = ST -> getBasePtr ( ) ; VT = ST -> getMemoryVT ( ) ; Alignment = ST -> getAlign ( ) ; } else if ( MaskedLoadSDNode * LD = dyn_cast < MaskedLoadSDNode > ( N ) ) { Ptr = LD -> getBasePtr ( ) ; VT = LD -> getMemoryVT ( ) ; Alignment = LD -> getAlign ( ) ; isSEXTLoad = LD -> getExtensionType ( ) == <STR_LIT> ; IsMasked = true ; } else if ( MaskedStoreSDNode * ST = dyn_cast < MaskedStoreSDNode > ( N ) ) { Ptr = ST -> getBasePtr ( ) ; VT = ST -> getMemoryVT ( ) ; Alignment = ST -> getAlign ( ) ; IsMasked = true ; } else return false ; bool isInc ; bool isLegal = false ; if ( VT . isVector ( ) ) isLegal = Subtarget -> hasMVEIntegerOps ( ) && getMVEIndexedAddressParts ( Ptr . getNode ( ) , VT , Alignment , isSEXTLoad , IsMasked , Subtarget -> isLittle ( ) , Base , Offset , isInc , DAG ) ; else { if ( Subtarget -> isThumb2 ( ) ) isLegal = getT2IndexedAddressParts ( Ptr . getNode ( ) , VT , isSEXTLoad , Base ,


<s> unsigned SplatBitSize ; bool HasAnyUndefs ; if ( BVN -> isConstantSplat ( SplatBits , SplatUndef , SplatBitSize , HasAnyUndefs , ElemBitSize , true ) && SplatBitSize == ElemBitSize ) { SDValue Shift = DAG . getConstant ( SplatBits . getZExtValue ( ) & <NUM_LIT> , DL , <STR_LIT> ) ; return DAG . getNode ( ByScalar , DL , VT , Op0 , Shift ) ; } BitVector UndefElements ; SDValue Splat = BVN -> getSplatValue ( & UndefElements ) ; if ( Splat ) { SDValue Shift = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Splat ) ; return DAG . getNode ( ByScalar , DL , VT , Op0 ,


<s> rtx def_reg = SET_DEST ( PATTERN ( producer ) ) ; gcc_assert ( get_attr_type ( producer ) == TYPE_LOAD


<s> void <ISA_LIT>DbgInfo :: EndModule ( Module & M ) { if ( ! EmitDebugDirectives ) return ; EmitVarDebugInfo ( M ) ; if ( CurFile != <STR_LIT> ) OS .

EmitRawText ( StringRef ( <STR_LIT> ) ) ;


<s> return & InstrInfo -> getRegisterInfo


<s> bool <ISA_LIT>DAGToDAGISel :: SelectImmShifterOperand ( SDValue N , SDValue & BaseReg , SDValue & Opc , bool CheckProfitability ) { if ( DisableShifterOp ) return false ; if ( N . getOpcode ( ) == <STR_LIT> ) { unsigned PowerOfTwo = <NUM_LIT> ; SDValue NewMulConst ; if ( canExtractShiftFromMul ( N , <NUM_LIT> , PowerOfTwo , NewMulConst ) ) { replaceDAGValue ( N . getOperand ( <NUM_LIT> ) , NewMulConst ) ; BaseReg = N ; Opc = CurDAG -> getTargetConstant ( <STR_LIT> ( <STR_LIT> , PowerOfTwo ) , SDLoc ( N ) , <STR_LIT> ) ; return true ; } } <STR_LIT> ShOpcVal = <STR_LIT> ( N . getOpcode ( ) ) ; if ( ShOpcVal == <STR_LIT> ) return


<s> default : llvm_unreachable ( <STR_LIT> ) ; case MachineOperand :: MO_Register : { unsigned Reg = MO . getReg ( ) ; assert ( TargetRegisterInfo :: isPhysicalRegister ( Reg ) ) ; assert ( ! MO . getSubReg ( ) && <STR_LIT> ) ; if ( <STR_LIT> . contains ( Reg ) ) { const MachineFunction & MF = * MI -> getParent ( ) -> getParent ( ) ; const TargetRegisterInfo * TRI = MF . getSubtarget ( ) . getRegisterInfo ( ) ; Reg = TRI -> getSubReg ( Reg , <STR_LIT> ) ; } O << <ISA_LIT>InstPrinter :: getRegisterName ( Reg ) ; break ; } case MachineOperand :: MO_Immediate : { int64_t Imm = MO . getImm ( ) ; O << '#' ; if ( TF == <STR_LIT> ) O << <STR_LIT> ; else if ( TF == <STR_LIT> ) O << <STR_LIT> ; O << Imm ; break ; } case MachineOperand :: MO_MachineBasicBlock : MO . getMBB ( ) -> getSymbol ( ) -> print ( O , MAI ) ; return ; case MachineOperand :: MO_GlobalAddress : { const GlobalValue * GV = MO


<s> Value * <ISA_LIT>IREmitter :: visitVPERMV ( const SDNode * N ) { llvm_unreachable ( <STR_LIT> ) ;


<s> if ( startswith ( section_name , <STR_LIT> ) ) return true ; if ( startswith ( section_name , <STR_LIT> ) ) return true ; return false ; } size = int_size_in_bytes ( TREE_TYPE ( decl ) ) ; if ( size > <NUM_LIT> &&


<s> case <STR_LIT> : return true ; } if ( isCallIndirect ( MI ) ) return true ; if ( ! MI . isCall ( ) ) return false ; const MachineOperand & MO = MI . getOperand ( getCalleeOpNo ( MI ) ) ; assert ( MO . isGlobal ( ) ) ; const auto * F = dyn_cast < Function > ( MO . getGlobal ( ) ) ; if ( ! F ) return


<s> unsigned <ISA_LIT>MCCodeEmitter :: getTLSRegEncoding ( const MCInst & MI , unsigned OpNo , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { const MCOperand & MO = MI . getOperand ( OpNo ) ; if ( MO . isReg ( ) ) return getMachineOpValue ( MI , MO , Fixups , STI ) ; Fixups . push_back ( MCFixup :: create ( <NUM_LIT> , MO . getExpr ( ) , ( MCFixupKind ) <STR_LIT> ) ) ; const Triple & TT = STI . getTargetTriple ( ) ; bool is<ISA_LIT>64 = TT .


<s> if ( getOptLevel ( ) != CodeGenOpt :: None ) addPass ( create<ISA_LIT>ShortenInstPass ( get<ISA_LIT>TargetMachine ( ) ) ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) addPass ( create<ISA_LIT>ElimComparePass ( get<ISA_LIT>TargetMachine ( ) ) ) ; addPass ( create<ISA_LIT>LongBranchPass ( get<ISA_LIT>TargetMachine ( )


<s> } else if ( TARGET_MVCLE ) { val = force_not_mem ( convert_modes ( Pmode , QImode , val , <NUM_LIT> ) ) ; if ( TARGET_64BIT ) emit_insn ( gen_setmem_long_di ( dst , convert_to_mode ( Pmode , len , <NUM_LIT> ) , val ) ) ; else emit_insn ( gen_setmem_long_si ( dst , convert_to_mode ( Pmode , len , <NUM_LIT> ) , val ) ) ; } else { rtx dst_addr , count , blocks , temp , dstp1 = NULL_RTX ; rtx_code_label * loop_start_label = gen_label_rtx ( ) ; rtx_code_label * onebyte_end_label = gen_label_rtx ( ) ; rtx_code_label * zerobyte_end_label = gen_label_rtx ( ) ; rtx_code_label * restbyte_end_label = gen_label_rtx ( ) ; machine_mode mode ; mode = GET_MODE ( len ) ; if ( mode == VOIDmode ) mode = Pmode ; dst_addr = gen_reg_rtx ( Pmode ) ; count = gen_reg_rtx ( mode ) ; blocks = gen_reg_rtx ( mode ) ; convert_move ( count , len , <NUM_LIT> ) ; emit_cmp_and_jump_insns ( count , const0_rtx , EQ , NULL_RTX , mode , <NUM_LIT> , zerobyte_end_label , profile_probability :: very_unlikely ( ) ) ; emit_move_insn ( dst_addr , force_operand ( XEXP ( dst , <NUM_LIT> ) , NULL_RTX ) ) ; dst = change_address ( dst , VOIDmode , dst_addr ) ; if ( val != const0_rtx ) { set_mem_size ( dst , <NUM_LIT> ) ; dstp1 = adjust_address ( dst , VOIDmode , <NUM_LIT> ) ; emit_cmp_and_jump_insns ( count , const1_rtx , EQ , NULL_RTX , mode , <NUM_LIT> , onebyte_end_label , profile_probability :: very_unlikely ( ) ) ; } temp = expand_binop ( mode , add_optab , count , val == const0_rtx ? constm1_rtx : GEN_INT ( - <NUM_LIT> ) , count , <NUM_LIT> , OPTAB_DIRECT ) ; if ( temp != count ) emit_move_insn ( count , temp ) ; temp = expand_binop ( mode , lshr_optab , count , GEN_INT ( <NUM_LIT> ) , blocks , <NUM_LIT> , OPTAB_DIRECT ) ; if ( temp != blocks ) emit_move_insn ( blocks , temp ) ; emit_cmp_and_jump_insns ( blocks , const0_rtx , EQ , NULL_RTX , mode , <NUM_LIT> , restbyte_end_label ) ; emit_jump ( loop_start_label ) ; if ( val != const0_rtx ) { emit_label ( onebyte_end_label ) ; emit_move_insn ( adjust_address ( dst , QImode , <NUM_LIT> ) , val ) ; emit_jump ( zerobyte_end_label ) ; } emit_label ( loop_start_label


<s> const <ISA_LIT>RegisterInfo & <ISA_LIT>SEInstrInfo :: getRegisterInfo ( )


<s> void <ISA_LIT>InstPrinter :: printInst ( const MCInst * MI ) { printInstruction ( MI


<s> <ISA_LIT>MCInst ( const MCInstrDesc & mcid ) : MCInst ( ) , MCID ( & mcid ) ,

packetStart ( <NUM_LIT> ) , packetEnd ( <NUM_LIT> ) { }


<s> vmull_high_u16 ( uint16x8_t a , uint16x8_t b ) { uint32x4_t result


<s> void eraseMatchingBitGroups ( function_ref < bool (


<s> return Lower<ISA_LIT>MachineOperandToMCOperand ( MO , MCOp , *


<s> <ISA_LIT>TargetMachine & get<ISA_LIT>TargetMachine ( ) const { return getTM < <ISA_LIT>TargetMachine > (


<s> unsigned ShiftAmt = SVOp -> getMaskElt ( i ) ; if ( ShiftAmt < i ) return - <NUM_LIT> ; ShiftAmt -= i ; if ( ! isUnary ) { for ( ++ i ; i != <NUM_LIT> ; ++ i ) if ( ! isConstantOrUndef ( SVOp -> getMaskElt ( i ) , ShiftAmt + i ) ) return - <NUM_LIT> ; } else { for ( ++ i ; i != <NUM_LIT> ; ++ i ) if ( ! isConstantOrUndef ( SVOp -> getMaskElt ( i ) , ( ShiftAmt + i ) & <NUM_LIT> ) ) return - <NUM_LIT> ; } return ShiftAmt


<s> else type_signature [ arg_num ] = 's' ; if ( qualifiers & qualifier_internal ) continue ; if ( qualifiers & qualifier_map_mode ) op_mode = d -> mode ; if ( qualifiers & qualifier_predicate ) op_mode = HImode ; if ( qualifiers & qualifier_pointer && VECTOR_MODE_P ( op_mode ) ) op_mode = GET_MODE_INNER ( op_mode ) ; if ( qualifiers & qualifier_void_pointer ) eltype = qualifiers & qualifier_const ? const_ptr_type_node : ptr_type_node ; else { eltype = arm_simd_builtin_type ( op_mode , qualifiers ) ; gcc_assert ( eltype != NULL ) ; if ( qualifiers & qualifier_const ) eltype = build_qualified_type ( eltype , TYPE_QUAL_CONST ) ; if ( qualifiers & qualifier_pointer ) eltype = build_pointer_type ( eltype ) ; } if ( arg_num == <NUM_LIT> ) return_type = eltype ; else args = tree_cons ( NULL_TREE , eltype


<s> switch ( ISDOpcode ) { default : return false ; case <STR_LIT> : case <STR_LIT> : DivOpc = <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : DivOpc = <STR_LIT> ; break ; } Register Src0Reg = getRegForValue ( I -> getOperand ( <NUM_LIT> ) ) ; Register Src1Reg = getRegForValue ( I -> getOperand ( <NUM_LIT> ) ) ; if ( ! Src0Reg || ! Src1Reg ) return false ; emitInst ( DivOpc ) . addReg ( Src0Reg ) . addReg ( Src1Reg ) ; emitInst ( <STR_LIT> ) . addReg ( Src1Reg ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ; Register ResultReg = createResultReg ( & <STR_LIT> ) ; if ( ! ResultReg ) return


<s> Data8bitsDirective = <STR_LIT> ; Data16bitsDirective = <STR_LIT> ; Data32bitsDirective = <STR_LIT> ; Data64bitsDirective = NULL ; ZeroDirective = NULL ; AsciiDirective = <STR_LIT> ; AscizDirective = NULL ; RomData8bitsDirective =


<s> if ( isPackedVectorType ( DataVT ) ) return splitPackedLoadStore ( Op , CDAG ) ; return legalizePackedAVL ( Op


<s> SDValue <ISA_LIT>TargetLowering :: LowerFRAMEADDR ( SDValue Op , SelectionDAG & DAG ) const { MachineFrameInfo * MFI = DAG . getMachineFunction ( ) . getFrameInfo ( ) ; MFI -> setFrameAddressIsTaken ( true ) ; EVT VT = Op . getValueType ( ) ; SDLoc dl ( Op ) ; unsigned Depth = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; const <ISA_LIT>RegisterInfo * RegInfo = static_cast < const <ISA_LIT>RegisterInfo * > ( getTargetMachine ( ) . getRegisterInfo ( ) ) ; unsigned FrameReg ; if ( Subtarget -> isTargetNaCl ( ) ) { FrameReg = Subtarget -> has64BitPointers ( ) ? <STR_LIT> : <STR_LIT> ; } else { FrameReg = RegInfo -> getFrameRegister ( DAG . getMachineFunction ( ) ) ; } assert ( ( ( FrameReg == <STR_LIT> && VT == <STR_LIT> ) || ( FrameReg == <STR_LIT> && VT == <STR_LIT> ) ) && <STR_LIT> ) ; SDValue FrameAddr = DAG . getCopyFromReg ( DAG . getEntryNode (


<s> unsigned Datasize = fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned ShifterVal = ( Imm >> <NUM_LIT> ) & <NUM_LIT> ; unsigned ImmVal = Imm & <NUM_LIT> ; const <ISA_LIT>Disassembler * Dis = static_cast < const <ISA_LIT>Disassembler * > ( Decoder ) ; if ( ShifterVal != <NUM_LIT> && ShifterVal != <NUM_LIT> ) return Fail ; if ( Datasize ) { if ( Rd == <NUM_LIT> && ! S ) DecodeGPR64spRegisterClass ( Inst , Rd , Addr , Decoder ) ; else DecodeGPR64RegisterClass ( Inst , Rd , Addr , Decoder ) ; DecodeGPR64spRegisterClass ( Inst , Rn , Addr , Decoder ) ; } else { if ( Rd == <NUM_LIT> && ! S ) DecodeGPR32spRegisterClass ( Inst ,


<s> unsigned long long res ; __asm__ ( <STR_LIT> : <STR_LIT> ( res ) : <STR_LIT> ( mm )


<s> bool isVectorRegLo ( ) const { return Kind == k_Register && Reg . Kind == RegKind :: NeonVector && <ISA_LIT>MCRegisterClasses

[ <STR_LIT> ] . contains ( Reg . RegNum ) ;


) _mm512_undefined_ps ( ) , ( __mmask16 ) - <NUM_LIT> , _MM_FROUND_CUR_DIRECTION ) ;


<s> void <ISA_LIT>FrameLowering :: processFunctionBeforeFrameFinalized ( MachineFunction & MF ) const { if ( hasFP ( MF ) ) { int FrameIdx = MF . getFrameInfo ( ) -> CreateFixedObject ( <NUM_LIT> , -


<s> getActionDefinitionsBuilder ( { G_LOAD , G_STORE } ) . legalForTypesWithMemDesc ( { { s32 , p0 , <NUM_LIT> , <NUM_LIT> } , { s32 , p0 , <NUM_LIT> , <NUM_LIT> } , { s32 , p0 , <NUM_LIT> , <NUM_LIT> } , { p0 , p0 , <NUM_LIT> , <NUM_LIT> } } ) . minScalar ( <NUM_LIT> , s32 ) ; getActionDefinitionsBuilder ( { G_ZEXTLOAD , G_SEXTLOAD } ) . legalForTypesWithMemDesc ( { { s32 , p0 , <NUM_LIT> , <NUM_LIT> } , { s32 , p0 , <NUM_LIT> , <NUM_LIT> } } ) . minScalar ( <NUM_LIT> , s32 ) ; getActionDefinitionsBuilder ( G_SELECT ) . legalForCartesianProduct ( { p0 , s32 } , { s32 } ) . minScalar ( <NUM_LIT> , s32 ) . minScalar ( <NUM_LIT> , s32 ) ; getActionDefinitionsBuilder ( G_BRCOND ) . legalFor ( { s32 } ) . minScalar ( <NUM_LIT> , s32 ) ; getActionDefinitionsBuilder ( G_PHI ) . legalFor ( { p0 , s32 } ) . minScalar ( <NUM_LIT> , s32 ) ; getActionDefinitionsBuilder ( { G_AND , G_OR , G_XOR } ) . legalFor ( { s32 } ) . clampScalar ( <NUM_LIT> , s32 , s32 ) ; getActionDefinitionsBuilder ( { G_SDIV , G_SREM , G_UREM , G_UDIV } ) . legalFor ( { s32 } ) . minScalar ( <NUM_LIT> , s32 ) . libcallFor ( { s64 } ) ; getActionDefinitionsBuilder ( { G_SHL , G_ASHR , G_LSHR } ) . legalFor ( { s32 , s32 } ) . minScalar ( <NUM_LIT> , s32 ) ; getActionDefinitionsBuilder ( G_ICMP ) . legalFor ( { { s32 , s32 } } ) . minScalar ( <NUM_LIT> , s32 ) ; getActionDefinitionsBuilder ( G_CONSTANT ) . legalFor ( { s32 } ) . clampScalar ( <NUM_LIT> , s32 , s32 ) ; getActionDefinitionsBuilder ( G_GEP ) . legalFor ( { { p0 , s32 } } ) ; getActionDefinitionsBuilder ( G_FRAME_INDEX ) . legalFor ( { p0 } ) ; getActionDefinitionsBuilder ( G_GLOBAL_VALUE ) . legalFor ( { p0 } ) ; getActionDefinitionsBuilder ( G_FCONSTANT ) . legalFor ( { s32 , s64 } ) ; getActionDefinitionsBuilder ( { G_FADD , G_FSUB , G_FMUL , G_FDIV , G_FABS , G_FSQRT } ) . legalFor ( { s32 , s64 } ) ; getActionDefinitionsBuilder ( G_FCMP ) . legalFor ( { { s32 , s32 } , { s32 , s64 } } ) . minScalar ( <NUM_LIT> , s32 ) ; getActionDefinitionsBuilder ( { G_FCEIL , G_FFLOOR } ) . libcallFor ( { s32 , s64 } ) ; getActionDefinitionsBuilder ( G_FPEXT ) . legalFor ( { { s64 , s32 } } ) ; getActionDefinitionsBuilder ( G_FPTRUNC ) . legalFor ( { { s32 ,


<s> } } } else if ( last >= <NUM_LIT> ) { int start ; for ( start = first >= <NUM_LIT> ? first : <NUM_LIT> ; start <= last ; start ++ ) if ( ! global_not_special_regno_p ( start ) ) break ; if ( start > last ) goto emit ; addr = plus_constant ( Pmode , base , offset + ( start - first ) * UNITS_PER_LONG ) ; if ( start == last ) { if ( TARGET_64BIT ) note = gen_movdi ( gen_rtx_MEM ( Pmode , addr ) , gen_rtx_REG ( Pmode , start ) ) ; else note = gen_movsi ( gen_rtx_MEM ( Pmode , addr ) , gen_rtx_REG ( Pmode , start ) ) ; note = PATTERN ( note ) ; add_reg_note ( insn , REG_FRAME_RELATED_EXPR , note ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; goto emit ; } note = gen_store_multiple ( gen_rtx_MEM ( Pmode , addr ) , gen_rtx_REG ( Pmode , start ) , GEN_INT ( last - start + <NUM_LIT> ) ) ; note = PATTERN ( note ) ; add_reg_note ( insn , REG_FRAME_RELATED_EXPR , note ) ; for ( i = <NUM_LIT> ; i < XVECLEN ( note , <NUM_LIT> ) ; i ++ ) if ( GET_CODE ( XVECEXP ( note , <NUM_LIT> , i ) ) == SET && ! global_not_special_regno_p ( REGNO ( SET_SRC ( XVECEXP ( note , <NUM_LIT> ,

i ) ) ) ) ) RTX_FRAME_RELATED_P ( XVECEXP ( note , <NUM_LIT> , i ) ) = <NUM_LIT> ;


<s> unsigned int <ISA_LIT>InstrInfo :: getPredicationCost ( const MachineInstr & ) const { return


<s> auto MIB = BuildMI ( MBB , MBBI , DL , get ( <STR_LIT> ) , DestReg ) ; if ( KillSrc ) { const MachineFunction * MF = MBB . getParent ( ) ; const TargetRegisterInfo * TRI = MF -> getSubtarget ( ) . getRegisterInfo ( ) ; MIB -> addRegisterKilled ( SrcReg , TRI ) ; } return ; } if ( DestReg == <STR_LIT> ) { BuildMI ( MBB , MBBI , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) . addImm ( <NUM_LIT> << ( <STR_LIT> - <NUM_LIT> ) ) ; return ; } unsigned Opcode ; if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opcode = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opcode = STI . hasVector ( ) ? <STR_LIT> : <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opcode = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opcode = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opcode = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opcode = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opcode = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opcode = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg ) && <STR_LIT> . contains (


<s> static const char * avr_out_store_psi ( rtx_insn * insn , rtx * op , int * plen ) { rtx dest = op [ <NUM_LIT> ] ; rtx src = op [ <NUM_LIT> ] ; rtx base = XEXP ( dest , <NUM_LIT> ) ; int reg_base = true_regnum ( base ) ; if ( CONSTANT_ADDRESS_P ( base ) ) { int n_words = AVR_TINY ? <NUM_LIT> : <NUM_LIT> ; return avr_asm_len ( <STR_LIT> CR_TAB <STR_LIT> CR_TAB <STR_LIT> , op , plen , - n_words ) ; } if ( reg_base > <NUM_LIT> ) { if ( AVR_TINY ) return avr_out_store_psi_reg_no_disp_tiny ( insn , op , plen ) ; if ( reg_base == REG_X ) { gcc_assert ( ! reg_overlap_mentioned_p ( base , src ) ) ; avr_asm_len ( <STR_LIT> CR_TAB <STR_LIT> CR_TAB <STR_LIT> , op , plen , - <NUM_LIT> ) ; if ( ! reg_unused_after ( insn , base ) ) avr_asm_len ( <STR_LIT> , op


<s> NewMIs . push_back ( addFrameReference ( BuildMI ( MF , DL , get ( <STR_LIT> ) ) . addReg ( <STR_LIT> , getKillRegState ( isKill ) ) , FrameIdx ) ) ; } } else if ( RC == <STR_LIT> ) { NewMIs . push_back ( addFrameReference ( BuildMI ( MF , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) , FrameIdx ) ) ; } else if ( RC == <STR_LIT> ) { NewMIs . push_back ( addFrameReference ( BuildMI ( MF , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) , FrameIdx ) ) ; } else if ( RC == <STR_LIT> ) { if ( ( Enable<ISA_LIT>32RS && ! TM . getSubtargetImpl ( ) -> is<ISA_LIT>64 ( ) ) || ( Enable<ISA_LIT>64RS && TM . getSubtargetImpl ( ) -> is<ISA_LIT>64 ( ) ) ) { NewMIs . push_back ( addFrameReference ( BuildMI ( MF , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) , FrameIdx ) ) ; return true ; } else { unsigned ScratchReg = TM . getSubtargetImpl ( ) -> isDarwinABI ( ) ? <STR_LIT> : <STR_LIT> ; NewMIs . push_back ( BuildMI ( MF , DL , get ( <STR_LIT> ) , ScratchReg ) ) ; if ( SrcReg != <STR_LIT> ) { unsigned ShiftBits = <ISA_LIT>RegisterInfo :: getRegisterNumbering ( SrcReg ) * <NUM_LIT> ; NewMIs . push_back ( BuildMI ( MF , DL , get ( <STR_LIT> ) , ScratchReg ) . addReg ( ScratchReg ) . addImm ( ShiftBits ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ) ; } NewMIs . push_back ( addFrameReference ( BuildMI ( MF , DL , get ( <STR_LIT> ) ) . addReg ( ScratchReg , getKillRegState ( isKill ) ) , FrameIdx ) ) ; } } else if ( RC == <STR_LIT> ) { unsigned Reg = <NUM_LIT> ; if ( SrcReg == <STR_LIT> || SrcReg == <STR_LIT> || SrcReg == <STR_LIT> || SrcReg == <STR_LIT> ) Reg = <STR_LIT> ; else if ( SrcReg == <STR_LIT> || SrcReg == <STR_LIT> || SrcReg == <STR_LIT> || SrcReg == <STR_LIT> ) Reg = <STR_LIT> ; else if ( SrcReg == <STR_LIT> || SrcReg == <STR_LIT> || SrcReg == <STR_LIT> || SrcReg == <STR_LIT> )


<s> static DecodeStatus DecodeVecShiftRImm ( llvm :: MCInst & Inst , unsigned Imm , unsigned Add ) { Inst . addOperand ( MCOperand :: CreateImm ( Add


<s> <ISA_LIT>LongBranch ( TargetMachine & tm ) : MachineFunctionPass ( ID ) , TM ( tm ) , IsPIC ( TM . getRelocationModel ( ) == Reloc :: PIC_ ) , ABI ( TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . getTargetABI (

) ) , LongBranchSeqSize ( ! IsPIC ? <NUM_LIT> : ( ABI == <ISA_LIT>Subtarget :: N64 ? <NUM_LIT> :


<s> switch ( Inst . getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true


<s> static DecodeStatus s12_0ImmDecoder ( MCInst & MI , unsigned

tmp , uint64_t , const void * Decoder ) {


<s> FunctionPass * llvm :: create<ISA_LIT>ISelDag ( TargetMachine * TM ,


<s> return Ty . isSimple ( ) && Subtarget . isHVXVectorType ( Ty . getSimpleVT ( ) , true ) ; } ; auto IsHvxOp = [ this ] ( SDValue Op ) { return Subtarget . isHVXVectorType ( ty ( Op ) , true ) ; } ; return llvm :: any_of ( N -> values ( ) , IsHvxTy ) || llvm ::


<s> for ( MachineBasicBlock :: iterator B = MBB -> begin ( ) ; I != B ; ) { -- I ; assert ( ! I -> isTerminator ( ) && <STR_LIT> ) ; switch ( I -> getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return I ; case <STR_LIT>


<s> if ( Reg < <STR_LIT> || Reg > <STR_LIT> ) return Reg ; unsigned RegNo = <NUM_LIT> ; for ( MCSubRegIterator SubRegs ( Reg , & TRI ) ; SubRegs . isValid ( ) ; ++ SubRegs ) { if ( hireg ) { if ( * SubRegs > RegNo ) RegNo = *


<s> int32_t OffImm = ( int32_t ) MO . getImm ( ) << scale ; O << markup ( <STR_LIT> ) ; if ( OffImm == INT32_MIN ) O << <STR_LIT> ; else if ( OffImm < <NUM_LIT> ) O << <STR_LIT> << - OffImm ; else O << <STR_LIT>


<s> Init<ISA_LIT>MCInstrInfo ( X ) ; return X


<s> if ( ( GET_CODE ( x ) == SYMBOL_REF ) && ( SYMBOL_REF_FLAGS ( x ) & SYMBOL_FLAG_FUNCVEC_FUNCTION ) ) { t = SYMBOL_REF_DECL ( x ) ; if ( TREE_CODE ( t ) != FUNCTION_DECL ) return <NUM_LIT> ; list = SH_ATTRIBUTES ( t ) ; while ( list


<s> const GlobalValue * GVal = MO . getGlobal ( ) ; auto * GVar = dyn_cast < GlobalVariable > ( GVal ) ; if ( GVar && GVar -> hasAttribute ( <STR_LIT> ) ) { MCSymbol * ORSym = OS . getContext ( ) . createTempSymbol


<s> void <ISA_LIT>InsertSkips :: kill ( MachineInstr & MI ) { MachineBasicBlock & MBB = * MI . getParent ( ) ; DebugLoc DL = MI . getDebugLoc ( ) ; const MachineOperand & Op = MI . getOperand ( <NUM_LIT> ) ; CallingConv :: ID CallConv = MBB . getParent ( ) -> getFunction ( ) -> getCallingConv ( ) ; assert ( CallConv == CallingConv :: <ISA_LIT>_PS || CallConv == CallingConv :: <ISA_LIT>_GS ) ; if ( Op . isImm ( ) ) { if ( Op . getImm (


<s> OS << <STR_LIT> << Attribute << <STR_LIT> <<


<s> if ( CSKY_FUNCTION_IS_INTERRUPT ( func_type ) ) return <STR_LIT> ; else return


<s> if ( TM . getDrvInterface ( ) == <STR_LIT> ) return ( SmVersion >= <NUM_LIT> ) ; return false


<s> static bool tilepro_legitimate_constant_p ( machine_mode mode ATTRIBUTE_UNUSED , rtx x ) { switch ( GET_CODE ( x ) ) { case CONST


<s> const TargetRegisterClass * Thumb1RegisterInfo :: getPointerRegClass ( unsigned Kind


<s> if ( Addr . getOpcode ( ) == <STR_LIT> ) RHSC = - RHSC ; Base = Addr . getOperand ( <NUM_LIT> ) ; Offset = CurDAG -> getTargetConstant ( RHSC , SDLoc ( Addr


<s> if ( isThumb2 ) { Register NewVReg1 = MRI -> createVirtualRegister ( TRC ) ; BuildMI ( * MBB , MI , dl , TII -> get ( <STR_LIT> ) , NewVReg1 ) . addConstantPoolIndex ( CPI ) . addMemOperand ( CPMMO ) . add ( predOps ( <STR_LIT> ) ) ; Register NewVReg2 = MRI -> createVirtualRegister ( TRC ) ; BuildMI ( * MBB , MI , dl , TII -> get ( <STR_LIT> ) , NewVReg2 ) . addReg ( NewVReg1 , RegState :: Kill ) . addImm ( <NUM_LIT> ) . add ( predOps ( <STR_LIT> ) ) . add ( condCodeOp ( ) ) ; Register NewVReg3 = MRI -> createVirtualRegister ( TRC ) ; BuildMI ( * MBB , MI , dl , TII -> get ( <STR_LIT> ) , NewVReg3 ) . addReg ( NewVReg2 , RegState :: Kill ) . addImm ( PCLabelId ) ; BuildMI ( * MBB , MI , dl , TII -> get ( <STR_LIT> ) ) . addReg ( NewVReg3 , RegState :: Kill ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( FIMMOSt ) . add ( predOps ( <STR_LIT> ) ) ; } else if ( isThumb ) { Register NewVReg1 = MRI -> createVirtualRegister ( TRC ) ; BuildMI ( * MBB , MI , dl , TII -> get ( <STR_LIT> ) , NewVReg1 ) . addConstantPoolIndex ( CPI ) . addMemOperand ( CPMMO ) . add ( predOps ( <STR_LIT> ) ) ; Register NewVReg2 = MRI -> createVirtualRegister ( TRC ) ; BuildMI ( * MBB , MI , dl , TII -> get ( <STR_LIT> ) , NewVReg2 ) . addReg ( NewVReg1 , RegState :: Kill ) . addImm ( PCLabelId ) ; Register NewVReg3 = MRI -> createVirtualRegister ( TRC ) ; BuildMI ( * MBB , MI , dl , TII -> get ( <STR_LIT> ) , NewVReg3 ) . addReg ( <STR_LIT> , RegState :: Define ) . addImm ( <NUM_LIT> ) . add ( predOps ( <STR_LIT> ) ) ; Register NewVReg4 = MRI -> createVirtualRegister ( TRC ) ; BuildMI ( * MBB , MI , dl , TII -> get ( <STR_LIT> ) , NewVReg4 ) . addReg ( <STR_LIT> , RegState :: Define ) . addReg ( NewVReg2 , RegState :: Kill ) . addReg ( NewVReg3 , RegState :: Kill ) . add ( predOps ( <STR_LIT> ) ) ; Register NewVReg5 = MRI -> createVirtualRegister ( TRC ) ; BuildMI ( * MBB , MI , dl , TII -> get ( <STR_LIT> ) , NewVReg5 ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) ; BuildMI ( * MBB , MI , dl , TII -> get ( <STR_LIT> ) ) . addReg ( NewVReg4 , RegState :: Kill ) . addReg ( NewVReg5 , RegState :: Kill ) . addImm ( <NUM_LIT> ) . addMemOperand ( FIMMOSt ) . add ( predOps ( <STR_LIT> ) ) ; }


<s> SDLoc dl ( Op ) ; assert ( ( ! N -> isCompressingStore ( ) || Subtarget . hasAVX512 ( ) ) && <STR_LIT> ) ; assert ( ( ! N -> isCompressingStore ( ) || ScalarVT . getSizeInBits ( ) >= <NUM_LIT> ) && <STR_LIT> ) ; assert ( Subtarget . hasAVX512 ( ) && ! Subtarget . hasVLX ( ) && ! VT . is512BitVector ( ) && <STR_LIT> ) ; assert ( ( ScalarVT . getSizeInBits ( ) >= <NUM_LIT> || ( Subtarget . hasBWI ( ) && ( ScalarVT == <STR_LIT> || ScalarVT == <STR_LIT> ) ) ) && <STR_LIT> ) ; unsigned NumEltsInWideVec = <NUM_LIT> / VT . getScalarSizeInBits ( ) ; MVT WideDataVT = <STR_LIT> ( ScalarVT , NumEltsInWideVec ) ; assert ( Mask . getSimpleValueType ( ) . getScalarType ( ) == <STR_LIT> && <STR_LIT> ) ; MVT WideMaskVT = <STR_LIT> ( <STR_LIT> , NumEltsInWideVec ) ; DataToStore = ExtendToType ( DataToStore , WideDataVT , DAG


<s> return ( ( ( reg_classes_intersect_p ( class1 , VEC_REGS ) && reg_classes_intersect_p ( class2 , GENERAL_REGS ) ) || ( reg_classes_intersect_p ( class1 , GENERAL_REGS ) && reg_classes_intersect_p ( class2 , VEC_REGS ) ) ) && ( ! TARGET_DFP || ! TARGET_64BIT || GET_MODE_SIZE ( mode ) != <NUM_LIT> ) && ( ! TARGET_VX || ( SCALAR_FLOAT_MODE_P ( mode )

&& GET_MODE_SIZE ( mode ) > <NUM_LIT> ) ) ) ;


<s> assert ( AllParams . count ( Param ) == <NUM_LIT> && <STR_LIT> ) ; return AllParams . find ( Param ) -> second .


<s> } else { llvm_unreachable ( <STR_LIT> ) ; } } else { unsigned ResReg = HEXAGON_RESERVED_REG_1 ; if ( ! MFI . hasVarSizedObjects ( ) && TII . isValidOffset ( MI . getOpcode ( ) , ( FrameSize + Offset ) ) ) { MI . getOperand ( FIOperandNum ) . ChangeToRegister ( getStackRegister ( ) , false , false , false ) ; MI . getOperand ( FIOperandNum + <NUM_LIT> ) . ChangeToImmediate ( FrameSize + Offset ) ; } else if ( ! TII . isValidOffset ( <STR_LIT> , Offset ) ) { BuildMI ( * MI . getParent ( ) , II , MI . getDebugLoc ( ) , TII . get ( <STR_LIT> ) , ResReg ) . addImm ( Offset ) ; BuildMI ( * MI . getParent ( ) , II , MI . getDebugLoc ( ) , TII . get ( <STR_LIT> ) , ResReg ) . addReg ( FrameReg ) . addReg ( ResReg ) ; MI . getOperand ( FIOperandNum ) . ChangeToRegister ( ResReg , false , false , true ) ; MI . getOperand ( FIOperandNum + <NUM_LIT> ) . ChangeToImmediate ( <NUM_LIT> ) ; } else { BuildMI ( * MI . getParent ( ) , II , MI . getDebugLoc ( ) , TII . get ( <STR_LIT> ) , ResReg ) . addReg ( FrameReg ) . addImm ( Offset ) ; MI . getOperand ( FIOperandNum ) . ChangeToRegister ( ResReg , false , false , true ) ; MI . getOperand ( FIOperandNum + <NUM_LIT> ) . ChangeToImmediate ( <NUM_LIT> ) ; } } } else { unsigned dstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; BuildMI ( * MI . getParent ( ) , II , MI . getDebugLoc ( ) , TII . get ( <STR_LIT> ) , dstReg ) . addImm ( Offset ) ; BuildMI ( * MI . getParent ( ) , II , MI . getDebugLoc ( ) , TII . get ( <STR_LIT> ) , dstReg ) . addReg ( FrameReg ) . addReg ( dstReg ) ; MI . getOperand ( FIOperandNum ) . ChangeToRegister ( dstReg , false , false , true ) ; MI . getOperand ( FIOperandNum + <NUM_LIT> ) . ChangeToImmediate ( <NUM_LIT> ) ; } } else


<s> EVT PtrVT = DAG . getTargetLoweringInfo ( ) . getPointerTy ( ) ; <ISA_LIT>FunctionInfo * FI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; int FPSI = FI -> getFramePointerSaveIndex ( ) ; if ( ! FPSI ) { int FPOffset = <ISA_LIT>FrameLowering :: getFramePointerSaveOffset (


<s> ( getSubtargetImpl ( ) -> isTargetCygMing ( ) || getSubtargetImpl ( ) -> isTargetWindows ( ) ) ? <STR_LIT> <STR_LIT> : <STR_LIT> <STR_LIT> ) , InstrInfo ( * this ) , TSInfo ( * this ) , TLInfo ( * this ) , JITInfo ( * this ) , STTI ( & TLInfo ) ,


<s> } Extensions [ ] = { { <STR_LIT> , { Feature_HasV8Bit } , { <STR_LIT> } } , { <STR_LIT> , { Feature_HasV8Bit } , { <STR_LIT> , <STR_LIT> , <STR_LIT> } } , { <STR_LIT> , { Feature_HasV8Bit } , { <STR_LIT> , <STR_LIT> , <STR_LIT> } } , { <STR_LIT> , { Feature_HasV8Bit } , { <STR_LIT> , <STR_LIT> , <STR_LIT> } } , { <STR_LIT> , { Feature_HasV8Bit } , { <STR_LIT> , <STR_LIT> } } , { ( <STR_LIT> | <STR_LIT> ) , { Feature_HasV7Bit , Feature_IsNotMClassBit } , { <STR_LIT> , <STR_LIT> } } , { <STR_LIT> , { Feature_HasV7Bit , Feature_IsNotMClassBit } , { <STR_LIT> } } , { <STR_LIT> , { Feature_HasV8Bit } , { <STR_LIT> , <STR_LIT> , <STR_LIT> } } , { <STR_LIT> , { Feature_HasV6KBit } , { <STR_LIT> } } , { <STR_LIT> , { Feature_HasV7Bit } , { <STR_LIT> } } , { <STR_LIT> , { Feature_HasV8_2aBit } , { <STR_LIT> , <STR_LIT> } } , { <STR_LIT> , { Feature_HasV8Bit } , { <STR_LIT> } } , { <STR_LIT> , { Feature_HasV8_1MMainlineBit } , { <STR_LIT> } } , { <STR_LIT> , { } , { } } , { <STR_LIT> , { } , { } } , { <STR_LIT> , { } , { } } , { <STR_LIT> , { } , { } } , { <STR_LIT> , { } , { } } , } ; bool EnableFeature = true ; if ( Name . startswith_insensitive ( <STR_LIT> ) ) { EnableFeature = false ; Name = Name . substr ( <NUM_LIT> ) ; } uint64_t FeatureKind = <STR_LIT> ( Name ) ; if ( FeatureKind == <STR_LIT> ) return Error ( ExtLoc , <STR_LIT> + Name ) ; for ( const auto & Extension : Extensions ) { if ( Extension . Kind != FeatureKind ) continue ; if ( Extension . Features . none ( ) ) return


<s> setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Expand ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Expand ) ; for ( MVT InnerVT : <STR_LIT> ( ) ) setLoadExtAction ( <STR_LIT> , InnerVT , VT . getSimpleVT ( ) , Expand ) ; if ( VT != <STR_LIT> && VT != <STR_LIT> ) setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Expand ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Expand ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Expand ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Expand ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Expand ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Expand ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Custom ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Custom ) ; if ( ! VT . isFloatingPoint ( ) && VT . getSimpleVT ( ) != <STR_LIT> && VT . getSimpleVT ( ) != <STR_LIT> ) for ( unsigned Opcode : { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ) setOperationAction ( Opcode , VT . getSimpleVT ( ) , Legal ) ; if ( VT . isFloatingPoint ( ) && VT . getVectorElementType ( ) != <STR_LIT> ) for ( unsigned Opcode : { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ) setOperationAction ( Opcode , VT . getSimpleVT ( ) , Legal ) ; if ( Subtarget -> isLittleEndian ( ) ) { for ( unsigned im = ( unsigned ) <STR_LIT> ; im != ( unsigned ) <STR_LIT> ; ++ im ) { setIndexedLoadAction ( im , VT . getSimpleVT ( ) , Legal ) ; setIndexedStoreAction ( im , VT .


<s> for ( auto & Def : MRI . def_instructions ( Reg ) ) if ( IsArgument ( & Def ) ) return true ; return false


<s> enum { ALIGN1 = <NUM_LIT> , ALIGN4 , ALIGN8 } AlignVariant ; if ( ( Align & <NUM_LIT> ) == <NUM_LIT> ) AlignVariant = ALIGN8 ; else if ( ( Align & <NUM_LIT> ) == <NUM_LIT> ) AlignVariant = ALIGN4 ; else AlignVariant = ALIGN1 ; TargetLowering :: ArgListTy Args ; TargetLowering :: ArgListEntry Entry ; Entry . Ty = DAG . getDataLayout ( ) . getIntPtrType ( * DAG . getContext ( ) ) ; Entry . Node = Dst ; Args . push_back ( Entry ) ; if ( AEABILibcall == AEABI_MEMCLR ) { Entry . Node = Size ; Args . push_back ( Entry ) ; } else if ( AEABILibcall == AEABI_MEMSET ) { Entry . Node = Size ; Args . push_back ( Entry ) ; if ( Src . getValueType ( ) . bitsGT ( <STR_LIT> ) ) Src = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Src ) ; else if ( Src . getValueType ( ) . bitsLT ( <STR_LIT> ) ) Src = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Src ) ; Entry . Node = Src ; Entry . Ty = Type :: getInt32Ty ( * DAG . getContext ( ) ) ; Entry . isSExt = false ; Args . push_back ( Entry ) ; } else { Entry . Node = Src ; Args . push_back ( Entry ) ; Entry . Node = Size ; Args . push_back ( Entry ) ; } char const * FunctionNames [ <NUM_LIT> ] [ <NUM_LIT> ] = { { <STR_LIT> , <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> ,


<s> CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; CUMULATIVE_ARGS next_cum ; tree fntype ; gcc_assert ( ! no_rtl ) ; if ( ! TARGET_64BIT ) return ; fntype = TREE_TYPE ( current_function_decl ) ; next_cum = * cum ; if ( ! TYPE_NO_NAMED_ARGS_STDARG_P ( TREE_TYPE ( current_function_decl ) ) && stdarg_p ( fntype ) ) ix86_function_arg_advance ( pack_cumulative_args ( & next_cum ) , arg ) ; if ( cum -> call_abi == MS_ABI ) setup_incoming_varargs_ms_64 (


<s> std :: tie ( Lo , Hi ) = DAG . SplitVector ( Match , DL ) ; Match = DAG . getNode ( BinOp , DL , Lo . getValueType ( ) , Lo , Hi ) ; MatchSizeInBits = Match . getValueSizeInBits ( ) ; } MVT MaskSrcVT ; if ( <NUM_LIT> == BitWidth || <NUM_LIT> == BitWidth ) MaskSrcVT = <STR_LIT> ( <STR_LIT> ( BitWidth ) , MatchSizeInBits / BitWidth ) ; else MaskSrcVT = <STR_LIT> ( <STR_LIT> , MatchSizeInBits / <NUM_LIT> ) ; SDValue BitcastLogicOp = DAG . getBitcast ( MaskSrcVT , Match ) ; Movmsk = getPMOVMSKB ( DL , BitcastLogicOp , DAG , Subtarget ) ; NumElts = MaskSrcVT . getVectorNumElements ( ) ; } assert ( NumElts <= <NUM_LIT> && <STR_LIT> ) ; if ( BinOp == <STR_LIT> ) { SDValue Mask = DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; SDValue Result = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Movmsk ) ; Result = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Result , Mask ) ; return DAG . getZExtOrTrunc ( Result , DL , ExtractVT ) ; } SDValue CmpC ; <STR_LIT> CondCode ; if ( BinOp == <STR_LIT> ) { CmpC = DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; CondCode = <STR_LIT> :: SETNE ; } else { CmpC = DAG . getConstant ( ( <NUM_LIT> << NumElts ) - <NUM_LIT> , DL , <STR_LIT> ) ; CondCode = <STR_LIT> :: SETEQ ; } const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; EVT SetccVT = TLI . getSetCCResultType ( DAG . getDataLayout ( ) , * DAG . getContext ( ) , <STR_LIT> ) ; SDValue Setcc = DAG . getSetCC ( DL , SetccVT , Movmsk


<s> static const char * getNanName ( uint64_t flags ) { return flags & llvm :: ELF :: EF_MIPS_NAN2008 ?


<s> Sec -> setAlignment ( Align ( <NUM_LIT> ) ) ; Streamer -> SwitchSection ( Sec ) ; Streamer -> emitInt8 ( ELF :: ODK_REGINFO ) ; Streamer -> emitInt8 ( <NUM_LIT> ) ; Streamer -> emitInt16 ( <NUM_LIT> ) ; Streamer -> emitInt32 ( <NUM_LIT> ) ; Streamer -> emitInt32 ( ri_gprmask ) ; Streamer -> emitInt32 ( <NUM_LIT> ) ; Streamer -> emitInt32 ( ri_cprmask [ <NUM_LIT> ] ) ; Streamer -> emitInt32 ( ri_cprmask [ <NUM_LIT> ] ) ; Streamer -> emitInt32 ( ri_cprmask [ <NUM_LIT> ] ) ; Streamer -> emitInt32 ( ri_cprmask [ <NUM_LIT> ] ) ; Streamer -> emitIntValue ( ri_gp_value , <NUM_LIT> ) ; } else { MCSectionELF * Sec = Context . getELFSection ( <STR_LIT> , ELF :: SHT_MIPS_REGINFO , ELF :: SHF_ALLOC , <NUM_LIT> , <STR_LIT> ) ; MCA . registerSection ( *


<s> unsigned DestReg = MRI -> createVirtualRegister ( SuperRC ) ; unsigned MergedOffset = std :: min ( CI . Offset0 , CI . Offset1 ) ; assert ( CI . I -> hasOneMemOperand ( ) && CI . Paired -> hasOneMemOperand ( ) ) ; const MachineMemOperand * MMOa = * CI . I -> memoperands_begin ( ) ; const MachineMemOperand * MMOb = * CI . Paired -> memoperands_begin ( ) ; BuildMI ( * MBB , CI . Paired , DL , TII -> get ( Opcode ) , DestReg ) . add ( * TII -> getNamedOperand ( * CI . I , <STR_LIT> :: sbase ) ) . addImm ( MergedOffset ) . addImm ( CI . GLC0 ) . addImm ( CI . DLC0 ) . addMemOperand ( combineKnownAdjacentMMOs ( * MBB -> getParent ( ) , MMOa , MMOb ) ) ; std :: pair < unsigned , unsigned > SubRegIdx = getSubRegIdxs ( CI ) ; const unsigned SubRegIdx0 = std :: get < <NUM_LIT> > ( SubRegIdx ) ; const unsigned SubRegIdx1 = std :: get < <NUM_LIT> > ( SubRegIdx ) ; const MCInstrDesc & CopyDesc = TII -> get ( TargetOpcode :: COPY ) ; const auto * Dest0 = TII -> getNamedOperand ( * CI . I , <STR_LIT> :: sdst ) ; const auto * Dest1 = TII -> getNamedOperand ( * CI . Paired , <STR_LIT> :: sdst ) ; BuildMI ( * MBB , CI . Paired , DL , CopyDesc ) . add ( * Dest0 ) . addReg ( DestReg , <NUM_LIT> , SubRegIdx0 ) ; MachineInstr * Copy1 = BuildMI ( * MBB , CI . Paired , DL , CopyDesc ) . add ( * Dest1 ) . addReg (

DestReg , RegState :: Kill , SubRegIdx1 ) ;


<s> std :: unique_ptr < ScheduleDAGMutation > create<ISA_LIT>MacroFusionDAGMutation


<s> EVT VT = V128Reg . getValueType ( ) ; unsigned WideSize = VT . getVectorNumElements ( ) ; MVT EltTy = VT . getVectorElementType ( ) . getSimpleVT ( ) ; MVT NarrowTy = <STR_LIT> ( EltTy , WideSize / <NUM_LIT> ) ; return DAG . getTargetExtractSubreg ( <STR_LIT> , SDLoc (


<s> GlobalAddressSDNode * G = dyn_cast < GlobalAddressSDNode > ( Callee ) ; if ( ! G ) return false ; if ( CodeModel :: Medium == TM . getCodeModel ( ) || CodeModel :: Large == TM . getCodeModel ( ) ) return TM . shouldAssumeDSOLocal ( * Caller -> getParent ( ) , G -> getGlobal ( ) ) ; const GlobalValue * GV = G -> getGlobal ( ) ; if ( ! GV -> isStrongDefinitionForLinker ( ) ) return false ; if ( TM . getFunctionSections ( ) || GV -> hasComdat ( ) || Caller -> hasComdat ( ) || GV -> getSection ( ) != Caller -> getSection ( ) ) return false ; if ( const auto * F = dyn_cast < Function > ( GV ) ) { if ( F -> getSectionPrefix ( ) != Caller -> getSectionPrefix ( ) ) return false ; } if ( ! TM . shouldAssumeDSOLocal ( * Caller -> getParent ( ) , GV ) )


<s> break ; case <STR_LIT> : { if ( Inst . getOperand ( <NUM_LIT> ) . getReg ( ) != <STR_LIT> ) SegmentReg = Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ; break ; } case <STR_LIT> : { if ( Inst . getOperand ( <NUM_LIT> ) . getReg ( ) != <STR_LIT> ) SegmentReg = Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ; break ; } case <STR_LIT> : { SegmentReg = Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ; break ; } } if ( SegmentReg != <NUM_LIT> ) return <STR_LIT> ( SegmentReg ) ; if ( STI . hasFeature ( <STR_LIT> ) ) return <STR_LIT> ; if ( MemoryOperand >= <NUM_LIT> ) { unsigned BaseRegNum = MemoryOperand + <STR_LIT> ; unsigned BaseReg = Inst . getOperand ( BaseRegNum ) . getReg ( ) ; if ( BaseReg == <STR_LIT> || BaseReg == <STR_LIT> ) return <STR_LIT> ; } return <STR_LIT>


<s> return llvm :: InlineCost :: getNever ( IsViable . getFailureReason ( ) ) ; } if ( isWrapperOnlyCall ( CB ) ) return llvm :: InlineCost :: getAlways ( <STR_LIT> ) ; InlineParams LocalParams = Params ; LocalParams . DefaultThreshold = ( int ) getInlineThreshold ( CB ) ; bool RemarksEnabled = false ; const auto & BBs = Caller -> getBasicBlockList ( ) ; if ( ! BBs . empty ( ) ) { auto DI = OptimizationRemark ( DEBUG_TYPE , <STR_LIT> , DebugLoc ( ) , & BBs . front ( ) ) ; if ( DI . isEnabled ( ) ) RemarksEnabled = true ; } OptimizationRemarkEmitter ORE ( Caller ) ; auto GetAssumptionCache = [ this ] ( Function & F ) -> AssumptionCache & { return ACT -> getAssumptionCache ( F ) ; } ; auto IC = llvm :: getInlineCost ( CB , Callee , LocalParams , TTI , GetAssumptionCache , GetTLI , nullptr , P<ISA_LIT> , RemarksEnabled ? & ORE : nullptr ) ; if ( IC && ! IC . isAlways ( ) && ! Callee -> hasFnAttribute ( Attribute :: InlineHint ) ) { size_t Size = Caller -> size ( ) + Callee -> size ( )


<s> BB = const_cast < MachineBasicBlock * > ( MR ->


<s> switch ( Op . getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; return SDValue ( ) ; case <STR_LIT> : return LowerFrameIndex ( Op , DAG ) ; case <STR_LIT> : return LowerGlobalAddress ( Op , DAG ) ; case <STR_LIT> : return LowerExternalSymbol ( Op , DAG ) ; case <STR_LIT> : return LowerJumpTable ( Op , DAG ) ; case <STR_LIT> : return LowerBR_JT ( Op ,


<s> if ( FrameIndexSDNode * FIN = dyn_cast < FrameIndexSDNode > ( Addr ) ) { EVT ValTy = Addr . getValueType ( ) ; Base = CurDAG -> getTargetFrameIndex ( FIN -> getIndex ( ) ,


<s> void <ISA_LIT>AsmPrinter :: emitArrayBound ( MCSymbol * Sym , const GlobalVariable * GV ) { assert ( ( ( GV -> hasExternalLinkage ( ) || GV -> hasWeakLinkage ( ) ) || GV -> hasLinkOnceLinkage ( ) ) && <STR_LIT> ) ; if ( ArrayType * ATy = dyn_cast < ArrayType > ( cast < PointerType > ( GV -> getType ( ) )


<s> else Inst . addOperand ( MCOperand :: createImm ( Value ) ) ; return MCDisassembler :: Success


<s> rtx temp = op0 ; if ( can_create_pseudo_p ( ) ) temp = gen_reg_rtx ( mode ) ; if ( GET_CODE ( op1 ) == CONST_INT ) { gcc_assert ( ! small_int_operand ( op1 , mode ) && ! const_high_operand ( op1 , mode ) ) ; emit_insn ( gen_rtx_SET ( temp , GEN_INT ( INTVAL ( op1 ) & ~ ( HOST_WIDE_INT ) <NUM_LIT> ) ) ) ; emit_insn ( gen_rtx_SET ( op0 , gen_rtx_IOR ( mode , temp , GEN_INT ( INTVAL ( op1 ) & <NUM_LIT> ) ) ) ) ; } else { emit_insn ( gen_rtx_SET ( temp , gen_rtx_HIGH ( mode , op1 ) ) ) ; emit_insn ( gen_rtx_SET ( op0 , gen_rtx_LO_SUM ( mode , temp


<s> const MCInstrDesc & MCID = MI . getDesc ( ) ; int CondNo = getCondSrcNoFromDesc ( MCID ) ; if ( CondNo < <NUM_LIT> ) return <STR_LIT> ; CondNo += MCID . getNumDefs ( ) ; return static_cast < <STR_LIT> > ( MI . getOperand ( CondNo ) . getImm


<s> switch ( MO . getImm ( ) ) { default : break ; case <NUM_LIT> : return <NUM_LIT> ; case <NUM_LIT> : return <NUM_LIT> ; case <NUM_LIT> : return <NUM_LIT> ; case <NUM_LIT> : return <NUM_LIT> ; } assert ( false && <STR_LIT> ) ; return <NUM_LIT>


<s> MachineBasicBlock * <ISA_LIT>SETargetLowering :: emitLD_F16_PSEUDO ( MachineInstr & MI , MachineBasicBlock * BB ) const { const TargetInstrInfo * TII = Subtarget . getInstrInfo ( ) ; MachineRegisterInfo & RegInfo = BB -> getParent ( ) -> getRegInfo ( ) ; DebugLoc DL = MI . getDebugLoc ( ) ; Register Wd = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; const TargetRegisterClass * RC = MI . getOperand ( <NUM_LIT> ) . isReg ( ) ? RegInfo . getRegClass ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) : ( Subtarget . isABI_O32 ( ) ? & <STR_LIT> : & <STR_LIT> ) ; const bool Using<ISA_LIT>32 = RC == & <STR_LIT> ; Register Rt = RegInfo . createVirtualRegister ( RC ) ; MachineInstrBuilder MIB = BuildMI ( * BB , MI , DL , TII -> get ( Using<ISA_LIT>32 ? <STR_LIT> : <STR_LIT> ) , Rt ) ; for ( const MachineOperand & MO : llvm :: drop_begin ( MI . operands ( ) ) ) MIB . add ( MO ) ; if ( ! Using<ISA_LIT>32 ) { Register Tmp = RegInfo . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) , Tmp ) . addReg ( Rt , <NUM_LIT> , <STR_LIT> ) ; Rt =


<s> SDValue <ISA_LIT>TargetLowering :: LowerConstantPool ( SDValue Op , SelectionDAG & DAG ) const { ConstantPoolSDNode * CP = cast < ConstantPoolSDNode > ( Op ) ; SDLoc dl ( CP ) ; EVT PtrVT = Op . getValueType ( ) ; SDValue Res ; if ( CP -> isMachineConstantPoolEntry ( ) ) { Res = DAG . getTargetConstantPool ( CP -> getMachineCPVal ( ) , PtrVT , CP -> getAlignment ( ) ) ; } else { Res = DAG . getTargetConstantPool ( CP -> getConstVal ( ) , PtrVT , CP -> getAlignment ( ) ) ; } return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> ,


<s> switch ( Val ) { case <NUM_LIT> : return createRegOperand ( getMCReg ( FLAT_SCR , STI ) ) ; case <NUM_LIT> : return createRegOperand ( VCC ) ; case <NUM_LIT> : return


<s> unsigned Alignment = LI -> getAlignment ( ) ; unsigned ABIAlignment = DL . getABITypeAlignment ( LI -> getType ( ) ) ; if ( Alignment == <NUM_LIT> ) Alignment = ABIAlignment ; unsigned ResultReg = <NUM_LIT> ; if ( ! <ISA_LIT>FastEmitLoad ( VT , AM , createMachineMemOperandFor ( LI ) , ResultReg , Alignment ) ) return false ; updateValueMap ( I , ResultReg


<s> if ( RemainingSize != <NUM_LIT> ) Changed |= padInstructionViaRelaxation ( RF , Emitter , RemainingSize ) ; if ( RemainingSize != <NUM_LIT> ) Changed |= padInstructionViaPrefix ( RF ,


<s> if ( isCommutedMOVLMask ( cast < ShuffleVectorSDNode > ( NewOp ) -> getMask ( ) , NewVT , true , false ) ) return getVZextMovL ( VT , NewVT , NewOp . getOperand ( <NUM_LIT> ) , DAG , Subtarget , dl ) ; } } else if ( <STR_LIT> ( V1 . getNode ( ) ) ) { SDValue NewOp = RewriteAsNarrowerShuffle ( SVOp , DAG , dl ) ; if ( NewOp . getNode ( ) ) { EVT NewVT = NewOp . getValueType ( ) ; if ( isMOVLMask ( cast < ShuffleVectorSDNode > ( NewOp ) -> getMask ( ) , NewVT ) ) return getVZextMovL ( VT , NewVT , NewOp . getOperand ( <NUM_LIT> ) , DAG , Subtarget , dl ) ; } } } return SDValue


<s> return ( ST == <STR_LIT> || ST == <STR_LIT> || ST == <STR_LIT> || ST == <STR_LIT> || ST ==


<s> auto TokOp = std :: make_unique < <ISA_LIT>Operand > ( k_Token , NameLoc , NameLoc ) ; TokOp -> Tok . Data = Token . data ( ) ; TokOp -> Tok . Length = Token . size


<s> SDValue Op ( N , <NUM_LIT> ) ; if ( SDValue Res = combine<ISA_LIT>ShufflesRecursively ( Op , DAG , Subtarget ) ) return Res ; } if ( ( VT . getScalarSizeInBits ( ) % <NUM_LIT> ) == <NUM_LIT> && N -> getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> && isa < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ) ) { SDValue BitMask = N -> getOperand ( <NUM_LIT> ) ; SDValue SrcVec = N -> getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ; EVT SrcVecVT = SrcVec . getValueType ( ) ; APInt UndefElts ; SmallVector < APInt , <NUM_LIT> > EltBits ; if ( VT == SrcVecVT . getScalarType ( ) && N -> getOperand ( <NUM_LIT> ) -> isOnlyUserOf ( SrcVec . getNode ( ) ) && getTargetConstantBitsFromNode ( BitMask , <NUM_LIT> , UndefElts , EltBits ) && llvm :: all_of ( EltBits , [ ] ( const APInt & M ) { return M . isNullValue ( ) || M . isAllOnesValue ( ) ; } ) ) { unsigned NumElts = SrcVecVT . getVectorNumElements ( ) ; unsigned Scale = SrcVecVT . getScalarSizeInBits ( ) / <NUM_LIT> ; unsigned Idx = N -> getOperand ( <NUM_LIT> ) . getConstantOperandVal ( <NUM_LIT> ) ; SmallVector < int , <NUM_LIT> > ShuffleMask ( NumElts * Scale , SM_SentinelUndef ) ; for ( unsigned i = <NUM_LIT> ; i != Scale ; ++ i ) { if ( UndefElts [ i ] ) continue ; int VecIdx = Scale * Idx + i ; ShuffleMask [ VecIdx ] = EltBits [ i ] . isNullValue ( ) ? SM_SentinelZero : VecIdx ; } if ( SDValue Shuffle = combine<ISA_LIT>ShufflesRecursively ( { SrcVec } , <NUM_LIT> , SrcVec , ShuffleMask , { } , <NUM_LIT> , <STR_LIT> , false , true , true , DAG , Subtarget ) ) return DAG . getNode ( <STR_LIT> , SDLoc ( N ) ,

VT , Shuffle , N -> getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ) ;


<s> LLVMTargetMachine & TM = const_cast < LLVMTargetMachine & > ( MF -> getTarget ( ) ) ; <ISA_LIT>TargetMachine & nvTM = static_cast < <ISA_LIT>TargetMachine & > ( TM ) ; const <ISA_LIT>MachineFunctionInfo * MFI = MF -> getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; const char * Sym = MFI -> getImageHandleSymbol ( Index ) ; std :: string * SymNamePtr = nvTM . getManagedStrPool ( ) -> getManagedString ( Sym ) ; MCOp = GetSymbolRef ( OutContext . getOrCreateSymbol ( StringRef ( * SymNamePtr


<s> if ( offset >= cfun_frame_layout . f8_offset ) next_fpr = i ; } if ( ! TARGET_PACKED_STACK ) next_fpr = cfun_save_high_fprs_p ? FPR15_REGNUM : <NUM_LIT> ; if ( flag_stack_usage_info ) current_function_static_stack_size = cfun_frame_layout . frame_size ; if ( cfun_frame_layout . frame_size > <NUM_LIT> ) { rtx frame_off = GEN_INT ( - cfun_frame_layout . frame_size ) ; rtx real_frame_off ; if ( s390_stack_size ) { HOST_WIDE_INT stack_guard ; if ( s390_stack_guard ) stack_guard = s390_stack_guard ; else { stack_guard = <NUM_LIT> ; while ( stack_guard < cfun_frame_layout . frame_size ) stack_guard <<= <NUM_LIT> ; } if ( cfun_frame_layout . frame_size >= s390_stack_size ) { warning ( <NUM_LIT> , <STR_LIT> <STR_LIT> <STR_LIT> <STR_LIT> , current_function_name ( ) , cfun_frame_layout . frame_size , s390_stack_size ) ; emit_insn ( gen_trap ( ) ) ; } else { if ( stack_guard >= s390_stack_size ) { warning ( <NUM_LIT> , <STR_LIT> <STR_LIT> <STR_LIT> <STR_LIT> , current_function_name ( ) , cfun_frame_layout . frame_size ) ; } else { HOST_WIDE_INT stack_check_mask = ( ( s390_stack_size - <NUM_LIT> ) & ~ ( stack_guard - <NUM_LIT> ) ) ; rtx t = gen_rtx_AND ( Pmode , stack_pointer_rtx , GEN_INT ( stack_check_mask ) ) ; if ( TARGET_64BIT ) emit_insn ( gen_ctrapdi4 ( gen_rtx_EQ ( VOIDmode , t , const0_rtx ) , t , const0_rtx , const0_rtx ) ) ; else emit_insn ( gen_ctrapsi4 ( gen_rtx_EQ ( VOIDmode , t , const0_rtx ) , t , const0_rtx , const0_rtx ) ) ; } } } if ( s390_warn_framesize > <NUM_LIT> && cfun_frame_layout . frame_size >= s390_warn_framesize ) warning ( <NUM_LIT> , <STR_LIT> , current_function_name ( ) , cfun_frame_layout . frame_size ) ; if ( s390_warn_dynamicstack_p && cfun -> calls_alloca ) warning ( <NUM_LIT> , <STR_LIT> , current_function_name ( ) ) ; if ( TARGET_BACKCHAIN || next_fpr ) insn = emit_insn ( gen_move_insn ( temp_reg , stack_pointer_rtx ) ) ; if ( DISP_IN_RANGE ( INTVAL ( frame_off ) ) ) { insn = gen_rtx_SET ( VOIDmode , stack_pointer_rtx , gen_rtx_PLUS ( Pmode , stack_pointer_rtx , frame_off ) ) ; insn = emit_insn ( insn ) ; } else { if ( ! CONST_OK_FOR_K ( INTVAL ( frame_off ) ) ) frame_off = force_const_mem ( Pmode , frame_off ) ; insn = emit_insn ( gen_add2_insn ( stack_pointer_rtx , frame_off ) ) ; annotate_constant_pool_refs ( & PATTERN ( insn ) ) ; } RTX_FRAME_RELATED_P ( insn ) =


<s> void <ISA_LIT>RegisterBankInfo :: applyMappingImpl ( const OperandsMapper & OpdMapper


<s> if ( Op32 == - <NUM_LIT> ) return false ; return pseudoToMCOpcode ( Op32 )


<s> const <ISA_LIT>Subtarget & ST = F . getSubtarget < <ISA_LIT>Subtarget > ( ) ; uint32_t FP32Denormals = ST . hasFP32Denormals ( ) ? FP_DENORM_FLUSH_NONE : FP_DENORM_FLUSH_IN_FLUSH_OUT ; uint32_t FP64Denormals = ST . hasFP64Denormals (


<s> Inst . RemoveOperand ( <NUM_LIT> ) ; Inst . setDesc ( get ( NewOpc ) ) ; Inst . addOperand ( MachineOperand :: CreateImm ( <NUM_LIT> ) ) ; Inst . addImplicitDefUseOperands ( * MBB . getParent ( ) ) ; MRI . replaceRegWith ( OldDstReg , ResultReg ) ; legalizeOperands ( Inst , MDT ) ; addUsersToMoveToVALUWorklist ( ResultReg , MRI , Worklist ) ; return


<s> static DecodeStatus DecodeVecShiftL64Imm ( llvm :: MCInst & Inst , unsigned Imm , uint64_t Addr , const void * Decoder ) { return DecodeVecShiftLImm ( Inst , Imm , <NUM_LIT>


<s> explicit <ISA_LIT>MCAsmInfo ( StringRef TT ) { PrivateGlobalPrefix = <STR_LIT> ; WeakRefDirective =


<s> if ( NumBytes >= IMM_LOW ) { BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addImm ( NumBytes ) . addReg ( <STR_LIT> ) ; } else if ( getUpper16 ( NumBytes ) >= IMM_LOW ) { BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addImm ( getUpper16 ( NumBytes ) ) . addReg ( <STR_LIT> ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addImm ( getLower16 ( NumBytes ) ) . addReg ( <STR_LIT> ) ; } else { std :: string msg ; raw_string_ostream Msg ( msg ) ; Msg << <STR_LIT> << NumBytes ; llvm_report_error ( Msg . str ( ) ) ; } if ( FP ) { BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) ) . addReg ( <STR_LIT> )

. addImm ( <NUM_LIT> ) . addReg ( <STR_LIT> ) ;


<s> __builtin_aarch64_simd_xi __o ; __o = __builtin_aarch64_ld4v16qi ( ( const __builtin_aarch64_simd_qi * ) __a ) ; ret . val [ <NUM_LIT> ] = ( int8x16_t ) __builtin_aarch64_get_qregxiv16qi ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( int8x16_t ) __builtin_aarch64_get_qregxiv16qi ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( int8x16_t ) __builtin_aarch64_get_qregxiv16qi ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( int8x16_t ) __builtin_aarch64_get_qregxiv16qi


<s> if ( crtl -> args . pretend_args_size ) ra_size += <NUM_LIT> ; return gen_rtx_MEM ( Pmode , gen_rtx_PLUS ( Pmode , arg_pointer_rtx ,


<s> Value * Cond = Term -> getCondition ( ) ; IRBuilder < > Builder ( Term ) ; Cond = Builder . CreateNot ( Cond ) ; Term -> setCondition ( Cond )


<s> ++ SrcIdx ; continue ; } if ( Op . isOff ( ) ) { ++ SrcIdx ; Inst . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ; continue ; } if ( Op . isImm ( ) && Op . getImmTy ( ) == <ISA_LIT>Operand :: ImmTyExpTgt ) { Op . addImmOperands ( Inst , <NUM_LIT> ) ; continue ; } if ( Op . isToken ( ) && Op . getToken ( ) == <STR_LIT> ) continue ; OptionalIdx [ Op . getImmTy ( ) ]


<s> bool AMDGPUDevice :: isSupported ( <STR_LIT> Mode ) const { return getExecutionMode ( Mode


<s> MCAsmBackend * llvm :: create<ISA_LIT>AsmBackendEB ( const Target &


<s> static inline int bpf_fib_lookup ( void * ctx , struct bpf_fib_lookup * param , int plen ,


<s> size_t getRelaEntrySize ( ) { return


<s> MCInstrInfo * X = new MCInstrInfo ( ) ; Init<ISA_LIT>MCInstrInfo ( X ) ; return


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , Optional < CodeModel :: Model > CM , CodeGenOpt :: Level OL , bool JIT ) : LLVMTargetMachine ( T , computeDataLayout

( TT ) , TT , CPU , FS , Options , ! RM . hasValue ( ) ? Reloc :: Static : * RM , getEffectiveCodeModel ( CM , CodeModel :: Small ) , OL ) , TLOF ( std :: make_unique < TargetLoweringObjectFileELF > ( ) ) {


<s> case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; } MachineInstrBuilder MIB1 = BuildMI ( MBB , MBBI , MI . getDebugLoc ( ) , TII -> get ( Opcode ) , MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) . add ( MI . getOperand ( <NUM_LIT> ) ) . add ( MI . getOperand ( <NUM_LIT> ) ) . addImm ( <STR_LIT> ( <STR_LIT> , <NUM_LIT> ) ) ; transferImpOps ( MI , MIB1 , MIB1 ) ; MI . eraseFromParent ( ) ; return true ; } case <STR_LIT> : { unsigned DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; const MachineOperand & MO1 = MI . getOperand ( <NUM_LIT> ) ; unsigned Flags = MO1 . getTargetFlags ( ) ; MachineInstrBuilder MIB1 = BuildMI ( MBB , MBBI , MI . getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , DstReg ) ; MachineInstrBuilder MIB2 = BuildMI ( MBB , MBBI , MI . getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . add ( MI . getOperand ( <NUM_LIT> ) ) . addReg ( DstReg ) ; if ( MO1 . isGlobal ( ) ) { MIB1 . addGlobalAddress ( MO1 . getGlobal ( ) , <NUM_LIT> , Flags | <STR_LIT> ) ; MIB2 . addGlobalAddress ( MO1 . getGlobal ( ) , <NUM_LIT> , Flags | <STR_LIT> | <STR_LIT> ) ; } else if ( MO1 . isSymbol ( ) ) { MIB1 . addExternalSymbol ( MO1 . getSymbolName ( ) , Flags | <STR_LIT> ) ; MIB2 . addExternalSymbol ( MO1 . getSymbolName ( ) , Flags | <STR_LIT> | <STR_LIT> ) ; } else { assert ( MO1 . isCPI ( ) && <STR_LIT> ) ; MIB1 . addConstantPoolIndex ( MO1 . getIndex ( ) , MO1 . getOffset ( ) , Flags | <STR_LIT> ) ; MIB2 . addConstantPoolIndex ( MO1 . getIndex ( ) , MO1 . getOffset ( ) , Flags | <STR_LIT> | <STR_LIT> ) ; } transferImpOps ( MI , MIB1 , MIB2 ) ; MI . eraseFromParent ( ) ; return true


<s> SDValue Mul ; SDValue Other ; if ( N -> getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) { Mul = N -> getOperand ( <NUM_LIT> ) ; Other = N -> getOperand ( <NUM_LIT> ) ; } else if ( N -> getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) { Mul = N -> getOperand ( <NUM_LIT> ) ; Other = N -> getOperand ( <NUM_LIT> ) ; } else { return SDValue ( ) ; } SDLoc dl ( N ) ; SDValue LL , RL , AddendL , AddendH ; LL = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Mul . getOperand ( <NUM_LIT> ) , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; RL = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Mul . getOperand ( <NUM_LIT> ) , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; AddendL = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Other , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; AddendH = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Other , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; APInt HighMask = APInt :: getHighBitsSet ( <NUM_LIT> , <NUM_LIT> ) ; unsigned LHSSB = DAG . ComputeNumSignBits ( Mul . getOperand ( <NUM_LIT> ) ) ; unsigned RHSSB = DAG . ComputeNumSignBits ( Mul . getOperand ( <NUM_LIT> ) ) ; if ( DAG . MaskedValueIsZero ( Mul . getOperand ( <NUM_LIT> ) , HighMask ) && DAG . MaskedValueIsZero ( Mul . getOperand ( <NUM_LIT> ) , HighMask ) ) { SDValue Hi = DAG . getNode ( <STR_LIT> , dl , DAG . getVTList ( <STR_LIT> , <STR_LIT> ) , AddendH , AddendL , LL , RL ) ; SDValue Lo ( Hi . getNode ( ) , <NUM_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Lo , Hi ) ; } if ( LHSSB > <NUM_LIT> && RHSSB > <NUM_LIT> ) { SDValue Hi = DAG . getNode ( <STR_LIT> , dl , DAG . getVTList ( <STR_LIT> , <STR_LIT> ) , AddendH , AddendL , LL , RL ) ; SDValue Lo ( Hi . getNode ( ) , <NUM_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl


<s> bool writeNopData ( uint64_t Count ,


<s> if ( ! BranchRelaxation ) return false ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; TII = ( const <ISA_LIT>InstrInfo * ) MF -> getTarget ( ) . getInstrInfo ( ) ; MF -> RenumberBlocks ( ) ; scanFunction ( ) ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; DEBUG ( dumpBBs ( ) ) ; bool MadeChange = false ; while ( relaxBranchInstructions ( ) ) MadeChange = true ; verify ( ) ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; DEBUG ( dbgs ( ) << '\n' ; dumpBBs ( ) ) ; BlockInfo . clear


<s> unsigned char perm2 [ <NUM_LIT> ] ; rtx temp ; bool ok ; if ( ! d -> one_operand_p ) return false ; elt = d -> perm [ <NUM_LIT> ] ; for ( i = <NUM_LIT> ; i < nelt ; ++ i ) if ( d -> perm [ i ] != elt ) return false ; switch ( d -> vmode ) { case E_V2SImode : case E_V2SFmode : perm2 [ <NUM_LIT> ] = elt ; perm2 [ <NUM_LIT> ] = elt + <NUM_LIT> ; ok = expand_vselect_vconcat ( d -> target , d -> op0 , d -> op0 ,


<s> static void emit_soft_tfmode_unop ( enum rtx_code code , rtx * operands ) { const char * func ; gcc_assert ( code ==


<s> insn = emit_insn ( gen_gpr_save ( GEN_INT ( mask ) ) ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; REG_NOTES ( insn ) = dwarf ; } if ( ( frame -> mask | frame -> fmask ) != <NUM_LIT> ) { HOST_WIDE_INT step1 = MIN ( size , riscv_first_stack_step ( frame ) ) ; insn = gen_add3_insn ( stack_pointer_rtx , stack_pointer_rtx , GEN_INT ( - step1 ) ) ; RTX_FRAME_RELATED_P ( emit_insn ( insn ) ) = <NUM_LIT> ; size -= step1 ; riscv_for_each_saved_reg ( size , riscv_save_reg ) ; } frame -> mask = mask


<s> case <STR_LIT> : return LowerFP_TO_UINT ( Op , DAG ) ; case <STR_LIT> : return LowerFABS ( Op , DAG ) ; case <STR_LIT> : return LowerFNEG ( Op , DAG ) ; case <STR_LIT> : return LowerFCOPYSIGN ( Op , DAG ) ; case <STR_LIT> : return LowerSETCC ( Op , DAG ) ; case <STR_LIT> : return LowerVSETCC ( Op , DAG ) ; case <STR_LIT> : return LowerSELECT ( Op , DAG ) ; case <STR_LIT> : return LowerBRCOND ( Op , DAG ) ; case <STR_LIT> : return LowerJumpTable ( Op , DAG ) ; case <STR_LIT> : return LowerVASTART ( Op , DAG ) ; case <STR_LIT> : return LowerVAARG ( Op , DAG ) ; case <STR_LIT> : return LowerVACOPY ( Op , DAG ) ; case <STR_LIT> : return LowerINTRINSIC_WO_CHAIN ( Op , DAG ) ; case <STR_LIT> : return LowerRETURNADDR ( Op , DAG ) ; case <STR_LIT> : return LowerFRAMEADDR ( Op , DAG ) ; case <STR_LIT> : return LowerFRAME_TO_ARGS_OFFSET ( Op , DAG ) ; case <STR_LIT> : return LowerDYNAMIC_STACKALLOC ( Op , DAG ) ; case <STR_LIT> : return LowerEH_RETURN ( Op , DAG ) ; case <STR_LIT> : return LowerTRAMPOLINE ( Op , DAG ) ; case <STR_LIT> : return LowerFLT_ROUNDS_ ( Op , DAG ) ; case <STR_LIT> : return LowerCTLZ ( Op , DAG ) ; case <STR_LIT> : return LowerCTTZ ( Op , DAG ) ; case <STR_LIT> : return LowerMUL_V2I64 ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerXALUO ( Op ,


<s> bool isImm0_65535 ( ) const { if ( ! isImm ( ) ) return false ; const MCConstantExpr * MCE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; if ( ! MCE ) return false ; int64_t Val = MCE -> getValue ( )


<s> TargetRegistry :: RegisterDCInstrSema ( The<ISA_LIT>_64Target , create<ISA_LIT>DCInstrSema ) ; TargetRegistry :: RegisterDCRegisterSema ( The<ISA_LIT>_64Target , create<ISA_LIT>DCRegisterSema


<s> for ( ArrayRef < int > :: iterator I = ShuffleMask . begin ( ) , E = ShuffleMask . end ( ) ; I != E ; ++ I ) VTBLMask . push_back ( DAG . getConstant ( * I , <STR_LIT> ) ) ; if ( V2 . getNode ( ) -> getOpcode ( ) == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , & VTBLMask [ <NUM_LIT> ] , <NUM_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , V2 , DAG . getNode


<s> Patterns . push_back ( Pattern ) ; return true ; } return false ; } ; typedef MachineCombinerPattern MCP ; switch ( Root . getOpcode ( ) ) { default : return false ; case <STR_LIT> : Found = Match ( <STR_LIT> , <NUM_LIT> , MCP :: FMULv2i32_indexed_OP1 ) ; Found |= Match ( <STR_LIT> , <NUM_LIT> , MCP :: FMULv2i32_indexed_OP2 ) ; break ; case <STR_LIT> : Found = Match ( <STR_LIT> , <NUM_LIT> , MCP :: FMULv2i64_indexed_OP1 ) ; Found |= Match ( <STR_LIT> , <NUM_LIT> , MCP :: FMULv2i64_indexed_OP2 ) ; break ; case <STR_LIT> : Found = Match ( <STR_LIT> , <NUM_LIT> , MCP :: FMULv4i16_indexed_OP1 ) ; Found |= Match ( <STR_LIT> , <NUM_LIT> ,


<s> static type_suffix_index find_type_suffix_for_scalar_type ( const_tree type ) { for ( unsigned int suffix_i = <NUM_LIT> ; suffix_i < NUM_TYPE_SUFFIXES ; ++ suffix_i ) if ( ! type_suffixes [ suffix_i ] . bool_p ) { vector_type_index vector_i = type_suffixes [ suffix_i ] . vector_type ; if ( matches_type_p ( scalar_types [ vector_i ] , type ) ) return type_suffix_index ( suffix_i ) ; } return NUM_TYPE_SUFFIXES


<s> <ISA_LIT>CFGOptimizer ( const <ISA_LIT>TargetMachine & TM ) : MachineFunctionPass ( ID ) , QTM ( TM ) , QST ( * TM . getSubtargetImpl ( ) ) { initialize<ISA_LIT>CFGOptimizerPass ( * PassRegistry :: getPassRegistry


<s> bool <ISA_LIT>AsmBackend :: canPadBranches ( MCObjectStreamer & OS ) const { if ( ! OS . getAllowAutoPadding ( ) ) return false ; assert ( allowAutoPadding ( ) && <STR_LIT> ) ; if ( ! OS . getCurrentSectionOnly ( ) -> getKind ( ) . isText ( ) ) return false ; if ( OS . getAssembler ( ) .


<s> const MachineFunction & MF = * MBB . getParent ( ) ; assert ( MF . getFrameInfo ( ) . getObjectSize ( FrameIdx ) >= TRI -> getSpillSize ( * RC ) && <STR_LIT> ) ; unsigned Alignment = std :: max < uint32_t > ( TRI -> getSpillSize ( * RC ) , <NUM_LIT> ) ; bool isAligned = ( Subtarget . getFrameLowering ( ) -> getStackAlign ( ) >=

Alignment ) || RI . canRealignStack ( MF ) ;


<s> <STR_LIT> , <STR_LIT> } ; BitVector Reserved ( getNumRegs ( ) ) ; for ( unsigned I = <NUM_LIT> ; I < array_lengthof ( ReservedCPURegs ) ; ++ I ) Reserved . set ( ReservedCPURegs [ I ] ) ; return


<s> if ( ( Imm < <NUM_LIT> ) || ( Imm > <NUM_LIT> ) ) O << <STR_LIT> ; } else if ( <NUM_LIT> == strcmp ( Modifier , <STR_LIT> ) ) { if ( Imm < <NUM_LIT> ) Imm = <NUM_LIT> ; O << <STR_LIT> << vecelem [ Imm % <NUM_LIT> ] ; } else if ( <NUM_LIT> == strcmp ( Modifier , <STR_LIT> ) ) { if ( ( Imm < <NUM_LIT> ) || ( Imm > <NUM_LIT> ) ) O << <STR_LIT> ; } else if ( <NUM_LIT> == strcmp ( Modifier , <STR_LIT> ) ) { if ( ( Imm < <NUM_LIT> ) || ( Imm > <NUM_LIT> ) ) O << <STR_LIT> ; } else if ( <NUM_LIT> == strcmp ( Modifier , <STR_LIT> ) ) { if ( Imm < <NUM_LIT> ) Imm = <NUM_LIT> ; O << <STR_LIT> << vecelem [ Imm %


<s> if ( TT . isOSBinFormatMachO ( ) ) { if ( TT . getArch ( ) == Triple :: x86_64 ) return new <ISA_LIT>_64MachoTargetObjectFile ( ) ; return new TargetLoweringObjectFileMachO ( ) ; } if ( TT . isOSLinux ( ) ) return new <ISA_LIT>LinuxTargetObjectFile (


<s> static rtx m32c_function_arg ( cumulative_args_t ca_v , const function_arg_info & arg ) { CUMULATIVE_ARGS * ca = get_cumulative_args ( ca_v ) ; rtx rv = NULL_RTX ; fprintf ( stderr , <STR_LIT> , ca -> parm_num , mode_name [ arg . mode ] , arg . named ) ; debug_tree ( arg . type ) ; if ( arg . end_marker_p ( ) ) return GEN_INT ( <NUM_LIT> ) ; if ( ca -> force_mem || ! arg . named ) { fprintf ( stderr , <STR_LIT> , ca -> force_mem , arg . named ) ; return NULL_RTX ; } if ( arg . type && INTEGRAL_TYPE_P ( arg . type ) && POINTER_TYPE_P ( arg . type ) ) return NULL_RTX ; if ( arg . aggregate_type_p ( ) ) return NULL_RTX ; switch ( ca -> parm_num ) { case <NUM_LIT> : if ( GET_MODE_SIZE ( arg . mode ) == <NUM_LIT> || GET_MODE_SIZE ( arg . mode ) == <NUM_LIT> ) rv = gen_rtx_REG ( arg . mode , TARGET_A16 ? R1_REGNO : R0_REGNO ) ; break ; case <NUM_LIT>


<s> uint32_t getAddrMode2OffsetOpValue ( const MachineInstr & MI , unsigned OpIdx ) const { return <NUM_LIT>


<s> size = ( <NUM_LIT> + h8300_constant_length ( offset ) + h8300_classify_operand ( src , GET_MODE_SIZE ( GET_MODE ( src ) ) , <NUM_LIT> ) ) ; if ( ! REG_P ( dest ) || ! REG_P ( src ) || REGNO ( src ) != REGNO ( dest ) ) size += <NUM_LIT> ; return


<s> const <ISA_LIT>InstrInfo & TII = * static_cast < const <ISA_LIT>InstrInfo * > ( MF . getTarget ( ) . getInstrInfo ( ) ) ; MachineBasicBlock :: iterator MBBI = MBB . begin ( ) ; DebugLoc dl = MBBI != MBB . end ( ) ? MBBI -> getDebugLoc ( ) : DebugLoc ( ) ; uint64_t StackSize = MFI -> getStackSize ( ) ; if ( StackSize == <NUM_LIT> && ! MFI -> adjustsStack ( ) ) return ; if ( isInt < <NUM_LIT> > ( - StackSize ) ) BuildMI ( MBB , MBBI ,

dl , TII . get ( <STR_LIT> ) ) . addImm ( StackSize ) ;


<s> unsigned int flags = call_properties ( ) ; if ( flags & CP_RAISE_FP_EXCEPTIONS ) return true ; if ( flags & CP_PREFETCH_MEMORY


<s> MF -> insert ( I , mainMBB ) ; MF -> insert ( I , sinkMBB ) ; MachineInstrBuilder MIB ; sinkMBB -> splice ( sinkMBB -> begin ( ) , MBB , llvm :: next ( MachineBasicBlock :: iterator ( MI ) ) , MBB -> end ( ) ) ; sinkMBB -> transferSuccessorsAndUpdatePHIs ( MBB ) ; MIB = BuildMI ( thisMBB , DL , TII -> get ( LOADOpc ) , AccPhyReg ) ; for ( unsigned i = <NUM_LIT> ; i < <STR_LIT> ; ++ i ) MIB . addOperand ( MI -> getOperand ( MemOpndSlot + i ) ) ; MIB . setMemRefs ( MMOBegin , MMOEnd ) ; thisMBB -> addSuccessor ( mainMBB ) ; MachineBasicBlock * origMainMBB = mainMBB ; mainMBB -> addLiveIn ( AccPhyReg ) ; unsigned AccReg = MRI . createVirtualRegister ( RC ) ; BuildMI ( mainMBB , DL , TII -> get ( TargetOpcode :: COPY ) , AccReg ) . addReg ( AccPhyReg ) ; unsigned t1 = MRI . createVirtualRegister ( RC ) ; unsigned Opc = MI -> getOpcode ( ) ; switch ( Opc ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { unsigned ARITHOpc = getNonAtomicOpcode ( Opc ) ; BuildMI ( mainMBB , DL , TII -> get ( ARITHOpc ) , t1 ) . addReg ( SrcReg ) . addReg ( AccReg ) ; break ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { unsigned t2 = MRI . createVirtualRegister ( RC ) ; unsigned NOTOpc ; unsigned ANDOpc = getNonAtomicOpcodeWithExtraOpc ( Opc , NOTOpc ) ; BuildMI ( mainMBB , DL , TII -> get ( ANDOpc ) , t2 ) . addReg ( SrcReg ) . addReg ( AccReg ) ; BuildMI ( mainMBB , DL , TII -> get ( NOTOpc ) , t1 ) . addReg ( t2 ) ; break ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { unsigned CMPOpc ; unsigned CMOVOpc = getNonAtomicOpcodeWithExtraOpc ( Opc , CMPOpc ) ; BuildMI ( mainMBB , DL , TII -> get ( CMPOpc ) ) . addReg ( SrcReg ) . addReg ( AccReg ) ; if ( Subtarget -> hasCMov


<s> return ( CountLeadingOnes_64 ( Chunk ) + countTrailingZeros ( Chunk )


<s> unsigned <ISA_LIT>TTIImpl :: getMinimumVF ( unsigned ElemWidth ) const { return ( <NUM_LIT> * ST . getVectorLength


<s> getMemEncodingMMImm4Lsl1 ( const MCInst & MI , unsigned OpNo , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { assert ( MI . getOperand ( OpNo ) . isReg ( ) ) ; unsigned RegBits = getMachineOpValue ( MI , MI . getOperand ( OpNo ) , Fixups , STI ) << <NUM_LIT> ; unsigned OffBits = getMachineOpValue ( MI , MI . getOperand ( OpNo + <NUM_LIT> ) , Fixups ,


<s> if ( state . insns_left != state . issue_rate && ! CALL_P ( subinsn ) ) { if ( subinsn == SEQ_BEGIN ( insn ) && aligned_p ) { gcc_assert ( last2 ) ; emit_insn_after ( gen_nop ( ) , last2 ) ; aligned_p = false ; } else if ( subinsn != SEQ_BEGIN ( insn ) && ! aligned_p ) { gcc_assert ( last ) ; emit_insn_after ( gen_nop ( ) , last ) ; aligned_p = true ; } } mips_sim_issue_insn ( & state , subinsn ) ; } mips_sim_finish_insn ( & state , insn ) ; length = get_attr_length ( insn ) ; if ( length > <NUM_LIT> ) { if ( NONJUMP_INSN_P ( SEQ_BEGIN ( insn ) ) && ( recog_memoized ( insn ) < <NUM_LIT> || length >= <NUM_LIT> ) ) { next = emit_insn_after ( gen_align ( GEN_INT ( <NUM_LIT> ) ) , insn ) ; next = NEXT_INSN ( next ) ; mips_sim_next_cycle ( & state ) ; aligned_p = true ; } else if ( length & <NUM_LIT> ) aligned_p = ! aligned_p ; last2 = last ; last = insn ; } if ( LABEL_P ( insn ) && label_to_alignment ( insn )


<s> unsigned Rn = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned Rm = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned inc = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) + <NUM_LIT> ; if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , Rd , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , ( Rd + inc ) % <NUM_LIT> , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , ( Rd + <NUM_LIT> * inc ) % <NUM_LIT> , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( Rm != <NUM_LIT> ) { if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rn , Address , Decoder ) ) ) return MCDisassembler :: Fail ; } if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rn , Address , Decoder ) ) ) return MCDisassembler :: Fail ; Inst . addOperand ( MCOperand :: createImm ( <NUM_LIT> ) ) ; if ( Rm == <NUM_LIT> ) Inst . addOperand ( MCOperand :: createReg ( <NUM_LIT>


<s> if ( CONST_INT_P ( length ) ) { if ( INTVAL ( length ) <= MIPS_MAX_MOVE_BYTES_STRAIGHT ) { mips_block_move_straight ( dest , src , INTVAL ( length ) ) ; return true ; } else if ( optimize ) { mips_block_move_loop ( dest , src , INTVAL ( length ) , MIPS_MAX_MOVE_BYTES_PER_LOOP_ITER ) ; return true ; } } return


<s> static int * find_mult_constants_used ( int multiplier ) { return ( int * ) bsearch ( & multiplier , multiply_constants_used , num_mult_constants_used , sizeof multiply_constants_used


<s> static DecodeStatus s6_0ImmDecoder ( MCInst & MI , unsigned tmp , uint64_t , const void * Decoder ) { signedDecoder < <NUM_LIT> > ( MI , tmp , Decoder ) ; return MCDisassembler :: Success


<s> enum reg_class ret = rs6000_preferred_reload_class ( x , rclass ) ; fprintf ( stderr , <STR_LIT> <STR_LIT> , reg_class_names [ ret ] , reg_class_names [ rclass ] , GET_MODE_NAME ( GET_MODE ( x ) ) ) ; debug_rtx ( x )


<s> OTy = GetRootType ( OTy ) ; gep_type_iterator IdxTyItr = gep_type_begin ( GI ) ; assert ( OTy == IdxTyItr . getIndexedType ( ) && <STR_LIT> ) ; return getTyIndexInFlattenedType_core ( Func , ConstantInt :: get ( Int32Ty , APInt ( <NUM_LIT> ,

<NUM_LIT> ) ) , GI , AccessMemFormFlatStruct ) ;


<s> if ( getTargetMachine ( ) . getRelocationModel ( ) == Reloc :: PIC_ ) return LowerToTLSGeneralDynamicModel ( GA , DAG ) ; else return LowerToTLSExecModels ( GA , DAG


<s> ReverseIter Filler ; RegDU . init ( Slot ) ; MachineBasicBlock :: iterator SlotI = Slot ; if ( ! searchRange ( MBB , ++ SlotI . getReverse ( ) , MBB . rend ( ) , RegDU , MemDU , Slot , Filler ) ) { LLVM_DEBUG ( dbgs ( ) << DEBUG_TYPE <STR_LIT>


<s> return selectInterpP1F16 ( I ) ; case <STR_LIT> : return constrainCopyLikeIntrin ( I , <STR_LIT> ) ; case <STR_LIT> : return constrainCopyLikeIntrin ( I , <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : return constrainCopyLikeIntrin ( I , <STR_LIT> ) ; case <STR_LIT> : return constrainCopyLikeIntrin ( I , <STR_LIT> ) ; case <STR_LIT> : return selectWritelane ( I ) ; case <STR_LIT> : return selectDivScale ( I ) ; case <STR_LIT> : return selectIntrinsicIcmp ( I ) ; case <STR_LIT> : return selectBallot ( I ) ; case <STR_LIT> : return selectRelocConstant ( I ) ; case <STR_LIT> : return selectGroupStaticSize ( I ) ; case <STR_LIT> : return selectReturnAddress ( I ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> Value * T = nullptr ; if ( match ( ShouldXoredV , m_Xor ( m_Value ( Y ) , m_Value ( Z ) ) ) ) { if ( ShouldSameV == Y ) T = Z ; else if ( ShouldSameV == Z ) T = Y ; else return false ; R = ShouldSameV ; } else if ( match ( ShouldSameV , m_Zero ( ) ) ) { if ( ! SelI -> hasOneUse ( ) ) return false ; T = ShouldXoredV ; Value * U = * SelI -> user_begin ( ) ; if ( ! match ( U , m_Xor ( m_Specific ( SelI ) , m_Value ( R ) ) ) && ! match ( U , m_Xor ( m_Value ( R ) , m_Specific ( SelI ) ) ) ) return false ; } else return false ; if ( ! match ( T , m_Shl ( m_Value ( Q ) , m_Specific ( CIV ) ) ) && ! match ( T , m_Shl ( m_ZExt ( m_Value ( Q

) ) , m_ZExt ( m_Specific ( CIV ) ) ) ) ) return false ;


<s> static DecodeStatus DecodeSimm4 ( MCInst & Inst , unsigned Value , uint64_t Address , const void * Decoder ) { Inst . addOperand ( MCOperand :: createImm ( SignExtend32 < <NUM_LIT>


<s> unsigned NumElts = SrcOps [ <NUM_LIT> ] . getValueType ( ) . getVectorNumElements ( ) ; EVT MaskVT = EVT :: getIntegerVT ( * DAG . getContext ( ) , NumElts ) ; SDValue Mask = combineBitcastvxi1 ( DAG , MaskVT , SrcOps [ <NUM_LIT> ] , dl , Subtarget ) ; if ( Mask ) { APInt AllBits = APInt :: getAllOnesValue ( NumElts ) ; return DAG . getSetCC ( dl , <STR_LIT> , Mask , DAG . getConstant ( AllBits , dl , MaskVT ) , <STR_LIT> ) ; } } } if ( DCI . isBeforeLegalizeOps ( ) ) return SDValue ( ) ; if ( SDValue R = combineCompareEqual ( N , DAG , DCI , Subtarget ) ) return R ; if ( SDValue FPLogic = convertIntLogicToFPLogic ( N , DAG , Subtarget ) ) return FPLogic ; if ( SDValue R = combineANDXORWithAllOnesIntoANDNP ( N , DAG ) ) return R ; if ( SDValue ShiftRight = combineAndMaskToShift ( N , DAG , Subtarget ) ) return ShiftRight ; if ( SDValue R = combineAndLoadToBZHI ( N , DAG , Subtarget ) ) return R ; if ( VT . isVector ( ) && ( VT . getScalarSizeInBits ( ) % <NUM_LIT> ) == <NUM_LIT> ) { SDValue Op ( N , <NUM_LIT> ) ; if ( SDValue Res = combine<ISA_LIT>ShufflesRecursively ( Op , DAG , Subtarget ) ) return Res ; } if ( ( VT . getScalarSizeInBits ( ) % <NUM_LIT> ) == <NUM_LIT> && N -> getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> && isa < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ) ) { SDValue BitMask = N -> getOperand ( <NUM_LIT> ) ; SDValue SrcVec = N -> getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ; EVT SrcVecVT = SrcVec . getValueType ( ) ; APInt UndefElts ; SmallVector < APInt , <NUM_LIT> > EltBits ; if ( VT == SrcVecVT . getScalarType ( ) && N -> getOperand ( <NUM_LIT> ) -> isOnlyUserOf ( SrcVec . getNode ( ) ) && getTargetConstantBitsFromNode ( BitMask , <NUM_LIT> , UndefElts , EltBits ) && llvm :: all_of ( EltBits , [ ] ( APInt M ) { return M . isNullValue ( ) || M . isAllOnesValue ( ) ; } ) ) { unsigned NumElts = SrcVecVT . getVectorNumElements ( ) ; unsigned Scale = SrcVecVT . getScalarSizeInBits ( ) / <NUM_LIT> ; unsigned Idx = N -> getOperand ( <NUM_LIT> ) . getConstantOperandVal ( <NUM_LIT> ) ; SmallVector < int , <NUM_LIT> > ShuffleMask ( NumElts * Scale ,


<s> } else if ( DEFAULT_ABI == ABI_V4 ) { if ( abi_v4_pass_in_fpr ( mode , named ) ) { if ( mode == TDmode && ( cum -> fregno % <NUM_LIT> ) == <NUM_LIT> ) cum -> fregno ++ ; if ( cum -> fregno + ( FLOAT128_2REG_P ( mode ) ? <NUM_LIT> : <NUM_LIT> ) <= FP_ARG_V4_MAX_REG ) cum -> fregno += ( GET_MODE_SIZE ( mode ) + <NUM_LIT> ) >> <NUM_LIT> ; else { cum -> fregno = FP_ARG_V4_MAX_REG + <NUM_LIT> ; if ( mode == DFmode || FLOAT128_IBM_P ( mode ) || mode == DDmode || mode == TDmode ) cum -> words += cum -> words & <NUM_LIT> ; cum -> words += rs6000_arg_size ( mode , type ) ; } } else { int n_words = rs6000_arg_size ( mode , type ) ; int gregno = cum -> sysv_gregno ; if ( n_words == <NUM_LIT> ) gregno += ( <NUM_LIT> - gregno ) & <NUM_LIT> ; if ( gregno + n_words - <NUM_LIT> > GP_ARG_MAX_REG ) { if ( n_words == <NUM_LIT> ) cum -> words += cum -> words & <NUM_LIT> ; cum -> words += n_words ; } cum -> sysv_gregno = gregno + n_words ; } if ( TARGET_DEBUG_ARG ) { fprintf ( stderr , <STR_LIT> , cum -> words , cum -> fregno ) ; fprintf ( stderr , <STR_LIT> , cum -> sysv_gregno , cum -> nargs_prototype , cum -> prototype ) ; fprintf ( stderr , <STR_LIT> , GET_MODE_NAME ( mode ) , named ) ; } } else { int n_words = rs6000_arg_size ( mode , type ) ; int start_words = cum -> words ; int align_words = rs6000_parm_start ( mode , type , start_words ) ; cum -> words = align_words + n_words ; if ( SCALAR_FLOAT_MODE_P ( elt_mode ) && TARGET_HARD_FLOAT ) { if ( elt_mode == TDmode && ( cum -> fregno % <NUM_LIT> ) == <NUM_LIT> ) cum -> fregno ++ ; cum -> fregno += n_elts * ( ( GET_MODE_SIZE ( elt_mode ) + <NUM_LIT> ) >> <NUM_LIT> ) ; } if ( TARGET_DEBUG_ARG ) { fprintf ( stderr , <STR_LIT> , cum -> words , cum


<s> int mmix_asm_preferred_eh_data_format ( int code ATTRIBUTE_UNUSED , int global ATTRIBUTE_UNUSED ) { return DW_EH_PE_absptr


<s> tmp = gen_reg_rtx ( Pmode ) ; emit_move_insn ( tmp , copy_rtx ( XEXP ( mem , <NUM_LIT> )


<s> void addVTypeIOperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: createImm ( getVType ( )


<s> bool <ISA_LIT>InstrInfo :: isDotNewInst ( const MachineInstr * MI


<s> bool <ISA_LIT>LowerMASSVEntries :: lowerMASSVCall ( CallInst * CI , Function & Func , Module & M , const <ISA_LIT>Subtarget * Subtarget ) { if ( CI -> use_empty ( ) ) return false ; std :: string MASSVEntryName = createMASSVFuncName ( Func , Subtarget ) ; FunctionCallee FCache = M . getOrInsertFunction ( MASSVEntryName , Func . getFunctionType ( ) , Func . getAttributes ( ) ) ; CI -> setCalledFunction ( FCache


<s> bool runOnMachineFunction ( MachineFunction & MF ) override { TII = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getInstrInfo ( ) ; LIS = & getAnalysis < LiveIntervals > ( ) ; bool Changed = false ; for ( MachineFunction :: iterator I = MF . begin ( ) ; I != MF . end ( ) ; ) { MachineBasicBlock & B = * I ++ ; if ( processBlock ( B ) ) Changed


<s> Parser . Lex ( ) ; if ( ParseOperand ( Operands , Name ) ) { SMLoc Loc = getLexer ( ) . getLoc ( ) ; Parser . eatToEndOfStatement ( ) ; return Error ( Loc , <STR_LIT> ) ; } if ( Parser . getTok ( ) . isNot ( AsmToken :: RParen ) ) { SMLoc Loc = getLexer ( ) . getLoc ( ) ; Parser . eatToEndOfStatement ( ) ; return Error ( Loc , <STR_LIT> ) ; } Operands . push_back ( <STR_LIT> ( <STR_LIT> , getLexer ( ) . getLoc ( ) , * this ) ) ; Parser . Lex ( ) ; } return false


<s> if ( ST -> isMisaligned128StoreSlow ( ) && Opcode == Instruction :: Store && LT . second . is128BitVector ( ) && ( ! Alignment || * Alignment < Align ( <NUM_LIT> ) ) ) { const int AmortizationCost = <NUM_LIT> ; return LT . first * <NUM_LIT> * AmortizationCost ; } if ( useNeonVector ( Ty ) && cast < VectorType > ( Ty ) -> getElementType ( ) -> isIntegerTy ( <NUM_LIT> ) ) { unsigned ProfitableNumElements ; if ( Opcode == Instruction :: Store ) ProfitableNumElements = <NUM_LIT> ; else ProfitableNumElements = <NUM_LIT> ; if ( cast < FixedVectorType > ( Ty ) -> getNumElements ( )


<s> SDLoc dl ( Op ) ; if ( ( ! Subtarget -> isThumb ( ) && Subtarget -> hasV6Ops ( ) ) || Subtarget -> isThumb2 ( ) ) if ( SDValue SatValue = LowerSaturatingConditional ( Op , DAG ) ) return SatValue ; SDValue LowerSatConstant ; SDValue SatValue ; if ( VT == <STR_LIT> && isLowerSaturatingConditional ( Op , SatValue , LowerSatConstant ) ) { SDValue ShiftV = DAG . getNode ( <STR_LIT> , dl , VT , SatValue , DAG . getConstant ( <NUM_LIT> , dl , VT ) ) ; if ( isNullConstant ( LowerSatConstant ) ) { SDValue NotShiftV = DAG . getNode ( <STR_LIT> , dl , VT , ShiftV , DAG . getAllOnesConstant ( dl , VT ) ) ; return DAG . getNode ( <STR_LIT> , dl , VT , SatValue , NotShiftV ) ; } else if ( isAllOnesConstant ( LowerSatConstant ) ) return DAG . getNode ( <STR_LIT> , dl , VT , SatValue , ShiftV ) ; } SDValue LHS = Op . getOperand ( <NUM_LIT> ) ; SDValue RHS = Op . getOperand ( <NUM_LIT> ) ; <STR_LIT> CC = cast < CondCodeSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> get ( ) ; SDValue TrueVal = Op . getOperand ( <NUM_LIT> ) ; SDValue FalseVal = Op . getOperand ( <NUM_LIT> ) ; ConstantSDNode * CFVal = dyn_cast < ConstantSDNode > ( FalseVal ) ; ConstantSDNode * CTVal = dyn_cast < ConstantSDNode > ( TrueVal ) ; if ( Subtarget -> hasV8_1MMainlineOps ( ) && CFVal && CTVal && LHS . getValueType ( ) == <STR_LIT> && RHS . getValueType ( ) == <STR_LIT> ) { unsigned TVal = CTVal -> getZExtValue ( ) ; unsigned FVal = CFVal -> getZExtValue ( ) ; unsigned Opcode = <NUM_LIT> ; if ( TVal == ~ FVal ) { Opcode = <STR_LIT> ; } else if ( TVal == ~ FVal + <NUM_LIT> ) { Opcode = <STR_LIT> ; } else if ( TVal + <NUM_LIT> == FVal ) { Opcode = <STR_LIT> ; } else if ( TVal == FVal + <NUM_LIT> ) { Opcode = <STR_LIT> ; std :: swap ( TrueVal , FalseVal ) ; std :: swap ( TVal , FVal ) ; CC = <STR_LIT> ( CC , LHS . getValueType ( ) ) ; } if (


<s> if ( ! usingDefaultRegAlloc ( ) ) report_fatal_error ( RegAllocOptNotSupportedMessage ) ; addPass ( createSGPRAllocPass (


<s> void <ISA_LIT>Z80FrameLowering :: emitEpilogue ( MachineFunction & MF , MachineBasicBlock & MBB ) const { CallingConv :: ID CallConv = MF . getFunction ( ) . getCallingConv ( ) ; MachineBasicBlock :: iterator MBBI = MBB . getLastNonDebugInstr ( ) ; assert ( MBBI -> getDesc ( ) . isReturn ( ) && <STR_LIT> ) ; DebugLoc DL = MBBI -> getDebugLoc ( ) ; const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const <ISA_LIT>Z80MachineFunctionInfo * AFI = MF . getInfo < <ISA_LIT>Z80MachineFunctionInfo > ( ) ; int FrameSize = MFI . getStackSize ( ) - AFI -> getCalleeSavedFrameSize ( ) ; const <ISA_LIT>Z80Subtarget & STI = MF . getSubtarget < <ISA_LIT>Z80Subtarget > ( ) ; const <ISA_LIT>Z80InstrInfo & TII = * STI . getInstrInfo ( ) ; if ( ! FrameSize ) { return ; } while ( MBBI != MBB . begin ( ) ) { MachineBasicBlock :: iterator PI = std :: prev ( MBBI ) ; int Opc = PI -> getOpcode ( ) ; if ( Opc != <STR_LIT> && ! PI -> isTerminator ( ) ) { break ; } -- MBBI ; } while ( FrameSize != <NUM_LIT> ) { int ToAdd = std :: min ( <NUM_LIT> , FrameSize ) ; MachineInstr * MI = BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) ) . addImm ( ToAdd

) . setMIFlag ( MachineInstr :: FrameDestroy ) ;


<s> initSubtargetFeatures ( CPU , FS ) ; return * this


<s> int64_t Shift = Inst . getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( Shift <= <NUM_LIT> ) return ; Shift -= <NUM_LIT> ; Inst . getOperand ( <NUM_LIT> ) . setImm ( Shift ) ; switch ( Inst . getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : Inst . setOpcode ( <STR_LIT> ) ; return ; case <STR_LIT> : Inst . setOpcode ( <STR_LIT> ) ; return ; case <STR_LIT> : Inst . setOpcode ( <STR_LIT> ) ; return ; case <STR_LIT> : Inst . setOpcode ( <STR_LIT> ) ; return ; case <STR_LIT> : Inst . setOpcode ( <STR_LIT> )


<s> <ISA_LIT>TargetStreamer & TS = getTargetStreamer ( ) ; if ( Subtarget -> isTargetNaCl ( ) ) EmitAlignment ( std :: max ( MF -> getAlignment ( ) , MIPS_NACL_BUNDLE_ALIGN ) ) ; if ( Subtarget -> inMicro<ISA_LIT>Mode ( ) ) TS . emitDirectiveSetMicro<ISA_LIT> ( ) ; else TS . emitDirectiveSetNoMicro<ISA_LIT> ( ) ; if ( Subtarget -> in<ISA_LIT>16Mode ( ) ) TS . emitDirectiveSet<ISA_LIT>16 ( ) ; else TS . emitDirectiveSetNo<ISA_LIT>16 ( ) ; TS . emitDirectiveEnt ( * CurrentFnSym ) ; OutStreamer . EmitLabel (


<s> return __builtin_mve_vctp32q_mhi ( __a ,


<s> SDValue <ISA_LIT>TargetLowering :: LowerConstantPool ( SDValue Op , SelectionDAG & DAG ) { SDValue ResNode ; ConstantPoolSDNode * N = cast < ConstantPoolSDNode > ( Op ) ; Constant * C = N -> getConstVal ( ) ; SDValue CP = DAG . getTargetConstantPool ( C , <STR_LIT> , N -> getAlignment ( ) ) ; DebugLoc dl = Op . getDebugLoc ( ) ; SDValue HiPart = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , CP ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , CP ) ; ResNode = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> ,


<s> f ( MI ) ; buildMI ( MBB , MBBI , <STR_LIT> ) . addImm ( SREG_ADDR ) . addReg ( SCRATCH_REGISTER ) ; MI . eraseFromParent ( ) ; return true


<s> Ops . push_back ( Chain ) ; std :: vector < EVT > ResTys ; ResTys . push_back ( <STR_LIT> ) ; ResTys . push_back ( <STR_LIT> ) ; SDNode * Ld = CurDAG -> getMachineNode ( Opc , dl , ResTys , Ops ) ; SDValue SuperReg = SDValue ( Ld , <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i < NumVecs ; ++ i ) ReplaceUses ( SDValue ( N , i ) , CurDAG -> getTargetExtractSubreg ( SubRegIdx + i


<s> void <ISA_LIT>FrameLowering :: updateEntryPaths ( MachineFunction & MF , MachineBasicBlock & SaveB ) const { SetVector < unsigned > Worklist ; MachineBasicBlock & EntryB = MF . front ( ) ; Worklist . insert ( EntryB . getNumber ( ) ) ; unsigned SaveN = SaveB . getNumber ( ) ; auto & CSI = MF . getFrameInfo ( ) . getCalleeSavedInfo ( ) ; for ( unsigned i = <NUM_LIT> ; i < Worklist . size ( ) ; ++ i ) { unsigned BN = Worklist [ i ] ; MachineBasicBlock & MBB = * MF . getBlockNumbered ( BN ) ; for ( auto & R : CSI ) if ( ! MBB . isLiveIn ( R . getReg ( ) ) ) MBB . addLiveIn ( R . getReg ( ) ) ; if ( BN != SaveN ) for ( auto & SB : MBB . successors ( ) ) Worklist .


<s> bool <ISA_LIT>FrameLowering :: hasReservedCallFrame ( const MachineFunction & MF


<s> builtin_define ( <STR_LIT> ) ; if ( TARGET_BIG_ENDIAN ) builtin_define ( <STR_LIT> ) ; else builtin_define ( <STR_LIT> ) ; { const char * version_code ; char * kernel_version_code ; switch ( bpf_kernel ) { case LINUX_V4_0 : version_code = <STR_LIT> ; break ; case LINUX_V4_1 : version_code = <STR_LIT> ; break ; case LINUX_V4_2 : version_code = <STR_LIT> ; break ; case LINUX_V4_3 : version_code = <STR_LIT> ; break ; case LINUX_V4_4 : version_code = <STR_LIT> ; break ; case LINUX_V4_5 : version_code = <STR_LIT> ; break ; case LINUX_V4_6 : version_code = <STR_LIT> ; break ; case LINUX_V4_7 : version_code = <STR_LIT> ; break ; case LINUX_V4_8 : version_code = <STR_LIT> ; break ; case LINUX_V4_9 : version_code = <STR_LIT> ; break ; case LINUX_V4_10 : version_code = <STR_LIT> ; break ; case LINUX_V4_11 : version_code = <STR_LIT> ; break ; case LINUX_V4_12 : version_code = <STR_LIT> ; break ; case LINUX_V4_13 : version_code = <STR_LIT> ; break ; case LINUX_V4_14 : version_code = <STR_LIT> ; break ; case LINUX_V4_15 : version_code = <STR_LIT> ;


<s> return llvm :: make_unique < <ISA_LIT>ELFObjectWriter > ( OSABI


<s> LastOpcodeType = OTHER ; LastInstWritesM0 = false ; ReturnsVoid = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) -> returnsVoid ( ) ; memset ( & UsedRegs , <NUM_LIT> , sizeof ( UsedRegs ) ) ; memset ( & DefinedRegs , <NUM_LIT> , sizeof ( DefinedRegs ) ) ; for ( MachineFunction :: iterator BI = MF . begin ( ) , BE = MF . end ( ) ; BI != BE ; ++ BI ) { MachineBasicBlock & MBB = * BI ; for ( MachineBasicBlock :: iterator I = MBB . begin ( ) , E


<s> if ( CONST_INT_P ( op2 ) ) { HOST_WIDE_INT n = trunc_int_for_mode ( INTVAL (


<s> bool opCanUseLiteralConstant ( unsigned OpType ) const { return OpType >= <STR_LIT> &&


<s> SchedModel ( SM ) , TotalPackets ( <NUM_LIT> ) { ResourcesModel = TM . getInstrInfo ( ) -> CreateTargetScheduleState ( & TM ,


<s> unsigned CC = I -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned regX = I -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned regY = I -> getOperand ( <NUM_LIT> )


<s> while ( ++ I != MBB . end ( ) ) { MachineInstr & MI


<s> return MIB . buildNot ( DstTy , FCmp ) . getReg ( <NUM_LIT> ) ; } ; case <STR_LIT> : return [ LHS , RHS , IsZero , DstTy ] ( MachineIRBuilder & MIB ) { return IsZero ? MIB . buildInstr ( <STR_LIT> , { DstTy } , { LHS } ) . getReg ( <NUM_LIT> ) : MIB . buildInstr ( <STR_LIT> , { DstTy } , { LHS , RHS } ) . getReg ( <NUM_LIT> ) ; } ; case <STR_LIT> : return [ LHS , RHS , IsZero , DstTy ] ( MachineIRBuilder & MIB ) { return IsZero ? MIB . buildInstr ( <STR_LIT> , { DstTy } , { LHS } ) . getReg ( <NUM_LIT> ) : MIB . buildInstr ( <STR_LIT> , { DstTy } , { LHS , RHS } ) . getReg ( <NUM_LIT> ) ; } ; case <STR_LIT> : return [ LHS , RHS , IsZero , DstTy ] ( MachineIRBuilder & MIB ) { return IsZero ? MIB . buildInstr ( <STR_LIT> , { DstTy } , { LHS } ) . getReg ( <NUM_LIT> ) : MIB . buildInstr ( <STR_LIT> , { DstTy } , { LHS , RHS } ) . getReg ( <NUM_LIT> ) ; } ; case <STR_LIT> : return [ LHS , RHS , IsZero , DstTy ] ( MachineIRBuilder & MIB ) { return IsZero ? MIB . buildInstr ( <STR_LIT> , { DstTy } , { LHS } ) . getReg ( <NUM_LIT> ) : MIB . buildInstr ( <STR_LIT> , { DstTy } , { RHS ,


<s> EFuncId getId ( ) const { return Impl -> getId (


<s> case <STR_LIT> : { assert ( ! Subtarget . is64Bit ( ) && <STR_LIT> ) ; SDVTList VTs = DAG . getVTList ( <STR_LIT> , <STR_LIT> , <STR_LIT> ) ; SDValue RCW = DAG . getNode ( <STR_LIT> , DL , VTs , N -> getOperand ( <NUM_LIT> ) ) ; Results . push_back ( RCW ) ; Results . push_back ( RCW . getValue ( <NUM_LIT> ) ) ; Results . push_back ( RCW . getValue ( <NUM_LIT> ) ) ; break ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : assert ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT> && Subtarget . is64Bit ( ) && <STR_LIT> ) ; if ( N -> getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) return ; Results . push_back ( customLegalizeToWOp ( N , DAG ) ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : assert ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT> && Subtarget . is64Bit ( ) && Subtarget . hasStdExtM ( ) && <STR_LIT> ) ; if ( N -> getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> || N -> getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) return ; Results . push_back ( customLegalizeToWOp ( N , DAG ) ) ; break ; case <STR_LIT> : { assert ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT> && Subtarget . is64Bit ( ) && Subtarget . hasStdExtF ( ) && <STR_LIT> ) ; SDLoc DL ( N ) ; SDValue Op0 = N -> getOperand ( <NUM_LIT> ) ; if ( Op0 . getValueType ( ) != <STR_LIT> )


<s> static MCInstPrinter * create<ISA_LIT>MCInstPrinter ( const Triple & T , unsigned SyntaxVariant , const MCAsmInfo & MAI , const MCInstrInfo & MII , const MCRegisterInfo & MRI ) { if ( SyntaxVariant == <NUM_LIT> ) return ( new <ISA_LIT>InstPrinter ( MAI , MII , MRI ) ) ; else return nullptr


<s> Inst . addOperand ( MCOperand :: CreateImm


<s> void <ISA_LIT>SchedStrategy :: initialize ( ScheduleDAGMI * dag ) { assert ( dag -> hasVRegLiveness ( ) && <STR_LIT> ) ; DAG = static_cast < ScheduleDAGMILive * > ( dag ) ; const <ISA_LIT>Subtarget & ST = DAG -> MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; TII = static_cast < const <ISA_LIT>InstrInfo * > ( DAG -> TII ) ; TRI = static_cast < const <ISA_LIT>RegisterInfo * > ( DAG -> TRI ) ; VLIW5 = ! ST . hasCaymanISA ( ) ; MRI = & DAG -> MRI ; CurInstKind = IDOther ; CurEmitted = <NUM_LIT> ; OccupiedSlotsMask = <NUM_LIT> ; InstKindLimit [ IDAlu ] = TII -> getMaxAlusPerClause ( ) ; InstKindLimit [ IDOther ] = <NUM_LIT> ; InstKindLimit [ IDFetch ] = ST . getTexVTXClauseSize