<s> const ArgDescriptor * Arg ; const TargetRegisterClass * RC ; LLT ArgTy ; std :: tie ( Arg , RC , ArgTy ) = MFI -> getPreloadedValue ( ArgType ) ; if ( ! Arg ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return nullptr


<s> Size = <NUM_LIT> ; return Fail ; } uint8_t DecodeByte = ( Bytes [ <NUM_LIT> ] & <NUM_LIT> ) >> <NUM_LIT> ; if ( DecodeByte < <NUM_LIT> ) { if ( Bytes . size ( ) < <NUM_LIT> ) { Size = <NUM_LIT> ; return Fail ; } if ( Bytes . size ( ) >= <NUM_LIT> ) { uint64_t Insn64 ; if ( ! readInstruction64 ( Bytes , Address , Size , Insn64 ) ) return Fail ; Result = decodeInstruction ( DecoderTable64 , Instr , Insn64 , Address , this , STI ) ; if ( Success == Result ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return Result ; } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; } uint32_t Insn32 ; if ( ! readInstruction32 ( Bytes , Address , Size , Insn32 ) ) { return Fail ; } return decodeInstruction ( DecoderTable32 , Instr , Insn32 , Address , this , STI ) ; } else { if ( Bytes . size ( ) >= <NUM_LIT> ) { uint64_t Insn48 ; if ( ! readInstruction48 ( Bytes , Address , Size , Insn48 ) ) return Fail ; Result = decodeInstruction ( DecoderTable48 , Instr , Insn48 , Address , this , STI ) ; if ( Success == Result ) { LLVM_DEBUG ( dbgs (


<s> unsigned Len = End . getPointer ( ) - TypeLoc . getPointer ( ) ; InstInfo -> AsmRewrites -> push_back ( AsmRewrite ( AOK_Imm , TypeLoc , Len , Size ) ) ; const MCExpr * Imm = MCConstantExpr :: Create ( Size , getContext ( ) ) ; return <STR_LIT> ( Imm , Start , End


<s> void <ISA_LIT>PassConfig :: addIRPasses ( ) { addPass ( create<ISA_LIT>AtomicExpandPass ( & get<ISA_LIT>TargetMachine


<s> if ( Triple ( TT ) . isOSDarwin ( ) ) return new Darwin<ISA_LIT>AsmBackend ( T ) ; return new ELF<ISA_LIT>AsmBackend ( T , Triple ( TT


<s> MachineBasicBlock * MBB = MI -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; MI -> RemoveOperand ( <NUM_LIT> ) ; MI -> setDesc ( get ( <STR_LIT> ) ) ; MachineInstrBuilder ( * MI -> getParent ( ) -> getParent ( ) , MI ) . addImm ( Pred [ <NUM_LIT> ] . getImm ( ) ) . addReg ( Pred [ <NUM_LIT> ] . getReg ( ) ) . addMBB ( MBB ) ; } return true ; } else if ( OpC == <STR_LIT> || OpC == <STR_LIT> || OpC == <STR_LIT> || OpC == <STR_LIT> ) { if ( Pred [ <NUM_LIT> ] . getReg ( ) == <STR_LIT> || Pred [ <NUM_LIT> ] . getReg ( ) == <STR_LIT> ) llvm_unreachable ( <STR_LIT> ) ; bool setLR = OpC == <STR_LIT> || OpC == <STR_LIT> ; bool is<ISA_LIT>64 = TM . getSubtargetImpl ( ) -> is<ISA_LIT>64 ( ) ; MI -> setDesc ( get ( is<ISA_LIT>64 ? ( setLR ? <STR_LIT> : <STR_LIT> ) : ( setLR ? <STR_LIT> : <STR_LIT> )


<s> if ( x > <NUM_LIT> ) return f_ginv ; } f_ginv . map = ( f_ginv . map << <NUM_LIT> ) + x ; } if ( avr_map_metric ( f_ginv . map , MAP_NONFIXED_0_7 ) == <NUM_LIT> ) f_ginv . cost = <NUM_LIT> + ( val_used_p && ! val_const_p ) ; else { rtx xop [ <NUM_LIT> ] ; xop [ <NUM_LIT> ] = all_regs_rtx [ <NUM_LIT> ] ; xop [ <NUM_LIT> ] = gen_int_mode ( f_ginv . map , SImode ) ; xop [ <NUM_LIT> ] = all_regs_rtx [ <NUM_LIT> ] ; xop [ <NUM_LIT> ] = val_used_p ? xop [ <NUM_LIT> ] : const0_rtx ; avr_out_insert_bits ( xop , & f_ginv .


<s> const BasicBlock * BB = FuncInfo -> MBB -> getBasicBlock ( ) ; return BB -> getTerminator ( ) -> getMetadata ( <STR_LIT>


<s> fprintf ( file , <STR_LIT> , cfun -> machine -> local_size ) ; fprintf ( file , <STR_LIT> , cfun -> machine -> out_args_size ) ; fprintf ( file , <STR_LIT> ) ; for ( r = <NUM_LIT> ; r < <NUM_LIT> ; r ++ ) { if ( df_regs_ever_live_p ( r ) ) fprintf ( file , <STR_LIT> , reg_names [ r ] ) ; } fputc ( '\n' , file ) ; fprintf ( file , <STR_LIT> ) ; attrs = DECL_ATTRIBUTES ( current_function_decl ) ; if ( ! attrs ) fprintf ( file , <STR_LIT> ) ; func_name = IDENTIFIER_POINTER ( DECL_NAME ( current_function_decl ) ) ; nds32_construct_isr_vectors_information ( attrs , func_name ) ; while ( attrs ) { name = TREE_PURPOSE ( attrs ) ; fprintf ( file , <STR_LIT> ,


<s> while ( true ) { DEBUG ( dbgs ( ) << <STR_LIT> << NoCPIters << '\n' ) ; bool CPChange = false ; for ( unsigned i = <NUM_LIT> , e = CPUsers . size ( ) ; i != e ; ++ i ) CPChange |= handleConstantPoolUser ( i ) ; if ( CPChange && ++ NoCPIters > <NUM_LIT> ) report_fatal_error ( <STR_LIT> ) ; DEBUG ( dumpBBs ( ) ) ; NewWaterList . clear ( ) ; DEBUG ( dbgs ( ) << <STR_LIT> << NoBRIters << '\n' ) ; bool BRChange = false ; for ( unsigned i = <NUM_LIT> , e = ImmBranches . size ( ) ; i != e ; ++ i ) BRChange |= fixupImmediateBr ( ImmBranches [ i ] ) ; if ( BRChange && ++ NoBRIters > <NUM_LIT> ) report_fatal_error ( <STR_LIT> ) ; DEBUG ( dumpBBs ( ) ) ; if ( ! CPChange && ! BRChange ) break ; MadeChange = true ; } DEBUG ( dbgs ( ) << '\n' ; dumpBBs ( ) ) ; BBInfo . clear ( ) ; WaterList . clear ( ) ; CPUsers . clear ( ) ; CPEntries . clear ( ) ; ImmBranches . clear


<s> bool isCompute ( CallingConv :: ID cc


<s> signed_width ( Size + <NUM_LIT> , Value , std :: string


<s> static bool xstormy16_function_value_regno_p ( const unsigned int regno ) { return ( regno == RETURN_VALUE_REGNUM )


<s> if ( ! SrcTy -> isIntegerTy ( ) || ! DstTy -> isIntegerTy ( ) ) return false ; return SrcTy -> getPrimitiveSizeInBits ( ) >


<s> MachineFrameInfo & MFI = * MF . getFrameInfo ( ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( PseudoSourceValue :: getFixedStack ( FI ) , MachineMemOperand :: MOStore , <NUM_LIT> , MFI . getObjectSize ( FI ) , MFI . getObjectAlignment ( FI ) ) ; AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( isKill

) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ) ;


<s> if ( ! Parser . getTok ( ) . getString ( ) . equals_lower ( <STR_LIT> ) || ! ( NextIsVL || NextIsHash ) ) return true ; Operands . push_back ( <ISA_LIT>Operand :: CreateToken ( <STR_LIT> , false , getLoc ( ) , getContext ( ) ) ) ; Parser . Lex ( ) ; if ( NextIsVL ) { Operands . push_back ( <ISA_LIT>Operand :: CreateToken ( <STR_LIT> , false , getLoc ( ) , getContext ( ) ) ) ; Parser . Lex ( ) ; return false ; } if ( NextIsHash ) { Parser . Lex ( ) ; SMLoc S = getLoc ( ) ; const MCExpr * ImmVal ; if ( ! Parser . parseExpression ( ImmVal ) ) if ( const MCConstantExpr * MCE = dyn_cast < MCConstantExpr > ( ImmVal ) ) { Operands . push_back ( <ISA_LIT>Operand :: CreateImm ( MCConstantExpr :: create ( MCE -> getValue ( ) , getContext ( ) ) , S , getLoc ( ) , getContext ( ) ) ) ; return MatchOperand_Success ; } } return Error ( getLoc ( )


<s> if ( ST -> hasAVX ( ) ) return <NUM_LIT> ; return <NUM_LIT>


<s> if ( Size <= <NUM_LIT> && ST -> has16BitInsts ( ) ) return false ; if ( DA -> isUniform ( & I ) ) return false ; Value * LHS = I . getOperand ( <NUM_LIT> ) ; Value * RHS = I . getOperand ( <NUM_LIT> ) ; IRBuilder < > Builder ( & I ) ; Builder . SetCurrentDebugLocation ( I . getDebugLoc ( ) ) ; unsigned LHSBits = <NUM_LIT> , RHSBits = <NUM_LIT> ; bool IsSigned = false ; if ( ST -> hasMulU24 ( ) && ( LHSBits = numBitsUnsigned ( LHS , Size ) ) <= <NUM_LIT> && ( RHSBits = numBitsUnsigned ( RHS , Size ) ) <= <NUM_LIT> ) { IsSigned = false ; } else if ( ST -> hasMulI24 ( ) && ( LHSBits = numBitsSigned ( LHS , Size ) ) <= <NUM_LIT> && ( RHSBits = numBitsSigned ( RHS , Size ) ) <= <NUM_LIT> ) { IsSigned = true ; } else return false ; SmallVector < Value * , <NUM_LIT> > LHSVals ; SmallVector < Value * , <NUM_LIT> > RHSVals ; SmallVector < Value * , <NUM_LIT> > ResultVals ; extractValues ( Builder , LHSVals , LHS ) ; extractValues ( Builder , RHSVals , RHS ) ; IntegerType * I32Ty = Builder . getInt32Ty ( ) ; for ( int I = <NUM_LIT> , E = LHSVals . size ( ) ; I != E ; ++ I ) { Value * LHS , * RHS ; if ( IsSigned ) { LHS = Builder . CreateSExtOrTrunc ( LHSVals [ I ] , I32Ty ) ; RHS = Builder . CreateSExtOrTrunc ( RHSVals [ I ] , I32Ty ) ; } else { LHS = Builder . CreateZExtOrTrunc ( LHSVals [ I ] , I32Ty ) ; RHS = Builder . CreateZExtOrTrunc ( RHSVals [ I ] , I32Ty ) ; } Value * Result = getMul24 ( Builder , LHS , RHS , Size , LHSBits + RHSBits , IsSigned ) ; if ( IsSigned ) { ResultVals . push_back ( Builder . CreateSExtOrTrunc ( Result , LHSVals [ I ] -> getType ( ) ) ) ; } else { ResultVals . push_back ( Builder . CreateZExtOrTrunc ( Result , LHSVals [ I ] -> getType ( ) ) ) ; } } Value * NewVal = insertValues ( Builder , Ty , ResultVals ) ; NewVal -> takeName ( & I ) ; I . replaceAllUsesWith ( NewVal


<s> static tree csky_floatHF_type_node = make_node ( REAL_TYPE ) ; TYPE_PRECISION ( csky_floatHF_type_node ) = GET_MODE_PRECISION ( HFmode ) ; layout_type ( csky_floatHF_type_node ) ; ( * lang_hooks . types . register_builtin_type ) ( csky_floatHF_type_node ,


<s> Info . OneUser = false ; Info . MultiUsers = false ; Info . LastADRP


<s> void tilegx_pre_atomic_barrier ( enum


<s> shmask . v = ( ( vec_uint4 ) { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ; shmask . c [ si_to_uint ( ( qword ) ( vec_add ( ( vec_uint4 ) ( a ) , ( vec_uint4 ) ( b ) ) ) ) & <NUM_LIT> ] = <NUM_LIT> ; return ( ( qword ) ( shmask . v


<s> DAG = static_cast < VLIWMachineScheduler * > ( dag ) ; SchedModel = DAG -> getSchedModel ( ) ; Top . init ( DAG , SchedModel ) ; Bot . init ( DAG , SchedModel ) ; const InstrItineraryData * Itin = DAG -> getSchedModel ( ) -> getInstrItineraries ( ) ; const TargetMachine & TM = DAG -> MF . getTarget ( ) ; delete Top . HazardRec ; delete Bot . HazardRec ; Top . HazardRec = TM . getSubtargetImpl ( ) -> getInstrInfo ( ) -> CreateTargetMIHazardRecognizer ( Itin , DAG ) ; Bot . HazardRec = TM . getSubtargetImpl ( ) -> getInstrInfo ( ) -> CreateTargetMIHazardRecognizer ( Itin , DAG ) ; delete Top . ResourceModel ; delete Bot


<s> if ( width == <NUM_LIT> ) return <NUM_LIT> ; if ( ( ix86_tune == PROCESSOR_ZNVER1 || ix86_tune == PROCESSOR_ZNVER2 || ix86_tune == PROCESSOR_ZNVER3 ) && INTEGRAL_MODE_P ( mode ) && op != PLUS && op != MINUS ) return <NUM_LIT> ; if ( TARGET_AVX256_SPLIT_REGS && GET_MODE_BITSIZE ( mode ) > <NUM_LIT> ) div = GET_MODE_BITSIZE ( mode ) / <NUM_LIT> ; else if ( TARGET_SSE_SPLIT_REGS && GET_MODE_BITSIZE ( mode ) > <NUM_LIT> ) div = GET_MODE_BITSIZE ( mode ) / <NUM_LIT> ; width = ( width + div


<s> emit_move_insn ( scratch , mem ) ; if ( TARGET_64BIT ) emit_insn ( gen_adddi3 ( out , out , GEN_INT ( <NUM_LIT> ) ) ) ; else emit_insn ( gen_addsi3 ( out , out , GEN_INT ( <NUM_LIT> ) ) ) ; emit_insn ( gen_addsi3 ( tmpreg , scratch , GEN_INT ( - <NUM_LIT> ) ) ) ; emit_insn ( gen_one_cmplsi2 ( scratch , scratch ) ) ; emit_insn ( gen_andsi3 ( tmpreg , tmpreg , scratch ) ) ; emit_insn ( gen_andsi3 ( tmpreg , tmpreg , gen_int_mode ( <NUM_LIT> , SImode ) ) ) ; emit_cmp_and_jump_insns ( tmpreg , const0_rtx , EQ , <NUM_LIT> , SImode , <NUM_LIT> , align_4_label ) ; if ( TARGET_CMOVE ) { rtx reg = gen_reg_rtx ( SImode ) ; rtx reg2 = gen_reg_rtx ( Pmode ) ; emit_move_insn ( reg , tmpreg ) ; emit_insn ( gen_lshrsi3 ( reg , reg , GEN_INT ( <NUM_LIT> ) ) ) ; emit_insn ( gen_testsi_ccno_1 ( tmpreg , GEN_INT ( <NUM_LIT> ) ) ) ; tmp = gen_rtx_REG ( CCNOmode , FLAGS_REG ) ; tmp = gen_rtx_EQ ( VOIDmode , tmp , const0_rtx ) ; emit_insn ( gen_rtx_SET ( VOIDmode , tmpreg , gen_rtx_IF_THEN_ELSE ( SImode , tmp , reg , tmpreg ) ) ) ; emit_insn ( gen_rtx_SET ( SImode , reg2 , gen_rtx_PLUS ( Pmode , out , const2_rtx ) ) ) ; tmp = gen_rtx_REG ( CCNOmode , FLAGS_REG ) ; tmp = gen_rtx_EQ ( VOIDmode , tmp , const0_rtx ) ; emit_insn ( gen_rtx_SET ( VOIDmode , out , gen_rtx_IF_THEN_ELSE ( Pmode , tmp , reg2 , out ) ) ) ; } else { rtx end_2_label = gen_label_rtx ( ) ; emit_insn ( gen_testsi_ccno_1 ( tmpreg , GEN_INT ( <NUM_LIT> ) ) ) ; tmp = gen_rtx_REG ( CCNOmode , FLAGS_REG ) ; tmp = gen_rtx_NE ( VOIDmode , tmp , const0_rtx ) ; tmp = gen_rtx_IF_THEN_ELSE ( VOIDmode , tmp , gen_rtx_LABEL_REF ( VOIDmode , end_2_label ) , pc_rtx ) ; tmp = emit_jump_insn ( gen_rtx_SET ( VOIDmode , pc_rtx , tmp ) ) ; JUMP_LABEL ( tmp ) = end_2_label ; emit_insn ( gen_lshrsi3 ( tmpreg , tmpreg , GEN_INT ( <NUM_LIT> ) ) ) ; if ( TARGET_64BIT ) emit_insn ( gen_adddi3 ( out , out , const2_rtx ) ) ; else emit_insn ( gen_addsi3 ( out , out , const2_rtx ) ) ; emit_label ( end_2_label ) ; } tmpreg = gen_lowpart ( QImode , tmpreg ) ; emit_insn ( gen_addqi3_cc ( tmpreg , tmpreg , tmpreg ) ) ; cmp = gen_rtx_LTU ( Pmode , gen_rtx_REG ( CCmode , <NUM_LIT> )


<s> unsigned getExplicitKernelArgOffset ( ) const { return isAmdHsaOS ( ) ? <NUM_LIT> :


<s> } else if ( isCondBranchOpcode ( I -> getOpcode ( ) ) ) { if ( ! Cond . empty ( ) ) return true ; assert ( ! FBB && <STR_LIT> ) ; FBB = TBB ; TBB = I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; Cond . push_back ( I -> getOperand ( <NUM_LIT> ) ) ; Cond . push_back ( I -> getOperand ( <NUM_LIT> ) ) ; Cond . push_back ( I -> getOperand ( <NUM_LIT> ) ) ; } else if ( I -> isReturn ( ) ) { CantAnalyze = ! isPredicated ( * I ) ; } else { return true ; } if ( ! isPredicated ( * I ) && ( isUncondBranchOpcode ( I -> getOpcode ( ) ) || isJumpOpcode ( I -> getOpcode ( ) ) || I -> isReturn ( ) ) ) { Cond . clear ( ) ; FBB = nullptr ; if ( AllowModify ) { MachineBasicBlock :: iterator DI = std :: next ( I ) ; while ( DI != MBB . end ( ) ) { MachineInstr & InstToDelete = * DI ; ++ DI


<s> bool <ISA_LIT>InstrInfo :: isMovDualGroup ( const MachineInstr & MI , unsigned * pSrcG , unsigned * pDstG ) const { if ( MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> ) { const MachineOperand & Op = MI . getOperand ( <NUM_LIT> ) ; unsigned Sw = Op . getImm ( ) ; if ( Sw != <ISA_LIT>II :: SW_MDG_TYPE_SINGLE ) return false ; * pSrcG = ( Sw & <ISA_LIT>II :: SW_SRC_DUAL_GROUP ) >> <ISA_LIT>II :: SW_SRC_DUAL_GROUP_SHIFT ; * pDstG = ( Sw & <ISA_LIT>II :: SW_DST_DUAL_GROUP ) >> <ISA_LIT>II :: SW_DST_DUAL_GROUP_SHIFT ; return


<s> return isMemOp ( ) && MemOp . Op == <STR_LIT> :: RegIndirectDisplacement && <STR_LIT> .


<s> void \ rdata_section ( ) \ { \ if ( in_section != in_rdata ) \ { \ if ( mips_abi != ABI_32 && mips_abi != ABI_O64 ) \ fprintf ( asm_out_file ,

<STR_LIT> , CONST_SECTION_ASM_OP_64 ) ; \ else \ fprintf ( asm_out_file , <STR_LIT> , CONST_SECTION_ASM_OP_32 ) ; \ in_section = in_rdata ; \ } \ }


<s> static __inline unsigned long long sh_media_MADD_W ( unsigned long long mm , unsigned long long mn ) { typedef float v4hi __attribute__ ( ( mode ( V4HI ) ) ) ; return ( unsigned long long ) __builtin_addv4hi3 ( ( v4hi ) mm , ( v4hi )


<s> unsigned ArgSize = ArgVT . getSizeInBits ( ) / <NUM_LIT> ; if ( Flags . isByVal ( ) ) ArgSize


<s> unsigned Reg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; const TargetRegisterClass * RC = MRI . getRegClass ( Reg ) ; if ( RC == & <STR_LIT> ) MRI . setRegClass ( Reg , & <STR_LIT> ) ; continue ; } if ( MI . getOpcode ( ) != <STR_LIT> ) continue ; const MachineOperand & Dst = MI . getOperand ( <NUM_LIT> ) ; const MachineOperand & Src = MI . getOperand ( <NUM_LIT> ) ; if ( ! TargetRegisterInfo :: isVirtualRegister ( Src . getReg ( ) ) || ! TargetRegisterInfo :: isVirtualRegister ( Dst . getReg ( ) ) ) continue ; const TargetRegisterClass * DstRC = MRI . getRegClass ( Dst . getReg ( ) ) ; const TargetRegisterClass * SrcRC = MRI . getRegClass ( Src . getReg ( ) ) ; DebugLoc DL = MI . getDebugLoc ( ) ; MachineInstr * DefInst = MRI . getUniqueVRegDef ( Src . getReg ( ) ) ; if ( DstRC == & <STR_LIT> && TRI -> getCommonSubClass ( SrcRC , & <STR_LIT> ) ) { I1Defs . push_back ( Dst . getReg ( ) ) ; if ( DefInst -> getOpcode ( ) == <STR_LIT> ) { if ( DefInst -> getOperand ( <NUM_LIT> ) . isImm ( ) ) { I1Defs . push_back ( Dst . getReg ( ) ) ; int64_t Val = DefInst -> getOperand (


<s> getBranchTargetOpValueMM ( const MCInst & MI , unsigned OpNo , SmallVectorImpl < MCFixup > & Fixups ) const { const MCOperand & MO = MI . getOperand (


<s> static inline int64_t __ev_convert_s64 ( __ev64_opaque__ a ) { return ( int64_t )


<s> void * getAdjustedAnalysisPointer ( const void * ID


<s> unsigned <ISA_LIT>FrameLowering :: getWinEHParentFrameOffset ( const MachineFunction & MF ) const { return


<s> if ( al == NULL ) { size_t buf_len ; char * linksym ; tree id ; if ( name [ <NUM_LIT> ] == '*' ) name ++ ; id = maybe_get_identifier ( name ) ; if ( id ) { while ( IDENTIFIER_TRANSPARENT_ALIAS ( id ) ) id = TREE_CHAIN ( id ) ; name = IDENTIFIER_POINTER ( id ) ; } buf_len = strlen ( name ) + <NUM_LIT> + <NUM_LIT> ; linksym = ( char * ) alloca ( buf_len ) ; snprintf ( linksym , buf_len , <STR_LIT> , cfun -> funcdef_no , name ) ; al = ggc_alloc <


<s> int gregs = ( code & <NUM_LIT> ) != <NUM_LIT> ; unsigned char mask = ( code & <NUM_LIT> ) ; if ( gregs ) UNW_DEC_GR_MEM ( P6 , mask


<s> void fr30_setup_incoming_varargs ( cumulative_args_t arg_regs_used_so_far_v , const function_arg_info & arg , int * pretend_size , int second_time ATTRIBUTE_UNUSED ) { CUMULATIVE_ARGS * arg_regs_used_so_far = get_cumulative_args ( arg_regs_used_so_far_v ) ; int size ; if ( ! TYPE_NO_NAMED_ARGS_STDARG_P ( TREE_TYPE ( current_function_decl ) ) ) { gcc_assert ( arg . mode != BLKmode ) ; if ( targetm . calls . strict_argument_naming ( arg_regs_used_so_far_v ) ) arg_regs_used_so_far +=


<s> static unsigned countMCSymbolRefExpr ( const MCExpr * Expr ) { if ( isa < MCSymbolRefExpr > ( Expr ) ) return <NUM_LIT> ; if ( const MCBinaryExpr * BExpr = dyn_cast < MCBinaryExpr > ( Expr ) ) return countMCSymbolRefExpr ( BExpr -> getLHS ( ) ) + countMCSymbolRefExpr ( BExpr -> getRHS ( ) ) ; if ( const MCUnaryExpr * UExpr = dyn_cast < MCUnaryExpr > ( Expr ) ) return countMCSymbolRefExpr ( UExpr -> getSubExpr ( ) ) ; return


<s> <ISA_LIT>_CCState :: <ISA_LIT>_CCState ( CallingConv :: ID CC , bool isVarArg , const TargetMachine & tm , SmallVector < CCValAssign , <NUM_LIT> > & locs , LLVMContext & c ) : CallingConv ( CC ) , IsVarArg ( isVarArg ) ,

TM ( tm ) , Locs ( locs ) , Context ( c ) {


<s> static void initiate_bundle_state_table ( void


<s> bool <ISA_LIT>TargetLowering :: isTruncateFree ( EVT VT1 , EVT VT2 ) const { if ( ! VT1 . isSimple ( ) || ! VT2 . isSimple ( ) ) return false ; return ( VT1 . getSimpleVT ( ) == <STR_LIT> ) && ( VT2 . getSimpleVT ( )


<s> static DecodeStatus decodeOperand_f16kimm ( MCInst & Inst , unsigned Imm , uint64_t Addr


<s> DEBUG ( dbgs ( ) << <STR_LIT> << RC -> getName ( ) << <STR_LIT> ) ; DEBUG ( dbgs ( ) << <STR_LIT> << MRI . isLiveIn ( reg ) << <STR_LIT> ) ; const MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; for ( MachineRegisterInfo :: livein_iterator LI = MRI . livein_begin ( ) , LE = MRI . livein_end ( ) ; LI != LE ; ++ LI ) { DEBUG ( dbgs ( ) << PrintReg ( LI -> second ) << <STR_LIT> << PrintReg ( LI -> first , TRI ) << <STR_LIT> ) ; } llvm_unreachable ( <STR_LIT> ) ; return - <NUM_LIT>


<s> inline bool <ISA_LIT>DAGToDAGISel :: SelectAnyImm2 ( SDValue & N , SDValue & R ) { return SelectAnyImmediate ( N , R ,


<s> void <ISA_LIT>TargetStreamer :: emitFnEnd


<s> <STR_LIT> CC = cast < CondCodeSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> get ( ) ; SDValue TrueVal = Op . getOperand ( <NUM_LIT> ) ; SDValue FalseVal = Op . getOperand ( <NUM_LIT> ) ; SDLoc dl ( Op ) ; unsigned Opc , <ISA_LIT>CC = ~ <NUM_LIT> ; LookThroughSetCC ( LHS , RHS , CC , <ISA_LIT>CC ) ; SDValue CompareFlag ; if ( LHS . getValueType ( ) . isInteger ( ) ) { CompareFlag = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , LHS , RHS ) ; Opc = LHS . getValueType ( ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; if ( <ISA_LIT>CC == ~ <NUM_LIT> ) <ISA_LIT>CC = IntCondCCodeToICC ( CC ) ; } else { if ( ! hasHardQuad && LHS . getValueType


<s> RegisterTargetMachine < <ISA_LIT>TargetMachine > X (


<s> if ( ! isMemory ( ) || ! Memory . OffsetRegNum || Memory . Alignment != <NUM_LIT> ) return false ; return true


<s> case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : { unsigned ConstraintID = InlineAsm :: getMemoryConstraintID ( MO . getImm ( ) ) ; switch ( ConstraintID ) { case InlineAsm :: Constraint_ZC : { const <ISA_LIT>Subtarget & Subtarget = MO . getParent ( ) -> getParent ( ) -> getParent ( ) -> getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( Subtarget . inMicro<ISA_LIT>Mode ( ) ) return <NUM_LIT> ; if ( Subtarget . has<ISA_LIT>32r6 ( ) ) return <NUM_LIT> ; return <NUM_LIT> ; } default : return <NUM_LIT>


<s> bool isCondBr ( ) const { return Kind == Expression || ( Kind == Immediate && isInt < <NUM_LIT>

> ( getImm ( ) ) && ( getImm ( ) & <NUM_LIT> ) == <NUM_LIT> ) ; }


<s> unsigned int alignment = <NUM_LIT> ; for ( tree field = TYPE_FIELDS ( type ) ; field ; field = DECL_CHAIN ( field ) ) if ( TREE_CODE ( field ) == FIELD_DECL ) alignment = std :: max ( alignment , DECL_ALIGN ( field ) ) ; return alignment


<s> return Kind == k_PostIndexRegister && PostIdxReg


<s> O << <STR_LIT> ; printRegName ( O , MI -> getOperand ( OpNum ) . getReg ( ) ) ; O << <STR_LIT> ; printRegName ( O , MI -> getOperand ( OpNum ) . getReg ( ) + <NUM_LIT> ) ; O <<


<s> if ( abi_id == ABI_VZEROUPPER ) return ( GET_MODE_SIZE ( mode ) > <NUM_LIT> && ( ( TARGET_64BIT && REX_SSE_REGNO_P ( regno ) ) || LEGACY_SSE_REGNO_P ( regno ) ) ) ; return SSE_REGNO_P ( regno ) && GET_MODE_SIZE (


<s> SDValue <ISA_LIT>TargetLowering :: lowerGlobalTLSAddress ( SDValue Op , SelectionDAG &


<s> TripCountPattern ( Instruction * P , Value * TC , VectorType * VT ) :

Predicate ( P ) , TripCount ( TC ) , VecTy ( VT ) { }


<s> bool shouldSignReturnAddress ( bool SpillsLR ) const { if ( ! SignReturnAddress ) return


<s> else if ( VT == <STR_LIT> ) IsLegal = <STR_LIT> ( Imm ) != - <NUM_LIT> ; else if ( VT == <STR_LIT> && Subtarget -> hasFullFP16 ( ) ) IsLegal = <STR_LIT> ( Imm ) != - <NUM_LIT> ; if ( IsLegal ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << VT . getEVTString ( ) << <STR_LIT> << ImmStrVal << <STR_LIT> ) ; return


<s> const TargetFrameLowering * TFI = getFrameLowering ( MF ) ; return TFI -> hasFP ( MF )


<s> const <ISA_LIT>MachineFunctionInfo * MFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; unsigned Occupancy = ST . getOccupancyWithLocalMemSize ( MFI -> getLDSSize ( ) , MF . getFunction ( ) ) ; switch ( RC -> getID ( ) ) { default : return <ISA_LIT>GenRegisterInfo :: getRegPressureLimit ( RC , MF ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> Value * <ISA_LIT>IREmitter :: visitANDNP ( const SDNode


<s> if ( recog_memoized ( insn ) >= <NUM_LIT> ) return get_attr_type ( insn ) ; else return


<s> uint16x8_t result ; __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a )


<s> void printf64mem ( const MCInst * MI , unsigned OpNo ) { printMemReference ( MI


<s> } else { MergeInstr = findIncDecAfter ( MBBI , Base , Pred , PredReg , Offset ) ; if ( ( ( Mode != <STR_LIT> && Mode != <STR_LIT> ) || Offset != Bytes ) && ( ( Mode != <STR_LIT> && Mode != <STR_LIT> ) || Offset != - Bytes ) ) return false ; } MBB . erase ( MergeInstr ) ; unsigned NewOpc = getUpdatingLSMultipleOpcode ( Opcode , Mode ) ; MachineInstrBuilder MIB = BuildMI ( MBB , MBBI , DL , TII -> get ( NewOpc ) ) . addReg ( Base , getDefRegState ( true ) ) . addReg ( Base , getKillRegState ( BaseKill ) ) . addImm ( Pred ) . addReg ( PredReg ) ; for ( unsigned OpNum = <NUM_LIT> , e = MI -> getNumOperands ( ) ; OpNum != e ; ++ OpNum ) MIB . addOperand ( MI -> getOperand ( OpNum ) ) ; MIB -> setMemRefs ( MI -> memoperands_begin ( ) , MI -> memoperands_end (


) _mm512_undefined_epi32 ( ) , ( __mmask8 ) - <NUM_LIT> ) ;


<s> bool isUImm20LUI ( ) const { <ISA_LIT>MCExpr :: VariantKind VK ; int64_t Imm ; bool IsValid ; if ( ! isImm ( ) ) return false ; bool IsConstantImm = evaluateConstantImm ( Imm , VK ) ; if ( ! IsConstantImm ) { IsValid = <ISA_LIT>AsmParser :: classifySymbolRef ( getImm ( ) , VK , Imm ) ; return IsValid && VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_HI ; }


<s> SymGOTMap & getSymGOTPLTMap ( ) { return m_SymGOTPLTMap


<s> if ( flags & SECTION_CODE ) smclass = <NUM_LIT> ; else if ( flags & SECTION_WRITE ) smclass = <NUM_LIT> ; else smclass = <NUM_LIT> ; fprintf ( asm_out_file , <STR_LIT> , ( flags & SECTION_CODE ) ? <STR_LIT> :

<STR_LIT> , name , suffix [ smclass ] , flags & SECTION_ENTSIZE ) ;


<s> } } next_arg_reg = iq2000_function_arg ( args_so_far , VOIDmode , void_type_node , true ) ; if ( next_arg_reg != <NUM_LIT> && GET_CODE ( next_arg_reg ) == PARALLEL ) { rtvec adjust = XVEC ( next_arg_reg , <NUM_LIT> ) ; int num = GET_NUM_ELEM ( adjust ) ; for ( i = <NUM_LIT> ; i < num ; i ++ ) { rtx pattern ; pattern = RTVEC_ELT ( adjust , i ) ; if ( GET_CODE ( pattern ) != SET || GET_CODE ( SET_SRC ( pattern ) ) != ASHIFT ) abort_with_insn ( pattern , <STR_LIT> ) ; PUT_CODE ( SET_SRC ( pattern ) , ASHIFTRT ) ; emit_insn ( pattern ) ; } } tsize = compute_frame_size ( get_frame_size ( ) ) ; if ( store_args_on_stack && ( stdarg_p ( fntype ) || last_arg_is_vararg_marker ) ) { int offset = ( regno - GP_ARG_FIRST ) * UNITS_PER_WORD ; rtx ptr = stack_pointer_rtx ; for ( ; regno <= GP_ARG_LAST ; regno ++ ) { if ( offset != <NUM_LIT> ) ptr = gen_rtx_PLUS ( Pmode , stack_pointer_rtx , GEN_INT ( offset ) ) ; emit_move_insn ( gen_rtx_MEM ( gpr_mode , ptr ) , gen_rtx_REG ( gpr_mode , regno ) ) ; offset += GET_MODE_SIZE ( gpr_mode ) ; } } if ( tsize > <NUM_LIT> ) { rtx tsize_rtx = GEN_INT ( tsize ) ; rtx adjustment_rtx , dwarf_pattern ; rtx_insn * insn ; if ( tsize > <NUM_LIT> ) { adjustment_rtx = gen_rtx_REG ( Pmode , IQ2000_TEMP1_REGNUM ) ; emit_move_insn ( adjustment_rtx , tsize_rtx ) ; } else adjustment_rtx = tsize_rtx ; insn = emit_insn ( gen_subsi3 ( stack_pointer_rtx , stack_pointer_rtx , adjustment_rtx ) ) ; dwarf_pattern = gen_rtx_SET ( Pmode , stack_pointer_rtx , plus_constant ( Pmode , stack_pointer_rtx , - tsize ) ) ; iq2000_annotate_frame_insn ( insn , dwarf_pattern ) ; save_restore_insns ( <NUM_LIT> ) ; if ( frame_pointer_needed ) { rtx_insn * insn = <NUM_LIT> ; insn = emit_insn ( gen_movsi ( hard_frame_pointer_rtx , stack_pointer_rtx ) ) ; if ( insn ) RTX_FRAME_RELATED_P ( insn


<s> CstIdxs . emplace_back ( ConstantInt :: get ( Type :: getInt8Ty ( Ctx ) , Offset ) ) ; } } MachineIRBuilder MIRBuilder ( I ) ; Constant * CPVal = ConstantVector :: get ( CstIdxs ) ; MachineInstr * IndexLoad = emitLoadFromConstantPool ( CPVal , MIRBuilder ) ; if ( ! IndexLoad ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } if ( DstTy . getSizeInBits ( ) != <NUM_LIT> ) { assert ( DstTy . getSizeInBits ( ) == <NUM_LIT> && <STR_LIT> ) ; MachineInstr * Concat = emitVectorConcat ( None , Src1Reg , Src2Reg , MIRBuilder ) ; if ( ! Concat ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } IndexLoad = emitScalarToVector ( <NUM_LIT> , & <STR_LIT> , IndexLoad -> getOperand ( <NUM_LIT> ) . getReg ( ) , MIRBuilder ) ; auto TBL1 = MIRBuilder . buildInstr ( <STR_LIT> , { & <STR_LIT> } , { Concat -> getOperand ( <NUM_LIT> ) . getReg ( ) , IndexLoad -> getOperand ( <NUM_LIT> ) . getReg ( ) } ) ; constrainSelectedInstRegOperands ( * TBL1 , TII , TRI , RBI ) ; auto Copy = MIRBuilder . buildInstr ( TargetOpcode :: COPY , { I . getOperand ( <NUM_LIT> ) . getReg ( ) } , { } ) . addReg ( TBL1 . getReg ( <NUM_LIT> ) , <NUM_LIT> , <STR_LIT> ) ; RBI . constrainGenericRegister ( Copy . getReg ( <NUM_LIT> ) , <STR_LIT> , MRI ) ; I . eraseFromParent ( ) ; return true ; } auto RegSeq = MIRBuilder . buildInstr ( TargetOpcode :: REG_SEQUENCE , { & <STR_LIT> } , { Src1Reg } ) . addImm ( <STR_LIT> ) .

addUse ( Src2Reg ) . addImm ( <STR_LIT> ) ;


<s> Val = cast < ConstantSDNode > ( N ) -> getZExtValue ( ) ; if ( ST -> isThumb1Only ( ) ) { if ( Val <= <NUM_LIT> || ~ Val <= <NUM_LIT> ) return DAG . getConstant ( Val , <STR_LIT> ) ; } else { if ( <STR_LIT> ( Val ) != - <NUM_LIT> || <STR_LIT> ( ~ Val ) != - <NUM_LIT> ) return DAG


<s> EVT PtrVT = Src1 . getValueType ( ) ; if ( Size > <NUM_LIT> * <NUM_LIT> ) return DAG . getNode ( <STR_LIT> , DL , VTs , Chain , Src1 , Src2 , DAG . getConstant ( Size , DL ,

PtrVT ) , DAG . getConstant ( Size / <NUM_LIT> , DL , PtrVT ) ) ;


<s> __slwpcb ( void ) { return __builtin_ia32_slwpcb ( )


<s> bool RegMemCounter = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getTargetLowering ( ) -> getTargetMachine ( ) . Options . RegMemCount ; if ( ! RegMemCounter && ! EnableSpillCounter ) { return false ; } if ( VectorSz == <NUM_LIT> ) { VectorSz = <NUM_LIT> ; } const <ISA_LIT>InstrInfo * TII = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getInstrInfo ( ) ; const <ISA_LIT>RegisterInfo & RI = TII -> getRegisterInfo ( ) ; std :: set < unsigned > SRF ; std :: set < unsigned > VRF ; std :: set < unsigned > IRF ; std :: set < unsigned > SPRF ; std :: set < unsigned > VPRF ; std :: set < unsigned > ADRF ; for ( auto & BB : MF ) { for ( auto & MI : BB ) { for ( auto & MO : MI . operands ( ) ) { if ( ! MO . isReg ( ) ) continue ; if ( ! MO . getReg ( ) . isPhysical ( ) ) continue ; unsigned R = MO . getReg ( ) ; if ( R ) { const TargetRegisterClass * RegClass = TII -> getClassOfPhysicalRegister ( R


<s> Stubs = MMIMacho . GetGVStubList ( ) ; if ( ! Stubs . empty ( ) ) { MCSection * TheSection = OutContext . getMachOSection ( <STR_LIT> , <STR_LIT> , MachO :: S_NON_LAZY_SYMBOL_POINTERS , SectionKind :: getMetadata ( ) ) ; OutStreamer -> SwitchSection ( TheSection ) ; for ( auto & Stub : Stubs ) emitNonLazySymbolPointer ( * OutStreamer , Stub . first , Stub . second ) ; Stubs . clear ( ) ; OutStreamer -> AddBlankLine ( ) ; } SM . serializeToStackMapSection ( ) ; FM . serializeToFaultMapSection ( ) ; OutStreamer -> EmitAssemblerFlag ( MCAF_SubsectionsViaSymbols ) ; } if ( TT . isKnownWindowsMSVCEnvironment ( ) && MMI -> usesVAFloatArgument ( ) ) { StringRef SymbolName = ( TT . getArch ( ) == Triple :: x86_64 ) ? <STR_LIT> : <STR_LIT> ; MCSymbol * S = MMI -> getContext ( ) . getOrCreateSymbol ( SymbolName ) ; OutStreamer -> EmitSymbolAttribute ( S , MCSA_Global ) ; } if ( TT . isOSBinFormatCOFF ( ) ) { SM . serializeToStackMapSection ( ) ; } if ( TT . isOSBinFormatELF ( ) ) { SM . serializeToStackMapSection


<s> if ( Opcode == <STR_LIT> ) NewBase = Regs [ NumRegs - <NUM_LIT> ] . first ; else { NewBase = Scratch ; if ( NewBase == <NUM_LIT> ) return false ; } int BaseOpc = <STR_LIT> ; if ( Offset < <NUM_LIT> ) { BaseOpc = <STR_LIT> ; Offset = - Offset ; } int ImmedOffset = <STR_LIT> ( Offset ) ; if ( ImmedOffset == - <NUM_LIT> ) return false ; BuildMI ( MBB , MBBI , dl , TII -> get ( BaseOpc ) , NewBase ) . addReg ( Base , getKillRegState ( BaseKill ) ) . addImm ( ImmedOffset ) . addImm ( Pred ) . addReg ( PredReg ) . addReg ( <NUM_LIT> ) ; Base = NewBase ; BaseKill = true ; } bool isDPR = Opcode == <STR_LIT> || Opcode == <STR_LIT> ; bool isDef = Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ; Opcode = getLoadStoreMultipleOpcode ( Opcode


<s> return ( vector unsigned int ) __builtin_altivec_vmsumubm ( ( vector signed char ) a1 , ( vector signed char ) a2 , (


<s> if ( GET_CODE ( xfoo0 ) == CONST_INT && INTVAL ( xfoo0 ) == ( int ) GET_MODE_SIZE ( mode ) && INDEX_REGISTER_P ( xfoo1 , strict ) ) return <NUM_LIT> ; if ( GET_CODE ( xfoo1 ) == CONST_INT && INTVAL ( xfoo1 ) == ( int ) GET_MODE_SIZE ( mode )

&& INDEX_REGISTER_P ( xfoo0 , strict ) ) return <NUM_LIT> ;


<s> rtx base = XEXP ( memref , <NUM_LIT> ) ; if ( GET_CODE ( base ) == PRE_MODIFY ) base = XEXP ( base


<s> EVT MemVT = MN -> getMemoryVT ( ) ; unsigned Size = MemVT . getSizeInBits ( ) ; if ( MemVT . isScalarInteger ( ) ) { assert ( Size <= <NUM_LIT> && <STR_LIT> ) ; if ( Size < <NUM_LIT> ) FlagSet |= <STR_LIT> ; else if ( Size == <NUM_LIT> ) FlagSet |= <STR_LIT> ; else FlagSet |= <STR_LIT> ; } else if ( MemVT . isVector ( ) && ! MemVT . isFloatingPoint ( ) ) { if ( Size == <NUM_LIT> ) FlagSet |= <STR_LIT> ; else if ( Size == <NUM_LIT> ) { assert ( Subtarget . pairedVectorMemops ( ) && <STR_LIT> <STR_LIT> ) ; FlagSet |= <STR_LIT> ; } else llvm_unreachable ( <STR_LIT> ) ; } else { if ( Size == <NUM_LIT> || Size == <NUM_LIT> ) FlagSet |= <STR_LIT> ; else if ( MemVT == <STR_LIT> || MemVT . isVector ( ) ) FlagSet |= <STR_LIT> ; else llvm_unreachable ( <STR_LIT> ) ; } computeFlagsForAddressComputation ( N , FlagSet , DAG ) ; if ( const LoadSDNode * LN = dyn_cast < LoadSDNode > ( Parent ) ) { switch ( LN -> getExtensionType ( ) ) { case <STR_LIT> : FlagSet |= <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT>


<s> bool HasAnyUndefs ; if ( ! C -> isConstantSplat ( SplatValue , SplatUndef , MinSplatBits , HasAnyUndefs ) ) return SDValue ( ) ; if ( ( SplatValue != <NUM_LIT> ) && ( SplatValue . isPowerOf2 ( ) || ( - SplatValue ) . isPowerOf2 ( ) ) ) { unsigned lg2 = SplatValue . countTrailingZeros ( ) ; SDValue Sz = DAG . getConstant ( EltTy . getSizeInBits ( ) - <NUM_LIT> , <STR_LIT> ) ; SDValue SGN = getTargetVShiftNode ( <STR_LIT> , dl , VT , N0 , Sz , DAG ) ; SDValue Amt = DAG . getConstant ( EltTy . getSizeInBits ( ) - lg2 , <STR_LIT> ) ; SDValue SRL = getTargetVShiftNode ( <STR_LIT> , dl , VT , SGN , Amt , DAG ) ; SDValue ADD = DAG . getNode ( <STR_LIT> , dl , VT , N0 ,


<s> static short find_set_regmode_weight ( rtx x , machine_mode mode ) { if ( GET_CODE ( x ) == CLOBBER && register_operand ( SET_DEST ( x ) , mode ) ) return <NUM_LIT> ; if ( GET_CODE ( x ) == SET && register_operand ( SET_DEST ( x ) , mode ) ) { if ( REG_P ( SET_DEST ( x ) ) ) { if ( ! reg_mentioned_p ( SET_DEST ( x ) , SET_SRC ( x ) ) ) return <NUM_LIT> ; else return <NUM_LIT> ; } return <NUM_LIT>


V2 , Mask , DAG , Subtarget ) ) return V ;


<s> const MachineOperand * SBase = getNamedOperand ( * MI , <STR_LIT> :: sbase ) ; bool IsKill = SBase -> isKill ( ) ; if ( OffOp ) { bool isVI = MBB -> getParent ( ) -> getSubtarget < <ISA_LIT>Subtarget > ( ) . getGeneration ( ) >= <ISA_LIT>Subtarget :: VOLCANIC_ISLANDS ; unsigned OffScale = isVI ? <NUM_LIT> : <NUM_LIT> ; unsigned LoOffset = OffOp -> getImm ( ) * OffScale ; unsigned HiOffset = LoOffset + HalfSize ; Lo = BuildMI ( * MBB , MI , DL , get ( HalfImmOp ) , RegLo ) . addReg ( SBase -> getReg ( ) , <NUM_LIT> , SBase -> getSubReg ( ) ) . addImm ( LoOffset / OffScale ) ; if ( ! isUInt < <NUM_LIT> > ( HiOffset ) || ( ! isVI && ! isUInt < <NUM_LIT> > ( HiOffset / OffScale ) ) ) { unsigned OffsetSGPR = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * MBB , MI , DL , get ( <STR_LIT> ) , OffsetSGPR ) . addImm ( HiOffset ) ; Hi = BuildMI ( * MBB , MI , DL , get ( HalfSGPROp ) , RegHi ) . addReg ( SBase -> getReg ( ) , getKillRegState ( IsKill ) , SBase -> getSubReg ( ) ) . addReg ( OffsetSGPR ) ; } else { Hi = BuildMI ( * MBB , MI , DL , get ( HalfImmOp ) , RegHi ) . addReg ( SBase ->

getReg ( ) , getKillRegState ( IsKill ) , SBase -> getSubReg ( ) ) . addImm ( HiOffset / OffScale ) ;


<s> void getAnalysisUsage ( AnalysisUsage &


<s> ReverseBranchCondition ( SmallVectorImpl < MachineOperand > & Cond ) const { assert ( Cond . size ( ) == <NUM_LIT> && <STR_LIT>


<s> void <ISA_LIT>TargetLowering :: ReplaceNodeResults ( SDNode * N , SmallVectorImpl < SDValue > & Results , SelectionDAG & DAG ) const { return LowerOperationWrapper ( N ,


<s> SDValue OpLHS , OpRHS ; OpLHS = GeneratePerfectShuffle ( PerfectShuffleTable [ LHSID ] , LHS , RHS , DAG , dl ) ; OpRHS = GeneratePerfectShuffle ( PerfectShuffleTable [ RHSID ] , LHS , RHS , DAG , dl ) ; EVT VT = OpLHS . getValueType ( ) ; switch ( OpNum ) { default : llvm_unreachable ( <STR_LIT> ) ; case OP_VREV : if ( VT . getVectorElementType ( ) == <STR_LIT> || VT . getVectorElementType ( ) == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , dl , VT , OpLHS ) ; if ( VT . getVectorElementType ( ) == <STR_LIT> || VT . getVectorElementType ( ) == <STR_LIT> || VT . getVectorElementType ( ) == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , dl , VT , OpLHS ) ; assert ( VT . getVectorElementType ( ) == <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , VT , OpLHS ) ; case OP_VDUP0 : case OP_VDUP1 : case OP_VDUP2 : case OP_VDUP3 : { EVT EltTy = VT . getVectorElementType ( ) ; unsigned Opcode ; if ( EltTy == <STR_LIT> ) Opcode = <STR_LIT> ; else if ( EltTy == <STR_LIT> || EltTy == <STR_LIT> || EltTy == <STR_LIT> ) Opcode = <STR_LIT> ; else if ( EltTy == <STR_LIT> || EltTy == <STR_LIT> ) Opcode = <STR_LIT> ; else if ( EltTy == <STR_LIT> || EltTy == <STR_LIT> ) Opcode = <STR_LIT> ; else llvm_unreachable ( <STR_LIT> ) ; if ( VT . getSizeInBits ( ) == <NUM_LIT> ) OpLHS = WidenVector ( OpLHS , DAG ) ; SDValue Lane = DAG . getConstant ( OpNum - OP_VDUP0 , dl , <STR_LIT> ) ; return DAG . getNode ( Opcode , dl , VT , OpLHS , Lane ) ; } case OP_VEXT1


<s> } MachineInstr * MOVA = buildDefaultInstruction ( * MBB , I , <STR_LIT> , <STR_LIT> , OffsetReg ) ; setImmOperand ( * MOVA , <STR_LIT> :: write , <NUM_LIT> ) ; MachineInstrBuilder Mov = buildDefaultInstruction ( * MBB , I , <STR_LIT> , ValueReg , AddrReg ) . addReg ( <STR_LIT> , RegState :: Implicit | RegState :: Kill ) ; setImmOperand ( * Mov , <STR_LIT> :: src0_rel , <NUM_LIT> ) ; return Mov


<s> unsigned <ISA_LIT>RegisterInfo :: getEHHandlerRegister ( ) const { llvm_unreachable ( <STR_LIT> ) ; return


<s> return CheckImmRange ( <NUM_LIT> , <NUM_LIT> , false , false


<s> return __aarch64_vget_lane_any ( __a ,


<s> const char * getPassName ( ) const override { return <STR_LIT>


<s> addr = plus_constant ( Pmode , dst , i ) ; mem = adjust_automodify_address ( dstbase , SImode , addr , i ) ; if ( ( align & <NUM_LIT> ) == <NUM_LIT> ) emit_move_insn ( mem , reg ) ; else emit_insn ( gen_unaligned_storesi ( mem , reg ) ) ; } if ( unaligned_access && i > <NUM_LIT> && ( i + <NUM_LIT> ) == length ) { addr = plus_constant ( Pmode , dst , i - <NUM_LIT> ) ; mem = adjust_automodify_address ( dstbase , SImode , addr , i - <NUM_LIT> ) ; if ( ( align & <NUM_LIT> ) == <NUM_LIT> ) set_mem_align ( mem , BITS_PER_UNIT ) ; emit_insn ( gen_unaligned_storesi ( mem , reg ) ) ; return true ; } if ( i + <NUM_LIT> <= length ) { reg = gen_lowpart ( HImode , val_reg ) ; addr = plus_constant ( Pmode , dst , i ) ; mem = adjust_automodify_address ( dstbase , HImode , addr , i ) ; if ( ( align & <NUM_LIT> ) == <NUM_LIT> ) emit_move_insn ( mem , reg ) ; else emit_insn ( gen_unaligned_storehi ( mem , reg ) ) ; i += <NUM_LIT> ; } if ( i + <NUM_LIT> == length ) { reg = gen_lowpart ( QImode , val_reg ) ; addr = plus_constant ( Pmode , dst


<s> for ( ; MI -> getOperand ( NumDefs ) . isReg ( ) && MI -> getOperand ( NumDefs ) . isDef ( ) ; ++ NumDefs ) ; const char * AsmStr = MI -> getOperand ( NumDefs ) . getSymbolName ( ) ; if ( AsmStr [ <NUM_LIT> ] == <NUM_LIT> ) return ; } if ( MI -> getOpcode ( ) == <STR_LIT> ) processLDimm64 ( MI ) ; const DebugLoc & DL = MI -> getDebugLoc ( ) ; if ( ! DL || PrevInstLoc == DL ) { if ( LineInfoGenerated == false ) { auto * S = MI -> getMF ( ) ->


<s> if ( ! Section ) { getStreamer ( ) . InitSections ( false ) ; Section = getStreamer ( ) . getCurrentSection ( ) . first ; } if ( Section -> UseCodeAlign ( ) ) getStreamer ( ) . EmitCodeAlignment ( <NUM_LIT> , <NUM_LIT> ) ; else getStreamer ( ) . EmitValueToAlignment ( <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> ) ; return


<s> InlineAsmIdentifierInfo Info ; StringRef Identifier = Tok . getString ( ) ; if ( ParseIntelIdentifier ( Val , Identifier , Info , false , End ) ) return nullptr ; if ( ! getLexer ( ) . is ( AsmToken :: LBrac ) ) return CreateMemForInlineAsm ( <NUM_LIT> , Val , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , Start , End , Size , Identifier , Info ) ; Parser . Lex ( ) ; IntelExprStateMachine SM ( <NUM_LIT> , true , false ) ; if ( ParseIntelExpression ( SM , End ) ) return nullptr ; if ( SM . getSym ( ) ) { Error ( Start , <STR_LIT> ) ; return nullptr ; } if ( SM . getBaseReg ( ) ) { Error ( Start , <STR_LIT> ) ; return nullptr ; } if ( SM . getIndexReg ( ) ) { Error ( Start , <STR_LIT> ) ; return nullptr ; } const MCExpr * Disp = MCConstantExpr :: Create ( SM . getImm ( ) , getContext (


<s> default : assert ( <NUM_LIT> && <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return TBZDisplacementBits ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return CBZDisplacementBits ; case <STR_LIT> : return BCCDisplacementBits


<s> return __builtin_aarch64_smaxpv4sf ( a


<s> const TargetRegisterClass * const * BlackfinRegisterInfo :: getCalleeSavedRegClasses ( const MachineFunction * MF ) const { using namespace <ISA_LIT> ; static const TargetRegisterClass * const CalleeSavedRegClasses [


<s> MCValue Value ; bool isRelocatable = SubExpr -> evaluateAsRelocatable ( Value , Layout , Fixup ) ; if ( ! isRelocatable ) return false ; if ( Value . isAbsolute ( ) ) { Result = MCValue :: get ( evaluateAsInt64 ( Value . getConstant ( ) ) ) ; } else { if ( ! Layout ) return false ; MCContext & Context = Layout -> getAssembler ( ) . getContext ( ) ; const MCSymbolRefExpr * Sym = Value .


<s> void <ISA_LIT>InstrInfo :: copyPhysRegTuple ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , const DebugLoc & DL , MCRegister DestReg , MCRegister SrcReg , bool KillSrc , unsigned Opcode , ArrayRef < unsigned > Indices ) const { assert ( Subtarget . hasNEON ( ) && <STR_LIT> ) ; const TargetRegisterInfo * TRI = & getRegisterInfo ( ) ; uint16_t DestEncoding = TRI -> getEncodingValue ( DestReg ) ; uint16_t SrcEncoding = TRI -> getEncodingValue ( SrcReg ) ; unsigned NumRegs = Indices . size ( ) ; int SubReg = <NUM_LIT> , End = NumRegs , Incr = <NUM_LIT> ; if ( forwardCopyWillClobberTuple ( DestEncoding , SrcEncoding , NumRegs ) ) { SubReg = NumRegs - <NUM_LIT> ; End = - <NUM_LIT> ; Incr = - <NUM_LIT> ; } for ( ; SubReg != End ; SubReg += Incr ) { const MachineInstrBuilder MIB = BuildMI ( MBB , I ,


<s> std :: pair < unsigned , MVT > LT = getTypeLegalizationCost ( ValTy ) ; MVT MTy = LT . second ; int ISD = InstructionOpcodeToISD ( Opcode ) ; assert ( ISD && <STR_LIT> ) ; const <ISA_LIT>Subtarget & ST = TLI -> getTargetMachine ( ) . getSubtarget < <ISA_LIT>Subtarget > ( ) ; static const <ISA_LIT>CostTblEntry SSE42CostTbl [ ] = { { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , } ; static const <ISA_LIT>CostTblEntry AVX1CostTbl [ ] = { { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , } ; static const <ISA_LIT>CostTblEntry AVX2CostTbl [ ] = { { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , } ; if ( ST . hasAVX2 ( ) ) { int Idx = FindInTable ( AVX2CostTbl , array_lengthof ( AVX2CostTbl ) , ISD , MTy ) ; if ( Idx != - <NUM_LIT> ) return LT . first


<s> MCSection * <ISA_LIT>TargetObjectFile :: SelectSectionForGlobal ( const GlobalObject * GO , SectionKind Kind , const TargetMachine & TM ) const { return getDataSection


<s> SDValue CPIdx0 = DAG . getConstantPool ( C0 , getPointerTy ( ) , <NUM_LIT> ) ; std :: vector < Constant * > CV1 ; CV1 . push_back ( ConstantFP :: get ( * Context , APFloat ( APInt ( <NUM_LIT> , <NUM_LIT> ) ) ) ) ; CV1 . push_back ( ConstantFP :: get ( * Context , APFloat ( APInt ( <NUM_LIT> , <NUM_LIT> ) ) ) ) ; Constant * C1 = ConstantVector :: get ( CV1 ) ; SDValue CPIdx1 = DAG . getConstantPool ( C1 , getPointerTy ( ) , <NUM_LIT> ) ; SDValue XR1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ) ; SDValue XR2 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ) ; SDValue Unpck1 = getUnpackl ( DAG , dl , <STR_LIT> , XR1 , XR2 ) ; SDValue CLod0 = DAG . getLoad ( <STR_LIT> , dl , DAG . getEntryNode ( ) , CPIdx0 , MachinePointerInfo :: getConstantPool ( ) , false , false , <NUM_LIT> ) ; SDValue Unpck2 = getUnpackl ( DAG , dl , <STR_LIT> , Unpck1 , CLod0 ) ; SDValue XR2F = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Unpck2 ) ; SDValue CLod1 = DAG . getLoad ( <STR_LIT> , dl , CLod0 . getValue ( <NUM_LIT> ) , CPIdx1 , MachinePointerInfo :: getConstantPool ( ) , false , false , <NUM_LIT> ) ; SDValue Sub = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , XR2F , CLod1 ) ; int ShufMask [ <NUM_LIT> ] = { <NUM_LIT>


<s> return ; case <STR_LIT> : ReplaceATOMIC_OP_64 ( N , Results , DAG , <STR_LIT> ) ; return ; case <STR_LIT> : ReplaceATOMIC_OP_64 ( N , Results , DAG , <STR_LIT> ) ; return ; case <STR_LIT> : ReplaceATOMIC_OP_64 ( N , Results , DAG , <STR_LIT> ) ; return ; case <STR_LIT> : ReplaceATOMIC_OP_64 ( N , Results , DAG , <STR_LIT> ) ; return ; case <STR_LIT> : ReplaceATOMIC_OP_64 ( N , Results , DAG , <STR_LIT> ) ; return ; case <STR_LIT>


<s> static rtx tilepro_function_arg ( cumulative_args_t cum_v , machine_mode mode , const_tree type , bool named ATTRIBUTE_UNUSED ) { CUMULATIVE_ARGS cum = * get_cumulative_args ( cum_v ) ; int byte_size = ( ( mode == BLKmode ) ? int_size_in_bytes ( type ) : GET_MODE_SIZE ( mode ) ) ; bool doubleword_aligned_p ; if ( cum >= TILEPRO_NUM_ARG_REGS ) return NULL_RTX ; doubleword_aligned_p = tilepro_function_arg_boundary ( mode , type ) > BITS_PER_WORD ; if ( doubleword_aligned_p ) cum += cum & <NUM_LIT> ; if ( ( cum + ( byte_size + UNITS_PER_WORD - <NUM_LIT> ) / UNITS_PER_WORD ) >


<s> NumIssued = <NUM_LIT> ; HasCTRSet = false ; NumStores =


<s> if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; } else { llvm_unreachable ( <STR_LIT>


<s> if ( checkFPAtomicToDenormModeHazard ( MI ) > <NUM_LIT> ) return NoopHazard ; if ( ST . hasNoDataDepHazard ( ) ) return NoHazard ; if ( <ISA_LIT>InstrInfo :: isVALU ( * MI ) && checkVALUHazards ( MI ) > <NUM_LIT> ) return NoopHazard ; if ( <ISA_LIT>InstrInfo :: isDPP ( * MI ) && checkDPPHazards ( MI ) > <NUM_LIT> ) return NoopHazard ; if ( isDivFMas ( MI -> getOpcode ( ) ) && checkDivFMasHazards ( MI ) > <NUM_LIT> ) return NoopHazard ; if ( isRWLane ( MI -> getOpcode ( ) ) && checkRWLaneHazards ( MI ) > <NUM_LIT> ) return NoopHazard ; if ( isSGetReg ( MI -> getOpcode ( ) ) && checkGetRegHazards ( MI ) > <NUM_LIT> ) return NoopHazard ; if ( isSSetReg ( MI -> getOpcode ( ) ) && checkSetRegHazards ( MI ) > <NUM_LIT> ) return NoopHazard ; if ( isRFE ( MI -> getOpcode ( ) ) && checkRFEHazards ( MI ) > <NUM_LIT> ) return NoopHazard ; if ( ST . hasReadM0MovRelInterpHazard ( ) && ( TII . isVINTRP ( * MI ) || isSMovRel ( MI -> getOpcode ( ) ) ) && checkReadM0Hazards ( MI ) > <NUM_LIT> ) return NoopHazard ; if ( ST . hasReadM0SendMsgHazard ( ) && isSendMsgTraceDataOrGDS ( TII , * MI ) && checkReadM0Hazards ( MI ) > <NUM_LIT> ) return NoopHazard ; if ( MI -> isInlineAsm ( ) && checkInlineAsmHazards ( MI ) > <NUM_LIT> ) return NoopHazard ; if ( checkAnyInstHazards ( MI ) > <NUM_LIT>


<s> if ( CIdx && ( CIdx -> getZExtValue ( ) <= <NUM_LIT> ) ) { SDValue CI = DAG . getTargetConstant ( CIdx -> getZExtValue ( ) , DL , <STR_LIT> ) ; SDNode * DUPQ = DAG . getMachineNode ( <STR_LIT> , DL , <STR_LIT> , V , CI ) ; return DAG . getNode ( <STR_LIT> , DL , VT , SDValue ( DUPQ , <NUM_LIT> ) ) ; } SDValue One = DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; SDValue SplatOne = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , One ) ; SDValue SV = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , One ) ; SV = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , SV , SplatOne ) ; SDValue Idx64 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Idx128 , Idx128 ) ; SDValue SplatIdx64 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Idx64


<s> if ( ! IN_RANGE ( width , <NUM_LIT> , GET_MODE_BITSIZE ( GET_MODE ( op ) ) - <NUM_LIT> ) ) return false ; if ( bitpos < <NUM_LIT> || bitpos + width > GET_MODE_BITSIZE ( GET_MODE ( op ) ) )


<s> auto Dims = HSAMetadataDoc -> getArrayNode ( ) ; if ( Node -> getNumOperands ( ) != <NUM_LIT> ) return Dims ; for ( auto & Op : Node -> operands ( ) ) Dims . push_back ( Dims . getDocument ( ) -> getNode ( uint64_t ( mdconst :: extract < ConstantInt > ( Op )


<s> SDValue Lower = getTargetVShiftByConstNode ( <STR_LIT> , dl , VT , R , ShiftAmt , DAG ) ; Lower = DAG . getBitcast ( ExVT , Lower ) ; if ( VT == <STR_LIT> ) Ex = DAG . getVectorShuffle ( ExVT , dl , Upper , Lower , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ; if ( VT == <STR_LIT> ) Ex = DAG . getVectorShuffle ( ExVT , dl , Upper , Lower , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ; } return DAG . getBitcast ( VT , Ex ) ; } ; APInt APIntShiftAmt ; if ( ! <STR_LIT> ( Amt , APIntShiftAmt ) ) return SDValue ( ) ; if ( APIntShiftAmt . uge ( VT . getScalarSizeInBits ( ) ) ) return DAG . getUNDEF ( VT ) ; uint64_t ShiftAmt = APIntShiftAmt . getZExtValue ( ) ; if ( SupportedVectorShiftWithImm ( VT , Subtarget , Op . getOpcode ( ) ) ) return getTargetVShiftByConstNode ( <ISA_LIT>Opc , dl , VT , R , ShiftAmt , DAG ) ; if ( ( ( ! Subtarget . hasXOP ( ) && VT == <STR_LIT> ) || ( Subtarget . hasInt256 ( ) && VT == <STR_LIT> ) ) && Op . getOpcode ( ) == <STR_LIT> ) return ArithmeticShiftRight64 ( ShiftAmt ) ; if ( VT == <STR_LIT> || ( Subtarget . hasInt256 ( ) && VT == <STR_LIT> ) || ( Subtarget . hasBWI ( ) && VT == <STR_LIT> ) ) { unsigned NumElts = VT . getVectorNumElements ( ) ; MVT ShiftVT = <STR_LIT> ( <STR_LIT> , NumElts / <NUM_LIT> ) ; if ( Op . getOpcode ( ) == <STR_LIT> && ShiftAmt == <NUM_LIT> ) { R = DAG . getNode ( <STR_LIT> , dl , VT , R ) ; return DAG . getNode ( <STR_LIT> , dl , VT , R , R ) ; } if ( Op . getOpcode ( ) == <STR_LIT> && ShiftAmt == <NUM_LIT> ) { SDValue Zeros = DAG . getConstant ( <NUM_LIT> , dl , VT ) ; if ( VT . is512BitVector ( ) ) { assert ( VT == <STR_LIT> && <STR_LIT> ) ; SDValue CMP = DAG . getSetCC ( dl , <STR_LIT> , Zeros , R , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , VT , CMP ) ; } return DAG . getNode ( <STR_LIT> , dl , VT , Zeros , R ) ; } if ( VT == <STR_LIT> && Subtarget . hasXOP (


<s> auto * AA = & getAnalysis < AAResultsWrapperPass > ( ) . getAAResults ( ) ; auto * DT = & getAnalysis < DominatorTreeWrapperPass > ( ) . getDomTree ( ) ; auto * LF = & getAnalysis < LoopInfoWrapperPass > ( ) . getLoopInfo (


<s> MachineBasicBlock & MBB = * ( FrameSetup -> getParent ( ) ) ; TII -> setFrameAdjustment ( * FrameSetup , Context . ExpectedDist ) ; const DebugLoc & DL = FrameSetup -> getDebugLoc ( ) ; bool Is64Bit = STI -> is64Bit ( ) ; for ( int Idx = ( Context . ExpectedDist >> Log2SlotSize ) - <NUM_LIT> ; Idx >= <NUM_LIT> ; -- Idx ) { MachineBasicBlock :: iterator Store = * Context . ArgStoreVector [ Idx ] ; const MachineOperand & PushOp = Store -> getOperand ( <STR_LIT> ) ; MachineBasicBlock :: iterator Push = nullptr ; unsigned PushOpcode ; switch ( Store -> getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : PushOpcode = Is64Bit ? <STR_LIT> : <STR_LIT> ; if ( PushOp . isImm ( ) ) { int64_t Val = PushOp . getImm ( ) ; if ( isInt < <NUM_LIT> > ( Val ) ) PushOpcode = Is64Bit ? <STR_LIT> : <STR_LIT> ; } Push = BuildMI ( MBB , Context . Call , DL , TII -> get ( PushOpcode ) ) . add ( PushOp ) ; Push -> cloneMemRefs ( MF , * Store ) ; break ; case <STR_LIT> : case <STR_LIT> : { Register Reg = PushOp . getReg ( ) ; if ( Is64Bit && Store -> getOpcode ( ) == <STR_LIT> ) { Register UndefReg = MRI -> createVirtualRegister ( & <STR_LIT> ) ; Reg = MRI -> createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( MBB , Context . Call , DL , TII -> get ( <STR_LIT> ) , UndefReg ) ; BuildMI ( MBB , Context . Call , DL , TII -> get ( <STR_LIT> ) , Reg ) . addReg ( UndefReg ) . add ( PushOp ) . addImm ( <STR_LIT> ) ; } bool SlowPUSHrmm = STI -> slowTwoMemOps ( ) ; MachineInstr * DefMov = nullptr ; if ( ! SlowPUSHrmm && ( DefMov =

canFoldIntoRegPush ( FrameSetup , Reg ) ) ) {


<s> MVT EltVT ; if ( VT . isVector ( ) ) { LogicVT = VT ; EltVT = VT . getVectorElementType ( ) ; } else if ( IsF128 ) { LogicVT = <STR_LIT> ; EltVT = VT ; } else { LogicVT = ( VT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; EltVT = VT ; } unsigned EltBits = EltVT . getSizeInBits ( ) ; APInt MaskElt = IsFABS ? APInt :: getSignedMaxValue ( EltBits ) : APInt :: getSignMask ( EltBits ) ; const fltSemantics & Sem = EltVT == <STR_LIT> ? APFloat :: IEEEdouble ( ) : ( IsF128 ? APFloat :: IEEEquad ( ) : APFloat :: IEEEsingle ( ) ) ; SDValue Mask = DAG . getConstantFP ( APFloat ( Sem , MaskElt ) , dl , LogicVT ) ; SDValue Op0 = Op . getOperand ( <NUM_LIT> ) ; bool IsFNABS = ! IsFABS && ( Op0 . getOpcode ( ) == <STR_LIT> ) ; unsigned LogicOp = IsFABS ? <STR_LIT> : IsFNABS ? <STR_LIT> : <STR_LIT> ; SDValue Operand = IsFNABS ? Op0 . getOperand ( <NUM_LIT> ) : Op0 ; if ( VT . isVector ( ) || IsF128 ) return DAG . getNode ( LogicOp , dl , LogicVT , Operand , Mask ) ; Operand = DAG . getNode ( <STR_LIT> , dl ,


<s> return getMachineOpValue ( MI , MI . getOperand ( OpNo ) ,


<s> void <ISA_LIT>TargetLowering :: ReplaceNodeResults ( SDNode * N , SmallVectorImpl < SDValue > & Results , SelectionDAG &


<s> assert ( NumNOPBytes % <NUM_LIT> == <NUM_LIT> && <STR_LIT> ) ; unsigned ShadowBytes = <NUM_LIT> ; const MachineBasicBlock & MBB = * MI . getParent ( ) ; MachineBasicBlock :: const_iterator MII ( MI ) ; ++ MII ; while ( ShadowBytes < NumNOPBytes ) { if ( MII == MBB . end ( ) || MII -> getOpcode ( ) == TargetOpcode :: PATCHPOINT || MII -> getOpcode ( ) == TargetOpcode :: STACKMAP ) break ; ShadowBytes += TII -> getInstSizeInBytes ( * MII ) ; if ( MII -> isCall ( ) ) break ; ++ MII


<s> } if ( AddrMode == <STR_LIT> || AddrMode == <STR_LIT> ) return Offset == <NUM_LIT> ; unsigned NumBits = <NUM_LIT> ; unsigned Scale = <NUM_LIT> ; bool isSigned = true ; switch ( AddrMode ) { case <STR_LIT> : case <STR_LIT> : Scale = <NUM_LIT> ; if ( Offset < <NUM_LIT> ) { NumBits = <NUM_LIT> ; Offset = - Offset ; } else { NumBits = <NUM_LIT> ; } break ; case <STR_LIT> : NumBits = <NUM_LIT> ; Scale = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : NumBits = <NUM_LIT> ; break ; case <STR_LIT> : NumBits = <NUM_LIT> ; break ; case <STR_LIT> : NumBits = <NUM_LIT> ; Scale = <NUM_LIT> ; isSigned = false ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } Offset += getFrameIndexInstrOffset ( MI , i ) ; if ( ( Offset & ( Scale - <NUM_LIT> ) ) != <NUM_LIT> ) return false ; if ( isSigned && Offset < <NUM_LIT> ) Offset = - Offset ; unsigned Mask = ( <NUM_LIT>


<s> const char * AMDGPUMCAsmInfo :: getDataASDirective ( unsigned int Size , unsigned int AS ) const { return <NUM_LIT>


<s> static unsigned HOST_WIDE_INT compute_current_alignment ( unsigned HOST_WIDE_INT base_align , unsigned HOST_WIDE_INT offset ) { if ( offset == <NUM_LIT> ) return base_align ; return min ( base_align , offset &


<s> unsigned <ISA_LIT>CodeEmitter :: getMachineOpValue ( const MachineInstr & MI , const MachineOperand & MO ) const { if ( MO . isReg ( ) ) { assert ( ( MI . getOpcode ( ) != <STR_LIT> && MI . getOpcode ( ) != <STR_LIT> ) || MO . getReg ( ) < <STR_LIT> || MO . getReg ( ) > <STR_LIT> ) ; return get<ISA_LIT>RegisterNumbering ( MO . getReg ( ) ) ; } assert ( MO . isImm ( ) && <STR_LIT> ) ; return MO . getImm


<s> if ( FixupKind != FK_Data_4 ) { Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; return COFF :: IMAGE_REL_AMD64_ADDR32 ; } FixupKind = FK_PCRel_4 ; } MCSymbolRefExpr :: VariantKind Modifier = Target . isAbsolute ( ) ? MCSymbolRefExpr :: VK_None : Target . getSymA ( ) -> getKind ( ) ; if ( getMachine ( ) == COFF :: IMAGE_FILE_MACHINE_AMD64 ) { switch ( FixupKind ) { case FK_PCRel_4 : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return COFF :: IMAGE_REL_AMD64_REL32 ; case FK_Data_4 : case <STR_LIT> : case <STR_LIT> : if ( Modifier == MCSymbolRefExpr :: VK_COFF_IMGREL32 ) return COFF :: IMAGE_REL_AMD64_ADDR32NB ; if ( Modifier == MCSymbolRefExpr :: VK_SECREL ) return COFF :: IMAGE_REL_AMD64_SECREL ; return COFF :: IMAGE_REL_AMD64_ADDR32 ; case FK_Data_8 : return COFF :: IMAGE_REL_AMD64_ADDR64 ; case FK_SecRel_2 : return COFF :: IMAGE_REL_AMD64_SECTION ; case FK_SecRel_4


<s> static DecodeStatus DecodeAddrRegsRegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t Address , const void * Decoder ) { if ( RegNo > <NUM_LIT> ) return MCDisassembler :: Fail ; unsigned Reg = getReg ( Decoder


<s> char State = isEntry ? StateExact : StateWQM ; auto II = MBB . getFirstNonPHI ( ) , IE = MBB . end ( ) ; while ( II != IE ) { MachineInstr & MI = * II ; ++ II ; if ( MI . getDesc ( ) . TSFlags & ( <STR_LIT> | <STR_LIT> ) && ! MI . isBranch ( ) && ! MI . isTerminator ( ) ) continue ; if ( TargetInstrInfo :: isGenericOpcode ( MI . getOpcode ( ) ) ) { if ( MI . getNumExplicitOperands ( ) >= <NUM_LIT> ) { const MachineOperand & Op = MI . getOperand ( <NUM_LIT> ) ; if ( Op . isReg ( ) ) { if ( TRI -> isSGPRReg ( * MRI , Op . getReg ( ) ) ) { continue ; } } } } char Needs = <NUM_LIT> ; char OutNeeds = <NUM_LIT> ; auto InstrInfoIt = Instructions . find ( & MI ) ; if ( InstrInfoIt != Instructions . end ( ) ) { Needs = InstrInfoIt -> second . Needs ; OutNeeds = InstrInfoIt -> second . OutNeeds


<s> void addDupAlignedMemory64or128Operands ( MCInst & Inst ,


<s> bool <ISA_LIT>CallFrameOptimization :: isProfitable ( MachineFunction & MF , ContextVector & CallSeqVector ) { bool CannotReserveFrame = MF . getFrameInfo ( ) -> hasVarSizedObjects ( ) ; if ( CannotReserveFrame ) return true ; if ( ! MF . getFunction ( ) -> optForSize ( ) ) return false ; unsigned StackAlign = TFL -> getStackAlignment ( ) ; int64_t Advantage = <NUM_LIT> ; for ( auto CC : CallSeqVector ) { if ( CC . NoStackParams ) continue ; if ( ! CC . UsePush ) { Advantage -= <NUM_LIT> ; } else { Advantage -= <NUM_LIT> ; if ( CC . ExpectedDist % StackAlign


<s> MCAsmBackend * llvm :: create<ISA_LIT>AsmBackendEL32 ( const Target & T , const MCRegisterInfo & MRI , StringRef TT ,


<s> if ( ! LD -> isSimple ( ) || ! N0 . hasOneUse ( ) || LD -> isIndexed ( ) || LD -> getExtensionType ( ) != <STR_LIT> ) return SDValue ( ) ; EVT FromVT = LD -> getValueType ( <NUM_LIT> ) ; EVT ToVT = N -> getValueType ( <NUM_LIT> ) ; if ( ! ToVT . isVector ( ) ) return SDValue ( ) ; assert ( FromVT . getVectorNumElements ( ) == ToVT . getVectorNumElements ( ) ) ; EVT ToEltVT = ToVT . getVectorElementType ( ) ; EVT FromEltVT = FromVT . getVectorElementType ( ) ; unsigned NumElements = <NUM_LIT> ; if ( ToEltVT == <STR_LIT> && ( FromEltVT == <STR_LIT> || FromEltVT == <STR_LIT> ) ) NumElements = <NUM_LIT> ; if ( ToEltVT == <STR_LIT> && FromEltVT == <STR_LIT> ) NumElements = <NUM_LIT> ; if ( NumElements == <NUM_LIT> || FromVT . getVectorNumElements ( ) == NumElements || FromVT . getVectorNumElements ( ) % NumElements != <NUM_LIT> || ! isPowerOf2_32 ( NumElements ) ) return SDValue ( ) ; SDLoc DL ( LD ) ; SDValue Ch = LD -> getChain ( ) ; SDValue BasePtr = LD -> getBasePtr ( ) ; Align Alignment = LD -> getOriginalAlign ( ) ; MachineMemOperand :: Flags MMOFlags = LD -> getMemOperand ( ) -> getFlags ( ) ; AAMDNodes AAInfo = LD -> getAAInfo ( ) ; <STR_LIT> NewExtType = N -> getOpcode ( ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; SDValue Offset = DAG . getUNDEF ( BasePtr . getValueType ( ) ) ; EVT NewFromVT = FromVT . getHalfNumVectorElementsVT ( * DAG . getContext ( ) ) ; EVT NewToVT = ToVT . getHalfNumVectorElementsVT ( * DAG . getContext ( ) ) ; unsigned NewOffset = NewFromVT . getSizeInBits ( ) / <NUM_LIT> ; SDValue NewPtr = DAG . getObjectPtrOffset ( DL , BasePtr , NewOffset ) ; SDValue NewLoad1 = DAG . getLoad ( <STR_LIT> , NewExtType , NewToVT , DL , Ch , BasePtr , Offset , LD -> getPointerInfo (

) , NewFromVT , Alignment . value ( ) , MMOFlags , AAInfo ) ;


<s> <ISA_LIT>ELFStreamer * S = new <ISA_LIT>ELFStreamer ( Context , std :: move ( TAB ) , OS , std :: move ( Emitter ) , IsThumb ) ; S -> getAssembler ( ) . setELFHeaderEFlags ( ELF :: EF_<ISA_LIT>_EABI_VER5 ) ; if ( RelaxAll ) S -> getAssembler ( ) . setRelaxAll ( true ) ; return


<s> EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( ! VT . isVector ( ) ) return SDValue ( ) ; SDValue N0 = N -> getOperand ( <NUM_LIT> ) ; SDValue N1 = N -> getOperand ( <NUM_LIT> ) ; EVT ExtraVT = cast < VTSDNode > ( N1 ) -> getVT ( ) ; SDLoc dl ( N ) ; if ( VT == <STR_LIT> && ( N0 . getOpcode ( ) == <STR_LIT> || N0 . getOpcode ( ) == <STR_LIT> ) ) { SDValue N00 = N0 . getOperand ( <NUM_LIT> ) ; if ( N00 . getOpcode ( ) == <STR_LIT> && Subtarget . hasInt256 ( ) ) if ( ! <STR_LIT> ( N00 . getNode ( ) ) ) return SDValue ( ) ; if ( N00 . getValueType ( ) == <STR_LIT> && ExtraVT . getSizeInBits ( ) < <NUM_LIT> ) { SDValue Tmp = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N00 , N1 ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Tmp


<s> const ConstantFP * FV = cast < ConstantFPSDNode > ( Node ) -> getConstantFPValue ( ) ; EVT DestType = Node -> getValueType ( <NUM_LIT> ) ; unsigned Alignment = TLI . getDataLayout ( ) -> getABITypeAlignment ( FV -> getType (


<s> assert ( Op . getOpcode ( ) == <STR_LIT> && <STR_LIT> ) ; if ( ! isa < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) ) return SDValue ( ) ; EVT VT = Op . getOperand ( <NUM_LIT> ) . getValueType ( ) ; if ( VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> ) return Op ; if ( VT != <STR_LIT> && VT != <STR_LIT> && VT != <STR_LIT>

&& VT != <STR_LIT> && VT != <STR_LIT> ) return SDValue ( ) ;


<s> if ( isUInt < <NUM_LIT> > ( Imm ) ) return shortOp ; else if ( isUInt < <NUM_LIT> > (


<s> MCRegisterInfo * X = new MCRegisterInfo ( ) ; Init<ISA_LIT>ompactMCRegisterInfo ( X , <STR_LIT> ) ; return


<s> for ( unsigned i = <NUM_LIT> , e = array_lengthof ( ReplaceableInstrsAVX2 ) ; i != e ; ++ i ) if ( ReplaceableInstrsAVX2 [ i ] [ domain - <NUM_LIT> ] == opcode ) return ReplaceableInstrsAVX2 [ i ] ; return <NUM_LIT>


<s> <ISA_LIT>MCAsmInfoDarwin :: <ISA_LIT>MCAsmInfoDarwin ( const Triple & T ) { bool is64Bit = T . getArch ( ) == Triple :: x86_64 ; if ( is64Bit ) PointerSize = CalleeSaveStackSlotSize = <NUM_LIT> ; AssemblerDialect =


<s> } else if ( isa < ConstantVector > ( C ) || isa < ConstantArray > ( C ) || isa < ConstantStruct > ( C ) ) { NewValue = remapConstantVectorOrConstantAggregate ( M , F , C , Builder ) ; } else if ( isa < ConstantExpr > ( C ) ) { NewValue = remapConstantExpr ( M , F , cast < ConstantExpr > ( C ) , Builder ) ; } ConstantToValueMap [ C ] = NewValue ; return


<s> virtual const TargetRegisterInfo & getRegisterInfo ( ) const { return


<s> if ( Imm . I >= <NUM_LIT> && Imm . I <= <NUM_LIT> ) return <NUM_LIT> + Imm . I ; if ( Imm . I >= - <NUM_LIT> && Imm . I <= - <NUM_LIT> ) return <NUM_LIT> + abs ( Imm . I ) ; if ( Imm . F == <NUM_LIT> ) return <NUM_LIT> ; if ( Imm . F == - <NUM_LIT> ) return <NUM_LIT> ; if ( Imm . F == <NUM_LIT> ) return <NUM_LIT> ; if ( Imm . F == - <NUM_LIT> )


<s> } SplitLIs . clear ( ) ; } for ( MachineInstr & MI : llvm :: make_early_inc_range ( MF . front ( ) ) ) { if ( MI . isImplicitDef ( ) && MI . getOperand ( <NUM_LIT> ) . isDead ( ) ) { LiveInterval & LI = LIS . getInterval ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; LIS . removeVRegDefAt ( LI , LIS . getInstructionIndex ( MI ) . getRegSlot ( ) ) ; LIS . RemoveMachineInstrFromMaps ( MI ) ; MI . eraseFromParent


<s> } else SetCC = SetCC . getOperand ( <NUM_LIT> ) ; } switch ( SetCC . getOpcode ( ) ) { case <STR_LIT> : if ( checkAgainstTrue && ! truncatedToBoolWithAnd ) break ; assert ( <STR_LIT> ( SetCC . getConstantOperandVal ( <NUM_LIT> ) ) == <STR_LIT> && <STR_LIT> ) ; case <STR_LIT> : CC = <STR_LIT> ( SetCC . getConstantOperandVal ( <NUM_LIT> ) ) ; if ( needOppositeCond ) CC = <STR_LIT> ( CC ) ; return SetCC . getOperand ( <NUM_LIT> ) ; case <STR_LIT> : { ConstantSDNode * FVal = dyn_cast < ConstantSDNode > ( SetCC . getOperand ( <NUM_LIT> ) ) ; ConstantSDNode * TVal = dyn_cast < ConstantSDNode > ( SetCC . getOperand ( <NUM_LIT> ) ) ; if ( ! TVal ) return SDValue ( ) ; if ( ! FVal ) { SDValue Op = SetCC . getOperand ( <NUM_LIT> ) ; if ( Op . getOpcode ( ) == <STR_LIT> || Op . getOpcode ( ) == <STR_LIT> ) Op = Op . getOperand ( <NUM_LIT> ) ; if ( ( Op . getOpcode ( ) != <STR_LIT> && Op . getOpcode ( ) != <STR_LIT> ) || Op . getResNo ( ) != <NUM_LIT> ) return SDValue ( ) ; } bool FValIsFalse = true ; if ( FVal && FVal -> getZExtValue ( ) != <NUM_LIT> ) { if ( FVal -> getZExtValue ( ) != <NUM_LIT> ) return SDValue ( ) ; needOppositeCond = ! needOppositeCond ; FValIsFalse =


<s> unsigned BitWidth = VT . getSizeInBits ( ) ; unsigned UBFMOpc = BitWidth == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; SDNode * ShiftNode ; if ( ShlAmount > <NUM_LIT> ) { ShiftNode = CurDAG -> getMachineNode ( UBFMOpc , dl , VT , Op , CurDAG -> getTargetConstant ( BitWidth - ShlAmount , dl , VT ) , CurDAG -> getTargetConstant ( BitWidth - <NUM_LIT> - ShlAmount , dl , VT ) ) ; } else { assert ( ShlAmount < <NUM_LIT> && <STR_LIT> ) ; int ShrAmount = - ShlAmount ; ShiftNode = CurDAG -> getMachineNode ( UBFMOpc , dl , VT , Op , CurDAG -> getTargetConstant ( ShrAmount , dl , VT

) , CurDAG -> getTargetConstant ( BitWidth - <NUM_LIT> , dl , VT ) ) ;


<s> if ( Subtarget -> hasSSE2 ( ) ) return <STR_LIT> ; if ( Subtarget -> hasSSE1 ( ) ) return <STR_LIT> ; } else if ( ! MemcpyStrSrc && Size >= <NUM_LIT> && ! Subtarget -> is64Bit ( ) && Subtarget -> getStackAlignment ( ) >= <NUM_LIT> && Subtarget -> hasSSE2 ( ) ) { return <STR_LIT> ; } } if ( Subtarget -> is64Bit ( ) && Size


<s> if ( MI . getOpcode ( ) == <STR_LIT> && MI . getOperand ( <NUM_LIT>

) . getImm ( ) == <NUM_LIT> ) return true ;


<s> FOR_EACH_BB_FN ( bb , cfun ) { insn = BB_END ( bb ) ; while ( insn != BB_HEAD ( bb ) && NOTE_P ( insn ) ) insn = PREV_INSN ( insn ) ; if ( ( control_flow_insn_p ( insn ) && GET_CODE ( PATTERN ( insn ) ) == RETURN ) || ( CALL_P ( insn ) && ( SIBLING_CALL_P ( insn ) || find_reg_note ( insn , REG_NORETURN , NULL_RTX ) ) ) ) { rtx_insn * seq = aarch64_speculation_clobber_sp ( ) ; emit_insn_before ( seq , insn ) ; fixups_pending


<s> if ( USE_HIDDEN_LINKONCE ) sprintf ( name , <STR_LIT> , reg_names [ REGNO ( got_register_rtx ) ] + <NUM_LIT> ) ; else ASM_GENERATE_INTERNAL_LABEL ( name , <STR_LIT> , REGNO ( got_register_rtx ) ) ; got_helper_rtx = gen_rtx_SYMBOL_REF ( Pmode , ggc_strdup ( name )


<s> if ( TREE_CODE ( type ) != RECORD_TYPE ) return false ; const_tree last_field = NULL_TREE ; for ( const_tree f = TYPE_FIELDS ( type ) ; f ; f = TREE_CHAIN ( f ) ) last_field = f ; if ( ! last_field ) return false ; const_tree last_field_type = TREE_TYPE ( last_field ) ; if ( TREE_CODE ( last_field_type ) != ARRAY_TYPE ) return false ; return ( ! TYPE_DOMAIN ( last_field_type ) || ! TYPE_MAX_VALUE


<s> return ; } } if ( MI . getOpcode ( ) == <STR_LIT> ) { MachineOperand & OtherMO = MI . getOperand ( <NUM_LIT> - FIOperandNum ) ; if ( OtherMO . isReg ( ) ) { unsigned OtherMOReg = OtherMO . getReg ( ) ; if ( TargetRegisterInfo :: isVirtualRegister ( OtherMOReg ) ) { MachineInstr * Def = MF . getRegInfo ( ) . getUniqueVRegDef ( OtherMOReg ) ; if ( Def && Def -> getOpcode ( ) == <STR_LIT> && MRI . hasOneNonDBGUse ( Def -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ) { MachineOperand & ImmMO = Def -> getOperand ( <NUM_LIT> ) ; ImmMO . setImm ( ImmMO . getImm ( ) + uint32_t ( FrameOffset ) ) ; MI . getOperand ( FIOperandNum ) . ChangeToRegister ( FrameRegister , false ) ; return ; } } } } const auto * TII = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getInstrInfo ( ) ; unsigned FIRegOperand = FrameRegister ; if ( FrameOffset ) { const TargetRegisterClass * PtrRC = MRI . getTargetRegisterInfo ( ) -> getPointerRegClass ( MF ) ; unsigned OffsetOp = MRI . createVirtualRegister ( PtrRC ) ; BuildMI ( MBB , * II , II -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , OffsetOp ) . addImm ( FrameOffset ) ; FIRegOperand = MRI . createVirtualRegister ( PtrRC ) ; BuildMI ( MBB , * II , II -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , FIRegOperand ) . addReg ( FrameRegister ) . addReg ( OffsetOp ) ; } MI . getOperand ( FIOperandNum ) .

ChangeToRegister ( FIRegOperand , false ) ;


<s> bool <ISA_LIT>InstrInfo :: SubsumesPredicate ( ArrayRef < MachineOperand > Pred1 , ArrayRef < MachineOperand > Pred2 ) const { return false


<s> MIB . addReg ( Info -> getScratchRSrcReg ( ) ) ; } , [ = ] ( MachineInstrBuilder & MIB ) { MIB . addReg ( HighBits ) ; } , [ = ] ( MachineInstrBuilder & MIB ) { const MachineMemOperand * MMO = * MI -> memoperands_begin ( ) ; const MachinePointerInfo & PtrInfo = MMO -> getPointerInfo ( ) ; if ( isStackPtrRelative ( PtrInfo ) ) MIB . addReg ( Info -> getStackPtrOffsetReg ( ) ) ; else MIB . addImm ( <NUM_LIT> ) ; } , [ = ] ( MachineInstrBuilder & MIB ) { MIB . addImm ( Offset & <NUM_LIT> ) ; } } } ; } assert ( Offset == <NUM_LIT> ) ; Optional < int > FI ; Register VAddr = Root . getReg ( ) ; if ( const MachineInstr * RootDef = MRI -> getVRegDef ( Root . getReg ( ) ) ) { if ( isBaseWithConstantOffset ( Root , * MRI ) ) { const MachineOperand & LHS = RootDef -> getOperand ( <NUM_LIT> ) ; const MachineOperand & RHS = RootDef -> getOperand ( <NUM_LIT> ) ; const MachineInstr * LHSDef = MRI -> getVRegDef ( LHS . getReg ( ) ) ; const MachineInstr * RHSDef = MRI -> getVRegDef ( RHS . getReg ( ) ) ; if ( LHSDef && RHSDef ) { int64_t PossibleOffset = RHSDef -> getOperand ( <NUM_LIT> ) . getCImm ( ) -> getSExtValue ( ) ; if ( <ISA_LIT>InstrInfo :: isLegalMUBUFImmOffset ( PossibleOffset ) && ( ! STI . privateMemoryResourceIsRangeChecked ( ) || KnownBits -> signBitIsZero ( LHS . getReg ( ) ) ) ) { if ( LHSDef -> getOpcode ( ) == <STR_LIT> ) FI = LHSDef -> getOperand ( <NUM_LIT> ) . getIndex ( ) ; else VAddr = LHS . getReg ( ) ; Offset = PossibleOffset ; } } } else if ( RootDef -> getOpcode ( ) == <STR_LIT> ) { FI = RootDef -> getOperand ( <NUM_LIT> ) . getIndex ( ) ; } } return { { [ = ] ( MachineInstrBuilder & MIB ) { MIB . addReg ( Info -> getScratchRSrcReg ( ) ) ; } , [ = ] ( MachineInstrBuilder & MIB ) { if ( FI . hasValue ( ) ) MIB . addFrameIndex ( FI . getValue ( ) ) ; else MIB . addReg ( VAddr ) ; } , [ = ] ( MachineInstrBuilder & MIB ) { if ( ! Info -> isEntryFunction ( ) && FI . hasValue ( ) ) MIB . addReg ( Info -> getStackPtrOffsetReg ( ) ) ; else MIB . addImm ( <NUM_LIT> ) ; } , [ = ] ( MachineInstrBuilder & MIB


<s> static bool m32r_pass_by_reference ( cumulative_args_t ca ATTRIBUTE_UNUSED , machine_mode mode , const_tree type , bool named ATTRIBUTE_UNUSED ) { int size ; if ( type ) size = int_size_in_bytes


<s> if ( Subtarget -> ldsRequiresM0Init ( ) ) return glueCopyToM0 ( N , CurDAG -> getTargetConstant ( - <NUM_LIT> , SDLoc ( N ) , <STR_LIT> ) ) ; } else if ( AS == <ISA_LIT>AS :: REGION_ADDRESS ) { MachineFunction & MF = CurDAG -> getMachineFunction ( ) ; unsigned Value = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) -> getGDSSize ( ) ; return glueCopyToM0 ( N , CurDAG -> getTargetConstant ( Value , SDLoc ( N ) , <STR_LIT> ) ) ; } return


<s> case <STR_LIT> : break ; } if ( OverrideNEON && ( VT . is128BitVector ( ) || VT . is64BitVector ( ) ) ) return true ; if ( VT . getFixedSizeInBits ( ) <= <NUM_LIT> ) return false ; if ( VT . getFixedSizeInBits ( ) > Subtarget -> getMinSVEVectorSizeInBits ( ) ) return false ; if ( ! VT . isPow2VectorType ( ) ) return false ; return


<s> return { { [ = ] ( MachineInstrBuilder & MIB ) { MIB . addReg ( Src ) ; } , [ = ]


<s> unsigned InsertReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; MachineInstr & InsMI = * BuildMI ( MBB , I , I . getDebugLoc ( ) , TII . get ( TargetOpcode :: INSERT_SUBREG ) , InsertReg ) . addUse ( ImpDefReg ) . addUse ( SrcReg ) . addImm ( <STR_LIT> ) ; constrainSelectedInstRegOperands ( ImpDefMI , TII , TRI , RBI ) ; constrainSelectedInstRegOperands ( InsMI , TII , TRI , RBI ) ; InsertRegs . push_back ( InsertReg ) ; } } unsigned CopyTo = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; auto FirstCopy = MIB . buildInstr ( TargetOpcode :: COPY , { CopyTo } , { } ) . addReg ( InsertRegs [ <NUM_LIT> ] , <NUM_LIT> , ExtractSubReg ) ; constrainSelectedInstRegOperands ( * FirstCopy , TII , TRI , RBI ) ; unsigned LaneIdx = <NUM_LIT> ; for ( unsigned InsReg : InsertRegs ) { unsigned CopyTo = I . getOperand ( LaneIdx ) . getReg ( ) ; MachineInstr & CopyInst = * BuildMI ( MBB , I , I . getDebugLoc ( ) , TII . get ( CopyOpc ) , CopyTo ) . addUse ( InsReg ) . addImm ( LaneIdx ) ; constrainSelectedInstRegOperands ( CopyInst , TII , TRI , RBI ) ; ++ LaneIdx ; } const TargetRegisterClass * RC = MRI . getRegClassOrNull ( I . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; if ( !


<s> SmallPtrSet < LandingPadInst * , <NUM_LIT> > LandingPads ; bool AllowExceptions = areAllExceptionsAllowed ( ) || EHWhitelistSet . count ( std :: string ( F . getName ( ) ) ) ; for ( BasicBlock & BB : F ) { auto * II = dyn_cast < InvokeInst > ( BB . getTerminator ( ) ) ; if ( ! II ) continue ; Changed = true ; LandingPads . insert ( II -> getLandingPadInst ( ) ) ; IRB . SetInsertPoint ( II ) ; bool NeedInvoke = AllowExceptions && canThrow ( II -> getCalledOperand ( ) ) ; if ( NeedInvoke ) { Value * Threw = wrapInvoke ( II ) ; ToErase . push_back ( II ) ; Value * Cmp = IRB . CreateICmpEQ ( Threw , IRB . getInt32 ( <NUM_LIT> ) , <STR_LIT> ) ; IRB . CreateCondBr ( Cmp , II -> getUnwindDest ( ) , II -> getNormalDest ( ) ) ; } else { SmallVector < Value * , <NUM_LIT> > Args ( II -> arg_begin ( ) , II -> arg_end ( ) ) ; CallInst * NewCall = IRB . CreateCall ( II -> getFunctionType ( ) , II -> getCalledOperand ( ) , Args ) ; NewCall -> takeName ( II ) ; NewCall -> setCallingConv ( II -> getCallingConv ( ) ) ; NewCall -> setDebugLoc ( II -> getDebugLoc ( ) ) ; NewCall -> setAttributes ( II -> getAttributes ( ) ) ; II -> replaceAllUsesWith ( NewCall ) ; ToErase . push_back ( II ) ; IRB . CreateBr ( II -> getNormalDest


<s> AsmPrinter :: emitFunctionEntryLabel ( ) ; <ISA_LIT>TargetStreamer & RTS = static_cast < <ISA_LIT>TargetStreamer & > ( *

OutStreamer -> getTargetStreamer ( ) ) ;


<s> return ( __m256i ) __builtin_ia32_pmovqd512_mask ( ( __v8di ) __A , ( __v8si ) _mm256_undefined_si256 ( ) , ( __mmask8 ) -


<s> unsigned <ISA_LIT>RegisterInfo :: reservedStackPtrOffsetReg ( const MachineFunction & MF ) const { return


<s> case LSHIFTRT : if ( GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == CONST_INT ) { switch ( INTVAL ( XEXP ( x , <NUM_LIT> ) ) ) { case <NUM_LIT> : * total = COSTS_N_INSNS ( <NUM_LIT> ) ; break ; case <NUM_LIT> : * total = COSTS_N_INSNS ( <NUM_LIT> ) ; break ; case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : * total = COSTS_N_INSNS ( <NUM_LIT> ) ; break ; case <NUM_LIT> : * total = COSTS_N_INSNS ( <NUM_LIT> ) ; break ; case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : * total = COSTS_N_INSNS ( <NUM_LIT> ) ; break ; case <NUM_LIT> : * total = COSTS_N_INSNS ( <NUM_LIT> ) ; break ; case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : * total = COSTS_N_INSNS ( <NUM_LIT> ) ; break ; case <NUM_LIT> : * total = COSTS_N_INSNS ( <NUM_LIT> ) ; break ; case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> :


<s> SMLoc S = Parser . getTok ( ) . getLoc ( ) ; if ( getParser ( ) . parseExpression ( IdVal ) ) return MatchOperand_ParseFail ; const MCConstantExpr * MCE = dyn_cast < MCConstantExpr > ( IdVal ) ; assert ( MCE && <STR_LIT> ) ; int64_t Val = MCE -> getValue


<s> bool <ISA_LIT>Subtarget :: enableBundling ( CodeGenOpt :: Level OptLevel ) const { return !


<s> for ( auto R : Regions ) { if ( R -> MaxPressure . getOccupancy ( ST ) >= NewOcc ) break ; DEBUG ( printRegion ( dbgs ( ) , R -> Begin , R -> End , LIS , <NUM_LIT> ) ; printLivenessInfo ( dbgs ( ) , R -> Begin , R -> End , LIS ) ) ; BuildDAG DAG ( * R , * this ) ; const auto MinSchedule = makeMinRegSchedule ( DAG . getTopRoots ( ) , * this ) ; const auto MaxRP = getSchedulePressure ( * R , MinSchedule ) ; DEBUG ( dbgs ( ) << <STR_LIT> ; printSchedRP ( dbgs ( ) , R -> MaxPressure , MaxRP ) ) ; NewOcc = std :: min ( NewOcc , MaxRP . getOccupancy ( ST ) ) ; if ( NewOcc <= Occ ) break ; setBestSchedule ( * R , MinSchedule , MaxRP ) ; } DEBUG ( dbgs ( ) << <STR_LIT> << NewOcc


<s> else if ( Val == <NUM_LIT> ) Parser . Lex ( ) ; else return Error ( L , <STR_LIT> ) ; if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) return Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; Parser . Lex (


<s> } MachineFunction & MF = DAG . getMachineFunction ( ) ; <ISA_LIT>MachineFunctionInfo * MFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; if ( AS == <ISA_LIT>AS :: FLAT_ADDRESS ) AS = MFI -> hasFlatScratchInit ( ) ? <ISA_LIT>AS :: PRIVATE_ADDRESS : <ISA_LIT>AS :: GLOBAL_ADDRESS ; unsigned NumElements = VT . getVectorNumElements ( ) ; if ( AS == <ISA_LIT>AS :: GLOBAL_ADDRESS || AS == <ISA_LIT>AS :: FLAT_ADDRESS ) { if ( NumElements > <NUM_LIT> ) return SplitVectorStore ( Op , DAG ) ; if ( NumElements == <NUM_LIT> && ! Subtarget -> hasDwordx3LoadStores ( ) ) return SplitVectorStore ( Op , DAG ) ; return SDValue ( ) ; } else if ( AS == <ISA_LIT>AS :: PRIVATE_ADDRESS ) { switch ( Subtarget -> getMaxPrivateElementSize ( ) ) { case <NUM_LIT> : return scalarizeVectorStore ( Store , DAG ) ; case <NUM_LIT> : if ( NumElements > <NUM_LIT> ) return SplitVectorStore ( Op , DAG ) ; return SDValue ( ) ; case <NUM_LIT> : if ( NumElements > <NUM_LIT> || NumElements == <NUM_LIT> ) return SplitVectorStore ( Op


<s> } else { MachineInstrBuilder InvertedMI ; int InvertedOpcode ; switch ( MI -> getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : InvertedOpcode = <STR_LIT> ; break ; case <STR_LIT> : InvertedOpcode = <STR_LIT> ; break ; case <STR_LIT> : InvertedOpcode = <STR_LIT> ; break ; case <STR_LIT> : InvertedOpcode = <STR_LIT> ; break ; case <STR_LIT> : InvertedOpcode = <STR_LIT> ; break ; case <STR_LIT> : InvertedOpcode = <STR_LIT> ; break ; case <STR_LIT> : InvertedOpcode = <STR_LIT> ; break ; case <STR_LIT> : InvertedOpcode = <STR_LIT> ; break ; } InvertedMI = BuildMI ( * MBB , MI , MI -> getDebugLoc ( ) , TII -> get ( InvertedOpcode ) ) ; for ( unsigned i = <NUM_LIT> , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) { InvertedMI . addOperand ( MI -> getOperand ( i ) ) ; if ( MI -> getOperand ( i ) . isMBB ( ) ) CondBrMBBOperand = i ; } MI -> eraseFromParent ( ) ; MI = Br . MI = InvertedMI ; } MachineInstr * BMI = & MBB -> back ( ) ; bool NeedSplit = ( BMI != MI ) || ! BBHasFallthrough ( MBB ) ; ++ NumCBrFixed ; if ( BMI != MI ) { if ( std :: next ( MachineBasicBlock :: iterator ( MI ) ) == std :: prev ( MBB -> end ( ) ) && BMI -> getOpcode ( ) == <STR_LIT> ) { MachineBasicBlock * NewDest = BMI -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; if ( isBBInRange ( MI , NewDest , Br . OffsetBits ) ) { DEBUG ( dbgs ( ) << <STR_LIT> << * BMI ) ; MachineBasicBlock * DestBB = MI -> getOperand ( CondBrMBBOperand ) . getMBB ( ) ; BMI -> getOperand ( <NUM_LIT> ) . setMBB ( DestBB ) ; MI -> getOperand ( CondBrMBBOperand ) . setMBB ( NewDest ) ; return true ; } } } if ( NeedSplit ) { MachineBasicBlock :: iterator MBBI = MI ; ++ MBBI ; splitBlockBeforeInstr ( MBBI ) ; int delta = TII -> getInstSizeInBytes ( MBB -> back ( ) ) ; BBInfo [ MBB -> getNumber ( ) ] . Size -= delta ; MBB -> back ( ) . eraseFromParent ( ) ; } MachineBasicBlock * NextBB = std :: next ( MachineFunction :: iterator ( MBB ) ) ; DEBUG ( dbgs ( ) << <STR_LIT> << MI -> getOperand ( CondBrMBBOperand ) . getMBB ( ) -> getNumber ( ) << <STR_LIT> << NextBB -> getNumber (


<s> if ( ! Elt || Elt -> isOpaque ( ) || Elt -> getSimpleValueType ( <NUM_LIT> ) != EltVT ) return SDValue ( ) ; if ( Elt -> getAPIntValue ( ) . isNullValue ( ) ) return SDValue ( ) ; NewVecC . push_back ( DAG . getConstant ( Elt -> getAPIntValue ( ) - <NUM_LIT>


<s> if ( d -> perm [ <NUM_LIT> ] == <NUM_LIT> ) odd = <NUM_LIT> ; else if ( d -> perm [ <NUM_LIT> ] == <NUM_LIT> ) odd = <NUM_LIT> ; else return false ; mask = ( d -> one_vector_p ? nelt - <NUM_LIT> : <NUM_LIT> * nelt - <NUM_LIT> ) ; for ( i = <NUM_LIT> ; i < nelt ; i += <NUM_LIT> ) { if ( d -> perm [ i ] != i + odd ) return false ; if ( d -> perm [ i + <NUM_LIT> ] != ( ( i + nelt + odd ) & mask ) ) return false ; } if ( d -> testing_p ) return true ; in0 = d -> op0 ; in1 = d -> op1 ; if ( BYTES_BIG_ENDIAN ) { x = in0 , in0 = in1 , in1 = x ; odd = ! odd ; } out = d -> target ; if ( odd ) { switch ( vmode ) { case V16QImode : gen = gen_aarch64_trn2v16qi ; break ; case V8QImode : gen = gen_aarch64_trn2v8qi ; break ; case V8HImode : gen = gen_aarch64_trn2v8hi ; break ; case V4HImode : gen = gen_aarch64_trn2v4hi ; break ; case V4SImode : gen = gen_aarch64_trn2v4si ; break ; case V2SImode : gen = gen_aarch64_trn2v2si ; break ; case V2DImode : gen = gen_aarch64_trn2v2di ; break ; case V4HFmode : gen = gen_aarch64_trn2v4hf ; break ; case V8HFmode : gen = gen_aarch64_trn2v8hf ; break ; case V4SFmode : gen = gen_aarch64_trn2v4sf ; break ; case V2SFmode : gen =


<s> if ( ts & BEGIN_DATA ) { if ( ts & BEGIN_CONTROL ) gen_ld = gen_ld_sa ; else gen_ld = gen_ld_a ; } else if ( ts & BEGIN_CONTROL ) { if ( ( spec_info -> flags & SEL_SCHED_SPEC_DONT_CHECK_CONTROL ) || ia64_needs_block_p ( ts ) ) gen_ld = gen_ld_s ; else gen_ld = gen_ld_s_a ; } else if ( ts == <NUM_LIT> ) gen_ld = gen_ld_ ; else gcc_unreachable ( ) ; return gen_ld [


<s> if ( getSTI ( ) . getTargetTriple ( ) . getOS ( ) != Triple :: AMDPAL ) { return Error ( getParser ( ) . getTok ( ) . getLoc ( ) , ( Twine ( PALMD :: AssemblerDirective ) + Twine ( <STR_LIT> <STR_LIT> ) ) . str ( ) ) ; } PALMD :: Metadata PALMetadata ; for ( ; ; )


<s> if ( ! isImm ( ) ) return false ; const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; if ( ! CE ) return


<s> } return true ; } } if ( ( MaskScalarSizeInBits == <NUM_LIT> || MaskScalarSizeInBits == <NUM_LIT> ) && ! ContainsZeros && ( AllowIntDomain || Subtarget . hasAVX ( ) ) ) { SmallVector < int , <NUM_LIT> > RepeatedMask ; if ( is128BitLaneRepeatedShuffleMask ( MaskEltVT , Mask , RepeatedMask ) ) { SmallVector < int , <NUM_LIT> > WordMask = RepeatedMask ; if ( MaskScalarSizeInBits == <NUM_LIT> ) scaleShuffleMask < int > ( <NUM_LIT> , RepeatedMask , WordMask ) ; Shuffle = ( AllowIntDomain ? <STR_LIT> : <STR_LIT> ) ; ShuffleVT = ( AllowIntDomain ? <STR_LIT> : <STR_LIT> ) ; ShuffleVT = <STR_LIT> ( ShuffleVT , InputSizeInBits / <NUM_LIT> ) ; PermuteImm = getV4<ISA_LIT>ShuffleImm ( WordMask ) ; return true ; } } if ( ! ContainsZeros && AllowIntDomain && MaskScalarSizeInBits == <NUM_LIT> ) { SmallVector < int , <NUM_LIT> > RepeatedMask ; if ( is128BitLaneRepeatedShuffleMask ( MaskEltVT , Mask , RepeatedMask ) ) { ArrayRef < int > LoMask ( Mask . data ( ) + <NUM_LIT> , <NUM_LIT> ) ; ArrayRef < int > HiMask ( Mask . data ( ) + <NUM_LIT> , <NUM_LIT> ) ; if ( isUndefOrInRange ( LoMask , <NUM_LIT> , <NUM_LIT> ) && isSequentialOrUndefInRange ( HiMask , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> ) ) { Shuffle = <STR_LIT> ; ShuffleVT = <STR_LIT> ( <STR_LIT> , InputSizeInBits / <NUM_LIT> ) ; PermuteImm = getV4<ISA_LIT>ShuffleImm ( LoMask ) ; return true ; } if ( isUndefOrInRange ( HiMask , <NUM_LIT> , <NUM_LIT> ) && isSequentialOrUndefInRange ( LoMask , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> ) ) { int OffsetHiMask [ <NUM_LIT> ] ; for ( int i = <NUM_LIT> ; i != <NUM_LIT> ; ++ i ) OffsetHiMask [ i ] = ( HiMask [ i ] < <NUM_LIT> ? HiMask [ i ] : HiMask [ i ] - <NUM_LIT> ) ; Shuffle = <STR_LIT> ; ShuffleVT = <STR_LIT> ( <STR_LIT> , InputSizeInBits / <NUM_LIT> ) ; PermuteImm = getV4<ISA_LIT>ShuffleImm ( OffsetHiMask ) ; return true ; } } } if ( AllowIntDomain && ( ( MaskVT . is128BitVector ( ) && Subtarget . hasSSE2 ( ) ) || ( MaskVT . is256BitVector ( ) && Subtarget . hasAVX2 ( ) ) ) ) { int ShiftAmt = matchShuffleAsShift ( ShuffleVT , Shuffle , MaskScalarSizeInBits , Mask , <NUM_LIT> , Zeroable , Subtarget ) ; if ( <NUM_LIT> < ShiftAmt ) { PermuteImm = (


<s> RC = isThumb2 ? & <STR_LIT> : & <STR_LIT> ; break ; case <STR_LIT> : if ( Alignment && Alignment < <NUM_LIT> && ! Subtarget -> allowsUnalignedMem ( ) ) return false ; if ( isThumb2 ) { if ( Addr . Offset < <NUM_LIT> && Addr . Offset > - <NUM_LIT> && Subtarget -> hasV6T2Ops ( ) ) Opc = <STR_LIT> ; else Opc = <STR_LIT> ; } else { Opc = <STR_LIT> ; } RC = isThumb2 ? & <STR_LIT> : & <STR_LIT> ; break ; case <STR_LIT> : if ( ! Subtarget -> hasVFP2 ( ) ) return false ; if ( Alignment && Alignment < <NUM_LIT> ) { needVMOV = true ; VT = <STR_LIT> ; Opc = isThumb2 ? <STR_LIT> : <STR_LIT> ; RC = isThumb2 ? & <STR_LIT> : & <STR_LIT> ; } else { Opc = <STR_LIT> ; RC = TLI . getRegClassFor ( VT ) ; } break ; case <STR_LIT> : if ( ! Subtarget -> hasVFP2 ( ) ) return false ; if ( Alignment && Alignment < <NUM_LIT> ) return false ; Opc = <STR_LIT> ; RC = TLI . getRegClassFor ( VT ) ; break ; } <ISA_LIT>SimplifyAddress ( Addr , VT , useAM3 ) ; if ( allocReg ) ResultReg = createResultReg ( RC ) ; assert ( ResultReg >


<s> } unsigned FrameReg ; if ( FrameIndex >= MinCSFI && FrameIndex <= MaxCSFI ) FrameReg = <STR_LIT> ; else { const TargetFrameLowering * TFI = MF . getTarget ( ) . getFrameLowering ( ) ; if ( TFI -> hasFP ( MF ) ) { FrameReg = <STR_LIT> ; } else { if ( ( MI . getNumOperands ( ) > OpNo + <NUM_LIT> ) && MI . getOperand ( OpNo + <NUM_LIT> ) . isReg ( ) ) FrameReg = MI . getOperand ( OpNo + <NUM_LIT> ) . getReg ( ) ; else FrameReg = <STR_LIT> ; } } int64_t Offset ; Offset = SPOffset + ( int64_t ) StackSize ; Offset += MI . getOperand ( OpNo + <NUM_LIT> ) . getImm ( ) ; DEBUG ( errs ( ) << <STR_LIT> << Offset << <STR_LIT> << <STR_LIT> ) ; if ( ! MI . isDebugValue ( ) && ( ( ( FrameReg != <STR_LIT> ) && ! isInt < <NUM_LIT> > ( Offset ) ) || ( ( FrameReg == <STR_LIT> ) && ! isInt < <NUM_LIT> > ( Offset ) ) ) ) { llvm_unreachable ( <STR_LIT> ) ; } MI . getOperand ( OpNo ) . ChangeToRegister


<s> char * curr_range_str , * next_range_str ; int i = <NUM_LIT> , n = <NUM_LIT> ; if ( is_memset ) default_algs = & ix86_cost -> memset [ TARGET_64BIT != <NUM_LIT> ] ; else default_algs = & ix86_cost -> memcpy [ TARGET_64BIT != <NUM_LIT> ] ; curr_range_str = strategy_str ; do { int maxs ; char alg_name [ <NUM_LIT> ] ; char align [ <NUM_LIT> ] ; next_range_str = strchr ( curr_range_str , ',' ) ; if ( next_range_str ) * next_range_str ++ = '\0' ; if ( <NUM_LIT> != sscanf ( curr_range_str , <STR_LIT> , alg_name , & maxs , align ) ) { error ( <STR_LIT> , curr_range_str , is_memset ? <STR_LIT> : <STR_LIT> ) ; return ; } if ( n > <NUM_LIT> && ( maxs < ( input_ranges [ n - <NUM_LIT> ] . max + <NUM_LIT> ) && maxs != - <NUM_LIT> ) ) { error ( <STR_LIT> , is_memset ?


<s> const MCOperand & MO = MI . getOperand ( OpNo ) ; if ( MO . isReg ( ) || MO . isImm ( ) ) return getMachineOpValue ( MI , MO , Fixups ) ; Fixups . push_back ( MCFixup :: Create ( <NUM_LIT> , MO . getExpr ( ) , ( MCFixupKind ) <STR_LIT> ) ) ; return <NUM_LIT>


<s> Out . EmitInstruction ( Inst ) ; return false ; } case Match_MissingFeature : Error ( IDLoc , <STR_LIT> ) ; return true ; case Match_InvalidOperand : { SMLoc ErrorLoc = IDLoc ; if ( ErrorInfo != ~ <NUM_LIT> ) { if ( ErrorInfo >= Operands . size ( ) ) return Error ( IDLoc , <STR_LIT> ) ; ErrorLoc = ( ( <ISA_LIT>Operand * ) Operands [ ErrorInfo ] ) -> getStartLoc ( ) ; if ( ErrorLoc == SMLoc ( ) ) ErrorLoc = IDLoc ; } return Error ( ErrorLoc ,


<s> void <ISA_LIT>FrameLowering :: emitPrologue ( MachineFunction & MF , MachineBasicBlock & MBB ) const { assert ( & MF . front ( ) == & MBB && <STR_LIT> ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; MachineBasicBlock :: iterator MBBI = MBB . begin ( ) ; unsigned FPReg = getFPReg ( ) ; unsigned SPReg = getSPReg ( ) ; DebugLoc DL


<s> SDValue <ISA_LIT>TargetLowering :: EmitNegate ( const SDLoc & DL , SDValue Op ,


<s> return ( unaligned_access ? ( align >= BITS_PER_WORD && ( offset & <NUM_LIT> ) == <NUM_LIT> ) : ( align >= <NUM_LIT> * BITS_PER_WORD && ( offset & <NUM_LIT> ) ==


<s> LaneBitmask M = AR . Mask & BR . Mask ; return M . any ( ) ? RegisterRef ( AR . Reg


<s> const TargetRegisterClass * DRC = MRI -> getRegClass ( ( * ( MovedInst -> defs ( ) .


<s> if ( I != Z ) continue ; CountBitSplit ++ ; MachineInstr * DefS = MRI . getVRegDef ( S ) ; assert ( DefS != nullptr ) ; DebugLoc DL = DefS -> getDebugLoc ( ) ; MachineBasicBlock & B = * DefS -> getParent ( ) ; auto At = DefS -> isPHI ( ) ? B . getFirstNonPHI ( ) : MachineBasicBlock :: iterator ( DefS ) ; if ( MRI . getRegClass ( SrcR ) -> getID ( ) == <STR_LIT> ) SrcSR = ( std :: min ( Pos , P ) == <NUM_LIT> ) ? <STR_LIT> : <STR_LIT> ; if ( ! validateReg ( { SrcR , SrcSR } , <STR_LIT> , <NUM_LIT> ) ) continue ; unsigned ImmOp = Pos <= P ? W - Z : Z ; unsigned NewR = <NUM_LIT> ; for ( MachineInstr * In : NewMIs ) { if ( In -> getOpcode ( ) != <STR_LIT> ) continue ; MachineOperand & Op1 = In -> getOperand ( <NUM_LIT> ) ; if ( Op1 . getReg ( ) != SrcR || Op1 . getSubReg ( ) != SrcSR ) continue ; if ( In -> getOperand ( <NUM_LIT> ) . getImm ( ) != ImmOp ) continue ; MachineOperand & Op0 = In -> getOperand ( <NUM_LIT> ) ; MachineInstr * DefI = MRI . getVRegDef ( Op0 . getReg ( ) ) ; assert ( DefI != nullptr ) ; if ( ! MDT . dominates ( DefI , & * At ) ) continue ; assert ( Op0 . getSubReg ( ) == <NUM_LIT> ) ; NewR = Op0 . getReg ( ) ; break ; } if ( ! NewR ) { NewR = MRI . createVirtualRegister ( & <STR_LIT> ) ; auto NewBS = BuildMI ( B , At , DL , HII . get ( <STR_LIT> ) , NewR ) . addReg ( SrcR , <NUM_LIT> , SrcSR ) . addImm ( ImmOp ) ; NewMIs . push_back ( NewBS ) ; } if ( Pos <= P ) { HBS :: replaceRegWithSub ( RD . Reg , NewR , <STR_LIT> , MRI ) ; HBS :: replaceRegWithSub ( S , NewR , <STR_LIT> , MRI ) ; } else { HBS :: replaceRegWithSub ( S , NewR , <STR_LIT> , MRI ) ; HBS :: replaceRegWithSub ( RD . Reg , NewR , <STR_LIT> , MRI ) ; } return true ; } return false


<s> handle_move_double ( operands , output_reg_adjust ,


<s> void <ISA_LIT>MachOTargetObjectFile :: Initialize ( MCContext & Ctx ,


<s> Op -> Tok . Data = Str . data ( ) ; Op -> Tok . Length = Str . size (


<s> const <ISA_LIT>InstrInfo * <ISA_LIT>InstrInfo :: create ( <ISA_LIT>Subtarget & STI ) { return new <ISA_LIT>InstrInfo (


<s> Properties ( Props ) , OrigF ( OrigF


<s> OptIncDec = ! ST . slowIncDec ( ) || Func . getFunction ( ) . optForMinSize ( ) ; OptLEA = ST . LEAusesAG ( ) || IsSlowLEA || IsSlow3OpsLEA ; if ( ! OptLEA && ! OptIncDec ) return false ; TSM . init ( & Func . getSubtarget ( ) ) ; TII = ST . getInstrInfo ( ) ; LLVM_DEBUG ( dbgs ( ) <<


<s> const char * name ; size_t nlen , plen ; char * string ; plen = strlen ( prefix ) ; name = IDENTIFIER_POINTER ( DECL_ASSEMBLER_NAME ( decl ) ) ; name = targetm . strip_name_encoding ( name ) ; nlen = strlen ( name ) ; string = alloca ( nlen + plen + <NUM_LIT> ) ; memcpy ( string , prefix , plen ) ; memcpy ( string + plen , name


<s> SDValue VRot ; if ( VRI . RLAmt ) { SDValue Ops [ ] = { VRI . V , getI32Imm ( VRI . RLAmt , dl ) , getI32Imm ( <NUM_LIT> , dl ) , getI32Imm ( <NUM_LIT> , dl ) } ; VRot = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , Ops ) , <NUM_LIT> ) ; } else { VRot = VRI . V ; } SDValue ANDIVal , ANDISVal ; if ( ANDIMask != <NUM_LIT> ) ANDIVal = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , VRot , getI32Imm ( ANDIMask , dl ) ) , <NUM_LIT> ) ; if ( ANDISMask != <NUM_LIT> ) ANDISVal = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , VRot , getI32Imm ( ANDISMask , dl ) ) , <NUM_LIT> ) ; SDValue TotalVal ; if ( ! ANDIVal ) TotalVal = ANDISVal ; else if ( ! ANDISVal ) TotalVal = ANDIVal ; else TotalVal = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , ANDIVal , ANDISVal ) , <NUM_LIT> ) ; if ( ! Res ) Res = TotalVal ; else Res = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , Res , TotalVal ) , <NUM_LIT> ) ; eraseMatchingBitGroups ( [ VRI ] ( const BitGroup & BG ) { return BG . V == VRI . V && BG .


<s> emit_move_insn ( gen_rtx_SUBREG ( SImode , dst , <NUM_LIT> ) , adjust_address ( tmp , SImode , <NUM_LIT> ) ) ; } else emit_move_insn ( dst , copy_rtx ( tmp ) ) ; } else if ( ! TARGET_64BIT && smode == DImode ) { if ( TARGET_SSE4_1 ) { rtx tmp = gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( <NUM_LIT> , const0_rtx ) ) ; emit_insn ( gen_rtx_SET ( gen_rtx_SUBREG ( SImode , dst , <NUM_LIT> ) , gen_rtx_VEC_SELECT ( SImode , gen_rtx_SUBREG ( V4SImode , src , <NUM_LIT> ) , tmp ) ) ) ; tmp = gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( <NUM_LIT> , const1_rtx ) ) ; emit_insn ( gen_rtx_SET ( gen_rtx_SUBREG ( SImode , dst , <NUM_LIT> ) , gen_rtx_VEC_SELECT ( SImode , gen_rtx_SUBREG ( V4SImode , src , <NUM_LIT> ) , tmp ) ) ) ; } else { rtx vcopy = gen_reg_rtx ( V2DImode ) ; emit_move_insn ( vcopy , gen_rtx_SUBREG ( V2DImode , src , <NUM_LIT>


<s> MVT VT = EVT . getSimpleVT ( ) ; switch ( VT . SimpleTy ) { default : return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return emitICmp ( VT , LHS , RHS , IsZExt ) ; case <STR_LIT> : case <STR_LIT> : return emitFCmp ( VT , LHS


<s> vld1_s64 ( const int64_t * __a ) { return ( int64x1_t ) { * __a


<s> if ( SDValue HOp = combineToHorizontalAddSub ( N , DAG , Subtarget ) ) return HOp ; return SDValue ( )


<s> for ( auto & MO : make_range ( MI . operands_begin ( ) + <NUM_LIT> , MI . operands_end ( ) ) ) if ( auto MaybeOperand = MCIL . LowerMachineOperand ( & MI , MO ) ) MCI . addOperand ( MaybeOperand . getValue ( ) ) ; SmallString < <NUM_LIT> > Code ; SmallVector < MCFixup , <NUM_LIT> > Fixups ; raw_svector_ostream VecOS ( Code ) ; CodeEmitter -> encodeInstruction ( MCI , VecOS , Fixups , getSubtargetInfo ( ) ) ; if ( Code . size ( ) < MinSize ) { if ( MinSize == <NUM_LIT> && Opcode == <STR_LIT> ) { MCI . setOpcode ( <STR_LIT> ) ; } else { unsigned NopSize = EmitNop ( * OutStreamer , MinSize , Subtarget -> is64Bit ( ) , getSubtargetInfo ( ) ) ; assert ( NopSize == MinSize && <STR_LIT> ) ; ( void


<s> if ( ( Subtarget . hasFastVectorShiftMasks ( ) && VT . isVector ( ) ) || ( Subtarget . hasFastScalarShiftMasks ( ) && ! VT . isVector ( ) ) ) { return N -> getOperand ( <NUM_LIT> ) == N ->

getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ;


<s> ResolveInfo * rsym = pReloc . symInfo ( ) ; Relocator :: DWord A = pReloc . target ( ) + pReloc . addend ( ) ; Relocator :: DWord S = pReloc . symValue ( ) ; if ( pParent . getRelRelMap ( ) . lookUp ( pReloc ) != NULL ) return Relocator :: BadReloc ; LDSection & target_sect = pReloc . targetRef ( ) . frag ( ) -> getParent ( ) -> getSection ( ) ; if ( ( llvm :: ELF :: SHF_ALLOC & target_sect . flag ( ) ) != <NUM_LIT> && ! rsym -> isLocal ( ) && rsym -> reserved ( ) & <ISA_LIT>Relocator :: ReservePLT ) S = helper_get_PLT_address ( * rsym , pParent ) ; Relocator :: SWord V = S +


<s> static MCStreamer * createMCAsmStreamer ( MCContext & Ctx , formatted_raw_ostream & OS , bool isVerboseAsm , bool useDwarfDirectory , MCInstPrinter * InstPrint , MCCodeEmitter * CE , MCAsmBackend * TAB , bool ShowInst ) { MCStreamer * S = llvm :: createAsmStreamer ( Ctx , OS , isVerboseAsm , useDwarfDirectory ,


<s> static SDValue lowerVectorShuffleAsRotate ( const SDLoc & DL , MVT VT , SDValue V1 , SDValue V2 , ArrayRef < int > Mask , const <ISA_LIT>Subtarget & Subtarget , SelectionDAG & DAG ) { assert ( ( VT . getScalarType ( ) == <STR_LIT> || VT . getScalarType (


<s> bool IsStrict = N -> isTargetStrictFPOpcode ( ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; SDValue In = N -> getOperand ( IsStrict ? <NUM_LIT> : <NUM_LIT> ) ; MVT InVT = In . getSimpleValueType ( ) ; if ( VT . getVectorNumElements ( ) < InVT . getVectorNumElements ( ) && <STR_LIT> ( In . getNode ( ) ) && In . hasOneUse ( ) ) { assert ( InVT . is128BitVector ( ) && <STR_LIT> ) ; LoadSDNode * LN = cast < LoadSDNode > ( In ) ; unsigned NumBits = InVT . getScalarSizeInBits ( ) * VT . getVectorNumElements ( ) ; MVT MemVT = <STR_LIT> ( NumBits ) ; MVT LoadVT = <STR_LIT> ( MemVT , <NUM_LIT> / NumBits ) ; if ( SDValue VZLoad = narrowLoadToVZLoad ( LN , MemVT , LoadVT , DAG ) ) { SDLoc dl ( N ) ; if ( IsStrict ) { SDValue Convert = DAG . getNode ( N -> getOpcode ( ) , dl , { VT , <STR_LIT> } , { N -> getOperand ( <NUM_LIT> ) , DAG . getBitcast ( InVT , VZLoad ) } ) ; DCI . CombineTo ( N , Convert , Convert . getValue ( <NUM_LIT> ) ) ; } else { SDValue Convert = DAG . getNode ( N -> getOpcode ( ) , dl , VT , DAG . getBitcast ( InVT , VZLoad ) ) ; DCI . CombineTo ( N , Convert


<s> static bool will_be_in_index_register ( const_rtx x ) { return GET_CODE ( x ) == UNSPEC && ( XINT ( x


<s> <ISA_LIT>FunctionInfo ( ) : isThumb ( false ) , hasThumb2 ( false ) , VarArgsRegSaveSize ( <NUM_LIT> ) , HasStackFrame ( false ) , RestoreSPFromFP ( false ) , LRSpilledForFarJump ( false ) , FramePtrSpillOffset ( <NUM_LIT> ) , GPRCS1Offset ( <NUM_LIT> ) , GPRCS2Offset ( <NUM_LIT> ) , DPRCSOffset ( <NUM_LIT> ) , GPRCS1Size ( <NUM_LIT> ) ,

GPRCS2Size ( <NUM_LIT> ) , DPRCSSize ( <NUM_LIT> ) , GPRCS1Frames ( <NUM_LIT> ) , GPRCS2Frames ( <NUM_LIT> ) , DPRCSFrames ( <NUM_LIT> ) , JumpTableUId ( <NUM_LIT> ) , PICLabelUId ( <NUM_LIT> ) , VarArgsFrameIndex ( <NUM_LIT> ) , HasITBlocks ( false ) {


<s> if ( ( mi -> getOpcode ( ) == <STR_LIT> || mi -> getOpcode ( ) == <STR_LIT> || mi -> getOpcode ( ) == <STR_LIT> || mi -> getOpcode ( ) == <STR_LIT> ) && mi -> getOperand ( <NUM_LIT> ) . isFI ( ) ) { fi = mi -> getOperand ( <NUM_LIT> ) . getIndex ( ) ; return mi -> getOperand ( <NUM_LIT> ) . getReg ( ) ; } return <NUM_LIT>


<s> bool <ISA_LIT>GOT :: dynSymOrderCompare ( const LDSymbol * pX , const LDSymbol * pY ) const { SymbolOrderMapType :: const_iterator itX = m_SymbolOrderMap . find


<s> for ( auto I : PHIInfo ) { for ( auto <ISA_LIT> : phiInfoElementGetSources ( I ) ) { if ( <ISA_LIT> . second == SourceMBB ) { FoundSource = true ; Sources . push_back ( <ISA_LIT>


<s> bool <ISA_LIT>InstrInfo :: getMachineCombinerPatterns ( MachineInstr & Root , SmallVectorImpl < MachineCombinerPattern > & Patterns , bool DoRegPressureReduce ) const { if ( Subtarget . getTargetMachine ( ) . getOptLevel ( ) != CodeGenOpt :: Aggressive ) return false ; if ( getFMAPatterns ( Root , Patterns ,


<s> O << <STR_LIT> ; if ( isABI ) { if ( Ty -> isFloatingPointTy ( ) || Ty -> isIntegerTy ( ) ) { unsigned size = <NUM_LIT> ; if ( auto * ITy = dyn_cast < IntegerType > ( Ty ) ) { size = ITy -> getBitWidth ( ) ; if ( size < <NUM_LIT> ) size = <NUM_LIT> ; } else { assert ( Ty -> isFloatingPointTy ( ) && <STR_LIT> ) ; size = Ty -> getPrimitiveSizeInBits ( ) ; } O << <STR_LIT> << size << <STR_LIT> ; } else if ( isa < PointerType > ( Ty ) ) { O << <STR_LIT> << TLI -> getPointerTy ( DL ) . getSizeInBits ( ) << <STR_LIT> ; } else if ( Ty -> isAggregateType ( ) || Ty -> isVectorTy ( ) ) { unsigned totalsz = DL . getTypeAllocSize ( Ty ) ; unsigned retAlignment = <NUM_LIT> ; if ( ! llvm :: getAlign ( * F , <NUM_LIT> , retAlignment ) ) retAlignment = DL . getABITypeAlignment ( Ty ) ; O << <STR_LIT> << retAlignment << <STR_LIT> << totalsz << <STR_LIT> ; } else llvm_unreachable ( <STR_LIT> ) ; }