<s> const int maxDForm2Offset = ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ; return DFormAddressPredicate ( Op , N , Disp ,

Base , minDForm2Offset , maxDForm2Offset ) ;


<s> StringRef getPassName ( ) const override { return


<s> llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : Opcode = <STR_LIT> ; break ; } SDVTList VTs = CurDAG -> getVTList ( <STR_LIT> ) ; SDValue Ops [ ] = { Address , Predicate , Base , Modifier , Offset , Chain } ; SDNode * Result = CurDAG -> getMachineNode ( Opcode , dl ,


<s> unsigned int num_of_st = <NUM_LIT> ; for ( unsigned int regno = <NUM_LIT> ; regno < FIRST_PSEUDO_REGISTER ; regno ++ ) if ( ( STACK_REGNO_P ( regno ) || MMX_REGNO_P ( regno ) ) && TEST_HARD_REG_BIT ( need_zeroed_hardregs , regno ) ) { num_of_st ++ ; break ; } if ( num_of_st == <NUM_LIT> ) return false ; bool return_with_x87 = false ; return_with_x87 = ( crtl -> return_rtx && ( STACK_REG_P ( crtl -> return_rtx ) ) ) ; bool complex_return = false ; complex_return = ( crtl -> return_rtx && COMPLEX_MODE_P ( GET_MODE ( crtl -> return_rtx ) ) ) ; if ( return_with_x87 ) if ( complex_return ) num_of_st = <NUM_LIT> ; else num_of_st = <NUM_LIT> ; else num_of_st = <NUM_LIT> ; rtx st_reg = gen_rtx_REG ( XFmode , FIRST_STACK_REG ) ; for ( unsigned int i = <NUM_LIT> ; i < num_of_st ; i ++ ) emit_insn ( gen_rtx_SET ( st_reg , CONST0_RTX ( XFmode ) ) ) ; for ( unsigned int i = <NUM_LIT> ; i < num_of_st ; i ++ ) { rtx insn ; insn = emit_insn ( gen_rtx_SET ( st_reg ,


<s> if ( Subtarget -> is64Bit ( ) ) { if ( ValVT == <STR_LIT> ) { if ( VA . getLocReg ( ) == <STR_LIT> || VA . getLocReg ( ) == <STR_LIT> ) { ValToCopy = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , ValToCopy ) ; ValToCopy = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , ValToCopy ) ; if ( ! Subtarget -> hasSSE2 ( ) ) ValToCopy = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , ValToCopy ) ; } } } Chain = DAG . getCopyToReg ( Chain , dl , VA . getLocReg ( ) , ValToCopy , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; } if ( Subtarget -> is64Bit ( ) && DAG . getMachineFunction ( ) . getFunction ( ) -> hasStructRetAttr ( ) ) { MachineFunction & MF = DAG . getMachineFunction ( ) ; <ISA_LIT>MachineFunctionInfo * FuncInfo = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; unsigned Reg = FuncInfo -> getSRetReturnReg ( ) ; assert ( Reg && <STR_LIT> ) ; SDValue Val = DAG . getCopyFromReg ( Chain , dl , Reg , getPointerTy ( ) ) ; Chain = DAG . getCopyToReg ( Chain , dl , <STR_LIT>


<s> assert ( ImageTy -> getOpcode ( ) == <STR_LIT> ) ; ImageTypeDescriptor TD ( SampledTy , ImageTy -> getOperand ( <NUM_LIT> ) . getImm ( ) , ImageTy -> getOperand ( <NUM_LIT> ) . getImm ( ) , ImageTy -> getOperand ( <NUM_LIT> ) . getImm ( ) , ImageTy -> getOperand ( <NUM_LIT> ) . getImm ( ) , ImageTy -> getOperand ( <NUM_LIT> ) . getImm (

) , ImageTy -> getOperand ( <NUM_LIT> ) . getImm ( ) , ImageTy -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ;


<s> avoid_collisions ( tag_map ) ; if ( dump_file ) { fprintf ( dump_file , <STR_LIT> , loop -> num ) ; tag_map . traverse < void * , dump_insn_list > ( NULL ) ; } tag_map . traverse < void * ,


<s> case ENCODING_CO : case ENCODING_CT : debug ( <STR_LIT> ) ; return true ; case ENCODING_IB : case ENCODING_IW : case ENCODING_ID : case ENCODING_IO : case ENCODING_Iv : case ENCODING_Ia : translateImmediate ( mcInst , insn . immediates [ insn . numImmediatesTranslated ++ ] , operand , insn , Dis ) ; return false ; case ENCODING_SI : return translateSrcIndex ( mcInst , insn ) ; case ENCODING_DI : return translateDstIndex ( mcInst , insn ) ; case ENCODING_RB : case ENCODING_RW : case ENCODING_RD : case


<s> if ( isVarArg ) return false ; MachineFunction & MF = DAG . getMachineFunction ( ) ; CallingConv :: ID CallerCC = MF . getFunction ( ) -> getCallingConv ( ) ; if ( CallerCC != CalleeCC ) return false ; if ( CalleeCC != CallingConv :: Fast && CalleeCC != CallingConv :: C ) return false ; if ( any_of ( Ins , [ ] ( const <STR_LIT> & IA ) { return IA . Flags .


<s> if ( F -> hasDLLExportLinkage ( ) ) DLLExportedFns . insert ( Mang -> makeNameProper ( F -> getName ( ) , <STR_LIT> ) ) ; emitFunctionHeader ( MF ) ; if ( TAI -> doesSupportDebugInformation ( ) || TAI -> doesSupportExceptionHandling ( ) ) DW -> BeginFunction ( & MF ) ; bool hasAnyRealCode = false ; for ( MachineFunction :: const_iterator I = MF . begin ( ) , E = MF . end ( ) ; I != E ; ++ I ) { if ( ! VerboseAsm && ( I -> pred_empty ( ) || I -> isOnlyReachableByFallthrough ( ) ) ) { } else { printBasicBlockLabel ( I , true , true , VerboseAsm ) ; O << '\n' ; } for ( MachineBasicBlock :: const_iterator II = I -> begin ( ) , IE = I -> end ( ) ; II != IE ; ++ II ) { if ( ! II -> isLabel ( ) ) hasAnyRealCode = true ; printMachineInstruction ( II ) ; } } if ( Subtarget -> isTargetDarwin ( ) && ! hasAnyRealCode ) { O << <STR_LIT> ; } if ( TAI -> hasDotTypeDotSizeDirective ( ) ) O << <STR_LIT> << CurrentFnName << <STR_LIT> << CurrentFnName << '\n' ; if ( TAI -> doesSupportDebugInformation ( ) ) DW -> EndFunction ( & MF ) ; EmitJumpTableInfo ( MF . getJumpTableInfo (


<s> auto C = dyn_cast < ConstantInt > ( TM -> getValue ( ) ) ; return C ->


<s> MCObjectWriter * llvm :: create<ISA_LIT>ELFObjectWriter ( raw_ostream & OS , bool Is64Bit , uint8_t


<s> unsigned NumFixedFPRs = <NUM_LIT> ; for ( unsigned I = <NUM_LIT> , E = ArgLocs . size ( ) ; I != E ; ++ I ) { SDValue ArgValue ; CCValAssign & VA = ArgLocs [ I ] ; EVT LocVT = VA . getLocVT ( ) ; if ( VA . isRegLoc ( ) ) { const TargetRegisterClass * RC ; switch ( LocVT . getSimpleVT ( ) . SimpleTy ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : NumFixedGPRs += <NUM_LIT> ; RC = & <STR_LIT> ; break ; case <STR_LIT> : NumFixedGPRs += <NUM_LIT> ; RC = & <STR_LIT> ; break ; case <STR_LIT> : NumFixedFPRs += <NUM_LIT> ; RC = & <STR_LIT> ; break ; case <STR_LIT> : NumFixedFPRs += <NUM_LIT> ; RC = & <STR_LIT> ; break ; } unsigned VReg = MRI . createVirtualRegister ( RC ) ; MRI . addLiveIn ( VA . getLocReg ( ) , VReg ) ; ArgValue = DAG . getCopyFromReg ( Chain , DL , VReg , LocVT ) ; } else { assert ( VA . isMemLoc ( ) && <STR_LIT> ) ; int FI = MFI -> CreateFixedObject ( LocVT . getSizeInBits ( ) / <NUM_LIT> , VA . getLocMemOffset ( ) , true ) ; EVT PtrVT = getPointerTy ( ) ; SDValue FIN = DAG . getFrameIndex ( FI , PtrVT ) ; if ( VA . getLocVT ( ) == <STR_LIT> || VA . getLocVT ( ) == <STR_LIT> ) FIN = DAG . getNode ( <STR_LIT> , DL , PtrVT , FIN , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; ArgValue = DAG . getLoad ( LocVT , DL , Chain , FIN , MachinePointerInfo :: getFixedStack ( FI ) , false , false , false , <NUM_LIT> ) ; } InVals . push_back ( convertLocVTToValVT ( DAG , DL , VA , Chain , ArgValue ) ) ; } if ( IsVarArg ) { FuncInfo -> setVarArgsFirstGPR ( NumFixedGPRs ) ; FuncInfo -> setVarArgsFirstFPR ( NumFixedFPRs ) ; int64_t StackSize = CCInfo . getNextStackOffset ( ) ; FuncInfo -> setVarArgsFrameIndex ( MFI -> CreateFixedObject ( <NUM_LIT> , StackSize , true ) ) ; int64_t RegSaveOffset = TFL -> getOffsetOfLocalArea ( ) ; unsigned RegSaveIndex = MFI -> CreateFixedObject ( <NUM_LIT> , RegSaveOffset , true ) ; FuncInfo -> setRegSaveFrameIndex ( RegSaveIndex ) ; if ( NumFixedFPRs < <STR_LIT> ) { SDValue MemOps [ <STR_LIT> ] ; for ( unsigned I = NumFixedFPRs ; I < <STR_LIT> ; ++ I ) { unsigned Offset = TFL -> getRegSpillOffset ( <STR_LIT> [ I ] ) ; int FI = MFI -> CreateFixedObject ( <NUM_LIT> , RegSaveOffset + Offset , true ) ; SDValue FIN = DAG . getFrameIndex ( FI , getPointerTy (


<s> static int ia64_reloc_rw_mask ( void ) { return flag_pic ? <NUM_LIT> :


<s> MCStreamer & OS = getStreamer ( ) ; OS . PushSection ( ) ; OS . SwitchSection ( <STR_LIT> ( OS . getContext ( ) ) ) ; OS . EmitBytes ( StringRef ( ( const char * ) & Header , sizeof ( Header ) ) ) ; OS . PopSection ( )


<s> static bool doesIgnoreDataTypeSuffix ( StringRef Mnemonic ,


<s> tree function_resolver :: report_no_such_form ( type_suffix_index type ) { error_at ( location , <STR_LIT> , fndecl , get_vector_type ( type ) ) ; return error_mark_node


<s> <ISA_LIT>3DNowLevel = NoThreeDNow ; HasX87 = false ; HasCMov = false ; Has<ISA_LIT>_64 = false ; HasPOPCNT = false ; HasSSE4A = false ; HasAES = false ; HasFXSR = false ; HasXSAVE = false ; HasXSAVEOPT = false ; HasXSAVEC = false ; HasXSAVES = false ; HasPCLMUL = false ; HasFMA = false ; HasFMA4 = false ; HasXOP = false ; HasTBM = false ; HasLWP = false ; HasMOVBE = false ; HasRDRAND = false ; HasF16C = false ; HasFSGSBase = false ; HasLZCNT = false ; HasBMI = false ; HasBMI2 = false ; HasVBMI = false ; HasIFMA = false ; HasRTM = false ; HasERI = false ; HasCDI = false ; HasPFI = false ; HasDQI = false ; HasVPOPCNTDQ = false ; HasBWI = false ; HasVLX = false ; HasADX = false ; HasPKU = false ; HasSHA = false ; HasPRFCHW = false ; HasRDSEED = false ; HasLAHFSAHF = false ; HasMWAITX =


<s> static inline bool hasVecPolicyOp ( uint64_t TSFlags ) { return TSFlags & HasVecPolicyOpMask


<s> { <NUM_LIT> , LegacyLegalizeActions :: Unsupported } , { <NUM_LIT> , LegacyLegalizeActions :: WidenScalar } , { <NUM_LIT> , LegacyLegalizeActions :: Unsupported } , { <NUM_LIT> , LegacyLegalizeActions :: WidenScalar } , { <NUM_LIT> , LegacyLegalizeActions :: Unsupported } } ; addAndInterleaveWithUnsupported ( result , v ) ; auto Largest = result . back ( ) . first ; result . push_back ( { Largest + <NUM_LIT> , LegacyLegalizeActions :: Unsupported } ) ; return


<s> break ; case DFmode : reg = gen_rtx_REG ( DFmode , <NUM_LIT> ) ; break ; case DImode : reg = gen_rtx_REG ( DImode , <NUM_LIT> ) ; break ; default : gcc_unreachable ( ) ; } tmp = gen_rtx_MEM ( QImode , func ) ; tmp = emit_call_insn ( gen_call_value ( reg , tmp , const0_rtx , const0_rtx , const0_rtx ) ) ; CALL_INSN_FUNCTION_USAGE ( tmp ) = usage ; RTL_CONST_CALL_P ( tmp ) = <NUM_LIT> ; tmp = get_insns ( ) ; end_sequence ( )


<s> if ( DstSize != <NUM_LIT> && DstSize != <NUM_LIT> && DstSize != <NUM_LIT> ) return false ; Register Src1Op1 = FAddMI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; Register Src1Op2 = FAddMI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; MachineInstr * Shuffle = getOpcodeDef ( TargetOpcode :: G_SHUFFLE_VECTOR , Src1Op2 , MRI ) ; MachineInstr * Other = MRI . getVRegDef ( Src1Op1 ) ; if ( ! Shuffle ) { Shuffle = getOpcodeDef ( TargetOpcode :: G_SHUFFLE_VECTOR , Src1Op1 , MRI ) ; Other = MRI . getVRegDef ( Src1Op2 ) ; } if ( Shuffle && Shuffle -> getOperand ( <NUM_LIT> ) . getShuffleMask ( ) [ <NUM_LIT> ] == <NUM_LIT> && Other == MRI . getVRegDef ( Shuffle -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ) { std :: get < <NUM_LIT> > (


<s> const TargetInstrInfo * TII = Subtarget . getInstrInfo ( ) ; MachineRegisterInfo & RegInfo = BB -> getParent ( ) -> getRegInfo ( ) ; DebugLoc DL = MI -> getDebugLoc ( ) ; unsigned Wd = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Wd_in = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Lane = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned Fs = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Wt = RegInfo . createVirtualRegister ( Subtarget . useOddSPReg ( ) ? & <STR_LIT> : & <STR_LIT> ) ; BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) , Wt ) . addImm ( <NUM_LIT> ) . addReg ( Fs ) . addImm ( <STR_LIT> ) ; BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) , Wd ) . addReg ( Wd_in )

. addImm ( Lane ) . addReg ( Wt ) . addImm ( <NUM_LIT> ) ;


<s> static <ISA_LIT>Operand * CreateShiftedRegister ( <STR_LIT> ShTy , unsigned SrcReg , unsigned ShiftReg , unsigned ShiftImm , SMLoc S , SMLoc E ) { <ISA_LIT>Operand * Op = new <ISA_LIT>Operand ( k_ShiftedRegister ) ; Op -> RegShiftedReg . ShiftTy = ShTy ; Op -> RegShiftedReg . SrcReg


<s> MachineBasicBlock :: iterator MII = MI . getIterator ( ) ; assert ( ResourceTracker -> canReserveResources ( MI ) ) ; ResourceTracker -> reserveResources (


<s> OutStreamer . EmitRawText ( StringRef ( <STR_LIT> ) ) ; OutStreamer . EmitRawText ( <STR_LIT> + Twine ( Sym -> getName ( ) ) ) ; OutStreamer . EmitRawText ( <STR_LIT> + Twine ( ATy -> getNumElements ( ) ) ) ; if ( GV -> hasWeakLinkage ( ) || GV -> hasLinkOnceLinkage ( ) ) { OutStreamer . EmitRawText ( MAI -> getWeakDefDirective ( ) + Twine ( Sym -> getName ( ) ) +


<s> static bool msp430_pass_by_reference ( cumulative_args_t cap ATTRIBUTE_UNUSED , machine_mode mode , const_tree type , bool


<s> static int ia64_function_arg_offset ( const CUMULATIVE_ARGS * cum , const_tree type , int words ) { if ( TARGET_ABI_OPEN_VMS || ( cum -> words & <NUM_LIT> ) == <NUM_LIT> ) return <NUM_LIT> ; if ( type && TREE_CODE ( type ) != INTEGER_TYPE && TREE_CODE ( type )

!= REAL_TYPE ) return TYPE_ALIGN ( type ) > <NUM_LIT> * BITS_PER_UNIT ;


<s> case TargetOpcode :: G_SEXTLOAD : case TargetOpcode :: G_ZEXTLOAD : { auto MMO = * MI . memoperands_begin ( ) ; const <ISA_LIT>Subtarget & STI = static_cast < const <ISA_LIT>Subtarget & > ( MI . getMF ( ) -> getSubtarget ( ) ) ; if ( ! isPowerOf2_64 ( MMO -> getSize ( ) ) ) return false ; bool isUnaligned = MMO -> getSize ( ) > MMO -> getAlignment ( ) ; if ( ! STI . systemSupportsUnalignedAccess ( ) &&


<s> unsigned DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( SrcReg == <STR_LIT> && TargetRegisterInfo :: isVirtualRegister ( DstReg ) ) { MF . getRegInfo ( ) . constrainRegClass ( DstReg , & <STR_LIT> ) ; return nullptr ; } if ( DstReg == <STR_LIT> && TargetRegisterInfo :: isVirtualRegister ( SrcReg ) ) { MF . getRegInfo ( ) . constrainRegClass ( SrcReg , & <STR_LIT> ) ; return nullptr


<s> const <ISA_LIT>TargetLowering * getTargetLowering ( ) const override { return getSubtargetImpl ( ) -> getTargetLowering (


<s> fprintf ( f , <STR_LIT> , rmw ? <STR_LIT> : <STR_LIT> ) ; fprintf ( f , <STR_LIT> , errata_skip ? <STR_LIT> : <STR_LIT> ) ; int wrap_k = str_prefix_p ( mcu -> name , <STR_LIT> ) ? <NUM_LIT> : str_prefix_p ( mcu -> name , <STR_LIT> ) ? <NUM_LIT> : ( str_prefix_p ( mcu -> name , <STR_LIT> ) || str_prefix_p ( mcu -> name , <STR_LIT> ) ) ? <NUM_LIT> : ( str_prefix_p ( mcu -> name , <STR_LIT> ) || str_prefix_p ( mcu -> name , <STR_LIT> ) || str_prefix_p ( mcu -> name , <STR_LIT> ) ) ? <NUM_LIT> : <NUM_LIT> ; fprintf ( f , <STR_LIT> ) ; if ( wrap_k ) fprintf ( f , <STR_LIT> , wrap_k ) ; fprintf ( f , <STR_LIT> ) ; fprintf ( f , <STR_LIT> , LINK_RELAX_SPEC ) ; fprintf ( f , <STR_LIT> , LINK_ARCH_SPEC ) ; if ( is_device ) { fprintf ( f , <STR_LIT> ) ; if ( mcu -> data_section_start != arch -> default_data_section_start ) fprintf ( f , <STR_LIT> , <NUM_LIT> + mcu -> data_section_start ) ; fprintf ( f , <STR_LIT> ) ; fprintf ( f , <STR_LIT> ) ; if ( mcu -> text_section_start != <NUM_LIT> ) fprintf ( f , <STR_LIT> , <NUM_LIT> + mcu -> text_section_start ) ; fprintf ( f , <STR_LIT> ) ; } if ( is_device ) { fprintf ( f , <STR_LIT> ) ; fprintf ( f , <STR_LIT> , arch -> name ) ; fprintf ( f , <STR_LIT> , sp8_spec ) ; fprintf ( f , <STR_LIT> , help_dev_lib_name ) ; fprintf ( f , <STR_LIT> ) ; fprintf ( f , <STR_LIT> , mcu -> macro , mcu -> name ) ; fprintf ( f , <STR_LIT> ) ; } fprintf ( f ,


<s> int PIdx = MI -> findFirstPredOperandIdx ( ) ; return PIdx != - <NUM_LIT> && MI -> getOperand ( PIdx ) . getImm ( )


<s> Optional < int > FI ; if ( FuncInfo -> isCalleeSavedReg ( CSRegs , LowestAvailableVGPR ) ) FI = FrameInfo . CreateSpillStackObject ( <NUM_LIT> , Align ( <NUM_LIT> ) ) ; const auto * ReservedVGPRInfoItr = std :: find_if ( FuncInfo -> getSGPRSpillVGPRs ( ) . begin ( ) , FuncInfo -> getSGPRSpillVGPRs ( ) . end ( ) , [ PreReservedVGPR ] ( const auto & SpillRegInfo ) { return SpillRegInfo . VGPR == PreReservedVGPR ; } ) ; assert ( ReservedVGPRInfoItr != FuncInfo -> getSGPRSpillVGPRs ( ) . end ( ) ) ; auto Index = std :: distance ( FuncInfo -> getSGPRSpillVGPRs ( ) . begin ( ) , ReservedVGPRInfoItr ) ; FuncInfo -> setSGPRSpillVGPRs ( LowestAvailableVGPR , FI , Index ) ; for ( MachineBasicBlock & MBB : MF ) { MBB . addLiveIn ( LowestAvailableVGPR ) ; MBB . sortUniqueLiveIns ( ) ; } return true


<s> const InstrItineraryData * getInstrItineraryData ( ) const override { return


<s> EVT MemVT = Store -> getMemoryVT ( ) ; SDValue Chain = Store -> getChain ( ) ; SDValue BasePtr = Store -> getBasePtr ( ) ; SDLoc SL ( Op ) ; EVT LoVT , HiVT ; EVT LoMemVT , HiMemVT ; SDValue Lo , Hi ; std :: tie ( LoVT , HiVT ) = DAG . GetSplitDestVTs ( VT ) ; std :: tie ( LoMemVT , HiMemVT ) = DAG . GetSplitDestVTs ( MemVT ) ; std :: tie ( Lo , Hi ) = DAG . SplitVector ( Val , SL , LoVT , HiVT ) ; EVT PtrVT = BasePtr . getValueType ( ) ; SDValue HiPtr = DAG . getNode ( <STR_LIT> , SL , PtrVT , BasePtr , DAG . getConstant ( LoMemVT . getStoreSize ( ) , SL , PtrVT ) ) ; const MachinePointerInfo & SrcValue = Store -> getMemOperand ( ) ->


<s> bool <ISA_LIT>FrameLowering :: canUseRedZone ( const MachineFunction & MF ) const { if ( ! EnableRedZone ) return false ; if ( MF . getFunction ( ) . hasFnAttribute ( Attribute :: NoRedZone ) ) return false ; const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; unsigned NumBytes = AFI


<s> case MCSymbolRefExpr :: VK_<ISA_LIT>_ADDR16_HI : return ELF :: R_<ISA_LIT>_ADDR16_HI ; case MCSymbolRefExpr :: VK_<ISA_LIT>_ADDR24_BANK : return ELF :: R_<ISA_LIT>_ADDR24_BANK ; case MCSymbolRefExpr :: VK_<ISA_LIT>_ADDR24_SEGMENT_LO : return ELF :: R_<ISA_LIT>_ADDR24_SEGMENT_LO ; case MCSymbolRefExpr :: VK_<ISA_LIT>_ADDR24_SEGMENT_HI : return ELF :: R_<ISA_LIT>_ADDR24_SEGMENT_HI ; } case FK_Data_2 : switch ( Modifier ) { default : llvm_unreachable ( <STR_LIT> ) ; case MCSymbolRefExpr :: VK_None : return ELF :: R_<ISA_LIT>_ADDR16 ; case MCSymbolRefExpr :: VK_<ISA_LIT>_ADDR24_SEGMENT : return ELF :: R_<ISA_LIT>_ADDR24_SEGMENT ; } case <STR_LIT> : return ELF :: R_<ISA_LIT>_IMM8 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_ADDR8 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_ADDR16 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_ADDR16_LO ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_ADDR16_HI ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_ADDR24 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_ADDR24_BANK ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_ADDR24_SEGMENT ; case


<s> std :: shared_ptr < msgpack :: Node > & getHSAMetadataRoot ( ) { return HSAMetadataRoot


<s> void <ISA_LIT>TargetStreamer :: emitRawBytes ( StringRef Data ) { MCTargetStreamer :: emitRawBytes ( Data ) ; const MCAsmInfo * MAI = Streamer . getContext ( ) . getAsmInfo ( ) ; const char * Directive = MAI -> getData8bitsDirective ( ) ; unsigned NumElements = Data . size ( ) ; const unsigned MaxLen = <NUM_LIT> ; unsigned NumChunks = <NUM_LIT> + ( ( NumElements - <NUM_LIT> ) / MaxLen ) ; for ( unsigned I = <NUM_LIT> ; I < NumChunks ; ++ I ) { SmallString < <NUM_LIT> > Str ; raw_svector_ostream OS (


<s> switch ( Op . getOpcode ( ) ) { default : llvm_unreachable (


<s> static int compute_total_frame_size ( void ) { int total_size = ( get_frame_size ( ) + tilepro_saved_regs_size ( ) + crtl -> outgoing_args_size + crtl -> args . pretend_args_size ) ; if ( ! tilepro_current_function_is_leaf ( ) || cfun -> calls_alloca ) { total_size += STACK_POINTER_OFFSET


<s> } ) ; PB . registerOptimizerLastEPCallback ( [ = ] ( ModulePassManager & MPM , PassBuilder :: OptimizationLevel Level ) { LoopPassManager LPM ( DebugPassManager ) ; FunctionPassManager FPM ( DebugPassManager ) ; LPM . addPass ( <ISA_LIT>VectorLoopCarriedReusePass ( ) ) ; FPM . addPass ( createFunctionToLoopPassAdaptor ( std :: move ( LPM ) ) ) ; MPM . addPass ( createModuleToFunctionPassAdaptor ( std :: move ( FPM ) ) ) ; }


<s> gcc_assert ( ! ix86_eax_live_at_start_p ( ) ) ; gcc_assert ( m -> fs . sp_offset >= frame . sse_reg_save_offset ) ; align = GET_MODE_ALIGNMENT ( V4SFmode ) ; addr = choose_baseaddr ( frame . stack_realign_offset + xlogue . get_stub_ptr_offset ( ) , & align , AX_REG ) ; gcc_assert ( align >= GET_MODE_ALIGNMENT ( V4SFmode ) ) ; emit_insn ( gen_rtx_SET ( rax , addr ) ) ; sym = xlogue . get_stub_rtx ( frame_pointer_needed ? XLOGUE_STUB_SAVE_HFP : XLOGUE_STUB_SAVE ) ; RTVEC_ELT ( v , vi ++ ) = gen_rtx_USE ( VOIDmode , sym ) ; for ( i = <NUM_LIT> ; i < ncregs ; ++ i ) { const xlogue_layout :: reginfo & r = xlogue . get_reginfo ( i ) ; rtx reg = gen_rtx_REG ( ( SSE_REGNO_P ( r . regno )

? V4SFmode : word_mode ) , r . regno ) ;


<s> return ( vector unsigned int ) __builtin_altivec_vaddcuw ( ( vector signed int ) a1 , ( vector


<s> int xstormy16_carry_plus_operand ( rtx x , enum machine_mode mode ATTRIBUTE_UNUSED ) { return ( GET_CODE ( x ) == PLUS && GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == CONST_INT && ( INTVAL ( XEXP (

x , <NUM_LIT> ) ) < - <NUM_LIT> || INTVAL ( XEXP ( x , <NUM_LIT> ) ) > <NUM_LIT> ) ) ;


<s> if ( riscv_v_ext_vector_mode_p ( mode ) ) { scalar_mode inner_mode = GET_MODE_INNER ( mode ) ; REAL_VALUE_TYPE f = REAL_VALUE_ATOF ( <STR_LIT> , inner_mode ) ; rtx ele = const_double_from_real_value ( f , inner_mode ) ; start_sequence ( ) ; rtx dest = gen_reg_rtx ( mode ) ; rtx dup = gen_const_vec_duplicate ( mode , ele ) ; emit_move_insn ( dest , dup ) ; rtx_insn * insn = get_last_insn ( ) ; rtx src = XEXP ( SET_SRC ( PATTERN ( insn ) ) , <NUM_LIT> ) ; ASSERT_TRUE ( rtx_equal_p ( src , gen_rtx_VEC_DUPLICATE ( mode , XEXP ( src , <NUM_LIT> ) ) ) ) ; end_sequence ( ) ; } } FOR_EACH_MODE_IN_CLASS ( mode , MODE_VECTOR_BOOL ) { if ( riscv_v_ext_vector_mode_p ( mode ) ) { start_sequence ( ) ; rtx dest = gen_reg_rtx ( mode ) ; emit_move_insn ( dest , CONSTM1_RTX ( mode ) ) ; rtx_insn * insn =


<s> return ST -> isFPOnlySP ( ) ? TargetTransformInfo :: TCC_Expensive : TargetTransformInfo :: TCC_Basic ; } } return TargetTransformInfo :: TCC_Expensive


<s> return true ; case AsmToken :: Identifier : { if ( ! tryParseRegisterWithWriteBack ( Operands ) ) return false ; int Res = tryParseShiftRegister ( Operands ) ; if ( Res == <NUM_LIT> ) return false ; else if ( Res == - <NUM_LIT> ) return true ; if ( Mnemonic == <STR_LIT> && Parser . getTok ( ) . getString ( ) == <STR_LIT> ) { S = Parser . getTok ( ) . getLoc ( ) ; Parser . Lex ( ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateToken ( <STR_LIT> , S ) ) ; return false ; } } case AsmToken :: LParen : case AsmToken :: Integer : case AsmToken :: String : case AsmToken :: Dot : { const MCExpr * IdVal ; S = Parser . getTok ( ) . getLoc ( ) ; if ( getParser ( ) . ParseExpression ( IdVal ) ) return true ; E = SMLoc :: getFromPointer ( Parser . getTok ( ) . getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateImm ( IdVal , S , E ) ) ; return false ; } case AsmToken :: LBrac : return parseMemory ( Operands ) ; case AsmToken :: LCurly : return parseRegisterList ( Operands ) ; case AsmToken :: Dollar : case AsmToken :: Hash : { S = Parser . getTok ( ) . getLoc ( ) ; Parser . Lex ( ) ; bool isNegative = Parser . getTok ( ) . is ( AsmToken :: Minus ) ; const MCExpr * ImmVal ; if ( getParser ( ) . ParseExpression ( ImmVal ) ) return true ; const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( ImmVal ) ; if ( CE ) { int32_t Val = CE -> getValue ( ) ; if ( isNegative && Val == <NUM_LIT> ) ImmVal = MCConstantExpr :: Create ( INT32_MIN , getContext ( ) ) ; } E = SMLoc :: getFromPointer ( Parser . getTok ( ) . getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateImm ( ImmVal , S , E ) ) ; return false ; } case AsmToken :: Colon : { <ISA_LIT>MCExpr ::


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> return parsePCRel ( Operands , - ( <NUM_LIT> << <NUM_LIT> ) , ( <NUM_LIT> << <NUM_LIT> )


<s> Val = MO . getImm ( ) ; return true ; } if ( ! MO . isReg ( ) ) return false ; int64_t TV ; unsigned R = MO . getReg ( ) ; if ( ! TargetRegisterInfo :: isVirtualRegister ( R ) ) return false ; MachineInstr * DI = MRI -> getVRegDef ( R ) ; unsigned DOpc = DI -> getOpcode ( ) ; switch ( DOpc ) { case TargetOpcode :: COPY : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { if ( ! checkForImmediate ( DI -> getOperand ( <NUM_LIT> ) , TV ) ) return false ; break ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { const MachineOperand & S1 = DI -> getOperand ( <NUM_LIT> ) ; const MachineOperand & S2 = DI -> getOperand ( <NUM_LIT> ) ; int64_t V1 , V2 ; if ( ! checkForImmediate ( S1 , V1 ) || ! checkForImmediate ( S2 , V2 ) ) return false ; TV = V2 | ( V1 << <NUM_LIT> ) ; break ; } case TargetOpcode :: REG_SEQUENCE : { const MachineOperand & S1 = DI -> getOperand ( <NUM_LIT> ) ; const MachineOperand & S3 = DI -> getOperand ( <NUM_LIT> ) ; int64_t V1 , V3 ; if ( ! checkForImmediate ( S1 , V1 ) || ! checkForImmediate ( S3 , V3 ) ) return false ; unsigned Sub2 = DI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned Sub4 = DI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( Sub2 == <STR_LIT> && Sub4 == <STR_LIT> ) TV = V1 | ( V3 << <NUM_LIT> ) ; else if ( Sub2 == <STR_LIT> && Sub4 == <STR_LIT> ) TV = V3 | ( V1 << <NUM_LIT> ) ; else llvm_unreachable ( <STR_LIT> ) ; break ; } default : return false ; } switch ( MO . getSubReg


<s> case - <NUM_LIT> : * total = <NUM_LIT> + ( outer_code == SET ) ; return true ; case <NUM_LIT> : case - <NUM_LIT> : if ( TARGET_H8300H || TARGET_H8300S ) * total = <NUM_LIT> + ( outer_code == SET ) ; else * total = <NUM_LIT> ; return true ; } } * total = <NUM_LIT> ; return true ; } case CONST : case LABEL_REF : case SYMBOL_REF : if ( TARGET_H8300SX ) { * total = <NUM_LIT> ; return true ; } * total = <NUM_LIT> ; return true ; case CONST_DOUBLE : * total = <NUM_LIT> ; return true ; case COMPARE : if ( XEXP ( x , <NUM_LIT> ) == const0_rtx ) * total = <NUM_LIT> ; return false ; case AND : if ( ! h8300_dst_operand ( XEXP ( x , <NUM_LIT> ) , VOIDmode ) || ! h8300_src_operand ( XEXP ( x , <NUM_LIT> ) , VOIDmode ) ) return false ; * total = COSTS_N_INSNS ( h8300_and_costs ( x ) ) ; return true ; case MOD : case DIV : case UMOD : case UDIV : if ( TARGET_H8300SX ) switch ( GET_MODE ( x ) ) { case QImode : case HImode : * total = COSTS_N_INSNS ( ! speed ? <NUM_LIT> : <NUM_LIT> ) ; return false ; case SImode : * total = COSTS_N_INSNS ( ! speed ? <NUM_LIT> : <NUM_LIT> ) ; return false ; default : break ; } * total = COSTS_N_INSNS ( <NUM_LIT> ) ; return true ; case MULT : if ( TARGET_H8300SX ) switch ( GET_MODE ( x ) ) { case QImode : case HImode : * total = COSTS_N_INSNS ( <NUM_LIT> ) ; return false ; case SImode : * total = COSTS_N_INSNS ( <NUM_LIT> ) ; return false ; default : break ; } * total = COSTS_N_INSNS ( <NUM_LIT> ) ; return true ; case ASHIFT : case ASHIFTRT : case LSHIFTRT : if ( h8sx_binary_shift_operator ( x , VOIDmode ) ) { * total = COSTS_N_INSNS ( <NUM_LIT> ) ; return false ; } else if ( h8sx_unary_shift_operator ( x , VOIDmode ) ) { * total = COSTS_N_INSNS ( <NUM_LIT> ) ; return false ; } * total = COSTS_N_INSNS ( h8300_shift_costs ( x ) ) ; return true ; case ROTATE : case ROTATERT : if ( GET_MODE ( x ) == HImode ) * total = <NUM_LIT> ; else * total = <NUM_LIT> ; return true ; default : * total = COSTS_N_INSNS (


<s> static unsigned getSpecialRegForName ( StringRef RegName ) { return StringSwitch < unsigned > ( RegName ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT>

, <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( <NUM_LIT> ) ;


<s> HOST_WIDE_INT gp_reg_size ; HOST_WIDE_INT fp_reg_size ; long mask ; gp_reg_size = <NUM_LIT> ; fp_reg_size = <NUM_LIT> ; mask = <NUM_LIT> ; extra_size = IQ2000_STACK_ALIGN ( ( <NUM_LIT> ) ) ; var_size = IQ2000_STACK_ALIGN ( size ) ; args_size = IQ2000_STACK_ALIGN ( crtl -> outgoing_args_size ) ; if ( args_size == <NUM_LIT> && cfun -> calls_alloca ) args_size = <NUM_LIT> * UNITS_PER_WORD ; total_size = var_size + args_size + extra_size ; for ( regno = GP_REG_FIRST ; regno <= GP_REG_LAST ; regno ++ ) { if ( MUST_SAVE_REGISTER ( regno ) ) { gp_reg_size += GET_MODE_SIZE ( gpr_mode ) ; mask |= <NUM_LIT> << ( regno - GP_REG_FIRST ) ; } } if ( crtl -> calls_eh_return ) { unsigned int i ; for ( i = <NUM_LIT> ; ; ++ i ) { regno = EH_RETURN_DATA_REGNO ( i ) ; if ( regno == ( int ) INVALID_REGNUM ) break ; gp_reg_size += GET_MODE_SIZE ( gpr_mode ) ; mask |= <NUM_LIT> << ( regno - GP_REG_FIRST ) ; } } gp_reg_rounded = IQ2000_STACK_ALIGN ( gp_reg_size ) ; total_size += gp_reg_rounded + IQ2000_STACK_ALIGN ( fp_reg_size ) ; if ( total_size == extra_size && ! profile_flag ) total_size = extra_size = <NUM_LIT> ; total_size += IQ2000_STACK_ALIGN ( crtl -> args . pretend_args_size ) ; cfun -> machine -> total_size = total_size ; cfun -> machine -> var_size = var_size ; cfun -> machine -> args_size = args_size ; cfun -> machine -> extra_size = extra_size ; cfun -> machine -> gp_reg_size = gp_reg_size ; cfun -> machine -> fp_reg_size = fp_reg_size ; cfun -> machine -> mask = mask ; cfun -> machine -> initialized = reload_completed ; cfun -> machine -> num_gp = gp_reg_size / UNITS_PER_WORD ; if ( mask ) { unsigned long offset ; offset = ( args_size + extra_size + var_size + gp_reg_size - GET_MODE_SIZE ( gpr_mode ) ) ; cfun -> machine -> gp_sp_offset = offset ; cfun -> machine -> gp_save_offset = offset


<s> <STR_LIT> Flags = Ins [ i ] . Flags ; bool AlwaysUseMutable = ( CallConv == CallingConv :: Fast ) && PerformTailCallOpt ; bool isImmutable = ! AlwaysUseMutable && ! Flags . isByVal ( ) ; EVT ValVT ; if ( VA . getLocInfo ( ) == CCValAssign :: Indirect ) ValVT = VA . getLocVT ( ) ; else ValVT = VA . getValVT ( ) ; int FI = MFI -> CreateFixedObject ( ValVT . getSizeInBits ( ) / <NUM_LIT> , VA .


<s> SCAEdge newEdge ( parent , this , site ) ; parent -> Children . insert ( newEdge ) ; Parents . insert ( newEdge


<s> if ( is<ISA_LIT> ( STI ) || isCI ( STI ) || isVI ( STI ) ) return ID_SYMBOLIC_FIRST_GFX9_ ; else if ( isGFX9 ( STI ) ) return ID_SYMBOLIC_FIRST_GFX10_ ; else return


<s> static rtx rs6000_expand_unop_builtin ( enum insn_code icode , tree exp , rtx target ) { rtx pat ; tree arg0 = CALL_EXPR_ARG ( exp , <NUM_LIT> ) ; rtx op0 = expand_normal ( arg0 ) ; machine_mode tmode = insn_data [ icode ] . operand [ <NUM_LIT> ] . mode ; machine_mode mode0 = insn_data [ icode ] . operand [ <NUM_LIT> ] . mode ; if ( icode == CODE_FOR_nothing ) return


<s> <ISA_LIT>AsmPrinter ( TargetMachine & TM , std :: unique_ptr < MCStreamer > Streamer ) : AsmPrinter ( TM , std :: move ( Streamer ) ) , MCInstLowering ( OutContext , * this ) , CurrCodeEnd ( <NUM_LIT> ) { if ( ! ( PTM = static_cast < <ISA_LIT>TargetMachine * > ( & TM ) ) ) { llvm_unreachable ( <STR_LIT>


<s> initializeGCNNSAReassignPass ( * PassRegistry :: getPassRegistry (


<s> inline void EmitPersonalityIndex ( unsigned PI ) { assert ( PI < <STR_LIT> :: NUM_PERSONALITY_INDEX && <STR_LIT> ) ; EmitByte ( <STR_LIT> :: EHT_COMPACT |


<s> MachineInstrBuilder MIB = BuildMI ( MBB , I , I -> getDebugLoc ( ) , get ( Opc ) , DestReg ) ; if ( Subtarget . isMClass ( ) ) MIB . addImm ( <NUM_LIT> ) ; MIB . add ( predOps ( <STR_LIT> ) ) . addReg ( <STR_LIT>

, RegState :: Implicit | getKillRegState ( KillSrc ) ) ;


<s> Triple TheTriple ( TT ) ; if ( TheTriple . getArch ( ) == Triple :: nvptx64 ) { PointerSize = CalleeSaveStackSlotSize = <NUM_LIT> ; } CommentString = <STR_LIT> ; PrivateGlobalPrefix = <STR_LIT> ; AllowPeriodsInName = false


<s> DL = & F . getParent ( ) -> getDataLayout ( ) ; DominatorTreeWrapperPass * const DTW = getAnalysisIfAvailable < DominatorTreeWrapperPass > ( ) ; DT = DTW ? & DTW -> getDomTree ( ) : nullptr ; const TargetPassConfig & TPC = getAnalysis < TargetPassConfig > ( ) ; const TargetMachine & TM = TPC . getTM < TargetMachine > ( ) ; const GCNSubtarget & ST = TM . getSubtarget < GCNSubtarget > ( F ) ; HasDPP = ST . hasDPP (


<s> assert ( ST -> useHVXOps ( ) ) ; NewOpc = <STR_LIT> ; } else llvm_unreachable ( <STR_LIT> ) ; BuildMI ( * BB , InsertPt , DL , TII -> get ( NewOpc ) , DoubleDestReg ) . addReg ( HiReg , HiRegKillFlag ) .


<s> unsigned n_pieces ; int piece = align ; rtx store [ <NUM_LIT> ] ; rtx tmpx [ <NUM_LIT> ] ; int i ; if ( ! CONST_INT_P ( operands [ <NUM_LIT> ] ) ) return false ; size = INTVAL ( operands [ <NUM_LIT> ] ) ; if ( align >= <NUM_LIT> ) n_pieces = ( size + <NUM_LIT> ) / <NUM_LIT> + ( size & <NUM_LIT> ) ; else if ( align == <NUM_LIT> ) n_pieces = ( size + <NUM_LIT> ) / <NUM_LIT> ; else n_pieces = size ; if ( n_pieces >= ( unsigned int ) ( optimize_size ? <NUM_LIT> : <NUM_LIT> ) ) return false ; if ( piece > <NUM_LIT> ) piece = <NUM_LIT> ; dst_addr = force_offsettable ( XEXP ( operands [ <NUM_LIT> ] , <NUM_LIT> ) , size , <NUM_LIT> ) ; src_addr = force_offsettable ( XEXP ( operands [ <NUM_LIT> ] , <NUM_LIT> ) , size , <NUM_LIT> ) ; store [ <NUM_LIT> ] = store [ <NUM_LIT> ] = NULL_RTX ; tmpx [ <NUM_LIT> ] = tmpx [ <NUM_LIT> ] = NULL_RTX ; for ( i = <NUM_LIT> ; size > <NUM_LIT> ; i ^= <NUM_LIT> , size -= piece ) { rtx tmp ; machine_mode mode ; if ( piece > size ) piece = size & - size ; mode = smallest_mode_for_size ( piece * BITS_PER_UNIT , MODE_INT ) ; if ( <NUM_LIT> && tmpx [ i ] && GET_MODE ( tmpx [ i ] ) == mode ) tmp = tmpx [ i ] ; else tmpx [ i ] = tmp = gen_reg_rtx ( mode ) ; dst_addr = force_offsettable ( dst_addr , piece , <NUM_LIT> ) ; src_addr = force_offsettable ( src_addr , piece , <NUM_LIT> ) ; if ( store [ i ] ) emit_insn ( store [ i ] ) ; emit_move_insn ( tmp , change_address ( src , mode , src_addr ) ) ; store [ i ] = gen_move_insn ( change_address ( dst , mode , dst_addr ) , tmp ) ; dst_addr = plus_constant ( Pmode , dst_addr , piece ) ; src_addr = plus_constant ( Pmode , src_addr , piece ) ; } if ( store [ i ] ) emit_insn ( store [ i ] ) ; if ( store [ i ^ <NUM_LIT> ] ) emit_insn ( store [ i ^ <NUM_LIT> ] ) ; return


<s> BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( <STR_LIT> ) ) ; return true ; } case <STR_LIT> : case <STR_LIT> : { const Function * Callee = I . getCalledFunction ( ) ; const Type * RetTy = cast < StructType > ( Callee -> getReturnType ( ) ) -> getTypeAtIndex ( unsigned ( <NUM_LIT> ) ) ; EVT VT ; if ( ! isTypeLegal ( RetTy , VT ) ) return false ; const Value * Op1 = I . getArgOperand ( <NUM_LIT> ) ; const Value * Op2 = I . getArgOperand ( <NUM_LIT> ) ; unsigned Reg1 = getRegForValue ( Op1 ) ; unsigned Reg2 = getRegForValue ( Op2 ) ; if ( Reg1 == <NUM_LIT> || Reg2 == <NUM_LIT> ) return false ; unsigned OpC = <NUM_LIT> ; if ( VT == <STR_LIT> ) OpC = <STR_LIT> ; else if ( VT == <STR_LIT> ) OpC = <STR_LIT> ; else return false ; unsigned ResultReg = createResultReg ( TLI . getRegClassFor ( VT ) ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( OpC ) , ResultReg ) . addReg ( Reg1 ) . addReg ( Reg2 ) ; unsigned DestReg1 = UpdateValueMap ( & I , ResultReg ) ; if ( DestReg1 != ResultReg ) ResultReg = DestReg1 + <NUM_LIT> ; else ResultReg = createResultReg ( TLI . getRegClassFor ( <STR_LIT> ) ) ; unsigned Opc = <STR_LIT> ; if ( I . getIntrinsicID ( ) == <STR_LIT> ) Opc = <STR_LIT> ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII


<s> if ( crtl -> calls_eh_return && regno >= <NUM_LIT> && regno < <NUM_LIT> ) return true ; return ! call_used_or_fixed_reg_p ( regno ) && df_regs_ever_live_p


<s> SelectionDAG & DAG = DCI . DAG ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( N -> getOpcode ( ) == <STR_LIT> && ( VT == <STR_LIT> || VT == <STR_LIT> ) ) return PerformSRACombine ( N , DCI ) ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; if ( ! VT . isVector ( ) || ! TLI . isTypeLegal ( VT ) ) return SDValue ( ) ; assert ( ST -> hasNEON ( ) && <STR_LIT> ) ; int64_t Cnt ; switch ( N -> getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : if ( isVShiftLImm ( N -> getOperand ( <NUM_LIT> ) , VT , Cnt ) ) { SDValue RHS = DAG . getNode ( <STR_LIT> , SDLoc ( N -> getOperand ( <NUM_LIT> ) ) , VT , DAG . getConstant ( Cnt , <STR_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , VT , N -> getOperand ( <NUM_LIT> ) , RHS ) ; } break ; case <STR_LIT> : case <STR_LIT> : if ( isVShiftRImm ( N -> getOperand ( <NUM_LIT> ) , VT , Cnt ) ) { SDValue RHS = DAG . getNode ( <STR_LIT> , SDLoc ( N -> getOperand ( <NUM_LIT> ) ) , VT , DAG . getConstant ( Cnt , <STR_LIT> ) ) ; return DAG . getNode ( N -> getOpcode ( ) , SDLoc ( N ) , VT , N -> getOperand ( <NUM_LIT> ) , RHS ) ; } break ; } return SDValue


<s> return PerformADDECombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformSUBECombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : return PerformDivRemCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformSELECTCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformANDCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformORCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformADDCombine ( N , DAG , DCI , Subtarget ) ; } return SDValue (


<s> if ( NumRegs > <NUM_LIT> && TableEntry -> copyAllListRegs ) MIB . addReg ( D1 , RegState :: Define | getDeadRegState ( DstIsDead ) ) ; if ( NumRegs > <NUM_LIT> && TableEntry -> copyAllListRegs ) MIB . addReg ( D2 , RegState :: Define | getDeadRegState ( DstIsDead ) ) ; if ( NumRegs > <NUM_LIT> && TableEntry -> copyAllListRegs ) MIB . addReg ( D3 , RegState :: Define | getDeadRegState ( DstIsDead ) ) ; if ( TableEntry -> isUpdating ) MIB . addOperand ( MI . getOperand ( OpIdx ++ ) ) ; MIB . addOperand ( MI . getOperand ( OpIdx ++ ) ) ; MIB . addOperand ( MI . getOperand ( OpIdx ++ ) ) ; if ( TableEntry -> hasWritebackOperand ) MIB . addOperand ( MI . getOperand ( OpIdx ++ ) ) ; unsigned SrcOpIdx = <NUM_LIT> ; if ( RegSpc == EvenDblSpc || RegSpc == OddDblSpc ) SrcOpIdx = OpIdx ++ ; MIB . addOperand ( MI . getOperand ( OpIdx ++ ) ) ; MIB . addOperand ( MI . getOperand ( OpIdx ++ ) ) ; if ( SrcOpIdx != <NUM_LIT> ) { MachineOperand MO = MI . getOperand ( SrcOpIdx ) ; MO . setImplicit ( true ) ; MIB . addOperand ( MO )


<s> if ( insn != BB_END ( bb ) ) distance = distance_agu_use_in_bb ( regno0 , insn , distance , NEXT_INSN ( insn ) , & found , & redefined ) ; if ( ! found && ! redefined && distance < LEA_SEARCH_THRESHOLD ) { edge e ; edge_iterator ei ; bool simple_loop = false ; FOR_EACH_EDGE ( e , ei , bb -> succs ) if ( e -> dest == bb ) { simple_loop = true ; break ; } if ( simple_loop ) distance = distance_agu_use_in_bb ( regno0 , insn , distance , BB_HEAD ( bb ) , & found , & redefined ) ; else { int shortest_dist = - <NUM_LIT> ; bool found_in_bb = false ; bool redefined_in_bb = false ; FOR_EACH_EDGE ( e , ei , bb -> succs ) { int bb_dist = distance_agu_use_in_bb ( regno0 , insn , distance , BB_HEAD

( e -> dest ) , & found_in_bb , & redefined_in_bb ) ;


<s> __attribute__ ( ( __always_inline__ , __gnu_inline__ , __artificial__ ) ) vmlal_n_s16 ( int32x4_t a , int16x4_t b , int16_t c ) { int32x4_t result ; __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT> ( b ) , <STR_LIT> ( c ) : ) ; return


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return Instr -> getOperand ( <NUM_LIT> ) . getReg ( ) != <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : return Instr -> getOperand ( <NUM_LIT> ) . getReg ( ) != <STR_LIT> ; case <STR_LIT> : return Instr -> getOperand ( <NUM_LIT> ) . getReg ( ) != <STR_LIT> && Instr -> getOperand ( <NUM_LIT> ) . getReg ( ) != <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : return Instr -> getOperand ( <NUM_LIT> ) . getReg ( ) != <STR_LIT> && Instr -> getOperand ( <NUM_LIT> ) .


<s> return GV -> getType ( ) -> getAddressSpace ( ) == AMDGPUA<ISA_LIT> . CONSTANT_ADDRESS &&


<s> return LowerFPToInt ( MI , DL , BB , TII , false , false , false , <STR_LIT> ) ; case <STR_LIT> : return LowerFPToInt ( MI , DL , BB , TII , true , false , false , <STR_LIT> ) ; case <STR_LIT> : return LowerFPToInt ( MI , DL , BB , TII , false , true , false , <STR_LIT> ) ; case <STR_LIT> : return LowerFPToInt ( MI , DL , BB , TII , true , true , false , <STR_LIT> ) ; case <STR_LIT> : return LowerFPToInt ( MI , DL , BB , TII , false , false , true , <STR_LIT> ) ; case <STR_LIT> : return LowerFPToInt ( MI , DL , BB , TII , true , false , true , <STR_LIT> ) ; case <STR_LIT> : return LowerFPToInt ( MI , DL , BB , TII , false , true , true , <STR_LIT> ) ; case <STR_LIT> : return LowerFPToInt ( MI , DL , BB , TII , true , true , true , <STR_LIT> ) ; case <STR_LIT>


<s> ( defined ( __ppc__ ) || defined ( __powerpc__ ) ) if ( CPUName == <STR_LIT> ) CPUName = sys :: getHostCPUName ( ) ; InstrItins = getInstrItineraryForCPU ( CPUName ) ; std :: string FullFS = FS ; if ( Is<ISA_LIT>64 ) { Has64BitSupport = true ; Use64BitRegs = true ; if ( ! FullFS . empty ( ) ) FullFS = <STR_LIT> + FullFS ; else FullFS = <STR_LIT> ; } if ( OptLevel >= CodeGenOpt :: Default ) { if ( ! FullFS . empty ( ) ) FullFS = <STR_LIT> + FullFS ; else FullFS = <STR_LIT> ; } ParseSubtargetFeatures ( CPUName , FullFS


<s> if ( V2 . getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> || V2 . getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> || V1 . getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; if ( ! <STR_LIT> ( V2 . getOperand ( <NUM_LIT> ) . getNode ( ) ) ) return SDValue ( ) ; for ( unsigned i = <NUM_LIT> ; i != NumElems / <NUM_LIT> ; ++ i ) if ( ! isUndefOrEqual ( SVOp -> getMaskElt ( i ) , i ) || ! isUndefOrEqual ( SVOp -> getMaskElt ( i + NumElems / <NUM_LIT> ) , NumElems ) ) return SDValue ( ) ; if ( LoadSDNode * Ld = dyn_cast < LoadSDNode > ( V1 . getOperand ( <NUM_LIT> ) ) ) { if ( Ld -> hasNUsesOfValue ( <NUM_LIT>


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<s> static __inline qword si_rotqbi ( qword a , qword count ) { vec_uchar16 x , y ; vec_uchar16 result ; x = vec_and ( vec_splat ( ( vec_uchar16 ) ( count ) , <NUM_LIT> ) , vec_splat_u8 ( <NUM_LIT> ) ) ; y = ( vec_uchar16 ) ( vec_sr ( ( vec_uint4 ) vec_sro ( ( vec_uchar16 ) ( a ) , ( ( vec_uchar16 ) ( ( vec_uint4 ) { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) ) ,

( vec_uint4 ) vec_sub ( vec_splat_u8 ( <NUM_LIT> ) , x ) ) ) ;


<s> static bool pdp11_legitimate_constant_p ( machine_mode mode ATTRIBUTE_UNUSED , rtx x ) { return GET_CODE ( x ) != CONST_DOUBLE || legitimate_const_double_p ( x


<s> aarch64_add_constant_internal ( mode , regnum , scratchreg , delta


<s> case <STR_LIT> : return std :: min ( ST . getMaxNumVGPRs ( Occupancy ) , ST . getMaxNumVGPRs ( MF ) ) ; case <STR_LIT> : return std :: min ( ST . getMaxNumSGPRs ( Occupancy , true ) , ST


<s> LiveNodes . insert ( N ) ; auto RA = DFG . addr < RefNode * > ( N ) ; if ( DFG . IsDef ( RA ) ) processDef ( RA , WorkQ ) ; else processUse ( RA , WorkQ ) ; } if ( trace ( ) ) { dbgs ( ) << <STR_LIT> ; for ( NodeId N : LiveNodes ) { auto RA = DFG . addr < RefNode * > ( N ) ; dbgs ( ) << PrintNode < RefNode * > ( RA , DFG ) << <STR_LIT> ; } } auto IsDead = [ this ] ( NodeAddr < InstrNode * > IA ) -> bool { for ( NodeAddr < DefNode * > DA : IA . Addr -> members_if ( DFG . IsDef , DFG ) ) if ( LiveNodes . count ( DA . Id ) ) return false ; return true ; } ; for ( NodeAddr < BlockNode * > BA : DFG . getFunc ( ) . Addr -> members ( DFG ) ) { for ( NodeAddr < InstrNode * > IA : BA . Addr -> members ( DFG ) ) { for ( NodeAddr < RefNode * > RA : IA . Addr -> members ( DFG ) ) if ( ! LiveNodes . count ( RA . Id ) ) DeadNodes . insert ( RA . Id ) ; if ( DFG . IsCode < NodeAttrs :: Stmt > ( IA ) ) if ( isLiveInstr ( NodeAddr < StmtNode * > ( IA ) . Addr -> getCode ( ) ) ) continue ; if ( IsDead ( IA ) ) { DeadInstrs . insert ( IA . Id ) ; if ( trace ( ) ) dbgs ( ) << <STR_LIT> << PrintNode < InstrNode * > ( IA , DFG ) << <STR_LIT> ; } } } return ! DeadNodes . empty (


<s> else if ( RC == <STR_LIT> ) BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , false , false , isKill ) ; else if ( RC == <STR_LIT> ) BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg (


<s> <ISA_LIT>TargetStreamer & getTargetStreamer ( ) { return static_cast < <ISA_LIT>TargetStreamer & > ( * OutStreamer . getTargetStreamer


<s> } Insn = ( Bytes [ <NUM_LIT> ] << <NUM_LIT> ) | ( Bytes [ <NUM_LIT> ] << <NUM_LIT> ) ; return true


<s> bool <ISA_LIT>AsmPrinter :: ShouldPrintNextBlock ( const MachineBasicBlock & CurMBB ) const { auto Term = CurMBB . terminators ( ) ; if ( Term . begin ( ) == Term . end ( ) || Term . begin ( ) -> getOpcode ( )

== <STR_LIT> || Term . begin ( ) -> getOpcode ( ) == <STR_LIT> ) return true ;


<s> Size = ( Suffix == 'n' ? <NUM_LIT> : <NUM_LIT> ) ; for ( unsigned II = <NUM_LIT> , IE = Size ; II != IE ; II = II + <NUM_LIT> ) { const unsigned I0 = LittleEndian ? II + <NUM_LIT> : II + <NUM_LIT> ; const unsigned I1 = LittleEndian ? II + <NUM_LIT> : II + <NUM_LIT> ; Buffer [ Size - II - <NUM_LIT> ] = uint8_t ( Inst >> I0 * CHAR_BIT ) ; Buffer [ Size - II - <NUM_LIT> ] = uint8_t ( Inst >> I1 * CHAR_BIT ) ; } break ; default : llvm_unreachable (


<s> bool Indirect = gvNeedsNonLazyPtr ( RelocOp -> getGlobal ( ) ) ; emitGlobalAddress ( RelocOp -> getGlobal ( ) , rt , RelocOp -> getOffset ( ) , PCAdj , NeedStub , Indirect ) ; } else if ( RelocOp -> isCPI ( ) ) { unsigned rt = Is64BitMode ? <STR_LIT> : <STR_LIT> ; emitConstPoolAddress ( RelocOp -> getIndex ( ) , rt , RelocOp -> getOffset ( ) , PCAdj ) ; } else if ( RelocOp -> isJTI ( ) ) { unsigned rt = Is64BitMode ? <STR_LIT> : <STR_LIT> ; emitJumpTableAddress ( RelocOp -> getIndex ( ) , rt


<s> unsigned getSGPR32PressureSet ( ) const { return SGPR32SetID


<s> bool <ISA_LIT>DAGToDAGISel :: SelectVOP3PModsDOT ( SDValue In , SDValue & Src , SDValue


<s> auto Pred = static_cast < CmpInst :: Predicate > ( PredNum ) ; switch ( Pred ) { case CmpInst :: ICMP_EQ : return <STR_LIT> ; case CmpInst :: ICMP_NE : return <STR_LIT> ; default : llvm_unreachable ( <STR_LIT>


<s> const Function * Fn = DAG . getMachineFunction ( ) . getFunction ( ) ; const Module * M = Fn -> getParent ( ) ; CalleeFn = M -> getFunction ( E -> getSymbol ( ) ) ; } if ( ! CalleeFn ) return <NUM_LIT> ; assert ( CalleeFn -> hasStructRetAttr ( ) && <STR_LIT> ) ; PointerType * Ty = cast < PointerType > ( CalleeFn -> arg_begin ( ) -> getType ( ) ) ; Type * ElementTy = Ty -> getElementType (


<s> if ( ML -> contains ( Bottom ) && ML -> isLoopLatch ( Bottom ) ) return true ; return false


<s> SMLoc getEndLoc ( ) const override { return


<s> std :: swap ( d -> op0 , d -> op1 ) ; location = d -> perm . length ( ) . to_constant ( ) - location ; } offset = GEN_INT ( location ) ; emit_set_insn ( d -> target , gen_rtx_UNSPEC ( d -> vmode , gen_rtvec ( <NUM_LIT> ,

d -> op0 , d -> op1 , offset ) , UNSPEC_EXT ) ) ;


<s> if ( CmpValue != ExpectedValue ) { if ( ! IsReversable ) return false ; IsReversedCC = CmpValue == ( ExpectedValue ^ Mask ) ; if ( ! IsReversedCC ) return false ; } Register DefReg = Def -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( IsReversedCC && ! MRI -> hasOneNonDBGUse ( DefReg ) ) return false ; for ( auto I = std :: next ( Def -> getIterator ( ) ) , E = CmpInstr . getIterator ( ) ; I != E ; ++ I ) { if ( I -> modifiesRegister ( <STR_LIT> , & RI ) || I -> killsRegister ( <STR_LIT> , & RI ) ) return false ; } MachineOperand * SccDef = Def -> findRegisterDefOperand ( <STR_LIT> ) ; SccDef -> setIsDead ( false ) ; CmpInstr . eraseFromParent ( ) ; if ( ! MRI -> use_nodbg_empty ( DefReg ) ) { assert ( ! IsReversedCC ) ; return true ; } MachineBasicBlock * MBB = Def -> getParent ( ) ; unsigned NewOpc = ( SrcSize == <NUM_LIT> ) ? IsReversedCC ? <STR_LIT> : <STR_LIT> : IsReversedCC ? <STR_LIT> : <STR_LIT> ; BuildMI ( * MBB , Def , Def -> getDebugLoc ( ) , get ( NewOpc ) ) . add ( * SrcOp ) . addImm ( Log2_64 ( Mask ) ) ; Def -> eraseFromParent ( ) ; return true ; } ; switch ( CmpInstr . getOpcode ( ) ) { default : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return optimizeCmpAnd ( <NUM_LIT> , <NUM_LIT> , true , false ) ; case <STR_LIT> : case <STR_LIT> : return optimizeCmpAnd ( <NUM_LIT> , <NUM_LIT> , false , false ) ; case <STR_LIT> : case <STR_LIT> : return optimizeCmpAnd ( <NUM_LIT> , <NUM_LIT> , false , true ) ; case <STR_LIT>


<s> auto const & ST = MIRBuilder . getMF ( ) . getSubtarget < <ISA_LIT>Subtarget > ( ) ; unsigned Opcode = ST . getReturnOpcode ( ) ; auto Ret = MIRBuilder . buildInstrNoInsert ( Opcode ) . add ( predOps ( <STR_LIT> ) ) ; if ( ! lowerReturnVal ( MIRBuilder , Val , VRegs , Ret ) ) return false ; MIRBuilder . insertInstr ( Ret )


<s> return __builtin_aarch64_lroundsfsi (


<s> const TargetMachine & TM = AP . TM ; Mangler * Mang = AP . Mang ; const DataLayout & DL = AP . getDataLayout ( ) ; MCContext & Ctx = AP . OutContext ; SmallString < <NUM_LIT> > Name ; StringRef Suffix ; if ( MO . getTargetFlags ( ) & <STR_LIT> ) Suffix = <STR_LIT> ; if ( ! Suffix . empty ( ) ) Name += DL . getPrivateGlobalPrefix ( ) ; if ( ! MO . isGlobal ( ) ) { assert ( MO . isSymbol ( ) && <STR_LIT> ) ; Mangler :: getNameWithPrefix ( Name , MO . getSymbolName ( ) , DL ) ; } else { const GlobalValue * GV = MO . getGlobal ( ) ; TM . getNameWithPrefix ( Name , GV , * Mang ) ; } Name += Suffix ; MCSymbol * Sym = Ctx . getOrCreateSymbol ( Name ) ; if ( MO . getTargetFlags ( ) & <STR_LIT> ) { MachineModuleInfoMachO & MachO = getMachOMMI ( AP ) ; MachineModuleInfoImpl :: StubValueTy & StubSym = MachO . getGVStubEntry (


<s> if ( auto * C = dyn_cast < ConstantSDNode > ( Y ) ) return C -> getAPIntValue


<s> TargetPassConfig :: addMachineSSAOptimization ( ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None ) addPass ( create<ISA_LIT>MIPeepholeOptPass ( )


<s> if ( rclass == CCREGS ) return mode == BImode ; if ( mode == PDImode || mode == V2PDImode ) return regno == REG_A0 || regno == REG_A1 ; if ( mode == DImode


<s> MFI = funcInfo . MF -> getInfo < <ISA_LIT>FunctionInfo > ( ) ; Context = & funcInfo . Fn -> getContext ( ) ; TargetSupported = ( ( TM . getRelocationModel ( ) == Reloc :: PIC_ ) && ( ( Subtarget -> has<ISA_LIT>32r2 ( ) || Subtarget -> has<ISA_LIT>32 ( ) ) && ( static_cast < const <ISA_LIT>TargetMachine & >


<s> __builtin_aarch64_simd_xi __o ; __o = __builtin_aarch64_ld4di ( ( const __builtin_aarch64_simd_di * ) __a ) ; ret . val [ <NUM_LIT> ] = ( uint64x1_t ) __builtin_aarch64_get_dregxidi ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( uint64x1_t ) __builtin_aarch64_get_dregxidi


<s> static bool real_insn_and_same_bb_p ( const insn_info * insn , const bb_info * bb ) { return insn != nullptr && insn -> is_real ( ) &&


<s> return ( __m512i ) __builtin_ia32_pbroadcastb512_mask ( ( __v16qi ) __A , ( __v64qi ) _mm512_setzero_si512 ( ) ,


<s> if ( HAS_VLINDEX ( MCID . TSFlags ) ) return GET_VLINDEX ( MCID . TSFlags ) ; return -


<s> unsigned Reg = Op . getReg ( ) ; O << getRegisterName ( Reg ) ; } else if ( Op . isImm ( ) ) { printImm ( MI , OpNo , STI , O ) ; } else { assert ( Op . isExpr ( ) && <STR_LIT> ) ; Op . getExpr ( ) -> print ( O


<s> std :: vector < const GlobalVariable * > Items = ExternalVarDefs ; if ( ! Items . size ( ) ) return ; O << <STR_LIT> << MAI -> getCommentString ( ) <<


<s> if ( ! multiple_operation_profitable_p ( false , count , <NUM_LIT> ) ) { rtx seq ; start_sequence ( ) ; for ( i = <NUM_LIT> ; i < count ; i ++ ) emit_move_insn ( gen_rtx_REG ( SImode , regs [ i ] ) , mems [ i ] ) ; if ( wback_offset != <NUM_LIT> ) emit_move_insn ( basereg , plus_constant ( Pmode , basereg , wback_offset ) ) ; seq = get_insns ( ) ; end_sequence ( ) ; return seq ; } result = gen_rtx_PARALLEL ( VOIDmode , rtvec_alloc ( count + ( wback_offset != <NUM_LIT> ?


<s> const char * p = getenv ( <STR_LIT> ) ; val = p && strlen ( p ) ; } return ! val


<s> const TargetRegisterClass * Thumb1RegisterInfo :: getLargestLegalSuperClass ( const TargetRegisterClass * RC ) const { if ( <STR_LIT> . hasSubClassEq ( RC


<s> bool Error ( SMLoc L , const Twine & Msg , ArrayRef < SMRange > Ranges = None ) { return Parser . Error ( L , Msg ,


<s> Register getExceptionSelectorRegister ( const Constant *


<s> while ( ( i != e ) && ( In [ i ] . PartOffset == Offset ) ) { Offset += In [ i ] . VT


<s> bool isNameEqual ( const std :: string & Other , const FeatureBitset & FeatureBits ) const { if ( FeatureBitSet . any ( ) && ( FeatureBitSet & FeatureBits ) . none ( ) ) return false ; return Name ==


<s> unsigned <ISA_LIT>MCCodeEmitter :: getShiftRightImm16 ( const MCInst & MI , unsigned Op , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { return <NUM_LIT> - MI . getOperand ( Op


<s> static bool c6x_print_operand_punct_valid_p ( unsigned char c ) { return c == '$' || c ==


<s> Op -> BTIHint . Val = Val | <NUM_LIT> ; Op -> BTIHint . Data = Str . data ( ) ; Op -> BTIHint . Length = Str . size (


<s> const TargetFrameLowering * getFrameLowering ( ) const override { return &


<s> if ( isa < FrameIndexSDNode > ( Addr ) ) return false ; if ( Addr . getOpcode ( ) == <STR_LIT> || Addr . getOpcode ( ) == <STR_LIT> || Addr . getOpcode ( ) == <STR_LIT> ) return false ; if ( Addr . getOpcode ( ) == <STR_LIT> ) { ; } else if ( Addr . getOpcode ( ) == <STR_LIT> ) { if ( ! CurDAG -> haveNoCommonBitsSet ( Addr . getOperand ( <NUM_LIT> ) , Addr . getOperand ( <NUM_LIT> ) ) ) return false ; } else { return false ; } if ( Addr . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> || Addr . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) return false ; Base = Addr . getOperand ( <NUM_LIT> ) ; Index = Addr . getOperand ( <NUM_LIT>


<s> if ( ( Reg >= <STR_LIT> && Reg <= <STR_LIT> ) || ( Reg >= <STR_LIT> && Reg <= <STR_LIT> ) || ( Reg >= <STR_LIT> && Reg <= <STR_LIT> ) ) DefFP = true ; continue ; } if ( Reg >= <STR_LIT> && Reg <= <STR_LIT> ) { int R = Reg - <STR_LIT> ; ClearRegs . reset ( R * <NUM_LIT> , ( R + <NUM_LIT> ) * <NUM_LIT> ) ; } else if ( Reg >= <STR_LIT> &&


<s> rtx_insn * rinsn ; if ( vector_config_insn_p ( insn -> rtl ( ) ) ) { rinsn = insn -> rtl ( ) ; gcc_assert ( vsetvl_insn_p ( rinsn ) && <STR_LIT> ) ; } else { gcc_assert ( has_vtype_op ( insn -> rtl ( ) ) ) ; rinsn = PREV_INSN ( insn


<s> if ( isProperty ( ) ) return Properties ; assert ( ! isTop ( ) && <STR_LIT> ) ; if ( isBottom ( ) ) return ConstantProperties :: Unknown ; assert ( size ( ) > <NUM_LIT> && <STR_LIT> ) ; uint32_t Ps = ConstantProperties :: deduce ( Values [ <NUM_LIT> ] ) ; for ( unsigned i = <NUM_LIT> ; i < size ( ) ; ++


<s> int64_t Fmt = UFMT_UNDEF ; if ( ! tryParseFmt ( <STR_LIT> , UFMT_MAX , Fmt ) ) return MatchOperand_ParseFail ; if ( Fmt == UFMT_UNDEF ) return


<s> MVT MaskVT ; if ( <NUM_LIT> == BitWidth || <NUM_LIT> == BitWidth ) MaskVT = <STR_LIT> ( <STR_LIT> ( BitWidth ) , MatchSizeInBits / BitWidth ) ; else MaskVT = <STR_LIT> ( <STR_LIT> , MatchSizeInBits / <NUM_LIT> ) ; APInt CompareBits ; <STR_LIT> CondCode ; if ( BinOp == <STR_LIT> ) { CompareBits = APInt :: getNullValue ( <NUM_LIT> ) ; CondCode = <STR_LIT> :: SETNE ; } else { CompareBits = APInt :: getLowBitsSet ( <NUM_LIT> , MaskVT . getVectorNumElements ( ) ) ; CondCode = <STR_LIT> :: SETEQ ; } unsigned ResWidth = std :: max ( BitWidth , <NUM_LIT> ) ; EVT ResVT = EVT :: getIntegerVT ( * DAG . getContext ( ) , ResWidth ) ; SDLoc DL ( Extract ) ; SDValue Zero = DAG . getConstant ( <NUM_LIT> , DL , ResVT ) ; SDValue Ones = DAG . getAllOnesConstant ( DL


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const { AU . addPreserved < MachineFunctionAnalysis > (


<s> EVT LoadedVT = LD -> getMemoryVT ( ) ; int64_t Offset = cast < GlobalAddressSDNode > ( Base ) -> getOffset ( ) ; if ( Offset != <NUM_LIT> && OffsetFitsS11 ( LoadedVT , Offset ) ) { MVT PointerTy = getTargetLowering ( ) -> getPointerTy ( ) ; const GlobalValue * GV = cast < GlobalAddressSDNode > ( Base ) -> getGlobal ( ) ; SDValue TargAddr = CurDAG -> getTargetGlobalAddress ( GV , dl , PointerTy , <NUM_LIT> ) ; SDNode * NewBase = CurDAG -> getMachineNode ( <STR_LIT> , dl , PointerTy , TargAddr ) ; if ( LoadedVT == <STR_LIT> ) Opcode = <STR_LIT> ; else if ( LoadedVT == <STR_LIT> ) Opcode = <STR_LIT> ; else if ( LoadedVT == <STR_LIT> ) Opcode = <STR_LIT> ; else if ( LoadedVT == <STR_LIT> ) Opcode = <STR_LIT> ; else llvm_unreachable ( <STR_LIT> ) ; SDValue TargetConstOff = CurDAG -> getTargetConstant ( Offset , PointerTy ) ; SDNode * Result = CurDAG -> getMachineNode ( Opcode , dl , LD -> getValueType ( <NUM_LIT> ) , <STR_LIT> , SDValue ( NewBase , <NUM_LIT> ) , TargetConstOff , Chain ) ; MachineSDNode :: mmo_iterator MemOp = MF -> allocateMemRefsArray


<s> static bool csky_cannot_force_const_mem ( machine_mode mode ATTRIBUTE_UNUSED ,


<s> static_assert ( <STR_LIT> < <STR_LIT> , <STR_LIT> ) ; if ( RegNo == <STR_LIT> ) RegNo = MatchRegisterAltName ( Name ) ; if ( IsRV32E && RegNo >= <STR_LIT> && RegNo <= <STR_LIT> ) RegNo = <STR_LIT> ; return RegNo ==


<s> return IsISR && ( FI == ISRDataRegFI [ <NUM_LIT> ] ||


<s> for ( unsigned i = <NUM_LIT> , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) { const MachineOperand & MO = MI -> getOperand ( i ) ; MCOperand MCOp ; if ( lowerOperand ( MO , MCOp )


<s> return ; } dstl = gen_reg_rtx ( DImode ) ; dsth = gen_reg_rtx ( DImode ) ; insl = gen_reg_rtx ( DImode ) ; insh = gen_reg_rtx ( DImode ) ; dsta = XEXP ( dst , <NUM_LIT> ) ; if ( GET_CODE ( dsta ) == LO_SUM ) dsta = force_reg ( Pmode , dsta ) ; meml = change_address ( dst , DImode , gen_rtx_AND ( DImode , plus_constant ( DImode , dsta , ofs ) , GEN_INT ( - <NUM_LIT> ) ) ) ; set_mem_alias_set ( meml , <NUM_LIT> ) ; memh = change_address ( dst , DImode , gen_rtx_AND ( DImode , plus_constant ( DImode , dsta , ofs + size - <NUM_LIT> ) , GEN_INT ( - <NUM_LIT> ) ) ) ; set_mem_alias_set ( memh , <NUM_LIT> ) ; emit_move_insn ( dsth , memh ) ; emit_move_insn ( dstl , meml ) ; addr = copy_addr_to_reg ( plus_constant ( Pmode , dsta , ofs ) ) ; if ( src != CONST0_RTX ( GET_MODE ( src ) ) ) { emit_insn ( gen_insxh ( insh , gen_lowpart ( DImode , src ) , GEN_INT ( size * <NUM_LIT> ) , addr ) ) ; switch ( ( int ) size ) { case <NUM_LIT> : emit_insn ( gen_inswl ( insl , gen_lowpart ( HImode , src ) , addr ) ) ; break ; case <NUM_LIT> : emit_insn ( gen_insll ( insl , gen_lowpart ( SImode , src ) , addr ) ) ; break ; case


<s> const uint32_t * <ISA_LIT>RegisterInfo :: getCallPreservedMask ( const MachineFunction & MF , CallingConv :: ID Id ) const { const <ISA_LIT>Subtarget & STI = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( STI . hasFPUv2DoubleFloat ( ) || STI . hasFPUv3DoubleFloat ( ) )


<s> case <STR_LIT> : * AddrIdx = <NUM_LIT> ; break ; case <STR_LIT> : * AddrIdx = <NUM_LIT> ; break ; } switch ( MI . getOperand ( * AddrIdx ) . getReg ( ) ) { default : break ; case <STR_LIT> : case


<s> bool isMemSrc10 ( ) const { if ( Kind != MemSrc || Mem . WithPreDec || Mem . WithPostInc ) { return


<s> for ( DenseMap < MachineBasicBlock * , unsigned int > :: iterator I = ReturnBBs . begin ( ) ; I != ReturnBBs . end ( ) ; ++ I ) { MBB = I -> first ; Cycles = I -> second ; if ( Cycles < Threshold ) { assert ( MBB -> size ( ) > <NUM_LIT> && <STR_LIT> ) ; MachineBasicBlock :: iterator ReturnLoc = -- MBB -> end ( ) ; while ( ReturnLoc -> isDebugValue ( ) ) -- ReturnLoc ; assert ( ReturnLoc -> isReturn ( ) && ! ReturnLoc -> isCall ( ) && <STR_LIT> ) ; addPadding ( MBB , ReturnLoc


<s> fprintf ( stderr , <STR_LIT> , subtree -> str ) ; rbt_dump ( t , subtree ->


<s> u . v = a ; u . i [ pos ] = b ; return u .


<s> unsigned getMemOp ( ) const { assert ( isMem ( ) && <STR_LIT> ) ; return Mem .


<s> printAddress ( & MAI , MI -> getOperand ( OpNum ) . getReg ( ) , MI -> getOperand ( OpNum + <NUM_LIT> ) , MI -> getOperand ( OpNum + <NUM_LIT>


<s> InstructionCost <ISA_LIT>TTIImpl :: getExtendedAddReductionCost ( bool IsMLA , bool IsUnsigned , Type * ResTy , VectorType * ValTy , TTI :: TargetCostKind CostKind ) { EVT ValVT = TLI -> getValueType ( DL , ValTy ) ; EVT ResVT = TLI -> getValueType ( DL , ResTy ) ; if ( ST -> hasMVEIntegerOps ( ) && ValVT .

isSimple ( ) && ResVT . isSimple ( ) ) {


<s> return getInvalidInstructionMapping ( ) ; default : break ; } unsigned NumOperands = MI . getNumOperands ( ) ; SmallVector < unsigned , <NUM_LIT> > OpSize ( NumOperands ) ; SmallVector < PartialMappingIdx , <NUM_LIT> > OpRegBankIdx ( NumOperands ) ; for ( unsigned Idx = <NUM_LIT> ; Idx < NumOperands ; ++ Idx ) { auto & MO = MI . getOperand ( Idx ) ; if ( ! MO . isReg ( ) || ! MO . getReg ( ) ) continue ; LLT Ty = MRI . getType ( MO . getReg ( ) ) ; OpSize [ Idx ] = Ty . getSizeInBits ( ) ; if ( Ty . isVector ( ) || isPreISelGenericFloatingPointOpcode ( Opc ) ) OpRegBankIdx [ Idx ] = PMI_FirstFPR ; else OpRegBankIdx [ Idx ] = PMI_FirstGPR ; } unsigned Cost = <NUM_LIT> ; switch ( Opc ) { case TargetOpcode :: G_SITOFP : case TargetOpcode :: G_UITOFP : OpRegBankIdx = { PMI_FirstFPR , PMI_FirstGPR } ; break ; case TargetOpcode :: G_FPTOSI : case TargetOpcode :: G_FPTOUI : OpRegBankIdx = { PMI_FirstGPR , PMI_FirstFPR } ; break ; case TargetOpcode :: G_FCMP : OpRegBankIdx = { PMI_FirstGPR , PMI_None , PMI_FirstFPR , PMI_FirstFPR } ; break ; case TargetOpcode :: G_BITCAST : if ( OpRegBankIdx [ <NUM_LIT> ] != OpRegBankIdx [ <NUM_LIT> ] ) Cost = copyCost ( * <ISA_LIT>GenRegisterBankInfo :: PartMappings [ OpRegBankIdx [ <NUM_LIT> ] ] . RegBank , * <ISA_LIT>GenRegisterBankInfo :: PartMappings [ OpRegBankIdx [ <NUM_LIT> ] ] . RegBank , OpSize [ <NUM_LIT> ] ) ; break ; case TargetOpcode :: G_LOAD : if ( OpRegBankIdx [ <NUM_LIT> ] != PMI_FirstGPR ) Cost = <NUM_LIT> ; else for ( const MachineInstr & UseMI : MRI . use_instructions ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ) if ( isPreISelGenericFloatingPointOpcode


<s> <ISA_LIT>TargetMachine & get<ISA_LIT>TargetMachine ( ) const { return getTM < <ISA_LIT>TargetMachine >


<s> auto DL = MF . getDataLayout ( ) ; auto & TLI = * getTLI < <ISA_LIT>TargetLowering > ( ) ; if ( ! isSupportedType ( DL , TLI , Val -> getType ( ) ) ) return false ; SmallVector < ArgInfo , <NUM_LIT> > SplitVTs ; ArgInfo RetInfo ( VReg , Val ->


<s> MVT IntSVT = <STR_LIT> ( IntBits ) ; MVT IntVT = <STR_LIT> ( IntSVT , VT . getSizeInBits ( ) / IntBits ) ; SDValue Op0 = DAG . getBitcast ( IntVT , N -> getOperand ( <NUM_LIT> ) ) ; SDValue Op1 = DAG . getBitcast ( IntVT , N -> getOperand ( <NUM_LIT> ) ) ; unsigned IntOpcode ; switch ( N -> getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : IntOpcode


<s> FunctionPass * llvm :: create<ISA_LIT>PrepareForLiveIntervals (


<s> LowerFormalArguments ( SDValue Chain , CallingConv :: ID CallConv , bool isVarArg , const SmallVectorImpl < <STR_LIT> > & Ins , DebugLoc dl , SelectionDAG & DAG , SmallVectorImpl < SDValue > &


<s> return isNarrowLoad ( Opc ) || isNarrowStore


<s> addDefaultPred ( BuildMI ( MBB , MI , dl , get (


<s> if ( unsorted_regs [ i ] < <NUM_LIT> || ( TARGET_THUMB1 && unsorted_regs [ i ] > LAST_LO_REGNUM ) || unsorted_regs [ i ] > <NUM_LIT> || ( i != nops - <NUM_LIT> && unsorted_regs [ i ] == base_reg ) ) return <NUM_LIT> ; if ( unsorted_regs [ i ] == SP_REGNUM && base_reg != SP_REGNUM ) return <NUM_LIT> ; unsorted_offsets [ i ] = INTVAL ( offset ) ; if ( i == <NUM_LIT> || unsorted_offsets [ i ] < unsorted_offsets [ order [ <NUM_LIT> ] ] ) order [ <NUM_LIT> ] = i ; } else return <NUM_LIT> ; } if ( ! compute_offset_order ( nops , unsorted_offsets , order , check_regs ? unsorted_regs : NULL ) ) return <NUM_LIT> ; if ( saved_order ) memcpy ( saved_order , order , sizeof order ) ; if ( base ) { * base = base_reg ; for ( i = <NUM_LIT> ; i < nops ; i ++ ) regs [ i ] = unsorted_regs [ check_regs ? order [ i ] : i ] ; * load_offset = unsorted_offsets [ order [ <NUM_LIT> ] ] ; } if ( TARGET_THUMB1 && ! peep2_reg_dead_p ( nops , base_reg_rtx ) ) return <NUM_LIT> ; if ( unsorted_offsets [ order [ <NUM_LIT> ] ] == <NUM_LIT> ) ldm_case = <NUM_LIT> ; else if ( TARGET_ARM && unsorted_offsets [ order [ <NUM_LIT> ] ] == <NUM_LIT> ) ldm_case = <NUM_LIT> ; else if ( TARGET_ARM && unsorted_offsets [ order [ nops - <NUM_LIT> ] ] == <NUM_LIT> ) ldm_case = <NUM_LIT> ; else if ( TARGET_32BIT && unsorted_offsets [ order [ nops - <NUM_LIT> ] ] == - <NUM_LIT> ) ldm_case = <NUM_LIT> ; else if ( const_ok_for_arm ( unsorted_offsets [ order [ <NUM_LIT> ] ] ) || const_ok_for_arm ( - unsorted_offsets [ order [ <NUM_LIT> ] ] ) ) ldm_case = <NUM_LIT> ; else return <NUM_LIT> ; if ( ! multiple_operation_profitable_p ( false , nops , ldm_case == <NUM_LIT> ? unsorted_offsets [ order [ <NUM_LIT> ] ]


<s> { <STR_LIT> , rs6000_d_handle_target_float_abi } , { <STR_LIT> , rs6000_d_handle_target_object_format } ,


<s> OP ( <NUM_LIT> ) = transcode_memory_rtx ( OP ( <NUM_LIT> ) , HL , insn ) ; MAYBE_OK ( insn ) ; if ( recog_data . constraints [ <NUM_LIT> ] [ <NUM_LIT> ] == '%' && is_virtual_register ( OP ( <NUM_LIT> ) ) && ! is_virtual_register ( OP ( <NUM_LIT> ) ) && ! CONSTANT_P ( OP ( <NUM_LIT> ) ) ) { rtx tmp = OP ( <NUM_LIT> ) ; OP ( <NUM_LIT> ) = OP ( <NUM_LIT> ) ; OP ( <NUM_LIT> ) = tmp ; } OP ( <NUM_LIT> ) = move_from_acc ( <NUM_LIT> , insn ) ; tmp_id = get_max_insn_count ( ) ; saved_op1 = OP ( <NUM_LIT> ) ; if ( rtx_equal_p ( OP ( <NUM_LIT> ) , OP ( <NUM_LIT> ) ) ) { gcc_assert ( GET_MODE ( OP ( <NUM_LIT> ) ) == QImode ) ; OP ( <NUM_LIT> ) = move_to_x ( <NUM_LIT> , insn ) ; OP ( <NUM_LIT> ) = A ; } else OP ( <NUM_LIT> ) = move_to_acc ( <NUM_LIT> , insn ) ; MAYBE_OK ( insn ) ; if ( tmp_id == get_max_insn_count ( ) ) force_into_acc ( saved_op1 , insn ) ; if ( prev ) first = next_nonnote_nondebug_insn ( prev ) ; else for ( first = insn ; prev_nonnote_nondebug_insn ( first ) ; first = prev_nonnote_nondebug_insn ( first ) ) ; OP ( <NUM_LIT> ) = move_to_x ( <NUM_LIT> , first


<s> if ( Negated ) Value *= - <NUM_LIT> ; switch ( Kind ) { case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_LO8 : break ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_HI8 : Value >>= <NUM_LIT> ; break ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_HH8 : Value >>= <NUM_LIT> ; break ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_HHI8 : Value >>= <NUM_LIT> ; break ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_PM_LO8


<s> for ( auto I = MBB . rbegin ( ) ; I != MBB . rend ( ) ; ++ I ) { MachineInstr * NewMI = nullptr ; MachineInstr * MI = & * I ; switch ( MI -> getOpcode ( ) ) { case <STR_LIT> : if ( MachineLoop * ML = MLI -> getLoopFor ( & MBB ) ) { if ( ML -> begin ( ) == ML -> end ( ) && ! OptForSize ) NewMI = tryReplaceLoad ( <STR_LIT> , MI ) ; } break ; case <STR_LIT> : NewMI = tryReplaceLoad ( <STR_LIT> , MI ) ; break ; case <STR_LIT> : case <STR_LIT> : NewMI = tryReplaceCopy


<s> if ( fcode == RS6000_BUILTIN_CPU_IS ) { const char * cpu = TREE_STRING_POINTER ( arg ) ; rtx cpuid = NULL_RTX ; for ( size_t i = <NUM_LIT> ; i < ARRAY_SIZE ( cpu_is_info ) ; i ++ ) if ( strcmp ( cpu , cpu_is_info [ i ] . cpu ) == <NUM_LIT> ) { cpuid = GEN_INT ( cpu_is_info [ i ] . cpuid + _DL_FIRST_PLATFORM ) ; break ; } if ( cpuid == NULL_RTX ) { error ( <STR_LIT> , cpu , rs6000_builtin_info [ ( size_t ) fcode ] . name ) ; return const0_rtx ; } rtx platform = gen_reg_rtx ( SImode ) ; rtx tcbmem = gen_const_mem ( SImode , gen_rtx_PLUS ( Pmode , gen_rtx_REG ( Pmode , TLS_REGNUM ) , GEN_INT ( TCB_PLATFORM_OFFSET ) ) ) ; emit_move_insn ( platform , tcbmem ) ; emit_insn ( gen_eqsi3 ( target , platform , cpuid ) ) ; } else if ( fcode == RS6000_BUILTIN_CPU_SUPPORTS ) { const char * hwcap = TREE_STRING_POINTER ( arg ) ; rtx mask = NULL_RTX ; int hwcap_offset ; for ( size_t i = <NUM_LIT> ; i < ARRAY_SIZE ( cpu_supports_info ) ; i ++ ) if ( strcmp ( hwcap , cpu_supports_info [ i ] . hwcap ) == <NUM_LIT> ) { mask = GEN_INT ( cpu_supports_info [ i ] . mask ) ; hwcap_offset = TCB_HWCAP_OFFSET ( cpu_supports_info [ i ] . id ) ; break ; } if ( mask == NULL_RTX ) { error ( <STR_LIT> , hwcap , rs6000_builtin_info [ ( size_t ) fcode ] . name ) ; return const0_rtx ; } rtx tcb_hwcap = gen_reg_rtx ( SImode ) ; rtx tcbmem = gen_const_mem ( SImode , gen_rtx_PLUS ( Pmode , gen_rtx_REG ( Pmode , TLS_REGNUM ) , GEN_INT ( hwcap_offset ) ) ) ; emit_move_insn ( tcb_hwcap , tcbmem ) ; rtx scratch1 = gen_reg_rtx ( SImode ) ; emit_insn ( gen_rtx_SET ( scratch1 , gen_rtx_AND ( SImode , tcb_hwcap , mask ) ) ) ; rtx scratch2 = gen_reg_rtx ( SImode )


<s> int getFramePointerRegister ( ) override final { return <STR_LIT>


<s> MemOp [ <NUM_LIT> ] = cast < MemIntrinsicSDNode > ( N ) -> getMemOperand ( ) ; SDValue Chain = N -> getOperand ( <NUM_LIT> ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; unsigned Alignment = <NUM_LIT> ; if ( NumVecs != <NUM_LIT> ) { Alignment = cast < ConstantSDNode > ( Align ) -> getZExtValue ( ) ; unsigned NumBytes = NumVecs * VT . getVectorElementType ( ) . getSizeInBits ( ) / <NUM_LIT> ; if ( Alignment > NumBytes ) Alignment = NumBytes ; if ( Alignment < <NUM_LIT> && Alignment < NumBytes ) Alignment = <NUM_LIT> ; Alignment = ( Alignment & - Alignment ) ; if ( Alignment == <NUM_LIT> ) Alignment = <NUM_LIT> ; } Align = CurDAG -> getTargetConstant ( Alignment , <STR_LIT> ) ; unsigned OpcodeIndex ; switch ( VT . getSimpleVT ( ) . SimpleTy ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; } SDValue Pred = getAL ( CurDAG ) ; SDValue Reg0 = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; SDValue SuperReg ; unsigned Opc = Opcodes [ OpcodeIndex ] ; SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . push_back ( MemAddr ) ; Ops . push_back ( Align ) ; if ( isUpdating ) { SDValue Inc = N ->


<s> return thumb1_base_register_rtx_p ( x , QImode


<s> bool requiresRealignment = ( ( MFI -> getMaxAlignment ( ) > StackAlign ) || F -> getFnAttributes ( ) . hasStackAlignmentAttr ( ) ) ; if ( ForceStackAlign ) return canRealignStack ( MF ) ; return requiresRealignment && canRealignStack (


<s> Value * <ISA_LIT>IREmitter :: visitUMAX ( const


<s> MachineFunction * MF = BB -> getParent ( ) ; MachineRegisterInfo & RegInfo = MF -> getRegInfo ( ) ; const TargetRegisterClass * RC = getRegClassFor ( <STR_LIT> ) ; const TargetInstrInfo * TII = Subtarget . getInstrInfo ( ) ; DebugLoc DL = MI . getDebugLoc ( ) ; unsigned Dest = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Ptr = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned CmpVal = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned NewVal = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned AlignedAddr = RegInfo . createVirtualRegister ( RC ) ; unsigned ShiftAmt = RegInfo . createVirtualRegister ( RC ) ; unsigned Mask = RegInfo . createVirtualRegister ( RC ) ; unsigned Mask2 = RegInfo . createVirtualRegister ( RC ) ; unsigned Mask3 = RegInfo . createVirtualRegister ( RC ) ; unsigned ShiftedCmpVal = RegInfo . createVirtualRegister ( RC ) ; unsigned OldVal = RegInfo . createVirtualRegister ( RC ) ; unsigned MaskedOldVal0 = RegInfo . createVirtualRegister ( RC ) ; unsigned ShiftedNewVal = RegInfo . createVirtualRegister ( RC ) ; unsigned MaskLSB2 = RegInfo . createVirtualRegister ( RC ) ; unsigned PtrLSB2 = RegInfo . createVirtualRegister ( RC ) ; unsigned MaskUpper = RegInfo . createVirtualRegister ( RC ) ; unsigned MaskedCmpVal = RegInfo . createVirtualRegister ( RC ) ; unsigned MaskedNewVal = RegInfo . createVirtualRegister ( RC ) ; unsigned MaskedOldVal1 = RegInfo . createVirtualRegister ( RC ) ; unsigned StoreVal = RegInfo . createVirtualRegister ( RC ) ; unsigned SrlRes = RegInfo . createVirtualRegister ( RC ) ; unsigned Success = RegInfo . createVirtualRegister ( RC ) ; const BasicBlock * LLVM_BB = BB -> getBasicBlock ( ) ; MachineBasicBlock * loop1MBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * loop2MBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * sinkMBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * exitMBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineFunction :: iterator It = ++ BB -> getIterator ( ) ; MF -> insert ( It , loop1MBB ) ; MF -> insert ( It , loop2MBB ) ; MF -> insert ( It , sinkMBB ) ; MF -> insert ( It , exitMBB ) ; exitMBB -> splice ( exitMBB -> begin ( ) , BB , std :: next ( MachineBasicBlock :: iterator ( MI ) ) , BB -> end ( ) ) ; exitMBB -> transferSuccessorsAndUpdatePHIs ( BB ) ; BB -> addSuccessor ( loop1MBB ) ; loop1MBB -> addSuccessor ( sinkMBB ) ; loop1MBB -> addSuccessor ( loop2MBB


<s> case <NUM_LIT> : type = TYPE_MOFFS64 ; break ; } } switch ( type ) { case TYPE_MOFFS8 : case TYPE_REL8 : if ( immediate & <NUM_LIT> ) immediate |= ~ ( <NUM_LIT> ) ; break ; case TYPE_MOFFS16 : if ( immediate & <NUM_LIT> ) immediate |= ~ ( <NUM_LIT> ) ; break ; case


<s> bool <ISA_LIT>RegisterInfo :: needsStackRealignment ( const MachineFunction & MF ) const { const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const Function * F = MF . getFunction ( ) ; unsigned StackAlign = TM . getFrameLowering ( ) -> getStackAlignment ( ) ; bool requiresRealignment = ( ( MFI -> getMaxAlignment ( ) > StackAlign ) || F ->

hasFnAttr ( Attribute :: StackAlignment ) ) ;


<s> emit_insn ( gen_movsi_internal ( gen_rtx_SUBREG ( SImode , tmp , <NUM_LIT> ) , gen_raw_REG ( SImode , A7_REG ) ) ) ; break ; case SFmode : emit_insn ( gen_movsf_internal ( tmp , gen_raw_REG ( mode , A7_REG ) ) ) ; break ; case SImode : emit_insn ( gen_movsi_internal ( tmp , gen_raw_REG ( mode , A7_REG ) ) ) ; break ; case HImode : emit_insn ( gen_movhi_internal ( tmp , gen_raw_REG ( mode , A7_REG ) ) ) ; break ; case QImode : emit_insn ( gen_movqi_internal ( tmp , gen_raw_REG ( mode , A7_REG ) ) ) ; break ; default : gcc_unreachable ( ) ; } cfun -> machine -> set_frame_ptr_insn = emit_insn ( gen_set_frame_ptr ( ) ) ; if ( mode == DFmode || mode == DImode ) emit_insn ( gen_movsi_internal ( gen_rtx_SUBREG ( SImode , tmp , <NUM_LIT> ) , gen_rtx_REG ( SImode , A7_REG - <NUM_LIT> ) ) ) ; entry_insns = get_insns ( ) ; end_sequence ( ) ; if ( cfun -> machine -> vararg_a7 ) { cfun -> machine -> vararg_a7_copy = entry_insns ; } else { push_topmost_sequence (


<s> bool rs6000_builtin_is_supported_p ( enum rs6000_builtins fncode ) { HOST_WIDE_INT fnmask = rs6000_builtin_info [ fncode ] . mask ; if ( ( fnmask & rs6000_builtin_mask ) != fnmask ) return false ; else return true


<s> return getTM < <ISA_LIT>TargetMachine >


<s> } } switch ( GET_CODE ( op ) ) { case REG : if ( letter == <NUM_LIT> || letter == 'z' || letter == 'y' ) { fprintf ( file , <STR_LIT> , reg_names [ REGNO ( op ) ] ) ; return ; } else if ( letter == 'D' ) { fprintf ( file , <STR_LIT> , reg_names [ REGNO ( op ) + <NUM_LIT> ] ) ; return ; } break ; case CONST_INT : { rtx int_rtx = op ; HOST_WIDE_INT val = INTVAL ( int_rtx ) ; HOST_WIDE_INT low = val & <NUM_LIT> ; HOST_WIDE_INT high = ( val >> <NUM_LIT> ) & <NUM_LIT> ; if ( letter == 'y' ) { if ( val == <NUM_LIT> ) fprintf ( file , <STR_LIT> ) ; else { if ( high != <NUM_LIT> ) { if ( low != <NUM_LIT> ) { gcc_assert ( TARGET_ARCH_R2 ) ; if ( high == <NUM_LIT> ) int_rtx = gen_int_mode ( low , SImode ) ; else if ( low == <NUM_LIT> ) int_rtx = gen_int_mode ( high , SImode ) ; else gcc_unreachable ( ) ; } else int_rtx = gen_int_mode ( high , SImode ) ; } else int_rtx = gen_int_mode ( low , SImode ) ; output_addr_const ( file , int_rtx ) ; } return ; } else if ( letter == 'z' ) { if ( val == <NUM_LIT> ) fprintf ( file , <STR_LIT> ) ; else { if ( low == <NUM_LIT> && high != <NUM_LIT> ) int_rtx = gen_int_mode ( high , SImode ) ; else if ( low != <NUM_LIT> ) { gcc_assert ( high == <NUM_LIT> || high == <NUM_LIT> ) ; int_rtx = gen_int_mode ( low , high == <NUM_LIT> ? SImode : HImode ) ; } else gcc_unreachable ( ) ; output_addr_const ( file , int_rtx ) ; } return ; } } case CONST : case LABEL_REF : case SYMBOL_REF : case CONST_DOUBLE : if ( letter == <NUM_LIT> || letter == 'z' ) { output_addr_const ( file , op ) ; return ; } else if ( letter == 'H' || letter == 'L' ) { fprintf ( file , <STR_LIT> ) ; if ( GET_CODE ( op ) == CONST && GET_CODE ( XEXP ( op , <NUM_LIT> ) ) == UNSPEC ) { rtx unspec = XEXP ( op , <NUM_LIT> ) ; int unspec_reloc = XINT ( unspec , <NUM_LIT> ) ; gcc_assert ( nios2_large_offset_p ( unspec_reloc ) ) ; fprintf ( file , <STR_LIT> , nios2_unspec_reloc_name ( unspec_reloc ) ) ; op = XVECEXP ( unspec , <NUM_LIT> , <NUM_LIT> ) ; } fprintf ( file , letter == 'H' ? <STR_LIT> : <STR_LIT> ) ; output_addr_const ( file , op ) ; fprintf ( file , <STR_LIT>


<s> assert ( VT == <STR_LIT> || VT == <STR_LIT> ) ; unsigned Opc = ( VT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; SDValue Ops [ <NUM_LIT> ] ; SelectVOP3Mods0 ( N -> getOperand ( <NUM_LIT> ) , Ops [ <NUM_LIT> ] , Ops [ <NUM_LIT> ] , Ops [ <NUM_LIT> ]


<s> SDValue Mask = DAG . getConstantFP ( APFloat ( Sem , MaskElt ) , dl , LogicVT ) ; SDValue Op0 = Op . getOperand ( <NUM_LIT> ) ; bool IsFNABS = ! IsFABS && ( Op0 . getOpcode ( ) == <STR_LIT> ) ; unsigned LogicOp = IsFABS ? <STR_LIT> : IsFNABS ? <STR_LIT> : <STR_LIT> ; SDValue Operand = IsFNABS ? Op0 . getOperand ( <NUM_LIT> ) : Op0 ; if ( VT . isVector ( ) || IsF128 ) return DAG . getNode ( LogicOp , dl , LogicVT , Operand , Mask ) ; Operand = DAG . getNode ( <STR_LIT> , dl , LogicVT , Operand ) ; SDValue LogicNode = DAG . getNode ( LogicOp , dl , LogicVT , Operand , Mask ) ; return DAG . getNode ( <STR_LIT> , dl , VT , LogicNode ,

DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ;


<s> case FK_Data_2 : return ELF :: R_<ISA_LIT>ARC_DI<ISA_LIT>16 ; case FK_Data_4 : return ELF :: R_<ISA_LIT>ARC_DI<ISA_LIT>32 ; case FK_Data_8 : return ELF :: R_<ISA_LIT>ARC_DI<ISA_LIT>64 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>ARC_WDI<ISA_LIT>30 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>ARC_WDI<ISA_LIT>22 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>ARC_WDI<ISA_LIT>19 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>ARC_PC22 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>ARC_PC10 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>ARC_WPLT30 ; } } switch ( ( unsigned ) Fixup . getKind ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case FK_Data_1 : return ELF :: R_<ISA_LIT>ARC_8 ; case FK_Data_2 : return ( ( Fixup . getOffset ( ) % <NUM_LIT> ) ? ELF :: R_<ISA_LIT>ARC_UA16 : ELF :: R_<ISA_LIT>ARC_16 ) ; case FK_Data_4 : return ( ( Fixup . getOffset ( ) % <NUM_LIT> ) ? ELF :: R_<ISA_LIT>ARC_UA32 : ELF :: R_<ISA_LIT>ARC_32 ) ; case FK_Data_8 : return ( ( Fixup . getOffset ( ) % <NUM_LIT> ) ? ELF :: R_<ISA_LIT>ARC_UA64 : ELF :: R_<ISA_LIT>ARC_64 ) ; case <STR_LIT> : return ELF :: R_<ISA_LIT>ARC_HI22 ; case <STR_LIT> : return


<s> std :: vector < std :: string > modr ( Rn a , StepZIDS as ) { return D ( <STR_LIT> , MemR ( a , as )


<s> int getTCReturnAddrDelta ( ) const { return


<s> unsigned DPDenormModeDefault = Mode . FP64FP16Denormals ? FP_DENORM_FLUSH_NONE : FP_DENORM_FLUSH_IN_FLUSH_OUT ; unsigned NewDenormModeValue = SPDenormMode | ( DPDenormModeDefault << <NUM_LIT> ) ; B . buildInstr ( <STR_LIT> ) . addImm ( NewDenormModeValue ) ; } else { unsigned SPDenormModeBitField = <STR_LIT> :: ID_MODE | ( <NUM_LIT> << <STR_LIT> ::


<s> assert ( isa < StructType > ( SrcTy ) && <STR_LIT> ) ; const DataLayout & DL = Func -> getParent ( ) -> getDataLayout ( ) ; const StructLayout * SL = DL . getStructLayout ( cast


<s> auto LoopMBB = MF -> CreateMachineBasicBlock ( MBB . getBasicBlock ( ) ) ; auto DoneMBB = MF -> CreateMachineBasicBlock ( MBB . getBasicBlock ( ) ) ; MF -> insert ( ++ MBB . getIterator ( ) , LoopMBB ) ; MF -> insert ( ++ LoopMBB -> getIterator ( ) , DoneMBB ) ; LoopMBB -> addSuccessor ( LoopMBB ) ; LoopMBB -> addSuccessor ( DoneMBB ) ; DoneMBB -> splice ( DoneMBB -> end ( ) , & MBB , MI , MBB . end ( ) ) ; DoneMBB -> transferSuccessorsAndUpdatePHIs ( & MBB ) ; MBB . addSuccessor ( LoopMBB ) ; Register R = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( LoopMBB , DL , TII -> get ( <STR_LIT> ) , R ) . addImm ( streamer ) ; Register Rs = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( LoopMBB , DL , TII -> get ( <STR_LIT> ) , Rs ) . addReg ( R , RegState :: Kill ) . addImm ( <NUM_LIT> ) ; BuildMI ( LoopMBB , DL , TII -> get ( <STR_LIT> ) ) . addReg ( Rs , RegState :: Kill ) . addReg ( <STR_LIT> ) . addMBB ( LoopMBB ) ; NextMBBI = MBB . end ( ) ; MI . eraseFromParent ( ) ; LivePhysRegs


<s> case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> :


<s> auto <STR_LIT> ( const Type * Ty ) const -> int { return DL . getTypeStoreSize ( const_cast < Type *


<s> return match ( SplatValue , m_FPOne ( ) ) || match ( SplatValue , m_One ( ) ) ; } ; auto IsUnitDup = [ ] ( auto * I ) { auto * IntrI = dyn_cast < IntrinsicInst > ( I ) ; if ( ! IntrI || IntrI -> getIntrinsicID ( ) != <STR_LIT> ) return false ; auto * SplatValue = IntrI -> getOperand ( <NUM_LIT> ) ; return match ( SplatValue , m_FPOne ( ) ) || match ( SplatValue , m_One ( ) ) ; } ; if ( IsUnitDup ( OpMultiplicand ) || IsUnitSplat ( OpMultiplicand ) ) std :: swap ( OpMultiplier , OpMultiplicand ) ; if ( IsUnitSplat ( OpMultiplier ) ) { OpMultiplicand -> takeName ( & II ) ; return IC . replaceInstUsesWith ( II , OpMultiplicand ) ; } else if ( IsUnitDup ( OpMultiplier ) ) { auto * DupInst = cast < IntrinsicInst > ( OpMultiplier ) ; auto * DupPg = DupInst -> getOperand ( <NUM_LIT> ) ; if ( OpPredicate == DupPg ) { OpMultiplicand -> takeName ( & II ) ; return IC . replaceInstUsesWith ( II , OpMultiplicand ) ; } } return None


<s> unsigned val = MI -> getOperand ( OpNum ) . getImm ( ) ; O << <STR_LIT> ( val )


<s> MCFixupKind Kind = MCFixupKind ( FIXUP ) ; if ( MO . getExpr ( ) -> getKind ( ) == MCExpr :: Target ) Kind = getTargetFixup ( MO . getExpr ( ) ) ; Fixups . push_back ( MCFixup :: create ( <NUM_LIT> , MO . getExpr ( ) , Kind ,


<s> switch ( Alignment ) { case <NUM_LIT> : LdOpc = <STR_LIT> ; StOpc = <STR_LIT> ; break ; case <NUM_LIT> : LdOpc = <STR_LIT> ; StOpc = <STR_LIT> ; break ; case <NUM_LIT> : LdOpc = <STR_LIT> ; StOpc = <STR_LIT> ; break ; case <NUM_LIT> : LdOpc = <STR_LIT> ; StOpc = <STR_LIT> ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } unsigned IterationNum = CopyLen >> Log2_64 ( Alignment ) ; for ( unsigned I = <NUM_LIT> ; I < IterationNum ; ++ I ) { BuildMI ( * BB , MI , dl , get ( LdOpc ) ) . addReg ( ScratchReg , RegState :: Define ) . addReg ( SrcReg ) . addImm ( I * Alignment ) ; BuildMI ( * BB , MI , dl , get ( StOpc ) ) . addReg ( ScratchReg , RegState :: Kill ) . addReg ( DstReg ) . addImm ( I * Alignment ) ; } unsigned BytesLeft = CopyLen & ( Alignment - <NUM_LIT> ) ; unsigned Offset = IterationNum * Alignment ; bool Hanging4Byte = BytesLeft & <NUM_LIT> ; bool Hanging2Byte = BytesLeft & <NUM_LIT> ; bool Hanging1Byte = BytesLeft & <NUM_LIT> ; if ( Hanging4Byte ) { BuildMI ( * BB , MI , dl , get ( <STR_LIT> ) ) . addReg ( ScratchReg , RegState :: Define ) . addReg ( SrcReg ) . addImm ( Offset ) ; BuildMI ( * BB , MI , dl , get ( <STR_LIT> ) ) . addReg ( ScratchReg , RegState :: Kill ) . addReg ( DstReg ) . addImm ( Offset ) ; Offset += <NUM_LIT> ; } if ( Hanging2Byte ) { BuildMI ( * BB , MI , dl , get ( <STR_LIT> ) ) . addReg ( ScratchReg , RegState :: Define ) . addReg ( SrcReg ) . addImm ( Offset ) ; BuildMI ( * BB , MI , dl , get ( <STR_LIT> ) ) . addReg ( ScratchReg , RegState :: Kill ) . addReg ( DstReg ) . addImm ( Offset ) ; Offset += <NUM_LIT> ; } if ( Hanging1Byte ) { BuildMI ( * BB , MI , dl , get ( <STR_LIT> ) ) . addReg ( ScratchReg , RegState :: Define ) . addReg ( SrcReg ) . addImm ( Offset ) ; BuildMI ( * BB , MI , dl , get ( <STR_LIT> ) ) . addReg ( ScratchReg , RegState :: Kill ) . addReg ( DstReg ) .


DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , PSHUFBMask ) ) ) ;


<s> bool haveFeatures ( FeatureBitset ActiveFeatures ) const { return ( FeaturesRequired & ActiveFeatures ) ==


<s> if ( NewLLT . getNumElements ( ) > OldLLT . getNumElements ( ) ) { if ( NewLLT . getNumElements ( ) != OldLLT . getNumElements ( ) * <NUM_LIT> ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } auto Undef = MIRBuilder . buildUndef ( { OldLLT } ) ; CurVReg = MIRBuilder . buildMerge ( { NewLLT } , { CurVReg , Undef } ) . getReg ( <NUM_LIT> ) ; } else { CurVReg = MIRBuilder . buildInstr ( ExtendOp , { NewLLT } , { CurVReg } ) . getReg ( <NUM_LIT> ) ; } } else if ( NewLLT . getNumElements ( ) == <NUM_LIT> ) { auto Undef = MIRBuilder . buildUndef ( { OldLLT } ) ; CurVReg = MIRBuilder . buildBuildVector ( { NewLLT } , { CurVReg , Undef . getReg ( <NUM_LIT> ) } ) . getReg ( <NUM_LIT> ) ; } else { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } } else { if ( NewLLT != MRI . getType ( CurVReg ) ) { CurVReg = MIRBuilder . buildInstr ( ExtendOp , { NewLLT } , { CurVReg } ) . getReg ( <NUM_LIT> ) ; } } } } if ( CurVReg != CurArgInfo . Regs [ <NUM_LIT> ] ) { CurArgInfo . Regs [ <NUM_LIT> ] = CurVReg ; setArgFlags ( CurArgInfo , AttributeList :: ReturnIndex , DL , F ) ; } splitToValueTypes ( CurArgInfo , SplitArgs , DL , CC ) ; } <ISA_LIT>OutgoingValueAssigner Assigner ( AssignFn , AssignFn ,


<s> FunctionPass * llvm :: create<ISA_LIT>AtomicExpandPass ( const <ISA_LIT>TargetMachine * TM ) { return new <ISA_LIT>AtomicExpandPass (


<s> static MCInstrInfo * create<ISA_LIT>MCInstrInfo ( ) { MCInstrInfo * X = new MCInstrInfo ( ) ; Init<ISA_LIT>MCInstrInfo ( X


<s> const MachineOperand & MO = MI -> getOperand ( OpNo ) ; switch ( MO . getType ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case MachineOperand :: MO_Register : O << <ISA_LIT>InstPrinter :: getRegisterName ( MO . getReg ( ) ) ; return ; case MachineOperand :: MO_Immediate : O << MO .


<s> size_t i = <NUM_LIT> ; for ( typename SmallVectorImpl < BlockT * > :: const_iterator iterBlk = orderedBlks . begin ( ) , iterBlkEnd = orderedBlks . end ( ) ; iterBlk != iterBlkEnd ; ++ iterBlk , ++ i ) { os << <STR_LIT> << ( * iterBlk ) -> getNumber ( ) ; os << <STR_LIT> << getSCCNum ( * iterBlk ) << <STR_LIT> << ( * iterBlk ) -> size ( ) << <STR_LIT> ; if ( i != <NUM_LIT> && i % <NUM_LIT> == <NUM_LIT>


<s> MCAsmParserExtension :: Initialize ( Parser ) ; MRI = getContext ( ) . getRegisterInfo ( ) ; setAvailableFeatures ( ComputeAvailableFeatures ( STI .


<s> gcc_assert ( JUMP_P ( branch ) ) ; if ( single_set ( branch ) == NULL_RTX || ! any_condjump_p ( branch ) ) reason = <STR_LIT> ; else { rtx_insn * label ; if ( dump_file ) flow_loop_dump ( loop , dump_file , NULL , <NUM_LIT> ) ; label = BB_HEAD ( loop -> header ) ; gcc_assert ( LABEL_P ( label ) ) ; mn10300_insert_setlb_lcc ( label


<s> for ( MCRegAliasIterator AI ( Reg , TRI , true ) ; AI . isValid ( ) ; ++ AI ) if ( RegSet


<s> return <NUM_LIT> - countTrailingZeros < uint64_t > ( Imm .


<s> unsigned OrigAlignment = St -> getAlignment ( ) ; unsigned EltOffset = NumVecElts == <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ; unsigned Alignment = std :: min ( OrigAlignment , EltOffset ) ; SDLoc DL ( St ) ; SDValue BasePtr = St -> getBasePtr ( ) ; SDValue NewST1 = DAG . getStore ( St -> getChain ( ) , DL , SplatVal , BasePtr , St -> getPointerInfo ( ) , St -> isVolatile ( ) , St -> isNonTemporal ( ) , St -> getAlignment ( ) ) ; unsigned Offset = EltOffset ; while ( -- NumVecElts ) { SDValue OffsetPtr = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , BasePtr , DAG . getConstant ( Offset , <STR_LIT> ) ) ; NewST1 = DAG . getStore ( NewST1 . getValue ( <NUM_LIT> ) , DL , SplatVal , OffsetPtr , St -> getPointerInfo ( ) , St -> isVolatile ( ) , St -> isNonTemporal ( ) , Alignment ) ; Offset +=


<s> unsigned <ISA_LIT>MCCodeEmitter :: getBranchTargetOpValue ( const MCInst & MI , unsigned OpNo , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { const MCOperand & MO = MI . getOperand ( OpNo ) ; if ( MO . isReg ( ) || MO . isImm ( ) ) return getMachineOpValue ( MI , MO , Fixups , STI ) ; Fixups . push_back ( MCFixup :: Create ( <NUM_LIT> , MO . getExpr ( )


<s> return usePackedStack ( MF ) ? <STR_LIT>


<s> rtx op1 = operands [ <NUM_LIT> ] ; if ( ! reload_in_progress && ! REG_P ( op0 ) && ! REG_P ( op1 ) && ! ( stik_const_operand ( op1 , mode ) && ! push_operand ( op0 , mode ) ) ) op1 = force_reg ( mode , op1 ) ; if ( GET_CODE ( op1 ) == LO_SUM && GET_MODE ( op1 ) == Pmode && dp_reg_operand ( XEXP ( op1 , <NUM_LIT> ) , mode ) ) { op1 = XEXP ( op1 , <NUM_LIT> ) ; } if ( symbolic_address_operand ( op1 , mode ) ) { if ( TARGET_LOAD_ADDRESS ) { emit_insn ( gen_load_immed_address ( op0 , op1 ) ) ; return <NUM_LIT> ; } else { op1 = force_const_mem ( Pmode , op1 ) ; } } else if ( mode == HFmode && CONSTANT_P ( op1 ) && ! LEGITIMATE_CONSTANT_P ( op1 ) ) { op1 = force_const_mem ( mode , op1 ) ; } if ( TARGET_EXPOSE_LDP && ! ( reload_in_progress || reload_completed ) && GET_CODE ( op1 ) == MEM && symbolic_address_operand ( XEXP ( op1 , <NUM_LIT> ) , Pmode ) ) { rtx dp_reg = gen_rtx_REG ( Pmode , DP_REGNO ) ; if ( ! TARGET_SMALL ) emit_insn ( gen_set_ldp ( dp_reg , XEXP ( op1 , <NUM_LIT> ) ) ) ; op1 = change_address ( op1 , mode , gen_rtx_LO_SUM ( Pmode , dp_reg , XEXP ( op1 , <NUM_LIT> ) ) ) ; } if ( TARGET_EXPOSE_LDP && ! ( reload_in_progress || reload_completed ) && GET_CODE ( op0 ) == MEM && symbolic_address_operand ( XEXP ( op0 , <NUM_LIT> )


<s> auto & RF = cast < MCRelaxableFragment > ( * K ) ; auto & Inst = const_cast < MCInst & > ( RF . getInst ( ) ) ; while ( Size > <NUM_LIT> && <ISA_LIT>MCInstrInfo :: bundleSize ( Inst ) < MaxPacketSize ) { MCInst * Nop = Context . createMCInst ( ) ; Nop -> setOpcode ( <STR_LIT> ) ; Inst . addOperand ( MCOperand :: createInst ( Nop ) ) ; Size -= <NUM_LIT> ; if ( ! <ISA_LIT>MCChecker ( Context , * MCII , * RF . getSubtargetInfo ( ) , Inst , * Context . getRegisterInfo ( ) , false ) . check ( ) ) { Inst . erase ( Inst . end ( ) -


<s> return ; } emitCodeAlignment ( <NUM_LIT> , <NUM_LIT> ) ; MCELFStreamer :: emitInstruction ( Inst , STI ) ; MCFragment * InstructionFragment = getCurrentFragment ( ) ; SMLoc InstLoc = Inst . getLoc ( ) ; if ( LastLabel && ! LastLabel -> isUnset ( ) && LastLabelLoc . isValid ( ) && InstLoc . isValid ( ) ) { const SourceMgr * SourceManager = getContext ( )


<s> void <ISA_LIT>InstPrinter :: printModImmOperand ( const MCInst * MI , unsigned OpNum , const MCSubtargetInfo & STI , raw_ostream & O ) { MCOperand Op = MI -> getOperand ( OpNum ) ; if ( Op . isExpr ( ) ) return printOperand ( MI , OpNum , STI , O ) ; unsigned Bits = Op . getImm ( ) & <NUM_LIT> ; unsigned Rot = ( Op . getImm ( ) & <NUM_LIT> ) >> <NUM_LIT> ; bool PrintUnsigned


<s> SDValue RHS = Op . getOperand ( IsStrict ? <NUM_LIT> : <NUM_LIT> ) ; SDValue Chain = IsStrict ? Op . getOperand ( <NUM_LIT> ) : SDValue ( ) ; EVT LHSVT = LHS . getValueType ( ) ; SDLoc dl ( Op ) ; if ( LHSVT == <STR_LIT> ) { assert ( ! Subtarget . hasP9Vector ( ) && <STR_LIT> ) ; softenSetCCOperands ( DAG , LHSVT , LHS , RHS , CC , dl , LHS , RHS , Chain , Op -> getOpcode ( ) == <STR_LIT> ) ; if ( RHS . getNode ( ) ) LHS = DAG . getNode ( <STR_LIT> , dl , Op . getValueType ( ) , LHS , RHS , DAG . getCondCode ( CC ) ) ; if ( IsStrict ) return DAG . getMergeValues ( { LHS , Chain } , dl ) ; return LHS ; } assert ( ! IsStrict && <STR_LIT> ) ; if ( Op . getValueType ( ) == <STR_LIT>


<s> -- I ; if ( I -> isDebugValue ( ) ) continue ; if ( ! isUnpredicatedTerminator ( * I ) ) break ; switch ( I -> getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : return true ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; case <STR_LIT> : return true ; default : if ( ! I -> isBranch ( ) ) { return true ; } } if ( isDeadBranch ( * I ) ) { if ( AllowModify ) { MachineBasicBlock :: iterator NewI = std :: next ( I ) ; I -> eraseFromParent ( ) ; I = NewI ; } continue ; } if ( ! LastTerminator ) { LastTerminator = & * I ; continue ; } if ( isUnconditionalBranch ( * I ) ) { if ( AllowModify ) LastTerminator -> eraseFromParent ( ) ; LastTerminator = & * I ; continue ; } MachineInstr * FirstTerminator = & * I ; if ( I != MBB . begin ( ) && isUnpredicatedTerminator ( * -- I ) ) { if ( isUnconditionalBranch ( * I ) ) { if ( AllowModify ) { LastTerminator -> eraseFromParent ( ) ; FirstTerminator -> eraseFromParent ( ) ; } LastTerminator = & * I ; continue ; } return true ; } if ( ! isUnconditionalBranch ( * LastTerminator ) || ! isConditionalBranch ( * FirstTerminator ) ) return true ; parseCondBranch ( * FirstTerminator , TrueBB , Cond ) ; TrueBB = getBranchTarget ( * FirstTerminator ) ; FalseBB = getBranchTarget ( * LastTerminator ) ; return false ; } if ( ! LastTerminator ) { assert ( ! TrueBB && ! FalseBB ) ; return false ; } if ( MBB . isLayoutSuccessor ( getBranchTarget ( * LastTerminator ) ) ) { LastTerminator -> eraseFromParent ( ) ; assert ( ! TrueBB && !


<s> if ( TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . isTargetDarwin ( ) ) return new <ISA_LIT>_MachoTargetObjectFile ( ) ; return new <ISA_LIT>_ELFTargetObjectFile (


<s> assert ( SrcReg == <STR_LIT> && <STR_LIT> ) ; for ( unsigned i = StartOp , NumOps = MI -> getNumOperands ( ) - NumOffset ; i != NumOps ; ++ i ) RegList . push_back ( MI -> getOperand ( i ) . getReg ( ) ) ; break ; case <STR_LIT> : assert ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> && <STR_LIT> ) ; RegList . push_back ( SrcReg ) ; break ; } OutStreamer . EmitRegSave ( RegList , Opc == <STR_LIT> ) ; } else { if ( SrcReg == <STR_LIT> ) { int64_t Offset = <NUM_LIT> ; switch ( Opc ) { default : MI -> dump ( ) ; assert ( <NUM_LIT> && <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Offset = <NUM_LIT> ; break ; case <STR_LIT> : Offset = - MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; break ; case <STR_LIT> : case <STR_LIT> : Offset = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; break ; case <STR_LIT> : Offset = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) * <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : Offset = - MI -> getOperand ( <NUM_LIT> ) . getImm ( ) * <NUM_LIT> ; break ; case <STR_LIT> : { unsigned CPI = MI -> getOperand ( <NUM_LIT> ) . getIndex ( ) ; const MachineConstantPool * MCP = MF . getConstantPool ( ) ; if ( CPI >= MCP -> getConstants ( ) . size ( ) ) CPI = AFI . getOriginalCPIdx ( CPI ) ; assert ( CPI != - <NUM_LIT>


<s> assert ( Bit < <NUM_LIT> && <STR_LIT> ) ; bool UseWReg = Bit < <NUM_LIT> ; unsigned NecessarySize = UseWReg ? <NUM_LIT> : <NUM_LIT> ; if ( Size != NecessarySize ) TestReg = moveScalarRegClass ( TestReg , UseWReg ? <STR_LIT> : <STR_LIT> , MIB ) ; static const unsigned OpcTable [ <NUM_LIT> ] [ <NUM_LIT> ] = { { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } } ; unsigned Opc = OpcTable [ UseWReg ] [ IsNegative ] ; auto TestBitMI = MIB . buildInstr ( Opc ) . addReg ( TestReg ) . addImm ( Bit ) . addMBB ( DstMBB ) ; constrainSelectedInstRegOperands ( * TestBitMI , TII , TRI ,


<s> DEBUG ( dbgs ( ) << <STR_LIT> << printMBBReference ( * BB ) << <STR_LIT> << BB -> getName ( ) << <STR_LIT> << BB -> getParent ( ) -> getName ( ) << <STR_LIT> << MLI -> getLoopDepth ( BB ) << <STR_LIT> ) ; buildDAGWithRegPressure ( ) ; SmallVector < SUnit * , <NUM_LIT> > TopRoots , BotRoots ; findRootsAndBiasEdges ( TopRoots , BotRoots ) ; SchedImpl -> initialize ( this ) ; DEBUG ( unsigned maxH = <NUM_LIT> ; for ( unsigned su = <NUM_LIT> , e = SUnits . size ( ) ; su != e ; ++ su ) if ( SUnits [ su ] . getHeight ( ) > maxH ) maxH = SUnits [ su ] . getHeight ( ) ; dbgs ( ) << <STR_LIT> << maxH << <STR_LIT> ; ) ; DEBUG ( unsigned maxD = <NUM_LIT> ; for ( unsigned su = <NUM_LIT> , e = SUnits . size ( ) ; su != e ; ++ su ) if ( SUnits [ su ] . getDepth ( ) > maxD ) maxD = SUnits [ su ] . getDepth ( ) ; dbgs ( ) << <STR_LIT> << maxD << <STR_LIT> ; ) ; DEBUG ( for ( unsigned su = <NUM_LIT> , e = SUnits . size ( ) ; su != e ; ++ su ) SUnits [ su ] .


<s> push ( HARD_FRAME_POINTER_REGNUM ) ; emit_move_insn ( hard_frame_pointer_rtx , addr ) ; if ( REGNO ( addr ) == SP_REG ) emit_move_insn ( hard_frame_pointer_rtx , plus_constant

( hard_frame_pointer_rtx , GET_MODE_SIZE ( word_mode ) ) ) ;


<s> unsigned ImmOffs = <STR_LIT> ( MO2 . getImm ( ) ) ; unsigned Op = <STR_LIT> ( MO2 . getImm ( ) ) ; if ( AlwaysPrintImm0 || ImmOffs || Op == <STR_LIT> ) { O << <STR_LIT> << markup ( <STR_LIT> ) << <STR_LIT> << <STR_LIT> ( <STR_LIT> ( MO2 . getImm ( ) ) ) << ImmOffs * <NUM_LIT> << markup ( <STR_LIT> ) ; } O << <STR_LIT> << markup (


<s> if ( RegNo > <NUM_LIT> ) return MCDisassembler :: Fail ; unsigned Reg = getReg ( Decoder , <STR_LIT> , RegNo ) ; Inst . addOperand ( MCOperand :: createReg ( Reg )


<s> for ( unsigned i = <NUM_LIT> , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) { const MachineOperand & MO = MI -> getOperand ( i ) ; MCOperand MCOp ; switch ( MO . getType ( ) ) { default : MI -> print ( errs ( ) ) ; llvm_unreachable ( <STR_LIT> ) ; case MachineOperand :: MO_Register : if ( MO . isImplicit ( ) ) continue ; MCOp = MCOperand :: createReg ( MO . getReg ( ) ) ; break ; case MachineOperand :: MO_Immediate : MCOp = MCOperand :: createImm ( MO . getImm ( ) ) ; break ; case MachineOperand :: MO_MachineBasicBlock : MCOp = MCOperand :: createExpr ( MCSymbolRefExpr :: create ( MO . getMBB


<s> OutStreamer -> emitInstruction ( MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) , STI ) ; OutStreamer -> emitInstruction ( MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( - <NUM_LIT> ) . addImm ( LPAC :: makePreOp ( LPAC :: ADD ) ) , STI ) ; if ( MI -> getOpcode ( ) == <STR_LIT> ) { MCInst TmpInst ; MCInstLowering . Lower ( MI , TmpInst ) ; TmpInst . setOpcode ( <STR_LIT> ) ; OutStreamer -> emitInstruction ( TmpInst , STI ) ; }