<s> const LLT DstTy = MRI . getType ( DstReg ) ; const LLT SrcTy = MRI . getType ( SrcReg ) ; if ( SrcTy != LLT :: scalar ( <NUM_LIT> ) ) return false ; unsigned AndOpc ; if ( DstTy == LLT :: scalar ( <NUM_LIT> ) ) AndOpc = <STR_LIT> ; else if ( DstTy == LLT :: scalar ( <NUM_LIT> ) ) AndOpc = <STR_LIT> ; else if ( DstTy == LLT :: scalar ( <NUM_LIT> ) ) AndOpc = <STR_LIT> ; else if ( DstTy == LLT :: scalar ( <NUM_LIT> ) ) AndOpc = <STR_LIT> ; else return false ; unsigned DefReg = SrcReg ; if ( DstTy != LLT :: scalar ( <NUM_LIT> ) ) { DefReg = MRI . createVirtualRegister ( getRegClass ( DstTy , DstReg , MRI ) ) ; BuildMI ( * I . getParent ( ) , I , I . getDebugLoc ( ) , TII . get ( TargetOpcode :: SUBREG_TO_REG ) , DefReg ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg ) . addImm ( <STR_LIT> ) ; } MachineInstr & AndInst = * BuildMI ( * I . getParent ( ) , I , I . getDebugLoc ( ) , TII . get ( AndOpc ) , DstReg ) . addReg ( DefReg ) . addImm ( <NUM_LIT> ) ; constrainSelectedInstRegOperands ( AndInst , TII , TRI


<s> SDValue <ISA_LIT>TargetLowering :: LowerFRAMEADDR ( SDValue Op , SelectionDAG & DAG ) const { SDLoc dl ( Op ) ; unsigned Depth = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; MachineFunction & MF = DAG . getMachineFunction ( ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; MFI . setFrameAddressIsTaken ( true ) ; EVT PtrVT = getPointerTy ( MF . getDataLayout ( ) ) ; bool is<ISA_LIT>64 = PtrVT == <STR_LIT> ; unsigned FrameReg ; if ( MF . getFunction ( ) -> hasFnAttribute ( Attribute :: Naked ) ) FrameReg = is<ISA_LIT>64 ? <STR_LIT> : <STR_LIT> ; else FrameReg = is<ISA_LIT>64 ? <STR_LIT>


<s> if ( const GlobalAlias * GA = dyn_cast < GlobalAlias > ( GV ) ) if ( const GlobalVariable * GVar = dyn_cast_or_null < GlobalVariable > ( GA -> resolveAliasedGlobal ( false ) ) ) if ( GVar -> isThreadLocal ( ) ) return false ; if ( ! Subtarget -> isPICStyleRIPRel ( ) || ( AM . Base . Reg == <NUM_LIT> && AM . IndexReg == <NUM_LIT> ) ) { AM . GV = GV ; unsigned char GVFlags = Subtarget -> ClassifyGlobalReference ( GV , TM ) ; if ( isGlobalRelativeToPICBase ( GVFlags ) ) { AM . Base . Reg = getInstrInfo ( ) -> getGlobalBaseReg ( FuncInfo . MF ) ; } if ( ! isGlobalStubReference ( GVFlags ) ) { if ( Subtarget -> isPICStyleRIPRel ( ) ) { assert ( AM . Base . Reg == <NUM_LIT> && AM . IndexReg == <NUM_LIT> ) ; AM . Base . Reg = <STR_LIT> ; } AM . GVOpFlags = GVFlags ; return true ; } DenseMap < const Value * , unsigned > :: iterator I = LocalValueMap . find ( V ) ; unsigned LoadReg ; if ( I != LocalValueMap . end ( ) && I -> second != <NUM_LIT> ) { LoadReg = I -> second ; } else { unsigned Opc = <NUM_LIT> ; const TargetRegisterClass * RC = NULL ; <ISA_LIT>AddressMode StubAM ; StubAM . Base . Reg = AM . Base . Reg ; StubAM . GV = GV ; StubAM . GVOpFlags = GVFlags ; SavePoint SaveInsertPt = enterLocalValueArea ( ) ; if ( TLI . getPointerTy ( ) == <STR_LIT> ) { Opc = <STR_LIT> ; RC = & <STR_LIT> ; if ( Subtarget -> isPICStyleRIPRel ( ) ) StubAM . Base . Reg = <STR_LIT> ; } else { Opc = <STR_LIT> ; RC = & <STR_LIT> ; } LoadReg = createResultReg ( RC ) ; MachineInstrBuilder LoadMI = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( Opc ) , LoadReg ) ; addFullAddress ( LoadMI , StubAM ) ; leaveLocalValueArea ( SaveInsertPt ) ; LocalValueMap [ V ] = LoadReg ; } AM . Base . Reg = LoadReg ; AM . GV = <NUM_LIT> ; return true ; } } if ( ! AM . GV || ! Subtarget -> isPICStyleRIPRel ( ) ) { if ( AM . Base . Reg == <NUM_LIT> ) { AM . Base . Reg = getRegForValue ( V ) ; return AM . Base . Reg != <NUM_LIT> ; } if ( AM . IndexReg == <NUM_LIT> ) { assert ( AM . Scale == <NUM_LIT> && <STR_LIT> ) ; AM . IndexReg = getRegForValue ( V ) ; return AM . IndexReg != <NUM_LIT> ; } } return false


<s> SelectionDAG & DAG = DCI . DAG ; SDValue Op = N -> getOperand ( <NUM_LIT> ) ; if ( ! Subtarget -> hasNEON ( ) ) return SDValue ( ) ; LoadSDNode * LD = dyn_cast < LoadSDNode > ( Op . getNode ( ) ) ; if ( LD && Op . hasOneUse ( ) && LD -> isUnindexed ( ) && LD -> getMemoryVT ( ) == N -> getValueType ( <NUM_LIT> ) . getVectorElementType ( ) ) { SDValue Ops [ ] = { LD -> getOperand ( <NUM_LIT> ) , LD -> getOperand ( <NUM_LIT> ) , DAG . getConstant ( LD -> getAlignment ( ) , SDLoc ( N ) , <STR_LIT> ) } ; SDVTList SDTys = DAG . getVTList ( N -> getValueType ( <NUM_LIT> ) , <STR_LIT> ) ; SDValue VLDDup = DAG . getMemIntrinsicNode ( <STR_LIT> , SDLoc ( N ) , SDTys , Ops , LD -> getMemoryVT ( ) , LD -> getMemOperand ( ) ) ; DAG . ReplaceAllUsesOfValueWith ( SDValue ( LD , <NUM_LIT> ) , VLDDup . getValue ( <NUM_LIT> ) ) ; return VLDDup ; } return SDValue ( )


<s> if ( V2 . isUndef ( ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , getV4<ISA_LIT>ShuffleImm8ForMask ( RepeatedMask , DL , DAG ) ) ; if ( SDValue Unpck = lowerVectorShuffleWithUNPCK ( DL , <STR_LIT> , Mask , V1 , V2 , DAG ) ) return Unpck ; return lowerVectorShuffleWithSHUFPS ( DL , <STR_LIT> , RepeatedMask , V1 , V2 , DAG ) ; } return lowerVectorShuffleWithPERMV ( DL , <STR_LIT> , Mask


<s> MachineFunction * MF = Header -> getParent ( ) ; DebugLoc DL ; if ( ! Latch || Header -> hasAddressTaken ( ) ) return <NUM_LIT> ; typedef MachineBasicBlock :: instr_iterator instr_iterator ; typedef MachineBasicBlock :: pred_iterator pred_iterator ; typedef std :: vector < MachineBasicBlock * > MBBVector ; MBBVector Preds ( Header -> pred_begin ( ) , Header -> pred_end ( ) ) ; SmallVector < MachineOperand , <NUM_LIT> > Tmp1 ; MachineBasicBlock * TB = <NUM_LIT> , * FB = <NUM_LIT> ; if ( TII -> AnalyzeBranch ( * Latch , TB , FB , Tmp1 , false ) ) return <NUM_LIT> ; for ( MBBVector :: iterator I = Preds . begin ( ) , E = Preds . end ( ) ; I != E ; ++ I ) { MachineBasicBlock * PB = * I ; if ( PB != Latch ) { bool NotAnalyzed = TII -> AnalyzeBranch ( * PB , TB , FB , Tmp1 , false ) ; if ( NotAnalyzed ) return <NUM_LIT> ; } } MachineBasicBlock * NewPH = MF -> CreateMachineBasicBlock ( ) ; MF -> insert ( Header , NewPH ) ; if ( Header -> pred_size ( ) > <NUM_LIT> ) { for ( instr_iterator I = Header -> instr_begin ( ) , E = Header -> instr_end ( ) ; I != E && I -> isPHI ( ) ; ++ I ) { MachineInstr * PN = & * I ; const MCInstrDesc & PD = TII -> get ( TargetOpcode :: PHI ) ; MachineInstr * NewPN = MF -> CreateMachineInstr ( PD , DL ) ; NewPH -> insert ( NewPH -> end ( ) , NewPN ) ; unsigned PR = PN -> getOperand ( <NUM_LIT> ) . getReg ( ) ; const TargetRegisterClass * RC = MRI -> getRegClass ( PR ) ; unsigned NewPR = MRI -> createVirtualRegister ( RC ) ; NewPN -> addOperand ( MachineOperand :: CreateReg ( NewPR , true ) ) ; for ( unsigned i = <NUM_LIT> , n = PN -> getNumOperands ( )


<s> vld1q_u16 ( const uint16_t * __a ) { return ( uint16x8_t ) __builtin_neon_vld1v8hi ( ( const __builtin_neon_hi * )


<s> struct unw_labeled_state * ls ; labeled_state_alloced ++ ; ls = malloc ( sizeof ( struct unw_labeled_state ) ) ; if ( ! ls ) { int n = atomic_alloc ( &


<s> DelayedWaitOn = ZeroCounts ; LastIssued = ZeroCounts ; LastOpcodeType = OTHER ; LastInstWritesM0 = false ; ReturnsVoid = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) -> returnsVoid ( ) ; memset ( & UsedRegs , <NUM_LIT> , sizeof ( UsedRegs ) ) ; memset ( & DefinedRegs , <NUM_LIT> , sizeof ( DefinedRegs ) ) ; SmallVector < MachineInstr * , <NUM_LIT> > RemoveMI ; for ( MachineFunction :: iterator BI = MF . begin ( ) , BE = MF . end ( ) ; BI != BE ; ++ BI ) { MachineBasicBlock & MBB = * BI ; for ( MachineBasicBlock :: iterator I = MBB . begin ( ) , E = MBB . end ( ) ; I != E ; ++ I ) { if ( ST -> getGeneration ( ) <= <ISA_LIT>Subtarget :: SEA_ISLANDS ) { if ( TII -> isSMRD ( I -> getOpcode ( ) ) ) { VCCZCorrupt = true ; } else if ( ! hasOutstandingLGKM ( ) && I -> modifiesRegister (


<s> bool hasStdExtZbr ( ) const { return HasStdExtZbr


<s> DebugLoc dl = N -> getDebugLoc ( ) ; assert ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT> && N -> getOpcode ( ) == <STR_LIT> && <STR_LIT> ) ; SDValue Chain , DataPtr ; LowerVAARG ( N , Chain , DataPtr , DAG ) ; SDValue Res = DAG . getLoad ( N -> getValueType ( <NUM_LIT> ) , dl , Chain , DataPtr

, NULL , <NUM_LIT> , false , false , <NUM_LIT> ) ;


<s> function_table = new hash_table < registered_function_hasher > ( <NUM_LIT> ) ; function_builder builder ; for ( unsigned int i = <NUM_LIT> ; i < ARRAY_SIZE ( function_groups ) ;

++ i ) builder . register_function_group ( function_groups [ i ] ) ;


<s> if ( parseOperand ( Operands ) ) return true ; } if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) { SMLoc Loc = getLexer ( ) . getLoc ( ) ; getParser ( ) . eatToEndOfStatement ( ) ; return Error ( Loc , <STR_LIT> ) ; } getParser ( ) . Lex


<s> void setName ( StringRef N ) { Name = std :: string ( N


<s> const MCSection * Section = getStreamer ( ) . getCurrentSectionOnly ( ) ; assert ( Section && <STR_LIT> ) ; if ( Section -> UseCodeAlign ( ) ) getStreamer ( ) . EmitCodeAlignment ( <NUM_LIT> , <NUM_LIT> ) ; else getStreamer ( ) . EmitValueToAlignment ( <NUM_LIT> , <NUM_LIT> ,


<s> DecodeStatus <ISA_LIT>Disassembler :: getInstruction ( MCInst & MI , uint64_t & Size , ArrayRef < uint8_t > Bytes_ , uint64_t Address , raw_ostream & WS , raw_ostream & CS ) const { CommentStream = & CS ; assert ( <STR_LIT> ( STI ) && <STR_LIT> ) ; const unsigned MaxInstBytesNum = ( std :: min ) ( ( size_t ) <NUM_LIT> , Bytes_ . size ( ) ) ; Bytes = Bytes_ . slice ( <NUM_LIT> , MaxInstBytesNum ) ; DecodeStatus Res = MCDisassembler :: Fail ; do { if ( Bytes . size ( ) < <NUM_LIT> ) break ; const uint32_t DW = eatB32 ( Bytes ) ; Res = tryDecodeInst ( DecoderTableVI32 , MI ,


<s> fs -> regs . reg [ <NUM_LIT> ] . loc . offset = ( long ) & sc -> REG_NAME ( ebx ) - new_cfa ; fs -> regs . reg [ <NUM_LIT> ] . how = REG_SAVED_OFFSET ; fs -> regs . reg [ <NUM_LIT> ] . loc . offset = ( long ) & sc -> REG_NAME ( ecx ) - new_cfa ; fs -> regs . reg [ <NUM_LIT> ] . how = REG_SAVED_OFFSET ; fs -> regs . reg [ <NUM_LIT> ] . loc . offset = ( long ) & sc -> REG_NAME ( edx ) - new_cfa ; fs -> regs . reg [ <NUM_LIT> ] . how = REG_SAVED_OFFSET ; fs -> regs . reg [ <NUM_LIT> ] . loc . offset = ( long ) & sc -> REG_NAME ( esi ) - new_cfa ; fs -> regs . reg [ <NUM_LIT> ] . how = REG_SAVED_OFFSET ; fs -> regs . reg [ <NUM_LIT> ] . loc . offset = ( long ) & sc -> REG_NAME ( edi ) - new_cfa ; fs -> regs . reg [ <NUM_LIT> ] . how = REG_SAVED_OFFSET ; fs -> regs . reg [ <NUM_LIT> ] . loc . offset = ( long ) & sc -> REG_NAME ( ebp ) - new_cfa ; fs -> regs . reg [ <NUM_LIT> ] . how


<s> BSSSection = nullptr ; ReadOnlySection = nullptr ; StaticCtorSection = nullptr ; StaticDtorSection = nullptr ; LSDASection = nullptr ; EHFrameSection = nullptr ; DwarfAbbrevSection = nullptr ; DwarfInfoSection = nullptr ; DwarfLineSection = nullptr ; DwarfFrameSection = nullptr ; DwarfPubTypesSection = nullptr


<s> } ; packLanes ( RayOrigin ) ; if ( IsA16 ) { auto UnmergeRayDir = B . buildUnmerge ( { S16 , S16 , S16 , S16 } , RayDir ) ; auto UnmergeRayInvDir = B . buildUnmerge ( { S16 , S16 , S16 , S16 } , RayInvDir ) ; Register R1 = MRI . createGenericVirtualRegister ( S32 ) ; Register R2 = MRI . createGenericVirtualRegister ( S32 ) ; Register R3 = MRI . createGenericVirtualRegister ( S32 ) ; B . buildMerge ( R1 , { UnmergeRayDir . getReg ( <NUM_LIT> ) , UnmergeRayDir . getReg ( <NUM_LIT> ) } ) ; B . buildMerge ( R2 , { UnmergeRayDir . getReg ( <NUM_LIT> ) , UnmergeRayInvDir . getReg ( <NUM_LIT> ) } ) ; B . buildMerge ( R3 , { UnmergeRayInvDir . getReg ( <NUM_LIT> ) , UnmergeRayInvDir . getReg ( <NUM_LIT> ) } ) ; Ops . push_back ( R1 ) ; Ops . push_back ( R2 ) ; Ops . push_back ( R3 ) ; } else { packLanes ( RayDir ) ; packLanes ( RayInvDir ) ; } auto MIB = B . buildInstr ( <STR_LIT> ) . addDef (


<s> LowerSETCC ( SDValue Op , SelectionDAG & DAG ) const { llvm_unreachable (


<s> DEBUG ( dbgs ( ) << <STR_LIT> ) ; DEBUG ( MI -> dump ( ) ) ; <ISA_LIT>MCInstLower MCInstLowering ( OutContext , * Mang , * this ) ; MCInst TmpInst


<s> return <NUM_LIT> ; } llvm_unreachable (


<s> switch ( MI . getOpcode ( ) ) { case TargetOpcode :: G_CONCAT_VECTORS : return Helper . tryCombineConcatVectors ( MI ) ; case TargetOpcode :: G_SHUFFLE_VECTOR : return Helper . tryCombineShuffleVector ( MI ) ; case TargetOpcode :: G_MEMCPY : case TargetOpcode :: G_MEMMOVE : case TargetOpcode :: G_MEMSET : { unsigned MaxLen = EnableOpt ? <NUM_LIT> :


<s> Instruction * <ISA_LIT>TargetLowering :: emitLeadingFence ( IRBuilder < > & Builder , Instruction *


<s> static unsigned int xtensa_hard_regno_nregs ( unsigned int regno , machine_mode mode ) { if ( FP_REG_P ( regno ) ) return CEIL ( GET_MODE_SIZE ( mode ) , UNITS_PER_FPREG ) ; return CEIL ( GET_MODE_SIZE ( mode ) , UNITS_PER_WORD


<s> delta_rtx = scratch ; } emit_insn ( gen_add2_insn ( this_rtx , delta_rtx ) ) ; } if ( vcall_offset ) { rtx vcall_offset_rtx = GEN_INT ( vcall_offset ) ; rtx scratch = gen_rtx_REG ( Pmode , <NUM_LIT> ) ; gcc_assert ( vcall_offset < <NUM_LIT> ) ; emit_move_insn ( scratch , gen_rtx_MEM ( Pmode , this_rtx ) ) ; if ( SPARC_SIMM13_P ( vcall_offset ) ) ; else if ( ! fixed_regs [ <NUM_LIT> ] && vcall_offset < - <NUM_LIT> ) { rtx scratch2 = gen_rtx_REG ( Pmode , <NUM_LIT> ) ; emit_move_insn ( scratch2 , vcall_offset_rtx ) ; vcall_offset_rtx = scratch2 ; } else { rtx increment = GEN_INT ( - <NUM_LIT> ) ; while ( ! SPARC_SIMM13_P ( vcall_offset ) ) { emit_insn ( gen_add2_insn ( scratch , increment ) ) ; vcall_offset += <NUM_LIT> ; } vcall_offset_rtx = GEN_INT ( vcall_offset ) ; } emit_move_insn ( scratch , gen_rtx_MEM ( Pmode , gen_rtx_PLUS ( Pmode , scratch , vcall_offset_rtx ) ) ) ; emit_insn ( gen_add2_insn ( this_rtx , scratch ) ) ; } if ( ! TREE_USED ( function ) ) { assemble_external ( function ) ; TREE_USED ( function ) = <NUM_LIT> ; } funexp = XEXP ( DECL_RTL ( function ) , <NUM_LIT> ) ; if ( flag_delayed_branch ) { funexp = gen_rtx_MEM ( FUNCTION_MODE , funexp ) ; insn = emit_call_insn ( gen_sibcall ( funexp ) ) ; SIBLING_CALL_P ( insn ) = <NUM_LIT> ; } else { rtx spill_reg , seq , scratch = gen_rtx_REG ( Pmode , <NUM_LIT> ) ; if ( flag_pic ) { spill_reg = gen_rtx_REG ( word_mode , <NUM_LIT> ) ; start_sequence ( ) ; load_got_register ( ) ; if ( ! TARGET_VXWORKS_RTP ) pic_offset_table_rtx = got_register_rtx ; scratch = sparc_legitimize_pic_address ( funexp , scratch ) ; seq = get_insns ( ) ; end_sequence (


<s> aarch64_isa_flags = <NUM_LIT> ; bool valid_cpu = true ; bool valid_tune = true ; bool valid_arch = true ; selected_cpu = NULL ; selected_arch = NULL ; selected_tune = NULL ; if ( aarch64_harden_sls_string ) aarch64_validate_sls_mitigation ( aarch64_harden_sls_string ) ; if ( aarch64_branch_protection_string ) aarch64_validate_mbranch_protection ( aarch64_branch_protection_string ) ; if ( aarch64_cpu_string ) valid_cpu = aarch64_validate_mcpu ( aarch64_cpu_string , & selected_cpu , & cpu_isa ) ; if ( aarch64_arch_string ) valid_arch = aarch64_validate_march ( aarch64_arch_string , & selected_arch , & arch_isa ) ; if ( aarch64_tune_string ) valid_tune = aarch64_validate_mtune ( aarch64_tune_string , & selected_tune ) ; SUBTARGET_OVERRIDE_OPTIONS ; if ( ! selected_cpu ) { if ( selected_arch ) { selected_cpu = & all_cores [ selected_arch -> ident ] ; aarch64_isa_flags = arch_isa ; explicit_arch = selected_arch -> arch ; } else { selected_cpu = aarch64_get_tune_cpu ( aarch64_none ) ; aarch64_isa_flags = TARGET_CPU_DEFAULT >> <NUM_LIT> ; } if ( selected_tune ) explicit_tune_core = selected_tune -> ident ; } else if ( selected_arch ) { if ( selected_arch -> arch != selected_cpu -> arch ) { warning ( <NUM_LIT> , <STR_LIT> , aarch64_cpu_string , aarch64_arch_string ) ; } aarch64_isa_flags = arch_isa ; explicit_arch = selected_arch -> arch ; explicit_tune_core = selected_tune ? selected_tune -> ident : selected_cpu -> ident ; } else { aarch64_isa_flags = cpu_isa ; explicit_tune_core = selected_tune ? selected_tune -> ident : selected_cpu -> ident ; gcc_assert ( selected_cpu ) ; selected_arch = & all_architectures [ selected_cpu -> arch ] ; explicit_arch = selected_arch -> arch ; } if ( ! selected_arch ) { gcc_assert ( selected_cpu ) ; selected_arch = & all_architectures [ selected_cpu -> arch ] ; } if ( ! selected_tune ) selected_tune = selected_cpu ; if ( aarch64_enable_bti == <NUM_LIT> ) { aarch64_enable_bti = <NUM_LIT> ; aarch64_enable_bti = <NUM_LIT>


<s> static bool callWaitsOnFunctionEntry ( const MachineInstr & MI


<s> bool <ISA_LIT>FrameLowering :: hasFP ( const MachineFunction & MF ) const { const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; return ( MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) || MF . getFrameInfo

( ) -> hasVarSizedObjects ( ) || MFI -> isFrameAddressTaken ( ) ) ;


<s> const TargetRegisterClass * getPointerRegClass ( const MachineFunction & MF , unsigned Kind = <NUM_LIT> ) const override { return &


<s> unsigned <ISA_LIT>MCCodeEmitter :: fixOneOperandFPComparison ( const MCInst & MI , unsigned EncodedValue , const MCSubtargetInfo & STI ) const { EncodedValue &= ~ ( <NUM_LIT> << <NUM_LIT>


<s> if ( cfun -> machine -> sdmode_stack_slot != NULL_RTX ) instantiate_decl_rtl ( cfun -> machine


<s> assert ( ValSize <= <NUM_LIT> && <STR_LIT> ) ; assert ( LocSize <= <NUM_LIT> && <STR_LIT> ) ; markPhysRegUsed ( PhysReg ) ; if ( ValSize == LocSize ) { MIRBuilder . buildCopy ( ValVReg , PhysReg ) ; } else { assert ( ValSize < LocSize && <STR_LIT> ) ; auto PhysRegToVReg = MIRBuilder . buildCopy ( LLT :: scalar ( LocSize ) , PhysReg ) ; MIRBuilder . buildTrunc ( ValVReg ,


<s> <ISA_LIT>Instr ( <ISA_LIT>CVIResource :: TypeUnitsAndLanes * T , MCInstrInfo const & MCII , MCInst const * id , MCInst const * Extender , unsigned s , bool x = false ) : ID ( id ) , Extender ( Extender ) , Core ( s ) , CVI ( T , MCII


<s> AddedSize += this -> getRegionSize ( ) ; return ; } bool BPChanged = false ; if ( CSRs . size ( ) > <NUM_LIT> && ( ( AddedSize + Offset ) - Scale ) > ( uint64_t ) Scale * <NUM_LIT> ) { Basereg = adjustRegBySVE ( MF , MBB , MBBI , DL , Basereg , AddedSize + Offset , true ) ; AddedSize = <NUM_LIT>


<s> address = temp_reg ; pic_ref = gen_const_mem ( Pmode , address ) ; crtl -> uses_pic_offset_table = <NUM_LIT> ; emit_move_insn ( reg , pic_ref ) ; return reg ; } } else if ( GET_CODE ( orig ) == CONST ) { rtx base , offset ; if ( GET_CODE ( XEXP ( orig , <NUM_LIT> ) ) == PLUS && XEXP ( XEXP ( orig , <NUM_LIT> ) , <NUM_LIT> ) == tilegx_got_rtx ( ) ) return orig ; if ( reg == <NUM_LIT> ) { gcc_assert ( can_create_pseudo_p ( ) ) ; reg = gen_reg_rtx ( Pmode ) ; } gcc_assert ( GET_CODE ( XEXP ( orig , <NUM_LIT> ) ) == PLUS ) ; base = tilegx_legitimize_pic_address ( XEXP ( XEXP ( orig , <NUM_LIT> ) , <NUM_LIT> ) , Pmode , reg ) ; offset = tilegx_legitimize_pic_address ( XEXP ( XEXP ( orig , <NUM_LIT> ) , <NUM_LIT> ) , Pmode , base == reg ? <NUM_LIT> : reg ) ; if ( CONST_INT_P ( offset ) ) { if ( can_create_pseudo_p ( ) ) offset = force_reg ( Pmode , offset ) ; else gcc_unreachable ( ) ; } if ( can_create_pseudo_p ( ) ) return force_reg ( Pmode , gen_rtx_PLUS ( Pmode , base , offset ) ) ; else gcc_unreachable ( ) ; } else if ( GET_CODE ( orig ) == LABEL_REF ) { rtx address ; rtx temp_reg ; if ( reg == <NUM_LIT> ) { gcc_assert ( can_create_pseudo_p ( ) ) ; reg = gen_reg_rtx ( Pmode ) ; } temp_reg = create_temp_reg_if_possible ( Pmode , reg ) ; tilegx_compute_pcrel_address ( temp_reg , orig ) ; crtl -> uses_pic_offset_table = <NUM_LIT> ; address = temp_reg ; emit_move_insn ( reg ,


<s> static MCOperand create<ISA_LIT>MCOperand ( <ISA_LIT>MCExpr :: VariantKind Kind , MCSymbol * Sym , MCContext & OutContext ) { const MCSymbolRefExpr * MCSym = MCSymbolRefExpr :: create ( Sym , OutContext ) ; const <ISA_LIT>MCExpr * expr = <ISA_LIT>MCExpr :: create ( Kind ,


<s> msb_val = val >= <NUM_LIT> ? <NUM_LIT> : - <NUM_LIT> ; for ( i = <NUM_LIT> ; i <= copies ; i *= <NUM_LIT> ) { HOST_WIDE_INT small_val ; bitsize /= <NUM_LIT> ; small_val = splat_val >> bitsize ; mask >>= bitsize ; if ( splat_val != ( ( small_val << bitsize ) | ( small_val & mask ) ) ) return false ; splat_val = small_val ; } if ( EASY_VECTOR_15 ( splat_val ) ) ; else if ( EASY_VECTOR_15_ADD_SELF ( splat_val ) && ( splat_val >= <NUM_LIT> || ( step == <NUM_LIT> && copies


<s> else if ( strcmp ( arg , <STR_LIT> ) == <NUM_LIT> ) mips_abi = ABI_64 ; else if ( strcmp ( arg , <STR_LIT> ) == <NUM_LIT> ) mips_abi = ABI_EABI ; else return false ; return true ; case OPT_march_ : case OPT_mtune_ : return mips_parse_cpu ( arg ) != <NUM_LIT> ; case


<s> <ISA_LIT>TargetStreamer & TS = getTargetStreamer ( ) ; TS . setPic ( OutContext . getObjectFileInfo ( ) -> isPositionIndependent ( ) ) ; const Triple & TT = TM . getTargetTriple ( ) ; StringRef CPU = <STR_LIT> ( TT , TM . getTargetCPU ( ) ) ; StringRef FS = TM . getTargetFeatureString ( ) ; const <ISA_LIT>TargetMachine & MTM = static_cast < const <ISA_LIT>TargetMachine & > ( TM ) ; const <ISA_LIT>Subtarget STI ( TT , CPU , FS , MTM . isLittleEndian ( ) , MTM , <NUM_LIT> ) ; bool IsABICalls = STI . isABICalls ( ) ; const <ISA_LIT>ABIInfo & ABI = MTM . getABI ( ) ; if ( IsABICalls ) { TS . emitDirectiveAbiCalls (


<s> MachineBasicBlock :: iterator InsertPos = isLd ? FirstOp : LastOp ; while ( InsertPos != MBB -> end ( ) && ( MemOps . count ( InsertPos ) || InsertPos -> isDebugValue ( ) ) ) ++ InsertPos ; MachineInstr * Op0 = Ops . back ( ) ; MachineInstr * Op1 = Ops [ Ops . size ( ) - <NUM_LIT> ] ; unsigned EvenReg = <NUM_LIT> , OddReg = <NUM_LIT> ; unsigned BaseReg = <NUM_LIT> , PredReg = <NUM_LIT> ; <STR_LIT> Pred = <STR_LIT> ; bool isT2 = false ; unsigned NewOpc = <NUM_LIT> ; int Offset = <NUM_LIT> ; DebugLoc dl ; if ( NumMove == <NUM_LIT> && CanFormLdStDWord ( Op0 , Op1 , dl , NewOpc , EvenReg , OddReg , BaseReg , Offset , PredReg , Pred , isT2 ) ) { Ops . pop_back ( ) ; Ops . pop_back ( ) ; const MCInstrDesc & MCID = TII -> get ( NewOpc ) ; const TargetRegisterClass * TRC = TII -> getRegClass ( MCID , <NUM_LIT> , TRI , * MF ) ; MRI -> constrainRegClass ( EvenReg , TRC ) ; MRI -> constrainRegClass ( OddReg , TRC ) ; if ( isLd ) { MachineInstrBuilder MIB = BuildMI ( * MBB , InsertPos , dl , MCID ) . addReg ( EvenReg , RegState :: Define ) . addReg ( OddReg , RegState :: Define ) . addReg ( BaseReg ) ; if ( ! isT2 ) MIB . addReg ( <NUM_LIT> ) ; MIB . addImm ( Offset ) . addImm ( Pred ) . addReg ( PredReg ) ; concatenateMemOperands ( MIB , Op0 , Op1 ) ; DEBUG ( dbgs ( ) << <STR_LIT> << * MIB << <STR_LIT> ) ; ++ NumLDRDFormed ; } else { MachineInstrBuilder MIB = BuildMI ( * MBB , InsertPos , dl , MCID ) . addReg ( EvenReg ) . addReg ( OddReg ) . addReg ( BaseReg ) ; if ( ! isT2 ) MIB . addReg ( <NUM_LIT> ) ; MIB . addImm ( Offset ) . addImm ( Pred ) . addReg ( PredReg ) ; concatenateMemOperands ( MIB , Op0 , Op1 ) ; DEBUG ( dbgs ( ) << <STR_LIT> << * MIB << <STR_LIT> ) ; ++ NumSTRDFormed ; } MBB -> erase ( Op0 ) ; MBB -> erase ( Op1 ) ; MRI -> setRegAllocationHint ( EvenReg , <STR_LIT> , OddReg ) ; MRI -> setRegAllocationHint ( OddReg , <STR_LIT> , EvenReg ) ; } else { for ( unsigned i = <NUM_LIT> ; i !=


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) : LLVMTargetMachine ( T , <STR_LIT> , TT , CPU , FS , Options , RM , CM , OL )

, TLOF ( make_unique < <ISA_LIT>TargetObjectFile > ( ) ) , Subtarget ( TT , CPU , FS , * this ) {


<s> if ( SDValue RV = foldXorTruncShiftIntoCmp ( N , DAG ) ) return RV ; if ( Subtarget . hasCMov ( ) ) if ( SDValue RV = combineIntegerAbs ( N


<s> MachinePointerInfo PtrInfo = MachinePointerInfo :: getFixedStack ( * MF , FrameIndex ) ; MachineMemOperand * MMO = MF -> getMachineMemOperand ( PtrInfo , MachineMemOperand :: MOLoad , FrameInfo . getObjectSize ( FrameIndex ) , FrameInfo . getObjectAlign ( FrameIndex ) ) ; if ( RI . isSGPRClass ( RC ) ) { MFI -> setHasSpilledSGPRs ( ) ; assert ( DestReg != <STR_LIT> && <STR_LIT> ) ; assert ( DestReg != <STR_LIT> && DestReg != <STR_LIT> && DestReg != <STR_LIT> && <STR_LIT> ) ; const MCInstrDesc & OpDesc = get ( getSGPRSpillRestoreOpcode ( SpillSize ) ) ; if ( DestReg . isVirtual ( ) && SpillSize == <NUM_LIT> ) { MachineRegisterInfo & MRI = MF -> getRegInfo ( ) ; MRI . constrainRegClass ( DestReg , & <STR_LIT> ) ; } if ( RI . spillSGPRToVGPR ( ) ) FrameInfo . setStackID ( FrameIndex , TargetStackID :: SGPRSpill ) ; BuildMI ( MBB , MI , DL , OpDesc , DestReg ) . addFrameIndex ( FrameIndex ) . addMemOperand ( MMO ) . addReg ( MFI -> getStackPtrOffsetReg ( ) , RegState :: Implicit ) ; return ; } unsigned Opcode = RI . hasAGPRs ( RC ) ? getAGPRSpillRestoreOpcode ( SpillSize ) :

getVGPRSpillRestoreOpcode ( SpillSize ) ;


<s> if ( ! InsertCacheInv ) return false ; bool Changed = false ; if ( ( AddrSpace & <STR_LIT> ) != <STR_LIT> ) { switch ( Scope ) { case <STR_LIT> : case <STR_LIT> : break ; case <STR_LIT>


<s> register union long_double_long ldl ; ldl . ld = ld ; if ( ! ldl . l . upper && ! ldl . l . middle && ! ldl . l . lower ) return <NUM_LIT> ; exp = EXPX ( ldl ) - EXCESSX + EXCESSD ; if ( exp >= EXPDMASK ) exp = EXPDMASK - <NUM_LIT> ; dl . l . upper = SIGNX ( ldl ) ; dl . l . upper |= exp << ( <NUM_LIT> - ( EXPDBITS + <NUM_LIT> ) ) ; dl . l . upper |= ( ldl . l . middle & MANTXMASK ) >> ( EXPDBITS + <NUM_LIT> - <NUM_LIT> ) ; dl . l . lower = ( ldl . l . middle & MANTXMASK ) << ( <NUM_LIT> - ( EXPDBITS + <NUM_LIT> - <NUM_LIT> ) ) ; dl . l . lower |= ldl . l . lower >> ( EXPDBITS + <NUM_LIT> - <NUM_LIT> ) ; return dl .


<s> raw_svector_ostream OS ( Str ) ; PrintDebugValueComment ( MI , OS ) ; return ; } MCInst TmpInst0 ; MCInstLowering . Lower (


<s> if ( Subtarget -> hasNEON ( ) ) { if ( VT == <STR_LIT> ) return <STR_LIT> ; else if ( VT == <STR_LIT> ) return <STR_LIT> ; } return TargetLowering :: getRegClassFor ( VT


<s> EVT PTy = getPointerTy ( ) ; unsigned EntrySize = DAG . getMachineFunction ( ) . getJumpTableInfo ( ) -> getEntrySize ( * getDataLayout ( ) ) ; Index = DAG . getNode ( <STR_LIT> , DL , PTy , Index , DAG . getConstant ( EntrySize , PTy ) ) ; SDValue Addr = DAG . getNode ( <STR_LIT> , DL , PTy , Index , Table ) ; EVT MemVT = EVT :: getIntegerVT ( * DAG . getContext ( ) , EntrySize * <NUM_LIT> ) ; Addr = DAG . getExtLoad ( <STR_LIT> , DL , PTy , Chain , Addr , MachinePointerInfo :: getJumpTable ( ) , MemVT , false , false , <NUM_LIT> ) ; Chain = Addr . getValue ( <NUM_LIT> ) ; if ( ( getTargetMachine ( ) . getRelocationModel ( ) == Reloc :: PIC_ ) || Subtarget . isABI_N64


<s> static const uint16_t ReservedCPURegs [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; BitVector Reserved ( getNumRegs ( ) ) ; typedef TargetRegisterClass :: iterator RegIter ; for ( unsigned I = <NUM_LIT> ; I < array_lengthof ( ReservedCPURegs ) ; ++ I ) Reserved


<s> else if ( MEP_NONGENERAL_CLASS ( rclass ) && ( mep_nonregister ( x ) || mep_nongeneral_reg ( x ) ) ) rv = GENERAL_REGS ; fprintf ( stderr , <STR_LIT> , reg_class_names [ rv ] ) ; return ( enum reg_class ) rv


<s> SmallPtrSet < MachineInstr * , <NUM_LIT> > FalseLanesZero ; SmallPtrSet < MachineInstr * , <NUM_LIT> > Predicated ; MachineBasicBlock * Header = ML . getHeader ( ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; for ( auto & MI : * Header ) { if ( ! shouldInspect ( MI ) ) continue ; if ( isVCTP ( & MI ) || isVPTOpcode ( MI . getOpcode ( ) ) ) continue ; bool isPredicated = isVectorPredicated ( & MI ) ; bool retainsOrReduces = retainsPreviousHalfElement ( MI ) || isHorizontalReduction ( MI ) ; if ( isPredicated ) Predicated . insert ( & MI ) ; if ( producesFalseLanesZero ( MI , QPRs , RDA , FalseLanesZero ) ) FalseLanesZero . insert ( & MI ) ; else if ( MI . getNumDefs ( ) == <NUM_LIT> ) continue ; else if ( ! isPredicated && retainsOrReduces ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << MI ) ; return false ; } else if ( ! isPredicated && MI . getOpcode ( ) != <STR_LIT> ) FalseLanesUnknown . insert ( & MI ) ; } LLVM_DEBUG ( { dbgs ( ) << <STR_LIT> ; for ( auto * I : Predicated ) dbgs ( ) << <STR_LIT> << *


<s> SDValue Input ; auto isSExtOfVecExtract = [ & ] ( SDValue Op ) -> bool { if ( ! Op ) return false ; if ( Op . getOpcode ( ) != <STR_LIT> && Op . getOpcode ( ) != <STR_LIT> ) return false ; SDValue Extract = Op . getOperand ( <NUM_LIT> ) ; if ( Extract . getOpcode ( ) == <STR_LIT> ) Extract = Extract . getOperand ( <NUM_LIT> ) ; if ( Extract . getOpcode ( ) != <STR_LIT> ) return false ; ConstantSDNode * ExtOp = dyn_cast < ConstantSDNode > ( Extract . getOperand ( <NUM_LIT> ) ) ; if ( ! ExtOp ) return false ; Index = ExtOp -> getZExtValue ( ) ; if ( Input && Input != Extract . getOperand ( <NUM_LIT> ) ) return false ; if ( ! Input ) Input =


<s> bool restoreCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo * TRI ) const override { return true


<s> void <ISA_LIT>PassConfig :: addCodeGenPrepare ( ) { addPass ( createLowerSwitchPass ( ) ) ; TargetPassConfig :: addCodeGenPrepare ( )


<s> bool isUnaryOperator ( const InfixCalculatorTok Op ) { return Op == IC_NEG || Op


<s> return & InstrInfo . getRegisterInfo (


<s> unsigned AssignedReg = FuncInfo . ValueMap [ I ] ; const TargetRegisterClass * RC = ( AssignedReg ? MRI . getRegClass ( AssignedReg ) : ( DestVT == <STR_LIT> ? & <STR_LIT> : & <STR_LIT> ) ) ; unsigned ResultReg = createResultReg ( RC ) ; if ( ! <ISA_LIT>EmitIntExt ( SrcVT , SrcReg , DestVT , ResultReg , IsZExt ) ) return false ; updateValueMap ( I , ResultReg ) ; return true


<s> assert ( ( SplatBits & ~ <NUM_LIT> ) == <NUM_LIT> && <STR_LIT> ) ; OpCmode = <NUM_LIT> ; Imm = SplatBits ; VT = is128Bits ? <STR_LIT> : <STR_LIT> ; break ; case <NUM_LIT> : VT = is128Bits ? <STR_LIT> : <STR_LIT> ; if ( ( SplatBits & ~ <NUM_LIT> ) == <NUM_LIT> ) { OpCmode = <NUM_LIT> ; Imm = SplatBits ; break ; } if ( ( SplatBits & ~ <NUM_LIT> ) == <NUM_LIT> ) { OpCmode = <NUM_LIT> ; Imm = SplatBits >> <NUM_LIT> ; break ; } return SDValue ( ) ; case <NUM_LIT> : VT = is128Bits ? <STR_LIT> : <STR_LIT> ; if ( ( SplatBits & ~ <NUM_LIT> ) == <NUM_LIT> ) { OpCmode = <NUM_LIT> ; Imm = SplatBits ; break ; } if ( ( SplatBits & ~ <NUM_LIT> ) == <NUM_LIT> ) { OpCmode = <NUM_LIT> ; Imm = SplatBits >> <NUM_LIT> ; break ; } if ( ( SplatBits & ~ <NUM_LIT> ) == <NUM_LIT> ) { OpCmode = <NUM_LIT> ; Imm = SplatBits >> <NUM_LIT> ; break ; } if ( ( SplatBits & ~ <NUM_LIT> ) == <NUM_LIT> ) { OpCmode = <NUM_LIT> ; Imm = SplatBits >> <NUM_LIT> ; break ; } if ( type == OtherModImm ) return SDValue ( ) ; if ( ( SplatBits & ~ <NUM_LIT> ) == <NUM_LIT> && ( ( SplatBits | SplatUndef ) & <NUM_LIT> ) == <NUM_LIT> ) { OpCmode = <NUM_LIT> ; Imm = SplatBits >> <NUM_LIT> ; break ; } if ( ( SplatBits & ~ <NUM_LIT> ) == <NUM_LIT> && ( ( SplatBits | SplatUndef ) & <NUM_LIT> ) == <NUM_LIT> ) { OpCmode = <NUM_LIT> ; Imm = SplatBits >> <NUM_LIT> ; break ; } return SDValue ( ) ; case <NUM_LIT> : { if ( type != VMOVModImm ) return SDValue ( ) ; uint64_t BitMask = <NUM_LIT> ; uint64_t Val = <NUM_LIT> ; unsigned ImmMask = <NUM_LIT> ; Imm = <NUM_LIT> ; for ( int ByteNum = <NUM_LIT> ; ByteNum < <NUM_LIT> ; ++ ByteNum ) { if ( ( ( SplatBits | SplatUndef ) & BitMask ) == BitMask ) { Val |=


<s> addPass ( createR600EmitClauseMarkers ( * TM ) ) ; addPass ( createR600ExpandSpecialInstrsPass ( * TM ) ) ; addPass ( & FinalizeMachineBundlesID ) ; addPass ( createR600Packetizer ( * TM ) ) ; addPass ( createR600ControlFlowFinalizer ( * TM ) ) ; } else { addPass ( create<ISA_LIT>LowerControlFlowPass ( * TM )


<s> static void matchLDPSTPAddrMode ( Register Root , Register & Base , int & Offset , MachineRegisterInfo & MRI ) { Base =


<s> if ( In . isBranch ( ) ) for ( auto & O : In . operands ( ) ) if ( O . isGlobal ( ) || O . isSymbol ( ) ) return true ; const MCInstrDesc & D = In . getDesc ( ) ; if ( ! D . getImplicitDefs ( ) && ! D . getImplicitUses


<s> if ( CSKY_FUNCTION_TYPE ( cfun -> machine -> func_type ) == CSKY_FT_UNKNOWN ) { unsigned long type = CSKY_FT_UNKNOWN ; tree a ; tree attr ; gcc_assert ( TREE_CODE ( current_function_decl ) == FUNCTION_DECL ) ; attr = DECL_ATTRIBUTES ( current_function_decl ) ; a = lookup_attribute ( <STR_LIT> , attr ) ; if ( a != NULL_TREE ) type |= CSKY_FT_NAKED ; a = lookup_attribute ( <STR_LIT> , attr ) ; if ( a == NULL_TREE ) a = lookup_attribute ( <STR_LIT> , attr ) ; if ( a == NULL_TREE ) type |= CSKY_FT_NORMAL ; else type |= get_csky_isr_type ( TREE_VALUE ( a ) ) ; cfun -> machine ->


<s> return <STR_LIT> ; case SUBB : return <STR_LIT> ; case AND : return <STR_LIT> ; case OR : return <STR_LIT> ; case XOR : return <STR_LIT> ; case SHL : return <STR_LIT> ; case SRL : return <STR_LIT>


<s> virtual const TargetRegisterInfo * getRegisterInfo ( ) const { return & InstrInfo .


<s> RegDU . setUnallocatableRegs ( * MBB . getParent ( ) ) ; if ( HasMultipleSuccs ) { IM . reset ( new LoadFromStackOrConst ( ) ) ; } else { const MachineFrameInfo * MFI = MBB . getParent ( ) -> getFrameInfo ( ) ; IM . reset ( new MemDefsUses ( * TM . getDataLayout ( ) , MFI ) ) ; } if ( ! searchRange ( MBB , SuccBB -> begin ( ) , SuccBB -> end ( ) , RegDU ,


<s> Triple TheTriple ( TT ) ; if ( TheTriple . isOSDarwin ( ) || TheTriple . getEnvironment ( ) == Triple :: MachO ) return new Darwin<ISA_LIT>_64AsmBackend ( T ) ; if ( TheTriple . isOSWindows ( ) ) return

new Windows<ISA_LIT>AsmBackend ( T , true ) ;


<s> if ( TARGET_DIRECT_MOVE && ( ( mode == SDmode ) || ( TARGET_POWERPC64 && size == <NUM_LIT> ) ) && ( ( to_type == GPR_REG_TYPE && from_type == VSX_REG_TYPE ) || ( to_type == VSX_REG_TYPE && from_type == GPR_REG_TYPE ) ) ) return true ; else if ( TARGET_MFPGPR && TARGET_POWERPC64 && size == <NUM_LIT> && ( ( to_type == GPR_REG_TYPE && from_type == FPR_REG_TYPE ) || ( to_type == FPR_REG_TYPE && from_type == GPR_REG_TYPE ) ) ) return true ; else if ( ( size == <NUM_LIT> || ( TARGET_POWERPC64 && size == <NUM_LIT> ) ) && ( ( to_type == GPR_REG_TYPE && from_type == SPR_REG_TYPE ) ||

( to_type == SPR_REG_TYPE && from_type == GPR_REG_TYPE ) ) ) return true ;


<s> static DecodeStatus DecodeBranchTarget21 ( MCInst & Inst , unsigned Offset , uint64_t Address , const MCDisassembler * Decoder ) { int32_t BranchOffset = SignExtend32 < <NUM_LIT> > ( Offset


<s> TargetLowering :: AtomicExpansionKind <ISA_LIT>TargetLowering :: shouldExpandAtomicLoadInIR ( LoadInst * LI ) const { return LI -> getType ( ) -> getPrimitiveSizeInBits ( ) > <NUM_LIT> ? AtomicExpansionKind :: LLSC


<s> static std :: unique_ptr < <ISA_LIT>Operand > CreateTokenWithStringCopy ( StringRef Str , SMLoc S , bool Is<ISA_LIT>64 ) { void * Mem = :: operator new ( sizeof ( <ISA_LIT>Operand ) + Str . size ( ) ) ; std :: unique_ptr < <ISA_LIT>Operand > Op ( new ( Mem ) <ISA_LIT>Operand ( Token ) ) ; Op -> Tok . Data = reinterpret_cast < const char * > ( Op . get ( ) + <NUM_LIT> ) ; Op -> Tok . Length = Str . size ( ) ; std :: memcpy ( const_cast < char * > ( Op -> Tok . Data ) , Str . data ( ) , Str . size ( ) ) ; Op -> StartLoc


<s> unsigned Addr = Saved [ <NUM_LIT> ] . getOperand ( <NUM_LIT> ) . getReg ( ) ; int64_t Pred = Saved [ <NUM_LIT> ] . getOperand ( <NUM_LIT> ) . getImm ( ) ; assert ( ( <STR_LIT> == Addr ) && <STR_LIT> ) ; Out . EmitBundleLock ( false ) ; Out . EmitInstruction ( Saved [ <NUM_LIT> ] , STI ) ; EmitBICMask ( STI , Out , Addr , Pred


<s> OutStreamer -> EmitSymbolAttribute ( Stub . second . getPointer ( ) , MCSA_IndirectSymbol ) ; const char HltInsts [ ] = <STR_LIT> ; OutStreamer -> EmitBytes ( StringRef ( HltInsts , <NUM_LIT> ) ) ; } Stubs . clear ( ) ; OutStreamer -> AddBlankLine ( ) ; } Stubs = MMIMacho . GetGVStubList ( ) ; if ( ! Stubs . empty ( ) ) { MCSection * TheSection = OutContext . getMachOSection ( <STR_LIT> , <STR_LIT> , MachO :: S_NON_LAZY_SYMBOL_POINTERS , SectionKind :: getMetadata ( ) ) ; OutStreamer -> SwitchSection ( TheSection ) ; for ( auto & Stub : Stubs ) emitNonLazySymbolPointer ( * OutStreamer , Stub . first , Stub . second ) ; Stubs . clear ( ) ; OutStreamer -> AddBlankLine ( ) ; } Stubs = MMIMacho . GetHiddenGVStubList ( ) ; if ( ! Stubs . empty ( ) ) { MCSection * TheSection = OutContext . getMachOSection ( <STR_LIT> , <STR_LIT> , MachO :: S_NON_LAZY_SYMBOL_POINTERS , SectionKind :: getMetadata ( ) ) ; OutStreamer -> SwitchSection ( TheSection ) ; for ( auto & Stub : Stubs ) emitNonLazySymbolPointer ( * OutStreamer , Stub . first


<s> unsigned NumLaneElems = NumElems / NumLanes ; if ( NumLaneElems != <NUM_LIT> && NumLaneElems != <NUM_LIT> ) return false ; unsigned EltSize = VT . getVectorElementType ( ) . getSizeInBits ( ) ; bool symetricMaskRequired = ( VT . getSizeInBits ( ) >= <NUM_LIT> ) && ( EltSize == <NUM_LIT> ) ; SmallVector < int , <NUM_LIT> > MaskVal ( NumLaneElems , - <NUM_LIT> ) ; unsigned HalfLaneElems = NumLaneElems / <NUM_LIT> ; for ( unsigned l = <NUM_LIT> ; l != NumElems ; l += NumLaneElems ) { for ( unsigned i = <NUM_LIT> ; i != NumLaneElems ; ++ i ) { int Idx = Mask [ i + l ] ; unsigned RngStart = l + ( ( Commuted == ( i < HalfLaneElems ) ) ? NumElems : <NUM_LIT> ) ; if ( ! isUndefOrInRange ( Idx , RngStart , RngStart + NumLaneElems ) ) return false ; if ( ! symetricMaskRequired ||


<s> const DebugLoc & DL = MI . getDebugLoc ( ) ; MachineBasicBlock :: iterator I ( & MI ) ; unsigned PhiReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; unsigned InitReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( MBB , I , DL , TII -> get ( TargetOpcode :: IMPLICIT_DEF ) , InitReg ) ; auto InsPt = loadM0FromVGPR ( TII , MBB , MI , InitReg , PhiReg , Offset , UseGPRIdxMode , true ) ; MachineBasicBlock * LoopBB = InsPt -> getParent ( ) ; if ( UseGPRIdxMode ) { BuildMI ( * LoopBB , InsPt , DL , TII -> get ( <STR_LIT> ) , Dst ) . addReg ( SrcReg , RegState :: Undef , SubReg ) . addReg ( SrcReg , RegState :: Implicit ) . addReg ( <STR_LIT> , RegState :: Implicit ) ; BuildMI ( * LoopBB , InsPt , DL , TII -> get ( <STR_LIT> ) ) ; } else { BuildMI ( * LoopBB , InsPt , DL , TII -> get ( <STR_LIT> ) , Dst ) . addReg ( SrcReg , RegState :: Undef , SubReg ) . addReg ( SrcReg ,


<s> MachineIRBuilder & B = Helper . MIRBuilder ; MachineRegisterInfo & MRI = * B . getMRI ( ) ; switch ( MI . getOpcode ( ) ) { case TargetOpcode :: G_ADDRSPACE_CAST : return legalizeAddrSpaceCast ( MI , MRI , B ) ; case TargetOpcode :: G_FRINT : return legalizeFrint ( MI , MRI , B ) ; case TargetOpcode :: G_FCEIL : return legalizeFceil ( MI , MRI , B ) ; case TargetOpcode :: G_FREM : return legalizeFrem ( MI , MRI , B ) ; case TargetOpcode :: G_INTRIN<ISA_LIT>C_TRUNC : return legalizeIntrinsicTrunc ( MI , MRI , B ) ; case TargetOpcode :: G_<ISA_LIT>TOFP : return legalizeITOFP ( MI , MRI , B , true ) ; case TargetOpcode :: G_UITOFP : return legalizeITOFP ( MI , MRI , B , false ) ; case TargetOpcode :: G_FPTO<ISA_LIT> : return legalizeFPTOI ( MI , MRI , B , true ) ; case TargetOpcode :: G_FPTOUI : return legalizeFPTOI ( MI , MRI , B , false ) ; case TargetOpcode :: G_FMINNUM : case TargetOpcode :: G_FMAXNUM : case TargetOpcode :: G_FMINNUM_IEEE : case TargetOpcode :: G_FMAXNUM_IEEE : return legalizeMinNumMaxNum ( Helper , MI ) ; case TargetOpcode :: G_EXTRACT_VECTOR_ELT : return legalizeExtractVectorElt ( MI , MRI , B ) ; case TargetOpcode :: G_INSERT_VECTOR_ELT : return legalizeInsertVectorElt ( MI , MRI , B ) ; case TargetOpcode :: G_SHUFFLE_VECTOR : return legalizeShuffleVector ( MI , MRI , B ) ; case TargetOpcode :: G_F<ISA_LIT>N : case TargetOpcode :: G_FCOS : return legalizeSinCos ( MI , MRI , B ) ; case TargetOpcode :: G_GLOBAL_VALUE : return legalizeGlobalValue ( MI , MRI , B ) ; case TargetOpcode :: G_LOAD : case TargetOpcode :: G_SEXTLOAD : case TargetOpcode :: G_ZEXTLOAD : return legalizeLoad ( Helper , MI ) ; case TargetOpcode


<s> Res = tryParseOptionalShiftExtend ( ExtOpnd ) ; if ( Res != MatchOperand_Success ) return Res ; auto Ext = static_cast < <ISA_LIT>Operand * > ( ExtOpnd . back ( ) . get ( ) ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateVectorReg ( RegNum , RegKind :: SVEDataVector , ElementWidth , S , Ext -> getEndLoc ( ) , getContext ( ) , Ext -> getShiftExtendType (

) , Ext -> getShiftExtendAmount ( ) , Ext -> hasShiftExtendAmount ( ) ) ) ;


<s> for ( MachineFunction :: iterator I = MF . begin ( ) , E = MF . end ( ) ; I != E ; ) { MachineBasicBlock & B = * I ++ ; Changed |= processBlock (


<s> static DecodeStatus DecodeShiftRight8Imm ( MCInst & Inst , unsigned Val , uint64_t Address , const void


<s> SDValue Chain = N -> getOperand ( <NUM_LIT> ) ; SDValue Ops [ ] = { N -> getOperand ( <NUM_LIT> ) , Chain } ; const EVT ResTys [ ] = { <STR_LIT> , <STR_LIT> } ; SDNode * Ld = CurDAG -> getMachineNode ( Opc , dl , ResTys , Ops ) ; SDValue SuperReg = SDValue ( Ld , <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i < NumVecs ; ++ i ) ReplaceUses ( SDValue ( N , i ) , CurDAG -> getTargetExtractSubreg ( SubRegIdx + i , dl , VT , SuperReg ) ) ; ReplaceUses ( SDValue ( N , NumVecs ) , SDValue ( Ld , <NUM_LIT> ) ) ; if ( auto * MemIntr = dyn_cast < MemIntrinsicSDNode > ( N ) ) { MachineMemOperand * MemOp = MemIntr -> getMemOperand


<s> rtx arm_gen_compare_reg ( enum rtx_code code , rtx x , rtx y , rtx scratch ) { machine_mode mode ; rtx cc_reg ; int dimode_comparison = GET_MODE ( x ) == DImode || GET_MODE ( y ) == DImode ; if ( dimode_comparison && ! REG_P ( x ) ) x = force_reg ( DImode , x ) ; mode = SELECT_CC_MODE ( code , x , y ) ; cc_reg = gen_rtx_REG ( mode , CC_REGNUM ) ; if ( dimode_comparison && mode != CC_CZmode ) { rtx clobber , set ; if ( mode == CC_Zmode && y != const0_rtx ) { gcc_assert ( ! reload_completed ) ; x = expand_binop ( DImode , xor_optab , x , y , NULL_RTX , <NUM_LIT> , OPTAB_WIDEN ) ; y = const0_rtx ; } if ( reload_completed ) gcc_assert ( scratch != NULL && GET_MODE ( scratch ) == SImode ) ; else scratch = gen_rtx_SCRATCH ( SImode ) ; clobber = gen_rtx_CLOBBER ( VOIDmode , scratch ) ; set = gen_rtx_SET ( VOIDmode , cc_reg , gen_rtx_COMPARE ( mode , x , y ) ) ; emit_insn ( gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( <NUM_LIT> , set


<s> for ( Function :: const_arg_iterator I = F -> arg_begin ( ) , E = F -> arg_end ( ) ; I != E ; ++ I ) if ( I -> hasNestAttr ( ) ) report_fatal_error ( <STR_LIT> <STR_LIT> ) ; } const TargetRegisterClass * AddrRegClass = getRegClassFor ( Has64BitPointers ? <STR_LIT> : <STR_LIT> ) ; unsigned Vreg = MRI . createVirtualRegister ( AddrRegClass ) ; Chain = DAG . getCopyToReg ( Chain , dl , Vreg , Size ) ; SDValue Value = DAG . getNode ( <STR_LIT> , dl , SPTy , Chain , DAG . getRegister ( Vreg , SPTy ) ) ; SDValue Ops1 [ <NUM_LIT> ] = { Value , Chain } ; return DAG . getMergeValues ( Ops1 , <NUM_LIT> , dl ) ; } else { SDValue Flag ; unsigned Reg = ( Has64BitPointers ? <STR_LIT> : <STR_LIT> ) ; Chain = DAG . getCopyToReg ( Chain , dl , Reg , Size , Flag ) ; Flag = Chain . getValue (


<s> SDValue DstPtr = Op . getOperand ( <NUM_LIT> ) ; SDValue SrcPtr = Op . getOperand ( <NUM_LIT> ) ; const Value * DstSV = cast < SrcValueSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getValue ( ) ; const Value * SrcSV = cast < SrcValueSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getValue ( ) ; SDLoc DL ( Op ) ; return DAG . getMemcpy ( Chain , DL , DstPtr , SrcPtr , DAG . getIntPtrConstant ( Subtarget -> has64BitPointers ( ) ? <NUM_LIT> : <NUM_LIT> )

, Subtarget -> has64BitPointers ( ) ? <NUM_LIT> : <NUM_LIT> , false , false , MachinePointerInfo ( DstSV ) , MachinePointerInfo ( SrcSV ) ) ;


<s> inline SDValue getI64Imm ( uint64_t Imm ,


<s> RegisterTarget < Triple :: tlcs900 > X ( The<ISA_LIT>Target , <STR_LIT> ,


<s> unsigned NumElems = HwLen / ( ElemTy .


<s> APInt Mask = APInt :: getLowBitsSet ( InSVT . getSizeInBits ( ) , OutSVT . getSizeInBits ( ) ) ; SDValue MaskVal = DAG . getConstant ( Mask , DL , InVT ) ; for ( auto & Reg : Regs ) Reg = DAG . getNode ( <STR_LIT> , DL , InVT , MaskVal , Reg ) ; MVT UnpackedVT , PackedVT ; if ( OutSVT == <STR_LIT> ) { UnpackedVT = <STR_LIT> ; PackedVT = <STR_LIT> ; } else { UnpackedVT = <STR_LIT> ; PackedVT = <STR_LIT> ; } auto RegNum = Regs . size ( ) ; for ( unsigned j = <NUM_LIT> , e = InSVT . getSizeInBits ( ) / OutSVT . getSizeInBits ( ) ; j < e ; j *= <NUM_LIT> , RegNum /= <NUM_LIT> ) { for ( unsigned i = <NUM_LIT> ; i < RegNum ; i ++ ) Regs [ i ] = DAG . getBitcast ( UnpackedVT , Regs [ i ] ) ; for ( unsigned i = <NUM_LIT> ; i < RegNum / <NUM_LIT> ; i ++ ) Regs [ i ] = DAG . getNode ( <STR_LIT> , DL , PackedVT , Regs [ i * <NUM_LIT> ] , Regs [ i *


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; const MCConstantExpr * MCE = cast < MCConstantExpr > ( getImm ( )


<s> else { * total = COSTS_N_INSNS ( <NUM_LIT> ) ; return true ; } return false ; case CONST : case LABEL_REF : case SYMBOL_REF : * total = COSTS_N_INSNS ( <NUM_LIT> ) ; return true ; case CONST_DOUBLE : * total = COSTS_N_INSNS ( <NUM_LIT> ) ; return true ; case HIGH : * total = <NUM_LIT> ; return true ; case MEM : if ( outer_code == ZERO_EXTEND || outer_code == SIGN_EXTEND ) * total = COSTS_N_INSNS ( <NUM_LIT> ) ; else * total = COSTS_N_INSNS ( <NUM_LIT> ) ; return true ; case PLUS : if ( GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == MULT && cint_248_operand ( XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) , VOIDmode ) ) { * total = ( rtx_cost ( XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) , mode , ( enum rtx_code ) outer_code , opno , speed ) + rtx_cost ( XEXP ( x , <NUM_LIT> ) , mode , ( enum rtx_code ) outer_code , opno , speed ) + COSTS_N_INSNS ( <NUM_LIT> ) ) ; return true ; } return false ; case MULT : * total = COSTS_N_INSNS ( <NUM_LIT> ) ; return false ; case SIGN_EXTEND : case ZERO_EXTEND : if ( outer_code == MULT ) * total = <NUM_LIT> ; else * total = COSTS_N_INSNS ( <NUM_LIT> ) ; return false ; case DIV : case UDIV : case MOD : case UMOD : * total = COSTS_N_INSNS ( <NUM_LIT> ) ; return false ; case UNSPEC : case UNSPEC_VOLATILE : { int num = XINT ( x , <NUM_LIT> ) ; if ( num <= TILEPRO_LAST_LATENCY_1_INSN ) * total = COSTS_N_INSNS ( <NUM_LIT> ) ; else if ( num <= TILEPRO_LAST_LATENCY_2_INSN ) * total = COSTS_N_INSNS ( <NUM_LIT> ) ; else if ( num > TILEPRO_LAST_LATENCY_INSN ) { if ( outer_code == PLUS )


<s> static inline AddrOpc getAM3Op ( unsigned AM3Opc


<s> MFI -> setReturnAddressIsTaken ( true ) ; EVT VT = Op . getValueType ( ) ; SDLoc DL ( Op ) ; unsigned Depth = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; if ( Depth ) { SDValue FrameAddr = LowerFRAMEADDR ( Op , DAG ) ; SDValue Offset = DAG . getConstant ( <NUM_LIT> , getPointerTy ( ) ) ; return DAG . getLoad ( VT , DL , DAG . getEntryNode ( ) , DAG . getNode ( <STR_LIT> , DL , VT , FrameAddr , Offset ) , MachinePointerInfo ( ) , false , false , false , <NUM_LIT> ) ; } unsigned Reg = MF . addLiveIn (


<s> return TargetTriple . isOSBinFormatELF (


<s> if ( MemVT . isPow2VectorType ( ) ) return SDValue ( ) ; if ( NumElements == <NUM_LIT> ) return WidenVectorLoad ( Op , DAG ) ; return SplitVectorLoad ( Op , DAG ) ; } } if ( AS == <ISA_LIT>AS :: CONSTANT_ADDRESS || AS == <ISA_LIT>AS :: CONSTANT_ADDRESS_32BIT || AS == <ISA_LIT>AS :: GLOBAL_ADDRESS || AS == <ISA_LIT>AS :: FLAT_ADDRESS ) { if ( NumElements > <NUM_LIT> ) return SplitVectorLoad ( Op , DAG ) ; if ( NumElements == <NUM_LIT> && ! Subtarget -> hasDwordx3LoadStores ( ) ) return WidenVectorLoad ( Op , DAG ) ; return SDValue ( ) ; } if ( AS == <ISA_LIT>AS :: PRIVATE_ADDRESS ) { switch ( Subtarget -> getMaxPrivateElementSize ( ) ) { case <NUM_LIT> : return scalarizeVectorLoad ( Load , DAG ) ; case <NUM_LIT> : if ( NumElements > <NUM_LIT> ) return SplitVectorLoad ( Op , DAG ) ; return SDValue ( ) ; case <NUM_LIT> : if ( NumElements > <NUM_LIT> ) return SplitVectorLoad ( Op , DAG ) ; if ( NumElements == <NUM_LIT> && ! Subtarget -> hasDwordx3LoadStores ( ) ) return WidenVectorLoad ( Op , DAG ) ; return SDValue ( ) ; default : llvm_unreachable ( <STR_LIT> ) ; } } else if ( AS == <ISA_LIT>AS :: LOCAL_ADDRESS ) { if ( Subtarget -> useDS128 ( ) && Load -> getAlignment ( ) >= <NUM_LIT> && MemVT . getStoreSize ( ) == <NUM_LIT> ) return SDValue ( ) ; if ( NumElements > <NUM_LIT> ) return SplitVectorLoad ( Op , DAG ) ; if ( Subtarget -> getGeneration ( ) == <ISA_LIT>Subtarget :: SOUTHERN_ISLANDS && NumElements == <NUM_LIT> && MemVT . getStoreSize ( ) == <NUM_LIT> && Load -> getAlignment ( ) < <NUM_LIT> ) { return SplitVectorLoad ( Op , DAG ) ; } } return SDValue


<s> bool NegateCC ; tie ( Chain , NegateCC ) = ConvertSETCC ( op , DAG ) ; if ( NegateCC ) Chain = DAG . getNode ( <STR_LIT> , op . getDebugLoc ( ) , <STR_LIT>

, Chain , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ;


<s> if ( NewC . Op0 . getValueType ( ) != <STR_LIT> || NewC . CCMask == <STR_LIT> || NewC . CCMask == <STR_LIT> || NewC . ICmpType == <STR_LIT> ) return ; if ( NewC . CCMask == <STR_LIT> || NewC . CCMask == <STR_LIT> ) { if ( CmpVal == uint64_t ( - <NUM_LIT> ) ) return ; CmpVal += <NUM_LIT> ; NewC . CCMask ^= <STR_LIT> ; } MaskVal = - ( CmpVal & - CmpVal ) ; NewC . ICmpType = <STR_LIT> ; } if ( ! MaskVal ) return ; unsigned BitSize = NewC . Op0 . getValueType ( ) . getSizeInBits ( ) ; unsigned NewCCMask , ShiftVal ; if ( NewC . ICmpType != <STR_LIT> && NewC . Op0 . getOpcode ( ) == <STR_LIT> && isSimpleShift ( NewC . Op0 , ShiftVal ) && ( NewCCMask = getTestUnderMaskCond ( BitSize , NewC . CCMask , MaskVal >> ShiftVal , CmpVal >> ShiftVal , <STR_LIT> ) ) ) { NewC . Op0 = NewC . Op0 . getOperand ( <NUM_LIT> ) ; MaskVal >>= ShiftVal ; } else if ( NewC . ICmpType != <STR_LIT> && NewC . Op0 . getOpcode ( ) == <STR_LIT> && isSimpleShift ( NewC . Op0 , ShiftVal ) && ( NewCCMask = getTestUnderMaskCond ( BitSize , NewC . CCMask , MaskVal << ShiftVal , CmpVal << ShiftVal , <STR_LIT> ) ) ) { NewC . Op0 = NewC . Op0 . getOperand ( <NUM_LIT> ) ; MaskVal <<=


<s> static unsigned computeLinkageSize ( const <ISA_LIT>Subtarget & STI ) { if ( STI . isAIXABI ( ) || STI . is<ISA_LIT>64 ( ) ) return ( STI . isELFv2ABI ( ) ? <NUM_LIT> : <NUM_LIT> ) * ( STI . is<ISA_LIT>64 ( ) ? <NUM_LIT> : <NUM_LIT> ) ; return <NUM_LIT>


<s> if ( InvokePAL . hasAttributes ( i ) ) { AttrBuilder B ( InvokePAL , i ) ; AttributesVec . push_back ( AttributeList :: get ( C , i + <NUM_LIT> , B ) ) ; } } if ( InvokePAL . hasAttributes ( AttributeList :: ReturnIndex ) ) AttributesVec . push_back ( AttributeList :: get ( C , InvokePAL . getRetAttributes ( ) ) ) ; if ( InvokePAL . hasAttributes ( AttributeList :: FunctionIndex ) ) AttributesVec . push_back ( AttributeList :: get ( C , InvokePAL . getFnAttributes ( ) ) ) ; AttributeList NewCallPAL = AttributeList :: get ( C , AttributesVec ) ; NewCall -> setAttributes ( NewCallPAL ) ; CI -> replaceAllUsesWith


<s> TripCountPattern ( Instruction * P , Value * TC , FixedVectorType * VT ) : Predicate ( P ) , TripCount ( TC )


<s> assert ( Scale < <NUM_LIT> && <STR_LIT> ) ; SDLoc DL ( N ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; SDValue Chain = N -> getOperand ( <NUM_LIT> ) ; SDValue Base , Offset ; unsigned Opc ; std :: tie ( Opc , Base , Offset ) = findAddrModeSVELoadStore ( N , Opc_rr , Opc_ri , N -> getOperand ( <NUM_LIT> ) , CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) , Scale ) ; SDValue Ops [ ] = { N -> getOperand ( <NUM_LIT> ) , Base , Offset , Chain } ; const EVT ResTys [ ] = { <STR_LIT> , <STR_LIT> } ; SDNode * Load = CurDAG -> getMachineNode ( Opc , DL , ResTys , Ops ) ; SDValue SuperReg = SDValue ( Load , <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i < NumVecs ; ++ i ) ReplaceUses ( SDValue ( N , i ) , CurDAG -> getTargetExtractSubreg ( <STR_LIT> + i , DL , VT , SuperReg ) ) ; unsigned ChainIdx = NumVecs ; ReplaceUses ( SDValue ( N , ChainIdx ) , SDValue ( Load , <NUM_LIT> ) ) ; CurDAG -> RemoveDeadNode ( N )


<s> const Function & F = MF . getFunction ( ) ; unsigned StackProbeSize = <NUM_LIT> ; if ( F . hasFnAttribute ( <STR_LIT> ) ) F . getFnAttribute ( <STR_LIT> ) . getValueAsString ( ) . getAsInteger ( <NUM_LIT> , StackProbeSize ) ; return StackSizeInBytes >= StackProbeSize


<s> bool requiresDiffExpressionRelocations ( ) const


<s> unsigned NumBytes = alignTo ( Info . TargetSize , <NUM_LIT> ) / <NUM_LIT> ; if ( Value == <NUM_LIT> ) return ; Value <<= Info . TargetOffset ; unsigned Offset = Fixup . getOffset ( ) ; assert ( Offset + NumBytes <= Data . size ( ) && <STR_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i != NumBytes ; ++ i ) Data [ Offset + i ] |= uint8_t (

( Value >> ( i * <NUM_LIT> ) ) & <NUM_LIT> ) ;


<s> if ( I != EnclosedInstrs . end ( ) ) { if ( I -> second != C . getID ( ) ) C . setAllIllegal ( ) ; return ; } EnclosedInstrs [ MI ] = C . getID ( ) ; C . addInstruction ( MI ) ; for ( int i = <NUM_LIT> ; i != NumDomains ; ++ i ) { if ( C . isLegal ( ( RegDomain ) i ) ) { InstrConverterBase * IC = Converters . lookup ( { i , MI -> getOpcode ( ) } ) ; if ( ! IC || ! IC -> isLegal ( MI , TII ) ) C .


<s> if ( ArgFlags . isSExt ( ) ) LocInfo = CCValAssign :: SExt ; else if ( ArgFlags . isZExt ( ) ) LocInfo = CCValAssign :: ZExt ; else LocInfo = CCValAssign :: AExt ; } if ( LocVT == <STR_LIT> ) { if ( ! CC_<ISA_LIT>32 ( ValNo , ValVT , LocVT , LocInfo , ArgFlags , State ) ) return false ; } if ( LocVT == <STR_LIT>


<s> extern __inline void __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) _mm512_mask_prefetch_i32gather_ps ( __m512i index , __mmask16 mask , void * addr , int scale


<s> if ( MO . isReg ( ) || MO . isImm ( ) ) return getMachineOpValue ( MI , MO , Fixups , STI ) ; const <ISA_LIT>InstrInfo * InstrInfo = static_cast < const <ISA_LIT>InstrInfo


<s> Entry . Node = RetPtr ; Entry . Ty = PointerType :: getUnqual ( RetTy ) ; if ( ! Subtarget -> is64Bit ( ) ) Entry . isSRet = true ; Entry . isReturned = false ; Args . push_back ( Entry ) ; RetTyABI = Type :: getVoidTy ( * DAG . getContext ( ) ) ; } assert ( Op -> getNumOperands ( ) >= numArgs && <STR_LIT> ) ; for ( unsigned i = <NUM_LIT> , e = numArgs ; i != e ; ++ i ) { Chain = LowerF128_LibCallArg ( Chain , Args , Op . getOperand ( i ) , SDLoc ( Op ) , DAG ) ; } TargetLowering :: CallLoweringInfo CLI ( DAG ) ; CLI . setDebugLoc ( SDLoc ( Op ) ) . setChain ( Chain ) . setCallee ( CallingConv :: C , RetTyABI , Callee , std :: move (


<s> unsigned getReturnAddressReg ( const MachineFunction &


<s> MVT OpVT = N -> getSimpleValueType ( <NUM_LIT> ) ; bool IsI1Vector = OpVT . getVectorElementType ( ) == <STR_LIT> ; SDLoc dl ( N ) ; SDValue Vec = N -> getOperand ( <NUM_LIT> ) ; SDValue SubVec = N -> getOperand ( <NUM_LIT> ) ; uint64_t IdxVal = N -> getConstantOperandVal ( <NUM_LIT> ) ; MVT SubVecVT = SubVec . getSimpleValueType ( ) ; if ( Vec . isUndef ( ) && SubVec . isUndef ( ) ) return DAG . getUNDEF ( OpVT ) ; if ( ( Vec . isUndef ( ) || <STR_LIT> ( Vec . getNode ( ) ) ) && ( SubVec . isUndef ( ) || <STR_LIT> ( SubVec . getNode ( ) ) ) ) return getZeroVector ( OpVT , Subtarget , DAG , dl ) ; if ( <STR_LIT> ( Vec . getNode ( ) ) ) { if ( SubVec . getOpcode ( ) == <STR_LIT> && <STR_LIT> ( SubVec . getOperand ( <NUM_LIT> ) . getNode ( ) ) ) { uint64_t Idx2Val = SubVec . getConstantOperandVal ( <NUM_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , OpVT , getZeroVector ( OpVT , Subtarget , DAG , dl ) , SubVec . getOperand ( <NUM_LIT> ) , DAG . getIntPtrConstant ( IdxVal + Idx2Val , dl ) ) ; } if ( SubVec . getOpcode ( ) == <STR_LIT> && IdxVal == <NUM_LIT> && isNullConstant ( SubVec . getOperand ( <NUM_LIT> ) ) && SubVec . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) { SDValue Ins = SubVec . getOperand ( <NUM_LIT> ) ; if ( isNullConstant ( Ins . getOperand ( <NUM_LIT> ) ) && <STR_LIT> ( Ins . getOperand ( <NUM_LIT> ) . getNode ( ) ) && Ins . getOperand ( <NUM_LIT> ) . getValueSizeInBits ( ) . getFixedSize ( ) <= SubVecVT . getFixedSizeInBits ( ) ) return DAG . getNode ( <STR_LIT> , dl , OpVT , getZeroVector ( OpVT , Subtarget , DAG , dl ) , Ins . getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) ) ; } } if ( IsI1Vector )


<s> EmitInstruction ( Out , MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) ) ; EmitInstruction ( Out , MCInstBuilder ( <STR_LIT> ) . addExpr ( DoneExpr ) ) ; InstrumentMOVSBase ( <STR_LIT> , <STR_LIT> , <STR_LIT> , AccessSize ,


<s> case <STR_LIT> : case <STR_LIT> : return LowerINT_TO_FP ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerFP_TO_INT ( Op , DAG ) ; case <STR_LIT> : return LowerFCOPYSIGN ( Op , DAG ) ; case <STR_LIT> : return LowerRETURNADDR ( Op , DAG ) ; case <STR_LIT> : return LowerFRAMEADDR ( Op , DAG ) ; case <STR_LIT> : return LowerEH_SJLJ_SETJMP ( Op , DAG ) ; case <STR_LIT> : return LowerEH_SJLJ_LONGJMP ( Op , DAG ) ; case <STR_LIT> : return LowerEH_SJLJ_SETUP_DISPATCH ( Op , DAG ) ; case <STR_LIT> : return LowerINTRINSIC_VOID ( Op , DAG , Subtarget ) ; case <STR_LIT> : return LowerINTRINSIC_WO_CHAIN ( Op , DAG , Subtarget ) ; case <STR_LIT> : return ExpandBITCAST ( Op . getNode ( ) , DAG , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerShift ( Op . getNode ( ) , DAG , Subtarget ) ; case <STR_LIT> : return LowerREM ( Op . getNode ( ) , DAG ) ; case <STR_LIT> : return LowerREM ( Op . getNode ( ) , DAG ) ; case <STR_LIT> : return LowerShiftLeftParts ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerShiftRightParts ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerCTTZ ( Op . getNode ( ) , DAG , Subtarget ) ; case <STR_LIT> : return LowerCTPOP ( Op . getNode ( ) , DAG , Subtarget ) ; case <STR_LIT> : return LowerVSETCC ( Op , DAG , Subtarget ) ; case <STR_LIT> : return LowerSETCCCARRY ( Op , DAG ) ; case <STR_LIT> : return LowerConstantFP ( Op , DAG , Subtarget ) ; case <STR_LIT> : return LowerBUILD_VECTOR ( Op , DAG , Subtarget ) ; case <STR_LIT> : return LowerVECTOR_SHUFFLE ( Op , DAG , Subtarget ) ; case <STR_LIT> : return LowerEXTRACT_SUBVECTOR ( Op , DAG , Subtarget ) ; case <STR_LIT> : return LowerINSERT_VECTOR_ELT ( Op , DAG ) ; case <STR_LIT> : return LowerEXTRACT_VECTOR_ELT ( Op , DAG , Subtarget ) ; case <STR_LIT> : return LowerCONCAT_VECTORS ( Op , DAG , Subtarget ) ; case <STR_LIT> : return LowerFLT_ROUNDS_ ( Op , DAG ) ; case <STR_LIT> : return LowerMUL ( Op , DAG ) ; case <STR_LIT>


<s> inline bool isCallIndirect ( unsigned Opc ) { switch ( Opc ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . setPreservesCFG (


<s> AU . addRequired < MachineDominatorTree > ( ) ; MachineFunctionPass :: getAnalysisUsage (


<s> <ISA_LIT>AddressMode ( ) : BaseType ( RegBase ) , Scale ( <NUM_LIT> ) , IndexReg ( <NUM_LIT> ) , Disp ( <NUM_LIT> ) , GV ( <NUM_LIT> ) { Base . Reg = <NUM_LIT>


<s> <STR_LIT> ArgFlags = Outs [ i ] . Flags ; if ( IsRet ) { if ( RetCC_<ISA_LIT> ( i , ArgVT , ArgVT , CCValAssign :: Full , ArgFlags , CCInfo ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << i << <STR_LIT> << NumArgs << <STR_LIT> << EVT ( ArgVT ) . getEVTString ( ) << <STR_LIT> ) ; llvm_unreachable ( nullptr ) ; } } else { if ( CC_<ISA_LIT> ( i , ArgVT , ArgVT , CCValAssign :: Full , ArgFlags , CCInfo ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << i << <STR_LIT> << NumArgs << <STR_LIT> << EVT ( ArgVT ) . getEVTString ( ) << <STR_LIT> ) ; llvm_unreachable ( nullptr )


<s> Lex ( ) ; if ( Parser . parseExpression ( Value ) ) return reportParseError ( <STR_LIT> ) ; MCSymbol * Sym = getContext ( ) . LookupSymbol ( Name ) ; if ( Sym ) return reportParseError ( <STR_LIT> ) ; Sym = getContext ( ) . GetOrCreateSymbol ( Name ) ; Sym -> setVariableValue ( Value ) ; return


<s> FunctionPass * llvm :: create<ISA_LIT>LoadStoreOptimizerPass


<s> IAH . Out ( <STR_LIT> ) ; if ( PicMode ) { IAH . Out ( <STR_LIT> ) ; IAH . Out ( <STR_LIT> ) ; IAH . Out ( <STR_LIT> ) ; IAH . Out ( <STR_LIT> + Name ) ; IAH . Out ( <STR_LIT> + LocalName ) ; } else { IAH . Out ( <STR_LIT> ) ; IAH . Out ( <STR_LIT> + Name ) ; } swapFPIntParams ( PV , M , IAH , LE , false ) ; IAH . Out ( <STR_LIT> ) ; IAH . Out ( LocalName + <STR_LIT> + Name ) ; new UnreachableInst ( FStub -> getContext ( ) ,


<s> assert ( getCurrentSection ( ) && <STR_LIT> ) ; if ( Emitter ) AddEncodingComment ( Inst ) ; if ( ShowInst ) { Inst . dump_pretty ( GetCommentOS ( ) , & MAI , InstPrinter . get ( ) , <STR_LIT> ) ; GetCommentOS ( ) << <STR_LIT> ; } if ( InstPrinter ) InstPrinter -> printInst ( & Inst , OS ) ; else Inst . print ( OS , & MAI ) ; EmitEOL (


<s> bool DeadCodeElimination :: isDead ( unsigned R ) const { for ( const MachineOperand & MO : MRI . use_operands ( R ) ) { const MachineInstr * UseI = MO .


<s> int CC ; CC = StringSwitch < unsigned > ( Name ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT>

, <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Default ( - <NUM_LIT> ) ;


<s> case <NUM_LIT> : return createRegOperand ( FLAT_SCR_HI ) ; case <NUM_LIT> : return createRegOperand ( XNACK_MASK_LO ) ; case <NUM_LIT> : return createRegOperand ( XNACK_MASK_HI ) ; case <NUM_LIT> : return createRegOperand ( VCC_LO ) ; case <NUM_LIT> : return createRegOperand ( VCC_HI ) ; case <NUM_LIT> : return createRegOperand ( TBA_LO ) ; case <NUM_LIT> : return createRegOperand ( TBA_HI ) ; case <NUM_LIT> : return createRegOperand ( TMA_LO ) ; case <NUM_LIT> : return createRegOperand ( TMA_HI ) ; case <NUM_LIT> : return createRegOperand ( M0 ) ; case <NUM_LIT> : return createRegOperand ( EXEC_LO ) ; case <NUM_LIT> : return createRegOperand ( EXEC_HI ) ; case <NUM_LIT> : return createRegOperand ( SRC_SHARED_BASE ) ; case <NUM_LIT> : return createRegOperand ( SRC_SHARED_LIMIT ) ; case <NUM_LIT> : return createRegOperand ( SRC_PRIVATE_BASE ) ; case <NUM_LIT> : return createRegOperand ( SRC_PRIVATE_LIMIT ) ; case <NUM_LIT> : return createRegOperand (


<s> return static_cast < MCELFStreamer &


<s> static rtx riscv_unspec_address_offset ( rtx base , rtx offset , enum riscv_symbol_type symbol_type ) { base = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( <NUM_LIT> , base

) , UNSPEC_ADDRESS_FIRST + symbol_type ) ;


<s> unsigned getNumXRegisterReserved ( )


<s> const static MCFixupKindInfo Infos [ <STR_LIT> ] = { { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel | MCFixupKindInfo :: FKF_IsAlignedDownTo32Bits } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel | MCFixupKindInfo :: FKF_IsAlignedDownTo32Bits } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel | MCFixupKindInfo :: FKF_IsAlignedDownTo32Bits } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel | MCFixupKindInfo :: FKF_IsAlignedDownTo32Bits } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , } ; if ( Kind < FirstTargetFixupKind ) return MCAsmBackend :: getFixupKindInfo ( Kind ) ; assert ( unsigned ( Kind - FirstTargetFixupKind ) < getNumFixupKinds ( ) && <STR_LIT> ) ; return Infos [ Kind - FirstTargetFixupKind


<s> SDValue Src1 = N -> getOperand ( <NUM_LIT> ) ; SDValue Src2 = N -> getOperand ( <NUM_LIT> ) ; unsigned Src0Mods , Src1Mods , Src2Mods ; bool Sel0 = SelectVOP3PMadMixModsImpl ( Src0 , Src0 , Src0Mods ) ; bool Sel1 = SelectVOP3PMadMixModsImpl ( Src1 , Src1 , Src1Mods ) ; bool Sel2 = SelectVOP3PMadMixModsImpl ( Src2 , Src2 , Src2Mods ) ; assert ( ! Subtarget -> hasFP32Denormals ( ) && <STR_LIT> ) ; if ( Sel0 || Sel1 || Sel2 ) { SDValue Zero = CurDAG -> getTargetConstant ( <NUM_LIT> , SDLoc ( ) , <STR_LIT> ) ; SDValue Ops [ ] = { CurDAG -> getTargetConstant ( Src0Mods , SDLoc ( ) , <STR_LIT> ) , Src0 , CurDAG -> getTargetConstant ( Src1Mods , SDLoc ( ) , <STR_LIT> ) , Src1 , CurDAG -> getTargetConstant ( Src2Mods , SDLoc ( ) , <STR_LIT> ) , Src2 , CurDAG -> getTargetConstant ( <NUM_LIT> , SDLoc ( ) , <STR_LIT> ) , Zero , Zero } ; CurDAG -> SelectNodeTo ( N , <STR_LIT> , <STR_LIT> , Ops


<s> void <ISA_LIT>DAGToDAGISel :: getAddressOperandsRI ( const <ISA_LIT>RRIAddressMode & AM , SDValue & Base , SDValue & Disp ) { if ( AM . BaseType == <STR_LIT> )


<s> void <ISA_LIT>BaseInstrInfo :: emitCFIForLRRestoreFromReg ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator It ) const { MachineFunction & MF = * MBB . getParent ( ) ; const MCRegisterInfo * MRI = Subtarget . getRegisterInfo ( ) ; unsigned DwarfLR = MRI -> getDwarfRegNum ( <STR_LIT> , true ) ; int64_t LRPosEntry = MF . addFrameInst ( MCCFIInstruction :: createRestore ( nullptr , DwarfLR ) ) ; BuildMI ( MBB , It , DebugLoc ( ) , get ( <STR_LIT> ) ) . addCFIIndex ( LRPosEntry )

. setMIFlags ( MachineInstr :: FrameDestroy ) ;


<s> case Instruction :: Add : case Instruction :: Sub : if ( Idx == <NUM_LIT> && Imm . getBitWidth ( ) <= <NUM_LIT> ) { if ( isUInt < <NUM_LIT> > ( Imm . getZExtValue ( ) ) ) return TTI :: TCC_Free ; if ( isUInt < <NUM_LIT> > ( - Imm . getSExtValue ( ) ) ) return TTI :: TCC_Free ; } break ; case Instruction :: Mul : if ( Idx == <NUM_LIT> && Imm . getBitWidth ( ) <= <NUM_LIT> ) { if ( isInt < <NUM_LIT> > ( Imm . getSExtValue ( ) ) ) return TTI :: TCC_Free ; } break ; case Instruction :: Or : case Instruction :: Xor : if ( Idx == <NUM_LIT> && Imm . getBitWidth ( ) <= <NUM_LIT> ) { if ( isUInt < <NUM_LIT> > ( Imm . getZExtValue ( ) ) ) return TTI :: TCC_Free ; if ( ( Imm . getZExtValue ( ) & <NUM_LIT> ) == <NUM_LIT> ) return TTI :: TCC_Free ; } break ; case Instruction :: And : if ( Idx == <NUM_LIT> && Imm . getBitWidth ( ) <= <NUM_LIT> ) { if ( BitSize <= <NUM_LIT> ) return TTI :: TCC_Free ; if ( isUInt < <NUM_LIT> > ( ~ Imm . getZExtValue ( ) ) ) return TTI :: TCC_Free ; if ( ( Imm . getZExtValue ( ) & <NUM_LIT> )


<s> bool isBoundary ( MachineOperand & MO ) const { if ( BoundarySel ) { if ( ! MO . isImm ( ) ) return false ; return MO . getImm ( ) ==


<s> if ( Terminator -> isUnconditionalBranch ( ) && I != Terminator ) { MachineBasicBlock * Succ = Terminator -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; if ( BB -> isLayoutSuccessor ( Succ ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * Terminator ) ; Terminator -> eraseFromParent ( ) ; } } } ; if ( LoLoop . Revert ) { if ( LoLoop . Start -> getOpcode ( ) == <STR_LIT> ) RevertWhile ( LoLoop . Start ) ; else LoLoop . Start -> eraseFromParent ( ) ; bool FlagsAlreadySet = RevertLoopDec ( LoLoop . Dec , true ) ; RevertLoopEnd ( LoLoop . End , FlagsAlreadySet ) ; } else { LoLoop . Start = ExpandLoopStart ( LoLoop ) ; RemoveDeadBranch ( LoLoop . Start ) ; LoLoop . End = ExpandLoopEnd ( LoLoop


<s> EVT VT = N -> getValueType ( <NUM_LIT> ) ; SDValue N0 = N -> getOperand ( <NUM_LIT> ) ; SDValue N1 = N -> getOperand ( <NUM_LIT> ) ; unsigned DstBitsPerElt = VT . getScalarSizeInBits ( ) ; unsigned SrcBitsPerElt = <NUM_LIT> * DstBitsPerElt ; assert ( N0 . getScalarValueSizeInBits ( ) == SrcBitsPerElt && N1 . getScalarValueSizeInBits ( ) == SrcBitsPerElt && <STR_LIT> ) ; APInt UndefElts0 , UndefElts1 ; SmallVector < APInt , <NUM_LIT> > EltBits0 , EltBits1 ; if ( ( N0 -> isUndef ( ) || N -> isOnlyUserOf ( N0 . getNode ( ) ) ) && ( N1 -> isUndef ( ) || N -> isOnlyUserOf ( N1 . getNode ( ) ) ) && getTargetConstantBitsFromNode ( N0 , SrcBitsPerElt , UndefElts0 , EltBits0 ) && getTargetConstantBitsFromNode ( N1 , SrcBitsPerElt , UndefElts1 , EltBits1 ) ) { unsigned NumLanes = VT . getSizeInBits ( ) / <NUM_LIT> ; unsigned NumDstElts = VT . getVectorNumElements ( ) ; unsigned NumSrcElts = NumDstElts / <NUM_LIT> ; unsigned NumDstEltsPerLane = NumDstElts / NumLanes ; unsigned NumSrcEltsPerLane = NumSrcElts / NumLanes ; bool IsSigned = ( <STR_LIT> == Opcode ) ; APInt Undefs ( NumDstElts , <NUM_LIT> )


<s> return MatchOperand_NoMatch ; } unsigned SYSmvalue = Val & <NUM_LIT> ; Parser . Lex ( ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateMSRMask ( SYSmvalue , S ) ) ; return MatchOperand_Success ; } if ( ! Tok . is ( AsmToken :: Identifier ) ) return MatchOperand_NoMatch ; StringRef Mask = Tok . getString ( ) ; if ( isMClass ( ) ) { auto TheReg = <STR_LIT> ( Mask . lower ( ) ) ; if ( ! TheReg || ! TheReg -> hasRequiredFeatures ( getSTI ( ) . getFeatureBits ( ) ) ) return MatchOperand_NoMatch ; unsigned SYSmvalue = TheReg -> Encoding & <NUM_LIT> ; Parser . Lex ( ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateMSRMask ( SYSmvalue , S ) ) ; return MatchOperand_Success ; } size_t Start = <NUM_LIT> , Next = Mask . find ( '_' ) ; StringRef Flags = <STR_LIT> ; std :: string SpecReg = Mask . slice ( Start , Next ) . lower ( ) ; if ( Next != StringRef :: npos ) Flags = Mask . slice ( Next + <NUM_LIT> , Mask


<s> if ( BadLB || Cond . size ( ) != <NUM_LIT> ) return ; if ( ! TII -> PredOpcodeHasJMP_c ( Cond [ <NUM_LIT> ] . getImm ( ) ) ) return ; if ( TB != HB && FB != HB ) return ; assert ( Cond [ <NUM_LIT> ] . isReg ( ) && <STR_LIT> ) ; unsigned PR = Cond [ <NUM_LIT> ] . getReg ( ) ; assert ( MRI -> getRegClass ( PR ) == & <STR_LIT> ) ; unsigned CmpR1 = <NUM_LIT> , CmpR2 = <NUM_LIT> ; const MachineInstr * CmpI = MRI -> getVRegDef ( PR ) ; while ( CmpI -> getOpcode ( ) == <STR_LIT> ) CmpI = MRI -> getVRegDef ( CmpI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; int Mask = <NUM_LIT> , Val = <NUM_LIT> ; bool OkCI = TII -> analyzeCompare ( * CmpI , CmpR1 , CmpR2 , Mask , Val ) ; if ( ! OkCI ) return ; if ( CmpR1 && MRI -> getRegClass ( CmpR1 ) != DoubleRC ) CmpR1 = <NUM_LIT> ; if ( CmpR2 && MRI -> getRegClass ( CmpR2 ) != DoubleRC ) CmpR2 = <NUM_LIT> ; if ( ! CmpR1 && ! CmpR2 ) return ; using UVect = std :: vector < unsigned > ; UVect DP ; for ( auto & MI : * HB ) { if ( ! MI . isPHI ( ) ) break ; const MachineOperand & MD = MI . getOperand ( <NUM_LIT> ) ; unsigned R = MD . getReg ( ) ; if ( MRI -> getRegClass ( R ) == DoubleRC ) DP . push_back ( R ) ; } if ( DP . empty ( ) ) return ; auto NoIndOp = [ this , CmpR1 , CmpR2 ] ( unsigned R ) -> bool { for ( auto I = MRI -> use_nodbg_begin ( R ) , E = MRI


<s> static Reloc :: Model getEffectiveRelocModel ( const Triple & TT , Optional < Reloc :: Model > RM ) { assert ( ( ! TT . isOSAIX ( ) || ! RM . hasValue ( ) || * RM == Reloc :: PIC_ ) && <STR_LIT> ) ; if ( RM . hasValue ( ) ) return * RM ; if ( TT . isOSDarwin ( ) ) return Reloc :: DynamicNoPIC ; if ( TT . getArch ( ) == Triple :: ppc64 || TT . isOSAIX ( )


<s> unsigned IdxOpc = getRegOffOpcode ( ExtOpc ) ; assert ( IdxOpc == <STR_LIT> ) ; int32_t D = isInt < <NUM_LIT> > ( Diff ) ? Diff : ( Diff > <NUM_LIT> ? <NUM_LIT> : - <NUM_LIT> ) ; BuildMI ( MBB , At , dl , HII -> get ( IdxOpc ) ) . add ( MI . getOperand ( <NUM_LIT> ) ) . add ( MachineOperand ( ExtR ) ) . addImm ( D ) ; Diff -= D ; OffsetRange Uses = getOffsetRange ( MI . getOperand ( <NUM_LIT> ) ) ; if ( ! Uses . contains ( Diff ) ) dbgs ( ) << <STR_LIT> << Diff << <STR_LIT> << Uses << <STR_LIT> << MI ; assert ( Uses . contains ( Diff ) ) ; MBB . erase ( MI ) ; return true ; } const ExtValue & EV = ExtI . first ; ( void ) EV ; const ExtExpr & Ex = ExtI . second ; ( void ) Ex ; if ( ExtOpc == <STR_LIT> || ExtOpc == <STR_LIT> ) { bool IsAddi = ExtOpc == <STR_LIT> ; const MachineOperand & RegOp = MI . getOperand ( IsAddi ? <NUM_LIT> : <NUM_LIT> ) ; const MachineOperand & ImmOp = MI . getOperand ( IsAddi ? <NUM_LIT> : <NUM_LIT> ) ; assert ( Ex . Rs == RegOp && EV == ImmOp && Ex . Neg != IsAddi && <STR_LIT> ) ; BuildMI ( MBB , At , dl , HII -> get ( TargetOpcode :: COPY ) ) . add ( MI . getOperand ( <NUM_LIT> ) ) . add ( MachineOperand ( ExtR ) ) ; Diff = <NUM_LIT> ; MBB . erase ( MI ) ; return true ; } if ( ExtOpc == <STR_LIT> || ExtOpc == <STR_LIT> || ExtOpc == <STR_LIT> || ExtOpc == <STR_LIT> ) { bool IsSub = ExtOpc == <STR_LIT> ; Register Rs = MI . getOperand ( IsSub ? <NUM_LIT> : <NUM_LIT> ) ; ExtValue V = MI . getOperand ( IsSub ? <NUM_LIT> : <NUM_LIT> ) ; assert ( EV == V && Rs == Ex . Rs && IsSub == Ex . Neg && <STR_LIT> ) ; unsigned NewOpc = ExtOpc == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; BuildMI ( MBB , At , dl , HII -> get ( NewOpc ) ) . add ( MI . getOperand ( <NUM_LIT> ) ) . add ( MI . getOperand ( <NUM_LIT> ) ) . add ( MachineOperand ( ExtR ) ) ; MBB . erase ( MI ) ; return true ; } if ( MI . mayLoad ( ) ||


<s> <ISA_LIT>FunctionInfo ( MachineFunction & MF ) : isThumb ( MF . getTarget ( ) . getSubtarget < <ISA_LIT>Subtarget > ( ) . isThumb ( ) ) , Align ( isThumb ? <NUM_LIT> : <NUM_LIT> ) , VarArgsRegSaveSize ( <NUM_LIT> ) , HasStackFrame ( false ) , LRSpilledForFarJump ( false ) , R3IsLiveIn ( false ) , FramePtrSpillOffset ( <NUM_LIT> ) , GPRCS1Offset ( <NUM_LIT> ) , GPRCS2Offset ( <NUM_LIT> ) , DPRCSOffset ( <NUM_LIT> )

, GPRCS1Size ( <NUM_LIT> ) , GPRCS2Size ( <NUM_LIT> ) , DPRCSSize ( <NUM_LIT> ) , GPRCS1Frames ( <NUM_LIT> ) , GPRCS2Frames ( <NUM_LIT> ) , DPRCSFrames ( <NUM_LIT> ) , SpilledCSRegs ( MF . getTarget ( ) . getRegisterInfo ( ) -> getNumRegs ( ) ) , JumpTableUId ( <NUM_LIT> ) , ConstPoolEntryUId ( <NUM_LIT> ) {


<s> if ( get<ISA_LIT>Subtarget ( ) . allowMixed16_32 ( ) ) { addPass ( create<ISA_LIT>ModuleISelDag ( get<ISA_LIT>TargetMachine ( ) ) ) ; addPass ( create<ISA_LIT>16ISelDag ( get<ISA_LIT>TargetMachine ( ) ) ) ; addPass ( create<ISA_LIT>SEISelDag ( get<ISA_LIT>TargetMachine ( ) ) ) ; } else { addPass ( create<ISA_LIT>ISelDag ( get<ISA_LIT>TargetMachine ( ) ) ) ; } return


<s> assert ( VT . getVectorElementCount ( ) . getKnownMinValue ( ) % N == <NUM_LIT> && <STR_LIT> ) ; EVT SplitVT = EVT :: getVectorVT ( * DAG . getContext ( ) , VT . getVectorElementType ( ) , VT . getVectorElementCount ( ) / N ) ; assert ( isTypeLegal ( SplitVT ) ) ; SmallVector < EVT , <NUM_LIT> > VTs ( N , SplitVT ) ; VTs . push_back ( <STR_LIT> ) ; SDVTList NodeTys = DAG . getVTList ( VTs ) ; SDValue PseudoLoad = DAG . getNode ( Opcode , DL , NodeTys , LoadOps ) ; SmallVector < SDValue , <NUM_LIT> > PseudoLoadOps ; for ( unsigned I = <NUM_LIT> ; I < N ; ++ I ) PseudoLoadOps . push_back ( SDValue


<s> MI . addOperand ( MCOperand :: createReg ( getReg ( Decoder , <STR_LIT> , Rs ) ) ) ; MI . addOperand ( MCOperand :: createReg ( getReg ( Decoder , <STR_LIT> , Rs ) ) ) ; MI . addOperand ( MCOperand :: createImm ( Imm ) ) ; return MCDisassembler


<s> bool <ISA_LIT>LongBranch :: mustRelaxABranch ( ) { for ( auto & Terminator : Terminators ) if ( mustRelaxBranch ( Terminator , Terminator . Address ) ) return true ; return false


<s> return createMachObjectWriter ( OS , true , object :: mach :: CTM_x86_64 , object :: mach :: CS<ISA_LIT>_ALL ,


<s> bool useAudioOps ( ) const { return UseAudioOps


<s> const unsigned SrcSize = SrcTy . getSizeInBits ( ) ; const unsigned PartSize = PartTy . getSizeInBits ( ) ; if ( SrcTy . isVector ( ) && ! PartTy . isVector ( ) && PartSize > SrcTy . getElementType ( ) . getSizeInBits ( ) ) { auto UnmergeToEltTy = B . buildUnmerge ( SrcTy . getElementType ( ) , SrcReg ) ; for ( int i = <NUM_LIT> , e = DstRegs . size ( ) ; i != e ; ++ i ) B . buildAnyExt ( DstRegs [ i ] , UnmergeToEltTy . getReg ( i ) ) ; return ; } if ( SrcSize % PartSize == <NUM_LIT> ) { B . buildUnmerge ( DstRegs ,


<s> SDValue <ISA_LIT>TargetLowering :: LowerFormalArguments ( SDValue Chain , CallingConv :: ID CallConv , bool isVarArg , const SmallVectorImpl < <STR_LIT> > & Ins , DebugLoc dl ,

SelectionDAG & DAG , SmallVectorImpl < SDValue > & InVals ) {


<s> if ( NumElem == <NUM_LIT> && VTy -> getScalarSizeInBits ( ) == <NUM_LIT> ) return <NUM_LIT> ; if ( ! isPowerOf2_32 ( NumElem ) ) { APInt DemandedElts = APInt :: getAllOnesValue ( NumElem ) ; int Cost = BaseT :: getMemoryOpCost ( Opcode , VTy -> getScalarType ( ) , Alignment , AddressSpace , CostKind ) ; int SplitCost = getScalarizationOverhead ( VTy , DemandedElts , Opcode == Instruction :: Load , Opcode == Instruction :: Store ) ; return NumElem * Cost + SplitCost ; } } if ( TLI -> getValueType ( DL , Src , true ) == <STR_LIT> ) return BaseT :: getMemoryOpCost ( Opcode , Src , Alignment , AddressSpace , CostKind ) ; std :: pair < int , MVT > LT = TLI -> getTypeLegalizationCost ( DL , Src ) ; assert ( ( Opcode == Instruction :: Load || Opcode == Instruction :: Store ) && <STR_LIT> ) ; int Cost = LT . first


<s> static rtx get_tls_get_addr ( void ) { if ( ! tls_get_addr_libfunc ) tls_get_addr_libfunc = init_one_libfunc ( <STR_LIT> ) ; return tls_get_addr_libfunc


<s> static <STR_LIT> getCondFromOpc ( unsigned Opc ) { <STR_LIT> CC = <STR_LIT> ; if ( CC == <STR_LIT> ) CC = <STR_LIT> ( Opc ) ; if ( CC == <STR_LIT> ) CC = <STR_LIT> ( Opc ) ; if ( CC == <STR_LIT> ) CC = <STR_LIT>


<s> if ( In != Op . getOperand ( <NUM_LIT> ) ) IsSplat = false ; } if ( AllContants ) { SDValue FullMask = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getConstant ( Immediate , <STR_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , dl , VT , FullMask , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; } if ( NumNonConsts == <NUM_LIT> && NonConstIdx != <NUM_LIT> ) { SDValue DstVec ; if ( NumConsts ) { SDValue VecAsImm = DAG . getConstant ( Immediate , <STR_LIT> ( VT . getSizeInBits ( ) ) ) ; DstVec = DAG . getNode ( <STR_LIT> , dl , VT , VecAsImm ) ; } else DstVec = DAG . getUNDEF ( VT ) ; return DAG . getNode ( <STR_LIT> , dl , VT , DstVec , Op . getOperand ( NonConstIdx ) , DAG . getIntPtrConstant ( NonConstIdx ) ) ; } if ( ! IsSplat && ( NonConstIdx != <NUM_LIT> ) ) llvm_unreachable ( <STR_LIT> ) ; MVT SelectVT = ( VT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; SDValue Select ; if ( IsSplat ) Select = DAG . getNode ( <STR_LIT> , dl , SelectVT , Op . getOperand ( <NUM_LIT> ) , DAG . getConstant ( - <NUM_LIT> , SelectVT ) , DAG . getConstant ( <NUM_LIT> , SelectVT ) ) ; else Select = DAG . getNode ( <STR_LIT> , dl , SelectVT , Op . getOperand ( <NUM_LIT> ) , DAG . getConstant ( ( Immediate | <NUM_LIT> ) , SelectVT ) , DAG . getConstant ( Immediate


<s> SDValue Pred = Op . getOperand ( <NUM_LIT> ) ; SDValue InVec = Op . getOperand ( <NUM_LIT> ) ; if ( isTypeLegal ( InVec . getValueType ( ) ) ) return Op ; EVT VT = Op . getValueType ( ) ; if ( VT . isFloatingPoint ( ) ) { EVT IntResVT = VT . changeTypeToInteger ( ) ; EVT IntVecVT = InVec . getValueType ( ) . changeVectorElementTypeToInteger ( ) ; SDValue IntInVec = DAG . getNode ( <STR_LIT> , DL , IntVecVT , InVec ) ; SDValue Res = DAG . getNode ( Op . getOpcode ( ) , DL , IntResVT , Pred , IntInVec ) ; return DAG . getNode ( <STR_LIT> , DL , VT , Res ) ; } assert ( isTypeLegal ( Pred . getValueType ( ) ) && <STR_LIT> ) ; EVT EltVT = InVec . getValueType ( ) . getVectorElementType ( ) ; EVT NewEltVT = EVT :: getIntegerVT ( * DAG . getContext ( ) , EltVT . getSizeInBits ( ) / <NUM_LIT> ) ; EVT SplitVT = InVec . getValueType ( ) . changeVectorElementType ( NewEltVT ) ; SDValue InVecLo , InVecHi ; std :: tie ( InVecLo , InVecHi ) = DAG . SplitVector ( InVec , DL ) ; InVecLo = DAG . getNode ( <STR_LIT> , DL , SplitVT , InVecLo ) ; InVecHi = DAG . getNode ( <STR_LIT> ,


<s> static MCSubtargetInfo * create<ISA_LIT>MCSubtargetInfo ( StringRef TT , StringRef CPU , StringRef FS ) { MCSubtargetInfo * X = new MCSubtargetInfo (


<s> virtual uint64_t getMachineOpValue ( const MCInst & MI , const MCOperand & MO , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { return <NUM_LIT>


<s> } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( ! MI -> getOperand ( <NUM_LIT> ) . isImm ( ) ) { return <NUM_LIT> ; } break ; case <STR_LIT> : case <STR_LIT> : if ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) != MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) { return


<s> static DecodeStatus DecodeMSRSystemRegister ( MCInst & Inst , unsigned Imm , uint64_t Address , const void * Decoder ) { Inst . addOperand ( MCOperand :: createImm ( Imm ) ) ; return Success


<s> if ( SignReturnAddressAll ) return true ; return SpillsLR


<s> switch ( Opc ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Scale = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Scale = <NUM_LIT> ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } unsigned OffsetIdx = MI . getNumExplicitOperands ( ) - <NUM_LIT> ; assert ( MI . getOperand ( OffsetIdx - <NUM_LIT> ) . getReg ( ) == <STR_LIT> && <STR_LIT> ) ; MachineOperand & OffsetOpnd = MI . getOperand ( OffsetIdx ) ; assert ( LocalStackSize % Scale == <NUM_LIT> ) ; OffsetOpnd . setImm ( OffsetOpnd . getImm ( ) + LocalStackSize


<s> const char * this_name = reg_names [ this_regno ] ; const char * fname ; gcc_assert ( call_used_regs [ GPR_IP ] ) ; gcc_assert ( call_used_regs [ GPR_16 ] ) ; if ( delta == <NUM_LIT> ) ; else if ( SIMM11 ( delta ) ) asm_fprintf ( file , <STR_LIT> , this_name , this_name , ( int ) delta ) ; else if ( delta < <NUM_LIT> && delta >= - <NUM_LIT> ) { asm_fprintf ( file , <STR_LIT> , ( int ) - delta ) ; asm_fprintf ( file , <STR_LIT> , this_name , this_name ) ; } else { asm_fprintf ( file , <STR_LIT> , ( long ) delta ) ; if ( delta & ~ <NUM_LIT> ) asm_fprintf ( file , <STR_LIT> , ( long ) delta ) ; asm_fprintf ( file , <STR_LIT> , this_name , this_name


<s> } unsigned FrameReg = TRI -> getFrameRegister ( MF ) ; BuildMI ( MBB , MI , DL , TII . get ( <STR_LIT> ) ) . addReg ( FrameReg ) ; BuildMI ( MBB , MI , DL , TII . get ( <STR_LIT> ) , FrameReg ) . addImm ( <NUM_LIT> ) ; BuildMI ( MBB , MI , DL , TII . get ( <STR_LIT> ) , FrameReg ) . addReg ( FrameReg ) ; FPOffset = <NUM_LIT> ; } BuildStackAdjustment ( MF , MBB , MI , DL , ScratchReg , StackSize


<s> SDValue <ISA_LIT>TargetLowering :: LowerBlockAddress ( SDValue Op , SelectionDAG & DAG ) const { MachineFunction & MF = DAG . getMachineFunction ( ) ; <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; unsigned <ISA_LIT>PCLabelIndex = <NUM_LIT> ; SDLoc DL ( Op ) ; EVT PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; const BlockAddress * BA = cast < BlockAddressSDNode > ( Op ) -> getBlockAddress ( ) ; SDValue CPAddr ; bool IsPositionIndependent = isPositionIndependent ( ) ; if ( ! IsPositionIndependent ) { CPAddr = DAG . getTargetConstantPool ( BA , PtrVT , <NUM_LIT> ) ; } else { unsigned PCAdj = Subtarget -> isThumb ( ) ? <NUM_LIT> : <NUM_LIT> ; <ISA_LIT>PCLabelIndex = AFI -> createPICLabelUId ( ) ; <ISA_LIT>ConstantPoolValue * CPV = <ISA_LIT>ConstantPoolConstant :: Create ( BA , <ISA_LIT>PCLabelIndex , <STR_LIT> , PCAdj ) ; CPAddr = DAG . getTargetConstantPool ( CPV , PtrVT , <NUM_LIT> ) ; } CPAddr = DAG . getNode ( <STR_LIT> , DL , PtrVT , CPAddr ) ; SDValue Result = DAG . getLoad ( PtrVT , DL , DAG . getEntryNode ( ) , CPAddr , MachinePointerInfo :: getConstantPool ( DAG . getMachineFunction ( ) ) ) ; if ( ! IsPositionIndependent )


<s> const RegisterBankInfo * getRegBankInfo ( ) const override { return RegBankInfo . get (


<s> Instr ( unsigned Opcode , unsigned Def , unsigned LHS , unsigned RHS ) : Opcode ( Opcode ) , Def ( Def ) , LHS ( LHS ) , RHS


<s> switch ( Value ) { case FpABIKind :: XX : return <STR_LIT> ; case FpABIKind :: S32 : return <STR_LIT> ; case FpABIKind :: S64 : return


<s> void LLVMInitialize<ISA_LIT>AsmPrinter ( ) { RegisterAsmPrinter < <ISA_LIT>AsmPrinter > X


<s> unsigned getExceptionPointerRegister ( const Constant


<s> typedef float v4hi __attribute__ ( ( mode ( V4HI ) ) ) ; return ( unsigned long long ) __builtin_sh_media_MMULFXRP_W ( ( v4hi ) mm , ( v4hi ) mn


<s> return std :: make_unique < <ISA_LIT>ELFObjectWriter > ( Is64Bit , OSABI , HasRelocationAddend


<s> case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; assert ( NumVecs == <NUM_LIT> && <STR_LIT> ) ; break ; } EVT ResTy ; if ( NumVecs == <NUM_LIT> ) ResTy = VT ; else { unsigned ResTyElts = ( NumVecs == <NUM_LIT> ) ? <NUM_LIT> : NumVecs ; if ( ! is64BitVector ) ResTyElts *= <NUM_LIT> ; ResTy = EVT :: getVectorVT ( * CurDAG -> getContext ( ) , <STR_LIT> , ResTyElts ) ; } std :: vector < EVT > ResTys ; ResTys . push_back ( ResTy ) ; if ( isUpdating ) ResTys . push_back ( <STR_LIT> ) ; ResTys . push_back ( <STR_LIT> ) ; SDValue Pred = getAL ( CurDAG , dl ) ; SDValue Reg0 = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; SDNode * VLd ; SmallVector < SDValue , <NUM_LIT> > Ops ; if ( is64BitVector || NumVecs <= <NUM_LIT> ) { unsigned Opc = ( is64BitVector ? DOpcodes [ OpcodeIndex ] : QOpcodes0 [ OpcodeIndex ] ) ; Ops . push_back ( MemAddr ) ; Ops . push_back ( Align ) ; if ( isUpdating ) { SDValue Inc = N -> getOperand ( AddrOpIdx + <NUM_LIT> ) ; bool IsImmUpdate = isPerfectIncrement ( Inc , VT , NumVecs ) ; if ( ( NumVecs <= <NUM_LIT> ) && ! IsImmUpdate ) Opc = getVLDSTRegisterUpdateOpcode ( Opc ) ; if ( ( NumVecs > <NUM_LIT> && ! isVLDfixed ( Opc ) ) || ! IsImmUpdate ) Ops . push_back ( IsImmUpdate ? Reg0 : Inc ) ; } Ops . push_back ( Pred ) ; Ops . push_back ( Reg0 ) ; Ops . push_back ( Chain ) ; VLd = CurDAG -> getMachineNode ( Opc , dl , ResTys , Ops ) ; } else { EVT AddrTy = MemAddr . getValueType ( ) ; SDValue ImplDef = SDValue ( CurDAG -> getMachineNode ( TargetOpcode :: IMPLICIT_DEF , dl , ResTy ) , <NUM_LIT> ) ; const SDValue OpsA [ ] = { MemAddr , Align , Reg0 , ImplDef , Pred , Reg0 , Chain } ; SDNode * VLdA = CurDAG -> getMachineNode ( QOpcodes0 [ OpcodeIndex ] , dl , ResTy , AddrTy , <STR_LIT> , OpsA ) ; Chain = SDValue ( VLdA , <NUM_LIT> ) ; Ops . push_back ( SDValue ( VLdA , <NUM_LIT> ) ) ; Ops . push_back ( Align ) ; if ( isUpdating ) { SDValue Inc = N -> getOperand ( AddrOpIdx + <NUM_LIT> ) ; assert ( isa < ConstantSDNode > ( Inc . getNode ( ) ) &&


<s> } assert ( Op . getOperand ( <NUM_LIT> ) . isUndef ( ) && <STR_LIT> ) ; SDValue LoadVal = LoadOperand ( DAG , DL , Val . getValueType ( ) , Val ) ; SDValue Ops [ ] = { Chain , LoadVal , Ptr } ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT>


<s> InstructionCost Cost = <NUM_LIT> ; if ( isWideningInstruction ( Ty , Opcode , Args ) ) Cost += ST -> getWideningBaseCost ( ) ; int ISD = TLI -> InstructionOpcodeToISD ( Opcode ) ; switch ( ISD ) { default : return Cost + BaseT :: getArithmeticInstrCost ( Opcode , Ty , CostKind , Opd1Info , Opd2Info , Opd1PropInfo , Opd2PropInfo ) ; case <STR_LIT> : if ( Opd2Info == TargetTransformInfo :: OK_UniformConstantValue && Opd2PropInfo == TargetTransformInfo :: OP_PowerOf2 ) { Cost += getArithmeticInstrCost ( Instruction :: Add , Ty , CostKind , Opd1Info , Opd2Info , TargetTransformInfo :: OP_None , TargetTransformInfo :: OP_None ) ; Cost += getArithmeticInstrCost ( Instruction :: Sub , Ty , CostKind , Opd1Info , Opd2Info , TargetTransformInfo :: OP_None , TargetTransformInfo :: OP_None ) ; Cost += getArithmeticInstrCost ( Instruction :: Select , Ty , CostKind , Opd1Info , Opd2Info , TargetTransformInfo :: OP_None , TargetTransformInfo :: OP_None ) ; Cost += getArithmeticInstrCost ( Instruction :: AShr , Ty , CostKind , Opd1Info , Opd2Info , TargetTransformInfo :: OP_None , TargetTransformInfo :: OP_None ) ; return Cost ; } LLVM_FALLTHROUGH ; case <STR_LIT> : if ( Opd2Info == TargetTransformInfo :: OK_UniformConstantValue ) { auto VT = TLI -> getValueType ( DL , Ty ) ; if ( TLI -> isOperationLegalOrCustom ( <STR_LIT> , VT ) ) { InstructionCost MulCost = getArithmeticInstrCost ( Instruction :: Mul , Ty , CostKind , Opd1Info , Opd2Info , TargetTransformInfo :: OP_None , TargetTransformInfo :: OP_None ) ; InstructionCost AddCost = getArithmeticInstrCost ( Instruction :: Add , Ty , CostKind , Opd1Info , Opd2Info , TargetTransformInfo :: OP_None , TargetTransformInfo :: OP_None ) ; InstructionCost ShrCost = getArithmeticInstrCost ( Instruction :: AShr , Ty , CostKind , Opd1Info , Opd2Info , TargetTransformInfo :: OP_None , TargetTransformInfo :: OP_None ) ; return MulCost * <NUM_LIT> + AddCost * <NUM_LIT> + ShrCost * <NUM_LIT> + <NUM_LIT> ; } } Cost += BaseT :: getArithmeticInstrCost ( Opcode , Ty , CostKind , Opd1Info , Opd2Info , Opd1PropInfo , Opd2PropInfo ) ; if ( Ty -> isVectorTy ( ) ) { Cost += getArithmeticInstrCost ( Instruction :: ExtractElement , Ty , CostKind , Opd1Info , Opd2Info , Opd1PropInfo , Opd2PropInfo ) ; Cost += getArithmeticInstrCost ( Instruction :: InsertElement , Ty , CostKind , Opd1Info , Opd2Info , Opd1PropInfo , Opd2PropInfo ) ; Cost += Cost ; } return Cost ; case <STR_LIT> : if ( LT . second != <STR_LIT> ) return ( Cost + <NUM_LIT> ) * LT . first ; return LT . first * <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ( Cost + <NUM_LIT> ) * LT . first ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( ! Ty -> getScalarType ( ) -> isFP128Ty ( ) ) return ( Cost + <NUM_LIT> ) * LT


<s> static inline MachineInstr * getMachineInstr ( const SUnit &


<s> initialize<ISA_LIT>MemAluCombinerPass ( * PassRegistry :: getPassRegistry ( )


<s> <ISA_LIT>LegalizerInfo :: FCmpLibcallsList <ISA_LIT>LegalizerInfo :: getFCmpLibcalls ( CmpInst :: Predicate Predicate , unsigned Size ) const { assert ( CmpInst :: isFPPredicate ( Predicate ) && <STR_LIT>


<s> if ( ! ST . debuggerInsertNops ( ) ) return false ; if ( ! MF . getMMI ( ) . hasDebugInfo ( ) ) return false ; const <ISA_LIT>InstrInfo * TII = ST . getInstrInfo ( ) ; DenseSet < unsigned > NopInserted ; for ( auto & MBB : MF ) { for ( auto MI = MBB . begin ( ) ; MI != MBB . end ( ) ; ++ MI ) { if ( MI -> isDebugInstr ( ) || ! MI -> getDebugLoc ( ) ) continue ; auto DL = MI -> getDebugLoc ( ) ; if ( NopInserted . find ( DL . getLine ( ) )


<s> uint16_t OMB = OM . first ( ) , OME = OM . last ( ) ; uint16_t NMB = NM . first ( ) , NME = NM . last ( ) ; ( void ) NME ; assert ( ( OME - OMB == NME - NMB ) && <STR_LIT> ) ; for ( std :: pair < const unsigned , RegisterCell > & P : Map ) { RegisterCell & RC = P . second ; for ( uint16_t i = <NUM_LIT> , w = RC .


<s> break ; } unsigned SrcReg = Cond [ <NUM_LIT> ] . getReg ( ) ; if ( Is64Bit ) { MRI . constrainRegClass ( SrcReg , & <STR_LIT> ) ; BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( SrcReg ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; } else { MRI . constrainRegClass ( SrcReg , & <STR_LIT> ) ; BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( SrcReg ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; } break ; } case <NUM_LIT> : { switch ( Cond [ <NUM_LIT> ] . getImm ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : CC = <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : CC = <STR_LIT> ; break ; } if ( Cond [ <NUM_LIT> ] . getImm ( ) == <STR_LIT> || Cond [ <NUM_LIT> ] . getImm ( ) == <STR_LIT> ) BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( Cond [ <NUM_LIT> ] . getReg ( ) ) . addImm ( <STR_LIT> ( <NUM_LIT> << Cond [ <NUM_LIT> ] . getImm ( ) , <NUM_LIT> ) ) ; else BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( Cond [ <NUM_LIT> ] . getReg ( ) ) . addImm ( <STR_LIT> ( <NUM_LIT> << Cond [ <NUM_LIT> ] . getImm ( ) , <NUM_LIT> ) ) ; break ; } } unsigned Opc = <NUM_LIT> ; const TargetRegisterClass * RC = nullptr ; bool TryFold = false ; if ( MRI . constrainRegClass ( DstReg , & <STR_LIT> ) ) { RC = & <STR_LIT> ; Opc = <STR_LIT> ; TryFold = true ; } else if ( MRI . constrainRegClass ( DstReg , & <STR_LIT> ) ) { RC = & <STR_LIT> ; Opc = <STR_LIT> ; TryFold = true ; } else if ( MRI . constrainRegClass ( DstReg , & <STR_LIT> ) ) { RC = & <STR_LIT> ; Opc = <STR_LIT> ; } else if ( MRI . constrainRegClass ( DstReg , & <STR_LIT> ) ) { RC = & <STR_LIT> ; Opc = <STR_LIT> ; } assert ( RC && <STR_LIT> ) ; if ( TryFold ) { unsigned NewVReg = <NUM_LIT> ; unsigned FoldedOpc = canFoldIntoCSel ( MRI , TrueReg , & NewVReg ) ; if ( FoldedOpc ) { CC = <STR_LIT> ( CC ) ; TrueReg = FalseReg ; } else FoldedOpc = canFoldIntoCSel ( MRI


<s> if ( ! Subtarget . isTargetLinux ( ) ) return false ; if ( Subtarget . is64Bit ( ) ) { Offset = <NUM_LIT> ; if ( getTargetMachine ( ) . getCodeModel ( ) == CodeModel :: Kernel ) AddressSpace = <NUM_LIT> ; else AddressSpace = <NUM_LIT> ; }


<s> const TargetFrameLowering * TFI = MF . getTarget ( ) . getFrameLowering ( ) ; const TargetRegisterInfo * RegInfo = MF . getTarget ( ) . getRegisterInfo ( ) ; unsigned MaxAlign = MFI -> getMaxAlignment ( ) ; int Offset = <NUM_LIT> ; for ( int i = MFI -> getObjectIndexBegin ( ) ; i != <NUM_LIT> ; ++ i ) { int FixedOff = - MFI -> getObjectOffset ( i ) ; if ( FixedOff > Offset ) Offset = FixedOff ; } for ( unsigned i = <NUM_LIT> , e = MFI -> getObjectIndexEnd ( ) ; i != e ; ++ i ) { if ( MFI -> isDeadObjectIndex ( i ) ) continue ; Offset += MFI -> getObjectSize ( i ) ; unsigned Align = MFI -> getObjectAlignment ( i ) ; Offset = ( Offset + Align - <NUM_LIT> ) / Align * Align ; MaxAlign = std :: max ( Align


<s> static const unsigned RegList [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; if ( unsigned Reg = State . AllocateReg ( RegList , <NUM_LIT> ) ) State . addLoc ( CCValAssign :: getCustomReg ( ValNo , ValVT , Reg , LocVT , LocInfo ) ) ; else { if ( CanFail ) return false ; State . addLoc ( CCValAssign :: getCustomMem ( ValNo , ValVT , State . AllocateStack ( <NUM_LIT> , <NUM_LIT> ) , LocVT , LocInfo ) ) ; return true ; } if ( unsigned Reg = State . AllocateReg ( RegList , <NUM_LIT> ) ) State . addLoc ( CCValAssign :: getCustomReg ( ValNo , ValVT , Reg , LocVT , LocInfo ) ) ; else State . addLoc ( CCValAssign :: getCustomMem ( ValNo , ValVT , State


<s> BuildMI ( MBB , I , DL , TII -> get ( <STR_LIT> ) , Dst ) . addReg ( SrcReg , RegState :: Undef , SubReg ) . addReg ( SrcReg , RegState :: Implicit ) . addReg ( <STR_LIT> , RegState :: Implicit ) ; BuildMI ( MBB , I , DL , TII -> get ( <STR_LIT> ) ) ; } else { BuildMI ( MBB , I , DL , TII -> get ( <STR_LIT> ) , Dst ) . addReg ( SrcReg , RegState :: Undef , SubReg ) . addReg ( SrcReg , RegState :: Implicit ) ; } MI . eraseFromParent ( ) ; return & MBB ; } const DebugLoc & DL = MI . getDebugLoc ( ) ; MachineBasicBlock :: iterator I ( & MI ) ; unsigned PhiReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; unsigned InitReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( MBB , I , DL , TII -> get ( TargetOpcode :: IMPLICIT_DEF ) , InitReg ) ; if ( UseGPRIdxMode ) { MachineInstr * SetOn = BuildMI ( MBB , I , DL , TII -> get ( <STR_LIT> ) ) . addImm ( <NUM_LIT> ) . addImm ( VGPRIndexMode :: SRC0_ENABLE ) ; SetOn -> getOperand ( <NUM_LIT> )


<s> static inline int decodeImm32_BL ( uint32_t insn ) { unsigned S = slice ( insn , <NUM_LIT> , <NUM_LIT> ) ; bool I1 = slice ( insn , <NUM_LIT> , <NUM_LIT> ) == S ; bool I2 = slice ( insn , <NUM_LIT> , <NUM_LIT> ) == S ; unsigned Imm25 = slice ( insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> | slice ( insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ; if ( S ) Imm25 |= <NUM_LIT> << <NUM_LIT> ; if ( I1 ) Imm25 |= <NUM_LIT>


<s> if ( ( Count % <NUM_LIT> ) != <NUM_LIT> ) return false ; for ( uint64_t i = <NUM_LIT> ; i < Count ; i += <NUM_LIT> ) <STR_LIT> :: write < uint64_t > ( OS , <NUM_LIT> , Endian ) ; return true


<s> void printi8mem ( const MCInst * MI , unsigned OpNo , raw_ostream & O ) { O << <STR_LIT> ; printMemReference ( MI , OpNo , O


<s> EndLoc = Parser . getTok ( ) . getLoc ( ) ; return ( RegNo == ( unsigned )


<s> if ( MO . isReg ( ) ) return TM . getRegisterInfo ( ) -> getEncodingValue ( MO . getReg ( ) ) ; else if ( MO . isImm ( ) ) return static_cast < unsigned > ( MO . getImm ( ) ) ; else if ( MO . isGlobal ( ) ) emitGlobalAddress ( MO . getGlobal ( )


<s> bool IsExtendFixupCandidate ( MachineRegisterInfo * MRI , MachineInstr * MI ) { unsigned Opcode = MI -> getOpcode ( ) ; switch ( Opcode ) { default : return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> bool <ISA_LIT>FastISel :: SelectSIToFP ( const Instruction * I ) { if ( ! Subtarget -> hasVFP2 ( ) ) return false ; MVT DstVT ; const Type * Ty = I -> getType ( ) ; if ( ! isTypeLegal ( Ty , DstVT ) ) return false ; unsigned Op = getRegForValue ( I -> getOperand (


<s> emit_move_insn ( offset == <NUM_LIT> ? change_address ( addr , SImode , NULL_RTX ) : adjust_address ( addr , SImode , offset


<s> return MCSymbolRefExpr :: create ( MBB -> getSymbol ( ) , MCSymbolRefExpr ::


<s> const MCInstrDesc & MCID = MI -> getDesc ( ) ; if ( MCID . isCall ( ) || MCID . hasImplicitDefOfPhysReg (


<s> unsigned Idx = isPairedLdSt ( MI ) ? <NUM_LIT> : <NUM_LIT> ; return MI . getOperand (


<s> static void PrintUnmangledNameSafely ( const Value * V , raw_ostream & OS ) { for ( const char * Name = V -> getNameStart ( ) , * E = Name + V -> getNameLen ( ) ; Name != E ; ++ Name ) if ( isprint ( * Name ) ) OS


<s> return ( __m128i ) __builtin_ia32_pmovsxbq128_mask ( ( __v16qi ) __A ,


<s> bool isSDWASrc0Sel ( ) const { return isImmTy ( ImmTySdwaSrc0Sel


<s> std :: unique_ptr < MCObjectTargetWriter > llvm :: create<ISA_LIT>MachObjectWriter ( bool Is64Bit , uint32_t


<s> else return true ; if ( GET_CODE ( x ) != SYMBOL_REF ) return true ; case SYMBOL_REF : return SYMBOL_REF_TLS_MODEL ( x ) == <NUM_LIT> ; case CONST_DOUBLE : if ( x == CONST0_RTX ( mode ) ) return true ; if ( FLOAT_MODE_P ( mode ) ) return false ; goto do_integer ; case CONST_VECTOR : if ( x == CONST0_RTX ( mode ) ) return true ; if ( GET_MODE_CLASS ( mode ) != MODE_VECTOR_INT )


<s> std :: vector < std :: string > mov2_ax_mij ( Ab a , ArpRn1 b , ArpStep1 bsi , ArpStep1 bsj ) { return D ( <STR_LIT> , R ( a ) , MemARPSI ( b ,


<s> const GlobalValue * GV = GSD -> getGlobal ( ) ; EVT PtrVT = Op . getValueType ( ) ; if ( ! shouldEmitGOTReloc ( GV , getTargetMachine ( ) ) ) return buildPCRelGlobalAddress ( DAG , GV , DL , GSD -> getOffset ( ) , PtrVT ) ; SDValue GOTAddr = buildPCRelGlobalAddress ( DAG , GV , DL , <NUM_LIT> , PtrVT , <ISA_LIT>InstrInfo :: MO_GOTPCREL ) ; Type * Ty = PtrVT . getTypeForEVT ( * DAG . getContext ( ) ) ; PointerType * PtrTy = PointerType :: get ( Ty , <ISA_LIT>AS


<s> if ( TARGET_ARCH64 && type != <NUM_LIT> && AGGREGATE_TYPE_P ( type ) ) return upward ; return DEFAULT_FUNCTION_ARG_PADDING ( mode , type


<s> unsigned Register = <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . getRegister ( RegNo ) ; Inst . addOperand ( MCOperand :: createReg ( Register ) ) ; return Success