<s> EltVT = <STR_LIT> ; VecVT = <STR_LIT> ; EltMask = DAG . getConstant ( <NUM_LIT> , EltVT ) ; if ( ! VT . isVector ( ) ) { VecVal1 = DAG . getTargetInsertSubreg ( <STR_LIT> , DL , VecVT , DAG . getUNDEF ( VecVT ) , In1 ) ; VecVal2 = DAG . getTargetInsertSubreg ( <STR_LIT> , DL , VecVT , DAG . getUNDEF ( VecVT ) , In2 ) ; } else { VecVal1 = DAG . getNode ( <STR_LIT> , DL , VecVT , In1 ) ; VecVal2 = DAG . getNode ( <STR_LIT> , DL , VecVT , In2 ) ; } } else { llvm_unreachable ( <STR_LIT> ) ; } std :: vector < SDValue > BuildVectorOps ; for ( unsigned i = <NUM_LIT> ; i < VecVT . getVectorNumElements ( ) ; ++ i ) BuildVectorOps . push_back ( EltMask ) ; SDValue BuildVec = DAG . getNode ( <STR_LIT> , DL , VecVT , BuildVectorOps ) ; if ( VT == <STR_LIT> || VT == <STR_LIT> ) { BuildVec = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , BuildVec ) ; BuildVec = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , BuildVec ) ; BuildVec = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , BuildVec ) ; } SDValue Sel = DAG . getNode ( <STR_LIT> , DL , VecVT , VecVal1 , VecVal2 , BuildVec ) ; if ( VT == <STR_LIT> ) return DAG . getTargetExtractSubreg ( <STR_LIT> , DL , VT , Sel ) ; else if ( VT == <STR_LIT> ) return DAG . getTargetExtractSubreg ( <STR_LIT>


<s> while ( Op . getOpcode ( ) == <STR_LIT> ) Op = Op . getOperand ( <NUM_LIT> ) ; BuildVectorSDNode * BVN = dyn_cast < BuildVectorSDNode > ( Op . getNode ( ) ) ; APInt SplatBits ,


<s> } } PN -> addOperand ( MachineOperand :: CreateReg ( NewPR , false ) ) ; PN -> addOperand ( MachineOperand :: CreateMBB ( NewPH ) ) ; } } else { assert ( Header -> pred_size ( ) == <NUM_LIT> ) ; for ( instr_iterator I = Header -> instr_begin ( ) , E = Header -> instr_end ( ) ; I != E && I -> isPHI ( ) ; ++ I ) { MachineInstr * PN = & * I ; for ( unsigned i = <NUM_LIT> , n = PN -> getNumOperands ( ) ; i < n ; i += <NUM_LIT> ) { MachineOperand & MO = PN -> getOperand ( i + <NUM_LIT> ) ; if ( MO . getMBB ( ) != Latch ) MO . setMBB ( NewPH ) ; } } } SmallVector < MachineOperand , <NUM_LIT> > Tmp2 ; SmallVector < MachineOperand , <NUM_LIT> > EmptyCond ; TB = FB = nullptr ; for ( MBBVector :: iterator I = Preds . begin ( ) , E = Preds . end ( ) ; I != E ; ++ I ) { MachineBasicBlock * PB = * I ; if ( PB != Latch ) { Tmp2 . clear ( ) ; bool NotAnalyzed = TII -> analyzeBranch ( * PB , TB , FB , Tmp2 , false ) ; ( void ) NotAnalyzed ; assert ( ! NotAnalyzed && <STR_LIT> ) ; if ( TB != Header && ( Tmp2 . empty ( ) || FB != Header ) ) TII -> insertBranch ( * PB , NewPH , nullptr , EmptyCond , DL ) ; PB -> ReplaceUsesOfBlockWith ( Header , NewPH ) ; } } TB = FB = nullptr ; bool LatchNotAnalyzed = TII -> analyzeBranch ( * Latch , TB , FB , Tmp2 , false ) ; ( void ) LatchNotAnalyzed ; assert ( ! LatchNotAnalyzed && <STR_LIT> ) ; if ( ! TB && ! FB ) TII -> insertBranch ( * Latch , Header , nullptr , EmptyCond , DL ) ; TII -> insertBranch ( * NewPH , Header ,


<s> MachineBasicBlock * thisMBB = BB ; MachineFunction * F = BB -> getParent ( ) ; MachineBasicBlock * copy0MBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * copy1MBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; <STR_LIT> CC = ( <STR_LIT> ) MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; BuildMI ( BB , dl , TII . getBrCond ( CC ) ) . addMBB ( copy1MBB ) ; F -> insert ( I , copy0MBB ) ; F -> insert ( I , copy1MBB ) ; for ( MachineBasicBlock :: succ_iterator SI = BB -> succ_begin ( ) , SE = BB -> succ_end ( ) ; SI != SE ; ++ SI ) EM -> insert ( std :: make_pair ( * SI , copy1MBB ) ) ; copy1MBB -> transferSuccessors ( BB ) ; BB -> addSuccessor ( copy0MBB ) ; BB -> addSuccessor ( copy1MBB ) ; BB = copy0MBB ; BB -> addSuccessor ( copy1MBB ) ; BB = copy1MBB ; BuildMI ( BB , dl , TII . get ( <STR_LIT> ) , MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addMBB ( copy0MBB ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addMBB ( thisMBB ) ; F -> DeleteMachineInstr ( MI


<s> return ( __m256i ) __builtin_ia32_pmovsxbw256 ( ( __v16qi


<s> bool KillInputReg = false ; if ( ! Subtarget -> is64Bit ( ) ) { const TargetRegisterClass * CopyRC = ( SrcVT == <STR_LIT> ) ? & <STR_LIT> : & <STR_LIT> ; unsigned CopyReg = createResultReg ( CopyRC ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: COPY ) , CopyReg ) . addReg ( InputReg ) ; InputReg = CopyReg ; KillInputReg = true ; } unsigned ResultReg = fastEmitInst_extractsubreg ( <STR_LIT> , InputReg , KillInputReg , <STR_LIT> ) ; if ( ! ResultReg ) return false ; updateValueMap ( I , ResultReg ) ; return true


<s> return ( uint32_t ) __builtin_neon_vget_laneuv2si ( ( int32x2_t )


<s> void rs6000_emit_le_vsx_store ( rtx dest , rtx source , machine_mode mode ) { gcc_assert ( can_create_pseudo_p ( ) ) ; if ( mode == TImode || mode == V1TImode ) { mode = V2DImode


<s> if ( avr_mem_flash_p ( src ) || avr_mem_flash_p ( dest ) ) { return avr_out_lpm ( insn , operands , plen ) ; } gcc_assert ( <NUM_LIT> == GET_MODE_SIZE ( GET_MODE ( dest ) ) ) ; if ( REG_P ( dest ) ) { if ( REG_P ( src ) ) { if ( test_hard_reg_class ( STACK_REG , dest ) ) return avr_asm_len ( <STR_LIT> , operands , plen , - <NUM_LIT> ) ; else if ( test_hard_reg_class ( STACK_REG , src ) ) return avr_asm_len ( <STR_LIT> , operands , plen , - <NUM_LIT> ) ; return avr_asm_len ( <STR_LIT> , operands , plen , - <NUM_LIT> ) ; } else if ( CONSTANT_P ( src ) ) { output_reload_in_const ( operands , NULL_RTX , plen , false ) ; return <STR_LIT> ; } else if ( MEM_P ( src ) ) return out_movqi_r_mr ( insn , operands , plen ) ; } else if ( MEM_P ( dest ) ) { rtx xop [ <NUM_LIT> ] ; xop [ <NUM_LIT> ] = dest ; xop [ <NUM_LIT> ] = src == CONST0_RTX ( GET_MODE


<s> O << '#' << MI -> getOperand ( OpNum ) . getImm


<s> SmallVector < CCValAssign , <NUM_LIT> > RVLocs ; CCState CCInfo ( CallConv , isVarArg , MF , RVLocs , Context ) ; if ( ! CCInfo . CheckReturn ( Outs , RetCC_<ISA_LIT>


<s> if ( SR1 ) * SR1 = R0 ; if ( SR2 ) { assert ( SR1 && <STR_LIT> ) ; * SR2 = R12 ; } if ( ( UseAtEnd && MBB -> isReturnBlock ( ) ) || ( ! UseAtEnd && ( & MBB -> getParent ( ) -> front ( ) == MBB ) ) ) return true ; RS . enterBasicBlock ( * MBB ) ; if ( UseAtEnd && ! MBB -> empty ( ) ) { MachineBasicBlock :: iterator MBBI = MBB -> getFirstTerminator ( ) ; if ( MBBI == MBB -> end ( ) ) MBBI = std :: prev ( MBBI ) ; if ( MBBI != MBB -> begin ( ) ) RS . forward ( MBBI ) ; } if ( ! RS . isRegUsed ( R0 ) && ! RS . isRegUsed ( R12 ) ) return true ; const <ISA_LIT>RegisterInfo * RegInfo = Subtarget . getRegisterInfo ( ) ; const MCPhysReg * CSRegs = RegInfo -> getCalleeSavedRegs ( MBB -> getParent ( ) ) ; BitVector BV = RS . getRegsAvailable ( Subtarget . is<ISA_LIT>64 ( ) ? & <STR_LIT> : & <STR_LIT> ) ; for ( int i = <NUM_LIT> ; CSRegs [ i ] ; ++ i ) BV . reset ( CSRegs [ i ] ) ; if ( SR1 ) { int FirstScratchReg = BV . find_first ( ) ; * SR1 = FirstScratchReg == - <NUM_LIT> ? ( unsigned ) <STR_LIT> : FirstScratchReg ; } if ( SR2 ) { int SecondScratchReg = BV . find_next ( * SR1 ) ; if ( SecondScratchReg != - <NUM_LIT> )


<s> if ( info -> altivec_save_offset ) fprintf ( stderr , <STR_LIT> , info -> altivec_save_offset ) ; if ( info -> spe_gp_save_offset ) fprintf ( stderr , <STR_LIT> , info -> spe_gp_save_offset ) ; if ( info -> vrsave_save_offset ) fprintf ( stderr , <STR_LIT> , info -> vrsave_save_offset ) ; if ( info -> lr_save_offset ) fprintf ( stderr , <STR_LIT> , info -> lr_save_offset ) ; if ( info -> cr_save_offset ) fprintf ( stderr , <STR_LIT> , info -> cr_save_offset ) ; if ( info -> toc_save_offset ) fprintf ( stderr , <STR_LIT> , info -> toc_save_offset ) ; if ( info -> varargs_save_offset ) fprintf ( stderr , <STR_LIT> , info -> varargs_save_offset ) ; if ( info -> total_size ) fprintf ( stderr , <STR_LIT> HOST_WIDE_INT_PRINT_DEC <STR_LIT> , info -> total_size ) ; if ( info -> vars_size ) fprintf ( stderr , <STR_LIT> HOST_WIDE_INT_PRINT_DEC <STR_LIT> , info -> vars_size ) ; if ( info -> parm_size ) fprintf ( stderr , <STR_LIT> , info -> parm_size ) ; if ( info -> fixed_size ) fprintf ( stderr , <STR_LIT> , info -> fixed_size ) ; if ( info -> gp_size ) fprintf ( stderr , <STR_LIT> , info -> gp_size ) ; if ( info -> spe_gp_size ) fprintf ( stderr , <STR_LIT> , info -> spe_gp_size ) ; if ( info -> fp_size ) fprintf ( stderr , <STR_LIT> , info -> fp_size ) ; if ( info -> altivec_size ) fprintf ( stderr , <STR_LIT> , info -> altivec_size ) ; if ( info -> vrsave_size ) fprintf ( stderr , <STR_LIT> , info -> vrsave_size ) ; if ( info -> altivec_padding_size ) fprintf ( stderr , <STR_LIT> , info -> altivec_padding_size ) ; if ( info -> spe_padding_size ) fprintf ( stderr , <STR_LIT> , info -> spe_padding_size ) ; if ( info -> lr_size ) fprintf ( stderr , <STR_LIT> ,


<s> return wi :: umin ( wi :: to_wide ( TYPE_SIZE ( type ) ) , <NUM_LIT>


<s> printPredicateOperand ( MI , <NUM_LIT> , O ) ; if ( Opcode == <STR_LIT> ) O << <STR_LIT> ; printAnnotation ( O , Annot ) ; return ; } if ( Opcode == <STR_LIT> ) { const MCOperand & Dst = MI -> getOperand ( <NUM_LIT> ) ; const MCOperand & MO1 = MI -> getOperand ( <NUM_LIT> ) ; const MCOperand & MO2 = MI -> getOperand ( <NUM_LIT> ) ; const MCOperand & MO3 = MI -> getOperand ( <NUM_LIT> ) ; O << '\t' << <STR_LIT> ( <STR_LIT> ( MO3 . getImm ( ) ) ) ; printSBitModifierOperand ( MI , <NUM_LIT> , O ) ; printPredicateOperand ( MI , <NUM_LIT> , O ) ; O << '\t' ; printRegName ( O , Dst . getReg ( ) ) ; O << <STR_LIT> ; printRegName ( O , MO1 . getReg ( ) ) ; O << <STR_LIT> ; printRegName ( O , MO2 . getReg ( ) ) ; assert ( <STR_LIT> ( MO3 . getImm ( ) ) == <NUM_LIT> ) ; printAnnotation ( O , Annot ) ; return ; } if ( Opcode == <STR_LIT> ) { const MCOperand & Dst = MI -> getOperand ( <NUM_LIT> ) ; const MCOperand & MO1 = MI -> getOperand ( <NUM_LIT> ) ; const MCOperand & MO2 = MI -> getOperand ( <NUM_LIT> ) ; O << '\t' << <STR_LIT> ( <STR_LIT> ( MO2 . getImm ( ) ) ) ; printSBitModifierOperand ( MI , <NUM_LIT> , O ) ; printPredicateOperand ( MI , <NUM_LIT> , O ) ; O << '\t' ; printRegName ( O , Dst . getReg ( ) ) ; O << <STR_LIT> ; printRegName ( O , MO1 . getReg ( ) ) ; if ( <STR_LIT> ( MO2 . getImm ( ) ) == <STR_LIT> ) { printAnnotation ( O , Annot ) ; return ; } O << <STR_LIT> << markup ( <STR_LIT> ) << <STR_LIT> << translateShiftImm ( <STR_LIT> ( MO2 . getImm ( ) ) ) << markup ( <STR_LIT> ) ; printAnnotation ( O , Annot ) ; return ; } if ( ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) && MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> && MI -> getNumOperands ( ) > <NUM_LIT> ) { O << '\t' << <STR_LIT> ; printPredicateOperand ( MI , <NUM_LIT> , O ) ; if ( Opcode == <STR_LIT> ) O << <STR_LIT> ; O << '\t' ; printRegisterList ( MI , <NUM_LIT> , O ) ; printAnnotation ( O , Annot ) ; return ; } if ( Opcode == <STR_LIT> && MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> && MI -> getOperand ( <NUM_LIT> ) . getImm ( ) == - <NUM_LIT> ) { O << '\t' << <STR_LIT> ; printPredicateOperand ( MI , <NUM_LIT>


<s> void addDupAlignedMemory16Operands ( MCInst & Inst , unsigned N


<s> bool <ISA_LIT>InstrInfo :: isPredicated ( const MachineInstr * MI ) const { int i = MI ->


<s> const <ISA_LIT>Subtarget & STI = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; const <ISA_LIT>InstrInfo & TII = * STI . getInstrInfo ( ) ; assert ( STI . isTargetWin64 ( ) && <STR_LIT> ) ; if ( ! MF . hasWinCFI ( ) ) return false ; bool Changed = false ; for ( MachineBasicBlock & MBB : MF ) { MachineBasicBlock * NextMBB = MBB . getNextNode ( ) ; if ( NextMBB && ! NextMBB -> isEHFuncletEntry ( ) ) continue ; auto LastRealInstr = llvm :: find_if ( reverse ( MBB ) , isRealInstruction ) ; bool IsEmpty = LastRealInstr == MBB . rend ( ) ; bool IsCall = ! IsEmpty && isCallInstruction ( * LastRealInstr ) ; if ( IsEmpty || IsCall ) { LLVM_DEBUG ( { if ( IsCall ) { dbgs ( ) << <STR_LIT> ; LastRealInstr -> dump ( ) ; dbgs ( ) << '\n' ; } else { dbgs ( ) << <STR_LIT> ; MBB . dump ( ) ; } } ) ; MachineBasicBlock :: iterator MBBI = MBB .


<s> if ( RegNo >= <NUM_LIT> ) return MCDisassembler :: Fail ; Register Reg = <STR_LIT> + RegNo ; Inst . addOperand ( MCOperand :: createReg ( Reg ) ) ; return MCDisassembler ::


<s> JumpTableSDNode * N = cast < JumpTableSDNode > ( Op ) ; return getAddr ( N ,


<s> static unsigned getPreIndexedLoadStoreOpcode ( unsigned Opc ) { switch ( Opc ) { case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : return


<s> else if ( REG_P ( op1 ) && CONSTANT_P ( op0 ) ) { output_addr_const ( file , op0 ) ; fprintf ( file , <STR_LIT> , reg_names [ REGNO ( op1 ) ] ) ; return ; } } break ; case REG : fprintf ( file , <STR_LIT> , reg_names [ REGNO ( op ) ] ) ; return ; case MEM : { rtx base = XEXP ( op , <NUM_LIT> ) ; nios2_print_operand_address ( file , base ) ; return ; } default : break ; } fprintf ( stderr , <STR_LIT> ) ; debug_rtx ( op ) ; gcc_unreachable (


<s> bool isLegalMaskedLoadStore ( Type * DataType , Align Alignment ) { if ( ! ST -> hasSVE ( ) ) return false ; if ( isa < FixedVectorType > ( DataType ) && ! ST -> useSVEForFixedLengthVectors ( ) ) return false ; return isElementTypeLegalForScalableVector ( DataType ->


<s> Sym = cast < MCSymbolWasm > ( Ctx . getOrCreateSymbol ( Name ) ) ; Sym -> setFunctionTable ( ) ; Sym -> setUndefined ( ) ; } return Sym


<s> void <ISA_LIT>FrameLowering :: emitEpilogue ( MachineFunction & MF , MachineBasicBlock & MBB ) const { MachineBasicBlock :: iterator MBBI = MBB . getLastNonDebugInstr ( ) ; DebugLoc dl = MBBI -> getDebugLoc ( ) ; MachineFrameInfo & MFI = MF . getFrameInfo


<s> else if ( TARGET_PORTABLE_RUNTIME ) { output_asm_insn ( <STR_LIT> , xoperands ) ; output_asm_insn ( <STR_LIT> , xoperands ) ; if ( ! val_14 ) output_asm_insn ( <STR_LIT> , xoperands ) ; output_asm_insn ( <STR_LIT> , xoperands ) ; if ( val_14 ) { output_asm_insn ( <STR_LIT> , xoperands ) ; nbytes += <NUM_LIT> ; } else { output_asm_insn ( <STR_LIT> , xoperands ) ; nbytes += <NUM_LIT> ; } } else if ( TARGET_SOM && flag_pic && TREE_PUBLIC ( function ) ) { ASM_GENERATE_INTERNAL_LABEL ( label , <STR_LIT> , current_thunk_number ) ; xoperands [ <NUM_LIT> ] = gen_rtx_SYMBOL_REF ( Pmode , label ) ; output_asm_insn ( <STR_LIT> , xoperands ) ; output_asm_insn ( <STR_LIT> , xoperands ) ; output_asm_insn ( <STR_LIT> , xoperands ) ; output_asm_insn ( <STR_LIT> , xoperands ) ; output_asm_insn ( <STR_LIT> , xoperands ) ; output_asm_insn ( <STR_LIT> , xoperands ) ; output_asm_insn ( <STR_LIT> , xoperands ) ; if ( ! val_14 ) { output_asm_insn ( <STR_LIT> , xoperands ) ; nbytes += <NUM_LIT> ; } if ( TARGET_PA_20 ) { output_asm_insn ( <STR_LIT> , xoperands ) ; nbytes += <NUM_LIT> ; } else if ( TARGET_NO_SPACE_REGS ) { output_asm_insn ( <STR_LIT> , xoperands ) ; nbytes += <NUM_LIT> ; } else { output_asm_insn ( <STR_LIT> , xoperands ) ; output_asm_insn ( <STR_LIT> , xoperands ) ; output_asm_insn ( <STR_LIT> , xoperands ) ; nbytes += <NUM_LIT> ; } if ( val_14 ) output_asm_insn ( <STR_LIT> , xoperands ) ; else output_asm_insn ( <STR_LIT> , xoperands ) ; } else if ( flag_pic ) { output_asm_insn ( <STR_LIT> , xoperands ) ; if ( TARGET_SOM || ! TARGET_GAS ) { output_asm_insn ( <STR_LIT> , xoperands ) ; output_asm_insn ( <STR_LIT> , xoperands ) ; } else { output_asm_insn ( <STR_LIT> , xoperands ) ; output_asm_insn ( <STR_LIT> , xoperands ) ; } if ( ! val_14 ) output_asm_insn ( <STR_LIT> , xoperands ) ; output_asm_insn ( <STR_LIT> , xoperands ) ; if ( val_14 ) { output_asm_insn ( <STR_LIT> , xoperands ) ; nbytes += <NUM_LIT> ; } else { output_asm_insn ( <STR_LIT> , xoperands ) ; nbytes += <NUM_LIT> ; } } else { if ( ! val_14 ) output_asm_insn ( <STR_LIT> , xoperands ) ; output_asm_insn ( <STR_LIT> , xoperands ) ; output_asm_insn ( <STR_LIT> , xoperands ) ; if ( val_14 ) { output_asm_insn ( <STR_LIT> , xoperands ) ; nbytes += <NUM_LIT> ; } else { output_asm_insn ( <STR_LIT> , xoperands ) ; nbytes += <NUM_LIT> ; } } fprintf ( file , <STR_LIT> ) ; if ( TARGET_SOM && flag_pic && TREE_PUBLIC ( function ) ) { data_section ( ) ; output_asm_insn ( <STR_LIT> , xoperands ) ; ASM_OUTPUT_LABEL ( file , label ) ; output_asm_insn ( <STR_LIT> , xoperands ) ; } else if ( TARGET_SOM && TARGET_GAS


<s> static DecodeStatus DecodeThumbBCCTargetOperand ( llvm :: MCInst & Inst , unsigned Val , uint64_t Address , const void * Decoder ) { Inst . addOperand ( MCOperand :: CreateImm ( Val << <NUM_LIT> )


<s> void DecodeMOVHLPSMask ( unsigned NElts , SmallVectorImpl < unsigned > & ShuffleMask ) { for ( unsigned i = NElts / <NUM_LIT> ; i != NElts ; ++ i ) ShuffleMask . push_back ( NElts


<s> unsigned RegNo ; matchRegisterNameHelper ( isRV32E ( ) , RegNo , Name ) ; if ( RegNo == <NUM_LIT> ) { if ( HadParens ) getLexer ( ) . UnLex ( Buf [ <NUM_LIT> ] ) ; return MatchOperand_NoMatch ; } if ( HadParens ) Operands . push_back ( <ISA_LIT>Operand :: createToken ( <STR_LIT> , FirstS , isRV64 ( ) ) ) ; SMLoc S = getLoc ( ) ; SMLoc E = SMLoc :: getFromPointer ( S . getPointer ( ) - <NUM_LIT> ) ; getLexer ( ) . Lex ( ) ; Operands . push_back ( <ISA_LIT>Operand :: createReg ( RegNo , S , E , isRV64 ( ) ) ) ; } if ( HadParens ) { getParser ( ) . Lex ( ) ; Operands . push_back ( <ISA_LIT>Operand :: createToken ( <STR_LIT> , getLoc ( ) , isRV64 ( ) ) ) ; } return


<s> Op0 = constrainOperandRegClass ( II , Op0 , <NUM_LIT> ) ; if ( II . getNumDefs ( ) >= <NUM_LIT> ) { AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , II , ResultReg ) . addReg ( Op0 ) . addImm ( Imm ) ) ; } else { AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , II ) . addReg ( Op0 ) . addImm ( Imm ) ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: COPY ) , ResultReg ) . addReg ( II . ImplicitDefs [ <NUM_LIT> ] ) ) ; } return ResultReg


<s> if ( MI -> isCall ( ) ) { for ( auto I : MBB -> successors ( ) ) if ( I -> isEHPad ( ) ) return true ; } if ( MI -> getOpcode ( ) == <STR_LIT> ) return true ; if ( MI -> getDesc ( ) . isTerminator ( ) || MI -> isPosition ( ) ) return true ; if ( MI -> isInlineAsm ( ) && !


<s> for ( ++ MII ; MII != MBB -> instr_end ( ) && MII -> isInsideBundle ( ) ; ++ MII ) if ( ! MII -> isDebugInstr ( ) && ! MII -> isImplicitDef ( ) ) <ISA_LIT>LowerToMC ( MCII , & * MII , MCB , * this ) ; } else { <ISA_LIT>LowerToMC ( MCII , MI , MCB , * this ) ; } const MachineFunction & MF = * MI -> getParent ( ) -> getParent ( ) ; const auto & HII = * MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getInstrInfo ( ) ; if ( MI -> isBundle ( ) && HII . getBundleNoShuf ( * MI ) ) <ISA_LIT>MCInstrInfo :: setMemReorderDisabled ( MCB ) ; MCContext & Ctx = OutStreamer -> getContext ( ) ; bool Ok = <ISA_LIT>MCInstrInfo :: canonicalizePacket ( MCII , * Subtarget , Ctx , MCB , nullptr ) ; assert ( Ok ) ; ( void )


<s> I = Attribute :: AttrKind ( I + <NUM_LIT> ) ) { if ( ! isValidFor<ISA_LIT> ( I ) ) AttrMask . addAttribute ( I ) ; } for ( auto & F : M . functions ( ) ) { F . removeFnAttrs ( AttrMask ) ; F . removeRetAttrs ( AttrMask ) ; for ( size_t Idx = <NUM_LIT> ; Idx < F . arg_size ( ) ; ++ Idx ) F . removeParamAttrs ( Idx , AttrMask ) ; for ( auto & BB : F ) { IRBuilder < > Builder ( & BB ) ; for ( auto & I : make_early_inc_range ( BB ) ) { if ( I . getOpcode ( ) == Instruction :: FNeg ) { Builder . SetInsertPoint (


<s> void <ISA_LIT>InstPrinter :: printRegister ( unsigned RegNo , raw_ostream & O ) const { O << '$' << getRegisterName


<s> unsigned CFIIndex = MF . addFrameInst ( MCCFIInstruction :: createDefCfaRegister ( nullptr , DRegNum ) ) ; BuildMI ( MBB , MBBI , dl , TII . get ( TargetOpcode :: CFI_INSTRUCTION ) ) .


<s> if ( ! VT . isVector ( ) || ! VT . isSimple ( ) || ! ( VT . getVectorElementType ( ) == <STR_LIT> ) ) return SDValue ( ) ; unsigned RegSize = <NUM_LIT> ; if ( Subtarget . useBWIRegs ( ) ) RegSize = <NUM_LIT> ; else if ( Subtarget . hasAVX ( ) ) RegSize = <NUM_LIT> ; if ( VT . getSizeInBits ( ) / <NUM_LIT> > RegSize ) return SDValue ( ) ; if ( Op0 . getOpcode ( ) != <STR_LIT> ) std :: swap ( Op0 , Op1 ) ; if ( Op0 . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; auto BuildPSADBW = [ & ] ( SDValue Op0 , SDValue Op1 ) { SDValue Sad = createPSADBW ( DAG , Op0 , Op1 , DL ,


<s> Res = <NUM_LIT> ; std :: string Text = Tok . getString ( ) . str ( ) ; if ( Text . size ( ) > <NUM_LIT> ) { return true ; } std :: transform ( Text . begin ( ) , Text . end ( ) , Text . begin ( ) , [ ] ( unsigned char C ) { return std :: tolower ( C ) ; } ) ; for ( char Letter : Text ) { signed char Converted = hexToChar ( Letter ) ; if ( Converted == - <NUM_LIT> ) { return


<s> if ( ReturnAddrIndex == <NUM_LIT> ) { unsigned SlotSize = Subtarget . getSlotSize ( ) ; ReturnAddrIndex = MF . getFrameInfo ( ) . CreateFixedObject ( SlotSize , - ( int64_t ) SlotSize , false ) ; FuncInfo -> setRAIndex ( ReturnAddrIndex ) ; } return DAG . getFrameIndex ( ReturnAddrIndex , getPointerTy (


<s> if ( I -> getOpcode ( ) == <STR_LIT> ) { Opnds . push_back ( I -> getOperand ( <NUM_LIT> ) ) ; Opnds . push_back ( I -> getOperand ( <NUM_LIT> ) ) ; e += <NUM_LIT> ; continue ; } if ( I -> getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; SDValue Idx = I -> getOperand ( <NUM_LIT> ) ; if ( ! isa < ConstantSDNode > ( Idx ) ) return SDValue ( ) ; SDValue ExtractedFromVec = I -> getOperand ( <NUM_LIT> ) ; DenseMap < SDValue , unsigned > :: iterator M = VecInMap . find ( ExtractedFromVec ) ; if ( M == VecInMap . end ( ) ) { VT = ExtractedFromVec . getValueType ( ) ; if ( ! VT . is128BitVector ( ) && ! VT . is256BitVector ( ) ) return SDValue ( ) ; if ( VecInMap . begin ( ) != VecInMap . end ( ) && VT != VecInMap . begin ( ) -> first . getValueType ( ) ) return SDValue ( ) ; M = VecInMap . insert ( std :: make_pair ( ExtractedFromVec , <NUM_LIT> ) ) . first ; } M -> second |= <NUM_LIT> << cast < ConstantSDNode > ( Idx ) -> getZExtValue ( ) ; } assert ( ( VT . is128BitVector ( ) || VT . is256BitVector ( ) ) && <STR_LIT> ) ; unsigned FullMask = ( <NUM_LIT> << VT . getVectorNumElements ( ) ) - <NUM_LIT> ; SmallVector < SDValue , <NUM_LIT> > VecIns ; for ( DenseMap < SDValue , unsigned > :: const_iterator I = VecInMap . begin ( ) , E = VecInMap . end ( ) ; I != E ; ++ I ) { if ( I -> second != FullMask ) return SDValue ( ) ; VecIns . push_back ( I -> first ) ; } EVT TestVT = VT . is128BitVector ( ) ? <STR_LIT> : <STR_LIT> ; for ( unsigned i = <NUM_LIT> , e = VecIns . size ( ) ; i < e ; ++ i ) VecIns [ i ] = DAG . getNode ( <STR_LIT> , DL , TestVT , VecIns [ i ] ) ; for ( unsigned Slot = <NUM_LIT> , e = VecIns . size ( ) ; e - Slot > <NUM_LIT> ; Slot += <NUM_LIT> , e += <NUM_LIT> ) { SDValue LHS = VecIns [ Slot ] ; SDValue RHS = VecIns [ Slot


<s> rtx body = PATTERN ( insn ) ; int elt = GET_CODE ( body ) == ADDR_DIFF_VEC ? <NUM_LIT> : <NUM_LIT> ; return GET_MODE_SIZE ( GET_MODE ( body ) ) * XVECLEN ( body , elt ) ; } return


<s> return ( poly64x1_t ) __builtin_neon_vreinterpretdiv2si ( ( int32x2_t )


<s> bool hasAVX ( ) const { return HasAVX


<s> MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; return MRI . createVirtualRegister ( ST . isWave32 ( ) ? & <STR_LIT> :


<s> void llvm :: clearAnnotationCache ( const


<s> unsigned TlsReg , TlsOffset ; DebugLoc DL ; unsigned ScratchReg = GetScratchRegister ( Is64Bit , IsLP64 , MF , true ) ; assert ( ! MF . getRegInfo ( ) . isLiveIn ( ScratchReg ) && <STR_LIT> ) ; if ( MF . getFunction ( ) -> isVarArg ( ) ) report_fatal_error ( <STR_LIT> ) ; if ( ! STI . isTargetLinux ( ) && ! STI . isTargetDarwin ( ) && ! STI . isTargetWin32 ( ) && ! STI . isTargetWin64 ( ) && ! STI . isTargetFreeBSD ( ) && ! STI . isTargetDragonFly ( ) ) report_fatal_error ( <STR_LIT> ) ; StackSize = MFI -> getStackSize ( ) ; if ( StackSize == <NUM_LIT> ) return ; MachineBasicBlock * allocMBB = MF . CreateMachineBasicBlock ( ) ; MachineBasicBlock * checkMBB = MF . CreateMachineBasicBlock ( ) ; <ISA_LIT>MachineFunctionInfo * <ISA_LIT>FI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; bool IsNested = false ; if ( Is64Bit ) IsNested = HasNestArgument ( & MF ) ; for ( MachineBasicBlock :: livein_iterator i = PrologueMBB . livein_begin ( ) , e = PrologueMBB . livein_end ( ) ; i != e ; i ++ ) { allocMBB -> addLiveIn ( * i ) ; checkMBB -> addLiveIn ( * i ) ; } if ( IsNested ) allocMBB -> addLiveIn ( IsLP64 ? <STR_LIT> : <STR_LIT> ) ; MF . push_front ( allocMBB ) ; MF . push_front ( checkMBB ) ; bool CompareStackPointer = StackSize < kSplitStackAvailable ; if ( Is64Bit ) { if ( STI . isTargetLinux ( ) ) { TlsReg = <STR_LIT> ; TlsOffset = IsLP64 ? <NUM_LIT> : <NUM_LIT> ; } else if ( STI . isTargetDarwin ( ) ) { TlsReg = <STR_LIT> ; TlsOffset = <NUM_LIT> + <NUM_LIT> * <NUM_LIT> ; } else if ( STI . isTargetWin64 ( ) ) { TlsReg = <STR_LIT> ; TlsOffset = <NUM_LIT> ; } else if ( STI . isTargetFreeBSD ( ) ) { TlsReg = <STR_LIT> ; TlsOffset = <NUM_LIT> ; } else if ( STI . isTargetDragonFly ( ) ) { TlsReg = <STR_LIT> ; TlsOffset = <NUM_LIT> ; } else { report_fatal_error ( <STR_LIT> ) ; } if ( CompareStackPointer ) ScratchReg = IsLP64 ? <STR_LIT> : <STR_LIT> ; else BuildMI ( checkMBB , DL , TII . get ( IsLP64 ? <STR_LIT> : <STR_LIT> ) , ScratchReg ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) . addImm ( - StackSize ) . addReg ( <NUM_LIT> ) ; BuildMI ( checkMBB , DL , TII . get ( IsLP64 ? <STR_LIT> : <STR_LIT> ) ) . addReg ( ScratchReg ) . addReg

( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) . addImm ( TlsOffset ) . addReg ( TlsReg ) ;


<s> AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , II ) . addReg ( Op0 ) . addImm ( Imm ) ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: COPY ) , ResultReg ) . addReg (


<s> if ( DstBank -> getID ( ) != <STR_LIT> ) return false ; Register Src0 = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register Src1 = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( MRI -> getType ( Src0 ) != S32 ) return false ; const DebugLoc & DL = MI . getDebugLoc ( ) ; MachineBasicBlock * BB = MI . getParent ( ) ; auto ConstSrc1 = getConstantVRegValWithLookThrough ( Src1 , * MRI , true , true , true ) ; if ( ConstSrc1 ) { auto ConstSrc0 = getConstantVRegValWithLookThrough ( Src0 , * MRI , true , true , true ) ; if ( ConstSrc0 ) { const int64_t K0 = ConstSrc0 -> Value . getSExtValue ( ) ; const int64_t K1 = ConstSrc1 -> Value . getSExtValue ( ) ; uint32_t Lo16 = static_cast < uint32_t > ( K0 ) & <NUM_LIT> ; uint32_t Hi16 = static_cast < uint32_t > ( K1 ) & <NUM_LIT> ; BuildMI ( * BB , & MI , DL , TII . get ( <STR_LIT> ) , Dst ) . addImm ( Lo16 | ( Hi16 << <NUM_LIT> ) ) ; MI . eraseFromParent ( ) ; return RBI . constrainGenericRegister ( Dst , <STR_LIT> , * MRI ) ; } } MachineInstr * Src1Def = getDefIgnoringCopies ( Src1 , * MRI ) ; if ( Src1Def && Src1Def -> getOpcode ( ) == <STR_LIT> ) { MI . setDesc ( TII . get ( <STR_LIT> ) ) ; MI . RemoveOperand ( <NUM_LIT> ) ; return RBI . constrainGenericRegister ( Dst , <STR_LIT> , * MRI ) && RBI . constrainGenericRegister ( Src0 , <STR_LIT> , * MRI ) ; } Register ShiftSrc0 ; Register ShiftSrc1 ; bool Shift0 = mi_match ( Src0 , * MRI , m_OneUse ( m_GLShr ( m_Reg ( ShiftSrc0 ) , m_SpecificICst ( <NUM_LIT> ) ) ) ) ; bool Shift1 = mi_match ( Src1 , * MRI , m_OneUse ( m_GLShr ( m_Reg ( ShiftSrc1 ) , m_SpecificICst ( <NUM_LIT> ) ) ) ) ; unsigned Opc = <STR_LIT> ; if ( Shift0 && Shift1 ) { Opc = <STR_LIT> ; MI . getOperand ( <NUM_LIT> ) . setReg ( ShiftSrc0 ) ; MI . getOperand ( <NUM_LIT> ) . setReg ( ShiftSrc1 ) ; } else if ( Shift1


<s> const Function & F = * MF . getFunction ( ) ; return F . optForSize ( ) && ! F . optForMinSize (


<s> isLoadOp = false ; isLaneOp = true ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; NumVecs = <NUM_LIT> ; isLoadOp = false ; hasAlignment = false ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; NumVecs = <NUM_LIT> ; isLoadOp = false ; hasAlignment = false ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; NumVecs = <NUM_LIT> ; isLoadOp = false ; hasAlignment = false ; break ; } } else { isLaneOp = true ; switch ( N -> getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : NewOpc = <STR_LIT> ; NumVecs = <NUM_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; NumVecs = <NUM_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; NumVecs = <NUM_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; NumVecs = <NUM_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; NumVecs = <NUM_LIT> ; isLaneOp = false ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; NumVecs = <NUM_LIT> ; isLaneOp = false ; isLoadOp = false ; break ; } } EVT VecTy ; if ( isLoadOp ) { VecTy = N -> getValueType ( <NUM_LIT> ) ; } else if ( Target . isIntrinsic ) { VecTy = N -> getOperand ( Target . AddrOpIdx + <NUM_LIT> ) . getValueType ( ) ; } else { assert ( Target . isStore && <STR_LIT> ) ; VecTy = N -> getOperand ( <NUM_LIT> ) . getValueType ( ) ; } bool isVLDDUPOp = NewOpc == <STR_LIT> || NewOpc == <STR_LIT> || NewOpc == <STR_LIT> || NewOpc == <STR_LIT> ; unsigned NumBytes = NumVecs * VecTy . getSizeInBits ( ) / <NUM_LIT> ; if ( isLaneOp || isVLDDUPOp ) NumBytes /= VecTy . getVectorNumElements ( ) ; if ( NumBytes >= <NUM_LIT> * <NUM_LIT> && User . ConstInc != NumBytes ) { return false ; } if ( SimpleConstIncOnly && User . ConstInc != NumBytes ) return false ; EVT AlignedVecTy = VecTy ; unsigned Alignment = MemN -> getAlignment ( ) ; if ( isa < LSBaseSDNode > ( N ) ) { if ( Alignment == <NUM_LIT> ) Alignment = <NUM_LIT> ; if ( Alignment < VecTy . getScalarSizeInBits ( ) / <NUM_LIT> ) { MVT EltTy = <STR_LIT> ( Alignment * <NUM_LIT> ) ; assert ( NumVecs == <NUM_LIT> && <STR_LIT> ) ; assert ( ! isLaneOp && <STR_LIT> ) ; unsigned NumElts = NumBytes / ( EltTy . getSizeInBits ( ) / <NUM_LIT> ) ; AlignedVecTy = <STR_LIT> ( EltTy , NumElts ) ; } Alignment = <NUM_LIT> ; } EVT Tys [ <NUM_LIT> ] ; unsigned NumResultVecs = ( isLoadOp ? NumVecs :


<s> for ( auto I : B . liveins ( ) ) if ( ! Reserved [ I . PhysReg ] ) LiveIns . insert ( { I . PhysReg , <NUM_LIT> } ) ; return


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; Inst . addOperand ( MCOperand :: createImm ( CE -> getValue (


<s> switch ( DefMCID . getOpcode ( ) ) { default : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : isSLoad = true ; break ; } if ( ( isSLoad && ( RegNo % <NUM_LIT> ) ) || DefAlign < <NUM_LIT> ) ++ DefCycle ; } else { DefCycle = RegNo + <NUM_LIT> ; } return


<s> case ADDRESS_SPACE_SHARED : Opc = Subtarget -> is64Bit ( ) ? <STR_LIT> : <STR_LIT> ; break ; case ADDRESS_SPACE_CONST : Opc = Subtarget -> is64Bit ( ) ? <STR_LIT> : <STR_LIT> ; break ; case ADDRESS_SPACE_LOCAL : Opc = Subtarget -> is64Bit ( ) ? <STR_LIT> : <STR_LIT> ; break ; } return CurDAG -> getMachineNode ( Opc , SDLoc ( N ) , N -> getValueType ( <NUM_LIT> ) , Src ) ; } else { if ( SrcAddrSpace != <NUM_LIT> ) report_fatal_error ( <STR_LIT> ) ; unsigned Opc ; switch ( DstAddrSpace ) { default : report_fatal_error ( <STR_LIT> ) ; case ADDRESS_SPACE_GLOBAL : Opc = Subtarget -> is64Bit ( ) ? <STR_LIT> : <STR_LIT> ; break ; case ADDRESS_SPACE_SHARED : Opc = Subtarget -> is64Bit ( ) ? <STR_LIT> : <STR_LIT> ; break ; case ADDRESS_SPACE_CONST : Opc = Subtarget -> is64Bit ( ) ? <STR_LIT> : <STR_LIT> ; break ; case ADDRESS_SPACE_LOCAL : Opc = Subtarget -> is64Bit (


<s> if ( ! LDBase ) { if ( Elt . getNode ( ) -> getOpcode ( ) == <STR_LIT> ) return SDValue ( ) ; LDBase = cast < LoadSDNode > ( Elt . getNode ( ) ) ; LastLoadedElt = i ; continue ; } if ( Elt . getOpcode ( ) == <STR_LIT> ) continue ; LoadSDNode * LD = cast < LoadSDNode > ( Elt ) ; if ( ! DAG . isConsecutiveLoad ( LD , LDBase , EltVT . getSizeInBits ( ) / <NUM_LIT> , i ) ) return SDValue ( ) ; LastLoadedElt = i ; } if ( LastLoadedElt == NumElems - <NUM_LIT> ) { SDValue NewLd = SDValue ( ) ; if ( DAG . InferPtrAlignment ( LDBase -> getBasePtr ( ) ) >= <NUM_LIT> ) NewLd = DAG . getLoad ( VT , DL , LDBase -> getChain ( ) , LDBase -> getBasePtr ( ) , LDBase -> getPointerInfo ( ) , LDBase -> isVolatile ( ) , LDBase -> isNonTemporal ( ) , LDBase -> isInvariant ( ) , <NUM_LIT> ) ; NewLd = DAG . getLoad ( VT , DL , LDBase -> getChain ( ) , LDBase -> getBasePtr ( ) , LDBase -> getPointerInfo ( ) , LDBase -> isVolatile ( ) , LDBase -> isNonTemporal ( ) , LDBase -> isInvariant ( ) , LDBase -> getAlignment ( ) ) ; if ( LDBase -> hasAnyUseOfValue ( <NUM_LIT> ) ) { SDValue NewChain = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , SDValue ( LDBase , <NUM_LIT> ) , SDValue ( NewLd . getNode ( ) , <NUM_LIT> ) ) ; DAG . ReplaceAllUsesOfValueWith ( SDValue ( LDBase , <NUM_LIT> ) , NewChain ) ; DAG . UpdateNodeOperands ( NewChain . getNode ( ) , SDValue ( LDBase , <NUM_LIT> ) , SDValue ( NewLd . getNode ( ) , <NUM_LIT> ) ) ; } return


<s> int64_t Offset = StackSize ; unsigned SlotSize = Subtarget . getSlotSize ( ) ; if ( ( Offset & AlignMask ) <= ( StackAlignment - SlotSize ) ) { Offset += ( ( StackAlignment - SlotSize ) - ( Offset & AlignMask )


<s> if ( MI != MBB . end ( ) ) { DL = MI -> getDebugLoc ( ) ; } const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( MF , FrameIndex ) , MachineMemOperand :: MOStore , MFI . getObjectSize ( FrameIndex ) , MFI . getObjectAlignment ( FrameIndex ) ) ; unsigned Opcode = <NUM_LIT> ; if ( RC -> hasType ( <STR_LIT> ) ) { Opcode = <STR_LIT> ; } else if ( RC -> hasType


<s> return ( ( aarch64_tune_params . extra_tuning_flags & AARCH64_EXTRA_TUNE_RENAME_LOAD_REGS ) &&


<s> Sch . BaseClass :: startBlock ( BB ) ; Sch . BaseClass :: enterRegion ( BB , R . Begin , R . End , R . NumRegionInstrs ) ; Sch . buildSchedGraph ( Sch . AA , nullptr ,


<s> static bool isShiftedMask ( uint64_t I , uint64_t & Pos , uint64_t & Size ) { if ( ! isShiftedMask_64 ( I ) ) return false ; Size = CountPopulation_64 ( I ) ; Pos = CountTrailingZeros_64 ( I ) ; return


<s> if ( high == <NUM_LIT> || high == - <NUM_LIT> ) return <NUM_LIT> ; high >>= <NUM_LIT> ; if ( low == <NUM_LIT> ) return num_insns_constant_wide ( high ) + <NUM_LIT> ; else if ( high == <NUM_LIT> ) return

num_insns_constant_wide ( low ) + <NUM_LIT> ;


<s> if ( MEM_P ( operands [ n ] ) ) { rtx tem = operands [ n ] ; operands [ n ] = operands [ n + <NUM_LIT>


<s> case G_FCMP : { assert ( MRI . getType ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) == MRI . getType ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) && <STR_LIT> ) ; auto OpSize = MRI . getType ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) . getSizeInBits ( ) ; auto OriginalResult = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; auto Predicate = static_cast < CmpInst :: Predicate > ( MI . getOperand ( <NUM_LIT> ) . getPredicate ( ) ) ; auto Libcalls = getFCmpLibcalls ( Predicate , OpSize ) ; if ( Libcalls . empty ( ) ) { assert ( ( Predicate == CmpInst :: FCMP_TRUE || Predicate == CmpInst :: FCMP_FALSE ) && <STR_LIT> ) ; MIRBuilder . buildConstant ( OriginalResult , Predicate == CmpInst :: FCMP_TRUE ? <NUM_LIT> : <NUM_LIT> ) ; MI . eraseFromParent ( ) ; return true ; } auto & Ctx = MIRBuilder . getMF ( ) . getFunction ( ) . getContext ( ) ; assert ( ( OpSize == <NUM_LIT> || OpSize == <NUM_LIT> ) && <STR_LIT> ) ; auto * ArgTy = OpSize == <NUM_LIT> ? Type :: getFloatTy ( Ctx ) : Type :: getDoubleTy ( Ctx ) ; auto * RetTy = Type :: getInt32Ty ( Ctx ) ; SmallVector < unsigned , <NUM_LIT> > Results ; for ( auto Libcall : Libcalls ) { auto LibcallResult = MRI . createGenericVirtualRegister ( LLT :: scalar ( <NUM_LIT> ) ) ; auto Status = createLibcall ( MIRBuilder , Libcall . LibcallID , { LibcallResult , RetTy } , { { MI . getOperand ( <NUM_LIT> ) . getReg ( ) , ArgTy } , { MI . getOperand ( <NUM_LIT> ) . getReg ( ) , ArgTy } } ) ; if ( Status != LegalizerHelper :: Legalized ) return false ; auto ProcessedResult = Libcalls . size ( ) == <NUM_LIT> ? OriginalResult : MRI . createGenericVirtualRegister ( MRI . getType ( OriginalResult ) ) ; CmpInst :: Predicate ResultPred = Libcall . Predicate ; if ( ResultPred == CmpInst :: BAD_ICMP_PREDICATE ) { MIRBuilder . buildTrunc ( ProcessedResult , LibcallResult ) ; } else { assert ( CmpInst :: isIntPredicate ( ResultPred ) && <STR_LIT> ) ; auto Zero = MRI . createGenericVirtualRegister ( LLT :: scalar ( <NUM_LIT> ) ) ; MIRBuilder . buildConstant ( Zero , <NUM_LIT> ) ; MIRBuilder . buildICmp ( ResultPred , ProcessedResult , LibcallResult , Zero ) ; } Results . push_back ( ProcessedResult ) ; } if ( Results . size ( ) != <NUM_LIT> ) { assert ( Results . size ( ) == <NUM_LIT> && <STR_LIT> ) ; MIRBuilder . buildOr ( OriginalResult , Results [ <NUM_LIT> ] , Results [ <NUM_LIT> ] ) ; } break ; } } MI . eraseFromParent


<s> const uint32_t * <ISA_LIT>RegisterInfo :: getThisReturnPreservedMask ( CallingConv :: ID CC ) const { assert ( CC != CallingConv


<s> OutMI . setOpcode ( Opcode ) ; for ( unsigned I = <NUM_LIT> , E = <NUM_LIT> ; I != E ; ++ I ) { const MachineOperand & MO = MI -> getOperand ( I ) ; OutMI . addOperand ( LowerOperand ( MO ) ) ; } OutMI . addOperand ( createSub ( MI -> getOperand ( <NUM_LIT> ) . getMBB ( ) , MI ->

getOperand ( <NUM_LIT> ) . getMBB ( ) , Kind ) ) ;


<s> switch ( RC . getID ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return getRegBank ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return getRegBank ( <STR_LIT>


<s> unsigned RHSReg = RHSIsReg ? MI . getOperand ( <NUM_LIT> ) . getReg ( ) : <NUM_LIT> ; bool RHSIsKill = RHSIsReg ? MI . getOperand ( <NUM_LIT> ) . isKill ( ) : false ; int8_t RHSImm = ! RHSIsReg ? MI . getOperand ( <NUM_LIT> ) . getImm ( ) : <NUM_LIT> ; assert ( RHSReg != <STR_LIT> ) ; BuildMI ( * MI . getParent ( ) , MI , DebugLoc ( ) , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( DstReg ) ; auto & B = BuildMI ( * MI . getParent ( ) , MI , DebugLoc ( ) , TII -> get ( NewOpc ) ) . addReg ( <STR_LIT> , RegState :: Define | getDeadRegState ( DstIsDead ) ) . addReg ( <STR_LIT> , RegState :: Kill ) ; if ( RHSIsReg ) B . addReg (

RHSReg , getKillRegState ( RHSIsKill ) ) ;


<s> return slots - ( ia64_rse_slot_num ( bspstore ) + slots


<s> switch ( MO . getTargetFlags ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <NUM_LIT> : break ; } return Ctx . GetOrCreateSymbol ( Name . str


<s> return getHardwareNumberOfRegisters ( Vec )


<s> InstructionSelector :: ComplexRendererFns <ISA_LIT>InstructionSelector :: selectVOP3Mods0Clamp0OMod ( MachineOperand & Root ) const { Register Src ; unsigned Mods ; std :: tie ( Src , Mods ) = selectVOP3ModsImpl ( Root . getReg ( ) ) ; return { { [ = ] ( MachineInstrBuilder & MIB ) { MIB . addReg ( Src ) ; } , [ = ] ( MachineInstrBuilder & MIB ) { MIB . addImm ( Mods ) ; } , [ = ] ( MachineInstrBuilder & MIB ) { MIB . addImm ( <NUM_LIT> ) ; } , [ = ] ( MachineInstrBuilder & MIB ) { MIB . addImm ( <NUM_LIT> ) ; } }


<s> if ( N . getOpcode ( ) == <STR_LIT> ) { int FI = cast < FrameIndexSDNode > ( N ) -> getIndex ( ) ; Base = CurDAG -> getTargetFrameIndex ( FI , TLI . getPointerTy ( ) ) ; OffImm = CurDAG -> getTargetConstant ( <NUM_LIT> , <STR_LIT> ) ; return true ; } else if ( N . getOpcode ( ) == <STR_LIT> && ! ( Subtarget -> useMovt ( ) && N . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) ) { Base = N . getOperand ( <NUM_LIT> ) ; } else Base = N ; OffImm = CurDAG -> getTargetConstant ( <NUM_LIT> , <STR_LIT> ) ; return true ; } if ( ConstantSDNode * RHS = dyn_cast < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) ) ) { int RHSC = ( int ) RHS -> getZExtValue ( ) ; if ( N . getOpcode ( ) == <STR_LIT> ) RHSC = - RHSC ; if ( RHSC >= <NUM_LIT> && RHSC < <NUM_LIT> ) { Base = N . getOperand ( <NUM_LIT> ) ; if ( Base . getOpcode ( ) == <STR_LIT> ) { int FI = cast < FrameIndexSDNode > ( Base ) -> getIndex ( ) ; Base = CurDAG -> getTargetFrameIndex ( FI , TLI . getPointerTy ( ) ) ; } OffImm = CurDAG -> getTargetConstant ( RHSC , <STR_LIT> ) ; return true ; } } Base =


<s> <ISA_LIT>Operand & FirstOperand = static_cast < <ISA_LIT>Operand & > ( * Operands [ <NUM_LIT> ] ) ; if ( FirstOperand . isToken ( ) && FirstOperand . getToken ( ) == <STR_LIT> ) { assert ( Operands . size ( ) == <NUM_LIT> && <STR_LIT> ) ; if ( InBrackets ) { getParser ( ) . Error ( IDLoc , <STR_LIT> ) ; return true ; } InBrackets = true ; return false ; } if ( FirstOperand . isToken ( ) && FirstOperand . getToken ( ) == <STR_LIT> ) { assert ( Operands . size ( ) == <NUM_LIT> && <STR_LIT> ) ; if ( ! InBrackets ) { getParser ( ) . Error ( IDLoc , <STR_LIT> ) ; return true ; } InBrackets = false ; if ( matchBundleOptions ( ) ) return true ; return finishBundle ( IDLoc ,


<s> selected_arch = aarch64_get_arch ( ptr -> x_explicit_arch ) ; opts -> x_explicit_tune_core = ptr -> x_explicit_tune_core ; if ( opts -> x_explicit_tune_core == aarch64_none && opts -> x_explicit_arch != aarch64_no_arch ) selected_tune = & all_cores [ selected_arch


<s> auto Node = getShaderFunction ( MF . getFunction ( ) . getName ( ) ) ; Node [ <STR_LIT> ] = MsgPackDoc . getNode ( Val


<s> int Src1Idx = <STR_LIT> ( Opc , <STR_LIT> :: src1 ) ; if ( Src1Idx == - <NUM_LIT> ) return false ; int Src0Idx = <STR_LIT> ( Opc , <STR_LIT> :: src0 ) ; MachineOperand * Src0 = getImmOrMaterializedImm ( MRI , MI -> getOperand ( Src0Idx ) ) ; MachineOperand * Src1 = getImmOrMaterializedImm ( MRI , MI -> getOperand ( Src1Idx ) ) ; if ( ! Src0 -> isImm ( ) && ! Src1 -> isImm ( ) ) return false ; if ( MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> ) { if ( Src0 -> isImm ( ) && Src0 -> getImm ( ) == <NUM_LIT> ) { bool UseCopy = TII -> getNamedOperand ( * MI , <STR_LIT> :: src2 ) -> isReg ( ) ; MI -> RemoveOperand ( Src1Idx ) ; MI -> RemoveOperand ( Src0Idx ) ; MI -> setDesc ( TII -> get ( UseCopy ? <STR_LIT> : <STR_LIT> ) ) ; return true ; } } if ( Src0 -> isImm ( ) && Src1 -> isImm ( ) ) { int32_t NewImm ; if ( ! evalBinaryInstruction ( Opc , NewImm , Src0 -> getImm ( ) , Src1 -> getImm ( ) ) ) return false ; const <ISA_LIT>RegisterInfo & TRI = TII -> getRegisterInfo ( ) ; bool IsSGPR = TRI . isSGPRReg ( MRI , MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; MI -> getOperand ( Src0Idx ) . ChangeToImmediate ( NewImm ) ; MI -> RemoveOperand ( Src1Idx ) ; mutateCopyOp ( * MI , TII -> get ( getMovOpc ( IsSGPR ) ) ) ; return true ; } if ( ! MI -> isCommutable ( ) ) return false ; if ( Src0 -> isImm ( ) && ! Src1 -> isImm ( ) ) { std :: swap ( Src0 , Src1


, <NUM_LIT> , PCRelFlagVal } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , PCRelFlagVal } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , PCRelFlagVal } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , PCRelFlagVal } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , PCRelFlagVal } , {


<s> } for ( MCGSites :: const_iterator i ( Sites . begin ( ) ) , ie ( Sites . end ( ) ) ; i != ie ; i ++ ) { delete * i


<s> } OptionalIdx [ Op . getImmTy ( ) ] = i ; } unsigned ClampIdx = OptionalIdx [ AMDGPUOperand :: ImmTyClamp ] ; unsigned OModIdx = OptionalIdx [ AMDGPUOperand :: ImmTyOMod ] ; ( ( AMDGPUOperand & ) * Operands [ ClampIdx ] ) . addImmOperands ( Inst , <NUM_LIT> ) ; ( ( AMDGPUOperand & ) * Operands [ OModIdx ] ) . addImmOperands ( Inst , <NUM_LIT> ) ; } else { for ( unsigned e = Operands . size ( ) ; i != e ; ++ i ) ( ( AMDGPUOperand & ) * Operands [ i ]

) . addRegOrImmOperands ( Inst , <NUM_LIT> ) ;


<s> LowerVASTART ( SDValue Op , SelectionDAG & DAG ) const { SDLoc dl ( Op ) ; MachineFunction & MF = DAG . getMachineFunction ( ) ; <ISA_LIT>FunctionInfo * XFI = MF . getInfo < <ISA_LIT>FunctionInfo >


<s> bool ConcreteRegion < MachineLoop > :: isLoop


<s> return ( uint16x8_t ) ( vabsq_f16 ( __a ) >= vabsq_f16 ( __b ) ) ; return ( uint16x8_t ) __builtin_neon_vcagev8hf ( __a ,


<s> inline unsigned GetDefaultP2Align ( unsigned Opcode ) { switch ( Opcode ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> if ( ( R == Match_Success ) || ( R == Match_PreferE32 ) || ( R == Match_MissingFeature && Result != Match_PreferE32 ) || ( R == Match_InvalidOperand && Result != Match_MissingFeature && Result != Match_PreferE32 ) || ( R == Match_MnemonicFail && Result != Match_InvalidOperand && Result != Match_MissingFeature && Result != Match_PreferE32 ) ) { Result = R ; ErrorInfo = EI ; } if ( R == Match_Success ) break ; } switch ( Result ) { default : break ; case Match_Success : if ( ! validateInstruction ( Inst , IDLoc ) ) { return true ; } Inst . setLoc ( IDLoc ) ; Out . EmitInstruction ( Inst , getSTI ( ) ) ; return false ; case Match_MissingFeature : return Error ( IDLoc , <STR_LIT> ) ; case Match_MnemonicFail : { FeatureBitset FBS = ComputeAvailableFeatures ( getSTI ( ) . getFeatureBits ( ) ) ; std :: string Suggestion = <ISA_LIT>MnemonicSpellCheck ( ( ( <ISA_LIT>Operand & ) * Operands [ <NUM_LIT> ] ) . getToken ( ) , FBS ) ; return Error ( IDLoc , <STR_LIT> + Suggestion , ( ( <ISA_LIT>Operand & ) * Operands [ <NUM_LIT> ] ) . getLocRange ( ) ) ; } case Match_InvalidOperand


<s> static MCSubtargetInfo * createAMDGPUMCSubtargetInfo ( StringRef TT , StringRef CPU , StringRef FS ) { MCSubtargetInfo * X = new MCSubtargetInfo ( ) ; InitAMDGPUMCSubtargetInfo ( X , TT


<s> bool <ISA_LIT>BasicMCBuilder :: RunBuildAfterHook ( bool Status , MCInst & MI , uint32_t insn ) { if ( ! SP ) return Status ; if ( Opcode == <STR_LIT> ) Status = SP -> InitIT ( slice ( insn , <NUM_LIT> , <NUM_LIT> ) )


<s> void <ISA_LIT>InstPrinter :: printPostIncOperand4 ( const MCInst * MI , unsigned OpNo , raw_ostream & O ) { printPostIncOperand ( MI , OpNo , <NUM_LIT> , O


<s> return llvm :: make_unique < <ISA_LIT>ELFObjectWriter > ( OSABI


<s> static Register getSPReg ( const <ISA_LIT>Subtarget & STI ) { return


<s> return ( __m128 ) __builtin_ia32_cmpltps ( ( __v4sf )


<s> MachineBasicBlock * Succ = * OrigBB -> succ_begin ( ) ; OrigBB -> removeSuccessor ( Succ ) ; NewBB -> addSuccessor ( Succ ) ; assert ( ( Succ -> empty ( ) || ! Succ -> begin ( ) -> isPHI ( ) ) && <STR_LIT> ) ; } OrigBB -> addSuccessor ( NewBB ) ; MF . RenumberBlocks ( NewBB ) ; BBSizes . insert ( BBSizes . begin ( ) + NewBB -> getNumber ( ) , <NUM_LIT> ) ; BBOffsets . insert ( BBOffsets . begin ( ) + NewBB -> getNumber ( ) , <NUM_LIT> ) ; water_iterator IP = std :: lower_bound ( WaterList . begin ( ) , WaterList . end ( ) , OrigBB , CompareMBBNumbers ) ; MachineBasicBlock * WaterBB = * IP ; if ( WaterBB == OrigBB ) WaterList . insert ( llvm :: next ( IP ) , NewBB ) ; else WaterList . insert ( IP , OrigBB ) ; NewWaterList . insert ( OrigBB ) ; unsigned NewBBSize = <NUM_LIT> ; for ( MachineBasicBlock :: iterator I = NewBB -> begin ( ) , E = NewBB -> end ( ) ; I != E ; ++ I ) NewBBSize += TII -> GetInstSizeInBytes ( I ) ; unsigned OrigBBI = OrigBB -> getNumber


<s> RegisterTargetMachine < <ISA_LIT>ebTargetMachine > A ( getThe<ISA_LIT>64Target ( ) ) ; RegisterTargetMachine < <ISA_LIT>elTargetMachine > B


<s> switch ( ErrCode ) { case Match_MissingFeature : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidOperand : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidSuffix : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryIndexedSImm9 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryIndexed32SImm7 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryIndexed64SImm7 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryIndexed128SImm7 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryIndexed8 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryIndexed16 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryIndexed32 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryIndexed64 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryIndexed128 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidImm0_7 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidImm0_15 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidImm0_31 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidImm0_63 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidImm1_8 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidImm1_16 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidImm1_32 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidImm1_64 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidIndexB : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidIndexH : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidIndexS : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidIndexD : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidLabel : return Error ( Loc


<s> if ( Tok . isNot ( AsmToken :: Identifier ) ) return true ; auto Keyword = Tok . getString ( ) ; Keyword = StringSwitch < StringRef > ( Keyword . lower ( ) ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( Keyword ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateToken ( Keyword , Tok . getLoc ( ) , getContext ( ) ) ) ; Lex ( )


<s> else if ( AsmParser -> isGFX9Plus ( ) ) return isRegClass

( <STR_LIT> ) || isInlinableImm ( type ) ;


<s> } else gcc_unreachable ( ) ; } } else { if ( mode == TImode ) split_double_mode ( mode , & operand , <NUM_LIT> , & parts [ <NUM_LIT> ] , & parts [ <NUM_LIT> ] ) ; if ( mode == XFmode || mode == TFmode ) { machine_mode upper_mode = mode == XFmode ? SImode : DImode ; if ( REG_P ( operand ) ) { gcc_assert ( reload_completed ) ; parts [ <NUM_LIT> ] = gen_rtx_REG ( DImode , REGNO ( operand ) + <NUM_LIT> ) ; parts [ <NUM_LIT> ] = gen_rtx_REG ( upper_mode , REGNO ( operand ) + <NUM_LIT> ) ; } else if ( offsettable_memref_p ( operand ) ) { operand = adjust_address ( operand , DImode , <NUM_LIT> ) ; parts [ <NUM_LIT> ] = operand ; parts [ <NUM_LIT> ] = adjust_address ( operand , upper_mode , <NUM_LIT> ) ; } else if ( GET_CODE ( operand ) == CONST_DOUBLE ) { REAL_VALUE_TYPE r ; long l [ <NUM_LIT> ] ; REAL_VALUE_FROM_CONST_DOUBLE ( r , operand ) ; real_to_target ( l , & r , mode ) ; if ( HOST_BITS_PER_WIDE_INT >= <NUM_LIT> ) parts [ <NUM_LIT> ] = gen_int_mode ( ( l [ <NUM_LIT> ] & ( ( ( HOST_WIDE_INT ) <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) ) + ( ( ( ( HOST_WIDE_INT ) l [ <NUM_LIT> ] ) << <NUM_LIT> ) << <NUM_LIT> ) , DImode ) ; else parts [ <NUM_LIT> ] = immed_double_const ( l [ <NUM_LIT> ] , l [ <NUM_LIT> ] , DImode ) ; if ( upper_mode == SImode ) parts [ <NUM_LIT> ] = gen_int_mode ( l [ <NUM_LIT> ] , SImode ) ; else if ( HOST_BITS_PER_WIDE_INT >= <NUM_LIT> ) parts [ <NUM_LIT> ] = gen_int_mode ( ( l [ <NUM_LIT> ] & ( ( ( HOST_WIDE_INT ) <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) ) + ( ( ( ( HOST_WIDE_INT ) l [ <NUM_LIT> ] ) << <NUM_LIT> ) << <NUM_LIT> ) , DImode ) ; else parts [ <NUM_LIT> ] = immed_double_const ( l [ <NUM_LIT> ] , l [ <NUM_LIT> ]


<s> if ( RegNo > <NUM_LIT> ) return MCDisassembler :: Fail ; unsigned Register = GPRDecoderTable [ RegNo + <NUM_LIT> ] ; Inst . addOperand ( MCOperand :: createReg ( Register ) ) ; return MCDisassembler :: Success


<s> int arm_address_offset_is_imm ( rtx_insn * insn ) { rtx mem , addr ; extract_insn_cached ( insn ) ; if ( REG_P ( recog_data . operand [ <NUM_LIT> ] ) ) return <NUM_LIT> ; mem = recog_data . operand


<s> unsigned getSRetReturnReg ( ) const { return SRetReturnReg


<s> std :: vector < std :: string > mpyi (


<s> if ( ! Subtarget . hasTBM ( ) && ! ( Subtarget . hasBMI ( ) && Subtarget . hasFastBEXTR ( ) ) ) return true ; if ( ! isShiftedMask_64 ( Mask ) ) return true ; unsigned ShiftAmt = Shift . getConstantOperandVal ( <NUM_LIT> ) ; unsigned AMShiftAmt = countTrailingZeros ( Mask ) ; if ( AMShiftAmt <= <NUM_LIT> || AMShiftAmt > <NUM_LIT> ) return true ; MVT VT = N . getSimpleValueType ( ) ; SDLoc DL ( N ) ; SDValue NewSRLAmt = DAG . getConstant ( ShiftAmt + AMShiftAmt , DL , <STR_LIT> ) ; SDValue NewSRL = DAG . getNode ( <STR_LIT> , DL , VT , X , NewSRLAmt ) ; SDValue NewMask = DAG . getConstant ( Mask >> AMShiftAmt , DL , VT ) ; SDValue NewAnd = DAG . getNode ( <STR_LIT> , DL , VT , NewSRL , NewMask ) ; SDValue NewSHLAmt = DAG . getConstant ( AMShiftAmt , DL , <STR_LIT> ) ; SDValue NewSHL = DAG . getNode ( <STR_LIT> , DL , VT , NewAnd , NewSHLAmt ) ; insertDAGNode ( DAG , N , NewSRLAmt ) ; insertDAGNode ( DAG , N , NewSRL ) ; insertDAGNode ( DAG , N , NewMask ) ; insertDAGNode ( DAG , N , NewAnd ) ; insertDAGNode ( DAG , N , NewSHLAmt ) ; insertDAGNode ( DAG , N , NewSHL ) ; DAG . ReplaceAllUsesWith ( N , NewSHL ) ; AM . Scale = <NUM_LIT> << AMShiftAmt ; AM . IndexReg = NewAnd ; return false


<s> const auto & CSI = MFI . getCalleeSavedInfo ( ) ; int MinCSFI = <NUM_LIT> ; int MaxCSFI = - <NUM_LIT> ; int Offset = MFI . getObjectOffset ( FI ) + MFI . getOffsetAdjustment ( ) ; if ( CSI . size ( ) ) { MinCSFI = CSI [ <NUM_LIT> ] . getFrameIdx ( ) ; MaxCSFI = CSI [ CSI . size ( ) - <NUM_LIT> ] . getFrameIdx ( ) ; } if ( FI >= MinCSFI && FI <= MaxCSFI ) { FrameReg = <STR_LIT> ; Offset += CFI -> getVarArgsSaveSize ( ) + CFI -> getCalleeSaveAreaSize ( ) ; } else if ( RI -> hasStackRealignment ( MF ) ) { assert ( hasFP ( MF ) ) ; if ( ! MFI . isFixedObjectIndex ( FI ) ) { FrameReg = hasBP ( MF ) ? getBPReg


<s> if ( SGPRPressureSets . test ( Idx ) && VGPRPressureSets . test ( Idx ) ) { return VSLimit ; } if ( SGPRPressureSets . test ( Idx ) ) return SGPRLimit ; return VGPRLimit


<s> void <ISA_LIT>TargetWinCOFFStreamer ::


<s> for ( first_reg = <NUM_LIT> + <NUM_LIT> ; first_reg <= <NUM_LIT> ; first_reg ++ ) if (


<s> if ( EffBits <= <NUM_LIT> ) ExtendOp = <STR_LIT> ; } } CmpVT = <STR_LIT> ; Op0 = DAG . getNode ( ExtendOp , dl , CmpVT , Op0 ) ; Op1 = DAG . getNode ( ExtendOp , dl , CmpVT , Op1 ) ; } } if ( CmpVT == <STR_LIT> && isa < ConstantSDNode > ( Op1 ) && ! is<ISA_LIT>CCSigned ( <ISA_LIT>CC ) && Op0 . hasOneUse ( ) && cast < ConstantSDNode > ( Op1 ) -> getAPIntValue ( ) . getActiveBits ( ) <= <NUM_LIT> && DAG . MaskedValueIsZero ( Op0 , APInt :: getHighBitsSet ( <NUM_LIT> , <NUM_LIT> ) ) ) { CmpVT = <STR_LIT> ; Op0 = DAG . getNode ( <STR_LIT> , dl , CmpVT , Op0 ) ; Op1 = DAG . getNode ( <STR_LIT> , dl , CmpVT , Op1 ) ; } SDVTList VTs = DAG . getVTList ( CmpVT , <STR_LIT> ) ; SDValue Sub = DAG . getNode ( <STR_LIT> , dl , VTs


<s> if ( unsigned Reg = State . AllocateReg ( <STR_LIT> ) ) { State . addLoc ( CCValAssign :: getReg ( ValNo , ValVT , Reg , LocVT , LocInfo ) ) ; return false ; } static const MCPhysReg RegList1 [ ] = { <STR_LIT> , <STR_LIT> } ; static const MCPhysReg RegList2 [ ] = { <STR_LIT> , <STR_LIT> } ; if ( unsigned Reg = State . AllocateReg ( RegList1 , RegList2 ) ) { State . addLoc ( CCValAssign :: getReg ( ValNo , ValVT , Reg , LocVT , LocInfo ) ) ; return false ; } unsigned Offset = State . AllocateStack ( <NUM_LIT> , <NUM_LIT> , <STR_LIT> ) ; State . addLoc ( CCValAssign :: getMem ( ValNo , ValVT , Offset , LocVT , LocInfo ) ) ; return


<s> const REAL_VALUE_TYPE * rv ; long val ; rv = CONST_DOUBLE_REAL_VALUE ( op ) ; REAL_VALUE_TO_TARGET_SINGLE ( * rv ,


<s> void <ISA_LIT>InstrInfo :: storeRegToStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned SrcReg , bool IsKill , int

FI , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const {


<s> const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( Mem . OffsetImm ) ; assert ( CE && <STR_LIT> ) ; int64_t Value = CE -> getValue


<s> LLT S1 = LLT :: scalar ( <NUM_LIT> ) ; MachineInstr * Compare = nullptr ; Register Flag ; MachineIRBuilder Builder ( MI ) ; MachineInstr * Load ; Register LHS ; if ( ! Compare && mi_match ( CondReg , MRI , m_CMPTermZ ( LHS , Flag ) ) ) Compare = Builder . buildInstr ( <STR_LIT> , { S1 } , { LHS } ) ; int64_t RHSConst ; if ( ! Compare && mi_match ( CondReg , MRI , m_CMPTermImm ( LHS , RHSConst , Flag ) ) ) Compare = Builder . buildInstr ( <STR_LIT> , { S1 } , { LHS , RHSConst } ) ; MachineOperand Addr = MachineOperand :: CreateReg ( <STR_LIT> , false ) ; if ( ! Compare && mi_match ( CondReg , MRI , m_CMPTermAbs ( LHS , Addr , Flag , Load , AA ) ) ) Compare = Builder . buildInstr ( <STR_LIT> , { S1 } , { LHS } ) . add ( Addr ) . cloneMemRefs ( * Load ) ; Register Idx ; if ( ! Compare && mi_match ( CondReg , MRI , m_CMPTermIdx ( LHS , Addr , Idx , Flag , Load , AA ) ) ) { Compare = Builder . buildInstr ( <STR_LIT> , { S1 } , { LHS } ) . add ( Addr ) . addUse ( Idx ) . cloneMemRefs ( * Load ) ; } Register RegAddr ; if ( ! Compare && mi_match ( CondReg , MRI , m_CMPTermIndir ( LHS , RegAddr , Idx , Flag , Load , AA ) ) ) { Compare = Builder . buildInstr ( <STR_LIT> , { S1 } , { LHS , RegAddr , Idx } ) . cloneMemRefs ( * Load ) ; } Register RHS ; if ( ! Compare && mi_match ( CondReg , MRI , m_CMPTermImag8 ( LHS , RHS , Flag ) ) ) Compare = Builder . buildInstr ( <STR_LIT> , { S1 } , { LHS , RHS } ) ; if ( Compare ) { if ( ! constrainSelectedInstRegOperands ( * Compare , TII , TRI , RBI ) ) return false ; assert ( Flag !=


<s> int <ISA_LIT>CFGStructurizer :: getContinueZeroOpcode ( int OldOpcode ) { switch ( OldOpcode ) { case <STR_LIT> : case <STR_LIT> : return <STR_LIT>


<s> <ISA_LIT>MCExpr :: VariantKind Variant ; if ( isNonConstantExpr ( ImmWithLSL . Val , Variant ) ) { return Variant == <ISA_LIT>MCExpr :: VK_AARCH64_LO12 || Variant == <ISA_LIT>MCExpr :: VK_AARCH64_DTPREL_LO12 || Variant == <ISA_LIT>MCExpr :: VK_AARCH64_DTPREL_LO12_NC || Variant == <ISA_LIT>MCExpr :: VK_AARCH64_TPREL_LO12 || Variant == <ISA_LIT>MCExpr :: VK_AARCH64_TPREL_LO12_NC

|| Variant == <ISA_LIT>MCExpr :: VK_AARCH64_TLSDESC_LO12 ;


<s> void Filler :: insertDefsUses ( MachineBasicBlock :: iterator MI , SmallSet < unsigned , <NUM_LIT> > & RegDefs , SmallSet < unsigned , <NUM_LIT> > & RegUses ) { for ( unsigned i = <NUM_LIT> , e = MI ->


<s> static MCDisassembler * create<ISA_LIT>Disassembler ( const Target & T , const MCSubtargetInfo & STI ,


<s> return ( float32x2_t ) __builtin_neon_vmul_lanev2sf (


<s> assert ( getTargetMachine ( ) . getCodeModel ( ) == CodeModel :: Small ) ; EVT PtrVT = getPointerTy ( ) ; DebugLoc dl = Op . getDebugLoc ( ) ; const GlobalAddressSDNode * GN = cast < GlobalAddressSDNode > ( Op ) ; const GlobalValue * GV = GN -> getGlobal ( ) ; unsigned Alignment = GV -> getAlignment ( ) ; Reloc :: Model RelocM = getTargetMachine ( ) . getRelocationModel ( ) ; if ( GV -> isWeakForLinker ( ) && GV -> isDeclaration ( ) && RelocM == Reloc :: Static ) { SDValue PoolAddr ; PoolAddr = DAG . getNode ( <STR_LIT> , dl , PtrVT , DAG . getTargetConstantPool ( GV , PtrVT , <NUM_LIT> , <NUM_LIT> , <STR_LIT> ) , DAG . getTargetConstantPool ( GV , PtrVT , <NUM_LIT> , <NUM_LIT> , <STR_LIT> ) , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDValue GlobalAddr = DAG . getLoad ( PtrVT , dl , DAG . getEntryNode ( ) , PoolAddr , MachinePointerInfo :: getConstantPool ( ) , false , true , true , <NUM_LIT> ) ; if ( GN -> getOffset ( ) != <NUM_LIT> ) return DAG . getNode ( <STR_LIT> , dl , PtrVT , GlobalAddr , DAG . getConstant ( GN -> getOffset ( ) , PtrVT ) ) ; return GlobalAddr ; } if ( Alignment == <NUM_LIT> ) { const PointerType * GVPtrTy = cast < PointerType > ( GV -> getType ( ) ) ; if ( GVPtrTy -> getElementType ( ) -> isSized ( ) ) { Alignment = getDataLayout ( ) -> getABITypeAlignment ( GVPtrTy -> getElementType ( ) ) ; } else { Alignment = <NUM_LIT> ; } } unsigned char HiFixup , LoFixup ; bool UseGOT = Subtarget -> GVIsIndirectSymbol ( GV , RelocM ) ; if ( UseGOT ) { HiFixup = <STR_LIT> ; LoFixup = <STR_LIT> ; Alignment = <NUM_LIT> ; } else { HiFixup = <STR_LIT> ; LoFixup = <STR_LIT> ; } SDValue GlobalRef = DAG . getNode ( <STR_LIT> , dl , PtrVT , DAG . getTargetGlobalAddress ( GV , dl , PtrVT , <NUM_LIT> , HiFixup ) , DAG . getTargetGlobalAddress ( GV , dl , PtrVT , <NUM_LIT> , LoFixup ) , DAG . getConstant ( Alignment , <STR_LIT> ) ) ; if ( UseGOT ) { GlobalRef = DAG . getNode ( <STR_LIT> , dl , PtrVT , DAG . getEntryNode ( ) , GlobalRef ) ; } if ( GN -> getOffset ( ) != <NUM_LIT> ) return DAG . getNode ( <STR_LIT> , dl , PtrVT

, GlobalRef , DAG . getConstant ( GN -> getOffset ( ) , PtrVT ) ) ;


<s> if ( MI . getOperand ( <NUM_LIT> ) . isReg ( ) && <STR_LIT> ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ) REX |= <NUM_LIT> << <NUM_LIT> ; i = isTwoAddr ? <NUM_LIT> : <NUM_LIT> ; for ( ; i != NumOps ; ++ i ) { const MCOperand & MO = MI . getOperand ( i ) ; if ( MO . isReg ( ) && <STR_LIT> ( MO . getReg ( ) ) ) REX |= <NUM_LIT> << <NUM_LIT> ; } break ; case <STR_LIT> : { if ( MI . getOperand ( <NUM_LIT> ) . isReg ( ) && <STR_LIT> ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ) REX |= <NUM_LIT> << <NUM_LIT> ; unsigned Bit = <NUM_LIT> ; i = isTwoAddr ? <NUM_LIT> : <NUM_LIT> ; for ( ; i != NumOps ; ++ i ) { const MCOperand & MO = MI . getOperand ( i ) ; if ( MO . isReg ( ) ) { if ( <STR_LIT> ( MO . getReg ( ) ) ) REX |= <NUM_LIT> << Bit ; Bit ++ ; } } break ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { unsigned e = ( isTwoAddr ? <STR_LIT> + <NUM_LIT> : <STR_LIT> ) ; i = isTwoAddr ? <NUM_LIT> : <NUM_LIT> ; if ( NumOps > e && MI . getOperand ( e ) . isReg ( ) && <STR_LIT> ( MI . getOperand ( e ) . getReg ( ) ) ) REX |= <NUM_LIT> << <NUM_LIT> ; unsigned Bit = <NUM_LIT> ; for ( ; i != e ; ++ i ) { const MCOperand & MO = MI .


<s> auto PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; SDValue Result = DAG . getTargetJumpTable ( JT -> getIndex ( ) , PtrVT , OpFlag ) ; SDLoc DL ( JT ) ; Result = DAG . getNode ( WrapperKind , DL , PtrVT , Result ) ; if ( <STR_LIT> (


<s> SDValue Vec = Op . getOperand ( <NUM_LIT> ) ; SDValue Elt = Op . getOperand ( <NUM_LIT> ) ; SDValue Idx = Op . getOperand ( <NUM_LIT> ) ; MVT VecVT = Vec . getSimpleValueType ( ) ; if ( ! isa < ConstantSDNode > ( Idx ) ) { MVT ExtVecVT = ( VecVT == <STR_LIT> ? <STR_LIT> : <STR_LIT> ) ; MVT ExtEltVT = ( VecVT == <STR_LIT> ? <STR_LIT> : <STR_LIT> ) ; SDValue ExtOp = DAG . getNode ( <STR_LIT> , dl , ExtVecVT , DAG . getNode ( <STR_LIT> , dl , ExtVecVT , Vec ) , DAG . getNode ( <STR_LIT> , dl , ExtEltVT , Elt ) , Idx ) ; return DAG . getNode ( <STR_LIT> , dl , VecVT , ExtOp ) ; } unsigned IdxVal = cast < ConstantSDNode > ( Idx ) -> getZExtValue ( ) ; SDValue EltInVec = DAG . getNode ( <STR_LIT> , dl , VecVT , Elt ) ; unsigned NumElems = VecVT . getVectorNumElements ( ) ; if ( Vec . isUndef ( ) ) { if ( IdxVal ) EltInVec = DAG . getNode ( <STR_LIT> , dl , VecVT , EltInVec , DAG . getConstant ( IdxVal , dl , <STR_LIT> ) ) ; return EltInVec ; } if ( IdxVal == <NUM_LIT> ) { Vec = DAG . getNode ( <STR_LIT> , dl , VecVT , Vec , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; Vec = DAG . getNode ( <STR_LIT> , dl , VecVT , Vec , DAG . getConstant


<s> void <ISA_LIT>InstrInfo :: storeRegToStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned SrcReg , bool isKill , int FI , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { const <ISA_LIT>TargetLowering * PTLI = TM . getTargetLowering ( ) ; DebugLoc DL ; if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; const Function * Func = MBB . getParent ( ) -> getFunction ( ) ; const std :: string FuncName = Func -> getName ( ) ; const char * tmpName = ESNames :: createESName ( PAN :: getTempdataLabel ( FuncName ) ) ; if ( RC == <STR_LIT> ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addImm ( PTLI -> GetTmpOffsetForFI ( FI , <NUM_LIT> , * MBB . getParent ( ) ) ) . addExternalSymbol ( tmpName ) . addImm ( <NUM_LIT> ) ; } else if ( RC == <STR_LIT> ) { unsigned opcode = ( SrcReg == <STR_LIT> )


<s> } } const ConstantExpr * CE = dyn_cast < ConstantExpr > ( CV ) ; if ( ! CE ) { llvm_unreachable ( <STR_LIT> ) ; } switch ( CE -> getOpcode ( ) ) { default : if ( Constant * C = ConstantFoldConstant ( CE , getDataLayout ( ) ) ) if ( C && C != CE ) return lowerConstantForGV ( C , ProcessingGeneric ) ; { std :: string S ; raw_string_ostream OS ( S ) ; OS << <STR_LIT> ; CE -> printAsOperand ( OS , false , ! MF ? nullptr : MF -> getFunction ( ) . getParent ( ) ) ; report_fatal_error ( OS . str ( ) ) ; } case Instruction :: AddrSpaceCast : { PointerType * DstTy = cast < PointerType > ( CE -> getType ( ) ) ; if ( DstTy -> getAddressSpace ( ) == <NUM_LIT> ) { return lowerConstantForGV ( cast < const Constant > ( CE -> getOperand ( <NUM_LIT> ) ) , true ) ; } std :: string S ; raw_string_ostream OS ( S ) ; OS << <STR_LIT> ; CE -> printAsOperand ( OS , false , ! MF ? nullptr : MF -> getFunction ( ) . getParent ( ) ) ; report_fatal_error ( OS . str ( ) ) ; } case Instruction :: GetElementPtr : { const DataLayout & DL = getDataLayout ( ) ; APInt OffsetAI ( DL . getPointerTypeSizeInBits ( CE -> getType ( ) ) , <NUM_LIT> ) ; cast < GEPOperator > ( CE ) -> accumulateConstantOffset ( DL , OffsetAI ) ; const MCExpr * Base = lowerConstantForGV ( CE -> getOperand ( <NUM_LIT> ) , ProcessingGeneric ) ; if ( ! OffsetAI ) return Base ; int64_t Offset = OffsetAI . getSExtValue ( ) ; return MCBinaryExpr :: createAdd ( Base , MCConstantExpr :: create ( Offset , Ctx ) , Ctx ) ; } case Instruction :: Trunc : LLVM_FALLTHROUGH ; case Instruction :: BitCast : return lowerConstantForGV ( CE -> getOperand ( <NUM_LIT> ) , ProcessingGeneric ) ; case Instruction :: IntToPtr : { const DataLayout & DL = getDataLayout (


<s> } } if ( Writer -> doesSymbolRequireExternRelocation ( * A ) ) { RelSymbol = A ; if ( ! A -> isUndefined ( ) ) FixedValue -= Layout . getSymbolOffset ( * A ) ; } else { const MCSection & Sec = A -> getSection ( ) ; Index = Sec . getOrdinal ( ) + <NUM_LIT> ; FixedValue += Writer -> getSectionAddress ( & Sec ) ; } if ( IsPCRel ) FixedValue -= Writer -> getSectionAddress ( Fragment -> getParent ( ) ) ; } MachO :: any_relocation_info MRE ; makeRelocationInfo ( MRE , FixupOffset , Index ,


<s> break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_ABS_HI : FixupKind = <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_ABS_LO : FixupKind = <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_TLSGD : FixupKind = <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_TLSLDM : FixupKind = <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_DTPREL_HI : FixupKind = <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_DTPREL_LO : FixupKind = <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOTTPREL : FixupKind = <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_TPREL_HI : FixupKind = <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_TPREL_LO : FixupKind = <STR_LIT> ; break ; default : break ; } Fixups . push_back ( MCFixup :: Create ( <NUM_LIT> , MO . getExpr ( ) , MCFixupKind ( FixupKind ) ) ) ; return <NUM_LIT>


<s> assert ( ImpDefSCC . getReg ( ) == <STR_LIT> && ImpDefSCC . isDef ( ) ) ; unsigned CopyReg = MRI -> createVirtualRegister ( & <STR_LIT> ) ; MachineInstr * CopyExec = BuildMI ( MBB , I , DL , TII -> get ( <STR_LIT> ) , CopyReg ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> , RegState :: ImplicitDefine ) ; unsigned Tmp = MRI -> createVirtualRegister ( & <STR_LIT> ) ; MachineInstr * And = BuildMI ( MBB , I , DL , TII -> get ( <STR_LIT> ) , Tmp ) . addReg ( CopyReg ) . addReg ( Cond . getReg ( ) ) ; setImpSCCDefDead ( * And , true ) ; MachineInstr * Xor = BuildMI ( MBB , I , DL , TII -> get ( <STR_LIT> ) , SaveExecReg ) . addReg ( Tmp ) . addReg ( CopyReg ) ; setImpSCCDefDead ( * Xor , ImpDefSCC . isDead ( ) ) ; MachineInstr * SetExec = BuildMI ( MBB , I , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( Tmp , RegState :: Kill ) ; MachineInstr * NewBr = BuildMI ( MBB , I , DL , TII -> get ( <STR_LIT> ) ) . addOperand ( MI . getOperand ( <NUM_LIT> ) ) ; if ( ! LIS


<s> __arm_vldrhq_gather_offset ( float16_t const *


<s> bool AMDGPUDAGToDAGISel :: isCPLoad ( const LoadSDNode * N ) const { MachineMemOperand * MMO = N -> getMemOperand ( ) ; if ( checkType ( N -> getSrcValue ( ) ,


<s> if ( LiveRegs . empty ( ) ) { if ( IsProlog ) { LiveRegs . init ( TRI ) ; LiveRegs . addLiveIns ( MBB ) ; if ( FuncInfo -> SGPRForFPSaveRestoreCopy ) LiveRegs . removeReg ( FuncInfo -> SGPRForFPSaveRestoreCopy ) ; if ( FuncInfo -> SGPRForBPSaveRestoreCopy ) LiveRegs . removeReg ( FuncInfo -> SGPRForBPSaveRestoreCopy ) ; } else { LiveRegs . init ( * ST . getRegisterInfo ( ) ) ; LiveRegs . addLiveOuts (


<s> if ( auto E = Obj . takeError ( ) ) return std :: move ( E ) ; std :: unique_ptr < HSACodeObject > Ret ( new HSACodeObject ( std :: move ( * Obj


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , Optional < CodeModel :: Model > CM , CodeGenOpt :: Level OL , bool JIT , bool LittleEndian ) : LLVMTargetMachine ( T , computeDataLayout ( TT , Options . MCOptions , LittleEndian ) , TT , CPU , FS , Options , getEffectiveRelocModel ( TT , RM ) , getEffectiveCodeModel ( TT , CM , JIT ) , OL ) , TLOF ( createTLOF ( getTargetTriple ( ) ) ) , isLittle ( LittleEndian ) { initAsmInfo ( ) ; if ( TT . isOSBinFormatMachO


<s> if ( GET_CODE ( op ) != MEM ) return false ; if ( mode == VOIDmode ) mode = GET_MODE ( op ) ; size = GET_MODE_SIZE ( mode ) ; if ( size > UNITS_PER_WORD ) return false ; addr = XEXP ( op , <NUM_LIT> ) ; if ( ! legitimate_small_data_address_p ( addr ) ) return false ; if ( ! short_p || size == <NUM_LIT> ) return true ; align = get_symbol_alignment ( addr ) ; switch ( mode ) { case E_HImode : mask = <NUM_LIT> ; break ; default : mask = <NUM_LIT>


<s> void <ISA_LIT>AsmPrinter :: emit_prolog ( const MachineInstr * MI ) { SmallString < <NUM_LIT> > prologueString ; raw_svector_ostream OS ( prologueString ) ; bool smallStack = <ISA_LIT>InstrInfo :: check_sconst_fits ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) , <NUM_LIT> ) ; OS << <STR_LIT> ; if ( smallStack ) { OS << <STR_LIT> ; printOperand ( MI , <NUM_LIT> , OS ) ; OS << <STR_LIT> ; } else { OS << <STR_LIT> ; printOperand ( MI , <NUM_LIT> , OS ) ; OS << <STR_LIT> ; } OS << <STR_LIT> ; if ( ! smallStack ) { OS << <STR_LIT> ; printOperand ( MI , <NUM_LIT> , OS ) ; OS << <STR_LIT> ; } OS << <STR_LIT> ; OS << <STR_LIT> ; OS << <STR_LIT> ; OS <<


<s> unsigned Idx = ( FullSize - <NUM_LIT> - i ) ; CurVal |= static_cast < uint64_t > ( static_cast < uint8_t > ( Data [ Offset + Idx ] ) ) << ( i * <NUM_LIT> ) ; } uint64_t Mask = ( static_cast < uint64_t > ( - <NUM_LIT> ) >> ( <NUM_LIT> - getFixupKindInfo ( Kind ) . TargetSize ) ) ; CurVal |= Value & Mask ; for ( unsigned i = <NUM_LIT> ; i !=


<s> AU . addRequired < <ISA_LIT>CallGraphBuilder > ( ) ; AU . addRequired < <ISA_LIT>StackCacheAnalysisInfo > ( ) ; PMLModuleExportPass :: getAnalysisUsage (


<s> if ( Constraint . size ( ) == <NUM_LIT> ) { switch ( Constraint [ <NUM_LIT> ] ) { default : break ; case 'r' : if ( VT == <STR_LIT> ) return std :: make_pair ( <NUM_LIT> , <STR_LIT> ) ; else if ( VT == <STR_LIT> ) return std


<s> __builtin_ia32_gatherpfqpd ( mask , ( __v8di ) index , ( long long const * ) addr


<s> unsigned NumElems = Input . getValueType ( ) . getVectorNumElements ( ) ; SmallVector < int , <NUM_LIT> > ShuffleMask ( NumElems , - <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i < N -> getNumOperands ( ) ; i ++ ) { if ( DAG . getDataLayout ( ) . isLittleEndian ( ) ) ShuffleMask [ CorrectElems & <NUM_LIT> ] = Elems & <NUM_LIT> ; else ShuffleMask [ ( CorrectElems & <NUM_LIT> ) >> <NUM_LIT> ] = ( Elems & <NUM_LIT> ) >> <NUM_LIT> ; CorrectElems = CorrectElems >> <NUM_LIT> ; Elems = Elems >> <NUM_LIT> ; } SDValue Shuffle = DAG . getVectorShuffle ( Input . getValueType ( ) , dl , Input , DAG . getUNDEF ( Input . getValueType ( ) ) , ShuffleMask ) ; EVT Ty = N -> getValueType ( <NUM_LIT> ) ; SDValue BV = DAG . getNode ( <STR_LIT> , dl , Ty , Shuffle ) ; return BV


<s> assert ( N . getOpcode ( ) == <STR_LIT> && <STR_LIT> ) ; SDLoc DL ( N ) ; SmallVector < SDValue , <NUM_LIT> > Chain ; SDValue V = N . getOperand ( <NUM_LIT> ) ; for ( ; V . hasOneUse ( ) ; V = V . getOperand ( <NUM_LIT> ) ) { switch ( V . getOpcode ( ) ) { default : return SDValue ( ) ; case <STR_LIT> : continue ; case <STR_LIT> : break ; case <STR_LIT> : if ( Mask [ <NUM_LIT> ] != <NUM_LIT> || Mask [ <NUM_LIT> ] != <NUM_LIT> || ! ( Mask [ <NUM_LIT> ] >= <NUM_LIT> && Mask [ <NUM_LIT> ] < <NUM_LIT> && Mask [ <NUM_LIT> ] >= <NUM_LIT> && Mask [ <NUM_LIT> ] < <NUM_LIT> ) ) return SDValue ( ) ; Chain . push_back ( V ) ; continue ; case <STR_LIT> : if ( Mask [ <NUM_LIT> ] != <NUM_LIT> || Mask [ <NUM_LIT> ] != <NUM_LIT> || ! ( Mask [ <NUM_LIT> ] >= <NUM_LIT> && Mask [ <NUM_LIT> ] < <NUM_LIT> && Mask [ <NUM_LIT> ] >= <NUM_LIT> && Mask [ <NUM_LIT> ] < <NUM_LIT> ) ) return SDValue ( ) ; Chain . push_back ( V ) ; continue ; case <STR_LIT> : case <STR_LIT> : if ( V . getSimpleValueType ( ) . getScalarType ( ) != <STR_LIT> && V . getSimpleValueType ( ) . getScalarType ( ) != <STR_LIT> ) return SDValue ( ) ; unsigned CombineOp = V . getOpcode ( ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; if ( V . getOperand ( <NUM_LIT> ) != V . getOperand ( <NUM_LIT> ) || ! V -> isOnlyUserOf ( V . getOperand ( <NUM_LIT> ) . getNode ( ) ) ) return SDValue ( ) ; Chain . push_back ( V ) ; V = V . getOperand ( <NUM_LIT> ) ; do { switch ( V . getOpcode ( ) ) { default : return SDValue ( ) ; case <STR_LIT> : case <STR_LIT> : if ( V . getOpcode ( ) == CombineOp )


<s> static unsigned parse_field ( const std :: string & field ) { const char * rest = strchr ( field . c_str ( ) , ':' ) ; if ( rest == NULL ) return - <NUM_LIT> ; char * after ; unsigned fint = strtol ( rest + <NUM_LIT> , & after , <NUM_LIT> ) ; if ( after == rest + <NUM_LIT> )


<s> SDValue <ISA_LIT>TargetLowering :: LowerFormalArguments ( SDValue Chain , CallingConv :: ID CallConv , bool IsVarArg , const SmallVectorImpl < <STR_LIT> > & Ins , const SDLoc & DL , SelectionDAG & DAG , SmallVectorImpl < SDValue > & InVals ) const { switch ( CallConv ) { default : report_fatal_error ( <STR_LIT> ) ; case CallingConv :: C : case CallingConv :: Fast : break ; } MachineFunction & MF = DAG . getMachineFunction ( ) ; MachineRegisterInfo & RegInfo = MF . getRegInfo ( ) ; SmallVector < CCValAssign , <NUM_LIT> > ArgLocs ; CCState CCInfo ( CallConv , IsVarArg , MF , ArgLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeFormalArguments ( Ins , getHasAlu32 ( ) ? CC_<ISA_LIT>32 : CC_<ISA_LIT>64 ) ; for ( auto & VA : ArgLocs ) { if ( VA . isRegLoc ( ) ) { EVT RegVT = VA . getLocVT ( ) ; <STR_LIT> SimpleTy = RegVT . getSimpleVT ( ) . SimpleTy ; switch ( SimpleTy ) { default : { errs ( ) << <STR_LIT> << RegVT . getEVTString ( ) << '\n' ; llvm_unreachable ( <NUM_LIT> ) ; } case <STR_LIT> : case <STR_LIT> : Register VReg = RegInfo . createVirtualRegister ( SimpleTy == <STR_LIT> ? & <STR_LIT> : & <STR_LIT> ) ; RegInfo . addLiveIn ( VA . getLocReg ( )


<s> SDNode * InFP128 = DAG . getMachineNode ( TargetOpcode :: IMPLICIT_DEF , dl , <STR_LIT> ) ; InFP128 = DAG . getMachineNode ( TargetOpcode :: INSERT_SUBREG , dl , <STR_LIT> , SDValue ( InFP128 , <NUM_LIT> ) , Hi64 , SubRegEven ) ; InFP128 = DAG . getMachineNode ( TargetOpcode :: INSERT_SUBREG , dl , <STR_LIT> , SDValue ( InFP128 , <NUM_LIT> ) , Lo64 , SubRegOdd ) ; SDValue OutChains [ <NUM_LIT> ] = { SDValue ( Hi64 . getNode ( ) , <NUM_LIT> ) , SDValue ( Lo64 . getNode ( ) , <NUM_LIT> ) } ; SDValue OutChain = DAG . getNode ( <STR_LIT> ,


<s> void <ISA_LIT>InstPrinter :: printInverseCondCode ( const MCInst * MI , unsigned OpNum , raw_ostream &


<s> void <ISA_LIT>TargetAsmStreamer :: emitDirectiveSetMsa ( ) { OS <<


<s> if ( isFloatingPointZero ( Op ) ) return DAG . getConstant ( <NUM_LIT> , SDLoc ( Op ) , <STR_LIT> ) ; if ( LoadSDNode * Ld = dyn_cast < LoadSDNode > ( Op ) ) return DAG . getLoad ( <STR_LIT> , SDLoc ( Op ) , Ld -> getChain ( ) , Ld -> getBasePtr ( ) , Ld -> getPointerInfo ( ) , Ld -> isVolatile

( ) , Ld -> isNonTemporal ( ) , Ld -> isInvariant ( ) , Ld -> getAlignment ( ) ) ;


<s> void <ISA_LIT>InstrInfo :: insertSelect ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , const DebugLoc & DL , unsigned DstReg , ArrayRef < MachineOperand > Pred , unsigned TrueReg , unsigned FalseReg ) const { MachineRegisterInfo & MRI = MBB . getParent ( ) -> getRegInfo ( ) ; const TargetRegisterClass * RC = MRI . getRegClass ( DstReg ) ; assert ( Pred . size ( ) == <NUM_LIT> && <STR_LIT> ) ; unsigned CCValid = Pred [ <NUM_LIT> ] . getImm ( ) ; unsigned CCMask = Pred [ <NUM_LIT> ] . getImm ( ) ; unsigned Opc ; if ( <STR_LIT> . hasSubClassEq ( RC ) ) { if ( STI . hasLoadStoreOnCond2 ( ) ) Opc = <STR_LIT> ; else { Opc = <STR_LIT> ; MRI . constrainRegClass ( DstReg , & <STR_LIT> ) ; } } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = <STR_LIT> ; else llvm_unreachable ( <STR_LIT> ) ; BuildMI ( MBB , I , DL , get ( Opc ) , DstReg ) . addReg ( FalseReg ) . addReg ( TrueReg )

. addImm ( CCValid ) . addImm ( CCMask ) ;


<s> SDValue FuncTLVGet = DAG . getLoad ( <STR_LIT> , DL , Chain , DescAddr , MachinePointerInfo :: getGOT ( DAG . getMachineFunction ( ) ) , <NUM_LIT> , MachineMemOperand :: MONonTemporal | MachineMemOperand :: MOInvariant ) ; Chain = FuncTLVGet . getValue ( <NUM_LIT> ) ; MachineFrameInfo * MFI = DAG . getMachineFunction ( ) . getFrameInfo ( ) ; MFI -> setAdjustsStack ( true ) ; const uint32_t * Mask = Subtarget -> getRegisterInfo ( ) -> getTLSCallPreservedMask ( ) ; Chain = DAG . getCopyToReg ( Chain , DL

, <STR_LIT> , DescAddr , SDValue ( ) ) ;


<s> if ( parseRegTypeList ( Signature -> Params ) ) return true ; WasmSym -> setSignature ( Signature . get ( ) ) ; addSignature ( std :: move ( Signature ) ) ; WasmSym -> setType ( <STR_LIT> ) ; TOut . emitEventType ( WasmSym ) ; return expect ( AsmToken :: EndOfStatement , <STR_LIT> ) ; } if ( DirectiveID . getString ( ) == <STR_LIT> ) { if ( CurrentState != FunctionStart ) return error ( <STR_LIT> , Lexer . getTok ( ) ) ; SmallVector < <STR_LIT> , <NUM_LIT> > Locals ; if ( parseRegTypeList ( Locals ) ) return true ; TOut . emitLocal ( Locals ) ; CurrentState = FunctionLocals ; return expect ( AsmToken :: EndOfStatement , <STR_LIT> ) ; } if ( DirectiveID . getString ( ) == <STR_LIT> ) { if ( CheckDataSection ( ) ) return true ; int64_t V ; if ( Parser . parseAbsoluteExpression ( V ) ) return error ( <STR_LIT> , Lexer . getTok ( ) ) ; Out . EmitIntValue ( static_cast < uint64_t > ( V ) , <NUM_LIT> ) ; return expect ( AsmToken :: EndOfStatement , <STR_LIT> ) ; } if ( DirectiveID . getString ( ) == <STR_LIT> ) { if ( CheckDataSection ( ) ) return true ; std :: string S ; if ( Parser . parseEscapedString ( S ) ) return error ( <STR_LIT> , Lexer . getTok ( ) ) ; Out . EmitBytes ( StringRef ( S . c_str ( ) , S . length ( ) + <NUM_LIT> ) ) ; return expect ( AsmToken :: EndOfStatement , <STR_LIT> ) ; } return


<s> unsigned SlotSize = RegInfo -> getSlotSize ( ) ; ReturnAddrIndex = MF . getFrameInfo ( ) -> CreateFixedObject ( SlotSize , - ( int64_t ) SlotSize , false ) ; FuncInfo -> setRAIndex (


<s> SDValue RHS = N -> getOperand ( <NUM_LIT> ) ; SDValue CompareOps [ ] = { LHS


<s> Inst . addOperand ( MCOperand :: CreateExpr


<s> DebugLoc DL ; if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; MachineFrameInfo & MFI = * MF . getFrameInfo ( ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo ( PseudoSourceValue :: getFixedStack ( FI ) ) , MachineMemOperand :: MOStore , MFI . getObjectSize ( FI ) , MFI . getObjectAlignment ( FI ) ) ; AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ) ; return ; } <ISA_LIT>BaseInstrInfo :: storeRegToStackSlot ( MBB , I , SrcReg , isKill , FI , RC ,


<s> bool enableMultipleCopyHints ( ) const override { return true


<s> return ( ( int ) ( spu_extract ( spu_gather ( spu_cmpeq ( exp , <NUM_LIT> ) ) , <NUM_LIT> ) == <NUM_LIT>


<s> if ( loc != UNKNOWN_LOCATION ) error_at ( loc , <STR_LIT> <STR_LIT> , avr_addrspace [ as ] . name , <NUM_LIT> * avr_n_flash ) ; return false


<s> for ( MutationList :: iterator it = Mutations . begin ( ) , ie = Mutations . end ( ) ; it != ie ; it ++


<s> return new <ISA_LIT>TargetELFStreamer ( S ,


<s> DOUT ( llvm :: dbgs ( ) << <STR_LIT> << To << <STR_LIT> ; for ( int x = <NUM_LIT> ; x <= <NUM_LIT> ; ++ x ) { AtI [ <NUM_LIT> * x - <NUM_LIT> ] = BUILD_SLLi ( <NUM_LIT> , <NUM_LIT> , <NUM_LIT> ) ; unsigned d = ( Fn >> ( <NUM_LIT> - <NUM_LIT> * x ) ) & <NUM_LIT> ; AtI [ <NUM_LIT> * x ] = BUILD_ORi ( <NUM_LIT> , <NUM_LIT> , d ) ; } AtI [ <NUM_LIT> ] = BUILD_JMP ( <NUM_LIT> ,


<s> MCRegisterInfo * X = new MCRegisterInfo ( ) ; Init<ISA_LIT>MCRegisterInfo ( X


<s> MachineFunction & MF = * MBB . getParent ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; MachineModuleInfo & MMI = MF . getMMI ( ) ; const MCRegisterInfo * MRI = MMI . getContext ( ) . getRegisterInfo ( ) ; const TargetInstrInfo * TII = MF . getTarget ( ) . getInstrInfo ( ) ; DebugLoc DL = MBB . findDebugLoc ( MBBI ) ; const std :: vector < CalleeSavedInfo > & CSI = MFI -> getCalleeSavedInfo ( ) ; if ( CSI . empty ( ) ) return ; const DataLayout * TD = MF . getTarget ( ) . getDataLayout ( ) ; bool HasFP = hasFP ( MF


<s> Chain = DAG . getCopyToReg ( Chain , dl , RegsToPass [ i ] . first , RegsToPass [ i ] . second , InFlag ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; } if ( GlobalAddressSDNode * G = dyn_cast < GlobalAddressSDNode > ( Callee ) ) Callee = DAG . getTargetGlobalAddress ( G -> getGlobal ( ) , dl , <STR_LIT> ) ; else if ( ExternalSymbolSDNode * E = dyn_cast < ExternalSymbolSDNode > ( Callee ) ) Callee = DAG . getTargetExternalSymbol ( E -> getSymbol ( ) , <STR_LIT> ) ; SDVTList NodeTys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . push_back ( Chain ) ; Ops . push_back ( Callee ) ; for ( unsigned i = <NUM_LIT> , e = RegsToPass . size ( ) ; i != e ; ++ i ) Ops . push_back ( DAG . getRegister ( RegsToPass [ i ] . first , RegsToPass [ i ] . second . getValueType ( ) ) ) ; if ( InFlag . getNode ( ) ) Ops . push_back ( InFlag ) ; Chain = DAG . getNode ( <STR_LIT> , dl , NodeTys , & Ops [ <NUM_LIT> ] , Ops . size ( ) ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; Chain = DAG . getCALLSEQ_END ( Chain , DAG . getConstant ( NumBytes , getPointerTy ( ) , true ) , DAG . getConstant ( <NUM_LIT> , getPointerTy ( ) , true ) , InFlag ) ; InFlag = Chain . getValue (


<s> IntID = <STR_LIT> ; break ; case RecurrenceDescriptor :: RK_FloatAdd : IntID = <STR_LIT> ; break ; } if ( IntID == <STR_LIT> ) return nullptr ; Module * M = Builder . GetInsertBlock ( ) -> getParent ( ) -> getParent ( ) ; Function * Intrinsic = <STR_LIT> ( M , IntID , Src ->


<s> Builder . SetCurrentDebugLocation ( I -> getDebugLoc ( ) ) ; Value * Args [ ] = { I -> getOperand ( <NUM_LIT> ) , I -> getOperand ( <NUM_LIT> ) } ; CallInst * Call = Builder . CreateCall ( DSPInst , Args ) ; ReplaceAllUsersOfWith ( I , Call ) ; InstsToRemove . push_back ( I ) ; NewInsts . insert ( Call ) ; TruncTysMap [ Call ] = OrigTy ; } ; auto InsertZExt = [ & ] ( Value * V , Instruction * InsertPt ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * V << <STR_LIT> ) ; Builder . SetInsertPoint ( InsertPt ) ; if ( auto * I = dyn_cast < Instruction > ( V ) ) Builder . SetCurrentDebugLocation ( I -> getDebugLoc ( ) ) ; auto * ZExt = cast < Instruction > ( Builder . CreateZExt ( V , ExtTy ) ) ; if ( isa < Argument > ( V ) ) ZExt -> moveBefore ( InsertPt ) ; else ZExt -> moveAfter ( InsertPt ) ; ReplaceAllUsersOfWith ( V , ZExt ) ; NewInsts . insert ( ZExt ) ; TruncTysMap [ ZExt ] = TruncTysMap [ V ] ; } ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; for ( auto V : Sources ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * V << <STR_LIT> ) ; if ( auto * I = dyn_cast < Instruction > ( V ) ) InsertZExt ( I , I ) ; else if ( auto * Arg = dyn_cast < Argument > ( V ) ) { BasicBlock & BB = Arg -> getParent ( ) -> front ( ) ; InsertZExt ( Arg , & * BB . getFirstInsertionPt ( ) ) ; } else { llvm_unreachable ( <STR_LIT> ) ; } Promoted . insert ( V ) ; } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; for ( auto * V : Visited ) { if ( Sources . count ( V ) ) continue ; auto * I = cast < Instruction > ( V ) ; if ( Sinks . count ( I ) ) continue ; for ( unsigned i = <NUM_LIT> , e = I -> getNumOperands ( ) ; i < e ; ++ i ) { Value * Op = I -> getOperand ( i ) ; if ( ( Op -> getType ( ) == ExtTy ) || ! isa < IntegerType > ( Op -> getType ( ) ) ) continue ; if ( auto * Const = dyn_cast < ConstantInt > ( Op ) ) FixConst ( Const , I ) ; else if ( isa < UndefValue > ( Op ) ) I -> setOperand ( i , UndefValue :: get ( ExtTy ) ) ; } if ( shouldPromote ( I ) ) { I -> mutateType ( ExtTy ) ; Promoted . insert (


<s> ZERO = <STR_LIT> ; BNE = <STR_LIT> ; BEQ = <STR_LIT> ; unsigned Dest = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Ptr = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned OldVal = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned NewVal = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Success = RegInfo . createVirtualRegister ( RC ) ; const BasicBlock * LLVM_BB = BB -> getBasicBlock ( ) ; MachineBasicBlock * loop1MBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * loop2MBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * exitMBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineFunction :: iterator It = ++ BB -> getIterator ( ) ; MF -> insert ( It , loop1MBB ) ; MF -> insert ( It , loop2MBB ) ; MF -> insert ( It , exitMBB ) ; exitMBB -> splice ( exitMBB -> begin ( ) , BB , std :: next ( MachineBasicBlock :: iterator ( MI ) ) , BB -> end ( ) ) ; exitMBB -> transferSuccessorsAndUpdatePHIs ( BB ) ; BB -> addSuccessor ( loop1MBB ) ; loop1MBB -> addSuccessor ( exitMBB ) ; loop1MBB -> addSuccessor ( loop2MBB ) ; loop2MBB -> addSuccessor ( loop1MBB ) ; loop2MBB -> addSuccessor ( exitMBB


<s> EVT VT = Op . getValueType ( ) ; SDLoc DL ( Op ) ; SDValue FrameAddr = DAG . getCopyFromReg ( DAG . getEntryNode ( ) , DL , isN64 ( )


<s> gcc_checking_assert ( n_extra_regs <= MAX_EXTRA_REGS ) ; gcc_assert ( stub < XLOGUE_STUB_COUNT ) ; gcc_assert ( crtl -> stack_realign_finalized ) ; return gen_rtx_SYMBOL_REF ( Pmode , get_stub_name ( stub


<s> bool isMemDisp12 ( MemoryKind MemKind , RegisterKind RegKind ) const { return isMem ( MemKind , RegKind ) && inRange ( Mem

. Disp , <NUM_LIT> , <NUM_LIT> , true ) ;


<s> if ( Tok . isNot ( AsmToken :: Identifier ) ) return - <NUM_LIT> ; std :: string lowerCase = Tok . getString ( ) . lower ( ) ; <STR_LIT> ShiftTy = StringSwitch < <STR_LIT> > ( lowerCase ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( <STR_LIT> ) ; if ( ShiftTy == <STR_LIT> ) return <NUM_LIT> ; Parser . Lex ( ) ; std :: unique_ptr < <ISA_LIT>Operand > PrevOp ( ( <ISA_LIT>Operand * ) Operands . pop_back_val ( ) ) ; if ( ! PrevOp -> isReg ( ) ) return Error ( PrevOp -> getStartLoc ( ) , <STR_LIT> ) ; int SrcReg = PrevOp -> getReg ( ) ; SMLoc EndLoc ; int64_t Imm = <NUM_LIT> ; int ShiftReg = <NUM_LIT> ; if ( ShiftTy == <STR_LIT> ) { ShiftReg = SrcReg ; } else { if ( Parser . getTok ( ) . is ( AsmToken :: Hash ) || Parser . getTok ( ) . is ( AsmToken :: Dollar ) ) { Parser . Lex ( ) ; SMLoc ImmLoc = Parser . getTok ( ) . getLoc ( ) ; const MCExpr * ShiftExpr = nullptr ; if ( getParser ( ) . parseExpression ( ShiftExpr , EndLoc ) ) { Error ( ImmLoc , <STR_LIT> ) ; return - <NUM_LIT> ; } const MCConstantExpr * CE = dyn_cast < MCConstantExpr >


<s> auto <STR_LIT> ( IRBuilder < > & Builder , Value * Mask , Type * FromTy , Type * ToTy ) const -> Value * { assert ( isa < VectorType > ( Mask -> getType ( ) ) ) ; Type * FromSTy = FromTy -> getScalarType ( ) ; Type * ToSTy = ToTy -> getScalarType ( ) ; if ( FromSTy == ToSTy ) return Mask ; int FromSize = getSizeOf ( FromSTy ) ; int ToSize = getSizeOf ( ToSTy ) ; assert ( FromSize % ToSize == <NUM_LIT> || ToSize % FromSize == <NUM_LIT>


<s> StringMap < int > map ; for ( auto Name : a ) map . insert ( std :: make_pair ( Name


<s> switch ( MI . getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : return EmitLoweredSelect ( MI , BB ) ; case <STR_LIT>


<s> emit_insn ( gen_rtx_SET ( dest , GEN_INT ( val & <NUM_LIT> ) ) ) ; if ( mode == SImode ) emit_insn ( gen_insv_immsi ( dest , GEN_INT ( <NUM_LIT> ) , GEN_INT ( ( val >> <NUM_LIT> ) & <NUM_LIT> ) ) ) ; else emit_insn ( gen_insv_immdi ( dest , GEN_INT ( <NUM_LIT> ) , GEN_INT ( ( val >> <NUM_LIT> ) & <NUM_LIT> ) ) ) ; } return <NUM_LIT> ; } mask = <NUM_LIT> ; zero_match = ( ( val & mask ) == <NUM_LIT> ) + ( ( val & ( mask << <NUM_LIT> ) ) == <NUM_LIT> ) + ( ( val & ( mask << <NUM_LIT> ) ) == <NUM_LIT> ) + ( ( val & ( mask << <NUM_LIT> ) ) == <NUM_LIT> ) ; one_match = ( ( ~ val & mask ) == <NUM_LIT> ) + ( ( ~ val & ( mask << <NUM_LIT> ) ) == <NUM_LIT> ) + ( ( ~ val & ( mask << <NUM_LIT> ) ) ==

<NUM_LIT> ) + ( ( ~ val & ( mask << <NUM_LIT> ) ) == <NUM_LIT> ) ;


<s> assert ( CapSize == ( getContext ( ) . getTargetTriple ( ) . isArch64Bit ( ) ? <NUM_LIT> : <NUM_LIT>


<s> else if ( TARGET_X32_P ( ix86_isa_flags ) ) return <STR_LIT> ; else return


<s> Ops . push_back ( V ) ; continue ; } MVT OpVT = V . getSimpleValueType ( ) ; MVT ContainerVT = getContainerForFixedLengthVector ( OpVT ) ; assert ( useRVVForFixedLengthVectorVT ( OpVT ) && <STR_LIT> ) ; Ops . push_back ( convertToScalableVector ( ContainerVT , V , DAG , Subtarget ) ) ; } if ( ! VT . isFixedLengthVector ( ) ) return DAG . getNode ( <ISA_LIT>ISDOpc , DL , VT ,


<s> SDLoc DL ( Op ) ; return DAG . getNode ( <STR_LIT> , DL , Op . getValueType ( ) , Op


<s> void <ISA_LIT>InstPrinter :: printSIMDType10Operand ( const MCInst * MI , unsigned OpNo , const MCSubtargetInfo & STI , raw_ostream & O ) { unsigned RawVal = MI -> getOperand ( OpNo ) .


<s> AU . addPreserved < DominatorTreeWrapperPass > ( ) ; AU . addRequired < TargetPassConfig > ( ) ; FunctionPass :: getAnalysisUsage ( AU


<s> GlobalAddressSDNode * GSDN = cast < GlobalAddressSDNode > ( Op ) ; DebugLoc DL = GSDN -> getDebugLoc ( ) ; const GlobalValue * GV = GSDN -> getGlobal ( ) ; if ( <ISA_LIT>SubTarget . isSVR4ABI ( ) && <ISA_LIT>SubTarget . is<ISA_LIT>64 ( ) ) { SDValue GA = DAG . getTargetGlobalAddress ( GV , DL , PtrVT , GSDN -> getOffset ( ) ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , GA , DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ) ; } unsigned MOHiFlag , MOLoFlag ; bool isPIC = GetLabelAccessInfo ( DAG . getTarget ( ) , MOHiFlag , MOLoFlag , GV ) ; SDValue GAHi = DAG . getTargetGlobalAddress ( GV , DL , PtrVT , GSDN -> getOffset ( ) , MOHiFlag ) ; SDValue GALo = DAG . getTargetGlobalAddress ( GV , DL , PtrVT , GSDN -> getOffset ( ) , MOLoFlag ) ; SDValue Ptr = LowerLabelRef ( GAHi , GALo , isPIC , DAG ) ; if ( MOHiFlag & <STR_LIT> ) Ptr = DAG . getLoad ( PtrVT , DL , DAG . getEntryNode ( ) , Ptr , MachinePointerInfo ( ) , false , false , <NUM_LIT> ) ; return


<s> IdxOffset = ConstantInt :: get ( Int32Ty , CumulativeIndex ) ; } else if ( NextRef == ArrayElemRef ) { IdxOffset = IRB . CreateBinOp ( Instruction :: Mul , ConstantInt :: get ( Int32Ty , APInt ( <NUM_LIT> , getNumElements ( cast < ArrayType > ( PrevTy ) -> getElementType ( ) , AccessMemFormFlatStruct ) ) ) , IdxVal ) ; } else IdxOffset = IdxVal ; if ( isa < ArrayType > ( IdxTy ) ) NextRef = ArrayElemRef ; else if ( isa < StructType > ( IdxTy ) || isa < PointerType > ( IdxTy ) ) NextRef = StructFieldRef ; else NextRef = ScalarRef ; Idx = IRB . CreateBinOp ( Instruction :: Add , Idx , IdxOffset ) ; if ( -- NumLeadingNonLeafArrDim == <NUM_LIT> ) return Idx ; PrevTy = IdxTy ; } if ( isa < GetElementPtrInst > ( * ( GI -> user_begin ( ) ) ) ) return getTyIndexInFlattenedType_core ( Func , Idx , cast <

GetElementPtrInst > ( * ( GI -> user_begin ( ) ) ) , AccessMemFormFlatStruct ) ;


<s> moxie_compute_frame ( ) ; if ( flag_stack_usage_info ) current_function_static_stack_size = cfun -> machine -> size_for_adjusting_sp ; for ( regno = <NUM_LIT> ; regno < FIRST_PSEUDO_REGISTER ; regno ++ ) { if ( df_regs_ever_live_p ( regno ) && ! call_used_or_fixed_reg_p ( regno ) ) { insn = emit_insn ( gen_movsi_push ( gen_rtx_REG ( Pmode , regno ) ) ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; } } if ( cfun -> machine -> size_for_adjusting_sp > <NUM_LIT> ) { int i = cfun -> machine -> size_for_adjusting_sp ; while ( ( i >= <NUM_LIT> ) && ( i <= <NUM_LIT> ) ) { insn = emit_insn ( gen_subsi3 ( stack_pointer_rtx , stack_pointer_rtx , GEN_INT ( <NUM_LIT> ) ) ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; i -= <NUM_LIT> ; } if ( i <= <NUM_LIT> ) { insn = emit_insn ( gen_subsi3 ( stack_pointer_rtx , stack_pointer_rtx , GEN_INT ( i ) ) ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; } else { rtx reg = gen_rtx_REG ( SImode , MOXIE_R12 ) ; insn = emit_move_insn ( reg , GEN_INT ( i ) ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; insn = emit_insn ( gen_subsi3 ( stack_pointer_rtx


<s> return getSubtargetImpl ( ) -> getRegisterInfo


<s> bool runOnMachineFunction ( MachineFunction & MF ) override { if ( skipFunction ( * MF . getFunction ( ) ) ) return false ; initialize ( MF )


<s> void emitConstant ( uint64_t Val , unsigned Size , raw_ostream & OS ) const { for ( unsigned i = <NUM_LIT> ; i != Size ; ++ i ) { emitByte ( Val & <NUM_LIT> , OS ) ; Val >>=


<s> return ( int32x4_t ) __builtin_neon_vreinterpretv4siv2di (


<s> storeRegToStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned SrcReg , bool isKill , int FI , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { DebugLoc DL ; if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; if ( RC == <STR_LIT> ) BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT>

) . addReg ( SrcReg , getKillRegState ( isKill ) ) ;


<s> unsigned FrameReg = GetFrameReg ( Ctx , Out ) ; if ( MRI && FrameReg != <STR_LIT> ) { SpillReg ( Out , <STR_LIT> ) ; if ( FrameReg == <STR_LIT> ) { Out . EmitCFIAdjustCfaOffset ( <NUM_LIT> ) ; Out . EmitCFIRelOffset ( MRI -> getDwarfRegNum ( <STR_LIT> , true ) , <NUM_LIT> ) ; } EmitInstruction ( Out , MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( FrameReg ) ) ; Out . EmitCFIRememberState ( ) ; Out . EmitCFIDefCfaRegister ( MRI -> getDwarfRegNum ( <STR_LIT> , true ) ) ; } EmitAdjustRSP ( Ctx , Out , - <NUM_LIT> ) ; SpillReg ( Out , RegCtx . shadowReg


<s> void onNot ( ) { IntelExprState CurrState = State ; switch ( State ) { default : State = IES_ERROR ; break ; case IES_OR : case IES_XOR : case IES_AND : case IES_LSHIFT : case IES_RSHIFT : case IES_PLUS : case IES_MINUS : case IES_NOT : case IES_MULTIPLY : case IES_DIVIDE : case IES_MOD : case IES_LPAREN : case IES_LBRAC : State = IES_NOT ; IC . pushOperator


<s> SDValue Cmp = Op . getOperand ( <NUM_LIT> ) ; if ( Cmp . getOpcode ( ) != <STR_LIT> || ! Cmp . hasOneUse ( ) || Cmp . getOperand ( <NUM_LIT> ) . getValueType ( ) != <STR_LIT> ) return false ; if ( auto * Constant = dyn_cast < ConstantSDNode > ( Cmp . getOperand ( <NUM_LIT> ) ) ) { int64_t NegConstant = <NUM_LIT> - Constant -> getSExtValue ( ) ; return isInt < <NUM_LIT> > ( NegConstant ) ; } return false ; } ; bool LHSHasPattern = isZextOfCompareWithConstant ( LHS ) ; bool RHSHasPattern = isZextOfCompareWithConstant ( RHS ) ; if ( LHSHasPattern && ! RHSHasPattern ) std :: swap ( LHS , RHS ) ; else if ( ! LHSHasPattern && ! RHSHasPattern ) return SDValue ( ) ; SDLoc DL ( N ) ; SDVTList VTs = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SDValue Cmp = RHS . getOperand ( <NUM_LIT> ) ; SDValue Z = Cmp . getOperand ( <NUM_LIT> ) ; auto * Constant = dyn_cast < ConstantSDNode > ( Cmp . getOperand ( <NUM_LIT> ) ) ; assert ( Constant && <STR_LIT> ) ; int64_t NegConstant = <NUM_LIT> - Constant -> getSExtValue ( ) ; switch ( cast < CondCodeSDNode > ( Cmp . getOperand ( <NUM_LIT> ) ) -> get ( ) ) { default : break ; case <STR_LIT> : { SDValue Add = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Z , DAG . getConstant ( NegConstant , DL , <STR_LIT> ) ) ; SDValue AddOrZ = NegConstant != <NUM_LIT> ? Add : Z ; SDValue Addc = DAG . getNode ( <STR_LIT> , DL , DAG . getVTList ( <STR_LIT> , <STR_LIT> ) , AddOrZ , DAG . getConstant ( - <NUM_LIT> , DL


<s> ArgValue2 = DAG . getLoad ( <STR_LIT> , dl , Root , FIN , MachinePointerInfo :: getFixedStack ( FI ) , false , false , false , <NUM_LIT> ) ; } else { Reg = MF . addLiveIn ( NextVA . getLocReg ( ) , RC ) ; ArgValue2 = DAG . getCopyFromReg ( Root , dl , Reg , <STR_LIT> ) ; } return DAG . getNode ( <STR_LIT> , dl


<s> static unsigned compute_vlmax ( unsigned vector_bits , unsigned elt_size , unsigned min_size ) { return ( ( vector_bits / elt_size ) *


<s> { <STR_LIT> , winnt_d_handle_target_object_format } , { NULL , NULL } , } ; d_add_target_info_handlers ( handlers )


<s> auto Offsets = splitBufferOffsets ( Op . getOperand ( <NUM_LIT> ) , DAG ) ; SDValue Ops [ ] = { Op . getOperand ( <NUM_LIT> ) , VData , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Offsets . first , Op . getOperand ( <NUM_LIT> ) , Offsets . second , Op . getOperand ( <NUM_LIT> ) ,

DAG . getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) , } ;


<s> const MCExpr * getImm ( ) const { assert ( isImm ( ) &&


<s> case <STR_LIT> : return LowerSETCC ( Op , DAG ) ; case <STR_LIT> : return LowerSETCCCARRY ( Op , DAG ) ; case <STR_LIT> : return LowerSELECT ( Op , DAG ) ; case <STR_LIT> : return LowerBRCOND ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerADDC_ADDE_SUBC_SUBE ( Op , DAG ) ; case <STR_LIT> : return LowerConstantPool ( Op , DAG ) ; case <STR_LIT> : return LowerGlobalAddress ( Op , DAG ) ; case <STR_LIT> : return LowerExternalSymbol ( Op , DAG ) ; case <STR_LIT> : return LowerBlockAddress ( Op , DAG ) ; case <STR_LIT> : return LowerJumpTable ( Op , DAG ) ; case <STR_LIT> : return LowerVASTART ( Op , DAG ) ; case


<s> const std :: vector < MVT > & getParams


<s> void addRegOperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: createReg


<s> const <ISA_LIT>InstrInfo * TII = ST . getInstrInfo ( ) ; unsigned NumWaitStates = TII -> getNumWaitStates ( * CurrCycleInstr ) ; EmittedInstrs . push_front ( CurrCycleInstr ) ; for ( unsigned i = <NUM_LIT> , e = std :: min ( NumWaitStates , getMaxLookAhead ( ) ) ; i < e ; ++ i ) { EmittedInstrs . push_front ( nullptr ) ; } EmittedInstrs . resize ( getMaxLookAhead