<s> if ( r -> n_allocated == r -> n_in_use ) r -> replacement [ r -> n_allocated ++ ] = gen_reg_rtx ( r -> mode ) ; return r -> replacement [ r


<s> FrameIndexSDNode * FIN = <NUM_LIT> ; if ( ( FIN = dyn_cast < FrameIndexSDNode > ( Addr ) ) ) { Base = CurDAG -> getTargetFrameIndex ( FIN -> getIndex ( ) , <STR_LIT> ) ; Offset = CurDAG -> getTargetConstant ( <NUM_LIT> , <STR_LIT> ) ; return true ; } if ( Addr . getOpcode ( ) == <STR_LIT> ) { ConstantSDNode * CN =


<s> } LLVM_FALLTHROUGH ; } case <STR_LIT> : case <STR_LIT> : { assert ( ( VT . is128BitVector ( ) || Subtarget . hasAVX2 ( ) ) && <STR_LIT> ) ; if ( Subtarget . hasBWI ( ) && Subtarget . hasVLX ( ) ) { MVT IntegerType = <STR_LIT> ( std :: max ( ( int ) VT . getVectorNumElements ( ) , <NUM_LIT> ) ) ; SDValue MaskNode = DAG . getConstant ( BlendMask , DL , IntegerType ) ; return getVectorMaskingNode ( V2 , MaskNode , V1 , Subtarget , DAG ) ; } if ( SDValue Masked = lowerVectorShuffleAsBitMask ( DL , VT , V1 , V2 , Mask , Zeroable , DAG ) ) return Masked ; int Scale = VT . getScalarSizeInBits ( ) / <NUM_LIT> ; MVT BlendVT = <STR_LIT> ( <STR_LIT> , VT . getSizeInBits ( ) / <NUM_LIT> ) ; SmallVector < SDValue , <NUM_LIT> > VSELECTMask ; for ( int i = <NUM_LIT> , Size = Mask . size ( ) ; i < Size ; ++ i ) for ( int j = <NUM_LIT> ; j < Scale ; ++ j ) VSELECTMask . push_back ( Mask [ i ] < <NUM_LIT> ? DAG . getUNDEF ( <STR_LIT> ) : DAG . getConstant ( Mask [ i ] < Size ? - <NUM_LIT> : <NUM_LIT> , DL , <STR_LIT> ) ) ; V1 = DAG . getBitcast ( BlendVT , V1 ) ; V2 = DAG . getBitcast ( BlendVT , V2 ) ; return DAG . getBitcast ( VT , DAG . getSelect ( DL , BlendVT , DAG . getBuildVector ( BlendVT , DL , VSELECTMask ) , V1 , V2 ) ) ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> return ( __builtin_sh_media_LDHI_Q ( ( char * ) p + <NUM_LIT> ) | __builtin_sh_media_LDLO_Q ( p ) ) ; return ( __builtin_sh_media_LDLO_Q ( ( char * ) p +

<NUM_LIT> ) | __builtin_sh_media_LDHI_Q ( p ) ) ;


<s> unsigned Op0SignBits = DAG . ComputeNumSignBits ( Op . getOperand ( <NUM_LIT> ) , Depth + <NUM_LIT> ) ; return std :: max ( SignBits , Op0SignBits ) ; } case <STR_LIT> : { ConstantSDNode * Width = dyn_cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) ; return Width ? <NUM_LIT> - ( Width -> getZExtValue ( ) & <NUM_LIT> ) : <NUM_LIT> ; } case <STR_LIT> : case


<s> bool <ISA_LIT>IndirectThunks :: runOnMachineFunction ( MachineFunction & MF ) { LLVM_DEBUG ( dbgs ( ) << getPassName ( ) << '\n' ) ; auto & MMI = getAnalysis < MachineModuleInfoWrapperPass > ( ) .


<s> <ISA_LIT>CodeGenPrepare ( const TargetMachine * TM =


<s> bool <ISA_LIT>AsmParser :: isToken ( const AsmToken :: TokenKind


<s> MachineInstr * <ISA_LIT>InstructionSelector :: emitCSetForFCmp ( Register Dst , CmpInst :: Predicate Pred , MachineIRBuilder & MIRBuilder ) const { MachineRegisterInfo & MRI = * MIRBuilder . getMRI ( ) ; LLT Ty = MRI . getType ( Dst ) ; assert ( ! Ty . isVector ( ) && Ty . getSizeInBits ( ) == <NUM_LIT> && <STR_LIT> ) ; const Register ZReg = <STR_LIT> ; <STR_LIT> CC1 , CC2 ; changeFCMPPredTo<ISA_LIT>CC ( Pred , CC1 , CC2 ) ; auto InvCC1 = <STR_LIT> ( CC1 ) ; if ( CC2 == <STR_LIT> ) return emitCSINC ( Dst , ZReg , ZReg , InvCC1 , MIRBuilder ) ; const TargetRegisterClass * RC = & <STR_LIT> ; Register Def1Reg = MRI . createVirtualRegister (


<s> MCStreamer * create<ISA_LIT>WinCOFFStreamer ( MCContext & C , MCAsmBackend & AB , MCCodeEmitter * CE , raw_ostream & OS , bool RelaxAll ) { <ISA_LIT>WinCOFFStreamer * S = new <ISA_LIT>WinCOFFStreamer ( C , AB , CE , OS ) ; S -> getAssembler ( ) . setRelaxAll ( RelaxAll ) ; return S


<s> if ( <STR_LIT> ( Op . getOperand ( <NUM_LIT> ) . getNode ( ) ) && Op . getConstantOperandVal ( <NUM_LIT> ) == <NUM_LIT> ) Op = Op . getOperand ( <NUM_LIT> ) ; else return SDValue ( ) ; } else { if ( isExpandWithZeros ( Op ) ) Op = Op . getOperand ( <NUM_LIT> ) ; else return SDValue


<s> if ( ! VT . isVector ( ) ) return getPointerTy ( DL ) ; if ( Subtarget . hasStdExtV ( ) ) return <STR_LIT> ( <STR_LIT> , VT . getVectorElementCount ( ) ) ; return VT . changeVectorElementTypeToInteger


<s> SDValue GA = DAG . getTargetJumpTable ( JT -> getIndex ( ) , Ty , <STR_LIT> ) ; SDValue MatAddr = DAG . getNode ( <STR_LIT> , DL , Ty , GA ) ; return MatAddr ; } if ( Subtarget . is64BitELFABI ( ) || Subtarget . isAIXABI ( ) ) { setUsesTOCBasePtr ( DAG ) ; SDValue GA = DAG . getTargetJumpTable ( JT -> getIndex ( ) , PtrVT ) ; return getTOCEntry ( DAG , SDLoc ( JT


<s> bool <ISA_LIT>TargetLowering :: isCheapAddrSpaceCast ( unsigned SrcAS , unsigned DestAS ) const { if ( SrcAS == AMDGPUA<ISA_LIT> . FLAT_ADDRESS ) return true ; return isNoopAddrSpaceCast ( SrcAS


<s> rewriteEdge ( src , i -> second -> Dst ) ; } } else if ( src -> Region != dst -> Region ) { for ( MachineBasicBlock :: instr_iterator j ( sbb -> instr_begin ( ) ) , je ( sbb -> instr_end ( ) ) ; j != je ; j ++ ) { MachineInstr * mi = & * j ; if ( ! mi -> isTerminator ( ) || mi -> isReturn ( ) || mi -> isBundle ( ) ) continue ; switch ( mi -> getOpcode ( ) ) { case <STR_LIT>


<s> if ( TREE_CODE ( type ) == VECTOR_TYPE || TREE_CODE ( type ) == COMPLEX_TYPE ) type = TREE_TYPE ( type ) ; unsigned HOST_WIDE_INT elt_size = int_size_in_bytes ( type ) ; machine_mode elt_mode = TYPE_MODE ( type ) == BLKmode ? Pmode : DImode ; elt_size |= GET_MODE_SIZE ( elt_mode ) ; elt_size &= - elt_size ; init_frag . size = elt_size ; init_frag . mask = ( ( unsigned HOST_WIDE_INT ) <NUM_LIT> << ( elt_size * BITS_PER_UNIT - <NUM_LIT> ) ) - <NUM_LIT> ; init_frag . val = <NUM_LIT> ; init_frag . offset = <NUM_LIT> ; init_frag . started = false ; init_frag . remaining = ( size + elt_size -


<s> if ( And1 . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; if ( ! ( CN = dyn_cast < ConstantSDNode > ( And1 . getOperand ( <NUM_LIT> ) ) ) || ! isShiftedMask ( CN -> getZExtValue ( ) , SMPos1 , SMSize1 ) ) return SDValue ( ) ; if ( SMPos0 != SMPos1 || SMSize0 != SMSize1 ) return SDValue ( ) ; SDValue Shl = And1 . getOperand ( <NUM_LIT> ) ; if ( Shl . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; if ( ! ( CN = dyn_cast < ConstantSDNode > ( Shl . getOperand ( <NUM_LIT> ) ) ) ) return SDValue ( ) ; unsigned Shamt = CN -> getZExtValue ( ) ; EVT ValTy = N -> getValueType


<s> InsertExport = true ; } ReturnInst :: Create ( F . getContext ( ) , RetVal , DummyReturnBB ) ; ReturningBlocks . push_back ( DummyReturnBB ) ; } if ( BI -> isUnconditional ( ) ) { BasicBlock * LoopHeaderBB = BI -> getSuccessor ( <NUM_LIT> ) ; BI -> eraseFromParent ( ) ; BranchInst :: Create ( LoopHeaderBB , DummyReturnBB , BoolTrue , BB ) ; Updates . push_back ( { DominatorTree :: Insert , BB , DummyReturnBB } ) ; } else { SmallVector < BasicBlock * , <NUM_LIT> > Successors ( succ_begin ( BB ) , succ_end ( BB ) ) ; BasicBlock * TransitionBB = BB -> splitBasicBlock ( BI , <STR_LIT> ) ; Updates . reserve ( Updates . size ( ) + <NUM_LIT> * Successors . size ( ) + <NUM_LIT> ) ; Updates . push_back ( { DominatorTree :: Insert , BB , TransitionBB } ) ; for ( BasicBlock * Successor : Successors ) { Updates . push_back ( { DominatorTree :: Insert , TransitionBB , Successor } ) ; Updates . push_back ( { DominatorTree :: Delete , BB , Successor } ) ; } BB -> getTerminator ( ) -> eraseFromParent ( ) ; BranchInst :: Create ( TransitionBB , DummyReturnBB , BoolTrue , BB ) ; Updates . push_back ( { DominatorTree :: Insert , BB , DummyReturnBB } ) ; } Changed = true ; } } if ( ! UnreachableBlocks . empty ( ) ) { BasicBlock * UnreachableBlock = nullptr ; if ( UnreachableBlocks . size ( ) == <NUM_LIT> ) { UnreachableBlock = UnreachableBlocks . front ( ) ; } else { UnreachableBlock = BasicBlock :: Create ( F . getContext ( ) , <STR_LIT> , & F ) ; new UnreachableInst ( F . getContext ( ) , UnreachableBlock ) ; Updates . reserve ( Updates . size ( ) + UnreachableBlocks . size ( ) ) ; for ( BasicBlock * BB : UnreachableBlocks ) { BB -> getTerminator ( ) -> eraseFromParent ( ) ; BranchInst :: Create ( UnreachableBlock , BB ) ; Updates . push_back ( { DominatorTree :: Insert , BB , UnreachableBlock } ) ; } Changed = true ; } if ( ! ReturningBlocks . empty ( ) ) { Type * RetTy = F . getReturnType (


<s> static void write_function_decl_and_comment ( std :: stringstream & s , const char * name , const_tree decl ) { s << <STR_LIT> ; if ( TREE_PUBLIC ( decl ) ) s


<s> if ( & I != G -> getKill ( ) ) { MachineOperand & MO = I . getOperand ( <NUM_LIT> ) ; bool Change = TransformAll || getColor ( MO . getReg ( ) ) != C ; if ( G -> requiresFixup ( ) && & I == G -> getLast ( ) ) Change = false ; if ( Change ) { Substs [ MO . getReg ( ) ] = Reg ; MO . setReg ( Reg ) ; Changed = true ; } } } assert ( Substs . size ( ) == <NUM_LIT> && <STR_LIT> ) ; if ( G -> getKill ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; } else { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; } return Changed


<s> tree decl = def_builtin2 ( mask , name , tcode , code ) ; if ( decl ) DECL_PURE_P ( decl ) = <NUM_LIT> ; else ix86_builtins_isa [ ( int ) code ] . pure_p =


<s> case TargetOpcode :: COPY : { unsigned DstReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; return ( <STR_LIT> . contains ( DstReg ) || <STR_LIT> . contains ( DstReg ) ) ; } case <STR_LIT> : if ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) { assert ( MI -> getDesc ( ) . getNumOperands ( ) == <NUM_LIT> && MI -> getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> && <STR_LIT> ) ; return true


<s> SDValue T ; if ( CPN -> isMachineConstantPoolEntry ( ) ) T = DAG . getTargetConstantPool ( CPN -> getMachineCPVal ( ) , ValTy , Align , Offset , TF ) ; else if ( isVTi1Type ) T = DAG . getTargetConstantPool ( CVal , ValTy , Align , Offset , TF ) ; else T = DAG . getTargetConstantPool ( CPN -> getConstVal ( ) , ValTy , Align , Offset , TF ) ; assert ( cast < ConstantPoolSDNode > ( T ) -> getTargetFlags ( ) == TF && <STR_LIT> ) ; if ( IsPositionIndependent ) return DAG . getNode ( <STR_LIT> , SDLoc ( Op ) , ValTy


<s> inline bool CC_XPLINK64_Shadow_Reg ( unsigned & ValNo , MVT & ValVT , MVT & LocVT , CCValAssign :: LocInfo & LocInfo , <STR_LIT> & ArgFlags , CCState & State ) { if ( LocVT == <STR_LIT> || LocVT == <STR_LIT> ) { State . AllocateReg ( <STR_LIT> ) ; } if ( LocVT == <STR_LIT> || LocVT . is128BitVector ( ) ) { State . AllocateReg ( <STR_LIT> ) ; State . AllocateReg ( <STR_LIT> ) ; if ( LocVT == <STR_LIT> ) { for ( unsigned I = <NUM_LIT> ; I < <STR_LIT> ; I += <NUM_LIT> ) if ( State . isAllocated ( <STR_LIT> [ I ] ) ) State . AllocateReg ( <STR_LIT> [ I + <NUM_LIT> ] ) ; } } return false


<s> return TargetTriple . getEnvironment ( )


<s> auto ScaledY = B . buildFMul ( S32 , RcpIFlag , Scale ) ; auto Z = B . buildFPTOUI ( S32 , ScaledY ) ; auto NegY = B . buildSub ( S32 , B . buildConstant ( S32 , <NUM_LIT> ) , Y ) ; auto NegYZ = B . buildMul ( S32 , NegY , Z ) ; Z = B . buildAdd ( S32 , Z , B . buildUMulH ( S32 , Z , NegYZ ) ) ; auto Q = B . buildUMulH ( S32 , X , Z ) ; auto R = B . buildSub ( S32 , X , B . buildMul ( S32 , Q , Y ) ) ; auto One = B . buildConstant ( S32 , <NUM_LIT> ) ; auto Cond = B . buildICmp ( CmpInst :: ICMP_UGE , S1 , R , Y ) ; if ( DstDivReg ) Q = B . buildSelect ( S32 , Cond , B . buildAdd ( S32 , Q , One ) , Q ) ; R = B . buildSelect ( S32 , Cond , B . buildSub ( S32 , R , Y ) , R ) ; Cond = B . buildICmp ( CmpInst :: ICMP_UGE , S1 , R , Y ) ; if ( DstDivReg ) B . buildSelect ( DstDivReg , Cond , B . buildAdd ( S32 , Q , One ) , Q ) ; if ( DstRemReg ) B . buildSelect ( DstRemReg , Cond , B . buildSub ( S32 , R , Y ) ,


<s> case Instruction :: Shl : ValueShifted = Builder . CreateShl ( ValuePHI , ConstantInt :: get ( Int32Ty , <NUM_LIT> ) ) ; break ; case Instruction :: LShr : ValueShifted = Builder . CreateLShr ( ValuePHI , ConstantInt :: get ( Int32Ty , <NUM_LIT> ) ) ; break ; case Instruction :: AShr : ValueShifted = Builder . CreateAShr ( ValuePHI , ConstantInt :: get ( Int32Ty , <NUM_LIT> ) ) ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } ValuePHI -> addIncoming ( ValueShifted , LoopBB ) ; Value * Cmp2 = Builder . CreateICmpEQ ( ShiftAmountSub , Int8Zero ) ; Builder . CreateCondBr ( Cmp2 , EndBB , LoopBB ) ; Builder . SetInsertPoint ( BI ) ; PHINode * Result = Builder . CreatePHI ( Int32Ty , <NUM_LIT> ) ; Result -> addIncoming ( BI -> getOperand


<s> case <STR_LIT> : case FK_Data_4 : Type = ELF :: R_<ISA_LIT>_32 ; break ; case <STR_LIT> : Type = ELF :: R_<ISA_LIT>_HI16 ; break ; case <STR_LIT> : Type = ELF :: R_<ISA_LIT>_LO16 ; break ; case <STR_LIT> : Type = ELF :: R_<ISA_LIT>_NONE ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } return Type


<s> static rtx gen_frame_store ( rtx reg , rtx frame_reg , int offset


<s> LoopUse = counter ; } ++ counter ; } MachineInstr * DefMI = MRI -> getVRegDef ( Phi -> getOperand ( LoopUse ) . getReg ( ) ) ; if ( DefMI == nullptr ) continue ; for ( MachineOperand & MO : DefMI -> uses ( ) ) { if ( MO . isReg ( ) && MO . getReg ( ) == PhiDef && <ISA_LIT>II :: isAdd ( DefMI -> getDesc ( ) ) ) { if ( DefMI -> getOperand ( <NUM_LIT> ) . isImm ( ) ) { LinearIVs [ DefMI ] = <NUM_LIT>


<s> static __inline qword si_rotqmbii ( qword a , int count ) { return ( ( qword ) ( vec_srl ( ( vec_uchar16 ) ( a ) , vec_splat ( ( vec_uchar16 ) ( si_from_int ( <NUM_LIT> - count )


<s> static void CalculateTailCallArgDest ( SelectionDAG & DAG , MachineFunction & MF , bool is<ISA_LIT>64 , SDValue Arg , int SPDiff , unsigned ArgOffset , SmallVector < TailCallArgumentInfo , <NUM_LIT> > & TailCallArguments ) { int Offset = ArgOffset + SPDiff ; uint32_t OpSize = ( Arg . getValueType ( ) . getSizeInBits ( ) + <NUM_LIT> ) / <NUM_LIT> ; int FI = MF . getFrameInfo ( ) -> CreateFixedObject ( OpSize , Offset , true ) ; EVT VT = is<ISA_LIT>64 ? <STR_LIT> : <STR_LIT> ; SDValue FIN = DAG . getFrameIndex ( FI , VT ) ; TailCallArgumentInfo Info ; Info . Arg =


<s> static const <ISA_LIT>MCExpr * CreateABS_G1_NC ( const MCExpr * Expr , MCContext


<s> if ( cfun -> machine -> naked_p ) return ; if ( riscv_use_save_libcall ( frame ) ) { rtx dwarf = NULL_RTX ; dwarf = riscv_adjust_libcall_cfi_prologue ( ) ; size -= frame -> save_libcall_adjustment ; insn = emit_insn ( riscv_gen_gpr_save_insn ( frame ) ) ; frame -> mask = <NUM_LIT> ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; REG_NOTES ( insn ) = dwarf ; } if ( ( frame -> mask | frame -> fmask ) != <NUM_LIT> ) { HOST_WIDE_INT step1 = MIN ( size , riscv_first_stack_step ( frame ) ) ; insn = gen_add3_insn ( stack_pointer_rtx , stack_pointer_rtx , GEN_INT ( - step1 ) ) ; RTX_FRAME_RELATED_P ( emit_insn ( insn ) ) = <NUM_LIT> ; size -=


<s> auto MRSMapper = <STR_LIT> ( ) ; uint32_t MRSReg = MRSMapper . fromString ( Tok . getString ( ) , STI . getFeatureBits ( ) , IsKnown ) ; assert ( IsKnown == ( MRSReg != - <NUM_LIT> ) && <STR_LIT> ) ; auto MSRMapper = <STR_LIT> ( ) ; uint32_t MSRReg = MSRMapper . fromString ( Tok . getString ( ) , STI . getFeatureBits ( ) , IsKnown ) ; assert ( IsKnown == ( MSRReg != - <NUM_LIT> ) && <STR_LIT> ) ; auto PStateMapper = <STR_LIT> ( ) ; uint32_t PStateField = PStateMapper . fromString ( Tok . getString ( ) , STI . getFeatureBits ( ) , IsKnown ) ; assert ( IsKnown == ( PStateField != - <NUM_LIT> ) && <STR_LIT> ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateSysReg ( Tok . getString ( ) , getLoc ( ) ,

MRSReg , MSRReg , PStateField , getContext ( ) ) ) ;


<s> default : llvm_unreachable ( <STR_LIT> ) ; case CmpInst :: FCMP_OEQ : CC = <NUM_LIT> ; break ; case CmpInst :: FCMP_OGT : NeedSwap = true ; LLVM_FALLTHROUGH ; case CmpInst :: FCMP_OLT : CC = <NUM_LIT> ; break ; case CmpInst :: FCMP_OGE : NeedSwap = true ; LLVM_FALLTHROUGH ; case CmpInst :: FCMP_OLE : CC = <NUM_LIT> ; break ; case CmpInst :: FCMP_UNO : CC = <NUM_LIT> ; break ; case CmpInst :: FCMP_UNE : CC = <NUM_LIT> ; break ; case CmpInst :: FCMP_ULE : NeedSwap = true ; LLVM_FALLTHROUGH ; case CmpInst :: FCMP_UGE : CC = <NUM_LIT> ; break ; case CmpInst :: FCMP_ULT : NeedSwap = true


<s> auto CurSled = OutContext . createTempSymbol ( <STR_LIT> , true ) ; OutStreamer -> emitLabel ( CurSled ) ; auto Target = OutContext . createTempSymbol ( ) ; const MCExpr * TargetExpr = MCSymbolRefExpr :: create ( Target , MCSymbolRefExpr :: VariantKind :: VK_None , OutContext ) ; EmitToStreamer ( * OutStreamer , MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addExpr ( TargetExpr ) ) ; for ( int8_t I = <NUM_LIT> ; I < NoopsInSledCount ; I ++ ) EmitToStreamer ( * OutStreamer , MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ) ; OutStreamer -> emitLabel ( Target ) ; if ( ! Subtarget -> isGP64bit ( ) ) { EmitToStreamer ( * OutStreamer , MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ) ; } recordSled ( CurSled , MI , Kind , <NUM_LIT>


<s> if ( recog_memoized ( in_insn ) < <NUM_LIT> || ( get_attr_type ( in_insn ) != TYPE_FPSTORE && get_attr_type ( in_insn ) != TYPE_FPSTORE_LOAD ) || recog_memoized ( out_insn ) < <NUM_LIT> ) return <NUM_LIT> ; store_mode = GET_MODE ( SET_SRC ( PATTERN ( in_insn ) ) ) ; set = single_set ( out_insn ) ; if ( ! set ) return <NUM_LIT> ; other_mode = GET_MODE ( SET_SRC ( set ) ) ; return ( GET_MODE_SIZE ( store_mode ) ==


<s> WorkItemIDX = true ; } if ( ST . debuggerEmitPrologue ( ) ) { WorkGroupIDY = true ; WorkGroupIDZ = true ; WorkItemIDY = true ; WorkItemIDZ = true ; } else { if ( F -> hasFnAttribute ( <STR_LIT> ) ) WorkGroupIDY = true ; if ( F -> hasFnAttribute ( <STR_LIT> ) ) WorkGroupIDZ = true ; if ( F -> hasFnAttribute ( <STR_LIT> ) ) WorkItemIDY = true ; if ( F -> hasFnAttribute ( <STR_LIT> ) ) WorkItemIDZ = true ; } if ( WorkItemIDZ ) WorkItemIDY = true ; const MachineFrameInfo & FrameInfo = MF . getFrameInfo ( ) ; bool MaySpill = ST . isVGPRSpillingEnabled ( * F ) ; bool HasStackObjects = FrameInfo . hasStackObjects ( ) ; if ( HasStackObjects || MaySpill ) PrivateSegmentWaveByteOffset = true ; if ( ST . isAmdCodeObjectV2 ( MF ) ) { if ( HasStackObjects || MaySpill ) PrivateSegmentBuffer = true ; if ( F -> hasFnAttribute ( <STR_LIT> ) ) DispatchPtr = true ; if ( F -> hasFnAttribute ( <STR_LIT> ) ) QueuePtr = true ; if ( F -> hasFnAttribute ( <STR_LIT> ) ) DispatchID = true ; } else if ( ST . isMesaGfxShader ( MF ) ) { if ( HasStackObjects || MaySpill


<s> return <NUM_LIT> ; case CallingConv :: <ISA_LIT>_VS : return <NUM_LIT> ; case CallingConv :: <ISA_LIT>_GS : return <NUM_LIT> ; case CallingConv :: <ISA_LIT>_HS : case CallingConv ::


<s> rtx tmp2 = gen_reg_rtx ( SImode ) ; rtx tmp3 = gen_reg_rtx ( SImode ) ; rtx tmp4 = gen_reg_rtx ( SImode ) ; rtx tmp5 = gen_reg_rtx ( SImode ) ; rtx tmp6 = gen_reg_rtx ( SImode ) ; rtx tmp7 = gen_reg_rtx ( SImode ) ; rtx tmp8 = gen_reg_rtx ( SImode ) ; rtx tmp9 = gen_reg_rtx ( SImode ) ; rtx tmp10 = gen_reg_rtx ( SImode ) ; rtx tmp11 = gen_reg_rtx ( SImode ) ; rtx tmp12 = gen_reg_rtx ( SImode ) ; rtx tmp13 = gen_reg_rtx ( SImode ) ; rtx result_lo = gen_reg_rtx ( SImode ) ; if ( sign ) { emit_insn ( gen_insn_mulhl_su ( tmp0 , op1 , op2 ) ) ; emit_insn ( gen_insn_mulhl_su ( tmp1 , op2 , op1 ) ) ; emit_insn ( gen_insn_mulll_uu ( tmp2 , op1 , op2 ) ) ; emit_insn ( gen_insn_mulhh_ss ( tmp3 , op1 , op2 ) ) ; } else { emit_insn ( gen_insn_mulhl_uu ( tmp0 , op1 , op2 ) ) ; emit_insn ( gen_insn_mulhl_uu ( tmp1 , op2 , op1 ) ) ; emit_insn ( gen_insn_mulll_uu ( tmp2 , op1 , op2 ) ) ; emit_insn ( gen_insn_mulhh_uu ( tmp3 , op1 , op2 ) ) ; } emit_move_insn ( tmp4 , ( gen_rtx_ASHIFT ( SImode , tmp0 , GEN_INT ( <NUM_LIT> ) ) ) ) ; emit_move_insn ( tmp5 , ( gen_rtx_ASHIFT ( SImode , tmp1 , GEN_INT ( <NUM_LIT> ) ) ) ) ; emit_move_insn ( tmp6 , ( gen_rtx_PLUS ( SImode , tmp4 , tmp5


<s> emit_note ( NOTE_INSN_PROLOGUE_END ) ; fnaddr = gen_rtx_MEM ( FUNCTION_MODE , XEXP ( DECL_RTL ( function ) , <NUM_LIT> ) ) ; temp1 = gen_rtx_REG ( Pmode , RISCV_PROLOGUE_TEMP_REGNUM ) ; temp2 = gen_rtx_REG ( Pmode , STATIC_CHAIN_REGNUM ) ; if ( aggregate_value_p ( TREE_TYPE ( TREE_TYPE ( function ) ) , function ) ) this_rtx = gen_rtx_REG ( Pmode , GP_ARG_FIRST + <NUM_LIT> ) ; else this_rtx = gen_rtx_REG ( Pmode , GP_ARG_FIRST ) ; if ( delta != <NUM_LIT> ) { rtx offset = GEN_INT ( delta ) ; if ( ! SMALL_OPERAND ( delta ) ) { riscv_emit_move ( temp1 , offset


<s> void printi32mem ( const MachineInstr * MI , unsigned OpNo ) { O << <STR_LIT> ; printMemReference ( MI , OpNo


<s> } for ( MachineInstr & MI : make_early_inc_range ( mbb_reverse ( MIS ) ) ) { if ( isTriviallyDead ( MI , MRI ) ) { MI . eraseFromParent ( ) ; continue ; } if ( ! select ( MI ) ) return false ; } return true


<s> addPass ( create<ISA_LIT>ISelDag ( get<ISA_LIT>TargetMachine ( ) , getOptLevel ( ) ) ) ; return false


<s> case MOVQ : return <STR_LIT> ; case NOTB : CC_STATUS_INIT ; operands [ <NUM_LIT> ] = GEN_INT ( i ^ <NUM_LIT> ) ; return <STR_LIT> ; case NOTW : CC_STATUS_INIT ; operands [ <NUM_LIT> ] = GEN_INT ( i ^ <NUM_LIT> ) ; return <STR_LIT> ; case


<s> return DAG . getMemcpy ( Chain , dl , Dst , Src , SizeNode , Flags . getByValAlign ( ) , false , true , false , MachinePointerInfo ( ) , MachinePointerInfo (


<s> MVT VT = StoreVal . getSimpleValueType ( ) ; if ( VT . getVectorElementType ( ) == <STR_LIT> && VT . getVectorNumElements ( ) < <NUM_LIT> ) { VT = <STR_LIT> ; StoreVal = DAG . getNode ( <STR_LIT> , DL , VT , DAG . getConstant ( <NUM_LIT> , DL , VT ) , StoreVal , DAG . getIntPtrConstant


<s> OP ( <NUM_LIT> ) = transcode_memory_rtx ( OP ( <NUM_LIT> ) , DE , insn ) ; OP ( <NUM_LIT> ) = transcode_memory_rtx ( OP ( <NUM_LIT> ) , HL , insn ) ; MAYBE_OK ( insn ) ; if ( recog_data . constraints [ <NUM_LIT> ] [ <NUM_LIT> ] == '%' && is_virtual_register ( OP ( <NUM_LIT> ) ) && ! is_virtual_register ( OP ( <NUM_LIT> ) ) && ! CONSTANT_P ( OP ( <NUM_LIT> ) ) ) { rtx tmp = OP ( <NUM_LIT> ) ; OP ( <NUM_LIT> ) = OP ( <NUM_LIT> ) ; OP ( <NUM_LIT> ) = tmp ; } OP ( <NUM_LIT> ) = move_from_acc ( <NUM_LIT> , insn ) ; tmp_id = get_max_insn_count ( ) ; saved_op1 = OP ( <NUM_LIT> ) ; if ( rtx_equal_p ( OP ( <NUM_LIT> ) , OP ( <NUM_LIT> ) ) ) { gcc_assert ( GET_MODE ( OP ( <NUM_LIT> ) ) == QImode ) ; OP ( <NUM_LIT> ) = move_to_x ( <NUM_LIT> , insn ) ; OP ( <NUM_LIT> ) = A ; } else OP ( <NUM_LIT> ) = move_to_acc ( <NUM_LIT> , insn ) ; MAYBE_OK ( insn ) ; if ( tmp_id == get_max_insn_count ( ) ) force_into_acc ( saved_op1 , insn ) ; if ( prev ) first =


<s> void <ISA_LIT>AsmPrinter :: setAndEmitFunctionVirtualRegisters ( const MachineFunction & MF ) { SmallString < <NUM_LIT> > Str ; raw_svector_ostream O ( Str ) ; const TargetRegisterInfo * TRI = MF . getSubtarget ( ) . getRegisterInfo ( ) ; const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; int NumBytes = ( int ) MFI . getStackSize ( ) ; if ( NumBytes ) { O << <STR_LIT> << MFI . getMaxAlign ( ) . value ( ) << <STR_LIT> << DEPOTNAME << getFunctionNumber ( ) << <STR_LIT> << NumBytes << <STR_LIT> ; if ( static_cast < const <ISA_LIT>TargetMachine & > ( MF . getTarget ( ) ) . is64Bit ( ) ) { O << <STR_LIT> ; O << <STR_LIT> ; } else { O <<


<s> Locals . resize ( NumLocals , <STR_LIT>


<s> Num += serialPatternMatch ( * HeadMBB -> succ_begin ( ) ) ; Num += serialPatternMatch ( * std :: next ( HeadMBB -> succ_begin ( ) ) ) ; Num += ifPatternMatch ( HeadMBB ) ; assert ( Num > <NUM_LIT> ) ; break ; } DEBUG ( dbgs ( ) << <STR_LIT> ; ) ; DownBlk = ( DownBlk -> succ_size ( ) == <NUM_LIT> ) ? ( * DownBlk -> succ_begin (


<s> float64x2x3_t temp ; temp . val [ <NUM_LIT> ] = vcombine_f64 ( val . val [ <NUM_LIT> ] , vcreate_f64 ( __AARCH64_UINT64_C ( <NUM_LIT> ) ) ) ; temp . val [ <NUM_LIT> ] = vcombine_f64 ( val . val [ <NUM_LIT> ] , vcreate_f64 ( __AARCH64_UINT64_C ( <NUM_LIT> ) ) ) ; temp . val [ <NUM_LIT> ] = vcombine_f64 ( val . val [ <NUM_LIT> ] , vcreate_f64 ( __AARCH64_UINT64_C ( <NUM_LIT> ) ) ) ; __o = __builtin_aarch64_set_qregciv2df ( __o , ( float64x2_t ) temp . val [ <NUM_LIT> ] ,


<s> SDValue NewDUP ; if ( IsDUPLANE ) NewDUP = DAG . getNode ( N . getOpcode ( ) , dl , NewDUPVT , N . getOperand ( <NUM_LIT> ) , N . getOperand ( <NUM_LIT> ) ) ; else NewDUP = DAG . getNode ( <STR_LIT> , dl , NewDUPVT , N . getOperand ( <NUM_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , dl , NarrowTy , NewDUP , DAG . getConstant ( NumElems , dl


<s> const Constant * mask2 = shaf_us -> getMask ( ) ; Value * op1_1 = shufinstr -> getOperand ( <NUM_LIT> ) ; Value * op1_2 = shaf_us -> getOperand ( <NUM_LIT> ) ; if ( mask1 == mask2


<s> EVT T = Node -> getValueType ( <NUM_LIT> ) ; SDValue negOp = DAG . getNode ( <STR_LIT> , dl , T , DAG . getConstant ( <NUM_LIT> , T ) , Node -> getOperand ( <NUM_LIT> ) ) ; return DAG . getAtomic ( <STR_LIT> , dl , cast < AtomicSDNode > ( Node ) -> getMemoryVT ( ) , Node -> getOperand ( <NUM_LIT> ) , Node -> getOperand ( <NUM_LIT> ) , negOp , cast < AtomicSDNode > ( Node ) -> getSrcValue ( ) , cast < AtomicSDNode

> ( Node ) -> getAlignment ( ) , cast < AtomicSDNode > ( Node ) -> getOrdering ( ) , cast < AtomicSDNode > ( Node ) -> getSynchScope ( ) ) ;


<s> for ( auto T : inst_counter_types ( ) ) if (


<s> return get<ISA_LIT>ArchVersion ( ) == <STR_LIT>


<s> NodeAddr < UseNode * > UN = * I ; NodeAddr < StmtNode * > SN = UN . Addr -> getOwner ( * DFG ) ; MachineInstr * MI = SN . Addr -> getCode ( ) ; const MCInstrDesc & MID = MI -> getDesc ( ) ; if ( ( MID . mayLoad ( ) || MID . mayStore ( ) ) ) { if ( ! hasRepForm ( MI , tfrDefR ) ) { KeepTfr = true ; continue ; } SizeInc ++ ; CanBeReplaced = true ; } else if ( MI -> getOpcode ( ) == <STR_LIT> ) { NodeList AddaslUseList ; DEBUG ( dbgs ( ) << <STR_LIT> << * MI << <STR_LIT> ) ; getAllRealUses ( SN , AddaslUseList ) ; if ( allValidCandidates ( SN , AddaslUseList ) && canRemoveAddasl ( SN , MI , AddaslUseList ) ) { SizeInc += AddaslUseList . size ( ) ; SizeInc -= <NUM_LIT> ; CanBeReplaced =


<s> unsigned Opc ; if ( SrcVT == <STR_LIT> ) { if ( Signed ) Opc = ( DestVT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; else Opc = ( DestVT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; } else { if ( Signed ) Opc = ( DestVT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; else Opc = ( DestVT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; } Register ResultReg = createResultReg ( DestVT == <STR_LIT> ? & <STR_LIT> : & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII

. get ( Opc ) , ResultReg ) . addReg ( SrcReg ) ;


<s> unsigned DemoteRegTo32_ ( unsigned RegIn ) { if ( RegIn ==


<s> static const TargetAsmInfo * createTargetAsmInfo ( const Target & T , const StringRef & TT ) { Triple TheTriple ( TT ) ; switch ( TheTriple . getOS ( ) ) { case Triple :: Darwin : return new <ISA_LIT>DarwinTargetAsmInfo ( TheTriple ) ; case Triple :: MinGW32 : case Triple :: MinGW64 : case Triple :: Cygwin : return new <ISA_LIT>COFFTargetAsmInfo ( TheTriple ) ; case Triple :: Win32 : return new <ISA_LIT>WinTargetAsmInfo ( TheTriple ) ; default : return new <ISA_LIT>ELFTargetAsmInfo ( TheTriple


<s> for ( unsigned i = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i ) DAG . getMachineFunction ( ) . getRegInfo ( ) . addLiveOut ( RVLocs [ i ] . getLocReg ( ) ) ; } SDValue Flag ; for ( unsigned i = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i ) { CCValAssign & VA = RVLocs [ i ] ; assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; Chain = DAG . getCopyToReg ( Chain , dl , VA . getLocReg ( ) , OutVals [ i ] , Flag ) ; Flag = Chain . getValue


<s> if ( MFI -> hasCalls ( ) || ( MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) && MFI -> adjustsStack ( ) ) ) return true ; return MFI -> hasVarSizedObjects ( ) || MFI -> isFrameAddressTaken


<s> DebugLoc dl = CP -> getDebugLoc ( ) ; EVT PtrVT = Op . getValueType ( ) ; SDValue Res ; if ( CP -> isMachineConstantPoolEntry ( ) ) { Res = DAG . getTargetConstantPool ( CP -> getMachineCPVal ( ) , PtrVT , CP -> getAlignment ( ) ) ; } else { Res = DAG . getTargetConstantPool ( CP -> getConstVal ( ) ,


<s> static bool GetCpuIDAndInfo ( unsigned value , unsigned * rEAX , unsigned * rEBX , unsigned * rECX , unsigned * rEDX ) { asm ( <STR_LIT> <STR_LIT> <STR_LIT> : <STR_LIT> ( * rEAX ) , <STR_LIT> ( * rEBX ) , <STR_LIT> ( * rECX ) , <STR_LIT> ( * rEDX ) : <STR_LIT> ( value ) ) ; return false ; int registers [ <NUM_LIT> ] ; __cpuid ( registers , value ) ; * rEAX = registers [ <NUM_LIT> ] ; * rEBX = registers [ <NUM_LIT> ] ; * rECX = registers [ <NUM_LIT> ] ; * rEDX = registers


<s> void <ISA_LIT>CodeEmitter :: emitBasicBlock ( MachineBasicBlock & MBB ) { MCE . StartMachineBasicBlock ( & MBB ) ; for ( MachineBasicBlock :: iterator I = MBB . begin ( ) , E = MBB . end ( ) ; I != E ; ++ I ) { const MachineInstr & MI = * I ; MCE . processDebugLoc ( MI . getDebugLoc ( ) , true ) ; switch ( MI . getOpcode ( ) ) { default : MCE . emitWordLE ( getBinaryCodeForInstr ( * I ) ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case TargetOpcode :: IMPLICIT_DEF : case TargetOpcode :: KILL : break ; } MCE . processDebugLoc ( MI . getDebugLoc (


<s> bool isDef ( long pos ) const { return defs . test


<s> const char * x86DisassemblerGetInstrName ( unsigned Opcode , void * mii ) { const MCInstrInfo * MII = static_cast < const MCInstrInfo * > ( mii ) ; return MII -> getName (


<s> void <ISA_LIT>InstPrinter :: printVectorListFourSpaced ( const MCInst * MI , unsigned OpNum , const MCSubtargetInfo & STI , raw_ostream & O ) { O << <STR_LIT> ; printRegName ( O , MI -> getOperand ( OpNum ) . getReg ( ) ) ; O << <STR_LIT> ; printRegName ( O , MI -> getOperand ( OpNum ) . getReg ( ) + <NUM_LIT> ) ; O << <STR_LIT> ; printRegName ( O , MI -> getOperand ( OpNum ) . getReg ( ) + <NUM_LIT> ) ; O << <STR_LIT> ; printRegName ( O , MI -> getOperand ( OpNum ) . getReg ( ) + <NUM_LIT> ) ; O <<


<s> static char * describe_cache ( unsigned l1_sizekb , unsigned l1_line , unsigned l1_assoc ATTRIBUTE_UNUSED , unsigned l2_sizekb ) { char l1size [ <NUM_LIT> ] , line [ <NUM_LIT> ] , l2size [ <NUM_LIT> ] ; sprintf ( l1size , <STR_LIT> , l1_sizekb ) ; sprintf ( line , <STR_LIT> , l1_line


<s> if ( IsUnscaled ) { int elemOffset = Offset / OffsetStride ; if ( elemOffset > <NUM_LIT> || elemOffset <


<s> void cris_asm_output_ident ( const char


<s> llvm_unreachable ( <STR_LIT> ) ; } <ISA_LIT>TargetELFStreamer * S = new <ISA_LIT>TargetELFStreamer ( ) ; return createELFStreamer ( Ctx , S , MAB , _OS ,


<s> MachineRegisterInfo & MRI = MBB . getParent ( ) -> getRegInfo ( ) ; const TargetRegisterClass * RegClass = MRI . getRegClass ( DestReg ) ; if ( RegClass == & <STR_LIT> || RegClass == & <STR_LIT> || RegClass == & <STR_LIT> || RegClass == & <STR_LIT> ) { BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , DestReg ) . addImm ( Value ) ; return ; } if ( RegClass == & <STR_LIT> || RegClass == & <STR_LIT> || RegClass == & <STR_LIT> ) { BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , DestReg ) . addImm ( Value ) ; return ; } if ( RegClass == & <STR_LIT> ) { BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , DestReg ) . addImm ( Value ) ; return ; } if ( RegClass -> hasSuperClassEq ( & <STR_LIT> ) ) { BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , DestReg ) . addImm ( Value ) ; return ; } unsigned EltSize = <NUM_LIT> ; unsigned Opcode = <STR_LIT> ; if ( RI . isSGPRClass ( RegClass ) ) { if ( RI . getRegSizeInBits ( * RegClass ) > <NUM_LIT> ) { Opcode = <STR_LIT> ; EltSize =


<s> t = build3 ( COND_EXPR , void_type_node , t , u , NULL_TREE ) ; gimplify_and_add ( t , pre_p ) ; t = sav ; if ( sav_ofs ) t = build2 ( PLUS_EXPR , ptr_type_node , sav , size_int ( sav_ofs ) ) ; u = build2 ( POSTINCREMENT_EXPR , TREE_TYPE ( reg ) , reg , size_int ( n_reg ) ) ; u = build1 ( CONVERT_EXPR , integer_type_node , u ) ; u = build2 ( MULT_EXPR , integer_type_node , u , size_int ( sav_scale ) ) ; t = build2 ( PLUS_EXPR , ptr_type_node , t , u ) ; t = build2 ( MODIFY_EXPR , void_type_node , addr , t ) ; gimplify_and_add ( t , pre_p ) ; t = build1 ( GOTO_EXPR , void_type_node , lab_over ) ; gimplify_and_add ( t , pre_p ) ; t = build1 ( LABEL_EXPR , void_type_node , lab_false ) ; append_to_statement_list ( t , pre_p ) ; if ( n_reg > <NUM_LIT> ) { t = build ( MODIFY_EXPR , TREE_TYPE ( reg ) , reg , size_int ( <NUM_LIT> ) ) ; gimplify_and_add ( t , pre_p ) ; } } t = ovf ; if ( align != <NUM_LIT> ) { t = build2 ( PLUS_EXPR , TREE_TYPE ( t ) , t , size_int ( align - <NUM_LIT> ) ) ; t = build2 ( BIT_AND_EXPR , TREE_TYPE ( t ) , t , build_int_cst ( NULL_TREE , - align ) ) ; } gimplify_expr ( & t , pre_p , NULL , is_gimple_val , fb_rvalue ) ; u = build2 ( MODIFY_EXPR , void_type_node , addr , t ) ; gimplify_and_add ( u , pre_p ) ; t = build2 ( PLUS_EXPR , TREE_TYPE ( t ) , t , size_int ( size ) ) ; t = build2 ( MODIFY_EXPR , TREE_TYPE ( ovf ) , ovf , t ) ; gimplify_and_add ( t , pre_p ) ; if ( lab_over ) { t = build1 ( LABEL_EXPR , void_type_node , lab_over


<s> } case 'v' : if ( ( type -> getPrimitiveSizeInBits ( ) == <NUM_LIT> ) && Subtarget . hasAVX512 ( ) ) weight = CW_Register ; LLVM_FALLTHROUGH ; case 'x' : if ( ( ( type -> getPrimitiveSizeInBits ( ) == <NUM_LIT> ) && Subtarget . hasSSE1 ( ) ) || ( ( type -> getPrimitiveSizeInBits ( ) == <NUM_LIT> ) && Subtarget . hasAVX ( ) ) ) weight = CW_Register ; break ; case 'k' : if ( ( type -> getPrimitiveSizeInBits ( ) == <NUM_LIT> ) && Subtarget . hasAVX512 ( ) ) weight = CW_Register ; break ; case 'I' : if ( ConstantInt * C = dyn_cast < ConstantInt > ( info . CallOperandVal ) ) { if ( C -> getZExtValue ( ) <= <NUM_LIT> ) weight = CW_Constant ; } break ; case 'J' : if ( ConstantInt * C = dyn_cast < ConstantInt > ( CallOperandVal ) ) { if ( C -> getZExtValue ( ) <= <NUM_LIT> ) weight = CW_Constant ; } break ; case 'K' : if ( ConstantInt * C = dyn_cast < ConstantInt > ( CallOperandVal ) ) { if ( ( C -> getSExtValue ( ) >= - <NUM_LIT> ) && ( C -> getSExtValue ( ) <= <NUM_LIT> ) ) weight = CW_Constant ; } break ; case 'L' : if ( ConstantInt * C = dyn_cast < ConstantInt > ( CallOperandVal ) ) { if ( ( C -> getZExtValue ( ) == <NUM_LIT> ) || ( C -> getZExtValue ( ) == <NUM_LIT> ) ) weight = CW_Constant ; } break ; case 'M'


<s> return ( IsGlobalInSmallSectionImpl ( GO , TM ) && ( Kind . isData ( ) || Kind . isBSS ( ) || Kind . isCommon


<s> for ( unsigned int regno = <NUM_LIT> ; regno < FIRST_PSEUDO_REGISTER ; regno ++ ) if ( ( LEGACY_SSE_REGNO_P ( regno ) || ( TARGET_64BIT && ( REX_SSE_REGNO_P ( regno ) || ( TARGET_AVX512F && EXT_REX_SSE_REGNO_P ( regno ) ) ) ) ) && ! TEST_HARD_REG_BIT ( need_zeroed_hardregs , regno ) ) return NULL ; return gen_avx_vzeroall (


<s> restoreCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo * TRI ) const { return


<s> return ( __m512i ) __builtin_ia32_pabsb512_mask ( ( __v64qi ) __A , ( __v64qi ) _mm512_setzero_qi ( ) , (


<s> for ( ; i < <NUM_LIT> ; i ++ ) if ( ! ( val & ( ( unsigned HOST_WIDE_INT ) <NUM_LIT> << i ) ) ) return false ; return true


<s> if ( ! TT . isArch32Bit ( ) && ! TT . isArch64Bit ( ) ) llvm_unreachable ( <STR_LIT> ) ; MCSection * Cur = OutStreamer -> getCurrentSectionOnly ( ) ; MCSection * Nt = MMI -> getContext ( ) . getELFSection ( <STR_LIT> , ELF :: SHT_NOTE , ELF :: SHF_ALLOC ) ; OutStreamer -> SwitchSection ( Nt ) ; int WordSize = TT . isArch64Bit ( ) ? <NUM_LIT> : <NUM_LIT> ; EmitAlignment ( WordSize == <NUM_LIT> ? Align ( <NUM_LIT> ) : Align ( <NUM_LIT> ) ) ; OutStreamer -> EmitIntValue ( <NUM_LIT> , <NUM_LIT> ) ; OutStreamer -> EmitIntValue ( <NUM_LIT> + WordSize , <NUM_LIT> ) ; OutStreamer -> EmitIntValue ( ELF :: NT_GNU_PROPERTY_TYPE_0 , <NUM_LIT> ) ; OutStreamer -> EmitBytes ( StringRef ( <STR_LIT> , <NUM_LIT> ) ) ; OutStreamer -> EmitIntValue ( ELF :: GNU_PROPERTY_<ISA_LIT>_FEATURE_1_AND , <NUM_LIT> ) ; OutStreamer -> EmitIntValue ( <NUM_LIT> , <NUM_LIT> ) ; OutStreamer -> EmitIntValue ( FeatureFlagsAnd , <NUM_LIT> ) ; EmitAlignment ( WordSize == <NUM_LIT> ? Align ( <NUM_LIT> ) : Align ( <NUM_LIT> ) ) ; OutStreamer -> endSection ( Nt ) ; OutStreamer -> SwitchSection ( Cur ) ; } } if ( TT . isOSBinFormatMachO ( ) ) OutStreamer -> SwitchSection ( getObjFileLowering ( ) . getTextSection ( ) ) ; if ( TT . isOSBinFormatCOFF ( ) ) { MCSymbol * S = MMI -> getContext ( ) . getOrCreateSymbol ( StringRef ( <STR_LIT> ) ) ; OutStreamer -> BeginCOFFSymbolDef ( S ) ; OutStreamer -> EmitCOFFSymbolStorageClass ( COFF :: IMAGE_SYM_CLASS_STATIC ) ; OutStreamer -> EmitCOFFSymbolType ( COFF :: IMAGE_SYM_DTYPE_NULL ) ; OutStreamer -> EndCOFFSymbolDef ( ) ; int64_t Feat00Flags = <NUM_LIT> ; if ( TT . getArch ( ) == Triple :: x86 ) { Feat00Flags |= <NUM_LIT>


<s> if ( Ps & ConstantProperties :: NaN ) os << <STR_LIT> ; if ( Ps & ConstantProperties :: PosOrZero ) os << <STR_LIT> ; if ( Ps & ConstantProperties :: NegOrZero ) os << <STR_LIT> ; os << '}' ; return ; } os << <STR_LIT> ; if ( isBottom ( ) ) { os << <STR_LIT> ; } else if ( isTop ( ) ) { os << <STR_LIT> ; } else { for ( unsigned i = <NUM_LIT> ; i < size ( ) ; ++ i ) { const Constant * C = Values [ i ] ; if ( i != <NUM_LIT>


<s> MVT BaseVT = MaskVT . getVectorElementType ( ) ; SmallVector < SDValue , <NUM_LIT> > MaskVec ; for ( unsigned i = <NUM_LIT> , e = NumElems / <NUM_LIT> ; i != e


<s> SDValue Value = Mst -> getValue ( ) ; if ( Value . getOpcode ( ) == <STR_LIT> && Value . getNode ( ) -> hasOneUse ( ) && TLI . isTruncStoreLegal ( Value . getOperand ( <NUM_LIT> ) . getValueType ( ) , Mst -> getMemoryVT ( ) ) ) { return DAG . getMaskedStore ( Mst -> getChain ( ) , SDLoc ( N ) , Value . getOperand ( <NUM_LIT> ) , Mst -> getBasePtr ( ) ,

Mask , Mst -> getMemoryVT ( ) , Mst -> getMemOperand ( ) , true ) ;


<s> if ( ( mi -> getOpcode ( ) == <STR_LIT> ) || ( mi -> getOpcode (


<s> for ( const MachineOperand & Op : MI . uses ( ) ) if ( Op . isFI ( ) ) return true ; return


<s> auto isConcatenatedNot = [ ] ( SDValue V ) { V = peekThroughBitcasts ( V ) ; if ( ! isBitwiseNot ( V ) ) return false ; SDValue NotOp = V -> getOperand ( <NUM_LIT> ) ; return peekThroughBitcasts ( NotOp ) . getOpcode ( ) == <STR_LIT> ; } ; if ( isConcatenatedNot ( WideVec . getOperand ( <NUM_LIT> ) ) || isConcatenatedNot ( WideVec . getOperand ( <NUM_LIT> ) ) ) { SDValue Concat = split256IntArith ( WideVec , DAG ) ; return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , VT , DAG . getBitcast ( WideVecVT , Concat ) , N -> getOperand ( <NUM_LIT> ) ) ; } } if ( DCI . isBeforeLegalizeOps ( ) ) return SDValue ( ) ; MVT OpVT = N -> getSimpleValueType ( <NUM_LIT> ) ; SDValue InVec = N -> getOperand ( <NUM_LIT> ) ; unsigned IdxVal = cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; if ( <STR_LIT> ( InVec . getNode ( ) ) ) return getZeroVector ( OpVT , Subtarget , DAG , SDLoc ( N ) ) ; if ( <STR_LIT> ( InVec . getNode ( ) ) ) { if ( OpVT . getScalarType ( ) == <STR_LIT> ) return DAG . getConstant ( <NUM_LIT> , SDLoc ( N ) , OpVT ) ; return getOnesVector ( OpVT , DAG , SDLoc ( N ) ) ; } if ( InVec . getOpcode ( ) == <STR_LIT> ) return DAG . getBuildVector ( OpVT , SDLoc ( N ) , InVec . getNode ( ) -> ops ( ) . slice ( IdxVal , OpVT . getVectorNumElements ( ) ) ) ; if ( IdxVal == <NUM_LIT> && InVec . hasOneUse ( ) ) { unsigned InOpcode = InVec . getOpcode ( ) ; if ( OpVT == <STR_LIT> && InVec . getValueType ( ) == <STR_LIT> ) { if ( InOpcode == <STR_LIT> && InVec . getOperand ( <NUM_LIT> ) . getValueType ( ) == <STR_LIT> ) { return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , OpVT , InVec . getOperand ( <NUM_LIT> ) ) ; } if ( InOpcode == <STR_LIT> && InVec . getOperand ( <NUM_LIT> ) . getValueType ( ) == <STR_LIT> ) { return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , OpVT , InVec . getOperand ( <NUM_LIT> ) ) ; } } if ( ( InOpcode == <STR_LIT> || InOpcode == <STR_LIT> ) && OpVT . is128BitVector ( ) && InVec . getOperand ( <NUM_LIT> ) . getSimpleValueType ( ) . is128BitVector ( ) ) { unsigned ExtOp = InOpcode == <STR_LIT>


<s> unsigned getNumUserSGPRs ( ) const { return


<s> RegisterTarget < Triple :: systemz , true > X ( getThe<ISA_LIT>Target ( ) , <STR_LIT> ,


<s> bool MachineConstEvaluator :: evaluateCOPY ( const RegisterSubReg & R1 , const CellMap & Inputs , LatticeCell & Result ) { return getCell ( R1 , Inputs ,


<s> bool hasAddr64 ( ) const { return ( getGeneration ( ) < VOLCANIC_ISLANDS


<s> if ( <STR_LIT> . hasSubClassEq ( RC ) ) return load ? <STR_LIT> : <STR_LIT> ; if ( <STR_LIT> . hasSubClassEq ( RC ) ) return load ? ( HasAVX512 ? <STR_LIT> : HasAVX ? <STR_LIT> : <STR_LIT> ) : ( HasAVX512 ? <STR_LIT> : HasAVX ? <STR_LIT> : <STR_LIT> ) ; if ( <STR_LIT> . hasSubClassEq ( RC ) ) return load ? <STR_LIT> : <STR_LIT> ; if ( <STR_LIT> . hasSubClassEq ( RC ) ) { assert ( STI . hasBWI ( ) && <STR_LIT> ) ; return load ? <STR_LIT> : <STR_LIT> ; } llvm_unreachable ( <STR_LIT> ) ; case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) return load ? <STR_LIT> : <STR_LIT> ; if ( <STR_LIT> . hasSubClassEq ( RC ) ) return load ? ( HasAVX512 ? <STR_LIT> : HasAVX ? <STR_LIT> : <STR_LIT> ) : ( HasAVX512 ? <STR_LIT> : HasAVX ? <STR_LIT> : <STR_LIT> ) ; if ( <STR_LIT> . hasSubClassEq ( RC ) ) return load ? <STR_LIT> : <STR_LIT> ; if ( <STR_LIT> . hasSubClassEq ( RC ) ) return load ? <STR_LIT> : <STR_LIT> ; if ( <STR_LIT> . hasSubClassEq ( RC ) ) { assert ( STI . hasBWI ( ) && <STR_LIT> ) ; return load ? <STR_LIT> : <STR_LIT> ; } llvm_unreachable ( <STR_LIT> ) ; case <NUM_LIT> : assert ( <STR_LIT> . hasSubClassEq ( RC ) && <STR_LIT> ) ; return load ? <STR_LIT> : <STR_LIT> ; case <NUM_LIT> : { if ( <STR_LIT> . hasSubClassEq ( RC ) ) { if ( isStackAligned ) return load ? ( HasVLX ? <STR_LIT> : HasAVX512 ? <STR_LIT> : HasAVX ? <STR_LIT> : <STR_LIT> ) : ( HasVLX ? <STR_LIT> : HasAVX512 ? <STR_LIT> : HasAVX ? <STR_LIT> : <STR_LIT> ) ; else return load ? ( HasVLX ? <STR_LIT> : HasAVX512 ? <STR_LIT> : HasAVX ? <STR_LIT> : <STR_LIT> ) : ( HasVLX ? <STR_LIT> : HasAVX512 ? <STR_LIT> : HasAVX ? <STR_LIT> : <STR_LIT> ) ; } if ( <STR_LIT> . hasSubClassEq ( RC ) ) { if ( STI . is64Bit ( ) ) return load ? <STR_LIT> : <STR_LIT> ; else return load ? <STR_LIT> : <STR_LIT> ; } llvm_unreachable ( <STR_LIT> ) ; } case <NUM_LIT> : assert ( <STR_LIT> . hasSubClassEq ( RC ) && <STR_LIT> ) ; if ( isStackAligned ) return load ? ( HasVLX ? <STR_LIT> : HasAVX512 ? <STR_LIT> : <STR_LIT> ) : ( HasVLX ? <STR_LIT> : HasAVX512 ? <STR_LIT> : <STR_LIT> ) ; else return load ? ( HasVLX ? <STR_LIT> : HasAVX512 ? <STR_LIT> : <STR_LIT> ) : ( HasVLX ? <STR_LIT> : HasAVX512 ? <STR_LIT> : <STR_LIT> ) ; case <NUM_LIT> : assert ( <STR_LIT> . hasSubClassEq ( RC )


<s> <STR_LIT> llvm :: getInstrPredicate ( const MachineInstr * MI , unsigned & PredReg ) { int PIdx = MI -> findFirstPredOperandIdx ( ) ; if ( PIdx == - <NUM_LIT> ) { PredReg = <NUM_LIT> ; return <STR_LIT> ; } PredReg = MI -> getOperand ( PIdx + <NUM_LIT> ) .


<s> else if ( GET_CODE ( XEXP ( op , <NUM_LIT> ) ) == VEC_SELECT ) return rtx_is_swappable_p ( XEXP ( op , <NUM_LIT> ) , special ) ; else return <NUM_LIT> ; case VEC_SELECT : if ( REG_P ( XEXP ( op , <NUM_LIT> ) ) && GET_MODE_INNER ( GET_MODE ( XEXP ( op , <NUM_LIT> ) ) ) == GET_MODE ( op ) && GET_CODE ( ( parallel = XEXP ( op , <NUM_LIT> ) ) ) == PARALLEL && XVECLEN ( parallel , <NUM_LIT> ) == <NUM_LIT> && CONST_INT_P ( XVECEXP ( parallel , <NUM_LIT> , <NUM_LIT> ) ) ) { * special = SH_EXTRACT ; return <NUM_LIT> ; } else if ( GET_CODE ( XEXP ( op , <NUM_LIT> ) ) == VEC_CONCAT && ( GET_MODE ( XEXP ( op , <NUM_LIT> ) ) == V4DFmode || GET_MODE ( XEXP ( op , <NUM_LIT> ) ) == V4DImode ) && GET_CODE ( ( parallel = XEXP ( op , <NUM_LIT> ) ) ) == PARALLEL && XVECLEN ( parallel , <NUM_LIT> ) == <NUM_LIT> && CONST_INT_P ( XVECEXP ( parallel , <NUM_LIT> , <NUM_LIT> ) ) && CONST_INT_P ( XVECEXP ( parallel , <NUM_LIT> , <NUM_LIT> ) ) ) { * special = SH_XXPERMDI ; return <NUM_LIT> ; } else if ( v2df_reduction_p ( op ) ) return <NUM_LIT> ; else return <NUM_LIT> ; case UNSPEC : { int val = XINT ( op , <NUM_LIT> ) ; switch ( val ) { default : break ; case UNSPEC_VBPERMQ : case UNSPEC_VMRGH_DIRECT : case UNSPEC_VMRGL_DIRECT : case UNSPEC_VPACK_SIGN_SIGN_SAT : case UNSPEC_VPACK_SIGN_UNS_SAT : case UNSPEC_VPACK_UNS_UNS_MOD : case UNSPEC_VPACK_UNS_UNS_MOD_DIRECT : case UNSPEC_VPACK_UNS_UNS_SAT : case UNSPEC_VPERM : case UNSPEC_VPERM_UNS : case UNSPEC_VPERMHI : case UNSPEC_VPERMSI : case UNSPEC_VPERMXOR : case UNSPEC_VPKPX : case UNSPEC_VSLDOI : case UNSPEC_VSLO : case UNSPEC_VSRO : case UNSPEC_VSUM2SWS : case UNSPEC_VSUM4S : case UNSPEC_VSUM4UBS : case UNSPEC_VSUMSWS : case UNSPEC_VSUMSWS_DIRECT : case UNSPEC_VSX_CONCAT : case UNSPEC_VSX_CVDPSPN : case UNSPEC_VSX_CVSPDP : case UNSPEC_VSX_CVSPDPN : case UNSPEC_VSX_EXTRACT : case UNSPEC_VSX_SET : case UNSPEC_VSX_SLDWI : case UNSPEC_VSX_VSLO : case UNSPEC_VUNPACK_HI_SIGN : case UNSPEC_VUNPACK_HI_SIGN_DIRECT : case UNSPEC_VUNPACK_LO_SIGN


<s> assert ( ShAmt . getValueType ( ) == <STR_LIT> && <STR_LIT> ) ; if ( isa < ConstantSDNode > ( ShAmt ) ) { switch ( Opc ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return DAG . getNode ( Opc , dl , VT , SrcOp , ShAmt ) ; } } switch ( Opc ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; } SDValue ShOps [ <NUM_LIT> ] ; ShOps [ <NUM_LIT> ] = ShAmt ; ShOps [ <NUM_LIT> ] = DAG . getConstant ( <NUM_LIT> ,


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { SDValue Elt0 = DAG . getNode ( <STR_LIT> , SL , EltVT , Vec . getOperand ( <NUM_LIT> ) , Idx ) ; SDValue Elt1 = DAG . getNode ( <STR_LIT> , SL , EltVT , Vec . getOperand ( <NUM_LIT> ) , Idx ) ; DCI . AddToWorklist ( Elt0 . getNode ( ) ) ; DCI . AddToWorklist ( Elt1 . getNode ( ) ) ; return DAG . getNode ( Opc , SL , EltVT , Elt0 , Elt1 , Vec -> getFlags ( ) ) ; } } } if ( ! DCI . isBeforeLegalize ( ) ) return SDValue ( ) ; unsigned VecSize = VecVT . getSizeInBits ( ) ; unsigned EltSize = EltVT . getSizeInBits ( ) ; auto * Idx = dyn_cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ; if ( isa < MemSDNode > ( Vec ) && EltSize <= <NUM_LIT> && EltVT . isByteSized ( ) && VecSize > <NUM_LIT> && VecSize % <NUM_LIT> == <NUM_LIT> && Idx ) { EVT NewVT = getEquivalentMemType ( * DAG . getContext (


<s> const MCInstrDesc & Desc = MCII . get ( MI . getOpcode ( ) ) ; unsigned bytes = Desc . getSize ( ) ; for ( unsigned i = <NUM_LIT> ; i < bytes ; i ++ ) { OS . write ( ( uint8_t ) ( ( Encoding >> ( <NUM_LIT> * i ) ) & <NUM_LIT> ) ) ; } if ( bytes > <NUM_LIT> ) return ; for ( unsigned i = <NUM_LIT> , e = MI . getNumOperands ( ) ; i < e ; ++ i ) { if ( ! isSrcOperand ( Desc , i ) ) continue ; int RCID = Desc . OpInfo [ i ] . RegClass ; const MCRegisterClass & RC = MRI . getRegClass ( RCID ) ; const MCOperand & Op = MI . getOperand ( i ) ; if ( getLitEncoding ( Op , RC . getSize ( ) ) != <NUM_LIT> ) continue ; int64_t Imm = <NUM_LIT> ; if ( Op . isImm ( ) ) Imm = Op . getImm ( ) ; else if ( Op . isExpr ( ) ) { if ( const MCConstantExpr * C = dyn_cast < MCConstantExpr > ( Op . getExpr ( ) ) ) Imm = C -> getValue ( ) ; } else if ( ! Op . isExpr ( )


<s> TargetLoweringBase :: AtomicRMWExpansionKind <ISA_LIT>TargetLowering :: shouldExpandAtomicRMWInIR ( AtomicRMWInst * AI ) const { unsigned NativeWidth = Subtarget -> is64Bit ( ) ? <NUM_LIT> : <NUM_LIT> ; Type * MemType = AI -> getType ( ) ; if ( MemType -> getPrimitiveSizeInBits ( ) > NativeWidth ) { return needsCmpXchgNb ( MemType ) ? AtomicRMWExpansionKind :: CmpXChg : AtomicRMWExpansionKind :: None ; } AtomicRMWInst :: BinOp Op = AI -> getOperation ( ) ; switch ( Op ) { default : llvm_unreachable ( <STR_LIT> ) ; case AtomicRMWInst :: Xchg : case AtomicRMWInst :: Add : case AtomicRMWInst ::


<s> if ( DontExpandCondPseudos16 ) return BB ; const TargetInstrInfo * TII = getTargetMachine ( ) . getInstrInfo ( ) ; unsigned CC = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned regX = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; int64_t Imm = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned SltOpc = <ISA_LIT>16WhichOp8uOr16simm ( SltiOpc


<s> for ( SmallVector < MachineInstr * , <NUM_LIT> > :: iterator si = StackStores . begin ( ) , se = StackStores . end ( ) ; si != se ; ++ si ) { MachineInstr * Store = * si ; unsigned Opc = Store -> getOpcode ( ) ; MachineBasicBlock & MBB = * Ret -> getParent ( ) ; int FI = Store -> getOperand ( <NUM_LIT> ) . getIndex ( ) ; if ( ZeroedLocations . count ( FI ) ) continue ; ZeroedLocations . insert ( FI ) ; if ( Opc == <STR_LIT> ) { MachineInstrBuilder MIB ( F , Ret ) ; BuildMI ( MBB , Ret , Ret -> getDebugLoc ( ) , InstrInfo -> get ( <STR_LIT> ) ) . addReg ( <STR_LIT> ) . addFrameIndex ( FI ) . addImm ( Store -> getOperand ( <NUM_LIT> ) . getImm ( ) ) . addMemOperand ( InstrInfo -> GetMemOperand ( MBB , FI , MachineMemOperand :: MOStore ) ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; } else { BuildMI ( MBB , Ret , Ret -> getDebugLoc ( ) , InstrInfo -> get ( Opc ) ) . addReg ( <STR_LIT> ) . addFrameIndex ( FI ) . addImm ( Store -> getOperand ( <NUM_LIT> ) . getImm ( ) ) . addMemOperand ( InstrInfo -> GetMemOperand ( MBB , FI , MachineMemOperand :: MOStore ) ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> )


<s> if ( NumOps == <NUM_LIT> ) return false ; switch ( Info -> get ( Inst . getOpcode ( ) )

. OpInfo [ NumOps - <NUM_LIT> ] . OperandType ) {


<s> int FrameIndex = StoreByValRegs ( CCInfo , DAG , dl , Chain , nullptr , CCInfo . getInRegsParamsCount ( ) , CCInfo . getNextStackOffset

( ) , std :: max ( <NUM_LIT> , TotalArgRegsSaveSize ) ) ;


<s> default : return None ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Sign *= - <NUM_LIT> ; LLVM_FALLTHROUGH ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { if ( ! MI . getOperand ( <NUM_LIT> ) . isReg ( ) || ! MI . getOperand ( <NUM_LIT> ) . isReg ( ) || ! MI . getOperand

( <NUM_LIT> ) . isImm ( ) ) return None ;


<s> if ( immed ) { if ( INTVAL ( operands [ <NUM_LIT> ] ) == <NUM_LIT> ) sprintf ( result , <STR_LIT> , op , ( TARGET_DENSITY && ( code == EQ || code == NE ) ) ? <STR_LIT> : <STR_LIT> ) ; else sprintf ( result , <STR_LIT> , op ) ; } else sprintf ( result , <STR_LIT> , op ) ; return result


<s> const MCSection * AMDGPUMCAsmInfo :: getNonexecutableStackSection ( MCContext & CTX )


<s> if ( * insn_ptr && r10k_needs_protection_p_1 ( x , * insn_ptr ) )


<s> unsigned Imm = ( unsigned ) ~ ( CI -> getSExtValue ( ) ) ; bool UseImm = isThumb2 ? ( <STR_LIT> ( Imm ) != - <NUM_LIT> ) : ( <STR_LIT> ( Imm ) != - <NUM_LIT> ) ; if ( UseImm ) { unsigned Opc = isThumb2 ? <STR_LIT> : <STR_LIT> ; const TargetRegisterClass * RC = isThumb2 ? & <STR_LIT> : & <STR_LIT> ; unsigned ImmReg = createResultReg ( RC ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , ImmReg ) . addImm ( Imm ) ) ; return ImmReg ; } } unsigned ResultReg = <NUM_LIT> ; if ( Subtarget -> useMovt ( ) ) ResultReg = fastEmit_i ( VT , VT , <STR_LIT> , CI -> getZExtValue ( ) ) ; if ( ResultReg ) return ResultReg ; if ( VT != <STR_LIT> ) return <NUM_LIT> ; unsigned Align = DL . getPrefTypeAlignment ( C -> getType ( ) ) ; if ( Align == <NUM_LIT> ) { Align = DL . getTypeAllocSize ( C -> getType ( ) ) ; } unsigned Idx = MCP . getConstantPoolIndex ( C , Align ) ; ResultReg = createResultReg ( TLI . getRegClassFor ( VT ) ) ; if ( isThumb2 ) AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , ResultReg ) . addConstantPoolIndex ( Idx ) ) ; else { ResultReg = constrainOperandRegClass ( TII . get ( <STR_LIT> ) , ResultReg , <NUM_LIT> ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , ResultReg ) . addConstantPoolIndex ( Idx )


<s> SDValue AMDGPUTargetLowering :: Lower<ISA_LIT>GN_EXTEND_INREG ( SDValue Op , SelectionDAG & DAG ) const { EVT ExtraVT = cast < VTSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getVT ( ) ; MVT VT = Op . getSimpleValueType ( ) ; MVT ScalarVT = VT . getScalarType ( ) ; if ( ! VT . isVector ( ) ) return SDValue ( ) ; SDValue Src = Op . getOperand ( <NUM_LIT> ) ; SDLoc DL ( Op ) ; unsigned NElts = VT . getVectorNumElements ( ) ; SmallVector < SDValue , <NUM_LIT> > Args ; DAG . ExtractVectorElements ( Src , Args , <NUM_LIT> , NElts ) ; SDValue VTOp = DAG . getValueType ( ExtraVT . getScalarType ( ) ) ; for ( unsigned I = <NUM_LIT> ; I < NElts ; ++ I ) Args [ I ] = DAG . getNode ( <STR_LIT> , DL , ScalarVT , Args [ I ] , VTOp ) ; return DAG . getNode ( <STR_LIT> , DL


<s> else size = int_size_in_bytes ( type ) ; if ( TARGET_32BIT ) return ( size + <NUM_LIT> ) >> <NUM_LIT> ; else return ( size + <NUM_LIT>


<s> bool <ISA_LIT>PassConfig :: addPreEmitPass ( ) { PM -> add ( create<ISA_LIT>FPMoverPass ( get<ISA_LIT>TargetMachine ( ) ) ) ; PM -> add ( create<ISA_LIT>DelaySlotFillerPass ( get<ISA_LIT>TargetMachine ( ) ) ) ; return


<s> if ( TT . isOSBinFormatMachO ( ) ) return <STR_LIT> ; if ( LittleEndian ) return <STR_LIT> ; return <STR_LIT>


<s> unsigned RegNo = getRegPair ( ) ; Inst . addOperand ( MCOperand :: createReg ( RegNo ++


<s> if ( VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> ) return Op ; return getZeroVector ( VT , Subtarget , DAG , DL ) ; } if ( Subtarget . hasSSE2 ( ) && <STR_LIT> ( Op .


<s> <ISA_LIT>SelectionDAGInfo ( const <ISA_LIT>TargetMachine & TM ) : TargetSelectionDAGInfo ( TM


<s> if ( HiddenArgNumBytes >= <NUM_LIT> ) { if ( Func . getParent ( ) -> getNamedMetadata ( <STR_LIT> ) ) emitKernelArg ( DL , Int8PtrTy , <STR_LIT> , Offset , Args ) ; else emitKernelArg ( DL , Int8PtrTy , <STR_LIT> , Offset , Args ) ; } if ( HiddenArgNumBytes >= <NUM_LIT> ) { if ( Func . hasFnAttribute ( <STR_LIT> ) ) { emitKernelArg ( DL , Int8PtrTy , <STR_LIT> , Offset , Args ) ; emitKernelArg ( DL , Int8PtrTy , <STR_LIT> , Offset , Args ) ; } else { emitKernelArg ( DL , Int8PtrTy , <STR_LIT> , Offset , Args ) ; emitKernelArg ( DL , Int8PtrTy , <STR_LIT> ,


<s> return DecodeCPURegsRegisterClass ( Inst , RegNo , Address ,


<s> bool <ISA_LIT>TargetLowering :: CanLowerReturn ( CallingConv :: ID , MachineFunction & , bool , const SmallVectorImpl < <STR_LIT> > & Outs , LLVMContext


<s> if ( SUJ -> Succs [ i ] . getSUnit ( ) != SUI ) { continue ; } SDep Dep = SUJ -> Succs [ i ] ; SDep :: Kind DepType = Dep . getKind ( ) ; unsigned DepReg = <NUM_LIT> ; if ( DepType != SDep :: Order ) { DepReg = Dep . getReg ( ) ; } if ( ( MCIDI . isCall ( ) || MCIDI . isReturn ( ) ) && DepType == SDep :: Order ) { } else if ( isDirectJump ( I ) && ! MCIDJ . isBranch ( ) && ! MCIDJ . isCall ( ) && ( DepType == SDep :: Order ) ) { } else if ( MCIDI . isConditionalBranch ( ) && ( DepType != SDep :: Data ) && ( DepType != SDep :: Output ) ) { } else if ( DepType == SDep :: Output && DepReg != <STR_LIT> ) { FoundSequentialDependence = true ; } else if ( DepType == SDep :: Order && Dep . isArtificial ( ) ) { } else if ( DepType != SDep :: Anti ) { FoundSequentialDependence = true ; } } if (


<s> return new <ISA_LIT>ToTHMStub ( m_pData , m_Size , fixup_begin ( )


<s> cmp_bytes = bytes_to_compare ; if ( extra_bytes < offset ) { offset -= extra_bytes ; cmp_bytes = load_mode_size ; bytes_to_compare = cmp_bytes ; } } else cmp_bytes = bytes_to_compare ; rtx offset_rtx ; if ( BYTES_BIG_ENDIAN || TARGET_AVOID_XFORM ) offset_rtx = GEN_INT ( offset ) ; else { offset_rtx = gen_reg_rtx ( Pmode ) ; emit_move_insn ( offset_rtx , GEN_INT ( offset ) ) ; } rtx addr1 = gen_rtx_PLUS ( Pmode , src1_addr , offset_rtx ) ; rtx addr2 = gen_rtx_PLUS ( Pmode , src2_addr , offset_rtx ) ; do_load_for_compare_from_addr ( load_mode , tmp_reg_src1 , addr1 , orig_src1 ) ; do_load_for_compare_from_addr ( load_mode , tmp_reg_src2 , addr2 , orig_src2 ) ; unsigned HOST_WIDE_INT remain = bytes_to_compare - cmp_bytes ; if ( load_mode_size != <NUM_LIT> ) { if ( load_mode_size < word_mode_size ) { rtx sh = GEN_INT ( BITS_PER_UNIT * ( word_mode_size - load_mode_size ) ) ; do_rotl3 ( tmp_reg_src1 , tmp_reg_src1 , sh ) ; do_rotl3 ( tmp_reg_src2 , tmp_reg_src2 , sh ) ; } if ( cmp_bytes < word_mode_size ) { HOST_WIDE_INT mb = BITS_PER_UNIT * ( word_mode_size - cmp_bytes ) ; rtx mask = GEN_INT ( HOST_WIDE_INT_M1U << mb ) ; do_and3 ( tmp_reg_src1 , tmp_reg_src1 , mask ) ; do_and3 ( tmp_reg_src2 , tmp_reg_src2 , mask ) ; } } rtx dst_label ; if ( remain > <NUM_LIT> || equality_compare_rest ) { if ( ! cleanup_label ) cleanup_label = gen_label_rtx ( ) ; dst_label = cleanup_label ; } else dst_label = final_move_label ; if ( load_mode_size == <NUM_LIT> ) { if ( equality_compare_rest ) { rtx lab_ref = gen_rtx_LABEL_REF ( VOIDmode , final_move_label ) ; rtx cond = gen_reg_rtx ( CCmode


<s> assert ( Outs . size ( ) <= <NUM_LIT> && <STR_LIT> ) ; break ; } MachineFunction & MF = DAG . getMachineFunction ( ) ; <ISA_LIT>MachineFunctionInfo * MFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; <ISA_LIT>ParamManager & PM = MFI -> getParamManager ( ) ; SDValue Flag ; const <ISA_LIT>Subtarget & ST = getTargetMachine ( ) . getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( ST . useParamSpaceForDeviceArgs ( ) ) { assert ( Outs . size ( ) < <NUM_LIT> && <STR_LIT> ) ; if ( Outs . size ( ) == <NUM_LIT> ) { unsigned ParamSize = OutVals [ <NUM_LIT> ] . getValueType ( ) . getSizeInBits ( ) ; unsigned Param = PM . addReturnParam ( ParamSize ) ; const std :: string & ParamName = PM . getParamName ( Param ) ; SDValue ParamValue = DAG . getTargetExternalSymbol ( ParamName . c_str ( ) , <STR_LIT> ) ; Chain = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Chain , ParamValue , OutVals [ <NUM_LIT> ] ) ; } } else { for ( unsigned i = <NUM_LIT> , e = Outs . size ( ) ; i != e ; ++ i ) { EVT RegVT = Outs [ i ] . VT ; TargetRegisterClass * TRC = <NUM_LIT> ; if ( RegVT == <STR_LIT> ) { TRC = <STR_LIT> ; } else if ( RegVT == <STR_LIT> ) { TRC = <STR_LIT> ; } else if ( RegVT == <STR_LIT> ) { TRC = <STR_LIT> ; } else if ( RegVT == <STR_LIT> ) { TRC = <STR_LIT> ; } else if ( RegVT == <STR_LIT> ) { TRC = <STR_LIT> ; } else if ( RegVT == <STR_LIT> ) { TRC = <STR_LIT> ; } else { llvm_unreachable ( <STR_LIT> ) ; } unsigned Reg = MF . getRegInfo ( ) . createVirtualRegister ( TRC ) ; SDValue Copy = DAG . getCopyToReg ( Chain , dl , Reg , OutVals [ i ] ) ; SDValue OutReg = DAG . getRegister ( Reg , RegVT ) ; Chain = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Copy , OutReg ) ; MFI -> addRetReg ( Reg ) ; } } if ( Flag . getNode ( ) == <NUM_LIT> ) { return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> ,


<s> static CodeModel :: Model getEffectiveCodeModel ( Optional < CodeModel :: Model > CM ) { if ( ! CM . hasValue ( ) ) return CodeModel :: Small ; return CM . getValue ( )


<s> BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addImm ( PTLI -> GetTmpOffsetForFI ( FI , <NUM_LIT> ) ) . addExternalSymbol ( tmpName ) . addImm ( <NUM_LIT> ) ; } else if ( RC == <STR_LIT> ) { unsigned opcode = ( DestReg == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; BuildMI ( MBB , I , DL , get ( opcode ) , DestReg ) . addImm ( PTLI -> GetTmpOffsetForFI ( FI , <NUM_LIT> ) ) . addExternalSymbol ( tmpName ) . addImm ( <NUM_LIT> ) ; } else assert ( <NUM_LIT> && <STR_LIT>


<s> MachineBasicBlock * canonicalize ( MachineBasicBlock * MBB ) { MachineLoop * InnerLoop = MLI . getLoopFor ( MBB ) ; if ( InnerLoop == Loop ) { return MBB ; } else { if ( ! LoopBlocks . count ( MBB ) ) { return nullptr ; } assert ( InnerLoop


<s> if ( isShuffleEquivalent ( Mask , Unpckl , V1 , V2 ) ) return DAG . getNode ( <STR_LIT> , DL , VT , V1 , V2 ) ; SmallVector < int , <NUM_LIT> > Unpckh ; createUnpackShuffleMask ( VT , Unpckh , false , false ) ; if ( isShuffleEquivalent ( Mask , Unpckh , V1 , V2 ) ) return DAG . getNode ( <STR_LIT> , DL , VT ,


<s> const TargetRegisterClass * RegClass = CSI [ i ] . getRegClass ( ) ; if ( RegClass == & <STR_LIT> ) loadRegFromStackSlot ( MBB , MI , Reg , CSI [ i ] . getFrameIdx ( ) , RegClass ) ; } unsigned LowReg = MFI -> getLowReg ( ) , HighReg = MFI -> getHighReg ( ) ; unsigned StartOffset = RegSpillOffsets [ LowReg ] ; if ( StartOffset ) { MachineInstrBuilder MIB = BuildMI ( MBB , MI , DL , get ( ( LowReg == HighReg ? <STR_LIT> : <STR_LIT> ) ) ) ; MIB . addReg ( LowReg , RegState :: Define ) ; if ( LowReg != HighReg ) MIB . addReg


<s> return false ; } if ( Start -> getOpcode ( ) == <STR_LIT> && ( BBUtils -> getOffsetOf ( Start ) > BBUtils -> getOffsetOf ( Start -> getOperand ( <NUM_LIT> ) . getMBB ( ) ) || ! BBUtils -> isBBInRange ( Start , Start -> getOperand ( <NUM_LIT> ) . getMBB ( ) , <NUM_LIT> ) ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } return true ; } ; auto FindStartInsertionPoint = [ ] ( MachineInstr * Start , MachineInstr * Dec , MachineBasicBlock :: iterator & InsertPt , MachineBasicBlock * & InsertBB , ReachingDefAnalysis & RDA , InstSet & ToRemove ) { if ( Start -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) { InsertPt = MachineBasicBlock :: iterator ( Start ) ; InsertBB = Start -> getParent ( ) ; return true ; } Register CountReg = Start -> getOperand ( <NUM_LIT> ) . getReg ( ) ; auto IsMoveLR = [ & CountReg ] ( MachineInstr * MI ) { return MI -> getOpcode ( ) == <STR_LIT> && MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> && MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == CountReg && MI -> getOperand ( <NUM_LIT> ) . getImm ( ) == <STR_LIT> ; } ; if ( auto * LRDef = RDA . getUniqueReachingMIDef ( Start , MCRegister :: from ( <STR_LIT> ) ) ) { if ( IsMoveLR ( LRDef ) && RDA . hasSameReachingDef ( Start , LRDef , CountReg . asMCReg ( ) ) ) { SmallPtrSet < MachineInstr * , <NUM_LIT> > Ignore = { Dec } ; if ( ! TryRemove ( LRDef , RDA , ToRemove , Ignore ) ) return false ; InsertPt = MachineBasicBlock :: iterator ( Start ) ; InsertBB = Start -> getParent ( ) ; return true ; } } MachineBasicBlock * MBB = Start -> getParent ( ) ; if ( auto * LRDef = RDA . getLocalLiveOutMIDef ( MBB , MCRegister :: from ( <STR_LIT> ) ) ) { if ( IsMoveLR ( LRDef ) && RDA . hasSameReachingDef ( Start , LRDef , CountReg ) ) { SmallPtrSet < MachineInstr * , <NUM_LIT> > Ignore = { Start , Dec } ; if ( ! TryRemove ( LRDef , RDA , ToRemove , Ignore ) ) return false ; InsertPt = MachineBasicBlock :: iterator ( LRDef ) ; InsertBB = LRDef -> getParent ( ) ; return true ; } } if ( ! RDA . isSafeToDefRegAt ( Start , MCRegister :: from ( <STR_LIT> ) ) ) return false ; InsertPt = MachineBasicBlock :: iterator ( Start ) ; InsertBB = Start -> getParent


<s> bool hasFCPSGN ( ) const { return HasFCPSGN


<s> OutStreamer . EmitRawText ( StringRef ( <STR_LIT> ) ) ; EmitAlignment ( F -> getAlignment ( ) , F ) ; EmitFunctionBodyStart ( ) ; EmitFunctionHeader ( ) ; MachineFunction :: const_iterator MBB ; for ( MBB = MF . begin ( ) ; MBB != MF . end ( ) ; ++ MBB ) { OutStreamer . EmitRawText ( NewLine ) ; printMBBInfo ( MBB ) ; if ( MBB != MF . begin (


<s> if ( TARGET_HARD_FLOAT_ABI && TARGET_VFP ) size += <NUM_LIT> ; if ( TARGET_IWMMXT_ABI ) size += <NUM_LIT> ; } return size


<s> if ( MI -> getDesc ( ) . mayLoad ( ) || MI -> getDesc ( ) . mayStore ( ) ) { switch ( getAddrMode ( MI ) ) { case <STR_LIT> : NonExtOpcode = <STR_LIT> ( MI ->


<s> <ISA_LIT>AsmParser ( MCSubtargetInfo & sti , MCAsmParser & parser , const MCInstrInfo & MII ) : MCTargetAsmParser ( ) , STI ( sti ) , Parser ( parser ) , hasConsumedDollar ( false ) { setAvailableFeatures ( ComputeAvailableFeatures ( STI . getFeatureBits ( ) )


<s> const struct d_target_info_spec handlers [ ] = { { <STR_LIT> , pa_d_handle_target_float_abi } , { <STR_LIT> , pa_d_handle_target_object_format } , { NULL , NULL }


<s> vtrnq_s32 ( int32x4_t a , int32x4_t b ) { return ( int32x4x2_t ) { vtrn1q_s32 ( a , b ) , vtrn2q_s32 ( a , b


<s> virtual void getAnalysisUsage ( AnalysisUsage &


<s> initialize<ISA_LIT>VSXFMAMutatePass ( * PassRegistry :: getPassRegistry ( ) ) ; insertPass ( VSXFMAMutateEarly ? & RegisterCoalescerID : & MachineSchedulerID , & <ISA_LIT>VSXFMAMutateID ) ; if ( get<ISA_LIT>TargetMachine ( ) . getRelocationModel ( ) == Reloc :: PIC_ ) addPass ( create<ISA_LIT>TLSDynamicCallPass


<s> memset ( ( char * ) & ultra_pipe , <NUM_LIT>


<s> bool slowLEA ( ) const { return SlowLEA


<s> const MCRegisterInfo * MRI = MMI . getContext ( ) . getRegisterInfo ( ) ; const TargetInstrInfo & TII = * MF . getTarget ( ) . getInstrInfo ( ) ; const std :: vector < CalleeSavedInfo > & CSI = MFI -> getCalleeSavedInfo ( ) ; if ( CSI . empty ( ) ) return ; for ( std :: vector < CalleeSavedInfo > :: const_iterator I = CSI . begin ( ) , E = CSI . end ( ) ; I != E ; ++ I ) { int64_t Offset = MFI -> getObjectOffset (


<s> MemIntrinsicSDNode * M = cast < MemIntrinsicSDNode > ( N ) ; MachineMemOperand * MMO = M -> getMemOperand ( ) ; if ( ConstantSDNode * ConstOffset = dyn_cast < ConstantSDNode > ( BaseOffset ) ) { glueCopyToM0 ( N , CurDAG -> getTargetConstant ( - <NUM_LIT> , SL , <STR_LIT> ) ) ; ImmOffset = ConstOffset -> getZExtValue ( ) + <NUM_LIT> ; } else { if ( CurDAG -> isBaseWithConstantOffset ( BaseOffset ) ) { ImmOffset = BaseOffset . getConstantOperandVal ( <NUM_LIT> ) ; BaseOffset = BaseOffset . getOperand ( <NUM_LIT> ) ; } SDNode * SGPROffset = CurDAG -> getMachineNode ( <STR_LIT> , SL , <STR_LIT> , BaseOffset ) ; SDNode * M0Base = CurDAG -> getMachineNode ( <STR_LIT> , SL , <STR_LIT> , SDValue ( SGPROffset , <NUM_LIT> ) , CurDAG -> getTargetConstant ( <NUM_LIT> , SL , <STR_LIT> ) ) ; glueCopyToM0 ( N , SDValue ( M0Base , <NUM_LIT> ) ) ; } SDValue V0 ; SDValue Chain = N -> getOperand ( <NUM_LIT> ) ; SDValue Glue ; if ( HasVSrc ) { SDValue VSrc0 = N -> getOperand ( <NUM_LIT> ) ; V0 = CurDAG -> getRegister ( <STR_LIT> , <STR_LIT> ) ; SDValue CopyToV0 = CurDAG -> getCopyToReg ( N -> getOperand ( <NUM_LIT> ) , SL , V0 , VSrc0 , N -> getOperand ( N -> getNumOperands ( ) - <NUM_LIT> ) ) ; Chain = CopyToV0 ; Glue = CopyToV0 . getValue ( <NUM_LIT> ) ; } SDValue OffsetField = CurDAG -> getTargetConstant ( ImmOffset , SL , <STR_LIT> ) ; SDValue GDS = CurDAG -> getTargetConstant ( <NUM_LIT> , SL , <STR_LIT> ) ; const unsigned Opc = gwsIntrinToOpcode ( IntrID ) ; SmallVector < SDValue , <NUM_LIT> > Ops


<s> unsigned imm = fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned shift = fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) ; shift <<= <NUM_LIT> ; switch ( Inst . getOpcode ( ) ) { default : return Fail ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( shift & ( <NUM_LIT> << <NUM_LIT> ) ) return Fail ; DecodeGPR32RegisterClass ( Inst , Rd , Addr , Decoder ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : DecodeGPR64RegisterClass ( Inst , Rd , Addr , Decoder ) ; break ; } if ( Inst . getOpcode ( ) == <STR_LIT> || Inst . getOpcode ( ) == <STR_LIT> ) Inst . addOperand ( Inst . getOperand (


<s> for ( new = imports_list ; new ; new = new -> next ) if ( new -> name == name ) return ; new = ( struct import * ) xmalloc ( sizeof ( struct import ) ) ; new -> next = imports_list ; imports_list = new ; new -> name


<s> virtual bool addPassesToEmitMC ( PassManagerBase & , MCContext * & , raw_ostream & , bool =


<s> void <ISA_LIT>HazardRecognizer970 :: Reset ( ) { LastWasBL8_ELF = false ; EndDispatchGroup (


<s> if ( offset == <NUM_LIT> ) return <NUM_LIT> ; if ( offset > <NUM_LIT> && offset <= sh_max_mov_insn_displacement ( mode , false ) ) return ( mode == HImode || mode == QImode ) ? <NUM_LIT> : <NUM_LIT> ; if ( TARGET_SH2A && offset > <NUM_LIT> && offset <= sh_max_mov_insn_displacement ( mode , true ) ) return <NUM_LIT> ; return <NUM_LIT> ; } if ( GET_CODE ( x ) == PLUS && ! CONSTANT_P ( XEXP ( x , <NUM_LIT> ) ) && ! TARGET_SHMEDIA ) return <NUM_LIT> ; return <NUM_LIT>


<s> void LLVMInitializePowerPCTarget ( ) { RegisterTargetMachine < <ISA_LIT>32TargetMachine > A (


<s> if ( N -> getMachineOpcode ( ) != <STR_LIT> ) continue ; if ( N -> getConstantOperandVal ( <NUM_LIT> ) != <NUM_LIT> || N -> getConstantOperandVal ( <NUM_LIT> ) != <NUM_LIT> ) continue ; SDValue ISR = N -> getOperand ( <NUM_LIT> ) ; if ( ! ISR . isMachineOpcode ( ) || ISR . getMachineOpcode ( ) != TargetOpcode :: INSERT_SUBREG ) continue ; if ( ! ISR . hasOneUse ( ) ) continue ; if ( ISR . getConstantOperandVal ( <NUM_LIT> ) != <STR_LIT> ) continue ; SDValue IDef = ISR . getOperand ( <NUM_LIT> ) ; if ( ! IDef . isMachineOpcode ( ) || IDef . getMachineOpcode ( ) != TargetOpcode :: IMPLICIT_DEF ) continue ; SDValue Op32 = ISR -> getOperand ( <NUM_LIT> ) ; if ( ! Op32 . isMachineOpcode ( ) ) continue ; SmallPtrSet < SDNode * , <NUM_LIT> > ToPromote ; if ( ! Peephole<ISA_LIT>64ZExtGather ( Op32 , ToPromote ) ) continue ; bool OutsideUse = false ; for ( SDNode * PN : ToPromote ) { for ( SDNode * UN : PN -> uses ( ) ) { if ( ! ToPromote . count ( UN ) && UN != ISR . getNode ( ) ) { OutsideUse = true ; break ; } } if ( OutsideUse ) break ; } if ( OutsideUse ) continue ; MadeChange = true ; for ( SDNode * PN : ToPromote ) { unsigned NewOpcode ; switch ( PN -> getMachineOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : NewOpcode = <STR_LIT> ; break ; case <STR_LIT> : NewOpcode = <STR_LIT> ; break ; case <STR_LIT> : NewOpcode = <STR_LIT> ; break ; case <STR_LIT> : NewOpcode = <STR_LIT> ; break ; case <STR_LIT> : NewOpcode = <STR_LIT> ; break ; case <STR_LIT> : NewOpcode = <STR_LIT> ; break ; case <STR_LIT> : NewOpcode = <STR_LIT> ; break ; case <STR_LIT> : NewOpcode = <STR_LIT> ; break ; case <STR_LIT> : NewOpcode = <STR_LIT> ; break ; case <STR_LIT> : NewOpcode = <STR_LIT> ; break ; case <STR_LIT> : NewOpcode = <STR_LIT> ; break ; case <STR_LIT> : NewOpcode = <STR_LIT>


<s> BB -> addSuccessor ( copy0MBB ) ; BB -> addSuccessor ( sinkMBB ) ; unsigned Opc = <STR_LIT> ( ( <STR_LIT> ) MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; BuildMI ( BB , DL , TII -> get ( Opc ) ) . addMBB ( sinkMBB ) ; copy0MBB -> addSuccessor ( sinkMBB ) ; BuildMI ( * sinkMBB , sinkMBB -> begin ( ) , DL , TII -> get ( <STR_LIT> ) , MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addMBB ( copy0MBB ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addMBB ( thisMBB ) ; MI -> eraseFromParent ( ) ; return


<s> return ( COMMUTATIVE_P ( x ) && ( TARGET_NO_SPACE_REGS || ( outer_code != UNKNOWN && outer_code != MEM ) || GET_CODE


<s> if ( Op . getOpcode ( ) != <STR_LIT> ) return false ; unsigned NumElements = Op . getNumOperands ( ) ; SDValue Element = Op . getOperand ( <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i < NumElements ; ++ i ) if ( Op . getOperand ( i ) != Element ) return false ; El = Element ; return


<s> SDValue Extract = DAG . getNode ( <STR_LIT> , dl , EltVT , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; SDValue Assert = DAG . getNode ( <STR_LIT> , dl , EltVT , Extract , DAG . getValueType ( VT ) ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Assert ) ; } else if ( VT . getSizeInBits ( ) == <NUM_LIT> ) { unsigned Idx = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; if ( Idx == <NUM_LIT> ) return Op ; int Mask [ <NUM_LIT> ] = { static_cast < int > ( Idx ) , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> } ; EVT VVT = Op . getOperand ( <NUM_LIT> ) . getValueType ( ) ; SDValue Vec = DAG . getVectorShuffle ( VVT , dl , Op . getOperand ( <NUM_LIT> ) , DAG . getUNDEF ( VVT ) , Mask ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Vec , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; } else if ( VT . getSizeInBits ( ) == <NUM_LIT> ) { unsigned Idx = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; if ( Idx == <NUM_LIT> ) return Op ; int Mask [ <NUM_LIT> ] = { <NUM_LIT> , - <NUM_LIT> } ; EVT VVT = Op . getOperand ( <NUM_LIT> ) . getValueType ( ) ; SDValue Vec = DAG . getVectorShuffle ( VVT , dl , Op . getOperand ( <NUM_LIT> ) , DAG . getUNDEF ( VVT ) , Mask ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Vec , DAG


<s> int NumUse = <NUM_LIT> ; for ( auto & Use : MRI . use_nodbg_operands ( VReg ) ) { auto & UseInst = * Use . getParent ( ) ; if ( UseInst . getParent ( ) != DefBB || UseInst . isPHI ( ) ) return true ; if ( ++ NumUse > MaxUseScan ) return true ; } if ( NumUse == <NUM_LIT> ) return false ; const int MaxInstScan = <NUM_LIT> ; int NumInst = <NUM_LIT> ; for ( auto I = std :: next ( DefMI . getIterator


<s> uint64_t <ISA_LIT>FrameLowering :: calculateMaxStackAlign ( const MachineFunction & MF ) const { const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; uint64_t MaxAlign = MFI


<s> return createMachObjectWriter ( OS , true , object :: mach :: CTM_x86_64 , object ::


<s> offset = INTVAL ( XEXP ( x , <NUM_LIT> ) ) ; } else if ( SYMBOL_REF_P ( x ) ) sym = x ; else if ( CONST_INT_P ( x ) ) offset = INTVAL ( x ) ; else if ( GET_CODE ( x ) == LABEL_REF ) offset = <NUM_LIT> ; else return false ; unsigned align = <NUM_LIT> ; if ( sym ) { tree decl = SYMBOL_REF_DECL ( sym ) ; if ( TARGET_MACHO && flag_pic && ! machopic_offs_p ) return false ; if ( MACHO_SYMBOL_INDIRECTION_P ( sym ) ) ; else if ( decl && DECL_ALIGN ( decl ) ) align = DECL_ALIGN_UNIT ( decl ) ; } unsigned int extra = <NUM_LIT> ; switch ( mode ) { case E_DFmode : case E_DDmode : case E_DImode : if ( VECTOR_MEM_VSX_P ( mode ) ) return false ; if ( ! TARGET_POWERPC64 ) extra = <NUM_LIT> ; else if ( ( offset & <NUM_LIT> ) || ( align & <NUM_LIT> ) ) return false ; break ; case E_TFmode : case E_IFmode : case E_KFmode : case E_TDmode : case E_TImode : case E_PTImode


<s> return ( strncmp ( DLL_IMPORT_PREFIX , symbol , strlen (


<s> SDValue Ptr ; unsigned Align ; bool isSEXTLoad = false ; if ( LoadSDNode * LD = dyn_cast < LoadSDNode > ( N ) ) { Ptr = LD -> getBasePtr ( ) ; VT = LD -> getMemoryVT ( ) ; Align = LD -> getAlignment ( ) ; isSEXTLoad = LD -> getExtensionType ( ) == <STR_LIT> ; } else if ( StoreSDNode * ST = dyn_cast < StoreSDNode > ( N ) ) { Ptr = ST -> getBasePtr ( ) ; VT = ST -> getMemoryVT ( ) ; Align = ST -> getAlignment ( ) ; } else return false ; bool isInc ; bool isLegal = false ; if ( VT . isVector ( ) ) isLegal = Subtarget -> hasMVEIntegerOps ( ) && getMVEIndexedAddressParts ( Ptr . getNode ( ) , VT , Align , isSEXTLoad , Subtarget -> isLittle (


<s> SDLoc dl ( N ) ; int64_t Imm = cast < ConstantSDNode > ( N ) ->


<s> unsigned <ISA_LIT>RegisterInfo :: getPtrSizedStackRegister ( const MachineFunction & MF ) const { const <ISA_LIT>Subtarget & Subtarget = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; unsigned StackReg = getStackRegister


<s> BuildMI ( BB , DL , TII -> get ( TargetOpcode :: COPY ) , tmpSPVReg ) . addReg ( physSPReg ) ; BuildMI ( BB , DL , TII -> get ( Is64Bit ? <STR_LIT> : <STR_LIT> ) , SPLimitVReg ) . addReg ( tmpSPVReg ) . addReg ( sizeVReg ) ; BuildMI ( BB , DL , TII -> get ( Is64Bit ? <STR_LIT> : <STR_LIT> ) ) . addReg ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) . addImm ( TlsOffset ) . addReg ( TlsReg ) . addReg ( SPLimitVReg ) ; BuildMI ( BB , DL , TII -> get ( <STR_LIT> ) ) . addMBB ( mallocMBB ) ; BuildMI ( bumpMBB , DL , TII -> get ( TargetOpcode :: COPY ) , physSPReg ) . addReg ( SPLimitVReg ) ; BuildMI ( bumpMBB , DL , TII -> get ( TargetOpcode :: COPY ) , bumpSPPtrVReg ) . addReg ( SPLimitVReg ) ; BuildMI ( bumpMBB , DL , TII -> get ( <STR_LIT> ) ) . addMBB ( continueMBB ) ; const uint32_t * RegMask = getTargetMachine ( ) . getRegisterInfo ( ) -> getCallPreservedMask ( CallingConv :: C ) ; if ( Is64Bit ) { BuildMI ( mallocMBB , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( sizeVReg ) ; BuildMI ( mallocMBB , DL , TII -> get ( <STR_LIT> ) ) . addExternalSymbol ( <STR_LIT> ) . addRegMask ( RegMask ) . addReg ( <STR_LIT> , RegState :: Implicit ) . addReg ( <STR_LIT> , RegState :: ImplicitDefine ) ; } else { BuildMI ( mallocMBB , DL , TII -> get ( <STR_LIT> ) , physSPReg ) . addReg ( physSPReg ) . addImm ( <NUM_LIT> ) ; BuildMI ( mallocMBB , DL , TII -> get ( <STR_LIT> ) ) . addReg ( sizeVReg ) ; BuildMI ( mallocMBB , DL , TII -> get ( <STR_LIT> ) ) . addExternalSymbol ( <STR_LIT> ) . addRegMask ( RegMask ) . addReg ( <STR_LIT> , RegState :: ImplicitDefine ) ; } if ( ! Is64Bit ) BuildMI ( mallocMBB , DL , TII -> get ( <STR_LIT> ) , physSPReg ) . addReg ( physSPReg ) . addImm ( <NUM_LIT> ) ; BuildMI ( mallocMBB , DL , TII -> get ( TargetOpcode :: COPY ) , mallocPtrVReg ) . addReg ( Is64Bit ? <STR_LIT> : <STR_LIT> ) ; BuildMI ( mallocMBB , DL , TII -> get ( <STR_LIT> ) ) . addMBB ( continueMBB ) ; BB -> addSuccessor ( bumpMBB ) ; BB -> addSuccessor ( mallocMBB ) ; mallocMBB -> addSuccessor (


<s> CallInst * DispatchPtr = Builder . CreateCall ( DispatchPtrFn , { } ) ; DispatchPtr -> addAttribute ( AttributeList :: ReturnIndex , Attribute :: NoAlias ) ; DispatchPtr -> addAttribute ( AttributeList :: ReturnIndex , Attribute :: NonNull ) ; DispatchPtr -> addDereferenceableAttr ( AttributeList :: ReturnIndex , <NUM_LIT> ) ; Type * I32Ty = Type :: getInt32Ty ( Mod -> getContext ( ) ) ; Value * CastDispatchPtr = Builder . CreateBitCast ( DispatchPtr , PointerType :: get ( I32Ty , AS . CONSTANT_ADDRESS ) ) ; Value * GEPXY = Builder . CreateConstInBoundsGEP1_64 ( CastDispatchPtr , <NUM_LIT> ) ; LoadInst * LoadXY = Builder . CreateAlignedLoad ( GEPXY , <NUM_LIT> ) ; Value * GEPZU = Builder . CreateConstInBoundsGEP1_64 ( CastDispatchPtr , <NUM_LIT> ) ; LoadInst * LoadZU = Builder . CreateAlignedLoad ( GEPZU , <NUM_LIT> ) ; MDNode * MD = MDNode :: get ( Mod ->


<s> <ISA_LIT>Bid ( unsigned B ) { Bid = B ? MAX /


<s> SMLoc ExtLoc = Parser . getTok ( ) . getLoc ( ) ; Lex ( ) ; bool EnableFeature = true ; if ( Name . startswith_lower ( <STR_LIT> ) ) { EnableFeature = false ; Name = Name . substr ( <NUM_LIT> ) ; } unsigned FeatureKind = <STR_LIT> ( Name ) ; if ( FeatureKind == <STR_LIT> ) { Error ( ExtLoc , <STR_LIT> + Name ) ; return false ; } for ( const auto & Extension : Extensions ) { if ( Extension . Kind != FeatureKind ) continue ; if ( Extension . Features . none ( ) ) { Error ( ExtLoc , <STR_LIT> + Name ) ; return false ; } if ( ( getAvailableFeatures ( ) & Extension . ArchCheck ) != Extension . ArchCheck ) { Error ( ExtLoc , <STR_LIT> + Name + <STR_LIT> <STR_LIT> ) ; return false ; } MCSubtargetInfo & STI =


<s> for ( i = <NUM_LIT> ; i < num_ops ; i ++ ) { if ( ! can_create_pseudo ) x = riscv_emit_set ( temp , x ) ; else x = force_reg ( mode , x ) ; codes [ i ] . value = trunc_int_for_mode ( codes [ i ] . value , mode ) ; x = gen_rtx_fmt_ee ( codes [ i ] . code , mode , x , GEN_INT ( codes [ i ] . value ) ) ; } } riscv_emit_set ( dest ,


<s> Register OldReg = MO . getReg ( ) ; if ( MO . isDef ( ) ) { assert ( MI . isInlineAsm ( ) ) ; unsigned LocalId = getLocalId ( Reg2Local , MFI , CurLocal , OldReg ) ; MI . untieRegOperand ( MI . getOperandNo ( & MO ) ) ; MO . ChangeToImmediate ( LocalId ) ; continue ; } if ( MFI . isVRegStackified ( OldReg ) ) { InsertPt = findStartOfTree ( MO , MRI , MFI ) ; continue ; } if ( MI . isInlineAsm ( ) ) { unsigned LocalId = getLocalId ( Reg2Local , MFI , CurLocal , OldReg ) ; MI . untieRegOperand ( MI . getOperandNo ( & MO ) ) ; MO . ChangeToImmediate ( LocalId ) ; continue ; } unsigned LocalId = getLocalId ( Reg2Local , MFI , CurLocal , OldReg ) ; const TargetRegisterClass * RC = MRI . getRegClass ( OldReg ) ; Register NewReg = MRI . createVirtualRegister ( RC ) ; unsigned Opc = getLocalGetOpcode ( RC ) ; InsertPt = BuildMI ( MBB , InsertPt , MI . getDebugLoc ( ) , TII -> get ( Opc ) , NewReg ) . addImm ( LocalId ) ; MO . setReg ( NewReg ) ; MFI . stackifyVReg ( NewReg ) ; Changed = true ; } if ( <STR_LIT> ( MI . getOpcode ( ) ) ) { MRI . replaceRegWith ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) , MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; MI . eraseFromParent ( ) ; Changed = true ; } } } MFI . setNumLocals ( CurLocal - MFI . getParams ( ) . size ( ) ) ; for ( unsigned I = <NUM_LIT> , E = MRI . getNumVirtRegs ( ) ; I < E ; ++ I ) { unsigned Reg = Register :: index2VirtReg ( I ) ; auto RL = Reg2Local . find ( Reg ) ; if ( RL == Reg2Local . end ( ) || RL -> second < MFI . getParams ( ) . size ( ) ) continue ; MFI . setLocal ( RL -> second - MFI . getParams ( ) . size ( ) , typeForRegClass ( MRI . getRegClass ( Reg ) ) ) ; Changed = true ; } for ( const MachineBasicBlock & MBB : MF ) { for ( const MachineInstr & MI : MBB ) { if ( MI . isDebugInstr ( ) || MI . isLabel ( ) ) continue ; for ( const MachineOperand & MO : MI . explicit_operands ( ) ) { assert ( ( ! MO . isReg ( ) || MRI . use_empty ( MO . getReg ( ) ) || MFI . isVRegStackified ( MO . getReg ( ) )


<s> } else { assert ( VA . isMemLoc ( ) ) ; unsigned ObjSize = VA . getLocVT ( ) . getSizeInBits ( ) / <NUM_LIT> ; if ( ObjSize > StackSlotSize ) { cerr << <STR_LIT> << VA . getLocVT ( ) . getSimpleVT ( ) << <STR_LIT> ; } int FI = MFI -> CreateFixedObject ( ObjSize , LRSaveSize + VA . getLocMemOffset ( ) ) ; SDValue FIN = DAG . getFrameIndex ( FI , <STR_LIT> ) ; ArgValues . push_back ( DAG . getLoad ( VA . getLocVT ( ) , dl , Root , FIN , NULL , <NUM_LIT> ) ) ; } } if ( isVarArg ) { static const unsigned ArgRegs [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; <ISA_LIT>FunctionInfo * XFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; unsigned FirstVAReg = CCInfo . getFirstUnallocated ( ArgRegs , array_lengthof ( ArgRegs ) ) ; if ( FirstVAReg < array_lengthof ( ArgRegs ) ) { SmallVector < SDValue , <NUM_LIT> > MemOps ; int offset = <NUM_LIT> ; for ( unsigned i = array_lengthof ( ArgRegs ) - <NUM_LIT> ; i >= FirstVAReg ; -- i ) { int FI = MFI -> CreateFixedObject ( <NUM_LIT> , offset ) ; if ( i == FirstVAReg ) { XFI -> setVarArgsFrameIndex ( FI ) ; } offset -= StackSlotSize ; SDValue FIN = DAG . getFrameIndex ( FI , <STR_LIT> ) ; unsigned VReg = RegInfo . createVirtualRegister ( <STR_LIT> ) ; RegInfo . addLiveIn ( ArgRegs [ i ] , VReg ) ; SDValue Val = DAG . getCopyFromReg ( Root , dl , VReg


<s> BuildMI ( & MBB , DL , get ( BOpc ) ) . addMBB ( TBB ) ; } else if ( isEndLoopN ( Cond [ <NUM_LIT> ] . getImm ( ) ) ) { int EndLoopOp = Cond [ <NUM_LIT> ] . getImm ( ) ; assert ( Cond [ <NUM_LIT> ] . isMBB ( ) ) ; SmallPtrSet < MachineBasicBlock * , <NUM_LIT> > VisitedBBs ; MachineInstr * Loop = findLoopInstr ( TBB , EndLoopOp , VisitedBBs ) ; assert ( Loop != <NUM_LIT> && <STR_LIT> ) ; Loop -> getOperand ( <NUM_LIT> ) . setMBB ( TBB ) ; BuildMI ( & MBB , DL , get ( EndLoopOp ) ) . addMBB ( TBB ) ; } else if ( isNewValueJump ( Cond [ <NUM_LIT> ] . getImm ( ) ) ) { assert ( ( Cond . size ( ) == <NUM_LIT> ) && <STR_LIT> ) ; unsigned Flags1 = getUndefRegState ( Cond [ <NUM_LIT> ] . isUndef ( ) ) ; DEBUG ( dbgs ( ) << <STR_LIT> << MBB . getNumber ( ) ; ) ; if ( Cond [ <NUM_LIT> ] . isReg ( ) ) { unsigned Flags2 = getUndefRegState ( Cond [ <NUM_LIT> ] . isUndef ( ) ) ; BuildMI ( & MBB , DL , get ( BccOpc ) ) . addReg ( Cond [ <NUM_LIT> ] . getReg ( ) , Flags1 ) . addReg ( Cond [ <NUM_LIT> ] . getReg ( ) , Flags2 ) . addMBB ( TBB ) ; } else if ( Cond [ <NUM_LIT> ] . isImm ( ) ) { BuildMI ( & MBB , DL , get ( BccOpc ) ) . addReg ( Cond [ <NUM_LIT> ] . getReg ( ) , Flags1 ) . addImm ( Cond

[ <NUM_LIT> ] . getImm ( ) ) . addMBB ( TBB ) ;


<s> case <STR_LIT> : return lowerBITCAST ( Op , DAG ) ; case <STR_LIT> : return lowerVASTART ( Op , DAG ) ; case <STR_LIT> : return lowerVACOPY ( Op , DAG ) ; case <STR_LIT> : return lowerDYNAMIC_STACKALLOC ( Op , DAG ) ; case <STR_LIT> : return lowerGET_DYNAMIC_AREA_OFFSET ( Op , DAG ) ; case <STR_LIT> : return lowerSMUL_LOHI ( Op , DAG ) ; case <STR_LIT> : return lowerUMUL_LOHI ( Op , DAG ) ; case <STR_LIT> : return lowerSDIVREM ( Op , DAG ) ; case <STR_LIT> : return lowerUDIVREM ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return lowerXALUO ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return lowerADDSUBCARRY ( Op , DAG ) ; case <STR_LIT> : return lowerOR ( Op , DAG ) ; case <STR_LIT> : return lowerCTPOP ( Op , DAG ) ; case <STR_LIT> : return lowerATOMIC_FENCE ( Op , DAG ) ; case <STR_LIT> : return lowerATOMIC_LOAD_OP ( Op , DAG , <STR_LIT> ) ; case <STR_LIT> : return lowerATOMIC_STORE ( Op , DAG ) ; case <STR_LIT> : return lowerATOMIC_LOAD ( Op , DAG ) ; case <STR_LIT> : return lowerATOMIC_LOAD_OP ( Op , DAG , <STR_LIT> ) ; case <STR_LIT> : return lowerATOMIC_LOAD_SUB ( Op , DAG ) ; case <STR_LIT> : return lowerATOMIC_LOAD_OP ( Op , DAG , <STR_LIT> ) ; case <STR_LIT> : return lowerATOMIC_LOAD_OP ( Op , DAG , <STR_LIT> ) ; case <STR_LIT> : return lowerATOMIC_LOAD_OP ( Op , DAG , <STR_LIT> ) ; case <STR_LIT> : return lowerATOMIC_LOAD_OP ( Op , DAG , <STR_LIT> ) ; case <STR_LIT> : return lowerATOMIC_LOAD_OP ( Op , DAG , <STR_LIT> ) ; case <STR_LIT> : return lowerATOMIC_LOAD_OP ( Op , DAG , <STR_LIT> ) ; case <STR_LIT> : return lowerATOMIC_LOAD_OP ( Op , DAG , <STR_LIT> ) ; case <STR_LIT> : return lowerATOMIC_LOAD_OP ( Op , DAG , <STR_LIT> ) ; case <STR_LIT> : return lowerATOMIC_CMP_SWAP ( Op , DAG ) ; case


<s> const <ISA_LIT>RegisterInfo & <ISA_LIT>InstrInfo :: getRegisterInfo ( ) const { return


<s> <ISA_LIT>Subtarget & <ISA_LIT>Subtarget :: initializeSubtargetDependencies ( StringRef CPU , StringRef FS ) { std :: string CPUName =


<s> case <STR_LIT> : if ( <ISA_LIT>ScalarSSEf64 ) Opc = HasAVX512 ? <STR_LIT> : HasAVX ? <STR_LIT> : <STR_LIT> ; else Opc = <STR_LIT> ; break ; case <STR_LIT> : return <NUM_LIT> ; } Align Alignment = DL . getPrefTypeAlign ( CFP -> getType ( ) ) ; unsigned PICBase = <NUM_LIT> ; unsigned char OpFlag = Subtarget -> classifyLocalReference ( nullptr ) ; if ( OpFlag == <STR_LIT> ) PICBase = getInstrInfo ( ) -> getGlobalBaseReg ( FuncInfo . MF ) ; else if ( OpFlag == <STR_LIT> ) PICBase = getInstrInfo ( ) -> getGlobalBaseReg ( FuncInfo . MF ) ; else if ( Subtarget -> is64Bit ( ) && TM . getCodeModel ( ) == CodeModel :: Small ) PICBase = <STR_LIT> ; unsigned CPI = MCP . getConstantPoolIndex ( CFP , Alignment ) ; Register ResultReg = createResultReg ( TLI . getRegClassFor ( VT . SimpleTy ) ) ; if ( Subtarget -> is64Bit ( ) && CM == CodeModel :: Large ) { Register AddrReg = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , AddrReg ) . addConstantPoolIndex ( CPI , <NUM_LIT> , OpFlag ) ; MachineInstrBuilder MIB = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc ,


<s> bool matchAsmImpl ( StringRef s , ArrayRef < const StringRef * > args ) { s = s . substr ( s . find_first_not_of ( <STR_LIT> ) ) ; for ( unsigned i = <NUM_LIT> , e = args . size ( ) ; i != e ; ++ i ) { StringRef piece ( * args [ i ] ) ; if ( ! s . startswith ( piece ) ) return false ; s = s . substr ( piece . size ( ) ) ; StringRef :: size_type pos = s . find_first_not_of ( <STR_LIT> ) ; if ( pos == <NUM_LIT> ) return false ; s = s . substr ( pos


<s> if ( SDValue Flags = combineCarryThroughADD ( N -> getOperand ( <NUM_LIT> ) , DAG ) ) { MVT VT = N -> getSimpleValueType ( <NUM_LIT> ) ; SDVTList VTs = DAG . getVTList ( VT , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , VTs , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , Flags ) ; } return SDValue ( )


<s> if ( TREE_CODE ( type ) == REAL_TYPE && TYPE_PRECISION ( type ) == <NUM_LIT> ) return <STR_LIT> ; if ( TYPE_NAME ( type ) != NULL ) { const char * res = <STR_LIT> (


<s> int NumBytes = ( int ) MFI -> getStackSize ( ) ; unsigned FramePtr = RegInfo -> getFrameRegister ( MF ) ; if ( MF . getFunction ( ) -> getCallingConv ( ) == CallingConv :: GHC ) return ; MachineBasicBlock :: iterator MBBI = MBB . getFirstTerminator ( ) ; DebugLoc dl = MBBI != MBB . end ( ) ? MBBI -> getDebugLoc ( ) : DebugLoc ( ) ; if ( ! AFI -> hasStackFrame ( ) ) { if ( NumBytes - ArgRegsSaveSize != <NUM_LIT> ) emitSPUpdate ( is<ISA_LIT> , MBB , MBBI , dl , TII , NumBytes - ArgRegsSaveSize ) ; } else { const MCPhysReg * CSRegs = RegInfo -> getCalleeSavedRegs ( & MF ) ; if ( MBBI != MBB . begin ( ) ) { do { -- MBBI ; } while ( MBBI != MBB . begin ( ) && isCSRestore ( MBBI , TII , CSRegs ) ) ; if ( ! isCSRestore ( MBBI , TII , CSRegs ) ) ++ MBBI ; } NumBytes -= ( ArgRegsSaveSize + AFI -> getGPRCalleeSavedArea1Size ( ) + AFI -> getGPRCalleeSavedArea2Size ( ) + AFI -> getDPRCalleeSavedGapSize ( ) + AFI -> getDPRCalleeSavedAreaSize ( ) ) ; if ( AFI -> shouldRestoreSPFromFP (


<s> if ( MOI . getOrdering ( ) == AtomicOrdering :: Release || MOI . getOrdering ( ) == AtomicOrdering :: AcquireRelease || MOI . getOrdering ( ) == AtomicOrdering :: SequentiallyConsistent || MOI . getFailureOrdering ( ) == AtomicOrdering :: SequentiallyConsistent ) Changed |= CC -> insertRelease ( MI , MOI . getScope ( ) , MOI . getOrderingAddrSpace ( ) , MOI . getIsCrossAddressSpaceOrdering ( ) , Position :: BEFORE ) ; if ( MOI . getOrdering ( ) == AtomicOrdering :: Acquire || MOI . getOrdering ( ) == AtomicOrdering :: AcquireRelease || MOI . getOrdering ( ) == AtomicOrdering :: SequentiallyConsistent || MOI . getFailureOrdering ( ) == AtomicOrdering :: Acquire || MOI . getFailureOrdering ( ) == AtomicOrdering :: SequentiallyConsistent ) { Changed |= CC -> insertWait ( MI , MOI . getScope ( ) , MOI . getOrderingAddrSpace ( ) , isAtomicRet ( * MI ) ? <STR_LIT> : <STR_LIT> , MOI . getIsCrossAddressSpaceOrdering ( ) , Position :: AFTER


<s> bool <ISA_LIT>LegalizerInfo :: loadInputValue ( Register DstReg , MachineIRBuilder & B , <STR_LIT> ArgType ) const { const <ISA_LIT>MachineFunctionInfo * MFI = B . getMF ( ) . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; const ArgDescriptor * Arg ; const TargetRegisterClass * ArgRC ; LLT ArgTy ; std :: tie ( Arg , ArgRC , ArgTy ) = MFI -> getPreloadedValue ( ArgType ) ; if ( ! Arg ) { assert ( ArgType == <STR_LIT> ) ; B . buildConstant ( DstReg ,


<s> rmap_ty :: iterator iter = RegisterMap . find ( Name . str ( ) ) ; if ( iter != RegisterMap . end ( ) ) return iter -> second ; else return


<s> if ( Offset > <NUM_LIT> ) { unsigned AddOpc = <STR_LIT> , SubOpc = <STR_LIT> ; int AddOffset = Offset - <NUM_LIT> + <NUM_LIT> ; if ( ( Offset - <NUM_LIT> + <NUM_LIT> ) > <NUM_LIT> ) { AddOpc = <STR_LIT> ; SubOpc = <STR_LIT> ; AddOffset = - AddOffset ; } BuildMI ( MBB , II , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addImm ( <NUM_LIT> ) ; MachineInstr * New = BuildMI ( MBB , II , dl , TII . get ( AddOpc ) , <STR_LIT> ) . addReg ( <STR_LIT> , RegState :: Kill ) . addImm ( AddOffset ) ; New -> getOperand ( <NUM_LIT> ) . setIsDead ( ) ; BuildMI ( MBB , std :: next ( II ) , dl , TII . get ( <STR_LIT> ) ) . addImm ( <NUM_LIT> ) . addReg ( <STR_LIT> , RegState :: Kill ) ; New = BuildMI ( MBB , std :: next ( II ) , dl , TII . get ( SubOpc ) , <STR_LIT> ) . addReg ( <STR_LIT> , RegState :: Kill ) . addImm ( Offset - <NUM_LIT> + <NUM_LIT> ) ; Offset = <NUM_LIT> ; } MI . getOperand ( FIOperandNum ) . ChangeToRegister ( <STR_LIT> , false ) ; assert ( isUInt < <NUM_LIT> > (


<s> return new <ISA_LIT>DAGToDAGISel ( TM , OptLevel


<s> static bool rs6000_secondary_reload_move ( enum rs6000_reg_type to_type , enum rs6000_reg_type from_type , machine_mode mode , secondary_reload_info * sri , bool altivec_p ) { if ( to_type == NO_REG_TYPE || from_type == NO_REG_TYPE ) return false ; if ( ( to_type == PSEUDO_REG_TYPE && from_type == PSEUDO_REG_TYPE ) || ( to_type == PSEUDO_REG_TYPE && IS_STD_REG_TYPE ( from_type ) ) || ( from_type == PSEUDO_REG_TYPE && IS_STD_REG_TYPE ( to_type ) ) ) return true ; if ( to_type == from_type && IS_STD_REG_TYPE ( to_type ) ) return true ; if ( rs6000_secondary_reload_simple_move ( to_type , from_type , mode ) ) { if ( sri


<s> SMLoc StartLoc = Parser . getTok ( ) . getLoc ( ) ; if ( getLexer ( ) . isNot ( AsmToken :: Comma ) ) return Error ( StartLoc , <STR_LIT> ) ; Lex ( ) ; OperandMatchResultTy ResTy ; if ( Kind == MCK_AnyReg ) ResTy = parseAnyReg ( Operands ) ; else if ( Kind == MCK_VR128 ) ResTy = parseVR128 ( Operands ) ; else if ( Kind == MCK_BDXAddr64Disp12 || Kind == MCK_BDXAddr64Disp20 ) ResTy = parseBDXAddr64 ( Operands ) ; else if ( Kind == MCK_BDAddr64Disp12 || Kind == MCK_BDAddr64Disp20 ) ResTy = parseBDAddr64 ( Operands ) ; else if ( Kind == MCK_BDVAddr64Disp12 ) ResTy = parseBDVAddr64 ( Operands ) ; else if ( Kind == MCK_PCRel32 ) ResTy = parsePCRel32 ( Operands ) ; else if ( Kind == MCK_PCRel16 ) ResTy = parsePCRel16 ( Operands ) ; else { const MCExpr * Expr ; SMLoc StartLoc = Parser . getTok ( ) . getLoc ( ) ; if ( Parser . parseExpression ( Expr ) ) return Error ( StartLoc , <STR_LIT> ) ; SMLoc EndLoc = SMLoc :: getFromPointer ( Parser . getTok ( ) . getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; Operands . push_back ( <ISA_LIT>Operand :: createImm ( Expr , StartLoc , EndLoc ) ) ; ResTy = MatchOperand_Success ; } if ( ResTy != MatchOperand_Success ) return true ; } MCInst Inst = MCInstBuilder ( Entry -> Opcode ) ; for ( size_t i = <NUM_LIT> ; i < Operands . size ( ) ; i ++ ) { MCParsedAsmOperand & Operand = * Operands [


<s> std :: vector < std :: string > ret ( Cond c ) { return D ( <STR_LIT> , c


<s> size_t builder :: len ( ) const { return len_visitor { } ( *


<s> bool chkP = checkPredicates ( ) ; bool chkNV = checkNewValues ( ) ; bool chkR = checkRegisters ( ) ; bool chkS = checkSolo ( ) ; bool chkSh = checkShuffle ( ) ; bool chkSl = checkSlots (


<s> SDValue InvMask = DAG . getNOT ( DL , Mask , VT ) ; SDValue Sel = DAG . getNode ( <STR_LIT> , DL , VT , Mask , In1 ) ; SDValue SelInv = DAG . getNode ( <STR_LIT> , DL , VT , InvMask , In2 ) ; return DAG . getNode ( <STR_LIT> , DL ,


<s> float32x2_t result ; __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT> ( b ) : ) ; return result


<s> if ( reg == NULL ) reg = gen_reg_rtx ( Pmode ) ; x = gen_rtx_UNSPEC ( SImode , gen_rtvec ( <NUM_LIT> , orig ) , UNSPEC_GOTOFF ) ; x = gen_rtx_CONST ( SImode , x ) ; emit_move_insn ( reg , x ) ; insn = emit_insn ( gen_addsi3 ( reg , reg , pic_offset_table_rtx ) ) ; } else if ( GET_CODE ( orig ) == SYMBOL_REF ) { if ( reg == NULL ) reg = gen_reg_rtx ( Pmode ) ; x = gen_rtx_UNSPEC ( SImode , gen_rtvec ( <NUM_LIT> , orig ) , UNSPEC_GOT ) ; x = gen_rtx_CONST ( SImode , x ) ; x = gen_rtx_PLUS ( SImode , pic_offset_table_rtx , x ) ; x = gen_const_mem ( SImode , x


<s> setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setLoadExtAction ( <STR_LIT> , <STR_LIT> , Promote ) ; setLoadExtAction ( <STR_LIT> , <STR_LIT> , Promote ) ; setLoadExtAction ( <STR_LIT> , <STR_LIT> , Promote ) ; setLoadExtAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setLoadExtAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; maxStoresPerMemset = <NUM_LIT> ; maxStoresPerMemmove = maxStoresPerMemcpy = <NUM_LIT> ; setTargetDAGCombine ( <STR_LIT> ) ; setTargetDAGCombine ( <STR_LIT>


<s> TLSModel :: Model model = DAG . getTarget ( ) . getTLSModel ( GV ) ; SDValue TPHi = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; TPHi = DAG . getNode ( <STR_LIT> , DL , PtrVT , TPHi ) ; SDValue TPLo = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; TPLo = DAG . getNode ( <STR_LIT> , DL , PtrVT , TPLo ) ; SDValue TPHiShifted = DAG . getNode ( <STR_LIT> , DL , PtrVT , TPHi , DAG . getConstant ( <NUM_LIT> , DL , PtrVT ) ) ; SDValue TP = DAG . getNode ( <STR_LIT> , DL , PtrVT , TPHiShifted , TPLo ) ; SDValue Offset ; switch ( model ) { case TLSModel :: GeneralDynamic : { <ISA_LIT>ConstantPoolValue * CPV = <ISA_LIT>ConstantPoolValue :: Create ( GV , <STR_LIT> ) ; Offset = DAG . getConstantPool ( CPV , PtrVT , <NUM_LIT> ) ; Offset = DAG . getLoad ( PtrVT , DL , DAG . getEntryNode ( ) , Offset , MachinePointerInfo :: getConstantPool ( DAG . getMachineFunction ( ) ) , false , false , false , <NUM_LIT> ) ; Offset = lowerTLSGetOffset ( Node , DAG , <STR_LIT> , Offset ) ; break ; } case TLSModel :: LocalDynamic : { <ISA_LIT>ConstantPoolValue * CPV = <ISA_LIT>ConstantPoolValue :: Create ( GV , <STR_LIT> ) ; Offset = DAG . getConstantPool ( CPV , PtrVT , <NUM_LIT> ) ; Offset = DAG . getLoad ( PtrVT , DL , DAG . getEntryNode ( ) , Offset , MachinePointerInfo :: getConstantPool ( DAG . getMachineFunction ( ) ) , false , false , false , <NUM_LIT> ) ; Offset = lowerTLSGetOffset ( Node , DAG , <STR_LIT> , Offset ) ; <ISA_LIT>MachineFunctionInfo * MFI = DAG . getMachineFunction ( ) . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; MFI -> incNumLocalDynamicTLSAccesses ( ) ; CPV = <ISA_LIT>ConstantPoolValue :: Create ( GV , <STR_LIT> ) ; SDValue DTPOffset = DAG . getConstantPool ( CPV , PtrVT , <NUM_LIT> ) ; DTPOffset = DAG . getLoad ( PtrVT , DL , DAG . getEntryNode ( ) , DTPOffset , MachinePointerInfo :: getConstantPool ( DAG . getMachineFunction ( ) ) , false , false , false , <NUM_LIT> ) ; Offset = DAG . getNode ( <STR_LIT> , DL , PtrVT , Offset , DTPOffset ) ; break ; } case TLSModel ::


<s> bool isConstantImm ( ) const { return isImm ( ) && getImm ( ) -> getKind ( ) == MCExpr ::


<s> AsmPrinter :: EmitBasicBlockEnd ( MBB ) ; <ISA_LIT>TargetStreamer & TS = getTargetStreamer ( ) ; if ( MBB . empty ( ) ) TS .


<s> __inline__ static void sh_media_PREFI ( void * mm , int s ) { __asm__ __volatile__ ( <STR_LIT> : : <STR_LIT> ( ( ( char * ) mm )


<s> MachineFunction & MF = MIRBuilder . getMF ( ) ; unsigned Align = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; Register Dst = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register ListPtr = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; LLT PtrTy = MRI . getType ( ListPtr ) ; LLT IntPtrTy = LLT :: scalar ( PtrTy . getSizeInBits ( ) ) ; const unsigned PtrSize = PtrTy . getSizeInBits ( ) / <NUM_LIT> ; Register List = MRI . createGenericVirtualRegister ( PtrTy ) ; MIRBuilder . buildLoad ( List , ListPtr , * MF . getMachineMemOperand ( MachinePointerInfo ( ) , MachineMemOperand :: MOLoad , PtrSize , PtrSize ) ) ; Register DstPtr ; if ( Align > PtrSize ) { auto AlignMinus1 = MIRBuilder . buildConstant ( IntPtrTy , Align -


<s> MCCFIInstruction Inst = MCCFIInstruction :: createDefCfa ( nullptr , <STR_LIT> , <NUM_LIT> ) ; MAI -> addInitialFrameState (


<s> expandLogic ( unsigned Op , Block & MBB , BlockIt MBBI ) { MachineInstr & MI = * MBBI ; Register SrcLoReg , SrcHiReg , DstLoReg , DstHiReg ; Register DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; bool DstIsDead = MI . getOperand ( <NUM_LIT> ) . isDead ( ) ; bool DstIsKill = MI . getOperand ( <NUM_LIT> ) . isKill ( ) ; bool SrcIsKill = MI . getOperand ( <NUM_LIT> ) . isKill ( ) ; bool ImpIsDead = MI . getOperand ( <NUM_LIT> ) . isDead ( ) ; TRI -> splitReg ( SrcReg , SrcLoReg , SrcHiReg ) ; TRI -> splitReg ( DstReg , DstLoReg , DstHiReg ) ; auto MIBLO = buildMI ( MBB , MBBI , Op ) . addReg ( DstLoReg , RegState :: Define | getDeadRegState ( DstIsDead ) ) . addReg ( DstLoReg , getKillRegState ( DstIsKill

) ) . addReg ( SrcLoReg , getKillRegState ( SrcIsKill ) ) ;