<s> const MCFixupKindInfo & <ISA_LIT>AsmBackend :: getFixupKindInfo ( MCFixupKind Kind ) const { const static MCFixupKindInfo InfosLE [ <STR_LIT> ] = { { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel | MCFixupKindInfo :: FKF_IsAlignedDownTo32Bits } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel | MCFixupKindInfo :: FKF_IsAlignedDownTo32Bits } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel | MCFixupKindInfo :: FKF_IsAlignedDownTo32Bits } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel | MCFixupKindInfo :: FKF_IsAlignedDownTo32Bits } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel | MCFixupKindInfo :: FKF_IsAlignedDownTo32Bits } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel | MCFixupKindInfo :: FKF_IsAlignedDownTo32Bits } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , } ; const static MCFixupKindInfo InfosBE


<s> return addr ( ) + ( <ISA_LIT>GOTPLT0Num +


<s> } } if ( call_really_used_regs [ FIRST_ADDRESS_REGNUM + <NUM_LIT> ] && ! fixed_regs [ FIRST_ADDRESS_REGNUM + <NUM_LIT> ] ) { this_strategy_size = <NUM_LIT> ; if ( size ) { this_strategy_size += SIZE_ADD_AX ( size ) ; } this_strategy_size += <NUM_LIT> * num_regs_to_save ; if ( size + <NUM_LIT> * num_regs_to_save + reg_save_bytes > <NUM_LIT> ) { this_strategy_size += <NUM_LIT> ; } if ( ! reg_save_bytes ) this_strategy_size -- ; if ( this_strategy_size < strategy_size ) { strategy = restore_a1 ; strategy_size = this_strategy_size ; } } switch ( strategy ) { case restore_sp_post_adjust : break ; case restore_sp_pre_adjust : emit_insn ( gen_addsi3 ( stack_pointer_rtx , stack_pointer_rtx , GEN_INT ( size ) ) ) ; size = <NUM_LIT> ; break ; case restore_sp_partial_adjust : emit_insn ( gen_addsi3 ( stack_pointer_rtx , stack_pointer_rtx , GEN_INT ( size + <NUM_LIT> * num_regs_to_save + reg_save_bytes - <NUM_LIT> ) ) ) ; size = <NUM_LIT> - reg_save_bytes - <NUM_LIT> * num_regs_to_save ; break ; case restore_a1 : reg = gen_rtx_REG ( SImode , FIRST_ADDRESS_REGNUM + <NUM_LIT> ) ; emit_insn ( gen_movsi ( reg , stack_pointer_rtx ) ) ; if ( size ) emit_insn ( gen_addsi3 ( reg , reg , GEN_INT ( size ) ) ) ; break ; default : gcc_unreachable ( ) ; } } if ( reg ) reg = gen_rtx_POST_INC ( SImode , reg ) ; for ( i = FIRST_FP_REGNUM ; i <= LAST_FP_REGNUM ; ++ i ) if ( df_regs_ever_live_p ( i ) && ! call_really_used_regs [ i ] ) { rtx addr ; if ( reg ) addr


<s> const MCOperand & RegOp = Inst . getOperand ( <NUM_LIT> ) ; assert ( RegOp . isReg ( ) && <STR_LIT> ) ; int ImmValue = ImmOp . getImm ( ) ; if ( - <NUM_LIT> <= ImmValue && ImmValue <= <NUM_LIT> ) { tmpInst . setOpcode ( <STR_LIT> ) ; tmpInst . addOperand ( MCOperand :: CreateReg ( RegOp . getReg ( ) ) ) ; tmpInst . addOperand ( MCOperand :: CreateReg ( <STR_LIT> ) ) ; tmpInst . addOperand ( MCOperand :: CreateImm ( ImmValue ) ) ; Instructions . push_back ( tmpInst ) ; } else


<s> SDValue EltNo = N -> getOperand ( <NUM_LIT> ) ; if ( ! isa < ConstantSDNode > ( EltNo ) ) return false ; bool HasShuffleIntoBitcast = false ; if ( V . getOpcode ( ) == <STR_LIT> ) { EVT SrcVT = V . getOperand ( <NUM_LIT> ) . getValueType ( ) ; if ( SrcVT . getVectorNumElements ( ) != VT . getVectorNumElements ( ) ) return false ; V = V . getOperand ( <NUM_LIT> ) ; HasShuffleIntoBitcast = true ; } unsigned NumElems = VT . getVectorNumElements ( ) ; unsigned Elt = cast < ConstantSDNode > ( EltNo ) -> getZExtValue ( ) ; int Idx = ( Elt > NumElems ) ? - <NUM_LIT> : SVOp -> getMaskElt ( Elt ) ; V = ( Idx < ( int ) NumElems ) ? V . getOperand ( <NUM_LIT> ) : V . getOperand ( <NUM_LIT> ) ; if ( V . getOpcode ( ) == <STR_LIT> ) V


<s> <ISA_LIT>FunctionInfo * FuncInfo = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; SDLoc dl ( Op ) ; SDValue FI = DAG . getFrameIndex ( FuncInfo -> getVarArgsFrameIndex ( ) , getPointerTy ( ) ) ; const Value * SV = cast < SrcValueSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getValue ( ) ; return DAG . getStore ( Op . getOperand ( <NUM_LIT> ) , dl , FI , Op . getOperand ( <NUM_LIT> )

, MachinePointerInfo ( SV ) , false , false , <NUM_LIT> ) ;


<s> int <ISA_LIT>TTIImpl :: getArithmeticInstrCost ( unsigned Opcode , Type * Ty , TTI :: OperandValueKind Op1Info , TTI :: OperandValueKind Op2Info

, TTI :: OperandValueProperties Opd1PropInfo , TTI :: OperandValueProperties Opd2PropInfo ) {


<s> else if ( const auto * CE = dyn_cast < MCConstantExpr > ( Expr ) ) Inst . addOperand ( MCOperand ::


<s> riscv_emit_int_compare ( & code , & op0 , & op1 ) ; rtx cond = gen_rtx_fmt_ee ( code , GET_MODE ( op0 ) , op0 , op1


<s> if ( AFI -> getDPRCalleeSavedAreaSize ( ) ) { MBBI ++ ; while ( MBBI -> getOpcode ( ) == <STR_LIT> ) MBBI ++ ; } if ( AFI -> getGPRCalleeSavedArea2Size ( ) ) MBBI ++ ; if ( AFI -> getGPRCalleeSavedArea1Size ( ) ) MBBI ++ ; } if ( RetOpcode == <STR_LIT> || RetOpcode == <STR_LIT> ) { MBBI = MBB . getLastNonDebugInstr ( ) ; MachineOperand & JumpTarget = MBBI -> getOperand ( <NUM_LIT> ) ; if ( RetOpcode == <STR_LIT> ) { unsigned TCOpcode = STI . isThumb ( ) ? ( STI . isTargetMachO ( ) ? <STR_LIT> : <STR_LIT> ) : <STR_LIT> ; MachineInstrBuilder MIB = BuildMI ( MBB , MBBI , dl , TII . get ( TCOpcode ) ) ; if ( JumpTarget . isGlobal ( ) ) MIB . addGlobalAddress ( JumpTarget . getGlobal ( ) , JumpTarget . getOffset ( ) , JumpTarget . getTargetFlags ( ) ) ; else { assert ( JumpTarget . isSymbol ( ) ) ; MIB . addExternalSymbol ( JumpTarget . getSymbolName ( ) , JumpTarget . getTargetFlags ( ) ) ; } if ( STI . isThumb ( ) ) MIB . addImm ( <STR_LIT> ) . addReg ( <NUM_LIT> ) ; } else if ( RetOpcode == <STR_LIT> ) { BuildMI ( MBB , MBBI , dl , TII . get ( STI . isThumb ( ) ? <STR_LIT> : <STR_LIT> ) ) . addReg ( JumpTarget . getReg ( ) , RegState :: Kill ) ; } MachineInstr * NewMI = std :: prev ( MBBI ) ; for ( unsigned i = <NUM_LIT> , e = MBBI -> getNumOperands ( ) ; i != e ; ++ i ) NewMI -> addOperand


<s> unsigned <ISA_LIT>TTIImpl :: getIntrinsicInstrCost ( const IntrinsicCostAttributes & ICA , TTI :: TargetCostKind CostKind ) { return BaseT :: getIntrinsicInstrCost ( ICA


<s> if ( TARGET_HS && ( arc_tune == ARC_TUNE_ARCHS4X_REL31A ) ) switch ( get_attr_type ( pred ) ) { case TYPE_STORE : switch ( get_attr_type ( succ ) ) { case TYPE_BRCC : case TYPE_BRCC_NO_DELAY_SLOT : case TYPE_LOOP_END : return <NUM_LIT> ; default : break ; } break ; case TYPE_BRCC


<s> void <ISA_LIT>LowerArgs :: handleByValParam ( Argument * Arg ) { Function * Func = Arg -> getParent ( ) ; Instruction * FirstInst = & ( Func -> getEntryBlock ( ) . front ( ) ) ; PointerType * PType = dyn_cast < PointerType > ( Arg -> getType ( ) ) ; assert ( PType &&


<s> else DecVal = ( Val << <NUM_LIT> ) ; if ( ! tryAddingSymbolicOperand ( Address , Address + DecVal + <NUM_LIT> , true , <NUM_LIT> , Inst , Decoder ) ) Inst

. addOperand ( MCOperand :: createImm ( isNeg ? - DecVal : DecVal ) ) ;


<s> void <ISA_LIT>TargetELFStreamer :: emitEndFunc ( ) { Streamer . EmitIntValue ( <STR_LIT> , sizeof ( uint64_t )


<s> SDValue Idx1 = Op1 . getOperand ( <NUM_LIT> ) ; SDValue Vec2 = Op2 . getOperand ( <NUM_LIT> ) ; SDValue FMAOp1 = FMA . getOperand ( <NUM_LIT> ) ; SDValue FMAOp2 = FMA . getOperand ( <NUM_LIT> ) ; SDValue FMAAcc = FMA . getOperand ( <NUM_LIT> ) ; if ( FMAOp1 . getOpcode ( ) != <STR_LIT> || FMAOp2 . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; FMAOp1 = FMAOp1 . getOperand ( <NUM_LIT> ) ; FMAOp2 = FMAOp2 . getOperand ( <NUM_LIT> ) ; if ( FMAOp1 . getOpcode ( ) != <STR_LIT> || FMAOp2 . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; SDValue Vec3 = FMAOp1 . getOperand ( <NUM_LIT> ) ; SDValue Vec4 = FMAOp2 . getOperand ( <NUM_LIT> ) ; SDValue Idx2 = FMAOp1 . getOperand ( <NUM_LIT> ) ; if ( Idx1 != Op2 . getOperand ( <NUM_LIT> ) || Idx2 != FMAOp2 . getOperand ( <NUM_LIT> ) || Idx1 == Idx2


<s> SDValue N0 = Op -> getOperand ( <NUM_LIT> ) ; SDValue ConstVec = Op -> getOperand ( <NUM_LIT> ) ; bool isSigned = N -> getOpcode ( ) == <STR_LIT> ; if ( ConstVec . getOpcode ( ) != <STR_LIT> || ! isConstVecPow2 ( ConstVec , isSigned , C ) ) return SDValue ( ) ; MVT FloatTy = Op . getSimpleValueType ( ) . getVectorElementType ( ) ; MVT IntTy = N -> getSimpleValueType ( <NUM_LIT> ) . getVectorElementType ( ) ; if ( FloatTy . getSizeInBits ( ) != <NUM_LIT> || IntTy . getSizeInBits ( ) > <NUM_LIT> ) { return SDValue ( ) ; } unsigned IntrinsicOpcode = isSigned


<s> if ( Op . getSubReg ( ) != <NUM_LIT> ) return false ; unsigned Reg = Op . getReg ( ) ; const MCPhysReg * ImpR = Op . isDef ( ) ? D . getImplicitDefs (


<s> Register RHS = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; uint16_t Flags = MI . getFlags ( ) ; LLT S32 = LLT :: scalar ( <NUM_LIT> ) ; LLT S1 = LLT :: scalar ( <NUM_LIT> ) ; auto Abs = B . buildFAbs ( S32 , RHS , Flags ) ; const APFloat C0Val ( <NUM_LIT> ) ; auto C0 = B . buildConstant ( S32 , <NUM_LIT> ) ; auto C1 = B . buildConstant ( S32 , <NUM_LIT> ) ; auto C2 = B . buildConstant ( S32 , FloatToBits ( <NUM_LIT> ) ) ; auto CmpRes = B . buildFCmp ( CmpInst :: FCMP_OGT , S1 , Abs


<s> SDLoc DL ( Op ) ; unsigned Reg = cast < RegisterSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getReg ( ) ; EVT VT = Src . getValueType ( ) ; SDValue Copy ( DAG . getMachineNode ( <STR_LIT> , DL , VT , Src ) ,


<s> bool writeNopData ( uint64_t Count , MCObjectWriter * OW


<s> Register PHIRes = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; const TargetRegisterClass * RC0 = MRI -> getRegClass ( PHIRes ) ; if ( AllAGPRUses && numVGPRUses && ! TRI -> isAGPRClass ( RC0 ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << MI ) ; MRI -> setRegClass ( PHIRes , TRI -> getEquivalentAGPRClass ( RC0 ) ) ; for ( unsigned I = <NUM_LIT> , N = MI . getNumOperands ( ) ; I != N ; I += <NUM_LIT> ) { MachineInstr * DefMI = MRI -> getVRegDef ( MI . getOperand ( I ) . getReg ( ) ) ; if ( DefMI && DefMI -> isPHI ( ) ) PHIOperands . insert ( DefMI ) ; } } bool hasVGPRInput = false ; for ( unsigned i = <NUM_LIT> ; i < MI . getNumOperands ( ) ; i += <NUM_LIT> ) { Register InputReg = MI . getOperand ( i ) . getReg ( ) ; MachineInstr * Def = MRI -> getVRegDef ( InputReg ) ; if ( TRI -> isVectorRegister ( * MRI , InputReg ) ) { if ( Def -> isCopy ( ) ) { Register SrcReg = Def -> getOperand ( <NUM_LIT> ) . getReg ( ) ; const TargetRegisterClass * RC = TRI -> getRegClassForReg ( * MRI , SrcReg ) ; if ( TRI -> isSGPRClass ( RC ) ) continue ; } hasVGPRInput = true ; break ; } else if ( Def -> isCopy ( ) && TRI -> isVectorRegister ( * MRI , Def -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ) { Register SrcReg = Def -> getOperand ( <NUM_LIT> ) . getReg ( ) ; MachineInstr * SrcDef = MRI -> getVRegDef ( SrcReg ) ; unsigned SMovOp ; int64_t Imm ; if ( ! isSafeToFoldImmIntoCopy ( Def , SrcDef , TII , SMovOp , Imm ) ) { hasVGPRInput = true ; break ; } else { MachineFunction * MF = MI . getParent ( ) -> getParent ( ) ; Def -> getOperand ( <NUM_LIT> ) . ChangeToImmediate ( Imm ) ; Def -> addImplicitDefUseOperands ( * MF ) ; Def -> setDesc ( TII -> get ( SMovOp ) ) ; } } } if ( ( ! TRI -> isVectorRegister ( * MRI , PHIRes ) && RC0 != & <STR_LIT> ) && ( hasVGPRInput || numVGPRUses > <NUM_LIT> ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << MI ) ; CreatedBB = TII -> moveToVALU ( MI ) ; } else { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << MI ) ; TII -> legalizeOperands ( MI , MDT ) ; } while ( ! PHIOperands . empty ( ) ) { processPHINode ( * PHIOperands . pop_back_val ( )


<s> if ( getOptLevel ( ) > CodeGenOpt :: None ) addPass ( create<ISA_LIT>HWWAGeneral ( ) ) ; TargetPassConfig :: addMachineSSAOptimization ( ) ; if ( getOptLevel ( ) > CodeGenOpt


<s> static MCCodeGenInfo * create<ISA_LIT>MCCodeGenInfo ( StringRef TT , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) { MCCodeGenInfo * X = new MCCodeGenInfo


<s> bool shouldExpandShift ( SelectionDAG & DAG , SDNode * N ) const override { if ( DAG . getMachineFunction ( ) . getFunction (


<s> ParseInstruction ( ParseInstructionInfo & Info , StringRef Name , SMLoc NameLoc , OperandVector & Operands ) { size_t Start = <NUM_LIT> , Next = Name . find ( '.' ) ; StringRef Mnemonic = Name . slice ( Start , Next ) ; if ( Mnemonic == <STR_LIT> ) Mnemonic = <STR_LIT> ; Operands . push_back ( <STR_LIT> ( Mnemonic , NameLoc ) ) ; if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) { if ( ParseOperand ( Operands , Name ) ) { SMLoc Loc = getLexer ( ) . getLoc ( ) ; Parser . eatToEndOfStatement ( ) ; return Error ( Loc , <STR_LIT> ) ; } while ( getLexer ( ) . is ( AsmToken :: Comma ) ) { Parser . Lex ( ) ; if ( ParseOperand ( Operands , Name ) ) { SMLoc Loc = getLexer ( ) . getLoc ( ) ; Parser . eatToEndOfStatement ( ) ; return Error ( Loc , <STR_LIT> ) ; } } } if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) { SMLoc Loc = getLexer ( ) . getLoc ( ) ; Parser . eatToEndOfStatement ( ) ; return Error ( Loc


<s> int getReturnAddrSaveIndex ( ) const { return


<s> auto MMO = MF . getMachineMemOperand ( MPO , MachineMemOperand :: MOLoad , Size , inferAlignFromPtrInfo ( MF , MPO ) ) ; return MIRBuilder . buildLoad ( Res , Addr ,


<s> assert ( ( PVT == <STR_LIT> || PVT == <STR_LIT> ) && <STR_LIT> ) ; const TargetRegisterClass * RC = ( PVT == <STR_LIT> ) ? & <STR_LIT> : & <STR_LIT> ; unsigned Tmp = MRI . createVirtualRegister ( RC ) ; const <ISA_LIT>RegisterInfo * RegInfo = Subtarget -> getRegisterInfo ( ) ; unsigned FP = ( PVT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; unsigned SP = RegInfo -> getStackRegister ( ) ; MachineInstrBuilder MIB ; const int64_t LabelOffset = <NUM_LIT> * PVT . getStoreSize ( ) ; const int64_t SPOffset = <NUM_LIT> * PVT . getStoreSize ( ) ; unsigned PtrLoadOpc = ( PVT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; unsigned IJmpOpc = ( PVT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; MIB = BuildMI ( * MBB , MI , DL , TII -> get ( PtrLoadOpc ) , FP ) ; for ( unsigned i = <NUM_LIT> ; i < <STR_LIT> ; ++ i ) MIB . addOperand ( MI -> getOperand ( i ) ) ; MIB . setMemRefs ( MMOBegin , MMOEnd ) ; MIB = BuildMI ( * MBB , MI , DL , TII -> get ( PtrLoadOpc ) , Tmp ) ; for ( unsigned i = <NUM_LIT> ; i < <STR_LIT> ; ++ i ) { if ( i == <STR_LIT> ) MIB . addDisp ( MI -> getOperand ( i ) , LabelOffset ) ; else MIB . addOperand ( MI -> getOperand ( i ) ) ; } MIB . setMemRefs ( MMOBegin


<s> bool <ISA_LIT>AsmParser :: ParseDirectiveISAVersion ( ) { if ( getSTI ( ) . getTargetTriple ( ) . getArch ( ) != Triple :: amdgcn ) { return Error ( getLoc ( ) , <STR_LIT> <STR_LIT> ) ; } auto ISAVersionStringFromASM = getToken ( ) . getStringContents ( ) ; std :: string ISAVersionStringFromSTI ; raw_string_ostream ISAVersionStreamFromSTI ( ISAVersionStringFromSTI ) ; IsaInfo :: streamIsaVersion ( & getSTI ( ) , ISAVersionStreamFromSTI ) ; if ( ISAVersionStringFromASM != ISAVersionStreamFromSTI . str


<s> void <ISA_LIT>PassConfig :: addPreEmitPass (


<s> else if ( flag_pic ) x = sparc_legitimize_pic_address ( x , NULL_RTX ) ; else if ( GET_CODE ( x ) == PLUS && CONSTANT_ADDRESS_P ( XEXP ( x , <NUM_LIT> ) ) ) x = gen_rtx_PLUS ( Pmode , XEXP ( x , <NUM_LIT> ) , copy_to_mode_reg ( Pmode , XEXP ( x , <NUM_LIT> ) ) ) ; else if ( GET_CODE ( x ) == PLUS && CONSTANT_ADDRESS_P ( XEXP ( x , <NUM_LIT> ) ) ) x = gen_rtx_PLUS ( Pmode , XEXP ( x , <NUM_LIT> ) , copy_to_mode_reg ( Pmode , XEXP ( x , <NUM_LIT> ) ) ) ; else if ( GET_CODE ( x ) == SYMBOL_REF || GET_CODE ( x ) == CONST || GET_CODE ( x ) == LABEL_REF ) x = copy_to_suggested_reg ( x , NULL_RTX , Pmode ) ; return x


<s> TargetLoweringObjectFile * getObjFileLowering ( ) const override { return TLOF . get ( )


<s> return ( ( Reg >= <STR_LIT> && Reg <= <STR_LIT> ) ||

( Reg >= <STR_LIT> && Reg <= <STR_LIT> ) ) ;


<s> unsigned OA = TRI . getSubRegIdxOffset ( RA . Sub ) ; unsigned SB = TRI . getSubRegIdxSize ( RB . Sub ) ; unsigned OB = TRI . getSubRegIdxOffset ( RB . Sub ) ; if ( OA <= OB && OA + SA > OB ) return true ; if ( OB <= OA && OB + SB > OA ) return true ; return false ; } assert ( PhysA && PhysB ) ; ( void ) PhysA , ( void ) PhysB ; unsigned A = RA . Sub ? TRI . getSubReg ( RA . Reg , RA . Sub ) : RA . Reg ; unsigned B = RB . Sub ? TRI . getSubReg ( RB . Reg , RB . Sub ) : RB . Reg ; for ( MCRegAliasIterator I ( A , & TRI , true ) ; I . isValid ( ) ; ++ I ) if ( B == *


<s> MCCodeEmitter * llvm :: create<ISA_LIT>MCCodeEmitter ( const MCInstrInfo & MII , const MCRegisterInfo & MRI , MCContext & Ctx ) { return new <ISA_LIT>MCCodeEmitter (


<s> return DestSourcePair { MI . getOperand ( <NUM_LIT> ) , MI . getOperand ( <NUM_LIT> ) } ; } if ( MI . getOpcode ( ) == <STR_LIT> && MI . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> && MI . getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) { return DestSourcePair { MI . getOperand ( <NUM_LIT> ) , MI . getOperand


<s> return false ; } MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; <ISA_LIT>MachineFunctionInfo * FuncInfo = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; const bool SpillVGPRToAGPR = ST . hasMAIInsts ( ) && FuncInfo -> hasSpilledVGPRs ( ) && EnableSpillVGPRToAGPR ; bool MadeChange = false ; const bool SpillToAGPR = EnableSpillVGPRToAGPR && ST . hasMAIInsts ( ) ; std :: unique_ptr < RegScavenger > RS ; bool NewReservedRegs = false ; const bool HasSGPRSpillToVGPR = TRI -> spillSGPRToVGPR ( ) && ( HasCSRs || FuncInfo -> hasSpilledSGPRs ( ) ) ; if ( HasSGPRSpillToVGPR || SpillVGPRToAGPR ) { lowerShiftReservedVGPR ( MF , ST ) ; for ( MachineBasicBlock & MBB : MF ) { MachineBasicBlock :: iterator Next ; for ( auto I = MBB . begin ( ) , E = MBB . end ( ) ; I != E ; I = Next ) { MachineInstr & MI = * I ; Next = std :: next ( I ) ; if ( SpillToAGPR && TII -> isVGPRSpill ( MI ) ) { unsigned FIOp = <STR_LIT> ( MI . getOpcode ( ) , <STR_LIT> :: vaddr


<s> void * Addr = ( void * ) ( intptr_t ) JCE . getCurrentPCValue ( ) ; for ( int x = <NUM_LIT> ; x < <NUM_LIT> ; ++ x ) JCE . emitWordLE ( <NUM_LIT> ) ; EmitBranchToAt ( Addr , Fn


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT>


<s> Register Reg = <STR_LIT> + RegNo ; Inst . addOperand ( MCOperand :: createReg (


<s> switch ( Kind ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : Value >>= <NUM_LIT> ; case <STR_LIT> : unsigned Hi4 = ( Value & <NUM_LIT> ) >> <NUM_LIT> ; unsigned Lo12 = Value & <NUM_LIT> ; Value = ( Hi4 << <NUM_LIT> ) | ( Lo12 ) ; return Value ; } return Value


<s> case <STR_LIT> : if ( Opd2Info == TargetTransformInfo :: OK_UniformConstantValue && Opd2PropInfo == TargetTransformInfo :: OP_PowerOf2 ) { Cost += getArithmeticInstrCost ( Instruction :: Add , Ty , Opd1Info , Opd2Info , TargetTransformInfo :: OP_None , TargetTransformInfo :: OP_None ) ; Cost += getArithmeticInstrCost ( Instruction :: Sub , Ty , Opd1Info , Opd2Info , TargetTransformInfo :: OP_None , TargetTransformInfo :: OP_None ) ; Cost += getArithmeticInstrCost ( Instruction :: Select , Ty , Opd1Info , Opd2Info , TargetTransformInfo :: OP_None , TargetTransformInfo :: OP_None ) ; Cost += getArithmeticInstrCost ( Instruction :: AShr , Ty , Opd1Info , Opd2Info , TargetTransformInfo :: OP_None , TargetTransformInfo :: OP_None ) ; return Cost ; } LLVM_FALLTHROUGH ; case <STR_LIT> : if ( Opd2Info == TargetTransformInfo :: OK_UniformConstantValue ) { auto VT = TLI -> getValueType ( DL , Ty ) ; if ( TLI -> isOperationLegalOrCustom ( <STR_LIT> , VT ) ) { int MulCost = getArithmeticInstrCost ( Instruction :: Mul , Ty , Opd1Info , Opd2Info , TargetTransformInfo :: OP_None , TargetTransformInfo :: OP_None ) ; int AddCost = getArithmeticInstrCost ( Instruction :: Add , Ty , Opd1Info , Opd2Info , TargetTransformInfo :: OP_None , TargetTransformInfo :: OP_None ) ; int ShrCost = getArithmeticInstrCost ( Instruction :: AShr , Ty , Opd1Info , Opd2Info , TargetTransformInfo :: OP_None , TargetTransformInfo :: OP_None ) ; return MulCost * <NUM_LIT> + AddCost * <NUM_LIT> + ShrCost * <NUM_LIT> + <NUM_LIT> ; } } Cost += BaseT :: getArithmeticInstrCost ( Opcode , Ty , Opd1Info , Opd2Info , Opd1PropInfo , Opd2PropInfo ) ; if ( Ty -> isVectorTy ( ) ) { Cost += getArithmeticInstrCost ( Instruction :: ExtractElement , Ty , Opd1Info , Opd2Info , Opd1PropInfo , Opd2PropInfo ) ; Cost += getArithmeticInstrCost ( Instruction :: InsertElement , Ty , Opd1Info , Opd2Info , Opd1PropInfo , Opd2PropInfo ) ; Cost += Cost ; } return Cost ; case


<s> if ( ! ! ( Ops [ I ] & Mod ) != DefaultValue ) return false ; } if ( HasDstSel && ( Ops [ <NUM_LIT> ] & <STR_LIT> ) != <NUM_LIT> ) return false ; return


<s> if ( ToW == <NUM_LIT> && isNEONi64splat


<s> arg2_stmt = va_list_skip_additions ( gimple_phi_arg_def ( offset_stmt , <NUM_LIT> ) ) ; if ( arg1_stmt == NULL || ! is_gimple_assign ( arg1_stmt ) || arg2_stmt == NULL || ! is_gimple_assign ( arg2_stmt ) ) goto escapes ; code1 = gimple_assign_rhs_code ( arg1_stmt ) ; code2 = gimple_assign_rhs_code ( arg2_stmt ) ; if ( code1 == COMPONENT_REF && ( code2 == MINUS_EXPR || code2 == PLUS_EXPR ) ) ; else if ( code2 == COMPONENT_REF && ( code1 == MINUS_EXPR || code1 == PLUS_EXPR ) ) { gimple tem = arg1_stmt ; code2 = code1 ; arg1_stmt = arg2_stmt ; arg2_stmt = tem ; } else goto escapes ; if ( ! tree_fits_shwi_p ( gimple_assign_rhs2 ( arg2_stmt ) ) ) goto escapes ; sub = tree_to_shwi ( gimple_assign_rhs2 ( arg2_stmt ) ) ; if ( code2 == MINUS_EXPR ) sub = - sub ; if ( sub < - <NUM_LIT> || sub > - <NUM_LIT> ) goto escapes ; arg1 = gimple_assign_rhs1 ( arg1_stmt ) ; arg2 = gimple_assign_rhs1 ( arg2_stmt ) ; if ( TREE_CODE ( arg2 ) == SSA_NAME ) { arg2_stmt = va_list_skip_additions ( arg2 ) ; if ( arg2_stmt == NULL || ! is_gimple_assign ( arg2_stmt ) || gimple_assign_rhs_code ( arg2_stmt ) != COMPONENT_REF ) goto escapes ; arg2 = gimple_assign_rhs1 ( arg2_stmt ) ; } if ( arg1 != arg2 ) goto escapes ; if ( TREE_CODE ( arg1 ) != COMPONENT_REF || TREE_OPERAND ( arg1 , <NUM_LIT> ) != va_list_gpr_counter_field || get_base_address ( arg1 ) != base ) goto escapes ; cfun -> va_list_fpr_size |= <NUM_LIT> ; return false ; } if ( offset_stmt && is_gimple_assign ( offset_stmt ) && gimple_assign_rhs_code ( offset_stmt ) == COMPONENT_REF ) offset = gimple_assign_rhs1 ( offset_stmt ) ; } if ( TREE_CODE ( offset ) != COMPONENT_REF || TREE_OPERAND ( offset , <NUM_LIT> ) != va_list_gpr_counter_field || get_base_address ( offset ) != base ) goto escapes ; else cfun -> va_list_fpr_size |= <NUM_LIT> ; return false ; escapes : si -> va_list_escapes = true ; return false


<s> return ( n == <NUM_LIT> ) ? <NUM_LIT> : <NUM_LIT> +


<s> const MCFixupKindInfo & getFixupKindInfo ( MCFixupKind Kind


<s> if ( ! STI . hasLoadStoreOnCond ( ) ) return false ; if ( Pred . size ( ) != <NUM_LIT> ) return false ; const MachineRegisterInfo & MRI = MBB . getParent ( ) -> getRegInfo ( ) ; const TargetRegisterClass * RC = RI . getCommonSubClass ( MRI . getRegClass ( TrueReg ) , MRI . getRegClass ( FalseReg ) ) ; if ( ! RC ) return false ; if ( ( STI . hasLoadStoreOnCond2 ( ) && <STR_LIT> . hasSubClassEq ( RC ) ) || <STR_LIT> . hasSubClassEq ( RC ) || <STR_LIT> . hasSubClassEq ( RC ) ) { CondCycles = <NUM_LIT> ; TrueCycles =


<s> unsigned FrameObjSize = std :: max ( Flags . getByValSize ( ) , RegAreaSize ) ; int FrameObjOffset ; if ( RegAreaSize ) FrameObjOffset = ( int ) CC . reservedArgArea ( ) - ( int ) ( ( CC . intArgRegs ( ) . size ( ) - FirstReg ) * GPRSizeInBytes ) ; else FrameObjOffset = VA . getLocMemOffset ( ) ; EVT PtrTy = getPointerTy ( ) ; int FI = MFI -> CreateFixedObject ( FrameObjSize , FrameObjOffset , true ) ; SDValue FIN = DAG . getFrameIndex ( FI , PtrTy ) ; InVals . push_back ( FIN ) ; if ( ! NumRegs


<s> setParent ( nullptr ) ; setBBSelectRegOut ( <NUM_LIT>


<s> if ( hasDisp && MSrc . isReg ( ) ) MSrc . setIsKill ( false ) ; MachineInstrBuilder MIM = BuildMI ( * BB , MI , DL , TII -> get ( MOp ) ) . addOperand ( MSrc ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) . addDisp ( hasDisp ? Disp : ZeroDisp , <NUM_LIT> ) . addReg ( <NUM_LIT> ) ; MachineInstr * MIO = BuildMI ( * BB , ( MachineInstr * ) MIM , DL , TII -> get ( FOp ) , MRI . createVirtualRegister ( MRI . getRegClass ( VSrc ) ) ) . addReg ( VSrc ) . addOperand ( MSrc ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) . addDisp ( hasDisp ? Disp : ZeroDisp , <NUM_LIT> ) . addReg ( <NUM_LIT> ) ; MIM . addReg ( MIO -> getOperand ( <NUM_LIT> ) . getReg


<s> static Reloc :: Model getEffectiveRelocModel ( const Triple & TT , Optional < Reloc :: Model > RM ) { return Reloc ::


<s> Res = tryDecodeInst ( DecoderTableGFX80_UNPACKED64 , MI , QW , Address ) ; if ( Res ) break ; } if ( STI . getFeatureBits ( ) [ <STR_LIT> ] ) { Res = tryDecodeInst ( DecoderTableGFX9_DL64 , MI , QW , Address ) ; if ( Res ) break ; } } Bytes = Bytes_ . slice ( <NUM_LIT> , MaxInstBytesNum ) ; if ( Bytes . size ( ) < <NUM_LIT> ) break ; const uint32_t DW = eatBytes < uint32_t > ( Bytes ) ; Res = tryDecodeInst ( DecoderTableVI32 , MI , DW , Address ) ; if ( Res ) break ; Res = tryDecodeInst ( DecoderTable<ISA_LIT>32 , MI , DW , Address ) ; if ( Res ) break ; Res = tryDecodeInst ( DecoderTableGFX932 , MI , DW , Address ) ; if ( Res ) break ; if ( Bytes . size ( ) < <NUM_LIT> ) break ; const uint64_t QW = ( ( uint64_t ) eatBytes < uint32_t > ( Bytes ) << <NUM_LIT> ) | DW ; Res = tryDecodeInst ( DecoderTableVI64 , MI , QW , Address ) ; if ( Res ) break ; Res = tryDecodeInst ( DecoderTable<ISA_LIT>64 , MI , QW ,


<s> return <STR_LIT> :: getAddressableNumVGPRs ( MCSubtargetInfo


<s> static <ISA_LIT>Operand :: Ptr CreateImm ( int64_t Val , SMLoc Loc , enum ImmTy Type = ImmTyNone , bool IsFPImm = false ) { auto Op = llvm :: make_unique < <ISA_LIT>Operand > ( Immediate ) ; Op -> Imm . Val = Val ; Op -> Imm . IsFPImm =


<s> return false ; case MachineOperand :: MO_ConstantPoolIndex : case MachineOperand :: MO_TargetIndex : case MachineOperand :: MO_JumpTableIndex : case MachineOperand :: MO_ExternalSymbol : case MachineOperand :: MO_GlobalAddress : case MachineOperand :: MO_BlockAddress : return true ; case MachineOperand :: MO_RegisterMask : case MachineOperand ::


<s> Params . clear ( ) ; Results . clear ( )


<s> assert ( ContainerVT . isScalableVector ( ) && <STR_LIT> ) ; MVT XLenVT = Subtarget . getXLenVT ( ) ; SDValue VL = VecVT . isFixedLengthVector ( ) ? DAG . getConstant ( VecVT . getVectorNumElements ( ) ,

DL , XLenVT ) : DAG . getTargetConstant ( <STR_LIT> , DL , XLenVT ) ;


<s> else return ( GET_MODE_SIZE ( mode )


<s> if ( epilogue_p < <NUM_LIT> || current_function_interrupt || ! call_used_regs [ temp ] || fixed_regs [ temp ] ) temp = - <NUM_LIT> ; if ( temp < <NUM_LIT> && ! current_function_interrupt && epilogue_p >= <NUM_LIT> ) { HARD_REG_SET temps = ( regs_invalidated_by_call & ~ fixed_reg_set & savable_regs ) ; if ( epilogue_p > <NUM_LIT> ) { int nreg = <NUM_LIT> ; if ( crtl -> return_rtx ) { machine_mode mode ; mode = GET_MODE ( crtl -> return_rtx ) ; if ( BASE_RETURN_VALUE_REG ( mode ) == FIRST_RET_REG ) nreg = hard_regno_nregs ( FIRST_RET_REG , mode ) ; } for ( i = <NUM_LIT> ; i < nreg ; i ++ ) CLEAR_HARD_REG_BIT ( temps , FIRST_RET_REG + i ) ; if ( crtl -> calls_eh_return ) { CLEAR_HARD_REG_BIT ( temps , EH_RETURN_STACKADJ_REGNO ) ; for ( i = <NUM_LIT> ; i <= <NUM_LIT> ; i ++ ) CLEAR_HARD_REG_BIT ( temps , EH_RETURN_DATA_REGNO ( i ) ) ; } } if ( epilogue_p <= <NUM_LIT> ) { for ( i = FIRST_PARM_REG ; i < FIRST_PARM_REG + NPARM_REGS ( SImode ) ; i ++ ) CLEAR_HARD_REG_BIT ( temps , i ) ; if ( cfun -> static_chain_decl != NULL ) CLEAR_HARD_REG_BIT ( temps , STATIC_CHAIN_REGNUM ) ; } temp = scavenge_reg ( & temps ) ; } if ( temp < <NUM_LIT> && live_regs_mask ) { HARD_REG_SET temps ; temps = * live_regs_mask ; CLEAR_HARD_REG_BIT ( temps , REGNO ( reg ) ) ; temp = scavenge_reg ( & temps


<s> } assert ( N -> getOpcode ( ) == <STR_LIT> && <STR_LIT> ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; unsigned EltSize = VT . getVectorElementType ( ) . getSizeInBits ( ) / <NUM_LIT> ; unsigned NumElts = VT . getVectorNumElements ( ) ; MVT TruncVT = <STR_LIT> ( EltSize ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; for ( unsigned i = <NUM_LIT> ; i != NumElts ; ++ i ) { ConstantSDNode * C = cast < ConstantSDNode > ( N -> getOperand ( i ) ) ; const APInt & CInt = C -> getAPIntValue ( ) ; Ops . push_back ( DAG . getConstant ( CInt . zextOrTrunc ( <NUM_LIT> ) ,


<s> if ( USE_HIDDEN_LINKONCE ) { cgraph_node :: create ( decl ) -> set_comdat_group ( DECL_ASSEMBLER_NAME ( decl ) ) ; targetm . asm_out . unique_section ( decl , <NUM_LIT> ) ; switch_to_section ( get_named_section ( decl , NULL , <NUM_LIT> ) ) ; DECL_WEAK ( decl ) = <NUM_LIT> ; ASM_WEAKEN_DECL ( asm_out_file , decl , name , <NUM_LIT> ) ; targetm . asm_out . globalize_label ( asm_out_file , name ) ; targetm . asm_out . assemble_visibility ( decl , VISIBILITY_HIDDEN ) ; ASM_DECLARE_FUNCTION_NAME ( asm_out_file , name , decl ) ; } else { switch_to_section ( text_section ) ; ASM_OUTPUT_LABEL ( asm_out_file , name ) ; } DECL_INITIAL ( decl ) = make_node ( BLOCK ) ; current_function_decl =


<s> break ; case Function :: WeakAnyLinkage : case Function :: WeakODRLinkage : case Function :: LinkOnceAnyLinkage : case Function :: LinkOnceODRLinkage : if ( Subtarget -> isTargetDarwin ( ) ) { O << <STR_LIT> << CurrentFnName << <STR_LIT> ; O << <STR_LIT> << CurrentFnName << <STR_LIT> ; } else { O << TAI -> getWeakRefDirective ( ) << CurrentFnName << <STR_LIT> ; } break ; } printVisibility ( CurrentFnName , F -> getVisibility ( ) ) ; if ( AFI -> isThumbFunction ( ) ) { EmitAlignment ( MF . getAlignment ( ) , F , AFI -> getAlign ( ) ) ; O << <STR_LIT> ; O << <STR_LIT> ; if ( Subtarget -> isTargetDarwin ( ) ) O << <STR_LIT> << CurrentFnName ; O << <STR_LIT> ; InCPMode = false ; } else { EmitAlignment ( MF . getAlignment ( ) , F ) ; } O << CurrentFnName << <STR_LIT> ; DW -> BeginFunction ( & MF ) ; if ( Subtarget -> isTargetDarwin ( ) ) { MachineFunction :: iterator I = MF . begin ( ) ; if ( ++ I == MF . end ( ) && MF . front ( ) . empty ( ) ) O << <STR_LIT> ; } for ( MachineFunction :: const_iterator I = MF . begin ( ) , E = MF . end ( ) ; I != E ; ++ I ) { if ( I != MF . begin ( ) ) { printBasicBlockLabel ( I , true , true , VerboseAsm ) ; O << '\n' ; } for ( MachineBasicBlock :: const_iterator II = I -> begin ( ) , E = I -> end ( ) ; II != E ;


<s> bool <ISA_LIT>InstructionSelector :: insertComparison ( CmpConstants Helper , InsertInfo I , unsigned ResReg , <STR_LIT> Cond , unsigned LHSReg , unsigned RHSReg , unsigned PrevRes ) const { auto CmpI = BuildMI ( I . MBB , I . InsertBefore , I . DbgLoc , TII . get ( Helper . ComparisonOpcode ) ) . addUse ( LHSReg ) . addUse ( RHSReg ) . add ( predOps ( <STR_LIT> ) ) ; if ( ! constrainSelectedInstRegOperands ( * CmpI , TII , TRI , RBI ) ) return false ; if ( Helper . ReadFlagsOpcode != <STR_LIT> ) { auto ReadI = BuildMI ( I . MBB , I . InsertBefore , I . DbgLoc , TII . get ( Helper . ReadFlagsOpcode ) )


<s> } } if ( Subtarget -> isThumb1Only ( ) ) { SDValue RHS = N -> getOperand ( <NUM_LIT> ) ; if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( RHS ) ) { int32_t imm = C -> getSExtValue ( ) ; if ( imm < <NUM_LIT> && imm > std :: numeric_limits < int > :: min ( ) ) { SDLoc DL ( N ) ; RHS = DAG . getConstant ( - imm , DL , <STR_LIT> ) ; unsigned Opcode = ( N -> getOpcode ( ) == <STR_LIT> )


<s> CommentString = <STR_LIT> ; CodePointerSize = CalleeSaveStackSlotSize = <NUM_LIT> ; IsLittleEndian = true ; StackGrowsUp = false ; DollarIsPC =


<s> RegisterTarget < Triple :: gbz80 , false >

X ( The<ISA_LIT>Z80Target , <STR_LIT> , <STR_LIT> ) ;


<s> MachineBasicBlock :: iterator I = MBB . getLastNonDebugInstr ( ) ; if ( I == MBB . end ( ) ) return <NUM_LIT> ; if ( I -> getOpcode ( ) != <STR_LIT> && I -> getOpcode ( ) != <STR_LIT> && I -> getOpcode ( ) != <STR_LIT> && I -> getOpcode ( ) != <STR_LIT> && I -> getOpcode ( ) != <STR_LIT> && I -> getOpcode ( ) != <STR_LIT> && I -> getOpcode ( ) != <STR_LIT> && I -> getOpcode ( ) != <STR_LIT> ) return <NUM_LIT> ; I -> eraseFromParent ( ) ; I = MBB . end ( ) ; if ( I == MBB . begin ( ) ) return <NUM_LIT> ; -- I ; if ( I -> getOpcode ( ) != <STR_LIT> && I -> getOpcode ( ) != <STR_LIT> && I -> getOpcode ( ) != <STR_LIT> && I -> getOpcode ( ) != <STR_LIT> && I -> getOpcode ( ) != <STR_LIT> && I -> getOpcode ( ) != <STR_LIT> && I -> getOpcode ( ) != <STR_LIT> ) return <NUM_LIT> ; I -> eraseFromParent ( ) ; return <NUM_LIT>


<s> unsigned Depth = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; DebugLoc dl = Op . getDebugLoc ( ) ; if ( Depth > <NUM_LIT> ) { SDValue FrameAddr = LowerFRAMEADDR ( Op , DAG ) ; SDValue Offset = DAG . getConstant ( TD -> getPointerSize ( ) , Subtarget -> is64Bit ( ) ? <STR_LIT> : <STR_LIT> ) ; return DAG . getLoad ( getPointerTy ( ) , dl , DAG . getEntryNode ( ) , DAG . getNode ( <STR_LIT> , dl , getPointerTy ( ) , FrameAddr , Offset ) , NULL , <NUM_LIT> ) ; } SDValue RetAddrFI = getReturnAddressFrameIndex ( DAG ) ; return DAG . getLoad ( getPointerTy ( ) , dl , DAG . getEntryNode ( ) , RetAddrFI , NULL


<s> if ( GV -> isThreadLocal ( ) ) return false ; if ( MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . ClassifyGlobalReference ( GV , MF . getTarget ( ) ) != <STR_LIT> ) return false ; Register Dst = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; uint64_t MinOffset = - <NUM_LIT> ; for ( auto & UseInstr : MRI . use_nodbg_instructions ( Dst ) ) { if ( UseInstr . getOpcode ( ) != TargetOpcode :: G_PTR_ADD ) return false ; auto Cst = getIConstantVRegValWithLookThrough ( UseInstr . getOperand ( <NUM_LIT> ) . getReg ( ) , MRI ) ; if ( ! Cst ) return false ; MinOffset = std :: min ( MinOffset , Cst -> Value . getZExtValue ( ) ) ; } uint64_t CurrOffset = GlobalOp .


<s> return static_cast < MCELFStreamer & > ( Streamer


<s> rtx_insn * insn = emit_move_insn ( gen_frame_mem ( Pmode , addr ) , reg ) ; RTX_FRAME_RELATED_P ( insn ) =


<s> pops_needed = <NUM_LIT> ; if ( reg_containing_return_addr == - <NUM_LIT> ) { regs_to_pop |= <NUM_LIT> << LR_REGNUM ; ++ pops_needed ; } if ( TARGET_BACKTRACE ) { regs_to_pop |= ( <NUM_LIT> << ARM_HARD_FRAME_POINTER_REGNUM ) | ( <NUM_LIT> << SP_REGNUM ) ; pops_needed += <NUM_LIT> ; } if ( pops_needed == <NUM_LIT> ) { if ( crtl -> calls_eh_return ) asm_fprintf ( f , <STR_LIT> , SP_REGNUM , ARM_EH_STACKADJ_REGNUM ) ; if ( IS_CMSE_ENTRY ( arm_current_func_type ( ) ) ) { asm_fprintf ( f , <STR_LIT> , reg_containing_return_addr ) ; asm_fprintf ( f , <STR_LIT> , reg_containing_return_addr ) ; } else asm_fprintf ( f , <STR_LIT> , reg_containing_return_addr ) ; return ; } else if ( ! TARGET_INTERWORK && ! TARGET_BACKTRACE && ! is_called_in_ARM_mode ( current_function_decl ) && ! crtl -> calls_eh_return && ! IS_CMSE_ENTRY ( arm_current_func_type ( ) ) ) { asm_fprintf ( f , <STR_LIT> , PC_REGNUM ) ; return ; } regs_available_for_popping = <NUM_LIT> ; if ( crtl -> calls_eh_return ) size = <NUM_LIT> ; else { if ( crtl -> return_rtx != <NUM_LIT> ) mode = GET_MODE ( crtl -> return_rtx ) ; else mode = DECL_MODE ( DECL_RESULT ( current_function_decl ) ) ; size = GET_MODE_SIZE ( mode ) ; if ( size == <NUM_LIT> ) { if ( mode == VOIDmode ) regs_available_for_popping = ( <NUM_LIT> << ARG_REGISTER ( <NUM_LIT> ) ) | ( <NUM_LIT> << ARG_REGISTER ( <NUM_LIT> ) ) | ( <NUM_LIT> << ARG_REGISTER ( <NUM_LIT> ) ) ; else regs_available_for_popping = ( <NUM_LIT> << ARG_REGISTER ( <NUM_LIT> ) ) | ( <NUM_LIT> << ARG_REGISTER ( <NUM_LIT> ) ) ; } else if ( size <= <NUM_LIT> ) regs_available_for_popping = ( <NUM_LIT> << ARG_REGISTER ( <NUM_LIT> ) ) | ( <NUM_LIT> << ARG_REGISTER ( <NUM_LIT> ) ) ; else if ( size <= <NUM_LIT> ) regs_available_for_popping = ( <NUM_LIT> << ARG_REGISTER ( <NUM_LIT> ) ) ; } for ( available = regs_available_for_popping , required = regs_to_pop ; required != <NUM_LIT> && available != <NUM_LIT> ; available &= ~ ( available & - available ) , required &= ~ ( required & - required ) ) -- pops_needed ; if ( available > <NUM_LIT> ) regs_available_for_popping &= ~ available ; else if ( pops_needed ) { if ( regs_available_for_popping == <NUM_LIT> && reg_containing_return_addr ==


<s> const <ISA_LIT>Subtarget & ST = F . getSubtarget < <ISA_LIT>Subtarget > ( ) ; uint32_t FP32Denormals = ST . hasFP32Denormals ( ) ? FP_DENORM_FLUSH_NONE : FP_DENORM_FLUSH_IN_FLUSH_OUT ; uint32_t FP64Denormals = ST . hasFP64Denormals ( ) ? FP_DENORM_FLUSH_NONE : FP_DENORM_FLUSH_IN_FLUSH_OUT ; return FP_ROUND_MODE_SP ( FP_ROUND_ROUND_TO_NEAREST ) | FP_ROUND_MODE_DP ( FP_ROUND_ROUND_TO_NEAREST ) | FP_DENORM_MODE_SP ( FP32Denormals ) | FP_DENORM_MODE_DP (


<s> bool <ISA_LIT>AsmParser :: ParseRegister ( unsigned & RegNo , SMLoc & StartLoc , SMLoc & EndLoc ) { return parseRegister ( RegNo , StartLoc , EndLoc ,


<s> const <ISA_LIT>Subtarget * getSubtargetImpl ( )


<s> unsigned RegNum = <ISA_LIT>RegisterInfo :: getRegisterNumbering ( CSI [ i ] . getReg ( ) ) ; if ( CSI [ i ] . getRegClass ( ) == <STR_LIT> ) CPUBitmask |= ( <NUM_LIT> << RegNum ) ; else FPUBitmask |= ( <NUM_LIT> << RegNum ) ; } if ( RI . hasFP ( * MF ) ) CPUBitmask |= ( <NUM_LIT> << <ISA_LIT>RegisterInfo :: getRegisterNumbering ( RI . getFrameRegister ( * MF ) ) ) ; if ( MFI -> hasCalls ( ) ) CPUBitmask |= ( <NUM_LIT> << <ISA_LIT>RegisterInfo :: getRegisterNumbering ( RI . getRARegister ( ) ) ) ; O << <STR_LIT> ; printHex32 ( CPUBitmask ) ; O << ',' << <ISA_LIT>FI -> getCPUTopSavedRegOff ( ) << '\n' ; O << <STR_LIT> ; printHex32 ( FPUBitmask ) ; O << <STR_LIT> << <ISA_LIT>FI ->


<s> case <STR_LIT> : case <STR_LIT> : { const TargetFrameLowering * TFI = MF . getSubtarget ( ) . getFrameLowering ( ) ; return <NUM_LIT> - TFI -> hasFP ( MF ) ; } case <STR_LIT> : { const TargetFrameLowering * TFI = MF . getSubtarget ( ) . getFrameLowering ( ) ; return <NUM_LIT> - TFI -> hasFP ( MF ) ; } case <STR_LIT> : return <NUM_LIT>


( __v2df ) _mm_setzero_pd ( ) , ( __mmask8 ) - <NUM_LIT> ) ;


<s> return ( int32x4_t ) __builtin_aarch64_addhn2v2di ( __a ,


<s> unsigned <ISA_LIT>InstrInfo :: insertBranch ( MachineBasicBlock & MBB , MachineBasicBlock * TBB , MachineBasicBlock * FBB , ArrayRef < MachineOperand > Cond , const DebugLoc & DL , int * BytesAdded ) const { assert ( ! BytesAdded && <STR_LIT> ) ; if ( Cond . empty ( ) ) { if ( ! TBB ) return <NUM_LIT> ; BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addMBB ( TBB ) ; return <NUM_LIT> ; } assert ( Cond . size ( ) == <NUM_LIT> && <STR_LIT> ) ; if ( Cond [ <NUM_LIT> ] . getImm ( ) ) { BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addMBB ( TBB ) . add ( Cond [ <NUM_LIT> ] ) ; } else


<s> unsigned int fcode = DECL_FUNCTION_CODE ( fndecl ) ; switch ( fcode ) { case IA64_BUILTIN_BSP : if ( ! target || ! register_operand ( target , DImode ) ) target = gen_reg_rtx ( DImode ) ; emit_insn ( gen_bsp_value ( target ) ) ; target = convert_memory_address ( ptr_mode , target ) ; return target ; case IA64_BUILTIN_FLUSHRS : emit_insn ( gen_flushrs ( ) ) ; return const0_rtx ; case IA64_BUILTIN_INFQ : case IA64_BUILTIN_HUGE_VALQ : { machine_mode target_mode = TYPE_MODE ( TREE_TYPE ( exp ) ) ; REAL_VALUE_TYPE inf ; rtx tmp ; real_inf ( & inf ) ; tmp = CONST_DOUBLE_FROM_REAL_VALUE ( inf , target_mode ) ; tmp = validize_mem ( force_const_mem ( target_mode , tmp ) ) ; if ( target == <NUM_LIT> ) target = gen_reg_rtx ( target_mode ) ; emit_move_insn ( target , tmp ) ; return target ; } case IA64_BUILTIN_FABSQ : case IA64_BUILTIN_COPYSIGNQ


<s> int Index = Base + M ; assert ( ( Index >= <NUM_LIT> && ( unsigned ) Index < RawMask . size ( ) ) && <STR_LIT> ) ; ShuffleMask . push_back (


<s> AFI = Fn . getInfo < <ISA_LIT>FunctionInfo > ( ) ; TII = static_cast < const Thumb2InstrInfo * > ( TM . getInstrInfo ( ) ) ; TRI = TM . getRegisterInfo ( ) ; restrictIT = TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . restrictIT ( ) ; if ( ! AFI -> isThumbFunction ( ) ) return false ; bool Modified = false ; for ( MachineFunction :: iterator MFI = Fn . begin ( ) , E = Fn . end ( ) ; MFI != E ; ) { MachineBasicBlock & MBB = * MFI ; ++ MFI ; Modified |= InsertITInstructions


<s> __vector signed int c ; __vector signed int zero = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; a = ( __vector signed short ) vec_splats ( __m1 ) ; b = ( __vector signed short ) vec_splats ( __m2 ) ; c = vec_vmsumshm ( a , b , zero ) ; return ( __builtin_unpack_vector_int128 ( ( __vector __int128_t ) c , <NUM_LIT> )


<s> BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) , Ws1 ) . addImm ( <NUM_LIT> ) ; BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) , Ws2 ) . addReg ( Ws1 ) ; BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) , MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( Ws2 ) . addReg ( MI ->

getOperand ( <NUM_LIT> ) . getReg ( ) ) ;


<s> for ( unsigned i = StartIdx ; i < MI -> getNumOperands ( ) ; ++ i ) { MachineOperand & MO = MI -> getOperand ( i ) ; if ( std :: find ( Ops . begin ( ) , Ops . end ( ) , i ) != Ops . end ( ) ) { MIB . addOperand ( MachineOperand :: CreateImm ( StackMaps :: IndirectMemRefOp ) ) ; MIB . addOperand ( MachineOperand :: CreateFI


<s> if ( lookup_attribute ( <STR_LIT> , DECL_ATTRIBUTES ( current_function_decl ) ) && !


<s> CCAssignFn * <ISA_LIT>CallLowering :: CCAssignFnForCall ( CallingConv :: ID CC , bool IsVarArg ) const { return CC_<ISA_LIT>


<s> return ( VT . isScalarInteger ( ) && TLI -> isTypeLegal ( VT


<s> void addHiImm16Operands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT> ) ; if ( const MCConstantExpr * ConstExpr = dyn_cast < MCConstantExpr > ( getImm ( ) ) ) Inst . addOperand ( MCOperand :: createImm ( ConstExpr -> getValue ( ) >> <NUM_LIT> ) ) ; else if ( isa < <ISA_LIT>MCExpr > ( getImm ( ) ) ) { const <ISA_LIT>MCExpr * SymbolRefExpr = dyn_cast < <ISA_LIT>MCExpr > ( getImm ( ) ) ; assert ( SymbolRefExpr && SymbolRefExpr -> getKind ( ) == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_ABS_HI ) ; Inst . addOperand ( MCOperand :: createExpr ( getImm ( ) ) ) ; } else if ( isa < MCBinaryExpr > ( getImm ( ) ) ) { const MCBinaryExpr * BinaryExpr = dyn_cast < MCBinaryExpr > ( getImm


<s> StringRef getVType ( SmallString < <NUM_LIT> > & Buf ) const { assert ( Kind == KindTy :: VType && <STR_LIT> ) ; Buf . append ( getSEWStr ( VType . Sew ) ) ; Buf . append ( <STR_LIT> ) ; Buf . append ( getLMULStr ( VType . Lmul ) ) ; return Buf . str


<s> SDValue Disp = DAG . getTargetConstant ( <NUM_LIT> , dl , <STR_LIT> ) ; SDValue Segment = DAG . getRegister ( <NUM_LIT> , <STR_LIT> ) ; EVT MaskVT = <STR_LIT> ( <STR_LIT> , Index . getSimpleValueType ( ) . getVectorNumElements ( ) ) ; SDValue MaskInReg ; ConstantSDNode * MaskC = dyn_cast < ConstantSDNode > ( Mask ) ; if ( MaskC ) MaskInReg = DAG . getTargetConstant ( MaskC -> getSExtValue (


<s> bool <ISA_LIT>MCInstrInfo :: hasExtenderForIndex ( MCInst const & MCB , size_t Index ) { return extenderForIndex ( MCB , Index ) !=


<s> break ; case VOIDmode : case QImode : case HImode : case SImode : regbase = GP_ARG_FIRST ; break ; case DImode : cum -> arg_words += ( cum -> arg_words & <NUM_LIT> ) ; regbase = GP_ARG_FIRST ; break ; case TImode : cum -> arg_words += ( cum -> arg_words & <NUM_LIT> ) ; regbase = GP_ARG_FIRST ; break ; } if ( * arg_words >= ( unsigned ) MAX_ARGS_IN_REGISTERS ) { if ( TARGET_DEBUG_D_MODE ) fprintf ( stderr , <STR_LIT> , struct_p ? <STR_LIT> : <STR_LIT> ) ; ret = <NUM_LIT> ; } else { gcc_assert ( regbase != - <NUM_LIT> ) ; if ( ! type || TREE_CODE ( type ) != RECORD_TYPE || ! named || ! TYPE_SIZE_UNIT ( type ) || ! tree_fits_uhwi_p ( TYPE_SIZE_UNIT ( type ) ) ) ret = gen_rtx_REG ( mode , regbase + * arg_words + bias ) ; else { tree field ; for ( field = TYPE_FIELDS ( type ) ; field ; field = DECL_CHAIN ( field ) ) if ( TREE_CODE ( field ) == FIELD_DECL && TREE_CODE ( TREE_TYPE ( field ) ) == REAL_TYPE && TYPE_PRECISION ( TREE_TYPE ( field ) ) == BITS_PER_WORD && tree_fits_shwi_p ( bit_position ( field ) ) && int_bit_position ( field ) % BITS_PER_WORD == <NUM_LIT> ) break ; if ( ! field || mode == DFmode ) ret = gen_rtx_REG ( mode , regbase + * arg_words + bias ) ; else { unsigned int chunks ; HOST_WIDE_INT bitpos ; unsigned int regno ; unsigned int i ; chunks = tree_to_uhwi ( TYPE_SIZE_UNIT ( type ) ) / UNITS_PER_WORD ; if ( chunks + * arg_words + bias > ( unsigned ) MAX_ARGS_IN_REGISTERS ) chunks = MAX_ARGS_IN_REGISTERS - * arg_words - bias ; ret = gen_rtx_PARALLEL ( mode , rtvec_alloc ( chunks ) ) ; bitpos = <NUM_LIT> ; regno = regbase + * arg_words + bias ; field = TYPE_FIELDS ( type ) ; for ( i = <NUM_LIT> ; i <


<s> SDValue Idx = Op . getNode ( ) -> getOperand ( <NUM_LIT> ) ; if ( Op . getNode ( ) -> getValueType ( <NUM_LIT> ) . getSizeInBits ( ) == <NUM_LIT> && SubVec . getNode ( ) -> getValueType ( <NUM_LIT> ) .


<s> TII = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getInstrInfo ( ) ; SmallVector < MachineInstr * , <NUM_LIT> > ToErase ; for ( auto & MBB : MF ) { for ( auto & MI : MBB ) { if ( MI . getOpcode ( ) != <STR_LIT> ) continue ; MachineInstr * ZExt = nullptr ; for ( auto & Use : MRI -> use_instructions ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ) if ( Use . getOpcode ( ) == <STR_LIT> ) ZExt = & Use ; if ( ! ZExt ) continue ; MachineInstr * FlagsDefMI = findFlagsImpDef ( MI . getParent ( ) , MachineBasicBlock :: reverse_iterator ( & MI ) ) ; if ( ! FlagsDefMI ) continue ; if ( impUsesFlags ( FlagsDefMI ) ) continue ; ++ NumSubstZexts ; Changed = true ; const TargetRegisterClass * RC = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . is64Bit ( ) ? & <STR_LIT> : & <STR_LIT> ; Register ZeroReg = MRI -> createVirtualRegister ( RC ) ; Register InsertReg = MRI -> createVirtualRegister ( RC ) ; BuildMI ( MBB , FlagsDefMI , MI . getDebugLoc ( ) , TII ->


<s> case E_QImode : gen = gen_aarch64_atomic_casqi ; break ; case E_HImode : gen = gen_aarch64_atomic_cashi ; break ; case E_SImode : gen = gen_aarch64_atomic_cassi ; break ; case E_DImode : gen = gen_aarch64_atomic_casdi ; break ; default : gcc_unreachable ( ) ; } emit_insn ( gen_rtx_SET ( rval , expected ) ) ; emit_insn ( gen ( rval , mem , desired


<s> static inline void vec_ste ( vec_float4 a , int b , float * c ) { vec_ste ( ( vec_uint4 ) ( a ) , b , (


<s> if ( ! UseContinueLogical ) { int BranchOpcode = TrueBranch == ContMBB ? getBranchNzeroOpcode ( OldOpcode ) : getBranchZeroOpcode ( OldOpcode ) ; insertCondBranchBefore ( I , BranchOpcode , DL ) ; insertInstrEnd ( ContingMBB , <STR_LIT> , DL ) ; insertInstrEnd ( ContingMBB , <STR_LIT> , DL ) ; } else { int BranchOpcode = TrueBranch == ContMBB ? getContinueNzeroOpcode ( OldOpcode ) : getContinueZeroOpcode ( OldOpcode ) ; insertCondBranchBefore ( I , BranchOpcode , DL ) ; } MI -> eraseFromParent ( )


<s> rtx mask = gen_reg_rtx ( V4SImode ) ; rtx bi = gen_reg_rtx ( SImode ) ; static unsigned char const shufa [ <NUM_LIT> ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; static unsigned char const insna [ <NUM_LIT> ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , STATIC_CHAIN_REGNUM , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , STATIC_CHAIN_REGNUM } ; shufc = force_reg ( TImode , array_to_constant ( TImode , shufa ) ) ; insnc = force_reg ( V4SImode , array_to_constant ( V4SImode , insna ) ) ; emit_insn ( gen_shufb ( shuf , fnaddr , cxt , shufc ) ) ; emit_insn ( gen_vrotlv4si3 ( rotl , shuf , spu_const ( V4SImode , <NUM_LIT>


<s> const char * suffix = <STR_LIT> ; switch ( ( sz << <NUM_LIT> ) | ( regi % <NUM_LIT> ) ) { case ( <NUM_LIT> << <NUM_LIT> ) | <NUM_LIT> : suffix = <STR_LIT> ; break ; case ( <NUM_LIT> << <NUM_LIT> ) | <NUM_LIT> : suffix = <STR_LIT> ; break ; case ( <NUM_LIT> << <NUM_LIT> ) | <NUM_LIT> : suffix = <STR_LIT> ; break ; case ( <NUM_LIT> << <NUM_LIT> ) | <NUM_LIT> : suffix = <STR_LIT> ; break ; case ( <NUM_LIT> << <NUM_LIT> ) | <NUM_LIT> : suffix = <STR_LIT> ; break ; case ( <NUM_LIT> << <NUM_LIT> ) | <NUM_LIT> : suffix = <STR_LIT> ; break ; case ( <NUM_LIT> << <NUM_LIT> ) | <NUM_LIT> : suffix = <STR_LIT> ; break ; case ( <NUM_LIT> << <NUM_LIT> ) | <NUM_LIT> : suffix = <STR_LIT> ; break ; default : continue ; } sprintf ( & canon_reg_names [ speci ] [ regi ] [ <NUM_LIT> ] , <STR_LIT> , regi / <NUM_LIT> , suffix ) ; } } switch ( GET_MODE_SIZE ( GET_MODE ( op ) ) ) { case <NUM_LIT> : speci = <NUM_LIT> ;


<s> value * merge_cells ( value * cl1 , value * cl2 ) const { auto b1 = std :: get < cell > ( * cl1 ) . b ; auto b2 = std :: get < cell > ( *


<s> } if ( Subtarget . usesFunctionDescriptors ( ) && ! hasNest ) Ops . push_back ( DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ) ; if ( isTailCall ) Ops . push_back ( DAG . getRegister ( Is<ISA_LIT>64 ? <STR_LIT> : <STR_LIT> , RegVT ) ) ; } if ( isTailCall ) Ops . push_back ( DAG . getConstant ( SPDiff , dl , <STR_LIT> ) ) ; for ( unsigned i = <NUM_LIT> , e = RegsToPass . size ( ) ; i != e ; ++ i ) Ops . push_back ( DAG . getRegister ( RegsToPass [ i ] . first , RegsToPass [ i ] . second . getValueType ( ) ) ) ; if ( ( Subtarget . is64BitELFABI ( ) || Subtarget . isAIXABI ( ) ) && ! isPatchPoint ) Ops . push_back ( DAG . getRegister ( Is<ISA_LIT>64 ? <STR_LIT> : <STR_LIT> , RegVT ) ) ; if ( isVarArg && Subtarget . is32BitELFABI ( ) ) Ops . push_back ( DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ) ; const TargetRegisterInfo * TRI = Subtarget . getRegisterInfo ( ) ; const uint32_t * Mask = TRI -> getCallPreservedMask ( DAG . getMachineFunction (


<s> return <STR_LIT> ( MI -> getOpcode ( ) , <STR_LIT>


<s> } break ; case Instruction :: Mul : if ( Idx == <NUM_LIT> && Imm . getBitWidth ( ) <= <NUM_LIT> ) { if ( isInt < <NUM_LIT> > ( Imm . getSExtValue ( ) ) ) return TTI :: TCC_Free ; } break ; case Instruction :: Or : case Instruction :: Xor : if ( Idx == <NUM_LIT> && Imm . getBitWidth ( ) <= <NUM_LIT> ) { if ( isUInt < <NUM_LIT> > ( Imm . getZExtValue ( ) ) ) return TTI :: TCC_Free ; if ( ( Imm . getZExtValue ( ) & <NUM_LIT> ) == <NUM_LIT> ) return TTI :: TCC_Free ; } break ; case Instruction :: And : if ( Idx == <NUM_LIT> && Imm . getBitWidth ( ) <= <NUM_LIT> ) { if ( BitSize <= <NUM_LIT> ) return TTI :: TCC_Free ; if ( isUInt < <NUM_LIT> > ( ~ Imm . getZExtValue ( ) ) ) return TTI :: TCC_Free ; if ( ( Imm . getZExtValue ( ) & <NUM_LIT> ) == <NUM_LIT> ) return TTI :: TCC_Free ; const <ISA_LIT>InstrInfo * TII = ST -> getInstrInfo ( ) ; unsigned Start , End ; if ( TII -> isRxSBGMask ( Imm . getZExtValue ( ) , BitSize , Start , End ) ) return TTI :: TCC_Free ; } break ; case Instruction :: Shl : case Instruction :: LShr : case Instruction :: AShr


<s> return new <ISA_LIT>PassConfig ( this ,


<s> int avr_hard_regno_mode_ok ( int regno , machine_mode mode ) { if ( GET_MODE_SIZE ( mode ) == <NUM_LIT> ) return <NUM_LIT> ; if ( GET_MODE_SIZE ( mode ) >= <NUM_LIT> && regno >= REG_X


<s> if ( ( ImmVal & SupportedMask ) != ImmVal ) { return SelectCode ( N ) ; } uint64_t LoMask = <NUM_LIT> ; uint64_t HiMask = <NUM_LIT> ; uint64_t ImmLo = ( ImmVal & LoMask ) ; uint64_t ImmHi = ( ImmVal & HiMask ) ; SDValue ConstLo = CurDAG -> getTargetConstant ( ImmLo , <STR_LIT> ) ; MachineSDNode * Move = CurDAG -> getMachineNode ( <STR_LIT> , N , <STR_LIT> , ConstLo ) ; if ( ImmHi ) { SDValue ConstHi = CurDAG -> getTargetConstant (


<s> void <ISA_LIT>InstPrinter :: printBrigMachineModel ( const MCInst * MI ,


<s> if ( getLexer ( ) . isNot ( AsmToken :: LParen ) ) { if ( HasDisplacement ) { MemOp . Op = <STR_LIT> :: Addr ; Operands . push_back ( <ISA_LIT>Operand :: createMemOp ( MemOp , Start , getLexer ( ) . getLoc ( ) ) ) ; return MatchOperand_Success ; } else if ( IsPD ) { Error ( getLexer ( ) . getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ; } return MatchOperand_NoMatch ; } Parser . Lex ( ) ; if ( ! HasDisplacement && isExpr ( ) ) { if ( Parser . parseExpression ( MemOp . OuterDisp ) ) { return MatchOperand_ParseFail ; } HasDisplacement = true ; if ( getLexer ( ) . isNot ( AsmToken :: Comma ) ) { MemOp . Op = <STR_LIT> :: Addr ; Operands . push_back ( <ISA_LIT>Operand :: createMemOp ( MemOp , Start , getLexer ( ) . getLoc ( ) ) ) ; return MatchOperand_Success ; } Parser . Lex ( ) ; } Result = parseRegister ( MemOp . OuterReg ) ; if ( Result == MatchOperand_ParseFail ) { return MatchOperand_ParseFail ; } if ( Result != MatchOperand_Success ) { Error ( getLexer ( ) . getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ; } bool HasIndex = false ; if ( Parser . getTok ( ) . is ( AsmToken :: Comma ) ) { Parser . Lex ( ) ; Result = parseRegister ( MemOp . InnerReg ) ; if ( Result == MatchOperand_ParseFail ) { return Result ; } if ( Result == MatchOperand_NoMatch ) { Error ( getLexer ( ) . getLoc ( ) , <STR_LIT> ) ; return


<s> EVT OutSVT = OutVT . getVectorElementType ( ) ; EVT InSVT = InVT . getVectorElementType ( ) ; if ( ! ( ( InSVT == <STR_LIT> || InSVT == <STR_LIT> || InSVT == <STR_LIT> ) && ( OutSVT == <STR_LIT> || OutSVT == <STR_LIT> ) && isPowerOf2_32 ( NumElems ) && NumElems >= <NUM_LIT> ) ) return SDValue ( ) ; if ( Subtarget . hasSSSE3 ( ) && NumElems == <NUM_LIT> && ( ( OutSVT == <STR_LIT> && InSVT != <STR_LIT> ) || ( InSVT == <STR_LIT> && OutSVT == <STR_LIT> ) ) ) return SDValue ( ) ; SDLoc DL ( N ) ; if ( Subtarget . hasSSE41 ( ) || OutSVT == <STR_LIT> ) return combineVectorTruncationWithPACKUS ( N , DL , Subtarget , DAG ) ; if ( InSVT == <STR_LIT> ) return combineVectorTruncationWithPACKSS (


<s> unsigned IntNo = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; SDLoc dl ( Op ) ; switch ( IntNo ) { default : return SDValue ( ) ; case <STR_LIT> : case <STR_LIT> : { EVT PtrVT = DAG . getTargetLoweringInfo ( ) . getPointerTy ( ) ; return DAG . getNode ( <STR_LIT> , dl , PtrVT ) ; } case <STR_LIT> : { MachineFunction & MF = DAG . getMachineFunction ( ) ; <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; unsigned <ISA_LIT>PCLabelIndex = AFI -> createPICLabelUId ( ) ; EVT PtrVT = getPointerTy ( ) ; Reloc :: Model RelocM = getTargetMachine ( ) . getRelocationModel ( ) ; SDValue CPAddr ; unsigned PCAdj = ( RelocM != Reloc :: PIC_ ) ? <NUM_LIT> : ( Subtarget -> isThumb ( ) ? <NUM_LIT> : <NUM_LIT> ) ; <ISA_LIT>ConstantPoolValue * CPV = <ISA_LIT>ConstantPoolConstant :: Create ( MF . getFunction ( ) , <ISA_LIT>PCLabelIndex , <STR_LIT> , PCAdj ) ; CPAddr = DAG . getTargetConstantPool ( CPV , PtrVT , <NUM_LIT> ) ; CPAddr = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , CPAddr ) ; SDValue Result = DAG . getLoad ( PtrVT , dl , DAG . getEntryNode ( ) , CPAddr , MachinePointerInfo :: getConstantPool (

) , false , false , false , <NUM_LIT> ) ;


<s> if ( getParser ( ) . parseExpression ( Value ) ) { Parser . eatToEndOfStatement ( ) ; return false ; } getParser ( ) . getStreamer ( ) . EmitValue ( Value , Size ) ; if ( getLexer ( ) . is ( AsmToken :: EndOfStatement ) ) break ; if ( getLexer ( ) . isNot (


<s> static std :: unique_ptr < <ISA_LIT>Operand > CreateToken ( StringRef Str , SMLoc Loc , bool HasExplicitEncodingSize = true ) { auto Res = llvm :: make_unique < <ISA_LIT>Operand > ( Token


<s> case <STR_LIT> : break ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return


<s> void setVarArgsFrameIndex ( int idx ) { VarArgsFrameIndex =


<s> const MCOperand & Offset = MI -> getOperand ( OpNo + <NUM_LIT> ) ; if ( WithPreDec ) { O << '-' ; } if ( Base . getReg ( ) ) { printRegister ( Base . getReg ( ) , O ) ; } if ( WithPostInc ) { O << '+'


<s> unsigned Lmul = Imm & <NUM_LIT> ; Sew = <NUM_LIT> << ( Sew + <NUM_LIT> ) ; Lmul = <NUM_LIT> << Lmul ; Ediv = <NUM_LIT> << Ediv ; O << <STR_LIT> <<


<s> bool isReg ( ) const override { return isRegKind ( ) && ! hasModifiers


<s> addPass ( create<ISA_LIT>ISelDag ( get<ISA_LIT>TargetMachine ( ) ) ) ; return false


<s> static MCRegister convertFPR64ToFPR32 ( MCRegister Reg ) { assert ( Reg >= <STR_LIT> &&


<s> unsigned int count = ( high - low ) + <NUM_LIT> ; rtx vector ; vector = gen_rtx_PARALLEL ( VOIDmode , rtvec_alloc ( count ) ) ; XVECEXP ( vector , <NUM_LIT> , <NUM_LIT> ) = gen_rtx_SET ( VOIDmode , stack_pointer_rtx , plus_constant ( Pmode , stack_pointer_rtx

, ( count - <NUM_LIT> ) * UNITS_PER_WORD ) ) ;


<s> unsigned <ISA_LIT>RegisterInfo :: getRARegister


<s> case H8OP_REGISTER : return <NUM_LIT> ; case H8OP_MEM_BASE : return ( size == <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ) ; case H8OP_MEM_ABSOLUTE : return operand_length + ( size == <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ) ; case H8OP_MEM_COMPLEX : return operand_length + <NUM_LIT> ; default : gcc_unreachable ( ) ; } } static unsigned int h8300_short_immediate_length ( rtx op ) { enum h8300_operand_class class ; unsigned int size , operand_length ; size = GET_MODE_SIZE ( GET_MODE


<s> if ( Constant * Mask = dyn_cast < Constant > ( II . getArgOperand ( <NUM_LIT> ) ) ) { assert ( cast < FixedVectorType > ( Mask -> getType ( ) ) -> getNumElements ( ) == <NUM_LIT> && <STR_LIT> ) ; bool AllEltsOk = true ; for ( unsigned i = <NUM_LIT> ; i != <NUM_LIT> ; ++ i ) { Constant * Elt = Mask -> getAggregateElement ( i ) ; if ( ! Elt || ! ( isa < ConstantInt > ( Elt ) || isa < UndefValue > ( Elt ) ) ) { AllEltsOk = false ; break ; } } if ( AllEltsOk ) { Value * Op0 = IC . Builder . CreateBitCast ( II . getArgOperand ( <NUM_LIT> ) , Mask -> getType ( ) ) ; Value * Op1 = IC . Builder . CreateBitCast ( II . getArgOperand ( <NUM_LIT> ) , Mask -> getType ( ) ) ; Value * Result = UndefValue :: get ( Op0 -> getType ( ) ) ; Value * ExtractedElts [ <NUM_LIT> ] ; memset ( ExtractedElts , <NUM_LIT> , sizeof ( ExtractedElts ) ) ; for ( unsigned i = <NUM_LIT> ; i != <NUM_LIT> ; ++ i ) { if ( isa < UndefValue > ( Mask -> getAggregateElement ( i ) ) ) continue ; unsigned Idx = cast < ConstantInt > ( Mask -> getAggregateElement ( i ) ) -> getZExtValue ( ) ; Idx &= <NUM_LIT> ; if ( DL . isLittleEndian ( ) ) Idx


<s> if ( Lo_32 ( ImmOp64 ) == <NUM_LIT> ) { if ( TmpReg != <STR_LIT> && loadImmediate ( ImmOp32 , TmpReg , <STR_LIT> , true , false , IDLoc , Out , STI ) ) return true ; TOut . emitRR ( <STR_LIT> , FirstReg , TmpReg , IDLoc , STI ) ; return false ; } MCSection * CS = getStreamer ( ) . getCurrentSectionOnly ( ) ; MCSection * ReadOnlySection = getContext ( ) . getELFSection ( <STR_LIT> , ELF :: SHT_PROGBITS , ELF :: SHF_ALLOC ) ; MCSymbol * Sym = getContext ( ) . createTempSymbol ( ) ; const MCExpr * LoSym = MCSymbolRefExpr :: create ( Sym , MCSymbolRefExpr :: VK_None , getContext ( ) ) ; const <ISA_LIT>MCExpr * LoExpr = <ISA_LIT>MCExpr :: create ( <ISA_LIT>MCExpr :: MEK_LO , LoSym , getContext ( ) ) ; getStreamer ( ) . SwitchSection ( ReadOnlySection ) ; getStreamer ( ) . EmitLabel ( Sym , IDLoc ) ; getStreamer ( ) . EmitIntValue ( ImmOp32 , <NUM_LIT> ) ; getStreamer ( ) . SwitchSection ( CS ) ; if ( emitPartialAddress ( TOut , IDLoc


<s> assert ( AddendDef . getOperand ( i ) . isReg ( ) ) ; MachineOperand PHISrcOp = AddendDef . getOperand ( i ) ; MachineInstr & PHISrcInst = * MRI . def_instr_begin ( PHISrcOp . getReg ( ) ) ; if ( & PHISrcInst == MI ) { unsigned NewFMAOpc = <NUM_LIT> ; switch ( MI -> getOpcode ( ) ) { case <STR_LIT> : NewFMAOpc = <STR_LIT> ; break ; case <STR_LIT> : NewFMAOpc = <STR_LIT> ; break ; case <STR_LIT> : NewFMAOpc = <STR_LIT> ; break ; case <STR_LIT> : NewFMAOpc = <STR_LIT> ; break ; case <STR_LIT> : NewFMAOpc = <STR_LIT> ; break ; case <STR_LIT> : NewFMAOpc = <STR_LIT> ; break ; case <STR_LIT> : NewFMAOpc = <STR_LIT> ; break ; case <STR_LIT> : NewFMAOpc = <STR_LIT> ; break ; case <STR_LIT> : NewFMAOpc = <STR_LIT> ; break ; case <STR_LIT> : NewFMAOpc = <STR_LIT> ; break ; case <STR_LIT> : NewFMAOpc = <STR_LIT> ; break ; case <STR_LIT> : NewFMAOpc = <STR_LIT> ; break ; case <STR_LIT> : NewFMAOpc = <STR_LIT> ; break ; case <STR_LIT> : NewFMAOpc = <STR_LIT> ; break ; case <STR_LIT> : NewFMAOpc = <STR_LIT> ; break ; case <STR_LIT> : NewFMAOpc = <STR_LIT> ; break ; case <STR_LIT> : NewFMAOpc = <STR_LIT> ; break ; case <STR_LIT> : NewFMAOpc = <STR_LIT> ; break ; case <STR_LIT> : NewFMAOpc = <STR_LIT> ; break ; case <STR_LIT> : NewFMAOpc = <STR_LIT> ; break ; case <STR_LIT> : NewFMAOpc = <STR_LIT> ; break ; case <STR_LIT> : NewFMAOpc = <STR_LIT> ; break ; case <STR_LIT> : NewFMAOpc = <STR_LIT> ; break ; case <STR_LIT> : NewFMAOpc = <STR_LIT> ; break ; case <STR_LIT> : NewFMAOpc = <STR_LIT> ; break ; case <STR_LIT> : NewFMAOpc = <STR_LIT> ; break ; case <STR_LIT> : NewFMAOpc = <STR_LIT> ; break ; case <STR_LIT> : NewFMAOpc = <STR_LIT> ; break ; case <STR_LIT> : NewFMAOpc = <STR_LIT> ; break ; case <STR_LIT> : NewFMAOpc = <STR_LIT> ; break ; case <STR_LIT> : NewFMAOpc = <STR_LIT> ; break ; case <STR_LIT> : NewFMAOpc = <STR_LIT> ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } const TargetInstrInfo & TII = *


<s> case '5' : return <NUM_LIT> ; case '6' : return <NUM_LIT> ; case '7' : return <NUM_LIT> ; case '8' : return <NUM_LIT> ; case '9' : return <NUM_LIT> ; } break ; case <NUM_LIT> : if ( Name [ <NUM_LIT> ] != CoprocOp || Name [ <NUM_LIT> ] != '1' ) return - <NUM_LIT> ; switch ( Name [ <NUM_LIT> ] ) { default : return - <NUM_LIT> ; case '0' : return <NUM_LIT> ; case '1' : return <NUM_LIT> ; case '2' : return <NUM_LIT> ; case '3' :


<s> uint64_t ArgOffset = alignTo ( ExplicitArgOffset , ABIAlign ) + BaseOffset ; ExplicitArgOffset = alignTo ( ExplicitArgOffset , ABIAlign ) + AllocSize ; ArrayRef < Register > OrigArgRegs = VRegs [ i ] ; Register ArgReg = OrigArgRegs . size ( ) == <NUM_LIT> ? OrigArgRegs [ <NUM_LIT> ] : MRI . createGenericVirtualRegister ( getLLTForType ( * ArgTy , DL ) ) ; unsigned Align = MinAlign ( KernArgBaseAlign , ArgOffset ) ; ArgOffset = alignTo ( ArgOffset , DL . getABITypeAlignment ( ArgTy ) ) ; lowerParameter ( MIRBuilder , ArgTy , ArgOffset , Align , ArgReg ) ; if ( OrigArgRegs . size ( ) > <NUM_LIT> ) unpackRegs ( OrigArgRegs , ArgReg , ArgTy ,


<s> SDLoc dl ( Op ) ; EVT VT = Op . getValueType ( ) ; SDValue TVal = DAG . getConstant ( <NUM_LIT> , VT ) ; SDValue FVal = DAG . getConstant ( <NUM_LIT> , VT ) ; if ( LHS . getValueType ( ) == <STR_LIT> ) { softenSetCCOperands ( DAG , <STR_LIT> , LHS , RHS , CC , dl ) ; if ( ! RHS . getNode ( ) ) { assert ( LHS . getValueType ( ) == Op . getValueType ( ) && <STR_LIT> ) ; return LHS ; } } if ( LHS . getValueType ( ) . isInteger ( ) ) { SDValue CCVal ; SDValue Cmp = get<ISA_LIT>Cmp ( LHS , RHS , <STR_LIT> ( CC , true ) , CCVal , DAG , dl ) ; return DAG . getNode ( <STR_LIT> , dl , VT , FVal , TVal , CCVal , Cmp ) ; } assert ( LHS . getValueType ( ) == <STR_LIT> || LHS . getValueType ( ) == <STR_LIT> ) ; SDValue Cmp = emitComparison ( LHS , RHS , CC , dl , DAG ) ; <STR_LIT> CC1 , CC2 ; changeFPCCTo<ISA_LIT>CC ( CC , CC1 , CC2 ) ; if ( CC2 == <STR_LIT> ) { changeFPCCTo<ISA_LIT>CC ( <STR_LIT> ( CC , false ) , CC1 , CC2 ) ; SDValue CC1Val = DAG . getConstant ( CC1 , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , VT , FVal , TVal , CC1Val , Cmp ) ; } else


<s> bool <ISA_LIT>FastISel :: <ISA_LIT>SelectLoad ( const Instruction * I ) { MVT VT ; if ( ! isTypeLegal ( I -> getType ( ) , VT , true ) ) return false ; <ISA_LIT>AddressMode AM ; if ( ! <ISA_LIT>SelectAddress ( I -> getOperand ( <NUM_LIT> ) , AM ) ) return false ; unsigned ResultReg = <NUM_LIT> ; if ( <ISA_LIT>FastEmitLoad ( VT , AM


<s> if ( tryInlineAsm ( N ) ) return ; break ; } case <STR_LIT> : ReplaceNode ( N , getGlobalBaseReg ( ) ) ; return ; case <STR_LIT> : case <STR_LIT> : { if ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT> ) break ; SDValue DivLHS = N -> getOperand ( <NUM_LIT> ) ; SDValue DivRHS = N -> getOperand ( <NUM_LIT> ) ; SDValue TopPart ; if ( N -> getOpcode ( ) == <STR_LIT> ) { TopPart = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , DivLHS , CurDAG -> getTargetConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) , <NUM_LIT> ) ; } else


<s> if ( mode == V2HImode ) return D_REGNO_P ( regno ) ; if ( class == CCREGS ) return mode == BImode ; if ( mode == PDImode ) return regno ==


<s> auto & ArgUsageInfo = DAG . getPass ( ) -> getAnalysis < <ISA_LIT>ArgumentUsageInfo > ( ) ; const <ISA_LIT>FunctionArgInfo & CalleeArgInfo = ArgUsageInfo . lookupFuncArgInfo ( * CalleeFunc ) ; const <ISA_LIT>FunctionArgInfo & CallerArgInfo = Info . getArgInfo ( ) ; <STR_LIT> InputRegs [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; for ( auto InputID : InputRegs ) { const ArgDescriptor * OutgoingArg ; const TargetRegisterClass * ArgRC ; std :: tie ( OutgoingArg , ArgRC ) = CalleeArgInfo . getPreloadedValue ( InputID ) ; if ( ! OutgoingArg ) continue ; const ArgDescriptor * IncomingArg ; const TargetRegisterClass * IncomingArgRC ; std :: tie ( IncomingArg , IncomingArgRC ) = CallerArgInfo . getPreloadedValue ( InputID ) ; assert ( IncomingArgRC == ArgRC ) ; EVT ArgVT = TRI -> getSpillSize ( * ArgRC ) == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; SDValue InputReg


<s> return std :: make_unique < <ISA_LIT>ELFObjectWriter >


<s> int64_t Value = MI -> getOperand ( OpNum ) . getImm ( ) ; assert ( isInt < <NUM_LIT> >


<s> static DecodeStatus DecodeGuestRegs64RegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t , const void * Decoder ) { using namespace <ISA_LIT> ; static const MCPhysReg GuestReg64DecoderTable [ ] = { G1_0 , <NUM_LIT> , G3_2 , <NUM_LIT> , G5_4 , <NUM_LIT> , G7_6 , <NUM_LIT> , G9_8 , <NUM_LIT> , G11_10 , <NUM_LIT> , G13_12 , <NUM_LIT> , G15_14 , <NUM_LIT> , G17_16 , <NUM_LIT> , G19_18 , <NUM_LIT> , G21_20 , <NUM_LIT> , G23_22 , <NUM_LIT> , G25_24 , <NUM_LIT> , G27_26 , <NUM_LIT> , G29_28 , <NUM_LIT> , G31_30 , <NUM_LIT> } ; if ( RegNo >= array_lengthof ( GuestReg64DecoderTable ) ) return MCDisassembler :: Fail ; if ( GuestReg64DecoderTable [ RegNo ] == <STR_LIT> ) return MCDisassembler :: Fail ; unsigned Register = GuestReg64DecoderTable [ RegNo ] ; Inst . addOperand ( MCOperand :: createReg ( Register )


<s> FiTmpOffsetMap . clear ( ) ; SetTmpSize ( <NUM_LIT>


<s> case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case FK_Data_4 : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case FK_Data_8 : return <NUM_LIT> ; case <STR_LIT> : case


<s> return ( uint8x8_t ) ( ( __a & __b )


<s> const MCProcResourceDesc & PRD = * SchedModel -> getProcResource ( PI -> ProcResourceIdx ) ; std :: string FU ( PRD . Name ) ; FU = FU . substr ( FU . find ( <STR_LIT> ) + <NUM_LIT> ) ; FU . resize ( FU . find ( <STR_LIT> ) ) ; OS << <STR_LIT> << FU ; if ( PI -> Cycles > <NUM_LIT> ) OS << <STR_LIT> << PI -> Cycles << <STR_LIT> ; } if ( SC -> NumMicroOps > <NUM_LIT> ) OS << <STR_LIT> << SC -> NumMicroOps << <STR_LIT> ; if ( SC -> BeginGroup && SC -> EndGroup ) OS << <STR_LIT> ; else if ( SC -> BeginGroup


<s> Inst . setOpcode ( <STR_LIT> ) ; break ; } unsigned imm = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; return DecodeMemBarrierOption ( Inst , imm , Address , Decoder ) ; } unsigned brtarget = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ; brtarget |= fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ; brtarget |= fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ; brtarget |= fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ; brtarget |= fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ; if ( ! Check ( S , DecodeT2BROperand ( Inst , brtarget , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodePredicateOperand ( Inst , pred , Address , Decoder ) ) ) return MCDisassembler :: Fail ; return


<s> bool HasBP = RegInfo -> hasBasePointer ( MF ) ; unsigned FrameSize = determineFrameLayout ( MF , false ) ; int NegFrameSize = - FrameSize ; bool IsLargeFrame = ! isInt < <NUM_LIT> > ( NegFrameSize ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; unsigned MaxAlign = MFI . getMaxAlignment


<s> Triple TT ( TM . getTargetTriple ( ) ) ; if ( TT . isOSBinFormatMachO ( ) ) OutStreamer . SwitchSection ( getObjFileLowering ( ) . getTextSection ( ) ) ; if ( TT . isOSBinFormatCOFF ( ) ) { if ( TT . getArch ( ) == Triple :: x86 ) { MCSymbol * S = MMI -> getContext ( ) . GetOrCreateSymbol ( StringRef ( <STR_LIT> ) ) ; OutStreamer . BeginCOFFSymbolDef ( S ) ; OutStreamer . EmitCOFFSymbolStorageClass ( COFF :: IMAGE_SYM_CLASS_STATIC ) ; OutStreamer . EmitCOFFSymbolType ( COFF :: IMAGE_SYM_DTYPE_NULL


<s> if ( AddrReg == <NUM_LIT> ) return false ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) ) . addReg ( AddrReg ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) ) ; const IndirectBrInst * IB = cast < IndirectBrInst > ( I ) ; for ( const BasicBlock * SuccBB : IB -> successors ( ) ) FuncInfo . MBB -> addSuccessor


<s> SDValue DivScale0 = DAG . getNode ( <STR_LIT> , SL , ScaleVT , Y , Y , X ) ; SDValue NegDivScale0 = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , DivScale0 ) ; SDValue Rcp = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , DivScale0 ) ; SDValue Fma0 = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , NegDivScale0 , Rcp , One ) ; SDValue Fma1 = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Rcp , Fma0 , Rcp ) ; SDValue Fma2 = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , NegDivScale0 , Fma1 , One ) ; SDValue DivScale1 = DAG . getNode ( <STR_LIT> , SL , ScaleVT , X , Y , X ) ; SDValue Fma3 = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Fma1 , Fma2 , Fma1 ) ; SDValue Mul = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , DivScale1 , Fma3 ) ; SDValue Fma4 = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , NegDivScale0 , Mul , DivScale1 ) ; SDValue Scale ; if ( Subtarget -> getGeneration ( ) == <ISA_LIT>Subtarget :: SOUTHERN_ISLANDS ) { const SDValue Hi = DAG . getConstant ( <NUM_LIT> , SL , <STR_LIT> ) ; SDValue NumBC = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , X ) ; SDValue DenBC = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Y ) ; SDValue Scale0BC = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , DivScale0 ) ; SDValue Scale1BC = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , DivScale1 ) ; SDValue NumHi = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , NumBC , Hi ) ; SDValue DenHi = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , DenBC , Hi ) ; SDValue Scale0Hi = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Scale0BC , Hi ) ; SDValue Scale1Hi = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Scale1BC , Hi ) ; SDValue CmpDen = DAG . getSetCC ( SL , <STR_LIT> , DenHi , Scale0Hi


<s> const MCOperand & MO = MI . getOperand ( OpNo ) ; if ( MO . isImm ( ) ) return MO . getImm ( ) >> <NUM_LIT> ; assert ( MO . isExpr (


<s> if ( areCFlagsAliveInSuccessors ( CmpInstr -> getParent ( ) ) ) return false ; AccessKind AccessToCheck = AK_Write ; if ( sForm ( * MI ) != MI -> getOpcode ( ) ) AccessToCheck = AK_All ; if ( areCFlagsAccessedBetweenInstrs ( MI , CmpInstr , TRI , AccessToCheck ) ) return false ; UsedNZCV NZCVUsedAfterCmp ; for ( const MachineInstr & Instr : instructionsWithoutDebug ( std :: next ( CmpInstr -> getIterator ( ) ) , CmpInstr -> getParent ( ) -> instr_end ( ) ) ) { if ( Instr . readsRegister ( <STR_LIT> , TRI ) ) { <STR_LIT> CC = findCondCodeUsedByInstr ( Instr ) ; if ( CC ==


<s> unsigned <ISA_LIT>RegisterInfo :: getEHExceptionRegister ( ) const { assert ( <NUM_LIT> && <STR_LIT> ) ; return <NUM_LIT>


<s> int64_t Imm = MI -> getOperand ( Op ) . getImm ( ) ; assert ( ( Imm & <NUM_LIT>


<s> const <ISA_LIT>TargetLowering * getTargetLowering ( ) const { return &


<s> O << ( int16_t ) MI -> getOperand ( OpNum ) . getImm


<s> SExpr * load1 = ctx -> load ( <NUM_LIT> , TRI -> getName ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ) ; SExpr * load2 = ctx -> load ( <NUM_LIT> , TRI -> getName ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ) ; SExpr * andexpr = ctx -> and_ ( <NUM_LIT> , load1 , load2 ) ; SExpr * stor = calcNZCV ( ctx , load1 , load2 , andexpr , ctx -> dec_unsigned ( <NUM_LIT> , <NUM_LIT> ) , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> ) ; alfbb . addStatement ( label , TII -> getName (


<s> Instruction * SVEExpandLibCall :: CreateCall ( <STR_LIT> Id , Type * RetTy , ArrayRef < Value * > Ops ) { auto Callee = <STR_LIT> ( F -> getParent ( ) , Id


<s> virtual unsigned getRelocationInfo ( ) const { return


<s> const Function & Func = MI -> getParent ( ) -> getParent ( ) -> getFunction ( ) ; DiagnosticInfoUnsupported Diag ( Func , Msg , MI -> getDebugLoc


<s> int numArgs = mInstr -> getNumOperands ( ) - <NUM_LIT> ; for ( int i = <NUM_LIT> ; i < numArgs ; ++ i ) argOpers [ i ] = & mInstr -> getOperand ( i + <NUM_LIT> ) ; int lastAddrIndx = <NUM_LIT> ; int valArgIndx = <NUM_LIT> ; unsigned t1 = F -> getRegInfo ( ) . createVirtualRegister ( <STR_LIT> ) ; MachineInstrBuilder MIB = BuildMI ( newMBB , dl , TII -> get ( <STR_LIT> ) , t1 ) ; for ( int i = <NUM_LIT> ; i <= lastAddrIndx ; ++ i ) ( * MIB ) . addOperand ( * argOpers [ i ] ) ; assert ( ( argOpers [ valArgIndx ] -> isReg ( ) || argOpers [ valArgIndx ] -> isImm ( ) ) && <STR_LIT> ) ; unsigned t2 = F -> getRegInfo ( ) . createVirtualRegister ( <STR_LIT> ) ; if ( argOpers [ valArgIndx ] -> isReg ( ) ) MIB = BuildMI ( newMBB , dl , TII -> get ( <STR_LIT> ) , t2 ) ; else MIB = BuildMI ( newMBB , dl , TII -> get ( <STR_LIT> ) , t2 ) ; ( * MIB ) . addOperand ( * argOpers [ valArgIndx ] ) ; MIB = BuildMI ( newMBB , dl , TII -> get ( <STR_LIT>


<s> case k_CondCode : CC = o . CC ; break ; case k_ITCondMask : ITMask = o . ITMask ; break ; case k_Token : Tok = o . Tok ; break ; case k_CCOut : case k_Register : Reg = o . Reg ; break ; case k_RegisterList : case k_DPRRegisterList : case k_SPRRegisterList : Registers = o . Registers ; break ; case k_VectorList : case k_VectorListAllLanes : VectorList = o . VectorList ; break ; case k_CoprocNum : case k_CoprocReg : Cop = o . Cop ; break ; case k_CoprocOption : CoprocOption = o . CoprocOption ; break ; case k_Immediate : Imm = o . Imm ; break ; case k_FPImmediate : FPImm = o . FPImm ; break ; case k_MemBarrierOpt : MBOpt = o . MBOpt ; break ; case k_Memory : Memory = o . Memory ; break ; case k_PostIndexRegister : PostIdxReg = o . PostIdxReg ; break ; case k_MSRMask : MMask = o . MMask ; break ; case k_ProcIFlags : IFlags = o . IFlags ; break ; case k_ShifterImmediate


<s> bool hasFP ( const MachineFunction & MF ) const override { return


<s> if ( GET_MODE_UNIT_BITSIZE ( mem_mode ) < type_suffix ( <NUM_LIT> ) . element_bits ) add_input_operand ( icode , CONSTM1_RTX ( VNx16BImode ) ) ; return generate_insn ( icode


<s> static SDValue LowerInterruptReturn ( SmallVectorImpl < SDValue > & RetOps , SDLoc DL , SelectionDAG & DAG ) { const MachineFunction & MF = DAG . getMachineFunction ( ) ; const Function * F = MF . getFunction ( ) ; StringRef IntKind = F -> getFnAttribute ( <STR_LIT> ) . getValueAsString ( ) ; int64_t LROffset ; if ( IntKind == <STR_LIT> || IntKind == <STR_LIT> || IntKind == <STR_LIT> || IntKind == <STR_LIT> ) LROffset = <NUM_LIT> ; else if ( IntKind == <STR_LIT> || IntKind == <STR_LIT> ) LROffset = <NUM_LIT> ; else report_fatal_error ( <STR_LIT>


<s> bool inMicro<ISA_LIT>Mode ( ) const { return getSTI ( ) . getFeatureBits ( )


<s> OffImm = CurDAG -> getTargetConstant ( <NUM_LIT> , <STR_LIT> ) ; return true ; } if ( ! CurDAG -> isBaseWithConstantOffset ( N ) ) return false ; RegisterSDNode * LHSR = dyn_cast < RegisterSDNode > ( N . getOperand ( <NUM_LIT> ) ) ; if ( N . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> || ( LHSR && LHSR -> getReg ( ) == <STR_LIT> ) ) { int RHSC ; if ( isScaledConstantInRange ( N . getOperand ( <NUM_LIT> ) , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , RHSC ) ) { Base = N . getOperand ( <NUM_LIT> ) ; if ( Base . getOpcode


<s> break ; case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) || <STR_LIT> . hasSubClassEq ( RC ) ) { if ( Align >= <NUM_LIT> && getRegisterInfo ( ) . canRealignStack ( MF ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) . add ( predOps ( <STR_LIT> ) ) ; } else { MachineInstrBuilder MIB = BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . add ( predOps ( <STR_LIT> ) ) . addMemOperand ( MMO ) ; MIB = AddDReg ( MIB , DestReg , <STR_LIT> , RegState :: DefineNoRead , TRI ) ; MIB = AddDReg ( MIB , DestReg , <STR_LIT> , RegState :: DefineNoRead , TRI ) ; MIB = AddDReg ( MIB , DestReg , <STR_LIT> , RegState :: DefineNoRead , TRI ) ; MIB = AddDReg ( MIB , DestReg , <STR_LIT> , RegState :: DefineNoRead , TRI ) ; if ( TargetRegisterInfo :: isPhysicalRegister ( DestReg ) ) MIB . addReg ( DestReg , RegState :: ImplicitDefine ) ; } } else llvm_unreachable ( <STR_LIT> ) ; break ; case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) { MachineInstrBuilder MIB = BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . add ( predOps ( <STR_LIT> ) ) . addMemOperand ( MMO ) ; MIB = AddDReg ( MIB , DestReg , <STR_LIT> , RegState :: DefineNoRead , TRI ) ; MIB = AddDReg ( MIB , DestReg , <STR_LIT> , RegState :: DefineNoRead , TRI ) ; MIB = AddDReg ( MIB , DestReg , <STR_LIT> , RegState :: DefineNoRead , TRI ) ; MIB = AddDReg ( MIB , DestReg , <STR_LIT> , RegState :: DefineNoRead , TRI ) ; MIB = AddDReg ( MIB , DestReg , <STR_LIT> , RegState :: DefineNoRead , TRI ) ; MIB = AddDReg ( MIB , DestReg , <STR_LIT> , RegState :: DefineNoRead , TRI ) ; MIB = AddDReg ( MIB , DestReg , <STR_LIT> , RegState :: DefineNoRead , TRI ) ; MIB = AddDReg ( MIB , DestReg , <STR_LIT> , RegState :: DefineNoRead , TRI ) ; if ( TargetRegisterInfo :: isPhysicalRegister ( DestReg ) ) MIB . addReg ( DestReg , RegState :: ImplicitDefine ) ; } else llvm_unreachable


<s> uint64_t StartSrcReg = forceReg ( MI , SrcBase , TII ) ; uint64_t StartDestReg = ( HaveSingleBase ? StartSrcReg : forceReg ( MI , DestBase , TII ) ) ; const TargetRegisterClass * RC = & <STR_LIT> ; uint64_t ThisSrcReg = MRI . createVirtualRegister ( RC ) ; uint64_t ThisDestReg = ( HaveSingleBase ? ThisSrcReg : MRI . createVirtualRegister ( RC ) ) ; uint64_t NextSrcReg = MRI . createVirtualRegister ( RC ) ; uint64_t NextDestReg = ( HaveSingleBase ? NextSrcReg : MRI . createVirtualRegister ( RC ) ) ; RC = & <STR_LIT> ; uint64_t ThisCountReg = MRI . createVirtualRegister ( RC ) ; uint64_t NextCountReg = MRI . createVirtualRegister ( RC ) ; MachineBasicBlock * StartMBB = MBB ; MachineBasicBlock * DoneMBB = splitBlockBefore ( MI , MBB ) ; MachineBasicBlock * LoopMBB = emitBlockAfter ( StartMBB ) ; MachineBasicBlock * NextMBB = ( EndMBB ? emitBlockAfter ( LoopMBB ) : LoopMBB ) ; MBB -> addSuccessor ( LoopMBB ) ; MBB = LoopMBB ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) , ThisDestReg ) . addReg ( StartDestReg ) . addMBB ( StartMBB ) . addReg ( NextDestReg ) . addMBB ( NextMBB ) ; if ( ! HaveSingleBase ) BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) , ThisSrcReg ) . addReg ( StartSrcReg ) . addMBB ( StartMBB ) . addReg ( NextSrcReg ) . addMBB ( NextMBB ) ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) , ThisCountReg ) . addReg ( StartCountReg ) . addMBB ( StartMBB ) . addReg ( NextCountReg ) . addMBB ( NextMBB ) ; if ( Opcode == <STR_LIT> ) BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) ) . addImm ( <STR_LIT> ) . addReg ( ThisDestReg ) . addImm ( DestDisp + <NUM_LIT> ) . addReg ( <NUM_LIT> ) ; BuildMI ( MBB , DL , TII -> get ( Opcode ) ) . addReg ( ThisDestReg ) . addImm ( DestDisp ) . addImm ( <NUM_LIT> ) . addReg ( ThisSrcReg ) . addImm ( SrcDisp ) ; if ( EndMBB ) { BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) ) . addImm ( <STR_LIT> ) . addImm ( <STR_LIT> ) . addMBB ( EndMBB ) ; MBB -> addSuccessor ( EndMBB ) ; MBB -> addSuccessor ( NextMBB ) ; } MBB = NextMBB ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) , NextDestReg ) . addReg ( ThisDestReg ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) ; if ( ! HaveSingleBase ) BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) , NextSrcReg ) . addReg ( ThisSrcReg ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) , NextCountReg ) . addReg

( ThisCountReg ) . addImm ( - <NUM_LIT> ) ;


<s> HasBMI2 = false ; HasVBMI = false ; HasIFMA = false ; HasRTM = false ; HasHLE = false ; HasERI = false ; HasCDI = false ; HasPFI = false ; HasDQI = false ; HasBWI = false ; HasVLX = false ; HasADX = false ; HasPKU = false ; HasSHA = false ; HasPRFCHW = false ; HasRDSEED = false ; HasLAHFSAHF = false ; HasMWAITX = false ; HasMPX = false ; IsBTMemSlow = false ; IsSHLDSlow = false ; IsUAMem16Slow = false ; IsUAMem32Slow = false ; HasSSEUnalignedMem = false ; HasCmpxchg16b = false ; UseLeaForSP = false ; HasFastPartialYMMWrite = false ; HasFastScalarFSQRT = false ; HasFastVectorFSQRT = false ; HasSlowDivide32 =


<s> const GlobalVariable * GVA = dyn_cast < GlobalVariable > ( GV ) ; if ( ! GVA ) return false ; if ( ! LocalSData && GV -> hasLocalLinkage ( ) ) return false ; if ( ! ExternSData && ( ( GV -> hasExternalLinkage ( ) && GV -> isDeclaration ( ) ) || GV ->


<s> if ( ! In . getValueType ( ) . isSimple ( ) ) return SDValue ( ) ; MVT VT = N -> getValueType ( <NUM_LIT> ) . getSimpleVT ( ) ; MVT SVT = VT . getScalarType ( ) ; MVT InVT = In . getValueType ( ) . getSimpleVT ( ) ; MVT InSVT = InVT . getScalarType ( ) ; if ( ! isPowerOf2_32 ( VT . getVectorNumElements ( ) ) ) return SDValue ( ) ; if ( SVT != <STR_LIT> && SVT != <STR_LIT> && SVT != <STR_LIT> ) return SDValue ( ) ; if ( InSVT != <STR_LIT> && InSVT != <STR_LIT> && InSVT != <STR_LIT> ) return SDValue ( ) ; if ( SVT == <STR_LIT> && VT . getSizeInBits ( ) < <NUM_LIT> ) return SDValue ( ) ; if ( Subtarget . hasAVX512 ( ) && ! ( ! Subtarget . useAVX512Regs ( ) && VT . is256BitVector ( ) && InVT . is512BitVector ( ) ) ) { SmallVector < SDValue


<s> if ( Flags . isByVal ( ) ) ArgSize = Flags . getByValSize ( ) ; ArgSize = ( ( ArgSize + PtrByteSize - <NUM_LIT> ) / PtrByteSize


<s> return ( long long ) __builtin_ia32_vcvttsd2si64 ( (


<s> bool <ISA_LIT>CallEntry :: isAliased ( const MachineFrameInfo * ) const { return


<s> FrameIndexSDNode * FIN = cast < FrameIndexSDNode > ( Op ) ; unsigned FrameIndex = FIN -> getIndex ( ) ; unsigned Offset = TFL -> getFrameIndexOffset (


<s> unsigned <ISA_LIT>AsmParser :: findImplicitSGPRReadInVOP ( const MCInst & Inst ) const { const MCInstrDesc & Desc = MII . get ( Inst . getOpcode ( ) ) ; const unsigned Num = Desc . getNumImplicitUses ( ) ; for ( unsigned i = <NUM_LIT> ; i < Num ; ++ i ) { unsigned Reg = Desc . ImplicitUses [ i ] ; switch ( Reg ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> void LLVMInitializeR600TargetMC ( ) { RegisterMCAsmInfo < AMDGPUMCAsmInfo > Y ( TheAMDGPUTarget ) ; TargetRegistry :: RegisterMCCodeGenInfo ( TheAMDGPUTarget , createAMDGPUMCCodeGenInfo ) ; TargetRegistry :: RegisterMCInstrInfo ( TheAMDGPUTarget , createAMDGPUMCInstrInfo ) ; TargetRegistry :: RegisterMCRegInfo ( TheAMDGPUTarget , createAMDGPUMCRegisterInfo ) ; TargetRegistry :: RegisterMCSubtargetInfo ( TheAMDGPUTarget , createAMDGPUMCSubtargetInfo ) ; TargetRegistry :: RegisterMCInstPrinter ( TheAMDGPUTarget , createAMDGPUMCInstPrinter ) ; TargetRegistry :: RegisterMCCodeEmitter ( TheAMDGPUTarget , createAMDGPUMCCodeEmitter ) ; TargetRegistry :: RegisterMCAsmBackend ( TheAMDGPUTarget , createAMDGPUAsmBackend


<s> Symbol -> setType ( ELF :: STT_NOTYPE ) ; Symbol -> setBinding ( ELF :: STB_LOCAL ) ; Symbol -> setExternal (


<s> static std :: unique_ptr < <ISA_LIT>Operand > CreateBarrier ( unsigned Val , SMLoc S , MCContext & Ctx ) { auto Op = make_unique < <ISA_LIT>Operand > ( k_Barrier , Ctx ) ; Op -> Barrier . Val = Val ; Op -> StartLoc = S ; Op -> EndLoc = S ; return Op


<s> unsigned <ISA_LIT>FastISel :: <ISA_LIT>MoveToFPReg ( MVT SrcVT , unsigned SrcReg , bool IsSigned ) { if ( SrcVT == <STR_LIT> ) { unsigned TmpReg = createResultReg ( & <STR_LIT> ) ; if ( ! <ISA_LIT>EmitIntExt ( <STR_LIT> , SrcReg , <STR_LIT> , TmpReg , ! IsSigned ) ) return <NUM_LIT> ; SrcReg = TmpReg ; } Address Addr ; Addr . BaseType = Address :: FrameIndexBase ; Addr . Base . FI = MFI . CreateStackObject ( <NUM_LIT> ,


<s> bool <ISA_LIT>CFGStructurizer :: isRetiredBlock ( MachineBasicBlock * MBB ) const { MBBInfoMap :: const_iterator It = BlockInfoMap . find ( MBB ) ; if ( It == BlockInfoMap . end ( ) )


<s> return parseRegister ( RegNo , StartLoc , EndLoc


<s> uint16_t VendorNameSize = VendorName . size ( ) + <NUM_LIT> ; uint16_t ArchNameSize = ArchName . size ( ) + <NUM_LIT> ; unsigned DescSZ = sizeof ( VendorNameSize ) + sizeof ( ArchNameSize ) + sizeof ( Major ) + sizeof ( Minor ) + sizeof ( Stepping ) + VendorNameSize + ArchNameSize ; EmitNote ( ElfNote :: NoteNameV2 , MCConstantExpr :: create ( DescSZ , getContext ( ) ) , ElfNote :: NT_<ISA_LIT>_HSA_ISA , [ & ] ( MCELFStreamer & OS ) { OS . emitIntValue ( VendorNameSize ,


<s> assert ( VT . isFloatingPoint ( ) && <STR_LIT>


<s> auto Op = make_unique < <ISA_LIT>Operand > ( k_VectorListIndexed ) ; Op -> VectorList . RegNum = RegNum ; Op -> VectorList . Count = Count ; Op -> VectorList . LaneIndex = Index ; Op -> VectorList . isDoubleSpaced = isDoubleSpaced ; Op -> StartLoc = S ; Op -> EndLoc


<s> int64_t ImmVal = ValAndVReg -> Value ; if ( OffsetOpc == TargetOpcode :: G_MUL ) { if ( ! isPowerOf2_32 ( ImmVal ) ) return None ; ImmVal = Log2_32 ( ImmVal ) ; } if ( ( ImmVal & <NUM_LIT> ) != ImmVal ) return None ; if ( ImmVal != LegalShiftVal ) return None ; return { { [ = ] ( MachineInstrBuilder & MIB ) { MIB . addUse ( Gep -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; } , [ = ] ( MachineInstrBuilder & MIB ) { MIB . addUse ( OffsetReg ) ; } , [ = ] ( MachineInstrBuilder & MIB ) { MIB . addImm ( <NUM_LIT> ) ; MIB . addImm ( <NUM_LIT> ) ; } }


<s> StringRef getPassName ( ) const override { return <STR_LIT>


<s> bool <ISA_LIT>AsmParser :: parseCondCode ( OperandVector & Operands , bool invertCondCode ) { MCAsmParser & Parser = getParser ( ) ; SMLoc S = getLoc ( ) ; const AsmToken & Tok = Parser . getTok ( ) ; assert ( Tok . is ( AsmToken :: Identifier ) && <STR_LIT> ) ; StringRef Cond = Tok .


<s> return ( int16x4_t ) __builtin_aarch64_srhaddv4hi ( __a ,


<s> bool Changed = false ; auto Children = Region -> getChildren ( ) ; for ( auto CI : * Children ) { if ( CI -> isRegion


<s> return __builtin_mve_vrshrq_m_n_uv16qi ( __arm_vuninitializedq_u8 ( ) , __a


<s> MachineInstr & SrcInst = * Src -> getInstr ( ) ; MachineInstr & DstInst = * Dst -> getInstr ( ) ; if ( Dst -> isBoundaryNode ( ) ) return false ; if ( SrcInst . isPHI ( ) || DstInst . isPHI ( ) ) return false ; SUnit * Best = nullptr ; SUnit * DstBest = nullptr ; SUnit * SrcBest = getZeroLatency ( Dst , Dst -> Preds ) ; if ( SrcBest == nullptr || Src -> NodeNum >= SrcBest -> NodeNum ) { DstBest = getZeroLatency ( Src , Src -> Succs ) ; if ( DstBest == nullptr || Dst -> NodeNum <= DstBest -> NodeNum ) Best = Dst ; } if ( Best != Dst ) return false ; if ( Src == SrcBest && Dst == DstBest ) return true ; if ( SrcBest != nullptr ) changeLatency ( SrcBest , SrcBest -> Succs , Dst , <NUM_LIT> ) ; if ( DstBest != nullptr ) changeLatency ( Src , Src -> Succs , DstBest


<s> if ( STI . in<ISA_LIT>16Mode ( ) ) return llvm ::


<s> TRI = ST . getRegisterInfo ( ) ; MRI = & MF . getRegInfo ( ) ; SchedModel . init ( & ST ) ; Traces = & getAnalysis < MachineTraceMetrics > ( ) ; MinInstr = nullptr ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << getPassName ( ) << <STR_LIT> << MF . getName ( ) << '\n' ) ; if ( ! SchedModel . hasInstrSchedModel ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } for ( auto & MBB : MF ) { bool SuppressSTP = false ; unsigned PrevBaseReg = <NUM_LIT> ; for ( auto & MI : MBB ) { if ( ! isNarrowFPStore ( MI ) ) continue ; const MachineOperand * BaseOp ; int64_t Offset ; if ( TII -> getMemOperandWithOffset ( MI , BaseOp , Offset , TRI ) && BaseOp -> isReg ( ) ) { unsigned BaseReg = BaseOp -> getReg ( ) ; if ( PrevBaseReg == BaseReg ) { if ( ! SuppressSTP && shouldAddSTPToBlock ( MI . getParent ( ) ) ) break ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT>


<s> this -> cc = static_cast < <ISA_LIT>CondCode > ( ccValue


<s> if ( skipFunction ( MF . getFunction ( ) ) ) return false ; bool Changed = false ; for ( auto & MBB : MF ) { auto BlockIter = MBB . begin ( ) ; while ( BlockIter != MBB . end ( ) ) { auto & MI = * BlockIter ++ ; if ( isCVTAToLocalCombinationCandidate ( MI ) ) { CombineCVTAToLocal ( MI )


<s> static <ISA_LIT>Operand CreateReg ( unsigned RegNo ) { <ISA_LIT>Operand Res ; Res . Kind = Register ; Res . Reg . RegNo =


<s> explicit <ISA_LIT>DAGToDAGISel ( <ISA_LIT>TargetMachine & targetmachine , CodeGenOpt :: Level OptLevel ) : SelectionDAGISel ( targetmachine , OptLevel ) ,


<s> MCCodeEmitter * llvm :: create<ISA_LIT>MCCodeEmitter ( const MCInstrInfo & MCII , const MCRegisterInfo & MRI ,


<s> Address ( ) : BaseType ( RegBase ) , Offset ( <NUM_LIT> ) { Base . Reg =


<s> int <ISA_LIT>TTIImpl :: getArithmeticInstrCost ( unsigned Opcode , Type * Ty , TTI :: OperandValueKind Op1Info , TTI :: OperandValueKind Op2Info , TTI :: OperandValueProperties Opd1PropInfo , TTI :: OperandValueProperties Opd2PropInfo ) { assert ( TLI -> InstructionOpcodeToISD ( Opcode ) && <STR_LIT> ) ; return BaseT :: getArithmeticInstrCost ( Opcode , Ty , Op1Info , Op2Info , Opd1PropInfo


<s> return createMachOStreamer ( Ctx , std :: move ( MAB ) , OS , std :: move ( Emitter ) , false


<s> SmallVector < SDValue , <NUM_LIT> > Elts ; if ( SrcVT . isVector ( ) ) DAG . ExtractVectorElements ( Src , Elts ) ; else Elts . push_back ( Src ) ; SDValue Undef = DAG . getUNDEF ( SrcVT . getScalarType ( ) ) ; while ( ExtraElts -- ) Elts . push_back (


<s> } if ( ValWidth == <NUM_LIT> ) { SDValue A0 = getInstr ( <STR_LIT> , dl , <STR_LIT> , { VecV } , DAG ) ; SDValue M0 = DAG . getConstant ( <NUM_LIT> / VecWidth , dl , <STR_LIT> ) ; SDValue I0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , IdxV , M0 ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , A0 , I0 ) ; } unsigned Scale = VecWidth / ValWidth ; assert ( ty ( IdxV ) == <STR_LIT> ) ; SDValue S0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , IdxV , DAG . getConstant ( <NUM_LIT> * Scale , dl , <STR_LIT> ) ) ; SDValue T0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , VecV ) ; SDValue T1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , T0 , S0 ) ; while ( Scale > <NUM_LIT> ) { T1 = DAG . getTargetExtractSubreg ( <STR_LIT> , dl , <STR_LIT> , T1 ) ; T1 = expandPredicate ( T1 , dl , DAG ) ; Scale /= <NUM_LIT> ; } return DAG . getNode ( <STR_LIT> , dl , ResTy , T1 ) ; } assert ( VecWidth == <NUM_LIT> || VecWidth == <NUM_LIT> ) ; MVT ScalarTy = tyScalar ( VecTy ) ; VecV = DAG . getBitcast ( ScalarTy , VecV ) ; SDValue WidthV = DAG . getConstant ( ValWidth , dl , <STR_LIT> ) ; SDValue ExtV ; if ( IdxN ) { unsigned Off = IdxN -> getZExtValue ( ) * ElemWidth ; if ( VecWidth == <NUM_LIT> && ValWidth == <NUM_LIT> ) { assert ( Off == <NUM_LIT> ||


<s> unsigned TensorId = std :: lower_bound ( ArchLdStLVec . begin ( ) , ArchLdStLVec . end ( ) , NumVal ) - ArchLdStLVec . begin ( ) - <NUM_LIT> ; if ( TensorId == - <NUM_LIT> ) TensorId = <NUM_LIT> ; StLTensors . insert ( ( TensorId ) ) ; if ( BailoutReason . empty (


<s> return UNSPEC_COND_NE ; case EQ : return UNSPEC_COND_EQ ; case LT : return UNSPEC_COND_LT ; case GT : return UNSPEC_COND_GT ; case LE


<s> return OpToFold . isFI ( ) && TII -> isMUBUF ( UseMI ) && OpNo == <STR_LIT> ( UseMI . getOpcode (


<s> MachineOperand & Src0 = Inst . getOperand ( <NUM_LIT> ) ; MachineOperand & Src1 = Inst . getOperand ( <NUM_LIT> ) ; unsigned NewDest = MRI . createVirtualRegister ( & <STR_LIT> ) ; unsigned Interm = MRI . createVirtualRegister ( & <STR_LIT> ) ; MachineInstr & Op = * BuildMI ( MBB , MII , DL , get ( Opcode ) , Interm ) . add ( Src0 ) . add ( Src1 ) ; MachineInstr & Not = * BuildMI ( MBB , MII , DL , get ( <STR_LIT> ) , NewDest ) . addReg ( Interm ) ; Worklist . insert ( & Op ) ; Worklist . insert (


<s> assert ( VA . isMemLoc ( ) ) ; ArgRegEnd = <NUM_LIT> ; unsigned ArgSize = VA . getLocVT ( ) . getSizeInBits ( ) / <NUM_LIT> ; unsigned StackLoc = VA . getLocMemOffset ( ) + <NUM_LIT> ; int FI = MFI -> CreateFixedObject ( ArgSize , <NUM_LIT> , true ) ; TFI -> recordLoadArgsFI ( FI , - StackLoc ) ; TFI -> recordLiveIn ( FI ) ; SDValue FIN = DAG . getFrameIndex ( FI , getPointerTy ( ) ) ; InVals . push_back ( DAG . getLoad ( VA . getValVT ( ) , dl , Chain , FIN , MachinePointerInfo :: getFixedStack ( FI ) , false , false , false , <NUM_LIT> ) ) ; } } if ( ( isVarArg ) && ArgRegEnd ) { if ( StackPtr . getNode ( ) == <NUM_LIT> ) StackPtr = DAG . getRegister ( StackReg , getPointerTy ( ) ) ; const TargetRegisterClass * RC = & <STR_LIT> ; unsigned Begin = get<ISA_LIT>RegisterNumbering ( <STR_LIT> ) ; unsigned Start = get<ISA_LIT>RegisterNumbering ( ArgRegEnd + <NUM_LIT> ) ; unsigned End = get<ISA_LIT>RegisterNumbering ( <STR_LIT> ) ; unsigned StackLoc = Start - Begin + <NUM_LIT> ; for ( ; Start <= End ; ++ Start , ++ StackLoc ) { unsigned Reg = get<ISA_LIT>RegisterFromNumbering ( Start ) ; unsigned LiveReg = MF . addLiveIn ( Reg , RC ) ; SDValue ArgValue = DAG . getCopyFromReg ( Chain , dl , LiveReg , <STR_LIT> ) ; int FI = MFI -> CreateFixedObject ( <NUM_LIT> , <NUM_LIT> , true ) ; TFI -> recordStoreVarArgsFI ( FI , -


<s> if ( CurDAG -> isBaseWithConstantOffset ( addr ) ) { LLVM_DEBUG ( errs ( ) << <STR_LIT> ) ; ConstantSDNode * CN = dyn_cast < ConstantSDNode > ( addr . getOperand ( <NUM_LIT> ) ) ; SDValue base ; SDNode * add ; if ( isInt < <NUM_LIT> > ( CN -> getSExtValue ( ) ) ) { base = addr . getOperand ( <NUM_LIT> ) ; LLVM_DEBUG ( errs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( base . dump ( ) ) ; SDValue off = CurDAG -> getTargetConstant ( CN -> getZExtValue ( ) , DL


<s> __inline__ static int sh_media_FMOV_SL ( float fg ) { int res ; __asm__ ( <STR_LIT> : <STR_LIT> ( res ) : <STR_LIT> ( fg ) ) ; return res


<s> if ( delta >= <NUM_LIT> && delta < <NUM_LIT> ) fprintf ( stream , <STR_LIT> , regname , ( int ) delta ) ; else if ( delta < <NUM_LIT> && delta >= - <NUM_LIT> ) fprintf ( stream , <STR_LIT> , regname , regname , ( int ) - delta ) ; else { mmix_output_register_setting ( stream , <NUM_LIT> , delta , <NUM_LIT> ) ; fprintf ( stream , <STR_LIT> , regname , regname ) ; } fprintf ( stream , <STR_LIT> ) ; assemble_name ( stream , XSTR ( XEXP ( DECL_RTL ( func ) , <NUM_LIT> ) , <NUM_LIT> ) ) ; fprintf ( stream , <STR_LIT>


<s> static bool isStartChunk ( uint64_t Chunk ) { if ( Chunk == <NUM_LIT> || Chunk == UINT64_MAX ) return false ; return ( CountLeadingOnes_64 ( Chunk ) + countTrailingZeros


<s> unsigned type = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned align = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; if ( type == <NUM_LIT> && align == <NUM_LIT> ) return MCDisassembler :: Fail ; if ( type == <NUM_LIT> && align == <NUM_LIT> ) return


<s> bool hasModifier ( ) const { return Modifier


<s> static bool isDisp8 ( int Value ) { return Value == ( signed


<s> SDValue <ISA_LIT>TargetLowering :: LowerReturn ( SDValue Chain , CallingConv :: ID CallConv , bool isVarArg , const SmallVectorImpl < <STR_LIT> > & Outs , const SmallVectorImpl < SDValue > & OutVals , const SDLoc & dl , SelectionDAG & DAG ) const { SmallVector < CCValAssign , <NUM_LIT> > RVLocs ; CCState CCInfo ( CallConv , isVarArg , DAG . getMachineFunction ( ) , RVLocs , * DAG . getContext ( ) ) ; auto CCFunction = CCAssignFnForReturn ( CallConv ) ; CCInfo . AnalyzeReturn ( Outs , CCFunction ) ; MachineFunction & MF = DAG . getMachineFunction ( ) ; unsigned e = RVLocs . size ( ) ; if ( e > <NUM_LIT> ) { std :: reverse ( RVLocs . begin ( ) , RVLocs . end ( ) ) ; } SDValue Flag ; SmallVector < SDValue , <NUM_LIT> > RetOps ( <NUM_LIT> , Chain ) ; for ( unsigned i = <NUM_LIT> ; i != e ; ++ i ) { CCValAssign & VA = RVLocs [ i ] ; assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; Chain = DAG . getCopyToReg ( Chain , dl , VA . getLocReg ( ) , OutVals [ i ] , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( VA . getLocReg (


<s> for ( const MachineOperand & MO : MI . implicit_operands ( ) ) if ( MO . isReg ( ) && MO . isDef ( ) ) if ( TRI -> regsOverlap ( Reg , MO . getReg ( ) ) ) return true ; return false


<s> <ISA_LIT>ConstantPoolValue * ACPV = static_cast < <ISA_LIT>ConstantPoolValue * > ( MCPV ) ; MCSymbol * MCSym ; if ( ACPV -> isLSDA ( ) ) { SmallString < <NUM_LIT> > Str ; raw_svector_ostream OS ( Str ) ; OS << DL -> getPrivateGlobalPrefix ( ) << <STR_LIT> << getFunctionNumber ( ) ; MCSym = OutContext . GetOrCreateSymbol ( OS . str ( ) ) ; } else if ( ACPV -> isBlockAddress ( ) ) { const BlockAddress * BA = cast < <ISA_LIT>ConstantPoolConstant > ( ACPV ) -> getBlockAddress ( ) ; MCSym = GetBlockAddressSymbol ( BA ) ; } else if ( ACPV -> isGlobalValue ( ) ) { const GlobalValue * GV = cast < <ISA_LIT>ConstantPoolConstant > ( ACPV ) -> getGV ( ) ; unsigned char TF = Subtarget -> isTargetMachO ( ) ? <STR_LIT> : <NUM_LIT> ; MCSym = Get<ISA_LIT>GVSymbol ( GV , TF ) ; } else if ( ACPV -> isMachineBasicBlock ( ) ) { const MachineBasicBlock * MBB = cast < <ISA_LIT>ConstantPoolMBB > ( ACPV ) -> getMBB ( ) ; MCSym = MBB -> getSymbol ( ) ; } else { assert ( ACPV -> isExtSymbol ( ) && <STR_LIT> ) ; const char * Sym = cast < <ISA_LIT>ConstantPoolSymbol > ( ACPV ) -> getSymbol ( ) ; MCSym = GetExternalSymbolSymbol ( Sym ) ; } const MCExpr * Expr = MCSymbolRefExpr :: Create ( MCSym , getModifierVariantKind ( ACPV -> getModifier ( ) ) , OutContext ) ; if ( ACPV -> getPCAdjustment ( ) ) { MCSymbol * PCLabel = getPICLabel ( DL -> getPrivateGlobalPrefix ( ) , getFunctionNumber ( ) , ACPV -> getLabelId ( ) , OutContext ) ; const MCExpr * PCRelExpr = MCSymbolRefExpr :: Create ( PCLabel , OutContext ) ; PCRelExpr = MCBinaryExpr :: CreateAdd ( PCRelExpr , MCConstantExpr :: Create ( ACPV

-> getPCAdjustment ( ) , OutContext ) , OutContext ) ;