<s> return __builtin_aarch64_fixuns_trunchfdi_us (


<s> unsigned <ISA_LIT>InstrInfo :: insertBranch ( MachineBasicBlock & MBB , MachineBasicBlock * TBB , MachineBasicBlock * FBB , ArrayRef < MachineOperand > Cond , const DebugLoc & DL , int * BytesAdded ) const { if ( ! FBB && Cond . empty ( ) ) { BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addMBB ( TBB ) ; if ( BytesAdded ) * BytesAdded = <NUM_LIT> ; return <NUM_LIT> ; } assert ( TBB && Cond [ <NUM_LIT> ] . isImm ( ) ) ; unsigned Opcode = getBranchOpcode ( static_cast < BranchPredicate > ( Cond [ <NUM_LIT> ] . getImm ( ) ) ) ; if ( ! FBB ) { Cond [ <NUM_LIT> ] . isUndef ( ) ; MachineInstr * CondBr = BuildMI ( & MBB , DL , get (


<s> <ISA_LIT>TargetStreamer & getTargetStreamer ( ) { assert ( getParser ( ) . getStreamer ( ) . getTargetStreamer ( ) && <STR_LIT>


<s> static bool loongarch_hard_regno_mode_ok ( unsigned int regno , machine_mode mode ) { return loongarch_hard_regno_mode_ok_p [ mode ] [


<s> if ( OPI != ReduceOpcodeMap . end ( ) ) { const ReduceEntry & Entry = ReduceTable [ OPI -> second ] ; if ( Entry . Special ) { if ( ReduceSpecial ( MBB , MI , Entry , LiveCPSR ) ) { Modified = true ; MachineBasicBlock :: iterator I = prior ( NextMII ) ; MI = & * I ; } goto ProcessNext ; } if ( Entry . NarrowOpc2 && ReduceTo2Addr ( MBB , MI , Entry , LiveCPSR ) ) { Modified = true ; MachineBasicBlock :: iterator I = prior ( NextMII ) ; MI = & * I ; goto ProcessNext


<s> static DecodeStatus DecodeFPR64RegisterClass ( MCInst & Inst , uint64_t RegNo , uint64_t Address , const void * Decoder ) { if ( RegNo > sizeof ( FPR64DecoderTable ) ) return MCDisassembler :: Fail ; unsigned Reg = FPR64DecoderTable [ RegNo ] ; Inst . addOperand ( MCOperand :: createReg ( Reg ) ) ; return MCDisassembler


<s> const ArrayRef < MCPhysReg > <ISA_LIT>ABIInfo :: GetByValArgRegs ( ) const { if ( IsO32 ( ) ) return


<s> if ( Opcode == TargetOpcode :: LOAD_STACK_GUARD ) return false ; if ( I . isCopy ( ) ) return selectCopy ( I , MRI ) ; return true ; } assert ( I . getNumOperands ( ) == I . getNumExplicitOperands ( ) && <STR_LIT> ) ; if ( selectImpl ( I , CoverageInfo ) ) return true ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; I . print ( dbgs ( ) ) ) ; switch ( I . getOpcode ( ) ) { default : return false ; case TargetOpcode :: G_STORE : case TargetOpcode :: G_LOAD : return selectLoadStoreOp ( I , MRI , MF ) ; case TargetOpcode :: G_GEP : case TargetOpcode :: G_FRAME_INDEX : return selectFrameIndexOrGep ( I , MRI , MF ) ; case TargetOpcode :: G_GLOBAL_VALUE : return selectGlobalValue ( I , MRI , MF ) ; case TargetOpcode :: G_CONSTANT : return selectConstant ( I , MRI , MF ) ; case TargetOpcode :: G_FCONSTANT : return materializeFP ( I , MRI , MF ) ; case TargetOpcode :: G_PTRTOINT : case TargetOpcode :: G_TRUNC : return selectTruncOrPtrToInt ( I , MRI , MF ) ; case TargetOpcode :: G_INTTOPTR : return selectCopy ( I , MRI ) ; case TargetOpcode :: G_ZEXT : return selectZext ( I , MRI , MF ) ; case TargetOpcode :: G_ANYEXT : return selectAnyext ( I , MRI , MF ) ; case TargetOpcode :: G_ICMP : return selectCmp ( I , MRI , MF ) ; case TargetOpcode :: G_FCMP : return selectFCmp ( I , MRI , MF ) ; case TargetOpcode :: G_UADDE : return selectUadde ( I , MRI , MF ) ; case TargetOpcode :: G_UNMERGE_VALUES : return selectUnmergeValues ( I , MRI , MF , CoverageInfo ) ; case TargetOpcode :: G_MERGE_VALUES : return selectMergeValues ( I , MRI , MF , CoverageInfo ) ; case TargetOpcode :: G_EXTRACT : return selectExtract ( I , MRI , MF ) ; case TargetOpcode :: G_INSERT : return selectInsert ( I , MRI , MF ) ; case TargetOpcode :: G_BRCOND : return selectCondBranch ( I , MRI , MF ) ; case TargetOpcode :: G_IMPLICIT_DEF : case TargetOpcode :: G_PHI : return selectImplicitDefOrPHI ( I , MRI ) ; case TargetOpcode :: G_SHL : case TargetOpcode :: G_ASHR : case TargetOpcode :: G_LSHR : return selectShift ( I , MRI , MF ) ; case TargetOpcode :: G_SDIV


<s> auto * Def = RDA -> getReachingMIDef ( MI , <STR_LIT> ) ; if ( ! Def ) return nullptr ; if ( ! ( NewOpcode = VCMPOpcodeToVPT ( Def -> getOpcode ( ) ) ) ) return nullptr ; if ( ! RDA -> hasSameReachingDef ( Def , MI , Def -> getOperand ( <NUM_LIT> ) . getReg ( ) ) || !

RDA -> hasSameReachingDef ( Def , MI , Def -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ) return nullptr ;


<s> BlockAddressSDNode * N = cast < BlockAddressSDNode > ( Op ) ; EVT Ty = Op . getValueType ( ) ; if ( ! isPositionIndependent ( ) ) return getAddrNonPIC ( N , Ty , DAG ) ; return getAddrLocal ( N , Ty , DAG


<s> if ( DEBUGME ) { errs ( ) << <STR_LIT> << loopRep -> getHeader ( ) ->

getNumber ( ) << <STR_LIT> << regNum << <STR_LIT> ;


<s> else { auto * CalleeTy = cast < PointerType > ( Callee -> getType ( ) ) -> getElementType ( ) ; CalleeFTy = dyn_cast < FunctionType > ( CalleeTy ) ; } std :: string Sig = getSignature ( CalleeFTy ) ; if ( InvokeWrappers . find ( Sig ) != InvokeWrappers . end ( ) ) return InvokeWrappers [ Sig ] ; ArgTys . push_back ( PointerType :: getUnqual ( CalleeFTy ) ) ; ArgTys . append ( CalleeFTy -> param_begin ( ) , CalleeFTy -> param_end ( ) ) ; FunctionType * FTy = FunctionType :: get ( CalleeFTy -> getReturnType ( ) , ArgTys , CalleeFTy -> isVarArg ( ) ) ; Function * F = Function :: Create ( FTy , GlobalValue :: ExternalLinkage , InvokePrefix +


<s> SmallVector < ArgInfo , <NUM_LIT> > SplitVTs ; SmallVector < unsigned , <NUM_LIT> > Regs ; ArgInfo RetInfo ( VReg , Val -> getType ( ) ) ; setArgFlags ( RetInfo , AttributeList :: ReturnIndex , DL , F ) ; splitToValueTypes ( RetInfo , SplitVTs , MF , [ & ] ( unsigned Reg , uint64_t Offset ) { Regs . push_back ( Reg ) ; } )


<s> void printPCD8Mem ( const MCInst * MI , uint64_t Address , unsigned opNum , raw_ostream &


<s> static bool sparc_function_ok_for_sibcall ( tree decl , tree exp ATTRIBUTE_UNUSED ) { return ( decl && flag_delayed_branch && ( TARGET_ARCH64 || ! cfun -> returns_struct ) && ! ( TARGET_VXWORKS_RTP &&

flag_pic && ! targetm . binds_local_p ( decl ) ) ) ;


<s> if ( IDN ) { MachineBasicBlock * IDB = IDN -> getBlock ( ) ; using GTN = GraphTraits < MachineDomTreeNode * > ; using DTNodeVectType = SmallVector < MachineDomTreeNode * , <NUM_LIT> > ; DTNodeVectType Cn ( GTN :: child_begin ( N ) , GTN :: child_end ( N ) ) ; for ( DTNodeVectType :: iterator I = Cn . begin ( ) , E = Cn . end ( ) ; I != E ; ++ I ) { MachineBasicBlock * SB = ( * I ) -> getBlock ( ) ; MDT -> changeImmediateDominator ( SB , IDB ) ; } } while ( B -> succ_size ( ) > <NUM_LIT> ) B -> removeSuccessor ( B -> succ_begin ( ) ) ; for ( auto I = B -> pred_begin ( ) , E = B -> pred_end ( ) ; I != E ; ++ I ) ( * I ) -> removeSuccessor ( B , true ) ; Deleted . insert ( B ) ; MDT -> eraseNode ( B ) ; MFN -> erase ( B -> getIterator


<s> } else { avr_asm_len ( <STR_LIT> CR_TAB <STR_LIT> CR_TAB <STR_LIT> , op , plen , - <NUM_LIT> ) ; } } else if ( test_hard_reg_class ( LD_REGS , op [ <NUM_LIT> ] ) && ( INTVAL ( op [ <NUM_LIT> ] ) != INTVAL ( op [ <NUM_LIT> ] ) || ! reg_overlap_mentioned_p ( op [ <NUM_LIT> ] , op [ <NUM_LIT> ] ) ) ) { avr_asm_len ( <STR_LIT> CR_TAB <STR_LIT> CR_TAB <STR_LIT> , op , plen , - <NUM_LIT> ) ; } else { avr_asm_len ( <STR_LIT> CR_TAB <STR_LIT> , op , plen , - <NUM_LIT> ) ; if ( ! reg_unused_after ( insn , op [ <NUM_LIT> ] ) || reg_overlap_mentioned_p ( op [ <NUM_LIT> ] , op [ <NUM_LIT> ] ) ) { avr_asm_len ( <STR_LIT> , op , plen


<s> case 'K' : return C_Immediate ; case 'A' : return C_Memory ; } } return TargetLowering :: getConstraintType


<s> static std :: string getFrameLabel ( const std :: string & Func ) { std :: string Func1 = addPrefix ( Func ) ; std :: string tag = getTagName


<s> if ( check ( getLexer ( ) . is ( AsmToken :: Percent ) , L , <STR_LIT> ) || getParser ( ) . parseExpression ( Val , End ) || check ( isa < <ISA_LIT>MCExpr > ( Val ) , L , <STR_LIT> ) ) return nullptr ; return <STR_LIT> ( Val , Start , End ) ; } case AsmToken :: LCurly : { SMLoc Start = Parser . getTok ( ) . getLoc ( ) ; return ParseRoundingModeOp ( Start ) ; } default : { SMLoc Loc = Parser . getTok ( ) . getLoc ( ) , EndLoc ; const MCExpr * Expr = nullptr ; unsigned Reg = <NUM_LIT> ; if ( getLexer ( ) . isNot ( AsmToken :: LParen ) ) { if ( Parser . parseExpression ( Expr , EndLoc )


<s> static __inline qword si_rotqbii ( qword a , int count ) { vec_uchar16 x , y ; vec_uchar16 result ; x = vec_splat ( ( vec_uchar16 ) ( si_from_int ( count & <NUM_LIT> ) ) , <NUM_LIT> ) ; y = ( vec_uchar16 ) ( vec_sr ( ( vec_uint4 ) vec_sro ( ( vec_uchar16 ) ( a ) , ( ( vec_uchar16 ) ( ( vec_uint4 ) { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> }

) ) ) , ( vec_uint4 ) vec_sub ( vec_splat_u8 ( <NUM_LIT> ) , x ) ) ) ;


<s> assert ( Op . getValueType ( ) == <STR_LIT> ) ; Op = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op


<s> bool <ISA_LIT>InstrInfo :: isLegalFLATOffset ( int64_t Offset , unsigned AddrSpace , bool Signed ) const { if ( ! ST . hasFlatInstOffsets ( ) ) return false ; if ( ST . hasFlatSegmentOffsetBug ( ) && AddrSpace == <ISA_LIT>AS :: FLAT_ADDRESS ) return false ; if ( ST . getGeneration ( ) >= <ISA_LIT>Subtarget :: GFX10 ) { return ( Signed && isInt < <NUM_LIT> > ( Offset ) ) || ( ! Signed && isUInt < <NUM_LIT> > ( Offset ) ) ; } return ( Signed && isInt < <NUM_LIT> > ( Offset ) ) || ( ! Signed && isUInt < <NUM_LIT> > (


<s> return arm_gen_constant ( code , SImode , NULL_RTX , INTVAL ( val ) , NULL_RTX , NULL_RTX , <NUM_LIT>


<s> return ( __m128i ) __builtin_ia32_paddusw128_mask ( ( __v8hi ) __A , ( __v8hi ) __B , (


<s> if ( regno == REGNO ( crtl -> drap_reg ) ) { gcc_checking_assert ( cfun -> machine -> fs . fp_valid ) ; addr = plus_constant ( Pmode , hard_frame_pointer_rtx , cfun -> machine -> fs . fp_offset - cfa_offset ) ; mem = gen_rtx_MEM ( mode , addr ) ; add_reg_note ( insn , REG_CFA_DEF_CFA , mem ) ; } else { gcc_checking_assert ( cfun -> machine -> fs . fp_valid ) ; addr = plus_constant ( Pmode , hard_frame_pointer_rtx , cfun -> machine -> fs . fp_offset - cfa_offset ) ; mem = gen_rtx_MEM ( mode , addr ) ; add_reg_note ( insn , REG_CFA_EXPRESSION , gen_rtx_SET (


<s> return new <ISA_LIT>InferAddressSpaces


<s> case <STR_LIT> : return ; default : break ; } assert ( ! MI . mayLoad ( ) && <STR_LIT> ) ; if ( ! MI . getOperand ( <NUM_LIT> ) . isReg ( ) ) return ; auto & TargetOp = MI . getOperand ( <NUM_LIT> ) ; unsigned OldTargetReg = TargetOp .


<s> __asm__ ( <STR_LIT> : <STR_LIT> ( res ) : <STR_LIT> ( mm ) , <STR_LIT>


<s> if ( I -> getName ( ) . startswith ( <STR_LIT> ) || I -> getName ( ) . startswith ( <STR_LIT> ) ) continue ; if ( TD -> getTypeAllocSize ( I -> getType ( ) -> getElementType ( ) ) < MaxOffset ) { const TargetLoweringObjectFile & TLOF = TLI -> getObjFileLowering ( ) ; if ( TLOF . getKindForGlobal ( I , TLI -> getTargetMachine ( ) ) . isBSSLocal ( ) ) BSSGlobals . push_back ( I ) ; else if ( I -> isConstant ( ) ) ConstGlobals . push_back ( I ) ; else Globals . push_back ( I ) ; } } if ( Globals . size ( ) > <NUM_LIT> ) Changed |= doMerge ( Globals , M , false ) ; if ( BSSGlobals . size ( ) > <NUM_LIT> ) Changed |= doMerge ( BSSGlobals , M , false ) ; return Changed


<s> BuildVectorSDNode * BVN = dyn_cast < BuildVectorSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ; SDLoc dl ( N ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; SelectionDAG & DAG = DCI . DAG ; if ( ! DAG . getTargetLoweringInfo ( ) . isTypeLegal ( VT ) ) return SDValue ( ) ; APInt SplatBits , SplatUndef ; unsigned SplatBitSize ; bool HasAnyUndefs ; if ( BVN && BVN -> isConstantSplat ( SplatBits , SplatUndef , SplatBitSize , HasAnyUndefs ) ) { if ( SplatBitSize <= <NUM_LIT> ) { EVT VbicVT ; SDValue Val = isNEONModifiedImm ( ( ~ SplatBits ) . getZExtValue ( ) , SplatUndef . getZExtValue ( ) , SplatBitSize , DAG , dl , VbicVT , VT . is128BitVector ( ) , OtherModImm ) ; if ( Val . getNode ( ) ) { SDValue Input = DAG . getNode ( <STR_LIT> , dl , VbicVT , N -> getOperand ( <NUM_LIT> ) ) ; SDValue Vbic = DAG . getNode ( <STR_LIT> , dl , VbicVT ,


<s> } if ( rtx_equal_p ( op0 , op1 ) ) { perm0 = perm0 & <NUM_LIT> ; perm1 = ( perm1 & <NUM_LIT> ) + <NUM_LIT> ; } else if ( perm0 & <NUM_LIT> ) { if ( perm1 & <NUM_LIT> ) return false ; perm0 -= <NUM_LIT> ; perm1 += <NUM_LIT> ; std :: swap ( op0 , op1 ) ; } else if ( ( perm1 & <NUM_LIT> ) == <NUM_LIT> ) return false ; if ( target != NULL ) { machine_mode vmode , dmode ; rtvec v ; vmode = GET_MODE ( target ) ; gcc_assert ( GET_MODE_NUNITS ( vmode )


<s> static DecodeStatus DecodeFPR64CRegisterClass ( MCInst & Inst , uint64_t RegNo , uint64_t Address , const void * Decoder ) { if ( RegNo > <NUM_LIT> ) { return MCDisassembler :: Fail ; } unsigned Reg = FPR64DecoderTable [ RegNo + <NUM_LIT>


<s> return __builtin_aarch64_smax_nanv2df ( __a ,


<s> case TargetOpcode :: G_FCOS : case TargetOpcode :: G_FSIN : case TargetOpcode :: G_FLOG10 : case TargetOpcode :: G_FLOG : case TargetOpcode :: G_FLOG2 : case TargetOpcode :: G_FSQRT : case TargetOpcode :: G_FABS : case TargetOpcode :: G_FEXP : case TargetOpcode :: G_FRINT : case TargetOpcode :: G_INTRINSIC_TRUNC : case TargetOpcode :: G_INTRINSIC_ROUND : return


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : TargetOptions Options = Inst . getParent ( ) -> getParent ( ) -> getTarget ( ) . Options ; return ( Options . UnsafeFPMath || Options . AllowFPOpFusion ==


<s> static void initialize_aarch64_code_model ( struct gcc_options * opts ) { if ( opts -> x_flag_pic ) { switch ( opts -> x_aarch64_cmodel_var ) { case AARCH64_CMODEL_TINY : aarch64_cmodel = AARCH64_CMODEL_TINY_PIC ; break ; case AARCH64_CMODEL_SMALL : aarch64_cmodel = ( flag_pic == <NUM_LIT> ? AARCH64_CMODEL_SMALL_PIC


<s> return PHI . getOperand ( Index * <NUM_LIT> + <NUM_LIT> ) . getReg


<s> Binary |= encodeNEONRd ( MI , <NUM_LIT> ) ; unsigned Imm = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned Op = ( Imm >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Cmode = ( Imm >> <NUM_LIT> ) & <NUM_LIT> ; unsigned I = ( Imm >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Imm3 = ( Imm >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Imm4 = Imm & <NUM_LIT> ; Binary |= ( I << <NUM_LIT> ) | ( Imm3 << <NUM_LIT> ) | ( Cmode << <NUM_LIT> ) | ( Op << <NUM_LIT> ) | Imm4 ; if ( IsThumb ) Binary = convertNEONDataProcToThumb


<s> node_version_info = node -> function_version ( ) ; gcc_assert ( node -> dispatcher_function && node_version_info != NULL ) ; if ( node_version_info -> dispatcher_resolver ) return node_version_info -> dispatcher_resolver ; default_ver_decl = node_version_info -> next -> this_node -> decl ; node -> definition = false ; resolver_decl = make_resolver_func ( default_ver_decl , node -> decl , & empty_bb ) ; node_version_info -> dispatcher_resolver = resolver_decl ; push_cfun ( DECL_STRUCT_FUNCTION ( resolver_decl ) ) ; auto_vec < tree , <NUM_LIT> > fn_ver_vec ; for ( versn_info = node_version_info -> next ; versn_info ; versn_info = versn_info -> next ) { versn = versn_info -> this_node ; if ( DECL_VINDEX ( versn -> decl ) ) sorry (


<s> static bool containsLongjmpableCalls ( const Function * F ) { for ( const auto & BB : * F ) for ( const auto & I : BB ) if ( const auto * CB = dyn_cast < CallBase > ( & I ) ) if ( canLongjmp ( CB -> getCalledOperand ( ) ) ) return true ; return false


<s> auto NumeratorScaled = B . buildIntrinsic ( <STR_LIT> , { S32 , S1 } , false ) . addUse ( LHS ) . addUse ( RHS ) . addImm ( <NUM_LIT> ) . setMIFlags ( Flags ) ; auto ApproxRcp = B . buildIntrinsic ( <STR_LIT> , { S32 } , false ) . addUse ( DenominatorScaled . getReg ( <NUM_LIT> ) ) . setMIFlags ( Flags ) ; auto NegDivScale0 = B . buildFNeg ( S32 , DenominatorScaled , Flags ) ; if ( ! Mode . allFP32Denormals ( ) ) toggleSPDenormMode ( true , B , ST , Mode ) ; auto Fma0 = B . buildFMA ( S32 , NegDivScale0 , ApproxRcp , One , Flags ) ; auto Fma1 = B . buildFMA ( S32 , Fma0 , ApproxRcp , ApproxRcp , Flags ) ; auto Mul = B . buildFMul ( S32 , NumeratorScaled , Fma1 , Flags ) ; auto Fma2 = B . buildFMA ( S32 , NegDivScale0 , Mul , NumeratorScaled , Flags ) ; auto Fma3 = B . buildFMA ( S32 , Fma2 , Fma1 , Mul


<s> } else continue ; } else continue ; unsigned PtrAddrSpace = PtrValue -> getType ( ) -> getPointerAddressSpace ( ) ; if ( PtrAddrSpace ) continue ; if ( L -> isLoopInvariant ( PtrValue ) ) continue ; const SCEV * LSCEV = SE -> getSCEVAtScope ( PtrValue , L ) ; const SCEVAddRecExpr * LARSCEV = dyn_cast < SCEVAddRecExpr > ( LSCEV ) ; if ( ! LARSCEV || LARSCEV -> getLoop ( ) != L ) continue ; if ( isValidCandidate ( & J , PtrValue ) ) addOneCandidate ( MemI , LSCEV , Buckets , MaxCandidateNum ) ; } return


<s> if ( PredicateFtor && ! PredicateFtor ( MF . getFunction ( ) ) ) return false ; STI = & static_cast < const <ISA_LIT>Subtarget & > ( MF . getSubtarget ( ) ) ; if ( STI -> isThumb1Only ( ) || STI -> prefers32BitThumb ( ) ) return false ; TII = static_cast < const Thumb2InstrInfo * > ( STI -> getInstrInfo


<s> UnCondBrIter = I ; if ( ! AllowModify ) { TBB = I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; continue ; } while ( std :: next ( I ) != MBB . end ( ) ) { std :: next ( I ) -> eraseFromParent ( ) ; } Cond . clear ( ) ; FBB = nullptr ; if ( MBB . isLayoutSuccessor ( I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ) ) { TBB = nullptr ; I -> eraseFromParent ( ) ; I = MBB . end ( ) ; UnCondBrIter = MBB . end ( ) ; continue ; } TBB = I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; continue ; } <STR_LIT> BranchCode = getCondFromBranchOpc ( I -> getOpcode ( ) ) ; if ( BranchCode == <STR_LIT> ) { return true ; } if ( Cond . empty ( ) ) { MachineBasicBlock * TargetBB = I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; if ( AllowModify && UnCondBrIter != MBB . end ( ) && MBB . isLayoutSuccessor ( TargetBB ) ) { BranchCode = getOppositeCondition ( BranchCode ) ; unsigned JNCC = getBrCond ( BranchCode ) . getOpcode ( ) ; MachineBasicBlock :: iterator OldInst = I ; BuildMI ( MBB , UnCondBrIter , MBB . findDebugLoc ( I ) , get ( JNCC ) ) . addMBB ( UnCondBrIter ->

getOperand ( <NUM_LIT> ) . getMBB ( ) ) ;


<s> bool <ISA_LIT>PassConfig :: addPreISel ( ) { if ( ! DisablePreIncPrep && getOptLevel ( ) != CodeGenOpt :: None ) addPass ( create<ISA_LIT>LoopPreIncPrepPass ( get<ISA_LIT>TargetMachine ( ) ) ) ; if ( ! DisableCTRLoops && getOptLevel ( ) != CodeGenOpt :: None )

addPass ( createHardwareLoopsPass ( ) ) ;


<s> bool <ISA_LIT>RegisterInfo :: needsFrameBaseReg ( MachineInstr * MI , int64_t Offset ) const { assert ( Offset < <NUM_LIT> && <STR_LIT> ) ; unsigned OpC = MI -> getOpcode ( ) ; if ( ! ImmToIdxMap . count ( OpC ) ) return false ; if ( ( OpC == <STR_LIT> || OpC == <STR_LIT> ) && MI -> getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) return false ; MachineBasicBlock & MBB = * MI -> getParent ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; const <ISA_LIT>FrameLowering * TFI = getFrameLowering ( MF ) ; unsigned StackEst = TFI -> determineFrameLayout ( MF , false ,


<s> static SDValue emitStrictFPComparison ( SDValue LHS , SDValue RHS , const SDLoc & dl , SelectionDAG & DAG , SDValue Chain , bool IsSignaling ) { EVT VT = LHS . getValueType ( ) ; assert ( VT != <STR_LIT> ) ; const bool FullFP16 = DAG . getSubtarget < <ISA_LIT>Subtarget > ( ) . hasFullFP16 ( ) ; if ( VT == <STR_LIT> && ! FullFP16 ) { LHS = DAG . getNode ( <STR_LIT> , dl , { <STR_LIT> , <STR_LIT> } , { Chain , LHS } ) ; RHS = DAG . getNode ( <STR_LIT> , dl , { <STR_LIT> , <STR_LIT> } , { LHS . getValue ( <NUM_LIT> ) , RHS } ) ; Chain = RHS . getValue ( <NUM_LIT>


<s> const MCExpr * ImmVal ; SMLoc ExprLoc = getLoc ( ) ; if ( getParser ( ) . parseExpression ( ImmVal ) ) return MatchOperand_ParseFail ; const MCConstantExpr * MCE = dyn_cast < MCConstantExpr > ( ImmVal ) ; if ( ! MCE ) { Error ( ExprLoc , <STR_LIT> ) ; return MatchOperand_ParseFail ; } if ( MCE -> getValue ( ) < <NUM_LIT> || MCE -> getValue ( ) > <NUM_LIT> ) { Error ( ExprLoc , <STR_LIT> ) ; return MatchOperand_ParseFail ; } Operands . push_back ( <ISA_LIT>Operand :: CreateBarrier ( MCE -> getValue ( ) , ExprLoc , getContext ( ) ) ) ; return MatchOperand_Success ; } if ( Tok . isNot ( AsmToken :: Identifier ) ) { TokError ( <STR_LIT> ) ; return MatchOperand_ParseFail ; } bool Valid ; unsigned Opt = <STR_LIT> ( ) . fromString ( Tok . getString ( ) , Valid ) ; if ( ! Valid ) { TokError ( <STR_LIT> ) ; return MatchOperand_ParseFail ; } if ( Mnemonic == <STR_LIT> && Opt != <STR_LIT> ) { TokError ( <STR_LIT> ) ; return MatchOperand_ParseFail


<s> bool <ISA_LIT>TargetMachine :: addPreEmitPass ( PassManagerBase & PM ) { PM . add ( create<ISA_LIT>DelaySlotFillerPass ( * this ) ) ; return true


<s> int prev_in_use , in_use , len , ldgp ; rtx_insn * i , * next ; shorten_branches ( get_insns ( ) ) ; unsigned int option_alignment = align_functions . levels [ <NUM_LIT> ] . get_value ( ) ; if ( option_alignment < <NUM_LIT> ) align = <NUM_LIT> ; else if ( ( unsigned int ) option_alignment < max_align ) align = option_alignment ; else align = max_align ; ofs = prev_in_use = <NUM_LIT> ; i = get_insns ( ) ; if ( NOTE_P ( i ) ) i = next_nonnote_insn ( i ) ; ldgp = alpha_function_needs_gp ? <NUM_LIT> : <NUM_LIT> ; while ( i ) { next = ( * next_group ) ( i , & in_use , & len ) ; if ( LABEL_P ( i ) ) { unsigned int new_align = label_to_alignment ( i ) . levels [ <NUM_LIT> ] . get_value ( ) ; if ( new_align >= align ) { align = new_align < max_align ? new_align : max_align ; ofs = <NUM_LIT> ; } else if ( ofs & ( new_align - <NUM_LIT> ) ) ofs = ( ofs | ( new_align - <NUM_LIT> ) ) + <NUM_LIT> ; gcc_assert ( ! len ) ; } else if ( in_use == <NUM_LIT> ) { if ( len < <NUM_LIT> ) { ofs = <NUM_LIT> ; align = <NUM_LIT> ; len = <NUM_LIT> ; } } else if ( ( int ) align < len ) { unsigned int new_log_align = len > <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ; rtx_insn * prev , * where ; where = prev = prev_nonnote_insn ( i ) ; if ( ! where || ! LABEL_P ( where ) ) where = i ; if ( ! ( TARGET_EXPLICIT_RELOCS && prev && CALL_P (


<s> unsigned CC = StringSwitch < unsigned > ( Head . substr ( Head . size ( ) - <NUM_LIT> ) ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( ~ <NUM_LIT> ) ; if ( CC != ~ <NUM_LIT> ) { Head = Head . slice ( <NUM_LIT> , Head . size ( ) - <NUM_LIT> ) ; } else CC = <STR_LIT> ; <ISA_LIT>Operand :: CreateToken ( Op , Head , NameLoc ) ; Operands . push_back ( Op . take ( ) ) ; <ISA_LIT>Operand :: CreateCondCode ( Op , <STR_LIT> ( CC ) , NameLoc ) ; Operands . push_back ( Op . take ( ) ) ; while ( Next != StringRef :: npos ) { Start = Next ; Next = Name . find ( '.' , Start + <NUM_LIT> ) ; Head = Name . slice ( Start , Next ) ; <ISA_LIT>Operand :: CreateToken ( Op ,


<s> rtx_insn * r15_restore = NULL , * r11_restore = NULL ; for ( rtx_insn * insn = tail ; insn != head ; insn = PREV_INSN ( insn ) ) { rtx set = single_set ( insn ) ; if ( ! INSN_P ( insn ) || ! RTX_FRAME_RELATED_P ( insn ) || set == NULL_RTX || ! REG_P ( SET_DEST ( set ) ) || ! FP_REG_P ( SET_SRC ( set ) ) ) continue ; if ( REGNO ( SET_DEST ( set ) ) == HARD_FRAME_POINTER_REGNUM ) r11_restore = insn ; if ( REGNO ( SET_DEST ( set ) ) == STACK_POINTER_REGNUM ) r15_restore = insn ; } if ( r11_restore == NULL || r15_restore == NULL ) return ; add_dependence ( r11_restore , r15_restore , REG_DEP_ANTI


<s> unsigned <ISA_LIT>BaseInstrInfo :: isStoreToStackSlot ( const MachineInstr * MI , int & FrameIndex ) const { switch ( MI -> getOpcode ( ) ) { default : break ; case <STR_LIT> : case <STR_LIT> : if ( MI -> getOperand ( <NUM_LIT> ) . isFI ( ) && MI -> getOperand ( <NUM_LIT> ) . isReg ( ) && MI -> getOperand ( <NUM_LIT> ) . isImm ( ) && MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <NUM_LIT> && MI -> getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) { FrameIndex = MI -> getOperand ( <NUM_LIT> ) . getIndex ( ) ; return MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; } break ; case <STR_LIT> : case


<s> vqshrn_n_u64 ( uint64x2_t __a , const int __b ) { return ( uint32x2_t ) __builtin_neon_vqshrnu_nv2di ( (


<s> std :: vector < <ISA_LIT>ScheduleBlock * >

getBlocks ( ) { return BlocksScheduled ; }


<s> unsigned <ISA_LIT>InstrInfo :: removeBranch ( MachineBasicBlock & MBB , int * BytesRemoved ) const { std :: cout << <STR_LIT> << std :: endl ; return <NUM_LIT>


<s> createShuffleStride ( VT , <NUM_LIT> , VPShuf ) ; setGroupSize ( VT , GroupSize ) ; for ( int i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) DecodePALIGNRMask ( VT , GroupSize [ <NUM_LIT> - i ] , VPAlign [ i ] , false ) ; DecodePALIGNRMask ( VT , GroupSize [ <NUM_LIT> ] + GroupSize [ <NUM_LIT> ] , VPAlign2 , true , true ) ; DecodePALIGNRMask ( VT , GroupSize [ <NUM_LIT> ] , VPAlign3 , true , true ) ; concatSubVector ( Vec , InVec , VecElems , Builder ) ; for ( int i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) Vec [ i ] = Builder . CreateShuffleVector ( Vec [ i ] , VPShuf ) ; for ( int i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) TempVector [ i ] = Builder . CreateShuffleVector ( Vec [ ( i + <NUM_LIT> ) % <NUM_LIT> ] , Vec [


<s> int aarch64_fpconst_pow_of_2 ( rtx x ) { const REAL_VALUE_TYPE * r ; if ( ! CONST_DOUBLE_P ( x ) ) return


<s> bool Filled = false ; if ( <ISA_LIT>CompactBranchPolicy . getValue ( ) != CB_Always || ! TII -> getEquivalentCompactForm ( I ) ) { if ( searchBackward ( MBB , * I ) ) { LLVM_DEBUG ( dbgs ( ) << DEBUG_TYPE <STR_LIT> <STR_LIT> ) ; Filled = true ; } else if ( I -> isTerminator ( ) ) { if ( searchSuccBBs ( MBB , I ) ) { Filled = true ; LLVM_DEBUG ( dbgs ( ) << DEBUG_TYPE <STR_LIT> <STR_LIT> ) ; } } else if ( searchForward ( MBB , I ) ) { LLVM_DEBUG ( dbgs ( ) << DEBUG_TYPE <STR_LIT> <STR_LIT> ) ; Filled = true ; } } if ( Filled ) { MachineBasicBlock :: instr_iterator DSI = I . getInstrIterator ( ) ; if ( InMicro<ISA_LIT>Mode && TII -> getInstSizeInBytes ( * std :: next ( DSI ) ) == <NUM_LIT> && DSI -> isCall ( ) ) { DSI -> setDesc ( TII -> get ( getEquivalentCallShort ( DSI -> getOpcode ( ) ) ) ) ; } ++ FilledSlots


<s> unsigned R600MachineFunctionInfo :: GetIJPerspectiveIndex ( ) const { assert ( HasPerspectiveInterpolation )


<s> if ( MFI -> isPredecessor ( & * MFI ) ) { I = -- MFI -> end ( ) ; return true ; } else return false


<s> V = peekThroughBitcasts ( V ) ; MVT NewVT = V . getSimpleValueType ( ) ; if ( ! NewVT . isVector ( ) || NewVT . getScalarSizeInBits ( ) != VT . getScalarSizeInBits ( ) ) return SDValue ( ) ; if ( V . getOpcode ( ) == <STR_LIT> || ( Idx == <NUM_LIT> &&


<s> bool shouldEmitConstantsToTextSection ( const Triple & TT ) { return TT . getOS ( ) == Triple ::


<s> bool isImmSExti64i32 ( ) const { if ( ! isImm ( ) )


<s> arg_words = crtl -> args . info . arg_words ; f_stk = TYPE_FIELDS ( va_list_type_node ) ; f_reg = DECL_CHAIN ( f_stk ) ; f_ndx = DECL_CHAIN ( f_reg ) ; stk = build3 ( COMPONENT_REF , TREE_TYPE ( f_stk ) , valist , f_stk , NULL_TREE ) ; reg = build3 ( COMPONENT_REF , TREE_TYPE ( f_reg ) , unshare_expr ( valist ) , f_reg , NULL_TREE ) ; ndx = build3 ( COMPONENT_REF , TREE_TYPE ( f_ndx ) , unshare_expr ( valist ) , f_ndx , NULL_TREE ) ; u = make_tree ( sizetype , expand_builtin_saveregs ( ) ) ; u = fold_convert ( ptr_type_node , u ) ; t = build2 ( MODIFY_EXPR , ptr_type_node , reg , u ) ; TREE_SIDE_EFFECTS ( t ) = <NUM_LIT> ; expand_expr ( t , const0_rtx , VOIDmode , EXPAND_NORMAL ) ; u = make_tree ( ptr_type_node , virtual_incoming_args_rtx ) ; u = fold_build_pointer_plus_hwi ( u , - <NUM_LIT> ) ; t = build2 ( MODIFY_EXPR , ptr_type_node , stk , u ) ; TREE_SIDE_EFFECTS ( t ) = <NUM_LIT>


<s> const <ISA_LIT>InstrInfo & TII = * static_cast < const <ISA_LIT>InstrInfo * > ( MF . getTarget ( ) . getInstrInfo ( ) ) ; DebugLoc dl = MBBI -> getDebugLoc ( ) ; uint64_t StackSize = MFI -> getStackSize ( ) ; if ( ! StackSize


<s> assert ( BranchMI && isCondBranch ( BranchMI ) ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * BranchMI ) ; BranchMI -> eraseFromParent ( ) ; SHOWNEWBLK ( MBB1 , <STR_LIT> ) ; MBB -> removeSuccessor ( MBB1


<s> void <ISA_LIT>ELFStreamer :: emitCantUnwind (


<s> bool isExpCompr ( ) const { return isImmTy (


<s> rtx tem = * op0 ; * op0 = * op1 ; * op1 = tem ; * code = ( int ) swap_condition ( ( enum rtx_code ) *


<s> void <ISA_LIT>JITInfo :: replaceMachineCodeForFunction ( void * Old , void *


<s> for ( unsigned i = <NUM_LIT> ; CSRegs [ i ] ; ++ i ) if ( Reg == CSRegs [ i ] )


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return


<s> bool SVEIntrinsicOpts :: optimizeFunctions ( SmallSetVector < Function * , <NUM_LIT> > & Functions ) { bool Changed = false


<s> bool <STR_LIT> ( SDNode * N ) { if ( ! isa < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) . getNode ( ) ) ) return false ; uint64_t Index = cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) . getNode ( ) ) -> getZExtValue ( ) ; MVT VT = N -> getValueType ( <NUM_LIT> ) . getSimpleVT ( ) ; unsigned ElSize = VT . getVectorElementType ( ) . getSizeInBits ( ) ; bool Result = ( Index * ElSize ) % <NUM_LIT> == <NUM_LIT> ; return


<s> if ( Subtarget -> is64Bit ( ) ) { if ( Subtarget -> isTargetWin64


<s> void <ISA_LIT>DAGToDAGISel :: emitFunctionEntryCode ( ) { const Function & F = MF -> getFunction ( ) ; if ( F . hasExternalLinkage ( ) && F . getName ( ) ==

<STR_LIT> ) emitSpecialCodeForMain ( ) ;


<s> uint32_t S = ( offset & <NUM_LIT> ) >> <NUM_LIT> ; uint32_t J1 = ( offset & <NUM_LIT> ) >> <NUM_LIT> ; uint32_t J2 = ( offset & <NUM_LIT> ) >> <NUM_LIT> ; J1 = ( ~ J1 & <NUM_LIT> ) ; J2 = ( ~ J2 & <NUM_LIT> ) ; J1 ^= S ; J2 ^= S ; offset &= ~


<s> donelab = gen_label_rtx ( ) ; f0 = gen_reg_rtx ( mode ) ; emit_cmp_and_jump_insns ( in , const0_rtx , LT , const0_rtx , inmode , <NUM_LIT> , neglab ) ; expand_float ( out , in , <NUM_LIT> ) ; emit_jump_insn ( gen_jump ( donelab ) ) ; emit_barrier ( ) ; emit_label ( neglab ) ; i0 = expand_simple_binop ( inmode , LSHIFTRT , in , const1_rtx , NULL , <NUM_LIT> , OPTAB_DIRECT ) ; i1 = expand_simple_binop ( inmode , AND , in ,


<s> DebugLoc DL ; if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; MachineFunction * MF = MBB . getParent ( ) ; const MachineFrameInfo & MFI = MF -> getFrameInfo ( ) ; MachineMemOperand * MMO = MF -> getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( * MF , FI ) , MachineMemOperand :: MOLoad , MFI . getObjectSize ( FI ) , MFI . getObjectAlignment ( FI ) ) ; if ( RC == & <STR_LIT> ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ; } else if ( RC == & <STR_LIT> ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) .


<s> void spu_split_convert ( rtx ops [ ] ) { if ( REGNO ( ops [ <NUM_LIT> ] ) == REGNO ( ops [ <NUM_LIT> ] ) ) emit_note ( NOTE_INSN_DELETED ) ; else { rtx op0 = gen_rtx_REG ( TImode , REGNO


<s> unsigned CPI = MCP -> getConstantPoolIndex ( CPV , <NUM_LIT> ) ; const TargetRegisterClass * TRC = isThumb ? ( const TargetRegisterClass * ) & <STR_LIT> : ( const TargetRegisterClass * ) & <STR_LIT> ; MachineMemOperand * CPMMO = MF -> getMachineMemOperand ( MachinePointerInfo :: getConstantPool ( ) , MachineMemOperand :: MOLoad , <NUM_LIT> , <NUM_LIT> ) ; MachineMemOperand * FIMMOSt = MF -> getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( FI ) , MachineMemOperand :: MOStore , <NUM_LIT> , <NUM_LIT> ) ; if ( isThumb2 ) { unsigned NewVReg1 = MRI -> createVirtualRegister ( TRC ) ; AddDefaultPred ( BuildMI ( * MBB , MI , dl , TII -> get ( <STR_LIT> ) , NewVReg1 ) . addConstantPoolIndex ( CPI ) . addMemOperand ( CPMMO ) ) ; unsigned NewVReg2 = MRI -> createVirtualRegister ( TRC ) ; AddDefaultCC ( AddDefaultPred ( BuildMI ( * MBB , MI , dl , TII -> get ( <STR_LIT> ) , NewVReg2 ) . addReg ( NewVReg1 , RegState :: Kill ) . addImm ( <NUM_LIT> ) ) ) ; unsigned NewVReg3 = MRI -> createVirtualRegister ( TRC ) ; BuildMI ( * MBB , MI , dl , TII -> get ( <STR_LIT> ) , NewVReg3 ) . addReg ( NewVReg2 , RegState :: Kill ) . addImm ( PCLabelId ) ; AddDefaultPred ( BuildMI ( * MBB , MI , dl , TII -> get ( <STR_LIT> ) ) . addReg ( NewVReg3 , RegState :: Kill ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( FIMMOSt ) ) ; } else if (


<s> EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( VT != <STR_LIT> && VT != <STR_LIT> ) return SDValue ( ) ; unsigned Opc = N -> getOpcode ( ) ; SDValue Op0 = N -> getOperand ( <NUM_LIT> ) ; SDValue Op1 = N -> getOperand ( <NUM_LIT> ) ; if ( ! ( Op0 -> isDivergent ( ) ^ Op1 -> isDivergent ( ) ) ) return SDValue ( ) ; if ( Op0 -> isDivergent ( ) ) std :: swap ( Op0 , Op1 ) ; if ( Op1 . getOpcode ( ) != Opc || ! Op1 . hasOneUse ( ) ) return SDValue ( ) ; SDValue Op2 = Op1 . getOperand ( <NUM_LIT> ) ; Op1 = Op1 . getOperand ( <NUM_LIT> ) ; if ( ! ( Op1 -> isDivergent ( ) ^ Op2 -> isDivergent ( ) ) ) return SDValue ( ) ; if ( Op1 -> isDivergent ( ) ) std ::


<s> return :: isUNPCKL_v_undef_Mask ( N -> getMask ( ) , N -> getValueType


<s> bool isPostIdxReg ( ) const { return isPostIdxRegShifted ( ) && PostIdxReg . ShiftTy ==


<s> return <STR_LIT> ; case GT : return <STR_LIT> ; case GTU : return <STR_LIT> ; case LT : return <STR_LIT> ; case GE : return <STR_LIT> ; case LE : return <STR_LIT> ; case ORDERED : return <STR_LIT> ; case UNORDERED : return <STR_LIT> ; case UNEQ : return <STR_LIT> ; case UNGE : return <STR_LIT> ; case UNGT : return <STR_LIT> ; case UNLE : return <STR_LIT> ; case UNLT : return <STR_LIT> ; case LTGT : return <STR_LIT>


<s> int NewRegs = countPopulation ( NewMask . getAsInteger ( ) ) - countPopulation ( PrevMask . getAsInteger ( ) ) ; if ( SRI -> isSGPRReg ( MRI , Reg ) ) SGPRs


<s> FunctionPass * llvm :: create<ISA_LIT>SplitTFRCondSets ( const <ISA_LIT>TargetMachine


<s> void addCondCodeOperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: CreateImm ( unsigned ( getCondCode ( ) ) ) ) ; unsigned RegNum = getCondCode ( ) == <STR_LIT> ? <NUM_LIT> : <STR_LIT> ; Inst . addOperand ( MCOperand :: CreateReg ( RegNum


<s> static std :: string computeDataLayout ( const Triple & TT , StringRef


<s> bool is_bc ( unsigned a , unsigned b ,


<s> virtual MachineInstr * foldMemoryOperandImpl ( MachineFunction & MF , MachineInstr * MI , const SmallVectorImpl < unsigned >


<s> const <ISA_LIT>RegisterInfo * RI = STI . getRegisterInfo ( ) ; uint64_t FrameSize = MFI . getStackSize ( ) ; uint64_t StackAlign = RI -> needsStackRealignment ( MF ) ? MFI .

getMaxAlignment ( ) : getStackAlignment ( ) ;


<s> static bool nvptx_vector_mode_supported ( machine_mode mode


<s> if ( ! IsOptNone ) addPass ( create<ISA_LIT>PostLegalizerCombiner (


<s> return ( uint32x4_t ) __builtin_neon_vqsubuv4si ( ( int32x4_t


<s> MCSection * getSectionForConstant ( const DataLayout & DL , SectionKind Kind , const Constant *


<s> if ( ! rs6000_tls_symbol ) rs6000_tls_symbol = init_one_libfunc ( <STR_LIT> ) ; return


<s> unsigned T9 = Subtarget . isGP64bit ( ) ? <STR_LIT> : <STR_LIT> ; unsigned ZERO = Subtarget . isGP64bit ( ) ? <STR_LIT> : <STR_LIT> ; unsigned OffsetReg = I -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned TargetReg = I -> getOperand ( <NUM_LIT> ) . getReg ( ) ; const TargetMachine & TM = MBB . getParent ( ) -> getTarget ( ) ; if ( TM . getRelocationModel ( ) == Reloc :: PIC_ ) BuildMI ( MBB , I , I -> getDebugLoc ( ) , get ( ADDU ) , T9 ) . addReg ( TargetReg ) . addReg ( ZERO ) ; BuildMI ( MBB , I , I -> getDebugLoc ( ) , get ( ADDU ) , RA ) . addReg


<s> void ensure ( unsigned Idx ) { if ( size ( ) <= Idx ) resize ( std :: max ( Idx


<s> void Thumb1InstrInfo :: copyPhysReg ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , DebugLoc

DL , unsigned DestReg , unsigned SrcReg , bool KillSrc ) const {


<s> if ( PtrTy != LLT :: pointer ( <NUM_LIT> ) ) { DEBUG ( dbgs ( ) << <STR_LIT> << PtrTy << <STR_LIT> << LLT :: pointer ( <NUM_LIT> ) << '\n' ) ; return false ; } const unsigned PtrReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; const RegisterBank & PtrRB = * RBI . getRegBank ( PtrReg , MRI , TRI ) ; assert ( PtrRB . getID ( ) == <STR_LIT> && <STR_LIT> ) ; assert ( MRI . getSize ( PtrReg ) == <NUM_LIT> && <STR_LIT> ) ; const unsigned ValReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; const RegisterBank & RB = * RBI . getRegBank ( ValReg , MRI , TRI ) ; const unsigned NewOpc = selectLoadStoreUIOp ( I . getOpcode ( ) , RB . getID ( ) , MemTy . getSizeInBits ( ) ) ; if ( NewOpc == I . getOpcode ( ) ) return false ; I . setDesc ( TII . get ( NewOpc ) ) ; I . removeTypes ( ) ; I . addOperand ( MachineOperand :: CreateImm ( <NUM_LIT> ) ) ; return constrainSelectedInstRegOperands ( I , TII , TRI , RBI ) ; } case TargetOpcode :: G_MUL : { if ( unsupportedBinOp ( I , RBI , MRI , TRI ) ) return false ; const unsigned DefReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; const RegisterBank & RB = * RBI . getRegBank ( DefReg , MRI , TRI ) ; if ( RB . getID ( ) != <STR_LIT> ) { DEBUG ( dbgs ( ) << <STR_LIT> << RB << <STR_LIT> ) ; return false ; } unsigned ZeroReg ; unsigned NewOpc ; if ( Ty == LLT :: scalar ( <NUM_LIT> ) ) { NewOpc = <STR_LIT> ; ZeroReg = <STR_LIT> ; } else if ( Ty == LLT :: scalar ( <NUM_LIT> ) ) { NewOpc = <STR_LIT> ; ZeroReg = <STR_LIT> ; } else { DEBUG ( dbgs ( ) << <STR_LIT> << Ty << <STR_LIT> << LLT :: scalar ( <NUM_LIT> ) << <STR_LIT> << LLT :: scalar ( <NUM_LIT> ) << '\n' ) ; return false ; } I . setDesc ( TII . get ( NewOpc ) ) ; I . removeTypes ( ) ; I . addOperand ( MachineOperand :: CreateReg ( ZeroReg , false ) ) ; return constrainSelectedInstRegOperands ( I , TII , TRI , RBI ) ; } case TargetOpcode :: G_FADD : case TargetOpcode :: G_FSUB : case TargetOpcode :: G_FMUL : case TargetOpcode :: G_FDIV : case TargetOpcode :: G_OR : case TargetOpcode :: G_XOR : case TargetOpcode :: G_AND : case TargetOpcode :: G_SHL


<s> if ( opts -> x_align_loops <= <NUM_LIT> ) opts -> x_align_loops = aarch64_tune_params . loop_align ; if ( opts -> x_align_jumps <= <NUM_LIT> ) opts -> x_align_jumps = aarch64_tune_params . jump_align ; if ( opts -> x_align_functions <= <NUM_LIT> ) opts -> x_align_functions =


<s> if ( MF . getTarget ( ) . getMCAsmInfo ( ) -> usesWindowsCFI ( ) ) { int FrameAddrIndex = FuncInfo -> getFAIndex ( ) ; if ( ! FrameAddrIndex ) { unsigned SlotSize = RegInfo -> getSlotSize ( ) ; FrameAddrIndex = MF . getFrameInfo ( ) -> CreateFixedObject ( SlotSize , <NUM_LIT> , false ) ; FuncInfo -> setFAIndex ( FrameAddrIndex ) ; } return DAG . getFrameIndex ( FrameAddrIndex , VT ) ; } unsigned FrameReg = RegInfo -> getPtrSizedFrameRegister ( DAG . getMachineFunction ( ) ) ; SDLoc dl (


<s> const MCInstrDesc & Desc = TII . get ( TargetOpcode :: COPY ) ; TII . loadRegFromStack ( MBB , I , VR0 , FI , RC , & RegInfo , <NUM_LIT> ) ; BuildMI ( MBB , I , DL , Desc , Lo ) . addReg ( VR0 , RegState :: Kill ) ; TII . loadRegFromStack ( MBB , I , VR1 , FI , RC , & RegInfo , RegSize ) ; BuildMI ( MBB , I , DL , Desc , Hi ) . addReg ( VR1 , RegState


<s> Parser . Lex ( ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateMSRMask ( SYSmvalue , S ) ) ; return MatchOperand_Success ; } size_t Start = <NUM_LIT> , Next = Mask . find ( '_' ) ; StringRef Flags = <STR_LIT> ; std :: string SpecReg = Mask . slice ( Start , Next ) . lower ( ) ; if ( Next != StringRef :: npos ) Flags = Mask . slice ( Next + <NUM_LIT> , Mask . size ( ) ) ; unsigned FlagsVal = <NUM_LIT> ; if ( SpecReg == <STR_LIT> ) { FlagsVal = StringSwitch < unsigned > ( Flags ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT>

) . Case ( <STR_LIT> , <NUM_LIT> ) . Default ( ~ <NUM_LIT> ) ;


<s> } else { s_level = nds32_isr_secure_level ; } if ( intr != NULL_TREE && TREE_CODE ( TREE_VALUE ( TREE_VALUE ( intr ) ) ) == STRING_CST ) { tree string_arg = TREE_VALUE ( TREE_VALUE ( intr ) ) ; nds32_interrupt_attribute_parse_string ( TREE_STRING_POINTER ( string_arg ) , func_name , s_level ) ; return ; } if ( excp != NULL_TREE && TREE_CODE ( TREE_VALUE ( TREE_VALUE ( excp ) ) ) == STRING_CST ) { tree string_arg = TREE_VALUE ( TREE_VALUE ( excp ) ) ; nds32_exception_attribute_parse_string ( TREE_STRING_POINTER ( string_arg ) , func_name , s_level ) ; return ; } if ( reset != NULL_TREE && TREE_CODE ( TREE_VALUE ( TREE_VALUE ( reset ) ) ) == STRING_CST ) { tree string_arg = TREE_VALUE ( TREE_VALUE ( reset ) ) ; nds32_reset_attribute_parse_string ( TREE_STRING_POINTER ( string_arg ) , func_name ) ; return ; } if ( intr || excp ) { tree id_list ; id_list = ( intr ) ? ( TREE_VALUE ( intr ) ) : ( TREE_VALUE ( excp ) ) ; while ( id_list ) { tree id ; int vector_id ; unsigned int vector_number_offset ; vector_number_offset = ( intr ) ? ( <NUM_LIT> ) : ( <NUM_LIT> ) ; id = TREE_VALUE ( id_list ) ; vector_id = TREE_INT_CST_LOW ( id ) + vector_number_offset ; nds32_isr_vectors [ vector_id ] . security_level = s_level ; nds32_isr_vectors [ vector_id ] . category = ( intr ) ? ( NDS32_ISR_INTERRUPT ) : ( NDS32_ISR_EXCEPTION ) ; strcpy ( nds32_isr_vectors [ vector_id ] . func_name , func_name ) ; if ( save_all ) nds32_isr_vectors [ vector_id ] . save_reg = NDS32_SAVE_ALL ; else if ( partial_save ) nds32_isr_vectors [ vector_id ] . save_reg = NDS32_PARTIAL_SAVE ; if ( nested ) nds32_isr_vectors [ vector_id ] . nested_type = NDS32_NESTED ; else if ( not_nested ) nds32_isr_vectors [ vector_id ] . nested_type = NDS32_NOT_NESTED ; else if ( nested_ready ) nds32_isr_vectors [ vector_id ] . nested_type = NDS32_NESTED_READY ; else if ( critical ) nds32_isr_vectors [ vector_id ] . nested_type = NDS32_CRITICAL ; id_list = TREE_CHAIN ( id_list ) ; } } else { tree id_list ; tree id ; tree nmi , warm ; nds32_isr_vectors [ <NUM_LIT> ] . category = NDS32_ISR_RESET ; id_list = TREE_VALUE ( reset ) ; id = TREE_VALUE ( id_list ) ; nds32_isr_vectors [ <NUM_LIT> ] . total_n_vectors = TREE_INT_CST_LOW ( id


<s> unsigned <ISA_LIT>FrameLowering :: getFPReg ( const MachineFunction & MF ) { return MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . hasAddr64 ( )


<s> const char * rs6000_overloaded_builtin_name ( enum rs6000_builtins fncode ) { return rs6000_builtin_info [ ( int )


<s> MBB -> insert ( MI , EarlierMI ) ; MachineOperand & HighRegOp = EarlierMI -> getOperand ( <NUM_LIT> ) ; MachineOperand & LowRegOp = MI -> getOperand ( <NUM_LIT> ) ; HighRegOp . setReg ( RI . getSubReg ( HighRegOp . getReg ( ) , <STR_LIT> ) ) ; LowRegOp . setReg ( RI . getSubReg ( LowRegOp . getReg ( ) , <STR_LIT> ) ) ; MachineOperand & HighOffsetOp = EarlierMI -> getOperand ( <NUM_LIT> ) ; MachineOperand & LowOffsetOp = MI -> getOperand ( <NUM_LIT> ) ; LowOffsetOp . setImm ( LowOffsetOp . getImm ( ) + <NUM_LIT> ) ; EarlierMI -> getOperand ( <NUM_LIT> ) . setIsKill ( false ) ; EarlierMI -> getOperand ( <NUM_LIT> ) . setIsKill ( false ) ; unsigned HighOpcode = getOpcodeForOffset ( NewOpcode , HighOffsetOp . getImm ( ) ) ; unsigned LowOpcode = getOpcodeForOffset ( NewOpcode , LowOffsetOp . getImm ( )


<s> bool <ISA_LIT>TargetLowering :: isCFIntrinsic ( const SDNode * Intr ) const { if ( Intr -> getOpcode ( ) != <STR_LIT> ) return false ; switch ( cast < ConstantSDNode > ( Intr -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ) { default :


<s> bool J2 = ( Val & <NUM_LIT> ) ; if ( I ^ J1 ) Val &= ~ <NUM_LIT> ; else Val |= <NUM_LIT> ; if ( I ^ J2 ) Val &= ~ <NUM_LIT> ; else Val |= <NUM_LIT> ; return Val


<s> void llvm :: dumpInst ( Value * base , char * instName ) { Instruction * I = getInst ( base , instName ) ; if ( I ) I -> dump (


<s> case <STR_LIT> : case <STR_LIT> : return updateALU_r ( MI ) ; case <STR_LIT> : case <STR_LIT> : return updateARITH_i10 ( MI ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return updateSHIFT_i6 ( MI ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return updateLD ( MI ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return updateST ( MI ) ; case <STR_LIT> : return updateBRA ( MI ) ; case <STR_LIT> : return updateBAL ( MI ) ; case <STR_LIT> : return updateJAL ( MI ) ; case


<s> int maxLeadIndex ( ) const { return ( std :: max ) ( Lead [ <NUM_LIT> ] ,


<s> Stride = Builder . getInt64 ( <NUM_LIT> ) ; } ; if ( AMXCast -> getType ( ) -> is<ISA_LIT>_AMXTy ( ) ) { if ( AMXCast -> use_empty ( ) ) { AMXCast -> eraseFromParent ( ) ; return true ; } Use & U = * ( AMXCast -> use_begin ( ) ) ; unsigned OpNo = U . getOperandNo ( ) ; auto * II = dyn_cast < IntrinsicInst > ( U . getUser ( ) ) ; if ( ! II ) return false ; Prepare ( AMXCast -> getOperand ( <NUM_LIT> ) -> getType ( ) ) ; Builder . CreateStore ( Src , AllocaAddr ) ; Value * Row = nullptr , * Col = nullptr ; std :: tie ( Row , Col ) = getShape ( II , OpNo ) ; std :: array < Value * , <NUM_LIT> > Args = { Row , Col , I8Ptr , Builder . CreateSExt ( Col , Builder . getInt64Ty ( ) ) } ; Value * NewInst = Builder . CreateIntrinsic ( <STR_LIT> , None , Args ) ; AMXCast -> replaceAllUsesWith ( NewInst ) ; AMXCast -> eraseFromParent ( ) ; } else { auto * II = dyn_cast < IntrinsicInst > ( Src ) ; if ( ! II


<s> llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return


<s> bool CC_<ISA_LIT>O32_FP64 ( unsigned ValNo , MVT ValVT , MVT LocVT , CCValAssign :: LocInfo LocInfo , <STR_LIT> ArgFlags , CCState & State ) { llvm_unreachable ( <STR_LIT> )


<s> int __gthr_win32_mutex_unlock ( __gthread_mutex_t * mutex ) { if ( InterlockedDecrement ( & mutex -> counter ) >= <NUM_LIT> ) return ReleaseSemaphore ( mutex -> sema , <NUM_LIT> , NULL ) ? <NUM_LIT> : <NUM_LIT> ; else return <NUM_LIT>


<s> int spu_expand_block_move ( rtx ops [ ] ) { HOST_WIDE_INT bytes , align , offset ; rtx src , dst , sreg , dreg , target ; int i ; if ( GET_CODE ( ops [ <NUM_LIT> ] ) != CONST_INT || GET_CODE ( ops [ <NUM_LIT> ] ) != CONST_INT || INTVAL ( ops [ <NUM_LIT> ] ) > ( HOST_WIDE_INT ) ( MOVE_RATIO ( optimize_insn_for_speed_p ( ) ) * <NUM_LIT> ) ) return <NUM_LIT> ; bytes = INTVAL ( ops [ <NUM_LIT> ] ) ; align = INTVAL ( ops [ <NUM_LIT> ] ) ; if ( bytes <= <NUM_LIT> ) return <NUM_LIT> ; dst = ops [ <NUM_LIT> ] ; src = ops [ <NUM_LIT> ] ; if ( align == <NUM_LIT> ) { for ( offset = <NUM_LIT> ; offset + <NUM_LIT> <= bytes ; offset += <NUM_LIT> ) { dst = adjust_address ( ops [ <NUM_LIT> ] , V16QImode , offset ) ; src = adjust_address ( ops [ <NUM_LIT> ] , V16QImode , offset ) ; emit_move_insn ( dst , src ) ; } if ( offset < bytes )


<s> tree arg0 = CALL_EXPR_ARG ( exp , <NUM_LIT> ) ; tree arg1 = CALL_EXPR_ARG ( exp , <NUM_LIT> ) ; machine_mode tmode = insn_data [ icode ] . operand [ <NUM_LIT> ] . mode ; machine_mode mode0 = Pmode ; machine_mode mode1 = Pmode ; rtx op0 = expand_normal ( arg0 ) ; rtx op1 = expand_normal ( arg1 ) ; if ( icode == CODE_FOR_nothing ) return <NUM_LIT> ; if ( arg0 == error_mark_node || arg1 == error_mark_node ) return const0_rtx ; if ( target == <NUM_LIT> || GET_MODE ( target ) != tmode || ! ( * insn_data [ icode ] . operand [ <NUM_LIT> ] . predicate ) ( target , tmode ) ) target = gen_reg_rtx ( tmode ) ; op1 = copy_to_mode_reg ( mode1 , op1 ) ; if ( op0 == const0_rtx ) { addr = gen_rtx_MEM ( tmode , op1 ) ; } else { op0 = copy_to_mode_reg ( mode0 , op0 ) ; addr = gen_rtx_MEM ( tmode , gen_rtx_PLUS ( Pmode , op0 , op1 ) ) ; } pat = GEN_FCN ( icode ) ( target , addr ) ; if ( ! pat ) return <NUM_LIT> ; emit_insn ( pat )


<s> align_flags rx_align_for_label ( rtx_insn * lab , int


<s> case Instruction :: Xor : case Instruction :: FAdd : case Instruction :: FSub : case Instruction :: FMul : case Instruction :: FDiv : case Instruction :: ICmp : case Instruction :: FCmp : return true ; case Instruction :: Shl : case Instruction :: LShr : case Instruction :: AShr : case Instruction :: UDiv : case Instruction :: SDiv : case Instruction :: URem : case Instruction :: SRem : return Operand == <NUM_LIT> ; case Instruction :: Call : if ( auto * II = dyn_cast < IntrinsicInst > ( I ) ) { switch ( II -> getIntrinsicID ( ) ) { case <STR_LIT> : case <STR_LIT> : return Operand == <NUM_LIT> || Operand == <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return Operand == <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return Operand == <NUM_LIT> || Operand == <NUM_LIT> ; default : return false ; } } return false ; default : return false ; } } ; for ( auto OpIdx : enumerate ( I -> operands ( ) ) ) { if ( ! IsSinker ( I , OpIdx . index ( ) ) ) continue ; Instruction * Op = dyn_cast < Instruction > ( OpIdx . value ( ) . get ( ) ) ; if ( ! Op || any_of ( Ops , [ & ] ( Use * U ) { return U -> get ( ) == Op ; } ) ) continue ; if ( ! match ( Op , m_Shuffle ( m_InsertElt ( m_Undef ( ) , m_Value ( ) , m_ZeroInt ( ) ) , m_Undef ( ) , m_ZeroMask ( ) ) ) ) continue ; for ( Use & U : Op -> uses ( ) ) { Instruction * Insn = cast < Instruction > ( U . getUser ( ) ) ; if ( ! IsSinker ( Insn , U . getOperandNo ( )


<s> static SDValue LowerSUB ( SDValue Op , SelectionDAG & DAG ) { assert ( Op . getValueType ( ) . is256BitVector ( ) && Op . getValueType (


<s> SetupMachineFunction ( MF ) ; SmallString < <NUM_LIT> > Name ; get<ISA_LIT>MangledName ( Name , MF . getFunction ( ) ) ; CurrentFnSym = OutContext . getOrCreateSymbol ( Name ) ; OutStreamer -> SwitchSection ( getObjFileLowering ( ) . getTextSection ( ) ) ; EmitFunctionBody ( )


<s> static_assert ( std :: is_same < T , <STR_LIT> > :: value || std :: is_same < T , <STR_LIT> > :: value , <STR_LIT> ) ; if ( ! Subtarget . is32Bit ( ) ) return false ; if ( Args . empty ( ) )


<s> if ( TARGET_Z10 && GET_MODE_SIZE ( mode ) == <NUM_LIT> ) { if ( reg_classes_intersect_p ( from , GENERAL_REGS ) && reg_classes_intersect_p ( to , FP_REGS ) ) return <NUM_LIT> ; if ( reg_classes_intersect_p ( to , GENERAL_REGS ) && reg_classes_intersect_p ( from , FP_REGS ) ) return <NUM_LIT> ; } if ( ( reg_classes_intersect_p ( from , GENERAL_REGS ) && reg_classes_intersect_p ( to , FP_REGS ) ) || ( reg_classes_intersect_p ( from , FP_REGS ) && reg_classes_intersect_p ( to , GENERAL_REGS )


<s> Opc = IsD16 ? <STR_LIT> : <STR_LIT> ; } else if ( IsFormat ) { Opc = IsD16 ? <STR_LIT> : <STR_LIT> ; } else { switch ( MemTy . getSizeInBits ( ) ) { case <NUM_LIT> : Opc = <STR_LIT> ; break ; case <NUM_LIT> : Opc = <STR_LIT> ; break ; default : Opc = <STR_LIT> ; break ; } } Register LoadDstReg ; bool IsExtLoad = ( ! IsD16 && MemTy . getSizeInBits ( ) < <NUM_LIT> ) || ( IsD16 && ! Ty . isVector ( ) ) ; LLT UnpackedTy = Ty . changeElementSize ( <NUM_LIT> ) ; if ( IsExtLoad ) LoadDstReg = B . getMRI ( ) -> createGenericVirtualRegister ( S32 ) ; else if ( Unpacked && IsD16 && Ty . isVector ( ) ) LoadDstReg = B . getMRI ( ) -> createGenericVirtualRegister ( UnpackedTy ) ; else LoadDstReg = Dst ; auto MIB = B . buildInstr ( Opc ) . addDef ( LoadDstReg ) . addUse ( RSrc ) . addUse ( VIndex ) . addUse ( VOffset ) . addUse ( SOffset ) . addImm ( ImmOffset ) ; if ( IsTyped ) MIB . addImm ( Format ) ; MIB . addImm ( AuxiliaryData ) . addImm ( HasVIndex ? - <NUM_LIT> : <NUM_LIT> ) . addMemOperand ( MMO ) ; if ( LoadDstReg != Dst ) { B . setInsertPt ( B . getMBB ( ) , ++ B . getInsertPt ( ) ) ; if ( IsExtLoad ) B . buildTrunc ( Dst , LoadDstReg ) ; else { auto Unmerge = B . buildUnmerge ( S32 , LoadDstReg ) ; SmallVector < Register ,


<s> if ( MO . getTargetFlags ( ) & <STR_LIT> ) { auto MOFrag = ( MO . getTargetFlags ( ) & <STR_LIT> ) ; if ( MOFrag == <STR_LIT> || MOFrag == <STR_LIT> || MOFrag == <STR_LIT> || MOFrag == <STR_LIT> ) RefFlags |= <ISA_LIT>MCExpr :: VK_NC ; } const MCExpr * Expr = MCSymbolRefExpr :: create ( Sym , MCSymbolRefExpr :: VK_None , Ctx ) ; if ( ! MO . isJTI ( ) && MO . getOffset ( ) ) Expr = MCBinaryExpr :: createAdd ( Expr , MCConstantExpr :: create ( MO . getOffset ( ) , Ctx ) , Ctx ) ; auto RefKind = static_cast < <ISA_LIT>MCExpr ::


<s> static bool c6x_return_in_msb ( const_tree valtype ) { HOST_WIDE_INT size = int_size_in_bytes ( valtype )


<s> switch ( VT . getSimpleVT ( ) . SimpleTy ) { default : return TargetLowering :: findRepresentativeClass ( VT ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : RRC = Subtarget -> is64Bit ( ) ? ( const TargetRegisterClass * ) & <STR_LIT> : ( const TargetRegisterClass * ) & <STR_LIT> ; break ; case <STR_LIT>


<s> Register SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; bool DstIsDead = MI . getOperand ( <NUM_LIT> ) . isDead ( ) ; bool DstIsKill = MI . getOperand ( <NUM_LIT> ) . isKill ( ) ; bool SrcIsKill = MI . getOperand ( <NUM_LIT> ) . isKill ( ) ; bool ImpIsDead = MI . getOperand ( <NUM_LIT> ) . isDead ( ) ; TRI -> splitReg ( SrcReg , SrcLoReg , SrcHiReg ) ; TRI -> splitReg ( DstReg , DstLoReg , DstHiReg ) ; buildMI ( MBB , MBBI , OpLo ) . addReg ( DstLoReg , RegState :: Define | getDeadRegState ( DstIsDead ) ) . addReg ( DstLoReg , getKillRegState (

DstIsKill ) ) . addReg ( SrcLoReg , getKillRegState ( SrcIsKill ) ) ;


<s> for ( SDValue & Op : Ops ) if ( Op . getValueType ( ) != VT ) Op = DAG . getNode ( <STR_LIT> , DL , VT , Op ) ; unsigned NumElemsPow2 = PowerOf2Ceil ( NumElems ) ; EVT Pow2VT = EVT :: getVectorVT ( * DAG . getContext ( ) , ScalarVT , NumElemsPow2 ) ; if ( NumElemsPow2 != NumElems ) { for ( SDValue & Op : Ops ) { SmallVector < SDValue , <NUM_LIT> > EltsOfOp ( NumElemsPow2 , DAG . getUNDEF ( ScalarVT ) ) ; for ( unsigned i = <NUM_LIT> ; i != NumElems ; ++ i ) { SDValue Idx = DAG . getIntPtrConstant ( i , DL ) ; EltsOfOp [ i ] = DAG . getNode ( <STR_LIT> , DL , ScalarVT , Op , Idx ) ; } Op = DAG . getBuildVector ( Pow2VT , DL , EltsOfOp ) ; } } SDValue Res = SplitOpsAndApply ( DAG , Subtarget , DL , Pow2VT , Ops , AVGBuilder ) ; if ( NumElemsPow2 == NumElems ) return Res ; return DAG . getNode ( <STR_LIT> , DL , VT , Res , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; } ; if ( IsConstVectorInRange ( Operands [ <NUM_LIT> ] , <NUM_LIT> , ScalarVT == <STR_LIT> ? <NUM_LIT> : <NUM_LIT> ) && IsZExtLike ( Operands [ <NUM_LIT> ] ) ) { SDValue VecOnes = DAG . getConstant ( <NUM_LIT> , DL , InVT ) ; Operands [ <NUM_LIT> ] = DAG . getNode ( <STR_LIT> , DL , InVT , Operands [ <NUM_LIT> ] , VecOnes ) ; return AVGSplitter ( { Operands [ <NUM_LIT> ] , Operands [ <NUM_LIT> ] } ) ; } auto FindAddLike = [ & ] ( SDValue V , SDValue & Op0 , SDValue & Op1 ) { if ( <STR_LIT> == V . getOpcode ( ) ) { Op0 = V . getOperand ( <NUM_LIT> ) ; Op1 = V . getOperand ( <NUM_LIT> ) ; return true ; } if ( <STR_LIT> != V . getOpcode ( ) ) return false ; V = V . getOperand ( <NUM_LIT> ) ; if ( V . getValueType ( ) != VT || <STR_LIT> != V . getOpcode ( ) || ! DAG . haveNoCommonBitsSet ( V . getOperand ( <NUM_LIT> ) , V . getOperand ( <NUM_LIT> ) ) ) return false ; Op0 = V . getOperand ( <NUM_LIT> ) ; Op1 = V . getOperand ( <NUM_LIT> ) ; return true ; } ; SDValue Op0 , Op1 ; if ( FindAddLike ( Operands [ <NUM_LIT> ] , Op0 , Op1 ) ) std :: swap ( Operands [ <NUM_LIT> ] ,


<s> bool <ISA_LIT>FastISel :: SelectFPTrunc ( const Instruction * I ) { Value * Src = I -> getOperand ( <NUM_LIT> ) ; EVT SrcVT = TLI . getValueType ( DL , Src -> getType ( ) , true ) ; EVT DestVT = TLI . getValueType ( DL , I -> getType ( ) , true ) ; if ( SrcVT != <STR_LIT> || DestVT != <STR_LIT> ) return false ; unsigned SrcReg = getRegForValue ( Src ) ; if ( ! SrcReg ) return false ; unsigned DestReg ; auto RC = MRI . getRegClass ( SrcReg ) ; if ( <ISA_LIT>SubTarget -> hasSPE ( ) ) { DestReg = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , DestReg )


<s> void AMDGPUCFGStructurizer :: cloneSuccessorList ( MachineBasicBlock * DstMBB , MachineBasicBlock * SrcMBB ) { for ( MachineBasicBlock :: succ_iterator It = SrcMBB -> succ_begin ( ) , iterEnd = SrcMBB -> succ_end ( ) ; It != iterEnd ; ++


<s> while ( <NUM_LIT> ) ; } return ( n == <NUM_LIT> ) ? <NUM_LIT> : <NUM_LIT> + intlog2 ( n


<s> <ISA_LIT>FunctionInfo * FI = DAG . getMachineFunction ( ) . getInfo < <ISA_LIT>FunctionInfo > ( ) ; return DAG . getRegister ( FI -> getGlobalBaseReg


<s> OpRef C = contracting ( SM , Va , Vb , Results ) ; if ( C . isValid ( ) ) return C ; int VecLen = SM . Mask . size ( ) ; SmallVector < int , <NUM_LIT> > PackedMask ( VecLen ) ; OpRef P = packs ( SM , Va , Vb , Results , PackedMask ) ; if ( P . isValid ( ) ) return shuffs1 ( ShuffleMask ( PackedMask ) , P , Results ) ; SmallVector < int , <NUM_LIT> > MaskL ( VecLen ) , MaskR ( VecLen ) ; splitMask ( SM . Mask , MaskL , MaskR ) ; OpRef L = shuffs1 ( ShuffleMask ( MaskL ) , Va , Results ) ; OpRef R = shuffs1 ( ShuffleMask ( MaskR ) , Vb , Results ) ; if ( ! L . isValid ( ) || ! R . isValid ( ) ) return OpRef :: fail ( ) ; SmallVector < uint8_t , <NUM_LIT> > Bytes ( VecLen ) ; for ( int I = <NUM_LIT> ; I != VecLen ; ++ I ) { if ( MaskL [ I ] != - <NUM_LIT> ) Bytes [ I


<s> void resetStackModelComment ( const MachineInstr * MI , const std :: string


<s> if ( G1 -> requiresFixup ( ) != G2 -> requiresFixup ( ) ) return G1 -> requiresFixup ( ) > G2 -> requiresFixup ( ) ; assert ( ( G1 == G2 || ( G1 -> startsBefore ( G2 ) ^ G2 -> startsBefore ( G1 ) ) ) && <STR_LIT> ) ; return G1 -> startsBefore ( G2 ) ; } ) ; Color PreferredColor = Parity < <NUM_LIT> ? Color :: Even : Color :: Odd ; while ( Chain * G = getAndEraseNext ( PreferredColor , GV ) ) { Color C = PreferredColor ; if ( Parity == <NUM_LIT> ) C =


<s> unsigned MyPredReg = <NUM_LIT> ; if ( ! MI ) return false ; if ( MI -> getOpcode ( ) != <STR_LIT> && MI -> getOpcode ( ) != <STR_LIT> && MI -> getOpcode ( ) != <STR_LIT> && MI -> getOpcode ( ) != <STR_LIT> && MI -> getOpcode ( ) != <STR_LIT> ) return false ; if ( Bytes <= <NUM_LIT> || ( Limit && Bytes >= Limit ) ) return false ; unsigned Scale = ( MI -> getOpcode ( ) == <STR_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; return ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == Base && MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == Base && ( MI -> getOperand ( <NUM_LIT> ) . getImm ( )

* Scale ) == Bytes && llvm :: getInstrPredicate ( MI , MyPredReg ) == Pred && MyPredReg == PredReg ) ;


<s> static DecodeStatus DecodeVecShiftLImm ( llvm :: MCInst & Inst , unsigned Imm ,


<s> emit_jump_insn ( gen_rtx_SET ( VOIDmode , pc_rtx , gen_rtx_IF_THEN_ELSE ( VOIDmode , condition_rtx ,


<s> bool <ISA_LIT>InstrInfo :: isSchedulingBoundary ( const MachineInstr & MI , const MachineBasicBlock * MBB , const MachineFunction & MF ) const { if ( MI . isTerminator ( ) || MI . isPosition ( ) ) return


<s> if ( Disp . getImm ( ) != <NUM_LIT> ) O << Disp . getImm ( ) ; } if ( Base . getReg ( ) ) O << '[' << getRegisterName (


<s> assert ( ! isSoloInstruction ( MI ) && <STR_LIT> ) ; if ( MI -> isDebugValue ( ) ) { return true


<s> virtual bool isShuffleMaskLegal ( const SmallVectorImpl < int > &


<s> case CCValAssign :: AExt : Arg = DAG . getNode ( <STR_LIT> , dl , VA . getLocVT ( ) , Arg ) ; break ; case CCValAssign :: ZExt : Arg = DAG . getNode ( <STR_LIT> , dl , VA . getLocVT ( ) , Arg ) ; break ; case CCValAssign :: SExt : Arg = DAG . getNode ( <STR_LIT> , dl , VA . getLocVT ( ) , Arg ) ; break ; } if ( Subtarget . hasSPE ( ) && VA . getLocVT ( ) == <STR_LIT> ) { bool isLittleEndian = Subtarget . isLittleEndian ( ) ; SDValue SVal = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Arg , DAG . getIntPtrConstant ( isLittleEndian ? <NUM_LIT> : <NUM_LIT> , dl ) ) ; Chain = DAG . getCopyToReg ( Chain , dl , VA . getLocReg ( ) , SVal , Flag ) ; RetOps . push_back ( DAG . getRegister ( VA . getLocReg ( ) , VA . getLocVT ( ) ) ) ; SVal = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Arg , DAG . getIntPtrConstant ( isLittleEndian ? <NUM_LIT> : <NUM_LIT> , dl ) ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; VA = RVLocs [ ++ i ] ; Chain = DAG . getCopyToReg ( Chain , dl , VA . getLocReg ( ) , SVal , Flag ) ; } else Chain = DAG . getCopyToReg ( Chain , dl , VA . getLocReg ( ) , Arg , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( VA . getLocReg ( ) , VA . getLocVT ( ) ) ) ; } const <ISA_LIT>RegisterInfo * TRI = Subtarget . getRegisterInfo ( ) ; const MCPhysReg * I = TRI -> getCalleeSavedRegsViaCopy ( & DAG . getMachineFunction ( ) ) ; if ( I ) { for ( ; * I ; ++ I ) { if ( <STR_LIT> . contains ( * I ) ) RetOps . push_back ( DAG . getRegister ( * I , <STR_LIT> ) ) ; else if ( <STR_LIT> . contains ( * I ) ) RetOps . push_back ( DAG . getRegister ( * I , <STR_LIT> ( <NUM_LIT> ) ) ) ; else if ( <STR_LIT> . contains ( * I ) ) RetOps . push_back ( DAG . getRegister ( * I , <STR_LIT> ) ) ; else if ( <STR_LIT> . contains ( * I ) ) RetOps . push_back ( DAG . getRegister ( *


<s> LandingPadInst * LP = nullptr ; for ( BasicBlock & BB : F ) { LP = BB . getLandingPadInst ( ) ; if ( LP ) break ; } if ( ! LP ) return false ; PersonalityFn = dyn_cast < Function > ( LP -> getPersonalityFn ( ) -> stripPointerCasts ( ) ) ; if ( ! PersonalityFn ) return false ; Personality = classifyEHPersonality ( PersonalityFn ) ; if ( ! isMSVCEHPersonality ( Personality ) ) return false ; F . addFnAttr ( <STR_LIT> , <STR_LIT> ) ; emitExceptionRegistrationRecord ( & F ) ; auto * MMIPtr = getAnalysisIfAvailable < MachineModuleInfo > ( ) ; assert ( MMIPtr &&


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return Opc ; case <STR_LIT> : return <STR_LIT>


<s> addPass ( & <ISA_LIT>PerfHintAnalysisID ) ; TargetPassConfig :: addCodeGenPrepare ( ) ; if ( EnableLoadStoreVectorizer ) addPass ( createLoadStoreVectorizerPass ( ) ) ; addPass ( createLowerSwitchPass


<s> const MCAsmInfo * MAI = Streamer . getContext ( ) . getAsmInfo ( ) ; const char * Directive = MAI -> getData8bitsDirective ( ) ; unsigned NumElements = Data . size ( ) ; const unsigned MaxLen = <NUM_LIT> ; unsigned NumChunks = <NUM_LIT> + ( ( NumElements - <NUM_LIT> ) / MaxLen ) ; for ( unsigned I = <NUM_LIT> ; I < NumChunks ; ++ I ) { SmallString < <NUM_LIT> > Str ; raw_svector_ostream OS ( Str ) ; const char * Label = Directive ; for ( auto It = std :: next ( Data . bytes_begin ( ) , I * MaxLen ) , End = ( I == NumChunks - <NUM_LIT> ) ? Data . bytes_end ( ) : std :: next ( Data . bytes_begin ( ) , ( I + <NUM_LIT> ) * MaxLen ) ; It != End ;


<s> if ( MO . isImm ( ) ) O << ( unsigned short


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , Optional < CodeModel :: Model > CM , CodeGenOpt :: Level OL , bool JIT ) : LLVMTargetMachine ( T , computeDataLayout ( TT ) , TT , CPU , FS , Options , getEffectiveRelocModel ( TT ,

RM ) , getEffectiveCodeModel ( CM , CodeModel :: Small ) , OL ) , TLOF ( std :: make_unique < <ISA_LIT>ELFTargetObjectFile > ( ) ) , Subtarget ( TT , CPU , FS , Options . MCOptions . getABIName ( ) , * this ) {


<s> if ( Ret -> getNumOperands ( ) > <NUM_LIT> ) { CallingConv :: ID CC = F . getCallingConv ( ) ; SmallVector < <STR_LIT> , <NUM_LIT> > Outs ; GetReturnInfo ( CC , F . getReturnType ( ) , F . getAttributes ( ) , Outs , TLI , DL ) ; SmallVector < CCValAssign , <NUM_LIT> > ValLocs ; CCState CCInfo ( CC , F . isVarArg ( ) , * FuncInfo . MF , ValLocs , I -> getContext ( ) ) ; CCAssignFn * RetCC = CC == CallingConv :: WebKit_JS ? RetCC_<ISA_LIT>_WebKit_JS : RetCC_<ISA_LIT>_AAPCS ; CCInfo . AnalyzeReturn ( Outs , RetCC ) ; if ( ValLocs . size ( ) != <NUM_LIT> ) return false ; CCValAssign & VA = ValLocs [ <NUM_LIT> ] ; const Value * RV = Ret -> getOperand ( <NUM_LIT> ) ; if ( ( VA . getLocInfo ( ) != CCValAssign :: Full ) && ( VA . getLocInfo ( ) != CCValAssign :: BCvt ) ) return false ; if ( ! VA . isRegLoc ( ) ) return false ; unsigned Reg = getRegForValue ( RV ) ; if ( Reg == <NUM_LIT> ) return false ; unsigned SrcReg = Reg + VA . getValNo ( ) ; Register DestReg = VA . getLocReg ( ) ; if ( ! MRI . getRegClass ( SrcReg ) -> contains ( DestReg ) ) return false ; EVT RVEVT = TLI . getValueType ( DL , RV -> getType ( ) ) ; if ( ! RVEVT . isSimple ( ) ) return false ; if ( RVEVT . isVector ( ) && RVEVT . getVectorNumElements ( ) > <NUM_LIT> && ! Subtarget -> isLittleEndian ( ) ) return false ; MVT RVVT = RVEVT . getSimpleVT ( ) ; if ( RVVT == <STR_LIT> ) return false ; MVT DestVT = VA . getValVT ( ) ; if ( RVVT != DestVT ) { if ( RVVT != <STR_LIT> && RVVT != <STR_LIT> && RVVT != <STR_LIT> ) return false ; if ( ! Outs [ <NUM_LIT> ] . Flags . isZExt ( ) && ! Outs [ <NUM_LIT> ] . Flags . isSExt ( ) ) return false ; bool IsZExt = Outs [ <NUM_LIT> ] . Flags . isZExt ( ) ; SrcReg = emitIntExt ( RVVT , SrcReg , DestVT , IsZExt ) ; if ( SrcReg == <NUM_LIT> ) return false ; } BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: COPY ) , DestReg ) . addReg ( SrcReg ) ; RetRegs . push_back ( VA . getLocReg ( ) ) ; } MachineInstrBuilder MIB = BuildMI ( * FuncInfo . MBB , FuncInfo .

InsertPt , DbgLoc , TII . get ( <STR_LIT> ) ) ;


<s> const DataLayout * getDataLayout ( ) const override { return &


<s> MVT InVT = In . getSimpleValueType ( ) ; MVT VTElt = VT . getVectorElementType ( ) ; MVT InVTElt = InVT . getVectorElementType ( ) ; SDLoc dl ( Op ) ; if ( ( InVTElt == <STR_LIT> ) && ( ( ( Subtarget -> hasBWI ( ) && Subtarget -> hasVLX ( ) && VT . getSizeInBits ( ) <= <NUM_LIT> && VTElt . getSizeInBits ( ) <= <NUM_LIT> ) ) || ( ( Subtarget -> hasBWI ( ) && VT . is512BitVector ( ) && VTElt . getSizeInBits ( ) <= <NUM_LIT> ) ) || ( ( Subtarget -> hasDQI ( ) && Subtarget -> hasVLX ( ) && VT . getSizeInBits ( ) <= <NUM_LIT> && VTElt . getSizeInBits ( ) >= <NUM_LIT> ) ) || ( ( Subtarget -> hasDQI ( ) && VT . is512BitVector ( ) && VTElt . getSizeInBits ( ) >= <NUM_LIT> ) ) ) ) return DAG . getNode ( <STR_LIT> , dl , VT , In ) ; unsigned int NumElts = VT . getVectorNumElements ( ) ; if ( NumElts != <NUM_LIT> && NumElts != <NUM_LIT> ) return SDValue ( ) ; if ( VT . is512BitVector ( ) && InVT . getVectorElementType ( ) != <STR_LIT> ) { if ( In . getOpcode ( ) == <STR_LIT> || In . getOpcode ( ) == <STR_LIT> ) return DAG . getNode ( In . getOpcode ( ) , dl , VT ,


<s> EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( VT == <STR_LIT> ) return ! hasFP32Denormals ( DAG . getMachineFunction ( ) ) ; if ( VT == <STR_LIT>


<s> return __builtin_mve_vcaddq_rot90_sv8hi ( __a ,


<s> Rsrc = buildScratchRSRC ( CurDAG , DL , CurDAG -> getCopyFromReg ( CurDAG -> getEntryNode ( ) , DL , MRI . getLiveInVirtReg ( ScratchPtrReg ) , <STR_LIT> ) ) ; SOffset = CurDAG -> getCopyFromReg ( CurDAG -> getEntryNode ( ) , DL , MRI . getLiveInVirtReg ( ScratchOffsetReg ) , <STR_LIT> ) ; if ( CurDAG -> isBaseWithConstantOffset ( Addr ) ) { SDValue N1 = Addr . getOperand ( <NUM_LIT> ) ; ConstantSDNode * C1 = cast < ConstantSDNode > ( N1 ) ; if ( isLegalMUBUFImmOffset ( C1 ) ) { VAddr = Addr . getOperand ( <NUM_LIT> ) ; ImmOffset = CurDAG -> getTargetConstant ( C1 -> getZExtValue ( ) , <STR_LIT> ) ; return true ; } } if ( ( Addr . getOpcode ( ) == <STR_LIT> || Addr . getOpcode ( ) == <STR_LIT> ) && isa < FrameIndexSDNode > ( Addr . getOperand ( <NUM_LIT> ) ) ) { VAddr = Addr . getOperand ( <NUM_LIT> ) ; ImmOffset = Addr . getOperand ( <NUM_LIT> ) ; return true ; } if ( isa < FrameIndexSDNode > ( Addr


<s> int pa_emit_hpdiv_const ( rtx * operands , int unsignedp ) { if ( GET_CODE ( operands [ <NUM_LIT> ] ) == CONST_INT && INTVAL ( operands [ <NUM_LIT> ] ) > <NUM_LIT> && INTVAL ( operands [ <NUM_LIT> ] ) < <NUM_LIT> && pa_magic_milli [ INTVAL ( operands [ <NUM_LIT> ] ) ] ) { rtx ret = gen_rtx_REG ( SImode , TARGET_64BIT ?


<s> if ( ! isTypeLegal ( <STR_LIT> ) || ( VT != <STR_LIT> && ( ( VT != <STR_LIT> && VT != <STR_LIT> ) || ! Subtarget . hasVSX ( ) ) ) ) return SDValue ( ) ; SDLoc DL ( Op ) ; SDValue FTSQRT = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op ) ; SDValue SRIdxVal = DAG . getTargetConstant (


<s> MI . eraseFromParent ( ) ; Offset = StackOffset ( ) ; return true ; } int64_t NewOffset ; unsigned UnscaledOp ; bool UseUnscaledOp ; int Status = is<ISA_LIT>FrameOffsetLegal ( MI , Offset , & UseUnscaledOp , & UnscaledOp , & NewOffset ) ; if ( Status & <ISA_LIT>FrameOffsetCanUpdate ) { if ( Status & <ISA_LIT>FrameOffsetIsLegal ) MI . getOperand ( FrameRegIdx ) . ChangeToRegister ( FrameReg , false ) ; if ( UseUnscaledOp ) MI . setDesc ( TII -> get ( UnscaledOp ) ) ; MI . getOperand ( ImmIdx ) . ChangeToImmediate ( NewOffset ) ; return !


<s> static const uint16_t CalleeSavedRegs [ ] = {


<s> case <STR_LIT> : return - <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : { uint64_t D = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned Lo = D & <NUM_LIT> ; unsigned Hi = D >> <NUM_LIT> ; return profitImm ( Lo , Hi ) ; } case <STR_LIT> : case <STR_LIT> : return profitImm ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) , MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; case <STR_LIT> : ImmX ++ ; case <STR_LIT> : { ImmX ++ ; int64_t V = MI -> getOperand ( ImmX ) . getImm ( ) ; if ( V == <NUM_LIT> || V == - <NUM_LIT> ) return <NUM_LIT> ; } case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : { unsigned S = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( S == <NUM_LIT> || S == <NUM_LIT> ) return <NUM_LIT> ; return - <NUM_LIT> ; } case <STR_LIT>


<s> return <ISA_LIT>II :: getImmEnd ( getDesc ( MCII , MCI )


<s> if ( RECORD_OR_UNION_TYPE_P ( type ) ) { msize = int_size_in_bytes ( type ) ; } } return msize != <NUM_LIT> && msize != <NUM_LIT> && msize != <NUM_LIT> && msize != <NUM_LIT> ; } else if ( arg . type && int_size_in_bytes ( arg . type ) == - <NUM_LIT> ) return true ; } return


<s> if ( ! isTypeLegal ( EVT :: getEVT ( Ty1 ) ) ) return false ; assert ( Ty1 -> getPrimitiveSizeInBits ( ) <= <NUM_LIT>


<s> if ( TARGET_SIMD ) { if ( aarch64_evpc_rev ( d ) ) return true ; else if ( aarch64_evpc_ext ( d ) ) return true ; else if ( aarch64_evpc_dup ( d ) ) return true ; else if ( aarch64_evpc_zip ( d ) ) return true ; else if ( aarch64_evpc_uzp ( d ) ) return


<s> if ( IDVal == <STR_LIT> ) return ParseDirective<ISA_LIT>HsaKernel ( ) ; if ( IDVal == <STR_LIT> ) return ParseDirectiveISAVersion ( ) ; if ( IDVal == <STR_LIT> :: AssemblerDirectiveBegin )


<s> else if ( GET_MODE_CLASS ( mode ) == MODE_COMPLEX_FLOAT ) { if ( is_ha != NULL ) * is_ha = true ; * count = <NUM_LIT> ; new_mode = GET_MODE_INNER ( mode ) ; } else if ( type && composite_p ) { int ag_count = aapcs_vfp_sub_candidate ( type , & new_mode ) ; if ( ag_count > <NUM_LIT> &&


<s> void <ISA_LIT>PostSelectOptimize :: getAnalysisUsage ( AnalysisUsage & AU ) const { AU . addRequired < TargetPassConfig > ( ) ; AU . setPreservesCFG (


<s> GCNSubtarget :: Generation Generation = ST . getGeneration ( ) ; if ( ST . hasGFX940Insts ( ) ) return std :: make_unique < <ISA_LIT>Gfx940CacheControl > ( ST ) ; if ( ST . hasGFX90AInsts ( ) ) return std :: make_unique < <ISA_LIT>Gfx90ACacheControl > ( ST ) ; if ( Generation <= <ISA_LIT>Subtarget :: SOUTHERN_ISLANDS ) return std

:: make_unique < <ISA_LIT>Gfx6CacheControl > ( ST ) ;


<s> unsigned <ISA_LIT>TTIImpl :: getMaxInterleaveFactor ( unsigned VF ) { if ( VF == <NUM_LIT> )


<s> } else if ( Op . isImm ( ) ) { O << ( uint32_t ) Op . getImm ( ) ; } else { assert ( Op . isExpr ( ) && <STR_LIT> ) ; Op . getExpr ( ) -> print ( O , &


<s> return ( __m512i ) __builtin_ia32_inserti32x4_mask ( ( __v16si ) __C , ( __v4si )


<s> return ( poly64x2_t ) __builtin_neon_vld1_lanev2di ( ( const __builtin_neon_di * )


<s> bool RHSSeenZero = false ; bool RHSOk = canChangeToInt ( RHS , RHSSeenZero , Subtarget ) ; if ( LHSOk && RHSOk && ( LHSSeenZero || RHSSeenZero ) ) { if ( CC == <STR_LIT> ) CC = <STR_LIT> ; else if ( CC == <STR_LIT> ) CC = <STR_LIT> ; SDValue Mask = DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ; SDValue <ISA_LIT>cc ; if ( LHS . getValueType ( ) == <STR_LIT> ) { LHS = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , bitcastf32Toi32 ( LHS , DAG ) , Mask ) ; RHS = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , bitcastf32Toi32 ( RHS , DAG ) , Mask ) ; SDValue Cmp = get<ISA_LIT>Cmp ( LHS , RHS , CC , <ISA_LIT>cc , DAG , dl ) ; SDValue CCR = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Chain , Dest , <ISA_LIT>cc , CCR , Cmp ) ; } SDValue LHS1 , LHS2 ; SDValue RHS1 , RHS2 ; expandf64Toi32 ( LHS , DAG , LHS1 , LHS2 ) ; expandf64Toi32 ( RHS , DAG , RHS1


<s> static void fold_compare_helper ( gimple_stmt_iterator * gsi , tree_code code , gimple * stmt ) { tree arg0 = gimple_call_arg ( stmt , <NUM_LIT> ) ; tree arg1 = gimple_call_arg ( stmt , <NUM_LIT> ) ; tree lhs = gimple_call_lhs ( stmt ) ; tree cmp = fold_build_vec_cmp ( code , TREE_TYPE ( lhs ) , arg0 , arg1 , gsi ) ; gimple * g = gimple_build_assign (


<s> bool <ISA_LIT>PassConfig :: addInstSelector ( ) { PM -> add ( create<ISA_LIT>ISelDag ( get<ISA_LIT>TargetMachine ( )


<s> loongarch_emit_move ( mem , reg ) ; loongarch_set_frame_expr ( loongarch_frame_set ( mem , reg )


<s> if ( ! HasV6T2Ops && hasThumb2 ( ) ) HasV4TOps = HasV5TOps = HasV5TEOps = HasV6Ops = HasV6T2Ops = true ; SchedModel = getSchedModelForCPU ( CPUString ) ; InstrItins = getInstrItineraryForCPU ( CPUString ) ; if ( ( TargetTriple . getTriple ( ) . find ( <STR_LIT> ) != std :: string :: npos ) || ( isTargetIOS ( ) && isMClass ( ) ) ) TargetABI = <ISA_LIT>_ABI_AAPCS ; if ( isAAPCS_ABI ( ) ) stackAlignment = <NUM_LIT> ; if ( ! isTargetIOS ( ) ) UseMovt = hasV6T2Ops ( ) ; else { IsR9Reserved = ReserveR9 | ! HasV6Ops ; UseMovt = DarwinUseMOVT && hasV6T2Ops ( ) ; SupportsTailCall = ! getTargetTriple ( ) . isOSVersionLT ( <NUM_LIT> , <NUM_LIT> ) ; } if ( isTargetNaCl ( ) ) stackAlignment = <NUM_LIT> ; if ( isTargetNaCl ( ) && ! useConstPool ( ) ) UseMovt = true ; if ( ! isThumb ( ) || hasThumb2 ( ) ) PostRAScheduler = true ; switch ( Align ) { case DefaultAlign : AllowsUnalignedMem = ( ( hasV7Ops ( ) && ( isTargetLinux ( ) || isTargetNaCl ( ) )

) || ( hasV6Ops ( ) && isTargetDarwin ( ) ) ) ;


<s> switch ( MI . getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case


<s> static DecodeStatus DecodeACRegsDSPRegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t Address , const void * Decoder ) { if ( RegNo >= <NUM_LIT> ) return MCDisassembler


<s> const <ISA_LIT>InstrInfo * QII = ( const <ISA_LIT>InstrInfo * ) TII ; const <ISA_LIT>RegisterInfo * QRI = ( const <ISA_LIT>RegisterInfo * ) TM . getRegisterInfo ( ) ; if ( ! QRI -> Subtarget . hasV4TOps ( ) || ! QII -> mayBeNewStore ( MI ) ) return false ; MachineInstr * PacketMI = PacketSU


<s> void <ISA_LIT>TargetLowering :: addTypeForFixedLengthSVE ( MVT VT ) { assert ( VT . isFixedLengthVector ( ) && <STR_LIT> ) ; for ( unsigned Op = <NUM_LIT> ; Op < <STR_LIT> ; ++ Op ) setOperationAction ( Op , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT


<s> const Value * SV = cast < SrcValueSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getValue ( ) ; return DAG . getStore ( Op . getOperand ( <NUM_LIT> ) , DL , FR , Op . getOperand ( <NUM_LIT> )


<s> AU . addRequired < TargetLibraryInfoWrapperPass > ( ) ; AU . addRequired < LoopInfoWrapperPass > ( ) ; AU . addRequired < DominatorTreeWrapperPass > ( ) ; AU . addRequired < TargetPassConfig > ( ) ; AU . addPreserved < LoopInfoWrapperPass > ( ) ; AU . setPreservesCFG


<s> int offset = info . total_size ; int stack_offset = info . total_size ; if ( ! info . save_fp && ! info . save_lr && ! reg_mask ) return ; if ( CONST_OK_FOR_LETTER_P ( offset , 'O' ) ) base_reg = stack_pointer_rtx ; else { base_reg = gen_rtx_REG ( SImode , GPR_R9 ) ; offset = <NUM_LIT> ; } if ( info . save_fp ) { offset -= UNITS_PER_WORD ; stack_offset -= UNITS_PER_WORD ; mt_emit_save_restore ( direction , gen_rtx_REG ( SImode , GPR_FP ) , gen_rtx_MEM ( SImode , gen_rtx_PLUS ( SImode , base_reg

, GEN_INT ( offset ) ) ) , stack_offset ) ;


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT>


<s> LoweredMI = MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) ; break ; default : <ISA_LIT>MCInstLower Lower ( MF -> getContext ( ) , * this ) ; Lower . lower ( & * I , LoweredMI ) ; break ; } EmitToStreamer ( * OutStreamer , LoweredMI ) ; } while ( ( ++ I != E ) &&


<s> getStreamer ( ) . setAttributeItem (


<s> if ( ( ( FlagI . getOpcode ( ) == <STR_LIT> && OI . getOpcode ( ) == <STR_LIT> ) || ( FlagI . getOpcode ( ) == <STR_LIT> && OI . getOpcode ( ) == <STR_LIT> ) || ( FlagI . getOpcode ( ) == <STR_LIT> && OI . getOpcode ( ) == <STR_LIT> ) || ( FlagI . getOpcode ( ) == <STR_LIT> && OI . getOpcode ( ) == <STR_LIT> ) ) && ( ( OI . getOperand ( <NUM_LIT> ) . getReg ( ) == SrcReg && OI . getOperand ( <NUM_LIT> )

. getReg ( ) == SrcReg2 ) || ( OI . getOperand ( <NUM_LIT> ) . getReg ( ) == SrcReg2 && OI . getOperand ( <NUM_LIT> ) . getReg ( ) == SrcReg ) ) ) return true ;


<s> if ( auto * RC = RegClassOrBank . dyn_cast < const TargetRegisterClass * > ( ) ) return & RBI . getRegBankFromRegClass ( * RC , LLT ( ) ) ; return


<s> assert ( Kind == Register && <STR_LIT>


<s> addPass ( create<ISA_LIT>LowOverheadLoopsPass ( ) ) ; if ( TM -> getTargetTriple ( ) . isOSWindows

( ) ) addPass ( createCFGuardLongjmpPass ( ) ) ;


<s> return ( __m128d ) __builtin_ia32_maxsd ( ( __v2df ) __A , ( __v2df )


<s> const auto Flags = Op . getNode ( ) -> getFlags ( ) ; if ( Flags . hasNoSignedZeros ( ) ) return


<s> Register ScratchWaveOffsetReg ; if ( TRI -> isSubRegisterEq ( ScratchRsrcReg , PreloadedScratchWaveOffsetReg ) ) { ArrayRef < MCPhysReg > AllSGPRs = TRI -> getAllSGPR32 ( MF ) ; unsigned NumPreloaded = MFI -> getNumPreloadedSGPRs ( ) ; AllSGPRs = AllSGPRs . slice ( std :: min ( static_cast < unsigned > ( AllSGPRs . size ( ) ) , NumPreloaded ) ) ; Register GITPtrLoReg = MFI -> getGITPtrLoReg ( MF ) ; for ( MCPhysReg Reg : AllSGPRs ) { if ( ! MRI . isPhysRegUsed ( Reg ) && MRI . isAllocatable ( Reg ) && ! TRI -> isSubRegisterEq ( ScratchRsrcReg , Reg ) && GITPtrLoReg != Reg ) { ScratchWaveOffsetReg = Reg ; BuildMI ( MBB , I , DL , TII -> get ( <STR_LIT> ) , ScratchWaveOffsetReg ) . addReg ( PreloadedScratchWaveOffsetReg , RegState :: Kill ) ; break ; } } } else { ScratchWaveOffsetReg = PreloadedScratchWaveOffsetReg ; } assert ( ScratchWaveOffsetReg ) ; if ( requiresStackPointerReference ( MF ) ) { Register SPReg = MFI -> getStackPtrOffsetReg ( ) ; assert ( SPReg != <STR_LIT> ) ; BuildMI ( MBB , I , DL , TII -> get ( <STR_LIT> ) , SPReg ) . addImm ( FrameInfo . getStackSize ( ) * getScratchScaleFactor ( ST ) ) ; } if ( hasFP ( MF ) ) { Register FPReg = MFI -> getFrameOffsetReg ( ) ; assert ( FPReg != <STR_LIT> ) ; BuildMI ( MBB , I , DL , TII -> get ( <STR_LIT> ) , FPReg ) . addImm ( <NUM_LIT> ) ; } bool NeedsFlatScratchInit = MFI -> hasFlatScratchInit ( ) && ( MRI . isPhysRegUsed ( <STR_LIT> ) || FrameInfo . hasCalls ( ) || ( ! allStackObjectsAreDead ( FrameInfo ) && ST . enableFlatScratch ( ) ) ) ; if ( ( NeedsFlatScratchInit || ScratchRsrcReg ) && ! ST . flatScratchIsArchitected ( ) ) { MRI . addLiveIn ( PreloadedScratchWaveOffsetReg ) ; MBB . addLiveIn ( PreloadedScratchWaveOffsetReg ) ; } if ( NeedsFlatScratchInit ) { emitEntryFunctionFlatScratchInit ( MF , MBB ,


<s> for ( uint64_t i = <NUM_LIT> ; i != NumNops ; ++ i ) OW -> Write32 ( <NUM_LIT> ) ; OW -> WriteZeros ( Count % <NUM_LIT> ) ; return true


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ( <STR_LIT> , <STR_LIT> , <STR_LIT> , & MI . getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ( <STR_LIT> , MI . getOperand ( <NUM_LIT> ) . getImm ( ) , MI . getOperand ( <NUM_LIT> ) . getImm ( ) , & MI . getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ( <STR_LIT> , <STR_LIT> , <STR_LIT> , & MI . getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : return <STR_LIT> ( <STR_LIT> , <STR_LIT> , <STR_LIT> , & MI . getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ( <STR_LIT> , <STR_LIT> , MI . getOperand ( <NUM_LIT> ) . getImm ( ) , & MI . getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ( <STR_LIT> , <STR_LIT> , MI . getOperand ( <NUM_LIT> ) . getImm ( ) , & MI . getOperand


<s> llvm :: reverse ( llvm :: make_range ( MBB . begin ( ) , TestPos ) ) ) { <STR_LIT> Cond = <STR_LIT> ( MI ) ; if ( Cond != <STR_LIT> && ! MI . mayStore ( ) && MI . getOperand ( <NUM_LIT> ) . isReg ( ) && MI . getOperand ( <NUM_LIT> ) . getReg ( ) . isVirtual ( ) ) { assert ( MI . getOperand ( <NUM_LIT> ) . isDef ( ) && <STR_LIT>


<s> if ( isPowerOf2_64 ( MulAmt2 ) && ! ( N -> hasOneUse ( ) && N -> use_begin ( ) -> getOpcode ( ) == <STR_LIT> ) ) std :: swap ( MulAmt1 , MulAmt2 ) ; if ( isPowerOf2_64 ( MulAmt1 ) ) NewMul = DAG . getNode ( <STR_LIT> , DL , VT , N -> getOperand ( <NUM_LIT> ) , DAG . getConstant ( Log2_64 ( MulAmt1 ) , DL , <STR_LIT> ) ) ; else NewMul = DAG . getNode ( <STR_LIT> , DL , VT , N -> getOperand ( <NUM_LIT> ) , DAG . getConstant ( MulAmt1 , DL , VT ) ) ; if ( isPowerOf2_64 ( MulAmt2 ) ) NewMul = DAG . getNode ( <STR_LIT> , DL , VT , NewMul , DAG . getConstant ( Log2_64 ( MulAmt2 ) , DL , <STR_LIT> ) ) ; else NewMul = DAG . getNode ( <STR_LIT> , DL , VT , NewMul , DAG . getConstant ( MulAmt2 , DL , VT ) ) ; if ( SignMulAmt < <NUM_LIT> ) NewMul = DAG . getNode ( <STR_LIT> , DL , VT , DAG . getConstant ( <NUM_LIT> , DL , VT ) , NewMul ) ; } else if ( ! Subtarget . slowLEA ( ) ) NewMul = combineMulSpecial ( C -> getZExtValue ( ) , N , DAG , VT , DL ) ; if ( ! NewMul ) { assert ( C -> getZExtValue ( ) != <NUM_LIT> && C -> getZExtValue ( ) != ( VT == <STR_LIT> ? UINT64_MAX : UINT32_MAX ) && <STR_LIT> <STR_LIT> ) ; if ( isPowerOf2_64 ( AbsMulAmt - <NUM_LIT> ) ) { NewMul = DAG . getNode ( <STR_LIT> , DL , VT , N -> getOperand ( <NUM_LIT> ) , DAG . getNode ( <STR_LIT> , DL , VT , N -> getOperand ( <NUM_LIT> ) , DAG . getConstant ( Log2_64 ( AbsMulAmt - <NUM_LIT> ) , DL , <STR_LIT> ) ) ) ; if ( SignMulAmt < <NUM_LIT> ) NewMul = DAG . getNode ( <STR_LIT> , DL , VT , DAG . getConstant ( <NUM_LIT> , DL , VT ) , NewMul ) ; } else if ( isPowerOf2_64 ( AbsMulAmt + <NUM_LIT> ) ) { NewMul = DAG . getNode ( <STR_LIT> , DL , VT , N -> getOperand ( <NUM_LIT> ) , DAG . getConstant ( Log2_64 ( AbsMulAmt + <NUM_LIT> ) , DL , <STR_LIT> ) ) ; if ( SignMulAmt < <NUM_LIT> ) NewMul = DAG . getNode ( <STR_LIT> , DL , VT , N -> getOperand ( <NUM_LIT> )


<s> void <ISA_LIT>ExpandPseudo :: ExpandCmp ( MachineInstr & MI , MachineBasicBlock & MBB ) { bool Is24Bit = MI . getOpcode ( ) == <STR_LIT> ; assert ( ( Is24Bit || MI . getOpcode ( ) == <STR_LIT> ) && <STR_LIT> ) ; DebugLoc DL = MI . getDebugLoc ( ) ; dbgs ( ) << <STR_LIT> ; MI . dump ( )


<s> MachineOperand & UO = PN -> getOperand ( <NUM_LIT> ) ; unsigned UseR = UO . getReg ( ) , UseSR = UO . getSubReg ( ) ; unsigned DefR = PN -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned NewR = UseR ; if ( UseSR ) { const DebugLoc & DL = PN -> getDebugLoc ( ) ; const TargetRegisterClass * RC = MRI -> getRegClass ( DefR ) ; NewR = MRI -> createVirtualRegister ( RC ) ; NonPHI = BuildMI ( * B , NonPHI , DL , HII -> get ( TargetOpcode :: COPY ) , NewR ) . addReg ( UseR , <NUM_LIT> , UseSR ) ; } MRI -> replaceRegWith ( DefR ,


<s> if ( ! PT ) { continue ; } Type * DereferencedType = PT -> getElementType ( ) ; if ( ! dyn_cast < StructType > ( DereferencedType ) ) { continue ; } if ( ! containsPointerType ( DereferencedType ) ) { continue ; } dumpAll =


<s> if ( isa < PHINode > ( I -> getArgOperand ( <NUM_LIT> ) ) ) return processPhiNode ( I ) ; SmallVector < Instruction * , <NUM_LIT> > CandidatesForRemoval ; Value * Cursor = I -> getOperand ( <NUM_LIT> ) , * EarliestReplacement = nullptr ; const auto * IVTy = cast < VectorType > ( I -> getType ( ) ) ; while ( Cursor ) { const auto * CursorVTy = cast < VectorType > (


<s> Type * BCTy = BitCast -> getType ( ) ; Type * BCSrcTy = BitCast -> getOperand ( <NUM_LIT> ) -> getType ( ) ; if ( BCTy -> getVectorNumElements ( ) == BCSrcTy -> getVectorNumElements


<s> static bool checkBoolTestAndOrSetCCCombine ( SDValue Cond , <STR_LIT> & CC0 , <STR_LIT> & CC1 , SDValue & Flags , bool & isAnd ) { if ( Cond -> getOpcode ( ) == <STR_LIT> ) { ConstantSDNode * CondOp1C = dyn_cast < ConstantSDNode > ( Cond -> getOperand ( <NUM_LIT> ) ) ; if ( ! CondOp1C || ! CondOp1C -> isNullValue ( ) ) return false ; Cond = Cond -> getOperand


<s> return ( SU -> getInstr ( ) -> getOpcode ( ) ==


<s> SDLoc DL ( Op ) ; if ( ! LD -> isVolatile ( ) ) { const GlobalValue * GV ; int64_t Offset = <NUM_LIT> ; if ( DAG . isBaseWithConstantOffset ( BasePtr ) && isWordAligned ( BasePtr -> getOperand ( <NUM_LIT> ) , DAG ) ) { SDValue NewBasePtr = BasePtr -> getOperand ( <NUM_LIT> ) ; Offset = cast < ConstantSDNode > ( BasePtr -> getOperand ( <NUM_LIT> ) ) -> getSExtValue ( ) ; return lowerLoadWordFromAlignedBasePlusOffset ( DL , Chain , NewBasePtr , Offset , DAG ) ; } if ( TLI . isGAPlusOffset ( BasePtr . getNode ( ) , GV , Offset ) && MinAlign ( GV -> getAlignment ( ) , <NUM_LIT> ) == <NUM_LIT> ) { SDValue NewBasePtr = DAG . getGlobalAddress ( GV , DL , BasePtr -> getValueType ( <NUM_LIT> ) ) ; return lowerLoadWordFromAlignedBasePlusOffset ( DL , Chain , NewBasePtr , Offset , DAG ) ; } } if ( LD -> getAlignment ( ) == <NUM_LIT> ) { SDValue Low = DAG . getExtLoad ( <STR_LIT> , DL , <STR_LIT> , Chain , BasePtr , LD -> getPointerInfo ( ) , <STR_LIT> , LD -> isVolatile ( ) , LD -> isNonTemporal ( ) , LD -> isInvariant ( ) , <NUM_LIT> ) ; SDValue HighAddr = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , BasePtr , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; SDValue High = DAG . getExtLoad ( <STR_LIT> , DL , <STR_LIT> , Chain , HighAddr , LD -> getPointerInfo ( ) . getWithOffset ( <NUM_LIT> ) , <STR_LIT> , LD -> isVolatile ( ) , LD -> isNonTemporal ( ) , LD -> isInvariant ( ) , <NUM_LIT> ) ; SDValue HighShifted = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , High , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; SDValue Result = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Low , HighShifted ) ; Chain = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Low . getValue ( <NUM_LIT> ) , High . getValue ( <NUM_LIT> ) ) ; SDValue Ops [ ] = {


<s> if ( skipFunction ( MF . getFunction ( ) ) ) return false ; initialize ( MF ) ; return removeLD (


<s> void restore ( ) { if ( SavedExecReg ) { TRI . buildVGPRSpillLoadStore ( * this , TmpVGPRIndex , <NUM_LIT> , true , false ) ; auto I = BuildMI ( * MBB , MI , DL , TII . get ( MovOpc ) , ExecReg ) . addReg ( SavedExecReg , RegState :: Kill ) ; if ( ! TmpVGPRLive ) { I . addReg ( TmpVGPR , RegState :: ImplicitKill ) ; } } else { TRI . buildVGPRSpillLoadStore ( * this , TmpVGPRIndex , <NUM_LIT> , true , false ) ; auto I = BuildMI ( * MBB , MI , DL , TII . get ( NotOpc ) , ExecReg ) . addReg ( ExecReg ) ; if ( ! TmpVGPRLive ) { I . addReg ( TmpVGPR , RegState :: ImplicitKill ) ; } if ( TmpVGPRLive ) TRI . buildVGPRSpillLoadStore ( * this ,


<s> if ( mode == SImode ) fn = gen_load_locked_si ; else if ( mode == DImode


<s> MachineMemOperand * MMO = GetMemOperand ( MBB , FI , MachineMemOperand :: MOStore ) ; unsigned Opc = <NUM_LIT> ; Opc = <STR_LIT> ; assert ( Opc && <STR_LIT> ) ; BuildMI ( MBB , I , DL , get ( Opc ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addFrameIndex

( FI ) . addImm ( Offset ) . addMemOperand ( MMO ) ;


<s> const <ISA_LIT>Operand & Op = static_cast < const <ISA_LIT>Operand & > ( * Operands [ ListNo ] ) ; bool HasWritebackToken = Op . isToken ( ) && Op . getToken ( ) == <STR_LIT> ; bool ListContainsSP = listContainsReg ( Inst , ListNo , <STR_LIT> ) ; bool ListContainsLR = listContainsReg ( Inst , ListNo , <STR_LIT> ) ; bool ListContainsPC = listContainsReg ( Inst , ListNo , <STR_LIT> ) ; if ( ! IsARPop && ListContainsSP ) return Error ( Operands [ ListNo + HasWritebackToken ] -> getStartLoc ( ) , <STR_LIT> ) ; else if ( ListContainsPC && ListContainsLR ) return Error ( Operands [ ListNo + HasWritebackToken ] -> getStartLoc ( ) , <STR_LIT> ) ; else if ( inITBlock ( ) && ! lastInITBlock ( ) && ListContainsPC ) return Error ( Operands [ ListNo + HasWritebackToken ] -> getStartLoc ( ) , <STR_LIT> <STR_LIT> ) ; return false


<s> Register CmpOperand = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( GR . isScalarOfType ( CmpOperand , <STR_LIT> ) ) CmpOpc = getPtrCmpOpcode ( Pred ) ; else if ( GR . isScalarOrVectorOfType ( CmpOperand , <STR_LIT> ) ) CmpOpc = getBoolCmpOpcode


<s> if ( Bits & <NUM_LIT> ) { BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , ScratchReg ) . addReg ( ScratchReg ) . addImm ( <NUM_LIT> & Bits ) . addImm ( <NUM_LIT> ) . setMIFlags ( MIFlags ) ; } Bits >>= <NUM_LIT> ; if ( Bits & <NUM_LIT> ) { BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , ScratchReg ) . addReg ( ScratchReg ) . addImm ( <NUM_LIT> & Bits ) . addImm ( <NUM_LIT> ) . setMIFlags ( MIFlags ) ; } Bits >>= <NUM_LIT> ; if ( Bits & <NUM_LIT> ) { BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , ScratchReg ) . addReg ( ScratchReg ) . addImm ( <NUM_LIT> & Bits ) . addImm ( <NUM_LIT> ) . setMIFlags ( MIFlags ) ; } unsigned AddOp = NumBytes > <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; BuildMI ( MBB , MBBI , dl , TII . get ( AddOp ) , DstReg ) . addReg ( SrcReg , RegState :: Kill ) . addReg ( ScratchReg , RegState :: Kill ) . addImm ( <NUM_LIT> ) . setMIFlag ( MIFlags ) ; return ; } unsigned LowOp , HighOp ; if ( NumBytes >= <NUM_LIT> ) { LowOp = <STR_LIT> ; HighOp = <STR_LIT> ; } else { LowOp = <STR_LIT> ; HighOp = <STR_LIT> ; NumBytes = abs ( NumBytes ) ; } if ( ( NumBytes & <NUM_LIT> ) || NumBytes == <NUM_LIT> ) { BuildMI ( MBB , MBBI , dl , TII . get ( LowOp ) , DstReg ) . addReg ( SrcReg , RegState :: Kill ) . addImm ( NumBytes & <NUM_LIT> ) . setMIFlag ( MIFlags ) ; SrcReg =


<s> * offset = m_GOTPLT . addr ( ) - addr ( ) + <NUM_LIT> - <NUM_LIT> ; offset = reinterpret_cast < uint32_t * > ( data + <NUM_LIT> ) ; * offset = m_GOTPLT . addr ( ) - addr ( ) + <NUM_LIT> - <NUM_LIT> ; plt0 -> setValue ( data


<s> const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; if ( ! CE )


<s> return makeArrayRef ( <STR_LIT> . begin ( ) , TRI


<s> IntelExprStateMachine SM ( ImmDisp , false , true ) ; if ( ParseIntelExpression ( SM , End ) ) return nullptr ; const MCExpr * Disp = nullptr ; if ( const MCExpr * Sym = SM . getSym ( ) ) { Disp = Sym ; if ( isParsingInlineAsm ( ) ) RewriteIntelBracExpression ( InstInfo -> AsmRewrites , SM . getSymName ( ) , ImmDisp , SM . getImm ( ) , BracLoc , StartInBrac , End ) ; } if ( SM . getImm ( ) || ! Disp ) { const MCExpr * Imm = MCConstantExpr :: create ( SM . getImm ( ) , getContext ( ) ) ; if ( Disp ) Disp = MCBinaryExpr :: createAdd ( Disp , Imm , getContext ( ) ) ; else Disp = Imm ; } if ( Tok . getString ( ) . find ( '.' ) != StringRef :: npos ) { const MCExpr * NewDisp ; if ( ParseIntelDotOperator ( Disp , NewDisp ) ) return nullptr ; End = Tok . getEndLoc ( ) ; Parser . Lex ( ) ; Disp = NewDisp ; } int BaseReg = SM . getBaseReg ( ) ; int IndexReg = SM . getIndexReg ( ) ; int Scale = SM . getScale ( ) ; if ( ! isParsingInlineAsm ( ) ) { if ( ! BaseReg && ! IndexReg ) { if ( ! SegReg ) return <STR_LIT> ( getPointerWidth ( ) , Disp , Start , End , Size ) ; return <STR_LIT> ( getPointerWidth ( ) , SegReg , Disp , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , Start , End , Size ) ; } StringRef ErrMsg ; if ( CheckBaseRegAndIndexReg ( BaseReg , IndexReg , ErrMsg ) ) { Error ( StartInBrac , ErrMsg ) ; return nullptr ; } return <STR_LIT> ( getPointerWidth ( ) , SegReg , Disp , BaseReg , IndexReg , Scale , Start , End ,


<s> vtst_p16 ( poly16x4_t a , poly16x4_t b ) { uint16x4_t result ; __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT> ( b ) : ) ; return result


<s> virtual void EmitCFIEndProcImpl ( MCDwarfFrameInfo & Frame ) { Frame . End = ( MCSymbol


<s> if ( reg == <NUM_LIT> ) { gcc_assert ( can_create_pseudo_p ( ) ) ; reg = gen_reg_rtx ( Pmode ) ; } rtx_insn * insn ; if ( ( LABEL_REF_P ( orig ) || ( SYMBOL_REF_P ( orig ) && SYMBOL_REF_LOCAL_P ( orig ) && ( SYMBOL_REF_DECL ( orig ) ? ! DECL_WEAK ( SYMBOL_REF_DECL ( orig ) ) : <NUM_LIT> ) && ( ! SYMBOL_REF_FUNCTION_P ( orig ) || arm_fdpic_local_funcdesc_p ( orig ) ) ) ) && NEED_GOT_RELOC && arm_pic_data_is_text_relative ) insn = arm_pic_static_addr ( orig , reg ) ; else { require_pic_register ( pic_reg , compute_now ) ; if ( pic_reg == NULL_RTX ) pic_reg = cfun -> machine -> pic_reg ; insn = calculate_pic_address_constant ( reg , pic_reg , orig ) ; } set_unique_reg_note ( insn , REG_EQUAL , orig ) ; return reg ; } else if ( GET_CODE ( orig ) == CONST ) { rtx base , offset ; if ( GET_CODE ( XEXP ( orig , <NUM_LIT> ) ) == PLUS && XEXP ( XEXP ( orig , <NUM_LIT> ) , <NUM_LIT> ) == cfun -> machine -> pic_reg ) return orig ; if ( GET_CODE ( XEXP ( orig , <NUM_LIT> ) ) == UNSPEC && XINT ( XEXP ( orig , <NUM_LIT> ) , <NUM_LIT> ) == UNSPEC_TLS ) return orig ; if ( GET_CODE ( XEXP ( orig , <NUM_LIT> ) ) == PLUS && GET_CODE ( XEXP ( XEXP ( orig , <NUM_LIT> ) , <NUM_LIT> ) ) == UNSPEC && XINT ( XEXP ( XEXP ( orig , <NUM_LIT> ) , <NUM_LIT> ) , <NUM_LIT> ) == UNSPEC_TLS ) { gcc_assert ( CONST_INT_P ( XEXP ( XEXP ( orig ,


<s> if ( Section . find ( <STR_LIT> ) != StringRef :: npos ) return getContext ( ) . getELFSection ( GV -> getSection ( ) , ELF :: SHT_PROGBITS , ELF :: SHF_ALLOC | ELF :: SHF_EXECINSTR ) ; if ( Section . find ( <STR_LIT> ) != StringRef :: npos ) return getContext ( ) . getELFSection ( GV -> getSection ( ) , ELF :: SHT_PROGBITS , ELF :: SHF_WRITE | ELF :: SHF_ALLOC ) ; } if ( isGlobalInSmallSection ( GV , TM ) ) return selectSmallSectionForGlobal


<s> label2 = gen_rtx_LABEL_REF ( VOIDmode , gen_label_rtx ( ) ) ; emit_load_locked ( mode , retval , mem ) ; x = retval ; if ( mask ) x = expand_simple_binop ( SImode , AND , retval , mask , NULL_RTX , <NUM_LIT> , OPTAB_LIB_WIDEN ) ; cond = gen_reg_rtx ( CCmode ) ; if ( mode != TImode ) x = gen_rtx_COMPARE ( CCmode , x , oldval ) ; else { rtx xor1_result = gen_reg_rtx ( DImode ) ; rtx xor2_result = gen_reg_rtx ( DImode ) ; rtx or_result = gen_reg_rtx ( DImode ) ; rtx new_word0 = simplify_gen_subreg ( DImode , x , TImode , <NUM_LIT> ) ; rtx new_word1 = simplify_gen_subreg ( DImode , x , TImode , <NUM_LIT> ) ; rtx old_word0 = simplify_gen_subreg ( DImode , oldval , TImode , <NUM_LIT> ) ; rtx old_word1 = simplify_gen_subreg ( DImode , oldval , TImode , <NUM_LIT> ) ; emit_insn ( gen_xordi3 ( xor1_result , new_word0 , old_word0 ) ) ; emit_insn ( gen_xordi3 ( xor2_result , new_word1 , old_word1 ) ) ; emit_insn ( gen_iordi3 ( or_result , xor1_result , xor2_result ) ) ; x = gen_rtx_COMPARE ( CCmode , or_result , const0_rtx ) ; } emit_insn ( gen_rtx_SET ( cond , x ) ) ; x = gen_rtx_NE ( VOIDmode , cond , const0_rtx ) ; emit_unlikely_jump ( x , label2 ) ; x = newval ; if ( mask ) x = rs6000_mask_atomic_subword ( retval , newval , mask ) ; emit_store_conditional ( orig_mode , cond , mem


<s> unsigned getExceptionPointerRegister ( const Constant