<s> bool loongarch_signed_immediate_p ( unsigned HOST_WIDE_INT x , int bits , int shift = <NUM_LIT> ) { x += <NUM_LIT> << ( bits + shift


<s> MachineBasicBlock * NewBB = MF -> CreateMachineBasicBlock ( OrigBB -> getBasicBlock ( ) ) ; MachineFunction :: iterator MBBI = OrigBB ; ++ MBBI ; MF -> insert ( MBBI , NewBB ) ; NewBB -> splice ( NewBB -> end ( ) , OrigBB , MI , OrigBB -> end ( ) ) ; unsigned Opc = isThumb ? ( isThumb2 ? <STR_LIT> : <STR_LIT> ) : <STR_LIT> ; if ( ! isThumb ) BuildMI ( OrigBB , DebugLoc ( ) , TII -> get ( Opc ) ) . addMBB ( NewBB ) ; else BuildMI ( OrigBB , DebugLoc ( ) , TII -> get ( Opc ) ) . addMBB ( NewBB ) . addImm ( <STR_LIT> ) . addReg ( <NUM_LIT> ) ; ++ NumSplit ; NewBB -> transferSuccessors ( OrigBB ) ; OrigBB -> addSuccessor ( NewBB ) ; MF -> RenumberBlocks ( NewBB ) ; BBInfo . insert ( BBInfo . begin ( ) + NewBB -> getNumber ( ) , BasicBlockInfo ( ) ) ; water_iterator IP = std :: lower_bound ( WaterList . begin ( ) , WaterList . end ( ) , OrigBB , CompareMBBNumbers ) ; MachineBasicBlock * WaterBB = *


<s> bool <ISA_LIT>SEDAGToDAGISel :: selectIntAddr11MM ( SDValue Addr , SDValue & Base , SDValue & Offset


<s> unsigned <ISA_LIT>RegisterInfo :: getFrameRegister ( const


<s> void <ISA_LIT>InstrInfo :: expandLOCPseudo ( MachineInstr & MI , unsigned LowOpcode , unsigned HighOpcode ) const { Register Reg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Opcode = isHighReg ( Reg ) ? HighOpcode : LowOpcode ; MI . setDesc ( get (


<s> return ( AMSubMode ) ( ( AM5Opc >> <NUM_LIT> )


<s> <ISA_LIT>TargetLowering * getTargetLowering ( ) const override { return const_cast < <ISA_LIT>TargetLowering * > ( & TLInfo


<s> else return _URC_END_OF_STACK ; new_cfa = ( _Unwind_Ptr ) sc ; fs -> cfa_how = CFA_REG_OFFSET ; fs -> cfa_reg = STACK_POINTER_REGNUM ; fs -> cfa_offset = new_cfa - ( _Unwind_Ptr ) context -> cfa ; new_cfa -= <NUM_LIT> ; for ( i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) { fs -> regs . reg [ i ] . how = REG_SAVED_OFFSET ; fs -> regs . reg [ i ] . loc . offset = ( _Unwind_Ptr ) & ( sc -> sc_regs [ i ] ) - new_cfa ; } fs -> regs . reg [ SIGNAL_UNWIND_RETURN_COLUMN ] . how = REG_SAVED_OFFSET ; fs -> regs . reg [ SIGNAL_UNWIND_RETURN_COLUMN ] . loc . offset = ( _Unwind_Ptr ) & ( sc


<s> static const MCDisassembler * create<ISA_LIT>_32Disassembler ( const Target & T ) { return new <ISA_LIT>Disassembler ::


<s> } if ( rs6000_hard_regno_nregs [ m ] [ r ] > <NUM_LIT> ) len += fprintf ( stderr , <STR_LIT> , comma , GET_MODE_NAME ( m ) , rs6000_hard_regno_nregs [ m ] [ r ] ) ; else len += fprintf ( stderr , <STR_LIT> , comma , GET_MODE_NAME ( m ) ) ; comma = <STR_LIT> ; } if ( call_used_regs [ r ] ) { if ( len > <NUM_LIT> ) { fprintf ( stderr , <STR_LIT> ) ; len = <NUM_LIT> ; comma = <STR_LIT> ; } len += fprintf ( stderr , <STR_LIT> , comma , <STR_LIT> ) ; comma = <STR_LIT> ; } if ( fixed_regs [ r ] ) { if ( len > <NUM_LIT> )


<s> if ( func && POINTER_TYPE_P ( TREE_TYPE ( TREE_TYPE ( func ) ) ) ) return gen_rtx_PARALLEL ( mode , gen_rtvec ( <NUM_LIT> , gen_rtx_EXPR_LIST ( VOIDmode , gen_rtx_REG ( mode , A0_REG ) , const0_rtx ) , gen_rtx_EXPR_LIST ( VOIDmode , gen_rtx_REG ( mode , D0_REG )


<s> void Thumb1RegisterInfo :: emitLoadConstPool ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator & MBBI , DebugLoc dl , unsigned DestReg , unsigned SubIdx , int Val , <STR_LIT> Pred , unsigned PredReg , unsigned MIFlags ) const { MachineFunction & MF = * MBB . getParent ( ) ; const TargetInstrInfo & TII = * MF . getTarget ( ) . getInstrInfo ( ) ; MachineConstantPool * ConstantPool = MF . getConstantPool ( ) ; const Constant * C = ConstantInt :: get ( Type :: getInt32Ty ( MBB . getParent ( ) -> getFunction ( ) -> getContext ( ) ) , Val ) ; unsigned Idx = ConstantPool -> getConstantPoolIndex ( C , <NUM_LIT> ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) ) . addReg ( DestReg , getDefRegState ( true )

, SubIdx ) . addConstantPoolIndex ( Idx ) . addImm ( Pred ) . addReg ( PredReg ) . setMIFlags ( MIFlags ) ;


<s> static MCCodeGenInfo * create<ISA_LIT>MCCodeGenInfo ( StringRef TT , Reloc :: Model RM , CodeModel :: Model CM ) { MCCodeGenInfo * X = new MCCodeGenInfo ( ) ; X -> InitMCCodeGenInfo ( RM , CM ) ; return


<s> MI . clear ( ) ; result = decodeThumb2Instruction16 ( MI , insn16 , Address , this , STI ) ; if ( result != MCDisassembler :: Fail ) { Size = <NUM_LIT> ; if ( MI . getOpcode ( ) == <STR_LIT> && ! ITBlock . empty ( ) ) result = MCDisassembler :: SoftFail ; Check ( result , AddThumbPredicate ( MI ) ) ; if ( MI . getOpcode ( ) == <STR_LIT> ) { unsigned firstcond = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned Mask = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned CondBit0 = Mask >> <NUM_LIT> & <NUM_LIT> ; unsigned NumTZ = CountTrailingZeros_32 ( Mask ) ; assert ( NumTZ <= <NUM_LIT> && <STR_LIT> ) ; for ( unsigned Pos = <NUM_LIT> , e = NumTZ ; Pos > e ; -- Pos ) { bool T = ( ( Mask >> Pos ) & <NUM_LIT> ) == CondBit0 ; if ( T ) ITBlock . insert ( ITBlock . begin ( ) , firstcond ) ; else ITBlock . insert ( ITBlock . begin ( ) , firstcond ^ <NUM_LIT> ) ; } ITBlock . push_back ( firstcond ) ; } return result ; } if ( Region . readBytes ( Address , <NUM_LIT> , ( uint8_t * ) bytes , NULL ) == - <NUM_LIT> ) { Size = <NUM_LIT> ; return MCDisassembler :: Fail ; } uint32_t insn32 = ( bytes [ <NUM_LIT> ] << <NUM_LIT> ) | ( bytes [ <NUM_LIT> ] << <NUM_LIT> ) | ( bytes [ <NUM_LIT> ] << <NUM_LIT> ) | ( bytes [ <NUM_LIT> ] << <NUM_LIT> ) ; MI . clear ( ) ; result = decodeThumbInstruction32 ( MI , insn32 , Address , this , STI ) ; if ( result != MCDisassembler :: Fail ) { Size = <NUM_LIT> ; bool InITBlock = ITBlock . size ( ) ; Check ( result , AddThumbPredicate ( MI ) ) ; AddThumb1SBit ( MI , InITBlock ) ; return result


<s> return Opc == <STR_LIT> || Opc == <STR_LIT> || Opc ==


<s> SelectInlineAsmMemoryOperand ( const SDValue & Op , char ConstraintCode , std :: vector < SDValue > & OutOps ) { SDValue Op0 , Op1 ; switch ( ConstraintCode ) { default : return true ; case 'm' : if ( ! SelectAddr ( Op , Op0 , Op1 ) ) return true ; break ; } OutOps . push_back


<s> static Waitcnt allZero ( ) { return Waitcnt ( <NUM_LIT> , <NUM_LIT> , <NUM_LIT>


<s> else if ( ! TARGET_MIX_SSE_I387 ) { if ( ! ( TARGET_SSE && TARGET_SSE_MATH ) ) return FLT_EVAL_METHOD_PROMOTE_TO_LONG_DOUBLE ; else if ( TARGET_SSE2

) return FLT_EVAL_METHOD_PROMOTE_TO_FLOAT ;


<s> return ( __m64 ) __builtin_ia32_punpckhwd ( ( __v4hi ) __m1 , (


<s> if ( GET_CODE ( x ) == VALUE && CSELIB_VAL_PTR ( x ) ) return ( pic_offset_table_rtx && rtx_equal_for_cselib_p ( x , pic_offset_table_rtx ) ) ; else if ( GET_CODE ( x ) == UNSPEC && XINT ( x , <NUM_LIT> ) == UNSPEC_SET_GOT ) return true ; else if ( ! REG_P ( x ) ) return false ; else if ( pic_offset_table_rtx ) { if ( REGNO ( x ) == REGNO ( pic_offset_table_rtx ) ) return true ; if ( HARD_REGISTER_P ( x ) && ! HARD_REGISTER_P ( pic_offset_table_rtx ) && ORIGINAL_REGNO ( x ) == REGNO ( pic_offset_table_rtx ) ) return true ; return


<s> assert ( OpVT == <STR_LIT> || ( OpVT == <STR_LIT> ) ) ; EVT floatVT = ( OpVT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; if ( Op . getValueType ( ) == <STR_LIT> && ( ! hasHardQuad || ! TLI . isTypeLegal ( OpVT ) ) ) { const char * libName = TLI . getLibcallName ( OpVT == <STR_LIT> ? RTLIB :: SINTTOFP_I32_F128 : RTLIB :: SINTTOFP_I64_F128 ) ; return TLI . LowerF128Op ( Op , DAG , libName , <NUM_LIT> ) ; } if ( ! TLI . isTypeLegal (


<s> static MCInstrPrinter * createNPEngineMCInstrPrinter ( const Target & T , unsigned SyntaxVariant , const MCASMInfo & MAI , const MCInstrInfo & MII , const MCRegisterInfo & MRI , const MCSubtargetInfo & STI ) { return new NPEngineInstrPrinter ( MAI , MII , MRI


<s> case TargetStackID :: NoAlloc : case TargetStackID :: SGPRSpill : return true ; case TargetStackID ::


<s> } if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) { BuildMI ( MBB , MBBI , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( <STR_LIT> ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; return ; } unsigned Opc ; if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg ) && <STR_LIT> . contains ( SrcReg ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg ) && <STR_LIT> . contains ( SrcReg ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg ) && <STR_LIT> . contains ( SrcReg ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg ) && <STR_LIT> . contains ( SrcReg ) ) Opc = <STR_LIT> ; else llvm_unreachable ( <STR_LIT> ) ; BuildMI ( MBB , MBBI , DL , get ( Opc ) , DestReg ) . addReg ( SrcReg


<s> if ( ! allowsMisalignedMemoryAccesses ( VT , AS , Align , & IsFast ) ) return expandUnalignedStore ( SN , DAG ) ; if ( ! IsFast ) return SDValue ( ) ; } if ( ! shouldCombineMemoryType ( VT ) ) return SDValue ( ) ; EVT NewVT = getEquivalentMemType ( * DAG . getContext ( ) , VT ) ; SDValue Val = SN -> getValue ( ) ; bool OtherUses = ! Val . hasOneUse ( ) ; SDValue CastVal = DAG . getNode ( <STR_LIT> , SL , NewVT , Val ) ; if ( OtherUses ) { SDValue CastBack = DAG . getNode ( <STR_LIT> , SL , VT , CastVal ) ; DAG . ReplaceAllUsesOfValueWith ( Val , CastBack


<s> __o = __builtin_aarch64_set_qregoiv16qi ( __o , ( int8x16_t ) tab . val [ <NUM_LIT> ] , <NUM_LIT> ) ; __o = __builtin_aarch64_set_qregoiv16qi ( __o , ( int8x16_t ) tab


<s> static Reloc :: Model getEffectiveRelocModel ( CodeModel :: Model CM , Optional < Reloc :: Model > RM ) { if ( ! RM . hasValue ( ) || CM == CodeModel :: JITDefault ) return Reloc :: Static ; return *


<s> MCOperand <ISA_LIT>Disassembler :: decodeOperand_VReg_256 ( unsigned Val )


<s> if ( StVal . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; if ( ! StVal . hasOneUse ( ) ) return SDValue ( ) ; if ( DAG . isBaseWithConstantOffset ( St . getBasePtr ( ) ) ) { int64_t Offset = St . getBasePtr ( ) -> getConstantOperandVal ( <NUM_LIT> ) ; if ( Offset < - <NUM_LIT> || Offset > <NUM_LIT> ) return SDValue ( ) ; } for ( int I = <NUM_LIT> ; I


<s> else { section * s ; char buf [ <NUM_LIT> ] ; snprintf ( buf , sizeof ( buf ) , <STR_LIT> , priority ) ; s = get_section ( buf , SECTION_WRITE , NULL ) ; switch_to_section ( s )


<s> static int mips_issue_rate ( void ) { switch ( mips_tune ) { case PROCESSOR_R4130 : case PROCESSOR_R5400 : case PROCESSOR_R5500 : case PROCESSOR_R7000 : case PROCESSOR_R9000 : return


<s> unsigned <ISA_LIT>ELFObjectWriter :: GetRelocType ( const MCValue & Target , const MCFixup & Fixup , bool IsPCRel , bool IsRelocWithSymbol , int64_t Addend ) const { unsigned Kind = ( unsigned ) Fixup . getKind ( ) ; llvm_unreachable (


<s> SDValue AMDGPUTargetLowering :: LowerEXTRACT_SUBVECTOR ( SDValue Op , SelectionDAG & DAG ) const { SmallVector < SDValue , <NUM_LIT> > Args ; EVT VT = Op . getValueType ( ) ; unsigned Start = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; ExtractVectorElements ( Op . getOperand ( <NUM_LIT> ) , DAG ,

Args , Start , VT . getVectorNumElements ( ) ) ;


<s> } MVT XLenVT = Subtarget . getXLenVT ( ) ; SDValue Zero = DAG . getConstant ( <NUM_LIT> , DL , XLenVT ) ; bool IsLegalInsert = Subtarget . is64Bit ( ) || Val . getValueType ( ) != <STR_LIT> ; if ( ! IsLegalInsert && isa < ConstantSDNode > ( Val ) ) { const auto * CVal = cast < ConstantSDNode > ( Val ) ; if ( isInt < <NUM_LIT> > ( CVal -> getSExtValue ( ) ) ) { IsLegalInsert = true ; Val = DAG . getConstant ( CVal -> getSExtValue ( ) , DL , <STR_LIT> ) ; } } SDValue Mask , VL ; std :: tie ( Mask , VL ) = getDefaultVLOps ( VecVT , ContainerVT , DL , DAG , Subtarget ) ; SDValue ValInVec ; if ( IsLegalInsert ) { unsigned Opc = VecVT . isFloatingPoint ( ) ? <STR_LIT> : <STR_LIT> ; if ( isNullConstant ( Idx ) ) { Vec = DAG . getNode ( Opc , DL , ContainerVT , Vec , Val , VL ) ; if ( ! VecVT . isFixedLengthVector ( ) ) return Vec ; return convertFromScalableVector ( VecVT , Vec , DAG , Subtarget ) ; } ValInVec = DAG . getNode ( Opc , DL , ContainerVT , DAG . getUNDEF ( ContainerVT ) , Val , VL ) ; } else { SDValue One = DAG . getConstant ( <NUM_LIT> , DL , XLenVT ) ; SDValue ValLo = DAG . getNode ( <STR_LIT> , DL , <STR_LIT>


<s> if ( Subtarget . getTargetMachine ( ) . getOptLevel ( ) != CodeGenOpt :: Aggressive ) return false ; return TargetInstrInfo :: getMachineCombinerPatterns ( Root


<s> static bool pdp11_can_change_mode_class ( machine_mode from , machine_mode to , reg_class_t rclass ) { if ( FLOAT_MODE_P ( from ) != FLOAT_MODE_P ( to ) ) return false ; return ! reg_classes_intersect_p ( FPU_REGS , rclass


<s> if ( riscv_int_order_operand_ok_p ( * code , * cmp1 ) ) return true ; if ( CONST_INT_P ( * cmp1 ) ) switch ( * code ) { case LE : plus_one = trunc_int_for_mode ( UINTVAL ( * cmp1 ) + <NUM_LIT> , mode ) ; if ( INTVAL ( * cmp1 ) < plus_one ) { * code = LT ; * cmp1 = force_reg ( mode , GEN_INT ( plus_one ) ) ; return


<s> NumVecs = <NUM_LIT> ; isLoad = false ; isLaneOp = true ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; NumVecs = <NUM_LIT> ; isLoad = false ; isLaneOp = true ; break ; } } else { isLaneOp = true ; switch ( N -> getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : NewOpc = <STR_LIT> ; NumVecs = <NUM_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; NumVecs = <NUM_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; NumVecs = <NUM_LIT> ; break ; } } EVT VecTy ; if ( isLoad ) VecTy = N -> getValueType ( <NUM_LIT> ) ; else VecTy = N -> getOperand ( AddrOpIdx + <NUM_LIT> ) . getValueType ( ) ; unsigned NumBytes = NumVecs * VecTy . getSizeInBits ( ) / <NUM_LIT> ; if ( isLaneOp ) NumBytes /= VecTy . getVectorNumElements ( ) ; SDValue Inc = User -> getOperand ( User -> getOperand ( <NUM_LIT> ) == Addr ? <NUM_LIT> : <NUM_LIT> ) ; if ( ConstantSDNode * CInc = dyn_cast < ConstantSDNode > ( Inc . getNode ( ) ) ) { uint64_t IncVal = CInc -> getZExtValue ( ) ; if ( IncVal != NumBytes ) continue ; } else if ( NumBytes >= <NUM_LIT> * <NUM_LIT> ) { continue ; } EVT Tys [ <NUM_LIT> ] ; unsigned NumResultVecs = ( isLoad ? NumVecs : <NUM_LIT> ) ; unsigned n ; for ( n = <NUM_LIT> ; n < NumResultVecs ; ++ n ) Tys [ n ] = VecTy ; Tys [ n ++ ] = <STR_LIT> ; Tys [ n ] = <STR_LIT> ; SDVTList SDTys = DAG . getVTList ( makeArrayRef ( Tys , NumResultVecs + <NUM_LIT> ) ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . push_back ( N -> getOperand ( <NUM_LIT>


<s> void <ISA_LIT>FrameLowering :: processFunctionBeforeCalleeSavedScan ( MachineFunction & MF , RegScavenger * RS ) const { MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; unsigned FP = STI . isABI_N64 ( ) ? <STR_LIT> : <STR_LIT> ; if ( hasFP ( MF ) ) MRI . setPhysRegUsed ( FP ) ; if ( MF . getFrameInfo ( ) -> hasCalls ( ) ) MRI . setPhysRegUsed ( <STR_LIT> ) ; else { MRI . setPhysRegUnused


<s> uint64_t NumNops = Count / <NUM_LIT> ; for ( uint64_t i = <NUM_LIT> ; i != NumNops ; ++ i ) OW -> Write16 ( nopEncoding ) ; if ( Count & <NUM_LIT> ) OW -> Write8 ( <NUM_LIT> ) ; return true ; } const uint32_t nopEncoding = hasNOP ( ) ? <ISA_LIT>v6T2_NopEncoding : <ISA_LIT>v4_NopEncoding ; uint64_t NumNops = Count / <NUM_LIT> ; for ( uint64_t i = <NUM_LIT> ; i != NumNops ; ++ i ) OW -> Write32 ( nopEncoding ) ; switch ( Count % <NUM_LIT>


<s> switch ( Info -> getDecorationStyle ( ) ) { case None : break ; case StdCall : if ( ! FT -> isVarArg ( ) || ( FT -> getNumParams ( ) == <NUM_LIT> ) || ( FT -> getNumParams ( ) == <NUM_LIT> && F -> hasStructRetAttr ( ) ) ) Name += '@' + utostr_32 ( Info -> getBytesToPopOnReturn ( ) ) ; break ; case FastCall : if ( ! FT -> isVarArg ( ) || ( FT -> getNumParams ( ) == <NUM_LIT> ) || ( FT -> getNumParams ( ) == <NUM_LIT> && F -> hasStructRetAttr ( ) ) ) Name += '@' + utostr_32 ( Info -> getBytesToPopOnReturn ( ) ) ; if ( Name [ <NUM_LIT> ] == '_' ) { Name [ <NUM_LIT> ] = '@' ; } else { Name = '@' + Name ; } break ; default : llvm_unreachable ( <STR_LIT>


<s> DecodeStatus <ISA_LIT>Disassembler :: getInstruction ( MCInst & MI , uint64_t & Size , ArrayRef < uint8_t > Bytes , uint64_t Address , raw_ostream & OS , raw_ostream & CS ) const { Size = <NUM_LIT> ; if ( Bytes . size ( ) < <NUM_LIT> ) { Size = <NUM_LIT> ; return MCDisassembler :: Fail ; } uint32_t Inst = IsLittleEndian ? <STR_LIT> :: read32le ( Bytes . data ( ) ) : <STR_LIT> :: read32be ( Bytes . data ( ) ) ; if ( STI . getFeatureBits ( ) [ <STR_LIT> ] ) { DecodeStatus result = decodeInstruction ( DecoderTableQPX32 , MI , Inst , Address , this , STI ) ; if ( result != MCDisassembler :: Fail ) return result ; } else if ( STI . getFeatureBits ( ) [ <STR_LIT> ] ) { DecodeStatus result = decodeInstruction ( DecoderTableSPE32 , MI , Inst , Address , this , STI ) ; if ( result != MCDisassembler :: Fail ) return result ; } return decodeInstruction ( DecoderTable32 , MI , Inst , Address


<s> return new <ISA_LIT>HazardRecognizer ( II ,


<s> SetOfMachineInstr & BBReachableUses = getSet ( ReachableUses , MBB , CurReg , NbReg ) ; SetOfMachineInstr & BBOutSet = getSet ( Out , MBB , CurReg , NbReg ) ; unsigned Size = BBOutSet . size ( ) ; for ( MachineBasicBlock * PredMBB : MBB . predecessors ( ) ) { SetOfMachineInstr & PredOutSet = getSet ( Out , * PredMBB , CurReg , NbReg ) ; BBInSet . insert ( PredOutSet . begin ( ) , PredOutSet . end ( ) ) ; } for ( const MachineInstr * MI : BBInSet ) { SetOfMachineInstr & OpReachedUses = getUses ( ColorOpToReachedUses , CurReg , * MI ) ; OpReachedUses . insert ( BBReachableUses . begin ( ) , BBReachableUses . end ( ) ) ; } if ( ! Kill [ & MBB ] . test ( CurReg ) ) BBOutSet . insert

( BBInSet . begin ( ) , BBInSet . end ( ) ) ;


<s> case AsmToken :: LParen : case AsmToken :: Plus : case AsmToken :: Minus : case AsmToken :: Integer : case AsmToken :: Identifier : SMLoc E ; if ( getParser ( ) . parseExpression ( EVal , E ) ) return true ; Operands . push_back ( std :: unique_ptr < MCParsedAsmOperand > ( <ISA_LIT>Operand :: CreateImm ( EVal , S , E ) ) ) ; return false


<s> bool isArgPassedInSGPR ( const Argument * A ) { const Function * F = A -> getParent ( ) ; CallingConv :: ID CC = F -> getCallingConv ( ) ; switch ( CC ) { case CallingConv :: <ISA_LIT>_KERNEL : case CallingConv :: SPIR_KERNEL : return true ; case CallingConv :: <ISA_LIT>_VS : case CallingConv :: <ISA_LIT>_LS : case CallingConv :: <ISA_LIT>_HS : case CallingConv :: <ISA_LIT>_ES : case CallingConv :: <ISA_LIT>_GS : case CallingConv ::


<s> unsigned VisitedIndex = <NUM_LIT> ; while ( VisitedIndex < PHIs . size ( ) ) { MachineInstr * VisitedPHI = PHIs [ VisitedIndex ] ; for ( unsigned PHIOp = <NUM_LIT> , NumOps = VisitedPHI -> getNumOperands ( ) ; PHIOp != NumOps ; PHIOp += <NUM_LIT> ) { Register RegOp = VisitedPHI -> getOperand ( PHIOp ) . getReg ( ) ; if ( ! Register :: isVirtualRegister


<s> gimple * gimple_fold_builtin ( unsigned int code , gimple_stmt_iterator * gsi , gcall * stmt ) { registered_function & rfn = * ( * registered_functions ) [ code ] ; return gimple_folder ( rfn . instance , rfn . decl , gsi ,


<s> const <ISA_LIT>RegisterInfo & <ISA_LIT>16InstrInfo ::


<s> SDValue <ISA_LIT>TargetLowering :: LowerGlobalAddress ( SDValue Op , SelectionDAG & DAG ) const { const GlobalValue * GV = cast < GlobalAddressSDNode > (


<s> } x ; int cnt ; vec_uchar16 mask ; x . v = ( vec_uchar16 ) ( count ) ; x . i [ <NUM_LIT> ] = cnt = ( <NUM_LIT> - x . i [ <NUM_LIT> ] ) << <NUM_LIT> ; x . v = vec_splat ( x . v ,


<s> void <ISA_LIT>InstPrinter :: printImplicitlyTypedVectorList ( const MCInst * MI , unsigned OpNum , raw_ostream & O ) { printVectorList ( MI , OpNum , O , <STR_LIT>


<s> MVT ElemTy = ty ( InpV ) . getVectorElementType ( ) ; if ( ElemTy == <STR_LIT> && Subtarget . isHVXVectorType ( ResTy ) ) return extendHvxVectorPred ( InpV , SDLoc ( Op ) , ty ( Op ) , true , DAG ) ; return Op


<s> <ISA_LIT>DisassemblerBase ( const MCSubtargetInfo & STI , const MCRegisterInfo * Info , bool bigEndian ) : MCDisassembler ( STI ) , RegInfo ( Info ) , IsN64 ( STI . getFeatureBits ( ) & <STR_LIT> ) ,


<s> bool <ISA_LIT>AnnotateControlFlow :: doInitialization ( Module & M ) { LLVMContext & Context = M . getContext ( ) ; Void = Type :: getVoidTy ( Context ) ; Boolean = Type :: getInt1Ty ( Context ) ; Int64 = Type :: getInt64Ty ( Context ) ; ReturnStruct = StructType :: get ( Boolean , Int64 , ( Type * ) nullptr ) ; BoolTrue = ConstantInt :: getTrue ( Context ) ; BoolFalse = ConstantInt :: getFalse ( Context ) ; BoolUndef = UndefValue :: get ( Boolean ) ; Int64Zero = ConstantInt :: get ( Int64 , <NUM_LIT>


<s> const char * getPassName ( ) const override { return


<s> const MCOperand & MO = MI . getOperand ( OpIdx ) ; if ( MO . isImm ( ) ) return MO . getImm ( ) ; assert ( MO . isExpr ( ) && <STR_LIT> ) ; MCFixupKind Kind = MI . getOpcode ( ) == <STR_LIT> ? MCFixupKind ( <STR_LIT> ) : MCFixupKind ( <STR_LIT> ) ; Fixups . push_back ( MCFixup :: Create ( <NUM_LIT> , MO . getExpr ( ) , Kind , MI . getLoc (


<s> MachineBasicBlock & SrcMBB = * block -> getMBB ( ) ; if ( predType == RAInfo :: Register ) { RAInfo & RI = S -> isSubheader ( block ) ? RAInfos . at ( S -> findScopeOf ( block ) ) : RAInfos . at ( S ) ; if ( ! S -> isSubheader ( block ) || ! RI . needsScopeSpill ( ) ) { assert ( ! S -> isSubheader ( block ) || ( RI . Scope -> getParent ( ) == S ) ) ; insertDefToRegLoc ( SrcMBB , predLoc , guardLoc , cond , ! first_def || S


<s> } else { WorkStack . push_back ( * AI ) ; GroupInst = AI -> Inst ; } AddrGroups [ GroupInst ] . push_back ( * AI ) ; } for ( DomTreeNode * C : DomN -> children ( ) ) Visit ( C , Visit ) ; while ( ! WorkStack . empty ( ) && WorkStack . back ( ) . Inst -> getParent ( ) == & Block ) WorkStack . pop_back ( ) ; } ; traverseBlock ( HVC . DT . getRootNode ( ) , traverseBlock ) ; assert ( WorkStack . empty ( ) ) ; erase_if ( AddrGroups , [ ] ( auto & G ) { return G . second . size ( ) == <NUM_LIT> ; } ) ; erase_if ( AddrGroups , [ & ] ( auto & G ) { return llvm :: none_of ( G . second , [ & ] ( auto & I ) { return HVC . HST . isTypeForHVX ( I . ValTy ) ; } ) ; } ) ; return ! AddrGroups . empty ( )


<s> int regno = REGNO ( x ) ; if ( ACC_P ( regno ) || ACCG_P


<s> case <STR_LIT> : return LowerShift ( Op , DAG ) ; case <STR_LIT> : return LowerSINT_TO_FP ( Op , DAG ) ; case <STR_LIT> : return LowerUINT_TO_FP ( Op , DAG ) ; case <STR_LIT> : return LowerFP_TO_SINT ( Op , DAG ) ; case <STR_LIT> : return LowerFP_TO_UINT ( Op , DAG ) ; case <STR_LIT> : return LowerFABS ( Op , DAG ) ; case <STR_LIT> : return LowerFNEG ( Op , DAG ) ; case <STR_LIT> : return LowerFCOPYSIGN ( Op , DAG ) ; case <STR_LIT> : return LowerSETCC ( Op , DAG ) ; case <STR_LIT> : return LowerVSETCC ( Op , DAG ) ; case <STR_LIT> : return LowerSELECT ( Op , DAG ) ; case <STR_LIT> : return LowerBRCOND ( Op , DAG ) ; case <STR_LIT> : return LowerJumpTable ( Op , DAG ) ; case <STR_LIT> : return LowerVASTART ( Op , DAG ) ; case <STR_LIT> : return LowerVAARG ( Op , DAG ) ; case <STR_LIT> : return LowerVACOPY ( Op , DAG ) ; case <STR_LIT> : return LowerINTRINSIC_WO_CHAIN ( Op , DAG ) ; case <STR_LIT> : return LowerRETURNADDR ( Op , DAG ) ; case <STR_LIT> : return LowerFRAMEADDR ( Op , DAG ) ; case <STR_LIT> : return LowerFRAME_TO_ARGS_OFFSET ( Op , DAG ) ; case <STR_LIT> : return LowerDYNAMIC_STACKALLOC ( Op , DAG ) ; case <STR_LIT> : return LowerEH_RETURN ( Op , DAG ) ; case <STR_LIT> : return LowerTRAMPOLINE ( Op , DAG ) ; case <STR_LIT> : return LowerFLT_ROUNDS_ ( Op , DAG ) ; case <STR_LIT> : return LowerCTLZ ( Op , DAG ) ; case <STR_LIT> : return LowerCTTZ ( Op , DAG ) ; case <STR_LIT> : return LowerMUL_V2I64 (


<s> default : return Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; case AsmToken :: Identifier : if ( ! tryParseRegisterOperand ( Operands ) ) { return false ; } LLVM_FALLTHROUGH ; case AsmToken :: LParen : case AsmToken :: Integer : case AsmToken :: Dot : return tryParseExpression ( Operands ) ; case AsmToken :: Plus : case AsmToken :: Minus : { switch ( getLexer ( ) . peekTok ( ) . getKind ( ) ) { case AsmToken :: Integer : case AsmToken :: BigNum : case AsmToken :: Identifier : case AsmToken


<s> MCSymbol * PICBase = MF -> getPICBaseSymbol ( ) ; OutStreamer . EmitLabel ( RelocSymbol ) ; const MCExpr * OffsExpr = MCBinaryExpr :: CreateSub ( MCSymbolRefExpr :: Create ( OutContext . GetOrCreateSymbol ( Twine ( <STR_LIT> ) ) , OutContext ) , MCSymbolRefExpr :: Create ( PICBase , OutContext ) , OutContext ) ; OutStreamer . EmitValue ( OffsExpr , <NUM_LIT> ) ; OutStreamer . EmitLabel ( CurrentFnSym ) ; return ; } else return AsmPrinter :: EmitFunctionEntryLabel ( ) ; } if ( Subtarget . isELFv2ABI ( ) ) return AsmPrinter :: EmitFunctionEntryLabel ( ) ; MCSectionSubPair Current = OutStreamer . getCurrentSection ( ) ; const MCSectionELF * Section = OutStreamer . getContext ( ) . getELFSection ( <STR_LIT> , ELF :: SHT_PROGBITS , ELF :: SHF_WRITE | ELF :: SHF_ALLOC , SectionKind :: getReadOnly ( ) ) ; OutStreamer . SwitchSection ( Section ) ; OutStreamer . EmitLabel ( CurrentFnSym ) ; OutStreamer . EmitValueToAlignment ( <NUM_LIT> ) ; MCSymbol * Symbol1 = OutContext . GetOrCreateSymbol ( <STR_LIT> + Twine ( CurrentFnSym -> getName ( ) ) ) ; OutStreamer . EmitValue ( MCSymbolRefExpr :: Create ( Symbol1 , OutContext ) , <NUM_LIT> ) ; MCSymbol * Symbol2 = OutContext . GetOrCreateSymbol ( StringRef ( <STR_LIT> ) ) ; OutStreamer . EmitValue ( MCSymbolRefExpr :: Create ( Symbol2 , MCSymbolRefExpr :: VK_<ISA_LIT>_TOCBASE , OutContext ) , <NUM_LIT> ) ; OutStreamer . EmitIntValue ( <NUM_LIT> , <NUM_LIT> ) ; OutStreamer . SwitchSection ( Current . first , Current . second ) ; MCSymbol * RealFnSym = OutContext . GetOrCreateSymbol ( <STR_LIT> + Twine ( CurrentFnSym -> getName ( ) ) ) ; OutStreamer . EmitLabel ( RealFnSym ) ; CurrentFnSymForSize =


<s> DebugLoc dl ; if ( MI != MBB . end ( ) ) dl = MI -> getDebugLoc ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; const TargetInstrInfo & TII = * MF . getTarget ( ) . getInstrInfo ( ) ; <ISA_LIT>MachineFunctionInfo * MFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo >


<s> std :: list < fma_node * > * fma_node :: get_children ( ) { return this ->


<s> bool SelectAddrImmShift ( SDValue N , SDValue & Disp , SDValue


<s> void addImmWithOptionalShiftOperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT> ) ; if ( auto ShiftedVal = getShiftedVal < Shift > ( ) ) { Inst . addOperand ( MCOperand :: createImm ( ShiftedVal -> first ) ) ; Inst . addOperand ( MCOperand :: createImm ( ShiftedVal -> second ) ) ; } else if ( isShiftedImm ( ) ) { addExpr ( Inst , getShiftedImmVal ( ) ) ; Inst . addOperand ( MCOperand :: createImm ( getShiftedImmShift ( ) ) ) ; }


<s> } } } if ( LowGPR ) { assert ( LowGPR != HighGPR && <STR_LIT> ) ; MachineInstrBuilder MIB = BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) ) ; addSavedGPR ( MBB , MIB , LowGPR , false ) ; addSavedGPR ( MBB , MIB , HighGPR , false ) ; MIB . addReg ( <STR_LIT> ) . addImm ( StartOffset ) ; for ( unsigned I = <NUM_LIT> , E = CSI . size ( ) ; I != E ; ++ I ) { unsigned Reg = CSI [ I ] . getReg ( ) ; if ( <STR_LIT> . contains ( Reg ) ) addSavedGPR ( MBB , MIB , Reg , true ) ; } if ( IsVarArg ) for ( unsigned I = ZFI -> getVarArgsFirstGPR ( ) ; I < <STR_LIT> ; ++ I ) addSavedGPR ( MBB , MIB , <STR_LIT> [ I ] , true ) ; } for ( unsigned I = <NUM_LIT> , E = CSI . size ( ) ; I != E ; ++ I ) { unsigned Reg = CSI [ I ] . getReg ( ) ; if ( <STR_LIT> . contains ( Reg ) ) { MBB . addLiveIn ( Reg )


<s> errors = true ; } break ; } if ( ! flag_unsafe_math_optimizations ) for ( i = <NUM_LIT> ; i < ARRAY_SIZE ( nios2_fpu_insn ) ; i ++ ) if ( N2FPU_ENABLED_P ( i ) && N2FPU_UNSAFE_P ( i ) ) warning ( <NUM_LIT> , <STR_LIT> <STR_LIT> , N2FPU_NAME ( i ) ) ; if ( ! flag_finite_math_only ) for ( i = <NUM_LIT> ; i < ARRAY_SIZE ( nios2_fpu_insn ) ; i ++ ) if ( N2FPU_ENABLED_P ( i ) && N2FPU_FINITE_P ( i ) ) warning ( <NUM_LIT> , <STR_LIT> <STR_LIT> , N2FPU_NAME ( i ) ) ; if ( flag_errno_math ) for ( i = <NUM_LIT> ; i < ARRAY_SIZE ( nios2_fpu_insn ) ; i ++ ) if ( N2FPU_ENABLED_P ( i ) && N2FPU_NO_ERRNO_P ( i ) ) warning (


<s> static unsigned getShuffleSHUFImmediate ( ShuffleVectorSDNode * N ) { MVT VT = N -> getSimpleValueType ( <NUM_LIT> ) ; assert ( ( VT . getSizeInBits ( ) >= <NUM_LIT> ) && <STR_LIT> ) ; unsigned NumElts = VT . getVectorNumElements ( ) ; unsigned NumLanes = VT . getSizeInBits ( ) / <NUM_LIT> ; unsigned NumLaneElts = NumElts / NumLanes ; assert ( ( NumLaneElts == <NUM_LIT> || NumLaneElts == <NUM_LIT> || NumLaneElts == <NUM_LIT> ) && <STR_LIT> ) ; unsigned Shift = ( NumLaneElts >= <NUM_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; unsigned Mask = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> ; i != NumElts ; ++ i ) { int Elt = N -> getMaskElt ( i ) ; if ( Elt < <NUM_LIT>


<s> for ( regno = FIRST_PSEUDO_REGISTER - <NUM_LIT> ; regno >= <NUM_LIT> ; regno -- ) if ( ix86_save_reg ( regno , true ) ) nregs ++ ; return


<s> rtx op0 = nds32_read_argument ( exp , <NUM_LIT> ) ; rtx addr_helper = gen_reg_rtx ( insn_data [ icode ] . operand [ <NUM_LIT> ] . mode ) ; target = nds32_legitimize_target ( icode , target ) ; op0 = nds32_legitimize_argument ( icode , <NUM_LIT> , op0 ) ; pat = GEN_FCN ( icode ) ( target , op0 , addr_helper ) ; if ( ! pat ) return NULL_RTX ; emit_move_insn ( addr_helper , GEN_INT ( <NUM_LIT> ) ) ; emit_insn ( pat ) ; return


<s> if ( misalignment == - <NUM_LIT> ) { if ( rs6000_vector_alignment_reachable ( type , is_packed ) ) { int element_size = TREE_INT_CST_LOW ( TYPE_SIZE ( type ) ) ; if ( element_size == <NUM_LIT> || element_size == <NUM_LIT> ) return true ; } return false ; } if ( misalignment % <NUM_LIT> == <NUM_LIT> ) return


<s> bool <ISA_LIT>InvISelDAG :: SelectAddrMode3 ( SDValue N , SDValue & Base , SDValue & Offset , SDValue & Opc ) { return true


<s> Triple TheTriple ( TT ) ; bool is<ISA_LIT>64 = ( TheTriple . getArch ( ) == Triple :: ppc64 || TheTriple . getArch ( ) == Triple :: ppc64le ) ; MCAsmInfo * MAI ; if ( TheTriple . isOSDarwin ( ) ) MAI = new <ISA_LIT>MCAsmInfoDarwin ( is<ISA_LIT>64 , TheTriple ) ; else MAI = new <ISA_LIT>LinuxMCAsmInfo ( is<ISA_LIT>64 ,


<s> case MCSymbolRefExpr :: VK_<ISA_LIT>_TLSLDM : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_DTPREL_HI : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_DTPREL_LO : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOTTPREL : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_TPREL_HI : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_TPREL_LO : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GPOFF_HI : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GPOFF_LO : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_DISP : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_PAGE : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_OFST : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_HIGHER : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_HIGHEST : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_HI16 : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_LO16 : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_CALL_HI16 : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_CALL_LO16 : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_PCREL_HI16 : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_PCREL_LO16 : OS << <STR_LIT> ; break ; } OS << SRE -> getSymbol ( ) ; if ( Offset ) { if ( Offset > <NUM_LIT>


<s> assert ( MI -> getNumOperands ( ) == <NUM_LIT> && <STR_LIT> ) ; assert ( MI -> getOperand ( <NUM_LIT> ) . isReg ( ) && MI -> getOperand ( <NUM_LIT> ) .


<s> SDLoc DL ( Op ) ; SDValue Vec = Op . getOperand ( <NUM_LIT> ) ; EVT VecEVT = Vec . getValueType ( ) ; if ( ! isTypeLegal ( VecEVT ) ) return SDValue ( ) ; MVT VecVT = VecEVT . getSimpleVT ( ) ; MVT VecEltVT = VecVT . getVectorElementType ( ) ; unsigned RVVOpcode = getRVVVPReductionOp ( Op . getOpcode ( ) ) ; MVT ContainerVT = VecVT ; if ( VecVT . isFixedLengthVector ( ) ) { ContainerVT = getContainerForFixedLengthVector ( VecVT ) ; Vec = convertToScalableVector ( ContainerVT , Vec , DAG , Subtarget ) ; } SDValue VL = Op . getOperand ( <NUM_LIT> ) ; SDValue Mask = Op . getOperand ( <NUM_LIT> ) ; MVT M1VT = getLMUL1VT ( ContainerVT ) ; MVT XLenVT = Subtarget . getXLenVT ( ) ; MVT ResVT = ! VecVT . isInteger ( ) || VecEltVT . bitsGE ( XLenVT ) ? VecEltVT : XLenVT ; SDValue StartSplat = lowerScalarSplat ( SDValue ( ) , Op . getOperand ( <NUM_LIT> ) , DAG . getConstant ( <NUM_LIT> , DL , XLenVT ) , M1VT , DL , DAG , Subtarget ) ; SDValue Reduction = DAG . getNode ( RVVOpcode , DL , M1VT , StartSplat , Vec , StartSplat , Mask , VL ) ; SDValue Elt0 = DAG . getNode ( <STR_LIT> , DL , ResVT , Reduction

, DAG . getConstant ( <NUM_LIT> , DL , XLenVT ) ) ;


<s> if ( VecTy . getVectorElementType ( ) != <STR_LIT> ) { assert ( ( ElemSize == <NUM_LIT> || ElemSize == <NUM_LIT> ) && <STR_LIT> ) ; unsigned OpsPerWord = ( ElemSize == <NUM_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; MVT PartVT = <STR_LIT> ( VecTy . getVectorElementType ( ) , OpsPerWord ) ; for ( unsigned i = <NUM_LIT> ; i != VecLen ; i += OpsPerWord ) { SDValue W = buildVector32 ( Values . slice ( i , OpsPerWord ) , dl , PartVT , DAG ) ; Words . push_back ( DAG . getBitcast ( <STR_LIT> , W ) ) ; } } else { Words . assign ( Values . begin ( ) , Values . end ( ) ) ; } unsigned NumWords = Words . size ( ) ; bool IsSplat = true , IsUndef = true ; SDValue SplatV ; for ( unsigned i = <NUM_LIT> ; i != NumWords && IsSplat ; ++ i ) { if ( isUndef ( Words [ i ] ) ) continue ; IsUndef = false ; if ( ! SplatV . getNode ( ) ) SplatV = Words [ i ] ; else if ( SplatV != Words [ i ] ) IsSplat = false ; } if ( IsUndef ) return DAG . getUNDEF ( VecTy ) ; if ( IsSplat ) { assert ( SplatV . getNode ( ) ) ; auto * IdxN = dyn_cast < ConstantSDNode > ( SplatV . getNode ( ) ) ; if ( IdxN && IdxN -> isNullValue ( ) ) return getZero ( dl , VecTy , DAG ) ; MVT WordTy = <STR_LIT> ( <STR_LIT> , HwLen / <NUM_LIT> ) ; SDValue S = DAG . getNode ( <STR_LIT> , dl , WordTy , SplatV ) ; return DAG . getBitcast ( VecTy , S ) ; } SmallVector < ConstantInt * , <NUM_LIT> > Consts ( VecLen ) ; bool AllConst = getBuildVectorConstInts ( Values , VecTy , DAG , Consts ) ; if ( AllConst ) { ArrayRef < Constant * > Tmp ( ( Constant * * ) Consts . begin ( ) , ( Constant * * ) Consts . end ( ) ) ; Constant * CV = ConstantVector :: get ( Tmp ) ; Align Alignment ( HwLen ) ; SDValue CP = LowerConstantPool ( DAG . getConstantPool ( CV , VecTy , Alignment ) , DAG ) ; return DAG . getLoad ( VecTy , dl , DAG . getEntryNode ( ) , CP , MachinePointerInfo :: getConstantPool ( MF ) , Alignment ) ; } auto IsBuildFromExtracts = [ this , & Values ] ( SDValue & SrcVec , SmallVectorImpl < int > & SrcIdx ) { SDValue Vec ; for ( SDValue V : Values ) { if ( isUndef ( V ) ) { SrcIdx . push_back ( - <NUM_LIT> ) ; continue ; } if ( V . getOpcode ( ) != <STR_LIT> ) return false ; SDValue T = V . getOperand ( <NUM_LIT>


<s> unsigned FrameReg = getFrameRegister ( MF ) ; if ( Subtarget . isTarget64BitILP32 ( ) ) FrameReg =

get<ISA_LIT>SubSuperRegister ( FrameReg , <STR_LIT> , false ) ;


<s> LLVM_EXTERNAL_VISIBILITY void LLVMInitialize<ISA_LIT>TargetInfo ( ) { RegisterTarget < Triple :: csky > X ( getThe<ISA_LIT>Target

( ) , <STR_LIT> , <STR_LIT> , <STR_LIT> ) ;


<s> return Base :: SelectSectionForGlobal ( GO , Kind , TM ) ; } if ( ! <ISA_LIT>TM . getSubtargetImpl ( ) -> hasELPM ( ) && <STR_LIT> ( GO ) != <STR_LIT> ) { getContext ( ) . reportError ( SMLoc ( ) , <STR_LIT> <STR_LIT> ) ; return ProgmemDataSection ; } switch ( <STR_LIT> ( GO ) ) { case <STR_LIT> : return ProgmemDataSection ; case <STR_LIT> : return Progmem1DataSection ; case <STR_LIT> : return Progmem2DataSection ; case <STR_LIT> : return Progmem3DataSection ; case <STR_LIT> : return Progmem4DataSection ; case <STR_LIT> : return Progmem5DataSection ; default : llvm_unreachable ( <STR_LIT> ) ; } } return Base :: SelectSectionForGlobal ( GO , Kind , TM


<s> <STR_LIT> MIbG = getDuplexCandidateGroup ( MIb ) ; return ( isDuplexPairMatch ( MIaG , MIbG ) || isDuplexPairMatch (


<s> static int getMemoryOpOffset ( const MachineInstr * MI ) { int Opcode = MI -> getOpcode ( ) ; bool isAM3 = Opcode == <STR_LIT> || Opcode == <STR_LIT> ; unsigned NumOperands = MI -> getDesc ( ) . getNumOperands ( ) ; unsigned OffField = MI -> getOperand ( NumOperands - <NUM_LIT> ) . getImm ( ) ; if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ) return OffField ; int Offset = isAM3 ? <STR_LIT> ( OffField ) : <STR_LIT> ( OffField ) * <NUM_LIT> ; if ( isAM3 ) { if ( <STR_LIT> ( OffField ) == <STR_LIT> ) Offset = - Offset ; } else { if ( <STR_LIT> ( OffField ) == <STR_LIT> ) Offset = - Offset ; } return


<s> bool useHVXDblOps ( ) const { return UseHVXOps &&


<s> bool <ISA_LIT>TargetLowering :: shouldSplitVectorType ( EVT VT ) const { return VT . getScalarType ( )


<s> void <ISA_LIT>TargetAsmStreamer :: emitGlobalType ( const MCSymbolWasm * Sym ) { assert ( Sym -> isGlobal ( ) ) ; OS << <STR_LIT> << Sym -> getName ( ) << <STR_LIT> << <STR_LIT> ( static_cast < <STR_LIT> > ( Sym -> getGlobalType (


<s> bool isSubregFoldable ( ) const override { return true


<s> unsigned int Value = MI -> getOperand ( OpNo ) . getImm ( ) ; assert ( Value <= <NUM_LIT> && <STR_LIT> ) ; O << ( unsigned int


<s> void <ISA_LIT>AsmParser :: getMnemonicAcceptInfo ( StringRef Mnemonic , StringRef FullInst , bool & CanAcceptCarrySet , bool & CanAcceptPredicationCode ) { CanAcceptCarrySet = Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic

== <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || ( ! isThumb ( ) && ( Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> ) ) ;


<s> auto * DRC = getFinalVRegClass ( RD , MRI ) ; if ( ! DRC ) return false ; return DRC == getFinalVRegClass ( RS , MRI


<s> std :: pair < SDValue , SDValue > Vals = FP_TO_INTHelper ( Op , DAG , false , false ) ; SDValue FIST = Vals . first , StackSlot = Vals . second ; if ( ! FIST . getNode ( ) ) return Op ; if ( StackSlot . getNode ( ) ) return DAG . getLoad ( Op . getValueType ( ) , SDLoc ( Op ) , FIST , StackSlot , MachinePointerInfo ( ) ) ; return


<s> Src = mN -> getMemOperand ( ) -> getValue ( ) ; } else if ( MemSDNode * mN = dyn_cast < MemIntrinsicSDNode > ( N ) ) { if ( spN == <NUM_LIT> && mN -> getMemOperand ( ) -> getPseudoValue ( ) ) return true ; Src = mN -> getMemOperand ( ) -> getValue


<s> MachineBasicBlock * MBB = MI -> getParent ( ) ; const MachineFunction * MF = MI -> getParent ( ) -> getParent ( ) ; const <ISA_LIT>InstrInfo * TII = static_cast < const <ISA_LIT>InstrInfo * > ( MF -> getSubtarget ( ) . getInstrInfo ( ) ) ; LLVMContext & Ctx = MF -> getFunction ( ) -> getContext ( ) ; DebugLoc DL = MI -> getDebugLoc ( ) ; bool IsLoad = TII -> get ( LoadStoreOp ) . mayLoad ( ) ; bool RanOutOfSGPRs = false ; unsigned SOffset = ScratchOffset ; unsigned NumSubRegs = getNumSubRegsForSpillOp ( MI -> getOpcode ( ) ) ; unsigned Size = NumSubRegs * <NUM_LIT> ; if ( ! isUInt < <NUM_LIT> > ( Offset + Size ) ) { SOffset = RS -> scavengeRegister ( & <STR_LIT> , MI , <NUM_LIT> ) ; if ( SOffset == <STR_LIT>


<s> } if ( DCI . isBeforeLegalizeOps ( ) ) return SDValue ( ) ; if ( N -> getNumOperands ( ) == <NUM_LIT> && N0Opc == N1Opc && ( N0Opc == <STR_LIT> || N0Opc == <STR_LIT> || N0Opc == <STR_LIT> || N0Opc == <STR_LIT> ) ) { SDValue N00 = N0 -> getOperand ( <NUM_LIT> ) ; SDValue N01 = N0 -> getOperand ( <NUM_LIT> ) ; SDValue N10 = N1 -> getOperand ( <NUM_LIT> ) ; SDValue N11 = N1 -> getOperand ( <NUM_LIT> ) ; EVT N00VT = N00 . getValueType ( ) ; EVT N10VT = N10 . getValueType ( ) ; if ( N00 -> getOpcode ( ) == <STR_LIT> && N01 -> getOpcode ( ) == <STR_LIT> && N10 -> getOpcode ( ) == <STR_LIT> && N11 -> getOpcode ( ) == <STR_LIT> && N00VT == N10VT ) { SDValue N00Source = N00 -> getOperand ( <NUM_LIT> ) ; SDValue N01Source = N01 -> getOperand ( <NUM_LIT> ) ; SDValue N10Source = N10 -> getOperand ( <NUM_LIT> ) ; SDValue N11Source = N11 -> getOperand ( <NUM_LIT> ) ; if ( N00Source == N10Source && N01Source == N11Source && N00Source . getValueType ( ) == VT && N01Source . getValueType ( ) == VT ) { assert ( N0 . getValueType ( ) == N1 . getValueType ( ) ) ; uint64_t N00Index = N00 . getConstantOperandVal ( <NUM_LIT> ) ; uint64_t N01Index = N01 . getConstantOperandVal ( <NUM_LIT> ) ; uint64_t N10Index = N10 . getConstantOperandVal ( <NUM_LIT> ) ; uint64_t N11Index = N11 . getConstantOperandVal ( <NUM_LIT> ) ; if ( N00Index == N01Index && N10Index == N11Index && N00Index == <NUM_LIT> && N10Index == N00VT . getVectorNumElements ( ) ) return DAG . getNode ( N0Opc , dl , VT , N00Source , N01Source ) ; } } } if ( N -> getNumOperands ( ) == <NUM_LIT> && N0 == N1 && VT . getVectorNumElements ( ) == <NUM_LIT> ) { assert ( VT . getScalarSizeInBits ( ) == <NUM_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , VT , WidenVector ( N0 , DAG ) , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; } if ( N -> getNumOperands ( ) != <NUM_LIT> || N1Opc != <STR_LIT> ) return SDValue ( ) ; SDValue RHS = N1 -> getOperand ( <NUM_LIT> ) ; MVT RHSTy = RHS . getValueType ( ) . getSimpleVT ( ) ; if ( ! RHSTy . isVector ( ) ) return SDValue ( ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; MVT ConcatTy = <STR_LIT> ( RHSTy . getVectorElementType ( ) , RHSTy .

getVectorNumElements ( ) * <NUM_LIT> ) ;


<s> if ( GET_CODE ( x ) == MEM ) x = XEXP ( x , <NUM_LIT> ) ; if ( TARGET_64BIT ) { if ( GET_CODE ( x ) != CONST || GET_CODE ( XEXP ( x , <NUM_LIT> ) ) != UNSPEC || XINT ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) != UNSPEC_GOTPCREL || GET_CODE ( orig_x ) != MEM ) return orig_x ; return XVECEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> , <NUM_LIT> ) ; } if ( GET_CODE ( x ) != PLUS || GET_CODE ( XEXP ( x , <NUM_LIT> ) ) != CONST ) return orig_x ; if ( GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == REG && REGNO ( XEXP ( x , <NUM_LIT> ) ) == PIC_OFFSET_TABLE_REGNUM ) y = NULL ; else if ( GET_CODE ( XEXP ( x , <NUM_LIT>


<s> unsigned AddressSpace = getAddressSpace ( ) ; Module * M = IRB . GetInsertBlock ( ) -> getParent ( ) -> getParent ( ) ; int Offset = M -> getStackProtectorGuardOffset ( ) ; if ( Offset == INT_MAX ) Offset = ( Subtarget . is64Bit ( ) ) ? <NUM_LIT> : <NUM_LIT> ; StringRef GuardReg = M -> getStackProtectorGuardReg ( ) ; if ( GuardReg == <STR_LIT> ) AddressSpace = <STR_LIT> ; else if ( GuardReg == <STR_LIT> ) AddressSpace = <STR_LIT> ; return SegmentOffset ( IRB , Offset , AddressSpace ) ; } } return TargetLowering :: getIRStackGuard


<s> bool <ISA_LIT>FrameLowering :: adjustStackWithPops ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI , const DebugLoc & DL , int Offset ) const { if ( Offset <= <NUM_LIT> ) return false ; if ( Offset % SlotSize ) return false ; int NumPops = Offset / SlotSize ; if ( NumPops != <NUM_LIT> && NumPops != <NUM_LIT> ) return false ; if ( MBBI == MBB . begin ( ) ) return false ; MachineBasicBlock :: iterator Prev = std :: prev ( MBBI ) ; if ( ! Prev -> isCall ( ) || ! Prev -> getOperand ( <NUM_LIT> ) . isRegMask ( ) ) return false ; unsigned Regs [ <NUM_LIT> ] ; unsigned FoundRegs = <NUM_LIT> ; auto & MRI = MBB . getParent ( ) -> getRegInfo ( ) ; auto RegMask = Prev -> getOperand (


<s> <ISA_LIT>ScheduleBlock * Block = ScheduledBlocks [ b ] ; std :: vector < SUnit * > SUs = Block -> getScheduledUnits ( ) ; for ( SUnit * SU : SUs ) Res . SUs . push_back ( SU -> NodeNum ) ; } Res . MaxSGPRUsage = Scheduler . getSGPRUsage ( ) ; Res . MaxVGPRUsage = Scheduler . getVGPRUsage ( ) ; return Res


<s> for ( unsigned i = <NUM_LIT> ; i != <NUM_LIT> ; ++ i ) { Tys [ <NUM_LIT> ] = PointerType :: get ( I8Ty , i ) ; Name = <STR_LIT> ( <STR_LIT> , Tys ) ; ReflectFunction = M . getFunction ( Name ) ; if ( ReflectFunction != <NUM_LIT> ) { Res |= handleFunction ( ReflectFunction ) ; } } ReflectFunction = M . getFunction ( NVVM_REFLECT_FUNCTION ) ; if ( ReflectFunction != <NUM_LIT> ) Res |= handleFunction ( ReflectFunction ) ; return


<s> void <ISA_LIT>FrameLowering :: determineCalleeSaves ( MachineFunction & MF , BitVector & SavedRegs , RegScavenger * RS ) const { TargetFrameLowering :: determineCalleeSaves ( MF


<s> MachineOperand * Op = & * MRI -> use_nodbg_begin ( Reg ) ; MachineInstr * UseMI = Op -> getParent ( ) ; while ( UseMI -> isCopy ( ) && ! Op -> getSubReg ( ) ) { Reg = UseMI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( ! TRI -> isVGPR ( * MRI , Reg ) || ! MRI -> hasOneNonDBGUse ( Reg ) ) return false ; Op = & * MRI -> use_nodbg_begin ( Reg ) ; UseMI = Op -> getParent ( ) ; } if ( Op -> getSubReg ( ) ) return false ; unsigned OpIdx = Op - & UseMI -> getOperand ( <NUM_LIT> ) ; const MCInstrDesc & InstDesc = UseMI -> getDesc ( ) ; if ( ! TRI -> isVectorSuperClass ( TRI -> getRegClass ( InstDesc . OpInfo [ OpIdx ] . RegClass ) ) ) return false ; const auto * NewDstRC = TRI -> getEquivalentAGPRClass ( MRI -> getRegClass ( Reg ) ) ; auto Dst = MRI -> createVirtualRegister ( NewDstRC ) ; auto RS = BuildMI ( * MI . getParent ( ) , MI , MI . getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , Dst ) ; for ( unsigned I = <NUM_LIT> ; I < Defs . size ( ) ; ++ I ) { MachineOperand * Def = Defs [ I ] . first ; Def -> setIsKill ( false ) ; if ( TRI -> isAGPR ( * MRI , Def -> getReg ( ) ) ) { RS . add ( * Def ) ; } else { MachineInstr * SubDef = MRI -> getVRegDef (


<s> else if ( ConstraintCode == <STR_LIT> ) return InlineAsm :: Constraint_Q ; else if ( ConstraintCode == <STR_LIT> ) return InlineAsm :: Constraint_Z ; else if ( ConstraintCode == <STR_LIT> ) return InlineAsm :: Constraint_Zy ; return TargetLowering :: getInlineAsmMemConstraint


<s> DecodeUNPCKLPMask ( <STR_LIT> ( <STR_LIT> , NElts ) ,


<s> assert ( DstRegOp . isReg ( ) && <STR_LIT> ) ; const MCOperand & ImmOp = Inst . getOperand ( <NUM_LIT> ) ; assert ( ( ImmOp . isImm ( ) || ImmOp . isExpr ( ) ) && <STR_LIT> ) ; if ( ! ImmOp . isImm ( ) ) { if ( loadAndAddSymbolAddress ( ImmOp . getExpr ( ) , DstRegOp . getReg ( ) , <STR_LIT> , Is32BitImm , IDLoc , Instructions ) ) return true ; return false ; } if ( loadImmediate ( ImmOp . getImm ( ) , DstRegOp . getReg ( ) , <STR_LIT> , Is32BitImm , IDLoc , Instructions ) ) return true ; return false


<s> SDValue ExpPart = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Hi , DAG . getConstant ( FractBits - <NUM_LIT> , SL , <STR_LIT> ) , DAG . getConstant ( ExpBits , SL , <STR_LIT> ) ) ; SDValue Exp = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , ExpPart , DAG

. getConstant ( <NUM_LIT> , SL , <STR_LIT> ) ) ;


<s> uint64_t <ISA_LIT>FrameLowering :: estimateStackSize ( const MachineFunction & MF ) const { const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const TargetRegisterInfo & TRI = * STI . getRegisterInfo ( ) ; int64_t Offset = <NUM_LIT> ; for ( int I = MFI -> getObjectIndexBegin ( ) ; I != <NUM_LIT> ; ++ I ) Offset = std :: max ( Offset , - MFI -> getObjectOffset ( I ) ) ; for ( const MCPhysReg * R = TRI . getCalleeSavedRegs ( & MF ) ; * R ; ++ R ) { unsigned Size = TRI . getMinimalPhysRegClass ( * R )


<s> unsigned getMaxDisp ( ) const { return MaxDisp - <NUM_LIT>


<s> unsigned getNumberOfRegisters ( bool Vector ) { if ( Vector ) { if ( ST -> hasNEON ( ) ) return <NUM_LIT> ; return <NUM_LIT>


<s> if ( SrcReg == <STR_LIT> ) { Warning ( IDLoc , <STR_LIT> ) ; if ( loadImmediate ( <NUM_LIT> , DstReg , <STR_LIT> , true , false , IDLoc , Out , STI ) ) return true ; return false ; } unsigned Opc ; if ( ImmValue > - <NUM_LIT> && ImmValue < <NUM_LIT> ) { ImmValue = - ImmValue ; Opc = isGP64bit ( ) ? <STR_LIT> : <STR_LIT> ; } else { Opc = <STR_LIT> ; } if ( isUInt < <NUM_LIT> > ( ImmValue ) ) { TOut . emitRRI ( Opc , DstReg , SrcReg , ImmValue , IDLoc , STI ) ; TOut . emitRRR ( <STR_LIT> , DstReg , <STR_LIT> , DstReg , IDLoc , STI ) ; return false ; } unsigned ATReg = getATReg ( IDLoc ) ; if ( ! ATReg ) return true ; if ( loadImmediate ( ImmValue , ATReg , <STR_LIT> , isInt < <NUM_LIT> > ( ImmValue ) , false , IDLoc , Out , STI ) ) return true ; TOut . emitRRR ( <STR_LIT> , DstReg , SrcReg , ATReg , IDLoc , STI ) ; TOut . emitRRR ( <STR_LIT> , DstReg , <STR_LIT> , DstReg , IDLoc , STI ) ; return false


<s> default : return true ; case ELF :: R_<ISA_LIT>_PREL31 : case ELF :: R_<ISA_LIT>_ABS32


<s> if ( ! VRegs . empty ( ) ) { MachineFunction & MF = MIRBuilder . getMF ( ) ; const Function & F = MF . getFunction ( ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; auto & DL = MF . getDataLayout ( ) ; LLVMContext & Ctx = Val -> getType ( ) -> getContext ( ) ; const <ISA_LIT>TargetLowering & TLI = * getTLI < <ISA_LIT>TargetLowering > ( ) ; SmallVector < EVT , <NUM_LIT> > SplitEVTs ; ComputeValueVTs ( TLI , DL , Val -> getType ( ) , SplitEVTs ) ; assert ( VRegs . size ( ) ==


<s> static rtx arc_legitimize_address ( rtx orig_x , rtx oldx , machine_mode mode ) { rtx new_x = arc_legitimize_address_0 ( orig_x , oldx , mode ) ; if ( new_x ) return new_x ; return


<s> unsigned <ISA_LIT>InstrInfo :: removeBranch ( MachineBasicBlock & MBB , int * BytesRemoved ) const { MachineBasicBlock :: iterator I = MBB . getFirstTerminator ( ) ; unsigned Count = <NUM_LIT> ; unsigned RemovedSize = <NUM_LIT> ; while ( I != MBB . end ( ) ) { MachineBasicBlock :: iterator Next = std :: next ( I ) ; RemovedSize += getInstSizeInBytes ( * I ) ; I -> eraseFromParent ( ) ; ++ Count ; I = Next ; } if ( BytesRemoved ) * BytesRemoved =


<s> bool <ISA_LIT>TargetLowering :: shouldExpandAtomicStoreInIR ( StoreInst * SI ) const { return SI -> getValueOperand ( ) -> getType ( )

-> getPrimitiveSizeInBits ( ) > <NUM_LIT> ;


<s> LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * MI << '\n' ) ; <ISA_LIT>MCInstLower InstLower ( OutContext , * this ) ; MCInst TmpInst ; InstLower . Lower ( MI


<s> return D ( <STR_LIT> , MemR ( a , as ) ,


<s> if ( TheTriple . isOSBinFormatMachO ( ) ) return new Darwin<ISA_LIT>AsmBackend ( T , MRI ) ; if ( TheTriple . isOSBinFormatCOFF ( ) ) return new COFF<ISA_LIT>AsmBackend ( T , TheTriple ) ; assert ( TheTriple . isOSBinFormatELF ( ) && <STR_LIT> ) ; uint8_t OSABI = MCELFObjectTargetWriter :: getOSABI ( TheTriple . getOS ( ) ) ; bool IsILP32 = Options . getABIName ( ) == <STR_LIT> ; return new ELF<ISA_LIT>AsmBackend ( T , OSABI , true ,


<s> case TargetTransformInfo :: RGK_Scalar : return TypeSize :: getFixed ( ST -> getXLen ( ) ) ; case TargetTransformInfo :: RGK_FixedWidthVector : return TypeSize :: getFixed ( ST -> hasStdExtV ( ) ? ST -> getMinRVVVectorSizeInBits


<s> TargetLoweringObjectFile * getObjFileLowering ( ) const override { return TLOF . get


<s> else if ( strcmp ( argv [ <NUM_LIT> ] , <STR_LIT> ) == <NUM_LIT> ) msp430_warn_devices_csv = atoi ( argv [ <NUM_LIT> ] ) ; else if ( strcmp ( argv [ <NUM_LIT> ] , <STR_LIT> ) == <NUM_LIT> ) msp430_devices_csv_loc = argv [ <NUM_LIT> ] ; else error ( <STR_LIT> , argv [ <NUM_LIT> ] , argv [ <NUM_LIT> ] ) ; return NULL


<s> if ( auto * AmtBV = dyn_cast < BuildVectorSDNode > ( Amt ) ) if ( auto * AmtSplat = AmtBV -> getConstantSplatNode ( ) ) { APInt ShiftAmt = AmtSplat -> getAPIntValue ( ) ; unsigned MaxAmount = VT . getSimpleVT ( ) . getVectorElementType ( ) . getSizeInBits ( ) ; if ( ShiftAmt . trunc ( <NUM_LIT> ) . uge ( MaxAmount ) ) return getZeroVector ( VT . getSimpleVT ( ) , Subtarget , DAG , DL ) ; } return SDValue


<s> return ( IsGlobalInSmallSectionImpl ( GV , TM ) && ( Kind . isDataRel ( ) || Kind .


<s> if ( ! insn -> can_be_optimized ( ) || insn -> is_asm ( ) || insn

-> has_volatile_refs ( ) || insn -> has_pre_post_modify ( ) ) return NULL_RTX ;


<s> const char * getPassName ( ) const override { return


<s> static std :: map < StringRef , unsigned > ElfFlags = { { <STR_LIT> , ELF :: EF_HEXAGON_MACH_V5 } , { <STR_LIT> , ELF :: EF_HEXAGON_MACH_V55 } , { <STR_LIT> , ELF :: EF_HEXAGON_MACH_V60

} , { <STR_LIT> , ELF :: EF_HEXAGON_MACH_V62 } , { <STR_LIT> , ELF :: EF_HEXAGON_MACH_V65 } , } ;


<s> __asm__ ( <STR_LIT> : <STR_LIT> ( ( ( char * ) p ) [


<s> assert ( <STR_LIT> . contains ( DstReg , SrcReg ) && <STR_LIT> ) ; BuildMI ( MBB , MBBI , DL , get ( <STR_LIT> ) , DstReg ) . addReg ( SrcReg


<s> for ( unsigned I = <NUM_LIT> ; I != array_lengthof ( HardFloatLibCalls ) ; ++ I ) { assert ( ( I == <NUM_LIT> || HardFloatLibCalls [ I - <NUM_LIT> ] < HardFloatLibCalls [ I ] ) && <STR_LIT> ) ; if ( HardFloatLibCalls [ I ] . Libcall != RTLIB :: UNKNOWN_LIBCALL ) setLibcallName ( HardFloatLibCalls [ I ] . Libcall , HardFloatLibCalls [ I ]


<s> set_mem_size ( mem , GET_MODE_SIZE ( mode ) ) ; do_load_for_compare ( dest ,


<s> unsigned NumLoads = alignTo ( VecWidth , AlignWidth ) / AlignWidth ; return <NUM_LIT> * NumLoads ; } unsigned Cost = VecTy -> getElementType ( ) -> isFloatingPointTy ( ) ? FloatFactor : <NUM_LIT> ; Alignment = std :: min ( Alignment , <NUM_LIT> ) ; unsigned AlignWidth = <NUM_LIT> * std :: max ( <NUM_LIT> , Alignment ) ; unsigned NumLoads = alignTo ( VecWidth , AlignWidth ) / AlignWidth ; if ( Alignment == <NUM_LIT> || Alignment == <NUM_LIT>


<s> assert ( MI . isRegSequence ( ) ) ; Register DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( ! TRI -> isSGPRClass ( MRI . getRegClass ( DstReg ) ) ) return false ; if ( ! MRI . hasOneUse ( DstReg ) ) return false ; MachineInstr & CopyUse = * MRI . use_instr_begin ( DstReg ) ; if ( ! CopyUse . isCopy ( ) ) return false ; if ( Register :: isPhysicalRegister ( CopyUse . getOperand ( <NUM_LIT> ) . getReg ( ) ) ) return false ; const TargetRegisterClass * SrcRC , * DstRC ; std :: tie ( SrcRC , DstRC ) = getCopyRegClasses ( CopyUse , * TRI , MRI ) ; if ( ! isSGPRToVGPRCopy ( SrcRC , DstRC , * TRI ) ) return false ; if ( tryChangeVGPRtoSGPRinCopy ( CopyUse , TRI , TII ) ) return true ; unsigned SubReg = CopyUse . getOperand ( <NUM_LIT> ) . getSubReg ( ) ; if ( SubReg != <STR_LIT> ) return false ; MRI . setRegClass ( DstReg , DstRC ) ; MI . getOperand ( <NUM_LIT> ) . setReg ( CopyUse . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; bool IsAGPR = TRI -> hasAGPRs ( DstRC ) ; for ( unsigned I = <NUM_LIT> , N = MI . getNumOperands ( ) ; I != N ; I += <NUM_LIT> ) { Register SrcReg = MI . getOperand ( I ) . getReg ( ) ; unsigned SrcSubReg = MI . getOperand ( I ) . getSubReg ( ) ; const TargetRegisterClass * SrcRC = MRI . getRegClass ( SrcReg ) ; assert ( TRI -> isSGPRClass ( SrcRC ) && <STR_LIT> ) ; SrcRC = TRI -> getSubRegClass ( SrcRC , SrcSubReg ) ; const TargetRegisterClass * NewSrcRC = TRI -> getEquivalentVGPRClass ( SrcRC ) ; Register TmpReg = MRI . createVirtualRegister ( NewSrcRC ) ; BuildMI ( * MI . getParent ( ) , & MI , MI . getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , TmpReg ) . add ( MI . getOperand ( I ) ) ; if ( IsAGPR ) { const TargetRegisterClass * NewSrcRC = TRI -> getEquivalentAGPRClass ( SrcRC ) ; Register TmpAReg = MRI . createVirtualRegister ( NewSrcRC ) ; unsigned Opc = NewSrcRC == & <STR_LIT> ? <STR_LIT> : <STR_LIT> ; BuildMI ( * MI . getParent ( ) , & MI , MI . getDebugLoc ( ) , TII -> get ( Opc ) ,

TmpAReg ) . addReg ( TmpReg , RegState :: Kill ) ;


<s> SDLoc dl ( Op ) ; Offset = CurDAG -> getTargetConstant ( <NUM_LIT> , dl , VT ) ; if ( auto FIN = dyn_cast < FrameIndexSDNode > ( Addr ) ) { Base = CurDAG -> getTargetFrameIndex ( FIN -> getIndex ( )


<s> unsigned getMaxSVEVectorSizeInBits ( )


<s> void forwardVPTPosition ( ) { if ( ! inVPTBlock ( )


<s> MCRegisterInfo * X = new MCRegisterInfo ( ) ; Init<ISA_LIT>MCRegisterInfo ( X , <STR_LIT> , <NUM_LIT> , <NUM_LIT>


<s> aapcs_cp_arg_layout [ pcum -> aapcs_cprc_slot ] . advance ( pcum , mode , type ) ; pcum -> aapcs_cprc_slot = - <NUM_LIT> ; } pcum -> aapcs_arg_processed = false ; pcum -> aapcs_ncrn = pcum -> aapcs_next_ncrn ; pcum -> aapcs_reg = NULL_RTX ; pcum -> aapcs_partial = <NUM_LIT> ; } else { pcum -> nargs += <NUM_LIT> ; if ( arm_vector_mode_supported_p ( mode ) && pcum -> named_count > pcum -> nargs && TARGET_IWMMXT_ABI ) pcum -> iwmmxt_nregs += <NUM_LIT> ; else pcum -> nregs += ARM_NUM_REGS2 ( mode


<s> return ( __m128i ) __builtin_ia32_movntdqa ( ( __v2di


<s> switch ( Opc ) { default : return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { if ( PostRA ) return false ; bool Changed = false ; unsigned DefReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; int64_t Comparand = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; int64_t SExtComparand = ( ( uint64_t ) Comparand & ~ <NUM_LIT> ) != <NUM_LIT> ? ( Comparand | <NUM_LIT> ) : Comparand ; for ( auto & CompareUseMI : MRI -> use_instructions ( DefReg ) ) { unsigned UseOpc = CompareUseMI . getOpcode ( ) ; if ( UseOpc != <STR_LIT> && UseOpc != <STR_LIT> ) continue ; unsigned CRSubReg = CompareUseMI . getOperand ( <NUM_LIT> ) . getSubReg ( ) ; unsigned TrueReg = CompareUseMI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned FalseReg = CompareUseMI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned RegToCopy = selectReg ( SExtImm , SExtComparand , Opc , TrueReg , FalseReg , CRSubReg ) ; if ( RegToCopy == <STR_LIT> ) continue ; if ( RegToCopy == <STR_LIT> || RegToCopy == <STR_LIT> ) { CompareUseMI . setDesc ( get ( UseOpc == <STR_LIT> ? <STR_LIT> : <STR_LIT> ) ) ; CompareUseMI . getOperand ( <NUM_LIT> ) . ChangeToImmediate ( <NUM_LIT> ) ; CompareUseMI . RemoveOperand ( <NUM_LIT> ) ; CompareUseMI . RemoveOperand ( <NUM_LIT> ) ; continue ; } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( DefMI -> dump ( ) ; MI . dump ( ) ; CompareUseMI . dump ( ) ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; CompareUseMI . setDesc ( get ( <STR_LIT> ) ) ; CompareUseMI . RemoveOperand ( <NUM_LIT> ) ; CompareUseMI . RemoveOperand ( RegToCopy == TrueReg ? <NUM_LIT> : <NUM_LIT> ) ; CmpIselsConverted ++ ; Changed = true ; LLVM_DEBUG ( CompareUseMI . dump ( ) ) ; } if ( Changed ) return true ; MissedConvertibleImmediateInstrs ++ ; return false ; } case <STR_LIT> : case <STR_LIT> : { int64_t Addend = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( isInt < <NUM_LIT> > ( Addend + SExtImm ) ) { ReplaceWithLI = true ; Is64BitLI = Opc == <STR_LIT> ; NewImm = Addend + SExtImm ; break ; } return false ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { int64_t SH = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; int64_t MB = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; APInt InVal ( ( Opc == <STR_LIT> || Opc == <STR_LIT> ) ? <NUM_LIT> : <NUM_LIT> , SExtImm , true ) ; InVal = InVal .


<s> AMDGPUAsmPrinter :: AMDGPUAsmPrinter ( TargetMachine & TM , std :: unique_ptr < MCStreamer > Streamer ) : AsmPrinter ( TM , std :: move ( Streamer ) ) { DisasmEnabled = TM . getSubtarget < AMDGPUSubtarget > ( ) . dumpCode (


<s> <ISA_LIT>SimplifyAddress ( Addr , VT , UseOffset , IndexReg ) ; bool IsVSFRC = ( ResultReg != <NUM_LIT> ) && isVSFRCRegister ( ResultReg ) ; if ( IsVSFRC && ( Opc == <STR_LIT> ) && ( Addr . BaseType != Address :: FrameIndexBase ) && UseOffset && ( Addr . Offset == <NUM_LIT> ) ) { UseOffset = false ; } if ( ResultReg == <NUM_LIT> ) ResultReg = createResultReg ( UseRC ) ; if ( Addr . BaseType == Address :: FrameIndexBase ) { if ( IsVSFRC && Opc == <STR_LIT> ) return false ; MachineMemOperand * MMO = FuncInfo . MF -> getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( Addr . Base . FI , Addr . Offset ) , MachineMemOperand :: MOLoad , MFI . getObjectSize ( Addr . Base . FI ) , MFI . getObjectAlignment ( Addr . Base . FI ) ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , ResultReg ) . addImm ( Addr . Offset ) . addFrameIndex ( Addr . Base . FI ) . addMemOperand ( MMO ) ; } else if ( UseOffset ) { if ( IsVSFRC && Opc == <STR_LIT> ) return false ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , ResultReg ) . addImm ( Addr . Offset ) . addReg ( Addr . Base . Reg ) ; } else { switch ( Opc ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = IsVSFRC ? <STR_LIT> : <STR_LIT> ; break ; } BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , ResultReg ) . addReg ( Addr . Base . Reg ) . addReg ( IndexReg ) ; } return


<s> getUsefulBits ( Op , Mask , Depth + <NUM_LIT> ) ; Mask = Mask . lshr ( ShiftAmt ) ; } else if ( <STR_LIT> ( ShiftTypeAndValue ) == <STR_LIT> ) { uint64_t ShiftAmt = <STR_LIT> ( ShiftTypeAndValue ) ; Mask = Mask . lshr ( ShiftAmt ) ; getUsefulBits ( Op , Mask , Depth + <NUM_LIT> ) ; Mask = Mask . shl ( ShiftAmt ) ; } else


<s> return new GlobalVariable ( M , IRB . getInt32Ty ( ) , false , GlobalValue :: WeakODRLinkage , IRB . getInt32


<s> RegisterTargetMachine < <ISA_LIT>TargetMachine > X


<s> SDValue <ISA_LIT>TargetLowering :: lowerJumpTable ( SDValue Op , SelectionDAG & DAG ) const { auto * N = cast < JumpTableSDNode > ( Op ) ; SDValue GA = DAG . getTargetJumpTable ( N -> getIndex ( ) , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , SDLoc ( N


<s> const uint16_t nopEncoding = hasNOP ( ) ? Thumb2_16bitNopEncoding : Thumb1_16bitNopEncoding ; uint64_t NumNops = Count / <NUM_LIT> ; for ( uint64_t i = <NUM_LIT> ; i != NumNops ; ++ i ) <STR_LIT> :: write ( OS , nopEncoding , Endian ) ; if ( Count & <NUM_LIT> ) OS << '\0' ; return true ; } const uint32_t nopEncoding = hasNOP ( ) ? <ISA_LIT>v6T2_NopEncoding : <ISA_LIT>v4_NopEncoding ; uint64_t NumNops = Count / <NUM_LIT> ; for ( uint64_t i = <NUM_LIT> ; i != NumNops ; ++ i ) <STR_LIT> :: write ( OS , nopEncoding , Endian ) ; switch ( Count % <NUM_LIT> ) { default : break ; case <NUM_LIT> : OS << '\0' ; break ; case <NUM_LIT> : OS . write ( <STR_LIT> , <NUM_LIT> ) ; break ; case <NUM_LIT> : OS . write ( <STR_LIT> , <NUM_LIT> ) ; break ; } return


<s> if ( llvm :: ELF :: R_386_32 == pReloc . type ( ) && helper_use_relative_reloc ( * rsym , * this ) ) { Relocation & reloc = helper_DynRel_init ( rsym , * pReloc . targetRef ( ) . frag ( ) , pReloc . targetRef ( ) . offset ( ) , llvm :: ELF :: R_<ISA_LIT>_64_RELATIVE , * this ) ; getRelRelMap ( ) . record ( pReloc , reloc ) ; } else { Relocation & reloc = helper_DynRel_init ( rsym , * pReloc . targetRef ( ) . frag ( ) , pReloc . targetRef ( ) . offset ( ) , pReloc . type ( ) , * this ) ; getRelRelMap ( ) . record ( pReloc , reloc ) ; } getTarget ( ) . checkAndSetHasTextRel ( * pSection . getLink ( ) ) ; } } return ; case llvm :: ELF :: R_<ISA_LIT>_64_GOTPCREL : if ( rsym -> reserved ( ) & ReserveGOT ) return ; if ( ! getTarget ( ) . symbolFinalValueIsKnown ( * rsym ) ) helper_GOT_init ( pReloc , true , * this ) ; else helper_GOT_init ( pReloc , false , * this ) ; rsym -> setReserved ( rsym -> reserved ( ) | ReserveGOT ) ; return ; case llvm :: ELF :: R_<ISA_LIT>_64_PLT32 : if ( rsym -> reserved ( ) & ReservePLT ) return ; if ( getTarget ( ) . symbolFinalValueIsKnown ( * rsym ) ) return ; if ( rsym -> isDefine ( ) && ! rsym -> isDyn ( ) && ! getTarget ( ) . isSymbolPreemptible ( * rsym ) ) { return ; } helper_PLT_init ( pReloc , * this ) ; rsym -> setReserved ( rsym -> reserved ( ) | ReservePLT ) ; return ; case llvm :: ELF :: R_<ISA_LIT>_64_PC32 : case llvm :: ELF :: R_<ISA_LIT>_64_PC16 : case llvm :: ELF :: R_<ISA_LIT>_64_PC8 : if ( getTarget ( ) . symbolNeedsPLT ( * rsym ) && LinkerConfig ::

DynObj != config ( ) . codeGenType ( ) ) {


<s> case <STR_LIT> : splitMove ( MI , <STR_LIT> ) ; return true ; case <STR_LIT> : splitMove ( MI , <STR_LIT> ) ; return true ; case <STR_LIT> : splitAdjDynAlloc ( MI ) ; return true


<s> SMLoc RegEndLoc2 , LayoutLoc2 ; SMLoc RegLoc2 = Parser . getTok ( ) . getLoc ( ) ; if ( ! TryParseVector ( Reg2 , RegEndLoc2 , LayoutStr2 , LayoutLoc2 ) ) return MatchOperand_ParseFail ; unsigned Space = ( Reg < Reg2 ) ? ( Reg2 - Reg ) : ( Reg2 + <NUM_LIT> - Reg ) ; if ( LayoutStr != LayoutStr2 ) { Error ( LayoutLoc2 , <STR_LIT> ) ; return MatchOperand_ParseFail ; } if ( Space == <NUM_LIT> || Space > <NUM_LIT> ) { Error ( RegLoc2 , <STR_LIT> ) ; return MatchOperand_ParseFail ; } Count += Space ; } else { unsigned LastReg = Reg ; while ( Parser . getTok ( ) . is ( AsmToken :: Comma ) ) { Parser . Lex ( ) ; unsigned Reg2 ; StringRef LayoutStr2 ; SMLoc RegEndLoc2 , LayoutLoc2 ; SMLoc RegLoc2 = Parser . getTok ( ) . getLoc ( ) ; if ( ! TryParseVector ( Reg2 , RegEndLoc2 , LayoutStr2 , LayoutLoc2 ) ) return MatchOperand_ParseFail ; unsigned Space = ( LastReg < Reg2 ) ? ( Reg2 - LastReg ) : ( Reg2 + <NUM_LIT> - LastReg ) ; Count ++ ; if ( Space != <NUM_LIT> ) { Error ( RegLoc2 , <STR_LIT> ) ; return MatchOperand_ParseFail ; } if ( LayoutStr != LayoutStr2 ) { Error ( LayoutLoc2 , <STR_LIT> ) ; return MatchOperand_ParseFail ; } if ( Count > <NUM_LIT> ) { Error ( RegLoc2 , <STR_LIT> ) ; return MatchOperand_ParseFail ; } LastReg =


<s> explicit <ISA_LIT>DAGToDAGISel ( const <ISA_LIT>TargetMachine & targetmachine , CodeGenOpt :: Level OptLevel ) : SelectionDAGISel ( targetmachine , OptLevel ) , Subtarget ( targetmachine . getSubtarget < <ISA_LIT>Subtarget > ( ) ) , TM ( targetmachine ) { initialize<ISA_LIT>DAGToDAGISelPass ( * PassRegistry :: getPassRegistry ( )


<s> int64_t SImmVal = Imm . getSExtValue ( ) ; uint64_t ZImmVal = Imm . getZExtValue ( ) ; if ( ! ST -> isThumb ( ) ) { if ( ( SImmVal >= <NUM_LIT> && SImmVal < <NUM_LIT> ) || ( <STR_LIT> ( ZImmVal ) != - <NUM_LIT> ) || ( <STR_LIT> ( ~ ZImmVal ) != - <NUM_LIT> ) ) return <NUM_LIT> ; return ST -> hasV6T2Ops ( ) ? <NUM_LIT> : <NUM_LIT> ; } if ( ST -> isThumb2 ( ) ) { if ( ( SImmVal >= <NUM_LIT> && SImmVal < <NUM_LIT> ) || ( <STR_LIT> ( ZImmVal ) != - <NUM_LIT> ) || ( <STR_LIT> ( ~ ZImmVal )


<s> auto DL = MF . getDataLayout ( ) ; SmallVector < ArgInfo , <NUM_LIT> > SplitArgs ; unsigned Idx = <NUM_LIT> ; for ( const auto & Arg : F . args ( ) ) { if ( Arg . hasAttribute ( Attribute :: ByVal ) || Arg . hasAttribute ( Attribute :: InReg ) || Arg . hasAttribute ( Attribute :: StructRet ) || Arg . hasAttribute ( Attribute :: SwiftSelf ) || Arg . hasAttribute ( Attribute :: SwiftError ) || Arg . hasAttribute ( Attribute :: Nest ) || VRegs [ Idx ] . size ( ) > <NUM_LIT> ) return false ; ArgInfo OrigArg ( VRegs [ Idx ] , Arg . getType ( ) ) ; setArgFlags ( OrigArg , Idx + AttributeList :: FirstArgIndex , DL , F ) ; splitToValueTypes ( OrigArg , SplitArgs , DL , F . getCallingConv ( ) ) ; Idx ++


<s> static SDValue unpackFromRegLoc ( SelectionDAG & DAG , SDValue Chain , const CCValAssign & VA , const SDLoc & DL , const <ISA_LIT>TargetLowering & TLI ) { MachineFunction & MF = DAG . getMachineFunction ( ) ; MachineRegisterInfo & RegInfo = MF . getRegInfo ( ) ; EVT LocVT = VA . getLocVT ( ) ; SDValue Val ; const TargetRegisterClass * RC = TLI . getRegClassFor (


<s> return isV60VectorInstruction ( MI ) &&


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { if ( MI . getOperand ( <NUM_LIT> + <STR_LIT> ) . isReg ( ) && MI . getOperand ( <NUM_LIT> + <STR_LIT> ) . isImm ( ) && MI . getOperand ( <NUM_LIT> + <STR_LIT> ) . isReg ( ) && MI . getOperand ( <NUM_LIT> + <STR_LIT> ) . getReg ( ) == <NUM_LIT> && MI . isInvariantLoad ( AA ) ) { unsigned BaseReg = MI . getOperand ( <NUM_LIT> + <STR_LIT> ) . getReg ( ) ; if ( BaseReg == <NUM_LIT> || BaseReg == <STR_LIT> ) return true ; if ( ! ReMatPICStubLoad && MI . getOperand ( <NUM_LIT> + <STR_LIT> ) . isGlobal ( ) ) return false ; const MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ; const MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; return regIsPICBase ( BaseReg , MRI ) ; } return false ; } case <STR_LIT> : case <STR_LIT> : { if ( MI . getOperand ( <NUM_LIT> + <STR_LIT> ) . isImm ( ) && MI . getOperand ( <NUM_LIT> + <STR_LIT> ) . isReg ( ) && MI . getOperand ( <NUM_LIT> + <STR_LIT> ) . getReg ( )

== <NUM_LIT> && ! MI . getOperand ( <NUM_LIT> + <STR_LIT> ) . isReg ( ) ) {


<s> bool is64Bit = Subtarget -> is64Bit ( ) ; DebugLoc dl = N . getDebugLoc ( ) ; DEBUG ( { dbgs ( ) <<


<s> MCTargetStreamer * llvm :: create<ISA_LIT>ObjectTargetStreamer ( MCStreamer & S , const MCSubtargetInfo & STI ) { const Triple & TT = STI . getTargetTriple ( ) ; if ( TT . isOSBinFormatELF ( ) ) return new <ISA_LIT>TargetELFStreamer ( S ) ; if ( TT . isOSBinFormatCOFF ( ) ) return new <ISA_LIT>TargetWinCOFFStreamer (


<s> } BitExtMI = BuildMI ( * LoadI -> getParent ( ) , LoadI , LoadI -> getDebugLoc ( ) , TII -> get ( IsStoreXReg ? <STR_LIT> : <STR_LIT> ) , LdRt ) . addReg ( IsStoreXReg ? <STR_LIT> : <STR_LIT> ) . addReg ( StRt ) . addImm ( <STR_LIT> ( <STR_LIT> , <NUM_LIT> ) ) ; } else { if ( ! Subtarget -> isLittleEndian ( ) ) return NextI ; bool IsUnscaled = TII -> isUnscaledLdSt ( * LoadI ) ; assert ( IsUnscaled == TII -> isUnscaledLdSt ( * StoreI ) && <STR_LIT> ) ; assert ( LoadSize <= StoreSize && <STR_LIT> ) ; int UnscaledLdOffset = IsUnscaled ? getLdStOffsetOp ( * LoadI ) . getImm ( ) : getLdStOffsetOp ( * LoadI ) . getImm ( ) * LoadSize ; int UnscaledStOffset = IsUnscaled ? getLdStOffsetOp ( * StoreI ) . getImm ( ) : getLdStOffsetOp ( * StoreI ) . getImm ( ) * StoreSize ; int Width = LoadSize * <NUM_LIT> ; int Immr = <NUM_LIT> * ( UnscaledLdOffset - UnscaledStOffset ) ; int Imms = Immr + Width - <NUM_LIT> ; unsigned DestReg = IsStoreXReg ? TRI -> getMatchingSuperReg ( LdRt , <STR_LIT> , & <STR_LIT> ) : LdRt ; assert ( ( UnscaledLdOffset >= UnscaledStOffset && ( UnscaledLdOffset + LoadSize ) <= UnscaledStOffset + StoreSize )


<s> assert ( ( I . getOpcode ( ) == TargetOpcode :: G_SHL || I . getOpcode ( ) == TargetOpcode :: G_ASHR || I . getOpcode ( ) == TargetOpcode :: G_LSHR ) && <STR_LIT> ) ; unsigned DstReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; const LLT DstTy = MRI . getType ( DstReg ) ; const RegisterBank & DstRB = * RBI . getRegBank ( DstReg , MRI , TRI ) ; const static struct ShiftEntry { unsigned SizeInBits ; unsigned CReg ; unsigned OpLSHR ; unsigned OpASHR ; unsigned OpSHL ; } OpTable [ ] = { { <NUM_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } , { <NUM_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } , { <NUM_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } , { <NUM_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } } ; if ( DstRB . getID ( ) != <STR_LIT> ) return false ; auto ShiftEntryIt = std :: find_if ( std :: begin ( OpTable ) , std :: end ( OpTable ) , [ DstTy ] ( const ShiftEntry & El ) { return El . SizeInBits == DstTy . getSizeInBits ( ) ; } ) ; if ( ShiftEntryIt == std :: end ( OpTable ) ) return false ; unsigned CReg = ShiftEntryIt -> CReg ; unsigned Opcode = <NUM_LIT> ; switch ( I . getOpcode ( ) ) { case TargetOpcode :: G_SHL : Opcode = ShiftEntryIt -> OpSHL ; break ; case TargetOpcode :: G_ASHR : Opcode = ShiftEntryIt -> OpASHR ; break ; case TargetOpcode :: G_LSHR : Opcode = ShiftEntryIt -> OpLSHR ; break ; default : return false


<s> DebugLoc DL = MI . getDebugLoc ( ) ; assert ( MI . getOpcode ( ) == <STR_LIT> && <STR_LIT> ) ; const BasicBlock * LLVM_BB = BB -> getBasicBlock ( ) ; MachineFunction :: iterator I = ++ BB -> getIterator ( ) ; MachineBasicBlock * HeadMBB = BB ; MachineFunction * F = BB -> getParent ( ) ; MachineBasicBlock * TailMBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * IfFalseMBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; F -> insert ( I , IfFalseMBB ) ; F -> insert ( I , TailMBB ) ; TailMBB -> splice ( TailMBB -> begin ( ) , HeadMBB , std :: next ( MachineBasicBlock :: iterator ( MI )


<s> bool hardenSlsBlr ( ) const { return HardenSlsBlr


<s> StringRef getPassName ( ) const override { return


<s> SDValue Op0 = DAG . getNode ( <STR_LIT> , dl , IntValTy , Op . getOperand ( <NUM_LIT> ) ) ; SDValue Op1 = DAG . getNode ( <STR_LIT> , dl , IntValTy , Op . getOperand ( <NUM_LIT> ) ) ; SDValue And0 = DAG . getNode ( <STR_LIT> , dl , IntValTy , Op0

, DAG . getConstant ( Mask - <NUM_LIT> , IntValTy ) ) ;


<s> impl_ptr clone ( ) const { return impl_ptr ( ptr_ ? copier_ ( ptr_ . get ( ) ) : nullptr , ptr_ . get_deleter (


<s> void buildLoad ( unsigned Val , const CCValAssign & VA ) { MachineMemOperand * MMO ; unsigned Addr = getStackAddress ( VA , MMO ) ; MIRBuilder . buildLoad ( Val , Addr ,


<s> MoveBelowOrigChain ( CurDAG , Load , SDValue ( N , <NUM_LIT> ) , Chain ) ; ++ NumLoadMoved ; continue ; } if ( N -> getOpcode ( ) != <STR_LIT> && N -> getOpcode ( ) != <STR_LIT> ) continue ; EVT SrcVT = N -> getOperand ( <NUM_LIT> ) . getValueType ( ) ; EVT DstVT = N -> getValueType ( <NUM_LIT> ) ; if ( SrcVT . isVector ( ) || DstVT . isVector ( ) ) continue ; <ISA_LIT>TargetLowering * <ISA_LIT>Lowering = ( <ISA_LIT>TargetLowering * ) getTargetLowering ( ) ; bool SrcIsSSE = <ISA_LIT>Lowering -> isScalarFPTypeInSSEReg ( SrcVT ) ; bool DstIsSSE = <ISA_LIT>Lowering -> isScalarFPTypeInSSEReg ( DstVT ) ; if ( SrcIsSSE && DstIsSSE ) continue ; if ( ! SrcIsSSE && ! DstIsSSE ) { if ( N -> getOpcode (


<s> rtx symbol ; if ( mem != NULL_RTX && GET_CODE ( mem ) == MEM && GET_CODE ( symbol = XEXP ( mem , <NUM_LIT> ) ) == SYMBOL_REF && SYMBOL_REF_FLAGS ( symbol ) & SYMBOL_FLAG_XSTORMY16_BELOW100 ) { const char * name2 ; int p2align = <NUM_LIT> ; bss100_section ( ) ; while ( align > <NUM_LIT> ) { align /= <NUM_LIT> ; p2align ++ ; } name2 = default_strip_name_encoding ( name ) ; if ( global ) fprintf ( stream , <STR_LIT> , name2 ) ; if ( p2align ) fprintf ( stream , <STR_LIT> , p2align ) ; fprintf ( stream , <STR_LIT> , name2 ) ; fprintf ( stream , <STR_LIT> , name2 , size ) ; fprintf ( stream , <STR_LIT> , name2 , size ) ; return ; } if ( ! global ) { fprintf ( stream , <STR_LIT> ) ; assemble_name ( stream , name ) ; fprintf ( stream , <STR_LIT>


<s> } getParser ( ) . eatToEndOfStatement ( ) ; Operands . push_back ( <STR_LIT> ( getLexer ( ) . getTok ( ) . getString ( ) , getLexer ( ) . getLoc ( ) ) ) ; getLexer ( ) . Lex ( ) ; if ( ParseOperand ( Operands ) ) return true ; Operands . push_back ( std :: move ( CntOp ) ) ; if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) { SMLoc Loc = getLexer ( ) . getLoc ( ) ; getParser ( ) . eatToEndOfStatement ( ) ; return Error ( Loc , <STR_LIT>


<s> DEBUG ( dbgs ( ) << <STR_LIT> << PrintMB ( B ) << <STR_LIT> ) ; MachineBasicBlock :: iterator I , NextI , NonPHI = B -> getFirstNonPHI ( ) ; for ( I = B -> begin ( ) ; I != NonPHI ; I = NextI ) { NextI = std :: next ( I ) ; MachineInstr * PN = & * I ; assert ( PN -> getNumOperands ( ) == <NUM_LIT> && <STR_LIT>


<s> O << <STR_LIT> << getRegisterName ( MI -> getOperand ( OpNum ) . getReg


<s> assert ( HST -> getVectorLength ( ) * <NUM_LIT> == ResTy . getSizeInBits ( ) ) ; SDValue C = CurDAG -> getTargetConstant ( - <NUM_LIT> , dl , <STR_LIT> ) ; SDNode * R = CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , C ) ; SDNode * T = CurDAG -> getMachineNode ( <STR_LIT> , dl , ResTy , N -> getOperand ( <NUM_LIT> ) , SDValue


<s> bool mergeStoresAfterLegalization ( EVT


<s> void printUImm12Offset ( const MCInst * MI , unsigned OpNum , const MCSubtargetInfo &


<s> temp = opint [ <NUM_LIT> ] & <NUM_LIT> ; temp |= ( opint [ <NUM_LIT> ] & <NUM_LIT> ) << <NUM_LIT> ; temp |= ( opint [ <NUM_LIT> ] &


<s> assert ( ! MO . getSubReg ( ) && <STR_LIT> ) ; MCOp = MCOperand :: CreateReg ( MO . getReg ( ) ) ; break ; case MachineOperand :: MO_Immediate : MCOp = MCOperand :: CreateImm ( MO . getImm ( ) ) ; break ; case MachineOperand :: MO_MachineBasicBlock : MCOp = MCOperand :: CreateExpr ( MCSymbolRefExpr :: Create ( MO . getMBB ( ) -> getSymbol ( ) , AP . OutContext ) ) ; break ; case MachineOperand :: MO_GlobalAddress : case MachineOperand :: MO_ExternalSymbol : MCOp = GetSymbolRef ( MO , GetSymbolFromOperand ( MO , AP ) , AP , isDarwin ) ; break ; case MachineOperand :: MO_JumpTableIndex : MCOp = GetSymbolRef ( MO , AP . GetJTISymbol ( MO . getIndex ( ) ) , AP , isDarwin ) ; break ; case MachineOperand :: MO_ConstantPoolIndex : MCOp = GetSymbolRef ( MO , AP . GetCPISymbol ( MO . getIndex ( ) ) , AP ,


<s> assert ( ( <STR_LIT> == N -> getOpcode ( ) || <STR_LIT> == N -> getOpcode ( ) || <STR_LIT> == N -> getOpcode ( ) ) && <STR_LIT> ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; SDValue N0 = N -> getOperand ( <NUM_LIT> ) ; SDValue N1 = N -> getOperand ( <NUM_LIT> ) ; if ( <STR_LIT> ( N0 . getNode ( ) ) ) return DAG . getConstant ( <NUM_LIT> , SDLoc ( N ) , VT ) ; APInt UndefElts ; SmallVector < APInt , <NUM_LIT> > EltBits ; if ( getTargetConstantBitsFromNode ( N1 , <NUM_LIT> , UndefElts , EltBits , true , false ) ) { unsigned <ISA_LIT>Opc = getTargetVShiftUniformOpcode ( N -> getOpcode ( ) , false ) ; return getTargetVShiftByConstNode ( <ISA_LIT>Opc , SDLoc ( N ) , VT . getSimpleVT ( ) , N0 , EltBits [ <NUM_LIT> ] . getZExtValue ( ) , DAG ) ; } const TargetLowering & TLI = DAG .


<s> break ; case <STR_LIT> : Op = emitIntrinsicWithGlue ( DAG , C . Op0 , C . Opcode ) ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } return SDValue ( Op . getNode ( ) , Op -> getNumValues ( ) - <NUM_LIT> ) ; } if ( C . Opcode == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , C . Op0 , C . Op1 , DAG . getConstant ( C . ICmpType , DL , <STR_LIT> ) ) ; if ( C . Opcode == <STR_LIT> ) { bool RegisterOnly = ( bool ( C . CCMask & <STR_LIT> )


<s> } case <STR_LIT> : if ( MI . getOpcode ( ) == <STR_LIT> ) { emitLEApcrelJTInstruction ( MI ) ; break ; } llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : emitPseudoInstruction ( MI ) ; break ; case <STR_LIT> : case <STR_LIT> : emitDataProcessingInstruction ( MI ) ; break ; case <STR_LIT> : case <STR_LIT> : emitLoadStoreInstruction ( MI ) ; break ; case <STR_LIT> : case <STR_LIT> : emitMiscLoadStoreInstruction ( MI ) ; break ; case <STR_LIT> : emitLoadStoreMultipleInstruction ( MI ) ; break ; case <STR_LIT> : emitMulFrmInstruction ( MI ) ; break ; case <STR_LIT> : emitExtendInstruction ( MI ) ; break ; case <STR_LIT> : emitMiscArithInstruction ( MI ) ; break ; case <STR_LIT> : emitSaturateInstruction ( MI ) ; break ; case <STR_LIT> : emitBranchInstruction ( MI ) ; break ; case <STR_LIT> : emitMiscBranchInstruction ( MI ) ; break ; case <STR_LIT> : case <STR_LIT> : emitVFPArithInstruction ( MI ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : emitVFPConversionInstruction ( MI ) ; break ; case <STR_LIT>


<s> if ( isSampler ( * TexHandle ) ) { replaceWith ( & I , ConstantInt :: getTrue ( I . getContext ( ) ) ) ; return true ; } else if ( isImage ( * TexHandle ) ) { replaceWith ( & I , ConstantInt :: getFalse ( I . getContext ( ) ) ) ; return true ; }


<s> EmitAlignment ( <NUM_LIT> ) ; const MCSymbol * Stub = Stubs [ i ] . first ; const MCSymbol * RawSym = Stubs [ i ] . second ; const MCSymbol * LazyPtr = GetLazyPtr ( Stub , OutContext ) ; const MCSymbol * AnonSymbol = GetAnonSym ( Stub , OutContext ) ; O << * Stub << <STR_LIT> ; O << <STR_LIT> << * RawSym << '\n' ; O << <STR_LIT> ; O << <STR_LIT> << * AnonSymbol << '\n' ; O << * AnonSymbol << <STR_LIT> ; O << <STR_LIT> ; O << <STR_LIT> << * LazyPtr << '-' << * AnonSymbol << <STR_LIT> ; O << <STR_LIT> ; O << ( is<ISA_LIT>64 ? <STR_LIT> : <STR_LIT> ) << <STR_LIT> << * LazyPtr << '-' << * AnonSymbol << <STR_LIT> ; O << <STR_LIT> ; O << <STR_LIT> ; OutStreamer . SwitchSection ( LSPSection ) ; O << * LazyPtr << <STR_LIT> ; O << <STR_LIT> << * RawSym << '\n' ; O << ( is<ISA_LIT>64 ? <STR_LIT> : <STR_LIT> ) << <STR_LIT> ; } O << '\n' ; return ; } const MCSection * StubSection = TLOFMacho . getMachOSection ( <STR_LIT> , <STR_LIT> , MCSectionMachO :: S_SYMBOL_STUBS | MCSectionMachO :: S_ATTR_PURE_INSTRUCTIONS , <NUM_LIT> , SectionKind :: getText ( ) ) ; for ( unsigned i = <NUM_LIT> , e = Stubs . size ( ) ; i != e ; ++ i ) { const MCSymbol * Stub = Stubs [ i ] . first ; const MCSymbol * RawSym = Stubs [ i ] . second ; const MCSymbol * LazyPtr = GetLazyPtr ( Stub , OutContext ) ; OutStreamer . SwitchSection ( StubSection ) ; EmitAlignment ( <NUM_LIT> ) ; O << * Stub << <STR_LIT> ; O << <STR_LIT> << * RawSym << '\n' ; O << <STR_LIT> << * LazyPtr


<s> DebugLoc DL = MI . getDebugLoc ( ) ; unsigned GPR3 = Is64Bit ? <STR_LIT> : <STR_LIT> ; unsigned Opc1 , Opc2 ; const unsigned OrigRegs [ ] = { OutReg , InReg , GPR3 } ; switch ( MI . getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : Opc1 = <STR_LIT> ; Opc2 = <STR_LIT> ; break ; case <STR_LIT> : Opc1 = <STR_LIT> ; Opc2 = <STR_LIT> ; break ; case <STR_LIT> : Opc1 = <STR_LIT> ; Opc2 = <STR_LIT> ; break ; case <STR_LIT> : Opc1 = <STR_LIT> ; Opc2 = <STR_LIT> ; break ; } BuildMI ( MBB , I , DL , TII -> get ( <STR_LIT> ) ) . addImm ( <NUM_LIT> ) ; MachineInstr * Addi = BuildMI ( MBB , I , DL , TII -> get ( Opc1 ) , GPR3 ) . addReg ( InReg ) ; Addi -> addOperand ( MI . getOperand ( <NUM_LIT> ) ) ; MachineBasicBlock :: iterator First = I ; -- First ; MachineInstr * Call = ( BuildMI ( MBB , I , DL , TII -> get ( Opc2 )


<s> MVT ElemTy = VecTy . getVectorElementType ( ) ; unsigned ElemWidth = ElemTy . getSizeInBits ( ) ; assert ( isPowerOf2_32 ( ElemWidth ) ) ; auto getIdx = [ ] ( unsigned Code ) { static const unsigned Idx [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> } ; for ( unsigned I = <NUM_LIT> , E = array_lengthof ( Idx ) ; I != E ; ++ I ) if ( Code == Idx [ I ] ) return I ; llvm_unreachable ( <STR_LIT> ) ; } ; static unsigned OpcTable [ <NUM_LIT> ] [ <NUM_LIT> ] = { { <STR_LIT> , <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> } } ; unsigned CmpOpc = OpcTable [ Log2_32 ( ElemWidth ) - <NUM_LIT>


<s> bool <ISA_LIT>PacketizerList :: shouldAddToPacket ( const MachineInstr & MI ) { return ! producesStall (


<s> for ( MachineInstr * MI : MIs ) { CounterPropagateAddr ( * MI , Addr


<s> emit_insn ( gen_rtx_SET ( new_base , gen_rtx_PLUS ( Pmode , base , new_base ) ) ) ; return new_base


<s> const TargetRegisterClass * RC = & <STR_LIT> ; if ( ! RBI . constrainGenericRegister ( DstReg , * RC , MRI ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << TII . getName ( I . getOpcode ( ) ) << <STR_LIT> ) ; return false ; } return true


<s> machine_mode mips_hard_regno_caller_save_mode ( unsigned int regno , unsigned int nregs , machine_mode mode ) { if ( mode == VOIDmode ) return choose_hard_reg_mode ( regno , nregs , NULL ) ; else return


<s> return ( __m128 ) __builtin_ia32_movsldup ( ( __v4sf


<s> MachineInstr * <ISA_LIT>FrameLowering :: buildCFIForRegToRegSpill ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI , const DebugLoc & DL , const

Register Reg , const Register RegCopy ) const {


<s> errs ( ) << <STR_LIT> << RegVT . getSimpleVT ( ) . SimpleTy << <STR_LIT> ; llvm_unreachable ( <NUM_LIT> ) ; } case <STR_LIT> : unsigned VReg = RegInfo . createVirtualRegister ( <STR_LIT> ) ; RegInfo . addLiveIn ( VA . getLocReg ( ) , VReg ) ; SDValue ArgValue = DAG . getCopyFromReg ( Chain , dl , VReg , RegVT ) ; if ( VA . getLocInfo ( ) == CCValAssign :: SExt ) ArgValue = DAG . getNode ( <STR_LIT> , dl , RegVT , ArgValue , DAG . getValueType ( VA . getValVT ( ) ) ) ; else if ( VA . getLocInfo ( ) == CCValAssign :: ZExt ) ArgValue = DAG . getNode ( <STR_LIT> , dl , RegVT , ArgValue , DAG . getValueType ( VA . getValVT ( ) ) ) ; if ( VA . getLocInfo ( ) != CCValAssign :: Full ) ArgValue = DAG . getNode ( <STR_LIT> , dl , VA . getValVT ( ) , ArgValue ) ; InVals . push_back ( ArgValue ) ; } } else { assert ( VA . isMemLoc ( ) ) ; unsigned ObjSize = VA . getLocVT ( ) . getSizeInBits ( ) / <NUM_LIT> ; if ( ObjSize > <NUM_LIT> ) { errs ( ) << <STR_LIT> << EVT ( VA . getLocVT ( ) ) . getEVTString ( ) << <STR_LIT> ; } int FI = MFI -> CreateFixedObject ( ObjSize , VA . getLocMemOffset


<s> if ( Result == MCDisassembler :: Fail ) return MCDisassembler :: Fail ; Result = decodeInstruction ( DecoderTable<ISA_LIT>32 , Instr , Insn , Address , this , STI ) ; if ( Result != MCDisassembler :: Fail ) { PostOperandDecodeAdjust ( Instr ,


<s> case ENCODING_IB : case ENCODING_IW : case ENCODING_ID : case ENCODING_IO : case ENCODING_Iv : case ENCODING_Ia : translateImmediate ( mcInst , insn . immediates [ insn . numImmediatesTranslated ++ ] , operand , insn ) ; return false ; case ENCODING_RB : case ENCODING_RW : case ENCODING_RD : case ENCODING_RO : translateRegister ( mcInst , insn . opcodeRegister ) ; return false ; case ENCODING_I : return translateFPRegister ( mcInst , insn . opcodeModifier ) ; case ENCODING_Rv


<s> bool <ISA_LIT>LegalizerInfo :: legalizeCTPOP ( MachineInstr & MI , MachineRegisterInfo & MRI , LegalizerHelper & Helper ) const { if ( ! ST -> hasNEON ( ) || MI . getMF ( ) -> getFunction ( ) . hasFnAttribute ( Attribute :: NoImplicitFloat ) ) return false ; MachineIRBuilder & MIRBuilder = Helper . MIRBuilder ; Register Dst = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register Val = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; LLT Ty = MRI . getType ( Val ) ; assert ( ! Ty . isVector ( ) && <STR_LIT> ) ; assert ( Ty == MRI . getType ( Dst ) && <STR_LIT> ) ; unsigned Size = Ty . getSizeInBits ( ) ; assert ( ( Size == <NUM_LIT> || Size == <NUM_LIT> ) && <STR_LIT> ) ; if ( Size == <NUM_LIT> ) Val = MIRBuilder . buildZExt ( LLT :: scalar ( <NUM_LIT> ) , Val ) . getReg ( <NUM_LIT> ) ; const LLT V8S8 = LLT :: vector ( <NUM_LIT> , LLT :: scalar ( <NUM_LIT> ) ) ; Val = MIRBuilder . buildBitcast ( V8S8 , Val ) . getReg ( <NUM_LIT> ) ; auto CTPOP = MIRBuilder . buildCTPOP ( V8S8 , Val ) ; auto UADDLV = MIRBuilder . buildIntrinsic ( <STR_LIT> , { LLT :: scalar ( <NUM_LIT> ) } , false ) . addUse ( CTPOP . getReg ( <NUM_LIT> ) ) ; if ( Size == <NUM_LIT> ) MIRBuilder . buildZExt


<s> <ISA_LIT>Subtarget :: <ISA_LIT>Subtarget ( const std :: string & TT , const std :: string & CPU , const std :: string & FS ) : <ISA_LIT>GenSubtargetInfo ( TT , CPU , FS ) , StackAlignment ( <NUM_LIT> ) , ProcDirective ( <STR_LIT> ) , UseLargeMem ( false ) { std :: string default_cpu ( <STR_LIT> ) ; ParseSubtargetFeatures ( default_cpu ,


<s> void addImmOperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT> ) ; addExpr ( Inst , getImm


<s> static DecodeStatus DecodeGPRCRegisterClass ( MCInst & Inst , uint64_t RegNo , uint64_t


<s> const TargetFrameLowering * getFrameLowering ( ) const


<s> assert ( ( Modifier == <NUM_LIT> || Modifier [ <NUM_LIT> ] == <NUM_LIT> ) && <STR_LIT> ) ; const MCOperand & Op = MI -> getOperand ( OpNo ) ; if ( Op .


<s> MIB . addImm ( MI . getOperand ( OpIdx ) . getImm ( ) & <STR_LIT>


<s> int64_t MinOffset = std :: min ( Op1 . getOffset ( ) , Op2 . getOffset ( ) ) ; int64_t Overlapa = Op1 . getSize ( ) + Op1 . getOffset ( ) - MinOffset ; int64_t Overlapb = Op2 . getSize ( ) + Op2 . getOffset ( ) - MinOffset ; return ! AA -> isNoAlias ( MemoryLocation ( Op1 . getValue ( ) , Overlapa , Op1 . getAAInfo ( ) ) , MemoryLocation ( Op2 .

getValue ( ) , Overlapb , Op2 . getAAInfo ( ) ) ) ;


<s> void <ISA_LIT>BitcodeWriter :: pushValueSigned ( const Value * V , unsigned InstID , SmallVectorImpl <


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT>


<s> static MCAsmInfo * create<ISA_LIT>MCAsmInfo ( const MCRegisterInfo & MRI , const Triple & TheTriple ) { bool is<ISA_LIT>64 = ( TheTriple . getArch ( ) == Triple :: ppc64 || TheTriple . getArch ( ) == Triple :: ppc64le ) ; MCAsmInfo * MAI ; if ( TheTriple . isOSDarwin ( ) ) MAI = new <ISA_LIT>MCAsmInfoDarwin ( is<ISA_LIT>64 , TheTriple ) ; else if ( TheTriple . isOSBinFormatXCOFF ( ) ) MAI = new <ISA_LIT>XCOFFMCAsmInfo ( is<ISA_LIT>64 , TheTriple ) ; else MAI = new <ISA_LIT>ELFMCAsmInfo ( is<ISA_LIT>64 , TheTriple ) ; unsigned Reg = is<ISA_LIT>64 ? <STR_LIT> : <STR_LIT> ; MCCFIInstruction Inst = MCCFIInstruction :: createDefCfa ( nullptr , MRI . getDwarfRegNum ( Reg , true ) , <NUM_LIT> ) ; MAI -> addInitialFrameState ( Inst ) ; return MAI


<s> if ( StackSize ) { MachineLocation SPDst ( MachineLocation :: VirtualFP ) ; MachineLocation SPSrc ( MachineLocation :: VirtualFP , <NUM_LIT> * stackGrowth ) ; Moves . push_back ( MachineMove ( FrameLabelId , SPDst , SPSrc ) ) ; } else { MachineLocation SPDst ( StackPtr ) ; MachineLocation SPSrc ( StackPtr , stackGrowth ) ; Moves . push_back ( MachineMove ( FrameLabelId , SPDst , SPSrc ) ) ; } MachineLocation FPDst ( MachineLocation :: VirtualFP , <NUM_LIT> * stackGrowth ) ; MachineLocation FPSrc ( FramePtr ) ; Moves . push_back ( MachineMove ( FrameLabelId , FPDst , FPSrc ) ) ; } BuildMI ( MBB , MBBI , DL , TII . get ( Is64Bit ? <STR_LIT> : <STR_LIT> ) , FramePtr ) . addReg ( StackPtr ) ; if ( needsFrameMoves ) { unsigned FrameLabelId = MMI -> NextLabelID ( ) ; BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) ) . addImm ( FrameLabelId ) ; MachineLocation FPDst ( FramePtr ) ; MachineLocation FPSrc ( MachineLocation :: VirtualFP ) ; Moves . push_back ( MachineMove ( FrameLabelId , FPDst , FPSrc ) ) ; } for ( MachineFunction :: iterator I = llvm :: next ( MF . begin ( ) ) , E = MF . end ( ) ; I != E ; ++ I ) I -> addLiveIn ( FramePtr ) ; if ( needsStackRealignment ( MF ) ) { MachineInstr * MI = BuildMI ( MBB , MBBI , DL , TII . get ( Is64Bit ? <STR_LIT> : <STR_LIT> ) , StackPtr ) . addReg ( StackPtr ) . addImm ( - MaxAlign ) ; MI -> getOperand ( <NUM_LIT> ) . setIsDead ( ) ; } } else { NumBytes = StackSize - <ISA_LIT>FI -> getCalleeSavedFrameSize ( ) ; } bool PushedRegs = false ; int StackOffset = <NUM_LIT> * stackGrowth ; while ( MBBI != MBB . end ( ) && ( MBBI -> getOpcode ( ) == <STR_LIT> || MBBI -> getOpcode ( ) == <STR_LIT> ) ) { PushedRegs = true ; ++ MBBI ; if ( ! HasFP && needsFrameMoves ) { unsigned LabelId = MMI -> NextLabelID ( ) ; BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) ) . addImm ( LabelId ) ; unsigned Ptr = StackSize ? MachineLocation :: VirtualFP : StackPtr ; MachineLocation SPDst ( Ptr ) ; MachineLocation SPSrc ( Ptr , StackOffset ) ; Moves . push_back ( MachineMove ( LabelId , SPDst , SPSrc ) ) ; StackOffset += stackGrowth ; } } DL = MBB . findDebugLoc ( MBBI ) ; if ( NumBytes >= <NUM_LIT> && Subtarget -> isTargetCygMing ( ) ) { bool isEAXAlive = false ; for ( MachineRegisterInfo :: livein_iterator II = MF . getRegInfo ( ) . livein_begin ( ) , EE = MF . getRegInfo ( ) . livein_end ( ) ; ( II != EE ) && ! isEAXAlive ; ++ II ) { unsigned Reg = II ->


<s> OutStreamer -> SwitchSection ( cast < MCSymbolXCOFF > ( CurrentFnDescSym ) -> getContainingCsect ( ) ) ; OutStreamer -> EmitLabel ( CurrentFnDescSym ) ; OutStreamer -> EmitValue ( MCSymbolRefExpr :: create ( CurrentFnSym , OutContext ) , PointerSize ) ; const MCSymbol * TOCBaseSym = cast < MCSectionXCOFF > ( getObjFileLowering ( ) . getTOCBaseSection ( ) ) -> getQualNameSymbol ( ) ; OutStreamer -> EmitValue ( MCSymbolRefExpr :: create ( TOCBaseSym , OutContext ) , PointerSize ) ; OutStreamer -> EmitIntValue ( <NUM_LIT>


<s> int64_t LoOffset = OffsetOp . getImm ( ) & <NUM_LIT> ; int64_t HiOffset = OffsetOp . getImm ( ) & ~ <NUM_LIT> ; if ( LoOffset & <NUM_LIT> ) HiOffset += <NUM_LIT> ; bool IsLargeOffset = HiOffset != <NUM_LIT> ; if ( IsLargeOffset ) { bool Is32BitImm = ( HiOffset >> <NUM_LIT> ) == <NUM_LIT> ; if ( loadImmediate ( HiOffset , TmpReg , <STR_LIT> , Is32BitImm , true , IDLoc , Out , STI ) ) return ; } if ( BaseReg != <STR_LIT> && BaseReg != <STR_LIT> ) TOut . emitRRR ( isGP64bit ( ) ? <STR_LIT> : <STR_LIT> , TmpReg , TmpReg , BaseReg , IDLoc , STI ) ; TOut . emitRRI ( Inst . getOpcode ( ) , DstReg , TmpReg , LoOffset , IDLoc , STI ) ; } else { assert ( OffsetOp . isExpr ( ) && <STR_LIT> ) ; const MCExpr * ExprOffset = OffsetOp . getExpr ( ) ; MCOperand LoOperand = MCOperand :: createExpr ( <ISA_LIT>MCExpr :: create ( <ISA_LIT>MCExpr :: MEK_LO , ExprOffset , getContext ( ) ) ) ; MCOperand HiOperand = MCOperand :: createExpr ( <ISA_LIT>MCExpr :: create ( <ISA_LIT>MCExpr :: MEK_HI , ExprOffset , getContext ( ) ) ) ; if ( IsLoad ) TOut . emitLoadWithSymOffset ( Inst . getOpcode ( ) , DstReg , BaseReg , HiOperand , LoOperand , TmpReg , IDLoc , STI ) ; else TOut . emitStoreWithSymOffset ( Inst . getOpcode ( ) , DstReg , BaseReg , HiOperand , LoOperand , TmpReg ,


<s> if ( GET_CODE ( op ) == PLUS && address ( XEXP ( op , <NUM_LIT> ) ) ) return true ; if ( GET_CODE ( op ) == SYMBOL_REF ) return true ; if ( GET_CODE ( op ) == LABEL_REF ) return


<s> if ( PredMBBInfo -> Modified ) fixupModifiedCond ( PredMBB ) ; CC = PredMBBInfo -> BranchCode ; if ( ! ( CC == <STR_LIT> && BranchPath . size ( ) == <NUM_LIT> ) ) replaceBrDest ( PredMBB , & MBB , MBBInfo -> FBB ) ; MachineBasicBlock * RootMBB = BranchPath . back ( ) ; TargetMBBInfo * RootMBBInfo = getMBBInfo ( RootMBB ) ; assert ( RootMBBInfo && <STR_LIT> ) ; if ( RootMBBInfo -> Modified ) fixupModifiedCond ( RootMBB ) ; CC = RootMBBInfo -> BranchCode ; if ( CC != <STR_LIT> ) { MachineBasicBlock :: iterator UncondBrI = findUncondBrI ( RootMBB ) ; <STR_LIT> NewCC ; switch ( CC ) { case <STR_LIT> : NewCC = <STR_LIT> ; break ; case <STR_LIT> : NewCC = <STR_LIT> ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } BuildMI ( * RootMBB , UncondBrI , RootMBB -> findDebugLoc ( UncondBrI ) , TII -> get ( <STR_LIT> ) ) . addMBB ( RootMBBInfo -> FBB ) . addImm ( NewCC ) ; BuildMI ( * RootMBB , UncondBrI , RootMBB -> findDebugLoc ( UncondBrI ) , TII

-> get ( <STR_LIT> ) ) . addMBB ( TargetMBB ) ;


<s> int regno ; for ( regno = <NUM_LIT> ; regno < FIRST_PSEUDO_REGISTER ; regno ++ ) if ( GENERAL_REGNO_P ( regno ) && ix86_save_reg ( regno , true , true ) ) nregs ++ ; return nregs


<s> static const char * reg_name_with_mode ( int regno , machine_mode mode ) { int mlen = GET_MODE_SIZE ( mode ) ; if ( regno == R0_REGNO && mlen == <NUM_LIT> ) return <STR_LIT> ; if ( regno == R0_REGNO && ( mlen == <NUM_LIT> || mlen == <NUM_LIT> ) ) return <STR_LIT> ; if ( regno == R0_REGNO && mlen == <NUM_LIT> ) return <STR_LIT> ; if ( regno == R0_REGNO && mlen == <NUM_LIT>


<s> adjustLiveRegs ( Bundle . Mask , Term ) ; if ( ! Bundle . Mask ) { DEBUG ( dbgs ( ) << <STR_LIT> ) ; return ; } DEBUG ( dbgs ( ) << <STR_LIT> << BundleIdx << <STR_LIT> ) ; if ( Bundle . isFixed ( ) ) { DEBUG ( dbgs ( ) << <STR_LIT> ) ; shuffleStackTop ( Bundle . FixStack , Bundle . FixCount , Term ) ; } else { DEBUG ( dbgs ( )


<s> static rtx_insn * avr_md_asm_adjust ( vec < rtx > & , vec < rtx > & , vec < machine_mode > & , vec < const char * > & , vec < rtx > & clobbers , HARD_REG_SET & clobbered_regs , location_t ) { clobbers . safe_push ( cc_reg_rtx


<s> if ( ! mayTailCallThisCC ( CalleeCC ) ) return false ; MachineFunction & MF = DAG . getMachineFunction ( ) ; const Function & CallerF = MF . getFunction ( ) ; CallingConv :: ID CallerCC = CallerF . getCallingConv ( ) ; const <ISA_LIT>RegisterInfo * TRI = getSubtarget ( ) -> getRegisterInfo ( ) ; const uint32_t * CallerPreserved = TRI -> getCallPreservedMask ( MF , CallerCC ) ; if ( ! CallerPreserved ) return false ; bool CCMatch = CallerCC == CalleeCC ; if ( DAG . getTarget ( ) . Options . GuaranteedTailCallOpt ) { if ( canGuaranteeTCO ( CalleeCC ) && CCMatch ) return true ; return false ; } if ( IsVarArg ) return false ; for ( const Argument & Arg : CallerF . args ( ) ) { if ( Arg . hasByValAttr ( ) ) return false ; } LLVMContext & Ctx = * DAG


<s> TII = static_cast < const <ISA_LIT>InstrInfo * > ( MF . getSubtarget ( ) . getInstrInfo ( ) ) ; bool Modified = false ; for ( auto & MBB : MF ) Modified |= selectMBB ( MBB ) ; return Modified


<s> virtual const <ISA_LIT>RegisterInfo & getRegisterInfo ( ) const { return RI


<s> HasFRSQRTE = false ; HasFRSQRTES = false ; HasRecipPrec = false ; HasSTFIWX = false ; HasLFIWAX = false ; HasFPRND = false ; HasFPCVT = false ; HasISEL = false ; HasPOPCNTD = false ; HasBPERMD = false ; HasExtDiv = false ; HasCMPB = false ; HasLDBRX = false ; IsBookE = false ; HasOnlyMSYNC = false ; Is<ISA_LIT>4xx = false ; Is<ISA_LIT>6xx = false ; IsE500 = false ; FeatureMFTB = false ; DeprecatedDST =


<s> computeRegisterProperties ( STI . getRegisterInfo ( ) ) ; setLibcallName ( RTLIB :: MEMSET , <STR_LIT> ) ; setLibcallName ( RTLIB :: UDIVREM_I8 , <STR_LIT> ) ; setLibcallName ( RTLIB :: UDIVREM_I16 , <STR_LIT> ) ; setLibcallName ( RTLIB :: UDIVREM_I32 , <STR_LIT> ) ; setLibcallName ( RTLIB :: UDIVREM_I64 , <STR_LIT> ) ; setLibcallName ( RTLIB :: SDIVREM_I8 , <STR_LIT> ) ; setLibcallName ( RTLIB :: SDIVREM_I16 , <STR_LIT> ) ; setLibcallName ( RTLIB :: SDIVREM_I32 , <STR_LIT> ) ; setLibcallName ( RTLIB ::


<s> U = I ; } } else if ( const ConstantExpr * C = dyn_cast < ConstantExpr > ( Obj ) ) { Opcode = C -> getOpcode ( ) ; U = C ; } if ( auto * Ty = dyn_cast < PointerType > ( Obj -> getType ( ) ) ) if ( Ty -> getAddressSpace ( ) > <NUM_LIT> ) return false ; if ( const GlobalValue * GV = dyn_cast < GlobalValue > ( Obj ) ) { if ( Addr . getGlobalValue ( ) ) return false ; Addr . setGlobalValue ( GV ) ; return true ; } switch ( Opcode ) { default : break ; case Instruction :: BitCast : { return computeAddress ( U -> getOperand ( <NUM_LIT> ) , Addr ) ; } case Instruction :: IntToPtr : { if ( TLI . getValueType ( DL , U -> getOperand ( <NUM_LIT> ) -> getType ( ) ) == TLI . getPointerTy ( DL ) ) return computeAddress ( U -> getOperand ( <NUM_LIT> ) , Addr ) ; break ; } case Instruction :: PtrToInt : { if ( TLI . getValueType ( DL , U -> getType ( ) ) == TLI . getPointerTy ( DL ) ) return computeAddress ( U -> getOperand ( <NUM_LIT> ) , Addr ) ; break ; } case Instruction :: GetElementPtr : { Address SavedAddr = Addr ; uint64_t TmpOffset = Addr . getOffset ( ) ; for ( gep_type_iterator GTI = gep_type_begin ( U ) , E = gep_type_end ( U ) ; GTI != E ; ++ GTI ) { const Value * Op = GTI . getOperand ( ) ; if ( StructType * STy = dyn_cast < StructType > ( * GTI ) ) { const StructLayout * SL = DL . getStructLayout ( STy ) ; unsigned Idx = cast < ConstantInt > ( Op ) -> getZExtValue ( ) ; TmpOffset += SL -> getElementOffset ( Idx ) ; } else { uint64_t S = DL . getTypeAllocSize ( GTI . getIndexedType ( ) ) ; for ( ; ; ) { if ( const ConstantInt * CI = dyn_cast < ConstantInt > ( Op ) ) { TmpOffset += CI -> getSExtValue ( ) * S ; break ; } if ( S == <NUM_LIT> && Addr . isRegBase ( ) && Addr . getReg ( ) == <NUM_LIT> ) { Addr . setReg ( getRegForValue ( Op ) ) ; break ; } if ( canFoldAddIntoGEP ( U , Op ) ) { ConstantInt * CI = cast < ConstantInt > ( cast < AddOperator > ( Op ) -> getOperand ( <NUM_LIT> ) ) ; TmpOffset += CI -> getSExtValue ( ) * S ; Op = cast < AddOperator > ( Op )


<s> AttributeSet AF = MF . getFunction ( ) -> getAttributes (


<s> bool <ISA_LIT>TargetLowering :: CanLowerReturn ( CallingConv :: ID CallConv , MachineFunction & MF , bool isVarArg , const SmallVectorImpl < <STR_LIT> > & Outs , LLVMContext & Context ) const { SmallVector < CCValAssign , <NUM_LIT> >