<s> set_optab_libfunc ( smul_optab , mode , <STR_LIT> ) ; set_optab_libfunc ( sdiv_optab , mode , <STR_LIT> ) ; if ( ! TARGET_HARD_FLOAT ) { set_optab_libfunc ( neg_optab , mode , <STR_LIT> ) ; set_optab_libfunc ( eq_optab , mode , <STR_LIT> ) ; set_optab_libfunc ( ne_optab , mode , <STR_LIT> ) ; set_optab_libfunc ( gt_optab , mode , <STR_LIT> ) ; set_optab_libfunc ( ge_optab , mode , <STR_LIT> ) ; set_optab_libfunc ( lt_optab , mode , <STR_LIT> ) ; set_optab_libfunc ( le_optab , mode , <STR_LIT> ) ; set_optab_libfunc ( unord_optab , mode , <STR_LIT> ) ; set_conv_libfunc ( sext_optab , mode , SFmode , <STR_LIT> ) ; set_conv_libfunc ( sext_optab , mode , DFmode , <STR_LIT> ) ; set_conv_libfunc ( trunc_optab , SFmode , mode , <STR_LIT> ) ; set_conv_libfunc ( trunc_optab , DFmode , mode , <STR_LIT> ) ; set_conv_libfunc ( sfix_optab , SImode , mode , <STR_LIT> ) ; set_conv_libfunc ( ufix_optab , SImode , mode , <STR_LIT> ) ; set_conv_libfunc ( sfloat_optab , mode , SImode , <STR_LIT> ) ; set_conv_libfunc ( ufloat_optab , mode , SImode , <STR_LIT> ) ; } } else { set_optab_libfunc ( add_optab , mode , <STR_LIT> ) ; set_optab_libfunc ( sub_optab , mode , <STR_LIT> ) ; set_optab_libfunc ( smul_optab ,


<s> void setLanes ( unsigned l ) { Lanes = l


<s> MachineInstr * MI = & * I ; InsDefs . clear ( ) ; getInstrDefs ( MI , InsDefs ) ; bool Skip = MI -> isCopy ( ) || MI -> isRegSequence ( ) ; if ( ! Skip ) { for ( unsigned VR = InsDefs . find_first ( ) ; VR ; VR = InsDefs . find_next ( VR ) ) { if ( ! DoConst && isConstant ( VR ) ) continue ; if ( findSelfReference ( VR ) || isSmallConstant ( VR ) ) continue ; findRecordInsertForms ( VR , AVs ) ; if ( IFMap . size ( ) > MaxIFMSize ) return ; } } for ( unsigned VR = InsDefs . find_first ( ) ; VR ; VR = InsDefs . find_next ( VR ) ) AVs . insert ( VR ) ; BlockDefs . insert ( InsDefs ) ; } for ( auto * DTN : children < MachineDomTreeNode * > ( MDT -> getNode ( B ) ) ) { MachineBasicBlock * SB = DTN -> getBlock ( ) ; collectInBlock ( SB ,


<s> void setManipulatesSP ( bool MSP ) { ManipulatesSP = MSP


<s> if ( STI -> getFeatureBits ( ) . test ( FeatureGFX90AInsts ) ) return <NUM_LIT> ; bool IsWave32 = EnableWavefrontSize32 ? * EnableWavefrontSize32 : STI -> getFeatureBits ( ) . test ( FeatureWavefrontSize32 ) ; return IsWave32 ?


<s> if ( LaneMask . all ( ) || TargetRegisterInfo :: isPhysicalRegister ( Reg ) || LaneMask == MRI -> getMaxLaneMaskForVReg ( Reg ) ) { Func ( <NUM_LIT> ) ; return ; } const TargetRegisterClass * RC = MRI -> getRegClass ( Reg ) ; unsigned E = TRI -> getNumSubRegIndices ( ) ; SmallVector < unsigned , <STR_LIT> > CoveringSubregs ; for ( unsigned Idx = <NUM_LIT> ; Idx < E ; ++ Idx ) { if ( TRI -> getSubClassWithSubReg ( RC , Idx ) != RC ) continue ; LaneBitmask SubRegMask = TRI -> getSubRegIndexLaneMask ( Idx ) ; if ( SubRegMask == LaneMask ) { Func ( Idx ) ; return ; } if ( ( SubRegMask & ~ LaneMask ) . any ( ) || ( SubRegMask & LaneMask ) . none ( ) ) continue ; CoveringSubregs . push_back ( Idx ) ; } llvm :: sort ( CoveringSubregs , [ this ] ( unsigned A , unsigned B ) { LaneBitmask MaskA = TRI -> getSubRegIndexLaneMask ( A ) ; LaneBitmask MaskB = TRI -> getSubRegIndexLaneMask ( B ) ; unsigned NA = MaskA . getNumLanes ( ) ; unsigned NB = MaskB . getNumLanes ( ) ; if ( NA != NB ) return NA > NB ; return MaskA . getHighestLane ( ) > MaskB . getHighestLane ( ) ; } )


<s> bool is64Bit = TM . is<ISA_LIT>64 ( ) ; DebugLoc dl = MI . getDebugLoc ( ) ; BuildMI ( MBB , II , dl , TII . get ( is64Bit ? <STR_LIT> : <STR_LIT> ) , MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) . addImm ( maxCallFrameSize ) ; MBB . erase


<s> if ( AsmTokStr == <STR_LIT> || AsmTokStr == <STR_LIT> ) return ParseIntelOperator ( IOK_TYPE ) ; } unsigned Size = getIntelMemOperandSize ( Tok . getString ( ) ) ; if ( Size ) { Parser . Lex ( ) ; if ( Tok . getString ( ) != <STR_LIT> && Tok . getString ( ) != <STR_LIT> ) return ErrorOperand ( Start , <STR_LIT> ) ; Parser . Lex ( ) ; } Start = Tok . getLoc ( ) ; if ( getLexer ( ) . is ( AsmToken :: Integer ) || getLexer ( ) . is ( AsmToken :: Minus ) || getLexer ( ) . is ( AsmToken :: LParen ) ) { AsmToken StartTok = Tok ; IntelExprStateMachine SM ( <NUM_LIT> , true , false ) ; if ( ParseIntelExpression ( SM , End ) ) return nullptr ; int64_t Imm = SM . getImm ( ) ; if ( isParsingInlineAsm ( ) ) { unsigned Len = Tok . getLoc ( ) . getPointer ( ) - Start . getPointer ( ) ; if ( StartTok . getString ( ) . size ( ) == Len ) InstInfo

-> AsmRewrites -> push_back ( AsmRewrite ( AOK_ImmPrefix , Start ) ) ;


<s> BuildMI ( checkMBB , DL , TII . get ( <STR_LIT> ) , ScratchReg2 ) . addImm ( TlsOffset ) ; BuildMI ( checkMBB , DL , TII . get ( <STR_LIT> ) ) . addReg ( ScratchReg ) . addReg ( ScratchReg2 ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( TlsReg ) ; if ( SaveScratch2 ) BuildMI ( checkMBB , DL , TII . get ( <STR_LIT> ) , ScratchReg2 ) ; } } BuildMI ( checkMBB , DL , TII . get ( <STR_LIT> ) ) . addMBB ( & PrologueMBB ) ; if ( Is64Bit ) { const unsigned RegAX = IsLP64 ? <STR_LIT> : <STR_LIT> ; const unsigned Reg10 = IsLP64 ? <STR_LIT> : <STR_LIT> ; const unsigned Reg11 = IsLP64 ? <STR_LIT> : <STR_LIT> ; const unsigned MOVrr = IsLP64 ? <STR_LIT> : <STR_LIT> ; const unsigned MOVri = IsLP64 ? <STR_LIT> : <STR_LIT> ; if ( IsNested ) BuildMI ( allocMBB , DL , TII . get ( MOVrr ) , RegAX ) . addReg ( Reg10 ) ; BuildMI ( allocMBB , DL , TII . get ( MOVri ) , Reg10 ) . addImm ( StackSize ) ; BuildMI ( allocMBB , DL , TII . get ( MOVri ) , Reg11 ) . addImm ( <ISA_LIT>FI -> getArgumentStackSize ( ) ) ; } else { BuildMI ( allocMBB , DL , TII . get ( <STR_LIT> ) ) . addImm ( <ISA_LIT>FI -> getArgumentStackSize ( ) ) ; BuildMI ( allocMBB , DL , TII . get ( <STR_LIT> ) ) . addImm ( StackSize ) ; } if ( Is64Bit && MF . getTarget ( ) . getCodeModel ( ) == CodeModel :: Large ) { if ( STI . useRetpoline ( ) ) report_fatal_error ( <STR_LIT> <STR_LIT> ) ; BuildMI ( allocMBB , DL , TII . get ( <STR_LIT> ) ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) . addExternalSymbol ( <STR_LIT> ) . addReg ( <NUM_LIT> ) ; MF . getMMI ( ) . setUsesMorestackAddr ( true ) ; } else { if ( Is64Bit ) BuildMI ( allocMBB , DL , TII . get ( <STR_LIT> ) ) . addExternalSymbol ( <STR_LIT> ) ; else BuildMI ( allocMBB , DL , TII . get ( <STR_LIT> ) ) . addExternalSymbol ( <STR_LIT> ) ; } if ( IsNested ) BuildMI ( allocMBB , DL , TII . get ( <STR_LIT> ) ) ; else BuildMI ( allocMBB , DL , TII . get ( <STR_LIT> ) ) ; allocMBB -> addSuccessor ( & PrologueMBB ) ; checkMBB -> addSuccessor ( allocMBB


<s> MVT VT = Op . getSimpleValueType ( ) ; switch ( VT . SimpleTy ) { default : break ; case <STR_LIT> : case <STR_LIT> : return SDValue ( )


<s> unsigned isLS = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; bool isOnlyStoreBarrier = ( isLL == <NUM_LIT> && isLS == <NUM_LIT> ) ; <STR_LIT> DMBOpt ; if ( isDeviceBarrier ) DMBOpt = isOnlyStoreBarrier ? <STR_LIT> : <STR_LIT> ; else DMBOpt = isOnlyStoreBarrier ? <STR_LIT> : <STR_LIT> ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) , DAG

. getConstant ( DMBOpt , <STR_LIT> ) ) ;


<s> if ( GET_MODE_SIZE ( from ) == GET_MODE_SIZE ( to ) ) return false ; if ( MAYBE_FP_REG_CLASS_P ( rclass ) ) return true ; if ( GET_MODE_SIZE ( to ) > UNITS_PER_WORD && GET_MODE_SIZE ( to ) > GET_MODE_SIZE


<s> return ( __m64 ) __builtin_arm_wcmpgtub ( ( __v8qi ) __m1 ,


<s> unsigned DPRDefReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; for ( MachineRegisterInfo :: use_iterator I = MRI -> use_begin ( DPRDefReg ) , E = MRI -> use_end ( ) ; I != E ; ++ I ) Uses . push_back ( & I . getOperand ( ) ) ; unsigned NewReg = optimizeSDPattern ( MI ) ; if ( NewReg != <NUM_LIT> ) { Modified = true ; for ( SmallVectorImpl < MachineOperand * > :: const_iterator I = Uses . begin ( ) , E = Uses . end ( ) ; I != E ; ++ I ) { DEBUG ( dbgs ( ) << <STR_LIT> << * * I << <STR_LIT> << PrintReg ( NewReg ) << <STR_LIT> ) ; ( * I ) -> substVirtReg ( NewReg , <NUM_LIT> , * TRI ) ; } } Replacements [ MI ] = NewReg ; } } return Modified


<s> assert ( isPowerOf2_32 ( SegLen ) ) ; SmallVector < unsigned , <NUM_LIT> > SegList ; if ( SM . MaxSrc == - <NUM_LIT> ) return SegList ; unsigned Shift = Log2_32 ( SegLen ) ; BitVector Segs ( alignTo ( SM . MaxSrc + <NUM_LIT> , SegLen ) >> Shift ) ; for ( int I = <NUM_LIT> , E = SM . Mask . size ( ) ; I != E ; ++ I ) { int M = SM . Mask [ I ] ; if ( M >= <NUM_LIT> ) Segs . set ( M >> Shift ) ; } for ( unsigned B : Segs . set_bits ( )


<s> static std :: unique_ptr < <ISA_LIT>Operand > CreateReg ( unsigned RegNum , SMLoc S , SMLoc E ) { return make_unique < <ISA_LIT>Operand > ( k_Reg ,


<s> ScheduleDAGInstrs * <ISA_LIT>PassConfig :: createMachineScheduler ( MachineSchedContext *


<s> if ( ST -> hasVSX ( ) ) { if ( LT . second == <STR_LIT> || LT . second == <STR_LIT> ) return Cost ; } bool UnalignedAltivec = Src -> isVectorTy ( ) && Src -> getPrimitiveSizeInBits ( ) >= LT . second . getSizeInBits ( ) && LT . second . getSizeInBits ( ) == <NUM_LIT> && Opcode == Instruction :: Load ; unsigned SrcBytes = LT . second . getStoreSize ( ) ; if ( SrcBytes && Alignment && Alignment < SrcBytes && ! UnalignedAltivec ) { Cost += LT . first * ( SrcBytes / Alignment - <NUM_LIT> ) ; if ( Src -> isVectorTy ( ) && Opcode == Instruction :: Store ) for ( int i = <NUM_LIT> , e = Src -> getVectorNumElements ( ) ; i < e ; ++ i ) Cost += getVectorInstrCost ( Instruction :: ExtractElement , Src , i ) ; } return Cost


<s> CASE ( <NUM_LIT> ) ; CASE ( <NUM_LIT> ) ; CASE ( <NUM_LIT> ) ; CASE ( <NUM_LIT> ) ; CASE ( <NUM_LIT> ) ; CASE ( <NUM_LIT> ) ; CASE ( <NUM_LIT> ) ; CASE ( <NUM_LIT> ) ; CASE ( <NUM_LIT> ) ; CASE ( <NUM_LIT> ) ; CASE ( <NUM_LIT> ) ; CASE ( <NUM_LIT> ) ; CASE ( <NUM_LIT> ) ; CASE ( <NUM_LIT> ) ; CASE ( <NUM_LIT> ) ; case <STR_LIT> ## n : \ case <STR_LIT> ## n : \ case <STR_LIT> ## n : \ case <STR_LIT> ## n : \ case <STR_LIT> ## n : \ return HasSVE ? <STR_LIT> ## n : <STR_LIT> ## n CASE ( <NUM_LIT> ) ; CASE ( <NUM_LIT> ) ; CASE ( <NUM_LIT> ) ; CASE ( <NUM_LIT> ) ; CASE ( <NUM_LIT> ) ; CASE ( <NUM_LIT> ) ; CASE ( <NUM_LIT> ) ; CASE ( <NUM_LIT> ) ; CASE ( <NUM_LIT> ) ; CASE ( <NUM_LIT> ) ; CASE ( <NUM_LIT> ) ; CASE ( <NUM_LIT> ) ; CASE ( <NUM_LIT> ) ; CASE ( <NUM_LIT> ) ; CASE ( <NUM_LIT> ) ; CASE ( <NUM_LIT> ) ; CASE ( <NUM_LIT> ) ; CASE ( <NUM_LIT> ) ; CASE ( <NUM_LIT> ) ; CASE ( <NUM_LIT> ) ; CASE ( <NUM_LIT> ) ; CASE ( <NUM_LIT> ) ; CASE ( <NUM_LIT> ) ; CASE ( <NUM_LIT> ) ; CASE ( <NUM_LIT> ) ; CASE ( <NUM_LIT> ) ; CASE ( <NUM_LIT> ) ; CASE ( <NUM_LIT> ) ; CASE ( <NUM_LIT> ) ; CASE ( <NUM_LIT>


<s> void \ sdata_section ( ) \ { \ if ( in_section != in_sdata ) \ { \ fprintf ( asm_out_file ,

<STR_LIT> , SDATA_SECTION_ASM_OP ) ; \ in_section = in_sdata ; \ } \ }


<s> output_addr_const ( file , op ) ; fprintf ( file , <STR_LIT> , reg_names [ GP_REGNO ] ) ; return ; } else if ( r0rel_constant_p ( op ) ) { if ( CONST_INT_P ( op ) ) { output_addr_const ( file , op ) ; fprintf ( file , <STR_LIT> ) ; return ; } else { fprintf ( file , <STR_LIT> ) ; output_addr_const ( file , op ) ; fprintf ( file , <STR_LIT> ) ; return ; } } break ; case PLUS : { rtx op0 = XEXP ( op , <NUM_LIT> ) ; rtx op1 = XEXP ( op , <NUM_LIT> ) ; if ( REG_P ( op0 ) && CONSTANT_P ( op1 ) ) { output_addr_const ( file , op1 ) ; fprintf ( file , <STR_LIT> , reg_names [ REGNO ( op0 ) ] ) ; return ; } else if ( REG_P ( op1 ) && CONSTANT_P ( op0 ) ) { output_addr_const ( file , op0 )


<s> llvm_unreachable ( <STR_LIT> ) ; case VK_<ISA_LIT>_LO : Result = Result & <NUM_LIT> ; break ; case VK_<ISA_LIT>_HI : Result = ( Result >> <NUM_LIT> ) & <NUM_LIT> ; break ; case VK_<ISA_LIT>_HA : Result = ( ( Result + <NUM_LIT> ) >> <NUM_LIT> ) & <NUM_LIT> ; break ; case VK_<ISA_LIT>_HIGHER : Result = ( Result >> <NUM_LIT> ) & <NUM_LIT> ; break ; case VK_<ISA_LIT>_HIGHERA : Result = ( ( Result + <NUM_LIT> ) >> <NUM_LIT> ) & <NUM_LIT> ; break ; case VK_<ISA_LIT>_HIGHEST : Result = ( Result >> <NUM_LIT> ) & <NUM_LIT> ; break ; case VK_<ISA_LIT>_HIGHESTA : Result = ( ( Result + <NUM_LIT> ) >> <NUM_LIT> ) & <NUM_LIT> ; break ; } Res = MCValue :: get ( Result ) ; } else { MCContext & Context = Layout -> getAssembler ( ) . getContext ( ) ; const MCSymbolRefExpr * Sym = Value . getSymA ( ) ; MCSymbolRefExpr :: VariantKind Modifier = Sym -> getKind ( ) ; if ( Modifier != MCSymbolRefExpr :: VK_None ) return false ; switch ( Kind ) { default : llvm_unreachable ( <STR_LIT> ) ; case VK_<ISA_LIT>_LO : Modifier = MCSymbolRefExpr :: VK_<ISA_LIT>_LO ; break ; case VK_<ISA_LIT>_HI : Modifier = MCSymbolRefExpr :: VK_<ISA_LIT>_HI ; break ; case VK_<ISA_LIT>_HA : Modifier = MCSymbolRefExpr :: VK_<ISA_LIT>_HA ; break ; case VK_<ISA_LIT>_HIGHERA : Modifier = MCSymbolRefExpr :: VK_<ISA_LIT>_HIGHERA ; break ; case VK_<ISA_LIT>_HIGHER : Modifier = MCSymbolRefExpr :: VK_<ISA_LIT>_HIGHER ; break ; case VK_<ISA_LIT>_HIGHEST


<s> void MCLDInitialize<ISA_LIT>LDTargetInfo ( ) { mcld :: RegisterTarget < llvm :: Triple :: arm

> X ( The<ISA_LIT>Target , <STR_LIT> ) ;


<s> if ( NumBytes ) { assert ( ! MFI . getPristineRegs ( MF ) . test ( <STR_LIT> ) && <STR_LIT> ) ; emitThumbRegPlusImmediate ( MBB , MBBI , dl , <STR_LIT> , FramePtr , - NumBytes , TII , * RegInfo ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . add ( predOps ( <STR_LIT> ) ) ; } else BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( FramePtr ) . add ( predOps ( <STR_LIT> ) ) ; } else { unsigned ScratchRegister = <STR_LIT> ; bool HasFP = hasFP ( MF ) ; for ( auto & I : MFI . getCalleeSavedInfo ( ) ) { unsigned Reg = I . getReg ( ) ; if ( is<ISA_LIT>LowRegister ( Reg ) && ! ( HasFP && Reg == FramePtr ) ) { ScratchRegister = Reg ; break ; } } if ( MBBI != MBB . end ( ) && MBBI -> getOpcode ( ) == <STR_LIT> && & MBB . front ( ) != & * MBBI && std :: prev ( MBBI ) -> getOpcode ( ) == <STR_LIT> ) { MachineBasicBlock :: iterator PMBBI = std :: prev ( MBBI ) ; if ( ! tryFoldSPUpdateIntoPushPop ( STI , MF , & * PMBBI , NumBytes ) ) emitPrologueEpilogueSPUpdate ( MBB , PMBBI , TII , dl , * RegInfo , NumBytes , ScratchRegister , MachineInstr :: NoFlags ) ; } else if ( ! tryFoldSPUpdateIntoPushPop ( STI , MF , & * MBBI , NumBytes ) ) emitPrologueEpilogueSPUpdate ( MBB , MBBI ,


<s> bool fixupNeedsRelaxation ( const MCFixup & Fixup , uint64_t Value , const MCInstFragment * DF , const MCAsmLayout & Layout ) const { llvm_unreachable (


<s> } ; assert ( ! isOverloaded ( IntrID ) && <STR_LIT> ) ; if ( IntrID < <STR_LIT> ) return <NUM_LIT> ; assert ( IntrID < <STR_LIT> && <STR_LIT> ) ; std :: string Result ( names [ IntrID - <STR_LIT> ] ) ; return


<s> if ( really_return ) { rtx ops [ <NUM_LIT> ] ; ops [ <NUM_LIT> ] = operand ; ops [ <NUM_LIT> ] = gen_rtx_SYMBOL_REF ( Pmode , NEED_PLT_RELOC ? <STR_LIT> : <STR_LIT> ) ; assemble_external_libcall ( ops [ <NUM_LIT> ] ) ; output_asm_insn ( reverse ? <STR_LIT> : <STR_LIT> , ops ) ; } return <STR_LIT> ; } gcc_assert ( ! current_function_calls_alloca || really_return ) ; sprintf ( conditional , <STR_LIT> , reverse ? 'D' : 'd' ) ; return_used_this_function = <NUM_LIT> ; live_regs_mask = arm_compute_save_reg_mask ( ) ; if ( live_regs_mask ) { const char * return_reg ; if ( really_return && ! TARGET_INTERWORK ) return_reg = reg_names [ PC_REGNUM ] ; else return_reg = reg_names [ LR_REGNUM ] ; if ( ( live_regs_mask & ( <NUM_LIT> << IP_REGNUM ) ) == ( <NUM_LIT> << IP_REGNUM ) ) { if ( frame_pointer_needed ) { live_regs_mask &= ~ ( <NUM_LIT> << IP_REGNUM ) ; live_regs_mask |= ( <NUM_LIT> << SP_REGNUM ) ; } else gcc_assert ( IS_INTERRUPT ( func_type ) || TARGET_REALLY_IWMMXT ) ; } for ( reg = <NUM_LIT> ; reg <= LAST_ARM_REGNUM ; reg ++ ) if ( live_regs_mask == ( <NUM_LIT> << reg ) ) break ; if ( reg <= LAST_ARM_REGNUM && ( reg != LR_REGNUM || ! really_return || ! IS_INTERRUPT ( func_type ) ) ) { sprintf ( instr , <STR_LIT> , conditional , ( reg == LR_REGNUM ) ? return_reg : reg_names [ reg ] ) ; } else { char * p ; int first = <NUM_LIT> ; if ( live_regs_mask & ( <NUM_LIT> << SP_REGNUM ) ) { unsigned HOST_WIDE_INT stack_adjust ; offsets = arm_get_frame_offsets ( ) ; stack_adjust = offsets -> outgoing_args - offsets -> saved_regs ; gcc_assert ( stack_adjust == <NUM_LIT> || stack_adjust == <NUM_LIT> ) ; if ( stack_adjust && arm_arch5 ) sprintf ( instr , <STR_LIT> , conditional ) ; else { if ( stack_adjust ) live_regs_mask |= <NUM_LIT> << <NUM_LIT> ; sprintf ( instr , <STR_LIT> , conditional ) ; } } else sprintf ( instr , <STR_LIT> , conditional ) ; p = instr + strlen ( instr ) ; for ( reg = <NUM_LIT> ; reg <= SP_REGNUM ; reg ++ ) if ( live_regs_mask & ( <NUM_LIT> << reg ) ) { int l = strlen ( reg_names [ reg ] ) ; if ( first ) first = <NUM_LIT> ; else { memcpy ( p , <STR_LIT> , <NUM_LIT> ) ; p +=


<s> emit_insn ( gen_rtx_SET ( target , x ) ) ; return true ; } return false ; case E_V8QImode : case E_V4QImode : if ( ! mmx_ok ) return false ; goto widen ; case E_V8HImode : case E_V8HFmode : case E_V8BFmode : if ( TARGET_AVX2 ) return ix86_vector_duplicate_value ( mode , target , val ) ; if ( TARGET_SSE2 ) { struct expand_vec_perm_d dperm ; rtx tmp1 , tmp2 ; permute : memset ( & dperm , <NUM_LIT> , sizeof ( dperm ) ) ; dperm . target = target ; dperm . vmode = mode ; dperm . nelt = GET_MODE_NUNITS ( mode ) ; dperm . op0 = dperm . op1 = gen_reg_rtx ( mode ) ; dperm . one_operand_p = true ; if ( mode == V8HFmode || mode == V8BFmode ) { tmp1 = force_reg ( GET_MODE_INNER ( mode ) , val ) ; tmp2 = gen_reg_rtx ( mode ) ; emit_insn ( maybe_gen_vec_set_0 ( mode , tmp2 , CONST0_RTX ( mode ) , tmp1 ) ) ; tmp1 = gen_lowpart ( mode , tmp2 ) ; } else { tmp1 = gen_reg_rtx ( SImode ) ; emit_move_insn ( tmp1 , gen_lowpart ( SImode , val ) ) ; tmp2 = gen_reg_rtx ( V4SImode ) ; emit_insn ( gen_vec_setv4si_0 ( tmp2 , CONST0_RTX ( V4SImode ) , tmp1 ) ) ; tmp1 = gen_lowpart ( mode , tmp2 ) ; } emit_move_insn ( dperm . op0 , tmp1 ) ; ok = ( expand_vec_perm_1 ( & dperm ) || expand_vec_perm_broadcast_1 ( & dperm ) ) ; gcc_assert ( ok ) ; return ok ; } goto widen ; case E_V16QImode : if ( TARGET_AVX2 ) return ix86_vector_duplicate_value ( mode , target , val ) ; if ( TARGET_SSE2 ) goto permute ; goto widen ; widen : { machine_mode smode , wsmode , wvmode ; rtx x ; smode = GET_MODE_INNER ( mode ) ; wvmode = get_mode_wider_vector ( mode ) ; wsmode = GET_MODE_INNER ( wvmode ) ; val = convert_modes ( wsmode , smode , val , true ) ; if ( smode == QImode && ! TARGET_PARTIAL_REG_STALL ) emit_insn ( gen_insv_1 ( wsmode , val , val ) ) ; else { x = expand_simple_binop ( wsmode , ASHIFT , val , GEN_INT ( GET_MODE_BITSIZE ( smode ) ) , NULL_RTX , <NUM_LIT> , OPTAB_LIB_WIDEN ) ; val = expand_simple_binop ( wsmode , IOR , val , x , x , <NUM_LIT> , OPTAB_LIB_WIDEN ) ; } x = gen_reg_rtx ( wvmode ) ; ok = ix86_expand_vector_init_duplicate ( mmx_ok , wvmode , x , val ) ; gcc_assert ( ok ) ; emit_move_insn ( target , gen_lowpart ( GET_MODE ( target ) , x ) ) ; return ok ; } case E_V16HImode : case E_V16HFmode : case E_V16BFmode


<s> Fixups . push_back ( MCFixup :: create ( <NUM_LIT> , MO . getExpr ( ) , ( MCFixupKind ) <STR_LIT> ) ) ; const Triple & TT = STI . getTargetTriple ( ) ; bool is<ISA_LIT>64 = TT . getArch ( ) == Triple :: ppc64 || TT . getArch ( ) == Triple :: ppc64le ; return CTX . getRegisterInfo ( ) -> getEncodingValue


<s> MCAsmParser & getParser ( ) const { return


<s> Register getImplicitBufferPtrUserSGPR ( ) const { return ArgInfo . ImplicitBufferPtr


<s> switch ( Opc ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; default : break ; } OpcodeTablePtr = & RegOp2MemOpTable0 ; } else if ( OpNum == <NUM_LIT> ) { OpcodeTablePtr = & RegOp2MemOpTable1 ; } else if ( OpNum == <NUM_LIT> ) { OpcodeTablePtr = & RegOp2MemOpTable2 ; } if ( OpcodeTablePtr ) { DenseMap < unsigned * , std :: pair < unsigned , unsigned > > :: iterator I = OpcodeTablePtr -> find ( ( unsigned * ) Opc ) ; if ( I != OpcodeTablePtr -> end ( ) )


<s> APInt Imm ( <NUM_LIT> , <NUM_LIT> ) ; for ( unsigned Idx = <NUM_LIT> , e = Src . getNumOperands ( ) ; Idx < e ; ++ Idx ) { if ( ! Src . getOperand ( Idx ) . isUndef ( ) && Src . getConstantOperandAPInt ( Idx ) . isNegative ( ) ) Imm . setBit ( Idx ) ; } return DAG . getConstant ( Imm , SDLoc ( N ) , VT ) ; } unsigned EltWidth = SrcVT . getScalarSizeInBits ( ) ; if ( Subtarget . hasSSE2 ( ) && Src . getOpcode ( ) == <STR_LIT> && Src . getOperand ( <NUM_LIT> ) . getScalarValueSizeInBits ( ) == EltWidth ) return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , VT , Src . getOperand ( <NUM_LIT> ) ) ; if ( SDValue NotSrc = IsNOT ( Src , DAG ) ) { SDLoc DL ( N ) ; APInt NotMask = APInt :: getLowBitsSet ( NumBits , NumElts ) ; NotSrc = DAG . getBitcast ( SrcVT , NotSrc ) ; return DAG . getNode ( <STR_LIT> , DL , VT , DAG . getNode ( <STR_LIT> , DL , VT , NotSrc ) , DAG . getConstant ( NotMask , DL , VT ) ) ; } const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; APInt DemandedMask ( APInt :: getAllOnesValue ( NumBits ) ) ; if ( TLI . SimplifyDemandedBits ( SDValue ( N , <NUM_LIT> ) , DemandedMask , DCI ) ) return SDValue ( N , <NUM_LIT> ) ; return SDValue ( )


<s> if ( basic_align < <NUM_LIT> ) return


<s> switch ( Opcode ) { default : return NULL ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return


<s> u . i [ <NUM_LIT> ] = a ; u . i [ <NUM_LIT> ] = b ; u . i [ <NUM_LIT> ] = c ; u . i [ <NUM_LIT> ]


<s> EVT OpVT = VT ; unsigned NumBits = VT . getSizeInBits ( ) ; DebugLoc dl = Op . getDebugLoc ( ) ; Op = Op . getOperand ( <NUM_LIT> ) ; if ( VT == <STR_LIT> ) { OpVT = <STR_LIT> ; Op = DAG . getNode ( <STR_LIT> , dl , OpVT , Op ) ; } SDVTList VTs = DAG . getVTList ( OpVT , <STR_LIT> ) ; Op = DAG . getNode ( <STR_LIT> , dl , VTs ,


<s> return D ( <STR_LIT> , R ( a ) , <STR_LIT> ,


<s> VT = LD -> getMemoryVT ( ) ; Ptr = LD -> getBasePtr ( ) ; } else if ( StoreSDNode * ST = dyn_cast < StoreSDNode > ( N ) ) { VT = ST -> getMemoryVT ( ) ; Ptr = ST -> getBasePtr ( ) ; } else return false ; bool IsInc ; if ( ! getIndexedAddressParts ( Ptr . getNode ( ) , Base , Offset , AM , IsInc , DAG ) ) return false ; AM = IsInc ? <STR_LIT> : <STR_LIT> ; return true


<s> if ( const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( Imm . Val ) ) return CE -> getValue ( ) % <NUM_LIT> == <NUM_LIT> ; return true


<s> case E_SImode : gen_neg = gen_negsi2 ; break ; case E_DImode : gen_neg = gen_negdi2 ; break ; default : gcc_unreachable ( ) ; } e1 = gen_reg_rtx ( inmode ) ; e2 = gen_reg_rtx ( inmode ) ; res = gen_reg_rtx ( outmode ) ; half = const_double_from_real_value ( dconsthalf , inmode ) ; emit_insn ( gen_rtx_SET ( scratch , gen_rtx_UNSPEC ( HImode , gen_rtvec ( <NUM_LIT> , op1 ) , UNSPEC_FXAM ) ) ) ; emit_insn ( gen_abs ( e1 , op1 ) ) ; half = force_reg ( inmode , half ) ; emit_insn ( gen_rtx_SET ( e2 , gen_rtx_PLUS ( inmode , e1 , half ) ) ) ; if ( inmode != XFmode ) { tmp1 = gen_reg_rtx ( XFmode ) ; emit_insn ( gen_rtx_SET ( tmp1 , gen_rtx_FLOAT_EXTEND ( XFmode , e2 ) ) ) ; } else tmp1 = e2 ; switch ( outmode ) { case E_SFmode : case E_DFmode : { rtx tmp0 = gen_reg_rtx ( XFmode ) ; emit_insn ( gen_frndintxf2_floor ( tmp0 , tmp1 ) ) ; emit_insn ( gen_rtx_SET ( res , gen_rtx_UNSPEC ( outmode , gen_rtvec ( <NUM_LIT> , tmp0 ) , UNSPEC_TRUNC_NOOP ) ) ) ; } break ; case E_XFmode : emit_insn ( gen_frndintxf2_floor ( res , tmp1 ) ) ; break ; case E_HImode : emit_insn ( gen_lfloorxfhi2 ( res , tmp1 ) ) ; break ; case E_SImode : emit_insn ( gen_lfloorxfsi2 ( res , tmp1 ) ) ; break ; case E_DImode : emit_insn ( gen_lfloorxfdi2 ( res , tmp1 ) ) ; break ; default : gcc_unreachable ( ) ; } emit_insn ( gen_testqi_ext_1_ccno ( scratch , GEN_INT ( <NUM_LIT> ) ) ) ; tmp = gen_rtx_IF_THEN_ELSE ( VOIDmode , gen_rtx_EQ ( VOIDmode , flags , const0_rtx ) , gen_rtx_LABEL_REF ( VOIDmode , jump_label ) , pc_rtx ) ; insn = emit_jump_insn ( gen_rtx_SET ( pc_rtx , tmp ) ) ; predict_jump ( REG_BR_PROB_BASE * <NUM_LIT> / <NUM_LIT> ) ; JUMP_LABEL ( insn ) = jump_label ; emit_insn ( gen_neg ( res , res ) ) ; emit_label ( jump_label ) ; LABEL_NUSES ( jump_label ) = <NUM_LIT> ; emit_move_insn ( op0 , res )


<s> return ( uint64x1_t ) ( __a >= __AARCH64_INT64_C (


<s> SDValue TGAHi = DAG . getTargetGlobalAddress ( GV , dl , PtrVT , <NUM_LIT> , <STR_LIT> ) ; SDValue TGALo = DAG . getTargetGlobalAddress ( GV , dl , PtrVT , <NUM_LIT> , <STR_LIT> ) ; SDValue TLSReg = DAG . getRegister ( is64bit ? <STR_LIT> : <STR_LIT> , is64bit ? <STR_LIT> : <STR_LIT> ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , dl , PtrVT , TGAHi , TLSReg ) ; return DAG . getNode ( <STR_LIT> , dl , PtrVT , TGALo , Hi ) ; } if ( ! is64bit ) llvm_unreachable ( <STR_LIT> ) ; if ( Model == TLSModel :: InitialExec ) { SDValue TGA = DAG . getTargetGlobalAddress ( GV , dl , PtrVT , <NUM_LIT> , <NUM_LIT> ) ; SDValue GOTReg = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; SDValue TPOffsetHi = DAG . getNode ( <STR_LIT> , dl , PtrVT , GOTReg , TGA ) ; SDValue TPOffset = DAG . getNode ( <STR_LIT> , dl , PtrVT , TGA , TPOffsetHi ) ; return DAG . getNode ( <STR_LIT> , dl , PtrVT , TPOffset , TGA ) ; } if ( Model == TLSModel :: GeneralDynamic ) { SDValue TGA = DAG . getTargetGlobalAddress ( GV , dl , PtrVT , <NUM_LIT> , <NUM_LIT> ) ; SDValue GOTReg = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; SDValue GOTEntryHi = DAG . getNode ( <STR_LIT> , dl , PtrVT , GOTReg , TGA ) ; SDValue GOTEntry = DAG . getNode ( <STR_LIT> , dl , PtrVT , GOTEntryHi , TGA ) ; SDValue Chain = DAG . getEntryNode ( ) ; Chain = DAG . getCopyToReg ( Chain , dl , <STR_LIT> , GOTEntry ) ; SDValue ParmReg = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; SDValue TLSAddr = DAG . getNode ( <STR_LIT> , dl , PtrVT , ParmReg , TGA ) ; Chain = DAG . getCopyToReg ( Chain , dl , <STR_LIT> , TLSAddr ) ; return DAG . getCopyFromReg ( Chain , dl , <STR_LIT> , PtrVT ) ; } if ( Model == TLSModel :: LocalDynamic


<s> unsigned CC ; if ( ! ITBlock . empty ( ) ) { CC = ITBlock . back ( ) ; ITBlock . pop_back ( ) ; } else CC = <STR_LIT> ; const MCOperandInfo * OpInfo = <ISA_LIT>Insts [ MI . getOpcode ( ) ] . OpInfo ; MCInst :: iterator I = MI . begin ( ) ; unsigned short NumOps = <ISA_LIT>Insts [ MI . getOpcode ( ) ] . NumOperands ; for ( unsigned i = <NUM_LIT> ; i < NumOps ; ++ i , ++ I ) { if ( OpInfo [ i ] . isPredicate ( ) ) { I -> setImm ( CC ) ; ++


<s> if ( Subtarget . hasAVX512 ( ) ) { APInt UndefElts ; SmallVector < APInt , <NUM_LIT> > EltBits ; if ( getTargetConstantBitsFromNode ( Amt , EltSizeInBits , UndefElts , EltBits ) ) { if ( ! UndefElts && llvm :: all_of ( EltBits , [ EltBits ] ( APInt & V ) { return EltBits [ <NUM_LIT> ] == V ; } ) ) { unsigned Op = ( Opcode == <STR_LIT> ? <STR_LIT> : <STR_LIT> ) ; uint64_t RotateAmt = EltBits [ <NUM_LIT> ] . urem ( EltSizeInBits ) ; return DAG . getNode ( Op , DL , VT , R , DAG . getConstant ( RotateAmt , DL , <STR_LIT> ) ) ; } } return Op


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : PointerType * PtrTy = cast < PointerType > ( I . getArgOperand ( <NUM_LIT> ) -> getType ( ) ) ; Info . opc = <STR_LIT> ; Info . memVT = <STR_LIT> ( PtrTy -> getElementType ( ) ) ; Info . ptrVal = I . getArgOperand ( <NUM_LIT> ) ; Info . offset = <NUM_LIT> ; Info . align = Align ( <NUM_LIT> ) ; Info . flags = MachineMemOperand :: MOLoad | MachineMemOperand :: MOStore | MachineMemOperand :: MOVolatile ; return true


<s> bool <ISA_LIT>TargetLowering :: isLegalAddImmediate ( int64_t Imm ) const { return isInt < <NUM_LIT> >


<s> SDValue <ISA_LIT>TargetLowering :: LowerFormalArguments ( SDValue Chain , CallingConv :: ID CallConv , bool isVarArg , const SmallVectorImpl < <STR_LIT> > & Ins , DebugLoc dl , SelectionDAG & DAG , SmallVectorImpl < SDValue > & InVals ) { unsigned NumArgVals = Ins . size ( ) ; MachineFunction & MF = DAG . getMachineFunction ( ) ; const Function * F = MF . getFunction ( ) ; std :: string FuncName = F -> getName ( ) ; ResetTmpOffsetMap ( ) ; InitReservedFrameCount ( F ) ; const char * tmpName = ESNames :: createESName ( PAN :: getArgsLabel ( FuncName


<s> static CodeModel :: Model getEffectiveCodeModel ( Optional < CodeModel :: Model >


<s> static bool v850_return_in_memory ( tree type , tree fntype ATTRIBUTE_UNUSED ) { return int_size_in_bytes ( type ) > <NUM_LIT> ||


<s> Error ( RegLoc , <STR_LIT> ) ; return MatchOperand_ParseFail ; } unsigned Count = <NUM_LIT> ; unsigned FirstReg = Reg ; if ( <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( Reg ) ) { FirstReg = Reg = getDRegFromQReg ( Reg ) ; ++ Reg ; ++ Count ; } if ( parseVectorLane ( LaneKind ) != MatchOperand_Success ) return MatchOperand_ParseFail ; while ( Parser . getTok ( ) . is ( AsmToken :: Comma ) || Parser . getTok ( ) . is ( AsmToken :: Minus ) ) { if ( Parser . getTok ( ) . is ( AsmToken :: Minus ) ) { Parser . Lex ( ) ; SMLoc EndLoc = Parser . getTok ( ) . getLoc ( ) ; int EndReg = tryParseRegister ( ) ; if ( EndReg == - <NUM_LIT> ) { Error ( EndLoc , <STR_LIT> ) ; return MatchOperand_ParseFail ; } if ( <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( EndReg ) ) EndReg = getDRegFromQReg ( EndReg ) + <NUM_LIT> ; if ( Reg == EndReg ) continue ; if ( ! <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( EndReg ) ) { Error ( EndLoc , <STR_LIT> ) ; return MatchOperand_ParseFail ; } if ( Reg > EndReg ) { Error ( EndLoc , <STR_LIT> ) ; return MatchOperand_ParseFail ; } VectorLaneTy NextLaneKind ; if ( parseVectorLane ( NextLaneKind ) != MatchOperand_Success ) return MatchOperand_ParseFail ; if ( NextLaneKind != LaneKind ) { Error ( EndLoc , <STR_LIT> ) ; return MatchOperand_ParseFail ; } EndLoc = Parser . getTok ( ) . getLoc ( ) ; Count += EndReg - Reg ; Reg = EndReg ; continue ; } Parser . Lex ( ) ; RegLoc = Parser . getTok ( ) . getLoc ( ) ; int OldReg = Reg ; Reg = tryParseRegister ( ) ; if ( Reg == - <NUM_LIT> ) { Error ( RegLoc , <STR_LIT> ) ; return MatchOperand_ParseFail ; } if ( <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( Reg ) ) { Reg = getDRegFromQReg ( Reg ) ; if ( Reg != OldReg + <NUM_LIT> ) { Error ( RegLoc , <STR_LIT> ) ; return MatchOperand_ParseFail ; } ++ Reg ; Count += <NUM_LIT> ; VectorLaneTy NextLaneKind ; SMLoc EndLoc = Parser . getTok ( ) . getLoc ( ) ; if ( parseVectorLane ( NextLaneKind ) != MatchOperand_Success ) return MatchOperand_ParseFail ; if ( NextLaneKind != LaneKind


<s> switch ( AsmOp . getReg ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return Match_Success ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return


<s> if ( Op . isReg ( ) ) OS << <STR_LIT> << getRegisterName ( Op . getReg ( ) ) ; else if ( Op . isImm ( ) ) OS


<s> virtual <ISA_LIT>JITInfo * getJITInfo


<s> Res = MCValue :: get ( Res . getSymA ( ) , Res . getSymB ( ) , Res . getConstant ( ) , getKind ( ) ) ; return Res . getSymB ( ) ? getKind ( ) ==


<s> SDLoc dl ( Op ) ; unsigned Depth = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; Register FrameReg = ARI . getFrameRegister ( MF ) ; SDValue FrameAddr = DAG . getCopyFromReg ( DAG . getEntryNode ( ) , dl , FrameReg , VT ) ; while ( Depth -- ) FrameAddr = DAG . getLoad ( VT , dl , DAG . getEntryNode ( ) , FrameAddr , MachinePointerInfo


<s> return Opcode == <STR_LIT> || Opcode == <STR_LIT>


<s> if ( & MBB != & MF . back ( ) ) return false ; MachineBasicBlock :: iterator End = MBB . end ( ) ; -- End ; assert ( End -> getOpcode ( ) == <STR_LIT> ) ; -- End ; if ( & MI != & * End ) return false ; if ( FallthroughOpc != <STR_LIT> ) { MachineOperand & MO = MI . getOperand ( <NUM_LIT> ) ; Register Reg = MO . getReg ( ) ; if ( ! MFI . isVRegStackified ( Reg ) ) { Register NewReg = MRI . createVirtualRegister ( MRI . getRegClass ( Reg ) ) ; BuildMI ( MBB , MI , MI . getDebugLoc ( ) , TII . get ( CopyLocalOpc ) , NewReg ) . addReg ( Reg ) ; MO . setReg ( NewReg ) ; MFI . stackifyVReg ( NewReg ) ; } } MI . setDesc ( TII . get ( FallthroughOpc ) ) ; return


<s> case V8DImode : if ( TARGET_AVX512F ) gen = gen_avx512f_vec_dupv8di_1 ; break ; default : break ; } if ( gen != NULL ) { if ( ! d -> testing_p ) emit_insn ( gen ( d -> target , d -> op0 ) ) ; return true ; } } if ( expand_vselect ( d -> target , d -> op0 , nd . perm , nelt , d -> testing_p ) ) return true ; for ( i = <NUM_LIT> ; i < nelt ; i += <NUM_LIT> ) { nd . perm [ i ] = d -> perm [ i ] & mask ; nd . perm [ i + <NUM_LIT> ] = ( d -> perm [ i + <NUM_LIT> ] & mask ) + nelt ; } if ( expand_vselect_vconcat ( d -> target , d -> op0 , d -> op0 , nd . perm , nelt , d -> testing_p ) ) return true ; if ( nelt >= <NUM_LIT> ) { for ( i = <NUM_LIT> ; i < nelt ; i += <NUM_LIT> ) { nd . perm [ i + <NUM_LIT> ] = d -> perm [ i + <NUM_LIT> ] & mask ; nd . perm [ i + <NUM_LIT> ] = d -> perm [ i + <NUM_LIT> ] & mask ; nd . perm [ i + <NUM_LIT> ] = ( d -> perm [ i + <NUM_LIT> ] & mask ) + nelt ; nd . perm [ i + <NUM_LIT> ] = ( d -> perm [ i + <NUM_LIT> ] & mask ) + nelt ; } if ( expand_vselect_vconcat ( d -> target , d -> op0 , d -> op0 , nd . perm , nelt , d -> testing_p ) ) return true ; } } if ( expand_vselect_vconcat ( d -> target , d -> op0 , d -> op1 , d -> perm , nelt , d -> testing_p ) ) return true ; if ( ! d ->


<s> if ( ! TARGET_HAVE_TLS ) return false ; return for_each_rtx ( & x , &


<s> unsigned Reg = State . AllocateReg ( HiRegList , LoRegList ) ; if ( ! Reg ) return false ; unsigned i ; for ( i = <NUM_LIT> ; i < sizeof ( HiRegList ) / sizeof ( HiRegList [ <NUM_LIT> ] ) ; ++ i ) if ( HiRegList [ i


<s> unsigned SparcRegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { return <STR_LIT>


<s> const MCInstrDesc & Desc = MCII . get ( MI . getOpcode ( ) ) ; unsigned Size = Desc . getSize ( ) ; switch ( Size ) { default : llvm_unreachable ( <STR_LIT> ) ; case <NUM_LIT> : { uint32_t Bits = getBinaryCodeForInstr ( MI ,


<s> assert ( Kind == Token && <STR_LIT> ) ; return StringRef ( Tok . Data , Tok


<s> assert ( VA . getLocInfo ( ) != CCValAssign :: FPExt && <STR_LIT> ) ; if ( ( ValVT == <STR_LIT> || ValVT == <STR_LIT> || VA . getLocReg ( ) == <STR_LIT> || VA . getLocReg ( ) == <STR_LIT> ) && ( Subtarget -> is64Bit ( ) && ! Subtarget -> hasSSE1 ( ) ) ) { report_fatal_error ( <STR_LIT> ) ; } if ( ValVT == <STR_LIT> && ( Subtarget -> is64Bit ( ) && ! Subtarget -> hasSSE2 ( ) ) ) report_fatal_error ( <STR_LIT> ) ; if ( VA . getLocReg ( ) == <STR_LIT> || VA . getLocReg ( ) == <STR_LIT> ) { if ( isScalarFPTypeInSSEReg ( VA . getValVT ( ) ) ) ValToCopy = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , ValToCopy ) ; RetOps . push_back ( ValToCopy ) ; continue ; } if ( Subtarget -> is64Bit ( ) ) { if ( ValVT == <STR_LIT> ) { if ( VA . getLocReg ( ) == <STR_LIT> || VA . getLocReg ( ) == <STR_LIT> ) { ValToCopy = DAG . getBitcast ( <STR_LIT> , ValToCopy ) ; ValToCopy = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , ValToCopy ) ; if ( ! Subtarget -> hasSSE2 ( ) ) ValToCopy = DAG . getBitcast ( <STR_LIT> , ValToCopy ) ; } } } Chain = DAG . getCopyToReg ( Chain , dl , VA . getLocReg ( ) , ValToCopy , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( VA . getLocReg ( ) , VA . getLocVT ( ) ) ) ; } if ( unsigned SRetReg = FuncInfo -> getSRetReturnReg ( ) ) { SDValue Val = DAG . getCopyFromReg ( Chain , dl , SRetReg , getPointerTy ( MF . getDataLayout ( ) ) ) ; unsigned RetValReg = ( Subtarget -> is64Bit ( ) && ! Subtarget -> isTarget64BitILP32 ( ) ) ? <STR_LIT> : <STR_LIT> ; Chain = DAG . getCopyToReg ( Chain , dl , RetValReg , Val , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( RetValReg , getPointerTy (


<s> return ( float32x4_t ) __builtin_neon_vld1_dupv4sf ( ( const __builtin_neon_sf


<s> const char * getPassName ( ) const override { return <STR_LIT>


<s> if ( MI -> getOperand ( i ) . isImplicit ( ) ) continue ; if ( ( int ) i != OpNum + <NUM_LIT> ) O << <STR_LIT> ; printOperand ( MI , i ) ; } O << <STR_LIT>


<s> const TargetRegisterInfo * RegInfo = MF . getSubtarget ( ) . getRegisterInfo ( ) ; if ( MF . hasEHFunclets ( ) ) return true ; if ( MFI . hasCalls ( ) && MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) ) return true ; if ( MFI . hasVarSizedObjects ( ) || MFI . isFrameAddressTaken ( ) || MFI . hasStackMap ( ) || MFI . hasPatchPoint ( ) || RegInfo -> needsStackRealignment ( MF ) ) return true ; if ( ! MFI . isMaxCallFrameSizeComputed ( ) || MFI . getMaxCallFrameSize

( ) > DefaultSafeSPDisplacement ) return true ;


<s> if ( RegNo != <NUM_LIT> ) return MCDisassembler :: Fail ; Inst . addOperand ( MCOperand :: CreateReg


<s> Data32bitsDirective = <STR_LIT> ; Data64bitsDirective = nullptr ; CommentString = <STR_LIT> ; SupportsDebugInformation = true ; LCOMMDirectiveAlignmentType = LCOMM :: ByteAlignment ; InlineAsmStart = <STR_LIT> ; InlineAsmEnd = <STR_LIT> ; ZeroDirective = <STR_LIT> ; AscizDirective = <STR_LIT> ; MinInstAlignment = <NUM_LIT> ; UsesELFSectionDirectiveForBSS =


<s> RegisterSDNode * RN = dyn_cast < RegisterSDNode > ( Base ) ; if ( RN && RN -> getReg ( ) == <NUM_LIT> ) Base = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; else if ( Base . getValueType ( ) == <STR_LIT> && ! dyn_cast < FrameIndexSDNode > ( Base ) ) { Base = SDValue ( CurDAG -> getMachineNode ( TargetOpcode :: SUBREG_TO_REG , DL , <STR_LIT> , CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) , Base , CurDAG -> getTargetConstant ( <STR_LIT> , DL , <STR_LIT> ) ) , <NUM_LIT> ) ; } RN = dyn_cast < RegisterSDNode >


<s> if ( ! TARGET_LINKED_FP ) return ! current_function_sp_is_unchanging ; if ( ! current_function_is_leaf ) return TRUE ; if ( get_frame_size ( ) != <NUM_LIT> ) return TRUE ; if ( cfun -> stdarg ) return TRUE ; if ( ! current_function_sp_is_unchanging ) return TRUE ; if ( ! TARGET_FDPIC && flag_pic && cfun -> uses_pic_offset_table ) return TRUE ; if ( profile_flag ) return TRUE ; if ( cfun -> machine -> frame_needed


<s> if ( CPU == <STR_LIT> ) report_fatal_error ( Twine ( <STR_LIT> ) + ( Is64Bit ? <STR_LIT> : <STR_LIT> ) ) ; if ( TuneCPU . empty ( ) ) TuneCPU = CPU ; ParseSubtargetFeatures ( CPU , TuneCPU


<s> if ( getLexer ( ) . isNot ( AsmToken :: Identifier ) && getLexer ( ) . isNot ( AsmToken :: String ) ) return Error ( L , <STR_LIT> ) ; StringRef CPU = Parser . getTok ( ) . getIdentifier ( ) ; Parser . Lex ( ) ; if ( CPU != <STR_LIT> && CPU != <STR_LIT> && CPU != <STR_LIT> ) return Error ( L , <STR_LIT> ) ; if ( getLexer ( ) . isNot ( AsmToken ::

EndOfStatement ) ) return Error ( L , <STR_LIT> ) ;


<s> if ( getRegSizeInBits ( * NewRC ) < <NUM_LIT> && getRegSizeInBits ( * DstRC ) < <NUM_LIT> && getRegSizeInBits ( * SrcRC ) < <NUM_LIT> ) return true ; auto NewRCWeight = MRI . getTargetRegisterInfo ( ) -> getRegClassWeight ( NewRC ) ; auto SrcRCWeight = MRI . getTargetRegisterInfo ( ) -> getRegClassWeight ( SrcRC ) ; auto DstRCWeight = MRI . getTargetRegisterInfo ( ) -> getRegClassWeight ( DstRC ) ; if ( SrcRCWeight . RegWeight > NewRCWeight . RegWeight ) return true ; if ( DstRCWeight . RegWeight > NewRCWeight . RegWeight ) return true ; auto AFI = MF -> getInfo < <ISA_LIT>FunctionInfo > ( ) ; auto It = AFI -> getCoalescedWeight (


<s> if ( ! MO . isReg ( ) ) continue ; Register Reg = MO . getReg ( ) ; assert ( ! ( Reg >= <STR_LIT> && Reg <= <STR_LIT> ) && <STR_LIT> ) ; if ( isHiRegIdx ( Reg ) ) return


<s> else if ( MII . get ( MI -> getOpcode ( ) ) . TSFlags & <STR_LIT> ) O << <STR_LIT> ; else if ( MII . get ( MI -> getOpcode ( ) ) . TSFlags & <STR_LIT> ) O << <STR_LIT> ; else O << <STR_LIT> ; } printOperand ( MI , OpNo , STI , O ) ; switch ( MI -> getOpcode ( ) ) { default : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> auto Tmp0 = B . buildFMA ( ResTy , NegY , R , One ) ; R = B . buildFMA ( ResTy , Tmp0 , R , R ) ; auto Tmp1 = B . buildFMA ( ResTy , NegY , R , One ) ; R = B . buildFMA ( ResTy , Tmp1 , R , R ) ; auto Ret = B . buildFMul ( ResTy , X , R ) ; auto Tmp2 = B . buildFMA ( ResTy , NegY , Ret , X ) ; B . buildFMA ( Res , Tmp2 ,


<s> for ( unsigned I = <NUM_LIT> , E = Filler -> getNumOperands ( ) ; I != E ; ++ I ) { const MachineOperand & MO = Filler -> getOperand ( I ) ; unsigned R ; if ( ! MO . isReg ( ) || ! MO . isDef ( ) || ! ( R = MO . getReg ( ) ) ) continue ; const MachineFunction & MF = * MBB .


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; default : return false


<s> return SelectAddrModeIndexed7S ( N , <NUM_LIT> ,


<s> return MI . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ; } return MI . getOpcode


<s> unsigned HOST_WIDE_INT nelt ; if ( ! d -> one_vector_p && ! d -> perm . length ( ) . is_constant ( & nelt ) ) return false ; if ( d -> testing_p ) return true ; machine_mode sel_mode = related_int_vector_mode ( d -> vmode ) . require ( ) ; rtx sel = vec_perm_indices_to_rtx ( sel_mode , d -> perm ) ; if ( d -> one_vector_p ) emit_unspec2 ( d -> target , UNSPEC_TBL ,

d -> op0 , force_reg ( sel_mode , sel ) ) ;


<s> const DataLayout & DL = DAG . getDataLayout ( ) ; Type * Ty = VT . getTypeForEVT ( * DAG . getContext ( ) ) ; MVT PtrVT = getPointerTy ( DL , <ISA_LIT>AS :: CONSTANT_ADDRESS ) ; PointerType * PtrTy = PointerType :: get ( Ty , <ISA_LIT>AS :: CONSTANT_ADDRESS ) ; SDValue PtrOffset = DAG . getUNDEF ( PtrVT ) ; MachinePointerInfo PtrInfo ( UndefValue :: get ( PtrTy )


<s> return decodeUImmOperand < <NUM_LIT> >


<s> switch ( AM . Scale ) { case <NUM_LIT> : break ; case <NUM_LIT> : if ( ! AM . HasBaseReg ) break ; return false ; default : return


<s> Operands . push_back ( <STR_LIT> ( IdVal , S , E , * this ) ) ; return MatchOperand_Success ; } if ( Tok . is ( AsmToken :: EndOfStatement ) ) { SMLoc E = SMLoc :: getFromPointer ( Parser . getTok ( ) . getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; auto Base = <STR_LIT> ( <NUM_LIT> , getContext ( ) . getRegisterInfo ( ) , S , E , * this ) ; Operands . push_back ( <STR_LIT> ( std :: move ( Base ) , IdVal , S , E , * this ) ) ; return MatchOperand_Success ; } Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ; } Parser . Lex ( ) ; } Res = parseAnyRegister ( Operands ) ; if ( Res != MatchOperand_Success ) return Res ; if ( Parser . getTok ( ) . isNot ( AsmToken :: RParen ) ) { Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ; } SMLoc E = SMLoc :: getFromPointer ( Parser . getTok ( ) . getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; Parser . Lex ( ) ; if ( ! IdVal ) IdVal = MCConstantExpr :: Create ( <NUM_LIT> , getContext ( ) ) ; std :: unique_ptr < <ISA_LIT>Operand > op ( static_cast < <ISA_LIT>Operand * > ( Operands . back ( ) . release ( ) ) ) ; Operands . pop_back ( ) ; if ( const MCBinaryExpr * BE = dyn_cast < MCBinaryExpr > ( IdVal ) ) { int64_t Imm ; if ( IdVal -> EvaluateAsAbsolute ( Imm ) ) IdVal = MCConstantExpr :: Create ( Imm , getContext ( ) ) ; else if ( BE -> getLHS ( ) -> getKind ( ) != MCExpr :: SymbolRef ) IdVal = MCBinaryExpr :: Create ( BE -> getOpcode ( ) , BE -> getRHS ( ) , BE -> getLHS (


<s> setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT>


<s> code = NE ; op0 = tmp ; op1 = const0_rtx ; break ; case GE : if ( mep_imm4_operand ( op1 , SImode ) ) break ; tmp = gen_reg_rtx ( SImode ) ; gcc_assert ( mep_expand_setcc_1 ( LT , tmp , op0 , op1 ) ) ; code = EQ ; op0 = tmp ; op1 = const0_rtx ; break ; case EQ : case NE : if ( ! mep_reg_or_imm4_operand ( op1 , SImode ) ) op1 = force_reg ( SImode , op1 ) ; break ; case LE : case GT : if ( GET_CODE ( op1 ) == CONST_INT && INTVAL ( op1 ) != <NUM_LIT> ) { op1 = GEN_INT ( INTVAL ( op1 ) + <NUM_LIT> ) ; code = ( code == LE ? LT : GE ) ; goto restart ; } tmp = gen_reg_rtx ( SImode ) ; gcc_assert ( mep_expand_setcc_1 ( LT , tmp , op1 , op0 ) ) ; code = ( code == LE ? EQ : NE ) ; op0 = tmp ; op1 = const0_rtx ; break ; case LTU : if ( op1 == const1_rtx ) { code = EQ ; op1 = const0_rtx ; break ; } tmp = gen_reg_rtx ( SImode ) ; gcc_assert ( mep_expand_setcc_1 ( LTU , tmp , op0 , op1 ) ) ; code = NE ; op0 = tmp ; op1 = const0_rtx ; break ; case LEU : tmp = gen_reg_rtx ( SImode ) ; if ( mep_expand_setcc_1 ( LEU , tmp , op0 , op1 ) ) code = NE ; else if ( mep_expand_setcc_1 ( LTU , tmp , op1 , op0 ) ) code = EQ ; else gcc_unreachable ( ) ; op0 = tmp ; op1 = const0_rtx ; break ; case GTU : tmp = gen_reg_rtx ( SImode ) ; gcc_assert ( mep_expand_setcc_1 ( GTU , tmp , op0 , op1 ) || mep_expand_setcc_1 ( LTU , tmp , op1 , op0 ) ) ; code = NE ; op0 = tmp ; op1 = const0_rtx ; break ; case GEU : tmp = gen_reg_rtx ( SImode ) ; if ( mep_expand_setcc_1 ( GEU , tmp , op0 , op1 ) ) code = NE ; else if ( mep_expand_setcc_1 ( LTU , tmp , op0 , op1 )


<s> int64_t Offset = <NUM_LIT> ; for ( int I = MFI -> getObjectIndexBegin ( ) ; I != <NUM_LIT> ; ++ I ) Offset = std :: max ( Offset , - MFI -> getObjectOffset ( I ) ) ; for ( const MCPhysReg * R = TRI . getCalleeSavedRegs ( & MF ) ; * R ; ++ R ) { unsigned Size = TRI . getMinimalPhysRegClass ( * R ) -> getSize ( ) ; Offset = RoundUpToAlignment ( Offset + Size ,


<s> SMLoc ExprEnd ; getLexer ( ) . UnLex ( AsmToken ( AsmToken :: LParen , <STR_LIT> ) ) ; if ( getParser ( ) . parseExpression ( Disp , ExprEnd ) ) return nullptr ; if ( getLexer ( ) . isNot ( AsmToken :: LParen ) ) { if ( SegReg == <NUM_LIT> ) return <STR_LIT> ( getPointerWidth ( ) , Disp , LParenLoc , ExprEnd ) ; return <STR_LIT> ( getPointerWidth ( ) , SegReg , Disp , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , MemStart , ExprEnd ) ; } Parser . Lex ( ) ; } } unsigned BaseReg = <NUM_LIT> , IndexReg = <NUM_LIT> , Scale = <NUM_LIT> ; SMLoc IndexLoc , BaseLoc ; if ( getLexer ( ) . is ( AsmToken :: Percent ) ) { SMLoc StartLoc , EndLoc ; BaseLoc = Parser . getTok ( ) . getLoc ( ) ; if ( ParseRegister ( BaseReg , StartLoc , EndLoc ) ) return nullptr ; if ( BaseReg == <STR_LIT> || BaseReg == <STR_LIT> ) { Error ( StartLoc , <STR_LIT> , SMRange ( StartLoc , EndLoc ) ) ; return nullptr ; } } if ( getLexer ( ) . is ( AsmToken :: Comma ) ) { Parser . Lex ( ) ; IndexLoc = Parser . getTok ( ) . getLoc ( ) ; if ( getLexer ( ) . is ( AsmToken :: Percent ) ) { SMLoc L ; if ( ParseRegister ( IndexReg , L , L ) ) return nullptr ; if ( BaseReg == <STR_LIT> ) { Error ( IndexLoc , <STR_LIT> ) ; return nullptr ; } if ( IndexReg == <STR_LIT> ) { Error ( IndexLoc , <STR_LIT> ) ; return nullptr ; } if ( getLexer ( ) . isNot ( AsmToken :: RParen ) ) { if ( getLexer ( ) . isNot ( AsmToken :: Comma ) ) { Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; return nullptr ; } Parser . Lex ( ) ; if ( getLexer ( ) . isNot ( AsmToken :: RParen ) ) { SMLoc Loc = Parser . getTok ( ) . getLoc ( ) ; int64_t ScaleVal ; if ( getParser ( ) . parseAbsoluteExpression ( ScaleVal ) ) { Error ( Loc , <STR_LIT> ) ; return nullptr ; } if ( <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( BaseReg ) && ScaleVal != <NUM_LIT> ) { Error ( Loc , <STR_LIT> ) ; return


<s> SDLoc dl ( N ) ; MVT VT = N -> getOperand ( <NUM_LIT> ) -> getSimpleValueType ( <NUM_LIT> ) ; assert ( ( VT == <STR_LIT> || VT == <STR_LIT> ) && <STR_LIT> ) ; SDValue Ld = N -> getOperand ( <NUM_LIT> ) ; if ( MayFoldLoad ( Ld ) ) { unsigned DestIndex = cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) >> <NUM_LIT> ; Ld = NarrowVectorLoadToElement ( cast < LoadSDNode > (


<s> DefMI = MRI -> getVRegDef ( InTileReg ) ; if ( InMBB != & MBB || ! DefMI -> isPHI ( ) ) continue ; InMO = & PHI -> getOperand ( I ) ; break ; } if ( ! InMO ) continue ; Register DefTileReg ; for ( unsigned I = <NUM_LIT> , E = DefMI -> getNumOperands ( ) ; I != E ; I += <NUM_LIT> ) { MachineBasicBlock * InMBB = PHI -> getOperand ( I + <NUM_LIT> ) . getMBB ( ) ; if ( InMBB != & MBB


<s> unsigned OpNo = <NUM_LIT> ; for ( unsigned e = MI . getNumOperands ( ) ; OpNo < e ; ++ OpNo ) { if ( & MO == & MI . getOperand ( OpNo ) ) break ; } const MCInstrDesc & Desc = MCII . get ( MI . getOpcode ( ) ) ; if ( isSrcOperand ( Desc , OpNo ) ) { int RCID = Desc . OpInfo [ OpNo ] . RegClass ; const MCRegisterClass & RC = MRI . getRegClass ( RCID ) ; uint32_t Enc = getLitEncoding ( MO , RC . getSize ( ) ) ; if ( Enc != ~ <NUM_LIT> && ( Enc != <NUM_LIT> || Desc . getSize ( ) == <NUM_LIT> ) ) return Enc ; } else if ( MO . isImm ( ) ) return MO .


<s> fprintf ( file , <STR_LIT> ) ; fprintf ( file , <STR_LIT> , bits ) ; fprintf ( file , <STR_LIT> ) ; fprintf ( file , <STR_LIT> , bits == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ) ; fprintf ( file , <STR_LIT> , bits , loc ) ; fprintf ( file , <STR_LIT> , bits , loc , loc ) ; if ( cfun -> machine -> unisimt_predicate ) { int master = REGNO ( cfun -> machine -> unisimt_master ) ; int pred = REGNO ( cfun -> machine -> unisimt_predicate ) ; fprintf ( file , <STR_LIT> , master , loc ) ; if ( cfun -> machine -> unisimt_outside_simt_predicate ) { int pred_outside_simt = REGNO ( cfun -> machine -> unisimt_outside_simt_predicate ) ; fprintf ( file , <STR_LIT> , pred_outside_simt , master ) ; } fprintf ( file , <STR_LIT> )


getFeatureBits ( ) & <STR_LIT> ) != <NUM_LIT> ;


<s> MF -> insert ( MBBI , NewBB ) ; NewBB -> splice ( NewBB -> end ( ) , OrigBB , MI , OrigBB -> end ( ) ) ; unsigned Opc = isThumb ? ( isThumb2 ? <STR_LIT> : <STR_LIT> ) : <STR_LIT> ; if ( ! isThumb ) BuildMI ( OrigBB , DebugLoc ( ) , TII -> get ( Opc ) ) . addMBB ( NewBB ) ; else BuildMI ( OrigBB , DebugLoc ( ) , TII -> get ( Opc ) ) . addMBB ( NewBB ) . addImm ( <STR_LIT> ) . addReg ( <NUM_LIT> ) ; ++ NumSplit ; NewBB -> transferSuccessors ( OrigBB ) ; OrigBB -> addSuccessor ( NewBB ) ; MF -> RenumberBlocks ( NewBB ) ; BBInfo . insert ( BBInfo . begin ( ) + NewBB -> getNumber ( ) , BasicBlockInfo ( ) ) ; water_iterator IP = std :: lower_bound ( WaterList . begin ( ) , WaterList . end ( ) , OrigBB , CompareMBBNumbers ) ; MachineBasicBlock * WaterBB =


<s> static Optional < <ISA_LIT>BitmanipPat > matchSHFLPat ( SDValue Op ) { static const uint64_t BitmanipMasks [ ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> ,


<s> <ISA_LIT>VSXCopyCleanup ( ) : MachineFunctionPass ( ID ) { initialize<ISA_LIT>VSXCopyCleanupPass ( * PassRegistry :: getPassRegistry


<s> return ( __m64 ) __builtin_ia32_psubsb ( ( __v8qi ) __m1 , ( __v8qi )


<s> void <ISA_LIT>MCInstLower :: Initialize ( Mangler * M ,


<s> SDValue TGALo = DAG . getTargetGlobalAddress ( GV , DL , PtrVT , <NUM_LIT> , <STR_LIT> ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , DL , PtrVT , TGALo ) ; SDValue Add = DAG . getNode ( <STR_LIT> , DL , PtrVT , Hi , Ret ) ; return DAG . getNode ( <STR_LIT> , DL , PtrVT , Add , Lo ) ; } SDValue Offset ; if ( model == TLSModel :: InitialExec ) { SDValue TGA = DAG . getTargetGlobalAddress ( GV , DL , PtrVT , <NUM_LIT> , <STR_LIT> ) ; TGA = DAG . getNode ( <STR_LIT> , DL , PtrVT , getGlobalReg ( DAG , PtrVT ) , TGA ) ; Offset = DAG . getLoad ( PtrVT , DL , DAG . getEntryNode ( ) , TGA , MachinePointerInfo ( ) , false , false , false , <NUM_LIT> ) ; } else { assert ( model == TLSModel :: LocalExec ) ; SDValue TGAHi = DAG . getTargetGlobalAddress ( GV , DL , PtrVT , <NUM_LIT> , <STR_LIT> ) ; SDValue TGALo = DAG . getTargetGlobalAddress ( GV , DL , PtrVT , <NUM_LIT> , <STR_LIT> ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , DL , PtrVT , TGAHi ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , DL , PtrVT , TGALo ) ; Offset = DAG . getNode ( <STR_LIT> , DL , PtrVT , Hi , Lo ) ; } SDValue ThreadPointer = DAG . getNode ( <STR_LIT> , DL , PtrVT ) ; return DAG . getNode ( <STR_LIT> , DL , PtrVT


<s> return id < <NUM_LIT> ? build_pointer_type ( t )


<s> if ( ! SU -> isInstr ( ) ) return false ; MachineInstr * MAI = nullptr ; auto IsMFMAFn = [ & MAI ] ( MachineInstr * MI ) { MAI = nullptr ; if ( <ISA_LIT>InstrInfo :: isMAI ( * MI ) && MI -> getOpcode ( ) != <STR_LIT> && MI -> getOpcode ( ) != <STR_LIT> ) MAI = MI ; return MAI != nullptr ; } ; MachineInstr * MI = SU -> getInstr


<s> bool <ISA_LIT>TargetELFStreamer :: emitDirectiveCpRestore ( int Offset , std :: function < unsigned ( ) > GetATReg , SMLoc IDLoc , const MCSubtargetInfo * STI ) { <ISA_LIT>TargetStreamer :: emitDirectiveCpRestore ( Offset , GetATReg , IDLoc


<s> void addu6ImmOperands ( MCInst & Inst , unsigned N


<s> unsigned <ISA_LIT>MCCodeEmitter :: getMachineOpValue ( const MCInst & MI , const MCOperand & MO , SmallVectorImpl < MCFixup >

& Fixups , const MCSubtargetInfo & STI ) const {


<s> return ( __m128i ) __builtin_ia32_pmovusqb512_mask ( ( __v8di ) __A , ( __v16qi ) _mm_undefined_si128 ( ) , ( __mmask8


<s> unsigned ResultReg = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , ResultReg ) . addFrameIndex ( SI -> second ) . addImm ( <NUM_LIT> ) ; return ResultReg


<s> const DataLayout * getDataLayout ( )


<s> std :: swap ( LHS , RHS ) ; Res = DAG . getCommutedVectorShuffle ( * SVN ) ; Mask = cast < ShuffleVectorSDNode > ( Res ) -> getMask ( ) ; } SmallVector < int , <NUM_LIT> > ShuffV ( Mask . begin ( ) , Mask . end ( ) ) ; SDValue SToVLHS = isScalarToVec ( LHS ) ; SDValue SToVRHS = isScalarToVec ( RHS ) ; if ( SToVLHS || SToVRHS ) { int NumEltsIn = SToVLHS ? SToVLHS . getValueType ( ) . getVectorNumElements ( ) : SToVRHS . getValueType ( ) . getVectorNumElements ( ) ; int NumEltsOut = ShuffV . size ( ) ; int LHSMaxIdx = - <NUM_LIT> ; int RHSMinIdx = - <NUM_LIT> ; int RHSMaxIdx = - <NUM_LIT> ; int HalfVec = LHS . getValueType ( ) . getVectorNumElements ( ) / <NUM_LIT> ; if ( SToVLHS ) { LHSMaxIdx = NumEltsOut / NumEltsIn ; SToVLHS = getSToVPermuted ( SToVLHS , DAG ) ; if ( SToVLHS . getValueType ( ) != LHS . getValueType ( ) ) SToVLHS = DAG . getBitcast ( LHS . getValueType (


<s> if ( min_mem_align > align ) align = min_mem_align / BITS_PER_UNIT ; if ( src_mem_align < align ) src_mem_align = align ; if ( dst_mem_align < align ) dst_mem_align = align ; if ( CONST_INT_P ( count_exp ) ) count = INTVAL ( count_exp ) ; else return false ; if ( count > ( ( unsigned HOST_WIDE_INT ) <NUM_LIT> << <NUM_LIT> ) ) return false ; if ( count >= <NUM_LIT> && ( count & <NUM_LIT> ) == <NUM_LIT> && align >= <NUM_LIT> ) { tree dst_expr = MEM_EXPR ( dst ) ; tree src_expr = MEM_EXPR ( src ) ; rtx fn = TARGET_INSNS_64PLUS ? strasgi64p_libfunc : strasgi_libfunc ; rtx srcreg = force_reg ( Pmode , XEXP ( src , <NUM_LIT> ) ) ; rtx dstreg = force_reg ( Pmode , XEXP ( dst , <NUM_LIT> ) ) ; if ( src_expr ) mark_addressable ( src_expr ) ; if ( dst_expr ) mark_addressable ( dst_expr ) ; emit_library_call ( fn , LCT_NORMAL , VOIDmode , dstreg , Pmode , srcreg , Pmode , count_exp , SImode ) ; return true ; } if ( biggest_move > align && ! TARGET_INSNS_64 ) biggest_move = align ; if ( count / biggest_move > <NUM_LIT> ) return false ; while ( count > <NUM_LIT> ) { rtx reg , reg_lowpart ; machine_mode srcmode , dstmode ; unsigned HOST_WIDE_INT src_size , dst_size , src_left ; int shift ; rtx srcmem , dstmem


<s> unsigned TargetFlags = get ( Opcode ) . TSFlags ; return ( ( TargetFlags & <STR_LIT> )


<s> DecodeGPR32RegisterClass ( Inst , Rs , Addr , Decoder ) ; case <STR_LIT> : case <STR_LIT> : DecodeGPR32RegisterClass ( Inst , Rt , Addr , Decoder ) ; DecodeGPR32RegisterClass ( Inst , Rt2 , Addr , Decoder ) ; break ; case <STR_LIT> : case <STR_LIT> : DecodeGPR32RegisterClass ( Inst , Rs , Addr , Decoder ) ; case <STR_LIT> : case <STR_LIT> : DecodeGPR64RegisterClass ( Inst , Rt , Addr , Decoder ) ; DecodeGPR64RegisterClass ( Inst , Rt2 , Addr , Decoder ) ; break ; } DecodeGPR64spRegisterClass ( Inst , Rn , Addr , Decoder ) ; if ( ( Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> )


<s> unsigned RegList = <NUM_LIT> << RegNum ; int HighRegNum = RegNum ; while ( Parser . getTok ( ) . is ( AsmToken :: Comma ) ) { Parser . Lex ( ) ; const AsmToken & RegTok = Parser . getTok ( ) ; SMLoc RegLoc = RegTok . getLoc ( ) ; if ( RegTok . isNot ( AsmToken :: Identifier ) ) return Error ( RegLoc , <STR_LIT> ) ; int RegNum = MatchRegisterName ( RegTok . getString ( ) ) ; if ( RegNum == - <NUM_LIT> ) return Error ( RegLoc , <STR_LIT>


<s> const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; if ( ! CE )


<s> bool Result = AsmPrinter :: doInitialization ( M ) ; if ( TAI -> doesSupportDebugInformation ( ) ) { MMI = getAnalysisIfAvailable < MachineModuleInfo >


<s> SDLoc dl ( N ) ; ShuffleVectorSDNode * SVOp = cast < ShuffleVectorSDNode > ( N ) ; SDValue V1 = SVOp -> getOperand ( <NUM_LIT> ) ; SDValue V2 = SVOp -> getOperand ( <NUM_LIT> ) ; MVT VT = SVOp -> getSimpleValueType ( <NUM_LIT> ) ; unsigned NumElems = VT . getVectorNumElements ( ) ; if ( V1 . getOpcode ( ) == <STR_LIT> && V2 . getOpcode ( ) == <STR_LIT> ) { if ( V2 . getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> || ! V2 . getOperand ( <NUM_LIT> ) . isUndef ( ) || ! V1 . getOperand ( <NUM_LIT> ) . isUndef ( ) ) return SDValue ( ) ; if ( ! <STR_LIT> ( V2 . getOperand ( <NUM_LIT> ) . getNode ( ) ) ) return SDValue ( ) ; for ( unsigned i = <NUM_LIT> ; i != NumElems / <NUM_LIT> ; ++ i ) if ( ! isUndefOrEqual ( SVOp -> getMaskElt ( i ) , i ) || ! isUndefOrEqual ( SVOp -> getMaskElt ( i + NumElems / <NUM_LIT> ) , NumElems ) ) return SDValue ( ) ; if ( LoadSDNode * Ld = dyn_cast < LoadSDNode > ( V1 . getOperand ( <NUM_LIT> ) ) ) { if ( Ld -> hasNUsesOfValue ( <NUM_LIT>


<s> } if ( is_sse ) { if ( TARGET_AVX ) { strcpy ( buf , ssep ) ; if ( GET_MODE ( operands [ <NUM_LIT> ] ) == SFmode ) strcat ( buf , <STR_LIT> ) ; else strcat ( buf , <STR_LIT> ) ; } else { strcpy ( buf , ssep + <NUM_LIT> ) ; if ( GET_MODE ( operands [ <NUM_LIT> ] ) == SFmode ) strcat ( buf , <STR_LIT> ) ; else strcat ( buf , <STR_LIT> ) ; } return buf ; } strcpy ( buf , p ) ; switch ( GET_CODE ( operands [ <NUM_LIT> ] ) ) { case MULT : case PLUS : if ( REG_P ( operands [ <NUM_LIT> ] ) && REGNO ( operands [ <NUM_LIT> ] ) == REGNO ( operands [ <NUM_LIT> ] ) ) std :: swap ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ; if ( MEM_P ( operands [ <NUM_LIT> ] ) ) { p = <STR_LIT> ; break ; } if ( find_regno_note ( insn , REG_DEAD , REGNO ( operands [ <NUM_LIT> ] ) ) ) { if ( STACK_TOP_P ( operands [ <NUM_LIT> ] ) ) p = <STR_LIT> ; else p = <STR_LIT> ; break ; } if ( STACK_TOP_P ( operands [ <NUM_LIT> ] ) ) p = <STR_LIT> ; else p = <STR_LIT> ; break ; case MINUS : case DIV : if ( MEM_P ( operands [ <NUM_LIT> ] ) ) { p = <STR_LIT> ; break ; } if ( MEM_P ( operands [ <NUM_LIT> ] ) ) { p = <STR_LIT> ; break ; } if ( find_regno_note ( insn , REG_DEAD , REGNO ( operands [ <NUM_LIT> ] ) ) ) { if ( STACK_TOP_P ( operands [ <NUM_LIT> ] ) ) p = <STR_LIT> ; else p = <STR_LIT> ; if ( STACK_TOP_P ( operands [ <NUM_LIT> ] ) ) p =


<s> bool hasProcessorAssist ( ) const { return


<s> bool LHSFromHi = <NUM_LIT> ; if ( ! findEXTRHalf ( N -> getOperand ( <NUM_LIT> ) , LHS , ShiftLHS , LHSFromHi ) ) return SDValue ( ) ; SDValue RHS ; uint32_t ShiftRHS = <NUM_LIT> ; bool RHSFromHi = <NUM_LIT> ; if ( ! findEXTRHalf ( N -> getOperand ( <NUM_LIT> ) , RHS , ShiftRHS , RHSFromHi ) ) return SDValue ( ) ; if ( LHSFromHi == RHSFromHi ) return SDValue ( ) ; if ( ShiftLHS + ShiftRHS != VT . getSizeInBits ( ) ) return SDValue ( ) ; if ( LHSFromHi ) { std :: swap ( LHS , RHS ) ; std :: swap ( ShiftLHS , ShiftRHS ) ; } return DAG . getNode ( <STR_LIT> , DL , VT , LHS

, RHS , DAG . getConstant ( ShiftRHS , <STR_LIT> ) ) ;


<s> static const uint16_t CalleeSavedRegs [ ] = { <NUM_LIT> } ; return CalleeSavedRegs


<s> Comparison C ( getCmp ( DAG , CmpOp0 , CmpOp1 , CC , DL ) ) ; if ( C . Opcode == <STR_LIT> && C . CCMask != <STR_LIT> && C . CCMask != <STR_LIT> && C . Op1 . getOpcode ( ) == <STR_LIT> && cast < ConstantSDNode > ( C . Op1 ) -> getZExtValue ( ) == <NUM_LIT> ) { if ( isAbsolute ( C . Op0 , TrueOp , FalseOp ) ) return getAbsolute ( DAG , DL , TrueOp , C . CCMask & <STR_LIT> ) ; if ( isAbsolute ( C . Op0 , FalseOp , TrueOp ) ) return getAbsolute ( DAG , DL , FalseOp , C . CCMask & <STR_LIT> ) ; } SDValue Glue = emitCmp ( DAG , DL , C ) ; SDValue Ops [ ] = { TrueOp , FalseOp , DAG . getConstant ( C . CCValid , DL , <STR_LIT> ) , DAG . getConstant ( C . CCMask , DL , <STR_LIT> ) , Glue } ; return DAG . getNode ( <STR_LIT> , DL , Op


<s> FunctionPass * llvm :: create<ISA_LIT>ISelDag ( <ISA_LIT>TargetMachine & TM , CodeGenOpt


<s> DebugLoc DL ; if ( Position != MBB . end ( ) ) { DL = Position -> getDebugLoc ( ) ; } if ( ! <STR_LIT> . hasSubClassEq ( RegisterClass ) ) { llvm_unreachable ( <STR_LIT> ) ; } BuildMI ( MBB , Position , DL , get ( <STR_LIT> ) , DestinationRegister ) . addFrameIndex (

FrameIndex ) . addImm ( <NUM_LIT> ) . addImm ( LPAC :: ADD ) ;


<s> const MCInstrDesc & getDesc ( void ) const { return *


<s> EVT Type = Op . getValueType ( ) ; int64_t Val = C -> getSExtValue ( ) ; if ( isInt < <NUM_LIT> > ( Val ) ) { Result = DAG . getTargetConstant ( Val , Type ) ; break ; } } return ; case 'J' : if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Op ) ) { EVT Type = Op . getValueType ( ) ; int64_t Val = C -> getZExtValue ( ) ; if ( Val == <NUM_LIT> ) { Result = DAG . getTargetConstant ( <NUM_LIT> , Type ) ; break ; } } return ; case 'K' : if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Op ) ) { EVT Type = Op . getValueType ( ) ; uint64_t Val = ( uint64_t ) C -> getZExtValue ( ) ; if ( isUInt < <NUM_LIT> > ( Val ) ) { Result = DAG . getTargetConstant ( Val , Type ) ; break ; } } return ; case 'L' : if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Op ) ) { EVT Type = Op . getValueType ( ) ; int64_t Val = C -> getSExtValue ( ) ; if ( ( isInt < <NUM_LIT> > ( Val ) ) && ( ( Val & <NUM_LIT> ) == <NUM_LIT> ) ) { Result = DAG . getTargetConstant ( Val , Type ) ; break ; } } return ; case 'N'


<s> SDValue <ISA_LIT>TargetLowering :: LowerHvxStore ( SDValue Op , SelectionDAG & DAG ) const { auto * N = Op . getNode ( ) ; const SDLoc & dl ( Op ) ; SDValue Q0 = N -> getOperand ( <NUM_LIT> ) ; EVT VTOp = Q0 . getNode ( ) -> getValueType ( <NUM_LIT> ) ; if ( Op . getOpcode ( ) != <STR_LIT> || VTOp != <STR_LIT> ) return Op ; SDValue Vor4 = HvxVecPredBitcastComputation ( Q0 , DAG ) ; SDValue C0 = DAG . getTargetConstant ( <NUM_LIT> , dl , <STR_LIT> ) ; SDValue InstrC0 = getInstr ( <STR_LIT> , dl , <STR_LIT> , C0 , DAG ) ; SDValue Vextract0 = getInstr ( <STR_LIT> , dl , <STR_LIT> , { Vor4 , InstrC0 } , DAG ) ; SDValue C32 = DAG . getTargetConstant ( <NUM_LIT> , dl , <STR_LIT> ) ; SDValue InstrC32 = getInstr ( <STR_LIT> , dl , <STR_LIT> , C32 , DAG ) ; SDValue Vextract1 = getInstr ( <STR_LIT> , dl , <STR_LIT> , { Vor4 , InstrC32 } , DAG ) ; SDValue Combine0 = getInstr ( <STR_LIT> , dl , <STR_LIT> , { Vextract1 , Vextract0 } , DAG ) ; SDValue C64 = DAG . getTargetConstant ( <NUM_LIT> , dl , <STR_LIT> ) ; SDValue InstrC64 = getInstr ( <STR_LIT> , dl , <STR_LIT> , C64 , DAG ) ; SDValue Vextract2 = getInstr ( <STR_LIT> , dl , <STR_LIT> , { Vor4 , InstrC64 } , DAG ) ; SDValue C96 = DAG . getTargetConstant ( <NUM_LIT> , dl , <STR_LIT> ) ; SDValue InstrC96 = getInstr ( <STR_LIT> , dl , <STR_LIT> , C96 , DAG ) ; SDValue Vextract3 = getInstr ( <STR_LIT> , dl , <STR_LIT> , { Vor4 , InstrC96 } , DAG ) ; SDValue Combine1 = getInstr ( <STR_LIT> , dl , <STR_LIT> , { Vextract3 , Vextract2 } , DAG ) ; StoreSDNode * ST = cast < StoreSDNode > ( Op . getNode ( ) ) ; SDValue C8 = DAG . getTargetConstant (


<s> } unsigned Offset = State . AllocateStack ( <NUM_LIT> , <NUM_LIT> ) ; State . addLoc ( CCValAssign :: getMem ( ValNo , ValVT , Offset , LocVT , LocInfo ) ) ; return false


<s> Function * createInitOrFiniKernelFunction ( Module & M , bool IsCtor ) { StringRef InitOrFiniKernelName = <STR_LIT> ; if ( ! IsCtor ) InitOrFiniKernelName = <STR_LIT> ; Function * InitOrFiniKernel = Function :: createWithDefaultAttr ( FunctionType :: get ( Type :: getVoidTy ( M . getContext ( ) ) , false ) , GlobalValue :: ExternalLinkage , <NUM_LIT> , InitOrFiniKernelName , & M ) ; BasicBlock * InitOrFiniKernelBB = BasicBlock :: Create ( M . getContext ( ) , <STR_LIT> , InitOrFiniKernel ) ; ReturnInst :: Create ( M . getContext ( ) , InitOrFiniKernelBB ) ; InitOrFiniKernel -> setCallingConv ( CallingConv :: <ISA_LIT>_KERNEL ) ; if ( IsCtor ) InitOrFiniKernel


<s> static VEC ( int , heap ) * funcdef_nos ; static void output_deferred_profile_counters ( void ) { unsigned int i ; int align , n ; if ( VEC_empty ( int , funcdef_nos ) ) return ; data_section ( ) ; align = MIN ( BIGGEST_ALIGNMENT , LONG_TYPE_SIZE


<s> static SDValue combineSetCCEFLAGS ( SDValue EFLAGS , <STR_LIT> & CC , SelectionDAG & DAG , const <ISA_LIT>Subtarget & Subtarget ) { if ( CC == <STR_LIT> ) if ( SDValue Flags = combineCarryThroughADD ( EFLAGS , DAG ) ) return Flags ; if ( SDValue R = checkBoolTestSetCCCombine ( EFLAGS , CC ) ) return R ; return combineSetCCAtomicArith ( EFLAGS , CC , DAG


<s> void <ISA_LIT>AsmPrinter :: printThumbAddrModeSPOperand ( const MachineInstr * MI , int Op , raw_ostream & O ) { const MachineOperand & MO1 = MI ->


<s> case <STR_LIT> : return LowerSELECT_CC ( Op , DAG , * this , hasHardQuad ) ; case <STR_LIT> : return LowerVASTART ( Op , DAG , * this ) ; case <STR_LIT> : return LowerVAARG ( Op , DAG ) ; case <STR_LIT> : return LowerDYNAMIC_STACKALLOC ( Op , DAG ) ; case <STR_LIT> : return LowerF128Load ( Op , DAG ) ; case <STR_LIT> : return LowerF128Store ( Op , DAG ) ; case <STR_LIT> : return LowerF128Op ( Op , DAG , getLibcallName ( RTLIB :: ADD_F128 ) , <NUM_LIT> ) ; case <STR_LIT> : return LowerF128Op ( Op , DAG , getLibcallName ( RTLIB :: SUB_F128 ) , <NUM_LIT> ) ; case <STR_LIT> : return LowerF128Op ( Op , DAG , getLibcallName ( RTLIB :: MUL_F128 ) , <NUM_LIT> ) ; case <STR_LIT> : return LowerF128Op ( Op , DAG , getLibcallName ( RTLIB :: DIV_F128 ) , <NUM_LIT> ) ; case <STR_LIT> : return LowerF128Op ( Op , DAG , getLibcallName ( RTLIB :: SQRT_F128 ) , <NUM_LIT> ) ; case <STR_LIT> : return LowerFNEG ( Op , DAG , * this , is64Bit ) ; case <STR_LIT> : return LowerFABS ( Op ,


<s> unsigned ByValSizeInBytes = Flags . getByValSize ( ) ; unsigned OffsetInBytes = <NUM_LIT> ; unsigned RegSizeInBytes = Subtarget . getGPRSizeInBytes ( ) ; unsigned Alignment = std :: min ( Flags . getByValAlign ( ) , RegSizeInBytes ) ; EVT PtrTy = getPointerTy ( DAG . getDataLayout ( ) ) , RegTy = <STR_LIT> ( RegSizeInBytes * <NUM_LIT> ) ; unsigned NumRegs = LastReg - FirstReg ; if ( NumRegs ) { ArrayRef < MCPhysReg > ArgRegs = ABI . GetByValArgRegs ( ) ; bool LeftoverBytes = ( NumRegs * RegSizeInBytes > ByValSizeInBytes ) ; unsigned I = <NUM_LIT> ; for ( ; I < NumRegs - LeftoverBytes ; ++ I , OffsetInBytes += RegSizeInBytes ) { SDValue LoadPtr = DAG . getNode ( <STR_LIT> , DL , PtrTy , Arg , DAG . getConstant ( OffsetInBytes , DL , PtrTy ) ) ; SDValue LoadVal = DAG . getLoad ( RegTy , DL , Chain , LoadPtr , MachinePointerInfo ( ) , Alignment ) ; MemOpChains . push_back ( LoadVal . getValue ( <NUM_LIT> ) ) ; unsigned ArgReg = ArgRegs [ FirstReg + I ] ; RegsToPass . push_back ( std :: make_pair ( ArgReg , LoadVal ) ) ; } if ( ByValSizeInBytes == OffsetInBytes ) return ; if ( LeftoverBytes ) { SDValue Val ; for ( unsigned LoadSizeInBytes = RegSizeInBytes / <NUM_LIT> , TotalBytesLoaded = <NUM_LIT> ; OffsetInBytes < ByValSizeInBytes ; LoadSizeInBytes /= <NUM_LIT> ) { unsigned RemainingSizeInBytes = ByValSizeInBytes - OffsetInBytes ; if ( RemainingSizeInBytes < LoadSizeInBytes )


<s> ConstantPools -> emitForCurrentSection ( Streamer )


<s> assert ( MF . getName ( ) == <STR_LIT> && <STR_LIT> ) ; populateThunk ( MF , <STR_LIT> ) ; } else { if ( MF . getName ( ) == EAXThunkName ) populateThunk ( MF , <STR_LIT> ) ; else if ( MF . getName ( ) == ECXThunkName ) populateThunk ( MF , <STR_LIT> ) ; else if ( MF . getName ( ) == EDXThunkName ) populateThunk ( MF , <STR_LIT> ) ; else if ( MF . getName ( ) == EDIThunkName ) populateThunk ( MF , <STR_LIT> ) ; else llvm_unreachable ( <STR_LIT>


<s> void addMemoryRegisterOffset64Operands ( MCInst & Inst , unsigned N ) { addMemoryRegisterOffsetOperands ( Inst , N ,


<s> void <ISA_LIT>InstrInfo :: storeRegToStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned SrcReg , bool IsKill , int FI , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { DebugLoc DL ; if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; if ( ! <STR_LIT> . hasSubClassEq ( RC


<s> f_ndx = build_decl ( FIELD_DECL , get_identifier ( <STR_LIT> ) , integer_type_node ) ; DECL_FIELD_CONTEXT ( f_stk ) = record ; DECL_FIELD_CONTEXT ( f_reg ) = record ; DECL_FIELD_CONTEXT ( f_ndx ) = record ; TREE_CHAIN ( record ) = type_decl ; TYPE_NAME ( record


<s> int EndOffset = BeginOffset + NumSubElts * EltBitWidth ; if ( BeginOffset <= BitOffset && BitOffset < EndOffset ) { BitOffset -= BeginOffset ; V = VInner ; } else { V = VOuter ; } continue ; } } break ; } assert ( ( BitOffset % NumEltBits ) == <NUM_LIT> && <STR_LIT> ) ; BroadcastIdx = BitOffset / NumEltBits ; bool BitCastSrc = V . getScalarValueSizeInBits ( ) != NumEltBits ; if ( BitCastSrc && VT . isInteger ( ) ) if ( SDValue TruncBroadcast = lowerShuffleAsTruncBroadcast ( DL , VT , V , BroadcastIdx , Subtarget , DAG ) ) return TruncBroadcast ; MVT BroadcastVT = VT ; if ( ! BitCastSrc && ( ( V . getOpcode ( ) == <STR_LIT> && V . hasOneUse ( ) ) || ( V . getOpcode ( ) == <STR_LIT> && BroadcastIdx == <NUM_LIT> ) ) ) { V = V . getOperand ( BroadcastIdx ) ; if ( ! BroadcastFromReg && ! isShuffleFoldableLoad ( V ) ) return SDValue ( ) ; } else if ( <STR_LIT> ( V . getNode ( ) ) && cast < LoadSDNode > ( V ) -> isSimple ( ) ) { if ( ! Subtarget . is64Bit ( ) && VT . getScalarType ( ) == <STR_LIT> ) { BroadcastVT = <STR_LIT> ( <STR_LIT> , VT . getVectorNumElements ( ) ) ; Opcode = ( BroadcastVT . is128BitVector ( ) && ! Subtarget . hasAVX2 ( ) ) ? <STR_LIT> : Opcode ; } LoadSDNode * Ld = cast < LoadSDNode > ( V ) ; SDValue BaseAddr = Ld -> getOperand ( <NUM_LIT> ) ; EVT SVT = BroadcastVT . getScalarType ( ) ; unsigned Offset = BroadcastIdx * SVT . getStoreSize ( ) ; assert ( ( int ) ( Offset * <NUM_LIT> ) == BitOffset && <STR_LIT> ) ; SDValue NewAddr = DAG . getMemBasePlusOffset ( BaseAddr , Offset , DL ) ; V = DAG . getLoad ( SVT , DL , Ld -> getChain ( ) , NewAddr , DAG . getMachineFunction ( ) . getMachineMemOperand ( Ld -> getMemOperand ( ) , Offset , SVT . getStoreSize ( ) ) ) ; DAG . makeEquivalentMemoryOrdering ( Ld , V ) ; } else if ( ! BroadcastFromReg ) { return SDValue ( ) ; } else if ( BitOffset


<s> unsigned Opc = I -> second . first ; unsigned Index = I -> second . second & TB_INDEX_MASK ; bool FoldedLoad = I -> second . second & TB_FOLDED_LOAD ; bool FoldedStore = I -> second . second & TB_FOLDED_STORE ; const MCInstrDesc & MCID = get ( Opc ) ; MachineFunction & MF = DAG . getMachineFunction ( ) ; const TargetRegisterClass * RC = getRegClass ( MCID , Index , & RI , MF ) ; unsigned NumDefs = MCID . NumDefs ; std :: vector < SDValue > AddrOps ; std :: vector < SDValue > BeforeOps ; std :: vector < SDValue > AfterOps ; DebugLoc dl = N -> getDebugLoc ( ) ; unsigned NumOps = N -> getNumOperands ( ) ; for ( unsigned i = <NUM_LIT> ; i != NumOps - <NUM_LIT> ; ++ i ) { SDValue Op = N -> getOperand ( i ) ; if ( i >= Index - NumDefs && i < Index - NumDefs + <STR_LIT> ) AddrOps . push_back ( Op ) ; else if ( i < Index - NumDefs ) BeforeOps . push_back ( Op ) ; else if ( i > Index - NumDefs ) AfterOps . push_back ( Op ) ; } SDValue Chain = N -> getOperand ( NumOps - <NUM_LIT> ) ; AddrOps . push_back ( Chain ) ; SDNode * Load = <NUM_LIT> ; if ( FoldedLoad ) { EVT VT = * RC -> vt_begin ( ) ; std :: pair < MachineInstr :: mmo_iterator , MachineInstr :: mmo_iterator > MMOs = MF . extractLoadMemRefs ( cast < MachineSDNode > ( N ) -> memoperands_begin ( ) , cast < MachineSDNode > ( N ) -> memoperands_end ( ) ) ; if ( ! ( * MMOs . first ) && RC == & <STR_LIT> && ! TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . isUnalignedMemAccessFast ( ) ) return false ; unsigned Alignment = RC -> getSize ( ) == <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ; bool isAligned = ( * MMOs . first ) && ( * MMOs . first ) -> getAlignment ( )


<s> static bool isMOVSHDUPMask ( ArrayRef < int > Mask , EVT VT , const <ISA_LIT>Subtarget * Subtarget ) { if ( ! Subtarget -> hasSSE3 ( ) ) return false ; unsigned NumElems = VT . getVectorNumElements (


<s> SDValue Zero = DAG . getConstant ( <NUM_LIT> , VT ) ; SDVTList VTs = DAG . getVTList ( VT , <STR_LIT> , <STR_LIT> ) ; SDValue Swap = DAG . getAtomicCmpSwap ( <STR_LIT> , dl , VT , VTs , Node -> getOperand ( <NUM_LIT> ) , Node -> getOperand ( <NUM_LIT> ) , Zero , Zero , cast < AtomicSDNode > ( Node ) -> getMemOperand ( ) , cast < AtomicSDNode > ( Node ) -> getOrdering ( ) , cast < AtomicSDNode > ( Node ) -> getOrdering (

) , cast < AtomicSDNode > ( Node ) -> getSynchScope ( ) ) ;


<s> CodeModel :: Model CModel = TM . getCodeModel ( ) ; MachineMemOperand * MMO = FuncInfo . MF -> getMachineMemOperand ( MachinePointerInfo :: getConstantPool ( * FuncInfo . MF ) , MachineMemOperand :: MOLoad , ( VT == <STR_LIT> ) ? <NUM_LIT> : <NUM_LIT> , Align ) ; unsigned Opc = ( VT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; unsigned TmpReg = createResultReg ( & <STR_LIT> ) ; <ISA_LIT>FuncInfo -> setUsesTOCBasePtr ( ) ; if ( CModel == CodeModel :: Small || CModel == CodeModel :: JITDefault ) { BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , TmpReg ) . addConstantPoolIndex ( Idx ) . addReg ( <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , DestReg ) . addImm ( <NUM_LIT> ) . addReg ( TmpReg ) . addMemOperand ( MMO ) ; } else { BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get

( <STR_LIT> ) , TmpReg ) . addReg ( <STR_LIT> ) . addConstantPoolIndex ( Idx ) ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return QRI . Subtarget . hasV4TOps ( ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> virtual void getAnalysisUsage ( AnalysisUsage & AU )


<s> int one_bit_count ; one_bit_count = popcount_hwi ( ( unsigned HOST_WIDE_INT ) (


<s> InstOffset += HII -> nonDbgBBSize ( & B ) * HEXAGON_INSTR_SIZE ; MachineBasicBlock * TBB = NULL , * FBB = NULL ; SmallVector < MachineOperand , <NUM_LIT> > Cond ; if ( HII -> analyzeBranch ( B , TBB , FBB , Cond , false ) ) { if ( HII -> isNewValueJump ( * FirstTerm ) ) TBB = FirstTerm -> getOperand ( HII -> getCExtOpNum ( * FirstTerm ) ) . getMBB ( ) ; } if ( TBB && & MI == & * FirstTerm ) { Distance = std :: abs ( ( long long ) InstOffset - BlockToInstOffset [ TBB ] ) + BranchRelaxSafetyBuffer ; return ! HII -> isJumpWithinBranchRange ( * FirstTerm , Distance ) ; } if ( FBB ) { auto SecondTerm = std :: next ( FirstTerm ) ; assert ( SecondTerm != B . instr_end ( ) && ( SecondTerm -> isBranch ( ) || SecondTerm -> isCall ( ) ) && <STR_LIT> ) ; if ( & MI != & * SecondTerm )


<s> return new Emitter < JITCodeEmitter > (


<s> if ( ! Disable<ISA_LIT>CFGOpt ) addPass (

create<ISA_LIT>CFGOptimizer ( ) , false ) ;


<s> return ( __m128 ) __builtin_ia32_loadss (


<s> if ( Predicate_i16immSExt8 ( Val . getNode ( ) ) ) Opc = <STR_LIT> ; else Opc = <STR_LIT> ; } else Opc = <STR_LIT> ; } break ; case <STR_LIT> : if ( isInc ) Opc = <STR_LIT> ; else if ( isDec ) Opc = <STR_LIT> ; else if ( isSub ) { if ( isCN ) { if ( Predicate_i32immSExt8 ( Val . getNode ( ) ) ) Opc = <STR_LIT> ; else Opc = <STR_LIT> ; } else Opc = <STR_LIT> ; } else { if ( isCN ) { if ( Predicate_i32immSExt8 ( Val . getNode ( ) ) ) Opc = <STR_LIT> ; else Opc = <STR_LIT> ; } else Opc = <STR_LIT> ; } break ; case <STR_LIT> : if ( isInc ) Opc = <STR_LIT> ; else if ( isDec ) Opc = <STR_LIT> ; else if ( isSub ) { Opc = <STR_LIT> ; if ( isCN ) { if ( Predicate_i64immSExt8 ( Val . getNode ( ) ) ) Opc = <STR_LIT> ; else if ( Predicate_i64immSExt32 ( Val . getNode ( ) ) ) Opc = <STR_LIT> ; } } else { Opc = <STR_LIT> ; if ( isCN ) { if ( Predicate_i64immSExt8 ( Val . getNode ( ) ) ) Opc = <STR_LIT> ; else if ( Predicate_i64immSExt32 ( Val . getNode ( ) ) ) Opc = <STR_LIT> ; } } break ; } DebugLoc dl = Node -> getDebugLoc ( ) ; SDValue Undef = SDValue ( CurDAG -> getTargetNode ( TargetInstrInfo :: IMPLICIT_DEF , dl , NVT ) , <NUM_LIT> ) ; SDValue MemOp = CurDAG -> getMemOperand ( cast < MemSDNode >


<s> SDValue <ISA_LIT>TargetLowering :: LowerBITCAST ( SDValue Op , SelectionDAG & DAG ) const { SDLoc dl ( Op ) ; SDValue Op0 = Op -> getOperand ( <NUM_LIT> ) ; if ( ! EnableQuadPrecision || ( Op . getValueType ( ) != <STR_LIT> ) || ( Op0 . getOpcode ( ) != <STR_LIT> ) || ( Op0 . getOperand ( <NUM_LIT> ) . getValueType ( ) !=

<STR_LIT> ) || ( Op0 . getOperand ( <NUM_LIT> ) . getValueType ( ) != <STR_LIT> ) ) return SDValue ( ) ;


<s> MachineFunction & MF = MIRBuilder . getMF ( ) ; const Function & F = MF . getFunction ( ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; auto & DL = F . getParent ( ) -> getDataLayout ( ) ; SmallVector < ArgInfo , <NUM_LIT> > OutArgs ; for ( auto & OrigArg : Info . OrigArgs ) { splitToValueTypes ( OrigArg , OutArgs , DL , Info . CallConv ) ; } SmallVector < ArgInfo , <NUM_LIT> > InArgs ; if ( ! Info . OrigRet . Ty -> isVoidTy ( ) ) splitToValueTypes ( Info . OrigRet , InArgs , DL , Info . CallConv ) ; MachineInstrBuilder CallSeqStart ; CallSeqStart = MIRBuilder . buildInstr ( <STR_LIT> ) ; unsigned Opc = Info . Callee . isReg ( ) ? <STR_LIT> : <STR_LIT> ; auto MIB = MIRBuilder . buildInstrNoInsert ( Opc ) ; MIB . add ( Info . Callee ) ; const uint32_t * Mask ; const <ISA_LIT>Subtarget & Subtarget = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; const auto * TRI = Subtarget . getRegisterInfo ( ) ; OutgoingValueAssigner ArgAssigner ( CC_<ISA_LIT> ) ; OutgoingArgHandler Handler ( MIRBuilder , MRI , MIB


<s> static tree aarch64_embedded_comparison_type ( stmt_vec_info stmt_info ) { if ( auto * assign = dyn_cast < gassign * > ( stmt_info -> stmt ) ) if ( gimple_assign_rhs_code ( assign ) == COND_EXPR ) { tree cond = gimple_assign_rhs1 ( assign )


<s> static SDValue LowerToTLSGeneralDynamicModel32 ( GlobalAddressSDNode * GA , SelectionDAG & DAG , const MVT PtrVT ) { SDValue InFlag ; DebugLoc dl = GA -> getDebugLoc ( ) ; SDValue Chain = DAG . getCopyToReg ( DAG . getEntryNode ( ) , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , DebugLoc :: getUnknownLoc


<s> return ( uint16x4_t ) __builtin_aarch64_sqmovunv4si


<s> bool hasReservedCallFrame ( const MachineFunction & MF ) const override { return true


<s> static int arm_get_strip_length ( int c ) { switch ( c


<s> if ( TARGET_A24 ) ofs = ( ofs + <NUM_LIT> ) & ~ <NUM_LIT> ; fprintf ( stderr , <STR_LIT> , from , to , ofs ) ; return ofs


<s> if ( MAYBE_MMX_CLASS_P ( class ) && CONSTANT_P ( x ) ) return NO_REGS ; if ( MAYBE_SSE_CLASS_P ( class ) && CONSTANT_P ( x ) ) return NO_REGS ; if ( GET_CODE ( x ) == PLUS ) return reg_class_subset_p ( class , GENERAL_REGS ) ? class : NO_REGS ; if ( GET_MODE ( x ) == QImode && ! CONSTANT_P ( x ) ) { if ( reg_class_subset_p ( class , Q_REGS ) ) return class ; if ( reg_class_subset_p ( Q_REGS , class ) ) return


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; case <STR_LIT> : case <STR_LIT> : return MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . isX18Reserved ( ) ; case <STR_LIT> : case <STR_LIT> : return TFI -> hasFP ( MF ) || TT . isOSDarwin ( ) ; case <STR_LIT>


<s> void mcore_override_options ( void )


<s> __v2du lshift ; __vector __bool long long shmask ; const __v2du shmax = { <NUM_LIT> , <NUM_LIT> } ; __v2du result ; lshift = vec_splat ( ( __v2du ) __B , <NUM_LIT> ) ; shmask = vec_cmplt ( lshift , shmax ) ; result = vec_sl ( ( __v2du ) __A


<s> return ( int32x2_t ) __builtin_neon_vqnegv2si


<s> default : return AsmPrinter :: PrintAsmOperand ( MI , OpNo , AsmVariant , ExtraCode , O ) ; case 'X' : if ( ( MO . getType ( ) ) != MachineOperand :: MO_Immediate ) return true ; O << <STR_LIT> << std :: hex << MO . getImm ( ) ; return false ; case 'x' : if ( ( MO . getType ( ) ) != MachineOperand :: MO_Immediate ) return true ; O << <STR_LIT> << std :: hex << ( MO . getImm ( ) &


<s> static __inline vec_int4 spu_mulh ( vec_short8 a , vec_short8 b ) { return ( ( vec_int4 ) ( si_mpyh ( ( qword ) ( a ) , ( qword ) ( b )


<s> df_ref ref ; for ( ref = DF_INSN_INFO_DEFS ( insn_info ) ; ref ; ref = DF_REF_NEXT_LOC ( ref ) ) if ( DF_REF_REGNO ( ref ) == regno ) return true ; if ( type == TYPE_LOAD || type == TYPE_FPLOAD || type == TYPE_VECLOAD ) for ( ref = DF_INSN_INFO_USES ( insn_info ) ; ref ; ref = DF_REF_NEXT_LOC ( ref ) ) if ( DF_REF_REGNO ( ref ) == regno ) return true ; return false


<s> const <ISA_LIT>FrameLowering * TFI = getFrameLowering ( MF ) ; return TFI -> hasFP ( MF ) ? <STR_LIT> :


<s> if ( <STR_LIT> ( InOp . getNode ( ) ) || <STR_LIT> ( InOp . getNode ( ) ) ) { SmallVector < SDValue , <NUM_LIT> > Ops ; for ( unsigned i = <NUM_LIT> ; i < InNumElts ; ++ i ) Ops . push_back ( InOp . getOperand ( i ) ) ; EVT EltVT = InOp . getOperand ( <NUM_LIT> ) . getValueType ( ) ; SDValue FillVal = FillWithZeroes ? DAG . getConstant ( <NUM_LIT> , dl , EltVT ) : DAG . getUNDEF ( EltVT ) ; for ( unsigned i = <NUM_LIT> ; i < WidenNumElts - InNumElts ; ++ i ) Ops . push_back ( FillVal ) ; return DAG . getBuildVector ( NVT , dl , Ops ) ; } SDValue FillVal = FillWithZeroes ? DAG . getConstant ( <NUM_LIT> , dl , NVT ) : DAG . getUNDEF (


<s> auto OpcodeN = N -> getOpcode ( ) ; auto OpcodeN0 = N0 . getOpcode ( ) ; if ( ! ( ( OpcodeN == <STR_LIT> && OpcodeN0 == <STR_LIT> ) || ( OpcodeN == <STR_LIT> && OpcodeN0 == <STR_LIT> ) ) ) return SDValue ( ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; EVT InVT = N0 . getValueType ( ) ; if ( N0 . getResNo ( ) != <NUM_LIT> || InVT != <STR_LIT> || ! ( VT == <STR_LIT> || VT == <STR_LIT> ) ) return SDValue ( ) ; SDVTList NodeTys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; auto DivRemOpcode = OpcodeN0 == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; SDValue R = DAG . getNode ( DivRemOpcode , SDLoc ( N ) , NodeTys , N0 . getOperand ( <NUM_LIT> ) , N0 . getOperand ( <NUM_LIT> ) ) ; DAG . ReplaceAllUsesOfValueWith ( N0 . getValue ( <NUM_LIT> ) ,


<s> std :: vector < <ISA_LIT>Exception * > & getSubExceptions ( ) { return


<s> static bool LLVM_ATTRIBUTE_UNUSED checkFeature ( MCSubtargetInfo * STI


<s> bool is<ISA_LIT>SOImmNeg ( ) const { if ( ! isImm ( ) ) return false ; const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; if ( ! CE ) return false ; int64_t Value = CE -> getValue ( ) ; return <STR_LIT> ( Value ) == - <NUM_LIT> && <STR_LIT> ( -


<s> bool <ISA_LIT>AddMissingPrototypes :: runOnModule ( Module & M ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; std :: vector < std :: pair < Function * , Function * >> Replacements ; for ( Function & F : M ) { if ( ! F . isDeclaration ( ) || ! F . hasFnAttribute ( <STR_LIT> ) ) continue ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << F . getName ( ) << <STR_LIT> ) ; if ( ! F . isVarArg ( ) ) report_fatal_error ( <STR_LIT> + F . getName ( ) ) ; if ( F . getFunctionType ( ) -> getNumParams ( ) != <NUM_LIT> ) report_fatal_error ( <STR_LIT> + F . getName ( ) ) ; FunctionType * NewType = nullptr ; Function * NewF = nullptr ; for ( Use & U : F . uses ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << F . getName


<s> unsigned <ISA_LIT>MCCodeEmitter :: getAVOperandEncoding ( const MCInst & MI , unsigned OpNo , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { unsigned Reg = MI . getOperand ( OpNo ) . getReg ( ) ; uint64_t Enc = MRI . getEncodingValue ( Reg ) ; if ( MRI . getRegClass ( <STR_LIT> ) . contains ( Reg ) || MRI . getRegClass ( <STR_LIT> ) . contains ( Reg )


<s> void <ISA_LIT>DAGToDAGISel :: PostprocessISelDAG ( ) { const <ISA_LIT>TargetLowering & Lowering = * static_cast < const <ISA_LIT>TargetLowering * > ( getTargetLowering ( ) ) ; bool IsModified = false ; do { IsModified = false ; SelectionDAG :: allnodes_iterator Position = CurDAG


<s> if ( getLexer ( ) . getTok ( ) . getIntVal ( ) != <NUM_LIT> ) return ! ErrorAndEatStatement ( getLexer ( ) . getLoc ( ) , <STR_LIT> ) ; Parser . Lex ( ) ; if ( ! getLexer ( ) . is ( AsmToken :: Identifier ) || ! getLexer ( ) . getTok ( ) . getIdentifier ( ) . startswith ( <STR_LIT> ) ) return ! ErrorAndEatStatement ( getLexer ( ) . getLoc ( ) , <STR_LIT> ) ; const char * BroadcastPrimitive = StringSwitch < const char * > ( getLexer ( ) . getTok ( ) . getIdentifier ( ) ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( nullptr ) ; if ( ! BroadcastPrimitive ) return ! ErrorAndEatStatement ( getLexer ( ) . getLoc ( ) , <STR_LIT> ) ; Parser . Lex ( ) ; if ( ! getLexer ( ) . is ( AsmToken :: RCurly ) ) return ! ErrorAndEatStatement ( getLexer ( ) . getLoc ( ) , <STR_LIT> ) ; Parser . Lex ( ) ; Operands . push_back ( <STR_LIT> ( BroadcastPrimitive , consumedToken ) ) ; return true ; } else { Operands . push_back ( <STR_LIT> ( <STR_LIT> , consumedToken ) ) ; if ( std :: unique_ptr < <ISA_LIT>Operand > Op = ParseOperand ( ) ) { Operands . push_back ( std :: move ( Op ) ) ; if ( ! getLexer ( ) . is ( AsmToken :: RCurly ) ) return ! ErrorAndEatStatement ( getLexer ( ) . getLoc ( ) , <STR_LIT> ) ; Operands . push_back ( <STR_LIT> ( <STR_LIT> , consumeToken ( ) ) ) ; if ( getLexer ( ) . is ( AsmToken :: LCurly ) ) { Operands . push_back ( <STR_LIT> ( <STR_LIT> , consumeToken (


<s> for ( unsigned i = <NUM_LIT> , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) { const MachineOperand & MO = MI -> getOperand ( i ) ; if ( ! MO . isReg ( ) || MO . isImplicit ( ) ) continue ; unsigned Reg = MO . getReg ( ) ; if ( Reg == <NUM_LIT> ||


<s> rtl_opt_pass * make_pass_resolve_sw_modes ( gcc :: context * ctxt


<s> uint64_t <ISA_LIT>MCCodeEmitter :: getBDRAddr12Encoding ( const MCInst & MI , unsigned OpNum , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { uint64_t Base = getMachineOpValue ( MI , MI . getOperand ( OpNum ) , Fixups , STI ) ; uint64_t Disp = getDispOpValue ( MI , OpNum + <NUM_LIT> , Fixups , <STR_LIT> ) ; uint64_t Len = getMachineOpValue ( MI , MI . getOperand ( OpNum + <NUM_LIT> )


<s> if ( RDFLimit . getPosition ( ) ) { if ( RDFCount >= RDFLimit ) return false ; RDFCount ++ ; } MDT = & getAnalysis < MachineDominatorTree > ( ) ; const auto & MDF = getAnalysis < MachineDominanceFrontier > ( ) ; const auto & HII = * MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getInstrInfo ( ) ; const auto & HRI = * MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getRegisterInfo ( ) ; MRI = & MF . getRegInfo ( ) ; bool Changed ; if ( RDFDump ) MF . print ( dbgs ( ) << <STR_LIT> << getPassName ( ) << <STR_LIT> , nullptr ) ; <ISA_LIT>RegisterAliasInfo HAI ( HRI ) ; TargetOperandInfo TOI ( HII ) ; DataFlowGraph G ( MF , HII , HRI , * MDT , MDF , HAI , TOI ) ; G . build ( ) ; if ( RDFDump ) dbgs ( ) << <STR_LIT> << MF . getName ( ) << '\n' << PrintNode < FuncNode * > ( G . getFunc ( ) , G ) << '\n' ; <ISA_LIT>CP CP ( G ) ; CP . trace ( RDFDump ) ; Changed = CP . run ( ) ; if ( RDFDump ) dbgs ( ) << <STR_LIT> << MF . getName ( ) << '\n' << PrintNode < FuncNode * > ( G . getFunc ( ) , G ) << '\n' ; <ISA_LIT>DCE DCE ( G , * MRI ) ; DCE . trace (


<s> <ISA_LIT>GenSubtargetInfo ( TT , GPU , FS ) , <ISA_LIT>CommonSubtarget ( TT , getFeatureBits ( ) ) , InstrInfo ( * this ) , FrameLowering ( TargetFrameLowering :: StackGrowsUp , getStackAlignment ( ) , <NUM_LIT> ) , FMA ( false ) , CaymanISA ( false ) , CFALUBug ( false ) , DX10Clamp ( false ) , HasVertexCache ( false ) , <ISA_LIT>ALUInst ( false ) , FP64 ( false ) , TexVTXClauseSize ( <NUM_LIT> ) , Gen ( <ISA_LIT> ) , TLInfo ( TM

, initializeSubtargetDependencies ( TT , GPU , FS ) ) , InstrItins ( getInstrItineraryForCPU ( GPU ) ) , AS ( <STR_LIT> ( TT ) ) {


<s> void <ISA_LIT>LongBranch :: relaxBranches ( ) { SmallVector < TerminatorInfo , <NUM_LIT> > :: iterator TI = Terminators . begin ( ) ; BlockPosition Position ( MF -> getAlignment ( ) ) ; for ( SmallVector < MBBInfo , <NUM_LIT> > :: iterator BI = MBBs . begin ( ) , BE = MBBs . end ( ) ; BI != BE ; ++ BI ) { skipNonTerminators ( Position , * BI ) ; for ( unsigned BTI = <NUM_LIT> , BTE = BI -> NumTerminators ; BTI != BTE ; ++ BTI ) { assert ( Position . Address <= TI -> Address && <STR_LIT> ) ; if ( mustRelaxBranch ( * TI , Position . Address ) ) relaxBranch ( * TI ) ; skipTerminator ( Position , * TI


<s> static void ready_reorder ( rtx * ready , int nready ) { SCHED_REORDER ( ready , nready )


<s> if ( TheTriple . isOSBinFormatMachO ( ) ) { MachO :: CPUSubType<ISA_LIT> CS = StringSwitch < MachO :: CPUSubType<ISA_LIT> > ( TheTriple . getArchName ( ) ) . Case ( <STR_LIT> , MachO :: CPU_SUBTYPE_<ISA_LIT>_64_H ) . Default ( MachO :: CPU_SUBTYPE_<ISA_LIT>_64_ALL ) ; return new Darwin<ISA_LIT>_64AsmBackend ( T , MRI , CPU , CS ) ; } if ( TheTriple . isOSWindows ( ) && TheTriple . isOSBinFormatCOFF ( )

) return new Windows<ISA_LIT>AsmBackend ( T , true , CPU ) ;


<s> DEBUG ( dbgs ( ) << <STR_LIT> << * MI << <STR_LIT> ) ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; BuildMI ( * MI -> getParent ( ) , MI , MI -> getDebugLoc ( ) , TII -> get ( getCmpForPseudo ( MI ) ) ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . add ( MI -> getOperand ( <NUM_LIT> ) ) ; BuildMI ( * MI -> getParent ( ) , MI , MI -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addMBB ( MI -> getOperand ( <NUM_LIT> ) . getMBB ( ) ) . addImm ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; MI -> eraseFromParent


<s> Inst . addOperand ( MCOperand :: CreateReg ( getGPRMM16Reg ( )


<s> State ( IES_PLUS ) , PrevState ( IES_ERROR ) , BaseReg ( <NUM_LIT> ) , IndexReg ( <NUM_LIT> ) , TmpReg ( <NUM_LIT> ) , Scale ( <NUM_LIT> ) , Imm ( imm ) , Sym ( <NUM_LIT> ) , StopOnLBrac ( stoponlbrac ) , AddImmPrefix ( addimmprefix ) { Info . clear ( )


<s> unsigned <ISA_LIT>RegisterInfo :: findUnusedRegister ( const MachineRegisterInfo & MRI , const TargetRegisterClass * RC , const MachineFunction & MF ) const { for ( unsigned Reg : * RC ) if ( MRI . isAllocatable ( Reg ) && ! MRI . isPhysRegUsed ( Reg ) ) return Reg ; return


<s> bool applyAdjustICmpImmAndPred ( MachineInstr & MI , std :: pair < uint64_t , CmpInst :: Predicate > & MatchInfo , MachineIRBuilder & MIB , GISelChangeObserver & Observer ) { MIB . setInstrAndDebugLoc ( MI ) ; MachineOperand & RHS = MI . getOperand ( <NUM_LIT> ) ; MachineRegisterInfo & MRI = * MIB . getMRI ( ) ; auto Cst = MIB . buildConstant ( MRI . cloneVirtualRegister ( RHS . getReg ( ) ) , MatchInfo . first ) ; Observer . changingInstr ( MI ) ; RHS . setReg ( Cst -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; MI . getOperand ( <NUM_LIT> ) . setPredicate ( MatchInfo . second ) ; Observer . changedInstr ( MI


<s> return ( TII -> areMemAccessesTriviallyDisjoint ( * A , * B , AA ) || ! ( A

-> mayStore ( ) || B -> mayStore ( ) ) ) ;


<s> SDValue <ISA_LIT>TargetLowering :: LowerImplicitParameter ( SelectionDAG & DAG , EVT VT , const SDLoc & DL , unsigned DwordOffset ) const { unsigned ByteOffset = DwordOffset * <NUM_LIT> ; PointerType * PtrType = PointerType :: get ( VT . getTypeForEVT ( * DAG . getContext ( ) ) , <ISA_LIT>AS :: CONSTANT_BUFFER_0 ) ; assert ( isInt < <NUM_LIT> > ( ByteOffset ) ) ; return DAG . getLoad ( VT , DL , DAG . getEntryNode ( ) , DAG . getConstant ( ByteOffset , DL , <STR_LIT> ) , MachinePointerInfo ( ConstantPointerNull :: get ( PtrType ) ) , false , false


<s> default : assert ( <NUM_LIT> && <STR_LIT> ) ; case FCOND_F : case FCOND_T : return <STR_LIT> ; case FCOND_UN : case FCOND_OR : return <STR_LIT> ; case FCOND_EQ : case FCOND_NEQ : return <STR_LIT> ; case FCOND_UEQ : case FCOND_OGL : return <STR_LIT> ; case FCOND_OLT : case FCOND_UGE : return <STR_LIT> ; case FCOND_ULT : case FCOND_OGE : return <STR_LIT> ; case FCOND_OLE : case FCOND_UGT : return <STR_LIT> ; case FCOND_ULE : case FCOND_OGT : return


<s> if ( __builtin_expect ( __builtin_tbegin ( <NUM_LIT> ) , <NUM_LIT> ) ) return _HTM_TBEGIN_STARTED ; * _TEXASR_PTR ( TM_buff ) = __builtin_get_texasr ( ) ; * _TEXASRU_PTR ( TM_buff ) = __builtin_get_texasru ( ) ; * _TEXASRL_PTR ( TM_buff ) =


<s> Rd |= fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ; unsigned Rn = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned Rm = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned align = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned size = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned regs = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) + <NUM_LIT> ; align *= ( <NUM_LIT> << size ) ; if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , Rd , Address

, Decoder ) ) ) return MCDisassembler :: Fail ;


<s> unsigned Count = <NUM_LIT> ; BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addMBB ( TBB ) . addImm ( Cond [ <NUM_LIT> ] . getImm ( ) ) ; ++ Count ; if ( FBB ) { BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addMBB ( FBB ) ; ++ Count ; } return Count


<s> unsigned <ISA_LIT>RegisterInfo :: getFrameRegister ( const MachineFunction & MF )


<s> if ( Tok . isNot ( AsmToken :: Identifier ) ) return TokError ( <STR_LIT> ) ; StringRef SymbolName = Tok . getIdentifier ( ) ; MCSymbol * Sym = getContext ( ) . lookupSymbol ( SymbolName ) ; if ( ! Sym ) return TokError ( <STR_LIT> ) ; Parser . Lex ( ) ; if ( parseEOL ( ) ) return


<s> return const_cast < <ISA_LIT>TargetLowering * > (


<s> MVT VT = Op . getSimpleValueType ( ) ; SDLoc DL ( Op ) ; if ( cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) != <NUM_LIT> ) return DAG . getConstant ( <NUM_LIT> , DL , VT ) ; MachineFunction & MF = DAG . getMachineFunction ( ) ; const <ISA_LIT>MachineFunctionInfo * Info = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; if ( Info -> isEntryFunction ( ) ) return DAG . getConstant ( <NUM_LIT> , DL , VT ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; MFI . setReturnAddressIsTaken ( true ) ; const <ISA_LIT>RegisterInfo * TRI = getSubtarget ( ) -> getRegisterInfo ( ) ; Register Reg = MF . addLiveIn ( TRI -> getReturnAddressReg ( MF ) , getRegClassFor ( VT , Op . getNode ( ) -> isDivergent ( ) ) ) ; return DAG . getCopyFromReg ( DAG . getEntryNode (


<s> Opc1 = <STR_LIT> ; Opc2 = <STR_LIT> ; } if ( NeedFence ) BuildMI ( MBB , I , DL , TII -> get ( <STR_LIT> ) ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; MachineInstr * Addi ; if ( IsTLSGDPCREL ) { Addi = BuildMI ( MBB , I , DL , TII -> get ( Opc1 ) , GPR3 ) . addImm ( <NUM_LIT> ) ; } else { assert ( InReg != <STR_LIT> && <STR_LIT> ) ; Addi = BuildMI ( MBB , I , DL , TII -> get ( Opc1 ) , GPR3 ) . addReg ( InReg ) ; } Addi -> addOperand ( MI . getOperand ( <NUM_LIT> ) ) ; MachineBasicBlock :: iterator First = I ; -- First ; MachineInstr * Call = ( BuildMI ( MBB , I , DL , TII -> get ( Opc2 ) , GPR3 ) . addReg ( GPR3 ) ) ; if ( IsTLSGDPCREL ) Call -> addOperand ( MI . getOperand ( <NUM_LIT> ) ) ; else Call -> addOperand ( MI . getOperand ( <NUM_LIT> ) ) ; if ( NeedFence ) BuildMI ( MBB , I , DL , TII -> get ( <STR_LIT> ) ) . addImm ( <NUM_LIT>


<s> unsigned Opcode = MI -> getOpcode ( ) ; if ( Opcode == <STR_LIT> ) Opcode = <STR_LIT> ; int MCOpcode = ST . getInstrInfo ( ) -> pseudoToMCOpcode ( Opcode ) ; if ( MCOpcode == - <NUM_LIT> ) { LLVMContext & C = MI -> getParent ( ) -> getParent ( ) -> getFunction ( ) -> getContext ( ) ; C . emitError ( <STR_LIT> <STR_LIT> + Twine ( MI -> getOpcode ( ) ) ) ; } OutMI . setOpcode ( MCOpcode ) ; for ( const MachineOperand & MO : MI -> explicit_operands ( ) ) { MCOperand MCOp


<s> FunctionPass * llvm :: create<ISA_LIT>MemorySize


<s> bool <ISA_LIT>TargetLowering :: isIntDivCheap ( EVT VT , AttributeSet Attr


<s> O << <STR_LIT> ; getSymbol ( GVar ) -> print ( O , MAI ) ; O << <STR_LIT> ; return ; } if ( ETy -> isFloatingPointTy ( ) || ETy -> isIntOrPtrTy ( ) ) { O << <STR_LIT> ; O << getPTXFundamentalTypeStr ( ETy ) ; O << <STR_LIT> ; getSymbol ( GVar ) -> print ( O , MAI ) ; return ; } int64_t ElementSize = <NUM_LIT> ; switch ( ETy -> getTypeID ( ) ) { case Type :: StructTyID : case Type :: ArrayTyID : case Type :: FixedVectorTyID : ElementSize = DL . getTypeStoreSize ( ETy ) ; O << <STR_LIT> ; getSymbol ( GVar ) -> print ( O , MAI ) ; O << <STR_LIT> ; if ( ElementSize ) { O << ElementSize ; } O << <STR_LIT>