<s> SDValue Ptr = MaskLoad -> getBasePtr ( ) ; if ( Ptr -> getOpcode ( ) == <STR_LIT> || Ptr -> getOpcode ( ) ==

<STR_LIT> ) Ptr = Ptr -> getOperand ( <NUM_LIT> ) ;


<s> vmull_s32 ( int32x2_t a , int32x2_t b ) { int64x2_t result


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( MI . getOperand ( <NUM_LIT> ) . isImm ( ) && ! MI . getOperand ( <NUM_LIT> ) . getImm ( ) && MI . getOperand ( <NUM_LIT> ) . isFI ( ) ) { FrameIndex = MI . getOperand ( <NUM_LIT> ) . getIndex ( ) ; return MI . getOperand ( <NUM_LIT> ) . getReg


<s> if ( RegNo > <NUM_LIT> ) return MCDisassembler :: Fail ; return DecodeDPRRegisterClass ( Inst , RegNo , Address , Decoder


<s> void <ISA_LIT>FrameLowering :: determineCalleeSaves ( MachineFunction & MF , BitVector & SavedRegs , RegScavenger * RS ) const { assert ( false &&


<s> MachineSDNode :: mmo_iterator MemOp = MF -> allocateMemRefsArray ( <NUM_LIT> ) ; MemOp [ <NUM_LIT> ] = cast < MemSDNode > ( N ) -> getMemOperand ( ) ; cast < MachineSDNode > ( Result ) -> setMemRefs ( MemOp


<s> unsigned getVGPRPressureSet ( ) const { return


<s> const <ISA_LIT>InstrInfo * llvm :: create<ISA_LIT>16InstrInfo ( <ISA_LIT>TargetMachine


<s> void <ISA_LIT>WinCOFFStreamer :: EmitWinEHHandlerData ( ) { MCStreamer :: EmitWinEHHandlerData (


<s> <ISA_LIT>BlockRanges :: <ISA_LIT>BlockRanges ( MachineFunction & mf ) : MF ( mf ) , HST ( mf . getSubtarget < <ISA_LIT>Subtarget > ( ) ) , TII ( * HST . getInstrInfo ( ) ) , TRI ( * HST . getRegisterInfo ( ) ) , Reserved ( TRI . getReservedRegs ( mf ) ) { for ( auto I = TRI . regclass_begin ( ) , E = TRI . regclass_end ( ) ; I != E ; ++ I ) { auto * RC = * I ; if ( RC -> isAllocatable ( ) ) continue ; for ( unsigned R : * RC ) Reserved [ R ]


<s> void emitRRI ( unsigned Opcode , unsigned DstReg , unsigned SrcReg , int16_t Imm , SMLoc IDLoc

, SmallVectorImpl < MCInst > & Instructions ) {


<s> __asm__ ( <STR_LIT> : <STR_LIT> ( res ) : <STR_LIT> ( mm ) , <STR_LIT> ( mn ) ) ; return


<s> rtx t ; int align ; if ( sparc_addr_list == NULL_RTX && sparc_addr_diff_list == NULL_RTX ) return ; function_section ( current_function_decl ) ; align = floor_log2 ( FUNCTION_BOUNDARY / BITS_PER_UNIT ) ; if ( align > <NUM_LIT> ) ASM_OUTPUT_ALIGN ( asm_out_file , align ) ; for ( t = sparc_addr_list ; t ; t = XEXP ( t , <NUM_LIT> ) ) sparc_output_addr_vec ( XEXP ( t , <NUM_LIT> ) ) ; for ( t = sparc_addr_diff_list ; t ; t = XEXP ( t , <NUM_LIT> ) ) sparc_output_addr_diff_vec ( XEXP


<s> __attribute__ ( ( __always_inline__ , __gnu_inline__ , __artificial__ ) ) vmull_n_s16 ( int16x4_t a , int16_t b ) { int32x4_t result ; __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT> ( b ) : ) ; return


<s> case VEX_LOB_0F38 : insn -> opcodeType = THREEBYTE_38 ; return consumeByte ( insn , & insn -> opcode ) ; case VEX_LOB_0F3A : insn -> opcodeType = THREEBYTE_3A ; return consumeByte ( insn , & insn -> opcode ) ; } } else if ( insn -> vectorExtensionType == TYPE_VEX_3B ) { switch ( mmmmmFromVEX2of3 ( insn -> vectorExtensionPrefix [ <NUM_LIT> ] ) ) { default : dbgprintf ( insn , <STR_LIT> , mmmmmFromVEX2of3 ( insn -> vectorExtensionPrefix [ <NUM_LIT> ] ) ) ; return - <NUM_LIT> ; case VEX_LOB_0F : insn -> opcodeType = TWOBYTE ; return consumeByte ( insn , & insn -> opcode ) ; case VEX_LOB_0F38 : insn -> opcodeType = THREEBYTE_38 ; return consumeByte ( insn , & insn -> opcode ) ; case VEX_LOB_0F3A : insn -> opcodeType = THREEBYTE_3A ; return consumeByte ( insn , & insn -> opcode ) ; } } else if ( insn -> vectorExtensionType == TYPE_VEX_2B ) { insn -> opcodeType = TWOBYTE ; return consumeByte ( insn , & insn -> opcode ) ; } else if ( insn -> vectorExtensionType == TYPE_XOP ) { switch ( mmmmmFromXOP2of3 ( insn -> vectorExtensionPrefix [ <NUM_LIT> ] ) ) { default : dbgprintf ( insn , <STR_LIT> , mmmmmFromVEX2of3 ( insn -> vectorExtensionPrefix [ <NUM_LIT> ] ) ) ; return - <NUM_LIT> ; case XOP_MAP_SELECT_8 : insn -> opcodeType = XOP8_MAP ; return consumeByte ( insn , & insn -> opcode ) ; case XOP_MAP_SELECT_9 : insn -> opcodeType = XOP9_MAP ; return consumeByte ( insn , & insn -> opcode ) ; case XOP_MAP_SELECT_A : insn -> opcodeType = XOPA_MAP ; return consumeByte ( insn , & insn -> opcode ) ; } } if ( consumeByte ( insn , & current ) ) return - <NUM_LIT> ; if ( current == <NUM_LIT> ) { dbgprintf ( insn , <STR_LIT> , current ) ; if ( consumeByte ( insn , & current ) ) return - <NUM_LIT> ; if ( current == <NUM_LIT> ) { dbgprintf ( insn , <STR_LIT> , current ) ; if ( consumeByte ( insn , & current ) ) return - <NUM_LIT> ; insn -> opcodeType = THREEBYTE_38 ; } else if ( current == <NUM_LIT> ) { dbgprintf ( insn , <STR_LIT> , current ) ; if ( consumeByte ( insn , & current ) ) return - <NUM_LIT> ; insn -> opcodeType = THREEBYTE_3A ; } else if ( current == <NUM_LIT> ) { dbgprintf ( insn , <STR_LIT> , current ) ; if ( readModRM ( insn ) ) return - <NUM_LIT> ; if ( consumeByte ( insn , & current ) ) return - <NUM_LIT> ; insn -> opcodeType = THREEDNOW_MAP ; } else


<s> static bool riscv_cannot_copy_insn_p ( rtx_insn


<s> return ( __m256 ) __builtin_ia32_broadcastss256_mask ( ( __v4sf ) __A ,


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . addRequired < MachineDominatorTree


<s> FOR_EACH_SUBRTX ( iter , array , x , ALL ) { const_rtx x = * iter ; if ( SYMBOL_REF_P ( x ) && SYMBOL_REF_TLS_MODEL ( x ) != <NUM_LIT> ) return true ; if ( GET_CODE ( x ) == UNSPEC && XINT ( x , <NUM_LIT>

) == UNSPEC_TLS ) iter . skip_subrtxes ( ) ;


<s> return new <ISA_LIT>TransformIntrin (


<s> extern __inline void __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) _aand_i32 ( int * __A , int __B ) { __builtin_ia32_aand32 ( ( int * )


<s> return * ( getContext ( ) . getRegisterInfo ( ) -> getRegClass ( RC )


<s> SDLoc dl ( N ) ; bool isSigned = N -> getOpcode ( ) == <STR_LIT> ; unsigned IntrinsicOpcode = isSigned ? <STR_LIT> : <STR_LIT> ; SDValue FixConv = DAG . getNode ( <STR_LIT> , dl , NumLanes == <NUM_LIT> ? <STR_LIT> : <STR_LIT> , DAG . getConstant ( IntrinsicOpcode , dl , <STR_LIT> ) , Op -> getOperand ( <NUM_LIT> ) , DAG . getConstant ( C , dl , <STR_LIT> ) ) ; if ( IntBits < FloatBits ) FixConv = DAG . getNode ( <STR_LIT> , dl , N -> getValueType ( <NUM_LIT> ) , FixConv ) ; return FixConv


<s> return ( uint64x2_t ) __builtin_neon_vreinterpretv2div8hi ( ( int16x8_t )


<s> SDValue Vec = Op . getOperand ( <NUM_LIT> ) ; if ( Op . getValueType ( ) == <STR_LIT> && Vec . getValueType ( ) . getVectorElementType ( ) . getSizeInBits ( ) < <NUM_LIT> ) { DebugLoc dl = Op . getDebugLoc ( ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Vec ,


<s> static MachineBasicBlock :: iterator skipAlignedDPRCS2Spills ( MachineBasicBlock :: iterator MI , unsigned NumAlignedDPRCS2Regs ) { ++ MI ; ++ MI ; ++ MI ; assert ( MI -> mayStore (


<s> SDLoc dl ( N ) ; SDValue Op = N -> getOperand ( <NUM_LIT> ) ; EVT SrcVT = Op . getValueType ( ) ; EVT DstVT = N -> getValueType ( <NUM_LIT> ) ; if ( SrcVT == <STR_LIT> && DstVT == <STR_LIT> ) { if ( ! Subtarget -> hasFullFP16 ( ) ) return SDValue ( ) ; return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , <STR_LIT> , DAG . getNode ( <STR_LIT> , SDLoc ( N ) , <STR_LIT> , Op ) ) ; } if ( SrcVT == <STR_LIT> && DstVT == <STR_LIT> ) { if ( ! Subtarget -> hasFullFP16 ( ) ) return SDValue ( ) ; return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , <STR_LIT> , DAG . getNode ( <STR_LIT> , SDLoc ( N ) , <STR_LIT> , Op ) ) ; } if ( ! ( SrcVT == <STR_LIT> || DstVT == <STR_LIT> ) ) return SDValue ( ) ; if ( SrcVT == <STR_LIT> && TLI . isTypeLegal ( DstVT ) ) { if ( SDValue Val = CombineVMOVDRRCandidateWithVecOp ( N , DAG ) ) return Val ; SDValue Lo = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , dl , DstVT , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Lo , Hi ) ) ; } if ( DstVT == <STR_LIT> && TLI


<s> int int_or_sig_p = cfun -> machine -> is_interrupt || cfun -> machine -> is_signal ; if ( set ) CLEAR_HARD_REG_SET ( * set ) ; count = <NUM_LIT> ; if ( TREE_THIS_VOLATILE ( current_function_decl ) || cfun -> machine ->

is_OS_task || cfun -> machine -> is_OS_main ) return <NUM_LIT> ;


<s> static <ISA_LIT>Operand * CreateProcIFlags ( <STR_LIT> IFlags , SMLoc S ) { <ISA_LIT>Operand * Op = new <ISA_LIT>Operand ( ProcIFlags ) ; Op -> IFlags . Val = IFlags ; Op -> StartLoc


<s> void <ISA_LIT>CFGStackify :: fixEndsAtEndOfFunction ( MachineFunction & MF ) { const auto & MFI = * MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; if ( MFI . getResults ( ) . empty ( ) ) return ; <STR_LIT> RetType = MFI . getResults ( ) . size ( ) > <NUM_LIT> ? <STR_LIT> :: Multivalue : <STR_LIT> ( <STR_LIT> ( MFI . getResults ( ) . front ( ) ) ) ; SmallVector < MachineBasicBlock :: reverse_iterator , <NUM_LIT> > Worklist ; Worklist . push_back ( MF . rbegin ( ) -> rbegin ( ) ) ; auto Process = [ & ] ( MachineBasicBlock :: reverse_iterator It ) { auto * MBB = It -> getParent ( ) ; while ( It != MBB -> rend ( ) ) { MachineInstr & MI = * It ++ ; if ( MI . isPosition ( ) || MI . isDebugInstr ( ) ) continue ; switch ( MI . getOpcode ( ) ) { case <STR_LIT> : { auto * EHPad = TryToEHPad . lookup ( EndToBegin [ & MI ] ) ; assert ( EHPad ) ; auto NextIt = std :: next ( <STR_LIT> ( EHPad ) -> getReverseIterator ( ) ) ; if ( NextIt != EHPad -> rend ( ) ) Worklist .


<s> Attribute FSAttr = F . getFnAttribute ( <STR_LIT> ) ; std :: string CPU = ! CPUAttr . hasAttribute ( Attribute :: None ) ? CPUAttr . getValueAsString ( ) . str ( ) : TargetCPU ; std :: string FS = ! FSAttr . hasAttribute ( Attribute :: None ) ? FSAttr . getValueAsString ( ) . str ( ) : TargetFS ; bool has<ISA_LIT>16Attr = ! F . getFnAttribute ( <STR_LIT> ) . hasAttribute ( Attribute :: None ) ; bool hasNo<ISA_LIT>16Attr = ! F . getFnAttribute ( <STR_LIT> ) . hasAttribute ( Attribute :: None ) ; bool HasMicro<ISA_LIT>Attr = ! F . getFnAttribute ( <STR_LIT> ) . hasAttribute ( Attribute :: None ) ; bool HasNoMicro<ISA_LIT>Attr = ! F . getFnAttribute ( <STR_LIT> ) . hasAttribute ( Attribute :: None ) ; bool softFloat = F . hasFnAttribute ( <STR_LIT> ) && F . getFnAttribute ( <STR_LIT> ) . getValueAsString ( ) == <STR_LIT> ; if ( has<ISA_LIT>16Attr ) FS += FS . empty ( ) ? <STR_LIT> : <STR_LIT> ; else if ( hasNo<ISA_LIT>16Attr ) FS += FS . empty ( ) ? <STR_LIT> : <STR_LIT> ; if ( HasMicro<ISA_LIT>Attr ) FS += FS . empty ( ) ? <STR_LIT> : <STR_LIT> ; else if ( HasNoMicro<ISA_LIT>Attr ) FS += FS . empty ( ) ? <STR_LIT> : <STR_LIT> ; if ( softFloat ) FS += FS . empty ( ) ? <STR_LIT> : <STR_LIT> ; auto & I = SubtargetMap


<s> for ( auto J : I -> operands ( ) ) { if ( J . isRegMask ( ) ) AvailableRegs . clearBitsNotInMask ( J . getRegMask ( ) ) ; if ( J . isReg ( ) && J . isDef ( ) ) { MCRegAliasIterator AI ( J . getReg ( ) , TRI , true ) ; if ( J . isDead ( ) ) for ( ; AI . isValid ( ) ; ++ AI ) AvailableRegs . reset ( * AI ) ; else for ( ; AI . isValid ( ) ; ++ AI ) assert ( ! AvailableRegs [ * AI ] && <STR_LIT> ) ; } } } auto Ord = RCI . getOrder ( TRI -> getRegClass ( RegClassID ) ) ; for ( auto Reg


<s> switch ( IntNo ) { default : break ; case <STR_LIT> : { SDLoc DL ( Op ) ; MVT XLenVT = Subtarget . getXLenVT ( ) ; SDValue Mask = Op . getOperand ( <NUM_LIT> ) ; bool IsUnmasked = <STR_LIT> ( Mask . getNode ( ) ) ; MVT VT = Op -> getSimpleValueType ( <NUM_LIT> ) ; MVT ContainerVT = getContainerForFixedLengthVector ( VT ) ; SDValue PassThru = Op . getOperand ( <NUM_LIT> ) ; if ( ! IsUnmasked ) { MVT MaskVT = <STR_LIT> ( <STR_LIT> , ContainerVT . getVectorElementCount ( ) ) ; Mask = convertToScalableVector ( MaskVT , Mask , DAG , Subtarget ) ; PassThru = convertToScalableVector ( ContainerVT , PassThru , DAG , Subtarget ) ; } SDValue VL = DAG . getConstant ( VT . getVectorNumElements ( ) , DL , XLenVT ) ; SDValue IntID = DAG . getTargetConstant ( IsUnmasked ? <STR_LIT> : <STR_LIT> , DL , XLenVT ) ; auto * Load = cast < MemIntrinsicSDNode > ( Op ) ; SmallVector < SDValue , <NUM_LIT> > Ops { Load -> getChain ( ) , IntID } ; if ( ! IsUnmasked ) Ops . push_back ( PassThru ) ; Ops . push_back ( Op . getOperand ( <NUM_LIT> ) ) ; Ops . push_back ( Op . getOperand ( <NUM_LIT> ) ) ; if ( ! IsUnmasked ) Ops . push_back ( Mask ) ; Ops . push_back ( VL ) ; SDVTList VTs = DAG . getVTList ( { ContainerVT , <STR_LIT> } ) ; SDValue Result = DAG . getMemIntrinsicNode ( <STR_LIT> , DL , VTs , Ops , Load -> getMemoryVT (


<s> SDValue P = DAG . getNode ( <STR_LIT> , dl , DstVT , Op0 ) ; return DAG . getNode ( <STR_LIT> , dl , N -> getValueType ( <NUM_LIT> ) , P ) ; } if ( Op0 . getOpcode ( ) == <STR_LIT> ) { LoadSDNode * Ld = cast < LoadSDNode > ( Op0 . getNode ( ) ) ; EVT VT = Ld -> getValueType ( <NUM_LIT> ) ; if ( ! Ld -> isVolatile ( ) && ! N -> getValueType ( <NUM_LIT> ) . isVector ( ) && <STR_LIT> ( Op0 . getNode ( ) ) && Op0 . hasOneUse ( ) && ! XTLI -> getSubtarget ( ) -> is64Bit ( ) && ! DAG . getTargetLoweringInfo ( ) . isTypeLegal ( VT ) ) { SDValue FILDChain = XTLI -> BuildFILD ( SDValue ( N , <NUM_LIT> ) , Ld -> getValueType ( <NUM_LIT> ) , Ld -> getChain ( ) , Op0 , DAG ) ; DAG . ReplaceAllUsesOfValueWith ( Op0 . getValue ( <NUM_LIT> ) , FILDChain


<s> void addExpr ( MCInst & Inst , const MCExpr * Expr ) const { if ( Expr == <NUM_LIT> ) Inst . addOperand ( MCOperand :: createImm ( <NUM_LIT> ) ) ; else if ( const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( Expr ) ) Inst

. addOperand ( MCOperand :: createImm ( CE -> getValue ( ) ) ) ;


<s> for ( unsigned i = <NUM_LIT> ; i != Size ; ++ i ) DF . getContents ( ) [ Fixup . getOffset ( ) + i ] = uint8_t (


<s> if ( GET_CODE ( dst ) != REG || REGNO ( dst ) != FLAGS_REG || GET_MODE ( dst ) != CCZmode ) return false ; rtx op1 = XEXP ( src , <NUM_LIT> ) ; rtx op2 = XEXP ( src , <NUM_LIT> ) ; if ( op2 != CONST0_RTX ( GET_MODE ( op2 ) ) ) return false ; if ( GET_CODE ( op1 ) != IOR ) return false ; op2 = XEXP ( op1 , <NUM_LIT> ) ; op1 = XEXP ( op1 , <NUM_LIT> ) ; if ( ! SUBREG_P ( op1 ) || ! SUBREG_P ( op2 ) || GET_MODE ( op1 ) != SImode || GET_MODE ( op2 ) != SImode || ( ( SUBREG_BYTE ( op1 ) != <NUM_LIT> || SUBREG_BYTE ( op2 ) != GET_MODE_SIZE ( SImode ) ) && ( SUBREG_BYTE ( op2 ) != <NUM_LIT> || SUBREG_BYTE ( op1 ) != GET_MODE_SIZE ( SImode ) ) ) ) return false ; op1 = SUBREG_REG ( op1 ) ; op2 = SUBREG_REG ( op2 ) ; if ( op1 != op2 || ! REG_P ( op1 ) || GET_MODE ( op1 )


<s> ImplicitDefReg = createResultReg ( RC ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: IMPLICIT_DEF ) , ImplicitDefReg ) ; } Register ResultReg = createResultReg ( RC ) ; MachineInstrBuilder MIB ; MIB = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpc ) , ResultReg ) ; if ( HasAVX ) MIB . addReg ( ImplicitDefReg ) ; MIB . addReg ( OpReg


<s> MachineBasicBlock * MBB = Br . MI -> getParent ( ) ; BBInfo [ MBB -> getNumber ( ) ] . Size -= <NUM_LIT> ; adjustBBOffsetsAfter ( MBB ) ; ++ NumT2BrShrunk ; MadeChange = true ; } } Opcode = Br . MI -> getOpcode ( ) ; if ( Opcode != <STR_LIT> ) continue ; if ( ! Br . MI -> killsRegister ( <STR_LIT> ) ) continue ; NewOpc = <NUM_LIT> ; unsigned PredReg = <NUM_LIT> ; <STR_LIT> Pred = getInstrPredicate ( Br . MI , PredReg ) ; if ( Pred == <STR_LIT> ) NewOpc = <STR_LIT> ; else if ( Pred == <STR_LIT> ) NewOpc = <STR_LIT> ; if ( ! NewOpc ) continue ; MachineBasicBlock * DestBB = Br . MI -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; unsigned BrOffset = getOffsetOf ( Br . MI ) + <NUM_LIT> - <NUM_LIT> ; unsigned DestOffset = BBInfo [ DestBB -> getNumber ( ) ] . Offset ; if ( BrOffset < DestOffset && ( DestOffset - BrOffset ) <= <NUM_LIT> ) { MachineBasicBlock :: iterator CmpMI = Br . MI ; if ( CmpMI != Br . MI -> getParent ( ) -> begin ( ) ) { -- CmpMI ; if ( CmpMI -> getOpcode ( ) == <STR_LIT> ) { unsigned Reg = CmpMI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; Pred = getInstrPredicate ( CmpMI , PredReg ) ; if ( Pred == <STR_LIT> && CmpMI -> getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> && is<ISA_LIT>LowRegister (


<s> static std :: unique_ptr < <ISA_LIT>Operand > createReg ( unsigned RegNo , SMLoc S , SMLoc E ) { auto Op = make_unique < <ISA_LIT>Operand > ( Register ) ; Op -> Reg . RegNum = RegNo ; Op -> StartLoc


<s> if ( isa < ArrayType > ( Ty ) ) { char IDStr [ <NUM_LIT> ] = { '\0' } ; Type * ElmTy = cast < ArrayType > ( Ty ) -> getElementType ( ) ; unsigned NumElm = cast < ArrayType > ( Ty ) -> getNumElements ( ) ; std :: string ElmTyStr = EmitTypeString ( ElmTy ) ; FieldInit += <STR_LIT> ; FieldInit += <STR_LIT> ; sprintf ( IDStr , <STR_LIT> , NumElm ) ; FieldInit += IDStr ; if ( isa < StructType > ( ElmTy ) ) FieldInit += <STR_LIT> ; else FieldInit += <STR_LIT> ; FieldInit += ElmTyStr ; FieldInit += <STR_LIT> ; FieldInit += ClassName ; FieldInit += <STR_LIT> ; IDStr [ <NUM_LIT> ] = '\0' ; sprintf ( IDStr , <STR_LIT> , FieldID ) ; FieldInit += IDStr ; FieldInit += <STR_LIT> ; MFI -> getTypeDescriptor ( Ty , FieldInit ) ; if ( isa < StructType > ( ElmTy ) ) { for ( unsigned i = <NUM_LIT> ; i < NumElm ; i ++ ) { FieldInit += <STR_LIT> ; FieldInit += <STR_LIT> ; FieldInit += ClassName ; FieldInit += <STR_LIT> ; IDStr [ <NUM_LIT> ] = '\0' ; sprintf ( IDStr , <STR_LIT> , FieldID ) ; FieldInit += IDStr ; FieldInit += <STR_LIT> ; MFI -> getTypeDescriptor ( Ty , FieldInit ) ; if ( i < <NUM_LIT> ) FieldInit += <STR_LIT> ; else FieldInit += <STR_LIT> ; IDStr [ <NUM_LIT> ] = '\0' ; sprintf ( IDStr , <STR_LIT> , i ) ; FieldInit += IDStr ; FieldInit += <STR_LIT> ; FieldInit += ElmTyStr ; FieldInit += <STR_LIT> ; FieldInit += <STR_LIT> ; FieldInit += ElmTyStr ; FieldInit += <STR_LIT> ; FieldInit += <STR_LIT> ; } } } else if ( isa < StructType > ( Ty ) ) { char IDStr [ <NUM_LIT> ] = { '\0' } ; std :: string TypeStr = EmitTypeString ( Ty ) ; FieldInit += <STR_LIT> ; FieldInit += <STR_LIT> ; FieldInit += TypeStr ; FieldInit += <STR_LIT> ; FieldInit += <STR_LIT> ; FieldInit += TypeStr ; FieldInit += <STR_LIT> ; FieldInit += <STR_LIT> ; FieldInit += ClassName ; FieldInit +=


<s> static DecodeStatus decodeImmShiftOpValue ( MCInst & Inst , uint64_t Imm

, int64_t Address , const MCDisassembler * Decoder ) {


<s> virtual bool runOnMachineFunction ( MachineFunction & MF ) { MachineFrameInfo * FFI = MF . getFrameInfo ( ) ; MachineRegisterInfo & RI = MF . getRegInfo ( ) ; unsigned MaxAlign = calculateMaxStackAlignment ( FFI ) ; for ( unsigned RegNum = TargetRegisterInfo :: FirstVirtualRegister ; RegNum < RI . getLastVirtReg ( ) ; ++ RegNum ) MaxAlign = std :: max ( MaxAlign , RI

. getRegClass ( RegNum ) -> getAlignment ( ) ) ;


<s> int64_t Val = Memory . OffsetImm -> getValue ( ) ; return Val >= <NUM_LIT> && Val <= <NUM_LIT> &&


<s> SDValue Vec = N -> getOperand ( <NUM_LIT> ) ; SelectionDAG & DAG = DCI . DAG ; if ( Vec . getOpcode ( ) == <STR_LIT> && allUsesHaveSourceMods ( N ) ) { SDLoc SL ( N ) ; EVT EltVT = N -> getValueType ( <NUM_LIT> ) ; SDValue Idx = N -> getOperand ( <NUM_LIT> ) ; SDValue Elt = DAG . getNode ( <STR_LIT> , SL , EltVT , Vec . getOperand ( <NUM_LIT> ) , Idx ) ; return DAG . getNode ( <STR_LIT> , SL ,


<s> <STR_LIT> NewCC = <STR_LIT> ( CC , true ) ; return DAG . getSetCC ( dl , VT , Op0 , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) , NewCC ) ; } if ( ! isNullConstant ( Op1 ) ) { SDValue Xor = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op0 , Op1 ) ; return DAG . getSetCC ( dl , VT , Xor , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) , CC ) ; } } bool IsFP = Op1 . getSimpleValueType ( ) . isFloatingPoint ( ) ; <STR_LIT> <ISA_LIT>CC = Translate<ISA_LIT>CC ( CC , dl , IsFP , Op0 , Op1 , DAG ) ; if ( <ISA_LIT>CC == <STR_LIT> ) return SDValue ( ) ; SDValue EFLAGS = EmitCmp ( Op0 , Op1 , <ISA_LIT>CC , dl , DAG ) ; EFLAGS = ConvertCmpIfNecessary ( EFLAGS , DAG ) ; SDValue SetCC = getSETCC ( <ISA_LIT>CC , EFLAGS , dl , DAG ) ; if ( VT == <STR_LIT> ) return DAG . getNode (


<s> unsigned <ISA_LIT>BaseRegisterInfo :: getEHHandlerRegister


<s> } else { VIndex = B . buildConstant ( S32 , <NUM_LIT> ) . getReg ( <NUM_LIT> ) ; } Register VOffset = MI . getOperand ( <NUM_LIT> + OpOffset ) . getReg ( ) ; Register SOffset = MI . getOperand ( <NUM_LIT> + OpOffset ) . getReg ( ) ; unsigned Format = <NUM_LIT> ; if ( IsTyped ) { Format = MI . getOperand ( <NUM_LIT> + OpOffset ) . getImm ( ) ; ++ OpOffset ; } unsigned AuxiliaryData = MI . getOperand ( <NUM_LIT> + OpOffset ) . getImm ( ) ; std :: tie ( VOffset , ImmOffset ) = splitBufferOffsets ( B , VOffset ) ; updateBufferMMO ( MMO , VOffset , SOffset , ImmOffset , VIndex , MRI ) ; unsigned Opc ; if ( IsTyped ) { Opc = IsD16 ? <STR_LIT> : <STR_LIT> ; } else if ( IsFormat ) { Opc = IsD16 ? <STR_LIT> : <STR_LIT> ; } else { switch ( MemSize ) { case <NUM_LIT> : Opc = <STR_LIT> ; break ; case <NUM_LIT> : Opc = <STR_LIT> ; break ; default : Opc = <STR_LIT>


<s> if ( CurDAG -> isBaseWithConstantOffset ( Addr ) ) { ConstantSDNode * CN = dyn_cast < ConstantSDNode > ( Addr . getOperand ( <NUM_LIT> ) ) ; if ( isInt < <NUM_LIT> > ( CN -> getSExtValue ( ) ) ) { if ( FrameIndexSDNode * FIN = dyn_cast < FrameIndexSDNode > ( Addr . getOperand ( <NUM_LIT> ) ) ) Base = CurDAG -> getTargetFrameIndex ( FIN -> getIndex ( ) , <STR_LIT> ) ; else Base = Addr . getOperand ( <NUM_LIT> ) ; Offset = CurDAG -> getTargetConstant ( CN -> getSExtValue ( ) , DL , <STR_LIT> ) ; return true


<s> unsigned Opc = <NUM_LIT> ; if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = <STR_LIT> ; else if ( TRI -> isTypeLegalForClass ( * RC , <STR_LIT> ) ) Opc = <STR_LIT> ; else if ( TRI -> isTypeLegalForClass ( * RC , <STR_LIT> ) || TRI -> isTypeLegalForClass ( * RC , <STR_LIT> ) ) Opc = <STR_LIT> ; else if ( TRI -> isTypeLegalForClass ( * RC , <STR_LIT> ) || TRI -> isTypeLegalForClass ( * RC , <STR_LIT> ) ) Opc = <STR_LIT> ; else if ( TRI -> isTypeLegalForClass ( * RC , <STR_LIT> ) || TRI -> isTypeLegalForClass ( * RC , <STR_LIT> ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = <STR_LIT> ; const Function * Func = MBB . getParent ( ) -> getFunction ( ) ; if ( Func -> hasFnAttribute ( <STR_LIT> ) ) { if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , <STR_LIT> ) ; SrcReg = <STR_LIT> ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , <STR_LIT> ) ; SrcReg =


<s> reg = gen_rtx_REG ( SImode , regno ) ; sym = gen_rtx_SYMBOL_REF ( SImode , symbol ) ; emit_insn ( gen_movsi_topsym_s ( reg ,


<s> if ( ! Reg ) return <NUM_LIT> ; if ( SubReg ) Reg = TRI -> getSubReg ( Reg , SubReg ) ; } const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ; unsigned Size = TRI -> getRegSizeInBits ( * RC ) / <NUM_LIT> ; if ( Size > <NUM_LIT> ) Reg = TRI -> getSubReg ( Reg , <STR_LIT> ) ; if ( TRI -> hasVGPRs ( RC ) ) { Reg -= <STR_LIT> ; unsigned Mask = ( <NUM_LIT> << Size ) - <NUM_LIT> ; unsigned Used = <NUM_LIT> ; for ( unsigned I = <NUM_LIT> ; I < Size ; ++ I ) if ( RegsUsed . test ( Reg + I ) ) Used |= <NUM_LIT> << I ; RegsUsed . set ( Reg , Reg + Size ) ; Mask &= ~ Used ; Mask <<= ( Bank == - <NUM_LIT> ) ? Reg % NUM_VGPR_BANKS : unsigned ( Bank ) ; return ( Mask | ( Mask >> NUM_VGPR_BANKS ) ) & VGPR_BANK_MASK ; } Reg = TRI -> getEncodingValue ( Reg ) / <NUM_LIT> ; unsigned StartBit = <STR_LIT> . getNumRegs ( ) ; if ( Reg + StartBit >= RegsUsed . size ( ) ) return <NUM_LIT> ; if ( Size > <NUM_LIT> ) Size /= <NUM_LIT> ; unsigned Mask = ( <NUM_LIT> << Size ) -


<s> SDValue N0 = Op . getOperand ( <NUM_LIT> ) ; SDValue N1 = Op . getOperand ( <NUM_LIT> ) ; SDValue N2 = Op . getOperand ( <NUM_LIT> ) ; if ( EVT . getSizeInBits ( ) == <NUM_LIT> ) { if ( N1 . getValueType ( ) != <STR_LIT> ) N1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N1 ) ; if ( N2 . getValueType ( ) != <STR_LIT> ) N2 = DAG . getIntPtrConstant ( cast < ConstantSDNode > ( N2 ) -> getZExtValue ( ) ) ; return DAG . getNode ( <STR_LIT> , dl , VT , N0 ,


<s> std :: string lowerCase = Tok . getString ( ) . lower ( ) ; <STR_LIT> ShiftTy = StringSwitch < <STR_LIT> > ( lowerCase ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( <STR_LIT> ) ; if ( ShiftTy == <STR_LIT> ) return <NUM_LIT> ; Parser . Lex ( ) ; std :: unique_ptr < <ISA_LIT>Operand > PrevOp ( ( <ISA_LIT>Operand * ) Operands . pop_back_val ( ) . release ( ) ) ; if ( ! PrevOp -> isReg ( ) ) return Error ( PrevOp -> getStartLoc ( ) , <STR_LIT> ) ; int SrcReg = PrevOp -> getReg ( ) ; SMLoc EndLoc ; int64_t Imm = <NUM_LIT> ; int ShiftReg = <NUM_LIT> ; if ( ShiftTy == <STR_LIT> ) { ShiftReg = SrcReg ; } else { if ( Parser . getTok ( ) . is ( AsmToken :: Hash ) || Parser . getTok ( ) . is ( AsmToken :: Dollar ) ) { Parser . Lex ( ) ; SMLoc ImmLoc = Parser . getTok ( ) . getLoc ( ) ; const MCExpr * ShiftExpr = nullptr ; if ( getParser ( ) . parseExpression ( ShiftExpr , EndLoc ) ) { Error ( ImmLoc , <STR_LIT> ) ; return - <NUM_LIT> ; } const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( ShiftExpr ) ; if ( ! CE ) { Error ( ImmLoc , <STR_LIT> ) ; return - <NUM_LIT> ; } Imm = CE -> getValue ( ) ; if ( Imm < <NUM_LIT> || ( ( ShiftTy == <STR_LIT> || ShiftTy == <STR_LIT> ) && Imm > <NUM_LIT> ) || ( ( ShiftTy == <STR_LIT> || ShiftTy == <STR_LIT> ) && Imm > <NUM_LIT> ) ) { Error ( ImmLoc , <STR_LIT> ) ; return - <NUM_LIT> ; } if ( Imm == <NUM_LIT> ) ShiftTy = <STR_LIT> ; } else if ( Parser . getTok ( ) . is ( AsmToken :: Identifier ) ) { SMLoc L = Parser . getTok ( ) . getLoc ( ) ; EndLoc = Parser . getTok ( ) . getEndLoc ( ) ; ShiftReg = tryParseRegister ( ) ; if ( ShiftReg == - <NUM_LIT> ) { Error ( L , <STR_LIT> ) ; return - <NUM_LIT> ; } } else { Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; return - <NUM_LIT> ; } } if ( ShiftReg && ShiftTy != <STR_LIT> ) Operands . push_back ( <ISA_LIT>Operand :: CreateShiftedRegister ( ShiftTy , SrcReg , ShiftReg , Imm , S , EndLoc ) ) ; else Operands . push_back ( <ISA_LIT>Operand :: CreateShiftedImmediate ( ShiftTy , SrcReg , Imm , S , EndLoc ) ) ; return <NUM_LIT>


<s> bool <ISA_LIT>TTIImpl :: isLSRCostLess ( const TargetTransformInfo :: LSRCost & C1 , const TargetTransformInfo :: LSRCost & C2 ) { if ( ! LsrNoInsnsCost ) return std :: tie ( C1 . Insns , C1 . NumRegs , C1 . AddRecCost , C1 . NumIVMuls , C1 . NumBaseAdds , C1 . ScaleCost , C1 . ImmCost , C1 .

SetupCost ) < std :: tie ( C2 . Insns , C2 . NumRegs , C2 . AddRecCost , C2 . NumIVMuls , C2 . NumBaseAdds , C2 . ScaleCost , C2 . ImmCost , C2 . SetupCost ) ;


<s> if ( Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || ( ! isThumb ( ) && ( Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> ) ) ) { CanAcceptCarrySet = true ; } else CanAcceptCarrySet = false ; if ( Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic . startswith ( <STR_LIT> ) || Mnemonic . startswith ( <STR_LIT> ) || Mnemonic . startswith ( <STR_LIT> ) || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic . startswith ( <STR_LIT> ) || Mnemonic . startswith ( <STR_LIT> ) || Mnemonic . startswith ( <STR_LIT> ) || ( FullInst . startswith ( <STR_LIT> ) && FullInst . endswith ( <STR_LIT> ) ) ) { CanAcceptPredicationCode =


<s> static bool aarch64_evpc_dup ( struct expand_vec_perm_d * d ) { rtx out = d -> target ; rtx in0 ; HOST_WIDE_INT elt ; machine_mode vmode = d -> vmode ; rtx lane ; if ( d -> vec_flags == VEC_SVE_PRED || d -> perm . encoding ( ) . encoded_nelts ( ) != <NUM_LIT> || ! d -> perm [ <NUM_LIT> ] . is_constant ( & elt ) ) return false ; if ( d -> vec_flags == VEC_SVE_DATA && elt >= <NUM_LIT> * GET_MODE_UNIT_SIZE ( vmode ) ) return false ; if ( d -> testing_p ) return true ; in0 = d -> op0 ; lane = GEN_INT ( elt


<s> setAvailableFeatures ( ComputeAvailableFeatures ( STI . ToggleFeature ( FeatureString )


<s> return __builtin_aarch64_lfrintnusfsi (


<s> } } unsigned CompareOpc = <ISA_LIT>ChooseCmpOpcode ( VT , Subtarget ) ; if ( CompareOpc == <NUM_LIT> ) return false ; unsigned Op1Reg = getRegForValue ( Op1 ) ; if ( Op1Reg == <NUM_LIT> ) return false ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( CompareOpc ) ) . addReg ( Op0Reg ) . addReg ( Op1Reg ) ; return true


<s> unsigned <ISA_LIT>InstrInfo :: isStoreToStackSlot ( const MachineInstr * MI , int & FrameIndex ) const { return


<s> bool <ISA_LIT>DAGToDAGISel :: SelectSMRDBufferImm32 ( SDValue Addr , SDValue & Offset ) const { if ( Subtarget -> getGeneration ( ) != <ISA_LIT>Subtarget


<s> void <ISA_LIT>MCExpr :: printImpl ( raw_ostream & OS , const MCAsmInfo * MAI ) const { switch ( Kind ) { default : llvm_unreachable ( <STR_LIT> ) ; case VK_<ISA_LIT>_GOT : OS << <STR_LIT> ; break ; case VK_<ISA_LIT>_ABS_HI : OS << <STR_LIT> ; break ; case VK_<ISA_LIT>_ABS_LO : OS << <STR_LIT> ; break ; } OS << '(' ; const MCExpr * Expr =


<s> llvm_unreachable ( <STR_LIT> ) ; } else if ( ArgVT . isFloatingPoint ( ) && ArgSize <= <NUM_LIT> ) { ArgMode = <NUM_LIT> ; } else if ( ArgVT . isInteger ( ) && ArgSize <= <NUM_LIT> ) { ArgMode = <NUM_LIT> ; } else { llvm_unreachable ( <STR_LIT> ) ; } if ( ArgMode == <NUM_LIT> ) { assert ( ! Subtarget -> useSoftFloat ( ) && ! ( DAG . getMachineFunction ( ) . getFunction ( ) -> hasFnAttribute ( Attribute :: NoImplicitFloat ) ) && Subtarget -> hasSSE1 ( ) ) ; } SDValue InstOps [ ] = { Chain , SrcPtr , DAG . getConstant ( ArgSize , dl , <STR_LIT> ) , DAG . getConstant ( ArgMode , dl , <STR_LIT> ) , DAG . getConstant ( Align , dl , <STR_LIT> ) } ; SDVTList VTs = DAG . getVTList (


<s> void <ISA_LIT>HazardRecognizer :: nextGroup ( ) { if ( CurrGroupSize == <NUM_LIT> ) return ; DEBUG ( dumpCurrGroup ( <STR_LIT> ) ) ; DEBUG ( CurGroupDbg = <STR_LIT> ; ) ; GrpCount ++ ; CurrGroupSize = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> ; i < SchedModel -> getNumProcResourceKinds ( ) ; ++ i ) if ( ProcResourceCounters [ i ] > <NUM_LIT> ) ProcResourceCounters [ i ] -- ; if ( CriticalResourceIdx != UINT_MAX && ( ProcResourceCounters [ CriticalResourceIdx ] <= ProcResCostLim


<s> FrameReg = TRI -> getStackRegister ( ) ; return StackOffset :: getFixed ( MFI . getObjectOffset ( FI

) - getOffsetOfLocalArea ( ) + Adjustment ) ;


<s> SmallVector < CCValAssign , <NUM_LIT> > ValLocs ; CCState CCInfo ( CC , F . isVarArg ( ) , * FuncInfo . MF , TM , ValLocs , * Context ) ; CCInfo . AnalyzeReturn ( Outs , RetCC_<ISA_LIT>64_ELF_FIS ) ; const Value * RV = Ret -> getOperand ( <NUM_LIT> ) ; if ( ValLocs . size ( ) > <NUM_LIT> ) return false ; if ( isa < ConstantInt > ( * RV ) ) { const Constant * C = cast < Constant > ( RV ) ; CCValAssign & VA = ValLocs [ <NUM_LIT> ] ; unsigned RetReg = VA . getLocReg ( ) ; unsigned SrcReg = <ISA_LIT>MaterializeInt ( C , <STR_LIT> , VA . getLocInfo ( ) == CCValAssign :: SExt ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: COPY ) , RetReg ) . addReg ( SrcReg ) ; RetRegs . push_back ( RetReg ) ; } else { unsigned Reg = getRegForValue ( RV ) ; if ( Reg == <NUM_LIT> ) return false ; for ( unsigned i = <NUM_LIT> ; i < ValLocs . size ( ) ; ++ i ) { CCValAssign & VA = ValLocs [ i ] ; assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; RetRegs . push_back ( VA . getLocReg ( ) ) ; unsigned SrcReg = Reg + VA . getValNo ( ) ; EVT RVEVT = TLI . getValueType ( RV -> getType ( ) ) ; if ( ! RVEVT . isSimple ( ) ) return false ; MVT RVVT = RVEVT . getSimpleVT ( ) ; MVT DestVT = VA . getLocVT ( ) ; if ( RVVT != DestVT && RVVT != <STR_LIT> && RVVT != <STR_LIT> && RVVT != <STR_LIT> ) return false ; if ( RVVT != DestVT ) { switch ( VA . getLocInfo


<s> void <ISA_LIT>TargetLowering :: ReplaceNodeResults ( SDNode * N , SmallVectorImpl < SDValue > & Results , SelectionDAG & DAG ) const { switch ( N -> getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : ReplaceBITCASTResults ( N , Results , DAG ) ; return ; case <STR_LIT> : case <STR_LIT> : assert ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT> &&


<s> <ISA_LIT>TargetLowering :: <ISA_LIT>TargetLowering ( const TargetMachine & TM , const <ISA_LIT>Subtarget & Subtarget ) : TargetLowering ( TM ) , TM ( TM ) , Subtarget ( Subtarget ) { addRegisterClass ( <STR_LIT> , & <STR_LIT> ) ; addRegisterClass ( <STR_LIT> , & <STR_LIT> ) ; computeRegisterProperties ( Subtarget . getRegisterInfo ( ) ) ; setStackPointerRegisterToSaveRestore ( <STR_LIT> ) ; setSchedulingPreference ( Sched :: Source ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom


<s> static int far_addr_space_p ( rtx x ) { if ( GET_CODE ( x ) != MEM ) return <NUM_LIT> ; fprintf ( stderr , <STR_LIT> ) ;


<s> bool useRegsForByval ( ) const { return CallConv != CallingConv


<s> SDValue V = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) ) ; SDValue Idx128 = Op . getOperand ( <NUM_LIT> ) ; auto * CIdx = dyn_cast < ConstantSDNode > ( Idx128 ) ; if ( CIdx && ( CIdx -> getZExtValue ( ) <= <NUM_LIT> ) ) { SDValue CI = DAG . getTargetConstant ( CIdx -> getZExtValue ( ) , DL , <STR_LIT> ) ; SDNode * DUPQ = DAG . getMachineNode ( <STR_LIT> , DL , <STR_LIT> , V , CI ) ; return DAG . getNode ( <STR_LIT> , DL , VT , SDValue ( DUPQ , <NUM_LIT> ) ) ; } SDValue One = DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; SDValue SplatOne = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , One ) ; SDValue SV = DAG . getNode ( <STR_LIT> , DL , <STR_LIT>


<s> long __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) __rorq ( unsigned long long __X , int __C ) { return ( __X >> __C ) | (


<s> const char * libName = TLI . getLibcallName ( VT == <STR_LIT> ? RTLIB :: FPTOSINT_F128_I32 : RTLIB :: FPTOSINT_F128_I64 ) ; return TLI . LowerF128Op ( Op , DAG , libName , <NUM_LIT> ) ; } if ( ! TLI . isTypeLegal ( VT ) ) return SDValue ( ) ; if ( VT == <STR_LIT> ) Op = DAG . getNode ( <STR_LIT> , dl

, <STR_LIT> , Op . getOperand ( <NUM_LIT> ) ) ;


<s> tree lhs_type = TREE_TYPE ( gimple_assign_lhs ( assign ) ) ; tree rhs_type = TREE_TYPE ( gimple_assign_rhs1 ( assign ) ) ; return ( INTEGRAL_TYPE_P ( lhs_type ) && INTEGRAL_TYPE_P ( rhs_type ) && TYPE_PRECISION

( lhs_type ) < TYPE_PRECISION ( rhs_type ) ) ;


<s> bool hasFPCVT ( ) const { return HasFPCVT


<s> MCObjectWriter * createObjectWriter ( raw_ostream & OS )


<s> if ( ! curLoc ) return ; DIScope Scope ( curLoc . getScope ( ) ) ; assert ( ( ! Scope || Scope . isScope ( ) ) && <STR_LIT> ) ; if ( ! Scope ) return ; StringRef fileName ( Scope . getFilename ( ) ) ; StringRef dirName ( Scope . getDirectory ( ) ) ; SmallString < <NUM_LIT> > FullPathName = dirName ; if ( ! dirName . empty ( ) && ! sys :: path :: is_absolute ( fileName ) ) { sys :: path :: append ( FullPathName , fileName ) ; fileName = FullPathName ; } if ( filenameMap . find ( fileName ) ==


<s> if ( Tok . isNot ( AsmToken :: Identifier ) ) return true ; const StringRef & ShiftName = Tok . getString ( ) ; if ( ShiftName == <STR_LIT> || ShiftName == <STR_LIT> ) St = Lsl ; else if ( ShiftName == <STR_LIT> || ShiftName == <STR_LIT> ) St = Lsr ; else if ( ShiftName == <STR_LIT> || ShiftName == <STR_LIT> ) St = Asr ; else if ( ShiftName == <STR_LIT> || ShiftName == <STR_LIT> ) St = Ror ; else if ( ShiftName == <STR_LIT> || ShiftName == <STR_LIT> ) St = Rrx ; else return true ; Parser . Lex (


<s> else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = IsN64 ? <STR_LIT> : <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = IsN64 ? <STR_LIT> : <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = IsN64 ? <STR_LIT> : <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = IsN64 ? <STR_LIT> : <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = IsN64 ? <STR_LIT> : <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc


<s> } unsigned Start , End ; if ( TII -> isRxSBGMask ( Value , BitsPerElement , Start , End ) ) { Start -= <NUM_LIT> - BitsPerElement ; End -= <NUM_LIT> - BitsPerElement ; MVT VecVT = <STR_LIT> ( <STR_LIT> ( BitsPerElement ) , <STR_LIT> / BitsPerElement ) ; SDValue Op = DAG . getNode ( <STR_LIT> , DL , VecVT , DAG . getConstant ( Start , DL , <STR_LIT> , false , true ) , DAG . getConstant ( End , DL , <STR_LIT> , false , true ) ) ; return DAG . getNode ( <STR_LIT> ,


<s> TargetLoweringObjectFile * getObjFileLowering ( ) const override { return this -> TLOF .


<s> if ( extracted_mcu_data . name != NULL ) return cached_result = ( extracted_mcu_data . hwmpy == <NUM_LIT> || extracted_mcu_data . hwmpy == <NUM_LIT> ) ; return cached_result = false


<s> if ( ( ( ArgVT == <STR_LIT> ) || ( ArgVT == <STR_LIT> ) || ( ArgVT == <STR_LIT> ) || ( ArgVT == <STR_LIT> ) ) && VA . isMemLoc ( ) ) { switch ( VA . getLocMemOffset ( ) ) { case <NUM_LIT> : VA . convertToReg ( <STR_LIT> ) ; break ; case <NUM_LIT> : VA . convertToReg ( <STR_LIT> ) ; break ; case <NUM_LIT> : VA . convertToReg ( <STR_LIT> ) ; break ; case <NUM_LIT> : VA . convertToReg ( <STR_LIT> ) ; break ; default : break ; } } unsigned ArgReg = getRegForValue ( ArgVal ) ; if ( ! ArgReg ) return false ; switch ( VA . getLocInfo ( ) ) { case CCValAssign :: Full : break ; case CCValAssign :: AExt : case CCValAssign :: SExt : { MVT DestVT = VA . getLocVT ( ) ; MVT SrcVT = ArgVT ; ArgReg = emitIntExt ( SrcVT , ArgReg , DestVT , false ) ; if ( ! ArgReg ) return false ; break ; } case CCValAssign :: ZExt : { MVT DestVT = VA . getLocVT ( ) ; MVT SrcVT = ArgVT ; ArgReg = emitIntExt ( SrcVT , ArgReg , DestVT , true ) ; if ( ! ArgReg ) return false ; break ; } default : llvm_unreachable ( <STR_LIT> ) ; } if ( VA . isRegLoc ( ) && ! VA . needsCustom ( ) ) { BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: COPY ) , VA . getLocReg ( ) ) . addReg ( ArgReg ) ; CLI . OutRegs . push_back ( VA . getLocReg ( ) ) ; } else if ( VA . needsCustom ( ) ) { llvm_unreachable ( <STR_LIT> ) ; return false ; } else { assert ( VA . isMemLoc ( ) && <STR_LIT> ) ; if ( isa < UndefValue > ( ArgVal ) ) continue ; unsigned ArgSize = RoundUpToAlignment ( ArgVT . getSizeInBits ( ) , <NUM_LIT> ) ; unsigned BEAlign = <NUM_LIT> ; if ( ArgSize < <NUM_LIT> && ! Subtarget -> isLittle ( ) ) BEAlign = <NUM_LIT> - ArgSize ; Address Addr ; Addr . setKind ( Address :: RegBase ) ; Addr . setReg ( <STR_LIT> ) ; Addr . setOffset ( VA . getLocMemOffset ( ) + BEAlign ) ; unsigned Alignment = DL . getABITypeAlignment ( ArgVal -> getType ( ) ) ; MachineMemOperand * MMO = FuncInfo . MF -> getMachineMemOperand ( MachinePointerInfo :: getStack ( * FuncInfo . MF , Addr . getOffset ( ) ) , MachineMemOperand :: MOStore , ArgVT . getStoreSize ( ) , Alignment ) ; ( void ) (


<s> unsigned MB = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( ( VT == <STR_LIT> && MB <= <NUM_LIT> ) || ( VT == <STR_LIT> && MB <= <NUM_LIT> ) || ( VT == <STR_LIT> && MB <= <NUM_LIT> ) ) break ; return false ; } case <STR_LIT> : case <STR_LIT> : { IsZExt = true ; unsigned MB = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( ( VT == <STR_LIT> && MB <= <NUM_LIT> ) || ( VT == <STR_LIT> && MB <= <NUM_LIT> ) ) break ; return false ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return false ; case <STR_LIT>


<s> break ; } if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , Rd , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , Rd + inc , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( Rm != <NUM_LIT> ) { if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rn , Address , Decoder ) ) ) return MCDisassembler :: Fail ; } if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rn , Address , Decoder ) ) ) return MCDisassembler :: Fail ; Inst . addOperand ( MCOperand :: createImm ( align ) ) ; if ( Rm != <NUM_LIT> ) { if ( Rm != <NUM_LIT> ) { if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rm , Address , Decoder ) ) ) return MCDisassembler :: Fail ; } else Inst . addOperand ( MCOperand :: createReg (


<s> if ( Opt == <STR_LIT> ) { NoAliases = true ; return true ; } if ( Opt == <STR_LIT> ) { ArchRegNames =


<s> S . SwitchSection ( Context . getELFSection ( ElfNote :: SectionName , ELF :: SHT_NOTE , ELF :: SHF_ALLOC ) ) ; S . emitInt32 ( NameSZ ) ; S . emitValue ( DescSZ , <NUM_LIT> ) ; S . emitInt32 ( NoteType ) ; S . emitBytes ( Name ) ; S . emitValueToAlignment ( <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> ) ; EmitDesc ( S


<s> SwitchLeafData ( const SwitchInst * I ) : BB ( I -> getParent ( )


<s> void aarch64_asm_output_pool_epilogue ( FILE * f , const char


<s> void applyFixup ( const MCAssembler & Asm , const MCFixup & Fixup , const MCValue & Target , MutableArrayRef < char > Data , uint64_t Value , bool IsResolved ) const override { Value = adjustFixupValue ( Fixup . getKind ( ) , Value ) ; if ( ! Value


<s> bool <ISA_LIT>InstructionSelector :: selectUnOp ( Register ResVReg , const <ISA_LIT>Type * ResType , MachineInstr & I , unsigned Opcode ) const { return selectUnOpWithSrc ( ResVReg , ResType , I , I . getOperand ( <NUM_LIT> ) . getReg ( )


<s> assert ( ( vecWidth == <NUM_LIT> || vecWidth == <NUM_LIT> ) && <STR_LIT> ) ; if ( ! isa < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) . getNode ( ) ) ) llvm_unreachable ( <STR_LIT> ) ; uint64_t Index = cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) . getNode ( ) ) ->


<s> unsigned getCommonDomains ( unsigned mask ) const { return AvailableDomains &


<s> if ( dst & ( <NUM_LIT> << ( <NUM_LIT> - <NUM_LIT> ) ) ) dst |= ~ ( ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) ; if ( fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) == <NUM_LIT> ) DecodeGPR32RegisterClass ( Inst , Rt , Addr , Decoder ) ; else DecodeGPR64RegisterClass ( Inst , Rt , Addr , Decoder ) ; Inst . addOperand ( MCOperand :: CreateImm ( bit ) ) ; if ( ! Dis -> tryAddingSymbolicOperand ( Inst , dst << <NUM_LIT> , Addr , true , <NUM_LIT> , <NUM_LIT> ) ) Inst . addOperand ( MCOperand :: CreateImm ( dst ) ) ; return


<s> return CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , MskSize ) ; } else if ( ! isUInt < <NUM_LIT> > ( Val ) ) { SDValue CPIdx = CurDAG -> getTargetConstantPool ( ConstantInt :: get ( Type :: getInt32Ty ( * CurDAG -> getContext ( ) ) , Val ) , getTargetLowering ( ) -> getPointerTy ( ) ) ; SDNode * node = CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , <STR_LIT> , CPIdx , CurDAG -> getEntryNode ( ) ) ; MachineSDNode :: mmo_iterator MemOp = MF -> allocateMemRefsArray ( <NUM_LIT> ) ; MemOp [ <NUM_LIT> ] = MF -> getMachineMemOperand ( MachinePointerInfo :: getConstantPool ( ) , MachineMemOperand :: MOLoad , <NUM_LIT> , <NUM_LIT> ) ; cast < MachineSDNode > ( node ) -> setMemRefs ( MemOp , MemOp + <NUM_LIT> ) ; return node ; } break ; } case <STR_LIT> : { SDValue Ops [ ] = { N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) } ; return CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , <STR_LIT> , Ops ) ; } case <STR_LIT> : { SDValue Ops [ ] = { N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) } ; return CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , <STR_LIT> , Ops ) ; } case <STR_LIT> : { SDValue Ops [ ] = { N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) } ; return CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT>


<s> MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; MachineModuleInfo & MMI = MF . getMMI ( ) ; const MCRegisterInfo * MRI = MMI . getContext ( ) . getRegisterInfo ( ) ; const TargetInstrInfo * TII = MF . getSubtarget ( ) . getInstrInfo ( ) ; DebugLoc DL = MBB . findDebugLoc ( MBBI ) ; const std :: vector < CalleeSavedInfo > & CSI = MFI -> getCalleeSavedInfo ( ) ; if ( CSI . empty ( ) ) return ; for ( const auto & Info : CSI ) { unsigned Reg = Info . getReg ( ) ; int64_t Offset = MFI -> getObjectOffset ( Info . getFrameIdx ( ) ) - getOffsetOfLocalArea ( ) ; unsigned DwarfReg = MRI -> getDwarfRegNum (


<s> return ( __m512i ) __builtin_ia32_pmaxuq512_mask ( ( __v8di ) __A , ( __v8di )


<s> SDValue Op1 = Op . getOperand ( <NUM_LIT> ) ; EVT VT = Op . getValueType ( ) ; assert ( VT == <STR_LIT> && <STR_LIT> ) ; SDValue Flag ; Flag = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> ) ; Flag = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Flag ) ; return DAG . getNode ( <STR_LIT> , dl , DAG . getVTList ( VT , <STR_LIT> )


<s> void LLVMInitializePowerPCAsmParser ( ) { RegisterMCAsmParser < <ISA_LIT>AsmParser > A ( The<ISA_LIT>32Target ) ; RegisterMCAsmParser < <ISA_LIT>AsmParser > B ( The<ISA_LIT>64Target


<s> return has_func_attr ( decl , <STR_LIT>


<s> rtx dest = operands [ <NUM_LIT> ] ; rtx op0 , op1 ; gcc_assert ( ! reload_in_progress && ! reload_completed ) ; op = XEXP ( op , <NUM_LIT> ) ; op0 = force_reg ( mode , XEXP ( op , <NUM_LIT> ) ) ; op1 = XEXP ( op , <NUM_LIT> ) ; if ( ! insn_data [ CODE_FOR_addsi3 ] . operand [ <NUM_LIT> ] . predicate ( op1 , mode ) ) op1 = force_reg ( mode , op1 ) ; if ( GET_CODE ( dest ) == MEM ) dest = gen_reg_rtx ( mode ) ; emit_insn ( gen_addsi3 ( dest , op0 , op1 ) ) ; if ( dest == operands [ <NUM_LIT> ] )


<s> void printLSROperand ( const MCInst * MI , unsigned OpNum


<s> return D ( <STR_LIT> , R ( a ) , <STR_LIT> , MemARS ( b


<s> BuildMI ( offsetMBB , DL , TII -> get ( <STR_LIT> ) , RegSaveReg ) . addOperand ( Base ) . addOperand ( Scale ) . addOperand ( Index ) . addDisp ( Disp , <NUM_LIT> ) . addOperand ( Segment ) . setMemRefs ( MMOBegin , MMOEnd ) ; unsigned OffsetReg64 = MRI . createVirtualRegister ( AddrRegClass ) ; BuildMI ( offsetMBB , DL , TII -> get ( <STR_LIT> ) , OffsetReg64 ) . addImm ( <NUM_LIT> ) . addReg ( OffsetReg ) . addImm ( <STR_LIT> ) ; BuildMI ( offsetMBB , DL , TII -> get ( <STR_LIT> ) , OffsetDestReg ) . addReg ( OffsetReg64 ) . addReg ( RegSaveReg ) ; unsigned NextOffsetReg = MRI . createVirtualRegister ( OffsetRegClass ) ; BuildMI ( offsetMBB , DL , TII -> get ( <STR_LIT> ) , NextOffsetReg ) . addReg ( OffsetReg ) . addImm ( UseFPOffset ? <NUM_LIT> : <NUM_LIT> ) ; BuildMI ( offsetMBB , DL , TII -> get ( <STR_LIT> ) ) . addOperand ( Base ) . addOperand ( Scale ) . addOperand ( Index ) . addDisp ( Disp , UseFPOffset ? <NUM_LIT> : <NUM_LIT> ) . addOperand ( Segment ) . addReg ( NextOffsetReg ) . setMemRefs ( MMOBegin , MMOEnd ) ; BuildMI ( offsetMBB , DL , TII -> get ( <STR_LIT> ) ) . addMBB ( endMBB ) ; } unsigned OverflowAddrReg = MRI . createVirtualRegister ( AddrRegClass ) ; BuildMI ( overflowMBB , DL , TII -> get ( <STR_LIT> ) , OverflowAddrReg ) . addOperand ( Base ) . addOperand ( Scale ) . addOperand ( Index ) . addDisp ( Disp , <NUM_LIT> ) . addOperand ( Segment ) . setMemRefs ( MMOBegin , MMOEnd ) ; if ( NeedsAlign ) { assert ( ( Align & ( Align - <NUM_LIT> ) ) == <NUM_LIT> && <STR_LIT> ) ; unsigned TmpReg = MRI . createVirtualRegister ( AddrRegClass ) ; BuildMI ( overflowMBB , DL , TII -> get ( <STR_LIT> ) , TmpReg ) . addReg ( OverflowAddrReg ) . addImm ( Align - <NUM_LIT> ) ; BuildMI ( overflowMBB , DL , TII -> get ( <STR_LIT> ) , OverflowDestReg ) . addReg ( TmpReg ) . addImm ( ~ ( uint64_t ) ( Align - <NUM_LIT> ) ) ; }


<s> unsigned const16 = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned s1 = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned is32Bit = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; if ( ! is32Bit ) return MCDisassembler :: Fail ; DecodeStatus status = DecodeOperandRegister ( Inst , d , Address , Decoder ) ; if ( status != MCDisassembler ::


<s> unsigned <ISA_LIT>CodeGenPrepare :: numBitsSigned ( Value * Op , unsigned ScalarSize )


<s> MCAsmBackend * llvm :: create<ISA_LIT>AsmBackend ( const Target & T , const MCSubtargetInfo & STI , const MCRegisterInfo & MRI , const MCTargetOptions & Options ) { const Triple & TheTriple = STI . getTargetTriple (


<s> Type * VecEltTy = MaskTy -> getVectorElementType ( ) ; if ( ! VecEltTy -> isIntegerTy ( ) ) return ; unsigned EltTySize = VecEltTy -> getIntegerBitWidth ( ) ; if ( EltTySize < <NUM_LIT> || EltTySize > ElSize ) return ; unsigned NumElements = MaskTySize / ElSize ; assert ( ( NumElements == <NUM_LIT> || NumElements == <NUM_LIT> || NumElements == <NUM_LIT> || NumElements == <NUM_LIT> ) && <STR_LIT> ) ; ShuffleMask . reserve ( NumElements ) ; unsigned NumElementsPerLane = <NUM_LIT> / ElSize ; unsigned Factor = ElSize / EltTySize ; for ( unsigned i = <NUM_LIT> ; i < NumElements ; ++ i ) { Constant * COp = C -> getAggregateElement ( i * Factor ) ; if ( ! COp ) { ShuffleMask . clear ( ) ; return ; } else if ( isa < UndefValue


<s> else { emitGRX32Move ( * MI -> getParent ( ) , MI , MI -> getDebugLoc ( ) , DestReg , SrcReg , <STR_LIT> , <NUM_LIT> , MI -> getOperand ( <NUM_LIT> ) . isKill ( ) ) ; MI -> setDesc ( get ( DestIsHigh ? HighOpcode : LowOpcode ) ) ; MI -> getOperand ( <NUM_LIT> ) . setReg


<s> Inst . addOperand ( MCOperand :: CreateReg ( getReg (


<s> void <ISA_LIT>InstPrinter :: printExecutionMode ( const MCInst * MI , unsigned OpNo , raw_ostream & O ) { if ( OpNo < MI -> getNumOperands ( )


<s> if ( ! MJTI ) return ; const std :: vector < MachineJumpTableEntry > & JT = MJTI -> getJumpTables ( ) ; if ( JT . empty ( ) ) return ; const Function & F = MF -> getFunction ( ) ; const TargetLoweringObjectFile & TLOF = getObjFileLowering ( ) ; bool JTInDiffSection = ! STI -> isTargetCOFF ( ) || ! TLOF . shouldPutJumpTableInFunctionSection ( MJTI -> getEntryKind ( ) == MachineJumpTableInfo :: EK_LabelDifference32 , F ) ; if ( JTInDiffSection ) { MCSection * ReadOnlySec = TLOF . getSectionForJumpTable ( F , TM ) ; OutStreamer -> SwitchSection ( ReadOnlySec ) ; } auto AFI = MF -> getInfo < <ISA_LIT>FunctionInfo > ( ) ; for ( unsigned JTI = <NUM_LIT> , e = JT . size ( ) ; JTI != e ; ++ JTI ) { const std :: vector < MachineBasicBlock * > & JTBBs = JT [ JTI ] . MBBs ; if ( JTBBs . empty ( ) ) continue ; unsigned Size = AFI -> getJumpTableEntrySize ( JTI ) ; EmitAlignment ( Log2_32 ( Size ) ) ; OutStreamer -> EmitLabel ( GetJTISymbol ( JTI ) ) ; for ( auto * JTBB : JTBBs ) emitJumpTableEntry ( MJTI , JTBB ,


<s> bool <ISA_LIT>EarlyIfConversion :: isPreheader ( const MachineBasicBlock * B ) const { if ( B -> succ_size ( ) != <NUM_LIT> ) return false ; MachineBasicBlock * SB = * B -> succ_begin ( ) ; MachineLoop * L = MLI -> getLoopFor ( SB ) ; return L && SB == L ->


<s> bool runOnFunction ( Function & F ) override { return <ISA_LIT>AbstractMemberAccess ( TM ) .


, ( __mmask8 ) __U , _MM_FROUND_CUR_DIRECTION ) ;


<s> case CmpInst :: FCMP_UNE : SETFOpc = & SETFOpcTable [ <NUM_LIT> ] [ <NUM_LIT> ] ; break ; } ResultReg = createResultReg ( & <STR_LIT> ) ; if ( SETFOpc ) { if ( ! <ISA_LIT>FastEmitCompare ( LHS , RHS , VT , I -> getDebugLoc ( ) ) ) return false ; Register FlagReg1 = createResultReg ( & <STR_LIT> ) ; Register FlagReg2 = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , FlagReg1 ) . addImm ( SETFOpc [ <NUM_LIT> ] ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , FlagReg2 ) . addImm ( SETFOpc [ <NUM_LIT> ] ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( SETFOpc [ <NUM_LIT> ] ) , ResultReg ) . addReg ( FlagReg1 ) . addReg ( FlagReg2 ) ; updateValueMap ( I , ResultReg ) ; return true ; } <STR_LIT> CC ; bool SwapArgs ; std :: tie ( CC , SwapArgs ) = <STR_LIT> ( Predicate ) ; assert ( CC <= <STR_LIT> && <STR_LIT> ) ; if ( SwapArgs ) std :: swap ( LHS , RHS ) ; if ( ! <ISA_LIT>FastEmitCompare ( LHS , RHS , VT , I -> getDebugLoc ( ) ) ) return false ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , ResultReg ) .


<s> MachineOperand StOp = MI -> getOperand ( MI -> getNumOperands ( ) - <NUM_LIT> ) ; if ( StOp . isReg ( ) && StOp . getReg ( ) == TfrDefR ) return false ; } if ( HII -> getAddrMode ( MI ) == <STR_LIT> ) return ( HII -> getBaseWithLongOffset ( MI ) >=


<s> const uint32_t * <ISA_LIT>BaseRegisterInfo :: getTLSCallPreservedMask ( const MachineFunction & MF ) const { assert ( MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . isTargetDarwin ( ) && <STR_LIT> ) ; return CSR_iOS_TLSCall_RegMask


<s> } Result = DAG . getTargetConstant ( CVal , Op . getValueType ( ) ) ; break ; } case 'S' : { if ( const GlobalAddressSDNode * GA = dyn_cast < GlobalAddressSDNode > ( Op ) ) { Result = DAG . getTargetGlobalAddress ( GA -> getGlobal ( ) , Op . getDebugLoc ( ) , GA -> getValueType ( <NUM_LIT> ) ) ; } else if ( const BlockAddressSDNode * BA = dyn_cast < BlockAddressSDNode > ( Op ) ) { Result = DAG . getTargetBlockAddress ( BA -> getBlockAddress ( ) , BA -> getValueType ( <NUM_LIT> ) ) ; } else if ( const ExternalSymbolSDNode * ES = dyn_cast < ExternalSymbolSDNode > ( Op ) ) { Result = DAG . getTargetExternalSymbol ( ES -> getSymbol ( ) , ES -> getValueType ( <NUM_LIT> ) ) ; } else return ; break ; } case 'Y' : if ( const ConstantFPSDNode * CFP = dyn_cast < ConstantFPSDNode > ( Op ) ) { if ( CFP -> isExactlyValue ( <NUM_LIT> ) ) { Result = DAG . getTargetConstantFP ( <NUM_LIT> , CFP -> getValueType ( <NUM_LIT> ) ) ; break ; } } return ; } if ( Result . getNode ( ) ) { Ops . push_back ( Result ) ; return ; } TargetLowering :: LowerAsmOperandForConstraint ( Op , Constraint , Ops , DAG


<s> case <STR_LIT> : return PerformCMOVCombine ( N , DAG , DCI ) ; case <STR_LIT> : return PerformAddCombine ( N , DAG , Subtarget ) ; case <STR_LIT> : return PerformSubCombine ( N , DAG , Subtarget ) ; case <STR_LIT> : return PerformADCCombine ( N , DAG , DCI ) ; case <STR_LIT> : return PerformMulCombine ( N , DAG , DCI ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return PerformShiftCombine ( N , DAG , Subtarget ) ; case <STR_LIT> : return PerformAndCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformOrCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformXorCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformLOADCombine ( N , DAG , Subtarget ) ; case <STR_LIT> : return PerformSTORECombine ( N , DAG , Subtarget ) ; case <STR_LIT> : return PerformSINT_TO_FPCombine ( N , DAG , this ) ; case <STR_LIT> : return PerformFADDCombine ( N , DAG , Subtarget ) ; case <STR_LIT> : return PerformFSUBCombine ( N , DAG ,


<s> if ( Trace ) dbgs ( ) << <STR_LIT> << PrintReg ( Reg , & ME . TRI ) << <STR_LIT> ; for ( const MachineInstr & UseI : MRI . use_nodbg_instructions ( Reg ) ) { if ( ! InstrExec . count


<s> BB -> moveAfter ( JTBB ) ; OldPrior -> updateTerminator ( ) ; BB -> updateTerminator ( ) ; MF -> RenumberBlocks ( ) ; ++ NumJTMoved ; return nullptr ; } MachineBasicBlock * NewBB = MF -> CreateMachineBasicBlock ( JTBB -> getBasicBlock ( ) ) ; MachineFunction :: iterator MBBI = ++ JTBB -> getIterator ( ) ; MF -> insert ( MBBI , NewBB ) ; if ( isThumb2 ) BuildMI ( NewBB , DebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addMBB ( BB ) . addImm ( <STR_LIT> ) . addReg ( <NUM_LIT> ) ; else BuildMI ( NewBB , DebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addMBB ( BB ) . addImm ( <STR_LIT>


<s> DebugLoc dl = ( MBBI != MBB . end ( ) ? MBBI -> getDebugLoc ( ) : DebugLoc ( ) ) ; bool FP = hasFP ( MF ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addGlobalAddress ( MF . getFunction ( ) ) . addReg ( <STR_LIT> ) . addImm ( ++ curgpdist ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addGlobalAddress ( MF . getFunction ( ) ) . addReg ( <STR_LIT> ) . addImm ( curgpdist ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) ) . addGlobalAddress ( MF . getFunction ( ) ) ; long NumBytes = MFI -> getStackSize ( ) ; if ( FP ) NumBytes += <NUM_LIT> ; if ( NumBytes == <NUM_LIT> ) return ; unsigned Align = getStackAlignment ( ) ; NumBytes = ( NumBytes + Align - <NUM_LIT> ) / Align * Align ; MFI -> setStackSize ( NumBytes ) ; NumBytes = - NumBytes ; if ( NumBytes >= <STR_LIT> ) { BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addImm ( NumBytes ) . addReg ( <STR_LIT> ) ; } else if ( getUpper16 ( NumBytes ) >= <STR_LIT> ) { BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addImm ( getUpper16 ( NumBytes ) ) . addReg ( <STR_LIT> ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addImm ( getLower16 ( NumBytes ) ) . addReg ( <STR_LIT> ) ; }


<s> MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; MachineBasicBlock :: iterator MBBI = prior ( MBB . end ( ) ) ; DebugLoc dl = MBBI -> getDebugLoc ( ) ; int FrameSize = MFI -> getStackSize ( ) ; assert ( FrameSize % <NUM_LIT> == <NUM_LIT> && <STR_LIT> ) ; if ( ! hasFP (


<s> std :: swap ( V1 , V2 ) ; SwappedOps = true ; } if ( V1 . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; if ( V1 . getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; SDValue Src = V1 . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ; MVT SrcVT = Src . getSimpleValueType ( ) ; if ( ! SrcVT . is512BitVector ( ) && ! Subtarget . hasVLX ( ) ) return SDValue ( ) ; if ( SrcVT . getVectorElementType ( ) == <STR_LIT> && VT == <STR_LIT> && ! Subtarget . hasBWI ( )


<s> if ( const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( getMemDisp ( ) ) ) Inst . addOperand ( MCOperand :: createImm ( CE -> getValue ( ) ) ) ; else Inst . addOperand ( MCOperand :: createExpr


<s> const uint64_t F = MI -> getDesc ( )


<s> if ( ! isImm ( ) ) return false ; const MCConstantExpr * MCE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; if ( ! MCE ) return false ; int64_t Val = MCE -> getValue ( ) ; int64_t Shift = Bits - <NUM_LIT>


<s> unsigned Reg1 = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Reg2 = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; MI -> getOperand ( <NUM_LIT> ) . setReg ( Reg2 ) ; MI -> getOperand ( <NUM_LIT> ) . setReg ( Reg1 ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( MI -> dump ( ) ) ; break ; } case SHValues :: SH_COPYWIDEN : { MachineInstr * MI = SwapVector [ EntryIdx ] . VSEMI ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( MI -> dump ( ) ) ; unsigned DstReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; const TargetRegisterClass * DstRC = MRI -> getRegClass ( DstReg ) ; unsigned NewVReg = MRI -> createVirtualRegister ( DstRC ) ; MI -> getOperand ( <NUM_LIT> ) . setReg ( NewVReg ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( MI -> dump ( ) ) ; auto InsertPoint = ++ MachineBasicBlock :: iterator ( MI ) ; if ( DstRC == & <STR_LIT> ) { unsigned VSRCTmp1 = MRI -> createVirtualRegister ( & <STR_LIT> ) ; unsigned VSRCTmp2 = MRI -> createVirtualRegister


<s> assert ( llvm :: is_sorted ( MemoryFoldTable4 ) && std :: adjacent_find ( std :: begin ( MemoryFoldTable4 ) , std :: end ( MemoryFoldTable4 ) ) == std :: end ( MemoryFoldTable4 ) && <STR_LIT> ) ; assert ( llvm :: is_sorted ( BroadcastFoldTable2 ) && std :: adjacent_find ( std :: begin ( BroadcastFoldTable2 ) , std :: end ( BroadcastFoldTable2 ) ) == std :: end ( BroadcastFoldTable2 ) && <STR_LIT> ) ; assert ( llvm :: is_sorted ( BroadcastFoldTable3 ) && std :: adjacent_find ( std :: begin ( BroadcastFoldTable3 ) , std :: end ( BroadcastFoldTable3 ) ) == std :: end ( BroadcastFoldTable3 ) && <STR_LIT> ) ; FoldTablesChecked . store ( true , std :: memory_order_relaxed ) ; } const <ISA_LIT>MemoryFoldTableEntry * Data = llvm :: lower_bound ( Table , RegOp ) ; if ( Data != Table . end ( ) && Data -> KeyOp == RegOp && ! ( Data -> Flags & TB_NO_FORWARD ) ) return Data ; return


<s> SDLoc DL ( N ) ; <STR_LIT> CC = <STR_LIT> ( N -> getConstantOperandVal ( <NUM_LIT> ) ) ; SDValue EFLAGS = N -> getOperand ( <NUM_LIT> ) ; if ( CC == <STR_LIT> ) { if ( EFLAGS . getOpcode ( ) == <STR_LIT> && EFLAGS . hasOneUse ( ) && EFLAGS . getValueType ( ) . isInteger ( ) && ! isa < ConstantSDNode > ( EFLAGS . getOperand ( <NUM_LIT> ) ) ) { SDValue NewSub = DAG . getNode ( <STR_LIT> , SDLoc ( EFLAGS ) , EFLAGS . getNode ( ) -> getVTList ( ) , EFLAGS . getOperand ( <NUM_LIT> ) , EFLAGS . getOperand ( <NUM_LIT> ) ) ; SDValue NewEFLAGS = SDValue ( NewSub . getNode ( ) , EFLAGS . getResNo ( ) ) ; return MaterializeSETB ( DL , NewEFLAGS , DAG , N


<s> DCI . AddToWorklist ( N ) ; return SDValue ( N , <NUM_LIT> ) ; } if ( Index . getOpcode ( ) == <STR_LIT> && Index . getScalarValueSizeInBits ( ) == <NUM_LIT> && Index . getOperand ( <NUM_LIT> ) . getScalarValueSizeInBits ( ) == <NUM_LIT> ) { if ( DAG . SignBitIsZero ( Index . getOperand ( <NUM_LIT> ) ) ) { SmallVector < SDValue , <NUM_LIT> > NewOps ( N -> op_begin ( ) , N -> op_end ( ) ) ; NewOps [ <NUM_LIT> ] = Index . getOperand ( <NUM_LIT> ) ; DAG . UpdateNodeOperands ( N , NewOps ) ; DCI . AddToWorklist ( Index . getNode ( ) ) ; DCI . AddToWorklist ( N ) ; return SDValue ( N , <NUM_LIT> ) ; } } } if ( ! Subtarget . hasAVX512 ( ) ) { const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; TargetLowering :: TargetLoweringOpt TLO ( DAG , ! DCI . isBeforeLegalize ( ) , ! DCI . isBeforeLegalizeOps ( ) ) ; SDValue Mask = N -> getOperand ( <NUM_LIT> ) ; KnownBits Known ; APInt DemandedMask ( APInt :: getSignMask ( Mask . getScalarValueSizeInBits ( ) ) ) ; if ( TLI . SimplifyDemandedBits ( Mask , DemandedMask , Known ,


<s> bool isMemOffs16 ( ) const { return Kind == Memory && ! getMemSegReg ( ) && ! getMemBaseReg ( ) && ! getMemIndexReg ( ) && getMemScale (

) == <NUM_LIT> && ( ! Mem . Size || Mem . Size == <NUM_LIT> ) ;


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , Optional < CodeModel :: Model > CM , CodeGenOpt :: Level OL , bool isLittle ) : LLVMTargetMachine ( T , computeDataLayout ( TT , CPU , Options , isLittle ) , TT , CPU , FS , Options , getEffectiveRelocModel ( CM , RM ) , CodeModel :: Medium , OL ) , isLittle ( isLittle ) , TLOF ( make_unique < <ISA_LIT>TargetObjectFile > ( ) ) ,

ABI ( <ISA_LIT>ABIInfo :: computeTargetABI ( ) ) , DefaultSubtarget ( TT , CPU , FS , isLittle , * this ) {


<s> const MCOperandInfo & OpInfo = get ( MI -> getOpcode ( ) ) . OpInfo [ OpNo ] ; assert ( MO . isImm ( ) || MO . isTargetIndex ( ) || MO . isFI ( ) ) ; if ( OpInfo . OperandType == MCOI :: OPERAND_IMMEDIATE ) return true ; if ( OpInfo . RegClass <


<s> bool mayNeedRelaxation ( const MCInst & Inst , const MCSubtargetInfo


<s> return ( int8x8_t ) __builtin_neon_vreinterpretv8qiv8qi ( ( int8x8_t


<s> par -> inner_mask = nvptx_process_pars ( par -> inner ) ; inner_mask |= par -> inner_mask ; } if ( par -> mask & GOMP_DIM_MASK ( GOMP_DIM_MAX ) ) ; else if ( par -> mask & GOMP_DIM_MASK ( GOMP_DIM_WORKER ) ) { nvptx_wpropagate ( false , par -> forked_block , par -> forked_insn ) ; nvptx_wpropagate ( true , par -> forked_block , par -> fork_insn ) ; emit_insn_after ( nvptx_wsync ( false ) , par -> forked_insn ) ; emit_insn_before ( nvptx_wsync ( true ) , par -> joining_insn ) ; } else if ( par -> mask & GOMP_DIM_MASK ( GOMP_DIM_VECTOR ) ) nvptx_vpropagate ( par -> forked_block , par -> forked_insn ) ; if ( par -> next ) inner_mask |=


<s> void <ISA_LIT>InstPrinter :: printSDWADstUnused ( const MCInst * MI , unsigned OpNo , raw_ostream & O ) { O << <STR_LIT> ; unsigned Imm = MI -> getOperand ( OpNo ) . getImm ( ) ; switch ( Imm ) { case <NUM_LIT> : O << <STR_LIT>


<s> } bool fixedPreHd = fixupLoopPreheader ( MF ) ; bool fixedLatch = fixupLoopLatch ( MF ) ; bool fixedInstr = fixupLoopInstrs ( MF ) ; for ( MachineBasicBlock & MBB : MF ) { unsigned instrs = <NUM_LIT> ; for ( MachineInstr & MI : MBB ) { instrs ++ ; if ( isHardwareLoop ( MI ) && instrs > <NUM_LIT> ) { MachineBasicBlock * New = splitMBBAt ( & MBB , MI


<s> APInt DemandedElts = APInt :: getAllOnesValue ( VF ) ; TTI :: TargetCostKind CostKind = TTI :: TCK_RecipThroughput ; int MaskUnpackCost = <NUM_LIT> ; if ( VariableMask ) { VectorType * MaskTy = VectorType :: get ( Type :: getInt1Ty ( SrcVTy -> getContext ( ) ) , VF ) ; MaskUnpackCost = getScalarizationOverhead ( MaskTy , DemandedElts , false , true ) ; int ScalarCompareCost = getCmpSelInstrCost ( Instruction :: ICmp , Type :: getInt1Ty ( SrcVTy -> getContext ( ) ) , nullptr , CostKind ) ; int BranchCost = getCFInstrCost ( Instruction :: Br , CostKind ) ; MaskUnpackCost += VF * ( BranchCost + ScalarCompareCost ) ; } int MemoryOpCost = VF * getMemoryOpCost ( Opcode , SrcVTy -> getScalarType ( ) , MaybeAlign ( Alignment ) , AddressSpace , CostKind ) ; int InsertExtractCost = <NUM_LIT> ; if ( Opcode == Instruction :: Load ) for ( unsigned i = <NUM_LIT> ; i < VF ; ++ i ) InsertExtractCost += getVectorInstrCost ( Instruction ::


<s> if ( * cum < <NUM_LIT> ) return gen_rtx_REG ( arg . mode , * cum + <NUM_LIT> ) ; else return


<s> } else { switch ( Pred -> getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : { auto * PredMask = MRI -> getUniqueVRegDef ( Pred -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; if ( Mask != PredMask ) return false ; NewOp = Pred -> getOpcode ( ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; OpChanged = true ; break ; } case <STR_LIT> : { auto * PredMask = MRI -> getUniqueVRegDef ( Pred -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; if ( Mask != PredMask ) return false ; NewOp = <STR_LIT> ; OpChanged = true ; break ; } case <STR_LIT> : { auto * PredMask = MRI -> getUniqueVRegDef ( Pred -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; if ( Mask != PredMask ) return false ; NewOp = <STR_LIT> ; OpChanged = true ; break ; } default : return false ; } } const TargetRegisterInfo * TRI = & getRegisterInfo ( ) ; if ( areCFlagsAccessedBetweenInstrs ( Pred , PTest , TRI ) ) return false ; Pred -> setDesc ( get ( NewOp ) ) ; PTest -> eraseFromParent ( ) ; if ( OpChanged ) { bool succeeded = UpdateOperandRegClass ( * Pred ) ; ( void ) succeeded ; assert ( succeeded && <STR_LIT>


<s> HasAES = false ; HasFXSR = false ; HasXSAVE = false ; HasXSAVEOPT = false ; HasXSAVEC = false ; HasXSAVES = false ; HasPCLMUL = false ; HasFMA = false ; HasFMA4 = false ; HasXOP = false ; HasTBM = false ; HasLWP = false ; HasMOVBE = false ; HasRDRAND = false ; HasF16C = false ; HasFSGSBase = false ; HasLZCNT = false ; HasBMI = false ; HasBMI2 = false ; HasVBMI = false ; HasIFMA = false ; HasRTM = false ; HasERI = false ; HasCDI = false ; HasPFI = false ; HasDQI = false ; HasVPOPCNTDQ = false ; HasBWI = false ; HasVLX = false ; HasADX = false ; HasPKU = false ; HasSHA = false ; HasPRFCHW = false ; HasRDSEED = false ; HasLAHFSAHF = false ; HasMWAITX = false


<s> static const __vector unsigned int mask = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; __v4sf a , b , c ; a = vec_splat ( ( __v4sf ) __A , <NUM_LIT> ) ; b = vec_splat ( ( __v4sf ) __B , <NUM_LIT> ) ; c = ( __v4sf ) vec_cmpgt ( a , b ) ; return ( ( __m128 ) vec_sel ( ( __v4sf ) __A ,


<s> const auto info = m_vector_manager -> vector_insn_infos [ INSN_UID ( rinsn ) ] ; emit_vsetvl_insn ( VSETVL_DISCARD_RESULT , EMIT_BEFORE , info , NULL_RTX , rinsn


<s> <ISA_LIT>TargetStreamer & RTS = static_cast < <ISA_LIT>TargetStreamer & > ( * OutStreamer -> getTargetStreamer ( ) ) ; const Triple & TT = TM . getTargetTriple ( ) ; StringRef CPU = TM


<s> for ( MCSubRegIterator I ( <STR_LIT> , this , true ) ; I . isValid ( ) ; ++ I ) Reserved . set ( * I ) ; } if ( hasBasePointer ( MF ) ) { CallingConv :: ID CC = MF . getFunction ( ) -> getCallingConv ( ) ; const uint32_t * RegMask = getCallPreservedMask ( MF , CC ) ; if ( MachineOperand :: clobbersPhysReg ( RegMask , getBaseRegister ( ) ) ) report_fatal_error ( <STR_LIT> <STR_LIT> ) ; unsigned BasePtr = get<ISA_LIT>SubSuperRegister ( getBaseRegister ( ) , <STR_LIT> , false ) ; for ( MCSubRegIterator I ( BasePtr , this , true ) ; I . isValid ( ) ; ++ I ) Reserved . set ( * I ) ; } Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; for ( unsigned n = <NUM_LIT> ; n != <NUM_LIT> ; ++ n ) Reserved . set ( <STR_LIT> + n ) ; if ( ! Is64Bit ) { Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; for ( unsigned n = <NUM_LIT> ; n != <NUM_LIT> ; ++ n ) { for ( MCRegAliasIterator AI ( <STR_LIT> + n , this , true ) ; AI . isValid ( ) ; ++ AI ) Reserved . set ( * AI ) ; for ( MCRegAliasIterator AI ( <STR_LIT> + n , this , true ) ; AI . isValid ( ) ; ++ AI ) Reserved . set ( * AI ) ; } } if ( ! Is64Bit || ! MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . hasAVX512 ( ) ) { for ( unsigned n = <NUM_LIT> ; n != <NUM_LIT> ; ++ n ) { for ( MCRegAliasIterator AI ( <STR_LIT> + n , this , true ) ; AI . isValid ( ) ; ++ AI ) Reserved . set ( * AI ) ; } } const <ISA_LIT>Subtarget & Subtarget = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; const bool RestrictR15 = FlagRestrictR15 ; assert ( FlagUseZeroBasedSandbox || RestrictR15 ) ; if ( Subtarget . isTargetNaCl64 ( ) ) { if ( RestrictR15 ) { Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; } Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT>


<s> if ( CONST_INT_P ( operands [ <NUM_LIT> ] ) ) { split_double_mode ( mode , operands , <NUM_LIT> , low , high ) ; count = INTVAL ( operands [ <NUM_LIT> ] ) & ( GET_MODE_BITSIZE ( mode ) - <NUM_LIT> ) ; if ( count >= half_width ) { emit_move_insn ( low [ <NUM_LIT> ] , high [ <NUM_LIT> ] ) ; ix86_expand_clear ( high [ <NUM_LIT> ] ) ; if ( count > half_width ) emit_insn ( gen_lshr3 ( low [ <NUM_LIT> ] , low [ <NUM_LIT> ] , GEN_INT ( count - half_width ) ) ) ; } else { gen_shrd = mode == DImode ? gen_x86_shrd : gen_x86_64_shrd ; if ( ! rtx_equal_p ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ) emit_move_insn ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ; emit_insn ( gen_shrd ( low [ <NUM_LIT> ] , high [ <NUM_LIT> ] , GEN_INT ( count ) ) ) ; emit_insn ( gen_lshr3 ( high [ <NUM_LIT> ] , high [ <NUM_LIT> ] , GEN_INT ( count ) ) ) ; } } else { machine_mode half_mode ; gen_shrd = mode == DImode ? gen_x86_shrd : gen_x86_64_shrd ; if ( ! rtx_equal_p ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ) emit_move_insn ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ; split_double_mode ( mode , operands , <NUM_LIT> , low , high


<s> RC = CurDAG -> getTargetConstant ( <STR_LIT> , DL , <STR_LIT> ) ; SubReg0 = CurDAG -> getTargetConstant ( <STR_LIT> , DL , <STR_LIT> ) ; SubReg1 = CurDAG -> getTargetConstant ( <STR_LIT> , DL , <STR_LIT> ) ; } else { llvm_unreachable ( <STR_LIT> ) ; } const SDValue Ops [ ] = { RC , N -> getOperand ( <NUM_LIT> ) , SubReg0 , N -> getOperand ( <NUM_LIT> ) , SubReg1 } ; ReplaceNode ( N , CurDAG -> getMachineNode ( TargetOpcode :: REG_SEQUENCE , DL , N -> getValueType ( <NUM_LIT> ) , Ops ) ) ; return ; } case <STR_LIT> : case <STR_LIT> : { if ( N -> getValueType ( <NUM_LIT> ) . getSizeInBits ( ) != <NUM_LIT> || isInlineImmediate ( N ) ) break ; uint64_t Imm ; if ( ConstantFPSDNode * FP = dyn_cast < ConstantFPSDNode > ( N ) ) Imm = FP -> getValueAPF ( ) . bitcastToAPInt ( ) . getZExtValue ( ) ; else { ConstantSDNode * C = cast < ConstantSDNode > ( N ) ; Imm = C -> getZExtValue ( ) ; } SDLoc DL ( N ) ; ReplaceNode ( N , buildSMovImm64 ( DL , Imm , N -> getValueType ( <NUM_LIT> ) ) ) ; return ; } case <STR_LIT> : case <STR_LIT> : { ConstantSDNode * Offset = dyn_cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ; if ( ! Offset ) break ; ConstantSDNode * Width = dyn_cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ; if ( ! Width ) break ; bool Signed = Opc == <STR_LIT> ; uint32_t OffsetVal = Offset -> getZExtValue ( ) ; uint32_t WidthVal = Width -> getZExtValue ( ) ; ReplaceNode ( N , getBFE32 ( Signed , SDLoc ( N ) , N -> getOperand ( <NUM_LIT> ) , OffsetVal , WidthVal ) ) ; return ; } case <STR_LIT> : { SelectDIV_SCALE ( N ) ; return ; } case <STR_LIT> : case <STR_LIT> : { SelectMAD_64_32 ( N ) ; return ; } case <STR_LIT> : case <STR_LIT> : return SelectMUL_LOHI ( N ) ; case <STR_LIT> : { const <ISA_LIT>TargetLowering & Lowering = * static_cast < const <ISA_LIT>TargetLowering * > ( getTargetLowering ( ) ) ; N = Lowering . legalizeTargetIndependentNode ( N , * CurDAG ) ; break ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( N -> getValueType ( <NUM_LIT> ) != <STR_LIT> ) break ; SelectS_BFE ( N ) ; return ; case <STR_LIT> : SelectBRCOND ( N ) ; return ; case <STR_LIT> : case <STR_LIT> : SelectFMAD_FMA ( N )


<s> if ( OutMI . getOpcode ( ) == <STR_LIT> ) { OutMI . setOpcode ( <STR_LIT> ) ; OutMI . addOperand ( MCOperand :: createImm ( <STR_LIT> ( <STR_LIT> ) -> Encoding ) ) ; OutMI . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ; return ; } if ( OutMI . getOpcode ( ) == <STR_LIT> ) { OutMI . setOpcode ( <STR_LIT>


<s> I != E ; ++ I ) { if ( ! V . count ( * I ) ) { _rdfs ( * I , V , order ) ; } } n -> num = order . size ( ) ; order . push_back (


<s> static const SpillSlot Offsets [ ] = { { <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> } } ; NumEntries = array_lengthof


<s> if ( V . getOpcode ( ) != <STR_LIT> ) continue ; if ( ( Size % V . getNumOperands ( ) ) == <NUM_LIT> ) { int Scale = Size / V -> getNumOperands ( ) ; SDValue Op = V . getOperand ( M / Scale ) ; if ( Op . isUndef ( ) || <STR_LIT> ( Op ) ) Zeroable [ i ] = true ; else if ( ConstantSDNode * Cst = dyn_cast < ConstantSDNode > ( Op ) ) { APInt Val = Cst -> getAPIntValue ( ) ; Val = Val . lshr ( ( M % Scale ) * ScalarSizeInBits ) ; Val = Val . getLoBits ( ScalarSizeInBits ) ; Zeroable [ i ] = ( Val == <NUM_LIT> ) ; } else if ( ConstantFPSDNode * Cst = dyn_cast < ConstantFPSDNode > ( Op ) ) { APInt Val = Cst -> getValueAPF ( ) . bitcastToAPInt ( ) ; Val = Val . lshr ( ( M % Scale ) * ScalarSizeInBits ) ; Val = Val . getLoBits ( ScalarSizeInBits ) ; Zeroable [ i ] = (


<s> Op -> PostIdxReg . isAdd = isAdd ; Op -> PostIdxReg . ShiftTy = ShiftTy ; Op -> PostIdxReg . ShiftImm = ShiftImm ; Op -> StartLoc


<s> if ( align_p ) strcat ( pattern , <STR_LIT> ) ; noreturn_p = find_reg_note ( insn , REG_NORETURN , NULL_RTX ) != NULL_RTX ; if ( noreturn_p ) { if ( TARGET_16_BIT ) strcat ( pattern , <STR_LIT> ) ; else strcat ( pattern


<s> return SYMBOL_REF_TDA_P ( addr ) ; case REG : return REGNO ( addr ) == EP_REGNUM ; case PLUS : op0 = XEXP ( addr , <NUM_LIT> ) ; op1 = XEXP ( addr , <NUM_LIT> ) ; if ( GET_CODE ( op1 ) == CONST_INT && INTVAL ( op1 ) < max_offset && INTVAL ( op1 ) >= <NUM_LIT> && ( INTVAL ( op1 ) & mask )


<s> case ELF :: R_<ISA_LIT>_GOT_LO32 : case ELF :: R_<ISA_LIT>_GOTOFF_HI32 : case ELF :: R_<ISA_LIT>_GOTOFF_LO32 : case ELF :: R_<ISA_LIT>_TLS_GD_HI32 : case ELF ::


<s> <ISA_LIT>LowerI1Copies ( ) : MachineFunctionPass ( ID ) { initialize<ISA_LIT>LowerI1CopiesPass ( * PassRegistry :: getPassRegistry ( )


<s> { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , } ; bool Is64Bit = SrcVT == <STR_LIT> ; if ( I -> getType ( ) -> isDoubleTy ( ) ) { Opcode = IsSigned ? SCvtOpc [ HasAVX512 ] [ <NUM_LIT> ] [ Is64Bit ] : UCvtOpc [ <NUM_LIT> ] [ Is64Bit ] ; } else if ( I -> getType ( ) -> isFloatTy ( ) ) { Opcode = IsSigned ? SCvtOpc [ HasAVX512 ] [ <NUM_LIT> ] [ Is64Bit ] : UCvtOpc [ <NUM_LIT> ] [ Is64Bit ] ; } else return false ; MVT DstVT = TLI . getValueType ( DL , I -> getType ( ) ) . getSimpleVT ( ) ; const TargetRegisterClass * RC = TLI . getRegClassFor ( DstVT ) ; unsigned ImplicitDefReg = createResultReg ( RC ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: IMPLICIT_DEF ) , ImplicitDefReg ) ; unsigned ResultReg = fastEmitInst_rr ( Opcode , RC , ImplicitDefReg , true , OpReg , false ) ; updateValueMap ( I , ResultReg ) ; return


<s> bool <ISA_LIT>TTIImpl :: isLegalMaskedScatter ( Type * DataType , Align Alignment ) { if ( ! ST -> hasAVX512 ( ) ) return false ; return isLegalMaskedGather ( DataType


<s> return ( int16x4_t ) __builtin_neon_vreinterpretv4hiv8qi (


<s> MachineRegisterInfo & MRI = MBB . getParent ( ) -> getRegInfo ( ) ; const TargetRegisterInfo & TRI = * MRI . getTargetRegisterInfo ( ) ; const TargetRegisterClass & RC = * MRI . getRegClass ( DstReg ) ; assert ( Cond . size ( ) == <NUM_LIT> && <STR_LIT> ) ; unsigned Opc = getCMovFromCond ( ( <STR_LIT> ) Cond [ <NUM_LIT> ] . getImm ( ) , TRI . getRegSizeInBits (


<s> Register DefReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; Register SrcReg = IsCopy ? MI -> getOperand ( <NUM_LIT> ) . getReg ( ) : Register ( ) ; int64_t SrcImm = IsMoveImm ? MI -> getOperand ( <NUM_LIT> ) . getImm ( ) : <NUM_LIT> ; if ( ! MRI -> isReserved ( DefReg ) && ( ( IsCopy && ( SrcReg == <STR_LIT> || SrcReg == <STR_LIT> ) ) || IsMoveImm ) ) { for ( RegImm & KnownReg : KnownRegs ) { if ( KnownReg . Reg != DefReg && ! TRI -> isSuperRegister ( DefReg , KnownReg . Reg ) ) continue ; if ( IsCopy && KnownReg . Imm != <NUM_LIT> ) continue ; if ( IsMoveImm ) { if ( KnownReg . Imm != SrcImm ) continue ; MCPhysReg CmpReg = KnownReg . Reg ; if ( any_of ( MI -> implicit_operands ( ) , [ CmpReg ] ( MachineOperand & O ) { return ! O . isDead ( ) && O . isReg ( ) && O . isDef ( ) && O . getReg ( ) != CmpReg ; } ) ) continue ; } if ( IsCopy ) LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * MI ) ; else LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * MI ) ; MI -> eraseFromParent ( ) ; Changed = true ; LastChange = I ; NumCopiesRemoved ++ ; UsedKnownRegs . insert ( KnownReg . Reg ) ; RemovedMI = true ; break ; } } } if ( RemovedMI ) continue ; for ( unsigned RI = <NUM_LIT> ; RI < KnownRegs . size ( ) ; ) if ( MI -> modifiesRegister


<s> MCAsmParser & getParser ( ) const { return Parser


<s> unsigned FromOpc = ReduceTable [ i ] . WideOpc ; if ( ! ReduceOpcodeMap . insert ( std :: make_pair ( FromOpc , i

) ) . second ) assert ( false && <STR_LIT> ) ;


<s> AsmPrinter :: doInitialization ( M ) ; if ( MAI -> doesSupportDebugInformation ( ) && ! empty (


<s> MCELFObjectTargetWriter * MOTW = new


<s> emit_insn ( gen_blockage ( ) ) ; move_block_from_reg ( local_cum . regs_used + FIRST_ARG_REGNO , mem , regs_to_push ) ; emit_insn ( gen_blockage ( ) ) ; } pret_size = regs_to_push * UNITS_PER_WORD ; if ( pret_size ) *


<s> if ( ! MCE ) return false ; return <STR_LIT> ( ~ MCE -> getValue ( ) , <NUM_LIT>


<s> static void rs6000_xcoff_select_section ( tree decl , int reloc , unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED ) { if ( decl_readonly_section_1 ( decl , reloc , <NUM_LIT> ) ) { if ( TREE_PUBLIC ( decl ) ) read_only_data_section ( ) ; else read_only_private_data_section ( ) ; } else { if ( TREE_PUBLIC ( decl ) ) data_section


<s> FunctionPass * llvm :: create<ISA_LIT>RemoveExtendArgs ( const <ISA_LIT>TargetMachine & TM ) { return new <ISA_LIT>RemoveExtendArgs (


<s> rtx dst_reg , src_reg ; tree dst_expr , src_expr ; if ( ! CONST_INT_P ( bytes_rtx ) || INTVAL ( bytes_rtx ) <= <NUM_LIT> ) return <NUM_LIT> ; dst_reg = copy_addr_to_reg ( XEXP ( dst , <NUM_LIT> ) ) ; src_reg = copy_addr_to_reg ( XEXP ( src , <NUM_LIT> ) ) ; if ( align >= <NUM_LIT> ) expand_block_move_4 ( dst , dst_reg , src


<s> return ( __m128i ) __builtin_ia32_vpcomgtub ( ( __v16qi ) __A , (


<s> static unsigned getShuffleSHUFImmediate ( ShuffleVectorSDNode * N ) { EVT VT = N -> getValueType ( <NUM_LIT> ) ; assert ( ( VT . is128BitVector ( ) || VT . is256BitVector ( ) ) && <STR_LIT> ) ; unsigned NumElts = VT . getVectorNumElements ( ) ; unsigned NumLanes = VT . getSizeInBits ( ) / <NUM_LIT> ; unsigned NumLaneElts = NumElts


<s> bool <ISA_LIT>TargetLowering :: shouldExpandAtomicInIR ( Instruction * Inst ) const { if ( StoreInst * SI = dyn_cast < StoreInst > ( Inst ) ) return SI -> getValueOperand ( ) -> getType ( ) -> getPrimitiveSizeInBits ( ) == <NUM_LIT> ; else if ( LoadInst * LI = dyn_cast < LoadInst > ( Inst ) ) return LI -> getType ( ) -> getPrimitiveSizeInBits ( ) == <NUM_LIT> ; return Inst -> getType ( ) -> getPrimitiveSizeInBits ( ) <=


<s> O << <STR_LIT> << size << <STR_LIT> ; } else if ( isa < PointerType > ( retTy ) ) { O << <STR_LIT> << PtrVT . getSizeInBits ( ) << <STR_LIT> ; } else if ( retTy -> isAggregateType ( ) || retTy -> isVectorTy ( ) || retTy -> isIntegerTy ( <NUM_LIT> ) ) { O << <STR_LIT> << ( retAlignment ? retAlignment -> value ( ) : <NUM_LIT> ) << <STR_LIT> << DL . getTypeAllocSize ( retTy ) << <STR_LIT> ; } else { llvm_unreachable ( <STR_LIT> ) ; } O << <STR_LIT> ; } O << <STR_LIT> ; bool first = true ; unsigned OIdx = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> , e = Args . size ( ) ; i != e ; ++ i , ++ OIdx ) { Type * Ty = Args [ i ] . Ty ; if ( ! first ) { O << <STR_LIT> ; } first = false ; if ( ! Outs [ OIdx ] . Flags . isByVal ( ) ) { if ( Ty -> isAggregateType ( ) || Ty -> isVectorTy ( ) || Ty -> isIntegerTy ( <NUM_LIT> ) ) { unsigned align = <NUM_LIT> ; const CallInst * CallI = cast < CallInst > ( & CB ) ; if ( ! getAlign ( * CallI , i + <NUM_LIT> , align ) ) align = DL . getABITypeAlignment ( Ty ) ; unsigned sz = DL . getTypeAllocSize ( Ty ) ; O << <STR_LIT> <<


<s> const <ISA_LIT>FrameLowering * getFrameLowering ( ) const override { return & FrameLowering


<s> YamlStream << getLexer ( ) . getTok ( ) . getString ( ) ; Lex ( ) ; } if ( getLexer ( ) . is ( AsmToken :: Identifier ) ) { StringRef ID = getLexer ( ) . getTok ( ) . getIdentifier ( ) ; if ( ID == <STR_LIT> :: MetadataAssemblerDirectiveEnd ) { Lex ( ) ; FoundEnd = true ; break ; } } YamlStream << Parser . parseStringToEndOfStatement ( ) << getContext ( ) . getAsmInfo


<s> if ( MI . modifiesRegister ( BaseReg , TRI ) ) return false ; if ( isLdStPairSuppressed ( MI ) ) return false ; if ( Subtarget . isPaired128Slow ( ) ) { switch ( MI . getOpcode ( ) ) { default : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case


<s> if ( MI . getOpcode ( ) == <STR_LIT> ) Opc = <STR_LIT> ; else if ( MI . getOpcode ( ) == <STR_LIT> ) Opc = <STR_LIT> ; else if ( MI . getOpcode ( ) == <STR_LIT> ) Opc = <STR_LIT> ; else llvm_unreachable ( <STR_LIT> ) ; OriginalCall = BuildMI ( MBB , MBBI , MI . getDebugLoc ( ) , TII -> get ( Opc ) ) . getInstr ( ) ; bool RAXImplicitDead = false ; for ( MachineOperand & Op : llvm :: drop_begin ( MI . operands ( ) ) ) { if ( Op . isReg ( ) && Op . isImplicit ( ) && Op . isDead ( ) && TRI -> regsOverlap ( Op . getReg ( ) , <STR_LIT> ) ) { Op . setIsDead ( false ) ; Op . setIsDef (


<s> const MCInstrDesc & MCID = MII . get ( Opc ) ; if ( MCID . TSFlags & <STR_LIT> ) { assert ( MCID . hasOptionalDef ( ) && <STR_LIT> ) ; assert ( MCID . NumOperands == Inst . getNumOperands ( ) && <STR_LIT> ) ; unsigned OpNo ; for ( OpNo = <NUM_LIT> ; ! MCID . OpInfo [ OpNo ] . isOptionalDef ( ) && OpNo < MCID . NumOperands ; ++ OpNo ) ; if ( isThumbOne ( ) && Inst . getOperand ( OpNo ) . getReg ( ) != <STR_LIT> ) return Match_MnemonicFail ; if ( isThumbTwo ( ) && Inst . getOperand ( OpNo ) . getReg ( ) != <STR_LIT> && ! inITBlock ( ) ) return Match_RequiresITBlock ; if ( isThumbTwo ( ) && Inst . getOperand ( OpNo ) . getReg

( ) == <STR_LIT> && inITBlock ( ) ) return Match_RequiresNotITBlock ;


<s> MCRegister <ISA_LIT>ElfTargetObjectFile :: getStaticBase ( ) const


<s> Instruction * back ( ) const { return Chain . back (


<s> return BaseT :: getShuffleCost ( Kind , Tp , Index , SubTp


<s> LoadSDNode * LD = cast < LoadSDNode > ( N1 . getNode ( ) ) ; if ( StOp -> getOperand ( <NUM_LIT> ) != LD -> getOperand ( <NUM_LIT> ) ) return NULL ; MVT VT = LD -> getMemoryVT ( ) . getSimpleVT ( ) ; unsigned Opc = ( VT == <STR_LIT> ? Opc32 : VT == <STR_LIT> ? Opc16 : Opc8 ) ; MachineSDNode :: mmo_iterator MemRefs0 = MF -> allocateMemRefsArray ( <NUM_LIT> ) ; MemRefs0 [ <NUM_LIT> ] = cast < MemSDNode > ( N1 ) -> getMemOperand ( ) ; SDValue Ops0 [ ] = { LD -> getBasePtr ( ) , N2 , LD -> getChain ( ) } ; SDNode * ResNode = CurDAG -> SelectNodeTo ( StOp , Opc , <STR_LIT> , <STR_LIT> , Ops0 , <NUM_LIT> ) ; cast < MachineSDNode > ( ResNode ) -> setMemRefs ( MemRefs0 , MemRefs0 +


<s> void <ISA_LIT>InstPrinter :: printR128A16 ( const MCInst * MI , unsigned OpNo , const MCSubtargetInfo


<s> bool simplifyCode ( ) { bool Changed = false ; for ( unsigned i = <NUM_LIT> ; i < AllCRLogicalOps . size ( ) ;

i ++ ) Changed |= handleCROp ( AllCRLogicalOps [ i ] ) ;


<s> <ISA_LIT>EarlyIfConversion ( ) : MachineFunctionPass ( ID ) , TII ( <NUM_LIT> ) , TRI ( <NUM_LIT> ) , MFN (

<NUM_LIT> ) , MRI ( <NUM_LIT> ) , MDT ( <NUM_LIT> ) , MLI ( <NUM_LIT> ) {


<s> if ( NumElts == <NUM_LIT> ) { Index = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Index ) ; SDValue Ops [ ] = { N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , Index } ; DAG . UpdateNodeOperands ( N , Ops ) ; return Op ; } NumElts = <NUM_LIT> ; MVT NewIndexVT = <STR_LIT> ( IndexVT . getScalarType ( ) , NumElts ) ; Index = ExtendToType ( Index , NewIndexVT , DAG ) ; if ( IndexVT . getScalarType ( ) == <STR_LIT> ) Index = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Index ) ; MVT MaskBitVT = <STR_LIT> ( <STR_LIT> , NumElts ) ; assert ( MaskVT . getScalarSizeInBits ( ) >= <NUM_LIT> && <STR_LIT> ) ; MVT ExtMaskVT = <STR_LIT> ( MaskVT . getScalarType ( ) , NumElts ) ; Mask = ExtendToType ( Mask , ExtMaskVT


<s> if ( VT . getVectorNumElements ( ) != <NUM_LIT> ) return false ; for ( unsigned i = <NUM_LIT> , e = <NUM_LIT> ; i != e ; ++ i ) if ( ! isUndefOrEqual ( Op -> getMaskElt ( i ) , i + <NUM_LIT> ) ) return false ; for ( unsigned i = <NUM_LIT> ; i != <NUM_LIT> ; ++ i ) if ( ! isUndefOrEqual ( Op -> getMaskElt ( i ) , i + <NUM_LIT> ) ) return false ; return


<s> return LowerGlobalAddress ( Op , DAG ) ; case <STR_LIT> : return LowerBUILD_VECTOR ( Op , DAG ) ; case <STR_LIT> : return LowerVECTOR_SHUFFLE ( Op , DAG ) ; case <STR_LIT> : return LowerINSERT_VECTOR_ELT ( Op , DAG ) ; case <STR_LIT> : return LowerEXTRACT_VECTOR_ELT ( Op , DAG ) ; case <STR_LIT> : return LowerSCALAR_TO_VECTOR ( Op , DAG ) ; case <STR_LIT> : return LowerSELECT_CC ( Op , DAG ) ; case <STR_LIT> : return LowerSELECT ( Op , DAG ) ; case <STR_LIT> : return LowerVSELECT ( Op , DAG ) ; case <STR_LIT> : return LowerSETCC ( Op , DAG ) ; case <STR_LIT> : return LowerConstantPool ( Op , DAG ) ; case <STR_LIT> : return LowerFDIV ( Op


<s> auto PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; if ( ( Offset & <NUM_LIT> ) == <NUM_LIT> ) { return DAG . getLoad ( PtrVT , DL , Chain , Base , MachinePointerInfo ( ) , false , false , false , <NUM_LIT> ) ; } int32_t HighOffset = alignTo ( Offset , <NUM_LIT> ) ; int32_t LowOffset = HighOffset - <NUM_LIT> ; SDValue LowAddr , HighAddr ; if ( GlobalAddressSDNode * GASD = dyn_cast < GlobalAddressSDNode > ( Base . getNode ( ) ) ) { LowAddr = DAG . getGlobalAddress ( GASD -> getGlobal ( ) , DL , Base . getValueType ( ) , LowOffset ) ; HighAddr = DAG . getGlobalAddress ( GASD -> getGlobal ( ) , DL , Base . getValueType ( ) , HighOffset ) ; } else { LowAddr = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Base , DAG . getConstant ( LowOffset , DL , <STR_LIT> ) ) ; HighAddr = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Base , DAG . getConstant ( HighOffset , DL , <STR_LIT> ) ) ; } SDValue LowShift = DAG . getConstant ( ( Offset - LowOffset ) * <NUM_LIT> , DL , <STR_LIT> ) ; SDValue HighShift = DAG . getConstant ( ( HighOffset - Offset ) * <NUM_LIT> , DL , <STR_LIT> ) ; SDValue Low = DAG . getLoad ( PtrVT , DL , Chain , LowAddr , MachinePointerInfo ( ) , false , false , false , <NUM_LIT> ) ; SDValue High = DAG . getLoad ( PtrVT , DL , Chain , HighAddr , MachinePointerInfo ( ) , false , false , false , <NUM_LIT> ) ; SDValue LowShifted = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Low , LowShift ) ; SDValue HighShifted = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , High , HighShift ) ; SDValue Result = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , LowShifted , HighShifted ) ; Chain = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Low . getValue ( <NUM_LIT> ) , High . getValue ( <NUM_LIT> ) ) ; SDValue Ops [ ] = {


<s> if ( ! first ) { O << <STR_LIT> ; } first = false ; if ( ! Outs [ OIdx ] . Flags . isByVal ( ) ) { if ( Ty -> isAggregateType ( ) || Ty -> isVectorTy ( ) || Ty -> isIntegerTy ( <NUM_LIT> ) ) { unsigned ParamAlign = <NUM_LIT> ; const CallInst * CallI = cast < CallInst > ( & CB ) ; if ( ! getAlign ( * CallI , i + <NUM_LIT> , ParamAlign ) ) ParamAlign = getFunctionParamOptimizedAlign ( F , Ty , DL ) . value ( ) ; O << <STR_LIT> << ParamAlign << <STR_LIT> ; O << <STR_LIT> ; O << <STR_LIT> << DL . getTypeAllocSize ( Ty ) << <STR_LIT> ; SmallVector < EVT , <NUM_LIT> > vtparts ; ComputeValueVTs ( * this , DL , Ty , vtparts ) ; if ( unsigned len = vtparts . size ( ) ) OIdx += len - <NUM_LIT> ; continue ; } assert ( ( getValueType ( DL , Ty ) == Outs [ OIdx ] . VT || ( getValueType ( DL , Ty ) == <STR_LIT> && Outs [ OIdx ] . VT == <STR_LIT> ) ) && <STR_LIT> ) ; unsigned sz = <NUM_LIT> ; if ( isa < IntegerType > ( Ty ) ) { sz = cast < IntegerType > ( Ty ) -> getBitWidth ( ) ; if ( sz < <NUM_LIT> ) sz = <NUM_LIT> ; } else if ( isa < PointerType > ( Ty ) ) { sz = PtrVT . getSizeInBits ( ) ; } else if ( Ty -> isHalfTy ( ) ) sz = <NUM_LIT> ; else sz = Ty -> getPrimitiveSizeInBits ( ) ; O << <STR_LIT> << sz << <STR_LIT> ; O << <STR_LIT> ; continue ; } Align ParamByValAlign = Outs [ OIdx ] . Flags . getNonZeroByValAlign ( ) ; Type * ETy = Args [ i ] . IndirectType ; Align AlignCandidate = getFunctionParamOptimizedAlign ( F , ETy , DL ) ; ParamByValAlign = std :: max ( ParamByValAlign , AlignCandidate ) ; O << <STR_LIT> << ParamByValAlign . value ( ) << <STR_LIT> ; O << <STR_LIT> ; O << <STR_LIT> << Outs [ OIdx ]

. Flags . getByValSize ( ) << <STR_LIT> ;


<s> else if ( from == ARG_POINTER_REGNUM && to == FRAME_POINTER_REGNUM ) ret = <NUM_LIT> ; else gcc_unreachable ( ) ; return


<s> if ( const IntrinsicInst * II = dyn_cast < IntrinsicInst > ( I ) ) { if ( readsLocalId ( II ) ) return true ; if ( readWorkgroupInvariant ( II ) ) return false ; if ( isPureFunction ( II ) ) return false ; } if ( isa < CallInst > ( I ) )


<s> MCInst const & getDesc ( ) const { return * ID


<s> return parseOptionalOps ( DSOptionalOpsOff01 ,


<s> AMDGPUAsmParser ( MCSubtargetInfo & STI , MCAsmParser & _Parser , const MCInstrInfo & MII , const MCTargetOptions & Options ) : MCTargetAsmParser ( ) , STI ( STI ) , MII ( MII ) , Parser ( _Parser ) , ForcedEncodingSize ( <NUM_LIT> ) { if ( STI . getFeatureBits ( ) . none ( ) ) { STI . ToggleFeature ( <STR_LIT>


<s> switch ( ID ) { case <STR_LIT> : NonKernelOnly = true ; return <STR_LIT> ; case <STR_LIT> : NonKernelOnly = true ; return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case


<s> const UUPair & P = F -> second ; int64_t Off = PostInc ? <NUM_LIT> : MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; LowI = BuildMI ( B , MI , DL , TII -> get ( <STR_LIT> ) , P . first ) . addReg ( AdrOp . getReg ( ) , RSA & ~ RegState :: Kill , AdrOp . getSubReg ( ) ) . addImm ( Off ) ; HighI = BuildMI ( B , MI , DL , TII -> get ( <STR_LIT> ) , P . second ) . addReg ( AdrOp . getReg ( ) , RSA & ~ RegState :: Kill , AdrOp . getSubReg ( ) ) . addImm ( Off + <NUM_LIT> ) ; } else { const UUPair & P = F -> second ; int64_t Off = PostInc ? <NUM_LIT> : MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; LowI = BuildMI ( B , MI , DL , TII -> get ( <STR_LIT> ) ) . addReg ( AdrOp . getReg ( ) , RSA & ~ RegState :: Kill , AdrOp . getSubReg ( ) ) . addImm ( Off ) . addReg ( P . first ) ; HighI = BuildMI ( B , MI , DL , TII -> get ( <STR_LIT> ) ) . addReg ( AdrOp . getReg ( ) , RSA & ~ RegState :: Kill , AdrOp . getSubReg ( ) ) . addImm ( Off + <NUM_LIT> ) . addReg ( P . second ) ; } if ( PostInc ) { int64_t Inc = Load ? MI -> getOperand ( <NUM_LIT> ) . getImm ( ) : MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; MachineOperand & UpdOp = Load ? MI -> getOperand ( <NUM_LIT> ) : MI -> getOperand ( <NUM_LIT> ) ; const TargetRegisterClass * RC = MRI -> getRegClass ( UpdOp . getReg ( ) ) ; Register NewR = MRI -> createVirtualRegister ( RC ) ; assert ( ! UpdOp . getSubReg ( ) && <STR_LIT> ) ; BuildMI ( B , MI , DL , TII -> get ( <STR_LIT> ) , NewR ) . addReg ( AdrOp . getReg ( ) , RSA ) . addImm ( Inc ) ; MRI -> replaceRegWith ( UpdOp . getReg ( ) , NewR ) ; } MachineFunction & MF = * B . getParent ( ) ; for ( auto & MO : MI -> memoperands ( ) ) { const MachinePointerInfo & Ptr = MO -> getPointerInfo ( ) ; MachineMemOperand :: Flags F = MO -> getFlags ( ) ; Align A = MO -> getAlign ( ) ; auto * Tmp1 = MF . getMachineMemOperand ( Ptr , F , <NUM_LIT> , A ) ; LowI -> addMemOperand ( MF


<s> return __builtin_mve_vaddq_m_sv8hi ( __arm_vuninitializedq_s16 ( ) ,


<s> return ( __m512i ) __builtin_ia32_psllv8di_mask ( ( __v8di ) __X , ( __v8di ) __Y , ( __v8di ) _mm512_undefined_pd ( ) , (


<s> DebugLoc DL ; if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; <ISA_LIT>MachineFunctionInfo * CFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; unsigned Opcode = <NUM_LIT> ; if ( <STR_LIT> . hasSubClassEq ( RC ) ) { Opcode = <STR_LIT> ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { Opcode = <STR_LIT> ; CFI -> setSpillsCR ( ) ; } else


<s> SDValue N0 = N -> getOperand ( <NUM_LIT> ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( ! DCI . isBeforeLegalizeOps ( ) && N -> getOpcode ( ) == <STR_LIT> && N0 . getOpcode ( ) == <STR_LIT> ) { SDValue Setcc = DAG . getNode ( <STR_LIT> , dl , VT , N0 -> getOperand ( <NUM_LIT> ) , N0 -> getOperand ( <NUM_LIT> ) ) ; bool ReplaceOtherUses = ! N0 . hasOneUse ( ) ; DCI . CombineTo ( N , Setcc ) ; if ( ReplaceOtherUses ) { SDValue Trunc = DAG . getNode ( <STR_LIT> , SDLoc ( N0 ) , N0 . getValueType ( ) , Setcc ) ; DCI . CombineTo ( N0 . getNode ( ) , Trunc ) ; } return SDValue ( N , <NUM_LIT> ) ; } if ( SDValue NewCMov = combineToExtendCMOV ( N , DAG ) ) return NewCMov ; if ( DCI . isBeforeLegalizeOps ( ) ) if ( SDValue V = combineExtSetcc ( N ,


<s> if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) { reportParseError ( <STR_LIT> ) ; return


<s> if ( rtx_equal_p ( cmp_op0 , if_true ) && rtx_equal_p ( cmp_op1 , if_false ) ) is_min = true ; else if ( rtx_equal_p ( cmp_op1 , if_true ) && rtx_equal_p ( cmp_op0 , if_false ) ) is_min = false ; else return false ; mode = GET_MODE ( dest ) ; if ( ! flag_finite_math_only || !


<s> MachineFunctionProperties getRequiredProperties (


<s> gcc_assert ( REG_P ( reg_1 ) && REG_P ( reg_2 ) && REG_P ( reg_3 ) && REG_P ( reg_4 ) ) ; if ( REGNO ( reg_1 ) == REGNO ( reg_2 ) || REGNO ( reg_3 ) == REGNO ( reg_4 ) ) return false ; } else { mem_1 = operands [ <NUM_LIT> ] ; reg_1 = operands [ <NUM_LIT> ] ; mem_2 = operands [ <NUM_LIT> ] ; reg_2 = operands [ <NUM_LIT> ] ; mem_3 = operands [ <NUM_LIT> ] ; reg_3 = operands [ <NUM_LIT> ] ; mem_4 = operands [ <NUM_LIT> ] ; reg_4 = operands [ <NUM_LIT> ] ; } if ( ! MEM_P ( mem_1 ) || aarch64_mem_pair_operand ( mem_1 , mode ) ) return false ; if ( MEM_VOLATILE_P ( mem_1 ) || MEM_VOLATILE_P ( mem_2 ) || MEM_VOLATILE_P ( mem_3 ) || MEM_VOLATILE_P ( mem_4 ) ) return false ; extract_base_offset_in_addr ( mem_1 , & base_1 , & offset_1 ) ; if ( base_1 == NULL_RTX || offset_1 == NULL_RTX ) return false ; extract_base_offset_in_addr ( mem_2 , & base_2 , & offset_2 ) ; if ( base_2 == NULL_RTX || offset_2 == NULL_RTX ) return false ; extract_base_offset_in_addr ( mem_3 , & base_3 , & offset_3 ) ; if ( base_3 == NULL_RTX || offset_3 == NULL_RTX ) return false ; extract_base_offset_in_addr ( mem_4 , & base_4 , & offset_4 ) ; if ( base_4 == NULL_RTX || offset_4 == NULL_RTX ) return false ; if ( ! rtx_equal_p ( base_1 , base_2 ) || ! rtx_equal_p ( base_2 , base_3 ) || ! rtx_equal_p ( base_3 , base_4 ) ) return false ; offval_1 = INTVAL ( offset_1 ) ; offval_2 = INTVAL ( offset_2 ) ; offval_3 = INTVAL ( offset_3 ) ; offval_4 = INTVAL ( offset_4 ) ; msize = GET_MODE_SIZE ( mode ) ; if ( ( offval_1 != ( offval_2 + msize ) || offval_1 != ( offval_3 + msize * <NUM_LIT> ) || offval_1 != ( offval_4 + msize * <NUM_LIT> ) ) && ( offval_4 != ( offval_3 + msize ) || offval_4 != ( offval_2 + msize * <NUM_LIT> ) || offval_4 != ( offval_1 + msize * <NUM_LIT> ) ) ) return false ; if ( load ) { if ( reg_mentioned_p ( reg_1 , mem_1 ) || reg_mentioned_p ( reg_2 , mem_2 ) || reg_mentioned_p ( reg_3 , mem_3 ) ) return false ; if ( offval_1 > offval_2 && reg_mentioned_p ( reg_4 , mem_4 ) ) return false ; } if ( mode == SImode && ( aarch64_tune_params . extra_tuning_flags & AARCH64_EXTRA_TUNE_SLOW_UNALIGNED_LDPW ) && ! optimize_size && MEM_ALIGN ( mem_1 ) < <NUM_LIT> * BITS_PER_UNIT ) return false ; if ( REG_P ( reg_1 ) && FP_REGNUM_P ( REGNO ( reg_1 ) ) ) rclass_1 = FP_REGS ; else rclass_1 = GENERAL_REGS ; if ( REG_P ( reg_2 ) && FP_REGNUM_P ( REGNO


<s> Value * <ISA_LIT>IREmitter :: visitVZEXT_MOVL ( const SDNode * N ) { llvm_unreachable ( <STR_LIT> ) ; return


<s> if ( cfun -> is_thunk ) { * imaskP = <NUM_LIT> ; * fmaskP = <NUM_LIT> ; return ; } if ( TARGET_ABI_OPEN_VMS && alpha_procedure_type == PT_STACK ) imask |= ( <NUM_LIT> << HARD_FRAME_POINTER_REGNUM ) ; for ( i = <NUM_LIT> ; i < FIRST_PSEUDO_REGISTER ; i ++ ) if ( ! fixed_regs [ i ] && ! call_used_regs [ i ] && df_regs_ever_live_p ( i ) && i != REG_RA ) { if ( i < <NUM_LIT> ) imask |= ( <NUM_LIT> << i ) ; else fmask |= ( <NUM_LIT> << ( i - <NUM_LIT> ) ) ; } if ( crtl -> calls_eh_return ) { for ( i = <NUM_LIT> ; ; ++ i ) { unsigned regno = EH_RETURN_DATA_REGNO ( i ) ; if ( regno == INVALID_REGNUM ) break ; imask |= <NUM_LIT> << regno ; } } if ( imask || fmask || alpha_ra_ever_killed ( ) ) imask |= (