<s> Offset = - Offset ; isSub = true ; MI . setDesc ( TII . get ( <STR_LIT> ) ) ; } if ( <STR_LIT> ( Offset ) != - <NUM_LIT> ) { MI . getOperand ( FrameRegIdx ) . ChangeToRegister ( FrameReg , false ) ; MI . getOperand ( FrameRegIdx + <NUM_LIT> ) . ChangeToImmediate ( Offset ) ; Offset = <NUM_LIT> ; return true ; } unsigned RotAmt = <STR_LIT> ( Offset ) ; unsigned ThisImmVal = Offset & <STR_LIT> ( <NUM_LIT> , RotAmt ) ; Offset &= ~ ThisImmVal ; assert ( <STR_LIT> ( ThisImmVal ) != - <NUM_LIT> && <STR_LIT> ) ; MI . getOperand ( FrameRegIdx + <NUM_LIT> ) . ChangeToImmediate ( ThisImmVal ) ; } else { unsigned ImmIdx = <NUM_LIT> ; int InstrOffs = <NUM_LIT> ; unsigned NumBits = <NUM_LIT> ; unsigned Scale = <NUM_LIT> ; switch ( AddrMode ) { case <STR_LIT> : ImmIdx = FrameRegIdx + <NUM_LIT> ; InstrOffs = MI . getOperand ( ImmIdx ) . getImm ( ) ; NumBits = <NUM_LIT> ; break ; case <STR_LIT> : ImmIdx = FrameRegIdx + <NUM_LIT> ; InstrOffs = <STR_LIT> ( MI . getOperand ( ImmIdx ) . getImm ( ) ) ; if ( <STR_LIT> ( MI . getOperand ( ImmIdx ) . getImm ( ) ) == <STR_LIT> ) InstrOffs *= - <NUM_LIT> ; NumBits = <NUM_LIT> ; break ; case <STR_LIT> : ImmIdx = FrameRegIdx + <NUM_LIT> ; InstrOffs = <STR_LIT> ( MI . getOperand ( ImmIdx ) . getImm ( ) ) ; if ( <STR_LIT> ( MI . getOperand ( ImmIdx ) . getImm ( ) ) == <STR_LIT> ) InstrOffs *= - <NUM_LIT> ; NumBits = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : return false ; case <STR_LIT> : ImmIdx = FrameRegIdx + <NUM_LIT> ; InstrOffs = <STR_LIT> ( MI . getOperand ( ImmIdx ) . getImm ( ) ) ; if ( <STR_LIT> ( MI . getOperand ( ImmIdx ) . getImm ( ) ) == <STR_LIT> ) InstrOffs *= - <NUM_LIT> ; NumBits = <NUM_LIT> ; Scale = <NUM_LIT> ; break ; case <STR_LIT> : ImmIdx = FrameRegIdx + <NUM_LIT> ; InstrOffs = <STR_LIT> ( MI . getOperand ( ImmIdx ) . getImm ( ) ) ; if ( <STR_LIT> ( MI . getOperand ( ImmIdx ) . getImm ( ) ) == <STR_LIT> ) InstrOffs *= - <NUM_LIT> ; NumBits = <NUM_LIT> ; Scale = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : ImmIdx = FrameRegIdx + <NUM_LIT> ; InstrOffs = MI . getOperand (


<s> return ( MFI -> hasCalls ( ) && MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) ) || MFI -> hasVarSizedObjects ( ) || MFI -> isFrameAddressTaken ( ) || MFI -> hasStackMap ( ) || MFI -> hasPatchPoint (

) || RegInfo -> needsStackRealignment ( MF ) ;


<s> static MCAsmInfo * create<ISA_LIT>MCAsmInfo ( const MCRegisterInfo & MRI , const Triple & TT ) { return new <ISA_LIT>MCAsmInfo ( TT


<s> bool hasBaseReg ( ) const { return BaseType == Base :: RegBase && BaseReg . getNode


<s> Optional < RegOrConstant > <ISA_LIT>GISelUtils :: get<ISA_LIT>VectorSplat ( const MachineInstr & MI , const MachineRegisterInfo & MRI ) { if ( auto Splat = getVectorSplat ( MI , MRI ) ) return Splat ; if ( MI . getOpcode ( ) != <STR_LIT> ) return None ; Register Src = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( auto ValAndVReg = getConstantVRegValWithLookThrough ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) , MRI ) ) return RegOrConstant ( ValAndVReg -> Value . getSExtValue ( ) ) ; return RegOrConstant ( Src )


<s> rtx sc_reg = force_reg ( Pmode , static_chain ) ; emit_library_call ( gen_rtx_SYMBOL_REF ( SImode , <STR_LIT> ) , LCT_NORMAL , VOIDmode , <NUM_LIT> , addr , Pmode , GEN_INT ( frv_trampoline_size ( ) ) , SImode , fnaddr ,


<s> static tree rs6000_fold_builtin ( tree fndecl ATTRIBUTE_UNUSED , int n_args ATTRIBUTE_UNUSED , tree * args ATTRIBUTE_UNUSED , bool ignore ATTRIBUTE_UNUSED ) { return SUBTARGET_FOLD_BUILTIN ( fndecl , n_args , args ,


<s> const char * getPassName ( ) const override { return <STR_LIT>


<s> return DAG . getNode ( <STR_LIT> , SDLoc ( Op ) , Op . getValueType ( ) , Op . getOperand


<s> static int getAddrOffset ( MachineInstr * MI ) { const MCInstrDesc & Descl = MI -> getDesc


<s> if ( CONSTANT_ADDRESS_P ( x ) ) return true ; if ( LINKAGE_SYMBOL_REF_P ( x ) ) return true ; if ( GET_CODE ( x ) == PLUS ) { rtx ofs = XEXP ( x , <NUM_LIT> ) ; x = XEXP ( x , <NUM_LIT> ) ; if ( GET_CODE ( x ) == SUBREG && ( GET_MODE_SIZE ( GET_MODE ( x ) ) < GET_MODE_SIZE ( GET_MODE ( SUBREG_REG ( x ) ) ) ) ) x = SUBREG_REG ( x ) ; if ( REG_P ( x ) ) { if ( ! strict && NONSTRICT_REG_OK_FP_BASE_P ( x ) && CONST_INT_P ( ofs ) ) return true ; if ( ( strict ? STRICT_REG_OK_FOR_BASE_P ( x ) : NONSTRICT_REG_OK_FOR_BASE_P ( x ) ) && CONSTANT_ADDRESS_P ( ofs ) ) return true ; } } else if ( TARGET_EXPLICIT_RELOCS && GET_MODE_SIZE ( mode


<s> SDValue Reg = Is64Bit ? DAG . getRegister ( <STR_LIT> , VT ) : DAG . getNode ( <STR_LIT> , dl , VT ) ; SDValue Ops [ ] = {


<s> if ( ! IsTailCall ) Chain = DAG . getCALLSEQ_START ( Chain , DAG . getConstant ( NumBytes , PtrVT , true ) , DL ) ; SmallVector < std :: pair < unsigned , SDValue > , <NUM_LIT> > RegsToPass ; SmallVector < SDValue , <NUM_LIT> > MemOpChains ; SDValue StackPtr ; for ( unsigned I = <NUM_LIT> , E = ArgLocs . size ( ) ; I != E ; ++ I ) { CCValAssign & VA = ArgLocs [ I ] ; SDValue ArgValue = OutVals [ I ] ; if ( VA . getLocInfo ( ) == CCValAssign :: Indirect ) { SDValue SpillSlot = DAG . CreateStackTemporary ( VA . getValVT ( ) ) ; int FI = cast < FrameIndexSDNode > ( SpillSlot ) -> getIndex ( ) ; MemOpChains . push_back ( DAG . getStore ( Chain , DL , ArgValue , SpillSlot , MachinePointerInfo :: getFixedStack ( FI ) , false , false , <NUM_LIT> ) ) ; ArgValue = SpillSlot ; } else ArgValue = convertValVTToLocVT ( DAG , DL , VA , ArgValue ) ; if ( VA . isRegLoc ( ) ) RegsToPass . push_back ( std :: make_pair ( VA . getLocReg ( ) , ArgValue ) ) ; else { assert ( VA . isMemLoc ( ) && <STR_LIT> ) ; if ( ! StackPtr . getNode ( ) ) StackPtr = DAG . getCopyFromReg ( Chain , DL , <STR_LIT> , PtrVT ) ; unsigned Offset = <STR_LIT> + VA . getLocMemOffset ( ) ; if ( VA . getLocVT ( ) == <STR_LIT> || VA . getLocVT ( ) == <STR_LIT> ) Offset += <NUM_LIT> ; SDValue Address = DAG . getNode ( <STR_LIT> , DL , PtrVT , StackPtr , DAG . getIntPtrConstant ( Offset ) ) ; MemOpChains . push_back ( DAG . getStore ( Chain , DL , ArgValue , Address , MachinePointerInfo ( ) , false , false , <NUM_LIT> ) ) ; } } if ( ! MemOpChains . empty ( ) ) Chain = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , & MemOpChains [ <NUM_LIT> ] , MemOpChains . size ( ) ) ; SDValue Glue ; if ( auto * G = dyn_cast < GlobalAddressSDNode > ( Callee ) ) { Callee = DAG . getTargetGlobalAddress ( G -> getGlobal ( ) , DL , PtrVT ) ; Callee = DAG . getNode ( <STR_LIT> , DL , PtrVT , Callee ) ; } else if ( auto * E = dyn_cast < ExternalSymbolSDNode


<s> if ( TM -> getOptLevel ( ) != CodeGenOpt :: None ) addPass ( create<ISA_LIT>BoolRetToIntPass ( ) ) ; addPass ( createAtomicExpandPass ( & get<ISA_LIT>TargetMachine ( ) ) ) ; bool UsePrefetching = TM -> getTargetTriple ( ) . getVendor ( ) == Triple :: BGQ && getOptLevel ( ) != CodeGenOpt :: None ; if ( EnablePrefetch . getNumOccurrences ( ) > <NUM_LIT> ) UsePrefetching = EnablePrefetch ; if ( UsePrefetching ) addPass ( create<ISA_LIT>LoopDataPrefetchPass ( ) ) ; if ( TM -> getOptLevel ( ) == CodeGenOpt :: Aggressive && EnableGEPOpt ) { addPass ( createSeparateConstOffsetFromGEPPass ( TM ,


<s> unsigned <ISA_LIT>ELFObjectWriter :: getRelocType ( MCContext & Ctx , const MCValue & Target , const MCFixup & Fixup , bool IsPCRel ) const { llvm_unreachable ( <STR_LIT>


<s> case <STR_LIT> : Ok = isUInt < <NUM_LIT> > ( Imm ) ; break ; case <STR_LIT> : Ok = isUInt < <NUM_LIT> > ( Imm ) ; break ; case <STR_LIT> : Ok = isUInt < <NUM_LIT> > ( Imm ) ; break ; case <STR_LIT> : Ok = isInt < <NUM_LIT> > ( Imm ) ; break ; case <STR_LIT> : Ok = isUInt < <NUM_LIT> > ( Imm ) ; break ; case <STR_LIT> : if ( STI . getTargetTriple ( ) . isArch64Bit ( ) ) Ok = isUInt < <NUM_LIT> > ( Imm ) ; else Ok = isUInt < <NUM_LIT> > ( Imm ) ; break ; } if ( ! Ok ) { ErrInfo = <STR_LIT> ; return


<s> void <ISA_LIT>AsmPrinter :: EmitFunctionEntryLabel ( ) { OutStreamer . EmitLabel (


<s> if ( e == static_cast < uint32_t > ( SelectionControl :: None ) ) return <STR_LIT> ; if ( e == static_cast < uint32_t > ( SelectionControl :: Flatten ) ) return <STR_LIT> ; if ( e & static_cast < uint32_t > ( SelectionControl :: Flatten ) ) { nameString += sep + <STR_LIT> ; sep = <STR_LIT> ; } if ( e == static_cast < uint32_t > ( SelectionControl :: DontFlatten ) ) return <STR_LIT> ; if ( e & static_cast < uint32_t > ( SelectionControl :: DontFlatten ) ) { nameString += sep +


<s> const char * <ISA_LIT>ConstantPoolValue :: getModifierText ( ) const { switch ( Modifier ) { case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; } llvm_unreachable (


<s> bool OnlyOptimizeForSize = ( TM -> getOptLevel ( ) < CodeGenOpt :: Aggressive ) && ( EnableGlobalMerge == cl :: BOU_UNSET ) ; bool MergeExternalByDefault = ! TM -> getTargetTriple ( ) . isOSBinFormatMachO ( ) ; addPass ( createGlobalMergePass ( TM , <NUM_LIT> , OnlyOptimizeForSize , MergeExternalByDefault ) ) ; } if ( TM -> getOptLevel ( ) != CodeGenOpt :: None ) addPass ( createHardwareLoopsPass ( ) ) ; return false


<s> ( ( <ISA_LIT>Operand * ) Operands [ <NUM_LIT> ] ) -> addRegOperands ( Inst , <NUM_LIT> ) ; ( ( <ISA_LIT>Operand * ) Operands [ <NUM_LIT> ] )

-> addMemImm8OffsetOperands ( Inst , <NUM_LIT> ) ;


<s> case NOTB : case NOTW : case NEGW : case SWAP : return <NUM_LIT> ; case MOVL : return


<s> bool <ISA_LIT>AsmParser :: ParseDirective (


<s> static bool memAccessesCanBeReordered ( MachineBasicBlock :: iterator A , MachineBasicBlock :: iterator B , const <ISA_LIT>InstrInfo * TII , llvm


<s> MachineBasicBlock :: iterator I = MBB . end ( ) ; unsigned Count = <NUM_LIT> ; while ( I != MBB . begin ( ) ) { -- I ; if ( I -> isDebugValue ( ) ) continue ; if ( I -> getOpcode ( ) != <STR_LIT> && GetCondFromBranchOpc ( I -> getOpcode ( ) ) == <STR_LIT> ) break ; I -> eraseFromParent


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { unsigned ShiftAmt = <STR_LIT> ( I -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; if ( ! I -> getOperand ( <NUM_LIT> ) . isImm ( ) ) { DEBUG ( dbgs ( ) << <STR_LIT> << * I << '\n' ) ; return nullptr ; } else if ( I -> getOperand ( <NUM_LIT> ) . getImm ( ) << ShiftAmt >= <NUM_LIT> ) { DEBUG ( dbgs ( ) << <STR_LIT> << * I << '\n' ) ; return nullptr ; } else if ( ! MRI -> use_empty ( I -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ) { DEBUG ( dbgs ( ) << <STR_LIT> << * I << '\n' ) ; return nullptr


<s> bool msp430_promote_prototypes ( const_tree fntype ATTRIBUTE_UNUSED ) { return false


<s> const MachineOperand MO = MI . getOperand ( opIdx ) ; return getMachineOpValue ( MI , MO


<s> if ( skipFunction ( MF . getFunction ( ) ) ) return false ; const <ISA_LIT>Subtarget & ST = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; bool IsSlowLEA = ST . slowLEA ( ) ; bool IsSlow3OpsLEA = ST . slow3OpsLEA ( ) ; bool LEAUsesAG = ST . LEAusesAG ( ) ; bool OptIncDec = ! ST . slowIncDec ( ) || MF . getFunction ( ) . hasOptSize ( ) ; bool UseLEAForSP = ST . useLeaForSP ( ) ; TSM . init ( & ST ) ; TII = ST . getInstrInfo ( ) ; TRI = ST . getRegisterInfo ( ) ; auto * PSI = & getAnalysis < ProfileSummaryInfoWrapperPass > ( ) . getPSI ( ) ; auto * MBFI = ( PSI && PSI -> hasProfileSummary ( ) ) ? & getAnalysis < LazyMachineBlockFrequencyInfoPass > ( ) . getBFI ( ) : nullptr ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; ) ; for ( MachineBasicBlock & MBB : MF ) { bool OptIncDecPerBB = OptIncDec || llvm :: shouldOptimizeForSize ( & MBB , PSI , MBFI ) ; for ( MachineBasicBlock :: iterator I = MBB . begin ( ) ; I != MBB . end


<s> if ( CSKY_TARGET_ARCH ( CK801 ) || CSKY_TARGET_ARCH ( CK802 ) ) error ( <STR_LIT> , <STR_LIT> , csky_active_target . arch_pp_name ) ; else if ( csky_fpu_index == TARGET_FPU_auto ) error ( <STR_LIT> ) ; else { csky_selected_fpu = & all_fpus [ csky_fpu_index ] ; sbitmap fpu_bits = sbitmap_alloc ( CSKY_ISA_FEATURE_GET ( max ) ) ; csky_initialize_isa ( fpu_bits , csky_selected_fpu -> isa_bits ) ; bitmap_ior ( csky_active_target . isa , csky_active_target . isa , fpu_bits ) ; sbitmap_free ( fpu_bits ) ; } } else { if ( TARGET_DOUBLE_FLOAT > <NUM_LIT> ) warning ( <NUM_LIT> , <STR_LIT> ) ; TARGET_DOUBLE_FLOAT = <NUM_LIT> ; if ( TARGET_FDIVDU > <NUM_LIT> ) warning ( <NUM_LIT> , <STR_LIT> ) ; TARGET_FDIVDU = <NUM_LIT> ; } { \ csky_arch_isa_features [ CSKY_ISA_FEATURE_GET ( IDENT ) ] = \ bitmap_bit_p ( csky_active_target . isa , CSKY_ISA_FEATURE_GET ( IDENT ) ) ; \ } if ( TARGET_ELRW == - <NUM_LIT> ) TARGET_ELRW = CSKY_TARGET_ARCH ( CK801 ) ; if ( ! TARGET_DSP ) TARGET_DSP = CSKY_ISA_FEATURE ( dsp ) ; if ( TARGET_DIV == - <NUM_LIT> ) TARGET_DIV = CSKY_ISA_FEATURE ( div ) ; if ( ( CSKY_TARGET_ARCH ( CK801 ) || CSKY_TARGET_ARCH ( CK802 ) ) && ! TARGET_CONSTANT_POOL ) error ( <STR_LIT> , <STR_LIT> , csky_active_target . arch_pp_name ) ; else if ( TARGET_CONSTANT_POOL == - <NUM_LIT> ) TARGET_CONSTANT_POOL = ( CSKY_TARGET_ARCH ( CK801 ) || CSKY_TARGET_ARCH ( CK802 ) ) ; if ( TARGET_MINI_REGISTERS > <NUM_LIT> && TARGET_HIGH_REGISTERS > <NUM_LIT> ) error ( <STR_LIT> ) ; else if ( CSKY_TARGET_ARCH ( CK801 ) || CSKY_TARGET_ARCH ( CK802 ) ||


<s> bool ret = rs6000_rtx_costs ( x , code , outer_code , opno , total , speed ) ; fprintf ( stderr , <STR_LIT> <STR_LIT> , ret ? <STR_LIT> : <STR_LIT> , GET_RTX_NAME ( code ) , GET_RTX_NAME ( outer_code ) , opno , * total , speed ? <STR_LIT> : <STR_LIT> ) ; debug_rtx ( x ) ; return ret


<s> static SDValue performAddSubCombine ( SDNode * N , TargetLowering :: DAGCombinerInfo & DCI , SelectionDAG & DAG ) { if ( SDValue Val = performUADDVCombine ( N , DAG ) ) return Val ; if ( SDValue Val = performAddDotCombine (


<s> SDValue VAListFI = Op . getOperand ( <NUM_LIT> ) ; const Value * VAListS = cast < SrcValueSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getValue ( ) ; int argOffset = FuncInfo -> getVarArgsOffset ( ) ; SDValue VAList = DAG . getNode ( <STR_LIT> , DL , getPointerTy ( ) , DAG . getRegister ( <STR_LIT> , <STR_LIT>

) , DAG . getIntPtrConstant ( argOffset ) ) ;


<s> if ( ! cum ) return false ; if ( TARGET_SHCOMPACT ) { cum -> byref = shcompact_byref ( cum , mode ,


<s> MIRBuilder . buildInstr ( STI . isFP64bit ( ) ? <STR_LIT> : <STR_LIT> ) . addDef ( PhysReg + ( STI . isLittle ( ) ? <NUM_LIT> : <NUM_LIT> ) ) . addUse ( ValVReg ) . addImm ( <NUM_LIT> ) . constrainAllUses ( MIRBuilder . getTII ( ) , * STI . getRegisterInfo ( ) , * STI . getRegBankInfo ( ) ) ; MIRBuilder . buildInstr ( STI . isFP64bit ( ) ? <STR_LIT> : <STR_LIT> ) . addDef ( PhysReg + ( STI . isLittle ( ) ? <NUM_LIT> : <NUM_LIT> ) ) . addUse ( ValVReg ) . addImm ( <NUM_LIT> ) . constrainAllUses ( MIRBuilder . getTII ( ) , * STI . getRegisterInfo ( ) , * STI . getRegBankInfo ( ) ) ; } else if ( VT == <STR_LIT> && PhysReg >= <STR_LIT> && PhysReg <= <STR_LIT> ) { MIRBuilder . buildInstr ( <STR_LIT> ) . addDef ( PhysReg ) . addUse ( ValVReg ) . constrainAllUses ( MIRBuilder . getTII ( ) , * STI . getRegisterInfo ( ) , * STI . getRegBankInfo ( ) ) ; } else { unsigned ExtReg = extendRegister ( ValVReg , VA ) ; MIRBuilder . buildCopy ( PhysReg ,


<s> return __aarch64_vdup_lane_u16 ( __a ,


<s> return isRegOrImmWithInputMods ( <STR_LIT>


<s> case QImode : case HImode : case SImode : cmp_mode = SImode ; icode = CODE_FOR_ccmpsi ; break ; case DImode : cmp_mode = DImode ; icode = CODE_FOR_ccmpdi ; break ; case SFmode : cmp_mode = SFmode ; cc_mode = aarch64_select_cc_mode ( ( rtx_code ) cmp_code , op0 , op1 ) ; icode = cc_mode == CCFPEmode ? CODE_FOR_fccmpesf : CODE_FOR_fccmpsf ; break ; case DFmode : cmp_mode = DFmode ; cc_mode = aarch64_select_cc_mode ( ( rtx_code ) cmp_code , op0 , op1 ) ; icode = cc_mode == CCFPEmode ? CODE_FOR_fccmpedf : CODE_FOR_fccmpdf ; break ; default : end_sequence ( ) ; return NULL_RTX ; } op0 = prepare_operand ( icode , op0 , <NUM_LIT> , op_mode , cmp_mode , unsignedp ) ; op1 = prepare_operand ( icode , op1 , <NUM_LIT> , op_mode , cmp_mode , unsignedp ) ; if ( ! op0 || ! op1 ) { end_sequence ( ) ; return NULL_RTX ; } * prep_seq = get_insns ( ) ; end_sequence ( ) ; target = gen_rtx_REG ( cc_mode , CC_REGNUM ) ; aarch64_cond = aarch64_get_condition_code_1 ( cc_mode , ( rtx_code ) cmp_code ) ; if ( bit_code != AND ) { prev = gen_rtx_fmt_ee ( REVERSE_CONDITION ( GET_CODE ( prev ) , GET_MODE ( XEXP ( prev , <NUM_LIT> ) ) ) , VOIDmode , XEXP ( prev , <NUM_LIT> ) , const0_rtx ) ; aarch64_cond = AARCH64_INVERSE_CONDITION_CODE ( aarch64_cond ) ; } create_fixed_operand ( & ops [ <NUM_LIT> ] ,


<s> StringRef IDVal = DirectiveID . getIdentifier ( ) ; if ( IDVal == <STR_LIT> ) return ParseDirectiveWord ( <NUM_LIT> , DirectiveID . getLoc ( ) ) ; return


<s> void \ common_section ( ) \ { \ in_section =


<s> void Stack :: addDef ( unsigned Reg , const DILocalVariable


<s> const <ISA_LIT>TargetLowering * getTargetLowering ( ) const override { return getSubtargetImpl ( )


<s> BuildMI ( EntryBB , IP , dl , TII . get ( <STR_LIT> ) , UpdatedVRSAVE ) . addReg ( InVRSAVE ) ; BuildMI ( EntryBB , IP , dl , TII . get ( <STR_LIT> ) ) . addReg ( UpdatedVRSAVE ) ; for ( MachineFunction :: iterator BB = Fn . begin ( ) , E = Fn . end ( ) ; BB != E ; ++ BB ) { if ( BB -> isReturnBlock ( ) ) { IP = BB -> end ( ) ; -- IP ; MachineBasicBlock :: iterator I2 = IP ; while ( I2 != BB -> begin ( ) && ( -- I2


<s> void <ISA_LIT>ConditionalCompares :: updateLoops ( ArrayRef < MachineBasicBlock * > Removed ) { if ( ! Loops ) return ; for ( unsigned i = <NUM_LIT> , e = Removed . size ( ) ; i != e ;

++ i ) Loops -> removeBlock ( Removed [ i ] ) ;


<s> const char * const * End = LibCalls + array_lengthof ( LibCalls ) ; <ISA_LIT>TargetLowering :: LTStr Comp ; for ( const char * const * I = LibCalls ; I < End - <NUM_LIT> ; ++ I ) assert ( Comp (


<s> static const unsigned Values [ ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> ,


<s> return __builtin_loongson_psubh_u ( s ,


<s> <ISA_LIT>Operand :: addExpr ( Inst , MemOp . OuterDisp ) ; Inst . addOperand ( MCOperand :: createReg


<s> auto IsALoadChain = [ & ] ( Value * Start ) { SmallVector < Value * , <NUM_LIT> > ValuesToCheck = { Start } ; auto IsALoadChainInstr = [ ] ( Value * V ) -> bool { if ( isa < GetElementPtrInst > ( V ) || isa < BitCastInst > ( V ) || isa < LoadInst > ( V ) ) return true ; if ( auto * ASC = dyn_cast < AddrSpaceCastInst > ( V ) ) { if ( ASC -> getDestAddressSpace ( ) == ADDRESS_SPACE_PARAM ) return true ; } return false ; } ; while ( ! ValuesToCheck . empty ( ) ) { Value * V = ValuesToCheck . pop_back_val ( ) ; if ( ! IsALoadChainInstr ( V ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * Arg << <STR_LIT> << * V << <STR_LIT> ) ; ( void ) Arg ; return false


<s> if ( isDesirableToShrinkOp ( Op . getOpcode ( ) , <STR_LIT> , Op . getValueType ( ) ) ) return false ; PVT = <STR_LIT> ; return


<s> if ( theArgs [ i ] -> use_empty ( ) ) { if ( ObjectVT . isVector ( ) ) { EVT EltVT = ObjectVT . getVectorElementType ( ) ; unsigned NumElts = ObjectVT . getVectorNumElements ( ) ; for ( unsigned vi = <NUM_LIT> ; vi < NumElts ; ++ vi ) { InVals . push_back ( DAG . getNode ( <STR_LIT> , dl , EltVT ) ) ; } } else { InVals . push_back ( DAG . getNode ( <STR_LIT> , dl , ObjectVT ) ) ; } continue ; } if ( PAL . hasAttribute ( i + <NUM_LIT> , Attribute :: ByVal ) == false ) { if ( ObjectVT . isVector ( ) ) { unsigned NumElts = ObjectVT . getVectorNumElements ( ) ; EVT EltVT = ObjectVT . getVectorElementType ( ) ; unsigned Offset = <NUM_LIT> ; for ( unsigned vi = <NUM_LIT> ; vi < NumElts ; ++ vi ) { SDValue A = getParamSymbol ( DAG , idx , getPointerTy ( ) ) ; SDValue B = DAG . getIntPtrConstant ( Offset ) ; SDValue Addr = DAG . getNode ( <STR_LIT> , dl , getPointerTy ( ) , A , B ) ; Value * SrcValue = Constant :: getNullValue ( PointerType :: get ( EltVT . getTypeForEVT ( F -> getContext ( ) ) , llvm :: ADDRESS_SPACE_PARAM ) ) ; SDValue Ld = DAG . getLoad ( EltVT , dl , Root , Addr , MachinePointerInfo ( SrcValue ) , false , false , false , TD -> getABITypeAlignment ( EltVT . getTypeForEVT ( F -> getContext ( ) ) ) ) ; Offset += EltVT . getStoreSizeInBits ( ) / <NUM_LIT> ; InVals . push_back ( Ld ) ; } continue ; } if ( isABI || isKernel ) { SDValue Arg = getParamSymbol ( DAG , idx , getPointerTy ( ) ) ; Value * srcValue = Constant :: getNullValue ( PointerType :: get ( ObjectVT . getTypeForEVT ( F -> getContext ( ) ) , llvm :: ADDRESS_SPACE_PARAM ) ) ; SDValue p = DAG . getLoad ( ObjectVT , dl , Root , Arg , MachinePointerInfo ( srcValue ) , false , false , false , TD -> getABITypeAlignment ( ObjectVT . getTypeForEVT ( F -> getContext ( ) ) ) ) ; if ( p . getNode ( ) ) p . getNode ( ) -> setIROrder ( idx + <NUM_LIT> ) ; InVals . push_back ( p ) ; } else { SDValue Arg = getParamSymbol ( DAG , idx , ObjectVT ) ; SDValue p = DAG . getNode ( <STR_LIT> , dl , ObjectVT , Arg ) ; if ( p . getNode ( ) ) p . getNode ( ) -> setIROrder ( idx + <NUM_LIT> ) ; InVals . push_back ( p ) ; } continue ; } if ( isABI || isKernel ) { SDValue Arg = getParamSymbol ( DAG , idx , getPointerTy


<s> void <ISA_LIT>TargetWinCOFFStreamer :: emit<ISA_LIT>WinCFISaveSP (


<s> const MCInstrDesc * Desc = & II -> get ( Opcode ) ; MI . setDesc ( * Desc ) ; return Desc


<s> if ( OpType >= <STR_LIT> && OpType <= <STR_LIT>

) return ! ST . hasMFMAInlineLiteralBug ( ) ;


<s> if ( ! MO . isReg ( ) || ! ( Reg = MO . getReg ( ) ) || ( Reg == ExcludedReg ) ) return ; if ( MO . isDef ( ) )


<s> std :: swap ( True , False ) ; std :: swap ( LHS , RHS ) ; CC = DAG . getCondCode ( CCSwapped ) ; } } } if ( isZero ( RHS ) ) { SDValue Cond = LHS ; SDValue Zero = RHS ; <STR_LIT> CCOpcode = cast < CondCodeSDNode > ( CC ) -> get ( ) ; if ( CompareVT != VT ) { True = DAG . getNode ( <STR_LIT> , DL , CompareVT , True ) ; False = DAG . getNode ( <STR_LIT> , DL , CompareVT , False ) ; } switch ( CCOpcode ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : CCOpcode = <STR_LIT> ( CCOpcode , CompareVT == <STR_LIT> ) ; Temp = True ; True = False ; False = Temp ; break ; default : break ; } SDValue SelectNode = DAG . getNode ( <STR_LIT> , DL , CompareVT , Cond , Zero , True , False , DAG . getCondCode ( CCOpcode ) ) ; return DAG . getNode ( <STR_LIT> , DL , VT , SelectNode ) ; } SDValue HWTrue , HWFalse ; if ( CompareVT == <STR_LIT> ) { HWTrue = DAG . getConstantFP ( <NUM_LIT> , DL , CompareVT ) ; HWFalse = DAG . getConstantFP ( <NUM_LIT> , DL , CompareVT ) ; } else if ( CompareVT == <STR_LIT> ) { HWTrue = DAG . getConstant ( - <NUM_LIT> , DL , CompareVT ) ; HWFalse = DAG . getConstant ( <NUM_LIT> , DL , CompareVT ) ; } else { llvm_unreachable ( <STR_LIT>


<s> static unsigned HOST_WIDE_INT xtensa_asan_shadow_offset ( void


<s> LHS = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , LHS ) ; RHS = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , RHS ) ; SDValue NewSetcc = DAG . getSetCC ( dl , <STR_LIT> , LHS , RHS , CC ) ; DAG . ReplaceAllUsesWith ( Op , NewSetcc ) ; CmpVT = <STR_LIT> ; } else return SDValue ( ) ; } assert ( ( ! FullFP16 && LHS . getValueType ( ) . getVectorElementType ( ) != <STR_LIT> ) || LHS . getValueType ( ) . getVectorElementType ( ) != <STR_LIT> ) ; <STR_LIT> CC1 , CC2 ; bool ShouldInvert ; changeVectorFPCCTo<ISA_LIT>CC ( CC , CC1 , CC2 , ShouldInvert ) ; bool NoNaNs = getTargetMachine ( ) . Options . NoNaNsFPMath ; SDValue Cmp = EmitVectorComparison ( LHS , RHS , CC1 , NoNaNs , CmpVT , dl , DAG ) ; if ( ! Cmp . getNode ( ) ) return SDValue ( ) ; if ( CC2 != <STR_LIT>


<s> static void DecodeSymbolicOperandOff ( MCInst & Inst , uint64_t Address , uint64_t Offset , const void * Decoder ) { uint64_t NextAddress = Address +


<s> EmitHwasanMemaccessSymbols ( M ) ; const Triple & TT = TM . getTargetTriple ( ) ; if ( TT . isOSBinFormatMachO ( ) ) { MachineModuleInfoMachO & MMIMacho = MMI -> getObjFileInfo < MachineModuleInfoMachO > ( ) ; auto Stubs = MMIMacho . getAuthGVStubList ( ) ; if ( ! Stubs . empty ( ) ) { OutStreamer -> SwitchSection ( OutContext . getMachOSection ( <STR_LIT> , <STR_LIT> , MachO :: S_REGULAR , SectionKind :: getMetadata ( ) ) ) ; EmitAlignment ( Align ( <NUM_LIT> ) ) ; for ( auto & Stub : Stubs ) emitAuthenticatedPointer ( * OutStreamer , Stub . first , Stub . second ) ; OutStreamer -> AddBlankLine ( ) ; } OutStreamer -> EmitAssemblerFlag ( MCAF_SubsectionsViaSymbols ) ; } emitStackMaps ( SM )


<s> void <ISA_LIT>MCAsmStreamer :: EmitULEB128Value ( const MCExpr * Value , unsigned AddrSpace


<s> if ( ! TARGET_DPFP && TARGET_DPFP_DISABLE_LRSR ) error ( <STR_LIT> ) ; if ( ( TARGET_DPFP_FAST_SET && TARGET_DPFP_COMPACT_SET ) || ( TARGET_SPFP_FAST_SET && TARGET_SPFP_COMPACT_SET ) ) error ( <STR_LIT> ) ; if ( TARGET_SPFP_FAST_SET && TARGET_ARC600_FAMILY ) error ( <STR_LIT> ) ; if ( ( TARGET_DPFP_FAST_SET || TARGET_DPFP_COMPACT_SET || TARGET_SPFP ) && TARGET_HARD_FLOAT ) error ( <STR_LIT> ) ; if ( flag_pic && TARGET_ARC600_FAMILY ) { warning ( DK_WARNING , <STR_LIT> , arc_cpu_string ) ; flag_pic = <NUM_LIT> ; } arc_init_reg_tables ( ) ; memset ( arc_punct_chars , <NUM_LIT> , sizeof ( arc_punct_chars ) ) ; arc_punct_chars [ '#' ] = <NUM_LIT> ; arc_punct_chars [ '*' ] = <NUM_LIT> ; arc_punct_chars [ '?' ] = <NUM_LIT> ; arc_punct_chars [ '!' ] = <NUM_LIT> ; arc_punct_chars [ '^' ] = <NUM_LIT> ; arc_punct_chars [ '&' ] = <NUM_LIT> ; arc_punct_chars [ '+' ] = <NUM_LIT> ; arc_punct_chars [ '_' ] = <NUM_LIT> ; if ( optimize > <NUM_LIT> && ! TARGET_NO_COND_EXEC ) { opt_pass * pass_arc_ifcvt_4 = make_pass_arc_ifcvt ( g ) ; struct register_pass_info arc_ifcvt4_info = { pass_arc_ifcvt_4 , <STR_LIT> , <NUM_LIT> , PASS_POS_INSERT_AFTER } ; struct register_pass_info arc_ifcvt5_info = { pass_arc_ifcvt_4 -> clone ( ) , <STR_LIT> , <NUM_LIT> , PASS_POS_INSERT_BEFORE } ; register_pass ( & arc_ifcvt4_info )


<s> void <ISA_LIT>InstPrinter :: printSignedShl2Operand ( const MCInst * MI , int OpNo , raw_ostream & O ) { unsigned int Value = MI -> getOperand (


<s> if ( HandlerDataLoc . isValid ( ) ) return Error ( L , <STR_LIT> ) ; if ( Parser . getTok ( ) . isNot ( AsmToken :: Hash ) && Parser . getTok ( ) . isNot ( AsmToken :: Dollar ) ) { return Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; } Parser . Lex ( ) ; const MCExpr * OffsetExpr ; SMLoc ExLoc = Parser . getTok ( ) . getLoc ( ) ; SMLoc EndLoc ; if ( getParser ( ) . parseExpression ( OffsetExpr , EndLoc ) ) return Error ( ExLoc , <STR_LIT> ) ; const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( OffsetExpr ) ; if ( ! CE ) return Error ( ExLoc , <STR_LIT> ) ; getParser ( ) . getStreamer ( ) . EmitPad ( CE -> getValue


<s> StackGrowsUp = true ; HasSingleParameterDotFile = false ; MinInstAlignment = <NUM_LIT> ; MaxInstLength = ( TT . getArch ( ) == Triple :: amdgcn ) ? <NUM_LIT> : <NUM_LIT> ; SeparatorString = <STR_LIT> ; CommentString = <STR_LIT> ; InlineAsmStart = <STR_LIT> ; InlineAsmEnd = <STR_LIT> ; SunStyleELFSectionSwitchSyntax = true ; UsesELFSectionDirectiveForBSS =


<s> virtual const char * getPassName ( ) const { return


<s> Type * ScalarTy = DataTy -> getScalarType ( ) ; int DataWidth = isa < PointerType > ( ScalarTy ) ? DL .

getPointerSizeInBits ( ) : ScalarTy -> getPrimitiveSizeInBits ( ) ;


<s> static void mips_file_end ( void ) { tree name_tree ; struct extern_list * p ; if ( extern_head ) { fputs ( <STR_LIT> , asm_out_file ) ; for ( p = extern_head ; p != <NUM_LIT> ; p = p -> next ) { name_tree = get_identifier ( p -> name ) ; if ( ! TREE_ASM_WRITTEN ( name_tree ) && TREE_SYMBOL_REFERENCED ( name_tree ) ) { TREE_ASM_WRITTEN ( name_tree ) = <NUM_LIT> ; if ( TARGET_IRIX && mips_abi == ABI_32 && p -> size == - <NUM_LIT> ) { fputs ( <STR_LIT> , asm_out_file ) ; assemble_name ( asm_out_file , p -> name


<s> for ( unsigned I = <NUM_LIT> ; I < NumElts ; I ++ ) { SDValue OpI = Op . getOperand ( I ) ; if ( OpI . getOpcode ( ) != <STR_LIT> || OpI . getOperand ( <NUM_LIT> ) != Op0 || ! isa < ConstantSDNode > ( OpI . getOperand ( <NUM_LIT> ) ) || OpI . getConstantOperandVal ( <NUM_LIT> ) != I * N ) return SDValue ( ) ; } SDLoc DL ( Op ) ; return DAG . getNode ( <STR_LIT> , DL , DAG . getVTList ( VT , <STR_LIT> ) , Op0

, DAG . getConstant ( N , DL , <STR_LIT> ) ) ;


<s> return ( ( qword ) ( vec_madd ( ( vec_float4 ) ( a ) , ( vec_float4 ) ( b


<s> WorkList . pop_front ( ) ; auto LowerConstantVec = [ & II , & LowerOp , & WorkList , & M ] ( ConstantVector * Vec , unsigned NumOfOp ) -> Value * { if ( std :: all_of ( Vec -> op_begin ( ) , Vec -> op_end ( ) , [ ] ( Value * V ) { return isa < ConstantExpr > ( V ) || isa < Function > ( V ) ; } ) ) { std :: list < Value * > OpList ; std :: transform ( Vec -> op_begin ( ) , Vec -> op_end ( ) , std :: back_inserter ( OpList ) , [ LowerOp ] ( Value * V ) { return LowerOp ( V ) ; } ) ; Value * Repl = nullptr ; unsigned Idx = <NUM_LIT> ; auto * PhiII = dyn_cast < PHINode > ( II ) ; auto * InsPoint = PhiII ? & PhiII -> getIncomingBlock ( NumOfOp ) -> back ( ) : II ; std :: list < Instruction * > ReplList ; for ( auto V : OpList ) { if ( auto * Inst = dyn_cast < Instruction > ( V ) ) ReplList . push_back ( Inst ) ; Repl = InsertElementInst :: Create ( ( Repl ? Repl : UndefValue :: get ( Vec -> getType ( ) ) ) , V , ConstantInt :: get ( Type :: getInt32Ty ( M -> getContext ( ) ) , Idx ++ ) , <STR_LIT> , InsPoint ) ; } WorkList . splice ( WorkList . begin ( ) , ReplList ) ; return Repl ; } return nullptr ; } ; for ( unsigned OI = <NUM_LIT> , OE = II -> getNumOperands ( ) ; OI != OE ; ++ OI ) { auto * Op = II -> getOperand ( OI ) ; if ( auto * Vec = dyn_cast < ConstantVector > ( Op ) ) { Value * ReplInst = LowerConstantVec (


<s> if ( ! isInt < <NUM_LIT> > ( Val ) ) report_fatal_error ( <STR_LIT> ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg ) . addImm ( Val


<s> User * Second = dyn_cast < User > ( Pair . second ) ; assert ( ( ! First || Second ) && <STR_LIT> ) ; if ( First ) for ( unsigned i = <NUM_LIT> ; i < First -> getNumOperands ( ) ; ++ i ) Second -> setOperand ( i , BoolToIntMap [ First -> getOperand ( i ) ] ) ; } Value * IntRetVal = BoolToIntMap [ U ] ; Type * Int1Ty = Type :: getInt1Ty ( U -> getContext ( ) ) ; Instruction * I = cast < Instruction > ( U . getUser ( ) ) ; Value * BackToBool = new TruncInst ( IntRetVal , Int1Ty , <STR_LIT> , I ) ; U . set ( BackToBool


<s> llvm_unreachable ( <STR_LIT> ) ; return


<s> MachineBasicBlock * exitMBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineFunction :: iterator It = ++ BB -> getIterator ( ) ; MF -> insert ( It , loopMBB ) ; MF -> insert ( It , exitMBB ) ; exitMBB -> splice ( exitMBB -> begin ( ) , BB , std :: next ( MachineBasicBlock :: iterator ( MI ) ) , BB -> end ( ) ) ; exitMBB -> transferSuccessorsAndUpdatePHIs ( BB ) ; BB -> addSuccessor ( loopMBB ) ; loopMBB -> addSuccessor ( loopMBB ) ; loopMBB -> addSuccessor ( exitMBB ) ; BB = loopMBB ; BuildMI ( BB , DL , TII -> get ( LL ) , OldVal ) . addReg ( Ptr ) . addImm ( <NUM_LIT> ) ; if ( Nand ) { BuildMI ( BB , DL , TII -> get ( AND ) , AndRes ) . addReg ( OldVal ) . addReg ( Incr ) ; BuildMI ( BB , DL , TII -> get ( NOR ) , StoreVal ) . addReg ( ZERO ) . addReg ( AndRes ) ; } else if ( BinOpcode ) { BuildMI ( BB , DL , TII -> get ( BinOpcode ) , StoreVal ) . addReg ( OldVal ) . addReg ( Incr ) ; }


<s> if ( MI != MBB . end ( ) && ! MI -> isDebugInstr ( ) ) DL = MI -> getDebugLoc ( ) ; for ( auto & CS : reverse ( CSI ) ) { Register Reg = CS . getReg ( ) ; const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ; TII . loadRegFromStackSlot ( MBB , MI , Reg , CS . getFrameIdx ( ) , RC , TRI ) ; assert ( MI != MBB . begin ( ) && <STR_LIT> ) ; } return true


<s> bool isNoopAddrSpaceCast ( unsigned SrcAS , unsigned DestAS ) const override { return true


<s> SDValue <ISA_LIT>TargetLowering :: makeHiLoPair ( SDValue Op , unsigned HiTF , unsigned LoTF , SelectionDAG & DAG ) const { SDLoc DL ( Op ) ; EVT VT = Op . getValueType ( ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , DL , VT , withTargetFlags


<s> static void EmitIndirectBranch ( const llvm :: MCSubtargetInfo & STI , const MCOperand & Op , bool Is64Bit , bool IsCall , MCStreamer & Out ) { const bool HideSandboxBase = ( FlagHideSandboxBase && Is64Bit && ! FlagUseZeroBasedSandbox ) ; const int JmpMask = - kNaCl<ISA_LIT>InstructionBundleSize ; unsigned Reg32 = Op . getReg ( ) ; MCSymbol * RetTarget = NULL ; const unsigned SafeReg32 = <STR_LIT> ; const unsigned SafeReg64 = <STR_LIT> ; if ( HideSandboxBase ) { if ( ( Reg32 != SafeReg32 ) && ( Reg32 != SafeReg64 ) ) { MCInst MOVInst ; MOVInst . setOpcode ( <STR_LIT> ) ; MOVInst . addOperand ( MCOperand :: CreateReg ( SafeReg32 ) ) ; MOVInst . addOperand ( MCOperand :: CreateReg ( Reg32 ) ) ; Out . EmitInstruction ( MOVInst , STI ) ; Reg32 = SafeReg32 ; } if ( IsCall ) { MCContext & Context = Out . getContext ( ) ; RetTarget = CreateTempLabel ( Context , <STR_LIT> ) ; PushReturnAddress ( STI , Context , Out , RetTarget


<s> return new <ISA_LIT>IfConversionTerm (


<s> bool <ISA_LIT>FastISel :: SelectFPToInt ( const Instruction * I , bool Signed ) { MVT DestVT ; if ( ! isTypeLegal ( I -> getType ( ) , DestVT ) || DestVT . isVector ( ) ) return false ; unsigned SrcReg = getRegForValue ( I -> getOperand ( <NUM_LIT> ) ) ; if ( SrcReg == <NUM_LIT> ) return false ; EVT SrcVT = TLI . getValueType ( I -> getOperand ( <NUM_LIT> ) -> getType ( ) , true ) ; if ( SrcVT == <STR_LIT> ) return false ; unsigned Opc ; if ( SrcVT == <STR_LIT> ) { if ( Signed ) Opc = ( DestVT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; else Opc = ( DestVT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; } else { if ( Signed ) Opc = ( DestVT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; else Opc = ( DestVT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; } unsigned ResultReg = createResultReg ( DestVT == <STR_LIT> ? & <STR_LIT> : &


<s> EVT <ISA_LIT>TargetLowering :: getPromotedVTForPredicate ( EVT


<s> default : break ; case <STR_LIT> : return PerformADDECombine ( N , DCI , Subtarget ) ; case <STR_LIT> : return PerformUMLALCombine ( N , DCI . DAG , Subtarget ) ; case <STR_LIT> : return PerformADDCombine ( N , DCI , Subtarget ) ; case <STR_LIT> : return PerformSUBCombine ( N , DCI ) ; case <STR_LIT> : return PerformMULCombine ( N , DCI , Subtarget ) ; case <STR_LIT> : return PerformORCombine ( N , DCI , Subtarget ) ; case <STR_LIT> : return PerformXORCombine ( N , DCI , Subtarget ) ; case <STR_LIT> : return PerformANDCombine ( N , DCI , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : return PerformAddcSubcCombine ( N , DCI , Subtarget ) ; case <STR_LIT> : return PerformAddeSubeCombine ( N , DCI . DAG , Subtarget ) ; case <STR_LIT> : return PerformBFICombine ( N , DCI ) ; case <STR_LIT> : return PerformVMOVRRDCombine ( N , DCI , Subtarget ) ; case <STR_LIT> : return PerformVMOVDRRCombine ( N , DCI . DAG ) ; case <STR_LIT> : return PerformSTORECombine ( N , DCI ) ; case <STR_LIT> : return PerformBUILD_VECTORCombine ( N , DCI , Subtarget ) ; case <STR_LIT> : return PerformInsertEltCombine ( N , DCI ) ; case <STR_LIT> : return PerformVECTOR_SHUFFLECombine ( N , DCI . DAG ) ; case <STR_LIT> : return PerformVDUPLANECombine ( N , DCI ) ; case <STR_LIT> : return PerformVDUPCombine ( N , DCI ) ; case <STR_LIT> : case <STR_LIT> : return PerformVCVTCombine ( N , DCI . DAG , Subtarget ) ; case <STR_LIT> : return PerformVDIVCombine ( N , DCI . DAG , Subtarget ) ; case <STR_LIT> : return PerformIntrinsicCombine ( N , DCI . DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return PerformShiftCombine ( N , DCI . DAG , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return PerformExtendCombine ( N , DCI . DAG , Subtarget ) ; case <STR_LIT> : return PerformCMOVCombine ( N , DCI . DAG ) ; case <STR_LIT> : return PerformBRCONDCombine ( N , DCI . DAG ) ; case <STR_LIT> : return PerformLOADCombine ( N , DCI ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case


<s> for ( MachineFunction :: iterator BI = MF . begin ( ) , BE = MF . end ( ) ; BI != BE ; ++ BI ) { MachineBasicBlock & MBB = * BI ; MachineBasicBlock :: iterator I , Next ; for ( I = MBB . begin ( ) ; I != MBB . end ( ) ; I = Next ) { Next = std :: next ( I ) ; MachineInstr & MI = * I ; if ( MI . getOpcode ( ) == AMDGPU :: V_MOV_I1 ) { I1Defs . push_back ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; MI . setDesc ( TII -> get ( AMDGPU :: V_MOV_B32_e32 ) ) ; continue ; } if ( MI . getOpcode ( ) == AMDGPU :: V_AND_I1 ) { I1Defs . push_back ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; MI . setDesc ( TII -> get ( AMDGPU :: V_AND_B32_e32 ) ) ; continue ; } if ( MI . getOpcode ( ) == AMDGPU :: V_OR_I1 ) { I1Defs . push_back ( MI . getOperand ( <NUM_LIT>


<s> bool and_operands_ok ( machine_mode mode , rtx op1 , rtx op2 ) { if ( memory_operand ( op1 , mode ) ) { if ( TARGET_MIPS16 ) { struct mips_address_info addr ; if ( ! mips_classify_address ( & addr , op1 , mode , false ) ) return false ; } return and_load_operand ( op2


<s> } MCSymbolRefExpr :: VariantKind Kind = MCSymbolRefExpr :: VK_None ; StringRef Name = Parser . getTok ( ) . getString ( ) ; if ( Name == <STR_LIT> ) Kind = MCSymbolRefExpr :: VK_TLSGD ; else if ( Name == <STR_LIT> ) Kind = MCSymbolRefExpr :: VK_TLSLDM ; else { Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ; } Parser . Lex ( ) ; if ( Parser . getTok ( ) . isNot ( AsmToken :: Colon ) ) { Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ; } Parser . Lex ( ) ; if ( Parser . getTok ( ) . isNot ( AsmToken :: Identifier ) ) { Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ; } StringRef Identifier = Parser . getTok ( ) . getString ( ) ; Sym = MCSymbolRefExpr :: create ( Ctx . getOrCreateSymbol ( Identifier ) , Kind , Ctx ) ; Parser . Lex (


<s> int64_t i = CI -> getValue ( ) . getSExtValue ( ) ; Type * NextTy = cast < StructType > ( Ty ) ->


<s> void LLVMInitialize<ISA_LIT>TargetInfo ( ) { RegisterTarget < Triple :: arm , true > X ( getThe<ISA_LIT>LETarget ( ) , <STR_LIT> , <STR_LIT> , <STR_LIT> ) ; RegisterTarget < Triple :: armeb , true > Y ( getThe<ISA_LIT>BETarget ( ) , <STR_LIT> , <STR_LIT> , <STR_LIT> ) ; RegisterTarget < Triple :: thumb , true > A ( getTheThumbLETarget ( ) , <STR_LIT> , <STR_LIT>


<s> Init<ISA_LIT>Z80MCRegisterInfo ( X , <NUM_LIT> ) ; return X


<s> static bool isSequentialOrUndefOrZeroInRange ( ArrayRef < int > Mask , unsigned Pos , unsigned

Size , int Low , int Step = <NUM_LIT> ) {


<s> case <STR_LIT> : if ( Rn == <NUM_LIT> ) return MCDisassembler :: Fail ; break ; default : break ; } if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rn , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecoderGPRRegisterClass ( Inst , Rm , Address , Decoder ) ) ) return MCDisassembler :: Fail ; Inst . addOperand ( MCOperand :: createImm ( imm ) ) ; return S


<s> build_target . isa = sbitmap_alloc ( isa_num_bits ) ; arm_configure_build_target ( & build_target , targ_options , false ) ; if ( build_target . core_name && ! bitmap_bit_p ( build_target . isa , isa_bit_quirk_no_asmcpu ) ) { const char * truncated_name = arm_rewrite_selected_cpu ( build_target . core_name ) ; asm_fprintf ( stream , <STR_LIT> , truncated_name ) ; } const arch_option * arch = arm_parse_arch_option_name ( all_architectures , <STR_LIT> , build_target . arch_name ) ; auto_sbitmap opt_bits ( isa_num_bits ) ; gcc_assert ( arch ) ; if ( strcmp ( build_target . arch_name , <STR_LIT> ) == <NUM_LIT> ) { asm_fprintf ( stream , <STR_LIT> ) ; asm_fprintf ( stream , <STR_LIT> ) ; asm_fprintf ( stream , <STR_LIT> ) ; asm_fprintf ( stream , <STR_LIT> ) ; asm_fprintf ( stream , <STR_LIT> ) ; } else asm_fprintf ( stream , <STR_LIT> , build_target . arch_name ) ; const char * fpu_name = ( TARGET_SOFT_FLOAT ? <STR_LIT> : arm_identify_fpu_from_isa ( build_target . isa ) ) ; asm_fprintf ( stream , <STR_LIT> , fpu_name ) ; if ( ! arch -> common . extensions ) return ; for ( const struct cpu_arch_extension * opt = arch -> common . extensions ; opt -> name != NULL ; opt ++ ) { if ( ! opt


<s> return ( ( regno >= GR_RET_FIRST && regno <= GR_RET_LAST ) || (

regno >= FR_RET_FIRST && regno <= FR_RET_LAST ) ) ;


<s> virtual const TargetFrameLowering * getFrameLowering


<s> <ISA_LIT>Operand :: Ptr <ISA_LIT>AsmParser :: defaultRowMask


<s> if ( T . getArch ( ) == Triple :: ppc64le || T . getArch ( ) == Triple :: ppcle ) report_fatal_error ( <STR_LIT> ) ; CodePointerSize = CalleeSaveStackSlotSize = Is64Bit ?


<s> case <STR_LIT> : return BB ; case <STR_LIT> : { const <ISA_LIT>InstrInfo * TII = getSubtarget ( ) -> getInstrInfo ( ) ; MachineFunction * MF = BB -> getParent ( ) ; <ISA_LIT>MachineFunctionInfo * MFI = MF -> getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; DebugLoc DL = MI . getDebugLoc ( ) ; BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) ) . addOperand ( MI . getOperand ( <NUM_LIT> ) ) . addImm ( MFI -> LDSSize ) ; MI . eraseFromParent ( ) ; return BB ; } case <STR_LIT>


<s> unsigned getRsaSize ( ) const { return


<s> MachineFunction & MF = MIRBuilder . getMF ( ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; auto & DL = MF . getDataLayout ( ) ; const Function & F = MF . getFunction ( ) ; ArgInfo OrigArg { VReg , Val -> getType ( ) } ; setArgFlags ( OrigArg , AttributeList :: ReturnIndex , DL , F ) ; SmallVector < ArgInfo , <NUM_LIT> > SplitArgs ; if ( ! splitToValueTypes ( OrigArg , SplitArgs , DL , MRI , [ & ] ( ArrayRef < unsigned > Regs ) { MIRBuilder . buildUnmerge ( Regs , VReg


<s> if ( ! isImm ( ) || evaluateConstantImm ( getImm ( ) , Imm , VK ) ) return false ; return <ISA_LIT>AsmParser :: classifySymbolRef ( getImm ( ) , VK , Imm ) && VK ==


<s> static bool isUNPCKLMask ( ArrayRef < int > Mask , MVT VT , bool HasInt256 , bool V2IsSplat = false ) { assert ( VT . getSizeInBits ( ) >= <NUM_LIT> && <STR_LIT> ) ; unsigned NumElts = VT . getVectorNumElements ( ) ; if ( VT . is256BitVector ( ) && NumElts != <NUM_LIT> && NumElts != <NUM_LIT> && ( ! HasInt256 || ( NumElts != <NUM_LIT> && NumElts != <NUM_LIT> ) ) ) return false ; assert ( ( ! VT . is512BitVector ( ) || VT . getScalarType ( ) . getSizeInBits ( ) >= <NUM_LIT> ) && <STR_LIT> ) ; unsigned NumLanes = VT . getSizeInBits ( ) / <NUM_LIT> ; unsigned NumLaneElts = NumElts


<s> MachineFunction & MF = DAG . getMachineFunction ( ) ; <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; int FrameIndex = StoreByValRegs ( CCInfo , DAG , dl , Chain , nullptr , CCInfo . getInRegsParamsCount ( ) , CCInfo . getNextStackOffset ( ) , <NUM_LIT> ) ; AFI -> setVarArgsFrameIndex (


<s> tmp = next_fp_limit ; if ( size > <NUM_LIT> && ! is_double ) tmp = fold_build_pointer_plus_hwi ( unshare_expr ( tmp ) , <NUM_LIT> - size ) ; tmp = build2 ( GE_EXPR , boolean_type_node , unshare_expr ( next_fp_tmp ) , unshare_expr ( tmp ) ) ; cmp = build3 ( COND_EXPR , void_type_node , tmp , build1 ( GOTO_EXPR , void_type_node , unshare_expr ( lab_false ) ) , NULL_TREE ) ; if ( ! is_double ) gimplify_and_add ( cmp , pre_p ) ; if ( TYPE_ALIGN ( eff_type ) > BITS_PER_WORD || ( is_double || size == <NUM_LIT> ) ) { tmp = fold_convert ( sizetype , next_fp_tmp ) ; tmp = build2 ( BIT_AND_EXPR , sizetype , tmp , size_int ( UNITS_PER_WORD ) ) ; tmp = fold_build_pointer_plus ( unshare_expr ( next_fp_tmp ) , tmp ) ; gimplify_assign ( unshare_expr ( next_fp_tmp ) , tmp , pre_p ) ; } if ( is_double ) gimplify_and_add ( cmp , pre_p ) ; if ( TYPE_MODE ( eff_type ) == SCmode && TARGET_SH4 && TARGET_LITTLE_ENDIAN ) { tree subtype = TREE_TYPE ( eff_type ) ; tree real , imag ; imag = std_gimplify_va_arg_expr ( next_fp_tmp , subtype , pre_p , NULL ) ; imag = get_initialized_tmp_var ( imag , pre_p , NULL ) ; real = std_gimplify_va_arg_expr ( next_fp_tmp , subtype , pre_p , NULL ) ; real = get_initialized_tmp_var ( real , pre_p , NULL ) ; result = build2 ( COMPLEX_EXPR , eff_type , real , imag ) ; if ( type != eff_type ) result = build1 ( VIEW_CONVERT_EXPR , type , result ) ; result = get_initialized_tmp_var ( result , pre_p , NULL ) ; } tmp = build1 ( GOTO_EXPR , void_type_node , unshare_expr ( lab_over ) ) ; gimplify_and_add ( tmp , pre_p ) ; tmp = build1 ( LABEL_EXPR , void_type_node , unshare_expr ( lab_false ) ) ; gimplify_and_add ( tmp , pre_p ) ; tmp = build1 ( ADDR_EXPR , pptr_type_node , unshare_expr ( next_stack ) ) ; gimplify_assign ( unshare_expr ( addr ) , tmp , pre_p ) ; gimplify_assign ( unshare_expr ( next_fp_tmp ) , unshare_expr ( valist ) , pre_p ) ; gimplify_assign ( unshare_expr ( valist ) , unshare_expr ( next_fp_tmp ) , post_p ) ; valist = next_fp_tmp ; } else { tmp = fold_build_pointer_plus_hwi ( unshare_expr ( next_o ) , rsize ) ; tmp = build2 ( GT_EXPR , boolean_type_node , tmp , unshare_expr ( next_o_limit ) ) ; tmp = build3 ( COND_EXPR , void_type_node , tmp , build1 ( GOTO_EXPR , void_type_node , unshare_expr ( lab_false ) ) , NULL_TREE ) ; gimplify_and_add ( tmp , pre_p ) ; tmp = build1 ( ADDR_EXPR , pptr_type_node , unshare_expr ( next_o ) ) ; gimplify_assign ( unshare_expr ( addr ) , tmp , pre_p ) ; tmp = build1 ( GOTO_EXPR , void_type_node , unshare_expr ( lab_over ) ) ; gimplify_and_add ( tmp , pre_p ) ; tmp = build1 ( LABEL_EXPR , void_type_node


<s> SDValue TVal = DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ; SDValue FVal = DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ; <STR_LIT> CC ; SDValue Value , Overflow ; std :: tie ( Value , Overflow ) = get<ISA_LIT>XALUOOp ( CC , Sel . getValue ( <NUM_LIT> ) , DAG ) ; SDValue CCVal = DAG . getConstant ( getInvertedCondCode ( CC ) , dl , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , Op . getValueType ( ) , TVal , FVal , CCVal , Overflow ) ; } if ( Sel . getOpcode ( ) != <STR_LIT> ) std :: swap ( Sel , Other ) ; if ( Sel . getOpcode ( ) != <STR_LIT> ) return Op ; <STR_LIT> CC = cast < CondCodeSDNode > ( Sel . getOperand ( <NUM_LIT> ) ) -> get ( ) ; SDValue LHS = Sel . getOperand ( <NUM_LIT> ) ; SDValue RHS = Sel . getOperand ( <NUM_LIT> ) ; SDValue TVal = Sel . getOperand ( <NUM_LIT> ) ; SDValue FVal = Sel . getOperand ( <NUM_LIT> ) ; if ( LHS . getValueType ( ) != <STR_LIT> && LHS . getValueType ( ) != <STR_LIT> ) return Op ; ConstantSDNode * CFVal = dyn_cast < ConstantSDNode


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; assert ( isRegShiftedImm ( ) && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: CreateReg


<s> return MachineFunctionProperties ( ) . set ( MachineFunctionProperties


<s> LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; SmallVector < Instruction * , <NUM_LIT> > LiveOuts ; LiveOuts = llvm :: findDefsUsedOutsideOfLoop ( L ) ; bool ReductionsDisabled = EnableTailPredication == TailPredication :: EnabledNoReductions || EnableTailPredication == TailPredication :: ForceEnabledNoReductions ; for ( auto * I : LiveOuts ) { if ( ! I -> getType ( ) -> isIntegerTy ( ) && ! I -> getType ( ) -> isFloatTy ( ) && ! I -> getType ( ) -> isHalfTy ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> <STR_LIT> ) ; return false ; } if ( ReductionsDisabled ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } } PredicatedScalarEvolution PSE = LAI -> getPSE ( ) ; SmallVector < Instruction * , <NUM_LIT> > LoadStores ; int ICmpCount = <NUM_LIT> ; for ( BasicBlock * BB : L -> blocks ( ) ) { for ( Instruction & I : BB -> instructionsWithoutDebug ( ) ) { if ( isa < PHINode > ( & I ) ) continue ; if ( ! canTailPredicateInstruction ( I , ICmpCount ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; I . dump ( ) ) ; return false ; } Type * T = I . getType ( ) ; if ( T -> isPointerTy ( ) ) T = T -> getPointerElementType ( ) ; if ( T -> getScalarSizeInBits ( ) > <NUM_LIT> ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; T -> dump ( ) ) ; return false ; } if ( isa < StoreInst > ( I ) || isa < LoadInst > ( I ) ) { Value * Ptr = isa < LoadInst > ( I ) ? I . getOperand ( <NUM_LIT> ) : I . getOperand ( <NUM_LIT> ) ; int64_t NextStride = getPtrStride ( PSE , Ptr , L ) ; if ( NextStride == <NUM_LIT> ) { continue ; } else if ( NextStride == - <NUM_LIT> || ( NextStride == <NUM_LIT> && MVEMaxSupportedInterleaveFactor >= <NUM_LIT> ) || ( NextStride == <NUM_LIT> && MVEMaxSupportedInterleaveFactor >= <NUM_LIT> ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> <STR_LIT> ) ; return false ; } else if (


<s> TargetRegistry :: RegisterMCInstrInfo ( getThe<ISA_LIT>Target ( ) , create<ISA_LIT>MCInstrInfo ) ; TargetRegistry :: RegisterMCRegInfo ( getThe<ISA_LIT>Target ( ) ,


<s> MCCodeEmitter * create<ISA_LIT>MCCodeEmitterEB ( const MCInstrInfo & MCII , const MCRegisterInfo & MRI , const MCSubtargetInfo & STI , MCContext & Ctx ) { return new <ISA_LIT>MCCodeEmitter ( MCII ,


<s> if ( cast < StructType > ( DstTy ) -> isOpaque ( ) ) { assert ( false ) ; return <NUM_LIT> ; } } if ( SrcTy -> getNumContainedTypes ( ) != DstTy -> getNumContainedTypes ( ) ) return <NUM_LIT> ; if ( isa < IntegerType > ( DstTy ) ) return <NUM_LIT> ; if ( PointerType * PT = dyn_cast < PointerType > ( DstTy ) ) { if ( PT -> getAddressSpace ( ) != cast < PointerType > ( SrcTy ) -> getAddressSpace ( ) ) return <NUM_LIT> ; } else if ( FunctionType * FT = dyn_cast < FunctionType > ( DstTy ) ) { if ( FT -> isVarArg ( ) != cast < FunctionType > ( SrcTy ) -> isVarArg ( ) ) return <NUM_LIT> ; } else if ( StructType * DSTy = dyn_cast < StructType > ( DstTy ) ) { StructType * SSTy = cast < StructType > ( SrcTy ) ; if ( DSTy -> isLiteral ( ) != SSTy -> isLiteral ( ) || DSTy -> isPacked ( ) != SSTy -> isPacked ( ) ) return <NUM_LIT> ; } else if ( ArrayType * DATy = dyn_cast < ArrayType > ( DstTy ) ) { if ( DATy -> getNumElements ( ) != cast < ArrayType > ( SrcTy ) -> getNumElements ( ) ) return <NUM_LIT> ; } else if ( VectorType * DVTy = dyn_cast < VectorType > ( DstTy ) ) { if ( DVTy -> getNumElements ( ) != cast < ArrayType > ( SrcTy ) -> getNumElements ( ) ) return <NUM_LIT> ; } EQ [ std :: make_pair ( DstTy , SrcTy ) ] = - <NUM_LIT> ; int retval = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> , e = SrcTy -> getNumContainedTypes ( ) ; i != e ; ++ i ) { switch ( areTypesIsomorphic ( DstTy -> getContainedType ( i ) , SrcTy -> getContainedType ( i ) ) ) { case <NUM_LIT> : EQ [ std :: make_pair ( DstTy , SrcTy ) ] = <NUM_LIT> ; return <NUM_LIT> ; case -


<s> while ( MadeChange ) { MadeChange = false ; for ( MachineFunction :: iterator MFI = Fn . begin ( ) , E = Fn . end ( ) ; MFI != E ; ++ MFI ) { MachineBasicBlock & MBB = * MFI ; unsigned MBBStartOffset = <NUM_LIT> ; for ( MachineBasicBlock :: iterator I = MBB . begin ( ) , E = MBB . end ( ) ; I != E ; ++ I ) { if ( ( I -> getOpcode ( ) != <STR_LIT> || I -> getOperand ( <NUM_LIT> ) . isImm ( ) ) && I -> getOpcode ( ) != <STR_LIT> ) { MBBStartOffset += TII -> GetInstSizeInBytes ( I ) ; continue ; } MachineBasicBlock * Dest = I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; int BranchSize ; if ( Dest -> getNumber ( ) <= MBB . getNumber ( ) ) { BranchSize = MBBStartOffset ; for ( unsigned i = Dest -> getNumber ( ) , e = MBB . getNumber ( ) ; i != e ; ++ i ) BranchSize += BlockSizes [ i ] ; } else { BranchSize = - MBBStartOffset ; for ( unsigned i = MBB . getNumber ( ) , e = Dest -> getNumber ( ) ; i != e ; ++ i ) BranchSize += BlockSizes [ i ] ; } if ( isInt < <NUM_LIT> > ( BranchSize ) ) { MBBStartOffset += <NUM_LIT> ; continue ; } unsigned NewSize ; MachineInstr * OldBranch = I ; DebugLoc dl = OldBranch -> getDebugLoc ( ) ; if ( I -> getOpcode ( ) == <STR_LIT> ) { NewSize = <NUM_LIT> ; } else { SmallVector < MachineOperand , <NUM_LIT> > Cond ; Cond . push_back ( I -> getOperand ( <NUM_LIT> ) ) ; TII -> ReverseBranchCondition ( Cond ) ; BuildMI ( MBB , I , dl , TII -> get ( <STR_LIT> ) ) . addImm ( <NUM_LIT> ) . addOperand ( Cond [ <NUM_LIT> ] ) ; NewSize = <NUM_LIT> ; } I = BuildMI ( MBB , I , dl , TII -> get ( <STR_LIT> ) ) . addMBB ( Dest ) ; OldBranch -> eraseFromParent ( )


<s> virtual bool requiresRegisterScavenging ( const MachineFunction & MF ) const LLVM_OVERRIDE { return true


<s> bool isS5Imm ( ) const { return Kind == Immediate && isInt < <NUM_LIT> > ( getImm (


<s> MachineInstr & MI = * I ; Next = std :: next ( I ) ; if ( ! TII -> isSGPRSpill ( MI ) ) continue ; int FI = TII -> getNamedOperand ( MI , <STR_LIT> :: addr ) -> getIndex ( ) ; assert ( MFI . getStackID ( FI ) == TargetStackID :: SGPRSpill ) ; if ( FuncInfo -> allocateSGPRSpillToVGPR ( MF , FI ) ) { NewReservedRegs = true ; bool Spilled = TRI -> eliminateSGPRToVGPRSpillFrameIndex ( MI , FI , nullptr , LIS ) ; ( void ) Spilled ; assert ( Spilled && <STR_LIT> ) ; SpillFIs . set ( FI ) ; } } } for ( MachineBasicBlock & MBB : MF ) { for ( auto SSpill : FuncInfo -> getSGPRSpillVGPRs ( ) ) MBB . addLiveIn ( SSpill . VGPR ) ; MBB . sortUniqueLiveIns ( ) ; for ( MachineInstr & MI : MBB ) { if ( MI . isDebugValue ( ) && MI . getOperand ( <NUM_LIT> ) . isFI ( ) && SpillFIs [ MI . getOperand ( <NUM_LIT> ) . getIndex ( ) ] ) { MI . getOperand ( <NUM_LIT> ) . ChangeToRegister ( Register ( ) , false ) ; MI . getOperand ( <NUM_LIT> ) . setIsDebug ( ) ; } } } MadeChange = true ; } else if ( FuncInfo -> VGPRReservedForSGPRSpill ) { FuncInfo -> removeVGPRForSGPRSpill ( FuncInfo -> VGPRReservedForSGPRSpill , MF ) ; } SaveBlocks . clear ( ) ; RestoreBlocks . clear ( ) ; if ( NewReservedRegs ) MRI . freezeReservedRegs (


<s> if ( NewMCID . hasOptionalDef ( ) ) MIB . add ( HasCC ? t1CondCodeOp ( CCDead ) : condCodeOp ( ) ) ; MIB . add ( MI -> getOperand ( <NUM_LIT> ) ) ; } else { MIB . add ( MI -> getOperand ( <NUM_LIT> ) ) ; if ( NewMCID . hasOptionalDef ( ) ) MIB . add ( HasCC ? t1CondCodeOp ( CCDead ) : condCodeOp ( ) ) ; } unsigned NumOps = MCID . getNumOperands ( ) ; for ( unsigned i = <NUM_LIT> , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) { if ( i < NumOps && MCID . OpInfo [ i ] . isOptionalDef ( ) ) continue ; if ( ( MCID . getOpcode ( ) == <STR_LIT> || MCID . getOpcode ( ) == <STR_LIT> || MCID . getOpcode ( ) == <STR_LIT> || MCID . getOpcode ( ) == <STR_LIT> || MCID . getOpcode ( ) == <STR_LIT> || MCID . getOpcode ( ) == <STR_LIT> ) && i == <NUM_LIT> ) continue ; bool isPred = ( i < NumOps && MCID . OpInfo [ i ] . isPredicate ( ) ) ; if ( SkipPred && isPred ) continue ; const MachineOperand & MO = MI -> getOperand ( i ) ; if ( MO . isReg ( ) && MO . isImplicit ( ) && MO . getReg ( ) == <STR_LIT> ) continue ; MIB . add ( MO ) ; } if ( ! MCID . isPredicable ( ) && NewMCID . isPredicable ( ) ) MIB . add ( predOps ( <STR_LIT> ) ) ; MIB . setMIFlags ( MI -> getFlags ( ) ) ; LLVM_DEBUG ( errs ( ) << <STR_LIT> << * MI << <STR_LIT> << * MIB ) ; MBB . erase_instr (


<s> CommentString = <STR_LIT> ; HasLEB128 = true ; SupportsDebugInformation = true ; SunStyleELFSectionSwitchSyntax = true ; UsesELFSectionDirectiveForBSS = true ; WeakRefDirective = <STR_LIT> ; PrivateGlobalPrefix =


<s> for ( auto * DVL : DbgValueLists ) { BuildMI ( * DVL -> getParent ( ) , DVL , DVL -> getDebugLoc ( ) , TII . get ( TargetOpcode :: DBG_VALUE ) , false , Register ( ) , DVL -> getOperand ( <NUM_LIT> ) . getMetadata ( ) , DVL -> getOperand ( <NUM_LIT> ) . getMetadata ( ) ) ; DVL -> eraseFromParent (


<s> Triple TheTriple ( STI . getTargetTriple ( ) ) ; Is<ISA_LIT>64 = ( TheTriple . getArch ( ) == Triple :: ppc64 || TheTriple . getArch ( ) == Triple :: ppc64le ) ; IsDarwin = TheTriple . isMacOSX ( ) ; setAvailableFeatures ( ComputeAvailableFeatures ( STI . getFeatureBits


<s> Instruction * MVEGatherScatterLowering :: tryCreateMaskedGatherBase ( IntrinsicInst * I , Value * Ptr , IRBuilder < > & Builder , int64_t Increment ) { using namespace PatternMatch ; auto * Ty = cast < FixedVectorType > ( I -> getType ( ) ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; if ( Ty -> getNumElements ( ) != <NUM_LIT> || Ty -> getScalarSizeInBits ( ) != <NUM_LIT> ) return nullptr ; Value * Mask = I -> getArgOperand ( <NUM_LIT> ) ; if ( match ( Mask , m_One ( ) ) ) return Builder . CreateIntrinsic ( <STR_LIT> , { Ty , Ptr -> getType ( ) } , { Ptr , Builder .


<s> rtx reg ; if ( ! JUMP_P ( insn ) || recog_memoized ( insn

) != CODE_FOR_loop_end ) return NULL_RTX ;


<s> std :: tie ( Ops [ <NUM_LIT> ] , Ops [ <NUM_LIT> ] ) = expandUnalignedLoad ( LN , DAG ) ; return DAG . getMergeValues ( Ops , SDLoc ( N ) ) ; } if ( ! IsFast ) return SDValue ( ) ; } if ( ! shouldCombineMemoryType ( VT ) ) return SDValue ( ) ; EVT NewVT = getEquivalentMemType ( * DAG . getContext ( ) , VT ) ; SDValue NewLoad = DAG . getLoad ( NewVT , SL , LN -> getChain ( ) , LN -> getBasePtr ( ) , LN -> getMemOperand ( ) ) ; SDValue BC = DAG . getNode ( <STR_LIT> , SL


<s> op0 = gen_reg_rtx ( GET_MODE ( x ) ) ; emit_move_insn ( op0 , x ) ; } emit_insn ( gen_rtx_SET ( dest , const0_rtx ) ) ; if ( GET_MODE ( op0 ) != DImode ) { temp = gen_reg_rtx ( DImode ) ; convert_move ( temp , op0 , <NUM_LIT> ) ; } else temp = op0 ; emit_insn ( gen_rtx_SET ( dest , gen_rtx_IF_THEN_ELSE ( GET_MODE ( dest ) , gen_rtx_fmt_ee ( compare_code , DImode , temp , const0_rtx ) , const1_rtx , dest ) ) ) ; return


<s> return ( ( reg_addr [ mode ] . addr_mask

[ RELOAD_REG_ANY ] & RELOAD_REG_QUAD_OFFSET ) != <NUM_LIT> ) ;


<s> unsigned getMemOffsetReg ( ) const { assert ( ( Kind == k_MemoryReg ) && <STR_LIT>


<s> if ( N -> getAlignment ( ) < <NUM_LIT> ) report_fatal_error ( <STR_LIT> ) ; return DAG . getTruncStore ( N -> getChain ( ) , SDLoc ( Op ) , N -> getVal ( ) , N -> getBasePtr ( ) , N -> getPointerInfo ( ) , <STR_LIT> , N -> getAlignment ( ) , N -> getMemOperand ( ) -> getFlags ( ) , N -> getAAInfo ( ) ) ; } if ( N -> getMemoryVT ( ) == <STR_LIT> ) return DAG . getTruncStore ( N -> getChain ( ) , SDLoc ( Op ) , N -> getVal ( ) , N -> getBasePtr ( ) , N -> getPointerInfo ( ) , <STR_LIT> , N -> getAlignment ( ) , N -> getMemOperand ( ) -> getFlags ( ) , N -> getAAInfo ( ) ) ; return SDValue ( )


<s> vmlsq_u16 ( uint16x8_t a , uint16x8_t b , uint16x8_t c ) { uint16x8_t result ; __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT> ( b ) , <STR_LIT> ( c ) : ) ; return result


<s> OPCODE ( CALL ) ; OPCODE ( SIBCALL ) ; OPCODE ( PCREL_WRAPPER ) ; OPCODE ( PCREL_OFFSET ) ; OPCODE ( IABS ) ; OPCODE ( ICMP ) ; OPCODE ( FCMP ) ; OPCODE ( TM ) ; OPCODE ( BR_CCMASK ) ; OPCODE ( SELECT_CCMASK ) ; OPCODE ( ADJDYNALLOC ) ; OPCODE ( EXTRACT_ACCESS ) ; OPCODE ( UMUL_LOHI64 ) ; OPCODE ( SDIVREM64 ) ; OPCODE ( UDIVREM32 ) ; OPCODE ( UDIVREM64 ) ; OPCODE ( MVC ) ; OPCODE ( MVC_LOOP ) ; OPCODE ( NC ) ; OPCODE ( NC_LOOP ) ; OPCODE ( OC ) ; OPCODE ( OC_LOOP ) ; OPCODE ( XC ) ; OPCODE ( XC_LOOP ) ; OPCODE ( CLC ) ; OPCODE ( CLC_LOOP ) ; OPCODE ( STRCMP ) ; OPCODE ( STPCPY ) ; OPCODE ( SEARCH_STRING ) ; OPCODE ( IPM ) ; OPCODE ( SERIALIZE )


<s> if ( set ) { x = SET_SRC ( set ) ; if ( GET_CODE ( x ) == HIGH && absolute_symbolic_operand ( XEXP ( x , <NUM_LIT> ) , VOIDmode ) ) return ! mips_lo_sum_offset_lookup

( htab , XEXP ( x , <NUM_LIT> ) , NO_INSERT ) ;


<s> PM . add ( create<ISA_LIT>BranchSelectionPass ( ) ) ; PM . add ( create<ISA_LIT>LLRPPass ( * this ) ) ; return false


<s> static const char * sparc_mangle_fundamental_type ( tree type ) { if ( ! TARGET_64BIT && TYPE_MAIN_VARIANT ( type ) == long_double_type_node && TARGET_LONG_DOUBLE_128 ) return <STR_LIT> ; return NULL


<s> StringRef getPassName ( ) const override { return


<s> MCCodeEmitter * llvm :: create<ISA_LIT>MCCodeEmitter ( const MCInstrInfo & MCII , const MCRegisterInfo & MRI , const MCSubtargetInfo & STI


<s> rtx ptr , mem ; ptr = plus_constant ( Pmode , virtual_incoming_args_rtx , REG_PARM_STACK_SPACE ( cfun -> decl ) - gp_saved * UNITS_PER_WORD ) ; mem = gen_frame_mem ( BLKmode , ptr ) ; set_mem_alias_set ( mem , get_varargs_alias_set ( ) ) ; move_block_from_reg ( local_cum . num_gprs + GP_ARG_FIRST , mem , gp_saved ) ; } if ( fp_saved > <NUM_LIT> ) { machine_mode mode ; int off , i ; off = ROUND_DOWN ( - gp_saved * UNITS_PER_WORD , UNITS_PER_FPVALUE ) ; off -= fp_saved * UNITS_PER_FPREG ; mode = TARGET_SINGLE_FLOAT ? SFmode : DFmode


<s> Builder . SetCurrentDebugLocation ( FDiv . getDebugLoc ( ) ) ; Function * Decl = <STR_LIT> ( Mod , <STR_LIT> ) ; Value * Num = FDiv . getOperand ( <NUM_LIT> ) ; Value * Den = FDiv . getOperand ( <NUM_LIT> ) ; Value * NewFDiv = nullptr ; if ( VectorType * VT = dyn_cast < VectorType > ( Ty ) ) { NewFDiv = UndefValue :: get ( VT ) ; for ( unsigned I = <NUM_LIT> , E = VT -> getNumElements ( ) ; I != E ; ++ I ) { Value * NumEltI = Builder . CreateExtractElement ( Num , I ) ; Value * DenEltI = Builder . CreateExtractElement ( Den , I ) ; Value * NewElt ; if ( shouldKeepFDivF32 ( NumEltI , UnsafeDiv ) ) { NewElt = Builder . CreateFDiv ( NumEltI , DenEltI ) ; } else { NewElt = Builder . CreateCall ( Decl , { NumEltI , DenEltI } ) ; } NewFDiv = Builder . CreateInsertElement ( NewFDiv , NewElt , I


<s> case Type :: FloatTyID : case Type :: DoubleTyID : return true ; case Type :: FP128TyID : return Subtarget . hasP9Vector


<s> LocVT = <STR_LIT> ; if ( ArgFlags . isSExt ( ) ) LocInfo = CCValAssign :: SExt ; else if ( ArgFlags . isZExt ( ) ) LocInfo = CCValAssign :: ZExt ; else LocInfo = CCValAssign :: AExt ; } unsigned Reg ; bool AllocateFloatsInIntReg = State . isVarArg ( ) || ValNo > <NUM_LIT> || State . getFirstUnallocated ( F32Regs , FloatRegsSize ) != ValNo ; unsigned OrigAlign = ArgFlags . getOrigAlign ( ) ; bool isI64 = ( ValVT == <STR_LIT> && OrigAlign == <NUM_LIT> ) ; if ( ValVT == <STR_LIT> || ( ValVT == <STR_LIT> && AllocateFloatsInIntReg ) ) { Reg = State . AllocateReg ( IntRegs , IntRegsSize ) ; if ( isI64 && ( Reg == <STR_LIT> || Reg == <STR_LIT> ) ) Reg = State . AllocateReg ( IntRegs , IntRegsSize ) ; LocVT = <STR_LIT> ; } else if ( ValVT == <STR_LIT> && AllocateFloatsInIntReg ) { Reg = State . AllocateReg ( IntRegs , IntRegsSize ) ; if ( Reg == <STR_LIT> || Reg == <STR_LIT> ) Reg


<s> const uint64_t F = MI . getDesc ( ) . TSFlags ; if ( ( F >> <STR_LIT> ) & <STR_LIT> )


<s> MachineInstrBuilder MIB = BuildMI ( & MBB , dl , get ( Cond [ <NUM_LIT> ] . getImm ( ) ) ) ; MIB . addReg ( Cond [ <NUM_LIT> ] . getReg ( ) ) . addMBB ( TBB ) ; DEBUG ( cerr << <STR_LIT> ) ; DEBUG ( ( * MIB ) . dump ( ) ) ; } return <NUM_LIT> ; } else { MachineInstrBuilder MIB = BuildMI ( & MBB , dl , get ( Cond [ <NUM_LIT> ] . getImm ( ) ) ) ; MachineInstrBuilder MIB2 = BuildMI ( & MBB , dl , get ( <STR_LIT> ) ) ; MIB . addReg ( Cond [ <NUM_LIT> ] . getReg ( ) ) . addMBB ( TBB ) ; MIB2 . addMBB ( FBB ) ; DEBUG ( cerr << <STR_LIT> ) ; DEBUG ( ( * MIB ) . dump ( ) ) ; DEBUG ( cerr <<


<s> return :: isUNPCKLMask ( N -> getMask ( ) , N -> getValueType ( <NUM_LIT> ) , HasAVX2 ,


<s> static const CostTblEntry CostTbl [ ] = { { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , ReciprocalDivCost } , { <STR_LIT> , <STR_LIT> , ReciprocalDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , ReciprocalDivCost } , { <STR_LIT> , <STR_LIT> , ReciprocalDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost

} , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , } ;


<s> return isLegalToVectorizeMemChain ( ChainSizeInBytes , Alignment , AddrSpace


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : JTOpcode = <STR_LIT> ; break ; case <STR_LIT> : JTOpcode = <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : JTOpcode = <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : JTOpcode = <STR_LIT> ; break ; } unsigned NumOps = MI -> getDesc ( ) . getNumOperands ( ) ; MachineOperand JTOp = MI -> getOperand ( NumOps - ( MI -> isPredicable ( ) ? <NUM_LIT> : <NUM_LIT> ) ) ; unsigned JTI = JTOp . getIndex ( ) ; unsigned Size = JT [ JTI ] . MBBs . size ( ) * sizeof ( uint32_t ) ; MachineBasicBlock * JumpTableBB = MF -> CreateMachineBasicBlock ( ) ; MF -> insert ( std :: next ( MachineFunction :: iterator ( MBB ) ) , JumpTableBB ) ; MachineInstr * CPEMI = BuildMI ( * JumpTableBB , JumpTableBB -> begin ( ) , DebugLoc ( ) , TII -> get ( JTOpcode ) ) . addImm ( i ++ ) . addJumpTableIndex ( JTI ) . addImm ( Size ) ; CPEMIs . push_back ( CPEMI


<s> static SDNode * findFlagUse ( SDNode * N ) { unsigned FlagResNo = N -> getNumValues ( ) - <NUM_LIT> ; for ( SDNode :: use_iterator I = N -> use_begin ( ) , E = N -> use_end ( ) ; I != E ; ++ I ) { SDUse & Use = I . getUse


<s> if ( TREE_THIS_VOLATILE ( cfun -> decl ) && ! ( m -> frame . nregs || m -> frame . nsseregs || frame_pointer_needed ) ) { rtx dummy_reg = gen_rtx_REG ( word_mode , TARGET_64BIT ? AX_REG : SI_REG ) ; rtx_insn * insn_push = emit_insn ( gen_push ( dummy_reg ) ) ; rtx_insn * insn_pop = emit_insn ( gen_pop ( dummy_reg ) ) ; m -> fs . sp_offset -= UNITS_PER_WORD ; if ( m -> fs . cfa_reg == stack_pointer_rtx ) { m -> fs . cfa_offset -= UNITS_PER_WORD ; rtx x = plus_constant ( Pmode , stack_pointer_rtx , - UNITS_PER_WORD ) ; x = gen_rtx_SET ( stack_pointer_rtx , x ) ; add_reg_note ( insn_push , REG_CFA_ADJUST_CFA , x ) ; RTX_FRAME_RELATED_P ( insn_push ) = <NUM_LIT> ; x = plus_constant ( Pmode , stack_pointer_rtx , UNITS_PER_WORD ) ; x = gen_rtx_SET ( stack_pointer_rtx , x ) ; add_reg_note ( insn_pop , REG_CFA_ADJUST_CFA , x ) ; RTX_FRAME_RELATED_P ( insn_pop ) = <NUM_LIT> ; } emit_insn ( gen_blockage ( ) ) ; } if ( size < ( <NUM_LIT> << PARAM_VALUE ( PARAM_STACK_CLASH_PROTECTION_GUARD_SIZE ) ) ) { pro_epilogue_adjust_stack ( stack_pointer_rtx , stack_pointer_rtx , GEN_INT ( - size ) , - <NUM_LIT> , m -> fs . cfa_reg == stack_pointer_rtx ) ; dump_stack_clash_frame_info ( NO_PROBE_SMALL_FRAME , true ) ; return ; } HOST_WIDE_INT probe_interval = get_probe_interval ( ) ; if ( size <= <NUM_LIT> * probe_interval ) { HOST_WIDE_INT i ; for ( i = probe_interval ; i <= size ; i += probe_interval ) { rtx insn = pro_epilogue_adjust_stack ( stack_pointer_rtx , stack_pointer_rtx , GEN_INT ( - probe_interval ) , - <NUM_LIT> , m -> fs . cfa_reg == stack_pointer_rtx ) ; add_reg_note ( insn , REG_STACK_CHECK , const0_rtx ) ; emit_stack_probe ( stack_pointer_rtx ) ; emit_insn ( gen_blockage ( ) ) ; } HOST_WIDE_INT residual = ( i - probe_interval - size ) ; if ( residual ) pro_epilogue_adjust_stack ( stack_pointer_rtx , stack_pointer_rtx , GEN_INT ( residual ) , - <NUM_LIT> , m -> fs . cfa_reg == stack_pointer_rtx ) ; dump_stack_clash_frame_info ( PROBE_INLINE , residual != <NUM_LIT> ) ; } else { gcc_assert ( int_registers_saved ) ; struct scratch_reg sr


<s> if ( reload_completed && cfun -> machine && ( cfun -> machine -> is_interrupt || cfun -> machine -> is_signal ) ) return <NUM_LIT> ; return <NUM_LIT>


<s> EVT SrcVT = SrcVal . getValueType ( ) ; EVT DstVT = Op . getValueType ( ) ; const unsigned DstSz = Op . getValueType ( ) . getSizeInBits ( ) ; const unsigned SrcSz = SrcVT . getSizeInBits ( ) ; ( void ) DstSz ; assert ( DstSz < SrcSz && SrcSz <= <NUM_LIT> && DstSz >= <NUM_LIT> && <STR_LIT> ) ; assert ( ( ! Subtarget -> hasFP64 ( ) || ! Subtarget -> hasFP<ISA_LIT>v8Base


<s> void <ISA_LIT>InstPrinter :: printU8ImmOperand ( const MCInst * MI , unsigned OpNo , raw_ostream & O ) { unsigned char Value = MI -> getOperand ( OpNo ) . getImm (


<s> switch ( MI -> getOpcode ( ) ) { case <STR_LIT> : { MachineFunction * MF = BB -> getParent ( ) ; auto * FuncInfo = MF -> getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; FuncInfo -> addAllocaAdjustInst ( MI ) ; return BB ; } default : llvm_unreachable ( <STR_LIT> )


<s> bool <ISA_LIT>AsmParser :: ParseDirectiveAMDKernelCodeT ( ) { amd_kernel_code_t Header ; <STR_LIT> ( Header , & getSTI ( ) ) ; while ( true ) { while ( trySkipToken ( AsmToken :: EndOfStatement ) ) ; StringRef ID ; if ( ! parseId ( ID , <STR_LIT> ) ) return true ; if ( ID == <STR_LIT> ) break ; if ( ParseAMDKernelCodeTValue ( ID , Header


<s> if ( ! mayTailCallThisCC ( CalleeCC ) ) return false ; MachineFunction & MF = DAG . getMachineFunction ( ) ; const Function & CallerF = MF . getFunction ( ) ; CallingConv :: ID CallerCC = CallerF . getCallingConv ( ) ; if ( CallerCC == CallingConv :: C && <ISA_LIT>RegisterInfo :: hasSVEArgsOrReturn ( & MF ) ) CallerCC = CallingConv :: <ISA_LIT>_SVE_VectorCall ; bool CCMatch = CallerCC == CalleeCC ; if ( CallerCC == CallingConv :: Win64 && ! Subtarget -> isTargetWindows ( ) && CalleeCC != CallingConv :: Win64 ) return false ; for ( Function :: const_arg_iterator i = CallerF . arg_begin ( ) , e = CallerF . arg_end ( ) ; i != e ; ++ i ) { if ( i -> hasByValAttr ( ) ) return false ; if ( i -> hasInRegAttr ( ) ) return false ; } if ( getTargetMachine ( ) . Options . GuaranteedTailCallOpt ) return canGuaranteeTCO ( CalleeCC ) && CCMatch ; if ( GlobalAddressSDNode * G = dyn_cast < GlobalAddressSDNode > ( Callee ) ) { const GlobalValue * GV = G -> getGlobal ( ) ; const Triple & TT = getTargetMachine ( ) . getTargetTriple ( ) ; if ( GV -> hasExternalWeakLinkage ( ) && ( ! TT . isOSWindows ( ) || TT . isOSBinFormatELF ( ) || TT . isOSBinFormatMachO ( ) ) ) return false ; } assert ( ( ! isVarArg || CalleeCC == CallingConv :: C ) && <STR_LIT> ) ; LLVMContext & C = * DAG . getContext ( ) ; if ( isVarArg && ! Outs . empty ( ) ) { SmallVector < CCValAssign , <NUM_LIT> > ArgLocs ; CCState CCInfo ( CalleeCC , isVarArg , MF , ArgLocs , C ) ; CCInfo . AnalyzeCallOperands ( Outs , CCAssignFnForCall ( CalleeCC , true ) ) ; for ( const CCValAssign & ArgLoc : ArgLocs ) if ( ! ArgLoc . isRegLoc ( ) ) return false ; } if ( ! CCState :: resultsCompatible ( CalleeCC , CallerCC , MF , C , Ins , CCAssignFnForCall ( CalleeCC , isVarArg ) , CCAssignFnForCall ( CallerCC , isVarArg ) ) ) return false ; const <ISA_LIT>RegisterInfo * TRI = Subtarget -> getRegisterInfo ( ) ; const uint32_t * CallerPreserved = TRI -> getCallPreservedMask ( MF , CallerCC ) ; if ( ! CCMatch ) { const uint32_t * CalleePreserved = TRI -> getCallPreservedMask ( MF , CalleeCC ) ; if ( Subtarget -> hasCustomCallingConv ( ) ) { TRI -> UpdateCustomCallPreservedMask ( MF


<s> if ( RegNo > <NUM_LIT> ) return MCDisassembler :: Fail ; unsigned Reg = getReg ( Decoder , <STR_LIT> ,


<s> static SDValue lowerV8F64VectorShuffle ( SDValue Op , SDValue V1 , SDValue V2 , const <ISA_LIT>Subtarget * Subtarget , SelectionDAG & DAG ) { SDLoc DL ( Op ) ; assert ( V1 . getSimpleValueType ( ) == <STR_LIT> && <STR_LIT> ) ; assert ( V2 . getSimpleValueType ( ) == <STR_LIT> && <STR_LIT> ) ; ShuffleVectorSDNode * SVOp = cast < ShuffleVectorSDNode > ( Op ) ; ArrayRef < int > Mask = SVOp


<s> assemble_external ( decl ) ; SET_SYMBOL_REF_DECL ( x , NULL ) ; } } if ( size == UNITS_PER_WORD && aligned_p && function_label_operand ( x , VOIDmode ) ) { fputs ( size == <NUM_LIT> ? <STR_LIT> : <STR_LIT> , asm_out_file ) ; if ( ! TARGET_FAST_INDIRECT_CALLS ) fputs ( <STR_LIT> , asm_out_file ) ; output_addr_const ( asm_out_file , x ) ; fputc ( '\n' , asm_out_file ) ; result = true ; } else result = default_assemble_integer ( x


<s> unsigned getInlineAsmMemConstraint ( StringRef ConstraintCode ) const override { if ( ConstraintCode == <STR_LIT> ) return InlineAsm :: Constraint_Q ; return TargetLowering :: getInlineAsmMemConstraint ( ConstraintCode


<s> MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; if ( ! FPSI && needsFP ( MF ) ) { int FPOffset = getFramePointerSaveOffset ( is<ISA_LIT>64 , isDarwinABI ) ; FPSI = MFI -> CreateFixedObject ( is<ISA_LIT>64 ? <NUM_LIT> : <NUM_LIT> , FPOffset , true ) ; FI -> setFramePointerSaveIndex ( FPSI ) ; } int TCSPDelta = <NUM_LIT> ; if ( MF . getTarget ( ) . Options . GuaranteedTailCallOpt && ( TCSPDelta = FI -> getTailCallSPDelta ( ) ) < <NUM_LIT> ) { MFI -> CreateFixedObject ( - <NUM_LIT> * TCSPDelta , TCSPDelta , true ) ; } if ( ! is<ISA_LIT>64 && ! isDarwinABI && ( MRI . isPhysRegUsed ( <STR_LIT> ) || MRI . isPhysRegUsed ( <STR_LIT> ) || MRI . isPhysRegUsed ( <STR_LIT> ) ) ) { int FrameIdx = MFI -> CreateFixedObject ( ( uint64_t ) <NUM_LIT> , ( int64_t )


<s> static void generatePsEndPgm ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , DebugLoc DL , const <ISA_LIT>InstrInfo * TII ) { BuildMI ( MBB , I , DL , TII -> get ( <STR_LIT> ) ) . addImm ( <NUM_LIT> ) . addReg ( <STR_LIT> , RegState :: Undef ) . addReg ( <STR_LIT> , RegState :: Undef ) . addReg ( <STR_LIT> , RegState :: Undef ) . addReg ( <STR_LIT> , RegState :: Undef ) . addImm ( <NUM_LIT>

) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ;


<s> zero = SET_SRC ( elt ) ; if ( ! REG_P ( reg ) || GET_MODE ( reg ) != expected_mode || zero != CONST0_RTX ( SImode ) ) return false ; regno = REGNO ( reg ) ; if ( vfp ) { if ( i != first_set && regno != last_regno + <NUM_LIT> ) return false ; } else { if ( regno == SP_REGNUM || regno == PC_REGNUM ) return false ; if ( i != first_set && regno <= last_regno ) return


<s> if ( TFI -> hasFP ( MF ) ) return <STR_LIT> ; return <STR_LIT>


<s> rtx end_label = gen_label_rtx ( ) ; value = force_reg ( QImode , value ) ; if ( need_end ) end = expand_binop ( Pmode , add_optab , itr , size , NULL_RTX , <NUM_LIT> , OPTAB_WIDEN ) ; emit_cmp_and_jump_insns ( size , const0_rtx , EQ , NULL , SImode , <NUM_LIT> , end_label ) ; if ( ! need_end ) end = expand_binop ( Pmode , add_optab , itr , size , NULL_RTX , <NUM_LIT> , OPTAB_WIDEN ) ; emit_label ( byte_mode_label ) ; nds32_emit_post_inc_load_store ( value , itr , QImode , false ) ; emit_cmp_and_jump_insns ( end , itr , NE , NULL , Pmode , <NUM_LIT> , byte_mode_label ) ; emit_label (


<s> if ( isAsynchronousEHPersonality ( Personality ) ) return ! Call . doesNotAccessMemory


<s> fputs ( <STR_LIT> , file ) ; return ; } if ( code == 'y' && STACK_TOP_P ( x ) ) { fputs ( <STR_LIT> , file ) ; return ; } if ( code == 'w' ) msize = <NUM_LIT> ; else if ( code == 'b' ) msize = <NUM_LIT> ; else if ( code == 'k' ) msize = <NUM_LIT> ; else if ( code == 'q' ) msize = <NUM_LIT> ; else if ( code == 'h' ) msize = <NUM_LIT> ; else if ( code == 'x' ) msize = <NUM_LIT> ; else if ( code == 't' ) msize = <NUM_LIT> ; else if ( code == 'g' ) msize = <NUM_LIT> ; else msize = GET_MODE_SIZE ( GET_MODE ( x ) ) ; regno = REGNO ( x ) ; if ( regno == ARG_POINTER_REGNUM || regno == FRAME_POINTER_REGNUM || regno == FPSR_REG ) { output_operand_lossage ( <STR_LIT> , reg_names [ regno ] ) ; return ; } else if ( regno == FLAGS_REG ) { output_operand_lossage ( <STR_LIT> ) ; return ; } if ( code == 'V' ) { if ( GENERAL_REGNO_P ( regno ) ) msize = GET_MODE_SIZE ( word_mode ) ; else error ( <STR_LIT> ) ; } duplicated = code == 'd' && TARGET_AVX ; switch ( msize ) { case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : if ( GENERAL_REGNO_P ( regno ) && msize > GET_MODE_SIZE ( word_mode ) ) warning ( <NUM_LIT> , <STR_LIT> ) ; case <NUM_LIT> : if ( LEGACY_INT_REGNO_P ( regno ) ) putc ( msize > <NUM_LIT> && TARGET_64BIT ? 'r' : 'e' , file ) ; case <NUM_LIT> : normal : reg = hi_reg_name [ regno ] ; break ; case <NUM_LIT> : if ( regno >= ARRAY_SIZE ( qi_reg_name ) ) goto normal ; if ( ! ANY_QI_REGNO_P ( regno ) ) error ( <STR_LIT> ) ; reg = qi_reg_name [ regno ] ; break ; case <NUM_LIT> : if ( regno >= ARRAY_SIZE ( qi_high_reg_name ) ) goto normal ; reg = qi_high_reg_name [ regno ] ; break ; case <NUM_LIT> : case <NUM_LIT> : if ( SSE_REGNO_P ( regno ) ) { gcc_assert ( ! duplicated ) ; putc ( msize == <NUM_LIT> ? 'y' : 'z' , file ) ; reg = hi_reg_name [ regno ] + <NUM_LIT> ; break ; } goto normal ; default : gcc_unreachable ( ) ; } fputs ( reg , file


<s> virtual const <ISA_LIT>Subtarget * getSubtargetImpl ( ) const { return & Subtarget


<s> OPCODE ( Lo ) ; OPCODE ( FENCE ) ; OPCODE ( SELECT_CC ) ; } return


<s> static DecodeStatus DecodeSimm18Lsl3 ( MCInst & Inst , unsigned Insn , uint64_t Address , const void * Decoder ) { Inst . addOperand ( MCOperand :: CreateImm ( SignExtend32 < <NUM_LIT> > ( Insn ) * <NUM_LIT> ) ) ; return MCDisassembler :: Success


<s> emitRX ( Opcode , DstReg , MCOperand :: createImm


<s> bool function_instance :: reads_global_state_p ( ) const { unsigned int flags = call_properties ( ) ; if ( flags & CP_READ_FPCR ) return true ; return flags & ( CP_READ_MEMORY |


<s> vec_int4 a0123 ; a0123 = spu_add ( spu_rlmaska ( ( vec_int4 ) ( a ) , - <NUM_LIT> ) , spu_extend ( a ) ) ; return ( vec_adds ( a0123 , b


<s> if ( isInt < <NUM_LIT> > ( Val ) ) { int64_t Hi20 = ( ( Val + <NUM_LIT> ) >> <NUM_LIT> ) & <NUM_LIT> ; int64_t Lo12 = SignExtend64 < <NUM_LIT> > ( Val ) ; if ( Hi20 ) Res . push_back ( <STR_LIT> ( <STR_LIT> , Hi20 ) ) ; if ( Lo12 || Hi20 == <NUM_LIT> ) { unsigned AddiOpc = ( IsRV64 && Hi20 )


<s> MCCodeEmitter * llvm :: create<ISA_LIT>MCCodeEmitter ( const MCInstrInfo & MCII , const MCRegisterInfo & MRI , const MCSubtargetInfo & STI , MCContext & Ctx ) { return new <ISA_LIT>MCCodeEmitter ( MCII


<s> StringRef getDimName ( Dim dim ) { switch ( dim ) { CASE_SUF ( Dim , DIM , <NUM_LIT> ) CASE_SUF ( Dim , DIM , <NUM_LIT> ) CASE_SUF ( Dim , DIM , <NUM_LIT> ) CASE_SUF ( Dim , DIM , Cube ) CASE_SUF (

Dim , DIM , Rect ) CASE_SUF ( Dim , DIM , Buffer ) CASE_SUF ( Dim , DIM , SubpassData ) break ;


<s> extern __inline void __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) _wrussq ( unsigned long long __B , void *


<s> bool hasHipeCC = ( F ? F -> getCallingConv ( ) == CallingConv :: HiPE : false ) ; if ( hasHipeCC ) return & <STR_LIT> ; return &


<s> bool vector_ret_type_p = ( ( ret_type && VECTOR_TYPE_P ( ret_type ) ) || ( ! ret_type && VECTOR_MODE_P ( mode ) ) ) ; if ( ret_type ) { int unsignedp = TYPE_UNSIGNED ( ret_type ) ; mode = promote_function_mode ( ret_type , mode , & unsignedp , fntype_or_decl , <NUM_LIT> ) ; } gcc_assert ( GET_MODE_CLASS ( mode ) == MODE_INT || SCALAR_FLOAT_MODE_P ( mode ) || ( TARGET_VX_ABI && vector_ret_type_p ) ) ; gcc_assert ( GET_MODE_SIZE ( mode ) <= ( TARGET_VX_ABI ? <NUM_LIT> : <NUM_LIT> ) ) ; if ( TARGET_VX_ABI && vector_ret_type_p ) return gen_rtx_REG ( mode , FIRST_VEC_ARG_REGNO ) ; else if ( TARGET_HARD_FLOAT && SCALAR_FLOAT_MODE_P ( mode ) ) return gen_rtx_REG ( mode , <NUM_LIT> ) ; else if ( GET_MODE_SIZE ( mode ) <= UNITS_PER_LONG || UNITS_PER_LONG == UNITS_PER_WORD ) return gen_rtx_REG ( mode , <NUM_LIT> ) ; else if ( GET_MODE_SIZE ( mode ) == <NUM_LIT> * UNITS_PER_LONG ) { rtvec p = rtvec_alloc ( <NUM_LIT> ) ; RTVEC_ELT ( p , <NUM_LIT> ) = gen_rtx_EXPR_LIST ( SImode , gen_rtx_REG ( SImode , <NUM_LIT> ) , const0_rtx ) ; RTVEC_ELT ( p , <NUM_LIT> ) = gen_rtx_EXPR_LIST ( SImode , gen_rtx_REG ( SImode , <NUM_LIT> ) , GEN_INT ( <NUM_LIT> ) ) ; return gen_rtx_PARALLEL ( mode , p ) ; } gcc_unreachable (


<s> MachineSDNode :: mmo_iterator MemOp = MF . allocateMemRefsArray ( <NUM_LIT> ) ; MemOp [ <NUM_LIT> ] = cast < MemSDNode > ( N ) -> getMemOperand ( ) ; cast < MachineSDNode > ( CmpSwap ) -> setMemRefs ( MemOp , MemOp + <NUM_LIT> ) ; bool isBigEndian = DAG . getDataLayout ( ) . isBigEndian ( ) ; Results . push_back ( DAG . getTargetExtractSubreg ( isBigEndian ? <STR_LIT> : <STR_LIT> , SDLoc ( N ) , <STR_LIT> , SDValue ( CmpSwap , <NUM_LIT> ) ) ) ; Results . push_back ( DAG . getTargetExtractSubreg ( isBigEndian ? <STR_LIT> : <STR_LIT> , SDLoc ( N ) , <STR_LIT> , SDValue ( CmpSwap , <NUM_LIT> ) ) ) ; Results . push_back ( SDValue ( CmpSwap , <NUM_LIT>


<s> if ( ! TargetRegisterInfo :: isVirtualRegister ( Reg ) ) continue ; ( void ) LiveRegs . insert ( Reg


<s> if ( VT == <STR_LIT> && <ISA_LIT>SubTarget . is<ISA_LIT>64 ( ) ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; case 'f' : if ( VT == <STR_LIT> || VT == <STR_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; if ( VT == <STR_LIT> || VT == <STR_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; break ; case 'v' : return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; case 'y' : return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; } } else if ( Constraint == <STR_LIT> ) { return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; } std :: pair < unsigned , const TargetRegisterClass * > R = TargetLowering :: getRegForInlineAsmConstraint ( Constraint , VT ) ; if ( R . first && VT == <STR_LIT> && <ISA_LIT>SubTarget . is<ISA_LIT>64 (

) && <STR_LIT> . contains ( R . first ) ) {


<s> if ( CONST_INT_P ( src ) ) { HOST_WIDE_INT val = INTVAL ( src ) ; emit_set_insn ( dest , GEN_INT ( val & <NUM_LIT> ) ) ; if ( ( val >> <NUM_LIT> ) & <NUM_LIT> ) { emit_set_insn ( gen_rtx_ZERO_EXTRACT ( SImode , dest , GEN_INT ( <NUM_LIT> ) , GEN_INT ( <NUM_LIT> ) ) , GEN_INT ( ( val >> <NUM_LIT> ) & <NUM_LIT> ) ) ; rtx_insn * insn = get_last_insn ( ) ; set_unique_reg_note ( insn , REG_EQUAL , copy_rtx ( src ) ) ; } return ; } emit_set_insn ( dest , gen_rtx_HIGH ( SImode , src


<s> <ISA_LIT>CallFrameOptimization :: InstClassification <ISA_LIT>CallFrameOptimization :: classifyInstruction ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const <ISA_LIT>RegisterInfo & RegInfo , DenseSet < unsigned int > & UsedRegs ) { if ( MI == MBB . end ( ) ) return Exit ; switch ( MI -> getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { MachineOperand ImmOp = MI -> getOperand ( <STR_LIT> ) ; return ImmOp . getImm ( ) == <NUM_LIT> ? Convert : Exit ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { MachineOperand ImmOp = MI -> getOperand ( <STR_LIT> ) ; return ImmOp . getImm ( ) == - <NUM_LIT> ? Convert : Exit ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return


<s> int64_t CarryInVal = MI . getOpcode ( ) == <STR_LIT> ? <NUM_LIT> : - <NUM_LIT> ; bool Success ; MachineInstr * Load ; Register LHS ; MachineOperand Addr = MachineOperand :: CreateReg ( <NUM_LIT> , false ) ; unsigned Opcode ; if ( MI . getOpcode ( ) == <STR_LIT> ) { Success = mi_match ( Dst , MRI , m_GAdd ( m_Reg ( LHS ) , m_all_of ( m_MInstr ( Load ) , m_FoldedLdAbs ( MI , Addr , AA ) ) ) ) ; Opcode = <STR_LIT> ; } else { Success = mi_match ( Dst , MRI , m_GSub ( m_Reg ( LHS ) , m_all_of ( m_MInstr ( Load ) , m_FoldedLdAbs ( MI , Addr , AA ) ) ) ) ; Opcode = <STR_LIT> ; } if ( Success ) { Register CIn = Builder . buildInstr ( <STR_LIT> , { S1 } , { CarryInVal } ) . getReg ( <NUM_LIT> ) ; auto Instr = Builder . buildInstr ( Opcode ) . addDef ( Dst ) . addDef ( MRI . createGenericVirtualRegister ( S1 ) ) . addDef ( MRI . createGenericVirtualRegister ( S1 ) ) . addUse ( LHS ) . add ( Addr ) . addUse ( CIn ) . cloneMemRefs ( * Load ) ; if ( ! constrainSelectedInstRegOperands ( * Instr , TII , TRI , RBI ) ) llvm_unreachable ( <STR_LIT> ) ; MI . eraseFromParent ( ) ; return true ; } Register Idx ; if ( MI . getOpcode ( ) == <STR_LIT> ) { Success = mi_match ( Dst , MRI , m_GAdd ( m_Reg ( LHS ) , m_all_of ( m_MInstr ( Load ) , m_FoldedLdIdx ( MI , Addr , Idx , AA ) ) ) ) ; Opcode = <STR_LIT> ; } else { Success = mi_match ( Dst , MRI , m_GSub ( m_Reg ( LHS ) , m_all_of ( m_MInstr ( Load ) , m_FoldedLdIdx ( MI , Addr , Idx , AA ) ) ) ) ; Opcode = <STR_LIT> ; } if ( Success ) { Register CIn = Builder . buildInstr ( <STR_LIT> , { S1 } , { CarryInVal } ) . getReg ( <NUM_LIT> ) ; auto Instr = Builder . buildInstr ( Opcode ) . addDef ( Dst ) . addDef ( MRI . createGenericVirtualRegister ( S1 ) ) . addDef ( MRI . createGenericVirtualRegister ( S1 ) ) . addUse ( LHS ) . add ( Addr ) . addUse ( Idx ) . addUse ( CIn ) . cloneMemRefs ( * Load ) ; if ( ! constrainSelectedInstRegOperands ( * Instr , TII , TRI , RBI ) ) llvm_unreachable ( <STR_LIT> ) ; MI . eraseFromParent ( ) ; return true ; } Register IndirAddr


<s> BuildMI ( MBB , InsertBefore , DL , TII -> get ( TargetOpcode :: IMPLICIT_DEF )


<s> const <ISA_LIT>TargetObjectFile * TLOF = static_cast < const <ISA_LIT>TargetObjectFile * > ( getTargetMachine ( ) . getObjFileLowering ( ) ) ; const GlobalObject * GO = GV -> getBaseObject ( ) ; if ( GO && TLOF -> IsGlobalInSmallSection ( GO , getTargetMachine ( ) ) ) return getAddrGPRel ( N , SDLoc ( N ) , Ty , DAG ) ; return getAddrNonPIC ( N , SDLoc ( N ) , Ty , DAG ) ; } if ( GV -> hasLocalLinkage ( ) ) return getAddrLocal ( N , SDLoc ( N ) , Ty , DAG , ABI . IsN32 ( ) || ABI . IsN64 ( ) ) ; if ( LargeGOT ) return getAddrGlobalLargeGOT ( N , SDLoc ( N ) , Ty , DAG , <STR_LIT> , <STR_LIT> , DAG . getEntryNode ( ) , MachinePointerInfo :: getGOT ( DAG . getMachineFunction ( ) ) ) ; return getAddrGlobal ( N , SDLoc ( N ) , Ty , DAG , ( ABI . IsN32 ( ) || ABI . IsN64 ( )

) ? <STR_LIT> : <STR_LIT> , DAG . getEntryNode ( ) , MachinePointerInfo :: getGOT ( DAG . getMachineFunction ( ) ) ) ;


<s> return __builtin_aarch64_ld1v4si ( ( const __builtin_aarch64_simd_si *


<s> EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( ( VT != <STR_LIT> && VT != <STR_LIT> ) || ! ( Divisor . isPowerOf2 ( ) || ( - Divisor ) . isPowerOf2 ( ) ) ) return SDValue ( ) ; SDLoc DL ( N ) ; SDValue N0 = N -> getOperand ( <NUM_LIT> ) ; unsigned Lg2 = Divisor . countTrailingZeros ( ) ; SDValue Zero = DAG . getConstant ( <NUM_LIT> , DL , VT ) ; SDValue Pow2MinusOne = DAG . getConstant ( ( <NUM_LIT> << Lg2 ) - <NUM_LIT> , DL , VT ) ; SDValue CCVal ; SDValue Cmp = get<ISA_LIT>Cmp ( N0 , Zero , <STR_LIT> ,


<s> void setReg ( unsigned Reg ) { assert ( isRegBase ( ) && <STR_LIT> ) ; assert ( ! IsBaseSet &&


<s> return ( vector signed short ) __builtin_altivec_vpkpx ( ( vector signed int


<s> unsigned tmp = ( Val & ~ <NUM_LIT> ) | ( I1 << <NUM_LIT> ) | ( I2 << <NUM_LIT> ) ; int imm32 = SignExtend32 < <NUM_LIT> > ( tmp << <NUM_LIT> ) ; if ( ! tryAddingSymbolicOperand ( Address , Address + imm32 + <NUM_LIT> , true , <NUM_LIT> , Inst , Decoder ) ) Inst . addOperand ( MCOperand :: CreateImm ( imm32 ) ) ; return MCDisassembler ::


<s> return GET_CODE ( x ) == REG && INT_REG_OK_FOR_BASE_P (


<s> const SDLoc & dl ( Op ) ; auto * LoadN = cast < LoadSDNode > ( Op . getNode ( ) ) ; assert ( LoadN -> isUnindexed ( ) && <STR_LIT> ) ; assert ( LoadN -> getMemoryVT ( ) . getVectorElementType ( ) != <STR_LIT> && <STR_LIT> ) ; SDValue Chain = LoadN -> getChain ( ) ; SDValue Base = LoadN -> getBasePtr ( ) ; SDValue Offset = DAG . getUNDEF ( <STR_LIT> ) ; MVT ResTy = ty ( Op ) ; unsigned HwLen = Subtarget . getVectorLength ( ) ; unsigned ResLen = ResTy . getStoreSize ( ) ; assert ( ResLen < HwLen && <STR_LIT> ) ; MVT BoolTy = <STR_LIT> ( <STR_LIT> , HwLen ) ; SDValue Mask = getInstr ( <STR_LIT> , dl , BoolTy , { DAG . getConstant ( ResLen , dl , <STR_LIT> ) } , DAG ) ; MVT LoadTy = <STR_LIT> ( <STR_LIT> , HwLen ) ; MachineFunction & MF = DAG . getMachineFunction ( ) ; auto * MemOp = MF . getMachineMemOperand ( LoadN -> getMemOperand ( ) , <NUM_LIT> , HwLen ) ; SDValue Load = DAG . getMaskedLoad ( LoadTy , dl , Chain , Base , Offset , Mask , DAG . getUNDEF ( LoadTy ) , LoadTy , MemOp , <STR_LIT> , <STR_LIT> , false ) ; SDValue Value = opCastElem ( Load , ResTy .


<s> { MO_ABSOLUTE_ADDRESS , <STR_LIT> } , { MO_PC_RELATIVE_ADDRESS , <STR_LIT> } , { MO_GOT , <STR_LIT> } , { MO_GOTOFF , <STR_LIT> } , { MO_GOTPCREL , <STR_LIT> } , { MO_PLT , <STR_LIT> } } ; return makeArrayRef ( TargetFlags


<s> while ( j <= LAST_ARM_REGNUM ) if ( saved_regs_mask & ( <NUM_LIT> << j ) ) { if ( ( j % <NUM_LIT> == <NUM_LIT> ) && ( saved_regs_mask & ( <NUM_LIT> << ( j + <NUM_LIT> ) ) ) ) { if ( offset < <NUM_LIT> ) { tmp = plus_constant ( Pmode , stack_pointer_rtx , offset ) ; tmp = gen_rtx_PRE_MODIFY ( Pmode , stack_pointer_rtx , tmp ) ; mem = gen_frame_mem ( DImode , tmp ) ; offset = <NUM_LIT> ; } else if ( offset > <NUM_LIT> ) mem = gen_frame_mem ( DImode , plus_constant ( Pmode , stack_pointer_rtx , offset ) ) ; else mem = gen_frame_mem ( DImode , stack_pointer_rtx ) ; tmp = gen_rtx_SET ( DImode , mem , gen_rtx_REG ( DImode , j ) ) ; RTX_FRAME_RELATED_P ( tmp ) = <NUM_LIT> ; tmp = emit_insn ( tmp ) ; if ( dwarf_index == <NUM_LIT> ) insn = tmp ; mem = gen_frame_mem ( SImode , plus_constant ( Pmode , stack_pointer_rtx , offset ) ) ; tmp = gen_rtx_SET ( SImode , mem , gen_rtx_REG ( SImode , j ) ) ; RTX_FRAME_RELATED_P ( tmp ) = <NUM_LIT> ; XVECEXP ( dwarf , <NUM_LIT> , dwarf_index ++ ) = tmp ; mem = gen_frame_mem ( SImode , plus_constant ( Pmode , stack_pointer_rtx , offset + <NUM_LIT> ) ) ; tmp = gen_rtx_SET ( SImode , mem , gen_rtx_REG ( SImode , j + <NUM_LIT> ) ) ; RTX_FRAME_RELATED_P ( tmp ) = <NUM_LIT> ; XVECEXP ( dwarf , <NUM_LIT> , dwarf_index ++ ) = tmp ; offset += <NUM_LIT> ; j += <NUM_LIT> ; } else { if ( offset < <NUM_LIT> ) { tmp = plus_constant ( Pmode , stack_pointer_rtx , offset ) ; tmp = gen_rtx_PRE_MODIFY ( Pmode , stack_pointer_rtx , tmp ) ; mem = gen_frame_mem ( SImode , tmp ) ; offset = <NUM_LIT> ; } else if ( offset > <NUM_LIT> ) mem = gen_frame_mem ( SImode , plus_constant ( Pmode , stack_pointer_rtx , offset ) ) ; else mem = gen_frame_mem ( SImode , stack_pointer_rtx ) ; tmp = gen_rtx_SET ( SImode , mem , gen_rtx_REG ( SImode , j ) ) ; RTX_FRAME_RELATED_P ( tmp ) = <NUM_LIT> ; tmp = emit_insn ( tmp ) ; if ( dwarf_index == <NUM_LIT> ) insn = tmp ; mem = gen_frame_mem ( SImode , plus_constant ( Pmode , stack_pointer_rtx , offset ) ) ; tmp = gen_rtx_SET ( SImode , mem , gen_rtx_REG ( SImode , j ) ) ; RTX_FRAME_RELATED_P ( tmp ) = <NUM_LIT> ; XVECEXP ( dwarf , <NUM_LIT> , dwarf_index ++ ) = tmp ; offset += <NUM_LIT> ; j += <NUM_LIT> ; } } else j ++ ; gcc_assert ( insn != NULL_RTX


<s> if ( N -> getOpcode ( ) != <STR_LIT> && N -> getOpcode ( ) != <STR_LIT> && N -> getOpcode ( ) != <STR_LIT> ) return ; if ( N -> getOperand ( <NUM_LIT> ) . getValueType ( ) != <STR_LIT> ) return ; if ( ! N -> hasOneUse ( ) ) return ; SDLoc dl ( N ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; SDValue Cond = N -> getOperand ( <NUM_LIT> ) ; SDValue ConstTrue = CurDAG -> getConstant ( N -> getOpcode ( ) == <STR_LIT> ? - <NUM_LIT> : <NUM_LIT> , dl , VT ) ; SDValue ConstFalse = CurDAG -> getConstant ( <NUM_LIT> , dl , VT ) ; do { SDNode * User = * N -> use_begin ( ) ; if ( User -> getNumOperands ( ) != <NUM_LIT> ) break ; auto TryFold = [ this , N , User , dl ] ( SDValue Val ) { SDValue UserO0 = User -> getOperand ( <NUM_LIT> ) , UserO1 = User -> getOperand ( <NUM_LIT> ) ; SDValue O0 = UserO0 . getNode ( ) == N ? Val : UserO0 ; SDValue O1 = UserO1 . getNode ( ) == N ? Val : UserO1 ; return CurDAG -> FoldConstantArithmetic ( User -> getOpcode ( ) , dl , User -> getValueType ( <NUM_LIT> ) , { O0 , O1 } ) ; } ; SDValue TrueRes = TryFold ( ConstTrue ) ; if ( ! TrueRes || TrueRes . isUndef ( ) ) break ; SDValue FalseRes = TryFold ( ConstFalse ) ; if ( ! FalseRes || FalseRes . isUndef ( ) ) break ; uint64_t True = cast < ConstantSDNode > ( TrueRes ) -> getZExtValue ( ) , False = cast < ConstantSDNode > ( FalseRes )


<s> MinInstAlignment = <NUM_LIT> ; CommentString = <STR_LIT> ; ZeroDirective = <STR_LIT> ; Data64bitsDirective = <STR_LIT> ; UsesELFSectionDirectiveForBSS = true ; SupportsDebugInformation =


<s> NumBytes = alignTo ( NumBytes , MFI . getMaxAlign ( ) ) ; MFI . setStackSize ( NumBytes ) ; emitPrologueInsns ( MF , MBB , MBBI , NumBytes , true ) ; if ( ! FuncInfo -> isLeafProc ( ) ) BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ; MaybeAlign RuntimeAlign = NeedsStackRealignment ? MaybeAlign ( MFI . getMaxAlign ( ) ) : None ; assert ( ( RuntimeAlign == None || ! FuncInfo -> isLeafProc ( ) ) && <STR_LIT> ) ; emitSPAdjustment ( MF , MBB , MBBI , - ( int64_t ) NumBytes , RuntimeAlign ) ; if ( hasBP ( MF


<s> case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; } } MIB = BuildMI ( * I -> getParent ( ) , I , I -> getDebugLoc ( ) , get ( NewOpc ) ) ; if ( NewOpc == <STR_LIT> || NewOpc == <STR_LIT> || NewOpc == <STR_LIT> || NewOpc == <STR_LIT> ) { if ( NewOpc == <STR_LIT> || NewOpc == <STR_LIT> ) MIB -> RemoveOperand ( <NUM_LIT> ) ; for ( unsigned J = <NUM_LIT> , E = I -> getDesc ( ) . getNumOperands ( ) ; J < E ; ++ J ) { MIB . addOperand ( I -> getOperand ( J ) ) ; } MIB . addImm


<s> void <ISA_LIT>InstPrinter :: printLiteral ( const MCInst * MI , unsigned OpNo , raw_ostream & O ) { int32_t Imm = MI -> getOperand ( OpNo ) . getImm (


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return


<s> return MEMMODEL_SEQ_CST ; } strong = ( is_mm_acq_rel ( model ) || is_mm_seq_cst ( model ) ) ; if ( val & IX86_HLE_ACQUIRE && ! ( is_mm_acquire ( model ) || strong ) ) { warning ( OPT_Winvalid_memory_model , <STR_LIT> ) ; return MEMMODEL_SEQ_CST | IX86_HLE_ACQUIRE ; } if ( val & IX86_HLE_RELEASE && ! ( is_mm_release ( model ) || strong ) ) { warning ( OPT_Winvalid_memory_model , <STR_LIT>


<s> addPass ( create<ISA_LIT>ProtectJTSupport ( )


<s> } if ( ! CountedExitBlock ) return MadeChange ; BasicBlock * Preheader = L -> getLoopPreheader ( ) ; if ( ! Preheader || mightUseCTR ( TT , Preheader ) ) Preheader = InsertPreheaderForLoop ( L , this ) ; if ( ! Preheader ) return MadeChange ; DEBUG ( dbgs ( ) << <STR_LIT> << Preheader -> getName ( ) << <STR_LIT> ) ; MadeChange = true ; SCEVExpander SCEVE ( * SE , <STR_LIT> ) ; LLVMContext & C = SE -> getContext ( ) ; Type * CountType = TT . isArch64Bit ( ) ? Type :: getInt64Ty ( C ) : Type :: getInt32Ty ( C ) ; if ( ! ExitCount -> getType ( ) -> isPointerTy ( ) && ExitCount -> getType ( ) != CountType ) ExitCount = SE -> getZeroExtendExpr ( ExitCount , CountType ) ; ExitCount = SE -> getAddExpr ( ExitCount , SE -> getConstant ( CountType , <NUM_LIT> ) ) ; Value * ECValue = SCEVE . expandCodeFor ( ExitCount , CountType , Preheader -> getTerminator ( ) ) ; IRBuilder < > CountBuilder ( Preheader -> getTerminator ( ) ) ; Module * M = Preheader -> getParent ( ) -> getParent ( ) ; Value * MTCTRFunc = <STR_LIT> ( M , <STR_LIT> , CountType ) ; CountBuilder . CreateCall ( MTCTRFunc , ECValue ) ; IRBuilder < > CondBuilder ( CountedExitBranch ) ; Value * DecFunc = <STR_LIT> ( M , <STR_LIT> ) ; Value * NewCond = CondBuilder . CreateCall


<s> MCAsmParser & Parser = getParser ( ) ; const AsmToken & HashTok = Parser . getTok ( ) ; if ( HashTok . isNot ( AsmToken :: Hash ) ) return MatchOperand_NoMatch ; Parser . Lex ( ) ; const SMLoc S = getLoc ( ) ; const AsmToken & FPImmTok = Parser . getTok ( ) ; if ( FPImmTok . isNot ( AsmToken :: Real ) ) return MatchOperand_NoMatch ; bool Valid ; unsigned ValID = MapperClass ( ) . fromString ( FPImmTok . getString ( ) , getSTI ( ) . getFeatureBits ( ) , Valid ) ; if ( ! Valid ) { Error ( S , <STR_LIT> ) ; return MatchOperand_ParseFail


<s> bool <ISA_LIT>TTIImpl :: expandMemCmp ( Instruction * I , unsigned & MaxLoadSize ) { MaxLoadSize = ST -> is64Bit ( ) ? <NUM_LIT> : <NUM_LIT> ; return true


<s> unsigned LoadOpcode , StoreOpcode ; TII . getLoadStoreOpcodes ( RC , LoadOpcode , StoreOpcode ) ; BuildMI ( MBB , SaveMBBI , DL , TII . get ( StoreOpcode ) ) . addReg ( Reg , RegState :: Kill ) . addReg ( Base ) . addImm ( Offset ) . addReg ( <NUM_LIT> ) ; BuildMI ( MBB , UseMBBI , DL , TII . get ( LoadOpcode ) , Reg ) . addReg ( Base


<s> OperandMatchResultTy parseGRH32 ( SmallVectorImpl < MCParsedAsmOperand * > &


<s> else if ( RC == & <STR_LIT> || <STR_LIT> . contains ( DestReg ) ) { BuildMI ( MBB , MI , dl , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FrameIndex ) . addImm ( <NUM_LIT> ) ; } else llvm_unreachable (


<s> const TargetRegisterClass * VRC = MRI . getRegClass ( SrcReg ) ; const TargetRegisterClass * SRC = RI . getEquivalentSGPRClass ( VRC ) ; unsigned DstReg = MRI . createVirtualRegister ( SRC ) ; unsigned SubRegs = VRC -> getSize ( ) / <NUM_LIT> ; SmallVector < unsigned , <NUM_LIT> > SRegs ; for ( unsigned i = <NUM_LIT> ; i < SubRegs ; ++ i ) { unsigned SGPR = MRI . createVirtualRegister ( &


<s> fatal_error ( input_location , <STR_LIT> , <STR_LIT> ) ; return X_NODEVLIB ; case <NUM_LIT> : if ( strcmp ( <STR_LIT> , argv [ <NUM_LIT> ] ) == <NUM_LIT> ) { return X_NODEVLIB ; } mmcu = AVR_MMCU_DEFAULT ; break ; default : mmcu = argv [ <NUM_LIT> ] ; for ( int i = <NUM_LIT> ; i < argc ; i ++ ) if ( strcmp ( mmcu , argv [ i ] ) != <NUM_LIT> ) { error ( <STR_LIT> , <STR_LIT> ) ; return X_NODEVLIB


<s> case ACCESS_REGS : reg_size = <NUM_LIT> ; break ; default : reg_size = UNITS_PER_WORD ; break ; } if ( reg_pair_required_p ) return <NUM_LIT> * ( ( GET_MODE_SIZE ( mode ) /


<s> MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , decodeRn ( insn ) ) ) ) ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , decodeRm ( insn ) ) ) ) ; if ( FourReg ) MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , decodeRd ( insn ) )


<s> bool <ISA_LIT>RegisterInfo :: requiresRegisterScavenging ( const MachineFunction


<s> Ptr1Reg = ptrB ; } BuildMI ( BB , dl , TII -> get ( <STR_LIT> ) , Shift1Reg ) . addReg ( Ptr1Reg ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( is8bit ? <NUM_LIT> : <NUM_LIT> ) ; BuildMI ( BB , dl , TII -> get ( is64bit ? <STR_LIT> : <STR_LIT> ) , ShiftReg ) . addReg ( Shift1Reg ) . addImm ( is8bit ? <NUM_LIT> : <NUM_LIT> ) ; if ( is64bit ) BuildMI ( BB , dl , TII -> get ( <STR_LIT> ) , PtrReg ) . addReg ( Ptr1Reg ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; else BuildMI ( BB , dl , TII -> get ( <STR_LIT> ) , PtrReg ) . addReg ( Ptr1Reg ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; BuildMI ( BB , dl , TII -> get ( <STR_LIT> ) , Incr2Reg ) . addReg ( incr ) . addReg ( ShiftReg ) ; if ( is8bit ) BuildMI ( BB , dl , TII -> get ( <STR_LIT> ) , Mask2Reg ) . addImm ( <NUM_LIT> ) ; else { BuildMI ( BB , dl , TII -> get ( <STR_LIT> ) , Mask3Reg ) . addImm ( <NUM_LIT> ) ; BuildMI ( BB , dl , TII -> get ( <STR_LIT> ) , Mask2Reg ) . addReg ( Mask3Reg ) . addImm ( <NUM_LIT> ) ; } BuildMI ( BB , dl , TII -> get ( <STR_LIT> ) , MaskReg ) . addReg ( Mask2Reg ) . addReg ( ShiftReg ) ; BB = loopMBB ; BuildMI ( BB , dl , TII -> get ( <STR_LIT> ) , TmpDestReg ) . addReg ( ZeroReg ) . addReg ( PtrReg ) ; if ( BinOpcode ) BuildMI ( BB , dl , TII -> get ( BinOpcode ) , TmpReg ) . addReg ( Incr2Reg ) . addReg ( TmpDestReg ) ; BuildMI ( BB , dl , TII -> get ( is64bit ? <STR_LIT> : <STR_LIT> ) , Tmp2Reg ) . addReg ( TmpDestReg )