<s> const MachineFunction & MF = * MBB . getParent ( ) ; unsigned Opc = STI . is64Bit ( ) ? <STR_LIT> : <STR_LIT> ; for ( const CalleeSavedInfo & I : llvm :: reverse ( CSI ) ) { unsigned Reg = I . getReg ( ) ; if ( ! <STR_LIT> . contains ( Reg ) && ! <STR_LIT> . contains ( Reg ) ) continue ; const MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; bool isLiveIn = MRI . isLiveIn ( Reg ) ; if ( ! isLiveIn ) MBB . addLiveIn ( Reg ) ; bool CanKill = ! isLiveIn ; if ( CanKill ) { for ( MCRegAliasIterator AReg ( Reg , TRI , false ) ; AReg . isValid ( ) ; ++ AReg ) { if ( MRI . isLiveIn ( * AReg ) ) { CanKill = false ; break ; } } } BuildMI ( MBB , MI , DL , TII . get ( Opc ) ) . addReg ( Reg , getKillRegState ( CanKill ) ) . setMIFlag ( MachineInstr :: FrameSetup ) ; } for ( const CalleeSavedInfo & I : llvm :: reverse ( CSI ) ) { unsigned Reg = I . getReg ( ) ; if ( <STR_LIT> . contains ( Reg ) || <STR_LIT> . contains ( Reg ) ) continue ; MVT VT = <STR_LIT> ; if ( <STR_LIT> . contains ( Reg ) ) VT =

STI . hasBWI ( ) ? <STR_LIT> : <STR_LIT> ;


<s> switch ( TheTriple . getObjectFormat ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case Triple :: MachO : { MachO :: CPUSubType<ISA_LIT> CS = StringSwitch < MachO :: CPUSubType<ISA_LIT> > ( TheTriple . getArchName ( ) ) . Cases ( <STR_LIT> , <STR_LIT> , MachO :: CPU_SUBTYPE_<ISA_LIT>_V4T ) . Cases ( <STR_LIT> , <STR_LIT> , MachO :: CPU_SUBTYPE_<ISA_LIT>_V5TEJ ) . Cases ( <STR_LIT> , <STR_LIT> , MachO :: CPU_SUBTYPE_<ISA_LIT>_V6 ) . Cases ( <STR_LIT> , <STR_LIT> , MachO :: CPU_SUBTYPE_<ISA_LIT>_V6M ) . Cases ( <STR_LIT> , <STR_LIT> , MachO :: CPU_SUBTYPE_<ISA_LIT>_V7EM ) . Cases ( <STR_LIT> , <STR_LIT> , MachO :: CPU_SUBTYPE_<ISA_LIT>_V7K ) . Cases ( <STR_LIT> , <STR_LIT> , MachO :: CPU_SUBTYPE_<ISA_LIT>_V7M ) . Cases ( <STR_LIT> , <STR_LIT> , MachO :: CPU_SUBTYPE_<ISA_LIT>_V7S ) . Default ( MachO :: CPU_SUBTYPE_<ISA_LIT>_V7 ) ; return new <ISA_LIT>AsmBackendDarwin ( T , TT , CS ) ; } case Triple :: COFF : assert ( TheTriple . isOSWindows ( ) && <STR_LIT> ) ; return new <ISA_LIT>AsmBackendWinCOFF ( T , TT ) ; case Triple :: ELF : assert ( TheTriple . isOSBinFormatELF ( ) && <STR_LIT> ) ; uint8_t OSABI = MCELFObjectTargetWriter :: getOSABI ( Triple ( TT ) . getOS ( ) ) ; if ( TheTriple . isOSNaCl ( ) ) return new <ISA_LIT>AsmBackendNaClELF (


<s> static void DecodeSymbolicOperandOff ( MCInst & Inst , uint64_t Address , uint64_t


<s> Results . push ( TargetOpcode :: REG_SEQUENCE , getPairVT ( <STR_LIT> ) , { DAG . getTargetConstant ( <STR_LIT> , dl , <STR_LIT> ) , Lo , DAG . getTargetConstant ( <STR_LIT> , dl , <STR_LIT> ) , Hi , DAG . getTargetConstant ( <STR_LIT>


<s> unsigned ImmShift = get<ISA_LIT>ImmediateShift ( MID . TSFlags ) ; O << ( Op . getImm ( ) << ImmShift ) ; } else { O << Op . getImm ( ) ; } return ; } assert ( Op . isExpr (


<s> op [ nopnds ] = expand_normal ( arg ) ; if ( ! ( * insn_op -> predicate ) ( op [ nopnds ] , insn_op -> mode ) ) { if ( ! strcmp ( insn_op -> constraint , <STR_LIT> ) ) { int arg_num = ( nonvoid ) ? nopnds : nopnds + <NUM_LIT> ; if ( ! CONST_INT_P ( op [ nopnds ] ) ) error ( <STR_LIT> , arg_num ) ; else error ( <STR_LIT> <STR_LIT> , arg_num ) ; return const0_rtx ; } op [ nopnds ] = copy_to_mode_reg ( insn_op -> mode , op [ nopnds ] ) ; } nopnds ++


<s> bool fixupNeedsRelaxation ( const MCFixup & Fixup , uint64_t Value , const MCRelaxableFragment * DF , const MCAsmLayout & Layout ) const override { return false


<s> unsigned SecondReg = Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned ThirdReg = Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( has<ISA_LIT>1 ( ) && ! has<ISA_LIT>2 ( ) ) { unsigned ATReg = getATReg ( IDLoc ) ; if ( ! ATReg ) return true ; emitRR ( <STR_LIT> , ThirdReg , <STR_LIT> , IDLoc , Instructions ) ; emitRR ( <STR_LIT> , ThirdReg , <STR_LIT> , IDLoc , Instructions ) ; createNop ( false , IDLoc , Instructions ) ; emitRRI ( <STR_LIT> , ATReg , ThirdReg , <NUM_LIT> , IDLoc , Instructions ) ; emitRRI ( <STR_LIT> , ATReg , ATReg , <NUM_LIT> , IDLoc , Instructions ) ; emitRR ( <STR_LIT> , <STR_LIT> , ATReg , IDLoc , Instructions ) ; createNop ( false , IDLoc , Instructions ) ; emitRR ( IsDouble ? ( Is64FPU ? <STR_LIT> : <STR_LIT> ) : <STR_LIT> , FirstReg , SecondReg , IDLoc , Instructions ) ; emitRR ( <STR_LIT> , <STR_LIT> , ThirdReg , IDLoc , Instructions ) ; createNop ( false , IDLoc , Instructions ) ; return false ; } emitRR ( IsDouble ? ( Is64FPU ? <STR_LIT> : <STR_LIT> ) : <STR_LIT>


<s> return ( poly64x2_t ) __builtin_neon_vreinterpretv2div8hi (


<s> const <ISA_LIT>TargetLowering * getTargetLowering ( ) const


<s> DenseMap < const AllocaInst * , int > :: iterator SI = FuncInfo . StaticAllocaMap . find ( AI ) ; if ( SI != FuncInfo . StaticAllocaMap . end ( ) ) { unsigned ResultReg = createResultReg ( Subtarget -> hasAddr64 ( ) ? & <STR_LIT> : & <STR_LIT>


<s> unsigned HOST_WIDE_INT shift_mask = ~ ( unsigned HOST_WIDE_INT ) <NUM_LIT> ; shift_mask <<= INTVAL


<s> const LLT v8s32 = LLT :: vector ( <NUM_LIT> , <NUM_LIT> ) ; const LLT v16s32 = LLT :: vector ( <NUM_LIT> , <NUM_LIT> ) ; const LLT v4s64 = LLT :: vector ( <NUM_LIT> , <NUM_LIT> ) ; const LLT v8s64 = LLT :: vector ( <NUM_LIT> , <NUM_LIT> ) ; for ( unsigned MemOp : { G_LOAD , G_STORE } ) for ( auto Ty : { v8s32 , v4s64 } ) setAction ( { MemOp , Ty } , Legal ) ; for ( auto Ty : { v32s8 , v16s16 , v8s32 , v4s64 } ) { setAction ( { G_INSERT , Ty } , Legal ) ; setAction ( { G_EXTRACT , <NUM_LIT> , Ty } , Legal


<s> if ( Hi == <NUM_LIT> || Hi == <NUM_LIT> ) P += <NUM_LIT> , HiZ1 = true ; if ( ! LoZ1 && ! HiZ1 && Lo == Hi ) P += <NUM_LIT> ; return P


<s> void encodeInstruction ( const MCInst & MI , raw_ostream & OS , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const override { verifyInstructionPredicates ( MI , computeAvailableFeatures ( STI . getFeatureBits ( ) ) ) ; unsigned Opcode = MI . getOpcode ( ) ; const MCInstrDesc & Desc = MCII . get ( Opcode ) ; uint64_t Bits = getBinaryCodeForInstr ( MI , Fixups , STI ) ; unsigned Size = Desc . getSize ( ) ; switch ( Size ) { case <NUM_LIT> : break ; case <NUM_LIT> : if ( IsLittleEndian ) { <STR_LIT> :: Writer < <STR_LIT> > ( OS ) . write < uint32_t > ( Bits ) ; } else { <STR_LIT> :: Writer < <STR_LIT> > ( OS ) . write < uint32_t > ( Bits ) ; } break ; case <NUM_LIT> : if ( IsLittleEndian ) { uint64_t Swapped = ( Bits << <NUM_LIT> ) | ( Bits >> <NUM_LIT> ) ; <STR_LIT> :: Writer < <STR_LIT> > ( OS ) . write < uint64_t > ( Swapped ) ; } else { <STR_LIT> :: Writer < <STR_LIT> > ( OS ) . write < uint64_t > ( Bits ) ; } break ; default : llvm_unreachable ( <STR_LIT> ) ; } ++ MCNumEmitted


<s> bool isDestroy = Opcode == TII . getCallFrameDestroyOpcode ( ) ; bool IsLP64 = STI . isTarget64BitLP64 ( ) ; DebugLoc DL = I -> getDebugLoc ( ) ; uint64_t Amount = ! reserveCallFrame ? I -> getOperand ( <NUM_LIT> ) . getImm ( ) : <NUM_LIT> ; uint64_t InternalAmt = ( isDestroy || Amount ) ? I -> getOperand ( <NUM_LIT> ) . getImm ( ) : <NUM_LIT> ; I = MBB . erase ( I ) ; if ( ! reserveCallFrame ) { if ( Amount == <NUM_LIT> ) return ; unsigned StackAlign = STI . getFrameLowering ( ) -> getStackAlignment ( ) ; Amount = ( Amount + StackAlign - <NUM_LIT> ) / StackAlign * StackAlign ; MachineInstr * New = nullptr ; Amount -= InternalAmt ; if ( Amount ) { if ( Opcode == TII . getCallFrameSetupOpcode ( ) ) { New = BuildMI ( MF , DL , TII . get ( getSUBriOpcode ( IsLP64 , Amount ) ) , StackPtr ) . addReg ( StackPtr ) . addImm ( Amount ) ; } else { assert ( Opcode == TII . getCallFrameDestroyOpcode ( ) ) ; unsigned Opc = getADDriOpcode ( IsLP64 , Amount ) ; New = BuildMI ( MF , DL , TII . get ( Opc ) , StackPtr ) . addReg ( StackPtr ) . addImm ( Amount ) ; } } if ( New ) { New -> getOperand ( <NUM_LIT> ) . setIsDead ( ) ; MBB . insert ( I , New ) ; } return ; } if ( Opcode == TII . getCallFrameDestroyOpcode ( ) && InternalAmt ) { unsigned Opc = getSUBriOpcode ( IsLP64 , InternalAmt ) ; MachineInstr * New = BuildMI ( MF , DL , TII . get ( Opc ) , StackPtr ) . addReg ( StackPtr ) . addImm ( InternalAmt ) ; New -> getOperand ( <NUM_LIT> ) . setIsDead ( ) ; MachineBasicBlock :: iterator B = MBB


<s> void printdwordmem ( const MCInst * MI , unsigned OpNo , raw_ostream & O ) { printMemReference ( MI , OpNo ,


<s> if ( PredEventUB > KillWaitBrackets [ I ] -> getScoreLB ( T ) ) { int NewEventUB = MaxPending [ T ] + PredEventUB - KillWaitBrackets [ I ] -> getScoreUB ( T ) ; if ( NewEventUB > <NUM_LIT>


<s> OutStreamer . emitLabel ( StubLabel ) ; OutStreamer . emitSymbolAttribute ( MCSym . getPointer ( ) , MCSA_IndirectSymbol ) ; if ( MCSym . getInt ( ) ) OutStreamer . emitIntValue ( <NUM_LIT> ,


<s> <STR_LIT> Flags = cast < ARG_FLAGSSDNode > ( Op . getOperand ( <NUM_LIT> + i ) ) -> getArgFlags ( ) ; bool AlwaysUseMutable = ( CC == CallingConv :: Fast ) && PerformTailCallOpt ; bool isImmutable = ! AlwaysUseMutable && ! Flags . isByVal ( ) ; int FI = MFI -> CreateFixedObject ( VA . getValVT ( ) . getSizeInBits ( ) / <NUM_LIT> , VA . getLocMemOffset ( ) , isImmutable ) ; SDValue FIN = DAG . getFrameIndex ( FI , getPointerTy ( ) ) ; if ( Flags . isByVal


<s> assert ( ( VT == <STR_LIT> || VT == <STR_LIT> ) && <STR_LIT> ) ; unsigned NumElts = VT . getVectorNumElements ( ) ; unsigned Mask = <NUM_LIT> ; for ( unsigned l = <NUM_LIT> ; l != NumElts ; l += <NUM_LIT> ) { for ( unsigned i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) { int Elt = N -> getMaskElt ( l + i ) ; if ( Elt < <NUM_LIT> ) continue ; Elt &= <NUM_LIT> ; Mask |= Elt << ( i * <NUM_LIT> ) ; } } return


<s> if ( TARGET_VECTOR ) return riscv_v_ext_vector_mode_p


<s> if ( F != Map . end ( ) ) return F -> second ; return


<s> int MaskSplitCost = getScalarizationOverhead ( MaskTy , false , true ) ; int ScalarCompareCost = getCmpSelInstrCost ( Instruction :: ICmp , Type :: getInt8Ty ( SrcVTy -> getContext ( ) ) , nullptr ) ; int BranchCost = getCFInstrCost ( Instruction :: Br ) ; int MaskCmpCost = NumElem * ( BranchCost + ScalarCompareCost ) ; int ValueSplitCost = getScalarizationOverhead ( SrcVTy , Opcode == Instruction :: Load , Opcode == Instruction :: Store ) ; int MemopCost = NumElem * BaseT :: getMemoryOpCost ( Opcode , SrcVTy -> getScalarType ( ) , Alignment , AddressSpace ) ; return MemopCost + ValueSplitCost + MaskSplitCost + MaskCmpCost ; } std :: pair < int , MVT > LT = TLI -> getTypeLegalizationCost ( DL , SrcVTy ) ; auto VT = TLI -> getValueType ( DL


<s> void <ISA_LIT>InstPrinter :: printUnsignedImmOperand ( const MCInst * MI , unsigned OpNo , raw_ostream & O ) const { O << MI -> getOperand ( OpNo ) . getImm


<s> else if ( real_equal ( & r , & dconst1 ) ) asm_fprintf ( f , <STR_LIT> ) ; else if ( real_equal ( & r , & dconsthalf )


<s> LE . write < uint8_t > ( <NUM_LIT> ) ; LE . write < uint8_t > ( <NUM_LIT> ) ; LE . write < uint16_t > ( <NUM_LIT> ) ; if ( IsLittleEndian ) LE . write < uint32_t > ( Imm >> <NUM_LIT> ) ; else BE . write < uint32_t > ( Imm >> <NUM_LIT> ) ; } else { uint64_t Value = getBinaryCodeForInstr ( MI , Fixups , STI ) ; LE . write < uint8_t > ( Value >> <NUM_LIT> ) ; if ( IsLittleEndian ) { LE . write < uint8_t > ( ( Value >> <NUM_LIT> ) & <NUM_LIT> ) ; LE . write < uint16_t > ( ( Value >> <NUM_LIT> ) & <NUM_LIT> ) ; LE . write < uint32_t > ( Value & <NUM_LIT> ) ; }


<s> S = Parser . getTok ( ) . getLoc ( ) ; Parser . Lex ( ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateToken ( <STR_LIT> , S ) ) ; return false ; } } } case AsmToken :: LParen : case AsmToken :: Integer : case AsmToken :: String : case AsmToken :: Dot : { const MCExpr * IdVal ; S = Parser . getTok ( ) . getLoc ( ) ; if ( getParser ( ) . parseExpression ( IdVal ) ) return true ; E = SMLoc :: getFromPointer ( Parser . getTok ( ) . getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateImm ( IdVal , S , E ) ) ; return false ; } case AsmToken :: LBrac : return parseMemory ( Operands ) ; case AsmToken :: LCurly : return parseRegisterList ( Operands ) ; case AsmToken :: Dollar : case AsmToken :: Hash : { S = Parser . getTok ( ) . getLoc ( ) ; Parser . Lex ( ) ; if ( Parser . getTok ( ) . isNot ( AsmToken :: Colon ) ) { bool isNegative = Parser . getTok ( ) . is ( AsmToken :: Minus ) ; const MCExpr * ImmVal ; if ( getParser ( ) . parseExpression ( ImmVal ) ) return true ; const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( ImmVal ) ; if ( CE ) { int32_t Val = CE -> getValue ( ) ; if ( isNegative && Val == <NUM_LIT> ) ImmVal = MCConstantExpr :: Create ( INT32_MIN , getContext ( ) ) ; } E = SMLoc :: getFromPointer ( Parser . getTok ( ) . getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateImm ( ImmVal , S , E ) ) ; if ( Parser . getTok ( ) . is ( AsmToken :: Exclaim ) ) { Operands . push_back ( <ISA_LIT>Operand :: CreateToken ( Parser . getTok ( ) . getString ( ) , Parser . getTok ( ) . getLoc ( ) ) ) ; Parser . Lex ( ) ; } return false ; } } case AsmToken :: Colon : { <ISA_LIT>MCExpr :: VariantKind RefKind ; if ( parsePrefix ( RefKind ) ) return true ; const MCExpr * SubExprVal ; if ( getParser ( ) . parseExpression ( SubExprVal ) ) return true ; const MCExpr * ExprVal = <ISA_LIT>MCExpr :: Create ( RefKind , SubExprVal , getContext ( ) ) ; E = SMLoc :: getFromPointer ( Parser . getTok ( ) . getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateImm ( ExprVal , S ,


<s> SDValue Assert = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Extract , DAG . getValueType ( VT ) ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Assert ) ; } else if ( VT . getSizeInBits ( ) == <NUM_LIT> ) { unsigned Idx = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; if ( Idx == <NUM_LIT> ) return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) ) , Op . getOperand ( <NUM_LIT> ) ) ) ; SDValue Extract = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; SDValue Assert = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Extract , DAG . getValueType ( VT ) ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Assert ) ; } else if ( VT == <STR_LIT> ) { if ( ! Op . hasOneUse ( ) ) return SDValue ( ) ; SDNode * User = * Op . getNode ( ) -> use_begin ( ) ; if ( ( User -> getOpcode ( ) != <STR_LIT> || ( isa < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) && cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> isNullValue ( ) ) ) && ( User -> getOpcode ( ) != <STR_LIT> || User -> getValueType ( <NUM_LIT> ) != <STR_LIT> ) ) return SDValue ( ) ; SDValue Extract = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) ) , Op . getOperand ( <NUM_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT>


<s> MachineFunction & MF = DAG . getMachineFunction ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; MachineRegisterInfo & RegInfo = MF . getRegInfo ( ) ; SmallVector < CCValAssign , <NUM_LIT> > ArgLocs ; CCState CCInfo ( CallConv , isVarArg , DAG . getMachineFunction ( ) , getTargetMachine ( ) , ArgLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeFormalArguments ( Ins , CC_<ISA_LIT> ) ; if ( isVarArg ) report_fatal_error ( <STR_LIT> ) ; for ( unsigned i = <NUM_LIT> , e = ArgLocs . size ( ) ; i != e ; ++ i ) { SDValue ArgValue ; CCValAssign & VA = ArgLocs [ i ] ; EVT LocVT = VA . getLocVT ( ) ; if ( VA . isRegLoc ( ) ) { TargetRegisterClass * RC ; switch ( LocVT . getSimpleVT


<s> SDValue <ISA_LIT>TargetLowering :: LowerCTPOP ( SDValue Op , SelectionDAG & DAG ) const { SDLoc dl ( Op ) ; SDValue InpVal = Op . getOperand ( <NUM_LIT> ) ; if ( isa < ConstantSDNode >


<s> assert ( Offset < <NUM_LIT> && <STR_LIT> ) ; unsigned OpC = MI -> getOpcode ( ) ; if ( ! ImmToIdxMap . count ( OpC ) ) return false ; if ( ( OpC == <STR_LIT> || OpC == <STR_LIT> ) && MI -> getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) return false ; MachineBasicBlock & MBB = * MI -> getParent ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; const <ISA_LIT>FrameLowering * <ISA_LIT>FI = static_cast < const <ISA_LIT>FrameLowering * > ( MF . getTarget ( )


<s> vld1q_p8 ( const poly8_t * __a ) { return ( poly8x16_t ) __builtin_neon_vld1v16qi ( ( const __builtin_neon_qi * )


<s> case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return


<s> return hash_combine ( DenseMapInfo < int > :: getHashValue ( V . FI ) , DenseMapInfo <


<s> MCInstrInfo * X = new MCInstrInfo ( ) ; Init<ISA_LIT>MCInstrInfo ( X


<s> std :: vector < std :: string > bkrepsto_memsp ( ) { return D ( <STR_LIT> ,


<s> assert ( STI . isTargetLinux ( ) && <STR_LIT> ) ; if ( MFI -> hasCalls ( ) ) { unsigned MoreStackForCalls = <NUM_LIT> ; for ( MachineFunction :: iterator MBBI = MF . begin ( ) , MBBE = MF . end ( ) ; MBBI != MBBE ; ++ MBBI ) for ( MachineBasicBlock :: iterator MI = MBBI -> begin ( ) , ME = MBBI -> end ( ) ; MI != ME ; ++ MI ) { if ( ! MI -> isCall ( ) ) continue ; const MachineOperand & MO = MI -> getOperand ( <NUM_LIT> ) ; if ( ! MO . isGlobal ( ) ) continue ; const Function * F = dyn_cast < Function > ( MO . getGlobal ( ) ) ; if ( ! F ) continue ; if ( F -> getName ( ) . find ( <STR_LIT> ) != StringRef :: npos || F -> getName ( ) . find ( <STR_LIT> ) != StringRef :: npos || F -> getName ( ) . find_first_of ( <STR_LIT> ) == StringRef :: npos ) continue ; unsigned CalleeStkArity = F -> arg_size ( ) > CCRegisteredArgs ? F -> arg_size ( ) - CCRegisteredArgs : <NUM_LIT> ; if ( HipeLeafWords - <NUM_LIT> > CalleeStkArity ) MoreStackForCalls = std :: max ( MoreStackForCalls , ( HipeLeafWords - <NUM_LIT> - CalleeStkArity ) * SlotSize ) ; } MaxStack += MoreStackForCalls ; } if ( MaxStack > Guaranteed ) { MachineBasicBlock * stackCheckMBB = MF . CreateMachineBasicBlock ( ) ; MachineBasicBlock * incStackMBB = MF . CreateMachineBasicBlock ( ) ; for ( unsigned LI : PrologueMBB . liveins ( ) ) { stackCheckMBB -> addLiveIn ( LI


<s> void <ISA_LIT>MCELFStreamer :: <ISA_LIT>MCEmitCommonSymbol ( MCSymbol * Symbol , uint64_t Size , unsigned ByteAlignment , unsigned AccessSize ) { getAssembler ( ) . registerSymbol ( * Symbol ) ; StringRef sbss [ <NUM_LIT> ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; auto ELFSymbol = cast < MCSymbolELF > ( Symbol ) ; if ( ! ELFSymbol -> isBindingSet ( ) ) { ELFSymbol -> setBinding ( ELF :: STB_GLOBAL ) ; ELFSymbol -> setExternal ( true ) ; } ELFSymbol -> setType ( ELF :: STT_OBJECT ) ; if ( ELFSymbol -> getBinding ( ) == ELF :: STB_LOCAL ) { StringRef SectionName = ( ( AccessSize == <NUM_LIT> ) || ( Size == <NUM_LIT> ) || ( Size > GPSize ) ) ? <STR_LIT> : sbss [ ( Log2_64 ( AccessSize ) ) ] ; MCSection & Section = * getAssembler ( ) . getContext ( ) . getELFSection ( SectionName , ELF :: SHT_NOBITS , ELF :: SHF_WRITE | ELF :: SHF_ALLOC ) ; MCSectionSubPair P = getCurrentSection ( ) ; SwitchSection ( & Section


<s> static tree arc_handle_fndecl_attribute ( tree * node , tree name , tree args ATTRIBUTE_UNUSED , int flags ATTRIBUTE_UNUSED , bool * no_add_attrs ) { if ( TREE_CODE ( * node ) != FUNCTION_DECL ) { warning ( OPT_Wattributes , <STR_LIT> ,


<s> const char * Sym = cast < ExternalSymbolSDNode > ( Op ) -> getSymbol ( ) ; auto PtrVT = getPointerTy ( DAG . getDataLayout ( )


<s> SupportsDebugInformation = true ; ExceptionsType = ExceptionHandling :: DwarfCFI ; if ( ( T . getOS ( ) == Triple :: OpenBSD || T . getOS ( ) == Triple ::

Bitrig ) && T . getArch ( ) == Triple :: x86 ) Data64bitsDirective = nullptr ;


<s> unsigned OffBits = getMachineOpValue ( MI , MI . getOperand ( OpNo + <NUM_LIT> ) , Fixups , STI ) >> <NUM_LIT> ; return ( OffBits & <NUM_LIT>


getRegisterName ( RegNo ) << markup ( <STR_LIT> ) ;


<s> Register DstReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; const LLT NarrowTy = MRI . getType ( DstReg ) ; const Register SrcReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; const LLT WideTy = MRI . getType ( SrcReg ) ; ( void ) WideTy ; assert ( WideTy . getSizeInBits ( ) >= NarrowTy . getSizeInBits ( ) && <STR_LIT> ) ; assert ( ! NarrowTy . isVector ( ) && <STR_LIT> ) ; MachineOperand & LaneIdxOp = I . getOperand ( <NUM_LIT> ) ; assert ( LaneIdxOp . isReg ( ) && <STR_LIT> ) ; if ( RBI . getRegBank ( DstReg , MRI , TRI ) -> getID ( ) != <STR_LIT> ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } auto VRegAndVal = getConstantVRegValWithLookThrough ( LaneIdxOp . getReg (


<s> CASE_AARCH64_ATOMIC_ ( LDADDA ) : CASE_AARCH64_ATOMIC_ ( LDADDAL ) : CASE_AARCH64_ATOMIC_ ( LDCLRA ) : CASE_AARCH64_ATOMIC_ ( LDCLRAL ) : CASE_AARCH64_ATOMIC_ ( LDEORA ) : CASE_AARCH64_ATOMIC_ ( LDEORAL ) : CASE_AARCH64_ATOMIC_ ( LDSETA ) : CASE_AARCH64_ATOMIC_ ( LDSETAL ) : CASE_AARCH64_ATOMIC_ ( LDSMAXA ) : CASE_AARCH64_ATOMIC_ ( LDSMAXAL ) : CASE_AARCH64_ATOMIC_ ( LDSMINA ) : CASE_AARCH64_ATOMIC_ ( LDSMINAL ) : CASE_AARCH64_ATOMIC_ ( LDUMAXA ) : CASE_AARCH64_ATOMIC_ ( LDUMAXAL ) : CASE_AARCH64_ATOMIC_ ( LDUMINA ) : CASE_AARCH64_ATOMIC_ ( LDUMINAL ) : CASE_AARCH64_ATOMIC_ ( SWPA ) : CASE_AARCH64_ATOMIC_ ( SWPAL


<s> static parse_codes parse_bif ( void ) { parse_codes result ; diag = & bif_diag ; if ( ! advance_line ( bif_file ) ) return PC_OK ; do result = parse_bif_stanza ( ) ; while ( result == PC_OK ) ; if ( result == PC_EOFILE ) return


<s> LowerToCopyInstrs . clear ( ) ; CallingConv = MF . getFunction ( ) . getCallingConv ( ) ; ST = & MF . getSubtarget < GCNSubtarget > ( ) ; TII = ST -> getInstrInfo ( ) ; TRI = & TII -> getRegisterInfo ( ) ; MRI = & MF . getRegInfo ( ) ; LIS = & getAnalysis < LiveIntervals > ( ) ; char GlobalFlags = analyzeFunction ( MF ) ; unsigned LiveMaskReg = <NUM_LIT> ; unsigned Exec = ST -> isWave32 ( ) ? <STR_LIT> : <STR_LIT> ; if ( ! ( GlobalFlags & StateWQM ) ) { lowerLiveMaskQueries ( Exec ) ; if ( ! ( GlobalFlags & StateWWM ) && LowerToCopyInstrs . empty ( ) ) return ! LiveMaskQueries .


<s> MachineBasicBlock :: iterator <ISA_LIT>FrameLowering :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { unsigned SP = STI . getABI ( ) . IsN64 ( ) ? <STR_LIT> : <STR_LIT> ; if ( ! hasReservedCallFrame ( MF ) ) { int64_t Amount = I -> getOperand ( <NUM_LIT>


<s> if ( ! mips_tls_symbol ) mips_tls_symbol = init_one_libfunc ( <STR_LIT> ) ; loc = mips_unspec_address ( sym , type ) ; start_sequence ( ) ; emit_insn ( gen_rtx_SET ( a0 , gen_rtx_LO_SUM ( Pmode , pic_offset_table_rtx , loc ) ) ) ; insn = mips_expand_call ( MIPS_CALL_NORMAL , v0 , mips_tls_symbol , const0_rtx , NULL_RTX , false ) ; RTL_CONST_CALL_P ( insn ) = <NUM_LIT> ; use_reg ( & CALL_INSN_FUNCTION_USAGE ( insn ) , a0


<s> if ( PAN :: isLocalToFunc ( FnName , VarName ) ) { const GlobalVariable * GV = I ; const Type * InitTy = GV -> getInitializer ( ) -> getType ( ) ; GlobalVariable * ClonedGV = new GlobalVariable ( InitTy , false , GV -> getLinkage ( ) , GV -> getInitializer ( ) ) ; ClonedGV -> setName ( PAN :: getCloneVarName ( FnName , VarName ) ) ; Globals . push_back (


<s> case GlobalValue :: InternalLinkage : case GlobalValue :: PrivateLinkage : break ; case GlobalValue :: DLLImportLinkage : llvm_unreachable ( <STR_LIT> ) ; case GlobalValue :: DLLExportLinkage : llvm_unreachable ( <STR_LIT> ) ; default : llvm_unreachable ( <STR_LIT> ) ; } EmitAlignment ( Align > <NUM_LIT> ? Align : <NUM_LIT> , GV ) ; if ( GV -> isThreadLocal ( ) ) { report_fatal_error ( <STR_LIT> ) ; } unsigned Size = TD -> getTypeAllocSize ( C -> getType ( ) ) ; if ( MAI -> hasDotTypeDotSizeDirective ( ) ) { OutStreamer . EmitSymbolAttribute ( GVSym , MCSA_ELF_TypeObject ) ; OutStreamer . EmitRawText ( <STR_LIT> + Twine ( GVSym -> getName ( ) ) + <STR_LIT> + Twine ( Size ) ) ; } OutStreamer . EmitLabel ( GVSym ) ; EmitGlobalConstant ( C ) ; if ( Size < <NUM_LIT> ) OutStreamer . EmitZeros ( <NUM_LIT> - Size ) ; OutStreamer . EmitRawText ( <STR_LIT> + Twine ( GVSym -> getName (


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; uint64_t Imm = getConstantImm ( ) - Offset ; Imm &= ( <NUM_LIT> << Bits )


<s> CCInfo . AnalyzeReturn ( Outs , RetCC_<ISA_LIT> ) ; if ( DAG . getMachineFunction ( ) . getRegInfo ( ) . liveout_empty ( ) ) { for ( unsigned i = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i ) if ( RVLocs [ i ] . isRegLoc ( ) ) DAG . getMachineFunction ( ) . getRegInfo ( ) . addLiveOut ( RVLocs [ i ] . getLocReg ( ) ) ; } SDValue Flag ; for ( unsigned i = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i ) { CCValAssign & VA = RVLocs [ i ] ; assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; Chain = DAG . getCopyToReg ( Chain , dl , VA . getLocReg ( ) , Outs [ i ] . Val , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; } if ( DAG . getMachineFunction ( ) . getFunction ( ) -> hasStructRetAttr


<s> bool isToken ( ) const override { return Kind == KindTy ::


<s> return ( ( split_type != SPLIT_FOR_SPEED || mips_tuning_info . fast_mult_zero_zero_p ) && src == const0_rtx && REG_P ( dest ) && GET_MODE_SIZE ( GET_MODE ( dest ) ) == <NUM_LIT> * UNITS_PER_WORD

&& ( ISA_HAS_DSP_MULT ? ACC_REG_P ( REGNO ( dest ) ) : MD_REG_P ( REGNO ( dest ) ) ) ) ;


<s> case <STR_LIT> : DataVT = <STR_LIT> ; MaskVT = <STR_LIT> ; break ; } <STR_LIT> PgPattern ; switch ( VT . getVectorNumElements ( ) ) { default : return SDValue ( ) ; case <NUM_LIT> : PgPattern = VL16 ; break ; case <NUM_LIT> : PgPattern = VL8 ; break ; case <NUM_LIT> : PgPattern = VL4 ; break ; case <NUM_LIT> : PgPattern = VL2 ; break ; } int Idx = VT . is64BitVector ( ) ? <STR_LIT> : <STR_LIT> ; Mask = DAG . getTargetInsertSubreg ( Idx , DL , MaskVT , DAG . getUNDEF ( MaskVT ) , Mask ) ; Data = DAG . getTargetInsertSubreg ( Idx , DL , DataVT , DAG . getUNDEF ( DataVT ) , Data ) ; EVT PredVT = MaskVT . changeVectorElementType ( <STR_LIT> ) ; SDValue Pg = getPTrue ( DAG , DL , PredVT , PgPattern ) ; Mask = DAG . getNode ( <STR_LIT> , DL , PredVT , Mask ) ; Mask = DAG . getNode ( <STR_LIT> , DL , PredVT , Mask , Pg ) ; return DAG . getMaskedStore ( MSN -> getChain ( ) , DL , Data , MSN -> getBasePtr ( ) , Mask , MSN -> getMemoryVT

( ) , MSN -> getMemOperand ( ) , MSN -> isTruncatingStore ( ) ) ;


<s> unsigned getNumFixupKinds ( ) const override { return


<s> CalleeFn = dyn_cast < Function > ( G -> getGlobal ( ) ) ; } else if ( ExternalSymbolSDNode * E = dyn_cast < ExternalSymbolSDNode > ( Callee ) ) { const Function * Fn = DAG . getMachineFunction ( ) . getFunction ( ) ; const Module * M = Fn -> getParent ( ) ; const char * CalleeName = E -> getSymbol ( ) ; CalleeFn = M -> getFunction


<s> MachineBasicBlock * <ISA_LIT>TargetLowering :: EmitInstrWithCustomInserter ( MachineInstr & MI , MachineBasicBlock * MBB ) const { switch ( MI . getOpcode ( ) ) { case <STR_LIT> : return emitBrCC ( MI , MBB ) ; case <STR_LIT> : return emitSelectCC ( MI , MBB ) ; default : llvm_unreachable ( <STR_LIT>


<s> static StringRef const Table [ ] = { <STR_LIT> , } ; return makeArrayRef ( Table


<s> __o = __builtin_aarch64_set_qregciv16qi ( __o , ( int8x16_t ) tab . val [ <NUM_LIT> ] , <NUM_LIT> ) ; return ( poly8x16_t ) __builtin_aarch64_qtbx3v16qi ( ( int8x16_t ) r , __o , ( int8x16_t


<s> } } else { DispVal = Op3 . getImm ( ) ; } const MachineOperand & Base = MI . getOperand ( Op ) ; const MachineOperand & Scale = MI . getOperand ( Op + <NUM_LIT> ) ; const MachineOperand & IndexReg = MI . getOperand ( Op + <NUM_LIT> ) ; unsigned BaseReg = Base . getReg ( ) ; if ( ( ! Is64BitMode || DispForReloc || BaseReg != <NUM_LIT> ) && IndexReg . getReg ( ) == <NUM_LIT> && ( BaseReg == <NUM_LIT> || get<ISA_LIT>RegNum ( BaseReg ) != N86 :: ESP ) ) { if ( BaseReg == <NUM_LIT> ) { MCE . emitByte ( ModRMByte ( <NUM_LIT> , RegOpcodeField , <NUM_LIT> ) ) ; emitDisplacementField ( DispForReloc , DispVal , PCAdj ) ; } else { unsigned BaseRegNo = get<ISA_LIT>RegNum ( BaseReg ) ; if ( ! DispForReloc && DispVal == <NUM_LIT> && BaseRegNo != N86 :: EBP ) { MCE . emitByte ( ModRMByte ( <NUM_LIT> , RegOpcodeField , BaseRegNo ) ) ; } else if ( ! DispForReloc && isDisp8 ( DispVal ) ) { MCE . emitByte ( ModRMByte ( <NUM_LIT> , RegOpcodeField , BaseRegNo ) ) ; emitConstant ( DispVal , <NUM_LIT> ) ; } else { MCE . emitByte ( ModRMByte ( <NUM_LIT> , RegOpcodeField , BaseRegNo ) ) ; emitDisplacementField ( DispForReloc , DispVal , PCAdj ) ; } } } else { assert ( IndexReg . getReg ( ) != <STR_LIT> && IndexReg . getReg ( ) != <STR_LIT> && <STR_LIT> ) ; bool ForceDisp32 = false ; bool ForceDisp8 = false ; if ( BaseReg == <NUM_LIT> ) { MCE . emitByte ( ModRMByte ( <NUM_LIT> , RegOpcodeField , <NUM_LIT> ) ) ; ForceDisp32 = true ; } else if ( DispForReloc ) { MCE . emitByte ( ModRMByte ( <NUM_LIT> , RegOpcodeField , <NUM_LIT> ) ) ; ForceDisp32 = true ; } else if ( DispVal == <NUM_LIT> && get<ISA_LIT>RegNum ( BaseReg ) != N86 :: EBP ) { MCE . emitByte ( ModRMByte ( <NUM_LIT> , RegOpcodeField


<s> if ( LI -> isAtomic ( ) ) return false ; MVT VT ; if ( ! isTypeLegal ( LI -> getType ( ) , VT , true ) ) return false ; const Value * Ptr = LI -> getPointerOperand ( ) ; <ISA_LIT>AddressMode AM ; if ( ! <ISA_LIT>SelectAddress ( Ptr , AM ) ) return false ; unsigned ResultReg = <NUM_LIT> ; if ( ! <ISA_LIT>FastEmitLoad ( VT , AM , createMachineMemOperandFor ( LI ) , ResultReg )


<s> return ( loongarch_classify_address ( & addr , x , mode , false ) && ( ( addr . type == ADDRESS_REG && CONST_INT_P (

addr . offset ) && LARCH_12BIT_OFFSET_P ( INTVAL ( addr . offset ) ) ) || addr . type == ADDRESS_LO_SUM ) ) ;


<s> unsigned KnownBits = BBInfo [ i - <NUM_LIT> ] . postKnownBits ( LogAlign ) ; if ( i > BBNum + <NUM_LIT> && BBInfo [ i ] . Offset == Offset && BBInfo [ i ] .


<s> if ( Chain . getNode ( ) == Load . getNode ( ) ) Ops . push_back ( Load . getOperand ( <NUM_LIT> ) ) ; else { assert ( Chain . getOpcode ( ) == <STR_LIT> && <STR_LIT> ) ; for ( unsigned i = <NUM_LIT> , e = Chain . getNumOperands ( ) ; i != e ; ++ i ) if ( Chain . getOperand ( i ) . getNode ( ) == Load . getNode ( ) ) Ops . push_back ( Load . getOperand ( <NUM_LIT> ) ) ; else Ops . push_back ( Chain . getOperand ( i ) ) ; SDValue NewChain = CurDAG -> getNode ( <STR_LIT> , SDLoc ( Load ) , <STR_LIT> , Ops ) ; Ops . clear ( ) ; Ops . push_back ( NewChain


<s> BB -> addSuccessor ( copy0MBB ) ; BB -> addSuccessor ( sinkMBB ) ; BuildMI ( BB , DL , TII -> get ( Opc2 ) ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addImm ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; BuildMI ( BB , DL , TII -> get ( Opc1 ) ) . addMBB ( sinkMBB ) ; BB = copy0MBB ; BB -> addSuccessor ( sinkMBB ) ; BB = sinkMBB ; BuildMI ( * BB , BB -> begin ( ) , DL , TII -> get ( <STR_LIT> ) , MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addMBB ( thisMBB ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addMBB ( copy0MBB ) ; MI -> eraseFromParent


<s> assert ( NumOps >= <NUM_LIT> && OpInfo [ <NUM_LIT> ] . RegClass == <STR_LIT> && OpInfo [ <NUM_LIT> ] . RegClass == <STR_LIT> && OpInfo [ <NUM_LIT> ] . RegClass == <STR_LIT> && OpInfo [ <NUM_LIT> ] . RegClass < <NUM_LIT> && <STR_LIT> ) ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , decodeRd ( insn ) ) ) ) ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , decodeRs ( insn ) ) ) ) ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , decodeRn ( insn ) ) ) ) ; int Offset = getImm8 ( insn ) * <NUM_LIT> ; if ( getUBit ( insn ) == <NUM_LIT> ) Offset = - Offset ; MI . addOperand ( MCOperand :: CreateImm ( Offset ) ) ; NumOpsAdded = <NUM_LIT>


<s> unsigned push ( unsigned Opc , MVT Ty , std :: vector < OpRef > && Ops ) { NodeTemplate Res ; Res . Opc = Opc ; Res . Ty = Ty ; Res . Ops


<s> if ( extractAndPopulate ( I , Src ) ) { latency = getLatency ( Src ) ; } else if ( isCompoundInst ( I ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; IntrinsicVector IVec = getCiiMap ( ) [ I -> getOpcode ( ) ] -> getMapping ( I , getST ( ) ) ; latency = std :: accumulate ( IVec . begin ( ) , IVec . end ( ) , <NUM_LIT> , [ & Src , & I , this ] ( unsigned SumAcc , IntrinsicBunch IB ) { unsigned int Latency = <NUM_LIT> ; Type :: TypeID Ty [ TYPE_MATRIX ] ; getTypeMatrix ( I , Ty ) ; if ( extractAndPopulate ( { IB . Id , { Ty [ _PRIMARY_TYPE ] , Ty [ _VECTOR_TYPE ] } } , Src ) ) { Latency = getLatency ( Src ) ; } else { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << IB . Id <<


<s> int64_t val = ( ( const MCConstantExpr * ) Imm . Val ) -> getValue ( ) ; return isInt < <NUM_LIT> > ( val ) ; } return


<s> assert ( strcmp ( RuntimeLibcallNames [ RTLIB :: DEOPTIMIZE ] , <STR_LIT> ) == <NUM_LIT> ) ; for ( size_t i = <NUM_LIT> , e = RTLIB :: UNKNOWN_LIBCALL ; i < e ; ++ i ) if ( RuntimeLibcallNames [ i ] && strcmp ( RuntimeLibcallNames [

i ] , Name ) == <NUM_LIT> ) return GetSignature ( Subtarget , RTLIB :: Libcall ( i ) , Rets , Params ) ;


<s> if ( SrcVT == <STR_LIT> ) return Op ; if ( SrcVT == <STR_LIT> ) { if ( DstVT == <STR_LIT> ) { SDNodeFlags Flags ; Flags . setNoFPExcept ( Op -> getFlags ( ) . hasNoFPExcept ( ) ) ; if ( IsSigned ) { SDValue Lo = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Src , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Src , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ; if ( IsStrict ) { SDValue Res = DAG . getNode ( <STR_LIT> , dl , DAG . getVTList ( <STR_LIT> , <STR_LIT> ) , { Op . getOperand ( <NUM_LIT> ) , Lo , Hi } , Flags ) ; return DAG . getNode ( <STR_LIT> , dl , DAG . getVTList ( <STR_LIT> , <STR_LIT> ) , { Res . getValue ( <NUM_LIT> ) , Res } , Flags ) ; } else { SDValue Res = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Lo , Hi ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Res ) ; } } else { const uint64_t TwoE31 [ ] = { <NUM_LIT> , <NUM_LIT> } ; APFloat APF = APFloat ( APFloat :: <ISA_LIT>DoubleDouble ( ) , APInt ( <NUM_LIT> , TwoE31 ) ) ; SDValue Cst = DAG . getConstantFP ( APF , dl , SrcVT ) ; SDValue SignMask = DAG . getConstant ( <NUM_LIT> , dl , DstVT ) ; if ( IsStrict


<s> fprintf ( file , <STR_LIT> , cfun -> machine -> local_size ) ; fprintf ( file , <STR_LIT> , cfun -> machine -> out_args_size ) ; fprintf ( file , <STR_LIT> ) ; for ( r = <NUM_LIT> ; r < <NUM_LIT> ; r ++ ) { if ( df_regs_ever_live_p ( r ) ) fprintf ( file , <STR_LIT> , reg_names [ r ] ) ; } fputc ( '\n'


<s> for ( auto * D : Dependences ) { if ( D -> front ( ) == I1 && D -> back ( ) == I2 ) return D ; } return nullptr


<s> switch ( MF -> getFunction ( ) -> getCallingConv ( ) ) { case CallingConv :: GHC : case CallingConv :: HiPE : return CSR_NoRegs_SaveList ; case CallingConv :: AnyReg : if ( HasAVX ) return CSR_64_AllRegs_AVX_SaveList ; return CSR_64_AllRegs_SaveList ; case CallingConv :: PreserveMost : return CSR_64_RT_MostRegs_SaveList ; case CallingConv :: PreserveAll : if ( HasAVX ) return CSR_64_RT_AllRegs_AVX_SaveList ; return CSR_64_RT_AllRegs_SaveList ; case CallingConv :: Intel_OCL_BI : { if ( HasAVX512 && IsWin64 ) return CSR_Win64_Intel_OCL_BI_AVX512_SaveList ; if ( HasAVX512 && Is64Bit

) return CSR_64_Intel_OCL_BI_AVX512_SaveList ;


<s> return ( __m512i ) __builtin_ia32_pbroadcastd512_gpr_mask ( __A , ( __v16si )


<s> EVT VT = Op . getValueType ( ) ; if ( ( Subtarget -> hasSSE1 ( ) && ( VT == <STR_LIT> || VT == <STR_LIT> ) ) || ( Subtarget -> hasAVX ( ) && VT == <STR_LIT> ) ) { RefinementSteps =


<s> OperandMatchResultTy parsePCRel12 ( OperandVector & Operands ) { return parsePCRel ( Operands , - ( <NUM_LIT> << <NUM_LIT> ) , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT>


<s> int i , n = ( int ) ( ARRAY_SIZE ( prefixes ) ) ; for ( i = <NUM_LIT> ; i < n ; i ++ ) if ( str_prefix_p ( str , prefixes [ i ] ) ) return i ; return n


<s> return true ; } } return false ; } ; struct ImmCompare { MachineInstr * MI = nullptr ; unsigned NewOpc = <NUM_LIT> ; } ; auto FindCmpForCBZ = [ this ] ( ImmBranch & Br , ImmCompare & ImmCmp , MachineBasicBlock * DestBB ) { ImmCmp . MI = nullptr ; ImmCmp . NewOpc = <NUM_LIT> ; if ( ! Br . MI -> killsRegister ( <STR_LIT> ) ) return false ; Register PredReg ; unsigned NewOpc = <NUM_LIT> ; <STR_LIT> Pred = getInstrPredicate ( * Br . MI , PredReg ) ; if ( Pred == <STR_LIT> ) NewOpc = <STR_LIT> ; else if ( Pred == <STR_LIT> ) NewOpc = <STR_LIT> ; else return false ; unsigned BrOffset = BBUtils -> getOffsetOf ( Br . MI ) + <NUM_LIT> - <NUM_LIT> ; BBInfoVector & BBInfo = BBUtils -> getBBInfo ( ) ; unsigned DestOffset = BBInfo [ DestBB -> getNumber ( ) ] . Offset ; if ( BrOffset >= DestOffset || ( DestOffset - BrOffset ) > <NUM_LIT> ) return false ; auto * TRI = STI -> getRegisterInfo ( ) ; MachineInstr * CmpMI = findCMPToFoldIntoCBZ ( Br . MI , TRI ) ; if ( ! CmpMI || CmpMI -> getOpcode ( ) != <STR_LIT> ) return false ; ImmCmp . MI = CmpMI ; ImmCmp . NewOpc = NewOpc ; return true ; } ; auto TryConvertToLE = [ this ] ( ImmBranch & Br , ImmCompare & Cmp ) { if ( Br . MI -> getOpcode ( ) != <STR_LIT> || ! STI -> hasLOB ( ) || STI -> hasMinSize ( ) ) return false ; MachineBasicBlock * MBB = Br . MI -> getParent ( ) ; MachineBasicBlock * DestBB = Br . MI -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; if ( BBUtils -> getOffsetOf ( MBB ) < BBUtils -> getOffsetOf ( DestBB ) || ! BBUtils -> isBBInRange ( Br . MI , DestBB , <NUM_LIT> ) ) return false ; if ( ! DT -> dominates ( DestBB , MBB ) ) return false ; Cmp . NewOpc = Cmp . NewOpc == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; MachineInstrBuilder MIB = BuildMI ( * MBB , Br . MI , Br . MI -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) ; MIB . add ( Br . MI -> getOperand ( <NUM_LIT> ) ) ; Br . MI -> eraseFromParent ( ) ; Br . MI


<s> virtual const <ISA_LIT>TargetLowering * getTargetLowering ( ) const { return &


<s> MachineFunction * MF = blk -> getParent ( ) ; MachineInstr * NewInstr = MF -> CreateMachineInstr ( TII -> get ( NewOpcode ) , DL ) ; blk -> insert ( I , NewInstr ) ; MachineInstrBuilder ( * MF , NewInstr ) . addReg ( RegNum , false ) ; SHOWNEWINSTR (


<s> if ( ( ( VT != <STR_LIT> ) || ( InVT != <STR_LIT> ) ) && ( ( VT != <STR_LIT> ) || ( InVT != <STR_LIT> ) ) ) return SDValue ( ) ; if ( Subtarget -> hasInt256 ( ) ) return DAG . getNode ( <STR_LIT> , dl , VT , In ) ; SDValue ZeroVec = getZeroVector ( InVT , Subtarget , DAG , dl ) ; SDValue Undef = DAG . getUNDEF ( InVT ) ; bool NeedZero = Op . getOpcode ( ) == <STR_LIT> ; SDValue OpLo = getUnpackl ( DAG , dl , InVT , In , NeedZero ? ZeroVec


<s> if ( reg_src == REG_X ) return ! mem_volatile_p && reg_unused_after ( insn , src ) ? avr_asm_len ( <STR_LIT> CR_TAB <STR_LIT> CR_TAB <STR_LIT> CR_TAB <STR_LIT> , op , plen , - <NUM_LIT> ) : avr_asm_len ( <STR_LIT> CR_TAB <STR_LIT> CR_TAB <STR_LIT> CR_TAB <STR_LIT> CR_TAB <STR_LIT> , op , plen , - <NUM_LIT> ) ; return ! mem_volatile_p && reg_unused_after ( insn , base ) ? avr_asm_len ( <STR_LIT> CR_TAB <STR_LIT> , op , plen , - <NUM_LIT> ) : avr_asm_len ( <STR_LIT> CR_TAB <STR_LIT> CR_TAB <STR_LIT> , op , plen , - <NUM_LIT> ) ; } else if ( GET_CODE ( base ) == PLUS ) { int disp = INTVAL ( XEXP ( base , <NUM_LIT> ) ) ; if ( AVR_TINY ) return avr_out_movhi_mr_r_reg_disp_tiny ( insn , op , plen ) ; reg_base = REGNO ( XEXP ( base , <NUM_LIT> ) ) ; if ( disp > MAX_LD_OFFSET ( GET_MODE ( dest ) ) ) { if ( reg_base != REG_Y ) fatal_insn ( <STR_LIT> , insn ) ; return disp <= <NUM_LIT> + MAX_LD_OFFSET ( GET_MODE ( dest ) ) ? avr_asm_len ( <STR_LIT> CR_TAB <STR_LIT> CR_TAB <STR_LIT> CR_TAB <STR_LIT> , op , plen , - <NUM_LIT> ) : avr_asm_len ( <STR_LIT>


<s> if ( ST -> getNumElements ( ) != NumElts ) return nullptr ; for ( unsigned i = <NUM_LIT> , e = NumElts ; i != e ; ++ i ) { if ( Inst -> getArgOperand ( i ) -> getType ( ) != ST -> getElementType ( i ) ) return nullptr ; } Value * Res = UndefValue :: get ( ExpectedType ) ; IRBuilder < > Builder ( Inst ) ; for ( unsigned i = <NUM_LIT> , e = NumElts ; i != e ; ++ i ) { Value * L = Inst -> getArgOperand ( i ) ; Res = Builder . CreateInsertValue ( Res , L , i ) ; } return Res ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( Inst -> getType ( ) ==


<s> MVT PtrVT = <STR_LIT> ( <NUM_LIT> * TM . getPointerSize ( <NUM_LIT> ) ) ; setSchedulingPreference ( Sched :: RegPressure ) ; addRegisterClass ( <STR_LIT> , & <STR_LIT> ) ; addRegisterClass ( <STR_LIT> , & <STR_LIT> ) ; setStackPointerRegisterToSaveRestore ( <STR_LIT> ) ; computeRegisterProperties ( STI . getRegisterInfo ( )


<s> static inline bool isBranchRetTrap ( MachineInstr * MI ) { return ( MI -> isBranch ( ) || MI -> isReturn ( ) || MI ->


<s> adjustRelativeBranch ( Size , Fixup , Value , Ctx ) ; Value &=


<s> for ( MCRegUnitRootIterator R ( Unit , & PRI . getTRI ( ) ) ; R . isValid ( ) ; ++ R ) for ( MCSuperRegIterator S ( * R , & PRI . getTRI ( ) , true ) ; S . isValid ( ) ; ++ S ) Regs . set ( * S ) ; } ; BitVector Regs ( PRI . getTRI ( ) . getNumRegs ( ) ) ; AliasedRegs ( U , Regs ) ; U = Units . find_next ( U ) ; while ( U >= <NUM_LIT> ) { BitVector AR ( PRI . getTRI ( ) . getNumRegs ( ) ) ; AliasedRegs ( U , AR ) ; Regs &= AR ; U = Units . find_next ( U ) ; } int F = Regs . find_first ( ) ; if ( F <= <NUM_LIT> ) return RegisterRef ( ) ; LaneBitmask M ; for ( MCRegUnitMaskIterator I ( F , & PRI . getTRI ( ) ) ; I . isValid ( ) ; ++ I ) { std :: pair < uint32_t , LaneBitmask >


<s> int Offset ; MachineBasicBlock :: iterator MergeInstr = findIncDecBefore ( MBBI , Base , Pred , PredReg , Offset ) ; <STR_LIT> Mode = getLoadStoreMultipleSubMode ( Opcode ) ; if ( Mode == <STR_LIT> && Offset == - Bytes ) { Mode = <STR_LIT> ; } else if ( Mode == <STR_LIT> && Offset == - Bytes ) { Mode = <STR_LIT> ; } else { MergeInstr = findIncDecAfter ( MBBI , Base , Pred , PredReg , Offset , TRI ) ; if ( ( ( Mode != <STR_LIT> && Mode != <STR_LIT> ) || Offset != Bytes ) && ( ( Mode != <STR_LIT> && Mode != <STR_LIT> ) || Offset != - Bytes ) ) { if ( ! STI -> hasMinSize ( ) || ! BaseKill ) return false ; bool HighRegsUsed = false ; for ( const MachineOperand & MO : llvm :: drop_begin ( MI -> operands ( ) , <NUM_LIT> ) ) if ( MO . getReg ( ) >= <STR_LIT> ) { HighRegsUsed = true ; break ; } if ( ! HighRegsUsed ) MergeInstr = MBB . end ( ) ; else return false ; } } if ( MergeInstr != MBB . end ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << *


<s> MFI -> setFrameAddressIsTaken ( true ) ; EVT VT = Op . getValueType ( ) ; SDLoc dl ( Op ) ; unsigned Depth = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; const <ISA_LIT>RegisterInfo * RegInfo = static_cast < const <ISA_LIT>RegisterInfo * > ( getTargetMachine ( ) . getRegisterInfo ( ) ) ; unsigned FrameReg = RegInfo -> getFrameRegister ( DAG . getMachineFunction ( )


<s> static Target The<ISA_LIT>32Target ; return The<ISA_LIT>32Target


<s> const bool WasThumb = isThumb ( StartInfo ) ; if ( ! EndInfo || WasThumb != isThumb ( * EndInfo ) ) { OutStreamer -> EmitAssemblerFlag ( WasThumb ? MCAF_Code16 :


<s> if ( MI . memoperands_empty ( ) ) return true ; for ( const MachineMemOperand * MMO : MI . memoperands ( ) ) { if ( MMO -> getAddrSpace ( ) == <ISA_LIT>AS :: FLAT_ADDRESS ) return true ; } return false


<s> MachineBasicBlock :: iterator <ISA_LIT>InstrInfo :: insertOutlinedCall ( Module & M , MachineBasicBlock & MBB , MachineBasicBlock :: iterator & It , MachineFunction & MF , const outliner :: Candidate & C ) const { if ( C . CallConstructionID == MachineOutlinerTailCall ) { It = MBB . insert ( It , BuildMI ( MF , DebugLoc ( ) , get ( <STR_LIT> ) ) . addGlobalAddress ( M . getNamedValue ( MF . getName ( ) ) ) ) ; } else { It = MBB . insert ( It , BuildMI ( MF , DebugLoc ( ) , get ( <STR_LIT> ) ) . addGlobalAddress ( M .


<s> bool <ISA_LIT>TargetLowering :: allowsMisalignedMemoryAccesses ( EVT VT , unsigned , unsigned , bool * Fast ) const { bool AllowsUnaligned = Subtarget -> allowsUnalignedMem ( ) ; switch ( VT . getSimpleVT ( ) . SimpleTy ) { default : return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { if ( AllowsUnaligned ) { if ( Fast ) * Fast = Subtarget -> hasV7Ops ( ) ; return


<s> const <ISA_LIT>TargetLowering * getTargetLowering ( ) const override { return &


<s> return ( uint64x1_t ) { __a [ <NUM_LIT> ] >= __b


<s> static bool isSupportedCmpOp ( unsigned opCode ) { return ( opCode == <STR_LIT> || opCode == <STR_LIT> || opCode == <STR_LIT> || opCode == <STR_LIT> || opCode == <STR_LIT> || opCode == <STR_LIT> ||

opCode == <STR_LIT> || opCode == <STR_LIT> ) ;


<s> MCELFStreamer :: EmitInstruction ( Inst


<s> static MCSymbolizer * create<ISA_LIT>ExternalSymbolizer ( StringRef TT , LLVMOpInfoCallback GetOpInfo , LLVMSymbolLookupCallback SymbolLookUp , void * DisInfo , MCContext * Ctx , MCRelocationInfo * RelInfo ) { return new llvm :: <ISA_LIT>ExternalSymbolizer ( * Ctx , std :: unique_ptr < MCRelocationInfo > ( RelInfo ) , GetOpInfo


<s> bool <ISA_LIT>AsmParser :: ParseOperand ( OwningPtr < <ISA_LIT>Operand > & Op ) { SMLoc S , E ; switch ( getLexer ( ) . getKind ( ) ) { case AsmToken :: Identifier : if ( ! MaybeParseRegister ( Op , true ) ) return false ; const MCExpr * IdVal ; S = Parser . getTok ( ) . getLoc ( ) ; if ( getParser ( ) . ParseExpression ( IdVal ) ) return true ; E = SMLoc :: getFromPointer ( Parser . getTok ( ) . getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; <ISA_LIT>Operand :: CreateImm ( Op , IdVal , S , E ) ; return false ; case AsmToken :: LBrac : return ParseMemory ( Op


<s> vmlsq_u16 ( uint16x8_t a , uint16x8_t b , uint16x8_t c ) { uint16x8_t result


<s> return ( poly64x1_t ) __builtin_neon_vreinterpretdiv4hi ( ( int16x4_t )


<s> void <ISA_LIT>InstPrinter :: printS8ImmOperand ( const MCInst * MI , int OpNum , raw_ostream & O ) { printSImmOperand < <NUM_LIT> > ( MI , OpNum , O


<s> if ( CS . isNoInline ( ) ) return llvm :: InlineCost :: getNever ( <STR_LIT> ) ; TargetTransformInfo & TTI = TTIWP -> getTTI ( * Callee ) ; if ( ! TTI . areInlineCompatible ( Caller , Callee ) ) return llvm :: InlineCost :: getNever ( <STR_LIT> ) ; if ( CS . hasFnAttr ( Attribute :: AlwaysInline ) ) { auto IsViable = isInlineViable ( * Callee ) ; if ( IsViable . isSuccess ( ) ) return llvm :: InlineCost :: getAlways ( <STR_LIT> ) ; return llvm :: InlineCost :: getNever ( IsViable . getFailureReason ( ) ) ; } if ( isWrapperOnlyCall ( CS ) ) return llvm :: InlineCost :: getAlways ( <STR_LIT> ) ; InlineParams LocalParams = Params ; LocalParams . DefaultThreshold = ( int ) getInlineThreshold ( CS ) ; bool RemarksEnabled = false ; const auto & BBs = Caller -> getBasicBlockList (


<s> rtx mem = gen_frame_mem ( BLKmode , stack_pointer_rtx ) ; if ( frame_pointer_needed ) emit_insn ( gen_stack_tie ( Pmode , mem , hard_frame_pointer_rtx )


<s> else if ( ! Subtarget . has<ISA_LIT>64 ( ) ) return CSR_O32_RegMask ; else if ( Subtarget . isABI_N32


<s> assert ( Slot < Data . size ( ) && <STR_LIT> ) ; return Data [ Slot


== <NUM_LIT> || ! sparc_leaf_function_p ) ;


<s> static LoadStoreMethod PossibleClasses [ ] = { { & <STR_LIT> , <STR_LIT> , <STR_LIT> } , { & <STR_LIT> , <STR_LIT> , <STR_LIT> } , } ; unsigned NumClasses = llvm :: array_lengthof ( PossibleClasses ) ; emitFrameMemOps ( true , MBB , MBBI , CSI , TRI , PossibleClasses , NumClasses ) ; return true


<s>
void
print
(
raw_ostream
&
OS
)
const
{
OS
<<
<STR_LIT>
<<
MinSrc
<<
<STR_LIT>
<<
MaxSrc
<<
<STR_LIT>
;
for
(
int
M
:
Mask
)
OS
<<
' '
<<
M
;
OS
<<
<STR_LIT>


<s> FPM . addPass ( <ISA_LIT>PreserveDITypePass ( ) ) ; MPM . addPass ( createModuleToFunctionPassAdaptor ( std :: move ( FPM ) ) ) ; } ) ; PB . registerPeepholeEPCallback ( [ = ] ( FunctionPassManager & FPM , PassBuilder :: OptimizationLevel Level ) { FPM . addPass ( SimplifyCFGPass ( SimplifyCFGOptions ( ) . hoistCommonInsts ( true )


<s> addPass ( createIfConverter ( [ ] ( const MachineFunction & MF ) { return ! MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . isThumb1Only ( ) ; } ) ) ; } addPass ( createMVEVPTBlockPass ( ) ) ; addPass ( createThumb2ITBlockPass ( ) ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) { addPass ( &


<s> char * str = ( char * ) xmalloc ( strlen ( const_str ) ) ; enum aarch_parse_opt_result res = aarch_parse_branch_protection ( const_str , & str ) ; if ( res == AARCH_PARSE_INVALID_ARG ) error (


<s> op12 = gen_rtx_ZERO_EXTRACT ( HImode , operands [ <NUM_LIT> ] , GEN_INT ( <NUM_LIT> ) , GEN_INT ( <NUM_LIT> ) ) ; op12 = gen_rtx_CONST ( HImode , op12 ) ; } else { op10 = rl78_subreg ( HImode , operands [ <NUM_LIT> ] , SImode , <NUM_LIT> ) ; op12 = rl78_subreg ( HImode , operands [ <NUM_LIT> ] , SImode , <NUM_LIT> ) ; } if ( rtx_equal_p ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ) ; else if ( rtx_equal_p ( op00 , op12 ) ) { emit_move_insn ( op02 , op12 ) ; emit_move_insn ( op00 , op10 ) ; } else { emit_move_insn ( op00 , op10 ) ; emit_move_insn ( op02


<s> bool <ISA_LIT>PassConfig :: addIRTranslator (


<s> default : break ; case <STR_LIT> : { int FI = cast < FrameIndexSDNode > ( Node ) -> getIndex ( ) ; SDValue TFI = CurDAG -> getTargetFrameIndex ( FI , TLI -> getPointerTy ( CurDAG -> getDataLayout ( ) ) ) ; CurDAG -> SelectNodeTo ( Node , <STR_LIT> , <STR_LIT> , TFI , CurDAG -> getTargetConstant ( <NUM_LIT> , dl ,


<s> virtual const InstrItineraryData * getInstrItineraryData ( ) const { return & InstrItins


<s> using ValueEntry = std :: pair < SDValue , size_t > ; SmallVector < ValueEntry , <NUM_LIT> > SplatValueCounts ; using SwizzleEntry = std :: pair < std :: pair < SDValue , SDValue > , size_t > ; SmallVector < SwizzleEntry , <NUM_LIT> > SwizzleCounts ; auto AddCount = [ ] ( auto & Counts , const auto & Val ) { auto CountIt = std :: find_if ( Counts . begin ( ) , Counts . end ( ) , [ & Val ] ( auto E ) { return E . first == Val ; } ) ; if ( CountIt == Counts . end ( ) ) { Counts . emplace_back ( Val , <NUM_LIT> ) ; } else { CountIt -> second ++ ; } } ; auto GetMostCommon = [ ] ( auto & Counts ) { auto CommonIt = std :: max_element ( Counts . begin ( ) , Counts . end ( ) , [ ] ( auto A , auto B ) { return A . second < B . second ; } ) ; assert ( CommonIt != Counts . end ( ) && <STR_LIT> ) ; return * CommonIt ; } ; size_t NumConstantLanes = <NUM_LIT> ; for ( size_t I = <NUM_LIT> ; I < Lanes ; ++ I ) { const SDValue & Lane = Op -> getOperand ( I ) ; if ( Lane . isUndef ( ) ) continue ; AddCount ( SplatValueCounts , Lane ) ; if ( IsConstant ( Lane ) ) { NumConstantLanes ++ ; } else if ( CanSwizzle ) { auto SwizzleSrcs = GetSwizzleSrcs ( I , Lane ) ; if ( SwizzleSrcs . first ) AddCount ( SwizzleCounts , SwizzleSrcs ) ; } } SDValue SplatValue ; size_t NumSplatLanes ; std :: tie ( SplatValue , NumSplatLanes ) = GetMostCommon ( SplatValueCounts ) ; SDValue SwizzleSrc ; SDValue SwizzleIndices ; size_t NumSwizzleLanes = <NUM_LIT> ; if ( SwizzleCounts . size ( ) ) std :: forward_as_tuple ( std :: tie ( SwizzleSrc , SwizzleIndices ) , NumSwizzleLanes ) = GetMostCommon ( SwizzleCounts ) ; std :: function < bool ( size_t , const SDValue & ) > IsLaneConstructed ; SDValue Result ; if ( NumSwizzleLanes >= NumSplatLanes && ( ! Subtarget -> hasUnimplementedSIMD128 ( ) || NumSwizzleLanes >= NumConstantLanes ) ) { Result = DAG . getNode ( <STR_LIT> , DL , VecT , SwizzleSrc , SwizzleIndices ) ; auto Swizzled = std :: make_pair ( SwizzleSrc , SwizzleIndices ) ; IsLaneConstructed = [ & , Swizzled ] ( size_t I , const SDValue & Lane ) { return Swizzled == GetSwizzleSrcs ( I , Lane ) ; } ; } else if ( NumConstantLanes >= NumSplatLanes && Subtarget -> hasUnimplementedSIMD128 ( ) ) { SmallVector < SDValue , <NUM_LIT> > ConstLanes ; for ( const SDValue & Lane : Op


<s> int mmix_asm_preferred_eh_data_format ( int code ATTRIBUTE_UNUSED , int global ATTRIBUTE_UNUSED ) { return DW_EH_PE_absptr


<s> Instr = match ( Opcode , Args ... ) ; return Instr !=


<s> static bool rs6000_hard_regno_mode_ok ( unsigned int regno , machine_mode


<s> int i [ <NUM_LIT> ] ; } x ; vec_uchar16 mask ; count = <NUM_LIT> - count ; x . i [ <NUM_LIT>


<s> CurFPOData -> PrologueEnd = emitFPOLabel ( ) ; return false


<s> bool SelectAddrIdxOffs ( SDValue N , SDValue & Out ) const { if ( isa < ConstantSDNode > ( N ) || N . getOpcode ( ) == <STR_LIT> || N . getOpcode ( ) == <STR_LIT> ) return false ; Out = N ; return true


<s> const TargetRegisterInfo & getRegisterInfo ( ) const { return RI


<s> GetInstSeqLs ( Imm & ~ <NUM_LIT> , RemSize , SeqLs ) ; AddInstr ( SeqLs , Inst ( ORi , Imm & <NUM_LIT>


<s> extern __inline int __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) __crcc_w_b_w ( char _1 , int _2 ) { return ( int ) __builtin_loongarch_crcc_w_b_w ( ( char ) _1 , ( int )


<s> DEBUG ( dbgs ( ) << <STR_LIT> ) ; bundleScope ( root ) ; DEBUG ( { dbgs ( ) << <STR_LIT> ; root -> dump ( dbgs ( ) , <NUM_LIT> , true ) ; dbgs ( ) << <STR_LIT> ; } )


<s> unsigned AddrOp = AddrBase + <NUM_LIT> ; assert ( Inst . getNumOperands ( ) == <NUM_LIT> && Inst . getOperand ( RegOp ) . isReg ( ) && Inst . getOperand ( AddrBase + <STR_LIT> ) . isReg ( ) && Inst . getOperand ( AddrBase + <STR_LIT> ) . isImm ( ) && Inst . getOperand ( AddrBase + <STR_LIT> ) . isReg ( ) && Inst . getOperand ( AddrBase + <STR_LIT> ) . isReg ( ) && ( Inst . getOperand ( AddrOp ) . isExpr ( ) || Inst . getOperand ( AddrOp ) . isImm ( ) ) && <STR_LIT> ) ; unsigned Reg = Inst . getOperand ( RegOp ) . getReg ( ) ; if ( Reg != <STR_LIT> && Reg != <STR_LIT> && Reg != <STR_LIT> && Reg != <STR_LIT> ) return ; bool Absolute = true ; if ( Inst . getOperand ( AddrOp ) . isExpr ( ) ) { const MCExpr * MCE = Inst . getOperand ( AddrOp ) . getExpr ( ) ; if ( const MCSymbolRefExpr * SRE = dyn_cast < MCSymbolRefExpr > ( MCE ) ) if ( SRE -> getKind ( ) == MCSymbolRefExpr :: VK_TLVP ) Absolute = false ; } if ( Absolute && ( Inst . getOperand ( AddrBase + <STR_LIT> ) . getReg ( ) != <NUM_LIT> || Inst . getOperand ( AddrBase + <STR_LIT> ) . getImm ( ) != <NUM_LIT> || Inst . getOperand ( AddrBase + <STR_LIT> ) . getReg ( ) != <NUM_LIT> ) ) return ; MCOperand Saved = Inst . getOperand ( AddrOp ) ; MCOperand Seg = Inst . getOperand (


<s> MCE . addRelocation ( MachineRelocation :: getBB ( MCE . getCurrentPCOffset ( ) , <STR_LIT> , MBB ) ) ; MCE . emitWordLE (


<s> if ( mode == TImode || mode == V1TImode ) { mode = V2DImode ; dest = adjust_address ( dest , V2DImode , <NUM_LIT> ) ; source = gen_lowpart ( V2DImode , source ) ; } rtx tmp = gen_reg_rtx_and_attrs ( source ) ; rs6000_emit_le_vsx_permute ( tmp , source , mode


<s> if ( ! ExtraCode ) { const MachineOperand & MO = MI -> getOperand ( OpNo ) ; if ( ! MO . isReg ( ) )


<s> unsigned count = <NUM_LIT> ; while ( * p && isspace ( * p ) && * p != '\n' ) p ++ ; count ++ ; while ( * p && * p != '\n' && strncmp ( p , BaseTAI :: CommentString , strlen ( BaseTAI :: CommentString ) ) != <NUM_LIT> ) { if ( * p ==


<s> void <ISA_LIT>LongBranch :: replaceBranch ( MachineBasicBlock & MBB , Iter Br , DebugLoc DL , MachineBasicBlock * MBBOpnd ) { unsigned NewOpc = TII -> GetOppositeBranchOpc ( Br -> getOpcode ( ) ) ; const MCInstrDesc & NewDesc = TII -> get ( NewOpc ) ; MachineInstrBuilder MIB = BuildMI ( MBB , Br , DL , NewDesc ) ; for ( unsigned I = <NUM_LIT> , E = Br -> getDesc ( ) . getNumOperands ( ) ; I < E ; ++ I ) { MachineOperand & MO = Br -> getOperand ( I ) ; if ( ! MO . isReg ( ) ) { assert ( MO . isMBB ( ) && <STR_LIT> ) ; break ; } MIB . addReg ( MO . getReg ( ) ) ; } MIB . addMBB (


<s> Types . try_emplace ( MI , InstType ::


<s> case <STR_LIT> : case <STR_LIT> : LGKMCnt |= IsCrossAddrSpaceOrdering ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : break ; default : llvm_unreachable ( <STR_LIT> ) ; } } if ( VMCnt || LGKMCnt ) { unsigned WaitCntImmediate = <STR_LIT> ( IV , VMCnt ? <NUM_LIT> : getVmcntBitMask ( IV ) , getExpcntBitMask ( IV ) , LGKMCnt ? <NUM_LIT> : getLgkmcntBitMask ( IV ) ) ; BuildMI ( MBB , MI , DL , TII -> get ( <STR_LIT> ) ) . addImm ( WaitCntImmediate ) ; Changed = true ; } if ( VSCnt ) { BuildMI ( MBB , MI , DL , TII -> get ( <STR_LIT> ) ) . addReg ( <STR_LIT> , RegState :: Undef ) . addImm ( <NUM_LIT> ) ; Changed = true ; } if ( Pos == Position :: AFTER


<s> assert ( MO . isExpr ( ) && <STR_LIT> ) ; MCFixupKind Kind = MCFixupKind ( <STR_LIT> ) ; Fixups . push_back ( MCFixup :: create ( <NUM_LIT> , MO . getExpr ( ) , Kind , MI . getLoc ( ) ) ) ; ++ MCNumFixups


<s> ReduceEntryVector :: const_iterator Start = std :: begin ( ReduceTable ) ; ReduceEntryVector :: const_iterator End = std :: end ( ReduceTable ) ; std :: pair < ReduceEntryVector :: const_iterator , ReduceEntryVector :: const_iterator > Range = std :: equal_range ( Start , End , Opcode ) ; if ( Range . first == Range . second ) return false ; for ( ReduceEntryVector :: const_iterator Entry = Range . first ; Entry != Range . second ; ++ Entry ) { ReduceEntryFunArgs Arguments ( & ( * MII ) , * Entry , NextMII ) ; if ( ( ( * Entry ) . ReduceFunction ) ( &


<s> assert ( N -> getOperand ( <NUM_LIT> ) . getValueType ( ) . getVectorElementType

( ) . getSizeInBits ( ) == <NUM_LIT> && <STR_LIT> ) ;


<s> Register Reg = <STR_LIT> + RegNo ; Inst . addOperand ( MCOperand :: createReg ( Reg ) ) ; return MCDisassembler ::


<s> if ( III . ImmMustBeMultipleOf > <NUM_LIT> || III . TruncateImmTo || III . ImmWidth != <NUM_LIT> ) return false ; if ( ImmMO . isGlobal ( ) ) { const DataLayout & DL = ImmMO . getGlobal ( ) -> getParent ( ) -> getDataLayout ( ) ; if ( ImmMO . getGlobal ( ) -> getPointerAlignment ( DL ) < III . ImmMustBeMultipleOf ) return false ; } return true ; } if ( ImmMO . isImm ( ) ) { Imm = SignExtend64 < <NUM_LIT> > ( ImmMO . getImm ( ) + BaseImm ) ; if ( Imm % III . ImmMustBeMultipleOf ) return false ; if ( III . TruncateImmTo ) Imm &= ( ( <NUM_LIT> << III . TruncateImmTo ) - <NUM_LIT> ) ; if ( III . SignedImm ) { APInt ActualValue ( <NUM_LIT> , Imm , true ) ; if ( ! ActualValue . isSignedIntN ( III . ImmWidth


<s> static bool IsFrameChange ( MachineInstr & MI ) { return MI . modifiesRegister ( <STR_LIT> , NULL ) ||

MI . modifiesRegister ( <STR_LIT> , NULL ) ;


<s> auto WideSize = VT . getVectorElementCount ( ) ; MVT EltTy = VT . getVectorElementType ( ) . getSimpleVT ( ) ; MVT NarrowTy = <STR_LIT> ( EltTy , WideSize / <NUM_LIT> ) ; return DAG . getTargetExtractSubreg ( <STR_LIT> , SDLoc ( V128Reg )


<s> RegisterMCAsmInfoFn X ( The<ISA_LIT>Target , create<ISA_LIT>MCAsmInfo ) ; RegisterMCAsmInfoFn Y ( The<ISA_LIT>V9Target , create<ISA_LIT>V9MCAsmInfo ) ; for ( Target * T : { & The<ISA_LIT>Target , & The<ISA_LIT>V9Target } ) { TargetRegistry :: RegisterMCInstrInfo ( * T , create<ISA_LIT>MCInstrInfo ) ; TargetRegistry :: RegisterMCRegInfo ( * T , create<ISA_LIT>MCRegisterInfo ) ; TargetRegistry :: RegisterMCSubtargetInfo ( * T , create<ISA_LIT>MCSubtargetInfo ) ; TargetRegistry :: RegisterMCCodeEmitter ( * T , create<ISA_LIT>MCCodeEmitter ) ; TargetRegistry :: RegisterMCAsmBackend ( * T , create<ISA_LIT>AsmBackend ) ; TargetRegistry :: RegisterObjectTargetStreamer ( * T , createObjectTargetStreamer ) ; TargetRegistry :: RegisterAsmTargetStreamer ( * T , createTargetAsmStreamer


<s> SeparatorString = <STR_LIT> ; CommentColumn = <NUM_LIT> ; CommentString = <STR_LIT> ; LabelSuffix = <STR_LIT> ; GlobalPrefix = <STR_LIT> ; PrivateGlobalPrefix = <STR_LIT> ; LinkerPrivateGlobalPrefix = <STR_LIT> ; InlineAsmStart = <STR_LIT> ; InlineAsmEnd = <STR_LIT> ; AssemblerDialect = <NUM_LIT> ; ZeroDirective = <STR_LIT> ; AsciiDirective = <STR_LIT> ; AscizDirective = <STR_LIT> ; Data8bitsDirective = <STR_LIT> ; Data16bitsDirective =


<s> gcc_assert ( GET_MODE ( reg ) == SImode && n >= - <NUM_LIT> && n != <NUM_LIT> && n <= <NUM_LIT> ) ; switch ( n ) { case <NUM_LIT> : s = <STR_LIT> ; break ; case <NUM_LIT> : s = <STR_LIT> ; break ; case <NUM_LIT> : s = <STR_LIT> ; break ; case - <NUM_LIT> : s =


<s> static bool ix86_function_naked ( const_tree fn ) { if ( fn && lookup_attribute ( <STR_LIT> , DECL_ATTRIBUTES ( fn ) ) ) return true ; return


<s> int indirect_p , size , n_reg , sav_ofs , sav_scale , max_reg ; tree lab_false , lab_over = NULL_TREE ; tree addr = create_tmp_var ( ptr_type_node , <STR_LIT> ) ; bool left_align_p ; f_gpr = TYPE_FIELDS ( TREE_TYPE ( va_list_type_node ) ) ; f_fpr = DECL_CHAIN ( f_gpr ) ; f_ovf = DECL_CHAIN ( f_fpr ) ; f_sav = DECL_CHAIN ( f_ovf ) ; gpr = build3 ( COMPONENT_REF , TREE_TYPE ( f_gpr ) , valist , f_gpr , NULL_TREE ) ; fpr = build3 ( COMPONENT_REF , TREE_TYPE ( f_fpr ) , valist , f_fpr , NULL_TREE ) ; sav = build3 ( COMPONENT_REF , TREE_TYPE ( f_sav ) , valist , f_sav , NULL_TREE ) ; valist = unshare_expr ( valist ) ; ovf = build3 ( COMPONENT_REF , TREE_TYPE ( f_ovf ) , valist , f_ovf , NULL_TREE ) ; size = int_size_in_bytes ( type ) ; s390_check_type_for_vector_abi ( type , true , false ) ; if ( pass_va_arg_by_reference ( type ) ) { if ( TARGET_DEBUG_ARG ) { fprintf ( stderr , <STR_LIT> ) ; debug_tree ( type ) ; } indirect_p = <NUM_LIT> ; reg = gpr ; n_reg = <NUM_LIT> ; sav_ofs = <NUM_LIT> * UNITS_PER_LONG ; sav_scale = UNITS_PER_LONG ; size = UNITS_PER_LONG ; max_reg = GP_ARG_NUM_REG - n_reg ; left_align_p = false ; } else if ( s390_function_arg_vector ( TYPE_MODE ( type ) , type ) ) { if ( TARGET_DEBUG_ARG ) { fprintf ( stderr , <STR_LIT> ) ; debug_tree ( type ) ; } indirect_p = <NUM_LIT> ; reg = NULL_TREE ; n_reg = <NUM_LIT> ; sav_ofs = <NUM_LIT> ; sav_scale = <NUM_LIT> ; max_reg = <NUM_LIT> ; left_align_p = true ; } else if ( s390_function_arg_float ( TYPE_MODE ( type ) , type ) ) { if ( TARGET_DEBUG_ARG ) { fprintf ( stderr , <STR_LIT> ) ; debug_tree ( type ) ; } indirect_p = <NUM_LIT> ; reg = fpr ; n_reg = <NUM_LIT> ; sav_ofs = <NUM_LIT>


<s> static int alpha_multipass_dfa_lookahead


<s> <ISA_LIT>MCInstrInfo :: setInnerLoop ( MCB ) ; <ISA_LIT>MCInstrInfo :: setOuterLoop ( MCB ) ; } else if ( Option . compare_insensitive ( <STR_LIT> ) == <NUM_LIT> ) { <ISA_LIT>MCInstrInfo :: setInnerLoop ( MCB ) ; } else if ( Option . compare_insensitive ( <STR_LIT> ) == <NUM_LIT> ) { <ISA_LIT>MCInstrInfo :: setOuterLoop ( MCB ) ; } else if ( Option . compare_insensitive ( <STR_LIT> ) == <NUM_LIT> ) { if ( getSTI ( ) . getFeatureBits ( ) [ <STR_LIT> ] ) <ISA_LIT>MCInstrInfo :: setMemReorderDisabled ( MCB ) ; else return getParser ( ) . Error ( IDLoc , MemNoShuffMsg ) ; } else if ( Option . compare_insensitive ( <STR_LIT> ) == <NUM_LIT> ) { } else return getParser ( ) . Error ( IDLoc , llvm :: Twine ( <STR_LIT> ) + Option +


<s> case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } const GCNSubtarget & ST = MBB . getParent ( ) -> getSubtarget < GCNSubtarget > ( ) ; if ( ST . hasNoSdstCMPX ( ) ) Opcode = <STR_LIT> ( Opcode ) ; assert ( MI . getOperand ( <NUM_LIT> ) . isReg ( ) ) ; if ( TRI -> isVGPR ( MBB . getParent ( ) -> getRegInfo ( ) , MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ) { Opcode = <STR_LIT> ( Opcode ) ; BuildMI ( MBB , & MI , DL , TII -> get ( Opcode ) ) . add ( MI . getOperand ( <NUM_LIT> ) ) . add ( MI . getOperand ( <NUM_LIT> ) ) ; } else { auto I = BuildMI ( MBB , & MI , DL , TII -> get ( Opcode ) ) ; if ( ! ST . hasNoSdstCMPX ( ) ) I . addReg ( <STR_LIT> , RegState :: Define ) ; I . addImm ( <NUM_LIT> ) . add ( MI . getOperand ( <NUM_LIT> ) ) . addImm ( <NUM_LIT> ) . add ( MI . getOperand ( <NUM_LIT> ) ) ; I . addImm (


<s> machine_mode mn10300_select_cc_mode ( enum rtx_code code , rtx x , rtx y ATTRIBUTE_UNUSED ) { int req ; if ( GET_MODE_CLASS ( GET_MODE ( x ) ) == MODE_FLOAT ) return CC_FLOATmode ; req = cc_flags_for_code ( code )


<s> bool IsSubAdd ; if ( ! isAddSubOrSubAdd ( BV , Subtarget , DAG , Opnd0 , Opnd1 , NumExtracts , IsSubAdd ) ) return SDValue ( ) ; MVT VT = BV -> getSimpleValueType ( <NUM_LIT> ) ; SDLoc DL ( BV ) ; SDValue Opnd2 ; if ( isFMAddSubOrFMSubAdd ( Subtarget , DAG , Opnd0 , Opnd1 , Opnd2 , NumExtracts ) ) { unsigned Opc = IsSubAdd ? <STR_LIT> : <STR_LIT> ; return DAG . getNode ( Opc , DL , VT , Opnd0 , Opnd1 , Opnd2 ) ; } if ( IsSubAdd ) return SDValue ( ) ; if ( VT . is512BitVector ( ) ) { SmallVector < int > Mask ; for ( int I = <NUM_LIT> , E = VT . getVectorNumElements ( ) ; I != E ; I += <NUM_LIT> ) { Mask . push_back (


<s> bool fixupNeedsRelaxation ( const MCFixup & Fixup , uint64_t Value , const MCRelaxableFragment * DF , const MCAsmLayout & Layout ) const override { return


<s> const JumpTableSDNode * JT = cast < JumpTableSDNode > ( Op ) ; return DAG . getTargetJumpTable ( JT -> getIndex ( ) , Op . getValueType ( ) ,


<s> bool IsNakedFunction = MF -> getFunction ( ) . hasFnAttribute ( Attribute :: Naked ) ; if ( ! IsNakedFunction ) emitFrameDirective ( ) ; if ( ! IsNakedFunction ) printSavedRegsBitmask ( ) ; if ( ! Subtarget -> in<ISA_LIT>16Mode ( ) ) { TS . emitDirectiveSetNoReorder


<s> const IFListType & LL = I -> second ; RegisterSet TT ; for ( unsigned i = <NUM_LIT> , n = LL . size ( ) ; i < n ; ++ i ) TT . insert ( LL [ i ] . second ) ; for ( unsigned R = TT . find_first ( ) ; R ; R = TT . find_next ( R ) ) RemC [ R ] ++ ; AllRMs . insert ( TT ) ; } for ( unsigned R = AllRMs . find_first ( ) ; R ; R = AllRMs . find_next ( R ) ) { typedef MachineRegisterInfo :: use_nodbg_iterator use_iterator ; typedef SmallSet < const MachineInstr * , <NUM_LIT> > InstrSet ; InstrSet UIs ; use_iterator E = MRI -> use_nodbg_end ( ) ; for ( use_iterator I = MRI -> use_nodbg_begin ( R ) ; I != E ; ++ I ) UIs . insert ( I -> getParent ( ) ) ; unsigned C = UIs . size ( ) ; unsigned D = RemC [ R ] ; UseC [ R ] = ( C > D ) ? C - D : <NUM_LIT> ; } bool SelectAll0 = OptSelectAll0 , SelectHas0 = OptSelectHas0 ; if ( ! SelectAll0 && ! SelectHas0 ) SelectAll0 = true ; IFOrdering IFO ( UseC , BaseOrd ) ; for ( IFMapType :: iterator I = IFMap . begin ( ) ; I != End ; ++ I ) { IFListType & LL = I -> second ; if ( LL . empty ( ) ) continue ; IFListType :: iterator MinI = std :: min_element ( LL . begin ( ) , LL . end ( ) , IFO ) ; assert ( MinI != LL . end ( ) ) ; IFRecordWithRegSet M = * MinI ; LL . clear ( ) ; RegisterSet Us ; const MachineInstr * DefI = MRI -> getVRegDef ( I -> first ) ; getInstrUses ( DefI , Us ) ; bool Accept = false ; if ( SelectAll0 ) { bool All0 = true ; for ( unsigned R = Us . find_first ( ) ; R ; R = Us . find_next ( R ) ) { if ( UseC [ R ] == <NUM_LIT> ) continue ; All0 = false ; break ; } Accept = All0 ; } else if ( SelectHas0 ) { bool Has0 = false ; for ( unsigned R = Us . find_first ( ) ; R ;


<s> bool <ISA_LIT>InsertWaits :: hasOutstandingLGKM ( )


<s> unsigned RegD = MI . getOperand ( OpIdx ) . getReg ( ) ; unsigned Binary = <NUM_LIT> ; bool isSPVFP = false ; RegD = <ISA_LIT>RegisterInfo :: getRegisterNumbering ( RegD , & isSPVFP ) ; if ( ! isSPVFP ) Binary |= RegD << <STR_LIT> ; else { Binary |= ( ( RegD & <NUM_LIT> ) >> <NUM_LIT> ) << <STR_LIT> ; Binary |= ( RegD & <NUM_LIT> ) <<


<s> return __builtin_mve_vrhaddq_m_sv4si ( __arm_vuninitializedq_s32 ( ) , __a ,


<s> SDValue Src = Op . getOperand ( <NUM_LIT> ) ; SDValue VL = Op . getOperand ( <NUM_LIT> ) ; MVT ContainerVT = VT ; if ( VT . isFixedLengthVector ( ) ) { ContainerVT = getContainerForFixedLengthVector ( VT ) ; MVT SrcVT = <STR_LIT> ( <STR_LIT> , ContainerVT . getVectorElementCount ( ) ) ; Src = convertToScalableVector ( SrcVT , Src , DAG , Subtarget ) ; } MVT XLenVT = Subtarget . getXLenVT ( ) ; SDValue Zero = DAG . getConstant ( <NUM_LIT> , DL , XLenVT ) ; SDValue ZeroSplat = DAG . getNode ( <STR_LIT> , DL , ContainerVT , DAG . getUNDEF ( ContainerVT ) , Zero , VL ) ; SDValue SplatValue = DAG . getConstant ( Op . getOpcode ( ) == <STR_LIT> ? <NUM_LIT> : - <NUM_LIT> , DL , XLenVT ) ; SDValue Splat = DAG . getNode ( <STR_LIT> , DL , ContainerVT , DAG . getUNDEF ( ContainerVT ) , SplatValue , VL ) ; SDValue Result = DAG . getNode ( <STR_LIT> , DL , ContainerVT , Src , Splat , ZeroSplat , VL ) ; if ( ! VT . isFixedLengthVector ( ) )


<s> return DAG . getStore ( Op . getOperand ( <NUM_LIT> ) , dl , FR , Op . getOperand ( <NUM_LIT> ) , MachinePointerInfo ( SV ) ) ; } SDValue ArgGPR = DAG . getConstant ( FuncInfo -> getVarArgsNumGPR ( ) , dl , <STR_LIT> ) ; SDValue ArgFPR = DAG . getConstant ( FuncInfo -> getVarArgsNumFPR ( ) , dl , <STR_LIT> ) ; SDValue StackOffsetFI = DAG . getFrameIndex ( FuncInfo -> getVarArgsStackOffset ( ) , PtrVT ) ; SDValue FR = DAG . getFrameIndex ( FuncInfo -> getVarArgsFrameIndex ( ) , PtrVT ) ; uint64_t FrameOffset = PtrVT . getSizeInBits ( ) / <NUM_LIT> ; SDValue ConstFrameOffset = DAG . getConstant ( FrameOffset , dl , PtrVT ) ; uint64_t StackOffset = PtrVT . getSizeInBits ( ) / <NUM_LIT> - <NUM_LIT> ; SDValue ConstStackOffset = DAG . getConstant ( StackOffset , dl ,


<s> static bool isFullyRelaxed ( const MCRelaxableFragment & RF ) { auto & Inst = RF . getInst ( ) ; auto & STI = * RF . getSubtargetInfo ( ) ; bool Is16BitMode = STI . getFeatureBits ( ) [ <STR_LIT> ] ; return getRelaxedOpcode ( Inst , Is16BitMode )


<s> uint64_t SrcExtra = fieldFromInstruction ( insn , <ISA_LIT>II :: LdSrcBStart , <ISA_LIT>II :: LdSrcBSize ) ; uint64_t Dest = fieldFromInstruction ( insn , <ISA_LIT>II :: LdDestStart , <ISA_LIT>II :: LdDestSize ) ; uint64_t Switches = fieldFromInstruction ( insn , <ISA_LIT>II :: LdSwitchesStart , <ISA_LIT>II :: LdSwitchesSize ) ; uint64_t Predicate = fieldFromInstruction ( insn , <ISA_LIT>II :: LdPredicateStart , <ISA_LIT>II :: LdPredicateSize ) ; bool Polarity = ( bool ) fieldFromInstruction ( insn , <ISA_LIT>II :: LdPolarityBit , <NUM_LIT> ) ; assert ( Opcode == <ISA_LIT>II :: LOOKUP || Opcode == <ISA_LIT>II :: LOOKUP_1C || Opcode == <ISA_LIT>II :: LOOKUP_2C ) ; if ( Opcode == <ISA_LIT>II :: LOOKUP_1C || Opcode == <ISA_LIT>II :: LOOKUP ) { if ( DecodeVRFRegisterClass ( Inst , Dest , Address , Decoder ) == MCDisassembler ::


<s> static bool rs6000_return_in_memory ( const_tree type , const_tree fntype ATTRIBUTE_UNUSED ) { if ( TARGET_MACHO && rs6000_darwin64_abi && TREE_CODE ( type ) == RECORD_TYPE && int_size_in_bytes ( type ) > <NUM_LIT> ) { CUMULATIVE_ARGS valcum ; rtx valret ; valcum . words = <NUM_LIT> ; valcum . fregno = FP_ARG_MIN_REG ; valcum . vregno = ALTIVEC_ARG_MIN_REG ; valret = rs6000_darwin64_record_arg ( & valcum , type , true , true ) ; if ( valret ) return false ; } if ( rs6000_discover_homogeneous_aggregate ( TYPE_MODE ( type ) , type , NULL ,


<s> void printf64mem ( const MCInst * MI , unsigned OpNo


<s> auto & DL = I . getModule ( ) -> getDataLayout ( ) ; switch ( Intrinsic ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { Info . opc = <STR_LIT> ; uint64_t NumElts = DL . getTypeSizeInBits ( I . getType ( ) ) / <NUM_LIT> ; Info . memVT = EVT :: getVectorVT ( I . getType ( ) -> getContext ( ) , <STR_LIT> , NumElts ) ; Info . ptrVal = I . getArgOperand ( I . getNumArgOperands ( ) - <NUM_LIT> ) ; Info . offset = <NUM_LIT> ; Info . align . reset ( ) ; Info . flags = MachineMemOperand :: MOLoad ; return true ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { Info . opc = <STR_LIT> ; unsigned NumElts = <NUM_LIT> ; for ( unsigned ArgI = <NUM_LIT> , ArgE = I . getNumArgOperands ( ) ; ArgI < ArgE ; ++ ArgI ) { Type * ArgTy = I . getArgOperand ( ArgI ) -> getType ( ) ; if ( ! ArgTy -> isVectorTy ( ) ) break ; NumElts += DL . getTypeSizeInBits ( ArgTy ) / <NUM_LIT> ; } Info . memVT = EVT :: getVectorVT ( I . getType ( ) -> getContext ( ) , <STR_LIT> , NumElts ) ; Info . ptrVal = I . getArgOperand ( I . getNumArgOperands ( ) - <NUM_LIT> ) ; Info . offset = <NUM_LIT> ; Info . align . reset ( ) ; Info . flags = MachineMemOperand :: MOStore ; return true ; } case <STR_LIT> : case <STR_LIT> : { PointerType * PtrTy = cast < PointerType > ( I . getArgOperand ( <NUM_LIT> ) -> getType ( ) ) ; Info . opc = <STR_LIT> ; Info . memVT = <STR_LIT> ( PtrTy -> getElementType ( ) ) ; Info . ptrVal = I . getArgOperand ( <NUM_LIT> ) ; Info . offset = <NUM_LIT> ; Info . align = MaybeAlign ( DL . getABITypeAlignment ( PtrTy -> getElementType ( ) ) ) ; Info . flags = MachineMemOperand :: MOLoad | MachineMemOperand :: MOVolatile ; return true ; } case <STR_LIT> : case <STR_LIT> : { PointerType * PtrTy = cast < PointerType > ( I .


<s> } } if ( ! TARGET_MMX && ! warnedmmx ) { if ( VECTOR_MODE_P ( mode ) && GET_MODE_SIZE ( mode ) == <NUM_LIT> ) { warnedmmx = true ; warning ( <NUM_LIT> , <STR_LIT> <STR_LIT> ) ; } } } return NULL


<s> if ( ! FS . empty ( ) ) FullFS = ( Twine ( FullFS ) + <STR_LIT> + FS ) . str ( ) ; ParseSubtargetFeatures ( CPU , TuneCPU , FullFS ) ; if ( hasSSE42 ( ) || hasSSE4A ( ) ) IsUAMem16Slow = false ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << <ISA_LIT>SSELevel << <STR_LIT> << <ISA_LIT>3DNowLevel << <STR_LIT> << Has<ISA_LIT>_64 << <STR_LIT> ) ; if ( In64BitMode && ! Has<ISA_LIT>_64 ) report_fatal_error ( <STR_LIT> <STR_LIT> ) ; if ( StackAlignOverride ) stackAlignment =


<s> bool <ISA_LIT>InstrInfo :: isPredicated ( const MachineInstr & MI ) const { int idx = MI . findFirstPredOperandIdx ( ) ; if ( idx < <NUM_LIT> ) return false ; unsigned Reg = MI . getOperand ( idx ) . getReg ( ) ; switch ( Reg ) { default : return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> output_asm_insn ( <STR_LIT> , operands ) ; } else output_asm_insn ( <STR_LIT> , operands ) ; output_asm_insn ( <STR_LIT> , operands ) ; if ( TARGET_16_BIT ) return


<s> LLVM_EXTERNAL_VISIBILITY void LLVMInitialize<ISA_LIT>TargetMC ( ) { RegisterMCAsmInfo < <ISA_LIT>MCAsmInfo > X ( getThe<ISA_LIT>Target ( ) ) ; TargetRegistry :: RegisterMCInstrInfo ( getThe<ISA_LIT>Target ( ) , create<ISA_LIT>MCInstrInfo ) ; TargetRegistry :: RegisterMCRegInfo ( getThe<ISA_LIT>Target ( ) , create<ISA_LIT>MCRegisterInfo ) ; TargetRegistry :: RegisterMCSubtargetInfo ( getThe<ISA_LIT>Target ( ) , create<ISA_LIT>MCSubtargetInfo ) ; TargetRegistry :: RegisterMCInstPrinter ( getThe<ISA_LIT>Target ( ) , create<ISA_LIT>MCInstPrinter ) ; TargetRegistry :: RegisterMCCodeEmitter ( getThe<ISA_LIT>Target ( )


<s> static enum insn_code tilepro_multiply_get_opcode ( const struct tilepro_multiply_insn_seq_entry * entry ) { return tilepro_multiply_insn_seq_decode_opcode [ entry ->


<s> static const uint16_t RegList2 [ ] = { <STR_LIT> , <STR_LIT> } ; if ( unsigned Reg = State . AllocateReg ( RegList1 , RegList2 , <NUM_LIT> ) ) { State . addLoc ( CCValAssign :: getReg ( ValNo , ValVT , Reg , LocVT , LocInfo ) ) ; return false ; } unsigned Offset = State . AllocateStack ( <NUM_LIT>


createGreedyRegisterAllocator ( onlyAllocateSGPRs ) ;


<s> } if ( TARGET_CPU_ZARCH ) { fixed_regs [ BASE_REGNUM ] = <NUM_LIT> ; call_used_regs [ BASE_REGNUM ] = <NUM_LIT> ; fixed_regs [ RETURN_REGNUM ] = <NUM_LIT> ; call_used_regs [ RETURN_REGNUM ] = <NUM_LIT> ; } if ( TARGET_64BIT ) { for ( i = FPR8_REGNUM ; i <= FPR15_REGNUM ; i ++ ) call_used_regs [

i ] = call_really_used_regs [ i ] = <NUM_LIT> ;


<s> Opc = isThumb2 ? <STR_LIT> : <STR_LIT> ; break ; case <STR_LIT> : Opc = isThumb2 ? <STR_LIT> : <STR_LIT> ; break ; } unsigned SrcReg1 = getRegForValue ( I -> getOperand ( <NUM_LIT> ) ) ; if ( SrcReg1 == <NUM_LIT> ) return false ; unsigned SrcReg2 = getRegForValue ( I -> getOperand ( <NUM_LIT> ) ) ; if ( SrcReg2 == <NUM_LIT> ) return false ; unsigned ResultReg = createResultReg ( & <STR_LIT> ) ; SrcReg1 = constrainOperandRegClass ( TII . get ( Opc ) , SrcReg1 , <NUM_LIT> ) ; SrcReg2 = constrainOperandRegClass ( TII . get ( Opc ) , SrcReg2 , <NUM_LIT> ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , ResultReg ) . addReg (


<s> bool <ISA_LIT>RegisterInfo :: spillSGPR ( MachineBasicBlock :: iterator MI , int Index , RegScavenger * RS , bool OnlyToVGPR ) const { MachineBasicBlock * MBB = MI -> getParent ( ) ; MachineFunction * MF = MBB -> getParent ( ) ; <ISA_LIT>MachineFunctionInfo * MFI = MF -> getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; DenseSet < unsigned > SGPRSpillVGPRDefinedSet ; ArrayRef < <ISA_LIT>MachineFunctionInfo :: SpilledReg > VGPRSpills = MFI -> getSGPRToVGPRSpills ( Index ) ; bool SpillToVGPR = ! VGPRSpills . empty ( ) ; if ( OnlyToVGPR && ! SpillToVGPR ) return false ; MachineRegisterInfo & MRI = MF -> getRegInfo ( ) ; const GCNSubtarget & ST = MF -> getSubtarget < GCNSubtarget > ( ) ; const <ISA_LIT>InstrInfo * TII = ST . getInstrInfo ( ) ; unsigned SuperReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; bool IsKill = MI -> getOperand ( <NUM_LIT> ) . isKill ( ) ; const DebugLoc & DL = MI -> getDebugLoc ( ) ; MachineFrameInfo & FrameInfo = MF -> getFrameInfo ( ) ; bool SpillToSMEM = spillSGPRToSMEM ( ) ; if ( SpillToSMEM && OnlyToVGPR ) return false ; assert ( SpillToVGPR || ( SuperReg != MFI -> getStackPtrOffsetReg ( ) && SuperReg != MFI -> getFrameOffsetReg ( ) && SuperReg != MFI -> getScratchWaveOffsetReg ( ) ) ) ; assert ( SuperReg != <STR_LIT> && <STR_LIT> ) ; unsigned OffsetReg = <STR_LIT> ; unsigned M0CopyReg = <STR_LIT> ; if ( SpillToSMEM ) { if ( RS -> isRegUsed ( <STR_LIT> ) ) { M0CopyReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * MBB , MI , DL , TII -> get ( <STR_LIT> ) , M0CopyReg ) . addReg ( <STR_LIT> ) ; } } unsigned ScalarStoreOp ; unsigned EltSize = <NUM_LIT> ; const TargetRegisterClass * RC = getPhysRegClass ( SuperReg ) ; if ( SpillToSMEM && isSGPRClass ( RC )


<s> bool hasLdsDirect ( ) const { return getGeneration ( ) >=


<s> if ( ! C ) return ; int64_t Val = C -> getSExtValue ( ) ; switch ( Constraint [ <NUM_LIT> ] ) { case 'I' : if ( Val > <NUM_LIT> && Val <= <NUM_LIT> ) break ; return ; case 'J' : if ( isInt < <NUM_LIT> > ( Val ) ) break ; return ; case 'K' : if ( Val < - <NUM_LIT> || Val >= <NUM_LIT> ) break ; return ; case 'L' : if ( Val < <NUM_LIT> && Val >= - <NUM_LIT> ) break ; return ; case 'M' : if ( Val < - <NUM_LIT> || Val >= <NUM_LIT> ) break ; return ; case 'N' : if ( Val >= <NUM_LIT> && Val <= <NUM_LIT> ) break ; return ; case 'O' : if ( Val == <NUM_LIT> ) break ; return ; case 'P' : if ( Val >= <NUM_LIT> && Val <= <NUM_LIT> ) break ; return ; default : llvm_unreachable ( <STR_LIT> ) ; } Result = DAG . getTargetConstant ( Val , SDLoc ( Op ) , Op . getValueType ( ) ) ; break ; } default : break ; } } if ( Constraint . size ( ) == <NUM_LIT> ) { switch ( Constraint [ <NUM_LIT> ] ) { case 'C' : switch ( Constraint [ <NUM_LIT> ] ) { case '0' : case 'i' : case 'j' : { auto * C = dyn_cast < ConstantSDNode > ( Op ) ; if ( ! C ) break ; int64_t Val = C -> getSExtValue ( ) ; switch ( Constraint [ <NUM_LIT> ] ) { case '0' : if ( ! Val ) break ; return ; case 'i'


<s> if ( ST -> hasVInstructions ( ) ) return <NUM_LIT> ; return


<s> else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) BuildMI ( MBB , MI , DL , get (

<STR_LIT> ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ;


<s> } if ( IsPICCall && ! InternalLinkage ) { unsigned GPReg = <STR_LIT> ; EVT Ty = <STR_LIT> ; RegsToPass . push_back ( std :: make_pair ( GPReg , getGlobalReg ( CLI . DAG , Ty ) ) ) ; } SDValue InFlag ; for ( unsigned i = <NUM_LIT> , e = RegsToPass . size ( ) ; i != e ; ++ i ) { Chain = CLI . DAG . getCopyToReg ( Chain , CLI . DL , RegsToPass [ i ] . first ,


<s> if ( ! cfun ) return ix86_abi ; return cfun -> machine


<s> MCAsmParser & Parser = getParser ( ) ; const AsmToken & Tok = Parser . getTok ( ) ; SMLoc S = Tok . getLoc ( ) ; if ( Tok . isNot ( AsmToken :: Identifier ) ) { Error ( S , <STR_LIT> ) ; return MatchOperand_ParseFail ; } int Val = StringSwitch < int > ( Tok . getString ( ) . lower ( ) ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Default ( - <NUM_LIT> ) ; Parser . Lex ( ) ; if ( Val == - <NUM_LIT> ) { Error ( S , <STR_LIT> ) ; return MatchOperand_ParseFail ; } Operands . push_back ( <ISA_LIT>Operand :: CreateImm ( MCConstantExpr :: Create ( Val , getContext ( ) ) , S ,


<s> reverseBranchCondition ( SmallVectorImpl < MachineOperand > & Cond ) const { assert ( Cond . size ( ) == <NUM_LIT> && <STR_LIT> ) ; if ( Cond [ <NUM_LIT> ] . getReg ( ) == <STR_LIT> || Cond [ <NUM_LIT> ] . getReg ( ) == <STR_LIT> ) Cond [ <NUM_LIT> ] . setImm ( Cond [ <NUM_LIT> ] . getImm ( ) == <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ) ; else Cond [ <NUM_LIT> ] . setImm ( <STR_LIT> ( ( <STR_LIT> ) Cond [ <NUM_LIT> ] . getImm ( ) ) ) ; return false


<s> return ( __m512d ) __builtin_ia32_divpd512_mask ( ( __v8df ) __M , ( __v8df ) __V , ( __v8df ) _mm512_undefined_pd ( ) , (


<s> } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { NewMIs . push_back ( addFrameReference ( BuildMI ( MF , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) , FrameIdx ) ) ; return true ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { NewMIs . push_back ( addFrameReference ( BuildMI ( MF , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) , FrameIdx ) ) ; return true ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { NewMIs . push_back ( addFrameReference ( BuildMI ( MF , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) , FrameIdx ) ) ; NonRI = true ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { unsigned Op = Subtarget . hasP9Vector ( ) ? <STR_LIT> : <STR_LIT> ; NewMIs . push_back ( addFrameReference ( BuildMI ( MF , DL , get ( Op ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) , FrameIdx ) ) ; NonRI = true ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { unsigned Opc = Subtarget . hasP9Vector ( ) ? <STR_LIT> : <STR_LIT> ; NewMIs . push_back ( addFrameReference ( BuildMI ( MF , DL , get ( Opc ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) , FrameIdx ) ) ; NonRI = true ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { unsigned Opc = Subtarget . hasP9Vector ( ) ? <STR_LIT> : <STR_LIT> ; NewMIs . push_back ( addFrameReference ( BuildMI ( MF , DL , get ( Opc ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) , FrameIdx ) ) ; NonRI = true ; } else if ( <STR_LIT> . hasSubClassEq ( RC )


<s> int param = N2FPU_N ( fpu_insn_index ) ; if ( <NUM_LIT> <= param && param <= <NUM_LIT> ) nios2_register_custom_code ( param , CCS_FPU , fpu_insn_index ) ; else if ( param != - <NUM_LIT> ) error ( <STR_LIT> , N2FPU_NAME ( fpu_insn_index )


<s> bool iss3_6Imm ( ) const { return CheckImmRange ( <NUM_LIT> , <NUM_LIT> , true , false


<s> } else if ( GET_CODE ( x ) == PLUS && ( ( REG_P ( gp = XEXP ( x , <NUM_LIT> ) ) && REGNO ( gp ) == PIC_OFFSET_TABLE_REGNUM ) || ( GET_CODE ( gp ) == CONST && GET_CODE ( u = XEXP ( gp , <NUM_LIT> ) ) == UNSPEC && XINT ( u , <NUM_LIT> ) == ARC_UNSPEC_GOT && GET_CODE ( XVECEXP ( u , <NUM_LIT> , <NUM_LIT> ) ) == SYMBOL_REF && ! strcmp ( XSTR ( XVECEXP ( u , <NUM_LIT> , <NUM_LIT> ) , <NUM_LIT> ) , <STR_LIT> ) ) ) && GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == CONST && GET_CODE ( u = XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) ) == UNSPEC && XINT ( u , <NUM_LIT> ) == ARC_UNSPEC_GOTOFF ) return XVECEXP ( u , <NUM_LIT> , <NUM_LIT> ) ; else if ( GET_CODE ( x ) == PLUS && GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == PLUS && ( ( REG_P ( gp = XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) ) && REGNO ( gp ) == PIC_OFFSET_TABLE_REGNUM ) || ( GET_CODE ( gp ) == CONST && GET_CODE ( u = XEXP ( gp , <NUM_LIT> ) ) == UNSPEC && XINT ( u , <NUM_LIT> ) == ARC_UNSPEC_GOT && GET_CODE ( XVECEXP ( u , <NUM_LIT> , <NUM_LIT> ) ) == SYMBOL_REF && ! strcmp ( XSTR ( XVECEXP ( u , <NUM_LIT> , <NUM_LIT> ) , <NUM_LIT> ) , <STR_LIT> ) ) ) && GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == CONST && GET_CODE ( u = XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) ) == UNSPEC && XINT ( u , <NUM_LIT> ) == ARC_UNSPEC_GOTOFF ) return gen_rtx_PLUS ( GET_MODE ( x ) , XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) , XVECEXP ( u , <NUM_LIT> , <NUM_LIT> ) ) ; else if ( GET_CODE ( x ) == PLUS && ( u = arc_delegitimize_address_0 ( XEXP ( x , <NUM_LIT> ) ) ) ) return gen_rtx_PLUS ( GET_MODE ( x )


<s> MachineFunctionPass :: getAnalysisUsage ( AU ) ; AU . addRequired < MachineDominatorTree > (


<s> bool FoldAsMAD = tryAddToFoldList ( FoldList , MI , OpNo , OpToFold , TII ) ; if ( FoldAsMAD ) { MI -> untieRegOperand ( OpNo ) ; return true ; } MI -> setDesc ( TII -> get ( Opc ) ) ; } if ( Opc == <STR_LIT> && OpToFold -> isImm ( ) ) { MI -> setDesc ( TII -> get ( <STR_LIT> ) ) ; FoldList . push_back ( FoldCandidate ( MI , OpNo , OpToFold ) ) ; return true ; } if ( isUseMIInFoldList ( FoldList , MI ) ) return false ; unsigned CommuteOpNo = OpNo ; unsigned CommuteIdx0 = TargetInstrInfo :: CommuteAnyOperandIndex ; unsigned CommuteIdx1 = TargetInstrInfo :: CommuteAnyOperandIndex ; bool CanCommute = TII -> findCommutedOpIndices ( * MI , CommuteIdx0 , CommuteIdx1 ) ; if ( CanCommute ) { if ( CommuteIdx0 == OpNo ) CommuteOpNo = CommuteIdx1 ; else if ( CommuteIdx1 == OpNo ) CommuteOpNo = CommuteIdx0 ; } if ( CanCommute && ( ! MI -> getOperand ( CommuteIdx0 ) . isReg ( ) || ! MI -> getOperand ( CommuteIdx1 ) . isReg ( ) ) ) return false ; if ( ! CanCommute || ! TII -> commuteInstruction ( * MI , false , CommuteIdx0 , CommuteIdx1 ) ) return false ; if ( ! TII -> isOperandLegal ( *


<s> case <STR_LIT> : { unsigned Reg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , Reg ) . addReg ( Reg , RegState :: Undef ) . addReg ( Reg , RegState :: Undef ) ; MBB . erase ( MI ) ; return true ; } case <STR_LIT> : { unsigned DstReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Src1Reg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Src2Reg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Src1SubHi = TRI . getSubReg ( Src1Reg , <STR_LIT> ) ; unsigned Src1SubLo = TRI . getSubReg ( Src1Reg , <STR_LIT> ) ; unsigned Src2SubHi = TRI . getSubReg ( Src2Reg , <STR_LIT> ) ; unsigned Src2SubLo = TRI . getSubReg ( Src2Reg , <STR_LIT> ) ; BuildMI ( MBB , MI , MI -> getDebugLoc ( ) , get ( <STR_LIT> ) , TRI . getSubReg ( DstReg , <STR_LIT> ) ) . addReg ( Src1SubHi ) . addReg ( Src2SubHi ) ; BuildMI ( MBB , MI , MI -> getDebugLoc ( ) , get ( <STR_LIT> ) , TRI . getSubReg ( DstReg , <STR_LIT>

) ) . addReg ( Src1SubLo ) . addReg ( Src2SubLo ) ;


<s> const char * abi ; if ( TARGET_FPU ) abi = <STR_LIT> ; else abi = <STR_LIT> ; return build_string_literal ( strlen ( abi ) + <NUM_LIT> ,


<s> bool OptSize = Attr . hasAttribute ( AttributeList :: FunctionIndex , Attribute :: MinSize ) ; return OptSize && ! VT


<s> getMatchingCondBranchOpcode ( int Opc , bool invertPredicate ) const { enum <STR_LIT> inPredSense ; inPredSense = invertPredicate ? <STR_LIT> : <STR_LIT> ; int CondOpcode = <STR_LIT> ( Opc , inPredSense ) ; if ( CondOpcode >= <NUM_LIT> ) return CondOpcode ; switch ( Opc


<s> case CONST_INT : if ( outer_code == SET ) { if ( satisfies_constraint_Is05 ( x ) ) * total = COSTS_N_INSNS ( <NUM_LIT> ) - <NUM_LIT> ; else if ( satisfies_constraint_Is20 ( x ) ) * total = COSTS_N_INSNS ( <NUM_LIT> ) ; else * total = COSTS_N_INSNS ( <NUM_LIT> ) ; } else if ( outer_code == PLUS || outer_code == MINUS ) { if ( satisfies_constraint_Iu05 ( x ) ) * total = COSTS_N_INSNS ( <NUM_LIT> ) - <NUM_LIT> ; else * total = COSTS_N_INSNS ( <NUM_LIT> ) ; } else if ( outer_code == ASHIFT ) { if ( satisfies_constraint_Iu03 ( x ) ) * total = COSTS_N_INSNS ( <NUM_LIT> ) - <NUM_LIT> ; else * total = COSTS_N_INSNS ( <NUM_LIT> ) ; } else if ( outer_code == ASHIFTRT || outer_code == LSHIFTRT ) { if ( satisfies_constraint_Iu05 ( x ) ) * total = COSTS_N_INSNS ( <NUM_LIT> ) - <NUM_LIT> ; else * total = COSTS_N_INSNS ( <NUM_LIT> ) ; } else { * total = COSTS_N_INSNS ( <NUM_LIT> ) ; } break ; case CONST_DOUBLE : * total = COSTS_N_INSNS ( <NUM_LIT>


<s> unsigned CondReg = getRegForValue ( Cond ) ; if ( CondReg == <NUM_LIT> ) return false ; bool CondIsKill = hasTrivialKill ( Cond ) ; if ( MRI . getRegClass ( CondReg ) == & <STR_LIT> ) { unsigned KCondReg = CondReg ; CondReg = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: COPY ) , CondReg ) . addReg ( KCondReg , getKillRegState ( CondIsKill ) ) ; CondReg = fastEmitInst_extractsubreg ( <STR_LIT> , CondReg , true , <STR_LIT> ) ; } BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) ) . addReg ( CondReg , getKillRegState ( CondIsKill ) ) . addImm ( <NUM_LIT> ) ; } const Value * LHS = I -> getOperand ( <NUM_LIT> ) ; const Value * RHS = I -> getOperand ( <NUM_LIT> ) ; unsigned LHSReg = getRegForValue ( LHS ) ; bool LHSIsKill = hasTrivialKill ( LHS ) ; unsigned RHSReg = getRegForValue ( RHS ) ; bool RHSIsKill = hasTrivialKill ( RHS ) ; if ( ! LHSReg || ! RHSReg ) return false ; const TargetRegisterClass * RC = TLI . getRegClassFor ( RetVT ) ; unsigned ResultReg = fastEmitInst_rri ( Opc , RC , RHSReg , RHSIsKill , LHSReg , LHSIsKill , CC ) ; updateValueMap ( I , ResultReg )


<s> const TargetInstrInfo * TII = getTargetMachine ( ) . getSubtargetImpl ( ) -> getInstrInfo ( ) ; unsigned CC = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned regX = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; int64_t Imm = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned SltOpc = <ISA_LIT>16WhichOp8uOr16simm ( SltiOpc , SltiXOpc , Imm ) ; BuildMI ( * BB , MI , MI -> getDebugLoc ( ) , TII -> get ( SltOpc ) ) . addReg ( regX ) . addImm ( Imm ) ; BuildMI ( * BB , MI , MI -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , CC ) . addReg ( <STR_LIT> ) ; MI -> eraseFromParent (


<s> NewC . ICmpType = <STR_LIT> ; } if ( ! MaskVal ) return ; unsigned BitSize = NewC . Op0 . getValueSizeInBits ( ) ; unsigned NewCCMask , ShiftVal ; if ( NewC . ICmpType != <STR_LIT> && NewC . Op0 . getOpcode ( ) == <STR_LIT> && isSimpleShift ( NewC . Op0 , ShiftVal ) && ( MaskVal >> ShiftVal != <NUM_LIT> ) && ( ( CmpVal >> ShiftVal ) << ShiftVal ) == CmpVal && ( NewCCMask = getTestUnderMaskCond ( BitSize , NewC . CCMask , MaskVal >> ShiftVal , CmpVal >> ShiftVal , <STR_LIT> ) ) ) { NewC . Op0 = NewC . Op0 . getOperand ( <NUM_LIT> ) ; MaskVal >>= ShiftVal ; } else if ( NewC . ICmpType != <STR_LIT> && NewC . Op0 . getOpcode ( ) == <STR_LIT> && isSimpleShift ( NewC . Op0 , ShiftVal ) && ( MaskVal << ShiftVal != <NUM_LIT> ) && ( ( CmpVal << ShiftVal ) >> ShiftVal ) == CmpVal && ( NewCCMask = getTestUnderMaskCond ( BitSize , NewC . CCMask , MaskVal << ShiftVal , CmpVal << ShiftVal , <STR_LIT> ) ) ) { NewC . Op0 = NewC . Op0 . getOperand ( <NUM_LIT> ) ; MaskVal <<= ShiftVal ; } else


<s> bool <ISA_LIT>TTIImpl :: isLegalToInferAttributeForFunction ( Function * F ) const { if ( F -> isDeclaration ( ) && ! F -> hasFnAttribute ( ( Attribute :: OptimizeNone ) ) && F -> getName ( ) == <STR_LIT> ) return true ; return


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> rtx memt = assign_stack_temp ( TImode , <NUM_LIT> ) ; emit_move_insn ( memt , SUBREG_REG ( in ) ) ; return adjust_address ( memt , mode , <NUM_LIT> ) ; } else if ( force && GET_CODE ( in ) == REG ) { rtx memx = assign_stack_temp ( mode


<s> bool isITBlockFull ( ) { return inITBlock ( ) && ( ITState . Mask


<s> const MCFixupKindInfo & getFixupKindInfo ( MCFixupKind Kind ) const { const static MCFixupKindInfo Infos [ <STR_LIT> ] = { { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel | MCFixupKindInfo :: FKF_IsAlignedDownTo32Bits } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel | MCFixupKindInfo :: FKF_IsAlignedDownTo32Bits } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel | MCFixupKindInfo :: FKF_IsAlignedDownTo32Bits } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel | MCFixupKindInfo :: FKF_IsAlignedDownTo32Bits } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel | MCFixupKindInfo :: FKF_IsAlignedDownTo32Bits } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ,


<s> MCAsmBackend * llvm :: create<ISA_LIT>_32AsmBackend ( const Target & T , const MCRegisterInfo & MRI , const Triple & TheTriple , StringRef CPU ) { if ( TheTriple . isOSBinFormatMachO ( ) ) return new Darwin<ISA_LIT>_32AsmBackend ( T , MRI , CPU ) ; if ( TheTriple . isOSWindows ( ) && ! TheTriple . isOSBinFormatELF ( ) ) return new Windows<ISA_LIT>AsmBackend ( T , false , CPU ) ; uint8_t OSABI = MCELFObjectTargetWriter :: getOSABI ( TheTriple . getOS ( ) ) ; if ( TheTriple . isOSIAMCU ( ) ) return new ELF<ISA_LIT>_IAMCUAsmBackend ( T ,


<s> if ( User && ! ( User -> getOpcode ( ) == Instruction :: FSub || User -> getOpcode ( ) == Instruction :: FAdd ) ) return true ; const TargetOptions & Options = getTargetMachine ( ) . Options ; const Function * F = I -> getFunction ( ) ; const DataLayout & DL = F -> getParent ( ) -> getDataLayout ( ) ; Type * Ty = User -> getOperand ( <NUM_LIT> ) -> getType ( ) ; return ! ( isFMAFasterThanFMulAndFAdd ( * F , Ty ) && isOperationLegalOrCustom ( <STR_LIT> , getValueType ( DL , Ty ) ) && ( Options . AllowFPOpFusion == FPOpFusion :: Fast || Options


<s> else if ( DIGV . isLocalToUnit ( ) ) ClassNo = <STR_LIT> ; else ClassNo = <STR_LIT> ; return ClassNo


<s> break ; } case 'Q' : if ( VT == <STR_LIT> || VT == <STR_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; if ( VT == <STR_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; if ( VT == <STR_LIT> || VT == <STR_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; if ( VT == <STR_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; break ; case 'r' : case 'l' : if ( VT == <STR_LIT> || VT == <STR_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; if ( VT == <STR_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; if ( VT == <STR_LIT> || VT == <STR_LIT> || ! Subtarget -> is64Bit ( ) ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; case 'R' : if ( VT == <STR_LIT> || VT == <STR_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; if ( VT == <STR_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; if ( VT == <STR_LIT> || ! Subtarget -> is64Bit ( ) ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; case 'f' : if ( VT == <STR_LIT> && ! isScalarFPTypeInSSEReg ( VT ) ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; if ( VT == <STR_LIT> && ! isScalarFPTypeInSSEReg ( VT ) ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; case 'y' : if ( ! Subtarget -> hasMMX ( ) ) break ; return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; case 'Y' : if ( ! Subtarget -> hasSSE2 ( ) ) break ; case 'x' : if ( ! Subtarget -> hasSSE1 ( ) ) break ; switch ( VT . SimpleTy ) { default : break ; case <STR_LIT> : case <STR_LIT> : return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; } break ; } } std :: pair < unsigned , const TargetRegisterClass


<s> Error ( S , <STR_LIT> ) ; return MatchOperand_ParseFail ; } Parser . Lex ( ) ; if ( Parser . getTok ( ) . isNot ( AsmToken :: Hash ) && Parser . getTok ( ) . isNot ( AsmToken :: Dollar ) ) { Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ; } Parser . Lex ( ) ; SMLoc ExLoc = Parser . getTok ( ) . getLoc ( ) ; const MCExpr * ShiftAmount ; SMLoc EndLoc ; if ( getParser ( ) . parseExpression ( ShiftAmount , EndLoc ) ) { Error ( ExLoc , <STR_LIT> ) ; return MatchOperand_ParseFail ; } const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( ShiftAmount ) ; if ( ! CE ) { Error ( ExLoc , <STR_LIT> ) ; return MatchOperand_ParseFail ; } int64_t Val = CE -> getValue ( ) ; if ( isASR ) { if ( Val < <NUM_LIT> || Val > <NUM_LIT> ) { Error ( ExLoc ,


<s> void <ISA_LIT>InstPrinter :: printLogicalImmOperand ( const MCInst * MI , unsigned OpNum , raw_ostream & O ) { const MCOperand & MO = MI -> getOperand ( OpNum ) ; uint64_t Val ; A64Imms :: isLogicalImmBits ( RegWidth , MO . getImm ( ) , Val ) ; O << <STR_LIT> ; O . write_hex (


<s> enum machine_mode valmode ; if ( AGGREGATE_TYPE_P ( valtype ) || TREE_CODE ( valtype ) == COMPLEX_TYPE || TREE_CODE ( valtype ) == VECTOR_TYPE ) { if ( TARGET_64BIT ) { rtx loc [ <NUM_LIT> ] ; int i , offset = <NUM_LIT> ; int ub = int_size_in_bytes ( valtype ) <= UNITS_PER_WORD ? <NUM_LIT> : <NUM_LIT> ; for ( i = <NUM_LIT> ; i < ub ; i ++ ) { loc [ i ] = gen_rtx_EXPR_LIST ( VOIDmode , gen_rtx_REG ( DImode , <NUM_LIT> + i ) , GEN_INT ( offset ) ) ; offset += <NUM_LIT> ; } return gen_rtx_PARALLEL ( BLKmode , gen_rtvec_v ( ub , loc ) ) ; } else if ( int_size_in_bytes ( valtype ) > UNITS_PER_WORD ) { rtx loc = gen_rtx_EXPR_LIST ( VOIDmode , gen_rtx_REG ( DImode , <NUM_LIT> ) , const0_rtx ) ; return gen_rtx_PARALLEL ( BLKmode , gen_rtvec ( <NUM_LIT> , loc ) ) ; } } if ( ( INTEGRAL_TYPE_P ( valtype ) && TYPE_PRECISION ( valtype ) < BITS_PER_WORD ) || POINTER_TYPE_P ( valtype )


<s> return ( __m128d ) __builtin_ia32_divsd_mask_round ( ( __v2df ) __A , ( __v2df ) __B , (


<s> SO = <NUM_LIT> << <NUM_LIT> ; SR = <NUM_LIT> << <NUM_LIT> ; SW = <NUM_LIT> << <NUM_LIT> ; } unsigned pred = PI | PO | PR | PW ; unsigned succ = SI | SO | SR | SW ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) , DAG . getConstant ( pred , DL , Subtarget . isRV64 ( ) ? <STR_LIT> : <STR_LIT> ) , DAG . getConstant ( succ , DL

, Subtarget . isRV64 ( ) ? <STR_LIT> : <STR_LIT> ) ) ;


<s> const TargetRegisterInfo * RI = MF . getSubtarget ( ) . getRegisterInfo ( ) ; const std :: vector < CalleeSavedInfo > & CSI = MFI . getCalleeSavedInfo ( ) ; int MinCSFI = <NUM_LIT> ; int MaxCSFI = - <NUM_LIT> ; int Offset = MFI . getObjectOffset ( FI ) - getOffsetOfLocalArea ( ) + MFI . getOffsetAdjustment ( ) ; if ( CSI . size ( ) ) { MinCSFI = CSI [ <NUM_LIT> ] . getFrameIdx ( ) ; MaxCSFI = CSI [ CSI . size ( ) - <NUM_LIT> ] . getFrameIdx ( ) ; } FrameReg = RI -> getFrameRegister ( MF ) ; if ( ( FI >= MinCSFI && FI <= MaxCSFI ) || ! hasFP ( MF ) ) { FrameReg = <STR_LIT> ; Offset += MF . getFrameInfo ( ) . getStackSize ( ) ; } return