<s> mbb1 -> insertAfter ( bundleWith , inst ) ; } } ; auto moveNextInstruction = [ & ] ( unsigned movedInstructions ) { auto mbb1next = mbb1 -> instr_begin ( ) ; for ( int i = <NUM_LIT> ; i < movedInstructions ; i ++ ) { mbb1next ++ ; mbb1next ++ ; } moveInstruction ( mbb1next ) ; } ; int nrMbb1Instrs = numberOfInstructions ( mbb1 ) ; if ( nrMbb1Instrs > numberOfInstructions ( mbb2 ) ) { for ( auto movedInstructions = <NUM_LIT> ; mbb2 -> instr_begin ( ) != mbb2 -> getFirstInstrTerminator ( ) ; movedInstructions ++ ) { moveNextInstruction ( movedInstructions ) ; } } else { for ( auto movedInstructions = <NUM_LIT> ; movedInstructions < nrMbb1Instrs ; movedInstructions ++ ) { moveNextInstruction ( movedInstructions ) ; } while ( mbb2 -> instr_begin ( ) != mbb2 -> getFirstInstrTerminator ( ) ) { auto inst = & ( * mbb2 -> instr_begin ( ) ) ; mbb2 -> remove (


<s> int OffsetOpIdx = <STR_LIT> ( MI -> getOpcode ( ) , <STR_LIT> :: addr ) ; int RegOpIdx = OffsetOpIdx + <NUM_LIT> ; int ChanOpIdx = <STR_LIT> ( MI -> getOpcode ( ) , <STR_LIT> :: chan ) ; if ( isRegisterLoad ( * MI ) ) { int DstOpIdx = <STR_LIT> ( MI -> getOpcode ( ) , <STR_LIT> :: dst ) ; unsigned RegIndex = MI -> getOperand ( RegOpIdx ) . getImm ( ) ; unsigned Channel = MI -> getOperand ( ChanOpIdx ) . getImm ( ) ; unsigned Address = calculateIndirectAddress ( RegIndex , Channel ) ; unsigned OffsetReg = MI -> getOperand ( OffsetOpIdx ) . getReg ( ) ; if ( OffsetReg == <STR_LIT> ) { buildMovInstr ( MBB , MI , MI -> getOperand ( DstOpIdx ) . getReg ( ) , getIndirectAddrRegClass ( ) -> getRegister ( Address ) ) ; } else { buildIndirectRead ( MBB , MI , MI -> getOperand ( DstOpIdx ) . getReg ( ) , Address , OffsetReg ) ; } } else if ( isRegisterStore ( * MI ) ) { int ValOpIdx = <STR_LIT> ( MI -> getOpcode ( ) , <STR_LIT> :: val ) ; unsigned RegIndex = MI -> getOperand ( RegOpIdx ) . getImm ( ) ; unsigned Channel = MI -> getOperand ( ChanOpIdx ) . getImm ( ) ; unsigned Address = calculateIndirectAddress ( RegIndex , Channel


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( Val . getOperand ( <NUM_LIT> ) . getValueType ( ) . isInteger ( ) ) { VTSDNode * T = cast < VTSDNode > ( Val . getOperand ( <NUM_LIT> ) ) ; if ( T -> getVT ( ) . getSizeInBits ( ) == NumBits ) { Src = Val . getOperand ( <NUM_LIT> ) ; return true ; } } break ; case <STR_LIT> : { uint64_t Mask = ( <NUM_LIT> << NumBits ) - <NUM_LIT> ; if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Val . getOperand ( <NUM_LIT> ) ) ) { if ( C -> getZExtValue ( ) == Mask ) { Src = Val . getOperand ( <NUM_LIT> ) ; return true ; } } if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Val . getOperand ( <NUM_LIT> ) ) ) { if ( C -> getZExtValue ( ) == Mask ) { Src = Val . getOperand ( <NUM_LIT> ) ; return true ; } } break ; } case <STR_LIT> : case <STR_LIT> : { uint64_t Mask = ( <NUM_LIT> << NumBits ) - <NUM_LIT> ; if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Val . getOperand ( <NUM_LIT> ) ) ) { if ( ( C -> getZExtValue ( ) & Mask ) == <NUM_LIT> ) { Src = Val . getOperand ( <NUM_LIT> ) ; return true ; } } if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Val . getOperand ( <NUM_LIT> ) ) ) { if ( ( C -> getZExtValue ( ) & Mask ) == <NUM_LIT> ) { Src = Val . getOperand


<s> MachineBasicBlock :: iterator StoreI ; if ( findMatchingStore ( MBBI , LdStLimit , StoreI ) ) { ++ NumLoadsFromStoresPromoted ; MBBI = promoteLoadFromStore ( MBBI ,


<s> static void xstormy16_function_arg_advance ( cumulative_args_t cum_v , const function_arg_info & arg ) { CUMULATIVE_ARGS * cum = get_cumulative_args


<s> bool <ISA_LIT>PassConfig :: addPreEmitPass


<s> if ( ! isImmWithLSL ( ) ) return false ; if ( ImmWithLSL . ShiftAmount % <NUM_LIT> != <NUM_LIT> ) return false ; if ( ImmWithLSL . ShiftAmount >= RegWidth ) return false ; <ISA_LIT>MCExpr :: VariantKind Modifier ; if ( isNonConstantExpr ( ImmWithLSL . Val ,


<s> SDValue <ISA_LIT>TargetLowering :: LowerJumpTable ( SDValue Op , SelectionDAG & DAG ) const { JumpTableSDNode * N = cast < JumpTableSDNode


<s> if ( I -> getOpcode ( ) == <STR_LIT> ) Amount = - Amount ; const <ISA_LIT>16InstrInfo & TII = * static_cast < const <ISA_LIT>16InstrInfo * > ( STI . getInstrInfo


<s> if ( AluIter -> getNumOperands ( ) != <NUM_LIT> ) return false ; MachineOperand & Dest = AluIter -> getOperand ( <NUM_LIT> ) ; MachineOperand & Op1 = AluIter -> getOperand ( <NUM_LIT> ) ; MachineOperand & Op2 = AluIter -> getOperand ( <NUM_LIT> ) ; if ( ! isSameOperand ( Dest , Base ) || ! isSameOperand ( Dest , Op1 ) ) return false ; if ( Op2 . isImm ( ) ) { if ( Offset . isReg ( ) && Offset . getReg ( ) == <STR_LIT> ) return true ; if ( Offset . isImm ( ) && ( ( Offset . getImm ( ) == <NUM_LIT> && ( ( IsSpls && isInt < <NUM_LIT> > ( Op2 . getImm ( ) ) ) || ( ! IsSpls && isInt < <NUM_LIT> > ( Op2 . getImm ( ) ) ) ) ) || Offset . getImm ( ) == Op2 . getImm ( ) ) ) return true ; } else if ( Op2 . isReg ( ) ) { if ( Offset . isReg ( ) && Op2 . getReg ( ) == Offset . getReg ( ) ) return true ; } else return


<s> SDValue RHS = Op . getOperand ( <NUM_LIT> ) ; SDValue True = Op . getOperand ( <NUM_LIT> ) ; SDValue False = Op . getOperand ( <NUM_LIT> ) ; SDValue CC = Op . getOperand ( <NUM_LIT> ) ; EVT VT = Op . getValueType ( ) ; SDLoc DL ( Op ) ; SDValue MinMax = LowerMinMax ( Op , DAG ) ; if ( MinMax . getNode ( ) ) { return MinMax


<s> const TargetRegisterClass * RC = RI . getRegClass ( RCID ) ; unsigned Opcode = AMDGPU :: V_MOV_B32_e32 ; if ( MO . isReg ( ) ) { Opcode = AMDGPU :: COPY ; } else if ( RI . isSGPRClass ( RC ) ) { Opcode = AMDGPU :: S_MOV_B32 ; } const TargetRegisterClass * VRC = RI . getEquivalentVGPRClass ( RC ) ; if ( RI . getCommonSubClass ( & AMDGPU :: VReg_64RegClass , VRC ) ) { VRC = & AMDGPU :: VReg_64RegClass ; }


<s> assert ( ! isAsynchronousEHPersonality ( classifyEHPersonality ( BB -> getParent ( ) -> getFunction ( ) . getPersonalityFn ( ) ) ) && <STR_LIT> ) ; return BB


<s> MF -> insert ( ++ StoreBB -> getIterator ( ) , DoneBB ) ; BuildMI ( LoadCmpBB , DL , TII -> get ( <STR_LIT> ) ) . addReg ( DestLo . getReg ( ) , RegState :: Define ) . addReg ( DestHi . getReg ( ) , RegState :: Define ) . addReg ( AddrReg ) ; BuildMI ( LoadCmpBB , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( DestLo . getReg ( ) , getKillRegState ( DestLo . isDead ( ) ) ) . addReg ( DesiredLoReg ) . addImm ( <NUM_LIT> ) ; BuildMI ( LoadCmpBB , DL , TII -> get ( <STR_LIT> ) , StatusReg ) . addUse ( <STR_LIT> ) . addUse ( <STR_LIT> ) . addImm ( <STR_LIT> ) ; BuildMI ( LoadCmpBB , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( DestHi . getReg ( ) , getKillRegState ( DestHi . isDead ( ) ) ) . addReg ( DesiredHiReg ) . addImm ( <NUM_LIT> ) ; BuildMI ( LoadCmpBB , DL , TII -> get ( <STR_LIT> ) , StatusReg ) . addUse ( StatusReg , RegState :: Kill ) . addUse ( StatusReg , RegState :: Kill ) . addImm ( <STR_LIT> ) ; BuildMI ( LoadCmpBB , DL , TII -> get ( <STR_LIT> ) ) . addUse ( StatusReg , getKillRegState ( StatusDead ) ) . addMBB ( DoneBB ) ; LoadCmpBB -> addSuccessor ( DoneBB ) ; LoadCmpBB -> addSuccessor ( StoreBB ) ; BuildMI ( StoreBB , DL , TII -> get ( <STR_LIT> ) , StatusReg ) . addReg ( NewLoReg ) . addReg ( NewHiReg ) . addReg ( AddrReg ) ; BuildMI ( StoreBB , DL , TII -> get ( <STR_LIT> ) ) . addReg ( StatusReg , getKillRegState ( StatusDead ) ) . addMBB ( LoadCmpBB ) ; StoreBB -> addSuccessor ( LoadCmpBB ) ; StoreBB -> addSuccessor ( DoneBB ) ; DoneBB -> splice ( DoneBB -> end ( ) , & MBB , MI , MBB . end ( ) ) ; DoneBB -> transferSuccessors ( & MBB ) ; MBB . addSuccessor ( LoadCmpBB ) ; NextMBBI = MBB . end ( ) ; MI . eraseFromParent ( ) ; LivePhysRegs LiveRegs ; computeAndAddLiveIns ( LiveRegs , * DoneBB ) ; computeAndAddLiveIns ( LiveRegs , * StoreBB ) ; computeAndAddLiveIns ( LiveRegs , * LoadCmpBB


<s> <ISA_LIT>LoopPreIncPrep ( <ISA_LIT>TargetMachine & TM ) : FunctionPass ( ID ) , TM ( & TM ) { initialize<ISA_LIT>LoopPreIncPrepPass ( * PassRegistry :: getPassRegistry ( )


<s> static bool CantUseSP ( const MachineFrameInfo & MFI ) { return MFI . hasVarSizedObjects ( )


<s> case <STR_LIT> : return LowerFP_TO_SINT ( Op , DAG ) ; case <STR_LIT> : return LowerFP_TO_UINT ( Op , DAG ) ; case <STR_LIT> : return lowerFP_EXTEND ( Op , DAG ) ; case <STR_LIT> : return LowerFABS ( Op , DAG ) ; case <STR_LIT> : return LowerFNEG ( Op , DAG ) ; case <STR_LIT> : return LowerFCOPYSIGN ( Op , DAG ) ; case <STR_LIT> : return LowerFGETSIGN ( Op , DAG ) ; case <STR_LIT> : return LowerSETCC ( Op , DAG ) ; case <STR_LIT> : return LowerSELECT ( Op , DAG ) ; case <STR_LIT> : return LowerBRCOND ( Op , DAG ) ; case <STR_LIT> : return LowerJumpTable ( Op , DAG ) ; case <STR_LIT> : return LowerVASTART ( Op , DAG ) ; case <STR_LIT> : return LowerVAARG ( Op , DAG ) ; case <STR_LIT> : return LowerVACOPY ( Op , Subtarget , DAG ) ; case <STR_LIT> : return LowerINTRINSIC_WO_CHAIN ( Op , DAG ) ; case <STR_LIT> : return LowerINTRINSIC_W_CHAIN ( Op , DAG ) ; case <STR_LIT> : return LowerRETURNADDR ( Op , DAG ) ; case <STR_LIT> : return LowerFRAMEADDR ( Op , DAG ) ; case <STR_LIT> : return LowerFRAME_TO_ARGS_OFFSET ( Op , DAG ) ; case <STR_LIT> : return LowerDYNAMIC_STACKALLOC ( Op , DAG ) ; case <STR_LIT> : return LowerEH_RETURN ( Op , DAG ) ; case <STR_LIT> : return lowerEH_SJLJ_SETJMP ( Op , DAG ) ; case <STR_LIT> : return lowerEH_SJLJ_LONGJMP ( Op , DAG ) ; case <STR_LIT> : return LowerINIT_TRAMPOLINE ( Op , DAG ) ; case <STR_LIT> : return LowerADJUST_TRAMPOLINE ( Op , DAG ) ; case <STR_LIT> : return LowerFLT_ROUNDS_ ( Op , DAG ) ; case <STR_LIT> : return LowerCTLZ ( Op , DAG ) ; case <STR_LIT> : return LowerCTLZ_ZERO_UNDEF ( Op , DAG ) ; case <STR_LIT> : return LowerCTTZ ( Op , DAG ) ; case <STR_LIT> : return LowerMUL ( Op , Subtarget , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerShift ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerXALUO ( Op , DAG ) ; case <STR_LIT> : return LowerREADCYCLECOUNTER ( Op ,


<s> MachineBasicBlock & B = * MI . getParent ( ) ; assert ( MI . isBundledWithPred ( ) ) ; if ( MI . isBundledWithSucc ( ) ) { MI . clearFlag ( MachineInstr :: BundledSucc ) ; MI . clearFlag ( MachineInstr :: BundledPred ) ; } else { MI . unbundleFromPred ( ) ; } B . splice ( InsertPt , & B , MI . getIterator ( ) ) ; MachineBasicBlock :: const_instr_iterator I = BundleIt . getInstrIterator ( ) ; MachineBasicBlock :: const_instr_iterator E = B . instr_end ( ) ; unsigned Size = <NUM_LIT> ; for ( ++ I ; I != E && I -> isBundledWithPred ( ) ; ++ I ) ++ Size ; if ( Size > <NUM_LIT> ) return BundleIt ; MachineBasicBlock :: iterator NextIt = std :: next ( BundleIt ) ; MachineInstr & SingleI = * BundleIt -> getNextNode


<s> case ENCODING_CW : case ENCODING_CD : case ENCODING_CP : case ENCODING_CO : case ENCODING_CT : debug ( <STR_LIT> ) ; return true ; case ENCODING_IB : case ENCODING_IW : case ENCODING_ID : case ENCODING_IO : case ENCODING_Iv : case ENCODING_Ia : translateImmediate ( mcInst , insn . immediates [ insn . numImmediatesTranslated ++ ] , operand , insn ) ; return false ; case ENCODING_RB : case ENCODING_RW : case ENCODING_RD : case


<s> return gen_rtx_REG ( Pmode , CRX_STRUCT_VALUE_REGNUM


<s> void writeDIArgList ( const DIArgList * N , SmallVectorImpl < uint64_t > & Record , unsigned Abbrev ) { llvm_unreachable (


<s> void <ISA_LIT>MCExpr :: visitUsedExpr ( MCStreamer & Streamer )


<s> void <ISA_LIT>InstrInfo :: movImm32 ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI , const DebugLoc & DL , Register DstReg , uint64_t Val , MachineInstr :: MIFlag Flag ) const { assert ( isInt < <NUM_LIT> > ( Val ) && <STR_LIT> ) ; uint64_t Hi20 = ( ( Val + <NUM_LIT> ) >> <NUM_LIT> ) & <NUM_LIT> ; uint64_t Lo12 = SignExtend64 < <NUM_LIT> > ( Val ) ; BuildMI ( MBB , MBBI , DL , get ( <STR_LIT> ) , DstReg ) . addImm ( Hi20 ) . setMIFlag ( Flag ) ; BuildMI ( MBB , MBBI , DL , get ( <STR_LIT> ) , DstReg ) . addReg ( DstReg , RegState :: Kill ) . addImm ( Lo12


<s> unsigned Size2 = Bytes - Size1 ; SDValue Chain1 = memsetStore ( DAG , DL , Chain , Dst , ByteVal , Size1 , Alignment . value ( ) , DstPtrInfo ) ; if ( Size2 == <NUM_LIT> ) return Chain1 ; Dst = DAG . getNode ( <STR_LIT> , DL , PtrVT , Dst , DAG . getConstant ( Size1 , DL , PtrVT ) ) ; DstPtrInfo = DstPtrInfo . getWithOffset ( Size1 ) ; SDValue Chain2 = memsetStore ( DAG , DL , Chain , Dst , ByteVal , Size2 , std :: min ( ( unsigned ) Alignment . value ( ) , Size1 ) , DstPtrInfo ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Chain1 , Chain2 ) ; } } else { if ( Bytes <= <NUM_LIT> ) { SDValue Chain1 = DAG . getStore ( Chain , DL , Byte , Dst , DstPtrInfo , Alignment ) ; if ( Bytes == <NUM_LIT> ) return Chain1 ; SDValue Dst2 = DAG . getNode ( <STR_LIT> , DL , PtrVT , Dst , DAG . getConstant ( <NUM_LIT> , DL , PtrVT ) ) ; SDValue Chain2 = DAG . getStore ( Chain , DL , Byte , Dst2 , DstPtrInfo . getWithOffset ( <NUM_LIT> ) , Align ( <NUM_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Chain1 , Chain2 ) ; } } assert ( Bytes >= <NUM_LIT> && <STR_LIT> ) ; auto * CByte = dyn_cast < ConstantSDNode > ( Byte ) ; if ( CByte && CByte -> getZExtValue ( ) == <NUM_LIT> ) return emitMemMem ( DAG

, DL , <STR_LIT> , <STR_LIT> , Chain , Dst , Dst , Bytes ) ;


<s> BlockWaitcntBrackets ( ) : WaitAtBeginning ( false ) , RevisitLoop ( false ) , ValidLoop ( false ) , MixedExpTypes ( false ) , LoopRegion ( NULL ) , PostOrder ( <NUM_LIT> ) , Waitcnt ( NULL ) , VgprUB ( <NUM_LIT> ) , SgprUB ( <NUM_LIT> ) { for ( enum InstCounterType T = VM_CNT


<s> void setLastComment ( const std :: string &


<s> if ( mode == TFmode && ! ( TARGET_ARCH64 && TARGET_HARD_QUAD ) ) return <NUM_LIT> ; if ( mode == TImode ) return <NUM_LIT> ; if ( TARGET_ARCH32 && ! optimize && ( mode == DFmode || mode == DImode ) ) return <NUM_LIT> ; } else if ( USE_AS_OFFSETABLE_LO10 && GET_CODE ( rs1 ) == LO_SUM && TARGET_ARCH64 && ! TARGET_CM_MEDMID && RTX_OK_FOR_OLO10_P ( rs2 , mode ) ) { rs2 = NULL ; imm1 = XEXP ( rs1 , <NUM_LIT> ) ; rs1 = XEXP ( rs1 , <NUM_LIT> ) ; if ( ! CONSTANT_P ( imm1 ) || ( GET_CODE ( rs1 ) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL ( rs1 ) ) ) return <NUM_LIT> ; } } else if ( GET_CODE ( addr ) == LO_SUM ) { rs1 = XEXP ( addr , <NUM_LIT> ) ; imm1 = XEXP ( addr , <NUM_LIT> ) ; if ( ! CONSTANT_P ( imm1 ) || ( GET_CODE ( rs1 ) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL ( rs1 ) ) ) return <NUM_LIT> ; if ( mode == TFmode && TARGET_ARCH32 ) return <NUM_LIT> ; if ( reload_in_progress && GET_CODE ( rs1 ) == HIGH && XEXP ( rs1 , <NUM_LIT> ) == imm1 ) return <NUM_LIT> ; } else if ( GET_CODE ( addr ) == CONST_INT && SMALL_INT ( addr ) ) return <NUM_LIT> ; else return <NUM_LIT> ; if ( GET_CODE ( rs1 ) == SUBREG ) rs1 = SUBREG_REG ( rs1 ) ; if ( ! REG_P ( rs1 ) ) return <NUM_LIT> ; if ( rs2 ) { if ( GET_CODE ( rs2 ) == SUBREG ) rs2 = SUBREG_REG ( rs2 ) ; if ( ! REG_P ( rs2 ) ) return <NUM_LIT> ; } if ( strict ) { if ( ! REGNO_OK_FOR_BASE_P ( REGNO ( rs1 ) ) || ( rs2 && ! REGNO_OK_FOR_BASE_P ( REGNO ( rs2 ) ) )


<s> emit<ISA_LIT>Nops ( * OutStreamer , Num , Subtarget ) ; return ; } auto CurSled = OutContext . createTempSymbol ( <STR_LIT> , true ) ; OutStreamer -> emitCodeAlignment ( <NUM_LIT> , & getSubtargetInfo ( ) ) ; OutStreamer -> emitLabel (


<s> static bool readInstruction32 ( ArrayRef < uint8_t > Bytes , uint64_t Address , uint64_t & Size , uint32_t & Insn ) { Size = <NUM_LIT> ; Insn = ( Bytes [ <NUM_LIT> ] << <NUM_LIT> ) | ( Bytes [ <NUM_LIT> ] << <NUM_LIT> ) | ( Bytes

[ <NUM_LIT> ] << <NUM_LIT> ) | ( Bytes [ <NUM_LIT> ] << <NUM_LIT> ) ;


<s> if ( Kind < FirstTargetFixupKind ) return MCAsmBackend :: getFixupKindInfo ( Kind ) ; assert ( unsigned ( Kind - FirstTargetFixupKind ) < getNumFixupKinds ( ) && <STR_LIT> ) ; return Infos [ Kind - FirstTargetFixupKind


<s> if ( REG_P ( operands [ <NUM_LIT> ] ) && symbolic_operand ( operands [ <NUM_LIT> ] , SImode ) ) { if ( push_operand ( operands [ <NUM_LIT> ] , SImode ) ) return <STR_LIT> ; return <STR_LIT> ; } if ( REG_P ( operands [ <NUM_LIT> ] ) && symbolic_operand ( operands [ <NUM_LIT> ] , SImode ) ) { if ( push_operand ( operands [ <NUM_LIT> ] , SImode ) ) return <STR_LIT> ; return <STR_LIT> ; } if ( flag_pic && REG_P ( operands [ <NUM_LIT> ] ) && symbolic_operand ( operands [ <NUM_LIT> ] , SImode ) ) return <STR_LIT> ; if ( flag_pic && ( symbolic_operand ( operands [ <NUM_LIT> ] , SImode ) || symbolic_operand ( operands [ <NUM_LIT> ] , SImode ) ) ) debug_rtx ( insn ) ; return <STR_LIT> ; case E_HImode : if ( rtx_equal_p ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ) { if ( operands [ <NUM_LIT> ] == const1_rtx ) return <STR_LIT> ; if ( operands [ <NUM_LIT> ] == constm1_rtx ) return <STR_LIT> ; if ( CONST_INT_P ( operands [ <NUM_LIT> ] ) && ( unsigned HOST_WIDE_INT ) ( - INTVAL ( operands [ <NUM_LIT> ] ) ) < <NUM_LIT> ) return <STR_LIT> ; return <STR_LIT> ; } if ( rtx_equal_p ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ) return <STR_LIT> ; if ( CONST_INT_P ( operands [ <NUM_LIT> ] ) && ( unsigned HOST_WIDE_INT ) ( - INTVAL ( operands [ <NUM_LIT> ] ) ) < <NUM_LIT> ) return <STR_LIT> ; return <STR_LIT> ; case E_QImode : if ( rtx_equal_p ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ) { if ( operands [ <NUM_LIT> ] == const1_rtx ) return <STR_LIT> ; if ( operands [ <NUM_LIT> ] == constm1_rtx ) return <STR_LIT> ; if ( CONST_INT_P ( operands [ <NUM_LIT> ] ) && ( unsigned HOST_WIDE_INT ) ( - INTVAL ( operands [ <NUM_LIT> ] ) ) < <NUM_LIT> ) return <STR_LIT> ; return <STR_LIT>


<s> DebugLoc dl ; const <ISA_LIT>InstrInfo & TII = * static_cast < const <ISA_LIT>InstrInfo * > ( MF . getSubtarget ( ) . getInstrInfo ( ) ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( <STR_LIT> ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) ) . addReg ( <STR_LIT> ) . addImm


<s> case AMDGPU :: <ISA_LIT>_SPILL_S256_RESTORE : case AMDGPU :: <ISA_LIT>_SPILL_S128_RESTORE : case AMDGPU :: <ISA_LIT>_SPILL_S64_RESTORE : case AMDGPU :: <ISA_LIT>_SPILL_S32_RESTORE : { unsigned NumSubRegs = getNumSubRegsForSpillOp ( MI -> getOpcode ( ) ) ; for ( unsigned i = <NUM_LIT> , e = NumSubRegs ; i < e ; ++ i ) { unsigned SubReg = getPhysRegSubReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) , & AMDGPU :: SGPR_32RegClass , i ) ; bool isM0 = SubReg == AMDGPU :: M0 ; struct <ISA_LIT>MachineFunctionInfo :: SpilledReg Spill = MFI -> getSpilledReg ( MF , Index , i ) ; if ( Spill . VGPR == AMDGPU :: NoRegister ) { LLVMContext & Ctx = MF -> getFunction ( ) -> getContext ( ) ; Ctx . emitError ( <STR_LIT> ) ; } if ( isM0 ) SubReg = RS -> scavengeRegister ( & AMDGPU :: SGPR_32RegClass , MI , <NUM_LIT> ) ; BuildMI ( * MBB , MI , DL , TII -> get ( AMDGPU :: V_READLANE_B32 ) , SubReg ) . addReg ( Spill . VGPR ) . addImm ( Spill . Lane ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) , RegState :: ImplicitDefine ) ; if ( isM0 ) { BuildMI ( * MBB , MI , DL , TII -> get ( AMDGPU :: S_MOV_B32 ) , AMDGPU :: M0 ) . addReg ( SubReg ) ; } } TII -> insertNOPs ( MI , <NUM_LIT> ) ; MI -> eraseFromParent ( ) ; break ; } case AMDGPU :: <ISA_LIT>_SPILL_V512_SAVE : case AMDGPU :: <ISA_LIT>_SPILL_V256_SAVE : case AMDGPU :: <ISA_LIT>_SPILL_V128_SAVE : case AMDGPU :: <ISA_LIT>_SPILL_V96_SAVE : case AMDGPU :: <ISA_LIT>_SPILL_V64_SAVE : case AMDGPU :: <ISA_LIT>_SPILL_V32_SAVE : buildScratchLoadStore ( MI , AMDGPU :: BUFFER_STORE_DWORD_OFFSET , TII -> getNamedOperand ( * MI , AMDGPU :: OpName :: src ) -> getReg ( ) , TII -> getNamedOperand ( * MI , AMDGPU :: OpName :: scratch_rsrc ) -> getReg ( ) , TII -> getNamedOperand ( * MI , AMDGPU :: OpName :: scratch_offset ) -> getReg ( ) , FrameInfo -> getObjectOffset ( Index ) , RS ) ; MI -> eraseFromParent ( ) ; break ; case AMDGPU :: <ISA_LIT>_SPILL_V32_RESTORE : case AMDGPU :: <ISA_LIT>_SPILL_V64_RESTORE : case AMDGPU :: <ISA_LIT>_SPILL_V96_RESTORE : case AMDGPU :: <ISA_LIT>_SPILL_V128_RESTORE : case AMDGPU :: <ISA_LIT>_SPILL_V256_RESTORE : case AMDGPU :: <ISA_LIT>_SPILL_V512_RESTORE : { buildScratchLoadStore ( MI , AMDGPU :: BUFFER_LOAD_DWORD_OFFSET , TII -> getNamedOperand ( * MI , AMDGPU :: OpName :: dst ) -> getReg ( ) , TII -> getNamedOperand ( * MI , AMDGPU :: OpName :: scratch_rsrc ) -> getReg ( ) , TII -> getNamedOperand ( * MI , AMDGPU :: OpName :: scratch_offset ) -> getReg ( ) , FrameInfo -> getObjectOffset ( Index ) , RS ) ; MI -> eraseFromParent ( ) ; break ; } default : { int64_t Offset = FrameInfo -> getObjectOffset ( Index ) ; FIOp . ChangeToImmediate ( Offset ) ; if ( ! TII -> isImmOperandLegal ( MI


<s> else PredicateValue = PredDef -> getOperand ( DefiningValueNo ) . getImm ( ) != <NUM_LIT> ; } if ( PredicateValue != InvertedPolarity ) { I . getOperand ( PredRegLoc ) . setReg ( <STR_LIT> ) ; I . getOperand ( PredRegLoc + <NUM_LIT> ) . setImm ( <NUM_LIT> ) ; if ( I . getOperand ( <NUM_LIT> ) . isReg ( ) && I . getOperand ( <NUM_LIT> ) . isDef ( ) && isDstFullyWritten ( I ) ) { unsigned IncomeReg = I . getOperand ( IncomeArg ) . getReg ( ) ; MachineInstr * IncomeDef = MRI -> getVRegDef ( IncomeReg ) ; if ( IncomeDef -> getOpcode ( ) != <STR_LIT> ) { Register ireg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; const TargetRegisterClass * RC ; if ( ireg . isVirtual ( ) ) { RC = MRI -> getRegClass ( ireg ) ; } else { RC = static_cast < const <ISA_LIT>InstrInfo * > ( TII ) -> getClassOfPhysicalRegister ( ireg , * TRI ) ; } unsigned Undef = MRI -> createVirtualRegister ( RC ) ; const DebugLoc & DL = I . getDebugLoc ( ) ; BuildMI ( * ( I . getParent ( ) ) , & I , DL , TII -> get ( <STR_LIT> ) , Undef ) ; I . getOperand ( IncomeArg ) . setReg ( Undef ) ; } } ++ NumReplaced ; } else { unsigned NIn = IncomeArg ; for ( MachineOperand & D : I . defs ( ) ) { assert ( D . isReg ( ) ) ; unsigned OldReg = D . getReg ( ) ; unsigned NewReg = I . getOperand ( NIn ) . getReg ( ) ; MRI -> replaceRegWith ( OldReg , NewReg ) ; ++ NIn ; } I . eraseFromParent ( ) ; ++ NumRemoved


<s> if ( ! LCREVT . isSimple ( ) ) return <NUM_LIT> ; GlobalValue * GV = new GlobalVariable ( Type :: getInt32Ty ( * Context ) , false , GlobalValue :: ExternalLinkage , <NUM_LIT> ,


<s> if ( ! TargetRegisterInfo :: isVirtualRegister ( SrcReg ) || DstRC == & AMDGPU :: M0RegRegClass ) return false ; SrcRC = TRI -> getSubRegClass ( MRI . getRegClass ( SrcReg ) , SrcSubReg ) ; return TRI -> isSGPRClass ( DstRC ) && TRI -> hasVGPRs


<s> if ( S == MCDisassembler :: Success ) { DecodeGRRegsRegisterClass ( Inst , Op1 , Address , Decoder ) ; DecodeGRRegsRegisterClass ( Inst , Op2 , Address , Decoder


<s> void <ISA_LIT>TargetELFStreamer :: emitIntTextAttribute ( unsigned Attribute , unsigned IntValue , StringRef StringValue ) { getStreamer ( ) . setAttributeItems ( Attribute , IntValue , StringValue ,


<s> static bool sh_function_value_regno_p ( const unsigned int regno ) { return regno == FIRST_RET_REG || ( TARGET_SH2E && regno


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) : LLVMTargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL ) , DL ( <STR_LIT> <STR_LIT> <STR_LIT> ) , Subtarget ( TT , CPU , FS ) , InstrInfo ( Subtarget ) , TLInfo ( * this ) , TSInfo ( * this ) , FrameLowering ( Subtarget ) , InstrItins ( & Subtarget . getInstrItineraryData ( ) ) { setMCUseCFI (


<s> error_iterator errors_begin ( ) { return mErrors . begin


<s> else if ( from == ARG_POINTER_REGNUM && to == FRAME_POINTER_REGNUM ) return pdp11_reg_save_size ( ) + <NUM_LIT> ; else if ( from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM ) return pdp11_reg_save_size


<s> if ( createMemLibcall ( MIRBuilder , * MIRBuilder . getMRI ( ) , MI ) == LegalizerHelper :: UnableToLegalize ) return false ; MI . eraseFromParent ( ) ; return true ; default : break ; } return


<s> static DecodeStatus DecodeGRRegsRegisterClass ( MCInst & Inst , uint64_t RegNo , uint64_t Address , const void * Decoder ) { if ( RegNo > array_lengthof ( GPRDecoderTable ) ) return MCDisassembler :: Fail ; Register Reg = GPRDecoderTable [


<s> const MCOperand & MO = MI . getOperand ( OpNo ) ; if ( MO . isImm ( ) ) return MO . getImm ( ) >> <NUM_LIT> ; assert ( MO . isExpr ( ) &&


<s> switch ( Opcode ) { default : return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> if ( nds32_expand_setmem_unroll ( dstmem , size , value , align , expected_align , expected_size ) ) return true ; return nds32_expand_setmem_loop ( dstmem , size ,


<s> if ( ShouldPreserveUseListOrder ) return ; std :: stable_sort ( Values . begin ( ) + CstStart , Values . begin ( ) + CstEnd , [ this ] ( const std :: pair < const Value * , unsigned > & LHS , const std :: pair < const Value * , unsigned > & RHS ) { if ( LHS . first -> getType ( ) != RHS . first -> getType ( ) ) return getTypeID ( LHS . first -> getType ( ) ) < getTypeID ( RHS . first -> getType ( ) ) ; return LHS . second > RHS . second ; } ) ; std :: stable_partition ( Values . begin ( ) + CstStart , Values . begin ( )


<s> Val = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Lo , Hi ) ; if ( VA . getLocVT ( ) == <STR_LIT> ) { SDValue Vec = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> ) ; Vec = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Vec , Val , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; VA = RVLocs [ ++ i ] ; Lo = DAG . getCopyFromReg ( Chain , dl , VA . getLocReg ( ) , <STR_LIT> , InFlag ) ; Chain = Lo . getValue ( <NUM_LIT> ) ; InFlag = Lo . getValue ( <NUM_LIT> ) ; VA = RVLocs [ ++ i ] ; Hi = DAG . getCopyFromReg ( Chain , dl , VA . getLocReg ( ) , <STR_LIT> , InFlag ) ; Chain = Hi . getValue ( <NUM_LIT> ) ; InFlag = Hi . getValue ( <NUM_LIT> ) ; Val = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Lo , Hi ) ; Val = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Vec , Val , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; } } else { Val = DAG . getCopyFromReg ( Chain , dl , VA . getLocReg ( ) , VA


<s> LLVMContext & Ctx = MF -> getFunction ( ) -> getContext ( ) ; Ctx . emitError ( <STR_LIT> ) ; } BuildMI ( * MBB , MI , DL , TII -> getMCOpcodeFromPseudo ( AMDGPU :: V_READLANE_B32 ) , SubReg ) . addReg ( Spill . VGPR ) . addImm ( Spill . Lane ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) , RegState :: ImplicitDefine ) ; } switch ( MF -> getSubtarget < AMDGPUSubtarget > ( ) . getGeneration ( ) ) { case AMDGPUSubtarget :: SOUTHERN_ISLANDS : TII -> insertNOPs ( MI , <NUM_LIT> ) ; break ; case AMDGPUSubtarget :: SEA_ISLANDS : break ; default : TII -> insertNOPs ( MI , <NUM_LIT> ) ; } MI -> eraseFromParent ( ) ; break ; } case AMDGPU :: <ISA_LIT>_SPILL_V512_SAVE : case AMDGPU :: <ISA_LIT>_SPILL_V256_SAVE : case AMDGPU :: <ISA_LIT>_SPILL_V128_SAVE : case AMDGPU :: <ISA_LIT>_SPILL_V96_SAVE : case AMDGPU :: <ISA_LIT>_SPILL_V64_SAVE : case AMDGPU :: <ISA_LIT>_SPILL_V32_SAVE : buildScratchLoadStore ( MI , AMDGPU :: BUFFER_STORE_DWORD_OFFSET , TII -> getNamedOperand ( * MI , AMDGPU :: OpName :: src ) -> getReg ( ) , TII -> getNamedOperand ( * MI , AMDGPU :: OpName :: scratch_rsrc ) -> getReg ( ) , TII -> getNamedOperand ( * MI , AMDGPU :: OpName :: scratch_offset ) -> getReg ( ) , FrameInfo -> getObjectOffset ( Index ) , RS ) ; MI -> eraseFromParent ( ) ; break ; case AMDGPU :: <ISA_LIT>_SPILL_V32_RESTORE : case AMDGPU :: <ISA_LIT>_SPILL_V64_RESTORE : case AMDGPU :: <ISA_LIT>_SPILL_V96_RESTORE : case AMDGPU :: <ISA_LIT>_SPILL_V128_RESTORE : case AMDGPU :: <ISA_LIT>_SPILL_V256_RESTORE : case AMDGPU :: <ISA_LIT>_SPILL_V512_RESTORE : { buildScratchLoadStore ( MI , AMDGPU :: BUFFER_LOAD_DWORD_OFFSET , TII -> getNamedOperand ( * MI , AMDGPU :: OpName :: dst ) -> getReg ( ) , TII -> getNamedOperand ( * MI , AMDGPU :: OpName :: scratch_rsrc ) -> getReg ( ) , TII -> getNamedOperand ( *


<s> MCAsmParserExtension :: Initialize ( parser ) ; parser . addAliasForDirective ( <STR_LIT> , <STR_LIT> ) ; setAvailableFeatures ( ComputeAvailableFeatures ( STI . getFeatureBits ( ) ) ) ; AssemblerOptions . push_back ( llvm :: make_unique < <ISA_LIT>AssemblerOptions > ( STI . getFeatureBits ( ) ) ) ; AssemblerOptions . push_back ( llvm :: make_unique < <ISA_LIT>AssemblerOptions > ( STI . getFeatureBits ( ) ) ) ; getTargetStreamer ( ) . updateABIInfo ( * this ) ; if ( ! isABI_O32 ( ) && ! useOddSPReg ( ) != <NUM_LIT> ) report_fatal_error ( <STR_LIT> ) ; CurrentFn =


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) : LLVMTargetMachine ( T , computeDataLayout ( TT ) , TT , CPU , FS , Options , getEffectiveRelocModel ( RM ) , CM ,

OL ) , TLOF ( make_unique < TargetLoweringObjectFileELF > ( ) ) , Subtarget ( TT , CPU , FS , * this ) {


<s> MachineRegisterInfo & RegInfo = BB -> getParent ( ) -> getRegInfo ( ) ; DebugLoc DL = MI -> getDebugLoc ( ) ; unsigned Wd = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Fs = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Wt1 = RegInfo . createVirtualRegister ( & <STR_LIT> ) ; unsigned Wt2 = RegInfo . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) , Wt1 ) ; BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) , Wt2 ) . addReg ( Wt1 ) . addReg ( Fs ) . addImm ( <STR_LIT> ) ; BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) , Wd ) . addReg ( Wt2 )


<s> if ( MergeInit ) AU . addRequired < AAResultsWrapperPass > (


<s> } if ( MO . isReg ( ) ) for ( unsigned IndexReg : <STR_LIT> ) if ( RI . isSubRegisterEq ( IndexReg , MO . getReg ( ) ) ) { return


<s> RegisterTarget < Triple :: lc3 > X ( The<ISA_LIT>Target


<s> unsigned Idx0 ; unsigned Idx1 ; static const unsigned Idxs [ <NUM_LIT> ] [ <NUM_LIT> ] = { { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } , } ; assert ( CI . Width >= <NUM_LIT> && CI . Width <= <NUM_LIT> ) ; assert ( Paired . Width >= <NUM_LIT> && Paired . Width <= <NUM_LIT> ) ; if ( ReverseOrder ) { Idx1 = Idxs [ <NUM_LIT> ] [ Paired . Width - <NUM_LIT> ] ; Idx0 = Idxs [ Paired . Width ] [ CI . Width - <NUM_LIT> ] ; }


<s> static MCInstPrinter * createMCInstPrinter ( const Triple & , unsigned SyntaxVariant , const MCAsmInfo & MAI , const MCInstrInfo & MII , const MCRegisterInfo & MRI ) { assert ( SyntaxVariant == <NUM_LIT>


<s> const SDValue & Base = LN -> getBasePtr ( ) ; const SDValue & Offset = LN -> getOffset ( ) ; if ( Is<ISA_LIT>Global ( Base ) ) { if ( ! Offset -> isUndef ( ) ) report_fatal_error ( <STR_LIT> , false ) ; SDVTList Tys = DAG . getVTList ( LN -> getValueType ( <NUM_LIT> ) , <STR_LIT> ) ; SDValue Ops [ ] = { LN -> getChain


<s> int Offset = SignExtend32 < <NUM_LIT> > ( Insn & <NUM_LIT> ) ; unsigned Reg = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned Base = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; Reg = getReg ( Decoder , <STR_LIT> , Reg ) ; Base = getReg ( Decoder , <STR_LIT> , Base ) ; if ( Inst . getOpcode ( ) == <STR_LIT> ) { Inst . addOperand ( MCOperand :: CreateReg ( Reg ) ) ; } Inst . addOperand ( MCOperand :: CreateReg ( Reg ) ) ; Inst . addOperand ( MCOperand :: CreateReg ( Base ) ) ; Inst . addOperand ( MCOperand :: CreateImm ( Offset


<s> void <ISA_LIT>16FrameLowering :: emitEpilogue ( MachineFunction & MF , MachineBasicBlock & MBB ) const { MachineBasicBlock :: iterator MBBI = MBB . getLastNonDebugInstr ( ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const <ISA_LIT>16InstrInfo & TII = * static_cast < const <ISA_LIT>16InstrInfo * > ( STI . getInstrInfo ( ) ) ; DebugLoc dl = MBBI -> getDebugLoc (


<s> static bool MorphToF128Reg ( <ISA_LIT>Operand & Op ) { unsigned Reg = Op . getReg ( ) ; unsigned regIdx = Reg -


<s> return isInt < <NUM_LIT> > ( MFI -> getMaxCallFrameSize ( ) + getStackAlignment ( ) ) &&


<s> else if ( ( fn_type & ARC_FUNCTION_ILINK2 ) != <NUM_LIT> ) regno = ILINK2_REG ; else gcc_unreachable ( ) ; } else if ( ARC_NORMAL_P ( fn_type ) || ARC_NAKED_P ( fn_type ) ) regno = RETURN_ADDR_REGNUM ; gcc_assert ( regno != <NUM_LIT> ) ; return


<s> if ( INSN_P ( insn ) && GET_CODE ( PATTERN ( insn ) ) == UNSPEC_VOLATILE && XINT ( PATTERN ( insn ) , <NUM_LIT> ) == UNSPEC_CONSTTABLE ) mips_set_text_contents_type ( asm_out_file , <STR_LIT> , XINT ( XVECEXP

( PATTERN ( insn ) , <NUM_LIT> , <NUM_LIT> ) , <NUM_LIT> ) , FALSE ) ;


<s> void <ISA_LIT>TargetELFStreamer :: emitObjectArch ( <STR_LIT> Value ) { EmittedArch =


<s> return selectAddrRiSpls ( Addr , Base , Offset ,


<s> return ( uint16x4_t ) __builtin_neon_vreinterpretv4hiv4hi (


<s> if ( MI . getOperand ( <NUM_LIT> ) . isFI ( ) && MI . getOperand ( <NUM_LIT> ) . isImm ( ) && MI . getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) { FrameIndex = MI . getOperand ( <NUM_LIT> ) . getIndex ( ) ; return MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; } } return


<s> unsigned NumInputs = Inputs . size ( ) ; if ( NumInputs == <NUM_LIT> ) return SDValue ( ) ; EVT RootVT = Root . getValueType ( ) ; unsigned RootSizeInBits = RootVT . getSizeInBits ( ) ; assert ( ( RootSizeInBits % NumMaskElts ) == <NUM_LIT> && <STR_LIT> ) ; SmallVector < SDValue , <NUM_LIT> > WideInputs ( Inputs . begin ( ) , Inputs . end ( ) ) ; SmallVector < unsigned , <NUM_LIT> > Offsets ( NumInputs , <NUM_LIT> ) ; unsigned WideSizeInBits = RootSizeInBits ; for ( unsigned i = <NUM_LIT> ; i != NumInputs ; ++ i ) { SDValue & Src = WideInputs [ i ] ; unsigned & Offset = Offsets [ i ] ; Src = peekThroughBitcasts ( Src ) ; EVT BaseVT = Src . getValueType ( ) ; while ( Src . getOpcode ( ) == <STR_LIT> ) { Offset += Src . getConstantOperandVal ( <NUM_LIT> ) ; Src = Src . getOperand ( <NUM_LIT> ) ; } WideSizeInBits = std :: max ( WideSizeInBits , ( unsigned ) Src . getValueSizeInBits ( ) ) ; assert ( ( Offset % BaseVT . getVectorNumElements ( ) ) == <NUM_LIT> && <STR_LIT> ) ; Offset /= BaseVT . getVectorNumElements ( ) ; Offset *= NumMaskElts ; } if ( llvm :: all_of ( Offsets , [ ] ( unsigned Offset ) { return Offset == <NUM_LIT> ; } ) ) return SDValue ( ) ; unsigned Scale = WideSizeInBits / RootSizeInBits ; assert ( ( WideSizeInBits % RootSizeInBits ) == <NUM_LIT> && <STR_LIT> ) ; EVT WideSVT = WideInputs [ <NUM_LIT> ] . getValueType ( ) . getScalarType ( ) ; if ( llvm :: any_of ( WideInputs , [ & WideSVT , & DAG ] ( SDValue Op ) { return ! DAG . getTargetLoweringInfo ( ) . isTypeLegal ( Op . getValueType ( ) ) || Op . getValueType ( ) . getScalarType ( ) != WideSVT ; } ) ) return


<s> if ( REG_P ( * x ) ) mips_sim_wait_reg ( data , mips_sim_insn , * x ) ; return <NUM_LIT>


<s> const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; return isInt < <NUM_LIT> > ( MFI -> getMaxCallFrameSize ( ) ) && !


<s> unsigned getScratchReg ( ) { for ( int i = <NUM_LIT> ; i >= <NUM_LIT> ; -- i ) if ( ! isLive ( i ) ) return i ; llvm_unreachable ( <STR_LIT>


<s> bool <ISA_LIT>ConstantIslands :: isOffsetInRange ( unsigned UserOffset , unsigned TrialOffset , unsigned MaxDisp , bool


<s> Position . Address += Terminator . Size ; if ( AssumeRelaxed ) Position . Address


<s> <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , } ; if ( ! STI . hasFeature ( <STR_LIT> ) && ! STI . hasFeature ( <STR_LIT> ) ) { for ( uint64_t i = <NUM_LIT> ; i < Count ; ++ i ) OS << '\x90' ; return true ; } uint64_t MaxNopLength = <NUM_LIT> ; if ( STI . getFeatureBits ( ) [ <STR_LIT> ] ) MaxNopLength = <NUM_LIT> ; else if ( STI . getFeatureBits ( ) [ <STR_LIT> ] ) MaxNopLength = <NUM_LIT> ; else if ( STI . getFeatureBits ( ) [ <STR_LIT> ] ) MaxNopLength = <NUM_LIT> ; do { const uint8_t ThisNopLength = ( uint8_t ) std :: min ( Count , MaxNopLength ) ; const uint8_t Prefixes = ThisNopLength <= <NUM_LIT> ? <NUM_LIT> : ThisNopLength - <NUM_LIT> ; for ( uint8_t i = <NUM_LIT> ; i < Prefixes ; i ++ ) OS << '\x66' ; const uint8_t Rest = ThisNopLength - Prefixes ; if ( Rest != <NUM_LIT> ) OS . write ( Nops [ Rest - <NUM_LIT> ] , Rest ) ; Count -= ThisNopLength ; } while ( Count != <NUM_LIT> ) ; return true


<s> int <ISA_LIT>FrameLowering :: getFrameIndexReferenceSP ( const MachineFunction & MF , int FI , Register & FrameReg , int Adjustment ) const { const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; FrameReg = TRI -> getStackRegister (


<s> bool isCmseNSEntryFunction ( ) const { return


<s> if ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) . getVectorElementType ( ) == <STR_LIT> ) { if ( VT . getVectorElementType ( ) == <STR_LIT> ) return Op ; return DAG . UnrollVectorOp ( Op . getNode ( ) ) ; } assert ( ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) == <STR_LIT> || Op . getOperand ( <NUM_LIT> ) . getValueType ( ) == <STR_LIT> ) && <STR_LIT> ) ; const bool HasFullFP16 = static_cast < const <ISA_LIT>Subtarget & > ( DAG . getSubtarget ( ) ) . hasFullFP16 ( ) ; EVT DestVecType ; if ( VT == <STR_LIT> ) DestVecType = <STR_LIT> ; else if ( VT == <STR_LIT> && HasFullFP16 ) DestVecType = <STR_LIT> ; else if ( VT == <STR_LIT> && HasFullFP16 ) DestVecType = <STR_LIT> ; else return DAG . UnrollVectorOp ( Op . getNode ( ) ) ; unsigned CastOpc ; unsigned Opc ; switch ( Op . getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : CastOpc = <STR_LIT> ; Opc = <STR_LIT> ; break ; case <STR_LIT>


<s> bool <ISA_LIT>PacketizerList :: DemoteToDotOld ( MachineInstr * MI ) { const <ISA_LIT>InstrInfo * QII = ( const <ISA_LIT>InstrInfo * ) TII ; int NewOpcode = GetDotOldOp ( MI -> getOpcode


<s> const Constant * C = CN -> getConstVal ( ) ; switch ( getTargetMachine ( ) . getCodeModel ( ) ) { case CodeModel :: Small : return DAG . getNode ( <STR_LIT> , DL , PtrVT , DAG . getTargetConstantPool ( C , PtrVT , <NUM_LIT> , <NUM_LIT> , <STR_LIT> ) , DAG . getTargetConstantPool ( C , PtrVT , <NUM_LIT>

, <NUM_LIT> , <STR_LIT> ) , DAG . getConstant ( CN -> getAlignment ( ) , <STR_LIT> ) ) ;


<s> const <ISA_LIT>InstrInfo * getInstrInfo


<s> printLeaMemReference ( MI , OpNo , O


<s> <ISA_LIT>BSel ( ) : MachineFunctionPass ( ID ) { initialize<ISA_LIT>BSelPass ( * PassRegistry :: getPassRegistry (


<s> bool nds32_n8_ex_to_ii_p ( rtx_insn * producer , rtx_insn * consumer ) { rtx def_reg ; switch ( get_attr_type ( producer ) ) { case TYPE_ALU : if ( movd44_insn_p ( producer ) ) def_reg = extract_movd44_odd_reg ( producer ) ; else def_reg = SET_DEST ( PATTERN ( producer ) ) ; break ; case TYPE_MUL : case TYPE_MAC : def_reg = SET_DEST ( PATTERN ( producer ) ) ; break ; case TYPE_DIV : if ( INSN_CODE ( producer ) == CODE_FOR_divmodsi4 || INSN_CODE ( producer ) == CODE_FOR_udivmodsi4 ) def_reg = SET_DEST ( parallel_element ( producer , <NUM_LIT> ) ) ; else def_reg = SET_DEST ( PATTERN ( producer ) ) ; break ; case TYPE_LOAD : case TYPE_STORE : case TYPE_LOAD_MULTIPLE : case TYPE_STORE_MULTIPLE : if ( ! post_update_insn_p ( producer ) ) return


<s> return TargetTriple . isOSBinFormatELF


<s> if ( VGPR_MIN <= Val && Val <= VGPR_MAX ) { return createRegOperand ( getVgprClassId ( Width ) , Val - VGPR_MIN ) ; } if ( Val <= SGPR_MAX ) { assert ( SGPR_MIN == <NUM_LIT> ) ; return createSRegOperand ( getSgprClassId ( Width ) , Val - SGPR_MIN ) ; } if ( TTMP_MIN <= Val && Val <= TTMP_MAX ) { return createSRegOperand ( getTtmpClassId ( Width ) , Val


<s> unsigned imm = fieldFromInstruction ( Val , <NUM_LIT> , <NUM_LIT> ) ; if ( ! Check ( S , DecodetGPRRegisterClass ( Inst , Rn , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeT2Imm7 < shift > ( Inst , imm , Address , Decoder ) ) ) return MCDisassembler :: Fail ; return


<s> imm |= ( fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ) ; if ( Inst . getOpcode ( ) == <STR_LIT> ) if ( ! Check ( S , DecoderGPRRegisterClass ( Inst , Rd , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecoderGPRRegisterClass ( Inst , Rd , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! tryAddingSymbolicOperand ( Address , imm , false , <NUM_LIT> , Inst , Decoder ) ) Inst . addOperand ( MCOperand :: CreateImm ( imm ) ) ; return S


<s> if ( InFlag . getNode ( ) ) Ops . push_back ( InFlag ) ; if ( isTailCall ) { assert ( ( ( Callee . getOpcode ( ) == <STR_LIT> && cast < RegisterSDNode > ( Callee ) -> getReg ( ) == <STR_LIT> ) || Callee . getOpcode ( ) == <STR_LIT> || Callee . getOpcode ( ) == <STR_LIT> || isa < ConstantSDNode > ( Callee ) ) && <STR_LIT> ) ; DAG . getMachineFunction ( ) . getFrameInfo ( ) . setHasTailCall ( ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Ops ) ; } MachineFunction & MF = DAG . getMachineFunction ( ) ; EVT PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; if ( ! isTailCall && ! isPatchPoint && ( ( Subtarget . isSVR4ABI ( ) && Subtarget . is<ISA_LIT>64 ( ) ) || Subtarget . isAIXABI ( ) ) ) { if ( CallOpc == <STR_LIT> ) { if ( Subtarget . isAIXABI ( ) ) report_fatal_error ( <STR_LIT> ) ; CallOpc = <STR_LIT> ; SDValue StackPtr = DAG . getRegister ( <STR_LIT> , PtrVT ) ; unsigned TOCSaveOffset = Subtarget . getFrameLowering ( ) -> getTOCSaveOffset ( ) ; SDValue TOCOff = DAG . getIntPtrConstant ( TOCSaveOffset , dl ) ; SDValue AddTOC = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , StackPtr , TOCOff ) ; Ops . insert ( std :: next ( Ops . begin ( ) ) , AddTOC ) ; } else if ( CallOpc == <STR_LIT> && ! callsShareTOCBase ( & MF . getFunction ( ) , Callee , DAG . getTarget ( ) ) ) { CallOpc = <STR_LIT> ; } } if ( Subtarget . isAIXABI ( ) && isFunctionGlobalAddress ( Callee ) ) { GlobalAddressSDNode * G = cast < GlobalAddressSDNode > ( Callee ) ; auto & Context = DAG . getMachineFunction ( ) . getMMI ( ) . getContext ( ) ; const GlobalObject * GO = cast < GlobalObject > ( G


<s> if ( SDValue V = combineBinOpToReduce ( N , DAG ) ) return V ; return combineSelectAndUseCommutative ( N ,


<s> unsigned TotalStallCycles = <NUM_LIT> ; SmallSet < const MachineInstr * , <NUM_LIT> > Visited ; for ( auto & MI : MRI -> use_nodbg_instructions ( SrcReg ) ) { if ( MI . isBundle ( ) ) continue ; if ( ! Visited . insert ( & MI ) . second ) continue ; unsigned StallCycles ; unsigned UsedBanks


<s> if ( NumV2Inputs == <NUM_LIT> ) { if ( SDValue Broadcast = lowerShuffleAsBroadcast ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return Broadcast ; if ( SDValue Shift = lowerShuffleAsShift ( DL , <STR_LIT> , V1 , V1 , Mask , Zeroable , Subtarget , DAG ) ) return Shift ; if ( SDValue V = lowerShuffleWithUNPCK ( DL , <STR_LIT> , Mask , V1 , V2 , DAG ) ) return V ; if ( SDValue V = lowerShuffleWithPACK ( DL , <STR_LIT> , Mask , V1 , V2 , DAG , Subtarget ) ) return V ; if ( SDValue Rotate = lowerShuffleAsByteRotate ( DL , <STR_LIT> , V1 , V1 , Mask , Subtarget , DAG ) ) return Rotate ; SmallVector < int , <NUM_LIT> > MutableMask ( Mask . begin ( ) , Mask . end ( ) ) ; return lowerV8I16GeneralSingleInputShuffle ( DL , <STR_LIT> , V1 , MutableMask , Subtarget , DAG ) ; } assert ( llvm :: any_of ( Mask , [ ] ( int M ) { return M >= <NUM_LIT> && M < <NUM_LIT> ; } ) && <STR_LIT> <STR_LIT> ) ; if ( SDValue Shift = lowerShuffleAsShift ( DL , <STR_LIT> , V1 , V2


<s> MachineFunction & MF = DAG . getMachineFunction ( ) ; <ISA_LIT>FunctionInfo * <ISA_LIT>FI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; <ISA_LIT>FI -> setISR ( ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> ,


<s> return isTargetWatchABI ( ) || ( useWideStrideVFP ( ) && ! OptMinSize


<s> if ( IsIndirect ) { auto FnPtr = CallParams . getOperand ( <NUM_LIT> ) ; CallParams . RemoveOperand ( <NUM_LIT> ) ; CallParams . addOperand ( FnPtr ) ; } for ( auto Def : CallResults . defs ( ) ) MIB . add ( Def ) ; if ( IsIndirect ) { MIB . addImm ( <NUM_LIT> ) ; MIB . addImm ( <NUM_LIT> ) ; } for ( auto Use : CallParams . uses ( ) ) MIB . add ( Use ) ; BB -> insert ( CallResults . getIterator ( ) , MIB ) ; CallParams . eraseFromParent ( ) ; CallResults . eraseFromParent ( ) ; return BB


<s> FastISel * <STR_LIT> ( FunctionLoweringInfo & funcInfo , const TargetLibraryInfo * libInfo ) { return new <ISA_LIT>FastISel ( funcInfo


<s> TII = ST . getInstrInfo ( ) ; TRI = ST . getRegisterInfo ( ) ; MFN = & MF ; MRI = & MF . getRegInfo ( ) ; MDT = & getAnalysis < MachineDominatorTree > ( ) ; MLI = & getAnalysis < MachineLoopInfo > ( ) ; MBPI = Enable<ISA_LIT>BP ? & getAnalysis < MachineBranchProbabilityInfo > ( ) : nullptr ; Deleted . clear ( ) ; bool Changed = false ; for ( MachineLoopInfo :: iterator I = MLI -> begin ( ) , E = MLI -> end ( ) ; I != E ; ++ I ) Changed |= visitLoop ( * I ) ; Changed |= visitLoop (


<s> if ( DAG . getTarget ( ) . Options . EmulatedTLS ) return LowerToTLSEmulatedModel ( GA , DAG ) ; if ( Subtarget -> isTargetDarwin ( ) ) return LowerDarwinGlobalTLSAddress ( Op , DAG ) ; if ( Subtarget -> isTargetELF ( ) ) return LowerELFGlobalTLSAddress ( Op , DAG ) ; llvm_unreachable ( <STR_LIT>


<s> static void const_double_split ( rtx x , HOST_WIDE_INT * p_high , HOST_WIDE_INT * p_low ) { if ( GET_CODE ( x ) == CONST_DOUBLE ) { long t [ <NUM_LIT> ] ; REAL_VALUE_TYPE rv ; switch ( GET_MODE ( x ) ) { case DFmode : REAL_VALUE_FROM_CONST_DOUBLE ( rv , x ) ; REAL_VALUE_TO_TARGET_DOUBLE ( rv ,


<s> <ISA_LIT>MCExpr :: VariantKind ELFRefKind ; MCSymbolRefExpr :: VariantKind DarwinRefKind ; int64_t Addend ; if ( ! <ISA_LIT>AsmParser :: classifySymbolRef ( Expr , ELFRefKind , DarwinRefKind , Addend ) ) { return true ; } if ( DarwinRefKind == MCSymbolRefExpr :: VK_PAGEOFF || ELFRefKind == <ISA_LIT>MCExpr :: VK_LO12 || ELFRefKind == <ISA_LIT>MCExpr :: VK_GOT_LO12 || ELFRefKind == <ISA_LIT>MCExpr :: VK_DTPREL_LO12 || ELFRefKind == <ISA_LIT>MCExpr :: VK_DTPREL_LO12_NC || ELFRefKind == <ISA_LIT>MCExpr :: VK_TPREL_LO12 || ELFRefKind ==


<s> auto AlignmentIsAcceptable = [ & ] ( EVT VT , Align AlignCheck ) { if ( Op . isAligned ( AlignCheck ) ) return true ; bool Fast ; return allowsMisalignedMemoryAccesses ( VT , <NUM_LIT> , Align ( <NUM_LIT> ) , MachineMemOperand :: MONone , & Fast ) && Fast ; } ; if ( CanUseNEON && Op . isMemset ( ) && ! IsSmallMemset && AlignmentIsAcceptable ( <STR_LIT> , Align ( <NUM_LIT> ) ) ) return <STR_LIT> ; if ( CanUseFP && ! IsSmallMemset && AlignmentIsAcceptable ( <STR_LIT> , Align ( <NUM_LIT> ) ) ) return <STR_LIT> ; if ( Op . size ( ) >= <NUM_LIT> && AlignmentIsAcceptable ( <STR_LIT> ,


<s> if ( ! OpInfo ) return false ; assert ( NumOps == <NUM_LIT> && OpInfo [ <NUM_LIT> ] . RegClass == <NUM_LIT> && <STR_LIT> ) ; unsigned Imm11 = getT1Imm11 (


<s> if ( startIdx < hvxInsts . size ( ) ) { if ( ! hvxInsts [ startIdx ] . Units ) return checkHVXPipes ( hvxInsts , startIdx + <NUM_LIT> , usedUnits ) ; for ( unsigned b = <NUM_LIT> ; b <= <NUM_LIT> ; b <<= <NUM_LIT> ) { if ( ( hvxInsts [ startIdx ] . Units & b ) == <NUM_LIT> ) continue ; unsigned allBits = makeAllBits ( b , hvxInsts [ startIdx ] . Lanes ) ; if ( ( allBits & usedUnits ) == <NUM_LIT> ) { if ( checkHVXPipes ( hvxInsts , startIdx + <NUM_LIT> , usedUnits | allBits ) ) return true ; } } return false


<s> MachineInstr * Def = MRI . getVRegDef ( Reg ) ; if ( ! Def ) return false ; if ( Def -> isCopy ( ) ) { Reg = Def -> getOperand ( <NUM_LIT> ) . getReg ( ) ; auto It = find_if_not ( MRI . reg_nodbg_instructions ( Reg ) , [ ] ( const MachineInstr & MI ) { return MI . isCopy ( ) ; } ) ; if ( It == MRI . reg_instr_nodbg_end ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } Def = & * It ; } if ( Def -> getOpcode ( ) != TargetOpcode :: G_CONSTANT ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> <STR_LIT> ) ; return false ; } Val = Def -> getOperand ( <NUM_LIT> ) . getCImm ( ) -> getLimitedValue ( ) ; return true


<s> if ( VT == <STR_LIT> ) { RefinementSteps = <NUM_LIT> ; return DAG . getNode ( <STR_LIT> , SDLoc ( Operand )


<s> MachineBasicBlock :: iterator NI = MergeWithPrevious ? nullptr : std :: next ( MBBI ) ; unsigned Opc = PI -> getOpcode ( ) ; int Offset = <NUM_LIT> ; if ( ! MergeWithPrevious && NI != MBB . end ( ) && NI -> getOpcode ( ) == TargetOpcode :: CFI_INSTRUCTION ) { return Offset ; } if ( Opc == <STR_LIT> && PI -> getOperand ( <NUM_LIT> ) . getReg ( ) == StackPtr ) { assert ( PI -> getOperand ( <NUM_LIT> ) . getReg ( ) == StackPtr ) ; Offset += PI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; MBB . erase ( PI ) ; if ( ! MergeWithPrevious ) MBBI = NI ; } else if ( Opc == <STR_LIT> && PI -> getOperand ( <NUM_LIT> ) . getReg ( ) == StackPtr ) { assert ( PI -> getOperand ( <NUM_LIT> ) . getReg ( ) == StackPtr ) ; Offset -= PI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; MBB . erase (


<s> <ISA_LIT>Subtarget & <ISA_LIT>Subtarget :: initializeSubtargetDependencies ( StringRef GPU ,


<s> for ( auto & LoopExitTerminator : LoopExit -> terminators ( ) ) { if ( LoopExitTerminator . getOpcode ( ) != <STR_LIT> ) continue ; MachineBasicBlock * LoopExit2 = LoopExitTerminator . getOperand ( <NUM_LIT> ) . getMBB ( ) ; if ( ! blockIsBefore ( LoopExit2 , LoopExit ) && ( LoopExit2 == Preheader || blockIsBefore ( LoopExit2 , Preheader ) ) ) { LLVM_DEBUG ( dbgs ( ) << DEBUG_PREFIX << <STR_LIT> <STR_LIT> ) ; CanMove = false ; break ; } } if ( CanMove ) { for ( auto It = LoopExit -> getIterator ( ) ; It != Preheader -> getIterator ( ) ; It ++ ) { MachineBasicBlock * MBB = & * It ; for ( auto & Terminator : MBB -> terminators ( ) ) { if ( Terminator . getOpcode ( ) != <STR_LIT> && Terminator . getOpcode ( ) !=


<s> break ; TARGET_NODE_CASE ( Lo ) TARGET_NODE_CASE ( Hi ) TARGET_NODE_CASE ( GETFUNPLT ) TARGET_NODE_CASE ( GETTLSADDR ) TARGET_NODE_CASE ( CALL ) TARGET_NODE_CASE ( RET_FLAG ) TARGET_NODE_CASE ( GLOBAL_BASE_REG ) } return


<s> bool isBrList ( ) const { return Kind == BrList


<s> if ( ! isSATValidOnAVX512Subtarget ( In . getValueType ( ) , VT , Subtarget ) ) return SDValue ( ) ; return detectUSatPattern ( In , VT


<s> s390_function_arg_advance ( cum , arg ) ; if ( ! parm_rtx ) continue ; if ( REG_P ( parm_rtx ) ) { int size = s390_function_arg_size ( arg . mode , arg . type ) ; int nregs = ( size + UNITS_PER_LONG - <NUM_LIT> ) / UNITS_PER_LONG ; for ( reg = <NUM_LIT> ; reg < nregs ; reg ++ ) if ( ! call_used_or_fixed_reg_p ( reg + REGNO ( parm_rtx ) ) ) return true ; } else if ( GET_CODE ( parm_rtx ) == PARALLEL ) { int i ; for ( i = <NUM_LIT> ; i < XVECLEN ( parm_rtx , <NUM_LIT> ) ; i ++ ) { rtx r = XEXP ( XVECEXP ( parm_rtx , <NUM_LIT> , i ) , <NUM_LIT> ) ; gcc_assert ( REG_P ( r ) ) ; gcc_assert ( REG_NREGS ( r )


<s> SDValue Tmp1 = DAG . getNode ( <STR_LIT> , DL , VT , Remainder_GE_Den , Remainder_GE_Zero ) ; SDValue Quotient_A_One = DAG . getNode ( <STR_LIT> , DL , VT , Quotient , DAG . getConstant ( <NUM_LIT> , DL , VT ) ) ; SDValue Quotient_S_One = DAG . getNode ( <STR_LIT> , DL , VT , Quotient , DAG . getConstant ( <NUM_LIT> , DL , VT ) ) ; SDValue Div = DAG . getSelectCC ( DL , Tmp1 , DAG . getConstant ( <NUM_LIT> , DL , VT ) , Quotient , Quotient_A_One , <STR_LIT> ) ; Div = DAG . getSelectCC ( DL , Remainder_GE_Zero , DAG . getConstant ( <NUM_LIT> , DL , VT ) , Quotient_S_One , Div , <STR_LIT> ) ; SDValue Remainder_S_Den = DAG . getNode ( <STR_LIT> , DL , VT , Remainder , Den ) ; SDValue Remainder_A_Den = DAG . getNode ( <STR_LIT> , DL , VT , Remainder , Den ) ; SDValue Rem = DAG . getSelectCC ( DL , Tmp1 , DAG . getConstant ( <NUM_LIT> , DL , VT ) , Remainder , Remainder_S_Den , <STR_LIT> ) ; Rem = DAG . getSelectCC ( DL , Remainder_GE_Zero , DAG . getConstant ( <NUM_LIT> , DL , VT ) , Remainder_A_Den , Rem , <STR_LIT> ) ; SDValue Ops [ <NUM_LIT> ] = { Div , Rem


<s> SDLoc dl ( Op ) ; bool UseHVX = Subtarget . useHVXOps ( ) ; EVT VT = Op . getValueType ( ) ; unsigned NElts = Op . getNumOperands ( ) ; SDValue Vec0 = Op . getOperand ( <NUM_LIT> ) ; EVT VecVT = Vec0 . getValueType ( ) ; unsigned Width = VecVT . getSizeInBits ( ) ; if ( NElts == <NUM_LIT> ) { MVT ST = VecVT . getSimpleVT ( ) ; if ( ST == <STR_LIT> || ST == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , dl , VT , Op . getOperand ( <NUM_LIT> ) , Vec0 ) ; if ( UseHVX ) { assert ( ( Width == <NUM_LIT> * <NUM_LIT> && Subtarget . useHVXSglOps ( ) ) || ( Width == <NUM_LIT> * <NUM_LIT> && Subtarget . useHVXDblOps ( ) ) ) ; SDValue Vec1 = Op . getOperand ( <NUM_LIT> ) ; MVT OpTy = Subtarget . useHVXSglOps ( ) ? <STR_LIT> : <STR_LIT> ; MVT ReTy = Subtarget . useHVXSglOps ( ) ? <STR_LIT> : <STR_LIT> ; SDValue B0 = DAG . getNode ( <STR_LIT> , dl , OpTy , Vec0 ) ; SDValue B1 = DAG . getNode ( <STR_LIT> , dl , OpTy , Vec1 ) ; SDValue VC = DAG . getNode ( <STR_LIT> , dl , ReTy , B1 , B0 ) ; return DAG . getNode ( <STR_LIT> , dl , VT , VC ) ; } } if ( VT . getSizeInBits ( ) != <NUM_LIT> && VT . getSizeInBits ( ) != <NUM_LIT> ) return SDValue ( ) ; SDValue C0 = DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ; SDValue C32 = DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ; SDValue W = DAG . getConstant ( Width , dl , <STR_LIT> ) ; SDValue S = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , W , C32 ) ; SDValue V = C0


<s> __o = __builtin_aarch64_ld3rv4hi ( ( const __builtin_aarch64_simd_hi * ) __a ) ; ret . val [ <NUM_LIT> ] = ( uint16x4_t


<s> aggrMemcpys . push_back ( intr ) ; } } else { aggrMemcpys . push_back ( intr ) ; } } else if ( MemSetInst * memsetintr = dyn_cast < MemSetInst > ( II ) ) { Value * len = memsetintr -> getLength ( ) ; if ( ConstantInt * len_int = dyn_cast < ConstantInt > ( len ) ) { if ( len_int -> getZExtValue ( ) >= MaxAggrCopySize ) { aggrMemsets . push_back ( memsetintr ) ; } } else { aggrMemsets . push_back ( memsetintr ) ; } } } } if ( ( aggrLoads . size ( ) == <NUM_LIT> ) && ( aggrMemcpys . size ( ) == <NUM_LIT> ) && ( aggrMemsets . size ( ) == <NUM_LIT> ) ) return false ; for ( unsigned i = <NUM_LIT> , e = aggrLoads . size ( ) ; i != e ; ++ i ) { LoadInst * load = aggrLoads [ i ] ; StoreInst * store = dyn_cast < StoreInst > ( * load -> user_begin ( ) ) ; Value * srcAddr = load -> getOperand ( <NUM_LIT> ) ; Value * dstAddr = store -> getOperand ( <NUM_LIT> ) ; unsigned numLoads = DL -> getTypeStoreSize ( load -> getType ( ) ) ; Value * len = ConstantInt :: get ( Type :: getInt32Ty ( Context ) , numLoads ) ; convertTransferToLoop ( store , srcAddr , dstAddr , len , load -> isVolatile ( ) , store -> isVolatile ( ) , Context , F ) ; store -> eraseFromParent ( ) ; load -> eraseFromParent ( ) ; } for ( unsigned i = <NUM_LIT> , e = aggrMemcpys . size ( ) ; i != e ; ++ i ) { MemTransferInst * cpy = aggrMemcpys [


<s> bool fixupNeedsRelaxation ( const MCFixup & Fixup , uint64_t Value , const MCRelaxableFragment * DF

, const MCAsmLayout & Layout ) const override {


<s> bool requiresDiffExpressionRelocations ( )


<s> static unsigned decodeMFS ( uint32_t insn ) { switch ( ( insn >> <NUM_LIT> ) & <NUM_LIT> ) { default : return UNSUPPORTED ; case <NUM_LIT> : switch ( ( insn >> <NUM_LIT> ) & <NUM_LIT> ) { default : return UNSUPPORTED ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; } case


<s> break ; case <NUM_LIT> : insn -> sibScale = <NUM_LIT> ; break ; case <NUM_LIT> : insn -> sibScale = <NUM_LIT> ; break ; case <NUM_LIT> : insn -> sibScale = <NUM_LIT> ; break ; } base = baseFromSIB ( insn -> sib ) | ( bFromREX ( insn -> rexPrefix ) << <NUM_LIT> ) ; switch ( base ) { case <NUM_LIT> : case <NUM_LIT> : switch ( modFromModRM ( insn -> modRM ) ) { case <NUM_LIT> : insn -> eaDisplacement = EA_DISP_32 ; insn -> sibBase = SIB_BASE_NONE ; break ; case <NUM_LIT> : insn -> eaDisplacement = EA_DISP_8 ; insn -> sibBase = ( SIBBase ) ( sibBaseBase + base ) ; break ; case <NUM_LIT> : insn -> eaDisplacement = EA_DISP_32 ; insn -> sibBase = ( SIBBase ) ( sibBaseBase + base ) ; break ; case <NUM_LIT>


<s> return true ; } unsigned Opcode = StringSwitch < unsigned > ( SpecialReg ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( <NUM_LIT> ) ; if ( Opcode ) { if ( ! Subtarget -> hasVFP2 ( ) ) return false ; if ( Opcode == <STR_LIT> && ! Subtarget -> hasFP<ISA_LIT>v8 ( ) ) return false ; Ops = { getAL ( CurDAG , DL ) , CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) , N -> getOperand ( <NUM_LIT> ) } ; ReplaceNode ( N , CurDAG -> getMachineNode ( Opcode , DL , <STR_LIT> , <STR_LIT> , Ops ) ) ; return true ; } if ( Subtarget -> isMClass ( ) ) { StringRef Flags = <STR_LIT> , Reg = SpecialReg ; if ( Reg . endswith ( <STR_LIT> ) ) { Flags = <STR_LIT> ; Reg = Reg . drop_back ( <NUM_LIT> ) ; } int SYSmValue = getMClassRegisterMask ( Reg , Flags , true , Subtarget ) ; if ( SYSmValue == - <NUM_LIT> ) return false ; SDValue Ops [ ] = { CurDAG -> getTargetConstant ( SYSmValue , DL , <STR_LIT> ) , getAL ( CurDAG , DL ) , CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) , N -> getOperand ( <NUM_LIT> ) } ; ReplaceNode ( N , CurDAG -> getMachineNode ( <STR_LIT> , DL , <STR_LIT> , <STR_LIT> , Ops ) ) ; return true ; } if ( SpecialReg == <STR_LIT> || SpecialReg == <STR_LIT> ) { Ops = { getAL ( CurDAG , DL ) , CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) , N -> getOperand ( <NUM_LIT> ) } ; ReplaceNode ( N , CurDAG -> getMachineNode ( IsThumb2 ? <STR_LIT> : <STR_LIT> , DL , <STR_LIT> , <STR_LIT> , Ops ) ) ; return true ; } if ( SpecialReg == <STR_LIT> ) { Ops = { getAL ( CurDAG , DL ) , CurDAG -> getRegister ( <NUM_LIT>


<s> int64_t CNVal = CN -> getSExtValue ( ) ; if ( ( int32_t ) CNVal != CNVal ) return Val ; if ( Op == ADD ) { if ( ( CNVal == <NUM_LIT> ) || ( CNVal == - <NUM_LIT> ) ) { Op = ( CNVal == <NUM_LIT> ) ? INC : DEC ; return SDValue ( ) ; } if ( CNVal < <NUM_LIT> ) { Op = SUB ; CNVal = - CNVal ; } } return CurDAG -> getTargetConstant ( CNVal


<s> rtx base ; HOST_WIDE_INT disp , offset ; gcc_assert ( MEM_P ( ref ) ) ; if ( reload_in_progress && ! memory_address_p ( GET_MODE ( ref ) , XEXP ( ref , <NUM_LIT> ) ) ) { base = find_replacement ( & XEXP ( ref , <NUM_LIT> ) ) ; gcc_assert ( memory_address_p ( GET_MODE ( ref ) , base ) ) ; } else base = XEXP ( ref , <NUM_LIT> ) ; if ( GET_CODE ( base ) == PLUS ) disp = INTVAL ( XEXP ( base , <NUM_LIT> ) ) , base = XEXP ( base , <NUM_LIT> ) ; else disp = <NUM_LIT> ; if ( MEM_ALIGN ( ref ) >= <NUM_LIT> ) offset = <NUM_LIT> ; else offset = disp & <NUM_LIT> ; gcc_assert ( offset + GET_MODE_SIZE ( GET_MODE ( ref ) ) <= GET_MODE_SIZE ( SImode ) ) ; * paligned_mem = widen_memory_access ( ref , SImode , - offset ) ; offset *=


<s> MCAsmBackend * llvm :: create<ISA_LIT>AsmBackend ( const Target & T , const MCSubtargetInfo & STI , const MCRegisterInfo & MRI , const MCTargetOptions & Options ) { return new <ISA_LIT>AsmBackend ( T , STI . getTargetTriple


<s> FixupKind = isMicro<ISA_LIT> ( STI ) ? <STR_LIT> : <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: MEK_GOTTPREL : FixupKind = <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: MEK_GOT : FixupKind = isMicro<ISA_LIT> ( STI ) ? <STR_LIT> : <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: MEK_GOT_CALL : FixupKind = isMicro<ISA_LIT> ( STI ) ? <STR_LIT> : <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: MEK_GOT_DISP : FixupKind = isMicro<ISA_LIT> ( STI ) ? <STR_LIT> : <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: MEK_GOT_HI16 : FixupKind = <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: MEK_GOT_LO16 : FixupKind = <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: MEK_GOT_PAGE : FixupKind = isMicro<ISA_LIT> ( STI ) ? <STR_LIT> : <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: MEK_GOT_OFST : FixupKind = isMicro<ISA_LIT> ( STI ) ? <STR_LIT> : <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: MEK_GPREL : FixupKind = <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: MEK_LO : { if ( <ISA_LIT>Expr -> isGpOff ( ) ) { FixupKind = <STR_LIT> ; break ; } FixupKind = isMicro<ISA_LIT> ( STI ) ? <STR_LIT> : <STR_LIT> ; break ; } case <ISA_LIT>MCExpr :: MEK_HIGHEST : FixupKind = <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: MEK_HIGHER : FixupKind = <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: MEK_HI : if ( <ISA_LIT>Expr -> isGpOff ( ) ) { FixupKind = <STR_LIT> ; break ; } FixupKind = isMicro<ISA_LIT> ( STI ) ? <STR_LIT> : <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: MEK_PCREL_HI16 : FixupKind = <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: MEK_PCREL_LO16 : FixupKind = <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: MEK_TLSGD : FixupKind = isMicro<ISA_LIT> ( STI ) ? <STR_LIT> : <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: MEK_TLSLDM : FixupKind = isMicro<ISA_LIT> ( STI ) ? <STR_LIT> : <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: MEK_TPREL_HI : FixupKind = isMicro<ISA_LIT> ( STI ) ? <STR_LIT> : <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: MEK_TPREL_LO : FixupKind = isMicro<ISA_LIT> ( STI ) ? <STR_LIT> : <STR_LIT> ; break ; } Fixups . push_back ( MCFixup :: create ( <NUM_LIT> , <ISA_LIT>Expr ,


<s> case <STR_LIT> : NewOpcode = <STR_LIT> ; break ; case <STR_LIT> : NewOpcode = <STR_LIT> ; break ; case <STR_LIT> : NewOpcode = <STR_LIT> ; break ; case <STR_LIT> : NewOpcode = <STR_LIT> ; break ; default : llvm_unreachable ( <STR_LIT>


<s> int64_t PrevVTYPEImm = PrevVSETVLI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; int64_t VTYPEImm = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( PrevAVLReg != AVLReg || PrevVTYPEImm != VTYPEImm ) { PrevVSETVLI = & MI ; continue ; } if ( AVLReg == <STR_LIT> ) { Register PrevOutVL = PrevVSETVLI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; Register OutVL = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( PrevOutVL == <STR_LIT> && OutVL != <STR_LIT> ) { PrevVSETVLI = & MI ; continue ; } } MI . eraseFromParent (


<s> const MCSymbol * Sym = Mang -> getSymbol ( GV ) ; const MCExpr * Res = MCSymbolRefExpr :: Create ( Sym , MCSymbolRefExpr :: VK_GOTPCREL , getContext ( ) ) ; const MCExpr * Four = MCConstantExpr :: Create ( <NUM_LIT> , getContext ( ) ) ; return MCBinaryExpr :: CreateAdd ( Res , Four , getContext ( ) ) ; } return TargetLoweringObjectFileMachO :: getTTypeGlobalReference ( GV , Mang , MMI , Encoding


<s> MRI . addLiveIn ( FlatScratchInitReg ) ; MBB . addLiveIn ( FlatScratchInitReg ) ; Register FlatScrInitLo = TRI -> getSubReg ( FlatScratchInitReg , <STR_LIT> ) ; Register FlatScrInitHi = TRI -> getSubReg ( FlatScratchInitReg , <STR_LIT> ) ; if ( ST . flatScratchIsPointer ( ) ) { if ( ST . getGeneration ( ) >= <ISA_LIT>Subtarget :: GFX10 ) { BuildMI ( MBB , I , DL , TII -> get ( <STR_LIT> ) , FlatScrInitLo ) . addReg ( FlatScrInitLo ) . addReg ( ScratchWaveOffsetReg ) ; BuildMI ( MBB , I , DL , TII -> get ( <STR_LIT> ) , FlatScrInitHi ) . addReg ( FlatScrInitHi ) . addImm ( <NUM_LIT> ) ; BuildMI ( MBB , I , DL , TII -> get ( <STR_LIT> ) ) . addReg ( FlatScrInitLo ) . addImm ( int16_t ( <STR_LIT> :: ID_FLAT_SCR_LO | ( <NUM_LIT> << <STR_LIT> :: WIDTH_M1_SHIFT_ ) ) ) ; BuildMI ( MBB , I , DL , TII -> get ( <STR_LIT> ) ) . addReg ( FlatScrInitHi ) . addImm ( int16_t ( <STR_LIT> :: ID_FLAT_SCR_HI | ( <NUM_LIT> << <STR_LIT> :: WIDTH_M1_SHIFT_ ) ) ) ; return ; } BuildMI ( MBB , I , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( FlatScrInitLo ) . addReg ( ScratchWaveOffsetReg ) ; BuildMI ( MBB , I , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( FlatScrInitHi ) . addImm ( <NUM_LIT> ) ; return ; } assert ( ST . getGeneration ( ) < <ISA_LIT>Subtarget :: GFX9 ) ; BuildMI ( MBB , I , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( FlatScrInitHi , RegState :: Kill ) ; BuildMI ( MBB , I , DL , TII -> get ( <STR_LIT> ) , FlatScrInitLo ) .


<s> StringRef RegName = getTokenStr ( ) ; const RegInfo * RI = getRegularRegInfo ( RegName ) ; if ( ! RI ) return <STR_LIT> ; lex ( ) ; RegKind = RI -> Kind ; StringRef RegSuffix = RegName . substr ( RI -> Name . size ( ) ) ; if ( ! RegSuffix . empty ( ) ) { if ( ! getRegNum ( RegSuffix , RegNum ) ) return <STR_LIT> ; RegWidth = <NUM_LIT> ; } else { if ( ! ParseRegRange ( RegNum , RegWidth ) ) return <STR_LIT> ; } return getRegularReg ( RegKind , RegNum , RegWidth


<s> int Val = cast < ConstantSDNode > ( UniquedVals [ Multiple - <NUM_LIT> ] ) -> getZExtValue ( ) ; if ( Val < <NUM_LIT> ) return DAG . getTargetConstant ( Val , SDLoc ( N ) , <STR_LIT> ) ; } if ( LeadingOnes ) { if ( ! UniquedVals [ Multiple - <NUM_LIT> ] . getNode ( ) ) return DAG . getTargetConstant ( ~ <NUM_LIT> , SDLoc ( N ) , <STR_LIT> ) ; int Val = cast < ConstantSDNode > ( UniquedVals [ Multiple - <NUM_LIT> ] ) -> getSExtValue ( ) ; if ( Val >= - <NUM_LIT> ) return DAG . getTargetConstant ( Val , SDLoc ( N ) , <STR_LIT> ) ; } return SDValue ( ) ; } for ( unsigned i = <NUM_LIT> , e = N -> getNumOperands ( ) ; i != e ; ++ i ) { if ( N -> getOperand ( i ) . isUndef ( ) ) continue ; if ( ! OpVal . getNode ( ) ) OpVal = N -> getOperand ( i ) ; else if ( OpVal != N -> getOperand ( i ) ) return SDValue ( ) ; } if ( ! OpVal . getNode ( ) ) return SDValue ( ) ; unsigned ValSizeInBytes = EltSize ; uint64_t Value =


<s> if ( MI -> getOperand ( Op ) . isFI ( ) ) return true ; return Op + <NUM_LIT> <= MI -> getNumOperands ( ) && MI -> getOperand ( Op + <NUM_LIT> ) .


<s> Op0 = TOS = Dest ; KillsOp0 = true ; } assert ( ( TOS == Op0 || TOS == Op1 ) && ( KillsOp0 || KillsOp1 ) && <STR_LIT> ) ; ArrayRef < TableEntry > InstTable ; bool isForward = TOS == Op0 ; bool updateST0 = ( TOS == Op0 && ! KillsOp1 ) || ( TOS == Op1 && ! KillsOp0 ) ; if ( updateST0 ) { if ( isForward ) InstTable = ForwardST0Table ; else InstTable = ReverseST0Table ; } else { if ( isForward ) InstTable = ForwardSTiTable ; else InstTable = ReverseSTiTable ; } int Opcode = Lookup ( InstTable , MI . getOpcode ( ) ) ; assert ( Opcode != - <NUM_LIT> && <STR_LIT> ) ; unsigned NotTOS = ( TOS == Op0 ) ? Op1 : Op0 ; MBB -> remove ( & * I ++ ) ; I = BuildMI ( * MBB , I , dl , TII -> get ( Opcode ) ) . addReg ( getSTReg ( NotTOS ) ) ; if ( ! MI . mayRaiseFPException ( ) ) I -> setFlag ( MachineInstr :: MIFlag :: NoFPExcept ) ; if ( KillsOp0 && KillsOp1 && Op0


<s> } if ( lra_in_progress ) { if ( ! decomposed && ! s390_decompose_address ( op , & addr ) ) return <NUM_LIT> ; decomposed = true ; } switch ( c ) { case 'Q' : if ( ! decomposed && ! s390_decompose_address ( op , & addr ) ) return <NUM_LIT> ; if ( addr . indx ) return <NUM_LIT> ; if ( ! s390_short_displacement ( addr . disp ) ) return <NUM_LIT> ; break ; case 'R' : if ( TARGET_LONG_DISPLACEMENT ) { if ( ! decomposed && ! s390_decompose_address ( op , & addr ) ) return <NUM_LIT> ; if ( ! s390_short_displacement ( addr . disp ) ) return <NUM_LIT> ; } break ; case 'S' : if ( ! decomposed && ! s390_decompose_address ( op


<s> return DAG . getNode ( <STR_LIT> , dl , Ty , getZero ( dl , <STR_LIT> , DAG ) ) ; } if ( Ty . isInteger ( ) ) return DAG . getConstant ( <NUM_LIT> , dl , Ty ) ; if ( Ty . isFloatingPoint ( ) ) return DAG . getConstantFP ( <NUM_LIT> , dl , Ty ) ; llvm_unreachable ( <STR_LIT> )


<s> TargetRegistry :: RegisterMCSubtargetInfo ( * T , <ISA_LIT>_MC :: create<ISA_LIT>MCSubtargetInfo ) ; TargetRegistry :: RegisterMCInstrAnalysis ( * T , create<ISA_LIT>MCInstrAnalysis ) ; TargetRegistry :: RegisterELFStreamer ( * T , createELFStreamer ) ; TargetRegistry :: RegisterCOFFStreamer ( * T , create<ISA_LIT>WinCOFFStreamer ) ; TargetRegistry :: RegisterMachOStreamer ( * T , create<ISA_LIT>MachOStreamer ) ; TargetRegistry :: RegisterObjectTargetStreamer ( * T , create<ISA_LIT>ObjectTargetStreamer ) ; TargetRegistry :: RegisterAsmTargetStreamer ( * T , create<ISA_LIT>TargetAsmStreamer ) ; TargetRegistry :: RegisterNullTargetStreamer ( * T , create<ISA_LIT>NullTargetStreamer ) ; TargetRegistry :: RegisterMCInstPrinter ( * T , create<ISA_LIT>MCInstPrinter


<s> return ( int16x4_t ) __builtin_neon_vqnegv4hi (


<s> if ( ! getTargetStreamer ( ) ) return ; if ( TM . getTargetTriple ( ) . getOS ( ) != Triple :: AMDHSA || isHsaAbiVersion2 ( getGlobalSTI ( ) ) ) getTargetStreamer ( ) -> EmitISAVersion ( ) ; if ( TM . getTargetTriple ( ) . getOS (


<s> SDValue <ISA_LIT>TargetLowering :: LowerFormalArguments ( SDValue Chain , CallingConv :: ID CallConv , bool isVarArg , const SmallVectorImpl < <STR_LIT> > & Ins , const SDLoc & dl , SelectionDAG & DAG ,

SmallVectorImpl < SDValue > & InVals ) const {


<s> } ) != To -> getParent ( ) -> rend ( ) ) ; for ( -- To ; To != From ; -- To ) { const MachineInstr & Instr = * To ; if ( ( ( AccessToCheck & AK_Write ) && Instr . modifiesRegister ( <STR_LIT> , TRI ) ) || ( ( AccessToCheck &

AK_Read ) && Instr . readsRegister ( <STR_LIT> , TRI ) ) ) return true ;


<s> bool <ISA_LIT>TargetLowering :: shouldExpandAtomicLoadInIR ( LoadInst * LI ) const { return LI -> getType ( ) -> getPrimitiveSizeInBits (


<s> while ( W > <NUM_LIT> && RC [ W - <NUM_LIT> ] . is ( <NUM_LIT> ) ) W -- ; if ( W == <NUM_LIT> || W == RC . width ( ) ) return false ; unsigned NewOpc = ( W == <NUM_LIT> ) ? <STR_LIT> : ( W == <NUM_LIT> ) ? <STR_LIT> : ( W < <NUM_LIT> ) ? <STR_LIT> : <STR_LIT> ; MachineBasicBlock & B = * MI -> getParent ( ) ; DebugLoc DL = MI -> getDebugLoc ( ) ; for ( auto & Op : MI -> uses ( ) ) { if ( ! Op . isReg ( ) ) continue ; BitTracker :: RegisterRef RS = Op ; if ( ! BT . has ( RS . Reg ) ) continue ; const BitTracker :: RegisterCell & SC = BT . lookup ( RS . Reg ) ; unsigned BN , BW ; if ( ! HBS :: getSubregMask ( RS , BN , BW , MRI ) ) continue ; if ( BW < W || ! HBS :: isEqual ( RC , <NUM_LIT> , SC , BN , W ) ) continue ; unsigned NewR = MRI . createVirtualRegister ( & <STR_LIT> ) ; auto At = MI -> isPHI ( ) ? B . getFirstNonPHI ( ) : MachineBasicBlock :: iterator ( MI ) ; auto MIB = BuildMI ( B , At , DL , HII . get ( NewOpc ) , NewR ) . addReg ( RS . Reg , <NUM_LIT> , RS . Sub ) ; if ( NewOpc == <STR_LIT> ) MIB . addImm ( ( <NUM_LIT> << W ) - <NUM_LIT> ) ; else if ( NewOpc == <STR_LIT> ) MIB . addImm ( W ) . addImm ( <NUM_LIT> ) ; HBS :: replaceSubWithSub ( RD . Reg , RD . Sub , NewR , <NUM_LIT>


<s> break ; } case CodeModel :: Large : { EmitHiLo ( * OutStreamer , GOTLabel , <ISA_LIT>MCExpr :: VK_<ISA_LIT>_HH , <ISA_LIT>MCExpr :: VK_<ISA_LIT>_HM , MCRegOP , OutContext , STI ) ; MCOperand imm = MCOperand :: createExpr ( MCConstantExpr :: create ( <NUM_LIT> , OutContext ) ) ; EmitSHL ( * OutStreamer , MCRegOP , imm , MCRegOP , STI ) ; MCOperand RegO7 = MCOperand :: createReg ( <STR_LIT> ) ; EmitHiLo ( * OutStreamer , GOTLabel , <ISA_LIT>MCExpr :: VK_<ISA_LIT>_HI , <ISA_LIT>MCExpr :: VK_<ISA_LIT>_LO , RegO7 , OutContext , STI ) ; EmitADD ( * OutStreamer , MCRegOP , RegO7 , MCRegOP , STI ) ; } } return ; } MCSymbol * StartLabel = OutContext . createTempSymbol ( ) ; MCSymbol * EndLabel = OutContext . createTempSymbol ( ) ; MCSymbol * SethiLabel = OutContext . createTempSymbol ( ) ; MCOperand RegO7 = MCOperand :: createReg ( <STR_LIT> ) ; OutStreamer -> EmitLabel ( StartLabel ) ; MCOperand Callee = createPCXCallOP ( EndLabel , OutContext ) ; EmitCall ( * OutStreamer , Callee , STI ) ; OutStreamer -> EmitLabel ( SethiLabel ) ; MCOperand hiImm = createPCXRelExprOp ( <ISA_LIT>MCExpr :: VK_<ISA_LIT>_PC22 , GOTLabel , StartLabel , SethiLabel , OutContext ) ; EmitSETHI ( * OutStreamer , hiImm , MCRegOP ,


<s> const <ISA_LIT>Subtarget & STI = MF -> getSubtarget < <ISA_LIT>Subtarget > ( ) ; bool UseSplitPush = STI . splitFramePushPop ( ) ; const MCPhysReg * RegList = STI . isTargetDarwin ( ) ? CSR_iOS_SaveList : ( UseSplitPush ? CSR_AAPCS_SplitPush_SaveList : CSR_AAPCS_SaveList ) ; const Function * F = MF -> getFunction ( ) ; if ( F -> getCallingConv ( ) == CallingConv :: GHC ) { return CSR_NoRegs_SaveList


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : break ; } switch ( Opc2 ) { default : return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> int XLenInBytes = Subtarget . getXLen ( ) / <NUM_LIT> ; EVT VT = Op . getValueType ( ) ; SDLoc DL ( Op ) ; SDValue FrameAddr = DAG . getCopyFromReg ( DAG . getEntryNode ( ) , DL , FrameReg , VT ) ; unsigned Depth = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) )


% <NUM_LIT> == <NUM_LIT> ) return TypeWidenVector ;


<s> case <STR_LIT> : case <STR_LIT> : Scale = <NUM_LIT> ; if ( Offset < <NUM_LIT> ) { NumBits = <NUM_LIT> ; Offset = - Offset ; } else { NumBits = <NUM_LIT> ; } break ; case <STR_LIT> : NumBits = <NUM_LIT> ; Scale = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : NumBits = <NUM_LIT> ; break ; case <STR_LIT> : NumBits = <NUM_LIT> ; break ; case <STR_LIT> : NumBits = ( BaseReg == <STR_LIT> ? <NUM_LIT> : <NUM_LIT> ) ; Scale = <NUM_LIT> ; isSigned = false ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } Offset += getFrameIndexInstrOffset ( MI , i ) ; if ( ( Offset & ( Scale - <NUM_LIT> ) )


<s> mips_va_arg ( valist , type ) { \ if ( TARGET_MIPS16 ) \ sorry ( <STR_LIT> ) ; \ fprintf ( FILE , <STR_LIT> ) ; \ fprintf ( FILE , <STR_LIT> , \ reg_names [ GP_REG_FIRST + <NUM_LIT> ] , reg_names [ GP_REG_FIRST + <NUM_LIT> ] ) ; \ fprintf ( FILE , \ <STR_LIT> , \ TARGET_64BIT

? <STR_LIT> : <STR_LIT> , \ reg_names [ STACK_POINTER_REGNUM ] , \ reg_names [ STACK_POINTER_REGNUM ] , \ Pmode == DImode ? <NUM_LIT> : <NUM_LIT> ) ; \ fprintf ( FILE , <STR_LIT> ) ; \ fprintf ( FILE , <STR_LIT> ) ; \ }


<s> default : llvm_unreachable ( <STR_LIT> ) ; case InlineAsm :: Constraint_i : case InlineAsm :: Constraint_o : case InlineAsm :: Constraint_v : case InlineAsm :: Constraint_m : case InlineAsm :: Constraint_X : if ( ! selectAddr ( nullptr , Op , Op0 , Op1 , Op2 , Op3 , Op4 ) )


<s> if ( skipFunction ( * MF . getFunction ( ) ) ) return false ; return fixupLoopInstrs ( MF


<s> MachineBasicBlock & FirstMBB = MF -> front ( ) ; MachineBasicBlock :: iterator MBBI = FirstMBB . begin ( ) ; MachineRegisterInfo & RegInfo = MF -> getRegInfo ( ) ; const TargetInstrInfo * TII = MF -> getTarget ( ) . getInstrInfo ( ) ; GlobalBaseReg = RegInfo . createVirtualRegister ( <STR_LIT> ) ; bool Ok = TII -> copyRegToReg ( FirstMBB , MBBI , GlobalBaseReg , <STR_LIT> , <STR_LIT> , <STR_LIT> ) ; assert ( Ok && <STR_LIT> ) ; Ok =


<s> MachineBasicBlock :: iterator NextI = I ; ++ NextI ; if ( NextI == MergeMI ) ++ NextI ; unsigned Opc = I -> getOpcode ( ) ; bool IsScaled = ! TII -> isUnscaledLdSt ( Opc ) ; int OffsetStride = IsScaled ? <NUM_LIT> : getMemScale ( * I ) ; bool MergeForward = Flags . getMergeForward ( ) ; MachineBasicBlock :: iterator InsertionPoint = MergeForward ? MergeMI : I ; const MachineOperand & BaseRegOp = MergeForward ? getLdStBaseOp ( * MergeMI ) : getLdStBaseOp ( * I ) ; MachineInstr * RtMI ; if ( getLdStOffsetOp ( * I ) . getImm ( ) == getLdStOffsetOp ( * MergeMI ) . getImm ( ) + OffsetStride ) RtMI = & * MergeMI ; else RtMI = & * I ; int OffsetImm = getLdStOffsetOp ( * RtMI )


<s> bool <ISA_LIT>16Attr = FnAttrs . hasAttribute ( AttributeSet :: FunctionIndex , <STR_LIT> ) ; bool No<ISA_LIT>16Attr = FnAttrs . hasAttribute ( AttributeSet :: FunctionIndex , <STR_LIT> ) ; assert ( ! ( <ISA_LIT>16Attr && No<ISA_LIT>16Attr ) && <STR_LIT> ) ; if ( <ISA_LIT>16Attr ) Subtarget = & <ISA_LIT>16Subtarget ; else if ( No<ISA_LIT>16Attr ) Subtarget = & No<ISA_LIT>16Subtarget ; else Subtarget =


<s> Known . One &= Known2 . One ; break ; } case <STR_LIT> : { ConstantSDNode * CN = cast < ConstantSDNode > ( Op -> getOperand ( <NUM_LIT> ) ) ; <STR_LIT> IntID = static_cast < <STR_LIT> > ( CN -> getZExtValue ( ) ) ; switch ( IntID ) { default : return ; case <STR_LIT> : case <STR_LIT> : { unsigned BitWidth = Known . getBitWidth ( ) ; EVT VT = cast < MemIntrinsicSDNode > ( Op ) -> getMemoryVT ( ) ; unsigned MemBits = VT . getScalarSizeInBits ( ) ; Known . Zero |= APInt :: getHighBitsSet ( BitWidth , BitWidth - MemBits ) ; return ; } } break ; } case <STR_LIT> : case <STR_LIT> : { unsigned IntNo = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; switch ( IntNo ) { default : break ; case <STR_LIT> : case <STR_LIT> : { MVT VT = Op . getOperand ( <NUM_LIT> ) . getValueType ( ) . getSimpleVT ( ) ; unsigned BitWidth = Known . getBitWidth ( ) ; if ( VT == <STR_LIT> || VT == <STR_LIT> ) { assert ( BitWidth >= <NUM_LIT> && <STR_LIT> ) ; APInt Mask = APInt :: getHighBitsSet ( BitWidth , BitWidth - <NUM_LIT> ) ; Known . Zero |= Mask ; } else if ( VT == <STR_LIT> || VT == <STR_LIT> ) { assert ( BitWidth >= <NUM_LIT> && <STR_LIT> ) ; APInt Mask = APInt :: getHighBitsSet ( BitWidth , BitWidth - <NUM_LIT> ) ; Known . Zero


<s> void <ISA_LIT>MCInstLower :: Lower ( const MachineInstr * MI , MCInst & OutMI ) const { OutMI . setOpcode ( MI -> getOpcode ( )


<s> aarch64_add_offset ( Pmode , stack_pointer_rtx , stack_pointer_rtx , - delta ,


<s> if ( RC == & <STR_LIT> ) return <STR_LIT> ; if ( RC == & <STR_LIT> ) return <STR_LIT> ; if ( RC == & <STR_LIT> ) return <STR_LIT> ; if ( RC == & <STR_LIT>


<s> Imm = ( short ) CN -> getZExtValue ( ) ; if ( vt . getSimpleVT ( ) >= <STR_LIT> && vt . getSimpleVT ( ) <= <STR_LIT> ) { return true ; } else if ( vt == <STR_LIT> ) { int32_t i_val = ( int32_t ) CN -> getZExtValue


<s> ablock * selectRegion ( ablock_set & regions ) { ablock * minID = NULL ; for ( ablock_set :: iterator i ( regions . begin ( ) ) , ie ( regions . end ( ) ) ; i != ie ; i ++


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerShift ( Op . getNode ( ) , DAG , Subtarget ) ; case <STR_LIT> : return LowerShiftLeftParts ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerShiftRightParts ( Op , DAG ) ; case <STR_LIT> : return LowerCTTZ ( Op . getNode ( ) , DAG , Subtarget ) ; case <STR_LIT> : return LowerCTPOP ( Op . getNode ( ) , DAG , Subtarget ) ; case <STR_LIT> : return LowerVSETCC ( Op , DAG ) ; case <STR_LIT> : return LowerConstantFP ( Op , DAG , Subtarget ) ; case <STR_LIT> : return LowerBUILD_VECTOR ( Op , DAG , Subtarget ) ; case <STR_LIT> : return LowerVECTOR_SHUFFLE ( Op , DAG ) ; case <STR_LIT> : return LowerINSERT_VECTOR_ELT ( Op , DAG ) ; case <STR_LIT> : return LowerEXTRACT_VECTOR_ELT ( Op , DAG ) ; case <STR_LIT> : return LowerCONCAT_VECTORS ( Op , DAG ) ; case <STR_LIT> : return LowerFLT_ROUNDS_ ( Op , DAG ) ; case <STR_LIT> : return LowerMUL ( Op , DAG ) ; case <STR_LIT> : return LowerSDIV ( Op , DAG ) ; case <STR_LIT> : return LowerUDIV ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerADDC_ADDE_SUBC_SUBE ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerAtomicLoadStore ( Op , DAG ) ; case <STR_LIT> : return LowerNaClTpTlsOffset ( Op , DAG ) ; case <STR_LIT> : return LowerNaClTpTdbOffset ( Op , DAG ) ; case <STR_LIT> : return LowerNaClTargetArch ( Op


<s> void <ISA_LIT>AsmPrinter :: EmitToStreamer ( MCStreamer & S , const MCInst & Inst ) { MCInst CInst


<s> const <ISA_LIT>RegisterInfo * TRI = static_cast < const <ISA_LIT>RegisterInfo * > ( DAG . getTarget ( ) . getRegisterInfo ( ) ) ; if ( TRI -> hasBasePointer ( DAG . getMachineFunction ( ) ) && TRI -> getBaseRegister ( ) == <STR_LIT> ) return SDValue ( ) ; MVT AVT ; if ( Align & <NUM_LIT> ) AVT = <STR_LIT> ; else if ( Align & <NUM_LIT> ) AVT = <STR_LIT> ; else if ( Align & <NUM_LIT> ) AVT = <STR_LIT> ; else AVT = Subtarget . is64Bit ( ) ? <STR_LIT> : <STR_LIT> ; unsigned UBytes = AVT . getSizeInBits ( ) / <NUM_LIT> ; unsigned CountVal = SizeVal / UBytes ; SDValue Count = DAG . getIntPtrConstant ( CountVal ) ; unsigned BytesLeft = SizeVal % UBytes ; SDValue InFlag ; Chain = DAG . getCopyToReg ( Chain , dl , Subtarget . is64Bit ( ) ? <STR_LIT> : <STR_LIT> , Count , InFlag ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; Chain = DAG . getCopyToReg ( Chain , dl , Subtarget . is64Bit ( ) ? <STR_LIT> : <STR_LIT> , Dst , InFlag ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; Chain = DAG . getCopyToReg ( Chain , dl , Subtarget . is64Bit ( ) ? <STR_LIT> : <STR_LIT> , Src


<s> if ( ! Subtarget . has<ISA_LIT>64 ( ) ) PM . add ( create<ISA_LIT>EmitGPRestorePass ( *


<s> while ( Carry . getOpcode ( ) == <STR_LIT> ) Carry = Carry . getOperand ( <NUM_LIT> ) ; return Carry . getOpcode ( )


<s> if ( ( rotr32 ( <NUM_LIT> , RotAmt ) & V ) == V ) return ( rotr32 ( V , <NUM_LIT> - RotAmt ) & <NUM_LIT> ) |

( ( RotAmt + <NUM_LIT> ) << <NUM_LIT> ) ;


<s> if ( <ISA_LIT>SinglePathInfo :: isEnabled ( ) ) { addPass ( createUnifyFunctionExitNodesPass ( ) ) ; addPass ( createLowerSwitchPass ( ) ) ; addPass ( create<ISA_LIT>SPClonePass ( )


<s> unsigned FrameReg ; if ( FrameIndex >= MinCSFI && FrameIndex <= MaxCSFI ) FrameReg = <STR_LIT> ; else { const TargetFrameLowering * TFI = MF . getSubtarget ( ) . getFrameLowering ( ) ; if ( TFI -> hasFP ( MF ) ) { FrameReg = <STR_LIT> ; } else { if ( ( MI . getNumOperands ( ) > OpNo + <NUM_LIT> ) && MI . getOperand ( OpNo + <NUM_LIT> ) . isReg ( ) ) FrameReg = MI . getOperand ( OpNo + <NUM_LIT> ) . getReg ( ) ; else FrameReg = <STR_LIT> ; } } int64_t Offset ; bool IsKill = false ; Offset = SPOffset + ( int64_t ) StackSize ; Offset += MI . getOperand ( OpNo + <NUM_LIT> ) . getImm ( ) ; LLVM_DEBUG ( errs ( ) << <STR_LIT> << Offset << <STR_LIT> << <STR_LIT> ) ; if ( ! MI . isDebugValue ( ) && ! <ISA_LIT>InstrInfo :: validImmediate ( MI . getOpcode ( ) , FrameReg , Offset ) ) { MachineBasicBlock & MBB = * MI . getParent ( ) ; DebugLoc DL = II -> getDebugLoc ( ) ; unsigned NewImm ; const <ISA_LIT>InstrInfo & TII = * static_cast < const <ISA_LIT>InstrInfo * > ( MF . getSubtarget ( ) . getInstrInfo ( ) ) ; FrameReg = TII . loadImmediate ( FrameReg , Offset , MBB , II ,


<s> if ( getParser ( ) . parseExpression ( EVal , E ) ) return true ; Operands . push_back ( <ISA_LIT>Operand :: CreateImm ( EVal , S , E ) ) ; return


<s> MCAsmParser & Parser = getParser ( ) ; const MCExpr * Value ; if ( getParser ( ) . parseExpression ( Value


<s> CV . push_back ( ConstantFP :: get ( APFloat ( APInt ( <NUM_LIT> , ~ ( <NUM_LIT> << <NUM_LIT> ) ) ) ) ) ; CV . push_back ( ConstantFP :: get ( APFloat ( APInt ( <NUM_LIT> , <NUM_LIT> ) ) ) ) ; } else { CV . push_back ( ConstantFP :: get ( APFloat ( APInt ( <NUM_LIT> , ~ ( <NUM_LIT> << <NUM_LIT> ) ) ) ) ) ; CV . push_back ( ConstantFP :: get ( APFloat ( APInt ( <NUM_LIT> , <NUM_LIT> ) ) ) ) ; CV . push_back ( ConstantFP :: get ( APFloat ( APInt ( <NUM_LIT> , <NUM_LIT> ) ) ) ) ; CV . push_back ( ConstantFP :: get ( APFloat ( APInt ( <NUM_LIT> , <NUM_LIT> ) ) ) ) ; } C = ConstantVector :: get ( CV ) ; CPIdx = DAG . getConstantPool ( C , getPointerTy ( ) , <NUM_LIT> ) ; SDValue Mask2 = DAG . getLoad ( VT , dl , DAG . getEntryNode ( ) , CPIdx , PseudoSourceValue :: getConstantPool ( ) , <NUM_LIT> , false , <NUM_LIT> ) ; SDValue Val = DAG . getNode ( <STR_LIT> , dl , VT , Op0 , Mask2 ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Val ,


<s> const GlobalValue * GV = cast < GlobalValue > ( ( * MI -> memoperands_begin ( ) ) -> getValue ( ) ) ; MachineInstrBuilder MIB ; BuildMI ( MBB , MI , DL , get ( LoadImmOpc ) , Reg ) . addGlobalAddress ( GV , <NUM_LIT> , <STR_LIT> ) ; if ( Subtarget . isGVIndirectSymbol ( GV ) ) { MIB = BuildMI ( MBB , MI , DL , get ( LoadOpc ) , Reg ) ; MIB . addReg ( Reg , RegState :: Kill ) . addImm ( <NUM_LIT> ) ; auto Flags = MachineMemOperand :: MOLoad | MachineMemOperand ::


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . setPreservesCFG ( ) ; AU . addPreservedID ( MachineLoopInfoID ) ; AU . addPreservedID (


<s> bool noCost ( ) const { return ( GroupingCost <= <NUM_LIT> &&


<s> if ( ( FirstOpcode == <STR_LIT> || FirstOpcode == <STR_LIT> ) && SecondOpcode == <STR_LIT> ) return true ; else if ( ( FirstOpcode == <STR_LIT> || FirstOpcode == <STR_LIT> ) && ( SecondOpcode == <STR_LIT> && SecondMI . getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) ) return true ; else if ( ( FirstOpcode == <STR_LIT> || FirstOpcode == <STR_LIT> ) && ( SecondOpcode == <STR_LIT> &&


<s> S = Decode3OpInstruction ( fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) , Op4 , Op5 , Op6 ) ; if ( S != MCDisassembler :: Success ) return S ; DecodeGRRegsRegisterClass ( Inst , Op1 , Address , Decoder ) ; DecodeGRRegsRegisterClass ( Inst , Op4 , Address , Decoder ) ; DecodeGRRegsRegisterClass ( Inst , Op2 , Address , Decoder ) ; DecodeGRRegsRegisterClass ( Inst , Op3 , Address , Decoder ) ; DecodeGRRegsRegisterClass ( Inst , Op5 , Address , Decoder ) ; DecodeGRRegsRegisterClass ( Inst , Op6


<s> virtual const <ISA_LIT>InstrInfo * getInstrInfo ( ) const { return &


<s> if ( ! f64RetAssign ( ValNo , ValVT , LocVT , LocInfo , State ) ) return false ; if ( LocVT == <STR_LIT> && ! f64RetAssign ( ValNo , ValVT , LocVT , LocInfo , State )


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const { MachineFunctionPass :: getAnalysisUsage (


<s> MinSVEVectorSize *= <NUM_LIT> ; MaxSVEVectorSize *= <NUM_LIT> ; } else { MinSVEVectorSize = SVEVectorBitsMinOpt ; MaxSVEVectorSize = SVEVectorBitsMaxOpt ; } assert ( MinSVEVectorSize % <NUM_LIT> == <NUM_LIT> && <STR_LIT> ) ; assert ( MaxSVEVectorSize % <NUM_LIT> == <NUM_LIT> && <STR_LIT> ) ; assert ( ( MaxSVEVectorSize >= MinSVEVectorSize || MaxSVEVectorSize == <NUM_LIT> ) && <STR_LIT> ) ; if ( MaxSVEVectorSize == <NUM_LIT> ) MinSVEVectorSize = ( MinSVEVectorSize / <NUM_LIT> ) * <NUM_LIT> ; else { MinSVEVectorSize = ( std :: min ( MinSVEVectorSize , MaxSVEVectorSize ) / <NUM_LIT> ) * <NUM_LIT> ; MaxSVEVectorSize = ( std :: max ( MinSVEVectorSize , MaxSVEVectorSize ) / <NUM_LIT> ) * <NUM_LIT> ; } Key += <STR_LIT> ; Key += std :: to_string ( MinSVEVectorSize ) ; Key += <STR_LIT> ; Key += std :: to_string ( MaxSVEVectorSize ) ; Key += CPU ; Key += TuneCPU ; Key += FS ; auto & I = SubtargetMap [


<s> addPass ( create<ISA_LIT>ModuleISelDag ( get<ISA_LIT>TargetMachine ( ) ) ) ; addPass ( create<ISA_LIT>16ISelDag ( get<ISA_LIT>TargetMachine ( ) ) ) ; addPass ( create<ISA_LIT>SEISelDag ( get<ISA_LIT>TargetMachine


<s> SUnit * R600SchedStrategy :: pickOther ( int QID ) { SUnit * SU = nullptr ; std :: vector < SUnit * > & AQ = Available [ QID ] ; if ( AQ . empty ( ) ) { MoveUnits ( Pending [ QID ] , AQ ) ; } if ( ! AQ . empty ( ) ) { SU = AQ . back ( ) ; AQ . resize ( AQ . size ( ) - <NUM_LIT> ) ; } return SU


<s> Register <ISA_LIT>TargetLowering :: getRegisterByName ( const char * RegName , EVT VT , const


<s> HOST_WIDE_INT size = int_size_in_bytes ( type ) ; return ( size == - <NUM_LIT> || size >


<s> static EVT memVTFromImageReturn ( Type * Ty , unsigned DMaskLanes ) { auto * ST = dyn_cast < StructType > ( Ty ) ; if ( ! ST ) return memVTFromImageData ( Ty


<s> machine_mode dst_inner = ( GET_CODE ( dst ) == SUBREG ? GET_MODE ( XEXP ( dst , <NUM_LIT> ) ) : dst_mode ) ; machine_mode src_inner = ( GET_CODE ( src ) == SUBREG ? GET_MODE ( XEXP ( src , <NUM_LIT> ) ) : dst_mode ) ; rtx sym = src ; if ( GET_CODE ( sym ) == CONST ) sym = XEXP ( XEXP ( sym , <NUM_LIT> ) , <NUM_LIT> ) ; if ( SYMBOL_REF_P ( sym ) ) { if ( SYMBOL_DATA_AREA ( sym ) != DATA_AREA_GENERIC ) return <STR_LIT> ; nvptx_maybe_record_fnsym ( sym ) ; } if ( src_inner == dst_inner ) return <STR_LIT> ; if ( CONSTANT_P ( src ) ) return ( GET_MODE_CLASS ( dst_inner ) == MODE_INT && GET_MODE_CLASS ( src_inner ) != MODE_FLOAT ? <STR_LIT> : <STR_LIT> ) ; if ( GET_MODE_SIZE ( dst_inner ) == GET_MODE_SIZE ( src_inner ) ) return <STR_LIT> ; return


<s> if ( OptLevel == <NUM_LIT> ) return false ; if ( MF . getTarget ( ) . Options . AllowFPOpFusion == FPOpFusion


<s> SDValue <ISA_LIT>TargetLowering :: LowerLOAD ( SDValue Op , SelectionDAG & DAG ) const { LoadSDNode * load = static_cast < LoadSDNode * > ( Op . getNode ( ) ) ; assert ( load -> getMemoryVT ( ) == <STR_LIT> ) ; SDValue newLoad = DAG . getLoad ( <STR_LIT> , <STR_LIT> , <STR_LIT> , Op , load -> getChain ( ) , load -> getBasePtr ( ) , load -> getOffset ( ) , <STR_LIT> , load -> getMemOperand ( ) ) ; SDValue newTrunc = DAG . getZExtOrTrunc ( newLoad , Op , <STR_LIT> ) ; SDValue Ops [ <NUM_LIT> ] = { newTrunc , newLoad .


<s> OS << <STR_LIT> << Opcode << <STR_LIT> << decIncOperator ( MI ) << <STR_LIT> << getRegisterName ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) << <STR_LIT> << getRegisterName ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; return true ; } if ( isPostIncrementForm ( MI


<s> static rtx mmix_function_incoming_arg ( cumulative_args_t argsp , machine_mode mode , const_tree type ,


<s> static DecodeStatus DecodeRRegsRegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t Address , const void * Decoder ) { if ( RegNo > <NUM_LIT> ) return MCDisassembler :: Fail ; Inst . addOperand ( MCOperand :: createReg ( RRegsTable [ RegNo ] ) ) ; return MCDisassembler ::


<s> else snprintf ( pattern , sizeof ( pattern ) , <STR_LIT> <STR_LIT> <STR_LIT> ) ; } else { if ( TARGET_RELAX_HINT ) snprintf ( pattern , sizeof ( pattern ) , <STR_LIT> <STR_LIT> ) ; else snprintf ( pattern , sizeof ( pattern ) , <STR_LIT> <STR_LIT> ) ; } output_asm_insn ( pattern , operands


<s> } SMLoc S = Tok . getLoc ( ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateSysReg ( Tok . getString ( ) , S ) ) ; Parser . Lex


<s> if ( Subtarget . is<ISA_LIT>64 ( ) && Directive < <STR_LIT> ) Directive = <STR_LIT> ; assert ( Directive <= <STR_LIT> && <STR_LIT> ) ; if ( OutStreamer . hasRawTextSupport ( ) ) { assert ( Directive < sizeof ( CPUDirectives ) / sizeof ( * CPUDirectives ) && <STR_LIT> ) ; OutStreamer . EmitRawText ( <STR_LIT> + Twine ( CPUDirectives [ Directive ] ) ) ; } const TargetLoweringObjectFileMachO & TLOFMacho = static_cast < const TargetLoweringObjectFileMachO & > ( getObjFileLowering ( ) ) ; OutStreamer . SwitchSection ( TLOFMacho . getTextCoalSection ( ) ) ; if ( TM . getRelocationModel ( ) == Reloc :: PIC_ ) { OutStreamer . SwitchSection ( OutContext . getMachOSection ( <STR_LIT> , <STR_LIT> , MCSectionMachO :: S_SYMBOL_STUBS | MCSectionMachO :: S_ATTR_PURE_INSTRUCTIONS , <NUM_LIT> , SectionKind :: getText ( ) ) ) ; } else if ( TM . getRelocationModel ( )


<s> return ( ( ( TARGET_SHMEDIA ? <NUM_LIT> : TARGET_FMOVD ? <NUM_LIT> : <NUM_LIT> ) + addend ) * ( ( GET_MODE_SIZE ( mode ) + <NUM_LIT> ) / <NUM_LIT> ) ) ; } if ( ( dstclass == FPUL_REGS && REGCLASS_HAS_GENERAL_REG ( srcclass ) ) || ( srcclass == FPUL_REGS && REGCLASS_HAS_GENERAL_REG ( dstclass ) ) ) return <NUM_LIT> ; if ( ( dstclass == FPUL_REGS && ( srcclass == PR_REGS || srcclass == MAC_REGS || srcclass == T_REGS ) ) || ( srcclass == FPUL_REGS && ( dstclass == PR_REGS || dstclass == MAC_REGS ) ) ) return <NUM_LIT> ; if ( ( srcclass == TARGET_REGS && ! REGCLASS_HAS_GENERAL_REG ( dstclass ) ) || ( ( dstclass ) == TARGET_REGS && ! REGCLASS_HAS_GENERAL_REG ( srcclass ) ) ) return <NUM_LIT> ; if ( TARGET_SHMEDIA && ( ( srcclass ) == TARGET_REGS || ( srcclass ) == SIBCALL_REGS ) ) { if ( sh_gettrcost >= <NUM_LIT> ) return sh_gettrcost ; else if ( ! TARGET_PT_FIXED ) return <NUM_LIT> ; } if ( ( srcclass == FPSCR_REGS && ! REGCLASS_HAS_GENERAL_REG ( dstclass ) ) || ( dstclass == FPSCR_REGS && ! REGCLASS_HAS_GENERAL_REG ( srcclass ) ) ) return <NUM_LIT> ; if ( TARGET_SHMEDIA || ( TARGET_FMOVD && ! REGCLASS_HAS_GENERAL_REG ( srcclass ) && ! REGCLASS_HAS_GENERAL_REG ( dstclass ) ) ) return <NUM_LIT> * (

( GET_MODE_SIZE ( mode ) + <NUM_LIT> ) / <NUM_LIT> ) ;


<s> if ( ! mustbelongordbl ) typedata -> base = BT_LONG ; else if ( ! strcmp ( mustbelongordbl , <STR_LIT> ) ) typedata -> base = BT_LONGLONG ; else if ( ! strcmp ( mustbelongordbl , <STR_LIT> ) ) typedata -> base = BT_LONGDOUBLE ; else { typedata -> base = BT_LONG ; pos = oldpos ; } } else if ( ! strcmp ( token , <STR_LIT> ) ) typedata -> base = BT_FLOAT ; else if ( ! strcmp ( token , <STR_LIT> ) ) typedata -> base = BT_DOUBLE ; else if ( ! strcmp ( token , <STR_LIT> ) ) typedata -> base = BT_INT128 ; else if ( ! strcmp ( token , <STR_LIT> ) ) typedata -> base = BT_FLOAT128 ; else if ( ! strcmp ( token , <STR_LIT> ) ) typedata -> base = BT_BOOL ; else if ( ! strcmp ( token , <STR_LIT> ) ) typedata -> base = BT_STRING ; else if ( ! strcmp ( token , <STR_LIT> ) ) typedata -> base = BT_DECIMAL32 ; else if ( ! strcmp ( token , <STR_LIT> ) ) typedata -> base = BT_DECIMAL64 ; else if ( ! strcmp ( token , <STR_LIT> ) ) typedata -> base = BT_DECIMAL128 ; else if ( ! strcmp ( token , <STR_LIT> ) ) typedata -> base = BT_IBM128 ; else { diag ( oldpos , <STR_LIT> ) ; return <NUM_LIT> ; } handle_pointer (


<s> static MCCodeGenInfo * create<ISA_LIT>MCCodeGenInfo ( const Triple & TT , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) { MCCodeGenInfo * X = new MCCodeGenInfo ( ) ; switch ( CM ) { default : break ; case CodeModel


<s> Offset /= <NUM_LIT> ; bool isU6 = isImmU6 ( Offset ) ; if ( ! isU6 && ! isImmU16 ( Offset ) ) report_fatal_error ( <STR_LIT> + Twine (


<s> Triple TheTriple ( TT ) ; if ( TheTriple . isOSDarwin ( ) || TheTriple . getEnvironment ( ) == Triple :: MachO ) return new Darwin<ISA_LIT>_32AsmBackend ( T

, MRI , CPU , TheTriple . isMacOSX ( ) && ! TheTriple . isMacOSXVersionLT ( <NUM_LIT> , <NUM_LIT> ) ) ;


<s> const MCConstantExpr * MCE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; if ( ! MCE ) return false ; int64_t Val = MCE -> getValue ( ) ; return ( Val >= - <NUM_LIT> && Val <= <NUM_LIT> && ( Val


<s> bool isImmCom8 ( ) const { if ( ! isImm ( ) ) return false ; const auto * CE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; if ( ! CE ) return false ; int64_t Value = CE -> getValue ( ) ; return isUInt < <NUM_LIT> > ( Value


<s> return avr_out_lpm_no_lpmx ( insn , xop , plen ) ; } switch ( GET_CODE ( addr ) ) { default : gcc_unreachable ( ) ; case REG : gcc_assert ( REG_Z == REGNO ( addr ) ) ; switch ( n_bytes ) { default : gcc_unreachable ( ) ; case <NUM_LIT> : return avr_asm_len ( <STR_LIT> , xop , plen , <NUM_LIT> ) ; case <NUM_LIT> : if ( REGNO ( dest ) == REG_Z ) return avr_asm_len ( <STR_LIT> CR_TAB <STR_LIT> CR_TAB <STR_LIT> , xop , plen , <NUM_LIT> ) ; else { avr_asm_len ( <STR_LIT> CR_TAB <STR_LIT> , xop , plen , <NUM_LIT> ) ; if ( ! reg_unused_after ( insn , addr ) ) avr_asm_len ( <STR_LIT> , xop , plen , <NUM_LIT> ) ; } break ; case <NUM_LIT> : avr_asm_len ( <STR_LIT> CR_TAB <STR_LIT> CR_TAB <STR_LIT> , xop , plen , <NUM_LIT> ) ; if ( ! reg_unused_after ( insn , addr ) ) avr_asm_len ( <STR_LIT> , xop , plen , <NUM_LIT> ) ; break ; case <NUM_LIT> : avr_asm_len ( <STR_LIT> CR_TAB <STR_LIT> , xop , plen , <NUM_LIT> ) ; if ( REGNO ( dest ) == REG_Z - <NUM_LIT> ) return avr_asm_len ( <STR_LIT> CR_TAB <STR_LIT> CR_TAB <STR_LIT> , xop , plen , <NUM_LIT> ) ; else { avr_asm_len ( <STR_LIT> CR_TAB <STR_LIT> , xop , plen , <NUM_LIT> ) ; if ( ! reg_unused_after ( insn , addr ) ) avr_asm_len ( <STR_LIT> , xop , plen , <NUM_LIT> ) ; } break ; } break ; case POST_INC : gcc_assert ( REG_Z == REGNO ( XEXP ( addr , <NUM_LIT> ) ) && n_bytes <= <NUM_LIT> ) ; avr_asm_len ( <STR_LIT> , xop , plen , <NUM_LIT> ) ; if ( n_bytes >= <NUM_LIT> ) avr_asm_len ( <STR_LIT> , xop , plen , <NUM_LIT> ) ; if ( n_bytes >= <NUM_LIT> ) avr_asm_len ( <STR_LIT> , xop , plen , <NUM_LIT> ) ; if ( n_bytes >= <NUM_LIT> ) avr_asm_len ( <STR_LIT> , xop , plen , <NUM_LIT> ) ; break ; } if ( xop [ <NUM_LIT> ] == xstring_e && AVR_HAVE_RAMPD ) { xop [ <NUM_LIT> ] = zero_reg_rtx ; avr_asm_len ( <STR_LIT> , xop ,


<s> } } else { for ( unsigned I = <NUM_LIT> ; I != VecLen ; I += <NUM_LIT> ) { unsigned B = <NUM_LIT> ; for ( ; B != <NUM_LIT> ; ++ B ) { if ( ! Values [ I + B ] . isUndef ( ) ) break ; } SDValue F = Values [ I + B ] ; AllT &= IsTrue ( F ) ; AllF &= IsFalse ( F ) ; SDValue Ext = ( B < <NUM_LIT> ) ? DAG . getZExtOrTrunc ( F , dl , <STR_LIT> ) : DAG . getUNDEF ( <STR_LIT> ) ; Bytes . push_back ( Ext ) ; for ( ; B != <NUM_LIT> ; ++ B ) assert ( Values [ I + B ] . isUndef ( ) || Values [ I + B ] == F ) ; } } if ( AllT ) return DAG . getNode ( <STR_LIT> , dl , VecTy ) ; if ( AllF ) return DAG . getNode ( <STR_LIT> , dl , VecTy ) ; MVT ByteTy = <STR_LIT> ( <STR_LIT> , HwLen ) ; SDValue ByteVec = buildHvxVectorReg ( Bytes , dl , ByteTy , DAG ) ; return DAG . getNode ( <STR_LIT> , dl , VecTy , ByteVec


<s> <ISA_LIT>GenSubtargetInfo ( TT , CPU , FS ) { std :: string


<s> static const uint16_t F64Regs [ ] = { <STR_LIT> , <STR_LIT> } ; return CC_<ISA_LIT>O32 ( ValNo , ValVT , LocVT ,

LocInfo , ArgFlags , State , F64Regs ) ;


<s> ++ NumMovwMovt ; Result = DAG . getNode ( <STR_LIT> , DL , PtrVT , DAG . getTargetGlobalAddress ( GV , DL , PtrVT , <NUM_LIT> , TargetFlags ) ) ; if ( GV -> hasDLLImportStorageClass ( ) ) Result = DAG . getLoad ( PtrVT , DL , DAG . getEntryNode ( )

, Result , MachinePointerInfo :: getGOT ( DAG . getMachineFunction ( ) ) ) ;


<s> rtx_insn * insn ; int this_reg_no ; rtx temp0 = gen_rtx_REG ( Pmode , A9_REG ) ; const char * fnname = IDENTIFIER_POINTER ( DECL_ASSEMBLER_NAME ( thunk ) ) ; reload_completed = <NUM_LIT> ; if ( aggregate_value_p ( TREE_TYPE ( TREE_TYPE ( function ) ) , function ) ) this_reg_no = <NUM_LIT> ; else this_reg_no = <NUM_LIT> ; this_rtx = gen_rtx_REG ( Pmode , A0_REG + this_reg_no ) ; if ( delta ) xtensa_emit_add_imm ( this_rtx , this_rtx , delta , temp0 , false ) ; if ( vcall_offset ) { rtx temp1 = gen_rtx_REG ( Pmode , A0_REG + <NUM_LIT> ) ; rtx addr = temp1 ; emit_move_insn ( temp0 , gen_rtx_MEM ( Pmode , this_rtx ) ) ; if ( xtensa_uimm8x4 ( vcall_offset ) ) addr = plus_constant


<s> if ( AssemblerOptions . back ( ) -> isReorder ( ) ) Warning ( Loc , <STR_LIT> ) ; SmallVector < std :: unique_ptr < MCParsedAsmOperand > , <NUM_LIT> > Reg ; OperandMatchResultTy ResTy = parseAnyRegister ( Reg ) ; if ( ResTy == MatchOperand_NoMatch || ResTy == MatchOperand_ParseFail ) { reportParseError ( <STR_LIT> ) ; return false ; } <ISA_LIT>Operand & RegOpnd = static_cast < <ISA_LIT>Operand & > ( * Reg [ <NUM_LIT> ] ) ; if ( ! RegOpnd . isGPRAsmReg ( ) ) { reportParseError ( RegOpnd . getStartLoc ( )


<s> if ( ( Val & <NUM_LIT> ) == <NUM_LIT> ) return ( uint64_t ) ( ( INT64_C ( <NUM_LIT> ) << <NUM_LIT> ) >> ( Val & <NUM_LIT> ) ) ; return ( ( uint64_t ) INT64_C ( - <NUM_LIT> ) >> (


<s> machine_mode mode ; rtx dest , vec ; dest = operands [ <NUM_LIT> ] ; vec = operands [ <NUM_LIT> ] ; mode = GET_MODE ( dest ) ; if ( TARGET_VSX ) { if ( zero_constant ( vec , mode ) ) return <STR_LIT> ; if ( ( mode == V2DImode || mode == V1TImode ) && INTVAL ( CONST_VECTOR_ELT ( vec , <NUM_LIT> ) ) == - <NUM_LIT> && INTVAL ( CONST_VECTOR_ELT ( vec , <NUM_LIT> ) ) == - <NUM_LIT> ) return <STR_LIT> ; } if ( TARGET_ALTIVEC ) { rtx splat_vec ; if ( zero_constant ( vec , mode ) ) return <STR_LIT> ; splat_vec = gen_easy_altivec_constant ( vec ) ; gcc_assert ( GET_CODE ( splat_vec ) == VEC_DUPLICATE ) ; operands [ <NUM_LIT> ] = XEXP ( splat_vec