<s> MCSymbol * Start = getContext ( ) . createTempSymbol ( ) ; EmitLabel ( Start ) ; auto * Symbol = cast < MCSymbolELF > ( getContext ( ) . getOrCreateSymbol ( Name + <STR_LIT> + Twine ( MappingSymbolCounter ++ ) ) ) ; getAssembler ( ) . registerSymbol ( * Symbol ) ; Symbol -> setType ( ELF :: STT_NOTYPE ) ; Symbol -> setBinding (


<s> bool LE = Subtarget . isLittle ( ) ; LLVMContext & Context = M -> getContext ( ) ; std :: string Name = F -> getName ( ) ; std :: string SectionName = <STR_LIT> + Name ; std :: string StubName = <STR_LIT> + Name ; std :: string LocalName = <STR_LIT> + Name ; Function * FStub = Function :: Create ( F -> getFunctionType ( ) , Function :: InternalLinkage , StubName , M ) ; FStub -> addFnAttr ( <STR_LIT> ) ; FStub -> addFnAttr ( llvm :: Attribute :: Naked ) ; FStub -> addFnAttr ( llvm :: Attribute :: NoUnwind ) ; FStub -> addFnAttr ( llvm :: Attribute :: NoInline ) ; FStub -> addFnAttr ( <STR_LIT> ) ; FStub -> setSection ( SectionName ) ; BasicBlock * BB = BasicBlock :: Create ( Context , <STR_LIT> , FStub ) ; InlineAsmHelper IAH ( Context , BB ) ; IAH . Out ( <STR_LIT> ) ; if ( PicMode ) { IAH . Out ( <STR_LIT> ) ; IAH . Out ( <STR_LIT> ) ; IAH . Out ( <STR_LIT> ) ; IAH . Out ( <STR_LIT> + Name ) ; IAH . Out ( <STR_LIT> + LocalName ) ; } else { IAH . Out ( <STR_LIT> ) ; IAH . Out ( <STR_LIT> +


<s> for ( unsigned i = <NUM_LIT> ; i < <STR_LIT> ; ++ i ) MIB . add ( MI . getOperand ( i ) ) ; MIB . setMemRefs ( MMOBegin , MMOEnd ) ; MIB = BuildMI ( * MBB , MI , DL , TII -> get ( PtrLoadOpc ) , Tmp ) ; for ( unsigned i = <NUM_LIT> ; i < <STR_LIT> ; ++ i ) { if ( i == <STR_LIT> ) MIB . addDisp ( MI . getOperand ( i ) , LabelOffset ) ; else MIB . add ( MI . getOperand ( i ) ) ; } MIB . setMemRefs ( MMOBegin , MMOEnd ) ; MIB = BuildMI ( * MBB , MI , DL , TII -> get ( PtrLoadOpc ) , SP ) ; for ( unsigned i = <NUM_LIT> ; i < <STR_LIT> ; ++ i ) { if ( i == <STR_LIT> ) MIB . addDisp ( MI . getOperand ( i ) , SPOffset ) ; else MIB . add ( MI . getOperand ( i ) ) ; } MIB . setMemRefs ( MMOBegin , MMOEnd ) ; BuildMI ( * MBB , MI , DL , TII -> get ( IJmpOpc ) ) . addReg ( Tmp ) ; MI . eraseFromParent ( ) ; return MBB


<s> assert ( MI . getDesc ( ) . isBranch (


<s> SDValue CCVal = DAG . getConstant ( <STR_LIT> , <STR_LIT> ) ; SDValue FalseValLo = DAG . getNode ( <STR_LIT> , dl , VT , Tmp1 , Tmp2 ) ; SDValue TrueValLo = DAG . getNode ( Opc , dl , VT , ShOpHi , ExtraShAmt ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , dl , VT , TrueValLo , FalseValLo , CCVal , Cmp ) ; SDValue FalseValHi = DAG . getNode ( Opc , dl , VT , ShOpHi , ShAmt ) ; SDValue TrueValHi = Opc == <STR_LIT> ? DAG . getNode ( Opc , dl , VT , ShOpHi , DAG . getConstant ( VTBits - <NUM_LIT> , <STR_LIT> ) ) : DAG . getConstant ( <NUM_LIT> , VT ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , dl , VT , TrueValHi , FalseValHi , CCVal


<s> union { __m128h a [ <NUM_LIT> ] ; __m256h v ; } u ; u . a [ <NUM_LIT>


<s> assert ( Op . getValueType ( ) == <STR_LIT> && <STR_LIT> ) ; SDValue Op0 = Op . getOperand ( <NUM_LIT> ) ; SDValue Op1 = Op . getOperand ( <NUM_LIT> ) ; DebugLoc dl = Op . getDebugLoc ( ) ; <STR_LIT> CC = cast < CondCodeSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> get ( ) ; if ( Op0 . getOpcode ( ) == <STR_LIT> && Op0 . hasOneUse ( ) && Op1 . getOpcode ( ) == <STR_LIT> && cast < ConstantSDNode > ( Op1 ) -> isNullValue ( ) && ( CC == <STR_LIT> || CC == <STR_LIT> ) ) { SDValue NewSetCC = LowerToBT ( Op0 , CC , dl , DAG ) ; if ( NewSetCC . getNode ( ) ) return NewSetCC ; } if ( Op1 . getOpcode ( ) == <STR_LIT> && ( cast < ConstantSDNode > ( Op1 ) -> getZExtValue ( ) == <NUM_LIT> || cast < ConstantSDNode > ( Op1 ) -> isNullValue ( ) ) && ( CC == <STR_LIT> || CC == <STR_LIT> ) ) { if ( Op0 . getOpcode ( )


<s> unsigned <ISA_LIT>BaseInstrInfo :: isLoadFromStackSlotPostFE ( const MachineInstr * MI , int & FrameIndex ) const { const MachineMemOperand * Dummy ; return MI -> getDesc ( ) . mayLoad ( ) && hasLoadFromStackSlot ( MI , Dummy


<s> return __builtin_mve_vabdq_m_sv16qi ( __arm_vuninitializedq_s8 ( ) , __a ,


<s> __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) __andn_u32 ( unsigned int __X , unsigned int __Y ) { return ~ __X &


<s> assert ( N -> getOpcode ( ) == <STR_LIT> ) ; SwitchEQNEToPLMI = false ; if ( ! Subtarget -> isThumb ( ) ) return ; SDValue And = N -> getOperand ( <NUM_LIT> ) ; if ( ! And -> hasOneUse ( ) ) return ; SDValue Zero = N -> getOperand ( <NUM_LIT> ) ; if ( ! isa < ConstantSDNode > ( Zero ) || ! cast < ConstantSDNode > ( Zero ) -> isZero ( ) || And -> getOpcode ( ) != <STR_LIT> ) return ; SDValue X = And . getOperand ( <NUM_LIT> ) ; auto C = dyn_cast < ConstantSDNode > ( And . getOperand ( <NUM_LIT> ) ) ; if ( ! C ) return ; auto Range = getContiguousRangeOfSetBits ( C -> getAPIntValue ( ) ) ; if ( ! Range ) return ; SDNode * NewN ; SDLoc dl ( N ) ; auto EmitShift = [ & ] ( unsigned Opc , SDValue Src , unsigned Imm ) -> SDNode * { if ( Subtarget -> isThumb2 ( ) ) { Opc = ( Opc == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; SDValue Ops [ ] = { Src , CurDAG -> getTargetConstant ( Imm , dl , <STR_LIT> ) , getAL ( CurDAG , dl ) , CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) , CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) } ; return CurDAG -> getMachineNode ( Opc , dl , <STR_LIT> , Ops ) ; } else { SDValue Ops [ ] = { CurDAG -> getRegister ( <STR_LIT> , <STR_LIT> ) , Src , CurDAG -> getTargetConstant ( Imm , dl , <STR_LIT> ) , getAL ( CurDAG , dl ) , CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) } ; return CurDAG -> getMachineNode ( Opc , dl , <STR_LIT> , Ops ) ; } } ; if ( Range -> second == <NUM_LIT> ) { NewN = EmitShift ( <STR_LIT> , X , <NUM_LIT> - Range -> first ) ; ReplaceNode ( And . getNode ( ) ,


<s> void <ISA_LIT>TargetLowering :: LowerFP_TO_INTForReuse ( SDValue Op , ReuseLoadInfo & RLI , SelectionDAG & DAG , const SDLoc & dl ) const { assert ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) . isFloatingPoint ( ) ) ; SDValue Src = Op . getOperand ( <NUM_LIT> ) ; if ( Src . getValueType ( ) == <STR_LIT> ) Src = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Src ) ; SDValue Tmp ; switch ( Op . getSimpleValueType ( ) . SimpleTy ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : Tmp = DAG . getNode ( Op . getOpcode ( ) == <STR_LIT> ? <STR_LIT> : ( Subtarget . hasFPCVT ( ) ? <STR_LIT> : <STR_LIT> ) , dl , <STR_LIT> , Src ) ; break ; case <STR_LIT> : assert ( ( Op . getOpcode ( ) == <STR_LIT> || Subtarget . hasFPCVT ( ) ) && <STR_LIT> ) ; Tmp = DAG . getNode ( Op . getOpcode ( ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> , dl , <STR_LIT> , Src ) ; break ; } bool i32Stack = Op . getValueType ( ) == <STR_LIT> && Subtarget . hasSTFIWX ( ) && ( Op . getOpcode ( ) == <STR_LIT> || Subtarget . hasFPCVT ( ) ) ; SDValue FIPtr = DAG . CreateStackTemporary ( i32Stack ? <STR_LIT> : <STR_LIT> ) ; int FI = cast < FrameIndexSDNode > ( FIPtr ) -> getIndex ( ) ; MachinePointerInfo MPI = MachinePointerInfo :: getFixedStack ( DAG . getMachineFunction ( ) , FI ) ; SDValue Chain ; Align Alignment ( DAG . getEVTAlign ( Tmp . getValueType ( )


<s> <ISA_LIT>TargetAsmStreamer * S = new <ISA_LIT>TargetAsmStreamer ( ) ; return llvm :: createAsmStreamer ( Ctx , S , OS , isVerboseAsm , useLoc , useCFI

, useDwarfDirectory , InstPrint , CE , TAB , ShowInst ) ;


<s> if ( GET_MODE_SIZE ( mode ) > UNITS_PER_WORD && ! ( TARGET_HARD_FLOAT && ( mode == DFmode || mode == DDmode ) ) ) return false ; return CONSTANT_P ( x ) || large_toc_ok ; } else if ( TARGET_MACHO ) { if ( GET_MODE_NUNITS ( mode ) != <NUM_LIT> ) return false ; if ( GET_MODE_SIZE ( mode ) > UNITS_PER_WORD && ! ( TARGET_HARD_FLOAT && ( mode == DFmode || mode == DDmode ) ) ) return false ; if ( MACHO_DYNAMIC_NO_PIC_P || ! flag_pic ) return CONSTANT_P ( x ) ; if ( GET_CODE ( x ) == CONST ) x = XEXP ( x , <NUM_LIT> ) ; if ( SYMBOL_REF_P ( x ) ) return false ; if ( GET_CODE ( x ) == UNSPEC && XINT ( x , <NUM_LIT> ) == UNSPEC_MACHOPIC_OFFSET ) return CONSTANT_P ( XVECEXP ( x ,


<s> return getSchedModel ( ) . hasInstrSchedModel ( ) &&


<s> return ( uint32x4_t ) __builtin_aarch64_uhaddv4si ( ( int32x4_t ) __a , (


<s> const std :: string & <ISA_LIT>CA53ErratumStub :: name ( ) const { return


<s> Value * <ISA_LIT>IREmitter :: visitFMIN ( const SDNode * N ) { llvm_unreachable ( <STR_LIT> ) ; return


<s> if ( old_tree != target_option_current_node ) new_tree = target_option_current_node ; else new_tree = NULL_TREE ; } else { new_tree = DECL_FUNCTION_SPECIFIC_TARGET ( fndecl ) ; if ( new_tree == NULL_TREE ) new_tree = target_option_default_node ; } if ( TARGET_DEBUG_TARGET ) { if ( new_tree ) { fprintf ( stderr , <STR_LIT> ) ; debug_tree ( new_tree ) ; } if ( old_tree ) { fprintf ( stderr , <STR_LIT> ) ; debug_tree ( old_tree ) ; } if ( old_tree != NULL_TREE || new_tree != NULL_TREE ) fprintf


<s> static const MachineOperand & getLoadStoreBaseOp ( const MachineInstr &


<s> { & getThe<ISA_LIT>32Target ( ) , & getThe<ISA_LIT>64Target ( ) , & getThe<ISA_LIT>64LETarget ( ) } ) { RegisterMCAsmInfoFn C ( * T , create<ISA_LIT>MCAsmInfo ) ; TargetRegistry :: RegisterMCInstrInfo ( * T , create<ISA_LIT>MCInstrInfo ) ; TargetRegistry :: RegisterMCRegInfo ( * T , create<ISA_LIT>MCRegisterInfo ) ; TargetRegistry :: RegisterMCSubtargetInfo ( * T , create<ISA_LIT>MCSubtargetInfo ) ; TargetRegistry :: RegisterMCCodeEmitter ( * T , create<ISA_LIT>MCCodeEmitter ) ; TargetRegistry :: RegisterMCAsmBackend ( * T , create<ISA_LIT>AsmBackend ) ; TargetRegistry :: RegisterObjectTargetStreamer ( * T , createObjectTargetStreamer ) ; TargetRegistry :: RegisterAsmTargetStreamer ( *


<s> const char * rl78_addsi3_internal ( rtx * operands , unsigned int alternative ) { if ( TARGET_ES0 && GET_CODE ( operands [ <NUM_LIT> ] ) == SYMBOL_REF && TREE_CODE ( SYMBOL_REF_DECL ( operands [ <NUM_LIT> ] ) ) == VAR_DECL && TREE_READONLY ( SYMBOL_REF_DECL ( operands [ <NUM_LIT> ] ) ) && ! TREE_SIDE_EFFECTS ( SYMBOL_REF_DECL ( operands [ <NUM_LIT> ] ) ) ) return <STR_LIT> ; switch ( alternative ) { case <NUM_LIT> : case <NUM_LIT> : return


<s> void <ISA_LIT>DAGToDAGISel :: SelectBRCOND ( SDNode * N ) { SDValue Cond = N -> getOperand ( <NUM_LIT> ) ; if ( Cond . isUndef ( ) ) { CurDAG -> SelectNodeTo ( N , <STR_LIT> , <STR_LIT> , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) ) ; return ; } bool UseSCCBr = isCBranchSCC ( N ) && isUniformBr ( N ) ; unsigned BrOp = UseSCCBr ? <STR_LIT> : <STR_LIT> ; unsigned CondReg = UseSCCBr ? <STR_LIT> : <STR_LIT> ; SDLoc SL ( N ) ; SDValue VCC = CurDAG -> getCopyToReg ( N -> getOperand ( <NUM_LIT> ) , SL


<s> } Type * PtrTy = VecTy -> getPointerTo ( LI -> getPointerAddressSpace ( ) ) ; Type * Tys [ <NUM_LIT> ] = { VecTy , PtrTy } ; static const <STR_LIT> LoadInts [ <NUM_LIT> ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> } ; Function * LdNFunc = <STR_LIT> ( LI -> getModule ( ) , LoadInts [ Factor - <NUM_LIT> ] , Tys ) ; DenseMap < ShuffleVectorInst * , SmallVector < Value * , <NUM_LIT> >> SubVecs ; for ( unsigned LoadCount = <NUM_LIT> ; LoadCount < NumLoads ; ++ LoadCount ) { if ( LoadCount > <NUM_LIT> ) BaseAddr = Builder . CreateConstGEP1_32 ( BaseAddr , VecTy -> getVectorNumElements ( ) * Factor ) ; CallInst * LdN = Builder . CreateCall ( LdNFunc , Builder . CreateBitCast ( BaseAddr , PtrTy ) , <STR_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i < Shuffles . size ( ) ; i ++ ) { ShuffleVectorInst * SVI = Shuffles [ i ] ; unsigned Index = Indices [ i ] ; Value * SubVec = Builder . CreateExtractValue ( LdN , Index ) ; if ( EltTy -> isPointerTy ( ) ) SubVec = Builder . CreateIntToPtr ( SubVec , VectorType :: get ( SVI -> getType

( ) -> getVectorElementType ( ) , VecTy -> getVectorNumElements ( ) ) ) ;


<s> SDValue <ISA_LIT>TargetLowering :: LowerFormalArguments ( SDValue Chain , CallingConv :: ID CallConv , bool isVarArg , const SmallVectorImpl < <STR_LIT> > & Ins , SDLoc dl , SelectionDAG & DAG , SmallVectorImpl < SDValue > & InVals ) const { if ( Subtarget . isSVR4ABI


<s> void <ISA_LIT>InstrInfo :: storeRegToStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned SrcReg , bool IsKill , int FI , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { DebugLoc DL ; if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; if ( RC == & <STR_LIT> ) BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( IsKill ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) ; else llvm_unreachable ( <STR_LIT> )


<s> MCObjectWriter * llvm :: create<ISA_LIT>ELFObjectWriter ( raw_ostream & OS , uint8_t


<s> int n ; int mask ; int max ; max = MAX_INSN_PER_IT_BLOCK ; if ( arm_condexec_count ) arm_condexec_count -- ; if ( arm_condexec_count ) return ; if ( GET_CODE ( body ) != COND_EXEC ) return ; if ( JUMP_P ( insn ) ) return ; predicate = COND_EXEC_TEST ( body ) ; arm_current_cc = get_arm_condition_code ( predicate ) ; n = get_attr_ce_count ( insn ) ; arm_condexec_count = <NUM_LIT> ; arm_condexec_mask = ( <NUM_LIT> << n ) - <NUM_LIT> ; arm_condexec_masklen = n ; for ( ; ; ) { insn = next_nonnote_insn ( insn ) ; if ( ! NONJUMP_INSN_P ( insn ) && ! JUMP_P ( insn ) ) break ; body = PATTERN ( insn ) ; if ( GET_CODE ( body ) == USE || GET_CODE ( body ) == CLOBBER ) continue ; if ( GET_CODE ( body ) != COND_EXEC ) break ; n = get_attr_ce_count ( insn ) ; if ( arm_condexec_masklen + n > max ) break ; predicate = COND_EXEC_TEST ( body ) ; code = get_arm_condition_code ( predicate ) ; mask = ( <NUM_LIT> << n ) - <NUM_LIT> ; if ( arm_current_cc == code ) arm_condexec_mask |= ( mask << arm_condexec_masklen ) ; else if ( arm_current_cc != ARM_INVERSE_CONDITION_CODE ( code ) ) break ; arm_condexec_count


<s> <ISA_LIT>PerfHint :: MemAccessInfo <ISA_LIT>PerfHint :: makeMemAccessInfo ( Instruction * Inst ) const { MemAccessInfo MAI ; const Value * MO = getMemoryInstrPtrAndType ( Inst


<s> if ( ConstantSDNode * RHS = dyn_cast < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) ) ) { if ( SelectT2AddrModeImm8 ( N , Base , OffImm ) ) return false ; int RHSC = ( int ) RHS -> getZExtValue ( ) ; if ( N . getOpcode ( ) == <STR_LIT> ) RHSC = - RHSC ; if ( RHSC >= <NUM_LIT> && RHSC < <NUM_LIT> ) { Base = N . getOperand ( <NUM_LIT> ) ; if ( Base . getOpcode ( ) == <STR_LIT> ) { int FI = cast < FrameIndexSDNode > ( Base ) -> getIndex ( ) ; Base = CurDAG -> getTargetFrameIndex ( FI , TLI -> getPointerTy ( ) ) ; } OffImm = CurDAG -> getTargetConstant ( RHSC , <STR_LIT>


<s> inline SDValue getI8Imm ( unsigned Imm ) { return CurDAG -> getTargetConstant ( Imm , <STR_LIT>


<s> int64_t Amount = VRegAndVal -> Value . getSExtValue ( ) ; if ( Amount > <NUM_LIT> ) return true ; auto ExtCst = MIRBuilder . buildConstant ( LLT :: scalar ( <NUM_LIT> ) , Amount ) ; Observer . changingInstr ( MI ) ; MI . getOperand ( <NUM_LIT> ) . setReg ( ExtCst . getReg ( <NUM_LIT> ) ) ; Observer . changedInstr ( MI ) ; return true


<s> int arc_decl_pretend_args ( tree decl ) { gcc_assert ( decl == current_function_decl


<s> case CallingConv :: <ISA_LIT>_Gfx : return F -> getAttributes ( ) . hasParamAttr ( A -> getArgNo ( ) , Attribute :: InReg ) || F -> getAttributes (

) . hasParamAttr ( A -> getArgNo ( ) , Attribute :: ByVal ) ;


<s> static int ix86_avx_u128_mode_after ( int mode , rtx_insn * insn ) { rtx pat = PATTERN ( insn ) ; if ( vzeroupper_pattern ( pat , VOIDmode ) || vzeroall_pattern ( pat , VOIDmode ) ) return AVX_U128_CLEAN ; if ( CALL_P ( insn


<s> unsigned Tmp4Reg = RegInfo . createVirtualRegister ( RC ) ; unsigned TmpDestReg = RegInfo . createVirtualRegister ( RC ) ; unsigned Ptr1Reg ; unsigned TmpReg = ( ! BinOpcode ) ? Incr2Reg : RegInfo . createVirtualRegister ( RC ) ; BB -> addSuccessor ( loopMBB ) ; if ( ptrA != ZeroReg ) { Ptr1Reg = RegInfo . createVirtualRegister ( RC ) ; BuildMI ( BB , dl , TII -> get ( is64bit ? <STR_LIT> : <STR_LIT> ) , Ptr1Reg ) . addReg ( ptrA ) . addReg ( ptrB ) ; } else { Ptr1Reg = ptrB ; } BuildMI ( BB , dl , TII -> get ( <STR_LIT> ) , Shift1Reg ) . addReg ( Ptr1Reg ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( is8bit ? <NUM_LIT> : <NUM_LIT> ) ; BuildMI ( BB , dl , TII -> get ( is64bit ? <STR_LIT> : <STR_LIT> ) , ShiftReg ) . addReg ( Shift1Reg ) . addImm ( is8bit ? <NUM_LIT> : <NUM_LIT> ) ; if ( is64bit ) BuildMI ( BB , dl , TII -> get ( <STR_LIT> ) , PtrReg ) . addReg ( Ptr1Reg ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; else BuildMI ( BB , dl , TII -> get ( <STR_LIT> ) , PtrReg ) . addReg ( Ptr1Reg ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; BuildMI ( BB , dl , TII -> get ( <STR_LIT> ) , Incr2Reg ) . addReg ( incr ) . addReg ( ShiftReg ) ; if ( is8bit ) BuildMI ( BB , dl , TII -> get ( <STR_LIT> ) , Mask2Reg ) . addImm ( <NUM_LIT> ) ; else { BuildMI ( BB , dl , TII -> get ( <STR_LIT>


<s> if ( Amount ) { unsigned Opc = getADDriOpcode ( Is64Bit , Amount ) ; New = BuildMI ( MF , Old -> getDebugLoc ( ) , TII . get ( Opc ) , StackPtr ) . addReg ( StackPtr ) . addImm ( Amount ) ; } } if ( New ) { New -> getOperand ( <NUM_LIT> ) . setIsDead ( ) ; MBB . insert ( I , New ) ; } } } else if ( I -> getOpcode ( ) == getCallFrameDestroyOpcode ( ) ) { if ( uint64_t CalleeAmt = I -> getOperand ( <NUM_LIT> ) . getImm ( ) ) { unsigned Opc = getSUBriOpcode ( Is64Bit , CalleeAmt ) ; MachineInstr * Old = I ; MachineInstr * New = BuildMI ( MF , Old -> getDebugLoc ( ) , TII . get ( Opc ) , StackPtr ) . addReg ( StackPtr ) . addImm ( CalleeAmt ) ; New -> getOperand ( <NUM_LIT> ) . setIsDead ( ) ; MBB . insert ( I ,


<s> static SDValue CreateCopyOfByValArgument ( SDValue Src , SDValue Dst , SDValue Chain , <STR_LIT> Flags , SelectionDAG & DAG ,


<s> ++ It ; MF -> insert ( It , loopMBB ) ; MF -> insert ( It , exitMBB ) ; exitMBB -> splice ( exitMBB -> begin ( ) , BB , std :: next ( MachineBasicBlock :: iterator ( MI ) ) , BB -> end ( ) ) ; exitMBB -> transferSuccessorsAndUpdatePHIs ( BB ) ; BB -> addSuccessor ( loopMBB ) ; loopMBB -> addSuccessor ( loopMBB ) ; loopMBB -> addSuccessor ( exitMBB ) ; BB = loopMBB ; BuildMI ( BB , DL , TII -> get ( LL ) , OldVal ) . addReg ( Ptr ) . addImm ( <NUM_LIT> ) ; if ( Nand ) { BuildMI ( BB , DL , TII -> get ( AND ) , AndRes ) . addReg ( OldVal ) . addReg ( Incr ) ; BuildMI ( BB , DL , TII -> get ( NOR ) , StoreVal ) . addReg ( ZERO ) . addReg ( AndRes ) ; } else if ( BinOpcode ) { BuildMI ( BB , DL , TII -> get ( BinOpcode ) , StoreVal ) . addReg ( OldVal ) . addReg ( Incr ) ; } else { StoreVal =


<s> SDValue Scc = DAG . getNode ( <STR_LIT> , dl , VT , Clz , DAG . getConstant ( Log2b , <STR_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Scc ) ; } if ( C -> isAllOnesValue ( ) || C -> isNullValue ( ) ) return SDValue ( ) ; } EVT LHSVT = Op . getOperand ( <NUM_LIT> ) . getValueType ( ) ; if ( LHSVT . isInteger ( ) && ( CC == <STR_LIT> || CC == <STR_LIT> ) ) { EVT VT = Op . getValueType ( ) ; SDValue Sub = DAG . getNode ( <STR_LIT> , dl , LHSVT , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; return DAG . getSetCC ( dl , VT , Sub , DAG . getConstant ( <NUM_LIT> , LHSVT ) , CC ) ; } return SDValue


<s> if ( ! Subtarget . is<ISA_LIT>64 ( ) ) return AsmPrinter :: EmitFunctionEntryLabel ( ) ; MCSectionSubPair Current = OutStreamer . getCurrentSection ( ) ; const MCSectionELF * Section = OutStreamer . getContext ( ) . getELFSection ( <STR_LIT> , ELF :: SHT_PROGBITS , ELF :: SHF_WRITE | ELF :: SHF_ALLOC , SectionKind :: getReadOnly ( ) ) ; OutStreamer . SwitchSection ( Section


<s> uint64_t FrameSize = StackSize - SlotSize ; if ( needsStackRealignment ( MF ) ) FrameSize = ( FrameSize + MaxAlign - <NUM_LIT> ) / MaxAlign * MaxAlign ; NumBytes = FrameSize - CSSize ; BuildMI ( MBB , MBBI , DL , TII . get ( Is64Bit ? <STR_LIT> : <STR_LIT> ) , FramePtr ) ; } else { NumBytes = StackSize - CSSize ; } MachineBasicBlock :: iterator LastCSPop = MBBI ; while ( MBBI != MBB . begin ( ) ) { MachineBasicBlock :: iterator PI = prior ( MBBI ) ; unsigned Opc = PI -> getOpcode ( ) ; if ( Opc != <STR_LIT> && Opc != <STR_LIT> && ! PI -> getDesc ( ) . isTerminator ( ) ) break ; -- MBBI ; } DL = MBBI -> getDebugLoc ( ) ; if ( NumBytes || MFI -> hasVarSizedObjects ( ) ) mergeSPUpdatesUp ( MBB , MBBI , StackPtr , & NumBytes ) ; if ( needsStackRealignment ( MF ) ) { if ( CSSize ) { emitSPUpdate ( MBB , MBBI , StackPtr , NumBytes , Is64Bit , TII ) ; MBBI = prior ( LastCSPop ) ; } BuildMI ( MBB , MBBI , DL , TII . get ( Is64Bit ? <STR_LIT> : <STR_LIT> ) , StackPtr ) . addReg ( FramePtr ) ; } else if ( MFI -> hasVarSizedObjects ( ) ) { if ( CSSize ) { unsigned Opc = Is64Bit ? <STR_LIT> : <STR_LIT> ; MachineInstr * MI = addRegOffset ( BuildMI ( MF , DL , TII . get ( Opc ) , StackPtr ) , FramePtr , false , - CSSize ) ; MBB . insert ( MBBI , MI ) ; } else BuildMI ( MBB , MBBI , DL , TII . get ( Is64Bit ? <STR_LIT> : <STR_LIT> ) , StackPtr ) . addReg ( FramePtr ) ; } else { if ( NumBytes ) emitSPUpdate ( MBB , MBBI , StackPtr , NumBytes , Is64Bit , TII ) ; } if ( RetOpcode == <STR_LIT> || RetOpcode == <STR_LIT> ) { MBBI = prior ( MBB . end ( ) ) ; MachineOperand & DestAddr = MBBI -> getOperand ( <NUM_LIT> ) ; assert ( DestAddr . isReg ( ) && <STR_LIT> ) ; BuildMI ( MBB , MBBI , DL , TII . get ( Is64Bit ? <STR_LIT> : <STR_LIT> ) , StackPtr ) . addReg ( DestAddr . getReg ( ) ) ; } else if ( RetOpcode == <STR_LIT> || RetOpcode == <STR_LIT> || RetOpcode == <STR_LIT> || RetOpcode == <STR_LIT> ) { MBBI = prior ( MBB . end (


<s> info -> must_restore_reg = <NUM_LIT> ; info -> first = insn ; info -> x_used = <NUM_LIT> ; info -> y_used = <NUM_LIT> ; info -> can_use_d = TARGET_M6811 ? <NUM_LIT> : <NUM_LIT> ; info -> found_call = <NUM_LIT> ; info -> z_died = <NUM_LIT> ; info -> last = <NUM_LIT> ; info -> regno = - <NUM_LIT> ; info -> z_set_count = <NUM_LIT> ; info -> z_value = NULL_RTX ; info -> must_push_reg = <NUM_LIT> ; info -> save_before_last = <NUM_LIT> ; info -> z_loaded_with_sp = <NUM_LIT> ; for ( ; insn && info -> z_died == <NUM_LIT> ; insn = NEXT_INSN ( insn ) ) { if ( m68hc11_check_z_replacement ( insn , info ) == <NUM_LIT> ) break ; } if ( info -> z_set_count == <NUM_LIT> ) { rtx p = info -> first ; rtx v = <NUM_LIT> ; if ( info -> x_used ) { v = find_last_value ( iy_reg , & p , insn , <NUM_LIT> ) ; } else if ( info -> y_used ) { v = find_last_value ( ix_reg , & p , insn , <NUM_LIT> ) ; } if ( v && ( v != iy_reg && v != ix_reg ) && rtx_equal_p ( v , info -> z_value ) ) { if ( info -> x_used ) info -> regno = HARD_Y_REGNUM ; else info -> regno = HARD_X_REGNUM ; info -> must_load_z = <NUM_LIT> ; info -> must_save_reg = <NUM_LIT> ; info -> must_restore_reg = <NUM_LIT> ; info -> found_call = <NUM_LIT> ; } } if ( info -> z_set_count == <NUM_LIT> ) info -> need_save_z = <NUM_LIT> ; if ( insn == <NUM_LIT> ) info -> need_save_z = <NUM_LIT> ; if ( info -> last == <NUM_LIT> ) info -> last = insn ; if ( info -> regno >= <NUM_LIT> ) { reg = info -> regno ; info -> replace_reg = gen_rtx_REG ( HImode , reg ) ; } else if ( info -> can_use_d ) { reg = HARD_D_REGNUM ; info -> replace_reg = d_reg ; } else if ( info -> x_used ) { reg = HARD_Y_REGNUM ; info -> replace_reg = iy_reg ; } else { reg = HARD_X_REGNUM ; info -> replace_reg


<s> static int getWaitStatesSince ( GCNHazardRecognizer :: IsHazardFn IsHazard , MachineBasicBlock * MBB , MachineBasicBlock :: reverse_instr_iterator I , int WaitStates , IsExpiredFn IsExpired , DenseSet < const MachineBasicBlock * > & Visited ) { for ( auto E = MBB -> instr_rend ( ) ; I != E ; ++ I ) { if ( I -> isBundle ( ) ) continue ; if ( IsHazard ( & * I ) ) return WaitStates ; if ( I -> isInlineAsm ( ) || I -> isImplicitDef ( ) || I -> isDebugInstr ( ) ) continue ; WaitStates += <ISA_LIT>InstrInfo :: getNumWaitStates ( * I ) ; if ( IsExpired ( & * I , WaitStates ) ) return std :: numeric_limits < int > :: max ( ) ; } int MinWaitStates = WaitStates ; bool Found = false ; for ( MachineBasicBlock * Pred : MBB -> predecessors ( ) ) { if ( ! Visited . insert ( Pred ) . second ) continue ; int W = getWaitStatesSince ( IsHazard , Pred , Pred -> instr_rbegin ( ) , WaitStates ,


<s> static void initializePassOnce ( PassRegistry & Registry ) { const char *


<s> xops [ <NUM_LIT> ] = reg1 ; HOST_WIDE_INT interval ; if ( flag_stack_clash_protection ) interval = stack_clash_probe_interval ; else interval = PROBE_INTERVAL ; gcc_assert ( aarch64_uimm12_shift ( interval ) ) ; xops [ <NUM_LIT> ] = GEN_INT ( interval ) ; output_asm_insn ( <STR_LIT> , xops ) ; if ( flag_stack_clash_protection ) xops [ <NUM_LIT> ] = GEN_INT ( STACK_CLASH_CALLER_GUARD ) ; else xops [ <NUM_LIT> ] = CONST0_RTX ( GET_MODE ( xops [ <NUM_LIT> ] ) ) ; output_asm_insn ( <STR_LIT> , xops ) ; xops [ <NUM_LIT> ]


<s> if ( ! isGPRMem ( ) || Memory . Alignment != <NUM_LIT> ) return false ; if ( Memory . ShiftType != <STR_LIT> ) return false ; if ( Memory . OffsetRegNum ) return true ; if ( ! Memory . OffsetImm ) return true ; if ( const auto * CE = dyn_cast < MCConstantExpr > ( Memory . OffsetImm ) ) { int64_t Val = CE


<s> void <ISA_LIT>InstPrinter :: printB64 ( const MCInst * MI , unsigned


<s> else if ( VA . getLocInfo ( ) == CCValAssign :: BCvt ) Val = DAG . getBitcast ( LocVT , Val ) ; else assert ( VA . getLocInfo ( ) == CCValAssign :: Full && <STR_LIT> ) ; if ( VA . isRegLoc ( ) ) { RegsToPass . push_back ( std :: make_pair ( Reg , Val ) ) ; } else if ( ! IsTailCall ) { assert ( VA . isMemLoc ( ) ) ; Chain = DAG . getMemIntrinsicNode ( <STR_LIT> , DL , DAG . getVTList ( <STR_LIT> ) , { Chain , Val , DAG . getConstant ( VA . getLocMemOffset ( ) , DL , PtrVT ) } , LocVT , MachinePointerInfo :: getStack ( DAG . getMachineFunction ( ) , VA . getLocMemOffset ( ) ) , <NUM_LIT> , false , false ) ; Chain = DAG . getStore ( Chain , DL , Val , DAG . getTargetIndex ( VA . getLocMemOffset ( ) / PtrBits , PtrVT , VA . getLocMemOffset ( ) % PtrBits ) , MachinePointerInfo :: getStack ( DAG . getMachineFunction ( ) , VA . getLocMemOffset ( ) ) ) ; } } SDValue InFlag ; for ( unsigned I = <NUM_LIT> , E = RegsToPass . size ( ) ; I != E ; ++ I ) { Chain = DAG . getCopyToReg ( Chain , DL , RegsToPass [ I ] . first , RegsToPass [ I ] . second , InFlag ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; } if ( IsTailCall ) InFlag = SDValue ( ) ; if ( GlobalAddressSDNode * G = dyn_cast < GlobalAddressSDNode > ( Callee ) ) Callee = DAG . getTargetGlobalAddress ( G -> getGlobal ( ) , DL , PtrVT ) ; else if ( ExternalSymbolSDNode * E = dyn_cast < ExternalSymbolSDNode > ( Callee ) ) Callee = DAG . getTargetExternalSymbol ( E -> getSymbol ( ) , PtrVT ) ; SDVTList NodeTys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . push_back ( Chain ) ; Ops . push_back ( Callee ) ; for ( unsigned I = <NUM_LIT> , E = RegsToPass . size ( ) ; I != E ; ++ I ) Ops . push_back ( DAG . getRegister ( RegsToPass [ I ] . first , RegsToPass [ I ] . second . getValueType ( ) ) ) ; const uint32_t * Mask = RegInfo -> getCallPreservedMask ( MF , CallConv ) ; assert ( Mask && <STR_LIT> ) ; Ops . push_back ( DAG . getRegisterMask ( Mask ) ) ; if ( InFlag . getNode ( ) )


<s> static unsigned offsetMinAlignForOpcode ( unsigned OpC ) { switch ( OpC ) { default : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> bool ResourceAssignment :: XPathOnSideAvailable ( unsigned dstSide ) { unsigned xuse = ( dstSide == <NUM_LIT> ) ? <STR_LIT> : <STR_LIT> ; return ! Hzd -> isXResBusy


<s> MachineOperand & SrcMO = MI . getOperand ( <NUM_LIT> ) ; if ( IsVSReg ( DstMO . getReg ( ) , MRI ) && ! IsVSReg ( SrcMO . getReg ( ) , MRI ) ) { Changed = true ; const TargetRegisterClass * SrcRC = & <STR_LIT> ; assert ( ( IsF8Reg ( SrcMO . getReg ( ) , MRI ) || IsVSSReg ( SrcMO . getReg ( ) , MRI ) || IsVSFReg ( SrcMO . getReg ( ) , MRI ) ) && <STR_LIT> ) ; unsigned NewVReg = MRI . createVirtualRegister ( SrcRC ) ; BuildMI ( MBB , MI , MI . getDebugLoc ( ) , TII -> get ( TargetOpcode :: SUBREG_TO_REG ) , NewVReg ) . addImm ( <NUM_LIT> ) . addOperand ( SrcMO ) . addImm ( <STR_LIT> ) ; SrcMO . setReg (


<s> if ( ! optimize ) return ; edge e ; edge_iterator ei ; for ( const bb_info * bb : crtl -> ssa -> bbs ( ) ) { basic_block cfg_bb = bb -> cfg_bb ( ) ; auto & curr_prob = m_vector_manager -> vector_block_infos [ cfg_bb -> index ] . probability ; if ( ENTRY_BLOCK_PTR_FOR_FN ( cfun ) == cfg_bb ) curr_prob = profile_probability ::


<s> unsigned Cycles = I -> second ; if ( Cycles < Threshold ) { assert ( MBB -> size ( ) > <NUM_LIT> && <STR_LIT> ) ; MachineBasicBlock :: iterator ReturnLoc = -- MBB -> end ( ) ; while ( ReturnLoc -> isDebugInstr ( ) ) -- ReturnLoc ; assert ( ReturnLoc -> isReturn ( ) && ! ReturnLoc -> isCall ( ) && <STR_LIT> ) ; addPadding ( MBB , ReturnLoc , Threshold - Cycles ) ; NumBBsPadded ++


<s> SDValue <ISA_LIT>TargetLowering :: LowerReturn ( SDValue Chain , CallingConv :: ID CallConv , bool isVarArg , const SmallVectorImpl < <STR_LIT> > & Outs , const SmallVectorImpl < SDValue > & OutVals , DebugLoc dl , SelectionDAG & DAG ) const { if ( isVarArg ) llvm_unreachable ( <STR_LIT> ) ; switch ( CallConv ) { default : llvm_unreachable ( <STR_LIT> ) ; case CallingConv :: <ISA_LIT>_Kernel : assert ( Outs . size ( ) == <NUM_LIT> && <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Chain ) ; case CallingConv :: <ISA_LIT>_Device : assert ( Outs . size ( ) <= <NUM_LIT> && <STR_LIT> ) ; break ; } MachineFunction & MF = DAG . getMachineFunction ( ) ; <ISA_LIT>MachineFunctionInfo * MFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; <ISA_LIT>ParamManager & PM = MFI -> getParamManager ( ) ; SDValue Flag ; const <ISA_LIT>Subtarget & ST = getTargetMachine ( ) . getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( ST . useParamSpaceForDeviceArgs ( ) ) { assert ( Outs . size ( ) < <NUM_LIT> && <STR_LIT> ) ; if ( Outs . size ( ) == <NUM_LIT> ) { unsigned ParamSize = OutVals [ <NUM_LIT> ] . getValueType ( ) . getSizeInBits ( ) ; unsigned Param = PM . addReturnParam ( ParamSize ) ; const std :: string & ParamName = PM . getParamName (


<s> bool <ISA_LIT>AnnotateControlFlow :: isTopOfStack ( BasicBlock


<s> for ( unsigned reg = <STR_LIT> ; reg <= <STR_LIT> ; ++ reg ) if

( MRI -> isPhysRegUsed ( reg ) ) return false ;


<s> for ( const auto & I : make_range ( Begin , End ) ) * BytesRemoved += getInstSizeInBytes ( I ) ; } MBB . erase ( Begin , End ) ; return


<s> return <ISA_LIT>MaterializeGV ( GV , TLI . getValueType ( GV -> getType ( ) )


<s> printRegName ( O , MI -> getOperand ( OpNum ) . getReg ( ) + <NUM_LIT> ) ; O << <STR_LIT> ; printRegName ( O , MI -> getOperand ( OpNum ) . getReg ( ) +


<s> bool isAligned = ( RI . getStackAlignment ( ) >= <NUM_LIT> ) || RI . canRealignStack ( MF ) ; unsigned Opc = getLoadRegOpcode ( DestReg , RC , isAligned , TM ) ; DebugLoc DL = MBB . findDebugLoc ( MI ) ; addFrameReference ( BuildMI ( MBB , MI , DL , get ( Opc )


<s> if ( ! constrainSelectedInstRegOperands ( * SubI , TII , TRI , RBI ) ) return false ; } break ; } case <NUM_LIT> : case <NUM_LIT> : { unsigned NewOpc = selectSimpleExtOpc ( I . getOpcode ( ) , SrcSize ) ; I . setDesc ( TII . get ( NewOpc ) ) ; MIB . addImm ( <NUM_LIT> ) . add ( predOps ( <STR_LIT> ) ) ; break ; } default : DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } break ; } case G_ADD : I . setDesc ( TII . get ( <STR_LIT> ) ) ; MIB . add ( predOps ( <STR_LIT> ) ) . add ( condCodeOp ( ) ) ; break ; case G_FRAME_INDEX : I . setDesc ( TII . get ( <STR_LIT> ) ) ; MIB . addImm ( <NUM_LIT> ) . add ( predOps ( <STR_LIT> ) ) . add ( condCodeOp ( ) ) ; break ; case G_LOAD : { LLT ValTy = MRI . getType ( I . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; const auto ValSize = ValTy . getSizeInBits ( ) ; if ( ValSize != <NUM_LIT> && ValSize != <NUM_LIT> && ValSize != <NUM_LIT> && ValSize != <NUM_LIT> ) return false ; const auto NewOpc = selectLoadOpCode ( ValSize ) ; I . setDesc ( TII . get ( NewOpc ) ) ; if ( NewOpc == <STR_LIT> ) MIB .


<s> for ( MachineInstr :: mop_iterator op = MI -> operands_begin ( ) ; op != MI -> operands_end ( ) ; ++ op ) { if ( op -> isSymbol ( ) ) { errs ( ) << <STR_LIT> << op -> getSymbolName ( ) << <STR_LIT> ; foundSymbol = true ; break ; } } if ( ! foundSymbol ) { errs ( ) << <STR_LIT> ; } errs ( ) << <STR_LIT> << MBB -> getParent ( ) -> getFunction ( ) . getName ( ) << <STR_LIT> ; abort ( ) ; } return


<s> static bool getTargetShuffleInputs ( SDValue Op , SmallVectorImpl < SDValue > & Inputs , SmallVectorImpl < int > & Mask , const SelectionDAG & DAG , unsigned Depth = <NUM_LIT> , bool ResolveKnownElts = true ) { EVT VT = Op


<s> case <STR_LIT> : case <STR_LIT> : { unsigned BitWidth = KnownOne . getBitWidth ( ) ; EVT VT = cast < MemIntrinsicSDNode > ( Op ) -> getMemoryVT ( ) ; unsigned MemBits = VT . getScalarSizeInBits ( ) ; KnownZero |= APInt :: getHighBitsSet ( BitWidth , BitWidth - MemBits ) ; return ; } } break ; } case <STR_LIT> : case <STR_LIT> : { unsigned IntNo = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; switch ( IntNo ) { default : break ; case <STR_LIT> : case <STR_LIT> : { MVT VT = Op . getOperand ( <NUM_LIT> ) . getValueType ( ) . getSimpleVT ( ) ; unsigned BitWidth = KnownZero . getBitWidth ( ) ; if ( VT == <STR_LIT> || VT == <STR_LIT> ) { assert ( BitWidth >= <NUM_LIT> && <STR_LIT> ) ; APInt Mask = APInt :: getHighBitsSet ( BitWidth , BitWidth - <NUM_LIT> ) ; KnownZero |= Mask ; } else if ( VT == <STR_LIT> || VT == <STR_LIT> ) { assert ( BitWidth >= <NUM_LIT> && <STR_LIT> ) ; APInt Mask = APInt :: getHighBitsSet ( BitWidth , BitWidth - <NUM_LIT> ) ; KnownZero |= Mask ; } break ; }


<s> static MCCodeGenInfo * create<ISA_LIT>MCCodeGenInfo ( StringRef TT , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) { MCCodeGenInfo * X = new MCCodeGenInfo (


<s> MachineBasicBlock :: iterator CurrentTopFastSched = DAG -> getCurrentTop ( ) ; std :: vector < MachineBasicBlock :: iterator > PosOld ; std :: vector < MachineBasicBlock :: iterator > PosNew ; PosOld . reserve ( DAG -> SUnits . size ( ) ) ; PosNew . reserve ( DAG -> SUnits . size ( ) ) ; for ( unsigned i = <NUM_LIT> , e = DAGSize ; i != e ; ++ i ) { int BlockIndice = TopDownIndex2Block [ i ] ; <ISA_LIT>ScheduleBlock * Block = CurrentBlocks [ BlockIndice ] ; std :: vector < SUnit * > SUs = Block -> getScheduledUnits ( ) ; for ( SUnit * SU : SUs ) { MachineInstr * MI = SU -> getInstr ( ) ; MachineBasicBlock :: iterator Pos = MI ; PosOld . push_back ( Pos ) ; if ( & * CurrentTopFastSched == MI ) { PosNew . push_back ( Pos ) ; CurrentTopFastSched = nextIfDebug ( ++ CurrentTopFastSched , DAG -> getCurrentBottom ( ) ) ; } else { DAG -> getBB ( ) -> splice ( CurrentTopFastSched , DAG -> getBB ( ) , MI ) ; DAG -> getLIS ( ) -> handleMove ( * MI , true ) ; PosNew . push_back (


<s> if ( ! strict_p && GET_CODE ( x ) == SUBREG ) x = SUBREG_REG ( x ) ; return ( REG_P ( x ) && ( strict_p ? REGNO_OK_FOR_BASE_P ( REGNO ( x )

) : REGNO_OK_FOR_BASE_NONSTRICT_P ( REGNO ( x ) ) ) ) ;


<s> unsigned char status = _HTM_STATE ( __builtin_tend ( <NUM_LIT> ) ) ; if ( __builtin_expect ( status , _HTM_TRANSACTIONAL ) ) return


<s> if ( INTVAL ( in0_idx0 ) == INTVAL ( in1_idx0 ) && INTVAL ( in0_idx1 ) == INTVAL ( in1_idx1 ) && INTVAL ( in0_idx0 ) != INTVAL ( in0_idx1 ) ) return false ; if ( INTVAL ( in0_idx0 ) != INTVAL ( in0_idx1 ) && INTVAL ( in1_idx0 ) != INTVAL ( in1_idx1 ) ) return false ; return true


<s> int NumLaneElts = NumElts / NumLanes ; int Rotation = <NUM_LIT> ; SDValue Lo , Hi ; for ( int l = <NUM_LIT> ; l < NumElts ; l += NumLaneElts ) { for ( int i = <NUM_LIT> ; i < NumLaneElts ; ++ i ) { if ( Mask [ l + i ] == - <NUM_LIT> ) continue ; assert ( Mask [ l + i ] >= <NUM_LIT> && <STR_LIT> ) ; int LaneIdx = ( Mask [ l + i ] % NumElts ) - l ; if ( LaneIdx < <NUM_LIT> || LaneIdx >= NumLaneElts ) return SDValue ( ) ; int StartIdx = i - LaneIdx ; if ( StartIdx == <NUM_LIT> ) return SDValue ( ) ; int CandidateRotation = StartIdx < <NUM_LIT> ? - StartIdx : NumLaneElts - StartIdx ; if ( Rotation == <NUM_LIT> ) Rotation = CandidateRotation ; else if ( Rotation != CandidateRotation ) return SDValue ( ) ; SDValue MaskV = Mask [ l + i ] < NumElts ? V1 : V2 ; SDValue & TargetV = StartIdx < <NUM_LIT> ?


<s> rtx elt ; if ( ! const_vec_duplicate_p ( x , & elt ) || ! CONST_INT_P ( elt ) ) return false ; HOST_WIDE_INT val = INTVAL ( elt ) ; if ( negate_p ) val = - val ; val &= GET_MODE_MASK ( GET_MODE_INNER ( GET_MODE ( x ) ) ) ; if ( val & <NUM_LIT> ) return IN_RANGE ( val , <NUM_LIT>


<s> static MCStreamer * createMCStreamer ( const Triple & T , MCContext & Context , MCAsmBackend & MAB , raw_pwrite_stream

& OS , MCCodeEmitter * Emitter , bool RelaxAll ) {


<s> BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addGlobalAddress ( MF . getFunction ( ) ) . addReg ( <STR_LIT> ) . addImm ( curgpdist ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) ) . addGlobalAddress ( MF . getFunction ( ) ) ; long NumBytes = MFI -> getStackSize ( ) ; if ( FP ) NumBytes += <NUM_LIT> ; if ( NumBytes == <NUM_LIT> ) return ; unsigned Align = getStackAlignment ( ) ; NumBytes = ( NumBytes + Align - <NUM_LIT> ) / Align * Align ; MFI -> setStackSize ( NumBytes ) ; NumBytes = - NumBytes ; if ( NumBytes >= <STR_LIT> ) { BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addImm ( NumBytes ) . addReg ( <STR_LIT> ) ; } else if ( getUpper16 ( NumBytes ) >= <STR_LIT> ) { BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addImm ( getUpper16 ( NumBytes ) ) . addReg ( <STR_LIT> ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addImm ( getLower16 ( NumBytes ) ) . addReg ( <STR_LIT> ) ; } else { report_fatal_error ( <STR_LIT> + Twine ( NumBytes ) ) ; } if ( FP ) { BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( <STR_LIT> ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT>


<s> if ( Name == <STR_LIT> || Name == <STR_LIT> ) return <NUM_LIT> ; else if ( Name == <STR_LIT> || Name == <STR_LIT> ) return <NUM_LIT> ; else if ( Name == <STR_LIT> || Name == <STR_LIT> ) return <NUM_LIT> ; else if ( Name == <STR_LIT> || Name == <STR_LIT> ) return <NUM_LIT> ; else if ( Name == <STR_LIT> || Name == <STR_LIT> ) return <NUM_LIT> ; else if ( Name == <STR_LIT> || Name == <STR_LIT> ) return <NUM_LIT> ; else if ( Name == <STR_LIT> || Name == <STR_LIT> ) return <NUM_LIT> ; else if ( Name == <STR_LIT> || Name == <STR_LIT> ) return <NUM_LIT> ; else if ( Name == <STR_LIT> || Name == <STR_LIT> ) return <NUM_LIT> ; else if ( Name == <STR_LIT> || Name == <STR_LIT> ) return <NUM_LIT> ; else if ( Name == <STR_LIT> || Name == <STR_LIT> ) return <NUM_LIT> ; else if ( Name == <STR_LIT> || Name == <STR_LIT> ) return


<s> addPass ( create<ISA_LIT>MemoryLegalizerPass ( ) ) ; addPass ( create<ISA_LIT>InsertWaitcntsPass ( ) ) ; addPass ( create<ISA_LIT>ShrinkInstructionsPass ( ) ) ; addPass ( create<ISA_LIT>ModeRegisterPass ( ) ) ; addPass ( & PostRAHazardRecognizerID ) ; addPass ( & <ISA_LIT>InsertSkipsPassID ) ; addPass ( & BranchRelaxationPassID )


<s> static bool ix86_additional_allocno_class_p ( reg_class_t cl


<s> CStringSection = <STR_LIT> ; PrivateGlobalPrefix = <STR_LIT> ; WeakRefDirective = <STR_LIT> ; SetDirective = <STR_LIT> ; DwarfRequiresFrameSection = false ; DwarfAbbrevSection = <STR_LIT> ; DwarfInfoSection = <STR_LIT> ; DwarfLineSection = <STR_LIT> ; DwarfFrameSection = <STR_LIT> ; DwarfPubNamesSection = <STR_LIT> ; DwarfPubTypesSection = <STR_LIT> ; DwarfStrSection = <STR_LIT> ; DwarfLocSection = <STR_LIT> ; DwarfARangesSection = <STR_LIT> ; DwarfRangesSection =


<s> static MCSymbolizer * create<ISA_LIT>ExternalSymbolizer ( const Triple & TT , LLVMOpInfoCallback GetOpInfo , LLVMSymbolLookupCallback SymbolLookUp , void * DisInfo , MCContext * Ctx , std :: unique_ptr < MCRelocationInfo > && RelInfo ) { return new llvm :: <ISA_LIT>ExternalSymbolizer ( * Ctx , move ( RelInfo ) , GetOpInfo


<s> void BRIGDwarfStreamer :: Finish ( ) { MCELFStreamer :: Finish ( ) ; dwarfStream -> flush ( ) ; dwarfStream -> releaseStream (


<s> bool hasMiscellaneousExtensions3 ( )


<s> if ( ! HasSoloAXInst ) return true ; for ( auto const & I : <ISA_LIT>MCInstrInfo :: bundleInstructions ( MCII , MCB ) ) { if ( & I != HasSoloAXInst && isNeitherAnorX (


<s> SDValue <ISA_LIT>TargetLowering :: EmitCmp ( SDValue Op0 , SDValue Op1 , unsigned <ISA_LIT>CC , const SDLoc & DL , SelectionDAG & DAG ) const { if ( isNullConstant ( Op1 ) ) return EmitTest ( Op0 , <ISA_LIT>CC , DL , DAG ) ; assert ( ! ( isa < ConstantSDNode > ( Op1 ) && Op0 . getValueType ( ) == <STR_LIT> ) && <STR_LIT> ) ; if ( ( Op0 . getValueType ( ) == <STR_LIT> || Op0 . getValueType ( ) == <STR_LIT> || Op0 . getValueType ( ) == <STR_LIT> || Op0 . getValueType ( ) == <STR_LIT> ) ) { if ( ( Op0 . getValueType ( ) == <STR_LIT> && ( isa < ConstantSDNode > ( Op0 ) || isa < ConstantSDNode > ( Op1 ) ) ) && ! DAG . getMachineFunction ( ) . getFunction ( ) . hasMinSize ( ) ) { unsigned ExtendOp = is<ISA_LIT>CCUnsigned ( <ISA_LIT>CC ) ? <STR_LIT> : <STR_LIT> ; Op0 = DAG . getNode ( ExtendOp , DL


<s> } MVT PtrVT = TLI -> getPointerTy ( CurDAG -> getDataLayout ( ) ) ; auto GlobalGetIns = PtrVT == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; SDLoc DL ( Node ) ; MachineFunction & MF = CurDAG -> getMachineFunction ( ) ; switch ( Node -> getOpcode ( ) ) { case <STR_LIT> : { if ( ! MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . hasAtomics ( ) ) break ; uint64_t SyncScopeID = Node -> getConstantOperandVal ( <NUM_LIT> ) ; MachineSDNode * Fence = nullptr ; switch ( SyncScopeID ) { case SyncScope :: SingleThread : Fence = CurDAG -> getMachineNode ( <STR_LIT> , DL , <STR_LIT> , Node -> getOperand ( <NUM_LIT> ) ) ; break ; case SyncScope :: System : Fence = CurDAG -> getMachineNode ( <STR_LIT> , DL , <STR_LIT> , CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) , Node -> getOperand ( <NUM_LIT> ) ) ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } ReplaceNode ( Node , Fence ) ; CurDAG -> RemoveDeadNode ( Node ) ; return ; } case <STR_LIT> : { unsigned IntNo = Node -> getConstantOperandVal ( <NUM_LIT> ) ; switch ( IntNo ) { case <STR_LIT> : { MachineSDNode * TLSSize = CurDAG -> getMachineNode ( GlobalGetIns , DL , PtrVT , CurDAG -> getTargetExternalSymbol ( <STR_LIT> , PtrVT ) ) ; ReplaceNode ( Node , TLSSize ) ; return ; } case <STR_LIT> : { MachineSDNode * TLSAlign = CurDAG -> getMachineNode ( GlobalGetIns , DL , PtrVT , CurDAG -> getTargetExternalSymbol ( <STR_LIT> , PtrVT ) ) ; ReplaceNode ( Node , TLSAlign ) ; return ; } } break ; } case <STR_LIT> : { unsigned IntNo = Node -> getConstantOperandVal ( <NUM_LIT> ) ; const auto & TLI = CurDAG -> getTargetLoweringInfo ( ) ; MVT PtrVT = TLI . getPointerTy ( CurDAG -> getDataLayout ( ) ) ; switch ( IntNo ) { case <STR_LIT> : { MachineSDNode * TLSBase = CurDAG -> getMachineNode ( GlobalGetIns , DL , PtrVT , <STR_LIT> , CurDAG -> getTargetExternalSymbol ( <STR_LIT> , PtrVT ) , Node -> getOperand ( <NUM_LIT> ) ) ; ReplaceNode ( Node , TLSBase ) ; return ; } case <STR_LIT> : { int Tag = Node -> getConstantOperandVal ( <NUM_LIT> ) ; SDValue SymNode = getTagSymNode ( Tag , CurDAG ) ; MachineSDNode * Catch = CurDAG -> getMachineNode ( <STR_LIT> , DL , { PtrVT , <STR_LIT> } , { SymNode , Node -> getOperand ( <NUM_LIT> ) } ) ; ReplaceNode ( Node , Catch ) ; return ; } } break ; } case <STR_LIT> : { unsigned IntNo = Node -> getConstantOperandVal ( <NUM_LIT>


<s> if ( ! I -> pred_empty ( ) ) { printBasicBlockLabel ( I , true , true ) ; O << '\n' ; } for ( MachineBasicBlock :: const_iterator II = I -> begin ( ) , E = I -> end ( ) ; II != E ; ++ II ) { printMachineInstruction ( II


<s> int NumLoInputs = count_if ( Mask , [ Size ] ( int M ) { return M >= <NUM_LIT> && M % Size < Size / <NUM_LIT> ; } ) ; int NumHiInputs = count_if ( Mask , [ Size ] ( int M ) { return M % Size >= Size / <NUM_LIT> ; } ) ; bool UnpackLo = NumLoInputs >= NumHiInputs ; auto TryUnpack = [ & ] ( MVT UnpackVT , int Scale ) { SmallVector < int , <NUM_LIT> > V1Mask ( Mask . size ( ) , - <NUM_LIT> ) ; SmallVector < int , <NUM_LIT> > V2Mask ( Mask . size ( ) , - <NUM_LIT> ) ; for ( int i = <NUM_LIT> ; i < Size ; ++ i ) { if ( Mask [ i ] < <NUM_LIT> ) continue ; int UnpackIdx = i / Scale ; if ( ( UnpackIdx % <NUM_LIT> == <NUM_LIT> ) != ( Mask [ i ] < Size ) ) return SDValue ( ) ; SmallVectorImpl < int > & VMask = ( UnpackIdx % <NUM_LIT> == <NUM_LIT> ) ? V1Mask : V2Mask ; VMask [ ( UnpackIdx / <NUM_LIT> ) * Scale + i % Scale + ( UnpackLo ? <NUM_LIT> : Size / <NUM_LIT> ) ] = Mask [ i ] % Size ; } if ( ( NumLoInputs == <NUM_LIT> || NumHiInputs == <NUM_LIT> ) && ! isNoopShuffleMask ( V1Mask ) && ! isNoopShuffleMask ( V2Mask ) ) return SDValue ( ) ; V1 = DAG . getVectorShuffle ( VT , DL , V1 , DAG . getUNDEF ( VT ) , V1Mask ) ; V2 = DAG . getVectorShuffle ( VT , DL , V2 , DAG . getUNDEF ( VT ) , V2Mask ) ; V1 = DAG . getBitcast ( UnpackVT , V1 ) ; V2 = DAG . getBitcast ( UnpackVT , V2 ) ; return DAG . getBitcast ( VT , DAG . getNode ( UnpackLo ? <STR_LIT> : <STR_LIT> , DL , UnpackVT , V1 , V2 ) ) ; } ; int OrigNumElements = VT . getVectorNumElements ( ) ; int OrigScalarSize = VT . getScalarSizeInBits ( ) ; for ( int ScalarSize = <NUM_LIT> ; ScalarSize >= OrigScalarSize ; ScalarSize /= <NUM_LIT> ) { int Scale = ScalarSize / OrigScalarSize ; int NumElements = OrigNumElements / Scale ; MVT UnpackVT = <STR_LIT> ( <STR_LIT> ( ScalarSize ) , NumElements ) ; if ( SDValue Unpack = TryUnpack ( UnpackVT , Scale ) ) return Unpack ; } if ( NumLoInputs == <NUM_LIT> || NumHiInputs == <NUM_LIT> ) { assert ( ( NumLoInputs > <NUM_LIT> || NumHiInputs > <NUM_LIT> ) && <STR_LIT> ) ; int HalfOffset = NumLoInputs == <NUM_LIT> ? Size / <NUM_LIT> : <NUM_LIT> ; SmallVector < int , <NUM_LIT> > PermMask ( ( unsigned )


<s> uint64_t NumNops = Count / <NUM_LIT> ; for ( uint64_t i = <NUM_LIT> ; i != NumNops ; ++ i ) { OS << <STR_LIT> ; } return


<s> SmallVector < CCValAssign , <NUM_LIT> > RVLocs ; CCState CCInfo ( CallConv , IsVarArg , MF , RVLocs , Context ) ; return CCInfo . CheckReturn ( Outs , Subtarget . isRV64 ( ) ? RetCC_<ISA_LIT>64 :


<s> GetReturnInfo ( F . getReturnType ( ) , F . getAttributes ( ) , Outs , TLI , DL ) ; SmallVector < CCValAssign , <NUM_LIT> > ValLocs ; CCState CCInfo ( CC , F . isVarArg ( ) , * FuncInfo . MF , ValLocs , I -> getContext ( ) ) ; CCInfo . AnalyzeReturn ( Outs , RetCC_<ISA_LIT> ) ; const Value * RV = Ret -> getOperand ( <NUM_LIT> ) ; unsigned Reg = getRegForValue ( RV ) ; if ( Reg == <NUM_LIT> ) return false ; if ( ValLocs . size ( ) != <NUM_LIT> ) return false ; CCValAssign & VA = ValLocs [ <NUM_LIT> ] ; if ( VA . getLocInfo ( ) != CCValAssign :: Full ) return false ; if ( ! VA . isRegLoc ( ) ) return false ; if ( VA . getLocReg ( ) == <STR_LIT> || VA . getLocReg ( ) == <STR_LIT> ) return false ; unsigned SrcReg = Reg + VA . getValNo ( ) ; EVT SrcVT = TLI . getValueType ( DL , RV -> getType ( ) ) ; EVT DstVT = VA . getValVT ( ) ; if ( SrcVT != DstVT ) { if ( SrcVT != <STR_LIT> && SrcVT != <STR_LIT> && SrcVT != <STR_LIT> ) return false ; if ( ! Outs [ <NUM_LIT> ] . Flags . isZExt ( ) && ! Outs [ <NUM_LIT> ] . Flags . isSExt ( ) ) return false ; assert ( DstVT == <STR_LIT> && <STR_LIT> ) ; if ( SrcVT == <STR_LIT> ) { if ( Outs [ <NUM_LIT> ] . Flags . isSExt ( ) ) return false ; SrcReg = fastEmitZExtFromI1 ( <STR_LIT> , SrcReg


<s> Function * Callee = CS . getCalledFunction ( ) ; Function * Caller = CS . getCaller ( ) ; if ( ! Callee || Callee -> isDeclaration ( ) ) return llvm :: InlineCost :: getNever ( <STR_LIT> ) ; if ( CS . isNoInline ( ) ) return llvm :: InlineCost :: getNever ( <STR_LIT> ) ; TargetTransformInfo & TTI = TTIWP -> getTTI ( * Callee ) ; if ( ! TTI . areInlineCompatible ( Caller , Callee ) ) return llvm :: InlineCost :: getNever ( <STR_LIT> ) ; if ( CS . hasFnAttr ( Attribute :: AlwaysInline ) ) { auto IsViable = isInlineViable ( * Callee ) ; if ( IsViable ) return llvm :: InlineCost :: getAlways ( <STR_LIT> ) ; return llvm :: InlineCost :: getNever ( IsViable . message ) ; } if ( isWrapperOnlyCall ( CS ) ) return llvm :: InlineCost :: getAlways ( <STR_LIT> ) ; InlineParams LocalParams = Params ; LocalParams . DefaultThreshold = ( int ) getInlineThreshold ( CS ) ; bool RemarksEnabled = false ; const auto & BBs = Caller -> getBasicBlockList ( ) ; if ( ! BBs .


<s> case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : break ; case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : if ( ! ( FeatureBits [ <STR_LIT> ] ) ) return MCDisassembler :: Fail ; break ; case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : if ( ! ( FeatureBits [ <STR_LIT> ] ) ) return MCDisassembler :: Fail ; LLVM_FALLTHROUGH ; case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : if ( ! ( FeatureBits [ <STR_LIT> ] ) ) return MCDisassembler :: Fail ; break ; case <NUM_LIT> : case <NUM_LIT> : case


<s> addSavedGPR ( MBB , MIB , SpillGPRs . LowGPR , false ) ; addSavedGPR ( MBB , MIB , SpillGPRs . HighGPR , false ) ; MIB . addReg ( Regs . getStackPointerRegister ( ) ) ; MIB . addImm ( SpillGPRs . GPROffset ) ; auto & GRRegClass = <STR_LIT> ; for ( unsigned I = <NUM_LIT> , E = CSI . size ( ) ; I != E ; ++ I ) { unsigned Reg = CSI [ I ] . getReg ( ) ; if ( GRRegClass . contains ( Reg ) ) addSavedGPR ( MBB , MIB , Reg , true ) ; } } for ( unsigned I = <NUM_LIT> , E = CSI . size ( ) ; I != E ; ++ I ) { unsigned Reg = CSI [ I ] . getReg


<s> reportParseError ( <STR_LIT> ) ; Parser . eatToEndOfStatement ( ) ; return false ; } <ISA_LIT>Operand & FuncRegOpnd = static_cast < <ISA_LIT>Operand & > ( * TmpReg [ <NUM_LIT> ] ) ; if ( ! FuncRegOpnd . isGPRAsmReg ( ) ) { reportParseError ( FuncRegOpnd . getStartLoc ( ) , <STR_LIT> ) ; Parser . eatToEndOfStatement ( ) ; return false ; } FuncReg = FuncRegOpnd . getGPR32Reg ( ) ; TmpReg . clear ( ) ; if ( ! eatComma ( <STR_LIT> ) ) return true ; ResTy = ParseAnyRegister ( TmpReg ) ; if ( ResTy == MatchOperand_NoMatch ) { const AsmToken & Tok = Parser . getTok ( ) ; if ( Tok . is ( AsmToken :: Integer ) ) { Save = Tok . getIntVal ( ) ; SaveIsReg = false ; Parser . Lex ( ) ; } else { reportParseError ( <STR_LIT> ) ; Parser . eatToEndOfStatement ( ) ; return false ; } } else { <ISA_LIT>Operand & SaveOpnd = static_cast < <ISA_LIT>Operand & > ( * TmpReg [ <NUM_LIT> ] ) ; if ( ! SaveOpnd . isGPRAsmReg ( ) ) { reportParseError ( SaveOpnd . getStartLoc ( ) , <STR_LIT> ) ; Parser . eatToEndOfStatement ( ) ; return false ; } Save = SaveOpnd . getGPR32Reg ( ) ; } if ( ! eatComma ( <STR_LIT> ) ) return true ; StringRef Name ; if ( Parser . parseIdentifier ( Name )


<s> ZeroDirective = <STR_LIT> ; CommentString = <STR_LIT> ; AscizDirective = <STR_LIT> ; HiddenVisibilityAttr = MCSA_Invalid ; HiddenDeclarationVisibilityAttr = MCSA_Invalid


<s> AU . addPreserved < MachineLoopInfo > ( ) ; AU . addRequired < MachineTraceMetrics > ( ) ; AU . addPreserved < MachineTraceMetrics >


<s> <ISA_LIT>TargetStreamer :: <ISA_LIT>TargetStreamer ( MCStreamer & S ) : MCTargetStreamer ( S ) , ModuleDirectiveAllowed ( true ) { GPRInfoSet = FPRInfoSet = FrameInfoSet


<s> return ( ( qword ) ( vec_and ( ( vec_char16 ) ( a ) , vec_splat ( ( vec_char16 ) ( si_from_char ( b ) ) , <NUM_LIT>


<s> machine_mode h8300_select_cc_mode ( enum rtx_code cond , rtx op0 , rtx op1 ) { if ( op1 == const0_rtx && ( cond == EQ || cond == NE || cond == LT || cond == GE ) && ( GET_CODE ( op0 ) == PLUS || GET_CODE ( op0 ) == MINUS || GET_CODE ( op0 ) == NEG || GET_CODE ( op0 ) == AND || GET_CODE ( op0 ) == IOR || GET_CODE ( op0 ) == XOR || GET_CODE ( op0 ) == NOT || GET_CODE ( op0 ) == ASHIFT || GET_CODE ( op0 ) == ASHIFTRT || GET_CODE ( op0 ) == LSHIFTRT || GET_CODE ( op0 ) == MULT || GET_CODE ( op0 ) == SYMBOL_REF || GET_CODE ( op0 ) == SIGN_EXTEND || GET_CODE ( op0 ) == ZERO_EXTEND || REG_P ( op0 ) || MEM_P ( op0 ) ) ) return CCZNmode ; return CCmode


<s> static void PrintUnmangledNameSafely ( const Value * V , raw_ostream & OS ) { for ( const char * Name = V -> getNameStart ( ) , * E = Name + V -> getNameLen ( ) ; Name != E ; ++ Name ) if ( isprint (


<s> return ( ( vec_double2 ) ( si_rotqmby ( ( qword ) ( a )


<s> TargetRegistry :: RegisterMCDisassembler ( The<ISA_LIT>_32Target , create<ISA_LIT>_32Disassembler ) ; TargetRegistry :: RegisterMCDisassembler ( The<ISA_LIT>_64Target , create<ISA_LIT>_64Disassembler


<s> EVT VT = Op . getValueType ( ) ; assert ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) == VT && Op . getOperand ( <NUM_LIT> ) . getValueType ( ) == VT && <STR_LIT> ) ; assert ( ( VT . is256BitVector ( ) || VT . is512BitVector ( ) ) && <STR_LIT> ) ; SDLoc dl ( Op ) ; SDValue LHS1 , LHS2 ; std :: tie ( LHS1 , LHS2 ) = splitVector ( Op . getOperand ( <NUM_LIT> ) , DAG , dl ) ; SDValue RHS1 , RHS2 ; std :: tie ( RHS1 , RHS2 ) = splitVector ( Op . getOperand ( <NUM_LIT> ) , DAG , dl ) ; EVT LoVT ,


<s> create_input_operand ( & ops [ <NUM_LIT> ] , value0 , TYPE_MODE ( TREE_TYPE ( arg0 ) ) ) ; if ( ! maybe_expand_insn ( icode , <NUM_LIT> , ops ) )


<s> switch ( RegEnum ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT>


<s> bool <ISA_LIT>InstrInfo :: isInlineConstant ( const MachineOperand & MO , unsigned OpSize ) const { if ( MO . isImm (


<s> if ( Op0 == Op1 ) return true ; unsigned Opcode0 = Op0 . getOpcode ( ) ; if ( ( Opcode0 == <STR_LIT> || Opcode0 == <STR_LIT> || Opcode0 == <STR_LIT> ) && Op0 . getOperand ( <NUM_LIT> ) . getScalarValueSizeInBits ( ) <= TruncSizeInBits ) return true ; unsigned Opcode1 = Op1 . getOpcode ( ) ; if ( ( Opcode1 == <STR_LIT> || Opcode1 == <STR_LIT> || Opcode1 == <STR_LIT> ) && Op1 . getOperand ( <NUM_LIT> ) . getScalarValueSizeInBits ( ) <= TruncSizeInBits ) return true ; SDValue BC0 = peekThroughOneUseBitcasts ( Op0 ) ; SDValue BC1 = peekThroughOneUseBitcasts ( Op1 ) ; return <STR_LIT> ( BC0 . getNode ( ) ) || <STR_LIT> ( BC1 . getNode ( ) ) ; } ; auto TruncateArithmetic = [ & ] ( SDValue N0 , SDValue N1 ) { SDValue Trunc0 = DAG . getNode ( <STR_LIT> , DL , VT , N0 ) ; SDValue Trunc1 = DAG . getNode ( <STR_LIT> , DL , VT , N1 ) ; return DAG . getNode ( Opcode , DL , VT , Trunc0 , Trunc1 ) ; } ; if ( ! N -> isOnlyUserOf ( Src . getNode ( ) ) ) return SDValue ( ) ; if ( ! VT . isVector ( ) ) return SDValue ( ) ; switch ( Opcode


<s> MachineFunction :: iterator It = BB ; ++ It ; MachineBasicBlock * thisMBB = BB ; MachineFunction * F = BB -> getParent ( ) ; MachineBasicBlock * copy0MBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * sinkMBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; F -> insert ( It , copy0MBB ) ; F -> insert ( It , sinkMBB ) ; sinkMBB -> splice ( sinkMBB -> begin ( ) , BB , std :: next ( MachineBasicBlock :: iterator ( MI ) ) , BB -> end ( ) ) ; sinkMBB -> transferSuccessorsAndUpdatePHIs ( BB ) ; BB -> addSuccessor ( copy0MBB ) ; BB -> addSuccessor ( sinkMBB ) ; BuildMI ( BB , dl , TII . get ( <STR_LIT> ) ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg (


<s> const <ISA_LIT>FrameLowering * getFrameLowering ( ) const override


<s> static Optional < int64_t > getVectorShiftImm ( Register Reg , MachineRegisterInfo & MRI ) { assert ( MRI . getType ( Reg ) . isVector ( ) && <STR_LIT> ) ; MachineInstr * OpMI = MRI . getVRegDef ( Reg ) ; assert ( OpMI && <STR_LIT> ) ; if ( OpMI -> getOpcode ( ) != TargetOpcode :: G_BUILD_VECTOR


<s> } Align = CurDAG -> getTargetConstant ( Alignment , <STR_LIT> ) ; unsigned OpcodeIndex ; switch ( VT . getSimpleVT ( ) . SimpleTy ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; } SDValue Pred = getAL ( CurDAG ) ; SDValue Reg0 = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; SDValue SuperReg ; unsigned Opc = Opcodes [ OpcodeIndex ] ; const SDValue Ops [ ] = { MemAddr , Align , Pred , Reg0 , Chain } ; unsigned ResTyElts = ( NumVecs == <NUM_LIT> ) ? <NUM_LIT> : NumVecs ; EVT ResTy = EVT :: getVectorVT ( * CurDAG -> getContext ( ) , <STR_LIT> , ResTyElts ) ; SDNode * VLdDup = CurDAG -> getMachineNode ( Opc , dl , ResTy , <STR_LIT> , Ops , <NUM_LIT> ) ; SuperReg = SDValue ( VLdDup , <NUM_LIT> ) ; Chain = SDValue ( VLdDup , <NUM_LIT> ) ; assert ( <STR_LIT> == <STR_LIT> + <NUM_LIT> && <STR_LIT> ) ; unsigned SubIdx = <STR_LIT> ; for ( unsigned Vec = <NUM_LIT> ; Vec < NumVecs ; ++ Vec ) ReplaceUses ( SDValue ( N , Vec ) , CurDAG -> getTargetExtractSubreg ( SubIdx + Vec , dl , VT , SuperReg ) ) ; ReplaceUses ( SDValue ( N , NumVecs ) , Chain ) ; return NULL


<s> bool <ISA_LIT>DAGToDAGISel :: SelectAddrModeUnscaled ( SDValue N , unsigned Size , SDValue & Base , SDValue & OffImm ) { if ( ! CurDAG -> isBaseWithConstantOffset ( N ) ) return false ; if ( ConstantSDNode * RHS = dyn_cast < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) ) ) { int64_t RHSC = RHS -> getSExtValue ( ) ; if ( ( RHSC & ( Size - <NUM_LIT> ) ) == <NUM_LIT> && RHSC >= <NUM_LIT> && RHSC < ( <NUM_LIT> << Log2_32 ( Size ) ) ) return false ; if ( RHSC >= - <NUM_LIT> && RHSC < <NUM_LIT> ) { Base = N . getOperand ( <NUM_LIT> ) ; if ( Base . getOpcode ( ) == <STR_LIT> ) { int FI = cast < FrameIndexSDNode > ( Base


<s> MVT EltVT = VT . getVectorElementType ( ) ; SDValue Zero = DAG . getConstant ( <NUM_LIT> , DL , EltVT ) ; SDValue AllOnes = DAG . getAllOnesConstant ( DL , EltVT ) ; SmallVector < SDValue , <NUM_LIT> > VMaskOps ( Mask . size ( ) , Zero ) ; SDValue V ; for ( int i = <NUM_LIT> , Size = Mask . size ( ) ; i < Size ; ++ i ) { if ( Zeroable [ i ]


<s> FunctionPass * llvm :: create<ISA_LIT>TypeRewriter (


<s> MachineInstr * UseI = Use -> getInstr ( ) ; if ( DefI -> isBundle ( ) ) { const <ISA_LIT>RegisterInfo * TRI = getRegisterInfo ( ) ; auto Reg = Dep . getReg ( ) ; MachineBasicBlock :: const_instr_iterator I ( DefI -> getIterator ( ) ) ; MachineBasicBlock :: const_instr_iterator E ( DefI -> getParent ( ) -> instr_end ( ) ) ; unsigned Lat = <NUM_LIT> ; for ( ++ I ; I != E && I -> isBundledWithPred ( ) ; ++ I ) { if ( I -> modifiesRegister ( Reg , TRI ) ) Lat = InstrInfo . getInstrLatency ( getInstrItineraryData ( ) , * I ) ; else if ( Lat ) -- Lat ; } Dep . setLatency ( Lat ) ; } else if ( UseI -> isBundle ( ) ) { const <ISA_LIT>RegisterInfo * TRI = getRegisterInfo ( ) ; auto Reg = Dep . getReg ( ) ; MachineBasicBlock :: const_instr_iterator I ( UseI -> getIterator ( ) ) ; MachineBasicBlock :: const_instr_iterator E ( UseI -> getParent ( ) ->


<s> SmallString < <NUM_LIT> > smallstr ; smallstr += <STR_LIT> ; smallstr += <STR_LIT> ; smallstr += Name ; const char * stored ; stored = ST -> addLibcall ( smallstr . c_str ( ) ) ; setLibcallName ( Call , stored


<s> static MCDisassembler * create<ISA_LIT>Disassembler ( const Target & T , const MCSubtargetInfo & STI ) { return new <ISA_LIT>Disassembler ( STI , T . createMCRegInfo (


<s> return ; } unsigned SrcReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned DstReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( ( UsedRegMask & <NUM_LIT> ) == UsedRegMask ) { if ( DstReg != SrcReg ) BuildMI ( * MI -> getParent ( ) , MI , dl , TII . get ( <STR_LIT> ) , DstReg ) . addReg ( SrcReg ) . addImm ( UsedRegMask ) ; else BuildMI ( * MI -> getParent ( ) , MI , dl , TII . get ( <STR_LIT> ) , DstReg ) . addReg ( SrcReg , RegState :: Kill ) . addImm ( UsedRegMask ) ; } else if ( ( UsedRegMask & <NUM_LIT> ) == UsedRegMask ) { if ( DstReg != SrcReg ) BuildMI ( * MI -> getParent ( ) , MI , dl , TII . get ( <STR_LIT> ) , DstReg ) . addReg ( SrcReg ) . addImm ( UsedRegMask >> <NUM_LIT> ) ; else BuildMI ( * MI -> getParent ( ) , MI , dl , TII . get ( <STR_LIT> ) , DstReg ) . addReg ( SrcReg , RegState :: Kill ) . addImm ( UsedRegMask >> <NUM_LIT> ) ; } else { if ( DstReg != SrcReg ) BuildMI ( * MI -> getParent ( ) , MI , dl , TII . get ( <STR_LIT> ) , DstReg


<s> initializeMVELaneInterleavingPass ( * PassRegistry :: getPassRegistry (


<s> unsigned getATRegIndex ( ) const { return ATReg


<s> bool Hash = Tok . is ( AsmToken :: Hash ) ; if ( Hash || Tok . is ( AsmToken :: Integer ) ) { if ( Hash ) Parser . Lex ( ) ; const MCExpr * ImmVal ; if ( getParser ( ) . parseExpression ( ImmVal ) ) return MatchOperand_ParseFail ; const MCConstantExpr * MCE = dyn_cast < MCConstantExpr > ( ImmVal ) ; if ( ! MCE ) { TokError ( <STR_LIT> ) ; return MatchOperand_ParseFail ; } unsigned prfop = MCE -> getValue ( ) ; if ( prfop > <NUM_LIT> ) { TokError ( <STR_LIT> ) ; return MatchOperand_ParseFail ; } bool Valid ; auto Mapper = <STR_LIT> ( ) ; StringRef Name = Mapper . toString ( MCE -> getValue ( ) , STI . getFeatureBits ( ) , Valid ) ; Operands . push_back ( <ISA_LIT>Operand :: CreatePrefetch ( prfop , Name , S , getContext ( ) ) ) ; return MatchOperand_Success ; } if ( Tok . isNot ( AsmToken :: Identifier ) ) { TokError ( <STR_LIT> ) ; return MatchOperand_ParseFail ; } bool Valid ; auto Mapper = <STR_LIT> ( ) ; unsigned prfop = Mapper . fromString ( Tok . getString ( ) , STI . getFeatureBits ( ) , Valid ) ; if ( ! Valid ) { TokError ( <STR_LIT> ) ; return MatchOperand_ParseFail ; } Parser . Lex ( ) ; Operands . push_back ( <ISA_LIT>Operand :: CreatePrefetch ( prfop , Tok . getString ( ) , S


<s> GlobalAddressSDNode * GA = dyn_cast < GlobalAddressSDNode > ( Val ) ; if ( ! GA ) return false ; const GlobalVariable * GV = dyn_cast_or_null < GlobalVariable > ( GA -> getGlobal ( ) ) ; if ( ! GV ) return false ; if ( ! GV -> hasAttribute ( <STR_LIT> ) ) return false ; assert ( PointerSize >= GV -> getAlign ( ) . valueOrOne

( ) . value ( ) && <STR_LIT> <STR_LIT> ) ;


<s> count = copy_to_mode_reg ( HImode , GEN_INT ( INTVAL ( count ) / <NUM_LIT> ) ) ; if ( TARGET_A16 ) emit_insn ( gen_movmemhi_whi_op ( desto , srco , counto , desta , srca , count ) ) ; else emit_insn ( gen_movmemhi_wpsi_op ( desto , srco , counto , desta , srca , count ) ) ; return <NUM_LIT> ; } if ( GET_CODE ( count ) != REG || REGNO ( count )

< FIRST_PSEUDO_REGISTER ) count = copy_to_mode_reg ( HImode , count ) ;


<s> bool Is<ISA_LIT>64 = Subtarget . is<ISA_LIT>64 ( ) ; bool IsELF32_ABI = Subtarget . isELF32_ABI ( ) ; bool IsMachoABI = Subtarget . isMachoABI ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; if ( ! FPSI && ( NoFramePointerElim || MFI -> hasVarSizedObjects ( ) ) && IsELF32_ABI ) { int FPOffset = <ISA_LIT>FrameInfo :: getFramePointerSaveOffset ( Is<ISA_LIT>64 , IsMachoABI ) ; FPSI = MF . getFrameInfo ( ) -> CreateFixedObject ( Is<ISA_LIT>64 ? <NUM_LIT> : <NUM_LIT> , FPOffset ) ; FI -> setFramePointerSaveIndex ( FPSI ) ; } int TCSPDelta = <NUM_LIT> ; if ( PerformTailCallOpt && ( TCSPDelta = FI -> getTailCallSPDelta ( ) ) < <NUM_LIT> ) { int AddFPOffsetAmount = IsELF32_ABI ? - <NUM_LIT> : <NUM_LIT> ; MF . getFrameInfo ( ) -> CreateFixedObject ( - <NUM_LIT> * TCSPDelta , AddFPOffsetAmount + TCSPDelta ) ; } if ( EnableRegisterScavenging ) if ( needsFP ( MF ) || spillsCR ( MF ) ) { const TargetRegisterClass * GPRC = & <STR_LIT> ; const TargetRegisterClass * G8RC = & <STR_LIT> ; const TargetRegisterClass * RC = Is<ISA_LIT>64 ? G8RC :


<s> MachineInstr * MI = MRI -> getVRegDef ( SReg ) ; if ( ! MI ) return <STR_LIT> ; MachineOperand * MO = MI -> findRegisterDefOperand ( SReg ) ; if ( ! MO ) return <STR_LIT> ; assert ( MO -> isReg ( ) && <STR_LIT> ) ; if ( MI -> isCopy ( ) && usesRegClass ( MI -> getOperand ( <NUM_LIT> )


<s> void ix86_output_addr_diff_elt ( FILE * file , int value , int rel ) { if ( TARGET_64BIT ) fprintf ( file , <STR_LIT> ,

ASM_LONG , LPREFIX , value , LPREFIX , rel ) ;


<s> return parsePKHImm ( O , <STR_LIT> ,


<s> void <ISA_LIT>AsmParser :: printWarningWithFixIt ( const Twine & Msg , const Twine & FixMsg , SMRange Range ,


<s> DEBUG ( MI -> dump ( ) ) ; DEBUG ( dbgs ( ) << MI -> getDesc ( ) . getName ( ) << <STR_LIT> << ( <STR_LIT> . contains ( src . getReg ( ) ) ? <STR_LIT> : <STR_LIT> ) << <STR_LIT> << ( <STR_LIT> . contains ( dst . getReg ( ) ) ? <STR_LIT> : <STR_LIT> ) << <STR_LIT> ) ; unsigned xuse = <NUM_LIT> ; if ( srcside != dstside )


<s> Vm |= ( fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ) ; unsigned imm = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned cmode = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; DecodeStatus S = MCDisassembler :: Success ; if ( ! ( imm & <NUM_LIT> ) && cmode == <NUM_LIT> ) { Inst . setOpcode ( <STR_LIT> ) ; return DecodeNEONModImmInstruction ( Inst , Insn , Address , Decoder ) ; } if ( ! ( imm & <NUM_LIT> ) ) Check ( S , MCDisassembler :: SoftFail ) ; if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , Vd , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , Vm , Address , Decoder ) ) ) return MCDisassembler :: Fail ; Inst . addOperand ( MCOperand :: CreateImm ( <NUM_LIT>


<s> unsigned RegSize = std :: max ( <NUM_LIT> , InVT . getSizeInBits ( ) ) ; unsigned NumConcat = RegSize / InVT . getSizeInBits ( ) ; SmallVector < SDValue , <NUM_LIT> > Ops ( NumConcat , DAG . getConstant ( <NUM_LIT> , DL , InVT ) ) ; Ops [ <NUM_LIT> ] = Zext0 . getOperand ( <NUM_LIT> ) ; MVT ExtendedVT = <STR_LIT> ( <STR_LIT> , RegSize / <NUM_LIT> ) ; SDValue SadOp0 = DAG . getNode ( <STR_LIT> , DL , ExtendedVT , Ops ) ; Ops [ <NUM_LIT> ] = Zext1 . getOperand ( <NUM_LIT> ) ; SDValue SadOp1 = DAG . getNode ( <STR_LIT> , DL , ExtendedVT ,


<s> if ( auto USatVal = detectUSatPattern ( In , VT , DAG , DL ) ) return DAG . getNode ( <STR_LIT> , DL , VT , USatVal ) ; } if ( VT . isVector ( ) && isPowerOf2_32 ( VT . getVectorNumElements ( ) ) && ! ( Subtarget . hasAVX512 ( ) && InSVT == <STR_LIT> ) && ! ( Subtarget . hasBWI ( ) && InSVT == <STR_LIT> ) && ( SVT == <STR_LIT> || SVT == <STR_LIT> ) && ( InSVT == <STR_LIT> || InSVT == <STR_LIT> ) ) { if ( auto USatVal = detectSSatPattern ( In , VT , true ) ) { if ( SVT == <STR_LIT> && InSVT == <STR_LIT> ) { EVT MidVT = EVT :: getVectorVT ( * DAG . getContext ( ) , <STR_LIT> , VT . getVectorNumElements ( ) ) ; SDValue Mid = truncateVectorWithPACK ( <STR_LIT> , MidVT , USatVal , DL , DAG


<s> return ( from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM ? ! frame_pointer_needed : from == RS6000_PIC_OFFSET_TABLE_REGNUM ? ! TARGET_MINIMAL_TOC

|| TARGET_NO_TOC || constant_pool_empty_p ( ) : true ) ;


<s> if ( isMemNoOffset ( false , <NUM_LIT> ) ) return true ; return isMemNoOffset ( false


<s> static std :: string computeDataLayout ( const Triple


<s> if ( MEM_P ( x ) ) x = XEXP ( x , <NUM_LIT> ) ; y = x ; if ( TARGET_CMODEL != CMODEL_SMALL && GET_CODE ( y ) == LO_SUM ) y = XEXP ( y , <NUM_LIT> ) ; offset = NULL_RTX ; if ( GET_CODE ( y ) == PLUS && GET_MODE ( y ) == Pmode && CONST_INT_P ( XEXP ( y , <NUM_LIT> ) ) ) { offset = XEXP ( y , <NUM_LIT> ) ; y = XEXP ( y , <NUM_LIT> ) ; } if ( GET_CODE ( y ) == UNSPEC && XINT ( y , <NUM_LIT> ) == UNSPEC_TOCREL ) { y = XVECEXP ( y , <NUM_LIT> , <NUM_LIT> ) ; if ( TARGET_XCOFF && GET_CODE ( y ) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P ( y ) && rs6000_real_tls_symbol_ref_p ( get_pool_constant ( y ) ) ) return orig_x ; if ( offset != NULL_RTX ) y = gen_rtx_PLUS ( Pmode , y , offset ) ; if ( ! MEM_P ( orig_x ) ) return y ; else return replace_equiv_address_nv ( orig_x , y ) ; } if ( TARGET_MACHO && GET_CODE ( orig_x ) == LO_SUM && GET_CODE ( XEXP ( orig_x , <NUM_LIT> ) ) == CONST ) { y = XEXP ( XEXP ( orig_x , <NUM_LIT> ) , <NUM_LIT> ) ; if ( GET_CODE ( y ) == UNSPEC && XINT ( y , <NUM_LIT> ) == UNSPEC_MACHOPIC_OFFSET ) return XVECEXP


<s> return true ; } ; auto FindStartInsertionPoint = [ ] ( MachineInstr * Start , MachineInstr * Dec , MachineBasicBlock :: iterator & InsertPt , MachineBasicBlock * & InsertBB , ReachingDefAnalysis & RDA , InstSet & ToRemove ) { if ( Start -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) { InsertPt = MachineBasicBlock :: iterator ( Start ) ; InsertBB = Start -> getParent ( ) ; return true ; } unsigned CountReg = Start -> getOperand ( <NUM_LIT> ) . getReg ( ) ; auto IsMoveLR = [ & CountReg ] ( MachineInstr * MI ) { return MI -> getOpcode ( ) == <STR_LIT> && MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> && MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == CountReg && MI -> getOperand ( <NUM_LIT> ) . getImm ( ) == <STR_LIT> ; } ; if ( auto * LRDef = RDA . getUniqueReachingMIDef ( Start , <STR_LIT> ) ) { if ( IsMoveLR ( LRDef ) && RDA . hasSameReachingDef ( Start , LRDef , CountReg ) ) { SmallPtrSet < MachineInstr * , <NUM_LIT> > Ignore = { Dec } ; if ( ! TryRemove ( LRDef , RDA , ToRemove , Ignore ) ) return false ; InsertPt = MachineBasicBlock :: iterator ( Start ) ; InsertBB = Start -> getParent ( ) ; return true ; } } MachineBasicBlock * MBB = Start -> getParent ( ) ; if ( auto * LRDef = RDA . getLocalLiveOutMIDef ( MBB , <STR_LIT> ) ) { if ( IsMoveLR ( LRDef ) && RDA . hasSameReachingDef ( Start , LRDef , CountReg ) ) { SmallPtrSet < MachineInstr * , <NUM_LIT> > Ignore = { Start , Dec } ; if ( ! TryRemove ( LRDef , RDA , ToRemove , Ignore ) ) return false ; InsertPt = MachineBasicBlock :: iterator ( LRDef ) ; InsertBB = LRDef -> getParent ( ) ; return true ; } } if ( ! RDA . isSafeToDefRegAt ( Start , <STR_LIT> ) ) return false ; InsertPt = MachineBasicBlock :: iterator ( Start ) ; InsertBB = Start -> getParent ( ) ; return true ; } ; auto TryAdjustInsertionPoint = [ ] ( MachineBasicBlock :: iterator & InsertPt , MachineInstr * Start , ReachingDefAnalysis & RDA ) { MachineBasicBlock * MBB = InsertPt -> getParent ( ) ; MachineBasicBlock :: iterator FirstNonTerminator = MBB -> getFirstTerminator ( ) ; unsigned CountReg = Start -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( FirstNonTerminator == MBB -> end ( ) ) { if ( RDA . isReachingDefLiveOut ( Start , CountReg ) && RDA . isReachingDefLiveOut ( Start

, <STR_LIT> ) ) InsertPt = FirstNonTerminator ;


<s> BaseT :: getUnrollingPreferences ( L , UP ) ; UP . Partial = UP . Runtime = true ; UP . PartialThreshold = UP


<s> <ISA_LIT>Subtarget & <ISA_LIT>Subtarget :: initializeSubtargetDependencies ( const Triple & TT , StringRef CPU , StringRef FS , StringRef ABIName ) { bool Is64Bit = TT . isArch64Bit ( ) ; std :: string CPUName = CPU ; if ( CPUName . empty ( ) ) CPUName = Is64Bit ? <STR_LIT> : <STR_LIT> ; ParseSubtargetFeatures ( CPUName , FS ) ; if ( Is64Bit ) { XLenVT = <STR_LIT> ; XLen = <NUM_LIT> ; } TargetABI = <STR_LIT> ( TT , getFeatureBits (


<s> assert ( NumOperands == <NUM_LIT> && <STR_LIT> ) ; unsigned Op0 = getFPReg ( MI . getOperand ( NumOperands - <NUM_LIT> ) ) ; unsigned Op1 = getFPReg ( MI . getOperand ( NumOperands - <NUM_LIT> ) ) ; bool KillsOp0 = MI . killsRegister ( <STR_LIT> + Op0 ) ; bool KillsOp1 = MI . killsRegister ( <STR_LIT> + Op1 ) ; moveToTop ( Op0 ,


<s> MachineBasicBlock * MBB = MI . getParent ( ) ; const DebugLoc & DL = MI . getDebugLoc ( ) ; BuildMI ( * MBB , & MI , DL , TII . get ( <STR_LIT> ) ) ; MI . eraseFromParent ( ) ; return true ; } } return selectImpl ( MI ,


<s> SDValue Trunc = DAG . getZExtOrTrunc ( Clz , dl , <STR_LIT> ) ; SDValue Scc = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Trunc , DAG . getConstant ( Log2b , dl


<s> if ( ! MO1 . isReg ( ) ) { printOperand ( MI , Op , O ) ; return ; } O << <STR_LIT> << getRegisterName ( MO1 . getReg ( ) ) ; if ( ! MO2 . getReg ( ) ) { if ( <STR_LIT> ( MO3 . getImm ( ) ) ) O << <STR_LIT> << <STR_LIT> ( <STR_LIT> ( MO3 . getImm ( ) ) ) << <STR_LIT> ( MO3 . getImm ( ) ) ; O << <STR_LIT> ; return ; } O << <STR_LIT> << <STR_LIT> ( <STR_LIT> ( MO3 . getImm ( ) ) ) << getRegisterName ( MO2 . getReg ( ) ) ; if ( unsigned ShImm = <STR_LIT> ( MO3 . getImm ( ) ) ) O << <STR_LIT> << <STR_LIT> ( <STR_LIT> ( MO3 . getImm ( ) ) ) << <STR_LIT> << ShImm ; O <<


<s> void addDupAlignedMemory64or128Operands ( MCInst & Inst , unsigned N ) const { addAlignedMemoryOperands ( Inst , N


<s> for ( i = <NUM_LIT> ; i < <NUM_LIT> ; i ++

) if ( ! df_regs_ever_live_p ( i ) ) return i ;


<s> unsigned V2 = <STR_LIT> ( MO1 . getImm ( ) ) ; unsigned Binary = <NUM_LIT> << <NUM_LIT> ; Binary |= II -> getPredicate ( & MI ) << <STR_LIT> ; Binary |= getMachineOpValue ( MI , MO0 ) << <STR_LIT> ; Binary |= <NUM_LIT> << <STR_LIT> ; Binary |= getMachineSoImmOpValue ( V1 ) ; emitWordLE ( Binary ) ; Binary = <NUM_LIT> << <NUM_LIT> ; Binary |= II -> getPredicate ( & MI ) << <STR_LIT> ; Binary |= getMachineOpValue ( MI , MO0 ) << <STR_LIT> ; Binary |= getMachineOpValue ( MI , MO0 ) << <STR_LIT> ; Binary |= <NUM_LIT> << <STR_LIT> ; Binary |= getMachineSoImmOpValue ( V2 ) ; emitWordLE ( Binary )


<s> for ( const_iterator I = cbegin ( ) ; I != cend ( ) ; ++ I ) { struct CVIUnits inst ; inst . Units = I -> CVI . getUnits ( ) ; inst . Lanes = I -> CVI . getLanes ( ) ; if ( inst . Units == <NUM_LIT> ) continue ; hvxInsts . push_back (


<s> DAG . getContext ( ) -> diagnose ( DiagnosticInfoUnsupported ( MF . getFunction ( ) , Msg ,


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return


<s> } if ( numArgs > <NUM_LIT> ) { if ( ( copr2 = dyn_cast < Constant > ( aCI -> getArgOperand ( <NUM_LIT> ) ) ) == nullptr ) return false ; } double DVal0 [ <NUM_LIT> ] , DVal1 [ <NUM_LIT> ] ; bool hasTwoResults = ( FInfo . getId ( ) == <ISA_LIT>LibFunc :: EI_<ISA_LIT>NCOS ) ; if ( getVecSize ( FInfo ) == <NUM_LIT> ) { if ( ! evaluateScalarMathFunc ( FInfo , DVal0 [ <NUM_LIT> ] , DVal1 [ <NUM_LIT> ] , copr0 , copr1 , copr2 ) ) { return false ; } } else { ConstantDataVector * CDV0 = dyn_cast_or_null < ConstantDataVector > ( copr0 ) ; ConstantDataVector * CDV1 = dyn_cast_or_null < ConstantDataVector > ( copr1 ) ; ConstantDataVector * CDV2 = dyn_cast_or_null < ConstantDataVector > ( copr2 ) ; for ( int i = <NUM_LIT> ; i < getVecSize ( FInfo ) ; ++ i ) { Constant * celt0 = CDV0 ? CDV0 -> getElementAsConstant ( i ) : nullptr ; Constant * celt1 = CDV1 ? CDV1 -> getElementAsConstant ( i ) : nullptr ; Constant * celt2 = CDV2 ? CDV2 -> getElementAsConstant ( i ) : nullptr ; if ( ! evaluateScalarMathFunc ( FInfo , DVal0 [ i ] , DVal1 [ i ] , celt0 , celt1 , celt2 ) ) { return false ; } } } LLVMContext & context = CI -> getParent ( ) -> getParent ( ) -> getContext ( ) ; Constant * nval0 , * nval1 ; if ( getVecSize ( FInfo ) == <NUM_LIT> ) { nval0 = ConstantFP :: get ( CI -> getType ( ) , DVal0 [ <NUM_LIT> ] ) ; if ( hasTwoResults ) nval1 = ConstantFP :: get ( CI -> getType ( ) , DVal1 [ <NUM_LIT> ] ) ; } else { if ( getArgType ( FInfo ) == <ISA_LIT>LibFunc :: F32 ) { SmallVector < float , <NUM_LIT> > FVal0 , FVal1 ; for ( int i = <NUM_LIT> ; i < getVecSize ( FInfo ) ; ++ i ) FVal0 . push_back ( ( float ) DVal0 [ i ] ) ; ArrayRef < float > tmp0 ( FVal0 ) ; nval0 = ConstantDataVector :: get ( context , tmp0 ) ; if ( hasTwoResults ) { for ( int i = <NUM_LIT> ; i < getVecSize ( FInfo ) ; ++ i ) FVal1 . push_back ( ( float ) DVal1 [ i ] ) ; ArrayRef < float > tmp1 ( FVal1 ) ; nval1 = ConstantDataVector :: get ( context , tmp1 ) ; } } else { ArrayRef < double > tmp0 ( DVal0 ) ; nval0 = ConstantDataVector :: get ( context ,


<s> TargetRegistry :: RegisterMCCodeGenInfo ( TheTile64Target , createTile64MCCodeGenInfo ) ; TargetRegistry :: RegisterMCInstrInfo ( TheTile64Target


<s> if ( ! isPowerOf2_64 ( Val ) ) return false ; unsigned TestedBit = Log2_64 ( Val ) ; if ( TestedBit >= RegWidth ) return false ; FixedPos = CurDAG -> getTargetConstant ( TestedBit , <STR_LIT>


<s> SDValue Cond = N -> getOperand ( <NUM_LIT> ) ; SDValue ConstTrue = CurDAG -> getConstant ( N -> getOpcode ( ) == <STR_LIT> ? - <NUM_LIT> : <NUM_LIT> , dl , VT ) ; SDValue ConstFalse = CurDAG -> getConstant ( <NUM_LIT> , dl , VT ) ; do { SDNode * User = * N -> use_begin ( ) ; if ( User -> getNumOperands ( ) != <NUM_LIT> ) break ; auto TryFold = [ this , N , User , dl ] ( SDValue Val ) { SDValue UserO0 = User -> getOperand ( <NUM_LIT> ) , UserO1 = User -> getOperand ( <NUM_LIT> ) ; SDValue O0 = UserO0 . getNode ( ) == N ? Val : UserO0 ; SDValue O1 = UserO1 . getNode ( ) == N ? Val : UserO1 ; return CurDAG -> FoldConstantArithmetic ( User -> getOpcode ( ) , dl , User -> getValueType ( <NUM_LIT> ) , { O0 , O1 } ) ; } ; SDValue TrueRes = TryFold ( ConstTrue ) ; if ( ! TrueRes || TrueRes . isUndef ( ) ) break ; SDValue FalseRes = TryFold ( ConstFalse ) ; if ( ! FalseRes || FalseRes . isUndef ( ) ) break ; uint64_t True = cast < ConstantSDNode > ( TrueRes ) -> getZExtValue ( ) , False = cast < ConstantSDNode > ( FalseRes ) -> getZExtValue ( ) ; if ( ! isInt < <NUM_LIT> > ( True ) || ! isInt < <NUM_LIT> > ( False ) ) break ; Res = CurDAG -> getSelect ( dl , User -> getValueType ( <NUM_LIT> ) , Cond , TrueRes , FalseRes ) ; N = User ; ConstTrue =


<s> <ISA_LIT>ABIInfo <ISA_LIT>ABIInfo :: computeTargetABI ( const Triple & TT , StringRef CPU , const MCTargetOptions & Options ) { StringRef ABIName = Options . getABIName ( ) ; if ( ABIName . startswith ( <STR_LIT> ) ) return <ISA_LIT>ABIInfo :: O32 ( ) ; if ( ABIName . startswith ( <STR_LIT> ) ) return <ISA_LIT>ABIInfo :: N32 ( ) ; if ( ABIName . startswith ( <STR_LIT> ) ) return <ISA_LIT>ABIInfo :: N64 ( ) ; if ( ABIName . startswith ( <STR_LIT> ) ) return <ISA_LIT>ABIInfo :: CheriPureCap ( ) ; if ( TT . getEnvironment ( ) == llvm :: Triple :: GNUABIN32 ) return <ISA_LIT>ABIInfo :: N32 ( ) ; assert ( Options . getABIName ( ) . empty ( )


<s> Builder . SetCurrentDebugLocation ( I . getDebugLoc ( ) ) ; Type * I32Ty = Builder . getInt32Ty ( ) ; Type * PT = PointerType :: get ( I32Ty , I . getPointerAddressSpace ( ) ) ; Value * BitCast = Builder . CreateBitCast ( I . getPointerOperand ( ) , PT ) ; Value * WidenLoad = Builder . CreateLoad ( BitCast ) ; int TySize = Mod -> getDataLayout ( ) . getTypeSizeInBits ( I . getType ( ) ) ; Type * IntNTy = Builder . getIntNTy ( TySize ) ; Value * ValTrunc = Builder . CreateTrunc (


<s> SmallVector < <STR_LIT> , <NUM_LIT> > ArgFlags ; Args . reserve ( I -> getNumOperands ( ) ) ; ArgRegs . reserve ( I -> getNumOperands ( ) ) ; ArgVTs . reserve ( I -> getNumOperands ( ) ) ; ArgFlags . reserve ( I -> getNumOperands ( ) ) ; for ( Value * Op : I -> operands ( ) ) { unsigned Arg = getRegForValue ( Op ) ; if ( Arg == <NUM_LIT> ) return false ; Type * ArgTy = Op -> getType ( ) ; MVT ArgVT ; if ( ! isTypeLegal ( ArgTy , ArgVT ) ) return false ; <STR_LIT> Flags ; Flags . setOrigAlign ( Align ( DL . getABITypeAlignment ( ArgTy ) ) ) ; Args . push_back ( Op ) ; ArgRegs . push_back ( Arg ) ; ArgVTs . push_back ( ArgVT ) ; ArgFlags . push_back ( Flags ) ; } SmallVector < Register , <NUM_LIT> > RegArgs ; unsigned NumBytes ; if ( ! ProcessCallArgs ( Args , ArgRegs , ArgVTs , ArgFlags , RegArgs , CC , NumBytes , false ) ) return false ; Register CalleeReg ; if ( Subtarget -> genLongCalls ( ) ) { CalleeReg = getLibcallReg ( TLI . getLibcallName ( Call ) ) ; if ( CalleeReg == <NUM_LIT> ) return false ; } unsigned CallOpc = <ISA_LIT>SelectCallOp ( Subtarget


<s> MBBInfoMap :: const_iterator It = BlockInfoMap . find ( MBB ) ; if ( It == BlockInfoMap . end ( ) ) return INVALIDSCCNUM ; return ( * It ) . second ->


<s> for ( MapVector < MCSymbol * , MCSymbol * > :: iterator I = TOC . begin ( ) , E = TOC . end ( ) ; I != E ; ++ I ) { OutStreamer . EmitLabel ( I -> second ) ; MCSymbol * S = I -> first ; if ( is<ISA_LIT>64 ) TS . emitTCEntry ( * S ) ; else OutStreamer . EmitSymbolValue ( S , <NUM_LIT> ) ; } } return AsmPrinter :: doFinalization ( M )


<s> auto InsertZExt = [ & ] ( Value * V , Instruction * InsertPt ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * V << <STR_LIT> ) ; Builder . SetInsertPoint ( InsertPt ) ; if ( auto * I = dyn_cast < Instruction > ( V ) ) Builder . SetCurrentDebugLocation ( I -> getDebugLoc ( ) ) ; auto * ZExt = cast < Instruction > ( Builder . CreateZExt ( V , ExtTy ) ) ; if ( isa < Argument > ( V ) ) ZExt -> moveBefore ( InsertPt ) ; else ZExt -> moveAfter ( InsertPt ) ; ReplaceAllUsersOfWith ( V , ZExt ) ; NewInsts . insert ( ZExt ) ; TruncTysMap [ ZExt ] = TruncTysMap [ V ] ; } ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; for ( auto V : Sources ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * V << <STR_LIT> ) ; if ( auto * I = dyn_cast < Instruction > ( V ) ) InsertZExt ( I , I ) ; else if ( auto * Arg = dyn_cast < Argument > ( V ) ) { BasicBlock & BB = Arg -> getParent ( ) -> front ( ) ; InsertZExt ( Arg , & * BB . getFirstInsertionPt ( ) ) ; } else { llvm_unreachable ( <STR_LIT> ) ; } Promoted . insert ( V ) ; } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; for ( auto * V : Visited ) { if ( Sources . count ( V ) ) continue ; auto * I = cast < Instruction > ( V ) ; if ( Sinks . count ( I ) ) continue ; for ( unsigned i = <NUM_LIT> , e = I -> getNumOperands ( ) ; i < e ; ++ i ) { Value * Op = I -> getOperand ( i ) ; if ( ( Op -> getType ( ) == ExtTy ) || ! isa < IntegerType > ( Op -> getType ( ) ) ) continue ; if ( auto * Const = dyn_cast < ConstantInt > ( Op ) ) FixConst ( Const , I ) ; else if ( isa < UndefValue > ( Op ) ) I -> setOperand ( i , UndefValue :: get ( ExtTy ) ) ; } if ( shouldPromote ( I ) ) { I -> mutateType ( ExtTy ) ; Promoted . insert ( I ) ; } } for ( auto * V : Visited ) { if ( Sources . count ( V ) ) continue ; if ( ! shouldPromote ( V ) || isPromotedResultSafe (


<s> unsigned ScratchRsrcReg = MFI -> getScratchRSrcReg ( ) ; if ( ScratchRsrcReg == <STR_LIT> || ! MRI . isPhysRegUsed ( ScratchRsrcReg ) ) return <STR_LIT> ; if ( ST . hasSGPRInitBug ( ) || ScratchRsrcReg != TRI -> reservedPrivateSegmentBufferReg ( MF ) ) return ScratchRsrcReg ; unsigned NumPreloaded = ( MFI -> getNumPreloadedSGPRs ( ) + <NUM_LIT> ) / <NUM_LIT> ; ArrayRef < MCPhysReg > AllSGPR128s = getAllSGPR128 ( ST , MF ) ; AllSGPR128s = AllSGPR128s . slice ( std :: min ( static_cast < unsigned > ( AllSGPR128s . size ( ) ) , NumPreloaded ) ) ; for ( MCPhysReg Reg : AllSGPR128s ) { if ( ! MRI . isPhysRegUsed ( Reg ) && MRI . isAllocatable ( Reg ) ) { MRI . replaceRegWith ( ScratchRsrcReg , Reg ) ; MFI -> setScratchRSrcReg ( Reg ) ; return Reg ; } } return


<s> MCRegisterInfo * X = new MCRegisterInfo ( ) ; if ( TT . getArch ( ) == Triple :: r600 ) Init<ISA_LIT>MCRegisterInfo ( X , <NUM_LIT> ) ; else Init<ISA_LIT>MCRegisterInfo ( X , <STR_LIT> ) ; return X


<s> BuildMI ( MBB , MBBI , DL , STI . getInstrInfo ( ) -> get ( <STR_LIT> ) , <STR_LIT> ) ; BuildMI ( MBB , MBBI , DL , STI . getInstrInfo ( ) -> get ( <STR_LIT> ) ) ; STI . getInstrInfo ( ) -> loadRegFromStackSlot ( MBB , MBBI , <STR_LIT> , <ISA_LIT>FI -> getISRRegFI ( <NUM_LIT> ) , PtrRC , STI . getRegisterInfo ( ) ) ; BuildMI ( MBB , MBBI , DL , STI . getInstrInfo ( ) -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ; STI . getInstrInfo ( ) -> loadRegFromStackSlot ( MBB , MBBI , <STR_LIT> , <ISA_LIT>FI ->


<s> break ; case <STR_LIT> : Value -= <NUM_LIT> ; Value = ( int64_t ) Value / <NUM_LIT> ; if ( ! isIntN ( <NUM_LIT> , Value ) && Ctx ) Ctx -> FatalError ( Fixup . getLoc ( ) , <STR_LIT> ) ; break ; case <STR_LIT> : Value = ( int64_t ) Value / <NUM_LIT> ; if ( ! isIntN ( <NUM_LIT> , Value ) && Ctx ) Ctx -> FatalError ( Fixup . getLoc ( ) , <STR_LIT> ) ; break ; case <STR_LIT> : Value >>= <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Value = ( ( Value + <NUM_LIT> ) >> <NUM_LIT> ) & <NUM_LIT> ; break ; case <STR_LIT> : Value = ( ( Value + <NUM_LIT> ) >> <NUM_LIT> ) & <NUM_LIT> ; break ; case <STR_LIT> : Value = ( ( Value + <NUM_LIT> ) >> <NUM_LIT> ) & <NUM_LIT> ; break ; case <STR_LIT> : Value >>=


<s> } break ; } case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : { switch ( Opc ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { unsigned EntrySize = ( Opc == <STR_LIT> ) ? <NUM_LIT> : ( ( Opc == <STR_LIT> ) ? <NUM_LIT> : <NUM_LIT> ) ; unsigned NumOps = TID . getNumOperands ( ) ; MachineOperand JTOP = MI -> getOperand ( NumOps - ( TID . isPredicable ( ) ? <NUM_LIT> : <NUM_LIT> ) ) ; unsigned JTI = JTOP . getIndex ( ) ; const MachineJumpTableInfo * MJTI = MF -> getJumpTableInfo ( ) ; assert ( MJTI != <NUM_LIT> ) ; const std :: vector < MachineJumpTableEntry > & JT = MJTI -> getJumpTables ( ) ; assert ( JTI < JT . size ( ) ) ; unsigned InstSize = ( Opc == <STR_LIT> || Opc == <STR_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; unsigned NumEntries = getNumJTEntries ( JT , JTI ) ; if ( Opc == <STR_LIT> && ( NumEntries & <NUM_LIT> ) ) ++ NumEntries ; return NumEntries * EntrySize


<s> ri_gprmask = <NUM_LIT> ; ri_cprmask [ <NUM_LIT> ] = ri_cprmask [ <NUM_LIT> ] = ri_cprmask [ <NUM_LIT> ] = ri_cprmask [ <NUM_LIT> ] = <NUM_LIT> ; ri_gp_value = <NUM_LIT> ; const MCRegisterInfo * TRI = Context . getRegisterInfo ( ) ; GPR32RegClass = & ( TRI -> getRegClass ( <STR_LIT> ) ) ; GPR64RegClass = & ( TRI ->


<s> return CallConv == CallingConv :: C || CallConv == CallingConv :: Fast || CallConv == CallingConv :: Cold || CallConv == CallingConv

:: PreserveMost || CallConv == CallingConv :: PreserveAll || CallConv == CallingConv :: CXX_FAST_TLS ;


<s> MIB = BuildMI ( * I -> getParent ( ) , I , I -> getDebugLoc ( ) , TII -> get ( NewOpc ) ) . add ( getLdStRegOp ( * Update ) ) . add ( getLdStRegOp ( * I ) ) . add ( getLdStBaseOp ( * I ) ) . addImm ( Value / Scale ) . setMemRefs ( I -> memoperands ( ) ) . setMIFlags ( I -> mergeFlagsWith ( * Update ) ) ; } else { MIB = BuildMI ( * I -> getParent ( ) , I , I -> getDebugLoc ( ) , TII -> get ( NewOpc ) ) . add ( getLdStRegOp ( * Update ) ) . add ( getLdStRegOp ( * I , <NUM_LIT> ) ) . add ( getLdStRegOp ( * I ,

<NUM_LIT> ) ) . add ( getLdStBaseOp ( * I ) ) . addImm ( Value / Scale ) . setMemRefs ( I -> memoperands ( ) ) . setMIFlags ( I -> mergeFlagsWith ( * Update ) ) ;


<s> auto Op = make_unique < <ISA_LIT>Operand > ( Register ) ; Op -> Reg . RegNum = RegNo ; Op -> StartLoc = S ; Op -> EndLoc


<s> MI -> getOperand ( FIOperandNum ) . ChangeToRegister ( BasePtr , false ) ; } else { int64_t OldOffset = Offset ; int64_t Mask = <NUM_LIT> ; do { Offset = OldOffset & Mask ; OpcodeForOffset = TII -> getOpcodeForOffset ( Opcode , Offset ) ; Mask >>= <NUM_LIT> ; assert ( Mask && <STR_LIT> ) ; } while ( ! OpcodeForOffset ) ; unsigned ScratchReg = MF . getRegInfo ( ) . createVirtualRegister ( & <STR_LIT> ) ; int64_t HighOffset = OldOffset - Offset ; if ( MI -> getDesc ( ) . TSFlags & <STR_LIT> && MI -> getOperand ( FIOperandNum + <NUM_LIT> ) . getReg ( ) == <NUM_LIT> ) { TII -> loadImmediate ( MBB , MI , ScratchReg , HighOffset ) ; MI -> getOperand ( FIOperandNum ) . ChangeToRegister ( BasePtr , false ) ; MI -> getOperand ( FIOperandNum + <NUM_LIT> ) . ChangeToRegister ( ScratchReg , false , false , true ) ; } else { unsigned LAOpcode = TII -> getOpcodeForOffset ( <STR_LIT> , HighOffset ) ; if ( LAOpcode ) BuildMI ( MBB , MI , DL , TII -> get ( LAOpcode ) , ScratchReg ) . addReg ( BasePtr

) . addImm ( HighOffset ) . addReg ( <NUM_LIT> ) ;


<s> if ( SelectADDRriS11_2 ( N1 , CPTmpN1_0 , CPTmpN1_1 ) && N1 . getNode ( ) -> getValueType ( <NUM_LIT> ) == <STR_LIT> ) { const <ISA_LIT>InstrInfo * TII = Subtarget -> getInstrInfo ( ) ; if ( TII -> isValidAutoIncImm ( LoadedVT , Val ) ) { SDValue TargetConstVal = CurDAG -> getTargetConstant ( Val , <STR_LIT> ) ; SDValue TargetConst0 = CurDAG -> getTargetConstant ( <NUM_LIT> , <STR_LIT> ) ; SDNode * Result_1 = CurDAG -> getMachineNode ( Opcode , dl , <STR_LIT> , <STR_LIT> , <STR_LIT> , Base , TargetConstVal , Chain ) ; SDNode * Result_2 = CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , TargetConst0 ) ; SDNode * Result_3 = CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , <STR_LIT> , SDValue ( Result_2 , <NUM_LIT> ) , SDValue ( Result_1 , <NUM_LIT> ) ) ; MachineSDNode :: mmo_iterator MemOp = MF -> allocateMemRefsArray ( <NUM_LIT> ) ; MemOp [ <NUM_LIT> ] = LD -> getMemOperand ( ) ; cast < MachineSDNode > ( Result_1 ) -> setMemRefs ( MemOp , MemOp + <NUM_LIT> ) ; const SDValue Froms [ ] = { SDValue ( LD , <NUM_LIT> ) , SDValue ( LD , <NUM_LIT> ) , SDValue ( LD , <NUM_LIT> ) } ; const SDValue Tos [ ] = { SDValue ( Result_3 , <NUM_LIT> ) , SDValue ( Result_1 , <NUM_LIT> ) , SDValue ( Result_1 , <NUM_LIT> ) } ; ReplaceUses ( Froms , Tos , <NUM_LIT> ) ; return Result_3 ; } SDValue TargetConst0 = CurDAG -> getTargetConstant ( <NUM_LIT> , <STR_LIT> ) ; SDValue TargetConstVal = CurDAG -> getTargetConstant ( Val , <STR_LIT> ) ; SDNode * Result_1 = CurDAG -> getMachineNode ( Opcode , dl , <STR_LIT> , <STR_LIT> , Base , TargetConst0 , Chain ) ; SDNode * Result_2 = CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , TargetConst0 ) ; SDNode * Result_3 = CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , <STR_LIT> , SDValue ( Result_2 , <NUM_LIT> ) , SDValue ( Result_1 , <NUM_LIT> ) ) ; SDNode * Result_4 = CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , Base , TargetConstVal , SDValue (


<s> if ( ! get<ISA_LIT>Subtarget ( ) . has<ISA_LIT>64 ( ) ) PM . add

( create<ISA_LIT>EmitGPRestorePass ( get<ISA_LIT>TargetMachine ( ) ) ) ;


<s> SDValue InVec1 = DAG . getUNDEF ( VT ) ; assert ( ( VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> ) && <STR_LIT> ) ; unsigned ExpectedOpcode = <STR_LIT> ; unsigned NextExpectedOpcode = <STR_LIT> ; bool AddFound = false ; bool SubFound = false ; for ( unsigned i = <NUM_LIT> , e = NumElts ; i != e ; ++ i ) { SDValue Op = BV -> getOperand ( i ) ; unsigned Opcode = Op . getOpcode ( ) ; if ( Opcode == <STR_LIT> ) { std :: swap ( ExpectedOpcode , NextExpectedOpcode ) ; continue ; } if ( Opcode != ExpectedOpcode ) return SDValue ( ) ; SDValue Op0 = Op . getOperand ( <NUM_LIT> ) ; SDValue Op1 = Op . getOperand ( <NUM_LIT> ) ; if ( Op0 . getOpcode ( ) != <STR_LIT> || Op1 . getOpcode ( ) != <STR_LIT> || ! isa < ConstantSDNode > ( Op0 . getOperand ( <NUM_LIT> ) ) || ! isa < ConstantSDNode > ( Op1 . getOperand ( <NUM_LIT> ) ) || Op0 . getOperand ( <NUM_LIT> ) != Op1 . getOperand ( <NUM_LIT> ) ) return SDValue ( ) ; unsigned I0 = cast < ConstantSDNode > ( Op0 . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; if ( I0 != i ) return SDValue ( ) ; if ( i & <NUM_LIT> ) AddFound = true ; else SubFound = true ; if ( InVec0 . getOpcode ( ) == <STR_LIT> ) InVec0 = Op0 . getOperand ( <NUM_LIT> ) ; if ( InVec1 . getOpcode ( ) == <STR_LIT> ) InVec1 = Op1 . getOperand ( <NUM_LIT> ) ; if ( InVec0 != Op0 . getOperand ( <NUM_LIT> ) ) { if ( ExpectedOpcode == <STR_LIT> ) return SDValue ( ) ; std :: swap ( Op0 , Op1 ) ; if ( InVec0 != Op0 . getOperand ( <NUM_LIT> ) ) return SDValue ( ) ; } if ( InVec1 != Op1 . getOperand (


<s> arm_stack_offsets * offsets ; offsets = arm_get_frame_offsets ( ) ; saved_regs_mask = offsets -> saved_regs_mask ; for ( i = <NUM_LIT> , num_regs = <NUM_LIT> ; i <= LAST_ARM_REGNUM ; i ++ ) if ( saved_regs_mask & ( <NUM_LIT> << i ) ) num_regs ++ ; if ( ! simple_return && saved_regs_mask ) { gcc_assert ( ! IS_CMSE_ENTRY ( arm_current_func_type ( ) ) ) ; if ( num_regs == <NUM_LIT> ) { rtx par = gen_rtx_PARALLEL ( VOIDmode , rtvec_alloc ( <NUM_LIT> ) ) ; rtx reg = gen_rtx_REG (


<s> bool isMachO = MAI . hasSubsectionsViaSymbols ( ) ; StringRef Name ; bool needFuncName = true ; if ( isMachO ) { const AsmToken & Tok = Parser . getTok ( ) ; if ( Tok . isNot ( AsmToken :: EndOfStatement ) ) { if ( Tok . isNot ( AsmToken :: Identifier ) && Tok . isNot ( AsmToken ::

String ) ) return Error ( L , <STR_LIT> ) ;


<s> if ( PreferredWidth >= <NUM_LIT> && ST -> hasAVX512 ( ) ) Options . LoadSizes . push_back ( <NUM_LIT> ) ; if ( PreferredWidth >= <NUM_LIT> && ST -> hasAVX ( ) ) Options . LoadSizes . push_back ( <NUM_LIT> ) ; if ( PreferredWidth >= <NUM_LIT> && ST -> hasSSE2 ( ) ) Options . LoadSizes . push_back ( <NUM_LIT> ) ; Options . AllowOverlappingLoads = true ; } if ( ST -> is64Bit ( ) ) { Options . LoadSizes . push_back (


<s> OperandMatchResultTy parsePCRel16 ( OperandVector & Operands ) { return parsePCRel ( Operands , <NUM_LIT>


<s> static inline enum insn_code rs6000_htm_spr_icode ( bool nonvoid ) { if ( nonvoid ) return ( TARGET_64BIT ) ? CODE_FOR_htm_mfspr_di : CODE_FOR_htm_mfspr_si ; else return ( TARGET_64BIT ) ?


<s> gcc_assert ( GET_MODE_SIZE ( o ) == GET_MODE_SIZE ( n ) ) ; return


<s> bool isVISrcV2F16 ( ) const { return isVISrcF16 ( ) ||


<s> DebugLoc dl = SVOp -> getDebugLoc ( ) ; unsigned NumElems = VT . getVectorNumElements ( ) ; MVT NewVT ; unsigned Scale ; switch ( VT . SimpleTy ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : NewVT = <STR_LIT> ; Scale = <NUM_LIT> ; break ; case <STR_LIT> : NewVT = <STR_LIT> ; Scale = <NUM_LIT> ; break ; case <STR_LIT> : NewVT = <STR_LIT> ; Scale = <NUM_LIT> ; break ; case <STR_LIT> : NewVT = <STR_LIT> ; Scale = <NUM_LIT> ; break ; case <STR_LIT> : NewVT = <STR_LIT> ; Scale = <NUM_LIT> ; break ; case <STR_LIT> : NewVT = <STR_LIT> ; Scale = <NUM_LIT> ; break ; } SmallVector < int , <NUM_LIT> > MaskVec ; for ( unsigned i = <NUM_LIT> ; i != NumElems ; i += Scale ) { int StartIdx = - <NUM_LIT> ; for ( unsigned j = <NUM_LIT> ; j != Scale ; ++ j ) { int EltIdx = SVOp -> getMaskElt ( i + j ) ; if ( EltIdx < <NUM_LIT> ) continue ; if ( StartIdx < <NUM_LIT> ) StartIdx = ( EltIdx / Scale ) ; if ( EltIdx != ( int ) ( StartIdx * Scale + j ) ) return SDValue ( ) ; } MaskVec . push_back ( StartIdx


<s> } markSuperRegs ( Reserved , <STR_LIT> ) ; markSuperRegs ( Reserved , <STR_LIT> ) ; markSuperRegs ( Reserved , <STR_LIT> ) ; markSuperRegs ( Reserved , <STR_LIT> ) ; if ( TFI -> hasFP ( MF ) ) markSuperRegs ( Reserved , <STR_LIT> ) ; if ( TFI -> hasBP ( MF ) ) markSuperRegs ( Reserved , <STR_LIT> ( ) ) ; markSuperRegs ( Reserved , <STR_LIT> ) ; markSuperRegs ( Reserved , <STR_LIT> ) ; markSuperRegs ( Reserved , <STR_LIT> ) ; markSuperRegs ( Reserved , <STR_LIT> ) ; markSuperRegs ( Reserved , <STR_LIT>


<s> const BasicBlock * LLVM_BB = MBB -> getBasicBlock ( ) ; MachineFunction :: iterator MBBIter = MBB ; ++ MBBIter ; MachineFunction * F = MBB -> getParent ( ) ; MachineBasicBlock * thisMBB = MBB ; MachineBasicBlock * newMBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * nextMBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; F -> insert ( MBBIter , newMBB ) ; F -> insert ( MBBIter , nextMBB ) ; nextMBB -> splice ( nextMBB -> begin ( ) , thisMBB , llvm :: next ( MachineBasicBlock :: iterator ( bInstr ) ) , thisMBB -> end ( ) ) ; nextMBB -> transferSuccessorsAndUpdatePHIs ( thisMBB ) ; thisMBB -> addSuccessor ( newMBB ) ; newMBB -> addSuccessor ( nextMBB ) ; newMBB -> addSuccessor ( newMBB ) ; DebugLoc dl = bInstr -> getDebugLoc ( ) ; assert ( bInstr -> getNumOperands ( ) < <STR_LIT> + <NUM_LIT> && <STR_LIT> ) ; MachineOperand & dest1Oper = bInstr -> getOperand ( <NUM_LIT> ) ; MachineOperand & dest2Oper = bInstr -> getOperand ( <NUM_LIT> ) ; MachineOperand * argOpers [ <NUM_LIT> + <STR_LIT> ] ; for ( int i = <NUM_LIT> ; i < <NUM_LIT> + <STR_LIT> ; ++ i ) { argOpers [ i ] = & bInstr -> getOperand ( i + <NUM_LIT> ) ; if ( argOpers [ i ] -> isReg ( ) && argOpers [ i ] -> isUse ( ) ) argOpers [ i ] -> setIsKill ( false ) ; } int lastAddrIndx = <STR_LIT> - <NUM_LIT> ; unsigned t1 = F -> getRegInfo ( ) . createVirtualRegister ( RC ) ; MachineInstrBuilder MIB = BuildMI ( thisMBB , dl , TII -> get ( LoadOpc ) , t1 ) ; for ( int i = <NUM_LIT> ; i <= lastAddrIndx ; ++ i ) ( * MIB ) . addOperand ( * argOpers [ i ] ) ; unsigned t2 = F -> getRegInfo ( ) . createVirtualRegister ( RC ) ; MIB = BuildMI ( thisMBB , dl , TII -> get ( LoadOpc ) , t2 ) ; for ( int i = <NUM_LIT> ; i <= lastAddrIndx - <NUM_LIT> ; ++ i ) ( * MIB ) . addOperand ( * argOpers [ i ] ) ; MachineOperand newOp3 = * ( argOpers [ <NUM_LIT>


<s> pReloc . target ( ) = pReloc . symValue ( )


<s> unsigned <ISA_LIT>FastISel :: getLibcallReg ( const Twine & Name ) { Type * GVTy = Type :: getInt32PtrTy ( * Context , <NUM_LIT> ) ; EVT LCREVT = TLI . getValueType ( GVTy ) ; if ( ! LCREVT . isSimple ( ) ) return <NUM_LIT> ; GlobalValue * GV = new GlobalVariable ( M , Type :: getInt32Ty ( * Context ) , false , GlobalValue :: ExternalLinkage , <NUM_LIT> , Name ) ; assert ( GV -> getType ( ) == GVTy &&


<s> static bool isPSHUFHWMask ( ArrayRef < int > Mask , MVT VT , bool HasInt256 ) { if ( VT != <STR_LIT> && ( ! HasInt256 || VT != <STR_LIT> ) ) return false ; if ( ! isSequentialOrUndefInRange ( Mask , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> ) ) return false ; for ( unsigned i = <NUM_LIT> ; i != <NUM_LIT> ; ++ i ) if ( ! isUndefOrInRange ( Mask [ i ] , <NUM_LIT> , <NUM_LIT> ) ) return false ; if ( VT == <STR_LIT> ) { if ( ! isSequentialOrUndefInRange ( Mask , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> ) ) return false ; for ( unsigned i = <NUM_LIT> ; i != <NUM_LIT> ; ++ i ) if ( ! isUndefOrInRange ( Mask [ i ] , <NUM_LIT> , <NUM_LIT>


<s> explicit <ISA_LIT>MachineFunctionInfo ( MachineFunction &