<s> case GEU : case GTU : code = reverse_condition ( code ) ; branch_code = EQ ; break ; default : gcc_unreachable ( ) ; } if ( cmp_mode != DImode && CONST_INT_P ( op1 ) && ( ! satisfies_constraint_I ( op1 ) || code == LEU ) ) { HOST_WIDE_INT n = trunc_int_for_mode ( INTVAL ( op1 ) , SImode ) ; switch ( code ) { case EQ : if ( ! ( symbolic_operand ( op0 , VOIDmode ) || ( REG_P ( op0 ) && REG_POINTER ( op0 ) ) ) ) { HOST_WIDE_INT add ; if ( n != - <NUM_LIT> - <NUM_LIT> ) add = - n ; else add = n ; op0 = force_reg ( SImode , op0 )


<s> return parseAddress ( Operands , BDRMem , <STR_LIT> , GR64Reg


<s> void <ISA_LIT>InstrInfo :: insertIndirectBranch ( MachineBasicBlock & MBB , MachineBasicBlock & NewDestBB , MachineBasicBlock & RestoreBB , const DebugLoc & DL , int64_t BrOffset , RegScavenger


<s> SelectCode ( N ) ; return ; } MVT VT = N -> getSimpleValueType ( <NUM_LIT> ) ; bool Is32 = ( VT == <STR_LIT> ) ; SDLoc SL ( N ) ; MachineSDNode * CmpSwap = nullptr ; if ( Subtarget -> hasAddr64 ( ) ) { SDValue SRsrc , VAddr , SOffset , Offset , GLC , SLC ; if ( SelectMUBUFAddr64 ( Mem -> getBasePtr ( ) , SRsrc , VAddr , SOffset , Offset , SLC ) ) { unsigned Opcode = Is32 ? <STR_LIT> : <STR_LIT> ; SDValue CmpVal = Mem -> getOperand ( <NUM_LIT> ) ; SDValue Ops [ ] = { CmpVal , VAddr , SRsrc , SOffset , Offset , SLC , Mem -> getChain ( ) } ; CmpSwap = CurDAG -> getMachineNode ( Opcode , SL , Mem -> getVTList ( ) , Ops ) ; } } if ( ! CmpSwap ) { SDValue SRsrc , SOffset , Offset , SLC ; if ( SelectMUBUFOffset ( Mem -> getBasePtr ( ) , SRsrc , SOffset , Offset , SLC ) ) { unsigned Opcode = Is32 ? <STR_LIT> : <STR_LIT> ; SDValue CmpVal = Mem -> getOperand ( <NUM_LIT> ) ; SDValue Ops [ ] = { CmpVal , SRsrc , SOffset , Offset , SLC , Mem -> getChain ( ) } ; CmpSwap = CurDAG -> getMachineNode ( Opcode , SL , Mem -> getVTList ( ) , Ops ) ; } } if ( ! CmpSwap ) { SelectCode ( N ) ; return ; } MachineSDNode :: mmo_iterator MMOs = MF -> allocateMemRefsArray ( <NUM_LIT> ) ; * MMOs = Mem -> getMemOperand ( ) ; CmpSwap -> setMemRefs ( MMOs , MMOs + <NUM_LIT> ) ; unsigned SubReg = Is32 ? <STR_LIT> : <STR_LIT> ; SDValue Extract = CurDAG -> getTargetExtractSubreg ( SubReg , SL , VT , SDValue ( CmpSwap


<s> MVT DestVT = VA . getLocVT ( ) ; MVT SrcVT = ArgVT ; ArgReg = emitIntExt ( SrcVT , ArgReg , DestVT , false ) ; if ( ! ArgReg ) return false ; break ; } case CCValAssign :: ZExt : { MVT DestVT = VA . getLocVT ( ) ; MVT SrcVT = ArgVT ; ArgReg = emitIntExt ( SrcVT , ArgReg , DestVT , true ) ; if ( ! ArgReg ) return false ; break ; } default : llvm_unreachable ( <STR_LIT> ) ; } if ( VA . isRegLoc ( ) && ! VA . needsCustom ( ) ) { BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: COPY ) , VA . getLocReg ( ) ) . addReg ( ArgReg ) ; CLI . OutRegs . push_back ( VA . getLocReg ( ) ) ; } else if ( VA . needsCustom ( ) ) { llvm_unreachable ( <STR_LIT> ) ; return false ; } else { assert ( VA . isMemLoc ( ) && <STR_LIT> ) ; if ( isa < UndefValue > ( ArgVal ) ) continue ; unsigned ArgSize = alignTo ( ArgVT . getSizeInBits ( ) , <NUM_LIT> ) ; unsigned BEAlign = <NUM_LIT> ; if ( ArgSize < <NUM_LIT> && ! Subtarget -> isLittle ( ) ) BEAlign = <NUM_LIT> - ArgSize ; Address Addr ; Addr . setKind ( Address :: RegBase ) ; Addr . setReg (


<s> args . reserve ( nargs ) ; for ( unsigned int i = <NUM_LIT> ; i < nargs ; ++ i ) args . quick_push ( expand_normal ( CALL_EXPR_ARG ( call_expr , i ) ) ) ; return base -> expand (


<s> StringRef getHwreg ( unsigned Id , const MCSubtargetInfo


<s> std :: string Ret = <STR_LIT> ; if ( isLittle ) Ret += <STR_LIT> ; else Ret += <STR_LIT> ; Ret += DataLayout :: getManglingComponent ( Triple ) ; Ret += <STR_LIT> ; if ( ABI != <ISA_LIT>BaseTargetMachine :: <ISA_LIT>_ABI_APCS ) Ret += <STR_LIT> ; if ( ABI == <ISA_LIT>BaseTargetMachine :: <ISA_LIT>_ABI_APCS ) Ret += <STR_LIT> ; if ( ABI == <ISA_LIT>BaseTargetMachine :: <ISA_LIT>_ABI_APCS ) Ret += <STR_LIT> ; else Ret += <STR_LIT> ; Ret += <STR_LIT> ; Ret += <STR_LIT> ; if ( Triple . isOSNaCl ( ) ) Ret += <STR_LIT> ; else if ( ABI == <ISA_LIT>BaseTargetMachine :: <ISA_LIT>_ABI_AAPCS ) Ret += <STR_LIT> ; else Ret += <STR_LIT>


<s> if ( GET_MODE_SIZE ( mode ) >= <NUM_LIT> ) return ( code == CONST_INT && INTVAL ( index ) < CSKY_LD16_MAX_OFFSET ( SImode ) && INTVAL ( index ) >= <NUM_LIT> && (

INTVAL ( index ) & <NUM_LIT> ) == <NUM_LIT> ) ;


<s> assert ( V1 . getSimpleValueType ( ) == <STR_LIT> && <STR_LIT> ) ; assert ( V2 . getSimpleValueType ( ) == <STR_LIT> && <STR_LIT> ) ; ShuffleVectorSDNode * SVOp = cast < ShuffleVectorSDNode > ( Op ) ; ArrayRef < int > Mask = SVOp -> getMask ( ) ; assert ( Mask . size ( ) == <NUM_LIT> && <STR_LIT> ) ; int NumV2Elements = std :: count_if ( Mask . begin ( ) , Mask . end ( ) , [ ] ( int M ) { return M >= <NUM_LIT> ; } ) ; if ( NumV2Elements == <NUM_LIT> ) { const int UnpackLoMask [ ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; const int UnpackHiMask [ ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; if ( isShuffleEquivalent ( Mask , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> ) ) Mask = UnpackLoMask ; else if ( isShuffleEquivalent ( Mask , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> ) ) Mask = UnpackHiMask ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1

, getV4<ISA_LIT>ShuffleImm8ForMask ( Mask , DAG ) ) ;


<s> OS << StringRef ( getRegisterName ( RegNo ) )


<s> MCRegister Res = get<ISA_LIT>SubSuperRegisterOrZero ( Reg , Size , High ) ; assert ( Res != <STR_LIT> && <STR_LIT> ) ; return Res


<s> forwardITPosition ( ) ; forwardVPTPosition ( ) ; return true ; } { while ( processInstruction ( Inst , Operands , Out ) ) LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; Inst . dump_pretty ( dbgs ( ) , MII . getName ( Inst . getOpcode ( ) ) ) ; dbgs ( ) << <STR_LIT> ) ; } forwardITPosition ( ) ; forwardVPTPosition ( ) ; if ( Inst . getOpcode ( ) == <STR_LIT> ) return false ; Inst . setLoc ( IDLoc ) ; if ( PendConditionalInstruction ) { PendingConditionalInsts . push_back ( Inst ) ; if ( isITBlockFull ( ) || isITBlockTerminator ( Inst ) )


<s> fixed_regs [ MEM0_REGNO + i ] = <NUM_LIT> ; CLEAR_HARD_REG_BIT ( reg_class_contents [ MEM_REGS ] , MEM0_REGNO + i ) ; } } if ( TARGET_A24 ) { call_used_regs [ R1_REGNO ] = <NUM_LIT> ; call_used_regs [ R2_REGNO ] = <NUM_LIT>


<s> int Offset = MF . getFrameInfo ( ) . getObjectOffset ( FrameIndex ) + MI . getOperand ( FIOperandNum + <NUM_LIT> ) . getImm ( ) ; MI . getOperand ( FIOperandNum ) . ChangeToRegister ( <STR_LIT> , false


<s> else for ( i = <NUM_LIT> ; i < count ; i ++ ) emit_move_insn ( gen_rtx_REG ( mode , rdest + count - i - <NUM_LIT> )

, gen_rtx_REG ( mode , rsrc + count - i - <NUM_LIT> ) ) ;


<s> for ( unsigned i = <NUM_LIT> ; i != NumElts ; i += <NUM_LIT> ) { if ( ( unsigned ) M [ i ] != Idx || ( unsigned ) M [ i + <NUM_LIT> ] != Idx + NumElts ) return false ; Idx += <NUM_LIT> ; } if ( VT . is64BitVector ( ) && VT . getVectorElementType ( )

. getSizeInBits ( ) == <NUM_LIT> ) return false ;


<s> if ( ! DisableInstrFormPrep && getOptLevel ( ) != CodeGenOpt :: None ) addPass ( create<ISA_LIT>LoopInstrFormPrepPass ( get<ISA_LIT>TargetMachine ( ) ) ) ; if ( ! DisableCTRLoops && getOptLevel ( ) != CodeGenOpt :: None ) addPass ( createHardwareLoopsPass


<s> for ( const auto & I : NewPreds ) { unsigned P = I ; if ( ! Defs . count ( P ) || LatePreds . count ( P ) ) { reportErrorNewValue ( P ) ; return false ; } } for ( const auto & I : LatePreds ) { unsigned P = I ; if ( LatePreds . count ( P ) > <NUM_LIT> || Defs . count ( P


<s> <ISA_LIT>MCInstLower MCInstLowering ( OutContext , STI , * this ) ; return MCInstLowering . lowerOperand ( MO , MCOp


<s> uint16_t getType ( ) const { return NodeAttrs :: type (


<s> if ( ! isa < IntrinsicInst > ( EV -> getAggregateOperand ( ) ) ) return false ; const auto * II = cast < IntrinsicInst > ( EV -> getAggregateOperand ( ) ) ; MVT RetVT ; const Function * Callee = II -> getCalledFunction ( ) ; Type * RetTy = cast < StructType > ( Callee -> getReturnType ( ) ) -> getTypeAtIndex ( <NUM_LIT> ) ; if ( ! isTypeLegal ( RetTy , RetVT ) ) return false ; if ( RetVT != <STR_LIT> && RetVT != <STR_LIT> ) return false ; <STR_LIT> TmpCC ; switch ( II -> getIntrinsicID ( ) ) { default : return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : TmpCC = <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : TmpCC = <STR_LIT> ; break ; } if ( II -> getParent ( ) != I -> getParent ( ) ) return false ; BasicBlock :: const_iterator Start ( I ) ; BasicBlock :: const_iterator End ( II ) ; for ( auto Itr = std :: prev ( Start ) ; Itr != End ; -- Itr ) { if ( ! isa < ExtractValueInst > ( Itr ) ) return false ; const auto * EVI = cast < ExtractValueInst


<s> setFeatures ( * NewF , NewFeatures ) ; if ( F . hasName ( ) ) { std :: string NewName = std :: string ( NewF -> getName ( ) ) ; NewF -> takeName ( & F ) ; F . setName


<s> void addVectorPred ( MCInst & Inst , unsigned N ) const { llvm_unreachable ( <STR_LIT>


<s> MCInst I ; if ( Opcode == <STR_LIT> ) { unsigned Temp = Reg1 ; Reg1 = Reg2 ; Reg2 = Temp ; } I . setOpcode ( Opcode


<s> if ( regs_available_for_popping == <NUM_LIT> && reg_containing_return_addr == LAST_ARG_REGNUM ) { asm_fprintf ( f , <STR_LIT> , LR_REGNUM , LAST_ARG_REGNUM ) ; reg_containing_return_addr = LR_REGNUM ; } else if ( size > <NUM_LIT> ) { restore_a4 = TRUE ; asm_fprintf ( f , <STR_LIT> , IP_REGNUM , LAST_ARG_REGNUM ) ; } if ( reg_containing_return_addr != LAST_ARG_REGNUM ) { regs_available_for_popping |= <NUM_LIT> << LAST_ARG_REGNUM ; -- pops_needed ; } } thumb_pushpop ( f , regs_available_for_popping , FALSE , NULL , regs_available_for_popping ) ; if ( reg_containing_return_addr == - <NUM_LIT> ) { regs_to_pop &= ~ ( <NUM_LIT> << LR_REGNUM ) ; reg_containing_return_addr = number_of_first_bit_set ( regs_available_for_popping ) ; regs_available_for_popping &= ~ ( <NUM_LIT> << reg_containing_return_addr ) ; } if ( regs_available_for_popping ) { int frame_pointer ; frame_pointer = number_of_first_bit_set ( regs_available_for_popping ) ; asm_fprintf ( f , <STR_LIT> , ARM_HARD_FRAME_POINTER_REGNUM , frame_pointer ) ; regs_available_for_popping &= ~ ( <NUM_LIT> << frame_pointer ) ; regs_to_pop &= ~ ( <NUM_LIT> << ARM_HARD_FRAME_POINTER_REGNUM ) ; if ( regs_available_for_popping ) { int stack_pointer ; stack_pointer = number_of_first_bit_set ( regs_available_for_popping ) ; asm_fprintf ( f , <STR_LIT> , SP_REGNUM , stack_pointer ) ; } else { regs_available_for_popping |= ( <NUM_LIT> << frame_pointer ) ; } } if ( regs_available_for_popping == <NUM_LIT> && pops_needed > <NUM_LIT> ) { regs_available_for_popping |= <NUM_LIT> << reg_containing_return_addr ; asm_fprintf ( f , <STR_LIT> , LR_REGNUM , reg_containing_return_addr ) ; reg_containing_return_addr = LR_REGNUM ; } if ( pops_needed > <NUM_LIT> ) { int popped_into ; int move_to ; thumb_pushpop ( f , regs_available_for_popping , FALSE , NULL , regs_available_for_popping ) ; popped_into = number_of_first_bit_set


<s> case <STR_LIT> : return select < <STR_LIT> > ( N ) ; case <STR_LIT> : return select < <STR_LIT> > ( N ) ; case <STR_LIT> : case <STR_LIT> : return selectMultiplication ( N ) ; case <STR_LIT> : return select < <STR_LIT> > ( N ) ; case


<s> static SDValue PerformSUBECombine ( SDNode * N , SelectionDAG & DAG , TargetLowering :: DAGCombinerInfo & DCI , const <ISA_LIT>Subtarget * Subtarget ) { if ( DCI . isBeforeLegalize ( ) ) return SDValue ( ) ; if ( Subtarget -> is<ISA_LIT>32 ( ) && SelectMsub ( N , & DAG


<s> static void doMaskedAtomicBinOpExpansion ( const <ISA_LIT>InstrInfo * TII , MachineInstr & MI , DebugLoc DL , MachineBasicBlock * ThisMBB , MachineBasicBlock * LoopMBB , MachineBasicBlock * DoneMBB , AtomicRMWInst :: BinOp BinOp , int Width ) { assert ( Width == <NUM_LIT> && <STR_LIT> ) ; unsigned DestReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned ScratchReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned AddrReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned IncrReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned MaskReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; AtomicOrdering Ordering = static_cast < AtomicOrdering > ( MI . getOperand


<s> return DAG . getNode ( <STR_LIT> + ShiftOffset / <NUM_LIT> , SL , <STR_LIT> , Shift ) ; } } } const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; APInt DemandedBits = APInt :: getBitsSet ( <NUM_LIT> , <NUM_LIT> * Offset , <NUM_LIT> * Offset + <NUM_LIT> ) ; if ( TLI . SimplifyDemandedBits ( Src , DemandedBits , DCI ) ) return SDValue ( N , <NUM_LIT> ) ; if ( SDValue DemandedSrc = TLI . SimplifyMultipleUseDemandedBits ( Src , DemandedBits , DAG ) ) return DAG .

getNode ( N -> getOpcode ( ) , SL , <STR_LIT> , DemandedSrc ) ;


<s> MachineInstr * FoldCmp = tryFoldIntegerCompare ( LHS , RHS , Predicate , MIRBuilder ) ; if ( FoldCmp ) return { FoldCmp , ( CmpInst :: Predicate ) Predicate . getPredicate ( ) } ; unsigned CmpOpc = <NUM_LIT> ; Register ZReg ; LLT CmpTy = MRI . getType ( LHS . getReg ( ) ) ; assert ( ( CmpTy . isScalar ( ) || CmpTy . isPointer ( ) ) && <STR_LIT> ) ; if ( CmpTy == LLT :: scalar ( <NUM_LIT> ) ) { CmpOpc = <STR_LIT> ; ZReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; } else if ( CmpTy == LLT :: scalar ( <NUM_LIT> ) || CmpTy . isPointer ( ) ) { CmpOpc = <STR_LIT> ; ZReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; } else { return { nullptr , CmpInst :: Predicate :: BAD_ICMP_PREDICATE } ; } MachineInstr * ImmedCmp = tryOptArithImmedIntegerCompare ( LHS , RHS , Predicate , MIRBuilder ) ; if ( ImmedCmp ) return { ImmedCmp , ( CmpInst :: Predicate ) Predicate . getPredicate ( ) } ; MachineInstr * ShiftedCmp = tryOptArithShiftedCompare ( LHS , RHS , MIRBuilder ) ; if ( ShiftedCmp ) return { ShiftedCmp , ( CmpInst :: Predicate ) Predicate . getPredicate ( ) } ; auto CmpMI = MIRBuilder . buildInstr ( CmpOpc , { ZReg } , { LHS . getReg ( ) , RHS . getReg ( ) } ) ; constrainSelectedInstRegOperands ( * CmpMI , TII , TRI , RBI ) ; return { & * CmpMI , ( CmpInst :: Predicate )


<s> if ( BranchRelaxation ) addPass ( & BranchRelaxationPassID ) ; if ( TM -> getTargetTriple ( ) . isOSWindows ( ) ) addPass ( createCFGuardLongjmpPass ( ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableCompressJumpTables ) addPass ( create<ISA_LIT>CompressJumpTablesPass ( ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableCollectLOH && TM -> getTargetTriple ( ) . isOSBinFormatMachO ( ) ) addPass ( create<ISA_LIT>CollectLOHPass ( ) ) ; addPass ( createUnpackMachineBundles (


<s> raw_svector_ostream O ( Str ) ; const TargetRegisterInfo * TRI = MF . getTarget ( ) . getRegisterInfo ( ) ; const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; int NumBytes = ( int ) MFI -> getStackSize ( ) ; if ( NumBytes ) { O << <STR_LIT> << MFI -> getMaxAlignment ( ) << <STR_LIT> << DEPOTNAME << getFunctionNumber ( ) << <STR_LIT> << NumBytes << <STR_LIT> ; if ( nvptxSubtarget . is64Bit ( ) ) { O << <STR_LIT> ; O << <STR_LIT> ; } else { O << <STR_LIT> ; O << <STR_LIT> ; } } unsigned int numVRs = MRI -> getNumVirtRegs ( ) ; for ( unsigned i = <NUM_LIT> ; i < numVRs ; i ++ ) { unsigned int vr = TRI -> index2VirtReg ( i ) ; const TargetRegisterClass * RC = MRI -> getRegClass ( vr ) ; DenseMap < unsigned , unsigned > & regmap = VRegMapping [ RC ] ; int n = regmap . size ( ) ; regmap . insert ( std :: make_pair ( vr , n + <NUM_LIT>


<s> const MachineOperand & MO1 = MI -> getOperand ( OpNum ) ; int32_t OffImm = ( int32_t ) MO1 . getImm ( ) ; if ( OffImm < <NUM_LIT> ) O << <STR_LIT>


<s> basic_block bb = bbs [ i ] ; gimple_stmt_iterator gsi ; for ( gsi = gsi_start_bb ( bb ) ; ! gsi_end_p ( gsi ) ; gsi_next ( & gsi ) ) { gimple * stmt = gsi_stmt ( gsi ) ; stmt_vec_info stmt_info = loop_vinfo -> lookup_stmt ( stmt ) ; if ( ! STMT_VINFO_RELEVANT_P ( stmt_info ) && ! STMT_VINFO_IN_PATTERN_P ( stmt_info ) ) not_vec_cost ++ ; } } free ( bbs ) ; density_pct = ( vec_cost * <NUM_LIT> ) / (


<s> for ( unsigned oper = <NUM_LIT> ; oper < MI . getNumOperands ( ) ; ++ oper ) { MachineOperand MO = MI . getOperand ( oper ) ; if ( MO . isReg ( ) && MO . isDef ( ) ) { const TargetRegisterClass * RC = HRI . getMinimalPhysRegClass ( MO . getReg ( ) ) ; if ( RC == & <STR_LIT> ) { Pred . push_back ( MO ) ; return


<s> return ST -> isMClass ( ) && ST -> isThumb2 ( ) && L -> getNumBlocks (


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { MachineFunctionPass :: getAnalysisUsage ( AU


<s> Shift = true ; break ; } EVT VT = Op . getValueType ( ) ; SDValue One = DAG . getConstant ( <NUM_LIT> , VT ) ; if ( Convert ) { SDValue SR = DAG . getCopyFromReg ( DAG . getEntryNode ( ) , dl , <STR_LIT> , <STR_LIT> , Flag ) ; if ( Shift ) SR = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , SR , One ) ; SR = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , SR , One ) ; if ( Invert ) SR = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , SR , One ) ; return SR ; } else { SDValue Zero = DAG . getConstant ( <NUM_LIT> , VT ) ; SDVTList VTs = DAG . getVTList ( Op . getValueType (


<s> case <STR_LIT> : return ELF :: R_390_PC16DBL ; case <STR_LIT> : return ELF :: R_390_PC24DBL ; case <STR_LIT> : return ELF :: R_390_PC32DBL ; } llvm_unreachable ( <STR_LIT>


<s> if ( Subtarget . is<ISA_LIT>64 ( ) ) return DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; return DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; } int CompareOpc ; bool isDot ; if ( ! getVectorCompareInfo ( Op , CompareOpc , isDot , Subtarget ) ) return SDValue ( ) ; if ( ! isDot ) { SDValue Tmp = DAG . getNode ( <STR_LIT> , dl , Op . getOperand ( <NUM_LIT> ) . getValueType ( ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , DAG . getConstant ( CompareOpc , dl , <STR_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , dl , Op . getValueType ( ) , Tmp ) ; } SDValue Ops [ ] = { Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , DAG . getConstant ( CompareOpc , dl , <STR_LIT> ) } ; EVT VTs [ ] = { Op . getOperand ( <NUM_LIT> ) . getValueType ( ) , <STR_LIT> } ; SDValue CompNode = DAG . getNode ( <STR_LIT> , dl , VTs , Ops ) ; SDValue Flags = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getRegister ( <STR_LIT> , <STR_LIT> ) , CompNode . getValue ( <NUM_LIT> ) ) ; unsigned BitNo ; bool InvertBit ; switch ( cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ) { default : case <NUM_LIT> : BitNo = <NUM_LIT> ; InvertBit = false ; break ; case <NUM_LIT> : BitNo = <NUM_LIT> ; InvertBit = true ; break ; case <NUM_LIT> : BitNo = <NUM_LIT> ; InvertBit =


<s> unsigned Register = PPRDecoderTable [ RegNo ] ; Inst . addOperand ( MCOperand :: createReg ( Register ) ) ; return Success


<s> } else if ( ACC_REG_P ( regno ) ) { first = <NUM_LIT> ; regno = <NUM_LIT> ; } if ( first == - <NUM_LIT> ) return <NUM_LIT> ; return first +


<s> bool <ISA_LIT>TTIImpl :: isLegalMaskedExpandLoad ( Type * DataTy ) { if ( ! isa < VectorType > ( DataTy ) ) return false ; if ( ! ST -> hasAVX512 ( ) ) return false ; if ( DataTy -> getVectorNumElements ( ) == <NUM_LIT> ) return false ; Type * ScalarTy = DataTy -> getVectorElementType ( ) ; if ( ScalarTy -> isFloatTy ( ) || ScalarTy -> isDoubleTy ( ) ) return true ; if ( ! ScalarTy -> isIntegerTy ( ) ) return false ; unsigned IntWidth = ScalarTy -> getIntegerBitWidth ( ) ; return IntWidth == <NUM_LIT> || IntWidth == <NUM_LIT> || ( ( IntWidth == <NUM_LIT> || IntWidth == <NUM_LIT>


<s> if ( ! ( LM & <NUM_LIT> ) && ( Mask & VGPR_BANK_MASK ) ) { unsigned Shift = countTrailingZeros ( LM ) ; if ( Shift >= NUM_VGPR_BANKS ) return <NUM_LIT> ; unsigned VB = FreeBanks & VGPR_BANK_MASK ; FreeBanks = ( ( VB >> Shift ) | ( VB << ( NUM_VGPR_BANKS - Shift ) ) ) & VGPR_BANK_MASK ; } else if ( ! ( LM & <NUM_LIT> ) && ( Mask & SGPR_BANK_MASK ) ) { unsigned Shift = countTrailingZeros ( LM ) >> <NUM_LIT> ; if ( Shift >= NUM_SGPR_BANKS ) return <NUM_LIT> ; unsigned SB = FreeBanks >> SGPR_BANK_OFFSET ; FreeBanks = ( ( SB >> Shift ) | ( SB << ( NUM_SGPR_BANKS - Shift ) ) ) & SGPR_BANK_SHIFTED_MASK ; FreeBanks <<= SGPR_BANK_OFFSET ; } LLVM_DEBUG ( if ( FreeBanks ) { dbgs ( ) << <STR_LIT> << printReg ( Reg , SubReg ) << <STR_LIT>


<s> const Register DestRegs [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> } ; bool UsedMask [ ] = { false , false , false } ; Register SrcRegs [ ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; for ( unsigned I = <NUM_LIT> ; I < MI . getNumOperands ( ) ; ++ I ) if ( auto Op = MCIL . LowerMachineOperand ( & MI , MI . getOperand ( I ) ) ) { assert ( Op -> isReg ( ) && <STR_LIT> ) ; SrcRegs [ I ] = get<ISA_LIT>SubSuperRegister ( Op -> getReg ( ) , <NUM_LIT> ) ; if ( SrcRegs [ I ] != DestRegs [ I ] ) { UsedMask [ I ] = true ; EmitAndCountInstruction ( MCInstBuilder ( <STR_LIT> ) . addReg ( DestRegs [ I ] ) ) ; } else { EmitNops ( * OutStreamer , <NUM_LIT> , Subtarget -> is64Bit ( ) , getSubtargetInfo ( ) ) ; } } for ( unsigned I = <NUM_LIT> ; I < MI . getNumOperands ( ) ; ++ I ) if ( UsedMask [ I ] ) EmitAndCountInstruction ( MCInstBuilder ( <STR_LIT> ) . addReg ( DestRegs [ I ] ) . addReg ( SrcRegs [ I ] ) ) ; auto TSym = OutContext .


<s> return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : return - <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : { uint64_t D = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned Lo = D & <NUM_LIT> ; unsigned Hi = D >> <NUM_LIT> ; return profitImm ( Lo , Hi ) ; } case <STR_LIT> : case <STR_LIT> : return profitImm ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) , MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; case <STR_LIT> : ImmX ++ ; case <STR_LIT> : { ImmX ++ ; int64_t V = MI -> getOperand ( ImmX ) . getImm ( ) ; if ( V == <NUM_LIT> || V == - <NUM_LIT> ) return <NUM_LIT> ; } case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT>


<s> Inst . addOperand ( MCOperand :: createImm ( MovDualGroup


<s> while ( i != <NUM_LIT> ) { unsigned LastReg = <NUM_LIT> ; for ( ; i != <NUM_LIT> ; -- i ) { unsigned Reg = CSI [ i - <NUM_LIT> ] . getReg ( ) ; if ( ! ( Func ) ( Reg , STI . isTargetMachO ( ) ) ) continue ; if ( Reg >= <STR_LIT> && Reg < <STR_LIT> + NumAlignedDPRCS2Regs ) continue ; bool isKill = true ; if ( Reg == <STR_LIT> ) { if ( MF . getFrameInfo ( ) -> isReturnAddressTaken ( ) && MF . getRegInfo ( ) . isLiveIn ( Reg ) ) isKill = false ; } if ( isKill ) MBB . addLiveIn ( Reg ) ; if ( NoGap && LastReg && LastReg != Reg - <NUM_LIT> ) break ; LastReg = Reg ; Regs . push_back ( std :: make_pair ( Reg , isKill ) ) ; } if ( Regs . empty ( ) ) continue ; if ( Regs . size ( )


<s> const MachineOperand * LaneSelectOp = TII -> getNamedOperand ( * RWLane , <STR_LIT> :: src1 ) ; if ( ! LaneSelectOp -> isReg ( ) || ! TRI -> isSGPRReg ( MRI , LaneSelectOp -> getReg ( ) ) ) return <NUM_LIT> ; unsigned LaneSelectReg = LaneSelectOp -> getReg ( ) ; auto IsHazardFn = [ TII ] ( MachineInstr * MI ) { return TII -> isVALU ( * MI ) ; } ; const int RWLaneWaitStates


<s> struct riscv_arg_info info ; CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; if ( cum != NULL ) { riscv_get_arg_info ( & info , cum , mode , type , named


<s> const Function & F = * MF . getFunction ( ) ; SmallVector < CCValAssign , <NUM_LIT> > ArgLocs ; CCState CCInfo ( F . getCallingConv ( ) , F . isVarArg ( ) , MF , ArgLocs , F . getContext ( ) ) ; unsigned NumArgs = Args . size ( ) ; Function :: const_arg_iterator CurOrigArg = Args . begin ( ) ; const <ISA_LIT>TargetLowering & TLI = * getTLI < <ISA_LIT>TargetLowering > ( ) ; for ( unsigned i = <NUM_LIT> ; i != NumArgs ; ++ i , ++ CurOrigArg ) { MVT ValVT = <STR_LIT> ( CurOrigArg -> getType ( ) ) ; CCAssignFn * AssignFn = TLI . CCAssignFnForCall ( F . getCallingConv ( ) , false ) ; bool Res = AssignFn ( i , ValVT , ValVT , CCValAssign :: Full , <STR_LIT> ( ) , CCInfo ) ; assert ( ! Res


<s> AssemblerDialect = AsmWriterFlavor ; GlobalPrefix = <STR_LIT> ; CommentString = <STR_LIT> ; PrivateGlobalPrefix = <STR_LIT> ; AlignDirective = <STR_LIT> ; ZeroDirective = <STR_LIT> ; ZeroDirectiveSuffix = <STR_LIT> ; AsciiDirective = <STR_LIT> ; AscizDirective = <NUM_LIT> ; Data8bitsDirective =


<s> if ( ! const_vector_equal_evenodd_p ( orig_op1 ) ) op1 = expand_binop ( wmode , lshr_optab , gen_lowpart ( wmode , op1 ) , x , NULL , <NUM_LIT> , OPTAB_DIRECT ) ; if ( ! const_vector_equal_evenodd_p ( orig_op2 ) ) op2 = expand_binop ( wmode , lshr_optab , gen_lowpart ( wmode , op2 ) , x , NULL , <NUM_LIT> , OPTAB_DIRECT ) ; op1 = gen_lowpart ( mode , op1 ) ; op2 = gen_lowpart ( mode , op2 ) ; } if ( mode == V16SImode ) { if ( uns_p ) x = gen_vec_widen_umult_even_v16si ( dest , op1 , op2 ) ; else x = gen_vec_widen_smult_even_v16si ( dest , op1 , op2 ) ; } else if ( mode == V8SImode ) { if ( uns_p ) x = gen_vec_widen_umult_even_v8si ( dest , op1 , op2 ) ; else x = gen_vec_widen_smult_even_v8si ( dest , op1 , op2 ) ; } else if ( uns_p ) x = gen_vec_widen_umult_even_v4si ( dest , op1 , op2 ) ; else if ( TARGET_SSE4_1 ) x = gen_sse4_1_mulv2siv2di3 ( dest , op1 , op2 ) ; else { rtx s1 , s2 , t0 , t1 , t2 ; s1 = ix86_expand_sse_cmp ( gen_reg_rtx ( mode ) , GT , CONST0_RTX


<s> if ( ! CONST_INT_P ( arg ) || ! IN_RANGE ( INTVAL ( arg )


<s> unsigned FrameReg = is<ISA_LIT>64 ? ( is31 ? <STR_LIT> : <STR_LIT> ) : ( is31 ? <STR_LIT> : <STR_LIT> ) ; SDValue FrameAddr = DAG . getCopyFromReg ( DAG . getEntryNode ( ) , dl , FrameReg , PtrVT ) ; while ( Depth -- ) FrameAddr = DAG . getLoad ( Op . getValueType ( ) , dl , DAG . getEntryNode ( ) , FrameAddr , MachinePointerInfo ( ) , false , false , false , <NUM_LIT> ) ; return


<s> return create<ISA_LIT>WasmObjectWriter ( OS , Is64Bit


<s> SDValue Result = DAG . getTargetConstantPool ( CP -> getConstVal ( ) , PtrVT , CP -> getAlignment ( ) , CP -> getOffset ( ) , OpFlag ) ; SDLoc DL ( CP ) ; Result = DAG . getNode ( getGlobalWrapperKind ( ) , DL , PtrVT , Result ) ; if (


<s> if ( CPV -> getNumOperands ( ) ) { StructType * ST = cast < StructType > ( CPV -> getType ( ) ) ; for ( unsigned i = <NUM_LIT> , e = CPV -> getNumOperands ( ) ; i != e ; ++ i ) { if ( i == ( e - <NUM_LIT> ) ) Bytes = TD -> getStructLayout ( ST ) -> getElementOffset ( <NUM_LIT> ) + TD -> getTypeAllocSize ( ST ) - TD -> getStructLayout ( ST ) -> getElementOffset ( i ) ; else Bytes = TD -> getStructLayout ( ST ) -> getElementOffset ( i + <NUM_LIT> ) - TD -> getStructLayout ( ST ) -> getElementOffset ( i ) ; bufferLEByte ( cast < Constant > ( CPV -> getOperand ( i ) ) , Bytes , aggBuffer ) ; } } return ; } llvm_unreachable ( <STR_LIT> )


<s> assert ( getParser ( ) . getStreamer (

) . getTargetStreamer ( ) && <STR_LIT> ) ;


<s> if ( TARGET_HITACHI ) return false ; if ( ! type ) return true ; return ! sh_attr_renesas_p ( type


<s> if ( ! isa < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) . getNode ( ) ) ) llvm_unreachable ( <STR_LIT> ) ; uint64_t Index = cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) . getNode ( ) ) -> getZExtValue ( ) ; EVT VecVT = N -> getValueType ( <NUM_LIT> ) ; EVT ElVT = VecVT . getVectorElementType


<s> } if ( TM -> Options . ExceptionModel == ExceptionHandling :: SjLj ) { for ( MachineBasicBlock :: iterator I = MBB . begin ( ) ; I != MBB . end ( ) ; ++ I ) { if ( MBB . isEHPad ( ) ) { if ( I -> isDebugInstr ( ) ) continue ; Changed |= addENDBR ( MBB , I ) ; break ; } else if ( I -> isEHLabel ( ) ) { MCSymbol * Sym = I -> getOperand ( <NUM_LIT> ) . getMCSymbol ( ) ; if ( ! MF . hasCallSiteLandingPad ( Sym ) ) continue ; Changed |= addENDBR ( MBB , std :: next ( I ) ) ; break ; } } } else if ( MBB . isEHPad ( ) ) { for ( MachineBasicBlock :: iterator I = MBB . begin ( ) ; I != MBB . end ( ) ;


<s> if ( Fits ) { if ( isSub ) { BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , DestReg ) . addReg ( BaseReg , RegState :: Kill ) . addReg ( DestReg , RegState :: Kill ) . addImm ( ( unsigned ) Pred ) . addReg ( PredReg ) . addReg ( <NUM_LIT> ) ; } else { BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , DestReg ) . addReg ( DestReg , RegState :: Kill ) . addReg ( BaseReg , RegState :: Kill ) . addImm ( ( unsigned ) Pred ) . addReg ( PredReg ) . addReg ( <NUM_LIT> ) ; } return ; } } while ( NumBytes ) { unsigned ThisVal = NumBytes ; unsigned Opc = <NUM_LIT> ; if ( DestReg == <STR_LIT> && BaseReg != <STR_LIT> ) { BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , DestReg ) . addReg ( BaseReg ) ; BaseReg = <STR_LIT> ; continue ; } bool HasCCOut = true ; if ( BaseReg == <STR_LIT> ) { if ( DestReg == <STR_LIT> && ( ThisVal < ( ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) * <NUM_LIT> ) ) { assert ( ( ThisVal & <NUM_LIT> ) == <NUM_LIT> && <STR_LIT> ) ; Opc = isSub ? <STR_LIT> : <STR_LIT> ; BuildMI ( MBB , MBBI , dl , TII . get ( Opc ) , DestReg ) . addReg ( BaseReg ) . addImm ( ThisVal / <NUM_LIT> ) ; NumBytes = <NUM_LIT> ; continue ; } Opc = isSub ? <STR_LIT> : <STR_LIT> ; if ( <STR_LIT> ( NumBytes ) != - <NUM_LIT> ) { NumBytes = <NUM_LIT> ; } else { unsigned RotAmt = CountLeadingZeros_32 ( ThisVal ) ; ThisVal = ThisVal & <STR_LIT> ( <NUM_LIT> , RotAmt ) ; NumBytes &= ~ ThisVal ; assert ( <STR_LIT> ( ThisVal ) != - <NUM_LIT> && <STR_LIT> ) ; } } else { assert ( DestReg != <STR_LIT> && BaseReg != <STR_LIT> ) ; Opc = isSub ? <STR_LIT> : <STR_LIT> ; if ( <STR_LIT> ( NumBytes ) != - <NUM_LIT> ) { NumBytes = <NUM_LIT> ; } else if ( ThisVal < <NUM_LIT> ) { Opc = isSub ? <STR_LIT> : <STR_LIT> ; HasCCOut = false ; NumBytes = <NUM_LIT> ; } else { unsigned RotAmt = CountLeadingZeros_32 ( ThisVal ) ; ThisVal = ThisVal & <STR_LIT> ( <NUM_LIT> , RotAmt ) ; NumBytes &= ~ ThisVal ; assert ( <STR_LIT> ( ThisVal ) != - <NUM_LIT> &&


<s> OffsetIsReg = ! MaybeParseRegister ( Op , false ) ; if ( OffsetIsReg ) OffsetRegNum = Op . getReg ( ) ; } if ( OffsetRegNum != - <NUM_LIT> ) { const AsmToken & Tok = Parser . getTok ( ) ; if ( Tok . is ( AsmToken :: Comma ) ) { Parser . Lex ( ) ; const AsmToken & Tok = Parser . getTok ( ) ; if ( ParseShift ( ShiftType , ShiftAmount ) ) return Error ( Tok . getLoc ( ) , <STR_LIT> ) ; OffsetRegShifted = true ; } } else { const AsmToken & HashTok = Parser . getTok ( ) ; if ( HashTok . isNot ( AsmToken :: Hash ) ) return Error ( HashTok . getLoc ( ) , <STR_LIT> ) ; Parser . Lex ( ) ; if ( getParser ( ) . ParseExpression ( Offset ) ) return true ; } return


<s> SDValue Extract = Cast . getOperand ( <NUM_LIT> ) ; MVT DestVT = Cast . getSimpleValueType ( ) ; if ( Extract . getOpcode ( ) != <STR_LIT> || ! isa < ConstantSDNode > ( Extract . getOperand ( <NUM_LIT> ) ) ) return SDValue ( ) ; SDValue VecOp = Extract . getOperand ( <NUM_LIT> ) ; MVT FromVT = VecOp . getSimpleValueType ( ) ; unsigned NumEltsInXMM = <NUM_LIT> / FromVT . getScalarSizeInBits ( ) ; MVT Vec128VT = <STR_LIT> ( FromVT . getScalarType ( ) , NumEltsInXMM ) ; MVT ToVT = <STR_LIT> ( DestVT , NumEltsInXMM ) ; if ( ! useVectorCast ( Cast . getOpcode ( ) , Vec128VT , ToVT , Subtarget ) ) return SDValue ( ) ; SDLoc DL ( Cast ) ; if ( ! isNullConstant ( Extract . getOperand (


<s> setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; if ( HWMultMode == HWMultIntr ) { setLibcallName ( RTLIB :: MUL_I8 , <STR_LIT> ) ; setLibcallName ( RTLIB :: MUL_I16 , <STR_LIT> ) ; } else if ( HWMultMode == HWMultNoIntr ) { setLibcallName ( RTLIB :: MUL_I8 , <STR_LIT> ) ; setLibcallName ( RTLIB :: MUL_I16


<s> oldval = operands [ <NUM_LIT> ] ; newval = operands [ <NUM_LIT> ] ; is_weak = ( operands [ <NUM_LIT> ] != const0_rtx ) ; model_rtx = operands [ <NUM_LIT> ] ; scratch = operands [ <NUM_LIT> ] ; mode = GET_MODE ( mem ) ; model = memmodel_from_int ( INTVAL ( model_rtx ) ) ; bool strong_zero_p = ! is_weak && oldval == const0_rtx ; label1 = NULL ; if ( ! is_weak ) { label1 = gen_label_rtx ( ) ; emit_label ( label1 ) ; } label2 = gen_label_rtx ( ) ; if ( is_mm_sync ( model ) ) aarch64_emit_load_exclusive ( mode , rval , mem , GEN_INT ( MEMMODEL_RELAXED ) ) ; else aarch64_emit_load_exclusive ( mode , rval , mem , model_rtx ) ; if ( strong_zero_p ) { if ( aarch64_track_speculation ) { rtx cc_reg = aarch64_gen_compare_reg ( NE , rval , const0_rtx ) ; x = gen_rtx_NE ( GET_MODE ( cc_reg ) , cc_reg , const0_rtx ) ; } else x = gen_rtx_NE ( VOIDmode , rval , const0_rtx ) ; x = gen_rtx_IF_THEN_ELSE ( VOIDmode , x , gen_rtx_LABEL_REF ( Pmode , label2 ) , pc_rtx ) ; aarch64_emit_unlikely_jump ( gen_rtx_SET ( pc_rtx , x ) ) ; } else { cond = aarch64_gen_compare_reg_maybe_ze ( NE , rval , oldval , mode ) ; x = gen_rtx_NE ( VOIDmode , cond , const0_rtx ) ; x = gen_rtx_IF_THEN_ELSE ( VOIDmode , x , gen_rtx_LABEL_REF ( Pmode , label2 ) , pc_rtx ) ; aarch64_emit_unlikely_jump ( gen_rtx_SET ( pc_rtx , x ) ) ; } aarch64_emit_store_exclusive ( mode , scratch , mem , newval , model_rtx ) ; if ( ! is_weak ) { if ( aarch64_track_speculation ) { rtx cc_reg = aarch64_gen_compare_reg ( NE , scratch , const0_rtx ) ; x = gen_rtx_NE ( GET_MODE ( cc_reg ) , cc_reg , const0_rtx ) ; } else x = gen_rtx_NE ( VOIDmode , scratch , const0_rtx ) ; x = gen_rtx_IF_THEN_ELSE ( VOIDmode , x , gen_rtx_LABEL_REF ( Pmode , label1 ) , pc_rtx ) ; aarch64_emit_unlikely_jump ( gen_rtx_SET ( pc_rtx , x


<s> switch ( c ) { case 'G' : return ( GET_MODE_CLASS ( GET_MODE ( value ) ) == MODE_FLOAT && value == CONST0_RTX ( GET_MODE ( value ) ) ) ; case 'H' : return ( GET_MODE ( value ) == VOIDmode && zap_mask ( CONST_DOUBLE_LOW ( value ) ) && zap_mask ( CONST_DOUBLE_HIGH ( value ) ) ) ; default : return false


<s> FIRST_EXTENDED_REGNUM + <NUM_LIT> , FIRST_EXTENDED_REGNUM + <NUM_LIT> , FIRST_EXTENDED_REGNUM + <NUM_LIT> , FIRST_EXTENDED_REGNUM + <NUM_LIT> , FIRST_DATA_REGNUM + <NUM_LIT> , FIRST_DATA_REGNUM + <NUM_LIT> , FIRST_ADDRESS_REGNUM + <NUM_LIT> , FIRST_ADDRESS_REGNUM + <NUM_LIT> , } ; rtx x , elts [ <NUM_LIT> ] ; unsigned int i ; int count ; if ( mask == <NUM_LIT> ) return ; for ( i = count = <NUM_LIT> ; i < ARRAY_SIZE ( store_order ) ; ++ i ) { unsigned regno = store_order [ i ] ; if ( ( ( mask >> regno ) & <NUM_LIT> ) == <NUM_LIT> ) continue ; ++ count ; x = plus_constant ( Pmode , stack_pointer_rtx , count * - <NUM_LIT> ) ; x = gen_frame_mem ( SImode , x ) ; x = gen_rtx_SET ( VOIDmode , x , gen_rtx_REG ( SImode , regno ) ) ; elts [ count ] = F ( x ) ; mask &= ~ ( <NUM_LIT> << regno ) ; } gcc_assert ( mask == <NUM_LIT> ) ; x = plus_constant ( Pmode , stack_pointer_rtx , count * - <NUM_LIT>


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : unsigned Width ; return getMemOperandWithOffsetWidth ( LdSt , BaseOp ,


<s> TII = ST . getInstrInfo ( ) ; TRI = & TII -> getRegisterInfo ( ) ; MRI = & MF . getRegInfo ( ) ; DomTree = & getAnalysis < MachineDominatorTree > ( ) ; LoopInfo = & getAnalysis < MachineLoopInfo > ( ) ; for ( MachineBasicBlock & MBB : MF ) { for ( MachineInstr & MI : MBB ) { if ( MI . getOpcode ( ) == <STR_LIT> ) WWMs . push_back ( & MI ) ; else { for ( MachineOperand & DefOpnd : MI . defs ( ) ) { if ( DefOpnd . isReg ( ) ) { unsigned Reg = DefOpnd . getReg ( ) ; if ( TRI -> isVGPR ( * MRI , Reg ) ) processDef ( DefOpnd ) ; } } } } } if ( ! WWMs . empty ( ) ) { for ( auto ThenDef : ThenDefs ) Modified |= processThenDef ( ThenDef ) ; for ( auto LoopExitDef : LoopExitDefs ) Modified |= processLoopExitDef ( LoopExitDef . first , LoopExitDef . second ) ; for ( auto LoopPhiDef : LoopPhiDefs ) Modified |= processLoopPhiDef ( LoopPhiDef . first , LoopPhiDef . second ) ; } WWMs . clear ( ) ; ThenDefs . clear


<s> auto Mapping = getValueMapping ( OpRegBankIdx [ Idx ] , <NUM_LIT> ) ; if ( ! Mapping -> isValid ( ) ) return false ; OpdsMapping [ Idx ] =


<s> bool ParseDirective ( AsmToken DirectiveID ) override { return true


<s> } else { SDValue Upper = getTargetVShiftByConstNode ( <STR_LIT> , dl , ExVT , Ex , ShiftAmt , DAG ) ; SDValue Lower = getTargetVShiftByConstNode ( <STR_LIT> , dl , VT , R , ShiftAmt , DAG ) ; Lower = DAG . getBitcast ( ExVT , Lower ) ; if ( VT == <STR_LIT> ) Ex = DAG . getVectorShuffle ( ExVT , dl , Upper , Lower , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ; if ( VT == <STR_LIT> ) Ex = DAG . getVectorShuffle ( ExVT , dl , Upper , Lower , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ; } return DAG . getBitcast ( VT , Ex ) ; } ; APInt APIntShiftAmt ; if ( ! isConstantSplat ( Amt , APIntShiftAmt ) ) return SDValue ( ) ; uint64_t ShiftAmt = APIntShiftAmt . getZExtValue ( ) ; if ( SupportedVectorShiftWithImm ( VT , Subtarget , Op . getOpcode ( ) ) ) return getTargetVShiftByConstNode ( <ISA_LIT>Opc , dl , VT , R , ShiftAmt , DAG ) ; if ( ( ( ! Subtarget . hasXOP ( ) && VT == <STR_LIT> ) || ( Subtarget . hasInt256 ( ) && VT == <STR_LIT> ) ) && Op . getOpcode ( ) == <STR_LIT> ) return ArithmeticShiftRight64 ( ShiftAmt ) ; if ( VT == <STR_LIT> || ( Subtarget . hasInt256 ( ) && VT == <STR_LIT> ) || VT == <STR_LIT> ) { unsigned NumElts = VT . getVectorNumElements ( ) ; MVT ShiftVT = <STR_LIT> ( <STR_LIT> , NumElts / <NUM_LIT> ) ; if ( Op . getOpcode ( ) == <STR_LIT> && ShiftAmt == <NUM_LIT> ) return DAG . getNode ( <STR_LIT> , dl , VT , R , R ) ; if ( Op . getOpcode ( ) == <STR_LIT> && ShiftAmt == <NUM_LIT> ) { SDValue Zeros = DAG . getConstant ( <NUM_LIT> , dl , VT ) ; if ( VT . is512BitVector ( ) ) { assert ( VT == <STR_LIT> && <STR_LIT> ) ; SDValue CMP = DAG . getSetCC ( dl , <STR_LIT> , Zeros , R , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , VT , CMP ) ; } return DAG . getNode ( <STR_LIT> , dl , VT , Zeros , R ) ; } if ( VT == <STR_LIT> && Subtarget . hasXOP ( ) ) return SDValue ( ) ; if ( Op . getOpcode ( ) == <STR_LIT> ) { SDValue SHL = getTargetVShiftByConstNode ( <STR_LIT> , dl , ShiftVT , R , ShiftAmt , DAG ) ; SHL = DAG . getBitcast ( VT , SHL


<s> void <ISA_LIT>TargetWinCOFFStreamer :: emitARM64WinCFIEpilogEnd ( ) { auto & S = getStreamer ( ) ; WinEH :: FrameInfo * CurFrame = S . EnsureValidWinFrameInfo ( SMLoc ( ) ) ; if ( ! CurFrame ) return ; InEpilogCFI = false ; MCSymbol * Label = S . emitCFILabel ( ) ; WinEH :: Instruction Inst = WinEH :: Instruction ( Win64EH

:: UOP_End , Label , - <NUM_LIT> , <NUM_LIT> ) ;


<s> if ( FuncInfo -> VGPRReservedForSGPRSpill && NumVGPRSpillLanes < WaveSize ) { assert ( FuncInfo -> VGPRReservedForSGPRSpill == SpillVGPRs . back ( ) . VGPR ) ; LaneVGPR = FuncInfo -> VGPRReservedForSGPRSpill ; } else if ( VGPRIndex == <NUM_LIT> ) { LaneVGPR = TRI -> findUnusedRegister ( MRI , & <STR_LIT> , MF ) ; if ( LaneVGPR == <STR_LIT> ) { SGPRToVGPRSpills . erase ( FI ) ; NumVGPRSpillLanes -= I ; return false ; } Optional < int > SpillFI ; if ( ! isEntryFunction ( ) ) { SpillFI = FrameInfo . CreateSpillStackObject ( <NUM_LIT> , Align ( <NUM_LIT> ) ) ; } SpillVGPRs . push_back ( SGPRSpillVGPR ( LaneVGPR , SpillFI ) ) ; for ( MachineBasicBlock & BB : MF ) BB . addLiveIn ( LaneVGPR ) ; } else { LaneVGPR = SpillVGPRs . back


<s> } case <STR_LIT> : { auto * PredMask = MRI -> getUniqueVRegDef ( Pred -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; if ( Mask != PredMask ) return false ; NewOp = <STR_LIT> ; OpChanged = true ; break ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { auto MaskOp = Mask -> getOpcode ( ) ; if ( ( MaskOp != <STR_LIT> && MaskOp != <STR_LIT> && MaskOp != <STR_LIT> && MaskOp != <STR_LIT> ) || ( Mask -> getOperand ( <NUM_LIT> ) . getImm ( ) != <NUM_LIT> ) ) return false ; break ; } default : return false ; } if ( Pred -> getParent ( ) != PTest -> getParent ( ) ) return false ; MachineBasicBlock :: iterator I = Pred , E = PTest ; ++ I ; for ( ; I != E ; ++ I ) { const MachineInstr & Inst = * I ; if ( Inst . modifiesRegister ( <STR_LIT> , TRI ) ) return false ; } Pred -> setDesc ( TII -> get ( NewOp ) ) ; PTest -> eraseFromParent ( ) ; if ( OpChanged ) { bool succeeded = UpdateOperandRegClass ( Pred ) ; ( void ) succeeded ; assert ( succeeded && <STR_LIT> ) ; Pred -> addRegisterDefined ( <STR_LIT> , TRI ) ; } if ( Pred -> registerDefIsDead ( <STR_LIT> , TRI ) ) { unsigned i = <NUM_LIT> , e =


<s> if ( hasSSE42 ( ) || hasSSE4A ( ) ) IsUAMem16Slow = false ; InstrItins = getInstrItineraryForCPU ( CPUName ) ; if ( In64BitMode ) ToggleFeature ( <STR_LIT> ) ; else if ( In32BitMode ) ToggleFeature ( <STR_LIT> ) ; else if ( In16BitMode ) ToggleFeature ( <STR_LIT> ) ; else llvm_unreachable ( <STR_LIT> ) ; DEBUG ( dbgs ( ) << <STR_LIT> << <ISA_LIT>SSELevel << <STR_LIT> << <ISA_LIT>3DNowLevel << <STR_LIT> << Has<ISA_LIT>_64 << <STR_LIT> ) ; assert ( ( ! In64BitMode || Has<ISA_LIT>_64 ) && <STR_LIT> ) ; if ( StackAlignOverride ) stackAlignment = StackAlignOverride ; else if ( isTargetDarwin ( ) || isTargetLinux ( ) || isTargetSolaris ( ) || isTargetKFreeBSD ( ) || In64BitMode ) stackAlignment = <NUM_LIT> ; if ( hasAVX512 ( ) || ( hasAVX2 ( ) && hasFastGather ( ) ) ) GatherOverhead = <NUM_LIT> ; if ( hasAVX512 ( ) )


<s> APInt Op0Zero , Op0One ; APInt Op1Zero , Op1One ; DAG . computeKnownBits ( Op0 , Op0Zero , Op0One , Depth ) ; DAG . computeKnownBits ( Op1 , Op1Zero , Op1One , Depth ) ; KnownZero = Op0Zero


<s> processFunctionBeforeFrameFinalized ( MachineFunction & MF ) const { MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; <ISA_LIT>FunctionInfo * <ISA_LIT>FI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; if ( <ISA_LIT>FI -> needGPSaveRestore ( ) ) MFI -> setObjectOffset ( <ISA_LIT>FI -> getGPFI

( ) , <ISA_LIT>FI -> getGPStackOffset ( ) ) ;


, CurSlots ( <NUM_LIT> ) , CurBranches ( <NUM_LIT> ) {


<s> SmallDataSection = getContext ( ) . getELFSection ( <STR_LIT> , ELF :: SHT_PROGBITS , ELF :: SHF_WRITE | ELF :: SHF_ALLOC | ELF :: SHF_HEX_GPREL ) ; SmallBSSSection = getContext ( ) . getELFSection ( <STR_LIT> , ELF :: SHT_NOBITS , ELF :: SHF_WRITE | ELF :: SHF_ALLOC |


<s> Opc = <STR_LIT> ; RC = & <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; RC = & <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; RC = & <STR_LIT> ; break ; } const BasicBlock * LLVM_BB = BB -> getBasicBlock ( ) ; MachineFunction :: iterator I = BB -> getParent ( ) -> begin ( ) ; ++ I ; MachineBasicBlock * LoopBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * RemBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; F -> insert ( I , LoopBB ) ; F -> insert ( I , RemBB ) ; RemBB -> splice ( RemBB -> begin ( ) , BB , std :: next ( MachineBasicBlock :: iterator ( MI ) ) , BB -> end ( ) ) ; RemBB -> transferSuccessorsAndUpdatePHIs ( BB ) ; BB -> addSuccessor ( LoopBB ) ; BB -> addSuccessor ( RemBB ) ; LoopBB -> addSuccessor ( RemBB ) ; LoopBB -> addSuccessor ( LoopBB ) ; unsigned ShiftAmtReg = RI . createVirtualRegister ( & <STR_LIT> ) ; unsigned ShiftAmtReg2 = RI . createVirtualRegister ( & <STR_LIT> ) ; unsigned ShiftReg = RI . createVirtualRegister ( RC ) ; unsigned ShiftReg2 = RI . createVirtualRegister ( RC ) ; unsigned ShiftAmtSrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; BuildMI ( BB , dl , TII . get ( <STR_LIT> ) ) . addReg ( ShiftAmtSrcReg ) . addImm ( <NUM_LIT> ) ; BuildMI ( BB , dl , TII . get ( <STR_LIT> ) ) . addMBB ( RemBB ) ; BuildMI ( LoopBB , dl , TII . get ( <STR_LIT> ) , ShiftReg ) . addReg ( SrcReg ) . addMBB ( BB ) . addReg ( ShiftReg2 ) . addMBB ( LoopBB ) ; BuildMI ( LoopBB , dl , TII . get ( <STR_LIT> ) , ShiftAmtReg ) . addReg ( ShiftAmtSrcReg ) . addMBB ( BB ) . addReg ( ShiftAmtReg2 ) . addMBB ( LoopBB ) ; BuildMI ( LoopBB , dl , TII . get ( Opc ) , ShiftReg2 ) . addReg ( ShiftReg ) ; BuildMI ( LoopBB , dl , TII . get ( <STR_LIT> ) , ShiftAmtReg2 ) . addReg ( ShiftAmtReg ) . addImm ( <NUM_LIT> ) ; BuildMI ( LoopBB , dl , TII . get ( <STR_LIT>


<s>
case
NearMissInfo
::
NearMissFeature
:
{
const
FeatureBitset
&
MissingFeatures
=
I
.
getFeatures
(
)
;
if
(
FeatureMissesSeen
.
count
(
MissingFeatures
)
)
break
;
FeatureMissesSeen
.
insert
(
MissingFeatures
)
;
if
(
MissingFeatures
.
test
(
Feature_Is<ISA_LIT>Bit
)
&&
!
has<ISA_LIT>
(
)
)
break
;
if
(
isThumb
(
)
&&
MissingFeatures
.
test
(
Feature_Is<ISA_LIT>Bit
)
&&
MissingFeatures
.
count
(
)
>
<NUM_LIT>
)
break
;
if
(
!
isThumb
(
)
&&
MissingFeatures
.
test
(
Feature_IsThumbBit
)
&&
MissingFeatures
.
count
(
)
>
<NUM_LIT>
)
break
;
if
(
!
isThumb
(
)
&&
MissingFeatures
.
test
(
Feature_IsThumb2Bit
)
&&
(
MissingFeatures
&
~
FeatureBitset
(
{
Feature_IsThumb2Bit
,
Feature_IsThumbBit
}
)
)
.
any
(
)
)
break
;
if
(
isMClass
(
)
&&
MissingFeatures
.
test
(
Feature_HasNEONBit
)
)
break
;
NearMissMessage
Message
;
Message
.
Loc
=
IDLoc
;
raw_svector_ostream
OS
(
Message
.
Message
)
;
OS
<<
<STR_LIT>
;
for
(
unsigned
i
=
<NUM_LIT>
,
e
=
MissingFeatures
.
size
(
)
;
i
!=
e
;
++
i
)
if
(
MissingFeatures
.
test
(
i
)
)
OS
<<
' '
<<
getSubtargetFeatureName
(
i
)
;
NearMissesOut
.
emplace_back
(
Message
)
;
break
;
}
case
NearMissInfo
::
NearMissPredicate
:
{
NearMissMessage
Message
;
Message
.
Loc
=
IDLoc
;
switch
(
I
.
getPredicateError
(
)
)
{
case
Match_RequiresNotITBlock
:
Message
.
Message
=
<STR_LIT>
;
break
;
case
Match_RequiresITBlock
:
Message
.
Message
=
<STR_LIT>
;
break
;
case
Match_RequiresV6
:
Message
.
Message
=
<STR_LIT>
;
break
;
case
Match_RequiresThumb2
:
Message
.
Message
=


<s> ResCount += ( SU -> getHeight ( ) * ScaleTwo ) ; if ( Top . ResourceModel -> isResourceAvailable ( SU ) ) ResCount <<= FactorOne ; } else { ResCount += ( SU -> getDepth ( ) * ScaleTwo ) ; if ( Bot . ResourceModel -> isResourceAvailable ( SU ) ) ResCount <<= FactorOne ; } unsigned NumNodesBlocking = <NUM_LIT> ; if ( Q . getID ( ) == TopQID ) { for ( SUnit :: const_succ_iterator I = SU -> Succs . begin ( ) , E = SU -> Succs . end ( ) ; I != E ; ++ I ) if ( getSingleUnscheduledPred ( I

-> getSUnit ( ) ) == SU ) ++ NumNodesBlocking ;


<s> bool GCNScheduleDAGMILive :: isTriviallyReMaterializable ( const MachineInstr & MI , AAResults * AA ) { if ( ! TII -> isTriviallyReMaterializable ( MI , AA ) ) return false ; for ( const MachineOperand & MO : MI . operands ( ) ) if ( MO . isReg ( ) && MO . isUse (

) && MO . getReg ( ) . isVirtual ( ) ) return false ;


<s> void ScheduleDAGPostRA :: startBlock ( MachineBasicBlock * BB ) { ScheduleDAGInstrs :: startBlock ( BB ) ; if ( AntiDepBreak != NULL ) AntiDepBreak ->


<s> const uint32_t * <ISA_LIT>RegisterInfo :: getNoPreservedMask


<s> static SDValue convertValVTToLocVT ( SelectionDAG & DAG , SDValue Val , const CCValAssign & VA , const SDLoc & DL ) { EVT LocVT = VA . getLocVT ( ) ; switch ( VA . getLocInfo ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case CCValAssign ::


<s> AU . setPreservesCFG ( ) ; AU . addRequired <


<s> unsigned getAddressableNumVGPRs ( ) const


<s> if ( ! const_vec_duplicate_p ( op , & elt ) || ! CONST_INT_P ( elt ) ) return false ; size = GET_MODE_UNIT_BITSIZE ( GET_MODE ( op ) ) ; if ( size > <NUM_LIT> ) return false ; mask = UINTVAL ( elt ) ; if ( s390_contiguous_bitmask_p ( mask , size , start , end


<s> bool <ISA_LIT>AsmBackend :: writeNopData ( raw_ostream & OS , uint64_t Count


<s> return ; } unsigned ImmOffs = <STR_LIT> ( MO2 . getImm ( ) ) ; assert ( ImmOffs && <STR_LIT> ) ; O << <STR_LIT> << ( char ) <STR_LIT> ( MO2 .


<s> std :: pair < bool , bool > R = parsePhysicalReg ( C , Prefix , Reg ) ; if ( ! R . first ) return std :: make_pair ( <NUM_LIT> , nullptr ) ; if ( ! R . second ) return std :: make_pair ( <NUM_LIT> , nullptr ) ; if ( Prefix == <STR_LIT> ) { if ( VT == <STR_LIT> ) VT = ( Subtarget . hasD ( ) ) ? <STR_LIT> : <STR_LIT> ; RC = getRegClassFor ( VT ) ; } else


<s> const <ISA_LIT>MachineFunctionInfo * MFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; DebugLoc DL ; MachineBasicBlock :: iterator I = MBB . begin ( ) ; unsigned FlatScratchInitReg = MFI -> getPreloadedReg ( <STR_LIT> ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; MRI . addLiveIn ( FlatScratchInitReg ) ; MBB . addLiveIn ( FlatScratchInitReg ) ; unsigned FlatScrInitLo = TRI -> getSubReg ( FlatScratchInitReg , <STR_LIT> ) ; unsigned FlatScrInitHi = TRI -> getSubReg ( FlatScratchInitReg , <STR_LIT> ) ; unsigned ScratchWaveOffsetReg = MFI -> getScratchWaveOffsetReg ( ) ; if ( ST . flatScratchIsPointer ( ) ) { BuildMI ( MBB , I , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( FlatScrInitLo ) . addReg ( ScratchWaveOffsetReg ) ; BuildMI ( MBB , I , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( FlatScrInitHi ) . addImm ( <NUM_LIT> ) ; return ; } BuildMI ( MBB , I , DL , TII -> get ( <STR_LIT> ) , <STR_LIT>

) . addReg ( FlatScrInitHi , RegState :: Kill ) ;


<s> if ( N -> Flags & GepNode :: Root ) { Roots . push_back ( N ) ; continue ; } GepNode * PN = N


<s> } if ( Callee && Callee -> getName ( ) == <STR_LIT> ) return outliner :: InstrType :: Illegal ; auto UnknownCallOutlineType = outliner :: InstrType :: Illegal ; if ( MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> ) UnknownCallOutlineType = outliner :: InstrType :: LegalTerminator ; if ( ! Callee ) return UnknownCallOutlineType ; MachineFunction * CalleeMF = MF -> getMMI ( ) . getMachineFunction ( * Callee ) ; if ( ! CalleeMF ) return UnknownCallOutlineType ; MachineFrameInfo & MFI = CalleeMF -> getFrameInfo ( ) ; if ( ! MFI . isCalleeSavedInfoValid ( ) || MFI . getStackSize ( ) > <NUM_LIT> || MFI . getNumObjects ( ) > <NUM_LIT> ) return UnknownCallOutlineType ; return outliner :: InstrType :: Legal ; } if ( MI . isPosition ( ) ) return outliner :: InstrType :: Illegal ; if ( MI . readsRegister ( <STR_LIT> , & getRegisterInfo ( ) ) || MI . modifiesRegister ( <STR_LIT> , & getRegisterInfo ( ) )


<s> virtual MachineInstr * foldMemoryOperandImpl ( MachineFunction & MF , MachineInstr * MI , const SmallVectorImpl < unsigned > & Ops , MachineInstr * LoadMI ) const { return


<s> static void setAliasRegs ( MachineFunction & MF , BitVector & SavedRegs , unsigned Reg ) { const TargetRegisterInfo * TRI = MF . getSubtarget ( ) . getRegisterInfo ( ) ; for ( MCRegAliasIterator AI ( Reg , TRI , true ) ; AI . isValid ( ) ; ++ AI ) SavedRegs . set (


<s> int UnscaledLdOffset = TII -> hasUnscaledLdStOffset ( LoadInst ) ? getLdStOffsetOp ( LoadInst ) . getImm ( ) : getLdStOffsetOp ( LoadInst ) . getImm ( ) * LoadSize ; return ( UnscaledStOffset <= UnscaledLdOffset ) && ( UnscaledLdOffset + LoadSize


<s>
const
MCOperand
&
MO2
=
MI
->
getOperand
(
OpNum
+
<NUM_LIT>
)
;
const
MCOperand
&
MO3
=
MI
->
getOperand
(
OpNum
+
<NUM_LIT>
)
;
printRegName
(
O
,
MO1
.
getReg
(
)
)
;
<STR_LIT>
ShOpc
=
<STR_LIT>
(
MO3
.
getImm
(
)
)
;
O
<<
<STR_LIT>
<<
<STR_LIT>
(
ShOpc
)
;
if
(
ShOpc
==
<STR_LIT>
)
return
;
O
<<
' '
;
printRegName
(
O
,
MO2
.
getReg


<s> void printAbsAddrOperand ( const MachineInstr *


<s> if ( Mask [ i ] >= <NUM_LIT> && Mask [ i ] < MaskSize ) { if ( EltFromOp0 != - <NUM_LIT> ) return - <NUM_LIT> ; EltFromOp0 = i ; } else if ( Mask [ i ] !=


<s> __inline__ static double sh_media_FMOV_QD ( long


<s> if ( ! Offset -> isDivergent ( ) ) { SDValue Ops [ ] = { Rsrc , Offset , GLC , DLC , } ; if ( VT . isVector ( ) && VT . getVectorNumElements ( ) == <NUM_LIT> ) { EVT WidenedVT = EVT :: getVectorVT ( * DAG . getContext ( ) , VT . getVectorElementType ( ) , <NUM_LIT> ) ; auto WidenedOp = DAG . getMemIntrinsicNode ( <STR_LIT> , DL , DAG . getVTList ( WidenedVT ) , Ops , WidenedVT , MF . getMachineMemOperand ( MMO , <NUM_LIT> , WidenedVT . getStoreSize ( ) ) ) ; auto Subvector = DAG . getNode ( <STR_LIT> , DL , VT , WidenedOp , DAG . getConstant ( <NUM_LIT> , DL , getVectorIdxTy ( DAG . getDataLayout ( ) ) ) ) ; return Subvector ; } return DAG . getMemIntrinsicNode ( <STR_LIT> , DL , DAG . getVTList ( VT ) , Ops , VT , MMO ) ; } SmallVector < SDValue , <NUM_LIT> > Loads ; unsigned NumLoads = <NUM_LIT> ; MVT LoadVT = VT . getSimpleVT ( ) ; unsigned NumElts = LoadVT . isVector ( ) ? LoadVT . getVectorNumElements ( ) : <NUM_LIT> ; assert ( ( LoadVT . getScalarType ( ) == <STR_LIT> || LoadVT . getScalarType ( ) == <STR_LIT> ) ) ; if ( NumElts == <NUM_LIT> || NumElts == <NUM_LIT> ) { NumLoads = NumElts / <NUM_LIT> ; LoadVT = <STR_LIT> ; } SDVTList VTList = DAG . getVTList ( { LoadVT , <STR_LIT> } ) ; unsigned CachePolicy = cast < ConstantSDNode > (


<s> return ( int64x1_t ) __builtin_neon_vdup_ndi ( ( __builtin_neon_di


<s> EVT VT = Vec . getValueType ( ) ; unsigned Elem = ElemN -> getZExtValue ( ) ; if ( Elem >= VT . getVectorNumElements ( ) ) return <NUM_LIT> ; SDValue Base , Disp , Index ; if ( ! selectBDVAddr12Only ( Store -> getBasePtr ( ) , ElemV , Base , Disp , Index ) || Index . getValueType ( ) != VT . changeVectorElementTypeToInteger ( ) ) return <NUM_LIT> ; SDLoc DL ( Store ) ; SDValue Ops [ ] = { Vec , Base , Disp , Index , CurDAG -> getTargetConstant ( Elem , DL , <STR_LIT> ) , Store -> getChain ( ) } ; return CurDAG -> getMachineNode ( Opcode , DL ,


<s> EVT VT = Node -> getValueType ( <NUM_LIT> ) ; SDLoc DL ( Node ) ; SDValue Upper = CurDAG -> getConstant ( UpperVal , DL , VT ) ; if ( Op0 . getNode ( ) ) Upper = CurDAG -> getNode ( Opcode , DL , VT , Op0 , Upper ) ; Upper = SDValue ( Select ( Upper . getNode ( ) ) , <NUM_LIT> ) ; SDValue Lower = CurDAG -> getConstant ( LowerVal , DL , VT ) ; SDValue Or = CurDAG -> getNode ( Opcode , DL , VT ,


<s>
break
;
case
LT
:
strcpy
(
string
,
<STR_LIT>
)
;
break
;
case
LE
:
strcpy
(
string
,
<STR_LIT>
)
;
break
;
case
GT
:
strcpy
(
string
,
<STR_LIT>
)
;
break
;
default
:
gcc_unreachable
(
)
;
}
p
=
strchr
(
string
,
'\0'
)
;
if
(
annul
&&
!
far
)
{
strcpy
(
p
,
<STR_LIT>
)
;
p
+=
<NUM_LIT>
;
}
if
(
insn
&&
(
note
=
find_reg_note
(
insn
,
REG_BR_PROB
,
NULL_RTX
)
)
)
{
strcpy
(
p
,
(
(
XINT
(
note
,
<NUM_LIT>
)
>=
REG_BR_PROB_BASE
/
<NUM_LIT>
)
^
far
)
<STR_LIT>
:
<STR_LIT>
)
;
p
+=
<NUM_LIT>
;
}
*
p
=
p
<
string
+
<NUM_LIT>
'\t'
:
' '
;
p
++
;
*
p
++
=
'%'
;
*
p
++
=
'0'
+
reg
;
*
p
++
=
','
;
*
p
++
=
' '
;
if
(
far
)
{
int
veryfar
=
<NUM_LIT>
,
delta
;
if
(
INSN_ADDRESSES_SET_P
(
)
)
{
delta
=
(
INSN_ADDRESSES
(
INSN_UID
(
dest
)
)
INSN_ADDRESSES
(
INSN_UID
(
insn
)
)
)
;
if
(
delta
>=
<NUM_LIT>
&&
delta
<
<NUM_LIT>
)
veryfar
=
<NUM_LIT>
;
}
strcpy
(
p
,
<STR_LIT>
)
;
if
(
annul
||
!
final_sequence
)
p
[
<NUM_LIT>
]
=
'6'
;
p
+=


<s> } if ( <ISA_LIT>InstrInfo :: isGenericOpcode ( MI . getOpcode ( ) ) || <ISA_LIT>InstrInfo :: isSALU ( MI

) || <ISA_LIT>InstrInfo :: isSMRD ( MI ) ) return false ;


<s> basic_block bb = e -> src ; rtx ret = BB_END ( bb ) ; rtx prev ; bool replace = false ; if ( GET_CODE ( ret ) != JUMP_INSN || GET_CODE ( PATTERN ( ret ) ) != RETURN || ! maybe_hot_bb_p ( bb ) ) continue ; for ( prev = PREV_INSN ( ret ) ; prev ; prev = PREV_INSN ( prev ) ) if ( active_insn_p ( prev ) || GET_CODE ( prev ) == CODE_LABEL ) break ; if ( prev && GET_CODE ( prev ) ==


<s> void <ISA_LIT>InstrInfo :: storeRegToStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , Register SrcReg , bool IsKill , int FI , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { DebugLoc DL ; if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; if ( RC == & <STR_LIT> ) BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( IsKill ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) ; else if ( RC == & <STR_LIT> ) BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( IsKill ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) ; else llvm_unreachable ( <STR_LIT>


<s> rtx op2 ; rtx op3 ; op0 = frv_int_to_acc ( icode , <NUM_LIT> , op0 ) ; if ( ! op0 ) return NULL_RTX ; op1 = frv_int_to_acc ( icode , <NUM_LIT> , op1 ) ; if ( ! op1 ) return NULL_RTX ; op2 = frv_matching_accg_for_acc ( op0 ) ; op3 = frv_matching_accg_for_acc ( op1 ) ; pat = GEN_FCN ( icode ) ( op0 , op1 , op2 , op3 ) ; if ( ! pat ) return


<s> case AtomicOrdering :: Unordered : llvm_unreachable ( <STR_LIT> ) ; case AtomicOrdering :: Monotonic : case AtomicOrdering :: Acquire : return nullptr ; case AtomicOrdering :: Release : case AtomicOrdering :: AcquireRelease : return Builder . CreateFence ( AtomicOrdering :: Release ) ; case AtomicOrdering ::


<s> AU . addRequired < MachineDominanceFrontier > ( ) ; AU . setPreservesAll (


<s> int FrameIdx ; if ( ! isVarArg ) { FrameIdx = MFI -> CreateFixedObject ( RC -> getSize ( ) / <NUM_LIT> , <NUM_LIT> , true ) ; } else { FrameIdx = MFI -> CreateStackObject ( RC -> getSize ( ) / <NUM_LIT> , RC -> getAlignment ( ) / <NUM_LIT> , false ) ; } XFI -> setUsesLR ( FrameIdx ) ; XFI -> setLRSpillSlot ( FrameIdx ) ; } if ( RegInfo -> requiresRegisterScavenging ( MF ) ) { RS -> setScavengingFrameIndex ( MFI -> CreateStackObject ( RC -> getSize ( ) / <NUM_LIT> , RC -> getAlignment ( ) / <NUM_LIT> , false ) ) ; } if ( hasFP ( MF


<s> AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , II ) . addImm ( Imm ) ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode

:: COPY ) , ResultReg ) . addReg ( II . ImplicitDefs [ <NUM_LIT> ] ) ) ;


<s> emit_move_insn ( op0 , x ) ; } emit_insn ( gen_rtx_SET ( VOIDmode , dest , const0_rtx ) ) ; if ( GET_MODE ( op0 ) != DImode ) { temp = gen_reg_rtx ( DImode ) ; convert_move ( temp , op0 , <NUM_LIT> ) ; } else temp = op0 ; emit_insn ( gen_rtx_SET ( VOIDmode , dest , gen_rtx_IF_THEN_ELSE ( GET_MODE ( dest ) , gen_rtx_fmt_ee ( compare_code , DImode , temp , const0_rtx ) , const1_rtx , dest ) ) ) ; return <NUM_LIT> ; } else { x = gen_compare_reg_1 ( compare_code , x , y ) ; y = const0_rtx


<s> if ( NumBytes < <NUM_LIT> ) { llvm_unreachable ( <STR_LIT> ) ; return <NUM_LIT> ; } else if ( NumBytes < <NUM_LIT> ) { OutStreamer . EmitInstruction ( MCInstBuilder ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( <STR_LIT> ) , STI ) ; return <NUM_LIT> ; } else if ( NumBytes < <NUM_LIT> ) { OutStreamer . EmitInstruction ( MCInstBuilder ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) , STI ) ; return <NUM_LIT> ; } else { MCSymbol * DotSym = OutContext . createTempSymbol ( ) ; const MCSymbolRefExpr * Dot = MCSymbolRefExpr :: create ( DotSym , OutContext ) ; OutStreamer . EmitInstruction ( MCInstBuilder ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . addExpr ( Dot ) , STI ) ; OutStreamer . EmitLabel ( DotSym )


<s> unsigned <ISA_LIT>BaseInstrInfo :: GetInstSizeInBytes ( const MachineInstr * MI ) const { const MachineBasicBlock & MBB = * MI -> getParent ( ) ; const MachineFunction * MF = MBB . getParent ( ) ; const MCAsmInfo * MAI = MF -> getTarget ( ) . getMCAsmInfo ( ) ; const MCInstrDesc & MCID = MI -> getDesc ( ) ; if ( MCID . getSize ( ) ) return MCID . getSize ( ) ; if ( MI -> getOpcode ( ) == <STR_LIT> ) return getInlineAsmLength ( MI -> getOperand ( <NUM_LIT> ) . getSymbolName ( ) , * MAI ) ; if ( MI -> isLabel ( ) ) return <NUM_LIT> ; unsigned Opc = MI -> getOpcode ( ) ; switch ( Opc ) { case TargetOpcode :: IMPLICIT_DEF : case TargetOpcode :: KILL : case TargetOpcode :: PROLOG_LABEL : case TargetOpcode :: EH_LABEL : case TargetOpcode :: DBG_VALUE : return <NUM_LIT> ; case TargetOpcode :: BUNDLE : return getInstBundleLength ( MI ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { unsigned EntrySize = ( Opc == <STR_LIT> ) ? <NUM_LIT> : ( ( Opc == <STR_LIT> ) ? <NUM_LIT> : <NUM_LIT> ) ; unsigned NumOps = MCID . getNumOperands ( ) ; MachineOperand JTOP = MI -> getOperand ( NumOps - ( MI -> isPredicable ( ) ? <NUM_LIT> : <NUM_LIT> ) ) ; unsigned JTI = JTOP . getIndex ( ) ; const MachineJumpTableInfo * MJTI = MF -> getJumpTableInfo ( ) ; assert ( MJTI != <NUM_LIT>


<s> return MBB . computeRegisterLiveness ( & RI , <STR_LIT> , I

, <NUM_LIT> ) == MachineBasicBlock :: LQR_Dead ;


<s> enum machine_mode mode = insn_data [ icode ] . operand [ opnum ] . mode ; if ( ( * insn_data [ icode ] . operand [ opnum ] .

predicate ) ( arg , mode ) ) return arg ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( MI -> getOperand ( <NUM_LIT> ) . isFI ( ) && MI -> getOperand ( <NUM_LIT> ) . isImm ( )

&& ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) ) {


<s> explicit <ISA_LIT>AsmPrinter ( TargetMachine & TM , std :: unique_ptr < MCStreamer > Streamer ) : AsmPrinter ( TM , std :: move ( Streamer ) ) { Subtarget = static_cast < <ISA_LIT>TargetMachine & > ( TM


<s> unsigned Opc = GetCondBranchFromCond ( ( <STR_LIT> ) Cond [ <NUM_LIT> ] . getImm ( ) ) ; BuildMI ( & MBB , DL , get ( Opc ) ) . addReg ( Cond [ <NUM_LIT> ] . getReg ( ) ) . addMBB ( TBB ) ; } return <NUM_LIT> ; } assert ( Cond . size ( ) == <NUM_LIT> && <STR_LIT> ) ; unsigned Opc = GetCondBranchFromCond ( ( <STR_LIT> ) Cond [ <NUM_LIT> ] . getImm ( ) ) ; BuildMI ( & MBB , DL , get ( Opc ) ) . addReg (


<s> if ( PacketSU -> isSucc ( PacketSUDep ) ) { for ( unsigned i = <NUM_LIT> ; i < PacketSU -> Succs . size ( ) ; ++ i ) { auto & Dep = PacketSU -> Succs [ i ] ; if ( Dep . getSUnit ( ) == PacketSUDep && Dep . getKind ( ) == SDep ::

Anti && Dep . getReg ( ) == DepReg ) return true ;


<s> SDValue TrueVal = Op . getOperand ( <NUM_LIT> ) ; SDValue FalseVal = Op . getOperand ( <NUM_LIT> ) ; SDLoc dl ( Op ) ; EVT ResultTy = getSetCCResultType ( * DAG . getContext ( ) , Op . getOperand ( <NUM_LIT> ) . getValueType ( ) ) ; SDValue Cond = DAG . getNode ( <STR_LIT> , dl , ResultTy , LHS , RHS , CC ) ; return DAG . getNode ( <STR_LIT> , dl , TrueVal . getValueType ( ) , Cond , TrueVal , FalseVal

, DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ) ;


<s> Register Reg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; bool IsHigh = <STR_LIT> ( Reg ) ; MI . setDesc ( get ( IsHigh ? HighOpcode : LowOpcode ) ) ; if ( IsHigh && ConvertHigh ) MI . getOperand ( <NUM_LIT> ) . setImm ( uint32_t ( MI . getOperand ( <NUM_LIT>


<s> if ( hasTiedUse ( OldR , MRI , NewSR ) ) return false ; auto Begin = MRI . use_begin ( OldR ) , End = MRI . use_end ( ) ; decltype ( End ) NextI ; for ( auto I = Begin ; I !=


<s> bool <ISA_LIT>InstrInfo :: isSchedulingBoundary ( const MachineInstr & MI , const MachineBasicBlock * MBB , const MachineFunction & MF ) const { if ( TargetInstrInfo :: isSchedulingBoundary ( MI , MBB , MF ) ) return true ; return isSEHInstruction (


<s> switch ( Opcode ) { default : llvm_unreachable ( <STR_LIT> ) ; case Instruction :: Trunc : return bitc :: CAST_TRUNC ; case Instruction :: ZExt : return bitc :: CAST_ZEXT ; case Instruction :: SExt : return bitc :: CAST_SEXT ; case Instruction :: FPToUI : return bitc ::


<s> rtx temp = gen_reg_rtx ( Pmode ) ; rtx temp2 = gen_reg_rtx ( Pmode ) ; tilegx_compute_pcrel_address ( temp , gen_rtx_LABEL_REF ( Pmode , op1 ) ) ; emit_move_insn ( temp2 , gen_rtx_PLUS ( Pmode , convert_to_mode ( Pmode , op0 , false ) , temp ) ) ; op0 = temp2


<s> static MCInstPrinter * createAMDGPUMCInstPrinter ( const Triple & T , unsigned SyntaxVariant , const MCAsmInfo & MAI , const MCInstrInfo & MII , const MCRegisterInfo & MRI ) { return new AMDGPUInstPrinter ( MAI ,


<s> static MCStreamer * create<ISA_LIT>MCStreamer ( const Triple & T , MCContext & Ctx , std :: unique_ptr < MCAsmBackend > && MAB , raw_pwrite_stream & OS , std :: unique_ptr < MCCodeEmitter > && Emitter , bool RelaxAll ) { return createELFStreamer ( Ctx , std :: move ( MAB ) , OS , std :: move (


<s> LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; <ISA_LIT>ISelAddressMode AM ( <ISA_LIT>ISelAddressMode :: PCD ) ; if ( ! matchAddress ( N , AM ) ) return false ; if ( ! AM . isPCRelative ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } if ( AM . hasIndexReg ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT>


<s> static void mips_end_ll_sc_sync_block (


<s> if ( cfun -> is_thunk ) return true ; return cfun -> machine -> r2_setup_needed


<s> ContainerVT = getContainerForFixedLengthVector ( VT ) ; Op1 = convertToScalableVector ( ContainerVT , Op1 , DAG , Subtarget ) ; Op2 = convertToScalableVector ( ContainerVT , Op2 , DAG , Subtarget ) ; } SDLoc DL ( Op ) ; SDValue Val = DAG . getNode ( MaskOpc , DL , ContainerVT ,


<s> if ( lowerLongBranch ( MI , OutMI ) ) return ; OutMI . setOpcode ( MI -> getOpcode ( ) ) ; for ( unsigned i = <NUM_LIT> , e = MI -> getNumOperands ( ) ; i != e


<s> void hh8 ( unsigned Size , const MCFixup & Fixup , uint64_t & Value , MCContext * Ctx = nullptr ) { Value = ( Value & <NUM_LIT> ) >> <NUM_LIT> ; ldi :: fixup ( Size , Fixup ,


<s> int i ; enum machine_mode mode = VOIDmode ; switch ( d -> vmode ) { case V16QImode : mode = V8HImode ; break ; case V32QImode : mode = V16HImode ; break ; case V64QImode : mode = V32HImode ; break ; case V8HImode : mode = V4SImode ; break ; case V16HImode : mode = V8SImode ; break ; case V32HImode : mode = V16SImode ; break ; case V4SImode : mode = V2DImode ; break ; case V8SImode : mode = V4DImode ; break ; case V16SImode : mode = V8DImode ; break ; default : return false ; } for ( i = <NUM_LIT> ; i < d -> nelt ; i += <NUM_LIT> ) if ( ( d -> perm [ i ] & <NUM_LIT> ) || d -> perm [ i + <NUM_LIT> ] != d -> perm [ i ] + <NUM_LIT> ) return false ; nd -> vmode = mode ; nd -> nelt = d -> nelt / <NUM_LIT> ; for ( i = <NUM_LIT> ; i < nd -> nelt ; i ++ ) nd -> perm [ i ] = d -> perm [ <NUM_LIT> * i ] / <NUM_LIT> ; if ( GET_MODE_INNER ( mode ) != DImode ) canonicalize_vector_int_perm ( nd , nd ) ; if ( nd != d ) { nd -> one_operand_p = d -> one_operand_p ; nd -> testing_p = d -> testing_p ; if ( d -> op0 == d -> op1 ) nd -> op0 = nd -> op1 = gen_lowpart (


<s> void <ISA_LIT>ELFStreamer :: emitLabel ( MCSymbol * Symbol , SMLoc Loc ) { LastLabel = Symbol ; LastLabelLoc = Loc


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return MSA3OpIntrinsicToGeneric ( MI , TargetOpcode :: G_ADD , MIRBuilder , ST ) ; case <STR_LIT> : return SelectMSA3OpIntrinsic ( MI , <STR_LIT> , MIRBuilder , ST ) ; case <STR_LIT> : return SelectMSA3OpIntrinsic ( MI , <STR_LIT> , MIRBuilder , ST ) ; case <STR_LIT> : return SelectMSA3OpIntrinsic ( MI , <STR_LIT> , MIRBuilder , ST ) ; case <STR_LIT> : return SelectMSA3OpIntrinsic ( MI , <STR_LIT> , MIRBuilder , ST ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return MSA3OpIntrinsicToGeneric ( MI , TargetOpcode :: G_SUB , MIRBuilder , ST ) ; case <STR_LIT> : return SelectMSA3OpIntrinsic ( MI , <STR_LIT> , MIRBuilder , ST ) ; case <STR_LIT> : return SelectMSA3OpIntrinsic ( MI , <STR_LIT> , MIRBuilder , ST ) ; case <STR_LIT> : return SelectMSA3OpIntrinsic ( MI , <STR_LIT> , MIRBuilder , ST ) ; case <STR_LIT> : return SelectMSA3OpIntrinsic ( MI , <STR_LIT> , MIRBuilder , ST ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return MSA3OpIntrinsicToGeneric ( MI , TargetOpcode :: G_MUL , MIRBuilder , ST ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return MSA3OpIntrinsicToGeneric ( MI , TargetOpcode :: G_SDIV , MIRBuilder , ST ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return MSA3OpIntrinsicToGeneric ( MI , TargetOpcode :: G_SREM , MIRBuilder , ST ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return MSA3OpIntrinsicToGeneric ( MI , TargetOpcode :: G_UDIV , MIRBuilder , ST ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return MSA3OpIntrinsicToGeneric ( MI , TargetOpcode :: G_UREM , MIRBuilder , ST ) ; case <STR_LIT> : case <STR_LIT> : return MSA3OpIntrinsicToGeneric ( MI , TargetOpcode :: G_FADD , MIRBuilder , ST ) ; case <STR_LIT> : case <STR_LIT> : return MSA3OpIntrinsicToGeneric ( MI , TargetOpcode :: G_FSUB , MIRBuilder , ST ) ; case <STR_LIT> : case <STR_LIT> : return MSA3OpIntrinsicToGeneric ( MI , TargetOpcode :: G_FMUL , MIRBuilder , ST ) ; case <STR_LIT> : case <STR_LIT> : return MSA3OpIntrinsicToGeneric ( MI , TargetOpcode :: G_FDIV , MIRBuilder , ST ) ; case <STR_LIT> : return SelectMSA3OpIntrinsic ( MI , <STR_LIT> , MIRBuilder , ST ) ; case <STR_LIT> : return SelectMSA3OpIntrinsic ( MI , <STR_LIT> , MIRBuilder , ST ) ; case <STR_LIT> : return MSA2OpIntrinsicToGeneric ( MI , TargetOpcode :: G_FSQRT , MIRBuilder , ST ) ; case <STR_LIT> : return MSA2OpIntrinsicToGeneric ( MI , TargetOpcode :: G_FSQRT , MIRBuilder , ST ) ; default : break ; } return


<s> if ( Align > PtrSize ) { auto AlignMinus1 = MIRBuilder . buildConstant ( IntPtrTy , Align - <NUM_LIT> ) ; unsigned ListTmp = MRI . createGenericVirtualRegister ( PtrTy ) ; MIRBuilder . buildGEP ( ListTmp , List , AlignMinus1 -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; DstPtr = MRI . createGenericVirtualRegister ( PtrTy ) ; MIRBuilder . buildPtrMask ( DstPtr , ListTmp , Log2_64 ( Align ) ) ; } else DstPtr = List ; uint64_t ValSize = MRI . getType ( Dst ) . getSizeInBits ( ) / <NUM_LIT> ; MIRBuilder . buildLoad ( Dst , DstPtr , * MF . getMachineMemOperand ( MachinePointerInfo ( ) ,

MachineMemOperand :: MOLoad , ValSize , std :: max ( Align , PtrSize ) ) ) ;


<s> unsigned ME = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( NewMI ) { unsigned Reg0 = ChangeReg0 ? Reg2 : MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; bool Reg0IsDead = MI -> getOperand ( <NUM_LIT> ) . isDead ( ) ; return BuildMI ( MF , MI -> getDebugLoc ( ) , MI -> getDesc ( ) ) . addReg ( Reg0 , RegState :: Define | getDeadRegState ( Reg0IsDead ) ) . addReg ( Reg2 , getKillRegState ( Reg2IsKill ) ) . addReg ( Reg1 , getKillRegState ( Reg1IsKill ) ) . addImm ( ( ME + <NUM_LIT> ) & <NUM_LIT> ) . addImm ( ( MB - <NUM_LIT> ) & <NUM_LIT> ) ; } if ( ChangeReg0 ) { MI -> getOperand ( <NUM_LIT> ) . setReg ( Reg2 ) ; MI -> getOperand ( <NUM_LIT> ) . setSubReg ( SubReg2 ) ; } MI -> getOperand ( <NUM_LIT> ) . setReg (


<s> HOST_WIDE_INT mode_align = ix86_static_rtx_alignment ( mode ) ; return MAX ( mode_align , align ) ; } else if ( ! optimize_size && TREE_CODE ( exp ) == STRING_CST && TREE_STRING_LENGTH ( exp ) >= <NUM_LIT>

&& align < BITS_PER_WORD ) return BITS_PER_WORD ;


<s> Offset = CE -> getValue ( ) ; } else if ( ! ( SRE = dyn_cast < MCSymbolRefExpr > ( Expr ) ) ) assert ( false && <STR_LIT> ) ; MCSymbolRefExpr :: VariantKind Kind = SRE -> getKind ( ) ; switch ( Kind ) { default : llvm_unreachable ( <STR_LIT> ) ; case MCSymbolRefExpr :: VK_None : break ; } OS << SRE -> getSymbol ( ) ; if ( Offset ) { if ( Offset > <NUM_LIT> ) OS


<s> void emitFnStartLocNotes ( ) const { for ( const SMLoc & Loc : FnStartLocs )


<s> <ISA_LIT>ABIInfo ABI = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getABI ( ) ; <ISA_LIT>PtrClass PtrClassKind = static_cast < <ISA_LIT>PtrClass > ( Kind ) ; switch ( PtrClassKind ) { case <STR_LIT> : return ABI . ArePtrs64bit ( ) ? & <STR_LIT> : & <STR_LIT> ; case


<s> Inst . addOperand ( MCOperand :: createImm ( unsigned


<s> if ( ! BO -> getType ( ) -> getVectorElementType ( ) -> isIntegerTy ( <NUM_LIT> ) ) return false ; bool Changed = false ; Changed |= trySADReplacement ( BO -> getOperand ( <NUM_LIT> ) , BO


<s> assert ( V2 . getSimpleValueType ( ) == <STR_LIT> && <STR_LIT> ) ; ShuffleVectorSDNode * SVOp = cast < ShuffleVectorSDNode > ( Op ) ; ArrayRef < int > Mask = SVOp -> getMask ( ) ; assert ( Mask . size ( ) == <NUM_LIT> && <STR_LIT> ) ; assert ( Subtarget -> hasAVX2 ( ) && <STR_LIT> ) ; if ( SDValue Broadcast = lowerVectorShuffleAsBroadcast ( <STR_LIT> , DL , V1 , Mask , Subtarget , DAG ) ) return Broadcast ; if ( is128BitLaneCrossingShuffleMask ( <STR_LIT> , Mask ) ) return lowerVectorShuffleAsLanePermuteAndBlend ( DL , <STR_LIT> , V1 , V2 , Mask , DAG ) ; if ( SDValue Blend = lowerVectorShuffleAsBlend ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return Blend ; if ( isShuffleEquivalent ( Mask , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , V2 ) ; if ( isShuffleEquivalent ( Mask , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , V2 ) ; if ( isSingleInputShuffleMask ( Mask ) ) { SDValue PSHUFBMask [ <NUM_LIT> ] ; for ( int i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) { if ( Mask [ i ] == - <NUM_LIT> ) { PSHUFBMask [ <NUM_LIT> * i ] = PSHUFBMask [ <NUM_LIT> * i + <NUM_LIT> ] = DAG . getUNDEF ( <STR_LIT> ) ; continue ; } int M = i < <NUM_LIT> ? Mask [ i ] : Mask [ i ] - <NUM_LIT> ; assert ( M >= <NUM_LIT> && M < <NUM_LIT> && <STR_LIT> ) ; PSHUFBMask [ <NUM_LIT> * i ] = DAG . getConstant ( <NUM_LIT> * M , <STR_LIT> ) ; PSHUFBMask [ <NUM_LIT> * i + <NUM_LIT> ] = DAG . getConstant ( <NUM_LIT> * M + <NUM_LIT> , <STR_LIT> ) ; } return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 ) , DAG . getNode ( <STR_LIT> ,


<s> const <ISA_LIT>TargetLowering & TLI = * TM . getSubtarget < <ISA_LIT>Subtarget > ( F ) . getTargetLowering ( ) ; SmallVector < EVT , <NUM_LIT> > VTs ; ComputeValueVTs ( TLI , DL , Ty , VTs ) ; for ( EVT VT : VTs ) { unsigned NumRegs = TLI . getNumRegisters ( F . getContext ( ) , VT ) ; MVT RegisterVT = TLI . getRegisterType ( F .


<s> } if ( Subtarget -> hasSSE2 ( ) ) return <STR_LIT> ; if ( Subtarget -> hasSSE1 ( ) ) return <STR_LIT> ; } else if ( ! MemcpyStrSrc && Size >= <NUM_LIT> && ! Subtarget -> is64Bit ( ) && Subtarget -> hasSSE2 ( ) ) { return <STR_LIT> ; } } if ( Subtarget -> is64Bit ( ) && Size >= <NUM_LIT> ) return <STR_LIT> ; return <STR_LIT>


<s> bool IsABICalls = Subtarget -> isABICalls ( ) ; const <ISA_LIT>ABIInfo & ABI = static_cast < const <ISA_LIT>TargetMachine & > ( TM ) . getABI ( ) ; if ( IsABICalls ) { getTargetStreamer ( ) . emitDirectiveAbiCalls ( ) ; Reloc :: Model RM = TM . getRelocationModel ( ) ; if ( RM == Reloc :: Static && ! ABI . IsN64 ( ) ) getTargetStreamer ( ) . emitDirectiveOptionPic0 ( ) ; } std :: string SectionName = std :: string ( <STR_LIT> ) + getCurrentABIString ( ) ; OutStreamer . SwitchSection ( OutContext . getELFSection ( SectionName , ELF :: SHT_PROGBITS , <NUM_LIT> ) ) ; Subtarget -> isNaN2008 ( ) ? getTargetStreamer ( ) . emitDirectiveNaN2008 ( ) : getTargetStreamer ( ) . emitDirectiveNaNLegacy ( ) ; if ( ABI . IsEABI ( ) ) { if ( Subtarget -> isGP32bit ( ) ) OutStreamer . SwitchSection ( OutContext . getELFSection ( <STR_LIT> , ELF :: SHT_PROGBITS , <NUM_LIT> ) ) ; else OutStreamer . SwitchSection ( OutContext . getELFSection ( <STR_LIT> , ELF :: SHT_PROGBITS , <NUM_LIT> ) ) ; } getTargetStreamer ( ) . updateABIInfo ( *


<s> bool <ISA_LIT>ELFObjectWriter :: needsRelocateWithSymbol ( const MCSymbol & Sym , unsigned Type ) const { switch ( Type ) { default : return false ; case ELF :: R_<ISA_LIT>ARC_GOT10 : case ELF :: R_<ISA_LIT>ARC_GOT13 : case ELF :: R_<ISA_LIT>ARC_GOT22 : case ELF :: R_<ISA_LIT>ARC_GOTDATA_HIX22 : case ELF :: R_<ISA_LIT>ARC_GOTDATA_LOX10 : case ELF :: R_<ISA_LIT>ARC_GOTDATA_OP_HIX22 : case ELF :: R_<ISA_LIT>ARC_GOTDATA_OP_LOX10


<s> void LLVMInitialize<ISA_LIT>Target ( ) { RegisterTargetMachine < <ISA_LIT>V8TargetMachine > X ( The<ISA_LIT>Target ) ; RegisterTargetMachine < <ISA_LIT>V9TargetMachine > Y ( The<ISA_LIT>V9Target ) ; RegisterAsmInfo < <ISA_LIT>ELFMCAsmInfo >


<s> SDValue Op0 = N -> getOperand ( <NUM_LIT> ) ; SDValue Op1 = N -> getOperand ( <NUM_LIT> ) ; if ( Commute ) std :: swap ( Op0 , Op1 ) ; MVT VT = N -> getSimpleValueType ( <NUM_LIT> ) ; unsigned NarrowSize = VT . getScalarSizeInBits ( ) / <NUM_LIT> ; MVT NarrowVT = <STR_LIT> ( <STR_LIT> ( NarrowSize ) , VT . getVectorElementCount ( ) ) ; SDValue Mask = N -> getOperand ( <NUM_LIT> ) ; SDValue VL = N -> getOperand ( <NUM_LIT> ) ; SDLoc DL ( N ) ; if ( ( Op1 . getOpcode ( ) == <STR_LIT> || Op1 . getOpcode ( ) == <STR_LIT> ) && Op1 . hasOneUse ( ) && Op1 . getOperand ( <NUM_LIT> ) == Mask && Op1 . getOperand ( <NUM_LIT> ) == VL ) { unsigned ExtOpc = Op1 . getOpcode ( ) ; Op1 = Op1 . getOperand ( <NUM_LIT> ) ; if ( Op1 . getValueType ( ) != NarrowVT ) Op1 = DAG . getNode ( ExtOpc , DL , NarrowVT , Op1 , Mask , VL ) ; unsigned WOpc ; if ( ExtOpc == <STR_LIT> ) WOpc = IsAdd


<s> static DecodeStatus DecodeMRSOperand ( llvm :: MCInst & Inst , unsigned Val , uint64_t Address , const void * Decoder ) { return DecodeSysRegOperand ( <STR_LIT> ( ) , Inst , Val , Address , Decoder


<s> return ( __m512i ) __builtin_ia32_cvtpd2uqq512_mask ( ( __v8df ) __A , ( __v8di )


<s> static tree common_object_handler ( tree * node , tree name ATTRIBUTE_UNUSED , tree args ATTRIBUTE_UNUSED , int flags ATTRIBUTE_UNUSED , bool * no_add_attrs ATTRIBUTE_UNUSED ) { tree decl = * node ; gcc_assert ( DECL_P ( decl ) ) ; DECL_COMMON ( decl )


<s> Register insertAssignInstr ( Register Reg , Type * Ty , <ISA_LIT>Type * SpirvTy , <ISA_LIT>GlobalRegistry * GR , MachineIRBuilder & MIB , MachineRegisterInfo & MRI ) { MachineInstr * Def = MRI . getVRegDef ( Reg ) ; assert ( ( Ty || SpirvTy ) && <STR_LIT> ) ; MIB . setInsertPt ( * Def -> getParent ( ) , ( Def -> getNextNode ( ) ? Def -> getNextNode ( ) -> getIterator ( )


<s> assert ( ( ( Val && ! VRegs . empty ( ) ) || ( ! Val && VRegs . empty ( ) ) ) && <STR_LIT> ) ; if ( VRegs . size ( ) > <NUM_LIT> ) return false ; MIRBuilder . buildInstr


<s> void setError ( unsigned Err ) { Error =


<s> } MI . RemoveOperand ( FrameRegIdx + <NUM_LIT> ) ; MI . getOperand ( FrameRegIdx + <NUM_LIT> ) . ChangeToImmediate ( <NUM_LIT> ) ; NewOpc = immediateOffsetOpcode ( Opcode ) ; AddrMode = <STR_LIT> ; } unsigned NumBits = <NUM_LIT> ; unsigned Scale = <NUM_LIT> ; if ( AddrMode == <STR_LIT> || AddrMode == <STR_LIT> ) { Offset += MI . getOperand ( FrameRegIdx + <NUM_LIT> ) . getImm ( ) ; if ( Offset < <NUM_LIT> ) { NewOpc = negativeOffsetOpcode ( Opcode ) ; NumBits = <NUM_LIT> ; isSub = true ; Offset = - Offset ; } else { NewOpc = positiveOffsetOpcode ( Opcode ) ; NumBits = <NUM_LIT> ; } } else if ( AddrMode == <STR_LIT> ) { const MachineOperand & OffOp = MI . getOperand ( FrameRegIdx + <NUM_LIT> ) ; int InstrOffs = <STR_LIT> ( OffOp . getImm ( ) ) ; if ( <STR_LIT> ( OffOp . getImm ( ) ) == <STR_LIT> ) InstrOffs *= - <NUM_LIT> ; NumBits = <NUM_LIT> ; Scale = <NUM_LIT> ; Offset += InstrOffs * <NUM_LIT> ; assert ( ( Offset & ( Scale - <NUM_LIT> ) ) == <NUM_LIT> && <STR_LIT> ) ; if ( Offset < <NUM_LIT> ) { Offset = - Offset ; isSub = true ; } } else if ( AddrMode == <STR_LIT> ) { Offset += MI . getOperand ( FrameRegIdx + <NUM_LIT> ) . getImm ( ) * <NUM_LIT> ; NumBits = <NUM_LIT> ; Scale = <NUM_LIT> ; assert ( ( Offset & <NUM_LIT> ) == <NUM_LIT> && <STR_LIT> ) ; } else { llvm_unreachable ( <STR_LIT> ) ; } if ( NewOpc != Opcode ) MI . setDesc ( TII . get ( NewOpc ) ) ; MachineOperand & ImmOp = MI . getOperand ( FrameRegIdx + <NUM_LIT> ) ; int ImmedOffset = Offset / Scale ; unsigned Mask = ( <NUM_LIT> << NumBits ) - <NUM_LIT> ; if ( ( unsigned ) Offset <= Mask * Scale ) { MI . getOperand ( FrameRegIdx ) . ChangeToRegister ( FrameReg , false ) ; if ( isSub ) { if ( AddrMode == <STR_LIT> ) ImmedOffset |= <NUM_LIT> <<


<s> void LLVMInitializeCell<ISA_LIT>AsmPrinter (


<s> void <ISA_LIT>InstPrinter :: printFunctionParameterAttribute ( const MCInst * MI , unsigned OpNo , raw_ostream & O ) { if ( OpNo < MI -> getNumOperands ( ) ) { <STR_LIT> e = static_cast < <STR_LIT> > ( MI ->


<s> return ( float32x4_t ) __builtin_neon_vcombinev2sf ( __a ,


<s> MF -> insert ( I , copy1MBB ) ; copy1MBB -> splice ( copy1MBB -> begin ( ) , MBB , std :: next ( MachineBasicBlock :: iterator ( MI ) ) , MBB -> end ( ) ) ; copy1MBB -> transferSuccessorsAndUpdatePHIs ( MBB ) ; MBB -> addSuccessor ( copy0MBB ) ; MBB -> addSuccessor ( copy1MBB ) ; BuildMI ( MBB , dl , TII . get ( <STR_LIT> ) ) . addMBB ( copy1MBB ) . addImm ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; MBB = copy0MBB ; MBB -> addSuccessor ( copy1MBB ) ; MBB = copy1MBB ; BuildMI ( * MBB , MBB -> begin ( ) , dl , TII . get ( <STR_LIT> ) , MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addMBB ( thisMBB ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addMBB ( copy0MBB ) ; MI -> eraseFromParent (


<s> BlockHasNoFallThrough ( const MachineBasicBlock & MBB ) const { if ( MBB . empty ( )


<s> AccessSize = <NUM_LIT> ; break ; case <STR_LIT> : AccessSize = <NUM_LIT> ; break ; case <STR_LIT> : AccessSize = <NUM_LIT> ; break ; case <STR_LIT> : AccessSize = <NUM_LIT> ; break ; default : return ; } InstrumentMOVSImpl ( AccessSize , Ctx


<s> const __vector unsigned int zero = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; unsigned short result ; a = ( __vector unsigned char ) __builtin_pack_vector_int128 ( <NUM_LIT> , __A ) ; b = ( __vector unsigned char ) __builtin_pack_vector_int128 ( <NUM_LIT> , __B ) ; vmin = vec_min ( a , b ) ; vmax = vec_max ( a , b ) ; vabsdiff = vec_sub ( vmax , vmin


<s> return <ISA_LIT>SinglePathInfo :: isReachable ( MF


<s> bool is64Bit ( ) const { return getSTI ( ) . getTargetTriple ( ) . getArch ( ) == Triple


<s> explicit <ISA_LIT>DAGToDAGISel ( <ISA_LIT>TargetMachine & tm ) : SelectionDAGISel ( tm ) , TM ( tm ) , Subtarget

( tm . getSubtarget < <ISA_LIT>Subtarget > ( ) ) {


<s> uint64_t COffsetVal = cast < ConstantSDNode > ( N1 ) -> getZExtValue ( ) ; if ( isUInt < <NUM_LIT> > ( COffsetVal ) ) { Addr = N0 ; OffsetVal = COffsetVal ; } } VAddr = Addr ; Offset = CurDAG -> getTargetConstant ( OffsetVal , SDLoc ( )


<s> SMLoc Start , End ; if ( isParsingInlineAsm ( ) ) { StringRef AsmTokStr = Tok . getString ( ) ; if ( AsmTokStr == <STR_LIT> || AsmTokStr == <STR_LIT> ) return ParseIntelOffsetOfOperator ( ) ; if ( AsmTokStr == <STR_LIT> || AsmTokStr == <STR_LIT> ) return ParseIntelOperator ( IOK_LENGTH ) ; if ( AsmTokStr == <STR_LIT> || AsmTokStr == <STR_LIT> ) return ParseIntelOperator ( IOK_SIZE ) ; if ( AsmTokStr == <STR_LIT> || AsmTokStr == <STR_LIT> ) return ParseIntelOperator ( IOK_TYPE ) ; } unsigned Size = getIntelMemOperandSize ( Tok . getString ( ) ) ; if ( Size ) { Parser . Lex ( ) ; if ( Tok . getString ( ) != <STR_LIT> && Tok . getString ( ) != <STR_LIT> ) return ErrorOperand ( Start , <STR_LIT> ) ; Parser . Lex ( ) ; } Start = Tok . getLoc ( ) ; if ( getLexer ( ) . is ( AsmToken :: Integer ) || getLexer ( ) . is ( AsmToken :: Minus ) || getLexer ( ) . is ( AsmToken :: LParen ) ) { AsmToken StartTok = Tok ; IntelExprStateMachine SM ( <NUM_LIT> , true , false ) ; if ( ParseIntelExpression ( SM , End ) ) return <NUM_LIT> ; int64_t Imm = SM . getImm ( ) ; if ( isParsingInlineAsm ( ) ) { unsigned Len = Tok . getLoc ( ) . getPointer ( ) - Start . getPointer ( ) ; if ( StartTok . getString ( ) . size ( ) == Len ) InstInfo -> AsmRewrites -> push_back ( AsmRewrite ( AOK_ImmPrefix , Start ) ) ; else InstInfo -> AsmRewrites -> push_back ( AsmRewrite ( AOK_Imm , Start , Len , Imm ) ) ; } if ( getLexer ( ) . isNot ( AsmToken :: LBrac ) ) { if ( SM . getSym ( ) ) return <STR_LIT> ( SM . getSym ( ) , Start , End , Size ) ; const MCExpr * ImmExpr = MCConstantExpr :: Create ( Imm , getContext ( ) ) ; return <STR_LIT> ( ImmExpr , Start , End ) ; } if ( Imm < <NUM_LIT> ) return ErrorOperand ( Start , <STR_LIT> <STR_LIT> ) ; return ParseIntelMemOperand ( Imm , Start , Size ) ; } unsigned RegNo = <NUM_LIT> ; if ( ! ParseRegister ( RegNo , Start , End ) ) { if ( getLexer ( ) . isNot ( AsmToken :: Colon ) ) return <STR_LIT> (


<s> virtual void getAnalysisUsage ( AnalysisUsage & AU ) const { AU . setPreservesCFG


<s> void rs6000_xcoff_declare_object_name ( FILE * file , const char * name , tree decl ) { struct declare_alias_data data = { file , false } ; ASM_OUTPUT_LABEL ( file ,


<s> bool Changed = false ; if ( DisableVSXFMAMutate ) return Changed ; for ( MachineFunction :: iterator I = MF . begin ( ) ; I != MF . end ( ) ; ) { MachineBasicBlock & B = * I ++ ; if ( processBlock ( B


<s> if ( getLexer ( ) . isNot ( AsmToken :: Comma ) ) return TokError ( <STR_LIT> ) ; Lex ( ) ; if ( getLexer ( ) . isNot ( AsmToken :: Integer ) ) return TokError ( <STR_LIT> ) ; Minor = getLexer ( ) . getTok ( ) . getIntVal ( ) ; Lex ( ) ; return false


<s> if ( RegNo > <NUM_LIT> ) return MCDisassembler :: Fail ; uint16_t Register = getReg ( Decoder


<s> EVT VectorT1 = Op0 . getOperand ( <NUM_LIT> ) . getValueType ( ) ; EVT VectorT2 = Op1 . getOperand ( <NUM_LIT> ) . getValueType ( ) ; uint64_t Size = VectorT1 . getFixedSizeInBits ( ) ; if ( VectorT1 != VectorT2 || ( Size != <NUM_LIT> && Size != <NUM_LIT> ) ) return SDValue ( ) ; EVT VT1 = VectorT1 . getVectorElementType ( ) ; if ( VT1 != <STR_LIT> && VT1 != <STR_LIT> && VT1 != <STR_LIT> ) return SDValue ( ) ; Op0 = Op0 . getOperand


<s> unsigned NumVectorInstToHideOverhead = <NUM_LIT> ; if ( Ty -> isVectorTy ( ) && IsComplex


<s> RegisterTargetMachine < <ISA_LIT>TargetMachine > X ( The<ISA_LIT>Target


<s> if ( IsRV64 ) { return Align ( cc128_get_required_alignment ( Size ) ) ; } else { return Align ( cc64_get_required_alignment


) _mm_setzero_di ( ) , ( __mmask8 ) __U ) ;


<s> I != E ; ++ I ) { if ( I -> getOpcode ( ) == AMDGPU :: S_BARRIER ) Changes |= insertWait ( MBB , I , LastIssued ) ; else Changes |= insertWait ( MBB , I , handleOperands ( * I ) ) ; pushInstruction ( MBB , I ) ; handleSendMsg ( MBB , I ) ; } Changes |= insertWait ( MBB , MBB . getFirstTerminator ( ) , LastIssued ) ; } return Changes


<s> bool isImm1_16 ( ) const { if ( ! isImm ( ) ) return false ; const MCConstantExpr * CE = dyn_cast <


<s> const IntrinsicData * Data = std :: lower_bound ( std :: begin ( IntrinsicsWithoutChain )

, std :: end ( IntrinsicsWithoutChain ) , IntrinsicToFind ) ;


<s> save_mask = & cfun -> machine -> save_mask ; CLEAR_HARD_REG_SET ( * save_mask ) ; var_size = PRU_STACK_ALIGN ( ( HOST_WIDE_INT ) get_frame_size ( ) ) ; out_args_size = PRU_STACK_ALIGN ( ( HOST_WIDE_INT ) crtl -> outgoing_args_size ) ; total_size = var_size + out_args_size ; save_reg_size = <NUM_LIT> ; for ( regno = <NUM_LIT> ; regno <= LAST_GP_REGNUM ; regno ++ ) if ( prologue_saved_reg_p ( regno ) ) { SET_HARD_REG_BIT ( * save_mask , regno ) ; save_reg_size += <NUM_LIT> ; } save_reg_size = PRU_STACK_ALIGN ( save_reg_size ) ; total_size += save_reg_size


<s> if ( MF . size ( ) < <NUM_LIT> ) return Changed ; for ( MachineFunction :: iterator I = MF . begin ( )


<s> if ( ! isUndefUpperHalf ( Mask ) ) return false ; int Len = HalfSize ; for ( ; Len > <NUM_LIT> ; -- Len ) if ( ! Zeroable [ Len - <NUM_LIT> ] ) break ; assert ( Len > <NUM_LIT> && <STR_LIT> ) ; SDValue Src ; int Idx = - <NUM_LIT> ; for ( int i = <NUM_LIT> ; i != Len ; ++ i ) { int M = Mask [ i ] ; if ( M == SM_SentinelUndef ) continue ; SDValue & V = ( M < Size ? V1 : V2 ) ; M = M % Size ; if ( i > M || M >= HalfSize )


<s> void EmitValueImpl ( const MCExpr * Value , unsigned Size , SMLoc Loc ) override { EmitDataMappingSymbol ( ) ; MCELFStreamer :: EmitValueImpl ( Value , Size


<s> default : break ; case CmpInst :: FCMP_OEQ : SETFOpc = & SETFOpcTable [ <NUM_LIT> ] [ <NUM_LIT> ] ; Predicate = CmpInst :: ICMP_NE ; break ; case CmpInst :: FCMP_UNE : SETFOpc = & SETFOpcTable [ <NUM_LIT> ] [ <NUM_LIT> ] ; Predicate = CmpInst :: ICMP_NE ; break ; } bool NeedSwap ; std :: tie ( CC , NeedSwap ) = get<ISA_LIT>ConditionCode ( Predicate ) ; assert ( CC <= <STR_LIT> && <STR_LIT> ) ; const Value * CmpLHS = CI -> getOperand ( <NUM_LIT> ) ; const Value * CmpRHS = CI -> getOperand ( <NUM_LIT> ) ; if ( NeedSwap ) std :: swap ( CmpLHS , CmpRHS ) ; EVT CmpVT = TLI . getValueType ( CmpLHS -> getType ( ) ) ; if ( ! <ISA_LIT>FastEmitCompare ( CmpLHS , CmpRHS , CmpVT ) ) return false ; if ( SETFOpc ) { unsigned FlagReg1 = createResultReg ( & <STR_LIT> ) ; unsigned FlagReg2 = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( SETFOpc [ <NUM_LIT> ] ) , FlagReg1 ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( SETFOpc [ <NUM_LIT> ] ) , FlagReg2 ) ; auto const & II = TII . get ( SETFOpc [ <NUM_LIT> ] ) ; if ( II . getNumDefs ( ) ) { unsigned TmpReg = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , II , TmpReg ) . addReg ( FlagReg2 ) . addReg ( FlagReg1 ) ; } else { BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , II ) . addReg ( FlagReg2 ) . addReg ( FlagReg1 ) ; } } NeedTest = false ; } else if ( fold<ISA_LIT>XALUIntrinsic ( CC , I , Cond ) ) { unsigned TmpReg = getRegForValue ( Cond ) ; if ( TmpReg == <NUM_LIT> ) return


<s> SDValue <ISA_LIT>TargetLowering :: lowerFRAMEADDR ( SDValue Op , SelectionDAG & DAG ) const { assert ( ( cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) == <NUM_LIT> ) && <STR_LIT> ) ; MachineFrameInfo & MFI = DAG . getMachineFunction ( ) . getFrameInfo ( ) ; MFI . setFrameAddressIsTaken ( true ) ; EVT VT = Op . getValueType ( ) ; SDLoc DL ( Op


<s> SDValue FractPart = DAG . getNode ( <STR_LIT> , DL , VT , DAG . getNode ( <STR_LIT> , DL , VT , DAG . getNode ( <STR_LIT> , DL , VT , Arg , DAG . getConstantFP ( <NUM_LIT> , DL , <STR_LIT> ) ) , DAG . getConstantFP ( <NUM_LIT> , DL , <STR_LIT> ) ) ) ; unsigned TrigNode ; switch ( Op . getOpcode ( ) ) { case <STR_LIT> : TrigNode = <STR_LIT> ; break ; case


<s> bool AMDGPUDAGToDAGISel :: FoldOperands ( unsigned Opcode , const R600InstrInfo * TII , std :: vector < SDValue > & Ops ) { int OperandIdx [ ] = { TII -> getOperandIdx ( Opcode , AMDGPU :: OpName :: src0 ) , TII -> getOperandIdx ( Opcode , AMDGPU :: OpName :: src1 ) , TII -> getOperandIdx ( Opcode , AMDGPU :: OpName :: src2 ) } ; int SelIdx [ ] = { TII -> getOperandIdx ( Opcode , AMDGPU :: OpName :: src0_sel ) , TII -> getOperandIdx ( Opcode , AMDGPU :: OpName :: src1_sel ) , TII -> getOperandIdx ( Opcode , AMDGPU :: OpName :: src2_sel ) } ; int NegIdx [ ] = { TII -> getOperandIdx ( Opcode , AMDGPU :: OpName :: src0_neg ) , TII -> getOperandIdx ( Opcode , AMDGPU :: OpName :: src1_neg ) , TII -> getOperandIdx ( Opcode , AMDGPU :: OpName :: src2_neg ) } ; int AbsIdx [ ] = { TII -> getOperandIdx ( Opcode , AMDGPU :: OpName :: src0_abs ) , TII -> getOperandIdx ( Opcode , AMDGPU :: OpName :: src1_abs ) , - <NUM_LIT> } ; for ( unsigned i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) { if ( OperandIdx [ i ] < <NUM_LIT> ) return false ; SDValue & Src = Ops [ OperandIdx [ i ] - <NUM_LIT> ] ; SDValue & Sel = Ops [ SelIdx [ i ] - <NUM_LIT> ] ; SDValue & Neg = Ops [ NegIdx [ i ] - <NUM_LIT> ] ; SDValue


<s> void aarch64_cpu_cpp_builtins ( cpp_reader * pfile ) { aarch64_define_unconditional_macros ( pfile ) ; aarch64_update_cpp_builtins (


<s> Cond = DAG . getNode ( <STR_LIT> , Op . getDebugLoc ( ) , <STR_LIT> , LHS , RHS , DAG . getConstant ( - <NUM_LIT> , <STR_LIT> ) , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) , CC ) ; } else if ( LHS . getValueType ( ) == <STR_LIT> ) { Cond = DAG . getNode ( <STR_LIT> , Op . getDebugLoc ( ) , <STR_LIT> , LHS , RHS , DAG . getConstantFP ( <NUM_LIT> , <STR_LIT> ) , DAG . getConstantFP ( <NUM_LIT> , <STR_LIT> ) , CC ) ; Cond = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Cond ) ; } else { assert ( <NUM_LIT> && <STR_LIT> ) ; } Cond = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) , Cond ) ; return Cond


<s> bool isVectorIndex32 ( ) const { if ( Kind != k_VectorIndex ) return false ; return VectorIndex . Val


<s> return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> for ( unsigned i = <NUM_LIT> ; i != NumElts ; ++ i ) { if ( UndefElts [ i ] ) { ShuffleMask . push_back ( SM_SentinelUndef ) ; continue ; } int Index = i & ~ ( NumEltsPerLane - <NUM_LIT> ) ; uint64_t Element = RawMask [ i ] ; if ( ElSize == <NUM_LIT> ) Index += ( Element >> <NUM_LIT> )


<s> if ( AddrDispShift != <NUM_LIT> ) Expr = DIExpression :: prepend ( Expr , DIExpression :: NoDeref , AddrDispShift , DIExpression :: WithStackValue ) ; MachineBasicBlock * MBB = MI . getParent ( ) ; DebugLoc DL = MI . getDebugLoc ( ) ; bool IsIndirect = MI .


<s> unsigned i , nelt = GET_MODE_NUNITS ( vmode ) ; vec_perm_builder perm ( nelt , nelt , <NUM_LIT> ) ; for ( i = <NUM_LIT> ; i < nelt ; i ++ ) perm . quick_push ( i * <NUM_LIT> ) ; rs6000_do_expand_vec_perm ( target , op0 , op1 , vmode


<s> ASM_OUTPUT_ALIGN ( file , floor_log2 ( align / BITS_PER_UNIT ) ) ; last_assemble_variable_decl = decl ; ASM_DECLARE_OBJECT_NAME ( file , name , decl ) ; ASM_OUTPUT_LABEL ( file , name


<s> static std :: unique_ptr < <ISA_LIT>Operand > CreateReg ( unsigned RegNo , SMLoc S , SMLoc E , const MCRegisterInfo * TRI , const MCSubtargetInfo * STI , bool ForceVOP3 ) { auto Op = llvm :: make_unique < <ISA_LIT>Operand > ( Register ) ; Op -> Reg . RegNo = RegNo ; Op -> Reg . TRI = TRI ; Op -> Reg . STI = STI ; Op -> Reg . Modifiers = <NUM_LIT> ; Op -> Reg . IsForcedVOP3 = ForceVOP3 ; Op -> StartLoc = S ; Op -> EndLoc = E ; return


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case


<s> bool YMMUsed = FnHasLiveInYmm ; if ( ! YMMUsed ) { const TargetRegisterClass * RC = & <STR_LIT> ; for ( TargetRegisterClass :: iterator i = RC -> begin ( ) , e = RC -> end ( ) ; i != e ; i ++ ) { if ( ! MRI . reg_nodbg_empty ( * i ) ) { YMMUsed = true ; break ; } } } if ( ! YMMUsed ) { return false ; } assert ( BlockStates . empty ( ) && DirtySuccessors . empty ( ) && <STR_LIT> ) ; BlockStates . resize ( MF . getNumBlockIDs ( ) ) ; for ( MachineBasicBlock & MBB : MF ) processBasicBlock ( MBB ) ; if ( FnHasLiveInYmm ) addDirtySuccessor ( MF . front ( ) ) ; while ( ! DirtySuccessors . empty ( ) ) { MachineBasicBlock & MBB = * DirtySuccessors . back ( ) ; DirtySuccessors . pop_back ( ) ; BlockState & BBState = BlockStates [ MBB . getNumber ( ) ] ; if ( BBState . FirstUnguardedCall != MBB . end ( ) ) insertVZeroUpper ( BBState . FirstUnguardedCall , MBB ) ; if ( BBState . ExitState == PASS_THROUGH ) { DEBUG ( dbgs ( ) << <STR_LIT> << MBB . getNumber ( ) << <STR_LIT> ) ; for ( MachineBasicBlock :: succ_iterator SI = MBB . succ_begin ( ) , SE = MBB .


<s> inline static bool isMaskAgnostic ( unsigned VType ) { return VType &


<s> Register DstReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( TargetRegisterInfo :: isPhysicalRegister ( DstReg ) ) return true ; const RegisterBank * RegBank = RBI . getRegBank ( DstReg , MRI , TRI ) ; const unsigned DstSize = MRI . getType ( DstReg ) . getSizeInBits ( ) ; const TargetRegisterClass * RC = & <STR_LIT> ; if ( RegBank -> getID ( ) == <STR_LIT> ) { if ( DstSize == <NUM_LIT> ) RC =


<s> unsigned getAdrLabelOpValue ( const MachineInstr & MI


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { MCInst ShlInst , FenceInst ; bool Parse32 = is32BitMode ( ) || Code16GCC ; unsigned Basereg = is64BitMode ( ) ? <STR_LIT> : ( Parse32 ? <STR_LIT> : <STR_LIT> ) ; const MCExpr * Disp = MCConstantExpr :: create ( <NUM_LIT> , getContext ( ) ) ; auto ShlMemOp = <STR_LIT> ( getPointerWidth ( ) , <NUM_LIT> , Disp , Basereg , <NUM_LIT> , <NUM_LIT> , SMLoc { } , SMLoc { } , <NUM_LIT> ) ; ShlInst . setOpcode ( <STR_LIT> ) ; ShlMemOp -> addMemOperands ( ShlInst , <NUM_LIT> ) ; ShlInst . addOperand ( MCOperand :: createImm ( <NUM_LIT> ) ) ; FenceInst . setOpcode ( <STR_LIT> ) ; Out . emitInstruction ( ShlInst , getSTI ( ) ) ; Out . emitInstruction ( FenceInst , getSTI (


<s> HII = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getInstrInfo ( ) ; HRI = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getRegisterInfo ( ) ; addMutation ( llvm :: make_unique < <ISA_LIT>Subtarget :: UsrOverflowMutation > (


<s> static reg_class_t loongarch_preferred_reload_class ( rtx x , reg_class_t rclass ) { if ( reg_class_subset_p ( FP_REGS , rclass ) && loongarch_mode_ok_for_mov_fmt_p ( GET_MODE ( x ) ) ) return FP_REGS ; if ( reg_class_subset_p ( GR_REGS , rclass ) ) rclass = GR_REGS ; return rclass


<s> EndLoc = Parser . getTok ( ) . getLoc ( ) ; return ( RegNo ==


<s> getContext ( ) . reportError ( L , <STR_LIT> ) ; return true ; } FPOInstruction Inst ; Inst . Label = emitFPOLabel ( ) ; Inst . Op = FPOInstruction :: StackAlign ; Inst . RegOrOffset = Align ; CurFPOData -> Instructions .


<s> MI . eraseFromParent ( ) ; return BB


<s> auto * OpPredicate = II . getOperand ( <NUM_LIT> ) ; auto BinOpCode = intrinsicIDToBinOpCode ( II . getIntrinsicID ( ) ) ; if ( BinOpCode == Instruction :: BinaryOpsEnd || ! match ( OpPredicate , m_Intrinsic < <STR_LIT> > ( m_ConstantInt < <STR_LIT> > ( ) ) ) ) return None ; IRBuilder < > Builder ( II . getContext


<s> const MachineJumpTableInfo * MJTI = MF -> getJumpTableInfo ( ) ; const std :: vector < MachineJumpTableEntry > & JT = MJTI -> getJumpTables ( ) ; const std :: vector < MachineBasicBlock * > & JTBBs = JT [ JTI ] . MBBs ; for ( unsigned i = <NUM_LIT> , e = JTBBs . size ( ) ; i != e ; ++ i ) { MachineBasicBlock * MBB = JTBBs [ i ] ; const MCExpr * Expr = MCSymbolRefExpr :: Create ( MBB -> getSymbol ( ) , OutContext ) ; if ( TM . getRelocationModel ( ) == Reloc :: PIC_ ) Expr = MCBinaryExpr :: CreateSub ( Expr , MCSymbolRefExpr :: Create ( JTISymbol , OutContext ) , OutContext ) ; else if ( AFI -> isThumbFunction ( ) ) Expr = MCBinaryExpr :: CreateAdd (

Expr , MCConstantExpr :: Create ( <NUM_LIT> , OutContext ) , OutContext ) ;


<s> BuildMI ( BB , I , BB . findDebugLoc ( I ) , TII -> get

( AMDGPU :: S_WAITCNT ) ) . addImm ( <NUM_LIT> ) ;


<s> void <ISA_LIT>SPClone :: handleRoot ( Function * F ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << F -> getName ( ) << <STR_LIT> ) ; if ( ! F -> hasFnAttribute (