<s> rtx aarch64_expand_sve_dupq ( rtx target , machine_mode mode , rtx src ) { machine_mode src_mode = GET_MODE ( src ) ; gcc_assert ( GET_MODE_INNER ( mode ) == GET_MODE_INNER ( src_mode ) ) ; insn_code icode = ( BYTES_BIG_ENDIAN ? code_for_aarch64_vec_duplicate_vq_be ( mode ) : code_for_aarch64_vec_duplicate_vq_le ( mode ) ) ; unsigned int i = <NUM_LIT> ; expand_operand ops [ <NUM_LIT> ] ; create_output_operand ( & ops [ i ++ ] , target , mode ) ; create_output_operand ( & ops [ i ++ ] , src , src_mode ) ; if ( BYTES_BIG_ENDIAN


<s> bool <ISA_LIT>AdvSIMDScalar :: isProfitableToTransform ( const MachineInstr * MI ) const { if ( ! isTransformable ( MI ) ) return false ; unsigned NumNewCopies = <NUM_LIT> ; unsigned NumRemovableCopies = <NUM_LIT> ; unsigned OrigSrc0 = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned OrigSrc1 = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Src0 = <NUM_LIT> , SubReg0 ; unsigned Src1 = <NUM_LIT> , SubReg1 ; if ( ! MRI -> def_empty ( OrigSrc0 ) ) { MachineRegisterInfo :: def_instr_iterator Def = MRI -> def_instr_begin ( OrigSrc0 ) ; assert ( std :: next ( Def ) == MRI -> def_instr_end ( ) && <STR_LIT> ) ; Src0 = getSrcFromCopy ( & * Def , MRI , SubReg0 ) ; if ( Src0 ) -- NumNewCopies ; if ( Src0 && MRI -> hasOneNonDBGUse ( OrigSrc0 ) ) ++ NumRemovableCopies ; } if ( ! MRI -> def_empty ( OrigSrc1 ) ) { MachineRegisterInfo :: def_instr_iterator Def = MRI -> def_instr_begin ( OrigSrc1 ) ; assert ( std :: next ( Def ) == MRI -> def_instr_end ( ) && <STR_LIT> ) ; Src1 = getSrcFromCopy ( & * Def , MRI , SubReg1 ) ; if ( Src1 ) -- NumNewCopies ; if ( Src1 && MRI -> hasOneNonDBGUse (


<s> } while ( theCurLine < lineNum ) { fstr . getline ( buff , <NUM_LIT> ) ; theCurLine ++ ; } return buff


<s> bool <ISA_LIT>RegisterInfo :: hasFP ( const MachineFunction & MF ) const { const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; return DisableFramePointerElim ( MF ) || MFI -> hasVarSizedObjects (


<s> bool HasAVX512 = Subtarget . hasAVX512 ( ) ; switch ( CC ) { case CallingConv :: GHC : case CallingConv :: HiPE : return CSR_NoRegs_RegMask ; case CallingConv :: AnyReg : if ( HasAVX ) return CSR_64_AllRegs_AVX_RegMask ; return CSR_64_AllRegs_RegMask ; case CallingConv :: PreserveMost : return CSR_64_RT_MostRegs_RegMask ; case CallingConv :: PreserveAll : if ( HasAVX ) return CSR_64_RT_AllRegs_AVX_RegMask ; return CSR_64_RT_AllRegs_RegMask ; case CallingConv :: Intel_OCL_BI : { if ( HasAVX512 && IsWin64 ) return CSR_Win64_Intel_OCL_BI_AVX512_RegMask ; if ( HasAVX512 && Is64Bit ) return CSR_64_Intel_OCL_BI_AVX512_RegMask ; if ( HasAVX && IsWin64 ) return CSR_Win64_Intel_OCL_BI_AVX_RegMask ; if ( HasAVX && Is64Bit ) return CSR_64_Intel_OCL_BI_AVX_RegMask ; if ( ! HasAVX && ! IsWin64 && Is64Bit ) return CSR_64_Intel_OCL_BI_RegMask ; break ; } case CallingConv :: Cold : if ( Is64Bit ) return CSR_64_MostRegs_RegMask ; break ; default : break ; case CallingConv :: <ISA_LIT>_64_Win64 : return CSR_Win64_RegMask ; case CallingConv :: <ISA_LIT>_64_SysV : return CSR_64_RegMask ; } if ( Is64Bit


<s> auto & HRI = * HST . getRegisterInfo ( ) ; unsigned SP = HRI . getStackRegister ( ) ; MachineInstr * RetI = getReturn ( MBB ) ; unsigned RetOpc = RetI ? RetI -> getOpcode ( ) : <NUM_LIT> ; MachineBasicBlock :: iterator InsertPt = MBB . getFirstTerminator ( ) ; DebugLoc DL ; if ( InsertPt != MBB . end ( ) ) DL = InsertPt -> getDebugLoc ( ) ; else if ( ! MBB . empty ( ) ) DL = std :: prev ( MBB . end ( ) ) -> getDebugLoc ( ) ; if ( RetOpc == <STR_LIT> ) { BuildMI ( MBB , InsertPt , DL , HII . get ( <STR_LIT> ) ) ; BuildMI ( MBB , InsertPt , DL , HII . get ( <STR_LIT> ) , SP ) . addReg ( SP ) . addReg ( <STR_LIT> ) ; return ; } if ( RetOpc == <STR_LIT> || RetOpc == <STR_LIT> || RetOpc == <STR_LIT> || RetOpc == <STR_LIT> ) { MachineBasicBlock :: iterator It = RetI ; ++ It ; while ( It != MBB . end ( ) ) { if ( ! It -> isLabel ( ) ) It = MBB . erase ( It ) ; else ++ It ; } return ; } bool NeedsDeallocframe = true ; if ( ! MBB . empty ( ) && InsertPt != MBB . begin ( ) ) { MachineBasicBlock :: iterator PrevIt = std :: prev ( InsertPt ) ; unsigned COpc = PrevIt -> getOpcode ( ) ; if ( COpc == <STR_LIT> || COpc == <STR_LIT> || COpc == <STR_LIT> || COpc == <STR_LIT> || COpc == <STR_LIT> || COpc == <STR_LIT> ) NeedsDeallocframe = false ; } if ( ! NeedsDeallocframe ) return ; if ( RetOpc != <STR_LIT> || DisableDeallocRet ) { BuildMI ( MBB , InsertPt , DL , HII . get ( <STR_LIT> ) ) ; return ; } unsigned NewOpc = <STR_LIT>


<s> unsigned getRegisterBitWidthUpperBound ( bool Vector )


<s> CCValAssign & VA = RVLocs [ i ] ; EVT CopyVT = VA . getValVT ( ) ; if ( ( CopyVT == <STR_LIT> || CopyVT == <STR_LIT> ) && ( ( Is64Bit || Ins [ i ] . Flags . isInReg ( ) ) && ! Subtarget -> hasSSE1 ( ) ) ) { llvm_report_error ( <STR_LIT> ) ; } if ( ( VA . getLocReg ( ) == <STR_LIT> || VA . getLocReg ( ) == <STR_LIT> ) && isScalarFPTypeInSSEReg ( VA . getValVT ( ) ) ) { CopyVT = <STR_LIT> ; } SDValue Val ; if ( Is64Bit && CopyVT . isVector ( ) && CopyVT . getSizeInBits ( ) == <NUM_LIT> ) { if ( VA . getLocReg ( ) == <STR_LIT> || VA . getLocReg ( ) == <STR_LIT> ) { Chain = DAG . getCopyFromReg ( Chain , dl , VA . getLocReg ( ) , <STR_LIT> , InFlag ) . getValue ( <NUM_LIT> ) ; Val = Chain . getValue ( <NUM_LIT> ) ; Val = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Val , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; } else { Chain = DAG . getCopyFromReg ( Chain , dl , VA . getLocReg ( ) , <STR_LIT> , InFlag ) . getValue ( <NUM_LIT> ) ; Val = Chain . getValue ( <NUM_LIT> ) ; } Val = DAG . getNode ( <STR_LIT> , dl , CopyVT , Val ) ; } else { Chain = DAG . getCopyFromReg ( Chain , dl , VA . getLocReg ( ) , CopyVT , InFlag ) . getValue ( <NUM_LIT> ) ; Val = Chain . getValue ( <NUM_LIT> ) ; } InFlag = Chain . getValue ( <NUM_LIT> ) ; if ( CopyVT != VA . getValVT ( ) ) { Val = DAG . getNode ( <STR_LIT> , dl , VA . getValVT ( ) , Val , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; } InVals . push_back (


<s> case <STR_LIT> : case <STR_LIT> : { const MachineOperand & Dst = MI . getOperand ( <NUM_LIT> ) ; if ( Dst . isReg ( ) && Dst . getReg ( ) == ( ST . isWave32 ( ) ? <STR_LIT> : <STR_LIT> ) && MI . getOperand ( <NUM_LIT> ) . isReg ( ) ) return MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; break ; } case <STR_LIT> : case <STR_LIT> : llvm_unreachable ( <STR_LIT> ) ; } return Register ( )


<s> if ( ! RC . contains ( Reg ) ) return diagnoseRegisterClass ( A -> RegisterName ) ; Arg = ArgDescriptor :: createRegister ( Reg ) ; } else Arg = ArgDescriptor :: createStack ( A -> StackOffset ) ; if ( A -> Mask ) Arg = ArgDescriptor :: createArg ( Arg , A -> Mask . getValue ( ) ) ; MFI -> NumUserSGPRs += UserSGPRs ; MFI -> NumSystemSGPRs += SystemSGPRs ; return false ; } ; if ( YamlMFI . ArgInfo && ( parseAndCheckArgument ( YamlMFI . ArgInfo -> PrivateSegmentBuffer , <STR_LIT> , MFI -> ArgInfo . PrivateSegmentBuffer , <NUM_LIT> , <NUM_LIT> ) || parseAndCheckArgument ( YamlMFI . ArgInfo -> DispatchPtr , <STR_LIT> , MFI -> ArgInfo . DispatchPtr , <NUM_LIT> , <NUM_LIT> ) || parseAndCheckArgument ( YamlMFI . ArgInfo -> QueuePtr , <STR_LIT> , MFI -> ArgInfo . QueuePtr , <NUM_LIT> , <NUM_LIT> ) || parseAndCheckArgument ( YamlMFI . ArgInfo -> KernargSegmentPtr , <STR_LIT> , MFI -> ArgInfo . KernargSegmentPtr , <NUM_LIT> , <NUM_LIT> ) || parseAndCheckArgument ( YamlMFI . ArgInfo -> DispatchID , <STR_LIT> , MFI -> ArgInfo . DispatchID , <NUM_LIT> , <NUM_LIT> ) || parseAndCheckArgument ( YamlMFI . ArgInfo -> FlatScratchInit , <STR_LIT> , MFI -> ArgInfo . FlatScratchInit , <NUM_LIT> , <NUM_LIT> ) || parseAndCheckArgument ( YamlMFI . ArgInfo -> PrivateSegmentSize , <STR_LIT> , MFI -> ArgInfo . PrivateSegmentSize , <NUM_LIT> , <NUM_LIT> ) || parseAndCheckArgument ( YamlMFI . ArgInfo -> WorkGroupIDX , <STR_LIT> , MFI -> ArgInfo . WorkGroupIDX , <NUM_LIT> , <NUM_LIT> ) || parseAndCheckArgument ( YamlMFI . ArgInfo -> WorkGroupIDY , <STR_LIT> , MFI -> ArgInfo . WorkGroupIDY , <NUM_LIT> , <NUM_LIT> ) || parseAndCheckArgument ( YamlMFI . ArgInfo -> WorkGroupIDZ , <STR_LIT> , MFI -> ArgInfo . WorkGroupIDZ , <NUM_LIT> , <NUM_LIT> ) || parseAndCheckArgument ( YamlMFI . ArgInfo -> WorkGroupInfo , <STR_LIT> , MFI -> ArgInfo . WorkGroupInfo , <NUM_LIT> , <NUM_LIT> ) || parseAndCheckArgument ( YamlMFI . ArgInfo -> PrivateSegmentWaveByteOffset , <STR_LIT> , MFI -> ArgInfo . PrivateSegmentWaveByteOffset , <NUM_LIT> , <NUM_LIT> ) || parseAndCheckArgument ( YamlMFI . ArgInfo -> ImplicitArgPtr , <STR_LIT> , MFI -> ArgInfo . ImplicitArgPtr , <NUM_LIT> , <NUM_LIT> ) || parseAndCheckArgument ( YamlMFI . ArgInfo -> ImplicitBufferPtr , <STR_LIT> , MFI -> ArgInfo . ImplicitBufferPtr , <NUM_LIT> , <NUM_LIT> ) || parseAndCheckArgument ( YamlMFI . ArgInfo ->

WorkItemIDX , <STR_LIT> , MFI -> ArgInfo . WorkItemIDX , <NUM_LIT> , <NUM_LIT> ) || parseAndCheckArgument ( YamlMFI . ArgInfo -> WorkItemIDY , <STR_LIT> , MFI -> ArgInfo . WorkItemIDY , <NUM_LIT> , <NUM_LIT> ) || parseAndCheckArgument ( YamlMFI . ArgInfo -> WorkItemIDZ , <STR_LIT> , MFI -> ArgInfo . WorkItemIDZ , <NUM_LIT> , <NUM_LIT> ) ) ) return true ;


<s> inline SDValue XformM5ToU5Imm ( signed Imm , SDLoc DL ) { assert ( ( Imm >= - <NUM_LIT> &&


<s> space_allocated = fi . arg_size + fi . reg_size + fi . local_size + fi . outbound_size + fi . pad_outbound + fi . pad_local + fi . pad_reg ; if ( TARGET_CG_DATA ) { rtx x ; x = DECL_RTL ( current_function_decl ) ; gcc_assert ( GET_CODE ( x ) == MEM ) ; x = XEXP ( x , <NUM_LIT> ) ; gcc_assert ( GET_CODE ( x ) == SYMBOL_REF ) ; if ( mcore_current_function_name ) free ( mcore_current_function_name ) ; mcore_current_function_name = xstrdup ( XSTR ( x , <NUM_LIT> ) ) ; ASM_OUTPUT_CG_NODE ( asm_out_file , mcore_current_function_name , space_allocated ) ; if ( current_function_calls_alloca ) ASM_OUTPUT_CG_EDGE ( asm_out_file , mcore_current_function_name , <STR_LIT> , <NUM_LIT> ) ; fprintf ( asm_out_file , <STR_LIT> , mcore_current_function_name , fi . arg_size , fi . reg_size , fi . reg_mask , fi . local_size , fi . outbound_size , frame_pointer_needed ) ; } if ( mcore_naked_function_p ( ) ) return ; output_stack_adjust ( - <NUM_LIT> , fi . growth [ growth ++ ] ) ; if ( fi . arg_size != <NUM_LIT> && current_function_pretend_args_size == <NUM_LIT> ) { int offset ; int rn = FIRST_PARM_REG +


<s> if ( Flags == <STR_LIT> ) return <STR_LIT> ; for ( auto FlagSet : AddrModesMap . at ( <STR_LIT> ) ) if ( ( Flags & FlagSet ) == FlagSet ) return <STR_LIT> ; for ( auto FlagSet : AddrModesMap . at ( <STR_LIT> ) ) if ( ( Flags & FlagSet ) ==


<s> __arm_uqshl ( uint32_t value , const int shift ) { return __builtin_mve_uqshl_si ( value


<s> uint64_t Index = N -> getConstantOperandVal ( <NUM_LIT> ) ; MVT VecVT = N -> getSimpleValueType ( <NUM_LIT> ) ; unsigned NumElemsPerChunk = VecWidth / VecVT . getScalarSizeInBits ( ) ; return getI8Imm ( Index / NumElemsPerChunk ,


<s> unsigned <ISA_LIT>InstructionSelector :: selectLoadStoreOpCode ( unsigned Opc , unsigned RegBank , unsigned Size ) const { bool isStore = Opc == TargetOpcode :: G_STORE ; if ( RegBank == <STR_LIT> ) { switch ( Size ) { case <NUM_LIT> : case <NUM_LIT> : return isStore ? Opcodes . STORE8 : Opcodes . LOAD8 ; case


<s> if ( Desc . TSFlags & ( <STR_LIT> | <STR_LIT> | <STR_LIT> | <STR_LIT> | <STR_LIT> | <STR_LIT> ) ) { if ( <STR_LIT> ( Opcode , <STR_LIT> :: imm ) != - <NUM_LIT> ) { ++ ConstantBusUseCount ; } SmallDenseSet < unsigned > SGPRsUsed ; unsigned SGPRUsed = findImplicitSGPRReadInVOP ( Inst ) ; if ( SGPRUsed != <STR_LIT> ) { SGPRsUsed . insert ( SGPRUsed ) ; ++ ConstantBusUseCount ; } const int Src0Idx = <STR_LIT> ( Opcode , <STR_LIT> :: src0 ) ; const int Src1Idx = <STR_LIT> ( Opcode , <STR_LIT> :: src1 ) ; const int Src2Idx = <STR_LIT> ( Opcode , <STR_LIT> :: src2 ) ; const int OpIndices [ ] = { Src0Idx , Src1Idx , Src2Idx } ; for ( int OpIdx : OpIndices ) { if ( OpIdx == - <NUM_LIT> ) break ; const MCOperand & MO = Inst . getOperand ( OpIdx ) ; if ( usesConstantBus ( Inst , OpIdx ) ) { if ( MO . isReg


<s> MCAsmBackend * llvm :: create<ISA_LIT>AsmBackend ( const Target & T , const MCRegisterInfo & MRI , StringRef TT , StringRef CPU ) { if ( Triple ( TT ) . isOSDarwin ( ) ) return new Darwin<ISA_LIT>AsmBackend ( T ) ; uint8_t OSABI = MCELFObjectTargetWriter :: getOSABI ( Triple ( TT ) . getOS (


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const


<s> void <ISA_LIT>ATTAsmPrinter :: printSSECC ( const MachineInstr * MI , unsigned Op ) { unsigned char value = MI -> getOperand ( Op ) . getImm ( ) ; assert ( value <= <NUM_LIT> && <STR_LIT> ) ; switch ( value ) { case <NUM_LIT> : O << <STR_LIT>


<s> SDValue Val = DAG . getCopyFromReg ( Chain , dl , VA . getLocReg ( ) , VA . getLocVT ( ) , InFlag ) ; Chain = Val . getValue ( <NUM_LIT> ) ; InFlag = Val . getValue ( <NUM_LIT> ) ; switch ( VA . getLocInfo ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case CCValAssign :: Full : break ; case CCValAssign :: AExt : Val = DAG . getNode ( <STR_LIT> , dl , VA . getValVT ( ) , Val ) ; break ; case CCValAssign :: ZExt : Val = DAG . getNode ( <STR_LIT> , dl , VA . getLocVT ( ) , Val , DAG . getValueType ( VA . getValVT ( ) ) ) ; Val = DAG . getNode ( <STR_LIT> , dl , VA . getValVT ( ) , Val ) ; break ; case CCValAssign :: SExt : Val = DAG . getNode ( <STR_LIT> , dl , VA . getLocVT ( ) , Val , DAG . getValueType ( VA . getValVT ( ) ) ) ; Val = DAG . getNode ( <STR_LIT> , dl , VA . getValVT ( ) , Val ) ; break ; } InVals . push_back (


<s> MEM_VOLATILE_P ( memref ) = <NUM_LIT> ; emit_insn ( gen_movsi ( memref , stack_pointer_rtx ) ) ; size -= mcore_stack_increment ; } while ( size > mcore_stack_increment ) ; } if ( size ) { rtx insn ; rtx val = GEN_INT ( size ) ; if ( size > <NUM_LIT> ) { rtx nval = gen_rtx_REG ( SImode


<s> static <ISA_LIT>Operand * CreateVectorIndex ( unsigned Idx , SMLoc S , SMLoc E , MCContext & Ctx ) { <ISA_LIT>Operand * Op = new <ISA_LIT>Operand ( k_VectorIndex , Ctx


<s> const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; if ( MFI . hasCalls ( ) && ! MF . getInfo

< <ISA_LIT>MachineFunctionInfo > ( ) -> isEntryFunction ( ) ) {


<s> unsigned <ISA_LIT>ompactRegisterInfo :: getRARegister (


<s> ScopeReg = buildI32Constant ( Scope , I ) ; unsigned ScSem = getMemSemanticsForStorageClass ( GR . getPointerStorageClass ( Ptr ) ) ; unsigned MemSemEq = getMemSemantics ( MemOp -> getSuccessOrdering ( ) ) | ScSem ; MemSemEqReg = buildI32Constant ( MemSemEq , I ) ; unsigned MemSemNeq = getMemSemantics ( MemOp -> getFailureOrdering ( ) ) | ScSem ; MemSemNeqReg = MemSemEq == MemSemNeq ? MemSemEqReg : buildI32Constant ( MemSemNeq , I ) ; } else { ScopeReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; MemSemEqReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; MemSemNeqReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; } Register Cmp = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register Val = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; <ISA_LIT>Type * SpvValTy = GR . get<ISA_LIT>TypeForVReg ( Val ) ; Register ACmpRes = MRI -> createVirtualRegister ( & <STR_LIT> ) ; const DebugLoc & DL = I . getDebugLoc ( ) ; bool Result = BuildMI ( * I . getParent ( ) , I , DL , TII . get ( <STR_LIT> ) ) . addDef ( ACmpRes ) . addUse ( GR . get<ISA_LIT>TypeID ( SpvValTy ) ) . addUse ( Ptr ) . addUse ( ScopeReg ) . addUse ( MemSemEqReg ) . addUse ( MemSemNeqReg ) . addUse ( Val ) . addUse ( Cmp ) . constrainAllUses ( TII , TRI , RBI ) ; Register CmpSuccReg = MRI -> createVirtualRegister ( & <STR_LIT> ) ; <ISA_LIT>Type * BoolTy = GR . getOrCreate<ISA_LIT>BoolType (


<s> const TargetRegisterClass * DefRC = RegClassOrBank . dyn_cast < const TargetRegisterClass * > ( ) ; if ( ! DefRC ) { if ( ! DefTy . isValid ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } const RegisterBank & RB = * RegClassOrBank . get < const RegisterBank * > ( ) ; if ( RB . getID ( ) == <STR_LIT> ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } DefRC = TRI . getRegClassForTypeOnBank ( DefTy , RB , * MRI ) ; if ( ! DefRC


<s> void <ISA_LIT>InstPrinter :: printT2AddrModeImm8Operand ( const MCInst * MI , unsigned OpNum , raw_ostream & O ) { const MCOperand & MO1 = MI -> getOperand ( OpNum ) ; const MCOperand & MO2 = MI -> getOperand ( OpNum + <NUM_LIT> ) ; O << markup ( <STR_LIT> ) << <STR_LIT> ; printRegName ( O , MO1 . getReg ( ) ) ; int32_t OffImm = ( int32_t ) MO2 . getImm ( ) ; if ( OffImm != <NUM_LIT> ) O << <STR_LIT> ; if ( OffImm != <NUM_LIT> && UseMarkup ) O << <STR_LIT> ; if ( OffImm == INT32_MIN ) O << <STR_LIT> ; else if ( OffImm < <NUM_LIT> ) O << <STR_LIT> << - OffImm ; else if ( OffImm > <NUM_LIT> ) O << <STR_LIT> << OffImm ; if ( OffImm != <NUM_LIT> && UseMarkup ) O << <STR_LIT> ; O << <STR_LIT> << markup (


<s> machine_mode mode = GET_MODE ( dst ) ; if ( GET_MODE_INNER ( mode ) == HFmode ) { gcc_assert ( ! recp ) ; return false ; } machine_mode mmsk = mode_for_vector ( int_mode_for_mode ( GET_MODE_INNER ( mode ) ) , GET_MODE_NUNITS ( mode ) ) ; if ( ! recp ) { if ( ! ( flag_mlow_precision_sqrt || ( aarch64_tune_params . approx_modes -> sqrt & AARCH64_APPROX_MODE ( mode ) ) ) ) return false ; if ( flag_finite_math_only || flag_trapping_math || ! flag_unsafe_math_optimizations || optimize_function_for_size_p ( cfun ) ) return false ; } else gcc_assert ( use_rsqrt_p ( mode ) ) ; rtx xmsk = gen_reg_rtx ( mmsk ) ; if ( ! recp ) emit_insn ( gen_rtx_SET ( xmsk , gen_rtx_NEG ( mmsk , gen_rtx_EQ ( mmsk , src , CONST0_RTX ( mode ) ) ) ) ) ; rtx xdst = gen_reg_rtx ( mode ) ; emit_insn ( ( * get_rsqrte_type ( mode ) ) ( xdst , src ) ) ; int iterations = ( GET_MODE_INNER ( mode ) == DFmode ) ? <NUM_LIT> : <NUM_LIT> ; if ( ( recp && flag_mrecip_low_precision_sqrt ) || ( ! recp && flag_mlow_precision_sqrt ) ) iterations -- ; rtx x1 = gen_reg_rtx ( mode ) ; while ( iterations


<s> const TargetRegisterClass * <ISA_LIT>InstrInfo :: getOpRegClass ( const MachineInstr & MI , unsigned OpNo ) const { const MachineRegisterInfo & MRI = MI . getParent ( ) -> getParent ( ) -> getRegInfo ( ) ; const MCInstrDesc & Desc = get ( MI . getOpcode ( ) ) ; if ( MI . isVariadic ( ) || OpNo >= Desc . getNumOperands ( ) || Desc . OpInfo [ OpNo ] . RegClass == - <NUM_LIT> ) { Register Reg = MI . getOperand ( OpNo ) . getReg ( ) ; if ( Reg . isVirtual ( ) ) return MRI . getRegClass ( Reg ) ; return RI . getPhysRegClass


<s> case ST : return <STR_LIT> ; case ISH : return <STR_LIT> ; case ISHST : return <STR_LIT> ; case NSH : return


<s> unsigned SpillAlign = <NUM_LIT> ; unsigned PrivateAlign = <NUM_LIT> ; for ( int I = MFI -> getObjectIndexBegin ( ) , E = MFI -> getObjectIndexEnd ( ) ; I != E ; ++ I ) { if ( MFI -> isDeadObjectIndex ( I ) ) continue ; unsigned Size = MFI -> getObjectSize ( I ) ; unsigned Align = MFI -> getObjectAlignment ( I ) ; unsigned Offset = MFI -> getObjectOffset ( I ) ; assert ( Offset == <NUM_LIT> && <STR_LIT> ) ; if ( MFI -> isSpillSlotObjectIndex ( I ) ) { SpillSize = ( SpillSize + Align - <NUM_LIT> ) / Align * Align ; SpillMap [ I ] = SpillSize ; SpillSize += Size ; SpillAlign = std :: max ( SpillAlign , Align ) ; } else { PrivateSize = ( PrivateSize + Align - <NUM_LIT> ) / Align * Align ; PrivateMap [ I ] = PrivateSize ; PrivateSize += Size ; PrivateAlign = std :: max ( PrivateAlign , Align ) ; } MFI -> RemoveStackObject ( I ) ; } int PrivateIndex = - <NUM_LIT> ; int SpillIndex = - <NUM_LIT> ; if ( PrivateSize != <NUM_LIT> ) PrivateIndex = MFI -> CreateStackObject ( PrivateSize , PrivateAlign , false ) ; if ( SpillSize != <NUM_LIT> ) SpillIndex = MFI -> CreateSpillStackObject ( SpillSize , SpillAlign ) ; for ( MachineBasicBlock & MBB : MF ) { for ( MachineInstr & MI : MBB ) { unsigned Opc = MI .


<s> static bool frv_issues_to_branch_unit_p (


<s> cgraph_node * local_info_node = cgraph_node :: local_info_node ( current_function_decl ) ; if ( local_info_node && local_info_node -> local ) return pic_offset_table_rtx ; if ( OPTION_SET_P ( bfin_library_id ) ) addr = plus_constant ( Pmode , pic_offset_table_rtx , - <NUM_LIT> - bfin_library_id * <NUM_LIT> ) ; else addr = gen_rtx_PLUS ( Pmode , pic_offset_table_rtx , gen_rtx_UNSPEC ( Pmode , gen_rtvec ( <NUM_LIT> , const0_rtx ) , UNSPEC_LIBRARY_OFFSET ) ) ; emit_insn ( gen_movsi ( dest , gen_rtx_MEM ( Pmode ,


<s> bool <ISA_LIT>BaseInstrInfo :: getRegSequenceLikeInputs ( const MachineInstr & MI , unsigned DefIdx , SmallVectorImpl < RegSubRegPairAndIdx > & InputRegs ) const { assert ( DefIdx < MI . getDesc ( ) . getNumDefs ( ) && <STR_LIT> ) ; assert ( MI . isRegSequenceLike ( ) && <STR_LIT> ) ; switch ( MI . getOpcode ( )


<s> if ( ! prev || ! has_memory_op ( prev ) ) return false ; body = single_set ( prev ) ; if ( GET_MODE ( recog_data . operand [ <NUM_LIT> ] ) == DImode && ( ! body || ! dep_between_memop_and_curr (


<s> else if ( MO . isGlobal ( ) ) emitGlobalAddress ( MO . getGlobal ( ) , getRelocation ( MI , MO ) , true ) ; else if ( MO . isSymbol ( ) ) emitExternalSymbolAddress ( MO . getSymbolName ( ) , getRelocation ( MI , MO ) ) ; else if ( MO . isCPI ( ) ) emitConstPoolAddress ( MO . getIndex ( ) , getRelocation ( MI , MO ) ) ; else if ( MO . isJTI ( ) ) emitJumpTableAddress ( MO . getIndex ( ) , getRelocation ( MI , MO ) ) ; else if ( MO . isMBB ( ) ) emitMachineBasicBlock ( MO . getMBB ( ) ,


<s> unsigned Lane = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned Fs = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Wt = RegInfo . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) , Wt ) . addImm ( <NUM_LIT> ) . addReg ( Fs ) .


<s> rtx_insn * insn ; if ( optimize_size ) return <NUM_LIT> ; insn = next_active_insn ( label ) ; if ( insn == <NUM_LIT> ) return <NUM_LIT> ; else if ( ( get_attr_length ( insn ) % <NUM_LIT> ) == <NUM_LIT> ) return <NUM_LIT> ; else return


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : for ( ConstMIOperands Mo ( DefI ) ; Mo . isValid ( ) ; ++ Mo ) if ( Mo -> isReg ( ) && Mo -> isUse ( ) ) WorkQ . push ( Register ( Mo -> getReg ( ) ) ) ; break ; default : return isScalarCmp (


<s> if ( Op . isReg ( ) ) { unsigned Reg = Op . getReg ( ) ; O << getRegisterName ( Reg ) ; } else if ( Op . isImm ( )


<s> static void aarch64_conditional_register_usage ( void ) { int i ; if ( ! TARGET_FLOAT ) { for ( i = V0_REGNUM ; i <= V31_REGNUM ; i ++ ) { fixed_regs [ i ] = <NUM_LIT> ; call_used_regs [ i ] =


<s> return ( vector signed int ) __builtin_altivec_vupklsh ( (


<s> if ( ! has_hard_reg_initial_val ( Pmode , REG_RA ) ) return regs_ever_live [ REG_RA ] ; push_topmost_sequence ( )


<s> } unsigned Count = <NUM_LIT> ; <STR_LIT> CC = ( <STR_LIT> ) Cond [ <NUM_LIT> ] . getImm ( ) ; MI = BuildMI ( & MBB , DL , get ( getBranchOpcodeFromCond ( CC ) ) ) . addMBB ( TBB ) . addReg ( Cond [ <NUM_LIT> ] . getReg ( ) ) . addReg ( Cond [ <NUM_LIT> ] . getReg ( ) ) ; if ( BytesAdded ) * BytesAdded += getInstSizeInBytes


<s> void <ISA_LIT>TargetAsmStreamer :: emitDirectiveSetNoVirt ( )


<s> static bool IsInSmallSection ( uint64_t


<s> auto & QST = MBB -> getParent ( ) -> getSubtarget < <ISA_LIT>Subtarget > ( ) ; const auto & QII = * QST . getInstrInfo ( ) ; if ( IsTop ) { for ( unsigned i = <NUM_LIT> , e = Packet . size ( ) ; i != e ; ++ i ) if ( hasDependence ( Packet [ i ] , SU , QII ) ) return false ; } else { for ( unsigned i = <NUM_LIT> , e = Packet . size ( ) ; i != e ; ++ i ) if ( hasDependence ( SU , Packet [ i ] , QII ) ) return false ; } return true


<s> if ( TT . isOSNaCl ( ) || TT . isOSIAMCU ( ) ) ; else if ( TT . isArch64Bit ( ) || TT . isOSDarwin ( ) || TT . isWindowsMSVCEnvironment ( ) ) Ret += <STR_LIT> ; else Ret += <STR_LIT> ; if ( TT . isOSIAMCU ( ) ) Ret += <STR_LIT> ; if ( TT . isArch64Bit ( ) ) Ret += <STR_LIT> ; else Ret += <STR_LIT> ; if ( ( ! TT . isArch64Bit ( ) && TT . isOSWindows ( ) ) || TT . isOSIAMCU ( ) )


<s> unsigned AddrReg = Saved [ <NUM_LIT> ] . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned SpReg = Saved [ <NUM_LIT> ] . getOperand ( <NUM_LIT> ) . getReg ( ) ; int64_t Pred = Saved [ <NUM_LIT> ] . getOperand ( <NUM_LIT> ) . getImm ( ) ; assert ( ( <STR_LIT> == SpReg ) && <STR_LIT> ) ; Out . EmitBundleLock ( false ) ; EmitBICMask ( STI , Out , AddrReg , Pred , <NUM_LIT> ) ; Out . EmitInstruction ( Saved [ <NUM_LIT> ] , STI ) ; EmitBICMask ( STI , Out , SpReg , Pred , <NUM_LIT> ) ; Out . EmitBundleUnlock ( )


<s> auto Cst = getBuildVectorConstantSplat ( * MI , MRI ) ; if ( ! Cst ) return false ; Cnt = * Cst ; int64_t ElementBits = Ty . getScalarSizeInBits ( ) ; return Cnt >= <NUM_LIT> && Cnt <=


<s> EVT ElVT = VT . getVectorElementType ( ) ; unsigned IdxVal = cast < ConstantSDNode > ( Idx ) -> getZExtValue ( ) ; EVT ResultVT = Result . getValueType ( ) ; unsigned ElemsPerChunk = <NUM_LIT> / ElVT . getSizeInBits ( ) ; unsigned NormalizedIdxVal = ( ( ( IdxVal * ElVT . getSizeInBits ( ) ) / <NUM_LIT> ) * ElemsPerChunk ) ; SDValue VecIdx = DAG . getConstant ( NormalizedIdxVal ,


<s> bool <ISA_LIT>InstructionSelector :: selectCopy ( MachineInstr & I , MachineRegisterInfo & MRI ) const { Register DstReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; const unsigned DstSize = RBI . getSizeInBits ( DstReg , MRI , TRI ) ; const RegisterBank & DstRegBank = * RBI . getRegBank ( DstReg , MRI , TRI ) ; Register SrcReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; const unsigned SrcSize = RBI . getSizeInBits ( SrcReg , MRI , TRI ) ; const RegisterBank & SrcRegBank = * RBI . getRegBank ( SrcReg , MRI , TRI ) ; if ( Register :: isPhysicalRegister ( DstReg ) ) { assert ( I . isCopy ( ) && <STR_LIT> ) ; if ( DstSize > SrcSize && SrcRegBank . getID ( ) == <STR_LIT> && DstRegBank . getID ( ) == <STR_LIT> ) { const TargetRegisterClass * SrcRC = getRegClass ( MRI . getType ( SrcReg ) , SrcRegBank ) ; const TargetRegisterClass * DstRC = getRegClassFromGRPhysReg ( DstReg ) ; if ( SrcRC != DstRC ) { Register ExtSrc = MRI . createVirtualRegister ( DstRC ) ; BuildMI ( * I . getParent ( ) , I , I . getDebugLoc ( ) , TII . get ( TargetOpcode :: SUBREG_TO_REG ) ) . addDef ( ExtSrc ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg ) . addImm ( getSubRegIndex ( SrcRC ) ) ; I . getOperand ( <NUM_LIT> ) . setReg ( ExtSrc ) ; } } return true ; } assert ( ( ! Register :: isPhysicalRegister ( SrcReg ) || I . isCopy ( ) ) && <STR_LIT> ) ; assert ( ( DstSize == SrcSize || ( Register :: isPhysicalRegister ( SrcReg ) && DstSize <= RBI . getSizeInBits ( SrcReg , MRI , TRI ) ) ) && <STR_LIT> ) ; const TargetRegisterClass * DstRC = getRegClass ( MRI . getType ( DstReg ) , DstRegBank ) ; if ( SrcRegBank . getID ( ) == <STR_LIT> && DstRegBank . getID ( ) == <STR_LIT> && SrcSize > DstSize && Register :: isPhysicalRegister ( SrcReg ) ) { const TargetRegisterClass * SrcRC = getRegClassFromGRPhysReg (


<s> return ( __m64 ) __builtin_arm_wabsdiffw ( ( __v2si ) a , (


<s> vmlal_high_u8 ( uint16x8_t a , uint8x16_t b , uint8x16_t c ) { uint16x8_t result ; __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) ,


<s> xpattern = gen_rtx_SET ( VOIDmode , xop [ <NUM_LIT> ] , xsrc ) ; op [ <NUM_LIT> ] = xop [ <NUM_LIT> ] ; op [ <NUM_LIT> ] = xop [ <NUM_LIT> ] ; op [ <NUM_LIT> ] = xadd ; avr_out_plus ( xpattern , op , plen_add , NULL , false ) ; avr_asm_len ( <STR_LIT> CR_TAB <STR_LIT> , NULL , plen_add , <NUM_LIT> ) ; rtx xreg = simplify_gen_subreg ( imode , xop [ <NUM_LIT> ] , mode , <NUM_LIT> ) ; rtx xmask = immed_wide_int_const ( - wi_add - wi_add , imode ) ; xpattern = gen_rtx_SET ( VOIDmode , xreg , gen_rtx_AND ( imode , xreg , xmask ) ) ; op [ <NUM_LIT> ] = xreg ; op [ <NUM_LIT> ] = xreg ; op [ <NUM_LIT> ] = xmask ; op [ <NUM_LIT> ] = gen_rtx_SCRATCH ( QImode ) ; avr_out_bitop ( xpattern , op , plen_and ) ; avr_asm_len ( <STR_LIT> , NULL , plen , <NUM_LIT> ) ; if ( plen ) *


<s> SDValue Div = DAG . getNode ( <STR_LIT> , DL , DAG . getVTList ( VT , VT ) , LHS , RHS ) ; SDValue Rem = Div . getValue ( <NUM_LIT> ) ; Div = DAG . getNode ( <STR_LIT> , DL , VT , Div , DSign ) ; Rem = DAG . getNode ( <STR_LIT> , DL , VT , Rem , RSign ) ; Div = DAG . getNode ( <STR_LIT> , DL , VT , Div , DSign ) ; Rem = DAG . getNode ( <STR_LIT> , DL , VT , Rem , RSign ) ; SDValue Res [ <NUM_LIT> ] = { Div ,


<s> if ( Reg == <STR_LIT> ) Reg = MatchRegisterName ( RegName ) ; if ( Reg == <STR_LIT> ) report_fatal_error ( Twine ( <STR_LIT> + StringRef ( RegName ) + <STR_LIT> ) ) ; BitVector ReservedRegs = Subtarget . getRegisterInfo ( ) -> getReservedRegs (


<s> Parser . eatToEndOfStatement ( ) ; return false ; } <ISA_LIT>Operand & FuncRegOpnd = static_cast < <ISA_LIT>Operand & > ( * TmpReg [ <NUM_LIT> ] ) ; if ( ! FuncRegOpnd . isGPRAsmReg ( ) ) { reportParseError ( FuncRegOpnd . getStartLoc ( ) , <STR_LIT> ) ; Parser . eatToEndOfStatement ( ) ; return false ; } FuncReg = FuncRegOpnd . getGPR32Reg ( ) ; TmpReg . clear ( ) ; if ( ! eatComma ( <STR_LIT> ) ) return true ; ResTy = parseAnyRegister ( TmpReg ) ; if ( ResTy == MatchOperand_NoMatch ) { const AsmToken & Tok = Parser . getTok ( ) ; if ( Tok . is ( AsmToken :: Integer ) ) { Save = Tok . getIntVal ( ) ; SaveIsReg = false ; Parser . Lex ( ) ; } else { reportParseError ( <STR_LIT> ) ; Parser . eatToEndOfStatement ( ) ; return false ; } } else { <ISA_LIT>Operand & SaveOpnd = static_cast < <ISA_LIT>Operand & > ( * TmpReg [ <NUM_LIT> ] ) ; if ( ! SaveOpnd . isGPRAsmReg ( ) ) { reportParseError ( SaveOpnd . getStartLoc ( ) , <STR_LIT> ) ; Parser . eatToEndOfStatement ( ) ; return false ; } Save = SaveOpnd . getGPR32Reg ( ) ; } if ( ! eatComma ( <STR_LIT> ) ) return true ; StringRef Name ; if ( Parser . parseIdentifier ( Name ) ) reportParseError ( <STR_LIT> ) ; MCSymbol * Sym = getContext ( ) . GetOrCreateSymbol ( Name ) ; getTargetStreamer ( ) . emitDirectiveCpsetup ( FuncReg , Save , * Sym , SaveIsReg ) ; return


<s> default : break ; case MCFragment :: FT_Align : { auto Size = Asm . computeFragmentSize ( Layout , J ) ; for ( auto K = J . getIterator ( ) ; K != Fragments . begin ( ) && Size >= HEXAGON_PACKET_SIZE ; ) { -- K ; switch ( K -> getKind ( ) ) { default : break ; case MCFragment :: FT_Align : { Size = <NUM_LIT> ; break ; } case MCFragment :: FT_Relaxable : { auto & RF = cast < MCRelaxableFragment > ( * K ) ; auto & Inst = const_cast < MCInst & > ( RF . getInst ( ) ) ; while ( Size > <NUM_LIT> && <ISA_LIT>MCInstrInfo :: bundleSize ( Inst ) < <NUM_LIT> ) { MCInst * Nop = new ( Asm . getContext ( ) ) MCInst ; Nop -> setOpcode ( <STR_LIT> ) ; Inst . addOperand ( MCOperand :: createInst ( Nop ) ) ; Size -=


<s> case <STR_LIT> : case <STR_LIT> : { SDValue InFlag = Node -> getOperand ( <NUM_LIT> ) , CmpLHS ; unsigned Opc = InFlag . getOpcode ( ) ; ( void ) Opc ; assert ( ( ( Opc == <STR_LIT> || Opc == <STR_LIT> ) || ( Opc == <STR_LIT> || Opc == <STR_LIT> ) ) && <STR_LIT> ) ; unsigned MOp ; if ( Opcode == <STR_LIT> ) { CmpLHS = InFlag . getValue ( <NUM_LIT> ) ; MOp = <STR_LIT> ; } else { CmpLHS = InFlag . getOperand ( <NUM_LIT> ) ; MOp = <STR_LIT> ; } SDValue Ops [ ] = { CmpLHS , InFlag . getOperand ( <NUM_LIT> ) } ; SDValue LHS = Node -> getOperand ( <NUM_LIT> ) ; SDValue RHS = Node -> getOperand ( <NUM_LIT> ) ; EVT VT = LHS . getValueType ( ) ; unsigned Sltu_op = <STR_LIT> ; SDNode * Carry = CurDAG -> getMachineNode ( Sltu_op , DL , VT , Ops ) ; unsigned Addu_op = <STR_LIT> ; SDNode * AddCarry = CurDAG -> getMachineNode ( Addu_op , DL , VT , SDValue ( Carry , <NUM_LIT> ) , RHS ) ; SDNode * Result = CurDAG -> SelectNodeTo ( Node , MOp , VT , <STR_LIT> , LHS , SDValue ( AddCarry , <NUM_LIT> ) ) ; return std :: make_pair ( true ,


<s> const TargetFrameLowering * TFI = MF -> getTarget ( ) .


<s> unsigned getInstSizeInBytes ( const MachineInstr & MI ) const override { return <NUM_LIT>


<s> unsigned int precision = and_val . get_precision ( ) ; unsigned HOST_WIDE_INT mask = <NUM_LIT> ; for ( unsigned int shift = <NUM_LIT> ; shift < precision ; shift += <NUM_LIT> ) { if ( and_val == ~ mask && ( ior_val & mask ) == ior_val ) return shift ; mask <<= <NUM_LIT>


<s> } else if ( const GEPOperator * GEP = dyn_cast < GEPOperator > ( V ) ) { V = GEP -> getPointerOperand ( ) -> stripPointerCasts ( ) ; continue ; } else if ( const PHINode * PN = dyn_cast < PHINode > ( V ) ) { if ( V != V2 && processed . find ( V ) != processed . end ( ) ) return NULL ; processed . insert ( PN ) ; const Value * common = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> ; i != PN -> getNumIncomingValues ( ) ; ++ i ) { const Value * pv = PN -> getIncomingValue ( i ) ; const Value * base = skipPointerTransfer ( pv , processed ) ; if ( base ) { if ( common == <NUM_LIT> ) common = base ; else if ( common != base ) return PN ; } } if ( common == <NUM_LIT> ) return PN ; V = common


<s> CT [ <NUM_LIT> ] = <NUM_LIT> ; } if ( TextureType == TEXTURE_CUBE_ARRAY || TextureType == TEXTURE_SHADOWCUBE_ARRAY ) CT [ <NUM_LIT> ] = <NUM_LIT> ; if ( TextureType == TEXTURE_1D_ARRAY || TextureType == TEXTURE_SHADOW1D_ARRAY ) { if ( hasLOD && useShadowVariant ) { CT [ <NUM_LIT> ] = <NUM_LIT> ; } else { CT [ <NUM_LIT> ] = <NUM_LIT> ; SrcSelect [ <NUM_LIT> ] = <NUM_LIT> ; } } else if ( TextureType == TEXTURE_2D_ARRAY || TextureType == TEXTURE_SHADOW2D_ARRAY ) { CT [ <NUM_LIT> ] = <NUM_LIT> ; } if ( ( TextureType == TEXTURE_SHADOW1D || TextureType == TEXTURE_SHADOW2D || TextureType == TEXTURE_SHADOWRECT || TextureType == TEXTURE_SHADOW1D_ARRAY ) && ! ( hasLOD && useShadowVariant

) ) SrcSelect [ <NUM_LIT> ] = <NUM_LIT> ;


<s> -- I ; while ( I -> isDebugValue ( ) ) { if ( I == MBB . begin ( ) ) return <NUM_LIT> ; -- I ; } if ( ! IsBRU ( I -> getOpcode ( ) ) && ! IsCondBranch ( I -> getOpcode ( ) ) ) return <NUM_LIT> ; I -> eraseFromParent (


<s> unsigned x86cc = ( cc0 == <STR_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; if ( Subtarget . hasAVX512 ( ) ) { SDValue FSetCC = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , CMP00 , CMP01 , DAG . getConstant ( x86cc , DL , <STR_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , DL , N -> getSimpleValueType ( <NUM_LIT> ) , FSetCC , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; } SDValue OnesOrZeroesF = DAG . getNode ( <STR_LIT> , DL , CMP00 . getValueType ( ) , CMP00 , CMP01 , DAG . getConstant ( x86cc , DL , <STR_LIT> ) ) ; bool is64BitFP = ( CMP00 . getValueType ( ) == <STR_LIT> ) ; MVT IntVT = is64BitFP ? <STR_LIT> : <STR_LIT> ; if ( is64BitFP && ! Subtarget . is64Bit ( ) ) { SDValue Vector64 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , OnesOrZeroesF ) ; SDValue Vector32 = DAG . getBitcast ( <STR_LIT> , Vector64 ) ; OnesOrZeroesF = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Vector32 , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; IntVT = <STR_LIT> ; } SDValue OnesOrZeroesI = DAG . getBitcast ( IntVT ,


<s> if ( Elt . getOpcode ( ) != <STR_LIT> || ! isa < ConstantSDNode > ( Elt . getOperand ( <NUM_LIT> ) ) ) return SDValue ( ) ; MVT VT = Elt . getOperand ( <NUM_LIT> ) . getSimpleValueType ( ) ; if ( ! VT . is128BitVector ( ) ) return SDValue ( ) ; if ( ! FirstNonZero . getNode ( ) ) { FirstNonZero = Elt ; FirstNonZeroIdx = i ; } } assert ( FirstNonZero . getNode ( ) && <STR_LIT> ) ; SDValue V1 = FirstNonZero . getOperand ( <NUM_LIT> ) ; MVT VT = V1 . getSimpleValueType ( ) ; SDValue Elt ; unsigned EltMaskIdx , EltIdx ; int Mask [ <NUM_LIT> ] ; for ( EltIdx = <NUM_LIT> ; EltIdx < <NUM_LIT> ; ++ EltIdx ) { if ( Zeroable [ EltIdx ] ) { Mask [ EltIdx ] = EltIdx + <NUM_LIT> ; continue ; } Elt = Op -> getOperand ( EltIdx ) ; EltMaskIdx = cast < ConstantSDNode > ( Elt . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; if ( Elt . getOperand ( <NUM_LIT> ) != V1 || EltMaskIdx != EltIdx ) break ; Mask [ EltIdx ] = EltIdx ; } if ( EltIdx == <NUM_LIT> ) { SDValue VZero = getZeroVector ( VT , Subtarget , DAG , SDLoc ( Op ) ) ; if ( V1 . getSimpleValueType ( ) != VT ) V1 = DAG . getNode ( <STR_LIT> , SDLoc ( V1 ) , VT , V1 ) ; return DAG . getVectorShuffle ( VT , SDLoc ( V1 ) , V1 , VZero , & Mask [ <NUM_LIT> ] ) ; } if ( ! Subtarget -> hasSSE41 ( ) ) return SDValue ( ) ; SDValue V2 = Elt . getOperand ( <NUM_LIT> ) ; if ( Elt == FirstNonZero && EltIdx == FirstNonZeroIdx ) V1 = SDValue ( ) ; bool CanFold = true ; for ( unsigned i = EltIdx + <NUM_LIT> ; i < <NUM_LIT> && CanFold ; ++ i ) { if ( Zeroable [ i ] ) continue ; SDValue Current = Op -> getOperand ( i ) ; SDValue SrcVector = Current -> getOperand ( <NUM_LIT> ) ; if ( ! V1 . getNode


<s> void <ISA_LIT>GNULDBackend :: emitRelocation ( llvm :: ELF :: Elf64_Rela & pRel , Relocation :: Type pType , uint32_t pSymIdx , uint64_t pOffset , int64_t pAddend ) const { uint64_t r_info = mcld :: bswap32 ( pType ) ; r_info <<= <NUM_LIT> ; r_info |= pSymIdx ; pRel . r_info = r_info


<s> virtual const <ISA_LIT>InstrInfo * getInstrInfo ( ) const { return &


<s> return __a * __aarch64_vget_lane_any (


<s> Error ( S , <STR_LIT> ) ; return MatchOperand_ParseFail ; } StringRef Tok = Parser . getTok ( ) . getIdentifier ( ) ; if ( Tok [ <NUM_LIT> ] != 'c' && Tok [ <NUM_LIT> ] != 'C' ) { Error ( S , <STR_LIT> ) ; return MatchOperand_ParseFail ; } uint32_t CRNum ; bool BadNum = Tok . drop_front ( ) . getAsInteger ( <NUM_LIT> , CRNum ) ; if ( BadNum || CRNum > <NUM_LIT> ) { Error ( S , <STR_LIT> ) ; return MatchOperand_ParseFail ; } Parser . Lex (


<s> if ( flag_pic == <NUM_LIT> && ( symbol_mentioned_p ( x ) || label_mentioned_p ( x ) ) && !

( TARGET_PIC_DATA_TEXT_REL && call_insn_operand ( x , VOIDmode ) ) ) return <NUM_LIT> ;


<s> bool invert = false ; op0 = force_reg ( mode , op0 ) ; if ( ( code != EQ && code != NE && ( op1 != const0_rtx || code == GTU || code == GEU || code == LTU || code == LEU ) ) || ( mode == DImode && op1 != const0_rtx ) || ( TARGET_SH2E && GET_MODE_CLASS ( mode ) == MODE_FLOAT ) ) op1 = force_reg ( mode , op1 ) ; if ( GET_MODE_CLASS ( mode ) == MODE_FLOAT ) { if ( code == LT || code == LE ) { std :: swap ( op0 , op1 ) ; code = swap_condition ( code ) ; } if ( code == GE ) { if ( TARGET_IEEE ) { lab = gen_label_rtx ( ) ; sh_emit_scc_to_t ( EQ , op0 , op1 ) ; emit_jump_insn ( gen_branch_true ( lab ) ) ; code = GT ; } else { code = LT ; invert = true ; } } } if ( code == NE ) { code =


<s> return __builtin_mve_vmaxnmvq_fv4sf ( __a ,


<s> switch ( IID ) { default : return false ; case <STR_LIT> : SelectTexSurfHandle ( N ) ; return


<s> FpABI = Value ; Is32BitABI = IsABI32Bit


<s> const TargetRegisterInfo * RegInfo = MF . getSubtarget ( ) . getRegisterInfo ( ) ; const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; return MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) || RegInfo -> needsStackRealignment ( MF )

|| MFI . hasVarSizedObjects ( ) || MFI . isFrameAddressTaken ( ) ;


<s> return ( __m512d ) __builtin_ia32_broadcastsd512 ( ( __v2df ) __A ,


<s> if ( Node -> isMachineOpcode ( ) ) { LLVM_DEBUG ( errs ( ) << <STR_LIT> ; Node -> dump ( CurDAG ) ; errs ( ) << <STR_LIT> ) ; Node -> setNodeId ( - <NUM_LIT> ) ; return ; } switch ( Node -> getOpcode ( ) ) { default : break ; case <STR_LIT> : { SmallVector < SDValue , <NUM_LIT> > Ops ( Node -> op_begin ( ) , Node -> op_end ( ) ) ; if ( Ops . size ( ) <= <NUM_LIT> ) { SDNode * Res = CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> ) ; ReplaceNode ( Node , Res ) ; return ; } SDNode * Res = CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , Ops ) ; ReplaceNode ( Node , Res ) ; return ; } case <STR_LIT> : { SmallVector < SDValue , <NUM_LIT> > Ops ( Node -> op_begin ( ) , Node -> op_end ( ) ) ; SDNode * Res = CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , Ops ) ; ReplaceNode ( Node , Res ) ; return ; } case <STR_LIT> : case <STR_LIT> : { bool DictCall = ( Node -> getOpcode ( ) == <STR_LIT> ) ; SmallVector < SDValue , <NUM_LIT> > Ops ( std :: next ( Node -> op_begin ( ) ) , Node -> op_end ( ) ) ; assert ( Ops [ <NUM_LIT> ] . getOpcode ( ) == <STR_LIT> ) ; Ops [ <NUM_LIT> ] = Ops [ <NUM_LIT> ] . getOperand (


<s> if ( ctx != NULL_TREE && ! TRANSLATION_UNIT_WARN_EMPTY_P ( ctx ) ) return ; if ( int_size_in_bytes ( type ) == <NUM_LIT> ) return ; warning ( OPT_Wabi , <STR_LIT>


<s> MachinePointerInfo PtrInfo = MachinePointerInfo :: getFixedStack ( * MF , FrameIndex ) ; MachineMemOperand * MMO = MF -> getMachineMemOperand ( PtrInfo , MachineMemOperand :: MOLoad , Size , Align ) ; if ( RI . isSGPRClass ( RC ) ) { MFI -> setHasSpilledSGPRs ( ) ; assert ( DestReg != <STR_LIT> && <STR_LIT> ) ; const MCInstrDesc & OpDesc = get ( getSGPRSpillRestoreOpcode ( SpillSize ) ) ; if ( Register :: isVirtualRegister ( DestReg ) && SpillSize == <NUM_LIT> ) { MachineRegisterInfo & MRI = MF -> getRegInfo ( ) ; MRI . constrainRegClass ( DestReg , & <STR_LIT> ) ; } if ( RI . spillSGPRToVGPR ( ) ) FrameInfo . setStackID

( FrameIndex , TargetStackID :: SGPRSpill ) ;


<s> const AsmToken & Tok = Parser . getTok ( ) ; bool Hash = Tok . is ( AsmToken :: Hash ) ; if ( Hash || Tok . is ( AsmToken :: Integer ) ) { if ( Hash ) Parser . Lex ( ) ; const MCExpr * ImmVal ; if ( getParser ( ) . parseExpression ( ImmVal ) ) return MatchOperand_ParseFail ; const MCConstantExpr * MCE = dyn_cast < MCConstantExpr > ( ImmVal ) ; if ( ! MCE ) { TokError ( <STR_LIT> ) ; return MatchOperand_ParseFail ; } unsigned prfop = MCE -> getValue ( ) ; if ( prfop > <NUM_LIT> ) { TokError ( <STR_LIT> )


<s> std :: string CPU = ! CPUAttr . hasAttribute ( Attribute :: None ) ? CPUAttr . getValueAsString ( ) . str ( ) : TargetCPU ; std :: string FS = ! FSAttr . hasAttribute ( Attribute :: None ) ? FSAttr . getValueAsString ( ) . str ( ) : TargetFS ; auto & I = SubtargetMap [ CPU + FS ] ; if ( ! I ) { resetTargetOptions ( F ) ; I = std :: make_unique < <ISA_LIT>Subtarget > ( TargetTriple , CPU , FS


<s> unsigned BlockSize = <NUM_LIT> ; for ( MachineBasicBlock :: iterator MBBI = MBB -> begin ( ) , EE = MBB -> end ( ) ; MBBI != EE ; ++ MBBI ) BlockSize += TII -> GetInstSizeInBytes ( MBBI ) ; BlockSizes [ MBB -> getNumber ( ) ] = BlockSize ; FuncSize += BlockSize ; } if ( FuncSize < ( <NUM_LIT> << <NUM_LIT> ) ) { BlockSizes . clear ( ) ; return false ; } bool MadeChange = true ; bool EverMadeChange = false ; while ( MadeChange ) { MadeChange = false ; for ( MachineFunction :: iterator MFI = Fn . begin ( ) , E = Fn . end ( ) ; MFI != E ; ++ MFI ) { MachineBasicBlock & MBB = * MFI ; unsigned MBBStartOffset = <NUM_LIT> ; for ( MachineBasicBlock :: iterator I = MBB . begin ( ) , E = MBB . end ( ) ; I != E ; ++ I ) { if ( ( I -> getOpcode ( ) != <STR_LIT> || I -> getOperand ( <NUM_LIT> ) . isImm ( ) ) && I -> getOpcode ( ) != <STR_LIT> ) { MBBStartOffset += TII -> GetInstSizeInBytes ( I ) ; continue ; } MachineBasicBlock * Dest = I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; int BranchSize ; if ( Dest -> getNumber ( ) <= MBB . getNumber ( ) ) { BranchSize = MBBStartOffset ; for ( unsigned i = Dest -> getNumber ( ) , e = MBB . getNumber ( ) ; i != e ; ++ i ) BranchSize += BlockSizes [ i ] ; } else { BranchSize = - MBBStartOffset ; for ( unsigned i = MBB . getNumber ( ) , e = Dest -> getNumber ( ) ; i != e ; ++ i ) BranchSize += BlockSizes [ i ] ; } if ( isInt < <NUM_LIT> > ( BranchSize ) ) { MBBStartOffset += <NUM_LIT> ; continue ; } unsigned NewSize ; MachineInstr * OldBranch = I ; DebugLoc dl = OldBranch -> getDebugLoc ( ) ; if ( I -> getOpcode ( ) == <STR_LIT> ) { NewSize = <NUM_LIT> ; } else { SmallVector < MachineOperand , <NUM_LIT> > Cond ; Cond . push_back ( I -> getOperand ( <NUM_LIT> ) ) ; TII -> ReverseBranchCondition ( Cond ) ; BuildMI ( MBB , I , dl , TII -> get ( <STR_LIT> )

) . addImm ( <NUM_LIT> ) . addOperand ( Cond [ <NUM_LIT> ] ) ;


<s> machine_mode mode = TYPE_MODE ( char_type_node ) ; rtx addr = expand_expr ( address , NULL_RTX , VOIDmode , EXPAND_NORMAL ) ; rtx mem = gen_rtx_MEM ( BLKmode , addr ) ; rtx value = gen_int_mode ( <NUM_LIT> , mode ) ; for ( i = FIRST_SPE_HIGH_REGNO ; i < LAST_SPE_HIGH_REGNO + <NUM_LIT> ; i ++ ) { int column = DWARF_REG_TO_UNWIND_COLUMN ( DWARF2_FRAME_REG_OUT ( DWARF_FRAME_REGNUM ( i ) , true ) ) ; HOST_WIDE_INT offset = column * GET_MODE_SIZE ( mode ) ; emit_move_insn ( adjust_address ( mem , mode , offset ) , value ) ; } } if ( TARGET_MACHO && ! TARGET_ALTIVEC ) { int i ; machine_mode mode = TYPE_MODE ( char_type_node ) ; rtx addr = expand_expr ( address , NULL_RTX , VOIDmode , EXPAND_NORMAL ) ; rtx mem = gen_rtx_MEM ( BLKmode ,


<s> unsigned getBankedReg ( ) const { assert ( Kind == k_BankedReg && <STR_LIT>


<s> else if ( ! TLBI -> haveFeatures ( getSTI ( ) . getFeatureBits ( ) ) ) { std :: string Str ( <STR_LIT> + std :: string ( TLBI -> Name ) + <STR_LIT> ) ; setRequiredFeatureString ( TLBI -> getRequiredFeatures ( ) , Str ) ; return TokError ( Str . c_str ( ) ) ; } createSysAlias ( TLBI -> Encoding , Operands , S ) ; } else if ( Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> ) { const <STR_LIT> * PRCTX = <STR_LIT> ( Op ) ; if ( ! PRCTX ) return TokError ( <STR_LIT> ) ; else if ( ! PRCTX -> haveFeatures ( getSTI ( ) . getFeatureBits ( ) ) ) { std :: string Str ( Mnemonic . upper ( ) + std :: string ( PRCTX -> Name ) + <STR_LIT> ) ; setRequiredFeatureString ( PRCTX -> getRequiredFeatures ( ) , Str ) ; return TokError ( Str . c_str ( ) ) ; } uint16_t PRCTX_Op2 = Mnemonic == <STR_LIT> ? <NUM_LIT> : Mnemonic == <STR_LIT> ? <NUM_LIT> : Mnemonic == <STR_LIT> ? <NUM_LIT> : <NUM_LIT> ; assert ( PRCTX_Op2 && <STR_LIT> ) ; createSysAlias ( PRCTX -> Encoding << <NUM_LIT> | PRCTX_Op2 , Operands , S ) ; } Parser . Lex ( ) ; bool ExpectRegister = ( Op . lower ( ) . find ( <STR_LIT> ) == StringRef :: npos ) ; bool HasRegister = false ; if ( parseOptionalToken ( AsmToken :: Comma


<s> if ( AddrSpace == <NUM_LIT> ) AM . Segment = CurDAG -> getRegister ( <STR_LIT> , <STR_LIT> ) ; if ( AddrSpace == <NUM_LIT> ) AM . Segment = CurDAG -> getRegister ( <STR_LIT> , <STR_LIT> ) ; if ( AddrSpace == <NUM_LIT> ) AM . Segment = CurDAG -> getRegister ( <STR_LIT> , <STR_LIT> ) ; SDLoc DL ( N ) ; Base = Mgs -> getBasePtr ( ) ; Index = Mgs -> getIndex ( ) ; unsigned ScalarSize = Mgs -> getValue ( ) . getScalarValueSizeInBits ( ) ; Scale = getI8Imm ( ScalarSize / <NUM_LIT> , DL ) ; if ( isa < ConstantSDNode > ( Base ) ) { assert ( cast < ConstantSDNode > ( Base ) -> isNullValue ( ) && <STR_LIT> ) ; Scale = getI8Imm ( <NUM_LIT> , DL ) ; Base = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; } if ( AM . Segment . getNode ( ) )


<s> FCmp32Libcalls [ CmpInst :: FCMP_OEQ ] = { { RTLIB :: OEQ_F32 , CmpInst :: ICMP_EQ } } ; FCmp32Libcalls [ CmpInst :: FCMP_OGE ] = { { RTLIB :: OGE_F32 , CmpInst :: ICMP_SGE } } ; FCmp32Libcalls [ CmpInst :: FCMP_OGT ] = { { RTLIB :: OGT_F32 , CmpInst :: ICMP_SGT } } ; FCmp32Libcalls [ CmpInst :: FCMP_OLE ] = { { RTLIB :: OLE_F32 , CmpInst :: ICMP_SLE } } ; FCmp32Libcalls [ CmpInst :: FCMP_OLT ] = { { RTLIB :: OLT_F32 , CmpInst :: ICMP_SLT } } ; FCmp32Libcalls [ CmpInst :: FCMP_ORD ] = { { RTLIB :: UO_F32 , CmpInst :: ICMP_EQ } } ; FCmp32Libcalls [ CmpInst :: FCMP_UGE ] = { { RTLIB :: OLT_F32 , CmpInst :: ICMP_SGE } } ; FCmp32Libcalls [ CmpInst :: FCMP_UGT ] = { { RTLIB :: OLE_F32 , CmpInst :: ICMP_SGT } } ; FCmp32Libcalls [ CmpInst :: FCMP_ULE ] = { { RTLIB :: OGT_F32 , CmpInst :: ICMP_SLE } } ; FCmp32Libcalls [ CmpInst :: FCMP_ULT ] = { { RTLIB :: OGE_F32 , CmpInst :: ICMP_SLT } } ; FCmp32Libcalls [ CmpInst :: FCMP_UNE ] = { { RTLIB :: UNE_F32 , CmpInst :: ICMP_NE } } ; FCmp32Libcalls [ CmpInst :: FCMP_UNO ] = { { RTLIB


<s> const MCOperand & IndexReg = MI -> getOperand ( Op + <NUM_LIT> ) ; const MCOperand & DispSpec = MI -> getOperand ( Op + <NUM_LIT> ) ; const MCOperand & SegReg = MI -> getOperand ( Op + <NUM_LIT> ) ; if ( SegReg . getReg ( ) ) { printOperand ( MI , Op + <NUM_LIT> , O ) ; O << ':' ; } if ( DispSpec . isImm ( ) ) { int64_t DispVal = DispSpec . getImm ( ) ; if ( DispVal || ( ! IndexReg . getReg ( ) && ! BaseReg . getReg ( ) ) ) O << DispVal ; }


<s> drop_front ( mangledName , N - <NUM_LIT> ) ; return true ; } return


<s> int i , k ; rtx rvec [ GP_ARG_NUM_REG + <NUM_LIT> ] ; if ( align_words >= GP_ARG_NUM_REG ) return NULL_RTX ; n_units = rs6000_arg_size ( mode , type ) ; if ( n_units == <NUM_LIT> || ( n_units == <NUM_LIT> && mode != BLKmode ) ) return gen_rtx_REG

( mode , GP_ARG_MIN_REG + align_words ) ;


<s> if ( ! TII -> isStridedAccess ( MI ) ) continue ; Optional < LoadInfo > OptLdI = getLoadInfo ( MI ) ; if ( ! OptLdI ) continue ; LoadInfo LdI = * OptLdI ; Optional < unsigned > OptOldTag = getTag ( TRI , MI , LdI ) ; if ( ! OptOldTag ) continue ; auto & OldCollisions = TagMap [ * OptOldTag ] ; if ( OldCollisions . size ( ) <= <NUM_LIT> ) continue ; bool Fixed = false ; DEBUG ( dbgs ( ) << <STR_LIT> << MI ) ; if ( ! DebugCounter :: shouldExecute ( FixCounter ) ) { DEBUG ( dbgs ( ) << <STR_LIT> << MI ) ; continue ; } for ( unsigned OpI = <NUM_LIT> , OpE = MI . getNumOperands ( ) ; OpI < OpE ; ++ OpI ) { if ( OpI == static_cast < unsigned > ( LdI . BaseRegIdx ) ) continue ; MachineOperand & MO = MI . getOperand ( OpI ) ; if ( MO . isReg ( ) && MO . readsReg ( ) ) LR . addReg ( MO . getReg ( ) ) ; } for ( unsigned ScratchReg : <STR_LIT> ) { if ( ! LR . available ( ScratchReg ) || MRI . isReserved ( ScratchReg ) ) continue ; LoadInfo NewLdI ( LdI ) ; NewLdI . BaseReg = ScratchReg ; unsigned NewTag = * getTag ( TRI , MI , NewLdI ) ; if ( TagMap . count ( NewTag ) ) continue ; DEBUG ( dbgs ( ) << <STR_LIT> << printReg ( ScratchReg , TRI ) << '\n' ) ; DebugLoc DL = MI . getDebugLoc ( ) ; BuildMI ( * MBB , & MI , DL , TII -> get ( <STR_LIT> ) , ScratchReg ) . addReg ( <STR_LIT> ) . addReg ( LdI . BaseReg ) . addImm ( <NUM_LIT> ) ; MachineOperand & BaseOpnd = MI . getOperand ( LdI . BaseRegIdx ) ; BaseOpnd . setReg


<s> const LLT P2 = LLT :: pointer ( <NUM_LIT> , <NUM_LIT> ) ; setAction ( { G_CONSTANT , S64 } , Legal ) ; setAction ( { G_GEP , P1 } , Legal ) ; setAction ( { G_GEP , P2 } , Legal ) ; setAction ( { G_GEP , <NUM_LIT> , S64 } , Legal ) ; setAction ( { G_LOAD , P1 } , Legal ) ; setAction ( { G_LOAD , P2 } , Legal ) ; setAction ( { G_LOAD , S32 } , Legal ) ; setAction ( { G_LOAD , <NUM_LIT> , P1 } , Legal ) ; setAction ( { G_LOAD , <NUM_LIT> , P2 } , Legal ) ; setAction ( { G_STORE , S32 } , Legal ) ; setAction ( { G_STORE , <NUM_LIT> , P1 } , Legal ) ; setAction ( { G_GEP ,


<s> if ( GET_CODE ( op ) == CONST_INT && CONST_OK_FOR_LETTER_P ( INTVAL ( op ) , 'M' )


<s> <ISA_LIT>Exception * getParentException ( ) const { return


<s> return ( GET_CODE ( x ) == LABEL_REF || GET_CODE ( x ) == SYMBOL_REF || GET_CODE ( x ) == CONST_INT || GET_CODE ( x

) == CONST || GET_CODE ( x ) == HIGH ) ;


<s> bool <ISA_LIT>TargetLowering :: isOffsetFoldingLegal ( const GlobalAddressSDNode * GA ) const { return


<s> virtual const <ISA_LIT>RegisterInfo & getRegisterInfo ( ) const { return


<s> static tree rs6000_builtin_mask_for_load ( void ) { if ( ( TARGET_ALTIVEC && ! TARGET_VSX ) || ( TARGET_VSX

&& ! TARGET_EFFICIENT_UNALIGNED_VSX ) ) return altivec_builtin_mask_for_load ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ! ForLoadFold ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> OS << <STR_LIT> << getVGPRNum ( ) ; if ( ST ) OS << <STR_LIT> << ST -> getOccupancyWithNumVGPRs ( getVGPRNum ( ) ) << ')' ; OS << <STR_LIT> << getSGPRNum ( ) ; if ( ST ) OS << <STR_LIT> << ST -> getOccupancyWithNumSGPRs ( getSGPRNum


<s> label_name = ( * targetm . strip_name_encoding ) ( ggc_strdup ( buf ) ) ; fun = gen_rtx_SYMBOL_REF ( Pmode , label_name ) ; emit_library_call ( init_one_libfunc ( RS6000_MCOUNT ) , <NUM_LIT> , VOIDmode , <NUM_LIT> , fun , Pmode ) ; } } else if ( DEFAULT_ABI == ABI_DARWIN ) { const char * mcount_name = RS6000_MCOUNT ; int caller_addr_regno = LINK_REGISTER_REGNUM ; current_function_uses_pic_offset_table = <NUM_LIT> ; if ( MACHOPIC_INDIRECT && current_function_uses_pic_offset_table ) caller_addr_regno =


<s> auto Where = llvm :: find_if ( PrologMBB , [ ] ( MachineInstr & MI ) { return MI . getOpcode ( ) == <STR_LIT> ; } ) ; if ( Where != PrologMBB . end ( ) ) { DebugLoc DL = PrologMBB . findDebugLoc ( Where ) ; emitStackProbeInline ( MF , PrologMBB , Where ,


<s> <ISA_LIT>Instr ( MCInstrInfo const & MCII , MCSubtargetInfo const & STI , MCInst const * id , MCInst const * Extender , unsigned s ) : ID ( id

) , Extender ( Extender ) , Core ( s ) , CVI ( MCII , STI , s , id ) { }


<s> unsigned <ISA_LIT>FastISel :: FastEmitInst_extractsubreg ( MVT RetVT , unsigned Op0 , bool Op0IsKill , uint32_t Idx ) { unsigned ResultReg = createResultReg ( TLI . getRegClassFor ( RetVT ) ) ; assert ( TargetRegisterInfo :: isVirtualRegister ( Op0 ) && <STR_LIT> ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: COPY ) , ResultReg ) . addReg ( Op0

, getKillRegState ( Op0IsKill ) , Idx ) ) ;


<s> if ( intoffset % BITS_PER_WORD != <NUM_LIT> ) mode = smallest_mode_for_size ( BITS_PER_WORD - intoffset % BITS_PER_WORD , MODE_INT ) ; else mode = word_mode ; intoffset /= BITS_PER_UNIT ; do { regno = parms -> regbase + this_slotno ; reg = gen_rtx_REG ( mode , regno ) ; XVECEXP ( parms -> ret , <NUM_LIT> , parms -> stack + parms -> nregs )

= gen_rtx_EXPR_LIST ( VOIDmode , reg , GEN_INT ( intoffset ) ) ;


<s> if ( empty ( M . debug_compile_units ( ) ) )


<s> explicit <ISA_LIT>AsmPrinter ( formatted_raw_ostream & O , TargetMachine & TM


<s> Ops [ NumOps ++ ] = MI -> getOperand ( Idx ) . getImm ( ) ; } const bool HasDstSel = NumOps > <NUM_LIT> && Mod == <STR_LIT> && MII . get ( MI -> getOpcode ( ) ) . TSFlags & <STR_LIT> ; if ( allOpsDefaultValue ( Ops , NumOps , Mod , HasDstSel ) ) return ; O << Name ; for ( int I = <NUM_LIT> ; I


<s> SmallVector < int , <NUM_LIT> > RepeatedMask ; if ( is128BitLaneRepeatedShuffleMask ( <STR_LIT> , Mask , RepeatedMask ) ) { SmallVector < int , <NUM_LIT> > PSHUFDMask ; scaleShuffleMask < int > ( <NUM_LIT> , RepeatedMask , PSHUFDMask ) ; return DAG . getBitcast ( <STR_LIT> , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getBitcast ( <STR_LIT> , V1 ) , getV4<ISA_LIT>ShuffleImm8ForMask ( PSHUFDMask , DL , DAG ) ) ) ; } return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , getV4<ISA_LIT>ShuffleImm8ForMask ( Mask , DL , DAG ) ) ; } if ( SDValue Shift = lowerVectorShuffleAsShift ( DL , <STR_LIT> , V1 , V2 , Mask , Zeroable , Subtarget , DAG ) ) return Shift ; if ( Subtarget . hasVLX ( ) ) { if ( SDValue Rotate = lowerVectorShuffleAsRotate ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return Rotate ; if ( SDValue V = lowerVectorShuffleToEXPAND ( DL , <STR_LIT> , Zeroable , Mask , V1 , V2 , DAG , Subtarget ) ) return V ; } if ( SDValue Rotate = lowerVectorShuffleAsByteRotate ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return Rotate ; if ( SDValue V = lowerVectorShuffleWithUNPCK ( DL , <STR_LIT> , Mask , V1 , V2


<s> static unsigned getScratchScaleFactor ( const GCNSubtarget &


<s> static MCTargetStreamer * create<ISA_LIT>ObjectTargetStreamer ( MCStreamer & S , const MCSubtargetInfo & STI ) { return new <ISA_LIT>TargetELFStreamer ( S


<s> auto * Mask = dyn_cast < ConstantSDNode > ( C . Op0 . getOperand ( <NUM_LIT> ) ) ; if ( ! Mask ) return ; KnownBits Known = DAG . computeKnownBits ( C . Op0 . getOperand ( <NUM_LIT> ) ) ; if ( ( ~ Known . Zero ) . getZExtValue ( ) & ~ Mask -> getZExtValue ( ) ) return ; C . Op0 = C . Op0 . getOperand (


<s> pointer release ( ) SPIMPL_NOEXCEPT { return ptr_ .


<s> MCInstrInfo * X = new MCInstrInfo ( ) ; Init<ISA_LIT>MCInstrInfo ( X


<s> SDValue StoreAddr = DAG . getNode ( <STR_LIT> , dl , PtrVT , DAG . getRegister ( <STR_LIT> , PtrVT ) , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ; Chain = DAG . getStore ( Chain , dl , Handler , StoreAddr , MachinePointerInfo ( ) ) ; Chain = DAG . getCopyToReg ( Chain


<s> if ( ! can_create_pseudo_p ( ) && ! df_regs_ever_live_p ( RS6000_PIC_OFFSET_TABLE_REGNUM ) ) df_set_regs_ever_live ( RS6000_PIC_OFFSET_TABLE_REGNUM , true ) ; crtl -> uses_pic_offset_table = <NUM_LIT> ; return


<s> static void ATTRIBUTE_UNUSED ix86_encode_section_info ( tree decl , rtx rtl , int first ) { default_encode_section_info ( decl , rtl


<s> if ( Op1 . getOpcode ( ) == <STR_LIT> ) std :: swap ( Op0 , Op1 ) ; if ( Op0 . getOpcode ( ) == <STR_LIT> ) { if ( ConstantSDNode * And00C = dyn_cast < ConstantSDNode > ( Op0 . getOperand ( <NUM_LIT> ) ) ) if ( And00C -> getZExtValue ( ) == <NUM_LIT> ) { unsigned BitWidth = Op0 . getValueSizeInBits ( ) ; unsigned AndBitWidth = And . getValueSizeInBits ( ) ; if ( BitWidth > AndBitWidth ) { APInt Zeros , Ones ; DAG . ComputeMaskedBits ( Op0 , Zeros , Ones ) ; if ( Zeros . countLeadingOnes ( ) < BitWidth - AndBitWidth ) return SDValue ( ) ; } LHS = Op1 ; RHS = Op0 . getOperand ( <NUM_LIT> ) ; } } else if ( Op1 . getOpcode ( ) == <STR_LIT> ) { ConstantSDNode * AndRHS = cast < ConstantSDNode > ( Op1 ) ; uint64_t AndRHSVal = AndRHS -> getZExtValue ( ) ; SDValue AndLHS = Op0 ; if ( AndRHSVal == <NUM_LIT> && AndLHS . getOpcode ( ) == <STR_LIT> ) { LHS = AndLHS . getOperand ( <NUM_LIT> ) ; RHS = AndLHS . getOperand ( <NUM_LIT> ) ; } if ( ! isUInt < <NUM_LIT> > ( AndRHSVal ) && isPowerOf2_64 ( AndRHSVal ) ) { LHS = AndLHS ; RHS = DAG . getConstant ( Log2_64_Ceil ( AndRHSVal ) , LHS . getValueType


<s> CommentString = <STR_LIT> ; AscizDirective = <STR_LIT> ; HiddenVisibilityAttr = MCSA_Invalid ; HiddenDeclarationVisibilityAttr = MCSA_Invalid ; ProtectedVisibilityAttr = MCSA_Invalid ; ExceptionsType = ExceptionHandling :: DwarfCFI ; DwarfRegNumForCFI = true


<s> void <ISA_LIT>MIPeephole :: initialize ( MachineFunction & MFParm ) { MF = & MFParm ; MRI = & MF -> getRegInfo ( ) ; MDT = & getAnalysis < MachineDominatorTree > ( ) ; TII = MF -> getSubtarget < <ISA_LIT>Subtarget > ( ) .


<s> } return false ; } bool Poz1 = ( Props1 & P :: PosOrZero ) , Poz2 = ( Props2 & P :: PosOrZero ) ; bool Nez1 = ( Props1 & P :: NegOrZero ) , Nez2 = ( Props2 & P :: NegOrZero ) ; if ( Nez1 && Poz2 ) { if ( NonZero1 || NonZero2 ) { Result = ( Cmp & Comparison :: L ) ; return true ; } if ( ( Cmp & Comparison :: EQ ) && ( Cmp & Comparison :: L ) ) return ( Result = true ) ; } if ( Poz1 && Nez2 ) { if ( NonZero1 || NonZero2 ) { Result = ( Cmp & Comparison :: G ) ; return true


<s> static MCInstPrinter * create<ISA_LIT>MCInstPrinter ( const Triple & , unsigned SyntaxVariant , const MCAsmInfo & MAI , const MCInstrInfo & MII , const


<s> } return false ; } if ( Option == <STR_LIT> ) { getTargetStreamer ( ) . emitDirectiveOptionPic2 ( ) ; Parser . Lex ( ) ; if ( Parser . getTok ( ) . isNot ( AsmToken :: EndOfStatement ) ) { Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; Parser . eatToEndOfStatement ( ) ; } return


<s> if ( ( value < ( HOST_WIDEST_INT ) <NUM_LIT> && value > ( HOST_WIDEST_INT ) - <NUM_LIT> ) || ( value >= ( HOST_WIDEST_INT ) <NUM_LIT> && value <= ( HOST_WIDEST_INT ) <NUM_LIT> ) ) fprintf ( stream , <STR_LIT> , ( int ) value ) ; else if ( value > ( HOST_WIDEST_INT ) <NUM_LIT> && value < ( ( HOST_WIDEST_INT ) <NUM_LIT> << <NUM_LIT> ) * <NUM_LIT> ) fprintf ( stream , <STR_LIT> , ( unsigned int ) value ) ; else fprintf ( stream , hex_format , value ) ; if ( do_begin_end ) fprintf ( stream ,


<s> if ( parseToken ( AsmToken :: EndOfStatement , <STR_LIT> ) ) return true ; if ( Name == <STR_LIT> ) { enableArchExtFeature ( <STR_LIT> , ExtLoc ) ; enableArchExtFeature ( <STR_LIT> , ExtLoc ) ; } if ( enableArchExtFeature ( Name , ExtLoc ) ) return false ; return Error ( ExtLoc , <STR_LIT>


<s> return ( isGTorGE ( CC ) && ( ( K == LHS && K == TrueVal ) || ( K == RHS && K == FalseVal ) ) ) || ( isLTorLE ( CC ) && ( ( K

== RHS && K == TrueVal ) || ( K == LHS && K == FalseVal ) ) ) ;


<s> const unsigned SrcSize = SrcTy . getSizeInBits ( ) ; const unsigned DstSize = DstTy . getSizeInBits ( ) ; unsigned Offset = I . getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( Offset % <NUM_LIT> != <NUM_LIT> || DstSize > <NUM_LIT> ) return false ; const TargetRegisterClass * DstRC = TRI . getConstrainedRegClassForOperand ( I . getOperand ( <NUM_LIT> ) , * MRI ) ; if ( ! DstRC || ! RBI . constrainGenericRegister ( DstReg , * DstRC , * MRI ) ) return false ; const RegisterBank * SrcBank = RBI . getRegBank ( SrcReg , * MRI , TRI ) ; const TargetRegisterClass * SrcRC = TRI . getRegClassForSizeOnBank ( SrcSize , * SrcBank , * MRI ) ; if ( ! SrcRC ) return false ; unsigned SubReg = <ISA_LIT>RegisterInfo :: getSubRegFromChannel ( Offset / <NUM_LIT> , DstSize / <NUM_LIT> ) ; SrcRC = TRI . getSubClassWithSubReg ( SrcRC , SubReg ) ; if ( ! SrcRC ) return false ; SrcReg = constrainOperandRegClass ( * MF , TRI , * MRI , TII , RBI , I , * SrcRC , I . getOperand ( <NUM_LIT> ) ) ; const DebugLoc & DL = I . getDebugLoc ( ) ; BuildMI ( * BB , & I , DL , TII . get ( TargetOpcode :: COPY ) , DstReg ) . addReg ( SrcReg , <NUM_LIT> , SubReg ) ; I . eraseFromParent ( ) ; return true


<s> } const auto & AvailableXmms = ArgXMMs . slice ( NumXMMRegs ) ; if ( ! AvailableXmms . empty ( ) ) { Register AL = TheMachineFunction . addLiveIn ( <STR_LIT> , & <STR_LIT> ) ; ALVal = DAG . getCopyFromReg ( Chain , DL , AL , <STR_LIT> ) ; for ( MCPhysReg Reg : AvailableXmms ) { Register XMMReg = TheMachineFunction . addLiveIn ( Reg , & <STR_LIT> ) ; LiveXMMRegs . push_back ( DAG . getCopyFromReg ( Chain , DL , XMMReg , <STR_LIT> ) ) ; } } SmallVector < SDValue , <NUM_LIT> > MemOps ; SDValue RSFIN = DAG . getFrameIndex ( FuncInfo -> getRegSaveFrameIndex ( ) , TargLowering . getPointerTy ( DAG . getDataLayout ( ) ) ) ; unsigned Offset = FuncInfo -> getVarArgsGPOffset ( ) ; for ( SDValue Val : LiveGPRs ) { SDValue FIN = DAG . getNode ( <STR_LIT> , DL , TargLowering . getPointerTy ( DAG . getDataLayout ( ) ) , RSFIN , DAG . getIntPtrConstant ( Offset , DL ) ) ; SDValue Store = DAG . getStore ( Val . getValue ( <NUM_LIT> ) , DL , Val , FIN , MachinePointerInfo :: getFixedStack ( DAG . getMachineFunction ( ) , FuncInfo -> getRegSaveFrameIndex ( ) , Offset ) ) ; MemOps . push_back ( Store ) ; Offset += <NUM_LIT> ; } if ( ! LiveXMMRegs . empty ( ) ) { SmallVector < SDValue , <NUM_LIT> > SaveXMMOps ; SaveXMMOps . push_back ( Chain ) ; SaveXMMOps . push_back ( ALVal ) ; SaveXMMOps . push_back ( DAG . getTargetConstant ( FuncInfo -> getRegSaveFrameIndex ( ) , DL , <STR_LIT> ) ) ; SaveXMMOps . push_back ( DAG . getTargetConstant ( FuncInfo -> getVarArgsFPOffset ( ) , DL , <STR_LIT> ) ) ; llvm :: append_range ( SaveXMMOps


<s> DEBUG ( dbgs ( ) << <STR_LIT> << predReg << <STR_LIT> << guard << <STR_LIT> ) ; MachineBasicBlock :: iterator MI = MBB . getFirstTerminator ( ) ; DebugLoc DL ( MI -> getDebugLoc ( ) ) ; MachineInstr * DefMI ; if ( usePmov ) { DEBUG ( dbgs ( ) << <STR_LIT> ) ; DefMI = BuildMI ( MBB , MI , DL , TII -> get ( <STR_LIT> ) , predReg ) . addReg ( guard ) . addImm ( <NUM_LIT> ) . addOperand ( Cond [ <NUM_LIT> ] ) . addOperand ( Cond [ <NUM_LIT> ] ) ; }


<s> } if ( ! hasV60Ops ( ) ) return ; if ( DstInst -> isCopy ( ) ) Dep . setLatency ( <NUM_LIT> ) ; if ( ( DstInst -> isRegSequence ( ) || DstInst -> isCopy ( ) ) && Dst -> NumSuccs == <NUM_LIT> ) { Register DReg = DstInst -> getOperand ( <NUM_LIT> ) . getReg ( ) ; MachineInstr * DDst = Dst -> Succs [ <NUM_LIT> ] . getSUnit ( ) -> getInstr ( ) ; unsigned UseIdx = - <NUM_LIT> ; for ( unsigned OpNum = <NUM_LIT> ; OpNum < DDst -> getNumOperands ( ) ; OpNum ++ ) { const MachineOperand & MO = DDst -> getOperand ( OpNum ) ; if ( MO . isReg ( ) && MO . getReg ( ) && MO . isUse ( ) && MO . getReg ( ) == DReg ) { UseIdx = OpNum


<s> build_32_64 ( b , signature , group , MODE_u32base_index ,


<s> if ( GET_CODE ( op0 ) == REG && GR_REGNO_P ( REGNO ( op0 ) ) ) { rtx out [ <NUM_LIT> ] ; gcc_assert ( ! no_new_pseudos ) ; if ( ( GET_CODE ( operands [ <NUM_LIT> ] ) == SUBREG && GET_MODE ( SUBREG_REG ( operands [ <NUM_LIT> ] ) ) == TImode ) || ( GET_CODE ( operands [ <NUM_LIT> ] ) == REG && GR_REGNO_P ( REGNO ( operands [ <NUM_LIT> ] ) ) ) ) { rtx op1 = operands [ <NUM_LIT> ] ; if ( GET_CODE ( op1 ) == SUBREG ) op1 = SUBREG_REG ( op1 ) ; else op1 = gen_rtx_REG ( TImode , REGNO ( op1 ) ) ; emit_move_insn ( gen_rtx_REG ( TImode , REGNO ( op0 ) ) , op1 ) ; return true ; } if ( GET_CODE ( operands [ <NUM_LIT> ] ) == CONST_DOUBLE ) { emit_move_insn ( gen_rtx_REG ( DImode , REGNO ( op0 ) ) , operand_subword ( operands [ <NUM_LIT> ] , WORDS_BIG_ENDIAN , <NUM_LIT> , mode ) ) ; emit_move_insn ( gen_rtx_REG ( DImode , REGNO ( op0 ) + <NUM_LIT> ) , operand_subword ( operands [ <NUM_LIT> ] , ! WORDS_BIG_ENDIAN , <NUM_LIT> , mode ) ) ; return true ; } if ( register_operand ( operands [ <NUM_LIT> ] , mode ) ) operands [ <NUM_LIT> ] = spill_xfmode_rfmode_operand ( operands [ <NUM_LIT> ] , <NUM_LIT> , mode ) ; gcc_assert ( GET_CODE ( operands [ <NUM_LIT> ] ) == MEM ) ; out [ <NUM_LIT> ] = gen_rtx_REG ( DImode , REGNO ( op0 ) ) ; out [ <NUM_LIT> ] = gen_rtx_REG ( DImode , REGNO ( op0 ) + <NUM_LIT> ) ; emit_move_insn ( out [ <NUM_LIT> ] , adjust_address ( operands [ <NUM_LIT> ] , DImode , <NUM_LIT> ) ) ; emit_move_insn ( out [ <NUM_LIT> ] , adjust_address ( operands [


<s> bool hasFP ( const MachineFunction & MF ) const


<s> const <ISA_LIT>FrameLowering * getFrameLowering ( )


<s> Subtarget = & MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; IndirectTlsSegRefs = MF . getFunction ( ) . hasFnAttribute ( <STR_LIT> ) ; OptForSize = MF . getFunction ( ) . hasOptSize ( ) ; OptForMinSize = MF . getFunction ( ) . hasMinSize


<s> bool <ISA_LIT>TargetLowering :: needsCmpXchgNb ( const Type * MemType ) const { const <ISA_LIT>Subtarget & Subtarget = getTargetMachine ( ) . getSubtarget


<s> return ( poly8x8_t ) __builtin_neon_vreinterpretv8qiv8qi ( ( int8x8_t


<s> switch ( ExtraCode [ <NUM_LIT> ] ) { default : return AsmPrinter :: PrintAsmOperand ( MI , OpNum , AsmVariant , ExtraCode , O ) ; case 'c' : if ( ! MI -> getOperand ( OpNum ) . isImm ( ) ) return true ; O << MI -> getOperand ( OpNum ) . getImm ( ) ; return false ; case 'w' : return printModifiedGPRAsmOperand ( MI -> getOperand ( OpNum ) , TRI , <STR_LIT> , O ) ; case 'x' : return printModifiedGPRAsmOperand ( MI -> getOperand ( OpNum ) , TRI , <STR_LIT> , O ) ; case 'H' : case 'Q' : case 'R' : llvm_unreachable ( <STR_LIT> ) ; case 'b' : return printModifiedFPRAsmOperand ( MI -> getOperand ( OpNum ) , TRI , <STR_LIT> , O ) ; case 'h' : return printModifiedFPRAsmOperand ( MI -> getOperand ( OpNum ) , TRI , <STR_LIT> , O ) ; case 's' : return printModifiedFPRAsmOperand ( MI -> getOperand ( OpNum ) , TRI , <STR_LIT> , O ) ; case 'd' : return printModifiedFPRAsmOperand ( MI -> getOperand ( OpNum ) , TRI , <STR_LIT> , O ) ; case 'q' : return printModifiedFPRAsmOperand ( MI -> getOperand ( OpNum ) , TRI , <STR_LIT> , O ) ; case 'A' : return printSymbolicAddress ( MI -> getOperand ( OpNum ) ,


<s> auto MBBI = llvm :: find_if_not ( MBB . instrs ( ) , [ ] ( const MachineInstr & MI ) { return MI . isMetaInstruction ( ) ; } ) ; if ( IsFirstBB ) { if ( MBBI != MBB . instr_end ( ) && MBBI -> getOpcode ( ) == <STR_LIT> ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << MBB . getName ( ) << <STR_LIT> ) ; OpCode = <STR_LIT> ; MIFlags = MachineInstr :: FrameSetup ; auto NextMBBI = std :: next ( MBBI ) ; MBBI -> eraseFromParent ( ) ; MBBI = NextMBBI ; } } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << ( OpCode == <STR_LIT> ? <STR_LIT> : <STR_LIT> ) << <STR_LIT>


<s> __asm__ ( <STR_LIT> : <STR_LIT> ( res ) : <STR_LIT> ( dg ) ) ; return


<s> SDValue SRL = OR . getOperand ( <NUM_LIT> ) ; SDValue SHL = OR . getOperand ( <NUM_LIT> ) ; if ( SRL . getOpcode ( ) != <STR_LIT> || SHL . getOpcode ( ) != <STR_LIT> ) { SRL = OR . getOperand ( <NUM_LIT> ) ; SHL = OR . getOperand ( <NUM_LIT> ) ; if ( SRL . getOpcode ( ) != <STR_LIT> || SHL . getOpcode ( ) != <STR_LIT> ) return false ; } ConstantSDNode * SRLSrc1 = dyn_cast < ConstantSDNode > ( SRL . getOperand ( <NUM_LIT> ) ) ; ConstantSDNode * SHLSrc1 = dyn_cast < ConstantSDNode > ( SHL . getOperand ( <NUM_LIT> ) ) ; if ( ! SRLSrc1 || ! SHLSrc1 || SRLSrc1 -> getZExtValue ( ) != <NUM_LIT> || SHLSrc1 -> getZExtValue ( ) != <NUM_LIT> ) return false ; if ( ( SRL . getOperand ( <NUM_LIT> ) . getNode ( ) != SHL . getOperand ( <NUM_LIT> ) . getNode ( ) ) || SRL . getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> ) return false ; SDNode * SMULLOHI = SRL . getOperand ( <NUM_LIT> ) . getNode ( ) ; if ( SRL . getOperand ( <NUM_LIT> ) != SDValue ( SMULLOHI , <NUM_LIT> ) || SHL . getOperand ( <NUM_LIT> ) != SDValue ( SMULLOHI , <NUM_LIT> ) ) return false ; if ( SearchSignedMulShort ( SMULLOHI -> getOperand ( <NUM_LIT> ) , Opc , Src1 , Accumulate ) ) { Src0 = SMULLOHI -> getOperand ( <NUM_LIT> ) ; } else if ( SearchSignedMulShort ( SMULLOHI -> getOperand ( <NUM_LIT> ) , Opc , Src1 , Accumulate ) ) { Src0 = SMULLOHI -> getOperand (


<s> Align Alignment = std :: max ( TargetAlign , MaxAlign ) ; const <ISA_LIT>RegisterInfo * RegInfo = Subtarget . getRegisterInfo ( ) ; unsigned LR = RegInfo -> getRARegister ( ) ; bool DisableRedZone = MF . getFunction ( ) . hasFnAttribute ( Attribute :: NoRedZone ) ; bool CanUseRedZone = ! MFI . hasVarSizedObjects ( ) && ! MFI . adjustsStack ( ) && ! MustSaveLR ( MF , LR

) && ! FI -> mustSaveTOC ( ) && ! RegInfo -> hasBasePointer ( MF ) ;


<s> return { { [ = ] ( MachineInstrBuilder & MIB ) { MIB . add ( Root ) ; } , [ = ] ( MachineInstrBuilder & MIB ) { MIB . addImm ( <NUM_LIT> ) ; } } } ; } int64_t ConstAddr = <NUM_LIT> ; if ( isBaseWithConstantOffset ( Root , MRI ) ) { const MachineOperand & LHS = RootDef -> getOperand ( <NUM_LIT> ) ; const MachineOperand & RHS = RootDef -> getOperand ( <NUM_LIT> ) ; const MachineInstr * LHSDef = MRI . getVRegDef ( LHS . getReg ( ) ) ; const MachineInstr * RHSDef = MRI . getVRegDef ( RHS . getReg ( ) ) ; if ( LHSDef && RHSDef ) { int64_t PossibleOffset = RHSDef -> getOperand ( <NUM_LIT> ) . getCImm ( ) -> getSExtValue ( ) ; if ( isDSOffsetLegal ( MRI , LHS , PossibleOffset , <NUM_LIT> ) ) { return { { [ = ] ( MachineInstrBuilder & MIB ) { MIB . add ( LHS ) ; } , [ = ] ( MachineInstrBuilder & MIB ) { MIB . addImm ( PossibleOffset ) ; } } } ; } } } else if ( RootDef -> getOpcode ( ) == <STR_LIT> ) { } else if ( mi_match ( Root . getReg ( ) , MRI , m_ICst ( ConstAddr ) ) ) { } return { { [ = ] ( MachineInstrBuilder & MIB ) { MIB . add ( Root ) ; } , [ = ] ( MachineInstrBuilder


<s> } Info . flags |= MachineMemOperand :: MOLoad ; } else if ( Attr . hasFnAttribute ( Attribute :: WriteOnly ) ) { Info . opc = <STR_LIT> ; Info . memVT = <STR_LIT> ( CI . getArgOperand ( <NUM_LIT> ) -> getType ( ) ) ; Info . flags |= MachineMemOperand :: MOStore ; } else { Info . opc = <STR_LIT> ; Info . memVT = <STR_LIT> ( CI . getType ( ) ) ; Info . flags = MachineMemOperand :: MOLoad | MachineMemOperand :: MOStore | MachineMemOperand :: MODereferenceable ; Info . flags |= MachineMemOperand :: MOVolatile ; } return true ; } switch ( IntrID ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { Info . opc = <STR_LIT> ; Info . memVT = <STR_LIT> ( CI . getType ( ) ) ; Info . ptrVal = CI . getOperand ( <NUM_LIT> ) ; Info . align = <NUM_LIT> ; Info . flags = MachineMemOperand :: MOLoad | MachineMemOperand :: MOStore ; const ConstantInt * Vol = cast < ConstantInt > ( CI . getOperand ( <NUM_LIT> ) ) ; if ( ! Vol -> isZero ( ) ) Info . flags |= MachineMemOperand :: MOVolatile ; return true ; } case <STR_LIT> : case <STR_LIT> : { Info . opc = <STR_LIT> ; Info . memVT = <STR_LIT> ( CI . getType ( ) ) ; Info . ptrVal = CI . getOperand ( <NUM_LIT> ) ; Info . align = <NUM_LIT> ; Info . flags = MachineMemOperand :: MOLoad | MachineMemOperand :: MOStore ; const ConstantInt * Vol = cast < ConstantInt > ( CI . getOperand ( <NUM_LIT> ) ) ; if ( ! Vol -> isZero ( ) ) Info . flags |= MachineMemOperand :: MOVolatile ; return true ; } case <STR_LIT> : case <STR_LIT> : { Info . opc = <STR_LIT> ; <ISA_LIT>MachineFunctionInfo * MFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; Info . ptrVal = MFI -> getGWSPSV ( * MF . getSubtarget < GCNSubtarget > ( ) . getInstrInfo ( ) ) ; Info . memVT =


<s> SDValue N1 = Op . getOperand ( <NUM_LIT> ) ; SDValue N2 , N3 ; if ( VT == <STR_LIT> ) { N0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N0 ) ; N1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N1 ) ; N2 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N0 , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; N3 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N1 , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; N0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N0 , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; N1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N1 , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; N0 = LowerSDIV_v4i8 ( N0 , N1 , dl , DAG ) ; N2 = LowerSDIV_v4i8 ( N2 , N3 , dl , DAG ) ; N0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N0 , N2 ) ; N0 = LowerCONCAT_VECTORS ( N0


<s> void <ISA_LIT>TargetLowering :: VarArgStyleRegisters ( CCState & CCInfo , SelectionDAG & DAG , DebugLoc dl , SDValue & Chain , unsigned ArgOffset ) const { MachineFunction & MF = DAG . getMachineFunction ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; unsigned firstRegToSaveIndex ; if ( CCInfo . isFirstByValRegValid ( ) ) firstRegToSaveIndex = CCInfo . getFirstByValReg ( ) - <STR_LIT> ; else { firstRegToSaveIndex = CCInfo . getFirstUnallocated ( GPRArgRegs , sizeof ( GPRArgRegs ) / sizeof ( GPRArgRegs [ <NUM_LIT> ] ) ) ; } unsigned VARegSize , VARegSaveSize ; computeRegArea ( CCInfo , MF , VARegSize , VARegSaveSize ) ; if ( VARegSaveSize ) { AFI -> setVarArgsRegSaveSize ( VARegSaveSize ) ; AFI -> setVarArgsFrameIndex ( MFI -> CreateFixedObject ( VARegSaveSize , ArgOffset + VARegSaveSize - VARegSize , false ) ) ; SDValue FIN = DAG . getFrameIndex ( AFI -> getVarArgsFrameIndex ( ) , getPointerTy ( ) ) ; SmallVector < SDValue , <NUM_LIT> > MemOps ; for ( ; firstRegToSaveIndex < <NUM_LIT> ; ++ firstRegToSaveIndex ) { const TargetRegisterClass * RC ; if ( AFI -> isThumb1OnlyFunction ( ) ) RC = & <STR_LIT> ; else RC = & <STR_LIT> ; unsigned VReg = MF . addLiveIn ( GPRArgRegs [


<s> void <ISA_LIT>InstrInfo :: storeRegToAddr ( MachineFunction & MF , unsigned SrcReg , bool isKill , SmallVectorImpl < MachineOperand > & Addr , const TargetRegisterClass * RC , MachineInstr :: mmo_iterator MMOBegin , MachineInstr :: mmo_iterator MMOEnd , SmallVectorImpl < MachineInstr * > & NewMIs ) const { unsigned Alignment = ( RC -> getSize ( ) / <NUM_LIT> ) == <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ; bool isAligned = MMOBegin != MMOEnd && ( * MMOBegin ) -> getAlignment ( ) >= Alignment ; unsigned Opc = getStoreRegOpcode ( SrcReg , RC , isAligned , TM ) ; DebugLoc DL ; MachineInstrBuilder MIB = BuildMI ( MF , DL , get


<s> WriteGraph ( OS , G , false , <STR_LIT> + MF . getName


<s> NumLoads = LoadSize / <NUM_LIT> ; Ty = Ty . divide ( NumLoads ) ; } const Align Alignment = NumLoads > <NUM_LIT> ? Align ( <NUM_LIT> * NumLoads ) : Align ( <NUM_LIT> ) ; MachineIRBuilder B ( MI ) ; MachineFunction & MF = B . getMF ( ) ; Register SOffset ; Register VOffset ; int64_t ImmOffset = <NUM_LIT> ; unsigned MMOOffset = setBufferOffsets ( B , * this , MI . getOperand ( <NUM_LIT> ) . getReg ( ) , VOffset , SOffset , ImmOffset , Alignment ) ; const unsigned MemSize = ( Ty . getSizeInBits ( ) + <NUM_LIT> ) / <NUM_LIT> ; const Align MemAlign ( <NUM_LIT> ) ; MachineMemOperand * BaseMMO = MF . getMachineMemOperand ( MachinePointerInfo ( ) , MachineMemOperand :: MOLoad | MachineMemOperand :: MODereferenceable | MachineMemOperand :: MOInvariant , MemSize , MemAlign ) ; if ( MMOOffset != <NUM_LIT> ) BaseMMO = MF . getMachineMemOperand ( BaseMMO , MMOOffset , MemSize ) ; Register RSrc = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register VIndex = B . buildConstant ( S32 , <NUM_LIT> ) . getReg ( <NUM_LIT> ) ; B . getMRI ( ) -> setRegBank ( VIndex , <STR_LIT> ) ; SmallVector < Register , <NUM_LIT> > LoadParts ( NumLoads ) ; MachineBasicBlock :: iterator MII = MI . getIterator ( ) ; MachineInstrSpan Span ( MII , & B . getMBB ( ) ) ; for ( int i = <NUM_LIT> ; i < NumLoads ; ++ i ) { if ( NumLoads == <NUM_LIT> ) { LoadParts [ i ] = Dst ; } else { LoadParts [ i ] = MRI . createGenericVirtualRegister ( Ty ) ; MRI . setRegBank ( LoadParts [ i ] , <STR_LIT> ) ; } MachineMemOperand * MMO = BaseMMO ; if ( i != <NUM_LIT> ) BaseMMO = MF . getMachineMemOperand ( BaseMMO , MMOOffset + <NUM_LIT> * i , MemSize ) ; B . buildInstr ( <STR_LIT> ) . addDef ( LoadParts [ i ] ) . addUse ( RSrc ) . addUse ( VIndex ) . addUse ( VOffset ) . addUse ( SOffset ) . addImm ( ImmOffset + <NUM_LIT> * i ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ; } if ( RSrcBank != & <STR_LIT>


<s> int priority1 = rs6000_clone_priority ( decl1 ) ; int priority2 = rs6000_clone_priority ( decl2 ) ; int ret = priority1


<s> MachineInstr * Clone = & * std :: prev ( Insert ) ; LIS . InsertMachineInstrInMaps ( * Clone ) ; LIS . createAndComputeVirtRegInterval ( NewReg ) ; MFI . stackifyVReg ( NewReg ) ; ImposeStackOrdering ( Clone ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; Clone -> dump ( ) ) ; bool IsDead = MRI . use_empty ( Reg ) ; if ( ! IsDead ) { LiveInterval & LI = LIS . getInterval ( Reg ) ; ShrinkToUses ( LI , LIS ) ; IsDead = ! LI . liveAt ( LIS . getInstructionIndex ( Def ) . getDeadSlot ( ) ) ; } if ( IsDead ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; SlotIndex Idx = LIS . getInstructionIndex ( Def ) . getRegSlot ( ) ; LIS . removePhysRegDefAt ( <STR_LIT> , Idx ) ; LIS . removeInterval ( Reg ) ; LIS . RemoveMachineInstrFromMaps ( Def ) ; Def . eraseFromParent ( ) ; MoveDebugValues ( Reg , & * Insert , MBB , MRI ) ; UpdateDebugValuesReg ( Reg , NewReg , MBB , MRI ) ; } else { CloneDebugValues ( Reg , & * Insert , NewReg , MBB ,


<s> return rs6000_mode_dependent_address_ptr ( addr


<s> return <ISA_LIT>AutoHVX && getST ( ) -> useHVXOps ( )


<s> if ( A_Base == B_Base && A_Base ) report_fatal_error ( <STR_LIT> , false ) ; if ( A -> isUndefined ( ) || B -> isUndefined ( ) ) { StringRef Name = A -> isUndefined ( ) ? A -> getName ( ) : B -> getName ( ) ; Asm . getContext ( ) . reportFatalError ( Fixup . getLoc ( ) , <STR_LIT> + Name + <STR_LIT> ) ; } Value += Writer -> getSymbolAddress ( * A , Layout ) - ( ! A_Base ? <NUM_LIT> : Writer -> getSymbolAddress ( * A_Base , Layout ) ) ; Value -= Writer -> getSymbolAddress ( * B , Layout ) - ( ! B_Base ? <NUM_LIT> : Writer -> getSymbolAddress ( * B_Base , Layout ) ) ; if ( ! A_Base ) Index = A -> getFragment ( ) -> getParent ( ) -> getOrdinal ( ) + <NUM_LIT> ; Type = MachO :: <ISA_LIT>_64_RELOC_UNSIGNED ; MachO :: any_relocation_info MRE ; MRE . r_word0 = FixupOffset ; MRE . r_word1 = ( Index << <NUM_LIT> ) | ( IsPCRel << <NUM_LIT> ) | ( Log2Size << <NUM_LIT> ) | ( Type << <NUM_LIT> ) ; Writer -> addRelocation ( A_Base , Fragment -> getParent ( ) , MRE ) ; if ( B_Base ) RelSymbol = B_Base ; else Index = B -> getFragment ( ) -> getParent ( ) -> getOrdinal ( ) + <NUM_LIT> ; Type = MachO :: <ISA_LIT>_64_RELOC_SUBTRACTOR ; } else { const MCSymbol * Symbol = & Target . getSymA ( ) -> getSymbol ( ) ; if ( Symbol -> isTemporary ( ) && Value ) { const MCSection & Sec = Symbol -> getSection ( ) ; if ( ! Asm . getContext ( ) . getAsmInfo ( ) -> isSectionAtomizableBySymbols ( Sec ) ) Asm . addLocalUsedInReloc ( * Symbol ) ; } RelSymbol = Asm . getAtom ( * Symbol ) ; if ( Symbol -> isInSection ( ) ) { const MCSectionMachO & Section = static_cast < const MCSectionMachO & > ( * Fragment -> getParent ( ) ) ; if ( Section . hasAttribute ( MachO :: S_ATTR_DEBUG ) ) RelSymbol = nullptr ; } if ( RelSymbol ) { if ( RelSymbol != Symbol ) Value += Layout . getSymbolOffset ( * Symbol ) - Layout . getSymbolOffset ( * RelSymbol ) ; } else if ( Symbol -> isInSection ( ) && ! Symbol -> isVariable ( ) ) { Index = Symbol -> getFragment ( ) -> getParent ( ) -> getOrdinal


<s> Inst . addOperand ( MCOperand :: CreateImm ( Imm ) ) ; return Success


<s> return ( __m256d ) __builtin_ia32_permvardf256_mask ( ( __v4df ) __Y , ( __v4di ) __X , (


<s> if ( Literal >= - <NUM_LIT> && Literal <= <NUM_LIT> ) return true ; uint16_t Val = static_cast < uint16_t > (


<s> } if ( Src2 -> isReg ( ) && Src2 -> getReg ( ) == Reg ) { bool Src0Inlined = false ; if ( Src0 -> isReg ( ) ) { MachineInstr * Def = MRI -> getUniqueVRegDef ( Src0 -> getReg ( ) ) ; if ( Def && Def -> isMoveImmediate ( ) && isInlineConstant ( Def -> getOperand ( <NUM_LIT> ) ) && MRI -> hasOneUse ( Src0 -> getReg ( ) ) ) { Src0 -> ChangeToImmediate ( Def -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; Src0Inlined = true ; } else if ( ( Register :: isPhysicalRegister ( Src0 -> getReg ( ) ) && ( ST . getConstantBusLimit ( Opc ) <= <NUM_LIT> && RI . isSGPRClass ( RI . getPhysRegClass ( Src0 -> getReg ( ) ) ) ) ) || ( Register :: isVirtualRegister ( Src0 -> getReg ( ) ) && ( ST . getConstantBusLimit ( Opc ) <= <NUM_LIT> && RI . isSGPRClass ( MRI -> getRegClass ( Src0 -> getReg ( ) ) ) ) ) ) return false ; } if ( Src1 -> isReg ( ) && ! Src0Inlined ) { MachineInstr * Def = MRI -> getUniqueVRegDef ( Src1 -> getReg ( ) ) ; if ( Def && Def -> isMoveImmediate ( ) && isInlineConstant ( Def -> getOperand ( <NUM_LIT> ) ) && MRI -> hasOneUse ( Src1 -> getReg ( ) ) && commuteInstruction ( UseMI ) ) { Src0 -> ChangeToImmediate ( Def -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; } else if ( ( Register :: isPhysicalRegister ( Src1 -> getReg ( ) ) && RI . isSGPRClass ( RI . getPhysRegClass ( Src1 -> getReg ( ) ) ) ) || ( Register :: isVirtualRegister ( Src1 -> getReg ( ) ) && RI . isSGPRClass ( MRI -> getRegClass ( Src1 -> getReg ( ) ) ) ) ) return false ; } unsigned NewOpc = IsFMA ? ( IsF32 ? <STR_LIT> : <STR_LIT> ) : ( IsF32 ? <STR_LIT> : <STR_LIT> ) ; if ( pseudoToMCOpcode ( NewOpc ) == - <NUM_LIT> ) return false ; const int64_t Imm = ImmOp -> getImm ( ) ; UseMI . RemoveOperand ( <STR_LIT> ( Opc , <STR_LIT> :: omod ) ) ; UseMI . RemoveOperand ( <STR_LIT> ( Opc , <STR_LIT> :: clamp ) ) ; if ( Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ) UseMI . untieRegOperand ( <STR_LIT> ( Opc , <STR_LIT> :: src2 ) ) ; Src2 -> ChangeToImmediate ( Imm ) ; removeModOperands ( UseMI


<s> if ( type == TYPE_MUL || type == TYPE_DIV || type == TYPE_SDIV || type == TYPE_DDIV || type == TYPE_SSQRT || type == TYPE_DSQRT || type == TYPE_MFCR ||

type == TYPE_MFCRF || type == TYPE_MFJMPR ) {


<s> if ( CALL_P ( insn ) && dep_type == REG_DEP_TRUE ) { rtx target = get_jump_target ( insn ) ; if ( ! REG_P ( target ) || ! set_of ( target


<s> assert ( Subtarget . hasBWI ( ) && <STR_LIT> ) ; SDValue Lo , Hi ; Lo = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Mask , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; Hi = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Mask , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; Lo = DAG . getBitcast ( <STR_LIT> , Lo ) ; Hi = DAG . getBitcast ( <STR_LIT> , Hi ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Lo


<s> return getTM < <ISA_LIT>TargetMachine >


<s> Again = ( Contigious && Type ) || ( Workaround && Type ) ; NeededWorkaround = NeededWorkaround || ( Again && ! ( Contigious && Type ) ) ; } std :: string Collapsed = RawString ; Collapsed . erase ( std :: remove_if ( Collapsed . begin ( ) , Collapsed . end ( ) , isspace ) , Collapsed . end ( ) ) ; StringRef FullString = Collapsed ; std :: pair < StringRef , StringRef > DotSplit = FullString . split ( '.' ) ; unsigned DotReg = MatchRegisterName ( DotSplit . first . lower ( ) ) ; if ( DotReg != <STR_LIT> && RegisterMatchesArch ( DotReg ) ) { if ( DotSplit . second . empty ( ) ) { RegNo = DotReg ; EndLoc = Lexer . getLoc ( ) ; if ( handleNoncontigiousRegister ( ! NeededWorkaround , StartLoc ) ) return true ; return false ; } else { RegNo = DotReg ; size_t First = RawString . find ( '.' ) ; StringRef DotString ( RawString . data ( ) + First , RawString . size ( ) - First ) ; Lexer . UnLex ( AsmToken ( AsmToken :: Identifier , DotString ) ) ; EndLoc = Lexer . getLoc ( ) ; if ( handleNoncontigiousRegister ( ! NeededWorkaround , StartLoc ) ) return true ; return false ; } } std :: pair < StringRef , StringRef > ColonSplit = StringRef ( FullString ) . split ( ':' ) ; unsigned ColonReg = MatchRegisterName ( ColonSplit . first . lower ( ) ) ; if ( ColonReg != <STR_LIT> && RegisterMatchesArch ( DotReg ) ) { Lexer . UnLex ( Lookahead . back ( ) ) ; Lookahead . pop_back ( ) ; Lexer . UnLex ( Lookahead . back ( ) ) ; Lookahead . pop_back ( ) ; RegNo = ColonReg ; EndLoc = Lexer . getLoc ( ) ; if ( handleNoncontigiousRegister ( ! NeededWorkaround , StartLoc


<s> NewMI = BuildMI ( * MF , MI -> getDebugLoc ( ) , TII -> get ( addrr_opcode ) ) . addOperand ( Dst ) . addOperand ( Src1 ) . addOperand ( Src2 ) ; MFI -> insert ( I , NewMI ) ; DEBUG ( NewMI -> dump ( ) ; ) ; } if ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) != <NUM_LIT> ) { const MachineOperand & SrcR = MI -> getOperand ( SrcR1 == DstR ? <NUM_LIT> : <NUM_LIT> ) ; NewMI = BuildMI ( * MF , MI -> getDebugLoc ( ) , TII -> get ( addri_opcode ) ) . addOperand ( Dst ) . addOperand ( SrcR ) . addImm ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; MFI -> insert ( I , NewMI ) ; DEBUG ( NewMI -> dump ( ) ; ) ; } if ( NewMI ) { MFI -> erase


<s> if ( PC != Ignore && PC != I ) Edges [ I ] . insert ( PC ) ; } } for ( unsigned I = <NUM_LIT> ; I != Order . size ( ) ; ++ I ) { if ( ! Needed . count ( I ) ) continue ; Node C = conj (


<s> } else { ++ I ; } continue ; } else if ( Opc == AMDGPU :: DS_WRITE_B32 || Opc == AMDGPU :: DS_WRITE_B64 ) { unsigned Size = ( Opc == AMDGPU :: DS_WRITE_B64 ) ? <NUM_LIT> : <NUM_LIT> ; MachineBasicBlock :: iterator Match = findMatchingD<ISA_LIT>nst ( I , Size ) ; if ( Match != E ) { Modified = true ; I = mergeWrite2Pair ( I , Match ,


<s> } emit_insn ( gen_add3_insn ( this_rtx , this_rtx , offset ) ) ; } if ( vcall_offset != <NUM_LIT> ) { rtx addr ; riscv_emit_move ( temp1 , gen_rtx_MEM ( Pmode , this_rtx ) ) ; addr = riscv_add_offset ( temp2 , temp1 , vcall_offset ) ; riscv_emit_move ( temp1 , gen_rtx_MEM ( Pmode , addr ) ) ; emit_insn ( gen_add3_insn ( this_rtx , this_rtx , temp1 ) ) ; } insn = emit_call_insn ( gen_sibcall ( fnaddr , const0_rtx , NULL , const0_rtx ) ) ; SIBLING_CALL_P ( insn ) = <NUM_LIT> ; insn = get_insns


<s> unsigned <ISA_LIT>Z80MCCodeEmitter :: getExprOpValue ( const MCExpr * Expr , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { MCExpr :: ExprKind Kind = Expr -> getKind ( ) ; if ( Kind == MCExpr :: Binary ) { Expr = static_cast < const MCBinaryExpr * > ( Expr ) -> getLHS ( ) ; Kind = Expr -> getKind ( ) ; } if ( Kind == MCExpr :: Target ) { <ISA_LIT>Z80MCExpr const * <ISA_LIT>Z80Expr = cast < <ISA_LIT>Z80MCExpr > ( Expr ) ; int64_t Result ; if ( <ISA_LIT>Z80Expr -> evaluateAsConstant ( Result )


<s> bool has<ISA_LIT>16Attr = ! FnAttrs . getAttribute ( AttributeSet :: FunctionIndex , <STR_LIT> ) . hasAttribute ( Attribute :: None ) ; bool hasNo<ISA_LIT>16Attr = ! FnAttrs . getAttribute ( AttributeSet :: FunctionIndex , <STR_LIT> ) . hasAttribute ( Attribute :: None ) ; Attribute SFAttr = FnAttrs . getAttribute ( AttributeSet :: FunctionIndex , <STR_LIT> ) ; bool softFloat = ! SFAttr . hasAttribute ( Attribute :: None ) ? SFAttr . getValueAsString ( ) == <STR_LIT> : Options . UseSoftFloat ; if ( has<ISA_LIT>16Attr ) FS += FS . empty ( ) ? <STR_LIT> : <STR_LIT> ; else if ( hasNo<ISA_LIT>16Attr ) FS += FS . empty ( ) ? <STR_LIT> : <STR_LIT> ; auto & I = SubtargetMap [ CPU + FS + ( softFloat ? <STR_LIT> : <STR_LIT> ) ] ; if ( ! I ) { resetTargetOptions ( F ) ; I = llvm :: make_unique < <ISA_LIT>Subtarget > ( TargetTriple , CPU , FS , isLittle , * this ) ; } return I . get ( )


<s> static MCInstPrinter * create<ISA_LIT>MCInstPrinter ( const Triple & T , unsigned SyntaxVariant , const MCAsmInfo & MAI , const MCInstrInfo & MII , const MCRegisterInfo & MRI ) { return new <ISA_LIT>InstPrinter ( MAI , MII


<s> MCCodeEmitter * create<ISA_LIT>MCCodeEmitterEB ( const MCInstrInfo & MCII , MCContext


<s> bool <ISA_LIT>FastISel :: isTypeLegal ( Type * Ty , MVT & VT ) { EVT Evt = TLI . getValueType ( DL , Ty , true ) ; if ( Evt == <STR_LIT> || ! Evt . isSimple ( ) ) return false ; VT = Evt . getSimpleVT ( ) ; return TLI . isTypeLegal


<s> if ( IsPIC && Subtarget . isSVR4ABI ( ) ) { SDValue GA = DAG . getTargetJumpTable ( JT -> getIndex ( ) , PtrVT , <STR_LIT> ) ; return getTOCEntry ( DAG , SDLoc ( GA ) , GA ) ; } SDValue JTIHi = DAG . getTargetJumpTable ( JT -> getIndex ( ) , PtrVT , MOHiFlag ) ; SDValue JTILo = DAG . getTargetJumpTable ( JT -> getIndex ( ) , PtrVT , MOLoFlag ) ; return LowerLabelRef ( JTIHi , JTILo , IsPIC ,


<s> assert ( ( RVVVectorBitsMin == <NUM_LIT> || ( RVVVectorBitsMin >= <NUM_LIT> && RVVVectorBitsMin <= <NUM_LIT> && isPowerOf2_32 ( RVVVectorBitsMin ) ) ) && <STR_LIT> <STR_LIT> ) ; assert ( ( RVVVectorBitsMax >= RVVVectorBitsMin || RVVVectorBitsMax == <NUM_LIT> ) && <STR_LIT> <STR_LIT> ) ; unsigned Min = RVVVectorBitsMin ; if ( RVVVectorBitsMax != <NUM_LIT> ) Min = std

:: min ( RVVVectorBitsMin , RVVVectorBitsMax ) ;


<s> FI -> setMustSaveLR ( MustSaveLR ( MF , LR ) ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; MRI . setPhysRegUnused ( LR ) ; int FPSI = FI -> getFramePointerSaveIndex ( ) ; bool is<ISA_LIT>64 = Subtarget . is<ISA_LIT>64 ( ) ; bool isDarwinABI = Subtarget . isDarwinABI ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; if ( ! FPSI && needsFP ( MF ) ) { int FPOffset = getFramePointerSaveOffset ( is<ISA_LIT>64 , isDarwinABI ) ; FPSI = MFI -> CreateFixedObject ( is<ISA_LIT>64 ? <NUM_LIT> : <NUM_LIT> , FPOffset , true ) ; FI -> setFramePointerSaveIndex ( FPSI ) ; } int BPSI = FI -> getBasePointerSaveIndex ( ) ; if ( ! BPSI && RegInfo -> hasBasePointer ( MF ) ) { int BPOffset = getBasePointerSaveOffset ( is<ISA_LIT>64 , isDarwinABI ) ; BPSI = MFI -> CreateFixedObject ( is<ISA_LIT>64 ? <NUM_LIT> : <NUM_LIT> , BPOffset , true ) ; FI -> setBasePointerSaveIndex


<s> default : break ; case <STR_LIT> : case <STR_LIT> : return PerformDivRemCombine ( N , DAG


<s> res = strstr ( arr [ <NUM_LIT> ] , str ) != NULL ; if ( res ) return res ; if ( arr [ <NUM_LIT> ] != NULL ) return strstr ( arr [ <NUM_LIT>


<s> getReadTimeStampCounter ( Op . getNode ( ) , DL , <STR_LIT> , DAG , Subtarget ,


<s> if ( GET_CODE ( address ) == REG && REGNO ( address ) == LR_REGNO ) SET_REGNO ( address , GPR_FIRST + <NUM_LIT> ) ; } } } frv_pack_insns ( ) ; memset ( frv_nops , <NUM_LIT> , sizeof ( frv_nops ) ) ; last_call = NULL ; for ( insn = get_insns ( ) ; insn ; insn = next ) { next = NEXT_INSN ( insn ) ; if ( CALL_P ( insn ) || ( INSN_P ( insn ) && GET_CODE ( PATTERN ( insn ) ) == SEQUENCE && CALL_P ( XVECEXP ( PATTERN ( insn ) , <NUM_LIT> , <NUM_LIT> ) ) ) ) last_call = insn ; if ( ! NOTE_P ( insn ) || NOTE_KIND ( insn ) != NOTE_INSN_CALL_ARG_LOCATION ) continue ; if ( NEXT_INSN ( last_call ) == insn ) continue ; SET_NEXT_INSN ( PREV_INSN ( insn ) ) = NEXT_INSN ( insn ) ; SET_PREV_INSN ( NEXT_INSN ( insn ) ) = PREV_INSN ( insn ) ; SET_PREV_INSN ( insn ) = last_call ; SET_NEXT_INSN ( insn ) = NEXT_INSN ( last_call ) ; SET_PREV_INSN ( NEXT_INSN ( insn ) ) = insn ; SET_NEXT_INSN ( PREV_INSN ( insn ) ) = insn ; last_call = insn


<s> const char * cpu = TREE_STRING_POINTER ( arg ) ; rtx cpuid = NULL_RTX ; for ( size_t i = <NUM_LIT> ; i < ARRAY_SIZE ( cpu_is_info ) ; i ++ ) if ( strcmp ( cpu , cpu_is_info [ i ] . cpu ) == <NUM_LIT> ) { cpuid = GEN_INT ( cpu_is_info [ i ] . cpuid + _DL_FIRST_PLATFORM ) ; break ; } if ( cpuid == NULL_RTX ) { error ( <STR_LIT> , cpu , rs6000_builtin_info [ ( size_t ) fcode ] . name ) ; return const0_rtx ; } rtx platform = gen_reg_rtx ( SImode ) ; rtx tcbmem = gen_const_mem ( SImode , gen_rtx_PLUS ( Pmode , gen_rtx_REG ( Pmode , TLS_REGNUM ) , GEN_INT ( TCB_PLATFORM_OFFSET ) ) ) ; emit_move_insn ( platform , tcbmem ) ; emit_insn ( gen_eqsi3 ( target , platform , cpuid ) ) ; } else if ( fcode == RS6000_BUILTIN_CPU_SUPPORTS ) { const char * hwcap = TREE_STRING_POINTER ( arg ) ; rtx mask =


<s> return getImm4 ( insn ) << <NUM_LIT> | slice ( insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> | getImm3 ( insn ) << <NUM_LIT> | getImm8


<s> <ISA_LIT>Operand * Op = static_cast < <ISA_LIT>Operand * > ( Operands [ <NUM_LIT> ] ) ; <ISA_LIT>Operand * Op2 = static_cast < <ISA_LIT>Operand * > ( Operands [ <NUM_LIT> ] ) ; Operands [ <NUM_LIT> ] = <ISA_LIT>Operand :: CreateToken ( <STR_LIT> , false , Op -> getStartLoc ( ) , Context ) ; Operands . push_back ( Operands [ <NUM_LIT> ] ) ; unsigned ZeroReg = <STR_LIT> ; if ( <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( Operands [ <NUM_LIT> ] -> getReg ( ) ) ) ZeroReg = <STR_LIT> ; Operands [ <NUM_LIT> ] = <ISA_LIT>Operand :: CreateReg ( ZeroReg , false , Op2 -> getStartLoc ( ) , Op2


<s> <ISA_LIT>AsmParser :: OperandMatchResultTy <ISA_LIT>AsmParser :: parseJumpTarget ( OperandVector & Operands ) { DEBUG ( dbgs ( ) << <STR_LIT> ) ; SMLoc S = getLexer ( ) . getLoc ( ) ; OperandMatchResultTy ResTy = parseImm ( Operands ) ; if ( ResTy != MatchOperand_NoMatch ) return ResTy ; ResTy = parseAnyRegister ( Operands ) ; if ( ResTy != MatchOperand_NoMatch ) return ResTy ; const MCExpr * Expr = nullptr ; if ( Parser . parseExpression ( Expr ) ) { return MatchOperand_ParseFail ; } Operands . push_back ( <STR_LIT> ( Expr , S , getLexer ( )


<s> bool <ISA_LIT>MCInstrInfo :: requiresSlot ( MCSubtargetInfo const & STI , MCInst const & MCI ) { const unsigned OpCode = MCI . getOpcode ( ) ; const bool IsTiny = STI . getFeatureBits ( )


<s> <ISA_LIT>Operand & Op = static_cast < <ISA_LIT>Operand & > ( AsmOp ) ; MatchClassKind Expected = static_cast < MatchClassKind > ( ExpectedKind ) ; if ( Op . isImm ( ) ) { if ( MCConstantExpr const * Const = dyn_cast < MCConstantExpr > ( Op . getImm ( ) ) ) { int64_t RegNum = Const -> getValue ( ) ; std :: ostringstream RegName ; RegName << <STR_LIT> << RegNum ; RegNum = MatchRegisterName ( RegName . str ( ) . c_str ( ) ) ; if ( RegNum != <STR_LIT> ) { Op . makeReg ( RegNum ) ; if ( validateOperandClass ( Op , Expected ) == Match_Success ) { return Match_Success ; } } } } if ( Op . isReg ( ) ) { if ( isSubclass ( Expected , MCK_DREGS ) ) { unsigned correspondingDREG = toDREG ( Op . getReg ( ) ) ; if ( correspondingDREG != <STR_LIT> ) { Op . makeReg ( correspondingDREG ) ; return validateOperandClass ( Op ,


<s> RegisterAsmPrinter < <ISA_LIT>AsmPrinter > X ( getThe<ISA_LIT>leTarget ( ) ) ; RegisterAsmPrinter < <ISA_LIT>AsmPrinter > Y ( getThe<ISA_LIT>beTarget ( ) ) ; RegisterAsmPrinter < <ISA_LIT>AsmPrinter > Z ( getTheARM64Target ( ) ) ; RegisterAsmPrinter < <ISA_LIT>AsmPrinter > W ( getTheARM64_32Target ( ) ) ; RegisterAsmPrinter < <ISA_LIT>AsmPrinter > V ( getThe<ISA_LIT>_32Target


<s> static bool CC_<ISA_LIT>_Custom_i1i8i16_Stack ( unsigned ValNo , MVT ValVT , MVT LocVT , CCValAssign :: LocInfo LocInfo , <STR_LIT> ArgFlags , CCState & State ) { unsigned Space = ( ( LocVT == <STR_LIT> || LocVT == <STR_LIT> ) ? <NUM_LIT> : <NUM_LIT> ) ; unsigned Offset12 = State . AllocateStack ( Space , Space ) ; ValVT = LocVT


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : OpId = <NUM_LIT> ; break ; case <STR_LIT> : OpId = <NUM_LIT> ; break ; } if ( Info -> get ( Inst . getOpcode ( ) ) . OpInfo [ OpId ] . OperandType != MCOI :: OPERAND_PCREL ) return false ; Target = Addr + Inst . getOperand ( OpId ) . getImm ( ) + <NUM_LIT> ; return


<s> case <STR_LIT> : case <STR_LIT> : { auto & DL = I . getCalledFunction ( ) -> getParent ( ) -> getDataLayout ( ) ; PointerType * PtrTy = cast < PointerType > ( I . getArgOperand ( <NUM_LIT> ) -> getType ( ) ) ; Info . opc = <STR_LIT> ; Info . memVT = <STR_LIT> ( PtrTy -> getElementType ( ) ) ; Info . ptrVal = I . getArgOperand ( <NUM_LIT> ) ; Info . offset = <NUM_LIT> ; Info . align = MaybeAlign ( DL . getABITypeAlignment ( PtrTy -> getElementType ( ) ) ) ; Info . flags = MachineMemOperand :: MOLoad | MachineMemOperand :: MOVolatile ; return true ; } case <STR_LIT> : case <STR_LIT> : { auto & DL = I . getCalledFunction ( ) -> getParent ( ) -> getDataLayout ( ) ; PointerType * PtrTy = cast < PointerType > ( I . getArgOperand ( <NUM_LIT> ) -> getType ( ) ) ; Info . opc = <STR_LIT> ; Info . memVT = <STR_LIT> ( PtrTy -> getElementType ( ) ) ; Info . ptrVal = I . getArgOperand ( <NUM_LIT> ) ; Info . offset = <NUM_LIT> ; Info . align = MaybeAlign ( DL . getABITypeAlignment ( PtrTy -> getElementType ( ) ) ) ; Info . flags = MachineMemOperand :: MOStore | MachineMemOperand :: MOVolatile ; return true ; } case <STR_LIT> : case <STR_LIT> : Info . opc = <STR_LIT> ; Info . memVT = <STR_LIT> ; Info . ptrVal = I . getArgOperand ( <NUM_LIT> ) ; Info . offset = <NUM_LIT> ; Info . align = Align ( <NUM_LIT> ) ; Info . flags = MachineMemOperand :: MOStore | MachineMemOperand :: MOVolatile ; return true ; case <STR_LIT> : case <STR_LIT> : Info . opc = <STR_LIT> ; Info . memVT = <STR_LIT> ; Info . ptrVal = I . getArgOperand ( <NUM_LIT> ) ; Info . offset = <NUM_LIT> ; Info . align = Align ( <NUM_LIT>


<s> if ( Value == <NUM_LIT> ) return ; MCFixupKindInfo Info = getFixupKindInfo ( Fixup . getKind ( ) ) ; auto NumBits = Info . TargetSize + Info . TargetOffset ; auto NumBytes = ( NumBits / <NUM_LIT> ) + ( ( NumBits % <NUM_LIT> ) == <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ) ; Value <<= Info . TargetOffset ; unsigned Offset = Fixup . getOffset ( ) ; assert ( Offset + NumBytes <= Data . size (


<s> static MCAsmInfo * create<ISA_LIT>MCAsmInfo ( const MCRegisterInfo & MRI , const Triple & TT ) { MCAsmInfo * MAI = new <ISA_LIT>MCAsmInfo ( ) ; MCCFIInstruction Inst = MCCFIInstruction :: createDefCfa ( nullptr , MRI . getDwarfRegNum ( <STR_LIT> , true ) , <STR_LIT> ) ; MAI -> addInitialFrameState ( Inst ) ; return


<s> unsigned int flags = <NUM_LIT> ; if ( strcmp ( name , <STR_LIT> ) == <NUM_LIT> || startswith ( name , <STR_LIT> ) || startswith ( name , <STR_LIT> ) || strcmp ( name , <STR_LIT>

) == <NUM_LIT> || startswith ( name , <STR_LIT> ) || startswith ( name , <STR_LIT> ) ) flags = SECTION_SMALL ;


<s> if ( IsaInfo :: hasCodeObjectV3 ( getGlobalSTI ( ) ) ) HSAMetadataStream . reset ( new MetadataStreamerV3