<s> static tree ix86_vectorize_builtin_gather ( const_tree mem_vectype , const_tree index_type , int scale ) { bool si ; enum ix86_builtins code ; if ( ! TARGET_AVX2 || ! TARGET_USE_GATHER ) return NULL_TREE ; if ( ( TREE_CODE ( index_type ) != INTEGER_TYPE && ! POINTER_TYPE_P ( index_type ) ) || ( TYPE_MODE ( index_type ) != SImode && TYPE_MODE ( index_type ) != DImode ) ) return NULL_TREE ; if ( TYPE_PRECISION ( index_type ) > POINTER_SIZE ) return NULL_TREE ; if ( TYPE_PRECISION ( index_type ) < POINTER_SIZE && TYPE_UNSIGNED ( index_type ) ) return NULL_TREE ; if ( scale <= <NUM_LIT> || scale > <NUM_LIT> || ( scale & ( scale - <NUM_LIT> ) ) != <NUM_LIT> ) return NULL_TREE ; si = TYPE_MODE ( index_type ) == SImode ; switch ( TYPE_MODE ( mem_vectype ) ) { case E_V2DFmode : if ( TARGET_AVX512VL ) code = si ? IX86_BUILTIN_GATHER3SIV2DF : IX86_BUILTIN_GATHER3DIV2DF ; else code = si ? IX86_BUILTIN_GATHERSIV2DF : IX86_BUILTIN_GATHERDIV2DF ; break ; case E_V4DFmode : if ( TARGET_AVX512VL ) code = si ? IX86_BUILTIN_GATHER3ALTSIV4DF : IX86_BUILTIN_GATHER3DIV4DF ; else code = si ? IX86_BUILTIN_GATHERALTSIV4DF : IX86_BUILTIN_GATHERDIV4DF ; break ; case E_V2DImode : if ( TARGET_AVX512VL ) code = si ? IX86_BUILTIN_GATHER3SIV2DI : IX86_BUILTIN_GATHER3DIV2DI ; else code = si ? IX86_BUILTIN_GATHERSIV2DI : IX86_BUILTIN_GATHERDIV2DI ; break ; case E_V4DImode : if ( TARGET_AVX512VL ) code = si ? IX86_BUILTIN_GATHER3ALTSIV4DI : IX86_BUILTIN_GATHER3DIV4DI ; else code = si ? IX86_BUILTIN_GATHERALTSIV4DI : IX86_BUILTIN_GATHERDIV4DI ; break ; case E_V4SFmode : if ( TARGET_AVX512VL ) code = si ? IX86_BUILTIN_GATHER3SIV4SF : IX86_BUILTIN_GATHER3DIV4SF ; else code = si ? IX86_BUILTIN_GATHERSIV4SF : IX86_BUILTIN_GATHERDIV4SF ; break ; case E_V8SFmode : if ( TARGET_AVX512VL ) code = si ? IX86_BUILTIN_GATHER3SIV8SF : IX86_BUILTIN_GATHER3ALTDIV8SF ; else code = si ? IX86_BUILTIN_GATHERSIV8SF : IX86_BUILTIN_GATHERALTDIV8SF ; break ; case E_V4SImode : if ( TARGET_AVX512VL ) code = si ? IX86_BUILTIN_GATHER3SIV4SI : IX86_BUILTIN_GATHER3DIV4SI ; else code = si ? IX86_BUILTIN_GATHERSIV4SI


<s> if ( RN && RN -> getReg ( ) == <NUM_LIT> ) Base = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; else if ( Base . getValueType ( ) == <STR_LIT> && ! dyn_cast < FrameIndexSDNode > ( N ) ) { Base = SDValue ( CurDAG -> getMachineNode ( TargetOpcode :: SUBREG_TO_REG , DL , <STR_LIT> , CurDAG -> getTargetConstant ( <NUM_LIT> , <STR_LIT> ) , Base , CurDAG ->

getTargetConstant ( <STR_LIT> , <STR_LIT> ) ) , <NUM_LIT> ) ;


<s> const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; return MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) || MFI -> hasVarSizedObjects ( ) || MFI ->


<s> MachineBasicBlock * Filler :: selectSuccBB ( MachineBasicBlock & B ) const { if ( B . succ_empty ( ) ) return nullptr ; auto & Prob = getAnalysis < MachineBranchProbabilityInfo > ( ) ; MachineBasicBlock * S = * std :: max_element ( B . succ_begin ( ) , B . succ_end ( ) , [ & ] ( const MachineBasicBlock * Dst0 , const MachineBasicBlock * Dst1 ) { return Prob . getEdgeWeight ( & B , Dst0 ) < Prob . getEdgeWeight ( & B , Dst1 ) ; } )


<s> if ( Register :: isVirtualRegister ( DestReg ) && SpillSize == <NUM_LIT> ) { MachineRegisterInfo & MRI = MF -> getRegInfo ( ) ; MRI . constrainRegClass ( DestReg , & <STR_LIT> ) ; } if ( RI . spillSGPRToVGPR ( ) ) FrameInfo . setStackID ( FrameIndex , TargetStackID :: SGPRSpill ) ; BuildMI ( MBB , MI , DL , OpDesc , DestReg ) . addFrameIndex ( FrameIndex ) . addMemOperand ( MMO ) . addReg ( MFI -> getScratchRSrcReg ( ) , RegState :: Implicit ) . addReg ( MFI -> getStackPtrOffsetReg ( ) , RegState :: Implicit ) ; return ; } unsigned Opcode = RI . hasAGPRs ( RC ) ? getAGPRSpillRestoreOpcode ( SpillSize ) : getVGPRSpillRestoreOpcode ( SpillSize ) ; auto MIB = BuildMI ( MBB , MI , DL , get


<s> bool prefersVectorizedAddressing ( )


<s> return Subtarget . isTargetMachO ( ) && ! ( Subtarget . getTargetLowering ( ) -> supportSwiftError ( )

&& Attrs . hasAttrSomewhere ( Attribute :: SwiftError ) ) ;


<s> if ( ! SrcIsSSE && ! DstIsSSE ) { if ( N -> getOpcode ( ) == <STR_LIT> ) continue ; if ( N -> getConstantOperandVal ( <NUM_LIT> ) ) continue ; } MVT MemVT ; if ( N -> getOpcode ( ) == <STR_LIT> ) MemVT = DstVT ; else MemVT = SrcIsSSE ? SrcVT : DstVT ; SDValue MemTmp = CurDAG -> CreateStackTemporary ( MemVT ) ; SDLoc dl ( N ) ; SDValue Store = CurDAG -> getTruncStore ( CurDAG -> getEntryNode ( ) , dl , N -> getOperand ( <NUM_LIT> ) , MemTmp , MachinePointerInfo ( ) , MemVT , false , false , <NUM_LIT> ) ; SDValue Result = CurDAG -> getExtLoad ( <STR_LIT> , dl , DstVT , Store , MemTmp , MachinePointerInfo ( ) , MemVT , false , false , <NUM_LIT> ) ; -- I


<s> rtx src_high_part , src_low_part ; rtx dst_high_part , dst_low_part ; dst_high_part = nds32_di_high_part_subreg ( dst ) ; dst_low_part = nds32_di_low_part_subreg ( dst ) ; src_high_part = nds32_di_high_part_subreg ( src ) ; src_low_part = nds32_di_low_part_subreg ( src ) ; if ( CONST_INT_P ( shiftamount ) ) { if ( INTVAL ( shiftamount ) < <NUM_LIT> ) { rtx ext_start ; ext_start = gen_int_mode ( <NUM_LIT> - INTVAL ( shiftamount ) , SImode ) ; emit_insn ( gen_wext ( dst_high_part , src , ext_start ) ) ; emit_insn ( gen_ashlsi3 ( dst_low_part , src_low_part , shiftamount ) ) ; } else { rtx new_shift_amout = gen_int_mode ( INTVAL ( shiftamount ) - <NUM_LIT> , SImode ) ; emit_insn ( gen_ashlsi3 ( dst_high_part , src_low_part , new_shift_amout ) ) ; emit_move_insn ( dst_low_part , GEN_INT ( <NUM_LIT> ) ) ; } } else { rtx dst_low_part_l32 , dst_high_part_l32 ; rtx dst_low_part_g32 , dst_high_part_g32 ; rtx new_shift_amout , select_reg ; dst_low_part_l32 = gen_reg_rtx ( SImode ) ; dst_high_part_l32 = gen_reg_rtx ( SImode ) ; dst_low_part_g32 = gen_reg_rtx ( SImode ) ; dst_high_part_g32 = gen_reg_rtx ( SImode ) ; new_shift_amout = gen_reg_rtx ( SImode ) ; select_reg = gen_reg_rtx ( SImode ) ; rtx ext_start ; ext_start = gen_reg_rtx ( SImode ) ; emit_insn ( gen_subsi3 ( ext_start , gen_int_mode ( <NUM_LIT> , SImode ) , shiftamount ) ) ; emit_insn ( gen_wext ( dst_high_part_l32 , src , ext_start ) ) ; emit_insn ( gen_cmovzsi ( dst_high_part_l32 , shiftamount , src_high_part , dst_high_part_l32


<s> static SDValue LowerBITCAST ( SDValue Op , SelectionDAG & DAG ) { EVT OpVT = Op . getValueType ( ) ; if ( OpVT != <STR_LIT> && OpVT != <STR_LIT> ) return SDValue ( ) ; assert ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) == <STR_LIT> ) ; SDLoc DL ( Op ) ; Op = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> ,


<s> unsigned NumMaskElts = Mask . size ( ) ; unsigned NumLanes = MaskVT . getSizeInBits ( ) / <NUM_LIT> ; unsigned NumEltsPerLane = NumMaskElts / NumLanes ; bool FloatDomain = MaskVT . isFloatingPoint ( ) ; if ( ! FloatDomain && ( ( MaskVT . is128BitVector ( ) && Subtarget . hasSSE2 ( ) ) || ( MaskVT . is256BitVector ( ) && Subtarget . hasAVX2 ( ) ) ) ) { for ( unsigned Shift = <NUM_LIT> ; Shift != NumEltsPerLane ; ++ Shift ) { bool IsVSHLDQ = true ; bool IsVSRLDQ = true ; for ( unsigned Lane = <NUM_LIT> ; Lane != NumLanes ; ++ Lane ) { unsigned Base = Lane * NumEltsPerLane ; unsigned Ofs = NumEltsPerLane - Shift ; IsVSHLDQ &= isUndefOrZeroInRange ( Mask , Base , Shift ) ; IsVSHLDQ &= isSequentialOrUndefInRange ( Mask , Base + Shift , Ofs , Base ) ; IsVSRLDQ &= isUndefOrZeroInRange ( Mask , Base + Ofs , Shift ) ; IsVSRLDQ &= isSequentialOrUndefInRange ( Mask , Base , Ofs , Base + Shift ) ; if ( ! IsVSHLDQ && ! IsVSRLDQ ) break ; } if ( IsVSHLDQ ) { Shuffle = <STR_LIT> ; ShuffleVT = <STR_LIT> ( <STR_LIT> , NumLanes * <NUM_LIT> ) ; PermuteImm = Shift * ( MaskVT . getScalarSizeInBits ( ) / <NUM_LIT> ) ; return true ; } if ( IsVSRLDQ ) { Shuffle = <STR_LIT> ; ShuffleVT = <STR_LIT> ( <STR_LIT> , NumLanes * <NUM_LIT> ) ; PermuteImm = Shift * ( MaskVT . getScalarSizeInBits ( ) / <NUM_LIT> ) ; return true ; } } } for ( int M : Mask ) { if ( M == SM_SentinelZero ) return false ; assert ( SM_SentinelUndef <= M && M < ( int ) Mask . size ( ) && <STR_LIT> ) ; } unsigned InputSizeInBits = MaskVT . getSizeInBits ( ) ; unsigned MaskScalarSizeInBits = InputSizeInBits / Mask . size ( ) ; MVT MaskEltVT = <STR_LIT> ( MaskScalarSizeInBits ) ; if ( MaskScalarSizeInBits == <NUM_LIT> ) { SmallVector < int , <NUM_LIT> > RepeatedMask ; if ( is128BitLaneRepeatedShuffleMask ( MaskEltVT , Mask , RepeatedMask ) ) { ArrayRef < int > LoMask ( Mask . data ( ) + <NUM_LIT> , <NUM_LIT> ) ; ArrayRef < int > HiMask ( Mask . data ( ) + <NUM_LIT> , <NUM_LIT> ) ; if ( isUndefOrInRange ( LoMask , <NUM_LIT> , <NUM_LIT> ) && isSequentialOrUndefInRange ( HiMask ,


<s> assert ( Bytes > <NUM_LIT> && <STR_LIT> ) ; Chain = emitCLC ( DAG , DL , Chain , Src1 , Src2 , Bytes ) ; SDValue Glue = Chain . getValue ( <NUM_LIT> ) ; return std :: make_pair ( addIPMSequence ( DL , Glue ,


<s> case ADDC : return <STR_LIT> ; case SUB : return <STR_LIT> ; case SUBB : return <STR_LIT> ; case AND : return <STR_LIT> ; case OR : return <STR_LIT> ; case XOR


<s> return <NUM_LIT> ; } unsigned Count = <NUM_LIT> ; <STR_LIT> CC = ( <STR_LIT> ) Cond [ <NUM_LIT> ] . getImm ( ) ; auto & CondMI = * BuildMI ( & MBB , DL , getBrCond ( CC ) ) . addMBB ( TBB ) ; if ( BytesAdded ) * BytesAdded += getInstSizeInBytes ( CondMI ) ; ++ Count ; if ( FBB ) { auto & MI = * BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addMBB ( FBB ) ; if ( BytesAdded ) * BytesAdded +=


<s> MachineRegisterInfo & MRI = MI . getParent ( ) -> getParent ( ) -> getRegInfo ( ) ; MachineInstr * DefMI = canFoldIntoMOVCC ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) , MRI , this ) ; bool Invert = ! DefMI ; if ( ! DefMI ) DefMI = canFoldIntoMOVCC ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) , MRI , this ) ; if ( ! DefMI ) return nullptr ; MachineOperand FalseReg = MI . getOperand ( Invert ? <NUM_LIT> : <NUM_LIT> ) ; unsigned DestReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; const TargetRegisterClass * PreviousClass = MRI . getRegClass ( FalseReg . getReg ( ) ) ; if ( ! MRI . constrainRegClass ( DestReg , PreviousClass ) ) return nullptr ; MachineInstrBuilder NewMI = BuildMI ( * MI . getParent ( ) , MI , MI . getDebugLoc ( ) , DefMI -> getDesc ( ) , DestReg ) ; const MCInstrDesc & DefDesc = DefMI -> getDesc ( ) ; for ( unsigned i = <NUM_LIT> , e = DefDesc . getNumOperands ( ) ; i != e && ! DefDesc . OpInfo [ i ] . isPredicate ( ) ; ++ i ) NewMI . addOperand ( DefMI -> getOperand ( i ) ) ; unsigned CondCode = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( Invert ) NewMI . addImm ( <STR_LIT> ( <STR_LIT> ( CondCode ) ) ) ; else NewMI . addImm ( CondCode ) ; NewMI . addOperand ( MI . getOperand ( <NUM_LIT> ) ) ; if ( NewMI -> hasOptionalDef ( ) ) AddDefaultCC ( NewMI ) ; FalseReg . setImplicit ( ) ; NewMI . addOperand (


<s> const char * <ISA_LIT>AsmPrinter :: getPassName ( ) const { return <STR_LIT>


<s> ParseSubtargetFeatures ( CPUName , CPUName , FS ) ; InstrItins = getInstrItineraryForCPU ( CPUName ) ; stackAlignment = <NUM_LIT>


<s> SDLoc DL ( Op ) ; EVT VT = Op . getValueType ( ) ; switch ( IntrinsicID ) { default : return Op ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , DL , VT , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , DL , VT , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; case


<s> if ( ( CC == <STR_LIT> ) && ! ( ( <STR_LIT> ( SetCC . getOperand ( <NUM_LIT> ) . getNode ( ) , SplatVal ) && SplatVal . isOneValue ( ) ) || ( <STR_LIT> ( SetCC . getOperand ( <NUM_LIT> ) . getNode ( ) ) ) ) ) return false ; if ( ( CC == <STR_LIT> ) && ! ( <STR_LIT> ( SetCC . getOperand ( <NUM_LIT> ) . getNode ( ) ) || <STR_LIT> ( SetCC . getOperand ( <NUM_LIT> ) . getNode ( ) ) ) ) return false ; if ( SelectOp1 . getOpcode ( ) != <STR_LIT> ) return false ; Op0 = SelectOp1 . getOperand ( <NUM_LIT> ) ; Op1 = SelectOp1 . getOperand


<s> static MCRegisterInfo * create<ISA_LIT>MCRegisterInfo ( StringRef TT ) { MCRegisterInfo * X = new MCRegisterInfo


<s> if ( ! GlobalsEmitted ) { emitGlobals ( * MF -> getFunction ( ) -> getParent ( ) ) ; GlobalsEmitted = true ; } MRI = & MF -> getRegInfo ( ) ; F = MF -> getFunction ( ) ; emitLinkageDirective ( F , O ) ; if ( llvm :: isKernelFunction ( * F ) ) O << <STR_LIT> ; else { O << <STR_LIT> ; printReturnValStr ( * MF ,


<s> return SelectFlatOffset < true > ( N , Addr ,


<s> PM . add ( create<ISA_LIT>DelaySlotFillerPass ( get<ISA_LIT>TargetMachine ( ) ) ) ; return


<s> std :: string Msg = <STR_LIT> ; unsigned Mask = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> ; i < ( sizeof ( ErrorInfo ) * <NUM_LIT> - <NUM_LIT> ) ; ++ i ) { if ( ErrorInfo & Mask ) { Msg += <STR_LIT> ; Msg += getSubtargetFeatureName ( ErrorInfo & Mask ) ; } Mask <<= <NUM_LIT> ; } return Error ( IDLoc , Msg ) ; } case Match_InvalidOperand : { SMLoc ErrorLoc = IDLoc ; if ( ErrorInfo != ~ <NUM_LIT> ) { if ( ErrorInfo >= Operands . size ( ) ) return Error ( IDLoc , <STR_LIT> ) ; ErrorLoc = ( ( <ISA_LIT>Operand * ) Operands [ ErrorInfo ] ) -> getStartLoc ( ) ; if ( ErrorLoc == SMLoc ( ) ) ErrorLoc = IDLoc ; } return Error ( ErrorLoc , <STR_LIT> ) ; } case Match_MnemonicFail : return Error ( IDLoc , <STR_LIT> , ( ( <ISA_LIT>Operand * ) Operands [ <NUM_LIT> ] ) -> getLocRange ( ) ) ; case Match_RequiresNotITBlock : return Error ( IDLoc , <STR_LIT> ) ; case Match_RequiresITBlock : return Error ( IDLoc , <STR_LIT> ) ; case Match_RequiresV6 : return Error ( IDLoc , <STR_LIT> ) ; case Match_RequiresThumb2


<s> break ; } SmallVector < SDValue , <NUM_LIT> > Ops ; for ( unsigned i = <NUM_LIT> ; i < NumElts ; ++ i ) Ops . push_back ( N -> getOperand ( i + <NUM_LIT> ) ) ; Ops . push_back ( CurDAG -> getTargetConstant ( ParamVal , DL , <STR_LIT> ) ) ; Ops . push_back ( CurDAG -> getTargetConstant ( OffsetVal , DL , <STR_LIT> ) ) ; Ops . push_back ( Chain ) ; Ops . push_back ( Flag ) ; Optional < unsigned > Opcode = <NUM_LIT> ; switch ( N -> getOpcode ( ) ) { default : switch ( NumElts ) { default : return false ; case <NUM_LIT> : Opcode = pickOpcodeForVT ( Mem -> getMemoryVT ( ) . getSimpleVT ( ) . SimpleTy , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> ) ; break ; case <NUM_LIT> : Opcode = pickOpcodeForVT ( Mem -> getMemoryVT ( ) . getSimpleVT ( ) . SimpleTy , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> ) ; break ; case <NUM_LIT> : Opcode = pickOpcodeForVT ( Mem -> getMemoryVT ( ) . getSimpleVT ( ) . SimpleTy , <STR_LIT> , <STR_LIT> , <STR_LIT> , None , <STR_LIT> , <STR_LIT> , <STR_LIT> , None ) ; break ; } if ( ! Opcode ) return false ; break ; case <STR_LIT> : { Opcode = <STR_LIT> ; SDValue CvtNone = CurDAG -> getTargetConstant ( <STR_LIT> :: NONE , DL , <STR_LIT> ) ; SDNode * Cvt = CurDAG -> getMachineNode ( <STR_LIT> , DL , <STR_LIT> , Ops [ <NUM_LIT> ] , CvtNone ) ; Ops [ <NUM_LIT> ] = SDValue ( Cvt , <NUM_LIT> ) ; break ; } case <STR_LIT> : { Opcode = <STR_LIT> ; SDValue CvtNone = CurDAG -> getTargetConstant ( <STR_LIT> :: NONE , DL , <STR_LIT> ) ; SDNode * Cvt = CurDAG -> getMachineNode ( <STR_LIT> , DL , <STR_LIT> , Ops [ <NUM_LIT> ] , CvtNone ) ; Ops [ <NUM_LIT> ] = SDValue


<s> rtx insn ; if ( val == NULL_RTX || INTVAL ( val ) == <NUM_LIT> ) { gcc_assert ( dest != src ) ; insn = emit_move_insn ( dest , src ) ; } else if ( ok_for_max_constant ( INTVAL ( val ) ) ) insn = emit_insn ( gen_addsi3 ( dest , src , val ) ) ; else { val = gen_rtx_CONST ( SImode , gen_rtx_UNSPEC ( SImode , gen_rtvec ( <NUM_LIT> , val ) , UNSPEC_CONST ) ) ; insn = emit_insn ( gen_addsi3 ( dest , src


<s> return DecodeMem ( Inst , insn , Address , Decoder , false


<s> struct riscv_arg_info arg ; riscv_get_arg_info ( & arg , get_cumulative_args ( cum ) , mode , type , named


<s> if ( ! f64RetAssign ( ValNo , ValVT , LocVT , LocInfo , State ) ) return false ; if ( LocVT == <STR_LIT> && ! f64RetAssign ( ValNo , ValVT , LocVT , LocInfo , State


<s> static int m32c_pushm_popm ( Push_Pop_Type ppt ) { int reg_mask = <NUM_LIT> ; int byte_count = <NUM_LIT> , bytes ; int i ; rtx dwarf_set [ PUSHM_N ] ; int n_dwarfs = <NUM_LIT> ; int nosave_mask = <NUM_LIT> ; if ( crtl -> return_rtx && GET_CODE ( crtl -> return_rtx ) == PARALLEL && ! ( crtl -> calls_eh_return || cfun -> machine -> is_interrupt ) ) { rtx exp = XVECEXP ( crtl -> return_rtx , <NUM_LIT> , <NUM_LIT> ) ; rtx rv = XEXP ( exp , <NUM_LIT> ) ; int rv_bytes = GET_MODE_SIZE ( GET_MODE ( rv ) ) ; if ( rv_bytes > <NUM_LIT> ) nosave_mask |= <NUM_LIT> ; else nosave_mask |= <NUM_LIT> ; if ( rv_bytes > <NUM_LIT> ) nosave_mask |= <NUM_LIT> ; } for ( i = <NUM_LIT> ; i < ( int ) PUSHM_N ; i ++ ) { if ( ! need_to_save ( pushm_info [ i ] . reg1 ) ) continue ; if ( pushm_info [ i ] . bit & nosave_mask ) continue ; reg_mask |= pushm_info [ i ] . bit ; bytes = TARGET_A16 ? pushm_info [ i ] . a16_bytes : pushm_info [ i ] . a24_bytes ; if ( ppt == PP_pushm ) { machine_mode mode = ( bytes == <NUM_LIT> ) ? HImode : SImode ; rtx addr ; addr = stack_pointer_rtx ; if ( byte_count != <NUM_LIT> ) addr = gen_rtx_PLUS ( GET_MODE ( addr ) , addr , GEN_INT ( byte_count ) ) ; dwarf_set [ n_dwarfs ++ ] = gen_rtx_SET ( gen_rtx_MEM ( mode , addr ) , gen_rtx_REG ( mode , pushm_info [ i ] . reg1 ) ) ; F ( dwarf_set [ n_dwarfs - <NUM_LIT> ] ) ; } byte_count += bytes ; } if ( cfun -> machine -> is_interrupt ) { cfun -> machine -> intr_pushm = reg_mask & <NUM_LIT> ; reg_mask = <NUM_LIT> ; byte_count = <NUM_LIT> ; } if ( cfun -> machine -> is_interrupt ) for ( i = MEM0_REGNO ; i <= MEM7_REGNO ; i ++ ) if ( need_to_save ( i ) ) { byte_count += <NUM_LIT> ; cfun -> machine -> intr_pushmem [ i - MEM0_REGNO ] = <NUM_LIT> ; } if ( ppt == PP_pushm && byte_count ) { rtx note = gen_rtx_SEQUENCE ( VOIDmode , rtvec_alloc ( n_dwarfs + <NUM_LIT> ) ) ; rtx pushm ; if ( reg_mask ) { XVECEXP ( note , <NUM_LIT> , <NUM_LIT> ) = gen_rtx_SET ( stack_pointer_rtx , gen_rtx_PLUS ( GET_MODE ( stack_pointer_rtx ) , stack_pointer_rtx , GEN_INT ( - byte_count ) ) ) ; F ( XVECEXP ( note , <NUM_LIT> , <NUM_LIT> ) ) ; for ( i = <NUM_LIT> ; i < n_dwarfs ; i ++ ) XVECEXP ( note , <NUM_LIT> , i + <NUM_LIT> ) = dwarf_set [ i ] ; pushm = F ( emit_insn ( gen_pushm ( GEN_INT ( reg_mask )


<s> return ( ( int_size_in_bytes ( type ) > ( <NUM_LIT> * UNITS_PER_WORD ) ) || ( int_size_in_bytes ( type ) ==


<s> else if ( recog_memoized ( prev ) == CODE_FOR_block_branch_redirect ) need_block = <NUM_LIT> ; } if ( GET_CODE ( PATTERN ( jump ) ) == RETURN ) { if ( ! need_block ) return prev ; return emit_insn_before ( gen_block_branch_redirect ( const0_rtx ) , jump ) ; } dest = XEXP ( SET_SRC ( PATTERN ( jump ) ) , <NUM_LIT> ) ; if ( optimize && ( INSN_ADDRESSES ( INSN_UID ( dest ) ) - addr + ( unsigned ) <NUM_LIT> > <NUM_LIT> + <NUM_LIT> ) ) { rtx_insn * scan ; unsigned attempt = <NUM_LIT> , used ; int jump_left = flag_expensive_optimizations + <NUM_LIT> ; for ( scan = jump ; ( scan = PREV_INSN ( scan ) ) ; ) { enum rtx_code code ; if ( scan -> deleted ( ) ) continue ; code = GET_CODE ( scan ) ; if ( code == CODE_LABEL || code == JUMP_INSN ) break ; if ( code == INSN && GET_CODE ( PATTERN ( scan ) ) != USE && GET_CODE ( PATTERN ( scan ) ) != CLOBBER && get_attr_in_delay_slot ( scan ) == IN_DELAY_SLOT_YES ) { attempt &= ~ regs_used ( PATTERN ( scan ) , <NUM_LIT> ) ; break ; } } for ( used = dead = <NUM_LIT> , scan = JUMP_LABEL_AS_INSN ( jump ) ; ( scan = NEXT_INSN ( scan ) ) ; ) { enum rtx_code code ; if ( scan -> deleted ( ) ) continue ; code = GET_CODE ( scan ) ; if ( INSN_P ( scan ) ) { used |= regs_used ( PATTERN ( scan ) , <NUM_LIT> ) ; if ( code == CALL_INSN ) used |= regs_used ( CALL_INSN_FUNCTION_USAGE ( scan ) , <NUM_LIT> ) ; dead |= ( used >> <NUM_LIT> ) &


<s> n = expand_binop ( SImode , lshr_optab , n , shift , NULL_RTX , <NUM_LIT> , OPTAB_LIB_WIDEN ) ; emit_move_insn ( o , gen_lowpart ( mode


<s> unsigned ThumbBit = <NUM_LIT> ; unsigned MovtBit = <NUM_LIT> ; switch ( ( unsigned ) Fixup . getKind ( ) ) { default : break ; case <STR_LIT> : MovtBit = <NUM_LIT> ; if ( A_SD -> getFlags ( ) & SF_ThumbFunc ) FixedValue &= <NUM_LIT> ; break ; case <STR_LIT> : if ( A_SD -> getFlags ( ) & SF_ThumbFunc ) FixedValue &= <NUM_LIT> ; MovtBit = <NUM_LIT> ; case <STR_LIT> : ThumbBit = <NUM_LIT> ; break ; } if ( Type == MachO :: <ISA_LIT>_RELOC_HALF_SECTDIFF ) { uint32_t OtherHalf = MovtBit ? ( FixedValue & <NUM_LIT> ) : ( ( FixedValue & <NUM_LIT> ) >> <NUM_LIT> ) ; MachO :: any_relocation_info MRE ; MRE . r_word0 = ( ( OtherHalf << <NUM_LIT> ) | ( MachO :: <ISA_LIT>_RELOC_PAIR << <NUM_LIT> ) | ( MovtBit << <NUM_LIT> ) | ( ThumbBit << <NUM_LIT> ) | ( IsPCRel << <NUM_LIT> ) | MachO :: R_SCATTERED ) ; MRE . r_word1 = Value2 ; Writer -> addRelocation ( Fragment -> getParent ( ) , MRE ) ; } MachO :: any_relocation_info MRE ; MRE . r_word0 = ( ( FixupOffset << <NUM_LIT> ) | ( Type << <NUM_LIT> ) | ( MovtBit << <NUM_LIT> ) | ( ThumbBit << <NUM_LIT> ) | ( IsPCRel << <NUM_LIT> ) | MachO :: R_SCATTERED ) ; MRE . r_word1 = Value ; Writer -> addRelocation ( Fragment -> getParent ( )


<s> void LLVMInitialize<ISA_LIT>TargetInfo ( ) { TargetRegistry :: RegisterTarget ( getThe<ISA_LIT>Target ( ) , <STR_LIT> , <STR_LIT> , <STR_LIT> , [ ] ( Triple :: ArchType ) {


<s> break ; } } } } if ( ! ContainsFPCode ) { const BasicBlock * LLVMBB = MBB -> getBasicBlock ( ) ; const PHINode * PN ; for ( succ_const_iterator SI = succ_begin ( LLVMBB ) , E = succ_end ( LLVMBB ) ; ! ContainsFPCode && SI != E ; ++ SI ) { for ( BasicBlock :: const_iterator II = SI -> begin ( ) ; ( PN = dyn_cast < PHINode > ( II ) ) ; ++ II ) { if ( PN -> getType ( ) == Type :: <ISA_LIT>_FP80Ty || ( ! Subtarget . hasSSE1 ( ) && PN -> getType ( ) -> isFloatingPoint ( ) ) || ( ! Subtarget . hasSSE2 ( ) && PN -> getType ( ) == Type :: DoubleTy ) ) { ContainsFPCode = true ; break ; } } } } if ( ContainsFPCode ) { BuildMI ( * MBB , MBBI -> getFirstTerminator ( ) , DebugLoc :: getUnknownLoc ( ) , MF . getTarget ( ) . getInstrInfo ( ) -> get ( <STR_LIT> ) ) ; ++ NumFPKill ; Changed = true ; } } return Changed


<s> return ( __m256i ) __builtin_ia32_pmovqd512_mask ( ( __v8di ) __A , ( __v8si )


<s> Instruction * TpcLoopOpt :: prologue ( BasicBlock * outerBB , BasicBlock * innerBB ) { Instruction * insertElement1 = dyn_cast < Instruction > ( LoadPtrList [ <NUM_LIT> ] -> getOperand ( <NUM_LIT> ) ) -> clone ( ) ; InsertElement2 = dyn_cast < Instruction > ( StorePtrList [ <NUM_LIT> ] -> getOperand ( <NUM_LIT> ) ) -> clone ( ) ; insertElement1 -> setOperand ( <NUM_LIT> , dyn_cast < Instruction > ( insertElement1 -> getOperand ( <NUM_LIT> ) ) -> getOperand ( <NUM_LIT> ) ) ; InsertElement2 -> setOperand ( <NUM_LIT> , dyn_cast < Instruction > ( InsertElement2 -> getOperand ( <NUM_LIT> ) ) -> getOperand ( <NUM_LIT> ) ) ; insertElement1 -> setOperand ( <NUM_LIT> , InducationPhi -> getOperand ( <NUM_LIT> ) ) ; InsertElement2 -> setOperand ( <NUM_LIT> , InducationPhi -> getOperand ( <NUM_LIT> ) ) ; Instruction * lastAdd = incInstruction ( innerBB , outerBB , LoadId , insertElement1 ,


<s> if ( TREE_CODE ( decl ) != VAR_DECL || TREE_TYPE (


<s> bool <ISA_LIT>TargetLowering :: CanLowerReturn ( CallingConv :: ID CallConv , MachineFunction & MF , bool IsVarArg , const SmallVectorImpl < <STR_LIT> > & Outs , LLVMContext & Context ) const { SmallVector < CCValAssign , <NUM_LIT> > RVLocs ; CCState CCInfo ( CallConv , IsVarArg , MF , RVLocs , Context ) ; Optional < unsigned > FirstMaskArgument ; if ( Subtarget . hasVInstructions ( ) ) FirstMaskArgument = preAssignMask ( Outs ) ; for ( unsigned i = <NUM_LIT> , e = Outs . size ( ) ; i != e ; ++ i ) { MVT VT = Outs [


<s> SMLoc S = Parser . getTok ( ) . getLoc ( ) ; if ( Parser . getTok ( ) . isNot ( AsmToken :: LCurly ) ) return MatchOperand_NoMatch ; Parser . Lex ( ) ; const MCExpr * Expr ; SMLoc Loc = Parser . getTok ( ) . getLoc ( ) ; if ( getParser ( ) . parseExpression ( Expr ) ) { Error ( Loc , <STR_LIT> ) ; return MatchOperand_ParseFail ; } const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( Expr ) ; if ( ! CE || CE -> getValue ( ) < <NUM_LIT> || CE ->


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> :


<s> unsigned Dst = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned ListPtr = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; LLT PtrTy = MRI . getType ( ListPtr ) ; LLT IntPtrTy = LLT :: scalar ( PtrTy . getSizeInBits ( ) ) ; const unsigned PtrSize = PtrTy . getSizeInBits ( ) / <NUM_LIT> ; unsigned List = MRI . createGenericVirtualRegister ( PtrTy ) ; MIRBuilder . buildLoad ( List , ListPtr , * MF . getMachineMemOperand ( MachinePointerInfo ( ) , MachineMemOperand :: MOLoad , PtrSize , PtrSize ) ) ; unsigned DstPtr ; if ( Align > PtrSize ) { auto AlignMinus1 = MIRBuilder . buildConstant ( IntPtrTy , Align - <NUM_LIT> ) ; unsigned ListTmp = MRI . createGenericVirtualRegister (


<s> auto * GV = dyn_cast < GlobalVariable > ( M . getOrInsertGlobal ( Name , IRB . getInt32Ty ( ) ) ) ; if ( ! GV ) report_fatal_error ( Twine ( <STR_LIT> ) + Name


<s> SmallVector < int , <NUM_LIT> > BlendMask ; for ( unsigned i = <NUM_LIT> ; i != NumElts ; ++ i ) BlendMask . push_back ( i == IdxVal ? i + NumElts : i ) ; return DAG . getVectorShuffle ( VT , dl , N0 , N1SplatVec , BlendMask ) ; } SDValue V = extract128BitVector ( N0 , IdxVal , DAG , dl ) ; unsigned IdxIn128 = IdxVal & ( NumEltsIn128 - <NUM_LIT> ) ; V = DAG . getNode ( <STR_LIT> , dl , V . getValueType ( ) , V , N1 , DAG . getIntPtrConstant ( IdxIn128 , dl ) ) ; return insert128BitVector ( N0 , V , IdxVal , DAG , dl ) ; } assert ( VT . is128BitVector ( ) && <STR_LIT> ) ; if ( IdxVal == <NUM_LIT> && <STR_LIT> ( N0 . getNode ( ) ) ) { if ( EltVT == <STR_LIT> || EltVT == <STR_LIT> || EltVT == <STR_LIT> || EltVT == <STR_LIT> || EltVT == <STR_LIT> ) { N1 = DAG . getNode ( <STR_LIT> , dl , VT , N1 ) ; return getShuffleVectorZeroOrUndef ( N1 , <NUM_LIT> , true , Subtarget , DAG ) ; } if ( EltVT == <STR_LIT> || EltVT == <STR_LIT> ) { N1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N1 ) ; MVT ShufVT = <STR_LIT> ( <STR_LIT> , VT . getSizeInBits ( ) / <NUM_LIT> ) ; N1 = DAG . getNode ( <STR_LIT> , dl , ShufVT , N1 ) ; N1 = getShuffleVectorZeroOrUndef ( N1 , <NUM_LIT> , true , Subtarget , DAG ) ; return DAG . getBitcast ( VT , N1 ) ; } } if ( VT == <STR_LIT> || ( VT == <STR_LIT> && Subtarget . hasSSE41 ( ) ) ) { unsigned Opc ; if ( VT == <STR_LIT> ) { assert ( Subtarget . hasSSE2 ( ) && <STR_LIT> ) ; Opc = <STR_LIT> ; } else { assert ( VT == <STR_LIT> && <STR_LIT> ) ; assert ( Subtarget . hasSSE41 ( ) && <STR_LIT> ) ; Opc = <STR_LIT> ; } assert ( N1 . getValueType ( ) != <STR_LIT> && <STR_LIT> ) ; N1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N1 ) ; N2 = DAG . getTargetConstant ( IdxVal , dl , <STR_LIT> ) ; return DAG . getNode ( Opc , dl , VT , N0 , N1 , N2 ) ; } if ( Subtarget . hasSSE41 ( ) ) { if ( EltVT == <STR_LIT> ) { bool MinSize = DAG . getMachineFunction ( ) . getFunction ( ) . hasMinSize ( ) ; if ( IdxVal == <NUM_LIT> && ( ! MinSize || ! MayFoldLoad ( N1 ) ) ) { N1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N1 ) ; return DAG . getNode ( <STR_LIT> , dl , VT , N0 , N1 , DAG . getTargetConstant ( <NUM_LIT>


<s> EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( VT . getSizeInBits ( ) . getKnownMinSize ( ) > <STR_LIT> ) return SDValue ( ) ; EVT ContainerVT = VT ; if ( ContainerVT . isInteger ( ) ) ContainerVT = getSVEContainerType ( ContainerVT ) ; SDVTList VTs = DAG . getVTList ( ContainerVT , <STR_LIT> ) ; SDValue Ops [ ] = { N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , DAG . getValueType ( VT ) } ; SDValue Load = DAG . getNode ( Opc , DL , VTs , Ops ) ; SDValue LoadChain = SDValue ( Load . getNode ( )


<s> if ( SDValue NewCMov = combineToExtendCMOV ( N , DAG ) ) return NewCMov ; if ( ! DCI . isBeforeLegalizeOps ( ) ) return SDValue ( ) ; if ( InVT == <STR_LIT> && N0 . getOpcode ( ) == <STR_LIT> && isAllOnesConstant ( N0 . getOperand ( <NUM_LIT> ) ) && N0 . hasOneUse ( ) ) { SDValue Zext = DAG . getNode ( <STR_LIT> , DL , VT , N0 . getOperand ( <NUM_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , DL , VT , Zext , DAG . getConstant ( <NUM_LIT> , DL , VT ) ) ; } if ( SDValue V = combineToExtendVectorInReg ( N , DAG , DCI , Subtarget ) ) return V ; if ( SDValue V = combineToExtendBoolVectorInReg ( N , DAG , DCI , Subtarget ) ) return V ; if ( VT . isVector ( ) ) if ( SDValue R = WidenMaskArithmetic ( N , DAG , DCI


<s> return selectShiftedRegister ( Root , true )


<s> const TargetRegisterClass * GPRC = & <STR_LIT> ; unsigned Reg = MF . getRegInfo ( ) . createVirtualRegister ( GPRC ) ; unsigned DestReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; assert ( MI . definesRegister ( DestReg ) && <STR_LIT> ) ; addFrameReference ( BuildMI ( MBB , II , dl , TII . get ( <STR_LIT> ) , Reg ) , FrameIndex ) ; BuildMI ( MBB , II , dl , TII . get ( <STR_LIT> ) , DestReg ) . addReg ( Reg , RegState :: Kill ) ; MBB . erase (


<s> encodeInstruction ( const MCInst & MI , raw_ostream & OS , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { uint32_t Binary = getBinaryCodeForInstr ( MI , Fixups , STI ) ; unsigned Opcode = MI . getOpcode ( ) ; if ( ( Opcode != <STR_LIT> ) && ( Opcode != <STR_LIT> ) && ! Binary ) llvm_unreachable ( <STR_LIT> ) ; const MCInstrDesc & Desc = MCII . get ( MI


<s> setAction ( { Op , s32 } , Legal ) ; setAction ( { Op , <NUM_LIT> , s1 } , Legal ) ; } for ( unsigned MemOp : { G_LOAD , G_STORE } ) { for ( auto Ty : { s8 , s16 , s32 , p0 } ) setAction ( { MemOp , Ty } , Legal ) ; setAction ( { MemOp , s1 } , WidenScalar ) ; setAction ( { MemOp , <NUM_LIT> , p0 } , Legal ) ; } setAction ( { G_FRAME_INDEX , p0 } , Legal ) ; setAction ( { G_GLOBAL_VALUE , p0 } , Legal ) ; setAction ( { G_GEP , p0 } , Legal ) ; setAction ( { G_GEP , <NUM_LIT> , s32 } , Legal ) ; for ( auto Ty : { s1 , s8 , s16 } ) setAction ( { G_GEP , <NUM_LIT> , Ty } , WidenScalar ) ; for ( auto Ty : { s8 , s16 , s32 , p0 } ) setAction ( { TargetOpcode :: G_CONSTANT , Ty } , Legal ) ; setAction ( { TargetOpcode :: G_CONSTANT , s1 } , WidenScalar ) ; setAction ( { TargetOpcode :: G_CONSTANT , s64 } , NarrowScalar ) ; for ( auto Ty : { s8 , s16 , s32 } ) { setAction ( { G_ZEXT , Ty } , Legal ) ; setAction ( { G_SEXT , Ty } , Legal ) ; } for ( auto Ty : { s1 , s8 , s16 } ) { setAction ( { G_ZEXT , <NUM_LIT> , Ty } , Legal ) ; setAction ( { G_SEXT , <NUM_LIT> , Ty } , Legal ) ; } setAction ( { G_ICMP , s1 } , Legal


<s> assert ( ( SegReg || BaseReg || IndexReg || DefaultBaseReg ) && <STR_LIT> ) ; assert ( ( ( Scale == <NUM_LIT> || Scale == <NUM_LIT> || Scale == <NUM_LIT> || Scale == <NUM_LIT> ) ) && <STR_LIT> ) ; auto Res = std :: make_unique < <ISA_LIT>Operand > ( Memory , StartLoc , EndLoc ) ; Res -> Mem . SegReg = SegReg ; Res -> Mem .


<s> const <ISA_LIT>Subtarget & ST = DAG -> MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; const MachineInstr * AMI = ASU -> getInstr ( ) ; if ( ! AMI || AMI -> isPseudo ( ) || AMI -> isTransient ( ) || ( Preds && ! shouldScheduleAdjacent ( * TII , ST , nullptr , AMI ) ) || ( ! Preds && ! shouldScheduleAdjacent ( * TII , ST , AMI , nullptr ) ) ) return false ; for ( SDep & BDep : APreds ) { if ( BDep . isWeak ( ) ) continue ; SUnit * BSU = BDep . getSUnit ( ) ; const MachineInstr * BMI = BSU -> getInstr ( ) ; if ( ! BMI || BMI -> isPseudo ( ) || BMI -> isTransient ( ) || ( Preds && ! shouldScheduleAdjacent ( * TII , ST , BMI , AMI ) ) || ( ! Preds && ! shouldScheduleAdjacent ( * TII , ST , AMI , BMI ) ) ) continue ; if ( Preds ) DAG -> addEdge ( ASU , SDep ( BSU , SDep :: Cluster ) ) ; else DAG -> addEdge ( BSU , SDep ( ASU , SDep :: Cluster ) ) ; for ( SDep & Dep : APreds ) if ( Dep . getSUnit ( ) == BSU ) Dep . setLatency ( <NUM_LIT> ) ; auto & BSuccs = Preds ? BSU -> Succs : BSU -> Preds ; for ( SDep & Dep : BSuccs ) if ( Dep . getSUnit ( ) == ASU ) Dep . setLatency ( <NUM_LIT> ) ; ++


<s> bool <ISA_LIT>AsmParser :: ParseIntelMemoryOperandSize ( unsigned & Size ) { Size = StringSwitch < unsigned > ( getTok ( ) . getString ( ) ) . Cases ( <STR_LIT> , <STR_LIT> , <NUM_LIT> ) . Cases ( <STR_LIT> , <STR_LIT> , <NUM_LIT> ) . Cases ( <STR_LIT> , <STR_LIT> , <NUM_LIT> ) . Cases ( <STR_LIT> , <STR_LIT> , <NUM_LIT> ) . Cases ( <STR_LIT> , <STR_LIT> , <NUM_LIT> ) . Cases ( <STR_LIT> , <STR_LIT> , <NUM_LIT> ) . Cases ( <STR_LIT> , <STR_LIT> , <NUM_LIT> ) . Cases ( <STR_LIT> , <STR_LIT> , <NUM_LIT> ) . Cases ( <STR_LIT> , <STR_LIT> , <NUM_LIT> ) . Cases ( <STR_LIT> , <STR_LIT> , <NUM_LIT> ) . Cases ( <STR_LIT> , <STR_LIT> , <NUM_LIT> ) . Cases ( <STR_LIT> , <STR_LIT> , <NUM_LIT> ) . Cases ( <STR_LIT> , <STR_LIT> , <NUM_LIT> ) . Cases ( <STR_LIT> , <STR_LIT> , <NUM_LIT> ) . Cases ( <STR_LIT> , <STR_LIT> , - <NUM_LIT> ) . Default ( <NUM_LIT> ) ; if ( Size ) { const AsmToken & Tok = Lex


<s> case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> :


<s> processFunctionBeforeCalleeSavedScan ( MachineFunction & MF , RegScavenger * RS ) const { MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; if ( MF . getFrameInfo ( ) -> hasCalls ( ) ) MRI . setPhysRegUsed


<s> return new <ISA_LIT>PassConfig ( this ,


<s> if ( I -> mayLoad ( ) ) return false ; if ( I -> getOpcode ( ) == <STR_LIT> || I -> getOpcode ( ) == <STR_LIT> ) return false ; return


<s> bool IsLE = DAG . getDataLayout ( ) . isLittleEndian ( ) ; if ( ShuffleKind == <NUM_LIT> ) { if ( IsLE ) return false ; for ( unsigned i = <NUM_LIT> ; i != <NUM_LIT> ; i += <NUM_LIT> ) if ( ! isConstantOrUndef ( N -> getMaskElt ( i ) , i * <NUM_LIT> + <NUM_LIT> ) || ! isConstantOrUndef ( N -> getMaskElt ( i + <NUM_LIT> ) , i * <NUM_LIT> + <NUM_LIT> ) ) return false ; } else if ( ShuffleKind == <NUM_LIT> ) { if ( ! IsLE ) return false ; for ( unsigned i = <NUM_LIT> ; i != <NUM_LIT> ; i += <NUM_LIT> ) if ( ! isConstantOrUndef ( N -> getMaskElt ( i ) , i * <NUM_LIT> ) || ! isConstantOrUndef ( N -> getMaskElt ( i + <NUM_LIT> ) , i * <NUM_LIT> + <NUM_LIT> ) ) return false ; } else if ( ShuffleKind == <NUM_LIT> ) { unsigned j = IsLE ? <NUM_LIT> : <NUM_LIT> ; for ( unsigned i = <NUM_LIT> ; i != <NUM_LIT> ; i += <NUM_LIT> ) if ( ! isConstantOrUndef ( N -> getMaskElt ( i ) , i * <NUM_LIT> + j ) || ! isConstantOrUndef ( N -> getMaskElt ( i + <NUM_LIT> ) , i * <NUM_LIT> + j +

<NUM_LIT> ) || ! isConstantOrUndef ( N -> getMaskElt ( i + <NUM_LIT> ) , i * <NUM_LIT> + j ) || ! isConstantOrUndef ( N -> getMaskElt ( i + <NUM_LIT> ) , i * <NUM_LIT> + j + <NUM_LIT> ) ) return false ;


<s> std :: unique_ptr < MCObjectWriter > llvm :: create<ISA_LIT>MachObjectWriter ( raw_pwrite_stream & OS

, bool Is64Bit , uint32_t CPUType , uint32_t CPUSubtype ) {


<s> case MCSymbolRefExpr :: VK_GOT : assert ( Type == RT32_32 ) ; return IsPCRel ? ELF :: R_386_GOTPC : ELF :: R_386_GOT32 ; case MCSymbolRefExpr :: VK_GOTOFF : assert ( Type == RT32_32 ) ; assert ( ! IsPCRel ) ; return ELF :: R_386_GOTOFF ; case MCSymbolRefExpr :: VK_TPOFF : assert ( Type == RT32_32 ) ; assert ( ! IsPCRel ) ; return ELF :: R_386_TLS_LE_32 ; case MCSymbolRefExpr :: VK_DTPOFF : assert ( Type == RT32_32 ) ; assert ( ! IsPCRel ) ; return ELF :: R_386_TLS_LDO_32 ; case MCSymbolRefExpr :: VK_TLSGD : assert ( Type == RT32_32 ) ; assert ( ! IsPCRel ) ; return ELF :: R_386_TLS_GD ; case MCSymbolRefExpr :: VK_GOTTPOFF : assert ( Type == RT32_32 ) ; assert ( ! IsPCRel ) ; return ELF :: R_386_TLS_IE_32 ; case MCSymbolRefExpr ::


<s> Type * LLVMTy = IntegerType :: get ( CurMF -> getFunction ( ) . getContext ( ) , BitWidth ) ; Register Reg ; if ( DT . find ( LLVMTy , CurMF , Reg ) ) { return get<ISA_LIT>TypeForVReg ( Reg ) ; } MachineBasicBlock & BB = * I . getParent ( ) ; auto MIB = BuildMI ( BB , I , I . getDebugLoc ( ) , TII . get ( <STR_LIT> ) ) . addDef ( createTypeVReg ( CurMF -> getRegInfo (

) ) ) . addImm ( BitWidth ) . addImm ( <NUM_LIT> ) ;


<s> case VSX_BUILTIN_XXSEL_2DI_UNS : case CRYPTO_BUILTIN_VPERMXOR : case CRYPTO_BUILTIN_VPERMXOR_V2DI : case CRYPTO_BUILTIN_VPERMXOR_V4SI : case CRYPTO_BUILTIN_VPERMXOR_V8HI : case CRYPTO_BUILTIN_VPERMXOR_V16QI : case CRYPTO_BUILTIN_VSHASIGMAW : case CRYPTO_BUILTIN_VSHASIGMAD : case CRYPTO_BUILTIN_VSHASIGMA : h . uns_p [ <NUM_LIT> ] = <NUM_LIT> ; h . uns_p [ <NUM_LIT> ] = <NUM_LIT> ; h . uns_p [ <NUM_LIT> ] = <NUM_LIT> ; h . uns_p [ <NUM_LIT> ] = <NUM_LIT> ; break ; case ALTIVEC_BUILTIN_VPERM_16QI : case ALTIVEC_BUILTIN_VPERM_8HI : case ALTIVEC_BUILTIN_VPERM_4SI : case ALTIVEC_BUILTIN_VPERM_4SF : case ALTIVEC_BUILTIN_VPERM_2DI : case ALTIVEC_BUILTIN_VPERM_2DF : case VSX_BUILTIN_VPERM_16QI : case VSX_BUILTIN_VPERM_8HI : case VSX_BUILTIN_VPERM_4SI : case VSX_BUILTIN_VPERM_4SF : case VSX_BUILTIN_VPERM_2DI : case VSX_BUILTIN_VPERM_2DF : h . uns_p [ <NUM_LIT> ] = <NUM_LIT> ; break ; case VSX_BUILTIN_XVCVUXDSP : case VSX_BUILTIN_XVCVUXDDP_UNS : case ALTIVEC_BUILTIN_UNSFLOAT_V4SI_V4SF : h . uns_p [ <NUM_LIT> ] = <NUM_LIT> ; break ; case VSX_BUILTIN_XVCVDPUXDS_UNS : case ALTIVEC_BUILTIN_FIXUNS_V4SF_V4SI : case MISC_BUILTIN_UNPACK_TD : case MISC_BUILTIN_UNPACK_V1TI : h . uns_p [ <NUM_LIT> ] = <NUM_LIT> ; break ; case ALTIVEC_BUILTIN_VCMPEQUB : case ALTIVEC_BUILTIN_VCMPEQUH : case ALTIVEC_BUILTIN_VCMPEQUW : case P8V_BUILTIN_VCMPEQUD : case VSX_BUILTIN_CMPGE_U16QI : case VSX_BUILTIN_CMPGE_U8HI : case VSX_BUILTIN_CMPGE_U4SI : case VSX_BUILTIN_CMPGE_U2DI : case ALTIVEC_BUILTIN_VCMPGTUB : case ALTIVEC_BUILTIN_VCMPGTUH : case ALTIVEC_BUILTIN_VCMPGTUW : case P8V_BUILTIN_VCMPGTUD : h . uns_p [ <NUM_LIT> ] = <NUM_LIT> ; h . uns_p [ <NUM_LIT> ] = <NUM_LIT> ; break ; case MISC_BUILTIN_PACK_TD : case MISC_BUILTIN_PACK_V1TI : h . uns_p [ <NUM_LIT> ] = <NUM_LIT> ; h . uns_p [ <NUM_LIT> ] = <NUM_LIT> ; break ; case ALTIVEC_BUILTIN_VSRB : case ALTIVEC_BUILTIN_VSRH : case ALTIVEC_BUILTIN_VSRW : case P8V_BUILTIN_VSRD : h . uns_p [ <NUM_LIT> ] = <NUM_LIT> ; break ; default : break ; } while ( num_args > <NUM_LIT> && h . mode [ num_args ] == VOIDmode ) num_args -- ; ret_type = builtin_mode_to_type [ h . mode [ <NUM_LIT> ] ] [ h .


<s> MachineBasicBlock :: iterator I = MBB . getLastNonDebugInstr ( ) ; if ( I == MBB . end ( ) ) return false ; if ( ! isUnpredicatedTerminator ( * I ) ) return false ; while ( I != MBB . begin ( ) ) { -- I ; if ( I -> isDebugValue ( ) ) continue ; if ( ! isUnpredicatedTerminator ( * I ) ) break ; if ( ! I -> isBranch ( ) ) return true ; return true


<s> printRegName ( O , MO . getReg ( ) ) ; } else if ( MO . isExpr ( ) ) { O << * MO . getExpr ( ) ; } else if ( MO . isImm ( ) ) { printImmOperand ( MI , OpNo , O ) ; } else


<s> const std :: multimap < int , std :: tuple < int , std :: string , std :: string >> & getStartBEndBCoords ( ) { return StartBEndBCoords


<s> static bool frv_must_pass_in_stack ( enum machine_mode mode , tree type ) { if ( mode == BLKmode )


<s> return makeArrayRef ( std :: begin ( GPR64ArgRegsWin64 ) , std :: end ( GPR64ArgRegsWin64 ) ) ; } static const MCPhysReg GPR64ArgRegs64Bit [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> ,


<s> ResVT = <STR_LIT> ; TruncVT = <STR_LIT> ; Opc = <STR_LIT> ; Src = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getUNDEF ( <STR_LIT> ) , Src , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ; } SDValue Res = DAG . getNode ( Opc , dl , ResVT , Src ) ; Res = DAG . getNode ( <STR_LIT> , dl , TruncVT , Res ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Res , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ; } assert ( Subtarget . hasDQI ( ) && Subtarget . hasVLX ( ) && <STR_LIT> ) ; if ( VT == <STR_LIT> && Src . getSimpleValueType ( ) == <STR_LIT> ) { return DAG . getNode ( IsSigned ? <STR_LIT> : <STR_LIT> , dl , VT , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Src , DAG . getUNDEF ( <STR_LIT> ) ) ) ; } return SDValue ( ) ; } assert ( ! VT . isVector ( ) ) ; std :: pair < SDValue , SDValue > Vals = FP_TO_INTHelper ( Op , DAG , IsSigned , false ) ; SDValue FIST = Vals . first , StackSlot = Vals


<s> if ( ! isImm ( ) ) return false ; const MCConstantExpr * ConstExpr = dyn_cast < MCConstantExpr > ( Imm . Value ) ; if ( ConstExpr ) { int64_t Value = ConstExpr -> getValue ( ) ; return ( Value != <NUM_LIT> ) && ( (


<s> rtx value , op ; rtx early_op ; if ( ! arm_get_set_operands ( producer , consumer , & value ,


<s> unsigned TOCSaveOffset = Subtarget . getFrameLowering ( ) -> getTOCSaveOffset ( ) ; unsigned StackOffset = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; Register StackReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register SPReg = Subtarget . is<ISA_LIT>64 (


<s> if ( ! SetHiMI -> getOperand ( <NUM_LIT> ) . isImm ( ) ) return false ; int64_t imm = SetHiMI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( ! isInt < <NUM_LIT> > ( imm ) ) return false ; imm = ( imm << <NUM_LIT> ) & <NUM_LIT> ; assert ( RestoreMI -> getOpcode ( ) == <STR_LIT> ) ; RestoreMI -> setDesc ( TII -> get ( <STR_LIT> ) ) ; RestoreMI -> getOperand ( <NUM_LIT> ) . setReg ( reg - <STR_LIT> + <STR_LIT> ) ; RestoreMI -> getOperand ( <NUM_LIT> ) . setReg


<s> return ( Value >> <NUM_LIT> ) & <NUM_LIT> ; case <STR_LIT> : return ( Value >> <NUM_LIT> ) & <NUM_LIT> ; case <STR_LIT> : return ( Value >> <NUM_LIT> ) & <NUM_LIT> ; case <STR_LIT> : return ( Value >> <NUM_LIT> ) & <NUM_LIT> ; case <STR_LIT> : return ( Value >> <NUM_LIT> ) & <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ( Value >> <NUM_LIT> ) & <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : return Value & <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return Value & <NUM_LIT> ; case <STR_LIT> : return ( Value >> <NUM_LIT> ) & <NUM_LIT> ; case <STR_LIT> : return ( Value >> <NUM_LIT> ) & <NUM_LIT> ; case <STR_LIT>


<s> if ( ! is64Bit ) Ret += <STR_LIT> ; Ret +=


<s> PReg < <STR_LIT> ; ++ PReg ) { if ( PReg == <STR_LIT> || PReg == <STR_LIT> ) continue ; const TargetRegisterClass * RC = TRI . getMinimalPhysRegClass ( PReg ) ; unsigned VReg = <STR_LIT> ; for ( MachineOperand & MO : llvm :: make_early_inc_range ( MRI . reg_operands ( PReg ) ) ) { if ( ! MO . isImplicit ( ) ) { if ( VReg == <STR_LIT> ) { VReg = MRI . createVirtualRegister ( RC ) ; if ( PReg == TRI . getFrameRegister ( MF ) ) { auto FI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; assert ( ! FI -> isFrameBaseVirtual ( ) ) ; FI -> setFrameBaseVreg ( VReg ) ; LLVM_DEBUG ( { dbgs ( ) << <STR_LIT> << PReg << <STR_LIT> << VReg << <STR_LIT> << Register :: virtReg2Index ( VReg ) << <STR_LIT> ; } ) ; } } MO . setReg ( VReg ) ; if ( MO . getParent ( ) -> isDebugValue ( ) ) MO . setIsDebug ( ) ; Changed =


<s> llvm :: initialize<ISA_LIT>PostRAScavengingPass ( * PassRegistry


<s> break ; case MachineOperand :: MO_BlockAddress : { MCSymbol * BA = GetBlockAddressSymbol ( MO . getBlockAddress ( ) ) ; O << BA -> getName ( ) ; break ; } case MachineOperand :: MO_ExternalSymbol : if ( TF == <STR_LIT> ) O << <STR_LIT> << * GetExternalSymbolSymbol ( MO . getSymbolName ( ) ) << <STR_LIT> ; else O << * GetExternalSymbolSymbol ( MO . getSymbolName ( ) ) ; break ; case MachineOperand :: MO_JumpTableIndex : O << MAI -> getPrivateGlobalPrefix ( ) << <STR_LIT> << getFunctionNumber ( ) << '_' << MO . getIndex ( ) ; break ; case MachineOperand :: MO_ConstantPoolIndex : O << MAI -> getPrivateGlobalPrefix ( ) << <STR_LIT> << getFunctionNumber


<s> auto Pg = getPredicateForVector ( DAG , DL , VT ) ; if ( useSVEForFixedLengthVectorVT ( VT ) ) { EVT ContainerVT = getContainerForFixedLengthVector ( DAG , VT ) ; SmallVector < SDValue , <NUM_LIT> > Operands = { Pg } ; for ( const SDValue & V : Op -> op_values ( ) ) { if ( isa < CondCodeSDNode > ( V ) ) { Operands . push_back ( V ) ; continue ; } assert ( useSVEForFixedLengthVectorVT ( V . getValueType ( ) ) && <STR_LIT> ) ; Operands . push_back ( convertToScalableVector ( DAG , ContainerVT , V )


<s> return VT . isSimple ( ) || ! isOperationExpand (


<s> MCELFObjectTargetWriter * MOTW = new <ISA_LIT>ELFObjectWriter ( OSABI ) ; return createELFObjectWriter ( MOTW , OS , true


<s> const char * prefix = <STR_LIT> ; const char * suffix = <STR_LIT> ; if ( TARGET_SPE ) { gcc_assert ( ( sel & SAVRES_REG ) == SAVRES_GPR ) ; if ( ( sel & SAVRES_SAVE ) ) prefix = info -> spe_64bit_regs_used ? <STR_LIT> : <STR_LIT> ; else prefix = info -> spe_64bit_regs_used ? <STR_LIT> : <STR_LIT> ; if ( ( sel & SAVRES_LR ) ) suffix = <STR_LIT> ; } else if ( DEFAULT_ABI == ABI_V4 ) { if ( TARGET_64BIT ) goto aix_names ; if ( ( sel & SAVRES_REG ) == SAVRES_GPR ) prefix = ( sel & SAVRES_SAVE ) ? <STR_LIT> : <STR_LIT> ; else if ( ( sel & SAVRES_REG ) == SAVRES_FPR ) prefix = ( sel & SAVRES_SAVE ) ? <STR_LIT> : <STR_LIT> ; else if ( ( sel & SAVRES_REG ) == SAVRES_VR ) prefix = ( sel & SAVRES_SAVE ) ? <STR_LIT> : <STR_LIT> ; else abort (


<s> else if ( SecondOpcode == <STR_LIT> ) { if ( ! FirstMI ) return true ; if ( FirstMI -> definesRegister ( <STR_LIT> ) ) switch ( FirstMI -> getOpcode ( ) ) { case <STR_LIT> : return ( ! <ISA_LIT>InstrInfo :: hasShiftedReg ( * FirstMI ) ) ; case <STR_LIT> : case <STR_LIT> : return ( ! <ISA_LIT>InstrInfo :: hasExtendedReg ( * FirstMI ) ) ; case


<s> e = XVECEXP ( p , <NUM_LIT> , i ) ; gcc_assert ( GET_CODE ( e ) == SET && MEM_P ( SET_DEST ( e ) ) && REG_P ( SET_SRC ( e ) ) ) ; reg = REGNO ( SET_SRC ( e ) ) ; gcc_assert ( reg >= lastreg ) ; if ( i != <NUM_LIT> ) fprintf ( out_file , <STR_LIT> ) ; if ( IS_VFP_REGNUM ( reg ) ) asm_fprintf ( out_file , <STR_LIT> , ( reg - FIRST_VFP_REGNUM ) / <NUM_LIT> ) ; else asm_fprintf ( out_file , <STR_LIT> , reg ) ; if ( flag_checking ) { e = XEXP ( SET_DEST ( e ) , <NUM_LIT> ) ; if ( GET_CODE ( e ) == PLUS ) gcc_assert ( REG_P ( XEXP ( e , <NUM_LIT> ) ) && REGNO ( XEXP ( e , <NUM_LIT> ) ) == SP_REGNUM && CONST_INT_P ( XEXP ( e , <NUM_LIT> ) ) && offset == INTVAL ( XEXP ( e , <NUM_LIT> ) ) ) ; else gcc_assert ( i == <NUM_LIT> && REG_P ( e ) && REGNO ( e ) == SP_REGNUM ) ; offset += reg_size ; } } fprintf ( out_file , <STR_LIT> ) ; if ( padfirst ) fprintf ( out_file , <STR_LIT> ,


<s> MachineInstr * ChkStkStub = nullptr ; for ( MachineInstr & MI : PrologMBB ) { if ( MI . isCall ( ) && MI . getOperand ( <NUM_LIT> ) . isSymbol ( ) && ChkStkStubSymbol == MI . getOperand ( <NUM_LIT> ) . getSymbolName ( ) ) { ChkStkStub = &


<s> return ( __m512i ) __builtin_ia32_pmovzxbw512_mask ( ( __v32qi ) __A , ( __v32hi ) _mm512_setzero_si512 ( )


<s> I . setLatency ( Lat ) ; SUnit * UpdateDst = I . getSUnit ( ) ; updateLatency ( SrcI , UpdateDst -> getInstr ( ) , I ) ; for ( auto & PI : UpdateDst -> Preds ) { if ( PI . getSUnit ( ) != Src || ! PI . isAssignedRegDep ( ) ) continue ; PI . setLatency ( Lat ) ; updateLatency ( SrcI , UpdateDst -> getInstr (


<s> MCAsmBackend * llvm :: create<ISA_LIT>AsmBackendEB32 ( const Target & T , const MCRegisterInfo & MRI , const Triple & TT

, StringRef CPU , const MCTargetOptions & Options ) {


<s> return DAG . getNode ( <STR_LIT> , DL , VT , Src , DAG . getConstant ( BitLen , DL , <STR_LIT> ) , DAG . getConstant ( BitIdx , DL , <STR_LIT> ) ) ; } ; if ( SDValue ExtrQ = LowerAsEXTRQ ( ) ) return ExtrQ ; auto LowerAsInsertQ = [ & ] ( ) { for ( int Idx = <NUM_LIT> ; Idx != HalfSize ; ++ Idx ) { SDValue Base ; if ( isUndefInRange ( Mask , <NUM_LIT> , Idx ) ) { } else if ( isSequentialOrUndefInRange ( Mask , <NUM_LIT> , Idx , <NUM_LIT> ) ) { Base = V1 ; } else if ( isSequentialOrUndefInRange ( Mask , <NUM_LIT> , Idx , Size ) ) { Base = V2 ; } else { continue ; } for ( int Hi = Idx + <NUM_LIT> ; Hi <= HalfSize ; ++ Hi ) { SDValue Insert ; int Len = Hi - Idx ; if ( isSequentialOrUndefInRange ( Mask , Idx , Len , <NUM_LIT> ) ) { Insert = V1 ; } else if ( isSequentialOrUndefInRange ( Mask , Idx , Len , Size ) ) { Insert = V2 ; } else { continue ; } if ( isUndefInRange ( Mask , Hi , HalfSize - Hi ) ) { } else if ( ( ! Base || ( Base == V1 ) ) && isSequentialOrUndefInRange ( Mask , Hi , HalfSize - Hi , Hi ) ) { Base = V1 ; } else if ( ( ! Base || ( Base == V2 ) ) && isSequentialOrUndefInRange ( Mask , Hi , HalfSize - Hi , Size + Hi ) ) { Base = V2 ; } else { continue ; } if ( ! Base ) Base = DAG . getUNDEF ( VT ) ; int BitLen = ( Len * VT . getScalarSizeInBits ( ) ) & <NUM_LIT> ; int BitIdx = ( Idx * VT . getScalarSizeInBits ( ) ) & <NUM_LIT> ; return DAG . getNode ( <STR_LIT> , DL , VT , Base , Insert , DAG . getConstant ( BitLen , DL , <STR_LIT>


<s> } MachineInstr * RetI = getReturn ( MBB ) ; unsigned RetOpc = RetI ? RetI -> getOpcode ( ) : <NUM_LIT> ; if ( RetOpc == <STR_LIT> ) { BuildMI ( MBB , InsertPt , dl , HII . get ( <STR_LIT> ) ) . addDef ( <STR_LIT> ) . addReg ( <STR_LIT> ) ; BuildMI ( MBB , InsertPt , dl , HII . get ( <STR_LIT> ) , SP ) . addReg ( SP ) . addReg ( <STR_LIT> ) ; return ; } if ( RetOpc == <STR_LIT> || RetOpc == <STR_LIT> || RetOpc == <STR_LIT> || RetOpc == <STR_LIT> ) { MachineBasicBlock :: iterator It = RetI ; ++ It ; while ( It != MBB . end ( ) ) { if ( ! It -> isLabel ( ) ) It = MBB . erase ( It ) ; else ++ It ; } return ; } bool NeedsDeallocframe = true ; if ( ! MBB . empty ( ) && InsertPt != MBB . begin ( ) ) { MachineBasicBlock :: iterator PrevIt = std :: prev ( InsertPt ) ; unsigned COpc = PrevIt -> getOpcode ( ) ; if ( COpc == <STR_LIT> || COpc == <STR_LIT> || COpc == <STR_LIT> || COpc == <STR_LIT> ||

COpc == <STR_LIT> || COpc == <STR_LIT> ) NeedsDeallocframe = false ;


<s> bool isAllocated ( unsigned Reg ) const { return UsedRegs [ Reg / <NUM_LIT> ] & ( <NUM_LIT> << ( Reg &


<s> void <ISA_LIT>TargetAsmStreamer :: emitArchExtension ( unsigned ArchExt ) { OS << <STR_LIT> << <STR_LIT>


<s> printRegName ( O , MI -> getOperand ( OpNum ) . getReg ( ) ) ; O << <STR_LIT> ; printRegName ( O , MI -> getOperand ( OpNum ) . getReg ( ) + <NUM_LIT> ) ; O << <STR_LIT> ; printRegName ( O , MI -> getOperand ( OpNum ) . getReg ( ) + <NUM_LIT> ) ; O << <STR_LIT> ; printRegName ( O , MI -> getOperand ( OpNum ) . getReg ( ) + <NUM_LIT> ) ; O <<


<s> EVT Ty = Op . getValueType ( ) ; if ( getTargetMachine ( ) . getRelocationModel ( ) != Reloc :: PIC_ && ! Subtarget . isABI_N64 ( ) ) return getAddrNonPIC ( N , SDLoc ( N ) , Ty , DAG ) ; return getAddrLocal ( N , SDLoc ( N ) , Ty , DAG , Subtarget

. isABI_N32 ( ) || Subtarget . isABI_N64 ( ) ) ;


<s> const <ISA_LIT>ELFDynamic & <ISA_LIT>LDBackend :: dynamic ( ) const { assert ( m_pDynamic != NULL ) ; return *


<s> const MCConstantExpr * CE = cast < MCConstantExpr > ( getImm ( ) ) ; Inst . addOperand ( MCOperand :: createImm ( CE -> getValue ( )


<s> virtual const <ISA_LIT>RegisterInfo & getRegisterInfo ( ) const { return


<s> static SDValue PerformAddCombine ( SDNode * N , SelectionDAG & DAG , const <ISA_LIT>Subtarget * Subtarget ) { EVT VT = N -> getValueType ( <NUM_LIT> ) ; SDValue Op0 = N -> getOperand ( <NUM_LIT> ) ; SDValue Op1 = N -> getOperand ( <NUM_LIT>


<s> void <ISA_LIT>AsmParser :: cvtD<ISA_LIT>mpl ( MCInst & Inst , const OperandVector & Operands , bool IsGdsHardcoded ) { OptionalImmIndexMap OptionalIdx ; for ( unsigned i = <NUM_LIT> , e = Operands . size ( ) ; i != e ; ++ i ) { <ISA_LIT>Operand & Op = ( ( <ISA_LIT>Operand & ) * Operands [ i ] ) ; if ( Op . isReg ( ) ) { Op . addRegOperands ( Inst , <NUM_LIT> ) ; continue ; } if ( Op . isToken ( ) && Op . getToken ( ) == <STR_LIT> ) { IsGdsHardcoded = true ; continue ; } OptionalIdx [ Op . getImmTy ( ) ] = i ; } addOptionalImmOperand ( Inst , Operands , OptionalIdx , <ISA_LIT>Operand :: ImmTyOffset ) ; if ( ! IsGdsHardcoded ) { addOptionalImmOperand ( Inst , Operands , OptionalIdx , <ISA_LIT>Operand :: ImmTyGDS ) ; } Inst . addOperand ( MCOperand :: createReg ( <STR_LIT> )


<s> static DecodeStatus DecodeGPROutRegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t Address , const void * Decoder ) { return DecodeCPURegsRegisterClass ( Inst , RegNo


<s> inline const BitTracker :: RegisterCell & BitTracker :: lookup


<s> SDLoc SL ( Op ) ; SDValue Src = Op . getOperand ( <NUM_LIT> ) ; SDValue Trunc = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Src ) ; SDValue K0 = DAG . getConstantFP ( BitsToDouble ( UINT64_C ( <NUM_LIT> ) ) , SL , <STR_LIT> ) ; SDValue K1 = DAG . getConstantFP ( BitsToDouble ( UINT64_C ( <NUM_LIT> ) ) , SL , <STR_LIT> ) ; SDValue Mul = DAG . getNode ( <STR_LIT> , SL , <STR_LIT>


<s> Value * <ISA_LIT>IREmitter :: visitVSHLLi ( const SDNode * N ) { llvm_unreachable ( <STR_LIT> ) ; return


<s> int OperandIdx = TII -> getOperandIdx ( BI -> getOpcode ( ) , <STR_LIT> :: write ) ; if ( OperandIdx > - <NUM_LIT> && BI -> getOperand ( OperandIdx ) . getImm ( ) == <NUM_LIT> ) continue ; int DstIdx = TII -> getOperandIdx ( BI -> getOpcode ( ) , <STR_LIT> :: dst ) ; if ( DstIdx == - <NUM_LIT> ) { continue ; } unsigned Dst = BI -> getOperand ( DstIdx ) . getReg ( ) ; if ( isTrans || TII -> isTransOnly ( BI ) ) { Result [ Dst ] = <STR_LIT> ; continue ; } if ( BI -> getOpcode ( ) == <STR_LIT> || BI -> getOpcode ( ) == <STR_LIT> ) { Result [ Dst ] = <STR_LIT> ; continue ; } if ( Dst == <STR_LIT> ) { continue ; } unsigned PVReg = <NUM_LIT> ; switch ( TRI . getHWRegChan ( Dst ) ) { case <NUM_LIT> : PVReg = <STR_LIT> ; break ; case <NUM_LIT> : PVReg = <STR_LIT> ; break ; case <NUM_LIT> : PVReg = <STR_LIT> ; break ; case <NUM_LIT> : PVReg = <STR_LIT>


<s> unsigned NumRegs = NextEmittedNumMemOps - EmittedNumMemOps ; Dst = DAG . getNode ( <STR_LIT> , dl , VTs , Chain , Dst , Src , DAG . getConstant ( NumRegs , dl , <STR_LIT> ) ) ; Src = Dst . getValue ( <NUM_LIT> ) ; Chain = Dst . getValue ( <NUM_LIT> ) ; DstPtrInfo = DstPtrInfo . getWithOffset ( NumRegs * VTSize ) ; SrcPtrInfo = SrcPtrInfo . getWithOffset ( NumRegs * VTSize ) ; EmittedNumMemOps = NextEmittedNumMemOps ; } if ( BytesLeft == <NUM_LIT> ) return Chain ; unsigned BytesLeftSave = BytesLeft ; i = <NUM_LIT> ; while ( BytesLeft ) { if ( BytesLeft >= <NUM_LIT> ) { VT = <STR_LIT> ; VTSize = <NUM_LIT> ; } else { VT = <STR_LIT> ; VTSize = <NUM_LIT> ; } Loads [ i ] = DAG . getLoad ( VT , dl , Chain , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Src , DAG . getConstant ( SrcOff , dl , <STR_LIT> ) ) , SrcPtrInfo . getWithOffset ( SrcOff ) , false , false , false , <NUM_LIT> ) ; TFOps [ i ] = Loads [ i ] . getValue ( <NUM_LIT> ) ; ++ i ; SrcOff += VTSize ; BytesLeft -= VTSize ; } Chain = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , makeArrayRef ( TFOps , i ) ) ; i = <NUM_LIT> ; BytesLeft = BytesLeftSave ; while ( BytesLeft


<s> O << nvptxSubtarget . getTargetName ( ) ; if ( nvptxSubtarget . getDrvInterface ( ) == <STR_LIT> ) O << <STR_LIT> ; if ( nvptxSubtarget . getDrvInterface ( ) == <STR_LIT> ) { if ( ! nvptxSubtarget . hasDouble ( ) ) O << <STR_LIT> ; } if ( MAI -> doesSupportDebugInformation ( ) ) O << <STR_LIT> ; O << <STR_LIT> ; O << <STR_LIT> ; if ( nvptxSubtarget . is64Bit ( ) ) O << <STR_LIT> ; else O << <STR_LIT> ; O << <STR_LIT> ; O << <STR_LIT>


<s> case AMDGPU :: S_LSHL_B64 : return AMDGPU :: V_LSHL_B64 ; case AMDGPU :: S_LSHR_B32 : return AMDGPU :: V_LSHR_B32_e32 ; case AMDGPU :: S_LSHR_B64 : return AMDGPU :: V_LSHR_B64 ; case AMDGPU :: S_SEXT_I32_I8 : return AMDGPU :: V_BFE_I32 ; case AMDGPU :: S_SEXT_I32_I16 : return AMDGPU :: V_BFE_I32 ; case AMDGPU :: S_BFE_U32 : return AMDGPU :: V_BFE_U32 ; case AMDGPU :: S_BFE_I32 : return AMDGPU :: V_BFE_I32 ; case AMDGPU :: S_NOT_B32 : return AMDGPU :: V_NOT_B32_e32 ; case AMDGPU :: S_CMP_EQ_I32 : return AMDGPU :: V_CMP_EQ_I32_e32 ; case AMDGPU :: S_CMP_LG_I32 : return AMDGPU :: V_CMP_NE_I32_e32 ; case AMDGPU :: S_CMP_GT_I32 : return AMDGPU :: V_CMP_GT_I32_e32 ; case AMDGPU :: S_CMP_GE_I32 : return AMDGPU :: V_CMP_GE_I32_e32 ; case AMDGPU :: S_CMP_LT_I32 : return AMDGPU :: V_CMP_LT_I32_e32 ; case AMDGPU :: S_CMP_LE_I32 : return AMDGPU :: V_CMP_LE_I32_e32 ; case AMDGPU :: S_LOAD_DWORD_IMM : case AMDGPU :: S_LOAD_DWORD_SGPR : return AMDGPU :: BUFFER_LOAD_DWORD_ADDR64 ; case AMDGPU :: S_LOAD_DWORDX2_IMM : case AMDGPU :: S_LOAD_DWORDX2_SGPR : return AMDGPU :: BUFFER_LOAD_DWORDX2_ADDR64 ; case AMDGPU :: S_LOAD_DWORDX4_IMM


<s> return F == <STR_LIT> || F == <STR_LIT> ; } ; if ( ! llvm :: count_if ( Features . getFeatures ( ) , IsQFloatFS ) ) { auto getHvxVersion = [ & Features ] ( StringRef FS ) -> StringRef { for ( StringRef F : llvm :: reverse ( Features . getFeatures ( ) ) ) { if ( F . startswith ( <STR_LIT> ) ) return F ; } for ( StringRef F : llvm :: reverse ( Features . getFeatures ( ) ) ) { if ( F == <STR_LIT> ) return StringRef ( ) ; if ( F . startswith ( <STR_LIT> ) || F == <STR_LIT> ) return F . take_front ( <NUM_LIT> ) ; } return StringRef ( ) ; } ; bool AddQFloat = false ; StringRef HvxVer = getHvxVersion ( FS ) ; if ( HvxVer . startswith ( <STR_LIT> ) ) { int Ver = <NUM_LIT> ; if ( ! HvxVer . drop_front ( <NUM_LIT> ) . consumeInteger ( <NUM_LIT> , Ver ) && Ver >= <NUM_LIT> ) AddQFloat = true ; } else if ( HvxVer == <STR_LIT> ) { if ( hasV68Ops ( ) ) AddQFloat =


<s> else if ( DstTy == LLT :: scalar ( <NUM_LIT> ) ) AndOpc = <STR_LIT> ; else if ( DstTy == LLT :: scalar ( <NUM_LIT> ) ) AndOpc = <STR_LIT> ; else if ( DstTy == LLT :: scalar ( <NUM_LIT> ) ) AndOpc = <STR_LIT> ; else return false ; unsigned DefReg = SrcReg ; if ( DstTy != LLT :: scalar ( <NUM_LIT> ) ) { DefReg = MRI . createVirtualRegister ( getRegClass ( DstTy , DstReg , MRI ) ) ; BuildMI ( * I . getParent ( ) , I , I . getDebugLoc ( ) , TII . get ( TargetOpcode :: SUBREG_TO_REG ) , DefReg ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg ) . addImm ( <STR_LIT> ) ; } MachineInstr & AndInst = * BuildMI ( * I . getParent ( ) , I , I . getDebugLoc ( ) , TII . get ( AndOpc ) , DstReg ) . addReg ( DefReg ) . addImm ( <NUM_LIT> ) ; constrainSelectedInstRegOperands ( AndInst , TII , TRI , RBI


<s> __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a )


<s> MRI = & MF . getRegInfo ( ) ; TII = ST . getInstrInfo ( ) ; bool Changed = false ; for ( auto & MBB : MF ) { for ( auto I = MBB . rbegin ( ) , E = MBB . rend ( ) ; I != E ; ) { auto & MI = *


<s> Type = MachO :: GENERIC_RELOC_VANILLA ; } else { if ( SD -> getSymbol ( ) . isVariable ( ) ) { int64_t Res ; if ( SD -> getSymbol ( ) . getVariableValue ( ) -> EvaluateAsAbsolute ( Res , Layout , Writer -> getSectionAddressMap ( ) ) ) { FixedValue = Res ; return ; } } if ( Writer -> doesSymbolRequireExternRelocation ( SD ) ) { IsExtern = <NUM_LIT> ; Index = SD -> getIndex ( ) ; if ( ! SD -> Symbol -> isUndefined ( ) ) FixedValue -= Layout . getSymbolOffset ( SD ) ; } else { const MCSectionData & SymSD = Asm . getSectionData ( SD -> getSymbol ( ) . getSection ( ) ) ; Index = SymSD . getOrdinal ( ) + <NUM_LIT> ; FixedValue += Writer -> getSectionAddress ( & SymSD ) ; } if ( IsPCRel ) FixedValue -= Writer -> getSectionAddress ( Fragment -> getParent ( ) ) ; Type = MachO :: GENERIC_RELOC_VANILLA


<s> LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * Inst << '\n' ) ; MemAccessInfo MAI = makeMemAccessInfo ( const_cast < Instruction * > ( Inst ) ) ; bool IsLargeStride = MAI . isLargeStride (


<s> bool SelectAddrMode2ShOp ( SDValue N , SDValue & Base , SDValue &


<s> if ( named ) return gen_reg_rtx ( mode ) ; return NULL_RTX


<s> return __builtin_loongson_packsswh ( s , t )


<s> static SDValue PerformShiftCombine ( SDNode * N , SelectionDAG & DAG , TargetLowering :: DAGCombinerInfo & DCI , const <ISA_LIT>Subtarget * Subtarget ) { if ( N -> getOpcode ( ) == <STR_LIT> ) if ( SDValue V = PerformSHLCombine ( N , DAG ) ) return V ; if ( N -> getOpcode ( ) != <STR_LIT> ) if ( SDValue V = performShiftToAllZeros ( N , DAG , Subtarget ) ) return V ; return SDValue ( )


<s> SDValue <ISA_LIT>TargetLowering :: LowerINTRINSIC_W_CHAIN ( SDValue Op , SelectionDAG & DAG ) const { unsigned IntNo = Op . getConstantOperandVal ( <NUM_LIT> ) ; switch ( IntNo ) { default : return SDValue ( ) ; case <STR_LIT> : { auto Node = cast < MemIntrinsicSDNode > ( Op . getNode ( ) ) ; SDLoc DL ( Op ) ; SDValue Chain = Node -> getChain ( ) ; SDValue Dst = Op . getOperand ( <NUM_LIT> ) ; SDValue Val = Op . getOperand ( <NUM_LIT> ) ; Val = DAG . getAnyExtOrTrunc ( Val , DL , <STR_LIT> ) ; SDValue Size = Op . getOperand ( <NUM_LIT> ) ; auto Alignment = Node -> getMemOperand ( ) -> getAlign ( ) ; bool IsVol = Node -> isVolatile ( ) ; auto DstPtrInfo = Node ->


<s> return TargetTriple . getOS ( ) == Triple


<s> if ( isVectorPredicated ( & MI ) ) { if ( MI . mayLoad ( ) ) FalseLanesZero . insert ( & MI ) ; Predicated . insert ( & MI ) ; continue ; } if ( MI . getNumDefs ( ) == <NUM_LIT> ) continue ; if ( ! producesFalseLanesZero ( MI , QPRs , RDA , FalseLanesZero ) ) { if ( retainsPreviousHalfElement ( MI ) || isHorizontalReduction ( MI ) ) return false ; FalseLanesUnknown . insert ( & MI ) ; } else if ( ! isHorizontalReduction ( MI ) ) FalseLanesZero . insert ( & MI ) ; } auto HasPredicatedUsers = [ this ] ( MachineInstr * MI , const MachineOperand & MO , SmallPtrSetImpl < MachineInstr * > & Predicated ) { SmallPtrSet < MachineInstr * , <NUM_LIT> > Uses ; RDA . getGlobalUses ( MI , MO . getReg ( ) , Uses ) ; for ( auto * Use : Uses ) { if ( Use != MI && ! Predicated . count ( Use ) ) return false ; } return


<s> if ( Opcode == <STR_LIT> ) checkADDrr ( MRI , RelocOp , GVal ) ; else if ( Opcode == <STR_LIT> ) checkShift ( MRI , * Inst -> getParent ( ) , RelocOp , GVal , <STR_LIT> ) ; else if ( Opcode == <STR_LIT> ) checkShift ( MRI , * Inst -> getParent ( ) , RelocOp , GVal , <STR_LIT> ) ; else if ( Opcode == <STR_LIT> ) checkShift ( MRI , * Inst -> getParent ( ) , RelocOp ,


<s> SDValue NegSize = DAG . getNode ( <STR_LIT> , dl , PtrVT , DAG . getConstant ( <NUM_LIT> , PtrVT ) , Size ) ; SDValue FPSIdx = getFramePointerFrameIndex ( DAG ) ; SDValue Ops [ <NUM_LIT> ] = { Chain , NegSize , FPSIdx


<s> return ( __m512i ) __builtin_ia32_pmovsxwq512_mask ( ( __v8hi ) __A , (

__v8di ) _mm512_undefined_si512 ( ) , ( __mmask8 ) - <NUM_LIT> ) ;


<s> SDValue LoadVal = DAG . getNode ( <STR_LIT> , DL , IntVT , BufferLoad ) ; LoadVal = DAG . getNode ( <STR_LIT> , DL , LoadVT , LoadVal ) ; return DAG . getMergeValues ( { LoadVal , BufferLoad . getValue ( <NUM_LIT>


<s> SmallVector < Instruction * , <NUM_LIT> > AtomicInsts ; for ( BasicBlock & BB : F ) for ( Instruction & Inst : BB ) { if ( isa < AtomicRMWInst > ( & Inst ) || ( isa < StoreInst > ( & Inst ) && cast < StoreInst > ( & Inst ) -> isAtomic ( ) ) ) AtomicInsts . push_back ( & Inst ) ; } bool MadeChange = false ; for ( Instruction * Inst : AtomicInsts ) { if ( ! shouldExpand ( Inst ) ) continue ; if ( AtomicRMWInst * AI = dyn_cast < AtomicRMWInst > ( Inst ) ) MadeChange |= expandAtomicRMW ( AI ) ; if ( StoreInst * SI = dyn_cast < StoreInst > ( Inst ) ) MadeChange |= expandAtomicStore ( SI ) ; assert ( MadeChange && <STR_LIT> ) ; Inst -> eraseFromParent ( ) ; } return MadeChange


<s> for ( unsigned PseudoReg : { <STR_LIT> , <STR_LIT> , <STR_LIT> } ) Mask [ PseudoReg / <NUM_LIT> ] &= ~ ( <NUM_LIT> << ( PseudoReg


<s> continue ; } TBB = I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; continue ; } assert ( I -> getOpcode ( ) == <STR_LIT> && <STR_LIT> ) ; <STR_LIT> BranchCode = static_cast < <STR_LIT> > ( I -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; if ( BranchCode == <STR_LIT> ) return true ; if ( Cond . empty ( ) ) { FBB = TBB ; TBB = I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; Cond . push_back ( MachineOperand :: CreateImm ( BranchCode ) ) ; continue ; } assert ( Cond . size ( ) == <NUM_LIT> ) ; assert ( TBB ) ; if ( TBB != I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ) return true ; <STR_LIT> OldBranchCode = ( <STR_LIT> ) Cond [ <NUM_LIT> ] . getImm


<s> case <STR_LIT> : return PerformEXTRACT_VECTOR_ELTCombine ( N , DAG , DCI ) ; case <STR_LIT> : case <STR_LIT> : return PerformSELECTCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformCMOVCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformAddCombine ( N , DAG , Subtarget ) ; case <STR_LIT> : return PerformSubCombine ( N , DAG , Subtarget ) ; case <STR_LIT> : return PerformADCCombine ( N , DAG , DCI ) ; case <STR_LIT> : return PerformMulCombine ( N , DAG , DCI ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return PerformShiftCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformAndCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformOrCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformXorCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformLOADCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformSTORECombine ( N , DAG , Subtarget ) ; case <STR_LIT> : return PerformSINT_TO_FPCombine ( N , DAG , this ) ; case <STR_LIT> : return PerformFADDCombine ( N , DAG , Subtarget ) ; case <STR_LIT> : return PerformFSUBCombine ( N , DAG , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : return PerformFORCombine ( N , DAG ) ; case <STR_LIT> : case <STR_LIT> : return PerformFMinFMaxCombine ( N , DAG ) ; case <STR_LIT> : return PerformFANDCombine ( N , DAG ) ; case <STR_LIT> : return PerformFANDNCombine ( N , DAG ) ; case <STR_LIT> : return PerformBTCombine ( N , DAG , DCI ) ; case <STR_LIT> : return PerformVZEXT_MOVLCombine ( N , DAG ) ; case <STR_LIT>


<s> SwitchToExIdxSection ( * FnStart ) ; if ( PersonalityIndex < <STR_LIT> :: NUM_PERSONALITY_INDEX && ! IsAndroid ) EmitPersonalityFixup ( GetAEABIUnwindPersonalityName ( PersonalityIndex ) ) ; const MCSymbolRefExpr * FnStartRef = MCSymbolRefExpr :: create ( FnStart , MCSymbolRefExpr :: VK_<ISA_LIT>_PREL31 , getContext ( ) ) ; EmitValue ( FnStartRef , <NUM_LIT> ) ; if ( CantUnwind ) { EmitIntValue ( <STR_LIT> :: EXIDX_CANTUNWIND , <NUM_LIT> ) ; } else if ( ExTab


<s> unsigned <ISA_LIT>RegisterInfo :: findUnusedRegister ( const MachineRegisterInfo & MRI , const TargetRegisterClass * RC ) const { for ( unsigned Reg : * RC ) if ( ! MRI


<s> assert ( Cond . size ( ) == <NUM_LIT> ) ; <STR_LIT> CC = static_cast < <STR_LIT> > ( Cond [ <NUM_LIT> ] . getImm ( ) ) ; Cond [ <NUM_LIT> ] . setImm ( GetOppositeBranchCondition ( CC )


<s> for ( const Argument & Arg : F . args ( ) ) { const bool IsByRef = Arg . hasByRefAttr ( ) ; Type * ArgTy = IsByRef ? Arg . getParamByRefType ( ) : Arg . getType ( ) ; MaybeAlign Alignment = IsByRef ? Arg . getParamAlign ( ) :


<s> CCAssignFn * AssignFn = TLI . CCAssignFnForReturn ( F . getCallingConv ( ) ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; auto & DL = F . getParent ( ) -> getDataLayout ( ) ; ArgInfo OrigArg { VReg , Val -> getType ( ) } ; setArgFlags ( OrigArg , AttributeSet :: ReturnIndex , DL , F ) ; SmallVector < ArgInfo , <NUM_LIT> > SplitArgs ; splitToValueTypes ( OrigArg , SplitArgs , DL , MRI , [ & ] ( ArrayRef < unsigned > Regs , ArrayRef < uint64_t > Offsets ) { MIRBuilder . buildExtract ( Regs , Offsets , VReg ) ; } ) ; OutgoingArgHandler Handler ( MIRBuilder , MRI , MIB ) ; Success = handleAssignments ( MIRBuilder , AssignFn , SplitArgs , Handler ) ; } MIRBuilder . insertInstr ( MIB ) ; return


<s> if ( MBBI == MBB . begin ( ) ) return ; MachineBasicBlock :: iterator PI = prior ( MBBI ) ; unsigned Opc = PI -> getOpcode ( ) ; if ( ( Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ) && PI -> getOperand ( <NUM_LIT> ) . getReg ( ) == StackPtr ) { if ( NumBytes ) * NumBytes += PI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; MBB . erase ( PI ) ; } else if ( ( Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ) && PI -> getOperand ( <NUM_LIT> ) . getReg ( ) == StackPtr ) { if ( NumBytes ) * NumBytes -= PI -> getOperand ( <NUM_LIT> ) . getImm


<s> if ( const Function * F = cast < CallBase > ( I ) . getCalledFunction ( ) ) { if ( isLoweredToCall ( F ) ) HasCall = true ; if ( F -> getIntrinsicID ( ) == <STR_LIT> || F -> getIntrinsicID ( ) == <STR_LIT> ) NumStores ++ ; } else { HasCall = true ; } } if ( isa < StoreInst > ( & I ) ) { Type * MemAccessTy = I . getOperand ( <NUM_LIT> ) -> getType


<s> bool <ISA_LIT>TTIImpl :: hasDivRemOp ( Type * DataType , bool IsSigned ) { EVT VT = TLI -> getValueType


<s> if ( CurDAG -> isBaseWithConstantOffset ( Addr ) ) { SDValue N0 = Addr . getOperand ( <NUM_LIT> ) ; SDValue N1 = Addr . getOperand ( <NUM_LIT> ) ; ConstantSDNode * C1 = cast < ConstantSDNode > ( N1 ) ; if ( isDSOffsetLegal ( N0 , C1 -> getSExtValue ( ) , <NUM_LIT> ) ) { Base = N0 ; Offset = N1 ; return true ; } } if ( const ConstantSDNode * CAddr = dyn_cast < ConstantSDNode > ( Addr ) ) { if ( isUInt < <NUM_LIT> > ( CAddr -> getZExtValue ( ) ) ) { SDValue Zero = CurDAG -> getTargetConstant ( <NUM_LIT> , <STR_LIT> ) ; MachineSDNode * MovZero = CurDAG -> getMachineNode ( AMDGPU :: V_MOV_B32_e32 , SDLoc (


<s> } legalizeOperands ( Inst ) ; const TargetRegisterClass * NewDstRC = getOpRegClass ( * Inst , <NUM_LIT> ) ; switch ( Inst -> getOpcode ( ) ) { case AMDGPU :: COPY : case AMDGPU :: PHI : case AMDGPU :: REG_SEQUENCE : if ( RI . hasVGPRs ( NewDstRC ) ) continue ; NewDstRC = RI . getEquivalentVGPRClass ( NewDstRC ) ; if ( ! NewDstRC ) continue ; break ; default : break ; } unsigned DstReg = Inst -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned NewDstReg = MRI . createVirtualRegister ( NewDstRC ) ; MRI . replaceRegWith ( DstReg , NewDstReg ) ; for ( MachineRegisterInfo :: use_iterator I = MRI . use_begin ( NewDstReg ) , E = MRI . use_end ( ) ; I != E ; ++ I ) { MachineInstr & UseMI = * I ; if ( ! canReadVGPR ( UseMI , I . getOperandNo ( ) ) ) { Worklist . push_back (


<s> uint64_t ObjSize = cast < ConstantSDNode > ( Size ) -> getZExtValue ( ) ; assert ( ObjSize % <NUM_LIT> == <NUM_LIT> ) ; MachineFunction & MF = DAG . getMachineFunction ( ) ; MachineMemOperand * BaseMemOperand = MF . getMachineMemOperand ( DstPtrInfo , MachineMemOperand :: MOStore , ObjSize , <NUM_LIT> ) ; bool UseSetTagRangeLoop = kSetTagLoopThreshold >= <NUM_LIT> && ( int ) ObjSize >= kSetTagLoopThreshold ; if ( ! UseSetTagRangeLoop ) return EmitUnrolledSetTag ( DAG , dl , Chain , Addr , ObjSize , BaseMemOperand , ZeroData ) ; if ( ObjSize % <NUM_LIT> != <NUM_LIT> ) { SDNode * St1 = DAG . getMachineNode ( ZeroData ? <STR_LIT> : <STR_LIT> , dl , { <STR_LIT> , <STR_LIT> } , { Addr , Addr , DAG . getTargetConstant ( <NUM_LIT> , dl , <STR_LIT> ) , Chain } ) ; DAG . setNodeMemRefs ( cast < MachineSDNode > ( St1 ) , { BaseMemOperand } ) ; ObjSize -= <NUM_LIT> ; Addr = SDValue ( St1 , <NUM_LIT> ) ; Chain = SDValue ( St1 , <NUM_LIT> ) ; } const EVT ResTys [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> } ; SDValue Ops [ ] = { DAG . getConstant ( ObjSize , dl , <STR_LIT> ) , Addr ,


<s> break ; default : break ; } if ( IN_RANGE ( ival , - <NUM_LIT> , <NUM_LIT> ) ) return OP_TYPE_IMM_W ; return OP_TYPE_IMM_L ; } if ( GET_CODE ( op ) == CONST_DOUBLE ) { switch ( GET_MODE ( op ) ) { case SFmode : return OP_TYPE_IMM_W ; case VOIDmode : case DFmode : return OP_TYPE_IMM_L ; default : gcc_unreachable ( ) ; } } if ( GET_CODE ( op ) == CONST || symbolic_operand ( op , VOIDmode ) || LABEL_P ( op ) ) { switch ( GET_MODE ( op ) ) { case QImode : return OP_TYPE_IMM_Q ; case HImode : return OP_TYPE_IMM_W ; case SImode : return OP_TYPE_IMM_L ; default : if ( symbolic_operand ( m68k_unwrap_symbol ( op , false ) , VOIDmode ) ) return OP_TYPE_IMM_W ; return OP_TYPE_IMM_L ; } } gcc_assert ( ! reload_completed ) ; if ( FLOAT_MODE_P ( GET_MODE ( op )


<s> OutStreamer -> EmitIntValue ( KernelInfo . ComputePGMRSrc2 , <NUM_LIT> ) ; OutStreamer -> EmitIntValue ( R_00B860_COMPUTE_TMPRING_<ISA_LIT>ZE , <NUM_LIT> ) ; OutStreamer -> EmitIntValue ( S_00B860_WAVE<ISA_LIT>ZE ( KernelInfo . ScratchBlocks ) , <NUM_LIT> ) ; } else { OutStreamer -> EmitIntValue ( RsrcReg , <NUM_LIT> ) ; OutStreamer -> EmitIntValue ( S_00B028_VGPRS ( KernelInfo . VGPRBlocks ) | S_00B028_SGPRS ( KernelInfo . SGPRBlocks ) , <NUM_LIT> ) ; if ( STM . isVGPRSpillingEnabled ( MFI ) ) { OutStreamer -> EmitIntValue ( R_0286E8_SPI_TMPRING_<ISA_LIT>ZE , <NUM_LIT> ) ; OutStreamer -> EmitIntValue ( S_0286E8_WAVE<ISA_LIT>ZE ( KernelInfo . ScratchBlocks ) , <NUM_LIT> ) ; } } if ( MFI -> getShaderType ( ) == ShaderType ::


<s> void arm_pr_no_long_calls ( struct cpp_reader * pfile ATTRIBUTE_UNUSED


<s> MCOperand DestReg = Inst . getOperand ( <NUM_LIT> ) ; const MCExpr * Symbol = Inst . getOperand ( <NUM_LIT> ) . getExpr ( ) ; emitAuipcInstPair ( DestReg , DestReg , Symbol , <ISA_LIT>MCExpr

:: VK_<ISA_LIT>_PCREL_HI , <STR_LIT> , IDLoc , Out ) ;


<s> emitLinkage ( name , GV -> getLinkage ( ) ) ; EmitAlignment ( TD -> getPreferredAlignmentLog ( GV ) , GV ) ; printVisibility ( name , GV -> getVisibility ( ) ) ; O << <STR_LIT> << name << <STR_LIT> ; O << <STR_LIT> << name << ',' << TD -> getTypeAllocSize ( C -> getType ( ) ) << '\n' ; O << name << <STR_LIT> ; EmitGlobalConstant ( C )


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return { Instruction :: FPToUI } ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return { Instruction :: SIToFP } ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return { Instruction :: UIToFP } ; case <STR_LIT> : return { Instruction :: FAdd , FTZ_Any } ; case <STR_LIT> : return { Instruction :: FAdd , FTZ_MustBeOff } ; case <STR_LIT> : return { Instruction :: FAdd , FTZ_MustBeOn } ; case <STR_LIT> : return { Instruction :: FMul , FTZ_Any } ; case <STR_LIT> : return { Instruction :: FMul , FTZ_MustBeOff } ; case <STR_LIT> : return { Instruction :: FMul , FTZ_MustBeOn } ; case <STR_LIT> : return { Instruction :: FDiv , FTZ_Any } ; case <STR_LIT> : return { Instruction :: FDiv , FTZ_MustBeOff } ; case <STR_LIT> : return { Instruction :: FDiv , FTZ_MustBeOn } ; case <STR_LIT> : return { SPC_Reciprocal , FTZ_Any } ; case <STR_LIT> : return { SPC_Reciprocal , FTZ_MustBeOff } ; case <STR_LIT> : return { SPC_Reciprocal , FTZ_MustBeOn } ; default : return { } ; } } ( ) ; if ( Action . FtzRequirement != FTZ_Any ) { StringRef Attr = II -> getFunction ( ) -> getFnAttribute ( <STR_LIT> ) . getValueAsString ( ) ; DenormalMode Mode = parseDenormalFPAttribute ( Attr ) ; bool FtzEnabled = Mode . Output != DenormalMode :: IEEE ; if ( FtzEnabled != ( Action . FtzRequirement == FTZ_MustBeOn ) ) return nullptr ; } if ( Action . IID ) { SmallVector < Value * , <NUM_LIT> > Args ( II -> args ( ) ) ; Type * Tys [ ] = { II -> getArgOperand ( <NUM_LIT> ) -> getType ( ) } ; return CallInst :: Create ( <STR_LIT> ( II -> getModule ( ) , * Action . IID , Tys ) , Args ) ; } if ( Action . BinaryOp ) return BinaryOperator :: Create ( * Action . BinaryOp , II -> getArgOperand ( <NUM_LIT> ) , II -> getArgOperand ( <NUM_LIT> ) , II -> getName ( ) ) ; if ( Action . CastOp ) return CastInst :: Create ( * Action . CastOp , II -> getArgOperand ( <NUM_LIT> ) , II -> getType ( ) , II -> getName ( ) ) ; if ( ! Action . Special ) return nullptr ; switch ( * Action . Special )


<s> initialize<ISA_LIT>LutCacheCounterPass ( * PassRegistry :: getPassRegistry


<s> return getMCOpcodeGen ( Opcode , ( enum Subtarget )


<s> void setSRetReturnReg ( unsigned Reg


<s> SDValue Result = DAG . getTargetGlobalAddress ( GV , dl , VT , Offset ) ; return DAG . getNode ( <STR_LIT> , dl ,


<s> if ( MI -> isCall ( ) ) RegDefs . insert ( <STR_LIT> ) ; if ( MI -> isReturn ( ) ) RegUses . insert ( <STR_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i != e ; ++ i ) { const MachineOperand & MO = MI -> getOperand ( i


<s> MCSection * Cur = OutStreamer -> getCurrentSectionOnly ( ) ; MCSection * Nt = MMI -> getContext ( ) . getELFSection ( <STR_LIT> , ELF :: SHT_NOTE , ELF :: SHF_ALLOC ) ; OutStreamer -> SwitchSection ( Nt ) ; EmitAlignment ( Align ( <NUM_LIT> ) ) ; OutStreamer -> EmitIntValue ( <NUM_LIT> , <NUM_LIT> ) ; OutStreamer -> EmitIntValue ( <NUM_LIT> * <NUM_LIT> , <NUM_LIT> ) ; OutStreamer -> EmitIntValue ( ELF :: NT_GNU_PROPERTY_TYPE_0 , <NUM_LIT> ) ; OutStreamer -> EmitBytes ( StringRef ( <STR_LIT> , <NUM_LIT> ) ) ; OutStreamer -> EmitIntValue ( ELF :: GNU_PROPERTY_AARCH64_FEATURE_1_AND , <NUM_LIT> ) ; OutStreamer -> EmitIntValue ( <NUM_LIT> , <NUM_LIT> ) ; OutStreamer -> EmitIntValue ( Flags


<s> } if ( Disp . isImm ( ) && isDisp8 ( Disp . getImm ( ) ) ) { EmitByte ( ModRMByte ( <NUM_LIT> , RegOpcodeField , BaseRegNo ) , CurByte , OS ) ; EmitImmediate ( Disp , <NUM_LIT> , FK_Data_1 , CurByte , OS , Fixups ) ; return ; } EmitByte ( ModRMByte ( <NUM_LIT> , RegOpcodeField , BaseRegNo ) , CurByte , OS ) ; EmitImmediate ( Disp , <NUM_LIT> , MCFixupKind ( <STR_LIT> ) , CurByte , OS , Fixups ) ; return ; } assert ( IndexReg . getReg ( ) != <STR_LIT> && IndexReg . getReg ( ) != <STR_LIT> && <STR_LIT> ) ; bool ForceDisp32 = false ; bool ForceDisp8 = false ; if ( BaseReg == <NUM_LIT> ) { EmitByte ( ModRMByte ( <NUM_LIT> , RegOpcodeField , <NUM_LIT> ) , CurByte , OS ) ; ForceDisp32 = true ; } else if ( ! Disp . isImm ( ) ) { EmitByte ( ModRMByte ( <NUM_LIT> , RegOpcodeField , <NUM_LIT> ) , CurByte , OS ) ; ForceDisp32 = true ; } else if ( Disp . getImm ( ) == <NUM_LIT> && BaseRegNo != N86 :: EBP ) { EmitByte ( ModRMByte ( <NUM_LIT> , RegOpcodeField , <NUM_LIT> ) , CurByte , OS ) ; } else if ( isDisp8 ( Disp . getImm ( ) ) ) { EmitByte ( ModRMByte ( <NUM_LIT> , RegOpcodeField , <NUM_LIT> ) , CurByte , OS ) ; ForceDisp8 = true ; } else { EmitByte ( ModRMByte ( <NUM_LIT> , RegOpcodeField , <NUM_LIT> ) , CurByte , OS ) ; } static const unsigned SSTable [ ] = { ~ <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , ~ <NUM_LIT> , <NUM_LIT> , ~ <NUM_LIT> , ~ <NUM_LIT> , ~ <NUM_LIT> , <NUM_LIT> } ; unsigned SS = SSTable [ Scale . getImm ( ) ] ; if ( BaseReg == <NUM_LIT> ) { unsigned IndexRegNo ; if ( IndexReg . getReg ( ) ) IndexRegNo = Get<ISA_LIT>RegNum ( IndexReg ) ; else IndexRegNo = <NUM_LIT> ; EmitSIBByte ( SS , IndexRegNo , <NUM_LIT> , CurByte , OS ) ; } else { unsigned IndexRegNo ; if ( IndexReg . getReg ( ) ) IndexRegNo = Get<ISA_LIT>RegNum ( IndexReg ) ; else IndexRegNo = <NUM_LIT> ; EmitSIBByte ( SS , IndexRegNo , Get<ISA_LIT>RegNum ( Base ) , CurByte , OS ) ; } if ( ForceDisp8 ) EmitImmediate ( Disp , <NUM_LIT> , FK_Data_1 , CurByte ,


<s> f_gpr = TYPE_FIELDS ( TREE_TYPE ( va_list_type_node ) ) ; f_fpr = DECL_CHAIN ( f_gpr ) ; f_res = DECL_CHAIN ( f_fpr ) ; f_ovf = DECL_CHAIN ( f_res ) ; f_sav = DECL_CHAIN ( f_ovf ) ; valist = build_simple_mem_ref ( valist ) ; gpr = build3 ( COMPONENT_REF , TREE_TYPE ( f_gpr ) , valist , f_gpr , NULL_TREE ) ; fpr = build3 ( COMPONENT_REF , TREE_TYPE ( f_fpr ) , unshare_expr ( valist ) , f_fpr , NULL_TREE ) ; ovf = build3 ( COMPONENT_REF , TREE_TYPE ( f_ovf ) , unshare_expr ( valist ) , f_ovf , NULL_TREE ) ; sav = build3 ( COMPONENT_REF , TREE_TYPE ( f_sav ) , unshare_expr ( valist ) , f_sav , NULL_TREE ) ; words = crtl -> args . info . words ; n_gpr = MIN ( crtl -> args . info . sysv_gregno - GP_ARG_MIN_REG , GP_ARG_NUM_REG ) ; n_fpr = MIN ( crtl -> args . info . fregno - FP_ARG_MIN_REG , FP_ARG_NUM_REG ) ; if ( TARGET_DEBUG_ARG ) fprintf ( stderr , <STR_LIT> HOST_WIDE_INT_PRINT_DEC <STR_LIT> HOST_WIDE_INT_PRINT_DEC <STR_LIT> HOST_WIDE_INT_PRINT_DEC <STR_LIT> , words , n_gpr , n_fpr ) ; if ( cfun -> va_list_gpr_size


<s> if ( ( pstate_field == <STR_LIT> || pstate_field == <STR_LIT> || pstate_field == <STR_LIT> ) && crm > <NUM_LIT> ) return Fail ; Inst . addOperand ( MCOperand :: createImm ( pstate_field ) ) ; Inst . addOperand ( MCOperand :: createImm ( crm ) ) ; const <ISA_LIT>Disassembler * Dis = static_cast < const <ISA_LIT>Disassembler * > ( Decoder ) ; auto PState = <STR_LIT> ( pstate_field ) ; if ( PState && PState -> haveFeatures ( Dis -> getSubtargetInfo ( ) . getFeatureBits ( ) ) ) return Success ; return Fail


<s> if ( ! trySkipToken ( AsmToken :: Comma ) ) return TokError ( <STR_LIT> ) ; if ( ParseAsAbsoluteExpression ( Stepping ) ) return TokError ( <STR_LIT> ) ; if ( ! trySkipToken ( AsmToken :: Comma ) ) return TokError ( <STR_LIT> ) ; if ( ! parseString ( VendorName , <STR_LIT> ) ) return true ; if ( ! trySkipToken ( AsmToken :: Comma ) ) return TokError ( <STR_LIT> ) ; if ( ! parseString ( ArchName , <STR_LIT> ) ) return true ; getTargetStreamer ( ) . EmitDirectiveHSACodeObjectISAV2 ( Major , Minor , Stepping ,


<s> Ctx = & M -> getContext ( ) ; LLVM_DEBUG ( dbgs ( ) <<


<s> addPass ( create<ISA_LIT>DelaySlotFillerPass ( TM ) ) ; if ( TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . hasStandardEncoding ( ) ) addPass ( create<ISA_LIT>LongBranchPass ( TM ) ) ; if ( TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . in<ISA_LIT>16Mode ( ) ) addPass ( create<ISA_LIT>ConstantIslandPass


<s> BasicBlock * Insert = Order . empty ( ) ? ParentRegion -> getExit ( ) : Order . back ( ) -> getEntry ( ) ; BasicBlock * Flow = BasicBlock :: Create ( Context , FlowBlockName , Func , Insert ) ; DT -> addNewBlock ( Flow , Dominator ) ; ParentRegion -> getRegionInfo ( ) -> setRegionFor ( Flow , ParentRegion ) ; return


<s> const MCOperand & MO = MI . getOperand ( OpNo ) ; if ( MO . isImm ( ) ) { unsigned Res = getMachineOpValue ( MI , MO , Fixups , STI ) ; assert ( ( Res & <NUM_LIT> ) == <NUM_LIT> ) ; return Res >> <NUM_LIT> ; } assert ( MO . isExpr ( ) && <STR_LIT> ) ; const MCExpr * Expr = MO . getExpr ( ) ; Fixups . push_back ( MCFixup :: Create ( <NUM_LIT> , Expr , MCFixupKind ( <STR_LIT> ) ) ) ; return <NUM_LIT>


<s> return getBits ( insn , <NUM_LIT> , <NUM_LIT>


<s> unsigned Offset = Fixup . getOffset ( ) ; unsigned BitSize = getFixupKindInfo ( Kind ) . TargetSize ; unsigned Size = ( BitSize + <NUM_LIT> ) / <NUM_LIT> ; assert ( Offset + Size <= Data . size ( ) && <STR_LIT> ) ; Value = extractBitsForFixup ( Kind , Value ) ; if ( BitSize < <NUM_LIT> ) Value &= ( ( uint64_t ) <NUM_LIT> << BitSize ) - <NUM_LIT> ; unsigned ShiftValue = ( Size * <NUM_LIT> ) -


<s> Value * <ISA_LIT>IREmitter :: visitVDUP ( const SDNode * N ) { llvm_unreachable ( <STR_LIT> ) ; return NULL


<s> return isGeneric ( ) || isCortexA53 ( ) || isCortexA57


<s> gcc_assert ( rclass == GENERAL_REGS || rclass == BASE_REGS ) ; addr = XEXP ( mem , <NUM_LIT> ) ; if ( GET_CODE ( addr ) == PRE_MODIFY ) { gcc_assert ( REG_P ( XEXP ( addr , <NUM_LIT> ) ) && GET_CODE ( XEXP ( addr , <NUM_LIT> ) ) == PLUS && XEXP ( XEXP ( addr , <NUM_LIT> ) , <NUM_LIT> ) == XEXP ( addr , <NUM_LIT> ) ) ; scratch_or_premodify = XEXP ( addr , <NUM_LIT> ) ; if ( ! HARD_REGISTER_P ( scratch_or_premodify ) ) scratch_or_premodify = find_replacement ( & XEXP ( addr , <NUM_LIT> ) ) ; addr = XEXP ( addr , <NUM_LIT> ) ; } gcc_assert ( GET_CODE ( addr ) == PLUS || GET_CODE ( addr ) == LO_SUM ) ; rs6000_emit_move ( scratch_or_premodify , addr ,


<s> static machine_mode s390_unwind_word_mode ( void


<s> bool isImm0_7 ( ) const { if ( Kind != k_Immediate ) return false ; const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; if ( ! CE ) return false ; int64_t Value = CE -> getValue (


<s> UnwindOpcodeAssembler ( ) : HasPersonality ( <NUM_LIT> ) { OpBegins . push_back (


<s> SDValue AddrOp ; if ( LDN || ( MIN && MIN -> getOpcode ( ) == <STR_LIT> ) ) AddrOp = N -> getOperand ( <NUM_LIT> ) ; else if ( STN ) AddrOp = STN -> getOperand ( <NUM_LIT> ) ; short Imm = <NUM_LIT> ; if ( FrameIndexSDNode * FI = dyn_cast < FrameIndexSDNode > ( AddrOp . getOpcode ( ) == <STR_LIT> ? AddrOp .


<s> Mangler * Mang = AP . Mang ; const DataLayout * DL = TM . getSubtargetImpl ( ) -> getDataLayout ( ) ; MCContext & Ctx = AP . OutContext ; bool isDarwin = Triple ( TM . getTargetTriple ( ) ) . isOSDarwin ( ) ; SmallString < <NUM_LIT> > Name ; StringRef Suffix ; if ( MO . getTargetFlags ( ) == <STR_LIT> ) { if ( isDarwin ) Suffix = <STR_LIT> ; } else if ( MO . getTargetFlags ( ) & <STR_LIT> ) Suffix = <STR_LIT> ; if ( ! Suffix . empty ( ) ) Name += DL -> getPrivateGlobalPrefix ( ) ; unsigned PrefixLen = Name . size ( ) ; if ( ! MO . isGlobal ( ) ) { assert ( MO . isSymbol ( ) && <STR_LIT> ) ; Mang -> getNameWithPrefix ( Name , MO . getSymbolName ( ) ) ; } else { const GlobalValue * GV = MO . getGlobal


<s> static int current_file_function_operand ( rtx sym_ref ) { if ( ENCODED_SHORT_CALL_ATTR_P ( XSTR ( sym_ref , <NUM_LIT>


<s> CommentStream = & cStream ; InternalInstruction internalInstr ; dlog_t loggerFn = logger ; if ( & vStream == & nulls ( ) ) loggerFn = nullptr ; int ret = decodeInstruction ( & internalInstr , regionReader , ( const void * ) & region , loggerFn , ( void * ) & vStream , ( const

void * ) MII . get ( ) , address , fMode ) ;


<s> LatticeCell LSL , LSH ; if ( ! getCell ( RL , Inputs , LSL ) || ! getCell ( RH , Inputs , LSH ) ) return false ; if ( LSL . isProperty ( ) || LSH . isProperty ( ) ) return false ; unsigned LN = LSL . size ( ) , HN = LSH . size ( ) ; SmallVector < APInt , <NUM_LIT> > LoVs ( LN ) , HiVs ( HN ) ; for ( unsigned i = <NUM_LIT> ; i < LN ; ++ i ) { bool Eval = constToInt ( LSL . Values [ i ] , LoVs [ i ] ) ; if ( ! Eval ) return false ; assert ( LoVs [ i ] . getBitWidth ( ) == <NUM_LIT> ) ; } for ( unsigned i = <NUM_LIT> ; i < HN ; ++ i ) { bool Eval = constToInt ( LSH . Values [ i ] , HiVs [ i ] ) ; if ( ! Eval )


<s> uint64_t Index = cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) . getNode ( ) ) -> getZExtValue ( ) ; unsigned VL = N -> getValueType ( <NUM_LIT> ) . getVectorNumElements


<s> int regno ; if ( reload_completed && cfun -> machine -> frame_laid_out ) return cfun -> machine -> current_frame_size ; if ( cfun -> static_chain_decl != NULL ) size += ( <NUM_LIT> * UNITS_PER_WORD ) ; cfun -> machine -> callee_save_size = <NUM_LIT> ; for ( regno = <NUM_LIT> ; regno < FIRST_PSEUDO_REGISTER


<s> const uint16_t * <ISA_LIT>RegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { static const uint16_t CalleeSavedRegs [ ] = { <STR_LIT> , <NUM_LIT> } ; return


<s> const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; return MFI -> getStackSize ( ) && ( DisableFramePointerElim ( MF ) || MFI ->


<s> static bool isVFRegister ( unsigned Reg ) { return Reg >= <STR_LIT> &&


<s> unsigned VandOpc = ! Is128B ? <STR_LIT> : <STR_LIT> ; BuildMI ( B , It , DL , HII . get ( VandOpc ) , TmpR1 ) . addReg ( SrcR , getKillRegState ( IsKill ) ) . addReg ( TmpR0 , RegState :: Kill ) ; auto * HRI = B . getParent ( ) -> getSubtarget < <ISA_LIT>Subtarget > ( ) . getRegisterInfo ( ) ; HII . storeRegToStackSlot ( B , It , TmpR1 , true , FI , RC , HRI ) ; expandStoreVec ( B , std :: prev ( It ) ,


<s> static void ix86_emit_restore_sse_regs_using_mov ( HOST_WIDE_INT cfa_offset , bool maybe_eh_return ) { unsigned int regno ; for ( regno = <NUM_LIT> ; regno < FIRST_PSEUDO_REGISTER ; regno ++ ) if ( SSE_REGNO_P ( regno ) && ix86_save_reg ( regno , maybe_eh_return ) ) { rtx reg = gen_rtx_REG ( V4SFmode , regno ) ; rtx mem ; mem = choose_baseaddr ( cfa_offset ) ; mem = gen_rtx_MEM ( V4SFmode


<s> <ISA_LIT>3DNowLevel = NoThreeDNow ; HasCMov = false ; Has<ISA_LIT>_64 = false ; HasPOPCNT = false ; HasSSE4A = false ; HasAES = false ; HasFXSR = false ; HasXSAVE = false ; HasXSAVEOPT = false ; HasXSAVEC = false ; HasXSAVES = false ; HasPCLMUL = false ; HasFMA = false ; HasFMA4 = false ; HasXOP = false ; HasTBM = false ; HasMOVBE = false ; HasRDRAND = false ; HasF16C = false ; HasFSGSBase =


<s> Register Val = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; LLT Ty = MRI . getType ( Val ) ; assert ( ! Ty . isVector ( ) && <STR_LIT> ) ; assert ( Ty == MRI . getType ( Dst ) && <STR_LIT> ) ; unsigned Size = Ty . getSizeInBits ( ) ; assert ( ( Size == <NUM_LIT> || Size == <NUM_LIT> ) && <STR_LIT> ) ; if ( Size == <NUM_LIT> ) Val = MIRBuilder . buildZExt ( LLT :: scalar ( <NUM_LIT> ) , Val ) . getReg ( <NUM_LIT> ) ; const LLT V8S8 = LLT :: vector ( <NUM_LIT> , LLT :: scalar ( <NUM_LIT> ) ) ; Val = MIRBuilder . buildBitcast ( V8S8 , Val ) . getReg ( <NUM_LIT> ) ; auto CTPOP = MIRBuilder . buildCTPOP ( V8S8


<s> initializeFixupBWInstPassPass ( * PassRegistry :: getPassRegistry


<s> bool <ISA_LIT>AsmParser :: parseSetNoReorderDirective ( ) { Parser . Lex ( ) ; if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement


<s> if ( VT . getSimpleVT ( ) . isVector ( ) ) { if ( Subtarget . hasVSX ( ) ) { if ( VT != <STR_LIT> && VT != <STR_LIT> && VT != <STR_LIT> && VT


<s> return hash_rtx ( p1 , VOIDmode , NULL , NULL , FALSE


<s> unsigned SaveExecOpc = ST . isWave32 ( ) ? <STR_LIT> : <STR_LIT> ; unsigned XorTermOpc = ST . isWave32 ( ) ? <STR_LIT> : <STR_LIT> ; unsigned AndOpc = ST . isWave32 ( ) ? <STR_LIT> : <STR_LIT> ; const auto * BoolXExecRC = TRI -> getRegClass ( <STR_LIT> ) ; MachineBasicBlock :: iterator I = LoopBB . begin ( ) ; Register VRsrc = Rsrc . getReg ( ) ; unsigned VRsrcUndef = getUndefRegState ( Rsrc . isUndef ( ) ) ; Register SaveExec = MRI . createVirtualRegister ( BoolXExecRC ) ; Register CondReg0 = MRI . createVirtualRegister ( BoolXExecRC ) ; Register CondReg1 = MRI . createVirtualRegister ( BoolXExecRC ) ; Register AndCond = MRI . createVirtualRegister ( BoolXExecRC ) ; Register SRsrcSub0 = MRI . createVirtualRegister ( & <STR_LIT> ) ; Register SRsrcSub1 = MRI . createVirtualRegister ( & <STR_LIT> ) ; Register SRsrcSub2 = MRI . createVirtualRegister ( & <STR_LIT> ) ; Register SRsrcSub3 = MRI . createVirtualRegister ( & <STR_LIT> ) ; Register SRsrc = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( LoopBB , I , DL , TII . get ( <STR_LIT> ) , SRsrcSub0 ) . addReg ( VRsrc , VRsrcUndef , <STR_LIT> ) ; BuildMI ( LoopBB , I , DL , TII . get ( <STR_LIT> ) , SRsrcSub1 ) . addReg ( VRsrc , VRsrcUndef , <STR_LIT> ) ; BuildMI ( LoopBB , I , DL , TII . get ( <STR_LIT> ) , SRsrcSub2 ) . addReg ( VRsrc , VRsrcUndef , <STR_LIT> ) ; BuildMI ( LoopBB , I , DL , TII . get ( <STR_LIT> ) , SRsrcSub3 ) .


<s> return STI -> getTargetTriple ( ) . getOS ( ) == Triple :: AMDHSA && STI -> getFeatureBits ( ) . test


<s> } for ( unsigned I = <NUM_LIT> ; I < WorkQ . size ( ) ; ++ I ) { Node N = WorkQ [ I ] ; NodeSet & Ns = Edges [ N ] ; auto P = getUniqueColor ( Ns ) ; if ( P . first ) { Colors [ N ] = other ( P . second ) ; continue ; } Node C = conj ( N ) ; uint8_t ColorN = other ( None ) ; uint8_t ColorC = other ( ColorN ) ; NodeSet & Cs = Edges [ C ] ; NodeSet CopyNs = Ns ; for ( Node M : CopyNs ) { uint8_t ColorM = getColor ( M ) ; if ( ColorM == ColorC ) { Cs . insert ( M ) ; Edges [ M ] . insert ( C ) ; Ns . erase ( M ) ; Edges [ M ] . erase ( N ) ; } } Colors [ N ] = ColorN ; Colors [ C ] = ColorC ; } for ( unsigned I = <NUM_LIT> ; I != Order . size ( ) ; ++ I ) if ( Colors . count ( I ) == <NUM_LIT> ) Colors


<s> std :: string HSAMetadataString ; raw_string_ostream StrOS ( HSAMetadataString ) ; yaml :: Output YOut ( StrOS ) ; YOut <<


<s> enum tls_model tls_kind = TLS_MODEL_NONE ; rtx sym , addend ; if ( GET_CODE ( addr ) == CONST ) { split_const ( addr , & sym , & addend ) ; if ( GET_CODE ( sym ) == SYMBOL_REF

) tls_kind = SYMBOL_REF_TLS_MODEL ( sym ) ;


<s> DEBUG ( dbgs ( ) << <STR_LIT> << MBB -> getNumber ( ) << <STR_LIT> ; ) ; advanceTo ( MBB -> getFirstTerminator


<s> SMLoc S = Parser . getTok ( ) . getLoc ( ) ; const AsmToken & Tok = Parser . getTok ( ) ; if ( Tok . isNot ( AsmToken :: Identifier ) ) return MatchOperand_NoMatch ; int Num = MatchCoprocessorOperandName ( Tok . getString ( ) , 'p' ) ; if ( Num == - <NUM_LIT> ) return MatchOperand_NoMatch ; Parser . Lex ( )


<s> break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_HIGHEST : Val = ( ( MCE -> getValue ( ) + <NUM_LIT> ) >> <NUM_LIT> ) & <NUM_LIT> ; break ; default : report_fatal_error ( <STR_LIT> ) ; } return MCConstantExpr :: create ( Val , getContext ( ) ) ; } if ( const MCSymbolRefExpr * MSRE = dyn_cast < MCSymbolRefExpr > ( Expr ) ) { StringRef Symbol = MSRE -> getSymbol ( ) . getName ( ) ; MCSymbolRefExpr :: VariantKind VK = getVariantKind ( RelocStr ) ; Res = MCSymbolRefExpr :: create ( Symbol , VK , getContext ( ) ) ; return Res ; } if ( const MCBinaryExpr * BE = dyn_cast < MCBinaryExpr > ( Expr ) ) { MCSymbolRefExpr :: VariantKind VK = getVariantKind ( RelocStr ) ; if ( <ISA_LIT>MCExpr :: isSupportedBinaryExpr ( VK , BE ) ) return <ISA_LIT>MCExpr :: create (


DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return V ;


<s> int Cc = ConvertCcString ( Format ) ; if ( Cc == - <NUM_LIT> ) { return Error ( NameLoc , <STR_LIT> ) ; } SMLoc E = SMLoc :: getFromPointer ( Parser . getTok ( ) . getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; Operands . push_back ( <STR_LIT> ( MCConstantExpr :: Create ( Cc , getContext ( ) ) , NameLoc , E ) ) ; } else { return parseMathOperation ( Name , NameLoc , Operands ) ; } Format = Name . slice ( Dot , StringRef :: npos ) ; Operands . push_back ( <STR_LIT> ( Format , NameLoc ) ) ; } setFpFormat ( Format ) ; } } if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) { if ( ParseOperand ( Operands , Mnemonic ) ) { SMLoc Loc = getLexer ( ) . getLoc ( ) ; Parser . eatToEndOfStatement ( ) ; return Error ( Loc


<s> assert ( SPAdj == <NUM_LIT> && <STR_LIT> ) ; unsigned i = <NUM_LIT> ; MachineInstr & MI = * II ; MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ; DebugLoc DL = MI . getDebugLoc ( ) ; while ( ! MI . getOperand ( i ) . isFI ( ) ) { ++ i ; assert ( i < MI . getNumOperands ( ) && <STR_LIT> ) ; } unsigned FrameReg = getFrameRegister ( MF ) ; int FrameIndex = MI . getOperand ( i ) . getIndex ( ) ; const TargetInstrInfo & TII = * MF . getSubtarget ( ) . getInstrInfo ( ) ; MachineBasicBlock & MBB = * MI . getParent ( ) ; if ( MI . getOpcode ( ) == <STR_LIT> ) { int Offset = MF . getFrameInfo ( ) . getObjectOffset ( FrameIndex ) ; MI . getOperand ( i ) . ChangeToRegister ( FrameReg , false ) ; unsigned reg = MI . getOperand ( i - <NUM_LIT> ) . getReg ( ) ; BuildMI ( MBB , ++ II , DL , TII . get ( <STR_LIT> ) , reg ) . addReg ( reg ) . addImm ( Offset ) ; return ; } int Offset = MF . getFrameInfo ( ) . getObjectOffset ( FrameIndex ) + MI . getOperand ( i + <NUM_LIT> ) . getImm ( ) ; if ( ! isInt < <NUM_LIT> > ( Offset ) ) llvm_unreachable ( <STR_LIT> ) ; if ( MI . getOpcode ( ) == <STR_LIT> ) { unsigned reg = MI . getOperand ( i - <NUM_LIT> ) . getReg ( ) ; BuildMI ( MBB , ++ II , DL , TII . get (

<STR_LIT> ) , reg ) . addReg ( FrameReg ) ;


<s> if ( FP_REG_P ( regno ) ) { if ( MSA_SUPPORTED_MODE_P ( mode ) ) return <NUM_LIT> ; return ( GET_MODE_SIZE ( mode ) + UNITS_PER_FPREG


<s> Register <ISA_LIT>TargetLowering :: getExceptionPointerRegister ( const Constant * PersonalityFn ) const { return <STR_LIT>


<s> static MCStreamer * createMCStreamer ( const Triple & TT , MCContext & Context , std :: unique_ptr < MCAsmBackend > && MAB , std :: unique_ptr < MCObjectWriter > && OW , std :: unique_ptr < MCCodeEmitter > && Emitter , bool RelaxAll ) { return createELFStreamer ( Context , std :: move ( MAB ) , std :: move ( OW ) , std ::


<s> return AMDGPU :: S_MOV_B64 ; } else if ( DstRC -> getSize ( ) == <NUM_LIT> && ! RI . isSGPRClass ( DstRC ) ) { return AMDGPU


<s> SDValue TOCOff = DAG . getIntPtrConstant ( TOCAnchorOffset , dl ) ; SDValue AddTOC = DAG . getNode ( <STR_LIT> , dl , RegVT , Callee , TOCOff ) ; SDValue TOCPtr = DAG . getLoad ( RegVT , dl , LDChain , AddTOC , MPI . getWithOffset ( TOCAnchorOffset ) , Alignment , MMOFlags ) ; SDValue PtrOff = DAG . getIntPtrConstant ( EnvPtrOffset , dl ) ; SDValue AddPtr = DAG . getNode ( <STR_LIT> , dl , RegVT , Callee , PtrOff ) ; SDValue LoadEnvPtr = DAG . getLoad ( RegVT , dl , LDChain , AddPtr , MPI . getWithOffset ( EnvPtrOffset ) , Alignment , MMOFlags ) ; SDValue TOCVal = DAG . getCopyToReg ( Chain , dl , TOCReg , TOCPtr , Glue ) ; Chain = TOCVal . getValue ( <NUM_LIT> ) ; Glue = TOCVal . getValue ( <NUM_LIT> ) ; assert ( ( ! hasNest || ! Subtarget . isAIXABI ( ) ) && <STR_LIT> ) ; if ( ! hasNest ) { SDValue EnvVal = DAG . getCopyToReg ( Chain , dl , EnvPtrReg , LoadEnvPtr , Glue ) ; Chain = EnvVal . getValue ( <NUM_LIT> ) ; Glue = EnvVal . getValue


<s> case <STR_LIT> : return IsSigned ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return IsSigned ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return IsSigned ? <STR_LIT> : <STR_LIT> ; } case <STR_LIT> : switch ( DestTy . SimpleTy ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : return IsSigned ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return IsSigned ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return IsSigned ? <STR_LIT> : <STR_LIT> ; } case <STR_LIT> : switch ( DestTy . SimpleTy ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : return IsSigned ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return IsSigned ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return IsSigned ? <STR_LIT> : <STR_LIT> ; } case <STR_LIT> : switch ( DestTy . SimpleTy ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : return IsSigned ? <STR_LIT> :


<s> void ChangeSection ( MCSection * Section , const MCExpr * Subsection ) override { LastMappingSymbols [ getPreviousSection ( ) . first ] = std :: move (