<s> DebugLoc DL = MI -> getDebugLoc ( ) ; for ( unsigned i = <NUM_LIT> , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) if ( MI -> getOperand ( i ) . getReg ( ) == Base ) return false ; int Bytes = getLSMultipleTransferSize ( MI ) ; MachineBasicBlock & MBB = * MI -> getParent ( ) ; MachineBasicBlock :: iterator MBBI ( MI ) ; int Offset ; MachineBasicBlock :: iterator MergeInstr = findIncDecBefore ( MBBI , Base , Pred , PredReg , Offset ) ; <STR_LIT> Mode = getLoadStoreMultipleSubMode ( Opcode ) ; if ( Mode == <STR_LIT> && Offset == - Bytes ) { Mode = <STR_LIT> ; } else if ( Mode == <STR_LIT> && Offset == - Bytes ) { Mode = <STR_LIT> ; } else { MergeInstr = findIncDecAfter ( MBBI , Base , Pred , PredReg , Offset ) ; if ( ( ( Mode != <STR_LIT> && Mode != <STR_LIT> ) || Offset != Bytes ) && ( ( Mode != <STR_LIT> && Mode != <STR_LIT> ) || Offset != - Bytes ) ) { if ( ! STI -> hasMinSize ( ) || ! BaseKill ) return false ; bool HighRegsUsed = false ; for ( unsigned i = <NUM_LIT> , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) if ( MI -> getOperand ( i ) . getReg ( ) >= <STR_LIT> ) { HighRegsUsed = true ; break ; } if ( ! HighRegsUsed ) MergeInstr = MBB . end ( ) ; else return false ; } } if ( MergeInstr != MBB . end ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * MergeInstr ) ; MBB . erase


<s> SDValue Vec ; if ( Size == <NUM_LIT> ) { if ( HasInt256 ) { SDValue Ops [ ] = { Cst , Cst , Cst , Cst , Cst , Cst , Cst , Cst } ; Vec = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Ops , <NUM_LIT> ) ; } else { Vec = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Cst , Cst , Cst , Cst ) ; Vec = Concat128BitVectors ( Vec , Vec , <STR_LIT> , <NUM_LIT> , DAG , dl ) ; } } else if ( Size == <NUM_LIT> ) { Vec = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Cst , Cst , Cst , Cst ) ; } else llvm_unreachable


<s> MCRegisterInfo * X = new MCRegisterInfo ( ) ; Init<ISA_LIT>MCRegisterInfo ( X , RA , <ISA_LIT>_MC :: getDwarfRegFlavour ( TT , false )

, <ISA_LIT>_MC :: getDwarfRegFlavour ( TT , true ) , RA ) ;


<s> if ( <STR_LIT> . contains ( DstReg , SrcReg ) ) { BuildMI ( MBB , MBBI , DL , get ( <STR_LIT> ) , DstReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) . addImm ( <NUM_LIT> ) . setMIFlag ( Flag ) ; return ; } else if ( <STR_LIT> . contains ( DstReg , SrcReg ) ) { BuildMI ( MBB , MBBI , DL , get ( <STR_LIT> ) , DstReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) . setMIFlag ( Flag ) ; return ; } unsigned Opc ; bool IsScalableVector = true ; unsigned NF = <NUM_LIT> ; unsigned LMul = <NUM_LIT> ; unsigned SubRegIdx = <STR_LIT> ; if ( <STR_LIT> . contains ( DstReg , SrcReg ) ) { Opc = <STR_LIT> ; IsScalableVector = false ; } else if ( <STR_LIT> . contains ( DstReg , SrcReg ) ) { Opc = <STR_LIT> ; IsScalableVector = false ; } else if ( <STR_LIT> . contains ( DstReg , SrcReg ) ) { Opc = <STR_LIT> ; IsScalableVector = false ; } else if ( <STR_LIT> . contains ( DstReg , SrcReg ) ) { Opc = <STR_LIT> ; } else if ( <STR_LIT> . contains ( DstReg , SrcReg ) ) { Opc = <STR_LIT> ; } else if ( <STR_LIT> . contains ( DstReg , SrcReg ) ) { Opc = <STR_LIT> ; } else if ( <STR_LIT> . contains ( DstReg , SrcReg ) ) { Opc = <STR_LIT> ; } else if ( <STR_LIT> . contains ( DstReg , SrcReg ) ) { Opc = <STR_LIT> ; SubRegIdx = <STR_LIT> ; NF = <NUM_LIT> ; LMul = <NUM_LIT> ; } else if ( <STR_LIT> . contains ( DstReg , SrcReg ) ) { Opc = <STR_LIT> ; SubRegIdx = <STR_LIT> ; NF = <NUM_LIT>


<s> } const Value * Cond = I -> getOperand ( <NUM_LIT> ) ; <STR_LIT> CC = <STR_LIT> ; const auto * CI = dyn_cast < CmpInst > ( Cond ) ; if ( CI && ( CI -> getParent ( ) == I -> getParent ( ) ) ) { bool NeedSwap ; std :: tie ( CC , NeedSwap ) = get<ISA_LIT>ConditionCode ( CI -> getPredicate ( ) ) ; if ( CC > <STR_LIT> ) return false ; const Value * CmpLHS = CI -> getOperand ( <NUM_LIT> ) ; const Value * CmpRHS = CI -> getOperand ( <NUM_LIT> ) ; if ( NeedSwap ) std :: swap ( CmpLHS , CmpRHS ) ; EVT CmpVT = TLI . getValueType ( CmpLHS -> getType


<s> if ( cfun && cfun -> decl ) return lookup_attribute ( <STR_LIT> , DECL_ATTRIBUTES ( cfun ->


<s> unsigned int <ISA_LIT>InstrInfo :: isStoreToStackSlot ( const MachineInstr & MI , int & FrameIndex ) const { return TargetInstrInfo :: isStoreToStackSlot ( MI


<s> if ( ! Tok . is ( AsmToken :: Colon ) && ! Tok . is ( AsmToken :: Comma ) && ! Tok . is ( AsmToken :: RBrac ) ) return Error ( Tok . getLoc ( ) , <STR_LIT> ) ; if ( Tok . is ( AsmToken :: RBrac ) ) { E = Tok . getEndLoc ( ) ; Parser . Lex ( ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateMem ( BaseRegNum , nullptr , <NUM_LIT> , <STR_LIT> , <NUM_LIT> , <NUM_LIT> , false , S , E ) ) ; if ( Parser . getTok ( ) . is ( AsmToken :: Exclaim ) ) { Operands . push_back ( <ISA_LIT>Operand :: CreateToken ( <STR_LIT> , Parser . getTok ( ) . getLoc ( ) ) ) ; Parser . Lex ( ) ; } return false ; } assert ( ( Tok . is ( AsmToken :: Colon ) || Tok . is ( AsmToken :: Comma ) ) && <STR_LIT> ) ; if ( Tok . is ( AsmToken :: Comma ) ) { Parser . Lex ( ) ; } if ( Parser . getTok ( ) . is ( AsmToken :: Colon ) ) { Parser . Lex ( ) ; E = Parser . getTok ( ) . getLoc ( ) ; SMLoc AlignmentLoc = Tok . getLoc ( ) ; const MCExpr * Expr ; if ( getParser ( ) . parseExpression ( Expr ) ) return true ; const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( Expr ) ; if ( ! CE ) return Error ( E , <STR_LIT> ) ; unsigned Align = <NUM_LIT> ; switch ( CE -> getValue ( ) ) { default : return Error ( E , <STR_LIT> ) ; case <NUM_LIT> : Align = <NUM_LIT> ; break ; case <NUM_LIT> : Align = <NUM_LIT> ; break ; case <NUM_LIT> : Align = <NUM_LIT> ; break ; case <NUM_LIT> : Align = <NUM_LIT> ; break ; case <NUM_LIT> : Align = <NUM_LIT> ; break ; } if ( Parser . getTok ( ) . isNot ( AsmToken :: RBrac ) ) return Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; E = Parser . getTok ( ) . getEndLoc ( ) ; Parser . Lex ( ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateMem ( BaseRegNum , nullptr , <NUM_LIT> , <STR_LIT> , <NUM_LIT> , Align , false , S , E , AlignmentLoc ) ) ; if ( Parser . getTok ( ) . is ( AsmToken :: Exclaim ) ) { Operands . push_back ( <ISA_LIT>Operand :: CreateToken ( <STR_LIT> , Parser . getTok ( ) . getLoc ( ) ) ) ; Parser . Lex ( ) ; } return


<s> const MCOperandInfo & MOI = this -> MII . get ( MI -> getOpcode ( ) ) . OpInfo [ OpNo ] ; if ( Op . isReg ( ) ) { bool isPtrReg = ( MOI . RegClass == <STR_LIT> ) || ( MOI . RegClass == <STR_LIT> ) || ( MOI . RegClass == <STR_LIT> ) ; if ( isPtrReg ) { O << getRegisterName ( Op . getReg ( ) , <STR_LIT> ) ; } else { O << getPrettyRegisterName ( Op . getReg (


<s> Type * <ISA_LIT>CodeGenPrepare :: getI32Ty ( IRBuilder < > & B , const Type * T ) const { assert ( needsPromotionToI32 ( T ) && <STR_LIT> ) ; if ( T -> isIntegerTy ( ) ) return B


<s> OutStreamer . SwitchSection ( fCodeSection ) ; O << <STR_LIT> << PAN :: getFrameLabel ( CurrentFnSym -> getName ( ) ) << <STR_LIT> ; O << <STR_LIT> << PAN :: getFrameLabel ( CurrentFnSym -> getName ( ) ) << <STR_LIT> ; O << * CurrentFnSym << <STR_LIT> ; DebugLoc CurDL ; O << <STR_LIT> ; for ( MachineFunction :: const_iterator I = MF . begin ( ) , E = MF . end ( ) ; I != E ; ++ I ) { if ( I != MF . begin ( ) ) { EmitBasicBlockStart ( I ) ; } for ( MachineBasicBlock :: const_iterator II = I -> begin ( ) , E = I -> end ( ) ; II != E ;


<s> MachineInstr & SI = * SII ; LLVM_DEBUG ( errs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( SI . dump ( ) ) ; BuildMI ( * SI . getParent ( ) , SI , SI . getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addReg ( SI

. getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( SI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ;


<s> void DecodeVPERM2F128Mask ( unsigned Imm , SmallVectorImpl < unsigned > & ShuffleMask ) { return DecodeVPERM2F128Mask ( <STR_LIT> , Imm , ShuffleMask


<s> ScheduleDAGInstrs * createMachineScheduler ( MachineSchedContext * C ) const override { return create<ISA_LIT>VLIWMachineSched ( C


<s> <STR_LIT> <ISA_LIT>HazardRecognizer970 :: GetInstrType ( unsigned Opcode , bool & isFirst , bool & isSingle , bool & isCracked , bool & isLoad , bool & isStore ) { const MCInstrDesc & MCID = TM . getInstrInfo ( ) -> get ( Opcode ) ; isLoad = MCID . mayLoad ( ) ; isStore = MCID . mayStore ( ) ; uint64_t TSFlags = MCID . TSFlags ; isFirst = TSFlags & <STR_LIT> ; isSingle = TSFlags & <STR_LIT> ; isCracked = TSFlags & <STR_LIT> ; return ( <STR_LIT> ) ( TSFlags &


<s> SDValue TrueV = Op . getOperand ( <NUM_LIT> ) ; SDValue FalseV = Op . getOperand ( <NUM_LIT> ) ; <STR_LIT> CC = cast < CondCodeSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> get ( ) ; SDValue <ISA_LIT>CC ; SDValue Flag = EmitCMP ( LHS , RHS , <ISA_LIT>CC , CC , dl , DAG ) ; return DAG . getNode ( <STR_LIT> , dl , VT , TrueV , FalseV


<s> do_load_for_compare_from_addr ( load_mode , d2 , src2_addr , orig_src2 ) ; do_sub3 ( shift_amount , GEN_INT ( load_mode_size ) , cmp_rem ) ; if ( word_mode == DImode ) { emit_insn ( gen_ashldi3 ( shift_amount , shift_amount , GEN_INT ( LOG2_BITS_PER_UNIT ) ) ) ; emit_insn ( gen_lshrdi3 ( d1 , d1 , gen_lowpart ( SImode , shift_amount ) ) ) ; emit_insn ( gen_lshrdi3 ( d2 , d2 , gen_lowpart ( SImode , shift_amount ) ) ) ; } else { emit_insn ( gen_ashlsi3 ( shift_amount , shift_amount , GEN_INT ( LOG2_BITS_PER_UNIT ) ) ) ; emit_insn ( gen_lshrsi3 ( d1 , d1 , shift_amount ) ) ; emit_insn ( gen_lshrsi3 ( d2 , d2 , shift_amount ) ) ; } if ( TARGET_P9_MISC ) { rtx cmp = gen_rtx_COMPARE ( CCUNSmode , d1 , d2 ) ; emit_insn ( gen_rtx_SET ( dcond , cmp ) ) ; } else { if ( word_mode == DImode ) emit_insn ( gen_subfdi3_carry ( diff , d2 , d1 ) ) ; else emit_insn ( gen_subfsi3_carry ( diff ,


<s> if ( isSExtLd ) Opcode = isPre ? <STR_LIT> : <STR_LIT> ; else Opcode = isPre ? <STR_LIT> : <STR_LIT> ; } else if ( Align >= <NUM_LIT> && ( CanChangeType || LoadedVT == <STR_LIT> || LoadedVT == <STR_LIT> ) && SelectT2AddrModeImm7Offset ( N , Offset , NewOffset , <NUM_LIT> ) ) Opcode = isPre ? <STR_LIT> : <STR_LIT> ; else if ( Align >= <NUM_LIT> && ( CanChangeType || LoadedVT == <STR_LIT> || LoadedVT == <STR_LIT> ) && SelectT2AddrModeImm7Offset ( N , Offset , NewOffset , <NUM_LIT> ) ) Opcode = isPre ? <STR_LIT> : <STR_LIT> ; else if ( ( CanChangeType || LoadedVT == <STR_LIT> ) && SelectT2AddrModeImm7Offset ( N , Offset , NewOffset , <NUM_LIT> ) ) Opcode = isPre ? <STR_LIT> : <STR_LIT> ; else return false ; SDValue Ops [ ] = { Base , NewOffset , CurDAG -> getTargetConstant ( Pred , SDLoc ( N ) , <STR_LIT> ) , PredReg , Chain } ; SDNode * New = CurDAG -> getMachineNode ( Opcode , SDLoc ( N ) , N -> getValueType ( <NUM_LIT> ) , <STR_LIT> , <STR_LIT> , Ops ) ; transferMemOperands ( N , New ) ; ReplaceUses ( SDValue ( N , <NUM_LIT> ) , SDValue ( New , <NUM_LIT> ) ) ; ReplaceUses ( SDValue ( N , <NUM_LIT> ) , SDValue ( New , <NUM_LIT> ) ) ; ReplaceUses ( SDValue ( N , <NUM_LIT> ) , SDValue ( New , <NUM_LIT> ) ) ; CurDAG -> RemoveDeadNode ( N


<s> return ( ( int ) ( spu_extract ( spu_orx ( spu_rlmask ( spu_cmpgt ( a , b ) , - <NUM_LIT> )


<s> if ( ST . debuggerEmitPrologue ( ) ) emitDebuggerPrologue ( MF , MBB ) ; if ( ! MF . getFrameInfo ( ) . hasStackObjects ( ) ) return ; assert ( & MF . front ( ) == & MBB && <STR_LIT> ) ; <ISA_LIT>MachineFunctionInfo * MFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; if ( hasOnlySGPRSpills ( MFI , MF . getFrameInfo ( ) ) ) return ; const <ISA_LIT>InstrInfo * TII = ST . getInstrInfo ( ) ; const <ISA_LIT>RegisterInfo * TRI = & TII -> getRegisterInfo ( ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; MachineBasicBlock :: iterator I = MBB . begin ( ) ; unsigned ScratchRsrcReg = MFI -> getScratchRSrcReg ( ) ; assert ( ScratchRsrcReg != <STR_LIT> ) ; unsigned ScratchWaveOffsetReg = MFI -> getScratchWaveOffsetReg ( ) ; assert ( ScratchWaveOffsetReg != <STR_LIT> ) ; unsigned PreloadedScratchWaveOffsetReg = TRI -> getPreloadedValue ( MF , <ISA_LIT>RegisterInfo :: PRIVATE_SEGMENT_WAVE_BYTE_OFFSET ) ; unsigned PreloadedPrivateBufferReg = <STR_LIT> ; if ( ST . isAmdHsaOS ( ) ) { PreloadedPrivateBufferReg = TRI -> getPreloadedValue ( MF , <ISA_LIT>RegisterInfo :: PRIVATE_SEGMENT_BUFFER ) ; } if ( MFI -> hasFlatScratchInit ( ) ) { DebugLoc DL ; unsigned FlatScratchInitReg = TRI -> getPreloadedValue ( MF , <ISA_LIT>RegisterInfo :: FLAT_SCRATCH_INIT ) ; MRI . addLiveIn ( FlatScratchInitReg ) ; MBB . addLiveIn ( FlatScratchInitReg ) ; unsigned FlatScrInitHi = TRI -> getSubReg ( FlatScratchInitReg , <STR_LIT> ) ; BuildMI ( MBB , I , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( FlatScrInitHi , RegState :: Kill ) ; unsigned FlatScrInitLo = TRI -> getSubReg ( FlatScratchInitReg , <STR_LIT> ) ; BuildMI ( MBB , I , DL , TII -> get ( <STR_LIT> ) , FlatScrInitLo ) . addReg ( FlatScrInitLo ) . addReg ( ScratchWaveOffsetReg ) ; BuildMI ( MBB , I , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( FlatScrInitLo , RegState :: Kill ) . addImm ( <NUM_LIT> ) ; } if ( ScratchRsrcReg == PreloadedPrivateBufferReg ) { assert ( ScratchWaveOffsetReg == PreloadedScratchWaveOffsetReg && <STR_LIT> ) ; return ; } MRI . addLiveIn ( PreloadedScratchWaveOffsetReg ) ; MBB . addLiveIn ( PreloadedScratchWaveOffsetReg ) ; if ( ST . isAmdHsaOS ( ) ) { MRI . addLiveIn ( PreloadedPrivateBufferReg ) ; MBB . addLiveIn ( PreloadedPrivateBufferReg ) ; } if ( ! ST . hasSGPRInitBug ( ) ) { if ( ScratchRsrcReg == TRI -> reservedPrivateSegmentBufferReg ( MF ) ) { MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; unsigned NumPreloaded = MFI -> getNumPreloadedSGPRs ( ) / <NUM_LIT> ; for ( MCPhysReg Reg : getAllSGPR128 ( ) . drop_back ( <NUM_LIT> ) . slice ( NumPreloaded ) ) { if ( ! MRI . isPhysRegUsed ( Reg ) ) { assert ( MRI . isAllocatable ( Reg ) ) ; MRI . replaceRegWith ( ScratchRsrcReg


<s> MI -> print ( errs ( ) ) ; } if ( MI -> isBundle ( ) ) { const MachineBasicBlock * MBB = MI -> getParent ( ) ; MachineBasicBlock :: const_instr_iterator I = ++ MI -> getIterator ( ) ; while ( I != MBB -> instr_end ( ) && I -> isInsideBundle ( ) ) { EmitInstruction ( & * I ) ; ++ I ; } } else { if ( MI -> getOpcode ( ) == <STR_LIT> ) { if ( isVerbose ( ) ) { SmallVector < char , <NUM_LIT> > BBStr ; raw_svector_ostream Str ( BBStr ) ; const MachineBasicBlock * MBB = MI -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; const MCSymbolRefExpr * Expr = MCSymbolRefExpr :: create ( MBB -> getSymbol ( ) , OutContext ) ; Expr -> print ( Str , MAI ) ; OutStreamer -> emitRawComment ( Twine ( <STR_LIT> ) + BBStr ) ; } return ; } if ( MI -> getOpcode ( ) == <STR_LIT> ) { if ( isVerbose ( ) ) OutStreamer -> emitRawComment ( <STR_LIT> ) ; return ; } if ( MI -> getOpcode ( ) == <STR_LIT> ) { if ( isVerbose ( ) ) OutStreamer -> emitRawComment ( <STR_LIT> ) ; return ; } if ( MI -> getOpcode ( ) == <STR_LIT> ) { if ( isVerbose ( ) ) OutStreamer -> emitRawComment ( <STR_LIT> ) ; return ; } MCInst TmpInst ; MCInstLowering . lower ( MI , TmpInst ) ; EmitToStreamer ( * OutStreamer , TmpInst ) ; if ( STI . dumpCode ( ) ) { DisasmLines . resize ( DisasmLines . size ( ) + <NUM_LIT> ) ; std :: string & DisasmLine = DisasmLines . back ( ) ; raw_string_ostream DisasmStream ( DisasmLine


<s> MachineOperand RegOp0 = getLdStRegOp ( * RtMI ) ; MachineOperand RegOp1 = getLdStRegOp ( * Rt2MI ) ; if ( RegOp0 . isUse ( ) ) { if ( ! MergeForward ) { RegOp0 . setIsKill ( false ) ; RegOp1 . setIsKill ( false ) ; } else { Register Reg = getLdStRegOp ( * I ) . getReg ( ) ; for ( MachineInstr & MI : make_range ( std :: next ( I ) , Paired ) ) MI . clearRegisterKills ( Reg , TRI ) ; } } unsigned int MatchPairOpcode = getMatchingPairOpcode ( Opc ) ; MIB = BuildMI ( * MBB , InsertionPoint , DL , TII -> get ( MatchPairOpcode ) ) ; if ( <ISA_LIT>InstrInfo :: isPreLdSt ( * RtMI ) ) MIB . addReg ( BaseRegOp . getReg ( ) , RegState :: Define ) ; MIB . add ( RegOp0 ) . add ( RegOp1 ) . add ( BaseRegOp ) . addImm ( OffsetImm ) . cloneMergedMemRefs ( { & * I , & * Paired } ) . setMIFlags ( I -> mergeFlagsWith ( * Paired ) ) ; ( void ) MIB ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( I -> print ( dbgs ( ) ) ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( Paired -> print ( dbgs ( ) ) ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; if ( SExtIdx != - <NUM_LIT> ) { MachineOperand & DstMO = MIB -> getOperand ( SExtIdx ) ; Register DstRegX = DstMO . getReg ( ) ; Register DstRegW = TRI -> getSubReg ( DstRegX , <STR_LIT> ) ; DstMO . setReg ( DstRegW ) ; LLVM_DEBUG ( ( ( MachineInstr * ) MIB ) -> print ( dbgs ( ) ) ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; MachineInstrBuilder MIBKill = BuildMI ( * MBB , InsertionPoint , DL , TII -> get ( TargetOpcode :: KILL ) , DstRegW ) . addReg ( DstRegW ) . addReg ( DstRegX , RegState :: Define ) ; MIBKill -> getOperand ( <NUM_LIT> ) . setImplicit ( ) ; MachineInstrBuilder MIBSXTW = BuildMI ( * MBB , InsertionPoint , DL , TII -> get ( <STR_LIT> ) , DstRegX ) . addReg ( DstRegX ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; ( void ) MIBSXTW ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( ( ( MachineInstr * ) MIBSXTW ) -> print


<s> static bool rx_allocate_stack_slots_for_args ( void ) { return ! is_naked_func (


<s> return SinglePathFIs [ SPCallSpillOffset + <NUM_LIT> ]


<s> unsigned LR = HRI . getRARegister ( ) ; if ( ( Op . getOpcode ( ) != <STR_LIT> && Op . getOpcode ( ) != <STR_LIT> ) || HMFI . hasClobberLR ( ) ) return Op ; unsigned NumOps = Op . getNumOperands ( ) ; if ( Op . getOperand ( NumOps - <NUM_LIT> ) . getValueType ( ) == <STR_LIT> ) -- NumOps ; for ( unsigned i = InlineAsm :: Op_FirstOperand ; i != NumOps ; ) { unsigned Flags = cast < ConstantSDNode > ( Op . getOperand ( i ) ) -> getZExtValue ( ) ; unsigned NumVals = InlineAsm :: getNumOperandRegisters ( Flags ) ; ++ i ; switch ( InlineAsm :: getKind ( Flags ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case InlineAsm :: Kind_RegUse : case InlineAsm :: Kind_Imm : case InlineAsm :: Kind_Mem : i +=


<s> for ( const MachineOperand & Op : MI . explicit_operands ( ) ) if ( isIndex ( Op , RI ) ) return true ; return


<s> MCOperand <ISA_LIT>MCInstLower :: LowerOperand ( const MachineOperand & MO ) const { MachineOperandType MOTy = MO . getType ( ) ; switch ( MOTy ) { default : assert ( <NUM_LIT> && <STR_LIT> ) ; break ; case MachineOperand :: MO_Register : if ( MO . isImplicit ( ) ) break ; return MCOperand :: CreateReg ( MO .


<s> for ( temp_node = file_head ; temp_node != <NUM_LIT> ; tail_node = temp_node , temp_node = temp_node -> next ) if ( strcmp ( temp_node -> name , file_name ) == <NUM_LIT> ) { current_file = temp_node ; break ; } if ( temp_node


<s> MCELFStreamer * create<ISA_LIT>NaClELFStreamer ( MCContext & Context , MCAsmBackend & TAB , raw_ostream & OS , MCCodeEmitter * Emitter , bool RelaxAll ) { <ISA_LIT>NaClELFStreamer * S = new <ISA_LIT>NaClELFStreamer ( Context , TAB , OS , Emitter ) ; if ( RelaxAll ) S -> getAssembler


<s> while ( isPredicated ( * I ) || I -> isTerminator ( ) || I -> isDebugValue ( ) ) { bool CantAnalyze = false ; while ( I -> isDebugValue ( ) || ! I -> isTerminator ( ) ) { if ( I == MBB . begin ( ) ) return false ; -- I ; } if ( isJumpOpcode ( I -> getOpcode ( ) ) ) { CantAnalyze = true ; } else if ( isUncondBranchOpcode ( I -> getOpcode ( ) ) ) { TBB = I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; } else if ( isCondBranchOpcode ( I -> getOpcode ( ) ) ) { if ( ! Cond . empty ( ) ) return true ; assert ( ! FBB && <STR_LIT> ) ; FBB = TBB ; TBB = I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; Cond . push_back ( I -> getOperand ( <NUM_LIT> ) ) ; Cond . push_back ( I -> getOperand ( <NUM_LIT> ) ) ; Cond . push_back ( I -> getOperand ( <NUM_LIT> ) ) ; } else if ( I -> isReturn ( ) ) { CantAnalyze = ! isPredicated ( * I ) ; } else { return true ; } if ( ! isPredicated ( * I ) && ( isUncondBranchOpcode ( I -> getOpcode ( ) ) || isJumpOpcode ( I -> getOpcode ( ) ) || I -> isReturn ( ) ) ) { Cond . clear


<s> static SDValue performIFJMPCombine ( SDNode * N , TargetLowering :: DAGCombinerInfo & DCI , SelectionDAG & DAG ) { SDValue Chain = N -> getOperand ( <NUM_LIT> ) ; SDValue N1 = N -> getOperand ( <NUM_LIT> ) ; SDValue Dest = N -> getOperand ( <NUM_LIT> ) ; if ( N1 . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; SDValue LHS = N1 -> getOperand ( <NUM_LIT> ) ; SDValue RHS = N1 -> getOperand ( <NUM_LIT> ) ; <STR_LIT> CC = cast < CondCodeSDNode > ( N1 -> getOperand ( <NUM_LIT> ) ) -> get ( ) ; if ( CC != <STR_LIT> :: SETNE ) return SDValue ( ) ; if ( LHS . getValueType ( ) != <STR_LIT> ) return SDValue ( ) ; if ( isNullConstant ( LHS ) ) std :: swap ( LHS , RHS ) ; if ( ! isNullConstant ( RHS ) ) return SDValue ( ) ; auto RV = DAG . getNode ( <STR_LIT> , SDLoc ( N ) , <STR_LIT> , Chain


<s> return TargetTriple . getEnvironment ( ) == Triple :: GNUEABIHF || TargetTriple . getEnvironment (


<s> if ( MO . isReg ( ) ) return Ctx . getRegisterInfo ( ) -> getEncodingValue ( MO . getReg ( ) ) ; if ( MO . isImm ( ) ) return static_cast < unsigned > ( MO . getImm ( ) ) ; llvm_unreachable ( <STR_LIT>


<s> if ( RegNo > <NUM_LIT> ) return MCDisassembler :: Fail ; uint16_t Register = getReg ( Decoder , <STR_LIT> , RegNo ) ; Inst . addOperand ( MCOperand :: CreateReg ( Register ) ) ; return MCDisassembler ::


<s> LLVM_EXTERNAL_VISIBILITY void LLVMInitialize<ISA_LIT>Disassembler ( ) { TargetRegistry :: RegisterMCDisassembler ( getThe<ISA_LIT>Target ( ) , create<ISA_LIT>Disassembler ) ; TargetRegistry :: RegisterMCDisassembler ( getThe<ISA_LIT>elTarget ( ) , create<ISA_LIT>elDisassembler ) ; TargetRegistry :: RegisterMCDisassembler ( getThe<ISA_LIT>64Target ( ) , create<ISA_LIT>Disassembler ) ; TargetRegistry :: RegisterMCDisassembler ( getThe<ISA_LIT>64elTarget ( ) , create<ISA_LIT>elDisassembler


<s> } else { Carry = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) , Carry ) ; Carry = ConvertBooleanCarryToCarryFlag ( Carry , DAG ) ; Result = DAG . getNode ( <STR_LIT> , DL , VTs , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Carry . getValue ( <NUM_LIT> ) ) ; Carry = ConvertCarryFlagToBooleanCarry ( Result . getValue ( <NUM_LIT> ) , VT


<s> assert ( VT == <STR_LIT> && <STR_LIT> ) ; SDValue Flag ; Flag = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> ) ; Flag = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Flag ) ; return DAG . getNode ( <STR_LIT> , dl , DAG . getVTList ( VT , <STR_LIT> ) , Op0 ,


<s> Inst . addOperand ( MCOperand :: createReg ( GPRDecoderTable [ Register ] ) ) ; unsigned Offset = ( Insn & <NUM_LIT> ) ; Inst . addOperand ( MCOperand :: createImm ( SignExtend32 < <NUM_LIT> > ( Offset ) ) ) ; return MCDisassembler :: Success


<s> return isRegOrImmWithInputMods ( <STR_LIT> , <STR_LIT>


<s> inline static unsigned encode<ISA_LIT>AluCode ( unsigned AluOp ) { unsigned const OP_ENCODING_MASK = <NUM_LIT> ; return AluOp &


<s> if ( Bytes . size ( ) < <NUM_LIT> ) { Size = <NUM_LIT> ; return MCDisassembler :: Fail ; } uint32_t Inst = IsLittleEndian ? <STR_LIT> :: read32le ( Bytes . data ( ) ) : <STR_LIT> :: read32be ( Bytes . data ( ) ) ; if ( STI . getFeatureBits ( ) [ <STR_LIT> ] ) { DecodeStatus result = decodeInstruction ( DecoderTableQPX32 , MI , Inst , Address , this , STI ) ; if ( result != MCDisassembler ::


<s> static SDValue LowerSCALAR_TO_VECTOR ( SDValue Op , SelectionDAG & DAG ) { SDValue Op0 = Op . getOperand ( <NUM_LIT> ) ; DebugLoc dl = Op . getDebugLoc ( ) ; if ( Op0 . getNode ( ) -> getOpcode ( ) == <STR_LIT> ) { ConstantSDNode * CN = cast < ConstantSDNode > ( Op0 . getNode ( ) ) ; SmallVector < SDValue , <NUM_LIT> > ConstVecValues ; EVT VT ; size_t n_copies ; switch ( Op . getValueType ( ) . getSimpleVT ( ) . SimpleTy ) { default : llvm_unreachable ( <STR_LIT> <STR_LIT> ) ; case <STR_LIT> : n_copies = <NUM_LIT> ; VT = <STR_LIT> ; break ; case <STR_LIT> : n_copies = <NUM_LIT> ; VT = <STR_LIT> ; break ; case <STR_LIT> : n_copies = <NUM_LIT> ; VT = <STR_LIT> ; break ; case <STR_LIT> : n_copies = <NUM_LIT> ; VT = <STR_LIT> ; break ; case <STR_LIT> : n_copies = <NUM_LIT> ; VT = <STR_LIT> ; break ; case <STR_LIT> : n_copies = <NUM_LIT> ; VT = <STR_LIT> ; break ; } SDValue CValue = DAG . getConstant ( CN -> getZExtValue ( )


<s> void MetadataStreamer :: emitKernelArg ( const Argument & Arg ) { auto Func = Arg . getParent ( ) ; auto ArgNo = Arg . getArgNo ( ) ; const MDNode * Node ; StringRef TypeQual ; Node = Func -> getMetadata ( <STR_LIT> ) ; if ( Node && ArgNo < Node -> getNumOperands ( ) ) TypeQual = cast < MDString > ( Node -> getOperand ( ArgNo ) ) -> getString ( ) ; StringRef BaseTypeName ; Node = Func -> getMetadata (


<s> if ( IsPextr ) { const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; if ( TLI . SimplifyDemandedBits ( SDValue ( N , <NUM_LIT> ) , APInt :: getAllOnes ( VT . getSizeInBits ( ) ) , DCI ) ) return SDValue ( N , <NUM_LIT> ) ; if ( ( InputVector . getOpcode ( ) == <STR_LIT> || InputVector . getOpcode ( ) == <STR_LIT> ) && InputVector . getOperand ( <NUM_LIT> ) == EltIdx ) { assert ( SrcVT == InputVector . getOperand ( <NUM_LIT> ) . getValueType ( ) && <STR_LIT> ) ; SDValue Scl = InputVector . getOperand ( <NUM_LIT> ) ; Scl = DAG . getNode ( <STR_LIT> , dl , SrcVT . getScalarType ( ) , Scl ) ; return DAG . getZExtOrTrunc ( Scl , dl , VT ) ; } return SDValue ( ) ; } if ( InputVector . getOpcode ( ) == <STR_LIT> && InputVector . hasOneUse ( ) && VT == <STR_LIT> && SrcVT == <STR_LIT> && isNullConstant ( EltIdx ) ) { SDValue MMXSrc = InputVector . getOperand ( <NUM_LIT> ) ; if ( MMXSrc . getValueType ( ) == <STR_LIT> ) return DAG . getBitcast ( VT , InputVector ) ; } if ( InputVector . getOpcode ( ) == <STR_LIT> && InputVector . hasOneUse ( ) && VT == <STR_LIT> && SrcVT == <STR_LIT> && isNullConstant ( EltIdx ) ) { SDValue MMXSrc = InputVector . getOperand ( <NUM_LIT> ) ; if ( MMXSrc . getValueType ( ) == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , MMXSrc ) ; } if ( SDValue SAD = combineBasicSADPattern ( N , DAG , Subtarget ) ) return SAD ; if ( SDValue VPDPBUSD = combineVPDPBUSDPattern ( N , DAG , Subtarget ) ) return VPDPBUSD ; if ( SDValue Cmp = combinePredicateReduction ( N , DAG , Subtarget ) ) return Cmp ; if ( SDValue MinMax = combineMinMaxReduction ( N , DAG , Subtarget ) ) return MinMax ; if ( SDValue V = combineArithReduction ( N , DAG , Subtarget ) ) return V ; if ( SDValue V = scalarizeExtEltFP ( N , DAG , Subtarget ) ) return V ; if ( SrcVT . getScalarType ( ) == <STR_LIT> ) { bool IsVar = ! CIdx ; SmallVector < SDNode * , <NUM_LIT> > BoolExtracts ; unsigned ResNo = InputVector . getResNo ( ) ; auto IsBoolExtract = [ & BoolExtracts , & ResNo , & IsVar ] ( SDNode * Use ) { if ( Use -> getOpcode ( ) == <STR_LIT> && Use -> getOperand ( <NUM_LIT> ) . getResNo ( ) == ResNo && Use -> getValueType ( <NUM_LIT> ) == <STR_LIT> ) { BoolExtracts . push_back ( Use


<s> BinOp -> setHasNoSignedWrap ( I . hasNoSignedWrap ( ) ) ; BinOp -> setHasNoUnsignedWrap ( I . hasNoUnsignedWrap ( ) ) ; } else if ( isa < PossiblyExactOperator > ( BinOp ) ) BinOp -> setIsExact ( I . isExact (


<s> Record . push_back ( VE . getMetadataOrNullID ( N -> getRawDirectory ( ) ) ) ; Stream . EmitRecord ( bitc :: METADATA_FILE , Record , Abbrev


<s> if ( ! <ISA_LIT>FastEmitCompare ( CI -> getOperand ( <NUM_LIT> ) , CI -> getOperand ( <NUM_LIT> ) , VT ) ) return false ; unsigned EReg = createResultReg ( & <STR_LIT> ) ; unsigned NPReg = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , EReg ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , NPReg ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , ResultReg ) . addReg ( NPReg ) . addReg ( EReg ) ; UpdateValueMap ( I , ResultReg ) ; return true ; } case CmpInst :: FCMP_UNE : { if ( ! <ISA_LIT>FastEmitCompare ( CI -> getOperand ( <NUM_LIT> ) , CI -> getOperand ( <NUM_LIT> ) , VT ) ) return false ; unsigned NEReg = createResultReg ( & <STR_LIT> ) ; unsigned PReg = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , NEReg ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , PReg ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , ResultReg ) . addReg ( PReg ) . addReg ( NEReg ) ; UpdateValueMap ( I , ResultReg ) ; return true ; } case CmpInst :: FCMP_OGT : SwapArgs = false ; SetCCOpc = <STR_LIT> ; break ; case CmpInst :: FCMP_OGE : SwapArgs = false ; SetCCOpc = <STR_LIT> ; break ; case CmpInst :: FCMP_OLT : SwapArgs = true ; SetCCOpc = <STR_LIT> ; break ; case CmpInst :: FCMP_OLE : SwapArgs = true ; SetCCOpc = <STR_LIT> ; break ; case CmpInst :: FCMP_ONE : SwapArgs = false ; SetCCOpc = <STR_LIT> ; break ; case CmpInst :: FCMP_ORD : SwapArgs = false ; SetCCOpc = <STR_LIT> ; break ; case CmpInst :: FCMP_UNO : SwapArgs = false ; SetCCOpc = <STR_LIT> ; break ; case CmpInst :: FCMP_UEQ : SwapArgs = false ; SetCCOpc = <STR_LIT> ; break ; case CmpInst :: FCMP_UGT : SwapArgs = true ; SetCCOpc = <STR_LIT> ; break ; case CmpInst :: FCMP_UGE : SwapArgs = true ; SetCCOpc = <STR_LIT> ; break ; case CmpInst :: FCMP_ULT : SwapArgs = false ; SetCCOpc = <STR_LIT> ; break ; case CmpInst :: FCMP_ULE : SwapArgs = false ; SetCCOpc = <STR_LIT> ; break ; case CmpInst :: ICMP_EQ : SwapArgs = false ; SetCCOpc = <STR_LIT> ; break ; case CmpInst :: ICMP_NE : SwapArgs = false ; SetCCOpc = <STR_LIT> ; break ; case CmpInst :: ICMP_UGT : SwapArgs = false ; SetCCOpc = <STR_LIT>


<s> virtual const TargetFrameInfo * getFrameInfo ( ) const { return &


<s> const_tree decl = SYMBOL_REF_DECL ( sym ) ; bool is_weak = ( decl && DECL_P ( decl ) && DECL_WEAK ( decl ) ) ; if ( ! is_weak && SYMBOL_REF_LOCAL_P ( sym ) ) emit_insn ( gen_sym_label2reg (


<s> for ( auto & MBB : * MF ) { if ( ! PrevCanFallthough ) { Changed = true ; MBB . setAlignment ( Alignment ) ; } PrevCanFallthough = MBB . canFallThrough ( ) ; if ( STI -> hasLOB ( ) ) { for ( const auto & MI : reverse ( MBB . terminators ( ) ) ) { if ( MI . getOpcode ( ) == <STR_LIT> && MI . getOperand ( <NUM_LIT> ) . getMBB ( ) == MBB . getNextNode ( ) ) continue ; if ( isLoopStart ( MI ) || MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> ) { PrevCanFallthough =


<s> if ( TfrLimitActive ) { if ( TfrCounter >= TfrLimit ) return false ; TfrCounter ++ ; } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << printMBBReference ( * MI . getParent ( ) ) << <STR_LIT> << MI ) ; MachineOperand & MD = MI . getOperand ( <NUM_LIT> ) ; MachineOperand & MP = MI . getOperand ( <NUM_LIT> ) ; assert ( MD . isDef ( ) ) ; unsigned DR = MD . getReg ( ) , DSR = MD . getSubReg ( ) ; bool ReadUndef = MD . isUndef ( ) ; MachineBasicBlock :: iterator At = MI ; auto updateRegs = [ & UpdRegs ] ( const MachineInstr & MI ) -> void { for ( auto & Op : MI . operands ( ) ) if ( Op . isReg ( ) ) UpdRegs . insert ( Op . getReg ( ) ) ; } ; MachineOperand & ST = MI . getOperand ( <NUM_LIT> ) ; MachineOperand & SF = MI . getOperand ( <NUM_LIT> ) ; if ( ST . isReg ( ) && SF . isReg ( ) ) { RegisterRef RT ( ST ) ; if ( RT == RegisterRef ( SF ) ) { updateRegs ( MI ) ; MI . setDesc ( HII -> get ( TargetOpcode :: COPY ) ) ; unsigned S = getRegState ( ST ) ; while ( MI . getNumOperands ( ) > <NUM_LIT> ) MI . RemoveOperand ( MI . getNumOperands ( ) - <NUM_LIT> ) ; MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ; MachineInstrBuilder ( MF , MI ) . addReg ( RT . Reg , S , RT . Sub ) ; return true


<s> MachineInstrBuilder MIB = BuildMI ( MBB , MI , dl , NewMCID ) ; MIB . addOperand ( MI -> getOperand ( <NUM_LIT> ) ) ; if ( NewMCID . hasOptionalDef ( ) ) { if ( HasCC ) AddDefaultT1CC ( MIB , CCDead ) ; else AddNoT1CC ( MIB ) ; } unsigned NumOps = MCID . getNumOperands ( ) ; for ( unsigned i = <NUM_LIT> , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) { if ( i < NumOps && MCID . OpInfo [ i ] . isOptionalDef ( ) ) continue ; if ( ( MCID . getOpcode ( ) == <STR_LIT> || MCID . getOpcode ( ) == <STR_LIT> || MCID . getOpcode ( ) == <STR_LIT> || MCID . getOpcode ( ) == <STR_LIT> || MCID . getOpcode ( ) == <STR_LIT> || MCID . getOpcode ( ) == <STR_LIT> ) && i == <NUM_LIT> ) continue ; bool isPred = ( i < NumOps && MCID . OpInfo [ i ] . isPredicate ( ) ) ; if ( SkipPred && isPred ) continue ; const MachineOperand & MO = MI -> getOperand ( i ) ; if ( MO . isReg ( ) && MO . isImplicit ( ) && MO . getReg ( ) == <STR_LIT> ) continue ; MIB . addOperand ( MO ) ; } if ( ! MCID . isPredicable ( ) && NewMCID . isPredicable ( ) ) AddDefaultPred ( MIB ) ; MIB . setMIFlags ( MI


) _MM_SET_FLUSH_ZERO_MODE ( unsigned int __mode ) {


<s> if ( ! Unsafe && VT == <STR_LIT> && Subtarget -> hasFP32Denormals ( ) ) return SDValue ( ) ; if ( const ConstantFPSDNode * CLHS = dyn_cast < ConstantFPSDNode > ( LHS ) ) { if ( Unsafe || VT == <STR_LIT> || VT == <STR_LIT> ) { if ( CLHS -> isExactlyValue ( <NUM_LIT> ) ) { if ( RHS . getOpcode ( ) == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , SL , VT , RHS . getOperand ( <NUM_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , SL , VT , RHS ) ; } if ( CLHS -> isExactlyValue ( - <NUM_LIT> ) ) { SDValue FNegRHS = DAG . getNode ( <STR_LIT> , SL , VT , RHS ) ; return DAG . getNode ( <STR_LIT> , SL , VT , FNegRHS ) ; } } } const SDNodeFlags * Flags = Op -> getFlags ( ) ; if ( Unsafe || Flags -> hasAllowReciprocal ( ) ) { SDNodeFlags


<s> unsigned IID = cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; switch (


<s> if ( DCI . isBeforeLegalizeOps ( ) ) return SDValue ( ) ; if ( SDValue Zext = VectorZextCombine ( N , DAG , DCI , Subtarget ) ) return Zext ; if ( SDValue R = CMPEQCombine ( N , DAG , DCI , Subtarget ) ) return R ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; SDValue N0 = N -> getOperand ( <NUM_LIT> ) ; SDValue N1 = N -> getOperand ( <NUM_LIT> ) ; SDLoc DL ( N ) ; if ( VT == <STR_LIT> || VT == <STR_LIT> ) { if ( ( Subtarget -> hasBMI ( ) || Subtarget -> hasTBM ( ) ) && ( N0 . getOpcode ( ) == <STR_LIT> || N0 . getOpcode ( ) == <STR_LIT> ) ) { ConstantSDNode * MaskNode = dyn_cast < ConstantSDNode > ( N1 ) ; ConstantSDNode * ShiftNode = dyn_cast < ConstantSDNode > ( N0 . getOperand ( <NUM_LIT> ) ) ; if ( MaskNode && ShiftNode ) { uint64_t Mask = MaskNode -> getZExtValue ( ) ; uint64_t Shift = ShiftNode -> getZExtValue ( ) ; if ( isMask_64 ( Mask ) ) { uint64_t MaskSize = countPopulation ( Mask ) ; if ( Shift + MaskSize <= VT . getSizeInBits ( ) ) return DAG . getNode ( <STR_LIT> , DL , VT , N0 . getOperand ( <NUM_LIT> ) , DAG . getConstant ( Shift | ( MaskSize << <NUM_LIT> ) , VT ) ) ; } } } return SDValue ( ) ; } if ( VT != <STR_LIT> && VT != <STR_LIT> )


<s> if ( island . size ( ) > stubGroupSize ( ) ) { error ( diag :: err_no_space_to_place_stubs ) << stubGroupSize ( ) ; return false ; } if ( island . numOfStubs ( ) == <NUM_LIT> ) { continue ; } Fragment * exit = & * island . end ( ) ; if ( exit == & * island . begin ( ) -> getParent ( ) -> end ( ) ) { continue ; } if ( ( island . offset ( ) + island . size ( ) ) > exit -> getOffset ( ) ) { if ( invalid_frags . empty ( ) || ( invalid_frags . back ( ) -> getParent ( ) != island . getParent ( ) ) ) { invalid_frags . push_back ( exit ) ; pFinished = false ; } continue ; } } for ( auto it = invalid_frags . begin ( ) , ie = invalid_frags . end ( ) ; it != ie ; ++ it ) { Fragment * invalid = * it ; while ( invalid != NULL ) { invalid -> setOffset ( invalid -> getPrevNode ( ) -> getOffset ( ) +

invalid -> getPrevNode ( ) -> size ( ) ) ;


<s> void <ISA_LIT>CFGStructurizer :: orderBlocks ( MachineFunction * MF ) { int SccNum = <NUM_LIT> ; MachineBasicBlock * MBB ; for ( scc_iterator < MachineFunction * > It = scc_begin ( MF ) ; ! It . isAtEnd ( ) ; ++ It , ++ SccNum ) { const std :: vector < MachineBasicBlock * > & SccNext


<s> int _U_Qfne ( long double a , long double b ) { return ( _U_Qfcmp ( a , b , <NUM_LIT>


<s> bool <ISA_LIT>FrameLowering :: hasFP ( const MachineFunction & MF ) const { const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const TargetRegisterInfo * RegInfo = MF . getTarget (


<s> assert ( InstMaskEnd >= <NUM_LIT> && <STR_LIT> ) ; SDValue Ops [ ] = { V , getI32Imm ( RLAmt ) , getI32Imm ( InstMaskStart - <NUM_LIT> ) , getI32Imm ( InstMaskEnd - <NUM_LIT> ) } ; return SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , Ops ) , <NUM_LIT> ) ; } if ( InstMaskEnd == <NUM_LIT> ) { SDValue Ops [ ] = { V , getI32Imm ( RLAmt ) , getI32Imm ( InstMaskStart ) } ; return SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , Ops ) , <NUM_LIT> ) ; } if ( InstMaskStart == <NUM_LIT> ) { SDValue Ops [ ] = { V , getI32Imm ( RLAmt ) , getI32Imm ( InstMaskEnd ) } ; return SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , Ops ) , <NUM_LIT> ) ; } if ( InstMaskEnd == <NUM_LIT> - RLAmt ) { SDValue Ops [ ] = { V , getI32Imm ( RLAmt ) , getI32Imm ( InstMaskStart ) } ; return SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , Ops ) , <NUM_LIT> ) ; } if ( InstCnt ) * InstCnt += <NUM_LIT> ; unsigned RLAmt2 = MaskStart


<s> for ( unsigned I = <NUM_LIT> , E = ( MI . getNumOperands ( ) - <NUM_LIT> ) / <NUM_LIT> ; I < E ; ++ I ) if ( MI . getOperand ( <NUM_LIT> + <NUM_LIT> * I + <NUM_LIT> ) . getImm ( ) == SubReg ) { auto & RegOp = MI . getOperand ( <NUM_LIT> + <NUM_LIT> * I ) ; return getRegOrUndef ( RegOp ) ; } return TargetInstrInfo :: RegSubRegPair


<s> rtx mode_mask = GEN_INT ( mode == QImode ? <NUM_LIT> : <NUM_LIT> ) ; shift = expand_binop ( SImode , and_optab , gen_lowpart ( SImode , addr ) , mode_mask , NULL_RTX , <NUM_LIT> , OPTAB_LIB_WIDEN ) ; if ( BYTES_BIG_ENDIAN ) shift = expand_binop ( SImode , xor_optab , shift , mode_mask , shift , <NUM_LIT> , OPTAB_LIB_WIDEN ) ; shift = expand_binop ( SImode , ashl_optab , shift , GEN_INT ( <NUM_LIT>

) , shift , <NUM_LIT> , OPTAB_LIB_WIDEN ) ;


<s> const char * insn_name = TARGET_CB_NEVER || reg_p ? <STR_LIT> : <STR_LIT> ; if ( ! final_sequence && ( TARGET_CB_MAYBE || ( ISA_HAS_JRC && ! link_p && reg_p ) ) ) { compact = <STR_LIT> ; nop = <STR_LIT> ; } if ( TARGET_USE_GOT && ! TARGET_EXPLICIT_RELOCS ) sprintf ( s , <STR_LIT> , insn_name , and_link , target_opno ) ; else { if ( ! reg_p && TARGET_ABICALLS_PIC2 ) s += sprintf ( s , <STR_LIT> ) ; if ( reg_p && mips_get_pic_call_symbol ( operands , size_opno ) ) { s += sprintf ( s , <STR_LIT> , size_opno ) ; short_delay =


<s> if ( ! CC . UsePush ) { Advantage -= <NUM_LIT> ; } else { Advantage -= <NUM_LIT> ; if ( ! isAligned ( StackAlign , CC . ExpectedDist ) ) Advantage -= <NUM_LIT> ; Advantage += ( CC . ExpectedDist >> Log2SlotSize


<s> if ( ! insn ) return ; if ( arc_verify_short ( insn , cfun -> machine -> unalign , <NUM_LIT> ) ) { fprintf ( file , <STR_LIT>


<s> if ( Subtarget -> isTargetNaCl ( ) ) EmitAlignment ( std :: max ( MF -> getAlignment ( ) , MIPS_NACL_BUNDLE_ALIGN ) ) ; if ( Subtarget -> inMicro<ISA_LIT>Mode ( ) ) TS . emitDirectiveSetMicro<ISA_LIT> ( ) ; else TS . emitDirectiveSetNoMicro<ISA_LIT> ( ) ; if ( Subtarget -> in<ISA_LIT>16Mode ( ) )


<s> andCC = true ; } } <STR_LIT> CC = cast < CondCodeSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> get ( ) ; SDValue TargetCC ; SDValue Flag = EmitCMP ( LHS , RHS , TargetCC , CC , dl , DAG ) ; bool Invert = false ; bool Shift = false ; bool Convert = true ; switch ( cast < ConstantSDNode > ( TargetCC ) -> getZExtValue ( ) ) { default : Convert = false ; break ; case <STR_LIT> : break ; case <STR_LIT> : Invert = true ; break ; case <STR_LIT> : if ( andCC ) { } else { Shift = true ; Invert = true ; } break ; case <STR_LIT> : Shift = true ; break ; } EVT VT = Op . getValueType ( ) ; SDValue One = DAG . getConstant


<s> return instAccessReg ( MI -> defs ( )


<s> void setMaxCallFrameSize ( unsigned S


<s> void microblaze_asm_output_ident ( const char * string ) { const char * section_asm_op ; int size ; char * buf ; if ( symtab -> state != PARSING ) return ; size = strlen ( string ) + <NUM_LIT> ; if ( size <= microblaze_section_threshold ) section_asm_op = SDATA2_SECTION_ASM_OP ; else section_asm_op = READONLY_DATA_SECTION_ASM_OP ; buf = ACONCAT ( ( <STR_LIT> , section_asm_op , <STR_LIT> , string


<s> if ( Opnd0 . getOpcode ( ) != <STR_LIT> || ! Opnd0 -> hasNUsesOfValue ( ExpectedUses , <NUM_LIT> ) || ! Subtarget . hasAnyFMA ( ) ) return false ; const TargetOptions & Options = DAG . getTarget ( ) . Options ; bool AllowFusion = ( Options . AllowFPOpFusion == FPOpFusion :: Fast || Options . UnsafeFPMath


<s> unsigned NumVectorInstToHideOverhead = <NUM_LIT> ; if ( Ty -> isVectorTy ( ) && IsComplex ) return NumVectorInstToHideOverhead ; return TargetTransformInfo :: getAddressComputationCost (


<s> const <ISA_LIT>Subtarget & SubTarget = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; Metadata * isCFProtectionSupported = MF . getMMI ( ) . getModule ( ) -> getModuleFlag ( <STR_LIT> ) ; if ( ! isCFProtectionSupported && ! IndirectBranchTracking ) return false ; bool Changed = false ; TII = SubTarget . getInstrInfo ( ) ; EndbrOpcode = SubTarget . is64Bit ( ) ? <STR_LIT> : <STR_LIT> ; if ( ( MF . getFunction ( ) . hasAddressTaken ( ) || ! MF . getFunction ( ) . hasLocalLinkage ( ) ) && ! MF . getFunction ( ) . doesNoCfCheck ( ) ) { auto MBB = MF . begin ( ) ; Changed |= addENDBR ( * MBB , MBB -> begin ( ) ) ; } for ( auto & MBB : MF ) { if ( MBB . hasAddressTaken ( ) ) Changed |= addENDBR ( MBB , MBB . begin ( ) ) ; for ( MachineBasicBlock :: iterator I = MBB . begin ( ) ; I != MBB . end ( ) ;


<s> assert ( N -> getOffset ( ) == <NUM_LIT> && <STR_LIT> ) ; const GlobalValue * GV = N -> getGlobal ( ) ; bool IsLocal = getTargetMachine ( ) . shouldAssumeDSOLocal ( * GV ->


<s> static rtx sparc_struct_value_rtx ( tree fndecl , int incoming ) { if ( TARGET_ARCH64 ) return <NUM_LIT> ; else { rtx mem ; if ( incoming ) mem = gen_frame_mem ( Pmode , plus_constant ( Pmode , frame_pointer_rtx , STRUCT_VALUE_OFFSET ) ) ; else mem = gen_frame_mem ( Pmode , plus_constant ( Pmode , stack_pointer_rtx , STRUCT_VALUE_OFFSET ) ) ; if ( incoming == <NUM_LIT> && sparc_std_struct_return && TYPE_SIZE_UNIT ( TREE_TYPE ( fndecl ) ) && TREE_CODE ( TYPE_SIZE_UNIT ( TREE_TYPE ( fndecl ) ) ) == INTEGER_CST ) { rtx ret_reg = gen_rtx_REG ( Pmode , RETURN_ADDR_REGNUM ) ; rtx scratch = gen_reg_rtx ( SImode


<s> if ( dep_type == <NUM_LIT> ) return cost ; if ( GET_MODE_CLASS ( GET_MODE ( SET_SRC ( dep_set ) ) ) != MODE_FLOAT ) return cost ; if ( ! set_is_load_p ( insn_set ) && ! set_is_store_p ( insn_set ) ) return cost ; if ( GET_MODE_CLASS ( GET_MODE ( SET_SRC ( insn_set ) ) ) != MODE_INT ) return cost ; timings = get_attr_timings ( insn ) ; return timings < <NUM_LIT> ? ( timings % <NUM_LIT> ) : ( timings %


<s> llvm_unreachable ( <STR_LIT> ) ; case MachineOperand :: MO_FPImmediate : { const APFloat & FloatValue = MO . getFPImm ( ) -> getValueAPF ( ) ; assert ( & FloatValue . getSemantics ( ) == & APFloat :: IEEEsingle && <STR_LIT> ) ; MCOp = MCOperand :: CreateFPImm ( FloatValue . convertToFloat ( ) ) ; break ; } case MachineOperand ::


<s> for ( unsigned i = <NUM_LIT> , e = CSI . size ( ) ; i != e ; ++ i ) BuildMI ( MBB ,

MI , DL , TII . get ( <STR_LIT> ) , CSI [ i ] . getReg ( ) ) ;


<s> void <ISA_LIT>InstPrinter :: printSHFMask ( const MCInst * MI , int opNum , raw_ostream & O ) { llvm_unreachable ( <STR_LIT> )


<s> <ISA_LIT>TRI = static_cast < const <ISA_LIT>RegisterInfo * > ( TRI ) ; VGPRSetID = <ISA_LIT>TRI ->


<s> MachineBasicBlock * FBB = nullptr ; <STR_LIT> CondCode ; if ( ! endsWithCondControlFlow ( MBB , TBB , FBB , CondCode ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; } else { <STR_LIT> InvCondCode = <STR_LIT> ( CondCode ) ; MachineBasicBlock * SplitEdgeTBB = MBB . SplitCriticalEdge ( TBB , * this ) ; MachineBasicBlock * SplitEdgeFBB = MBB . SplitCriticalEdge ( FBB , * this ) ; assert ( SplitEdgeTBB != nullptr ) ; assert ( SplitEdgeFBB != nullptr ) ; DebugLoc DL ; if ( MBB . instr_end ( ) != MBB . instr_begin ( ) ) DL = ( -- MBB . instr_end ( ) ) -> getDebugLoc ( ) ; insertTrackingCode ( * SplitEdgeTBB , CondCode , DL ) ; insertTrackingCode ( * SplitEdgeFBB , InvCondCode , DL ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * SplitEdgeTBB << <STR_LIT> ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * SplitEdgeFBB << <STR_LIT> ) ; Modified = true ; } SmallVector < std :: pair < MachineInstr * , unsigned > , <NUM_LIT> > ReturnInstructions ; SmallVector < std :: pair < MachineInstr * , unsigned > , <NUM_LIT> > CallInstructions ; bool TmpRegisterNotAvailableEverywhere = false ; RegScavenger RS ; RS . enterBasicBlock ( MBB ) ; for ( MachineBasicBlock :: iterator I = MBB . begin ( ) ; I != MBB . end ( ) ; I ++ ) { MachineInstr & MI = * I ; if ( ! MI . isReturn ( ) && ! MI . isCall ( ) ) continue ; if ( I != MBB . begin ( ) ) RS . forward ( std :: prev ( I ) ) ; unsigned TmpReg = RS . FindUnusedReg ( & <STR_LIT> ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << ( ( TmpReg == <NUM_LIT> ) ? <STR_LIT> : <STR_LIT> ) ; if ( TmpReg != <NUM_LIT> ) dbgs ( ) << printReg ( TmpReg , TRI ) << <STR_LIT> ; dbgs ( ) << <STR_LIT> << MI ) ; if ( TmpReg == <NUM_LIT> ) TmpRegisterNotAvailableEverywhere = true ; if ( MI . isReturn ( ) ) ReturnInstructions . push_back ( { & MI , TmpReg } ) ; else if ( MI . isCall ( ) ) CallInstructions . push_back ( { & MI , TmpReg } ) ; } if ( TmpRegisterNotAvailableEverywhere ) { insertFullSpeculationBarrier ( MBB , MBB . begin ( ) , ( MBB . begin ( ) ) -> getDebugLoc ( ) ) ; UsesFullSpeculationBarrier = true ; Modified = true ; } else { for ( auto MI_Reg : ReturnInstructions ) { assert ( MI_Reg . second != <NUM_LIT> ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << printReg ( MI_Reg . second , TRI ) << <STR_LIT> << * MI_Reg . first ) ; insertRegToSPTaintPropagation ( MBB , MI_Reg . first , MI_Reg . second ) ; Modified = true ; } for ( auto MI_Reg :


<s> } break ; case <STR_LIT> : for ( unsigned i = <NUM_LIT> ; i != NumElts ; ++ i ) { SDValue CurrentOp = SrcOp -> getOperand ( i ) ; if ( CurrentOp -> isUndef ( ) ) { Elts . push_back ( CurrentOp ) ; continue ; } auto * ND = cast < ConstantSDNode > ( CurrentOp ) ; const APInt & C = ND -> getAPIntValue ( ) ; Elts . push_back ( DAG . getConstant ( C . lshr ( ShiftAmt ) , dl , ElementType ) ) ; } break ; case <STR_LIT> : for ( unsigned i = <NUM_LIT> ; i != NumElts ; ++ i ) { SDValue CurrentOp = SrcOp -> getOperand ( i ) ; if ( CurrentOp -> isUndef ( ) ) { Elts . push_back ( CurrentOp ) ; continue ; } auto * ND = cast < ConstantSDNode > ( CurrentOp ) ; const APInt & C = ND


<s> static DecodeStatus DecodeCPU16RegsRegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t Address , const


<s> int M = Mask [ i ] ; if ( M < <NUM_LIT> ) { KnownUndef . setBit ( i ) ; continue ; } if ( ( M >= <NUM_LIT> && M < Size && V1IsZero ) || ( M >= Size && V2IsZero ) ) { KnownZero . setBit ( i ) ; continue ; } SDValue V = M < Size ? V1 : V2 ; M %= Size ; if ( V . getOpcode ( ) != <STR_LIT> ) continue ; if ( ( Size % V . getNumOperands ( ) ) == <NUM_LIT> ) { int Scale = Size / V -> getNumOperands ( ) ; SDValue Op = V . getOperand ( M / Scale ) ; if ( Op . isUndef ( ) ) KnownUndef . setBit ( i ) ; if ( <STR_LIT> ( Op ) ) KnownZero . setBit ( i ) ; else if ( ConstantSDNode * Cst = dyn_cast < ConstantSDNode > ( Op ) ) { APInt Val = Cst -> getAPIntValue ( ) ; Val = Val . extractBits ( ScalarSizeInBits , ( M % Scale ) * ScalarSizeInBits ) ; if ( Val == <NUM_LIT> ) KnownZero . setBit ( i ) ; } else if ( ConstantFPSDNode * Cst = dyn_cast < ConstantFPSDNode > ( Op ) ) { APInt Val = Cst -> getValueAPF ( ) . bitcastToAPInt ( ) ; Val = Val . extractBits ( ScalarSizeInBits , ( M % Scale ) * ScalarSizeInBits ) ; if ( Val == <NUM_LIT> ) KnownZero . setBit ( i ) ; } continue ; } if ( ( V . getNumOperands ( ) % Size ) == <NUM_LIT> ) { int Scale = V -> getNumOperands ( ) / Size ; bool AllUndef = true ; bool AllZero = true ; for ( int j = <NUM_LIT> ; j < Scale ; ++ j ) { SDValue Op = V . getOperand ( ( M * Scale ) + j ) ; AllUndef &= Op . isUndef ( ) ; AllZero &= <STR_LIT> ( Op


<s> bool <ISA_LIT>PassConfig :: addInstSelector ( ) { addPass ( create<ISA_LIT>ISelDAG ( get<ISA_LIT>TargetMachine ( ) , getOptLevel ( ) ) ) ; return false


<s> return Subtarget . hasVLX ( ) || Subtarget . canExtendTo512DQ ( ) || VT . is512BitVector


<s> SDNode * <ISA_LIT>DAGToDAGISel :: Select ( SDNode * N


<s> assemble_align ( POINTER_SIZE ) ; if ( DEFAULT_ABI == ABI_V4 && ( TARGET_RELOCATABLE || flag_pic > <NUM_LIT> ) ) { fputs ( <STR_LIT> , asm_out_file ) ; output_addr_const ( asm_out_file , symbol ) ; fputs ( <STR_LIT> , asm_out_file


<s> return ( int16_t ) __builtin_aarch64_sqrdmulhhi (


<s> typedef StackMaps :: Location Location ; assert ( std :: distance ( MOI , MOE ) >= <NUM_LIT> && <STR_LIT> ) ; const MachineOperand & Base = * MOI ; const MachineOperand & Scale = * ( ++ MOI ) ; const MachineOperand & Index = * ( ++ MOI ) ; const MachineOperand & Disp = * ( ++ MOI ) ; const MachineOperand & ZeroReg = * ( ++ MOI ) ; assert ( Base . isReg ( ) && Scale . isImm ( ) && Scale . getImm ( ) == <NUM_LIT> && Index . isReg ( ) && Index . getReg ( ) == <NUM_LIT> && Disp . isImm ( ) && ZeroReg . isReg ( ) && ( ZeroReg . getReg ( ) == <NUM_LIT> ) && <STR_LIT> ) ; ( void )


<s> if ( Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic . startswith ( <STR_LIT> ) || Mnemonic . startswith ( <STR_LIT> ) || Mnemonic . startswith ( <STR_LIT> ) || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic . startswith ( <STR_LIT> ) || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic . startswith ( <STR_LIT> ) || Mnemonic . startswith ( <STR_LIT> ) || ( FullInst . startswith ( <STR_LIT> ) && FullInst . endswith ( <STR_LIT> ) ) || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT>

|| Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic . startswith ( <STR_LIT> ) || Mnemonic . startswith ( <STR_LIT> ) ) {


<s> name = XSTR ( addr , <NUM_LIT> ) ; if ( name [ strlen ( name ) - <NUM_LIT> ] != ']' && ( TREE_PUBLIC ( SYMBOL_REF_DECL ( addr ) ) || bss_initializer_p ( SYMBOL_REF_DECL ( addr ) ) ) ) { tlsname = XALLOCAVEC ( char , strlen ( name ) + <NUM_LIT> ) ; strcpy ( tlsname , name ) ; strcat ( tlsname , bss_initializer_p ( SYMBOL_REF_DECL ( addr ) ) ? <STR_LIT> : <STR_LIT> ) ; tlsaddr = copy_rtx ( addr ) ; XSTR ( tlsaddr , <NUM_LIT> ) = ggc_strdup ( tlsname ) ; } else tlsaddr = addr ; sym = force_const_mem ( GET_MODE ( tlsaddr ) , tlsaddr ) ; if ( constant_pool_expr_p ( XEXP ( sym , <NUM_LIT> ) ) && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P ( get_pool_constant ( XEXP ( sym , <NUM_LIT> ) ) , Pmode ) ) { tocref = create_TOC_reference ( XEXP ( sym , <NUM_LIT> ) , NULL_RTX ) ; mem = gen_const_mem ( Pmode , tocref ) ; set_mem_alias_set ( mem , get_TOC_alias_set ( ) ) ; } else return sym


<s> if ( Val >= - <NUM_LIT> && Val <= <NUM_LIT> ) { Imm = Val


<s> SDValue <ISA_LIT>TargetLowering :: LowerCTTZ ( SDValue Op , SelectionDAG & DAG ) const { EVT VT = Op . getValueType ( ) ; assert ( VT . isScalableVector ( ) || useSVEForFixedLengthVectorVT ( VT , Subtarget -> useSVEForFixedLengthVectors ( ) ) ) ; SDLoc DL ( Op ) ; SDValue RBIT = DAG . getNode ( <STR_LIT> , DL , VT , Op . getOperand ( <NUM_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , DL , VT


<s> static DecodeStatus DecodeVLDST3Instruction ( MCInst & Inst , unsigned Insn , uint64_t Address , const MCDisassembler * Decoder ) { unsigned size = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; if ( size == <NUM_LIT> ) return MCDisassembler :: Fail ; unsigned align = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; if ( align & <NUM_LIT> ) return


<s> if ( Subtarget . is64Bit ( ) && SrcVT == <STR_LIT> && DstVT == <STR_LIT> ) return SDValue ( ) ; SDValue StackSlot = DAG . CreateStackTemporary ( <STR_LIT> ) ; if ( SrcVT == <STR_LIT> ) { SDValue OffsetSlot = DAG . getMemBasePlusOffset ( StackSlot , <NUM_LIT> , dl ) ; SDValue Store1 = DAG . getStore ( Chain , dl , Src , StackSlot , MachinePointerInfo ( ) ) ; SDValue Store2 = DAG . getStore ( Store1 , dl , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) , OffsetSlot , MachinePointerInfo ( ) ) ; std :: pair < SDValue , SDValue > Tmp = BuildFILD ( Op , <STR_LIT> , Store2 , StackSlot , DAG ) ; if ( IsStrict ) return DAG . getMergeValues ( { Tmp . first , Tmp . second } , dl ) ; return Tmp . first ; } assert ( SrcVT == <STR_LIT> && <STR_LIT> ) ; SDValue ValueToStore = Src ; if ( isScalarFPTypeInSSEReg ( Op . getValueType ( ) ) && ! Subtarget . is64Bit ( ) ) { ValueToStore = DAG . getBitcast ( <STR_LIT> , ValueToStore ) ; } SDValue Store = DAG . getStore ( Chain , dl , ValueToStore , StackSlot , MachinePointerInfo ( ) ) ; int SSFI = cast < FrameIndexSDNode > ( StackSlot ) -> getIndex ( ) ; MachineMemOperand * MMO = DAG . getMachineFunction ( ) . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( DAG . getMachineFunction ( ) , SSFI ) , MachineMemOperand :: MOLoad , <NUM_LIT> , <NUM_LIT> ) ; SDVTList Tys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SDValue Ops [ ] = { Store , StackSlot } ; SDValue Fild = DAG . getMemIntrinsicNode ( <STR_LIT> , dl , Tys , Ops , <STR_LIT> , MMO ) ; Chain = Fild . getValue ( <NUM_LIT> ) ; APInt FF ( <NUM_LIT> , <NUM_LIT> ) ; SDValue SignSet = DAG . getSetCC ( dl , getSetCCResultType ( DAG . getDataLayout ( ) , * DAG . getContext ( ) , <STR_LIT> ) , Op . getOperand ( OpNo ) , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) , <STR_LIT> ) ; SDValue FudgePtr = DAG . getConstantPool ( ConstantInt :: get ( * DAG . getContext ( ) , FF . zext ( <NUM_LIT> ) ) , PtrVT ) ; SDValue Zero = DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ; SDValue Four = DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ; SDValue Offset = DAG . getSelect ( dl , Zero . getValueType ( ) , SignSet , Zero , Four ) ; FudgePtr = DAG . getNode ( <STR_LIT> , dl , PtrVT , FudgePtr , Offset ) ; SDValue Fudge = DAG . getExtLoad ( <STR_LIT> , dl , <STR_LIT> , Chain , FudgePtr , MachinePointerInfo :: getConstantPool

( DAG . getMachineFunction ( ) ) , <STR_LIT> , <NUM_LIT> ) ;


<s> switch ( MI . getOpcode ( ) ) { default : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <ISA_LIT>FrameOffsetCannotUpdate ; } TypeSize ScaleValue ( <NUM_LIT> , false ) ; unsigned Width ; int64_t MinOff , MaxOff ; if ( ! <ISA_LIT>InstrInfo :: getMemOpInfo ( MI . getOpcode ( ) , ScaleValue , Width , MinOff , MaxOff ) ) llvm_unreachable ( <STR_LIT> ) ; bool IsMulVL = ScaleValue . isScalable ( ) ; unsigned Scale = ScaleValue . getKnownMinSize ( ) ; int64_t Offset = IsMulVL ? SOffset . getScalableBytes ( ) : SOffset . getBytes ( ) ; const MachineOperand & ImmOpnd = MI . getOperand ( <ISA_LIT>InstrInfo :: getLoadStoreImmIdx ( MI . getOpcode ( ) ) ) ; Offset += ImmOpnd . getImm ( ) * Scale ; Optional < unsigned > UnscaledOp = <ISA_LIT>InstrInfo :: getUnscaledLdSt ( MI . getOpcode ( ) ) ; bool useUnscaledOp = UnscaledOp && ( Offset % Scale || Offset < <NUM_LIT> ) ; if ( useUnscaledOp && ! <ISA_LIT>InstrInfo :: getMemOpInfo ( * UnscaledOp , ScaleValue , Width , MinOff , MaxOff ) ) llvm_unreachable ( <STR_LIT> ) ; Scale = ScaleValue . getKnownMinSize ( ) ; assert ( IsMulVL == ScaleValue . isScalable ( ) && <STR_LIT> ) ; int64_t Remainder = Offset % Scale ; assert ( ! ( Remainder && useUnscaledOp ) && <STR_LIT> ) ; assert ( MinOff < MaxOff && <STR_LIT> ) ; int64_t NewOffset = Offset / Scale ; if ( MinOff <= NewOffset && NewOffset <= MaxOff ) Offset = Remainder ; else { NewOffset = NewOffset < <NUM_LIT> ? MinOff : MaxOff ; Offset = Offset - NewOffset * Scale + Remainder ; } if ( EmittableOffset ) *


<s> ( AFI -> isThumb1OnlyFunction ( ) ? <STR_LIT> : <STR_LIT> ) ; MachineBasicBlock :: iterator Ins = MBB -> begin ( ) ; DebugLoc DL ; if ( Ins != MBB -> end ( ) ) DL = Ins -> getDebugLoc ( ) ; const MachineFunction & MF = * MBB -> getParent ( ) ; MachineRegisterInfo & MRI = MBB -> getParent (


<s> SDLoc dl ( Op ) ; SDValue TargetCC ; SDValue Cmp = get<ISA_LIT>Cmp ( LHS , RHS , CC , TargetCC , DAG , dl ) ; SDVTList VTs = DAG . getVTList ( Op . getValueType ( ) , <STR_LIT> ) ; SDValue Ops [ ] = { TrueV , FalseV , TargetCC , Cmp } ; return DAG . getNode ( <STR_LIT> , dl , VTs ,


<s> if ( align & <NUM_LIT> ) return MCDisassembler :: Fail ; unsigned load = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; return load ? DecodeVLDInstruction ( Inst , Insn , Address , Decoder ) : DecodeVSTInstruction ( Inst , Insn ,


<s> } if ( GEP -> getNumOperands ( ) != <NUM_LIT> ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << <STR_LIT> ) ; return nullptr ; } Offsets = GEP -> getOperand ( <NUM_LIT> ) ; assert ( cast < FixedVectorType > ( Ty ) -> getNumElements ( ) == cast < FixedVectorType > ( Offsets -> getType ( ) ) -> getNumElements ( ) ) ; if ( Offsets -> getType ( ) -> getScalarSizeInBits ( ) != <NUM_LIT> ) return nullptr ; if ( ZExtInst * ZextOffs = dyn_cast < ZExtInst > ( Offsets ) ) Offsets = ZextOffs -> getOperand ( <NUM_LIT> ) ; else if ( ! ( cast < FixedVectorType > ( Offsets -> getType ( ) ) -> getNumElements ( ) == <NUM_LIT> && Offsets -> getType ( ) -> getScalarSizeInBits ( ) == <NUM_LIT> ) ) return nullptr ; if ( Ty != Offsets -> getType (


<s> fprintf ( file , <STR_LIT> , reg_names [ REGNO ( addr . reg ) ] ) ; return ; case ADDRESS_CONST_INT : output_addr_const ( file , x ) ; fprintf ( file , <STR_LIT> , reg_names [ <NUM_LIT> ] ) ; return ; case


<s> return cfun -> calls_alloca || crtl ->


<s> setAttributeItems ( Attribute , IntValue , StringValue ,


<s> static nodes_iterator nodes_end ( const SpillCostAnalysisGraph & G ) { return G . getNodes (


<s> MCB . addOperand ( MCOperand :: createImm ( BundleFlags ) ) ; MCB . setLoc ( Loc ) ; for ( <ISA_LIT>Shuffler :: iterator I = begin ( ) ; I != end ( ) ; ++ I ) { MCInst const & MI = I -> getDesc ( ) ; MCInst const * Extender = I -> getExtender ( ) ; if ( Extender ) MCB . addOperand ( MCOperand :: createInst ( Extender ) ) ; MCB . addOperand ( MCOperand :: createInst ( & MI )


<s> unsigned SubRegIndex ; if ( RegSpc == EvenDblSpc ) { SubRegIndex = <STR_LIT> ; } else { assert ( RegSpc == OddDblSpc && <STR_LIT> ) ; SubRegIndex = <STR_LIT> ; } unsigned SubReg = TRI -> getSubReg ( DstReg , SubRegIndex ) ; unsigned DstRegPair = TRI -> getMatchingSuperReg ( SubReg , <STR_LIT> , & <STR_LIT> ) ; MIB . addReg ( DstRegPair , RegState :: Define | getDeadRegState ( DstIsDead ) ) ; } else { unsigned D0 , D1 , D2 , D3 ; GetDSubRegs ( DstReg , RegSpc , TRI , D0 , D1 , D2 , D3 ) ; MIB . addReg ( D0 , RegState :: Define | getDeadRegState ( DstIsDead ) ) ; if ( NumRegs > <NUM_LIT> && TableEntry -> copyAllListRegs ) MIB . addReg ( D1 , RegState :: Define | getDeadRegState ( DstIsDead ) ) ; if ( NumRegs > <NUM_LIT> && TableEntry -> copyAllListRegs ) MIB . addReg ( D2 , RegState :: Define | getDeadRegState ( DstIsDead ) ) ; if ( NumRegs > <NUM_LIT> && TableEntry -> copyAllListRegs ) MIB . addReg ( D3 , RegState :: Define | getDeadRegState ( DstIsDead ) ) ; } if ( TableEntry -> isUpdating ) MIB . add ( MI . getOperand ( OpIdx ++ ) ) ; MIB . add ( MI . getOperand ( OpIdx ++ ) ) ; MIB . add ( MI . getOperand ( OpIdx ++ ) ) ; if ( TableEntry


<s> OutStreamer . EmitValueToAlignment ( <NUM_LIT> ) ; MCSymbol * Symbol1 = OutContext . GetOrCreateSymbol ( <STR_LIT> + Twine ( CurrentFnSym -> getName ( ) ) ) ; MCSymbol * Symbol2 = OutContext . GetOrCreateSymbol ( StringRef ( <STR_LIT> ) ) ; OutStreamer . EmitValue ( MCSymbolRefExpr :: Create ( Symbol1 , OutContext ) , Subtarget .


<s> while ( ! MI . getOperand ( i ) . isFI ( ) ) { ++ i ; assert ( i < MI . getNumOperands ( ) && <STR_LIT> ) ; } int FrameIndex = MI . getOperand ( i ) . getIndex ( ) ; unsigned BasePtr = ( TFI -> hasFP ( MF ) ? <STR_LIT> : <STR_LIT> ) ; int Offset = MF . getFrameInfo ( ) -> getObjectOffset ( FrameIndex ) ; Offset += <NUM_LIT> ; if ( ! TFI -> hasFP ( MF ) ) Offset += MF . getFrameInfo ( ) -> getStackSize ( ) ; else Offset += <NUM_LIT> ; Offset += MI . getOperand ( i + <NUM_LIT> ) . getImm ( ) ; if ( MI . getOpcode ( ) == <STR_LIT> ) { MI . setDesc ( TII .


<s> inline bool is_st_tnsr ( const MCInstrDesc & MCInstD ) { if ( ! isStoreInst ( MCInstD ) )


<s> TLSModel :: Model Model = getTargetMachine ( ) . getTLSModel ( GA -> getGlobal ( ) ) ; SDValue TPOff ; EVT PtrVT = getPointerTy ( ) ; SDLoc DL ( Op ) ; const GlobalValue * GV = GA -> getGlobal ( ) ; SDValue ThreadBase = DAG . getNode ( <STR_LIT> , DL , PtrVT ) ; if ( Model == TLSModel :: InitialExec ) { TPOff = DAG . getNode ( <STR_LIT> , DL , PtrVT , DAG . getTargetGlobalAddress ( GV , DL , PtrVT , <NUM_LIT> , <STR_LIT> ) , DAG . getTargetGlobalAddress ( GV , DL , PtrVT , <NUM_LIT> , <STR_LIT> ) , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; TPOff = DAG . getNode ( <STR_LIT> , DL , PtrVT , DAG . getEntryNode ( ) , TPOff ) ; } else if ( Model == TLSModel :: LocalExec ) { SDValue HiVar = DAG . getTargetGlobalAddress ( GV , DL , <STR_LIT> , <NUM_LIT> , <STR_LIT> ) ; SDValue LoVar = DAG . getTargetGlobalAddress ( GV , DL , <STR_LIT> , <NUM_LIT> , <STR_LIT> ) ; TPOff = SDValue ( DAG . getMachineNode ( <STR_LIT> , DL , PtrVT , HiVar

, DAG . getTargetConstant ( <NUM_LIT> , <STR_LIT> ) ) , <NUM_LIT> ) ;


<s> unsigned R = getRelaxedOpcodeArith ( Op ) ; if ( R !=


<s> AII = AST -> getInstrInfo ( ) ; MRI = & MF . getRegInfo ( ) ; MDT = & getAnalysis < MachineDominatorTree > ( ) ; bool Changed = false ; for ( auto & MBB : MF ) Changed |= processBasicBlock ( MBB ) ; if ( DUMP_AFTER ( ) ) MF . dump ( ) ; if ( VIEW_AFTER ( ) ) MF . viewCFG ( ) ; return


<s> return __builtin_ia32_comige ( ( __v4sf ) __A , (


<s> setAction ( { G_CONSTANT , S1 } , Legal ) ; setAction ( { G_FADD , S32 } , Legal ) ; setAction ( { G_FCMP , S1 } , Legal ) ; setAction ( { G_FCMP , <NUM_LIT> , S32 } , Legal ) ; setAction ( { G_FCMP , <NUM_LIT> , S64 } , Legal ) ; setAction ( { G_FMUL , S32 } , Legal ) ; setAction ( { G_ZEXT , S64 } , Legal ) ; setAction ( { G_ZEXT , <NUM_LIT> , S32 } , Legal ) ; setAction ( { G_FPTO<ISA_LIT> , S32 } , Legal ) ; setAction ( { G_FPTO<ISA_LIT> , <NUM_LIT> , S32 } , Legal ) ; setAction ( { G_FPTOUI , S32 } , Legal ) ; setAction ( { G_FPTOUI , <NUM_LIT> , S32 } , Legal ) ; for ( LLT PtrTy : AddrSpaces ) { LLT IdxTy = LLT :: scalar ( PtrTy . getSizeInBits ( ) ) ; setAction ( { G_GEP , PtrTy } , Legal ) ; setAction ( { G_GEP , <NUM_LIT> , IdxTy } , Legal ) ; } setAction ( { G_ICMP , S1 } , Legal ) ; setAction ( { G_ICMP , <NUM_LIT> , S32 } , Legal ) ; getActionDefinitionsBuilder ( { G_LOAD , G_STORE } ) . legalIf ( [ = , & ST ] ( const LegalityQuery & Query ) { const LLT & Ty0 = Query . Types [ <NUM_LIT> ] ; switch ( Ty0 . getSizeInBits ( ) ) { case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : return true ; case <NUM_LIT> : return ( ST . getGeneration ( ) >= <ISA_LIT>Subtarget :: SEA_ISLANDS ) ; case <NUM_LIT> : case <NUM_LIT> : default : return false ; } } ) ; setAction ( { G_SELECT , S32 } , Legal ) ; setAction ( { G_SELECT , <NUM_LIT> , S1 } , Legal ) ; setAction ( { G_SHL , S32 } , Legal ) ; setAction ( { G_GEP , S64 } , Legal ) ; for ( unsigned Op : { G_EXTRACT_VECTOR_ELT , G_INSERT_VECTOR_ELT } ) { getActionDefinitionsBuilder ( Op ) . legalIf ( [ = ] ( const LegalityQuery & Query ) { const LLT & VecTy = Query . Types [ <NUM_LIT> ] ; const LLT & IdxTy = Query . Types [ <NUM_LIT> ] ; return VecTy . getSizeInBits ( ) % <NUM_LIT> == <NUM_LIT> && VecTy . getSizeInBits ( ) <= <NUM_LIT> && IdxTy


<s> int VOP3LiteralLimit = ST . hasVOP3Literal ( ) ? <NUM_LIT> : <NUM_LIT> ; if ( isVALU ( MI ) && usesConstantBus ( MRI , * MO , OpInfo ) ) { if ( isVOP3 ( MI ) && isLiteralConstantLike ( * MO , OpInfo ) && ! VOP3LiteralLimit -- ) return false ; SmallDenseSet < RegSubRegPair > SGPRsUsed ; if ( MO -> isReg ( ) ) SGPRsUsed . insert ( RegSubRegPair ( MO -> getReg ( ) , MO -> getSubReg ( ) ) ) ; for ( unsigned i = <NUM_LIT> , e = MI . getNumOperands ( ) ; i != e ; ++ i ) { if ( i == OpIdx ) continue ; const MachineOperand & Op = MI . getOperand ( i ) ; if ( Op . isReg ( ) ) { RegSubRegPair SGPR ( Op . getReg ( ) , Op . getSubReg ( ) ) ; if ( ! SGPRsUsed . count ( SGPR ) && usesConstantBus ( MRI , Op , InstDesc . OpInfo [ i ] ) ) { if ( -- ConstantBusLimit <= <NUM_LIT> ) return false ; SGPRsUsed . insert ( SGPR ) ; } } else if ( InstDesc . OpInfo [ i ] . OperandType == <STR_LIT> ) { if ( -- ConstantBusLimit <= <NUM_LIT> ) return false ; } else if ( isVOP3 ( MI ) && <STR_LIT> ( InstDesc , i ) && isLiteralConstantLike ( Op , InstDesc . OpInfo [ i ] ) ) { if ( ! VOP3LiteralLimit -- ) return false ; if ( -- ConstantBusLimit <=


<s> for ( i = <NUM_LIT> ; ; i ++ ) { unsigned int test = EH_RETURN_DATA_REGNO ( i ) ; if ( test == INVALID_REGNUM ) break ; if ( test == regno ) return true ; } } if ( fixed_regs [ regno ] ) return


<s> if ( ParseReg ( Operands , InstType ) ) return true ; auto & RParen = Lexer . getTok ( ) ; Operands . push_back ( make_unique < <ISA_LIT>Operand > ( <STR_LIT> , RParen . getLoc ( ) , RParen . getEndLoc ( ) , <STR_LIT> { RParen . getString ( ) } ) ) ; if ( Expect ( AsmToken :: RParen , <STR_LIT> ) ) return true ; if ( Lexer . is ( AsmToken :: Integer ) ) { ParseSingleInteger ( false , Operands ) ; }


<s> static unsigned getADDriOpcode ( int64_t Imm ) { return <STR_LIT>


<s> bool <ISA_LIT>TargetLowering :: CanLowerReturn ( CallingConv :: ID CallConv , MachineFunction & MF , bool IsVarArg , const SmallVectorImpl < <STR_LIT> > & Outs , LLVMContext & Context ) const { if ( <STR_LIT> ( CallConv ) ) return true ; SmallVector < CCValAssign , <NUM_LIT> > RVLocs ; CCState CCInfo ( CallConv , IsVarArg , MF , RVLocs


<s> <ISA_LIT>MCInstLower ( MCContext & ctx , Mangler & mang , AsmPrinter & printer ) : Ctx ( ctx ) , Mang ( mang ) , Printer ( printer ) { } void Lower ( const MachineInstr * MI , MCInst & OutMI ) const ; MCSymbol * GetGlobalAddressSymbol ( const MachineOperand & MO ) const ; MCSymbol * GetExternalSymbolSymbol ( const MachineOperand & MO ) const ; MCSymbol * GetJumpTableSymbol ( const MachineOperand &


<s> const std :: vector < MachineBasicBlock * > & JTBBs = JT [ JTI ] . MBBs ; for ( MachineBasicBlock * MBB : JTBBs ) { const MCExpr * Expr = MCSymbolRefExpr :: create ( MBB -> getSymbol ( ) , OutContext ) ; if ( isPositionIndependent ( ) || Subtarget -> isROPI ( ) || Subtarget -> isPIP ( ) ) Expr =

MCBinaryExpr :: createSub ( Expr , MCSymbolRefExpr :: create ( JTISymbol , OutContext ) , OutContext ) ;


<s> static DecodeStatus DecodeSimm19Lsl2 ( MCInst & Inst , unsigned Insn , uint64_t Address


<s> bool is<ISA_LIT>6xx ( ) const { return Is<ISA_LIT>6xx


<s> delete StaticDtorSection ; delete LSDASection ; delete EHFrameSection ; delete DwarfAbbrevSection ; delete DwarfInfoSection ; delete DwarfLineSection ; delete DwarfFrameSection ; delete DwarfPubTypesSection ; delete DwarfDebugInlineSection


<s> if ( EltTy -> isPointerTy ( ) ) { Type * IntTy = DL . getIntPtrType ( EltTy ) ; Type * IntVecTy = VectorType :: get ( IntTy , Op0 -> getType ( ) -> getVectorNumElements ( ) ) ; Op0 = Builder . CreatePtrToInt ( Op0 , IntVecTy ) ; Op1 = Builder . CreatePtrToInt ( Op1 , IntVecTy ) ; SubVecTy = VectorType :: get ( IntTy , NumSubElts ) ; } static <STR_LIT> StoreInts [ <NUM_LIT> ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> } ; Function * VstNFunc = <STR_LIT> ( SI -> getModule ( ) , StoreInts [ Factor - <NUM_LIT> ] , SubVecTy ) ; SmallVector < Value * , <NUM_LIT> > Ops ; Type * Int8Ptr = Builder . getInt8PtrTy ( SI -> getPointerAddressSpace ( ) ) ; Ops . push_back ( Builder . CreateBitCast ( SI -> getPointerOperand ( ) , Int8Ptr ) ) ; for ( unsigned i = <NUM_LIT> ; i < Factor ; i ++ ) Ops . push_back ( Builder . CreateShuffleVector ( Op0 , Op1 , getSequentialMask ( Builder , NumSubElts * i , NumSubElts ) ) ) ; Ops . push_back ( Builder . getInt32 ( SI -> getAlignment ( ) )


<s> MVT VT = Amt . getSimpleValueType ( ) ; if ( ! ( VT == <STR_LIT> || VT == <STR_LIT> || ( Subtarget . hasInt256 ( ) && VT == <STR_LIT> ) ) ) return SDValue ( ) ; if ( <STR_LIT> ( Amt . getNode ( ) ) ) { SmallVector < SDValue , <NUM_LIT> > Elts ; MVT SVT = VT . getVectorElementType ( ) ; unsigned SVTBits = SVT . getSizeInBits ( ) ; APInt One ( SVTBits , <NUM_LIT> ) ; unsigned NumElems = VT . getVectorNumElements ( ) ; for ( unsigned i = <NUM_LIT> ; i != NumElems ; ++ i ) { SDValue Op = Amt -> getOperand ( i ) ; if ( Op -> isUndef ( ) ) { Elts . push_back ( Op ) ; continue ; } ConstantSDNode * ND = cast < ConstantSDNode > ( Op ) ; APInt C ( SVTBits , ND -> getAPIntValue ( ) . getZExtValue ( ) ) ; uint64_t ShAmt = C . getZExtValue ( ) ; if ( ShAmt >= SVTBits ) { Elts . push_back ( DAG . getUNDEF ( SVT ) ) ; continue ; } Elts . push_back ( DAG . getConstant ( One . shl ( ShAmt ) , dl , SVT ) ) ; } return DAG . getBuildVector ( VT , dl , Elts ) ; } if ( VT == <STR_LIT> ) { Amt = DAG . getNode ( <STR_LIT> , dl , VT , Amt , DAG . getConstant ( <NUM_LIT> , dl , VT ) ) ; Amt = DAG . getNode ( <STR_LIT> , dl , VT , Amt , DAG . getConstant ( <NUM_LIT> , dl , VT ) ) ; Amt = DAG . getBitcast


<s> if ( Op1Opc == <STR_LIT> && Op1 . getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> && Op1 . getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> ) { std :: swap ( Op0 , Op1 ) ; std :: swap ( Op0Opc , Op1Opc ) ; std :: swap ( TargetMask , InsertMask ) ; } } unsigned MB , ME ; if ( isRunOfOnes ( InsertMask , MB , ME ) ) { SDValue Tmp1 , Tmp2 ; if ( ( Op1Opc == <STR_LIT> || Op1Opc == <STR_LIT> ) && isInt32Immediate ( Op1 . getOperand ( <NUM_LIT> ) , Value ) ) { Op1 = Op1 . getOperand ( <NUM_LIT> ) ; SH = ( Op1Opc == <STR_LIT> ) ? Value : <NUM_LIT> - Value ; } if ( Op1Opc == <STR_LIT> ) { APInt MKZ , MKO ; CurDAG -> computeKnownBits ( Op1 . getOperand ( <NUM_LIT> ) , MKZ , MKO ) ; bool CanFoldMask = InsertMask == MKO . getZExtValue ( ) ; unsigned SHOpc = Op1 . getOperand ( <NUM_LIT> ) . getOpcode ( ) ; if ( ( SHOpc == <STR_LIT> || SHOpc == <STR_LIT> ) && CanFoldMask && isInt32Immediate ( Op1 .

getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) , Value ) ) {


<s> void printPCD32Mem ( const MCInst * MI , uint64_t Address , unsigned opNum , raw_ostream & O


<s> rtx cfa_relative_mem = gen_frame_mem ( Pmode , cfa_relative_addr ) ; rtx real = gen_rtx_SET ( cfa_relative_mem , reg_note ) ; add_reg_note ( mov , REG_CFA_OFFSET , real ) ; return emit_insn ( mov


<s> CCValAssign & VA = RVLocs [ i ] ; assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; SDValue Arg = OutVals [ realRVLocIdx ] ; switch ( VA . getLocInfo ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case CCValAssign :: Full : if ( Outs [ i ] . ArgVT == <STR_LIT> ) { Arg = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Arg ) ; Arg = DAG . getNode ( <STR_LIT> , DL , VA . getLocVT ( ) , Arg ) ; } break ; case CCValAssign :: BCvt : Arg = DAG . getNode ( <STR_LIT> , DL , VA . getLocVT ( ) , Arg ) ; break ; case CCValAssign :: AExt : case CCValAssign :: ZExt : Arg = DAG . getZExtOrTrunc ( Arg , DL , VA . getLocVT ( ) ) ; break ; case CCValAssign :: AExtUpper : assert ( VA . getValVT ( ) == <STR_LIT> && <STR_LIT> ) ; Arg = DAG . getZExtOrTrunc ( Arg , DL , VA . getLocVT ( ) ) ; Arg = DAG . getNode ( <STR_LIT> , DL , VA . getLocVT ( ) , Arg , DAG . getConstant ( <NUM_LIT> , DL , VA . getLocVT ( ) ) ) ; break ; } if ( RegsUsed . count ( VA . getLocReg ( ) ) ) { SDValue & Bits = std :: find_if ( RetVals . begin ( ) , RetVals . end ( ) , [ = ] ( const std :: pair < unsigned , SDValue > & Elt ) { return Elt . first == VA . getLocReg ( ) ; } ) -> second ; Bits = DAG . getNode ( <STR_LIT> , DL , Bits . getValueType ( ) , Bits , Arg ) ; } else { RetVals . emplace_back ( VA . getLocReg ( ) , Arg ) ; RegsUsed . insert ( VA . getLocReg ( ) ) ; } } SmallVector < SDValue , <NUM_LIT> > RetOps ( <NUM_LIT> , Chain ) ; for ( auto & RetVal : RetVals ) { Chain = DAG . getCopyToReg ( Chain , DL , RetVal . first , RetVal . second , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> )


<s> F -> setComdat ( M . getOrInsertComdat ( Name ) ) ; AttrBuilder B ; B . addAttribute ( llvm :: Attribute :: NoUnwind ) ; B . addAttribute ( llvm :: Attribute :: Naked ) ; F -> addAttributes ( llvm :: AttributeList :: FunctionIndex , B ) ; BasicBlock * Entry = BasicBlock :: Create ( Ctx , <STR_LIT> , F ) ; IRBuilder < > Builder ( Entry


<s> assert ( GV -> hasInitializer ( ) && <STR_LIT> ) ; const Constant * C = GV -> getInitializer ( ) ; assert ( C -> isNullValue ( ) && <STR_LIT> ) ; const TargetData * TD = TM -> getTargetData ( ) ; const Type * Ty = C -> getType ( ) ; unsigned ValSize = TD -> getTypeAllocSize ( Ty ) ; <ISA_LIT>Section * Found = NULL ; for ( unsigned i = <NUM_LIT> ; i < UDATASections_ . size ( ) ; i ++ ) { if ( DataBankSize - UDATASections_ [ i ] -> getSize ( ) >= ValSize ) { Found = UDATASections_ [


<s> return <STR_LIT> ; } if ( GET_CODE ( operands [ <NUM_LIT> ] ) == CONST_INT && ( logval = exact_log2 ( ~ INTVAL ( operands [ <NUM_LIT> ] ) ) ) >= <NUM_LIT> && ( DATA_REG_P ( operands [ <NUM_LIT> ] ) || offsettable_memref_p ( operands [ <NUM_LIT> ] ) ) ) { if ( DATA_REG_P ( operands [ <NUM_LIT> ] ) ) { operands [ <NUM_LIT> ] = GEN_INT ( logval ) ; } else { operands [ <NUM_LIT> ] = adjust_address ( operands [ <NUM_LIT> ] , SImode , <NUM_LIT> - ( logval / <NUM_LIT> ) ) ; operands [ <NUM_LIT> ] = GEN_INT (


<s> const MachineFunction * MF = MO . getParent ( ) -> getParent ( ) -> getParent ( ) ; const <ISA_LIT>Subtarget * Subtarget = & ( MF -> getSubtarget < <ISA_LIT>Subtarget > ( ) ) ; const TargetMachine & TM = Printer . TM ; const MCExpr * Expr = MCSymbolRefExpr :: create ( Symbol , RefKind , Ctx ) ; if ( Subtarget -> isSecurePlt ( ) && TM . isPositionIndependent ( ) && MO . getTargetFlags ( ) == <STR_LIT> ) Expr = MCBinaryExpr :: createAdd ( Expr , MCConstantExpr :: create ( <NUM_LIT> , Ctx ) , Ctx ) ; if ( ! MO . isJTI ( ) && MO . getOffset ( ) ) Expr = MCBinaryExpr :: createAdd ( Expr , MCConstantExpr :: create ( MO . getOffset ( ) , Ctx ) , Ctx ) ; if ( MO . getTargetFlags ( ) & <STR_LIT> ) { const MachineFunction * MF = MO . getParent ( ) -> getParent ( ) -> getParent ( ) ; const MCExpr * PB = MCSymbolRefExpr :: create ( MF -> getPICBaseSymbol ( ) , Ctx ) ; Expr = MCBinaryExpr :: createSub ( Expr , PB , Ctx ) ; } switch ( access ) { case <STR_LIT> : Expr = <ISA_LIT>MCExpr :: createLo ( Expr ,


<s> case SDATA_SYSV : fprintf ( file , <STR_LIT> , start ) ; start = <STR_LIT> ; break ; case SDATA_EABI : fprintf ( file , <STR_LIT> , start ) ; start = <STR_LIT> ; break ; } if ( rs6000_sdata && g_switch_value ) { fprintf ( file , <STR_LIT> , start , g_switch_value ) ; start = <STR_LIT> ; } if ( * start == '\0' ) putc ( '\n' , file ) ; } if ( ! ( rs6000_default_cpu && rs6000_default_cpu [ <NUM_LIT> ] ) && ! global_options_set . x_rs6000_cpu_index ) { fputs ( <STR_LIT> , asm_out_file ) ; if ( ( rs6000_isa_flags & OPTION_MASK_MODULO ) != <NUM_LIT> ) fputs ( <STR_LIT> , asm_out_file ) ; else if ( ( rs6000_isa_flags & OPTION_MASK_DIRECT_MOVE ) != <NUM_LIT> ) fputs ( <STR_LIT> , asm_out_file ) ; else if ( ( rs6000_isa_flags & OPTION_MASK_POPCNTD ) != <NUM_LIT> ) fputs ( <STR_LIT> , asm_out_file ) ; else if ( ( rs6000_isa_flags & OPTION_MASK_CMPB ) != <NUM_LIT> ) fputs ( <STR_LIT> , asm_out_file ) ; else if ( ( rs6000_isa_flags & OPTION_MASK_POPCNTB ) != <NUM_LIT> ) fputs ( <STR_LIT> , asm_out_file ) ; else if ( ( rs6000_isa_flags & OPTION_MASK_MFCRF ) != <NUM_LIT> ) fputs ( <STR_LIT> , asm_out_file ) ; else if ( ( rs6000_isa_flags & OPTION_MASK_POWERPC64 ) != <NUM_LIT> ) fputs ( <STR_LIT> , asm_out_file ) ; else fputs ( <STR_LIT> , asm_out_file


<s> if ( Subtarget -> has<ISA_LIT>64 ( ) && ( Op . getValueType ( ) == <STR_LIT> ) ) return lowerFABS64 ( Op , DAG , Subtarget -> has<ISA_LIT>32r2


<s> SDValue Res ; if ( CP -> isMachineConstantPoolEntry ( ) ) Res = DAG . getTargetConstantPool ( CP -> getMachineCPVal ( ) , PtrVT , CP -> getAlignment ( ) ) ; else Res = DAG . getTargetConstantPool ( CP -> getConstVal ( ) , PtrVT , CP -> getAlignment ( ) ) ; return DAG . getNode ( <STR_LIT> , dl ,


<s> static MCAsmInfo * create<ISA_LIT>MCAsmInfo ( const MCRegisterInfo & MRI , StringRef TT ) { MCAsmInfo * MAI = new <ISA_LIT>MCAsmInfo ( TT ) ; unsigned SP = MRI . getDwarfRegNum ( <STR_LIT> , true ) ; MCCFIInstruction Inst = MCCFIInstruction :: createDefCfa ( <NUM_LIT> , SP , <NUM_LIT> ) ; MAI -> addInitialFrameState ( Inst ) ; return MAI


<s> void addKind ( <STR_LIT> Value ) { AlignBranchKind |= Value


<s> int h8300_hard_regno_mode_ok ( int regno , machine_mode mode ) { if ( TARGET_H8300 ) return ( ( regno & <NUM_LIT> ) == <NUM_LIT> ) || ( mode == HImode ) || ( mode == QImode ) ; else return regno == MAC_REG ? mode ==


<s> PtrValue = IMemI -> getArgOperand ( <NUM_LIT> ) ; } else continue ; } else continue ; unsigned PtrAddrSpace = PtrValue -> getType ( ) -> getPointerAddressSpace ( ) ; if ( PtrAddrSpace ) continue ; if ( ST && ST -> hasAltivec ( ) && PtrValue -> getType ( ) -> getPointerElementType ( ) -> isVectorTy ( ) ) continue ; if ( L -> isLoopInvariant ( PtrValue ) ) continue ; const SCEV * LSCEV = SE -> getSCEVAtScope ( PtrValue , L ) ; if ( const SCEVAddRecExpr * LARSCEV = dyn_cast < SCEVAddRecExpr > ( LSCEV ) ) { if ( LARSCEV -> getLoop ( ) != L ) continue ; } else { continue ; } bool FoundBucket = false ; for ( unsigned i = <NUM_LIT> , e = Buckets . size ( ) ; i != e ; ++ i ) for ( Bucket :: iterator K = Buckets [ i ] . begin ( ) , KE = Buckets [ i ] . end ( ) ; K != KE ; ++ K ) { const SCEV * Diff = SE -> getMinusSCEV ( K -> first , LSCEV ) ; if ( isa < SCEVConstant > ( Diff ) ) { Buckets [ i ] . insert ( std :: make_pair ( LSCEV , MemI ) ) ; FoundBucket = true ; break ; } } if ( ! FoundBucket ) { Buckets . push_back ( Bucket ( SCEVLess ( SE ) ) ) ; Buckets [ Buckets . size ( ) - <NUM_LIT> ] . insert ( std :: make_pair ( LSCEV , MemI ) ) ; } } } if ( Buckets . empty ( ) || Buckets . size ( ) > MaxVars ) return MadeChange ; BasicBlock * LoopPredecessor = L -> getLoopPredecessor ( ) ; if ( ! LoopPredecessor || ! LoopPredecessor -> getTerminator ( ) -> getType ( ) -> isVoidTy ( ) ) { LoopPredecessor = InsertPreheaderForLoop ( L , this ) ; if ( LoopPredecessor ) MadeChange = true ; } if ( ! LoopPredecessor ) return MadeChange ; DEBUG ( dbgs ( ) << <STR_LIT> << Buckets . size ( ) << <STR_LIT> ) ; SmallSet < BasicBlock * , <NUM_LIT> > BBChanged ; for ( unsigned i = <NUM_LIT> , e = Buckets . size ( ) ; i != e ; ++ i ) { const SCEVAddRecExpr * BasePtrSCEV = cast < SCEVAddRecExpr > ( Buckets [ i ] . begin ( ) -> first ) ; if ( ! BasePtrSCEV -> isAffine ( ) ) continue ; DEBUG ( dbgs ( ) << <STR_LIT> << * BasePtrSCEV << <STR_LIT> ) ; assert ( BasePtrSCEV -> getLoop ( ) == L && <STR_LIT> ) ; Instruction * MemI = Buckets [ i ] . begin ( ) -> second ; Value * BasePtr = GetPointerOperand ( MemI ) ; assert ( BasePtr && <STR_LIT> )


<s> void <ISA_LIT>TargetLowering :: emitAtomicCmpXchgNoStoreLLBalance ( IRBuilderBase & Builder ) const { if ( ! Subtarget -> hasV7Ops ( ) ) return ; Module * M = Builder . GetInsertBlock ( ) -> getParent ( ) -> getParent


<s> switch ( Op . getOpcode ( ) ) { case <STR_LIT> : return LowerBR_CC ( Op , DAG ) ; case <STR_LIT> : return LowerGlobalAddress ( Op


<s> explicit <ISA_LIT>AsmPrinter ( formatted_raw_ostream & O , TargetMachine & TM , MCContext & Ctx , MCStreamer & Streamer , const MCAsmInfo * T ) : AsmPrinter ( O , TM , Ctx , Streamer , T ) , AFI ( NULL ) , MCP ( NULL ) { Subtarget = & TM . getSubtarget


<s> static MCInstPrinter * create<ISA_LIT>MCInstPrinter ( const Target & T , unsigned SyntaxVariant , const MCAsmInfo & MAI , const MCInstrInfo & MII , const MCRegisterInfo & MRI , const MCSubtargetInfo & STI ) { if ( SyntaxVariant == <NUM_LIT> ) return ( new <ISA_LIT>InstPrinter ( MAI , MII , MRI ) ) ; else return NULL


<s> size = GET_MODE_SIZE ( GET_MODE ( op ) ) ; if ( size != <NUM_LIT> && size != <NUM_LIT> ) return false ; return ( GET_CODE ( addr ) == inc_code || ( GET_CODE ( addr ) == PLUS && GET_CODE ( XEXP ( addr , <NUM_LIT> ) ) == REG && h8300_displacement_length


<s> DT . recalculate ( F ) ; SSAUpdaterBulk SSA ; for ( BasicBlock & BB : F ) { for ( Instruction & I : BB ) { unsigned VarID = SSA . AddVariable ( I . getName ( ) , I . getType ( ) ) ; if ( auto * II = dyn_cast < InvokeInst > ( & I ) ) SSA . AddAvailableValue ( VarID , II -> getNormalDest ( ) , II ) ; else SSA . AddAvailableValue ( VarID , & BB , & I ) ; for ( auto & U : I . uses ( ) ) { auto * User = cast < Instruction > ( U . getUser ( ) ) ; if ( auto * UserPN = dyn_cast < PHINode > ( User ) ) if ( UserPN -> getIncomingBlock ( U ) == & BB ) continue ; if ( DT . dominates ( &


<s> if ( ! AFI -> hasStackFrame ( ) ) { if ( NumBytes - ArgRegsSaveSize != <NUM_LIT> ) emitSPUpdate ( MBB , MBBI , TII , dl , * RegInfo , NumBytes - ArgRegsSaveSize ) ; } else { if ( MBBI != MBB . begin ( ) ) { do -- MBBI ; while ( MBBI != MBB . begin ( ) && isCSRestore ( * MBBI , CSRegs ) ) ; if ( ! isCSRestore ( * MBBI , CSRegs ) ) ++ MBBI ; } NumBytes -= ( AFI -> getGPRCalleeSavedArea1Size ( ) + AFI -> getGPRCalleeSavedArea2Size ( ) + AFI -> getDPRCalleeSavedAreaSize ( ) + ArgRegsSaveSize ) ; if ( AFI -> shouldRestoreSPFromFP ( ) ) { NumBytes = AFI -> getFramePtrSpillOffset ( ) - NumBytes ; if ( NumBytes ) { assert ( ! MFI . getPristineRegs ( MF ) . test ( <STR_LIT> ) && <STR_LIT> ) ; emitThumbRegPlusImmediate ( MBB , MBBI , dl , <STR_LIT> , FramePtr , - NumBytes , TII , * RegInfo ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . add ( predOps ( <STR_LIT> ) ) ; } else BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( FramePtr ) . add ( predOps ( <STR_LIT> ) ) ; } else


<s> int TailCallReturnAddrDelta = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) -> getTCReturnAddrDelta ( ) ; assert ( ! ( TailCallReturnAddrDelta < <NUM_LIT> ) && <STR_LIT> ) ; } FrameReg = TRI -> getStackRegister ( ) ; int Offset = MFI -> getObjectOffset ( FI ) - getOffsetOfLocalArea (


<s> SDLoc DL ( Op ) ; EVT VT = Op . getValueType ( ) ; if ( VT == <STR_LIT> ) Val = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Val ) ; Val = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Val ) ; SDValue CtPop = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Val ) ; SDValue UaddLV = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getConstant ( <STR_LIT> , DL , <STR_LIT> ) , CtPop ) ; if ( VT == <STR_LIT> ) UaddLV = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , UaddLV ) ; return


<s> } if ( HasStmts && CanReorder ) { MI = MI -> removeFromParent ( ) ; E = CmpInstr ; CmpInstr . getParent ( ) -> insert ( E , MI ) ; } I = CmpInstr ; E = MI ; } const TargetRegisterInfo * TRI = & getRegisterInfo ( ) ; do { const MachineInstr & Instr = * -- I ; if ( isRedundantFlagInstr ( & CmpInstr , SrcReg , SrcReg2 , CmpValue , & Instr ) ) { SubAdd = & * I ; break ; } if ( I == E ) break ; if ( Instr . modifiesRegister ( <STR_LIT> , TRI ) || Instr . readsRegister ( <STR_LIT> , TRI ) ) return false ; } while ( I != B ) ; if ( ! MI && ! SubAdd ) return false ; if ( SubAdd ) { MI = SubAdd ; IsThumb1 = false ; } if ( isPredicated ( * MI ) ) return false ; SmallVector < std :: pair < MachineOperand * , <STR_LIT> > , <NUM_LIT> > OperandsToUpdate ; bool isSafe = false ; I = CmpInstr ; E = CmpInstr . getParent ( ) -> end ( ) ; while ( ! isSafe && ++ I != E ) { const MachineInstr & Instr = * I ; for ( unsigned IO = <NUM_LIT> , EO = Instr . getNumOperands ( ) ; ! isSafe && IO != EO ; ++ IO ) { const MachineOperand & MO = Instr . getOperand ( IO ) ; if ( MO . isRegMask ( ) && MO . clobbersPhysReg ( <STR_LIT> ) ) { isSafe = true ; break ; } if ( ! MO . isReg ( ) || MO . getReg ( ) != <STR_LIT> ) continue ; if ( MO . isDef ( ) ) { isSafe = true ; break ; } <STR_LIT> CC ; bool IsInstrVSel = true ; switch ( Instr . getOpcode ( ) ) { default : IsInstrVSel = false ; CC = ( <STR_LIT> ) Instr . getOperand ( IO - <NUM_LIT> ) . getImm ( ) ; break ; case <STR_LIT> : case <STR_LIT> : CC = <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : CC = <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : CC = <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : CC = <STR_LIT> ; break ; } if ( SubAdd ) { unsigned Opc = SubAdd -> getOpcode ( ) ; bool IsSub = Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ; if ( ! IsSub || ( SrcReg2 != <NUM_LIT> && SubAdd -> getOperand ( <NUM_LIT> ) . getReg (

) == SrcReg2 && SubAdd -> getOperand ( <NUM_LIT> ) . getReg ( ) == SrcReg ) ) {


<s> SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . push_back ( N -> getOperand ( <NUM_LIT> ) ) ; Ops . push_back ( N -> getOperand ( <NUM_LIT> ) ) ; Ops . push_back ( Chain ) ; std :: vector < EVT > ResTys ; ResTys . push_back ( <STR_LIT> ) ; ResTys . push_back ( <STR_LIT> ) ; ResTys . push_back ( <STR_LIT> ) ; SDNode * Ld = CurDAG -> getMachineNode ( Opc , dl , ResTys , Ops ) ; ReplaceUses ( SDValue ( N , NumVecs ) , SDValue ( Ld , <NUM_LIT> ) ) ; SDValue SuperReg = SDValue ( Ld , <NUM_LIT> ) ; if ( NumVecs == <NUM_LIT> ) ReplaceUses ( SDValue ( N , <NUM_LIT> ) , SuperReg ) ; else for ( unsigned i = <NUM_LIT> ; i < NumVecs ; ++ i ) ReplaceUses ( SDValue ( N , i ) , CurDAG -> getTargetExtractSubreg ( SubRegIdx + i , dl , VT , SuperReg ) ) ; ReplaceUses ( SDValue ( N , NumVecs + <NUM_LIT> ) , SDValue ( Ld , <NUM_LIT> ) ) ; return nullptr


<s> return isa < ConstantAggregate > ( V ) || isa < ConstantDataArray > ( V ) || ( isa <

ConstantAggregateZero > ( V ) && ! V -> getType ( ) -> isVectorTy ( ) ) ;


<s> } else if ( ! AVR_HAVE_LPMX ) { return avr_out_lpm_no_lpmx ( insn , xop , plen ) ; } switch ( GET_CODE ( addr ) ) { default : gcc_unreachable ( ) ; case REG : gcc_assert ( REG_Z == REGNO ( addr ) ) ; switch ( n_bytes ) { default : gcc_unreachable ( ) ; case <NUM_LIT> : avr_asm_len ( <STR_LIT> , xop , plen , <NUM_LIT> ) ; break ; case <NUM_LIT> : if ( REGNO ( dest ) == REG_Z ) avr_asm_len ( <STR_LIT> CR_TAB <STR_LIT> CR_TAB <STR_LIT> , xop , plen , <NUM_LIT> ) ; else { avr_asm_len ( <STR_LIT> CR_TAB <STR_LIT> , xop , plen , <NUM_LIT> ) ; if ( ! reg_unused_after ( insn , addr ) ) avr_asm_len ( <STR_LIT> , xop , plen , <NUM_LIT> ) ; } break ; case <NUM_LIT> : avr_asm_len ( <STR_LIT> CR_TAB <STR_LIT> CR_TAB <STR_LIT> , xop , plen , <NUM_LIT> ) ; if ( ! reg_unused_after ( insn , addr ) ) avr_asm_len ( <STR_LIT> , xop , plen , <NUM_LIT> ) ; break ; case <NUM_LIT> : avr_asm_len ( <STR_LIT> CR_TAB <STR_LIT> , xop , plen , <NUM_LIT> ) ; if ( REGNO ( dest ) == REG_Z - <NUM_LIT> ) avr_asm_len ( <STR_LIT> CR_TAB <STR_LIT> CR_TAB <STR_LIT> , xop , plen , <NUM_LIT> ) ; else { avr_asm_len ( <STR_LIT> CR_TAB <STR_LIT> , xop , plen , <NUM_LIT> ) ; if ( ! reg_unused_after ( insn , addr ) ) avr_asm_len ( <STR_LIT> , xop , plen , <NUM_LIT> ) ; } break ; } break ; case POST_INC : gcc_assert ( REG_Z == REGNO ( XEXP ( addr , <NUM_LIT> ) ) && n_bytes <= <NUM_LIT> ) ; avr_asm_len ( <STR_LIT> , xop , plen , <NUM_LIT> ) ; if ( n_bytes >= <NUM_LIT> ) avr_asm_len ( <STR_LIT> , xop , plen , <NUM_LIT> ) ; if ( n_bytes >= <NUM_LIT> ) avr_asm_len ( <STR_LIT> , xop , plen , <NUM_LIT> ) ; if ( n_bytes >= <NUM_LIT> ) avr_asm_len ( <STR_LIT> , xop , plen , <NUM_LIT> ) ; break ; } if ( xop [ <NUM_LIT> ] == xstring_e && AVR_HAVE_RAMPD ) { xop [ <NUM_LIT> ]


<s> for ( unsigned I = <NUM_LIT> , E = Operands . size ( ) ; I != E ; ++ I )


<s> aarch64_add_offset ( Pmode , stack_pointer_rtx , stack_pointer_rtx , - delta , temp1 ,


<s> Operands . push_back ( <STR_LIT> ( RegNo , S , Parser . getTok ( ) . getLoc ( ) ) ) ; Parser . Lex ( )


<s> if ( mode == VNx2DImode && BYTES_BIG_ENDIAN ) continue ; poly_int64 offset = cfun -> machine -> frame . reg_offset [ regno ] ; if ( flag_stack_clash_protection && maybe_ne ( cfun -> machine -> frame . below_hard_fp_saved_regs_size , <NUM_LIT> ) && known_eq ( offset , <NUM_LIT> ) ) continue ; if ( frame_pointer_needed ) offset -= cfun -> machine -> frame . below_hard_fp_saved_regs_size ; else offset += crtl -> outgoing_args_size ; if ( aarch64_sve_mode_p ( mode ) ? offset_9bit_signed_scaled_p ( mode , offset ) : offset_12bit_unsigned_scaled_p ( mode , offset ) ) bitmap_set_bit ( components , regno ) ; } if ( frame_pointer_needed ) bitmap_clear_bit ( components , HARD_FRAME_POINTER_REGNUM ) ; if ( cfun -> machine -> frame . spare_pred_reg != INVALID_REGNUM ) bitmap_clear_bit ( components , cfun -> machine -> frame . spare_pred_reg ) ; unsigned reg1 = cfun -> machine -> frame . wb_candidate1 ; unsigned reg2 = cfun -> machine


<s> union { vec_uchar16 v ; int i [ <NUM_LIT> ] ; } x ; x . i [ <NUM_LIT> ] = <NUM_LIT> << <NUM_LIT> ; if ( b & <NUM_LIT> ) { vec_uint4 nan_mask = ( vec_uint4 ) { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; vec_uint4 a_inf = ( vec_uint4 ) vec_cmpeq ( aabs , nan_mask ) ; if ( b & <NUM_LIT> ) { vec_uint4 a_nan = ( vec_uint4 ) vec_cmpgt ( aabs , nan_mask ) ; a_nan = vec_or ( a_nan , vec_and ( ( vec_uint4 ) vec_slo ( ( vec_uchar16 ) a_nan , x . v ) , a_inf ) ) ; a_nan = ( vec_uint4 ) vec_perm ( ( vec_uchar16 ) a_nan , ( vec_uchar16 ) a_nan , splat_hi ) ; result = vec_or ( result , a_nan ) ; } if ( b & <NUM_LIT> ) { a_inf = vec_and ( ( vec_uint4 ) vec_slo ( ( vec_uchar16 ) a_inf , x . v ) , a_inf ) ; a_inf = ( vec_uint4 ) vec_perm ( ( vec_uchar16 ) a_inf , ( vec_uchar16 ) a_inf , splat_hi ) ; if ( b & <NUM_LIT> ) result = vec_or ( vec_andc ( a_inf , sign ) , result ) ; if ( b & <NUM_LIT> ) result = vec_or ( vec_and ( a_inf , sign ) , result ) ; } } if ( b & <NUM_LIT> ) { vec_uint4 iszero = ( vec_uint4 ) vec_cmpeq ( aabs , ( vec_uint4 ) vec_splat_u32 ( <NUM_LIT> ) ) ; iszero = vec_and ( iszero , ( vec_uint4 ) vec_slo ( ( vec_uchar16 ) iszero , x . v ) ) ; if ( b & <NUM_LIT> ) { vec_uint4 denorm_mask = ( vec_uint4 ) { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; vec_uint4 isdenorm = vec_nor ( ( vec_uint4 ) vec_cmpgt ( aabs , denorm_mask ) , iszero ) ; isdenorm = ( vec_uint4 ) vec_perm ( ( vec_uchar16 ) isdenorm , ( vec_uchar16 ) isdenorm , splat_hi ) ; if ( b & <NUM_LIT> ) result = vec_or ( vec_andc ( isdenorm , sign ) , result ) ; if ( b & <NUM_LIT> ) result = vec_or ( vec_and ( isdenorm , sign ) ,


<s> static unsigned getNumOfConsecutiveZeros ( SDValue Op , SDValue Mask , unsigned NumElems , bool Low , SelectionDAG & DAG ) { unsigned NumZeros = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> ; i < NumElems ; ++ i ) { unsigned Index = Low ? i : NumElems - i - <NUM_LIT> ; SDValue Idx = Mask . getOperand ( Index ) ; if ( Idx . getOpcode ( ) == <STR_LIT> ) { ++ NumZeros ; continue ; } SDValue Elt = DAG . getShuffleScalarElt ( Op . getNode ( ) , Index ) ; if ( Elt . getNode ( ) && isZeroNode ( Elt ) ) ++ NumZeros ; else


<s> return <NUM_LIT> ; } unsigned Opc = Cond [ <NUM_LIT> ] . getImm ( ) ; MachineInstr & CondMI = * BuildMI ( & MBB , DL , get ( Opc ) ) . add ( Cond [ <NUM_LIT> ] ) . add ( Cond [ <NUM_LIT> ] ) . addMBB ( TBB ) ; if ( BytesAdded ) * BytesAdded += getInstSizeInBytes ( CondMI ) ; if ( ! FBB )


<s> static bool DisassembleLdMiscFrm ( MCInst & MI , unsigned Opcode , uint32_t insn

, unsigned short NumOps , unsigned & NumOpsAdded , BO B ) {


<s> unsigned <ISA_LIT>TTIImpl :: getOperandsScalarizationOverhead ( ArrayRef < const Value * > Args , unsigned VF ) { return BaseT :: getOperandsScalarizationOverhead ( Args


<s> if ( UI . getUse ( ) . getResNo ( ) != <NUM_LIT> ) continue ; if ( UI -> getOpcode ( ) != <STR_LIT> ) return false ; if ( cast < RegisterSDNode > ( UI -> getOperand ( <NUM_LIT> ) ) -> getReg ( ) != <STR_LIT> ) return false ; for ( SDNode :: use_iterator FlagUI = UI -> use_begin ( ) , FlagUE = UI -> use_end ( ) ; FlagUI != FlagUE ; ++ FlagUI ) { if ( FlagUI . getUse ( ) . getResNo ( ) != <NUM_LIT> ) continue ; if ( ! FlagUI -> isMachineOpcode ( ) ) return false ; switch ( FlagUI -> getMachineOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case


<s> static unsigned char avr_class_max_nregs ( reg_class_t rclass


<s> return RegIdx . Index >= <NUM_LIT> &&


<s> const RegisterBank & <ISA_LIT>RegisterBankInfo :: getRegBankFromRegClass ( const TargetRegisterClass & RC , LLT ) const { using namespace <ISA_LIT> ; switch ( RC . getID ( ) ) { case GPRRegClassID : case GPRwithAPSRRegClassID : case GPRnoipRegClassID : case GPRnopcRegClassID : case GPRnoip_and_GPRnopcRegClassID : case rGPRRegClassID : case GPRspRegClassID : case GPRnoip_and_tcGPRRegClassID : case tcGPRRegClassID : case tGPRRegClassID


<s> ASM_OUTPUT_LABEL ( asm_out_file , label ) ; } if ( ! TARGET_ZARCH ) fputs ( <STR_LIT> , asm_out_file ) ; if ( REG_P ( execute_target ) ) fprintf ( asm_out_file , <STR_LIT> , REGNO ( execute_target ) ) ; else output_asm_insn ( <STR_LIT> , & execute_target ) ; if ( ! TARGET_ZARCH ) fputs ( <STR_LIT> , asm_out_file ) ; fputs ( <STR_LIT> , asm_out_file )


<s> if ( MO . isImm ( ) ) return isInlineConstant ( APInt ( <NUM_LIT> , MO . getImm ( ) , true ) ) ; if ( MO . isFPImm ( ) ) { APFloat FpImm = MO . getFPImm ( ) -> getValueAPF ( ) ; return isInlineConstant ( FpImm . bitcastToAPInt ( )


<s> auto * ZeroVec = getOpcodeDef ( G_BUILD_VECTOR , I . getOperand ( <NUM_LIT> ) . getReg ( ) , MRI ) ; if ( ! ZeroVec ) return false ; int64_t Zero = <NUM_LIT> ; if ( ! mi_match ( ZeroVec -> getOperand ( <NUM_LIT> ) . getReg ( ) , MRI , m_ICst ( Zero ) ) || Zero ) return false ; for ( unsigned i = <NUM_LIT> , e = ZeroVec -> getNumOperands ( ) - <NUM_LIT> ; i < e ; ++ i ) { if ( ZeroVec -> getOperand ( i ) . getReg ( ) != ZeroVec -> getOperand ( <NUM_LIT> ) . getReg ( ) ) return false ; } LLT VecTy = MRI . getType ( I . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; LLT EltTy = VecTy . getElementType ( ) ; if ( VecTy . getSizeInBits ( ) != <NUM_LIT> || EltTy . getSizeInBits ( ) < <NUM_LIT> ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } bool IsFP = ScalarRB -> getID ( ) == <STR_LIT> ; static const unsigned OpcTable [ <NUM_LIT> ] [ <NUM_LIT> ] = { { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } } ; unsigned Opc = OpcTable [ IsFP ] [ EltTy . getSizeInBits ( ) == <NUM_LIT> ] ; if ( IsFP ) { MachineInstr * Widen = emitScalarToVector ( EltTy . getSizeInBits ( ) , &


<s> bool Changed = ( Kind != Bottom ) ; Kind = Bottom ; Size =


<s> auto Unmerge = B . buildUnmerge ( { S32 , S32 } , Src ) ; auto CvtHi = Signed ? B . build<ISA_LIT>TOFP ( S64 , Unmerge . getReg ( <NUM_LIT> ) ) : B . buildUITOFP ( S64 , Unmerge . getReg ( <NUM_LIT> ) ) ; auto CvtLo = B . buildUITOFP ( S64 , Unmerge . getReg ( <NUM_LIT> ) ) ; auto ThirtyTwo = B . buildConstant (


<s> void AMDGPUInstPrinter :: printAbs ( const MCInst * MI , unsigned OpNo , raw_ostream &


<s> static rtx rl78_subreg ( machine_mode mode , rtx r , machine_mode omode ,


<s> } } } else if ( AllowFloatDomain && Subtarget . hasAVX ( ) ) { Shuffle = <STR_LIT> ; ShuffleVT = <STR_LIT> ( <STR_LIT> , Mask . size ( ) ) ; PermuteImm = <NUM_LIT> ; for ( int i = <NUM_LIT> , e = Mask . size ( ) ; i != e ; ++ i ) { int M = Mask [ i ] ; if ( M == SM_SentinelUndef ) continue ; assert ( ( ( M / <NUM_LIT> ) == ( i / <NUM_LIT> ) ) && <STR_LIT> ) ; PermuteImm |= ( M & <NUM_LIT> ) << i ; } return true ; } } if ( ( MaskScalarSizeInBits == <NUM_LIT> || MaskScalarSizeInBits == <NUM_LIT> ) && ! ContainsZeros && ( AllowIntDomain || Subtarget . hasAVX ( ) ) ) { SmallVector < int , <NUM_LIT> > RepeatedMask ; if ( is128BitLaneRepeatedShuffleMask ( MaskEltVT , Mask , RepeatedMask ) ) { SmallVector < int , <NUM_LIT> > WordMask = RepeatedMask ; if ( MaskScalarSizeInBits == <NUM_LIT> ) narrowShuffleMaskElts ( <NUM_LIT> , RepeatedMask , WordMask ) ; Shuffle = ( AllowIntDomain ? <STR_LIT> : <STR_LIT> ) ; ShuffleVT = ( AllowIntDomain ? <STR_LIT> : <STR_LIT> ) ; ShuffleVT = <STR_LIT> ( ShuffleVT , InputSizeInBits / <NUM_LIT> ) ; PermuteImm = getV4<ISA_LIT>ShuffleImm ( WordMask ) ; return true ; } } if ( ! ContainsZeros && AllowIntDomain && MaskScalarSizeInBits == <NUM_LIT> && ( ( MaskVT . is128BitVector ( ) && Subtarget . hasSSE2 ( ) ) || ( MaskVT . is256BitVector ( ) && Subtarget . hasAVX2 ( ) ) || ( MaskVT . is512BitVector ( ) && Subtarget . hasBWI ( ) ) ) ) { SmallVector < int , <NUM_LIT> > RepeatedMask ; if ( is128BitLaneRepeatedShuffleMask ( MaskEltVT , Mask , RepeatedMask ) ) { ArrayRef < int > LoMask ( RepeatedMask . data ( ) + <NUM_LIT> , <NUM_LIT> ) ; ArrayRef < int > HiMask ( RepeatedMask . data ( ) + <NUM_LIT> , <NUM_LIT> ) ; if ( isUndefOrInRange ( LoMask , <NUM_LIT> , <NUM_LIT> ) && isSequentialOrUndefInRange ( HiMask , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> ) ) { Shuffle = <STR_LIT> ; ShuffleVT = <STR_LIT> ( <STR_LIT> , InputSizeInBits / <NUM_LIT> ) ; PermuteImm = getV4<ISA_LIT>ShuffleImm ( LoMask ) ; return true ; } if ( isUndefOrInRange ( HiMask , <NUM_LIT> , <NUM_LIT> ) && isSequentialOrUndefInRange ( LoMask , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> ) ) { int OffsetHiMask [ <NUM_LIT> ] ; for ( int i = <NUM_LIT> ; i != <NUM_LIT> ; ++ i ) OffsetHiMask [ i ] = ( HiMask [ i ] < <NUM_LIT> ? HiMask [ i ] : HiMask [ i ] - <NUM_LIT> ) ; Shuffle = <STR_LIT> ; ShuffleVT = <STR_LIT> ( <STR_LIT> , InputSizeInBits / <NUM_LIT> ) ; PermuteImm = getV4<ISA_LIT>ShuffleImm ( OffsetHiMask ) ; return true ; } } } if ( AllowIntDomain && ( ( MaskVT . is128BitVector ( ) && Subtarget . hasSSE2 ( ) ) || ( MaskVT . is256BitVector ( )

&& Subtarget . hasAVX2 ( ) ) || ( MaskVT . is512BitVector ( ) && Subtarget . hasAVX512 ( ) ) ) ) {