<s> else { LL = IsN64 ? <STR_LIT> : <STR_LIT> ; SC = IsN64 ? <STR_LIT> : <STR_LIT> ; ZERO = <STR_LIT> ; BNE = <STR_LIT> ; BEQ = <STR_LIT> ; } unsigned Dest = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Ptr = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned OldVal = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned NewVal = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Success = RegInfo . createVirtualRegister ( RC ) ; const BasicBlock * LLVM_BB = BB -> getBasicBlock ( ) ; MachineBasicBlock * loop1MBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * loop2MBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * exitMBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineFunction :: iterator It = BB ; ++ It ; MF -> insert ( It , loop1MBB ) ; MF -> insert ( It , loop2MBB ) ; MF -> insert ( It , exitMBB ) ; exitMBB -> splice ( exitMBB -> begin ( ) , BB , llvm :: next ( MachineBasicBlock :: iterator ( MI ) ) , BB -> end ( ) ) ; exitMBB -> transferSuccessorsAndUpdatePHIs ( BB ) ; BB -> addSuccessor ( loop1MBB ) ; loop1MBB -> addSuccessor ( exitMBB ) ; loop1MBB -> addSuccessor ( loop2MBB ) ; loop2MBB -> addSuccessor ( loop1MBB ) ; loop2MBB -> addSuccessor ( exitMBB ) ; BB = loop1MBB ; BuildMI ( BB , dl , TII -> get ( LL ) , Dest ) . addReg ( Ptr ) . addImm


<s> if ( Register :: isPhysicalRegister ( DstReg ) ) return true ; const TargetRegisterClass * RC = guessRegClass ( DstReg , MRI , TRI , RBI ) ; if ( ! RBI . constrainGenericRegister ( DstReg , * RC , MRI ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << TII . getName ( I . getOpcode ( ) ) << <STR_LIT> ) ; return false ; } return true


<s> bool isImm ( int64_t MinValue , int64_t MaxValue )


<s> const MachineFrameInfo * FrameInfo = MF -> getFrameInfo ( ) ; const <ISA_LIT>RegisterInfo * TRI = static_cast < const <ISA_LIT>RegisterInfo * > ( MF -> getSubtarget < <ISA_LIT>Subtarget > ( ) . getRegisterInfo ( ) ) ; MachineRegisterInfo & MRI = MF -> getRegInfo ( ) ; int64_t Offset = FrameInfo -> getObjectOffset ( FrameIndex ) ; Offset += SubIdx * <NUM_LIT> ; unsigned LaneVGPRIdx = Offset / ( <NUM_LIT> * <NUM_LIT> ) ; unsigned Lane = ( Offset / <NUM_LIT> ) % <NUM_LIT> ; struct SpilledReg Spill ; if ( ! LaneVGPRs . count ( LaneVGPRIdx ) ) { unsigned LaneVGPR = TRI -> findUnusedRegister ( MRI , & <STR_LIT> ) ; LaneVGPRs [ LaneVGPRIdx ] = LaneVGPR ; for ( MachineFunction :: iterator BI = MF -> begin ( ) , BE = MF -> end ( ) ; BI != BE ; ++ BI ) { BI -> addLiveIn ( LaneVGPR ) ; } } Spill . VGPR = LaneVGPRs [ LaneVGPRIdx ] ; Spill . Lane = Lane ; return


<s> EVT AddrVT = StNode -> getBasePtr ( ) . getValueType ( ) ; SDValue HiPtr = DAG . getNode ( <STR_LIT> , DL , AddrVT , StNode -> getBasePtr ( ) , DAG . getConstant ( <NUM_LIT> , DL , AddrVT ) ) ; OutChains [ <NUM_LIT> ] = DAG . getStore ( StNode -> getChain ( ) , DL , SDValue ( Hi64 , <NUM_LIT> ) , HiPtr , MachinePointerInfo ( ) , Alignment , StNode -> isVolatile ( ) ? MachineMemOperand :: MOVolatile : MachineMemOperand :: MONone ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> ,


<s> Current -> replaceLiveOut ( Register , NewRegister ) ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; DEBUG ( Current -> print ( dbgs ( ) , MRI -> getTargetRegisterInfo ( ) ) ) ; Current = Current -> getParent ( ) ; } } for ( MachineRegisterInfo :: reg_iterator I = MRI -> reg_begin ( Register ) , E = MRI -> reg_end ( ) ; I != E ; ) { MachineOperand & O = * I ; ++ I ; if ( O . isDef ( ) ) continue ; bool IsInside = contains ( O . getParent ( ) -> getParent ( ) ) ; bool IsLoopPHI = IsInside && ( O . getParent ( ) -> isPHI ( ) && O . getParent ( ) -> getParent ( ) == getEntry ( ) ) ; bool ShouldReplace = ( IsInside && ReplaceInside ) || ( ! IsInside && ReplaceOutside ) || ( IncludeLoopPHI && IsLoopPHI ) ; if ( ShouldReplace ) { if ( TargetRegisterInfo :: isPhysicalRegister ( NewRegister ) ) { DEBUG ( dbgs ( ) << <STR_LIT> << PrintReg ( NewRegister , MRI -> getTargetRegisterInfo ( ) ) << <STR_LIT> ) ; llvm_unreachable ( <STR_LIT> ) ; } else { DEBUG ( dbgs ( ) << <STR_LIT> << PrintReg ( Register , MRI -> getTargetRegisterInfo ( ) ) << <STR_LIT> << PrintReg


<s> const LDSymbol * getGOTSymbol ( ) const { return m_pGOTSymbol


<s> MCCodeEmitter * llvm :: create<ISA_LIT>MCCodeEmitter ( const MCInstrInfo & MCII , const MCRegisterInfo & MRI , const MCSubtargetInfo & STI , MCContext & Ctx ) { return new <ISA_LIT>MCCodeEmitter ( MCII


<s> while ( InsertPos != MBB -> end ( ) ) { if ( AfterSet . count ( & * InsertPos ) ) { for ( auto Pos = InsertPos , E = MBB -> end ( ) ; Pos != E ; ++ Pos ) assert ( ! BeforeSet . count ( & * Pos ) ) ; break ; } ++ InsertPos


<s> std :: vector < GlobalVariable * > & gvars = localDecls [ f ] ; for ( unsigned i = <NUM_LIT> , e = gvars . size ( )


<s> std :: string <ISA_LIT>Subtarget :: get<ISA_LIT>VersionString ( ) const { switch ( <ISA_LIT>Version ) { default : llvm_unreachable ( <STR_LIT> ) ; case <ISA_LIT>_VERSION_2_0 : return


<s> MachineBasicBlock :: iterator FirstCSPop = MBBI ; while ( MBBI != MBB . begin ( ) ) { MachineBasicBlock :: iterator PI = std :: prev ( MBBI ) ; unsigned Opc = PI -> getOpcode ( ) ; if ( Opc != <STR_LIT> && ! PI -> isTerminator ( ) ) { if ( ( Opc != <STR_LIT> || ! PI -> getFlag ( MachineInstr :: FrameDestroy ) ) && ( Opc != <STR_LIT> || ! PI -> getFlag ( MachineInstr :: FrameDestroy ) ) ) break ; FirstCSPop = PI ; } -- MBBI ; } MBBI = FirstCSPop ; if ( IsFunclet && Terminator -> getOpcode ( ) == <STR_LIT> ) emitCatchRetReturnValue ( MBB , FirstCSPop , & * Terminator ) ; if ( MBBI != MBB . end ( ) ) DL = MBBI -> getDebugLoc ( ) ; if ( NumBytes || MFI . hasVarSizedObjects ( ) ) NumBytes += mergeSPUpdates ( MBB , MBBI , true ) ; if ( ( TRI -> needsStackRealignment ( MF ) || MFI . hasVarSizedObjects ( ) ) && ! IsFunclet ) { if ( TRI -> needsStackRealignment ( MF ) ) MBBI = FirstCSPop ; unsigned SEHFrameOffset = calculateSetFPREG ( SEHStackAllocAmt ) ; uint64_t LEAAmount = IsWin64Prologue ? SEHStackAllocAmt - SEHFrameOffset : - CSSize ; if ( LEAAmount != <NUM_LIT> ) { unsigned Opc = getLEArOpcode ( Uses64BitFramePtr ) ; addRegOffset ( BuildMI ( MBB , MBBI , DL , TII . get ( Opc ) , StackPtr ) , FramePtr , false , LEAAmount ) ; -- MBBI ; } else { unsigned Opc = ( Uses64BitFramePtr ? <STR_LIT> : <STR_LIT> ) ; BuildMI ( MBB , MBBI , DL , TII . get ( Opc ) , StackPtr ) . addReg ( FramePtr ) ; -- MBBI ; } } else if ( NumBytes ) { emitSPUpdate ( MBB , MBBI , DL , NumBytes , true ) ; if ( ! hasFP ( MF ) && NeedsDwarfCFI ) { BuildCFI ( MBB , MBBI , DL , MCCFIInstruction :: createDefCfaOffset ( nullptr , - CSSize - SlotSize ) ) ; } -- MBBI ; } if ( NeedsWin64CFI && MF . hasWinCFI ( ) ) BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) ) ; if ( ! hasFP ( MF ) && NeedsDwarfCFI ) { MBBI = FirstCSPop ; int64_t Offset = - CSSize - SlotSize ; while ( MBBI != MBB .


<s> if ( GET_MODE_SIZE ( mode ) == GET_MODE_SIZE ( ( * p ) -> mode ) ) first_of_size_p = false ; } if ( pool -> first == <NUM_LIT> ) pool -> highest_address = pool -> insn_address - ( UNITS_PER_WORD - <NUM_LIT> ) + <NUM_LIT> ; pool -> highest_address -= GET_MODE_SIZE ( mode ) ; if ( first_of_size_p ) pool -> highest_address -= GET_MODE_SIZE ( mode ) - <NUM_LIT> ; c = XNEW ( struct


<s> static void lm32_setup_incoming_varargs ( cumulative_args_t cum_v , machine_mode mode , tree type , int * pretend_size , int no_rtl ) { CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; int first_anon_arg ; tree fntype ; fntype = TREE_TYPE ( current_function_decl ) ; if ( stdarg_p ( fntype ) ) first_anon_arg = * cum + LM32_FIRST_ARG_REG ; else { int size ; if ( mode == BLKmode ) size = int_size_in_bytes ( type ) ; else size = GET_MODE_SIZE ( mode ) ; first_anon_arg = * cum + LM32_FIRST_ARG_REG + ( ( size + UNITS_PER_WORD - <NUM_LIT> ) / UNITS_PER_WORD ) ; } if ( ( first_anon_arg < ( LM32_FIRST_ARG_REG + LM32_NUM_ARG_REGS ) ) && ! no_rtl ) { int first_reg_offset = first_anon_arg ; int size = LM32_FIRST_ARG_REG + LM32_NUM_ARG_REGS - first_anon_arg ; rtx regblock ; regblock = gen_rtx_MEM ( BLKmode , plus_constant ( Pmode , arg_pointer_rtx , FIRST_PARM_OFFSET ( <NUM_LIT> ) ) ) ; move_block_from_reg ( first_reg_offset , regblock , size ) ; * pretend_size = size *


<s> bool <ISA_LIT>ExpandPseudo :: runOnMachineFunction ( MachineFunction & MF ) { STI = & MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; TII = STI -> getInstrInfo ( ) ; TRI = STI -> getRegisterInfo ( ) ; <ISA_LIT>FI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; <ISA_LIT>FL = STI -> getFrameLowering ( ) ; bool Modified = ExpandPseudosWhichAffectControlFlow ( MF


<s> ImmInstrInfo III ; bool IsVFReg = MI . getOperand ( <NUM_LIT> ) . isReg ( ) ? isVFRegister ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) : false ; bool HasImmForm = instrHasImmForm ( MI . getOpcode ( ) , IsVFReg , III , PostRA ) ; if ( HasImmForm && transformToImmFormFedByAdd ( MI , III , ForwardingOperand , * DefMI , KillFwdDefMI ) ) return true ; if ( HasImmForm && transformToImmFormFedByLI ( MI , III , ForwardingOperand , * DefMI ) ) return true ; if ( ! HasImmForm && simplifyToLI ( MI , * DefMI , ForwardingOperand , KilledDef )


<s> OptimizeSize = MinimizeSize = false ; for ( unsigned i = <NUM_LIT> , e = array_lengthof ( ReduceTable ) ; i != e ; ++ i ) { unsigned FromOpc = ReduceTable [ i ] . WideOpc ; if ( ! ReduceOpcodeMap . insert ( std :: make_pair ( FromOpc , i ) ) . second ) assert ( false


<s> void <ISA_LIT>TargetLowering :: LowerOperationWrapper ( SDNode * N , SmallVectorImpl < SDValue > & Results , SelectionDAG & DAG ) const { if ( isHvxOperation ( N , DAG


<s> return VectorList . Count == <NUM_LIT> && VectorList .


<s> if ( align_words >= GP_ARG_NUM_REG ) return NULL_RTX ; if ( TARGET_32BIT && TARGET_POWERPC64 ) return rs6000_mixed_function_arg ( mode , type , align_words ) ; part_mode = mode ; n_words = rs6000_arg_size ( mode , type ) ; if ( align_words + n_words > GP_ARG_NUM_REG ) part_mode = DImode ; return gen_rtx_REG ( part_mode , GP_ARG_MIN_REG + align_words ) ; } } else if ( abi == ABI_V4 ) { if ( abi_v4_pass_in_fpr ( mode , named ) ) { if ( mode == TDmode && ( cum -> fregno % <NUM_LIT> ) == <NUM_LIT> ) cum -> fregno ++ ; if ( cum -> fregno + ( FLOAT128_2REG_P ( mode ) ? <NUM_LIT> : <NUM_LIT> ) <= FP_ARG_V4_MAX_REG ) return gen_rtx_REG ( mode , cum -> fregno ) ; else return NULL_RTX ; } else { int n_words = rs6000_arg_size ( mode , type ) ; int gregno = cum -> sysv_gregno ; if ( n_words == <NUM_LIT> ) gregno += ( <NUM_LIT> - gregno ) & <NUM_LIT> ; if ( gregno + n_words - <NUM_LIT> > GP_ARG_MAX_REG ) return NULL_RTX ; if ( TARGET_32BIT && TARGET_POWERPC64 ) return rs6000_mixed_function_arg ( mode , type , gregno - GP_ARG_MIN_REG ) ; return gen_rtx_REG ( mode , gregno ) ; } } else { int align_words = rs6000_parm_start ( mode , type , cum -> words ) ; if ( elt_mode == TDmode && ( cum -> fregno % <NUM_LIT> ) == <NUM_LIT> ) cum -> fregno ++ ; if ( USE_FP_FOR_ARG_P ( cum , elt_mode ) && ! ( TARGET_AIX && ! TARGET_ELF && type != NULL && AGGREGATE_TYPE_P ( type ) ) ) { rtx rvec [ GP_ARG_NUM_REG + AGGR_ARG_NUM_REG + <NUM_LIT> ] ; rtx r , off ; int i , k = <NUM_LIT> ; unsigned long n_fpreg = ( GET_MODE_SIZE ( elt_mode ) + <NUM_LIT> ) >> <NUM_LIT> ; int fpr_words ; if ( type && ( cum -> nargs_prototype <= <NUM_LIT> || ( ( DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2 ) && TARGET_XL_COMPAT && align_words >= GP_ARG_NUM_REG ) ) ) k = rs6000_psave_function_arg ( mode , type , align_words , rvec ) ; for ( i = <NUM_LIT> ; i < n_elts && cum -> fregno + i


<s> bool hasVDSPV2 ( ) const { return HasVDSPV2


<s> virtual bool writeNopData ( uint64_t Count , MCObjectWriter * OW ) const { return


<s> obstack_ptr_grow ( & argv_obstack , <STR_LIT> ) ; obstack_ptr_grow ( & argv_obstack , <STR_LIT> ) ; switch ( offload_abi ) { case OFFLOAD_ABI_LP64 : obstack_ptr_grow ( & argv_obstack , <STR_LIT> ) ; break ; case OFFLOAD_ABI_ILP32 : obstack_ptr_grow ( & argv_obstack , <STR_LIT> ) ; break ; default : gcc_unreachable ( ) ; } obstack_ptr_grow ( & argv_obstack , infile ) ; obstack_ptr_grow ( & argv_obstack , <STR_LIT> ) ; obstack_ptr_grow ( & argv_obstack , <STR_LIT> ) ; obstack_ptr_grow ( & argv_obstack , outfile ) ; obstack_ptr_grow ( & argv_obstack , NULL ) ; const char * * new_argv = XOBFINISH ( & argv_obstack , const char * * ) ; fork_execute ( new_argv [ <NUM_LIT> ] , CONST_CAST ( char * * , new_argv ) , true , <STR_LIT> ) ; obstack_free ( & argv_obstack ,


<s> void addMemThumbRIs1Operands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> &&


<s> if ( s390_function_arg_size ( mode , type ) > <NUM_LIT> ) return false ; if ( TARGET_SOFT_FLOAT ) return false ; if ( ! type ) return mode == SFmode || mode == DFmode || mode == SDmode || mode == DDmode ; if ( ! s390_single_field_struct_p ( REAL_TYPE , type , false ) ) return false ; return true


<s> MachineBasicBlock :: iterator K = J -- ; K -> eraseFromParent ( ) ; BlockChanged = true ; ++ NumBLR ; continue ; } } else if ( J -> getOpcode ( ) == <STR_LIT> ) { if ( J -> getOperand ( <NUM_LIT> ) . getMBB ( ) == & ReturnMBB ) { BuildMI ( * * PI , J , J -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addImm ( J -> getOperand ( <NUM_LIT> ) . getImm ( ) ) . addReg ( J -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . copyImplicitOps ( * I ) ; MachineBasicBlock :: iterator K = J -- ; K -> eraseFromParent ( ) ; BlockChanged = true ; ++ NumBCLR ; continue ; } } else if ( J -> getOpcode ( ) == <STR_LIT> || J -> getOpcode ( ) == <STR_LIT> ) { if ( J -> getOperand ( <NUM_LIT> ) . getMBB ( ) == & ReturnMBB ) { BuildMI ( * * PI , J , J -> getDebugLoc ( ) , TII -> get ( J -> getOpcode ( ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> ) ) . addReg ( J -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . copyImplicitOps ( * I ) ; MachineBasicBlock :: iterator K = J -- ; K -> eraseFromParent ( ) ; BlockChanged = true ; ++ NumBCLR ; continue ; } } else if ( J -> isBranch ( ) ) { if ( J -> isIndirectBranch ( ) ) { if ( ReturnMBB . hasAddressTaken ( ) ) OtherReference = true ; } else for ( unsigned i = <NUM_LIT> ; i < J -> getNumOperands ( ) ; ++ i ) if ( J -> getOperand ( i ) . isMBB ( ) && J -> getOperand ( i ) . getMBB ( ) == & ReturnMBB ) OtherReference = true ; } else if ( ! J -> isTerminator ( ) && ! J -> isDebugValue ( ) ) break ; if ( J == ( * PI ) -> begin ( ) ) break ; -- J ; } if ( ( * PI ) -> canFallThrough ( ) && ( * PI ) -> isLayoutSuccessor ( & ReturnMBB ) ) OtherReference = true ; if ( ! OtherReference && BlockChanged ) { PredToRemove . push_back ( * PI ) ; } if ( BlockChanged ) Changed = true ; } for ( unsigned i = <NUM_LIT> , ie = PredToRemove . size ( ) ; i != ie ; ++ i ) PredToRemove [ i ] -> removeSuccessor ( & ReturnMBB , true ) ; if ( Changed && ! ReturnMBB . hasAddressTaken ( ) ) { if ( ReturnMBB . pred_size ( ) ==


<s> tree dims = attr ? TREE_VALUE ( attr ) : NULL_TREE ; fprintf ( asm_out_file , <STR_LIT> , IDENTIFIER_POINTER ( DECL_ASSEMBLER_NAME ( decl ) ) ) ; for ( ; dims ; dims = TREE_CHAIN ( dims ) ) { int size = TREE_INT_CST_LOW ( TREE_VALUE ( dims ) ) ; gcc_assert ( ! TREE_PURPOSE ( dims ) ) ; fprintf ( asm_out_file , <STR_LIT> , size ) ; } fprintf ( asm_out_file , <STR_LIT> ) ; } break ; default : gcc_unreachable ( )


<s> unsigned Polarity = ( Code >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Register = PredicateTable [ RegNo ] ; Inst . addOperand ( MCOperand :: createReg


<s> } unsigned LHS = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; bool isSignedCmp = ( CC == <STR_LIT> || CC == <STR_LIT> || CC == <STR_LIT> || CC == <STR_LIT> ) ; if ( is32BitCmp ) LHS = EmitSubregExt ( MI , BB , LHS , isSignedCmp ) ; if ( isSelectRROp ) { unsigned RHS = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( is32BitCmp ) RHS = EmitSubregExt ( MI , BB , RHS , isSignedCmp ) ; BuildMI ( BB , DL , TII . get ( NewCC ) ) . addReg ( LHS ) . addReg ( RHS ) . addMBB ( Copy1MBB ) ; } else { int64_t imm32 = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; assert ( isInt < <NUM_LIT> > ( imm32 ) ) ; BuildMI ( BB , DL , TII . get ( NewCC ) ) . addReg ( LHS ) . addImm ( imm32 ) . addMBB ( Copy1MBB ) ; } BB = Copy0MBB ; BB -> addSuccessor ( Copy1MBB ) ; BB = Copy1MBB ; BuildMI ( * BB , BB -> begin ( ) , DL , TII . get ( <STR_LIT> ) , MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) . addMBB ( Copy0MBB ) . addReg ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) . addMBB ( ThisMBB ) ; MI . eraseFromParent (


<s> Rv ( StackFixup :: pushI ( j ) ) ; Rv ( StackFixup :: swap ( ) ) ; return ; } if ( i == <NUM_LIT> ) return pattern2_px ( Rv , j , k ) ; XchgPairCorrector CorrectI ( i , <NUM_LIT> ) ; CorrectI ( j ) ( k ) ; if ( k == <NUM_LIT> ) { Rv ( StackFixup :: xchg ( i , <NUM_LIT> ) ) ; Rv ( StackFixup :: pushI ( j ) ) ; Rv ( StackFixup :: swap ( ) ) ; } else { Rv ( StackFixup :: xcpuxc ( i ,


<s> const MachineConstantPoolEntry & MCPE = ( * MCPEs ) [ CPIndex ] ; JTI -> addConstantPoolEntryAddr ( CPI , MCE . getCurrentPCValue ( ) ) ; if ( MCPE . isMachineConstantPoolEntry ( ) ) { <ISA_LIT>ConstantPoolValue * ACPV = static_cast < <ISA_LIT>ConstantPoolValue * > ( MCPE . Val . MachineCPVal ) ; DOUT << <STR_LIT> << CPI << <STR_LIT> << ( void * ) MCE . getCurrentPCValue ( ) << <STR_LIT> << * ACPV << '\n' ; GlobalValue * GV = ACPV -> getGV ( ) ; if ( GV ) { assert ( ! ACPV -> isStub ( ) && <STR_LIT> ) ; if ( ACPV -> isNonLazyPointer ( ) ) MCE . addRelocation ( MachineRelocation :: getIndirectSymbol ( MCE . getCurrentPCOffset ( ) , <STR_LIT> , GV , ( intptr_t ) ACPV , false ) ) ; else emitGlobalAddress ( GV , <STR_LIT> , ACPV -> isStub ( ) || isa < Function > ( GV ) , ( intptr_t ) ACPV ) ; } else { assert ( ! ACPV -> isNonLazyPointer ( ) && <STR_LIT> ) ; emitExternalSymbolAddress ( ACPV -> getSymbol ( ) , <STR_LIT> ) ; } emitWordLE ( <NUM_LIT> ) ; } else { Constant * CV = MCPE . Val . ConstVal ; DOUT << <STR_LIT> << CPI << <STR_LIT> << ( void * ) MCE . getCurrentPCValue (


<s> case FK_SecRel_1 : case FK_Data_1 : return <NUM_LIT> ; case FK_PCRel_2 : case FK_SecRel_2 : case FK_Data_2 : return <NUM_LIT> ; case FK_PCRel_4


<s> size_t ReadCount = getLexer ( ) . peekTokens ( Buf ) ; if ( ReadCount == <NUM_LIT> && Buf [ <NUM_LIT> ] . getKind ( ) == AsmToken :: RParen ) { HadParens = true ; LParen = getParser ( ) . getTok ( ) ; getParser ( ) . Lex ( ) ; } } switch ( getLexer ( ) . getKind ( ) ) { default : if ( HadParens ) getLexer ( ) . UnLex ( LParen ) ; return MatchOperand_NoMatch ; case AsmToken :: Identifier : StringRef Name = getLexer ( ) . getTok ( ) . getIdentifier ( ) ; MCRegister RegNo ; matchRegisterNameHelper ( isRV32E ( ) , RegNo , Name ) ; if ( RegNo == <STR_LIT> ) { if ( HadParens ) getLexer ( ) . UnLex ( LParen ) ; return MatchOperand_NoMatch ; } if ( HadParens ) Operands . push_back ( <ISA_LIT>Operand :: createToken ( <STR_LIT> , FirstS , isRV64 ( ) ) ) ; SMLoc S = getLoc ( ) ; SMLoc E = SMLoc :: getFromPointer ( S . getPointer ( ) - <NUM_LIT> ) ; getLexer ( ) . Lex ( ) ; Operands . push_back ( <ISA_LIT>Operand :: createReg ( RegNo , S , E , isRV64 ( ) ) ) ; } if ( HadParens


<s> unsigned inc = <NUM_LIT> ; switch ( size ) { default : return MCDisassembler :: Fail ; case <NUM_LIT> : if ( fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ) return MCDisassembler :: Fail ; index = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; break ; case <NUM_LIT> : if ( fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ) return MCDisassembler :: Fail ; index = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; if ( fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ) inc = <NUM_LIT> ; break ; case <NUM_LIT> : if ( fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ) return MCDisassembler :: Fail ; index = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; if ( fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ) inc = <NUM_LIT> ; break ; } if ( Rm != <NUM_LIT> ) { if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rn , Address , Decoder ) ) ) return MCDisassembler :: Fail ; } if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rn , Address , Decoder ) ) ) return MCDisassembler :: Fail ; Inst . addOperand ( MCOperand :: CreateImm ( align ) ) ; if ( Rm != <NUM_LIT> ) { if ( Rm != <NUM_LIT> ) { if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rm , Address , Decoder ) ) ) return MCDisassembler :: Fail ; } else Inst . addOperand ( MCOperand


<s> void <ISA_LIT>IntelInstPrinter :: printMemOffset ( const MCInst * MI , unsigned Op , raw_ostream & O ) { const MCOperand & DispSpec = MI -> getOperand ( Op ) ; printOptionalSegReg ( MI , Op + <NUM_LIT> , O ) ; O << '[' ; if ( DispSpec . isImm ( ) ) { O << formatImm ( DispSpec . getImm ( ) ) ; }


<s> return ( ( vec_int4 ) ( si_orx ( ( qword )


<s> if ( Op . isReg ( ) ) { bool isPtrReg = ( MOI . RegClass == <STR_LIT> ) || ( MOI . RegClass == <STR_LIT> ) || ( MOI . RegClass == <STR_LIT> ) ; if ( isPtrReg ) { O << getRegisterName ( Op . getReg ( ) ,


<s> label = gen_label_rtx ( ) ; rtx tmp = gen_rtx_fmt_ee ( UNORDERED , VOIDmode , flag , const0_rtx ) ; tmp = gen_rtx_IF_THEN_ELSE ( VOIDmode , tmp , gen_rtx_LABEL_REF ( VOIDmode , label ) , pc_rtx ) ; emit_jump_insn ( gen_rtx_SET ( pc_rtx , tmp ) ) ; } if ( GET_MODE ( set_dst ) != mode ) { gcc_assert ( mode == CCAmode || mode == CCCmode || mode == CCOmode || mode == CCPmode || mode == CCSmode || mode == CCZmode ) ; set_dst = gen_rtx_REG ( mode , FLAGS_REG


<s> Policy . OnlyTopDown = false ; Policy . OnlyBottomUp = false ; Policy . DisableLatencyHeuristic


<s> if ( GET_CODE ( x ) == PLUS && m32r_rtx_ok_for_base_p ( XEXP ( x , <NUM_LIT> ) , strict ) && m32r_rtx_ok_for_offset_p ( XEXP (


<s> return i < ( int ) VT . getVectorNumElements ( ) ; } ) && <STR_LIT> ) ; if ( unsigned ShuffleOpc = isNEONTwoResultShuffleMask ( ShuffleMask , SubVT , WhichResult , isV_UNDEF ) ) { if ( isV_UNDEF ) SubV2 = SubV1 ; assert ( ( WhichResult == <NUM_LIT> ) && <STR_LIT> ) ; SDValue Res = DAG . getNode ( ShuffleOpc , dl , DAG . getVTList ( SubVT , SubVT ) , SubV1 , SubV2 ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Res . getValue ( <NUM_LIT> ) , Res . getValue ( <NUM_LIT> ) ) ; } } } unsigned NumElts = VT . getVectorNumElements ( ) ; if ( NumElts == <NUM_LIT> ) { unsigned PFIndexes [ <NUM_LIT> ] ; for ( unsigned i = <NUM_LIT> ; i != <NUM_LIT> ; ++ i ) { if ( ShuffleMask [ i ] < <NUM_LIT> ) PFIndexes [ i ] = <NUM_LIT> ; else PFIndexes [ i ] = ShuffleMask [ i ] ; } unsigned PFTableIndex = PFIndexes [ <NUM_LIT> ] * <NUM_LIT> * <NUM_LIT> * <NUM_LIT> + PFIndexes [ <NUM_LIT> ] * <NUM_LIT> * <NUM_LIT> + PFIndexes [ <NUM_LIT> ] * <NUM_LIT> + PFIndexes [ <NUM_LIT> ] ; unsigned PFEntry = PerfectShuffleTable [ PFTableIndex ] ; unsigned Cost = ( PFEntry >> <NUM_LIT> ) ; if ( Cost <= <NUM_LIT> ) return GeneratePerfectShuffle ( PFEntry , V1 , V2 , DAG , dl ) ; } if ( EltSize >= <NUM_LIT> ) { EVT EltVT = EVT :: getFloatingPointVT ( EltSize ) ; EVT VecVT = EVT :: getVectorVT ( * DAG . getContext ( ) , EltVT , NumElts ) ; V1 = DAG . getNode ( <STR_LIT> , dl , VecVT , V1 ) ; V2 = DAG . getNode ( <STR_LIT> , dl , VecVT , V2 ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; for ( unsigned i = <NUM_LIT> ; i < NumElts ; ++ i ) { if ( ShuffleMask [ i ] < <NUM_LIT> ) Ops . push_back ( DAG . getUNDEF ( EltVT ) ) ; else Ops . push_back ( DAG . getNode ( <STR_LIT> , dl , EltVT , ShuffleMask [ i ] < ( int ) NumElts ? V1 : V2 , DAG . getConstant ( ShuffleMask [ i ] & ( NumElts - <NUM_LIT> ) , dl , <STR_LIT> ) ) ) ; } SDValue Val = DAG . getNode ( <STR_LIT> , dl , VecVT , Ops ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Val ) ; } if ( ( VT == <STR_LIT> || VT == <STR_LIT> ) && isReverseMask ( ShuffleMask , VT ) ) return LowerReverse_VECTOR_SHUFFLEv16i8_v8i16 ( Op , DAG ) ; if ( VT == <STR_LIT> ) if ( SDValue NewOp = LowerVECTOR_SHUFFLEv8i8 ( Op , ShuffleMask , DAG ) ) return NewOp ; return SDValue


<s> bool <ISA_LIT>AsmParser :: parseDirectiveArch ( SMLoc L ) { StringRef Arch = getParser ( ) . parseStringToEndOfStatement ( ) . trim ( ) ; unsigned ID = <STR_LIT> ( Arch


<s> } } if ( ! SrcReg ) SrcReg = getRegForValue ( Op0 ) ; if ( ! SrcReg ) return false ; auto * SI = cast < StoreInst > ( I ) ; if ( SI -> isAtomic ( ) ) { AtomicOrdering Ord = SI -> getOrdering ( ) ; if ( isReleaseOrStronger ( Ord ) ) { unsigned AddrReg = getRegForValue ( PtrV ) ; return emitStoreRelease ( VT , SrcReg , AddrReg , createMachineMemOperandFor ( I ) ) ; } } Address Addr ; if ( ! computeAddress ( PtrV , Addr , Op0 -> getType ( ) ) ) return false ; if ( ! emitStore ( VT , SrcReg , Addr , createMachineMemOperandFor ( I ) ) ) return false ; return true


<s> if ( * cum >= <NUM_LIT> ) return <NUM_LIT> ; if ( ft32_pass_by_reference ( cum_v , mode , type , named ) ) size = <NUM_LIT> ; else if ( type ) { if ( AGGREGATE_TYPE_P ( type )


<s> switch ( Expr -> getKind ( ) ) { case MCExpr :: Target : llvm_unreachable ( <STR_LIT> ) ; break ; case MCExpr :: Constant : break ; case MCExpr :: Binary : { const MCBinaryExpr * BE = cast < MCBinaryExpr > ( Expr ) ; fixELFSymbolsInTLSFixupsImpl ( BE -> getLHS ( )


<s> if ( decl == NULL_TREE && ( strcmp ( name , <STR_LIT> ) == <NUM_LIT> || strcmp ( name , <STR_LIT> ) == <NUM_LIT> ) ) flags |= SECTION_RELRO ; if ( strcmp ( name , <STR_LIT> ) == <NUM_LIT> || startswith ( name , <STR_LIT> ) || startswith ( name , <STR_LIT> ) ) flags |= SECTION_BSS ; return flags


<s> else T = DAG . getTargetConstantPool ( CPN -> getConstVal ( ) , ValTy , Align , Offset , TF ) ; assert ( cast < ConstantPoolSDNode > ( T ) -> getTargetFlags ( ) == TF && <STR_LIT> ) ; if ( IsPositionIndependent ) return DAG . getNode ( <STR_LIT>


<s> auto * TRI = static_cast < const <ISA_LIT>RegisterInfo * > ( MRI . getTargetRegisterInfo ( ) ) ; unsigned Dst = IsStore ? Reg : ValueReg ; unsigned Src = IsStore ? ValueReg : Reg ; unsigned Opc = ( IsStore ^ TRI -> isVGPR ( MRI , Reg ) ) ? <STR_LIT> : <STR_LIT> ; auto MIB = BuildMI ( * MBB , MI , MI -> getDebugLoc ( ) , TII -> get ( Opc ) , Dst ) . addReg ( Src , getKillRegState ( IsKill ) ) ; MIB -> setAsmPrinterFlag ( MachineInstr :: ReloadReuse


<s> return ( MO1 . isImm ( ) && MO2 . isImm ( ) ) || ( MO1 . isCPI ( ) && MO2 . isCPI ( ) && MO1 . getIndex ( ) == MO2 . getIndex ( ) ) || ( MO1 . isJTI ( ) && MO2 . isJTI ( ) && MO1 . getIndex ( ) == MO2 . getIndex ( ) ) || ( MO1 . isSymbol ( ) && MO2 . isSymbol ( ) && MO1 . getSymbolName ( ) == MO2 . getSymbolName ( ) ) || ( MO1 . isGlobal ( ) && MO2 . isGlobal ( ) && MO1 . getGlobal ( ) == MO2 . getGlobal ( ) ) || ( MO1 . isBlockAddress ( ) && MO2 . isBlockAddress ( ) && MO1 . getBlockAddress ( ) == MO2 . getBlockAddress ( )

) || ( MO1 . isMCSymbol ( ) && MO2 . isMCSymbol ( ) && MO1 . getMCSymbol ( ) == MO2 . getMCSymbol ( ) ) ;


<s> DEBUG ( dbgs ( ) << <STR_LIT> << * SaveExecInst << '\n' ) ; continue ; } else { DEBUG ( dbgs ( ) << <STR_LIT> << * J << '\n' ) ; break ; } } else if ( ReadsCopyFromExec && ! SaveExecInst ) { DEBUG ( dbgs ( ) << <STR_LIT> << * J << '\n' ) ; break ; } if ( SaveExecInst && J -> readsRegister ( CopyToExec , TRI ) ) { assert ( SaveExecInst != & * J ) ; OtherUseInsts . push_back ( & * J ) ; } } if ( ! SaveExecInst ) continue ; DEBUG ( dbgs ( ) << <STR_LIT> << * SaveExecInst << '\n' ) ; MachineOperand & Src0 = SaveExecInst -> getOperand ( <NUM_LIT> ) ; MachineOperand & Src1 = SaveExecInst -> getOperand ( <NUM_LIT> ) ; MachineOperand * OtherOp = nullptr ; if ( Src0 . isReg ( ) && Src0 . getReg ( ) == CopyFromExec ) { OtherOp = & Src1 ; } else if ( Src1 . isReg ( ) && Src1 . getReg ( ) == CopyFromExec ) { if ( ! SaveExecInst -> isCommutable ( ) ) break ; OtherOp = & Src0 ; } else llvm_unreachable ( <STR_LIT> ) ; CopyFromExecInst -> eraseFromParent ( ) ; auto InsPt = SaveExecInst -> getIterator ( ) ; const DebugLoc & DL = SaveExecInst -> getDebugLoc ( ) ; BuildMI ( MBB , InsPt , DL , TII -> get ( getSaveExecOp ( SaveExecInst -> getOpcode ( ) ) ) , CopyFromExec ) . addReg ( OtherOp -> getReg ( ) ) ; SaveExecInst -> eraseFromParent ( ) ; CopyToExecInst -> eraseFromParent ( ) ; for ( MachineInstr * OtherInst : OtherUseInsts ) { OtherInst -> substituteRegister ( CopyToExec , <STR_LIT> , <STR_LIT> ,


<s> if ( MO . getSubReg ( ) || MO . isDef ( ) || FoundSrcOperand ) return nullptr ; SrcOperandId = i ; FoundSrcOperand = true ; } if ( ! FoundSrcOperand ) return nullptr ; SmallVector < unsigned , <NUM_LIT> > Ops ; Ops . push_back ( SrcOperandId ) ; MachineInstr * FoldMI = foldMemoryOperand ( MI , Ops , DefMI ) ; if ( FoldMI ) { FoldAsLoadDefReg = <NUM_LIT> ; return FoldMI ; } return nullptr


<s> int <ISA_LIT>FrameLowering :: getFrameIndexReference ( const MachineFunction & MF , int FI , unsigned & FrameReg ) const { return resolveFrameIndexReference ( MF , FI , FrameReg


<s> } if ( Ops . size ( ) != <NUM_LIT> ) return false ; unsigned OpNum = Ops [ <NUM_LIT> ] ; unsigned Opc = MI -> getOpcode ( ) ; unsigned NumOps = MI -> getDesc ( ) . getNumOperands ( ) ; bool isTwoAddr = NumOps > <NUM_LIT> && MI -> getDesc ( ) . getOperandConstraint ( <NUM_LIT> , MCOI :: TIED_TO ) != - <NUM_LIT> ; const DenseMap < unsigned , std :: pair < unsigned , unsigned > > * OpcodeTablePtr = nullptr ; if ( isTwoAddr && NumOps >= <NUM_LIT> && OpNum < <NUM_LIT> ) { OpcodeTablePtr = & RegOp2MemOpTable2Addr ; } else if ( OpNum == <NUM_LIT> ) { if ( Opc == <STR_LIT> ) return true ; OpcodeTablePtr = & RegOp2MemOpTable0 ; } else if ( OpNum == <NUM_LIT> ) { OpcodeTablePtr = &


<s> MCSymbol * <ISA_LIT>MCInstLower :: GetBlockAddressSymbol ( const MachineOperand & MO ) const { switch ( MO . getTargetFlags ( )


<s> MCI . addOperand ( MCOperand :: CreateImm ( <NUM_LIT> ) ) ; MCI . addOperand ( MCOperand ::


<s> static void arm_option_save ( struct cl_target_option * ptr , struct gcc_options * opts ) { ptr -> x_arm_arch_string = opts -> x_arm_arch_string ; ptr -> x_arm_cpu_string =


<s> unsigned Bits = Unalign ? Unalign : KnownBits ; if ( Size & ( ( <NUM_LIT> << Bits ) - <NUM_LIT>

) ) Bits = countTrailingZeros ( Size ) ;


<s> if ( I -> isTerminator ( ) ) { if ( ! ( I -> isBranch ( ) ) && ! ( I -> isCall ( ) ) && ! ( I -> isReturn ( ) ) && ! ( I -> isCompare ( ) ) && ! ( I -> getOpcode ( ) == <STR_LIT> || ( I -> getOpcode ( ) > <NUM_LIT> && I -> getOpcode ( ) < <NUM_LIT> ) ) ) { int distinguishResult = distinguishInstr ( I ) ; if ( distinguishResult == - <NUM_LIT> ) { errs ( ) << <STR_LIT> << MF . getName ( ) << <STR_LIT> << I -> getParent ( ) -> getName ( ) << <STR_LIT> << * I << <STR_LIT> ; exit ( <NUM_LIT> ) ; } else { if ( distinguishResult == <NUM_LIT> ) { InstrsM . push_back ( I ) ; } else if ( distinguishResult == <NUM_LIT> ) { InstrsS1 . push_back ( I ) ; } else if ( distinguishResult == <NUM_LIT> ) { InstrsS2 . push_back ( I ) ; } } I ++ ; } emitInstrs_4Interleaving ( MBB , I , InstrsM , InstrsS1 , InstrsS2 ) ; break ; } else if ( std :: next ( I ) == E ) { if ( ! ( I -> isBranch ( ) ) && ! ( I -> isCall ( ) ) && ! ( I -> isReturn ( ) ) && ! ( I -> isCompare ( ) ) && ! ( I -> getOpcode ( ) == <STR_LIT> || ( I -> getOpcode ( ) > <NUM_LIT> && I -> getOpcode ( ) < <NUM_LIT> ) ) ) { int distinguishResult = distinguishInstr ( I ) ; if ( distinguishResult == - <NUM_LIT> ) { errs ( ) << <STR_LIT> << MF . getName ( ) << <STR_LIT> << I -> getParent ( ) -> getName ( ) << <STR_LIT> << * I << <STR_LIT> ; exit ( <NUM_LIT> ) ; } else { if ( distinguishResult == <NUM_LIT> ) { InstrsM . push_back ( I ) ; } else if ( distinguishResult == <NUM_LIT> ) { InstrsS1 . push_back ( I ) ; } else if ( distinguishResult == <NUM_LIT> ) { InstrsS2 . push_back ( I ) ; } } I ++ ; } emitInstrs_4Interleaving ( MBB , I , InstrsM , InstrsS1 , InstrsS2 ) ; break ; } else if ( ( I -> isBranch ( ) && ! ( I -> getOpcode ( ) > <NUM_LIT> && I -> getOpcode ( ) < <NUM_LIT> ) ) ) { emitInstrs_4Interleaving ( MBB , I , InstrsM , InstrsS1 , InstrsS2 ) ; } else if ( I -> getOpcode ( ) == <STR_LIT> || I -> getOpcode ( ) ==


<s> explicit <ISA_LIT>AsmPrinter ( raw_ostream & O , <ISA_LIT>TargetMachine & TM , const TargetAsmInfo * T , CodeGenOpt :: Level OL , bool V ) : AsmPrinter ( O , TM , T , OL , V ) , DbgInfo ( O , T ) { PTLI = TM .


<s> while ( it != ie ) { plt1 = & ( llvm :: cast < <ISA_LIT>PLT1 > ( * it ) ) ; memcpy ( buffer + result , plt1 -> getValue ( ) , <ISA_LIT>PLT1 :: EntrySize ) ; result += <ISA_LIT>PLT1 :: EntrySize ; ++ it ; } return


<s> return true ; } LoadSDNode * LD = dyn_cast < LoadSDNode > ( Op ) ; if ( ! LD || LD -> getExtensionType ( ) != ET || LD -> isVolatile ( ) || LD -> isNonTemporal ( ) ) return false ; if ( LD -> getMemoryVT ( ) != MemVT ) return false ; RLI . Ptr = LD -> getBasePtr ( ) ; if ( LD -> isIndexed ( ) && ! LD -> getOffset ( ) . isUndef ( ) ) { assert ( LD -> getAddressingMode ( ) == <STR_LIT> && <STR_LIT> ) ; RLI . Ptr = DAG . getNode ( <STR_LIT> , dl , RLI . Ptr . getValueType ( ) , RLI . Ptr , LD -> getOffset ( ) ) ; } RLI . Chain = LD -> getChain ( ) ; RLI . MPI = LD -> getPointerInfo (


<s> bool CanImplicitFloat = ! FuncAttributes . hasFnAttribute ( Attribute :: NoImplicitFloat ) ; bool CanUseNEON = Subtarget -> hasNEON ( ) && CanImplicitFloat ; bool CanUseFP = Subtarget -> hasFPARMv8 ( ) && CanImplicitFloat ; bool IsSmallMemset = IsMemset && Size < <NUM_LIT> ; auto AlignmentIsAcceptable = [ & ] ( EVT VT , unsigned AlignCheck ) { if ( memOpAlign ( SrcAlign , DstAlign , AlignCheck ) ) return true ; bool Fast ; return allowsMisalignedMemoryAccesses ( VT , <NUM_LIT> , <NUM_LIT> , & Fast ) && Fast ; } ; if ( CanUseNEON && IsMemset && ! IsSmallMemset && AlignmentIsAcceptable ( <STR_LIT> , <NUM_LIT> ) ) return <STR_LIT> ; if ( CanUseFP && ! IsSmallMemset && AlignmentIsAcceptable ( <STR_LIT> , <NUM_LIT> ) ) return <STR_LIT> ; if ( Size >= <NUM_LIT> && AlignmentIsAcceptable ( <STR_LIT> , <NUM_LIT> ) )


<s> MachineFunction & MF = * MBB . getParent ( ) ; MachineFrameInfo & MFI = * MF . getFrameInfo ( ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( MF , FI ) , MachineMemOperand :: MOLoad , MFI . getObjectSize ( FI ) , MFI . getObjectAlignment ( FI ) ) ; AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm (


<s> if ( N . getOpcode ( ) == <STR_LIT> ) return true ; if ( N . getNumOperands ( ) < <NUM_LIT> || ! isa < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) ) || N . getOpcode ( ) != <STR_LIT> ) return false ; switch ( N . getConstantOperandVal ( <NUM_LIT> ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; } return false


<s> int32_t Val = cast < ConstantSDNode > ( OffsetNode ) -> getSExtValue ( ) ; EVT StoredVT = ST -> getMemoryVT ( ) ; EVT ValueVT = Value . getValueType ( ) ; const <ISA_LIT>InstrInfo & TII = * HST -> getInstrInfo ( ) ; if ( TII . isValidAutoIncImm ( StoredVT , Val ) ) { unsigned Opcode = <NUM_LIT> ; if ( StoredVT == <STR_LIT> ) Opcode = <STR_LIT> ; else if ( StoredVT == <STR_LIT> ) Opcode = <STR_LIT> ; else if ( StoredVT == <STR_LIT> ) Opcode = <STR_LIT> ; else if ( StoredVT == <STR_LIT> ) Opcode = <STR_LIT> ; else llvm_unreachable ( <STR_LIT> ) ; if ( ST -> isTruncatingStore ( ) && ValueVT . getSizeInBits ( ) == <NUM_LIT> ) { assert ( StoredVT . getSizeInBits ( ) < <NUM_LIT> && <STR_LIT> ) ; Value = CurDAG -> getTargetExtractSubreg ( <STR_LIT> , dl , <STR_LIT> , Value ) ; } SDValue Ops [ ] = { Base , CurDAG -> getTargetConstant ( Val , <STR_LIT> ) , Value , Chain } ; SDNode * Result = CurDAG -> getMachineNode ( Opcode , dl , <STR_LIT> , <STR_LIT> , Ops ) ; MachineSDNode :: mmo_iterator MemOp = MF -> allocateMemRefsArray ( <NUM_LIT> ) ; MemOp [ <NUM_LIT> ] = ST -> getMemOperand ( ) ; cast < MachineSDNode > ( Result ) -> setMemRefs ( MemOp , MemOp + <NUM_LIT> ) ; ReplaceUses ( ST , Result


<s> return ; } if ( LLTy . isVector ( ) && PartLLT . isVector ( ) ) { assert ( LLTy . getElementType ( ) == PartLLT . getElementType ( ) ) ; int DstElts = LLTy . getNumElements ( ) ; int PartElts = PartLLT . getNumElements ( ) ; if ( DstElts % PartElts == <NUM_LIT> ) B . buildConcatVectors ( OrigRegs [ <NUM_LIT> ] , Regs ) ; else { assert ( PartElts == <NUM_LIT> && DstElts % <NUM_LIT> != <NUM_LIT> ) ; int RoundedElts = PartElts * ( ( DstElts + PartElts - <NUM_LIT> ) / PartElts ) ; LLT RoundedDestTy = LLT :: vector ( RoundedElts , PartLLT . getElementType ( ) ) ; auto RoundedConcat = B . buildConcatVectors ( RoundedDestTy , Regs ) ; B . buildExtract ( OrigRegs [ <NUM_LIT> ] , RoundedConcat , <NUM_LIT> ) ; } return ; } assert ( LLTy . isVector ( ) && ! PartLLT . isVector ( ) ) ; LLT DstEltTy = LLTy . getElementType ( ) ; if ( DstEltTy == PartLLT ) { B . buildBuildVector ( OrigRegs [ <NUM_LIT> ]


<s> const TargetFrameLowering * getFrameLowering ( ) const { return & FrameLowering


<s> unsigned char TF = IsPositionIndependent ? <STR_LIT> : <NUM_LIT> ; unsigned Offset = <NUM_LIT> ; SDValue T ; if ( CPN -> isMachineConstantPoolEntry ( ) ) T = DAG . getTargetConstantPool ( CPN -> getMachineCPVal ( ) , ValTy , Alignment , Offset , TF ) ; else if ( isVTi1Type ) T = DAG . getTargetConstantPool ( CVal , ValTy , Alignment , Offset , TF ) ; else T = DAG . getTargetConstantPool ( CPN -> getConstVal ( ) , ValTy , Alignment , Offset , TF ) ; assert ( cast < ConstantPoolSDNode > ( T ) -> getTargetFlags ( ) == TF && <STR_LIT> ) ; if ( IsPositionIndependent ) return DAG . getNode ( <STR_LIT> , SDLoc ( Op ) , ValTy , T ) ; return DAG . getNode ( <STR_LIT> , SDLoc ( Op ) , ValTy


<s> TgtMBB -> setAlignment ( MIPS_NACL_BUNDLE_ALIGN ) ; } } else { Pos = LongBrMBB -> begin ( ) ; BuildMI ( * LongBrMBB , Pos , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( - <NUM_LIT> ) ; BuildMI ( * LongBrMBB , Pos , DL , TII -> get ( <STR_LIT> ) ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ; BuildMI ( * LongBrMBB , Pos , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addMBB ( TgtMBB , <STR_LIT> ) . addMBB ( BalTgtMBB ) ; BuildMI ( * LongBrMBB , Pos , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ; MIBundleBuilder ( * LongBrMBB , Pos ) . append ( BuildMI ( * MF , DL , TII -> get ( BalOp ) ) . addMBB ( BalTgtMBB ) ) . append ( BuildMI ( * MF , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addMBB ( TgtMBB , <STR_LIT> ) . addMBB ( BalTgtMBB ) ) ; Pos = BalTgtMBB -> begin ( ) ; BuildMI ( * BalTgtMBB , Pos , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) ; BuildMI ( * BalTgtMBB , Pos , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ; MIBundleBuilder ( * BalTgtMBB , Pos ) . append ( BuildMI ( * MF , DL , TII -> get ( <STR_LIT> ) ) . addReg ( <STR_LIT> ) ) . append ( BuildMI ( * MF , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ) ; } assert ( LongBrMBB -> size ( ) + BalTgtMBB -> size ( ) == LongBranchSeqSize ) ; } else { Pos = LongBrMBB -> begin ( )


<s> unsigned Opcode ; if ( MBBI -> getOpcode ( ) == <STR_LIT> ) Opcode = <STR_LIT> ; else Opcode = <STR_LIT> ; const MCInstrDesc & Desc = TII -> get ( Opcode ) ; assert ( Desc . getNumOperands ( ) == <NUM_LIT> && <STR_LIT> ) ; Register DstReg = MBBI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; bool DstIsDead = MBBI -> getOperand (


<s> BasicBlock * loopBB = BasicBlock :: Create ( Context , <STR_LIT> , & F , newBB ) ; origBB -> getTerminator ( ) -> setSuccessor ( <NUM_LIT> , loopBB ) ; IRBuilder < > builder ( origBB , origBB -> getTerminator ( ) ) ; unsigned dstAS = dyn_cast < PointerType > ( dstAddr -> getType ( ) ) -> getAddressSpace ( ) ; dstAddr = builder . CreateBitCast ( dstAddr , PointerType :: get ( val -> getType ( ) , dstAS ) ) ; IRBuilder < > loop ( loopBB ) ; PHINode * ind = loop . CreatePHI ( len -> getType ( ) , <NUM_LIT> ) ; ind -> addIncoming ( ConstantInt :: get ( len -> getType ( ) , <NUM_LIT> ) , origBB ) ; loop . CreateStore ( val , loop . CreateGEP ( dstAddr , ind ) , false ) ; Value * newind = loop . CreateAdd ( ind , ConstantInt :: get ( len -> getType ( ) , <NUM_LIT> ) ) ; ind -> addIncoming (


<s> while ( it != ie ) { plt1 = & ( llvm :: cast < <ISA_LIT>PLT1 > ( * it ) ) ; memcpy ( buffer + result , plt1 -> getValue ( ) , <ISA_LIT>PLT1 :: EntrySize ) ; result += <ISA_LIT>PLT1 :: EntrySize ; ++


<s> SDValue <ISA_LIT>TargetLowering :: getTargetNode ( ConstantPoolSDNode * N , EVT Ty , SelectionDAG & DAG , unsigned Flag ) const { return DAG . getTargetConstantPool ( N -> getConstVal ( ) , Ty , N -> getAlign ( ) , N -> getOffset


<s> uint32_t <ISA_LIT>MCCodeEmitter :: getAdrLabelOpValue ( const MCInst & MI , unsigned OpIdx , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { const MCOperand & MO = MI . getOperand ( OpIdx ) ; if ( MO . isImm ( ) ) return MO . getImm ( ) ; assert ( MO . isExpr ( ) && <STR_LIT> ) ; const MCExpr * Expr = MO . getExpr ( ) ; MCFixupKind Kind = MI . getOpcode ( ) == <STR_LIT> ? MCFixupKind ( <STR_LIT> ) : MCFixupKind ( <STR_LIT> ) ; Fixups . push_back ( MCFixup :: Create ( <NUM_LIT> , Expr , Kind , MI


<s> const char * getPassName ( ) const override { return


<s> bool shouldMaximizeVectorBandwidth ( ) const { return


<s> unsigned getNumFixupKinds ( ) const override { return <STR_LIT>


<s> MachineBasicBlock * MBB = BA . Addr -> getCode ( ) ; for ( auto SB : MBB -> successors ( ) ) { auto SBA = Func . Addr -> findBlock ( SB , * this ) ; for ( NodeAddr < InstrNode * > IA : SBA . Addr -> members_if ( IsPhi , * this ) ) { for ( auto U : IA . Addr -> members_if ( IsUseForBA , * this ) ) { NodeAddr < PhiUseNode * > PUA = U ; RegisterRef RR = PUA . Addr -> getRegRef ( ) ; linkRefUp < UseNode * > ( IA , PUA , DefM


<s> <ISA_LIT>PipelinerLoopInfo ( MachineInstr * Loop , MachineInstr * EndLoop ) : Loop ( Loop ) , EndLoop ( EndLoop ) , MF ( Loop -> getParent ( ) -> getParent ( ) ) , TII ( MF -> getSubtarget < <ISA_LIT>Subtarget > ( ) . getInstrInfo ( ) ) , DL ( Loop -> getDebugLoc ( ) ) { TripCount = Loop -> getOpcode ( ) == <STR_LIT> ? - <NUM_LIT> : Loop -> getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( TripCount == - <NUM_LIT> ) LoopCount = Loop ->


<s> return CurDAG -> getTargetConstant ( Imm


<s> SDValue <ISA_LIT>TargetLowering :: LowerFRAMEADDR ( SDValue Op , SelectionDAG & DAG ) const { if ( cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) > <NUM_LIT> ) return SDValue ( ) ; MachineFunction & MF = DAG . getMachineFunction ( ) ; const TargetRegisterInfo * RegInfo = getTargetMachine ( ) . getSubtargetImpl ( ) -> getRegisterInfo (


<s> default : LLVM_FALLTHROUGH ; case CallingConv :: <ISA_LIT>_GS : LLVM_FALLTHROUGH ; case CallingConv :: <ISA_LIT>_CS : LLVM_FALLTHROUGH ; case CallingConv :: <ISA_LIT>_VS : RsrcReg = R_028868_SQ_PGM_RESOURCES_VS ; break ; case CallingConv :: <ISA_LIT>_PS : RsrcReg = R_028850_SQ_PGM_RESOURCES_PS ; break ; } } OutStreamer -> emitIntValue ( RsrcReg , <NUM_LIT> ) ; OutStreamer -> emitIntValue ( S_NUM_GPRS ( MaxGPR + <NUM_LIT> ) | S_STACK_<ISA_LIT>ZE ( MFI -> CFStackSize ) , <NUM_LIT> ) ; OutStreamer -> emitIntValue ( R_02880C_DB_SHADER_CONTROL , <NUM_LIT> ) ; OutStreamer -> emitIntValue ( S_02880C_KILL_ENABLE ( killPixel ) , <NUM_LIT> ) ; if ( <STR_LIT> ( MF . getFunction ( ) . getCallingConv ( ) ) ) { OutStreamer -> emitIntValue ( R_0288E8_SQ_LDS_ALLOC , <NUM_LIT> ) ; OutStreamer -> emitIntValue ( alignTo ( MFI -> getLDSSize ( ) , <NUM_LIT> ) >>


<s> bool isCheapToSpeculateCtlz ( ) const override { return true


<s> return <NUM_LIT> - FPDiff ; case <STR_LIT> : return <NUM_LIT> - FPDiff ; case <STR_LIT> : return Subtarget -> is64Bit ( ) ? <NUM_LIT> : <NUM_LIT> ; case <STR_LIT>


<s> return __builtin_mve_vmulhq_uv8hi ( __a ,


<s> pat = gen_calculate_pic_address ( reg , pic_reg , orig ) ; mem = SET_SRC ( pat ) ; gcc_assert ( MEM_P ( mem ) && ! MEM_VOLATILE_P ( mem ) ) ; MEM_READONLY_P ( mem ) = <NUM_LIT> ; MEM_NOTRAP_P ( mem ) = <NUM_LIT> ; return emit_insn ( pat


<s> static bool isPreferredADD ( int64_t ImmOff ) { if ( ( ImmOff & <NUM_LIT>


<s> BTFType . Type = RetType ? BDebug . getTypeId ( RetType ) : <NUM_LIT> ; BTFType . NameOff = <NUM_LIT> ; for ( unsigned I = <NUM_LIT> , N = Elements . size ( ) ; I <


<s> if ( U -> getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> || U -> getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) return SDValue ( ) ; break ; } } if ( N -> getOpcode ( ) != <STR_LIT> && N -> getOpcode ( ) != <STR_LIT> && N -> getOpcode ( ) != <STR_LIT> && N -> getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; if ( N -> getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; SDValue SHL = N -> getOperand ( <NUM_LIT> ) ; auto * C1ShlC2 = dyn_cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ; auto * C2 = dyn_cast < ConstantSDNode > ( SHL . getOperand ( <NUM_LIT> ) ) ; if ( ! C1ShlC2 || ! C2 ) return SDValue ( ) ; DEBUG ( dbgs ( ) << <STR_LIT> ; N -> dump (


<s> EVT OpVT = Op . getOperand ( <NUM_LIT> ) . getValueType ( ) ; if ( OpVT != Op . getOperand ( <NUM_LIT> ) . getValueType ( ) ) return SDValue ( ) ; SDLoc dl ( Op ) ; SDValue OpLHS = Op . getOperand ( <NUM_LIT> ) ; SDValue OpRHS = Op . getOperand ( <NUM_LIT> ) ; assert ( VT . getVectorNumElements ( ) == ( OpVT . getVectorNumElements ( ) * <NUM_LIT> ) && <STR_LIT> ) ; if ( OpVT . getVectorElementType ( ) . isInteger ( ) && OpVT . getVectorElementType ( ) != <STR_LIT> ) { EVT WideVT = OpVT . widenIntegerVectorElementType ( * DAG . getContext ( ) ) ; OpLHS = DAG . getNode ( <STR_LIT> , dl , WideVT , OpLHS ) ; OpRHS = DAG . getNode ( <STR_LIT> , dl , WideVT , OpRHS ) ; } if ( ( OpLHS -> getOpcode ( ) == <STR_LIT> ) && ( OpRHS -> getOpcode ( ) == <STR_LIT> ) && ( OpLHS -> getOperand ( <NUM_LIT> ) == OpRHS -> getOperand ( <NUM_LIT> ) ) ) { APInt ShiftAmount ; if ( DAG . isConstantIntSplat ( OpLHS -> getOperand ( <NUM_LIT> ) , &


<s> if ( ! V1 -> hasOneUse ( ) || ! V2 -> hasOneUse ( ) ) return false ; SDValue LHS = V1 -> getOperand ( <NUM_LIT> ) , RHS = V1 -> getOperand ( <NUM_LIT> ) ; if ( ( V2 -> getOperand ( <NUM_LIT> ) != LHS || V2 -> getOperand ( <NUM_LIT> ) != RHS ) && ( V2 -> getOperand ( <NUM_LIT> ) != RHS || V2 -> getOperand ( <NUM_LIT> ) != LHS ) ) return false ; if ( ! ( isShuffleEquivalent ( V1 , V2 , Mask , { <NUM_LIT> , <NUM_LIT> } ) || isShuffleEquivalent ( V1 , V2 , Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) || isShuffleEquivalent ( V1 , V2 , Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) || isShuffleEquivalent ( V1 , V2 , Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) ) return false ; Opnd0 = LHS ; Opnd1 = RHS ; return true


<s> break ; case E_HImode : if ( cc_meaningful || ( b0 != <NUM_LIT> && b1 != <NUM_LIT> ) ) { sprintf ( insn_buf , <STR_LIT> , opname ) ; output_asm_insn ( insn_buf , operands ) ; } else { if ( b0 != <NUM_LIT> ) { sprintf ( insn_buf , <STR_LIT> , opname ) ; output_asm_insn ( insn_buf , operands ) ; } if ( b1 != <NUM_LIT> ) { sprintf ( insn_buf , <STR_LIT> , opname ) ; output_asm_insn ( insn_buf , operands ) ; } } break ; case E_SImode : lower_half_easy_p = ( b0 == <NUM_LIT> || b1 == <NUM_LIT> || ( code != IOR && w0 == <NUM_LIT> ) ) ; upper_half_easy_p = ( ( code != IOR && w1 == <NUM_LIT> ) || ( code == AND && w1 == <NUM_LIT> ) ) ; if ( cc_meaningful || ( w0 != <NUM_LIT> && w1 != <NUM_LIT> && ! ( lower_half_easy_p && upper_half_easy_p ) && ! ( code == IOR && w1 == <NUM_LIT> && ( w0 & <NUM_LIT> ) != <NUM_LIT> && lower_half_easy_p ) ) ) { sprintf ( insn_buf , <STR_LIT> , opname ) ; output_asm_insn ( insn_buf , operands ) ; } else { if ( w0 == <NUM_LIT> && ( code != IOR ) ) output_asm_insn ( ( code == AND ) ? <STR_LIT> : <STR_LIT> , operands ) ; else if ( ( b0 != <NUM_LIT> ) && ( b1 != <NUM_LIT> ) ) { sprintf ( insn_buf , <STR_LIT> , opname ) ; output_asm_insn ( insn_buf , operands ) ; } else { if ( b0 != <NUM_LIT> ) { sprintf ( insn_buf , <STR_LIT> , opname ) ; output_asm_insn ( insn_buf , operands ) ; } if ( b1 != <NUM_LIT> ) { sprintf ( insn_buf , <STR_LIT> , opname ) ; output_asm_insn ( insn_buf , operands ) ; } } if ( ( w1 == <NUM_LIT> ) && ( code != IOR ) ) output_asm_insn ( ( code == AND ) ? <STR_LIT> : <STR_LIT> , operands ) ; else if ( code == IOR && w1 == <NUM_LIT> && ( w0 & <NUM_LIT> ) != <NUM_LIT> ) { output_asm_insn ( <STR_LIT> , operands ) ; } else if ( code == AND && w1 == <NUM_LIT> ) { output_asm_insn ( <STR_LIT> , operands ) ; } else { if ( w1 != <NUM_LIT> ) { sprintf ( insn_buf , <STR_LIT> , opname ) ; output_asm_insn ( insn_buf , operands ) ; } } } break ; default : gcc_unreachable ( )


<s> explicit <ISA_LIT>FunctionInfo ( MachineFunction & MF ) { ( void )


<s> if ( ! Check ( S , DecodeGPRnopcRegisterClass ( Inst , Rm , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeGPRnopcRegisterClass ( Inst , Rs , Address , Decoder ) ) ) return MCDisassembler :: Fail ; <STR_LIT> Shift = <STR_LIT> ; switch ( type ) { case <NUM_LIT> : Shift = <STR_LIT> ; break ; case <NUM_LIT> : Shift = <STR_LIT> ; break ; case <NUM_LIT> : Shift = <STR_LIT> ; break ; case <NUM_LIT>


<s> if ( cum -> nregs < NUM_ARG_REGS ) * pretend_size = ( NUM_ARG_REGS


<s> case Immediate : OS << * getImm ( ) ; break ; case Register : OS << <STR_LIT> ; OS << getReg ( ) << <STR_LIT> ; break ; case Token : OS << <STR_LIT> << getToken ( ) << <STR_LIT> ; break ; case SystemRegister


<s> bool dumpConstPool ( ) const { return DumpConstPool


<s> void init_cumulative_args ( struct sparc_args * cum , tree fntype , rtx , tree ) { cum -> words = <NUM_LIT> ; cum -> prototype_p = fntype && prototype_p ( fntype ) ; cum -> libcall_p


<s> void <ISA_LIT>PassConfig :: addPreEmitPass2 ( ) { addPass ( create<ISA_LIT>ExpandPseudoPass ( ) , false


<s> SchedCandidate TCand ; TCand . reset ( CandPolicy ( ) ) ; pickNodeFromQueue ( Top , TopPolicy , DAG -> getTopRPTracker ( ) , TCand ) ; assert ( TCand . SU == TopCand . SU && <STR_LIT> ) ; } } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; traceCandidate ( TopCand ) ; dbgs ( ) << <STR_LIT> ; traceCandidate ( BotCand ) ; ) ; SchedCandidate Cand ; if ( TopCand . Reason == BotCand . Reason ) { Cand = BotCand ; GenericSchedulerBase :: CandReason TopReason = TopCand . Reason ; TopCand . Reason = NoCand ; GenericScheduler :: tryCandidate ( Cand , TopCand , nullptr ) ; if ( TopCand . Reason != NoCand ) { Cand . setBest ( TopCand ) ; } else { TopCand . Reason = TopReason ; } } else { if ( TopCand . Reason == RegExcess && TopCand . RPDelta . Excess . getUnitInc ( ) <= <NUM_LIT> ) { Cand = TopCand ; } else if ( BotCand . Reason == RegExcess && BotCand . RPDelta . Excess . getUnitInc ( ) <= <NUM_LIT> ) { Cand = BotCand ; } else if ( TopCand . Reason == RegCritical && TopCand . RPDelta . CriticalMax . getUnitInc ( ) <= <NUM_LIT> ) { Cand = TopCand ; } else if ( BotCand . Reason == RegCritical && BotCand . RPDelta . CriticalMax . getUnitInc ( ) <= <NUM_LIT> ) { Cand = BotCand ; } else { if ( BotCand . Reason > TopCand . Reason ) { Cand = TopCand ; } else { Cand =


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; const MCConstantExpr * MCE = cast < MCConstantExpr > ( getImm ( ) ) ; uint64_t encoding = <STR_LIT> ( MCE ->


<s> UOpc = <STR_LIT> ; Bits = <NUM_LIT> ; Scale = <NUM_LIT> ; break ; case <STR_LIT> : Bits = <NUM_LIT> ; Scale = <NUM_LIT> ; break ; } unsigned MaxOffs = ( ( <NUM_LIT> << ( Bits - <NUM_LIT> ) ) - <NUM_LIT> ) * Scale ; ImmBranches . push_back ( ImmBranch ( I , MaxOffs , isCond , UOpc ) ) ; } if ( Opc == <STR_LIT> || Opc == <STR_LIT> ) PushPopMIs . push_back ( I ) ; if ( Opc == <STR_LIT> ) continue ; for ( unsigned op = <NUM_LIT> , e = I -> getNumOperands ( ) ; op != e ; ++ op ) if ( I -> getOperand ( op ) . isCPI ( ) ) { unsigned Bits = <NUM_LIT> ; unsigned Scale = <NUM_LIT> ; bool NegOk = false ; bool IsSoImm = false ; switch ( Opc ) { default : llvm_unreachable ( <STR_LIT> ) ; break ; case <STR_LIT> : Bits = <NUM_LIT> ; Scale = <NUM_LIT> ; NegOk = true ; IsSoImm = true ; break ; case <STR_LIT> : Bits = <NUM_LIT> ; NegOk = true ; break ; case <STR_LIT> : Bits = <NUM_LIT> ; Scale = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Bits = <NUM_LIT> ; NegOk = true ; break ; case <STR_LIT> : case <STR_LIT> : Bits = <NUM_LIT> ; Scale = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : Bits = <NUM_LIT> ; Scale = <NUM_LIT> ; NegOk = true ; break ; } unsigned CPI = I -> getOperand ( op ) . getIndex ( ) ; MachineInstr * CPEMI = CPEMIs [ CPI ] ; unsigned MaxOffs = ( ( <NUM_LIT> << Bits ) - <NUM_LIT> ) * Scale ; CPUsers . push_back ( CPUser ( I , CPEMI , MaxOffs , NegOk , IsSoImm ) ) ; CPEntry * CPE = findConstPoolEntry ( CPI , CPEMI ) ; assert ( CPE && <STR_LIT> ) ; CPE -> RefCount


<s> AI . PrivateSegmentBuffer = ArgDescriptor :: createRegister ( <STR_LIT> ) ; AI . DispatchPtr = ArgDescriptor :: createRegister ( <STR_LIT> ) ; AI . QueuePtr = ArgDescriptor :: createRegister ( <STR_LIT> ) ; AI . ImplicitArgPtr = ArgDescriptor :: createRegister ( <STR_LIT> ) ; AI . DispatchID = ArgDescriptor :: createRegister ( <STR_LIT> ) ; AI . WorkGroupIDX = ArgDescriptor :: createRegister ( <STR_LIT> ) ; AI . WorkGroupIDY = ArgDescriptor :: createRegister ( <STR_LIT> ) ; AI . WorkGroupIDZ = ArgDescriptor :: createRegister ( <STR_LIT> ) ; const unsigned Mask = <NUM_LIT> ; AI . WorkItemIDX = ArgDescriptor :: createRegister ( <STR_LIT>


<s> const __v8hu shmax = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; __v8hu result ; rshift = vec_splat ( ( __v8hu ) __B , <NUM_LIT> ) ; rshift = vec_splat ( ( __v8hu ) __B , <NUM_LIT> ) ; shmask = rshift <= shmax ; result = vec_vsrh ( ( __v8hu ) __A , rshift ) ; result = vec_sel ( shmask , result , shmask ) ; return ( __m128i ) result


<s> bool <ISA_LIT>TargetLowering :: allowsUnalignedMemoryAccesses ( EVT VT , bool * Fast ) const { if ( Fast ) * Fast

= Subtarget -> isUnalignedMemAccessFast ( ) ;


<s> void MCLDInitialize<ISA_LIT>Emulation ( ) { mcld :: TargetRegistry :: RegisterEmulation ( mcld :: The<ISA_LIT>elTarget , mcld :: emulate<ISA_LIT>LD ) ; mcld :: TargetRegistry :: RegisterEmulation ( mcld :: The<ISA_LIT>64elTarget , mcld ::


<s> static void arm_override_options_after_change


<s> if ( new_opts_set . x_target_flags || new_opts_set . x_s390_arch || new_opts_set . x_s390_tune || new_opts_set . x_s390_stack_guard || new_opts_set . x_s390_stack_size || new_opts_set . x_s390_branch_cost || new_opts_set . x_s390_warn_framesize || new_opts_set . x_s390_warn_dynamicstack_p ) { const unsigned char * src = ( const unsigned char * ) opts_set ; unsigned char * dest = ( unsigned char * ) &


<s> bool isTargetzOS ( ) const { return TargetTriple . isOSzOS (


<s> for ( unsigned i = <NUM_LIT> , e = CSI . size ( ) ; i != e ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; unsigned RegNum = <ISA_LIT>RegisterInfo :: getRegisterNumbering ( Reg ) ; if ( <STR_LIT> -> contains ( Reg ) ) CPUBitmask |= ( <NUM_LIT> << RegNum ) ; else FPUBitmask |= ( <NUM_LIT> << RegNum ) ; } if ( RI . hasFP ( * MF ) ) CPUBitmask |=


<s> bool <ISA_LIT>AsmParser :: parseDirectiveCPU ( SMLoc L ) { StringRef CPU = getParser ( ) . parseStringToEndOfStatement ( ) . trim ( ) ; getTargetStreamer ( ) . emitTextAttribute ( <STR_LIT> , CPU ) ; if ( ! STI . isCPUStringValid ( CPU ) ) { Error ( L , <STR_LIT> ) ; return false ; } STI . InitMCProcessorInfo ( CPU ,


<s> return D ( <STR_LIT> , R ( a ) , MemARPSI ( b


<s> if ( parseToken ( AsmToken :: EndOfStatement , <STR_LIT> ) ) return true ; bool EnableFeature = true ; if ( Name . startswith_lower ( <STR_LIT> ) ) { EnableFeature = false ; Name = Name . substr ( <NUM_LIT> ) ; } MCSubtargetInfo & STI = copySTI ( ) ; FeatureBitset Features = STI . getFeatureBits ( ) ; for ( const auto & Extension : ExtensionMap ) { if ( Extension . Name != Name ) continue ; if ( Extension . Features . none ( ) ) return Error ( ExtLoc , <STR_LIT> + Name ) ; FeatureBitset ToggleFeatures = EnableFeature ? ( ~ Features & Extension . Features ) :


<s> SDNode * <ISA_LIT>DAGToDAGISel :: createQQuadNode ( SDValue V0 , SDValue V1 , SDValue V2 , SDValue V3 ) { SDLoc dl ( V0 . getNode ( ) ) ; SDValue RegClass = CurDAG -> getTargetConstant ( <STR_LIT> , <STR_LIT> ) ; SDValue SubReg0 = CurDAG -> getTargetConstant ( <STR_LIT> , <STR_LIT> ) ; SDValue SubReg1 = CurDAG -> getTargetConstant ( <STR_LIT> , <STR_LIT> ) ; SDValue SubReg2 = CurDAG -> getTargetConstant


<s> if ( ( Mask [ i ] % Size ) / LaneSize != i / LaneSize ) return false ; if ( RepeatedMask [ i % LaneSize ] == - <NUM_LIT> ) RepeatedMask [ i % LaneSize ] = Mask [ i ] < Size ? Mask [ i ] % LaneSize : Mask [ i ] % LaneSize + Size ; else if ( RepeatedMask [ i % LaneSize ] + ( i /

LaneSize ) * LaneSize != Mask [ i ] ) return false ;


<s> if ( TT . isOSBinFormatMachO ( ) ) { OutStreamer -> emitAssemblerFlag ( MCAF_SubsectionsViaSymbols ) ; } emitStackMaps ( SM


<s> const int single_width = mode == DImode ? <NUM_LIT> : <NUM_LIT> ; if ( GET_CODE ( operands [ <NUM_LIT> ] ) == CONST_INT ) { ( mode == DImode ? split_di : split_ti ) ( operands , <NUM_LIT> , low , high ) ; count = INTVAL ( operands [ <NUM_LIT> ] ) & ( single_width * <NUM_LIT> - <NUM_LIT> ) ; if ( count >= single_width ) { emit_move_insn ( low [ <NUM_LIT> ] , high [ <NUM_LIT> ] ) ; ix86_expand_clear ( high [ <NUM_LIT> ] ) ; if ( count > single_width ) emit_insn ( ( mode == DImode ? gen_lshrsi3 : gen_lshrdi3 ) ( low [ <NUM_LIT> ] , low [ <NUM_LIT> ] , GEN_INT ( count - single_width ) ) ) ; } else { if ( ! rtx_equal_p ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ) emit_move_insn ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ; emit_insn ( ( mode == DImode ? gen_x86_shrd_1 : gen_x86_64_shrd ) ( low [ <NUM_LIT> ] , high [ <NUM_LIT> ] , GEN_INT ( count ) ) ) ; emit_insn ( ( mode == DImode ? gen_lshrsi3 : gen_lshrdi3 ) ( high [ <NUM_LIT> ] , high [ <NUM_LIT> ] , GEN_INT ( count ) ) ) ; } } else { if ( ! rtx_equal_p ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ) emit_move_insn ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ; ( mode == DImode ? split_di : split_ti ) ( operands , <NUM_LIT> , low , high ) ; emit_insn ( ( mode == DImode ? gen_x86_shrd_1 : gen_x86_64_shrd ) ( low [ <NUM_LIT> ] , high [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ) ; emit_insn ( ( mode == DImode ? gen_lshrsi3 : gen_lshrdi3 ) ( high [ <NUM_LIT> ] , high [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ) ; if ( TARGET_CMOVE && scratch ) { ix86_expand_clear ( scratch ) ; emit_insn ( ( mode == DImode ? gen_x86_shift_adj_1 : gen_x86_64_shift_adj ) ( low [ <NUM_LIT> ] , high [ <NUM_LIT> ] , operands [ <NUM_LIT> ] , scratch ) ) ; } else emit_insn ( gen_x86_shift_adj_2 ( low [ <NUM_LIT> ] , high [ <NUM_LIT> ]


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; } llvm_unreachable ( <STR_LIT> )


<s> if ( & MO == & MI . getOperand ( OpNo ) ) break ; } const MCInstrDesc & Desc = MCII . get ( MI . getOpcode ( ) ) ; if ( isSrcOperand ( Desc , OpNo ) ) { int RCID = Desc . OpInfo [ OpNo ] . RegClass ; const MCRegisterClass & RC = MRI . getRegClass ( RCID ) ; uint32_t Enc = getLitEncoding ( MO , RC . getSize ( ) ) ; if ( Enc != ~ <NUM_LIT> && ( Enc != <NUM_LIT> || Desc . getSize ( ) == <NUM_LIT> ) ) return Enc ; } else if ( MO . isImm ( ) ) return MO . getImm ( ) ; llvm_unreachable ( <STR_LIT>


<s> static bool pa_print_operand_punct_valid_p ( unsigned char code ) { if ( code == '@' || code == '#' || code ==


<s> adjustJTTargetBlockForward ( MachineBasicBlock * BB , MachineBasicBlock * JTBB ) { MachineBasicBlock * TBB = nullptr , * FBB = nullptr ; SmallVector < MachineOperand , <NUM_LIT> > Cond ; SmallVector < MachineOperand , <NUM_LIT> > CondPrior ; MachineFunction :: iterator BBi = BB -> getIterator ( ) ; MachineFunction :: iterator OldPrior = std :: prev ( BBi ) ; bool B = TII -> AnalyzeBranch ( * BB , TBB , FBB , Cond ) ; if ( ! B && Cond . empty ( ) && BB != MF -> begin ( ) && ! TII -> AnalyzeBranch ( * OldPrior , TBB , FBB , CondPrior ) ) { BB -> moveAfter ( JTBB ) ; OldPrior -> updateTerminator ( ) ; BB -> updateTerminator ( ) ; MF -> RenumberBlocks ( ) ; ++ NumJTMoved ; return nullptr ; } MachineBasicBlock * NewBB = MF -> CreateMachineBasicBlock ( JTBB -> getBasicBlock ( ) ) ; MachineFunction :: iterator MBBI = ++ JTBB -> getIterator ( ) ; MF -> insert (


<s> unsigned Opcode = MI . getOpcode ( ) ; using namespace <ISA_LIT> ; if ( isIMUL ( Opcode ) ) return true ; if ( isBSF ( Opcode ) || isBSR ( Opcode ) || isLZCNT ( Opcode ) || isPOPCNT ( Opcode ) || isTZCNT ( Opcode ) ) return true ; if ( isBLCFILL ( Opcode ) || isBLCI ( Opcode ) || isBLCIC ( Opcode ) || isBLCMSK ( Opcode ) || isBLCS ( Opcode ) || isBLSFILL ( Opcode ) || isBLSI ( Opcode ) || isBLSIC ( Opcode ) || isBLSMSK ( Opcode ) || isBLSR ( Opcode ) || isTZMSK ( Opcode ) ) return true ; if ( isBEXTR ( Opcode ) || isBZHI ( Opcode ) ) return true ; if ( isROL ( Opcode ) || isROR ( Opcode ) || isSAR ( Opcode ) || isSHL ( Opcode ) || isSHR ( Opcode ) || isSHLD ( Opcode ) || isSHRD ( Opcode ) ) return true ; if ( isADC ( Opcode ) || isADD ( Opcode ) || isAND ( Opcode ) || isOR ( Opcode ) || isSBB ( Opcode ) || isSUB ( Opcode ) || isXOR ( Opcode ) ) return true ; if ( isADCX ( Opcode ) || isADOX ( Opcode ) || isANDN ( Opcode ) ) return true ; if ( isDEC ( Opcode ) || isINC ( Opcode ) || isNEG


<s> MCSubtargetInfo & STI = copySTI ( ) ; FeatureBitset FeatureBits = STI . getFeatureBits ( ) ; FeatureBits &= ~ <ISA_LIT>AssemblerOptions :: AllArchRelatedMask ; STI . setFeatureBits ( FeatureBits ) ; setAvailableFeatures ( ComputeAvailableFeatures ( STI . ToggleFeature ( ArchFeature ) ) ) ; AssemblerOptions . back ( ) -> setFeatures (


<s> void <ISA_LIT>PassConfig :: addIRPasses ( ) { TargetPassConfig :: addIRPasses ( ) ; addPass ( createGenericToNVVMPass (


<s> SectionKind Kind = CPE . getSectionKind ( & DL ) ; const Constant * C = CPE . Val . ConstVal ; unsigned Align = CPE . Alignment ; if ( const MCSectionCOFF * S = dyn_cast < MCSectionCOFF > ( getObjFileLowering ( ) . getSectionForConstant ( DL , Kind , C , Align ) ) ) { if ( MCSymbol * Sym = S -> getCOMDATSymbol ( ) ) { if ( Sym -> isUndefined ( ) ) OutStreamer -> EmitSymbolAttribute ( Sym , MCSA_Global ) ; return Sym


<s> static SDValue lowerShuffleWithUNPCK256 ( const SDLoc & DL , MVT VT , ArrayRef < int > Mask , SDValue V1 , SDValue V2 , SelectionDAG & DAG ) { SmallVector < int , <NUM_LIT> > Unpckl , Unpckh ; createSplat2ShuffleMask ( VT , Unpckl , true ) ; createSplat2ShuffleMask ( VT , Unpckh , false ) ; unsigned UnpackOpcode ; if ( isShuffleEquivalent ( Mask , Unpckl , V1 , V2


<s> if ( Features . test ( FeatureISAVersion8_0_1 ) ) return { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; if ( Features . test ( FeatureISAVersion8_0_2 ) ) return { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; if ( Features . test ( FeatureISAVersion8_0_3 ) ) return { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; if ( Features . test ( FeatureISAVersion8_0_4 ) ) return { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; if ( Features . test ( FeatureISAVersion8_1_0 ) ) return { <NUM_LIT> ,


<s> extern __inline int __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) _mm_popcnt_u32 ( unsigned int __X ) { return __builtin_popcount (


<s> void <ISA_LIT>DeadRegisterDefinitions :: processMachineBasicBlock ( MachineBasicBlock & MBB ) { const MachineFunction & MF = * MBB . getParent ( ) ; for ( MachineInstr & MI : MBB ) { if ( usesFrameIndex ( MI ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; continue ; } if ( MI . definesRegister ( <STR_LIT> ) || MI . definesRegister ( <STR_LIT> ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; continue ; } if ( atomicBarrierDroppedOnZero ( MI . getOpcode ( ) ) || atomicReadDroppedOnZero ( MI . getOpcode ( ) ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; continue ; } const MCInstrDesc & Desc = MI . getDesc ( ) ; for ( int I = <NUM_LIT> , E = Desc . getNumDefs


<s> bool <ISA_LIT>CallLowering :: lowerReturn ( MachineIRBuilder & MIRBuilder , const Value * Val , unsigned VReg ) const { assert ( ( ( Val && VReg ) || ( ! Val && ! VReg ) ) && <STR_LIT> ) ; auto MIB = MIRBuilder . buildInstrNoInsert ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ; if ( VReg ) { MachineFunction & MF = MIRBuilder . getMF ( ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; auto & DL = MF . getDataLayout ( ) ; const Function & F = * MF . getFunction ( ) ; ArgInfo OrigArg { VReg , Val -> getType ( ) } ; setArgFlags ( OrigArg , AttributeList :: ReturnIndex , DL , F ) ; SmallVector < ArgInfo , <NUM_LIT> > SplitArgs ; splitToValueTypes ( OrigArg , SplitArgs , DL , MRI , [ & ] ( ArrayRef < unsigned > Regs ) { MIRBuilder . buildUnmerge ( Regs , VReg ) ; } ) ; FuncReturnHandler Handler ( MIRBuilder , MRI , MIB , RetCC_<ISA_LIT>


<s> if ( MemType -> getPrimitiveSizeInBits ( ) > NativeWidth ) return nullptr ; auto Builder = IRBuilder < > ( AI ) ; Module * M = Builder . GetInsertBlock ( ) -> getParent ( ) -> getParent ( ) ; auto SynchScope = AI -> getSynchScope ( ) ; auto Order = AtomicCmpXchgInst :: getStrongestFailureOrdering ( AI -> getOrdering ( ) ) ; auto Ptr = AI -> getPointerOperand


<s> void <ISA_LIT>InstPrinter :: printMemRegReg ( const MCInst * MI , unsigned OpNo , const MCSubtargetInfo & STI , raw_ostream & O ) { if ( MI -> getOperand ( OpNo ) . getReg ( ) == <STR_LIT> ) O << <STR_LIT> ; else printOperand ( MI , OpNo , STI , O ) ; O << <STR_LIT> ; printOperand ( MI , OpNo + <NUM_LIT> , STI


<s> TargetRegistry :: RegisterMCSubtargetInfo ( The<ISA_LIT>Target , create<ISA_LIT>MCSubtargetInfo ) ; TargetRegistry :: RegisterMCInstPrinter ( The<ISA_LIT>Target , create<ISA_LIT>MCInstPrinter ) ; TargetRegistry :: RegisterELFStreamer ( The<ISA_LIT>Target , createMCStreamer ) ; TargetRegistry :: RegisterAsmTargetStreamer ( The<ISA_LIT>Target ,


<s> <ISA_LIT>AsmInstrumentation * Create<ISA_LIT>AsmInstrumentation ( const MCTargetOptions & MCOptions , const MCContext & Ctx , const MCSubtargetInfo * & STI ) { Triple T ( STI -> getTargetTriple ( ) ) ; const bool hasCompilerRTSupport = T . isOSLinux ( ) ; if ( ClAsanInstrumentAssembly && hasCompilerRTSupport && MCOptions . SanitizeAddress ) { if ( STI -> getFeatureBits ( ) [ <STR_LIT> ] != <NUM_LIT> ) return new <ISA_LIT>AddressSanitizer32 ( STI ) ; if ( STI -> getFeatureBits ( ) [ <STR_LIT> ] != <NUM_LIT> ) return new <ISA_LIT>AddressSanitizer64 ( STI ) ; } return new <ISA_LIT>AsmInstrumentation ( STI


<s> case <STR_LIT> : case <STR_LIT> : { unsigned CPI = Orig -> getOperand ( <NUM_LIT> ) . getIndex ( ) ; unsigned PCLabelId = duplicateCPV ( MF , CPI ) ; Orig -> getOperand ( <NUM_LIT> ) . setIndex ( CPI ) ; Orig -> getOperand ( <NUM_LIT> )


<s> bool Error ( SMLoc L , const Twine & Msg ,


<s> StringRef <STR_LIT> ( const Triple & TT , StringRef CPU ) { if ( CPU . empty ( ) || CPU == <STR_LIT> ) { if ( TT . isMIPS32 ( ) ) CPU =


<s> OptLEA = ST . LEAusesAG ( ) || ST . slowLEA ( ) || ST . slow3OpsLEA ( ) ; if ( ! OptLEA && ! OptIncDec ) return false ; TII = ST . getInstrInfo ( ) ; DEBUG ( dbgs ( ) << <STR_LIT> ; ) ; for ( MachineFunction :: iterator I = Func . begin ( ) , E = Func . end ( ) ; I != E ; ++ I ) processBasicBlock ( Func , I ) ; DEBUG ( dbgs ( ) << <STR_LIT>


<s> void <ISA_LIT>MCExpr :: visitUsedExpr ( MCStreamer & Streamer ) const { Streamer . visitUsedExpr ( * getSubExpr


<s> case CONST : case LABEL_REF : case SYMBOL_REF : * total = <NUM_LIT> ; return true ; case CONST_DOUBLE : * total = <NUM_LIT> ; return true ; case MULT : if ( optimize_size ) * total = COSTS_N_INSNS ( <NUM_LIT> ) ; else * total = COSTS_N_INSNS ( <NUM_LIT> ) ; return false ; case DIV : if ( optimize_size ) * total = COSTS_N_INSNS ( <NUM_LIT> ) ; else * total = COSTS_N_INSNS ( <NUM_LIT> ) ; return false ; case MOD : if ( optimize_size ) * total = COSTS_N_INSNS ( <NUM_LIT> ) ; else * total = COSTS_N_INSNS ( <NUM_LIT> ) ; return false ; case ABS : * total = COSTS_N_INSNS ( <NUM_LIT> ) ; return false ; case ZERO_EXTEND : * total = COSTS_N_INSNS ( <NUM_LIT> ) ; return false ; case SIGN_EXTEND : if ( GET_MODE ( x ) == HImode ) * total = COSTS_N_INSNS ( <NUM_LIT> ) ; else if ( GET_MODE ( x ) == SImode ) * total = COSTS_N_INSNS ( <NUM_LIT> ) ; else * total = COSTS_N_INSNS ( <NUM_LIT> ) ; return false ; case ASHIFT : case LSHIFTRT : case ASHIFTRT : if ( optimize_size ) * total = COSTS_N_INSNS ( <NUM_LIT> ) ; else if ( GET_MODE ( x ) ==


<s> void LLVMInitialize<ISA_LIT>TargetInfo ( ) { TargetRegistry :: RegisterTarget ( The<ISA_LIT>Target , <STR_LIT> , <STR_LIT> , [ ] ( Triple :: ArchType ) { return false ; } , true ) ; RegisterTarget < Triple :: bpfel , true > X ( The<ISA_LIT>leTarget


<s> const char * <ISA_LIT>TargetAsmInfo :: getASDirective ( unsigned size , unsigned AS ) const { if ( AS == <STR_LIT> ) return getRomDirective ( size


<s> return __builtin_shuffle ( a , ( uint8x8_t ) { <NUM_LIT> , <NUM_LIT> , <NUM_LIT>


<s> PM . add ( createBasicTargetTransformInfoPass ( this )


<s> { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel | MCFixupKindInfo :: FKF_IsAlignedDownTo32Bits } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel | MCFixupKindInfo :: FKF_IsAlignedDownTo32Bits } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel | MCFixupKindInfo :: FKF_IsAlignedDownTo32Bits } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel | MCFixupKindInfo :: FKF_IsAlignedDownTo32Bits } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo ::


<s> MaxJumpTableSize = <NUM_LIT> ; PrefFunctionLogAlignment = <NUM_LIT> ; PrefLoopLogAlignment = <NUM_LIT> ; break ; case Falkor : MaxInterleaveFactor = <NUM_LIT> ; MinVectorRegisterBitWidth = <NUM_LIT> ; CacheLineSize = <NUM_LIT> ; PrefetchDistance = <NUM_LIT> ; MinPrefetchStride = <NUM_LIT> ; MaxPrefetchIterationsAhead = <NUM_LIT> ; break ; case Kryo : MaxInterleaveFactor = <NUM_LIT> ; VectorInsertExtractBaseCost = <NUM_LIT> ; CacheLineSize = <NUM_LIT> ; PrefetchDistance = <NUM_LIT> ; MinPrefetchStride = <NUM_LIT> ; MaxPrefetchIterationsAhead = <NUM_LIT> ; MinVectorRegisterBitWidth = <NUM_LIT> ; break ; case NeoverseE1 : PrefFunctionLogAlignment = <NUM_LIT> ; break ; case NeoverseN1 : PrefFunctionLogAlignment = <NUM_LIT> ; break ; case Saphira : MaxInterleaveFactor = <NUM_LIT> ; MinVectorRegisterBitWidth = <NUM_LIT> ; break ; case ThunderX2T99 : CacheLineSize = <NUM_LIT> ; PrefFunctionLogAlignment = <NUM_LIT> ; PrefLoopLogAlignment = <NUM_LIT> ; MaxInterleaveFactor = <NUM_LIT> ; PrefetchDistance = <NUM_LIT> ; MinPrefetchStride = <NUM_LIT> ; MaxPrefetchIterationsAhead = <NUM_LIT> ; MinVectorRegisterBitWidth = <NUM_LIT> ; break ; case ThunderX : case ThunderXT88 : case ThunderXT81 : case ThunderXT83 : CacheLineSize = <NUM_LIT> ; PrefFunctionLogAlignment = <NUM_LIT> ; PrefLoopLogAlignment = <NUM_LIT> ; MinVectorRegisterBitWidth = <NUM_LIT> ; break ; case TSV110 : CacheLineSize = <NUM_LIT> ; PrefFunctionLogAlignment = <NUM_LIT> ; PrefLoopLogAlignment = <NUM_LIT> ; break ; case ThunderX3T110 : CacheLineSize = <NUM_LIT> ; PrefFunctionLogAlignment = <NUM_LIT> ; PrefLoopLogAlignment =


<s> SDValue TGA = DAG . getTargetGlobalAddress ( GA -> getGlobal ( ) , dl , GA -> getValueType ( <NUM_LIT> ) , GA -> getOffset ( ) , OperandFlags ) ; <STR_LIT> CallType = LocalDynamic ? <STR_LIT> : <STR_LIT> ; if ( InFlag ) { SDValue Ops [ ] = { Chain , TGA , * InFlag } ; Chain = DAG . getNode ( CallType , dl , NodeTys , Ops , array_lengthof ( Ops ) ) ; } else { SDValue Ops [ ] = { Chain , TGA } ; Chain = DAG . getNode ( CallType , dl , NodeTys , Ops , array_lengthof ( Ops ) ) ; } MFI -> setAdjustsStack (


<s> VL = CurDAG -> getTargetConstant ( C -> getZExtValue ( ) , SDLoc ( N ) , N -> getValueType ( <NUM_LIT> ) ) ; } else if ( C && C -> isAllOnesValue ( ) ) { VL = CurDAG -> getTargetConstant ( <STR_LIT> , SDLoc ( N ) , N -> getValueType ( <NUM_LIT> ) ) ; } else if ( isa < RegisterSDNode > ( N ) && cast < RegisterSDNode > ( N ) -> getReg ( ) == <STR_LIT> ) { VL = CurDAG -> getTargetConstant ( <STR_LIT> , SDLoc ( N ) , N -> getValueType ( <NUM_LIT> ) ) ; } else { VL = N ; } return


<s> Register getExceptionSelectorRegister ( const Constant * PersonalityFn ) const override { return <STR_LIT>


<s> int imm = Val & <NUM_LIT> ; if ( Val == <NUM_LIT> ) imm = INT32_MIN ; else if ( ! ( Val & <NUM_LIT>


<s> void addParam ( MVT VT ) { Params . push_back ( VT )


<s> return iq2000_print_operand_punct [ code ]


<s> } unsigned Opcode = I -> getOpcode ( ) ; if ( Opcode != <STR_LIT> && Opcode != <STR_LIT> ) return true ; <STR_LIT> BranchCode = ( <STR_LIT> ) I -> getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( Cond . empty ( ) ) { MachineBasicBlock * TargetBB = I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; if ( AllowModify && UnCondBrIter != MBB . end ( ) && MBB . isLayoutSuccessor ( TargetBB ) ) { BranchCode = GetOppositeBranchCondition ( BranchCode ) ; MachineBasicBlock :: iterator OldInst = I ; BuildMI ( MBB , UnCondBrIter , MBB . findDebugLoc ( I ) , get ( Opcode ) ) . addMBB ( UnCondBrIter -> getOperand ( <NUM_LIT> ) . getMBB ( ) ) . addImm ( BranchCode ) ; BuildMI ( MBB , UnCondBrIter , MBB . findDebugLoc ( I ) , get ( <STR_LIT> ) ) . addMBB ( TargetBB ) ; OldInst -> eraseFromParent ( ) ; UnCondBrIter -> eraseFromParent ( ) ; UnCondBrIter = MBB . end ( ) ; I = MBB . end ( ) ; continue ; } FBB = TBB ; TBB = I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; Cond . push_back ( MachineOperand :: CreateImm ( BranchCode ) ) ; continue ; } return true


<s> if ( fntype ) { pcum -> force_mem = ( ( TARGET_HITACHI || pcum -> renesas_abi ) && aggregate_value_p ( TREE_TYPE ( fntype ) , fndecl ) ) ; pcum -> prototype_p = TYPE_ARG_TYPES ( fntype ) ? TRUE : FALSE ; pcum -> arg_count [ ( int ) SH_ARG_INT ] = TARGET_SH5 && aggregate_value_p ( TREE_TYPE ( fntype ) , fndecl ) ; pcum -> call_cookie = CALL_COOKIE_RET_TRAMP ( TARGET_SHCOMPACT && pcum -> arg_count [ ( int ) SH_ARG_INT ] == <NUM_LIT> && ( TYPE_MODE ( TREE_TYPE ( fntype ) ) == BLKmode ? int_size_in_bytes ( TREE_TYPE ( fntype ) ) : GET_MODE_SIZE ( TYPE_MODE ( TREE_TYPE ( fntype ) ) ) ) > <NUM_LIT> && ( BASE_RETURN_VALUE_REG ( TYPE_MODE ( TREE_TYPE ( fntype ) ) ) == FIRST_RET_REG ) ) ; } else { pcum -> arg_count [ ( int ) SH_ARG_INT ] = <NUM_LIT> ; pcum -> prototype_p = FALSE ; if ( mode != VOIDmode


<s> return ( __m128i ) __builtin_ia32_prorq128_mask ( ( __v2di ) __A , __B , ( __v2di ) _mm_setzero_di ( ) , (


<s> static int stackSlotSize ( ) { return <NUM_LIT>


<s> virtual const char * getPassName ( )


<s> } SmallVector < Instruction * , <NUM_LIT> > ToRemove ; for ( Instruction & I : instructions ( F ) ) { CallInst * Call = dyn_cast < CallInst > ( & I ) ; if ( ! Call ) continue ; Function * Callee = Call -> getCalledFunction ( ) ; if ( ! Callee || ( Callee -> getName ( ) != NVVM_REFLECT_FUNCTION && Callee -> getIntrinsicID ( ) != <STR_LIT> ) ) continue ; assert ( Call -> getNumOperands ( ) == <NUM_LIT> && <STR_LIT> ) ; const Value * Str = Call -> getArgOperand ( <NUM_LIT> ) ; if ( const CallInst * ConvCall = dyn_cast < CallInst > ( Str ) ) { Str = ConvCall -> getArgOperand ( <NUM_LIT> ) ; } assert ( isa < ConstantExpr > ( Str ) && <STR_LIT> ) ; const ConstantExpr * GEP = cast < ConstantExpr > ( Str ) ; const Value * Sym = GEP -> getOperand ( <NUM_LIT> ) ; assert ( isa < Constant > ( Sym ) && <STR_LIT> ) ; const Value * Operand = cast < Constant > (


<s> inline vector signed short vec_vupkhsb ( vector


<s> MachineOperand & PMO = MI . getOperand ( PIdx ) ; PMO . setImm ( Pred [ <NUM_LIT> ] . getImm ( ) ) ; if ( Pred [ <NUM_LIT> ] . getImm ( ) == <STR_LIT> ) MI . getOperand ( PIdx + <NUM_LIT> ) . ChangeToRegister ( <NUM_LIT> , false ) ; else MI . getOperand ( PIdx + <NUM_LIT> ) . ChangeToRegister ( <STR_LIT> , false , true ) ; return true


<s> RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; emit_insn ( gen_frame_blockage ( ) ) ; } else { rtx size_int_rtx = GEN_INT ( - size ) ; if ( size <= <NUM_LIT> ) emit_window_save ( size_int_rtx ) ; else if ( size <= <NUM_LIT> ) { emit_window_save ( GEN_INT ( - <NUM_LIT> ) ) ; emit_insn ( gen_stack_pointer_inc ( GEN_INT ( <NUM_LIT> - size ) ) ) ; emit_insn ( gen_frame_blockage ( ) ) ; } else { rtx size_rtx = gen_rtx_REG ( Pmode , <NUM_LIT> ) ; emit_move_insn ( size_rtx , size_int_rtx ) ; emit_window_save ( size_rtx ) ; } } if ( sparc_leaf_function_p ) { sparc_frame_base_reg = stack_pointer_rtx ; sparc_frame_base_offset = size + SPARC_STACK_BIAS ; } else { sparc_frame_base_reg =


<s> const TargetRegisterClass * <ISA_LIT>RegisterInfo :: getPointerRegClass ( const MachineFunction & MF


<s> static MCRegisterInfo * create<ISA_LIT>MCRegisterInfo ( const Triple & TT ) { MCRegisterInfo * X =


<s> if ( RegNum > getContext ( ) . getRegisterInfo ( ) -> getRegClass

( RegClass ) . getNumRegs ( ) - <NUM_LIT> ) return - <NUM_LIT> ;


<s> RegisterRef RegisterAggr :: clearIn ( RegisterRef RR ) const { RegisterAggr T ( PRI ) ; T . insert ( RR ) .


<s> static DecodeStatus DecodeT2ShifterImmOperand ( MCInst & Inst , uint32_t Val , uint64_t Address , const void


<s> case ESize16 : return ( insn >> <NUM_LIT> ) & <NUM_LIT> ; case ESize32 : return ( insn >> <NUM_LIT> ) &


<s> if ( TARGET_OMIT_LEAF_FRAME_POINTER && ! crtl -> is_leaf ) return true ; return false


<s> <STR_LIT> CC = <STR_LIT> ( N -> getConstantOperandVal ( <NUM_LIT> ) ) ; SDValue EFLAGS = N -> getOperand ( <NUM_LIT> ) ; if ( CC == <STR_LIT> ) { if ( EFLAGS . getOpcode ( ) == <STR_LIT> && EFLAGS . hasOneUse ( ) && EFLAGS . getValueType ( ) . isInteger ( ) && ! isa < ConstantSDNode > ( EFLAGS . getOperand ( <NUM_LIT> ) ) ) { SDValue NewSub = DAG . getNode ( <STR_LIT> , SDLoc ( EFLAGS ) , EFLAGS . getNode ( ) -> getVTList ( ) , EFLAGS . getOperand ( <NUM_LIT> ) , EFLAGS . getOperand ( <NUM_LIT> ) ) ; SDValue NewEFLAGS = SDValue ( NewSub . getNode ( ) , EFLAGS . getResNo ( ) ) ; return MaterializeSETB ( DL , NewEFLAGS , DAG , N -> getSimpleValueType ( <NUM_LIT> ) ) ; } } if ( CC == <STR_LIT> ) return MaterializeSETB ( DL , EFLAGS , DAG , N -> getSimpleValueType ( <NUM_LIT> ) ) ; if ( SDValue Flags = combineSetCCEFLAGS ( EFLAGS , CC , DAG ) ) return getSETCC ( CC , Flags , DL , DAG ) ; return SDValue (


<s> LLVM_FALLTHROUGH ; case Instruction :: Add : case Instruction :: Or : case Instruction :: Xor : ShiftedFree = true ; LLVM_FALLTHROUGH ; case Instruction :: Sub : case Instruction :: Mul : case Instruction :: Shl : case Instruction :: LShr : case Instruction :: AShr : ImmIdx = <NUM_LIT> ; break ; case Instruction :: ICmp : UnsignedFree = true ; ImmIdx = <NUM_LIT> ; LLVM_FALLTHROUGH ; case Instruction :: Select : ZeroFree = true ; break ; case Instruction :: PHI : case Instruction :: Call : case Instruction :: Ret : case Instruction :: Load : case Instruction :: Store : break ; } if ( ZeroFree && Imm == <NUM_LIT> ) return TTI :: TCC_Free ; if ( Idx == ImmIdx && Imm . getBitWidth ( ) <= <NUM_LIT> ) { if ( isInt < <NUM_LIT> > ( Imm . getSExtValue ( ) ) ) return TTI :: TCC_Free ; if ( RunFree ) { if ( Imm . getBitWidth ( ) <= <NUM_LIT> && ( isShiftedMask_32 ( Imm . getZExtValue ( ) ) || isShiftedMask_32 ( ~ Imm .

getZExtValue ( ) ) ) ) return TTI :: TCC_Free ;


<s> bool <ISA_LIT>TargetLowering :: isReassocProfitable ( SelectionDAG & DAG , SDValue N0 , SDValue N1 ) const { if ( ! N0 . hasOneUse ( ) ) return false ; if ( N0 -> isDivergent ( ) || ! N1 -> isDivergent


<s> bool <ISA_LIT>DAGToDAGISel :: isPrivateStore ( const StoreSDNode * N ) { const Value * MemVal = N -> getMemOperand ( ) ->


<s> unsigned getImmMinusOneOpValue ( const MachineInstr & MI


<s> virtual bool requiresRegisterScavenging ( const MachineFunction & MF )


<s> __builtin_ia32_pmovusdb128mem_mask ( ( unsigned int * ) __P ,


<s> DebugLoc dl = N -> getDebugLoc ( ) ; SDValue Base = DAG . getLoad ( <STR_LIT> , dl , Chain , VAListP , VAListS , <NUM_LIT> ) ; SDValue Tmp = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , VAListP , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDValue Offset = DAG . getExtLoad ( <STR_LIT> , dl , <STR_LIT> , Base . getValue ( <NUM_LIT> ) , Tmp , NULL , <NUM_LIT> , <STR_LIT> ) ; DataPtr = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Base , Offset ) ; if ( N -> getValueType ( <NUM_LIT> ) . isFloatingPoint ( ) ) { SDValue FPDataPtr = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DataPtr , DAG . getConstant ( <NUM_LIT> * <NUM_LIT> , <STR_LIT> ) ) ; SDValue CC = DAG . getSetCC ( dl , <STR_LIT> , Offset , DAG . getConstant ( <NUM_LIT> * <NUM_LIT> , <STR_LIT> ) , <STR_LIT> ) ; DataPtr = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , CC , FPDataPtr , DataPtr ) ; } SDValue NewOffset = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Offset , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; Chain = DAG . getTruncStore ( Offset . getValue ( <NUM_LIT> ) , dl , NewOffset , Tmp , NULL , <NUM_LIT>


<s> if ( data_ref_p ( op ) ) return true ; return


<s> void <ISA_LIT>CFGStructurizer :: showImproveSimpleJumpintoIf ( MachineBasicBlock * HeadMBB , MachineBasicBlock * TrueMBB , MachineBasicBlock * FalseMBB , MachineBasicBlock * LandMBB , bool Detail ) { dbgs ( ) << <STR_LIT> << HeadMBB -> getNumber ( ) << <STR_LIT> << HeadMBB -> size ( ) ; if ( Detail ) { dbgs ( ) << <STR_LIT> ; HeadMBB -> print ( dbgs ( ) ) ; dbgs ( ) << <STR_LIT> ; } if ( TrueMBB ) { dbgs ( ) << <STR_LIT> << TrueMBB -> getNumber ( ) << <STR_LIT> << TrueMBB -> size ( ) << <STR_LIT> << TrueMBB -> pred_size ( ) ; if ( Detail ) { dbgs ( ) << <STR_LIT> ; TrueMBB -> print ( dbgs ( ) ) ; dbgs ( ) << <STR_LIT> ; } } if ( FalseMBB ) { dbgs ( ) << <STR_LIT> << FalseMBB -> getNumber ( ) << <STR_LIT> << FalseMBB -> size ( ) << <STR_LIT> << FalseMBB -> pred_size ( ) ; if ( Detail ) { dbgs ( ) << <STR_LIT> ; FalseMBB -> print ( dbgs ( ) ) ; dbgs ( ) << <STR_LIT> ; } } if ( LandMBB ) { dbgs ( ) << <STR_LIT> << LandMBB -> getNumber ( ) << <STR_LIT> << LandMBB -> size ( ) << <STR_LIT> << LandMBB -> pred_size ( ) ; if ( Detail ) { dbgs ( ) << <STR_LIT> ; LandMBB -> print ( dbgs ( )


<s> for ( int l = <NUM_LIT> ; l < NumElts ; l += NumLaneElts ) { for ( int i = <NUM_LIT> ; i < NumLaneElts ; ++ i ) { if ( Mask [ l + i ] == - <NUM_LIT> ) continue ; assert ( Mask [ l + i ] >= <NUM_LIT> && <STR_LIT> ) ; int LaneIdx = ( Mask [ l + i ] % NumElts ) - l ; if ( LaneIdx < <NUM_LIT> || LaneIdx >= NumLaneElts ) return SDValue ( ) ; int StartIdx = i - LaneIdx ; if ( StartIdx == <NUM_LIT> ) return SDValue ( ) ; int CandidateRotation = StartIdx < <NUM_LIT> ? - StartIdx : NumLaneElts - StartIdx ; if ( Rotation == <NUM_LIT> ) Rotation = CandidateRotation ; else if ( Rotation != CandidateRotation ) return SDValue ( ) ; SDValue MaskV = Mask [ l + i ] < NumElts ? V1 : V2 ; SDValue & TargetV = StartIdx < <NUM_LIT> ? Hi : Lo ; if ( ! TargetV ) TargetV = MaskV ; else if ( TargetV != MaskV ) return SDValue ( ) ; } } assert ( Rotation != <NUM_LIT> && <STR_LIT> ) ; assert ( ( Lo || Hi ) && <STR_LIT> ) ; if ( ! Lo ) Lo = Hi ; else if ( ! Hi ) Hi = Lo ; int Scale = <NUM_LIT> / NumLaneElts ; if ( Subtarget -> hasSSSE3 ( ) ) { MVT AlignVT = <STR_LIT> ( <STR_LIT> , <NUM_LIT> * NumLanes ) ; Lo = DAG . getBitcast ( AlignVT ,


<s> unsigned HOST_WIDE_INT temp ; if ( op_const == <NUM_LIT> ) return NULL ; if ( opint [ <NUM_LIT> ] == <NUM_LIT> ) temp = <NUM_LIT> ; else temp = <NUM_LIT> - floor_log2 ( opint [ <NUM_LIT> ] ) - <NUM_LIT> ; return build_int_cst ( alpha_dimode_u , temp


<s> if ( isBitwiseNot ( Op0 ) ) return SDValue ( ) ; if ( ! SupportedVectorShiftWithImm ( VT0 . getSimpleVT ( ) , Subtarget , <STR_LIT> ) ) return SDValue ( ) ; unsigned EltBitWidth = VT0 . getScalarSizeInBits ( ) ; if ( EltBitWidth != DAG . ComputeNumSignBits ( Op0 ) ) return SDValue ( ) ; SDLoc DL ( N ) ; unsigned ShiftVal = SplatVal . countTrailingOnes ( ) ; SDValue ShAmt = DAG . getConstant ( EltBitWidth - ShiftVal , DL


<s> unsigned Reg = Op . getReg ( ) ; if ( Reg == <STR_LIT> ) O << '#' << Imm ; else O << getRegisterName ( Reg ) ; } else llvm_unreachable


<s> if ( MI -> getOperand ( Op ) . isFI ( ) ) return true ; return Op + <STR_LIT> <= MI -> getNumOperands ( ) && MI -> getOperand ( Op + <STR_LIT> ) . isReg ( ) && isScale ( MI -> getOperand ( Op + <STR_LIT> ) ) && MI -> getOperand ( Op + <STR_LIT> ) . isReg ( ) && ( MI -> getOperand ( Op + <STR_LIT> ) . isImm ( ) || MI -> getOperand ( Op + <STR_LIT> ) . isGlobal ( ) || MI -> getOperand ( Op + <STR_LIT> ) . isCPI (

) || MI -> getOperand ( Op + <STR_LIT> ) . isJTI ( ) ) ;


<s> if ( ! TARGET_SSE_MATH ) for ( i = FIRST_STACK_REG ; i <= LAST_STACK_REG ; i ++ ) reg_alloc_order [ pos ++ ] = i ; for ( i = FIRST_SSE_REG ; i <= LAST_SSE_REG ; i ++ ) reg_alloc_order [ pos ++ ] = i ; for ( i = FIRST_REX_SSE_REG ; i <= LAST_REX_SSE_REG ; i ++ ) reg_alloc_order [ pos ++ ] = i ; for ( i = FIRST_EXT_REX_SSE_REG ; i <= LAST_EXT_REX_SSE_REG ; i ++ ) reg_alloc_order [ pos ++ ] = i ; for ( i = FIRST_MASK_REG ; i <= LAST_MASK_REG ; i ++ ) reg_alloc_order [ pos ++ ] = i ; if ( TARGET_SSE_MATH ) for ( i = FIRST_STACK_REG ; i <= LAST_STACK_REG ; i ++ ) reg_alloc_order [ pos ++ ] = i ; for ( i = FIRST_MMX_REG ; i <= LAST_MMX_REG ; i ++ ) reg_alloc_order [ pos ++ ] = i ; while ( pos < FIRST_PSEUDO_REGISTER ) reg_alloc_order [ pos ++ ] =


<s> bool isVGPRCopy ( const MachineInstr & MI ) const { assert ( MI . isCopy ( ) ) ; unsigned Dest = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; const MachineFunction & MF = * MI .


<s> InstructionCost getVectorSplitCost (


<s> const MCExpr * getConstantPoolImm ( ) const { assert ( isConstantPoolImm ( ) && <STR_LIT> ) ; return Imm


<s> DebugLoc dl = Lower . getDebugLoc ( ) ; assert ( Lower . getValueType ( ) == Upper . getValueType ( ) && <STR_LIT> ) ; EVT VT = EVT :: getVectorVT ( * DAG . getContext ( ) , Lower . getValueType ( ) . getVectorElementType ( ) , Lower . getValueType ( ) . getVectorNumElements ( ) * <NUM_LIT> ) ; assert ( VT . getSizeInBits ( ) == <NUM_LIT> && <STR_LIT> ) ; SDValue Vec = Insert128BitVector ( DAG . getNode ( <STR_LIT> , dl , VT ) , Upper , DAG . getConstant ( Lower . getValueType ( ) . getVectorNumElements ( ) , <STR_LIT> ) , DAG , dl ) ; Vec = Insert128BitVector ( Vec , Lower , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) , DAG , dl ) ; return Vec


<s> if ( getTargetMachine ( ) . getRelocationModel ( ) != Reloc :: PIC_ ) return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Lo , Hi ) ; SDValue GlobalBase = DAG . getNode ( <STR_LIT> , dl , getPointerTy ( ) ) ; SDValue RelAddr = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Lo , Hi ) ; SDValue AbsAddr = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , GlobalBase


<s> unsigned pred = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; Rm |= fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ; if ( Rt == <NUM_LIT> || Rt2 == <NUM_LIT> || Rm == <NUM_LIT> ) S = MCDisassembler :: SoftFail ; if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rt , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rt2 , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeSPRRegisterClass ( Inst , Rm , Address , Decoder ) )


<s> if ( ! Subtarget -> hasVFP2 ( ) || Subtarget -> isFPOnlySP ( ) ) return false ; Value * V = I -> getOperand ( <NUM_LIT> ) ; if ( ! I -> getType ( ) -> isDoubleTy ( ) || ! V -> getType ( ) -> isFloatTy ( )


<s> bool isLiveIn ( int FI ) { for ( unsigned i = <NUM_LIT> , e = LiveInFI . size ( ) ; i < e ; ++ i ) if ( FI == LiveInFI [ i ] ) return true ; return false


<s> static DecodeStatus DecodeGPRnopcRegisterClass ( llvm :: MCInst & Inst , unsigned RegNo , uint64_t Address , const void *


<s> static unsigned findScratchNonCalleeSaveRegister ( MachineBasicBlock * MBB ) { MachineFunction * MF = MBB -> getParent ( ) ; if ( & MF -> front ( ) == MBB ) return <STR_LIT> ; RegScavenger RS ; RS . enterBasicBlock ( MBB ) ; if ( ! RS . isRegUsed ( <STR_LIT> ) ) return <STR_LIT> ; const <ISA_LIT>Subtarget & Subtarget = MF -> getSubtarget < <ISA_LIT>Subtarget > ( ) ; const <ISA_LIT>RegisterInfo * RegInfo = Subtarget . getRegisterInfo


<s> if ( AnyExt && EltBits == <NUM_LIT> && Scale > <NUM_LIT> ) { int PSHUFDMask [ <NUM_LIT> ] = { <NUM_LIT> , - <NUM_LIT> , <NUM_LIT> , - <NUM_LIT> } ; InputV = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , InputV ) , getV4<ISA_LIT>ShuffleImm8ForMask ( PSHUFDMask , DAG ) ) ; int PSHUFHWMask [ <NUM_LIT> ] = { <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> } ; return DAG . getNode ( <STR_LIT> , DL , VT , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , InputV ) , getV4<ISA_LIT>ShuffleImm8ForMask ( PSHUFHWMask , DAG ) ) ) ; } if ( Scale > <NUM_LIT> && EltBits == <NUM_LIT> && Subtarget -> hasSSSE3 ( ) ) { assert ( NumElements == <NUM_LIT> && <STR_LIT> ) ; SDValue PSHUFBMask [ <NUM_LIT> ] ; for ( int i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) PSHUFBMask [ i ] = DAG . getConstant ( ( i % Scale == <NUM_LIT> ) ? i / Scale : <NUM_LIT> , <STR_LIT> ) ; InputV = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , InputV ) ; return DAG . getNode ( <STR_LIT> , DL , VT , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , InputV , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , PSHUFBMask ) ) ) ; } do { MVT InputVT = <STR_LIT> ( <STR_LIT> ( EltBits ) , NumElements ) ; SDValue Ext = AnyExt ? DAG . getUNDEF ( InputVT ) : getZeroVector ( InputVT , Subtarget , DAG , DL ) ; InputV = DAG . getNode ( <STR_LIT> , DL , InputVT , InputV ) ; InputV = DAG . getNode ( <STR_LIT> , DL , InputVT , InputV , Ext ) ; Scale /= <NUM_LIT> ; EltBits *= <NUM_LIT> ; NumElements /= <NUM_LIT> ; } while ( Scale > <NUM_LIT> ) ; return DAG . getNode ( <STR_LIT> , DL , VT ,


<s> assert ( Kind == KindTy :: SpecialCapRegister


<s> rtl_opt_pass * make_pass_handle_trap_shadows ( gcc :: context * ctxt


<s> bool <ISA_LIT>BaseInstrInfo :: isPredicable ( const MachineInstr & MI ) const { if ( ! MI . isPredicable ( ) ) return false ; if ( MI . isBundle ( ) ) return false ; if ( ! isEligibleForITBlock ( & MI ) ) return false ; const <ISA_LIT>FunctionInfo * AFI = MI . getParent ( ) -> getParent ( ) -> getInfo < <ISA_LIT>FunctionInfo > ( ) ; if ( ( MI . getDesc ( ) . TSFlags & <STR_LIT> ) == <STR_LIT> ) return false ; if ( AFI -> isThumb2Function ( ) ) { if ( getSubtarget ( ) . restrictIT ( )


<s> bool mayNeedRelaxation ( const MCInst & Inst ) const override { return


<s> if ( Op . isImm ( ) ) { int64_t Imm = Op . getImm ( ) * <NUM_LIT> + <NUM_LIT> ; O << <STR_LIT> ; if ( Imm >= <NUM_LIT> ) O << '+' ; O <<


<s> SDValue InChain = DAG . getEntryNode ( ) ; TargetLowering :: ArgListTy Args = getDivRemArgList ( Op . getNode ( ) , DAG . getContext ( ) , Subtarget ) ; SDValue Callee = DAG . getExternalSymbol ( getLibcallName ( LC ) , getPointerTy ( DAG . getDataLayout ( ) ) ) ; Type * RetTy = ( Type * ) StructType :: get ( Ty , Ty , nullptr ) ; if ( Subtarget -> isTargetWindows ( ) ) InChain = WinDBZCheckDenominator ( DAG , Op . getNode ( ) , InChain ) ; TargetLowering :: CallLoweringInfo CLI ( DAG ) ; CLI . setDebugLoc ( dl ) . setChain ( InChain ) . setCallee ( getLibcallCallingConv ( LC ) , RetTy , Callee , std :: move ( Args ) ) . setInRegister ( ) . setSExtResult ( isSigned ) . setZExtResult ( ! isSigned ) ; std :: pair < SDValue , SDValue > CallInfo = LowerCallTo ( CLI ) ; return CallInfo . first


<s> if ( ! STI -> hasV5TEOps ( ) ) return false ; unsigned Scale = <NUM_LIT> ; unsigned Opcode = Op0 -> getOpcode ( ) ; if ( Opcode == <STR_LIT> ) NewOpc = <STR_LIT> ; else if ( Opcode == <STR_LIT> ) NewOpc = <STR_LIT> ; else if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) { NewOpc = <STR_LIT> ; Scale = <NUM_LIT> ; isT2 = true ; } else if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) { NewOpc = <STR_LIT> ; Scale = <NUM_LIT> ; isT2 = true ; } else return false ; if ( ! Op0 -> hasOneMemOperand ( ) || ! ( * Op0 -> memoperands_begin ( ) ) -> getValue ( ) || ( * Op0 -> memoperands_begin ( ) ) -> isVolatile ( ) ) return false ; unsigned Align = ( * Op0 -> memoperands_begin ( ) ) -> getAlignment ( ) ; const Function * Func = MF -> getFunction ( ) ; unsigned ReqAlign = STI -> hasV6Ops ( ) ? TD -> getABITypeAlignment ( Type :: getInt64Ty ( Func -> getContext ( ) ) ) : <NUM_LIT> ; if ( Align < ReqAlign ) return false ; int OffImm = getMemoryOpOffset ( Op0 ) ; if ( isT2 ) { if ( OffImm < <NUM_LIT> ) { if ( OffImm < - <NUM_LIT> ) return false ; } else


<s> if ( LoadStoreOp == - <NUM_LIT> ) return false ; const MachineOperand * Reg = TII -> getNamedOperand ( * MI , <STR_LIT> :: vdata ) ; BuildMI ( * MBB , MI , DL , TII -> get ( LoadStoreOp ) ) . add ( * Reg ) . add ( * TII -> getNamedOperand ( * MI , <STR_LIT> :: srsrc ) ) . add ( * TII -> getNamedOperand ( * MI , <STR_LIT> :: soffset ) ) . addImm ( Offset ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . setMemRefs ( MI -> memoperands_begin ( ) , MI -> memoperands_end ( ) ) ; return


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , Optional < CodeModel :: Model > CM , CodeGenOpt :: Level OL , bool JIT ) : LLVMTargetMachine ( T , computeDataLayout ( TT ) , TT , CPU , FS , Options , getEffectiveRelocModel ( RM ) , getEffectiveCodeModel (

CM , CodeModel :: Small ) , OL ) , TLOF ( createTLOF ( ) ) , Subtarget ( TT , CPU , FS , * this ) {


<s> enum attr_type dep_insn_type ; int dep_insn_code_number ; if ( REG_NOTE_KIND ( link ) != <NUM_LIT> ) return <NUM_LIT> ; dep_insn_code_number = recog_memoized ( dep_insn ) ; if ( dep_insn_code_number < <NUM_LIT> || recog_memoized ( insn ) < <NUM_LIT> ) return cost ; dep_insn_type = get_attr_type ( dep_insn ) ; if ( dep_insn_type == TYPE_MOVE || dep_insn_type == TYPE_MCLD ) { rtx pat = PATTERN ( dep_insn ) ; rtx dest , src ; if ( GET_CODE ( pat ) == PARALLEL ) pat = XVECEXP ( pat , <NUM_LIT> , <NUM_LIT> ) ; dest = SET_DEST ( pat ) ; src = SET_SRC ( pat ) ; if ( ! ADDRESS_REGNO_P ( REGNO ( dest ) ) || ! ( MEM_P ( src ) || D_REGNO_P ( REGNO ( src ) ) ) ) return cost ; return cost + ( dep_insn_type == TYPE_MOVE


<s> return __builtin_mve_vdupq_m_n_sv8hi ( __arm_vuninitializedq_s16 ( )


<s> static bool hasSpills ( const MachineFunction & MF ) { const <ISA_LIT>FunctionInfo * FuncInfo = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; return FuncInfo -> hasSpills ( )


<s> return StringSwitch < unsigned > ( RegName ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case

( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( <NUM_LIT> ) ;


<s> MVT VT = Op . getSimpleValueType ( ) ; SDValue In = Op . getOperand ( <NUM_LIT> ) ; MVT SVT = In . getSimpleValueType ( ) ; if ( VT == <STR_LIT> ) { RTLIB :: Libcall LC = RTLIB :: getFPEXT ( SVT , VT ) ; return LowerF128Call ( Op ,


<s> Arg = DAG . getNode ( <STR_LIT> , dl , VA . getLocVT ( ) , Arg ) ; break ; case CCValAssign :: SExt : Arg = DAG . getNode ( <STR_LIT> , dl , VA . getLocVT ( ) , Arg ) ; break ; } Chain = DAG . getCopyToReg ( Chain , dl , VA . getLocReg ( ) , Arg , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( VA . getLocReg ( ) , VA . getLocVT ( ) ) ) ; } RetOps [ <NUM_LIT> ] = Chain ; if ( Flag . getNode ( ) ) RetOps . push_back ( Flag ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , & RetOps [


<s> unsigned UnitSz = ( AS == <NUM_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; assert ( ( Sz % UnitSz == <NUM_LIT> ) && <STR_LIT> ) ; MVT VT = ( AS == <NUM_LIT> ) ? <STR_LIT> : <STR_LIT> ; const <ISA_LIT>Subtarget & STI = DAG . getMachineFunction ( ) . getSubtarget < <ISA_LIT>Subtarget > ( ) ; const <ISA_LIT>TargetLowering & TLI = * STI . getTargetLowering ( ) ; const TargetRegisterClass * RC = TLI . getRegClassFor ( VT ) ; MachineFunction & MF = DAG . getMachineFunction ( ) ; uint64_t Val = V -> getZExtValue ( ) & <NUM_LIT> ; assert ( V -> getZExtValue ( ) == Val && <STR_LIT> ) ; Val = ( Val << <NUM_LIT> ) | Val ; Val = ( Val << <NUM_LIT> ) | Val ; unsigned ValueReg = MF . getRegInfo ( )


<s> SDValue <ISA_LIT>TargetLowering :: LowerFormalArguments ( SDValue Chain , CallingConv :: ID CallConv , bool isVarArg , const SmallVectorImpl < <STR_LIT> > & Ins , DebugLoc dl , SelectionDAG & DAG , SmallVectorImpl < SDValue > & InVals ) const { return


<s> static_assert ( B > <NUM_LIT> , <STR_LIT> ) ; Inst . addOperand ( MCOperand :: createImm ( SignExtend32 < B > ( maskTrailingOnes < decltype ( InsnS ) > ( B ) & InsnS ) ) ) ; return MCDisassembler ::


<s> if ( Kind == <STR_LIT> ) { std :: string ValueStr = utostr ( Value ) ; assert ( ( ( ValueStr . size ( ) + <NUM_LIT> + Offset ) <= Data . size ( ) ) && <STR_LIT> ) ; std :: copy ( ValueStr . begin ( ) , ValueStr . end ( ) , Data . begin ( ) + Offset ) ; Data [ Offset + ValueStr . size ( ) ] = '\0' ; return ; } unsigned int Bytes = <NUM_LIT> ; switch ( Kind ) { case <STR_LIT> : case <STR_LIT> : case


<s> unsigned getMaskedMemoryOpCost ( unsigned Opcode , Type * Src

, unsigned Alignment , unsigned AddressSpace ) {


<s> SMLoc getStartLoc ( ) const override { return Start


<s> <ISA_LIT>RegBankCombiner :: <ISA_LIT>RegBankCombiner ( bool IsOptNone ) : MachineFunctionPass ( ID ) , IsOptNone ( IsOptNone ) { initialize<ISA_LIT>RegBankCombinerPass ( * PassRegistry :: getPassRegistry (