<s> static bool nds32_hard_regno_mode_ok ( unsigned int regno , machine_mode mode ) { if ( regno > FIRST_PSEUDO_REGISTER ) return true ; if ( ( TARGET_FPU_SINGLE || TARGET_FPU_DOUBLE ) && NDS32_IS_FPR_REGNUM ( regno ) ) { if ( NDS32_IS_EXT_FPR_REGNUM ( regno ) ) return ( NDS32_FPR_REGNO_OK_FOR_DOUBLE ( regno ) && ( mode == DFmode ) ) ; else if ( mode == SFmode || mode == SImode ) return NDS32_FPR_REGNO_OK_FOR_SINGLE ( regno ) ; else if ( mode == DFmode ) return NDS32_FPR_REGNO_OK_FOR_DOUBLE ( regno ) ; return false ; } if ( regno <= NDS32_LAST_GPR_REGNUM ) return ( targetm . hard_regno_nregs ( regno , mode ) == <NUM_LIT>


<s> void setValid ( bool val ) { valid =


<s> return new <ISA_LIT>65816PassConfig ( this ,


<s> unsigned VReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( ! TargetRegisterInfo :: isVirtualRegister ( VReg ) ) return false ; MachineInstr * DefMI = MRI -> getVRegDef ( VReg ) ; while ( DefMI -> isCopy ( ) ) { unsigned CopyVReg = DefMI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( ! MRI -> hasOneNonDBGUse ( CopyVReg ) ) return false ; if ( ! MRI -> hasOneDef ( CopyVReg ) ) return false ; DefMI = MRI -> getVRegDef ( CopyVReg ) ; } switch ( DefMI -> getOpcode ( ) ) { default : return false ; case <STR_LIT> : case <STR_LIT> : { if ( IsTestAndBranch ) return false ; if ( DefMI -> getParent ( ) != MBB ) return false ; if ( ! MRI -> hasOneNonDBGUse ( VReg ) ) return false ; uint64_t Mask = <STR_LIT> ( DefMI -> getOperand ( <NUM_LIT> ) . getImm ( ) , ( DefMI -> getOpcode ( ) == <STR_LIT> ) ? <NUM_LIT> : <NUM_LIT> ) ; if ( ! isPowerOf2_64 ( Mask ) ) return false ; MachineOperand & MO = DefMI -> getOperand ( <NUM_LIT> ) ; unsigned NewReg = MO . getReg ( ) ; if ( ! TargetRegisterInfo :: isVirtualRegister ( NewReg ) ) return false ; assert ( ! MRI -> def_empty ( NewReg ) && <STR_LIT> ) ; MachineBasicBlock & RefToMBB = * MBB ; MachineBasicBlock * TBB = MI -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; DebugLoc DL = MI -> getDebugLoc ( ) ; unsigned Imm = Log2_64 ( Mask ) ; unsigned Opc = ( Imm < <NUM_LIT> ) ? ( IsNegativeBranch ? <STR_LIT> : <STR_LIT> ) : ( IsNegativeBranch ? <STR_LIT> : <STR_LIT> ) ; BuildMI ( RefToMBB , MI , DL , get ( Opc ) ) . addReg ( NewReg ) . addImm ( Imm ) . addMBB ( TBB ) ; MI -> eraseFromParent ( ) ; return true ; } case <STR_LIT> : case <STR_LIT> : { if ( ! ( DefMI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> && DefMI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) && ! ( DefMI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> && DefMI -> getOperand ( <NUM_LIT>

) . getReg ( ) == <STR_LIT> ) ) return false ;


<s> EVT WidenedVT = EVT :: getVectorVT ( * DAG . getContext ( ) , VT . getVectorElementType ( ) , <NUM_LIT> ) ; auto WidenedOp = DAG . getMemIntrinsicNode ( <STR_LIT> , DL , DAG . getVTList ( WidenedVT ) , Ops , WidenedVT , MF . getMachineMemOperand ( MMO , <NUM_LIT> , WidenedVT . getStoreSize ( ) ) ) ; auto Subvector = DAG . getNode ( <STR_LIT> , DL , VT , WidenedOp , DAG . getVectorIdxConstant ( <NUM_LIT> , DL ) ) ; return Subvector ; } return DAG . getMemIntrinsicNode ( <STR_LIT> , DL , DAG . getVTList ( VT ) , Ops , VT , MMO ) ; } SmallVector < SDValue , <NUM_LIT> > Loads ; unsigned NumLoads = <NUM_LIT> ; MVT LoadVT = VT . getSimpleVT ( ) ; unsigned NumElts = LoadVT . isVector ( ) ? LoadVT . getVectorNumElements ( ) : <NUM_LIT> ; assert ( ( LoadVT . getScalarType ( ) == <STR_LIT> || LoadVT . getScalarType ( ) == <STR_LIT> ) ) ; if ( NumElts == <NUM_LIT> || NumElts == <NUM_LIT> ) { NumLoads = NumElts / <NUM_LIT>


<s> if ( Memory . OffsetRegNum ) return false ; if ( ! Memory . OffsetImm ) return true ; if ( const auto * CE = dyn_cast < MCConstantExpr > ( Memory . OffsetImm ) ) { int64_t Val = CE -> getValue ( ) ; return ( Val >= - <NUM_LIT> && Val <= <NUM_LIT> && ( ( Val & <NUM_LIT> ) == <NUM_LIT> ) ) || Val == std ::


<s> const static MCFixupKindInfo Infos [ <STR_LIT> ] = { { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , } ; if ( Kind < FirstTargetFixupKind ) return MCAsmBackend :: getFixupKindInfo ( Kind ) ; assert ( unsigned ( Kind - FirstTargetFixupKind ) <


<s> F -> insert ( It , sinkMBB ) ; sinkMBB -> splice ( sinkMBB -> begin ( ) , BB , llvm :: next ( MachineBasicBlock :: iterator ( MI ) ) , BB -> end ( ) ) ; sinkMBB -> transferSuccessorsAndUpdatePHIs ( BB ) ; BB -> addSuccessor ( copy0MBB ) ; BB -> addSuccessor ( sinkMBB ) ; BuildMI ( BB , DL , TII -> get ( Opc2 ) ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; BuildMI ( BB , DL , TII -> get ( Opc1 ) )


<s> MCSymbol * <ISA_LIT>AsmPrinter :: Get<ISA_LIT>SJLJEHLabel ( ) const { const DataLayout * DL = TM . getDataLayout ( ) ; SmallString < <NUM_LIT> > Name ; raw_svector_ostream ( Name ) << DL -> getPrivateGlobalPrefix ( ) << <STR_LIT> << getFunctionNumber ( ) ; return OutContext . GetOrCreateSymbol ( Name .


<s> if ( RelocM == Reloc :: PIC_ ) { bool UseGOTOFF = GV -> hasLocalLinkage ( ) || GV -> hasHiddenVisibility ( ) ; <ISA_LIT>ConstantPoolValue * CPV = new <ISA_LIT>ConstantPoolValue ( GV , UseGOTOFF ? <STR_LIT> : <STR_LIT> ) ; SDValue CPAddr = DAG . getTargetConstantPool ( CPV , PtrVT , <NUM_LIT> ) ; CPAddr = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , CPAddr ) ; SDValue Result = DAG . getLoad ( PtrVT , dl , DAG . getEntryNode ( ) , CPAddr , PseudoSourceValue :: getConstantPool ( ) , <NUM_LIT> , false , false , <NUM_LIT> ) ; SDValue Chain = Result . getValue ( <NUM_LIT> ) ; SDValue GOT = DAG . getGLOBAL_OFFSET_TABLE ( PtrVT ) ; Result = DAG . getNode ( <STR_LIT> , dl , PtrVT , Result , GOT ) ; if ( ! UseGOTOFF ) Result = DAG . getLoad ( PtrVT , dl , Chain , Result , PseudoSourceValue :: getGOT ( ) , <NUM_LIT> , false , false , <NUM_LIT> ) ; return Result ; } else { if ( Subtarget -> useMovt ( ) ) { return DAG . getNode ( <STR_LIT> , dl , PtrVT , DAG . getTargetGlobalAddress ( GV , PtrVT


<s> { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } } ; if ( Kind < FirstTargetFixupKind ) return MCAsmBackend :: getFixupKindInfo ( Kind ) ; assert ( unsigned ( Kind - FirstTargetFixupKind ) < getNumFixupKinds (


<s> auto NewReg = createNewIdReg ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) , Opc , MRI , * GR ) . first ; AssignTypeInst . getOperand ( <NUM_LIT> ) . setReg ( NewReg ) ; MI . getOperand ( <NUM_LIT> ) . setReg ( NewReg ) ; MIB . setInsertPt ( * MI . getParent ( ) , ( MI . getNextNode ( ) ? MI . getNextNode ( ) -> getIterator ( ) : MI . getParent ( ) -> end ( ) ) ) ; for ( auto & Op : MI . operands (


<s> insertPass ( & <ISA_LIT>LowerControlFlowID , & <ISA_LIT>FixWWMLivenessID , false ) ; TargetPassConfig :: addOptimizedRegAlloc


<s> if ( ! isITCondCode ( ) ) return false ; <STR_LIT> CC = getCondCode ( ) ; return CC == <STR_LIT> || CC


<s> ConstantSDNode * Offset = dyn_cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ; if ( ! Offset ) break ; SDValue BitsFrom = N -> getOperand ( <NUM_LIT> ) ; uint32_t OffsetVal = Offset -> getZExtValue ( ) & <NUM_LIT> ; bool Signed = N -> getOpcode ( ) == <STR_LIT> ; if ( OffsetVal == <NUM_LIT> ) { unsigned SignBits = Signed ? ( <NUM_LIT> - WidthVal + <NUM_LIT> ) : ( <NUM_LIT> - WidthVal ) ; unsigned OpSignBits = DAG . ComputeNumSignBits ( BitsFrom ) ; if ( OpSignBits >= SignBits ) return BitsFrom ; EVT SmallVT = EVT :: getIntegerVT ( * DAG . getContext ( ) , WidthVal ) ; if ( Signed ) { return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , BitsFrom , DAG . getValueType ( SmallVT ) ) ; } return DAG . getZeroExtendInReg ( BitsFrom , DL , SmallVT ) ; } if ( ConstantSDNode * CVal = dyn_cast < ConstantSDNode > ( BitsFrom ) ) { if ( Signed ) { return constantFoldBFE < int32_t > ( DAG , CVal -> getSExtValue ( ) , OffsetVal , WidthVal ) ; } return constantFoldBFE < uint32_t > ( DAG , CVal -> getZExtValue ( ) , OffsetVal , WidthVal ) ; } APInt Demanded = APInt :: getBitsSet ( <NUM_LIT> , OffsetVal , OffsetVal + WidthVal ) ; if ( ( OffsetVal + WidthVal ) >= <NUM_LIT> ) { SDValue ShiftVal = DAG . getConstant ( OffsetVal ,


<s> return MatchOperand_Success ; } unsigned Reg = matchRegisterNameAlias ( Name , RegKind :: Matrix ) ; if ( ! Reg ) return MatchOperand_NoMatch ; size_t DotPosition = Name . find ( '.' ) ; assert ( DotPosition != StringRef :: npos && <STR_LIT> ) ; StringRef Head = Name . take_front ( DotPosition ) ; StringRef Tail = Name . drop_front ( DotPosition ) ; StringRef RowOrColumn = Head . take_back ( ) ; MatrixKind Kind = StringSwitch < MatrixKind > ( RowOrColumn ) . Case ( <STR_LIT> , MatrixKind :: Row ) . Case ( <STR_LIT> , MatrixKind :: Col ) . Default ( MatrixKind :: Tile ) ; const auto & KindRes = parseVectorKind ( Tail , RegKind :: Matrix ) ; if ( ! KindRes ) { TokError ( <STR_LIT> ) ; return MatchOperand_ParseFail ; } unsigned ElementWidth =


<s> return ! RC . isBottom ( ) ; } bool Eval = evaluate ( R , L , RC ) ; return Eval && ! RC


<s> bool <ISA_LIT>InstrInfo :: getMemOperandWithOffset ( const MachineInstr & LdSt , const MachineOperand * & BaseOp , int64_t & Offset , const TargetRegisterInfo * TRI ) const { unsigned Width ; return getMemOperandWithOffsetWidth ( LdSt , BaseOp , Offset ,


<s> TYPE_PRECISION ( fpreg_type ) = <NUM_LIT> ; layout_type ( fpreg_type ) ; ( * lang_hooks . types . register_builtin_type ) ( fpreg_type , <STR_LIT> ) ; if ( float64x_type_node != NULL_TREE && TYPE_MODE ( float64x_type_node ) == XFmode ) float80_type = float64x_type_node ; else { float80_type = make_node ( REAL_TYPE ) ; TYPE_PRECISION ( float80_type ) = <NUM_LIT> ; layout_type ( float80_type ) ; } ( * lang_hooks . types . register_builtin_type ) ( float80_type , <STR_LIT> ) ; if ( ! TARGET_HPUX ) { tree ftype ; tree const_string_type = build_pointer_type ( build_qualified_type ( char_type_node , TYPE_QUAL_CONST ) ) ; ( * lang_hooks . types . register_builtin_type ) ( float128_type_node , <STR_LIT> ) ; ftype = build_function_type_list ( float128_type_node , NULL_TREE ) ; decl = add_builtin_function ( <STR_LIT> , ftype , IA64_BUILTIN_INFQ , BUILT_IN_MD , NULL , NULL_TREE ) ; ia64_builtins [ IA64_BUILTIN_INFQ ] = decl ; decl = add_builtin_function ( <STR_LIT> , ftype , IA64_BUILTIN_HUGE_VALQ , BUILT_IN_MD ,


<s> for ( ; R . isValid ( ) ; ++ R ) Reserved


<s> APFloat C2Val ( APFloat :: IEEEdouble ( ) , <STR_LIT> ) ; auto C1 = MIRBuilder . buildFConstant ( Ty , C1Val ) ; auto CopySign = MIRBuilder . buildFCopysign ( Ty , C1 , Src ) ; auto Tmp1 = MIRBuilder . buildFAdd ( Ty , Src , CopySign ) ; auto Tmp2 = MIRBuilder . buildFSub ( Ty , Tmp1 , CopySign ) ; auto C2 = MIRBuilder . buildFConstant ( Ty , C2Val ) ; auto Fabs = MIRBuilder . buildFAbs ( Ty , Src ) ; auto Cond = MIRBuilder . buildFCmp ( CmpInst :: FCMP_OGT , LLT :: scalar ( <NUM_LIT> ) , Fabs , C2 ) ; MIRBuilder . buildSelect ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) , Cond , Src , Tmp2 ) ; return true


<s> return MaskBit ? <STR_LIT> ( ITState . Cond


<s> i != values . end ( ) ; ++ i ) if ( i -> value == NULL_RTX || ! rtx_equal_p ( last_value , i -> value ) ) return false ; return true


<s> int64_t Val = Memory . OffsetImm -> getValue ( ) ; return ( Val >= - <NUM_LIT> && Val <= <NUM_LIT> && ( Val & <NUM_LIT> )


<s> const Triple & TheTriple = STI . getTargetTriple ( ) ; if ( TheTriple . isOSBinFormatMachO ( ) ) { return new Darwin<ISA_LIT>AsmBackend ( T , TheTriple , MRI ) ; } if ( TheTriple . isOSBinFormatCOFF ( ) ) return new COFF<ISA_LIT>AsmBackend ( T , TheTriple ) ; assert ( TheTriple . isOSBinFormatELF ( ) && <STR_LIT> ) ; uint8_t OSABI = MCELFObjectTargetWriter :: getOSABI ( TheTriple . getOS ( ) ) ; bool IsILP32 = Options .


<s> void <ISA_LIT>AsmParser :: convertToMapAndConstraints ( unsigned Kind , const OperandVector & Operands ) { dbgs ( ) << <STR_LIT> << Kind <<


<s> inline bool isImmUnsignedi8Value ( uint64_t Value ) { return ( ( Value <= <NUM_LIT> ) || ( <NUM_LIT> <= Value


<s> insn = emit_move_insn ( mem , gen_rtx_REG ( DImode , regno ) ) ; fp_offset -= <NUM_LIT> ; } } } } if ( cfun -> calls_alloca ) { insn = emit_move_insn ( stack_pointer_rtx , hard_frame_pointer_rtx ) ; if ( size > <NUM_LIT> ) { insn = emit_insn ( gen_rtx_SET ( stack_pointer_rtx , gen_rtx_PLUS ( Pmode

, stack_pointer_rtx , GEN_INT ( - size ) ) ) ) ;


<s> bool <ISA_LIT>AsmPrinter :: PrintAsmMemoryOperand ( const MachineInstr * MI , unsigned OpNum , unsigned AsmVariant , const char * ExtraCode , raw_ostream & O ) { const MachineOperand & MO = MI


<s> Inst . addOperand ( MCOperand :: createImm ( CE -> getValue ( )


<s> rtx hi ; rtx lo ; rtx addr ; const char * load_string ; int r ; if ( GET_CODE ( mem ) == FLOAT_EXTEND || GET_CODE ( mem ) == ZERO_EXTEND ) { mem = XEXP ( mem , <NUM_LIT> ) ; mode = GET_MODE ( mem ) ; } if ( GET_CODE ( reg ) == SUBREG ) { gcc_assert ( SUBREG_BYTE ( reg ) == <NUM_LIT> ) ; reg = SUBREG_REG ( reg ) ; } if ( ! REG_P ( reg ) ) fatal_insn ( <STR_LIT> , reg ) ; r = REGNO ( reg ) ; if ( FP_REGNO_P ( r ) ) { if ( mode == SFmode ) load_string = <STR_LIT> ; else if ( mode == DFmode || mode == DImode ) load_string = <STR_LIT> ; else gcc_unreachable ( ) ; } else if ( ALTIVEC_REGNO_P ( r ) && TARGET_P9_VECTOR ) { if ( mode == SFmode ) load_string = <STR_LIT> ; else if ( mode == DFmode || mode == DImode ) load_string = <STR_LIT> ; else gcc_unreachable ( ) ; } else if ( INT_REGNO_P ( r ) ) { switch ( mode ) { case E_QImode : load_string = <STR_LIT> ; break ; case E_HImode : load_string = <STR_LIT> ; break ; case E_SImode : case E_SFmode


<s> for ( BBPredicates :: iterator I = Preds . begin ( ) , E = Preds . end ( ) ; I != E ; ++ I ) { if ( I -> second != BoolTrue ) return false ; if ( ! Dominated && DT -> dominates ( I -> first , PrevNode -> getEntry ( ) ) ) Dominated = true ; } return Dominated


<s> default : llvm_unreachable ( <STR_LIT> ) ; case FK_NONE : return <NUM_LIT> ; case FK_Data_1 : return <NUM_LIT> ; case FK_Data_2 : return <NUM_LIT> ; case FK_Data_4 : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> next_tail = NEXT_INSN ( tail ) ; for ( insn = head ; insn != next_tail ; insn = NEXT_INSN ( insn ) ) { if ( ! INSN_P ( insn ) ) continue ; if ( mode == SFmode ) INSN_REGMODE_WEIGHT ( insn , mode ) = find_insn_regmode_weight ( insn ,

mode ) + <NUM_LIT> * find_insn_regmode_weight ( insn , DFmode ) ;


<s> return Features . test ( FeatureCodeObjectV3 )


<s> return ( Val == <NUM_LIT> || Val == <NUM_LIT> || Val


<s> status = DecodeI64RegisterClass ( MI , sz , Address , Decoder ) ; if ( status != MCDisassembler :: Success ) return status ; } else { MI . addOperand ( MCOperand :: createImm ( <NUM_LIT> ) ) ; } MI . addOperand ( MCOperand :: createImm ( simm32


<s> return TM -> Options . UseSoftFloat && !


<s> Inst . setOpcode ( <STR_LIT> ) ; Inst . addOperand ( MCOperand :: CreateReg ( <STR_LIT> ) ) ; const MCExpr * Disp = MCConstantExpr :: Create ( Offset , Ctx ) ; std :: unique_ptr < <ISA_LIT>Operand > Op ( <STR_LIT> ( <NUM_LIT> , Disp , <STR_LIT> , <NUM_LIT> , <NUM_LIT> , SMLoc ( ) , SMLoc ( ) ) ) ; Op -> addMemOperands ( Inst ,


<s> <ISA_LIT>RegisterInfo :: <ISA_LIT>RegisterInfo ( const Triple & TT ) : <ISA_LIT>GenRegisterInfo ( ( TT . isArch64Bit ( ) ? <STR_LIT> : <STR_LIT> ) , <ISA_LIT>_MC :: getDwarfRegFlavour ( TT , false ) , <ISA_LIT>_MC :: getDwarfRegFlavour ( TT , true ) , ( TT . isArch64Bit ( ) ? <STR_LIT> : <STR_LIT> ) ) { <ISA_LIT>_MC :: initLLVMToSEHAndCVRegMapping ( this ) ; Is64Bit = TT . isArch64Bit ( ) ; IsWin64 = Is64Bit && TT . isOSWindows ( ) ; if ( Is64Bit ) { SlotSize = <NUM_LIT> ; bool Use64BitReg = TT . getEnvironment ( ) !=


<s> static DecodeStatus DecodeT2SOImm ( MCInst & Inst , unsigned Val , uint64_t Address , const MCDisassembler * Decoder ) { unsigned ctrl = fieldFromInstruction ( Val , <NUM_LIT> , <NUM_LIT> ) ; if ( ctrl == <NUM_LIT> ) { unsigned byte = fieldFromInstruction ( Val , <NUM_LIT> , <NUM_LIT> ) ; unsigned imm = fieldFromInstruction ( Val , <NUM_LIT> , <NUM_LIT> ) ; switch ( byte ) { case <NUM_LIT> : Inst . addOperand ( MCOperand :: createImm ( imm ) ) ; break ; case <NUM_LIT> : Inst . addOperand ( MCOperand :: createImm ( ( imm << <NUM_LIT> ) | imm ) ) ; break ; case <NUM_LIT> : Inst . addOperand ( MCOperand :: createImm ( ( imm << <NUM_LIT> ) | ( imm << <NUM_LIT> ) ) ) ; break ; case <NUM_LIT> : Inst . addOperand ( MCOperand :: createImm ( ( imm << <NUM_LIT> ) | ( imm << <NUM_LIT> ) | ( imm << <NUM_LIT> ) | imm ) ) ; break ; } } else { unsigned unrot = fieldFromInstruction ( Val , <NUM_LIT>


<s> <STR_LIT> AM = LdSt -> getAddressingMode ( ) ; if ( AM != <STR_LIT> ) return false ; Offset = N ; if ( ConstantSDNode * NC = dyn_cast < ConstantSDNode


<s> SDNode * Mul = CurDAG -> getMachineNode ( Opc , DL , <STR_LIT> , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) ) ; SDValue InFlag = SDValue ( Mul , <NUM_LIT> ) ; if ( HasLo ) { unsigned Opcode = <STR_LIT> ; Lo = CurDAG -> getMachineNode ( Opcode , DL , Ty , <STR_LIT> , InFlag ) ; InFlag = SDValue ( Lo , <NUM_LIT> ) ; } if ( HasHi ) { unsigned Opcode = <STR_LIT> ; Hi = CurDAG -> getMachineNode ( Opcode , DL , Ty ,


<s> if ( CC == CallingConv :: GHC ) return NULL ; return ( STI . isTargetIOS ( ) && ! STI . isAAPCS_ABI (

) ) ? CSR_iOS_ThisReturn_RegMask : CSR_AAPCS_ThisReturn_RegMask ;


<s> case <STR_LIT> : break ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case


<s> CSOpcode = TII -> getOpcodeForOffset ( CSOpcode , Disp ) ; assert ( LOpcode && CSOpcode && <STR_LIT> ) ; unsigned OrigVal = MRI . createVirtualRegister ( RC ) ; unsigned OldVal = MRI . createVirtualRegister ( RC ) ; unsigned NewVal = ( BinOpcode || IsSubWord ? MRI . createVirtualRegister ( RC ) : Src2 . getReg ( ) ) ; unsigned RotatedOldVal = ( IsSubWord ? MRI . createVirtualRegister ( RC ) : OldVal ) ; unsigned RotatedNewVal = ( IsSubWord ? MRI . createVirtualRegister ( RC ) : NewVal ) ; MachineBasicBlock * StartMBB = MBB ; MachineBasicBlock * DoneMBB = splitBlockBefore ( MI , MBB ) ; MachineBasicBlock * LoopMBB = emitBlockAfter ( StartMBB ) ; MBB = StartMBB ; BuildMI ( MBB , DL , TII -> get ( LOpcode ) , OrigVal ) . addOperand ( Base ) . addImm ( Disp ) . addReg ( <NUM_LIT> ) ; MBB -> addSuccessor ( LoopMBB ) ; MBB = LoopMBB ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) , OldVal ) . addReg ( OrigVal ) . addMBB ( StartMBB ) . addReg ( Dest ) . addMBB ( LoopMBB ) ; if ( IsSubWord ) BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) , RotatedOldVal ) . addReg ( OldVal ) . addReg ( BitShift ) . addImm ( <NUM_LIT> ) ; if ( Invert ) { unsigned Tmp = MRI . createVirtualRegister ( RC ) ; BuildMI ( MBB , DL , TII -> get ( BinOpcode ) , Tmp ) . addReg ( RotatedOldVal ) . addOperand ( Src2 ) ; if ( BitSize <= <NUM_LIT> ) BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) , RotatedNewVal ) . addReg ( Tmp ) . addImm ( - <NUM_LIT> << ( <NUM_LIT> - BitSize ) ) ; else { unsigned Tmp2 = MRI . createVirtualRegister ( RC ) ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) , Tmp2 ) . addReg ( Tmp ) ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) , RotatedNewVal ) . addReg ( Tmp2


<s> bool <ISA_LIT>TargetLowering :: allowsMisalignedMemoryAccesses ( EVT VT , unsigned AddrSpace , unsigned Alignment , MachineMemOperand :: Flags Flags , bool * Fast ) const { MVT SVT = VT . getSimpleVT ( ) ; if ( Subtarget . isHVXVectorType ( SVT , true ) ) return allowsHvxMisalignedMemoryAccesses (


<s> TotalSGPRCountPer<ISA_LIT>MD = <NUM_LIT> ; AddressableSGPRCount = <NUM_LIT> ; SGPRUsageAlignment = <NUM_LIT> ; ReservedSGPRCount = <NUM_LIT> ; } else { TotalSGPRCountPer<ISA_LIT>MD = <NUM_LIT> ; AddressableSGPRCount = <NUM_LIT> ; SGPRUsageAlignment = <NUM_LIT> ; ReservedSGPRCount = <NUM_LIT> ; } unsigned MaxSGPRCount = ( TotalSGPRCountPer<ISA_LIT>MD / MaxWaveCountPer<ISA_LIT>MD


<s> else if ( IDVal == <STR_LIT> ) parseDirectiveUnreq ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) parseDirectiveFnEnd ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) parseDirectiveCantUnwind ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) parseDirectivePersonality ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) parseDirectiveHandlerData ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) parseDirectiveSetFP ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) parseDirectivePad ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) parseDirectiveRegSave ( DirectiveID . getLoc ( ) , false ) ; else if ( IDVal == <STR_LIT> ) parseDirectiveRegSave ( DirectiveID . getLoc ( ) , true ) ; else if ( IDVal == <STR_LIT> || IDVal == <STR_LIT> ) parseDirectiveLtorg ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) parseDirectiveEven ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) parseDirectivePersonalityIndex ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) parseDirectiveUnwindRaw ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) parseDirectiveMovSP ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) parseDirectiveArchExtension ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) return parseDirectiveAlign (


<s> if ( Inst . getOpcode ( ) == <STR_LIT> && Inst . getOperand ( <NUM_LIT>

) . getImm ( ) == <STR_LIT> ) return false ;


<s> static bool isLowerSaturate ( const SDValue LHS , const SDValue RHS , const SDValue TrueVal , const SDValue FalseVal , const <STR_LIT> CC , const SDValue K ) { return ( isGTorGE ( CC ) && ( ( K == LHS && K == TrueVal ) || ( K == RHS && K == FalseVal ) ) ) || ( isLTorLE ( CC ) && ( ( K == RHS && K == TrueVal ) || ( K ==


<s> pcmpgth_s ( int16x4_t s , int16x4_t t ) { return __builtin_loongson_pcmpgth_s ( s ,


<s> DEBUG ( dbgs ( ) << <STR_LIT> ) ; MachineBasicBlock :: iterator MBBI = MBB . getLastNonDebugInstr ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const <ISA_LIT>InstrInfo & TII = * static_cast < const <ISA_LIT>InstrInfo * > ( MF . getTarget ( ) . getInstrInfo ( ) ) ; DebugLoc dl = MBBI -> getDebugLoc (


<s> if ( SPR_P ( REGNO ( reg ) ) ) { rtx temp = gen_rtx_REG ( mode , TEMP_REGNO ) ; emit_insn ( gen_rtx_SET ( VOIDmode , temp , reg ) ) ; frv_frame_insn ( gen_rtx_SET ( Pmode , mem , temp ) , frv_dwarf_store ( reg , stack_offset ) ) ; } else if ( GET_MODE ( reg ) == DImode ) { rtx reg1 = gen_rtx_REG ( SImode , REGNO ( reg ) ) ; rtx reg2 = gen_rtx_REG ( SImode , REGNO ( reg ) + <NUM_LIT> ) ; rtx set1 = frv_dwarf_store ( reg1 , stack_offset ) ; rtx set2 = frv_dwarf_store ( reg2 , stack_offset + <NUM_LIT> ) ; frv_frame_insn ( gen_rtx_SET ( Pmode , mem , reg ) , gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( <NUM_LIT> , set1 , set2 ) ) ) ; } else frv_frame_insn ( gen_rtx_SET ( Pmode , mem , reg


<s> arm_simd_types [ Uint8x16_t ] . eltype = unsigned_intQI_type_node ; arm_simd_types [ Uint16x4_t ] . eltype = unsigned_intHI_type_node ; arm_simd_types [ Uint16x8_t ] . eltype = unsigned_intHI_type_node ; arm_simd_types [ Uint32x2_t ] . eltype = unsigned_intSI_type_node ; arm_simd_types [ Uint32x4_t ] . eltype = unsigned_intSI_type_node ; arm_simd_types [ Uint64x2_t ] . eltype = unsigned_intDI_type_node ; arm_simd_types [ Poly8x8_t ] . eltype = arm_simd_polyQI_type_node ; arm_simd_types [ Poly8x16_t ] . eltype = arm_simd_polyQI_type_node ; arm_simd_types [ Poly16x4_t ] . eltype = arm_simd_polyHI_type_node ; arm_simd_types [ Poly16x8_t ] . eltype = arm_simd_polyHI_type_node ; arm_simd_types [ Float16x4_t ] . eltype = arm_fp16_type_node ; arm_simd_types [ Float16x8_t ] . eltype = arm_fp16_type_node ; arm_simd_types [ Float32x2_t ] . eltype = float_type_node ; arm_simd_types [ Float32x4_t ] . eltype = float_type_node ; for ( i = <NUM_LIT> ; i < nelts ; i ++ ) { tree eltype = arm_simd_types [ i ] . eltype ; machine_mode mode = arm_simd_types [ i ] . mode ; if ( arm_simd_types [ i ] . itype == NULL ) arm_simd_types [ i ] . itype = build_distinct_type_copy ( build_vector_type ( eltype , GET_MODE_NUNITS ( mode ) ) ) ; tdecl = add_builtin_type ( arm_simd_types [ i ] . name , arm_simd_types [ i ] . itype ) ; TYPE_NAME ( arm_simd_types [ i ] . itype ) = tdecl ; SET_TYPE_STRUCTURAL_EQUALITY ( arm_simd_types [ i ] . itype ) ; } make_signed_type ( GET_MODE_PRECISION ( mode ) ) ; arm_simd_intOI_type_node = AARCH_BUILD_SIGNED_TYPE ( OImode ) ; arm_simd_intEI_type_node = AARCH_BUILD_SIGNED_TYPE ( EImode ) ; arm_simd_intCI_type_node = AARCH_BUILD_SIGNED_TYPE ( CImode ) ; arm_simd_intXI_type_node = AARCH_BUILD_SIGNED_TYPE ( XImode ) ; tdecl = add_builtin_type ( <STR_LIT> , arm_simd_intEI_type_node ) ; TYPE_NAME ( arm_simd_intEI_type_node ) = tdecl ; tdecl = add_builtin_type ( <STR_LIT> , arm_simd_intOI_type_node ) ; TYPE_NAME ( arm_simd_intOI_type_node ) = tdecl ; tdecl = add_builtin_type ( <STR_LIT> , arm_simd_intCI_type_node


<s> return new MandarinPassConfig ( this ,


<s> bool SuppressSTP = false ; unsigned PrevBaseReg = <NUM_LIT> ; for ( auto & MI : MBB ) { if ( ! isNarrowFPStore ( MI ) ) continue ; unsigned BaseReg ; int64_t Offset ; if ( TII -> getMemOpBaseRegImmOfs ( & MI , BaseReg , Offset , TRI ) ) { if ( PrevBaseReg == BaseReg ) { if ( ! SuppressSTP && shouldAddSTPToBlock ( MI . getParent ( ) ) ) break ; DEBUG ( dbgs ( ) << <STR_LIT> << MI << <STR_LIT> ) ; SuppressSTP = true ; TII -> suppressLdStPair ( & MI ) ; } PrevBaseReg = BaseReg ; } else PrevBaseReg = <NUM_LIT> ; } } return false


<s> static MachineInstr * genFusedMultiply ( MachineFunction & MF , MachineRegisterInfo & MRI , const TargetInstrInfo * TII , MachineInstr & Root , SmallVectorImpl < MachineInstr * > & InsInstrs , unsigned IdxMulOpd , unsigned MaddOpc , const TargetRegisterClass * RC , FMAInstKind kind = FMAInstKind :: Default , const unsigned * ReplacedAddend = nullptr ) { assert ( IdxMulOpd == <NUM_LIT> || IdxMulOpd == <NUM_LIT> ) ; unsigned IdxOtherOpd = IdxMulOpd == <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ; MachineInstr * MUL = MRI . getUniqueVRegDef ( Root . getOperand ( IdxMulOpd ) . getReg ( ) ) ; unsigned ResultReg = Root . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned SrcReg0 = MUL -> getOperand ( <NUM_LIT> ) . getReg ( ) ; bool Src0IsKill = MUL -> getOperand ( <NUM_LIT> ) . isKill ( ) ; unsigned SrcReg1 = MUL -> getOperand ( <NUM_LIT> ) . getReg ( ) ; bool Src1IsKill = MUL -> getOperand ( <NUM_LIT> ) . isKill ( ) ; unsigned SrcReg2 ; bool Src2IsKill ; if ( ReplacedAddend ) { SrcReg2 = * ReplacedAddend ; Src2IsKill = true ; } else { SrcReg2 = Root . getOperand ( IdxOtherOpd ) . getReg ( ) ; Src2IsKill = Root . getOperand ( IdxOtherOpd ) . isKill ( ) ; } if ( TargetRegisterInfo :: isVirtualRegister ( ResultReg ) ) MRI . constrainRegClass ( ResultReg , RC ) ; if ( TargetRegisterInfo :: isVirtualRegister ( SrcReg0 ) ) MRI . constrainRegClass ( SrcReg0 , RC ) ; if ( TargetRegisterInfo :: isVirtualRegister ( SrcReg1 ) ) MRI . constrainRegClass ( SrcReg1 , RC ) ; if ( TargetRegisterInfo :: isVirtualRegister ( SrcReg2 ) ) MRI . constrainRegClass ( SrcReg2 , RC ) ; MachineInstrBuilder MIB ; if ( kind == FMAInstKind :: Default ) MIB = BuildMI ( MF , Root . getDebugLoc ( ) , TII -> get ( MaddOpc ) , ResultReg ) . addReg ( SrcReg0 , getKillRegState ( Src0IsKill ) ) .

addReg ( SrcReg1 , getKillRegState ( Src1IsKill ) ) . addReg ( SrcReg2 , getKillRegState ( Src2IsKill ) ) ;


<s> void <ISA_LIT>CCState :: PreAnalyzeFormalArgumentsForF128 ( const SmallVectorImpl < <STR_LIT> > & Ins ) { const MachineFunction & MF = getMachineFunction ( ) ; for ( unsigned i = <NUM_LIT> ; i < Ins . size ( ) ; ++ i ) { Function :: const_arg_iterator FuncArg = MF . getFunction ( ) -> arg_begin ( ) ; if ( Ins [ i ] . Flags . isSRet ( ) ) { OriginalArgWasF128 . push_back ( false ) ; OriginalArgWasFloat . push_back ( false ) ; continue ; } assert ( Ins [ i ] . getOrigArgIndex ( ) < MF . getFunction ( ) -> arg_size ( ) ) ; std :: advance ( FuncArg , Ins [ i ] . getOrigArgIndex ( ) ) ; OriginalArgWasF128 . push_back ( originalTypeIsF128 ( FuncArg -> getType ( ) , nullptr ) ) ; OriginalArgWasFloat . push_back ( FuncArg -> getType ( ) ->


<s> inline int vec_all_gt ( vector float a1 ,


<s> do -- MBBI ; while ( MBBI != MBB . begin ( ) && isCSRestore ( MBBI , CSRegs ) ) ; if ( ! isCSRestore ( MBBI , CSRegs ) ) ++ MBBI ; } NumBytes -= ( AFI -> getGPRCalleeSavedArea1Size ( ) + AFI -> getGPRCalleeSavedArea2Size ( ) + AFI -> getDPRCalleeSavedAreaSize ( ) + ArgRegsSaveSize ) ; if ( AFI -> shouldRestoreSPFromFP ( ) ) { NumBytes = AFI -> getFramePtrSpillOffset ( ) - NumBytes ; if ( NumBytes ) { assert ( MF . getRegInfo ( ) . isPhysRegUsed ( <STR_LIT> ) && <STR_LIT> ) ; emitThumbRegPlusImmediate ( MBB , MBBI , dl , <STR_LIT> , FramePtr , - NumBytes , TII , * RegInfo ) ; AddDefaultPred ( BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) ) ; } else AddDefaultPred ( BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( FramePtr ) ) ; } else { if ( MBBI -> getOpcode ( ) == <STR_LIT> && & MBB . front ( ) != MBBI && std :: prev ( MBBI ) -> getOpcode ( ) == <STR_LIT> ) { MachineBasicBlock :: iterator PMBBI = std :: prev ( MBBI ) ; if ( ! tryFoldSPUpdateIntoPushPop ( STI , MF , PMBBI , NumBytes ) ) emitSPUpdate ( MBB , PMBBI , TII , dl , * RegInfo , NumBytes ) ; } else if ( ! tryFoldSPUpdateIntoPushPop ( STI , MF , MBBI , NumBytes ) ) emitSPUpdate ( MBB , MBBI , TII , dl , * RegInfo , NumBytes ) ; } } if ( ArgRegsSaveSize ) { MBBI = MBB .


<s> BTFTypeStruct :: BTFTypeStruct ( const DICompositeType * STy , bool IsStruct , bool HasBitField , uint32_t Vlen ) : STy ( STy ) , HasBitField ( HasBitField ) { Kind = IsStruct ? <STR_LIT> : <STR_LIT> ; BTFType . Size = roundupToBytes ( STy -> getSizeInBits ( ) ) ; BTFType . Info = ( HasBitField << <NUM_LIT> ) | ( Kind << <NUM_LIT>


<s> Parser . Lex ( ) ; StringRef Arch ; if ( Parser . parseIdentifier ( Arch ) ) return reportParseError ( <STR_LIT> ) ; StringRef ArchFeatureName = StringSwitch < StringRef > ( Arch ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case

( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( <STR_LIT> ) ;


<s> const TargetRegisterInfo * TRI = Subtarget . getRegisterInfo ( ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> ( TRI -> getSubRegIdxSize ( Idx ) ) , DAG . getNode ( <STR_LIT> , DL , Op . getValueType ( ) , Op , DAG . getConstant ( TRI -> getSubRegIdxOffset


<s> unsigned R600InstrInfo :: getIEQOpcode ( ) const { return AMDGPU


<s> Register TmpReg = MRI -> createVirtualRegister ( PS -> RC ) ; BuildMI ( MBB , InsertPt , Loc , TII -> get ( TargetOpcode :: COPY ) , TmpReg ) . addReg ( <STR_LIT> ) ; auto ShiftI = BuildMI ( MBB , InsertPt , Loc , TII -> get ( <STR_LIT> ) , PredStateReg ) . addReg ( TmpReg , RegState :: Kill ) . addImm ( TRI -> getRegSizeInBits ( * PS -> RC ) - <NUM_LIT> ) ; ShiftI -> addRegisterDead ( <STR_LIT> , TRI ) ; ++ NumInstsInserted


<s> OperandMatchResultTy parseGRX32 ( SmallVectorImpl < MCParsedAsmOperand * > &


<s> MachineBasicBlock :: iterator MBBI = MBB . getFirstTerminator ( ) ; DebugLoc dl = MBBI != MBB . end ( ) ? MBBI -> getDebugLoc ( ) : DebugLoc ( ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; const ThumbRegisterInfo * RegInfo = static_cast < const ThumbRegisterInfo * > ( STI . getRegisterInfo ( ) ) ; const Thumb1InstrInfo & TII = * static_cast < const Thumb1InstrInfo * > ( STI . getInstrInfo ( ) ) ; unsigned ArgRegsSaveSize = AFI -> getArgRegsSaveSize ( ) ; int NumBytes = ( int ) MFI . getStackSize ( ) ; assert ( ( unsigned ) NumBytes >= ArgRegsSaveSize && <STR_LIT> ) ; const MCPhysReg * CSRegs = RegInfo -> getCalleeSavedRegs ( & MF ) ; Register FramePtr = RegInfo -> getFrameRegister ( MF ) ; if ( ! AFI -> hasStackFrame ( ) ) { if ( NumBytes - ArgRegsSaveSize != <NUM_LIT> ) emitPrologueEpilogueSPUpdate ( MBB , MBBI , TII , dl , * RegInfo , NumBytes - ArgRegsSaveSize , <STR_LIT> , MachineInstr :: NoFlags ) ; } else { if ( MBBI != MBB . begin ( ) ) { do -- MBBI ; while ( MBBI != MBB . begin ( ) && isCSRestore ( * MBBI , CSRegs ) ) ; if ( ! isCSRestore ( * MBBI , CSRegs ) ) ++ MBBI ; } NumBytes -= ( AFI -> getGPRCalleeSavedArea1Size ( ) + AFI -> getGPRCalleeSavedArea2Size ( ) + AFI -> getDPRCalleeSavedAreaSize ( ) + ArgRegsSaveSize ) ; if ( AFI -> shouldRestoreSPFromFP ( ) ) { NumBytes = AFI -> getFramePtrSpillOffset ( ) - NumBytes ; if ( NumBytes ) { assert ( ! MFI . getPristineRegs ( MF ) . test ( <STR_LIT> ) && <STR_LIT> ) ; emitThumbRegPlusImmediate ( MBB , MBBI , dl , <STR_LIT> , FramePtr , - NumBytes , TII , * RegInfo ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . add ( predOps ( <STR_LIT> ) ) ; } else BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( FramePtr ) . add ( predOps ( <STR_LIT> ) ) ; } else { unsigned ScratchRegister


<s> assert ( ( Cond . size ( ) == <NUM_LIT> || Cond . size ( ) == <NUM_LIT> ) && <STR_LIT> ) ; if ( Cond . empty ( ) ) { assert ( ! FBB && <STR_LIT> ) ; BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addMBB ( TBB ) ; return <NUM_LIT> ; } unsigned Opcode = Cond [ <NUM_LIT>


<s> static SDValue performSUBECombine ( SDNode * N , SelectionDAG & DAG , TargetLowering :: DAGCombinerInfo & DCI , const <ISA_LIT>Subtarget * Subtarget ) { if ( DCI . isBeforeLegalize ( ) ) return SDValue ( ) ; if ( Subtarget -> has<ISA_LIT>32 ( ) && N -> getValueType ( <NUM_LIT> ) == <STR_LIT> && selectMSUB ( N , & DAG ) ) return SDValue


<s> Instr1 . setOpcode ( <STR_LIT> ) ; Instr1 . addOperand ( Target ) ; Instr1 . addOperand ( Base ) ; Instr1 . addOperand ( AdjName ) ; Instr2 . setOpcode ( <STR_LIT> ) ; Instr2 . addOperand ( Target ) ; Instr2 . addOperand ( Base ) ; Instr2 . addOperand ( Name ) ; } break ; } case <STR_LIT> : { MCOperand AdjName = LowerOperand ( UnLoweredName , <NUM_LIT> ) ; Instr1 . setOpcode ( <STR_LIT> ) ; Instr1 . addOperand ( ATReg ) ; Instr1 . addOperand ( Base ) ; Instr1 . addOperand ( AdjName ) ; Instr2 . setOpcode ( <STR_LIT> ) ; Instr2 . addOperand ( Target ) ; Instr2 . addOperand ( Base ) ; Instr2 . addOperand ( Name ) ; Instr3 . setOpcode ( <STR_LIT> ) ; Instr3 . addOperand ( Target ) ; Instr3 . addOperand ( ATReg ) ; Instr3 . addOperand ( MCOperand :: CreateImm ( <NUM_LIT> ) ) ; Instr3 . addOperand ( MCOperand :: CreateImm ( <NUM_LIT> ) ) ; break ; } case <STR_LIT> : { assert ( Base . getReg ( ) != Target . getReg ( ) ) ; TwoInstructions = true ; MCOperand AdjName = LowerOperand ( UnLoweredName , <NUM_LIT> ) ; Instr1 . setOpcode ( <STR_LIT> ) ; Instr1 . addOperand ( Target ) ; Instr1 . addOperand ( Base ) ; Instr1 . addOperand ( AdjName ) ; Instr2 . setOpcode ( <STR_LIT> ) ; Instr2 . addOperand ( Target ) ; Instr2 . addOperand ( Base ) ; Instr2 . addOperand ( Name ) ; break ; } case <STR_LIT> : { MCOperand AdjName = LowerOperand ( UnLoweredName , <NUM_LIT> ) ; Instr1 . setOpcode ( <STR_LIT> ) ; Instr1 . addOperand ( Target ) ; Instr1 . addOperand ( Base ) ; Instr1 . addOperand ( Name ) ; Instr2 . setOpcode ( <STR_LIT> ) ; Instr2 . addOperand ( ATReg ) ; Instr2 . addOperand ( Target ) ; Instr2 . addOperand ( MCOperand :: CreateImm ( <NUM_LIT> ) ) ; Instr3 . setOpcode ( <STR_LIT> ) ; Instr3 . addOperand ( ATReg ) ; Instr3 . addOperand ( Base ) ; Instr3 . addOperand ( AdjName ) ; break ; } default : assert ( <NUM_LIT> && <STR_LIT>


<s> unsigned NumInstr = <NUM_LIT> ; MachineFunction * MF = From -> getParent ( ) ; for ( MachineFunction :: iterator MBBI ( From ) , ToI ( To ) , End = MF -> end ( ) ; MBBI != End && MBBI != ToI ; ++ MBBI ) { MachineBasicBlock & MBB = * MBBI ; for ( MachineBasicBlock :: iterator I = MBB . begin ( ) , E = MBB . end ( ) ; NumInstr < SkipThreshold && I != E ; ++ I ) { if ( opcodeEmitsNoInsts ( I ->


<s> else if ( ! TARGET_MEMPARM && ! type ) { if ( mode == QFmode || mode == HFmode ) reg = c4x_fp_reglist [ cum -> floats ] ; else if ( mode == QImode || mode == Pmode ) reg = c4x_int_reglist [ <NUM_LIT> ] [ cum -> ints ] ; } if ( TARGET_DEBUG ) { fprintf ( stderr , <STR_LIT> , GET_MODE_NAME ( mode ) , named ) ; if ( reg ) fprintf ( stderr , <STR_LIT> , reg_names [ reg ] ) ; else fprintf ( stderr , <STR_LIT> ) ; fprintf ( stderr , <STR_LIT>


<s> operands [ <NUM_LIT> ] = XEXP ( x , <NUM_LIT> ) ; operands [ <NUM_LIT> ] = XEXP ( x , <NUM_LIT> ) ; operands [ <NUM_LIT> ] = x ; return compute_logical_op_length ( GET_MODE ( x ) , AND ,


<s> EVT Ty = Op . getValueType ( ) ; if ( getTargetMachine ( ) . getRelocationModel ( ) != Reloc :: PIC_ && ! IsN64 ) return getAddrNonPIC ( N , Ty , DAG ) ; return getAddrLocal ( N , Ty , DAG , Has<ISA_LIT>64


<s> if ( ! Op0 -> hasOneMemOperand ( ) || ! ( * Op0 -> memoperands_begin ( ) ) -> getValue ( ) || ( * Op0 -> memoperands_begin ( ) ) -> isVolatile ( ) ) return false ; unsigned Align = ( * Op0 -> memoperands_begin ( ) ) -> getAlignment ( ) ; const Function * Func = MF -> getFunction ( ) ; unsigned ReqAlign = STI -> hasV6Ops ( ) ? TD -> getABITypeAlignment ( Type :: getInt64Ty ( Func -> getContext ( ) ) ) : <NUM_LIT> ; if ( Align < ReqAlign ) return false ; int OffImm = getMemoryOpOffset ( Op0 ) ; if ( isT2 ) { int Limit = ( <NUM_LIT> << <NUM_LIT> ) * Scale ; if ( OffImm >= Limit || ( OffImm <= - Limit ) || ( OffImm & ( Scale - <NUM_LIT> ) ) ) return false ; Offset = OffImm ; } else { <STR_LIT> AddSub = <STR_LIT> ; if ( OffImm < <NUM_LIT> ) { AddSub = <STR_LIT> ; OffImm = - OffImm ; } int Limit = ( <NUM_LIT> << <NUM_LIT> ) * Scale ; if ( OffImm >= Limit || ( OffImm & ( Scale - <NUM_LIT> ) ) ) return false ; Offset = <STR_LIT> ( AddSub , OffImm ) ; } EvenReg = Op0 -> getOperand ( <NUM_LIT> ) . getReg ( ) ; OddReg = Op1 -> getOperand ( <NUM_LIT>


<s> static SDValue LowerVAARG ( SDValue Op , SelectionDAG & DAG ) { SDNode * Node = Op . getNode ( ) ; EVT VT = Node -> getValueType ( <NUM_LIT> ) ; SDValue InChain = Node -> getOperand ( <NUM_LIT> ) ; SDValue VAListPtr = Node -> getOperand ( <NUM_LIT> ) ; const Value * SV = cast < SrcValueSDNode > ( Node -> getOperand ( <NUM_LIT> ) ) -> getValue ( ) ; DebugLoc dl = Node -> getDebugLoc ( ) ; SDValue VAList = DAG . getLoad ( <STR_LIT> , dl , InChain , VAListPtr , SV , <NUM_LIT> , false , false , <NUM_LIT> ) ; SDValue NextPtr = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , VAList , DAG .

getConstant ( VT . getSizeInBits ( ) / <NUM_LIT> , <STR_LIT> ) ) ;


<s> void getLiteral ( MachineInstr * MI , std :: vector < int64_t > & Lits ) const { static const unsigned LiteralRegs [ ] = { AMDGPU :: ALU_LITERAL_X , AMDGPU :: ALU_LITERAL_Y , AMDGPU :: ALU_LITERAL_Z , AMDGPU :: ALU_LITERAL_W } ; const SmallVector < std :: pair < MachineOperand * , int64_t > , <NUM_LIT> > Srcs = TII -> getSrcs ( MI ) ; for ( unsigned i = <NUM_LIT> , e = Srcs . size ( ) ; i < e ; ++ i ) { if ( Srcs [ i ] . first -> getReg ( ) != AMDGPU :: ALU_LITERAL_X ) continue ; int64_t Imm = Srcs [ i ] . second ; std :: vector < int64_t > :: iterator It = std :: find ( Lits . begin ( ) , Lits . end ( ) , Imm ) ; if ( It != Lits . end ( ) ) { unsigned Index = It - Lits . begin ( ) ; Srcs [ i ] . first -> setReg ( LiteralRegs [ Index ] ) ; } else { assert ( Lits . size ( ) < <NUM_LIT> && <STR_LIT> ) ; Srcs [ i ] . first -> setReg ( LiteralRegs [ Lits . size ( ) ] ) ; Lits . push_back


<s> MVT <ISA_LIT>TargetLowering :: getScalarShiftAmountTy ( EVT LHSTy ) const { return <STR_LIT>


<s> int arg_offset = <NUM_LIT> ; if ( base -> use_mask_predication_p ( ) ) { if ( use_real_mask_p ( pred ) ) add_input_operand ( arg_offset ++ ) ; else add_all_one_mask_operand ( mask_mode ( ) ) ; } if ( ! function_returns_void_p ( ) && base -> has_merge_operand_p ( ) ) { if ( use_real_merge_p ( pred ) ) add_input_operand ( arg_offset ++ ) ; else add_vundef_operand ( mode ) ; } for ( int argno = arg_offset ; argno < call_expr_nargs ( exp ) ; argno ++ ) add_input_operand ( argno ) ; if ( base -> apply_tail_policy_p ( ) ) add_input_operand ( Pmode , get_tail_policy_for_pred ( pred ) ) ; if ( base -> apply_mask_policy_p ( ) ) add_input_operand ( Pmode , get_mask_policy_for_pred ( pred


<s> static bool pa_function_value_regno_p ( const


<s> for ( const unsigned * Regs = TID . ImplicitDefs ; * Regs ; ++ Regs

) if ( * Regs == <STR_LIT> ) return true ;


<s> case MCSymbolRefExpr :: VK_<ISA_LIT>_ABS_LO : case MCSymbolRefExpr :: VK_<ISA_LIT>_ABS_HI : case MCSymbolRefExpr :: VK_<ISA_LIT>_HIGHER : case MCSymbolRefExpr :: VK_<ISA_LIT>_HIGHEST : break ; default : return false ; } if ( isa < MCBinaryExpr > ( BE -> getLHS ( ) ) ) { if ( ! isa < MCConstantExpr > ( BE -> getRHS


<s> const MachineOperand & BaseRegOp = MergeForward ? getLdStBaseOp ( Paired ) : getLdStBaseOp ( I ) ; MachineInstr * RtMI , * Rt2MI ; if ( getLdStOffsetOp ( I ) . getImm ( ) == getLdStOffsetOp ( Paired ) . getImm ( ) + OffsetStride ) { RtMI = Paired ; Rt2MI = I ; if ( SExtIdx != - <NUM_LIT> ) SExtIdx = ( SExtIdx + <NUM_LIT> ) % <NUM_LIT> ; } else { RtMI = I ; Rt2MI = Paired ; } int OffsetImm = getLdStOffsetOp ( RtMI ) . getImm ( ) ; if ( IsUnscaled && Enable<ISA_LIT>UnscaledMemOp ) OffsetImm /= OffsetStride ; MachineInstrBuilder MIB = BuildMI ( * I -> getParent ( ) , InsertionPoint , I -> getDebugLoc ( ) , TII -> get ( NewOpc ) ) . addOperand ( getLdStRegOp ( RtMI ) ) . addOperand ( getLdStRegOp ( Rt2MI ) ) . addOperand ( BaseRegOp ) . addImm ( OffsetImm ) ; ( void ) MIB ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; DEBUG ( I -> print ( dbgs ( ) ) ) ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; DEBUG ( Paired -> print ( dbgs ( ) ) ) ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; if ( SExtIdx != - <NUM_LIT> ) { MachineOperand & DstMO = MIB -> getOperand ( SExtIdx ) ; unsigned DstRegX = DstMO . getReg ( ) ; unsigned DstRegW = TRI -> getSubReg ( DstRegX , <STR_LIT> ) ; DstMO . setReg ( DstRegW ) ; DEBUG ( ( ( MachineInstr * ) MIB ) -> print ( dbgs ( ) ) ) ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; MachineInstrBuilder MIBKill = BuildMI ( * I -> getParent ( ) , InsertionPoint , I -> getDebugLoc ( ) , TII -> get ( TargetOpcode :: KILL ) , DstRegW ) . addReg ( DstRegW ) . addReg ( DstRegX , RegState :: Define ) ; MIBKill -> getOperand ( <NUM_LIT> ) . setImplicit ( ) ; MachineInstrBuilder MIBSXTW = BuildMI ( * I -> getParent ( ) , InsertionPoint , I -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , DstRegX ) . addReg ( DstRegX ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; ( void ) MIBSXTW ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; DEBUG ( ( ( MachineInstr * ) MIBSXTW ) -> print ( dbgs ( ) ) ) ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; } else { DEBUG ( ( ( MachineInstr * ) MIB ) -> print ( dbgs ( ) ) ) ; DEBUG ( dbgs ( )


<s> if ( recog_memoized ( insn ) >= <NUM_LIT> && get_attr_slot ( insn ) == slot && get_attr_length ( insn ) == length ) return insn ; } return


<s> printSymbolLo ( MI , OpNo , O ) ; O << '(' ; if ( MI -> getOperand ( OpNo + <NUM_LIT> ) . getReg (


<s> exp = EXPD ( dl1 ) - EXPONENT_BIAS - MANTISSA_BITS ; if ( exp <= - PRECISION ) return <NUM_LIT> ; if ( ( EXPD ( dl1 ) == <NUM_LIT> ) && ! FRACD_ZERO_P ( dl1 ) ) return <NUM_LIT> ; if ( exp >= - HIGH_LL_FRAC_BITS ) { l = ( long long ) <NUM_LIT> << <NUM_LIT> ; return SIGND ( dl1 ) ?


<s> unsigned Shift = <STR_LIT> ( Val ) ; return <STR_LIT> ( Val ) == <STR_LIT> && ( Shift ==


<s> SDValue IdxV = Op . getOperand ( <NUM_LIT> ) ; auto * IdxN = dyn_cast < ConstantSDNode > ( IdxV . getNode ( ) ) ; if ( ! IdxN ) return SDValue ( ) ; unsigned Idx = IdxN -> getZExtValue ( ) ; SDValue DstV = Op . getOperand ( <NUM_LIT> ) ; SDValue SrcV = Op . getOperand ( <NUM_LIT> ) ; MVT DstTy = ty ( DstV ) ; MVT SrcTy = ty (


<s> if ( fntype && stdarg_p ( fntype ) ) { cfun -> machine -> is_varadic = true ; cfun -> machine -> has_varadic = true ; cfun -> machine -> num_args ++ ; } } if ( REG_P ( arg ) && arg != pc_rtx ) { cfun -> machine ->


<s> const <ISA_LIT>InstrInfo * getInstrInfo ( )


<s> assert ( MO . isImm ( ) && <STR_LIT> ) ; return <NUM_LIT> - MO .


<s> Result = DAG . getTargetGlobalAddress ( GV , getPointerTy ( ) , Offset ) ; Offset = <NUM_LIT> ; } else { unsigned char OpFlags = <NUM_LIT> ; if ( ExtraLoadRequired ) OpFlags = <STR_LIT> ; Result = DAG . getTargetGlobalAddress ( GV , getPointerTy ( ) , <NUM_LIT> , OpFlags ) ; } Result = DAG . getNode ( <STR_LIT> , dl , getPointerTy ( ) , Result ) ; if ( ExtraLoadRequired ) Result = DAG . getLoad ( getPointerTy ( ) , dl , DAG . getEntryNode ( ) , Result , PseudoSourceValue :: getGOT ( ) , <NUM_LIT> ) ; if ( Offset != <NUM_LIT> ) Result = DAG . getNode ( <STR_LIT> , dl , getPointerTy ( ) , Result ,

DAG . getConstant ( Offset , getPointerTy ( ) ) ) ;


<s> static bool isSimpleReturn ( const MachineInstr &


<s> else { HasRs = true ; MI . setOpcode ( <STR_LIT> ) ; } if ( HasRs ) MI . addOperand ( MCOperand :: createReg ( getReg ( Decoder , <STR_LIT> , Rs ) ) ) ; MI . addOperand ( MCOperand :: createReg ( getReg ( Decoder , <STR_LIT> , Rt ) ) ) ; MI . addOperand ( MCOperand :: createImm ( Imm )


<s> if ( MFI . isFixedObjectIndex ( FI ) ) FrameReg = hasFP ( MF ) ? ABI . GetFramePtr ( ) : ABI . GetStackPtr ( ) ; else FrameReg = hasBP ( MF ) ? ABI . GetBasePtr ( ) : ABI


<s> Instructions . push_back ( Inst ) ; MCInst NopInst ; NopInst . setOpcode ( <STR_LIT> ) ; NopInst . addOperand ( MCOperand :: CreateReg ( <STR_LIT> ) ) ; NopInst . addOperand ( MCOperand :: CreateReg ( <STR_LIT> ) ) ; NopInst . addOperand ( MCOperand :: CreateImm ( <NUM_LIT> ) ) ; Instructions . push_back ( NopInst ) ; return false ; } if ( MCID . mayLoad ( ) || MCID . mayStore ( ) ) { for ( unsigned i = <NUM_LIT> ; i < MCID . getNumOperands ( ) ; i ++ ) { const MCOperandInfo & OpInfo = MCID . OpInfo [ i ] ; if ( ( OpInfo . OperandType == MCOI :: OPERAND_MEMORY ) || ( OpInfo . OperandType == MCOI :: OPERAND_UNKNOWN ) ) { MCOperand & Op = Inst . getOperand ( i ) ; if ( Op . isImm ( ) ) { int MemOffset = Op . getImm ( ) ; if ( MemOffset < - <NUM_LIT> || MemOffset > <NUM_LIT> ) { expandMemInst ( Inst , IDLoc , Instructions , MCID .


<s> O << STI . getTargetName ( ) ; const <ISA_LIT>TargetMachine & NTM = static_cast < const <ISA_LIT>TargetMachine & > ( TM ) ; if ( NTM . getDrvInterface ( ) == <STR_LIT> ) O << <STR_LIT> ; if ( MAI -> doesSupportDebugInformation ( ) ) O << <STR_LIT> ; O <<


<s> if ( isInt < <NUM_LIT> > ( Imm ) ) return <STR_LIT> ; return <STR_LIT> ; } else { if ( isInt < <NUM_LIT> > ( Imm ) ) return <STR_LIT> ; return


<s> virtual const <ISA_LIT>TargetLowering * getTargetLowering ( ) const { return & TLInfo


<s> const MCSection * <ISA_LIT>TargetObjectFile :: getSectionForFunction ( const std :: string &


<s> if ( SDValue FPLogic = convertIntLogicToFPLogic ( N , DAG , Subtarget ) ) return FPLogic ; if ( SDValue R = combineANDXORWithAllOnesIntoANDNP ( N , DAG ) ) return R ; if ( SDValue ShiftRight = combinePCMPAnd1 ( N , DAG ) ) return ShiftRight ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; SDValue N0 = N -> getOperand ( <NUM_LIT> ) ; SDValue N1 = N -> getOperand ( <NUM_LIT> ) ; SDLoc DL ( N ) ; if ( VT != <STR_LIT> && VT != <STR_LIT> ) return SDValue ( ) ; if ( ! Subtarget . hasBMI ( ) && ! Subtarget . hasTBM ( ) ) return SDValue ( ) ; if ( N0 . getOpcode ( ) != <STR_LIT> && N0 . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; ConstantSDNode * MaskNode = dyn_cast < ConstantSDNode > ( N1 ) ; ConstantSDNode * ShiftNode = dyn_cast < ConstantSDNode > ( N0 . getOperand ( <NUM_LIT> ) ) ; if ( MaskNode && ShiftNode ) { uint64_t Mask = MaskNode -> getZExtValue ( ) ; uint64_t Shift = ShiftNode -> getZExtValue ( ) ; if ( isMask_64 ( Mask ) ) { uint64_t MaskSize = countPopulation ( Mask ) ; if ( Shift + MaskSize <= VT . getSizeInBits ( ) ) return DAG . getNode ( <STR_LIT> , DL , VT , N0 . getOperand ( <NUM_LIT> ) , DAG . getConstant ( Shift |

( MaskSize << <NUM_LIT> ) , DL , VT ) ) ;


<s> return new <ISA_LIT>16DAGToDAGISel ( TM


<s> EVT VT = <STR_LIT> ; EVT WideVT = <STR_LIT> ; SDLoc dl ( Op ) ; SDValue LHS = Op . getOperand ( <NUM_LIT> ) ; if ( LHS . getValueType ( ) != VT ) return Op ; SDValue ShiftAmt = DAG . getConstant ( <NUM_LIT> , dl , VT ) ; SDValue RHS = Op . getOperand ( <NUM_LIT> ) ; SDValue HiLHS = DAG . getNode ( <STR_LIT> , dl , VT , LHS , ShiftAmt ) ; SDValue HiRHS = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , RHS , ShiftAmt ) ; SDValue Args [ ] = { HiLHS , LHS ,


<s> unsigned NumMayIncreaseSize = <NUM_LIT> ; MVT VT = N -> getValueType ( <NUM_LIT> ) . getScalarType ( ) . getSimpleVT ( ) ; for ( const SDNode * U : N -> uses


<s> break ; case ZERO_EXTRACT : n = BITS_PER_WORD - INTVAL_OR_ELSE ( XEXP ( x , <NUM_LIT> ) , BITS_PER_WORD ) ; x = NULL_RTX ; break ; case AND : w = INTVAL_OR_ELSE ( XEXP ( x , <NUM_LIT> ) , HWINT ( - <NUM_LIT> ) ) ; for ( i = BITS_PER_WORD - <NUM_LIT> ; i >= <NUM_LIT> ; i -- ) { if ( w & ( ( HWINT ( <NUM_LIT> ) ) << i ) ) break ; } n = BITS_PER_WORD - i ; x = XEXP ( x


<s> static std :: unique_ptr < <ISA_LIT>Operand > CreateDXReg (


<s> static bool isCallInstruction ( const MachineInstr & MI ) { return MI . isCall ( ) && ! MI


<s> unsigned <ISA_LIT>InstrInfo :: getIssueWidth ( const MachineInstr * MI ) const { if ( MI -> isInlineAsm ( ) ) return PST . getSchedModel ( ) -> IssueWidth ; return PST . getIssueWidth ( MI -> getDesc (


<s> case <STR_LIT> : Reloc = <STR_LIT> ; break ; } } MachineRelocation R ; if ( MO . isGlobal ( ) ) { R = MachineRelocation :: getGV ( MCE . getCurrentPCOffset ( ) , Reloc , MO . getGlobal ( ) , <NUM_LIT> , isa < Function > ( MO . getGlobal ( ) ) ) ; } else if ( MO . isSymbol ( ) ) { R = MachineRelocation :: getExtSym ( MCE . getCurrentPCOffset ( ) , Reloc , MO . getSymbolName ( ) , <NUM_LIT> ) ; } else if ( MO . isCPI ( ) ) { R = MachineRelocation :: getConstPool ( MCE . getCurrentPCOffset ( ) , Reloc , MO . getIndex ( ) , <NUM_LIT> ) ; } else { assert ( MO . isJTI ( ) ) ; R = MachineRelocation :: getJumpTable ( MCE . getCurrentPCOffset ( ) , Reloc , MO . getIndex ( ) , <NUM_LIT> ) ; } if ( TM . getRelocationModel ( ) == Reloc :: PIC_ && Reloc != <STR_LIT> ) { assert ( MovePCtoLROffset && <STR_LIT> ) ; R . setConstantVal ( - ( intptr_t ) MovePCtoLROffset - <NUM_LIT> ) ; } MCE . addRelocation ( R ) ; } else if ( MO . isMBB ( ) ) { unsigned Reloc = <NUM_LIT> ; unsigned Opcode = MI . getOpcode ( ) ; if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ) Reloc = <STR_LIT> ; else Reloc = <STR_LIT> ; MCE . addRelocation ( MachineRelocation :: getBB ( MCE . getCurrentPCOffset ( ) , Reloc , MO . getMBB ( ) ) ) ; }


<s> if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ) return true ; if ( MI . isInlineAsm ( ) ) return


<s> for ( unsigned i = <NUM_LIT> , n = MI . getNumOperands ( ) ; i < n ; ++ i ) if ( & MI . getOperand ( i ) == & MO ) { OperandNumber = i ; break ; } assert ( ( OperandNumber != ~ <NUM_LIT> ) && <STR_LIT> ) ; if ( <ISA_LIT>MCInstrInfo :: isNewValue ( MCII , MI ) && & MO == & <ISA_LIT>MCInstrInfo :: getNewValueOperand ( MCII , MI ) ) { unsigned SOffset = <NUM_LIT> ; unsigned VOffset = <NUM_LIT> ; unsigned UseReg = MO . getReg ( ) ; unsigned DefReg1 = <STR_LIT> ; unsigned DefReg2 = <STR_LIT> ; auto Instrs = <ISA_LIT>MCInstrInfo :: bundleInstructions ( * State . Bundle ) ; const MCOperand * I = Instrs . begin ( ) + State . Index - <NUM_LIT> ; for ( ; ; -- I ) { assert ( I != Instrs . begin ( ) - <NUM_LIT> && <STR_LIT> ) ; MCInst const & Inst = * I -> getInst ( ) ; if ( <ISA_LIT>MCInstrInfo :: isImmext ( Inst ) ) continue ; DefReg1 = <STR_LIT> ; DefReg2 = <STR_LIT> ; ++ SOffset ; if ( <ISA_LIT>MCInstrInfo :: isVector ( MCII , Inst ) ) { ++ VOffset ; } if ( <ISA_LIT>MCInstrInfo :: hasNewValue ( MCII , Inst ) ) DefReg1 = <ISA_LIT>MCInstrInfo :: getNewValueOperand ( MCII , Inst ) . getReg ( ) ; if ( <ISA_LIT>MCInstrInfo :: hasNewValue2 ( MCII , Inst ) ) DefReg2 = <ISA_LIT>MCInstrInfo :: getNewValueOperand2 ( MCII , Inst ) . getReg ( ) ; if ( ! RegisterMatches ( UseReg , DefReg1 , DefReg2 ) ) { continue ; } if ( ! <ISA_LIT>MCInstrInfo :: isPredicated ( MCII , Inst ) ) { break ; } assert ( <ISA_LIT>MCInstrInfo :: isPredicated ( MCII , MI ) && <STR_LIT> ) ; if ( <ISA_LIT>MCInstrInfo :: isPredicatedTrue ( MCII , Inst ) == <ISA_LIT>MCInstrInfo :: isPredicatedTrue ( MCII , MI ) ) break ; } unsigned Offset = <ISA_LIT>MCInstrInfo :: isVector ( MCII , MI ) ? VOffset : SOffset ; Offset <<= <NUM_LIT> ; Offset |= <ISA_LIT>MCInstrInfo :: SubregisterBit ( UseReg , DefReg1 , DefReg2 ) ; return Offset ; } assert ( ! MO . isImm ( ) ) ; if ( MO . isReg ( ) ) { unsigned Reg = MO . getReg ( ) ; switch ( <ISA_LIT>MCInstrInfo :: getDesc ( MCII , MI ) . OpInfo [ OperandNumber ] . RegClass ) { case GeneralSubRegsRegClassID : case GeneralDoubleLow8RegsRegClassID : return <ISA_LIT>MCInstrInfo :: getDuplexRegisterNumbering ( Reg ) ; default : break ; } return MCT . getRegisterInfo ( ) -> getEncodingValue (


<s> rtx fuse_ops [ <NUM_LIT> ] ; char insn_template [ <NUM_LIT> ] ; fuse_ops [ <NUM_LIT> ] = load_store_reg ; fuse_ops [ <NUM_LIT> ] = addis_reg ; if ( CONST_INT_P ( offset ) && satisfies_constraint_I ( offset ) ) { sprintf ( insn_template , <STR_LIT> , insn_str ) ; fuse_ops [ <NUM_LIT> ] = offset ; output_asm_insn ( insn_template , fuse_ops ) ; } else if ( GET_CODE ( offset ) == UNSPEC && XINT ( offset , <NUM_LIT> ) == UNSPEC_TOCREL ) { if ( TARGET_ELF ) sprintf ( insn_template , <STR_LIT> , insn_str ) ; else if ( TARGET_XCOFF ) sprintf ( insn_template , <STR_LIT> ,


<s> Function * <ISA_LIT>IntrinsicInfo :: getDeclaration ( Module * M , unsigned IntrID , ArrayRef < Type * > Tys ) const { FunctionType * FTy = getType ( M -> getContext ( ) , IntrID


<s> static bool hasVGPRs ( const TargetRegisterClass * RC


<s> extract_insn ( insn ) ; if ( constrain_operands ( <NUM_LIT> , get_preferred_alternatives ( insn ) ) ) { fprintf ( stderr , <STR_LIT> ) ; debug_rtx ( insn ) ; fprintf ( stderr , <STR_LIT> ) ; if ( SET_P ( pattern ) ) record_content ( SET_DEST ( pattern ) , SET_SRC ( pattern ) ) ; for ( i = <NUM_LIT> ; i < recog_data . n_operands ; i ++ ) if ( GET_CODE ( OP ( i ) ) == MEM && GET_MODE ( XEXP ( OP ( i ) , <NUM_LIT> ) ) == SImode && GET_CODE ( XEXP ( OP ( i ) , <NUM_LIT> ) ) != UNSPEC ) goto not_ok ; return true ; } } not_ok : INSN_CODE ( insn ) = - <NUM_LIT> ; cfun -> machine -> virt_insns_ok


<s> HasExtender = false ; printInstruction ( MCI . getOperand ( <NUM_LIT> ) . getInst ( ) , OS ) ; } else printInstruction ( & MCI , OS ) ; setExtender ( MCI ) ; OS << <STR_LIT> ; } auto Separator = <STR_LIT> ; if ( <ISA_LIT>MCInstrInfo :: isInnerLoop ( * MI ) ) { OS << Separator ; Separator = <STR_LIT> ; MCInst ME ; ME . setOpcode ( <STR_LIT> ) ; printInstruction ( & ME , OS ) ; } if ( <ISA_LIT>MCInstrInfo :: isOuterLoop ( * MI ) ) { OS << Separator ; Separator = <STR_LIT> ; MCInst ME ; ME . setOpcode ( <STR_LIT> ) ; printInstruction ( & ME


<s> static MCInstPrinter * create<ISA_LIT>MCInstPrinter ( const Target & T , unsigned SyntaxVariant , const MCAsmInfo & MAI , const MCInstrInfo & MII , const MCRegisterInfo & MRI , const MCSubtargetInfo & STI ) { if ( SyntaxVariant == <NUM_LIT> ) return new <ISA_LIT>InstPrinter ( MAI , MII , MRI ) ; return <NUM_LIT>


<s> RegisterTarget < Triple :: cahp > X ( getThe<ISA_LIT>Target ( ) , <STR_LIT> , <STR_LIT> ,


<s> unsigned NumElts = SrcOps [ <NUM_LIT> ] . getValueType ( ) . getVectorNumElements ( ) ; EVT MaskVT = EVT :: getIntegerVT ( * DAG . getContext ( ) , NumElts ) ; SDValue Mask = combineBitcastvxi1 ( DAG , MaskVT , SrcOps [ <NUM_LIT> ] , dl , Subtarget ) ; if ( ! Mask && TLI . isTypeLegal ( SrcOps [ <NUM_LIT> ] . getValueType ( ) ) ) Mask = DAG . getBitcast ( MaskVT , SrcOps [ <NUM_LIT> ] ) ; if ( Mask ) { assert ( SrcPartials [ <NUM_LIT> ] . getBitWidth ( ) == NumElts && <STR_LIT> ) ; SDValue ZeroBits = DAG . getConstant ( <NUM_LIT> , dl , MaskVT ) ; SDValue PartialBits = DAG . getConstant ( SrcPartials [ <NUM_LIT> ] , dl , MaskVT ) ; Mask = DAG . getNode ( <STR_LIT> , dl , MaskVT , Mask , PartialBits ) ; return DAG . getSetCC ( dl , <STR_LIT> , Mask , ZeroBits , <STR_LIT> ) ; } } } if ( SDValue R = combineBitOpWithMOVMSK ( N , DAG ) ) return R ; if ( DCI . isBeforeLegalizeOps ( ) ) return SDValue ( ) ; if ( SDValue R = combineCompareEqual ( N , DAG , DCI , Subtarget ) ) return R ; if ( SDValue FPLogic = convertIntLogicToFPLogic ( N , DAG , Subtarget ) ) return FPLogic ; if ( SDValue R = canonicalizeBitSelect ( N , DAG , Subtarget ) ) return R ; if ( SDValue R = combineLogicBlendIntoPBLENDV ( N , DAG , Subtarget ) ) return R ; if ( N0 . getOpcode ( ) == <STR_LIT> || N1 . getOpcode ( ) == <STR_LIT> ) { unsigned NumElts = VT . getVectorNumElements ( ) ; unsigned HalfElts = NumElts / <NUM_LIT> ; APInt UpperElts = APInt :: getHighBitsSet ( NumElts , HalfElts ) ; if ( NumElts >= <NUM_LIT> && N1 . getOpcode ( ) == <STR_LIT> && N1 . getConstantOperandAPInt ( <NUM_LIT> ) == HalfElts && DAG . MaskedValueIsZero ( N0 , APInt ( <NUM_LIT> , <NUM_LIT> )


<s> SDValue StoreVal = createTuple ( * CurDAG , Regs , NF , LMUL ) ; SmallVector < SDValue , <NUM_LIT> > Operands ; Operands . push_back ( StoreVal ) ; unsigned CurOp = <NUM_LIT> + NF ; MVT IndexVT ; addVectorLoadStoreOperands ( Node , ScalarSize , DL , CurOp , IsMasked , true , Operands , & IndexVT ) ; assert ( VT . getVectorElementCount ( ) == IndexVT . getVectorElementCount ( ) && <STR_LIT> ) ; <STR_LIT> IndexLMUL = <ISA_LIT>TargetLowering :: getLMUL ( IndexVT ) ; unsigned IndexScalarSize = IndexVT . getScalarSizeInBits ( ) ; const <STR_LIT> * P = <STR_LIT> ( NF , IsMasked , IsOrdered , IndexScalarSize , static_cast < unsigned > ( LMUL ) , static_cast < unsigned > ( IndexLMUL ) ) ; MachineSDNode * Store = CurDAG -> getMachineNode ( P -> Pseudo , DL , Node -> getValueType ( <NUM_LIT> ) , Operands ) ; if ( auto * MemOp = dyn_cast < MemSDNode > ( Node ) ) CurDAG -> setNodeMemRefs ( Store , { MemOp -> getMemOperand ( ) } ) ; ReplaceNode ( Node , Store


<s> MachineOperand & DstMO = MI . getOperand ( <NUM_LIT> ) ; MachineOperand & SrcMO = MI . getOperand ( <NUM_LIT> ) ; if ( IsVSReg ( DstMO . getReg ( ) , MRI ) && ! IsVSReg ( SrcMO . getReg ( ) , MRI ) ) { Changed = true ; const TargetRegisterClass * SrcRC = & <STR_LIT> ; assert ( ( IsF8Reg ( SrcMO . getReg ( ) , MRI ) || IsVSSReg ( SrcMO . getReg ( ) , MRI ) || IsVSFReg ( SrcMO . getReg ( ) , MRI ) ) && <STR_LIT> ) ; unsigned NewVReg = MRI . createVirtualRegister ( SrcRC ) ; BuildMI ( MBB , MI , MI . getDebugLoc ( ) , TII -> get ( TargetOpcode :: SUBREG_TO_REG ) , NewVReg ) . addImm ( <NUM_LIT> ) . addOperand ( SrcMO ) . addImm ( <STR_LIT> ) ; SrcMO . setReg ( NewVReg ) ; } else if ( ! IsVSReg ( DstMO . getReg ( ) , MRI ) && IsVSReg ( SrcMO . getReg ( ) , MRI ) ) { Changed = true ; const TargetRegisterClass * DstRC = & <STR_LIT> ; assert ( ( IsF8Reg ( DstMO . getReg ( ) , MRI ) || IsVSFReg ( DstMO . getReg ( ) , MRI ) || IsVSSReg ( DstMO . getReg ( ) , MRI ) ) && <STR_LIT> ) ; unsigned NewVReg = MRI . createVirtualRegister ( DstRC ) ; BuildMI ( MBB , MI , MI . getDebugLoc ( ) , TII -> get ( TargetOpcode :: COPY ) , NewVReg )


<s> static void emit_unlikely_jump ( rtx cond , rtx label ) { int very_unlikely = REG_BR_PROB_BASE


<s> void addInstruction ( TagStoreInstr I ) { assert ( ( TagStores . empty ( ) || TagStores . back ( ) . Offset + TagStores . back ( ) . Size == I . Offset


<s> if ( InsertExport ) { removeDoneExport ( F ) ; Value * Undef = UndefValue :: get ( B . getFloatTy ( ) ) ; B . CreateIntrinsic ( <STR_LIT> , { B . getFloatTy ( ) } , { B . getInt32 ( <NUM_LIT> ) , B . getInt32 ( <NUM_LIT> ) , Undef , Undef , Undef , Undef , B . getTrue ( ) , B . getTrue ( ) , } ) ; } PHINode * PN = nullptr ; if ( F . getReturnType ( ) -> isVoidTy ( ) ) { B . CreateRetVoid ( ) ; } else { PN = B . CreatePHI ( F . getReturnType ( ) , ReturningBlocks . size ( ) , <STR_LIT> ) ; assert ( ! InsertExport ) ; B . CreateRet ( PN ) ; } for ( BasicBlock * BB : ReturningBlocks ) { if ( PN ) PN -> addIncoming ( BB -> getTerminator ( ) ->


<s> auto & I = SubtargetMap [ CPU + FS ] ; if ( ! I ) { resetTargetOptions ( F ) ; I = llvm :: make_unique < <ISA_LIT>Subtarget > ( TargetTriple , CPU , computeFSAdditions ( FS , getOptLevel ( ) , getTargetTriple ( ) ) , * this ) ; } return I .


<s> if ( auto GREV = combineORToGREV ( SDValue ( N , <NUM_LIT> ) , DAG , Subtarget ) ) return GREV ; if ( auto GORC = combineORToGORC ( SDValue ( N , <NUM_LIT> )


<s> Register SaveExecDest = SaveExec . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( ! TRI -> isSGPRReg ( MRI , SaveExecDest ) ) return nullptr ; MachineOperand * SaveExecSrc0 = TII -> getNamedOperand ( SaveExec , <STR_LIT> :: src0 ) ; if ( ! SaveExecSrc0 -> isReg ( ) ) return nullptr ; VCmp = findInstrBackwards ( SaveExec , [ & ] ( MachineInstr * Check ) { return <STR_LIT> ( Check -> getOpcode ( ) ) != - <NUM_LIT> && Check -> modifiesRegister ( SaveExecSrc0 -> getReg ( ) , TRI ) ; } , { Exec , SaveExecSrc0 -> getReg ( ) } , TRI ) ; if ( ! VCmp ) return nullptr ; MachineOperand * VCmpDest = TII -> getNamedOperand ( * VCmp , <STR_LIT> :: sdst ) ; assert ( VCmpDest && <STR_LIT> ) ; MachineOperand * Src0 = TII -> getNamedOperand ( * VCmp , <STR_LIT> :: src0 ) ; if ( Src0 -> isReg ( ) && TRI -> isSGPRReg ( MRI , Src0 -> getReg ( ) )

&& SaveExec . modifiesRegister ( Src0 -> getReg ( ) , TRI ) ) return nullptr ;


<s> void <ISA_LIT>MCExpr :: printImpl ( raw_ostream & OS ,


<s> SmallVector < MVT , <NUM_LIT> > ArgVTs ; SmallVector < <STR_LIT> , <NUM_LIT> > ArgFlags ; Args . reserve ( NumArgs ) ; ArgRegs . reserve ( NumArgs ) ; ArgVTs . reserve ( NumArgs ) ; ArgFlags . reserve ( NumArgs ) ; for ( unsigned i = <NUM_LIT> , ie = NumArgs ; i != ie ; ++ i ) { <STR_LIT> Flags = CLI . OutFlags [ i ] ; if ( Flags . isInReg ( ) || Flags . isSRet ( ) || Flags . isNest ( ) || Flags . isByVal ( ) ) return false ; Value * ArgValue = CLI . OutVals [ i ] ; Type * ArgTy = ArgValue -> getType ( ) ; MVT ArgVT ; if ( ! isTypeLegal ( ArgTy , ArgVT ) && ArgVT != <STR_LIT> && ArgVT != <STR_LIT> ) return false ; if ( ArgVT . isVector ( ) ) return false ; unsigned Arg = getRegForValue ( ArgValue ) ; if ( Arg == <NUM_LIT> ) return false ; Args . push_back ( ArgValue ) ; ArgRegs . push_back ( Arg ) ; ArgVTs . push_back ( ArgVT ) ; ArgFlags . push_back ( Flags ) ; } SmallVector < unsigned , <NUM_LIT>


<s> if ( ! MI -> isBranch ( ) ) return false ; for ( auto & Op : MI -> operands ( ) ) if ( Op . isGlobal ( ) || Op . isSymbol ( ) ) return true ; return


<s> bool isUnary = TID . TSFlags & <STR_LIT> ; if ( ! isUnary ) { if ( ImplicitRn ) Binary |= ( <ISA_LIT>RegisterInfo :: getRegisterNumbering ( ImplicitRn ) << <STR_LIT> ) ; else { Binary |= getMachineOpValue ( MI , OpIdx ) << <STR_LIT> ; ++ OpIdx ; } } const MachineOperand & MO = MI . getOperand ( OpIdx ) ; if ( ( TID . TSFlags & <STR_LIT> ) == <STR_LIT> ) { emitWordLE ( Binary | getMachineSoRegOpValue ( MI , TID , MO , OpIdx ) ) ; return ; } if ( MO . isReg


<s> GRTop = DAG . getFrameIndex ( FuncInfo -> getVarArgsGPRIndex ( ) , getPointerTy ( ) ) ; GRTop = DAG . getNode ( <STR_LIT> , DL , getPointerTy ( ) , GRTop , DAG . getConstant ( GPRSize , getPointerTy ( ) ) ) ; MemOps . push_back ( DAG . getStore ( Chain , DL , GRTop , GRTopAddr , MachinePointerInfo ( SV , <NUM_LIT> ) , false , false , <NUM_LIT> ) ) ; } int FPRSize = FuncInfo -> getVarArgsFPRSize ( ) ; if ( FPRSize > <NUM_LIT> ) { SDValue VRTop , VRTopAddr ; VRTopAddr = DAG . getNode ( <STR_LIT> , DL , getPointerTy ( ) , VAList , DAG . getConstant ( <NUM_LIT> , getPointerTy ( ) ) ) ; VRTop = DAG . getFrameIndex ( FuncInfo -> getVarArgsFPRIndex ( ) , getPointerTy ( ) ) ; VRTop = DAG . getNode ( <STR_LIT> , DL , getPointerTy ( ) , VRTop , DAG . getConstant ( FPRSize , getPointerTy ( ) ) ) ; MemOps . push_back ( DAG . getStore ( Chain , DL , VRTop , VRTopAddr , MachinePointerInfo ( SV , <NUM_LIT> ) , false , false , <NUM_LIT> ) ) ; } SDValue GROffsAddr = DAG . getNode ( <STR_LIT> , DL , getPointerTy ( ) , VAList , DAG . getConstant ( <NUM_LIT> , getPointerTy ( ) ) ) ; MemOps . push_back ( DAG . getStore ( Chain , DL , DAG . getConstant ( - GPRSize , <STR_LIT> ) , GROffsAddr , MachinePointerInfo ( SV , <NUM_LIT> ) , false , false , <NUM_LIT> ) ) ; SDValue VROffsAddr = DAG . getNode ( <STR_LIT> , DL , getPointerTy ( ) , VAList , DAG . getConstant ( <NUM_LIT> , getPointerTy ( ) ) ) ; MemOps . push_back ( DAG . getStore ( Chain , DL , DAG . getConstant ( - FPRSize , <STR_LIT> ) , VROffsAddr , MachinePointerInfo ( SV , <NUM_LIT> ) , false , false , <NUM_LIT> ) ) ; return DAG . getNode ( <STR_LIT> ,


<s> return DecodeGPRSeqPairsClassRegisterClass ( Inst , <STR_LIT> , RegNo


<s> return new <ISA_LIT>TargetNullStreamer (


<s> return <NUM_LIT> - MI . getOperand ( Op ) . getImm


<s> for ( const MachineInstr & MI : MBB ) Size += TII -> GetInstSizeInBytes ( MI ) ; BlockInfo [ MBB . getNumber ( )


<s> struct DecodeTable { const uint8_t * P ; bool DecodePred ; } ; const DecodeTable Tables [ ] = { { DecoderTableVFP32 , false } , { DecoderTableVFPV832 , false } , { DecoderTableNEONData32 , true } , { DecoderTableNEONLoadStore32 , true } , { DecoderTableNEONDup32 , true } , { DecoderTablev8NEON32 , false } , { DecoderTablev8Crypto32 , false } , } ; for ( auto Table : Tables ) { Result = decodeInstruction ( Table . P , MI , Insn , Address , this , STI ) ; if ( Result != MCDisassembler :: Fail ) { Size = <NUM_LIT> ; if ( Table . DecodePred && ! DecodePredicateOperand ( MI , <NUM_LIT>

, Address , this ) ) return MCDisassembler :: Fail ;


<s> MVT VecTy = ty ( Op . getOperand ( <NUM_LIT> ) ) ; assert ( VecTy == ty ( Op . getOperand ( <NUM_LIT> ) ) ) ; SDValue Cmp = Op . getOperand ( <NUM_LIT> ) ; <STR_LIT> CC = cast < CondCodeSDNode > ( Cmp ) -> get ( ) ; bool Negate = false , Swap = false ; switch ( CC ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : CC = <STR_LIT> ( CC , true ) ; Negate = true ; break ; default : break ; } switch ( CC ) { case <STR_LIT> : case <STR_LIT> : CC = <STR_LIT> ( CC ) ; Swap = true ; break ; default : break ; } assert ( CC == <STR_LIT> || CC == <STR_LIT> || CC == <STR_LIT> ) ; MVT ElemTy = VecTy


<s> static const char * get_some_local_dynamic_name ( void ) { rtx insn ; if ( cfun -> machine -> some_ld_name ) return cfun -> machine -> some_ld_name ; for ( insn = get_insns ( ) ; insn ; insn = NEXT_INSN ( insn ) ) if ( INSN_P ( insn ) && for_each_rtx ( & PATTERN ( insn ) , get_some_local_dynamic_name_1 , <NUM_LIT> ) ) return cfun -> machine -> some_ld_name ; gcc_unreachable (


<s> return ( uint32x2_t ) __builtin_neon_vqshrun_nv2di ( __a ,


<s> int32_t <ISA_LIT>SplitDoubleRegs :: profit ( unsigned Reg ) const { assert ( TargetRegisterInfo :: isVirtualRegister ( Reg ) ) ; const MachineInstr * DefI = MRI -> getVRegDef ( Reg ) ; switch ( DefI -> getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return profit ( DefI ) ; default : break ; } return


<s> uint32_t v = ~ MO . getImm ( ) ; int32_t lsb = CountTrailingZeros_32 ( v ) ; int32_t width = ( <NUM_LIT> - CountLeadingZeros_32 ( v ) ) - lsb ; assert ( MO . isImm ( )


<s> static_cast < <ISA_LIT>InstPrinter * > ( this ) -> printRel


<s> if ( stack_frame_needed_p ( ) ) emit_insn ( gen_unlink ( ) ) ; else { rtx postinc = gen_rtx_MEM ( Pmode , gen_rtx_POST_INC ( Pmode , spreg ) ) ; add_to_reg ( spreg , frame_size , <NUM_LIT> , epilogue_p ) ; if ( all || must_save_fp_p ( ) ) { rtx fpreg = gen_rtx_REG ( Pmode , REG_FP ) ; emit_move_insn ( fpreg , postinc ) ; emit_use ( fpreg


<s> addPass ( create<ISA_LIT>RegColoring ( ) ) ; } addPass ( create<ISA_LIT>CFGSort ( ) ) ; addPass ( create<ISA_LIT>CFGStackify ( ) ) ; if ( ! WasmDisableExplicitLocals ) addPass ( create<ISA_LIT>ExplicitLocals ( ) ) ; addPass ( create<ISA_LIT>LowerBrUnless ( ) ) ; if ( getOptLevel ( ) != CodeGenOpt :: None

) addPass ( create<ISA_LIT>Peephole ( ) ) ;


<s> void setScratchRSrcReg ( Register Reg ) { assert ( Reg != <NUM_LIT> && <STR_LIT>


<s> if ( loadImmediate ( <NUM_LIT> , nextReg ( FirstReg ) , <STR_LIT> , true , false , IDLoc , Out , STI ) ) return true ; } return false ; } MCSection * CS = getStreamer ( ) . getCurrentSectionOnly ( ) ; MCSection * ReadOnlySection = getContext ( ) . getELFSection ( <STR_LIT> , ELF :: SHT_PROGBITS , ELF :: SHF_ALLOC ) ; MCSymbol * Sym = getContext ( ) . createTempSymbol ( ) ; const MCExpr * LoSym = MCSymbolRefExpr :: create ( Sym , MCSymbolRefExpr :: VK_None , getContext ( ) ) ; const <ISA_LIT>MCExpr * LoExpr = <ISA_LIT>MCExpr :: create ( <ISA_LIT>MCExpr :: MEK_LO , LoSym , getContext ( ) ) ; getStreamer ( ) . SwitchSection ( ReadOnlySection ) ; getStreamer ( ) . emitLabel ( Sym , IDLoc ) ; getStreamer ( ) . emitValueToAlignment ( <NUM_LIT> ) ; getStreamer ( ) . emitIntValue ( ImmOp64 , <NUM_LIT> ) ; getStreamer ( ) . SwitchSection ( CS ) ; unsigned TmpReg = getATReg ( IDLoc ) ; if ( ! TmpReg ) return true ; if ( emitPartialAddress ( TOut , IDLoc , Sym ) ) return true ; TOut . emitRRX ( isABI_N64 ( ) ? <STR_LIT> : <STR_LIT> , TmpReg , TmpReg , MCOperand :: createExpr ( LoExpr ) , IDLoc , STI ) ; if ( isGP64bit ( ) ) TOut . emitRRI ( <STR_LIT> , FirstReg , TmpReg , <NUM_LIT> , IDLoc , STI ) ; else { TOut . emitRRI ( <STR_LIT> , FirstReg , TmpReg , <NUM_LIT> , IDLoc , STI ) ; TOut . emitRRI ( <STR_LIT> , nextReg ( FirstReg ) , TmpReg , <NUM_LIT> , IDLoc , STI ) ; } return false


<s> int extra_count ; int num_use_regs ; int par_index ; int offset ; int save_fp , save_gp , save_lp ; rtx reg ; rtx mem ; rtx pop_rtx ; rtx adjust_sp_rtx ; rtx parallel_insn ; rtx dwarf = NULL_RTX ; save_fp = INTVAL ( En4 ) & <NUM_LIT> ; save_gp = INTVAL ( En4 ) & <NUM_LIT> ; save_lp = INTVAL ( En4 ) & <NUM_LIT> ; extra_count = <NUM_LIT> ; if ( save_fp ) extra_count ++ ; if ( save_gp ) extra_count ++ ; if ( save_lp ) extra_count ++ ; if ( REGNO ( Rb ) == SP_REGNUM && REGNO ( Re ) == SP_REGNUM ) num_use_regs = extra_count ; else num_use_regs = REGNO ( Re ) - REGNO ( Rb ) + <NUM_LIT> + extra_count ; parallel_insn = gen_rtx_PARALLEL ( VOIDmode , rtvec_alloc ( num_use_regs + <NUM_LIT> ) ) ; par_index = <NUM_LIT> ; offset = <NUM_LIT> ; for ( regno = REGNO ( Rb ) ; regno <= ( int ) REGNO ( Re ) ; regno ++ ) { if ( regno == SP_REGNUM ) break ; reg = gen_rtx_REG ( SImode , regno ) ; mem = gen_frame_mem ( SImode , plus_constant ( Pmode , stack_pointer_rtx , offset ) ) ; pop_rtx = gen_rtx_SET ( reg , mem ) ; XVECEXP ( parallel_insn , <NUM_LIT> , par_index ) = pop_rtx ; RTX_FRAME_RELATED_P ( pop_rtx ) = <NUM_LIT> ; offset = offset + <NUM_LIT> ; par_index ++ ; dwarf = alloc_reg_note ( REG_CFA_RESTORE , reg , dwarf ) ; } if ( save_fp ) { reg = gen_rtx_REG ( SImode , FP_REGNUM ) ; mem = gen_frame_mem ( SImode , plus_constant ( Pmode , stack_pointer_rtx , offset ) ) ; pop_rtx = gen_rtx_SET ( reg , mem ) ; XVECEXP ( parallel_insn , <NUM_LIT> , par_index ) = pop_rtx ; RTX_FRAME_RELATED_P ( pop_rtx ) = <NUM_LIT> ; offset = offset + <NUM_LIT> ; par_index ++ ; dwarf = alloc_reg_note ( REG_CFA_RESTORE , reg ,


<s> if ( MBBI -> isDebugValue ( ) ) continue ; MachineInstr * NMI = & * MBBI ; <STR_LIT> NCC = getInstrPredicate ( NMI , PredReg ) ; if ( ! ( NCC == CC || NCC == OCC ) || NMI -> modifiesRegister ( SrcReg , & TRI ) || NMI -> modifiesRegister ( <STR_LIT> , & TRI ) ) break ; if ( ++ NumInsts == <NUM_LIT> ) return ; } if (


<s> case MEK_CAPTABLE20 : case MEK_CAPTABLE_HI16 : case MEK_CAPTABLE_LO16 : if ( const <ISA_LIT>MCExpr * E = dyn_cast < const <ISA_LIT>MCExpr > ( getSubExpr ( ) ) ) E -> fixELFSymbolsInTLSFixups ( Asm ) ; break ; case MEK_DTPREL : case MEK_DTPREL_HI : case MEK_DTPREL_LO : case MEK_TLSLDM : case MEK_TLSGD : case MEK_GOTTPREL : case MEK_TPREL_HI : case MEK_TPREL_LO : case MEK_CAPTAB_TLSGD_HI16 : case MEK_CAPTAB_TLSGD_LO16


<s> unsigned <ISA_LIT>TargetLowering :: getExceptionPointerRegister ( const Constant * PersonalityFn ) const { return <STR_LIT>


<s> uint64_t Disp = Field & <NUM_LIT> ; assert ( Length < <NUM_LIT> && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: createReg ( Base == <NUM_LIT> ? <NUM_LIT> : Regs [ Base ] ) ) ; Inst . addOperand ( MCOperand :: createImm ( Disp ) ) ; Inst . addOperand ( MCOperand :: createImm (


<s> const char * getPassName ( ) const override { return


<s> void <ISA_LIT>AsmPrinter :: EmitFunctionBodyStart ( ) { MCInstLowering . Initialize ( Mang , & MF ->


<s> rtx temp = ! can_create_pseudo_p ( ) ? operands [ <NUM_LIT> ] : gen_reg_rtx ( Pmode ) ; if ( GET_CODE ( operands [ <NUM_LIT> ] ) == MEM ) operands [ <NUM_LIT> ] = force_reg ( Pmode , operands [ <NUM_LIT> ] ) ; else if ( TLS_SYMBOLIC_CONST ( operands [ <NUM_LIT> ] ) ) operands [ <NUM_LIT> ] = legitimize_tls_address ( operands [ <NUM_LIT>


<s> int constantpool_mem_p ( rtx op ) { if ( GET_CODE ( op ) == SUBREG ) op


<s> if ( MO . isImm ( ) ) return MO . getImm ( ) ; assert ( MO .


<s> TBB -> addSuccessor ( Sink ) ; BuildMI ( BB , DL , TII -> get ( BranchOp ) ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addMBB ( TBB ) ; unsigned RD1 = RegInfo . createVirtualRegister ( RC ) ; BuildMI ( * FBB , FBB -> end ( ) , DL , TII -> get ( <STR_LIT> ) , RD1 ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ; BuildMI ( * FBB , FBB -> end ( ) , DL , TII -> get ( <STR_LIT> ) ) . addMBB ( Sink ) ; unsigned RD2 = RegInfo . createVirtualRegister ( RC ) ; BuildMI ( * TBB , TBB -> end ( ) , DL , TII -> get ( <STR_LIT> ) , RD2 ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ; BuildMI ( * Sink , Sink -> begin ( ) , DL , TII -> get ( <STR_LIT> ) , MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( RD1 ) . addMBB ( FBB ) . addReg ( RD2 ) . addMBB ( TBB ) ; MI -> eraseFromParent


<s> auto_vec < basic_block > spanlist ; spanlist . reserve ( blocks . length ( ) ) ; for ( ix = <NUM_LIT> ; blocks . iterate ( ix , & block ) ; ix ++ ) { if ( BB_GET_SESE ( block ) ) continue ; if ( dump_file ) fprintf ( dump_file , <STR_LIT> , block -> index ) ; int depth = nvptx_sese_number ( <NUM_LIT> , <NUM_LIT> , + <NUM_LIT> , block , & spanlist ) ; while ( spanlist . length ( ) ) { block = spanlist . pop ( ) ; bb_sese * sese = BB_GET_SESE ( block ) ; nvptx_sese_pseudo ( block , sese , depth , + <NUM_LIT> , sese -> dir > <NUM_LIT> ? block -> succs : block -> preds , ( sese -> dir > <NUM_LIT> ? offsetof ( edge_def , dest ) : offsetof ( edge_def , src ) ) ) ; sese -> set_color ( color_counts ) ; nvptx_sese_pseudo ( block , sese , depth , - <NUM_LIT> , sese -> dir < <NUM_LIT> ? block -> succs : block -> preds , ( sese -> dir < <NUM_LIT> ? offsetof ( edge_def , dest ) : offsetof ( edge_def , src ) ) ) ; } if ( dump_file ) fprintf ( dump_file , <STR_LIT> ) ; } if ( dump_file ) { unsigned count ; const char * comma = <STR_LIT> ; fprintf ( dump_file , <STR_LIT> , color_counts . length ( ) ) ; for ( ix = <NUM_LIT> ; color_counts . iterate ( ix , & count ) ; ix ++ ) { fprintf ( dump_file , <STR_LIT> , comma , ix , count ) ; comma = <STR_LIT> ; for ( unsigned jx = <NUM_LIT> ; blocks . iterate ( jx , & block ) ; jx ++ ) if ( BB_GET_SESE ( block ) -> color == ix ) { block -> flags |= BB_VISITED ; fprintf ( dump_file , <STR_LIT> , comma , block -> index ) ; comma = <STR_LIT> ; } fprintf ( dump_file ,


<s> assert ( VT == <STR_LIT> || VT == <STR_LIT> ) ; unsigned Opc = ( VT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; SDValue CarryIn = N -> getOperand ( <NUM_LIT> ) ; SDValue VCC = CurDAG -> getCopyToReg ( CurDAG -> getEntryNode ( ) , SL , <STR_LIT> , CarryIn , SDValue ( ) ) ; SDValue Ops [ <NUM_LIT> ] ; SelectVOP3Mods0 ( N -> getOperand ( <NUM_LIT> ) , Ops [ <NUM_LIT> ] , Ops [ <NUM_LIT> ] , Ops [


<s> AU . addRequired < MachineDominanceFrontier > ( ) ; AU . setPreservesAll


<s> if ( Subtarget . hasDirectMove ( ) && Subtarget . is<ISA_LIT>64 ( ) ) return LowerFP_TO_INTDirectMove ( Op , DAG , dl ) ; ReuseLoadInfo RLI ; LowerFP_TO_INTForReuse ( Op , RLI , DAG , dl ) ; return DAG . getLoad ( Op . getValueType ( ) , dl , RLI . Chain , RLI . Ptr , RLI . MPI , RLI .

Alignment , RLI . MMOFlags ( ) , RLI . AAInfo , RLI . Ranges ) ;


<s> MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; const auto & TRI = * MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getRegisterInfo ( ) ; bool Changed = false ; assert ( ! mustPreserveAnalysisID ( LiveIntervalsID ) && <STR_LIT> ) ; MRI . leaveSSA ( ) ; MRI . invalidateLiveness ( ) ; for ( unsigned PReg = <STR_LIT> + <NUM_LIT> ; PReg < <STR_LIT> ; ++ PReg ) { if ( PReg == <STR_LIT> || PReg == <STR_LIT> ) continue ; const TargetRegisterClass * RC = TRI . getMinimalPhysRegClass ( PReg ) ; unsigned VReg = <STR_LIT> ; for ( auto I = MRI . reg_begin ( PReg ) , E = MRI . reg_end ( ) ; I != E ; ) { MachineOperand & MO = * I ++ ; if ( ! MO . isImplicit ( ) ) { if ( VReg == <STR_LIT> ) VReg = MRI . createVirtualRegister ( RC ) ; MO . setReg ( VReg


<s> unsigned off18_0 = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned off18_1 = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned off18_2 = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned off18_3 = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned off18 = ( off18_0 << <NUM_LIT> ) | ( off18_1 << <NUM_LIT> ) | ( off18_2 << <NUM_LIT> ) | ( off18_3 << <NUM_LIT> ) ; unsigned s1_d = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned is32Bit = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; if ( ! is32Bit ) return MCDisassembler :: Fail ; switch ( Inst . getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : status = DecodeAddrRegsRegisterClass ( Inst , s1_d , Address , Decoder ) ; break ; case <STR_LIT> : case <STR_LIT> : status = DecodeExtRegsRegisterClass ( Inst , s1_d , Address , Decoder ) ; break ; case <STR_LIT> : case <STR_LIT> : status = DecodePairAddrRegsRegisterClass ( Inst , s1_d , Address , Decoder ) ; break ; default : status = DecodeDataRegsRegisterClass ( Inst , s1_d , Address , Decoder ) ; break ; } if ( status != MCDisassembler ::


<s> unsigned Imm = MI -> getOperand ( OpNo ) . getImm ( ) ; if ( ! Imm ) return ; O << <STR_LIT> <<


<s> static bool classof ( const MCExpr *


<s> case D11 : case D10 : case D9 : case D8 : case D7 : case D6 : case D5 : case D4 : case D3 : case D2 : case D1 : case D0 : case D31 : case D30 : case D29 : case D28 : case D27 : case D26 : case D25 : case D24 : case D23 : case D22 : case D21 : case D20 : case D19 : case D18 : case


<s> unsigned <ISA_LIT>CodeEmitter :: getSimm19Lsl2Encoding ( const MachineInstr & MI , unsigned


<s> } for ( aedges :: iterator i ( BackEdges . begin ( ) ) , ie ( BackEdges . end ( ) ) ; i != ie ; i ++ ) { rewriteEdge ( i -> second -> Src ,


<s> MatchClassKind Expected = static_cast < MatchClassKind > ( ExpectedKind ) ; if ( Op . isImm ( ) ) { if ( MCConstantExpr const * Const = dyn_cast < MCConstantExpr > ( Op . getImm ( ) ) ) { int64_t RegNum = Const -> getValue ( ) ; std :: ostringstream RegName ; RegName << <STR_LIT> << RegNum ; RegNum = MatchRegisterName ( RegName . str ( ) . c_str ( ) ) ; if ( RegNum != <STR_LIT> ) { Op . makeReg ( RegNum ) ; if ( validateOperandClass ( Op , Expected ) == Match_Success ) { return Match_Success ; } } } } if ( Op . isReg ( ) ) { if ( isSubclass ( Expected , MCK_DREGS ) ) { unsigned correspondingDREG = toDREG ( Op . getReg ( ) ) ; if ( correspondingDREG != <STR_LIT> ) { Op . makeReg ( correspondingDREG )


<s> DEBUG ( dbgs ( ) << <STR_LIT> ) ; bool Changed = false ; Changed |= peepholeOpt ( MF ) ; return Changed


<s> StringRef getPassName ( ) const override { return


<s> <ISA_LIT>ELFMCAsmInfo :: <ISA_LIT>ELFMCAsmInfo ( bool is64Bit , const Triple & T ) { if ( is64Bit ) { PointerSize = CalleeSaveStackSlotSize = <NUM_LIT> ; } IsLittleEndian = T . getArch ( ) == Triple :: ppc64le ; AlignmentIsInBytes = false ; CommentString = <STR_LIT> ; UsesELFSectionDirectiveForBSS = true ; SupportsDebugInformation = true ; DollarIsPC = true ; MinInstAlignment = <NUM_LIT> ; ExceptionsType = ExceptionHandling :: DwarfCFI ; ZeroDirective = <STR_LIT> ; Data64bitsDirective = is64Bit ? <STR_LIT> : nullptr ; AssemblerDialect = <NUM_LIT> ; LCOMMDirectiveAlignmentType = LCOMM ::


<s> Opc = <STR_LIT> ; } else { assert ( <NUM_LIT> && <STR_LIT> ) ; } DebugLoc DL = DebugLoc :: getUnknownLoc ( ) ; MachineInstrBuilder MIB = BuildMI ( MF , DL , get ( Opc ) ) ; for ( unsigned i = <NUM_LIT> , e = Addr . size ( ) ; i != e ; ++ i ) MIB . addOperand ( Addr [ i ] ) ; MIB . addReg ( SrcReg , getKillRegState (


<s> if ( ( Name . find ( getTagName ( LIBCALL ) ) != std :: string :: npos )

|| isMemIntrinsic ( Name ) ) return true ;


<s> case fixup_<ISA_LIT>_B7_PCREL : case fixup_<ISA_LIT>_B13_PCREL : case fixup_<ISA_LIT>_B9_PCREL : case fixup_<ISA_LIT>_B32_PCREL_X : case fixup_<ISA_LIT>_B22_PCREL_X : case fixup_<ISA_LIT>_B15_PCREL_X : case fixup_<ISA_LIT>_B13_PCREL_X : case fixup_<ISA_LIT>_B9_PCREL_X : case fixup_<ISA_LIT>_B7_PCREL_X : case fixup_<ISA_LIT>_32_PCREL : case fixup_<ISA_LIT>_PLT_B22_PCREL : case fixup_<ISA_LIT>_GD_PLT_B22_PCREL : case


<s> if ( V -> getType ( ) -> isFloatTy ( ) ) { unsigned OpReg = getRegForValue ( V ) ; if ( OpReg == <NUM_LIT> ) return false ; unsigned ResultReg = createResultReg ( <STR_LIT> ) ; BuildMI ( MBB , DL , TII . get ( <STR_LIT> ) , ResultReg ) . addReg ( OpReg ) ; UpdateValueMap ( I , ResultReg ) ; return true ; } } return


<s> static DecodeStatus DecodeDoubleRegsRegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t , const void * Decoder ) { static const uint16_t DoubleRegDecoderTable [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT>


<s> if ( ! gpr_or_gpr_p ( operands [ <NUM_LIT> ] , operands


<s> static __inline __m128i __attribute__ ( ( __always_inline__ ) ) _mm_loadu_si128 ( __m128i const * __P ) { return ( __m128i ) __builtin_ia32_loaddqu ( ( char const *


<s> MVT VT = Op . getSimpleValueType ( ) ; assert ( ( Op . getOpcode ( ) == <STR_LIT> || Op . getOpcode ( ) == <STR_LIT> ) && <STR_LIT> ) ; assert ( ( VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> ) && <STR_LIT> ) ; SDLoc DL ( Op ) ; SDValue Op0 = Op . getOperand ( <NUM_LIT> ) ; SDValue Op1 = Op . getOperand ( <NUM_LIT> ) ; SDValue Amt = Op . getOperand ( <NUM_LIT> ) ; bool OptForSize = DAG . getMachineFunction ( ) . getFunction ( ) . optForSize ( ) ; if ( ! OptForSize && Subtarget . isSHLDSlow ( ) ) return SDValue ( ) ; bool IsFSHR = Op . getOpcode ( ) == <STR_LIT> ; if ( IsFSHR ) std :: swap ( Op0 , Op1 ) ; if ( VT == <STR_LIT> ) Amt = DAG . getNode ( <STR_LIT> , DL , Amt . getValueType ( ) , Amt , DAG . getConstant ( <NUM_LIT> , DL , Amt . getValueType ( ) ) ) ; unsigned SHDOp = ( IsFSHR ? <STR_LIT> : <STR_LIT> ) ; return DAG . getNode ( SHDOp , DL , VT , Op0 ,


<s> if ( cfun -> machine -> indirect_branch_type != indirect_branch_keep && ( cfun -> machine -> indirect_branch_type != indirect_branch_thunk_extern ) && ( flag_cf_protection & CF_RETURN ) ) error ( <STR_LIT> <STR_LIT> ) ; } if ( cfun -> machine -> function_return_type == indirect_branch_unset ) { tree attr = lookup_attribute ( <STR_LIT> , DECL_ATTRIBUTES ( fndecl ) ) ; if ( attr != NULL ) { tree args = TREE_VALUE ( attr ) ; if ( args == NULL ) gcc_unreachable ( ) ; tree cst = TREE_VALUE ( args ) ; if ( strcmp ( TREE_STRING_POINTER ( cst ) , <STR_LIT> ) == <NUM_LIT> ) cfun -> machine -> function_return_type = indirect_branch_keep ; else if ( strcmp ( TREE_STRING_POINTER ( cst ) , <STR_LIT> ) == <NUM_LIT> ) cfun -> machine -> function_return_type = indirect_branch_thunk ; else if ( strcmp ( TREE_STRING_POINTER ( cst ) , <STR_LIT> ) == <NUM_LIT> ) cfun -> machine -> function_return_type = indirect_branch_thunk_inline ; else if ( strcmp ( TREE_STRING_POINTER ( cst ) , <STR_LIT> ) == <NUM_LIT> ) cfun -> machine -> function_return_type = indirect_branch_thunk_extern ; else gcc_unreachable ( ) ; } else cfun -> machine -> function_return_type = ix86_function_return ; if ( ( ix86_cmodel == CM_LARGE || ix86_cmodel == CM_LARGE_PIC ) && ( ( cfun -> machine -> function_return_type == indirect_branch_thunk_extern ) || ( cfun -> machine -> function_return_type == indirect_branch_thunk ) ) ) error ( <STR_LIT> <STR_LIT> , ( ( cfun -> machine -> function_return_type == indirect_branch_thunk_extern ) ? <STR_LIT> : <STR_LIT> ) ) ; if ( cfun -> machine -> function_return_type != indirect_branch_keep && ( cfun -> machine -> function_return_type != indirect_branch_thunk_extern ) &&


<s> if ( Op -> getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> || cast < ConstantSDNode > ( Op -> getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) != <NUM_LIT> || Op -> getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; MachineFrameInfo * MFI = DAG . getMachineFunction ( ) . getFrameInfo ( ) ; EVT ValTy = Op -> getValueType ( <NUM_LIT> ) ; int FI = MFI -> CreateFixedObject ( Op . getValueSizeInBits ( ) / <NUM_LIT> , <NUM_LIT> , false ) ; SDValue InArgsAddr = DAG . getFrameIndex (


<s> switch ( Opc ) { case TargetOpcode :: G_SMIN : case TargetOpcode :: G_SMAX : return TargetOpcode :: G_SEXT ; case TargetOpcode :: G_UMIN : case TargetOpcode


<s> SDValue SDImm = CurDAG -> getTargetConstant ( Inst . Imm , DL , XLenVT ) ; if ( Inst . Opc == <STR_LIT> ) Result = CurDAG -> getMachineNode ( <STR_LIT> , DL , XLenVT , SDImm ) ; else if ( Inst . Opc == <STR_LIT> ) Result = CurDAG -> getMachineNode ( <STR_LIT> , DL , XLenVT , SrcReg , CurDAG -> getRegister ( <STR_LIT> , XLenVT ) ) ; else if ( Inst . Opc == <STR_LIT> || Inst . Opc == <STR_LIT> || Inst . Opc == <STR_LIT> ) Result = CurDAG -> getMachineNode ( Inst . Opc , DL , XLenVT , SrcReg , SrcReg ) ; else Result = CurDAG -> getMachineNode ( Inst . Opc , DL , XLenVT , SrcReg , SDImm ) ; SrcReg = SDValue ( Result , <NUM_LIT> ) ; } return


<s> if ( PSPI -> isConverting ( MF ) && STC . enableBundling ( TM . getOptLevel ( ) ) ) { SPBlocks += MF . size (


<s> case A2_addh_l16_hl : case A2_addh_l16_sat_hl : case A2_subh_l16_hl : case A2_subh_l16_sat_hl : if ( OpN == <NUM_LIT> ) { Bits . set ( Begin , Begin + <NUM_LIT> ) ; return true ; } if ( OpN == <NUM_LIT> ) { Bits . set ( Begin + <NUM_LIT> , Begin + <NUM_LIT> ) ; return true ; } break ; case A2_addh_h16_hl : case A2_addh_h16_sat_hl : case A2_combine_hl : case A2_subh_h16_hl : case A2_subh_h16_sat_hl : case M2_mpy_acc_hl_s0 : case M2_mpy_acc_hl_s1 : case M2_mpy_acc_sat_hl_s0 : case M2_mpy_acc_sat_hl_s1 : case M2_mpy_hl_s0 : case M2_mpy_hl_s1 : case M2_mpy_nac_hl_s0 : case M2_mpy_nac_hl_s1 : case M2_mpy_nac_sat_hl_s0 : case M2_mpy_nac_sat_hl_s1 : case M2_mpy_rnd_hl_s0 : case M2_mpy_rnd_hl_s1 : case M2_mpy_sat_hl_s0 : case M2_mpy_sat_hl_s1 : case M2_mpy_sat_rnd_hl_s0 : case M2_mpy_sat_rnd_hl_s1 : case M2_mpyd_acc_hl_s0 : case M2_mpyd_acc_hl_s1 : case M2_mpyd_hl_s0 : case M2_mpyd_hl_s1 : case M2_mpyd_nac_hl_s0 : case M2_mpyd_nac_hl_s1 : case M2_mpyd_rnd_hl_s0 : case M2_mpyd_rnd_hl_s1 : case M2_mpyu_acc_hl_s0 : case M2_mpyu_acc_hl_s1 : case M2_mpyu_hl_s0 : case M2_mpyu_hl_s1 : case M2_mpyu_nac_hl_s0 : case M2_mpyu_nac_hl_s1 : case M2_mpyud_acc_hl_s0 : case M2_mpyud_acc_hl_s1 : case M2_mpyud_hl_s0 : case M2_mpyud_hl_s1 : case M2_mpyud_nac_hl_s0 : case M2_mpyud_nac_hl_s1 : if ( OpN == <NUM_LIT> ) { Bits . set ( Begin + <NUM_LIT> , Begin + <NUM_LIT> ) ; return true ; } if ( OpN == <NUM_LIT> ) { Bits . set ( Begin , Begin + <NUM_LIT> ) ; return true ; } break ; case A2_addh_h16_hh : case A2_addh_h16_sat_hh : case A2_combine_hh : case A2_subh_h16_hh : case A2_subh_h16_sat_hh : case M2_mpy_acc_hh_s0 : case M2_mpy_acc_hh_s1 : case M2_mpy_acc_sat_hh_s0 : case M2_mpy_acc_sat_hh_s1 : case M2_mpy_hh_s0 : case M2_mpy_hh_s1 : case M2_mpy_nac_hh_s0 : case M2_mpy_nac_hh_s1 : case M2_mpy_nac_sat_hh_s0 : case M2_mpy_nac_sat_hh_s1 : case M2_mpy_rnd_hh_s0 : case M2_mpy_rnd_hh_s1 : case M2_mpy_sat_hh_s0 : case M2_mpy_sat_hh_s1 : case M2_mpy_sat_rnd_hh_s0 : case M2_mpy_sat_rnd_hh_s1 : case M2_mpyd_acc_hh_s0 : case M2_mpyd_acc_hh_s1 : case M2_mpyd_hh_s0 : case M2_mpyd_hh_s1 : case M2_mpyd_nac_hh_s0 : case M2_mpyd_nac_hh_s1 : case M2_mpyd_rnd_hh_s0 : case M2_mpyd_rnd_hh_s1 : case M2_mpyu_acc_hh_s0 : case M2_mpyu_acc_hh_s1 : case M2_mpyu_hh_s0 : case M2_mpyu_hh_s1 : case M2_mpyu_nac_hh_s0 : case M2_mpyu_nac_hh_s1 : case M2_mpyud_acc_hh_s0 : case M2_mpyud_acc_hh_s1 : case M2_mpyud_hh_s0 : case M2_mpyud_hh_s1 : case M2_mpyud_nac_hh_s0 : case M2_mpyud_nac_hh_s1 : if ( OpN == <NUM_LIT> ||


<s> if ( MO . isImm ( ) ) { const unsigned Imm = MO . getImm ( ) ; const unsigned Lo16 = Imm & <NUM_LIT> ; const unsigned Hi16 = ( Imm >> <NUM_LIT> ) & <NUM_LIT> ; LO16 = LO16 . addImm ( Lo16 ) ; HI16 = HI16 . addImm ( Hi16 ) ; } else { const GlobalValue * GV = MO . getGlobal ( ) ; const unsigned TF = MO . getTargetFlags ( ) ; LO16 = LO16 . addGlobalAddress ( GV , MO . getOffset ( ) , TF | <STR_LIT> ) ; HI16 = HI16 . addGlobalAddress ( GV , MO . getOffset ( ) , TF | <STR_LIT> ) ; } MBB . erase (


<s> if ( DecodeGPR8RegisterClass ( Inst , d , Address , Decoder ) == MCDisassembler :: Fail ) return MCDisassembler :: Fail ; if ( DecodeGPR8RegisterClass ( Inst , d , Address , Decoder


<s> MachineFrameInfo & MFI = FuncInfo . MF -> getFrameInfo ( ) ; MFI . setFrameAddressIsTaken ( true ) ; unsigned LdrOpc = isThumb2 ? <STR_LIT> : <STR_LIT> ; const TargetRegisterClass * RC = isThumb2 ? & <STR_LIT> : & <STR_LIT> ; const <ISA_LIT>BaseRegisterInfo * RegInfo = static_cast < const <ISA_LIT>BaseRegisterInfo * > ( Subtarget -> getRegisterInfo ( ) ) ; Register FramePtr = RegInfo -> getFrameRegister ( * ( FuncInfo . MF ) ) ; unsigned SrcReg = FramePtr ; unsigned DestReg ; unsigned Depth = cast < ConstantInt > ( I . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; while ( Depth -- ) { DestReg = createResultReg ( RC ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( LdrOpc ) , DestReg ) . addReg ( SrcReg ) . addImm ( <NUM_LIT> ) ) ; SrcReg = DestReg ; } updateValueMap ( & I , SrcReg ) ; return true ; } case <STR_LIT> : case <STR_LIT> : { const MemTransferInst & MTI = cast < MemTransferInst > ( I ) ; if ( MTI . isVolatile ( ) ) return false ; bool isMemCpy = ( I . getIntrinsicID ( ) == <STR_LIT> ) ; if ( isa < ConstantInt > ( MTI . getLength ( ) ) && isMemCpy ) { uint64_t Len = cast < ConstantInt > ( MTI . getLength ( ) ) -> getZExtValue ( ) ; if ( <ISA_LIT>IsMemCpySmall ( Len ) ) { Address Dest , Src ; if ( ! <ISA_LIT>ComputeAddress ( MTI . getRawDest ( ) , Dest ) || ! <ISA_LIT>ComputeAddress ( MTI . getRawSource ( ) , Src ) ) return false ; unsigned Alignment = MinAlign ( MTI . getDestAlignment ( ) , MTI . getSourceAlignment ( ) ) ; if ( <ISA_LIT>TryEmitSmallMemCpy ( Dest , Src , Len , Alignment ) ) return true ; } } if ( ! MTI . getLength ( ) -> getType ( ) -> isIntegerTy ( <NUM_LIT> ) ) return false ; if ( MTI . getSourceAddressSpace ( ) > <NUM_LIT> || MTI . getDestAddressSpace ( ) > <NUM_LIT> ) return false ; const char * IntrMemName = isa < MemCpyInst


<s> if ( operands [ <NUM_LIT> ] != const1_rtx && operands [ <NUM_LIT> ] != constm1_rtx ) return false ; if ( ! ix86_expand_carry_flag_compare ( code , op0 , op1 , & compare_op ) ) return false ; code = GET_CODE ( compare_op ) ; flags = XEXP ( compare_op , <NUM_LIT> ) ; if ( GET_MODE ( flags ) == CCFPmode ) { fpcmp = true ; code = ix86_fp_compare_code_to_integer ( code ) ; } if ( code != LTU ) { val = constm1_rtx ; if ( fpcmp ) PUT_CODE ( compare_op , reverse_condition_maybe_unordered ( GET_CODE ( compare_op ) ) ) ; else PUT_CODE ( compare_op , reverse_condition ( GET_CODE ( compare_op ) ) ) ; } mode = GET_MODE ( operands [ <NUM_LIT> ] ) ; if ( ( code == LTU ) == ( operands [ <NUM_LIT> ] == constm1_rtx ) ) { switch ( mode ) { case E_QImode : insn = gen_subqi3_carry ; break ; case E_HImode : insn = gen_subhi3_carry ; break ; case E_SImode : insn = gen_subsi3_carry ; break ; case E_DImode : insn = gen_subdi3_carry ; break ; default : gcc_unreachable ( ) ; } } else { switch ( mode ) { case E_QImode : insn = gen_addqi3_carry


<s> } TII = ( const <ISA_LIT>16InstrInfo * ) STI -> getInstrInfo ( ) ; MFI = MF -> getInfo < <ISA_LIT>FunctionInfo > ( ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << <STR_LIT> ) ; if ( ! PrescannedForConstants ) prescanForConstants ( ) ; HasFarJump = false ; MF -> getRegInfo ( ) . invalidateLiveness ( ) ; MF -> RenumberBlocks ( ) ; bool MadeChange = false ; std :: vector < MachineInstr * > CPEMIs ; if ( ! MCP -> isEmpty ( ) ) doInitialPlacement ( CPEMIs ) ; initPICLabelUId ( CPEMIs . size ( ) ) ; initializeFunctionInfo ( CPEMIs ) ; CPEMIs . clear ( ) ; LLVM_DEBUG ( dumpBBs ( ) ) ; MadeChange |= removeUnusedCPEntries ( ) ; unsigned NoCPIters = <NUM_LIT> , NoBRIters = <NUM_LIT> ; ( void ) NoBRIters ; while ( true ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << NoCPIters << '\n' ) ; bool CPChange = false ; for ( unsigned i = <NUM_LIT> , e = CPUsers . size ( ) ; i != e ; ++ i ) CPChange |= handleConstantPoolUser ( i ) ; if ( CPChange && ++ NoCPIters > <NUM_LIT> ) report_fatal_error ( <STR_LIT> ) ; LLVM_DEBUG ( dumpBBs ( )


<s> if ( return_in_pc ) XVECEXP ( par , <NUM_LIT> , <NUM_LIT> ) = ret_rtx ; if ( emit_update ) { tmp = gen_rtx_SET ( stack_pointer_rtx , plus_constant ( Pmode , stack_pointer_rtx , <NUM_LIT> * num_regs ) ) ; RTX_FRAME_RELATED_P ( tmp ) = <NUM_LIT> ; XVECEXP ( par , <NUM_LIT> , offset_adj ) = tmp ; } for ( j = <NUM_LIT> , i = <NUM_LIT> ; j < num_regs ; i ++ ) if ( saved_regs_mask & ( <NUM_LIT> << i ) ) { rtx dwarf_reg = reg = gen_rtx_REG ( SImode , i ) ; if ( arm_current_function_pac_enabled_p ( ) && i == IP_REGNUM ) dwarf_reg = gen_rtx_REG ( SImode , RA_AUTH_CODE ) ; if ( ( num_regs == <NUM_LIT> ) && emit_update && ! return_in_pc ) { tmp = gen_frame_mem ( SImode , gen_rtx_POST_INC ( Pmode , stack_pointer_rtx ) ) ; tmp = emit_insn ( gen_rtx_SET ( reg , tmp ) ) ; REG_NOTES ( tmp ) = alloc_reg_note ( REG_CFA_RESTORE , dwarf_reg , dwarf ) ; return ; } tmp = gen_rtx_SET ( reg , gen_frame_mem ( SImode , plus_constant ( Pmode , stack_pointer_rtx , <NUM_LIT> * j ) ) ) ; RTX_FRAME_RELATED_P ( tmp ) = <NUM_LIT> ; XVECEXP ( par , <NUM_LIT> , j + emit_update + offset_adj ) = tmp ; if ( i != PC_REGNUM ) dwarf = alloc_reg_note ( REG_CFA_RESTORE , dwarf_reg , dwarf ) ; j ++ ; } if ( return_in_pc ) par = emit_jump_insn ( par ) ; else par = emit_insn ( par ) ; REG_NOTES ( par ) =


<s> const MCOperand & ScaleOp = MI -> getOperand ( OpNum ) ; O << '#' << ( <NUM_LIT> - ScaleOp .


<s> llvm :: FastISel * <STR_LIT> ( FunctionLoweringInfo & FuncInfo , const TargetLibraryInfo * LibInfo


<s> if ( Items . empty ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; } else { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; Items . back ( ) -> dump ( ) ) ; } Mask |= ( <NUM_LIT> << TI -> getIndex ( )


<s> int ShiftRegBytes = TRI -> getRegSizeInBits ( ShiftRC ) / <NUM_LIT> ; unsigned DefSubRegImm = SubRegImms [ Log2_32 ( DefRegBytes ) ] ; unsigned StateReg = GetStateRegInRC ( ShiftRC ) ; unsigned TmpReg = MRI -> createVirtualRegister ( DefRC ) ; DefOp . setReg ( TmpReg ) ; unsigned ShiftInputReg = TmpReg ; if ( DefRegBytes != ShiftRegBytes ) { unsigned UndefReg = MRI -> createVirtualRegister ( & ShiftRC ) ; BuildMI ( MBB , InsertPt , Loc , TII -> get ( <STR_LIT> ) , UndefReg ) ; ShiftInputReg = MRI -> createVirtualRegister ( & ShiftRC ) ; BuildMI ( MBB , InsertPt , Loc , TII -> get ( <STR_LIT> ) , ShiftInputReg ) . addReg ( UndefReg ) . addReg ( TmpReg ) . addImm ( DefSubRegImm ) ; } unsigned ShiftedReg = MRI -> createVirtualRegister ( & ShiftRC ) ; auto Shift1I = BuildMI ( MBB , InsertPt , Loc , TII -> get ( ShiftOpCode ) , ShiftedReg ) . addReg ( ShiftInputReg ) . addReg ( StateReg ) ; ( void ) Shift1I ; ++ NumInstsInserted ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; Shift1I -> dump ( ) ; dbgs ( ) << <STR_LIT> ) ; if ( DefRegBytes == ShiftRegBytes ) { ShiftInputReg = ShiftedReg ; auto Shift2I = BuildMI ( MBB , InsertPt , Loc , TII -> get ( ShiftOpCode ) , OldDefReg ) . addReg ( ShiftInputReg ) . addReg ( StateReg ) ; ( void ) Shift2I


<s> unsigned <ISA_LIT>RegisterInfo :: getFrameRegister ( const MachineFunction & ) const { return <STR_LIT>


<s> return __builtin_aarch64_fmulxsf ( __a ,


<s> std :: string Buffer ; { raw_string_ostream TempStream ( Buffer ) ; RawPrinter -> printInst ( MI , TempStream , <STR_LIT> , STI ) ; } StringRef Contents ( Buffer ) ; auto PacketBundle = Contents . rsplit ( '\n' ) ; auto HeadTail = PacketBundle . first . split ( '\n' ) ; auto Preamble = <STR_LIT> ; auto Separator = <STR_LIT> ; while ( ! HeadTail . first . empty ( ) ) { O << Separator ; StringRef Inst ; auto Duplex = HeadTail . first . split ( '\v' ) ; if ( ! Duplex . second . empty ( ) ) { O << Duplex . first << <STR_LIT> ; Inst = Duplex . second ; } else Inst = Duplex . first ; O <<


<s> unsigned Imm = Bits >> <NUM_LIT> ; if ( DecodeGR16RegisterClass ( MI , Reg , Address , Decoder ) != MCDisassembler :: Success ) return MCDisassembler :: Fail ; MI . addOperand ( MCOperand :: createImm ( ( int16_t ) Imm


<s> return ( __m512d ) __builtin_ia32_vfmaddpd512_maskz ( - ( __v8df ) __A , ( __v8df )


<s> assert ( OrigArg . Regs . size ( ) == SplitVTs . size ( ) ) ; int SplitIdx = <NUM_LIT> ; for ( EVT VT : SplitVTs ) { Register Reg = OrigArg . Regs [ SplitIdx ] ; Type * Ty = VT . getTypeForEVT ( Ctx ) ; LLT LLTy = getLLTForType ( * Ty , DL ) ; if ( OrigArgIdx == AttributeList :: ReturnIndex && VT . isScalarInteger ( ) ) { unsigned ExtendOp = TargetOpcode :: G_ANYEXT ; if ( OrigArg . Flags [ <NUM_LIT> ] . isSExt ( ) ) { assert ( OrigArg . Regs . size ( ) == <NUM_LIT> && <STR_LIT> ) ; ExtendOp = TargetOpcode :: G_SEXT ; } else if ( OrigArg . Flags [ <NUM_LIT> ] . isZExt ( ) ) { assert ( OrigArg . Regs . size ( ) == <NUM_LIT> && <STR_LIT> ) ; ExtendOp = TargetOpcode :: G_ZEXT ; } EVT ExtVT = TLI . getTypeForExtReturn ( Ctx , VT , extOpcodeToISDExtOpcode ( ExtendOp ) ) ; if ( ExtVT != VT ) { VT = ExtVT ; Ty = ExtVT . getTypeForEVT ( Ctx ) ; LLTy = getLLTForType ( * Ty , DL ) ; Reg = B . buildInstr ( ExtendOp , { LLTy } , { Reg } ) . getReg ( <NUM_LIT> ) ; } } unsigned NumParts = TLI . getNumRegistersForCallingConv ( Ctx , CallConv , VT ) ; MVT RegVT = TLI . getRegisterTypeForCallingConv ( Ctx , CallConv , VT ) ; if ( NumParts == <NUM_LIT> ) { SplitArgs . emplace_back ( Reg , Ty , OrigArg . Flags , OrigArg . IsFixed ) ; ++ SplitIdx ; continue ; } SmallVector < Register , <NUM_LIT> > SplitRegs ; Type * PartTy = EVT ( RegVT ) . getTypeForEVT ( Ctx ) ; LLT PartLLT = getLLTForType ( * PartTy , DL ) ; MachineRegisterInfo & MRI = * B . getMRI ( ) ; for ( unsigned i = <NUM_LIT> ; i < NumParts ; ++ i