<s> RTLIB :: Libcall LC ; LC = RTLIB :: getFPROUND ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) , Op . getValueType ( ) ) ; SDValue SrcVal = Op . getOperand ( <NUM_LIT> ) ; return makeLibCall ( DAG , LC , Op . getValueType ( ) , &

SrcVal , <NUM_LIT> , false , SDLoc ( Op ) ) . first ;


<s> static SDValue combine<ISA_LIT>ShufflesRecursively ( SDValue Op , SelectionDAG & DAG , const <ISA_LIT>Subtarget & Subtarget ) { return combine<ISA_LIT>ShufflesRecursively ( { Op } , <NUM_LIT> , Op , { <NUM_LIT> } ,

{ } , <NUM_LIT> , false , true , DAG , Subtarget ) ;


<s> if ( ! isABI ) return Chain ; const DataLayout & DL = DAG . getDataLayout ( ) ; SmallVector < EVT , <NUM_LIT> > VTs ; SmallVector < uint64_t , <NUM_LIT> > Offsets ; ComputePTXValueVTs ( * this , DL , RetTy , VTs , & Offsets ) ; assert ( VTs . size ( ) == OutVals . size ( ) && <STR_LIT> ) ; auto VectorInfo = VectorizePTXValueVTs ( VTs , Offsets , RetTy -> isSized ( ) ? DL . getABITypeAlign ( RetTy ) : Align ( <NUM_LIT> ) ) ; bool ExtendIntegerRetVal = RetTy -> isIntegerTy ( ) && DL . getTypeAllocSizeInBits ( RetTy ) < <NUM_LIT> ; SmallVector < SDValue , <NUM_LIT> > StoreOperands ; for ( unsigned i = <NUM_LIT> , e = VTs . size ( ) ; i != e ; ++ i ) { if ( VectorInfo [ i ] & PVF_FIRST ) { assert ( StoreOperands . empty ( ) && <STR_LIT> ) ; StoreOperands . push_back ( Chain ) ; StoreOperands . push_back ( DAG . getConstant ( Offsets [ i ] , dl , <STR_LIT> ) ) ; } SDValue RetVal = OutVals [ i ] ; if ( ExtendIntegerRetVal ) { RetVal = DAG . getNode ( Outs [ i ] . Flags . isSExt ( ) ? <STR_LIT> : <STR_LIT> , dl , <STR_LIT> , RetVal ) ; } else if ( RetVal . getValueSizeInBits ( ) < <NUM_LIT> ) { RetVal = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , RetVal ) ; } StoreOperands . push_back ( RetVal ) ; if ( VectorInfo [ i ] & PVF_LAST ) { <STR_LIT> Op ; unsigned NumElts = StoreOperands . size ( ) - <NUM_LIT> ; switch ( NumElts ) { case <NUM_LIT>


<s> bool Imm = false ; if ( ! SelectSMRD ( Addr , SBase , Offset


<s> if ( isa < PHINode > ( In ) || ( To != Block . end ( ) && isa < PHINode > ( * To ) ) ) return false ; if ( ! mayHaveNonDefUseDependency ( In ) ) return true ; bool MayWrite = In . mayWriteToMemory ( ) ; auto MaybeLoc = getLocOrNone ( In ) ; auto From = In . getIterator ( ) ; if ( From == To ) return true ; bool MoveUp = ( To != Block . end ( ) && To -> comesBefore ( & In ) ) ; auto Range = MoveUp ? std :: make_pair ( To , From ) : std :: make_pair ( std :: next ( From ) , To ) ; for ( auto It = Range . first ; It != Range . second ; ++ It ) { const Instruction & I = * It ; if ( llvm :: is_contained ( Ignore , & I ) ) continue ; if ( auto * II = dyn_cast < IntrinsicInst > ( & I ) ) { if ( II -> getIntrinsicID ( ) == <STR_LIT> ) continue ; } if ( I . mayThrow ( ) ) return false ; if ( auto * CB = dyn_cast < CallBase > ( & I ) ) { if ( ! CB -> hasFnAttr ( Attribute :: WillReturn ) ) return false ; if ( ! CB -> hasFnAttr ( Attribute :: NoSync ) ) return false ; } if ( I . mayReadOrWriteMemory ( ) ) { auto MaybeLocI = getLocOrNone ( I ) ; if ( MayWrite || I . mayWriteToMemory ( ) ) { if ( ! MaybeLoc || ! MaybeLocI ) return false ; if ( ! AA . isNoAlias ( * MaybeLoc , * MaybeLocI


<s> unsigned decodeExpcnt ( IsaVersion Version , unsigned Waitcnt ) { return unpackBits ( Waitcnt , getExpcntBitShift (


<s> else if ( ( code == POST_MODIFY || code == PRE_MODIFY ) && arm_address_register_rtx_p ( XEXP ( x , <NUM_LIT> ) , strict_p ) && GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == PLUS && rtx_equal_p ( XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) , XEXP ( x , <NUM_LIT> ) ) ) { rtx addend = XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) ; HOST_WIDE_INT offset ; if ( ! CONST_INT_P ( addend ) ) return <NUM_LIT> ; offset = INTVAL ( addend ) ; if ( GET_MODE_SIZE ( mode ) <= <NUM_LIT> ) return ( offset > - <NUM_LIT> && offset < <NUM_LIT> ) ; return ( use_ldrd && offset > - <NUM_LIT> && offset < <NUM_LIT> && ( offset & <NUM_LIT> ) == <NUM_LIT> ) ; } else if ( reload_completed && ( code == LABEL_REF || ( code == CONST && GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == PLUS && GET_CODE ( XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) ) == LABEL_REF && CONST_INT_P ( XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) ) ) ) ) return <NUM_LIT> ; else if ( mode == TImode || ( TARGET_NEON && VALID_NEON_STRUCT_MODE ( mode ) ) ) return <NUM_LIT> ; else if ( code == PLUS )


<s> if ( flags & MASK_UNALIGNED_DOUBLES ) fprintf ( stderr , <STR_LIT> ) ; if ( flags & MASK_V8PLUS ) fprintf ( stderr , <STR_LIT> ) ; if ( flags & MASK_VIS ) fprintf ( stderr , <STR_LIT> ) ; if ( flags & MASK_VIS2 ) fprintf ( stderr , <STR_LIT> ) ; if ( flags & MASK_VIS3 ) fprintf ( stderr , <STR_LIT> ) ; if ( flags & MASK_VIS4 ) fprintf ( stderr , <STR_LIT> ) ; if ( flags & MASK_CBCOND ) fprintf ( stderr , <STR_LIT> ) ; if ( flags & MASK_DEPRECATED_V8_INSNS ) fprintf ( stderr , <STR_LIT> ) ; if ( flags & MASK_SPARCLET ) fprintf ( stderr , <STR_LIT> ) ; if ( flags & MASK_SPARCLITE ) fprintf


<s> Builder . SetInsertPoint ( & BB -> back ( ) ) ; Value * ShiftAmount = Builder . CreateTrunc ( BI -> getOperand ( <NUM_LIT> ) , Int8Ty ) ; Value * Cmp1 = Builder . CreateICmpEQ ( ShiftAmount , Int8Zero ) ; Builder . CreateCondBr ( Cmp1 , EndBB , LoopBB ) ; BB -> back ( ) . eraseFromParent ( ) ; Builder . SetInsertPoint ( LoopBB ) ; PHINode * ShiftAmountPHI = Builder . CreatePHI ( Int8Ty , <NUM_LIT> ) ; ShiftAmountPHI -> addIncoming ( ShiftAmount , BB ) ; PHINode * ValuePHI = Builder . CreatePHI ( Int32Ty , <NUM_LIT> ) ; ValuePHI -> addIncoming ( BI -> getOperand ( <NUM_LIT> ) , BB ) ; Value * ShiftAmountSub = Builder . CreateSub ( ShiftAmountPHI , ConstantInt :: get ( Int8Ty , <NUM_LIT> ) ) ; ShiftAmountPHI -> addIncoming ( ShiftAmountSub , LoopBB ) ; Value * ValueShifted ; switch ( BI -> getOpcode ( ) ) { case Instruction :: Shl : ValueShifted = Builder . CreateShl ( ValuePHI , ConstantInt :: get ( Int32Ty , <NUM_LIT> ) ) ; break ; case Instruction :: LShr : ValueShifted = Builder . CreateLShr ( ValuePHI , ConstantInt :: get ( Int32Ty , <NUM_LIT> ) ) ; break ; case Instruction :: AShr : ValueShifted = Builder . CreateAShr ( ValuePHI , ConstantInt :: get ( Int32Ty ,


<s> assert ( Scope != <STR_LIT> && ( OrderingAddrSpace & <STR_LIT> ) != <STR_LIT> && ( InstrAddrSpace & <STR_LIT> ) != <STR_LIT> ) ; if ( ( OrderingAddrSpace == InstrAddrSpace ) && isPowerOf2_32 ( uint32_t ( InstrAddrSpace ) ) ) this -> IsCrossAddressSpaceOrdering = false ; if ( ( InstrAddrSpace & ~ <STR_LIT> ) == <STR_LIT> ) { this -> Scope = std :: min ( Scope , <STR_LIT> ) ; } else if ( ( InstrAddrSpace & ~ ( <STR_LIT> | <STR_LIT> ) ) == <STR_LIT> ) { this -> Scope = std :: min (


<s> static DecodeStatus DecodeGPR32RegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t Addr , const void * Decoder ) { if ( RegNo > <NUM_LIT> ) return


<s> switch ( opts -> x_aarch64_cmodel_var ) { case AARCH64_CMODEL_TINY : if ( opts -> x_flag_pic ) aarch64_cmodel = AARCH64_CMODEL_TINY_PIC ; break ; case AARCH64_CMODEL_SMALL : if ( opts -> x_flag_pic ) { aarch64_cmodel = ( flag_pic == <NUM_LIT>


<s> SDValue V1Mask [ <NUM_LIT> ] ; SDValue V2Mask [ <NUM_LIT> ] ; V1InUse = false ; V2InUse = false ; int Size = Mask . size ( ) ; int Scale = <NUM_LIT> / Size ; for ( int i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) { if ( Mask [ i / Scale ] == - <NUM_LIT> ) { V1Mask [ i ] = V2Mask [ i ] = DAG . getUNDEF ( <STR_LIT> ) ; } else { const int ZeroMask = <NUM_LIT> ; int V1Idx = Mask [ i / Scale ] < Size ? Mask [ i / Scale ] * Scale + i % Scale : ZeroMask ; int V2Idx = Mask [ i / Scale ] < Size ? ZeroMask : ( Mask [ i / Scale ] - Size ) * Scale + i % Scale ; if ( Zeroable [ i / Scale ] ) V1Idx = V2Idx = ZeroMask ; V1Mask [ i ] = DAG . getConstant ( V1Idx , <STR_LIT> ) ; V2Mask [ i ] = DAG . getConstant ( V2Idx , <STR_LIT> ) ; V1InUse |= ( ZeroMask != V1Idx ) ; V2InUse |= ( ZeroMask != V2Idx ) ; } } if ( V1InUse ) V1 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 ) , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1Mask ) ) ; if ( V2InUse ) V2 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V2 ) , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V2Mask ) ) ; SDValue V ; if ( V1InUse && V2InUse ) V = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , V2 ) ; else V = V1InUse ? V1 : V2 ; return DAG . getNode ( <STR_LIT> , DL , VT


<s> void <ISA_LIT>TargetStreamer :: outputDwarfFileDirectives ( ) { for ( const std :: string & S : DwarfFiles ) getStreamer ( ) . emitRawText


<s> using namespace <ISA_LIT> ; for ( auto & RC : { HvxVRRegClass , HvxWRRegClass , HvxQRRegClass } ) if ( RC . contains ( Reg ) ) return TRI . getRegSizeInBits ( RC ) ; if ( const TargetRegisterClass * RC = TRI . getMinimalPhysRegClass ( Reg )

) return TRI . getRegSizeInBits ( * RC ) ;


<s> void writeDILabel ( const DILabel * N , SmallVectorImpl < uint64_t > & Record , unsigned Abbrev ) { llvm_unreachable ( <STR_LIT>


<s> SDValue LHS = Op . getOperand ( <NUM_LIT> ) ; SDValue RHS = Op . getOperand ( <NUM_LIT> ) ; SDValue TrueV = Op . getOperand ( <NUM_LIT> ) ; SDValue FalseV = Op . getOperand ( <NUM_LIT> ) ; <STR_LIT> CC = cast < CondCodeSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> get ( ) ; DebugLoc dl = Op . getDebugLoc ( ) ; SDValue TargetCC ; SDValue Flag = EmitCMP ( LHS , RHS , TargetCC , CC , dl , DAG ) ; SDVTList VTs = DAG . getVTList ( Op . getValueType ( ) , <STR_LIT> ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . push_back ( TrueV ) ; Ops . push_back ( FalseV ) ; Ops . push_back ( TargetCC ) ; Ops . push_back ( Flag ) ; return DAG . getNode ( <STR_LIT> , dl , VTs , & Ops


<s> O << <STR_LIT> ; return ; } if ( OpNo >= MI -> size ( ) ) { O << <STR_LIT> ; return ; } const MCOperand & Op = MI -> getOperand ( OpNo ) ; if ( Op . isReg ( ) ) { bool isPtrReg = ( MOI . RegClass == <STR_LIT> ) || ( MOI . RegClass == <STR_LIT> ) || ( MOI . RegClass == <STR_LIT> ) ; if ( isPtrReg ) { O << getRegisterName ( Op . getReg ( ) , <STR_LIT> ) ; } else { O << getPrettyRegisterName ( Op . getReg ( ) , MRI ) ; } } else if ( Op . isImm ( ) ) { O << formatImm ( Op . getImm ( ) ) ; } else


<s> printMemOperand<ISA_LIT>EA ( const MCInst * MI , int


<s> if ( ( ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_MEDIUM_PIC ) && size > ( unsigned int ) ix86_section_threshold ) fprintf


<s> EVT VT = Op . getValueType ( ) ; DebugLoc dl = Op . getDebugLoc ( ) ; if ( ! Op . getOperand ( <NUM_LIT> ) . getValueType ( ) . is128BitVector ( ) ) return SDValue ( ) ; if ( VT . getSizeInBits ( ) == <NUM_LIT> ) { SDValue Extract = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; SDValue Assert = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Extract , DAG . getValueType ( VT ) ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Assert ) ; } if ( VT . getSizeInBits ( ) == <NUM_LIT> ) { unsigned Idx = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; if ( Idx == <NUM_LIT> ) return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) ) , Op . getOperand ( <NUM_LIT> ) ) ) ; SDValue Extract = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; SDValue Assert = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Extract , DAG . getValueType ( VT ) ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Assert ) ; } if ( VT == <STR_LIT> ) { if ( ! Op . hasOneUse ( ) ) return SDValue ( ) ; SDNode * User = * Op . getNode ( ) -> use_begin ( ) ; if ( ( User -> getOpcode ( ) != <STR_LIT> || ( isa < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) && cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> isNullValue ( ) ) ) && ( User -> getOpcode ( ) != <STR_LIT> || User -> getValueType ( <NUM_LIT> ) != <STR_LIT> ) ) return SDValue ( ) ; SDValue Extract = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) ) , Op . getOperand ( <NUM_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Extract ) ; } if ( VT == <STR_LIT> || VT == <STR_LIT> ) { if ( isa < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) )


<s> const Function * F = MF . getFunction ( ) ; unsigned StackProbeSize = ( MFI . getStackProtectorIndex ( ) > <NUM_LIT>


<s> for ( MVT T : { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ) if ( TRC -> hasType ( T ) ) return EVT ( T ) . getEVTString ( ) ; DEBUG ( errs ( ) << <STR_LIT> << RegNo


<s> MCFragment * findAssociatedFragment ( )


<s> if ( ! matchVectorAddressRecursively ( N . getOperand ( <NUM_LIT> ) , AM , Depth + <NUM_LIT> ) && ! matchVectorAddressRecursively ( Handle . getValue ( ) . getOperand ( <NUM_LIT> ) , AM , Depth + <NUM_LIT> ) ) return false ; AM = Backup ; if ( ! matchVectorAddressRecursively ( Handle . getValue ( ) . getOperand ( <NUM_LIT> ) , AM , Depth + <NUM_LIT> ) && ! matchVectorAddressRecursively ( Handle . getValue ( ) . getOperand ( <NUM_LIT> ) , AM , Depth + <NUM_LIT> ) ) return false ; AM = Backup ; N = Handle .


<s> case 'r' : return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; case 'l' : case 'N' : return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; case 'f' : return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; case 'd' : return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; } } return TargetLowering :: getRegForInlineAsmConstraint ( Constraint


<s> assert ( Inst . getNumExplicitOperands ( ) == <NUM_LIT> ) ; MachineOperand Op1 = Inst . getOperand ( <NUM_LIT> ) ; Inst . removeOperand ( <NUM_LIT> ) ; Inst . addOperand ( Op1 )


<s> RegisterSubReg DefR ( MI . getOperand ( <NUM_LIT> ) ) ; RegisterSubReg R1 ( MI . getOperand ( <NUM_LIT> ) ) ; assert ( Inputs . has ( R1 . Reg ) ) ; LatticeCell RC = Outputs . get ( DefR . Reg ) ; bool Eval ; unsigned Opc = MI . getOpcode ( ) ; switch ( Opc ) { case <STR_LIT> : Eval = evaluateSplatr ( R1 , <NUM_LIT> , <NUM_LIT> , Inputs , RC ) ; break ; case <STR_LIT> : Eval = evaluateSplatr ( R1 , <NUM_LIT> , <NUM_LIT> , Inputs , RC ) ; break ; default : return false ; } if ( ! Eval ) return false ; Outputs . update ( DefR . Reg , RC ) ; return true


<s> if ( Size >= <NUM_LIT> && ( Subtarget -> isUnalignedMemAccessFast ( ) || ( ( DstAlign == <NUM_LIT> || DstAlign >= <NUM_LIT> ) && ( SrcAlign == <NUM_LIT> || SrcAlign >= <NUM_LIT> ) ) ) && Subtarget -> getStackAlignment ( ) >= <NUM_LIT> ) { if ( Subtarget -> getStackAlignment ( ) >= <NUM_LIT> ) { if ( Subtarget -> hasAVX2 ( ) ) return <STR_LIT> ; if ( Subtarget -> hasAVX ( ) ) return <STR_LIT> ; } if ( Subtarget -> hasSSE2 ( ) )


<s> static bool isCFAlu ( const MachineInstr & MI ) { switch ( MI . getOpcode ( ) ) { case <STR_LIT>


<s> InstructionCost <ISA_LIT>TTIImpl :: getIntrinsicInstrCost ( const IntrinsicCostAttributes & ICA , TTI :: TargetCostKind CostKind ) { if ( ICA . getID ( ) == <STR_LIT> ) { std :: pair < InstructionCost , MVT > LT = TLI . getTypeLegalizationCost ( DL , ICA


<s> bool <ISA_LIT>WinCOFFTargetStreamer :: emitFPOData ( const MCSymbol * ProcSym , SMLoc L ) { MCStreamer & OS = getStreamer ( ) ; MCContext & Ctx = OS . getContext ( ) ; auto I = AllFPOData . find ( ProcSym ) ; if ( I == AllFPOData . end ( ) ) { Ctx . reportError ( L , Twine ( <STR_LIT> ) + ProcSym -> getName ( ) ) ; return true ; } const FPOData * FPO = I -> second . get ( ) ; assert ( FPO -> Begin && FPO -> End && FPO -> PrologueEnd && <STR_LIT> ) ; MCSymbol * FrameBegin = Ctx . createTempSymbol ( ) , * FrameEnd = Ctx . createTempSymbol ( ) ; OS . EmitIntValue ( unsigned ( DebugSubsectionKind :: FrameData ) , <NUM_LIT> ) ; OS . emitAbsoluteSymbolDiff ( FrameEnd , FrameBegin , <NUM_LIT> ) ; OS . EmitLabel ( FrameBegin ) ; OS . EmitValue ( MCSymbolRefExpr :: create ( FPO -> Function , MCSymbolRefExpr :: VK_COFF_IMGREL32 , Ctx ) , <NUM_LIT> ) ; FPOStateMachine FSM ( FPO ) ; FSM . emitFrameDataRecord ( OS , FPO -> Begin ) ; for ( const FPOInstruction & Inst : FPO -> Instructions ) { switch ( Inst . Op ) { case FPOInstruction :: PushReg : FSM . CurOffset += <NUM_LIT> ; FSM . SavedRegSize += <NUM_LIT> ; FSM . RegSaveOffsets . push_back ( { Inst . RegOrOffset , FSM . CurOffset } ) ; break ; case FPOInstruction :: SetFrame : FSM . FrameReg = Inst . RegOrOffset ; FSM . FrameRegOff = FSM . CurOffset ; break ; case FPOInstruction :: StackAlign : FSM . StackOffsetBeforeAlign = FSM .


<s> virtual const MCSection * getExplicitSectionGlobal ( const GlobalValue * GV , SectionKind Kind , Mangler * Mang , const TargetMachine & TM


<s> if ( VT . getVectorElementType ( ) == <STR_LIT> ) return LowerCONCAT_VECTORSvXi1 ( Op , Subtarget , DAG ) ; assert ( ( VT . is256BitVector ( ) && Op . getNumOperands ( ) == <NUM_LIT> ) || ( VT . is512BitVector ( ) && ( Op . getNumOperands ( ) == <NUM_LIT> || Op . getNumOperands ( ) == <NUM_LIT> ) ) ) ; return LowerAVXCONCAT_VECTORS ( Op , DAG , Subtarget


<s> FunctionPass * llvm :: create<ISA_LIT>Scheduler ( TargetMachine


<s> DEBUG ( dbgs ( ) << <STR_LIT> ) ; SDLoc DL ( N ) ; EVT Ty = getPointerTy ( DAG


<s> int MImm = ( int ) MI -> getOperand ( OpNum ) . getImm ( ) & <NUM_LIT> ; if ( MImm > <NUM_LIT> ) O << <STR_LIT> << MImm - <NUM_LIT> << <STR_LIT> ; else O << <STR_LIT> << MImm


<s> void <ISA_LIT>PassConfig :: addPreEmitPass ( ) { <ISA_LIT>TargetMachine & TM = get<ISA_LIT>TargetMachine ( ) ; addPass ( create<ISA_LIT>DelaySlotFillerPass ( TM )


<s> enum calling_abi abi = ix86_abi ; if ( fntype == NULL_TREE || TYPE_ATTRIBUTES ( fntype ) == NULL_TREE ) return abi ; if ( abi == SYSV_ABI && lookup_attribute ( <STR_LIT> , TYPE_ATTRIBUTES ( fntype ) ) ) { static int warned ; if ( TARGET_X32 && ! warned ) { error ( <STR_LIT> ) ; warned =


<s> MCAsmBackend * llvm :: create<ISA_LIT>beAsmBackend ( const Target & T , const MCRegisterInfo & MRI , StringRef TT , StringRef CPU ) { Triple TheTriple ( TT ) ; assert ( TheTriple . isOSBinFormatELF (


<s> getRegForInlineAsmConstraint ( const std :: string & Constraint , EVT VT ) const { if ( Constraint . size ( ) == <NUM_LIT> ) { switch ( Constraint [ <NUM_LIT> ] ) { default : break ; case 'r' : if ( VT == <STR_LIT> ) return std :: make_pair ( <NUM_LIT> , <STR_LIT> ) ; return std :: make_pair ( <NUM_LIT> , <STR_LIT> ) ; } } return TargetLowering :: getRegForInlineAsmConstraint ( Constraint , VT


<s> assert ( CPI < ConstPoolId2AddrMap . size ( ) ) ; return ConstPoolId2AddrMap [ CPI


<s> MachineRegisterInfo & getRegInfo ( Block & MBB ) { return MBB . getParent ( ) -> getRegInfo


<s> if ( ! isImm ( ) ) return false ; <ISA_LIT>MCExpr :: VariantKind VK = <ISA_LIT>MCExpr ::


<s> if ( ! VT1 . isInteger ( ) || ! VT2 . isInteger (


<s> MachineInstr * PrevMI = <NUM_LIT> ; if ( I != BB . begin ( ) ) PrevMI = prior ( I ) ; ++ NumFP ; DEBUG ( errs ( ) << <STR_LIT> << * MI ) ; SmallVector < unsigned , <NUM_LIT> > DeadRegs ; for ( unsigned i = <NUM_LIT> , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) { const MachineOperand & MO = MI -> getOperand ( i ) ; if ( MO . isReg ( ) && MO . isDead ( ) ) DeadRegs . push_back ( MO . getReg ( ) ) ; } switch ( FPInstClass ) { case <STR_LIT> : handleZeroArgFP ( I ) ; break ; case <STR_LIT> : handleOneArgFP ( I ) ; break ; case <STR_LIT> : handleOneArgFPRW ( I ) ; break ; case <STR_LIT> : handleTwoArgFP ( I ) ; break ; case <STR_LIT> : handleCompareFP ( I ) ; break ; case <STR_LIT> : handleCondMovFP ( I ) ; break ; case <STR_LIT> : handleSpecialFP ( I ) ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } for ( unsigned i = <NUM_LIT> , e = DeadRegs . size ( ) ; i != e ; ++ i ) { unsigned Reg = DeadRegs [ i ] ; if ( Reg >= <STR_LIT> && Reg <= <STR_LIT> ) { DEBUG ( errs ( ) << <STR_LIT> << Reg - <STR_LIT> << <STR_LIT> ) ; freeStackSlotAfter ( I , Reg - <STR_LIT> ) ; } } DEBUG ( MachineBasicBlock :: iterator


<s> static MCRegister convertFPR64ToFPR32 ( MCRegister Reg ) { assert ( Reg >= <STR_LIT> && Reg <= <STR_LIT> && <STR_LIT>


<s> const char * <ISA_LIT>ClauseMergePass :: getPassName (


<s> static const MCPhysReg ArgRegs [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , } ; const unsigned NumArgRegs = array_lengthof ( ArgRegs ) ; unsigned RegNum = State . getFirstUnallocated ( ArgRegs ) ; if ( RegNum != NumArgRegs && RegNum % <NUM_LIT> == <NUM_LIT> ) { State . AllocateReg ( ArgRegs


<s> if ( isForcedVOP3 ( ) ) return <STR_LIT> ; if ( isForcedSDWA ( ) ) return


<s> void addBoolRegOperands ( MCInst & Inst , unsigned


<s> return DAG . getVectorShuffle ( VT , dl , V1 , V2 , & Mask1 [ <NUM_LIT> ] ) ; } Mask1 [ <NUM_LIT> ] = HiIndex & <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ; Mask1 [ <NUM_LIT> ] = HiIndex & <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ; Mask1 [ <NUM_LIT> ] = PermMask [ <NUM_LIT> ] ; Mask1 [ <NUM_LIT> ] = PermMask [ <NUM_LIT> ] ; if ( Mask1 [ <NUM_LIT> ] >= <NUM_LIT> ) Mask1 [ <NUM_LIT> ] += <NUM_LIT> ; if ( Mask1 [ <NUM_LIT> ] >= <NUM_LIT> ) Mask1 [ <NUM_LIT> ] += <NUM_LIT> ; return DAG . getVectorShuffle ( VT , dl , V2 , V1 , & Mask1 [ <NUM_LIT> ] ) ; } int LoMask [ ] = { - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> } ; int HiMask [ ] = { - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> } ; int * MaskPtr = LoMask ; unsigned MaskIdx = <NUM_LIT> ; unsigned LoIdx = <NUM_LIT> ; unsigned HiIdx = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> ; i != <NUM_LIT> ; ++ i ) { if ( i == <NUM_LIT> ) { MaskPtr = HiMask ; MaskIdx = <NUM_LIT> ; LoIdx = <NUM_LIT> ; HiIdx = <NUM_LIT> ; } int Idx = PermMask [ i ] ; if ( Idx < <NUM_LIT> ) { Locs [ i ] = std :: make_pair ( - <NUM_LIT> , - <NUM_LIT> ) ; } else if ( Idx < <NUM_LIT> ) { Locs [ i ] = std :: make_pair ( MaskIdx , LoIdx ) ; MaskPtr [ LoIdx ] = Idx ; LoIdx ++ ; } else { Locs [ i ] = std :: make_pair ( MaskIdx , HiIdx ) ; MaskPtr [ HiIdx ] = Idx ; HiIdx ++ ; } } SDValue LoShuffle = DAG . getVectorShuffle ( VT , dl , V1 , V2 , & LoMask [ <NUM_LIT> ] ) ; SDValue HiShuffle = DAG . getVectorShuffle ( VT , dl , V1 , V2 , & HiMask [ <NUM_LIT> ] ) ; int MaskOps [ ] = { - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> } ; for ( unsigned i = <NUM_LIT> ; i != <NUM_LIT> ; ++ i ) if ( Locs [ i ] . first != - <NUM_LIT> ) MaskOps [ i ] = Locs [ i ]

. first * <NUM_LIT> + Locs [ i ] . second ;


<s> void <ISA_LIT>PromoteConstant :: computeInsertionPoint ( Instruction * User , unsigned OpNo , InsertionPoints & InsertPts ) { DEBUG ( dbgs ( ) << <STR_LIT> << OpNo << <STR_LIT> ) ; DEBUG ( User -> print ( dbgs ( ) ) ) ; DEBUG ( dbgs ( ) << '\n' ) ; Instruction * InsertionPoint = findInsertionPoint ( * User ,


<s> <ISA_LIT>TargetStreamer & TTS = static_cast < <ISA_LIT>TargetStreamer & > ( TS ) ; TTS . EmitInstructionLabel ( instructionCount


<s> bool Modified = false ; for ( MachineFunction :: iterator MFI = MF . begin ( ) , E = MF . end ( ) ; MFI != E ; ++ MFI ) Modified |= ExpandMBB ( * MFI ) ; return Modified


<s> return INTVAL ( XEXP ( XEXP ( x , <NUM_LIT> )


<s> return ; } const char * RegName = TM . getRegisterInfo ( ) -> get ( RegNo ) . AsmName ; if ( ! Subtarget . isDarwin ( )

) RegName = stripRegisterPrefix ( RegName ) ;


<s> default : break ; case TargetOpcode :: DBG_VALUE : return ; case <STR_LIT> : lowerGETGOTAndEmitMCInsts ( MI , getSubtargetInfo ( ) ) ; return ; case <STR_LIT> : lowerGETFunPLTAndEmitMCInsts ( MI , getSubtargetInfo ( ) ) ; return ; } MachineBasicBlock :: const_instr_iterator I = MI -> getIterator ( ) ; MachineBasicBlock :: const_instr_iterator E = MI -> getParent ( ) -> instr_end ( ) ; do { MCInst TmpInst ; Lower<ISA_LIT>MachineInstrToMCInst ( & * I , TmpInst , * this ) ; EmitToStreamer ( * OutStreamer


<s> int64_t Imm ; bool IsValid ; if ( ! isImm ( ) ) return false ; bool IsConstantImm = evaluateConstantImm ( getImm ( ) , Imm , VK ) ; if ( ! IsConstantImm ) IsValid = <ISA_LIT>AsmParser :: classifySymbolRef ( getImm


<s> unsigned Opcode = ( N -> getOpcode ( ) == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; return DAG . getNode ( Opcode , DL , N -> getVTList ( ) , N -> getOperand ( <NUM_LIT> ) , RHS , N


<s> static amd_element_byte_size_t getElementByteSizeValue ( unsigned Size ) { switch ( Size ) { case <NUM_LIT>


<s> if ( Op . getOpcode ( ) == <STR_LIT> && Op . getValueType ( ) == <STR_LIT> ) return LowerTruncateToBT ( Op , CC ,


<s> DEBUG ( dbgs ( ) << <STR_LIT> << UNodeList . size ( ) << <STR_LIT> ) ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; for ( auto I = UNodeList . rbegin ( ) , E = UNodeList . rend ( ) ; I != E ; ++ I ) { NodeAddr < UseNode * > UseN = * I ; assert ( ! ( UseN . Addr -> getFlags ( ) & NodeAttrs :: PhiRef ) && <STR_LIT> ) ; NodeAddr < StmtNode * > OwnerN = UseN . Addr -> getOwner ( * DFG ) ; MachineInstr * UseMI = OwnerN . Addr -> getCode ( ) ; DEBUG ( dbgs ( ) << <STR_LIT> << UseMI -> getParent ( ) -> getNumber ( ) << <STR_LIT> << * UseMI << <STR_LIT> ) ; int UseMOnum = - <NUM_LIT> ; unsigned NumOperands = UseMI -> getNumOperands ( ) ; for ( unsigned j = <NUM_LIT> ; j < NumOperands - <NUM_LIT> ; ++ j ) { const MachineOperand & op = UseMI -> getOperand


<s> gcc_assert ( TARGET_LINK_STACK ) ; if ( USE_HIDDEN_LINKONCE ) sprintf (


<s> const <ISA_LIT>ImagePseudoSourceValue * getImagePSV


<s> addPass ( create<ISA_LIT>FixFunctionBitcasts ( ) ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) addPass ( create<ISA_LIT>OptimizeReturned ( ) ) ; if ( ! EnableEmException && TM -> Options . ExceptionModel == ExceptionHandling :: None ) { addPass ( createLowerInvokePass ( ) ) ; addPass ( createUnreachableBlockEliminationPass (


<s> if ( ( flag_pic || TARGET_FDPIC ) && size == UNITS_PER_WORD ) { if ( GET_CODE ( value ) == CONST || GET_CODE ( value ) == SYMBOL_REF || GET_CODE ( value ) == LABEL_REF ) { if ( TARGET_FDPIC && GET_CODE ( value ) == SYMBOL_REF && SYMBOL_REF_FUNCTION_P ( value ) ) { fputs ( <STR_LIT> , asm_out_file ) ; output_addr_const ( asm_out_file , value ) ; fputs ( <STR_LIT> , asm_out_file ) ; return true ; } else if ( TARGET_FDPIC && GET_CODE ( value ) == CONST && frv_function_symbol_referenced_p ( value ) ) return false ; if ( aligned_p && ! TARGET_FDPIC ) { static int label_num = <NUM_LIT> ; char buf [ <NUM_LIT> ] ; const char * p ; ASM_GENERATE_INTERNAL_LABEL ( buf , <STR_LIT> , label_num ++ ) ; p = ( * targetm . strip_name_encoding ) ( buf ) ; fprintf ( asm_out_file , <STR_LIT> , p ) ; fprintf ( asm_out_file , <STR_LIT> , FIXUP_SECTION_ASM_OP ) ; fprintf ( asm_out_file , <STR_LIT> , p ) ; fprintf ( asm_out_file , <STR_LIT> ) ; } assemble_integer_with_op ( <STR_LIT> , value ) ; return true ; } if ( ! aligned_p ) { assemble_integer_with_op ( <STR_LIT> ,


<s> if ( * cum >= ECO32_MAX_PARM_REGS ) words = <NUM_LIT> ; else if ( ( * cum + size ) > ECO32_MAX_PARM_REGS ) words = ( * cum + size ) - ECO32_MAX_PARM_REGS ; else words =


<s> NumBytes = ( ( NumBytes + <NUM_LIT> ) / <NUM_LIT> ) * <NUM_LIT> ; NumBytes += <NUM_LIT> * nAltivecParamsAtEnd ; } NumBytes = std :: max ( NumBytes , <ISA_LIT>FrameLowering :: getMinCallFrameSize ( is<ISA_LIT>64 , true ) ) ; if ( CC == CallingConv :: Fast && DAG . getTarget ( ) . Options . GuaranteedTailCallOpt ) { unsigned TargetAlign = DAG . getMachineFunction ( ) . getTarget ( ) . getFrameLowering ( ) -> getStackAlignment ( ) ; unsigned AlignMask = TargetAlign - <NUM_LIT> ; NumBytes = ( NumBytes + AlignMask ) & ~


<s> MachineFunction * MF = MBB . getParent ( ) ; const TargetInstrInfo & TII = * MF -> getSubtarget ( ) . getInstrInfo ( ) ; bool AtStart = MI == MBB . begin ( ) ; MachineBasicBlock :: iterator BeforeI = MI ; if ( ! AtStart ) -- BeforeI ; for ( const CalleeSavedInfo & CSR


<s> int size = int_size_in_bytes ( type ) ; return size > <NUM_LIT> * UNITS_PER_WORD || size


<s> static bool shouldRematerialize ( const MachineInstr & Def , AliasAnalysis

& AA , const <ISA_LIT>InstrInfo * TII ) {


<s> SIBBase sibBaseBase = <NUM_LIT> ; uint8_t index , base ; dbgprintf ( insn , <STR_LIT> ) ; if ( insn -> consumedSIB ) return <NUM_LIT> ; insn -> consumedSIB = TRUE ; switch ( insn -> addressSize ) { case <NUM_LIT> : dbgprintf ( insn , <STR_LIT> ) ; return - <NUM_LIT> ; break ; case <NUM_LIT> : sibIndexBase = SIB_INDEX_EAX ; sibBaseBase = SIB_BASE_EAX ; break ; case <NUM_LIT> : sibIndexBase = SIB_INDEX_RAX ; sibBaseBase = SIB_BASE_RAX ; break ; } if ( consumeByte ( insn , & insn -> sib ) ) return - <NUM_LIT> ; index = indexFromSIB ( insn -> sib ) | ( xFromREX ( insn -> rexPrefix ) << <NUM_LIT> ) ; switch ( index ) { case <NUM_LIT> : insn -> sibIndex = SIB_INDEX_NONE ; break ; default : insn -> sibIndex = ( SIBIndex ) ( sibIndexBase + index ) ; if ( insn -> sibIndex == SIB_INDEX_sib || insn -> sibIndex == SIB_INDEX_sib64 ) insn -> sibIndex = SIB_INDEX_NONE ; break ; } switch ( scaleFromSIB ( insn -> sib ) ) { case


<s> assert ( Op . getValueType ( ) == <STR_LIT> && <STR_LIT> ) ; SDLoc DL ( Op ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op


<s> setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; <STR_LIT> FPCCToExtend [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; <STR_LIT> FPOpToExtend [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; if ( Subtarget . hasStdExtF ( ) ) { setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; for ( auto CC : FPCCToExtend ) setCondCodeAction ( CC , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; for ( auto Op : FPOpToExtend ) setOperationAction ( Op , <STR_LIT> , Expand ) ; } if ( Subtarget . hasStdExtD ( ) ) { setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; for ( auto CC : FPCCToExtend ) setCondCodeAction ( CC , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setLoadExtAction ( <STR_LIT> , <STR_LIT> , <STR_LIT> , Expand ) ; setTruncStoreAction ( <STR_LIT> , <STR_LIT> , Expand ) ; for ( auto Op : FPOpToExtend ) setOperationAction ( Op , <STR_LIT> , Expand ) ; } setOperationAction ( <STR_LIT> , XLenVT , Custom ) ; setOperationAction ( <STR_LIT> , XLenVT , Custom ) ; setOperationAction ( <STR_LIT> , XLenVT , Custom ) ; if ( Subtarget . hasStdExtA ( )


<s> __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) __andn_u32 ( unsigned int __X , unsigned int __Y ) { return ( ~ __X &


<s> return TTI :: TCC_Free ; case Instruction :: Store : ImmIdx = <NUM_LIT> ; break ; case Instruction :: Add : case Instruction :: Sub : case Instruction :: Mul : case Instruction :: UDiv : case Instruction :: SDiv : case Instruction :: URem : case Instruction :: SRem : case Instruction :: And : case Instruction :: Or : case Instruction :: Xor : case Instruction :: ICmp : ImmIdx = <NUM_LIT> ; break ; case Instruction :: Shl : case Instruction :: LShr : case Instruction :: AShr : if ( Idx == <NUM_LIT> ) return TTI :: TCC_Free ; break ; case Instruction :: Trunc : case Instruction :: ZExt : case Instruction :: SExt


<s> return ( __m128i ) __builtin_ia32_movdqa64load128_mask ( ( __v2di * ) __P ,


<s> initialize<ISA_LIT>LoopDataPrefetchPass ( * PassRegistry :: getPassRegistry


<s> return selectBDAddr ( <STR_LIT> , Addr


<s> if ( ( Slct . getOpcode ( ) != <STR_LIT> && Slct . getOpcode ( ) != <STR_LIT> ) || ! Slct . hasOneUse ( ) ) return SDValue ( ) ; auto isZeroOrAllOnes = [ ] ( SDValue N , bool AllOnes ) { return AllOnes ? isAllOnesConstant ( N ) : isNullConstant ( N ) ; } ; bool SwapSelectOps ; unsigned OpOffset = Slct . getOpcode ( ) == <STR_LIT> ? <NUM_LIT> : <NUM_LIT> ; SDValue TrueVal = Slct . getOperand ( <NUM_LIT> + OpOffset ) ; SDValue FalseVal = Slct . getOperand ( <NUM_LIT> + OpOffset ) ; SDValue NonConstantVal ; if ( isZeroOrAllOnes ( TrueVal , AllOnes ) ) { SwapSelectOps = false ; NonConstantVal = FalseVal ; } else if ( isZeroOrAllOnes ( FalseVal , AllOnes ) ) { SwapSelectOps = true ; NonConstantVal = TrueVal ; } else return SDValue


<s> bool <ISA_LIT>DAGToDAGISel :: TryFoldLoad ( SDNode * P , SDValue N , SDValue & Base , SDValue & Disp , SDValue & Index ) { if ( <STR_LIT> ( N . getNode ( ) ) && IsLegalToFold ( N , P , P , OptLevel ) ) return SelectAddrRRI20 ( P , N . getOperand ( <NUM_LIT> ) , Base , Disp , Index ) ; return false


<s> void function_builder :: apply_predication ( const function_instance & instance , tree return_type , vec < tree > & argument_types ) const { if ( instance . base -> has_merge_operand_p ( ) ) if ( instance . pred == PRED_TYPE_tu || instance . pred == PRED_TYPE_tum || instance . pred == PRED_TYPE_tumu || instance . pred == PRED_TYPE_mu ) argument_types . quick_insert ( <NUM_LIT> , return_type ) ; vector_type_index mask_type_index = function_types [ instance . type . index ] . type_indexes [ RVV_BASE_mask ] ; tree mask_type = builtin_types [ mask_type_index ] . vector ; if ( instance . pred == PRED_TYPE_m || instance . pred == PRED_TYPE_tum || instance . pred == PRED_TYPE_tumu || instance . pred == PRED_TYPE_mu ) argument_types . quick_insert ( <NUM_LIT> , mask_type ) ; if ( instance . base -> apply_vl_p ( ) ) argument_types . quick_push (


<s> MachineInstr * FixupBWInstPass :: tryReplaceCopy ( MachineInstr * MI ) const { assert ( MI -> getNumExplicitOperands ( ) == <NUM_LIT> ) ; auto & OldDest = MI -> getOperand ( <NUM_LIT> ) ; auto & OldSrc = MI -> getOperand ( <NUM_LIT> ) ; unsigned NewDestReg ; if ( ! getSuperRegDestIfDead ( MI , NewDestReg ) ) return nullptr ; unsigned NewSrcReg = get<ISA_LIT>SubSuperRegister ( OldSrc . getReg ( ) , <NUM_LIT> ) ; auto * TRI = & TII -> getRegisterInfo ( ) ; if ( TRI -> getSubRegIndex ( NewSrcReg , OldSrc . getReg ( ) ) != TRI -> getSubRegIndex ( NewDestReg , OldDest . getReg ( ) ) ) return nullptr ; MachineInstrBuilder MIB = BuildMI ( * MF , MI -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , NewDestReg ) . addReg ( NewSrcReg , RegState :: Undef ) . addReg ( OldSrc . getReg ( ) , RegState :: Implicit ) ; for ( auto & Op : MI -> implicit_operands ( ) ) if ( Op . getReg ( ) != ( Op . isDef ( ) ? NewDestReg : NewSrcReg ) ) MIB . add ( Op ) ; return MIB


<s> static void * rs6000_alloc_sched_context (


<s> SDLoc dl ( Op ) ; SDValue Cv = DAG . getNode ( Op . getOpcode ( ) , dl , InVT . changeVectorElementTypeToInteger ( ) , Op . getOperand ( <NUM_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Cv ) ; } if ( VTSize > InVTSize ) { SDLoc dl ( Op ) ; MVT ExtVT = <STR_LIT> ( <STR_LIT> ( VT . getScalarSizeInBits ( ) ) , VT . getVectorNumElements ( ) ) ; SDValue Ext = DAG . getNode ( <STR_LIT> , dl , ExtVT , Op . getOperand ( <NUM_LIT> ) ) ; return DAG . getNode ( Op . getOpcode ( ) , dl , VT ,


<s> Op -> FPImm . Val = Val ; Op -> StartLoc = S ; Op -> EndLoc = S ; return Op


<s> const GlobalVariable * GVA = dyn_cast < GlobalVariable > ( GO ) ; if ( ! GVA ) return false ; if ( GVA -> hasSection ( ) ) { StringRef Section = GVA -> getSection ( ) ; if ( Section == <STR_LIT> || Section == <STR_LIT> ) return true ; return false


<s> static DecodeStatus DecodeDoubleRegStore ( MCInst & Inst , unsigned Insn , uint64_t Address , const void * Decoder ) { DecodeStatus S = MCDisassembler :: Success ; unsigned Rd = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned Rt = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned Rn = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned pred = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; if ( ! Check ( S , DecoderGPRRegisterClass ( Inst , Rd , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ( Rt & <NUM_LIT> ) || Rt == <NUM_LIT> || Rn == <NUM_LIT> ) return MCDisassembler :: Fail ; if ( Rd == Rn || Rd == Rt || Rd

== Rt + <NUM_LIT> ) return MCDisassembler :: Fail ;


<s> else if ( ConstraintCode == <STR_LIT> ) return InlineAsm :: Constraint_v ; else if ( ConstraintCode == <STR_LIT> ) return


<s> emitThumbRegPlusImmediate ( MBB , MBBI , <STR_LIT> , <STR_LIT> , NumBytes , TII , MRI


<s> unsigned getExplicitKernelArgOffset ( const Function & F


<s> unsigned Reg = MO . getReg ( ) ; if ( ! Reg || Reg == <STR_LIT> || Reg == <STR_LIT> ) continue ; if ( MO . isUse ( ) ) LocalUses . push_back ( Reg ) ; else LocalDefs . push_back ( Reg ) ; } for ( unsigned i = <NUM_LIT> , e = LocalUses . size ( ) ; i != e ; ++ i ) { unsigned Reg = LocalUses [ i ] ; for ( MCSubRegIterator Subreg ( Reg , TRI , true ) ; Subreg . isValid ( ) ; ++ Subreg ) Uses . insert ( * Subreg ) ; } for ( unsigned i = <NUM_LIT> , e = LocalDefs . size ( ) ; i != e ; ++ i ) { unsigned Reg = LocalDefs [ i ] ; for ( MCSubRegIterator Subreg ( Reg , TRI , true ) ; Subreg . isValid ( ) ; ++ Subreg ) Defs . insert ( * Subreg ) ; if ( Reg ==


<s> case <STR_LIT> : llvm_unreachable ( <STR_LIT> ) ; default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : return UseSPE ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : return UseSPE ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : return UseSPE ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : return


<s> return StringSwitch < AluCode > ( S ) . Case ( <STR_LIT> , ADD ) . Case ( <STR_LIT> , ADDC ) . Case ( <STR_LIT> , SUB ) . Case ( <STR_LIT> , SUBB ) . Case ( <STR_LIT> , AND ) . Case ( <STR_LIT> , OR ) . Case ( <STR_LIT> , XOR ) . Case ( <STR_LIT> ,

SHL ) . Case ( <STR_LIT> , SRL ) . Case ( <STR_LIT> , SRA ) . Default ( UNKNOWN ) ;


<s> static bool shiftedInBitsMatter ( RxSBGOperands & RxSBG , uint64_t Count , bool IsLeft ) { uint64_t ShiftedIn = allOnes ( Count ) ; if ( ! IsLeft ) ShiftedIn <<= RxSBG . BitSize - Count ; if ( RxSBG . Rotate != <NUM_LIT> ) ShiftedIn = ( ( ShiftedIn << RxSBG . Rotate ) | ( ShiftedIn


<s> bool <ISA_LIT>PacketizerList :: canReserveResourcesForConstExt ( MachineInstr * MI ) { const <ISA_LIT>InstrInfo * QII = ( const <ISA_LIT>InstrInfo * ) TII ; assert ( QII -> isExtended ( MI ) && <STR_LIT> ) ; MachineFunction * MF = MI -> getParent ( ) -> getParent ( ) ; MachineInstr * PseudoMI = MF -> CreateMachineInstr ( QII -> get ( <STR_LIT> ) , MI -> getDebugLoc ( ) ) ; bool CanReserve = ResourceTracker -> canReserveResources ( PseudoMI ) ; MF -> DeleteMachineInstr ( PseudoMI ) ; return CanReserve


<s> if ( EltType == <STR_LIT> ) return <STR_LIT> ; if ( EltType == <STR_LIT> || EltType == <STR_LIT> ) return <STR_LIT> ; if ( EltType == <STR_LIT> || EltType == <STR_LIT> ) return <STR_LIT> ; if ( EltType == <STR_LIT> || EltType == <STR_LIT> ) return <STR_LIT> ; llvm_unreachable ( <STR_LIT> )


<s> DenseMap < MachineDomTreeNode * , unsigned > OpenChildren ; WorkList . push_back ( Node ) ; do { Node = WorkList . pop_back_val ( ) ; Scopes . push_back ( Node ) ; const std :: vector < MachineDomTreeNode * > & Children = Node -> getChildren ( ) ; OpenChildren [ Node ] = Children . size ( ) ; for ( MachineDomTreeNode * Child : Children ) WorkList . push_back ( Child ) ; } while ( ! WorkList . empty ( ) ) ; for ( MachineDomTreeNode * Node : Scopes ) { MachineBasicBlock * MBB = Node -> getBlock ( ) ; EnterScope (


<s> if ( ! isCondset ( MI ) ) continue ; MachineOperand & S1 = MI -> getOperand ( <NUM_LIT> ) , & S2 = MI -> getOperand ( <NUM_LIT> ) ; if ( ! S1 . isReg ( ) && ! S2 . isReg ( ) ) continue ; Condsets . push_back ( MI ) ; } } bool Changed = false ; for ( unsigned i = <NUM_LIT> , n = Condsets . size ( ) ; i < n ; ++ i ) { MachineInstr * CI = Condsets [ i ] ; RegisterRef RD = CI -> getOperand ( <NUM_LIT> ) ; RegisterRef RP = CI -> getOperand ( <NUM_LIT> ) ; MachineOperand & S1 = CI -> getOperand ( <NUM_LIT> ) , & S2 = CI -> getOperand ( <NUM_LIT> ) ; bool Done = false ; if ( S1 . isReg ( ) ) { RegisterRef RS = S1 ; MachineInstr * RDef = getReachingDefForPred ( RS , CI , RP . Reg , true ) ; if ( ! RDef || ! HII -> isPredicable ( RDef ) ) Done = coalesceRegisters ( RD , RegisterRef ( S1


<s> unsigned Opc = <NUM_LIT> ; const TargetRegisterClass * RC = NULL ; switch ( VT . getSimpleVT ( ) . SimpleTy ) { default : return false ; case <STR_LIT> : case <STR_LIT> : Opc = <STR_LIT> ; RC = & <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; RC = & <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; RC = & <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; RC = & <STR_LIT> ; break ; case <STR_LIT> : if ( <ISA_LIT>ScalarSSEf32 ) { Opc = Subtarget -> hasAVX ( ) ? <STR_LIT>


<s> unsigned srcregnum = Instr -> getOperand ( <NUM_LIT> ) . getReg ( ) ; SmallVector < unsigned , <NUM_LIT> > src = getScalarRegisters ( srcregnum ) ; MachineOperand which = Instr -> getOperand ( <NUM_LIT> ) ; assert ( which . isImm ( ) && <STR_LIT> ) ; DebugLoc DL = Instr -> getDebugLoc ( ) ; MachineInstr * copy = BuildMI ( F , DL , InstrInfo -> get ( getScalarVersion ( Instr ) ) , Instr -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; copy -> addOperand ( MachineOperand :: CreateReg ( src [ which . getImm ( ) ] , false ) ) ; copies . push_back ( copy


<s> SDValue X = Op . getOperand ( <NUM_LIT> ) ; SDValue T = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , X ) ; SDValue Diff = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , X , T ) ; SDValue AbsDiff = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Diff ) ; const SDValue Zero = DAG . getConstantFP ( <NUM_LIT> , SL , <STR_LIT> ) ; const SDValue One = DAG . getConstantFP ( <NUM_LIT> ,


<s> if ( DEFAULT_ABI == ABI_V4 && ( TARGET_RELOCATABLE || flag_pic > <NUM_LIT> ) ) { fputs ( <STR_LIT> , asm_out_file ) ; output_addr_const ( asm_out_file , symbol ) ; fputs ( <STR_LIT> , asm_out_file


<s> FI -> setMustSaveLR ( MustSaveLR ( MF , LR ) ) ; MF . getRegInfo ( ) . setPhysRegUnused ( LR ) ; int FPSI = FI -> getFramePointerSaveIndex ( ) ; bool Is<ISA_LIT>64 = Subtarget . is<ISA_LIT>64 ( ) ; bool IsELF32_ABI = Subtarget . isELF32_ABI ( ) ; bool IsMachoABI = Subtarget . isMachoABI ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; if ( ! FPSI && ( NoFramePointerElim || MFI -> hasVarSizedObjects ( ) ) && IsELF32_ABI ) { int FPOffset = <ISA_LIT>FrameInfo :: getFramePointerSaveOffset ( Is<ISA_LIT>64 , IsMachoABI ) ; FPSI = MF . getFrameInfo ( ) -> CreateFixedObject ( Is<ISA_LIT>64 ? <NUM_LIT>


<s> Register <ISA_LIT>TargetLowering :: getRegisterByName ( const char * RegName , LLT VT , const MachineFunction & MF ) const { unsigned Reg = StringSwitch < unsigned > ( RegName ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( <NUM_LIT> ) ; if ( Reg ) return Reg ; report_fatal_error ( <STR_LIT>


<s> if ( getTargetMachine ( ) . getRelocationModel ( ) == Reloc :: PIC_ ) { Addr = DAG . getLoad ( ( EVT ) <STR_LIT> , dl , Chain , Addr , PseudoSourceValue :: getJumpTable ( ) , <NUM_LIT> , false , false , <NUM_LIT> ) ; Chain = Addr . getValue ( <NUM_LIT> ) ; Addr = DAG . getNode ( <STR_LIT> , dl , PTy , Addr , Table ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Chain , Addr , JTI , UId ) ; } else { Addr = DAG . getLoad ( PTy , dl , Chain , Addr , PseudoSourceValue :: getJumpTable ( ) , <NUM_LIT> , false , false , <NUM_LIT> ) ; Chain = Addr . getValue ( <NUM_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT>


<s> switch ( MI . getOpcode ( ) ) { default : break ; case <STR_LIT> : Offset *= - <NUM_LIT> ; case <STR_LIT> : if ( ! MI . getOperand ( <NUM_LIT> ) . isImm ( ) ) break ; if ( <STR_LIT> ( MI . getOperand ( <NUM_LIT> ) . getImm ( ) ) ) break ; if ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) != BaseReg || MI . getOperand ( <NUM_LIT> ) . getReg ( ) != BaseReg ) break ; bool IsPairedInsn = isPairedLdSt (


<s> op0 = nds32_legitimize_argument ( icode , <NUM_LIT> , op0 ) ; pat = GEN_FCN ( icode ) ( target , op0 , addr_helper ) ; if ( ! pat


<s> AddrReg = B . buildBitcast ( V2S16 , AddrReg ) . getReg ( <NUM_LIT> ) ; PackedAddrs . push_back ( AddrReg ) ; } else { if ( ( ( I + <NUM_LIT> ) >= ( AddrIdx + NumVAddrs ) ) || ( ( NumGradients / <NUM_LIT> ) % <NUM_LIT> == <NUM_LIT> && ( I == DimIdx + ( NumGradients / <NUM_LIT> ) - <NUM_LIT> || I == DimIdx + NumGradients - <NUM_LIT> ) ) || ! MI . getOperand ( I + <NUM_LIT> ) . isReg ( ) ) { PackedAddrs . push_back ( B . buildBuildVector ( V2S16 , { AddrReg , B . buildUndef ( S16 ) . getReg ( <NUM_LIT> )


<s> RegT = get<ISA_LIT>RegisterNumbering ( RegT ) ; Binary |= ( RegT << <STR_LIT> ) ; Binary |= encodeNEONRn ( MI , <NUM_LIT> ) ; emitWordLE ( Binary


<s> if ( ST . hasAddNoCarry ( ) ) return BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) ; Register UnusedCarry = ! RS . isRegUsed ( <STR_LIT> ) ? Register ( RI . getVCC ( ) )

: RS . scavengeRegister ( RI . getBoolRC ( ) , I , <NUM_LIT> , false ) ;


<s> const MCOperand & OffsetOp = MI -> getOperand ( OpNo + <NUM_LIT> ) ; printOperand ( MI , OpNo , O ) ; if ( OffsetOp . isImm ( ) ) { int64_t Offset = OffsetOp . getImm ( ) ; if ( Offset >= <NUM_LIT> ) O << '+' ; O << Offset ; } else if ( OffsetOp . isExpr ( ) ) { O << * OffsetOp . getExpr ( ) ; } else


<s> static machine_mode msp430_get_raw_arg_mode ( int regno ) { return ( regno == ARG_POINTER_REGNUM ) ? VOIDmode


<s> if ( inverted ) std :: swap ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ; emit_insn ( gen_neon_vbsl ( GET_MODE ( operands [ <NUM_LIT> ] ) , operands [ <NUM_LIT> ] , mask , operands [ <NUM_LIT> ] , operands


<s> if ( ACPV -> Kind == Kind && ACPV -> PCAdjust == PCAdjust && ACPV -> Modifier == Modifier && ACPV -> LabelId == LabelId && ACPV

-> AddCurrentAddress == AddCurrentAddress ) {


<s> SmallPtrSet < MachineInstr * , <NUM_LIT> > Ignore ; for ( auto I = MachineBasicBlock :: iterator ( MI ) , E = MBB -> end ( ) ; I != E ; ++ I ) { if ( I -> getOpcode ( ) == <STR_LIT> ) { Ignore . insert ( & * I ) ; break ; } } bool SetFlags = RDA -> isSafeToDefRegAt ( MI , <STR_LIT> , Ignore ) ; MachineInstrBuilder MIB = BuildMI ( * MBB , MI , MI -> getDebugLoc ( ) ,


<s> addPass ( create<ISA_LIT>AbstractMemberAccess ( & get<ISA_LIT>TargetMachine ( ) ) ) ; addPass ( create<ISA_LIT>PreserveDIType (


<s> unsigned Reg = MO . getReg ( ) ; if ( Reg == <STR_LIT> || Reg == <STR_LIT> || Reg == <STR_LIT> || Reg == <STR_LIT> ) UsesHighByteReg = true ; if ( <STR_LIT> ( Reg ) ) REX |= <NUM_LIT> ; } else if ( MO . isExpr ( ) && STI . getTargetTriple ( ) . isX32 ( ) ) { const auto * Ref = dyn_cast < MCSymbolRefExpr > ( MO . getExpr ( ) ) ; if ( Ref && ( Ref -> getKind ( ) == MCSymbolRefExpr :: VK_GOTTPOFF || Ref -> getKind ( ) == MCSymbolRefExpr :: VK_TLSDESC ) ) { REX |= <NUM_LIT> ; } } } switch ( TSFlags & <STR_LIT> ) { case <STR_LIT> : REX |= isREXExtendedReg ( MI , CurOp ++ ) << <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : REX |= isREXExtendedReg ( MI , CurOp ++ ) << <NUM_LIT> ; REX |= isREXExtendedReg ( MI , CurOp ++ ) << <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : REX |= isREXExtendedReg ( MI , CurOp ++ ) << <NUM_LIT> ; REX |= isREXExtendedReg ( MI , MemOperand + <STR_LIT> ) << <NUM_LIT> ; REX |= isREXExtendedReg ( MI , MemOperand + <STR_LIT> ) << <NUM_LIT> ; CurOp += <STR_LIT> ; break ; case <STR_LIT> : REX |= isREXExtendedReg ( MI , CurOp ++ ) << <NUM_LIT> ; REX |= isREXExtendedReg ( MI , CurOp ++ ) << <NUM_LIT> ; break ; case <STR_LIT> : REX |= isREXExtendedReg ( MI , MemOperand + <STR_LIT> ) << <NUM_LIT> ; REX |= isREXExtendedReg ( MI , MemOperand + <STR_LIT> ) << <NUM_LIT> ; CurOp += <STR_LIT> ; REX |= isREXExtendedReg ( MI , CurOp ++ ) << <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case


<s> return StringSwitch < <STR_LIT> > ( Type ) . Case ( <STR_LIT> , <STR_LIT> :: Externref ) . Case (

<STR_LIT> , <STR_LIT> :: Funcref ) . Default ( <STR_LIT> :: Invalid ) ;


<s> TII = STI -> getInstrInfo ( ) ; initConverters ( ) ; bool Changed = false ; DenseSet < unsigned > EnclosedEdges ; DenseMap < MachineInstr * , Closure * > EnclosedInstrs ; std :: vector < Closure > Closures ; for ( unsigned Idx = <NUM_LIT> ; Idx < MRI -> getNumVirtRegs ( ) ; ++ Idx ) { unsigned Reg = TargetRegisterInfo :: index2VirtReg ( Idx ) ; if ( ! isGPR ( MRI -> getRegClass ( Reg ) ) ) continue ; if ( EnclosedEdges . count ( Reg ) )


<s> break ; case GE : if ( mep_imm4_operand ( op1 , SImode ) ) break ; tmp = gen_reg_rtx ( SImode ) ; gcc_assert ( mep_expand_setcc_1 ( LT , tmp , op0 , op1 ) ) ; code = EQ ; op0 = tmp ; op1 = const0_rtx ; break ; case EQ : case NE : if ( ! mep_reg_or_imm4_operand ( op1 , SImode ) ) op1 = force_reg ( SImode , op1 ) ; break ; case LE : case GT : if ( GET_CODE ( op1 ) == CONST_INT && INTVAL ( op1 ) != <NUM_LIT> ) { op1 = GEN_INT ( INTVAL ( op1 ) + <NUM_LIT> ) ; code = ( code == LE ? LT : GE ) ; goto restart ; } tmp = gen_reg_rtx ( SImode ) ; gcc_assert ( mep_expand_setcc_1 ( LT , tmp , op1 , op0 ) ) ; code = ( code == LE ? EQ : NE ) ; op0 = tmp ; op1 = const0_rtx ; break ; case LTU : if ( op1 == const1_rtx ) { code =


<s> return DAG . getTargetBlockAddress ( N -> getBlockAddress ( ) , Ty


<s> unsigned <STR_LIT> ( unsigned Opcode , Type * Ty , OperandValueKind Op1Info , OperandValueKind Op2Info ) const { int ISDOpcode = TLI -> InstructionOpcodeToISD ( Opcode ) ; std :: pair < unsigned , MVT > LT = TLI -> getTypeLegalizationCost ( Ty ) ; const unsigned FunctionCallDivCost = <NUM_LIT> ; const unsigned ReciprocalDivCost = <NUM_LIT> ; static const CostTblEntry < MVT > CostTbl [ ] = { { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , ReciprocalDivCost } , { <STR_LIT> , <STR_LIT> , ReciprocalDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , ReciprocalDivCost } , { <STR_LIT> , <STR_LIT> , ReciprocalDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , } ; int Idx = - <NUM_LIT> ; if ( ST -> hasNEON ( ) ) Idx = CostTableLookup < MVT > ( CostTbl , array_lengthof ( CostTbl ) , ISDOpcode , LT . second ) ; if ( Idx != - <NUM_LIT> ) return LT . first * CostTbl [ Idx ] . Cost ; return TargetTransformInfo :: getArithmeticInstrCost ( Opcode , Ty


<s> CCMask &= CCValid ; adjustZeroCmp ( DAG , IsUnsigned , CmpOp0 , CmpOp1 , CCMask ) ; adjustSubwordCmp ( DAG , IsUnsigned , CmpOp0 , CmpOp1 , CCMask ) ; Opcode = <STR_LIT> ; if ( CCMask == <STR_LIT> || CCMask == <STR_LIT> || ( DAG . SignBitIsZero ( CmpOp0 ) && DAG . SignBitIsZero ( CmpOp1 ) ) ) ICmpType = <STR_LIT> ; else if ( IsUnsigned ) ICmpType = <STR_LIT> ; else ICmpType = <STR_LIT> ; } if ( shouldSwapCmpOperands ( CmpOp0 , CmpOp1 , ICmpType ) ) { std :: swap ( CmpOp0 , CmpOp1 ) ; CCMask = ( ( CCMask & <STR_LIT> ) | ( CCMask & <STR_LIT> ? <STR_LIT> : <NUM_LIT> ) | ( CCMask & <STR_LIT> ? <STR_LIT> : <NUM_LIT> ) | ( CCMask & <STR_LIT> ) ) ; } adjustForTestUnderMask ( DAG , Opcode , CmpOp0 , CmpOp1 , CCValid , CCMask ,


<s> static DecodeStatus DecodeGPRPairnospRegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t Address , const void * Decoder ) { if ( RegNo > <NUM_LIT> ) return MCDisassembler :: Fail ; unsigned RegisterPair = GPRPairDecoderTable [ RegNo / <NUM_LIT> ] ; Inst . addOperand ( MCOperand :: createReg ( RegisterPair ) ) ; if ( ( RegNo & <NUM_LIT> ) || RegNo > <NUM_LIT> ) return


<s> return findOneNVVMAnnotation ( & F , <STR_LIT> ,


<s> unsigned getTotalNumVGPRs ( ) const { return <STR_LIT> :: getTotalNumVGPRs ( this


<s> isPostRA ( postRA ) , PacketNum ( <NUM_LIT> ) , MF ( SchedDAG -> MF ) , ST ( SchedDAG -> MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ) , Resources ( SchedDAG -> MF . getSubtarget <

<ISA_LIT>Subtarget > ( ) . createDFAPacketizer ( II ) ) , DAG ( SchedDAG ) {


<s> return ( vector signed int ) __builtin_altivec_vcmpequw ( ( vector signed int ) a1 , ( vector


<s> const MachineOperand & MO = MI -> getOperand ( ExtOpNum ) ; if ( MO . getTargetFlags ( ) && <STR_LIT> ) return true ; if ( MO . isMBB ( ) ) return false ; if ( MO . isGlobal ( ) || MO . isSymbol ( ) || MO . isBlockAddress ( ) || MO . isJTI ( ) || MO . isCPI ( ) ) return true ; assert ( MO . isImm ( ) && <STR_LIT> ) ; int MinValue = getMinValue


<s> return isShiftedInt < N , S > ( minConstant ( MCI


<s> case E_V16QImode : if ( ! BYTES_BIG_ENDIAN ) { if ( TARGET_P9_VECTOR ) emit_insn ( gen_vsx_ld_elemrev_v16qi_internal ( reg , mem ) ) ; else { rtx reg_v2di = simplify_gen_subreg ( V2DImode , reg , V16QImode , <NUM_LIT> ) ; gcc_assert ( MEM_P ( mem ) ) ; rtx addr = XEXP ( mem , <NUM_LIT> ) ; rtx mem_v2di = gen_rtx_MEM ( V2DImode , addr ) ; MEM_COPY_ATTRIBUTES ( mem_v2di , mem ) ; set_mem_size ( mem , GET_MODE_SIZE ( V2DImode ) ) ; emit_insn ( gen_vsx_ld_elemrev_v2di ( reg_v2di , mem_v2di ) ) ; } } else emit_insn ( gen_vsx_movv2di_64bit ( reg , mem ) ) ; break ; default : gcc_unreachable ( ) ; } break ; case E_DImode : switch ( mode ) { case E_QImode : emit_insn ( gen_zero_extendqidi2 ( reg , mem ) ) ; break ; case E_HImode : { rtx src = mem ; if ( ! BYTES_BIG_ENDIAN ) { src = gen_reg_rtx ( HImode ) ; emit_insn ( gen_bswaphi2 ( src , mem ) ) ; } emit_insn ( gen_zero_extendhidi2 ( reg , src ) ) ; break ; } case E_SImode : { rtx src = mem ; if ( ! BYTES_BIG_ENDIAN ) { src = gen_reg_rtx ( SImode ) ; emit_insn ( gen_bswapsi2 ( src , mem ) ) ; } emit_insn ( gen_zero_extendsidi2 ( reg , src ) ) ; } break ; case E_DImode : if ( ! BYTES_BIG_ENDIAN ) emit_insn ( gen_bswapdi2 ( reg , mem ) ) ; else emit_insn ( gen_movdi ( reg , mem ) ) ; break ; default : gcc_unreachable ( ) ; } break ; case E_SImode : switch ( mode ) { case E_QImode : emit_insn ( gen_zero_extendqisi2 ( reg , mem ) ) ; break ; case E_HImode : { rtx src = mem ; if ( ! BYTES_BIG_ENDIAN ) { src = gen_reg_rtx ( HImode ) ; emit_insn ( gen_bswaphi2 ( src , mem ) ) ; } emit_insn ( gen_zero_extendhisi2 ( reg , src ) ) ; break ; } case E_SImode : if ( ! BYTES_BIG_ENDIAN ) emit_insn ( gen_bswapsi2 ( reg , mem ) ) ; else emit_insn ( gen_movsi ( reg , mem ) ) ; break ; case E_DImode : gcc_unreachable ( ) ; break ; default : gcc_unreachable (


<s> case <STR_LIT> : std :: swap ( TV , FV ) ; case <STR_LIT> : case <STR_LIT> : if ( LHS . getValueType ( ) == <STR_LIT> ) LHS = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , LHS ) ; return DAG . getNode ( <STR_LIT> , dl , ResVT , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , LHS ) , TV , FV ) ; } SDValue Cmp ; switch ( CC ) { default : break ; case <STR_LIT> : std :: swap ( TV , FV ) ; case <STR_LIT> : Cmp = DAG . getNode ( <STR_LIT> , dl , CmpVT , LHS , RHS ) ; if ( Cmp . getValueType ( ) == <STR_LIT> ) Cmp = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Cmp ) ; Sel1 = DAG . getNode ( <STR_LIT> , dl , ResVT , Cmp , TV , FV ) ; if ( Sel1 . getValueType ( ) == <STR_LIT> ) Sel1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Sel1 ) ; return DAG . getNode ( <STR_LIT> , dl , ResVT , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Cmp ) , Sel1 , FV ) ; case <STR_LIT> : case <STR_LIT> : Cmp = DAG . getNode ( <STR_LIT> , dl , CmpVT , LHS , RHS ) ; if ( Cmp . getValueType ( ) == <STR_LIT> ) Cmp = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Cmp ) ; return DAG . getNode ( <STR_LIT> , dl , ResVT , Cmp , FV , TV ) ; case <STR_LIT> : case <STR_LIT> : Cmp = DAG . getNode ( <STR_LIT> , dl , CmpVT , LHS , RHS ) ; if ( Cmp . getValueType ( ) == <STR_LIT> ) Cmp = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Cmp ) ; return DAG . getNode ( <STR_LIT> , dl , ResVT , Cmp , TV , FV ) ; case <STR_LIT> : case <STR_LIT> : Cmp = DAG . getNode ( <STR_LIT> , dl , CmpVT , RHS , LHS ) ; if ( Cmp . getValueType ( ) == <STR_LIT> ) Cmp = DAG . getNode ( <STR_LIT> ,


<s> const <STR_LIT> & Out = Outs [ i ] ; if ( Out . VT . isVector ( ) ) { MVT VT = Out . VT . getVectorElementType ( ) ; <STR_LIT> NewOut = Out ; NewOut . Flags . setSplit ( ) ; NewOut . VT = VT ; unsigned NumElements = Out . ArgVT . getVectorNumElements ( ) ; for ( unsigned j = <NUM_LIT> ; j != NumElements ; ++ j ) { SDValue Elem = DAG . getNode ( <STR_LIT> , DL , VT , OutVals [ i ] , DAG . getConstant ( j , DL , <STR_LIT> ) ) ; SplitVals . push_back ( Elem ) ; Splits . push_back ( NewOut ) ; NewOut . PartOffset += NewOut . VT . getStoreSize ( ) ; } } else { SplitVals . push_back ( OutVals [ i ] ) ; Splits . push_back ( Out ) ; } } SmallVector < CCValAssign , <NUM_LIT> > RVLocs ; CCState CCInfo ( CallConv , isVarArg , DAG . getMachineFunction ( ) , RVLocs , * DAG . getContext ( ) ) ; AnalyzeReturn ( CCInfo , Splits ) ; SDValue Flag ; SmallVector < SDValue , <NUM_LIT> > RetOps ; RetOps . push_back ( Chain ) ; for ( unsigned i = <NUM_LIT> , realRVLocIdx = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i , ++ realRVLocIdx ) { CCValAssign & VA = RVLocs [ i ] ; assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; SDValue Arg = SplitVals [ realRVLocIdx ] ; switch ( VA . getLocInfo ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case CCValAssign :: Full : break ; case CCValAssign :: BCvt : Arg = DAG . getNode ( <STR_LIT> , DL , VA . getLocVT ( ) , Arg ) ; break ; } Chain = DAG . getCopyToReg ( Chain , DL , VA . getLocReg ( ) , Arg , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( VA . getLocReg ( ) , VA . getLocVT ( ) ) ) ; } RetOps [ <NUM_LIT> ] =


<s> if ( MO . getTargetFlags ( ) == <STR_LIT> ) GVSym = OutContext . GetOrCreateSymbol ( Twine ( <STR_LIT> ) + GVSym -> getName ( ) ) ; if ( MO . getTargetFlags ( ) == <STR_LIT> || MO . getTargetFlags ( ) == <STR_LIT> ) { MCSymbol * Sym = GetSymbolWithGlobalValueBase ( GV , <STR_LIT> ) ; MachineModuleInfoImpl :: StubValueTy & StubSym = MMI -> getObjFileInfo < MachineModuleInfoMachO > ( ) . getGVStubEntry ( Sym ) ; if ( StubSym . getPointer ( ) == <NUM_LIT> ) StubSym = MachineModuleInfoImpl :: StubValueTy ( Mang -> getSymbol ( GV ) , ! GV -> hasInternalLinkage ( ) ) ; } else if ( MO . getTargetFlags ( ) == <STR_LIT> ) { MCSymbol * Sym = GetSymbolWithGlobalValueBase ( GV , <STR_LIT> ) ; MachineModuleInfoImpl :: StubValueTy & StubSym = MMI -> getObjFileInfo < MachineModuleInfoMachO > ( ) . getHiddenGVStubEntry ( Sym ) ; if ( StubSym . getPointer ( ) == <NUM_LIT> ) StubSym = MachineModuleInfoImpl :: StubValueTy ( Mang -> getSymbol ( GV ) , ! GV -> hasInternalLinkage ( ) ) ; } else if ( MO . getTargetFlags ( ) == <STR_LIT> ) { MCSymbol * Sym = GetSymbolWithGlobalValueBase ( GV , <STR_LIT> ) ; MachineModuleInfoImpl :: StubValueTy & StubSym = MMI -> getObjFileInfo < MachineModuleInfoMachO > ( ) . getFnStubEntry ( Sym ) ; if ( StubSym . getPointer ( ) == <NUM_LIT> ) StubSym = MachineModuleInfoImpl :: StubValueTy ( Mang -> getSymbol ( GV ) , ! GV -> hasInternalLinkage ( ) ) ; } if ( GVSym -> getName ( ) [ <NUM_LIT> ] != '$' ) O << * GVSym ; else O << '(' << * GVSym << ')' ; printOffset ( MO . getOffset ( ) , O ) ; break ; } case MachineOperand :: MO_ExternalSymbol : { const MCSymbol * SymToPrint ; if ( MO . getTargetFlags ( ) == <STR_LIT> ) { SmallString < <NUM_LIT> > TempNameStr ; TempNameStr += StringRef ( MO . getSymbolName ( ) ) ; TempNameStr += StringRef ( <STR_LIT> ) ; MCSymbol * Sym = GetExternalSymbolSymbol ( TempNameStr . str ( ) ) ; MachineModuleInfoImpl :: StubValueTy & StubSym = MMI -> getObjFileInfo < MachineModuleInfoMachO > ( ) . getFnStubEntry ( Sym ) ; if ( StubSym . getPointer ( ) == <NUM_LIT> ) { TempNameStr . erase ( TempNameStr . end ( ) - <NUM_LIT> , TempNameStr . end ( ) ) ; StubSym = MachineModuleInfoImpl :: StubValueTy ( OutContext . GetOrCreateSymbol ( TempNameStr . str ( ) ) , true ) ; } SymToPrint = StubSym . getPointer ( ) ; } else { SymToPrint = GetExternalSymbolSymbol ( MO . getSymbolName ( ) ) ; } if ( SymToPrint -> getName ( ) [ <NUM_LIT> ]


<s> assert ( ( N -> getOpcode ( ) == <STR_LIT> || N -> getOpcode ( ) == <STR_LIT> ) && <STR_LIT> ) ; if ( ! isa < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) || cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) != <NUM_LIT> ) return SDValue ( ) ; if ( ST -> isThumb1Only ( ) ) return SDValue ( ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N -> getOperand ( <NUM_LIT> ) , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N -> getOperand ( <NUM_LIT> ) , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; unsigned Opc = N -> getOpcode ( ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; Hi = DAG . getNode ( Opc , dl , DAG . getVTList ( <STR_LIT> , <STR_LIT> ) , & Hi , <NUM_LIT> ) ; Lo = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Lo , Hi . getValue ( <NUM_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> ,


<s> __builtin_altivec_stvebx ( ( vector signed char ) a1 ,


<s> static inline bool hasLEAOffset ( const MachineOperand & Offset ) { return ( Offset . isImm ( ) && Offset . getImm (

) != <NUM_LIT> ) || Offset . isGlobal ( ) ;


<s> APInt ToMask , FromMask ; SDValue From = ParseBFI ( N , ToMask , FromMask ) ; SDValue To = N -> getOperand ( <NUM_LIT> ) ; SDValue V = To ; if ( V . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; APInt NewToMask , NewFromMask ; SDValue NewFrom = ParseBFI ( V . getNode ( ) , NewToMask ,


<s> if ( getStubFactory ( ) == NULL ) return false ; getStubFactory ( ) -> addPrototype ( new <ISA_LIT>LA25Stub ( * this )


<s> bool <ISA_LIT>AsmParser :: ParseLiteralValues ( unsigned Size , SMLoc L ) { auto parseOne = [ & ] ( ) -> bool { const MCExpr * Value ; if ( getParser ( ) . parseExpression (


<s> FunctionPass * llvm :: create<ISA_LIT>ArgumentMove ( ) { return new <ISA_LIT>ArgumentMove


<s> int size = int_size_in_bytes ( type ) ; if ( size <= <NUM_LIT> ) ++ cum -> words ; else if ( size <= <NUM_LIT> ) cum -> words += <NUM_LIT> ; else ++ cum -> words ; } else { cum -> words += ( mode != BLKmode ? ROUND_ADVANCE ( GET_MODE_SIZE ( mode ) )

: ROUND_ADVANCE ( int_size_in_bytes ( type ) ) ) ;


<s> if ( strcmp ( name , <STR_LIT> ) == <NUM_LIT> && cfun -> machine -> red_partition ) { fprintf ( file , <STR_LIT> ) ; fprintf ( file , <STR_LIT> ) ; fprintf ( file , <STR_LIT> <STR_LIT> , REGNO ( cfun -> machine -> red_partition ) , vector_red_partition ) ; } gcc_assert ( vector_red_partition * nvptx_mach_max_workers ( ) <= vector_red_size ) ; fprintf ( file


<s> const <ISA_LIT>FrameLowering * TFI = MF . getSubtarget < GCNSubtarget > ( ) . getFrameLowering ( ) ; const <ISA_LIT>MachineFunctionInfo * FuncInfo = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; return TFI -> hasFP ( MF ) ? FuncInfo -> getFrameOffsetReg ( ) : FuncInfo ->


<s> return frv_function_arg_1 ( cum , arg ,


<s> for ( int i = MI . getNumOperands ( ) - <NUM_LIT> ; i > OperandToKeep ; i -- ) MI . RemoveOperand ( i ) ; if ( LII . SetCR ) { MI . setDesc ( get ( LII . Is64Bit ? <STR_LIT> : <STR_LIT> ) ) ; MachineInstrBuilder ( * MI . getParent ( ) -> getParent ( ) , MI ) . addImm ( LII . Imm ) . addReg ( <STR_LIT> , RegState :: ImplicitDefine ) ; return ; } else MI . setDesc ( get ( LII . Is64Bit ? <STR_LIT> : <STR_LIT> ) ) ; MachineInstrBuilder ( * MI . getParent ( ) -> getParent ( ) , MI ) . addImm ( LII


<s> const MCSymbol * PersonalitySym = getContext ( ) . GetOrCreateSymbol ( Name ) ; const MCSymbolRefExpr * PersonalityRef = MCSymbolRefExpr :: Create ( PersonalitySym , MCSymbolRefExpr :: VK_<ISA_LIT>_NONE , getContext ( ) ) ; AddValueSymbols ( PersonalityRef )


<s> if ( VT != <STR_LIT> && VT != <STR_LIT> && VT != <STR_LIT> ) return SDValue ( ) ; SDValue Sub = Op0 . getOperand ( <NUM_LIT> ) ; if ( Sub . getOpcode ( ) == <STR_LIT> ) { SDValue SubOp0 = Sub . getOperand ( <NUM_LIT> ) ; SDValue SubOp1 = Sub . getOperand ( <NUM_LIT> ) ; if ( ( SubOp0 . getOpcode ( ) == <STR_LIT> ) && ( SubOp1 . getOpcode ( ) == <STR_LIT> ) ) { return DCI . DAG . getNode ( <STR_LIT> , dl , VT , SubOp0 . getOperand ( <NUM_LIT> ) , SubOp1 . getOperand ( <NUM_LIT> ) , DCI . DAG . getTargetConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; } } } if ( Op0 . getValueType ( ) != <STR_LIT> || N -> getValueType ( <NUM_LIT> ) != <STR_LIT> ) return SDValue ( ) ; int EltToExtract = DCI . DAG . getDataLayout ( ) . isBigEndian ( ) ? <NUM_LIT> : <NUM_LIT> ; if ( Op0 . getOpcode ( ) == <STR_LIT> ) { ConstantSDNode * ConstNode = dyn_cast < ConstantSDNode > ( Op0 . getOperand ( <NUM_LIT> ) ) ; if ( ! ConstNode || ConstNode -> getZExtValue ( ) != <NUM_LIT> ) return SDValue ( ) ; EltToExtract = EltToExtract ? <NUM_LIT> : <NUM_LIT> ; Op0 = Op0 . getOperand ( <NUM_LIT> ) ; } if ( Op0 . getOpcode ( ) == <STR_LIT> && Op0 . getValueType ( ) == <STR_LIT> && Op0 . getOperand ( <NUM_LIT> ) . getValueType ( ) == <STR_LIT> ) { SDValue Bitcast = DCI . DAG . getBitcast ( <STR_LIT> , Op0 . getOperand ( <NUM_LIT> ) ) ; return DCI . DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Bitcast , DCI . DAG . getTargetConstant ( EltToExtract , dl , <STR_LIT> ) ) ; } return SDValue ( )


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { ModulePass :: getAnalysisUsage ( AU


<s> unsigned Rn = get<ISA_LIT>RegisterNumbering ( MO . getReg ( ) ) ; unsigned Imm5 = MO1 . getImm ( ) ; return ( ( Imm5 & <NUM_LIT> ) << <NUM_LIT> ) |


<s> static bool visium_class_likely_spilled_p ( reg_class_t rclass ATTRIBUTE_UNUSED ) { return false


<s> MCObjectWriter * createObjectWriter ( raw_ostream


<s> assert ( ValVT . getFixedSizeInBits ( ) < LocVT . getFixedSizeInBits ( ) ) ; if ( Flags . isSExt ( ) ) ArgValue = DAG . getNode ( <STR_LIT> , dl , LocVT , ArgValue , DAG


<s> MI . addOperand ( MCOperand :: createImm ( <ISA_LIT>ValToCondCode ( cf , isIntegerBCKind ( MI ) ) ) ) ; return MCDisassembler ::


<s> LROpOut = DAG . getLoad ( VT , dl , Chain , LROpOut , MachinePointerInfo ( ) , false , false , false , <NUM_LIT> ) ; Chain = SDValue ( LROpOut . getNode ( ) , <NUM_LIT> ) ; if ( Subtarget . isDarwinABI ( ) ) { FPOpOut = getFramePointerFrameIndex ( DAG ) ; FPOpOut = DAG . getLoad ( VT , dl , Chain , FPOpOut , MachinePointerInfo ( ) , false , false , false , <NUM_LIT> ) ; Chain = SDValue ( FPOpOut . getNode


<s> if ( ! op0_preserve_value && GET_CODE ( * op0 ) == FLOAT && MEM_P ( XEXP ( * op0 , <NUM_LIT> ) ) && REG_P ( * op1 ) ) { enum rtx_code scode = swap_condition ( ( enum rtx_code ) * code


<s> if ( OpReg == <NUM_LIT> ) return false ; unsigned ResultReg = createResultReg ( <STR_LIT> ) ; BuildMI ( MBB , DL , TII . get ( <STR_LIT> ) , ResultReg ) . addReg ( OpReg ) ; UpdateValueMap ( I ,


<s> OpRef R = shuffp1 ( ShuffleMask ( MaskR ) , Vb , Results ) ; if ( ! L . isValid ( ) || ! R . isValid ( ) ) return OpRef :: fail ( ) ; SmallVector < uint8_t , <NUM_LIT> > Bytes ( VecLen ) ; for ( int I = <NUM_LIT> ; I != VecLen ; ++ I ) { if ( MaskL [ I ] != - <NUM_LIT> ) Bytes [ I ] = <NUM_LIT> ; } return vmuxp ( Bytes , L , R , Results


<s> void setCalleeSavedFrameSize ( unsigned Bytes ) { CalleeSavedFrameSize = Bytes


<s> gcc_assert ( GET_CODE ( body ) == SET && GET_CODE ( SET_DEST ( body ) ) == MEM && GET_CODE ( SET_SRC ( body ) ) == VEC_SELECT ) ; rtx mem = SET_DEST ( body ) ; rtx base_reg = XEXP ( mem , <NUM_LIT> ) ; rtx and_operation = find_alignment_op ( insn , base_reg ) ; if ( and_operation != <NUM_LIT> ) { rtx src_reg = XEXP ( SET_SRC ( body ) ,


) ) incoming_stack_boundary = MAIN_STACK_BOUNDARY ;


<s> mips_get_arg_info ( & info , cum , arg . mode , arg . type , arg . named ) ; if ( info . reg_offset == MAX_ARGS_IN_REGISTERS ) return NULL ; if ( TARGET_NEWABI && TARGET_HARD_FLOAT && arg . named && arg . type != <NUM_LIT> && TREE_CODE ( arg . type ) == RECORD_TYPE && TYPE_SIZE_UNIT ( arg . type ) && tree_fits_uhwi_p ( TYPE_SIZE_UNIT ( arg . type ) ) ) { tree field ; for ( field = TYPE_FIELDS ( arg . type ) ; field ; field = DECL_CHAIN ( field ) ) if ( TREE_CODE ( field ) == FIELD_DECL && SCALAR_FLOAT_TYPE_P ( TREE_TYPE ( field ) ) && TYPE_PRECISION ( TREE_TYPE ( field ) ) == BITS_PER_WORD && tree_fits_shwi_p ( bit_position ( field ) ) && int_bit_position ( field ) % BITS_PER_WORD == <NUM_LIT> ) break ; if ( field != <NUM_LIT> ) { unsigned int i ; HOST_WIDE_INT bitpos ; rtx ret ; ret = gen_rtx_PARALLEL ( arg . mode , rtvec_alloc ( info . reg_words ) ) ; bitpos = <NUM_LIT> ; field = TYPE_FIELDS ( arg . type ) ; for ( i = <NUM_LIT> ; i < info . reg_words ; i ++ ) { rtx reg ; bool zero_width_field_abi_change = false ; for ( ; field ; field = DECL_CHAIN ( field ) ) { if ( TREE_CODE ( field ) != FIELD_DECL ) continue ; if ( DECL_FIELD_CXX_ZERO_WIDTH_BIT_FIELD ( field ) ) continue ; if ( DECL_SIZE ( field ) && integer_zerop ( DECL_SIZE ( field ) ) ) { zero_width_field_abi_change = true ; continue ; } if ( int_bit_position ( field ) >= bitpos ) break ; } if ( field && int_bit_position ( field ) == bitpos && SCALAR_FLOAT_TYPE_P ( TREE_TYPE ( field ) ) && TYPE_PRECISION ( TREE_TYPE ( field ) ) == BITS_PER_WORD ) reg = gen_rtx_REG ( DFmode , FP_ARG_FIRST + info . reg_offset + i ) ; else { reg = gen_rtx_REG ( DImode , GP_ARG_FIRST + info . reg_offset + i ) ; zero_width_field_abi_change = false ; } if ( zero_width_field_abi_change && warn_psabi ) { static unsigned last_reported_type_uid ; unsigned uid = TYPE_UID ( TYPE_MAIN_VARIANT ( arg . type ) ) ; if ( uid != last_reported_type_uid ) { static const char * url = CHANGES_ROOT_URL <STR_LIT> ; inform ( input_location , <STR_LIT> <STR_LIT> <STR_LIT> <STR_LIT> , url ) ; last_reported_type_uid = uid ; } } XVECEXP ( ret , <NUM_LIT> , i ) = gen_rtx_EXPR_LIST ( VOIDmode

, reg , GEN_INT ( bitpos / BITS_PER_UNIT ) ) ;


<s> MCCodeEmitter * llvm :: create<ISA_LIT>MCCodeEmitterEL ( const MCInstrInfo & MCII , const MCRegisterInfo & MRI , MCContext & Ctx ) { return new <ISA_LIT>MCCodeEmitter ( MCII , Ctx , true


<s> SmallVector < MachineInstr * , <NUM_LIT> > DeadInstrs ; ArtCombiner . tryCombineUnmergeValues ( MI , DeadInstrs , UpdatedDefs , Observer ) ; for ( MachineInstr * DeadMI : DeadInstrs ) DeadMI


<s> return ( __m512i ) __builtin_ia32_cvtps2uqq512_mask ( ( __v8sf ) __A , ( __v8di ) _mm512_setzero_si512 ( ) , ( __mmask8


<s> static bool isAddSubSExt ( SDNode * N , SelectionDAG & DAG ) { unsigned Opcode = N -> getOpcode ( ) ; if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) { SDNode * N0 = N -> getOperand ( <NUM_LIT> ) . getNode ( ) ; SDNode * N1 = N -> getOperand ( <NUM_LIT> ) . getNode ( ) ; return N0 -> hasOneUse ( ) && N1 -> hasOneUse ( ) && isSignExtended ( N0 , DAG


<s> if ( final_sequence ) output_asm_insn ( <STR_LIT> , operands ) ; else output_asm_insn ( <STR_LIT> , operands ) ; } else { output_asm_insn ( <STR_LIT> , operands ) ; if ( final_sequence ) { rtx delay = NEXT_INSN ( insn ) ; gcc_assert ( delay ) ; output_restore ( PATTERN ( delay ) ) ; PATTERN ( delay ) = gen_blockage ( ) ; INSN_CODE ( delay ) = -


<s> if ( SCRATCH != GET_CODE ( scratch ) && HImode == GET_MODE ( scratch ) && QImode == move_mode ) scratch = simplify_gen_subreg ( move_mode , scratch , HImode , <NUM_LIT> ) ; move_size = GET_MODE_SIZE ( move_mode ) ; offset = ( num >> <NUM_LIT> ) / move_size ; size = GET_MODE_SIZE ( mode ) / move_size ; if ( mode == HImode && same_reg ) { rtx src , dst ; src = simplify_gen_subreg ( move_mode , operands [ <NUM_LIT> ] , mode , <NUM_LIT> ) ; dst = simplify_gen_subreg ( move_mode , operands [ <NUM_LIT> ] , mode , <NUM_LIT> ) ; if ( ! rtx_equal_p ( dst , src ) ) { emit_move_insn ( dst , gen_rtx_XOR ( QImode , dst , src ) ) ; emit_move_insn ( src , gen_rtx_XOR ( QImode , src , dst ) ) ; emit_move_insn ( dst , gen_rtx_XOR ( QImode , dst , src ) ) ; } } else { struct { rtx src , dst ; int links ; } move [ MAX_SIZE + <NUM_LIT> ] ; int blocked , moves ; gcc_assert ( size <= MAX_SIZE ) ; for ( int i = <NUM_LIT> ; i < size ; i ++ ) { int from = i ; int to = ( from + offset ) % size ; move [ i ] . src = simplify_gen_subreg ( move_mode , operands [ <NUM_LIT> ] , mode , from * move_size ) ; move [ i ] . dst = simplify_gen_subreg ( move_mode , operands [ <NUM_LIT> ] , mode , to * move_size ) ; move [ i ] . links = - <NUM_LIT> ; } if ( overlapped ) for ( int i = <NUM_LIT> ; i < size ; i ++ ) if ( reg_overlap_mentioned_p ( move [ i ] . dst , operands [ <NUM_LIT> ] ) ) for ( int j = <NUM_LIT> ; j < size ; j ++ ) if ( j != i && rtx_equal_p ( move [ j ] . src , move [ i ] . dst ) ) { move [ i ] . links = j ; break ; } blocked = - <NUM_LIT> ; moves = <NUM_LIT> ; do { blocked = - <NUM_LIT> ; moves = <NUM_LIT> ; for ( int i = <NUM_LIT> ; i < size ; i ++ ) if ( move [ i ] .


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT>


<s> if ( SyntaxVariant == <NUM_LIT> ) return new <ISA_LIT>InstPrinter ( MAI , MII , MRI ) ; return nullptr


<s> { MO_ABS_HI , <STR_LIT> } , { MO_ABS_LO , <STR_LIT> } , } ; return makeArrayRef ( Flags


<s> case <STR_LIT> : return LowerConstantPool ( Op , DAG ) ; case <STR_LIT> : return LowerDYNAMIC_STACKALLOC ( Op , DAG ) ; case <STR_LIT> : return LowerGlobalAddress ( Op , DAG ) ; case <STR_LIT> : return LowerBlockAddress ( Op , DAG ) ; case <STR_LIT> : return LowerGlobalTLSAddress ( Op , DAG ) ; case <STR_LIT> : return LowerJumpTable ( Op , DAG ) ; case <STR_LIT> : return LowerSELECT ( Op , DAG ) ; case <STR_LIT> : return LowerVASTART ( Op , DAG


<s> bool IsOnlyPredicatedOn ( MachineInstr * MI ) const { return IsPredicatedOn ( MI ) && VPST -> Predicates . size ( )


<s> static Target TheDirectXTarget ; return


<s> inline vector signed int vec_vmaxsw ( vector signed int a1 ,


<s> VT = TLI . getValueType ( Ty , true ) ; if ( VT == <STR_LIT> || ! VT . isSimple ( )


<s> PM -> add ( create<ISA_LIT>BranchSelectionPass


<s> const <ISA_LIT>RegisterInfo * TRI = ST . getRegisterInfo ( ) ; <ISA_LIT>MachineFunctionInfo * FuncInfo = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; FuncInfo -> removeDeadFrameIndices ( MFI ) ; assert ( allSGPRSpillsAreDead ( MF ) && <STR_LIT>


<s> if ( Opd2Info == TargetTransformInfo :: OK_UniformConstantValue ) { auto VT = TLI -> getValueType ( DL , Ty ) ; if ( TLI -> isOperationLegalOrCustom ( <STR_LIT> , VT ) ) { int MulCost = getArithmeticInstrCost ( Instruction :: Mul , Ty , CostKind , Opd1Info , Opd2Info , TargetTransformInfo :: OP_None , TargetTransformInfo :: OP_None ) ; int AddCost = getArithmeticInstrCost ( Instruction :: Add , Ty , CostKind , Opd1Info , Opd2Info , TargetTransformInfo :: OP_None , TargetTransformInfo :: OP_None ) ; int ShrCost = getArithmeticInstrCost ( Instruction :: AShr , Ty , CostKind , Opd1Info , Opd2Info , TargetTransformInfo :: OP_None , TargetTransformInfo :: OP_None ) ; return MulCost * <NUM_LIT> + AddCost * <NUM_LIT> + ShrCost * <NUM_LIT> + <NUM_LIT> ; } } Cost += BaseT :: getArithmeticInstrCost ( Opcode , Ty , CostKind , Opd1Info , Opd2Info , Opd1PropInfo , Opd2PropInfo ) ; if ( Ty -> isVectorTy ( ) ) { Cost += getArithmeticInstrCost ( Instruction :: ExtractElement , Ty , CostKind , Opd1Info , Opd2Info , Opd1PropInfo , Opd2PropInfo ) ; Cost += getArithmeticInstrCost ( Instruction :: InsertElement , Ty , CostKind , Opd1Info , Opd2Info , Opd1PropInfo , Opd2PropInfo ) ; Cost += Cost ; } return


<s> ArgTypes . push_back ( ImageSizeType ) ; ArgMD [ <NUM_LIT> ] = ArgMD [ <NUM_LIT> ] = MDString :: get ( * Context , ImageSizeArgMDType ) ; PushArgMD ( NewArgMDs , ArgMD ) ; ArgTypes . push_back ( ImageFormatType ) ; ArgMD [ <NUM_LIT> ] = ArgMD [ <NUM_LIT> ] = MDString :: get ( * Context , ImageFormatArgMDType ) ; PushArgMD ( NewArgMDs , ArgMD ) ; Modified = true ; } if ( ! Modified ) { return std :: make_tuple ( nullptr , nullptr ) ; } auto NewFT = FunctionType :: get ( FT -> getReturnType ( ) , ArgTypes , false ) ; auto NewF = Function :: Create ( NewFT , F -> getLinkage ( ) , F -> getAddressSpace ( ) , F -> getName ( ) ) ; ValueToValueMapTy VMap ; auto NewFArgIt = NewF


<s> return true ; } case FusionFeature :: FK_SldiAdd : return ( matchingImmOps ( FirstMI , <NUM_LIT> , <NUM_LIT> ) && matchingImmOps ( FirstMI , <NUM_LIT> , <NUM_LIT> ) ) || ( matchingImmOps ( FirstMI , <NUM_LIT> , <NUM_LIT> ) && matchingImmOps ( FirstMI , <NUM_LIT> , <NUM_LIT> ) ) ; case FusionFeature :: FK_RotateLeftXor : return matchingImmOps ( FirstMI , <NUM_LIT> , <NUM_LIT> ) && matchingImmOps ( FirstMI , <NUM_LIT> , <NUM_LIT> ) ; case FusionFeature :: FK_RotateRightXor : return matchingImmOps ( FirstMI , <NUM_LIT> , <NUM_LIT> ) && matchingImmOps ( FirstMI , <NUM_LIT> , <NUM_LIT> ) ; case FusionFeature :: FK_LoadCmp1 : case FusionFeature :: FK_LoadCmp2 : { const MachineOperand & BT = SecondMI . getOperand ( <NUM_LIT> ) ; if ( ! BT . isReg ( ) || ( ! Register :: isVirtualRegister ( BT . getReg ( ) ) && BT . getReg ( ) != <STR_LIT> ) ) return false ; if ( SecondMI . getOpcode ( ) == <STR_LIT> && matchingImmOps ( SecondMI , <NUM_LIT> , - <NUM_LIT> , <NUM_LIT> ) ) return true ; return matchingImmOps ( SecondMI , <NUM_LIT> , <NUM_LIT> ) || matchingImmOps ( SecondMI , <NUM_LIT> , <NUM_LIT> ) ; } case FusionFeature :: FK_LoadCmp3 : { const MachineOperand & BT = SecondMI . getOperand ( <NUM_LIT> ) ; if ( ! BT . isReg ( ) || ( ! Register :: isVirtualRegister ( BT . getReg ( ) ) && BT . getReg ( ) != <STR_LIT> ) ) return false ; return matchingImmOps ( SecondMI , <NUM_LIT> , <NUM_LIT> ) || matchingImmOps ( SecondMI , <NUM_LIT> , <NUM_LIT> ) || matchingImmOps ( SecondMI , <NUM_LIT> , - <NUM_LIT> , <NUM_LIT> ) ; } case FusionFeature :: FK_ZeroMoveCTR : return ( FirstMI . getOpcode ( ) != <STR_LIT> && FirstMI . getOpcode ( ) != <STR_LIT> ) || matchingImmOps ( FirstMI , <NUM_LIT> , <NUM_LIT> ) ; case FusionFeature :: FK_ZeroMoveLR : return ( FirstMI . getOpcode ( ) != <STR_LIT> && FirstMI . getOpcode ( ) != <STR_LIT> ) || matchingImmOps ( FirstMI , <NUM_LIT> , <NUM_LIT> ) ; case FusionFeature ::


<s> if ( ! MI -> isPseudo ( ) ) Resources -> reserveResources ( * MI ) ; CurrentPacket . push_back ( SU )


<s> auto it = std :: find ( RealNext -> getChildren ( ) -> begin ( ) , RealNext -> getChildren ( ) -> end ( ) , LoopHead ) ; if ( it != RealNext -> getChildren ( ) -> end ( ) )


<s> void addAM2OffsetImmOperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT> ) ; const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; assert ( CE && <STR_LIT> ) ; int32_t Val = CE -> getValue ( ) ; <STR_LIT> AddSub = Val < <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; if ( Val == INT32_MIN )


<s> static unsigned char csky_class_max_nregs ( reg_class_t rclass , machine_mode mode ) { if ( rclass == V_REGS ) return <NUM_LIT> ; else return CSKY_NUM_REGS


<s> ELF<ISA_LIT>AsmBackend ( const Target & T , Triple :: OSType _OSType ) : <ISA_LIT>AsmBackend ( T ) , OSType ( _OSType ) { HasScatteredSymbols =


<s> Offset = CP -> getOffset ( ) ; } else if ( ExternalSymbolSDNode * S = dyn_cast < ExternalSymbolSDNode > ( N0 ) ) { AM . ES = S -> getSymbol ( ) ; AM . SymbolFlags = S -> getTargetFlags ( ) ; } else if ( auto * S = dyn_cast < MCSymbolSDNode > ( N0 ) ) { AM . MCSym = S -> getMCSymbol ( ) ; } else if ( JumpTableSDNode * J = dyn_cast < JumpTableSDNode > ( N0 ) ) { AM . JT = J -> getIndex ( ) ; AM . SymbolFlags = J -> getTargetFlags ( ) ; } else if ( BlockAddressSDNode * BA = dyn_cast < BlockAddressSDNode > ( N0 ) ) { AM . BlockAddr = BA -> getBlockAddress ( ) ; AM . SymbolFlags = BA -> getTargetFlags ( ) ; Offset = BA -> getOffset ( ) ; } else llvm_unreachable ( <STR_LIT> ) ; if ( foldOffsetIntoAddress ( Offset ,


<s> bool has<ISA_LIT>32r2 ( ) const { return ( STI . getFeatureBits ( )


<s> bool isUImm1 ( ) const { return isUImm < <NUM_LIT>


<s> bool fixupNeedsRelaxation ( const MCFixup & Fixup , uint64_t Value , const MCRelaxableFragment * DF , const MCAsmLayout & Layout ) const override { return


<s> if ( Type == <STR_LIT> || Type == <STR_LIT> || Type == <STR_LIT> || Type == <STR_LIT> || Type == <STR_LIT> || Type == <STR_LIT> || Type == <STR_LIT> ) return <STR_LIT> :: V128 ; if ( Type == <STR_LIT> ) return


<s> default : llvm_unreachable ( <STR_LIT> ) ; case Instruction :: LShr : OpReg = <STR_LIT> ; break ; case Instruction :: AShr : OpReg = <STR_LIT> ; break ; case Instruction :: Shl : OpReg = <STR_LIT> ; break ; } } else if ( I -> getType ( ) -> isIntegerTy ( <NUM_LIT> ) ) { CReg = <STR_LIT> ; RC = & <STR_LIT> ; switch ( I -> getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case Instruction :: LShr : OpReg = <STR_LIT> ; break ; case Instruction :: AShr : OpReg = <STR_LIT> ; break ; case Instruction :: Shl : OpReg = <STR_LIT> ; break ; } } else { return false ; } MVT VT ; if ( ! isTypeLegal ( I -> getType ( ) , VT ) ) return false ; unsigned Op0Reg = getRegForValue ( I -> getOperand ( <NUM_LIT> ) ) ; if ( Op0Reg == <NUM_LIT> ) return


<s> if ( ArgFlags . isSExt ( ) ) LocInfo = CCValAssign :: SExt ; else if ( ArgFlags . isZExt ( ) ) LocInfo = CCValAssign :: ZExt ; else LocInfo = CCValAssign :: AExt ; } unsigned Reg ; bool AllocateFloatsInIntReg = State . isVarArg ( ) || ValNo > <NUM_LIT> || State . getFirstUnallocated ( F32Regs , FloatRegsSize ) != ValNo ; unsigned OrigAlign = ArgFlags . getOrigAlign ( ) ; bool isI64 = ( ValVT == <STR_LIT> && OrigAlign == <NUM_LIT> ) ; if ( ValVT == <STR_LIT> || ( ValVT == <STR_LIT> && AllocateFloatsInIntReg ) ) { Reg = State . AllocateReg ( IntRegs , IntRegsSize ) ; if ( isI64 && ( Reg == <STR_LIT> || Reg == <STR_LIT> ) ) Reg = State . AllocateReg ( IntRegs , IntRegsSize ) ; LocVT = <STR_LIT> ; } else if ( ValVT == <STR_LIT> && AllocateFloatsInIntReg ) { Reg = State . AllocateReg ( IntRegs , IntRegsSize ) ; if ( Reg == <STR_LIT> || Reg == <STR_LIT> ) Reg = State . AllocateReg ( IntRegs , IntRegsSize ) ; State . AllocateReg ( IntRegs , IntRegsSize ) ; LocVT = <STR_LIT> ; } else if ( ValVT . isFloatingPoint ( ) && ! AllocateFloatsInIntReg ) { if ( ValVT == <STR_LIT> ) { Reg = State . AllocateReg ( F32Regs , FloatRegsSize ) ; State . AllocateReg ( IntRegs , IntRegsSize ) ; } else { Reg = State . AllocateReg ( F64Regs , FloatRegsSize ) ; unsigned Reg2 = State . AllocateReg ( IntRegs , IntRegsSize ) ; if ( Reg2 == <STR_LIT> || Reg2 == <STR_LIT> ) State . AllocateReg ( IntRegs , IntRegsSize ) ; State . AllocateReg ( IntRegs , IntRegsSize ) ; } } else llvm_unreachable ( <STR_LIT> ) ; unsigned SizeInBytes = ValVT . getSizeInBits ( ) >> <NUM_LIT> ; unsigned Offset ; if ( ! ArgFlags . isSRet ( ) ) Offset =

State . AllocateStack ( SizeInBytes , OrigAlign ) ;


<s> MCAsmBackend * llvm :: create<ISA_LIT>AsmBackend ( Target const & T , const MCSubtargetInfo & STI , MCRegisterInfo const & , const MCTargetOptions & Options ) { const Triple & TT = STI . getTargetTriple ( ) ; uint8_t OSABI = MCELFObjectTargetWriter :: getOSABI ( TT . getOS ( ) ) ; StringRef CPUString = <ISA_LIT>_MC :: select<ISA_LIT>CPU ( STI .


<s> DeleteRet = true ; LdmOpc = AFI -> isThumbFunction ( ) ? <STR_LIT> : <STR_LIT> ; } else LdmOpc = AFI -> isThumbFunction ( ) ? <STR_LIT> : <STR_LIT> ; } if ( NoGap && LastReg && LastReg != Reg - <NUM_LIT> ) break ; LastReg = Reg ; Regs . push_back ( Reg ) ; } if ( Regs . empty ( ) ) continue ; if ( Regs . size ( ) > <NUM_LIT> || LdrOpc == <NUM_LIT> ) { MachineInstrBuilder MIB = AddDefaultPred ( BuildMI ( MBB , MI , DL , TII . get ( LdmOpc ) , <STR_LIT> ) . addReg ( <STR_LIT> ) ) ; for ( unsigned i = <NUM_LIT> , e = Regs . size ( ) ; i < e ; ++ i ) MIB . addReg ( Regs [ i ] , getDefRegState ( true ) ) ; if ( DeleteRet && MI != MBB . end ( ) ) { MIB . copyImplicitOps ( & * MI ) ; MI -> eraseFromParent ( ) ; } MI = MIB ; } else if ( Regs . size ( ) == <NUM_LIT> ) { if ( Regs [ <NUM_LIT> ] == <STR_LIT> ) Regs [ <NUM_LIT>


<s> word_type i ; if ( b & <NUM_LIT> ) a >>= <NUM_LIT> ; if ( b & <NUM_LIT> ) a >>= <NUM_LIT> ; for ( i = ( b & <NUM_LIT> ) ; i > <NUM_LIT> ; -- i )


<s> <ISA_LIT>LongBranch ( TargetMachine & tm ) : MachineFunctionPass ( ID ) , TM ( tm ) , IsPIC ( TM . getRelocationModel ( ) == Reloc :: PIC_ ) , ABI ( TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . getABI ( ) ) , LongBranchSeqSize ( ! IsPIC ? <NUM_LIT> : ( ABI . IsN64 ( ) ? <NUM_LIT> : ( ! TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . isTargetNaCl ( ) ? <NUM_LIT>


<s> if ( ( flags & OPTION_MASK_SOFT_FLOAT ) != <NUM_LIT> ) rs6000_define_or_undefine_macro ( define_p , <STR_LIT> ) ; if ( ( flags & OPTION_MASK_RECIP_PRECISION ) != <NUM_LIT> ) rs6000_define_or_undefine_macro ( define_p , <STR_LIT> ) ; if ( ( flags & OPTION_MASK_ALTIVEC ) != <NUM_LIT> ) { const char * vec_str = ( define_p ) ? <STR_LIT> : <STR_LIT> ; rs6000_define_or_undefine_macro ( define_p , <STR_LIT> ) ; rs6000_define_or_undefine_macro ( define_p , vec_str ) ; if ( ! flag_iso ) rs6000_define_or_undefine_macro ( define_p , <STR_LIT> ) ; } if ( ( flags & OPTION_MASK_VSX ) != <NUM_LIT> ) rs6000_define_or_undefine_macro ( define_p , <STR_LIT> ) ; if ( ( flags & OPTION_MASK_HTM ) != <NUM_LIT> ) rs6000_define_or_undefine_macro ( define_p , <STR_LIT> ) ; if ( ( flags & OPTION_MASK_P8_VECTOR ) != <NUM_LIT> ) rs6000_define_or_undefine_macro ( define_p , <STR_LIT> ) ; if ( ( flags & OPTION_MASK_QUAD_MEMORY ) != <NUM_LIT> ) rs6000_define_or_undefine_macro ( define_p , <STR_LIT> ) ; if ( ( flags & OPTION_MASK_QUAD_MEMORY_ATOMIC ) != <NUM_LIT> ) rs6000_define_or_undefine_macro ( define_p , <STR_LIT> ) ; if ( ( flags & OPTION_MASK_CRYPTO ) != <NUM_LIT> ) rs6000_define_or_undefine_macro ( define_p , <STR_LIT> ) ; if ( ( flags & OPTION_MASK_UPPER_REGS_DF ) != <NUM_LIT>


<s> assert ( MO . isReg ( ) && <STR_LIT> ) ; const TargetRegisterInfo * RI = STI -> getRegisterInfo ( ) ; Register Reg = MO . getReg ( ) ; unsigned RegToPrint = RC -> getRegister ( RI -> getEncodingValue ( Reg ) ) ; if ( ! RI -> regsOverlap ( RegToPrint , Reg ) ) return true ; O << <ISA_LIT>InstPrinter :: getRegisterName ( RegToPrint ,


<s> iterator first = m_pSectionData -> getFragmentList ( ) . begin ( ) ; assert ( first != m_pSectionData -> getFragmentList ( ) . end ( ) && <STR_LIT> ) ; PLTEntryBase * plt0 = & ( llvm :: cast < PLTEntryBase > ( *


<s> bool isAM3 = Opcode == <STR_LIT> || Opcode == <STR_LIT> ; unsigned NumOperands = MI -> getDesc ( ) . getNumOperands ( ) ; unsigned OffField = MI -> getOperand ( NumOperands - <NUM_LIT> ) . getImm ( ) ; if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ) return OffField ; if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) return OffField * <NUM_LIT> ; int Offset = isAM3 ? <STR_LIT> ( OffField ) : <STR_LIT> ( OffField


<s> const TargetInstrInfo & TII = * MF . getTarget ( ) . getInstrInfo ( ) ; const <ISA_LIT>Subtarget & STI = MF . getTarget ( ) . getSubtarget < <ISA_LIT>Subtarget > ( ) ; for ( unsigned i = <NUM_LIT> , e = CSI . size ( ) ; i != e ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; if ( <STR_LIT> . contains ( Reg ) || <STR_LIT> . contains ( Reg ) ) continue ; const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass


<s> const MCExpr * <ISA_LIT>ElfTargetObjectFile :: getTTypeGlobalReference ( const GlobalValue * GV , unsigned Encoding , Mangler & Mang , const TargetMachine & TM , MachineModuleInfo * MMI , MCStreamer & Streamer ) const { if ( TM . getMCAsmInfo ( ) -> getExceptionHandlingType ( ) != ExceptionHandling :: <ISA_LIT> ) return TargetLoweringObjectFileELF :: getTTypeGlobalReference ( GV , Encoding , Mang , TM , MMI , Streamer ) ; assert ( Encoding ==


<s> bool <ISA_LIT>RegisterInfo :: needsFrameBaseReg ( MachineInstr * MI , int64_t Offset ) const { return false


<s> const bool HasCalls = F . hasFnAttribute ( <STR_LIT> ) ; const bool UseFixedABI = <ISA_LIT>TargetMachine :: EnableFixedFunctionABI && CC != CallingConv :: <ISA_LIT>_Gfx && ( ! isEntryFunction ( ) || HasCalls ) ; if ( CC == CallingConv :: <ISA_LIT>_KERNEL || CC == CallingConv :: SPIR_KERNEL ) { if ( ! F . arg_empty ( ) ) KernargSegmentPtr = true ; WorkGroupIDX = true ; WorkItemIDX = true ; } else if ( CC == CallingConv :: <ISA_LIT>_PS ) { P<ISA_LIT>nputAddr = <STR_LIT> ( F ) ; } if ( ! isEntryFunction ( ) ) { if ( UseFixedABI ) ArgInfo = <ISA_LIT>ArgumentUsageInfo :: FixedABIFunctionInfo ; FrameOffsetReg = <STR_LIT> ; StackPtrOffsetReg = <STR_LIT> ; if ( ! ST . enableFlatScratch ( ) ) { ScratchRSrcReg = <STR_LIT> ; ArgInfo . PrivateSegmentBuffer = ArgDescriptor :: createRegister ( ScratchRSrcReg ) ; } if ( F . hasFnAttribute ( <STR_LIT> ) ) ImplicitArgPtr = true ; } else { if ( F . hasFnAttribute ( <STR_LIT> ) ) { KernargSegmentPtr = true ; MaxKernArgAlign = std :: max ( ST . getAlignmentForImplicitArgPtr ( ) , MaxKernArgAlign ) ; } } if ( UseFixedABI ) { WorkGroupIDX = true ; WorkGroupIDY = true ; WorkGroupIDZ = true ; WorkItemIDX = true ; WorkItemIDY = true ; WorkItemIDZ = true ; ImplicitArgPtr = true ; } else { if ( F . hasFnAttribute ( <STR_LIT> ) ) WorkGroupIDX = true ; if ( F . hasFnAttribute ( <STR_LIT> ) ) WorkGroupIDY = true ; if ( F . hasFnAttribute ( <STR_LIT>


<s> static bool mips_truly_noop_truncation ( poly_uint64 outprec , poly_uint64 inprec ) { return ! TARGET_64BIT || inprec <= <NUM_LIT> ||


<s> if ( ! IsTailCall ) return IsIndirect ? getBLRCallOpcode ( CallerF ) : ( unsigned ) <STR_LIT> ; if ( ! IsIndirect ) return <STR_LIT> ; if ( CallerF . getInfo < <ISA_LIT>FunctionInfo > ( ) -> branchTargetEnforcement ( )


<s> if ( TM -> Options . ThreadModel == ThreadModel :: Single ) addPass ( createLowerAtomicPass ( ) ) ; else addPass ( createAtomicExpandPass ( ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableAtomicTidy ) addPass ( createCFGSimplificationPass ( SimplifyCFGOptions ( ) . hoistCommonInsts ( true ) . sinkCommonInsts ( true ) , [ this ] ( const Function & F ) { const auto & ST = this -> TM -> getSubtarget < <ISA_LIT>Subtarget > ( F ) ; return ST . hasAnyDataBarrier ( ) && ! ST . isThumb1Only ( ) ; } ) ) ; addPass ( createMVEGatherScatterLoweringPass ( ) ) ; addPass ( createMVELaneInterleavingPass ( ) ) ; TargetPassConfig :: addIRPasses ( ) ; if ( getOptLevel ( ) == CodeGenOpt :: Aggressive ) addPass ( create<ISA_LIT>ParallelDSPPass ( ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None ) addPass ( createInterleavedAccessPass ( ) ) ; if ( TM -> getTargetTriple ( ) . isOSWindows ( ) ) addPass


<s> error ( <STR_LIT> , <STR_LIT> , type ) ; return NULL_TREE ; } tree size = TREE_VALUE ( args ) ; if ( TREE_CODE ( size ) != INTEGER_CST ) { error ( <STR_LIT> , <STR_LIT> ) ; return NULL_TREE ; } unsigned HOST_WIDE_INT value = tree_to_uhwi ( size ) ; if ( maybe_ne ( value , BITS_PER_SVE_VECTOR ) ) { warning ( OPT_Wattributes , <STR_LIT> ) ; return NULL_TREE ; } tree new_sve_type_args = copy_list ( TREE_VALUE ( attr ) ) ; tree mangled_name_node = chain_index ( <NUM_LIT> , new_sve_type_args ) ; const char * old_mangled_name = IDENTIFIER_POINTER ( TREE_VALUE ( mangled_name_node ) ) ; char * new_mangled_name = xasprintf ( <STR_LIT> , old_mangled_name , ( int ) value ) ; TREE_VALUE ( mangled_name_node ) = get_identifier ( new_mangled_name ) ; free ( new_mangled_name ) ; tree new_type ; tree base_type = TYPE_MAIN_VARIANT ( type ) ; if ( lang_GNU_C ( ) && VECTOR_BOOLEAN_TYPE_P ( type ) ) new_type = build_variant_type_copy ( base_type ) ; else new_type = build_distinct_type_copy ( base_type ) ; tree acle_name_node = TREE_CHAIN (


<s> if ( VT . getSizeInBits ( ) == ( SubVT . getSizeInBits ( ) * <NUM_LIT> ) && Idx == ( VT . getVectorNumElements ( ) / <NUM_LIT> ) && Src . getOpcode ( ) == <STR_LIT> && Src . getOperand ( <NUM_LIT> ) . getValueType ( ) == SubVT && isNullConstant ( Src . getOperand ( <NUM_LIT> ) ) ) { Ops . push_back ( Src . getOperand ( <NUM_LIT> ) ) ; Ops . push_back ( Sub ) ; return true ; } } return false


<s> fprintf ( stream , <STR_LIT> ) ; fprintf ( stream , <STR_LIT> ) ; fprintf ( stream , <STR_LIT>


<s> if ( align_labels_log < <NUM_LIT> ) { rtx_insn * next = next_nonnote_nondebug_insn ( label


<s> size = GET_MODE_SIZE ( GET_MODE ( op ) ) ; operand_length = h8300_classify_operand ( op , size , & opclass ) ; switch ( opclass ) { case H8OP_MEM_BASE : case


<s> for ( MachineRegisterInfo :: use_iterator I = MRI . use_begin ( DstReg ) , E = MRI . use_end ( ) ; I != E ; ++ I ) { MachineInstr & UseMI = * I -> getParent ( ) ; if ( ! canReadVGPR ( UseMI , I .


<s> SmallVector < MachineInstr * , <NUM_LIT> > DeadCopies ; for ( MachineBasicBlock & MBB : * MF ) { for ( MachineInstr & MI : MBB ) { if ( MI . getOpcode ( ) != <STR_LIT> ) continue ; Register DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( ! isVreg1 ( SrcReg


<s> if ( first + size <= <NUM_LIT> ) { HOST_WIDE_INT i ; for ( i = PROBE_INTERVAL ; i < size ; i += PROBE_INTERVAL ) emit_stack_probe ( plus_constant ( Pmode , stack_pointer_rtx , - ( first + i ) ) ) ; emit_stack_probe ( plus_constant ( Pmode , stack_pointer_rtx , - ( first + size ) ) ) ; } else { HOST_WIDE_INT rounded_size ; rtx r12 = gen_rtx_REG ( Pmode , <NUM_LIT> ) ; rtx r0 = gen_rtx_REG ( Pmode , <NUM_LIT> ) ; gcc_assert ( first <= <NUM_LIT> ) ; rounded_size = size &


<s> return - <NUM_LIT> ; } ; unsigned Imm = getImm ( GPR ) ; if ( Imm == - <NUM_LIT> ) { LastVPTReg = <NUM_LIT> ; continue ; } unsigned NotImm = ~ Imm & <NUM_LIT> ; if ( LastVPTReg != <NUM_LIT> && LastVPTReg != VPR && LastVPTImm == Imm ) { Instr . getOperand ( PIdx + <NUM_LIT> ) . setReg ( LastVPTReg ) ; if ( MRI -> use_empty ( VPR ) ) { DeadInstructions . insert ( Copy ) ; if ( MRI -> hasOneUse ( GPR ) ) DeadInstructions . insert ( MRI -> getVRegDef ( GPR ) ) ; } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << Instr ) ; } else if ( LastVPTReg != <NUM_LIT> && LastVPTImm == NotImm ) { Register NewVPR = MRI -> createVirtualRegister ( & <STR_LIT> ) ; auto VPNot = BuildMI ( MBB , & Instr , Instr . getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , NewVPR ) . addReg ( LastVPTReg ) ; addUnpredicatedMveVpredNOp ( VPNot ) ; Instr . getOperand ( PIdx + <NUM_LIT> ) . setReg ( NewVPR ) ; if ( MRI -> use_empty ( VPR ) ) { DeadInstructions . insert ( Copy ) ; if ( MRI -> hasOneUse ( GPR ) ) DeadInstructions . insert ( MRI -> getVRegDef ( GPR ) ) ; } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * VPNot << <STR_LIT> << Instr ) ; VPR = NewVPR


<s> bool <ISA_LIT>TTIImpl :: isTypeLegal ( Type * Ty ) { return true


<s> void <ISA_LIT>InstPrinter :: printRegName ( raw_ostream & OS , unsigned RegNo


<s> assert ( <NUM_LIT> && <STR_LIT> ) ; } return new <ISA_LIT>LDBackend ( pConfig , new <ISA_LIT>GNUInfo ( pConfig . targets ( )


<s> Type * CmpOpTy = ( ( I != nullptr ) ? getCmpOpsType ( I , VF ) : nullptr ) ; if ( CmpOpTy != nullptr ) Cost = getVectorBitmaskConversionCost (


<s> void <ISA_LIT>Operand :: print ( raw_ostream &


<s> for ( DeferredEraseSetIter I = EraseSet . begin ( ) , E = EraseSet . end ( ) ; I != E ; I ++


<s> unsigned short base_mode_size = GET_MODE_SIZE ( base_mode ) ; int nregs = size / base_mode_size , i ; rtx regs ; regs = gen_rtx_PARALLEL ( BLKmode , rtvec_alloc ( nregs ) ) ; for ( i = <NUM_LIT> ; i < nregs ; i ++ ) { XVECEXP ( regs , <NUM_LIT> , i ) = gen_rtx_EXPR_LIST ( VOIDmode , gen_rtx_REG ( base_mode , regno ) , GEN_INT ( base_mode_size * i ) ) ; regno += base_mode_size /


<s> Vals . push_back ( VE . getTypeID ( V -> getType ( ) ) ) ; return true ; } return false


<s> FastISel * <STR_LIT> ( FunctionLoweringInfo & funcInfo , const TargetLibraryInfo * libInfo ) { const TargetMachine & TM = funcInfo . MF -> getTarget ( ) ; const <ISA_LIT>Subtarget * Subtarget = & TM . getSubtarget < <ISA_LIT>Subtarget > ( ) ; bool UseFastISel = false ; UseFastISel |= Subtarget -> isTargetMachO ( ) && ! Subtarget -> isThumb1Only ( ) ; UseFastISel |= Subtarget -> isTargetLinux ( ) &&


<s> return false ; } bool MadeChange = true ; bool EverMadeChange = false ; while ( MadeChange ) { MadeChange = false ; for ( MachineFunction :: iterator MFI = Fn . begin ( ) , E = Fn . end ( ) ; MFI != E ; ++ MFI ) { MachineBasicBlock & MBB = * MFI ; unsigned MBBStartOffset = <NUM_LIT> ; for ( MachineBasicBlock :: iterator I = MBB . begin ( ) , E = MBB . end ( ) ; I != E ; ++ I ) { if ( ( I -> getOpcode ( ) != <STR_LIT> || I -> getOperand ( <NUM_LIT> ) . isImm ( ) ) && I -> getOpcode ( ) != <STR_LIT> ) { MBBStartOffset += TII -> GetInstSizeInBytes ( I ) ; continue ; } MachineBasicBlock * Dest = I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; int BranchSize ; if ( Dest -> getNumber ( ) <= MBB . getNumber ( ) ) { BranchSize = MBBStartOffset ; for ( unsigned i = Dest -> getNumber ( ) , e = MBB . getNumber ( )

; i != e ; ++ i ) BranchSize += BlockSizes [ i ] ;


<s> if ( TREE_CODE ( node ) == FIELD_DECL ) { const tree container = DECL_CONTEXT ( node ) ; dw_die_ref die = lookup_type_die ( container ) ; if ( die == NULL ) return - <NUM_LIT> ; ctf_dtdef_ref dtd = ctf_dtd_lookup ( ctfc , die ) ; if ( dtd == NULL ) return -


<s> break ; default : return false ; } if ( ! MI -> getOperand ( <NUM_LIT> ) . isReg ( ) ) return false ; MachineOperand & OffOp = MI -> getOperand ( <NUM_LIT> ) ; if ( ! OffOp . isImm ( ) ) return false ; int64_t Off = OffOp . getImm ( ) ; if ( ! isUIntN ( <NUM_LIT> + Align , Off ) || ( Off & ( ( <NUM_LIT> << Align ) - <NUM_LIT> ) ) ) return false ; BitTracker :: RegisterRef RS = MI -> getOperand ( <NUM_LIT> ) ; if ( ! BT . has ( RS . Reg ) ) return false ; const BitTracker :: RegisterCell & RC = BT . lookup ( RS . Reg ) ; uint64_t U ; if ( ! HBS :: getConst ( RC , <NUM_LIT> , RC . width ( ) , U ) ) return false ; int V ; switch ( Opc ) { case <STR_LIT> : V = int8_t ( U ) ; break ; case <STR_LIT> : V = int16_t ( U ) ; break ; case <STR_LIT> : V = int32_t ( U ) ; break ; } if ( ! isInt < <NUM_LIT> > ( V ) ) return false ; MI -> RemoveOperand ( <NUM_LIT> ) ; switch ( Opc ) { case <STR_LIT>


<s> for ( unsigned i = <NUM_LIT> ; i != Scale ; ++ i ) for ( unsigned j = <NUM_LIT> ; j != SrcNumElts ; ++ j