<s> default : llvm_unreachable ( <STR_LIT> ) ; case <NUM_LIT> : llvm_unreachable ( <STR_LIT> ) ; case <NUM_LIT> : llvm_unreachable ( <STR_LIT> ) ; case <NUM_LIT> : * ( data + <NUM_LIT> ) = uint8_t ( Value ) ; * ( data + <NUM_LIT> ) = uint8_t ( Value >> <NUM_LIT> ) ; * ( data + <NUM_LIT> ) = uint8_t ( Value >> <NUM_LIT> ) ; * ( data + <NUM_LIT> ) = uint8_t ( Value >> <NUM_LIT> ) ; break ; case <NUM_LIT> : * ( data + <NUM_LIT> ) = uint8_t


<s> __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) : ) ; return result


<s> if ( MI . getOpcode ( ) != TargetOpcode :: G_XOR ) return false ; auto ConstVal = getIConstantVRegSExtVal ( MI . getOperand ( <NUM_LIT> ) . getReg


<s> bool <ISA_LIT>DAGToDAGISel :: selectShiftMask ( SDValue N , unsigned ShiftWidth , SDValue & ShAmt ) { if ( N . getOpcode ( ) == <STR_LIT> && isa < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) ) ) { const APInt & AndMask = N -> getConstantOperandAPInt ( <NUM_LIT> ) ; assert ( isPowerOf2_32 ( ShiftWidth )


<s> if ( ! HARD_REGISTER_NUM_P ( regno ) ) { if ( ! strict_p ) return true ; if ( ! reg_renumber ) return false ; regno = reg_renumber [ regno ] ; } return ( GP_REGNUM_P ( regno ) || regno == SP_REGNUM || regno == FRAME_POINTER_REGNUM || regno ==


<s> } address = RTVEC_ELT ( XVEC ( unspec , <NUM_LIT> ) , <NUM_LIT> ) ; gcc_assert ( MEM_P ( address ) ) ; gcc_assert ( REG_P ( XEXP ( address , <NUM_LIT> ) ) ) ; address_regnum = REGNO ( XEXP ( address , <NUM_LIT> ) ) ; if ( address_regnum < R0_REGNUM + NUM_ARG_REGS ) bitmap_clear_bit ( to_clear_bitmap , address_regnum ) ; set_block_for_insn ( insn , bb ) ; df_set_flags ( DF_DEFER_INSN_RESCAN ) ; start_sequence ( ) ; emit_insn ( gen_blockage ( ) ) ; fntype = TREE_TYPE ( MEM_EXPR ( address ) ) ; arm_init_cumulative_args ( & args_so_far_v , fntype , NULL_RTX , NULL_TREE ) ; args_so_far = pack_cumulative_args ( & args_so_far_v ) ; FOREACH_FUNCTION_ARGS ( fntype , arg_type , args_iter ) { rtx arg_rtx ; uint64_t to_clear_args_mask ; machine_mode arg_mode = TYPE_MODE ( arg_type ) ; if ( VOID_TYPE_P ( arg_type ) ) continue ; if ( ! first_param ) arm_function_arg_advance ( args_so_far , arg_mode , arg_type , true ) ; arg_rtx = arm_function_arg ( args_so_far , arg_mode , arg_type , true ) ; gcc_assert ( REG_P ( arg_rtx ) ) ; to_clear_args_mask = compute_not_to_clear_mask ( arg_type , arg_rtx , REGNO ( arg_rtx ) , & padding_bits_to_clear [ <NUM_LIT> ] ) ; if ( to_clear_args_mask ) { for ( regno = R0_REGNUM ; regno <= maxregno ; regno ++ ) { if ( to_clear_args_mask & ( <NUM_LIT> << regno ) ) bitmap_clear_bit ( to_clear_bitmap , regno ) ; } } first_param = false ; } clearing_reg = XEXP ( address , <NUM_LIT> ) ; shift = gen_rtx_LSHIFTRT ( SImode , clearing_reg , const1_rtx ) ; emit_insn ( gen_rtx_SET ( clearing_reg , shift ) ) ; shift = gen_rtx_ASHIFT ( SImode , clearing_reg , const1_rtx ) ; emit_insn ( gen_rtx_SET ( clearing_reg , shift ) ) ; ip_reg = gen_rtx_REG ( SImode , IP_REGNUM ) ; cmse_clear_registers ( to_clear_bitmap , padding_bits_to_clear , NUM_ARG_REGS , ip_reg ,


<s> SDValue <ISA_LIT>TargetLowering :: LowerBSWAP ( SDValue Op , SelectionDAG & DAG ) const { SDLoc dl ( Op ) ; Op = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) , Op . getOperand


<s> LoopBB -> addSuccessor ( LoopBB ) ; unsigned ShiftAmtReg = RI . createVirtualRegister ( <STR_LIT> ) ; unsigned ShiftAmtReg2 = RI . createVirtualRegister ( <STR_LIT> ) ; unsigned ShiftReg = RI . createVirtualRegister ( RC ) ; unsigned ShiftReg2 = RI . createVirtualRegister ( RC ) ; unsigned ShiftAmtSrcReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned SrcReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned DstReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; BuildMI ( BB , dl , TII . get ( <STR_LIT> ) ) . addReg ( ShiftAmtSrcReg ) . addImm ( <NUM_LIT> ) ; BuildMI ( BB , dl , TII . get ( <STR_LIT> ) ) . addMBB ( RemBB ) . addImm ( <STR_LIT> ) ; BuildMI ( LoopBB , dl , TII . get ( <STR_LIT> ) , ShiftReg ) . addReg ( SrcReg ) . addMBB ( BB ) . addReg ( ShiftReg2 ) . addMBB ( LoopBB ) ; BuildMI ( LoopBB , dl , TII . get ( <STR_LIT> ) , ShiftAmtReg ) . addReg ( ShiftAmtSrcReg ) . addMBB ( BB ) . addReg ( ShiftAmtReg2 ) . addMBB ( LoopBB ) ; BuildMI ( LoopBB , dl , TII . get ( Opc ) , ShiftReg2 ) . addReg ( ShiftReg ) ; BuildMI ( LoopBB , dl , TII . get ( <STR_LIT> ) , ShiftAmtReg2 ) . addReg ( ShiftAmtReg ) . addImm ( <NUM_LIT> ) ; BuildMI ( LoopBB , dl , TII . get ( <STR_LIT> ) ) . addMBB ( LoopBB ) . addImm


<s> void rx_split_cbranch ( machine_mode cc_mode , enum rtx_code cmp1 , rtx c1 , rtx c2 , rtx label ) { rtx flags , x ; flags = gen_rtx_REG ( cc_mode , CC_REG ) ; x = gen_rtx_COMPARE ( cc_mode , c1 , c2 ) ; x = gen_rtx_SET ( flags , x ) ; emit_insn ( x ) ; x = gen_rtx_fmt_ee ( cmp1 , VOIDmode , flags , const0_rtx ) ; x = gen_rtx_IF_THEN_ELSE ( VOIDmode , x , label ,


<s> Chain = DAG . getCopyFromReg ( Chain , dl , VA . getLocReg ( ) , VA . getLocVT ( ) , InFlag ) . getValue ( <NUM_LIT> ) ; SDValue RetValue = Chain . getValue ( <NUM_LIT> ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; if ( VA . getLocInfo ( ) == CCValAssign :: SExt ) RetValue = DAG . getNode ( <STR_LIT> , dl , VA . getLocVT ( ) , RetValue , DAG . getValueType ( VA . getValVT ( ) ) ) ; else if ( VA . getLocInfo ( ) == CCValAssign :: ZExt ) RetValue = DAG . getNode ( <STR_LIT> , dl , VA . getLocVT ( ) , RetValue , DAG . getValueType ( VA . getValVT ( ) ) ) ; if ( VA . getLocInfo ( ) != CCValAssign :: Full ) RetValue = DAG . getNode ( <STR_LIT> , dl , VA . getValVT ( ) , RetValue ) ; InVals . push_back ( RetValue ) ; } return Chain


<s> bool hasSpills ( ) const { return HasSpills


<s> unsigned i = <NUM_LIT> ; for ( auto & Arg : F . args ( ) ) { if ( DL . getTypeStoreSize ( Arg . getType ( ) ) . isZero ( ) ) continue ; ArgInfo OrigArg { VRegs [ i ] , Arg } ; setArgFlags ( OrigArg , i + AttributeList :: FirstArgIndex , DL , F ) ; if ( Arg . hasAttribute ( Attribute :: SwiftAsync ) ) MF . getInfo < <ISA_LIT>FunctionInfo > ( ) -> setHasSwiftAsyncContext ( true ) ; splitToValueTypes ( OrigArg , SplitArgs , DL , F . getCallingConv ( ) ) ; ++ i ; } if ( ! MBB . empty ( ) ) MIRBuilder . setInstr ( * MBB . begin ( ) ) ; const <ISA_LIT>TargetLowering & TLI = * getTLI < <ISA_LIT>TargetLowering > ( ) ; CCAssignFn * AssignFn = TLI . CCAssignFnForCall ( F . getCallingConv ( ) , false ) ; <ISA_LIT>IncomingValueAssigner Assigner ( AssignFn , AssignFn ) ; FormalArgHandler Handler ( MIRBuilder , MRI ) ; if ( ! determineAndHandleAssignments ( Handler , Assigner , SplitArgs , MIRBuilder , F . getCallingConv

( ) , F . isVarArg ( ) ) ) return false ;


<s> SDVTList NodeTys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; DebugLoc dl = GA -> getDebugLoc ( ) ; SDValue TGA = DAG . getTargetGlobalAddress ( GA -> getGlobal ( ) , GA -> getValueType ( <NUM_LIT> ) , GA -> getOffset ( ) , OperandFlags ) ; if ( InFlag ) { SDValue Ops [ ] = { Chain , TGA , * InFlag } ; Chain = DAG . getNode ( <STR_LIT> , dl , NodeTys , Ops , <NUM_LIT> ) ; } else { SDValue Ops [ ] = { Chain


<s> SDValue <ISA_LIT>TargetLowering :: lowerATOMIC_STORE ( SDValue Op , SelectionDAG & DAG ) const { auto * Node = cast < AtomicSDNode > ( Op . getNode ( ) ) ; SDValue Chain = DAG . getTruncStore ( Node -> getChain ( ) , SDLoc ( Op ) , Node -> getVal ( ) , Node -> getBasePtr ( ) , Node -> getMemoryVT ( ) , Node -> getMemOperand ( ) ) ; if ( Node -> getOrdering ( ) == AtomicOrdering :: SequentiallyConsistent ) Chain = SDValue ( DAG . getMachineNode ( <STR_LIT> , SDLoc

( Op ) , <STR_LIT> , Chain ) , <NUM_LIT> ) ;


<s> inline bool <ISA_LIT>DAGToDAGISel :: foldGlobalAddressGP ( SDValue &


<s> ++ NumRestores ; -- LastPopI ; } while ( LastPopI != MBB . begin ( ) && isCSRestore ( LastPopI , CSRegs ) ) ; if ( ! isCSRestore ( LastPopI , CSRegs ) ) { ++ LastPopI ; -- NumRestores ; } } NumBytes -= NumRestores * <NUM_LIT> ; assert ( NumBytes >= <NUM_LIT> && <STR_LIT> ) ; if ( ! hasFP ( MF ) ) { if ( ! canUseRedZone ( MF ) ) emitFrameOffset ( MBB , LastPopI , DL , <STR_LIT> , <STR_LIT> , NumBytes , TII ) ; return ; } if ( NumBytes || MFI -> hasVarSizedObjects ( ) ) emitFrameOffset ( MBB , LastPopI , DL , <STR_LIT> , <STR_LIT> , - ( NumRestores - <NUM_LIT> ) * <NUM_LIT> ,


<s> Inst . addOperand ( MCOperand :: createImm


<s> bool areInlineCompatible ( const Function * Caller , const Function * Callee ) const { return


<s> static void riscv_unique_section ( tree decl , int reloc ) { const char * prefix = NULL ; bool one_only = DECL_ONE_ONLY ( decl ) && ! HAVE_COMDAT_GROUP ; switch ( categorize_decl_for_section ( decl , reloc ) ) { case SECCAT_SRODATA : prefix = one_only ? <STR_LIT> :


<s> <STR_LIT> CC = cast < CondCodeSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> get ( ) ; DebugLoc dl = Op . getDebugLoc ( ) ; switch ( CC ) { default : break ; case <STR_LIT> : CC = <STR_LIT> ; RHS = DAG . getSelectCC ( dl , LHS , LHS , RHS , LHS , CC ) ; break ; case <STR_LIT> : CC = <STR_LIT> ; RHS = DAG . getSelectCC ( dl , LHS , LHS , LHS , RHS , CC ) ; break ; } if ( NegateFCC ( LHS , RHS , CC ) ) std :: swap ( TrueV , FalseV ) ; SDValue TargetCC = DAG . getConstant ( CC , <STR_LIT> ) ; SDValue Flag = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , LHS , RHS , TargetCC ) ; SDVTList VTs = DAG . getVTList ( Op


<s> switch ( Op . getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; return SDValue ( ) ; case <STR_LIT> : return LowerFrameIndex ( Op , DAG ) ; case <STR_LIT> : return LowerGlobalAddress ( Op , DAG ) ; case <STR_LIT> : return LowerExternalSymbol ( Op , DAG ) ; case <STR_LIT> : return LowerJumpTable ( Op , DAG ) ; case <STR_LIT> : return LowerBR_JT ( Op , DAG ) ; case <STR_LIT> : return LowerVASTART ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : fail ( DL , DAG , <STR_LIT> ) ; return SDValue ( ) ; case <STR_LIT> : return LowerRETURNADDR ( Op , DAG ) ; case <STR_LIT> : return LowerFRAMEADDR ( Op , DAG ) ; case <STR_LIT> : return LowerCopyToReg ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerAccessVectorElement ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerIntrinsic ( Op , DAG ) ; case <STR_LIT> : return LowerSIGN_EXTEND_INREG ( Op , DAG ) ; case <STR_LIT> : return LowerBUILD_VECTOR ( Op , DAG ) ; case <STR_LIT>


<s> poly_int64 size = - <NUM_LIT> ; if ( type && TREE_CODE ( type ) == VECTOR_TYPE ) size = int_size_in_bytes ( type ) ; else if ( GET_MODE_CLASS ( mode ) == MODE_VECTOR_INT || GET_MODE_CLASS ( mode

) == MODE_VECTOR_FLOAT ) size = GET_MODE_SIZE ( mode ) ;


<s> __asm__ ( <STR_LIT> : <STR_LIT> ( d ) : <STR_LIT> ( a ) ) ; return d


<s> return hasSMEMByteOffset ( ST ) ? isUInt < <NUM_LIT> > ( EncodedOffset ) : isUInt


<s> if ( Size == <NUM_LIT> ) Size = <NUM_LIT> ; if ( GVar -> hasLocalLinkage ( ) ) O << <STR_LIT> << name << '\n' ; O << TAI -> getCOMMDirective ( ) << name << ',' << Size ; if ( TAI -> getCOMMDirectiveTakesAlignment ( ) ) O << ',' << ( <NUM_LIT> << Align ) ; O << '\n' ; return ; } } switch ( GVar -> getLinkage ( ) ) { case GlobalValue :: CommonLinkage : case GlobalValue :: LinkOnceAnyLinkage : case GlobalValue :: LinkOnceODRLinkage : case GlobalValue :: WeakAnyLinkage : case GlobalValue :: WeakODRLinkage : O << <STR_LIT> << name << '\n' ; break ; case GlobalValue :: AppendingLinkage : case GlobalValue :: ExternalLinkage : O << TAI -> getGlobalDirective ( ) << name << '\n' ; case GlobalValue :: PrivateLinkage : case GlobalValue :: InternalLinkage : break ; case GlobalValue :: GhostLinkage : cerr << <STR_LIT> ; abort ( ) ; case GlobalValue :: DLLImportLinkage : cerr << <STR_LIT> ; abort ( ) ; case GlobalValue :: DLLExportLinkage : cerr << <STR_LIT> ; abort ( ) ; default : assert ( <NUM_LIT> && <STR_LIT> ) ; } EmitAlignment ( Align , GVar ) ; if ( TAI -> hasDotTypeDotSizeDirective ( ) ) { O << <STR_LIT> << name << <STR_LIT> ; O << <STR_LIT> << name << ',' << Size << '\n' ; } O << name <<


<s> void <ISA_LIT>InstPrinter :: printMemoryPostIndexed32 ( const MCInst * MI , unsigned OpNum , raw_ostream & O ) { O << '[' << getRegisterName ( MI -> getOperand ( OpNum ) . getReg ( ) ) <<

']' << <STR_LIT> << <NUM_LIT> * MI -> getOperand ( OpNum + <NUM_LIT> ) . getImm ( ) ;


<s> if ( Register :: isPhysicalRegister ( SubReg . getReg ( ) ) ) return TRI . isSubRegister ( SuperVec . getReg ( ) , SubReg . getReg ( ) ) ; return SubReg . getSubReg ( ) != <STR_LIT> && SubReg . getReg ( ) == SuperVec


<s> virtual const TargetData * getTargetData ( ) const { return &


<s> bool <ISA_LIT>FrameLowering :: hasReservedCallFrame ( const MachineFunction & MF ) const { return ! MF . getFrameInfo (


<s> bool <ISA_LIT>FrameLowering :: enableShrinkWrapping ( const MachineFunction & MF ) const { if ( STI . hasV8_1MMainlineOps ( ) && MF . getInfo < <ISA_LIT>FunctionInfo >

( ) -> isCmseNSEntryFunction ( ) ) return false ;


<s> assert ( ! Features [ <STR_LIT> ] || ! Features [ <STR_LIT> ] ) ; M . addModuleFlag ( Module :: ModFlagBehavior :: Error , MDKey , <STR_LIT> ) ; } else if ( Features [ KV . Value ] ) { M . addModuleFlag ( Module :: ModFlagBehavior :: Error , MDKey ,


<s> return parseRegister ( Operands , RegGR


<s> return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getConstant ( Cond , dl , <STR_LIT> )


<s> if ( ! MI -> mayLoad ( ) && ! MI -> mayStore ( ) ) return false ; MachineFunction & MF = * MI -> getParent ( ) -> getParent ( ) ; const <ISA_LIT>FrameLowering * TFI = getFrameLowering ( MF ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; int64_t FPOffset = Offset - <NUM_LIT> * <NUM_LIT> ; Offset += MFI .


<s> for ( unsigned i = <NUM_LIT> , e = InitList -> getNumOperands ( ) ; i != e ; ++ i ) if ( const Function * F =

dyn_cast < Function > ( InitList -> getOperand ( i ) -> stripPointerCasts ( ) ) ) Result . insert ( F -> getName ( ) ) ;


<s> return ( uint64x2_t ) __builtin_neon_vrshru_nv2di ( ( int64x2_t )


<s> MVT SadVT = SAD . getSimpleValueType ( ) ; if ( Stages > <NUM_LIT> ) { unsigned SadElems = SadVT . getVectorNumElements ( ) ; for ( unsigned i = Stages - <NUM_LIT> ; i > <NUM_LIT> ; -- i ) { SmallVector < int , <NUM_LIT> > Mask ( SadElems , - <NUM_LIT> ) ; for ( unsigned j = <NUM_LIT> , MaskEnd = <NUM_LIT> << ( i - <NUM_LIT> ) ; j < MaskEnd ; ++ j ) Mask [ j ] = MaskEnd + j ; SDValue Shuffle = DAG . getVectorShuffle ( SadVT , DL , SAD , DAG . getUNDEF ( SadVT ) , Mask ) ; SAD = DAG . getNode ( <STR_LIT> , DL , SadVT , SAD , Shuffle ) ; } } MVT Type = Extract -> getSimpleValueType ( <NUM_LIT> ) ; unsigned TypeSizeInBits = Type . getSizeInBits (


<s> return c4x_arn_mem_operand ( op , mode , AR2_REGNO


<s> case <STR_LIT> : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : llvm_unreachable ( <STR_LIT> ) ; default : break ; } StringRef RegName ( getRegisterName ( RegNo ) ) ; if ( ! Keep16BitSuffixes ) if ( ! RegName . consume_back ( <STR_LIT> ) ) RegName . consume_back


<s> bool <ISA_LIT>AsmPrinter :: PrintAsmMemoryOperand ( const MachineInstr * MI , unsigned OpNum , unsigned AsmVariant , const char * ExtraCode , raw_ostream & O ) { if ( ExtraCode && ExtraCode [ <NUM_LIT> ] ) return true ; const MachineOperand & MO = MI -> getOperand ( OpNum ) ; assert ( MO . isReg ( ) && <STR_LIT> ) ; O << <STR_LIT> << <ISA_LIT>InstPrinter :: getRegisterName ( MO . getReg ( ) ) << <STR_LIT> ; return false


<s> if ( s390_function_arg_vector ( mode ,


<s> return decodeRegisterClass ( Inst , RegNo , XRegs


<s> unsigned long count = <NUM_LIT> ; while ( value ) { count


<s> fail ( DL , DAG , <STR_LIT> ) ; return SDValue ( ) ; case <STR_LIT> : return LowerRETURNADDR ( Op , DAG ) ; case <STR_LIT> : return LowerFRAMEADDR ( Op , DAG ) ; case <STR_LIT> : return LowerCopyToReg ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerAccessVectorElement ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerIntrinsic ( Op , DAG ) ; case <STR_LIT> : return LowerSIGN_EXTEND_INREG ( Op , DAG ) ; case <STR_LIT> : return LowerBUILD_VECTOR ( Op , DAG ) ; case <STR_LIT> : return LowerVECTOR_SHUFFLE ( Op , DAG ) ; case <STR_LIT> : return LowerSETCC ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerShift ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerFP_TO_INT_SAT ( Op , DAG ) ; case <STR_LIT> : return LowerLoad ( Op , DAG ) ; case <STR_LIT> : return LowerStore ( Op , DAG ) ; case <STR_LIT>


<s> static DecodeStatus DecodeFPR128_loRegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t Addr , const MCDisassembler


<s> if ( count == <NUM_LIT> ) goto out_fail ; if ( ! get_unit_operand_masks ( chain -> insn , & mask1 , & mask2 ) ) goto out_fail ; extract_insn ( chain -> insn ) ; mask_changed = <NUM_LIT> ; for ( i = <NUM_LIT> ; i < recog_data . n_operands ; i ++ ) { int j ; int n_this_op = this_rr -> op_info [ i ] . n_chains ; for ( j = <NUM_LIT> ; j < n_this_op ; j ++ ) { du_head_p other = this_rr -> op_info [ i ] . heads [ j ] ; if ( regrename_chain_from_id ( other -> id ) == this_head ) break ; } if ( j == n_this_op ) continue ; if ( n_this_op != <NUM_LIT> ) goto out_fail ; mask_changed |= <NUM_LIT> << i ; } gcc_assert ( mask_changed != <NUM_LIT> ) ; if ( mask_changed != mask1 && mask_changed != mask2 ) goto out_fail ; } COMPL_HARD_REG_SET ( unavailable , reg_class_contents [ ( int ) super_class ] ) ; old_reg = this_head -> regno ; best_reg = find_rename_reg ( this_head , super_class , & unavailable , old_reg , true ) ; regrename_do_replace ( this_head , best_reg ) ; count_unit_reqs ( new_reqs , head , PREV_INSN ( tail ) ) ; merge_unit_reqs ( new_reqs ) ; if ( dump_file ) { fprintf ( dump_file , <STR_LIT> <STR_LIT> , INSN_UID ( insn ) , op_mask , orig_side , best_reg ) ; fprintf ( dump_file , <STR_LIT> , unit_req_imbalance ( reqs ) , unit_req_imbalance ( new_reqs ) ) ; } if ( unit_req_imbalance ( new_reqs ) > unit_req_imbalance ( reqs ) ) regrename_do_replace (


<s> void <ISA_LIT>InstPrinter :: printMemOperand ( const MCInst * MI , int OpNum , raw_ostream & O ) { printOperand ( MI , OpNum + <NUM_LIT> , O ) ; O << <STR_LIT> ; printOperand ( MI , OpNum , O ) ; O << <STR_LIT>


<s> void <ISA_LIT>InstrInfo :: legalizeGenericOperand ( MachineBasicBlock & InsertMBB , MachineBasicBlock :: iterator I , const TargetRegisterClass * DstRC , MachineOperand & Op , MachineRegisterInfo & MRI , const DebugLoc & DL ) const { unsigned OpReg = Op . getReg ( ) ; unsigned OpSubReg = Op . getSubReg ( ) ; const TargetRegisterClass * OpRC = RI . getSubClassWithSubReg ( RI . getRegClassForReg ( MRI , OpReg ) , OpSubReg ) ; if ( DstRC == OpRC ) return ; unsigned DstReg = MRI . createVirtualRegister ( DstRC ) ; MachineInstr * Copy = BuildMI ( InsertMBB , I , DL , get ( <STR_LIT> ) , DstReg ) . addOperand ( Op ) ; Op . setReg ( DstReg ) ; Op . setSubReg ( <NUM_LIT> ) ; MachineInstr * Def = MRI . getVRegDef ( OpReg ) ; if ( ! Def ) return ; if ( Def -> isMoveImmediate ( ) ) FoldImmediate ( * Copy ,


<s> bool isInSCC ( ) const { return IsInSCC


<s> for ( MachineBasicBlock :: const_succ_iterator si = MBB -> succ_begin ( ) , se = MBB -> succ_end ( ) ; si != se ; ++ si ) { if ( ! visited . count ( * si ) ) { dfs ( * si ) ; } else if ( ! finished . count ( * si ) ) { if ( ! DT . dominates ( * si ,


<s> llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : return MI . getOperand ( <NUM_LIT> ) . getMBB ( ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return MI . getOperand ( <NUM_LIT> ) . getMBB ( ) ; case <STR_LIT> : case


<s> <ISA_LIT>Operand * op = static_cast < <ISA_LIT>Operand * > ( & * Operands [ i ] ) ; assert ( op != nullptr


<s> bool isLegalMaskedScatter ( Type * Ty , MaybeAlign Alignment ) { return false


<s> switch ( Mode ) { default : assert ( <NUM_LIT> && <STR_LIT> ) ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT>


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return


<s> if ( is_ha != NULL ) * is_ha = true ; * count = <NUM_LIT> ; new_mode = GET_MODE_INNER ( mode ) ; } else if ( type && composite_p ) { int ag_count = aapcs_vfp_sub_candidate ( type , & new_mode ) ; if ( ag_count > <NUM_LIT> && ag_count <= HA_MAX_NUM_FLDS ) { if ( is_ha != NULL ) * is_ha = true ; * count = ag_count ; } else return false


<s> static const uint16_t HiRegList [ ] = { <STR_LIT> , <STR_LIT> } ; static const uint16_t LoRegList [ ] = { <STR_LIT> , <STR_LIT> } ; static const uint16_t ShadowRegList [ ] = { <STR_LIT> , <STR_LIT> } ; static const uint16_t GPRArgRegs [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; unsigned Reg = State . AllocateReg ( HiRegList , ShadowRegList , <NUM_LIT> ) ; if ( Reg == <NUM_LIT> ) { Reg = State . AllocateReg ( GPRArgRegs , <NUM_LIT> ) ; assert ( ( ! Reg || Reg == <STR_LIT> ) && <STR_LIT> ) ; if ( CanFail ) return false ; State . addLoc ( CCValAssign :: getCustomMem ( ValNo , ValVT , State . AllocateStack ( <NUM_LIT> , <NUM_LIT> ) , LocVT , LocInfo ) ) ; return true ; } unsigned


<s> Chain = DAG . getNode ( <STR_LIT> , dl , NodeTys , Chain , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; Chain = DAG . getCopyFromReg ( Chain , dl , <ISA_LIT>StackPtr , SPTy ) . getValue ( <NUM_LIT> ) ; SDValue Ops1 [ <NUM_LIT> ] = { Chain . getValue ( <NUM_LIT> ) , Chain } ; return DAG . getMergeValues ( Ops1 ,


<s> return ( __m64 ) __builtin_arm_wsubaddhx ( ( __v4hi ) a


<s> void addImm1_64Operands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT>


<s> static SDValue LowerVASTART ( SDValue Op , SelectionDAG & DAG ) { MachineFunction & MF = DAG . getMachineFunction ( ) ; <ISA_LIT>FunctionInfo * FuncInfo = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; SDLoc dl ( Op ) ; EVT PtrVT = DAG . getTargetLoweringInfo ( ) . getPointerTy ( DAG . getDataLayout ( ) ) ; SDValue FR = DAG . getFrameIndex ( FuncInfo -> getVarArgsFrameIndex ( ) , PtrVT ) ; const Value * SV = cast < SrcValueSDNode > ( Op . getOperand ( <NUM_LIT> ) ) ->


<s> for ( int i = info -> first_fp_reg_save ; i < <NUM_LIT> ; i ++ ) { if ( bitmap_bit_p ( components , i ) ) { rtx reg = gen_rtx_REG ( fp_reg_mode , i ) ; rtx_insn * insn = emit_insn ( gen_frame_load ( reg , ptr_reg , offset ) ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; add_reg_note ( insn , REG_CFA_RESTORE , reg ) ; } offset += fp_reg_size ; } offset = info -> gp_save_offset ; if ( info -> push_p ) offset += info -> total_size ; for ( int i = info -> first_gp_reg_save ; i < <NUM_LIT> ; i ++ ) { if ( bitmap_bit_p ( components , i ) ) { rtx reg = gen_rtx_REG ( reg_mode , i ) ; rtx_insn * insn = emit_insn ( gen_frame_load ( reg , ptr_reg , offset ) ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; add_reg_note ( insn , REG_CFA_RESTORE ,


<s> assert ( MF . getName ( ) . startswith ( getThunkPrefix ( ) ) ) ; auto ThunkIt = llvm :: find_if ( SLSBLRThunks , [ & MF ] ( auto T ) { return T . Name == MF . getName ( ) ; } ) ; assert ( ThunkIt != std :: end ( SLSBLRThunks ) ) ; Register ThunkReg = ThunkIt -> Reg ; const TargetInstrInfo * TII = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getInstrInfo ( ) ; assert ( MF . size ( ) == <NUM_LIT> ) ; MachineBasicBlock * Entry = & MF . front ( ) ; Entry -> clear ( ) ; Entry -> addLiveIn ( ThunkReg ) ; BuildMI ( Entry , DebugLoc ( ) , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( ThunkReg


<s> case Instruction :: SDiv : case Instruction :: URem : case Instruction :: SRem : return Operand == <NUM_LIT> ; case Instruction :: Call : if ( auto * II = dyn_cast < IntrinsicInst > ( I ) ) { switch ( II -> getIntrinsicID ( ) ) { case <STR_LIT> : return Operand == <NUM_LIT> || Operand == <NUM_LIT> ; default : return false ; } } return false ; default : return false ; } } ; for ( auto OpIdx : enumerate ( I -> operands ( ) ) ) { if ( ! IsSinker ( I , OpIdx . index ( ) ) ) continue ; Instruction * Op = dyn_cast < Instruction > ( OpIdx . value ( ) . get ( ) ) ; if ( ! Op || any_of ( Ops , [ & ] ( Use * U ) { return U ->


<s> static DecodeStatus DecodeLogicalImmOperand ( llvm :: MCInst & Inst , unsigned Bits , uint64_t Address , const void * Decoder ) { uint64_t


<s> return ( __m128i ) __builtin_ia32_pmovsqw256_mask ( ( __v4di ) __A , ( __v8hi ) _mm_undefined_si128 ( ) , ( __mmask8 )


<s> OutStreamer . EmitRawText ( StringRef ( <STR_LIT> ) ) ; OutStreamer . EmitRawText ( <STR_LIT> + Twine ( CurrentFnSym -> getName ( )


<s> bool <ISA_LIT>SETargetLowering :: allowsUnalignedMemoryAccesses ( EVT VT , unsigned , bool * Fast ) const { <STR_LIT> SVT = VT . getSimpleVT ( ) . SimpleTy ; switch ( SVT ) { case <STR_LIT>


<s> NewInst . setOpcode ( MCI . getOpcode ( ) ) ; for ( MCOperand & I : MCI ) if ( I . isImm ( ) ) { int64_t Value ( I . getImm ( ) ) ; NewInst . addOperand ( MCOperand :: createExpr ( <ISA_LIT>MCExpr :: create ( MCConstantExpr :: create ( Value , getContext ( ) ) , getContext ( ) ) ) ) ; } else { if ( I . isExpr ( ) && cast < <ISA_LIT>MCExpr > ( I . getExpr ( ) ) -> signMismatch ( ) && WarnSignedMismatch ) Warning ( MCI . getLoc ( )


<s> <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } ; const <ISA_LIT>FrameLowering * TFI = getFrameLowering ( * MF ) ; if ( TFI -> hasFP ( * MF ) ) return CalleeSavedRegsFP ; return


<s> bool <ISA_LIT>TargetLowering :: isExternrefType ( const Type *


<s> for ( auto * User : I . users ( ) ) ProcessUser ( MemOpOffsetMap , * User , Offset , false ) ; ProcessMemOpWRTCompositeSource ( SrcMem , MemOpOffsetMap , DestTy ,


<s> if ( Vec . getValueType ( ) != VT ) return SDValue ( ) ; SDValue Idx = SplatVal . getOperand ( <NUM_LIT> ) ; if ( Idx . getValueType ( ) != Subtarget . getXLenVT ( ) ) return SDValue ( ) ; MVT ContainerVT = VT ; if ( VT . isFixedLengthVector ( ) ) { ContainerVT = getContainerForFixedLengthVector ( DAG , VT , Subtarget


<s> static bool isCCallConvention ( CallingConv :: ID CC


<s> case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : O << <STR_LIT> ; return ; } } SYSm &= <NUM_LIT> ; if ( Opcode == <STR_LIT> && FeatureBits [ <STR_LIT> ] ) { switch ( SYSm ) { case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : O << <STR_LIT> ; return ; } } switch ( SYSm ) { default : llvm_unreachable ( <STR_LIT> ) ; case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : O << <STR_LIT>


<s> if ( double_p ) { unsigned int base_reg ; if ( GET_CODE ( memrtx ) == PLUS ) base_reg = REGNO ( XEXP ( memrtx , <NUM_LIT> ) ) ; else base_reg = REGNO ( memrtx ) ; if ( dest_reg != base_reg ) dest_reg ++ ; } } else if ( GET_CODE ( dest ) == MEM ) memrtx = XEXP ( dest , <NUM_LIT> ) ; else if ( GET_MODE_CLASS ( GET_MODE ( dest ) ) != MODE_CC ) { if ( GET_CODE ( dest ) == STRICT_LOW_PART || GET_CODE ( dest ) == ZERO_EXTRACT ) dest = XEXP ( dest , <NUM_LIT> ) ; dest_reg = REGNO ( dest ) ; if ( GET_CODE ( SET_SRC ( set ) ) == REG ) { unsigned int srcreg = REGNO ( SET_SRC ( set ) ) ; if ( srcreg == dest_reg ) return ; if ( double_p && dest_reg != srcreg + <NUM_LIT> ) dest_reg ++ ; } } if ( * last_insn_call ) dest_reg = <NUM_LIT> ; if ( * last_reg != <NUM_LIT> && memrtx != NULL_RTX ) { unsigned int reg = <NUM_LIT> ; if ( GET_CODE ( memrtx ) == PLUS ) reg = REGNO ( XEXP ( memrtx , <NUM_LIT> ) ) ; else if ( TARGET_MCM || ( double_p && REGNO ( memrtx ) == dest_reg ) ) reg = REGNO ( memrtx ) ; if ( reg == * last_reg ) { if ( dump_file ) fprintf ( dump_file , <STR_LIT> , INSN_UID ( insn ) ) ; emit_insn_after ( gen_hazard_nop ( ) , prev_active_insn ( insn ) ) ; emit_insn_after ( gen_blockage ( ) , insn ) ; } } * last_reg


<s> PM . add ( createAMDGPUTargetTransformInfoPass ( this )


<s> cum -> words = GET_MODE_SIZE ( mode ) ; } else { cum -> words += GET_MODE_SIZE ( mode ) ; if ( cum -> words <= HARD_REG_SIZE )


<s> void <ISA_LIT>ATTInstPrinter :: printInst ( const MCInst * MI , raw_ostream & OS ) { printInstruction ( MI , OS ) ; if ( CommentStream ) EmitAny<ISA_LIT>InstComments ( MI ,


<s> assert ( ! Orig . isImplicit ( ) ) ; return MachineOperand :: CreateReg ( Orig . getReg ( ) , Orig . isDef ( ) , true , Orig . isKill ( ) , Orig . isDead ( ) , Orig . isUndef ( ) , Orig . isEarlyClobber ( ) , Orig . getSubReg ( ) , Orig .

isDebug ( ) , Orig . isInternalRead ( ) ) ;


<s> unsigned NumElts = VT . getVectorNumElements ( ) ; if ( M . size ( ) != NumElts && M . size ( ) != NumElts * <NUM_LIT> ) return false ; for ( unsigned i = <NUM_LIT> ; i < M . size ( ) ; i += NumElts ) { if ( M . size ( ) == NumElts * <NUM_LIT>


<s> bool <ISA_LIT>RegisterInfo :: isVGPR ( const MachineRegisterInfo &


<s> if ( ! MI ) return false ; const uint64_t F = get ( MI -> getOpcode ( ) ) . TSFlags ; const uint64_t V = ( ( F


<s> if ( ! canWidenShuffleElements ( Mask , WidenedMask ) ) return SDValue ( ) ; if ( SDValue Blend = lowerVectorShuffleAsBlend ( DL , VT , V1 , V2 , Mask , Zeroable , Subtarget , DAG ) ) return Blend ; bool IsV1Zero = <STR_LIT> ( V1 . getNode ( ) ) ; bool IsV2Zero = <STR_LIT> ( V2 . getNode ( ) ) ; if ( ! IsV1Zero && ! IsV2Zero ) { bool OnlyUsesV1 = isShuffleEquivalent ( V1 , V2 , Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ; if ( OnlyUsesV1 || isShuffleEquivalent ( V1 , V2 , Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) { if ( Subtarget . hasAVX2 ( ) && V2 . isUndef ( ) ) return


<s> Value <<= Info . TargetOffset ; unsigned Offset = Fixup . getOffset ( ) ; assert ( Offset + NumBytes <= Data . size ( ) && <STR_LIT> ) ; for ( unsigned I = <NUM_LIT> ; I != NumBytes ; ++ I ) Data [ Offset + I

] |= uint8_t ( ( Value >> ( I * <NUM_LIT> ) ) & <NUM_LIT> ) ;


<s> YamlIO . mapOptional ( <STR_LIT> , MFI . WaveLimiter , false ) ; YamlIO . mapOptional ( <STR_LIT> , MFI . ScratchRSrcReg , StringValue ( <STR_LIT> ) ) ; YamlIO . mapOptional ( <STR_LIT> , MFI . ScratchWaveOffsetReg , StringValue ( <STR_LIT> ) ) ; YamlIO . mapOptional ( <STR_LIT> , MFI . FrameOffsetReg , StringValue ( <STR_LIT> ) ) ; YamlIO . mapOptional ( <STR_LIT> , MFI .

StackPtrOffsetReg , StringValue ( <STR_LIT> ) ) ;


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : return <STR_LIT>


<s> bool runOnMachineFunction ( MachineFunction & MF ) override { initialize ( MF ) ; assert ( ( MF . getRegInfo ( ) . use_empty ( <STR_LIT> ) || ! MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . isUsingPCRelativeCalls ( ) ) && <STR_LIT> ) ; if ( skipFunction ( MF . getFunction ( )


<s> TargetPassConfig * <ISA_LIT>TargetMachine :: createPassConfig ( PassManagerBase & PM ) { return new <ISA_LIT>PassConfig ( *


<s> SDValue BitShift = DAG . getNode ( <STR_LIT> , DL , PtrVT , Addr , DAG . getConstant ( <NUM_LIT> , DL , PtrVT ) ) ; BitShift = DAG . getNode ( <STR_LIT> , DL , WideVT , BitShift ) ; SDValue NegBitShift = DAG . getNode ( <STR_LIT> , DL , WideVT , DAG . getConstant ( <NUM_LIT> , DL , WideVT ) , BitShift ) ; SDVTList VTList = DAG . getVTList ( WideVT , <STR_LIT> ) ; SDValue Ops [ ] = { ChainIn , AlignedAddr , CmpVal , SwapVal , BitShift , NegBitShift , DAG . getConstant ( BitSize , DL , WideVT ) } ; SDValue AtomicOp = DAG . getMemIntrinsicNode ( <STR_LIT> , DL , VTList , Ops , NarrowVT ,


<s> void printAMIndexedWB ( const MCInst * MI , unsigned OpNum , raw_ostream & O ) { printAMIndexedWB ( MI , OpNum , BitWidth /


<s> unsigned Kind = Fixup . getKind ( ) ; switch ( Modifier ) { case MCSymbolRefExpr :: VK_None : if ( IsPCRel ) return getPCRelReloc ( Kind ) ; return getAbsoluteReloc ( Kind ) ; case MCSymbolRefExpr :: VK_NTPOFF : assert ( ! IsPCRel && <STR_LIT> ) ; return getTLSLEReloc ( Kind ) ; case MCSymbolRefExpr :: VK_GOT : llvm_unreachable ( <STR_LIT> )


<s> MCSection * <ISA_LIT>MCAsmInfo :: getNonexecutableStackSection ( MCContext & Ctx ) const { return


<s> MCFragment * findAssociatedFragment (


<s> auto MIOpIdx = <STR_LIT> ( MI . getOpcode ( ) , Op ) ; bool IsPCRel = Desc . OpInfo [ MIOpIdx ] . OperandType == MCOI :: OPERAND_PCREL ; MCOperand MCO ; if ( <STR_LIT> ( MI . getOpcode ( ) , Op ) ) { if ( IsPCRel ) { assert ( Alt && <STR_LIT> ) ; MCO = MI . getOperand ( MIOpIdx + <STR_LIT> ) ; } else { MCO = MI . getOperand ( MIOpIdx + ( Alt ? <STR_LIT> : <STR_LIT> ) ) ; } } else { assert ( ! Alt && <STR_LIT> ) ; MCO = MI . getOperand ( MIOpIdx ) ; } unsigned RegNum = MCO . getReg ( ) ; auto RI = Ctx . getRegisterInfo ( ) ; unsigned Written = <NUM_LIT> ; if ( Reg ) { uint32_t Val = RI -> getEncodingValue ( RegNum ) ; Buffer |= ( Val & <NUM_LIT> ) << Offset ; Offset += <NUM_LIT> ; Written += <NUM_LIT> ; } if ( DA


<s> auto & MRI = MF . getRegInfo ( ) ; unsigned SPReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; auto * SPSymbol = MF . createExternalSymbolName ( <STR_LIT> ) ; BuildMI ( MBB , InsertPt , DL , TII -> get ( <STR_LIT> ) , SPReg ) . addExternalSymbol ( SPSymbol ) ; auto * LoadMMO = new MachineMemOperand ( MachinePointerInfo ( ) , MachineMemOperand :: MOLoad , <NUM_LIT> , <NUM_LIT> ) ; BuildMI ( MBB , InsertPt , DL , TII -> get ( <STR_LIT> ) , SPReg ) . addImm ( <NUM_LIT> ) . addReg ( SPReg ) . addMemOperand ( LoadMMO ) ; unsigned OffsetReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( MBB , InsertPt , DL , TII -> get ( <STR_LIT> ) , OffsetReg ) . addImm ( StackSize ) ; BuildMI ( MBB , InsertPt , DL , TII -> get ( AdjustUp ? <STR_LIT> : <STR_LIT> ) , <STR_LIT> ) . addReg ( SPReg ) . addReg ( OffsetReg ) ; BuildMI ( MBB , InsertPt , DL , TII -> get ( <STR_LIT> ) , OffsetReg ) . addExternalSymbol ( SPSymbol ) ; auto * MMO = new MachineMemOperand ( MachinePointerInfo ( ) , MachineMemOperand :: MOStore , <NUM_LIT> , <NUM_LIT> ) ; BuildMI ( MBB , InsertPt , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addImm

( <NUM_LIT> ) . addReg ( OffsetReg ) . addReg ( <STR_LIT> ) . addMemOperand ( MMO ) ;


<s> bool <ISA_LIT>DAGToDAGISel :: SelectPCLIP ( SDValue Dest , SDValue & SRC1 , SDValue & SRC2 ) { return RI5CY_pclip_check ( CurDAG , Dest , SRC1


<s> void MachineConstPropagator :: visitUsesOf ( unsigned Reg ) { DEBUG ( dbgs ( ) << <STR_LIT> << printReg ( Reg , & MCE . TRI ) << Cells . get ( Reg ) << '\n' ) ; for ( MachineInstr & MI : MRI -> use_nodbg_instructions ( Reg ) ) { if ( ! InstrExec . count ( & MI ) ) continue ; if ( MI . isPHI ( ) ) visitPHI ( MI ) ; else if ( ! MI . isBranch ( ) )


<s> if ( LastOpcodeHasJMP_c ) { TBB = LastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; if ( LastOpcodeHasNot ) { Cond . push_back ( MachineOperand :: CreateImm ( <NUM_LIT> ) ) ; } Cond . push_back ( LastInst -> getOperand ( <NUM_LIT> ) ) ; return false ; } return true ; } int SecLastOpcode = SecondLastInst -> getOpcode ( ) ; bool SecLastOpcodeHasJMP_c = PredOpcodeHasJMP_c ( SecLastOpcode ) ; bool SecLastOpcodeHasNot = PredOpcodeHasNot ( SecLastOpcode ) ; if ( SecLastOpcodeHasJMP_c && ( LastOpcode == <STR_LIT> ) ) { TBB = SecondLastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; if ( SecLastOpcodeHasNot ) Cond . push_back ( MachineOperand :: CreateImm ( <NUM_LIT> ) ) ; Cond . push_back ( SecondLastInst -> getOperand ( <NUM_LIT> ) ) ; FBB = LastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; return false ; } if ( SecLastOpcode == <STR_LIT> && LastOpcode == <STR_LIT> ) { TBB = SecondLastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; I = LastInst ; if ( AllowModify ) I -> eraseFromParent ( ) ; return false ; } if ( SecLastOpcode == <STR_LIT> && LastOpcode == <STR_LIT> ) { TBB = SecondLastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; Cond . push_back ( SecondLastInst -> getOperand


<s> <ISA_LIT>Operand * Op = new <ISA_LIT>Operand ( k_Immediate , S , E ) ; Op -> Imm . Val = Val ; return Op


<s> unsigned VmcntLo = unpackBits ( Waitcnt , getVmcntBitShiftLo ( ) , getVmcntBitWidthLo ( ) ) ; if ( Version . Major < <NUM_LIT> ) return VmcntLo ; unsigned VmcntHi = unpackBits ( Waitcnt , getVmcntBitShiftHi ( ) , getVmcntBitWidthHi ( ) ) ; VmcntHi <<= getVmcntBitWidthLo ( ) ; return VmcntLo


<s> return DecodeMem ( Inst , insn , Address , Decoder ,


<s> double r ; __asm__ ( <STR_LIT> : <STR_LIT> ( r ) : <STR_LIT> ( x ) , <STR_LIT> ( y ) , <STR_LIT> ( z ) ) ; return r


<s> bool <ISA_LIT>FrameLowering :: hasSP ( const MachineFunction &


<s> rtx mem = plus_constant ( Pmode , stack_pointer_rtx , adjustment ) ; mem = gen_rtx_POST_MODIFY ( Pmode , stack_pointer_rtx , mem ) ; emit_move_insn ( reg1 , gen_frame_mem ( mode , mem ) ) ; } else { rtx reg2 = gen_rtx_REG ( mode , regno2


<s> void s390_expand_vec_compare ( rtx target , enum rtx_code cond , rtx cmp_op1 , rtx cmp_op2 ) { machine_mode mode = GET_MODE ( target ) ; bool neg_p = false , swap_p = false ; rtx tmp ; if ( GET_MODE_CLASS ( GET_MODE ( cmp_op1 ) ) == MODE_VECTOR_FLOAT ) { switch ( cond ) { case NE : cond = EQ ; neg_p = true ; break ; case UNGT : cond = GE ; neg_p = true ; swap_p = true ; break ; case UNGE : cond = GT ; neg_p = true ; swap_p = true ; break ; case LE : cond = GE ; swap_p = true ; break ; case UNLE : cond = GT ; neg_p = true ; break ; case LT : cond = GT ; swap_p = true ; break ; case UNLT : cond = GE ; neg_p = true ; break ; case UNEQ : emit_insn ( gen_vec_cmpuneq ( target , cmp_op1 , cmp_op2 ) ) ; return ; case LTGT : emit_insn ( gen_vec_cmpltgt ( target , cmp_op1 , cmp_op2 ) ) ; return ; case ORDERED : emit_insn ( gen_vec_ordered ( target , cmp_op1 , cmp_op2 ) ) ; return ; case UNORDERED : emit_insn ( gen_vec_unordered ( target , cmp_op1 , cmp_op2 ) ) ; return ; default : break ; } } else { switch ( cond ) { case NE : cond = EQ ; neg_p = true ; break ; case GE : cond = GT ; neg_p = true ; swap_p = true ; break ; case GEU : cond = GTU ; neg_p = true ; swap_p = true ; break ; case LE : cond = GT ; neg_p = true ; break ; case LEU : cond = GTU ; neg_p = true ; break ; case LT : cond = GT ; swap_p = true ; break ; case LTU : cond = GTU ; swap_p = true ; break ; default : break ; } } if ( swap_p ) { tmp = cmp_op1 ; cmp_op1 = cmp_op2 ; cmp_op2 =


<s> assert ( ( ~ STI . getFeatureBits ( ) & llvm :: <STR_LIT> ) && <STR_LIT> ) ; assert ( MI . getNumOperands ( ) >= <NUM_LIT> && <STR_LIT> ) ; for ( unsigned OI = <NUM_LIT> , OE = MI . getNumOperands ( ) ; OI < OE ; ++ OI ) { assert ( MI . getOperand ( OI ) . isReg ( ) && <STR_LIT> ) ; if ( MI . getOperand ( OI ) . getReg ( ) == <STR_LIT> || MI . getOperand ( OI ) . getReg ( ) == <STR_LIT> ) { Info = <STR_LIT> ; return true


<s> virtual const ScalarTargetTransformInfo *

getScalarTargetTransformInfo ( ) const {


<s> const DataLayout * DL = TM . getDataLayout ( ) ; SmallString < <NUM_LIT> > Name ; raw_svector_ostream ( Name ) << DL -> getPrivateGlobalPrefix ( ) <<


<s> if ( isDesirableToShrinkOp ( Op . getOpcode ( ) , <STR_LIT> , Op . getValueType ( ) ) ) { return false ; } PVT = <STR_LIT> ; return true ; return false


<s> bool <ISA_LIT>TargetLowering :: shouldReduceLoadWidth ( SDNode * N , <STR_LIT> ExtTy , EVT NewVT ) const { if ( ! TargetLoweringBase :: shouldReduceLoadWidth ( N , ExtTy , NewVT ) ) return false ; unsigned NewSize = NewVT . getStoreSizeInBits ( ) ; if ( NewSize == <NUM_LIT> ) return true ; EVT OldVT = N -> getValueType ( <NUM_LIT> ) ; unsigned OldSize = OldVT . getStoreSizeInBits ( ) ; MemSDNode * MN = cast < MemSDNode > ( N


<s> return ( __m128i ) __builtin_ia32_packuswb128_mask ( ( __v8hi ) __A , ( __v8hi ) __B , (


<s> bool Changed = false ; TII = SubTarget . getInstrInfo ( ) ; EndbrOpcode = SubTarget . is64Bit ( ) ? <STR_LIT> : <STR_LIT> ; if ( ( TM -> getCodeModel ( ) == CodeModel :: Large || MF . getFunction ( ) . hasAddressTaken ( ) || ! MF . getFunction ( ) . hasLocalLinkage ( ) ) && ! MF . getFunction ( ) . doesNoCfCheck ( ) ) { auto MBB = MF . begin ( ) ; Changed |= addENDBR ( * MBB , MBB -> begin ( ) ) ; } for ( auto & MBB : MF ) { if ( MBB . hasAddressTaken ( ) ) Changed |= addENDBR ( MBB , MBB . begin ( ) ) ; for ( MachineBasicBlock :: iterator I = MBB . begin ( ) ; I != MBB . end ( ) ; ++ I ) { if ( I -> isCall ( ) && I -> getNumOperands ( ) > <NUM_LIT> && IsCallReturnTwice ( I -> getOperand ( <NUM_LIT> ) ) ) { Changed |= addENDBR ( MBB , std :: next ( I ) ) ; } } if ( TM -> Options . ExceptionModel == ExceptionHandling :: SjLj ) { for ( MachineBasicBlock :: iterator I = MBB . begin ( ) ; I != MBB . end ( ) ; ++ I ) { if ( MBB . isEHPad ( ) ) { if ( I -> isDebugInstr ( ) ) continue ; Changed |= addENDBR ( MBB , I ) ; break ; } else if ( I ->


<s> I != MBB -> livein_end ( ) ; ) { MCPhysReg Reg = I -> PhysReg ; static_assert ( <STR_LIT> - <STR_LIT> == <NUM_LIT> , <STR_LIT> ) ; if ( Reg >= <STR_LIT> && Reg <= <STR_LIT> ) { Mask |= <NUM_LIT> << ( Reg - <STR_LIT> ) ; if ( RemoveFPs ) { I = MBB -> removeLiveIn


<s> const ReduceEntry & Entry = ReduceTable [ OPI -> second ] ; if ( Entry . Special ) return ReduceSpecial ( MBB , MI , Entry , LiveCPSR , IsSelfLoop ) ; if ( Entry . NarrowOpc2 && ReduceTo2Addr ( MBB , MI , Entry , LiveCPSR , IsSelfLoop ) ) return true ; if ( Entry . NarrowOpc1 && ReduceToNarrow ( MBB , MI , Entry , LiveCPSR


<s> const <ISA_LIT>Subtarget & STI = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( STI . isTargetWindowsCoreCLR ( ) ) { if ( InProlog ) { BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) ) . addImm ( <NUM_LIT> ) ; } else { emitStackProbeInline ( MF , MBB , MBBI , DL , false ) ; } } else { emitStackProbeCall ( MF , MBB , MBBI , DL , InProlog


<s> unsigned Rd = fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned Rm = fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned Rn = fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) ; if ( Rd == Rm || Rm == Rn || Rd == Rn ) return MCDisassembler :: Fail ; if ( ! DecodeGPR64commonRegisterClass ( Inst , Rd , Addr , Decoder ) || ! DecodeGPR64RegisterClass ( Inst , Rn , Addr , Decoder ) || ! DecodeGPR64commonRegisterClass ( Inst , Rd , Addr , Decoder ) || ! DecodeGPR64RegisterClass ( Inst , Rn , Addr

, Decoder ) || ! DecodeGPR64RegisterClass ( Inst , Rm , Addr , Decoder ) ) return MCDisassembler :: Fail ;


<s> BuildMI ( * BB , I , DL , TII -> get ( <STR_LIT> ) ) . addUse ( Tmp ) . addUse ( Address ) . addImm ( Imm ) ; } else { Register Tmp = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * BB , I , DL , TII -> get ( <STR_LIT> ) ) . addDef ( Tmp ) . addUse ( StoreVal ) . addImm ( <NUM_LIT> ) ; BuildMI ( * BB , I , DL , TII -> get ( <STR_LIT> ) ) . addUse ( Tmp ) . addUse ( Address ) . addImm ( Imm + ( IsLittle ? <NUM_LIT> : <NUM_LIT> ) ) ; BuildMI ( * BB , I , DL , TII -> get ( <STR_LIT> ) ) . addUse ( Tmp ) . addUse ( Address ) . addImm ( Imm + ( IsLittle ? <NUM_LIT> : <NUM_LIT> ) ) ; } MI . eraseFromParent (


<s> assert ( ( MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> ) && ( MO . getReg ( ) >= <STR_LIT> && MO . getReg ( ) <= <STR_LIT> ) ) ; return <NUM_LIT> >> TM . getRegisterInfo ( ) -> getEncodingValue ( MO . getReg (


<s> MachineInstr * MI = BuildMI ( MBB , MBBI , dl , MF . getSubtarget ( ) . getInstrInfo ( ) -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( LocalReg ) ; BuildMI ( MBB , MI , dl , MF . getSubtarget ( ) . getInstrInfo ( ) -> get ( <STR_LIT> ) , LocalReg ) . addImm ( MF . getFunctionNumber ( ) ) ; } else { unsigned LocalReg = MRI . createVirtualRegister ( & <STR_LIT>


<s> std :: string Diagnostic = <STR_LIT> + Description ; int64_t Min = minIntN ( Width ) ; int64_t Max = maxIntN ( Width ) ; Diagnostic += <STR_LIT> + std :: to_string ( Min ) + <STR_LIT> + std :: to_string ( Max ) + <STR_LIT> ; if ( Ctx ) { Ctx -> reportError ( Fixup . getLoc ( ) , Diagnostic ) ; } else { llvm_unreachable ( Diagnostic . c_str ( )


<s> bool isGFX10Before1030 ( const MCSubtargetInfo


<s> for ( unsigned I = <NUM_LIT> , E = array_lengthof ( XPLINKSpillOffsetTable ) ; I != E ; ++ I ) RegSpillOffsets [

XPLINKSpillOffsetTable [ I ] . Reg ] = XPLINKSpillOffsetTable [ I ] . Offset ;


<s> EVT VT = N -> getValueType ( <NUM_LIT> ) ; assert ( VT == <STR_LIT> || VT == <STR_LIT> ) ; unsigned Opc = ( VT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; SDValue Ops [ <NUM_LIT> ] ; SelectVOP3Mods0 ( N -> getOperand ( <NUM_LIT> ) , Ops [ <NUM_LIT> ] , Ops [ <NUM_LIT> ] , Ops [ <NUM_LIT> ] , Ops [ <NUM_LIT> ] ) ; SelectVOP3Mods ( N -> getOperand ( <NUM_LIT> ) , Ops [ <NUM_LIT> ] , Ops [ <NUM_LIT>


<s> if ( VT == <STR_LIT> && ! <ISA_LIT>ScalarSSEf32 ) return false ; if ( VT == <STR_LIT> ) return false ; return ( AllowI1 && VT == <STR_LIT> )


<s> switch ( s390_tune ) { case PROCESSOR_2084_Z990 : case PROCESSOR_2094_Z9_109 : case PROCESSOR_2094_Z9_EC : case PROCESSOR_2817_Z196 : return <NUM_LIT> ; case PROCESSOR_2097_Z10 : return <NUM_LIT> ; case PROCESSOR_9672_G5


<s> TargetRegistry :: RegisterMCRelocationInfo ( * T , create<ISA_LIT>MCRelocationInfo ) ; } for ( Target * T : { & The<ISA_LIT>LETarget , & TheThumbLETarget } ) TargetRegistry :: RegisterMCCodeEmitter ( * T , create<ISA_LIT>LEMCCodeEmitter ) ; for ( Target * T : { & The<ISA_LIT>BETarget , & TheThumbBETarget } ) TargetRegistry :: RegisterMCCodeEmitter ( * T , create<ISA_LIT>BEMCCodeEmitter ) ; TargetRegistry :: RegisterMCAsmBackend ( The<ISA_LIT>LETarget , create<ISA_LIT>LEAsmBackend ) ; TargetRegistry :: RegisterMCAsmBackend ( The<ISA_LIT>BETarget , create<ISA_LIT>BEAsmBackend ) ; TargetRegistry :: RegisterMCAsmBackend ( TheThumbLETarget , createThumbLEAsmBackend


<s> assert ( ( N -> getOpcode ( ) == <STR_LIT> || N -> getOpcode ( ) == <STR_LIT> ) && <STR_LIT> ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( ! VT . is128BitVector ( ) && ! VT . is256BitVector ( ) && ! VT . is512BitVector ( ) ) return SDValue ( ) ; APInt SplatVal ; if ( ! isConstantSplat ( N -> getOperand ( <NUM_LIT> ) , SplatVal ) || ! SplatVal . isOneValue ( ) ) return SDValue ( ) ; SDValue AllOnesVec = getOnesVector ( VT , DAG , SDLoc ( N ) ) ; unsigned NewOpcode = N -> getOpcode ( ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; return DAG . getNode ( NewOpcode , SDLoc ( N ) ,

VT , N -> getOperand ( <NUM_LIT> ) , AllOnesVec ) ;


<s> return DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , r3 , Mul ) ; } const SDValue One = DAG . getConstantFP ( <NUM_LIT> , SL , <STR_LIT> ) ; SDVTList ScaleVT = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SDValue DenominatorScaled = DAG . getNode ( <STR_LIT> , SL , ScaleVT , RHS , RHS , LHS ) ; SDValue NumeratorScaled = DAG . getNode ( <STR_LIT> , SL , ScaleVT , LHS , RHS , LHS ) ; SDValue ApproxRcp = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , DenominatorScaled ) ; SDValue NegDivScale0 = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , DenominatorScaled ) ; SDValue Fma0 = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , NegDivScale0 , ApproxRcp , One ) ; SDValue Fma1 = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Fma0 , ApproxRcp , ApproxRcp ) ; SDValue Mul = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , NumeratorScaled , Fma1 ) ; SDValue Fma2 = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , NegDivScale0 , Mul , NumeratorScaled ) ; SDValue Fma3 = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Fma2 , Fma1 , Mul ) ; SDValue Fma4 = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> ,

NegDivScale0 , Fma3 , NumeratorScaled ) ;


<s> return ( ShuffleVectorSDNode :: isSplatMask ( & M [ <NUM_LIT> ] , VT ) || isVREVMask ( M , VT , <NUM_LIT> ) || isVREVMask ( M , VT , <NUM_LIT> ) || isVREVMask ( M , VT , <NUM_LIT> ) || isVEXTMask ( M , VT , ReverseVEXT , Imm ) || isVTRNMask ( M , VT ,

WhichResult ) || isVUZPMask ( M , VT , WhichResult ) || isVZIPMask ( M , VT , WhichResult ) || isVTRN_v_undef_Mask ( M , VT , WhichResult ) || isVUZP_v_undef_Mask ( M , VT , WhichResult ) || isVZIP_v_undef_Mask ( M , VT , WhichResult ) ) ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; SrcReg2 = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; CmpMask = ~ <NUM_LIT> ; CmpValue = <NUM_LIT> ; return true ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; SrcReg2 = <NUM_LIT> ; CmpMask = ~ <NUM_LIT> ; CmpValue = MI . getOperand ( <NUM_LIT> ) . getImm ( ) != <NUM_LIT> ; return true


<s> for ( const auto & TypeEntry : TypeEntries )


<s> return Kind == k_VectorListAllLanes && VectorList .


<s> if ( ! must_link ( ) && ( cfun -> machine -> callee_saved_reg_size == <NUM_LIT> ) ) { insn = emit_insn ( gen_link ( gen_rtx_REG ( Pmode , FT32_R13 ) , GEN_INT ( - cfun -> machine -> size_for_adjusting_sp ) ) ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; return ; } if ( optimize_size ) { for ( regno = FIRST_PSEUDO_REGISTER ; regno -- > <NUM_LIT> ; ) { if ( ! fixed_regs [ regno ] && ! call_used_regs [ regno ] && df_regs_ever_live_p ( regno ) ) { rtx preg = gen_rtx_REG ( Pmode , regno ) ; emit_insn ( gen_call_prolog ( preg ) ) ; break ; } } } else { for ( regno = <NUM_LIT> ; regno < FIRST_PSEUDO_REGISTER ; regno ++ ) { if ( ! fixed_regs [ regno ] && df_regs_ever_live_p ( regno ) && ! call_used_regs [ regno ] ) { insn = emit_insn ( gen_movsi_push ( gen_rtx_REG ( Pmode , regno ) ) ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; } } } if ( cfun -> machine -> size_for_adjusting_sp >= <NUM_LIT> ) { error ( <STR_LIT> ) ; return ; } if ( must_link ( ) ) { insn = emit_insn ( gen_link ( gen_rtx_REG ( Pmode , FT32_FP ) , GEN_INT ( - cfun -> machine -> size_for_adjusting_sp ) ) ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; } else if ( cfun -> machine -> size_for_adjusting_sp > <NUM_LIT> ) { int adj = cfun -> machine ->


<s> SDValue Src0 = N -> getOperand ( <NUM_LIT> ) ; SDValue Src1 = N -> getOperand ( <NUM_LIT> ) ; EVT CmpVT = Src0 . getValueType ( ) ; SDLoc SL ( N ) ; if ( CmpVT == <STR_LIT> && ! TLI . isTypeLegal ( CmpVT ) ) { Src0 = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Src0 ) ; Src1 = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Src1 ) ; } FCmpInst :: Predicate IcInput = static_cast < FCmpInst :: Predicate > ( CondCode ) ; <STR_LIT> CCOpcode = getFCmpCondCode ( IcInput ) ; unsigned WavefrontSize = TLI . getSubtarget ( ) -> getWavefrontSize ( ) ; EVT CCVT = EVT :: getIntegerVT ( * DAG . getContext ( ) , WavefrontSize ) ; SDValue SetCC = DAG . getNode ( <STR_LIT> , SL , CCVT , Src0 , Src1 , DAG . getCondCode


<s> else if ( ( GET_CODE ( x ) == POST_INC || GET_CODE ( x ) == PRE_DEC ) && MAYBE_BASE_REGISTER_RTX_P ( XEXP ( x , <NUM_LIT> ) , strict ) ) return true ; else if ( GET_CODE ( x ) == PLUS ) { rtx xop0 = XEXP ( x , <NUM_LIT> ) ; rtx xop1 = XEXP ( x , <NUM_LIT> ) ; if ( REG_P ( xop0 ) && REGNO ( xop0 ) == GBR_REG ) return gbr_displacement ( xop1 , mode ) ; if ( GET_MODE_SIZE ( mode ) <= <NUM_LIT> && MAYBE_BASE_REGISTER_RTX_P ( xop0 , strict ) && sh_legitimate_index_p ( mode , xop1 , TARGET_SH2A , false ) ) return true ; if ( GET_MODE_SIZE ( mode ) <= <NUM_LIT> || ( TARGET_FPU_DOUBLE && TARGET_FMOVD && mode == DFmode ) ) { if ( MAYBE_BASE_REGISTER_RTX_P ( xop1 , strict ) && MAYBE_INDEX_REGISTER_RTX_P ( xop0 ,


<s> default : return ParseMemOperand ( ) ; case AsmToken :: Percent : { unsigned RegNo ; SMLoc Start , End ; if ( ParseRegister ( RegNo , Start , End ) ) return <NUM_LIT> ; return <STR_LIT> ( RegNo , Start , End ) ; } case AsmToken :: Dollar : { SMLoc Start = Parser . getTok ( ) . getLoc ( ) , End ; Parser . Lex ( ) ; const MCExpr * Val ; if ( getParser ( ) . ParseExpression ( Val , End ) ) return <NUM_LIT> ; return <STR_LIT> ( Val , Start , End


<s> Name . insert ( Name . begin ( ) , Prefix , Prefix + strlen ( Prefix ) ) ; break ; } case <STR_LIT> : case <STR_LIT> : { Name += <STR_LIT> ; MCSymbol * Sym = Ctx . GetOrCreateSymbol ( Name . str ( ) ) ; MachineModuleInfoImpl :: StubValueTy & StubSym = getMachOMMI ( ) . getGVStubEntry ( Sym ) ; if ( StubSym . getPointer ( ) == <NUM_LIT> ) { assert ( MO . isGlobal ( ) && <STR_LIT> ) ; StubSym = MachineModuleInfoImpl :: StubValueTy ( Mang -> getSymbol ( MO . getGlobal ( ) ) , ! MO . getGlobal ( ) -> hasInternalLinkage ( ) ) ; } return Sym ; } case <STR_LIT> : { Name += <STR_LIT> ; MCSymbol * Sym = Ctx . GetOrCreateSymbol ( Name . str ( ) ) ; MachineModuleInfoImpl :: StubValueTy & StubSym = getMachOMMI ( ) . getHiddenGVStubEntry ( Sym ) ; if ( StubSym . getPointer ( ) == <NUM_LIT> ) { assert ( MO . isGlobal ( ) && <STR_LIT> ) ; StubSym = MachineModuleInfoImpl :: StubValueTy ( Mang -> getSymbol ( MO . getGlobal ( ) ) , ! MO . getGlobal ( ) -> hasInternalLinkage ( ) ) ; } return Sym ; } case <STR_LIT> : { Name += <STR_LIT> ; MCSymbol * Sym = Ctx . GetOrCreateSymbol ( Name . str ( ) ) ; MachineModuleInfoImpl :: StubValueTy & StubSym = getMachOMMI ( ) . getFnStubEntry ( Sym ) ; if ( StubSym . getPointer ( ) ) return Sym ; if ( MO . isGlobal ( ) ) { StubSym =


<s> assert ( MO . isExpr ( ) && <STR_LIT> ) ; const MCExpr * Expr = MO . getExpr ( ) ; Fixups . push_back ( MCFixup :: create ( <NUM_LIT> , Expr ,


<s> Val = Tok . getIntVal ( ) ; if ( Val > <NUM_LIT> || Val < <NUM_LIT> ) { TokError ( <STR_LIT> ) ; return MatchOperand_ParseFail ; } } else { APFloat RealVal ( APFloat :: IEEEdouble ( ) , Tok . getString ( ) ) ; uint64_t IntVal = RealVal . bitcastToAPInt ( ) . getZExtValue ( ) ; IntVal ^= ( uint64_t ) isNegative << <NUM_LIT> ; Val = <STR_LIT> ( APInt ( <NUM_LIT> , IntVal ) ) ; } Parser . Lex ( ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateFPImm ( Val , S , getContext ( ) ) ) ; return MatchOperand_Success ; } if ( ! Hash ) return MatchOperand_NoMatch ; TokError (


<s> unsigned Idx = <NUM_LIT> ; for ( auto & Arg : F . args ( ) ) { ArgInfo OrigArgInfo ( VRegs [ Idx ] , Arg . getType ( ) , Idx ) ; setArgFlags ( OrigArgInfo , Idx + AttributeList :: FirstArgIndex , DL , F ) ; splitToValueTypes ( OrigArgInfo , SplitArgInfos , DL , F . getCallingConv ( ) ) ; Idx ++ ; } if ( ! MBB . empty ( ) ) MIRBuilder . setInstr ( * MBB . begin ( ) ) ; if ( ! determineAndHandleAssignments ( ArgHandler , ArgAssigner , SplitArgInfos , MIRBuilder , F . getCallingConv ( ) , F . isVarArg ( ) ) ) return false ; MIRBuilder . setMBB


<s> unsigned Opc = isThumb ? ( isThumb2 ? <STR_LIT> : <STR_LIT> ) : <STR_LIT> ; if ( ! isThumb ) BuildMI ( OrigBB , DebugLoc ( ) , TII -> get ( Opc ) ) . addMBB ( NewBB ) ; else BuildMI ( OrigBB , DebugLoc ( ) , TII -> get ( Opc ) ) . addMBB ( NewBB ) . addImm ( <STR_LIT> ) . addReg ( <NUM_LIT> ) ; ++ NumSplit ; while ( ! OrigBB -> succ_empty ( ) ) { MachineBasicBlock * Succ = * OrigBB -> succ_begin ( ) ; OrigBB -> removeSuccessor ( Succ ) ; NewBB -> addSuccessor ( Succ ) ; assert ( ( Succ -> empty ( ) || ! Succ -> begin ( ) -> isPHI ( ) ) && <STR_LIT> ) ; } OrigBB -> addSuccessor ( NewBB ) ; MF . RenumberBlocks ( NewBB ) ; BBSizes . insert ( BBSizes . begin ( ) + NewBB -> getNumber ( ) , <NUM_LIT> ) ; BBOffsets . insert ( BBOffsets . begin ( ) + NewBB -> getNumber ( ) , <NUM_LIT> ) ; water_iterator IP = std :: lower_bound ( WaterList . begin ( ) , WaterList . end ( ) , OrigBB , CompareMBBNumbers ) ; MachineBasicBlock * WaterBB = * IP ; if ( WaterBB == OrigBB ) WaterList . insert ( llvm :: next ( IP ) , NewBB ) ; else WaterList . insert ( IP , OrigBB ) ; NewWaterList . insert ( OrigBB ) ; unsigned OrigBBI = OrigBB -> getNumber ( ) ; unsigned NewBBI = NewBB -> getNumber ( ) ; int delta = isThumb1 ? <NUM_LIT> : <NUM_LIT> ; unsigned OrigBBSize = <NUM_LIT> ; for ( MachineBasicBlock :: iterator I = OrigBB -> begin ( ) , E = OrigBB -> end ( ) ; I != E ; ++ I ) OrigBBSize += TII -> GetInstSizeInBytes ( I ) ; BBSizes [ OrigBBI ] = OrigBBSize ; BBOffsets [ NewBBI ] = BBOffsets [ OrigBBI ] + BBSizes [ OrigBBI ] ; unsigned NewBBSize = <NUM_LIT> ; for ( MachineBasicBlock :: iterator I = NewBB -> begin ( ) , E = NewBB -> end ( ) ; I != E ; ++ I ) NewBBSize += TII -> GetInstSizeInBytes ( I ) ; BBSizes [ NewBBI ] = NewBBSize ; MachineInstr * ThumbJTMI = prior ( NewBB -> end ( ) ) ; if ( ThumbJTMI -> getOpcode ( ) == <STR_LIT> ) { unsigned OrigOffset = BBOffsets [ OrigBBI ] + BBSizes [


<s> if ( EnableBitSimplify ) addPass ( create<ISA_LIT>BitSimplify ( ) ) ; addPass ( create<ISA_LIT>Peephole ( ) ) ; if ( ! DisableHCP ) { addPass ( create<ISA_LIT>ConstPropagationPass ( ) ) ; addPass ( & UnreachableMachineBlockElimID ) ; } if ( EnableGenInsert ) addPass ( create<ISA_LIT>GenInsert ( ) ) ; if ( EnableEarlyIf ) addPass ( create<ISA_LIT>EarlyIfConversion ( ) ) ; } return false


<s> case <STR_LIT> : case <STR_LIT> : return ( int64_t ) Value / <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; } llvm_unreachable ( <STR_LIT> ) ; } namespace { class <ISA_LIT>MCAsmBackend : public MCAsmBackend { uint8_t OSABI ; public : <ISA_LIT>MCAsmBackend ( uint8_t osABI ) : OSABI ( osABI ) { } unsigned getNumFixupKinds ( ) const override { return <STR_LIT> ; } const MCFixupKindInfo & getFixupKindInfo ( MCFixupKind Kind ) const override ; void applyFixup ( const MCFixup & Fixup , char * Data , unsigned DataSize , uint64_t Value , bool IsPCRel ) const override ; bool mayNeedRelaxation ( const MCInst & Inst ) const override { return false ; } bool fixupNeedsRelaxation ( const MCFixup & Fixup , uint64_t Value , const MCRelaxableFragment * Fragment , const MCAsmLayout & Layout ) const override { return false ; } void relaxInstruction ( const MCInst & Inst , const MCSubtargetInfo & STI , MCInst & Res ) const override { llvm_unreachable ( <STR_LIT> ) ; } bool writeNopData ( uint64_t Count , MCObjectWriter * OW ) const override ; MCObjectWriter * createObjectWriter ( raw_pwrite_stream & OS ) const override { return create<ISA_LIT>ObjectWriter ( OS , OSABI ) ; } } ; } const MCFixupKindInfo & <ISA_LIT>MCAsmBackend :: getFixupKindInfo ( MCFixupKind Kind ) const { const static MCFixupKindInfo Infos [ <STR_LIT> ] = { { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } } ; if ( Kind < FirstTargetFixupKind ) return MCAsmBackend :: getFixupKindInfo ( Kind ) ; assert ( unsigned ( Kind - FirstTargetFixupKind ) < getNumFixupKinds ( ) && <STR_LIT> ) ; return Infos [ Kind - FirstTargetFixupKind ] ; } void <ISA_LIT>MCAsmBackend :: applyFixup ( const MCFixup & Fixup , char * Data , unsigned DataSize , uint64_t


<s> std :: vector < CPEntry > & CPEs = CPEntries [ CPI ] ; for ( CPEntry & CPE : CPEs ) if ( CPE . CPEMI == CPEMI ) return & CPE ; return nullptr


<s> __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT> ( b ) : ) ; return


<s> if ( cast < VectorType > ( VecTy ) -> isScalable ( ) ) return false ; if ( ! cast < VectorType > ( VecTy ) -> getElementType ( ) -> isIntegerTy ( ) ) return false ; EVT VecVT = EVT :: getEVT ( VecTy ) ; if ( ! VecVT . isSimple ( ) || VecVT . getSizeInBits ( ) <= <NUM_LIT> ) return false ; if ( ST . isHVXVectorType ( VecVT . getSimpleVT ( ) ) ) return true ; auto Action = TLI . getPreferredVectorAction ( VecVT . getSimpleVT ( ) ) ; return Action == TargetLoweringBase ::


<s> unsigned getOpSize ( const MachineInstr & MI , unsigned OpNo )


<s> unsigned <ISA_LIT>MachineFunctionInfo :: addQueuePtr ( const <ISA_LIT>RegisterInfo & TRI ) { ArgInfo . QueuePtr = ArgDescriptor :: createRegister ( TRI . getMatchingSuperReg ( getNextUserSGPR ( ) , <STR_LIT> , & <STR_LIT> ) ) ; NumUserSGPRs += <NUM_LIT>


<s> unsigned getInliningThresholdMultiplier (


<s> MachineBasicBlock * MBB = MI -> getParent ( ) ; MachineInstr * BMI = & MBB -> back ( ) ; bool NeedSplit = ( BMI != MI ) || ! BBHasFallthrough ( MBB ) ; ++ NumCBrFixed ; if ( BMI != MI ) { if ( std :: next ( MachineBasicBlock :: iterator ( MI ) ) == std :: prev ( MBB -> end ( ) ) && BMI -> getOpcode ( ) == Br . UncondBr ) { MachineBasicBlock * NewDest = BMI -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; if ( BBUtils -> isBBInRange ( MI , NewDest , Br . MaxDisp ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * BMI ) ; BMI -> getOperand ( <NUM_LIT> ) . setMBB ( DestBB ) ; MI -> getOperand ( <NUM_LIT> ) . setMBB ( NewDest ) ; MI -> getOperand ( <NUM_LIT> ) . setImm ( CC ) ; return true ; } } } if ( NeedSplit ) { splitBlockBeforeInstr ( MI ) ; int delta = TII -> getInstSizeInBytes ( MBB -> back ( ) ) ; BBUtils -> adjustBBSize ( MBB , - delta ) ; MBB -> back ( ) . eraseFromParent ( ) ; MBB -> addSuccessor ( DestBB ) ; std :: next ( MBB -> getIterator ( ) ) -> removeSuccessor ( DestBB ) ; } MachineBasicBlock * NextBB = & * ++ MBB -> getIterator ( ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << printMBBReference ( * DestBB ) << <STR_LIT> << printMBBReference ( * NextBB ) << <STR_LIT> ) ; BuildMI ( MBB , DebugLoc ( ) , TII -> get ( MI -> getOpcode ( ) ) ) . addMBB ( NextBB ) . addImm ( CC ) . addReg ( CCReg ) ; Br . MI = & MBB -> back ( ) ; BBUtils -> adjustBBSize ( MBB , TII -> getInstSizeInBytes ( MBB -> back ( ) ) ) ; if ( isThumb ) BuildMI ( MBB , DebugLoc ( ) , TII -> get ( Br . UncondBr ) ) . addMBB ( DestBB ) . add ( predOps


<s> bool isVecListFourQ ( ) const { if ( ! isDoubleSpacedVectorList ( ) ) return false ; return VectorList . Count


<s> x = emit_jump_insn ( gen_rtx_SET ( pc_rtx , x ) ) ; add_int_reg_note ( x , REG_BR_PROB ,


<s> bool <ISA_LIT>PassConfig :: addInstSelector ( ) { addPass ( create<ISA_LIT>ISelDag ( get<ISA_LIT>TargetMachine ( ) , getOptLevel ( ) ) ) ; if ( Triple ( TM -> getTargetTriple ( ) ) . isOSBinFormatELF ( ) && getOptLevel ( ) != CodeGenOpt :: None )


<s> unsigned BitWidth = VT . getSizeInBits ( ) - NumberOfIgnoredHighBits ; APInt SignificantDstMask = APInt ( BitWidth , DstMask ) ; APInt SignificantBitsToBeInserted = BitsToBeInserted . zextOrTrunc ( BitWidth ) ; return ( SignificantDstMask & SignificantBitsToBeInserted ) == <NUM_LIT> && (

SignificantDstMask | SignificantBitsToBeInserted ) . isAllOnesValue ( ) ;


<s> Optional < int64_t > OffsetVal = getConstantVRegVal ( Reg , MRI ) ; if ( ! OffsetVal || ! isInt < <NUM_LIT> > ( * OffsetVal ) ) return None ; return Lo_32 ( * OffsetVal


<s> static DecodeStatus DecodeSETPANInstruction ( MCInst & Inst , unsigned Insn , uint64_t Address , const MCDisassembler * Decoder ) { DecodeStatus S = MCDisassembler :: Success ; unsigned Imm = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; const MCDisassembler * Dis = static_cast < const MCDisassembler * > ( Decoder ) ; const FeatureBitset & FeatureBits = Dis -> getSubtargetInfo ( ) . getFeatureBits ( ) ; if ( ! FeatureBits [ <STR_LIT> ] || !

FeatureBits [ <STR_LIT> ] ) return MCDisassembler :: Fail ;


<s> if ( Model == TLSModel :: LocalDynamic ) Model = TLSModel :: GeneralDynamic ; } SDValue TPOff ; EVT PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; SDLoc DL ( Op ) ; const GlobalValue * GV = GA -> getGlobal ( ) ; SDValue ThreadBase = DAG . getNode ( <STR_LIT> , DL , PtrVT ) ; if ( Model == TLSModel :: LocalExec ) { SDValue HiVar = DAG . getTargetGlobalAddress ( GV , DL , PtrVT , <NUM_LIT> , <STR_LIT> | <STR_LIT> ) ; SDValue LoVar = DAG . getTargetGlobalAddress ( GV , DL , PtrVT , <NUM_LIT> , <STR_LIT> | <STR_LIT> | <STR_LIT> ) ; SDValue TPWithOff_lo = SDValue ( DAG . getMachineNode ( <STR_LIT> , DL , PtrVT , ThreadBase , HiVar , DAG . getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) , <NUM_LIT> ) ; SDValue TPWithOff = SDValue ( DAG . getMachineNode ( <STR_LIT> , DL , PtrVT , TPWithOff_lo , LoVar , DAG . getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) , <NUM_LIT> ) ; return TPWithOff ; } else if ( Model == TLSModel :: InitialExec ) { TPOff = DAG . getTargetGlobalAddress ( GV , DL , PtrVT , <NUM_LIT> , <STR_LIT> ) ; TPOff = DAG . getNode ( <STR_LIT> , DL , PtrVT , TPOff ) ; } else if ( Model == TLSModel :: LocalDynamic ) { <ISA_LIT>FunctionInfo * MFI = DAG . getMachineFunction ( ) . getInfo < <ISA_LIT>FunctionInfo > ( ) ; MFI -> incNumLocalDynamicTLSAccesses ( ) ; SDValue SymAddr = DAG . getTargetExternalSymbol ( <STR_LIT> , PtrVT , <STR_LIT> ) ; TPOff = LowerELFTLSDescCallSeq ( SymAddr , DL , DAG ) ; SDValue HiVar = DAG . getTargetGlobalAddress ( GV , DL , <STR_LIT> , <NUM_LIT> , <STR_LIT> | <STR_LIT> ) ; SDValue LoVar = DAG . getTargetGlobalAddress ( GV , DL , <STR_LIT> , <NUM_LIT> , <STR_LIT> | <STR_LIT> | <STR_LIT> ) ; TPOff = SDValue ( DAG . getMachineNode ( <STR_LIT> , DL , PtrVT , TPOff , HiVar , DAG . getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) , <NUM_LIT> ) ; TPOff = SDValue ( DAG . getMachineNode ( <STR_LIT> , DL , PtrVT , TPOff , LoVar , DAG . getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) , <NUM_LIT> ) ; } else if ( Model == TLSModel :: GeneralDynamic ) { SDValue SymAddr = DAG . getTargetGlobalAddress ( GV , DL , PtrVT , <NUM_LIT> , <STR_LIT> ) ; TPOff = LowerELFTLSDescCallSeq ( SymAddr , DL , DAG ) ; } else llvm_unreachable ( <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , DL , PtrVT , ThreadBase


<s> if ( ! MO . isReg ( ) ) continue ; unsigned Reg = MO . getReg ( ) ; if ( ! isVecReg ( Reg ) && ! isScalarVecReg ( Reg ) ) continue ; if ( ! TargetRegisterInfo :: isVirtualRegister ( Reg ) ) { if ( ! ( MI -> isCopy ( ) && isScalarVecReg ( Reg ) ) ) SwapVector [ EntryIdx ] . MentionsPhysVR = <NUM_LIT> ; continue ; } if ( ! MO . isUse ( ) ) continue ; MachineInstr * DefMI = MRI -> getVRegDef ( Reg ) ; assert ( SwapMap . find ( DefMI ) != SwapMap . end ( ) && <STR_LIT> ) ; int DefIdx = SwapMap [ DefMI ] ; ( void ) EC -> unionSets ( SwapVector [ DefIdx ] . VSEId , SwapVector [ EntryIdx ] . VSEId ) ; LLVM_DEBUG ( dbgs ( ) << format ( <STR_LIT> , SwapVector [ DefIdx ]

. VSEId , SwapVector [ EntryIdx ] . VSEId ) ) ;


<s> static struct machine_function * ia64_init_machine_status ( void ) { return ggc_cleared_alloc < machine_function


<s> for ( unsigned int i = <NUM_LIT> ; all_ops [ i ] . index != NUM_VECTOR_TYPES ; i ++ ) if ( type_idx == all_ops [ i ] . index ) return all_ops [ i ] . required_extensions ; for ( unsigned int i = <NUM_LIT> ; b_ops [ i ] . index != NUM_VECTOR_TYPES ; i ++ ) if ( type_idx == b_ops [ i ] . index ) return b_ops [ i ] . required_extensions ; gcc_unreachable (


<s> LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; Op . getParent ( ) -> dump ( ) ) ; <ISA_LIT>DebugValueManager DefDIs ( & Def ) ; unsigned NewReg = MRI . createVirtualRegister ( MRI . getRegClass ( Reg ) ) ; TII -> reMaterialize ( MBB , Insert , NewReg , <NUM_LIT> , Def , * TRI ) ; Op . setReg ( NewReg ) ; MachineInstr * Clone = & * std :: prev ( Insert ) ; LIS . InsertMachineInstrInMaps ( * Clone ) ; LIS . createAndComputeVirtRegInterval ( NewReg ) ; MFI . stackifyVReg ( NewReg ) ; ImposeStackOrdering ( Clone ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; Clone -> dump ( ) ) ; bool IsDead = MRI . use_empty ( Reg ) ; if ( ! IsDead ) { LiveInterval & LI = LIS . getInterval ( Reg ) ; ShrinkToUses ( LI , LIS ) ; IsDead = ! LI . liveAt ( LIS . getInstructionIndex ( Def ) . getDeadSlot ( ) ) ; } if ( IsDead ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; SlotIndex Idx = LIS . getInstructionIndex ( Def


<s> bool <ISA_LIT>DAGToDAGISel :: isRunOfOnes ( unsigned Val , unsigned & MB , unsigned & ME ) { if ( isShiftedMask_32 ( Val ) ) { MB = countLeadingZeros ( Val ) ; ME = countLeadingZeros ( ( Val -


<s> if ( opc == <STR_LIT> || opc == <STR_LIT> ) { unsigned sreg = MI -> getOperand ( ( opc == <STR_LIT> ) ? <NUM_LIT> : <NUM_LIT> ) . getReg ( ) ; BitVector safeSRegs ( getRegisterInfo ( ) . getNumRegs ( ) ) ; safeSRegs . set ( <STR_LIT>


<s> if ( isLoopStart ( MI ) ) return & MI ; } if ( MBB -> pred_size ( ) == <NUM_LIT> ) return SearchForStart ( * MBB -> pred_begin ( ) ) ; return nullptr ; } ; LowOverheadLoop LoLoop ( * ML , * MLI , * RDA , * TRI ) ; if ( auto * Preheader = ML -> getLoopPreheader ( ) ) LoLoop . Start = SearchForStart ( Preheader ) ; else if ( auto * Preheader = MLI -> findLoopPreheader ( ML , true ) ) LoLoop . Start = SearchForStart ( Preheader ) ; else return false ; for ( auto * MBB : reverse ( ML -> getBlocks ( ) ) ) { for ( auto & MI : * MBB ) { if ( MI . isDebugValue ( ) ) continue ; else if ( MI . getOpcode ( ) == <STR_LIT> ) LoLoop . Dec = & MI ; else if ( MI . getOpcode ( ) == <STR_LIT> ) LoLoop . End = & MI ; else if ( isLoopStart ( MI ) ) LoLoop . Start = & MI ; else if ( MI . getDesc ( ) . isCall ( ) ) { LoLoop . Revert = true ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; } else


<s> unsigned DestSub0 = MRI . createVirtualRegister ( DestRC ) ; MachineInstr * LoHalf = BuildMI ( MBB , MII , DL , InstDesc , DestSub0 ) . addOperand ( SrcReg0Sub0 ) ; MachineOperand SrcReg0Sub1 = buildExtractSubRegOrImm ( MII , MRI , Src0 , Src0RC , AMDGPU :: sub1 , Src0SubRC ) ; unsigned DestSub1 = MRI . createVirtualRegister ( DestSubRC ) ; MachineInstr * HiHalf = BuildMI ( MBB , MII , DL , InstDesc , DestSub1 ) . addOperand ( SrcReg0Sub1 ) ; unsigned FullDestReg = MRI . createVirtualRegister ( DestRC ) ; BuildMI ( MBB , MII , DL , get ( TargetOpcode :: REG_SEQUENCE ) , FullDestReg ) . addReg ( DestSub0 ) . addImm ( AMDGPU :: sub0 ) . addReg ( DestSub1 ) . addImm ( AMDGPU :: sub1 ) ; MRI . replaceRegWith ( Dest . getReg ( ) , FullDestReg


<s> if ( PersonalityIndex < <STR_LIT> :: NUM_PERSONALITY_INDEX ) EmitPersonalityFixup ( GetAEABIUnwindPersonalityName ( PersonalityIndex ) ) ; const MCSymbolRefExpr * FnStartRef = MCSymbolRefExpr :: Create ( FnStart , MCSymbolRefExpr :: VK_<ISA_LIT>_PREL31 , getContext ( ) ) ; EmitValue ( FnStartRef , <NUM_LIT> ) ; if ( CantUnwind ) { EmitIntValue ( <STR_LIT> :: EXIDX_CANTUNWIND , <NUM_LIT> ) ; } else if ( ExTab ) { const MCSymbolRefExpr * ExTabEntryRef = MCSymbolRefExpr :: Create ( ExTab , MCSymbolRefExpr :: VK_<ISA_LIT>_PREL31 , getContext ( ) ) ; EmitValue ( ExTabEntryRef


<s> if ( V1 . getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; SDValue Src = V1 . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ; MVT SrcVT = Src . getSimpleValueType ( ) ; if ( ! SrcVT . is512BitVector ( ) && ! Subtarget . hasVLX ( ) ) return SDValue ( ) ; if ( SrcVT . getVectorElementType ( ) == <STR_LIT> && VT == <STR_LIT> && ! Subtarget . hasBWI ( ) ) return SDValue ( ) ; if ( ! matchVectorShuffleAsVPMOV ( Mask , SwappedOps , <NUM_LIT> ) && ! matchVectorShuffleAsVPMOV

( Mask , SwappedOps , <NUM_LIT> ) ) return SDValue ( ) ;


<s> getParser ( ) . Lex ( ) ; if ( getParser ( ) . parseAbsoluteExpression ( Off ) ) return true ; if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) )


<s> bool <ISA_LIT>AsmParser :: ParseInstruction ( ParseInstructionInfo & Info , StringRef Name , SMLoc NameLoc , OperandVector & Operands ) { <ISA_LIT>TextSectOffset ++ ; if ( Name == <STR_LIT> ) Name = <STR_LIT> ; Name = StringSwitch < StringRef > ( Name . lower ( ) ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( Name ) ; size_t Start = <NUM_LIT> , Next = Name . find ( '.' ) ; StringRef Head = Name . slice ( Start , Next ) ; Operands . push_back ( <STR_LIT> ( Head , NameLoc ) ) ; if ( Head == <STR_LIT> && Next != StringRef :: npos ) { Start = Next ; Next = Name . find ( '.' , Start + <NUM_LIT> ) ; Head = Name . slice ( Start + <NUM_LIT> , Next ) ; SMLoc SuffixLoc = SMLoc :: getFromPointer ( NameLoc . getPointer ( ) + ( Head . data ( ) - Name . data ( ) ) ) ; <STR_LIT> CC = parseCondCodeString ( Head ) ; if ( CC == <STR_LIT> :: COND_INVAL ) return Error ( SuffixLoc , <STR_LIT> ) ; const MCExpr * CC_Expr = MCConstantExpr :: create ( ( int64_t ) CC , getContext ( ) ) ; Operands . push_back ( <STR_LIT> ( CC_Expr , Parser . getTok ( ) . getLoc ( ) , SMLoc :: getFromPointer ( Parser . getTok ( ) . getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ) ) ; } if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) { if ( ParseOperand ( Operands , Name ) ) { SMLoc Loc = getLexer ( ) . getLoc ( ) ; Parser . eatToEndOfStatement ( ) ; return Error ( Loc , <STR_LIT> ) ; } while ( getLexer ( ) . is ( AsmToken :: Comma ) ) { Parser . Lex ( ) ; if ( ParseOperand ( Operands , Name ) ) { SMLoc Loc = getLexer ( ) . getLoc ( ) ; Parser . eatToEndOfStatement ( ) ; return Error ( Loc


<s> if ( ! VT . isVector ( ) ) return SDValue ( ) ; if ( ! VT . is64BitVector ( ) && ! VT . is128BitVector ( ) ) return SDValue ( ) ; SDValue N0 = N -> getOperand ( <NUM_LIT> ) ; if ( N0 . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; SDValue N1 = N -> getOperand ( <NUM_LIT> ) ; if ( N1 . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; for ( int i = <NUM_LIT> ; i >= <NUM_LIT> ; -- i ) { for ( int j = <NUM_LIT> ; j >= <NUM_LIT> ; -- j ) { SDValue O0 = N0 -> getOperand ( i ) ; SDValue O1 = N1 -> getOperand ( j ) ; SDValue Sub , Add , SubSibling , AddSibling ; if ( O0 . getOpcode ( ) == <STR_LIT> && O1 . getOpcode ( ) == <STR_LIT> ) { Sub = O0 ; Add = O1 ; SubSibling = N0 -> getOperand ( <NUM_LIT> - i ) ; AddSibling = N1 -> getOperand ( <NUM_LIT> - j ) ; } else if ( O0 . getOpcode ( ) == <STR_LIT> && O1 . getOpcode ( ) == <STR_LIT> ) { Add = O0 ; Sub = O1 ; AddSibling = N0 -> getOperand ( <NUM_LIT> - i ) ; SubSibling = N1 -> getOperand ( <NUM_LIT> - j ) ; } else continue ; if ( ! <STR_LIT> ( Sub . getOperand ( <NUM_LIT> ) . getNode ( ) ) ) continue ; if ( ! <STR_LIT> ( Add . getOperand ( <NUM_LIT> ) . getNode ( ) ) ) continue ; if ( Sub . getOperand ( <NUM_LIT> ) != Add . getOperand ( <NUM_LIT> ) ) continue ; return DAG . getNode ( <STR_LIT> , DL , VT , Sub , SubSibling , AddSibling ) ; } } unsigned Bits = VT . getScalarSizeInBits ( ) ; uint64_t BitMask = Bits == <NUM_LIT> ? - <NUM_LIT> : ( ( <NUM_LIT> << Bits ) - <NUM_LIT> ) ; for ( int i = <NUM_LIT> ; i >= <NUM_LIT> ; -- i ) for ( int j = <NUM_LIT> ; j >= <NUM_LIT> ; -- j ) { BuildVectorSDNode * BVN0 = dyn_cast < BuildVectorSDNode > ( N0 -> getOperand ( i ) ) ; BuildVectorSDNode * BVN1 = dyn_cast < BuildVectorSDNode > ( N1 -> getOperand ( j ) ) ; if ( ! BVN0 || ! BVN1 ) continue ; bool FoundMatch = true ; for ( unsigned k = <NUM_LIT> ; k < VT . getVectorNumElements ( ) ;


<s> if ( is<ISA_LIT>64 ( ) || isFP64 ( ) ) FpFormat = FP_FORMAT_D ; else FpFormat = FP_FORMAT_S


<s> static unsigned HOST_WIDE_INT aarch64_shift_truncation_mask ( machine_mode mode ) { return ( aarch64_vector_mode_supported_p ( mode ) || aarch64_vect_struct_mode_p ( mode ) ) ? <NUM_LIT> : ( GET_MODE_BITSIZE ( mode )


<s> int MaxUInt = ( <NUM_LIT> << width ) ; if ( ExtType == <STR_LIT> ) AddConstant -= ( <NUM_LIT> << ( width - <NUM_LIT> ) ) ; switch ( CC ) { case <STR_LIT> : case <STR_LIT> : if ( ( AddConstant == <NUM_LIT> ) || ( CompConstant == MaxUInt - <NUM_LIT> && AddConstant < <NUM_LIT> ) || ( AddConstant >= <NUM_LIT> && CompConstant < <NUM_LIT> ) || ( AddConstant <= <NUM_LIT> && CompConstant <= <NUM_LIT> && CompConstant < AddConstant ) ) return true ; break ; case <STR_LIT> : case <STR_LIT> : if ( ( AddConstant == <NUM_LIT> ) || ( AddConstant >= <NUM_LIT> && CompConstant <= <NUM_LIT> ) || ( AddConstant <= <NUM_LIT> && CompConstant <= <NUM_LIT> && CompConstant <= AddConstant ) ) return true ; break ; case <STR_LIT> : case <STR_LIT>


<s> if ( alignment > <NUM_LIT> ) alignment = <NUM_LIT> ; SDValue Hi64 = DAG . getLoad ( <STR_LIT> , dl , LdNode -> getChain ( ) , LdNode -> getBasePtr ( ) , LdNode -> getPointerInfo ( ) , false , false , false , alignment ) ; EVT addrVT = LdNode -> getBasePtr ( ) . getValueType ( ) ; SDValue LoPtr = DAG . getNode ( <STR_LIT> , dl , addrVT , LdNode -> getBasePtr ( ) , DAG . getConstant ( <NUM_LIT> , dl , addrVT ) ) ; SDValue Lo64 = DAG . getLoad ( <STR_LIT> , dl , LdNode -> getChain ( ) , LoPtr , LdNode -> getPointerInfo ( ) , false , false , false , alignment ) ; SDValue SubRegEven = DAG . getTargetConstant ( <STR_LIT> , dl , <STR_LIT> ) ; SDValue SubRegOdd = DAG . getTargetConstant (


<s> POPInst . setOpcode ( Is64Bit ? <STR_LIT> : <STR_LIT> ) ; POPInst . addOperand ( MCOperand :: CreateReg ( RegTarget ) ) ; Out . EmitInstruction ( POPInst ) ; if ( AmtOp ) { assert ( ! Is64Bit ) ; MCInst ADDInst ; unsigned ADDReg = <STR_LIT> ; ADDInst . setOpcode ( <STR_LIT> ) ; ADDInst . addOperand ( MCOperand :: CreateReg ( ADDReg ) ) ; ADDInst . addOperand ( MCOperand :: CreateReg ( ADDReg ) ) ; ADDInst . addOperand ( * AmtOp ) ; Out . EmitInstruction ( ADDInst ) ; } MCInst JMPInst ; JMPInst . setOpcode ( Is64Bit ? <STR_LIT> : <STR_LIT> ) ; JMPInst . addOperand ( MCOperand ::


<s> static bool isAbsoluteReg ( unsigned Reg ) { Reg = getReg64 (


<s> int InputIdx0 = - <NUM_LIT> , InputIdx1 = - <NUM_LIT> ; for ( int i = <NUM_LIT> , e = Ops . size ( ) ; i < e ; ++ i ) { SDValue BC = peekThroughBitcasts ( Ops [ i ] ) ; if ( Input0 && BC == peekThroughBitcasts ( Input0 ) ) InputIdx0 = i ; if ( Input1 && BC == peekThroughBitcasts ( Input1 ) ) InputIdx1 = i ; } if ( Input0 && InputIdx0 < <NUM_LIT> ) { InputIdx0 = SrcOpIndex ; Ops [ SrcOpIndex ] = Input0 ; } if ( Input1 && InputIdx1 < <NUM_LIT> ) { InputIdx1 = Ops . size ( ) ; Ops . push_back ( Input1 ) ; } assert ( ( ( RootMask . size ( ) > OpMask . size ( ) && RootMask . size ( ) % OpMask . size ( ) == <NUM_LIT> ) || ( OpMask . size ( ) > RootMask . size ( ) && OpMask . size ( ) % RootMask . size ( ) == <NUM_LIT> ) || OpMask . size ( ) == RootMask . size ( ) ) && <STR_LIT> ) ; assert ( isPowerOf2_32 ( RootMask . size ( ) ) && <STR_LIT> ) ; assert ( isPowerOf2_32 ( OpMask . size ( ) ) && <STR_LIT> ) ; unsigned RootMaskSizeLog2 = countTrailingZeros ( RootMask . size ( ) ) ; unsigned OpMaskSizeLog2 = countTrailingZeros ( OpMask . size ( ) ) ; unsigned MaskWidth = std :: max < unsigned > ( OpMask . size ( ) , RootMask . size ( ) ) ; unsigned RootRatio = std :: max < unsigned > ( <NUM_LIT> , OpMask . size ( ) >> RootMaskSizeLog2 ) ; unsigned OpRatio = std :: max < unsigned > ( <NUM_LIT> , RootMask . size ( ) >> OpMaskSizeLog2 ) ; assert ( ( RootRatio == <NUM_LIT> || OpRatio == <NUM_LIT> ) && <STR_LIT> ) ; assert ( isPowerOf2_32 ( MaskWidth ) && <STR_LIT> ) ; assert ( isPowerOf2_32 ( RootRatio ) && <STR_LIT> ) ; assert ( isPowerOf2_32 ( OpRatio ) && <STR_LIT> ) ; unsigned RootRatioLog2 = countTrailingZeros ( RootRatio ) ; unsigned OpRatioLog2 = countTrailingZeros ( OpRatio ) ; SmallVector < int , <NUM_LIT> > Mask ( MaskWidth , SM_SentinelUndef ) ; for ( unsigned i = <NUM_LIT> ; i <


<s> TM = static_cast < const <ISA_LIT>TargetMachine * > ( & MF . getTarget ( ) ) ; TII = TM -> getSubtargetImpl ( ) -> getInstrInfo ( ) ; bool Changed = false ; if ( MF . size ( ) < <NUM_LIT> ) return Changed ; for ( MachineFunction :: iterator I = MF . begin ( ) ; I != MF .


<s> assert ( LHS . isReg ( ) && RHS . isReg ( ) && <STR_LIT> ) ; MachineRegisterInfo & MRI = MIRBuilder . getMF ( ) . getRegInfo ( ) ; unsigned RegSize = MRI . getType ( LHS . getReg ( ) ) . getSizeInBits ( ) ; bool Is32Bit = ( RegSize == <NUM_LIT> ) ; const unsigned OpcTable [ <NUM_LIT> ] [ <NUM_LIT> ] = { { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } } ; Register ZReg = Is32Bit ? <STR_LIT> : <STR_LIT> ; if ( auto ValAndVReg = getConstantVRegValWithLookThrough ( RHS . getReg ( ) , MRI ) ) { if ( <STR_LIT> ( ValAndVReg -> Value , RegSize ) ) { auto TstMI = MIRBuilder . buildInstr ( OpcTable [ <NUM_LIT> ] [ Is32Bit ] , { ZReg } , { LHS } ) ; TstMI . addImm ( <STR_LIT> ( ValAndVReg -> Value , RegSize ) ) ; constrainSelectedInstRegOperands ( * TstMI , TII , TRI , RBI ) ; return & * TstMI ; } } if ( auto Fns = selectLogicalShiftedRegister ( RHS ) ) return emitInstr ( OpcTable [ <NUM_LIT> ] [

Is32Bit ] , { ZReg } , { LHS } , MIRBuilder , Fns ) ;


<s> if ( Specifier != 's' ) return false ; const PointerType * PT = dyn_cast < PointerType > ( OpType ) ; if ( ! PT || PT -> getAddressSpace ( ) != <ISA_LIT>AS :: CONSTANT_ADDRESS ) return false ; Type * ElemType = PT -> getContainedType ( <NUM_LIT> ) ; if ( ElemType -> getTypeID ( ) != Type :: IntegerTyID ) return


<s> static DecodeStatus DecodeL4RSrcDstSrcDstInstruction ( MCInst & Inst , unsigned Insn , uint64_t Address , const MCDisassembler * Decoder ) { unsigned Op1 , Op2 , Op3 ; unsigned Op4 = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; DecodeStatus S = Decode3OpInstruction ( fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) , Op1 , Op2 , Op3 ) ; if ( S == MCDisassembler :: Success


<s> MachineFunction & MF = DAG . getMachineFunction ( ) ; <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; unsigned <ISA_LIT>PCLabelIndex = AFI -> createConstPoolEntryUId ( ) ; EVT PtrVT = getPointerTy ( ) ; DebugLoc dl = Op . getDebugLoc ( ) ; unsigned PCAdj = Subtarget -> isThumb ( ) ? <NUM_LIT> : <NUM_LIT> ; <ISA_LIT>ConstantPoolValue * CPV = new <ISA_LIT>ConstantPoolValue ( * DAG . getContext ( ) , <STR_LIT> , <ISA_LIT>PCLabelIndex , PCAdj ) ; SDValue CPAddr = DAG . getTargetConstantPool ( CPV ,


<s> Result = DAG . getNode ( <STR_LIT> , DL , PtrVT , Result ) ; Offset -= Anchor ; if ( Offset != <NUM_LIT> && ( Offset & <NUM_LIT> ) == <NUM_LIT> ) { SDValue Full = DAG . getTargetGlobalAddress ( GV , DL , PtrVT , Anchor + Offset ) ; Result = DAG . getNode ( <STR_LIT> , DL , PtrVT , Full , Result ) ; Offset = <NUM_LIT> ; } } else { Result = DAG . getTargetGlobalAddress ( GV , DL , PtrVT , <NUM_LIT> , <STR_LIT> ) ; Result = DAG . getNode ( <STR_LIT> , DL , PtrVT , Result ) ; Result = DAG . getLoad ( PtrVT , DL , DAG . getEntryNode ( ) , Result , MachinePointerInfo :: getGOT ( DAG . getMachineFunction ( ) ) , false , false , false , <NUM_LIT> ) ; } if ( Offset != <NUM_LIT> ) Result = DAG . getNode ( <STR_LIT> , DL ,

PtrVT , Result , DAG . getConstant ( Offset , DL , PtrVT ) ) ;


<s> case <STR_LIT> : JTOpcode = <STR_LIT> ; break ; case <STR_LIT> : JTOpcode = <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : JTOpcode = <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : JTOpcode = <STR_LIT> ; break ; } unsigned NumOps = MI -> getDesc ( ) . getNumOperands ( ) ; MachineOperand JTOp = MI -> getOperand ( NumOps - ( MI -> isPredicable ( ) ? <NUM_LIT> : <NUM_LIT> ) ) ; unsigned JTI = JTOp . getIndex ( ) ; unsigned Size = JT [ JTI ] . MBBs . size ( ) * sizeof ( uint32_t ) ; MachineBasicBlock * JumpTableBB = MF -> CreateMachineBasicBlock ( ) ; MF -> insert ( std :: next ( MachineFunction :: iterator ( MBB ) ) , JumpTableBB ) ; MachineInstr * CPEMI = BuildMI ( * JumpTableBB , JumpTableBB -> begin ( ) , DebugLoc ( ) , TII -> get ( JTOpcode ) ) . addImm ( i ++ ) . addJumpTableIndex ( JTI ) . addImm ( Size ) ; CPEMIs . push_back ( CPEMI ) ; CPEntries . emplace_back ( <NUM_LIT> , CPEntry ( CPEMI , JTI ) ) ; JumpTableEntryIndices . insert ( std :: make_pair ( JTI , CPEntries . size ( ) - <NUM_LIT> ) ) ; if ( ! LastCorrectlyNumberedBB ) LastCorrectlyNumberedBB = &


<s> Value * Src2 = Vals [ Next ( ) ] ; Type * VecTy = ResEVT . getTypeForEVT ( * Ctx ) ; assert ( VecTy -> isVectorTy ( ) ) ; assert ( VecTy == Src1 -> getType ( ) && VecTy == Src2 -> getType ( ) ) ; unsigned NumElt = VecTy -> getVectorNumElements ( ) ; Value * Res = UndefValue ::


<s> bool isBlockAddress ( ) const { return Kind ==


<s> for ( const SDep & PI : Dst -> Preds ) { if ( PI . getLatency ( )


<s> case <STR_LIT> : case <STR_LIT> : return true ; } return


<s> if ( OptLevel == CodeGenOpt :: None ) return false ; return ! DisableMIPreRA


<s> const MCSymbolData & SD = Asm . getSymbolData ( * Reloc . Symbol ) ; if ( MCELF :: GetBinding ( SD ) != ELF :: STB_LOCAL ) return ELF :: R_MIPS_NONE ; if ( Type == ELF :: R_MIPS_GOT16 ) return ELF :: R_MIPS_LO16 ; if ( Type == ELF :: R_MICROMIPS_GOT16 ) return ELF :: R_MICROMIPS_LO16 ; if ( Type == ELF :: R_MIPS16_GOT16


<s> if ( load_p && ( REGNO ( reg1 ) == REGNO ( base1 ) || ( REGNO ( reg2 ) == REGNO ( base1 ) ) ) ) return false ; if ( load_p && REGNO ( reg1 ) == REGNO ( reg2 ) ) return false ; rc1 = REGNO_REG_CLASS ( REGNO ( reg1 ) ) ; rc2 = REGNO_REG_CLASS ( REGNO ( reg2 ) ) ; if ( rc1 != rc2 && ! reg_class_subset_p ( rc1 , rc2 ) && ! reg_class_subset_p ( rc2 , rc1 ) ) return false ; if ( abs ( offset1 - offset2 ) != GET_MODE_SIZE ( mode ) ) return false ; return


<s> raw_svector_ostream OS ( Str ) ; printInstruction ( MI


<s> MVT VT = DataToStore . getSimpleValueType ( ) ; MVT ScalarVT = VT . getScalarType ( ) ; SDValue Mask = N -> getMask ( ) ; SDLoc dl ( Op ) ; assert ( ( ! N -> isCompressingStore ( ) || Subtarget . hasAVX512 ( ) ) && <STR_LIT> ) ; assert ( ( ! N -> isCompressingStore ( ) || ScalarVT . getSizeInBits ( ) >= <NUM_LIT> ) && <STR_LIT> ) ; assert ( Subtarget . hasAVX512 ( ) && ! Subtarget . hasVLX ( ) && ! VT . is512BitVector ( ) && <STR_LIT> ) ; assert ( ( ScalarVT . getSizeInBits ( ) >= <NUM_LIT> || ( Subtarget . hasBWI ( ) && ( ScalarVT == <STR_LIT> || ScalarVT == <STR_LIT> ) ) ) && <STR_LIT> ) ; unsigned NumEltsInWideVec = <NUM_LIT> / VT . getScalarSizeInBits ( ) ; MVT WideDataVT = <STR_LIT> ( ScalarVT , NumEltsInWideVec ) ; assert ( Mask . getSimpleValueType ( ) . getScalarType ( ) == <STR_LIT> && <STR_LIT> ) ; MVT WideMaskVT = <STR_LIT> ( <STR_LIT> , NumEltsInWideVec ) ; DataToStore = ExtendToType ( DataToStore , WideDataVT , DAG ) ; Mask = ExtendToType ( Mask , WideMaskVT , DAG , true ) ; return DAG . getMaskedStore ( N -> getChain ( ) , dl , DataToStore , N -> getBasePtr ( ) , Mask , N ->

getMemoryVT ( ) , N -> getMemOperand ( ) , N -> isTruncatingStore ( ) , N -> isCompressingStore ( ) ) ;


<s> <ISA_LIT>JITInfo :: <ISA_LIT>JITInfo ( bool UseSSE


<s> MCOperand <ISA_LIT>MCInstLower :: LowerOperand ( const MachineOperand & MO , unsigned offset ) const { MachineOperandType MOTy = MO . getType ( ) ; switch ( MOTy ) { default : assert ( <NUM_LIT> && <STR_LIT> ) ; break ; case MachineOperand :: MO_Register


<s> switch ( RC -> getSize ( ) * <NUM_LIT> ) { case <NUM_LIT> : Opcode = <STR_LIT> ; break ; case <NUM_LIT> : Opcode = <STR_LIT> ; break ; case <NUM_LIT> : Opcode = <STR_LIT> ; break ; case <NUM_LIT> : Opcode = <STR_LIT> ; break ; case <NUM_LIT> : Opcode = <STR_LIT> ; break ; case <NUM_LIT> : Opcode = <STR_LIT> ; break ; } } if ( Opcode != - <NUM_LIT> ) { FrameInfo -> setObjectAlignment ( FrameIndex , <NUM_LIT> ) ; BuildMI ( MBB , MI , DL , get ( Opcode ) ) . addReg ( SrcReg ) . addFrameIndex ( FrameIndex ) . addReg ( <STR_LIT> , RegState :: Undef ) . addReg ( <STR_LIT> , RegState :: Undef ) ; } else


<s> SDValue In64 ; if ( Subtarget . hasHighWord ( ) ) { SDNode * U64 = DAG . getMachineNode ( TargetOpcode :: IMPLICIT_DEF , DL , <STR_LIT> ) ; In64 = DAG . getTargetInsertSubreg ( <STR_LIT> , DL , <STR_LIT> , SDValue ( U64 , <NUM_LIT> ) , In ) ; } else { In64 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , In ) ; In64 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , In64 , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; } SDValue Out64 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , In64 ) ; return DAG . getTargetExtractSubreg ( <STR_LIT> , DL , <STR_LIT> , Out64 ) ; } if ( InVT == <STR_LIT> && ResVT == <STR_LIT> ) { SDNode * U64 = DAG . getMachineNode ( TargetOpcode :: IMPLICIT_DEF , DL , <STR_LIT> ) ; SDValue In64 = DAG . getTargetInsertSubreg ( <STR_LIT> , DL , <STR_LIT> , SDValue ( U64 , <NUM_LIT> ) , In ) ; SDValue Out64 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , In64 ) ; if ( Subtarget . hasHighWord ( ) ) return DAG . getTargetExtractSubreg ( <STR_LIT> , DL , <STR_LIT> , Out64 ) ; SDValue Shift = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Out64 , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Shift ) ; } llvm_unreachable ( <STR_LIT>


<s> int length ; int wic_addr0 = <NUM_LIT> * <NUM_LIT> ; int wic_addr1 = <NUM_LIT> * <NUM_LIT> ; int first_addr = INSN_ADDRESSES ( INSN_UID ( first ) ) ; for ( insn = first ; insn ; insn = NEXT_INSN ( insn ) ) if ( INSN_P ( insn ) ) { addr_offset = INSN_ADDRESSES ( INSN_UID ( insn ) ) - first_addr ; length = get_attr_length ( insn ) ; if ( before_4 == <NUM_LIT> && addr_offset + length >= <NUM_LIT> * <NUM_LIT> ) before_4 = insn ; if ( JUMP_P ( insn ) ) return ; if ( before_16 == <NUM_LIT> && addr_offset + length >= <NUM_LIT> * <NUM_LIT> ) before_16 = insn ; if ( CALL_P ( insn ) || tablejump_p ( insn , <NUM_LIT> , <NUM_LIT>


<s> report_fatal_error ( <STR_LIT> + Twine ( FrameSize ) ) ; } if ( FrameSize ) { <ISA_LIT>FunctionInfo * XFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; if ( FP ) { int FPSpillOffset = MFI -> getObjectOffset ( XFI -> getFPSpillSlot ( ) ) ; FPSpillOffset += FrameSize * <NUM_LIT> ; loadFromStack ( MBB , MBBI , <STR_LIT> , FPSpillOffset , dl , TII ) ; } bool restoreLR = XFI -> getUsesLR ( ) ; if ( restoreLR && MFI -> getObjectOffset ( XFI -> getLRSpillSlot ( ) ) != <NUM_LIT> ) { int LRSpillOffset = MFI -> getObjectOffset ( XFI -> getLRSpillSlot ( ) ) ; LRSpillOffset += FrameSize * <NUM_LIT> ; loadFromStack ( MBB , MBBI , <STR_LIT> , LRSpillOffset , dl , TII ) ; restoreLR = false ; } if ( restoreLR ) { assert ( MBBI -> getOpcode ( ) == <STR_LIT> || MBBI ->


<s> if ( isUpdating ) ResTys . push_back ( <STR_LIT> ) ; ResTys . push_back ( <STR_LIT> ) ; SDValue Pred = getAL ( CurDAG ) ; SDValue Reg0 = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; SDNode * VLd ; SmallVector < SDValue , <NUM_LIT> > Ops ; if ( is64BitVector || NumVecs <= <NUM_LIT> ) { unsigned Opc = ( is64BitVector ? DOpcodes [ OpcodeIndex ] : QOpcodes0 [ OpcodeIndex ] ) ; Ops . push_back ( MemAddr ) ; Ops . push_back ( Align ) ; if ( isUpdating ) { SDValue Inc = N -> getOperand ( AddrOpIdx + <NUM_LIT> ) ; Ops . push_back ( isa < ConstantSDNode > ( Inc . getNode ( ) ) ? Reg0 : Inc ) ; } Ops . push_back ( Pred ) ; Ops . push_back ( Reg0 ) ; Ops . push_back ( Chain ) ; VLd = CurDAG -> getMachineNode ( Opc , dl , ResTys , Ops . data ( ) , Ops . size ( ) ) ; } else { EVT AddrTy = MemAddr . getValueType ( ) ; SDValue ImplDef = SDValue ( CurDAG -> getMachineNode ( TargetOpcode :: IMPLICIT_DEF , dl , ResTy ) , <NUM_LIT> ) ; const SDValue OpsA [ ] = { MemAddr , Align , Reg0 , ImplDef , Pred , Reg0 , Chain } ; SDNode * VLdA = CurDAG -> getMachineNode ( QOpcodes0 [ OpcodeIndex ] , dl , ResTy , AddrTy , <STR_LIT> , OpsA , <NUM_LIT> ) ; Chain = SDValue ( VLdA , <NUM_LIT> ) ; Ops . push_back ( SDValue ( VLdA , <NUM_LIT> ) ) ; Ops . push_back ( Align ) ; if (


<s> else if ( regno == <NUM_LIT> ) return NOTR0_REG ; else if ( regno < <NUM_LIT> ) return NOTSP_REG ; else return GENERAL_REGS


<s> while ( insn ) { if ( insn == label ) break ; else insn = NEXT_INSN ( insn ) ; } return ( insn ==


<s> V = rotr32 ( ~ <NUM_LIT> , getT2SOImmValRotate ( V ) ) & V ; if ( V == <NUM_LIT> ) return false ; if ( getT2SOImmVal ( V ) != - <NUM_LIT> ) return true ; V = Imm ; if ( getT2SOImmValSplatVal ( V & <NUM_LIT> ) != - <NUM_LIT> ) V &= ~ <NUM_LIT> ; else if ( getT2SOImmValSplatVal ( V & <NUM_LIT> ) != - <NUM_LIT> ) V &= ~ <NUM_LIT> ; if ( getT2SOImmVal ( V ) != - <NUM_LIT>


<s> StringRef Identifier = Tok . getString ( ) ; if ( <ISA_LIT>Operand * Err = ParseIntelIdentifier ( Val , Identifier , Info , true , End ) ) return Err ; unsigned CVal = <NUM_LIT> ; switch ( OpKind ) { default : llvm_unreachable ( <STR_LIT> ) ; case IOK_LENGTH : CVal = Info . Length ; break ; case IOK_SIZE : CVal = Info . Size ; break ; case IOK_TYPE : CVal = Info . Type ; break ; } unsigned Len = End . getPointer ( ) - TypeLoc .


<s> fprintf ( file , <STR_LIT> ) ; fprintf ( file ,


<s> bool IsStore = ( Instruction :: Store == Opcode ) ; VectorType * SrcVTy = dyn_cast < VectorType > ( SrcTy ) ; if ( ! SrcVTy ) return getMemoryOpCost ( Opcode , SrcTy , Alignment , AddressSpace ) ; unsigned NumElem = SrcVTy -> getVectorNumElements ( ) ; VectorType * MaskTy = VectorType :: get ( Type :: getInt8Ty ( SrcVTy -> getContext ( ) ) , NumElem ) ; if ( ( IsLoad && ! isLegalMaskedLoad ( SrcVTy , MaybeAlign ( Alignment ) ) ) || ( IsStore && ! isLegalMaskedStore ( SrcVTy , MaybeAlign ( Alignment ) ) ) || ! isPowerOf2_32 ( NumElem ) ) { int MaskSplitCost = getScalarizationOverhead ( MaskTy , false , true ) ; int ScalarCompareCost = getCmpSelInstrCost ( Instruction :: ICmp , Type :: getInt8Ty ( SrcVTy -> getContext ( ) ) , nullptr ) ; int BranchCost = getCFInstrCost ( Instruction :: Br ) ; int MaskCmpCost = NumElem * ( BranchCost + ScalarCompareCost ) ; int ValueSplitCost = getScalarizationOverhead ( SrcVTy , IsLoad , IsStore ) ; int MemopCost = NumElem * BaseT :: getMemoryOpCost ( Opcode , SrcVTy -> getScalarType ( ) , Alignment , AddressSpace ) ; return MemopCost + ValueSplitCost + MaskSplitCost + MaskCmpCost ; } std :: pair < int , MVT > LT = TLI -> getTypeLegalizationCost ( DL , SrcVTy ) ; auto VT = TLI -> getValueType ( DL , SrcVTy ) ; int Cost = <NUM_LIT> ; if ( VT . isSimple ( ) && LT . second != VT . getSimpleVT ( ) && LT . second . getVectorNumElements ( ) == NumElem ) Cost += getShuffleCost ( TTI :: SK_PermuteTwoSrc , SrcVTy , <NUM_LIT> , nullptr ) + getShuffleCost ( TTI :: SK_PermuteTwoSrc , MaskTy , <NUM_LIT> , nullptr ) ; else if ( LT . second .


<s> if ( Triple ( TT ) . isOSNaCl ( ) ) return new NaCl<ISA_LIT>AsmBackend ( T , true ) ; return new <ISA_LIT>AsmBackend ( T , Triple ( TT ) . getOS (


<s> } else if ( MO . isImm ( ) && ! TID . OpInfo [ i ] . isPredicate ( ) ) { if ( MO . getImm ( ) > Limit || ( MO . getImm ( ) & ( Scale - <NUM_LIT> ) ) != <NUM_LIT> ) return false ; } } const TargetInstrDesc & NewTID = TII -> get ( Entry . NarrowOpc1 ) ; unsigned PredReg = <NUM_LIT> ; <STR_LIT> Pred = getInstrPredicate ( MI , PredReg ) ; bool SkipPred = false ; if ( Pred != <STR_LIT> ) { if ( ! NewTID . isPredicable ( ) ) return false ; } else { SkipPred = ! NewTID . isPredicable ( ) ; } bool HasCC = false ; bool CCDead = false ; if ( TID . hasOptionalDef ( ) ) { unsigned NumOps = TID . getNumOperands ( ) ; HasCC = ( MI -> getOperand ( NumOps - <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) ; if ( HasCC && MI -> getOperand ( NumOps - <NUM_LIT> ) . isDead ( ) ) CCDead = true ; } if ( ! VerifyPredAndCC ( MI , Entry , false , Pred , LiveCPSR , HasCC , CCDead ) ) return false ; DebugLoc dl = MI -> getDebugLoc ( ) ; MachineInstrBuilder MIB = BuildMI ( MBB , * MI , dl , NewTID ) ; MIB . addOperand ( MI -> getOperand ( <NUM_LIT> ) ) ; if ( NewTID . hasOptionalDef ( ) ) { if ( HasCC ) AddDefaultT1CC ( MIB , CCDead ) ; else AddNoT1CC ( MIB ) ; } unsigned NumOps = TID . getNumOperands ( ) ; for ( unsigned i = <NUM_LIT> , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) { if ( i < NumOps && TID . OpInfo [ i ] . isOptionalDef ( ) ) continue ; if ( ( TID . getOpcode ( ) == <STR_LIT> || TID . getOpcode ( ) == <STR_LIT> ) && i == <NUM_LIT> ) continue ; bool isPred = ( i < NumOps && TID . OpInfo [ i ] . isPredicate ( ) ) ; if ( SkipPred && isPred ) continue ; const MachineOperand & MO = MI -> getOperand ( i ) ; if ( Scale > <NUM_LIT> && ! isPred && MO . isImm ( ) ) MIB . addImm ( MO . getImm ( ) / Scale ) ; else { if ( MO . isReg ( ) && MO . isImplicit ( ) && MO . getReg ( ) == <STR_LIT> ) continue ; MIB . addOperand ( MO ) ; } } if ( ! TID . isPredicable ( ) && NewTID . isPredicable ( ) ) AddDefaultPred ( MIB ) ; DOUT << <STR_LIT> << * MI << <STR_LIT> << * MIB ; MBB . erase ( MI


<s> addPass ( create<ISA_LIT>RelaxMemPass ( ) ) ; addPass ( create<ISA_LIT>ExpandPseudoPass (


<s> val = operands [ <NUM_LIT> ] ; desto = gen_reg_rtx ( Pmode ) ; counto = gen_reg_rtx ( HImode ) ; if ( GET_CODE ( desta ) != REG || REGNO ( desta ) < FIRST_PSEUDO_REGISTER ) desta = copy_to_mode_reg ( Pmode , desta ) ; if ( GET_CODE ( count ) == CONST_INT && GET_CODE ( val ) == CONST_INT && ! ( INTVAL ( count ) & <NUM_LIT> ) && ( INTVAL ( count ) > <NUM_LIT> ) && ( INTVAL ( val )

<= <NUM_LIT> && INTVAL ( val ) >= - <NUM_LIT> ) ) {


<s> } else if ( reg_unused_after ( insn , op [ <NUM_LIT> ] ) && compare_eq_p ( insn ) ) { avr_asm_len ( <STR_LIT> , op , plen , - <NUM_LIT> ) ; } else { avr_out_compare ( insn , op


<s> static bool sparc_hard_regno_mode_ok ( unsigned int


<s> return gen_rtx_REG ( TYPE_MODE ( type )


<s> if ( SDValue Res = tryCombineToEXTR ( N , DCI ) ) return Res ; if ( SDValue Res = tryCombineToBSL ( N , DCI ) ) return Res ; if ( SDValue Res = tryCombineVecOrNot ( N , DCI ) ) return Res ; return SDValue


<s> for ( unsigned i = <NUM_LIT> ; i < PacketSU -> Succs . size ( ) ; ++ i ) { auto & Dep = PacketSU -> Succs [ i ] ; if ( Dep . getSUnit ( ) == PacketSUDep && Dep . getKind ( ) == SDep :: Anti && Dep .


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , ( Rd + <NUM_LIT> ) % <NUM_LIT> , Address , Decoder ) ) ) return MCDisassembler :: Fail ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , ( Rd + <NUM_LIT> ) % <NUM_LIT> , Address , Decoder ) ) ) return MCDisassembler :: Fail ; break ; default : break ; } switch ( Inst . getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , wb , Address , Decoder ) ) ) return MCDisassembler :: Fail ; break ; default : break ; } if ( ! Check ( S , DecodeAddrMode6Operand ( Inst , Rn , Address , Decoder ) ) ) return MCDisassembler :: Fail ; switch ( Inst . getOpcode ( ) ) { default : if ( Rm == <NUM_LIT> ) { Inst . addOperand ( MCOperand :: CreateReg ( <NUM_LIT> ) ) ; break ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> if ( optimize_size || optimize < <NUM_LIT> ) return false ; if ( TARGET_ISA_V3M && ! align_to_4_bytes ) return nds32_expand_setmem_loop_v3m ( dstmem , size , value ) ; if ( nds32_expand_setmem_unroll ( dstmem , size , value , align

, expected_align , expected_size ) ) return true ;


<s> uint64_t Size = initMBBInfo ( ) ; if ( Size <= MaxForwardRange || ! mustRelaxABranch ( ) ) return false ; setWorstCaseAddresses ( )


<s> NeedWait = CNT_MASK ( T ) ; setScoreLB ( T , getScoreUB ( T ) ) ; return NeedWait ; } const int32_t LB = getScoreLB ( T ) ; const int32_t UB = getScoreUB ( T ) ; if ( ( UB >= ScoreToWait ) && ( ScoreToWait >