<s> bool <ISA_LIT>InstrInfo :: shouldClusterMemOps ( MachineInstr & FirstLdSt , unsigned BaseReg1 , MachineInstr & SecondLdSt , unsigned BaseReg2 , unsigned NumLoads ) const { if ( ! memOpsHaveSameBasePtr ( FirstLdSt , BaseReg1 , SecondLdSt , BaseReg2 ) ) return false ; const MachineOperand * FirstDst = nullptr ; const MachineOperand * SecondDst = nullptr ; if ( ( isMUBUF ( FirstLdSt ) && isMUBUF ( SecondLdSt ) ) || ( isMTBUF ( FirstLdSt ) && isMTBUF ( SecondLdSt ) ) || ( isFLAT ( FirstLdSt ) && isFLAT ( SecondLdSt ) ) ) { const unsigned MaxGlobalLoadCluster = <NUM_LIT> ; if ( NumLoads > MaxGlobalLoadCluster ) return false ; FirstDst = getNamedOperand ( FirstLdSt , <STR_LIT> :: vdata ) ; if ( ! FirstDst ) FirstDst = getNamedOperand ( FirstLdSt , <STR_LIT> :: vdst ) ; SecondDst = getNamedOperand ( SecondLdSt , <STR_LIT> :: vdata ) ; if ( ! SecondDst ) SecondDst = getNamedOperand ( SecondLdSt , <STR_LIT> :: vdst ) ; } else if ( isSMRD ( FirstLdSt ) && isSMRD ( SecondLdSt ) ) { FirstDst = getNamedOperand ( FirstLdSt , <STR_LIT> :: sdst ) ; SecondDst = getNamedOperand ( SecondLdSt , <STR_LIT> :: sdst ) ; } else if ( isDS ( FirstLdSt ) && isDS ( SecondLdSt ) ) { FirstDst = getNamedOperand ( FirstLdSt , <STR_LIT> :: vdst ) ; SecondDst = getNamedOperand ( SecondLdSt , <STR_LIT> ::


<s> if ( isSRA16 ( Op ) ) return isSHL16 ( Op . getOperand ( <NUM_LIT> ) ) ; return DAG . ComputeNumSignBits ( Op ) ==


<s> bool <ISA_LIT>MCInstrInfo :: isInnerLoop ( MCInst const & MCI ) { assert ( isBundle ( MCI )


<s> } count = <NUM_LIT> ; } else if ( TARGET_SSSE3 ) count = <NUM_LIT> ; return ix86_vec_cost ( mode , cost -> sse_op * count , true ) ; } else return ix86_vec_cost ( mode , cost -> sse_op , true ) ; } if ( GET_MODE_SIZE ( mode ) > UNITS_PER_WORD ) { if ( constant_op1 ) { if ( op1_val > <NUM_LIT> ) return cost -> shift_const + COSTS_N_INSNS ( <NUM_LIT> ) ; else return cost -> shift_const * <NUM_LIT> ; } else { if ( and_in_op1 ) return cost -> shift_var * <NUM_LIT> ; else return cost -> shift_var * <NUM_LIT> + COSTS_N_INSNS ( <NUM_LIT> ) ; } } else { if ( constant_op1 ) return cost -> shift_const ; else if ( shift_and_truncate ) { if ( skip_op0 ) * skip_op0 = * skip_op1 = true ; return cost


<s> label = ix86_expand_sse_compare_and_jump ( UNLE , TWO52 , xa , false ) ; xa = expand_simple_binop ( mode , PLUS , xa , TWO52 , NULL_RTX , <NUM_LIT> , OPTAB_DIRECT ) ; xa = expand_simple_binop ( mode , MINUS , xa , TWO52 , xa , <NUM_LIT> , OPTAB_DIRECT ) ; ix86_sse_copysign_to_positive ( xa , xa , res , mask ) ; one = force_reg ( mode , const_double_from_real_value ( do_floor ? dconst1 : dconstm1 , mode ) ) ; tmp = ix86_expand_sse_compare_mask ( UNGT , xa


<s> Op -> Mem . RegKind = RegKind ; Op -> Mem . Base = Base ; Op -> Mem . Index = Index ; Op -> Mem . Disp =


<s> if ( ErrorInfo >= Operands . size ( ) ) return Error ( IDLoc , <STR_LIT> ) ; ErrorLoc = ( ( <ISA_LIT>Operand & ) * Operands [ ErrorInfo ] ) . getStartLoc ( ) ; if ( ErrorLoc == SMLoc ( ) ) ErrorLoc = IDLoc ; } return Error ( ErrorLoc , <STR_LIT> ) ; } case Match_MnemonicFail : return Error ( IDLoc , <STR_LIT>


<s> } SmallVector < <STR_LIT> , <NUM_LIT> > Returns ; SmallVector < <STR_LIT> , <NUM_LIT> > Params ; if ( strcmp ( Name , <STR_LIT> ) == <NUM_LIT> ) { WasmSym -> setType ( <STR_LIT> ) ; WasmSym -> setEventType ( { <STR_LIT> , <NUM_LIT> } ) ; WasmSym -> setWeak ( true ) ; WasmSym -> setExternal ( true ) ; Params . push_back ( Subtarget . hasAddr64 ( ) ? <STR_LIT> :: I64 : <STR_LIT> :: I32 ) ; } else { WasmSym -> setType ( <STR_LIT> ) ; getLibcallSignature ( Subtarget , Name , Returns


<s> const TargetRegisterInfo * TRI = MF . getSubtarget ( ) . getRegisterInfo ( ) ; if ( ! MO . isReg ( ) ) return true ; unsigned RegNumber = MO . getReg ( ) ; if ( <STR_LIT> . contains ( RegNumber ) ) RegNumber = TRI -> getSubReg ( RegNumber , ExtraCode [ <NUM_LIT> ] == 'L' ? <STR_LIT> : <STR_LIT> ) ; OS << <ISA_LIT>InstPrinter :: getRegisterName ( RegNumber ) ; return false ; } case 'I' : if ( MI -> getOperand ( OpNo ) . isImm ( ) ) OS << <STR_LIT> ; return false


<s> emit_insn ( gen_ashl ( tmp , idx , GEN_INT ( shift ) ) ) ; if ( ! BYTES_BIG_ENDIAN ) emit_insn ( gen_add ( tmp , tmp , GEN_INT ( <NUM_LIT> ) ) ) ; else emit_insn ( gen_sub ( tmp , GEN_INT ( <NUM_LIT> - width ) , tmp ) ) ; rtx mask = gen_reg_rtx ( V16QImode ) ; rtx mask_v2di = gen_reg_rtx ( V2DImode ) ; rtvec v = rtvec_alloc ( <NUM_LIT> ) ; if ( ! BYTES_BIG_ENDIAN ) { RTVEC_ELT ( v , <NUM_LIT> ) = gen_rtx_CONST_INT ( DImode , <NUM_LIT> ) ; RTVEC_ELT ( v , <NUM_LIT> ) = gen_rtx_CONST_INT ( DImode , mode_mask ) ; } else { RTVEC_ELT ( v , <NUM_LIT> ) = gen_rtx_CONST_INT ( DImode , mode_mask ) ; RTVEC_ELT ( v , <NUM_LIT> ) = gen_rtx_CONST_INT ( DImode , <NUM_LIT> ) ; } emit_insn ( gen_vec_initv2didi ( mask_v2di , gen_rtx_PARALLEL ( V2DImode , v ) ) ) ; rtx sub_mask = simplify_gen_subreg ( V16QImode , mask_v2di , V2DImode , <NUM_LIT> ) ; emit_insn ( gen_rtx_SET ( mask , sub_mask ) ) ; rtx tmp_val = gen_reg_rtx ( SImode ) ; if ( inner_mode == E_SFmode ) if ( TARGET_DIRECT_MOVE_64BIT ) emit_insn ( gen_movsi_from_sf ( tmp_val , val ) ) ; else { rtx stack = rs6000_allocate_stack_temp ( SFmode , false , true ) ; emit_insn ( gen_movsf_hardfloat ( stack , val ) ) ; rtx stack2 = copy_rtx ( stack ) ; PUT_MODE ( stack2 , SImode ) ; emit_move_insn ( tmp_val , stack2 ) ; } else tmp_val = force_reg ( SImode , val ) ; rtx val_v16qi = gen_reg_rtx ( V16QImode ) ; rtx val_v2di = gen_reg_rtx ( V2DImode ) ; rtvec vec_val = rtvec_alloc ( <NUM_LIT> ) ; if ( ! BYTES_BIG_ENDIAN ) { RTVEC_ELT ( vec_val , <NUM_LIT> ) = gen_rtx_CONST_INT ( DImode , <NUM_LIT> ) ; RTVEC_ELT ( vec_val , <NUM_LIT> ) = tmp_val ; } else { RTVEC_ELT ( vec_val , <NUM_LIT> ) = tmp_val ; RTVEC_ELT ( vec_val , <NUM_LIT> ) = gen_rtx_CONST_INT ( DImode , <NUM_LIT> ) ; } emit_insn ( gen_vec_initv2didi ( val_v2di , gen_rtx_PARALLEL ( V2DImode , vec_val ) ) ) ; rtx sub_val = simplify_gen_subreg ( V16QImode , val_v2di , V2DImode , <NUM_LIT> ) ; emit_insn ( gen_rtx_SET ( val_v16qi , sub_val ) ) ; rtx pcv = gen_reg_rtx ( V16QImode ) ; emit_insn ( gen_lvsl ( pcv , tmp ) ) ; rtx val_perm = gen_reg_rtx ( V16QImode ) ; rtx mask_perm = gen_reg_rtx ( V16QImode


<s> bool <ISA_LIT>InstrInfo :: isIndirectCall ( const MachineInstr * MI ) const { switch ( MI -> getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; } return false


<s> assert ( Op . getSimpleValueType ( ) . isVector ( ) && <STR_LIT> ) ; return LowerVectorCTPOP ( Op , Subtarget


<s> bool isPacketStart ( ) const { return ( packetStart


<s> MCObjectWriter * llvm :: create<ISA_LIT>ELFObjectWriter ( raw_pwrite_stream & OS , uint8_t OSABI , bool IsLittleEndian , bool IsILP32 ) { MCELFObjectTargetWriter * MOTW = new <ISA_LIT>ELFObjectWriter ( OSABI , IsLittleEndian , IsILP32 ) ; return createELFObjectWriter ( MOTW , OS ,


<s> static DecodeStatus DecodeBranchTarget7MM ( MCInst & Inst , unsigned Offset , uint64_t Address , const MCDisassembler * Decoder ) { int32_t BranchOffset = SignExtend32 < <NUM_LIT> > ( Offset << <NUM_LIT> ) ; Inst . addOperand ( MCOperand :: createImm ( BranchOffset ) ) ; return MCDisassembler


<s> return __builtin_aarch64_sminv4si ( __a ,


<s> static DecodeStatus s4_3ImmDecoder ( MCInst & MI , unsigned tmp , uint64_t , const void * Decoder ) { signedDecoder < <NUM_LIT> > ( MI , tmp , Decoder ) ; return MCDisassembler ::


<s> static std :: unique_ptr < <ISA_LIT>Operand > CreatePrefix ( unsigned Prefixes , SMLoc StartLoc , SMLoc EndLoc ) { auto Res = llvm :: make_unique < <ISA_LIT>Operand > ( Prefix , StartLoc , EndLoc ) ; Res -> Pref .


<s> void <ISA_LIT>InstrInfo :: loadRegFromStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned DestReg , int FrameIndex , const TargetRegisterClass * RC

, const TargetRegisterInfo * TRI ) const {


<s> Inst . setOpcode ( <STR_LIT> ) ; Inst . addOperand ( MCOperand :: CreateReg ( ShadowRegI8 ) ) ; const MCExpr * Disp = MCConstantExpr :: Create ( kShadowOffset , Ctx ) ; std :: unique_ptr < <ISA_LIT>Operand > Op ( <STR_LIT> ( <NUM_LIT> , Disp , ShadowRegI64 , <NUM_LIT> , <NUM_LIT> , SMLoc ( ) , SMLoc ( ) ) ) ; Op -> addMemOperands ( Inst , <NUM_LIT> ) ; EmitInstruction ( Out , Inst ) ; } EmitInstruction ( Out , MCInstBuilder ( <STR_LIT> ) . addReg ( ShadowRegI8 ) . addReg ( ShadowRegI8 ) ) ; MCSymbol * DoneSym = Ctx . CreateTempSymbol ( ) ; const MCExpr * DoneExpr = MCSymbolRefExpr :: Create ( DoneSym , Ctx ) ; EmitInstruction ( Out , MCInstBuilder ( <STR_LIT> ) . addExpr ( DoneExpr ) ) ; EmitInstruction ( Out , MCInstBuilder ( <STR_LIT> ) . addReg ( ScratchRegI32 ) . addReg ( AddressRegI32 ) ) ; EmitInstruction ( Out , MCInstBuilder ( <STR_LIT> ) . addReg ( ScratchRegI32 ) . addReg ( ScratchRegI32 ) . addImm ( <NUM_LIT> ) ) ; switch ( AccessSize


<s> assert ( I != MBB -> end ( ) && <STR_LIT> ) ; Offset += TII -> getInstSizeInBytes ( * I ) ; } return


<s> ItaniumMangler Mangler ( true ) ; ParamIterator I ( Leads , manglingRules [ FuncId ] ) ; Param P ; while ( ( P = I . getNextParam ( ) ) . ArgType != <NUM_LIT> ) Mangler ( S , P ) ; return S . str


<s> MCInstrInfo * X = new MCInstrInfo ( ) ; Init<ISA_LIT>MCInstrInfo (


<s> void <ISA_LIT>InstructionSelector :: renderTruncImm32 ( MachineInstrBuilder & MIB , const MachineInstr & MI , int OpIdx ) const { assert ( MI . getOpcode ( ) == TargetOpcode :: G_CONSTANT && OpIdx ==


<s> bool IsTrivialInst ( MachineInstr & MI ) const { switch ( MI . getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> auto F = DeadMap . find ( { Reg , <NUM_LIT> } ) ; if ( F == DeadMap . end ( ) ) return false ; for ( auto & DR : F -> second ) if ( DR . contains ( FIR ) ) return true ; return false ; } ; for ( unsigned Reg : RC -> getRawAllocationOrder ( MF ) ) { bool Dead = true ; for ( auto R : <ISA_LIT>BlockRanges :: expandToSubRegs ( { Reg , <NUM_LIT> } , MRI , HRI ) ) { if ( isDead ( R . Reg ) ) continue ; Dead = false


<s>
void
<ISA_LIT>InstPrinter
::
printOpConstantVarOps
(
const
MCInst
*
MI
,
unsigned
StartIndex
,
raw_ostream
&
O
)
{
O
<<
' '
;
if
(
MI
->
getNumOperands
(
)
StartIndex
==
<NUM_LIT>
)
{
uint64_t
Imm
=
MI
->
getOperand
(
StartIndex
)
.
getImm
(
)
;
Imm
|=
(
MI
->
getOperand
(
StartIndex
+
<NUM_LIT>
)
.
getImm
(
)
<<
<NUM_LIT>
)
;
O
<<
Imm
;
}
else


<s> case 'o' : case 'v' : default : return true ; case 'm' : if ( ! SelectAddr ( Op . getNode ( ) , Op , Op0 , Op1


<s> unsigned const4 = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned s1 = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned is32Bit = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; if ( ! is32Bit ) return MCDisassembler :: Fail ; DecodeStatus status = DecodeDataRegsRegisterClass ( Inst , s1 , Address , Decoder ) ; if ( status != MCDisassembler :: Success ) return status ; Inst . addOperand ( MCOperand :: createImm ( const4


<s> flag_schedule_insns_after_reload = <NUM_LIT> ; flag_split_wide_types = <NUM_LIT> ; } if ( mn10300_tune_string ) { if ( strcasecmp ( mn10300_tune_string , <STR_LIT> ) == <NUM_LIT> ) mn10300_tune_cpu = PROCESSOR_MN10300 ; else if ( strcasecmp ( mn10300_tune_string , <STR_LIT>


<s> return <ISA_LIT>ABIInfo ( ABI :: EABI )


<s> if ( ! GAN ) return true ; const GlobalValue * GV = GAN -> getGlobal ( ) ; unsigned Alignment = GV -> getAlignment ( ) ; const DataLayout * DL = TLI -> getDataLayout ( ) ; if ( Alignment == <NUM_LIT> && ! Subtarget -> isTargetDarwin ( ) ) Alignment = DL -> getABITypeAlignment ( GV -> getType ( ) -> getElementType ( ) ) ; if ( Alignment >= Size ) return true ; } if ( CurDAG -> isBaseWithConstantOffset ( N ) ) { if ( ConstantSDNode * RHS = dyn_cast < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) ) ) { int64_t RHSC = ( int64_t ) RHS -> getZExtValue ( ) ; unsigned Scale = Log2_32 ( Size ) ; if ( ( RHSC & ( Size - <NUM_LIT> ) ) == <NUM_LIT> && RHSC >= <NUM_LIT> && RHSC < ( <NUM_LIT> << Scale ) ) { Base = N . getOperand ( <NUM_LIT> ) ; if ( Base . getOpcode ( ) == <STR_LIT> ) { int FI = cast < FrameIndexSDNode > ( Base ) -> getIndex ( ) ; Base = CurDAG -> getTargetFrameIndex ( FI , TLI -> getPointerTy ( ) ) ; } OffImm = CurDAG -> getTargetConstant ( RHSC >> Scale , <STR_LIT> ) ; return true ; } } } if ( SelectAddrModeUnscaled ( N , Size , Base


<s> for ( auto Op : Node -> operands ( ) ) if ( Op -> getNumOperands ( ) ) Printf . push_back ( Printf . getDocument ( ) -> getNode ( cast < MDString > ( Op -> getOperand ( <NUM_LIT> ) )


<s> if ( I . getFlag ( MachineInstr :: MIFlag :: NoSWrap ) && canUseNSW ( NewOpcode ) && getSymbolicOperandRequirements ( OperandCategory :: DecorationOperand , Decoration :: NoSignedWrap , ST ) . isSatisfiable ) buildOpDecorate ( Target , I

, TII , Decoration :: NoSignedWrap , { } ) ;


<s> unsigned BestGrowth = ~ <NUM_LIT> ; for ( water_iterator IP = std :: prev ( WaterList . end ( ) ) , B = WaterList . begin ( ) ; ; -- IP ) { MachineBasicBlock * WaterBB = * IP ; unsigned Growth ; if ( isWaterInRange ( UserOffset , WaterBB , U , Growth ) && ( WaterBB -> getNumber ( ) < U . HighWaterMark -> getNumber ( ) || NewWaterList . count ( WaterBB ) ) && Growth < BestGrowth ) { BestGrowth = Growth ; WaterIter = IP ; DEBUG ( dbgs ( ) << <STR_LIT> << WaterBB -> getNumber ( ) << <STR_LIT> << Growth << '\n' ) ; if ( BestGrowth == <NUM_LIT>


<s> if ( getLexer ( ) . isNot ( AsmToken :: Identifier ) ) { Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; return true ; } StringRef IDVal = Parser . getTok ( ) . getIdentifier ( ) ; if ( IDVal == <STR_LIT> ) { RefKind = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_LO16 ; } else if ( IDVal == <STR_LIT> ) { RefKind = <ISA_LIT>MCExpr


<s> return getSubExpr ( ) -> findAssociatedFragment


<s> int64x2_t result ; __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT> ( b ) : ) ; return result


<s> return new <ISA_LIT>PassConfig ( this ,


<s> TargetRegistry :: RegisterMCSubtargetInfo ( * T , <ISA_LIT>_MC :: create<ISA_LIT>MCSubtargetInfo ) ; TargetRegistry :: RegisterMCInstrAnalysis ( * T , create<ISA_LIT>MCInstrAnalysis ) ; TargetRegistry :: RegisterMCCodeEmitter ( * T , create<ISA_LIT>MCCodeEmitter ) ; TargetRegistry :: RegisterCOFFStreamer ( * T , create<ISA_LIT>WinCOFFStreamer ) ; TargetRegistry :: RegisterMCInstPrinter ( * T , create<ISA_LIT>MCInstPrinter ) ; TargetRegistry :: RegisterMCRelocationInfo ( * T , create<ISA_LIT>MCRelocationInfo ) ; } TargetRegistry :: RegisterMCAsmBackend ( The<ISA_LIT>_32Target ,


<s> return ; } if ( isa < ConstantStruct > ( CPV ) ) { if ( CPV -> getNumOperands ( ) ) { StructType * ST = cast < StructType > ( CPV -> getType ( ) ) ; for ( unsigned i = <NUM_LIT> , e = CPV -> getNumOperands ( ) ; i != e ; ++ i ) { if ( i == ( e - <NUM_LIT> ) ) Bytes = TD -> getStructLayout ( ST ) -> getElementOffset ( <NUM_LIT> ) + TD -> getTypeAllocSize ( ST ) - TD -> getStructLayout ( ST ) -> getElementOffset ( i ) ; else Bytes = TD -> getStructLayout ( ST ) -> getElementOffset ( i + <NUM_LIT> ) - TD -> getStructLayout


<s> if ( crtl -> calls_eh_return ) { for ( i = <NUM_LIT> ; ; ++ i ) { unsigned regno = EH_RETURN_DATA_REGNO ( i ) ; if ( regno == INVALID_REGNUM ) break ; imask |= <NUM_LIT> << regno ; } } if ( imask || fmask || alpha_ra_ever_killed ( ) ) imask |= ( <NUM_LIT> << REG_RA ) ; * imaskP =


<s> if ( offset >= insn -> bytes . size ( ) ) return true ; byte = insn -> bytes


<s> getExprForDwarfGlobalReference ( const GlobalValue * GV , Mangler * Mang , MachineModuleInfo * MMI , unsigned Encoding , MCStreamer & Streamer ) const { if ( Encoding & ( DW_EH_PE_indirect | DW_EH_PE_pcrel ) ) { const MCSymbol * Sym = Mang -> getSymbol ( GV ) ; const MCExpr * Res = MCSymbolRefExpr :: Create ( Sym , MCSymbolRefExpr :: VK_GOTPCREL , getContext ( ) ) ; const MCExpr * Four = MCConstantExpr :: Create ( <NUM_LIT> , getContext ( ) ) ; return MCBinaryExpr :: CreateAdd ( Res , Four , getContext (


<s> unsigned <ISA_LIT>TargetELFStreamer :: getEFlags ( ) { switch ( STI . getTargetTriple ( ) . getArch ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case Triple :: r600 : return getEFlags<ISA_LIT> ( ) ; case Triple :: amdgcn : return getEFlagsAMDGCN (


<s> SDValue LHS = N -> getOperand ( <NUM_LIT> ) ; SDValue RHS = N -> getOperand ( <NUM_LIT> ) ; if ( LHS . getOpcode ( ) == <STR_LIT> && RHS . getOpcode ( ) == <STR_LIT> ) { SDValue Src = LHS . getOperand ( <NUM_LIT> ) ; if ( Src != RHS . getOperand ( <NUM_LIT> ) ) return SDValue ( ) ; const ConstantSDNode * CLHS = dyn_cast < ConstantSDNode > ( LHS . getOperand (


<s> else { rtx par = gen_rtx_PARALLEL ( VOIDmode , rs6000_const_vec ( mode ) ) ; return gen_rtx_VEC_SELECT ( mode , source ,


<s> eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { if ( ! hasReservedCallFrame ( MF ) ) { int64_t Amount = I -> getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( I -> getOpcode ( ) == <STR_LIT> ) Amount


<s> TRI -> splitReg ( DstReg , DstLoReg , DstHiReg ) ; buildMI ( MBB , MBBI , <STR_LIT> ) . addReg ( DstLoReg , RegState :: Define | getDeadRegState ( DstIsDead ) ) . addReg ( DstHiReg ) ; buildMI ( MBB , MBBI , <STR_LIT> ) . addReg ( DstLoReg , RegState :: Define | getDeadRegState ( DstIsDead ) ) . addReg ( DstLoReg , getKillRegState ( DstIsKill ) ) ; auto MI0 = buildMI ( MBB , MBBI , <STR_LIT> ) . addReg ( DstLoReg , RegState :: Define | getDeadRegState ( DstIsDead ) ) . addReg ( DstLoReg , getKillRegState ( DstIsKill ) ) . addImm ( <NUM_LIT> ) ; MI0 -> getOperand ( <NUM_LIT> ) . setIsDead ( ) ; auto MIBHI = buildMI ( MBB , MBBI , <STR_LIT> ) . addReg ( DstHiReg , RegState :: Define | getDeadRegState ( DstIsDead ) ) . addReg ( DstHiReg , getKillRegState ( DstIsKill ) ) . addReg ( DstHiReg , getKillRegState ( DstIsKill ) ) ; if ( ImpIsDead ) MIBHI -> getOperand ( <NUM_LIT> ) . setIsDead ( ) ; MI . eraseFromParent ( ) ; return


<s> const Function & F = MF . getFunction ( ) ; SmallPtrSet < MachineBasicBlock * , <NUM_LIT> > JumpTableTargets ; if ( auto * JTI = MF . getJumpTableInfo ( ) ) for ( auto & JTE : JTI -> getJumpTables ( ) ) for ( auto * MBB : JTE . MBBs ) JumpTableTargets . insert ( MBB ) ; bool MadeChange = false ; for ( MachineBasicBlock & MBB : MF ) { bool CouldCall = false , CouldJump


<s> if ( AT == <NUM_LIT> ) reportParseError ( Loc , <STR_LIT> ) ; return AT


<s> DEBUG ( dbgs ( ) << <STR_LIT> << F . getName ( ) << <STR_LIT> ) ; RelooperAlgorithm R ; std :: map < const BasicBlock * , Block * > BB2B ; std :: map < const Block * , const BasicBlock * > B2BB ; for ( const BasicBlock & BB : F ) { Block * B = new Block ( BB . getName ( ) . str ( ) . data ( ) , nullptr ) ; R . AddBlock ( B ) ; assert ( BB2B . find ( & BB ) == BB2B . end ( ) && <STR_LIT> ) ; assert ( B2BB . find ( B ) == B2BB . end ( ) && <STR_LIT> ) ; BB2B [ & BB ] = B ; B2BB [ B ] = & BB ; } for ( Block * B : R . Blocks ) { const BasicBlock * BB = B2BB [ B


<s> assert ( lsb <= msb && <STR_LIT> ) ; for ( uint32_t i = lsb ; i <= msb ; ++ i ) Val |= ( <NUM_LIT> << i ) ; return ~


<s> DataFlowGraph G ( MF , HII , HRI , * MDT , MDF , HAI , TOI ) ; G . build ( ) ; if ( RDFDump ) dbgs ( ) << <STR_LIT> << MF . getName ( ) << '\n' << PrintNode < FuncNode * > ( G . getFunc ( ) , G ) << '\n' ; <ISA_LIT>CP CP ( G ) ; CP . trace ( RDFDump ) ; Changed = CP . run ( ) ; if ( RDFDump ) dbgs ( ) << <STR_LIT> << MF . getName ( ) << '\n' << PrintNode < FuncNode * > ( G . getFunc ( ) , G ) << '\n' ; <ISA_LIT>DCE DCE ( G , * MRI


<s> case <STR_LIT> : switch ( RetVT . getSimpleVT ( ) . SimpleTy ) { default : return NULL ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; } break ; case <STR_LIT> : switch ( RetVT . getSimpleVT ( ) . SimpleTy ) { default : return NULL ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; } break ; } } else { switch ( N -> getOpcode ( ) ) { default : return NULL ; case <STR_LIT> : switch ( RetVT . getSimpleVT ( ) . SimpleTy ) { default : return NULL ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; } break ; case <STR_LIT> : switch ( RetVT . getSimpleVT ( ) . SimpleTy ) { default : return NULL ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT>


<s> TargetRegistry :: RegisterMCDisassembler ( getThe<ISA_LIT>Target (


<s> if ( arg0 == error_mark_node ) return const0_rtx ; if ( target == <NUM_LIT> || GET_MODE ( target ) != tmode || ! ( * insn_data [ icode ] . operand [ <NUM_LIT> ] . predicate ) ( target , tmode ) ) target = gen_reg_rtx ( tmode ) ; if ( ! ( * insn_data [ icode ] . operand [ <NUM_LIT> ] . predicate ) ( op0 , mode0 ) ) op0 = copy_to_mode_reg ( mode0 , op0 ) ; scratch1 = gen_reg_rtx ( mode0 ) ; scratch2 = gen_reg_rtx ( mode0 ) ; pat = GEN_FCN ( icode ) ( target , op0 , scratch1 , scratch2 ) ; if ( ! pat ) return <NUM_LIT> ; emit_insn ( pat ) ; return


<s> unsigned SubRegs = VRC -> getSize ( ) / <NUM_LIT> ; SmallVector < unsigned , <NUM_LIT> > SRegs ; for ( unsigned i = <NUM_LIT> ; i < SubRegs ; ++ i ) { unsigned SGPR = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * UseMI . getParent ( ) , UseMI , UseMI . getDebugLoc ( ) , get ( <STR_LIT> ) , SGPR ) . addReg ( SrcReg , <NUM_LIT> , RI . getSubRegFromChannel ( i ) ) ; SRegs . push_back ( SGPR ) ; } MachineInstrBuilder MIB = BuildMI ( * UseMI . getParent ( ) , UseMI , UseMI . getDebugLoc ( ) , get ( <STR_LIT> ) , DstReg ) ; for ( unsigned i = <NUM_LIT> ; i < SubRegs ; ++


<s> AU . addPreserved < DominatorTreeWrapperPass > ( ) ; AU . addRequired < LegacyDivergenceAnalysis > ( ) ; AU . addRequired < TargetPassConfig > (


<s> if ( RegVT == <STR_LIT> ) RC = Subtarget -> in<ISA_LIT>16Mode ( ) ? & <STR_LIT> : & <STR_LIT> ; else if ( RegVT == <STR_LIT> ) RC = & <STR_LIT> ; else if ( RegVT == <STR_LIT> ) RC = & <STR_LIT> ; else if ( RegVT == <STR_LIT> ) RC = Has<ISA_LIT>64 ? & <STR_LIT> : & <STR_LIT> ; else llvm_unreachable ( <STR_LIT> ) ; unsigned Reg = AddLiveIn ( DAG . getMachineFunction ( ) , ArgReg , RC ) ; SDValue ArgValue = DAG . getCopyFromReg ( Chain , dl , Reg , RegVT ) ; if ( VA . getLocInfo ( ) != CCValAssign :: Full ) { unsigned Opcode = <NUM_LIT> ; if ( VA . getLocInfo ( ) == CCValAssign :: SExt ) Opcode = <STR_LIT> ; else if ( VA . getLocInfo ( ) == CCValAssign :: ZExt ) Opcode = <STR_LIT> ; if ( Opcode ) ArgValue = DAG . getNode ( Opcode , dl , RegVT , ArgValue , DAG . getValueType ( ValVT ) ) ; ArgValue = DAG . getNode ( <STR_LIT> , dl , ValVT , ArgValue ) ; } if ( ( RegVT == <STR_LIT> && ValVT == <STR_LIT> ) || ( RegVT == <STR_LIT> && ValVT == <STR_LIT> ) ) ArgValue = DAG . getNode ( <STR_LIT> , dl , ValVT , ArgValue ) ; else if ( IsO32 && RegVT == <STR_LIT> && ValVT == <STR_LIT> ) { unsigned Reg2 = AddLiveIn ( DAG . getMachineFunction ( ) , getNextIntArgReg ( ArgReg ) , RC ) ; SDValue ArgValue2 = DAG . getCopyFromReg ( Chain , dl , Reg2 , RegVT ) ; if ( ! Subtarget -> isLittle ( ) ) std :: swap ( ArgValue , ArgValue2 ) ; ArgValue = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , ArgValue , ArgValue2 ) ; } InVals . push_back ( ArgValue ) ; } else { assert ( VA . isMemLoc ( ) ) ; int FI = MFI -> CreateFixedObject ( ValVT . getSizeInBits ( ) / <NUM_LIT> , VA . getLocMemOffset ( ) , true ) ; SDValue FIN = DAG . getFrameIndex ( FI , getPointerTy ( ) ) ; InVals . push_back ( DAG . getLoad ( ValVT , dl , Chain , FIN , MachinePointerInfo :: getFixedStack ( FI ) , false , false , false , <NUM_LIT> ) ) ; } } if ( DAG . getMachineFunction ( ) . getFunction ( ) -> hasStructRetAttr ( ) ) { unsigned Reg = <ISA_LIT>FI -> getSRetReturnReg ( ) ; if ( !


<s> MachineInstr * I = SUI -> getInstr ( ) ; assert ( I && SUJ -> getInstr ( )


<s> if ( ( RegNo & <NUM_LIT> ) || RegNo == <NUM_LIT> ) S = MCDisassembler :: SoftFail ; unsigned RegisterPair = GPRPairDecoderTable [ RegNo / <NUM_LIT> ] ; Inst . addOperand ( MCOperand :: createReg (


<s> std :: unique_ptr < MCObjectWriter > llvm :: create<ISA_LIT>ELFObjectWriter ( raw_pwrite_stream & OS , uint8_t OSABI ) { auto MOTW = llvm :: make_unique < <ISA_LIT>ELFObjectWriter > ( OSABI ) ; return createELFObjectWriter ( std :: move ( MOTW


<s> const MCConstantExpr * MCE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; if ( ! MCE ) return false ; int64_t Val = MCE -> getValue ( ) ; return ( Val >= <NUM_LIT> && Val


<s> Value * ArgPtr ; if ( DoShiftOpt ) { ArgPtr = Builder . CreateConstInBoundsGEP1_64 ( KernArgSegment , AlignDownOffset , Arg . getName ( ) + <STR_LIT> ) ; ArgPtr = Builder . CreateBitCast ( ArgPtr , Builder . getInt32Ty ( ) -> getPointerTo ( AS ) , ArgPtr -> getName ( ) + <STR_LIT> ) ; } else { ArgPtr = Builder . CreateConstInBoundsGEP1_64 ( KernArgSegment , EltOffset , Arg . getName ( ) + <STR_LIT> ) ; ArgPtr = Builder . CreateBitCast ( ArgPtr , ArgTy -> getPointerTo ( AS ) , ArgPtr -> getName ( ) + <STR_LIT> ) ; } if ( IsV3 && Size >= <NUM_LIT> ) { V4Ty = VectorType :: get ( VT -> getVectorElementType ( ) , <NUM_LIT> ) ; ArgPtr = Builder . CreateBitCast ( ArgPtr , V4Ty -> getPointerTo ( AS ) ) ; } LoadInst * Load = Builder . CreateAlignedLoad ( ArgPtr , AdjustedAlign ) ; Load -> setMetadata ( LLVMContext :: MD_invariant_load , MDNode :: get ( Ctx , { } ) ) ; MDBuilder MDB ( Ctx ) ; if ( isa < PointerType > ( ArgTy ) ) { if ( Arg . hasNonNullAttr ( ) ) Load -> setMetadata ( LLVMContext :: MD_nonnull , MDNode :: get ( Ctx , { } ) ) ; uint64_t DerefBytes = Arg . getDereferenceableBytes ( ) ; if ( DerefBytes != <NUM_LIT> ) { Load -> setMetadata ( LLVMContext :: MD_dereferenceable , MDNode :: get ( Ctx , MDB . createConstant ( ConstantInt :: get ( Builder . getInt64Ty ( ) , DerefBytes ) ) ) ) ; } uint64_t DerefOrNullBytes = Arg . getDereferenceableOrNullBytes ( ) ; if ( DerefOrNullBytes != <NUM_LIT> ) { Load -> setMetadata ( LLVMContext :: MD_dereferenceable_or_null , MDNode :: get ( Ctx , MDB . createConstant ( ConstantInt :: get ( Builder . getInt64Ty ( ) , DerefOrNullBytes ) ) ) ) ; } unsigned ParamAlign = Arg . getParamAlignment ( ) ; if ( ParamAlign != <NUM_LIT> ) { Load -> setMetadata ( LLVMContext :: MD_align , MDNode :: get ( Ctx , MDB . createConstant ( ConstantInt :: get ( Builder . getInt64Ty ( ) , ParamAlign ) ) ) ) ; } } if ( DoShiftOpt ) { Value * ExtractBits = OffsetDiff == <NUM_LIT> ? Load : Builder . CreateLShr ( Load , OffsetDiff * <NUM_LIT> ) ; IntegerType * ArgIntTy = Builder . getIntNTy ( Size ) ; Value * Trunc = Builder . CreateTrunc ( ExtractBits , ArgIntTy ) ; Value * NewVal = Builder . CreateBitCast ( Trunc , ArgTy , Arg . getName ( ) + <STR_LIT> ) ; Arg . replaceAllUsesWith ( NewVal ) ; } else if ( IsV3 ) { Value * Shuf = Builder . CreateShuffleVector ( Load , UndefValue :: get ( V4Ty ) , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , Arg . getName ( ) + <STR_LIT> ) ; Arg . replaceAllUsesWith


<s> if ( TLI . SimplifyDemandedBits ( SDValue ( N , <NUM_LIT> ) , APInt :: getAllOnes ( NumBits ) , DCI )


<s> return std :: distance ( std :: begin ( Data ) , llvm :: find_or_fail


<s> return parseNamedBit ( <STR_LIT> , Operands


<s> if ( F -> getAttributes ( ) . hasAttribute ( Idx , Attribute :: ByVal ) || F -> getAttributes ( ) . hasAttribute ( Idx , Attribute :: InReg ) || F -> getAttributes ( ) . hasAttribute ( Idx , Attribute :: StructRet ) || F -> getAttributes ( ) . hasAttribute ( Idx , Attribute :: SwiftSelf ) || F -> getAttributes ( ) . hasAttribute ( Idx , Attribute :: SwiftError ) || F -> getAttributes ( ) . hasAttribute ( Idx , Attribute :: Nest ) ) return false ; Type * ArgTy = Arg . getType ( ) ; if ( ArgTy -> isStructTy ( ) || ArgTy -> isArrayTy ( ) ) return false ; EVT ArgVT = TLI . getValueType ( DL , ArgTy ) ; if ( ! ArgVT . isSimple ( ) ) return false ; MVT VT = ArgVT . getSimpleVT ( ) . SimpleTy ; if ( VT . isFloatingPoint ( ) && ! Subtarget -> hasFPARMv8 ( ) ) return false ; if ( VT . isVector ( ) && ( ! Subtarget -> hasNEON ( ) || ! Subtarget -> isLittleEndian ( ) ) ) return false ; if ( VT >= <STR_LIT> && VT <= <STR_LIT> ) ++ GPRCnt ; else if ( ( VT >= <STR_LIT> && VT <= <STR_LIT> ) || VT . is64BitVector ( ) || VT . is128BitVector ( ) ) ++ FPRCnt ; else return false ; if ( GPRCnt > <NUM_LIT> || FPRCnt > <NUM_LIT> ) return false ; } static const MCPhysReg Registers [ <NUM_LIT> ] [ <NUM_LIT> ] = { { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } } ; unsigned GPRIdx = <NUM_LIT> ; unsigned FPRIdx = <NUM_LIT> ; for ( auto const & Arg : F -> args ( ) ) { MVT VT = TLI . getSimpleValueType ( DL , Arg . getType ( ) ) ; unsigned SrcReg ; const TargetRegisterClass * RC ; if ( VT >= <STR_LIT> && VT <= <STR_LIT> ) { SrcReg = Registers [ <NUM_LIT> ] [ GPRIdx ++ ] ; RC = & <STR_LIT> ; VT =


<s> void LLVMInitializePowerPCAsmPrinter ( ) { TargetRegistry :: RegisterAsmPrinter ( The<ISA_LIT>32Target ,


<s> inline vector signed int vec_vsubsws ( vector signed int a1


<s> MachineFunction & MF = DAG . getMachineFunction ( ) ; CCState CCInfo ( CallConv , IsVarArg , MF , RVLocs , * DAG . getContext ( ) ) ; <ISA_LIT>CC <ISA_LIT>CCInfo ( CallConv , Subtarget , CCInfo ) ; <ISA_LIT>CCInfo . analyzeReturn ( Outs , Subtarget . abiUsesSoftFloat ( ) , MF . getFunction ( ) -> getReturnType ( ) ) ; SDValue Flag ; SmallVector < SDValue , <NUM_LIT> > RetOps ( <NUM_LIT> , Chain ) ; for ( unsigned i = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i ) { SDValue Val = OutVals [ i ] ; CCValAssign & VA = RVLocs [ i ] ; assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; if ( RVLocs [ i ] . getValVT ( ) != RVLocs [ i ] . getLocVT ( ) ) Val = DAG . getNode ( <STR_LIT> , DL , RVLocs [ i ] . getLocVT ( ) , Val ) ; Chain = DAG . getCopyToReg ( Chain , DL , VA . getLocReg ( ) , Val , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( VA . getLocReg ( ) , VA . getLocVT ( ) ) ) ; } if ( MF . getFunction ( ) -> hasStructRetAttr ( ) ) { <ISA_LIT>FunctionInfo * <ISA_LIT>FI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; unsigned Reg = <ISA_LIT>FI -> getSRetReturnReg ( ) ; if ( ! Reg ) llvm_unreachable ( <STR_LIT> ) ; SDValue Val = DAG . getCopyFromReg ( Chain , DL , Reg , getPointerTy ( ) ) ; unsigned V0 = Subtarget . isABI_N64 ( ) ? <STR_LIT> : <STR_LIT> ; Chain = DAG . getCopyToReg ( Chain , DL , V0 , Val , Flag ) ; Flag = Chain .


<s> if ( <STR_LIT> . contains ( DstReg , SrcReg ) ) { MI . setDesc ( MII . get (


<s> bool <ISA_LIT>TargetLowering :: isMemOpHasNoClobberedMemOperand ( const SDNode * N ) const { const MemSDNode * MemNode = cast < MemSDNode > ( N ) ; const Value * Ptr = MemNode -> getMemOperand ( ) -> getValue ( ) ; const Instruction * I = dyn_cast_or_null < Instruction > ( Ptr ) ; return I && I ->


<s> void <ISA_LIT>AsmPrinter :: printOperand ( const MachineInstr * MI , int OpNo , raw_ostream & O ) { const MachineOperand & MO = MI -> getOperand ( OpNo ) ; switch ( MO . getTargetFlags ( ) ) { case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; } switch ( MO . getType ( ) ) { case MachineOperand :: MO_Register : O << <ISA_LIT>InstPrinter :: getRegisterName ( MO . getReg ( ) ) ; break ; case MachineOperand :: MO_Immediate : O << MO . getImm ( ) ; break ; case MachineOperand :: MO_GlobalAddress : O << * getSymbol ( MO . getGlobal ( ) ) ; break ; default : llvm_unreachable (


<s> uint32x2_t result ; __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) : ) ; return


<s> void <ISA_LIT>TargetObjectFile :: Initialize ( MCContext & Ctx , const TargetMachine & TM ) { TargetLoweringObjectFileWasm :: Initialize (


<s> int <ISA_LIT>ConstantPoolSymbol :: getExistingMachineCPValue ( MachineConstantPool * CP , unsigned Alignment ) { unsigned AlignMask = Alignment - <NUM_LIT> ; const std :: vector < MachineConstantPoolEntry > Constants = CP -> getConstants ( ) ; for ( unsigned i = <NUM_LIT> , e = Constants . size ( ) ; i != e ; ++ i ) { if ( Constants [ i ] . isMachineConstantPoolEntry ( ) && ( Constants [ i ] . getAlignment ( ) & AlignMask ) == <NUM_LIT> ) { <ISA_LIT>ConstantPoolValue * CPV = ( <ISA_LIT>ConstantPoolValue * ) Constants [ i ] . Val . MachineCPVal ; <ISA_LIT>ConstantPoolSymbol * APS = dyn_cast <


<s> SDValue PtrOff = DAG . getNode ( <STR_LIT> , DL , getPointerTy ( DAG . getDataLayout ( ) ) , StackPtr , DAG . getIntPtrConstant ( Offset , DL ) ) ; return DAG . getStore ( Chain , DL , Arg , PtrOff , MachinePointerInfo ( ) ) ; } MachineFrameInfo & MFI = DAG . getMachineFunction ( ) . getFrameInfo ( ) ; int FI = MFI . CreateFixedObject ( Arg . getValueSizeInBits ( ) / <NUM_LIT> , Offset , false ) ; SDValue FIN = DAG . getFrameIndex ( FI , getPointerTy ( DAG .


<s> bool Modified = false ; MachineBasicBlock :: instr_iterator MII = MBB . instr_begin ( ) , E = MBB . instr_end ( ) ; MachineBasicBlock :: instr_iterator NextMII ; for ( ; MII != E ;


<s> unsigned NumElts = VT . getVectorNumElements ( ) ; ShuffleMask . push_back ( <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i < NumElts ; i ++ ) ShuffleMask


<s> <ISA_LIT>Kernel ( ) { curSize = <NUM_LIT> ; curRSize = <NUM_LIT> ; curHWSize = <NUM_LIT>


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT>


<s> unsigned DWord3 = MRI . createVirtualRegister ( & AMDGPU :: SGPR_32RegClass ) ; BuildMI ( * MBB , MI , MI -> getDebugLoc ( ) , get ( AMDGPU :: S_MOV_B32 ) , DWord1 ) . addImm ( <NUM_LIT> ) ; BuildMI ( * MBB , MI , MI -> getDebugLoc ( ) , get ( AMDGPU :: S_MOV_B32 ) , DWord2 ) . addImm ( AMDGPU :: RSRC_DATA_FORMAT & <NUM_LIT> ) ; BuildMI ( * MBB , MI , MI -> getDebugLoc ( ) , get ( AMDGPU :: S_MOV_B32 ) , DWord3 ) . addImm ( AMDGPU :: RSRC_DATA_FORMAT >> <NUM_LIT> ) ; BuildMI ( * MBB , MI , MI -> getDebugLoc ( ) , get ( AMDGPU :: REG_SEQUENCE ) , SRsrc ) . addReg ( DWord0 ) . addImm ( AMDGPU :: sub0 ) . addReg ( DWord1 ) . addImm ( AMDGPU :: sub1 ) . addReg ( DWord2 ) . addImm ( AMDGPU :: sub2 ) . addReg ( DWord3 ) . addImm ( AMDGPU :: sub3 ) ; MI -> setDesc ( get ( NewOpcode ) ) ; if ( MI -> getOperand ( <NUM_LIT> ) . isReg ( ) ) { MI -> getOperand ( <NUM_LIT> ) . setReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; } else { MI -> getOperand ( <NUM_LIT> ) . ChangeToRegister ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) , false ) ; } MI -> getOperand ( <NUM_LIT> ) . setReg ( SRsrc ) ; MI -> addOperand ( * MBB -> getParent ( ) , MachineOperand :: CreateImm ( ImmOffset ) ) ; const TargetRegisterClass * NewDstRC = RI . getRegClass ( get ( NewOpcode ) . OpInfo [ <NUM_LIT> ] . RegClass ) ; unsigned DstReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned NewDstReg = MRI . createVirtualRegister ( NewDstRC ) ; MRI . replaceRegWith ( DstReg , NewDstReg ) ; break ; } case AMDGPU :: S_LOAD_DWORDX8_IMM : case AMDGPU :: S_LOAD_DWORDX8_SGPR : { MachineInstr * Lo , * Hi ; splitSMRD ( MI , & AMDGPU :: SReg_128RegClass , AMDGPU :: S_LOAD_DWORDX4_IMM , AMDGPU :: S_LOAD_DWORDX4_SGPR , Lo , Hi ) ; MI -> eraseFromParent ( ) ; moveSMRDToVALU ( Lo , MRI ) ; moveSMRDToVALU ( Hi , MRI ) ; break ; } case AMDGPU :: S_LOAD_DWORDX16_IMM : case AMDGPU :: S_LOAD_DWORDX16_SGPR : { MachineInstr * Lo , *


<s> } else if ( const auto * MS = dyn_cast < MemSetInst > ( I ) ) { ConstantInt * C = dyn_cast < ConstantInt > ( MS -> getLength ( ) ) ; if ( ! C ) return - <NUM_LIT> ; const unsigned Size = C -> getValue ( ) . getZExtValue ( ) ; const Align DstAlign = * MS -> getDestAlign ( ) ; MOp = MemOp :: Set ( Size , false , DstAlign , false , false ) ; DstAddrSpace = MS -> getDestAddressSpace ( ) ; } else llvm_unreachable ( <STR_LIT> ) ; unsigned Limit , Factor = <NUM_LIT> ; switch ( I -> getIntrinsicID ( ) ) { case <STR_LIT> : Limit = TLI -> getMaxStoresPerMemcpy ( F -> hasMinSize ( ) ) ; break ; case <STR_LIT> : Limit = TLI -> getMaxStoresPerMemmove ( F -> hasMinSize ( ) ) ; break ; case <STR_LIT> : Limit = TLI -> getMaxStoresPerMemset ( F -> hasMinSize ( )


<s> rtx clob = gen_rtx_CLOBBER ( VOIDmode , gen_rtx_REG ( CCmode , FLAGS_REG ) ) ; tmp = gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( <NUM_LIT> , tmp


<s> unsigned MOVE = ABI . GetGPRMoveOp ( ) ; if ( hasFP ( MF ) ) { MachineBasicBlock :: iterator I = MBBI ; for ( unsigned i = <NUM_LIT> ; i < MFI . getCalleeSavedInfo ( ) . size ( ) ; ++ i ) -- I ; BuildMI ( MBB , I , DL , TII . get ( MOVE ) , SP ) . addReg ( FP ) . addReg ( ZERO ) ; } if ( <ISA_LIT>FI -> callsEhReturn ( ) ) { const TargetRegisterClass * RC = ABI . ArePtrs64bit ( ) ? & <STR_LIT> : & <STR_LIT> ; MachineBasicBlock :: iterator I = MBBI ; for ( unsigned i = <NUM_LIT> ; i < MFI . getCalleeSavedInfo ( ) . size ( ) ; ++ i ) -- I ; for ( int J = <NUM_LIT> ; J < <NUM_LIT> ; ++ J ) { TII . loadRegFromStackSlot ( MBB , I , ABI . GetEhDataReg ( J ) , <ISA_LIT>FI -> getEhDataRegFI ( J ) , RC , & RegInfo ) ; } } if ( MF . getFunction ( ) . hasFnAttribute ( <STR_LIT> ) ) emitInterruptEpilogueStub ( MF , MBB ) ; uint64_t StackSize = MFI . getStackSize ( ) ; if ( !


<s> emit_insn ( gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( <NUM_LIT> , gen_rtx_SET ( VOIDmode , copy_rtx ( operands [ <NUM_LIT> ] ) , gen_rtx_fmt_ee ( code , mode , copy_rtx ( operands [ <NUM_LIT> ] ) , operands [ <NUM_LIT> ] ) ) , gen_rtx_CLOBBER ( VOIDmode , gen_rtx_SCRATCH ( QImode ) ) ) ) ) ; return true


<s> extern __inline __m256d __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) _mm256_i32gather_pd ( double const * base , __m128i index , const int scale ) { __v4df zero = _mm256_setzero_pd


<s> static inline MachineOperand t1CondCodeOp ( bool isDead =


<s> Relocator :: Size <ISA_LIT>Relocator :: getSize ( Relocation :: Type pType ) const { return ApplyFunctions [ pType ] .


<s> PHINode * PN = nullptr ; if ( F . getReturnType ( ) -> isVoidTy ( ) ) { ReturnInst :: Create ( F . getContext ( ) , nullptr , NewRetBlock ) ; } else { PN = PHINode :: Create ( F . getReturnType ( ) , ReturningBlocks . size ( ) , <STR_LIT> ) ; NewRetBlock -> getInstList ( ) . push_back ( PN ) ; ReturnInst :: Create ( F . getContext ( ) , PN , NewRetBlock ) ; } for ( BasicBlock * BB : ReturningBlocks ) { if ( PN ) PN -> addIncoming ( BB -> getTerminator (


<s> unsigned EltSize = VT . getScalarSizeInBits ( ) ; if ( EltSize >= <NUM_LIT> || ShuffleVectorSDNode :: isSplatMask ( & M [ <NUM_LIT> ] , VT ) || ShuffleVectorInst :: isIdentityMask ( M ) || isVREVMask ( M , VT , <NUM_LIT> ) || isVREVMask ( M , VT , <NUM_LIT> ) || isVREVMask ( M , VT , <NUM_LIT> ) ) return true ; else if ( Subtarget -> hasNEON ( ) && ( isVEXTMask ( M , VT , ReverseVEXT , Imm ) || isVTBLMask ( M , VT ) || isNEONTwoResultShuffleMask ( M , VT ,

WhichResult , isV_UNDEF ) ) ) return true ;


<s> static bool DecodeSymbolicOperand ( MCInst & Inst , uint64_t Address , uint64_t Value ,


<s> BitVector <ISA_LIT>RegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; Reserved . set ( <STR_LIT>


<s> static SDValue lowerV16F32VectorShuffle ( SDValue Op , SDValue V1 , SDValue V2 , const <ISA_LIT>Subtarget & Subtarget , SelectionDAG & DAG ) { SDLoc DL ( Op ) ; assert ( V1 . getSimpleValueType ( ) == <STR_LIT> && <STR_LIT> ) ; assert ( V2 . getSimpleValueType ( ) == <STR_LIT> && <STR_LIT> ) ; ShuffleVectorSDNode * SVOp = cast < ShuffleVectorSDNode > ( Op ) ; ArrayRef < int > Mask = SVOp -> getMask ( ) ; assert ( Mask . size ( ) == <NUM_LIT> && <STR_LIT> ) ; if ( SDValue Unpck = lowerVectorShuffleWithUNPCK ( DL , <STR_LIT> , Mask , V1 , V2 , DAG ) ) return Unpck ; return lowerVectorShuffleWithPERMV ( DL , <STR_LIT> , Mask , V1 ,


<s> std :: vector < const SUnit * > makeGCNILPScheduler ( ArrayRef < const SUnit * > BotRoots , const ScheduleDAG & DAG ) { GCNILPScheduler S ; return S . schedule ( BotRoots ,


<s> return MF -> getFunction ( ) -> getCallingConv ( ) == CallingConv :: CXX_FAST_TLS && MF -> getFunction ( ) -> hasFnAttribute ( Attribute


<s> bool <ISA_LIT>DAGToDAGISel :: MatchAddressBase ( SDValue N , <ISA_LIT>ISelAddressMode & AM ) { if ( AM . BaseType != <ISA_LIT>ISelAddressMode :: RegBase || AM . Base . Reg . getNode ( ) ) { return true ; } AM . BaseType = <ISA_LIT>ISelAddressMode :: RegBase ; AM . Base . Reg =


<s> HABaseType Base = HA_UNKNOWN ; uint64_t Members = <NUM_LIT> ; bool result = isHomogeneousAggregate ( Ty , Base , Members ) ; DEBUG ( dbgs ( ) << <STR_LIT> << result << <STR_LIT> ; Ty -> dump ( ) ; dbgs ( ) << <STR_LIT> ) ; return result


<s> } auto * cptr = std :: get < constant > ( * idx ) . val ; if ( cptr -> getValue ( ) . getActiveBits ( ) > <NUM_LIT>


<s> SDValue Ops [ ] = { Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , DAG . getConstant ( CompareOpc , dl , <STR_LIT> ) } ; EVT VTs [ ] = { Op . getOperand ( <NUM_LIT> ) . getValueType ( ) , <STR_LIT> } ; SDValue CompNode = DAG . getNode ( <STR_LIT> , dl , VTs , Ops ) ; SDValue Flags = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getRegister ( <STR_LIT> , <STR_LIT> ) , CompNode . getValue ( <NUM_LIT> ) ) ; unsigned BitNo ; bool InvertBit ; switch ( cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ) { default : case <NUM_LIT> : BitNo = <NUM_LIT> ; InvertBit = false ; break ; case <NUM_LIT> : BitNo = <NUM_LIT> ; InvertBit = true ; break ; case <NUM_LIT> : BitNo = <NUM_LIT> ; InvertBit = false ; break ; case <NUM_LIT> : BitNo = <NUM_LIT> ; InvertBit = true ; break ; } Flags = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Flags , DAG . getConstant ( <NUM_LIT> - ( <NUM_LIT> - BitNo ) , dl , <STR_LIT> ) ) ; Flags = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Flags , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; if ( InvertBit ) Flags = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Flags , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; return Flags


<s> bool <ISA_LIT>LowerControlFlow :: skipIfDead ( MachineInstr & MI , MachineBasicBlock & NextBB ) { MachineBasicBlock & MBB = * MI . getParent ( ) ; MachineFunction * MF = MBB . getParent ( ) ; if ( MF -> getFunction ( ) -> getCallingConv ( ) != CallingConv :: <ISA_LIT>_PS || ! shouldSkip ( & MBB , & MBB . getParent ( ) -> back ( ) ) ) return false ; MachineBasicBlock * SkipBB = insertSkipBlock ( MBB ,


<s> SDLoc dl ( V . getNode ( ) ) ; SDValue VLo = DAG . getAnyExtOrTrunc ( V , dl , <STR_LIT> ) ; SDValue VHi = DAG . getAnyExtOrTrunc ( DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , V , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) , dl , <STR_LIT> ) ; SDValue RegClass = DAG . getTargetConstant ( <STR_LIT> , dl , <STR_LIT> ) ; SDValue SubReg0 = DAG . getTargetConstant (


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case


<s> bool IsUnscaled = TII -> isUnscaledLdSt ( LoadI ) ; assert ( IsUnscaled == TII -> isUnscaledLdSt ( StoreI ) && <STR_LIT> ) ; assert ( LoadSize <= StoreSize && <STR_LIT> ) ; int UnscaledLdOffset = IsUnscaled ? getLdStOffsetOp ( LoadI ) . getImm ( ) : getLdStOffsetOp ( LoadI ) . getImm ( ) * LoadSize ; int UnscaledStOffset = IsUnscaled ? getLdStOffsetOp ( StoreI ) . getImm ( ) : getLdStOffsetOp ( StoreI ) . getImm ( ) * StoreSize ; int Width = LoadSize * <NUM_LIT> ; int Immr = <NUM_LIT> * ( UnscaledLdOffset - UnscaledStOffset ) ; int Imms = Immr + Width - <NUM_LIT> ; unsigned DestReg = IsStoreXReg ? TRI -> getMatchingSuperReg ( LdRt , <STR_LIT> , & <STR_LIT> ) : LdRt ; assert ( ( UnscaledLdOffset >= UnscaledStOffset && ( UnscaledLdOffset + LoadSize ) <= UnscaledStOffset + StoreSize ) && <STR_LIT> ) ; Immr = <NUM_LIT> * ( UnscaledLdOffset - UnscaledStOffset ) ; Imms = Immr + Width - <NUM_LIT> ; if ( UnscaledLdOffset == UnscaledStOffset ) { uint32_t AndMaskEncoded = ( ( IsStoreXReg ? <NUM_LIT> : <NUM_LIT> ) << <NUM_LIT> ) | ( ( Immr ) << <NUM_LIT> ) | ( ( Imms ) << <NUM_LIT> ) ; BitExtMI = BuildMI ( * LoadI -> getParent ( ) , LoadI , LoadI -> getDebugLoc ( ) , TII -> get ( IsStoreXReg ? <STR_LIT> : <STR_LIT> ) , DestReg ) . addReg ( StRt , getKillRegState ( StRtIsKill ) ) . addImm ( AndMaskEncoded ) ; } else { BitExtMI = BuildMI ( * LoadI -> getParent ( ) , LoadI , LoadI -> getDebugLoc ( ) , TII -> get ( IsStoreXReg ? <STR_LIT> : <STR_LIT> ) , DestReg ) . addReg ( StRt , getKillRegState ( StRtIsKill ) ) . addImm ( Immr ) . addImm ( Imms ) ; } } ( void ) BitExtMI ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; DEBUG ( StoreI -> print ( dbgs ( ) ) ) ; DEBUG ( dbgs (


<s> bool requiresFrameIndexScavenging ( const MachineFunction & MF ) const override { return


<s> Type * ElmTy = cast < ArrayType > ( Ty ) -> getElementType ( ) ; bool exploreArr = ! CheckIfFlattendType ( ElmTy ) || ! AccessMemFormFlatStruct ; if ( isa < StructType > ( ElmTy ) || ( isa < ArrayType > ( ElmTy ) && exploreArr ) ) { int NumArrElems = cast < ArrayType > ( Ty ) -> getNumElements ( ) ; NumElems += NumArrElems * getNumElements ( ElmTy , AccessMemFormFlatStruct ) ; } else NumElems += exploreArr ? cast < ArrayType > ( Ty ) -> getNumElements ( ) : <NUM_LIT> ; } else if ( isa < PointerType >


<s> static rtx s390_function_and_libcall_value ( machine_mode mode , const_tree ret_type , const_tree fntype_or_decl , bool outgoing ATTRIBUTE_UNUSED ) { if ( ret_type ) { int unsignedp = TYPE_UNSIGNED ( ret_type ) ; mode = promote_function_mode ( ret_type , mode , & unsignedp , fntype_or_decl , <NUM_LIT> ) ; } gcc_assert ( GET_MODE_CLASS ( mode ) == MODE_INT || SCALAR_FLOAT_MODE_P ( mode


<s> const DataLayout * getDataLayout ( ) const override


<s> if ( ! Ty . isVector ( ) ) return Ty ; return <STR_LIT> ( Ty . getSizeInBits ( )


<s> void <ISA_LIT>Z80RegisterInfo :: splitReg ( unsigned Reg , unsigned & LoReg , unsigned & HiReg ) const { assert ( <STR_LIT> . contains ( Reg ) && <STR_LIT> ) ; LoReg = getSubReg ( Reg , <STR_LIT> ) ; HiReg = getSubReg ( Reg , <STR_LIT>


<s> setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand


<s> LabelInst . addOperand ( MCOperand :: createReg ( MAI -> getOrCreateMBBRegister ( MBB ) ) ) ; outputMCInst ( LabelInst )


<s> if ( ( VT == <STR_LIT> || VT == <STR_LIT> ) && Subtarget . hasAVX512 ( ) && ! Subtarget . hasBWI ( ) ) return TypeSplitVector ; if ( VT . getVectorNumElements ( ) != <NUM_LIT> && VT . getVectorElementType

( ) != <STR_LIT> ) return TypeWidenVector ;


<s> unsigned NumLoBits = Op . getOperand ( <NUM_LIT> ) . getValueType ( ) . getVectorNumElements ( ) ; Known . Zero . setBitsFrom ( NumLoBits ) ; break ; } case <STR_LIT> : case <STR_LIT> : { SDValue Src = Op . getOperand ( <NUM_LIT> ) ; EVT SrcVT = Src . getValueType ( ) ; APInt DemandedElt = APInt :: getOneBitSet ( SrcVT . getVectorNumElements ( ) , Op . getConstantOperandVal ( <NUM_LIT> ) ) ; DAG . computeKnownBits ( Src , Known , DemandedElt , Depth + <NUM_LIT> ) ; Known = Known . zextOrTrunc ( BitWidth ) ; Known . Zero . setBitsFrom ( SrcVT . getScalarSizeInBits ( ) ) ; break ; } case <STR_LIT> : case <STR_LIT> : { if ( auto * ShiftImm = dyn_cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) ) { if ( ShiftImm -> getAPIntValue ( ) . uge ( VT . getScalarSizeInBits ( ) ) ) { Known . setAllZero ( ) ; break ; } DAG . computeKnownBits ( Op . getOperand ( <NUM_LIT> ) , Known , DemandedElts , Depth + <NUM_LIT> ) ; unsigned ShAmt = ShiftImm -> getZExtValue ( ) ; if ( Opc == <STR_LIT> ) { Known . Zero <<= ShAmt ; Known . One <<= ShAmt ; Known . Zero . setLowBits ( ShAmt ) ; } else { Known . Zero . lshrInPlace ( ShAmt ) ; Known . One . lshrInPlace


<s> bool Done = false ; if ( ! Addr . hasOneUse ( ) ) { unsigned Opcode = Addr . getOpcode ( ) ; if ( Opcode != <STR_LIT> && Opcode != <STR_LIT> ) { for ( SDNode :: use_iterator UI = Addr . getNode ( ) -> use_begin ( ) , UE = Addr . getNode ( ) -> use_end ( ) ; UI != UE ; ++ UI ) { if ( UI -> getOpcode ( ) == <STR_LIT> ) { MatchAddressBase ( Addr , AM ) ; Done = true ; break ; } } } } if ( ! Done && MatchAddress ( Addr , AM , false ) ) return false ; DOUT ( llvm :: dbgs ( ) << <STR_LIT> ; DEBUG ( AM . dump ( ) ) ; EVT VT = Addr . getValueType ( ) ; if ( AM . BaseType


<s> Align getStackAlignment ( ) const { return stackAlignment


<s> default : llvm_unreachable ( <STR_LIT> ) ; case CallingConv :: C : case CallingConv :: Fast : return LowerCCCArguments ( Chain , CallConv , isVarArg ,


<s> printOperand ( MI , opNum + <NUM_LIT> ) ; O <<


<s> if ( N -> isMachineOpcode ( ) ) return ; SelectCode ( N


<s> Lex ( ) ; const MCExpr * Value ; if ( Parser . parseExpression ( Value ) ) { TokError ( <STR_LIT> ) ; Parser . eatToEndOfStatement ( ) ; return false ; } if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) { TokError ( <STR_LIT> ) ; Parser . eatToEndOfStatement ( )


<s> std :: string cloneVarName = Var ; std :: string cloneFnName = getCloneFnName ( Fn ) ; cloneVarName . replace ( cloneVarName . find ( Fn ) , Fn . length (


<s> return Opc == <STR_LIT> || isT1i32Store ( Opc )


<s> static std :: string computeDataLayout ( StringRef TT , StringRef CPU , const TargetOptions & Options , bool isLittle ) { std :: string Ret = <STR_LIT> ; <ISA_LIT>ABIInfo ABI = <ISA_LIT>ABIInfo :: computeTargetABI ( Triple ( TT ) , CPU , Options . MCOptions ) ; if ( isLittle ) Ret +=


<s> if ( VecWidth != <NUM_LIT> && VecTy -> getElementType ( ) -> isFloatingPointTy ( ) ) return false ; } unsigned EltWidth = DataTy -> getScalarSizeInBits ( ) ; return ( EltWidth == <NUM_LIT> && Alignment >= <NUM_LIT> ) || ( EltWidth == <NUM_LIT> && Alignment >= <NUM_LIT> ) ||


<s> return ( * It ) . isImplicitDef ( ) ; } llvm_unreachable ( <STR_LIT> ) ; return


<s> assert ( MI . getOperand ( OpNo ) . isReg ( ) ) ; unsigned RegBits = getMachineOpValue ( MI , MI . getOperand ( OpNo )


<s> return false ; } switch ( p_attr -> attr_type ) { case aarch64_attr_custom : gcc_assert ( p_attr -> handler ) ; if ( ! p_attr -> handler ( arg ) ) return false ; break ; case aarch64_attr_bool : { struct cl_decoded_option decoded ; generate_option ( p_attr -> opt_num , NULL , ! invert , CL_TARGET , & decoded ) ; aarch64_handle_option ( & global_options , & global_options_set , & decoded , input_location ) ; break ; } case aarch64_attr_mask : { struct cl_decoded_option decoded ; decoded . opt_index = p_attr -> opt_num ; decoded . value = ! invert ; aarch64_handle_option ( & global_options , & global_options_set , & decoded , input_location ) ; break ; } case aarch64_attr_enum : { gcc_assert ( arg ) ; bool valid ; int value ; valid = opt_enum_arg_to_value ( p_attr -> opt_num , arg , & value , CL_TARGET ) ; if ( valid ) { set_option ( & global_options , NULL , p_attr -> opt_num , value , NULL , DK_UNSPECIFIED , input_location , global_dc ) ; } else { error ( <STR_LIT> , str_to_check , arg ) ; } break ; } default : gcc_unreachable ( ) ; } } return found


<s> static bool mips_lwxs_address_p ( rtx addr ) { if ( ISA_HAS_LWXS && GET_CODE ( addr ) == PLUS && REG_P ( XEXP ( addr , <NUM_LIT> ) ) ) { rtx offset = XEXP ( addr , <NUM_LIT> ) ; if ( GET_CODE ( offset ) == MULT && REG_P ( XEXP ( offset , <NUM_LIT> ) ) && CONST_INT_P ( XEXP ( offset , <NUM_LIT> ) ) && INTVAL ( XEXP ( offset , <NUM_LIT> ) ) == <NUM_LIT> ) return true ; } return


<s> void <ISA_LIT>PassConfig :: addEarlyCSEOrGVNPass ( ) { if ( getOptLevel ( ) == CodeGenOpt :: Aggressive ) addPass ( createGVNPass (


<s> for ( MachineBasicBlock :: iterator I = BB . begin ( ) ; I != BB . end ( ) ; ++ I ) { MachineInstr & MI = * I ; uint64_t Flags = MI . getDesc ( ) . TSFlags ; unsigned FPInstClass = Flags & <STR_LIT> ; if ( MI . isInlineAsm ( ) ) FPInstClass = <STR_LIT> ; if ( MI . isCopy ( ) && isFPCopy ( MI ) ) FPInstClass = <STR_LIT> ; if ( MI . isImplicitDef ( ) && <STR_LIT> . contains ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ) FPInstClass = <STR_LIT> ; if ( MI . isCall ( ) ) FPInstClass = <STR_LIT> ; if ( FPInstClass == <STR_LIT> ) continue ; MachineInstr * PrevMI = nullptr ; if ( I != BB . begin ( ) ) PrevMI = & * std :: prev ( I ) ; ++ NumFP ; DEBUG ( dbgs ( ) << <STR_LIT> << MI ) ; SmallVector < unsigned , <NUM_LIT> > DeadRegs ; for ( unsigned i = <NUM_LIT> , e = MI . getNumOperands ( ) ; i != e ; ++ i ) { const MachineOperand & MO = MI . getOperand ( i ) ; if ( MO . isReg ( ) && MO . isDead ( ) ) DeadRegs . push_back ( MO . getReg ( ) ) ; } switch ( FPInstClass ) { case <STR_LIT> : handleZeroArgFP ( I ) ; break ; case <STR_LIT> : handleOneArgFP ( I ) ; break ; case <STR_LIT> : handleOneArgFPRW ( I ) ; break ; case <STR_LIT> : handleTwoArgFP ( I ) ; break ; case <STR_LIT> : handleCompareFP ( I ) ; break ; case <STR_LIT> : handleCondMovFP ( I ) ; break ; case <STR_LIT> : handleSpecialFP ( I ) ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } for ( unsigned i = <NUM_LIT> , e = DeadRegs . size ( ) ; i != e ; ++ i ) { unsigned Reg = DeadRegs [ i ] ; static_assert ( <STR_LIT> - <STR_LIT> == <NUM_LIT> , <STR_LIT> ) ; if ( Reg >= <STR_LIT> && Reg <= <STR_LIT> && isLive ( Reg - <STR_LIT> ) ) { DEBUG ( dbgs ( ) << <STR_LIT> << Reg - <STR_LIT> << <STR_LIT> ) ; freeStackSlotAfter ( I , Reg - <STR_LIT> ) ; } } DEBUG ( { MachineBasicBlock :: iterator PrevI =


<s> return GuaranteedTailCallOpt && canGuaranteeTCO (


<s> case <STR_LIT> : Alignment = <NUM_LIT> ; break ; case <STR_LIT> : Alignment = <NUM_LIT> ; break ; case <STR_LIT> : Alignment = <NUM_LIT> ; break ; default : return nullptr ; } if ( Ops . size ( ) == <NUM_LIT> && Ops [ <NUM_LIT> ] == <NUM_LIT> && Ops [ <NUM_LIT> ] == <NUM_LIT> ) { unsigned NewOpc = <NUM_LIT> ; switch ( MI . getOpcode ( ) ) { default : return nullptr ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; } MI . setDesc ( get ( NewOpc ) ) ; MI . getOperand ( <NUM_LIT> ) . ChangeToImmediate ( <NUM_LIT> ) ; } else if ( Ops . size ( ) != <NUM_LIT> ) return nullptr ; if ( LoadMI . getOperand ( <NUM_LIT> ) . getSubReg ( ) != MI . getOperand ( Ops [ <NUM_LIT> ] ) . getSubReg ( ) ) return nullptr ; SmallVector < MachineOperand , <STR_LIT> > MOs ; switch ( LoadMI . getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { if ( MF . getTarget ( ) . getCodeModel ( ) != CodeModel :: Small && MF . getTarget ( ) . getCodeModel ( ) != CodeModel :: Kernel ) return nullptr ; unsigned PICBase = <NUM_LIT> ; if ( MF . getTarget ( ) . isPositionIndependent ( ) ) { if ( Subtarget . is64Bit ( ) ) PICBase = <STR_LIT> ; else return nullptr ; } MachineConstantPool & MCP = * MF . getConstantPool ( ) ; Type * Ty ; unsigned Opc = LoadMI . getOpcode ( ) ; if ( Opc == <STR_LIT> ) Ty = Type :: getFloatTy ( MF . getFunction ( ) ->


<s> const uint64_t F = MCID . TSFlags ; return ( ( F >>


<s> MachineInstr * <ISA_LIT>InstrInfo :: buildMovInstr ( MachineBasicBlock * MBB , MachineBasicBlock

:: iterator I , unsigned DstReg , unsigned SrcReg ) const {


<s> return TargetTriple . isWindowsCygwinEnvironment


<s> case MCCFIInstruction :: OpOffset : { unsigned Reg1 = MRI . getLLVMRegNum ( Inst . getRegister ( ) , true ) ; if ( i + <NUM_LIT> == e ) return CU :: UNWIND_ARM64_MODE_DWARF ; const MCCFIInstruction & Inst2 = Instrs [ ++ i ] ; if ( Inst2 . getOperation ( ) != MCCFIInstruction :: OpOffset ) return CU :: UNWIND_ARM64_MODE_DWARF ; unsigned Reg2 = MRI . getLLVMRegNum ( Inst2 . getRegister ( ) , true ) ; Reg1 = getXRegFromWReg ( Reg1 ) ; Reg2 = getXRegFromWReg ( Reg2 ) ; if ( Reg1 == <STR_LIT> && Reg2 == <STR_LIT> && ( CompactUnwindEncoding & <NUM_LIT> ) == <NUM_LIT> ) CompactUnwindEncoding |= CU :: UNWIND_ARM64_FRAME_X19_X20_PAIR ; else if ( Reg1 == <STR_LIT> && Reg2 == <STR_LIT> && ( CompactUnwindEncoding & <NUM_LIT> ) == <NUM_LIT> ) CompactUnwindEncoding |= CU :: UNWIND_ARM64_FRAME_X21_X22_PAIR ; else if ( Reg1 == <STR_LIT> && Reg2 == <STR_LIT> && ( CompactUnwindEncoding & <NUM_LIT> ) == <NUM_LIT> ) CompactUnwindEncoding |= CU :: UNWIND_ARM64_FRAME_X23_X24_PAIR ; else if ( Reg1 == <STR_LIT> && Reg2 == <STR_LIT> && ( CompactUnwindEncoding & <NUM_LIT> ) == <NUM_LIT> ) CompactUnwindEncoding |= CU :: UNWIND_ARM64_FRAME_X25_X26_PAIR ; else if ( Reg1 == <STR_LIT> && Reg2 == <STR_LIT> && ( CompactUnwindEncoding & <NUM_LIT> ) == <NUM_LIT> ) CompactUnwindEncoding |= CU :: UNWIND_ARM64_FRAME_X27_X28_PAIR ; else { Reg1 = getDRegFromBReg (


<s> InVals . push_back ( DAG . getLoad ( PartVA . getValVT ( ) , DL , Chain , Address , MachinePointerInfo ( ) ) ) ; ++ i ; } continue ; } InVals . push_back ( ArgValue ) ; } if ( IsVarArg ) { ArrayRef < MCPhysReg > ArgRegs = makeArrayRef ( ArgGPRs ) ; unsigned Idx = CCInfo . getFirstUnallocated ( ArgRegs ) ; const TargetRegisterClass * RC = & <STR_LIT> ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; MachineRegisterInfo & RegInfo = MF . getRegInfo ( ) ; <ISA_LIT>MachineFunctionInfo * RVFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; int VaArgOffset , VarArgsSaveSize ; if ( ArgRegs . size ( ) == Idx ) { VaArgOffset = CCInfo . getNextStackOffset ( ) ; VarArgsSaveSize = <NUM_LIT> ; } else { VarArgsSaveSize = XLenInBytes * ( ArgRegs . size ( ) - Idx ) ; VaArgOffset = - VarArgsSaveSize ; } int FI = MFI . CreateFixedObject ( XLenInBytes , VaArgOffset , true ) ; RVFI -> setVarArgsFrameIndex ( FI ) ; if ( Idx % <NUM_LIT> ) { FI = MFI . CreateFixedObject ( XLenInBytes , VaArgOffset - ( int ) XLenInBytes , true ) ; VarArgsSaveSize += XLenInBytes ; } for ( unsigned I = Idx ; I < ArgRegs . size ( ) ; ++ I , VaArgOffset += XLenInBytes ) { const unsigned Reg = RegInfo . createVirtualRegister ( RC ) ; RegInfo . addLiveIn ( ArgRegs [ I ] , Reg ) ; SDValue ArgValue = DAG . getCopyFromReg ( Chain , DL , Reg , XLenVT ) ; FI = MFI . CreateFixedObject ( XLenInBytes , VaArgOffset , true ) ; SDValue PtrOff = DAG . getFrameIndex ( FI , getPointerTy ( DAG . getDataLayout ( ) ) ) ; SDValue Store = DAG . getStore ( Chain , DL , ArgValue , PtrOff , MachinePointerInfo :: getFixedStack ( MF , FI ) ) ; cast < StoreSDNode > ( Store . getNode ( ) ) -> getMemOperand ( ) -> setValue ( ( Value * ) nullptr ) ; OutChains . push_back (


<s> bool <ISA_LIT>DAGToDAGISel :: SelectCMP_SWAP ( SDNode * N ) { unsigned Opcode ; EVT MemTy = cast < MemSDNode > ( N ) -> getMemoryVT ( ) ; if ( Subtarget -> hasLSE ( ) ) return false ; if ( MemTy == <STR_LIT> ) Opcode = <STR_LIT> ; else if ( MemTy == <STR_LIT> ) Opcode = <STR_LIT> ; else if ( MemTy == <STR_LIT> ) Opcode = <STR_LIT> ; else if ( MemTy == <STR_LIT> ) Opcode = <STR_LIT> ; else llvm_unreachable ( <STR_LIT> )


<s> bool isSPVFP = <STR_LIT> . contains ( RegM ) ; RegM = II -> getRegisterInfo ( ) . getEncodingValue ( RegM ) ; if ( ! isSPVFP ) { Binary |= ( RegM & <NUM_LIT> ) ; Binary |= ( ( RegM & <NUM_LIT> ) >> <NUM_LIT> ) << <STR_LIT> ; } else { Binary |= ( ( RegM & <NUM_LIT> ) >> <NUM_LIT> ) ; Binary |= ( RegM & <NUM_LIT> )


<s> break ; default : return SDValue ( ) ; } assert ( NumSubVectors == <NUM_LIT> || NumSubVectors == <NUM_LIT> ) ; SmallVector < SDValue , <NUM_LIT> > SubRegValues ; if ( auto * CP = dyn_cast < ConstantPoolSDNode > ( Ptr ) ) { const Constant * C = CP -> getConstVal ( ) ; if ( isa < ConstantAggregateZero > ( C ) ) { SDValue ZeroSubVector = DAG . getConstant ( APInt ( <NUM_LIT> , <NUM_LIT> ) , DL , SubVectorTy ) ; SubRegValues . append ( NumSubVectors , ZeroSubVector ) ; } else { return SDValue ( ) ; } } else { SDValue V0 = DAG . getLoad ( SubVectorTy , DL , Chain , Ptr , LoadNode -> getPointerInfo ( ) . getWithOffset ( <NUM_LIT> ) , LoadNode -> getAlignment ( ) , LoadNode -> getMemOperand ( ) -> getFlags ( ) , LoadNode -> getAAInfo ( ) ) ; SubRegValues . push_back ( V0 ) ; SDValue NewPtr = DAG . getNode ( <STR_LIT> , DL , Ptr . getValueType ( ) , Ptr , DAG . getConstant ( SubRegSize , DL , Ptr . getValueType ( ) ) ) ; SDValue V1 = DAG . getLoad ( SubVectorTy , DL , Chain , NewPtr , LoadNode -> getPointerInfo ( ) . getWithOffset ( SubRegSize ) , LoadNode -> getAlignment ( ) , LoadNode -> getMemOperand ( ) -> getFlags ( ) , LoadNode -> getAAInfo ( ) ) ; SubRegValues . push_back ( V1 ) ; if ( NumSubVectors > <NUM_LIT> ) { NewPtr = DAG . getNode ( <STR_LIT> , DL , Ptr . getValueType ( ) , Ptr , DAG . getConstant ( <NUM_LIT> * SubRegSize , DL , Ptr . getValueType ( ) ) ) ; SDValue V2 = DAG . getLoad ( SubVectorTy , DL , Chain , NewPtr , LoadNode -> getPointerInfo ( ) . getWithOffset ( <NUM_LIT> * SubRegSize ) , LoadNode -> getAlignment ( ) , LoadNode -> getMemOperand ( ) -> getFlags (


<s> case CallingConv :: <ISA_LIT>_APCS : case CallingConv :: GHC : case CallingConv :: CFGuard_Check : return CC ; case CallingConv :: PreserveMost : return CallingConv :: PreserveMost ; case CallingConv :: <ISA_LIT>_AAPCS_VFP : case CallingConv :: Swift : case CallingConv :: SwiftTail : return isVarArg ? CallingConv :: <ISA_LIT>_AAPCS : CallingConv :: <ISA_LIT>_AAPCS_VFP ; case CallingConv :: C : if ( ! Subtarget -> isAAPCS_ABI ( ) ) return CallingConv :: <ISA_LIT>_APCS ; else if ( Subtarget -> hasVFP2Base ( ) && ! Subtarget -> isThumb1Only ( ) && getTargetMachine ( ) . Options . FloatABIType == FloatABI :: Hard && ! isVarArg ) return CallingConv :: <ISA_LIT>_AAPCS_VFP ; else return CallingConv :: <ISA_LIT>_AAPCS ; case CallingConv :: Fast : case CallingConv :: CXX_FAST_TLS : if ( ! Subtarget -> isAAPCS_ABI ( ) ) { if ( Subtarget -> hasVFP2Base ( ) && ! Subtarget -> isThumb1Only (

) && ! isVarArg ) return CallingConv :: Fast ;


<s> static unsigned getLocalId ( DenseMap < unsigned , unsigned > & Reg2Local

, unsigned & CurLocal , unsigned Reg ) {


<s> BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) , Tmp ) . addImm ( <NUM_LIT> ) . addReg ( Rs ) . addImm ( <STR_LIT> ) ; Rs = Tmp ; } BuildMI ( * BB , MI , DL , TII -> get ( Using<ISA_LIT>32 ? <STR_LIT> : <STR_LIT> ) ) . addReg ( Rs ) . addReg ( Rt ) . addImm ( Imm ) . addMemOperand ( BB -> getParent ( ) -> getMachineMemOperand ( & MMO , MMO . getOffset ( ) , MMO . getSize ( ) ) ) ; MI . eraseFromParent (


<s> unsigned llvm :: getBLRCallOpcode ( const MachineFunction & MF ) { if ( MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . hardenSlsBlr


<s> RegNo >>= <NUM_LIT> ; unsigned Register = QPRDecoderTable [ RegNo ] ; Inst . addOperand ( MCOperand :: CreateReg ( Register )


<s> const <ISA_LIT>MachineFunctionInfo * MFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; const Function & F = MF . getFunction ( ) ; const DataLayout & DL = F . getParent ( ) -> getDataLayout ( ) ; PointerType * PtrTy = PointerType :: get ( ParamTy , <ISA_LIT>AS :: CONSTANT_ADDRESS ) ; LLT PtrType = getLLTForType ( * PtrTy , DL ) ; Register DstReg = MRI . createGenericVirtualRegister ( PtrType ) ; Register KernArgSegmentPtr = MFI -> getPreloadedReg ( <STR_LIT> ) ; Register KernArgSegmentVReg = MRI . getLiveInVirtReg (


<s> unsigned Opc = <STR_LIT> ; if ( Node -> hasOneUse ( ) ) return CurDAG -> SelectNodeTo ( Node , Opc , VT , TFI , imm ) ; return CurDAG -> getMachineNode ( Opc , dl , VT , TFI , imm ) ; } case <STR_LIT> : { if ( TM . getRelocationModel ( ) == Reloc :: PIC_ ) { SDValue Chain = Node -> getOperand ( <NUM_LIT> ) ; SDValue Callee = Node -> getOperand ( <NUM_LIT> ) ; SDValue R20Reg = CurDAG -> getRegister ( <STR_LIT> , <STR_LIT> ) ; SDValue InFlag ( <NUM_LIT> , <NUM_LIT> ) ; if ( ( isa < GlobalAddressSDNode > ( Callee ) ) || ( isa < ExternalSymbolSDNode > ( Callee ) ) ) { SDValue GPReg = CurDAG -> getRegister ( <STR_LIT> , <STR_LIT> ) ; SDValue Ops [ ] = { Callee , GPReg , Chain } ; SDValue Load = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , <STR_LIT> , Ops ) , <NUM_LIT> ) ; Chain = Load . getValue ( <NUM_LIT> ) ; Chain = CurDAG -> getCopyToReg ( Chain , dl , R20Reg , Load , InFlag ) ; } else Chain = CurDAG -> getCopyToReg ( Chain , dl , R20Reg , Callee , InFlag ) ; SDNode * ResNode = CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , <STR_LIT> , R20Reg , Chain ) ; Chain = SDValue ( ResNode , <NUM_LIT> ) ; InFlag = SDValue ( ResNode , <NUM_LIT> ) ; ReplaceUses ( SDValue ( Node , <NUM_LIT> ) , Chain ) ; ReplaceUses ( SDValue ( Node , <NUM_LIT> ) , InFlag ) ; return ResNode ; } } } SDNode * ResNode = SelectCode ( Node ) ; DEBUG ( errs ( ) << <STR_LIT> ) ; if ( ResNode == NULL || ResNode == Node ) DEBUG ( Node -> dump ( CurDAG ) ) ; else DEBUG ( ResNode -> dump ( CurDAG ) ) ; DEBUG ( errs ( ) << <STR_LIT> ) ; return


<s> void DecodeEXTRQIMask ( int Len , int Idx , SmallVectorImpl < int > & ShuffleMask ) { Len &= <NUM_LIT> ; Idx &= <NUM_LIT> ; if ( <NUM_LIT> != ( Len % <NUM_LIT> ) || <NUM_LIT> != ( Idx % <NUM_LIT> ) ) return ; if ( Len == <NUM_LIT> ) Len = <NUM_LIT> ; if ( ( Len + Idx ) > <NUM_LIT> ) { ShuffleMask . append ( <NUM_LIT> ,


<s> SDValue Arg = Op . getOperand ( <NUM_LIT> ) ; EVT ArgVT = Arg . getValueType ( ) ; Type * ArgTy = ArgVT . getTypeForEVT ( * DAG . getContext ( ) ) ; ArgListTy Args ; ArgListEntry Entry ; Entry . Node = Arg ; Entry . Ty = ArgTy ; Entry . IsSExt = false ; Entry . IsZExt = false ; Args . push_back ( Entry ) ; const char * LibcallName = ( ArgVT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; SDValue Callee = DAG . getExternalSymbol ( LibcallName , getPointerTy ( DAG . getDataLayout ( ) ) ) ; StructType * RetTy = StructType :: get ( ArgTy , ArgTy , nullptr


<s> unsigned <ISA_LIT>MCCodeEmitter :: getMovePRegSingleOpValue ( const MCInst & MI , unsigned OpNo , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { assert ( ( ( OpNo == <NUM_LIT> ) || ( OpNo == <NUM_LIT> ) ) && <STR_LIT> ) ; MCOperand Op = MI . getOperand ( OpNo ) ; assert ( Op . isReg ( ) && <STR_LIT> ) ; switch ( Op . getReg ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return


<s> ConstantSDNode * Idx = dyn_cast < ConstantSDNode > ( Input . getOperand ( <NUM_LIT> ) ) ; SDValue OrigVector = Input . getOperand ( <NUM_LIT> ) ; if ( Idx && VT == OrigVector . getValueType ( ) ) { unsigned NumElts = VT . getVectorNumElements ( ) ; assert ( NumElts > <NUM_LIT> && <STR_LIT> ) ; SmallVector < int , <NUM_LIT> > NewMask ( NumElts , - <NUM_LIT> ) ; unsigned ResultInElt = NumElts / <NUM_LIT> ; ResultInElt -= Subtarget . isLittleEndian ( ) ? <NUM_LIT> : <NUM_LIT> ; NewMask [ ResultInElt ] = Idx -> getZExtValue ( ) ; return DAG . getVectorShuffle ( VT , dl , OrigVector , OrigVector


<s> SDValue getAddrGPRel ( NodeTy * N , const SDLoc & DL , EVT Ty , SelectionDAG & DAG , bool IsN64 ) const { assert ( ! ABI . IsCheriPureCap ( ) ) ; assert ( ! Ty . isFatPointer ( ) ) ; SDValue GPRel = getTargetNode ( N , Ty , DAG , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , DL , Ty , DAG . getRegister ( IsN64 ? <STR_LIT> : <STR_LIT> , Ty ) , DAG . getNode ( <STR_LIT> , DL , DAG .


<s> if ( ! Width ) break ; uint32_t WidthVal = Width -> getZExtValue ( ) & <NUM_LIT> ; if ( WidthVal == <NUM_LIT> ) return DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ; ConstantSDNode * Offset = dyn_cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ; if ( ! Offset ) break ; SDValue BitsFrom = N -> getOperand ( <NUM_LIT> ) ; uint32_t OffsetVal = Offset -> getZExtValue ( ) & <NUM_LIT> ; bool Signed = N -> getOpcode ( ) == <STR_LIT> ; if ( OffsetVal == <NUM_LIT> ) { unsigned SignBits = Signed ? ( <NUM_LIT> - WidthVal + <NUM_LIT> ) : ( <NUM_LIT> - WidthVal ) ; unsigned OpSignBits = DAG . ComputeNumSignBits ( BitsFrom ) ; if ( OpSignBits >= SignBits ) return BitsFrom ; EVT SmallVT = EVT :: getIntegerVT ( * DAG . getContext ( ) , WidthVal ) ; if ( Signed ) { return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , BitsFrom , DAG . getValueType ( SmallVT ) ) ; } return DAG . getZeroExtendInReg ( BitsFrom , DL , SmallVT ) ; } if ( ConstantSDNode * Val = dyn_cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ) { if ( Signed ) { return constantFoldBFE < int32_t > ( DAG , Val -> getSExtValue ( ) , OffsetVal , WidthVal ) ; } return constantFoldBFE < uint32_t > ( DAG , Val -> getZExtValue ( ) , OffsetVal , WidthVal ) ; } APInt Demanded = APInt :: getBitsSet ( <NUM_LIT> , OffsetVal , OffsetVal + WidthVal ) ; if ( ( OffsetVal + WidthVal ) >= <NUM_LIT> ) { SDValue ShiftVal = DAG . getConstant ( OffsetVal , <STR_LIT> ) ; return DAG . getNode ( Signed ? <STR_LIT> : <STR_LIT> , DL , <STR_LIT> , BitsFrom , ShiftVal ) ; } APInt KnownZero , KnownOne


<s> if ( Subtarget . hasVPOPCNTDQ ( ) ) { unsigned NumElems = VT . getVectorNumElements ( ) ; assert ( ( VT . getVectorElementType ( ) == <STR_LIT> || VT . getVectorElementType ( ) == <STR_LIT> ) && <STR_LIT> ) ; if ( NumElems <= <NUM_LIT> ) { MVT NewVT = <STR_LIT> ( <STR_LIT> , NumElems ) ; Op = DAG . getNode ( <STR_LIT> , DL , NewVT , Op0 ) ; Op = DAG . getNode ( <STR_LIT> , DL , NewVT , Op ) ; return DAG . getNode ( <STR_LIT> , DL , VT


<s> Exec = <STR_LIT> ; } char GlobalFlags = analyzeFunction ( MF ) ; unsigned LiveMaskReg = <NUM_LIT> ; if ( ! ( GlobalFlags & StateWQM ) ) { lowerLiveMaskQueries ( Exec ) ; if ( ! ( GlobalFlags & StateWWM ) && LowerToCopyInstrs . empty ( ) && LowerToMovInstrs . empty ( ) ) return ! LiveMaskQueries . empty ( ) ; } else { MachineBasicBlock & Entry = MF . front ( ) ; MachineBasicBlock :: iterator EntryMI = Entry . getFirstNonPHI ( ) ; if ( GlobalFlags & StateExact || ! LiveMaskQueries . empty ( ) ) { LiveMaskReg = MRI -> createVirtualRegister ( TRI -> getBoolRC ( ) ) ; MachineInstr * MI = BuildMI ( Entry , EntryMI , DebugLoc ( ) , TII -> get ( <STR_LIT> ) , LiveMaskReg ) . addReg ( Exec ) ; LIS -> InsertMachineInstrInMaps ( * MI ) ; } lowerLiveMaskQueries ( LiveMaskReg ) ; if ( GlobalFlags == StateWQM ) { auto MI = BuildMI ( Entry , EntryMI , DebugLoc ( ) , TII -> get ( ST -> isWave32 ( ) ? <STR_LIT> : <STR_LIT> ) ,


<s> SDValue <ISA_LIT>TargetLowering :: LowerFormalArguments ( SDValue Chain , unsigned CallConv , bool isVarArg , const SmallVectorImpl < <STR_LIT> > & Ins , DebugLoc dl , SelectionDAG & DAG , SmallVectorImpl < SDValue > & InVals ) { if ( <ISA_LIT>SubTarget . isSVR4ABI ( ) && ! <ISA_LIT>SubTarget . is<ISA_LIT>64 ( ) ) { return LowerFormalArguments_SVR4 ( Chain , CallConv , isVarArg , Ins , dl , DAG , InVals ) ; } else { return LowerFormalArguments_Darwin ( Chain , CallConv , isVarArg ,


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return


<s> static EVT getExtensionTo64Bits ( const EVT & OrigVT ) { if ( OrigVT . getSizeInBits ( ) >= <NUM_LIT> ) return OrigVT ; assert ( OrigVT . isSimple ( ) && <STR_LIT> ) ; <STR_LIT> OrigSimpleTy = OrigVT . getSimpleVT ( ) . SimpleTy ; switch ( OrigSimpleTy ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT>


<s> if ( size == <NUM_LIT> ) ; else { rtx size_int_rtx , size_rtx ; size_rtx = size_int_rtx = GEN_INT ( - size ) ; if ( size <= <NUM_LIT> ) insn = emit_insn ( gen_stack_pointer_inc ( size_int_rtx ) ) ; else if ( size <= <NUM_LIT> && ! frame_pointer_needed ) { insn = emit_insn ( gen_stack_pointer_inc ( GEN_INT ( - <NUM_LIT> ) ) ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; insn = emit_insn ( gen_stack_pointer_inc ( GEN_INT ( <NUM_LIT> - size ) ) ) ; } else { size_rtx = gen_rtx_REG ( Pmode , <NUM_LIT> ) ; emit_move_insn ( size_rtx , size_int_rtx ) ; insn = emit_insn ( gen_stack_pointer_inc ( size_rtx ) ) ; add_reg_note ( insn , REG_CFA_ADJUST_CFA , gen_stack_pointer_inc ( size_int_rtx ) ) ; } RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; emit_insn ( gen_frame_blockage ( ) ) ; if ( frame_pointer_needed ) { insn = emit_insn ( gen_rtx_SET ( hard_frame_pointer_rtx , gen_rtx_MINUS ( Pmode , stack_pointer_rtx , size_rtx ) ) ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; add_reg_note ( insn , REG_CFA_ADJUST_CFA , gen_rtx_SET ( hard_frame_pointer_rtx , plus_constant ( Pmode , stack_pointer_rtx , size ) ) ) ; } if ( return_addr_reg_needed_p ( sparc_leaf_function_p ) ) { rtx o7 = gen_rtx_REG ( Pmode , INCOMING_RETURN_ADDR_REGNUM ) ; rtx i7 = gen_rtx_REG ( Pmode , RETURN_ADDR_REGNUM ) ; insn = emit_move_insn ( i7 , o7 ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; add_reg_note ( insn , REG_CFA_REGISTER , gen_rtx_SET ( i7 , o7 ) ) ; emit_use ( i7


<s> return ( vector unsigned int ) __builtin_altivec_vupklpx (


<s> N -> getMask ( M ) ; return :: isUNPCKLMask ( M , N -> getValueType ( <NUM_LIT> ) ,


<s> int register_ok_for_ldd ( rtx reg ) { if ( ! REG_P ( reg ) ) return <NUM_LIT> ; if ( REGNO ( reg ) < FIRST_PSEUDO_REGISTER ) return ( REGNO ( reg ) % <NUM_LIT> == <NUM_LIT> ) ; return <NUM_LIT>


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : RegList = <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : RegList = <STR_LIT> ; break ; default : return false ; } unsigned UnallocatedRegisterIndex = State . getFirstUnallocated ( RegList ) ; if ( UnallocatedRegisterIndex < RegList . size ( ) ) State . AllocateStack ( LocVT . getSizeInBits ( ) / <NUM_LIT> , Align ( <NUM_LIT> ) ) ; return


<s> if ( ! MIa . hasOneMemOperand ( ) || ! MIb . hasOneMemOperand ( ) ) return false ; MachineMemOperand * MMOa = * MIa . memoperands_begin ( ) ; MachineMemOperand * MMOb = * MIb . memoperands_begin ( ) ; const Value * VALa = MMOa -> getValue ( ) ; const Value * VALb = MMOb -> getValue ( ) ; bool SameVal = ( VALa && VALb && ( VALa == VALb ) ) ; if ( ! SameVal ) { const PseudoSourceValue * PSVa = MMOa -> getPseudoValue ( ) ; const PseudoSourceValue * PSVb = MMOb -> getPseudoValue ( ) ; if ( PSVa && PSVb && ( PSVa == PSVb ) ) SameVal = true ; } if ( SameVal


<s> bool hasFP ( const MachineFunction & ) const override { return


<s> void <ISA_LIT>AsmPrinter :: PrintDebugValueComment ( const MachineInstr * MI , raw_ostream &


<s> assert ( SrcPartials [ <NUM_LIT> ] . getBitWidth ( ) == NumElts && <STR_LIT> ) ; SDValue PartialBits = DAG . getConstant ( SrcPartials [ <NUM_LIT> ] , dl , MaskVT ) ; Mask = DAG . getNode ( <STR_LIT> , dl , MaskVT , Mask , PartialBits ) ; return DAG . getSetCC ( dl , <STR_LIT> , Mask , PartialBits , <STR_LIT> ) ; } } } if ( SDValue V = combineScalarAndWithMaskSetcc ( N , DAG , Subtarget ) ) return V ; if ( SDValue R = combineBitOpWithMOVMSK ( N , DAG ) ) return R ; if ( DCI . isBeforeLegalizeOps ( ) ) return SDValue ( ) ; if ( SDValue R = combineCompareEqual ( N , DAG , DCI , Subtarget ) ) return R ; if ( SDValue FPLogic = convertIntLogicToFPLogic ( N , DAG , Subtarget ) ) return FPLogic ; if ( SDValue R = combineANDXORWithAllOnesIntoANDNP ( N , DAG ) ) return R ; if ( SDValue ShiftRight = combineAndMaskToShift ( N , DAG , Subtarget ) ) return ShiftRight ; if ( SDValue R = combineAndLoadToBZHI ( N , DAG , Subtarget ) ) return R ; if ( VT . isVector ( ) && ( VT . getScalarSizeInBits ( ) % <NUM_LIT> ) == <NUM_LIT> ) { SDValue Op ( N , <NUM_LIT> ) ; if ( SDValue Res = combine<ISA_LIT>ShufflesRecursively ( Op , DAG , Subtarget ) ) return Res ; } if ( ( VT . getScalarSizeInBits ( ) % <NUM_LIT> ) == <NUM_LIT> && N -> getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> && isa < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ) ) { SDValue BitMask = N -> getOperand ( <NUM_LIT> ) ; SDValue SrcVec = N -> getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ; EVT SrcVecVT = SrcVec . getValueType ( ) ; APInt UndefElts ; SmallVector < APInt , <NUM_LIT> > EltBits ; if ( VT == SrcVecVT . getScalarType ( ) && N -> getOperand ( <NUM_LIT> ) -> isOnlyUserOf ( SrcVec . getNode ( ) ) && getTargetConstantBitsFromNode ( BitMask , <NUM_LIT> , UndefElts , EltBits ) && llvm :: all_of ( EltBits , [ ] ( APInt M ) { return M . isNullValue ( ) || M . isAllOnesValue ( ) ; } ) ) { unsigned NumElts = SrcVecVT . getVectorNumElements ( ) ; unsigned Scale = SrcVecVT . getScalarSizeInBits ( ) / <NUM_LIT> ; unsigned Idx = N -> getOperand ( <NUM_LIT> ) . getConstantOperandVal ( <NUM_LIT> ) ; SmallVector < int , <NUM_LIT> > ShuffleMask ( NumElts *


<s> static bool isUsedAsMemCpySource ( const Value * V , bool & OtherUse ) { bool UsedAsMemCpySource = false ; for ( const User * U : V -> users ( ) ) if ( const Instruction * User = dyn_cast


<s> if ( LDN ) AddrOp = LDN -> getOperand ( <NUM_LIT> ) ; else if ( STN ) AddrOp = STN -> getOperand ( <NUM_LIT> ) ; short Imm = <NUM_LIT> ; if ( AddrOp . getOpcode ( ) == <STR_LIT> ) { if ( FrameIndexSDNode * FI = dyn_cast < FrameIndexSDNode > ( AddrOp . getOperand ( <NUM_LIT> ) ) ) { const MachineFrameInfo & MFI = CurDAG -> getMachineFunction ( ) . getFrameInfo ( ) ; unsigned SlotAlign = MFI . getObjectAlignment ( FI -> getIndex ( ) ) ; if ( ( SlotAlign % Val ) != <NUM_LIT> ) return false ; } return isIntS16Immediate ( AddrOp . getOperand ( <NUM_LIT> ) , Imm ) && ! ( Imm % Val ) ; } return AddrOp . getOpcode ( )


<s> const SDValue Dividend = Op -> getOperand ( <NUM_LIT> ) ; const SDValue Divisor = Op -> getOperand ( <NUM_LIT> ) ; SDValue Div = DAG . getNode ( DivOpcode , dl , VT , Dividend , Divisor ) ; SDValue Mul = DAG . getNode ( <STR_LIT> , dl , VT , Div , Divisor ) ; SDValue Rem = DAG . getNode ( <STR_LIT> , dl , VT , Dividend , Mul ) ; SDValue Values [ <NUM_LIT> ] = { Div , Rem } ; return DAG . getNode ( <STR_LIT> , dl , DAG . getVTList ( VT , VT ) , Values ) ; } RTLIB :: Libcall LC = getDivRemLibcall ( Op . getNode ( ) , VT . getSimpleVT ( ) . SimpleTy ) ; SDValue InChain = DAG . getEntryNode ( ) ; TargetLowering :: ArgListTy Args = getDivRemArgList ( Op . getNode ( ) , DAG . getContext ( ) , Subtarget ) ; SDValue Callee = DAG . getExternalFunctionSymbol ( getLibcallName ( LC ) ) ; Type * RetTy = StructType :: get ( Ty , Ty ) ; if ( Subtarget -> isTargetWindows ( ) ) InChain = WinDBZCheckDenominator ( DAG , Op . getNode ( ) , InChain ) ; TargetLowering :: CallLoweringInfo CLI ( DAG


<s> switch ( Type ) { case ST_ROM0 : O << <STR_LIT> ; break ; case ST_ROMX : O << <STR_LIT> ; break ; case ST_VRAM : O << <STR_LIT> ; break ; case ST_SRAM : O << <STR_LIT> ; break ; case ST_WRAM0 : O << <STR_LIT> ; break ; case ST_WRAMX : O << <STR_LIT> ; break ; case ST_OAM : O


<s> MCAsmBackend * llvm :: create<ISA_LIT>AsmBackend ( const Target & T , const MCSubtargetInfo & STI , const MCRegisterInfo & , const MCTargetOptions & ) { const Triple & TT = STI . getTargetTriple ( ) ; if ( ! TT . isOSBinFormatELF ( ) ) llvm_unreachable


<s> assert ( ( ( frontOperand . isReg ( ) && backOperand . isReg ( ) ) || ( frontOperand . isImm ( ) && backOperand . isImm ( ) ) ) && <STR_LIT> ) ; if ( order ) { if ( frontOperand . isReg ( ) && backOperand . isReg ( ) && backOperand . getReg ( ) != <STR_LIT> && frontOperand . getReg ( ) != backOperand . getReg ( ) ) return false ; } else { if ( frontOperand . isReg ( ) && backOperand . isReg ( ) && frontOperand . getReg ( ) != backOperand . getReg ( ) ) return false ; } if ( frontOperand . isImm ( ) && backOperand . isImm ( ) && ! ( frontOperand . getImm ( ) == backOperand . getImm ( ) ) ) return false ; } return true


<s> SDValue StVal = St . getValue ( ) ; EVT VT = StVal . getValueType ( ) ; if ( VT . isScalableVector ( ) ) return SDValue ( ) ; int NumVecElts = VT . getVectorNumElements ( ) ; if ( ! ( ( ( NumVecElts == <NUM_LIT> || NumVecElts == <NUM_LIT> ) && VT . getVectorElementType ( ) . getSizeInBits ( ) == <NUM_LIT> ) || ( ( NumVecElts == <NUM_LIT> || NumVecElts == <NUM_LIT> || NumVecElts == <NUM_LIT> ) && VT . getVectorElementType ( ) . getSizeInBits ( ) == <NUM_LIT> ) ) ) return SDValue ( ) ; if ( StVal . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; if ( ! StVal . hasOneUse ( ) ) return SDValue ( ) ; if ( St . isTruncatingStore ( ) ) return SDValue ( ) ; if ( DAG . isBaseWithConstantOffset ( St


<s> SDValue <ISA_LIT>TargetLowering :: combineBSWAP ( SDNode * N , DAGCombinerInfo & DCI ) const { SelectionDAG & DAG = DCI . DAG ; if ( <STR_LIT> ( N -> getOperand ( <NUM_LIT> ) . getNode ( ) ) && N -> getOperand ( <NUM_LIT> ) . hasOneUse ( ) && ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT> || N -> getValueType ( <NUM_LIT> ) == <STR_LIT> || N -> getValueType ( <NUM_LIT> ) == <STR_LIT> ) && ! cast < LoadSDNode > ( N -> getOperand ( <NUM_LIT> ) ) -> isVolatile ( ) ) { SDValue Load = N -> getOperand ( <NUM_LIT> ) ; LoadSDNode * LD = cast < LoadSDNode > ( Load ) ; SDValue Ops [ ] = { LD -> getChain ( ) , LD -> getBasePtr ( ) , DAG . getValueType ( N -> getValueType ( <NUM_LIT> ) ) } ; SDValue BSLoad = DAG . getMemIntrinsicNode ( <STR_LIT> , SDLoc ( N ) , DAG . getVTList ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> , <STR_LIT> ) , Ops , LD -> getMemoryVT ( ) , LD -> getMemOperand ( ) ) ; SDValue ResVal = BSLoad ; if ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT> ) ResVal = DAG . getNode ( <STR_LIT> , SDLoc ( N ) , <STR_LIT> , BSLoad ) ; DCI . CombineTo ( N , ResVal ) ; DCI . CombineTo ( Load . getNode ( ) , ResVal , BSLoad .


<s> if ( TgtBB != ML . getHeader ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } if ( BBUtils -> getOffsetOf ( End ) < BBUtils -> getOffsetOf ( ML . getHeader ( ) ) || ! BBUtils -> isBBInRange ( End , ML . getHeader ( ) , <NUM_LIT> ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } if ( isWhileLoopStart ( * Start ) ) { MachineBasicBlock * TargetBB = getWhileLoopStartTargetBB ( * Start ) ; if ( BBUtils -> getOffsetOf ( Start ) > BBUtils -> getOffsetOf ( TargetBB ) || ! BBUtils -> isBBInRange ( Start , TargetBB , <NUM_LIT> ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } } return true ; } ; StartInsertPt = MachineBasicBlock :: iterator ( Start ) ; StartInsertBB = Start ->


<s> Inst . addOperand ( MCOperand :: CreateReg (


<s> MVT VT = N -> getSimpleValueType ( <NUM_LIT> ) ; unsigned ElSize = VT . getScalarSizeInBits ( ) ; return ( Index * ElSize ) % vecWidth ==


<s> std :: tie ( LoMemVT , HiMemVT ) = DAG . GetSplitDestVTs ( MemVT ) ; std :: tie ( Lo , Hi ) = DAG . SplitVector ( Op , SL , LoVT , HiVT ) ; unsigned Size = LoMemVT . getStoreSize ( ) ; unsigned BaseAlign = Load -> getAlignment ( ) ; unsigned HiAlign = MinAlign ( BaseAlign , Size ) ; SDValue LoLoad = DAG . getExtLoad ( Load -> getExtensionType ( ) , SL , LoVT , Load -> getChain ( ) , BasePtr , SrcValue , LoMemVT , BaseAlign , Load -> getMemOperand ( ) -> getFlags ( ) ) ; SDValue HiPtr = DAG . getNode ( <STR_LIT> , SL , PtrVT , BasePtr , DAG . getConstant ( Size ,


<s> return mode == DFmode ? loongarch_cost ->


<s> bool <ISA_LIT>DAGToDAGISel :: isMaskZeroExtended ( SDNode * N ) const { if ( N -> getOpcode ( ) == <STR_LIT> ) return isLegalMaskCompare ( N -> getOperand ( <NUM_LIT> ) . getNode ( ) , Subtarget ) || isLegalMaskCompare ( N -> getOperand ( <NUM_LIT> ) . getNode ( ) , Subtarget ) ; return isLegalMaskCompare ( N , Subtarget


<s> return SelectDSReadWrite2 ( Addr , Base , Offset0 , Offset1 , <NUM_LIT>


<s> MIB . add ( MI -> getOperand ( <NUM_LIT> ) ) ; MIB . addImm ( <NUM_LIT> ) ; MIB . addImm ( <STR_LIT> ) ; MIB . addReg ( <STR_LIT> ) ; MIB . addReg ( <STR_LIT> , RegState :: Define ) ; } MachineInstrBuilder MIB = BuildMI ( * MBB , MI , MI -> getDebugLoc ( ) , TII -> get ( BrOpc ) ) ; MIB . addMBB ( getWhileLoopStartTargetBB ( * MI ) ) ; MIB . addImm ( <STR_LIT> ) ; MIB . addReg ( <STR_LIT>


<s> long foo = __fixdfsi ( ( double ) ld


<s> SDValue getAddrNonPIC ( NodeTy * N , const SDLoc & DL , EVT Ty , SelectionDAG & DAG ) const { SDValue Hi = getTargetNode ( N , Ty


<s> if ( Subtarget -> isThumb2 ( ) ) return <STR_LIT> ( llvm


<s> TmpInst . addOperand ( MCOperand :: CreateReg ( <STR_LIT> ) ) ; const MCSymbolRefExpr * LoSym = MCSymbolRefExpr :: Create ( <STR_LIT> , MCSymbolRefExpr :: VK_<ISA_LIT>_ABS_LO , MCA . getContext ( ) ) ; TmpInst . addOperand ( MCOperand :: CreateExpr ( LoSym ) ) ; getStreamer ( ) . EmitInstruction ( TmpInst , STI ) ; TmpInst . clear ( ) ; TmpInst . setOpcode ( <STR_LIT> ) ; TmpInst . addOperand ( MCOperand :: CreateReg ( <STR_LIT> ) ) ; TmpInst . addOperand ( MCOperand :: CreateReg ( <STR_LIT> ) ) ; TmpInst . addOperand ( MCOperand :: CreateReg


<s> for ( unsigned I = <NUM_LIT> ; I < array_lengthof ( ReservedCPURegs ) ; ++ I ) Reserved . set ( ReservedCPURegs [ I ] ) ; const <ISA_LIT>MachineFunctionInfo * <ISA_LIT>FI = MF . getInfo <


<s> unsigned int call_properties ( const function_instance & ) const override { return


<s> if ( ! HARD_REGISTER_P ( pic_offset_table_rtx ) && ( HARD_REGISTER_P ( x ) || lra_in_progress ) && ORIGINAL_REGNO ( x ) == REGNO ( pic_offset_table_rtx


<s> bool checkForP2AlignIfLoadStore ( OperandVector & Operands , StringRef InstName ) { auto IsLoadStore = InstName . contains ( <STR_LIT> ) || InstName . contains ( <STR_LIT> ) || InstName . contains ( <STR_LIT> ) ; auto IsAtomic = InstName . contains ( <STR_LIT> ) ; if ( IsLoadStore || IsAtomic ) { if ( IsLoadStore && isNext ( AsmToken :: Colon ) ) { auto Id = expectIdent ( ) ; if ( Id != <STR_LIT> ) return error ( <STR_LIT> + Id ) ; if ( expect ( AsmToken :: Equal , <STR_LIT> ) ) return true ; if ( ! Lexer . is ( AsmToken :: Integer ) ) return error ( <STR_LIT> ) ; parseSingleInteger ( false , Operands ) ; } else { auto IsLoadStoreLane = InstName . contains ( <STR_LIT> ) ; if ( IsLoadStoreLane && Operands . size ( ) == <NUM_LIT> ) return false ; auto Tok = Lexer . getTok ( ) ; Operands . push_back ( std :: make_unique < <ISA_LIT>Operand > ( <STR_LIT> , Tok . getLoc ( ) , Tok . getEndLoc ( ) , <STR_LIT> { - <NUM_LIT> } ) ) ; } } return false


<s> unsigned FromN = FromB -> getNumber ( ) , ToN = ToB -> getNumber ( ) ; PairMapType :: iterator F = M . find ( std :: make_pair ( FromN , ToN ) ) ; if ( F != M . end ( ) ) return F -> second ; unsigned ToRPO = RPO . lookup ( ToN ) ; unsigned MaxD = <NUM_LIT> ; using pred_iterator = MachineBasicBlock :: const_pred_iterator ; for ( pred_iterator I = ToB -> pred_begin ( ) , E = ToB -> pred_end ( ) ; I != E ; ++ I ) { const MachineBasicBlock * PB = * I ; if ( PB == FromB || RPO . lookup ( PB -> getNumber


<s> rtx cfa_relative_addr = gen_rtx_PLUS ( Pmode , cfa , GEN_INT ( cfa_offset ) ) ; rtx cfa_relative_mem = gen_frame_mem ( DImode , cfa_relative_addr ) ; rtx real = gen_rtx_SET ( cfa_relative_mem , reg_note ) ; add_reg_note ( mov , REG_CFA_OFFSET , real ) ; return emit_insn ( mov


<s> assert ( VT . is256BitVector ( ) && <STR_LIT> ) ; int Size = Mask . size ( ) ; int LaneSize = Size / <NUM_LIT> ; bool LaneCrossing [ <NUM_LIT> ] = { false , false } ; for ( int i = <NUM_LIT> ; i < Size ; ++ i ) if ( Mask [ i ] >= <NUM_LIT> && ( Mask [ i ] % Size ) / LaneSize != i / LaneSize ) LaneCrossing [ ( Mask [ i ] % Size ) / LaneSize ] = true ; if ( ! LaneCrossing [ <NUM_LIT> ] || ! LaneCrossing [ <NUM_LIT> ] ) return splitAndLowerVectorShuffle ( DL , VT , V1 , V2 , Mask , DAG ) ; assert ( V2 . isUndef ( ) && <STR_LIT> ) ; SmallVector < int , <NUM_LIT> > FlippedBlendMask ( Size ) ; for ( int i = <NUM_LIT> ; i < Size ; ++ i ) FlippedBlendMask [ i ] = Mask [ i ] < <NUM_LIT> ? - <NUM_LIT> : ( ( ( Mask [ i ] % Size ) / LaneSize == i / LaneSize ) ? Mask [ i ] : Mask [ i ] % LaneSize + ( i / LaneSize ) * LaneSize + Size ) ; unsigned PERMMask = <NUM_LIT> | <NUM_LIT> << <NUM_LIT> ; SDValue Flipped = DAG . getNode ( <STR_LIT> , DL , VT , DAG . getUNDEF ( VT ) , V1 , DAG . getConstant ( PERMMask , DL , <STR_LIT> ) ) ; return DAG . getVectorShuffle ( VT , DL


<s> switch ( MO . getType ( ) ) { case MachineOperand :: MO_Register : OS << <STR_LIT> << <ISA_LIT>InstPrinter :: getRegisterName ( MO . getReg ( ) ) ; break ; case MachineOperand :: MO_Immediate : OS << '#' << MO . getImm ( ) ; break ; case MachineOperand :: MO_MachineBasicBlock : MO . getMBB ( ) -> getSymbol ( ) -> print


<s> unsigned <ISA_LIT>Z80DAGToDAGISel :: selectIndexedProgMemLoad ( const LoadSDNode * LD , MVT VT ) { <STR_LIT> AM = LD -> getAddressingMode ( ) ; if ( LD -> getExtensionType ( ) != <STR_LIT> || AM != <STR_LIT> ) { return <NUM_LIT> ; } unsigned Opcode = <NUM_LIT> ; int Offs = cast < ConstantSDNode > ( LD -> getOffset ( ) ) -> getSExtValue ( ) ; switch ( VT . SimpleTy ) { case <STR_LIT> : { if ( Offs != <NUM_LIT> ) { return <NUM_LIT> ; } Opcode = <STR_LIT> ; break ; } case <STR_LIT> : { if ( Offs != <NUM_LIT> ) { return <NUM_LIT> ; } Opcode = <STR_LIT> ; break ; } default : return <NUM_LIT>


<s> SDValue <ISA_LIT>TargetLowering :: LowerVACOPY ( SDValue Op , SelectionDAG & DAG ) { assert ( Subtarget -> is64Bit ( ) && <STR_LIT> ) ; SDValue Chain = Op . getOperand ( <NUM_LIT> ) ; SDValue DstPtr = Op . getOperand ( <NUM_LIT> ) ; SDValue SrcPtr = Op .


<s> if ( TYPE_ARG_TYPES ( TREE_TYPE ( decl ) ) == NULL_TREE ) { tree * slot = needed_fndecls_htab -> find_slot ( decl , INSERT ) ; if ( * slot == NULL )


<s> Target & getThe<ISA_LIT>Target ( ) { static Target


<s> static DecodeStatus DecodeBranchImmInstruction ( MCInst & Inst , unsigned Insn , uint64_t Address , const void * Decoder ) { DecodeStatus S = MCDisassembler :: Success ; unsigned pred = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned imm = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ; if ( pred == <NUM_LIT> ) { Inst . setOpcode ( <STR_LIT> ) ; imm |= fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ; if ( ! tryAddingSymbolicOperand ( Address , Address + SignExtend32 < <NUM_LIT> > ( imm ) + <NUM_LIT> , true , <NUM_LIT> , Inst , Decoder ) ) Inst . addOperand ( MCOperand :: createImm ( SignExtend32 < <NUM_LIT> > ( imm ) ) ) ; return


<s> SDValue VTOp = DAG . getValueType ( ExtraVT . getScalarType ( ) ) ; for ( unsigned I = <NUM_LIT> ; I < NElts ; ++ I ) Args [ I ] = DAG . getNode ( <STR_LIT> , DL , ScalarVT , Args [ I ] , VTOp ) ; return DAG . getBuildVector ( VT , DL , Args


<s> SmallVector < SDValue , <NUM_LIT> > ConstVecValues ; EVT VT ; size_t n_copies ; switch ( Op . getValueType ( ) . getSimpleVT ( ) . SimpleTy ) { default : llvm_unreachable ( <STR_LIT> <STR_LIT> ) ; case <STR_LIT> : n_copies = <NUM_LIT> ; VT = <STR_LIT> ; break ; case <STR_LIT> : n_copies = <NUM_LIT> ; VT = <STR_LIT> ; break ; case <STR_LIT> : n_copies = <NUM_LIT> ; VT = <STR_LIT> ; break ; case <STR_LIT> : n_copies = <NUM_LIT> ; VT = <STR_LIT> ; break ; case <STR_LIT> : n_copies = <NUM_LIT> ; VT = <STR_LIT> ; break ; case <STR_LIT> : n_copies = <NUM_LIT> ; VT = <STR_LIT> ; break ; } SDValue CValue = DAG . getConstant ( CN -> getZExtValue ( ) , VT ) ; for ( size_t j = <NUM_LIT> ; j < n_copies ; ++ j ) ConstVecValues . push_back ( CValue ) ; return DAG . getNode ( <STR_LIT> , dl , Op . getValueType ( ) , & ConstVecValues [ <NUM_LIT> ] , ConstVecValues . size ( ) ) ; } else { switch ( Op0 . getValueType ( ) . getSimpleVT ( ) . SimpleTy ) { default : llvm_unreachable ( <STR_LIT> ) ; case


<s> } FPKills &= ~ ( STDefs | STClobbers ) ; unsigned char STUsesArray [ <NUM_LIT> ] ; for ( unsigned I = <NUM_LIT> ; I < NumSTUses ; ++ I ) STUsesArray [ I ] = I ; shuffleStackTop ( STUsesArray , NumSTUses , Inst ) ; DEBUG ( { dbgs ( ) << <STR_LIT> ; dumpStack ( ) ; } ) ; for ( unsigned i = <NUM_LIT> , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) { MachineOperand & Op = MI -> getOperand ( i ) ; if ( ! Op . isReg ( ) || Op . getReg ( ) < <STR_LIT> || Op . getReg ( ) > <STR_LIT> ) continue ; unsigned FPReg = getFPReg ( Op ) ; if ( FRegIdx . count ( i ) ) Op . setReg ( getSTReg ( FPReg ) ) ; else Op . setReg ( <STR_LIT> + FPReg ) ; } StackTop -= NumSTPopped ; for ( unsigned i = <NUM_LIT> ; i < NumSTDefs ; ++ i ) pushReg ( NumSTDefs - i - <NUM_LIT> ) ; while ( FPKills ) { unsigned FPReg = countTrailingZeros ( FPKills ) ; if ( isLive ( FPReg ) ) freeStackSlotAfter ( Inst , FPReg ) ; FPKills &= ~ ( <NUM_LIT> << FPReg ) ; } return ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : unsigned FirstFPRegOp = ~ <NUM_LIT> , SecondFPRegOp = ~ <NUM_LIT> ; unsigned LiveMask = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) { MachineOperand & Op = MI -> getOperand ( i ) ; if ( ! Op . isReg ( ) || Op . getReg ( ) < <STR_LIT> || Op . getReg ( ) > <STR_LIT> ) continue ; assert ( Op . isUse ( ) && ( Op . isKill ( ) || getFPReg ( Op ) == FirstFPRegOp || MI -> killsRegister ( Op . getReg ( ) ) ) && <STR_LIT> ) ; if ( FirstFPRegOp == ~ <NUM_LIT> ) FirstFPRegOp = getFPReg ( Op ) ; else { assert ( SecondFPRegOp == ~ <NUM_LIT> && <STR_LIT> ) ; SecondFPRegOp = getFPReg ( Op ) ; } LiveMask |= ( <NUM_LIT> << getFPReg ( Op ) ) ; MI -> RemoveOperand ( i ) ; -- i , -- e ; } adjustLiveRegs ( LiveMask , MI ) ; if ( ! LiveMask ) return


<s> ConstantSDNode * RHS = dyn_cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ; if ( ! RHS ) return SDValue ( ) ; SDValue LHS = N -> getOperand ( <NUM_LIT> ) ; unsigned RHSVal = RHS -> getZExtValue ( ) ; if ( ! RHSVal ) return LHS ; SDLoc SL ( N ) ; SelectionDAG & DAG = DCI . DAG ; switch ( LHS -> getOpcode ( ) ) { default : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { SDValue X = LHS -> getOperand ( <NUM_LIT> ) ; if ( VT == <STR_LIT> && RHSVal == <NUM_LIT> && X . getValueType ( ) == <STR_LIT> && isOperationLegal ( <STR_LIT> , <STR_LIT> ) ) { SDValue Vec = DAG . getBuildVector ( <STR_LIT> , SL , { DAG . getConstant ( <NUM_LIT> , SL , <STR_LIT> ) , LHS -> getOperand (


<s> if ( InstrInfo . MaskRegOp && hasSameVLMAX ( InstrInfo ) && TailAgnostic == InstrInfo . TailAgnostic && MaskAgnostic == InstrInfo . MaskAgnostic ) return true ; return false


<s> } do { const uint8_t ThisNopLength = ( uint8_t ) std :: min ( Count , ( uint64_t ) <NUM_LIT> ) ; const uint8_t Prefixes = ThisNopLength <= <NUM_LIT> ? <NUM_LIT> : ThisNopLength - <NUM_LIT> ; for ( uint8_t i = <NUM_LIT> ; i < Prefixes ; i ++ ) OW -> Write8 ( <NUM_LIT> ) ; const uint8_t Rest = ThisNopLength - Prefixes ; for ( uint8_t i = <NUM_LIT> ; i < Rest ; i ++ ) OW -> Write8 ( Nops [ Rest - <NUM_LIT> ] [ i ] ) ; Count -= ThisNopLength


<s> unsigned getRegisterBitWidth ( bool Vector ) const { if ( Vector ) { return


<s> bool <ISA_LIT>DAGToDAGISel :: SelectAddrRI12Only ( SDValue Op , SDValue & Addr


<s> Addend = <NUM_LIT> ; if ( const <ISA_LIT>MCExpr * AE = dyn_cast < <ISA_LIT>MCExpr > ( Expr ) ) { ELFRefKind = AE -> getKind ( ) ; Expr = AE -> getSubExpr ( ) ; } const MCSymbolRefExpr * SE = dyn_cast < MCSymbolRefExpr > ( Expr ) ; if ( SE ) { DarwinRefKind = SE -> getKind ( ) ; return true ; } const MCBinaryExpr * BE = dyn_cast < MCBinaryExpr > ( Expr ) ; if ( ! BE ) return false ; SE = dyn_cast < MCSymbolRefExpr > ( BE -> getLHS ( ) ) ; if ( ! SE ) return false ; DarwinRefKind = SE -> getKind ( ) ; if ( BE -> getOpcode ( ) != MCBinaryExpr :: Add && BE -> getOpcode ( ) != MCBinaryExpr :: Sub ) return false ; auto AddendExpr = dyn_cast < MCConstantExpr > ( BE -> getRHS ( ) ) ; if ( ! AddendExpr ) return false ; Addend = AddendExpr -> getValue ( ) ; if ( BE -> getOpcode ( ) == MCBinaryExpr :: Sub ) Addend = - Addend ; return ELFRefKind == <ISA_LIT>MCExpr :: VK_INVALID

|| DarwinRefKind == MCSymbolRefExpr :: VK_None ;


<s> LLVMContext & Ctx = AI -> getContext ( ) ; unsigned Imm = countTrailingZeros ( cast < ConstantInt > ( I -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ) ; Function * BitTest = <STR_LIT> ( AI -> getModule ( ) , IID , AI -> getType ( ) ) ; Value * Addr = Builder . CreatePointerCast ( AI -> getPointerOperand ( ) , Type :: getInt8PtrTy ( Ctx ) ) ; Value * Result = Builder . CreateCall ( BitTest , { Addr , Builder . getInt8 ( Imm ) } ) ; I -> replaceAllUsesWith ( Result ) ; I -> eraseFromParent


<s> if ( UseVZeroUpper ) addPass ( create<ISA_LIT>IssueVZeroUpperPass ( ) ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) { addPass ( create<ISA_LIT>FixupBWInsts ( ) ) ; addPass ( create<ISA_LIT>PadShortFunctions ( ) ) ; addPass ( create<ISA_LIT>FixupLEAs ( ) ) ; addPass ( create<ISA_LIT>EvexToVexInsts


<s> } if ( ci_opr1 == <NUM_LIT> ) { std :: vector < const Type * > ParamsTys ; ParamsTys . push_back ( opr0 -> getType ( ) ) ; Module * M = CI -> getModule ( ) ; if ( Constant * FPExpr = getFunction ( M , <ISA_LIT>LibFunc ( <ISA_LIT>LibFunc :: EI_SQRT , FInfo ) ) ) { LLVM_DEBUG ( errs ( ) << <STR_LIT> << * CI << <STR_LIT> << * opr0 << <STR_LIT> ) ; Value * nval = CreateCallEx ( B , FPExpr , opr0 , <STR_LIT> ) ; replaceCall ( nval ) ; return true ; } } else if ( ci_opr1 == <NUM_LIT> ) { Module * M = CI -> getModule ( ) ; if ( Constant * FPExpr = getFunction ( M , <ISA_LIT>LibFunc ( <ISA_LIT>LibFunc :: EI_CBRT , FInfo ) ) ) { LLVM_DEBUG ( errs ( ) << <STR_LIT> << * CI << <STR_LIT> << * opr0 << <STR_LIT> ) ; Value * nval = CreateCallEx ( B , FPExpr , opr0 , <STR_LIT> ) ; replaceCall ( nval ) ; return true ; } } else if ( ci_opr1 == - <NUM_LIT> ) { LLVM_DEBUG ( errs ( ) << <STR_LIT> << * CI << <STR_LIT> << * opr0 <<


<s> return ( uint8x8_t ) __builtin_neon_vld1v8qi ( (