<s> dump_stack_clash_frame_info ( PROBE_INLINE , residual != <NUM_LIT> ) ; } else { gcc_assert ( int_registers_saved ) ; struct scratch_reg sr ; get_scratch_register_on_entry ( & sr ) ; if ( sr . saved ) size -= UNITS_PER_WORD ; HOST_WIDE_INT rounded_size = size & - probe_interval ; rtx addr = plus_constant ( Pmode , stack_pointer_rtx , - rounded_size ) ; rtx insn ; if ( address_no_seg_operand ( addr , Pmode ) ) insn = emit_insn ( gen_rtx_SET ( sr . reg , addr ) ) ; else { emit_move_insn ( sr . reg , GEN_INT ( - rounded_size ) ) ; insn = emit_insn ( gen_rtx_SET ( sr . reg , gen_rtx_PLUS ( Pmode , sr . reg , stack_pointer_rtx ) ) ) ; } if ( m -> fs . cfa_reg == stack_pointer_rtx ) { add_reg_note ( insn , REG_CFA_DEF_CFA , plus_constant ( Pmode , sr . reg , m -> fs . cfa_offset + rounded_size ) ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; } rtx size_rtx = GEN_INT ( rounded_size ) ; insn = emit_insn ( gen_adjust_stack_and_probe ( Pmode , sr . reg , sr . reg , size_rtx ) ) ; if ( m -> fs . cfa_reg == stack_pointer_rtx ) { m -> fs . cfa_offset += rounded_size ; add_reg_note ( insn , REG_CFA_DEF_CFA , plus_constant ( Pmode , stack_pointer_rtx , m -> fs . cfa_offset ) ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; } m -> fs . sp_offset += rounded_size ; emit_insn ( gen_blockage ( ) ) ; if ( size != rounded_size ) pro_epilogue_adjust_stack ( stack_pointer_rtx , stack_pointer_rtx , GEN_INT ( rounded_size - size ) , - <NUM_LIT> , m -> fs . cfa_reg == stack_pointer_rtx ) ; dump_stack_clash_frame_info ( PROBE_LOOP , size != rounded_size


<s> void <ISA_LIT>FrameLowering :: emitEpilogue ( MachineFunction & MF , MachineBasicBlock & MBB ) const { const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; <ISA_LIT>MachineFunctionInfo * <ISA_LIT>FI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; const <ISA_LIT>InstrInfo & TII = * static_cast < const <ISA_LIT>InstrInfo * > ( MF . getTarget ( ) . getInstrInfo ( ) ) ; MachineBasicBlock :: iterator MBBI = MBB . getLastNonDebugInstr ( ) ; unsigned RetOpcode = MBBI -> getOpcode ( ) ; DebugLoc DL = MBBI -> getDebugLoc ( ) ; switch ( RetOpcode ) { case <STR_LIT> : case <STR_LIT> : break ; default : llvm_unreachable ( <STR_LIT> ) ; } uint64_t StackSize = MFI -> getStackSize ( ) ; unsigned CSSize = <ISA_LIT>FI -> getCalleeSavedFrameSize ( ) ; uint64_t NumBytes = StackSize - CSSize ; if ( hasFP ( MF ) ) { BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) ; } while ( MBBI != MBB . begin ( ) ) { MachineBasicBlock :: iterator PI = prior ( MBBI ) ; unsigned Opc = PI -> getOpcode ( ) ; if ( Opc != <STR_LIT> && ! PI -> isTerminator ( ) ) break ; -- MBBI ; } DL = MBBI -> getDebugLoc ( ) ; if ( MFI -> hasVarSizedObjects ( ) ) { BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) ; if ( CSSize ) { MachineInstr * MI = BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( CSSize ) ; MI -> getOperand ( <NUM_LIT> ) . setIsDead ( ) ; } } else { if ( NumBytes ) { MachineInstr * MI = BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( NumBytes ) ; MI -> getOperand ( <NUM_LIT> ) . setIsDead


<s> unsigned HOST_WIDE_INT count = <NUM_LIT> , offset = <NUM_LIT> ; unsigned int biggest_move = TARGET_STDW ? <NUM_LIT> : <NUM_LIT> ; if ( CONST_INT_P ( align_exp ) ) align = INTVAL ( align_exp ) ; src_mem_align = MEM_ALIGN ( src ) / BITS_PER_UNIT ; dst_mem_align = MEM_ALIGN ( dst ) / BITS_PER_UNIT ; min_mem_align = MIN ( src_mem_align , dst_mem_align ) ; if ( min_mem_align > align ) align = min_mem_align / BITS_PER_UNIT ; if ( src_mem_align < align ) src_mem_align = align ; if ( dst_mem_align < align ) dst_mem_align = align ; if ( CONST_INT_P ( count_exp ) ) count = INTVAL ( count_exp ) ; else return false ; if ( count > ( ( unsigned HOST_WIDE_INT ) <NUM_LIT> << <NUM_LIT> ) ) return false ; if ( count >= <NUM_LIT> && ( count & <NUM_LIT> ) == <NUM_LIT> && align >= <NUM_LIT> ) { tree dst_expr = MEM_EXPR ( dst ) ; tree src_expr = MEM_EXPR ( src ) ; rtx fn = TARGET_INSNS_64PLUS ? strasgi64p_libfunc : strasgi_libfunc ; rtx srcreg = force_reg ( Pmode , XEXP ( src , <NUM_LIT> ) ) ; rtx dstreg = force_reg ( Pmode , XEXP ( dst , <NUM_LIT> ) ) ; if ( src_expr ) mark_addressable ( src_expr ) ; if ( dst_expr ) mark_addressable ( dst_expr ) ; emit_library_call ( fn , LCT_NORMAL , VOIDmode , dstreg , Pmode , srcreg , Pmode , count_exp , SImode ) ; return true ; } if ( biggest_move > align && ! TARGET_INSNS_64 ) biggest_move = align ; if ( count / biggest_move > <NUM_LIT> ) return false ; while ( count > <NUM_LIT> ) { rtx reg , reg_lowpart ; machine_mode srcmode , dstmode ; unsigned HOST_WIDE_INT src_size , dst_size , src_left ; int shift ; rtx srcmem , dstmem ; while ( biggest_move > count ) biggest_move /= <NUM_LIT> ; src_size = dst_size = biggest_move ; if ( src_size > src_mem_align && src_size == <NUM_LIT> ) src_size


<s> void <ISA_LIT>ExpandCondsets :: removeImplicitUses ( MachineBasicBlock & B ) { for ( MachineInstr & MI : B ) if ( HII -> isPredicated ( MI )


<s> __builtin_ia32_pmovwb256mem_mask ( ( __v16qi * ) __P , ( __v16hi )


<s> MCTargetStreamer * create<ISA_LIT>ObjectTargetStreamer ( MCStreamer & S , const MCSubtargetInfo & STI ) { const Triple & TT = STI . getTargetTriple ( ) ; if ( TT . isOSBinFormatELF ( ) ) return new <ISA_LIT>TargetELFStreamer ( S ) ; if ( TT . isOSBinFormatCOFF ( ) ) return

new <ISA_LIT>TargetWinCOFFStreamer ( S ) ;


<s> StringRef FPType ; bool IsLegal = false ; SmallString < <NUM_LIT> > ImmStrVal ; Imm . toString ( ImmStrVal ) ; if ( VT == <STR_LIT> ) { FPType = <STR_LIT> ; IsLegal = <STR_LIT> ( Imm ) != - <NUM_LIT> ; } else if ( VT == <STR_LIT> ) { FPType = <STR_LIT> ; IsLegal = <STR_LIT> ( Imm ) != - <NUM_LIT> ; } else if ( VT == <STR_LIT> && Subtarget -> hasFullFP16 (


<s> Stub * <ISA_LIT>ToTHMStub :: doClone ( ) { return new <ISA_LIT>ToTHMStub ( m_pData , m_Size , fixup_begin (


<s> EVT ValTy = Addr . getValueType ( ) ; Base = CurDAG -> getTargetFrameIndex ( FIN -> getIndex ( ) ,


<s> for ( i = REG_P0 ; i <= REG_P5 ; i ++ ) if ( ( regs_ever_live [ i ] && ( is_inthandler || ! call_used_regs [ i ] ) ) || ( i == PIC_OFFSET_TABLE_REGNUM && ( current_function_uses_pic_offset_table || ( TARGET_ID_SHARED_LIBRARY && ! current_function_is_leaf ) ) ) ) return REG_P5 - i + <NUM_LIT> ; return <NUM_LIT>


<s> static DecodeStatus DecodeCtrRegsRegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t , const void * Decoder ) { static const uint16_t CtrlRegDecoderTable [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; if ( RegNo >= sizeof ( CtrlRegDecoderTable ) / sizeof ( CtrlRegDecoderTable [ <NUM_LIT> ] ) ) return MCDisassembler :: Fail ; if ( CtrlRegDecoderTable [ RegNo ] == <STR_LIT> ) return MCDisassembler :: Fail ; unsigned Register = CtrlRegDecoderTable [ RegNo ] ; Inst . addOperand ( MCOperand :: createReg ( Register )


<s> CRMIB . addReg ( Reg , RegState :: ImplicitKill ) ; continue ; } if ( ( Reg == <STR_LIT> || Reg == <STR_LIT> ) && MustSaveTOC ) continue ; if ( IsCRField ) { <ISA_LIT>FunctionInfo * FuncInfo = MF -> getInfo < <ISA_LIT>FunctionInfo > ( ) ; if ( Subtarget . is<ISA_LIT>64 ( ) ) { FuncInfo -> addMustSaveCR ( Reg ) ; } else { CRSpilled = true ; FuncInfo -> setSpillsCR ( ) ; CRMIB = BuildMI ( * MF , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( Reg , RegState :: ImplicitKill ) ; MBB . insert ( MI , CRMIB ) ; MBB . insert ( MI , addFrameReference ( BuildMI ( * MF , DL , TII . get ( <STR_LIT> ) ) . addReg ( <STR_LIT> , getKillRegState ( true ) ) , CSI [ i


<s> bool <ISA_LIT>DAGToDAGISel :: isConstantLoad ( const LoadSDNode * N , int CbId ) const { const Value * MemVal = N -> getMemOperand ( ) -> getValue ( ) ; if ( CbId == - <NUM_LIT> ) return checkType ( MemVal , <ISA_LIT>AS :: CONSTANT_ADDRESS ) ; return checkType ( MemVal , <ISA_LIT>AS :: CONSTANT_BUFFER_0


<s> for ( MachineBasicBlock * Succ : SrcMBB -> successors ( ) ) DstMBB -> addSuccessor


<s> case <STR_LIT> : case <STR_LIT> : return true ; case <STR_LIT> : return Subtarget -> has<ISA_LIT>32r2Or64 ( ) ; default : return false


<s> BMI -> getOperand ( BMI -> getNumExplicitOperands ( ) - <NUM_LIT> ) . setMBB ( DestBB ) ; MI -> getOperand ( MI -> getNumExplicitOperands ( ) - <NUM_LIT> ) . setMBB ( NewDest ) ; MI -> setDesc ( TII -> get ( Cond [ <NUM_LIT> ] . getImm ( ) ) ) ; return true ; } } } if ( NeedSplit ) { splitBlockBeforeInstr ( * MI ) ; int Delta = TII -> getInstSizeInBytes ( MBB -> back ( ) ) ; BBInfo [ MBB -> getNumber ( ) ] . Size -= Delta ; MBB -> back ( ) . eraseFromParent ( ) ; MBB -> addSuccessor ( DestBB ) ; std :: next ( MBB -> getIterator ( ) ) -> removeSuccessor ( DestBB ) ; } MachineBasicBlock * NextBB = & * ++ MBB -> getIterator ( ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << printMBBReference ( * DestBB ) << <STR_LIT> << printMBBReference


<s> const MCRegisterInfo * MRI = Subtarget . getRegisterInfo ( ) ; unsigned DwarfLR = MRI -> getDwarfRegNum ( <STR_LIT> , true ) ; int Align = Subtarget . getStackAlignment ( ) . value ( ) ; int64_t StackPosEntry = MF . addFrameInst ( MCCFIInstruction :: cfiDefCfaOffset ( nullptr , Align ) ) ; BuildMI ( MBB , It , DebugLoc ( ) , get ( <STR_LIT> ) ) . addCFIIndex ( StackPosEntry ) . setMIFlags


<s> if ( Res != MatchOperand_Success ) return true ; const auto & KindRes = parseVectorKind ( Kind , RegKind :: NeonVector ) ; if ( ! KindRes ) return true ; unsigned ElementWidth = KindRes -> second ; Operands . push_back ( <ISA_LIT>Operand :: CreateVectorReg ( Reg , RegKind :: NeonVector , ElementWidth , S , getLoc ( ) , getContext ( ) ) ) ; if ( ! Kind . empty ( ) ) Operands . push_back ( <ISA_LIT>Operand :: CreateToken (


<s> const char * <ISA_LIT>Relocator :: getName ( Relocator :: Type pType ) const { return ApplyFunctions [ pType ] .


<s> * hi_op1 = gen_highpart ( SImode , op1 ) ; * lo_op2 = simplify_gen_subreg ( SImode , op2 , DImode , subreg_lowpart_offset ( SImode ,


<s> } MemOpChains . push_back ( MemOp ) ; } } if ( ! MemOpChains . empty ( ) ) Chain = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , & MemOpChains [ <NUM_LIT> ] , MemOpChains . size ( ) ) ; SDValue InFlag ; for ( unsigned i = <NUM_LIT> , e = RegsToPass . size ( ) ; i != e ; ++ i ) { Chain = DAG . getCopyToReg ( Chain , dl , RegsToPass [ i ] . first , RegsToPass [ i ] . second , InFlag ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; } if ( GlobalAddressSDNode * G = dyn_cast < GlobalAddressSDNode > ( Callee ) ) Callee = DAG . getTargetGlobalAddress ( G -> getGlobal ( ) , dl , <STR_LIT> ) ; else if ( ExternalSymbolSDNode * E = dyn_cast < ExternalSymbolSDNode > ( Callee ) ) Callee = DAG . getTargetExternalSymbol ( E -> getSymbol ( ) , <STR_LIT> ) ; SDVTList NodeTys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . push_back ( Chain ) ; Ops . push_back ( Callee ) ; for ( unsigned i = <NUM_LIT> , e = RegsToPass . size ( ) ; i != e ; ++ i ) Ops . push_back ( DAG . getRegister ( RegsToPass [ i ] . first , RegsToPass [ i ] . second . getValueType ( ) ) ) ; if ( InFlag . getNode ( ) ) Ops . push_back ( InFlag ) ; Chain = DAG . getNode ( <STR_LIT> , dl , NodeTys , & Ops [ <NUM_LIT> ] , Ops . size ( ) ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; Chain = DAG . getCALLSEQ_END ( Chain , DAG . getConstant ( NumBytes , getPointerTy ( ) , true ) , DAG . getConstant ( <NUM_LIT> , getPointerTy ( ) , true ) , InFlag ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; return LowerCallResult ( Chain , InFlag , CallConv , isVarArg ,


<s> bool <ISA_LIT>InsertVSETVLI :: runOnMachineFunction ( MachineFunction & MF ) { const <ISA_LIT>Subtarget & ST = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( ! ST . hasVInstructions ( ) ) return false ; TII = ST . getInstrInfo ( ) ; MRI = & MF . getRegInfo ( ) ; assert ( BlockInfo . empty ( ) && <STR_LIT> ) ; BlockInfo . resize ( MF . getNumBlockIDs ( ) ) ; bool HaveVectorOp = false ; for ( const MachineBasicBlock & MBB : MF ) HaveVectorOp |= computeVLVTYPEChanges ( MBB ) ; if ( HaveVectorOp ) { for ( const MachineBasicBlock & MBB : MF ) { WorkList . push ( & MBB


<s> Register ScratchReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register AddrReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register IncrReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register MaskReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; AtomicOrdering Ordering = static_cast < AtomicOrdering > ( MI . getOperand ( <NUM_LIT> ) . getImm ( ) ) ; BuildMI ( LoopMBB , DL , TII -> get ( getLRForRMW32 ( Ordering ) ) , DestReg ) . addReg ( AddrReg ) ; switch ( BinOp ) { default : llvm_unreachable ( <STR_LIT> ) ; case AtomicRMWInst :: Xchg : BuildMI ( LoopMBB , DL , TII -> get ( <STR_LIT> ) , ScratchReg )

. addReg ( IncrReg ) . addImm ( <NUM_LIT> ) ;


<s> if ( ForceTopDown ) { SU = Top . pickOnlyChoice ( ) ; if ( ! SU ) { SchedCandidate TopCand ; CandResult TopResult = pickNodeFromQueue ( Top , DAG -> getTopRPTracker ( ) , TopCand ) ; assert ( TopResult != NoCand && <STR_LIT> ) ; ( void ) TopResult ; SU = TopCand . SU ; } IsTopNode = true ; } else if ( ForceBottomUp ) { SU = Bot . pickOnlyChoice ( ) ; if ( ! SU ) { SchedCandidate BotCand ; CandResult BotResult = pickNodeFromQueue ( Bot , DAG -> getBotRPTracker ( ) , BotCand ) ; assert ( BotResult != NoCand && <STR_LIT> ) ; ( void ) BotResult ; SU = BotCand . SU ; } IsTopNode = false ; } else { SU = pickNodeBidrectional ( IsTopNode ) ; } if ( SU -> isTopReady ( ) ) Top . removeReady ( SU ) ; if ( SU -> isBottomReady ( ) ) Bot . removeReady ( SU ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << ( IsTopNode ? <STR_LIT> : <STR_LIT> ) << <STR_LIT> << ( IsTopNode ? Top . CurrCycle : Bot . CurrCycle ) <<

<STR_LIT> << reportPackets ( ) << <STR_LIT> ;


<s> static unsigned int flags_from_code ( enum rtx_code code ) { switch ( code ) { case LT : case GE : return CC_FLAG_S ; case GT : case LE


<s> break ; case 'L' : if ( ! MI -> getOperand ( OpNo ) . isReg ( ) || OpNo + <NUM_LIT> == MI -> getNumOperands ( ) || ! MI -> getOperand ( OpNo + <NUM_LIT> ) . isReg ( ) ) return true ; ++ OpNo ; break ; case 'I' : if ( MI -> getOperand ( OpNo ) . isImm ( ) ) O << <STR_LIT> ; return false ; } } printOperand ( MI , OpNo , O


<s> continue ; } if ( insn_defines_reg ( regno1 , INVALID_REGNUM , prev ) ) return true ; else if ( insn_defines_reg ( regno2 , INVALID_REGNUM , prev ) ) return false ; prev = PREV_INSN ( prev ) ; } return false


<s> if ( ! ST -> hasMVEIntegerOps ( ) ) return false ; LI = & getAnalysis < LoopInfoWrapperPass > ( ) . getLoopInfo ( ) ; SmallVector < IntrinsicInst * , <NUM_LIT> > Gathers ; SmallVector < IntrinsicInst * , <NUM_LIT> > Scatters ; bool Changed = false ; for ( BasicBlock & BB : F ) { for ( Instruction & I : BB ) { IntrinsicInst * II = dyn_cast < IntrinsicInst > ( & I ) ; if ( II && II -> getIntrinsicID ( ) == <STR_LIT> && isa < FixedVectorType > ( II -> getType ( ) ) ) { Gathers . push_back ( II ) ; Changed |= optimiseAddress ( II -> getArgOperand ( <NUM_LIT> ) , II -> getParent ( ) ,


<s> ArrayRef < SGPRSpillVGPRCSR > getSGPRSpillVGPRs ( ) const { return SpillVGPRs


<s> do { unsigned IdxC = <NUM_LIT> ; if ( ! NA [ nax ] -> PTy -> isPointerTy ( ) ) { Type * Int32Ty = Type :: getInt32Ty ( * Ctx ) ; IdxList [ IdxC ++ ] = ConstantInt :: get ( Int32Ty , <NUM_LIT> ) ; } while ( ++ nax <= Num ) { GepNode * N = NA [ nax - <NUM_LIT> ] ; IdxList [ IdxC ++ ] = N -> Idx ; if ( nax < Num ) { Type * NextTy = next_type ( N -> PTy , N -> Idx ) ; if ( NextTy != NA [ nax ] -> PTy ) break ; } } ArrayRef < Value * > A ( IdxList , IdxC ) ; Type * InpTy = Input -> getType ( ) ; Type * ElTy = cast < PointerType > ( InpTy -> getScalarType ( ) ) -> getElementType ( ) ; NewInst = GetElementPtrInst :: Create ( ElTy , Input , A , <STR_LIT> , & * At ) ; NewInst -> setIsInBounds ( RN -> Flags & GepNode :: InBounds ) ; DEBUG ( dbgs ( ) << <STR_LIT> << * NewInst << '\n' ) ; Input = NewInst


<s> bool <ISA_LIT>InstrInfo :: isUnpredicatedTerminator ( const MachineInstr * MI ) const { if ( ! MI -> isTerminator ( ) ) return false ; if ( MI -> isBranch ( ) && ! MI -> isBarrier ( )


<s> MIB -> getOperand ( <NUM_LIT> ) . setIsDef ( true ) ; MachineBasicBlock * DestBB = MI -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; unsigned BrOpc = BBUtils -> isBBInRange ( MI , DestBB , <NUM_LIT> ) ? <STR_LIT> : <STR_LIT> ; MIB = BuildMI ( * MBB , MI , MI -> getDebugLoc ( ) , TII -> get ( BrOpc ) ) ; MIB . add ( MI -> getOperand ( <NUM_LIT> ) ) ; MIB . addImm ( <STR_LIT> ) ; MIB . addReg


<s> return true ; } if ( isZeroOrAllOnes ( N2 , AllOnes ) ) { Invert = true ; OtherOp = N1 ; return true ; } return false ; } case <STR_LIT> : if ( AllOnes ) return false ; case <STR_LIT> : { SDLoc dl ( N ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; CC = N -> getOperand ( <NUM_LIT> ) ; if ( CC . getValueType ( ) != <STR_LIT> ) return false ; Invert = ! AllOnes ; if ( AllOnes ) OtherOp = DAG . getConstant ( <NUM_LIT> , dl , VT ) ; else if ( N -> getOpcode ( ) == <STR_LIT> ) OtherOp = DAG . getConstant ( <NUM_LIT> , dl , VT ) ; else OtherOp = DAG . getConstant ( APInt :: getAllOnesValue ( VT


<s> } SDValue Flag ; SmallVector < SDValue , <NUM_LIT> > RetOps ( <NUM_LIT> , Chain ) ; for ( unsigned i = <NUM_LIT> ; i != e ; ++ i ) { CCValAssign & VA = RVLocs [ i ] ; assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; Chain = DAG . getCopyToReg ( Chain , dl , VA . getLocReg ( ) , OutVals [ i ] , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( VA . getLocReg ( ) , VA . getLocVT ( ) ) ) ; } if ( MF . getFunction ( ) . getAttributes ( ) . hasAttribute ( AttributeList :: FunctionIndex , Attribute :: Naked ) ) { return Chain ; } unsigned RetOpc = ( CallConv == CallingConv :: <ISA_LIT>_INTR || CallConv ==


<s> if ( CONSTANT_P ( op ) && letter != 'u' && letter != 's' && letter != 'r' && letter != 'S' && letter != 'B' ) fprintf ( file , <STR_LIT> ) ; rl78_print_operand_1 ( file , op , letter


<s> const SDValue OpsA [ ] = { MemAddr , Align , Reg0 , ImplDef , Pred , Reg0 , Chain } ; SDNode * VLdA = CurDAG -> getMachineNode ( QOpcodes0 [ OpcodeIndex ] , dl , ResTy , AddrTy , <STR_LIT> , OpsA ) ; Chain = SDValue ( VLdA , <NUM_LIT> ) ; Ops . push_back ( SDValue ( VLdA , <NUM_LIT> ) ) ; Ops . push_back ( Align ) ; if ( isUpdating ) { SDValue Inc = N -> getOperand ( AddrOpIdx + <NUM_LIT> ) ; assert ( isa < ConstantSDNode > ( Inc . getNode ( ) ) && <STR_LIT> ) ; ( void ) Inc ; Ops . push_back ( Reg0 ) ; } Ops . push_back ( SDValue ( VLdA , <NUM_LIT> ) ) ; Ops . push_back ( Pred ) ; Ops . push_back ( Reg0 ) ; Ops . push_back ( Chain ) ; VLd = CurDAG -> getMachineNode ( QOpcodes1 [ OpcodeIndex ] , dl , ResTys , Ops ) ; } MachineSDNode :: mmo_iterator MemOp = MF -> allocateMemRefsArray ( <NUM_LIT> ) ; MemOp [ <NUM_LIT> ] = cast < MemIntrinsicSDNode > ( N ) -> getMemOperand ( ) ; cast < MachineSDNode > ( VLd ) -> setMemRefs ( MemOp , MemOp + <NUM_LIT> ) ; if ( NumVecs == <NUM_LIT> ) return VLd ; SDValue SuperReg = SDValue ( VLd , <NUM_LIT> ) ; assert ( <STR_LIT> == <STR_LIT> + <NUM_LIT> && <STR_LIT> == <STR_LIT> + <NUM_LIT> && <STR_LIT> ) ; unsigned Sub0 = ( is64BitVector ? <STR_LIT> : <STR_LIT> ) ; for ( unsigned Vec = <NUM_LIT> ; Vec < NumVecs ; ++ Vec ) ReplaceUses ( SDValue ( N , Vec ) , CurDAG -> getTargetExtractSubreg ( Sub0 + Vec , dl , VT , SuperReg ) ) ; ReplaceUses ( SDValue ( N , NumVecs ) , SDValue ( VLd , <NUM_LIT>


<s> FINI_SECTION_FUNCTION void \ const_section ( ) \ { \ if ( ! USE_CONST_SECTION ) \ text_section ( ) ; \ else if ( in_section != in_const ) \ { \ fprintf ( asm_out_file , <STR_LIT> ,

CONST_SECTION_ASM_OP ) ; \ in_section = in_const ; \ } \ }


, ( __mmask8 ) __U , _MM_FROUND_CUR_DIRECTION ) ;


<s> const DataLayout * getDataLayout ( ) const override { return getSubtargetImpl ( ) -> getDataLayout (


<s> } else if ( type == TYPE_IMM ) { switch ( operand . encoding ) { default : break ; case ENCODING_IB : if ( immediate & <NUM_LIT> ) immediate |= ~ ( <NUM_LIT> ) ; break ; case ENCODING_IW : if ( immediate & <NUM_LIT> ) immediate |= ~ ( <NUM_LIT> ) ; break ; case ENCODING_ID : if ( immediate & <NUM_LIT> ) immediate |= ~ ( <NUM_LIT> ) ; break ; case ENCODING_IO : break ; } } switch ( type ) { case TYPE_XMM : mcInst . addOperand ( MCOperand :: createReg ( <STR_LIT> + ( immediate >> <NUM_LIT> ) ) ) ; return ; case TYPE_YMM : mcInst . addOperand ( MCOperand :: createReg ( <STR_LIT> + ( immediate >> <NUM_LIT> ) ) ) ; return ; case TYPE_ZMM : mcInst . addOperand ( MCOperand :: createReg ( <STR_LIT> + ( immediate >> <NUM_LIT> ) ) ) ; return ; default : break ; } if ( ! tryAddingSymbolicOperand ( immediate + pcrel , isBranch , insn . startLocation , insn . immediateOffset , insn . immediateSize , mcInst , Dis ) ) mcInst . addOperand ( MCOperand :: createImm ( immediate ) ) ; if ( type == TYPE_MOFFS ) { MCOperand segmentReg ; segmentReg = MCOperand :: createReg ( segmentRegnums [ insn . segmentOverride ] ) ; mcInst . addOperand


<s> SupportsDebugInformation = true ; DollarIsPC = true ; MinInstAlignment = <NUM_LIT> ; ExceptionsType = ExceptionHandling :: DwarfCFI ; ZeroDirective = <STR_LIT> ; Data64bitsDirective = is64Bit ? <STR_LIT>


<s> uint64_t CVal = Val . getZExtValue ( ) ; SDValue Vec = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , DAG . getConstant ( Lo_32 ( CVal ) , SL , <STR_LIT> ) , DAG . getConstant ( Hi_32 ( CVal ) , SL , <STR_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , SL , DestVT , Vec ) ; } break ; } case <STR_LIT> : { if ( DCI . getDAGCombineLevel ( ) < AfterLegalizeDAG ) break ; return performShlCombine ( N , DCI ) ; } case <STR_LIT> : { if ( DCI . getDAGCombineLevel ( ) < AfterLegalizeDAG ) break ; return performSrlCombine ( N , DCI ) ; } case <STR_LIT> : { if ( DCI . getDAGCombineLevel ( ) < AfterLegalizeDAG ) break ; return performSraCombine ( N , DCI ) ; } case <STR_LIT> : return performTruncateCombine ( N , DCI ) ; case <STR_LIT> : return performMulCombine ( N , DCI ) ; case <STR_LIT> : return performMulhsCombine ( N , DCI ) ; case <STR_LIT> : return performMulhuCombine ( N , DCI ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { if ( SDValue V = simplifyI24 ( N , DCI ) ) return V ; return SDValue ( ) ; } case <STR_LIT> : case <STR_LIT> : return performMulLoHi24Combine ( N , DCI ) ; case <STR_LIT> : return performSelectCombine ( N , DCI ) ; case <STR_LIT> : return performFNegCombine ( N , DCI ) ; case <STR_LIT> : return performFAbsCombine ( N , DCI ) ; case <STR_LIT> : case <STR_LIT> : { assert ( ! N -> getValueType ( <NUM_LIT> ) . isVector ( ) && <STR_LIT> ) ; ConstantSDNode * Width = dyn_cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ; if ( ! Width ) break ; uint32_t WidthVal = Width -> getZExtValue ( ) & <NUM_LIT> ; if ( WidthVal == <NUM_LIT> ) return DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; ConstantSDNode * Offset = dyn_cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ; if ( ! Offset ) break ; SDValue BitsFrom = N -> getOperand ( <NUM_LIT> ) ; uint32_t OffsetVal = Offset -> getZExtValue ( ) & <NUM_LIT> ; bool Signed = N -> getOpcode ( ) == <STR_LIT> ; if ( OffsetVal == <NUM_LIT> ) { unsigned SignBits = Signed ? ( <NUM_LIT> - WidthVal + <NUM_LIT> ) :


<s> <ISA_LIT>ELFMCAsmInfo :: <ISA_LIT>ELFMCAsmInfo ( const Triple & T ) { bool is64Bit = T . getArch ( ) == Triple :: x86_64 ; bool isX32 = T . isX32 ( ) ; CodePointerSize = ( is64Bit && ! isX32 ) ? <NUM_LIT> : <NUM_LIT> ; CalleeSaveStackSlotSize = is64Bit ? <NUM_LIT> : <NUM_LIT> ; AssemblerDialect = AsmWriterFlavor ; TextAlignFillValue = <NUM_LIT> ; SupportsDebugInformation = true ; ExceptionsType = ExceptionHandling


<s> int get_ta ( rtx ta ) { if ( INTVAL ( ta ) == TAIL_ANY ) return INVALID_ATTRIBUTE ; return INTVAL (


<s> union { uint32_t I ; float F ; } FPUnion ; uint8_t Sign = ( Imm >> <NUM_LIT> ) & <NUM_LIT> ; uint8_t Exp = ( Imm >> <NUM_LIT> ) & <NUM_LIT> ; uint8_t Mantissa = Imm & <NUM_LIT> ; FPUnion . I = <NUM_LIT> ; FPUnion . I |= Sign << <NUM_LIT> ; FPUnion . I |= ( ( Exp & <NUM_LIT> ) != <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ) << <NUM_LIT> ; FPUnion . I |= ( ( Exp & <NUM_LIT> ) != <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> )


<s> if ( GET_CODE ( pattern ) != PARALLEL || get_attr_type ( insn ) != TYPE_SFUNC ) return NULL_RTX ; for ( reg_part = NULL_RTX , i = XVECLEN ( pattern , <NUM_LIT> ) - <NUM_LIT> ; i >= <NUM_LIT> ; i -- ) { part = XVECEXP ( pattern , <NUM_LIT> , i ) ; if ( GET_CODE ( part ) == USE && GET_MODE ( XEXP ( part , <NUM_LIT> ) ) == SImode ) reg_part = part ; } if ( ! reg_part ) return NULL_RTX ; reg = XEXP ( reg_part , <NUM_LIT> ) ; for ( i = XVECLEN ( pattern , <NUM_LIT> ) - <NUM_LIT> ; i >= <NUM_LIT> ; i -- ) { part = XVECEXP ( pattern , <NUM_LIT> , i


<s> return TargetTransformInfo ( <ISA_LIT>TTIImpl ( this , F ) ) ; } )


<s> bool <ISA_LIT>AsmPrinter :: runOnMachineFunction ( MachineFunction & MF ) { this -> MF = & MF ; SetupMachineFunction ( MF ) ; EmitConstantPool ( MF . getConstantPool ( ) ) ; EmitJumpTableInfo ( MF . getJumpTableInfo ( ) , MF ) ; emitFunctionStart ( MF ) ; DW -> BeginFunction ( & MF ) ; for ( MachineFunction :: const_iterator I = MF . begin ( ) , E = MF . end ( ) ; I != E ; ++ I ) { if ( I != MF . begin ( ) ) { printBasicBlockLabel ( I , true , true ) ; O << '\n' ; } for ( MachineBasicBlock :: const_iterator II = I -> begin ( ) , E = I -> end ( ) ; II != E ; ++ II ) { O << <STR_LIT> ; printMachineInstruction ( II


<s> Inst . addOperand ( MCOperand :: createImm ( Field << <NUM_LIT> ) ) ; return MCDisassembler ::


<s> return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case


<s> unsigned Src = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned In128 = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * MBB , MI , DL , TII -> get ( TargetOpcode :: IMPLICIT_DEF ) , In128 ) ; if ( ClearEven ) { unsigned NewIn128 = MRI . createVirtualRegister ( & <STR_LIT> ) ; unsigned Zero64 = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * MBB , MI , DL , TII -> get ( <STR_LIT> ) , Zero64 ) . addImm ( <NUM_LIT> ) ; BuildMI ( * MBB , MI , DL , TII -> get ( TargetOpcode :: INSERT_SUBREG ) , NewIn128 ) . addReg

( In128 ) . addReg ( Zero64 ) . addImm ( <STR_LIT> ) ;


<s> virtual const TargetData * getTargetData ( ) const { return & DataLayout


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT>


<s> addPass ( create<ISA_LIT>DelaySlotFillerPass ( get<ISA_LIT>TargetMachine ( )


<s> return DecodeGPRRegisterClass ( Inst , RegNo , Address ,


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : CC = ( CC < <NUM_LIT> ) ? ( CC + <NUM_LIT> ) : CC ; break ; } O << <ISA_LIT>ARCCondCodeToString ( ( <STR_LIT> ) CC


<s> static bool rs6000_use_blocks_for_constant_p ( machine_mode mode , const_rtx


<s> static int count = <NUM_LIT> ; sprintf ( unicosmk_section_buf , <STR_LIT> , count ++ ) ; return


<s> return ( __m256d ) __builtin_ia32_broadcastf64x2_256_mask ( ( __v2df ) __A , ( __v4df ) _mm256_undefined_pd ( ) , ( __mmask8


<s> assert ( NumNOPBytes % <NUM_LIT> == <NUM_LIT> && <STR_LIT> ) ; const MachineBasicBlock & MBB = * MI . getParent ( ) ; MachineBasicBlock :: const_iterator MII ( MI ) ; ++ MII ; while ( NumNOPBytes > <NUM_LIT> ) { if ( MII == MBB . end ( ) || MII -> isCall ( ) || MII -> getOpcode ( ) == <STR_LIT> || MII -> getOpcode ( ) ==

TargetOpcode :: PATCHPOINT || MII -> getOpcode ( ) == TargetOpcode :: STACKMAP ) break ;


<s> if ( MI . mayLoad ( ) && ! MI . isInvariantLoad ( & AA ) ) Read = true ; if ( MI . mayStore ( ) ) { Write = true ; for ( auto MMO : MI . memoperands ( ) ) { const MachinePointerInfo & MPI = MMO -> getPointerInfo ( ) ; if ( MPI . V . is < const PseudoSourceValue * > ( ) ) { auto PSV = MPI . V . get < const PseudoSourceValue * > ( ) ; if ( const ExternalSymbolPseudoSourceValue * EPSV = dyn_cast < ExternalSymbolPseudoSourceValue > ( PSV ) ) if ( StringRef ( EPSV -> getSymbol ( ) ) == <STR_LIT> ) StackPointer = true ; } } } else if ( MI . hasOrderedMemoryRef ( ) ) { switch ( MI . getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case


<s> static rtx m32c_subreg ( enum machine_mode outer , rtx x , enum machine_mode inner , int byte ) { int r , nr = - <NUM_LIT> ; if ( GET_CODE ( x ) == SUBREG && SUBREG_BYTE ( x ) == <NUM_LIT> && GET_CODE ( SUBREG_REG ( x ) ) == MEM && ( GET_MODE_SIZE ( GET_MODE ( x ) ) == GET_MODE_SIZE ( GET_MODE ( SUBREG_REG ( x ) ) ) ) ) { rtx oldx = x ; x = gen_rtx_MEM ( GET_MODE ( x ) , XEXP ( SUBREG_REG ( x ) , <NUM_LIT> ) ) ; MEM_COPY_ATTRIBUTES ( x , SUBREG_REG ( oldx ) ) ; } if ( GET_CODE ( x ) == MEM && ( GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == PRE_DEC || GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == POST_INC ) ) return gen_rtx_MEM ( outer , XEXP ( x , <NUM_LIT> ) ) ; if ( GET_CODE ( x ) == SUBREG && GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == MEM && ( GET_CODE ( XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) ) == PRE_DEC || GET_CODE ( XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) ) == POST_INC ) ) return gen_rtx_MEM ( outer , XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) ) ; if ( GET_CODE ( x ) != REG ) return simplify_gen_subreg ( outer , x , inner , byte ) ; r = REGNO ( x ) ; if ( r >= FIRST_PSEUDO_REGISTER || r == AP_REGNO ) return simplify_gen_subreg ( outer , x , inner , byte ) ; if ( IS_MEM_REGNO ( r ) ) return simplify_gen_subreg ( outer , x , inner , byte ) ; if ( byte == <NUM_LIT> ) nr = r ; else if ( outer == HImode ) { if ( r == R0_REGNO && byte == <NUM_LIT>


<s> std :: vector < std :: string > modr_i2_dmod ( Rn a ) { return D ( <STR_LIT> , R ( a


<s> addPass ( create<ISA_LIT>PreEmitPeepholePass ( ) ) ; addPass ( create<ISA_LIT>ExpandISELPass ( ) ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) addPass ( create<ISA_LIT>EarlyReturnPass


<s> SDValue ArgValue2 ; if ( NextVA . isMemLoc ( ) ) { MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; int FI = MFI -> CreateFixedObject ( <NUM_LIT> , NextVA . getLocMemOffset ( ) , true ) ; SDValue FIN = DAG . getFrameIndex ( FI , getPointerTy ( DAG . getDataLayout ( ) ) ) ; ArgValue2 = DAG . getLoad ( <STR_LIT> , dl , Root , FIN , MachinePointerInfo :: getFixedStack ( DAG . getMachineFunction ( ) , FI ) , false , false , false , <NUM_LIT> ) ; } else { Reg = MF . addLiveIn ( NextVA . getLocReg ( ) , RC ) ; ArgValue2 = DAG . getCopyFromReg ( Root , dl , Reg , <STR_LIT> ) ; } if ( ! Subtarget -> isLittle ( ) ) std :: swap ( ArgValue ,


<s> RegisterAsmPrinter < <ISA_LIT>AsmPrinter > W ( getTheARM64_32Target ( ) ) ; RegisterAsmPrinter < <ISA_LIT>AsmPrinter > V ( getThe<ISA_LIT>_32Target


<s> default_elf_asm_named_section ( sname , flags , decl ) ; return ; } default_elf_asm_named_section ( new_prefix , flags , decl ) ; return ; } if ( ! avr_need_copy_data_p ) avr_need_copy_data_p = ( startswith ( name , <STR_LIT> ) || startswith ( name , <STR_LIT> ) ) ; if ( ! avr_need_copy_data_p && avr_arch -> flash_pm_offset == <NUM_LIT> ) avr_need_copy_data_p = ( startswith ( name , <STR_LIT> ) ||


<s> static MachineBasicBlock * emitSplitF64Pseudo ( MachineInstr & MI , MachineBasicBlock * BB ) { assert ( MI . getOpcode ( ) == <STR_LIT> && <STR_LIT> ) ; MachineFunction & MF = * BB -> getParent ( ) ; DebugLoc DL = MI . getDebugLoc ( ) ; const TargetInstrInfo & TII = * MF . getSubtarget ( ) . getInstrInfo ( ) ; const TargetRegisterInfo * RI = MF . getSubtarget ( ) . getRegisterInfo ( ) ; Register LoReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register HiReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; const TargetRegisterClass * SrcRC = & <STR_LIT> ; int FI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) -> getMoveF64FrameIndex ( ) ; TII . storeRegToStackSlot ( * BB , MI , SrcReg , MI . getOperand ( <NUM_LIT> ) . isKill (


<s> uint64_t Offset = ( ( InstDesc . TSFlags & <STR_LIT> ) == <STR_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; if ( InstDesc . getOpcode ( ) == <STR_LIT> )


<s> __builtin_neon_vst4v16qi ( ( __builtin_neon_qi * ) __a ,


<s> if ( Flags . isByVal ( ) ) return CreateCopyOfByValArgument ( Arg , PtrOff , Chain , Flags , DAG , DL ) ; return DAG . getStore ( Chain , DL , Arg , PtrOff , MachinePointerInfo :: getStack ( DAG . getMachineFunction


<s> if ( PIdx == - <NUM_LIT> ) { PredReg = <NUM_LIT> ; return <STR_LIT> ; } PredReg = MI . getOperand ( PIdx


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return


<s> for ( const SDValue & Op : Ops ) IntOps . push_back ( Op ) ; return DAG . getNode ( <STR_LIT> , dl


<s> static void rs6000_instantiate_decls ( void ) { if ( cfun -> machine -> sdmode_stack_slot != NULL_RTX

) instantiate_decl_rtl ( cfun -> machine -> sdmode_stack_slot ) ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { unsigned Rt = Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Rt2 = Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( Rt == Rt2 ) return Error ( Loc [ <NUM_LIT> ] , <STR_LIT> ) ; break ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { unsigned Rt = Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Rt2 = Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Rn = Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( RI -> isSubRegisterEq ( Rn , Rt ) ) return Error ( Loc [ <NUM_LIT> ] , <STR_LIT> <STR_LIT> ) ; if ( RI -> isSubRegisterEq ( Rn , Rt2 ) ) return Error ( Loc [ <NUM_LIT> ] , <STR_LIT> <STR_LIT> ) ; break ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { unsigned Rt = Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Rn = Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( RI -> isSubRegisterEq ( Rn , Rt ) ) return Error ( Loc [ <NUM_LIT> ] , <STR_LIT> <STR_LIT> ) ; break ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { unsigned Rt = Inst . getOperand ( <NUM_LIT> ) . getReg


<s> if ( decl && DECL_SECTION_NAME ( decl ) ) { const char * name = DECL_SECTION_NAME ( decl ) ; if ( DECL_COMDAT_GROUP ( decl ) && strncmp ( name , <STR_LIT> , <NUM_LIT> ) == <NUM_LIT> ) { char * rname = ASTRDUP ( name ) ; rname [ <NUM_LIT> ] = 'd' ; return get_section ( rname , SECTION_LINKONCE | SECTION_WRITE , decl ) ; } else if ( flag_function_sections && flag_data_sections && strncmp ( name , <STR_LIT> , <NUM_LIT> ) == <NUM_LIT> ) { char * rname = ASTRDUP ( name ) ; memcpy ( rname + <NUM_LIT> , <STR_LIT> , <NUM_LIT> ) ; return get_section ( rname , SECTION_WRITE , decl ) ; } } return data_section


<s> BuildMI ( MBB , & MI , MI . getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addDef ( <STR_LIT> ) . addUse ( <STR_LIT> ) . addUse ( <STR_LIT> ) ; BuildMI ( MBB , & MI , MI . getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addDef ( <STR_LIT> ) . addUse

( <STR_LIT> ) . addImm ( - <NUM_LIT> ) ;


<s> if ( need_atomic_barrier_p ( model , true ) ) emit_insn


<s> if ( GET_CODE ( addr ) == UNSPEC && XINT ( addr , <NUM_LIT> ) == UNSPEC_FUSION_ADDIS ) { lo = XVECEXP ( addr , <NUM_LIT> , <NUM_LIT> ) ; hi = gen_rtx_HIGH ( Pmode


<s> bool Hash = false ; if ( Parser . getTok ( ) . is ( AsmToken :: Hash ) ) { Parser . Lex ( ) ; Hash = true ; } bool isNegative = false ; if ( Parser . getTok ( ) . is ( AsmToken :: Minus ) ) { isNegative = true ; Parser . Lex ( ) ; } const AsmToken & Tok = Parser . getTok ( ) ; if ( Tok . is ( AsmToken :: Real ) ) { APFloat RealVal ( APFloat :: IEEEdouble , Tok . getString ( ) ) ; uint64_t IntVal = RealVal . bitcastToAPInt ( ) . getZExtValue ( ) ; IntVal ^= ( uint64_t ) isNegative << <NUM_LIT> ; int Val = <STR_LIT> ( APInt ( <NUM_LIT> , IntVal ) ) ; Parser . Lex ( ) ; if ( Val == - <NUM_LIT> && ! RealVal . isZero ( ) ) { TokError ( <STR_LIT> ) ; return MatchOperand_ParseFail ; } Operands . push_back ( <ISA_LIT>Operand :: CreateFPImm ( Val , S , getContext ( ) ) ) ; return MatchOperand_Success ; } if ( Tok . is ( AsmToken :: Integer ) ) { int64_t Val ; if ( ! isNegative && Tok . getString ( ) . startswith ( <STR_LIT> ) ) { Val = Tok . getIntVal ( ) ; if ( Val > <NUM_LIT> || Val


<s> AFI = Fn . getInfo < <ISA_LIT>FunctionInfo > ( ) ; isThumb = AFI -> isThumbFunction ( ) ; HasFarJump = false ; Fn . RenumberBlocks ( ) ; AFI -> setAlign ( isThumb ? <NUM_LIT> : <NUM_LIT> ) ; std :: vector < MachineInstr * > CPEMIs ; if ( ! MCP . isEmpty ( ) ) { DoInitialPlacement ( Fn , CPEMIs ) ; if ( isThumb ) AFI -> setAlign ( <NUM_LIT> ) ; } AFI -> initConstPoolEntryUId ( CPEMIs . size ( ) ) ; InitialFunctionScan ( Fn , CPEMIs ) ; CPEMIs . clear ( ) ; RemoveUnusedCPEntries ( ) ; bool MadeChange = false ; while ( true ) { bool Change = false ; for ( unsigned i = <NUM_LIT> , e = CPUsers . size ( ) ; i != e ; ++ i ) Change |= HandleConstantPoolUser ( Fn , i ) ; DEBUG ( dumpBBs ( ) ) ; for ( unsigned i = <NUM_LIT> , e = ImmBranches . size ( ) ; i != e ; ++ i ) Change |= FixUpImmediateBr ( Fn , ImmBranches [ i ] ) ; DEBUG ( dumpBBs ( ) ) ; if ( ! Change ) break ; MadeChange = true ; } verify ( Fn ) ; if ( ! HasFarJump && AFI -> isLRSpilledForFarJump ( ) && isThumb ) MadeChange |= UndoLRSpillRestore ( ) ; BBSizes . clear ( ) ; BBOffsets . clear ( ) ; WaterList . clear ( ) ; CPUsers . clear ( ) ; CPEntries . clear ( )


<s> MachineInstrBuilder MIB ; MIB = BuildMI ( LoadCmpBB , DL , TII -> get ( LDREXD ) ) ; addExclusiveRegPair ( MIB , Dest , RegState :: Define , IsThumb , TRI ) ; MIB . addReg ( Addr . getReg ( ) ) ; AddDefaultPred ( MIB ) ; unsigned CMPrr = IsThumb ? <STR_LIT> : <STR_LIT> ; AddDefaultPred ( BuildMI ( LoadCmpBB , DL , TII -> get ( CMPrr ) ) . addReg ( DestLo , getKillRegState ( Dest . isDead ( ) ) ) . addReg ( DesiredLo , getKillRegState ( Desired . isDead ( ) ) ) ) ; BuildMI ( LoadCmpBB , DL , TII -> get ( CMPrr ) ) . addReg ( DestHi , getKillRegState ( Dest . isDead ( ) ) ) . addReg ( DesiredHi , getKillRegState ( Desired . isDead ( ) ) ) . addImm ( <STR_LIT> ) . addReg ( <STR_LIT> , RegState :: Kill ) ; unsigned Bcc = IsThumb ? <STR_LIT> : <STR_LIT> ; BuildMI ( LoadCmpBB , DL , TII -> get ( Bcc ) ) . addMBB ( DoneBB ) . addImm ( <STR_LIT> ) . addReg ( <STR_LIT> , RegState :: Kill ) ; LoadCmpBB -> addSuccessor ( DoneBB ) ; LoadCmpBB -> addSuccessor ( StoreBB ) ; StoreBB -> addLiveIn ( Addr . getReg ( ) ) ; StoreBB -> addLiveIn ( New . getReg ( ) ) ; addPostLoopLiveIns ( StoreBB , LiveRegs ) ; unsigned STREXD = IsThumb ? <STR_LIT> : <STR_LIT> ; MIB = BuildMI ( StoreBB , DL , TII -> get ( STREXD ) , StatusReg ) ; addExclusiveRegPair ( MIB , New , <NUM_LIT> , IsThumb , TRI ) ; MIB . addOperand ( Addr ) ; AddDefaultPred ( MIB ) ; unsigned CMPri = IsThumb ? <STR_LIT> : <STR_LIT> ; AddDefaultPred ( BuildMI ( StoreBB , DL , TII -> get ( CMPri ) ) . addReg ( StatusReg , RegState :: Kill ) . addImm ( <NUM_LIT> ) ) ; BuildMI ( StoreBB , DL , TII -> get ( Bcc ) ) . addMBB ( LoadCmpBB ) . addImm ( <STR_LIT> ) . addReg ( <STR_LIT> , RegState :: Kill ) ; StoreBB -> addSuccessor ( LoadCmpBB ) ; StoreBB -> addSuccessor ( DoneBB ) ; DoneBB -> splice ( DoneBB -> end ( ) , & MBB , MI , MBB . end ( ) ) ; DoneBB -> transferSuccessors ( & MBB ) ; addPostLoopLiveIns ( DoneBB , LiveRegs ) ; MBB . addSuccessor ( LoadCmpBB ) ; NextMBBI = MBB . end ( ) ; MI . eraseFromParent (


<s> unsigned Base = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; Reg = getReg ( Decoder , <STR_LIT> , Reg ) ; Base = getReg ( Decoder , <STR_LIT> , Base ) ; if ( Inst . getOpcode ( ) == <STR_LIT> ) { Inst . addOperand ( MCOperand ::


<s> PrivateLabelPrefix = <STR_LIT> ; SeparatorString = <STR_LIT> ; CommentString = <STR_LIT> ; CalleeSaveStackSlotSize = <NUM_LIT> ; CodePointerSize = IsILP32 ? <NUM_LIT> : <NUM_LIT> ; AlignmentIsInBytes = false ; UsesELFSectionDirectiveForBSS = true ; SupportsDebugInformation = true ; UseDataRegionDirectives = true ; ExceptionsType = ExceptionHandling ::


<s> static FunctionPass * createBasicSGPRRegisterAllocator (


<s> SDLoc DL ( & St ) ; SDValue BasePtr = St . getBasePtr ( ) ; uint64_t BaseOffset = <NUM_LIT> ; const MachinePointerInfo & PtrInfo = St . getPointerInfo ( ) ; SDValue NewST1 = DAG . getStore ( St . getChain ( ) , DL , SplatVal , BasePtr , PtrInfo , OrigAlignment , St . getMemOperand ( ) -> getFlags ( ) ) ; if ( BasePtr -> getOpcode ( ) == <STR_LIT> && isa < ConstantSDNode > ( BasePtr -> getOperand ( <NUM_LIT> ) ) ) { BaseOffset = cast < ConstantSDNode > ( BasePtr -> getOperand ( <NUM_LIT> ) ) -> getSExtValue ( ) ; BasePtr = BasePtr -> getOperand ( <NUM_LIT> ) ; } unsigned Offset = EltOffset ; while ( -- NumVecElts ) { unsigned Alignment = MinAlign ( OrigAlignment , Offset ) ; SDValue OffsetPtr = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , BasePtr , DAG . getConstant ( BaseOffset + Offset , DL , <STR_LIT> ) ) ; NewST1 = DAG . getStore ( NewST1 . getValue ( <NUM_LIT> ) , DL , SplatVal , OffsetPtr , PtrInfo

. getWithOffset ( Offset ) , Alignment , St . getMemOperand ( ) -> getFlags ( ) ) ;


<s> if ( isToken ( Kind ) ) { lex ( ) ; return true ; } return


<s> BuildMI ( BB , DL , TII . get ( <STR_LIT> ) , PromotedReg0 ) . addReg ( Reg ) ; BuildMI ( BB , DL , TII . get ( <STR_LIT> ) , PromotedReg1 ) . addReg ( PromotedReg0 ) . addImm ( <NUM_LIT> ) ; BuildMI ( BB , DL , TII . get ( RShiftOp ) , PromotedReg2 ) . addReg ( PromotedReg1 ) . addImm ( <NUM_LIT> ) ; return PromotedReg2


<s> if ( DAG . ComputeNumSignBits ( In ) < InVT . getScalarSizeInBits ( ) ) { MVT ExtVT = <STR_LIT> ( <STR_LIT> , InVT . getSizeInBits ( ) / <NUM_LIT> ) ; In = DAG . getNode ( <STR_LIT> , DL , ExtVT , DAG . getBitcast ( ExtVT , In ) , DAG . getConstant ( ShiftInx , DL , ExtVT ) ) ; In = DAG . getBitcast ( InVT , In ) ; } return DAG . getNode ( <STR_LIT> , DL , VT , DAG . getConstant ( <NUM_LIT> , DL , InVT ) , In , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; } assert ( ( InVT . is256BitVector ( ) || InVT . is128BitVector ( ) ) && <STR_LIT> ) ; unsigned NumElts = InVT . getVectorNumElements ( ) ; assert ( ( NumElts == <NUM_LIT> || NumElts == <NUM_LIT> ) && <STR_LIT> ) ; if ( NumElts == <NUM_LIT> && ! Subtarget . canExtendTo512DQ ( ) ) { if ( InVT == <STR_LIT> ) { InVT = <STR_LIT> ; In = DAG . getNode ( <STR_LIT> , DL , InVT , In ) ; } SDValue Lo = extract128BitVector ( In , <NUM_LIT> , DAG , DL ) ; SDValue Hi = extract128BitVector ( In , <NUM_LIT> , DAG , DL ) ; Lo = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Lo ) ; Hi = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Hi ) ; return DAG . getNode ( <STR_LIT> , DL , VT , Lo , Hi ) ; } MVT EltVT = Subtarget . hasVLX ( ) ? <STR_LIT> : <STR_LIT> ( <NUM_LIT> / NumElts ) ; MVT ExtVT = <STR_LIT> ( EltVT , NumElts ) ; In = DAG . getNode ( <STR_LIT> , DL


<s> SDNodeTreeBuilder b ( Op , & DAG ) ; if ( VT == <STR_LIT> ) { SDValue A1 = b . BITCAST ( Op . getOperand ( <NUM_LIT> ) , FullVT ) ; SDValue A2 = b . BITCAST ( Op . getOperand ( <NUM_LIT>


<s> const char * <ISA_LIT>AsmPrinter :: getCurrentABIString ( ) const { switch ( Subtarget -> getABI ( ) . GetEnumValue ( ) ) { case <ISA_LIT>ABIInfo :: ABI :: O32 : return <STR_LIT> ; case <ISA_LIT>ABIInfo :: ABI :: N32 : return <STR_LIT> ; case <ISA_LIT>ABIInfo :: ABI :: N64 : return <STR_LIT> ; case <ISA_LIT>ABIInfo :: ABI :: EABI : return <STR_LIT> ; default : llvm_unreachable (


<s> bool <ISA_LIT>RegisterInfo :: trackLivenessAfterRegAlloc ( const


<s> SDValue RHS = N -> getOperand ( <NUM_LIT> ) ; if ( N -> getOpcode ( ) == <STR_LIT> ) { if ( isa < ConstantSDNode > ( LHS ) ) { std :: swap ( LHS , RHS ) ; } } if ( N -> getOpcode ( ) == <STR_LIT> ) { ConstantSDNode * ShlRHS = dyn_cast < ConstantSDNode > ( RHS ) ; if ( ! ShlRHS ) { return SDValue ( ) ; } APInt ShiftAmt = ShlRHS -> getAPIntValue ( ) ; unsigned BitWidth = MulType . getSizeInBits ( ) ; if ( ShiftAmt . sge ( <NUM_LIT> ) && ShiftAmt . slt ( BitWidth ) ) { APInt MulVal = APInt ( BitWidth , <NUM_LIT> ) << ShiftAmt ; RHS = DCI . DAG . getConstant ( MulVal , DL , MulType ) ; } else { return SDValue ( ) ; } } bool Signed ; if ( ! AreMulWideOperandsDemotable ( LHS , RHS , OptSize , Signed ) ) { return SDValue ( ) ; } EVT DemotedVT ; if ( MulType == <STR_LIT> ) { DemotedVT = <STR_LIT>


<s> if ( ! isImm ( ) ) return false ; const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; if ( ! CE ) return false ; int64_t Value = CE ->


<s> temp . val [ <NUM_LIT> ] = vcombine_p16 ( val . val [ <NUM_LIT> ] , vcreate_p16 ( __AARCH64_UINT64_C ( <NUM_LIT> ) ) ) ; __o = __builtin_aarch64_set_qregoiv8hi ( __o , ( int16x8_t ) temp


<s> if ( ! MI . isTransient ( ) ) ++ Count ; Flags . setSExtIdx ( - <NUM_LIT> ) ; if ( areCandidatesToMergeOrPair ( FirstMI , MI , Flags , TII ) && getLdStOffsetOp ( MI ) . isImm ( ) ) { assert ( MI . mayLoadOrStore ( ) && <STR_LIT> ) ; Register MIBaseReg = getLdStBaseOp ( MI ) . getReg ( ) ; int MIOffset = getLdStOffsetOp ( MI ) . getImm ( ) ; bool MIIsUnscaled = TII -> isUnscaledLdSt ( MI ) ; if ( IsUnscaled != MIIsUnscaled ) { int MemSize = getMemScale ( MI ) ; if ( MIIsUnscaled ) { if ( MIOffset % MemSize ) { LiveRegUnits :: accumulateUsedDefed ( MI , ModifiedRegUnits , UsedRegUnits , TRI ) ; MemInsns . push_back ( & MI ) ; continue ; } MIOffset /= MemSize ; } else { MIOffset *= MemSize ; } } if ( BaseReg == MIBaseReg && ( ( Offset == MIOffset + OffsetStride ) || ( Offset + OffsetStride == MIOffset ) ) ) { int MinOffset = Offset < MIOffset ? Offset : MIOffset ; if ( FindNarrowMerge ) { if ( ( ! IsUnscaled && alignTo ( MinOffset , <NUM_LIT> ) != MinOffset ) || ( IsPromotableZeroStore && Reg != getLdStRegOp ( MI ) . getReg ( ) ) ) { LiveRegUnits :: accumulateUsedDefed ( MI , ModifiedRegUnits , UsedRegUnits , TRI ) ; MemInsns . push_back ( & MI ) ; continue ; } } else { if ( ! inBoundsForPair ( IsUnscaled , MinOffset , OffsetStride ) ) { LiveRegUnits :: accumulateUsedDefed ( MI , ModifiedRegUnits , UsedRegUnits , TRI ) ; MemInsns . push_back ( & MI ) ; continue ; } if ( IsUnscaled && ( alignTo ( MinOffset , OffsetStride ) != MinOffset ) ) { LiveRegUnits :: accumulateUsedDefed ( MI , ModifiedRegUnits , UsedRegUnits , TRI ) ; MemInsns . push_back ( & MI ) ; continue ; } } if ( MayLoad && Reg == getLdStRegOp ( MI ) . getReg ( ) ) { LiveRegUnits :: accumulateUsedDefed ( MI , ModifiedRegUnits , UsedRegUnits ,


<s> } SDValue IncV = CurDAG -> getTargetConstant ( Inc , dl , <STR_LIT> ) ; MachineSDNode :: mmo_iterator MemOp = MF -> allocateMemRefsArray ( <NUM_LIT> ) ; MemOp [ <NUM_LIT> ] = LD -> getMemOperand ( ) ; auto getExt64 = [ this , ExtType ] ( MachineSDNode * N , const SDLoc & dl ) -> MachineSDNode * { if ( ExtType == <STR_LIT> || ExtType == <STR_LIT> ) { SDValue Zero = CurDAG -> getTargetConstant ( <NUM_LIT> , dl , <STR_LIT> ) ; return CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , Zero , SDValue ( N , <NUM_LIT> ) ) ; } if ( ExtType == <STR_LIT> ) return CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , SDValue ( N , <NUM_LIT> ) ) ; return N ; } ; SDValue From [ <NUM_LIT> ] = { SDValue ( LD , <NUM_LIT> ) , SDValue ( LD , <NUM_LIT> ) , SDValue ( LD , <NUM_LIT> ) } ; SDValue To [ <NUM_LIT> ] ; EVT ValueVT = LD -> getValueType ( <NUM_LIT> ) ; if ( ValueVT == <STR_LIT> && ExtType != <STR_LIT> ) { assert ( LoadedVT . getSizeInBits ( ) <= <NUM_LIT> ) ; ValueVT = <STR_LIT> ; } if ( IsValidInc ) { MachineSDNode * L = CurDAG -> getMachineNode ( Opcode , dl , ValueVT , <STR_LIT> , <STR_LIT> , Base , IncV , Chain ) ; L -> setMemRefs ( MemOp , MemOp + <NUM_LIT> ) ; To [ <NUM_LIT> ] = SDValue ( L , <NUM_LIT> ) ; To [ <NUM_LIT> ] = SDValue ( L , <NUM_LIT> ) ; if ( LD -> getValueType ( <NUM_LIT> ) == <STR_LIT> ) L = getExt64 ( L , dl ) ; To [ <NUM_LIT> ] = SDValue ( L , <NUM_LIT> ) ; } else { SDValue Zero = CurDAG -> getTargetConstant ( <NUM_LIT> , dl , <STR_LIT> ) ; MachineSDNode * L = CurDAG -> getMachineNode ( Opcode , dl , ValueVT , <STR_LIT> , Base , Zero , Chain ) ; L -> setMemRefs ( MemOp , MemOp + <NUM_LIT> ) ; To [ <NUM_LIT> ] = SDValue ( L , <NUM_LIT> ) ; MachineSDNode * A = CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , Base , IncV ) ; To [ <NUM_LIT> ] = SDValue ( A , <NUM_LIT> ) ; if ( LD -> getValueType ( <NUM_LIT> ) == <STR_LIT> ) L = getExt64 ( L ,


<s> enum immediate_class c = classify_immediate ( x , mode ) ; return c == IC_CPAT ; } return


<s> const <ISA_LIT>SelectionDAGInfo * getSelectionDAGInfo ( )


<s> while ( MBBI == MBB -> begin ( ) ) { if ( MBB == MBB -> getParent ( ) -> begin ( ) ) return nullptr ; MBB = MBB -> getPrevNode ( ) ; MBBI = MBB -> end


<s> SDValue FractPart = DAG . getNode ( <STR_LIT> , DL , VT , DAG . getNode ( <STR_LIT> , DL , VT , Arg , DAG . getConstantFP ( <NUM_LIT> / M_PI , DL , VT ) ) ) ; switch ( Op . getOpcode ( ) ) { case <STR_LIT> : return DAG . getNode ( <STR_LIT> , SDLoc ( Op ) , VT , FractPart ) ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , SDLoc ( Op


<s> report_fatal_error ( <STR_LIT> ) ; case GlobalValue :: LinkOnceAnyLinkage : case GlobalValue :: LinkOnceODRLinkage : case GlobalValue :: WeakAnyLinkage : case GlobalValue :: WeakODRLinkage : case GlobalValue :: ExternalLinkage : case GlobalValue :: CommonLinkage : emitArrayBound ( GVSym , GV ) ; OutStreamer -> EmitSymbolAttribute ( GVSym , MCSA_Global ) ; if ( GV -> hasWeakLinkage ( ) || GV -> hasLinkOnceLinkage ( ) || GV -> hasCommonLinkage ( ) ) OutStreamer -> EmitSymbolAttribute ( GVSym , MCSA_Weak ) ; LLVM_FALLTHROUGH ; case GlobalValue :: InternalLinkage : case GlobalValue :: PrivateLinkage : break ; default : llvm_unreachable ( <STR_LIT> ) ; } EmitAlignment ( std :: max ( Alignment , Align ( <NUM_LIT> ) ) , GV ) ; if ( GV -> isThreadLocal ( ) ) { report_fatal_error ( <STR_LIT> ) ; } unsigned Size = DL . getTypeAllocSize ( C -> getType ( ) ) ; if ( MAI -> hasDotTypeDotSizeDirective ( ) ) { OutStreamer -> EmitSymbolAttribute ( GVSym , MCSA_ELF_TypeObject ) ; OutStreamer -> emitELFSize ( GVSym , MCConstantExpr :: create ( Size , OutContext ) ) ; } OutStreamer -> EmitLabel ( GVSym ) ; EmitGlobalConstant ( DL ,


<s> if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addMemOperand ( MMO ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addMemOperand ( MMO ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addMemOperand ( MMO ) ; } else { llvm_unreachable ( <STR_LIT> )


<s> if ( isLegalAVL ( AVL ) ) return AVL ; return getNode ( <STR_LIT> , AVL . getValueType


<s> IRBuilder < > Builder ( I -> getContext ( ) ) ; Builder . SetInsertPoint ( I ) ; Builder . SetCurrentDebugLocation ( I -> getDebugLoc ( ) ) ; Value * Store = tryCreateMaskedScatterOffset ( I , Ptr , Builder ) ; if ( ! Store ) Store = tryCreateMaskedScatterBase ( I , Ptr , Builder ) ; if ( ! Store ) return nullptr ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; I -> replaceAllUsesWith (


<s> return DecodeMem ( Inst , insn , Address , Decoder


<s> void <ISA_LIT>InstPrinter :: printCoprocOptionImm ( const MCInst * MI , unsigned OpNum , const MCSubtargetInfo & STI , raw_ostream & O ) { O << <STR_LIT> << MI -> getOperand ( OpNum


<s> const GlobalValue * GV = cast < GlobalAddressSDNode > ( Op ) -> getGlobal ( ) ; int64_t Offset = cast < GlobalAddressSDNode > ( Op ) -> getOffset ( ) ; SDValue Result = DAG . getTargetGlobalAddress ( GV , Op . getDebugLoc ( ) , getPointerTy ( ) , Offset ) ; return DAG . getNode ( <STR_LIT> , Op . getDebugLoc ( )


<s> static reg_class_t sparc_preferred_reload_class ( rtx x , reg_class_t rclass ) { machine_mode mode = GET_MODE ( x ) ; if ( CONSTANT_P ( x ) ) { if ( FP_REG_CLASS_P ( rclass ) || rclass == GENERAL_OR_FP_REGS || rclass == GENERAL_OR_EXTRA_FP_REGS || ( GET_MODE_CLASS ( mode ) == MODE_FLOAT && ! TARGET_FPU ) || ( mode == TFmode && ! const_zero_operand ( x


<s> ParallelMAC ( Instruction * I , ValueList & V , bool RdOnly ) : Mul ( I ) , VL


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> :


<s> return ( __m128h ) __builtin_ia32_vfmaddsh3_maskz ( ( __v8hf ) __W , ( __v8hf )


<s> rtx insn , dwarf ; amount = offsets -> outgoing_args - offsets -> locals_base ; if ( amount < <NUM_LIT> ) insn = emit_insn ( gen_addsi3 ( hard_frame_pointer_rtx , stack_pointer_rtx , GEN_INT ( amount ) ) ) ; else { emit_insn ( gen_movsi ( hard_frame_pointer_rtx , GEN_INT ( amount ) ) ) ; if ( TARGET_THUMB2 ) { insn = emit_insn ( gen_addsi3 ( hard_frame_pointer_rtx , stack_pointer_rtx , hard_frame_pointer_rtx ) ) ; } else { insn = emit_insn ( gen_addsi3 ( hard_frame_pointer_rtx , hard_frame_pointer_rtx , stack_pointer_rtx ) ) ; } dwarf = gen_rtx_SET ( VOIDmode , hard_frame_pointer_rtx , plus_constant ( Pmode , stack_pointer_rtx , amount ) ) ; RTX_FRAME_RELATED_P ( dwarf ) = <NUM_LIT> ; add_reg_note ( insn , REG_FRAME_RELATED_EXPR ,


<s> ++ i ; } if ( ! MBB . empty ( ) ) MIRBuilder . setInstr ( * MBB . begin ( ) ) ; const <ISA_LIT>TargetLowering & TLI = * getTLI < <ISA_LIT>TargetLowering > ( ) ; CCAssignFn * AssignFn = TLI . CCAssignFnForCall ( F . getCallingConv ( ) , false ) ; FormalArgHandler Handler ( MIRBuilder , MRI , AssignFn ) ; if ( ! handleAssignments ( MIRBuilder , SplitArgs , Handler ) ) return false ; if ( F . isVarArg ( ) ) { if ( ! MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . isTargetDarwin ( ) ) { return false ; } uint64_t StackOffset = alignTo ( Handler . StackUsed , <NUM_LIT> ) ; auto & MFI = MIRBuilder . getMF ( ) . getFrameInfo ( ) ; <ISA_LIT>FunctionInfo * FuncInfo = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; FuncInfo -> setVarArgsStackIndex ( MFI . CreateFixedObject ( <NUM_LIT> ,


<s> bool isMM16AsmRegMoveP ( ) const { if ( ! ( isRegIdx ( ) && RegIdx


<s> if ( VT . isVector ( ) ) return <STR_LIT> ( <STR_LIT> , VT


<s> FunctionPass * llvm :: create<ISA_LIT>VectorCombineLegacyPass


<s> unsigned Rt2 = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned Rn = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned pred = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; if ( pred == <NUM_LIT> ) return DecodeCPSInstruction ( Inst , Insn , Address , Decoder ) ; DecodeStatus S = MCDisassembler :: Success ; if ( Rt == Rn || Rn == Rt2 ) S =


<s> const int16_t Sub0_3 [ ] = { AMDGPU :: sub0 , AMDGPU :: sub1 , AMDGPU :: sub2 , AMDGPU :: sub3 , <NUM_LIT> } ; const int16_t Sub0_1 [ ] = { AMDGPU :: sub0 , AMDGPU :: sub1 , <NUM_LIT> } ; unsigned Opcode ; const int16_t * SubIndices ; if ( AMDGPU :: SReg_32RegClass . contains ( DestReg ) ) { assert ( AMDGPU :: SReg_32RegClass . contains ( SrcReg ) ) ; BuildMI ( MBB , MI , DL , get ( AMDGPU :: S_MOV_B32 ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; return ; } else if ( AMDGPU :: SReg_64RegClass . contains ( DestReg ) ) { assert ( AMDGPU :: SReg_64RegClass . contains ( SrcReg ) ) ; BuildMI ( MBB , MI , DL , get ( AMDGPU :: S_MOV_B64 ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; return ; } else if ( AMDGPU :: SReg_128RegClass . contains ( DestReg ) ) { assert ( AMDGPU :: SReg_128RegClass . contains ( SrcReg ) ) ; Opcode = AMDGPU :: S_MOV_B32 ; SubIndices = Sub0_3 ; } else if ( AMDGPU :: SReg_256RegClass . contains ( DestReg ) ) { assert ( AMDGPU :: SReg_256RegClass . contains ( SrcReg ) ) ; Opcode = AMDGPU :: S_MOV_B32 ; SubIndices = Sub0_7 ; } else if ( AMDGPU :: SReg_512RegClass . contains ( DestReg ) ) { assert ( AMDGPU :: SReg_512RegClass . contains ( SrcReg ) ) ; Opcode = AMDGPU :: S_MOV_B32 ; SubIndices = Sub0_15 ; } else if ( AMDGPU :: VReg_32RegClass . contains ( DestReg ) ) { assert ( AMDGPU :: VReg_32RegClass . contains ( SrcReg ) || AMDGPU :: SReg_32RegClass . contains


<s> SDValue Low = Value ; SDValue High = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Value , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; SDValue StoreLow = DAG . getTruncStore ( Chain , dl , Low , BasePtr , ST -> getPointerInfo ( ) , <STR_LIT> , ST -> isVolatile ( ) , ST -> isNonTemporal ( ) , <NUM_LIT> ) ; SDValue HighAddr = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , BasePtr , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; SDValue StoreHigh = DAG . getTruncStore ( Chain , dl , High , HighAddr , ST -> getPointerInfo ( ) . getWithOffset ( <NUM_LIT> ) , <STR_LIT> , ST -> isVolatile ( ) , ST -> isNonTemporal ( ) , <NUM_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , StoreLow , StoreHigh ) ; } Type * IntPtrTy = getDataLayout ( ) -> getIntPtrType ( * DAG . getContext ( ) ) ; TargetLowering :: ArgListTy Args ; TargetLowering :: ArgListEntry Entry ; Entry . Ty = IntPtrTy ; Entry . Node = BasePtr ; Args . push_back ( Entry ) ; Entry . Node = Value ; Args . push_back ( Entry ) ; TargetLowering :: CallLoweringInfo CLI ( DAG ) ; CLI . setDebugLoc ( dl ) . setChain ( Chain ) . setCallee ( CallingConv :: C , Type :: getVoidTy ( * DAG . getContext ( ) ) , DAG . getExternalSymbol ( <STR_LIT> , getPointerTy ( ) ) , std :: move ( Args ) , <NUM_LIT> ) ; std :: pair < SDValue , SDValue > CallResult = LowerCallTo ( CLI ) ; return CallResult .


<s> LLVM_EXTERNAL_VISIBILITY void LLVMInitialize<ISA_LIT>TargetInfo ( ) { RegisterTarget < Triple :: patmos > X ( getThe<ISA_LIT>Target (

) , <STR_LIT> , <STR_LIT> , <STR_LIT> ) ;


<s> rtx mcore_function_arg ( CUMULATIVE_ARGS cum , enum machine_mode mode , tree type , int named ) { int arg_reg ; if ( ! named || mode ==


<s> if ( MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) && MFI -> adjustsStack ( ) ) return true ; return MFI -> hasVarSizedObjects ( ) || MFI


<s> if ( ! ( recog_memoized ( use_insn ) == CODE_FOR_lo_sum || nds32_symbol_load_store_p ( use_insn ) || ( nds32_reg_base_load_store_p ( use_insn ) && ! nds32_sp_base_or_plus_load_store_p ( use_insn ) ) ) ) return ; } group_id = GEN_INT ( relax_group_id ) ; emit_insn_before ( gen_relax_group ( group_id ) , sethi ) ; for ( link = DF_REF_CHAIN ( def_record ) ; link ; link = link -> next ) { if ( ! DF_REF_INSN_INFO ( link -> ref ) ) continue ; use_insn = DF_REF_INSN ( link -> ref ) ; if ( active_insn_p ( use_insn ) ) emit_insn_before ( gen_relax_group


<s> default : MI -> dump ( ) ; llvm_unreachable ( <STR_LIT> ) ; case MachineOperand :: MO_Register : if ( MO . isImplicit ( ) ) continue ; MCOp = MCOperand :: CreateReg ( MO . getReg ( ) ) ; break ; case MachineOperand :: MO_Immediate : MCOp = MCOperand :: CreateImm ( MO . getImm ( ) ) ; break ; case MachineOperand ::


<s> return static_cast < const <ISA_LIT>Subtarget & > ( STI ) .


<s> bool isVecListDPairSpaced ( ) const { if ( isSingleSpacedVectorList ( ) ) return false ; return ( <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains


<s> if ( ! isALUInstr ( MI -> getOpcode ( ) ) ) { return false ; } for ( MachineInstr :: const_mop_iterator I = MI -> operands_begin ( ) , E = MI -> operands_end ( ) ; I != E ; ++ I ) { if ( ! I -> isReg ( ) || ! I -> isUse ( ) || TargetRegisterInfo

:: isVirtualRegister ( I -> getReg ( ) ) ) continue ;


<s> if ( IsZExt ) { unsigned ResultReg = emitAnd_ri ( <STR_LIT> , SrcReg , false , <NUM_LIT> ) ; assert ( ResultReg && <STR_LIT> ) ; if ( DestVT == <STR_LIT> ) { unsigned Reg64 = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , Reg64 ) . addImm ( <NUM_LIT> ) . addReg ( ResultReg ) . addImm ( <STR_LIT> ) ; ResultReg = Reg64 ; } return ResultReg ; } else { if ( DestVT == <STR_LIT> ) { return <NUM_LIT> ; } return fastEmitInst_rii ( <STR_LIT> , & <STR_LIT> , SrcReg , false ,


<s> EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( <STR_LIT> ( N ) && VT . isVector ( ) && DCI . DAG . getTargetLoweringInfo ( ) . isTypeLegal ( VT ) ) return CombineBaseUpdate ( N , DCI ) ; return SDValue


<s> assert ( TLI -> InstructionOpcodeToISD ( Opcode ) && <STR_LIT> ) ; return TargetTransformInfo :: getArithmeticInstrCost ( Opcode , Ty


<s> return ( MI . mayStore ( ) && ( MI . getOperand ( <NUM_LIT> ) ) . isReg ( ) && ( ( MI . getOperand ( <NUM_LIT> ) ) . getReg


<s> format ( <STR_LIT> , FixupOffset ) . print ( Buffer , sizeof ( Buffer ) ) ; Asm . getContext ( ) . FatalError ( Fixup . getLoc ( ) , Twine ( <STR_LIT> <STR_LIT> ) + Buffer + <STR_LIT> <STR_LIT> ) ; llvm_unreachable ( <STR_LIT> ) ; } macho :: RelocationEntry MRE ; MRE . Word0 = ( ( <NUM_LIT> << <NUM_LIT> ) | ( macho :: RIT_Pair << <NUM_LIT> ) | ( Log2Size << <NUM_LIT> ) | ( IsPCRel << <NUM_LIT> ) | macho :: RF_Scattered ) ; MRE . Word1 = Value2 ; Writer -> addRelocation ( Fragment -> getParent ( ) , MRE ) ; } else { if ( FixupOffset > <NUM_LIT> ) return false ; } macho :: RelocationEntry MRE ; MRE . Word0 = ( ( FixupOffset << <NUM_LIT> ) | ( Type << <NUM_LIT> ) | ( Log2Size << <NUM_LIT> ) | ( IsPCRel << <NUM_LIT> ) | macho :: RF_Scattered ) ; MRE . Word1 = Value ; Writer -> addRelocation ( Fragment -> getParent (


<s> __asm__ ( <STR_LIT> : <STR_LIT> ( d ) : <STR_LIT> ( a ) ) ; return ( int


<s> static bool getTargetShuffleMaskIndices ( SDValue MaskNode , unsigned MaskEltSizeInBits , SmallVectorImpl < uint64_t > & RawMask ) { APInt UndefElts ; SmallVector < APInt , <NUM_LIT> > EltBits ; if ( ! getTargetConstantBitsFromNode ( MaskNode , MaskEltSizeInBits , UndefElts , EltBits


<s> insn = emit_insn_after ( gen_setlb ( ) , label ) ; label = gen_label_rtx ( ) ; emit_label_after ( label , insn ) ; DUMP ( <STR_LIT> , label ) ; } else { DUMP ( <STR_LIT> , label ) ; emit_insn_before ( gen_setlb ( ) , label ) ; } comparison = XEXP ( SET_SRC ( PATTERN ( branch ) ) , <NUM_LIT> ) ; cmp_reg = XEXP ( comparison , <NUM_LIT> ) ; gcc_assert ( REG_P ( cmp_reg ) ) ; gcc_assert ( REGNO ( cmp_reg ) == CC_REG ) ; if ( GET_MODE ( cmp_reg ) == CC_FLOATmode ) lcc = gen_FLcc ( comparison , label ) ; else lcc = gen_Lcc ( comparison , label ) ; rtx_insn * jump = emit_jump_insn_before


<s> Register <ISA_LIT>RegisterInfo :: getFrameRegister ( const MachineFunction & MF


<s> StringRef getType ( ) { return CurType .


<s> switch ( getRegSizeInBits ( * VRC ) ) { case <NUM_LIT> : return & <STR_LIT> ; case <NUM_LIT> : return & <STR_LIT> ; case <NUM_LIT> : return & <STR_LIT> ; case <NUM_LIT> : return & <STR_LIT> ; case <NUM_LIT> : return & <STR_LIT> ; case <NUM_LIT> : return & <STR_LIT> ; case <NUM_LIT> : return & <STR_LIT>


<s> Inst . addOperand ( MCOperand :: createImm ( SysReg .


<s> SDValue Mask = DAG . getNode ( <STR_LIT> , DL , VT , MaskConstant , Shift ) ; SDValue Src [ <NUM_LIT> ] = { ShiftedValue , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) , Mask } ; SDValue Input = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Src ) ; SDValue Args [ <NUM_LIT> ] = { Chain , Input , DWordAddr } ; return DAG . getMemIntrinsicNode ( <STR_LIT> , DL , Op -> getVTList ( ) , Args , MemVT , StoreNode -> getMemOperand ( ) ) ; } else if ( Ptr -> getOpcode ( ) != <STR_LIT> && Value . getValueType ( ) . bitsGE ( <STR_LIT> ) ) { Ptr = DAG . getNode ( <STR_LIT> , DL , Ptr . getValueType ( ) , DAG . getNode ( <STR_LIT> , DL , Ptr . getValueType ( ) , Ptr , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ) ; if ( StoreNode -> isTruncatingStore ( ) || StoreNode -> isIndexed ( ) ) { llvm_unreachable ( <STR_LIT> ) ; } else { Chain = DAG . getStore ( Chain , DL , Value , Ptr , StoreNode -> getMemOperand ( ) ) ; } return Chain ; } } EVT ValueVT = Value . getValueType ( ) ; if ( StoreNode -> getAddressSpace ( ) != <STR_LIT> ) { return SDValue ( ) ; } SDValue Ret = AMDGPUTargetLowering :: LowerSTORE ( Op , DAG ) ; if ( Ret . getNode ( ) ) { return Ret ; } const MachineFunction & MF = DAG . getMachineFunction ( ) ; const AMDGPUFrameLowering * TFL = static_cast < const AMDGPUFrameLowering * > ( Subtarget -> getFrameLowering ( ) ) ; unsigned StackWidth = TFL -> getStackWidth (


<s> while ( MBB -> succ_size ( ) ) MBB -> removeSuccessor ( * MBB -> succ_begin (


<s> else if ( const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( Expr ) ) Inst . addOperand ( MCOperand :: CreateImm (


<s> assert ( ( SegReg || BaseReg || IndexReg ) && <STR_LIT> ) ; assert ( ( ( Scale == <NUM_LIT> || Scale == <NUM_LIT> || Scale == <NUM_LIT> || Scale == <NUM_LIT> ) ) && <STR_LIT> ) ; auto Res = llvm :: make_unique < <ISA_LIT>Operand > ( Memory , StartLoc , EndLoc ) ; Res -> Mem . SegReg = SegReg ; Res -> Mem . Disp = Disp ; Res -> Mem . BaseReg = BaseReg ; Res -> Mem . IndexReg = IndexReg ; Res -> Mem . Scale = Scale ; Res -> Mem . Size = Size ; Res -> Mem . ModeSize = ModeSize ; Res -> SymName = SymName ; Res -> OpDecl = OpDecl ; Res -> AddressOf = false


<s> MCInstrInfo * X = new MCInstrInfo ( ) ; Init<ISA_LIT>MCInstrInfo ( X


<s> Op -> SysReg . Data = Str . data ( ) ; Op -> SysReg . Length = Str . size ( ) ; Op -> SysReg . FeatureBits =


<s> CanUseDblLoad = ( SuperRegNext == SuperReg ) ; } if ( CanUseDblLoad ) { TII . loadRegFromStackSlot ( MBB , MI , SuperReg , CSI [ i + <NUM_LIT> ] . getFrameIdx ( ) , SuperRegClass , TRI ) ; MBB . addLiveIn ( SuperReg ) ; ++ i ; } else { ContiguousRegs = false ; const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ; TII . loadRegFromStackSlot ( MBB , MI , Reg , CSI [ i ] . getFrameIdx ( ) , RC , TRI ) ; MBB . addLiveIn ( Reg ) ; } } return true


<s> if ( ! isa < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) . getNode ( ) ) ) return false ; uint64_t Index = N -> getConstantOperandVal ( <NUM_LIT> ) ; MVT VT = N -> getSimpleValueType ( <NUM_LIT> ) ; unsigned ElSize = VT . getScalarSizeInBits ( ) ; return ( Index * ElSize ) % vecWidth


<s> int mcore_num_arg_regs ( machine_mode mode , const_tree type ) { int size ; function_arg_info arg ( const_cast < tree > ( type ) , mode , true ) ; if ( targetm . calls . must_pass_in_stack ( arg ) ) return <NUM_LIT> ; if ( type && mode == BLKmode ) size = int_size_in_bytes ( type ) ; else size = GET_MODE_SIZE ( mode ) ; return ROUND_ADVANCE ( size


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT>


<s> BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( <STR_LIT> ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( <STR_LIT> ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . addImm


<s> Function * Fn = CGN -> getFunction ( ) ; if ( ! Fn || ! Fn -> hasSection ( ) ) return Depth ; if ( Fn -> getSection ( ) . find ( <STR_LIT> ) == string :: npos ) return Depth ; Depth = Depth + InterruptDepth ; return


<s> Type * I16Ty = Type :: getInt16Ty ( Ctx ) ; Value * PaletteOffset = ConstantInt :: get ( Type :: getInt64Ty ( Ctx ) , <NUM_LIT> ) ; Value * PaletteValue = ConstantInt :: get ( Type :: getInt8Ty ( Ctx ) , <NUM_LIT> ) ; Value * PalettePos = GetElementPtrInst :: Create ( I8Ty , I8Ptr , PaletteOffset , <STR_LIT> , Pos ) ; new StoreInst ( PaletteValue , PalettePos , Pos ) ; for ( int I = <NUM_LIT> , E = Shapes . size ( ) / <NUM_LIT> ; I < E ; I ++ ) { Value * RowOffset = ConstantInt :: get ( Type :: getInt64Ty ( Ctx ) , <NUM_LIT> + I ) ; Value * ColOffset = ConstantInt :: get ( Type :: getInt64Ty ( Ctx ) , <NUM_LIT> + I * <NUM_LIT> ) ; const std :: string ShapeName = <STR_LIT> + itostr


<s> DebugLoc dl = Op . getDebugLoc ( ) ; bool SeenZero = false ; if ( canChangeToInt ( LHS , SeenZero , Subtarget ) && canChangeToInt ( RHS , SeenZero , Subtarget ) && ( SeenZero || ( DAG . isKnownNeverNaN ( LHS ) && DAG . isKnownNeverNaN ( RHS ) ) ) ) { if ( CC == <STR_LIT> ) CC = <STR_LIT> ; else if ( CC == <STR_LIT> ) CC = <STR_LIT> ; SDValue <ISA_LIT>cc ; if ( LHS . getValueType ( ) == <STR_LIT> ) { LHS = bitcastf32Toi32 ( LHS , DAG ) ; RHS = bitcastf32Toi32 ( RHS , DAG ) ; SDValue Cmp = get<ISA_LIT>Cmp ( LHS , RHS , CC , <ISA_LIT>cc , DAG , dl ) ; SDValue CCR = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Chain , Dest , <ISA_LIT>cc , CCR , Cmp ) ; } SDValue LHS1 , LHS2 ; SDValue RHS1 , RHS2 ; expandf64Toi32 ( LHS , DAG , LHS1 , LHS2 ) ; expandf64Toi32 ( RHS , DAG , RHS1 , RHS2 ) ; <STR_LIT> CondCode = IntCCTo<ISA_LIT>CC ( CC ) ; <ISA_LIT>cc = DAG . getConstant ( CondCode , <STR_LIT> ) ; SDVTList VTList = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SDValue Ops [ ] = { Chain , <ISA_LIT>cc , LHS1 , LHS2 , RHS1 , RHS2 , Dest } ; return DAG . getNode ( <STR_LIT> , dl , VTList , Ops , <NUM_LIT> ) ; } return SDValue (


<s> Cst = - ( intptr_t ) MovePCtoLROffset - <NUM_LIT> ; } if ( MO . isGlobal ( ) ) return MachineRelocation :: getGV ( MCE . getCurrentPCOffset ( ) , RelocID , const_cast < GlobalValue * > ( MO . getGlobal ( ) ) , Cst , isa < Function > ( MO . getGlobal ( ) ) ) ; if ( MO . isSymbol ( ) ) return MachineRelocation :: getExtSym ( MCE . getCurrentPCOffset ( )

, RelocID , MO . getSymbolName ( ) , Cst ) ;


<s> } if ( ! args ) { cur_tree = ( ( pop_target ) ? pop_target : target_option_default_node ) ; cl_target_option_restore ( & global_options , & global_options_set , TREE_TARGET_OPTION ( cur_tree ) ) ; } else { rs6000_cpu_index = rs6000_tune_index = - <NUM_LIT> ; if ( ! rs6000_inner_target_options ( args , false ) || ! rs6000_option_override_internal ( false ) || ( cur_tree = build_target_option_node ( & global_options , & global_options_set ) ) == NULL_TREE ) { if ( TARGET_DEBUG_BUILTIN || TARGET_DEBUG_TARGET ) fprintf ( stderr , <STR_LIT> ) ; return false ; } } target_option_current_node = cur_tree ; rs6000_activate_target_options ( target_option_current_node ) ; if ( rs6000_target_modify_macros_ptr ) { prev_opt = TREE_TARGET_OPTION ( prev_tree ) ; prev_flags = prev_opt -> x_rs6000_isa_flags ; cur_opt = TREE_TARGET_OPTION ( cur_tree ) ; cur_flags = cur_opt -> x_rs6000_isa_flags ; diff_flags = ( prev_flags ^ cur_flags


<s> bool IsStrict = N -> isStrictFPOpcode ( ) || N -> isTargetStrictFPOpcode ( ) ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; if ( ! TLI . isTypeLegal ( VT ) ) return SDValue ( ) ; SDValue A = N -> getOperand ( IsStrict ? <NUM_LIT> : <NUM_LIT> ) ; SDValue B = N -> getOperand ( IsStrict ? <NUM_LIT> : <NUM_LIT> ) ; SDValue C = N -> getOperand ( IsStrict ? <NUM_LIT> : <NUM_LIT> ) ; SDNodeFlags Flags = N -> getFlags ( ) ; if ( ! IsStrict && Flags . hasAllowReassociation ( ) && TLI . isOperationExpand ( <STR_LIT> , VT ) ) { SDValue Fmul = DAG . getNode ( <STR_LIT> , dl , VT , A , B , Flags ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Fmul , C , Flags ) ; } EVT ScalarVT = VT . getScalarType ( ) ; if ( ( ScalarVT != <STR_LIT> && ScalarVT != <STR_LIT> ) || ! Subtarget . hasAnyFMA ( ) ) return SDValue ( ) ; auto invertIfNegative = [ & DAG , & TLI , & DCI ] ( SDValue & V ) { bool CodeSize = DAG . getMachineFunction ( ) . getFunction ( ) . hasOptSize ( ) ; bool LegalOperations = ! DCI . isBeforeLegalizeOps ( ) ; if ( SDValue NegV = TLI . getCheaperNegatedExpression ( V , DAG , LegalOperations , CodeSize ) ) { V = NegV ; return true ; } if ( V . getOpcode ( ) == <STR_LIT> && isNullConstant ( V . getOperand ( <NUM_LIT> ) ) ) { SDValue Vec = V . getOperand ( <NUM_LIT> ) ; if ( SDValue NegV = TLI . getCheaperNegatedExpression ( Vec , DAG , LegalOperations , CodeSize ) ) { V = DAG . getNode ( <STR_LIT> , SDLoc ( V ) , V . getValueType ( ) , NegV , V . getOperand ( <NUM_LIT> ) ) ; return true ; } } return false ; } ; bool NegA = invertIfNegative ( A ) ; bool NegB = invertIfNegative ( B ) ; bool NegC = invertIfNegative ( C ) ; if ( ! NegA && ! NegB && ! NegC ) return SDValue ( ) ; unsigned NewOpcode = negateFMAOpcode ( N -> getOpcode ( ) , NegA != NegB , NegC , false ) ; if ( IsStrict ) { assert ( N -> getNumOperands ( ) == <NUM_LIT> && <STR_LIT> ) ; return DAG . getNode ( NewOpcode , dl , { VT , <STR_LIT> } , { N -> getOperand ( <NUM_LIT> ) , A , B , C } ) ; } else { if ( N -> getNumOperands ( ) == <NUM_LIT> ) return DAG . getNode ( NewOpcode , dl , VT , A ,

B , C , N -> getOperand ( <NUM_LIT> ) ) ;


<s> auto * CCMask = dyn_cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ; if ( ! CCValid || ! CCMask ) return SDValue ( ) ; int CCValidVal = CCValid -> getZExtValue ( ) ; int CCMaskVal = CCMask -> getZExtValue ( ) ; SDValue Select = N -> getOperand ( <NUM_LIT> ) ; if ( Select -> getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; auto * SelectCCValid = dyn_cast < ConstantSDNode > ( Select -> getOperand ( <NUM_LIT> ) ) ; auto * SelectCCMask = dyn_cast < ConstantSDNode > ( Select -> getOperand ( <NUM_LIT> ) ) ; if ( ! SelectCCValid || ! SelectCCMask ) return SDValue ( ) ; int SelectCCValidVal = SelectCCValid -> getZExtValue ( ) ; int SelectCCMaskVal = SelectCCMask -> getZExtValue ( ) ; auto * TrueVal = dyn_cast < ConstantSDNode > ( Select -> getOperand ( <NUM_LIT> ) ) ; auto * FalseVal = dyn_cast < ConstantSDNode > ( Select -> getOperand ( <NUM_LIT> ) ) ; if ( ! TrueVal || ! FalseVal ) return SDValue ( ) ; if ( TrueVal -> getZExtValue ( ) != <NUM_LIT> && FalseVal -> getZExtValue ( ) == <NUM_LIT> ) ; else if ( TrueVal -> getZExtValue ( ) == <NUM_LIT> && FalseVal -> getZExtValue ( ) != <NUM_LIT> ) SelectCCMaskVal ^= SelectCCValidVal ; else return SDValue (


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( ! getLdStOffsetOp ( MI )


<s> if ( samplerInstr -> getOperand ( <NUM_LIT> ) . isCImm ( ) ) { auto sampMask = getIConstVal ( OrigArgs [ <NUM_LIT> ] , MRI ) ; Register res ; sampler = buildSamplerLiteral ( sampMask , res , GR -> get<ISA_LIT>TypeForVReg ( sampler ) , MIRBuilder , GR ) ; } } Register reg ; Register sampledImage = buildOpSampledImage ( reg , image , sampler , MIRBuilder , GR ) ; Register coord = OrigArgs [ <NUM_LIT> ] ; Register lod = GR -> buildConstantFP ( APFloat :: getZero ( APFloat :: IEEEsingle ( ) ) , MIRBuilder ) ; <ISA_LIT>Type * tmpType = retType ; bool NeedExtract = false ; if ( tmpType -> getOpcode ( ) != <STR_LIT>


<s> uint64_t dest = symbol -> fragRef ( ) -> frag ( ) -> getParent ( ) -> getSection ( ) . addr ( ) + symbol -> fragRef ( ) -> getOutputOffset ( ) ; uint64_t src = pIsland . getParent ( ) -> getSection ( ) . addr ( ) + pIsland . offset ( ) + pIsland . size ( ) ; if ( isValidForADRP ( src , dest ) ) { m_pData = ADRP_TEMPLATE ; m_Name = <STR_LIT> ; m_Size = sizeof ( ADRP_TEMPLATE ) ; getFixupList ( ) . clear ( ) ; addFixup ( <NUM_LIT> , <NUM_LIT> , llvm :: ELF :: R_AARCH64_ADR_PREL_PG_HI21 ) ; addFixup ( <NUM_LIT> , <NUM_LIT> , llvm


<s> EVT VTs [ ] = { Op . getOperand ( <NUM_LIT> ) . getValueType ( ) , <STR_LIT> } ; SDValue CompNode = DAG . getNode ( <STR_LIT> , dl , VTs , Ops ) ; SDValue Flags = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getRegister ( <STR_LIT> , <STR_LIT> ) , CompNode . getValue ( <NUM_LIT> ) ) ; unsigned BitNo ; bool InvertBit ; switch ( cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ) { default : case <NUM_LIT> : BitNo = <NUM_LIT> ; InvertBit = false ; break ; case <NUM_LIT> : BitNo = <NUM_LIT> ; InvertBit = true ; break ; case <NUM_LIT> : BitNo = <NUM_LIT> ; InvertBit = false ; break ; case <NUM_LIT>


<s> void <ISA_LIT>AsmPrinter :: printOperand ( const MachineInstr * MI , int OpNum , raw_ostream & O ) { const MachineOperand & MO = MI -> getOperand ( OpNum ) ; switch ( MO . getType ( ) ) { case MachineOperand :: MO_Register : O << <ISA_LIT>InstPrinter :: getRegisterName ( MO . getReg ( ) ) ; break ; case MachineOperand :: MO_Immediate : O << MO . getImm ( ) ; break ; case MachineOperand :: MO_MachineBasicBlock : O << * MO . getMBB ( ) -> getSymbol ( ) ; break ; case MachineOperand :: MO_GlobalAddress : O << * getSymbol ( MO . getGlobal ( ) ) ; break ; case MachineOperand :: MO_BlockAddress : { MCSymbol * BA = GetBlockAddressSymbol ( MO . getBlockAddress ( ) ) ; O << BA -> getName ( ) ; break ; } case MachineOperand :: MO_ExternalSymbol : O << * GetExternalSymbolSymbol ( MO . getSymbolName ( ) ) ; break ; case MachineOperand ::


<s> SDValue <ISA_LIT>TargetLowering :: LowerOperation ( SDValue Op , SelectionDAG & DAG ) const { switch ( Op . getOpcode ( ) ) { default : return <ISA_LIT>TargetLowering :: LowerOperation ( Op , DAG ) ; case <STR_LIT> : return LowerBRCOND ( Op , DAG ) ; case <STR_LIT> : return LowerRETURNADDR ( Op , DAG ) ; case <STR_LIT> : { SDValue Result = LowerLOAD ( Op , DAG ) ; assert ( ( ! Result . getNode ( ) || Result . getNode ( ) -> getNumValues ( ) == <NUM_LIT> ) && <STR_LIT> ) ; return Result ; } case <STR_LIT> : case <STR_LIT> : return LowerTrig ( Op , DAG ) ; case <STR_LIT> : return LowerSELECT ( Op , DAG ) ; case <STR_LIT> : return LowerFDIV ( Op , DAG ) ; case <STR_LIT> : return LowerATOMIC_CMP_SWAP ( Op , DAG ) ; case <STR_LIT> : return LowerSTORE ( Op , DAG ) ; case <STR_LIT> : { MachineFunction & MF = DAG . getMachineFunction ( ) ; <ISA_LIT>MachineFunctionInfo * MFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; return LowerGlobalAddress ( MFI , Op , DAG ) ; } case <STR_LIT> : return LowerINTRIN<ISA_LIT>C_WO_CHAIN ( Op , DAG ) ; case <STR_LIT> : return LowerINTRIN<ISA_LIT>C_W_CHAIN ( Op , DAG ) ; case <STR_LIT> : return LowerINTRIN<ISA_LIT>C_VOID ( Op , DAG ) ; case <STR_LIT> : return lowerADDRSPACECAST ( Op , DAG ) ; case <STR_LIT> : return lowerINSERT_VECTOR_ELT ( Op , DAG ) ; case <STR_LIT> : return lowerEXTRACT_VECTOR_ELT ( Op , DAG ) ; case <STR_LIT> : return lowerBUILD_VECTOR ( Op , DAG ) ; case <STR_LIT> : return lowerFP_ROUND ( Op , DAG ) ; case <STR_LIT> : return lowerTRAP ( Op , DAG ) ; case <STR_LIT> : return lowerDEBUGTRAP ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return splitUnaryVectorOp ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return lowerFMINNUM_FMAXNUM ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case


<s> int M = Mask [ I ] ; if ( M >= <NUM_LIT> && M != I


<s> case <STR_LIT> : CompareOpc = <NUM_LIT> ; isDot = <NUM_LIT> ; break ; case <STR_LIT> : if ( Subtarget . hasP8Altivec ( ) ) { CompareOpc = <NUM_LIT> ; isDot = <NUM_LIT> ; } else return false ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( Subtarget . hasVSX ( ) ) { switch ( IntrinsicID ) { case <STR_LIT> : CompareOpc = <NUM_LIT> ; break ; case <STR_LIT> : CompareOpc = <NUM_LIT> ; break ; case <STR_LIT> : CompareOpc = <NUM_LIT> ; break ; case <STR_LIT> : CompareOpc = <NUM_LIT> ; break ; case <STR_LIT> : CompareOpc = <NUM_LIT> ; break ; case <STR_LIT> : CompareOpc = <NUM_LIT> ; break ; } isDot = <NUM_LIT> ; } else return false ; break ; case <STR_LIT> : CompareOpc = <NUM_LIT> ; isDot = <NUM_LIT> ; break ; case <STR_LIT> : CompareOpc = <NUM_LIT> ; isDot = <NUM_LIT> ; break ; case <STR_LIT> : CompareOpc = <NUM_LIT> ; isDot = <NUM_LIT> ; break ; case <STR_LIT> : CompareOpc = <NUM_LIT> ; isDot = <NUM_LIT> ; break ; case <STR_LIT> : CompareOpc = <NUM_LIT> ; isDot = <NUM_LIT> ; break ; case <STR_LIT> : if ( Subtarget . hasP8Altivec ( ) ) { CompareOpc = <NUM_LIT> ; isDot = <NUM_LIT> ; } else return false ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( Subtarget . hasP9Altivec ( ) ) { switch ( IntrinsicID ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : CompareOpc = <NUM_LIT> ; break ; case <STR_LIT> : CompareOpc = <NUM_LIT> ; break ; case <STR_LIT> : CompareOpc = <NUM_LIT> ; break ; case <STR_LIT> : CompareOpc = <NUM_LIT> ; break ; case <STR_LIT> : CompareOpc = <NUM_LIT> ; break ; case <STR_LIT> : CompareOpc = <NUM_LIT> ; break ; } isDot = <NUM_LIT> ; } else return false ; break ; case <STR_LIT> : CompareOpc = <NUM_LIT> ; isDot = <NUM_LIT> ; break ; case <STR_LIT> : CompareOpc = <NUM_LIT> ; isDot = <NUM_LIT> ; break ; case <STR_LIT> : CompareOpc = <NUM_LIT> ; isDot = <NUM_LIT> ; break ; case <STR_LIT> : CompareOpc = <NUM_LIT> ; isDot = <NUM_LIT> ; break ; case <STR_LIT> : CompareOpc = <NUM_LIT> ; isDot = <NUM_LIT> ; break ; case <STR_LIT> : if ( Subtarget . hasP8Altivec ( ) ) { CompareOpc = <NUM_LIT> ; isDot = <NUM_LIT> ; } else return false ; break ; case <STR_LIT> : CompareOpc = <NUM_LIT> ; isDot = <NUM_LIT> ; break ; case <STR_LIT> : CompareOpc = <NUM_LIT> ; isDot


<s> int64_t Val = MCE -> getValue ( ) ; return ( Val >= <NUM_LIT> && Val < <NUM_LIT>


<s> assert ( NumTZ <= <NUM_LIT> && <STR_LIT> ) ; for ( unsigned Pos = <NUM_LIT> , e = NumTZ ; Pos > e ; -- Pos ) { bool T = ( ( Mask >> Pos ) & <NUM_LIT> ) == CondBit0 ; if ( T ) O <<


<s> void function_expander :: rotate_inputs_left ( unsigned int start , unsigned int end ) { rtx new_last = args [ start ] ; for ( unsigned int i = start ; i < end - <NUM_LIT> ; ++ i ) args [


<s> auto & HRI = * MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getRegisterInfo ( ) ; int Offset = MFI . getObjectOffset ( FI ) ; bool HasAlloca = MFI . hasVarSizedObjects ( ) ; bool HasExtraAlign = HRI . needsStackRealignment ( MF ) ; bool NoOpt = MF . getTarget ( ) . getOptLevel ( ) == CodeGenOpt :: None ; unsigned SP = HRI . getStackRegister ( ) , FP = HRI . getFrameRegister ( ) ; auto & HMFI = * MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; unsigned AP = HMFI . getStackAlignBasePhysReg ( ) ; unsigned FrameSize = MFI . getStackSize ( ) ; bool UseFP = false , UseAP = false ; if ( NoOpt && ! HasExtraAlign ) UseFP = true ; if ( MFI . isFixedObjectIndex ( FI ) || MFI . isObjectPreAllocated ( FI ) ) { UseFP |= ( HasAlloca || HasExtraAlign ) ; } else { if ( HasAlloca ) { if ( HasExtraAlign ) UseAP = true ; else UseFP = true ; } } bool HasFP = hasFP ( MF ) ; assert ( ( HasFP || ! UseFP ) && <STR_LIT> ) ; if ( Offset > <NUM_LIT> && ! HasFP ) Offset -= <NUM_LIT> ; if ( UseFP ) FrameReg = FP ; else if ( UseAP ) FrameReg = AP ; else FrameReg = SP ; int RealOffset =


<s> bool hasSHA ( ) const { return HasSHA


<s> if ( & vStream == & nulls ( ) ) loggerFn = <NUM_LIT> ; int ret = decodeInstruction ( & internalInstr , regionReader , ( void * ) & region , loggerFn , ( void * ) & vStream , ( void * ) MII , address , fMode ) ; if ( ret ) { size = internalInstr . readerCursor - address ; return Fail


<s> void <ISA_LIT>TargetLowering :: LowerOperationWrapper ( SDNode * N , SmallVectorImpl < SDValue > & Results , SelectionDAG & DAG ) { SDValue Op = SDValue ( N , <NUM_LIT> ) ; SDValue Res ; unsigned i ; switch ( Op . getOpcode ( ) ) { case <STR_LIT> : Res = ExpandLoad ( Op . getNode ( ) , DAG ) ; break ; default


<s> uint64_t Value = CE -> getValue ( ) ; unsigned Imm = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i , Value >>= <NUM_LIT> ) { Imm |= ( Value &


<s> bool privateMemoryResourceIsRangeChecked ( ) const { return getGeneration ( )


<s> void <ISA_LIT>LowerControlFlowPass :: SkipIfDead ( MachineInstr & MI ) { MachineBasicBlock & MBB = * MI . getParent ( ) ; DebugLoc DL = MI . getDebugLoc ( ) ; if ( ! shouldSkip ( & MBB , & MBB . getParent ( ) -> back ( ) ) ) return ; MachineBasicBlock :: iterator Insert = & MI ; ++ Insert ; BuildMI ( MBB , Insert , DL , TII -> get ( AMDGPU :: S_CBRANCH_EXECNZ ) ) . addImm ( <NUM_LIT> ) . addReg ( AMDGPU :: EXEC ) ; BuildMI ( MBB , Insert , DL , TII -> get ( AMDGPU :: EXP ) ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( AMDGPU :: VGPR0 ) . addReg ( AMDGPU :: VGPR0 ) . addReg ( AMDGPU ::


<s> MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const <ISA_LIT>16InstrInfo & TII = * static_cast < const <ISA_LIT>16InstrInfo * > ( MF . getTarget ( ) . getInstrInfo ( ) ) ; MachineBasicBlock :: iterator MBBI = MBB . begin ( ) ; DebugLoc dl = MBBI != MBB . end ( ) ? MBBI -> getDebugLoc ( ) : DebugLoc ( ) ; uint64_t StackSize = MFI -> getStackSize ( ) ; if ( StackSize == <NUM_LIT> && ! MFI -> adjustsStack ( ) ) return ; MachineModuleInfo & MMI = MF . getMMI ( ) ; std :: vector < MachineMove > & Moves = MMI . getFrameMoves ( ) ; MachineLocation DstML , SrcML ; TII . makeFrame ( <STR_LIT> , StackSize , MBB , MBBI ) ; MCSymbol * AdjustSPLabel = MMI . getContext ( ) . CreateTempSymbol ( ) ; BuildMI ( MBB , MBBI , dl , TII . get ( TargetOpcode :: PROLOG_LABEL ) ) . addSym ( AdjustSPLabel ) ; DstML = MachineLocation ( MachineLocation :: VirtualFP ) ; SrcML = MachineLocation ( MachineLocation :: VirtualFP , - StackSize ) ; Moves . push_back ( MachineMove ( AdjustSPLabel , DstML , SrcML ) ) ; MCSymbol * CSLabel = MMI . getContext ( ) . CreateTempSymbol ( ) ; BuildMI ( MBB , MBBI , dl , TII . get ( TargetOpcode :: PROLOG_LABEL ) ) . addSym ( CSLabel ) ; DstML = MachineLocation ( MachineLocation :: VirtualFP , - <NUM_LIT> ) ; SrcML = MachineLocation ( <STR_LIT> ) ; Moves . push_back ( MachineMove ( CSLabel , DstML , SrcML ) ) ; DstML = MachineLocation ( MachineLocation :: VirtualFP , - <NUM_LIT> ) ; SrcML = MachineLocation ( <STR_LIT> ) ; Moves . push_back ( MachineMove ( CSLabel ,


<s> MachineBasicBlock :: iterator <ISA_LIT>FrameLowering :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator


<s> void printInlineJT32 ( const MachineInstr * MI


<s> SDValue Val ; if ( VA . getLocReg ( ) == <STR_LIT> || VA . getLocReg ( ) == <STR_LIT> ) { if ( isScalarFPTypeInSSEReg ( VA . getValVT ( ) ) ) CopyVT = <STR_LIT> ; bool isST0 = VA . getLocReg ( ) == <STR_LIT> ; unsigned Opc = <NUM_LIT> ; if ( CopyVT == <STR_LIT> ) Opc = isST0 ? <STR_LIT> : <STR_LIT> ; if ( CopyVT == <STR_LIT> ) Opc = isST0 ? <STR_LIT> : <STR_LIT> ; if ( CopyVT == <STR_LIT> ) Opc = isST0 ? <STR_LIT> : <STR_LIT> ; SDValue Ops [ ] = { Chain , InFlag } ; Chain = SDValue ( DAG . getMachineNode ( Opc , dl , CopyVT , <STR_LIT> , <STR_LIT> , Ops , <NUM_LIT> ) , <NUM_LIT> ) ; Val = Chain . getValue ( <NUM_LIT> ) ; if ( CopyVT != VA . getValVT ( ) ) Val = DAG . getNode ( <STR_LIT> , dl , VA . getValVT ( ) , Val , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; } else if ( Is64Bit && CopyVT . isVector ( ) && CopyVT . getSizeInBits ( ) == <NUM_LIT> ) { if ( VA . getLocReg ( ) == <STR_LIT> || VA . getLocReg ( ) == <STR_LIT> ) { Chain = DAG . getCopyFromReg ( Chain , dl , VA . getLocReg ( ) , <STR_LIT> , InFlag ) . getValue ( <NUM_LIT> ) ; Val = Chain . getValue ( <NUM_LIT> ) ; Val = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Val , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; } else { Chain = DAG . getCopyFromReg ( Chain , dl , VA . getLocReg ( ) , <STR_LIT> , InFlag ) . getValue ( <NUM_LIT> ) ; Val = Chain . getValue ( <NUM_LIT> ) ; } Val = DAG . getNode ( <STR_LIT> , dl , CopyVT , Val ) ; } else { Chain = DAG . getCopyFromReg ( Chain , dl , VA . getLocReg ( ) ,

CopyVT , InFlag ) . getValue ( <NUM_LIT> ) ;


<s> } if ( isSMRD ( Opc0 ) && isSMRD ( Opc1 ) ) { assert ( getNumOperandsNoGlue ( Load0 ) == getNumOperandsNoGlue ( Load1 ) ) ; if ( Load0 -> getOperand ( <NUM_LIT> ) != Load1 -> getOperand ( <NUM_LIT> ) ) return false ; if ( findChainOperand ( Load0 ) != findChainOperand ( Load1 ) ) return false ; Offset0 = cast < ConstantSDNode > ( Load0 -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; Offset1 = cast < ConstantSDNode > ( Load1 -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; return true ; } if ( ( isMUBUF ( Opc0 ) || isMTBUF ( Opc0 ) ) && ( isMUBUF ( Opc1 ) || isMTBUF ( Opc1 ) ) ) { if ( ! nodesHaveSameOperandValue ( Load0 , Load1 , AMDGPU :: OpName :: soffset ) || findChainOperand ( Load0 ) != findChainOperand ( Load1 ) || ! nodesHaveSameOperandValue ( Load0 , Load1 , AMDGPU :: OpName :: vaddr ) || ! nodesHaveSameOperandValue ( Load0 , Load1 , AMDGPU :: OpName :: srsrc ) ) return false ; int OffIdx0 = AMDGPU :: getNamedOperandIdx ( Opc0 , AMDGPU :: OpName :: offset ) ; int OffIdx1 = AMDGPU :: getNamedOperandIdx ( Opc1 , AMDGPU :: OpName :: offset ) ; if ( OffIdx0 == - <NUM_LIT> || OffIdx1 == - <NUM_LIT> ) return false ; -- OffIdx0 ; -- OffIdx1 ; SDValue Off0 = Load0 -> getOperand ( OffIdx0 ) ; SDValue Off1 = Load1 -> getOperand ( OffIdx1 ) ; if ( ! isa < ConstantSDNode > ( Off0 ) || ! isa < ConstantSDNode > ( Off1 ) ) return false ; Offset0 = cast < ConstantSDNode > ( Off0 ) -> getZExtValue ( ) ; Offset1 = cast < ConstantSDNode > ( Off1 ) -> getZExtValue ( ) ; return true ; } return


<s> BuildMI ( TrapBB , DL , TII -> get ( <STR_LIT> ) ) . addImm ( <NUM_LIT> ) ; MBB -> addSuccessor ( TrapBB ) ; BuildMI ( * MBB , MI , DL , TII -> get ( <STR_LIT> ) ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addMBB ( TrapBB ) ; MI -> eraseFromParent ( ) ; return ContBB


<s> DebugLoc DL ; using RegAndKill = std :: pair < unsigned , bool > ; SmallVector < RegAndKill , <NUM_LIT> > Regs ; unsigned i = CSI . size ( ) ; while ( i != <NUM_LIT> ) { unsigned LastReg = <NUM_LIT> ; for ( ; i != <NUM_LIT> ; -- i ) { Register Reg = CSI [ i - <NUM_LIT> ] . getReg ( ) ; if ( ! ( Func ) ( Reg , STI . splitFramePushPop ( MF ) ) ) continue ; if ( Reg >= <STR_LIT> && Reg < <STR_LIT> + NumAlignedDPRCS2Regs ) continue ; const MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; bool isLiveIn = MRI . isLiveIn ( Reg ) ; if ( ! isLiveIn && ! MRI . isReserved ( Reg ) ) MBB . addLiveIn ( Reg ) ; if ( NoGap && LastReg && LastReg != Reg - <NUM_LIT> ) break ; LastReg = Reg ; Regs . push_back ( std :: make_pair ( Reg , ! isLiveIn ) ) ; } if ( Regs . empty ( ) ) continue ; llvm :: sort ( Regs , [ & ] ( const RegAndKill & LHS , const RegAndKill & RHS ) { return TRI . getEncodingValue ( LHS . first ) < TRI . getEncodingValue ( RHS . first ) ; } )


<s> void <ISA_LIT>FrameLowering :: emitEpilogue ( MachineFunction & MF , MachineBasicBlock & MBB ) const { assert ( false && <STR_LIT>


<s> if ( node -> isUnknown ( ) ) { return <NUM_LIT> ; } else { unsigned int k = getBytesReserved ( node ) ; MCGSiteUInt :: const_iterator siteBound ( WorstCaseSiteEnsureBound . find


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( MI . getOperand ( <NUM_LIT> ) . isImm ( ) && ! MI . getOperand ( <NUM_LIT> ) . getImm ( ) && MI . getOperand ( <NUM_LIT> ) . isFI ( ) ) { FrameIndex = MI . getOperand ( <NUM_LIT> )


<s> S -> getAssembler ( ) . setELFHeaderEFlags ( ELF :: EF_<ISA_LIT>_EABI_VER5 ) ; if ( RelaxAll ) S -> getAssembler ( ) . setRelaxAll ( true ) ; if ( NoExecStack ) S -> getAssembler ( ) . setNoExecStack (


<s> std :: set < unsigned > CurrentReads , CurrentWrites , OrigWrites ; for ( unsigned i = <NUM_LIT> ; i < CurrentInsn -> getNumOperands ( ) ; i ++ ) { MachineOperand & MO = CurrentInsn -> getOperand ( i ) ; if ( MO . isReg ( ) ) { if ( MO . isUse ( ) ) { CurrentReads . insert ( MO . getReg ( ) ) ; } if ( MO . isDef ( ) ) { CurrentWrites . insert ( MO . getReg ( ) ) ; OrigWrites . insert ( MO . getReg ( ) ) ; } } } set_intersect ( CurrentReads , PendingRegWrites ) ; set_intersect ( CurrentWrites , PendingRegWrites ) ; if ( ! ( CurrentReads . empty ( ) && CurrentWrites . empty ( ) ) ) { CurrentInsn = BuildMI ( MBB , CurrentInsn , CurrentInsn -> getDebugLoc ( ) , TM . getInstrInfo ( ) -> get ( <STR_LIT> ) , <NUM_LIT> ) ; PendingRegWrites = OrigWrites ; Changed = true ; StopBitsAdded ++


<s> if ( ! isImm ( ) ) return false ; <ISA_LIT>MCExpr :: VariantKind VK ; int64_t


<s> return ( vector signed int ) __builtin_altivec_vmsumshs ( ( vector signed short ) a1 , (

vector signed short ) a2 , ( vector signed int ) a3 ) ;


<s> return ( __m512i ) __builtin_ia32_vpdpwssd_v16si_mask ( ( __v16si ) __A , ( __v16si )


<s> MachineInstr * ReplaceTLSBaseAddrCall ( MachineInstr * I , unsigned TLSBaseAddrReg ) { MachineFunction * MF = I -> getParent ( ) -> getParent ( ) ; const <ISA_LIT>TargetMachine * TM = static_cast < const <ISA_LIT>TargetMachine * > (