<s> std :: tie ( Lo1 , Hi1 ) = DAG . SplitVectorOperand ( Op . getNode ( ) , <NUM_LIT> ) ; SDLoc SL ( Op ) ; SDValue OpLo = DAG . getNode ( Opc , SL , Lo0 . getValueType ( ) , Lo0 , Lo1 , Op -> getFlags ( ) ) ; SDValue OpHi = DAG . getNode ( Opc , SL , Hi0 . getValueType ( ) , Hi0 , Hi1 ,


<s> gcc_assert ( reg != NULL_RTX && mem != NULL_RTX && scratch != NULL_RTX ) ; fprintf ( stderr , <STR_LIT> , line , store_p ? <STR_LIT> : <STR_LIT> ) ; if ( store_p ) set = gen_rtx_SET ( VOIDmode , mem , reg ) ; else set = gen_rtx_SET ( VOIDmode , reg , mem ) ; clobber = gen_rtx_CLOBBER ( VOIDmode , scratch )


<s> if ( N0 . getOperand ( <NUM_LIT> ) == Mask ) Y = N0 . getOperand ( <NUM_LIT> ) ; if ( N0 . getOperand ( <NUM_LIT> ) == Mask ) Y = N0 . getOperand ( <NUM_LIT> ) ; if ( ! Y . getNode ( ) ) return SDValue ( ) ; Mask = peekThroughBitcasts ( Mask ) ; X = peekThroughBitcasts ( X ) ; Y = peekThroughBitcasts ( Y ) ; EVT MaskVT = Mask . getValueType ( ) ; unsigned EltBits = MaskVT . getScalarSizeInBits ( ) ; unsigned SraAmt = ~ <NUM_LIT> ; if ( Mask . getOpcode ( ) == <STR_LIT> ) { if ( auto * AmtBV = dyn_cast < BuildVectorSDNode > ( Mask . getOperand ( <NUM_LIT> ) ) ) if ( auto * AmtConst = AmtBV -> getConstantSplatNode ( ) ) SraAmt = AmtConst -> getZExtValue ( ) ; } else if ( Mask . getOpcode ( ) == <STR_LIT> ) { SDValue SraC = Mask . getOperand ( <NUM_LIT> ) ; SraAmt = cast < ConstantSDNode > ( SraC ) -> getZExtValue ( ) ; } if ( ( SraAmt + <NUM_LIT> ) != EltBits ) return SDValue ( ) ; SDLoc DL ( N ) ; if ( X . getValueType ( ) == MaskVT && Y . getValueType ( ) == MaskVT ) { auto IsNegV = [ ] ( SDNode * N , SDValue V ) { return N -> getOpcode ( ) == <STR_LIT> && N -> getOperand ( <NUM_LIT> ) == V && <STR_LIT> ( N -> getOperand ( <NUM_LIT> ) . getNode ( ) ) ; } ; SDValue V ; if ( IsNegV ( Y . getNode ( ) , X ) ) V = X ; else if ( IsNegV ( X . getNode ( ) , Y ) ) V = Y ; if ( V ) { assert ( EltBits == <NUM_LIT> || EltBits == <NUM_LIT> || EltBits == <NUM_LIT> ) ; SDValue SubOp1 = DAG . getNode ( <STR_LIT> , DL , MaskVT , V , Mask ) ; SDValue SubOp2 = Mask ; if ( V == Y ) std :: swap ( SubOp1 , SubOp2 ) ; return DAG . getBitcast ( VT , DAG . getNode ( <STR_LIT> , DL , MaskVT , SubOp1


<s>
SDValue
TFI
=
CurDAG
->
getTargetFrameIndex
(
FI
,
<STR_LIT>
)
;
if
(
Node
->
hasOneUse
(
)
)
return
CurDAG
->
SelectNodeTo
(
Node
,
<STR_LIT>
,
<STR_LIT>
,
TFI
,
CurDAG
->
getTargetConstant
(
<NUM_LIT>
,
<STR_LIT>
)
)
;
return
CurDAG
->
getTargetNode
(
<STR_LIT>
,
dl
,
<STR_LIT>
,
TFI
,
CurDAG
->
getTargetConstant
(
<NUM_LIT>
,
<STR_LIT>
)
)
;
}
}
SDNode
*
ResNode
=
SelectCode
(
Op
)
;
DOUT
(
llvm
::
dbgs
(
)
<<
std
::
string
(
Indent
<NUM_LIT>
,
' '
)
<<
<STR_LIT>
;
if
(
ResNode
==
||
ResNode
==
Op
.
getNode
(
)
)
DEBUG
(
Op
.
getNode
(
)
->
dump
(
CurDAG
)
)
;
else
DEBUG
(
ResNode
->
dump
(
CurDAG
)
)
;
DOUT
(
llvm
::
dbgs
(


<s> static inline int vec_all_eq ( vec_float4 a ,


<s> BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) , This2Reg ) . addReg ( Start2Reg ) . addMBB ( StartMBB ) . addReg ( End2Reg ) . addMBB ( LoopMBB ) ; BuildMI ( MBB , DL , TII -> get ( TargetOpcode :: COPY ) , <STR_LIT> ) . addReg ( CharReg ) ; BuildMI ( MBB , DL , TII -> get ( Opcode ) ) . addReg ( End1Reg , RegState :: Define ) . addReg ( End2Reg , RegState :: Define ) . addReg ( This1Reg ) . addReg ( This2Reg ) ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) ) . addImm ( <STR_LIT> ) . addImm ( <STR_LIT> ) . addMBB ( LoopMBB ) ; MBB -> addSuccessor ( LoopMBB ) ; MBB -> addSuccessor ( DoneMBB ) ; DoneMBB -> addLiveIn (


<s> unsigned <ISA_LIT>MachineCFGStructurizer :: storePHILinearizationInfo ( MachineInstr & PHI , SmallVector < unsigned , <NUM_LIT> > * RegionIndices ) { unsigned DestReg = getPHIDestReg ( PHI ) ; unsigned LinearizeDestReg = MRI -> createVirtualRegister ( MRI -> getRegClass ( DestReg ) ) ; PHIInfo . addDest ( LinearizeDestReg , PHI . getDebugLoc ( ) ) ; storePHILinearizationInfoDest ( LinearizeDestReg , PHI , RegionIndices ) ; return LinearizeDestReg


<s> auto Reg = StackReg . drop_front ( StackOp . size ( ) ) ; unsigned long long ParsedRegNo = <NUM_LIT> ; if ( ! Reg . empty ( ) && getAsUnsignedInteger ( Reg , <NUM_LIT> , ParsedRegNo ) ) return Error ( <STR_LIT> , StackRegTok ) ; unsigned RegNo = static_cast < unsigned > ( ParsedRegNo ) ; if ( StackOp == <STR_LIT> ) { auto RegType = ParseRegType ( TypePrefix ) ; GetType ( StackTypes , RegNo ) = RegType ; Operands . push_back ( make_unique < <ISA_LIT>Operand > ( <STR_LIT> , StackRegTok . getLoc ( ) , StackRegTok . getEndLoc ( ) , <STR_LIT> { RegNo , RegType } ) ) ; } else if ( StackOp == <STR_LIT> ) { auto RegType = GetType ( StackTypes , RegNo ) ; Operands . push_back ( make_unique < <ISA_LIT>Operand > ( <STR_LIT> , StackRegTok . getLoc ( ) , StackRegTok . getEndLoc ( ) , <STR_LIT> { RegNo , RegType } ) ) ; } else if ( StackOp == <STR_LIT> ) { } else { return Error ( <STR_LIT> , StackRegTok ) ; } Parser . Lex ( ) ; } else { return Error ( <STR_LIT> , Lexer .


<s> LoadedVT = LD -> getMemoryVT ( ) ; if ( ! LoadedVT . isVector ( ) ) return false ; Chain = LD -> getChain ( ) ; Base = LD -> getBasePtr ( ) ; Offset = LD -> getOffset ( ) ; Alignment = LD -> getAlign ( ) ; isSExtLd = LD -> getExtensionType ( ) == <STR_LIT> ; isPre = ( AM == <STR_LIT> ) || ( AM == <STR_LIT> ) ; Pred = <STR_LIT> ; PredReg = LD -> getMask ( ) ; } else llvm_unreachable ( <STR_LIT> ) ; bool CanChangeType = Subtarget -> isLittle ( ) && ! isa < MaskedLoadSDNode > ( N ) ; SDValue NewOffset ; if ( Alignment >= Align ( <NUM_LIT> ) && LoadedVT == <STR_LIT> && SelectT2AddrModeImm7Offset ( N , Offset , NewOffset , <NUM_LIT> ) ) { if ( isSExtLd ) Opcode = isPre ? <STR_LIT> : <STR_LIT> ; else Opcode = isPre ? <STR_LIT> : <STR_LIT> ; } else if ( LoadedVT == <STR_LIT> && SelectT2AddrModeImm7Offset ( N , Offset , NewOffset , <NUM_LIT> ) ) { if ( isSExtLd ) Opcode = isPre ? <STR_LIT> : <STR_LIT> ; else Opcode = isPre ? <STR_LIT> : <STR_LIT> ; } else if ( LoadedVT == <STR_LIT> && SelectT2AddrModeImm7Offset ( N , Offset , NewOffset , <NUM_LIT> ) ) { if ( isSExtLd ) Opcode = isPre ? <STR_LIT> : <STR_LIT> ; else Opcode = isPre ? <STR_LIT> : <STR_LIT> ; } else if ( Alignment >= Align ( <NUM_LIT> ) && ( CanChangeType || LoadedVT == <STR_LIT> || LoadedVT == <STR_LIT> ) && SelectT2AddrModeImm7Offset ( N , Offset , NewOffset , <NUM_LIT> ) ) Opcode = isPre ? <STR_LIT> : <STR_LIT> ; else if ( Alignment >= Align ( <NUM_LIT> ) && ( CanChangeType || LoadedVT == <STR_LIT> || LoadedVT == <STR_LIT> ) && SelectT2AddrModeImm7Offset ( N , Offset , NewOffset , <NUM_LIT> ) ) Opcode = isPre ? <STR_LIT> : <STR_LIT> ; else if ( ( CanChangeType || LoadedVT == <STR_LIT> ) && SelectT2AddrModeImm7Offset ( N , Offset , NewOffset , <NUM_LIT> ) ) Opcode = isPre ? <STR_LIT> : <STR_LIT> ; else return false


<s> if ( MO . isReg ( ) || MO . isImm ( ) ) return getMachineOpValue ( MI , MO , Fixups ) ; Fixups . push_back ( MCFixup :: Create ( <NUM_LIT> , MO . getExpr ( ) , ( MCFixupKind ) <STR_LIT> ) ) ; return


<s> static void c6x_gen_bundles ( void ) { basic_block bb ; FOR_EACH_BB_FN ( bb , cfun ) { rtx_insn * insn , * next ; rtx_insn * slot [ <NUM_LIT> ] ; int n_filled = <NUM_LIT> ; int first_slot = <NUM_LIT> ; for ( insn = BB_HEAD ( bb ) ; ; insn = next ) { int at_end ; rtx delete_this = NULL_RTX ; if ( NONDEBUG_INSN_P ( insn ) ) { if ( CALL_P ( insn ) ) { first_slot ++ ; if ( n_filled ) { memmove ( & slot [ <NUM_LIT> ] , & slot [ <NUM_LIT> ] , n_filled * sizeof ( slot [ <NUM_LIT> ] ) ) ; } if ( ! shadow_p ( insn ) ) { PUT_MODE ( insn , TImode ) ; if ( n_filled ) PUT_MODE ( slot [ <NUM_LIT> ] , VOIDmode ) ; } n_filled ++ ; slot [ <NUM_LIT> ] = insn ; } else { slot [ n_filled ++ ] = insn ; } } next = NEXT_INSN (


<s> AnalyzeFormalArguments ( CCInfo , LocalIns ) ; for ( unsigned i = <NUM_LIT> , e = Ins . size ( ) ; i < e ; ++ i ) { CCValAssign & VA = ArgLocs [ i ] ; EVT VT = Ins [ i ] . VT ; EVT MemVT = LocalIns [ i ] . VT ; if ( ShaderType != ShaderType :: COMPUTE ) { unsigned Reg = MF . addLiveIn ( VA . getLocReg ( ) , & AMDGPU :: R600_Reg128RegClass ) ; SDValue Register = DAG . getCopyFromReg ( Chain , DL , Reg , VT ) ; InVals . push_back ( Register ) ; continue ; } PointerType * PtrTy = PointerType :: get ( VT . getTypeForEVT ( * DAG . getContext ( ) ) , <STR_LIT> ) ; <STR_LIT> Ext = <STR_LIT> ; SDValue Arg = DAG . getExtLoad ( Ext , DL , VT , Chain , DAG . getConstant ( <NUM_LIT> + VA . getLocMemOffset ( ) , <STR_LIT> ) , MachinePointerInfo ( UndefValue :: get ( PtrTy ) ) , MemVT , false , false , <NUM_LIT> ) ; InVals . push_back ( Arg


<s> unsigned Binary = <NUM_LIT> ; RegM = II -> getRegisterInfo ( ) . getEncodingValue ( RegM ) ; Binary |= ( RegM & <NUM_LIT> ) ; Binary |= ( ( RegM >> <NUM_LIT> ) & <NUM_LIT> ) << <STR_LIT> ; return


<s> void <ISA_LIT>Z80AsmPrinter :: EmitInstruction ( const MachineInstr * MI ) { <ISA_LIT>Z80MCInstLower MCInstLowering ( OutContext , *


<s> switch ( MO . getType ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case MachineOperand :: MO_Register : O << <ISA_LIT>InstPrinter :: getRegisterName ( MO . getReg ( ) ) ; return ; case MachineOperand :: MO_Immediate : O << MO . getImm ( ) ; return ; case MachineOperand :: MO_MachineBasicBlock : O << * MO . getMBB ( ) -> getSymbol ( ) ; return ; case MachineOperand :: MO_GlobalAddress : { bool isMemOp = Modifier && ! strcmp ( Modifier , <STR_LIT> ) ; uint64_t Offset = MO . getOffset ( ) ; if ( isMemOp ) O << '[' ; O << * Mang -> getSymbol ( MO . getGlobal ( ) ) ; if ( Offset ) O << '+' << Offset ; if ( isMemOp ) O << ']' ; return ; } case MachineOperand :: MO_ExternalSymbol : { bool isMemOp = Modifier && ! strcmp (


<s> void GCNPassConfig :: addFastRegAlloc ( FunctionPass * RegAllocPass ) { insertPass ( & PHIEliminationID , & <ISA_LIT>LowerControlFlowID , false ) ; insertPass ( & <ISA_LIT>LowerControlFlowID , & <ISA_LIT>FixWWMLivenessID ,


<s> static bool spu_warn_func_return ( tree decl )


<s> assert ( Op . isImm ( ) && <STR_LIT> ) ; O << <ISA_LIT>CondCodeToString ( ( <STR_LIT> ) Op .


<s> if ( odd ) { OutStreamer . AddComment ( <STR_LIT> ) ; EmitInt8 ( dwarf :: DW_OP_bit_piece ) ; EmitULEB128 ( <NUM_LIT> ) ; EmitULEB128 ( <NUM_LIT> ) ; } else { OutStreamer . AddComment ( <STR_LIT> ) ; EmitInt8 ( dwarf :: DW_OP_bit_piece ) ; EmitULEB128 ( <NUM_LIT> ) ; EmitULEB128 ( <NUM_LIT> ) ; } } else if ( Reg >= <STR_LIT> && Reg <= <STR_LIT> ) { assert ( <STR_LIT> + <NUM_LIT> == <STR_LIT> && <STR_LIT> ) ; unsigned QReg = Reg - <STR_LIT> ; unsigned D1 = <NUM_LIT> + <NUM_LIT> * QReg ; unsigned D2 = D1 + <NUM_LIT> ; OutStreamer . AddComment ( <STR_LIT> ) ; EmitInt8 ( dwarf :: DW_OP_regx


<s> <ISA_LIT>MCChecker PerfCheck ( * BaseCheck , STI , false ) ; if ( canonicalizePacketImpl ( MCII , STI , Context , MCB , & PerfCheck ) ) return true ; <ISA_LIT>MCChecker ArchCheck ( * BaseCheck , * ArchSTI , true ) ; return canonicalizePacketImpl ( MCII , * ArchSTI ,


<s> static SDValue LowerAtomicLoadStore ( SDValue Op , SelectionDAG & DAG ) { if ( isStrongerThanMonotonic ( cast < AtomicSDNode > ( Op ) -> getOrdering ( ) ) ) return SDValue ( ) ; return Op


<s> bool OptForSize = MF . getFunction ( ) -> getAttributes ( ) . hasAttribute ( AttributeSet :: FunctionIndex , Attribute :: OptimizeForSize ) ; if ( ! OptForSize && Subtarget -> isSHLDSlow ( ) ) return SDValue ( ) ; if ( N0 . getOpcode ( ) == <STR_LIT> && N1 . getOpcode ( ) == <STR_LIT> ) std :: swap ( N0 , N1 ) ; if ( N0 . getOpcode ( ) != <STR_LIT> || N1 . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; if ( ! N0 . hasOneUse ( ) || ! N1 . hasOneUse ( ) ) return SDValue ( ) ; SDValue ShAmt0 = N0 . getOperand ( <NUM_LIT> ) ; if ( ShAmt0 . getValueType ( ) != <STR_LIT> ) return SDValue ( ) ; SDValue ShAmt1 = N1 . getOperand ( <NUM_LIT> ) ; if ( ShAmt1 . getValueType ( ) != <STR_LIT> ) return SDValue ( ) ; if ( ShAmt0 . getOpcode ( ) == <STR_LIT> ) ShAmt0 = ShAmt0 . getOperand ( <NUM_LIT> ) ; if ( ShAmt1 . getOpcode ( ) == <STR_LIT> ) ShAmt1 = ShAmt1 . getOperand ( <NUM_LIT> ) ; SDLoc DL ( N ) ; unsigned Opc = <STR_LIT> ; SDValue Op0 = N0 . getOperand ( <NUM_LIT> ) ; SDValue Op1 = N1 . getOperand ( <NUM_LIT> ) ; if ( ShAmt0 . getOpcode ( ) == <STR_LIT> ) { Opc = <STR_LIT> ; std :: swap ( Op0 , Op1 ) ; std :: swap ( ShAmt0 , ShAmt1 ) ; } unsigned Bits = VT . getSizeInBits ( ) ; if ( ShAmt1 . getOpcode ( ) == <STR_LIT> ) { SDValue Sum = ShAmt1 . getOperand ( <NUM_LIT> ) ; if ( ConstantSDNode * SumC = dyn_cast < ConstantSDNode > ( Sum ) ) { SDValue ShAmt1Op1 = ShAmt1 . getOperand ( <NUM_LIT> ) ; if ( ShAmt1Op1 . getNode ( ) -> getOpcode ( ) == <STR_LIT> ) ShAmt1Op1 = ShAmt1Op1 . getOperand ( <NUM_LIT> ) ; if ( SumC -> getSExtValue ( ) == Bits && ShAmt1Op1 == ShAmt0 ) return DAG . getNode ( Opc , DL , VT , Op0 , Op1 , DAG . getNode ( <STR_LIT> , DL


<s> unsigned <ISA_LIT>FastISel :: TargetMaterializeAlloca ( const AllocaInst * C ) { if ( ! FuncInfo . StaticAllocaMap . count ( C ) ) return <NUM_LIT> ; assert ( C -> isStaticAlloca ( ) && <STR_LIT> ) ; <ISA_LIT>AddressMode AM ; if ( ! <ISA_LIT>SelectAddress ( C , AM ) ) return <NUM_LIT> ; unsigned Opc = Subtarget -> is64Bit ( ) ?


<s> return StringSwitch < <ISA_LIT>MCExpr :: VariantKind > ( name ) . Case ( <STR_LIT> , VK_<ISA_LIT>_LO ) . Case ( <STR_LIT> , VK_<ISA_LIT>_HI ) . Case ( <STR_LIT> , VK_<ISA_LIT>_H44 ) . Case ( <STR_LIT> , VK_<ISA_LIT>_M44 ) . Case ( <STR_LIT> , VK_<ISA_LIT>_L44 ) . Case ( <STR_LIT> , VK_<ISA_LIT>_HH ) . Case ( <STR_LIT> , VK_<ISA_LIT>_HM ) . Case ( <STR_LIT> , VK_<ISA_LIT>_PC22 ) . Case ( <STR_LIT> , VK_<ISA_LIT>_PC10 ) . Case ( <STR_LIT> , VK_<ISA_LIT>_GOT22 ) . Case ( <STR_LIT> , VK_<ISA_LIT>_GOT10 ) . Case ( <STR_LIT> , VK_<ISA_LIT>_GOT13 ) . Case ( <STR_LIT> , VK_Sparc_R_DI<ISA_LIT>32 ) . Case ( <STR_LIT> , VK_<ISA_LIT>_TLS_GD_HI22 ) . Case ( <STR_LIT> , VK_<ISA_LIT>_TLS_GD_LO10 ) . Case ( <STR_LIT> , VK_<ISA_LIT>_TLS_GD_ADD ) . Case ( <STR_LIT> , VK_<ISA_LIT>_TLS_GD_CALL ) . Case ( <STR_LIT> , VK_<ISA_LIT>_TLS_LDM_HI22 ) . Case ( <STR_LIT> , VK_<ISA_LIT>_TLS_LDM_LO10 ) . Case ( <STR_LIT>

, VK_<ISA_LIT>_TLS_LDM_ADD ) . Case ( <STR_LIT> , VK_<ISA_LIT>_TLS_LDM_CALL ) . Case ( <STR_LIT> , VK_<ISA_LIT>_TLS_LDO_HIX22 ) . Case ( <STR_LIT> , VK_<ISA_LIT>_TLS_LDO_LOX10 ) . Case ( <STR_LIT> , VK_<ISA_LIT>_TLS_LDO_ADD ) . Case ( <STR_LIT> , VK_<ISA_LIT>_TLS_IE_HI22 ) . Case ( <STR_LIT> , VK_<ISA_LIT>_TLS_IE_LO10 ) . Case ( <STR_LIT> , VK_<ISA_LIT>_TLS_IE_LD ) . Case ( <STR_LIT> , VK_<ISA_LIT>_TLS_IE_LDX ) . Case ( <STR_LIT> , VK_<ISA_LIT>_TLS_IE_ADD ) . Case ( <STR_LIT> , VK_<ISA_LIT>_TLS_LE_HIX22 ) . Case ( <STR_LIT> , VK_<ISA_LIT>_TLS_LE_LOX10 ) . Default ( VK_<ISA_LIT>_None ) ;


<s> const MCFixupKindInfo & <ISA_LIT>AsmBackend :: getFixupKindInfo ( MCFixupKind Kind ) const { const static MCFixupKindInfo Infos [ <STR_LIT> ] = { { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT>


<s> const <ISA_LIT>Subtarget & STI = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; const TargetInstrInfo & TII = * STI . getInstrInfo ( ) ; for ( unsigned i = CSI . size ( ) ; i !=


<s> unsigned BaseRegA = <NUM_LIT> , BaseRegB = <NUM_LIT> ; int OffsetA = <NUM_LIT> , OffsetB = <NUM_LIT> ; int WidthA = <NUM_LIT> , WidthB = <NUM_LIT> ; assert ( MIa && MIa -> mayLoadOrStore ( ) && <STR_LIT> ) ; assert ( MIb && MIb -> mayLoadOrStore ( ) && <STR_LIT> ) ; if ( MIa -> hasUnmodeledSideEffects ( ) || MIb -> hasUnmodeledSideEffects ( ) || MIa -> hasOrderedMemoryRef ( ) || MIb -> hasOrderedMemoryRef ( ) ) return false ; if ( getLdStBaseRegImmOfsWidth ( MIa , BaseRegA , OffsetA , WidthA , TRI ) && getLdStBaseRegImmOfsWidth ( MIb , BaseRegB , OffsetB , WidthB , TRI ) ) { if ( BaseRegA == BaseRegB


<s> virtual const <ISA_LIT>TargetLowering * getTargetLowering ( ) const { return & TLInfo


<s> Ret . DefsSingleUse &= MRI -> hasOneNonDBGUse ( Def2 -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; Ret . DefsSingleUse &= MRI -> hasOneNonDBGUse ( Ret . CopyDefs . second -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; assert ( Def2 && <STR_LIT> ) ; Ret . TrueDefs = std :: make_pair ( Def1 , Def2 ) ; } else { Ret . TrueDefs = std :: make_pair ( Def1 , nullptr ) ; Ret . CopyDefs . second = nullptr ; } } Ret . ContainedInBlock = <NUM_LIT> ; for ( MachineInstr & UseMI : MRI -> use_nodbg_instructions ( MIParam . getOperand ( <NUM_LIT> ) . getReg ( ) ) ) { unsigned Opc = UseMI . getOpcode ( ) ; if ( Opc == <STR_LIT> || Opc == <STR_LIT> ) Ret . FeedsISEL = <NUM_LIT> ; if ( Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ) Ret . FeedsBR = <NUM_LIT> ; Ret . FeedsLogical = isCRLogical ( UseMI ) ; if ( UseMI . getParent ( ) != MIParam . getParent ( ) ) Ret . ContainedInBlock = <NUM_LIT> ; } Ret . SingleUse = MRI -> hasOneNonDBGUse ( MIParam . getOperand ( <NUM_LIT> ) . getReg ( ) ) ? <NUM_LIT> : <NUM_LIT> ; if ( ! Ret . IsNullary ) { Ret . ContainedInBlock &= ( MIParam . getParent ( ) == Ret . TrueDefs . first -> getParent ( ) ) ; if ( Ret . IsBinary ) Ret . ContainedInBlock &= ( MIParam . getParent ( ) == Ret . TrueDefs . second -> getParent ( ) ) ; } LLVM_DEBUG ( Ret . dump ( )


<s> AliasResult Result = ASAliasRules . getAliasResult ( asA , asB ) ; if ( Result == NoAlias ) return Result ; return AAResultBase :: alias ( LocA , LocB


<s> void ix86_emit_binop ( enum rtx_code code , machine_mode mode , rtx dst , rtx src ) { rtx op , clob ; op = gen_rtx_SET ( dst , gen_rtx_fmt_ee ( code , mode , dst , src ) ) ; clob = gen_rtx_CLOBBER ( VOIDmode , gen_rtx_REG ( CCmode


<s> const <ISA_LIT>Subtarget & STI = DAG . getMachineFunction ( ) . getSubtarget < <ISA_LIT>Subtarget > ( ) ; const char * bzeroName = ( V && V -> isZero ( ) ) ? DAG . getTargetLoweringInfo ( ) . getLibcallName ( RTLIB :: BZERO ) : nullptr ; if ( bzeroName && ( ! SizeValue || SizeValue -> getZExtValue ( ) > <NUM_LIT> ) ) { const <ISA_LIT>TargetLowering & TLI = * STI . getTargetLowering ( ) ; EVT IntPtr = TLI . getPointerTy ( DAG . getDataLayout ( ) ) ; Type * IntPtrTy = Type :: getInt8PtrTy ( * DAG . getContext ( ) ) ; TargetLowering :: ArgListTy Args ; TargetLowering :: ArgListEntry Entry ; Entry . Node = Dst ; Entry . Ty = IntPtrTy ; Args . push_back ( Entry ) ; Entry . Node = Size ; Args . push_back ( Entry ) ; TargetLowering :: CallLoweringInfo CLI ( DAG ) ; CLI . setDebugLoc ( dl ) . setChain ( Chain ) . setLibCallee ( CallingConv :: C , Type :: getVoidTy ( * DAG . getContext ( ) ) , DAG . getExternalSymbol ( bzeroName , IntPtr ) , std :: move ( Args ) ) . setDiscardResult ( ) ; std :: pair < SDValue , SDValue > CallResult = TLI . LowerCallTo


<s> BNE = <STR_LIT> ; BEQ = <STR_LIT> ; } else { LL = STI -> has<ISA_LIT>64r6 ( ) ? <STR_LIT> : <STR_LIT> ; SC = STI -> has<ISA_LIT>64r6 ( ) ? <STR_LIT> : <STR_LIT> ; ZERO = <STR_LIT> ; BNE = <STR_LIT> ; BEQ = <STR_LIT> ; } unsigned Dest = I -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Ptr = I -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned OldVal = I -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned NewVal = I -> getOperand ( <NUM_LIT> ) . getReg ( ) ; const BasicBlock * LLVM_BB = BB . getBasicBlock ( ) ; MachineBasicBlock * loop1MBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * loop2MBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * exitMBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineFunction :: iterator It = ++ BB . getIterator ( ) ; MF -> insert ( It , loop1MBB ) ; MF -> insert ( It , loop2MBB ) ; MF -> insert ( It , exitMBB ) ; exitMBB -> splice ( exitMBB -> begin ( ) , & BB , std :: next ( MachineBasicBlock :: iterator ( I ) ) , BB . end ( ) ) ; exitMBB -> transferSuccessorsAndUpdatePHIs ( & BB ) ; BB . addSuccessor ( loop1MBB , BranchProbability :: getOne ( ) ) ; loop1MBB -> addSuccessor ( exitMBB ) ; loop1MBB -> addSuccessor ( loop2MBB ) ; loop2MBB -> addSuccessor ( loop1MBB ) ; loop2MBB -> addSuccessor ( exitMBB ) ; BuildMI ( loop1MBB , DL , TII -> get ( LL ) , Dest ) . addReg ( Ptr ) . addImm ( <NUM_LIT> ) ; BuildMI ( loop1MBB , DL , TII -> get ( BNE ) ) . addReg ( Dest ) .

addReg ( OldVal ) . addMBB ( exitMBB ) ;


<s> TargetLoweringObjectFile * getObjFileLowering ( ) const override { return TLOF . get ( )


<s> WeakRefDirective = <STR_LIT> ; PCSymbol = <STR_LIT> ; CommentString = <STR_LIT> ; AlignmentIsInBytes = false ; AllowNameToStartWithDigit =


<s> unsigned GetRelocType ( const MCValue & Target , const MCFixup & Fixup , bool IsPCRel ) const override { return Fixup . getKind (


<s> return isMem128 ( ) && isMemIndexReg ( <STR_LIT>


<s> if ( isInt < <NUM_LIT> > ( CN -> getSExtValue ( ) ) ) { if ( FrameIndexSDNode * FIN = dyn_cast < FrameIndexSDNode > ( Addr . getOperand ( <NUM_LIT> ) ) ) Base = CurDAG -> getTargetFrameIndex ( FIN -> getIndex ( ) , <STR_LIT> ) ; else return false ; Offset = CurDAG -> getTargetConstant ( CN -> getSExtValue ( ) , DL , <STR_LIT> ) ; return true ; } return false


<s> if ( useSVEForFixedLengthVectorVT ( OpVT ) ) return LowerFixedLengthBitcastToSVE ( Op , DAG ) ; if ( OpVT . isScalableVector ( ) ) { if ( isTypeLegal ( OpVT ) && ! isTypeLegal ( ArgVT ) ) { assert ( OpVT . isFloatingPoint ( ) && ! ArgVT . isFloatingPoint ( ) && <STR_LIT> ) ; SDValue ExtResult = DAG . getNode ( <STR_LIT> , SDLoc ( Op ) , getSVEContainerType ( ArgVT ) , Op . getOperand ( <NUM_LIT> ) ) ; return getSVESafeBitCast ( OpVT , ExtResult , DAG ) ; } return getSVESafeBitCast ( OpVT , Op . getOperand ( <NUM_LIT> ) , DAG ) ; } if ( OpVT != <STR_LIT> && OpVT != <STR_LIT> ) return SDValue ( ) ; if ( ArgVT == <STR_LIT> || ArgVT == <STR_LIT> ) return Op ; assert ( ArgVT == <STR_LIT> ) ; SDLoc DL ( Op )


<s> bool hasSHSTK ( ) const { return HasSHSTK


<s> return ELF :: R_<ISA_LIT>_PREL31 ; } case <STR_LIT> : case <STR_LIT> : switch ( Modifier ) { case MCSymbolRefExpr :: VK_PLT : return ELF :: R_<ISA_LIT>_CALL ; case MCSymbolRefExpr :: VK_TLSCALL : return ELF :: R_<ISA_LIT>_TLS_CALL ; default : return ELF :: R_<ISA_LIT>_CALL ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ELF :: R_<ISA_LIT>_JUMP24 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_THM_JUMP19 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_THM_JUMP24 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_MOVT_PREL ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_MOVW_PREL_NC ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_THM_MOVT_PREL ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_THM_MOVW_PREL_NC ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_THM_JUMP11 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_THM_JUMP8 ; case <STR_LIT> : case <STR_LIT> : switch ( Modifier ) { case MCSymbolRefExpr :: VK_TLSCALL : return ELF :: R_<ISA_LIT>_THM_TLS_CALL ; default : return ELF :: R_<ISA_LIT>_THM_CALL ; } case <STR_LIT> : case <STR_LIT> : return ELF :: R_<ISA_LIT>_THM_PC8 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_THM_ALU_PREL_11_0 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_THM_PC12 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_THM_BF16 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_THM_BF12 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_THM_BF18 ; } } switch ( Fixup . getTargetKind ( ) ) { default : Ctx . reportFatalError ( Fixup . getLoc ( ) , <STR_LIT> ) ; return ELF :: R_<ISA_LIT>_NONE ; case FK_NONE : return ELF :: R_<ISA_LIT>_NONE ; case FK_Data_1 : switch ( Modifier ) { default : llvm_unreachable ( <STR_LIT> ) ; case MCSymbolRefExpr :: VK_None : return ELF :: R_<ISA_LIT>_ABS8 ; } case FK_Data_2 : switch ( Modifier ) { default : llvm_unreachable ( <STR_LIT> ) ; case MCSymbolRefExpr :: VK_None : return ELF :: R_<ISA_LIT>_ABS16 ; } case FK_Data_4 : switch ( Modifier ) { default : llvm_unreachable ( <STR_LIT> ) ; case MCSymbolRefExpr :: VK_<ISA_LIT>_NONE : return ELF :: R_<ISA_LIT>_NONE ; case MCSymbolRefExpr :: VK_GOT : return ELF :: R_<ISA_LIT>_GOT_BREL ; case MCSymbolRefExpr :: VK_TLSGD : return ELF :: R_<ISA_LIT>_TLS_GD32 ; case MCSymbolRefExpr :: VK_TPOFF : return ELF :: R_<ISA_LIT>_TLS_LE32 ; case MCSymbolRefExpr :: VK_GOTTPOFF : return ELF :: R_<ISA_LIT>_TLS_IE32 ; case MCSymbolRefExpr :: VK_None : return ELF :: R_<ISA_LIT>_ABS32 ; case MCSymbolRefExpr :: VK_GOTOFF : return ELF :: R_<ISA_LIT>_GOTOFF32 ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_PREL : return ELF :: R_<ISA_LIT>_GOT_PREL ; case MCSymbolRefExpr :: VK_<ISA_LIT>_TARGET1 : return ELF :: R_<ISA_LIT>_TARGET1 ; case MCSymbolRefExpr :: VK_<ISA_LIT>_TARGET2 : return ELF :: R_<ISA_LIT>_TARGET2 ; case MCSymbolRefExpr :: VK_<ISA_LIT>_PREL31 : return ELF :: R_<ISA_LIT>_PREL31 ; case MCSymbolRefExpr :: VK_<ISA_LIT>_SBREL : return ELF :: R_<ISA_LIT>_SBREL32 ; case MCSymbolRefExpr ::


<s> void <ISA_LIT>InstrInfo :: buildOutlinedFrame ( MachineBasicBlock & MBB , MachineFunction & MF , const outliner :: OutlinedFunction & OF ) const { if ( OF . FrameConstructionID == MachineOutlinerTailCall ) return ; MachineInstr * retq = BuildMI ( MF , DebugLoc ( ) , get ( <STR_LIT> ) ) ; MBB . insert ( MBB . end ( )


<s> bool isMSRPState ( ) const { if ( ! isSysReg ( ) ) return false ; bool


<s> return & InstrInfo . getRegisterInfo (


<s> for ( MVT Type : Types ) { if ( Grouped . empty ( ) || Grouped . back ( ) . first != Type ) Grouped . push_back ( std :: make_pair ( Type , <NUM_LIT> ) ) ; else ++ Grouped . back ( ) . second ; } Streamer . EmitULEB128IntValue ( Grouped . size ( ) ) ; for ( auto Pair : Grouped ) { Streamer . EmitULEB128IntValue ( Pair .


<s> SDValue OpLo = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , In , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; SDValue OpHi = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , In , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; OpLo = DAG . getBitcast ( <STR_LIT> , OpLo ) ; OpHi = DAG . getBitcast ( <STR_LIT> , OpHi ) ; static const int ShufMask [ ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; return DAG . getVectorShuffle ( VT , DL , OpLo , OpHi , ShufMask ) ; } if ( ( VT == <STR_LIT> ) && ( InVT == <STR_LIT> ) ) { if ( Subtarget -> hasInt256 ( ) ) { In = DAG . getBitcast ( <STR_LIT> , In ) ; SmallVector < SDValue , <NUM_LIT> > pshufbMask ; for ( unsigned i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) { pshufbMask . push_back ( DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; pshufbMask . push_back ( DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; pshufbMask . push_back ( DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; pshufbMask . push_back ( DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; pshufbMask . push_back ( DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; pshufbMask . push_back ( DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; pshufbMask . push_back ( DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; pshufbMask . push_back ( DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; for ( unsigned j = <NUM_LIT> ; j < <NUM_LIT> ; ++ j ) pshufbMask . push_back ( DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; } SDValue BV = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , pshufbMask ) ; In = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , In , BV ) ; In = DAG . getBitcast ( <STR_LIT> , In ) ; static const int ShufMask [ ] = { <NUM_LIT> , <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> } ; In = DAG . getVectorShuffle ( <STR_LIT> , DL , In , DAG . getUNDEF ( <STR_LIT> ) , & ShufMask [ <NUM_LIT> ] ) ; In = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , In , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; return DAG . getBitcast ( VT


<s> if ( SDValue V = lowerVectorShuffleWithUNPCK ( DL , <STR_LIT> , Mask , V1 , V2 , DAG ) ) return V ; if ( SDValue V = lowerVectorShuffleWithPACK ( DL , <STR_LIT> , Mask , V1 , V2 , DAG , Subtarget ) ) return V ; if ( SDValue Shift = lowerVectorShuffleAsShift ( DL , <STR_LIT> , V1 , V2 , Mask , Zeroable , Subtarget , DAG ) ) return Shift ; if ( SDValue Rotate = lowerVectorShuffleAsByteRotate ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return Rotate ; if ( SDValue PSHUFB = lowerVectorShuffleWithPSHUFB ( DL , <STR_LIT> , Mask , V1 , V2 , Zeroable


<s> void EmitARM64WinCFISaveFRegPX ( unsigned Reg , int Offset ) override { OS << <STR_LIT> << Reg <<


<s> I != E && I -> isPHI ( ) ; ++ I ) { MachineInstr * Phi = & * I ; for ( unsigned i = <NUM_LIT> , n = Phi -> getNumOperands ( ) ; i < n ; i += <NUM_LIT> ) { if ( Phi -> getOperand ( i + <NUM_LIT> ) . getMBB ( ) != Latch ) continue ; Register PhiOpReg = Phi -> getOperand ( i ) . getReg ( ) ; MachineInstr * DI = MRI -> getVRegDef ( PhiOpReg ) ; if ( DI -> getDesc ( ) . isAdd ( ) ) { Register IndReg = DI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; MachineOperand & Opnd2 = DI -> getOperand ( <NUM_LIT> ) ; int64_t V ; if ( MRI -> getVRegDef ( IndReg ) == Phi && checkForImmediate ( Opnd2 , V ) ) { Register UpdReg = DI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; IndMap . insert ( std :: make_pair ( UpdReg , std :: make_pair ( IndReg , V ) ) ) ; } } } } SmallVector < MachineOperand , <NUM_LIT> > Cond ; MachineBasicBlock * TB = nullptr , * FB = nullptr ; bool NotAnalyzed = TII -> analyzeBranch ( * ExitingBlock , TB , FB , Cond , false ) ; if ( NotAnalyzed ) return false ; unsigned PredR , PredPos , PredRegFlags ; if ( ! TII -> getPredReg ( Cond , PredR , PredPos , PredRegFlags ) ) return false ; MachineInstr * PredI = MRI -> getVRegDef ( PredR ) ; if ( ! PredI -> isCompare ( ) ) return false ; unsigned CmpReg1 = <NUM_LIT> , CmpReg2 = <NUM_LIT> ; int CmpImm = <NUM_LIT> , CmpMask = <NUM_LIT> ; bool CmpAnalyzed = TII -> analyzeCompare ( * PredI , CmpReg1 , CmpReg2 , CmpMask , CmpImm ) ; if ( ! CmpAnalyzed ) return false ; InductionMap :: iterator IndMapEnd = IndMap . end ( ) ; InductionMap :: iterator F = IndMapEnd ; if ( CmpReg1 != <NUM_LIT> ) { InductionMap :: iterator F1 = IndMap . find ( CmpReg1 ) ; if ( F1 != IndMapEnd ) F = F1 ; } if ( CmpReg2


<s> rtx ret ; start_sequence ( ) ; emit_insn ( gen_rtx_SET ( cr_reg , gen_rtx_fmt_ee ( GET_CODE ( test ) , GET_MODE ( cr_reg ) , cc_reg , const0_rtx ) ) ) ; emit_move_insn ( dest , GEN_INT ( value


<s> bool <ISA_LIT>AsmPrinter :: PrintAsmMemoryOperand ( const MachineInstr * MI , unsigned OpNum , const char * ExtraCode , raw_ostream & O ) { if ( ExtraCode && ExtraCode [ <NUM_LIT> ] && ExtraCode [ <NUM_LIT> ] != 'a' ) return true ; const MachineOperand & MO = MI -> getOperand (


<s> unsigned int s390_case_values_threshold ( void


<s> case 'f' : case 'v' : return RegName + <NUM_LIT> ; case 'c' : if ( RegName [ <NUM_LIT> ] == 'r' ) return RegName + <NUM_LIT> ; } return


<s> bool NamedImmMapper :: validImm ( uint32_t


<s> unsigned <ISA_LIT>InstrInfo :: InsertBranch ( MachineBasicBlock & MBB , MachineBasicBlock * TBB , MachineBasicBlock * FBB , const SmallVectorImpl < MachineOperand > & Cond , DebugLoc DL ) const { assert ( TBB && <STR_LIT> ) ; assert ( ( Cond . size ( ) == <NUM_LIT> || Cond . size ( ) == <NUM_LIT> ) && <STR_LIT> ) ; if ( Cond . empty ( ) ) { assert ( ! FBB && <STR_LIT> ) ; BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addMBB ( TBB ) ; return <NUM_LIT> ; } unsigned Count = <NUM_LIT> ; BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addMBB ( TBB ) . addImm ( Cond [ <NUM_LIT> ] . getImm ( ) ) ; Count ++ ; if ( FBB


<s> cum -> count = <NUM_LIT> ; cum -> nregs = <NUM_LIT> ; if ( ! libname && fntype ) { if ( stdarg_p ( fntype ) ) cum -> nregs = type_num_arguments ( fntype ) - <NUM_LIT> ; if ( cum -> nregs > <NUM_LIT> )


<s> static int loongarch_set_reg_reg_piece_cost ( machine_mode mode , unsigned int units ) { return COSTS_N_INSNS ( ( GET_MODE_SIZE ( mode ) + units -


<s> if ( flags & SectionFlags :: Code ) Flags += 'x' ; if ( flags & SectionFlags :: Writeable ) Flags


<s> auto CachePolicyConst = cast < ConstantSDNode > ( CachePolicy . getNode ( ) ) ; uint64_t Value = CachePolicyConst -> getZExtValue ( ) ; SDLoc DL ( CachePolicy ) ; if ( GLC ) { * GLC = DAG . getTargetConstant ( ( Value & <NUM_LIT> ) ? <NUM_LIT> : <NUM_LIT> , DL , <STR_LIT> ) ; Value &= ~ ( uint64_t ) <NUM_LIT> ; } if ( SLC ) { * SLC = DAG . getTargetConstant ( ( Value & <NUM_LIT> ) ? <NUM_LIT> : <NUM_LIT> , DL , <STR_LIT> ) ; Value &= ~ ( uint64_t ) <NUM_LIT> ; } return Value == <NUM_LIT>


<s> for ( unsigned i = <NUM_LIT> ; i < NumFixedOperands ; ++ i ) { const MCOperandInfo & Info = Desc . OpInfo [ i ] ; switch ( Info . OperandType ) { case MCOI :: OPERAND_IMMEDIATE : case <STR_LIT> : case <STR_LIT> : { if ( Pos + sizeof ( uint64_t ) > Bytes . size ( ) ) return MCDisassembler :: Fail ; uint64_t Imm = <STR_LIT> :: read64le ( Bytes . data ( ) + Pos ) ; Pos += sizeof ( uint64_t ) ; MI . addOperand ( MCOperand :: createImm ( Imm ) ) ; break ; } case MCOI :: OPERAND_REGISTER : { if ( Pos + sizeof ( uint64_t ) > Bytes . size ( ) ) return MCDisassembler :: Fail ; uint64_t Reg = <STR_LIT> :: read64le ( Bytes . data ( ) + Pos ) ; Pos += sizeof ( uint64_t ) ; MI . addOperand ( MCOperand :: createReg ( Reg ) ) ; break ; } case <STR_LIT> : { if ( Pos + sizeof ( uint64_t ) > Bytes . size ( ) ) return MCDisassembler


<s> int64_t Res ; if ( A -> getVariableValue ( ) -> evaluateAsAbsolute ( Res , Layout , Writer -> getSectionAddressMap ( ) ) ) { FixedValue = Res ; return ; } } if ( requiresExternRelocation ( Writer , Asm , * Fragment , RelocType , * A , FixedValue ) ) { RelSymbol = A ; if ( ! A -> isUndefined ( ) ) FixedValue -= Layout . getSymbolOffset ( * A ) ; } else { const MCSection & Sec = A -> getSection ( ) ; Index = Sec . getOrdinal ( ) + <NUM_LIT> ; FixedValue += Writer -> getSectionAddress ( & Sec ) ; } if ( IsPCRel ) FixedValue -= Writer -> getSectionAddress ( Fragment -> getParent ( ) ) ; Type = RelocType ; } MachO :: any_relocation_info MRE ; MRE . r_word0 = FixupOffset ; MRE . r_word1 = ( Index << <NUM_LIT> ) | ( IsPCRel << <NUM_LIT> ) | ( Log2Size << <NUM_LIT> ) | ( Type << <NUM_LIT> ) ; if ( Type == MachO :: <ISA_LIT>_RELOC_HALF ) { uint32_t Value = <NUM_LIT> ; switch ( ( unsigned ) Fixup . getKind ( ) ) { default : break ; case <STR_LIT> : case <STR_LIT> : Value = ( FixedValue >> <NUM_LIT> ) & <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : Value = FixedValue &


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL , bool is64Bit ) : LLVMTargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL ) , Subtarget ( TT , CPU , FS , * this , is64Bit , OL ) { initAsmInfo (


<s> static SDValue getAbsolute ( SelectionDAG & DAG , SDLoc DL , SDValue Op , bool IsNegative ) { Op = DAG . getNode ( <STR_LIT> , DL , Op . getValueType ( ) , Op ) ; if ( IsNegative ) Op = DAG . getNode ( <STR_LIT> , DL , Op . getValueType ( ) , DAG .

getConstant ( <NUM_LIT> , Op . getValueType ( ) ) , Op ) ;


<s> uint32_t <ISA_LIT>MCCodeEmitter :: getHiLo16ImmOpValue ( const MCInst & MI , unsigned OpIdx , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { const MCOperand & MO = MI . getOperand ( OpIdx ) ; if ( MO . isImm ( ) ) return static_cast < unsigned > ( MO . getImm ( ) ) ; const MCExpr * E = MO . getExpr ( ) ; MCFixupKind Kind ; if ( E -> getKind ( ) == MCExpr :: Target ) { const <ISA_LIT>MCExpr * <ISA_LIT>16Expr = cast < <ISA_LIT>MCExpr > ( E ) ; E = <ISA_LIT>16Expr -> getSubExpr ( ) ; if ( const MCConstantExpr * MCE = dyn_cast < MCConstantExpr > ( E ) ) { const int64_t Value = MCE -> getValue ( ) ; if ( Value > UINT32_MAX ) report_fatal_error ( <STR_LIT> ) ; switch ( <ISA_LIT>16Expr -> getKind ( ) ) { case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_HI16 : return ( int32_t ( Value ) & <NUM_LIT> ) >> <NUM_LIT> ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_LO16 : return ( int32_t ( Value ) & <NUM_LIT> ) ; default : llvm_unreachable ( <STR_LIT> ) ; } } switch ( <ISA_LIT>16Expr -> getKind ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_HI16


<s> else if ( mode == V2DImode ) { if ( GET_CODE ( CONST_VECTOR_ELT ( op , <NUM_LIT> ) ) != CONST_INT || GET_CODE ( CONST_VECTOR_ELT ( op , <NUM_LIT> ) ) != CONST_INT ) return false ; if ( zero_constant ( op , mode ) ) return true ; if ( INTVAL ( CONST_VECTOR_ELT ( op , <NUM_LIT> ) ) == - <NUM_LIT> && INTVAL ( CONST_VECTOR_ELT ( op , <NUM_LIT> ) ) == - <NUM_LIT> ) return true ; return false ; } else if ( mode == V1TImode ) return false ; step = GET_MODE_NUNITS ( mode ) /


<s> void ValueEnumerator :: EnumerateAttributes ( AttributeList PAL ) { if ( PAL . isEmpty ( ) ) return ; unsigned & Entry = AttributeListMap [ PAL ] ; if ( Entry == <NUM_LIT> ) { AttributeLists . push_back ( PAL ) ; Entry = AttributeLists . size ( ) ; } for ( unsigned i : PAL . indexes


<s> unsigned SrcReg = Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ; int32_t ImmValue = Inst . getOperand ( <NUM_LIT> ) . getImm ( ) ; ATReg = getATReg ( IDLoc ) ; if ( ! ATReg ) return true ; loadImmediate ( ImmValue , ATReg , <STR_LIT> , true , false


<s> assert ( V1 . getSimpleValueType ( ) . is128BitVector ( ) && <STR_LIT> ) ; assert ( V2 . getSimpleValueType ( ) . is128BitVector ( ) && <STR_LIT> ) ; assert ( Mask . size ( ) == <NUM_LIT> && <STR_LIT> ) ; auto matchAsInsertPS = [ & ] ( SDValue VA , SDValue VB , ArrayRef < int > CandidateMask ) { unsigned ZMask = <NUM_LIT> ; int VADstIndex = - <NUM_LIT> ; int VBDstIndex = - <NUM_LIT> ; bool VAUsedInPlace = false ; for ( int i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) { if ( Zeroable [ i ] ) { ZMask |= <NUM_LIT> << i ; continue ; } if ( i == CandidateMask [ i ] ) { VAUsedInPlace = true ; continue ; } if ( VADstIndex >= <NUM_LIT> || VBDstIndex >= <NUM_LIT> ) return false ; if ( CandidateMask [ i ] < <NUM_LIT> ) { VADstIndex = i ; } else { VBDstIndex =


<s> rtx riscv_return_addr ( int count , rtx frame ATTRIBUTE_UNUSED ) { if ( count != <NUM_LIT>


<s> struct mips_arg_info info ; if ( ( f & <NUM_LIT> ) == <NUM_LIT> ) mode = SFmode ; else if ( ( f & <NUM_LIT> ) == <NUM_LIT> ) mode = DFmode ; else gcc_unreachable ( ) ; mips_get_arg_info ( & info , & cum , mode , NULL , true ) ; gparg = mips_arg_regno ( & info , false ) ; fparg = mips_arg_regno ( & info , true ) ; if ( mode == SFmode ) mips_output_32bit_xfer ( direction , gparg , fparg ) ; else mips_output_64bit_xfer ( direction , gparg , fparg ) ; mips_function_arg_advance ( pack_cumulative_args ( & cum ) ,


<s> return ( ( TARGET_RTD && ( ! fundecl || TREE_CODE ( fundecl ) != IDENTIFIER_NODE ) && ( !

stdarg_p ( funtype ) ) ) ? ( HOST_WIDE_INT ) size : <NUM_LIT> ) ;


<s> bool <ISA_LIT>MCExpr :: evaluateAsRelocatableImpl ( MCValue & Res , const MCAsmLayout * Layout , const MCFixup *


<s> LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << <STR_LIT> << L -> getNumBlocks ( ) << <STR_LIT> << <STR_LIT> << ExitingBlocks . size ( ) << <STR_LIT> ) ; if ( ExitingBlocks . size ( ) > <NUM_LIT> ) return ; if ( L -> getNumBlocks ( ) > <NUM_LIT> ) return ; if ( getBooleanLoopAttribute ( L , <STR_LIT> ) ) return ; InstructionCost Cost = <NUM_LIT> ; for ( auto * BB : L -> getBlocks ( ) ) { for ( auto & I : * BB ) { if ( I . getType ( ) -> isVectorTy ( ) ) return ; if ( isa < CallInst > ( I ) || isa < InvokeInst > ( I ) ) { if ( const Function * F = cast < CallBase > ( I ) . getCalledFunction ( ) ) { if ( ! isLoweredToCall ( F ) ) continue ; } return ; } SmallVector < const Value * > Operands ( I . operand_values ( ) ) ; Cost += getUserCost ( & I , Operands , TargetTransformInfo :: TCK_SizeAndLatency ) ; } } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << Cost << <STR_LIT> ) ; UP . Partial = true ; UP . Runtime = true


<s> default : return MCDisassembler :: Fail ; } if ( Inst . getOpcode ( ) == <STR_LIT> ) { unsigned Mask = fieldFromInstruction ( Val , <NUM_LIT> , <NUM_LIT> ) ; if ( ! ( FeatureBits [ <STR_LIT> ] ) ) { if ( Mask != <NUM_LIT> ) S = MCDisassembler :: SoftFail ; } else { if ( Mask == <NUM_LIT> || ( Mask != <NUM_LIT> && ValLow > <NUM_LIT> ) || ( ! ( FeatureBits [ <STR_LIT> ] ) && ( Mask & <NUM_LIT> ) ) ) S = MCDisassembler :: SoftFail ; } } } else { if ( Val == <NUM_LIT> ) return MCDisassembler :: Fail ; } Inst . addOperand ( MCOperand :: createImm


<s> rtx tmp = op ; if ( SUBREG_P ( tmp ) ) tmp = SUBREG_REG ( tmp ) ; if ( REG_P ( tmp ) && REGNO ( tmp ) >=


<s> MIB . addReg ( DestReg , RegState :: Undef


<s> void llvm :: emitFrameOffset ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI , const DebugLoc & DL , unsigned DestReg , unsigned SrcReg , StackOffset Offset , const TargetInstrInfo * TII , MachineInstr :: MIFlag Flag , bool SetNZCV , bool NeedsWinCFI , bool * HasWinCFI ) { int64_t Bytes


<s> default : return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> SmallVectorImpl < CCValAssign > & PendingMembers = State . getPendingLocs ( ) ; if ( ! ArgFlags . isSplit ( ) && PendingMembers . empty ( ) ) return false ; LocVT = <STR_LIT> ; LocInfo = CCValAssign :: Indirect ; PendingMembers . push_back ( CCValAssign :: getPending ( ValNo , ValVT , LocVT , LocInfo ) ) ; if ( ! ArgFlags . isSplitEnd ( ) ) return true ; unsigned Reg = State . AllocateReg ( <STR_LIT> ) ; unsigned Offset = Reg ? <NUM_LIT> : State . AllocateStack ( <NUM_LIT> , Align ( <NUM_LIT> ) ) ; for ( auto & It : PendingMembers ) { if ( Reg ) It . convertToReg ( Reg ) ; else It . convertToMem ( Offset ) ; State . addLoc ( It


<s> if ( SrcVT == <STR_LIT> && TLI . isTypeLegal ( SrcVT ) ) return DAG . getNode ( <STR_LIT> , dl , Op . getValueType ( ) , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Src ) ) ; MVT IntegerVT = <STR_LIT> ( <STR_LIT> , SrcVT . getVectorNumElements ( ) ) ; return DAG . getNode ( <STR_LIT> , dl , Op . getValueType ( ) , DAG . getNode ( <STR_LIT> , dl , IntegerVT , Src ) ) ; } return SDValue ( ) ; } assert ( SrcVT <= <STR_LIT> && SrcVT >= <STR_LIT> && <STR_LIT> ) ; if ( SrcVT == <STR_LIT> && isScalarFPTypeInSSEReg ( Op . getValueType ( ) ) ) return Op ; if ( SrcVT == <STR_LIT> && isScalarFPTypeInSSEReg ( Op . getValueType ( ) ) && Subtarget . is64Bit ( ) ) { return Op ; } SDValue ValueToStore = Op . getOperand ( <NUM_LIT> ) ; if ( SrcVT == <STR_LIT> && isScalarFPTypeInSSEReg ( Op . getValueType ( ) ) && ! Subtarget . is64Bit ( ) ) ValueToStore = DAG . getBitcast ( <STR_LIT> , ValueToStore ) ; unsigned Size = SrcVT . getSizeInBits ( ) / <NUM_LIT> ; MachineFunction & MF = DAG . getMachineFunction ( ) ; auto PtrVT = getPointerTy ( MF . getDataLayout ( ) ) ; int SSFI = MF . getFrameInfo ( ) . CreateStackObject ( Size , Size , false ) ; SDValue StackSlot = DAG . getFrameIndex ( SSFI , PtrVT ) ; SDValue Chain = DAG . getStore ( DAG . getEntryNode ( ) , dl , ValueToStore , StackSlot , MachinePointerInfo :: getFixedStack

( DAG . getMachineFunction ( ) , SSFI ) ) ;


<s> assert ( LD -> isUnindexed ( ) && <STR_LIT> ) ; if ( MemVT == <STR_LIT> && Subtarget -> hasV5TEOps ( ) && ! Subtarget -> isThumb1Only ( ) && LD -> isVolatile ( ) ) { SDLoc dl ( N ) ; SDValue Result = DAG . getMemIntrinsicNode ( <STR_LIT> , dl , DAG . getVTList ( { <STR_LIT> , <STR_LIT> , <STR_LIT> } ) , { LD -> getChain ( ) , LD -> getBasePtr (

) } , MemVT , LD -> getMemOperand ( ) ) ;


<s> if ( Rt == <NUM_LIT> ) { switch ( Inst . getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : Inst . setOpcode ( <STR_LIT> ) ; break ; case <STR_LIT> : Inst . setOpcode ( <STR_LIT> ) ; break ; case <STR_LIT> : return MCDisassembler :: Fail ; default : break ; } } switch ( Inst . getOpcode ( ) ) { case <STR_LIT>


<s> unsigned FuncOp = isThumb ? <NUM_LIT> : <NUM_LIT> ; unsigned Opc = Call -> getOperand ( FuncOp ) . isReg ( ) ? isThumb ? <STR_LIT> : <STR_LIT> : isThumb ? Subtarget . isTargetMachO ( ) ? <STR_LIT> : <STR_LIT> : <STR_LIT> ; MachineInstrBuilder MIB = BuildMI ( MBB , MBB . end ( ) , DebugLoc ( ) , get ( Opc ) ) . add ( Call -> getOperand ( FuncOp ) ) ; if ( isThumb && ! Call -> getOperand ( FuncOp ) . isReg ( ) ) MIB . add ( predOps ( <STR_LIT> ) ) ; Call -> eraseFromParent ( ) ; return ; } BuildMI ( MBB , MBB . end ( ) , DebugLoc ( ) , get ( Subtarget . getReturnOpcode ( ) ) ) . add ( predOps (


<s> if ( Inst . getNumOperands ( ) == <NUM_LIT> ) { emitToStreamer ( Out , MCInstBuilder ( Opcode ) . addOperand ( Inst . getOperand ( <NUM_LIT> ) ) . addOperand ( Inst . getOperand ( <NUM_LIT> ) ) . addOperand ( Inst . getOperand ( <NUM_LIT> ) ) . addReg ( <STR_LIT> ) ) ; emitToStreamer ( Out , MCInstBuilder ( <STR_LIT> ) . addOperand ( Inst . getOperand ( <NUM_LIT> ) ) . addOperand ( Inst . getOperand ( <NUM_LIT> ) ) . addOperand ( Inst . getOperand ( <NUM_LIT> ) ) ) ; } else if ( Inst . getNumOperands ( ) == <NUM_LIT> ) { assert ( Inst . getOperand ( <NUM_LIT> ) . getReg ( ) != <STR_LIT> && <STR_LIT> ) ; emitToStreamer ( Out , MCInstBuilder ( Opcode ) . addOperand ( Inst . getOperand ( <NUM_LIT> ) ) . addOperand ( Inst . getOperand ( <NUM_LIT> ) ) . addOperand ( Inst . getOperand ( <NUM_LIT> ) ) . addOperand ( Inst


<s> const <ISA_LIT>FunctionInfo * <ISA_LIT>FI = MF -> getInfo < <ISA_LIT>FunctionInfo > ( ) ; if ( <ISA_LIT>FI -> usesPICBase ( ) ) { MCSymbol * RelocSymbol = <ISA_LIT>FI -> getPICOffsetSymbol ( ) ; MCSymbol * PICBase = MF -> getPICBaseSymbol ( ) ; OutStreamer . EmitLabel ( RelocSymbol ) ; const MCExpr * OffsExpr = MCBinaryExpr :: CreateSub ( MCSymbolRefExpr :: Create ( OutContext . GetOrCreateSymbol ( Twine ( <STR_LIT> ) ) , OutContext ) , MCSymbolRefExpr :: Create ( PICBase , OutContext ) , OutContext ) ; OutStreamer . EmitValue ( OffsExpr , <NUM_LIT> ) ; OutStreamer . EmitLabel ( CurrentFnSym ) ; return ; } else return AsmPrinter :: EmitFunctionEntryLabel ( ) ; } if ( Subtarget . isELFv2ABI ( ) ) return AsmPrinter :: EmitFunctionEntryLabel ( ) ; MCSectionSubPair Current = OutStreamer . getCurrentSection ( ) ; const MCSectionELF * Section = OutStreamer . getContext ( ) . getELFSection ( <STR_LIT> , ELF :: SHT_PROGBITS , ELF :: SHF_WRITE | ELF :: SHF_ALLOC , SectionKind :: getReadOnly ( ) ) ; OutStreamer . SwitchSection ( Section ) ; OutStreamer . EmitLabel (


<s> zero = v4sf_const0 ; } else { dest_vecmode = V2DFmode ; zero = gen_rtx_SUBREG ( V2DFmode , v4sf_const0 , <NUM_LIT> ) ; } src = gen_rtx_VEC_DUPLICATE ( dest_vecmode , src ) ; src = gen_rtx_VEC_MERGE ( dest_vecmode , src , zero , GEN_INT ( HOST_WIDE_INT_1U ) ) ; rtx vec = gen_reg_rtx ( dest_vecmode ) ; set = gen_rtx_SET ( vec , src ) ; set_insn = emit_insn_before ( set , insn ) ; df_insn_rescan ( set_insn ) ; if ( cfun -> can_throw_non_call_exceptions ) { rtx note = find_reg_note ( insn , REG_EH_REGION , NULL_RTX ) ; if ( note ) { control_flow_insns . safe_push ( set_insn ) ; add_reg_note ( set_insn , REG_EH_REGION , XEXP ( note , <NUM_LIT> ) ) ; } } src = gen_rtx_SUBREG ( dest_mode , vec , <NUM_LIT> ) ; set = gen_rtx_SET ( dest


<s> if ( Subtarget -> isTargetELF ( ) ) { auto & TLOFELF = static_cast < const TargetLoweringObjectFileELF & > ( getObjFileLowering ( ) ) ; MachineModuleInfoELF & MMIELF = MMI -> getObjFileInfo < MachineModuleInfoELF > ( ) ; MachineModuleInfoELF :: SymbolListTy Stubs = MMIELF . GetGVStubList ( ) ; if ( ! Stubs . empty ( ) ) { OutStreamer . SwitchSection ( TLOFELF . getDataRelSection ( ) ) ; const DataLayout * TD = TM . getDataLayout ( ) ; for ( unsigned i = <NUM_LIT> , e = Stubs . size (


<s> unsigned IntVal ; if ( NumString . getAsInteger ( <NUM_LIT> , IntVal ) ) return MatchOperand_NoMatch ; unsigned Reg = matchRegisterByNumber ( IntVal , <STR_LIT> ) ; <ISA_LIT>Operand * Op = <STR_LIT> ( Reg , S , Parser . getTok ( ) . getLoc ( ) ) ; Op -> setRegKind ( <STR_LIT> ) ; Operands . push_back ( Op ) ; Parser . Lex


<s> if ( ! AsmParser . useOddSPReg ( ) && RegIdx . Index & <NUM_LIT> ) AsmParser . getParser ( ) . printError


<s> bool isABI_N64 ( ) const { return ABI . IsN64


<s> const DataLayout & DL = CurDAG -> getDataLayout ( ) ; const MachineFrameInfo & MFI = MF -> getFrameInfo ( ) ; if ( N . getOpcode ( ) == <STR_LIT> ) { int FI = cast < FrameIndexSDNode > ( N ) -> getIndex ( ) ; if ( FI == <NUM_LIT> || MFI . getStackID ( FI ) == TargetStackID :: ScalableVector ) { Base = CurDAG -> getTargetFrameIndex ( FI , TLI -> getPointerTy ( DL ) ) ; OffImm = CurDAG -> getTargetConstant ( <NUM_LIT> , SDLoc ( N ) , <STR_LIT> ) ; return true ; } return false ; } if ( MemVT == EVT ( ) ) return


<s> if ( ar_arp ) { return <STR_LIT> + std :: to_string ( ( ( ar_arp -> arp [ a . Index ( ) ]

>> <NUM_LIT> ) & <NUM_LIT> ) + <NUM_LIT> ) ;


<s> AMDGPUAsmParser :: OperandMatchResultTy AMDGPUAsmParser :: parseSLC ( OperandVector


<s> MachineFunction & MF = * MBB . getParent ( ) ; MachineConstantPool * ConstantPool = MF . getConstantPool ( ) ; const Constant * C = ConstantInt :: get ( Type :: getInt32Ty ( MBB . getParent ( ) -> getFunction ( ) -> getContext ( ) ) , Val ) ; unsigned Idx = ConstantPool -> getConstantPoolIndex ( C


<s> VPTBlock ( MachineInstr * MI , SetVector < MachineInstr * > & Preds ) { VPST = std :: make_unique < PredicatedMI


<s> static void packCmovGroup ( MachineInstr * First , MachineInstr * Last ) { assert ( <STR_LIT> ( Last -> getOpcode ( ) ) != <STR_LIT> && <STR_LIT> ) ; SmallVector < MachineInstr * , <NUM_LIT> > DBGInstructions ; for ( auto I = First -> getIterator ( ) , E = Last -> getIterator ( ) ; I != E ; I ++ ) { if ( I -> isDebugValue ( ) ) DBGInstructions .


<s> void pattern3_xpp ( StackFixup & Rv , unsigned i , unsigned j , unsigned k ) { if ( i == <NUM_LIT> ) return pattern2_pp ( Rv , j , k ) ; XchgPairCorrector CorrectI ( i , <NUM_LIT> ) ; CorrectI ( j )


<s> void <ISA_LIT>BitcodeWriter :: writeDISubrange ( const DISubrange * N , SmallVectorImpl < uint64_t > & Record , unsigned Abbrev ) { Record . push_back ( N -> isDistinct (


<s> unsigned FrameReg = RegInfo -> getFrameRegister ( DAG . getMachineFunction ( ) ) ; assert ( ( ( FrameReg == <STR_LIT> && VT == <STR_LIT> ) || ( FrameReg == <STR_LIT> && VT == <STR_LIT> ) ) && <STR_LIT> ) ; SDValue FrameAddr = DAG . getCopyFromReg ( DAG . getEntryNode ( ) , dl , FrameReg , VT ) ; while ( Depth -- ) FrameAddr = DAG . getLoad ( VT , dl , DAG . getEntryNode (

) , FrameAddr , MachinePointerInfo ( ) , false , false , false , <NUM_LIT> ) ;


<s> assert ( GA -> getTargetFlags ( ) == <NUM_LIT> && <STR_LIT> ) ; if ( GA -> getAddressSpace ( ) != <NUM_LIT> ) fail ( DL , DAG , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , DL , VT , DAG . getTargetGlobalAddress ( GA -> getGlobal ( ) , DL , VT ,


<s> ArrayRef < MCPhysReg > <ISA_LIT>ABIInfo :: GetByValArgRegs ( ) const { if ( IsCheriPureCap ( ) ) return { } ; if ( IsO32 ( ) ) return makeArrayRef ( O32IntRegs ) ; if ( IsN32 ( ) || IsN64 ( ) ) return makeArrayRef (


<s> if ( ALTIVEC_OR_VSX_VECTOR_MODE ( mode2 ) ) return false ; if ( SCALAR_FLOAT_MODE_P ( mode1 ) ) return SCALAR_FLOAT_MODE_P ( mode2 ) ; if ( SCALAR_FLOAT_MODE_P ( mode2 ) ) return false ; if ( GET_MODE_CLASS ( mode1 ) == MODE_CC ) return GET_MODE_CLASS ( mode2 )


<s> return getTargetMachine ( ) . getInstrInfo (


<s> return ( ( GET_MODE_SIZE ( mode ) + UNITS_PER_WORD - <NUM_LIT> )


<s> SDValue Op1 = convertToScalableVector ( ContainerVT , Op . getOperand ( <NUM_LIT> ) , DAG , Subtarget ) ; SDValue Op2 = convertToScalableVector ( ContainerVT , Op . getOperand ( <NUM_LIT> ) , DAG , Subtarget ) ; SDLoc DL ( Op ) ; SDValue Mask , VL ; std :: tie ( Mask , VL ) = getDefaultVLOps ( VT , ContainerVT , DL , DAG , Subtarget ) ; SDValue Select = DAG . getNode ( <STR_LIT> , DL , ContainerVT , CC , Op1 , Op2 , VL ) ; return convertFromScalableVector ( VT , Select ,


<s> assert ( ST -> hasNEON ( ) && <STR_LIT> ) ; assert ( ( VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> || VT


<s> else if ( isa < PointerType > ( Ty ) ) { O << <STR_LIT> << TLI -> getPointerTy ( ) . getSizeInBits ( ) << <STR_LIT> ; } else { if ( ( Ty -> getTypeID ( ) == Type :: StructTyID ) || isa < VectorType > ( Ty ) ) { SmallVector < EVT , <NUM_LIT> > vtparts ; ComputeValueVTs ( * TLI , Ty , vtparts ) ; unsigned totalsz = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> , e = vtparts . size ( ) ; i != e ; ++ i ) { unsigned elems = <NUM_LIT> ; EVT elemtype = vtparts [ i ] ; if ( vtparts [ i ] . isVector ( ) ) { elems = vtparts [ i ] . getVectorNumElements ( ) ; elemtype = vtparts [ i ] . getVectorElementType ( ) ; } for ( unsigned j = <NUM_LIT> , je = elems ; j != je ; ++ j ) { unsigned sz = elemtype . getSizeInBits ( ) ; if ( elemtype . isInteger ( ) && ( sz < <NUM_LIT> ) ) sz = <NUM_LIT> ; totalsz += sz / <NUM_LIT> ; } } unsigned retAlignment = <NUM_LIT> ; if ( ! llvm :: getAlign ( * F , <NUM_LIT> , retAlignment ) ) retAlignment = TD -> getABITypeAlignment ( Ty ) ; O << <STR_LIT> << retAlignment << <STR_LIT> << totalsz << <STR_LIT> ; } else assert ( false && <STR_LIT> ) ; } } else { SmallVector < EVT , <NUM_LIT> > vtparts ; ComputeValueVTs ( * TLI , Ty , vtparts ) ; unsigned idx = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> , e = vtparts . size ( ) ; i != e ; ++ i ) { unsigned elems = <NUM_LIT> ; EVT elemtype = vtparts [ i ] ; if ( vtparts [ i ] . isVector ( ) ) { elems = vtparts [ i ] . getVectorNumElements ( ) ; elemtype = vtparts [ i


<s> bool ProfitableArch = Subtarget -> isCortexA57 ( ) ; return ProfitableArch && ! Subtarget


<s> SDValue Elt = DAG . getNode ( <STR_LIT> , SL , EltVT , Vec . getOperand ( <NUM_LIT> ) , Idx ) ; return DAG . getNode ( Vec . getOpcode ( ) , SL , EltVT , Elt ) ; } if ( Vec . hasOneUse ( ) && DCI . isBeforeLegalize ( ) ) { SDLoc SL ( N ) ; EVT EltVT = N -> getValueType ( <NUM_LIT> ) ; SDValue Idx = N -> getOperand ( <NUM_LIT> ) ; unsigned Opc = Vec . getOpcode ( ) ; switch ( Opc ) { default : return SDValue (


<s> static bool ix86_pic_register_p ( rtx x ) { if ( GET_CODE ( x ) == VALUE && CSELIB_VAL_PTR ( x ) ) return ( pic_offset_table_rtx && rtx_equal_for_cselib_p ( x , pic_offset_table_rtx ) ) ; else if ( ! REG_P ( x )


<s> Reserved . set ( <STR_LIT> ) ; } if ( Subtarget . is<ISA_LIT>64 ( ) ) { Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; if ( ! EnableRegisterScavenging ) Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; if ( Subtarget . isSVR4ABI ( ) ) { Reserved . set ( <STR_LIT> ) ; } } if ( needsFP ( MF ) ) Reserved . set ( <STR_LIT> ) ; return Reserved


<s> if ( VT . getSizeInBits ( ) . getKnownMinSize ( ) > <STR_LIT> ) return SDValue ( ) ; EVT ContainerVT = VT ; if ( ContainerVT . isInteger ( ) ) ContainerVT = getSVEContainerType ( ContainerVT ) ; SDVTList VTs = DAG . getVTList ( ContainerVT , <STR_LIT> ) ; SDValue Ops [ ] = { N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , DAG . getValueType ( VT ) } ; SDValue Load = DAG . getNode ( Opc , DL , VTs , Ops ) ; SDValue LoadChain = SDValue ( Load . getNode ( ) , <NUM_LIT> ) ; if ( ContainerVT . isInteger ( ) && ( VT != ContainerVT ) ) Load = DAG . getNode ( <STR_LIT> , DL , VT , Load . getValue ( <NUM_LIT> ) ) ; return DAG . getMergeValues ( { Load , LoadChain


<s> case MULT : if ( index ) return <NUM_LIT> ; index = XEXP ( op , <NUM_LIT> ) ; scale_rtx = XEXP ( op , <NUM_LIT> ) ; break ; case UNSPEC : if ( XINT ( op , <NUM_LIT> ) == UNSPEC_TP && TARGET_TLS_DIRECT_SEG_REFS && seg == SEG_DEFAULT ) seg = TARGET_64BIT ? SEG_FS : SEG_GS ; else return <NUM_LIT> ; break ; case REG : case SUBREG : if ( ! base ) base = op ; else if ( ! index ) index = op ; else return <NUM_LIT> ; break ; case CONST : case CONST_INT : case SYMBOL_REF : case LABEL_REF : if ( disp ) return <NUM_LIT> ; disp = op ; break ; default : return <NUM_LIT> ; } } } else if ( GET_CODE ( addr ) == MULT ) { index = XEXP ( addr , <NUM_LIT> ) ; scale_rtx = XEXP ( addr , <NUM_LIT> ) ; } else if ( GET_CODE ( addr ) == ASHIFT ) { rtx tmp ; index = XEXP ( addr , <NUM_LIT> ) ; tmp = XEXP ( addr , <NUM_LIT> ) ; if ( GET_CODE ( tmp ) != CONST_INT ) return <NUM_LIT> ; scale = INTVAL ( tmp ) ; if ( ( unsigned HOST_WIDE_INT ) scale > <NUM_LIT> ) return <NUM_LIT> ; scale = <NUM_LIT> << scale ; retval = - <NUM_LIT> ; } else disp = addr ; if ( scale_rtx ) { if ( GET_CODE ( scale_rtx ) != CONST_INT ) return <NUM_LIT> ; scale = INTVAL ( scale_rtx ) ; } base_reg = base && GET_CODE ( base ) == SUBREG ? SUBREG_REG ( base ) : base ; index_reg = index && GET_CODE ( index ) == SUBREG ? SUBREG_REG ( index ) : index ; if ( base_reg && index_reg && scale == <NUM_LIT> && ( index_reg == arg_pointer_rtx || index_reg == frame_pointer_rtx || ( REG_P ( index_reg ) && REGNO ( index_reg ) == STACK_POINTER_REGNUM ) ) ) { rtx tmp ; tmp = base , base = index , index = tmp ; tmp = base_reg , base_reg = index_reg , index_reg = tmp ; } if ( ( base_reg == hard_frame_pointer_rtx || base_reg == frame_pointer_rtx || base_reg == arg_pointer_rtx ) && !


<s> static int last_insn_address = <NUM_LIT> ; const int uid = INSN_UID ( insn ) ; if ( TARGET_ADDRESSES ) { fprintf ( asm_out_file , <STR_LIT> , INSN_ADDRESSES ( uid ) , INSN_ADDRESSES ( uid ) - last_insn_address ) ; last_insn_address = INSN_ADDRESSES ( uid


<s> targetm . target_option . pragma_parse = arm_pragma_target_parse ; targetm . resolve_overloaded_builtin =


<s> void LLVMInitialize<ISA_LIT>AsmPrinter ( ) { RegisterAsmPrinter < <ISA_LIT>AsmPrinter > X (


<s> bool isGOTPLDpc ( MachineInstr & Instr ) { if ( Instr . getOpcode ( ) != <STR_LIT> ) return false ; const MachineOperand & LoadedAddressReg = Instr . getOperand


<s> const unsigned Num = Desc . getNumImplicitUses ( ) ; for ( unsigned i = <NUM_LIT> ; i < Num ; ++ i ) { unsigned Reg = Desc . ImplicitUses [ i ] ; switch ( Reg ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return Reg ; default : break ; } } return


<s> case V8HImode : return CODE_FOR_aarch64_reload_movcpv8hidi ; case V2SImode : return CODE_FOR_aarch64_reload_movcpv2sidi ; case V4SImode : return CODE_FOR_aarch64_reload_movcpv4sidi ; case V2DImode : return CODE_FOR_aarch64_reload_movcpv2didi ; case V2DFmode : return CODE_FOR_aarch64_reload_movcpv2dfdi ; default : gcc_unreachable (


<s> bool <ISA_LIT>TargetMachine :: addInstSelector ( PassManagerBase & PM ) { PM . add ( create<ISA_LIT>ISelDag


<s> const char * getPassName ( ) const override { return


<s> inline bool <ISA_LIT>DAGToDAGISel :: SelectAnyImm0 ( SDValue & N , SDValue & R ) { return SelectAnyImmediate ( N , R , <NUM_LIT>


<s> SDValue V2 = SVOp -> getOperand ( <NUM_LIT> ) ; DebugLoc dl = SVOp -> getDebugLoc ( ) ; MVT VT = SVOp -> getValueType ( <NUM_LIT> ) . getSimpleVT ( ) ; MVT EltVT = VT . getVectorElementType ( ) ; unsigned NumElems = VT . getVectorNumElements ( ) ; if ( ! Subtarget -> hasSSE41 ( ) || EltVT == <STR_LIT> ) return SDValue ( ) ; if ( ! Subtarget -> hasInt256 ( ) && VT == <STR_LIT> ) return SDValue ( ) ; unsigned MaskValue = <NUM_LIT> ; unsigned NumLanes = ( NumElems - <NUM_LIT> ) / <NUM_LIT> + <NUM_LIT> ; unsigned NumElemsInLane = NumElems / NumLanes ; for ( unsigned i = <NUM_LIT> ; i < NumElemsInLane ; ++ i ) { int SndLaneEltIdx = ( NumLanes == <NUM_LIT> ) ? SVOp -> getMaskElt


<s> fprintf ( file , <STR_LIT> ) ; tree size = DECL_SIZE_UNIT ( decl ) ; nvptx_assemble_decl_begin ( file , name , section_for_decl ( decl ) , TREE_TYPE ( decl ) , size ? tree_to_shwi ( size ) : <NUM_LIT> ,


<s> SmallVector < BasicBlock * , <NUM_LIT> > ReturningBlocks ; SmallVector < BasicBlock * , <NUM_LIT> > UnreachableBlocks ; BasicBlock * DummyReturnBB = nullptr ; bool InsertExport = false ; for ( BasicBlock * BB : PDT . getRoots ( ) ) { if ( isa < ReturnInst > ( BB -> getTerminator ( ) ) ) { if ( ! isUniformlyReached ( DA , * BB ) ) ReturningBlocks . push_back ( BB ) ; } else if ( isa < UnreachableInst > ( BB -> getTerminator ( ) ) ) { if ( ! isUniformlyReached ( DA , * BB ) ) UnreachableBlocks . push_back ( BB ) ; } else if ( BranchInst * BI = dyn_cast < BranchInst > ( BB -> getTerminator ( ) ) ) { ConstantInt * BoolTrue = ConstantInt :: getTrue ( F . getContext ( ) ) ; if ( DummyReturnBB == nullptr ) { DummyReturnBB = BasicBlock :: Create ( F . getContext ( ) , <STR_LIT> , & F ) ; Type * RetTy = F . getReturnType ( ) ; Value * RetVal = RetTy -> isVoidTy ( ) ? nullptr : UndefValue :: get ( RetTy ) ; if ( F . getCallingConv ( ) == CallingConv :: <ISA_LIT>_PS && RetTy -> isVoidTy ( ) ) { InsertExport = true ; } ReturnInst :: Create ( F . getContext ( ) , RetVal , DummyReturnBB ) ; ReturningBlocks . push_back ( DummyReturnBB ) ; } if ( BI -> isUnconditional ( ) ) { BasicBlock * LoopHeaderBB = BI -> getSuccessor ( <NUM_LIT> ) ; BI -> eraseFromParent ( ) ; BranchInst :: Create ( LoopHeaderBB , DummyReturnBB , BoolTrue , BB ) ; } else { BasicBlock * TransitionBB = BB -> splitBasicBlock ( BI , <STR_LIT> ) ; BB -> getTerminator ( ) -> eraseFromParent ( ) ; BranchInst :: Create ( TransitionBB , DummyReturnBB , BoolTrue , BB ) ; } } } if ( ! UnreachableBlocks . empty ( ) ) { BasicBlock * UnreachableBlock = nullptr ; if ( UnreachableBlocks . size ( ) == <NUM_LIT> ) { UnreachableBlock = UnreachableBlocks . front ( ) ; }


<s> return ( int32x4_t ) __builtin_neon_vsublsv4hi (


<s> treg = avr_hregs_split_reg ( & set ) ; if ( treg < <NUM_LIT> ) treg = AVR_TMP_REGNO ; cfun -> machine -> gasisr . regno = treg ; cfun -> machine -> stack_usage += <NUM_LIT> + ( treg != AVR_TMP_REGNO ) ; emit_insn ( gen_gasisr ( GEN_INT ( GASISR_Prologue ) , GEN_INT ( treg ) ) ) ; } else { emit_push_byte ( AVR_ZERO_REGNO , true ) ; emit_push_byte ( AVR_TMP_REGNO , true ) ; emit_push_sfr ( sreg_rtx , false , false , AVR_TMP_REGNO ) ; emit_move_insn ( zero_reg_rtx , const0_rtx ) ; emit_use ( zero_reg_rtx ) ; } if ( AVR_HAVE_RAMPD ) emit_push_sfr ( rampd_rtx , false , true , treg ) ; if ( AVR_HAVE_RAMPX && TEST_HARD_REG_BIT ( set , REG_X ) && TEST_HARD_REG_BIT ( set


<s> return ( vector signed int ) __builtin_altivec_vcmpgefp ( ( vector float ) a1 , ( vector float


<s> cfun -> machine -> seh -> after_prologue = true ; fputs ( <STR_LIT> ,


<s> if ( RB0 == <STR_LIT> || RB1 == <STR_LIT> ) return <STR_LIT> ; return regBankUnion ( RB0 ,


<s> case <STR_LIT> : return ELF :: R_<ISA_LIT>_TLS_GD_HI20 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_JAL ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_BRANCH ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_RVC_JUMP ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_RVC_BRANCH ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_CALL ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_CALL_PLT ; } } switch ( Kind ) { default : llvm_unreachable ( <STR_LIT> ) ; case FK_Data_4 : return ELF :: R_<ISA_LIT>_32 ; case FK_Data_8 : return ELF :: R_<ISA_LIT>_64 ; case FK_Data_Add_1 : return ELF :: R_<ISA_LIT>_ADD8 ; case FK_Data_Add_2 : return ELF :: R_<ISA_LIT>_ADD16 ; case FK_Data_Add_4 : return ELF :: R_<ISA_LIT>_ADD32 ; case FK_Data_Add_8 : return ELF :: R_<ISA_LIT>_ADD64 ; case FK_Data_Add_6b : return ELF :: R_<ISA_LIT>_SET6 ; case FK_Data_Sub_1 : return ELF :: R_<ISA_LIT>_SUB8 ; case FK_Data_Sub_2 : return ELF :: R_<ISA_LIT>_SUB16 ; case FK_Data_Sub_4 : return ELF :: R_<ISA_LIT>_SUB32 ; case FK_Data_Sub_8 : return ELF :: R_<ISA_LIT>_SUB64 ; case FK_Data_Sub_6b : return ELF :: R_<ISA_LIT>_SUB6 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_HI20 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_LO12_I ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_LO12_S ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_TPREL_HI20 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_TPREL_LO12_I ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_TPREL_LO12_S ; case <STR_LIT> : return ELF


<s> lane = lane >= half_elts ? lane - half_elts : lane + half_elts ; XVECEXP ( unspec , <NUM_LIT> , <NUM_LIT> ) = GEN_INT ( lane ) ; INSN_CODE ( insn ) = - <NUM_LIT> ; df_insn_rescan ( insn ) ; if ( dump_file ) fprintf ( dump_file , <STR_LIT>


<s> bool <ISA_LIT>FastISel :: <ISA_LIT>SelectStore ( const Instruction * I ) { const StoreInst * S = cast < StoreInst > ( I ) ; if ( S -> isAtomic ( ) ) return false ; const Value * Val = S -> getValueOperand ( ) ; const Value * Ptr = S -> getPointerOperand ( ) ; MVT VT ; if ( ! isTypeLegal ( Val -> getType ( ) , VT , true ) ) return false ; unsigned Alignment = S -> getAlignment ( ) ; unsigned ABIAlignment = DL . getABITypeAlignment ( Val -> getType ( ) ) ; if ( Alignment == <NUM_LIT> ) Alignment = ABIAlignment ; bool Aligned =


<s> setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Promote ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; for ( MVT VT : { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ) { for ( unsigned Op = <NUM_LIT> ; Op < <STR_LIT> ; ++ Op ) { switch ( Op ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : break ; case <STR_LIT> : setOperationAction ( Op , VT , Custom ) ; break ; default : setOperationAction ( Op , VT , Expand ) ; break ; } } } for ( MVT Vec64 : { <STR_LIT> , <STR_LIT> } ) { setOperationAction ( <STR_LIT> , Vec64 , Promote ) ; AddPromotedToType ( <STR_LIT> , Vec64 , <STR_LIT> ) ; setOperationAction ( <STR_LIT> , Vec64 , Promote ) ; AddPromotedToType ( <STR_LIT> , Vec64 , <STR_LIT> ) ; setOperationAction ( <STR_LIT> , Vec64 , Promote ) ; AddPromotedToType ( <STR_LIT> , Vec64 , <STR_LIT> ) ; setOperationAction ( <STR_LIT> , Vec64 , Promote ) ; AddPromotedToType ( <STR_LIT> , Vec64 , <STR_LIT> ) ; } setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; if ( getSubtarget ( ) -> hasFlatAddressSpace ( ) ) { setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom


<s> bool writeNopData ( uint64_t Count , MCObjectWriter * OW ) const { if ( ( Count % <NUM_LIT> ) != <NUM_LIT> ) return false ; for ( uint64_t i = <NUM_LIT> ; i < Count ; i += <NUM_LIT> ) OW -> Write32


<s> if ( Signed && isPow2Splat ( Op . getOperand ( <NUM_LIT> ) , SplatVal , Negated ) ) { EVT ContainerVT = getContainerForFixedLengthVector ( DAG , VT ) ; SDValue Op1 = convertToScalableVector ( DAG , ContainerVT , Op . getOperand ( <NUM_LIT> ) ) ; SDValue Op2 = DAG . getTargetConstant ( Log2_64 ( SplatVal ) , dl , <STR_LIT> ) ; SDValue Pg = getPredicateForFixedLengthVector ( DAG , dl , VT ) ; SDValue Res = DAG . getNode ( <STR_LIT> , dl , ContainerVT , Pg , Op1 , Op2 ) ; if ( Negated ) Res = DAG . getNode ( <STR_LIT> , dl , VT , DAG . getConstant ( <NUM_LIT> , dl , VT ) , Res ) ; return convertFromScalableVector ( DAG , VT , Res ) ; } if ( EltVT == <STR_LIT> || EltVT == <STR_LIT> ) return LowerToPredicatedOp ( Op , DAG , PredOpcode ) ; EVT ContainerVT = getContainerForFixedLengthVector ( DAG , VT ) ; EVT HalfVT = VT . getHalfNumVectorElementsVT ( * DAG . getContext ( ) ) ; EVT FixedWidenedVT = HalfVT . widenIntegerVectorElementType ( * DAG . getContext ( ) ) ; EVT ScalableWidenedVT = getContainerForFixedLengthVector ( DAG , FixedWidenedVT ) ; EVT WidenedVT = VT . widenIntegerVectorElementType ( * DAG . getContext ( ) ) ; if ( DAG . getTargetLoweringInfo ( ) . isTypeLegal ( WidenedVT ) ) { unsigned ExtendOpcode = Signed ? <STR_LIT> : <STR_LIT> ; SDValue Op0 = DAG . getNode ( ExtendOpcode , dl , WidenedVT , Op . getOperand ( <NUM_LIT> ) ) ; SDValue Op1 = DAG . getNode ( ExtendOpcode , dl , WidenedVT , Op . getOperand ( <NUM_LIT> ) ) ; SDValue Div = DAG . getNode ( Op . getOpcode ( ) , dl , WidenedVT , Op0 , Op1 ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Div ) ; } SDValue Op0 = convertToScalableVector ( DAG , ContainerVT , Op . getOperand ( <NUM_LIT> ) ) ; SDValue Op1 = convertToScalableVector ( DAG , ContainerVT , Op . getOperand ( <NUM_LIT> ) ) ; unsigned UnpkLo = Signed ? <STR_LIT> : <STR_LIT> ; unsigned UnpkHi = Signed ? <STR_LIT> : <STR_LIT> ; SDValue Op0Lo = DAG . getNode ( UnpkLo , dl , ScalableWidenedVT , Op0 ) ; SDValue Op1Lo = DAG . getNode ( UnpkLo , dl , ScalableWidenedVT , Op1 ) ; SDValue Op0Hi = DAG . getNode ( UnpkHi , dl , ScalableWidenedVT , Op0 ) ; SDValue Op1Hi = DAG . getNode ( UnpkHi , dl , ScalableWidenedVT , Op1 ) ; Op0Lo = convertFromScalableVector ( DAG , FixedWidenedVT , Op0Lo ) ; Op1Lo = convertFromScalableVector ( DAG , FixedWidenedVT , Op1Lo


<s> bool SelectAddrImm ( SDValue N , SDValue & Disp , SDValue


<s> static bool FoldMaskedShiftToScaledMask ( SelectionDAG & DAG , SDValue N , uint64_t Mask , SDValue Shift , SDValue X , <ISA_LIT>ISelAddressMode & AM ) { if ( Shift . getOpcode ( ) != <STR_LIT> || ! isa < ConstantSDNode > ( Shift . getOperand ( <NUM_LIT> ) ) ) return true ; if ( ! N . hasOneUse ( ) || ! Shift . hasOneUse ( ) ) return true ; unsigned ShiftAmt = Shift . getConstantOperandVal ( <NUM_LIT> ) ; if ( ShiftAmt != <NUM_LIT> && ShiftAmt != <NUM_LIT> && ShiftAmt != <NUM_LIT> ) return true ; MVT VT = N . getSimpleValueType ( ) ; SDLoc DL ( N ) ; SDValue NewMask = DAG . getConstant ( Mask >> ShiftAmt , DL , VT ) ; SDValue NewAnd = DAG . getNode ( <STR_LIT> , DL , VT , X , NewMask ) ; SDValue NewShift = DAG . getNode ( <STR_LIT> , DL , VT , NewAnd , Shift . getOperand ( <NUM_LIT> ) ) ; InsertDAGNode ( DAG , N , NewMask ) ; InsertDAGNode ( DAG , N , NewAnd ) ; InsertDAGNode ( DAG , N , NewShift ) ; DAG . ReplaceAllUsesWith (


<s> virtual unsigned getJumpTableEncoding ( )


<s> rtx insn_set ; rtx dep_set ; int timings ; if ( ! TARGET_AM33 ) return <NUM_LIT> ; insn_set = single_set ( insn ) ; if ( ! insn_set ) return cost ; dep_set = single_set ( dep ) ; if ( ! dep_set ) return cost ; if ( mn10300_tune_cpu == PROCESSOR_AM34 && set_is_load_p ( dep_set ) && set_is_store_p ( insn_set ) ) cost += <NUM_LIT> ; else if ( mn10300_tune_cpu == PROCESSOR_AM34 && ! set_is_store_p ( insn_set ) && ! JUMP_P ( insn ) && GET_MODE_CLASS ( GET_MODE ( SET_SRC ( dep_set ) ) ) == MODE_FLOAT && GET_MODE_CLASS ( GET_MODE ( SET_SRC ( insn_set ) ) ) == MODE_FLOAT ) cost += <NUM_LIT> ; if ( ! TARGET_AM33_2 )


<s> rtx * loc = * iter ; if ( MEM_P ( * loc ) ) { loongarch_rewrite_small_data_1 ( & XEXP ( * loc , <NUM_LIT> ) ) ; iter . skip_subrtxes (


<s> if ( BitWidth <= <NUM_LIT> ) return & <STR_LIT> ; if ( BitWidth <= <NUM_LIT> ) return & <STR_LIT> ; if ( BitWidth <= <NUM_LIT> ) return & <STR_LIT> ; if ( BitWidth <= <NUM_LIT> ) return & <STR_LIT> ; if ( BitWidth <= <NUM_LIT> ) return & <STR_LIT> ; if ( BitWidth <= <NUM_LIT>


<s> DebugLoc dl = Op . getDebugLoc ( ) ; unsigned Depth = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; EVT PtrVT = DAG . getTargetLoweringInfo ( ) . getPointerTy ( ) ; bool is<ISA_LIT>64 = PtrVT == <STR_LIT> ; MachineFunction & MF = DAG . getMachineFunction ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; MFI -> setFrameAddressIsTaken ( true ) ; bool is31 = ( DisableFramePointerElim ( MF ) || MFI -> hasVarSizedObjects ( ) ) && MFI -> getStackSize ( ) && ! MF . getFunction ( ) -> hasFnAttr ( Attribute :: Naked ) ; unsigned FrameReg = is<ISA_LIT>64 ? ( is31 ? <STR_LIT> : <STR_LIT> ) : ( is31 ? <STR_LIT> : <STR_LIT> ) ; SDValue FrameAddr = DAG . getCopyFromReg ( DAG . getEntryNode ( ) , dl , FrameReg , PtrVT ) ; while ( Depth -- ) FrameAddr = DAG . getLoad ( Op . getValueType ( ) , dl , DAG . getEntryNode ( ) , FrameAddr , MachinePointerInfo ( ) , false , false , false , <NUM_LIT> ) ; return


<s> default : if ( HadParens ) getLexer ( ) . UnLex ( LParen ) ; return MatchOperand_NoMatch ; case AsmToken :: Identifier : StringRef Name = getLexer ( ) . getTok ( ) . getIdentifier ( ) ; Register RegNo ; matchRegisterNameHelper ( isRV32E ( ) , RegNo , Name ) ; if ( RegNo == <STR_LIT> ) RegNo = <STR_LIT> ; if ( RegNo == <STR_LIT> ) { if ( HadParens ) getLexer ( ) . UnLex ( LParen ) ; return MatchOperand_NoMatch ; } if ( HadParens ) Operands . push_back ( <ISA_LIT>Operand :: createToken ( <STR_LIT> , FirstS , isRV64 ( )


<s> assert ( ( N -> getOpcode ( ) == <STR_LIT> || N -> getOpcode ( ) == <STR_LIT> ) && <STR_LIT> ) ; SDValue WideRes ; if ( isLogicOp ( N -> getOperand ( <NUM_LIT> ) . getOpcode ( ) ) && N -> getOperand ( <NUM_LIT> ) . getValueType ( ) == <STR_LIT> && N -> getOpcode ( ) == <STR_LIT> ) WideRes = computeLogicOpInGPR ( N -> getOperand ( <NUM_LIT> ) ) ; else if ( N -> getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> ) return nullptr ; else WideRes = getSETCCInGPR ( N -> getOperand ( <NUM_LIT> ) , N -> getOpcode ( ) == <STR_LIT> ? SetccInGPROpts :: SExtOrig : SetccInGPROpts :: ZExtOrig ) ; if ( ! WideRes ) return nullptr ; SDLoc dl ( N ) ; bool Input32Bit = WideRes . getValueType ( ) == <STR_LIT> ; bool Output32Bit = N -> getValueType ( <NUM_LIT> ) == <STR_LIT> ; NumSextSetcc += N -> getOpcode ( ) == <STR_LIT> ? <NUM_LIT> : <NUM_LIT> ; NumZextSetcc += N -> getOpcode ( ) == <STR_LIT> ? <NUM_LIT> : <NUM_LIT> ; SDValue ConvOp = WideRes ; if ( Input32Bit != Output32Bit ) ConvOp = addExtOrTrunc ( WideRes , Input32Bit ? ExtOrTruncConversion :: Ext : ExtOrTruncConversion :: Trunc ) ; return ConvOp . getNode


<s> bool hasMulI24 ( ) const { return HasMulI24


<s> return ( __m512d ) __builtin_ia32_vfmaddpd512_mask3 ( ( __v8df ) __A , ( __v8df ) __B , (


<s> StringRef getUnifiedFormatName ( unsigned Id ) { return isValidUnifiedFormat ( Id ) ? UfmtSymbolic


<s> PredicatedMI * Divergent = Block . getDivergent ( ) ; if ( isVCTP ( Divergent -> MI ) ) { uint64_t Size = get<ISA_LIT>VPTBlockMask ( Block . size ( ) - <NUM_LIT> ) ; Block . getVPST ( ) -> getOperand ( <NUM_LIT> ) . setImm ( Size ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; } else if ( Block . IsOnlyPredicatedOn ( LoLoop . VCTP ) ) { for ( auto I = ++ MachineBasicBlock :: iterator ( Block . getVPST ( ) ) , E = ++ MachineBasicBlock :: iterator ( Divergent -> MI ) ; I != E ; ++ I ) RemovePredicate ( & * I ) ; unsigned Size = <NUM_LIT> ; auto E = MachineBasicBlock :: reverse_iterator ( Divergent -> MI ) ; auto I = MachineBasicBlock :: reverse_iterator ( Insts . back ( ) . MI ) ; MachineInstr * InsertAt = nullptr ; while ( I != E ) { InsertAt = &


<s> setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand


<s> SmallVector < T * , N > list ; for ( BasicBlock :: iterator II = ( * BB ) -> begin ( ) ; II != ( * BB ) -> end ( ) ; II ++ ) if ( auto Intrin = dyn_cast < T > ( II ) ) list . push_back ( Intrin ) ; return


<s> if ( delta < <NUM_LIT> ) emit_insn ( gen_rtx_SET ( Pmode , this_rtx , gen_rtx_MINUS ( Pmode , this_rtx , shift ) ) ) ; else emit_insn ( gen_rtx_SET ( Pmode , this_rtx , gen_rtx_PLUS ( Pmode , this_rtx , shift ) ) ) ; } if ( mdelta % <NUM_LIT> != <NUM_LIT> ) { scratch_rtx = GEN_INT ( ( delta < <NUM_LIT> ? - <NUM_LIT> :

<NUM_LIT> ) * ( mdelta % <NUM_LIT> ) ) ;


<s> if ( ! Flags . isSRet ( ) || Flags . isInReg ( ) ) return false ; if ( Subtarget . getTargetTriple ( ) . isOSMSVCRT ( ) ) return false ; if ( Subtarget . isTargetMCU ( ) ) return false ; return


<s> } else if ( GET_CODE ( x ) == PLUS && REG_P ( XEXP ( x , <NUM_LIT> ) ) && CONST_INT_P ( XEXP ( x , <NUM_LIT> ) ) ) fprintf ( file , HOST_WIDE_INT_PRINT_DEC <STR_LIT> , INTVAL ( XEXP ( x , <NUM_LIT> ) ) , reg_names [ REGNO ( XEXP ( x , <NUM_LIT> ) ) ] ) ; else if ( GET_CODE ( x ) == LO_SUM && REG_P ( XEXP ( x , <NUM_LIT> ) ) && CONSTANT_P ( XEXP ( x , <NUM_LIT> ) ) ) { fprintf ( file , <STR_LIT> ) ; output_addr_const ( file , XEXP ( x , <NUM_LIT> ) ) ; fprintf ( file , <STR_LIT> , reg_names [ REGNO ( XEXP ( x , <NUM_LIT> ) ) ] ) ; } else if ( GET_CODE ( x ) == LO_SUM && REG_P ( XEXP ( x , <NUM_LIT> ) ) && CONSTANT_P ( XEXP ( x , <NUM_LIT> ) ) ) { output_addr_const ( file , XEXP ( x , <NUM_LIT> ) ) ; fprintf ( file , <STR_LIT> , reg_names [ REGNO ( XEXP ( x , <NUM_LIT> ) ) ] ) ; } else if ( toc_relative_expr_p ( x , false , & tocrel_base_oac , & tocrel_offset_oac ) ) { output_addr_const ( file , CONST_CAST_RTX ( tocrel_base_oac ) ) ; if ( GET_CODE ( x ) == LO_SUM ) fprintf ( file , <STR_LIT> , reg_names [ REGNO ( XEXP ( x , <NUM_LIT> ) ) ] ) ; else fprintf ( file , <STR_LIT> , reg_names [ REGNO ( XVECEXP ( tocrel_base_oac , <NUM_LIT> , <NUM_LIT>


<s> memset ( rws_sum , <NUM_LIT> , sizeof ( rws_sum


<s> return getImm3 ( insn ) << <NUM_LIT> | getImm2 (


<s> setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; if ( ! TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . hasCT ( ) ) { setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; } setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Promote ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Promote ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom


<s> return COSTS_N_INSNS ( ( GET_MODE_SIZE ( mode ) +


<s> unsigned isExtendable = ( F >> <STR_LIT> ) & <STR_LIT> ; if ( ! isExtendable ) return false ; short ExtOpNum = getCExtOpNum ( MI ) ; const MachineOperand & MO = MI -> getOperand ( ExtOpNum ) ; if ( MO . getTargetFlags ( ) && <STR_LIT> ) return true ; if ( MO . isMBB ( ) ) return false ; if ( MO . isGlobal ( ) || MO . isSymbol ( ) || MO . isBlockAddress ( ) || MO . isJTI ( ) || MO . isCPI ( ) ) return true ; assert ( MO . isImm


<s> } } if ( which == AARCH64_CHECK_MOV ) { unsigned int i ; for ( i = <NUM_LIT> ; i < <NUM_LIT> ; i += <NUM_LIT> ) { unsigned char byte = ( val64 >> i ) & <NUM_LIT> ; if ( byte != <NUM_LIT> && byte != <NUM_LIT> ) break ; } if ( i == <NUM_LIT> ) { if ( info ) * info = simd_immediate_info ( DImode , val64


<s> llvm_unreachable ( <STR_LIT> ) ; return


<s> return ( __m64 ) __builtin_ia32_punpckhbw ( ( __v8qi


<s> void <ISA_LIT>InstPrinter :: printU16ImmOperand ( const MCInst * MI , unsigned OpNo , raw_ostream & O ) { if ( MI -> getOperand ( OpNo ) . isImm ( ) ) O << ( unsigned short ) MI -> getOperand ( OpNo ) . getImm ( ) ; else printOperand ( MI , OpNo


<s> EmitInstruction ( Out , MCInstBuilder ( <STR_LIT> ) . addReg ( ShadowRegI64 ) . addReg ( ShadowRegI64 ) . addImm ( <NUM_LIT> ) ) ; { MCInst Inst ; switch ( AccessSize ) { default : llvm_unreachable ( <STR_LIT> ) ; case <NUM_LIT> : Inst . setOpcode ( <STR_LIT> ) ; break ; case <NUM_LIT> : Inst . setOpcode ( <STR_LIT> ) ; break ; } const MCExpr * Disp = MCConstantExpr :: create ( kShadowOffset , Ctx ) ; std :: unique_ptr < <ISA_LIT>Operand > Op ( <STR_LIT> ( getPointerWidth ( ) , <NUM_LIT> , Disp , ShadowRegI64 , <NUM_LIT> , <NUM_LIT> , SMLoc ( ) , SMLoc ( ) ) ) ; Op -> addMemOperands ( Inst , <NUM_LIT> ) ; Inst . addOperand ( MCOperand :: createImm ( <NUM_LIT> ) ) ; EmitInstruction ( Out , Inst


<s> void <ISA_LIT>AsmPrinter :: EmitFunctionBodyEnd ( ) { if ( OutStreamer . hasRawTextSupport ( ) ) { OutStreamer . EmitRawText ( StringRef ( <STR_LIT> )


<s> if ( VT == <STR_LIT> ) return false ; } } if ( FrameIndexSDNode * FIN = dyn_cast < FrameIndexSDNode > ( Addr ) ) { Base = CurDAG -> getTargetFrameIndex ( FIN -> getIndex ( ) , ValTy ) ; Offset = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , ValTy ) ; return true ; } if ( Addr . getOpcode ( ) == <STR_LIT> ) { Base = Addr . getOperand ( <NUM_LIT> ) ; Offset = Addr . getOperand ( <NUM_LIT> ) ; return true ; } if ( TM . getRelocationModel ( ) != Reloc :: PIC_ ) { if ( ( Addr . getOpcode ( ) == <STR_LIT> || Addr . getOpcode ( ) == <STR_LIT> ) ) return false ; } if ( CurDAG -> isBaseWithConstantOffset ( Addr ) ) { ConstantSDNode * CN = dyn_cast < ConstantSDNode > ( Addr . getOperand ( <NUM_LIT> ) ) ; if ( isInt < <NUM_LIT> > ( CN -> getSExtValue ( ) ) ) { if ( FrameIndexSDNode * FIN = dyn_cast < FrameIndexSDNode > ( Addr . getOperand ( <NUM_LIT> )

) ) Base = CurDAG -> getTargetFrameIndex ( FIN -> getIndex ( ) , ValTy ) ;


<s> <ISA_LIT>MCAsmInfoMicrosoft :: <ISA_LIT>MCAsmInfoMicrosoft ( const Triple & Triple ) { if ( Triple . getArch ( ) == Triple :: x86_64 ) { PrivateGlobalPrefix = <STR_LIT> ; PrivateLabelPrefix = <STR_LIT> ; PointerSize = <NUM_LIT> ; WinEHEncodingType = WinEH :: EncodingType :: Itanium ; ExceptionsType = ExceptionHandling :: WinEH ; } AssemblerDialect = AsmWriterFlavor ; TextAlignFillValue =


<s> } else if ( const auto * CI = dyn_cast < ConstantInt > ( BI -> getCondition ( ) ) ) { uint64_t Imm = CI -> getZExtValue ( ) ; MachineBasicBlock * Target = ( Imm == <NUM_LIT> ) ? FBB : TBB ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) ) . addMBB ( Target ) ; if ( FuncInfo . BPI ) { auto BranchProbability = FuncInfo . BPI -> getEdgeProbability ( BI -> getParent ( ) , Target -> getBasicBlock ( ) ) ; FuncInfo . MBB -> addSuccessor ( Target , BranchProbability ) ; } else FuncInfo . MBB -> addSuccessorWithoutProb ( Target ) ; return true ; } else { <STR_LIT> CC = <STR_LIT> ; if ( foldXALUIntrinsic ( CC , I , BI -> getCondition ( ) ) ) { Register CondReg = getRegForValue ( BI -> getCondition ( ) ) ; if ( ! CondReg ) return false ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) ) . addImm ( CC ) . addMBB ( TBB ) ; finishCondBranch ( BI -> getParent ( ) , TBB , FBB ) ; return true ; } } Register CondReg = getRegForValue ( BI -> getCondition ( ) ) ; if ( CondReg == <NUM_LIT> ) return false ; unsigned Opcode = <STR_LIT> ; if ( FuncInfo . MBB -> isLayoutSuccessor ( TBB ) ) { std :: swap ( TBB , FBB ) ; Opcode = <STR_LIT> ; } const MCInstrDesc & II = TII . get ( Opcode ) ; Register ConstrainedCondReg = constrainOperandRegClass ( II , CondReg , II . getNumDefs ( ) ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , II ) . addReg ( ConstrainedCondReg ) . addImm ( <NUM_LIT> ) . addMBB ( TBB ) ; finishCondBranch ( BI -> getParent ( ) , TBB


<s> assert ( Cond . empty ( ) && ! FBB && TBB && <STR_LIT> ) ; BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addMBB ( TBB ) ; return


<s> unsigned Reg = CSI [ i ] . getReg ( ) ; unsigned RegNum = TM . getRegisterInfo ( ) -> getEncodingValue ( Reg ) ; CPUBitmask |= ( <NUM_LIT> << RegNum ) ; } FPUTopSavedRegOff = FPUBitmask ? ( HasAFGR64Reg ? - AFGR64RegSize : - FGR32RegSize ) : <NUM_LIT> ; CPUTopSavedRegOff = CPUBitmask ? - CSFPRegsSize - CPURegSize : <NUM_LIT> ; O << <STR_LIT> ; printHex32 ( CPUBitmask , O ) ; O << ',' << CPUTopSavedRegOff << '\n' ; O << <STR_LIT> ; printHex32 ( FPUBitmask , O ) ; O << <STR_LIT> << FPUTopSavedRegOff


<s> return ( int64x2_t ) __builtin_neon_vaddlsv2si (


<s> SMLoc getLoc ( ) const { return getParser ( ) . getTok ( ) .


<s> const char * <ISA_LIT>Subtarget :: getBZeroEntry ( ) const { return <STR_LIT>


<s> O << <STR_LIT> ; printU4ImmOperand ( MI , OpNo ,


<s> return __aarch64_vset_lane_any ( * __src , __vec ,


<s> bool <ISA_LIT>TargetLowering :: allowsMisalignedMemoryAccesses ( EVT , unsigned , Align , MachineMemOperand :: Flags , bool * Fast ) const { if ( Fast ) * Fast


<s> static int already_reported_p [ ARRAY_SIZE ( cgen_intrinsics ) ] ; if ( already_reported_p [ intrinsic ] ) return ; if ( mep_intrinsic_insn [ intrinsic ] < <NUM_LIT> ) error ( <STR_LIT> , cgen_intrinsics [ intrinsic ] ) ; else if ( CGEN_CURRENT_GROUP == GROUP_VLIW ) error ( <STR_LIT> , cgen_intrinsics [ intrinsic ] ) ; else error ( <STR_LIT> , cgen_intrinsics [ intrinsic ] ) ; already_reported_p [ intrinsic


<s> case <STR_LIT> : case <STR_LIT> : Valid = ( isUInt < <NUM_LIT> > ( v ) || v == - <NUM_LIT> ) ; break ; case <STR_LIT> : case <STR_LIT> : Valid = isUInt < <NUM_LIT> > ( v ) ; break ; case <STR_LIT> : case <STR_LIT> : Valid = ( v == <NUM_LIT> ) ; break ; } if ( ! Valid ) return false ; } unsigned cmpReg1 , cmpOp2 = <NUM_LIT> ; cmpReg1 = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( secondReg ) { cmpOp2 = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( cmpReg1 == cmpOp2 ) return false ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; if ( secondReg && ! Register :: isPhysicalRegister ( cmpOp2 ) ) { MachineInstr * def = MRI


<s> bool <ISA_LIT>FastISel :: selectFPTrunc ( const Instruction * I ) { Value * V = I -> getOperand ( <NUM_LIT> ) ; if ( ! I -> getType ( ) -> isFloatTy ( ) || ! V -> getType ( ) -> isDoubleTy ( ) ) return false ; Register Op = getRegForValue ( V ) ; if ( Op == <NUM_LIT> ) return false ; Register ResultReg = createResultReg


<s> unsigned TrapID = Op . getOpcode ( ) == <STR_LIT> ? <ISA_LIT>Subtarget :: TrapIDLLVMDebugTrap : <ISA_LIT>Subtarget :: TrapIDLLVMTrap ; if ( Subtarget -> getTrapHandlerAbi ( ) == <ISA_LIT>Subtarget :: TrapHandlerAbiHsa && Subtarget -> isTrapHandlerEnabled ( ) ) { <ISA_LIT>MachineFunctionInfo * Info = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; unsigned UserSGPR = Info -> getQueuePtrUserSGPR ( ) ; assert ( UserSGPR != <STR_LIT> ) ; SDValue QueuePtr = CreateLiveInRegister ( DAG , & <STR_LIT> , UserSGPR , <STR_LIT> ) ; SDValue SGPR01 = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; SDValue ToReg = DAG . getCopyToReg ( Chain , SL , SGPR01 , QueuePtr , SDValue ( ) ) ; SDValue Ops [ ] =


<s> unsigned Reg = getReg ( Decoder , <STR_LIT> , RegNo ) ; Inst . addOperand ( MCOperand ::


<s> static void iq2000_setup_incoming_varargs ( CUMULATIVE_ARGS * cum , enum machine_mode mode ATTRIBUTE_UNUSED , tree type ATTRIBUTE_UNUSED , int * pretend_size , int no_rtl ) { unsigned int iq2000_off = ! cum -> last_arg_fp ; unsigned int iq2000_fp_off = cum -> last_arg_fp ; if ( ( cum -> arg_words < MAX_ARGS_IN_REGISTERS - iq2000_off ) ) { int iq2000_save_gp_regs = MAX_ARGS_IN_REGISTERS - cum -> arg_words - iq2000_off ; int iq2000_save_fp_regs = ( MAX_ARGS_IN_REGISTERS - cum -> fp_arg_words - iq2000_fp_off ) ; if ( iq2000_save_gp_regs < <NUM_LIT> ) iq2000_save_gp_regs = <NUM_LIT> ; if ( iq2000_save_fp_regs < <NUM_LIT> ) iq2000_save_fp_regs = <NUM_LIT> ; * pretend_size = ( ( iq2000_save_gp_regs * UNITS_PER_WORD ) + ( iq2000_save_fp_regs * UNITS_PER_FPREG ) ) ; if ( ! ( no_rtl ) ) { if ( cum -> arg_words < MAX_ARGS_IN_REGISTERS - iq2000_off ) { rtx ptr , mem ; ptr = plus_constant ( virtual_incoming_args_rtx , - ( iq2000_save_gp_regs * UNITS_PER_WORD ) ) ; mem = gen_rtx_MEM (


<s> SDLoc DL ( N ) ; auto * TrueC = dyn_cast < ConstantSDNode > ( LHS ) ; auto * FalseC = dyn_cast < ConstantSDNode > ( RHS ) ; if ( ! TrueC || ! FalseC ) return SDValue ( ) ; if ( ! DAG . getTargetLoweringInfo ( ) . isTypeLegal ( LHS . getValueType ( ) ) ) return SDValue ( ) ; bool NeedsCondInvert = false ; if ( TrueC -> getAPIntValue ( ) . ult ( FalseC -> getAPIntValue ( ) ) && ( Cond . getOpcode ( ) == <STR_LIT> || ( Cond . getOpcode ( ) == <STR_LIT> && isa < ConstantSDNode > ( Cond . getOperand ( <NUM_LIT> ) ) ) ) ) { NeedsCondInvert = true ; std :: swap ( TrueC , FalseC ) ; } if ( FalseC -> getAPIntValue ( ) == <NUM_LIT> && TrueC -> getAPIntValue ( ) . isPowerOf2 ( ) ) { if ( NeedsCondInvert ) Cond = DAG . getNode ( <STR_LIT> , DL , Cond . getValueType ( ) , Cond , DAG . getConstant ( <NUM_LIT> , DL , Cond . getValueType ( ) ) ) ; Cond = DAG . getNode ( <STR_LIT> , DL , LHS . getValueType ( ) , Cond ) ; unsigned ShAmt = TrueC -> getAPIntValue ( ) . logBase2 ( ) ; return DAG . getNode ( <STR_LIT> , DL , LHS . getValueType ( ) , Cond , DAG . getConstant ( ShAmt , DL , <STR_LIT> ) ) ; } if ( FalseC -> getAPIntValue ( ) + <NUM_LIT> == TrueC -> getAPIntValue ( ) ) { if ( NeedsCondInvert ) Cond = DAG . getNode ( <STR_LIT> , DL , Cond . getValueType ( ) , Cond , DAG . getConstant ( <NUM_LIT> , DL , Cond . getValueType ( ) ) ) ; Cond = DAG . getNode ( <STR_LIT> , DL , FalseC -> getValueType ( <NUM_LIT> ) , Cond ) ; return DAG . getNode ( <STR_LIT> , DL , Cond . getValueType ( ) , Cond , SDValue ( FalseC , <NUM_LIT> ) ) ; } if ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT> || N -> getValueType ( <NUM_LIT> ) == <STR_LIT> ) { uint64_t Diff = TrueC -> getZExtValue ( ) - FalseC -> getZExtValue ( ) ; if ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT> ) Diff = ( unsigned ) Diff ; bool isFastMultiplier = false ; if ( Diff < <NUM_LIT> ) { switch ( ( unsigned char ) Diff ) { default : break ; case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : isFastMultiplier = true ; break ; } } if ( isFastMultiplier ) { APInt Diff = TrueC -> getAPIntValue ( ) -


<s> printInstruction ( MI , O ) ; printAnnotation ( O


<s> bool <ISA_LIT>AsmParser :: parseOperand ( OperandVector & Operands ) { DEBUG ( dbgs ( ) << <STR_LIT> ) ; switch ( getLexer ( ) . getKind ( ) ) { default : return Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; case AsmToken :: Identifier : if ( ! tryParseRegisterOperand ( Operands ) ) { return false ; } LLVM_FALLTHROUGH ; case AsmToken :: LParen : case AsmToken :: Integer


<s> MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; auto * RVFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; Register FPReg = getFPReg ( ) ; Register SPReg = getSPReg ( ) ; if ( MF . getFunction ( ) . getCallingConv ( ) == CallingConv :: GHC ) return ; MachineBasicBlock :: iterator MBBI = MBB . end ( ) ; DebugLoc DL ; if ( ! MBB . empty ( ) ) { MBBI = MBB . getFirstTerminator ( ) ; if ( MBBI == MBB . end ( ) ) MBBI = MBB . getLastNonDebugInstr ( ) ; DL = MBBI -> getDebugLoc ( ) ; if ( ! MBBI -> isTerminator ( ) ) MBBI = std :: next ( MBBI ) ; while ( MBBI != MBB . begin ( ) && std :: prev ( MBBI ) -> getFlag ( MachineInstr :: FrameDestroy ) ) -- MBBI ; } const auto & CSI = getNonLibcallCSI ( MF , MFI . getCalleeSavedInfo ( ) ) ; auto LastFrameDestroy = MBBI ; if ( ! CSI . empty ( ) ) LastFrameDestroy = std :: prev ( MBBI , CSI . size ( ) ) ; uint64_t StackSize = MFI . getStackSize ( ) + RVFI -> getRVVPadding ( ) ; uint64_t RealStackSize = StackSize + RVFI -> getLibCallStackSize ( ) ; uint64_t FPOffset = RealStackSize - RVFI -> getVarArgsSaveSize ( ) ; uint64_t RVVStackSize = RVFI -> getRVVStackSize ( ) ; if ( RI -> hasStackRealignment ( MF ) || MFI . hasVarSizedObjects ( ) ) { assert ( hasFP ( MF ) && <STR_LIT> ) ; adjustReg ( MBB , LastFrameDestroy , DL , SPReg , FPReg , - FPOffset , MachineInstr :: FrameDestroy ) ; } else { if ( RVVStackSize ) adjustStackForRVV ( MF , MBB , LastFrameDestroy , DL , RVVStackSize , MachineInstr :: FrameDestroy ) ; } uint64_t FirstSPAdjustAmount = getFirstSPAdjustAmount ( MF ) ; if (


<s> void arc_toggle_unalign ( void ) { cfun -> machine -> unalign ^=


<s> AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( Opc ) ) . addReg ( AddrReg ) ) ; const IndirectBrInst * IB = cast < IndirectBrInst


<s> void <ISA_LIT>FrameLowering :: determineCalleeSaves ( MachineFunction & MF , BitVector & SavedRegs , RegScavenger * RS ) const { TargetFrameLowering :: determineCalleeSaves ( MF , SavedRegs , RS ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; <ISA_LIT>MachineFunctionInfo * <ISA_LIT>FI = MF . getInfo <


<s> TREE_STATIC ( decl ) = <NUM_LIT> ; if ( USE_HIDDEN_LINKONCE && ! TARGET_XCOFF ) { cgraph_node :: create ( decl ) -> set_comdat_group ( DECL_ASSEMBLER_NAME ( decl ) ) ; targetm . asm_out . unique_section ( decl , <NUM_LIT> ) ; switch_to_section ( get_named_section ( decl , NULL , <NUM_LIT> ) ) ; DECL_WEAK ( decl ) = <NUM_LIT> ; ASM_WEAKEN_DECL ( asm_out_file , decl , name , <NUM_LIT> ) ; targetm . asm_out . globalize_label ( asm_out_file , name ) ; targetm . asm_out . assemble_visibility ( decl , VISIBILITY_HIDDEN


<s> MinCSFI = CSI [ <NUM_LIT> ] . getFrameIdx ( ) ; MaxCSFI = CSI [ CSI . size ( ) - <NUM_LIT> ] . getFrameIdx ( ) ; } if ( FI >= MinCSFI && FI <= MaxCSFI ) { FrameReg = <STR_LIT> ; if ( FirstSPAdjustAmount ) Offset += FirstSPAdjustAmount ; else Offset += MFI . getStackSize ( ) ; } else if ( RI -> needsStackRealignment ( MF ) && ! MFI . isFixedObjectIndex ( FI ) ) { if ( hasBP ( MF ) ) FrameReg = <STR_LIT> ( ) ; else FrameReg = <STR_LIT> ; Offset += MFI . getStackSize ( ) ; if ( FI < <NUM_LIT> ) Offset += RVFI -> getLibCallStackSize ( ) ; } else { FrameReg = RI -> getFrameRegister ( MF ) ; if ( hasFP ( MF ) ) { Offset += RVFI -> getVarArgsSaveSize ( ) ; if ( FI >= <NUM_LIT> ) Offset -= RVFI -> getLibCallStackSize ( ) ; } else { Offset += MFI . getStackSize ( ) ; if ( FI < <NUM_LIT> ) Offset +=


<s> Tile64Type Tile64VLIWPacketizerList :: Tile64TypeOf ( const MachineInstr * MI ) const { const uint64_t F = MI -> getDesc ( ) . TSFlags ; return ( Tile64Type ) ( ( F >> TypePos )


<s> return false ; } unsigned Lo , Hi ; Lo = RI . getSubReg ( Reg , <STR_LIT> ) ; Hi = RI . getSubReg ( Reg , <STR_LIT> ) ; MI -> eraseFromParent ( ) ; return true


<s> switch ( mode ) { default : return false


<s> else if ( RC == <STR_LIT> ) BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FrameIdx ) . addReg ( <STR_LIT> ) ; else if ( RC == <STR_LIT> ) BuildMI ( MBB , MI , DL , get ( <STR_LIT>


<s> if ( OutStreamer . hasRawTextSupport ( ) ) OutStreamer . EmitRawText ( <STR_LIT> + Twine ( CurrentFnSym -> getName ( ) ) ) ; OutStreamer . EmitLabel ( CurrentFnSym


<s> const char * output_move_qimode ( rtx * operands ) { gcc_assert ( ! ( GET_CODE ( operands [ <NUM_LIT> ] ) == MEM && GET_CODE ( XEXP ( operands [ <NUM_LIT> ] , <NUM_LIT> ) ) == PRE_DEC && XEXP ( XEXP ( operands [ <NUM_LIT> ] , <NUM_LIT> ) , <NUM_LIT> ) == stack_pointer_rtx && ! ADDRESS_REG_P ( operands [ <NUM_LIT> ] ) && ! TARGET_COLDFIRE ) ) ; if ( ! ADDRESS_REG_P ( operands [ <NUM_LIT> ] ) && ( ( TARGET_68020 || TARGET_COLDFIRE ) || ! ( GET_CODE ( operands [ <NUM_LIT> ] ) == MEM && MEM_VOLATILE_P ( operands [ <NUM_LIT> ] ) ) ) ) { if ( operands [ <NUM_LIT> ] == const0_rtx ) return <STR_LIT> ; if ( ( ! TARGET_COLDFIRE || DATA_REG_P ( operands [ <NUM_LIT> ] ) ) && GET_CODE ( operands [ <NUM_LIT> ] ) == CONST_INT && ( INTVAL ( operands [ <NUM_LIT> ] ) & <NUM_LIT> ) == <NUM_LIT> ) { CC_STATUS_INIT ; return <STR_LIT> ; } } if ( GET_CODE ( operands [ <NUM_LIT> ] ) == CONST_INT && DATA_REG_P ( operands [ <NUM_LIT> ] ) && INTVAL ( operands [ <NUM_LIT> ] ) < <NUM_LIT> && INTVAL ( operands [ <NUM_LIT>


<s> if ( ! FnStartLoc . isValid ( ) ) return Error ( L , <STR_LIT> ) ; resetUnwindDirectiveParserState ( ) ; getParser ( ) . getStreamer ( ) .


<s> static section * c6x_select_rtx_section ( machine_mode mode , rtx x , unsigned HOST_WIDE_INT align


<s> BranchSize = BrOffset ; MaxAlign = std :: max ( MaxAlign , Src -> getAlignment ( ) ) ; int DestBlock = Dest -> getNumber ( ) ; BranchSize += BlockSizes [ DestBlock ] . first ; for ( unsigned i = DestBlock + <NUM_LIT> , e = Src -> getNumber ( ) ; i < e ; ++ i ) { BranchSize += BlockSizes [ i ] . first ; MaxAlign = std :: max ( MaxAlign , Fn . getBlockNumbered ( i ) -> getAlignment ( ) ) ; } NeedExtraAdjustment = ( FirstImpreciseBlock >= <NUM_LIT> ) && ( DestBlock >= FirstImpreciseBlock ) ; } else { unsigned StartBlock = Src -> getNumber ( ) ; BranchSize = BlockSizes [ StartBlock ] . first - BrOffset ; MaxAlign = std :: max ( MaxAlign , Dest -> getAlignment ( ) ) ; for ( unsigned i = StartBlock + <NUM_LIT> , e = Dest -> getNumber ( ) ; i != e ; ++ i ) { BranchSize += BlockSizes [ i ] . first ; MaxAlign = std :: max ( MaxAlign , Fn . getBlockNumbered ( i ) -> getAlignment (


<s> <ISA_LIT>BitcodeWriter ModuleWriter ( M , Buffer , StrtabBuilder , * Stream ) ; ModuleWriter . write (


<s> <ISA_LIT>MCAsmInfo :: <ISA_LIT>MCAsmInfo ( StringRef TT ) { Triple TheTriple ( TT ) ; if ( TheTriple . getArch ( ) == Triple :: nvptx64 ) { PointerSize = CalleeSaveStackSlotSize = <NUM_LIT> ; } CommentString = <STR_LIT> ; HasSingleParameterDotFile = false ; InlineAsmStart = <STR_LIT> ; InlineAsmEnd = <STR_LIT> ; SupportsDebugInformation = CompileForDebugging ; HasFunctionAlignment = false ; HasDotTypeDotSizeDirective =


<s> bool <ISA_LIT>TargetLowering :: getSafeStackPointerLocation ( unsigned & AddressSpace , unsigned & Offset ) const { if ( ! Subtarget -> isTargetAndroid (