<s> Out . EmitInstruction ( Inst , getSTI ( ) ) ; return false ; case Match_MissingFeature : return Error ( IDLoc , <STR_LIT> ) ; case Match_MnemonicFail : { FeatureBitset FBS = ComputeAvailableFeatures ( getSTI ( ) . getFeatureBits ( ) ) ; std :: string Suggestion = <ISA_LIT>MnemonicSpellCheck ( ( ( <ISA_LIT>Operand & ) * Operands [ <NUM_LIT> ] ) . getToken ( ) , FBS ) ; return Error ( IDLoc , <STR_LIT> + Suggestion , ( ( <ISA_LIT>Operand & ) * Operands [ <NUM_LIT> ] ) . getLocRange ( ) ) ; } case Match_InvalidOperand : { SMLoc ErrorLoc = IDLoc ; if ( ErrorInfo != ~ <NUM_LIT> ) { if ( ErrorInfo >= Operands . size ( ) ) return Error ( IDLoc , <STR_LIT> ) ; ErrorLoc = ( ( <ISA_LIT>Operand & ) * Operands [ ErrorInfo ] ) . getStartLoc ( ) ; if ( ErrorLoc == SMLoc ( ) ) ErrorLoc = IDLoc ; } return Error ( ErrorLoc , <STR_LIT>


<s> if ( ExtraCode && ExtraCode [ <NUM_LIT> ] ) { if ( ExtraCode [ <NUM_LIT> ] != <NUM_LIT> ) return true ; switch ( ExtraCode [ <NUM_LIT> ] ) { default : return true ; case 'L' : if ( ! MI -> getOperand ( OpNo ) . isReg ( ) || OpNo + <NUM_LIT> == MI -> getNumOperands ( ) || ! MI -> getOperand

( OpNo + <NUM_LIT> ) . isReg ( ) ) return true ;


<s> if ( Ret . getNode ( ) ) return Ret ; } return SDValue (


<s> const LLT NarrowTy = MRI . getType ( DstReg ) ; const Register SrcReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; const LLT WideTy = MRI . getType ( SrcReg ) ; ( void ) WideTy ; assert ( WideTy . getSizeInBits ( ) >= NarrowTy . getSizeInBits ( ) && <STR_LIT> ) ; assert ( ! NarrowTy . isVector ( ) && <STR_LIT> ) ; MachineOperand & LaneIdxOp = I . getOperand ( <NUM_LIT> ) ; assert ( LaneIdxOp . isReg ( ) && <STR_LIT> ) ; if ( RBI . getRegBank ( DstReg , MRI , TRI ) -> getID ( ) != <STR_LIT> ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return


<s> return true ; } if ( ! MO . isReg ( ) ) { return false ; } int64_t TV ; Register R = MO . getReg ( ) ; if ( ! R . isVirtual ( ) ) { if ( R == <STR_LIT> ) { Val = <NUM_LIT> ; return true ; } return false ; } MachineInstr * DI = MRI -> getVRegDef ( R ) ; unsigned DOpc = DI -> getOpcode ( ) ; switch ( DOpc ) { case TargetOpcode :: COPY : if ( ! checkForImmediate ( DI -> getOperand ( <NUM_LIT> ) , TV ) ) { return false ; } else { Val = TV ; } break ; case <STR_LIT> : if ( DI -> getOperand ( <NUM_LIT> ) . isReg ( ) && DI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) { if ( ! checkForImmediate ( DI -> getOperand ( <NUM_LIT> ) , TV ) ) { return false ; } else { Val = TV ; } } else if ( DI -> getOperand ( <NUM_LIT> ) . isImm ( ) && DI -> getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) { if ( ! checkForImmediate ( DI -> getOperand ( <NUM_LIT> ) , TV ) ) { return false ; } else { Val = TV ; } } else { return false ; } break ; default : return false


<s> if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) { reportParseError ( <STR_LIT> ) ; return false ; } Parser . Lex ( ) ; return false


<s> <ISA_LIT>TargetStreamer :: emitDirectiveSetSoftFloat (


<s> __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a )


<s> } report_fatal_error ( <STR_LIT> <STR_LIT> + mbb -> getParent ( ) -> getFunction ( ) . getName


<s> if ( ! Op . isReg ( ) || ! Op . isUse ( ) ) continue ; Register R = Op


<s> SUnit * SU = PendingQueue [ i ] ; if ( SU -> getHeight ( ) <= CurrCycle ) { avail ++ ; PendingQueue [ i ] = * ( PendingQueue . end ( ) - avail ) ; i -- ; AvailableQueue . push_back ( SU ) ; std :: inplace_merge ( AvailableQueue . begin ( ) , AvailableQueue . end ( ) - <NUM_LIT> , AvailableQueue . end ( ) , Cmp ) ; } } PendingQueue . resize ( PendingQueue . size (


<s> RegisterTargetMachine < AMDGPUTargetMachine > X (


<s> bool hasPOPCNTFalseDeps ( ) const { return HasPOPCNTFalseDeps


<s> SmallVector < BasicBlock * , <NUM_LIT> > Preds ; for ( BasicBlock * Pred : predecessors ( BB ) ) { if ( ! is_contained ( Latches , Pred ) ) Preds . push_back ( Pred ) ; } BB = SplitBlockPredecessors ( BB , Preds , <STR_LIT> , DT , LI , nullptr , false ) ; } Value * Exec = popSaved ( ) ; Instruction * FirstInsertionPt = & * BB


<s> unsigned FrameReg = RegInfo -> getFrameRegister ( MF ) ; SDValue FrameAddr = DAG . getCopyFromReg ( DAG . getEntryNode ( ) , DL , FrameReg , PtrVT ) ; while ( Depth -- ) FrameAddr = DAG . getLoad ( Op . getValueType ( ) , DL , DAG . getEntryNode ( ) , FrameAddr ,


<s> if ( CALL_P ( insn ) ) { bool avx_upper_reg_found = false ; note_stores ( pat , ix86_check_avx_upper_stores , & avx_upper_reg_found


<s> u = Imm | ( Imm << <NUM_LIT> ) ; if ( Vs == u ) return ( ( ( Vs == V ) ? <NUM_LIT> : <NUM_LIT> ) << <NUM_LIT> ) | Imm ; if ( Vs == ( u | ( u << <NUM_LIT> ) ) ) return ( <NUM_LIT> <<


<s> const MCExpr * EVal ; switch ( getLexer ( ) . getKind ( ) ) { default : return <NUM_LIT> ; case AsmToken :: LParen : case AsmToken :: Plus : case AsmToken :: Minus


<s> MCSymbol * <ISA_LIT>MCInstLower :: GetExternalSymbolSymbol ( const MachineOperand & MO ) const { return Printer . GetExternalSymbolSymbol ( MO


<s> NumMatch += loopendPatternMatch ( ) ; NumMatch += serialPatternMatch ( MBB


<s> if ( CModel == CodeModel :: Large || ! GVar || ! GVar -> hasInitializer ( ) || GVar -> hasCommonLinkage ( ) || GVar -> hasAvailableExternallyLinkage ( ) ) BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , DestReg ) . addGlobalAddress ( GV ) . addReg ( HighPartReg ) ; else BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , DestReg ) . addReg ( HighPartReg ) . addGlobalAddress ( GV ) ; } return


<s> DebugLoc Loc ; MachineBasicBlock & Entry = * MF . begin ( ) ; auto EntryInsertPt = Entry . SkipPHIsLabelsAndDebug ( Entry . begin ( ) ) ; bool HasVulnerableLoad = hasVulnerableLoad ( MF ) ; SmallVector < BlockCondInfo , <NUM_LIT> > Infos = collectBlockCondInfo ( MF ) ; if ( ! HasVulnerableLoad && Infos . empty ( ) ) return true ; const int PoisonVal = - <NUM_LIT> ; PS -> PoisonReg = MRI -> createVirtualRegister ( PS -> RC ) ; BuildMI ( Entry , EntryInsertPt , Loc , TII -> get ( <STR_LIT> ) , PS -> PoisonReg ) . addImm ( PoisonVal ) ; ++ NumInstsInserted ; if ( HasVulnerableLoad && FenceCallAndRet ) { BuildMI ( Entry , EntryInsertPt , Loc , TII -> get ( <STR_LIT> ) ) ; ++ NumInstsInserted ; ++ NumLFENCEsInserted ; } if ( FenceCallAndRet && Infos . empty ( ) ) return true ; if ( HardenInterprocedurally && ! FenceCallAndRet ) { PS -> InitialReg = extractPredStateFromSP ( Entry , EntryInsertPt , Loc ) ; } else { PS -> InitialReg = MRI -> createVirtualRegister ( PS -> RC ) ; unsigned PredStateSubReg = MRI -> createVirtualRegister ( & <STR_LIT> ) ; auto ZeroI = BuildMI ( Entry , EntryInsertPt , Loc , TII -> get ( <STR_LIT> ) , PredStateSubReg ) ; ++ NumInstsInserted ; MachineOperand * ZeroEFLAGSDefOp = ZeroI -> findRegisterDefOperand ( <STR_LIT> ) ; assert ( ZeroEFLAGSDefOp && ZeroEFLAGSDefOp -> isImplicit ( ) && <STR_LIT> ) ; ZeroEFLAGSDefOp -> setIsDead ( true ) ; BuildMI ( Entry , EntryInsertPt , Loc , TII -> get ( <STR_LIT> ) , PS -> InitialReg ) . addImm ( <NUM_LIT> ) . addReg ( PredStateSubReg ) . addImm ( <STR_LIT> ) ; } canonicalizePHIOperands ( MF ) ; PS -> SSA . Initialize ( PS -> InitialReg ) ; PS -> SSA . AddAvailableValue ( & Entry , PS -> InitialReg ) ; auto CMovs = tracePredStateThroughCFG ( MF , Infos ) ; if ( HardenInterprocedurally ) { for ( MachineBasicBlock & MBB : MF ) { assert ( ! MBB . isEHScopeEntry ( ) && <STR_LIT> ) ; assert ( ! MBB . isEHFuncletEntry ( ) && <STR_LIT> ) ; assert ( ! MBB . isCleanupFuncletEntry ( ) && <STR_LIT> ) ; if ( ! MBB . isEHPad ( ) ) continue ; PS -> SSA . AddAvailableValue ( & MBB , extractPredStateFromSP ( MBB , MBB . SkipPHIsAndLabels ( MBB . begin ( ) ) , Loc ) ) ; } } if ( HardenIndirectCallsAndJumps ) unfoldCallAndJumpLoads ( MF ) ; tracePredStateThroughBlocksAndHarden ( MF ) ; for ( MachineInstr * CMovI : CMovs ) for ( MachineOperand & Op


<s> BuildMI ( MBB , MBBI , DL , get ( <STR_LIT> ) , Result ) . addReg ( SrcReg , RegState :: Kill ) . addReg ( <STR_LIT> ) . setMIFlag ( Flag ) ; } else if ( Inst . Opc == <STR_LIT> || Inst . Opc == <STR_LIT> || Inst . Opc == <STR_LIT> ) { BuildMI ( MBB , MBBI , DL , get ( Inst . Opc ) , Result ) . addReg ( SrcReg , RegState :: Kill ) . addReg ( SrcReg , RegState :: Kill ) . setMIFlag ( Flag ) ; } else { BuildMI ( MBB , MBBI , DL , get ( Inst . Opc ) , Result ) . addReg ( SrcReg , RegState :: Kill ) . addImm ( Inst . Imm ) . setMIFlag ( Flag ) ; } SrcReg =


<s> if ( ! isValidMsgId ( Msg . Id , getSTI ( ) ) ) { Error ( Msg . Loc , <STR_LIT> ) ; return false ; } } if ( Strict && ( msgRequiresOp ( Msg . Id , getSTI ( ) ) != Op . IsDefined ) ) { if ( Op . IsDefined ) { Error ( Op . Loc , <STR_LIT> ) ; } else { Error ( Msg . Loc , <STR_LIT> ) ; } return false ; } if ( ! isValidMsgOp ( Msg . Id , Op . Id , getSTI ( ) , Strict ) ) { Error ( Op . Loc , <STR_LIT> ) ; return false ; } if ( Strict && ! msgSupportsStream ( Msg . Id , Op . Id , getSTI ( ) ) && Stream . IsDefined ) { Error ( Stream . Loc , <STR_LIT> ) ; return false ; } if ( ! isValidMsgStream ( Msg . Id , Op . Id , Stream . Id , getSTI


<s> auto & TM = static_cast < const <ISA_LIT>TargetMachine & > ( MF . getTarget ( ) ) ; if ( STI . in<ISA_LIT>16Mode (


<s> In = extractSubVector ( In , <NUM_LIT> , DAG , DL , std :: max ( <NUM_LIT> , ( unsigned ) VT . getSizeInBits ( ) / Scale ) ) ; InVT = In . getValueType ( ) ; } if ( VT . getVectorNumElements ( ) != InVT . getVectorNumElements ( ) ) Opcode =

getOpcode_EXTEND_VECTOR_INREG ( Opcode ) ;


<s> return ; case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : O << <STR_LIT> ; return ; } } switch ( SYSm ) { default : llvm_unreachable ( <STR_LIT> ) ; case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : O << <STR_LIT>


<s> return MachineFunctionProperties ( ) . set ( MachineFunctionProperties


<s> credit -= get_attr_length ( prev ) ; } if ( prev && jump_to_label_p ( prev ) ) { rtx_insn * x ; if ( jump_to_next || next_real_insn ( JUMP_LABEL ( prev ) ) == next || JUMP_LABEL ( prev ) == next_nonnote_insn ( next ) || ( x = ( NEXT_INSN ( NEXT_INSN ( PREV_INSN ( prev ) ) ) ) , ( INSN_P ( x ) && ( INSN_CODE ( x ) == CODE_FOR_block_branch_redirect || INSN_CODE ( x ) == CODE_FOR_indirect_jump_scratch || INSN_CODE ( x ) == CODE_FOR_stuff_delay_slot ) ) ) ) { rtx pat = PATTERN ( prev ) ; if ( GET_CODE ( pat ) == PARALLEL ) pat = XVECEXP ( pat , <NUM_LIT> , <NUM_LIT> ) ; if ( credit - slot >= ( GET_CODE ( SET_SRC ( pat ) ) == PC ? <NUM_LIT> : <NUM_LIT> ) ) return <NUM_LIT> ; } } } return align_jumps_log


<s> Y = Y . getOperand ( <NUM_LIT> ) ; PeekedThroughZext = true ; } if ( ! IsSub && ! PeekedThroughZext && X . getOpcode ( ) == <STR_LIT> && Y . getOpcode ( ) != <STR_LIT> ) std :: swap ( X , Y ) ; if ( Y . getOpcode ( ) != <STR_LIT> || ! Y . hasOneUse ( ) ) return SDValue ( ) ; SDLoc DL ( N ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; <STR_LIT> CC = ( <STR_LIT> ) Y . getConstantOperandVal ( <NUM_LIT> ) ; if ( CC == <STR_LIT> ) { SDValue SBB = materializeSBB ( Y . getNode ( ) , Y . getOperand ( <NUM_LIT> ) , DAG ) ; if ( SBB . getValueSizeInBits ( ) != VT . getSizeInBits ( ) ) SBB = DAG . getZExtOrTrunc ( SBB , DL , VT ) ; return DAG . getNode ( IsSub ? <STR_LIT> : <STR_LIT> , DL , VT , X , SBB ) ; } if ( CC == <STR_LIT> ) { SDValue EFLAGS = Y -> getOperand ( <NUM_LIT> ) ; if ( EFLAGS . getOpcode ( ) == <STR_LIT> && EFLAGS . hasOneUse ( ) && EFLAGS . getValueType ( ) . isInteger ( ) && ! isa < ConstantSDNode > ( EFLAGS . getOperand ( <NUM_LIT> ) ) ) { SDValue NewSub = DAG . getNode ( <STR_LIT> , SDLoc ( EFLAGS ) , EFLAGS . getNode ( ) -> getVTList ( ) , EFLAGS . getOperand ( <NUM_LIT> ) , EFLAGS . getOperand ( <NUM_LIT> ) ) ; SDValue NewEFLAGS = SDValue ( NewSub . getNode ( ) , EFLAGS . getResNo ( ) ) ; SDValue SBB = materializeSBB ( Y . getNode ( ) , NewEFLAGS , DAG ) ; if ( SBB . getValueSizeInBits ( ) != VT . getSizeInBits ( ) ) SBB = DAG . getZExtOrTrunc ( SBB , DL , VT ) ; return DAG . getNode ( IsSub ? <STR_LIT> : <STR_LIT> , DL , VT , X , SBB ) ; } } if ( CC != <STR_LIT> && CC != <STR_LIT> ) return SDValue ( ) ; SDValue Cmp = Y . getOperand ( <NUM_LIT> ) ; if ( Cmp . getOpcode ( ) != <STR_LIT> || ! Cmp . hasOneUse ( ) || ! <STR_LIT> ( Cmp . getOperand ( <NUM_LIT> ) ) || ! Cmp . getOperand ( <NUM_LIT> ) . getValueType ( ) . isInteger ( ) ) return SDValue ( ) ; SDValue Z = Cmp . getOperand ( <NUM_LIT> ) ; EVT ZVT = Z . getValueType ( ) ; if ( auto * ConstantX = dyn_cast < ConstantSDNode


<s> unsigned BP = <NUM_LIT> ; int FI = MI . getOperand ( FIOp ) . getIndex ( ) ; int Offset = HFI . getFrameIndexReference ( MF , FI , BP ) ; int RealOffset = Offset + MI . getOperand ( FIOp + <NUM_LIT> ) . getImm ( ) ; bool IsKill = false ; unsigned Opc = MI . getOpcode ( ) ; switch ( Opc ) { case <STR_LIT> : MI . setDesc ( HII . get ( <STR_LIT> ) ) ; MI . getOperand ( FIOp ) . ChangeToImmediate ( RealOffset ) ; MI . RemoveOperand ( FIOp + <NUM_LIT> ) ; return ; case <STR_LIT> : MI . setDesc ( HII . get ( <STR_LIT> ) ) ; break ; } if ( ! HII . isValidOffset ( Opc , RealOffset , this ) ) { auto & MRI = MF . getRegInfo ( ) ; Register TmpR = MRI . createVirtualRegister ( & <STR_LIT> ) ; const DebugLoc & DL = MI . getDebugLoc ( ) ; BuildMI ( MB , II , DL , HII . get ( <STR_LIT> ) , TmpR )

. addReg ( BP ) . addImm ( RealOffset ) ;


<s> static bool CC_<ISA_LIT>_AAPCS_Custom_f64 ( unsigned ValNo , MVT ValVT , MVT LocVT , CCValAssign :: LocInfo

LocInfo , <STR_LIT> ArgFlags , CCState & State ) {


<s> if ( STI . isTargetNaCl ( ) ) { unsigned AddrIdx ; if ( ( isBasePlusOffsetMemoryAccess ( CurrI -> getOpcode ( ) , & AddrIdx ) && baseRegNeedsLoadStoreMask ( CurrI -> getOperand ( AddrIdx ) . getReg ( ) ) ) || CurrI -> modifiesRegister ( <STR_LIT> , STI . getRegisterInfo ( ) ) ) continue ; } bool InMicro<ISA_LIT>Mode = STI . inMicro<ISA_LIT>Mode ( ) ; const <ISA_LIT>InstrInfo * TII = STI . getInstrInfo ( ) ; unsigned Opcode = ( * Slot ) . getOpcode ( ) ; if ( InMicro<ISA_LIT>Mode && TII -> getInstSizeInBytes ( * CurrI ) == <NUM_LIT> && ( Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ) ) continue ; Filler = CurrI ; return true


<s> static void Passv64i1ArgInRegs ( const SDLoc & Dl , SelectionDAG & DAG , SDValue & Arg , SmallVectorImpl < std :: pair < unsigned , SDValue >> & RegsToPass , CCValAssign & VA , CCValAssign & NextVA , const <ISA_LIT>Subtarget & Subtarget ) { assert ( Subtarget . hasBWI ( ) && <STR_LIT> ) ; assert ( Subtarget . is32Bit ( ) && <STR_LIT> ) ; assert ( Arg . getValueType ( ) == <STR_LIT> && <STR_LIT> ) ; assert ( VA . isRegLoc ( ) && NextVA . isRegLoc ( ) && <STR_LIT> ) ; Arg = DAG . getBitcast ( <STR_LIT> , Arg ) ; SDValue Lo ,


<s> if ( ITCounter == <NUM_LIT> ) ITState = <NUM_LIT> ; else { unsigned short NewITState4_0 = slice ( ITState , <NUM_LIT> ,


<s> if ( Index >= <NUM_LIT> ) return MI . getOperand ( Index )


<s> const unsigned NumVIndexOps = IsCmpSwap ? <NUM_LIT> : <NUM_LIT> ; const bool HasVIndex = MI . getNumOperands ( ) == NumVIndexOps ; Register VIndex ; if ( HasVIndex ) { VIndex = MI . getOperand ( <NUM_LIT> + OpOffset ) . getReg ( ) ; ++ OpOffset ; } Register VOffset = MI . getOperand ( <NUM_LIT> + OpOffset ) . getReg ( ) ; Register SOffset = MI . getOperand ( <NUM_LIT> + OpOffset ) . getReg ( ) ; unsigned AuxiliaryData = MI . getOperand ( <NUM_LIT> + OpOffset ) . getImm ( ) ; MachineMemOperand * MMO = * MI . memoperands_begin ( ) ; unsigned ImmOffset ; unsigned TotalOffset ; std :: tie ( VOffset , ImmOffset , TotalOffset ) = splitBufferOffsets ( B , VOffset ) ; if ( TotalOffset != <NUM_LIT> ) MMO = B . getMF ( ) . getMachineMemOperand ( MMO , TotalOffset , MMO -> getSize ( ) ) ; if ( ! VIndex ) VIndex = B . buildConstant ( LLT :: scalar ( <NUM_LIT> ) , <NUM_LIT> ) . getReg ( <NUM_LIT> ) ; auto MIB = B . buildInstr ( getBufferAtomicPseudo ( IID ) ) . addDef ( Dst ) . addUse ( VData ) ; if ( IsCmpSwap ) MIB . addReg ( CmpVal


<s> const MUBUFInfo * Info = getMUBUFOpcodeHelper ( Opc ) ; return Info ? Info -> IsBufferInv


<s> SDValue <ISA_LIT>TargetLowering :: LowerGLOBALADDRESS ( SDValue Op , SelectionDAG & DAG ) const { SDValue Result ; const GlobalValue * GV = cast < GlobalAddressSDNode > ( Op ) -> getGlobal ( ) ; int64_t Offset = cast < GlobalAddressSDNode > ( Op ) -> getOffset ( ) ; DebugLoc dl = Op . getDebugLoc ( ) ; Result = DAG . getTargetGlobalAddress ( GV , dl , getPointerTy ( ) , Offset ) ; <ISA_LIT>TargetObjectFile & TLOF = ( <ISA_LIT>TargetObjectFile & ) getObjFileLowering ( ) ; if ( TLOF . IsGlobalInSmallSection ( GV , getTargetMachine ( ) ) ) { return DAG . getNode ( <STR_LIT> , dl , getPointerTy ( )


<s> unsigned shift = Log2_64 ( NumBytes ) ; if ( NumBytes && Offset > <NUM_LIT> && ( Offset / NumBytes ) <= ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> && ( Offset >> shift ) << shift == Offset ) return true ; return false ; } if ( ! AM . Scale || AM . Scale == <NUM_LIT> || ( AM . Scale

> <NUM_LIT> && ( uint64_t ) AM . Scale == NumBytes ) ) return true ;


<s> uint64_t Mask = <NUM_LIT> ; switch ( RetVT . SimpleTy ) { default : return <NUM_LIT> ; case <STR_LIT> : Opc = <STR_LIT> ; NeedTrunc = true ; Mask = <NUM_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; NeedTrunc = true ; Mask = <NUM_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; } const TargetRegisterClass * RC = ( RetVT == <STR_LIT> ) ? & <STR_LIT> :


<s> return ( int16x8_t ) __builtin_aarch64_sqaddv8hi (


<s> static inline bool isDoLoopStart ( const MachineInstr & MI


<s> if ( auto * BV = dyn_cast < BuildVectorSDNode > ( Op0 . getOperand ( <NUM_LIT> ) ) ) { if ( ! BV -> isConstant ( ) ) return SDValue ( ) ; SDLoc DL ( N ) ; EVT IntVT = BV -> getValueType ( <NUM_LIT> ) ; SDValue SourceConst ; if ( IsStrict ) SourceConst = DAG . getNode ( N -> getOpcode ( ) , DL , { VT , <STR_LIT> } , { N -> getOperand ( <NUM_LIT> ) , SDValue ( BV , <NUM_LIT> ) } ) ; else SourceConst = DAG . getNode ( N -> getOpcode ( ) , DL , VT , SDValue ( BV , <NUM_LIT> ) ) ; SDValue MaskConst = DAG . getBitcast ( IntVT , SourceConst ) ; SDValue NewAnd = DAG . getNode ( <STR_LIT> , DL , IntVT , Op0 -> getOperand ( <NUM_LIT> ) , MaskConst ) ; SDValue Res = DAG . getBitcast


<s> unsigned <ISA_LIT>InstrInfo :: isStoreFromStackSlot ( const MachineInstr * MI


<s> static rtx pdp11_function_arg ( cumulative_args_t


<s> if ( SyntaxVariant == <NUM_LIT> ) return new <ISA_LIT>InstPrinter ( MAI , MII , MRI ) ; return <NUM_LIT>


<s> StringRef Dirname ( DIUnit . getDirectory ( ) ) ; SmallString < <NUM_LIT> > FullPathName = Dirname ; if ( ! Dirname . empty ( ) && ! sys :: path :: is_absolute ( Filename ) ) { sys :: path :: append ( FullPathName , Filename ) ; Filename = FullPathName ; } if ( filenameMap . find ( Filename ) != filenameMap . end ( ) ) continue ; filenameMap [ Filename ] = i ; OutStreamer . EmitDwarfFileDirective ( i , <STR_LIT> , Filename ) ; ++ i ; } for ( DISubprogram SP : DbgFinder . subprograms ( ) ) { StringRef Filename ( SP . getFilename ( ) ) ; StringRef Dirname ( SP . getDirectory ( ) ) ; SmallString < <NUM_LIT> > FullPathName = Dirname ; if ( ! Dirname . empty ( ) && ! sys :: path :: is_absolute ( Filename


<s> static unsigned AddLiveIn ( MachineFunction & MF , unsigned PReg , const TargetRegisterClass * RC ) { assert ( RC -> contains ( PReg


<s> if ( ID == & TargetTransformInfo :: ID ) return ( TargetTransformInfo *


<s> const <ISA_LIT>InstrInfo * llvm :: create<ISA_LIT>SEInstrInfo ( const <ISA_LIT>Subtarget & STI ) { return new <ISA_LIT>SEInstrInfo


<s> auto E = CurrentISELList . end ( ) ; while ( I != E ) { assert ( isISEL ( * * I ) && <STR_LIT> ) ; MachineOperand & Dest = ( * I ) -> getOperand ( <NUM_LIT> ) ; MachineOperand & TrueValue = ( * I ) -> getOperand ( <NUM_LIT> ) ; MachineOperand & FalseValue = ( * I ) -> getOperand ( <NUM_LIT> ) ; if ( useSameRegister ( Dest , TrueValue ) && useSameRegister ( Dest , FalseValue ) ) { DEBUG ( dbgs ( ) << <STR_LIT> << * * I << <STR_LIT> ) ; NumRemoved ++ ; ( * I ) -> eraseFromParent ( ) ; I ++ ; } else if ( useSameRegister ( TrueValue , FalseValue ) ) { MachineBasicBlock * MBB = ( * I ) -> getParent ( ) ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; DEBUG ( dbgs ( ) << <STR_LIT>


<s> size_t <ISA_LIT>To<ISA_LIT>Stub :: size ( )


<s> void <ISA_LIT>MCAsmStreamer :: EmitBytes ( StringRef Data ) { for ( unsigned i = <NUM_LIT> , e = Data . size ( ) ; i != e ; ++ i ) { EmitValue ( MCConstantExpr :: create ( ( unsigned char ) Data [ i ] ,


<s> MCObjectWriter * llvm :: create<ISA_LIT>WinCOFFObjectWriter ( raw_ostream & OS , bool Is64Bit ) { MCWinCOFFObjectTargetWriter * MOTW = new <ISA_LIT>WinCOFFObjectWriter ( Is64Bit ) ; return createWinCOFFObjectWriter ( MOTW ,


<s> for ( auto iter = Definitions . begin ( ) , end = Definitions . end ( ) ; iter != end ; iter ++ ) { if ( ( * iter ) . useBlock == oldBlock ) { ( * iter ) . useBlock = newBlock ; } } for ( auto iter = ExitTargets . begin ( ) , end = ExitTargets . end ( ) ; iter != end ; iter ++ ) { if ( * iter


<s> void push ( unsigned Weight , const Candidate && C


<s> static int ATTRIBUTE_UNUSED nvptx_mach_max_workers ( ) { if ( ! cfun -> machine -> axis_dim_init_p )


<s> Opc = <STR_LIT> ; RC = & <STR_LIT> ; } break ; case <STR_LIT> : return false ; case <STR_LIT> : if ( IsNonTemporal && Alignment >= <NUM_LIT> && HasSSE41 ) Opc = HasVLX ? <STR_LIT> : HasAVX ? <STR_LIT> : <STR_LIT> ; else if ( Alignment >= <NUM_LIT> ) Opc = HasVLX ? <STR_LIT> : HasAVX ? <STR_LIT> : <STR_LIT> ; else Opc = HasVLX ? <STR_LIT> : HasAVX ? <STR_LIT> : <STR_LIT> ; RC = HasVLX ? & <STR_LIT> : & <STR_LIT> ; break ; case <STR_LIT> : if ( IsNonTemporal && Alignment >= <NUM_LIT> && HasSSE41 ) Opc = HasVLX ? <STR_LIT> : HasAVX ? <STR_LIT> : <STR_LIT> ; else if ( Alignment >= <NUM_LIT> ) Opc = HasVLX ? <STR_LIT> : HasAVX ? <STR_LIT> : <STR_LIT> ; else Opc = HasVLX ? <STR_LIT> : HasAVX ? <STR_LIT> : <STR_LIT> ; RC = HasVLX ? & <STR_LIT> : & <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( IsNonTemporal && Alignment >= <NUM_LIT> ) Opc = HasVLX ? <STR_LIT> : HasAVX ? <STR_LIT> : <STR_LIT> ; else if ( Alignment >= <NUM_LIT> ) Opc = HasVLX ? <STR_LIT> : HasAVX ? <STR_LIT> : <STR_LIT> ; else Opc = HasVLX ? <STR_LIT> : HasAVX ? <STR_LIT> : <STR_LIT> ; RC = HasVLX ? & <STR_LIT> : & <STR_LIT> ; break ; case <STR_LIT> : assert ( HasAVX ) ; if ( IsNonTemporal && Alignment >= <NUM_LIT> && HasAVX2 ) Opc = HasVLX ? <STR_LIT> : <STR_LIT> ; else if ( IsNonTemporal && Alignment >= <NUM_LIT> ) return false ; else if ( Alignment >= <NUM_LIT> ) Opc = HasVLX ? <STR_LIT> : <STR_LIT> ; else Opc = HasVLX ? <STR_LIT> : <STR_LIT> ; RC = HasVLX ? & <STR_LIT> : & <STR_LIT> ; break ; case <STR_LIT> : assert ( HasAVX ) ; if ( IsNonTemporal && Alignment >= <NUM_LIT> && HasAVX2 ) Opc = HasVLX ? <STR_LIT> : <STR_LIT> ; else if ( IsNonTemporal && Alignment >= <NUM_LIT> ) return false ; else if ( Alignment >= <NUM_LIT> ) Opc = HasVLX ? <STR_LIT> : <STR_LIT> ; else Opc = HasVLX ? <STR_LIT> : <STR_LIT> ; RC = HasVLX ? & <STR_LIT> : & <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : assert ( HasAVX ) ; if ( IsNonTemporal && Alignment >= <NUM_LIT> && HasAVX2 ) Opc = HasVLX ? <STR_LIT> : <STR_LIT> ; else if ( IsNonTemporal && Alignment >= <NUM_LIT> ) return false ; else if ( Alignment >= <NUM_LIT> ) Opc = HasVLX ? <STR_LIT> : <STR_LIT> ; else Opc = HasVLX ? <STR_LIT>


<s> RegisterMCAsmParser < <ISA_LIT>AsmParser > Y ( The<ISA_LIT>beTarget


<s> return CurDAG -> getTargetConstant (


<s> bool hasBranchDivergence ( ) { return


<s> yaml :: MachineFunctionInfo * <ISA_LIT>TargetMachine :: createDefaultFuncInfoYAML ( ) const { return new yaml :: <ISA_LIT>FunctionInfo


<s> const <ISA_LIT>TargetLowering * getTargetLowering (


<s> break ; case <STR_LIT> : case <STR_LIT> : OpCode = <STR_LIT> ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } if ( DstReg == SrcReg ) { unsigned ATReg = getATReg ( Inst . getLoc ( ) ) ; if ( ! ATReg ) return true ; ImmReg = ATReg ; } if ( loadImmediate ( ImmValue , ImmReg , <STR_LIT> , isInt < <NUM_LIT> > ( ImmValue ) , false , IDLoc , Out ,


<s> if ( ReadCount == <NUM_LIT> && Buf [ <NUM_LIT> ] . getKind ( ) == AsmToken :: RParen ) { HadParens = true ; LParen = getParser ( ) . getTok ( ) ; getParser ( ) . Lex ( ) ; } } switch ( getLexer ( ) . getKind ( ) ) { default : if ( HadParens ) getLexer ( ) . UnLex ( LParen ) ; return MatchOperand_NoMatch ; case AsmToken :: Identifier : StringRef Name = getLexer ( ) . getTok ( ) . getIdentifier ( ) ; unsigned RegNo


<s> switch ( getSlotOpCode ( MCInstD ) ) { case LD_L : return true ; } return false


<s> static unsigned getADDriOpcode ( unsigned is64Bit , int64_t Imm ) { if ( is64Bit ) { if ( isInt < <NUM_LIT> > ( Imm ) ) return <STR_LIT> ; return <STR_LIT> ; } else { if ( isInt < <NUM_LIT> > ( Imm ) ) return <STR_LIT> ; return <STR_LIT>


<s> vpaddq_f64 ( float64x2_t a , float64x2_t b ) { float64x2_t result ; __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT> (


<s> SDNode * Res = DAG . getMachineNode ( <STR_LIT> , DL , <STR_LIT> , <STR_LIT> , Ops ) ; return SDValue ( Res , <NUM_LIT> ) ; } SDValue Zero = DAG . getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; SDValue Ops [ ] = { DAG . getRegister ( <STR_LIT> , <STR_LIT> ) , DAG . getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) , DAG . getRegister ( <NUM_LIT> , <STR_LIT> ) , DAG . getTargetConstant ( SPOffset , DL , <STR_LIT> ) , DAG . getRegister ( <NUM_LIT> , <STR_LIT> )


<s> void <ISA_LIT>InstPrinter :: printImmScale ( const MCInst * MI , unsigned OpNum , raw_ostream & O ) { O << '#' << Scale * MI -> getOperand ( OpNum ) . getImm


<s> code = alt_code ; * op2 = alt_op2 ; goto rebuild_cmp ; } if ( ! nios2_simple_const_p ( * op2 ) && nios2_simple_const_p ( alt_op2 ) ) { code = alt_code ; * op2 = alt_op2 ; } * op2 = force_reg ( SImode , * op2 ) ; } check_rebuild_cmp : if ( code == GT || code == GTU || code == LE || code == LEU ) { rtx t = * op1 ; * op1 = *


<s> return ( __mmask32 ) __builtin_ia32_kmovd ( (


<s> if ( Op . getValueType ( ) == <STR_LIT> && Vec . getScalarValueSizeInBits ( ) < <NUM_LIT> ) { SDLoc dl ( Op ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Vec , Lane ) ; } return


<s> SDNode * <ISA_LIT>DAGToDAGISel :: SelectT2CMOVSoImmOp ( SDNode * N , SDValue FalseVal , SDValue TrueVal , <STR_LIT> CCVal , SDValue CCR , SDValue InFlag ) { ConstantSDNode * T = dyn_cast < ConstantSDNode > ( TrueVal ) ; if ( ! T ) return


<s> if ( ReportErrors ) Context . reportError ( Loc


_rdrand64_step ( unsigned long long * __P ) {


<s> if ( ! ret ) ++ ( insn -> readerCursor ) ; return


<s> for ( int i = <NUM_LIT> ; i < s -> m_num_vals ; i ++ ) { Expr * e = & s


<s> void <ISA_LIT>TargetLowering :: AnalyzeReturn ( CCState & State , const SmallVectorImpl < <STR_LIT>


<s> void GCNScheduleDAGMILive :: computeBlockPressure ( const MachineBasicBlock * MBB ) { GCNDownwardRPTracker RPTracker ( * LIS ) ; const MachineBasicBlock * OnlySucc = nullptr ; if ( MBB -> succ_size ( ) == <NUM_LIT> && ! ( * MBB -> succ_begin ( ) ) -> empty ( ) ) { SlotIndexes * Ind = LIS -> getSlotIndexes ( ) ; if ( Ind -> getMBBStartIdx ( MBB ) < Ind -> getMBBStartIdx ( * MBB -> succ_begin ( ) ) ) OnlySucc = * MBB -> succ_begin ( ) ; } size_t CurRegion = RegionIdx ; for ( size_t E = Regions . size ( ) ; CurRegion != E ; ++ CurRegion ) if ( Regions [ CurRegion ] . first -> getParent ( ) != MBB ) break ; -- CurRegion ; auto I = MBB -> begin ( ) ; auto LiveInIt = MBBLiveIns . find ( MBB ) ; if ( LiveInIt != MBBLiveIns . end ( ) ) { auto LiveIn = std :: move ( LiveInIt -> second ) ; RPTracker . reset ( * MBB -> begin ( ) , & LiveIn ) ; MBBLiveIns . erase ( LiveInIt ) ; } else { auto & Rgn = Regions [ CurRegion ] ; I = Rgn . first ; auto * NonDbgMI = & * skipDebugInstructionsForward ( Rgn . first , Rgn . second ) ; auto LRS = BBLiveInMap . lookup ( NonDbgMI ) ; assert ( isEqual ( getLiveRegsBefore ( * NonDbgMI , * LIS ) , LRS ) ) ; RPTracker . reset ( * I , & LRS ) ; } for ( ; ; ) { I = RPTracker . getNext ( ) ; if ( Regions [ CurRegion ] . first == I ) { LiveIns [ CurRegion ] = RPTracker . getLiveRegs ( ) ; RPTracker . clearMaxPressure ( ) ; } if ( Regions [ CurRegion ] . second == I ) { Pressure [ CurRegion ] = RPTracker . moveMaxPressure ( ) ; if ( CurRegion -- == RegionIdx ) break ; } RPTracker . advanceToNext ( ) ; RPTracker . advanceBeforeNext ( ) ; } if ( OnlySucc ) { if ( I != MBB -> end ( ) ) { RPTracker . advanceToNext ( ) ; RPTracker . advance ( MBB -> end ( ) ) ; } RPTracker . reset ( * OnlySucc -> begin ( ) , & RPTracker . getLiveRegs ( ) ) ; RPTracker . advanceBeforeNext ( ) ; MBBLiveIns [ OnlySucc ] = RPTracker .


<s> if ( bitmap_bit_p ( edge_components , <NUM_LIT> ) && bitmap_bit_p ( DF_LIVE_IN ( e -> dest ) , <NUM_LIT> ) ) { if ( dump_file ) fprintf ( dump_file , <STR_LIT> <STR_LIT> , e -> dest -> index ) ; bitmap_clear_bit ( components , <NUM_LIT>


<s> if ( GET_CODE ( op ) == LABEL_REF ) return TARGET_ADDR32 ; if ( GET_CODE ( op ) == SYMBOL_REF ) sym = op ; else if ( GET_CODE ( op ) == CONST && GET_CODE ( XEXP ( op , <NUM_LIT> ) ) == PLUS && GET_CODE ( XEXP ( XEXP ( op , <NUM_LIT> ) , <NUM_LIT> ) ) == SYMBOL_REF && GET_CODE ( XEXP ( XEXP ( op , <NUM_LIT> ) , <NUM_LIT> ) ) == CONST_INT && ! flag_pic ) sym = XEXP ( XEXP ( op , <NUM_LIT> ) , <NUM_LIT> ) ; else return <NUM_LIT> ; return ( ! addr24_operand ( sym , mode ) && ! small_data_operand ( sym ,


<s> vpmax_s32 ( int32x2_t a , int32x2_t b ) { return __builtin_aarch64_smaxpv2si ( a , b


<s> ArtCombiner . tryCombineMerges ( MI , DeadInstrs , UpdatedDefs ) ; for ( MachineInstr * DeadMI : DeadInstrs )


<s> Displacement = <NUM_LIT> ; IndexReg = <STR_LIT> ; break ; case <NUM_LIT> : NopSize = <NUM_LIT> ; Opc = <STR_LIT> ; Displacement = <NUM_LIT> ; break ; case <NUM_LIT> : NopSize = <NUM_LIT> ; Opc = <STR_LIT> ; Displacement = <NUM_LIT> ; IndexReg = <STR_LIT> ; break ; case <NUM_LIT> : NopSize = <NUM_LIT> ; Opc = <STR_LIT> ; Displacement = <NUM_LIT> ; IndexReg = <STR_LIT> ; break ; default : NopSize = <NUM_LIT> ; Opc = <STR_LIT> ; Displacement = <NUM_LIT> ; IndexReg = <STR_LIT> ; SegmentReg = <STR_LIT> ; break ; } unsigned NumPrefixes = std :: min ( NumBytes - NopSize , <NUM_LIT> ) ; NopSize += NumPrefixes ; for ( unsigned i = <NUM_LIT> ; i != NumPrefixes ; ++ i ) OS . EmitBytes ( <STR_LIT> ) ; switch ( Opc ) { default : llvm_unreachable ( <STR_LIT> ) ; break ; case <STR_LIT> : OS . EmitInstruction ( MCInstBuilder ( Opc ) , STI ) ; break ; case <STR_LIT> : OS . EmitInstruction ( MCInstBuilder ( Opc ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) , STI ) ; break ; case


<s> if ( is_packed ) return false ; if ( TREE_CODE ( TYPE_SIZE ( type ) ) == INTEGER_CST && ( wi :: to_widest ( TYPE_SIZE (


<s> return RetAddr ; } SDValue FrameAddr = getFRAMEADDR ( depth - <NUM_LIT> , Op , DAG , Subtarget ) ; unsigned Offset = ( Subtarget -> is64Bit ( ) ) ? <NUM_LIT> : <NUM_LIT> ; SDValue Ptr = DAG . getNode ( <STR_LIT> , dl , VT , FrameAddr , DAG . getIntPtrConstant ( Offset , dl ) ) ; RetAddr = DAG . getLoad ( VT , dl , DAG . getEntryNode ( ) , Ptr , MachinePointerInfo (

) , false , false , false , <NUM_LIT> ) ;


<s> return __builtin_aarch64_lceilhfhi ( __a )


<s> MachineBasicBlock & B = * MI -> getParent ( ) ; DebugLoc DL = MI -> getDebugLoc ( ) ; unsigned PredOpc = getCondOpcode ( Opc , invertJump ) ; MachineInstrBuilder T = BuildMI ( B , MI , DL , get ( PredOpc ) ) ; unsigned NOp = <NUM_LIT> , NumOps = MI -> getNumOperands ( ) ; while ( NOp < NumOps ) { MachineOperand & Op = MI -> getOperand ( NOp ) ; if ( ! Op . isReg ( ) || ! Op . isDef ( ) || Op . isImplicit ( ) ) break ; T . addOperand ( Op ) ; NOp ++ ; } unsigned PredReg , PredRegPos , PredRegFlags ; bool GotPredReg = getPredReg ( Cond , PredReg , PredRegPos , PredRegFlags ) ; ( void )


<s> unsigned RegAreaSize = NumRegs * GPRSizeInBytes ; unsigned FrameObjSize = std :: max ( Flags . getByValSize ( ) , RegAreaSize ) ; int FrameObjOffset ; ArrayRef < MCPhysReg > ByValArgRegs = ABI . GetByValArgRegs ( ) ; if ( RegAreaSize ) FrameObjOffset = ( int ) ABI . GetCalleeAllocdArgSizeInBytes ( State . getCallingConv ( ) ) - ( int ) ( ( ByValArgRegs . size ( ) - FirstReg ) * GPRSizeInBytes ) ; else FrameObjOffset = VA . getLocMemOffset ( ) ; EVT PtrTy = getPointerTy ( DAG . getDataLayout ( ) ) ; int FI = MFI . CreateFixedObject ( FrameObjSize , FrameObjOffset , false , true ) ; SDValue FIN = DAG . getFrameIndex ( FI , PtrTy ) ; InVals . push_back ( FIN ) ; if ( ! NumRegs ) return ; MVT RegTy = <STR_LIT> ( GPRSizeInBytes * <NUM_LIT> ) ; const TargetRegisterClass * RC = getRegClassFor ( RegTy ) ; for ( unsigned I = <NUM_LIT> ; I < NumRegs ; ++ I ) { unsigned ArgReg = ByValArgRegs [ FirstReg + I ] ; unsigned VReg = addLiveIn ( MF ,


<s> rtx mem = gen_rtx_MEM ( BLKmode , gen_rtx_REG ( Pmode , STACK_POINTER_REGNUM )


<s> const MCExpr * TargetExpr = MCSymbolRefExpr :: create ( Target , MCSymbolRefExpr :: VariantKind :: VK_None , OutContext ) ; EmitToStreamer ( * OutStreamer , MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addExpr ( TargetExpr ) ) ; for ( int8_t I = <NUM_LIT> ; I < NoopsInSledCount ; I ++ ) EmitToStreamer ( * OutStreamer , MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ) ; OutStreamer -> EmitLabel ( Target ) ; if ( ! Subtarget -> isGP64bit ( ) ) { EmitToStreamer ( * OutStreamer , MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> )


<s> return ( flag_pic && ! TARGET_PIC_DATA_TEXT_REL


<s> void <ISA_LIT>InstPrinter :: printInst ( const MCInst * MI , raw_ostream &


<s> static void sparc_emit_set_const64_quick2 ( rtx op0 , rtx temp , unsigned HOST_WIDE_INT high_bits , unsigned HOST_WIDE_INT low_immediate , int shift_count ) { rtx temp2 = op0 ; if ( ( high_bits & <NUM_LIT> ) != <NUM_LIT> ) { emit_insn ( gen_safe_HIGH64 ( temp ,


<s> return __builtin_mve_vpnotv16bi ( __a )


<s> return ( __m512i ) __builtin_ia32_movdqa32load512_mask ( ( const __v16si * ) __P , ( __v16si


<s> <ISA_LIT>Operand * <ISA_LIT>AsmParser :: ParseIntelOffsetOfOperator ( SMLoc Start ) { SMLoc OffsetOfLoc = Start ; Parser . Lex ( ) ; Start = Parser . getTok ( ) . getLoc ( ) ; assert ( Parser . getTok ( ) . is ( AsmToken :: Identifier ) && <STR_LIT> ) ; SMLoc End ; const MCExpr *


<s> int <ISA_LIT>TTIImpl :: getAddressComputationCost ( Type * Ty , ScalarEvolution * SE , const SCEV * Ptr ) { unsigned NumVectorInstToHideOverhead = <NUM_LIT> ; int MaxMergeDistance = <NUM_LIT> ; if ( Ty -> isVectorTy ( ) && SE && ! BaseT :: isConstantStridedAccessLessThan ( SE , Ptr , MaxMergeDistance + <NUM_LIT> ) ) return NumVectorInstToHideOverhead ; return <NUM_LIT>


<s> if ( ! KindRes ) return true ; unsigned ElementWidth = KindRes -> second ; Operands . push_back ( <ISA_LIT>Operand :: CreateVectorReg ( Reg , RegKind :: NeonVector , ElementWidth , S , getLoc ( ) , getContext ( ) ) ) ; if ( ! Kind . empty ( ) ) Operands . push_back ( <ISA_LIT>Operand :: CreateToken ( Kind , S , getContext ( ) ) ) ; return tryParseVectorIndex ( Operands ) ==


<s> opnum = nonvoid ; FOR_EACH_CALL_EXPR_ARG ( arg , iter , exp ) { const struct insn_operand_data * insn_op ; if ( arg == error_mark_node ) return NULL_RTX ; if ( opnum > MAX_BUILTIN_ARGS ) return NULL_RTX ; insn_op = & insn_data [ icode ] . operand [ opnum ] ; op [ opnum ] = expand_expr ( arg , NULL_RTX , insn_op -> mode , EXPAND_NORMAL ) ; if ( ! ( * insn_op -> predicate ) ( op [ opnum ] , insn_op -> mode ) ) { machine_mode opmode = insn_op -> mode ; if ( opmode == VOIDmode ) { machine_mode m = GET_MODE ( op [ opnum ] ) ; gcc_assert ( m == Pmode || m == VOIDmode ) ; opmode = Pmode ; } op [ opnum ] = copy_to_mode_reg ( opmode , op [ opnum ] ) ; } if ( ! ( * insn_op -> predicate ) ( op [ opnum ] , insn_op -> mode ) ) { error_at ( EXPR_LOCATION ( exp ) , <STR_LIT> ) ; return const0_rtx ; } opnum ++ ; } if ( nonvoid ) { machine_mode tmode = insn_data [ icode ] . operand [ <NUM_LIT> ] . mode ; if ( ! target || GET_MODE ( target ) != tmode || ! ( * insn_data [ icode ] . operand [ <NUM_LIT> ] . predicate ) ( target , tmode ) ) { if ( tmode == VOIDmode ) { tmode = TYPE_MODE ( TREE_TYPE ( TREE_TYPE ( fndecl ) ) ) ; } target = gen_reg_rtx ( tmode ) ; } op [ <NUM_LIT> ] = target ; } fn = GEN_FCN ( icode ) ; switch ( opnum ) { case <NUM_LIT> : pat = fn ( NULL_RTX


<s> if ( ! active_insn_p ( use_insn ) ) return ; if ( ! nds32_float_reg_load_store_p ( use_insn ) || find_post_update_rtx ( use_insn ) != - <NUM_LIT> ) return ; } group_id = GEN_INT ( nds32_alloc_relax_group_id ( ) ) ; emit_insn_before ( gen_relax_group ( group_id ) , insn ) ; for ( link = DF_REF_CHAIN ( def_record ) ; link ; link = link -> next ) { if ( ! DF_REF_INSN_INFO ( link -> ref ) ) continue ; use_insn = DF_REF_INSN ( link -> ref ) ; emit_insn_before ( gen_relax_group ( group_id


<s> } else { NewOpcode = <STR_LIT> ; Start &= <NUM_LIT> ; End &= <NUM_LIT> ; } MachineOperand & Dest = MI . getOperand ( <NUM_LIT> ) ; MachineOperand & Src = MI . getOperand ( <NUM_LIT> ) ; MachineInstrBuilder MIB = BuildMI ( * MBB , MI , MI . getDebugLoc ( ) , get ( NewOpcode ) ) . add ( Dest ) . addReg ( <NUM_LIT> ) . addReg ( Src . getReg ( ) , getKillRegState ( Src . isKill ( ) ) , Src . getSubReg ( ) ) . addImm ( Start ) . addImm ( End + <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; if ( LV ) { unsigned NumOps = MI . getNumOperands ( ) ; for ( unsigned I = <NUM_LIT> ; I < NumOps ; ++ I ) { MachineOperand & Op = MI . getOperand


<s> else { if ( cfun -> machine -> is_interrupt ) { fputs ( <STR_LIT> , file ) ; } else if ( cfun -> machine -> is_signal ) { fputs ( <STR_LIT> , file ) ; } else fputs ( <STR_LIT> , file ) ; } if ( ACCUMULATE_OUTGOING_ARGS ) fprintf ( file , <STR_LIT> , avr_outgoing_args_size ( ) ) ; fprintf ( file , <STR_LIT> HOST_WIDE_INT_PRINT_DEC <STR_LIT> , ( HOST_WIDE_INT ) get_frame_size ( ) ) ; if ( ! cfun -> machine -> gasisr . yes ) { fprintf ( file , <STR_LIT> , cfun -> machine -> stack_usage ) ; fprintf ( file , <STR_LIT> , cfun -> machine -> stack_usage ) ; } else { int used_by_gasisr = <NUM_LIT> + ( cfun -> machine -> gasisr .


<s> if ( ( Lo . getOpcode ( ) != <STR_LIT> ) || ( Lo . getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> ) ) return SDValue ( ) ; EVT ValTy = N -> getValueType ( <NUM_LIT> ) ; DebugLoc DL = N -> getDebugLoc ( ) ; SDValue Add1 = DAG . getNode ( <STR_LIT> , DL , ValTy , N -> getOperand ( <NUM_LIT> ) , Add . getOperand (


<s> static bool isExport ( const SUnit & SU ) { const MachineInstr * MI = SU . getInstr ( ) ; return MI -> getOpcode ( ) == <STR_LIT> || MI ->


<s> return getLoadStoreRegOpcode ( DestReg , RC ,


<s> HOST_WIDE_INT value = real_to_integer ( & r0 ) ; value = value & <NUM_LIT> ; if ( ( value != <NUM_LIT> ) && ( ( value &

( value - <NUM_LIT> ) ) == <NUM_LIT> ) ) {


<s> __ev64_opaque__ v ; int16_t i [ <NUM_LIT> ] ; } u ; u . i [ <NUM_LIT> ] = a ; u . i [ <NUM_LIT> ] = b ; u . i [ <NUM_LIT>


<s> lowerConstantPool ( SDValue Op , SelectionDAG & DAG ) const { ConstantPoolSDNode * N = cast < ConstantPoolSDNode > ( Op ) ; EVT Ty = Op . getValueType ( ) ; if ( ! isPositionIndependent ( ) ) { const <ISA_LIT>TargetObjectFile * TLOF = static_cast < const <ISA_LIT>TargetObjectFile * > ( getTargetMachine ( ) . getObjFileLowering ( ) ) ; if ( TLOF -> IsConstantInSmallSection ( DAG . getDataLayout ( ) , N -> getConstVal ( ) , getTargetMachine ( ) ) ) return getAddrGPRel ( N , SDLoc ( N ) , Ty , DAG ,


<s> bool found = false ; int ( * getAltOpcode ) ( uint16_t , <STR_LIT> ) ; int ( * getAltOpcodeGen ) ( uint16_t , <STR_LIT> ) = nullptr ; int ( * getAltOpcodeGenEx ) ( uint16_t , <STR_LIT> ) = nullptr ; if ( <ISA_LIT>II :: isVPUInst ( MI -> getDesc ( ) ) ) { getAltOpcode = llvm :: <STR_LIT> ; } else if ( <ISA_LIT>II :: isSPUInst ( MI -> getDesc ( ) ) ) { getAltOpcode = llvm :: <STR_LIT> ; } else if ( <ISA_LIT>II :: isLoadInst ( MI -> getDesc ( ) ) ) { getAltOpcode = llvm :: <STR_LIT> ; } else if ( <ISA_LIT>II :: isStoreInst ( MI -> getDesc ( ) ) ) { getAltOpcode = llvm :: <STR_LIT> ; } else { return found ; } <STR_LIT> slots [ <NUM_LIT> ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; for ( int i = <NUM_LIT> ; i < <NUM_LIT> ; i


<s> if ( hw_before > <NUM_LIT> ) { unsigned int function_alignment ; int i ; asm_fprintf ( asm_out_file , <STR_LIT> <STR_LIT> , hw_before ) ; for ( i = <NUM_LIT> ; i < hw_before ; i ++ ) fputs ( <STR_LIT> , asm_out_file ) ; function_alignment = MAX ( <NUM_LIT> , DECL_ALIGN ( decl ) / BITS_PER_UNIT ) ; if ( ! DECL_USER_ALIGN ( decl ) ) function_alignment = MAX ( function_alignment , ( unsigned int ) align_functions ) ; fputs ( <STR_LIT> , asm_out_file ) ; ASM_OUTPUT_ALIGN ( asm_out_file , floor_log2 ( function_alignment ) ) ; } if ( S390_USE_TARGET_ATTRIBUTE && TARGET_DEBUG_ARG ) { asm_fprintf ( asm_out_file , <STR_LIT> , fname , s390_arch


<s> return nullptr ; } MCSubtargetInfo * X = create<ISA_LIT>MCSubtargetInfoImpl ( TT , CPUName , ArchFS ) ; if ( X -> getFeatureBits ( ) [ <STR_LIT> ] ) { llvm :: FeatureBitset Features = X -> getFeatureBits ( ) ; X -> setFeatureBits ( Features . set


<s> unsigned getSRetReturnReg ( ) const { return


<s> unsigned getReg ( ) const override { assert ( isReg ( ) &&


<s> if ( ( TARGET_PORTABLE_RUNTIME || ! TARGET_GAS || ! TARGET_SOM ) && ! IN_NAMED_SECTION_P (


<s> Imm >>= shift ; if ( ! isAdd ) Imm = - ( uint32_t ) Imm ; Imm &= <NUM_LIT> ; if ( isAdd ) Imm |= <NUM_LIT> ; assert ( Qm < <NUM_LIT> && <STR_LIT> ) ; return ( Qm << <NUM_LIT>


<s> static void ReplaceREADCYCLECOUNTER ( SDNode * N , SmallVectorImpl < SDValue > & Results , SelectionDAG & DAG , const <ISA_LIT>Subtarget * Subtarget ) { SDLoc DL ( N ) ; SDValue Cycles32 , OutChain ; if ( Subtarget -> hasPerfMon ( ) ) { SDValue Ops [ ] = { N -> getOperand ( <NUM_LIT> ) , DAG . getConstant ( <STR_LIT> , <STR_LIT> ) , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) } ; Cycles32 = DAG . getNode ( <STR_LIT> , DL , DAG . getVTList ( <STR_LIT> , <STR_LIT> ) , & Ops [ <NUM_LIT> ] , array_lengthof ( Ops ) ) ; OutChain = Cycles32 . getValue ( <NUM_LIT>


<s> } } if ( LD -> getAlignment ( ) == <NUM_LIT> ) { SDValue Low = DAG . getExtLoad ( <STR_LIT> , DL , <STR_LIT> , Chain , BasePtr , LD -> getPointerInfo ( ) , <STR_LIT> , LD -> isVolatile ( ) , LD -> isNonTemporal ( ) , LD -> isInvariant ( ) , <NUM_LIT> ) ; SDValue HighAddr = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , BasePtr , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; SDValue High = DAG . getExtLoad ( <STR_LIT> , DL , <STR_LIT> , Chain , HighAddr , LD -> getPointerInfo ( ) . getWithOffset ( <NUM_LIT> ) , <STR_LIT> , LD -> isVolatile ( ) , LD -> isNonTemporal ( ) , LD -> isInvariant ( ) , <NUM_LIT> ) ; SDValue HighShifted = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , High , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; SDValue Result = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Low , HighShifted ) ; Chain = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Low . getValue ( <NUM_LIT> ) , High . getValue ( <NUM_LIT> ) ) ; SDValue Ops [ ] = { Result , Chain } ; return DAG . getMergeValues ( Ops , DL ) ; } Type * IntPtrTy = getDataLayout ( ) -> getIntPtrType ( * DAG . getContext ( ) ) ; TargetLowering :: ArgListTy Args ; TargetLowering :: ArgListEntry Entry ; Entry . Ty = IntPtrTy ; Entry . Node = BasePtr ; Args . push_back ( Entry ) ; TargetLowering :: CallLoweringInfo CLI ( DAG ) ; CLI . setDebugLoc ( DL ) . setChain ( Chain ) . setCallee ( CallingConv :: C , IntPtrTy , DAG . getExternalSymbol ( <STR_LIT> , getPointerTy ( ) ) , std :: move ( Args ) , <NUM_LIT> ) ; std :: pair < SDValue , SDValue >


<s> rtx mcore_function_value ( tree valtype , tree func ATTRIBUTE_UNUSED ) { enum machine_mode mode ; int unsigned_p ; mode = TYPE_MODE ( valtype ) ; PROMOTE_MODE ( mode , unsigned_p , NULL ) ; return handle_structs_in_regs ( mode , valtype , FIRST_RET_REG


<s> OutStreamer -> emitCodeAlignment ( <NUM_LIT> , & getSubtargetInfo ( ) ) ; OutStreamer -> emitLabel ( CurSled ) ; unsigned OpCode = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; MCInst Ret ; Ret . setOpcode ( OpCode ) ; for ( auto & MO : drop_begin ( MI . operands ( ) ) ) if ( auto MaybeOperand = MCIL . LowerMachineOperand ( & MI , MO ) ) Ret . addOperand ( MaybeOperand . getValue ( ) ) ; OutStreamer -> emitInstruction ( Ret


<s> static_assert ( <STR_LIT> == <STR_LIT> + <NUM_LIT> , <STR_LIT> ) ; for ( unsigned R = <NUM_LIT> ; R < <NUM_LIT> ; ++ R ) markSuperRegs ( Reserved , <STR_LIT> + R ) ; } const TargetRegisterClass & RC = <STR_LIT> ; for ( unsigned Reg : RC ) for ( MCSubRegIterator SI ( Reg , this ) ; SI . isValid ( ) ; ++ SI ) if ( Reserved . test ( * SI ) ) markSuperRegs ( Reserved , Reg ) ; markSuperRegs ( Reserved , <STR_LIT> ) ; assert ( checkAllSuperRegsMarked ( Reserved ) ) ; return Reserved


<s> if ( V2 . isUndef ( ) ) V2 = V1 ; if ( SVN -> isSplat ( ) ) { int Lane = SVN -> getSplatIndex ( ) ; if ( Lane == - <NUM_LIT> ) Lane = <NUM_LIT> ; if ( Lane == <NUM_LIT> && V1 . getOpcode ( ) == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , dl , VT , V1 . getOperand ( <NUM_LIT> ) ) ; if ( Lane == <NUM_LIT> && V1 . getOpcode ( ) == <STR_LIT> && ! isa < ConstantSDNode > ( V1 . getOperand ( <NUM_LIT> ) ) ) { bool IsScalarToVector = true ; for ( unsigned i = <NUM_LIT> , e = V1 . getNumOperands ( ) ; i != e ; ++ i ) { if ( ! V1 . getOperand ( i ) .


<s> assert ( TargetRegisterInfo :: isPhysicalRegister ( RegNo ) && <STR_LIT> ) ; if ( R0AsZero && RegNo == <STR_LIT> ) { O << <STR_LIT> ; return ; } const char * RegName = getRegisterName ( RegNo ) ; if ( ! Subtarget . isDarwin ( ) )

RegName = stripRegisterPrefix ( RegName ) ;


<s> extern __inline __m128 __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) _mm_set_ps ( const float __Z , const float __Y , const float __X , const float __W ) { return __extension__ ( __m128 ) ( __v4sf ) {


<s> static tree ix86_stack_protect_fail ( void )


<s> const unsigned MinParameterSaveAreaSize = <NUM_LIT> * PtrByteSize ; const unsigned NumBytes = LinkageSize + MinParameterSaveAreaSize ; Chain = DAG . getCALLSEQ_START ( Chain , NumBytes , <NUM_LIT> , dl ) ; SDValue CallSeqStart = Chain ; SmallVector < std :: pair < unsigned , SDValue > , <NUM_LIT> > RegsToPass ; for ( CCValAssign & VA : ArgLocs ) { SDValue Arg = OutVals [ VA . getValNo ( ) ] ; switch ( VA . getLocInfo ( ) ) { default : report_fatal_error ( <STR_LIT> ) ; case CCValAssign :: Full : break ; case CCValAssign :: ZExt : Arg = DAG . getNode ( <STR_LIT> , dl , VA . getLocVT ( ) , Arg ) ; break ; case CCValAssign :: SExt : Arg = DAG . getNode ( <STR_LIT> , dl , VA . getLocVT ( ) , Arg ) ; break ; } if ( VA . isRegLoc ( ) ) RegsToPass . push_back ( std :: make_pair ( VA . getLocReg ( ) , Arg ) ) ; if ( VA . isMemLoc ( ) ) report_fatal_error ( <STR_LIT> <STR_LIT> ) ; } SDValue


<s> Type * Ty = I -> getType ( ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; if ( Ty -> getVectorNumElements ( ) != <NUM_LIT> || Ty -> getScalarSizeInBits ( ) != <NUM_LIT> ) return nullptr ; Value * Mask = I -> getArgOperand ( <NUM_LIT> ) ; if ( match ( Mask , m_One ( ) ) ) return Builder . CreateIntrinsic ( <STR_LIT> , { Ty , Ptr -> getType ( ) } , { Ptr , Builder . getInt32 ( <NUM_LIT> ) } ) ; else return Builder . CreateIntrinsic ( <STR_LIT> , { Ty , Ptr -> getType ( ) , Mask -> getType ( ) } , { Ptr , Builder . getInt32 ( <NUM_LIT> )


<s> if ( DestRC != SrcRC ) { if ( ( ( DestRC == <STR_LIT> ) && ( SrcRC == <STR_LIT> ) ) || ( ( SrcRC == <STR_LIT> ) && ( DestRC == <STR_LIT> ) ) ) { } else { return false ; } } if ( DestRC == <STR_LIT> ) { AddDefaultCC ( AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg ) ) ) ; } else if ( DestRC == <STR_LIT> ) { AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg ) ) ; } else if ( ( DestRC == <STR_LIT> ) || ( DestRC == <STR_LIT> ) ) { AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg (


<s> return std :: make_unique < <ISA_LIT>ELFObjectWriter


<s> return CheckImmRange ( <NUM_LIT> , <NUM_LIT> , false , false


<s> int Opc = I -> getOpcode ( ) ; if ( I -> isBranch ( ) ) { bool isCond = false ; unsigned Bits = <NUM_LIT> ; unsigned Scale = <NUM_LIT> ; int UOpc = Opc ; switch ( Opc ) { default : continue ; } unsigned MaxOffs = ( ( <NUM_LIT> << ( Bits - <NUM_LIT> ) ) - <NUM_LIT> ) * Scale ; ImmBranches . push_back ( ImmBranch ( I , MaxOffs , isCond , UOpc ) ) ; } if ( Opc == <STR_LIT> ) continue ; for ( unsigned op = <NUM_LIT> , e = I -> getNumOperands ( ) ; op != e ; ++ op ) if ( I -> getOperand ( op ) . isCPI ( ) ) { unsigned Bits = <NUM_LIT> ; unsigned Scale = <NUM_LIT> ; bool NegOk = false ; unsigned LongFormBits = <NUM_LIT> ; unsigned LongFormScale = <NUM_LIT> ; unsigned LongFormOpcode = <NUM_LIT> ; switch ( Opc ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : Bits = <NUM_LIT> ; Scale = <NUM_LIT> ; LongFormOpcode = <STR_LIT> ; break ; case <STR_LIT> : Bits = <NUM_LIT> ; Scale = <NUM_LIT> ; NegOk = true ; break ; } unsigned CPI = I -> getOperand ( op ) . getIndex ( ) ; MachineInstr * CPEMI = CPEMIs [ CPI ] ; unsigned MaxOffs = ( ( <NUM_LIT> << Bits ) - <NUM_LIT> ) * Scale ; unsigned LongFormMaxOffs = ( ( <NUM_LIT> << LongFormBits ) - <NUM_LIT>


<s> const MCSymbol * SB = & B -> getSymbol ( ) ; if ( ! SB -> getFragment ( ) ) Asm . getContext ( ) . reportFatalError ( Fixup . getLoc ( ) , <STR_LIT> + B -> getSymbol ( ) . getName ( ) + <STR_LIT> ) ; Type = MachO :: <ISA_LIT>_RELOC_SECTDIFF ; Value2 = Writer -> getSymbolAddress ( B -> getSymbol ( ) , Layout ) ; FixedValue -= Writer -> getSectionAddress ( SB -> getFragment ( ) -> getParent ( ) ) ; } if ( Type == MachO :: <ISA_LIT>_RELOC_SECTDIFF || Type == MachO :: <ISA_LIT>_RELOC_LOCAL_SECTDIFF ) { MachO :: any_relocation_info MRE ; MRE . r_word0 = ( ( <NUM_LIT> << <NUM_LIT> ) | ( MachO :: <ISA_LIT>_RELOC_PAIR << <NUM_LIT> ) | ( Log2Size << <NUM_LIT> ) | ( IsPCRel << <NUM_LIT> ) | MachO :: R_SCATTERED ) ; MRE . r_word1 = Value2 ; Writer -> addRelocation ( nullptr , Fragment -> getParent ( ) , MRE ) ; } MachO :: any_relocation_info MRE ; MRE . r_word0 = ( ( FixupOffset << <NUM_LIT> ) | ( Type << <NUM_LIT> ) | ( Log2Size << <NUM_LIT> ) | ( IsPCRel << <NUM_LIT> ) | MachO :: R_SCATTERED ) ; MRE . r_word1 =


<s> Ops . clear ( ) ; Ops . push_back ( Chain ) ; Ops . push_back ( Arg ) ; Ops . push_back ( PtrLo ) ; Ops . push_back ( PtrHi ) ; Ops . push_back ( DAG . getConstant ( StoreOffset , <STR_LIT> ) ) ; Ops . push_back ( InFlag ) ; StoreRet = DAG . getNode ( <STR_LIT> , dl , Tys , & Ops [ <NUM_LIT> ] , Ops . size ( ) ) ; Chain = getChain ( StoreRet ) ; InFlag = getOutFlag ( StoreRet ) ; ArgVT = Arg . getValueType ( ) ; Size = ArgVT . getSizeInBits ( ) ; Size = Size


<s> assert ( TBB && <STR_LIT> ) ; assert ( ( Cond . size ( ) == <NUM_LIT> || Cond . size ( ) == <NUM_LIT> ) && <STR_LIT> ) ; if ( Cond . empty ( ) ) { assert ( ! FBB && <STR_LIT> ) ; return <NUM_LIT> ; } unsigned Count = <NUM_LIT> ; ++ Count ; if ( FBB ) { ++ Count ; } return Count


<s> if ( Subtarget . useHVXOps ( ) ) { unsigned Action = getPreferredHvxVectorAction ( VT ) ; if ( Action != ~ <NUM_LIT> ) return static_cast < TargetLoweringBase :: LegalizeTypeAction > ( Action ) ; } if ( ElemTy == <STR_LIT> ) return TargetLoweringBase


<s> bool Res = SelectVOP3Mods0 ( In , Src , SrcMods , Clamp , Omod ) ; return Res && cast < ConstantSDNode > ( SrcMods ) -> isNullValue ( ) && cast < ConstantSDNode > ( Clamp ) -> isNullValue ( ) && cast <

ConstantSDNode > ( Omod ) -> isNullValue ( ) ;


<s> void <ISA_LIT>AsmParser :: expandMemInst ( MCInst & Inst , SMLoc IDLoc , MCStreamer & Out , const MCSubtargetInfo *


<s> Value = <STR_LIT> ( Value ) ; MovTy = isWide ? <STR_LIT> : <STR_LIT> ; } if ( isAdvSIMDModImm ) { SDLoc dl ( Op ) ; SDValue Mov = DAG . getNode ( NewOp , dl , MovTy , DAG . getConstant ( Value , dl , <STR_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Mov ) ; } } return SDValue ( )


<s> unsigned int startbit , endbit ; int intregs , intoffset ; if ( cum -> floats_in_gpr == <NUM_LIT> && ( cum -> intoffset % <NUM_LIT> == <NUM_LIT> || ( cum -> intoffset == - <NUM_LIT> && final ) ) ) { cum -> words ++ ; cum -> floats_in_gpr = <NUM_LIT> ; } if ( cum -> intoffset == - <NUM_LIT> ) return ; intoffset = cum -> intoffset ; cum -> intoffset = - <NUM_LIT> ; cum -> floats_in_gpr = <NUM_LIT> ; if ( intoffset % BITS_PER_WORD != <NUM_LIT> ) { unsigned int bits = BITS_PER_WORD - intoffset % BITS_PER_WORD ; if ( ! int_mode_for_size ( bits , <NUM_LIT> ) . exists ( ) ) { intoffset = ROUND_DOWN ( intoffset , BITS_PER_WORD ) ; } } startbit = ROUND_DOWN ( intoffset , BITS_PER_WORD ) ; endbit = ROUND_UP ( bitpos , BITS_PER_WORD ) ; intregs = ( endbit - startbit ) / BITS_PER_WORD ; cum -> words += intregs ; if ( ( unsigned ) cum -> words < ( endbit


<s> void LLVMInitialize<ISA_LIT>AsmParser ( ) { RegisterMCAsmParser < <ISA_LIT>AsmParser > X ( getThe<ISA_LIT>leTarget ( ) ) ; RegisterMCAsmParser < <ISA_LIT>AsmParser > Y ( getThe<ISA_LIT>beTarget (


<s> <ISA_LIT>Disassembler ( const MCSubtargetInfo &


<s> static void ia64_asm_unwind_emit ( FILE * out_file , rtx_insn * insn ) { bool unwind = ia64_except_unwind_info ( & global_options ) == UI_TARGET ; bool frame = dwarf2out_do_frame ( ) ; rtx note , pat ; bool handled_one ; if ( ! unwind && ! frame ) return ; if ( NOTE_INSN_BASIC_BLOCK_P ( insn ) ) { last_block = NOTE_BASIC_BLOCK ( insn ) -> next_bb == EXIT_BLOCK_PTR_FOR_FN ( cfun ) ; if ( need_copy_state ) { if ( unwind ) { fprintf ( out_file , <STR_LIT> ) ; fprintf ( out_file , <STR_LIT> , cfun -> machine -> state_num ) ; } need_copy_state = false ; } } if ( NOTE_P ( insn ) || ! RTX_FRAME_RELATED_P ( insn ) ) return ; if ( INSN_CODE ( insn ) == CODE_FOR_alloc ) { rtx dest = SET_DEST ( XVECEXP ( PATTERN ( insn ) , <NUM_LIT> , <NUM_LIT> ) ) ; int dest_regno = REGNO ( dest ) ; if ( dest_regno == current_frame_info . r [ reg_save_ar_pfs ] ) { if ( unwind ) fprintf ( out_file , <STR_LIT> , ia64_debugger_regno ( dest_regno ) ) ; } else { if ( current_frame_info . total_size == <NUM_LIT> && ! frame_pointer_needed ) process_epilogue ( out_file , insn , unwind , frame ) ; if ( unwind ) fprintf ( out_file , <STR_LIT> ) ; } return ; } handled_one = false ; for ( note = REG_NOTES ( insn ) ; note ; note = XEXP ( note , <NUM_LIT> ) ) switch ( REG_NOTE_KIND ( note ) ) { case REG_CFA_ADJUST_CFA : pat = XEXP ( note , <NUM_LIT> ) ; if ( pat == NULL ) pat = PATTERN ( insn ) ; process_cfa_adjust_cfa ( out_file , pat , insn , unwind , frame ) ; handled_one = true ; break ; case REG_CFA_OFFSET : pat = XEXP ( note , <NUM_LIT> ) ; if ( pat == NULL ) pat = PATTERN ( insn ) ; process_cfa_offset ( out_file , pat , unwind ) ; handled_one = true ; break ; case REG_CFA_REGISTER : pat = XEXP ( note , <NUM_LIT> ) ; if ( pat == NULL ) pat = PATTERN ( insn ) ; process_cfa_register ( out_file , pat ,


<s> EVT CCVT = getSetCCResultType ( DAG . getDataLayout ( ) , * DAG . getContext ( ) , VT ) ; SDValue FPZero = DAG . getConstantFP ( <NUM_LIT> , DL , VT ) ; return DAG . getSetCC ( DL , CCVT , Op ,


<s> clear ( RegisterRef ( i , LaneBitmask :: getAll ( ) ) ) ; } return * this ; } RegisterRef NR = PRI . normalize ( RR ) ; auto F = Masks . find ( NR . Reg ) ; if ( F == Masks . end ( ) ) return * this ; LaneBitmask NewM = F -> second & ~ NR . Mask ; if ( NewM . none ( ) ) Masks . erase ( F ) ; else F -> second =


<s> static MCInstPrinter * create<ISA_LIT>MCInstPrinter ( const Target & T , unsigned SyntaxVariant , const MCAsmInfo & MAI ,

const MCInstrInfo & MII , const MCRegisterInfo & MRI , const MCSubtargetInfo & STI ) {


<s> MCSymbolRefExpr :: VariantKind Kind ; const MCSymbol * Symbol ; switch ( MO . getTargetFlags ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; } switch ( MOTy ) { case MachineOperand :: MO_GlobalAddress : break ; default : llvm_unreachable (


<s> gimple * g = gimple_build_assign ( lhs , cmp ) ; gimple_set_location ( g , gimple_location ( stmt ) ) ; gsi_replace ( gsi , g ,


<s> switch ( Kind ) { case k_Token : O << <STR_LIT> << getToken ( ) << <STR_LIT> ; break ; case k_Register : O << <STR_LIT> << getReg ( ) ; break ; case k_Immediate : O << <STR_LIT> << * getImm ( ) << <STR_LIT> ; break ; case k_Memri :


<s> AU . addRequired < MachineLoopInfo > (


<s> return <NUM_LIT> ; } unsigned CPI = CPEMI -> getOperand ( <NUM_LIT> ) . getIndex ( ) ; std :: vector < CPEntry > & CPEs = CPEntries [ CPI ] ; for ( unsigned i = <NUM_LIT> , e = CPEs . size ( ) ; i != e ; ++ i ) { if ( CPEs [ i ] . CPEMI == CPEMI ) continue ; if ( CPEs [ i ] . CPEMI == NULL ) continue ; if ( CPEIsInRange ( UserMI , UserOffset , CPEs [ i ] . CPEMI , U . MaxDisp , U . NegOk ) ) { DOUT << <STR_LIT> << CPI << <STR_LIT> << CPEs [ i ] . CPI << <STR_LIT> ; U . CPEMI = CPEs [ i ] . CPEMI ; for ( unsigned j = <NUM_LIT> , e = UserMI -> getNumOperands ( ) ; j != e ; ++ j ) if ( UserMI -> getOperand ( j ) . isCPI ( ) ) { UserMI -> getOperand ( j ) . setIndex ( CPEs [ i ] . CPI ) ; break ; } CPEs [ i ] . RefCount ++ ; return DecrementOldEntry ( CPI , CPEMI ) ? <NUM_LIT> : <NUM_LIT> ; } } return <NUM_LIT>


<s> } x = gen_rtx_CONST_VECTOR ( imode , gen_rtvec_v ( nelt , perm ) ) ; x = expand_vec_perm ( vmode , op0 , op1 , x , target ) ; if ( x != target ) emit_move_insn (


<s> I . eraseFromParent ( ) ; return true ; } Register HiReg = MRI -> createVirtualRegister ( & RegRC ) ; Register LoReg = MRI -> createVirtualRegister ( & RegRC ) ; BuildMI ( * BB , & I , DL , TII . get ( <STR_LIT> ) , LoReg ) . addReg ( SrcReg , <NUM_LIT> , <STR_LIT> ) ; BuildMI ( * BB , & I , DL , TII . get ( <STR_LIT> ) , HiReg ) . addReg ( SrcReg , <NUM_LIT> , <STR_LIT> ) ; Register MaskedLo , MaskedHi ; if ( CanCopyLow32 ) { MaskedLo = LoReg ; } else { Register MaskLo = MRI -> createVirtualRegister ( & RegRC ) ; MaskedLo = MRI -> createVirtualRegister ( & RegRC ) ; BuildMI ( * BB , & I , DL , TII . get ( <STR_LIT> ) , MaskLo ) . addReg ( MaskReg , <NUM_LIT> , <STR_LIT> ) ; BuildMI ( * BB , & I , DL , TII . get ( NewOpc ) , MaskedLo ) . addReg ( LoReg ) . addReg ( MaskLo ) ; } if ( CanCopyHi32 ) { MaskedHi = HiReg ; } else { Register MaskHi = MRI -> createVirtualRegister ( & RegRC ) ; MaskedHi = MRI -> createVirtualRegister ( & RegRC ) ; BuildMI ( * BB , & I , DL , TII . get ( <STR_LIT> ) , MaskHi ) . addReg ( MaskReg , <NUM_LIT> , <STR_LIT> ) ; BuildMI ( * BB , & I , DL , TII . get ( NewOpc ) , MaskedHi ) . addReg ( HiReg ) . addReg ( MaskHi ) ; } BuildMI ( * BB , & I , DL , TII . get ( <STR_LIT> ) , DstReg ) . addReg ( MaskedLo ) . addImm ( <STR_LIT> ) . addReg ( MaskedHi ) . addImm ( <STR_LIT> ) ; I . eraseFromParent (


<s> break ; case CCValAssign :: ZExt : Arg = DAG . getNode ( <STR_LIT> , dl , VA . getLocVT ( ) , Arg ) ; break ; case CCValAssign :: AExt : Arg = DAG . getNode ( <STR_LIT> , dl , VA . getLocVT ( ) , Arg ) ; break ; } if ( VA . isRegLoc ( ) ) { RegsToPass . push_back ( std :: make_pair ( VA . getLocReg ( ) , Arg ) ) ; } else { assert ( VA . isMemLoc ( ) ) ; if ( StackPtr . getNode ( ) == <NUM_LIT> ) StackPtr = DAG . getCopyFromReg ( Chain , dl , <STR_LIT> , <STR_LIT> ) ; SDValue PtrOff = DAG . getNode ( <STR_LIT> , dl , getPointerTy ( ) , StackPtr , DAG . getIntPtrConstant ( VA . getLocMemOffset ( ) ) ) ; MemOpChains . push_back ( DAG . getStore ( Chain , dl , Arg , PtrOff , MachinePointerInfo ( ) , false , false , <NUM_LIT> ) ) ; } } if ( ! MemOpChains . empty ( ) ) Chain = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , & MemOpChains [ <NUM_LIT> ] , MemOpChains . size ( ) ) ; SDValue InFlag ; for ( unsigned i = <NUM_LIT> , e = RegsToPass . size ( ) ; i != e ; ++ i ) { Chain = DAG . getCopyToReg ( Chain , dl , RegsToPass [ i ] . first , RegsToPass [ i ] . second ,


<s> EVT VT = LHS . getValueType ( ) ; SDLoc DL ( Op ) ; SDValue NotA = notValue ( DAG , DL , VT , LHS ) ; SDValue NotB = notValue ( DAG , DL , VT , RHS ) ; SDValue Or = DAG . getNode ( <STR_LIT> , DL , VT , NotA ,


<s> if ( landBlk == NULL ) { errs ( ) << <STR_LIT> ; } else { errs ( ) << <STR_LIT> << landBlk -> getNumber ( ) ; } errs ( ) << <STR_LIT> ; } int oldOpcode = branchInstr -> getOpcode ( ) ; DebugLoc branchDL = branchInstr -> getDebugLoc ( ) ; typename BlockT :: iterator branchInstrPos = CFGTraits :: getInstrPos ( curBlk , branchInstr ) ; CFGTraits :: insertCondBranchBefore ( branchInstrPos , CFGTraits :: getBranchNzeroOpcode ( oldOpcode ) , passRep , branchDL ) ; if ( trueBlk ) { curBlk -> splice ( branchInstrPos , trueBlk , trueBlk -> begin ( ) , trueBlk -> end ( ) ) ; curBlk -> removeSuccessor ( trueBlk ) ; if ( landBlk && trueBlk -> succ_size ( ) != <NUM_LIT> ) { trueBlk -> removeSuccessor ( landBlk ) ; } retireBlock ( curBlk , trueBlk ) ; } CFGTraits :: insertInstrBefore ( branchInstrPos , AMDGPU :: ELSE , passRep ) ; if ( falseBlk ) { curBlk -> splice ( branchInstrPos , falseBlk , falseBlk -> begin ( ) , falseBlk -> end ( ) ) ; curBlk -> removeSuccessor ( falseBlk ) ; if ( landBlk && falseBlk -> succ_size ( ) != <NUM_LIT> ) { falseBlk -> removeSuccessor ( landBlk ) ; } retireBlock ( curBlk , falseBlk ) ; } CFGTraits :: insertInstrBefore ( branchInstrPos , AMDGPU :: ENDIF


<s> MCSymbolXCOFF * FSym = cast < MCSymbolXCOFF > ( getSymbol ( F ) ) ; if ( ! FSym -> hasContainingCsect ( ) ) { MCSectionXCOFF * Csect = cast < MCSectionXCOFF > ( F -> isDeclaration ( ) ? getObjFileLowering ( ) . getSectionForExternalReference ( F , TM ) : getObjFileLowering ( ) . getSectionForFunctionDescriptor ( FSym ) ) ; FSym -> setContainingCsect


<s> const std :: vector < AttributeList > & Attrs = VE . getAttributeLists ( ) ; if ( Attrs . empty ( ) ) return ; Stream . EnterSubblock ( bitc :: PARAMATTR_BLOCK_ID , <NUM_LIT> ) ; SmallVector < uint64_t , <NUM_LIT> > Record ; for ( unsigned i = <NUM_LIT> , e = Attrs . size ( ) ; i != e ; ++ i ) { AttributeList AL = Attrs [ i ] ; for ( unsigned i : AL . indexes ( ) ) { AttributeSet AS = AL . getAttributes ( i ) ; if ( AS . hasAttributes ( ) ) Record . push_back ( VE . getAttributeGroupID ( { i , AS } ) ) ; } Stream . EmitRecord ( bitc :: PARAMATTR_CODE_ENTRY , Record ) ; Record . clear


<s> return ( vector unsigned short ) __builtin_altivec_vmuleub ( ( vector signed char ) a1 , (


<s> unsigned CCReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; MachineBasicBlock * MBB = MI -> getParent ( ) ; MachineInstr * BMI = & MBB -> back ( ) ; bool NeedSplit = ( BMI != MI ) || ! BBHasFallthrough ( MBB ) ; ++ NumCBrFixed ; if ( BMI != MI ) { if ( llvm :: next ( MachineBasicBlock :: iterator ( MI ) ) == prior ( MBB -> end ( ) ) && BMI -> getOpcode ( ) == Br . UncondBr ) { MachineBasicBlock * NewDest = BMI -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; if ( isBBInRange ( MI , NewDest , Br . MaxDisp ) ) { DEBUG ( dbgs ( ) << <STR_LIT> << * BMI ) ; BMI -> getOperand ( <NUM_LIT> ) . setMBB ( DestBB ) ; MI -> getOperand ( <NUM_LIT> ) . setMBB ( NewDest ) ; MI -> getOperand ( <NUM_LIT> ) . setImm ( CC ) ; return true ; } } } if ( NeedSplit ) { splitBlockBeforeInstr ( MI ) ; int delta = TII -> GetInstSizeInBytes ( & MBB -> back ( ) ) ; BBInfo [ MBB -> getNumber ( ) ] . Size -= delta ; MBB -> back ( ) . eraseFromParent ( ) ; } MachineBasicBlock * NextBB = llvm :: next ( MachineFunction :: iterator ( MBB ) ) ; DEBUG ( dbgs ( ) << <STR_LIT> << DestBB -> getNumber ( ) << <STR_LIT> << NextBB -> getNumber ( ) << <STR_LIT> ) ; BuildMI ( MBB , DebugLoc ( ) , TII -> get ( MI -> getOpcode ( ) ) ) . addMBB ( NextBB ) . addImm ( CC ) . addReg ( CCReg ) ; Br . MI = & MBB


<s> <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; if ( handleAttr ( Parent , Callee , <STR_LIT> ) ) NeedQueuePtr = true ; for ( StringRef AttrName : AttrNames ) handleAttr ( Parent ,


<s> return ! MF . getFrameInfo ( ) . hasVarSizedObjects ( ) && ! MF . getInfo

< <ISA_LIT>MachineFunctionInfo > ( ) -> getHasPushSequences ( ) ;


<s> case <STR_LIT> : case <STR_LIT> : return false ; case <STR_LIT> : if ( simpleCC ) * simpleCC = <STR_LIT> ; if ( reverseCC ) * reverseCC = <STR_LIT> ; return true ; case <STR_LIT> : if ( simpleCC ) * simpleCC = <STR_LIT> ; if ( reverseCC ) * reverseCC = <STR_LIT> ; return true ; case <STR_LIT> : if ( simpleCC ) * simpleCC = <STR_LIT> ; if ( reverseCC ) * reverseCC =


<s> SDValue Hi = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Scalar , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; return splatPartsI64WithVL ( DL , VT , Lo , Hi


<s> assert ( ( Cond . size ( ) && Cond . size ( ) <= <NUM_LIT> ) && <STR_LIT> ) ; Cond [ <NUM_LIT> ] . setImm ( GetOppositeBranchOpc ( Cond [ <NUM_LIT> ] . getImm ( ) ) ) ; return false


<s> auto & S = getStreamer ( ) ; WinEH :: FrameInfo * CurFrame = S . EnsureValidWinFrameInfo ( SMLoc ( ) ) ; if ( ! CurFrame ) return ; MCSymbol * Label = S . emitCFILabel ( ) ; CurFrame -> PrologEnd = Label ; WinEH :: Instruction Inst = WinEH :: Instruction ( Win64EH :: UOP_End , nullptr , - <NUM_LIT> , <NUM_LIT> ) ; auto it = CurFrame -> Instructions . begin ( ) ; CurFrame -> Instructions . insert ( it ,


<s> __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT> ( b


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; case <STR_LIT> : return MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; case <STR_LIT> : case <STR_LIT> : { unsigned Size = getInlineAsmLength ( MI . getOperand ( <NUM_LIT> ) . getSymbolName ( ) , * MAI ) ; if ( ! MF -> getInfo < <ISA_LIT>FunctionInfo > ( ) -> isThumbFunction ( ) ) Size


<s> IntelExprState CurrState = State ; switch ( State ) { default : State = IES_ERROR ; break ; case IES_INTEGER : case IES_RPAREN : case IES_REGISTER


<s> } return Default ( ) ; } if ( Shl_0 . getOpcode ( ) == <STR_LIT> ) { SDValue Sub_0 = Shl_0 . getOperand ( <NUM_LIT> ) ; SDValue Sub_1 = Shl_0 . getOperand ( <NUM_LIT> ) ; if ( ConstantSDNode * C1 = dyn_cast < ConstantSDNode > ( Sub_0 ) ) { if ( C1 -> getSExtValue ( ) != <NUM_LIT> || Sub_1 . getOpcode ( ) != <STR_LIT> ) return Default ( ) ; SDValue Shl2_0 = Sub_1 . getOperand ( <NUM_LIT> ) ; SDValue Shl2_1 = Sub_1 . getOperand ( <NUM_LIT> ) ; if ( ConstantSDNode * C2 = dyn_cast < ConstantSDNode > ( Shl2_1 ) ) { int32_t ValConst = <NUM_LIT> << ( ShlConst + C2 -> getSExtValue ( ) ) ; if ( isInt < <NUM_LIT> > ( - ValConst ) ) { SDValue Val = CurDAG -> getTargetConstant ( - ValConst , dl , <STR_LIT> ) ; SDNode * Result = CurDAG -> getMachineNode ( <STR_LIT> ,


<s> for ( auto & Op : I -> operands ( ) ) { if ( Op . isReg ( ) ) RecalcRegs . insert ( Op . getReg ( ) ) ; } auto Next = std :: next ( I ) ; LIS -> RemoveMachineInstrFromMaps ( * I ) ; I -> eraseFromParent ( ) ; I = Next ; Changed = true ; } if ( I != E ) continue ; for ( auto * Pred : CurBB -> predecessors ( ) ) { if ( Pred -> succ_size ( ) == <NUM_LIT> ) Blocks . push_back ( Pred ) ; } } continue ; } auto Lead = MBB . begin ( ) , E = MBB . end ( ) ; if ( MBB . succ_size ( ) != <NUM_LIT> || Lead == E || ! isEndCF ( * Lead , TRI ) ) continue ; const MachineBasicBlock * Succ = * MBB . succ_begin ( ) ; if ( ! MBB . isLayoutSuccessor ( Succ ) ) continue ; auto I = std :: next ( Lead ) ; for ( ; I != E ; ++ I ) if ( ! TII -> isSALU ( * I ) || I -> readsRegister ( <STR_LIT> , TRI ) ) break ; if ( I != E ) continue ; const auto NextLead = Succ -> begin ( ) ; if ( NextLead == Succ -> end ( ) || ! isEndCF ( * NextLead , TRI ) || ! getOrExecSource ( * NextLead , * TII , MRI ) ) continue ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * Lead << '\n' ) ; auto SaveExec = getOrExecSource ( * Lead , * TII , MRI ) ; unsigned SaveExecReg = getOrNonExecReg ( *


<s> MCSection * <ISA_LIT>ElfTargetObjectFile :: getExplicitSectionGlobal ( const GlobalObject * GO , SectionKind SK , const TargetMachine & TM ) const { if ( isExecuteOnlyFunction ( GO , SK , TM ) ) SK = SectionKind :: getExecuteOnly ( ) ; return TargetLoweringObjectFileELF :: getExplicitSectionGlobal ( GO , SK ,


<s> return ( REG_P ( exp ) && VALID_AVX256_REG_OR_OI_MODE ( GET_MODE ( exp


<s> const MCFixupKindInfo & getFixupKindInfo ( MCFixupKind Kind ) const { const static MCFixupKindInfo Infos [ <STR_LIT> ] = { { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT>

, MCFixupKindInfo :: FKF_IsPCRel } , } ;


<s> OperandMatchResultTy <ISA_LIT>AsmParser :: parseSymbolicOrNumericFormat ( int64_t & Format ) { using namespace llvm :: <STR_LIT> ; if ( ! trySkipId ( <STR_LIT> , AsmToken :: Colon ) ) return MatchOperand_NoMatch ; if ( trySkipToken ( AsmToken :: LBrac ) ) { StringRef FormatStr ; SMLoc Loc = getLoc ( ) ; if ( ! parseId ( FormatStr , <STR_LIT> ) ) return MatchOperand_ParseFail ; auto Res = parseSymbolicUnifiedFormat ( FormatStr , Loc , Format ) ; if ( Res == MatchOperand_NoMatch ) Res = parseSymbolicSplitFormat ( FormatStr , Loc , Format ) ; if ( Res != MatchOperand_Success ) return Res ; if ( ! skipToken ( AsmToken :: RBrac , <STR_LIT> ) ) return MatchOperand_ParseFail ; return MatchOperand_Success


<s> case <NUM_LIT> : if ( Subtarget . isTarget64BitLP64 ( ) ) return & <STR_LIT> ; return & <STR_LIT> ; case <NUM_LIT> : if ( Subtarget . isTarget64BitLP64 ( ) ) return & <STR_LIT> ; return & <STR_LIT> ; case <NUM_LIT> : if ( Subtarget . isTargetWin64 ( ) ) return & <STR_LIT> ; else if ( Subtarget . is64Bit ( ) ) return & <STR_LIT> ; const Function * F = MF .


<s> const TargetRegisterInfo & RI = * TM . getRegisterInfo ( ) ; unsigned stackReg = RI . getFrameRegister ( * MF ) ; unsigned returnReg = RI . getRARegister ( ) ; unsigned stackSize = MF -> getFrameInfo ( ) -> getStackSize ( ) ; if ( OutStreamer . hasRawTextSupport ( ) ) OutStreamer . EmitRawText ( <STR_LIT> + StringRef ( <ISA_LIT>InstPrinter :: getRegisterName ( stackReg ) ) . lower ( ) + <STR_LIT>

+ Twine ( stackSize ) + <STR_LIT> + StringRef ( <ISA_LIT>InstPrinter :: getRegisterName ( returnReg ) ) . lower ( ) ) ;


<s> OpNum = <NUM_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; OpNum = <NUM_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; OpNum = <NUM_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; OpNum = <NUM_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; OpNum = <NUM_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; OpNum = <NUM_LIT> ; break ; default : return false ; } auto IsDead = [ this ] ( NodeAddr < DefNode * > DA ) -> bool { return getDeadNodes ( ) . count ( DA . Id ) ; } ; NodeList Defs ; MachineOperand & Op = MI . getOperand ( OpNum ) ; for ( NodeAddr < DefNode * > DA : IA . Addr -> members_if ( DFG . IsDef , DFG ) ) { if ( & DA . Addr -> getOp ( ) != & Op ) continue ; Defs = DFG . getRelatedRefs ( IA , DA ) ; if ( ! llvm :: all_of ( Defs , IsDead ) ) return false ; break ; } for ( auto D : Defs ) Remove . insert ( D . Id ) ; if ( trace ( ) ) dbgs ( ) << <STR_LIT> << MI ; MI . setDesc ( HII . get ( NewOpc ) ) ; MI . getOperand ( OpNum + <NUM_LIT> ) . setImm ( <NUM_LIT> ) ; removeOperand ( IA , OpNum ) ; if ( trace ( ) ) dbgs ( ) << <STR_LIT> << MI ; return


<s> return supportedVectorShiftWithImm ( VT , Subtarget ,


<s> return new <ISA_LIT>Disassembler ( STI , Ctx , T . createMCInstrInfo (


<s> Inst . addOperand ( MCOperand :: createImm ( Value ==


<s> else return <STR_LIT> ; } else { if ( TARGET_BIG_ENDIAN ) return <STR_LIT> ; else return <STR_LIT> ; } } if ( INTVAL ( in0_idx0 ) != INTVAL ( in0_idx1 ) && INTVAL ( in1_idx0 ) != INTVAL ( in1_idx1 ) ) { if ( INTVAL ( in0_idx0 ) == <NUM_LIT> ) { if ( TARGET_BIG_ENDIAN ) return <STR_LIT> ; else return <STR_LIT> ; } else { if ( TARGET_BIG_ENDIAN ) return <STR_LIT> ; else return <STR_LIT> ; } } gcc_unreachable ( ) ; return <STR_LIT>


<s> Instruction * ArgInGlobal = new AddrSpaceCastInst ( Arg , PointerType :: get ( Arg -> getType ( ) -> getPointerElementType ( ) , ADDRESS_SPACE_GLOBAL ) , Arg -> getName ( ) , FirstInst ) ; Value * ArgInGeneric = new AddrSpaceCastInst ( ArgInGlobal , Arg -> getType ( ) , Arg -> getName ( ) , FirstInst ) ; Arg -> replaceAllUsesWith


<s> extern __inline __m128i __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) _mm_slli_epi64 ( __m128i __A , int __B ) { __v2du lshift ; __v2di result = { <NUM_LIT> , <NUM_LIT> } ; if ( __B >= <NUM_LIT> && __B < <NUM_LIT> ) { if ( __builtin_constant_p ( __B ) && __B < <NUM_LIT> ) lshift = ( __v2du ) vec_splat_s32 ( __B ) ; else lshift = ( __v2du ) vec_splats ( ( unsigned int ) __B ) ; result = vec_sl ( ( __v2di ) __A , lshift ) ; } return ( __m128i


<s> unsigned Opc = MI -> getOpcode ( ) ; unsigned PredOpc = HII -> getCondOpcode ( Opc , ! Cond ) ; MachineInstrBuilder MB = BuildMI ( B , Where , DL , HII -> get ( PredOpc ) ) ; unsigned Ox = <NUM_LIT> , NP = MI -> getNumOperands ( ) ; while ( Ox < NP ) { MachineOperand & MO = MI -> getOperand ( Ox ) ; if ( ! MO . isReg ( ) || ! MO . isDef ( ) ) break ; Ox ++ ; } MB . addReg ( DefOp . getReg ( ) , getRegState ( DefOp ) , DefOp . getSubReg ( ) ) ; MB . addReg ( PredOp . getReg ( ) , PredOp . isUndef ( ) ? RegState :: Undef : <NUM_LIT> , PredOp . getSubReg ( ) ) ; while ( Ox < NP ) { MachineOperand & MO = MI -> getOperand ( Ox ) ; if ( ! MO . isReg ( ) || ! MO . isImplicit ( ) ) MB . addOperand ( MO ) ; Ox ++ ; } MachineFunction & MF = * B . getParent ( ) ; MachineInstr :: mmo_iterator I = MI -> memoperands_begin ( ) ; unsigned NR = std :: distance ( I , MI -> memoperands_end ( ) ) ; MachineInstr :: mmo_iterator MemRefs = MF . allocateMemRefsArray ( NR ) ; for ( unsigned i = <NUM_LIT> ; i < NR ; ++ i ) MemRefs [ i ] = * I ++ ; MB . setMemRefs ( MemRefs , MemRefs + NR ) ; MachineInstr * NewI = MB ; NewI -> clearKillInfo ( ) ; LIS -> InsertMachineInstrInMaps ( * NewI ) ; for ( auto & Op : NewI -> operands ( ) ) if ( Op . isReg ( ) ) UpdRegs .


<s> } ; const auto & Users = P -> users ( ) ; const auto & Operands = P -> operands ( ) ; if ( ! std :: all_of ( Users . begin ( ) , Users . end ( ) , IsValidUser ) || ! std :: all_of ( Operands . begin ( ) , Operands . end ( ) , IsValidOperand ) ) ToRemove . push_back ( P ) ; } auto IsPromotable = [ & Promotable ] ( const Value * V ) -> bool { const PHINode * Phi = dyn_cast < PHINode > ( V ) ; return ! Phi || Promotable . count ( Phi ) ; } ; while ( ! ToRemove . empty ( )


<s> const char * reg_frame = reg_names [ FRAME_POINTER_REGNUM ] ; const char * reg_sspslot = reg_names [ SOFTSTACK_SLOT_REGNUM ] ; const char * reg_sspprev = reg_names [ SOFTSTACK_PREV_REGNUM ] ; fprintf ( file , <STR_LIT> , bits , reg_stack ) ; fprintf ( file , <STR_LIT> , bits , reg_frame ) ; fprintf ( file , <STR_LIT> , bits , reg_sspslot ) ; fprintf ( file , <STR_LIT> , bits , reg_sspprev ) ; fprintf ( file , <STR_LIT> ) ; fprintf ( file , <STR_LIT> ) ; fprintf ( file , <STR_LIT> , bits ) ; fprintf ( file , <STR_LIT> , bits ) ; fprintf ( file , <STR_LIT> ) ; fprintf ( file , <STR_LIT> , bits == <NUM_LIT> ? <STR_LIT> : <STR_LIT> , bits / <NUM_LIT> ) ; fprintf ( file , <STR_LIT> , bits ) ; fprintf ( file , <STR_LIT> , bits , reg_sspslot ) ; fprintf ( file , <STR_LIT> , bits , reg_sspprev , reg_sspslot ) ; fprintf ( file , <STR_LIT> HOST_WIDE_INT_PRINT_DEC <STR_LIT> , bits , reg_frame , reg_sspprev , size ) ; if ( alignment > keep_align ) fprintf ( file , <STR_LIT> , bits , reg_frame , reg_frame , - alignment ) ; size = crtl -> outgoing_args_size ; gcc_assert ( size % keep_align == <NUM_LIT> ) ; fprintf ( file , <STR_LIT> HOST_WIDE_INT_PRINT_DEC <STR_LIT> , bits , reg_stack , reg_frame , size ) ; if ( ! crtl -> is_leaf ) fprintf ( file , <STR_LIT> , bits , reg_sspslot , reg_stack ) ; fprintf ( file


<s> if ( ! SI . isUnordered ( ) ) return false ; return ExperimentalUnorderedISEL


<s> DebugLoc dl = Op . getDebugLoc ( ) ; SDValue V ( <NUM_LIT> , <NUM_LIT> ) ; bool First = true ; for ( unsigned i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) { bool ThisIsNonZero = ( NonZeros & ( <NUM_LIT> << i ) ) != <NUM_LIT> ; if ( ThisIsNonZero && First ) { if ( NumZero ) V = getZeroVector ( <STR_LIT> , true , DAG , dl ) ; else V = DAG . getUNDEF ( <STR_LIT> ) ; First = false ; } if ( ( i & <NUM_LIT> ) != <NUM_LIT> ) { SDValue ThisElt ( <NUM_LIT> , <NUM_LIT> ) , LastElt ( <NUM_LIT> , <NUM_LIT> ) ; bool LastIsNonZero = ( NonZeros & ( <NUM_LIT> << ( i - <NUM_LIT> ) ) ) != <NUM_LIT> ; if ( LastIsNonZero ) { LastElt = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( i - <NUM_LIT> ) ) ; } if ( ThisIsNonZero ) { ThisElt = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( i ) ) ; ThisElt = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , ThisElt , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; if ( LastIsNonZero ) ThisElt = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , ThisElt , LastElt ) ; } else ThisElt = LastElt ; if ( ThisElt . getNode ( ) ) V = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , V , ThisElt , DAG . getIntPtrConstant ( i / <NUM_LIT> ) ) ; } } return DAG . getNode ( <STR_LIT> , dl , <STR_LIT>


<s> SDValue Src = N -> getOperand ( <NUM_LIT> ) ; if ( Src . getOpcode ( ) == <STR_LIT> && ! VT . isVector ( ) ) { SDValue Vec = Src . getOperand ( <NUM_LIT> ) ; if ( Vec . getOpcode ( ) == <STR_LIT> ) { SDValue Elt0 = Vec . getOperand ( <NUM_LIT> ) ; EVT EltVT = Elt0 . getValueType ( ) ; if ( VT . getFixedSizeInBits ( ) <= EltVT . getFixedSizeInBits ( ) ) { if ( EltVT . isFloatingPoint ( ) ) { Elt0 = DAG . getNode ( <STR_LIT> , SL , EltVT . changeTypeToInteger ( ) , Elt0 ) ; } return DAG . getNode ( <STR_LIT> , SL , VT , Elt0 ) ; } } } if ( Src . getOpcode ( ) == <STR_LIT> && ! VT . isVector ( ) ) { if ( auto K = isConstOrConstSplat ( Src . getOperand ( <NUM_LIT> ) ) ) { if ( <NUM_LIT> * K -> getZExtValue ( ) == Src . getValueType ( ) . getScalarSizeInBits ( ) ) { SDValue BV = stripBitcast ( Src . getOperand ( <NUM_LIT> ) ) ; if ( BV . getOpcode ( ) == <STR_LIT> && BV . getValueType ( ) . getVectorNumElements ( ) == <NUM_LIT> ) { SDValue SrcElt = BV . getOperand ( <NUM_LIT> ) ; EVT SrcEltVT = SrcElt . getValueType ( ) ; if ( SrcEltVT . isFloatingPoint ( ) ) { SrcElt = DAG . getNode ( <STR_LIT> , SL , SrcEltVT . changeTypeToInteger ( ) , SrcElt ) ; } return DAG . getNode ( <STR_LIT> , SL , VT , SrcElt ) ; } } } } if ( VT . getScalarSizeInBits ( ) < <NUM_LIT> ) { EVT SrcVT = Src . getValueType ( ) ; if ( SrcVT . getScalarSizeInBits ( ) > <NUM_LIT> && ( Src . getOpcode ( ) == <STR_LIT> || Src . getOpcode ( ) == <STR_LIT> || Src . getOpcode ( ) == <STR_LIT> ) ) { SDValue Amt = Src . getOperand (


<s> bool isGFX9Plus ( const MCSubtargetInfo & STI ) { return isGFX9 ( STI ) || isGFX10


<s> in_section = NULL ; fputs ( <STR_LIT> , stream ) ; assemble_name ( stream , funname ) ; fputs ( <STR_LIT> , stream ) ; ASM_OUTPUT_LABEL ( stream , funname ) ; fprintf ( stream , <STR_LIT> ) ; assemble_name ( stream , funname ) ; fprintf ( stream , <STR_LIT> , alpha_procedure_type == PT_STACK ? <STR_LIT> : alpha_procedure_type == PT_REGISTER ? <STR_LIT> : <STR_LIT> ) ; if ( cfun -> machine


<s> return getSTI ( ) . getFeatureBits ( ) [


<s> return ( vec_lvsr ( a , ( unsigned char


<s> if ( IsTailCall ) ++ NumTailCalls ; unsigned StackAlignment = TFL -> getStackAlignment ( ) ; NextStackOffset = RoundUpToAlignment ( NextStackOffset , StackAlignment ) ; SDValue NextStackOffsetVal = DAG . getIntPtrConstant ( NextStackOffset , true ) ; if ( ! IsTailCall ) Chain = DAG . getCALLSEQ_START ( Chain , NextStackOffsetVal , DL ) ; SDValue StackPtr = DAG . getCopyFromReg ( Chain , DL , Subtarget . isABI_N64 ( ) ? <STR_LIT> : <STR_LIT> , getPointerTy ( ) ) ; std :: deque < std :: pair < unsigned , SDValue > > RegsToPass ; SmallVector < SDValue , <NUM_LIT> > MemOpChains ; <STR_LIT> ByValArg = <ISA_LIT>CCInfo . byval_begin ( ) ; for ( unsigned i = <NUM_LIT> , e = ArgLocs . size ( ) ; i != e ; ++ i ) { SDValue Arg = OutVals [ i ] ; CCValAssign & VA = ArgLocs [ i ] ; MVT ValVT = VA . getValVT ( ) , LocVT = VA . getLocVT ( ) ; <STR_LIT> Flags = Outs [ i ] . Flags ; if ( Flags . isByVal ( ) ) { assert ( Flags . getByValSize ( ) && <STR_LIT> ) ; assert ( ByValArg != <ISA_LIT>CCInfo . byval_end ( ) ) ; assert ( ! IsTailCall && <STR_LIT> ) ; passByValArg ( Chain , DL , RegsToPass , MemOpChains , StackPtr , MFI , DAG , Arg , <ISA_LIT>CCInfo , * ByValArg , Flags , Subtarget . isLittle ( ) ) ; ++ ByValArg ; continue ; } switch ( VA . getLocInfo ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case CCValAssign :: Full : if ( VA . isRegLoc ( ) ) { if ( ( ValVT == <STR_LIT> && LocVT == <STR_LIT> ) || ( ValVT == <STR_LIT> && LocVT == <STR_LIT> ) || ( ValVT == <STR_LIT> && LocVT == <STR_LIT> ) ) Arg = DAG . getNode ( <STR_LIT> , DL , LocVT , Arg ) ; else if ( ValVT == <STR_LIT> && LocVT == <STR_LIT> ) { SDValue Lo = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Arg , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Arg , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; if ( ! Subtarget . isLittle ( ) ) std :: swap ( Lo , Hi ) ; unsigned LocRegLo = VA . getLocReg ( ) ; unsigned LocRegHigh = getNextIntArgReg ( LocRegLo ) ; RegsToPass . push_back ( std :: make_pair ( LocRegLo , Lo ) ) ; RegsToPass . push_back ( std :: make_pair ( LocRegHigh , Hi ) ) ; continue ; } } break ; case CCValAssign :: SExt : Arg = DAG . getNode ( <STR_LIT> , DL , LocVT , Arg ) ; break ; case CCValAssign ::


<s> switch ( RC -> getSize ( ) ) { case <NUM_LIT> : LoadOp = <STR_LIT> ; break ; case <NUM_LIT> : LoadOp = <STR_LIT> ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { LoadOp = <STR_LIT> ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { LoadOp = <STR_LIT> ; } else if ( RC -> hasType ( <STR_LIT> ) || RC -> hasType ( <STR_LIT> ) || RC -> hasType ( <STR_LIT> ) ) { switch ( RC -> getSize ( ) ) { case <NUM_LIT> : LoadOp = <STR_LIT> ; break ; case <NUM_LIT> : LoadOp = <STR_LIT> ; break ; case <NUM_LIT> : LoadOp = <STR_LIT> ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } } else { if ( <STR_LIT> . hasSubClassEq ( RC ) ) LoadOp = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) LoadOp = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) LoadOp = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) LoadOp = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) LoadOp = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) LoadOp = <STR_LIT> ; else llvm_unreachable ( <STR_LIT> ) ; MachineInstrBuilder NewMI = BuildMI ( MBB , MBBI , DL , get ( LoadOp ) , DestReg ) ; NewMI . addFrameIndex ( FrameIdx ) . addMemOperand ( MMO


<s> OutStreamer -> EmitIntValue ( ELF :: GNU_PROPERTY_<ISA_LIT>_FEATURE_1_AND , <NUM_LIT> ) ; OutStreamer -> EmitIntValue ( WordSize , <NUM_LIT> ) ; OutStreamer -> EmitIntValue ( FeatureFlagsAnd , WordSize ) ; EmitAlignment ( WordSize == <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ) ; OutStreamer -> endSection ( Nt ) ; OutStreamer -> SwitchSection ( Cur ) ; } } if ( TT . isOSBinFormatMachO ( ) ) OutStreamer -> SwitchSection ( getObjFileLowering ( ) . getTextSection ( ) ) ; if ( TT . isOSBinFormatCOFF ( ) ) { MCSymbol * S = MMI -> getContext ( ) . getOrCreateSymbol ( StringRef ( <STR_LIT> ) ) ; OutStreamer -> BeginCOFFSymbolDef ( S ) ; OutStreamer -> EmitCOFFSymbolStorageClass ( COFF :: IMAGE_SYM_CLASS_STATIC ) ; OutStreamer -> EmitCOFFSymbolType ( COFF :: IMAGE_SYM_DTYPE_NULL ) ; OutStreamer -> EndCOFFSymbolDef ( ) ; int64_t Feat00Flags = <NUM_LIT> ; if ( TT . getArch ( ) == Triple :: x86 ) { Feat00Flags |= <NUM_LIT> ; } if ( M . getModuleFlag ( <STR_LIT> ) ) Feat00Flags


<s> RTVEC_ELT ( p , offset ++ ) = gen_rtx_CLOBBER ( VOIDmode , gen_rtx_REG ( Pmode , use_reg ) ) ; RTVEC_ELT ( p , offset ++ ) = gen_rtx_USE ( VOIDmode , gen_rtx_REG ( Pmode , <NUM_LIT> ) ) ; } else RTVEC_ELT ( p , offset ++ ) = gen_rtx_USE ( VOIDmode , gen_rtx_REG ( Pmode , use_reg ) ) ; for ( i = <NUM_LIT> ; i < end_reg - start_reg ; i ++ ) RTVEC_ELT ( p , i + offset ) = gen_frame_set ( gen_rtx_REG ( reg_mode , start_reg + i ) , frame_reg_rtx , save_area_offset + reg_size * i , ( sel & SAVRES_SAVE ) != <NUM_LIT> ) ; if ( ( sel & SAVRES_SAVE ) && ( sel & SAVRES_LR ) ) RTVEC_ELT ( p , i + offset ) = gen_frame_store ( gen_rtx_REG ( Pmode , <NUM_LIT> ) , frame_reg_rtx , lr_offset ) ; par = gen_rtx_PARALLEL ( VOIDmode ,


<s> DEBUG ( dbgs ( ) << <STR_LIT> << MBBI . getNumber ( ) << <STR_LIT> << MBB -> getNumber ( ) << <STR_LIT> ) ; } FallthroughMap [ & MBBI ]


<s> if ( ( early_op = arm_find_shift_sub_rtx ( op ) ) ) return ! reg_overlap_mentioned_p ( value , early_op ) ; return


<s> unsigned <ISA_LIT>MCInstrInfo :: slotsConsumed ( MCInstrInfo const & MCII , MCSubtargetInfo const & STI , MCInst const & MCI ) { unsigned slotsUsed =


<s> bool <ISA_LIT>FixFunctionBitcasts :: runOnModule ( Module & M ) { Modified = false


<s> SDValue Flag = EmitCMP ( LHS , RHS , TargetCC , CC , dl , DAG ) ; return DAG . getNode ( <STR_LIT> , dl , Op . getValueType ( ) , Chain , Dest


<s> RegisterMCAsmInfo < <ISA_LIT>MCAsmInfo > X ( The<ISA_LIT>Target ) ; TargetRegistry :: RegisterMCCodeGenInfo ( The<ISA_LIT>Target , create<ISA_LIT>MCCodeGenInfo ) ; TargetRegistry :: RegisterMCInstrInfo ( The<ISA_LIT>Target , create<ISA_LIT>MCInstrInfo ) ; TargetRegistry :: RegisterMCRegInfo ( The<ISA_LIT>Target , create<ISA_LIT>MCRegisterInfo ) ; TargetRegistry :: RegisterMCSubtargetInfo ( The<ISA_LIT>Target ,


<s> } else if ( hasMovingSP ) { assert ( RegInfo -> hasBasePointer ( MF ) && <STR_LIT> ) ; if ( AFI -> isThumb2Function ( ) ) { if ( FPOffset >= - <NUM_LIT> && FPOffset < <NUM_LIT> ) { FrameReg = RegInfo -> getFrameRegister ( MF ) ; return FPOffset ; } } } else if ( AFI -> isThumbFunction ( ) ) { if ( Offset >= <NUM_LIT> && ( Offset & <NUM_LIT> ) == <NUM_LIT> && Offset <= <NUM_LIT> ) return Offset ; if ( AFI -> isThumb2Function ( ) && FPOffset >= - <NUM_LIT> && FPOffset < <NUM_LIT> ) { FrameReg = RegInfo -> getFrameRegister ( MF ) ; return FPOffset ; } } else if ( Offset > ( FPOffset < <NUM_LIT> ? - FPOffset : FPOffset ) ) { FrameReg = RegInfo -> getFrameRegister


<s> if ( E == VMEM_ACCESS ) return VM_CNT ; if ( WaitEventMaskForInst [ LGKM_CNT ] & ( <NUM_LIT> << E ) ) return LGKM_CNT ; assert ( WaitEventMaskForInst [ EXP_CNT ] & (


<s> void ReplaceCallInst ( CallInst & I , FunctionType * FT , const char * Name , unsigned SrcSelect [ <NUM_LIT> ] , Value * Offset [ <NUM_LIT> ] , Value * Resource , Value * Sampler , unsigned CT [ <NUM_LIT> ] , Value * Coord ) { IRBuilder < > Builder ( & I ) ; Constant * Mask [ ] = { ConstantInt :: get ( Int32Type , SrcSelect [ <NUM_LIT> ] ) , ConstantInt :: get ( Int32Type , SrcSelect [ <NUM_LIT> ] ) , ConstantInt :: get ( Int32Type , SrcSelect [ <NUM_LIT> ] ) , ConstantInt :: get ( Int32Type , SrcSelect [ <NUM_LIT> ] ) } ; Value * SwizzleMask = ConstantVector :: get ( Mask ) ; Value * SwizzledCoord = Builder . CreateShuffleVector ( Coord , Coord , SwizzleMask ) ; Value * Args [ ] = { SwizzledCoord , Offset [ <NUM_LIT> ] , Offset [ <NUM_LIT> ] , Offset [ <NUM_LIT> ] , Resource , Sampler , ConstantInt :: get ( Int32Type , CT [ <NUM_LIT> ] ) , ConstantInt :: get ( Int32Type , CT [ <NUM_LIT> ] ) , ConstantInt :: get ( Int32Type , CT [ <NUM_LIT> ] ) , ConstantInt :: get ( Int32Type , CT [ <NUM_LIT> ] ) } ; Function * F = Mod -> getFunction ( Name ) ; if ( ! F ) { F = Function :: Create ( FT , GlobalValue :: ExternalLinkage , Name , Mod ) ; F -> addFnAttr (


<s> } } MVT LaneVT = <STR_LIT> ( VT . isFloatingPoint ( ) ? <STR_LIT> : <STR_LIT> , VT . getSizeInBits ( ) / <NUM_LIT> ) ; SmallVector < int , <NUM_LIT> > LaneMask ; LaneMask . resize ( NumLanes * <NUM_LIT> , - <NUM_LIT> ) ; for ( int i = <NUM_LIT> ; i < NumLanes ; ++ i ) if ( Lanes [ i ] >= <NUM_LIT> ) { LaneMask [ <NUM_LIT> * i + <NUM_LIT> ] = <NUM_LIT> * Lanes [ i ] + <NUM_LIT> ; LaneMask [ <NUM_LIT> * i + <NUM_LIT> ] = <NUM_LIT> * Lanes [ i ] + <NUM_LIT> ; } V1 = DAG . getBitcast ( LaneVT , V1 ) ; V2 = DAG . getBitcast ( LaneVT , V2 ) ; SDValue LaneShuffle = DAG . getVectorShuffle ( LaneVT , DL , V1 , V2 , LaneMask ) ; LaneShuffle = DAG . getBitcast ( VT , LaneShuffle


<s> SDLoc dl ( Op ) ; int CompareOpc ; bool isDot ; if ( ! getVectorCompareInfo ( Op , CompareOpc , isDot , Subtarget ) ) return SDValue ( ) ; if ( ! isDot ) { SDValue Tmp = DAG . getNode ( <STR_LIT> , dl , Op . getOperand ( <NUM_LIT> ) . getValueType ( ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , DAG . getConstant ( CompareOpc , dl , <STR_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , dl , Op . getValueType ( ) , Tmp ) ; } SDValue Ops [ ] = { Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , DAG . getConstant ( CompareOpc , dl , <STR_LIT> ) } ; EVT VTs [ ] = { Op . getOperand ( <NUM_LIT>


<s> Error ( S , <STR_LIT> ) ; return false ; } else if ( Strict && ( msgRequiresOp ( Msg . Id ) != Op . IsDefined ) ) { Error ( S , Op . IsDefined ? <STR_LIT> : <STR_LIT> ) ; return false ; } else if ( ! isValidMsgOp ( Msg . Id , Op . Id , Strict ) ) { Error ( S , <STR_LIT> ) ; return


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Value = insn & UINT64_C ( <NUM_LIT> ) ; DecodeIntRegsRegisterClass ( MI , Value , <NUM_LIT> , nullptr ) ; Value = ( insn >> <NUM_LIT> ) & UINT64_C ( <NUM_LIT> ) ; DecodePredRegsRegisterClass ( MI , Value , <NUM_LIT> , nullptr ) ; Value = ( insn >> <NUM_LIT> ) & UINT64_C ( <NUM_LIT> ) ; Value |= ( insn >> <NUM_LIT> ) & UINT64_C ( <NUM_LIT> ) ; MI . addOperand ( MCOperand :: createImm ( Value ) ) ; break ; case ( <STR_LIT> ) : ++ shift ; case <STR_LIT> : case <STR_LIT> : ++ shift ; case <STR_LIT> : case <STR_LIT> : Value |= insn & UINT64_C ( <NUM_LIT> ) ; DecodeIntRegsRegisterClass ( MI , Value , <NUM_LIT> , nullptr ) ; Value = ( insn >> <NUM_LIT> ) & UINT64_C ( <NUM_LIT> ) ; Value |= ( insn >> <NUM_LIT> ) & UINT64_C ( <NUM_LIT> ) ; Value |= ( insn >> <NUM_LIT> ) & UINT64_C ( <NUM_LIT> ) ; MI . addOperand ( MCOperand :: createImm ( Value << shift ) ) ; break ; case <STR_LIT> : Value = insn & UINT64_C ( <NUM_LIT> ) ; DecodeDoubleRegsRegisterClass ( MI , Value , <NUM_LIT> , nullptr ) ; Value = ( insn >> <NUM_LIT> ) & UINT64_C ( <NUM_LIT> ) ; Value |= ( insn >> <NUM_LIT> ) & UINT64_C ( <NUM_LIT> ) ; Value |= ( insn >> <NUM_LIT> ) & UINT64_C ( <NUM_LIT> ) ; MI . addOperand ( MCOperand :: createImm ( Value << <NUM_LIT> ) ) ; break ; case <STR_LIT> : Value = ( insn >> <NUM_LIT> ) & UINT64_C ( <NUM_LIT> ) ; Value |= ( insn >> <NUM_LIT> ) & UINT64_C ( <NUM_LIT> ) ; Value |= ( insn >> <NUM_LIT> ) & UINT64_C ( <NUM_LIT> ) ; Value |= insn & UINT64_C ( <NUM_LIT> ) ; MI . addOperand ( MCOperand :: createImm ( Value << <NUM_LIT> ) ) ; Value = ( insn >> <NUM_LIT> ) & UINT64_C ( <NUM_LIT> ) ; DecodeDoubleRegsRegisterClass ( MI , Value , <NUM_LIT> , nullptr ) ; break ; case <STR_LIT> : ++ shift ; case <STR_LIT> : ++ shift ; case <STR_LIT> : Value = ( insn >> <NUM_LIT> ) & UINT64_C ( <NUM_LIT> ) ; Value |= ( insn >> <NUM_LIT> ) & UINT64_C ( <NUM_LIT> ) ; Value |= ( insn >> <NUM_LIT> ) & UINT64_C ( <NUM_LIT> ) ; Value |= insn & UINT64_C ( <NUM_LIT> ) ; MI . addOperand ( MCOperand :: createImm ( Value << shift ) ) ; Value = ( insn >> <NUM_LIT> ) & UINT64_C ( <NUM_LIT> ) ; DecodeIntRegsRegisterClass ( MI , Value , <NUM_LIT> ,


<s> const uint8_t * THMToTHMStub :: getContent ( )


<s> vmvn_p8 ( poly8x8_t __a ) { return ( poly8x8_t ) ~ ( (


<s> } else { unsigned Align = FrameInfo -> getObjectAlignment ( Index ) ; unsigned Size = FrameInfo -> getObjectSize ( Index ) ; MachinePointerInfo PtrInfo = MachinePointerInfo :: getFixedStack ( * MF , Index ) ; MachineMemOperand * MMO = MF -> getMachineMemOperand ( PtrInfo , MachineMemOperand :: MOLoad , Size , Align ) ; BuildMI ( * MBB , MI , DL , TII -> get ( <STR_LIT> ) , TmpReg ) . addFrameIndex ( Index ) . addReg ( MFI -> getScratchRSrcReg ( ) ) . addReg ( MFI -> getScratchWaveOffsetReg ( ) ) . addImm ( i * <NUM_LIT> ) . addMemOperand ( MMO ) ; BuildMI ( * MBB , MI , DL , TII -> get ( <STR_LIT> ) , SubReg ) . addReg ( TmpReg , RegState :: Kill ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) , RegState :: ImplicitDefine ) ; } } MI -> eraseFromParent ( ) ; break ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : buildScratchLoadStore ( MI , <STR_LIT> , TII -> getNamedOperand ( * MI , <STR_LIT> :: src ) -> getReg ( ) , TII -> getNamedOperand ( * MI , <STR_LIT> :: scratch_rsrc ) -> getReg ( ) , TII -> getNamedOperand ( * MI , <STR_LIT> :: scratch_offset ) -> getReg ( ) , FrameInfo -> getObjectOffset ( Index ) + TII -> getNamedOperand ( * MI , <STR_LIT> :: offset ) -> getImm ( ) , RS ) ; MI -> eraseFromParent ( ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { buildScratchLoadStore ( MI , <STR_LIT> , TII -> getNamedOperand ( * MI , <STR_LIT> :: dst ) -> getReg ( ) , TII -> getNamedOperand ( * MI , <STR_LIT> :: scratch_rsrc ) -> getReg ( ) , TII -> getNamedOperand ( * MI , <STR_LIT> :: scratch_offset ) -> getReg ( ) , FrameInfo -> getObjectOffset ( Index ) + TII -> getNamedOperand ( * MI , <STR_LIT> :: offset ) -> getImm ( ) , RS ) ; MI -> eraseFromParent ( ) ; break ; } default : { int64_t Offset = FrameInfo -> getObjectOffset ( Index ) ; FIOp . ChangeToImmediate ( Offset ) ; if ( ! TII -> isImmOperandLegal ( MI , FIOperandNum


<s> } if ( delayHasHazard ( * CurrI , RegDU , IM ) ) continue ; const <ISA_LIT>Subtarget & STI = MBB . getParent ( ) -> getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( STI . isTargetNaCl ( ) ) { unsigned AddrIdx ; if ( ( isBasePlusOffsetMemoryAccess ( CurrI -> getOpcode ( ) , & AddrIdx ) && baseRegNeedsLoadStoreMask ( CurrI -> getOperand ( AddrIdx ) . getReg ( ) ) ) || CurrI -> modifiesRegister ( <STR_LIT> , STI . getRegisterInfo ( ) ) ) continue ; } bool InMicro<ISA_LIT>Mode = STI


<s> if ( strcmp ( name , <STR_LIT> ) == <NUM_LIT> ) return <STR_LIT> ; if ( strcmp ( name , <STR_LIT> ) == <NUM_LIT> ) return <STR_LIT> ; if ( strcmp ( name , <STR_LIT> ) == <NUM_LIT> ) return <STR_LIT> ; if ( strcmp ( name , <STR_LIT> ) == <NUM_LIT> ) return <STR_LIT> ; return name


<s> return ( __m256bh ) __builtin_ia32_cvtneps2bf16_v16sf_mask ( __C ,


<s> unsigned VReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Writemask = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned BitsSet = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) BitsSet += Writemask & ( <NUM_LIT> << i ) ? <NUM_LIT> : <NUM_LIT> ; const TargetRegisterClass * RC ; switch ( BitsSet ) { default : return ; case <NUM_LIT> : RC = & AMDGPU :: VReg_32RegClass ; break ; case <NUM_LIT> : RC = & AMDGPU :: VReg_64RegClass ; break ; case <NUM_LIT> : RC = & AMDGPU :: VReg_96RegClass ; break ; } unsigned NewOpcode = TII -> getMaskedMIMGOp ( MI -> getOpcode ( ) , BitsSet ) ; MI -> setDesc ( TII -> get (


<s> bool selectBDXAddr12Pair ( SDValue Addr , SDValue & Base , SDValue


<s> bool <ISA_LIT>TargetLowering :: isHWFalseValue ( SDValue Op ) const { if ( ConstantFPSDNode * CFP = dyn_cast < ConstantFPSDNode > ( Op ) ) { return CFP -> getValueAPF ( ) . isZero ( ) ; } if ( ConstantSDNode * C = dyn_cast < ConstantSDNode >


<s> bundle_pos ++ ; } if ( GET_CODE ( insn ) != CODE_LABEL ) b = bundle + INTVAL ( XVECEXP ( pat , <NUM_LIT> , <NUM_LIT> ) ) ; else b = <NUM_LIT> ; bundle_pos = <NUM_LIT> ; continue ; } else if ( GET_CODE ( pat ) == UNSPEC_VOLATILE && XINT ( pat , <NUM_LIT> ) == <NUM_LIT> ) { int t = INTVAL ( XVECEXP ( pat , <NUM_LIT> , <NUM_LIT> ) ) ; if ( b ) while ( bundle_pos < t ) { emit_insn_before ( gen_nop_type ( b -> t [ bundle_pos ] ) , insn ) ; bundle_pos ++ ; } continue ; } if ( bundle_pos == <NUM_LIT> ) b = <NUM_LIT> ; if ( b && INSN_P ( insn ) ) { t = ia64_safe_type


<s> if ( GET_MODE ( dest ) == DImode ) emit_insn ( gen_isel_cc_di ( dest , cmp , src_t ,


<s> ExitMBB -> splice ( ExitMBB -> begin ( ) , & MBB , std :: next ( MI . getIterator ( ) ) , MBB . end ( ) ) ; ExitMBB -> transferSuccessorsAndUpdatePHIs ( & MBB ) ; MBB . addSuccessor ( LoopCmpMBB ) ; MachineBasicBlock * CurrentMBB = LoopCmpMBB ; BuildMI ( CurrentMBB , DL , LL , Old ) . addReg ( RA ) . addReg ( RB ) ; BuildMI ( CurrentMBB , DL , TII -> get ( <STR_LIT> ) , ScratchLo ) . addReg ( OldLo ) . addReg ( CmpLo ) ; BuildMI ( CurrentMBB , DL , TII -> get ( <STR_LIT> ) , ScratchHi ) . addReg ( OldHi ) . addReg ( CmpHi ) ; BuildMI ( CurrentMBB , DL , TII -> get ( <STR_LIT> ) , ScratchLo ) . addReg ( ScratchLo ) . addReg ( ScratchHi ) ; BuildMI ( CurrentMBB , DL , TII -> get ( <STR_LIT> ) ) . addImm ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addMBB ( CmpFailMBB ) ; CurrentMBB -> addSuccessor ( CmpSuccMBB ) ; CurrentMBB -> addSuccessor ( CmpFailMBB ) ; CurrentMBB = CmpSuccMBB ; PairedCopy ( TII , * CurrentMBB , CurrentMBB -> end ( ) , DL , ScratchHi , ScratchLo , NewHi , NewLo ) ; BuildMI ( CurrentMBB , DL , SC ) . addReg ( Scratch ) . addReg ( RA ) . addReg ( RB ) ; BuildMI ( CurrentMBB , DL , TII -> get ( <STR_LIT> ) ) . addImm ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addMBB ( LoopCmpMBB ) ; BuildMI ( CurrentMBB , DL , TII -> get ( <STR_LIT> ) ) . addMBB ( ExitMBB ) ; CurrentMBB -> addSuccessor ( LoopCmpMBB ) ; CurrentMBB -> addSuccessor ( ExitMBB ) ; CurrentMBB = CmpFailMBB ; BuildMI ( CurrentMBB , DL , SC ) . addReg ( Old ) . addReg ( RA ) . addReg ( RB ) ; CurrentMBB -> addSuccessor ( ExitMBB ) ; recomputeLiveIns ( * LoopCmpMBB )


<s> const <ISA_LIT>TargetMachine & TM = static_cast < const <ISA_LIT>TargetMachine & > ( getTargetMachine ( ) ) ; if ( ASC -> getSrcAddressSpace ( ) == <ISA_LIT>AS :: FLAT_ADDRESS ) { unsigned DestAS = ASC -> getDestAddressSpace ( ) ; if ( DestAS == <ISA_LIT>AS :: LOCAL_ADDRESS || DestAS == <ISA_LIT>AS :: PRIVATE_ADDRESS ) { unsigned NullVal = TM . getNullPointerValue ( DestAS ) ; SDValue SegmentNullPtr = DAG . getConstant ( NullVal , SL , <STR_LIT> ) ; SDValue NonNull = DAG . getSetCC ( SL , <STR_LIT> , Src , FlatNullPtr , <STR_LIT> ) ; SDValue Ptr = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Src ) ; return DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , NonNull , Ptr , SegmentNullPtr ) ; } } if ( ASC -> getDestAddressSpace ( )


<s> unsigned DstReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( TargetRegisterInfo :: isPhysicalRegister ( DstReg ) ) { assert ( I . isCopy ( ) && <STR_LIT> ) ; return true ; } const RegisterBank & RegBank = * RBI . getRegBank ( DstReg , MRI , TRI ) ; const unsigned DstSize = MRI . getType ( DstReg ) . getSizeInBits ( ) ; unsigned SrcReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; const unsigned SrcSize = RBI . getSizeInBits ( SrcReg , MRI , TRI ) ; assert ( ( ! TargetRegisterInfo :: isPhysicalRegister ( SrcReg ) || I . isCopy ( ) ) && <STR_LIT> ) ; assert ( ( DstSize == SrcSize || ( TargetRegisterInfo :: isPhysicalRegister ( SrcReg ) && DstSize <= RBI . getSizeInBits ( SrcReg ,


<s> bool hasWorkGroupIDY ( ) const { return WorkGroupIDY