<s> return <ISA_LIT>Operand :: CreateImm ( this , <NUM_LIT> , SMLoc ( ) ,


<s> unsigned Flags = MCA . getELFHeaderEFlags ( ) ; Flags |= ELF :: EF_MIPS_MICROMIPS ; MCA . setELFHeaderEFlags (


<s> virtual const TargetFrameLowering * getFrameLowering ( ) const { return &


<s> for ( MachineBasicBlock :: iterator I = MBB . begin ( ) , E = MBB . end ( ) ; I != E ; ++ I ) { MachineInstr & MI = * I ; switch ( MI . getOpcode ( ) ) { default : continue ; case <STR_LIT> : { if ( ! TargetRegisterInfo :: isVirtualRegister ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ) continue ; const TargetRegisterClass * SrcRC , * DstRC ; std :: tie ( SrcRC , DstRC ) = getCopyRegClasses ( MI , * TRI , MRI ) ; if ( isVGPRToSGPRCopy ( SrcRC , DstRC , * TRI ) ) { DEBUG ( dbgs ( ) << <STR_LIT> << MI ) ; TII -> moveToVALU ( MI ) ; } break ; } case <STR_LIT> : { DEBUG ( dbgs ( ) << <STR_LIT> << MI ) ; unsigned Reg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( ! TRI -> isSGPRClass ( MRI . getRegClass ( Reg ) ) ) break ; bool SGPRBranch = false ; bool HasBreakDef = false ; for ( unsigned i = <NUM_LIT> ; i < MI . getNumOperands ( ) ; i += <NUM_LIT> ) { unsigned Reg = MI . getOperand ( i ) . getReg ( ) ; if ( TRI -> hasVGPRs ( MRI . getRegClass ( Reg ) ) ) { TII -> moveToVALU ( MI ) ; break ; } MachineInstr * DefInstr = MRI . getUniqueVRegDef ( Reg ) ; assert ( DefInstr ) ; switch ( DefInstr -> getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> Type * ArgTy = VT . getTypeForEVT ( * DAG . getContext ( ) ) ; unsigned ArgSize = DAG . getDataLayout ( ) . getTypeAllocSize ( ArgTy ) ; if ( VT . isInteger ( ) && ! VT . isVector ( ) ) ArgSize = std :: max ( ArgSize , MinSlotSize ) ; bool NeedFPTrunc = false ; if ( VT . isFloatingPoint ( ) && ! VT . isVector ( ) && VT != <STR_LIT> ) { ArgSize = <NUM_LIT> ; NeedFPTrunc = true ; } SDValue VANext = DAG . getNode ( <STR_LIT> , DL , PtrVT , VAList , DAG . getConstant ( ArgSize , DL , PtrVT ) ) ; VANext = DAG . getZExtOrTrunc ( VANext , DL , PtrMemVT ) ; SDValue APStore = DAG . getStore ( Chain , DL , VANext , Addr , MachinePointerInfo ( V ) ) ; if ( NeedFPTrunc ) { SDValue WideFP = DAG . getLoad ( <STR_LIT> , DL , APStore , VAList , MachinePointerInfo ( ) ) ; SDValue NarrowFP = DAG . getNode ( <STR_LIT> , DL , VT , WideFP . getValue ( <NUM_LIT> ) , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; SDValue Ops [ ] = { NarrowFP , WideFP


<s> APInt DemandedElts = APInt :: getAllOnes ( VT . getVectorNumElements ( ) ) ; if ( TLI . SimplifyDemandedVectorElts ( SDValue ( N , <NUM_LIT> ) , DemandedElts ,

KnownUndef , KnownZero , DCI ) ) return SDValue ( N , <NUM_LIT> ) ;


<s> SchedImpl -> initialize ( this ) ; DEBUG ( unsigned maxH = <NUM_LIT> ; for ( unsigned su = <NUM_LIT> , e = SUnits . size ( ) ; su != e ; ++ su ) if ( SUnits [ su ] . getHeight ( ) > maxH ) maxH = SUnits [ su ] . getHeight ( ) ; dbgs ( ) << <STR_LIT> << maxH << <STR_LIT> ; ) ; DEBUG ( unsigned maxD = <NUM_LIT> ; for ( unsigned su = <NUM_LIT> , e = SUnits . size ( ) ; su != e ; ++ su ) if ( SUnits [ su ] . getDepth ( ) > maxD ) maxD = SUnits [ su ] . getDepth ( ) ; dbgs ( ) << <STR_LIT> << maxD << <STR_LIT> ; ) ; DEBUG ( for ( unsigned su = <NUM_LIT> , e = SUnits . size ( ) ; su != e ; ++ su ) SUnits [ su ] . dumpAll ( this ) ) ; initQueues ( TopRoots , BotRoots ) ; bool IsTopNode = false ; while ( true ) { DEBUG ( dbgs ( ) << <STR_LIT> ) ; SUnit * SU = SchedImpl -> pickNode ( IsTopNode ) ; if ( ! SU


<s> void <ISA_LIT>InstrInfo :: loadRegFromStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , unsigned DestReg , int FrameIdx , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { MachineFunction & MF = * MBB . getParent ( ) ; SmallVector < MachineInstr * , <NUM_LIT> > NewMIs ; DebugLoc DL ; if ( MI != MBB . end ( ) ) DL = MI -> getDebugLoc ( ) ; LoadRegFromStackSlot ( MF , DL , DestReg , FrameIdx , RC , NewMIs ) ; for ( unsigned i = <NUM_LIT> , e = NewMIs . size ( ) ; i != e ; ++ i ) MBB . insert ( MI , NewMIs [ i ] ) ; const MachineFrameInfo & MFI = * MF


<s> if ( TyAlign > <NUM_LIT> ) return TyAlign ; return <NUM_LIT> ; } unsigned Align = <NUM_LIT> ; if ( Subtarget -> hasSSE1 ( ) ) getMaxByValAlign ( Ty ,


<s> ConstantSDNode * ConstOpOrElement = isConstOrConstSplat ( N -> getOperand ( <NUM_LIT> ) ) ; if ( ! ConstOpOrElement ) return SDValue ( ) ; if ( DAG . getMachineFunction ( ) . getFunction ( ) . hasMinSize ( ) && isOperationLegal ( <STR_LIT> , N -> getValueType ( <NUM_LIT> ) ) ) return SDValue ( ) ; auto IsProfitable = [ this ] ( bool IsNeg , bool IsAddOne , EVT VT ) -> bool { switch ( this -> Subtarget . getCPUDirective ( ) ) { default : return false ; case <STR_LIT> : return true ; case <STR_LIT> : case <STR_LIT> : return IsAddOne && IsNeg ? VT . isVector ( ) : true ; } } ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; SDLoc DL ( N ) ; const APInt & MulAmt = ConstOpOrElement -> getAPIntValue ( ) ; bool IsNeg = MulAmt . isNegative ( ) ; APInt MulAmtAbs = MulAmt . abs ( ) ; if ( ( MulAmtAbs - <NUM_LIT> ) . isPowerOf2 ( ) ) { if ( ! IsProfitable ( IsNeg , true , VT ) ) return SDValue ( ) ; SDValue Op0 = N -> getOperand ( <NUM_LIT> ) ; SDValue Op1 = DAG . getNode ( <STR_LIT> , DL , VT , N -> getOperand ( <NUM_LIT> ) , DAG . getConstant ( ( MulAmtAbs - <NUM_LIT> ) . logBase2 ( ) , DL , VT ) ) ; SDValue Res = DAG . getNode ( <STR_LIT> , DL , VT , Op0 , Op1 ) ; if ( ! IsNeg ) return Res ; return DAG . getNode ( <STR_LIT> , DL , VT , DAG . getConstant ( <NUM_LIT> , DL , VT ) , Res ) ; } else if ( ( MulAmtAbs + <NUM_LIT> ) . isPowerOf2 ( ) ) { if ( ! IsProfitable ( IsNeg , false , VT ) ) return SDValue ( ) ; SDValue Op0 = N -> getOperand ( <NUM_LIT> ) ; SDValue Op1 = DAG . getNode ( <STR_LIT> , DL , VT , N -> getOperand ( <NUM_LIT> ) , DAG . getConstant ( ( MulAmtAbs + <NUM_LIT>


<s> vst1q_f64 ( float64_t * a , float64x2_t b ) { __builtin_aarch64_st1v2df ( ( __builtin_aarch64_simd_df * ) a ,


<s> return LowerSTATEPOINT ( OutStreamer , SM , * MI , Subtarget -> is64Bit ( ) , TM , getSubtargetInfo ( ) , MCInstLowering ) ; case TargetOpcode :: STACKMAP : return LowerSTACKMAP ( OutStreamer , SM , * MI , Subtarget -> is64Bit ( ) , getSubtargetInfo ( ) ) ; case TargetOpcode :: PATCHPOINT : return LowerPATCHPOINT ( OutStreamer , SM , * MI , Subtarget -> is64Bit ( ) , getSubtargetInfo ( ) ) ; case <STR_LIT> : EmitToStreamer ( OutStreamer , MCInstBuilder ( getRetOpcode ( * Subtarget ) ) ) ; return ; case <STR_LIT> : EmitToStreamer ( OutStreamer , MCInstBuilder ( getRetOpcode ( * Subtarget ) ) ) ; EmitToStreamer ( OutStreamer , MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) ) ; return ; case <STR_LIT> : OutStreamer . EmitWinCFIPushReg ( RI -> getSEHRegNum ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ) ; return ; case <STR_LIT> : OutStreamer . EmitWinCFISaveReg ( RI -> getSEHRegNum ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) , MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; return ; case <STR_LIT> : OutStreamer . EmitWinCFISaveXMM ( RI -> getSEHRegNum ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) , MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; return ; case <STR_LIT> : OutStreamer . EmitWinCFIAllocStack ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; return ; case <STR_LIT> : OutStreamer . EmitWinCFISetFrame ( RI -> getSEHRegNum ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) , MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; return ; case


<s> LLVM_ATTRIBUTE_UNUSED static bool isCopyFromRegOfInlineAsm ( const SDNode * N ) { assert ( N -> getOpcode ( ) == <STR_LIT> ) ; do { N = N -> getOperand ( <NUM_LIT> ) . getNode ( ) ; if ( N -> getOpcode ( ) ==


<s> SDValue Cond = DAG . getSetCC ( DL , CCVT , R , Y , <STR_LIT> ) ; Q = DAG . getNode ( <STR_LIT> , DL , VT , Cond , DAG . getNode ( <STR_LIT> , DL , VT , Q , One ) , Q ) ; R = DAG . getNode ( <STR_LIT> , DL , VT , Cond , DAG . getNode ( <STR_LIT> , DL , VT , R , Y ) , R ) ; Cond = DAG . getSetCC ( DL , CCVT , R , Y , <STR_LIT> ) ; Q = DAG . getNode ( <STR_LIT> , DL , VT , Cond , DAG . getNode ( <STR_LIT> , DL , VT , Q , One ) , Q ) ; R = DAG . getNode ( <STR_LIT> , DL , VT , Cond , DAG . getNode ( <STR_LIT>


<s> Op -> MatrixTileList . RegMask = RegMask ; Op -> StartLoc = S ; Op -> EndLoc = E ; return Op


<s> uint32_t <ISA_LIT>MCCodeEmitter :: getVecShiftL8OpValue ( const MCInst & MI , unsigned OpIdx ,

SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const {


<s> StringRef Head = Name . slice ( Start , Next ) ; if ( Head == <STR_LIT> || Head == <STR_LIT> || Head == <STR_LIT> || Head == <STR_LIT> ) return parseSysAlias ( Head , NameLoc , Operands ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateToken ( Head , false , NameLoc , getContext ( ) ) ) ; Mnemonic = Head ; if ( Head == <STR_LIT> && Next != StringRef :: npos ) { Start = Next ; Next = Name . find ( '.' , Start + <NUM_LIT> ) ; Head = Name . slice ( Start + <NUM_LIT> , Next ) ; SMLoc SuffixLoc = SMLoc :: getFromPointer ( NameLoc . getPointer ( ) + ( Head . data ( ) - Name . data ( ) ) ) ; unsigned CC = parseCondCodeString ( Head ) ; if ( CC == <STR_LIT> ) return Error ( SuffixLoc , <STR_LIT> ) ; const MCExpr * CCExpr = MCConstantExpr :: Create ( CC , getContext


<s> SDValue CC = N -> getOperand ( <NUM_LIT> ) ; unsigned Opc = CC -> getOpcode ( ) ; SDValue Int ; if ( ( Opc == <STR_LIT> || Opc == <STR_LIT> ) && ( CC -> getOperand ( <NUM_LIT> ) -> getOpcode ( ) == <STR_LIT> ) ) { assert ( ( isa < ConstantSDNode > ( CC -> getOperand ( <NUM_LIT> ) ) && cast < ConstantSDNode > ( CC -> getOperand ( <NUM_LIT> ) ) -> isOne ( ) ) && <STR_LIT> ) ; Int = CC -> getOperand ( <NUM_LIT> ) ; } else if ( CC -> getOpcode ( ) == <STR_LIT> ) Int = CC ; else return SDValue ( ) ; unsigned IntOp = cast < ConstantSDNode > ( Int . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; if ( IntOp != <STR_LIT> ) return SDValue ( ) ; SDLoc dl ( Int ) ; SDValue Chain = N -> getOperand ( <NUM_LIT> ) ; SDValue Elements = Int . getOperand ( <NUM_LIT> ) ; SDValue ExitBlock = N -> getOperand ( <NUM_LIT> ) ; SDValue Ops [ ] = { Chain , Elements , ExitBlock


<s> static bool fr30_function_value_regno_p ( const unsigned int regno


<s> if ( IsLoad ) { unsigned ResTyElts = ( NumVecs == <NUM_LIT> ) ? <NUM_LIT> : NumVecs ; if ( ! is64BitVector ) ResTyElts *= <NUM_LIT> ; ResTys . push_back ( EVT :: getVectorVT ( * CurDAG -> getContext ( ) , <STR_LIT> , ResTyElts ) ) ; } if ( isUpdating ) ResTys . push_back ( <STR_LIT> ) ; ResTys . push_back ( <STR_LIT> ) ; SDValue Pred = getAL ( CurDAG ) ; SDValue Reg0 = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . push_back ( MemAddr ) ; Ops . push_back ( Align ) ; if ( isUpdating ) { SDValue Inc = N -> getOperand ( AddrOpIdx + <NUM_LIT> ) ; Ops . push_back ( isa < ConstantSDNode > ( Inc . getNode ( ) ) ? Reg0 : Inc ) ; } SDValue SuperReg ; SDValue V0 = N -> getOperand ( Vec0Idx + <NUM_LIT> ) ; SDValue V1 = N -> getOperand ( Vec0Idx + <NUM_LIT> ) ; if ( NumVecs == <NUM_LIT> ) { if ( is64BitVector ) SuperReg = SDValue ( createDRegPairNode ( <STR_LIT> , V0 , V1 ) , <NUM_LIT> ) ; else SuperReg = SDValue ( createQRegPairNode ( <STR_LIT> , V0 , V1 ) , <NUM_LIT> ) ; } else { SDValue V2 = N -> getOperand ( Vec0Idx + <NUM_LIT> ) ; SDValue V3 = ( NumVecs == <NUM_LIT> ) ? SDValue ( CurDAG -> getMachineNode ( TargetOpcode :: IMPLICIT_DEF , dl , VT ) , <NUM_LIT> ) : N -> getOperand ( Vec0Idx + <NUM_LIT> ) ; if ( is64BitVector ) SuperReg = SDValue ( createQuadDRegsNode ( <STR_LIT> , V0 , V1 , V2 , V3 ) , <NUM_LIT> ) ; else SuperReg = SDValue ( createQuadQRegsNode ( <STR_LIT> , V0 , V1 , V2 , V3 ) , <NUM_LIT> ) ; } Ops . push_back ( SuperReg ) ; Ops . push_back ( getI32Imm ( Lane ) ) ; Ops . push_back ( Pred ) ; Ops . push_back ( Reg0 ) ; Ops . push_back ( Chain ) ; unsigned Opc = ( is64BitVector ? DOpcodes [ OpcodeIndex ] : QOpcodes [ OpcodeIndex ] ) ; SDNode * VLdLn = CurDAG -> getMachineNode ( Opc , dl , ResTys , Ops ) ; cast < MachineSDNode > ( VLdLn ) -> setMemRefs ( MemOp , MemOp + <NUM_LIT> ) ; if ( ! IsLoad ) return VLdLn ; SuperReg = SDValue ( VLdLn , <NUM_LIT>


<s> if ( numBitsUnsigned ( MulLHS , DAG ) <= <NUM_LIT> && numBitsUnsigned ( MulRHS , DAG ) <= <NUM_LIT> ) { MulLHS = DAG . getZExtOrTrunc ( MulLHS , SL , <STR_LIT> ) ; MulRHS = DAG . getZExtOrTrunc ( MulRHS , SL , <STR_LIT> ) ; AddRHS = DAG . getZExtOrTrunc ( AddRHS , SL , <STR_LIT> ) ; return getMad64_32 ( DAG , SL , VT , MulLHS , MulRHS , AddRHS , false ) ; } if ( numBitsSigned ( MulLHS , DAG ) < <NUM_LIT> && numBitsSigned ( MulRHS , DAG ) < <NUM_LIT> ) { MulLHS = DAG . getSExtOrTrunc ( MulLHS , SL , <STR_LIT> ) ; MulRHS = DAG . getSExtOrTrunc ( MulRHS , SL , <STR_LIT> ) ; AddRHS = DAG . getSExtOrTrunc ( AddRHS , SL , <STR_LIT> ) ; return getMad64_32 ( DAG , SL , VT , MulLHS , MulRHS , AddRHS , true ) ; } return SDValue ( ) ; } if ( VT != <STR_LIT> ) return SDValue ( ) ; unsigned Opc = LHS . getOpcode ( ) ; if ( Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ) std :: swap ( RHS , LHS ) ; Opc = RHS . getOpcode ( ) ; switch ( Opc ) { default : break ; case <STR_LIT> : case


<s> RegisterMCAsmInfoFn A ( The<ISA_LIT>64Target , create<ISA_LIT>MCAsmInfo ) ; RegisterMCAsmInfoFn B ( The<ISA_LIT>64elTarget , create<ISA_LIT>MCAsmInfo ) ; TargetRegistry :: RegisterMCCodeGenInfo ( The<ISA_LIT>Target , create<ISA_LIT>MCCodeGenInfo ) ; TargetRegistry :: RegisterMCCodeGenInfo ( The<ISA_LIT>elTarget , create<ISA_LIT>MCCodeGenInfo ) ; TargetRegistry :: RegisterMCCodeGenInfo ( The<ISA_LIT>64Target , create<ISA_LIT>MCCodeGenInfo ) ; TargetRegistry :: RegisterMCCodeGenInfo ( The<ISA_LIT>64elTarget , create<ISA_LIT>MCCodeGenInfo ) ; TargetRegistry :: RegisterMCInstrInfo ( The<ISA_LIT>Target , create<ISA_LIT>MCInstrInfo ) ; TargetRegistry :: RegisterMCInstrInfo ( The<ISA_LIT>elTarget , create<ISA_LIT>MCInstrInfo ) ; TargetRegistry :: RegisterMCInstrInfo ( The<ISA_LIT>64Target , create<ISA_LIT>MCInstrInfo ) ; TargetRegistry :: RegisterMCInstrInfo ( The<ISA_LIT>64elTarget , create<ISA_LIT>MCInstrInfo ) ; TargetRegistry :: RegisterMCRegInfo ( The<ISA_LIT>Target , create<ISA_LIT>MCRegisterInfo ) ; TargetRegistry :: RegisterMCRegInfo ( The<ISA_LIT>elTarget , create<ISA_LIT>MCRegisterInfo ) ; TargetRegistry :: RegisterMCRegInfo ( The<ISA_LIT>64Target , create<ISA_LIT>MCRegisterInfo ) ; TargetRegistry :: RegisterMCRegInfo ( The<ISA_LIT>64elTarget , create<ISA_LIT>MCRegisterInfo ) ; TargetRegistry :: RegisterMCCodeEmitter ( The<ISA_LIT>Target , create<ISA_LIT>MCCodeEmitter ) ; TargetRegistry :: RegisterMCCodeEmitter ( The<ISA_LIT>elTarget , create<ISA_LIT>MCCodeEmitter ) ; TargetRegistry :: RegisterMCCodeEmitter ( The<ISA_LIT>64Target , create<ISA_LIT>MCCodeEmitter ) ; TargetRegistry :: RegisterMCCodeEmitter ( The<ISA_LIT>64elTarget , create<ISA_LIT>MCCodeEmitter ) ; TargetRegistry :: RegisterMCObjectStreamer ( The<ISA_LIT>Target , createMCStreamer ) ; TargetRegistry :: RegisterMCObjectStreamer ( The<ISA_LIT>elTarget , createMCStreamer ) ; TargetRegistry :: RegisterMCObjectStreamer ( The<ISA_LIT>64Target , createMCStreamer ) ; TargetRegistry :: RegisterMCObjectStreamer ( The<ISA_LIT>64elTarget , createMCStreamer ) ; TargetRegistry :: RegisterMCAsmBackend ( The<ISA_LIT>Target , create<ISA_LIT>AsmBackend ) ; TargetRegistry :: RegisterMCAsmBackend ( The<ISA_LIT>elTarget


<s> GlobalBaseReg = <NUM_LIT> ; <ISA_LIT>SubTarget = & MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; Subtarget = & MF . getSubtarget <


<s> va_list_gpr_counter_field = f_gpr ; va_list_fpr_counter_field = f_fpr ; DECL_FIELD_CONTEXT ( f_gpr ) = record ; DECL_FIELD_CONTEXT ( f_fpr ) = record ; DECL_FIELD_CONTEXT ( f_res ) = record ; DECL_FIELD_CONTEXT ( f_ovf ) = record ; DECL_FIELD_CONTEXT ( f_sav ) = record ; TYPE_STUB_DECL ( record ) = type_decl ; TYPE_NAME ( record ) = type_decl ; TYPE_FIELDS ( record ) = f_gpr ; DECL_CHAIN ( f_gpr ) = f_fpr ; DECL_CHAIN ( f_fpr )


<s> const ArrayRef < MCPhysReg > IntArgRegs = Subtarget . getABI ( ) . GetByValArgRegs ( ) ; const MCPhysReg * ShadowRegs = Subtarget . isABI_O32 ( ) ? IntArgRegs . data ( ) : <ISA_LIT>64DPRegs ; assert ( ! ( Align % RegSizeInBytes ) && <STR_LIT> <STR_LIT> ) ; FirstReg = State -> getFirstUnallocated ( IntArgRegs . data ( ) , IntArgRegs . size ( ) ) ; if ( ( Align > RegSizeInBytes ) && ( FirstReg % <NUM_LIT> ) ) { State -> AllocateReg ( IntArgRegs [ FirstReg ] , ShadowRegs [ FirstReg ] ) ; ++ FirstReg ; } Size = RoundUpToAlignment ( Size , RegSizeInBytes ) ; for ( unsigned I = FirstReg ; Size > <NUM_LIT> && (


<s> if ( Opcode == <STR_LIT> ) { if ( isShiftMask ) Mask = Mask << Shift ; Indeterminant = ~ ( <NUM_LIT> << Shift ) ; } else if ( Opcode == <STR_LIT> ) { if ( isShiftMask ) Mask = Mask >> Shift ; Indeterminant = ~ ( <NUM_LIT> >> Shift ) ; Shift = <NUM_LIT> - Shift ; } else if ( Opcode ==


<s> return TargetTransformInfo ( <ISA_LIT>TTIImpl ( this , F )


<s> MachineInstrBuilder MIB = BuildMI ( MBB , I , I -> getDebugLoc ( ) , get ( Opc ) , DestReg ) ; if ( Subtarget . isMClass ( ) ) MIB . addImm ( <NUM_LIT> ) ; AddDefaultPred ( MIB ) ; MIB . addReg ( <STR_LIT> , RegState :: Implicit | getKillRegState (


<s> O << <STR_LIT> << retAlignment << <STR_LIT> << DL . getTypeAllocSize ( retTy ) << <STR_LIT> ; } else { llvm_unreachable ( <STR_LIT> ) ; } O << <STR_LIT> ; } O << <STR_LIT> ; bool first = true ; unsigned OIdx = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> , e = Args . size ( ) ; i != e ; ++ i , ++ OIdx ) { Type * Ty = Args [ i ] . Ty ; if ( ! first ) { O << <STR_LIT> ; } first = false ; if ( ! Outs [ OIdx ] . Flags . isByVal ( ) ) { if ( Ty -> isAggregateType ( ) || Ty -> isVectorTy ( ) || Ty -> isIntegerTy ( <NUM_LIT> ) ) { unsigned align = <NUM_LIT> ; const CallInst * CallI = cast < CallInst > ( CS . getInstruction ( ) ) ; if ( ! getAlign ( * CallI , i + <NUM_LIT> , align ) ) align = DL . getABITypeAlignment ( Ty ) ; unsigned sz = DL . getTypeAllocSize ( Ty ) ; O << <STR_LIT> << align << <STR_LIT> ; O << <STR_LIT> ; O << <STR_LIT> << sz << <STR_LIT> ; SmallVector < EVT , <NUM_LIT> > vtparts ; ComputeValueVTs ( * this , DL , Ty , vtparts ) ; if ( unsigned len = vtparts . size ( ) ) OIdx += len - <NUM_LIT> ; continue ; } assert ( ( getValueType ( DL , Ty ) == Outs [ OIdx ] . VT || ( getValueType ( DL , Ty ) == <STR_LIT> && Outs [ OIdx ] . VT == <STR_LIT> ) ) && <STR_LIT> ) ; unsigned sz = <NUM_LIT> ; if ( isa < IntegerType > ( Ty ) ) { sz = cast < IntegerType > ( Ty ) -> getBitWidth ( ) ; if ( sz < <NUM_LIT> ) sz = <NUM_LIT> ; } else if ( isa < PointerType > ( Ty ) ) { sz = PtrVT . getSizeInBits ( ) ; } else if ( Ty -> isHalfTy ( ) ) sz = <NUM_LIT> ; else sz = Ty -> getPrimitiveSizeInBits ( ) ; O << <STR_LIT> << sz << <STR_LIT> ; O << <STR_LIT> ; continue ; } auto * PTy = dyn_cast < PointerType > ( Ty ) ; assert ( PTy && <STR_LIT> ) ; Type * ETy = PTy -> getElementType ( ) ; Align align = Outs [ OIdx ] . Flags . getNonZeroByValAlign ( ) ; unsigned sz = DL . getTypeAllocSize ( ETy ) ; O << <STR_LIT> << align . value ( ) << <STR_LIT> ; O << <STR_LIT> ; O << <STR_LIT> <<


<s> rtx gen_easy_altivec_constant ( rtx op ) { enum machine_mode mode = GET_MODE ( op ) ; int nunits = GET_MODE_NUNITS ( mode ) ; rtx last = CONST_VECTOR_ELT ( op , nunits - <NUM_LIT> ) ; unsigned step = nunits / <NUM_LIT> ; unsigned copies = <NUM_LIT> ; if ( vspltis_constant ( op , step , copies ) ) return gen_rtx_VEC_DUPLICATE ( V4SImode , gen_lowpart ( SImode , last ) ) ; if ( step == <NUM_LIT> ) copies <<= <NUM_LIT> ; else step >>= <NUM_LIT> ; if ( vspltis_constant ( op , step , copies ) ) return gen_rtx_VEC_DUPLICATE ( V8HImode , gen_lowpart ( HImode , last ) ) ; if ( step == <NUM_LIT> ) copies


<s> SDValue GlobalBase = DAG . getNode ( <STR_LIT> , DL , VT ) ; SDValue AbsAddr = DAG . getNode ( <STR_LIT> , DL , VT , GlobalBase , HiLo ) ; MachineFrameInfo * MFI = DAG . getMachineFunction ( ) . getFrameInfo ( ) ; MFI -> setHasCalls ( true ) ; return DAG . getLoad ( VT , DL , DAG . getEntryNode ( ) , AbsAddr , MachinePointerInfo :: getGOT ( DAG . getMachineFunction ( ) ) , false , false , false , <NUM_LIT> ) ; } switch ( getTargetMachine ( ) . getCodeModel ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case CodeModel :: Small : return makeHiLoPair ( Op , <ISA_LIT>MCExpr :: VK_<ISA_LIT>_HI , <ISA_LIT>MCExpr :: VK_<ISA_LIT>_LO , DAG ) ; case CodeModel :: Medium : { SDValue H44 = makeHiLoPair ( Op , <ISA_LIT>MCExpr :: VK_<ISA_LIT>_H44 , <ISA_LIT>MCExpr :: VK_<ISA_LIT>_M44 , DAG ) ; H44 = DAG . getNode ( <STR_LIT> , DL , VT , H44 , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; SDValue L44 = withTargetFlags ( Op , <ISA_LIT>MCExpr :: VK_<ISA_LIT>_L44 , DAG ) ; L44 = DAG . getNode ( <STR_LIT> , DL , VT , L44 ) ; return DAG . getNode ( <STR_LIT> , DL , VT , H44 , L44 ) ; } case CodeModel :: Large : { SDValue Hi = makeHiLoPair ( Op , <ISA_LIT>MCExpr :: VK_<ISA_LIT>_HH , <ISA_LIT>MCExpr ::


<s> void CFStack :: pushLoop ( ) { LoopStack . push_back ( CFStack :: ENTRY


<s> Relocator :: Address GOT_ORG = helper_GOT_ORG ( pParent ) ; pReloc . target ( ) = GOT_ORG + A - pReloc . place ( ) ; return Relocator ::


, V2 , Mask , Subtarget , DAG ) ) return Blend ;


<s> SDValue <ISA_LIT>TargetLowering :: LowerGlobalTLSAddress ( SDValue Op , SelectionDAG & DAG ) const { llvm_unreachable ( <STR_LIT>


<s> MCOperand <ISA_LIT>Disassembler :: decodeOperand_AReg_128 ( unsigned Val ) const { return createRegOperand ( <STR_LIT> , Val


<s> convert_op ( & op11 , insn ) ; convert_op ( & op12 , insn ) ; if ( ! REG_P ( op11 ) ) { tmp = gen_reg_rtx ( vmode ) ; emit_insn_before ( gen_rtx_SET ( tmp , op11 ) , insn ) ; op11 = tmp ; } return gen_rtx_UNSPEC ( CCmode , gen_rtvec ( <NUM_LIT> , op11 , op12 ) , UNSPEC_PTEST ) ; } else { convert_op ( & op1 , insn ) ; src = op1 ; } if ( ! REG_P ( src ) ) { tmp = gen_reg_rtx ( vmode ) ; emit_insn_before ( gen_rtx_SET ( tmp , src ) , insn ) ; src = tmp ; } if ( vmode == V2DImode ) { tmp = gen_reg_rtx ( vmode ) ; emit_insn_before ( gen_vec_interleave_lowv2di ( tmp , src , src ) , insn ) ; src = tmp ; } else if ( vmode == V4SImode ) { tmp = gen_reg_rtx ( vmode ) ; emit_insn_before ( gen_sse2_pshufd ( tmp , src , const0_rtx ) , insn ) ; src = tmp ; } return gen_rtx_UNSPEC ( CCmode , gen_rtvec ( <NUM_LIT> , src ,


<s> return ( TargetTriple . getEnvironment ( ) != Triple :: ELF && TargetTriple


<s> unsigned <ISA_LIT>FunctionInfo :: getGlobalBaseReg ( ) { if ( GlobalBaseReg ) return GlobalBaseReg ; if ( <ISA_LIT>FixGlobalBaseReg ) return GlobalBaseReg = <STR_LIT> ; const TargetRegisterClass * RC ; RC = ( const TargetRegisterClass * )


<s> n = INTVAL_OR_ELSE ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) ; x = XEXP ( x , <NUM_LIT> ) ; break ; case SIGN_EXTRACT : n = BITS_PER_WORD - INTVAL_OR_ELSE ( XEXP ( x , <NUM_LIT> ) , BITS_PER_WORD ) ; x = NULL_RTX ; break ; case IOR : w = INTVAL_OR_ELSE ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) ; for ( i = BITS_PER_WORD - <NUM_LIT> ; i


<s> EmitNops ( * OutStreamer , <NUM_LIT> , Subtarget -> is64Bit ( ) , getSubtargetInfo ( ) ) ; OutStreamer -> EmitLabel ( Target ) ; recordSled ( CurSled , MI


<s> bool isExtend64 ( ) const { if ( Kind != k_Extend


<s> case ENCODING_CD : case ENCODING_CP : case ENCODING_CO : case ENCODING_CT : debug ( <STR_LIT> ) ; return true ; case ENCODING_IB : case ENCODING_IW : case ENCODING_ID : case ENCODING_IO : case ENCODING_Iv : case ENCODING_Ia : translateImmediate ( mcInst , insn . immediates [ insn . numImmediatesTranslated ++ ] , operand , insn , Dis ) ; return false ; case ENCODING_RB : case ENCODING_RW : case ENCODING_RD : case ENCODING_RO : translateRegister ( mcInst , insn . opcodeRegister ) ; return false


<s> bool useCheriCapTable ( ) const { return getABI ( )


<s> PrivateGlobalPrefix = <STR_LIT> ; WeakRefDirective = <STR_LIT> ; ExceptionsType = ExceptionHandling :: DwarfCFI ; UsesELFSectionDirectiveForBSS = true ; UseIntegratedAssembler = true ; CommentString = <STR_LIT> ; SupportsDebugInformation = true


<s> return __builtin_mve_vqrdmladhq_sv16qi ( __inactive ,


<s> unsigned <ISA_LIT>AsmParser :: getReg ( int RC , int RegNo ) { return * ( getContext ( ) . getRegisterInfo ( ) -> getRegClass ( RC ) .


<s> for ( ; I < ByVal . NumRegs - LeftoverBytes ; ++ I , OffsetInBytes += RegSizeInBytes ) { SDValue LoadPtr = DAG . getNode ( <STR_LIT> , DL , PtrTy , Arg , DAG . getConstant ( OffsetInBytes , PtrTy ) ) ; SDValue LoadVal = DAG . getLoad ( RegTy , DL , Chain , LoadPtr , MachinePointerInfo ( ) , false , false , false , Alignment ) ; MemOpChains . push_back ( LoadVal . getValue ( <NUM_LIT> ) ) ; unsigned ArgReg = ArgRegs [ ByVal . FirstIdx + I ] ; RegsToPass . push_back ( std :: make_pair ( ArgReg , LoadVal ) ) ; } if ( ByValSizeInBytes == OffsetInBytes ) return ; if ( LeftoverBytes ) { assert ( ( ByValSizeInBytes > OffsetInBytes ) && ( ByValSizeInBytes < OffsetInBytes + RegSizeInBytes ) && <STR_LIT> ) ; SDValue Val ; for ( unsigned LoadSizeInBytes = RegSizeInBytes / <NUM_LIT> , TotalBytesLoaded = <NUM_LIT> ; OffsetInBytes < ByValSizeInBytes ; LoadSizeInBytes /= <NUM_LIT> ) { unsigned RemainingSizeInBytes = ByValSizeInBytes - OffsetInBytes ; if ( RemainingSizeInBytes < LoadSizeInBytes ) continue ; SDValue LoadPtr = DAG . getNode ( <STR_LIT> , DL , PtrTy , Arg , DAG . getConstant ( OffsetInBytes , PtrTy ) ) ; SDValue LoadVal = DAG . getExtLoad ( <STR_LIT> , DL , RegTy , Chain , LoadPtr , MachinePointerInfo ( ) , <STR_LIT> ( LoadSizeInBytes * <NUM_LIT> ) , false , false , Alignment ) ; MemOpChains . push_back ( LoadVal . getValue


<s> const <ISA_LIT>TargetLowering * getTargetLowering


<s> if ( riscv_symbol_insns ( sym_type ) == <NUM_LIT> ) return false ; if ( ! riscv_split_symbol_type ( sym_type


<s> unsigned MaxSize = Size * <NUM_LIT> ; if ( ! Arg . IsFixed ) MaxSize = <NUM_LIT> ; Register ValVReg = VA . getLocInfo ( ) != CCValAssign :: LocInfo :: FPExt ? extendRegister ( Arg

. Regs [ <NUM_LIT> ] , VA , MaxSize ) : Arg . Regs [ <NUM_LIT> ] ;


<s> void <ISA_LIT>AsmPrinter :: EmitFunctionBodyEnd ( ) { OutStreamer . EmitRawText ( <STR_LIT> + Twine (


<s> IRBuilder < > Builder ( InsertAtEnd ) ; Value * Idx [ <NUM_LIT> ] ; Idx [ <NUM_LIT> ] = Builder . getInt32 ( <NUM_LIT> ) ; Idx [ <NUM_LIT> ] = Builder . getInt32 ( getTranslator ( ) . getRegSetDesc ( ) . RegOffsetsInSet [

getTranslator ( ) . getRegSetDesc ( ) . RegLargestSupers [ <STR_LIT> ] ] ) ;


<s> DEBUG ( dbgs ( ) << <STR_LIT> ) ; LoadI -> eraseFromParent ( ) ; return NextI ; } BitExtMI = BuildMI ( * LoadI -> getParent ( ) , LoadI , LoadI -> getDebugLoc ( ) , TII -> get ( IsStoreXReg ? <STR_LIT> : <STR_LIT> ) , LdRt ) . addReg ( IsStoreXReg ? <STR_LIT> : <STR_LIT> ) . addReg ( StRt ) . addImm ( <STR_LIT> ( <STR_LIT> , <NUM_LIT> ) ) ; } else { if ( ! Subtarget -> isLittleEndian ( ) ) return NextI ; bool IsUnscaled = TII -> isUnscaledLdSt ( LoadI ) ; assert ( IsUnscaled == TII -> isUnscaledLdSt ( StoreI ) && <STR_LIT> ) ; assert ( LoadSize <= StoreSize && <STR_LIT> ) ; int UnscaledLdOffset = IsUnscaled ? getLdStOffsetOp ( LoadI ) . getImm ( ) : getLdStOffsetOp ( LoadI ) . getImm ( ) * LoadSize ; int UnscaledStOffset = IsUnscaled ? getLdStOffsetOp ( StoreI ) . getImm ( ) : getLdStOffsetOp ( StoreI ) . getImm ( ) * StoreSize ; int Width = LoadSize * <NUM_LIT> ; int Immr = <NUM_LIT> * ( UnscaledLdOffset - UnscaledStOffset ) ; int Imms = Immr + Width - <NUM_LIT> ; unsigned DestReg = IsStoreXReg ? TRI -> getMatchingSuperReg ( LdRt , <STR_LIT> , & <STR_LIT> ) : LdRt ; assert ( ( UnscaledLdOffset >= UnscaledStOffset && ( UnscaledLdOffset + LoadSize ) <= UnscaledStOffset + StoreSize ) && <STR_LIT> ) ; Immr = <NUM_LIT> * ( UnscaledLdOffset - UnscaledStOffset ) ; Imms = Immr + Width - <NUM_LIT> ; if ( UnscaledLdOffset == UnscaledStOffset ) { uint32_t AndMaskEncoded = ( ( IsStoreXReg ? <NUM_LIT> : <NUM_LIT> ) << <NUM_LIT> ) | ( ( Immr ) << <NUM_LIT> ) | ( ( Imms ) << <NUM_LIT> ) ; BitExtMI = BuildMI ( * LoadI -> getParent ( ) , LoadI , LoadI -> getDebugLoc ( ) , TII -> get ( IsStoreXReg ? <STR_LIT> : <STR_LIT> ) , DestReg ) . addReg ( StRt ) . addImm ( AndMaskEncoded ) ; } else { BitExtMI = BuildMI ( * LoadI -> getParent ( ) , LoadI , LoadI -> getDebugLoc ( ) , TII -> get ( IsStoreXReg ? <STR_LIT> : <STR_LIT> ) , DestReg ) . addReg ( StRt ) . addImm ( Immr ) . addImm ( Imms ) ; } } ( void ) BitExtMI ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; DEBUG ( StoreI -> print ( dbgs ( )


<s> if ( RegClass == AMDGPU :: VSrc_32RegClassID ) RegClass = AMDGPU :: VReg_32RegClassID ; else if ( RegClass == AMDGPU :: VSrc_64RegClassID ) RegClass = AMDGPU :: VReg_64RegClassID ; else return ; if ( fitsRegClass ( DAG , Operand , RegClass ) ) return ; if ( ! ScalarSlotUsed ) { ScalarSlotUsed = true ; return ; } SDValue RC = DAG . getTargetConstant ( RegClass , <STR_LIT> ) ; SDNode * Node = DAG . getMachineNode ( TargetOpcode :: COPY_TO_REGCLASS , SDLoc ( ) , Operand .


<s> std :: string SectionName = <STR_LIT> + Name ; std :: string StubName = <STR_LIT> + Name ; std :: string LocalName = <STR_LIT> + Name ; Function * FStub = Function :: Create ( F -> getFunctionType ( ) , Function :: InternalLinkage , StubName , M ) ; FStub -> addFnAttr ( <STR_LIT> ) ; FStub -> addFnAttr ( Attribute :: Naked ) ; FStub -> addFnAttr ( Attribute :: NoUnwind ) ; FStub -> addFnAttr ( Attribute :: NoInline ) ; FStub -> addFnAttr ( <STR_LIT> ) ; FStub -> setSection ( SectionName ) ; BasicBlock * BB = BasicBlock :: Create ( Context , <STR_LIT> , FStub ) ; std ::


<s> case <STR_LIT> : Opc = IsDirect ? <STR_LIT> : <STR_LIT> ; ResultReg = createResultReg ( & <STR_LIT> ) ; break ; case <STR_LIT> : Opc = IsDirect ? <STR_LIT> : <STR_LIT> ; ResultReg = createResultReg ( & <STR_LIT> ) ; break ; case <STR_LIT> : Opc = IsDirect ? <STR_LIT> : <STR_LIT> ; ResultReg = createResultReg ( & <STR_LIT> ) ; break ; default : return false ; } } SmallVector < unsigned , <NUM_LIT> > Args ; for ( unsigned i = <NUM_LIT> , e = Call -> getNumArgOperands ( ) ; i < e ; ++ i ) { Value * V = Call -> getArgOperand ( i ) ; <STR_LIT> ArgTy = getSimpleType ( V -> getType ( ) ) ; if ( ArgTy == <STR_LIT> ) return false ; const AttributeSet & Attrs = Call -> getAttributes ( ) ; if ( Attrs . hasAttribute ( i + <NUM_LIT> , Attribute :: ByVal ) || Attrs . hasAttribute ( i + <NUM_LIT> , Attribute :: SwiftSelf ) || Attrs . hasAttribute ( i + <NUM_LIT> , Attribute :: SwiftError ) || Attrs . hasAttribute ( i + <NUM_LIT> , Attribute :: InAlloca ) || Attrs . hasAttribute ( i + <NUM_LIT> , Attribute :: Nest ) ) return false ; unsigned Reg ; if ( Attrs . hasAttribute ( i + <NUM_LIT> , Attribute :: SExt ) ) Reg = getRegForSignedValue ( V ) ; else if ( Attrs . hasAttribute ( i + <NUM_LIT> , Attribute :: ZExt ) ) Reg = getRegForUnsignedValue ( V ) ; else Reg = getRegForValue ( V ) ; if ( Reg == <NUM_LIT> ) return false ; Args . push_back ( Reg ) ; } auto MIB = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) ) ; if ( ! IsVoid ) MIB . addReg ( ResultReg , RegState :: Define ) ; if ( IsDirect ) MIB . addGlobalAddress (


<s> Register regX = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register regY = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; BuildMI ( * BB , MI , MI . getDebugLoc ( ) , TII -> get ( SltOpc ) ) . addReg ( regX ) . addReg ( regY ) ; BuildMI ( * BB , MI , MI . getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , CC ) . addReg ( <STR_LIT> ) ; MI . eraseFromParent ( )


<s> unsigned Opc ; Type * OpTy = I -> getOperand ( <NUM_LIT> ) -> getType ( ) ; if ( OpTy -> isFloatTy ( ) ) Opc = isSigned ? <STR_LIT> : <STR_LIT> ; else if ( OpTy -> isDoubleTy ( ) ) Opc = isSigned ? <STR_LIT> : <STR_LIT> ; else return false ; unsigned ResultReg = createResultReg ( TLI . getRegClassFor ( <STR_LIT> ) ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( Opc ) , ResultReg ) . addReg ( Op ) ) ; unsigned IntReg = <ISA_LIT>MoveToIntReg ( DstVT , ResultReg ) ; if ( IntReg == <NUM_LIT> )


<s> bool isMemDisp12 ( MemoryKind MemKind , RegisterKind RegKind


<s> const int mult = ( named ? <NUM_LIT> : <NUM_LIT> ) ; unsigned int nwords ; if ( slotno == ( named ? SPARC_FP_ARG_MAX : SPARC_INT_ARG_MAX ) - <NUM_LIT> ) nwords = <NUM_LIT> ; else nwords = CEIL_NWORDS ( size ) ; rtx regs = gen_rtx_PARALLEL ( BLKmode , rtvec_alloc ( nwords ) ) ; if ( size < UNITS_PER_WORD ) XVECEXP ( regs , <NUM_LIT> , <NUM_LIT> ) = gen_rtx_EXPR_LIST ( VOIDmode , gen_rtx_REG ( SImode , regno ) , const0_rtx ) ; else for ( unsigned int i = <NUM_LIT> ; i < nwords ; i ++ ) XVECEXP ( regs , <NUM_LIT> , i ) = gen_rtx_EXPR_LIST ( VOIDmode , gen_rtx_REG ( word_mode , regno + i * mult ) , GEN_INT ( i * UNITS_PER_WORD ) ) ; return


<s> assemble_start_function ( thunk , fnname ) ; fprintf ( file , <STR_LIT> HOST_WIDE_INT_PRINT_DEC , delta ) ; asm_fprintf ( file , <STR_LIT> ) ; fprintf ( file ,


<s> if ( ! BTP -> has ( OutR ) || ! BTP -> has ( InpR ) ) return false ; const BitTracker :: RegisterCell & OutC = BTP -> lookup ( OutR ) ; for ( unsigned i = <NUM_LIT> , w = OutC . width ( ) ; i < w ; ++ i ) { const BitTracker :: BitValue & V = OutC [ i ] ; if ( V . Type != BitTracker :: BitValue :: Ref ) continue ; if ( V . RefI . Reg != InpR ) return false ; } return


<s> subrtx_var_iterator :: array_type array ; FOR_EACH_SUBRTX_VAR ( iter , array , x , NONCONST ) { rtx x = * iter ; if ( GET_CODE ( x ) == TRUNCATE ) { rtx reg = XEXP ( x , <NUM_LIT> ) ; machine_mode reg_mode = GET_MODE ( reg ) ; if ( REG_P ( reg ) && GET_MODE_SIZE ( reg_mode ) > <NUM_LIT> ) { int offset = subreg_lowpart_offset ( DImode , reg_mode ) ; XEXP ( x , <NUM_LIT> ) = simplify_subreg ( DImode , reg


<s> <ISA_LIT>GNULDBackend :: initTargetSections ( pModule , pBuilder ) ; if ( LinkerConfig :: Object == config ( ) . codeGenType ( ) ) return ; ELFFileFormat * fileFormat = getOutputFormat ( ) ; LDSection & got = fileFormat -> getGOT ( ) ; m_pGOT = new <ISA_LIT>64GOT ( got ) ; LDSection & gotplt = fileFormat


<s> Chain = CurDAG -> getCopyToReg ( Chain , dl , <STR_LIT> , GOT , InFlag ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; Chain = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , <STR_LIT> , Addr . getOperand ( <NUM_LIT> ) , Chain , InFlag ) , <NUM_LIT> ) ; } else { Chain = CurDAG -> getCopyToReg ( Chain , dl , <STR_LIT> , Addr , InFlag ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; Chain = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , <STR_LIT> , Chain , InFlag ) , <NUM_LIT> ) ; } InFlag = Chain .


<s> MBBVector ExitBlks ; LoopRep -> getExitBlocks ( ExitBlks ) ; SmallPtrSet < MachineBasicBlock * , <NUM_LIT> > ExitBlkSet ; for ( unsigned i = <NUM_LIT> , e = ExitBlks . size ( ) ; i < e ; ++ i ) ExitBlkSet . insert ( ExitBlks [ i ] ) ; assert ( ExitBlkSet . size ( ) == <NUM_LIT> ) ; MachineBasicBlock * ExitBlk = * ExitBlks . begin ( ) ; assert ( ExitBlk && <STR_LIT> ) ; MBBVector LatchBlks ; for ( auto * LB : inverse_children < MachineBasicBlock * > ( LoopHeader ) ) if ( LoopRep -> contains ( LB ) ) LatchBlks . push_back ( LB ) ; for ( unsigned i = <NUM_LIT> , e = ExitingMBBs . size ( ) ; i < e ; ++ i ) mergeLoopbreakBlock ( ExitingMBBs [ i ] , ExitBlk ) ; for ( unsigned i = <NUM_LIT> , e = LatchBlks . size ( ) ; i < e ; ++ i ) settleLoopcontBlock ( LatchBlks [ i ] , LoopHeader ) ; int Match = <NUM_LIT> ; do { Match = <NUM_LIT> ; Match += serialPatternMatch ( LoopHeader


<s> if ( strcmp ( name , <STR_LIT> ) == <NUM_LIT> ) return NULL ; if ( strcmp ( name , <STR_LIT> ) == <NUM_LIT> ) return NULL ; lib_path = locate_lib ( name ) ; if ( lib_path ) return lib_path ; fprintf ( stderr , <STR_LIT> , name , name , name ) ; exit ( EXIT_FAILURE


<s> Relocator :: Result none ( Relocation & pReloc , <ISA_LIT>Relocator


<s> if ( ! matchShuffleAsInsertPS ( V1 , V2 , InsertPSMask , Zeroable , Mask , DAG ) ) return SDValue ( ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , V2 , DAG . getTargetConstant ( InsertPSMask


<s> case <STR_LIT> : return DAG . getNode ( <STR_LIT> , dl , VT , Op , VMask ) ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , dl , VT , Op , VMask ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : OpcodeSelect = <STR_LIT> ; break ; } if ( PreservedSrc . isUndef ( ) ) PreservedSrc = getZeroVector ( VT , Subtarget , DAG


<s> debug_rtx ( x ) ; if ( mode == QImode && GET_CODE ( x ) == MEM && ( cc & ~ class_contents [ R23_REGS ] [ <NUM_LIT> ] ) == <NUM_LIT> ) return QI_REGS ; if ( classes_intersect ( rclass , CR_REGS ) && GET_CODE ( x ) == REG && REGNO ( x ) >=

SB_REGNO && REGNO ( x ) <= SP_REGNO ) return TARGET_A16 ? HI_REGS : A_REGS ;


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , Optional < CodeModel :: Model > CM , CodeGenOpt :: Level OL , bool JIT ) : LLVMTargetMachine ( T , <STR_LIT> <STR_LIT> , TT , CPU , FS , Options , getRelocModel ( RM ) , getEffectiveCodeModel ( CM , CodeModel :: Small ) , OL ) , TLOF ( std :: make_unique < TargetLoweringObjectFileELF >

( ) ) , Subtarget ( TT , std :: string ( CPU ) , std :: string ( FS ) , * this ) {


<s> bool <ISA_LIT>PreLegalizerCombiner :: runOnMachineFunction ( MachineFunction & MF ) { if ( MF . getProperties ( ) . hasProperty (

MachineFunctionProperties :: Property :: FailedISel ) ) return false ;


<s> Warning ( Loc , <STR_LIT> ) ; getParser ( ) . Lex ( ) ; return false ; } if ( IdVal == <STR_LIT> ) { getParser ( ) . Lex ( ) ; return false ; } if ( IdVal == <STR_LIT> ) return parseSetFpDirective ( ) ; if ( IdVal == <STR_LIT> ) return parseSetOddSPRegDirective ( ) ; if ( IdVal == <STR_LIT> ) return parseSetNoOddSPRegDirective ( ) ; if ( IdVal == <STR_LIT> ) return parseSetPopDirective ( ) ; if ( IdVal == <STR_LIT> ) return parseSetPushDirective ( ) ; if ( IdVal == <STR_LIT> ) return parseSetReorderDirective ( ) ; if ( IdVal == <STR_LIT> ) return parseSetNoReorderDirective ( ) ; if ( IdVal == <STR_LIT> ) return parseSetMacroDirective ( ) ; if ( IdVal == <STR_LIT> ) return parseSetNoMacroDirective ( ) ; if ( IdVal == <STR_LIT> ) return parseSet<ISA_LIT>16Directive ( ) ; if ( IdVal == <STR_LIT> ) return parseSetNo<ISA_LIT>16Directive ( ) ; if ( IdVal == <STR_LIT> ) { clearFeatureBits ( <STR_LIT> , <STR_LIT> ) ; getTargetStreamer ( ) . emitDirectiveSetNoMicro<ISA_LIT> ( ) ; getParser ( ) . eatToEndOfStatement ( ) ; return false ; } if ( IdVal == <STR_LIT> ) { if ( has<ISA_LIT>64r6 ( ) ) { Error ( Loc , <STR_LIT> ) ; return false ; } return parseSetFeature ( <STR_LIT> ) ; } if ( IdVal == <STR_LIT> ) return parseSet<ISA_LIT>0Directive ( ) ; if ( IdVal == <STR_LIT> ) return parseSetFeature ( <STR_LIT> ) ; if ( IdVal == <STR_LIT> ) return parseSetFeature ( <STR_LIT> ) ; if ( IdVal == <STR_LIT> ) return parseSetFeature ( <STR_LIT> ) ; if ( IdVal == <STR_LIT> ) return parseSetFeature ( <STR_LIT> ) ; if ( IdVal == <STR_LIT> ) return parseSetFeature ( <STR_LIT> ) ; if ( IdVal == <STR_LIT> )


<s> const <ISA_LIT>RegisterInfo & getRegisterInfo ( ) const { return


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . addRequired < LoopInfoWrapperPass > ( ) ; AU . addRequired < DominatorTreeWrapperPass >


<s> return ( __mmask64 ) __builtin_ia32_kmovq ( * ( __mmask64 * )


<s> <ISA_LIT>PostRASchedStrategy :: ~ <ISA_LIT>PostRASchedStrategy ( ) { for ( auto I


<s> static MCAsmBackend * createAsmBackend ( const Target & , const MCRegisterInfo & , const Triple & TT , StringRef , const MCTargetOptions & ) { return create<ISA_LIT>AsmBackend ( TT )


<s> if ( ! isImm ( ) ) return false ; if ( ! getImm ( ) . isAbsolute ( ) ) return true ; int64_t Value = getImm ( ) . getConstant ( ) ; return Value == ( int64_t ) ( int8_t


<s> bool NeedWait = false ; for ( unsigned i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) { if ( Required . Array [ i ] <= WaitedOn . Array [ i ] ) continue ; NeedWait = true ; if ( Ordered [ i ] ) { unsigned Value = LastIssued . Array [ i ] - Required . Array [ i ] ; Counts . Array [ i ] = std :: min ( Value , WaitCounts . Array [ i ] ) ; } else Counts . Array [ i ] = <NUM_LIT> ; WaitedOn . Array [ i ] = LastIssued . Array [ i ] - Counts . Array [ i ] ; } if ( ! NeedWait ) return false ; if ( Counts . Named . EXP == <NUM_LIT> ) ExpInstrTypesSeen = <NUM_LIT> ; BuildMI ( MBB , I , DebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addImm ( ( Counts . Named . VM & <NUM_LIT> ) | ( ( Counts . Named . EXP & <NUM_LIT> ) << <NUM_LIT> ) | ( ( Counts . Named . LGKM & <NUM_LIT> ) << <NUM_LIT> ) ) ; LastOpcodeType = OTHER ; LastInstWritesM0 =


<s> else if ( code == RS6000_BIF_GET_TFIAR || code == RS6000_BIF_SET_TFIAR ) return TFIAR_SPR ; else if ( code == RS6000_BIF_GET_TEXASR || code == RS6000_BIF_SET_TEXASR ) return TEXASR_SPR ; gcc_assert ( code == RS6000_BIF_GET_TEXASRU || code == RS6000_BIF_SET_TEXASRU ) ; return


<s> const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const TargetRegisterInfo * TRI = STI . getRegisterInfo ( ) ; return MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) || MFI ->

hasVarSizedObjects ( ) || MFI -> isFrameAddressTaken ( ) || TRI -> needsStackRealignment ( MF ) ;


<s> if ( isOpcWithIntImmediate ( N0 . getNode ( ) , <STR_LIT> , And_imm ) ) std :: swap ( N0 , N1 ) ; } if ( ! And_imm ) continue ; unsigned TZ = countTrailingZeros ( And_imm ) ; if ( TZ != <NUM_LIT> && TZ != <NUM_LIT> ) continue ; And_imm >>= TZ ; if ( And_imm & ( And_imm + <NUM_LIT> ) ) continue ; SDValue Srl = N1 . getOperand ( <NUM_LIT> ) ; unsigned Srl_imm = <NUM_LIT> ; if ( ! isOpcWithIntImmediate ( Srl . getNode ( ) , <STR_LIT> , Srl_imm ) || ( Srl_imm <= <NUM_LIT> ) ) continue ; SDValue CPTmp0 ; SDValue CPTmp1 ; SDValue CPTmp2 ; if ( isThumb2 ) { if ( SelectImmShifterOperand ( N0 , CPTmp0 , CPTmp1 ) ) continue ; } else { if ( SelectImmShifterOperand ( N0 , CPTmp0 , CPTmp1 ) || SelectRegShifterOperand ( N0 , CPTmp0 , CPTmp1 , CPTmp2 ) ) continue ; } Srl = CurDAG -> getNode ( <STR_LIT> , SDLoc ( Srl ) , <STR_LIT> , Srl . getOperand ( <NUM_LIT> ) , CurDAG -> getConstant ( Srl_imm + TZ , SDLoc ( Srl ) , <STR_LIT> ) ) ; N1 = CurDAG -> getNode ( <STR_LIT> , SDLoc ( N1 ) , <STR_LIT> , Srl , CurDAG -> getConstant ( And_imm , SDLoc ( Srl ) , <STR_LIT> ) ) ; N1 = CurDAG -> getNode ( <STR_LIT> , SDLoc ( N1 ) , <STR_LIT> , N1 , CurDAG -> getConstant ( TZ , SDLoc ( Srl ) , <STR_LIT> ) ) ; CurDAG -> UpdateNodeOperands ( & N


<s> assert ( Target . getSymA ( ) -> getKind ( ) == MCSymbolRefExpr :: VK_TLVP && ! is64Bit ( ) && <STR_LIT> ) ; unsigned Log2Size = getFixupKindLog2Size ( Fixup . getKind ( ) ) ; uint32_t Value = Layout . getFragmentOffset ( Fragment ) + Fixup . getOffset ( ) ; unsigned IsPCRel = <NUM_LIT> ; if ( Target . getSymB ( ) ) { uint32_t FixupAddress = Writer -> getFragmentAddress ( Fragment , Layout ) + Fixup . getOffset ( ) ; IsPCRel = <NUM_LIT> ; FixedValue = FixupAddress - Writer -> getSymbolAddress ( Target . getSymB ( ) -> getSymbol ( ) , Layout ) + Target . getConstant ( ) ; FixedValue += <NUM_LIT> << Log2Size ; } else { FixedValue = <NUM_LIT> ; } MachO :: any_relocation_info MRE ; MRE . r_word0 = Value ; MRE . r_word1 = ( IsPCRel << <NUM_LIT> ) | ( Log2Size << <NUM_LIT> )

| ( MachO :: GENERIC_RELOC_TLV << <NUM_LIT> ) ;


<s> if ( isa < PHINode > ( & I ) ) continue ; if ( ! canTailPredicateInstruction ( I , ICmpCount ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; I . dump ( ) ) ; return false ; } Type * T = I . getType ( ) ; if ( T -> isPointerTy ( ) ) T = T -> getPointerElementType ( ) ; if ( T -> getScalarSizeInBits ( ) > <NUM_LIT> ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; T -> dump ( ) ) ; return false ; } if ( isa < StoreInst > ( I ) || isa < LoadInst > ( I ) ) { Value * Ptr = getLoadStorePointerOperand ( & I ) ; Type * AccessTy = getLoadStoreType ( & I ) ; int64_t NextStride = getPtrStride ( PSE , AccessTy , Ptr , L ) ; if ( NextStride == <NUM_LIT> ) { continue ; } else if ( NextStride == - <NUM_LIT> || ( NextStride == <NUM_LIT> && MVEMaxSupportedInterleaveFactor >= <NUM_LIT> ) || ( NextStride == <NUM_LIT> && MVEMaxSupportedInterleaveFactor >= <NUM_LIT> ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> <STR_LIT> ) ; return false ; } else if ( EnableMaskedGatherScatters ) { const SCEV * PtrScev = PSE . getSE ( ) -> getSCEV


<s> assert ( MI . getOperand ( <NUM_LIT> ) . isReg ( ) && MI . getOperand ( <NUM_LIT> ) . isReg ( ) && MI . getOperand ( <NUM_LIT> ) . isReg ( ) && <STR_LIT> ) ; size_t OrigScore = TheStack . position ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) == <NUM_LIT> ; OrigScore += TheStack . position ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) == <NUM_LIT> ; size_t RScore = TheStack . position ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) == <NUM_LIT> ; RScore += TheStack . position ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) == <NUM_LIT> ; if ( RScore > OrigScore ) { MIB = BuildMI ( * MI . getParent ( ) , & MI , MI . getDebugLoc ( ) , TII -> get ( OpcodeMap . at ( MI . getOpcode ( ) ) ) , MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; if ( MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> ) { assert ( MI . getOperand ( <NUM_LIT> ) . isCImm ( ) && <STR_LIT> ) ; MIB . addCImm ( MI . getOperand ( <NUM_LIT> ) . getCImm ( ) ) ; } } else { return nullptr ; } break ; } case <STR_LIT> : case <STR_LIT> : { assert ( MI . getOperand ( <NUM_LIT> ) . isReg ( ) && MI . getOperand ( <NUM_LIT> ) . isReg ( ) && MI . getOperand ( <NUM_LIT> ) . isReg ( ) && MI . getOperand ( <NUM_LIT> ) . isReg ( ) && <STR_LIT> ) ; size_t OrigScore = TheStack . position ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) == <NUM_LIT> ; OrigScore += TheStack . position ( MI . getOperand ( <NUM_LIT> ) . getReg ( )


<s> A = A . addAttribute ( C , AttributeSet :: FunctionIndex , Attribute :: ReadNone ) ; A = A . addAttribute ( C , AttributeSet :: FunctionIndex , Attribute :: NoInline ) ; Value * F = ( M -> getOrInsertFunction ( Name , A , MyVoid , T , nullptr ) ) ; CallInst :: Create ( F , Params , <STR_LIT> , & Inst ) ; } else if ( const CallInst * CI = dyn_cast < CallInst > ( I ) ) { const Value * V = CI -> getCalledValue ( ) ; Type * T = nullptr ; if ( V ) T = V -> getType ( ) ; PointerType * PFT = nullptr ; if ( T ) PFT = dyn_cast < PointerType > ( T ) ; FunctionType * FT = nullptr ; if ( PFT ) FT = dyn_cast < FunctionType > (


<s> hoistAddrSpaceCastFromGEP ( GEP ) ; } if ( Operator * Cast = dyn_cast < Operator > ( MI -> getOperand ( Idx ) ) ) { if ( IsEliminableAddrSpaceCast ( Cast ) ) { MI -> setOperand ( Idx , Cast -> getOperand (


<s> return ( TM . getRelocationModel ( ) != Reloc ::

Static ? Reloc :: LocalOrGlobal : Reloc :: Global ) ;


<s> } unsigned NumElts = InVT . getVectorNumElements ( ) ; if ( InVT . getVectorElementType ( ) == <STR_LIT> && ! Subtarget -> hasFullFP16 ( ) ) { MVT NewVT = <STR_LIT> ( <STR_LIT> , NumElts ) ; SDLoc dl ( Op ) ; return DAG . getNode ( Op . getOpcode ( ) , dl , Op . getValueType ( ) , DAG . getNode ( <STR_LIT> , dl , NewVT , Op . getOperand ( <NUM_LIT> ) ) ) ; } if ( VT . getSizeInBits ( ) < InVT . getSizeInBits ( ) ) { SDLoc dl (


<s> iq2000_va_start ( valist , nextarg ) { \ fprintf ( STREAM , <STR_LIT> ) ; \ fprintf ( STREAM , <STR_LIT> ) ; \ fprintf ( STREAM , <STR_LIT> ) ; \ if ( Pmode == DImode ) \ { \ fprintf ( STREAM , <STR_LIT> ) ; \ fprintf ( STREAM , <STR_LIT> ) ; \ } \ else \ { \ fprintf ( STREAM , <STR_LIT> ) ; \ fprintf ( STREAM , <STR_LIT> ) ; \ } \ fprintf ( STREAM , <STR_LIT> ) ; \ fprintf (

STREAM , <STR_LIT> ) ; \ fprintf ( STREAM , <STR_LIT> ) ; \ fprintf ( STREAM , <STR_LIT> ) ; \ fprintf ( STREAM , <STR_LIT> ) ; \ }


<s> SWAP_INT ( fixed_regs [ i ] , fixed_regs [ i + <NUM_LIT> ] ) ; SWAP_INT ( call_used_regs [ i ] , call_used_regs [ i + <NUM_LIT> ] ) ; SWAP_INT ( call_really_used_regs [ i ] , call_really_used_regs [ i + <NUM_LIT> ] ) ; SWAP_STRING ( reg_names [ i ] , reg_names [ i


<s> if ( ST -> hasMVEIntegerOps ( ) ) { if ( Opcode == Instruction :: Load && isLegalMaskedLoad ( Src , Alignment ) ) return ST -> getMVEVectorCostFactor ( CostKind ) ; if ( Opcode == Instruction :: Store && isLegalMaskedStore ( Src , Alignment ) ) return


<s> bool isImm0_15 ( ) const { if ( ! isImm ( ) ) return false ; const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; if ( ! CE ) return false ; int64_t Value = CE


<s> bool <ISA_LIT>PassConfig :: addPreRegAlloc ( ) { if ( TM -> getOptLevel ( ) != CodeGenOpt :: None


<s> void <ISA_LIT>InstPrinter :: printMemOperand ( const MCInst * MI , int OpNo , raw_ostream & O , const char * Modifier ) { O << <STR_LIT> ; printOperand ( MI , OpNo , O , NULL ) ; O << <STR_LIT> ; printOperand ( MI , OpNo + <NUM_LIT> , O , NULL ) ; O << <STR_LIT>


<s> const MCInstrDesc & Desc = MI . getDesc ( ) ; if ( ( Desc . TSFlags & <STR_LIT> ) == <STR_LIT> ) return <NUM_LIT> ; if ( Desc . TSFlags & <STR_LIT> ) REX |= <NUM_LIT> << <NUM_LIT> ; unsigned NumOps = Desc . getNumOperands ( ) ; if ( NumOps ) { bool isTwoAddr = NumOps > <NUM_LIT> && Desc . getOperandConstraint ( <NUM_LIT> , MCOI :: TIED_TO ) != - <NUM_LIT> ; unsigned i = isTwoAddr ? <NUM_LIT> : <NUM_LIT> ; for ( unsigned e = NumOps ; i != e ; ++ i ) { const MachineOperand & MO = MI . getOperand ( i ) ; if ( MO . isReg ( ) ) { unsigned Reg = MO . getReg ( ) ; if ( <STR_LIT> ( Reg ) ) REX |= <NUM_LIT> ; } } switch ( Desc . TSFlags & <STR_LIT> ) { case <STR_LIT> : { if ( <ISA_LIT>InstrInfo :: is<ISA_LIT>_64ExtendedReg ( MI . getOperand ( <NUM_LIT> ) ) ) REX |= <NUM_LIT> << <NUM_LIT> ; i = isTwoAddr ? <NUM_LIT> : <NUM_LIT> ; for ( unsigned e = NumOps ; i != e ; ++ i ) { const MachineOperand & MO = MI . getOperand ( i ) ; if ( <ISA_LIT>InstrInfo :: is<ISA_LIT>_64ExtendedReg ( MO ) ) REX |= <NUM_LIT> << <NUM_LIT> ; } break ; } case <STR_LIT> : { if ( <ISA_LIT>InstrInfo :: is<ISA_LIT>_64ExtendedReg ( MI . getOperand ( <NUM_LIT> ) ) ) REX |= <NUM_LIT> << <NUM_LIT> ; unsigned Bit = <NUM_LIT> ; i = isTwoAddr ? <NUM_LIT> : <NUM_LIT> ; for ( ; i != NumOps ; ++ i ) { const MachineOperand & MO = MI . getOperand ( i ) ; if ( MO . isReg ( ) ) { if ( <ISA_LIT>InstrInfo :: is<ISA_LIT>_64ExtendedReg ( MO ) ) REX |= <NUM_LIT> << Bit ; Bit ++


<s> } } else { int FI = MFI -> CreateFixedObject ( <NUM_LIT> , <NUM_LIT> * ( ArgNo - <NUM_LIT> ) , true , false ) ; SDValue FIN = DAG . getFrameIndex ( FI , <STR_LIT> ) ; ArgVal = DAG . getLoad ( ObjectVT , dl , Chain , FIN , NULL , <NUM_LIT> , false , false , <NUM_LIT> ) ; } InVals . push_back ( ArgVal ) ; } if ( isVarArg ) { VarArgsOffset = Ins . size ( ) * <NUM_LIT> ; std :: vector < SDValue > LS ; for ( int i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) { if ( TargetRegisterInfo :: isPhysicalRegister ( args_int [ i ] ) ) args_int [ i ] = AddLiveIn ( MF , args_int [ i ] , & <STR_LIT> ) ; SDValue argt = DAG . getCopyFromReg ( Chain , dl , args_int [ i ] , <STR_LIT> ) ; int FI = MFI -> CreateFixedObject ( <NUM_LIT> , - <NUM_LIT> * ( <NUM_LIT> - i ) , true , false ) ; if ( i == <NUM_LIT> ) VarArgsBase = FI ; SDValue SDFI = DAG . getFrameIndex ( FI , <STR_LIT> ) ; LS . push_back ( DAG . getStore ( Chain , dl , argt , SDFI , NULL , <NUM_LIT> , false , false , <NUM_LIT> ) ) ; if ( TargetRegisterInfo :: isPhysicalRegister ( args_float [ i ] ) ) args_float [ i ] = AddLiveIn ( MF , args_float [ i ] , & <STR_LIT> ) ; argt = DAG . getCopyFromReg ( Chain , dl , args_float [


<s> if ( IsThumb ) EmitThumbMappingSymbol ( ) ; else Emit<ISA_LIT>MappingSymbol ( )


<s> for ( ImmutableCallSite :: arg_iterator i = CS . arg_begin ( ) , e = CS . arg_end ( ) ; i != e ; ++ i ) { if ( IntrMemName && e - i <= <NUM_LIT> ) break ; <STR_LIT> Flags ; unsigned AttrInd = i - CS . arg_begin ( ) + <NUM_LIT> ; if ( CS . paramHasAttr ( AttrInd , Attribute :: SExt ) ) Flags . setSExt ( ) ; if ( CS . paramHasAttr ( AttrInd , Attribute :: ZExt ) ) Flags . setZExt ( ) ; if ( CS . paramHasAttr ( AttrInd , Attribute :: InReg ) || CS . paramHasAttr ( AttrInd , Attribute :: StructRet ) || CS . paramHasAttr ( AttrInd , Attribute :: Nest ) || CS . paramHasAttr ( AttrInd , Attribute :: ByVal ) ) return false ; Type * ArgTy = ( * i ) -> getType ( ) ; MVT ArgVT ; if ( ! isTypeLegal ( ArgTy , ArgVT ) && ArgVT != <STR_LIT> && ArgVT != <STR_LIT> && ArgVT != <STR_LIT> ) return false ; unsigned Arg = getRegForValue ( * i ) ; if ( Arg == <NUM_LIT> ) return false ; unsigned OriginalAlignment = TD . getABITypeAlignment ( ArgTy ) ; Flags . setOrigAlign ( OriginalAlignment ) ; Args . push_back ( * i ) ; ArgRegs . push_back ( Arg ) ; ArgVTs . push_back ( ArgVT ) ; ArgFlags . push_back ( Flags ) ; } SmallVector < unsigned , <NUM_LIT> > RegArgs ; unsigned NumBytes ; if ( ! ProcessCallArgs ( Args , ArgRegs , ArgVTs , ArgFlags , RegArgs , CC , NumBytes , isVarArg ) ) return false ; bool UseReg = false ; const GlobalValue * GV = dyn_cast < GlobalValue > ( Callee ) ; if ( ! GV || Enable<ISA_LIT>LongCalls ) UseReg = true ; unsigned CalleeReg = <NUM_LIT> ; if ( UseReg ) { if ( IntrMemName ) CalleeReg = getLibcallReg ( IntrMemName ) ; else CalleeReg = getRegForValue ( Callee ) ; if ( CalleeReg == <NUM_LIT> ) return false ; } unsigned CallOpc = <ISA_LIT>SelectCallOp ( UseReg ) ; MachineInstrBuilder MIB = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( CallOpc ) ) ; if ( isThumb2 ) AddDefaultPred ( MIB ) ; if ( UseReg ) MIB . addReg ( CalleeReg ) ; else if ( ! IntrMemName ) MIB . addGlobalAddress (


<s> } const MCExpr * Expr = MCSymbolRefExpr :: Create ( MCSym , getModifierVariantKind ( ACPV -> getModifier ( ) ) , OutContext ) ; if ( ACPV -> getPCAdjustment ( ) ) { MCSymbol * PCLabel = getPICLabel ( MAI -> getPrivateGlobalPrefix ( ) , getFunctionNumber ( ) , ACPV -> getLabelId ( ) , OutContext ) ; const MCExpr * PCRelExpr = MCSymbolRefExpr :: Create ( PCLabel , OutContext ) ; PCRelExpr = MCBinaryExpr :: CreateAdd ( PCRelExpr , MCConstantExpr :: Create ( ACPV -> getPCAdjustment ( ) , OutContext ) , OutContext ) ; if ( ACPV -> mustAddCurrentAddress ( ) ) { MCSymbol * DotSym = OutContext . CreateTempSymbol ( ) ; OutStreamer . EmitLabel ( DotSym ) ; const MCExpr * DotExpr = MCSymbolRefExpr :: Create ( DotSym , OutContext ) ; PCRelExpr = MCBinaryExpr :: CreateSub ( PCRelExpr , DotExpr , OutContext ) ; } Expr = MCBinaryExpr :: CreateSub ( Expr , PCRelExpr


<s> if ( TARGET_DSBT ) { struct cgraph_local_info * this_func ; if ( ! decl ) return false ; this_func = cgraph_node :: local_info ( current_function_decl ) ; return this_func -> local ; } return true


<s> SDLoc SL ( In ) ; Src = CurDAG -> getTargetConstantFP ( C -> getValueAPF ( ) , SL , C -> getValueType ( <NUM_LIT> ) ) ; } else Src = In ; return true


<s> return __builtin_aarch64_reduc_smin_scal_v4sf ( __a )


<s> assert ( ( ! OptForMinSize || OptForSize ) && <STR_LIT> ) ; for ( SelectionDAG :: allnodes_iterator I = CurDAG -> allnodes_begin ( ) , E = CurDAG -> allnodes_end ( ) ; I != E ; ) { SDNode * N = & * I ++ ; if ( OptLevel != CodeGenOpt :: None && ( ( N -> getOpcode ( ) == <STR_LIT> && ! Subtarget -> callRegIndirect ( ) ) || ( N -> getOpcode ( ) == <STR_LIT> && ( Subtarget -> is64Bit ( ) || ! getTargetMachine ( ) . isPositionIndependent ( ) ) ) ) ) { bool HasCallSeq = N -> getOpcode ( ) == <STR_LIT> ; SDValue Chain = N -> getOperand ( <NUM_LIT> ) ; SDValue Load = N -> getOperand ( <NUM_LIT> ) ; if ( ! isCalleeLoad ( Load , Chain , HasCallSeq ) ) continue ; moveBelowOrigChain ( CurDAG , Load , SDValue ( N , <NUM_LIT> ) , Chain ) ; ++ NumLoadMoved ; continue ; } if ( N -> getOpcode ( ) != <STR_LIT> && N -> getOpcode


<s> return Kind == Register && <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains (


<s> first_dreg_to_save = lastdreg ; for ( i = <NUM_LIT> , group = <NUM_LIT> ; i < XVECLEN ( op , <NUM_LIT> ) - <NUM_LIT> ; i ++ ) { rtx t = XVECEXP ( op , <NUM_LIT> , i ) ; rtx src , dest ; int regno ; if ( GET_CODE ( t ) != SET ) return <NUM_LIT> ; src = SET_SRC ( t ) ; dest = SET_DEST ( t ) ; if ( GET_CODE ( dest ) != MEM || ! REG_P ( src ) ) return <NUM_LIT> ; dest = XEXP ( dest , <NUM_LIT> ) ; if ( GET_CODE ( dest ) != PLUS || ! REG_P ( XEXP ( dest , <NUM_LIT> ) ) || REGNO ( XEXP ( dest , <NUM_LIT> ) ) != REG_SP || GET_CODE ( XEXP ( dest , <NUM_LIT> ) ) != CONST_INT || INTVAL ( XEXP ( dest , <NUM_LIT> ) ) != - i * <NUM_LIT> ) return <NUM_LIT> ; regno = REGNO ( src ) ; if ( group == <NUM_LIT> ) { if ( D_REGNO_P ( regno ) ) { group = <NUM_LIT> ; first_dreg_to_save = lastdreg = regno - REG_R0 ; } else if ( regno >= REG_P0 && regno <= REG_P7 ) { group = <NUM_LIT> ; first_preg_to_save = lastpreg = regno - REG_P0 ; } else return <NUM_LIT> ; continue ; } if ( group == <NUM_LIT> ) { if ( regno >= REG_P0 && regno <= REG_P7 ) { group = <NUM_LIT> ; first_preg_to_save = lastpreg = regno - REG_P0 ; } else if ( regno != REG_R0 + lastdreg + <NUM_LIT> ) return <NUM_LIT> ; else lastdreg ++


<s> const MCOperand & Op = MI -> getOperand ( OpNum ) ; <STR_LIT> CC = ( <STR_LIT> ) Op . getImm ( ) ; const char * Str = condCodeToString (


<s> MCRegisterInfo * X = new MCRegisterInfo ( ) ; Init<ISA_LIT>MCRegisterInfo ( X , <STR_LIT>


<s> O << <STR_LIT> ; printSrcIdx ( MI , OpNo , O


<s> assert ( TLI -> InstructionOpcodeToISD ( Opcode ) && <STR_LIT> ) ; return TargetTransformInfo :: getArithmeticInstrCost ( Opcode


<s> static SDValue lowerFABS32 ( SDValue Op , SelectionDAG & DAG , bool HasExtractInsert ) { SDLoc DL ( Op ) ; SDValue Res , Const1 = DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; SDValue X = ( Op . getValueType ( ) == <STR_LIT> ) ? DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) ) : DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) , Const1 ) ; if ( HasExtractInsert ) Res = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getRegister ( <STR_LIT> , <STR_LIT>

) , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) , Const1 , X ) ;


<s> ArrayRef < int > Mask = SV -> getMask ( ) ; bool CanFold = true ; for ( unsigned i = <NUM_LIT> , e = NumElts ; i != e && CanFold ; ++ i ) CanFold = Mask [ i ] == ( int ) ( ( i & <NUM_LIT> ) ? i + NumElts : i ) ; if ( CanFold ) { SDValue Op0 = N1 -> getOperand ( <NUM_LIT> ) ; SDValue Op1 = DAG . getNode ( <STR_LIT> , dl , VT , N1 -> getOperand ( <NUM_LIT> ) ) ; SDValue Sub = DAG . getNode ( <STR_LIT> , dl , VT , Op0 , Op1 ) ; SDValue Add = DAG . getNode ( <STR_LIT> , dl , VT , Op0 , Op1 ) ; return DAG . getVectorShuffle ( VT , dl , Sub , Add , Mask ) ; } } const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; if ( ! DCI . isBeforeLegalize ( ) && ! TLI . isTypeLegal ( VT . getVectorElementType ( ) ) ) return SDValue ( ) ; if ( Subtarget -> hasFp256 ( ) && VT . is256BitVector ( ) && N -> getOpcode ( ) == <STR_LIT> ) return PerformShuffleCombine256 ( N , DAG , DCI , Subtarget ) ; if ( ! DCI . isBeforeLegalize ( ) && DCI . isBeforeLegalizeOps ( ) && N1 . getOpcode ( ) == <STR_LIT> && N0 . hasOneUse ( ) && N0 . getOpcode ( ) == <STR_LIT> ) { SDValue BC0 = N0 . getOperand ( <NUM_LIT> ) ; EVT SVT = BC0 . getValueType ( ) ; unsigned Opcode = BC0 . getOpcode ( ) ; unsigned NumElts = VT . getVectorNumElements ( ) ; if ( BC0 . hasOneUse ( ) && SVT . isVector ( ) && SVT . getVectorNumElements ( ) * <NUM_LIT> == NumElts && TLI . isOperationLegal ( Opcode , VT ) ) { bool CanFold = false ; switch ( Opcode ) { default : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : CanFold = true ; } unsigned SVTNumElts = SVT . getVectorNumElements ( ) ; ShuffleVectorSDNode * SVOp = cast < ShuffleVectorSDNode


<s> SDValue <ISA_LIT>TargetLowering :: LowerImplicitParameter ( SelectionDAG & DAG , EVT VT , const SDLoc & DL , unsigned DwordOffset ) const { unsigned ByteOffset = DwordOffset * <NUM_LIT> ; PointerType * PtrType = PointerType :: get ( VT . getTypeForEVT ( * DAG . getContext ( ) ) , AMDGPUA<ISA_LIT> . PARAM_I_ADDRESS ) ; assert ( isInt < <NUM_LIT> > ( ByteOffset


<s> TargetPassConfig * <ISA_LIT>BaseTargetMachine :: createPassConfig ( PassManagerBase & PM ) { return new <ISA_LIT>PassConfig ( this , PM


<s> static const unsigned CalleeSavedRegs [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> ,


<s> assert ( ( ! Reg || Reg == <STR_LIT> ) && <STR_LIT> ) ; if ( CanFail ) return false ; State . addLoc ( CCValAssign :: getCustomMem ( ValNo , ValVT , State . AllocateStack ( <NUM_LIT> , <NUM_LIT> ) , LocVT , LocInfo ) ) ; return true ; } unsigned i ; for ( i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) if ( HiRegList [ i ] == Reg ) break ; unsigned T = State . AllocateReg ( LoRegList [ i ] ) ; ( void ) T ; assert ( T == LoRegList [ i ]


<s> if ( ! crtl -> is_leaf && call_used_regs [ regno ] ) current_frame_info . save_regs [ regno ] = <NUM_LIT> ; else if ( df_regs_ever_live_p ( regno ) ) current_frame_info . save_regs [ regno ] = <NUM_LIT> ; else current_frame_info . save_regs [ regno ] = <NUM_LIT> ; } else { if ( df_regs_ever_live_p ( regno ) && ( ! call_used_regs [ regno ] || regno == RETURN_ADDRESS_REGNUM ) ) current_frame_info . save_regs [ regno ] = <NUM_LIT> ; else current_frame_info . save_regs [ regno ] = <NUM_LIT> ; } } if ( crtl -> calls_eh_return ) { unsigned int i ; for ( i = <NUM_LIT> ; ; ++ i ) { regno = EH_RETURN_DATA_REGNO


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( MI . getOperand ( <NUM_LIT> ) . isImm ( ) && ! MI . getOperand ( <NUM_LIT> ) . getImm ( ) && MI . getOperand ( <NUM_LIT> ) . isFI ( ) ) { FrameIndex = MI . getOperand ( <NUM_LIT> ) . getIndex ( ) ; return MI . getOperand ( <NUM_LIT> )


<s> SDLoc dl ( N ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; SDValue Cond = N -> getOperand ( <NUM_LIT> ) ; SDValue ConstTrue = CurDAG -> getConstant ( N -> getOpcode ( ) == <STR_LIT> ? - <NUM_LIT> : <NUM_LIT> , VT ) ; SDValue ConstFalse = CurDAG -> getConstant ( <NUM_LIT> , VT ) ; do { SDNode * User = * N -> use_begin ( ) ; if ( User -> getNumOperands ( ) != <NUM_LIT> ) break ; auto TryFold = [ this , N , User ] ( SDValue Val ) { SDValue UserO0 = User -> getOperand ( <NUM_LIT> ) , UserO1 = User -> getOperand ( <NUM_LIT> ) ; SDValue O0 = UserO0 . getNode ( ) == N ? Val : UserO0 ; SDValue O1 = UserO1 . getNode ( ) == N ? Val : UserO1 ; return CurDAG -> FoldConstantArithmetic ( User -> getOpcode ( ) , User -> getValueType ( <NUM_LIT> ) , O0 . getNode ( ) , O1 . getNode ( ) ) ; } ; SDValue TrueRes = TryFold ( ConstTrue ) ; if ( ! TrueRes ) break ; SDValue FalseRes = TryFold ( ConstFalse ) ; if ( ! FalseRes ) break ; uint64_t True = cast < ConstantSDNode > ( TrueRes ) -> getZExtValue ( ) , False = cast < ConstantSDNode > ( FalseRes ) -> getZExtValue ( ) ; if ( ! isInt < <NUM_LIT> > ( True ) || ! isInt < <NUM_LIT> > ( False ) ) break ; Res = CurDAG -> getSelect ( dl , User -> getValueType

( <NUM_LIT> ) , Cond , TrueRes , FalseRes ) ;


<s> Q . push_back ( C . Root ) ; unsigned Count = <NUM_LIT> ; const unsigned Limit = SimplifyLimit ; while ( ! Q . empty ( ) ) { if ( Count ++ >= Limit ) break ; Instruction * U = dyn_cast < Instruction > ( Q . pop_front_val ( ) ) ; if ( ! U || U -> getParent ( ) || ! C . Used . count ( U ) ) continue ; bool Changed = false ; for ( Rule & R : Rules ) { Value * W = R . Fn ( U , C . Ctx ) ; if ( ! W ) continue ; Changed = true ; C . record ( W ) ; C . replace (


<s> unsigned VSEW = ( VType >> <NUM_LIT> ) & <NUM_LIT> ; return static_cast < <ISA_LIT>VSEW > ( VSEW


<s> <ISA_LIT>FunctionInfo * <ISA_LIT>FI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; <ISA_LIT>FI -> adjustLoadArgsFI ( MFI ) ; <ISA_LIT>FI -> adjustStoreVarArgsFI ( MFI ) ; unsigned FrameSize = MFI -> getStackSize ( ) ; DEBUG ( dbgs ( ) << <STR_LIT> << FrameSize << <STR_LIT> ) ; unsigned TargetAlign = MF . getTarget ( ) . getFrameLowering ( ) -> getStackAlignment ( ) ; unsigned AlignMask = TargetAlign


<s> assert ( Subtarget . hasSSSE3 ( ) && <STR_LIT> ) ; SDValue In = Op . getOperand ( <NUM_LIT> ) ; SDLoc DL ( Op ) ; if ( VT == <STR_LIT> && ! Subtarget . hasBWI ( ) ) return splitVectorIntUnary ( Op , DAG ) ; unsigned NumElts = VT . getVectorNumElements ( ) ; assert ( VT . getScalarType ( ) == <STR_LIT> && <STR_LIT> ) ; if ( VT . is256BitVector ( ) && ! Subtarget . hasInt256 ( ) ) return splitVectorIntUnary ( Op , DAG ) ; SDValue NibbleMask = DAG . getConstant ( <NUM_LIT> , DL , VT ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , DL , VT , In , NibbleMask ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , DL , VT , In , DAG . getConstant ( <NUM_LIT> , DL , VT ) ) ; const int LoLUT [ <NUM_LIT> ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> ,


<s> CCState CCInfo ( CallConv , isVarArg , DAG . getMachineFunction ( ) , RVLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeCallResult ( Ins , RetCC_<ISA_LIT> ) ; for ( auto & Loc : RVLocs ) { Chain = DAG . getCopyFromReg ( Chain , dl , Loc . getLocReg ( ) , Loc . getValVT ( ) , InGlue ) . getValue ( <NUM_LIT> ) ; InGlue = Chain . getValue ( <NUM_LIT> ) ; InVals . push_back ( Chain . getValue (


<s> if ( TARGET_LP64 ) return xstrdup ( <STR_LIT>


<s> Reloc :: Model getEffectiveRelocModel ( Optional < Reloc :: Model


<s> TargetTriple ( TT ) , Has16BitInsts ( false ) , HasMadMixInsts ( false ) , FP32Denormals ( false ) , FPExceptions ( false ) , HasSDWA ( false ) , HasVOP3PInsts ( false ) , HasMulI24 ( true ) , HasMulU24 ( true ) , HasInv2PiInlineImm ( false ) , HasFminFmaxLegacy ( true ) , EnablePromoteAlloca ( false ) , HasTrigReducedRange ( false ) , MaxWavesPerEU ( <NUM_LIT> )

, LocalMemorySize ( <NUM_LIT> ) , WavefrontSize ( <NUM_LIT> ) {


<s> FunctionPass * llvm :: create<ISA_LIT>ISelDag ( <ISA_LIT>TargetMachine & TM


<s> bool selectBDXAddr20Pair ( SDValue Addr , SDValue & Base , SDValue & Disp , SDValue & Index ) { return selectBDXAddr ( <STR_LIT> , <STR_LIT> , Addr


<s> CmpInstr . RemoveOperand ( DeadNZCVIdx ) ; bool succeeded = UpdateOperandRegClass ( CmpInstr ) ; ( void ) succeeded ; assert ( succeeded && <STR_LIT> ) ; return true ; } assert ( ( CmpValue == <NUM_LIT> || CmpValue == <NUM_LIT> ) && <STR_LIT> ) ; if ( CmpValue != <NUM_LIT> || SrcReg2 != <NUM_LIT> ) return false ; if ( ! MRI -> use_nodbg_empty ( CmpInstr . getOperand ( <NUM_LIT> ) . getReg (


<s> return makeArrayRef ( <STR_LIT> . begin ( ) , <STR_LIT> .


<s> LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << MI ) ; const MachineOperand & BaseOp = MI . getOperand ( <NUM_LIT> ) ; Register Base = BaseOp . getReg ( ) ; const MachineOperand & Reg0Op = MI . getOperand ( <NUM_LIT> ) ; const MachineOperand & Reg1Op = MI . getOperand ( <NUM_LIT> ) ; if ( Reg0Op . getReg ( ) == Base || Reg1Op . getReg ( ) == Base ) return false ; Register PredReg ; <STR_LIT> Pred = getInstrPredicate ( MI , PredReg ) ; MachineBasicBlock :: iterator MBBI ( MI ) ; MachineBasicBlock & MBB = * MI . getParent ( ) ; int Offset ; MachineBasicBlock :: iterator MergeInstr = findIncDecBefore ( MBBI , Base , Pred , PredReg , Offset ) ; unsigned NewOpc ; if ( Offset == <NUM_LIT> || Offset == - <NUM_LIT> ) { NewOpc = Opcode == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; } else { MergeInstr = findIncDecAfter ( MBBI , Base , Pred , PredReg , Offset , TRI ) ; if ( MergeInstr == MBB . end ( ) ) return false ; NewOpc = Opcode == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; if ( ! isLegalAddressImm ( NewOpc , Offset , TII ) ) return false ; } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * MergeInstr ) ; MBB . erase ( MergeInstr ) ; DebugLoc DL = MI . getDebugLoc ( ) ; MachineInstrBuilder MIB = BuildMI ( MBB , MBBI , DL , TII -> get ( NewOpc ) ) ; if ( NewOpc == <STR_LIT> || NewOpc == <STR_LIT> ) { MIB . add ( Reg0Op ) . add ( Reg1Op ) . addReg ( BaseOp . getReg ( ) , RegState :: Define ) ; } else { assert ( NewOpc == <STR_LIT> || NewOpc == <STR_LIT> ) ; MIB . addReg ( BaseOp . getReg ( ) , RegState :: Define ) . add ( Reg0Op ) . add ( Reg1Op ) ; } MIB . addReg ( BaseOp . getReg ( ) , RegState :: Kill ) . addImm ( Offset ) . addImm ( Pred ) . addReg ( PredReg ) ; assert ( TII -> get ( Opcode ) . getNumOperands ( ) == <NUM_LIT> && TII -> get ( NewOpc ) . getNumOperands ( ) == <NUM_LIT> && <STR_LIT> ) ; for ( const MachineOperand & MO : MI . implicit_operands ( ) ) MIB . add ( MO ) ; MIB . cloneMemRefs ( MI )


<s> bool <ISA_LIT>RegisterInfo :: needsFrameBaseReg ( MachineInstr * MI , int64_t Offset ) const { if ( ! MI -> mayLoadOrStore ( ) ) return false ; int64_t FullOffset = Offset +


<s> MachineBasicBlock :: iterator MBBI = MBB . getFirstTerminator ( ) ; DebugLoc DL ; if ( MBBI != MBB . end ( ) ) DL = MBBI -> getDebugLoc ( ) ; if ( Subtarget . hasPAuth ( ) && MBBI != MBB . end ( ) && MBBI -> getOpcode ( ) == <STR_LIT> ) { BuildMI ( MBB , MBBI , DL , TII -> get ( MFI . shouldSignWithBKey ( ) ? <STR_LIT> : <STR_LIT> ) ) . copyImplicitOps ( * MBBI ) ; MBB . erase ( MBBI ) ; } else { BuildMI ( MBB , MBBI , DL , TII -> get ( MFI . shouldSignWithBKey ( ) ? <STR_LIT> : <STR_LIT> ) ) . setMIFlag


<s> MCSymbol * LabelSym = getContext ( ) . getOrCreateSymbol ( SymExpr -> getSymbol ( ) . getName ( ) ) ; const MCExpr * LabelExpr = MCSymbolRefExpr :: create ( LabelSym , getContext ( ) ) ; const MCExpr * Eight = MCConstantExpr :: create ( <NUM_LIT> , getContext ( ) ) ; const MCExpr * SubExpr = MCBinaryExpr :: createSub ( LabelExpr , Eight , getContext ( ) ) ; MCSymbol * CurrentLocation = getContext ( ) . createTempSymbol ( ) ; const MCExpr * CurrentLocationExpr = MCSymbolRefExpr :: create ( CurrentLocation , getContext ( ) ) ; const MCExpr * SubExpr2 = MCBinaryExpr :: createSub ( CurrentLocationExpr , SubExpr , getContext ( ) ) ; MCDataFragment * DF = static_cast < MCDataFragment * > ( LabelSym -> getFragment ( ) ) ; assert ( DF && <STR_LIT> ) ; MCFixupKind FixupKind = static_cast < MCFixupKind > ( FirstLiteralRelocationKind + ELF


<s> if ( regno > FIRST_PSEUDO_REGISTER ) return true ; if ( ( TARGET_FPU_SINGLE || TARGET_FPU_DOUBLE ) && NDS32_IS_FPR_REGNUM ( regno ) ) { if ( NDS32_IS_EXT_FPR_REGNUM ( regno ) ) return ( NDS32_FPR_REGNO_OK_FOR_DOUBLE ( regno ) && ( mode == DFmode ) ) ; else if ( mode == SFmode || mode == SImode ) return NDS32_FPR_REGNO_OK_FOR_SINGLE ( regno ) ; else if ( mode == DFmode ) return NDS32_FPR_REGNO_OK_FOR_DOUBLE ( regno ) ; return false ; } if ( regno <= NDS32_LAST_GPR_REGNUM ) return ( targetm . hard_regno_nregs ( regno , mode ) == <NUM_LIT> || ! ( ( regno


<s> <ISA_LIT>InstPrinter ( const MCAsmInfo & mai , const MCInstrInfo & mii , const MCRegisterInfo & mri ) : MCInstPrinter ( mai , mii , mri ) , InBundle ( false ) { switch ( mai . getAssemblerDialect


<s> InstructionSelector * getInstructionSelector ( ) const


<s> return ; case 'f' : if ( GET_CODE ( op ) == REG ) fputs ( reg_names [ REGNO ( op ) ] , file ) ; else fputs ( reg_names [ FP_FIRST_REGNUM ] , file ) ; return ; } switch ( GET_CODE ( op ) ) { case REG : if ( letter == 'd' ) fputs ( reg_names [ REGNO ( op ) + <NUM_LIT> ] , file ) ; else fputs ( reg_names [ REGNO ( op ) ] , file ) ; break ; case SYMBOL_REF : case LABEL_REF : case CONST : output_addr_const ( file , op ) ; break ; case MEM : visium_output_address ( file , GET_MODE ( op ) , XEXP ( op , <NUM_LIT> ) ) ; break ; case CONST_INT : fprintf ( file , HOST_WIDE_INT_PRINT_DEC , INTVAL ( op ) ) ; break ; case CODE_LABEL : asm_fprintf ( file , <STR_LIT> , CODE_LABEL_NUMBER ( op ) ) ; break ; case


<s> case AARCH64_BUILTIN_RSQRT_DF : gen = gen_rsqrtdf2 ; break ; case AARCH64_BUILTIN_RSQRT_SF : gen = gen_rsqrtsf2 ; break ; case AARCH64_BUILTIN_RSQRT_V2DF : gen = gen_rsqrtv2df2 ; break ; case AARCH64_BUILTIN_RSQRT_V2SF : gen = gen_rsqrtv2sf2 ; break ; case AARCH64_BUILTIN_RSQRT_V4SF : gen = gen_rsqrtv4sf2 ; break ; default : gcc_unreachable ( ) ; } if ( ! target ) target = gen_reg_rtx


<s> unsigned LocMemOffset = VA . getLocMemOffset ( ) ; SDValue PtrOff = DAG . getIntPtrConstant ( LocMemOffset , dl ) ; PtrOff = DAG . getNode ( <STR_LIT> , dl , getPointerTy ( DAG . getDataLayout ( ) ) , StackPtr , PtrOff ) ; if ( Flags . isByVal ( ) ) return CreateCopyOfByValArgument ( Arg , PtrOff , Chain , Flags , DAG , dl ) ; MachineMemOperand :: Flags MMOFlags = MachineMemOperand :: MONone ; if ( Flags . sgx_type ) MMOFlags |= MachineMemOperand :: MOTargetFlag1 ; return DAG . getStore ( Chain , dl , Arg , PtrOff , MachinePointerInfo :: getStack ( DAG . getMachineFunction ( ) , LocMemOffset )


<s> LoadSDNode * LoadSDN = cast < LoadSDNode > ( LD ) ; EVT MemVT = LoadSDN -> getMemoryVT ( ) ; if ( MemVT != VT . getVectorElementType ( ) ) return SDValue ( ) ; for ( SDNode :: use_iterator UI = LD -> use_begin ( ) , UE = LD -> use_end ( ) ; UI != UE ; ++ UI ) { if ( UI . getUse ( ) . getResNo ( ) == <NUM_LIT> ) continue ; if ( * UI != N ) return SDValue ( ) ; } SDValue Addr = LD -> getOperand ( <NUM_LIT> ) ; SDValue Vector = N -> getOperand ( <NUM_LIT> ) ; for ( SDNode :: use_iterator UI = Addr . getNode ( ) -> use_begin ( ) , UE = Addr . getNode ( ) -> use_end ( ) ; UI != UE ; ++ UI ) { SDNode * User = * UI ; if ( User -> getOpcode ( ) != <STR_LIT> || UI . getUse ( ) . getResNo ( ) != Addr . getResNo ( ) ) continue ; if ( User -> isPredecessorOf ( LD ) || LD -> isPredecessorOf ( User ) ) continue ; if ( User -> isPredecessorOf ( Vector . getNode ( ) ) ) continue ; SDValue Inc = User -> getOperand ( User -> getOperand ( <NUM_LIT> ) == Addr ? <NUM_LIT> : <NUM_LIT> ) ; if ( ConstantSDNode * CInc = dyn_cast < ConstantSDNode > ( Inc . getNode ( ) ) ) { uint32_t IncVal = CInc -> getZExtValue ( ) ; unsigned NumBytes = VT . getScalarSizeInBits (


<s> if ( VT . isVector ( ) ) { unsigned NumElts = VT . getVectorNumElements ( ) ; EVT EltVT = VT . getVectorElementType ( ) ; if ( EltVT == <STR_LIT> && NumElts % <NUM_LIT> == <NUM_LIT> ) { EltVT = <STR_LIT> ; NumElts /= <NUM_LIT> ; } for ( unsigned j = <NUM_LIT> ; j != NumElts ; ++ j ) { ValueVTs . push_back (


<s> for ( SDep & SuccDep : SU -> Succs ) { SUnit * Succ = SuccDep . getSUnit ( ) ; if ( SuccDep . isWeak ( ) || Succ -> NodeNum >= DAGSize ) continue ; SUColors . insert ( CurrentColoring [ Succ -> NodeNum


<s> EVT VT = N -> getValueType ( <NUM_LIT> ) ; SDValue N0 = N -> getOperand ( <NUM_LIT> ) ; SDValue N1 = N -> getOperand ( <NUM_LIT> ) ; SDLoc DL ( N ) ; if ( VT != <STR_LIT> && VT != <STR_LIT> ) return SDValue ( ) ; if ( N1 . getOpcode ( ) == <STR_LIT> ) std :: swap ( N0 , N1 ) ; if ( N0 . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; SDValue N00 = N0 -> getOperand ( <NUM_LIT> ) ; SDValue N01 = N0 -> getOperand ( <NUM_LIT> ) ; N01 = peekThroughBitcasts ( N01 ) ; if ( ! <STR_LIT> ( N01 . getNode ( ) ) ) { if ( ! VT . is256BitVector ( ) || N01 ->


<s> extern __inline void __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) _wrpkru ( unsigned int key ) { return __builtin_ia32_wrpkru ( key )


<s> for ( auto & R : SGPRToVGPRSpills ) { if ( R . first != FramePointerSaveIndex ) MFI . RemoveStackObject ( R . first ) ; } for ( int i = MFI . getObjectIndexBegin ( ) , e = MFI . getObjectIndexEnd ( )


<s> SDValue Chain = Op -> getOperand ( <NUM_LIT> ) ; SDValue RMValue = Op -> getOperand ( <NUM_LIT> ) ; SDValue SysRegNo = DAG . getConstant ( <STR_LIT> ( <STR_LIT> ) -> Encoding , DL , XLenVT ) ; static const unsigned Table = ( <STR_LIT> << <NUM_LIT> * int ( RoundingMode :: NearestTiesToEven ) ) | ( <STR_LIT> << <NUM_LIT> * int ( RoundingMode :: TowardZero ) ) | ( <STR_LIT> << <NUM_LIT> * int ( RoundingMode :: TowardNegative ) ) | ( <STR_LIT> << <NUM_LIT> * int ( RoundingMode :: TowardPositive ) ) | ( <STR_LIT> << <NUM_LIT> * int ( RoundingMode :: NearestTiesToAway ) ) ; SDValue Shift = DAG . getNode ( <STR_LIT> , DL , XLenVT , RMValue , DAG . getConstant ( <NUM_LIT> , DL , XLenVT ) ) ; SDValue Shifted = DAG . getNode ( <STR_LIT> , DL , XLenVT , DAG . getConstant ( Table , DL , XLenVT ) , Shift ) ; RMValue = DAG . getNode ( <STR_LIT> , DL , XLenVT , Shifted , DAG . getConstant ( <NUM_LIT> , DL , XLenVT ) ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Chain ,


<s> Register BasePtr = MRI . createVirtualRegister ( PtrRC ) ; FI -> setBasePointerVreg ( BasePtr ) ; BuildMI ( MBB , InsertPt , DL , TII -> get ( <STR_LIT> ) , BasePtr ) . addReg ( SPReg ) ; } if ( StackSize ) { Register OffsetReg = MRI . createVirtualRegister ( PtrRC ) ; BuildMI ( MBB , InsertPt , DL , TII -> get ( <STR_LIT> ) , OffsetReg ) . addImm ( StackSize ) ; BuildMI ( MBB , InsertPt , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( SPReg ) . addReg ( OffsetReg ) ; } if ( HasBP ) { Register BitmaskReg = MRI . createVirtualRegister ( PtrRC ) ; unsigned Alignment = MFI . getMaxAlignment ( ) ; assert ( ( <NUM_LIT> << countTrailingZeros ( Alignment ) ) == Alignment && <STR_LIT> ) ; BuildMI ( MBB , InsertPt , DL , TII -> get ( <STR_LIT> ) , BitmaskReg ) . addImm ( ( int ) ~ ( Alignment - <NUM_LIT> ) ) ; BuildMI ( MBB , InsertPt , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( BitmaskReg ) ; } if ( hasFP (


<s> case <STR_LIT> : case <STR_LIT> : { SDValue Src0 = Node -> getOperand ( <NUM_LIT> ) ; SDValue Src1 = Node -> getOperand ( <NUM_LIT> ) ; SDValue Src2 = Node -> getOperand ( <NUM_LIT> ) ; if ( ( Src0 . isMachineOpcode ( ) && Src0 . getMachineOpcode ( ) != <STR_LIT> ) && ( Src0 == Src1 || Src0 == Src2 ) ) break ; MVT VT = Src0 . getValueType ( ) . getSimpleVT ( ) ; const TargetRegisterClass * RC = getRegClassFor ( VT ) ; MachineRegisterInfo & MRI = DAG . getMachineFunction ( ) . getRegInfo ( ) ; SDValue UndefReg = DAG . getRegister ( MRI . createVirtualRegister ( RC ) , VT ) ; SDValue ImpDef = DAG . getCopyToReg ( DAG . getEntryNode ( ) , SDLoc ( Node ) , UndefReg , Src0 , SDValue ( ) ) ; if ( Src0 . isMachineOpcode ( ) && Src0 . getMachineOpcode ( ) == <STR_LIT> ) { if ( Src1 . isMachineOpcode ( ) && Src1 . getMachineOpcode ( ) != <STR_LIT> ) Src0 = Src1 ; else if ( Src2 . isMachineOpcode ( ) && Src2 . getMachineOpcode ( ) != <STR_LIT> ) Src0 = Src2 ; else { assert ( Src1 . getMachineOpcode ( ) == <STR_LIT> ) ; Src0 = UndefReg ; Src1 = UndefReg ; } } else break ; SmallVector < SDValue , <NUM_LIT> > Ops = { Src0 , Src1 , Src2 } ; for ( unsigned I = <NUM_LIT> , N = Node -> getNumOperands ( ) ; I != N ; ++ I ) Ops . push_back ( Node -> getOperand ( I ) ) ; Ops . push_back ( ImpDef . getValue ( <NUM_LIT> ) ) ; return DAG . getMachineNode ( Opcode , SDLoc ( Node ) , Node -> getVTList ( ) , Ops ) ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { unsigned NumOps = Node -> getNumOperands ( ) ; SDValue OldChain = Node -> getOperand ( NumOps - <NUM_LIT> ) ; if ( OldChain . getValueType ( ) !=


<s> } else { assert ( AFI -> getTailCallReservedStack ( ) == <NUM_LIT> && <STR_LIT> ) ; const unsigned VarArgsArea = AFI -> getVarArgsGPRSize ( ) ; const unsigned UnwindHelpObject = ( MF . hasEHFunclets ( ) ? <NUM_LIT> :


<s> ProgInfo . ScratchSize = Info . PrivateSegmentSize ; ProgInfo . VCCUsed = Info . UsesVCC ; ProgInfo . FlatUsed = Info . UsesFlatScratch ; ProgInfo . DynamicCallStack = Info . HasDynamicallySizedStack || Info . HasRecursion ; if ( ! isUInt < <NUM_LIT> > ( ProgInfo . ScratchSize ) ) { DiagnosticInfoStackSize DiagStackSize ( MF . getFunction ( ) , ProgInfo . ScratchSize , DS_Error ) ; MF . getFunction ( ) . getContext ( ) . diagnose ( DiagStackSize ) ; } const GCNSubtarget & STM = MF . getSubtarget < GCNSubtarget > ( ) ; const <ISA_LIT>MachineFunctionInfo * MFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; unsigned ExtraSGPRs = IsaInfo :: getNumExtraSGPRs ( & STM , ProgInfo . VCCUsed , ProgInfo . FlatUsed ) ; if ( STM . getGeneration ( ) >= <ISA_LIT>Subtarget :: VOLCANIC_ISLANDS && ! STM . hasSGPRInitBug ( ) ) { unsigned MaxAddressableNumSGPRs = STM . getAddressableNumSGPRs ( ) ; if ( ProgInfo . NumSGPR > MaxAddressableNumSGPRs ) { LLVMContext & Ctx = MF . getFunction ( ) . getContext ( ) ; DiagnosticInfoResourceLimit Diag ( MF . getFunction ( ) , <STR_LIT> , ProgInfo . NumSGPR , DS_Error , DK_ResourceLimit , MaxAddressableNumSGPRs ) ; Ctx . diagnose ( Diag ) ; ProgInfo . NumSGPR = MaxAddressableNumSGPRs - <NUM_LIT> ; } } ProgInfo . NumSGPR += ExtraSGPRs ; unsigned WaveDispatchNumSGPR = <NUM_LIT> , WaveDispatchNumVGPR = <NUM_LIT> ; for ( auto & Arg : MF . getFunction ( ) . args ( ) ) { unsigned NumRegs = ( Arg . getType ( ) -> getPrimitiveSizeInBits ( ) + <NUM_LIT> ) / <NUM_LIT> ; if ( Arg . hasAttribute ( Attribute :: InReg ) ) WaveDispatchNumSGPR += NumRegs ; else WaveDispatchNumVGPR += NumRegs ; } ProgInfo . NumSGPR = std :: max ( ProgInfo . NumSGPR , WaveDispatchNumSGPR ) ; ProgInfo . NumVGPR = std :: max ( ProgInfo . NumVGPR , WaveDispatchNumVGPR ) ; ProgInfo . NumSGPRsForWavesPerEU = std :: max ( std :: max ( ProgInfo . NumSGPR , <NUM_LIT> ) , STM . getMinNumSGPRs ( MFI -> getMaxWavesPerEU ( ) ) ) ; ProgInfo . NumVGPRsForWavesPerEU = std :: max ( std :: max ( ProgInfo . NumVGPR , <NUM_LIT> ) , STM . getMinNumVGPRs ( MFI -> getMaxWavesPerEU ( ) ) ) ; if ( STM . getGeneration ( ) <= <ISA_LIT>Subtarget :: SEA_ISLANDS


<s> virtual <ISA_LIT>TargetLowering * getTargetLowering (


<s> __builtin_ia32_compressstoresf128_mask ( ( __v4sf * ) __P , ( __v4sf ) __A , (


<s> <ISA_LIT>PostLegalizerCombinerInfo ( bool EnableOpt , bool OptSize , bool MinSize , GISelKnownBits * KB , MachineDominatorTree * MDT ) : CombinerInfo ( true , false , nullptr , EnableOpt , OptSize , MinSize ) , KB ( KB ) , MDT ( MDT ) { if ( ! Generated . parseCommandLineOption ( ) ) report_fatal_error


<s> sh_cpu = PROCESSOR_SH1 ; assembler_dialect = <NUM_LIT> ; if ( TARGET_SH2 ) sh_cpu = PROCESSOR_SH2 ; if ( TARGET_SH2E ) sh_cpu = PROCESSOR_SH2E ; if ( TARGET_SH2A ) sh_cpu = PROCESSOR_SH2A ; if ( TARGET_SH3 ) sh_cpu = PROCESSOR_SH3 ; if ( TARGET_SH3E ) sh_cpu = PROCESSOR_SH3E ; if ( TARGET_SH4 ) { assembler_dialect = <NUM_LIT> ; sh_cpu = PROCESSOR_SH4 ; } if ( TARGET_SH4A ) { assembler_dialect = <NUM_LIT> ; sh_cpu = PROCESSOR_SH4A ; } if ( ! TARGET_SH3 && TARGET_USERMODE ) TARGET_USERMODE = false ; if ( ! strcmp ( sh_div_str , <STR_LIT> ) ) sh_div_strategy = SH_DIV_CALL_DIV1 ; else if ( ! strcmp ( sh_div_str , <STR_LIT> ) && TARGET_FPU_ANY ) sh_div_strategy = SH_DIV_CALL_FP ; else if ( ! strcmp ( sh_div_str , <STR_LIT> ) && TARGET_DYNSHIFT ) sh_div_strategy = SH_DIV_CALL_TABLE ; else { if ( TARGET_HARD_SH4 ) sh_div_strategy = SH_DIV_CALL_TABLE ; else if ( TARGET_SH2A ) sh_div_strategy = SH_DIV_INTRINSIC ; else sh_div_strategy = SH_DIV_CALL_DIV1 ; } if ( sh_divsi3_libfunc [ <NUM_LIT> ] ) ; else if ( TARGET_DIVIDE_CALL_FP ) sh_divsi3_libfunc = <STR_LIT> ; else if ( TARGET_DIVIDE_CALL_TABLE ) sh_divsi3_libfunc = <STR_LIT> ; else sh_divsi3_libfunc = <STR_LIT> ; if ( sh_branch_cost == - <NUM_LIT> ) { sh_branch_cost = <NUM_LIT> ; } if ( ! global_options_set . x_TARGET_ZDCBRANCH && TARGET_HARD_SH4 ) TARGET_ZDCBRANCH = <NUM_LIT> ; if ( TARGET_FDPIC && ! flag_pic ) flag_pic = <NUM_LIT> ; for ( regno = <NUM_LIT> ; regno < FIRST_PSEUDO_REGISTER ; regno ++ ) if ( ! VALID_REGISTER_P ( regno ) ) sh_register_names [ regno ] [ <NUM_LIT> ] = '\0' ; for ( regno = <NUM_LIT> ; regno < ADDREGNAMES_SIZE ; regno ++ ) if ( ! VALID_REGISTER_P ( ADDREGNAMES_REGNO ( regno ) ) ) sh_additional_register_names [ regno ] [ <NUM_LIT> ] = '\0' ; if ( flag_pic && ! TARGET_PREFERGOT ) flag_no_function_cse = <NUM_LIT> ; if ( targetm . small_register_classes_for_mode_p ( VOIDmode ) ) { if ( ! TARGET_HARD_SH4 || flag_pic ) flag_schedule_insns = <NUM_LIT> ; else if ( flag_exceptions ) { if ( flag_schedule_insns && global_options_set . x_flag_schedule_insns ) warning ( <NUM_LIT> , <STR_LIT> <STR_LIT> ) ; flag_schedule_insns = <NUM_LIT> ; } else if ( flag_schedule_insns && ! global_options_set . x_flag_schedule_insns ) flag_schedule_insns = <NUM_LIT> ; } if ( ( flag_unwind_tables || flag_asynchronous_unwind_tables || flag_exceptions || flag_non_call_exceptions ) && flag_omit_frame_pointer && ! TARGET_ACCUMULATE_OUTGOING_ARGS ) { warning ( <NUM_LIT> , <STR_LIT> <STR_LIT> ) ; TARGET_ACCUMULATE_OUTGOING_ARGS = <NUM_LIT> ; } if ( flag_unsafe_math_optimizations


<s> static void MoveBelowTokenFactor ( SelectionDAG * CurDAG , SDValue Load , SDValue Store , SDValue TF ) { SmallVector < SDValue , <NUM_LIT> > Ops ; for ( unsigned i = <NUM_LIT> , e = TF . getNode ( ) -> getNumOperands ( ) ; i != e ; ++ i ) if ( Load . getNode ( ) == TF . getOperand ( i ) . getNode (

) ) Ops . push_back ( Load . getOperand ( <NUM_LIT> ) ) ;


<s> machine_mode mode = GET_MODE ( e . target ) ; rtx vlenb = gen_int_mode ( BYTES_PER_RISCV_VECTOR


<s> public : <ISA_LIT>MCInstLower ( MCContext & ctx , Mangler & mang , AsmPrinter & printer ) : Ctx ( ctx ) , Mang ( mang ) , Printer ( printer ) { } void Lower ( const MachineInstr * MI , MCInst & OutMI


<s> int64_t Val = CE -> getValue ( ) ; return ( Val == INT32_MIN ) || ( Val > -


<s> InstructionSelector :: setupMF ( MF , KB , CoverageInfo , PSI , BFI , AA ) ; MIB . setMF ( MF ) ; ProduceNonFlagSettingCondBr = ! MF . getFunction ( ) . hasFnAttribute ( Attribute :: SpeculativeLoadHardening ) ; MFReturnAddr = Register (


<s> } if ( Load -> getAddressSpace ( ) == <STR_LIT> && isa < GlobalVariable > ( GetUnderlyingObject ( Load -> getMemOperand ( ) -> getValue ( ) ) ) ) { SDValue Ptr = DAG . getZExtOrTrunc ( Load -> getBasePtr ( ) , DL , getPointerTy ( <STR_LIT> ) ) ; Ptr = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Ptr , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , DL , Op -> getVTList ( ) , Load -> getChain ( ) , Ptr , DAG . getTargetConstant ( <NUM_LIT> , <STR_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; } if ( Load -> getAddressSpace ( ) != <STR_LIT> || ExtType == <STR_LIT> || Load -> getMemoryVT ( ) . bitsGE ( <STR_LIT> ) ) return SDValue ( ) ; SDValue Ptr = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Load -> getBasePtr ( ) , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDValue Ret = DAG . getNode ( <STR_LIT> , DL , Op . getValueType ( ) , Load -> getChain ( ) , Ptr , DAG . getTargetConstant ( <NUM_LIT> , <STR_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; SDValue ByteIdx = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Load -> getBasePtr ( ) , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDValue ShiftAmt = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , ByteIdx , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; Ret = DAG . getNode ( <STR_LIT> , DL ,


<s> } if ( DestAS == <ISA_LIT>AS :: CONSTANT_ADDRESS_32BIT ) { B . buildExtract ( Dst , Src , <NUM_LIT> ) ; MI . eraseFromParent ( ) ; return true ; } if ( SrcAS == <ISA_LIT>AS :: CONSTANT_ADDRESS_32BIT ) { const <ISA_LIT>MachineFunctionInfo * Info = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; uint32_t AddrHiVal = Info -> get32BitAddressHighBits ( ) ; auto HighAddr = B . buildConstant ( LLT :: pointer ( <ISA_LIT>AS :: CONSTANT_ADDRESS_32BIT , <NUM_LIT> ) , AddrHiVal ) ; B . buildMerge ( Dst , { Src , HighAddr } ) ; MI . eraseFromParent ( ) ; return true ; } if ( SrcAS == <ISA_LIT>AS :: FLAT_ADDRESS ) { assert ( DestAS == <ISA_LIT>AS :: LOCAL_ADDRESS || DestAS == <ISA_LIT>AS :: PRIVATE_ADDRESS ) ; if ( isKnownNonNull ( Src , MRI , TM , SrcAS ) ) { B . buildExtract ( Dst , Src , <NUM_LIT> ) ; MI . eraseFromParent ( ) ; return true ; } unsigned NullVal = TM . getNullPointerValue ( DestAS ) ; auto SegmentNull = B . buildConstant ( DstTy , NullVal ) ; auto FlatNull = B . buildConstant ( SrcTy , <NUM_LIT> ) ; auto PtrLo32 = B . buildExtract ( DstTy , Src , <NUM_LIT> ) ; auto CmpRes = B . buildICmp ( CmpInst :: ICMP_NE , LLT :: scalar ( <NUM_LIT> ) , Src , FlatNull . getReg ( <NUM_LIT> ) ) ; B . buildSelect ( Dst , CmpRes , PtrLo32 , SegmentNull . getReg ( <NUM_LIT> ) ) ; MI . eraseFromParent ( ) ; return true ; } if ( SrcAS != <ISA_LIT>AS :: LOCAL_ADDRESS && SrcAS != <ISA_LIT>AS :: PRIVATE_ADDRESS ) return false ; if ( ! ST . hasFlatAddressSpace ( ) ) return false ; Register ApertureReg = getSegmentAperture ( SrcAS , MRI , B ) ; if ( ! ApertureReg . isValid ( ) ) return false ; Register SrcAsInt = B . buildPtrToInt ( S32 , Src ) . getReg ( <NUM_LIT> ) ; auto BuildPtr = B . buildMerge ( DstTy , { SrcAsInt , ApertureReg } ) ; if ( isKnownNonNull ( Src , MRI , TM , SrcAS ) ) { B . buildCopy ( Dst , BuildPtr ) ; MI . eraseFromParent ( ) ; return true ; } auto SegmentNull = B . buildConstant ( SrcTy , TM .


<s> bool runOnMachineFunction ( MachineFunction & F ) { bool Changed = false ; if ( EnableDelJmp ) { MachineFunction :: iterator FJ = F . begin ( ) ; if ( FJ != F . end (


<s> auto F = MI -> getOperand ( <NUM_LIT> ) . getFPImm ( ) -> getValueAPF ( ) ; if ( F . isNaN ( ) && F . isSignaling ( ) ) return false ; return ! F . isDenormal ( ) || denormalsEnabledForType ( MRI . getType ( Reg ) , MF ) ; } if ( MaxDepth == <NUM_LIT> ) return false ; switch ( Opcode ) { case <STR_LIT> : case <STR_LIT>


<s> void <ISA_LIT>SEFrameLowering :: determineCalleeSaves ( MachineFunction & MF , BitVector & SavedRegs , RegScavenger * RS ) const { TargetFrameLowering :: determineCalleeSaves ( MF , SavedRegs , RS ) ; <ISA_LIT>FunctionInfo * <ISA_LIT>FI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; <ISA_LIT>ABIInfo ABI = STI . getABI ( ) ; unsigned FP = ABI . GetFramePtr ( ) ; unsigned BP = ABI . IsN64 ( ) ? <STR_LIT> : <STR_LIT> ; if ( hasFP ( MF ) ) setAliasRegs ( MF , SavedRegs , FP ) ; if ( hasBP ( MF ) ) setAliasRegs ( MF , SavedRegs , BP ) ; if ( <ISA_LIT>FI -> callsEhReturn ( ) ) <ISA_LIT>FI -> createEhDataRegsFI ( ) ; if ( <ISA_LIT>FI -> isISR ( ) ) <ISA_LIT>FI -> createISRRegFI ( ) ; if ( ExpandPseudo ( MF ) . expand ( ) ) { const TargetRegisterClass * RC = STI . has<ISA_LIT>64 ( ) ? & <STR_LIT> : & <STR_LIT> ; int FI = MF . getFrameInfo ( ) . CreateStackObject ( RC -> getSize ( ) , RC -> getAlignment ( ) , false ) ; RS -> addScavengingFrameIndex ( FI ) ; } uint64_t MaxSPOffset = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) -> getIncomingArgSize ( ) + estimateStackSize ( MF ) ; if ( isInt < <NUM_LIT> > ( MaxSPOffset ) ) return ; const TargetRegisterClass * RC = ABI . ArePtrs64bit ( ) ? & <STR_LIT> : & <STR_LIT> ; int FI = MF . getFrameInfo ( ) . CreateStackObject ( RC -> getSize ( )


<s> return DAG . getNode ( <STR_LIT> , dl , PtrVT ) ; } case <STR_LIT> : { EVT Ty = Op . getValueType ( ) ; if ( Ty == <STR_LIT> ) { SDValue Result = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) ) ; Result = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Result ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Result ) ; } else if ( Ty . isVector ( ) && Ty . isInteger ( ) && isTypeLegal ( Ty ) ) { return DAG . getNode ( <STR_LIT> , dl , Ty , Op . getOperand ( <NUM_LIT> ) ) ; } else { report_fatal_error ( <STR_LIT> ) ; } } case <STR_LIT> : return DAG . getNode ( <STR_LIT> , dl , Op . getValueType ( ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , dl , Op . getValueType ( ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , dl , Op . getValueType ( ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , dl , Op . getValueType ( ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand


<s> inline vector signed short vec_cmpgtsh ( vector signed short a1 , vector signed short a2 ) { return ( vector signed short ) __builtin_altivec_vcmpgtsh ( ( vector signed short ) a1 , ( vector


<s> bool NeedSwap ; std :: tie ( CC , NeedSwap ) = <STR_LIT> ( CI -> getPredicate ( ) ) ; if ( CC > <STR_LIT> ) return false ; const Value * CmpLHS = CI -> getOperand ( <NUM_LIT> ) ; const Value * CmpRHS = CI -> getOperand ( <NUM_LIT> ) ; if ( NeedSwap ) std :: swap ( CmpLHS , CmpRHS ) ; EVT CmpVT = TLI . getValueType ( DL , CmpLHS -> getType ( ) ) ; if ( ! <ISA_LIT>FastEmitCompare ( CmpLHS , CmpRHS , CmpVT , CI -> getDebugLoc ( ) ) ) return false ; } else { unsigned CondReg = getRegForValue ( Cond ) ; if ( CondReg == <NUM_LIT> ) return false ; bool CondIsKill = hasTrivialKill ( Cond ) ; if ( MRI . getRegClass ( CondReg ) == & <STR_LIT> ) { unsigned KCondReg = CondReg ; CondReg = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: COPY ) , CondReg ) . addReg ( KCondReg , getKillRegState ( CondIsKill ) ) ; CondReg = fastEmitInst_extractsubreg ( <STR_LIT> , CondReg , true , <STR_LIT> ) ; } BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) ) . addReg ( CondReg , getKillRegState ( CondIsKill ) ) . addImm ( <NUM_LIT> ) ; } const Value * LHS = I -> getOperand ( <NUM_LIT> ) ; const Value * RHS = I -> getOperand ( <NUM_LIT> ) ; unsigned LHSReg = getRegForValue (


<s> if ( TARGET_FPU ) { clobbers . safe_push ( gen_rtx_REG ( CCmode , FCC_REGNUM ) ) ; SET_HARD_REG_BIT ( clobbered_regs , FCC_REGNUM ) ; } return NULL


<s> signed_width ( Size + <NUM_LIT> , Value , std :: string ( <STR_LIT> ) , Fixup ,


<s> return D ( <STR_LIT> , R ( a ) , R ( b


<s> assert ( ( VT . getScalarType ( ) == <STR_LIT> || VT . getScalarType ( ) == <STR_LIT> ) && <STR_LIT> ) ; assert ( ( Subtarget . hasVLX ( ) || ( ! VT . is128BitVector ( ) && ! VT . is256BitVector ( ) ) ) && <STR_LIT> ) ; SDValue Lo = V1 , Hi = V2 ; int Rotation = matchShuffleAsByteRotate ( Lo , Hi , Mask ) ; if ( Rotation <= <NUM_LIT>


<s> RegisterMCAsmParser < <ISA_LIT>AsmParser > X (


<s> continue ; } uint64_t PermuteOp = ( M >> <NUM_LIT> ) & <NUM_LIT> ; if ( PermuteOp == <NUM_LIT> ) { ShuffleMask . push_back ( SM_SentinelZero ) ; continue ; } if ( PermuteOp != <NUM_LIT> ) { ShuffleMask . clear ( ) ; return ; } uint64_t Index = M & <NUM_LIT> ; ShuffleMask . push_back ( (


<s> if ( N0 -> getOpcode ( ) == <STR_LIT> && N0 -> getOperand ( <NUM_LIT> ) -> getValueType ( <NUM_LIT> ) . is256BitVector ( ) && Subtarget . hasAVX ( ) ) { SExtVT = <STR_LIT> ; FPCastVT = <STR_LIT> ; } break ; case <STR_LIT> : SExtVT = <STR_LIT> ; break ; case <STR_LIT> : SExtVT = <STR_LIT> ; break ; } ; SDLoc DL ( BitCast ) ; SDValue V = DAG . getSExtOrTrunc ( N0 , DL , SExtVT ) ; if ( SExtVT == <STR_LIT> && ! Subtarget . hasInt256 ( ) ) { const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; MVT ShiftTy = TLI . getScalarShiftAmountTy ( DAG . getDataLayout ( ) , <STR_LIT> ) ; SDValue Lo = extract128BitVector ( V , <NUM_LIT> , DAG , DL ) ; SDValue Hi = extract128BitVector ( V , <NUM_LIT> , DAG , DL ) ; Lo = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Lo ) ; Hi = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Hi ) ; Hi = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Hi , DAG . getConstant ( <NUM_LIT> , DL , ShiftTy ) ) ; V = DAG . getNode ( <STR_LIT> , DL


<s> void \ fini_section ( ) \ { \ if ( in_section != in_fini ) \ { \ fprintf ( asm_out_file , <STR_LIT> , FINI_SECTION_ASM_OP ) ; \ in_section =


<s> static bool can_use_cdx_ldstw ( int regno , int basereg , int offset ) { if ( CDX_REG_P ( regno ) && CDX_REG_P ( basereg ) && ( offset & <NUM_LIT> ) == <NUM_LIT> && <NUM_LIT> <=

offset && offset < <NUM_LIT> ) return true ;


<s> MCOperand <ISA_LIT>Disassembler :: decodeBoolReg ( unsigned Val ) const { return STI . getFeatureBits ( ) [ <STR_LIT> ] ? decodeOperand_SReg_64 (


<s> void <ISA_LIT>InstPrinter :: printVectorList ( const MCInst * MI , unsigned OpNum , raw_ostream & O ) { assert ( Count >= <NUM_LIT> && Count <= <NUM_LIT> && <STR_LIT> ) ; unsigned Reg = MI -> getOperand ( OpNum ) . getReg ( ) ; std :: string LayoutStr = A64VectorLayoutToString ( Layout ) ; O << <STR_LIT> ; if ( Count > <NUM_LIT> ) { bool IsVec64 = ( Layout < <STR_LIT> ) ; unsigned SubRegIdx = IsVec64 ? <STR_LIT> : <STR_LIT> ; for ( unsigned I = <NUM_LIT> ; I < Count ; I ++ ) { std :: string Name = getRegisterName ( MRI . getSubReg ( Reg , SubRegIdx ++ ) ) ; Name [ <NUM_LIT> ] = 'v' ; O << Name << LayoutStr ; if ( I != Count - <NUM_LIT> ) O << <STR_LIT> ; } } else { std :: string Name = getRegisterName ( Reg


<s> } } else { switch ( model ) { case TLSModel :: GeneralDynamic : case TLSModel :: LocalDynamic : return LowerToTLSGeneralDynamicModel32 ( GA , DAG , getPointerTy ( ) ) ; case TLSModel :: InitialExec : case TLSModel :: LocalExec : return LowerToTLSExecModel ( GA , DAG , getPointerTy ( ) , model , false ) ; } } assert ( <NUM_LIT> && <STR_LIT> ) ; return SDValue


<s> return isUInt < <NUM_LIT> > ( ( short ) CN -> getZExtValue


<s> if ( aapcs_cp_arg_layout [ slot ] . allocate ( pcum , mode , type ) ) return ; pcum -> aapcs_cprc_failed [ slot ] = true ; pcum -> can_split = false ; } gcc_assert ( pcum -> can_split == false ) ; return ; } } ncrn = pcum -> aapcs_ncrn ; if ( ncrn & <NUM_LIT> ) { int res = arm_needs_doubleword_align ( mode , type ) ; if ( res < <NUM_LIT> && warn_psabi && currently_expanding_gimple_stmt ) inform ( input_location , <STR_LIT> <STR_LIT> , type ) ; else if ( res > <NUM_LIT> ) ncrn ++ ; } nregs = ARM_NUM_REGS2 ( mode , type ) ; gcc_assert ( nregs >= <NUM_LIT> ) ; nregs2 = nregs ? nregs : <NUM_LIT> ; if ( ncrn + nregs2 <= NUM_ARG_REGS ) { pcum -> aapcs_reg = gen_rtx_REG ( mode , ncrn ) ; pcum -> aapcs_next_ncrn = ncrn + nregs ; return ; } if ( ncrn < NUM_ARG_REGS && pcum -> can_split ) { pcum -> aapcs_reg = gen_rtx_REG ( mode ,


<s> unsigned BitWidth = IsWInstruction ? <NUM_LIT> : VT . getSizeInBits ( ) ; assert ( isPowerOf2_32 ( BitWidth ) && <STR_LIT> ) ; unsigned ShAmt1 = N -> getConstantOperandVal ( <NUM_LIT> ) ; unsigned ShAmt2 = Src . getConstantOperandVal ( <NUM_LIT> ) ; if ( BitWidth < <NUM_LIT> || ShAmt1 != ( BitWidth / <NUM_LIT> ) || ShAmt2 != ( BitWidth - <NUM_LIT> ) ) return SDValue ( ) ; Src = Src . getOperand ( <NUM_LIT> ) ; unsigned CombinedShAmt = ShAmt1 ^ ShAmt2 ; if ( CombinedShAmt == <NUM_LIT> ) return Src ; SDValue Res = DAG . getNode ( <STR_LIT> , DL , VT , Src , DAG . getConstant ( CombinedShAmt , DL , N -> getOperand ( <NUM_LIT> ) . getValueType ( ) ) ) ; if ( ! IsWInstruction ) return Res ; return DAG . getNode ( <STR_LIT> , DL , VT , Res , DAG


<s> assert ( ( VecVT . getVectorNumElements ( ) <= <NUM_LIT> || Subtarget . hasBWI ( ) ) && <STR_LIT> ) ; if ( ! isa < ConstantSDNode > ( Idx ) ) { unsigned NumElts = VecVT . getVectorNumElements ( ) ; MVT ExtEltVT = ( NumElts <= <NUM_LIT> ) ? <STR_LIT> ( <NUM_LIT> / NumElts ) : <STR_LIT> ; MVT ExtVecVT = <STR_LIT> ( ExtEltVT , NumElts ) ; SDValue Ext = DAG . getNode ( <STR_LIT> , dl , ExtVecVT , Vec ) ; SDValue Elt = DAG . getNode ( <STR_LIT> , dl , ExtEltVT , Ext , Idx ) ; return DAG . getNode ( <STR_LIT> , dl , EltVT , Elt ) ; } if ( EltVT != <STR_LIT> ) { SDValue Extract = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Vec , Idx ) ; return DAG . getAnyExtOrTrunc ( Extract , dl , EltVT ) ; } unsigned IdxVal = cast < ConstantSDNode > ( Idx


<s> OptionalArgs . push_back ( emitEHLSDA ( Builder , & F ) ) ; } else if ( Personality == EHPersonality :: MSVC_<ISA_LIT>SEH ) { OptionalArgs . push_back ( SehLongjmpUnwind . getCallee ( ) ) ; OptionalArgs . push_back ( State ) ; if ( UseStackGuard ) OptionalArgs . push_back ( Cookie ) ; } else { llvm_unreachable ( <STR_LIT> ) ; } SmallVector < Value * , <NUM_LIT> > Args ; Args . push_back ( Builder . CreateBitCast ( Call . getArgOperand ( <NUM_LIT> ) , Builder . getInt8PtrTy ( ) ) ) ; Args . push_back ( Builder . getInt32 ( OptionalArgs . size ( ) ) ) ; Args . append ( OptionalArgs . begin ( ) , OptionalArgs . end ( ) ) ; CallBase * NewCall ; if ( auto * CI = dyn_cast < CallInst > ( & Call ) ) { CallInst * NewCI = Builder . CreateCall ( SetJmp3 , Args , OpBundles ) ; NewCI -> setTailCallKind ( CI -> getTailCallKind