<s> void <ISA_LIT>TargetLowering :: validateCCReservedRegs ( const SmallVectorImpl < std :: pair < llvm :: Register , llvm :: SDValue >> & Regs , MachineFunction & MF ) const { const Function & F = MF . getFunction ( ) ; const <ISA_LIT>Subtarget & STI = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( std :: any_of ( std :: begin ( Regs ) , std :: end ( Regs ) , [ & STI ] ( auto Reg ) { return STI . isRegisterReservedByUser ( Reg . first ) ; } ) ) F . getContext ( ) . diagnose ( DiagnosticInfoUnsupported { F , <STR_LIT>


<s> OperandMatchResultTy parseBDXAddr64 ( OperandVector & Operands


<s> assert ( Mask [ i ] >= - <NUM_LIT> && <STR_LIT> ) ; int MaskIdx = Mask [ i ] ; int ExpectedIdx = ExpectedMask [ i ] ; if ( <NUM_LIT> <= MaskIdx && MaskIdx != ExpectedIdx ) { SDValue MaskV = MaskIdx < Size ? V1 : V2 ; SDValue ExpectedV = ExpectedIdx < Size ? V1 : V2 ; MaskIdx = MaskIdx < Size ? MaskIdx : ( MaskIdx -


<s> FunctionPass * llvm :: create<ISA_LIT>ISelDag ( TargetMachine &


<s> <ISA_LIT>MCAsmInfo :: <ISA_LIT>MCAsmInfo ( const Triple & TT ) { IsLittleEndian = false ; UseIntegratedAssembler = true ; CodePointerSize = CalleeSaveStackSlotSize =


<s> unsigned getMaxCallFrameSize ( ) const


<s> bool isDarwinABI ( ) const { return isTargetMachO ( ) || isDarwin (


<s> SmallVector < Value * , <NUM_LIT> > Args ; if ( EscapeCall ) { auto Ops = EscapeCall -> arg_operands ( ) ; Args . append ( Ops . begin ( ) , Ops . end ( ) ) ; } Args . push_back ( RegNode ) ; IRBuilder < > Builder ( & F . getEntryBlock ( ) , EscapeCall ? EscapeCall : F .


<s> if ( DecodeGPR8RegisterClass ( Inst , d , Address , Decoder ) == MCDisassembler :: Fail ) return MCDisassembler :: Fail ; if ( DecodeGPR8RegisterClass ( Inst , d , Address , Decoder )


<s> const <ISA_LIT>TargetLowering * getTLI ( ) const { return TLI


<s> static std :: string getRomdataSectionName ( unsigned num , std :: string prefix = <STR_LIT> ) { std :: ostringstream o


<s> void <ISA_LIT>AsmPrinter :: EmitStartOfAsmFile ( Module & M ) { if ( Subtarget -> isTargetEnvMacho ( ) ) OutStreamer . SwitchSection ( getObjFileLowering ( ) . getTextSection ( ) ) ; if ( Subtarget -> isTargetCOFF ( ) ) { if ( ! Subtarget -> is64Bit


<s> emit_move_insn ( tmpreg , retreg ) ; insn = emit_move_insn ( gen_rtx_MEM ( DImode , plus_constant ( Pmode , stack_pointer_rtx , offset ) ) , tmpreg ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; add_reg_note ( insn , REG_FRAME_RELATED_EXPR , gen_rtx_SET ( gen_rtx_MEM ( DImode , plus_constant ( Pmode , stack_pointer_rtx , offset ) ) , retreg ) ) ; offset -= <NUM_LIT> ; } else if ( MMIX_CFUN_HAS_LANDING_PAD ) offset -= <NUM_LIT> ; if ( MMIX_CFUN_HAS_LANDING_PAD ) { if ( offset < <NUM_LIT> ) { HOST_WIDE_INT stack_chunk = stack_space_to_allocate > ( <NUM_LIT> - <NUM_LIT> - <NUM_LIT> ) ? ( <NUM_LIT> - <NUM_LIT> - <NUM_LIT> ) : stack_space_to_allocate ; mmix_emit_sp_add ( - stack_chunk ) ; total_allocated_stack_space += stack_chunk ; offset += stack_chunk ; stack_space_to_allocate -= stack_chunk ; } emit_move_insn ( gen_rtx_REG ( DImode , <NUM_LIT> ) , gen_rtx_REG ( DImode , MMIX_rO_REGNUM ) ) ; emit_move_insn ( gen_rtx_MEM ( DImode , plus_constant ( Pmode , stack_pointer_rtx , offset ) ) , gen_rtx_REG ( DImode , <NUM_LIT> ) ) ; offset -= <NUM_LIT> ; } offset -= ( locals_size + <NUM_LIT> ) & ~ <NUM_LIT> ; for ( regno = <NUM_LIT> ; regno >= MMIX_FIRST_GLOBAL_REGNUM ; regno -- ) if ( ( ( regno != MMIX_FRAME_POINTER_REGNUM || ! frame_pointer_needed ) && df_regs_ever_live_p ( regno ) && ! call_used_or_fixed_reg_p ( regno ) ) || IS_MMIX_EH_RETURN_DATA_REG ( regno ) ) { rtx insn ; if ( offset < <NUM_LIT> ) { HOST_WIDE_INT stack_chunk = ( stack_space_to_allocate > ( <NUM_LIT> - offset - <NUM_LIT> ) ? ( <NUM_LIT> - offset - <NUM_LIT> ) : stack_space_to_allocate ) ; mmix_emit_sp_add ( - stack_chunk ) ; total_allocated_stack_space += stack_chunk ; offset += stack_chunk ; stack_space_to_allocate -= stack_chunk ; } insn = emit_move_insn ( gen_rtx_MEM ( DImode , plus_constant ( Pmode , stack_pointer_rtx , offset ) ) , gen_rtx_REG


<s> void <ISA_LIT>AsmPrinter :: EmitFunctionBodyStart ( ) { MCInstLowering . Initialize ( Mang , & MF -> getContext (


<s> DecodeStatus S = MCDisassembler :: Success ; Inst . addOperand ( MCOperand :: createImm ( imm8 ) ) ; if ( ! Check ( S , DecodePredicateOperand ( Inst , pred , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( imm8 == <NUM_LIT> && pred != <NUM_LIT> && ( ( FeatureBits [ <STR_LIT> ] )

!= <NUM_LIT> ) ) S = MCDisassembler :: SoftFail ;


<s> void adjustArgFlags ( CallLowering :: ArgInfo & Arg , LLT Ty ) { if ( ! Ty . isPointer ( ) ) return ; auto & Flags = Arg . Flags


<s> AssemblerDialect = AsmWriterFlavor ; TextAlignFillValue = <NUM_LIT> ; if ( ! is64Bit ) Data64bitsDirective = <NUM_LIT> ; CommentString = <STR_LIT> ; SupportsDebugInformation =


<s> DEBUG ( dbgs ( ) << <STR_LIT> ) ; Changed = false ; for ( auto & MBB : MF ) processMachineBasicBlock ( MBB ) ; return Changed


<s> MDT = getAnalysisIfAvailable < MachineDominatorTree > ( ) ; MRI = & MF . getRegInfo ( ) ; BoolRC = TRI -> getBoolRC ( ) ; if ( ST . isWave32 ( ) ) { AndOpc = <STR_LIT> ; OrOpc = <STR_LIT> ; XorOpc = <STR_LIT> ; MovTermOpc = <STR_LIT> ; Andn2TermOpc = <STR_LIT> ; XorTermrOpc = <STR_LIT> ; OrTermrOpc = <STR_LIT> ; OrSaveExecOpc = <STR_LIT> ; Exec = <STR_LIT> ; } else { AndOpc = <STR_LIT> ; OrOpc = <STR_LIT> ; XorOpc = <STR_LIT> ; MovTermOpc = <STR_LIT> ; Andn2TermOpc = <STR_LIT> ; XorTermrOpc = <STR_LIT> ; OrTermrOpc = <STR_LIT> ; OrSaveExecOpc = <STR_LIT> ; Exec = <STR_LIT> ; } const bool CanDemote = MF . getFunction ( ) . getCallingConv ( ) == CallingConv :: <ISA_LIT>_PS ; for ( auto & MBB : MF ) { bool IsKillBlock = false ; for ( auto & Term : MBB . terminators ( ) ) { if ( TII -> isKillTerminator ( Term . getOpcode ( ) ) ) { KillBlocks . insert ( & MBB ) ; IsKillBlock = true ; break ; } } if ( CanDemote && ! IsKillBlock ) { for ( auto & MI : MBB ) { if ( MI . getOpcode ( ) == <STR_LIT> ) { KillBlocks . insert ( & MBB ) ; break ; } } } } MachineFunction :: iterator NextBB ; for ( MachineFunction :: iterator BI = MF . begin ( ) ; BI != MF . end ( ) ; BI = NextBB ) { NextBB = std :: next ( BI ) ; MachineBasicBlock * MBB = & * BI ; MachineBasicBlock :: iterator I , E , Next ; E = MBB -> end ( ) ; for ( I = MBB -> begin ( ) ; I != E ; I = Next ) { Next = std :: next ( I ) ; MachineInstr & MI = * I ; MachineBasicBlock * SplitMBB = MBB ; switch ( MI . getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : SplitMBB = process ( MI ) ; break ; case <STR_LIT> : case <STR_LIT>


<s> const MachineOperand & MO = MI . getOperand ( i ) ; if ( ( MO . isReg ( ) && MO . isImplicit ( ) )

|| MO . isRegMask ( ) ) NewMI . addOperand ( MF , MO ) ;


<s> if ( ID == & TargetTransformInfo :: ID

) return ( TargetTransformInfo * ) this ;


<s> MI . addOperand ( MCOperand :: CreateImm ( <STR_LIT> ( SubMode ) ) ) ; int64_t CondVal = insn >> <STR_LIT> ; MI . addOperand ( MCOperand :: CreateImm ( CondVal == <NUM_LIT> ? <NUM_LIT> : CondVal ) ) ; MI . addOperand ( MCOperand :: CreateReg ( <STR_LIT> ) ) ; OpIdx += <NUM_LIT> ; bool isSPVFP = ( Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ) ; unsigned RegClassID = isSPVFP ? <STR_LIT> : <STR_LIT> ; unsigned RegD = decodeVFPRd ( insn , isSPVFP ) ; unsigned char Imm8 = insn & <NUM_LIT> ; unsigned Regs = isSPVFP ? Imm8 :


<s> break ; } case <STR_LIT> : { auto ConditionCode = <STR_LIT> ( MI . getOperand ( <NUM_LIT> ) . getImm ( ) ) ; resolveComparison ( MBB , MI , DL , ConditionCode , MI . getOperand ( <NUM_LIT> ) , MI . getOperand ( <NUM_LIT> ) ) ; BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) ) . add ( MI . getOperand ( <NUM_LIT> ) ) ; break ; } case <STR_LIT> : { auto Dst = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; auto TrueValue = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; auto FalseValue = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) ) . addImm ( <NUM_LIT> ) ; BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) ) . addReg ( Dst ) . addReg ( <STR_LIT> ) . addReg ( FalseValue ) ; BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) ) . addImm ( <NUM_LIT> ) ; BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) ) . addReg ( Dst ) . addReg ( <STR_LIT> ) . addReg ( TrueValue ) ; break ; } case <STR_LIT> : { auto Dst = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; auto ConditionCode = <STR_LIT> ( MI . getOperand ( <NUM_LIT> ) . getImm ( ) ) ; auto TrueValue = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; auto FalseValue = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; resolveComparison ( MBB , MI , DL , ConditionCode , MI . getOperand ( <NUM_LIT> ) , MI . getOperand ( <NUM_LIT> ) ) ; BuildMI ( MBB , MI , DL , get ( <STR_LIT> )


<s> return ( TlsFree ( key ) != <NUM_LIT> ) ? <NUM_LIT>


<s> static DecodeStatus DecodeMem ( MCInst & MI , uint64_t insn , uint64_t Address , const MCDisassembler * Decoder , bool isLoad , DecodeFunc DecodeSX ) { unsigned sx = fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) ; DecodeStatus status ; if ( isLoad ) { status = DecodeSX ( MI , sx , Address , Decoder ) ; if ( status != MCDisassembler :: Success ) return status ; } status = DecodeASX ( MI , insn , Address , Decoder ) ; if ( status != MCDisassembler :: Success ) return status ; if ( ! isLoad ) { status = DecodeSX ( MI , sx , Address , Decoder ) ; if ( status != MCDisassembler :: Success )


<s> else WideRes = getSETCCInGPR ( N -> getOperand ( <NUM_LIT> ) , N -> getOpcode ( ) == <STR_LIT> ? SetccInGPROpts :: SExtOrig : SetccInGPROpts :: ZExtOrig ) ; if ( ! WideRes ) return false ; SDLoc dl ( N ) ; bool Inputs32Bit = N -> getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) . getValueType ( ) == <STR_LIT> ; bool Output32Bit = N -> getValueType ( <NUM_LIT> ) == <STR_LIT> ; NumSextSetcc += N -> getOpcode ( ) == <STR_LIT> ?


<s> int IRFLengthStore = findIRF ( IRFStore , StoreIRF ) ; if ( IRFLengthLoad == IRFLengthStore ) { for ( int i = <NUM_LIT> ; i < IRFLengthStore ; i ++ ) { SCEVParser scevRunerLoad ( SE -> getSCEV ( LoadIRF [ i ] ) , SE , F . getParent (


<s> } } MachineInstr * And = nullptr , * Or = nullptr ; if ( ! SkipAnding ) { Register AndReg = MRI -> createVirtualRegister ( BoolRC ) ; And = BuildMI ( MBB , & MI , DL , TII -> get ( AndOpc ) , AndReg ) . addReg ( Exec ) . add ( MI . getOperand ( <NUM_LIT> ) ) ; Or = BuildMI ( MBB , & MI , DL , TII -> get ( OrOpc ) , Dst ) .

addReg ( AndReg ) . add ( MI . getOperand ( <NUM_LIT> ) ) ;


<s> MVT InVT = In . getValueType ( ) . getSimpleVT ( ) ; MVT InSVT = InVT . getScalarType ( ) ; if ( ! isPowerOf2_32 ( VT . getVectorNumElements ( ) ) ) return SDValue ( ) ; if ( SVT != <STR_LIT> && SVT != <STR_LIT> && SVT != <STR_LIT> ) return SDValue ( ) ; if ( InSVT != <STR_LIT> && InSVT != <STR_LIT> && InSVT != <STR_LIT> ) return SDValue ( ) ; if ( SVT == <STR_LIT> && VT . getSizeInBits ( ) < <NUM_LIT> ) return SDValue ( ) ; if ( Subtarget . hasAVX512 ( ) && ! ( ! Subtarget . useAVX512Regs ( ) && VT . is256BitVector ( ) && InVT . is512BitVector ( ) ) ) return SDValue ( ) ; unsigned NumPackedSignBits = std :: min < unsigned > ( SVT . getSizeInBits ( ) , <NUM_LIT> ) ; unsigned NumPackedZeroBits = Subtarget . hasSSE41 ( ) ? NumPackedSignBits : <NUM_LIT> ; KnownBits Known = DAG . computeKnownBits ( In ) ; unsigned NumLeadingZeroBits = Known . countMinLeadingZeros ( ) ; if ( NumLeadingZeroBits >= ( InSVT . getSizeInBits ( ) - NumPackedZeroBits ) ) return truncateVectorWithPACK ( <STR_LIT> , VT , In , DL , DAG , Subtarget ) ; unsigned NumSignBits = DAG . ComputeNumSignBits ( In ) ; if ( NumSignBits > ( InSVT . getSizeInBits ( ) - NumPackedSignBits ) ) return truncateVectorWithPACK ( <STR_LIT> , VT , In , DL ,


<s> unsigned ikind = <ISA_LIT>MCInstrInfo :: getType ( MCII


<s> std :: vector < std :: vector < std :: pair < int , unsigned > > > IGSrcs ; ValidSwizzle . clear ( ) ; for ( unsigned i = <NUM_LIT> , e = IG . size ( ) ; i < e ; ++ i ) { IGSrcs . push_back ( ExtractSrcs ( IG [ i ] , PV ) ) ; unsigned Op = getOperandIdx ( IG [ i ] -> getOpcode ( ) , AMDGPU :: OpName :: bank_swizzle ) ; ValidSwizzle . push_back ( ( R600InstrInfo :: BankSwizzle ) IG [ i ] -> getOperand (


<s> unsigned FixedNum = <NUM_LIT> , SplitNum = <NUM_LIT> , LoopPhiNum = <NUM_LIT> ; int32_t TotalP = <NUM_LIT> ; for ( unsigned DR : Part ) { MachineInstr * DefI = MRI -> getVRegDef ( DR ) ; int32_t P = profit ( DefI ) ; if ( P == std :: numeric_limits < int > :: min ( ) ) return false ; TotalP += P ; if ( isInduction ( DR , IRM ) ) TotalP -= <NUM_LIT> ; for ( auto U = MRI -> use_nodbg_begin ( DR ) , W = MRI -> use_nodbg_end ( ) ; U != W ; ++


<s> void <ISA_LIT>AsmPrinter :: EmitBasicBlockStart ( const MachineBasicBlock &


<s> SDValue N1 = N -> getOperand ( <NUM_LIT> ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( ! ( ( VT == <STR_LIT> ) || ( VT == <STR_LIT> && Subtarget . hasInt256 ( ) ) ) ) return SDValue ( ) ; assert ( Subtarget . hasSSE2 ( ) && <STR_LIT> ) ; if ( N0 . getOpcode ( ) == <STR_LIT> ) std :: swap ( N0 , N1 ) ; if ( N0 . getOpcode ( ) != <STR_LIT> || N1 . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; SDValue Mask = N1 . getOperand ( <NUM_LIT> ) ; SDValue X = N1 . getOperand ( <NUM_LIT> ) ; SDValue Y ; if ( N0 . getOperand ( <NUM_LIT> ) == Mask ) Y = N0 . getOperand ( <NUM_LIT> ) ; if ( N0 . getOperand ( <NUM_LIT> ) == Mask ) Y = N0 . getOperand ( <NUM_LIT> ) ; if ( ! Y . getNode ( ) ) return SDValue ( ) ; if ( Mask . getOpcode ( ) == <STR_LIT> ) Mask = Mask . getOperand ( <NUM_LIT> ) ; if ( X . getOpcode ( ) == <STR_LIT> ) X = X . getOperand ( <NUM_LIT> ) ; if ( Y . getOpcode ( ) == <STR_LIT> ) Y = Y . getOperand ( <NUM_LIT> ) ; EVT MaskVT = Mask . getValueType


<s> return <ISA_LIT>II :: getImmEnd ( getDesc (


<s> <STR_LIT> SetCCOpcode = cast < CondCodeSDNode > ( CC ) -> get ( ) ; SDValue NotOp0 = DAG . getNode ( <STR_LIT> , dl , VT , Op0 , DAG . getConstant ( - <NUM_LIT> , dl , VT ) ) ; SDValue NotOp1 = DAG . getNode ( <STR_LIT> , dl , VT , Op1 , DAG . getConstant ( - <NUM_LIT> , dl , VT ) ) ; switch ( SetCCOpcode ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , dl , VT , DAG . getNode ( <STR_LIT> , dl , VT , Op0 , Op1 ) , DAG . getConstant ( - <NUM_LIT> , dl , VT ) ) ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , dl , VT , Op0 , Op1 ) ; case <STR_LIT> : case <STR_LIT> : return DAG . getNode ( <STR_LIT> , dl , VT , Op0 , NotOp1 ) ; case <STR_LIT> : case <STR_LIT> : return DAG . getNode ( <STR_LIT> , dl , VT , NotOp0 , Op1 ) ; case <STR_LIT> : case <STR_LIT>


<s> CCState CCInfo ( CallConv , isVarArg , getTargetMachine ( ) , RVLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeCallResult ( Ins , RetCC_<ISA_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i ) { Chain = DAG . getCopyFromReg ( Chain , dl , RVLocs [ i ] . getLocReg ( ) , RVLocs [ i ] . getValVT ( ) , InFlag ) . getValue ( <NUM_LIT> ) ; InFlag = Chain . getValue ( <NUM_LIT>


<s> if ( Adjust % ElemSize == <NUM_LIT> ) { Value * Tmp0 = Builder . CreateGEP ( Ptr , HVC . getConstInt ( Adjust / ElemSize ) ) ; return Builder . CreatePointerCast ( Tmp0 , ValTy -> getPointerTo ( ) ) ; } PointerType * CharPtrTy = Type :: getInt8PtrTy ( HVC .


<s> if ( TT . isOSDarwin ( ) ) return new Darwin<ISA_LIT>AsmBackend ( T , STI . getCPU ( ) ) ; uint8_t OSABI = MCELFObjectTargetWriter :: getOSABI ( TT . getOS ( ) ) ; bool IsLittleEndian = TT . getArch ( ) == Triple ::


<s> if ( GV . getType ( ) -> getAddressSpace ( ) == llvm :: ADDRESS_SPACE_GENERIC && ! llvm :: isTexture ( GV ) && ! llvm :: isSurface ( GV ) && ! llvm :: isSampler ( GV ) && ! GV . getName ( ) . startswith ( <STR_LIT> ) ) { GlobalVariable * NewGV = new GlobalVariable ( M , GV . getValueType ( ) , GV . isConstant ( ) , GV . getLinkage ( ) , GV . hasInitializer ( ) ? GV . getInitializer ( ) : nullptr , <STR_LIT> , & GV , GV . getThreadLocalMode ( ) , llvm :: ADDRESS_SPACE_GLOBAL ) ; NewGV -> copyAttributesFrom ( & GV ) ; GVMap [ & GV ] = NewGV ; } } if ( GVMap . empty ( ) ) { return false ; } for ( Module :: iterator I = M . begin ( ) , E = M . end ( ) ; I != E ; ++ I ) { if ( I -> isDeclaration ( ) ) { continue ; } IRBuilder < > Builder ( I -> getEntryBlock ( ) . getFirstNonPHIOrDbg ( ) ) ; for ( Function :: iterator BBI = I -> begin ( ) , BBE = I -> end ( ) ; BBI != BBE ; ++ BBI ) { for ( BasicBlock :: iterator II = BBI -> begin ( ) , IE = BBI -> end ( ) ; II != IE ; ++ II ) { for ( unsigned i = <NUM_LIT> , e = II -> getNumOperands ( ) ; i < e ; ++ i ) { Value * Operand = II -> getOperand ( i ) ; if ( isa < Constant > ( Operand ) ) { II -> setOperand ( i , remapConstant ( & M , & * I , cast < Constant > ( Operand ) , Builder ) ) ; } } } } ConstantToValueMap . clear ( ) ; } ValueToValueMapTy VM ; for ( auto I = GVMap . begin ( ) , E = GVMap . end ( ) ; I != E ; ++ I ) VM [ I -> first ] = I -> second ; for ( GVMapTy :: iterator I = GVMap . begin ( ) , E = GVMap . end ( ) ; I != E ; ) { GlobalVariable * GV = I -> first ; GlobalVariable * NewGV = I -> second ; auto Next = std :: next ( I ) ; GVMap . erase ( I ) ; I = Next ; Constant * BitCastNewGV = ConstantExpr :: getPointerCast ( NewGV , GV -> getType ( ) ) ; GV -> replaceAllUsesWith ( BitCastNewGV ) ; std :: string Name = std :: string ( GV -> getName ( ) ) ; GV -> eraseFromParent (


<s> if ( <ISA_LIT>SubTarget . isSVR4ABI ( ) && <ISA_LIT>SubTarget . is<ISA_LIT>64 ( ) ) { SDValue GA = DAG . getTargetJumpTable ( JT -> getIndex ( ) , PtrVT ) ; return DAG . getNode ( <STR_LIT> , SDLoc ( JT ) , <STR_LIT> , GA , DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ) ; } unsigned MOHiFlag , MOLoFlag ; bool isPIC = GetLabelAccessInfo ( DAG . getTarget ( ) , MOHiFlag , MOLoFlag ) ; SDValue JTIHi = DAG . getTargetJumpTable ( JT -> getIndex ( ) , PtrVT , MOHiFlag ) ; SDValue JTILo = DAG . getTargetJumpTable ( JT -> getIndex ( ) , PtrVT ,


<s> DEBUG ( errs ( ) << <STR_LIT> << MF . getFunction ( ) -> getName ( ) << <STR_LIT> ; errs ( ) << <STR_LIT> << MI ) ; int FrameIndex = MI . getOperand ( i ) . getIndex ( ) ; int stackSize = MF . getFrameInfo ( ) -> getStackSize ( ) ; int spOffset = MF . getFrameInfo ( ) -> getObjectOffset ( FrameIndex ) ; DEBUG ( errs ( ) << <STR_LIT> << FrameIndex << <STR_LIT> << <STR_LIT> << spOffset << <STR_LIT> << <STR_LIT> << stackSize << <STR_LIT> ) ; int Offset = ( ( spOffset < <NUM_LIT> ) ? ( stackSize + ( - ( spOffset + <NUM_LIT> ) ) ) : ( spOffset ) ) ; Offset += MI . getOperand ( i - <NUM_LIT> ) .


<s> bool <ISA_LIT>InstrInfo :: isSALUInstr ( const MachineInstr & MI


<s> void setGlobalRetAddr ( unsigned Reg ) { GlobalRetAddr =


<s> void \ const_section ( ) \ { \ text_section ( )


<s> TRI = static_cast < const <ISA_LIT>RegisterInfo * > ( MF -> getTarget ( ) . getSubtargetImpl ( ) -> getRegisterInfo ( ) ) ; LIs = LI ; DEBUG ( MF -> dump ( ) ; ) ; for ( MachineFunction :: const_iterator mbbItr = MF -> begin ( ) , mbbEnd = MF -> end ( ) ; mbbItr != mbbEnd ; ++ mbbItr ) { const MachineBasicBlock * MBB = & * mbbItr ; Chains . clear ( ) ; for ( MachineBasicBlock :: const_iterator miItr = MBB -> begin ( ) , miEnd = MBB -> end ( ) ; miItr != miEnd ; ++ miItr ) { const MachineInstr * MI = & * miItr ; switch ( MI -> getOpcode ( ) ) { case <STR_LIT> : case


<s> if ( TM -> getTargetTriple ( ) . getArch ( ) == Triple :: amdgcn && EnableLowerKernelArguments ) addPass ( create<ISA_LIT>LowerKernelArgumentsPass ( ) ) ; TargetPassConfig :: addCodeGenPrepare (


<s> O << '#' << formatImm ( Scale * MI -> getOperand ( OpNum ) . getImm (


<s> static unsigned HOST_WIDE_INT sparc_asan_shadow_offset ( void


<s> Op -> Mem . Base = Base ; Op -> Mem . IndexReg = <NUM_LIT> ; Op -> Mem .


<s> BO . push_back ( & Fn -> front ( ) ) ; for ( unsigned i = <NUM_LIT> ; i < BO . size ( ) ; ++ i ) { BasicBlock * B = cast < BasicBlock > ( BO [ i ] ) ; for ( auto DTN : children < DomTreeNode * > ( DT -> getNode ( B ) ) ) BO . push_back ( DTN -> getBlock ( ) ) ; } for ( unsigned i = BO . size ( ) ; i > <NUM_LIT> ; -- i ) { BasicBlock * B = cast < BasicBlock > ( BO [ i - <NUM_LIT> ] ) ; BasicBlock :: InstListType & IL = B -> getInstList ( ) ; typedef BasicBlock :: InstListType :: reverse_iterator reverse_iterator ; ValueVect Ins ; for ( reverse_iterator I = IL . rbegin ( ) , E = IL . rend ( ) ; I != E ; ++ I ) Ins . push_back ( & * I ) ; for ( ValueVect :: iterator I = Ins . begin ( ) , E = Ins .


<s> return false ; } unsigned PtrSize = ValTy . getElementType ( ) . getSizeInBits ( ) ; const LLT NewTy = LLT :: vector ( ValTy . getElementCount ( ) , PtrSize ) ; auto & MMO = * * MI . memoperands_begin ( ) ; MMO . setType ( NewTy ) ; if ( MI . getOpcode ( ) == TargetOpcode :: G_STORE ) { auto Bitcast = MIRBuilder . buildBitcast ( NewTy , ValReg ) ; MIRBuilder . buildStore ( Bitcast . getReg ( <NUM_LIT> ) , MI . getOperand ( <NUM_LIT> ) , MMO ) ; }


<s> EVT VT = Op . getValueType ( ) ; ShuffleVectorSDNode * SVN = cast < ShuffleVectorSDNode > ( Op . getNode ( ) ) ; if ( useSVEForFixedLengthVectorVT ( VT ) ) return LowerFixedLengthVECTOR_SHUFFLEToSVE ( Op , DAG ) ; ArrayRef < int > ShuffleMask = SVN -> getMask ( ) ; SDValue V1 = Op . getOperand ( <NUM_LIT> ) ; SDValue V2 = Op . getOperand ( <NUM_LIT> ) ; assert ( V1 . getValueType ( ) == VT && <STR_LIT> ) ; assert ( ShuffleMask . size ( ) == VT . getVectorNumElements ( ) && <STR_LIT> ) ; if ( SVN -> isSplat ( ) ) { int Lane = SVN -> getSplatIndex ( ) ; if ( Lane == - <NUM_LIT> ) Lane = <NUM_LIT> ; if ( Lane == <NUM_LIT> && V1 . getOpcode ( ) == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , dl , V1 . getValueType ( ) , V1 . getOperand ( <NUM_LIT> ) ) ; if ( V1 . getOpcode ( ) == <STR_LIT> && ! isa < ConstantSDNode > ( V1 . getOperand ( Lane ) ) ) return DAG . getNode ( <STR_LIT> , dl , VT , V1 . getOperand ( Lane ) ) ; unsigned Opcode = getDUPLANEOp ( V1 . getValueType ( ) . getVectorElementType ( ) ) ; return constructDup ( V1 , Lane , dl , VT , Opcode , DAG ) ; } for ( unsigned LaneSize : { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) { unsigned Lane = <NUM_LIT> ; if ( isWideDUPMask ( ShuffleMask , VT , LaneSize , Lane ) ) { unsigned Opcode = LaneSize == <NUM_LIT> ? <STR_LIT> : LaneSize == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; MVT NewEltTy = <STR_LIT> ( LaneSize ) ; unsigned NewEltCount = VT . getSizeInBits ( ) / LaneSize ; MVT NewVecTy = <STR_LIT> ( NewEltTy , NewEltCount ) ; V1 = DAG . getBitcast ( NewVecTy , V1 ) ; V1 = constructDup ( V1 , Lane , dl , NewVecTy , Opcode , DAG ) ; return DAG . getBitcast ( VT , V1 ) ; } } if ( isREVMask ( ShuffleMask , VT , <NUM_LIT> ) ) return DAG . getNode ( <STR_LIT> , dl , V1 . getValueType ( ) , V1 , V2 ) ; if ( isREVMask ( ShuffleMask , VT , <NUM_LIT> ) ) return DAG . getNode ( <STR_LIT> , dl , V1 . getValueType ( ) , V1 , V2 ) ; if ( isREVMask ( ShuffleMask , VT , <NUM_LIT> ) ) return DAG . getNode ( <STR_LIT> , dl , V1 . getValueType ( ) , V1 , V2 ) ; if ( ( ( VT . getVectorNumElements ( ) == <NUM_LIT> && VT . getScalarSizeInBits ( ) == <NUM_LIT> ) || ( VT . getVectorNumElements ( ) == <NUM_LIT> && VT . getScalarSizeInBits ( ) == <NUM_LIT>

) ) && ShuffleVectorInst :: isReverseMask ( ShuffleMask ) ) {


<s> MachineBasicBlock :: const_instr_iterator E = MI -> getParent ( ) -> instr_end ( ) ; do { customEmitInstruction ( I ++ ) ; } while ( ( I != E ) && I ->


<s> setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; if ( HWMultMode == HWMultIntr ) { setLibcallName ( RTLIB :: MUL_I8


<s> bool <ISA_LIT>InstrInfo :: invertAndChangeJumpTarget ( MachineInstr & MI , MachineBasicBlock * NewTarget ) const { DEBUG ( dbgs ( ) << <STR_LIT> << printMBBReference ( * NewTarget ) ; MI . dump ( ) ; ) ; assert ( MI . isBranch ( ) ) ; unsigned NewOpcode = getInvertedPredicatedOpcode ( MI . getOpcode ( ) ) ; int TargetPos = MI . getNumOperands ( )


<s> BasicBlock * Entry = PrevNode -> getEntry ( ) ; if ( ! PrevNode -> isSubRegion ( ) ) { killTerminator ( Entry ) ; if ( ! NeedEmpty || Entry -> getFirstInsertionPt ( ) == Entry -> end ( ) ) return Entry ; } BasicBlock * Flow = getNextFlow ( Entry ) ; changeExit ( PrevNode ,


<s> MachineFunction * MF = MBB . getParent ( ) ; const MachineFrameInfo & MFI = * MF -> getFrameInfo ( ) ; MachineMemOperand * MMO = MF -> getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( * MF , FI ) , MachineMemOperand :: MOStore , MFI . getObjectSize ( FI ) , MFI . getObjectAlignment ( FI ) ) ; if ( RC == & <STR_LIT> ) BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addMemOperand ( MMO ) ; else if ( RC == & <STR_LIT> ) BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addMemOperand ( MMO ) ; else if ( RC == & <STR_LIT> ) BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addMemOperand ( MMO ) ; else if ( RC == & <STR_LIT> ) BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) .


<s> if ( TII -> isSGPRSpill ( MI ) ) { int FI = TII -> getNamedOperand ( MI , <STR_LIT> :: addr ) -> getIndex ( ) ; assert ( MFI . getStackID ( FI ) == TargetStackID :: SGPRSpill ) ; if ( FuncInfo -> allocateSGPRSpillToVGPR ( MF , FI ) ) { bool Spilled = TRI . eliminateSGPRToVGPRSpillFrameIndex ( MI , FI , RS ) ; ( void ) Spilled ; assert ( Spilled && <STR_LIT> ) ; } else AllSGPRSpilledToVGPRs = false ; } } } } FuncInfo -> removeSGPRToVGPRFrameIndices ( MFI ) ; if ( FuncInfo -> hasNonSpillStackObjects ( ) || FuncInfo -> hasSpilledVGPRs ( ) || ! AllSGPRSpilledToVGPRs || ! allStackObjectsAreDead ( MFI ) ) { assert ( RS && <STR_LIT> ) ; if ( FuncInfo -> isEntryFunction ( ) ) { int ScavengeFI = MFI . CreateFixedObject ( TRI . getSpillSize ( <STR_LIT> ) , <NUM_LIT> , false ) ; RS -> addScavengingFrameIndex ( ScavengeFI


<s> static LoadInst * CreateLoadIns ( IRBuilder < NoFolder > & IRB , LoadInst & BaseLoad , Type * LoadTy ) { const unsigned AddrSpace = BaseLoad .


<s> MachineInstr & MI = * II ; MachineBasicBlock & MBB = * MI . getParent ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; DebugLoc dl = MI . getDebugLoc ( ) ; bool FP = hasFP ( MF ) ; while ( ! MI . getOperand ( i ) . isFI ( ) ) { ++ i ; assert ( i < MI . getNumOperands ( ) && <STR_LIT> ) ; } int FrameIndex = MI . getOperand ( i ) . getIndex ( ) ; unsigned BaseRegister = FP ? <STR_LIT> : <STR_LIT> ; MI . getOperand ( i ) . ChangeToRegister ( BaseRegister , false ) ; int Offset = MF . getFrameInfo ( ) -> getObjectOffset ( FrameIndex ) ; Offset += MF . getFrameInfo (


<s> VT = LD -> getMemoryVT ( ) ; isSEXTLoad = LD -> getExtensionType ( ) == <STR_LIT> ; } else if ( StoreSDNode * ST = dyn_cast < StoreSDNode > ( N ) ) { Ptr = ST -> getBasePtr ( ) ; VT = ST -> getMemoryVT ( ) ; } else return false ; bool isInc ; bool isLegal = getIndexedAddressParts ( Ptr . getNode ( ) , VT , isSEXTLoad , Base , Offset , isInc , DAG ) ; if ( isLegal ) { AM = isInc ? <STR_LIT> : <STR_LIT> ; return true ; } return


<s> if ( NumRegs <= <NUM_LIT> ) return false ; unsigned NewBase ; if ( isi32Load ( Opcode ) ) NewBase = Regs [ NumRegs - <NUM_LIT> ] . first ; else { NewBase = Scratch ; if ( NewBase == <NUM_LIT> ) return false ; } int BaseOpc = ! isThumb2 ? <STR_LIT> : ( ( Base == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ) ; if ( Offset < <NUM_LIT> ) { BaseOpc = ! isThumb2 ? <STR_LIT> : ( ( Base == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ) ; Offset = - Offset ; } int ImmedOffset = isThumb2 ? <STR_LIT> ( Offset ) : <STR_LIT> ( Offset ) ; if ( ImmedOffset == - <NUM_LIT> ) return false ; BuildMI ( MBB , MBBI , dl , TII -> get ( BaseOpc ) , NewBase ) . addReg ( Base , getKillRegState ( BaseKill ) ) . addImm ( Offset ) . addImm ( Pred ) . addReg ( PredReg ) . addReg ( <NUM_LIT> ) ; Base = NewBase


<s> virtual BlackfinTargetLowering * getTargetLowering ( ) const { return const_cast < BlackfinTargetLowering * > ( & TLInfo


<s> static inline bool mode_supports_pre_incdec_p ( machine_mode mode ) { return ( ( reg_addr [ mode ] . addr_mask [ RELOAD_REG_ANY ] & RELOAD_REG_PRE_INCDEC )


<s> PM . add ( create<ISA_LIT>ISelDag ( * this ) ) ; return false


<s> SDValue <ISA_LIT>TargetLowering :: addTokenForArgument ( SDValue Chain , SelectionDAG & DAG , MachineFrameInfo & MFI , int ClobberedFI ) const { SmallVector < SDValue , <NUM_LIT> > ArgChains ; int64_t FirstByte = MFI . getObjectOffset ( ClobberedFI ) ; int64_t LastByte = FirstByte + MFI . getObjectSize ( ClobberedFI ) - <NUM_LIT> ; ArgChains . push_back ( Chain ) ; for ( SDNode :: use_iterator U = DAG . getEntryNode ( ) . getNode ( ) -> use_begin ( ) , UE = DAG . getEntryNode ( ) . getNode ( ) -> use_end ( ) ; U != UE ; ++ U ) if ( LoadSDNode * L = dyn_cast < LoadSDNode > ( * U ) ) if ( FrameIndexSDNode * FI = dyn_cast < FrameIndexSDNode > ( L -> getBasePtr ( ) ) ) if ( FI -> getIndex ( ) < <NUM_LIT> ) { int64_t InFirstByte = MFI . getObjectOffset ( FI -> getIndex ( ) ) ; int64_t InLastByte = InFirstByte ; InLastByte += MFI . getObjectSize ( FI -> getIndex ( ) ) - <NUM_LIT> ; if ( ( InFirstByte <= FirstByte && FirstByte <= InLastByte ) || ( FirstByte <= InFirstByte && InFirstByte <= LastByte ) ) ArgChains . push_back ( SDValue ( L , <NUM_LIT> ) ) ; } return DAG . getNode ( <STR_LIT> , SDLoc ( Chain


<s> FunctionPass * llvm :: create<ISA_LIT>ISelDag ( <ISA_LIT>TargetMachine & TM ) { return new <ISA_LIT>DAGToDAGISel ( TM


<s> break ; case G_SELECT : { LLT Ty2 = MRI . getType ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; ( void ) Ty2 ; assert ( Ty . getSizeInBits ( ) == <NUM_LIT> && <STR_LIT> ) ; assert ( Ty2 . getSizeInBits ( ) == <NUM_LIT> && <STR_LIT> ) ; OperandsMapping = getOperandsMapping ( { & <STR_LIT> [ <STR_LIT> ] , & <STR_LIT> [ <STR_LIT> ] , & <STR_LIT> [ <STR_LIT> ] , & <STR_LIT> [ <STR_LIT> ] } ) ; break ; } case G_ICMP : { LLT Ty2 = MRI . getType ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; ( void ) Ty2 ; assert ( Ty2 . getSizeInBits ( ) == <NUM_LIT> && <STR_LIT> ) ; OperandsMapping = getOperandsMapping ( { & <STR_LIT> [ <STR_LIT> ] , nullptr , & <STR_LIT> [ <STR_LIT> ] , & <STR_LIT> [ <STR_LIT> ] } ) ; break ; } case G_FCMP : { LLT Ty1 = MRI . getType ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; ( void ) Ty1 ; LLT Ty2 = MRI . getType ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; ( void ) Ty2 ; assert ( Ty . getSizeInBits ( ) == <NUM_LIT> && <STR_LIT> ) ; assert ( Ty1 . getSizeInBits ( ) == <NUM_LIT> && <STR_LIT> ) ; assert ( Ty2 . getSizeInBits ( ) == <NUM_LIT> && <STR_LIT> ) ; OperandsMapping = getOperandsMapping ( { & <STR_LIT> [ <STR_LIT> ] , nullptr , & <STR_LIT> [ <STR_LIT> ] , & <STR_LIT> [ <STR_LIT> ] } ) ; break ; } case G_MERGE_VALUES : { LLT Ty1 = MRI . getType ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; LLT Ty2 = MRI . getType ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; if ( Ty . getSizeInBits ( ) != <NUM_LIT> || Ty1 . getSizeInBits ( ) != <NUM_LIT> || Ty2 . getSizeInBits ( ) != <NUM_LIT> ) return getInvalidInstructionMapping ( ) ; OperandsMapping = getOperandsMapping ( { & <STR_LIT> [ <STR_LIT> ] , & <STR_LIT> [ <STR_LIT> ] , & <STR_LIT> [ <STR_LIT> ] } ) ; break ; } case G_UNMERGE_VALUES : { LLT Ty1 = MRI . getType ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; LLT Ty2 = MRI . getType ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; if ( Ty . getSizeInBits ( ) != <NUM_LIT> || Ty1 . getSizeInBits ( ) != <NUM_LIT> || Ty2 . getSizeInBits ( ) != <NUM_LIT>


<s> Offset = MF . getSubtarget ( ) . getFrameLowering ( ) -> getFrameIndexOffset ( MF , - <NUM_LIT> ) ; return getIndirectIndexBegin ( MF ) +


<s> void BT :: run ( ) { reset ( ) ; assert ( FlowQ . empty ( ) ) ; using MachineFlowGraphTraits = GraphTraits < const MachineFunction * > ; const MachineBasicBlock * Entry = MachineFlowGraphTraits :: getEntryNode ( & MF ) ; unsigned MaxBN = <NUM_LIT> ; for ( const MachineBasicBlock &


<s> default : llvm_unreachable ( <STR_LIT> ) ; case InlineAsm :: Constraint_m : case InlineAsm :: Constraint_o : case InlineAsm :: Constraint_Q : case InlineAsm :: Constraint_Um : case InlineAsm :: Constraint_Un : case InlineAsm :: Constraint_Uq : case InlineAsm :: Constraint_Us : case InlineAsm :: Constraint_Ut : case InlineAsm :: Constraint_Uv


<s> void setGlobalValue ( const GlobalValue


<s> unsigned Opc ; if ( Ty == LLT :: scalar ( <NUM_LIT> ) ) Opc = <STR_LIT> ; else if ( Ty == LLT :: scalar ( <NUM_LIT> ) ) Opc = <STR_LIT> ; else return false ; const DebugLoc & DL = MI . getDebugLoc ( ) ; MachineBasicBlock * MBB = MI . getParent ( ) ; Register Numer = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register Denom = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned ChooseDenom = MI . getOperand ( <NUM_LIT> ) . getImm


<s> bool needsRelocateWithSymbol ( const MCSymbol & Sym , unsigned


<s> const EDInstInfo * <ISA_LIT>Disassembler :: getEDInfo ( ) const { return


<s> int ret = <NUM_LIT> ; switch ( DEFAULT_ABI ) { default : abort ( ) ; case ABI_AIX : ret = ( TARGET_32BIT ) ? <NUM_LIT> : <NUM_LIT> ; break ; case


<s> static MCDisassembler * create<ISA_LIT>Disassembler ( const Target & T , const MCSubtargetInfo &


<s> IsGlobalInSmallSection ( const GlobalObject * GO , const TargetMachine & TM , SectionKind Kind ) const { return IsGlobalInSmallSectionImpl ( GO , TM ) && ( Kind . isData ( ) || Kind . isBSS ( ) || Kind . isCommon ( )


<s> if ( Slot == - <NUM_LIT> ) { Error ( S , <STR_LIT> ) ; return MatchOperand_ParseFail ; } Operands . push_back ( <ISA_LIT>Operand :: CreateImm ( this , Slot , S , <ISA_LIT>Operand :: ImmTyInterpSlot ) ) ; return


<s> rvv_switcher rvv ; if ( ! TARGET_VECTOR ) return ; register_builtin_types (


<s> return ParseMemoryOperand ( Operands , <NUM_LIT> , false


<s> } else if ( Subtarget -> isRClass ( ) ) { ATS . emitAttribute ( <STR_LIT> , <STR_LIT> ) ; } else if ( Subtarget -> isMClass ( ) ) { ATS . emitAttribute ( <STR_LIT> , <STR_LIT> ) ; } ATS . emitAttribute ( <STR_LIT> , Subtarget -> has<ISA_LIT>Ops ( ) ? <STR_LIT> : <STR_LIT> ) ; if ( Subtarget -> isThumb1Only ( ) ) { ATS . emitAttribute ( <STR_LIT> , <STR_LIT> ) ; } else if ( Subtarget -> hasThumb2 ( ) ) { ATS . emitAttribute ( <STR_LIT> , <STR_LIT> ) ; } if ( Subtarget -> hasNEON ( ) ) { if ( Subtarget -> hasFP<ISA_LIT>v8 ( ) ) { if ( Subtarget -> hasCrypto ( ) ) ATS . emitFPU ( <STR_LIT> ) ; else ATS . emitFPU ( <STR_LIT> ) ; } else if ( Subtarget -> hasVFP4 ( ) ) ATS . emitFPU ( <STR_LIT> ) ; else ATS . emitFPU ( <STR_LIT> ) ; if ( Subtarget -> hasV8Ops ( ) ) ATS . emitAttribute ( <STR_LIT> , <STR_LIT> ) ; } else { if ( Subtarget -> hasFP<ISA_LIT>v8 ( ) ) ATS . emitFPU ( <STR_LIT> ) ; else if ( Subtarget -> hasVFP4 ( ) ) ATS . emitFPU ( Subtarget -> hasD16 ( ) ? <STR_LIT> : <STR_LIT> ) ; else if ( Subtarget -> hasVFP3 ( ) ) ATS . emitFPU ( Subtarget -> hasD16 ( ) ? <STR_LIT> : <STR_LIT> ) ; else if ( Subtarget -> hasVFP2 ( ) ) ATS . emitFPU ( <STR_LIT> ) ; } if ( ! TM . Options . UnsafeFPMath ) { ATS . emitAttribute ( <STR_LIT> , <STR_LIT> ) ; ATS . emitAttribute (


<s> void <ISA_LIT>Subtarget :: initializeEnvironment ( ) { UseSjLjEH = isTargetDarwin ( ) &&


<s> case <STR_LIT> : return LowerGlobalTLSAddress ( Op , DAG ) ; case <STR_LIT> : return LowerBlockAddress ( Op , DAG ) ; case <STR_LIT> : return LowerConstantPool ( Op , DAG ) ; case <STR_LIT> : return LowerBR_JT ( Op , DAG ) ; case <STR_LIT> : return LowerLOAD ( Op , DAG ) ; case <STR_LIT> : return LowerSTORE ( Op , DAG ) ; case <STR_LIT> : return LowerSELECT_CC ( Op , DAG ) ; case <STR_LIT> : return LowerVAARG ( Op , DAG ) ; case <STR_LIT> : return LowerVASTART ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return ExpandADDSUB ( Op . getNode (


<s> int _U_Qfle ( long double a , long double b ) { return ( _U_Qfcmp ( a , b , QCMP_INV | QCMP_EQ | QCMP_LT )


<s> BSSSection = new <ISA_LIT>Section ( MCSection :: SV_ELF , SectionKind :: getBSS ( ) ) ; ReadOnlySection = new <ISA_LIT>Section ( MCSection :: SV_ELF , SectionKind :: getReadOnly ( ) ) ; StaticCtorSection = new <ISA_LIT>Section ( MCSection :: SV_ELF , SectionKind :: getMetadata ( ) ) ; StaticDtorSection = new <ISA_LIT>Section ( MCSection :: SV_ELF , SectionKind :: getMetadata ( ) ) ; LSDASection = new <ISA_LIT>Section ( MCSection :: SV_ELF , SectionKind :: getMetadata ( ) ) ; EHFrameSection = new <ISA_LIT>Section ( MCSection :: SV_ELF , SectionKind :: getMetadata ( ) ) ; DwarfAbbrevSection = new <ISA_LIT>Section ( MCSection :: SV_ELF , SectionKind :: getMetadata ( ) ) ; DwarfInfoSection = new <ISA_LIT>Section ( MCSection :: SV_ELF , SectionKind :: getMetadata ( ) ) ; DwarfLineSection = new <ISA_LIT>Section ( MCSection :: SV_ELF , SectionKind :: getMetadata ( ) ) ; DwarfFrameSection = new <ISA_LIT>Section ( MCSection :: SV_ELF , SectionKind :: getMetadata ( ) ) ; DwarfPubTypesSection = new <ISA_LIT>Section ( MCSection :: SV_ELF , SectionKind :: getMetadata ( ) ) ; DwarfDebugInlineSection = new <ISA_LIT>Section ( MCSection :: SV_ELF , SectionKind :: getMetadata ( ) ) ; DwarfStrSection = new <ISA_LIT>Section ( MCSection :: SV_ELF , SectionKind :: getMetadata ( ) ) ; DwarfLocSection = new <ISA_LIT>Section ( MCSection :: SV_ELF , SectionKind :: getMetadata ( ) ) ; DwarfARangesSection = new <ISA_LIT>Section ( MCSection :: SV_ELF , SectionKind :: getMetadata ( ) ) ; DwarfRangesSection = new <ISA_LIT>Section ( MCSection :: SV_ELF , SectionKind


<s> for ( auto i = <NUM_LIT> ; i < latency ; i ++ ) { TM . getInstrInfo ( ) -> insertNoop ( * mbb , std :: next ( instrIter ) ) ; } instrIter = std :: next ( instrIter , <NUM_LIT> + latency ) ; } } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; mf . dump ( ) ) ; LLVM_DEBUG ( { dbgs ( ) << <STR_LIT> ; rootScope -> dump ( dbgs ( ) , <NUM_LIT> , true ) ; } )


<s> opNum = MI -> getNumOperands ( ) - <NUM_LIT> ; break ; } printOperand ( MI , opNum + <NUM_LIT> , O ) ; O << <STR_LIT> ; printOperand ( MI , opNum , O ) ; O << <STR_LIT>


<s> static SDValue Extract256BitVector ( SDValue Vec , unsigned IdxVal , SelectionDAG & DAG , SDLoc dl ) { assert ( Vec . getValueType ( ) . is512BitVector (


<s> if ( opts -> x_flag_align_labels && ! opts -> x_str_align_labels ) opts -> x_str_align_labels = processor_cost_table [ ix86_tune ] -> align_label ; if ( opts -> x_flag_align_functions && ! opts -> x_str_align_functions ) opts -> x_str_align_functions = processor_cost_table [ ix86_tune


<s> emit_update = ( saved_regs_mask & ( <NUM_LIT> << SP_REGNUM ) ) ? <NUM_LIT> : <NUM_LIT> ; par = gen_rtx_PARALLEL ( VOIDmode , rtvec_alloc ( num_regs + emit_update + offset_adj ) ) ; if ( return_in_pc ) XVECEXP ( par , <NUM_LIT> , <NUM_LIT> ) = ret_rtx ; if ( emit_update ) { tmp = gen_rtx_SET ( stack_pointer_rtx , plus_constant ( Pmode , stack_pointer_rtx , <NUM_LIT> * num_regs ) ) ; RTX_FRAME_RELATED_P ( tmp ) = <NUM_LIT> ; XVECEXP ( par , <NUM_LIT> , offset_adj ) = tmp ; } for ( j = <NUM_LIT> , i = <NUM_LIT> ; j < num_regs ; i ++ ) if ( saved_regs_mask & ( <NUM_LIT> << i ) ) { reg = gen_rtx_REG ( SImode , i ) ; if ( ( num_regs == <NUM_LIT> ) && emit_update && ! return_in_pc ) { tmp = gen_frame_mem ( SImode , gen_rtx_POST_INC ( Pmode , stack_pointer_rtx ) ) ; tmp = emit_insn ( gen_rtx_SET ( reg , tmp ) ) ; REG_NOTES ( tmp ) = alloc_reg_note ( REG_CFA_RESTORE , reg , dwarf ) ; return ; } tmp = gen_rtx_SET ( reg , gen_frame_mem ( SImode , plus_constant ( Pmode , stack_pointer_rtx , <NUM_LIT> * j ) ) ) ; RTX_FRAME_RELATED_P ( tmp ) = <NUM_LIT> ; XVECEXP ( par , <NUM_LIT> , j + emit_update + offset_adj ) = tmp ; if ( i != PC_REGNUM ) dwarf = alloc_reg_note ( REG_CFA_RESTORE , reg , dwarf ) ; j ++ ; } if ( return_in_pc ) par


<s> int m32c_trampoline_alignment ( void


<s> DecodeStatus DecodeGPRRegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t , const void * ) { if ( RegNo > <NUM_LIT> ) return MCDisassembler :: Fail ; unsigned Reg = GPRDecoderTable [ RegNo ] ; Inst . addOperand ( MCOperand :: createReg (


<s> unsigned Imm = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , Imm ) . addImm ( <NUM_LIT> - MVT ( From ) . getSizeInBits ( ) ) ; unsigned Left = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , Left ) . addReg ( Reg ) . addReg ( Imm ) ; unsigned Right = createResultReg (


<s> u . v = a ; u . i [ pos ] = b ; return u .


<s> AddDefaultPred ( BuildMI ( MBB , InsertBefore , DL , TII -> get ( <STR_LIT> ) , Out

) . addReg ( Ssub0 ) . addReg ( Ssub1 ) . addImm ( <NUM_LIT> ) ) ;


<s> <ISA_LIT>SplitConst32AndConst64 ( ) : MachineFunctionPass (


<s> if ( Cond [ <NUM_LIT> ] . getImm ( ) ) { if ( IsBrOnExn ) { const char * CPPExnSymbol = MF . createExternalSymbolName ( <STR_LIT> ) ; BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addMBB ( TBB ) . addExternalSymbol ( CPPExnSymbol , <STR_LIT> ) . add ( Cond [ <NUM_LIT> ] ) ; } else BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addMBB ( TBB ) . add ( Cond [ <NUM_LIT> ] ) ; } else { assert ( ! IsBrOnExn && <STR_LIT> ) ; BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addMBB ( TBB ) . add ( Cond [ <NUM_LIT> ] ) ; } if ( ! FBB ) return <NUM_LIT> ; BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) .


<s> assert ( ( Kind == RegisterList || Kind == DPRRegisterList || Kind


<s> bool & Interesting = ValueEntry -> first ; SmallVector < ValueBit , <NUM_LIT> > & Bits = ValueEntry -> second ; Bits . resize ( NumBits ) ; switch ( V . getOpcode ( ) ) { default : break ; case <STR_LIT> : if ( isa < ConstantSDNode > ( V . getOperand ( <NUM_LIT> ) ) ) { unsigned RotAmt = V . getConstantOperandVal ( <NUM_LIT> ) ; const auto & LHSBits = * getValueBits ( V . getOperand ( <NUM_LIT> ) , NumBits ) . second ; for ( unsigned i = <NUM_LIT> ; i < NumBits ; ++ i ) Bits [ i ] = LHSBits [ i < RotAmt ? i + ( NumBits - RotAmt ) : i - RotAmt ] ; return std :: make_pair ( Interesting = true , & Bits ) ; } break ; case <STR_LIT> : if ( isa < ConstantSDNode > ( V . getOperand ( <NUM_LIT> ) ) ) { unsigned ShiftAmt = V . getConstantOperandVal ( <NUM_LIT> ) ; const auto & LHSBits = * getValueBits ( V . getOperand ( <NUM_LIT> ) , NumBits ) . second ; for ( unsigned i = ShiftAmt ; i < NumBits ; ++ i ) Bits [ i ] = LHSBits [ i - ShiftAmt ] ; for ( unsigned i = <NUM_LIT> ; i < ShiftAmt ; ++ i ) Bits [ i ] = ValueBit ( ValueBit :: ConstZero ) ; return std :: make_pair ( Interesting = true , & Bits ) ; } break ; case <STR_LIT> : if ( isa < ConstantSDNode > ( V . getOperand ( <NUM_LIT> ) ) ) { unsigned ShiftAmt = V . getConstantOperandVal ( <NUM_LIT> ) ; const auto & LHSBits = * getValueBits ( V . getOperand ( <NUM_LIT> ) , NumBits


<s> void <ISA_LIT>AsmPrinter :: LowerPATCHABLE_FUNCTION_ENTER ( const MachineInstr & MI , <ISA_LIT>MCInstLower & MCIL ) { auto CurSled = OutContext . createTempSymbol ( <STR_LIT> , true ) ; OutStreamer -> EmitCodeAlignment ( <NUM_LIT> ) ; OutStreamer -> EmitLabel ( CurSled ) ; OutStreamer -> EmitBytes ( <STR_LIT> ) ; EmitNops ( * OutStreamer , <NUM_LIT> , Subtarget -> is64Bit ( ) , getSubtargetInfo ( ) ) ; recordSled ( CurSled , MI , SledKind :: FUNCTION_ENTER


<s> static bool mips_use_shadow_register_set_p (


<s> SDLoc Dl ( Op ) ; SDValue Victim = Op . getOperand ( <NUM_LIT> ) ; assert ( isa < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) ) ; int ShiftAmount = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; if ( ShiftAmount == <NUM_LIT> ) return shiftBy8 ( Op , DAG ) ; switch ( Op . getOpcode ( ) ) { case <STR_LIT>


<s> static bool mips_return_in_memory ( const_tree type , const_tree fndecl ATTRIBUTE_UNUSED ) { if ( TARGET_OLDABI ) return ( VECTOR_FLOAT_TYPE_P ( type ) || TYPE_MODE ( type ) == BLKmode ) ; return ( ! IN_RANGE ( int_size_in_bytes ( type ) , <NUM_LIT> , <NUM_LIT>


<s> } , <STR_LIT> ) ; } ) ) { return true ; } break ; } case <STR_LIT> : { auto arg1 = II -> getArgOperand ( <NUM_LIT> ) ; assert ( arg1 -> getType ( ) -> isIntegerTy ( <NUM_LIT> ) ) ; if ( eliminate_mem_intrinsic ( F , II , <STR_LIT> , [ & ] ( auto * arg0 , auto * arg2 , auto len ) { eliminate < std :: pair < Value * , Value * > , PHINode * > ( F , BB , instr_iter , len , <NUM_LIT> , [ & ] ( auto & builder , auto entry_block ) { Value * val_i32_done ; if ( auto * set_to_const = dyn_cast < ConstantInt > ( arg1 ) ) { auto set_to_val = set_to_const -> getValue ( ) . getLimitedValue ( std :: numeric_limits < uint16_t > :: max ( ) ) ; assert ( set_to_val <= std :: numeric_limits < uint8_t > :: max ( ) && <STR_LIT> ) ; auto set_to_shl8 = set_to_val << <NUM_LIT> ; auto set_to_half = set_to_shl8 + set_to_val ; auto set_to_upper = set_to_half << <NUM_LIT> ; val_i32_done = builder . getInt32 ( set_to_upper + set_to_half ) ; } else { auto * val_i32 = builder . CreateZExt ( arg1 , Type :: getInt32Ty ( F . getContext ( ) ) ) ; auto * val_shl8 = builder . CreateShl ( val_i32 , builder . getInt32 ( <NUM_LIT> ) ) ; auto * val_halfword = builder . CreateAdd ( val_shl8 , val_i32 ) ; auto * val_upper = builder . CreateShl ( val_halfword , builder . getInt32 ( <NUM_LIT> ) ) ; auto * val_i32_done_instr = builder . CreateAdd ( val_halfword , val_upper , <STR_LIT> ) ; val_i32_done = val_i32_done_instr ; } auto * dest_i32 = builder . CreateBitCast ( arg0 , PointerType :: get ( builder . getInt32Ty ( ) , <NUM_LIT> ) , <STR_LIT> ) ; return std :: make_pair ( dest_i32 , val_i32_done ) ; } , [ & ] ( auto & builder , auto entry_block , auto entry_ret , auto condition_block ) { auto * dest_phi = builder . CreatePHI ( PointerType :: get ( builder . getInt32Ty ( ) , <NUM_LIT> )


<s> unsigned <ISA_LIT>FastISel :: fastMaterializeAlloca ( const AllocaInst * AI ) { DenseMap < const AllocaInst * , int > :: iterator SI = FuncInfo . StaticAllocaMap . find ( AI ) ; if ( SI != FuncInfo . StaticAllocaMap . end ( ) ) { Register ResultReg = createResultReg ( Subtarget -> hasAddr64 ( ) ? & <STR_LIT> : & <STR_LIT> ) ; unsigned Opc = Subtarget -> hasAddr64 ( ) ? <STR_LIT> : <STR_LIT> ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , ResultReg ) . addFrameIndex ( SI -> second ) ; return ResultReg


<s> LoadsToReplace . push_back ( LD ) ; } else if ( StoreSDNode * ST = dyn_cast < StoreSDNode > ( & Node ) ) { SDValue Value = ST -> getValue ( ) ; if ( Value . getValueType ( ) != <STR_LIT> || ST -> isTruncatingStore ( ) ) continue ; StoresToReplace . push_back ( ST ) ; } } for ( LoadSDNode * LD : LoadsToReplace ) { SDLoc SL ( LD ) ; SDValue NewLoad = CurDAG -> getLoad ( <STR_LIT> , SL , LD -> getChain ( ) , LD -> getBasePtr ( ) , LD -> getMemOperand ( ) ) ; SDValue BitCast = CurDAG -> getNode ( <STR_LIT> , SL , <STR_LIT> , NewLoad ) ; CurDAG -> ReplaceAllUsesOfValueWith ( SDValue ( LD , <NUM_LIT> ) , NewLoad . getValue ( <NUM_LIT> ) ) ; CurDAG -> ReplaceAllUsesOfValueWith ( SDValue ( LD , <NUM_LIT> ) , BitCast ) ; Modified = true ; } for ( StoreSDNode * ST : StoresToReplace


<s> assert ( VT . isVector ( ) && <STR_LIT> ) ; int64_t ElementBits = VT . getScalarSizeInBits ( ) ; if ( ! getVShiftImm ( Op ,


<s> __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) _mm_encodekey256_u32 ( unsigned int


<s> return hash_rtx ( p1 , VOIDmode , NULL ,


<s> if ( MI -> isCopy ( ) ) CopySrcReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; else { assert ( MI -> isSubregToReg ( ) && <STR_LIT> ) ; CopySrcReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; } if ( ! TargetRegisterInfo :: isVirtualRegister ( CopySrcReg ) ) return CopySrcReg ; SrcReg =


<s> for ( MCSubRegIterator SubRegs ( VA . getLocReg ( ) , TRI , true ) ; SubRegs . isValid ( ) ; ++ SubRegs ) RegMask [ * SubRegs / <NUM_LIT> ] &= ~ ( <NUM_LIT> << ( * SubRegs % <NUM_LIT> ) ) ; } if ( ! Subtarget . hasSSE1 ( ) && <STR_LIT> . contains ( VA . getLocReg ( ) ) ) { errorUnsupported ( DAG , dl , <STR_LIT> ) ; if ( VA . getLocReg ( ) == <STR_LIT> ) VA . convertToReg ( <STR_LIT> ) ; else VA . convertToReg ( <STR_LIT> ) ; } else if ( ! Subtarget . hasSSE2 ( ) && <STR_LIT> . contains ( VA . getLocReg ( ) ) && CopyVT == <STR_LIT> ) { errorUnsupported ( DAG , dl , <STR_LIT> ) ; if ( VA . getLocReg ( ) == <STR_LIT> ) VA . convertToReg ( <STR_LIT> ) ; else VA . convertToReg ( <STR_LIT> ) ; } bool RoundAfterCopy = false ; if ( ( VA . getLocReg ( ) == <STR_LIT> || VA . getLocReg ( ) == <STR_LIT> ) && isScalarFPTypeInSSEReg ( VA . getValVT ( ) ) ) { if ( ! Subtarget . hasX87 ( ) ) report_fatal_error ( <STR_LIT> ) ; CopyVT = <STR_LIT> ; RoundAfterCopy = ( CopyVT != VA . getLocVT ( ) ) ; } SDValue Val ; if ( VA . needsCustom ( ) ) { assert ( VA . getValVT ( ) == <STR_LIT> && <STR_LIT> ) ; Val = getv64i1Argument ( VA , RVLocs [ ++ I ] , Chain , DAG , dl , Subtarget , & InFlag ) ; }


<s> if ( LABEL_P ( lab ) && LABEL_NUSES ( lab ) < uses_threshold ) return <NUM_LIT> ; if ( optimize_size ) return <NUM_LIT> ; int max_skip = rx_max_skip_for_label ( lab ) ; if ( max_skip <= <NUM_LIT>


<s> for ( auto U : V . users ( ) ) if ( auto * I = dyn_cast < Instruction > ( U ) ) if ( hasVolatileAccess ( I ) ) return true ; return false


<s> void <ISA_LIT>InstPrinter :: printVectorListOneAllLanes ( const MCInst * MI , unsigned OpNum , raw_ostream & O ) { O << <STR_LIT> << getRegisterName ( MI -> getOperand ( OpNum ) . getReg (


<s> sigstk . ss_sp = xmalloc ( SIGSTKSZ ) ; sigstk . ss_size = SIGSTKSZ ; sigstk . ss_flags = <NUM_LIT> ; if ( sigaltstack ( & sigstk , NULL ) < <NUM_LIT> ) fatal_error ( <STR_LIT> ) ; sigemptyset ( & sact . sa_mask ) ; sact . sa_flags = SA_ONSTACK | SA_SIGINFO ; sact . sa_sigaction =


<s> if ( IsPCRel && RelocType == MachO :: <ISA_LIT>_RELOC_VANILLA ) Offset += <NUM_LIT> << Log2Size ; if ( Offset && A && ! Writer -> doesSymbolRequireExternRelocation ( * A ) ) return Record<ISA_LIT>ScatteredRelocation ( Writer , Asm , Layout , Fragment , Fixup , Target , RelocType , Log2Size , FixedValue ) ; uint32_t FixupOffset = Layout . getFragmentOffset ( Fragment ) + Fixup . getOffset ( ) ; unsigned Index = <NUM_LIT> ; unsigned Type = <NUM_LIT> ; const MCSymbol * RelSymbol = nullptr ; if ( Target . isAbsolute ( ) ) { report_fatal_error ( <STR_LIT> <STR_LIT> ) ; } else { if ( A -> isVariable ( ) ) { int64_t Res ; if ( A -> getVariableValue ( ) -> evaluateAsAbsolute ( Res , Layout , Writer -> getSectionAddressMap ( ) ) ) { FixedValue = Res ; return ; } } if ( requiresExternRelocation ( Writer , Asm , * Fragment , RelocType , * A , FixedValue ) ) { RelSymbol = A ; if ( ! A -> isUndefined ( ) ) FixedValue -= Layout . getSymbolOffset ( * A ) ; } else { const MCSection & Sec = A -> getSection ( ) ; Index = Sec . getOrdinal ( ) + <NUM_LIT> ; FixedValue += Writer -> getSectionAddress ( & Sec ) ; } if ( IsPCRel ) FixedValue -= Writer -> getSectionAddress ( Fragment -> getParent ( ) ) ; Type = RelocType ; } MachO :: any_relocation_info MRE ; MRE . r_word0 = FixupOffset ; MRE . r_word1 = ( Index << <NUM_LIT> ) | ( IsPCRel << <NUM_LIT> ) | ( Log2Size << <NUM_LIT> ) | ( Type << <NUM_LIT> ) ; if ( Type == MachO :: <ISA_LIT>_RELOC_HALF ) { uint32_t Value = <NUM_LIT> ; switch ( ( unsigned ) Fixup . getKind ( ) ) { default : break ; case <STR_LIT> : case <STR_LIT> : Value = ( FixedValue >> <NUM_LIT> ) & <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : Value = FixedValue & <NUM_LIT> ; break ; } MachO :: any_relocation_info MREPair ; MREPair . r_word0 = Value ; MREPair . r_word1 = ( ( <NUM_LIT> << <NUM_LIT> ) | ( Log2Size << <NUM_LIT> ) | ( MachO :: <ISA_LIT>_RELOC_PAIR << <NUM_LIT> ) ) ; Writer -> addRelocation ( nullptr , Fragment -> getParent ( ) , MREPair ) ; } Writer -> addRelocation ( RelSymbol , Fragment -> getParent (


<s> const uint64_t QW = eatBytes < uint64_t > ( Bytes ) ; Res = tryDecodeInst ( DecoderTableDPP64 , MI , QW , Address ) ; if ( Res ) break ; Res = tryDecodeInst ( DecoderTableSDWA64 , MI , QW , Address ) ; if ( Res ) { IsSDWA = true ; break ; } Res = tryDecodeInst ( DecoderTableSDWA964 , MI , QW , Address ) ; if ( Res ) { IsSDWA = true ; break ; } } Bytes = Bytes_ . slice ( <NUM_LIT> , MaxInstBytesNum ) ; if ( Bytes . size ( ) < <NUM_LIT> ) break ; const uint32_t DW = eatBytes < uint32_t > ( Bytes ) ; Res = tryDecodeInst ( DecoderTableVI32 , MI , DW , Address ) ; if ( Res ) break ; Res = tryDecodeInst ( DecoderTable<ISA_LIT>32 , MI , DW , Address ) ; if ( Res ) break ; if ( Bytes . size (


<s> GetElementPtrInst * GEP = cast < GetElementPtrInst > ( stripBitcasts ( Ptr ) ) ; auto I = GEPIdx . find ( GEP ) ; return I == GEPIdx . end ( ) ?


<s> if ( AssignFn ( ValNo , ValVT , LocVT , LocInfo , Info . Flags , State ) ) return true ; StackSize = std :: max ( StackSize , static_cast < uint64_t > ( State . getNextStackOffset ( ) ) ) ; return


<s> return __builtin_aarch64_simd_bslv4hi_uuuu ( __a ,


<s> void <ISA_LIT>FrameLowering :: emitCalleeSavedSVERestores ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI ) const { emitCalleeSavedRestores ( MBB , MBBI


<s> MCOperand MCOp ; switch ( MO . getType ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case MachineOperand :: MO_GlobalAddress : { Register FuncReg = MAI -> getFuncReg ( MO . getGlobal ( ) -> getGlobalIdentifier ( ) ) ; assert ( FuncReg . isValid ( ) && <STR_LIT> ) ; MCOp = MCOperand :: createReg ( FuncReg ) ; break ; } case MachineOperand :: MO_MachineBasicBlock : MCOp = MCOperand :: createReg ( MAI -> getOrCreateMBBRegister ( *


<s> } if ( <STR_LIT> . contains ( SrcReg ) && <STR_LIT> . contains ( DestReg ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg , KillFlag ) ; return ; } if ( <STR_LIT> . contains ( SrcReg ) && <STR_LIT> . contains ( DestReg ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg , KillFlag ) ; return ; } if ( <STR_LIT> . contains ( SrcReg , DestReg ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg , KillFlag ) ; return ; } if ( <STR_LIT> . contains ( SrcReg , DestReg ) ) { unsigned LoSrc = HRI . getSubReg ( SrcReg , <STR_LIT> ) ; unsigned HiSrc = HRI . getSubReg ( SrcReg , <STR_LIT> ) ; BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( HiSrc , KillFlag ) . addReg ( LoSrc , KillFlag ) ; return ; } if ( <STR_LIT> . contains ( SrcReg , DestReg ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg ) . addReg ( SrcReg , KillFlag ) ; return ; } if ( <STR_LIT> . contains ( SrcReg ) && <STR_LIT> . contains ( DestReg ) ) { llvm_unreachable (


<s> SMLoc S = Parser . getTok ( ) . getLoc ( ) ; const AsmToken & Tok = Parser . getTok ( ) ; if ( Tok . isNot ( AsmToken :: Identifier ) ) return MatchOperand_NoMatch ; if ( ! Tok . getString ( ) . equals_lower ( <STR_LIT> ) ) return MatchOperand_NoMatch ; Parser . Lex ( )


<s> SDValue Op0 = N -> getOperand ( <NUM_LIT> ) ; SDValue Op1 = N -> getOperand ( <NUM_LIT> ) ; if ( SDValue MAdd = matchPMADDWD ( DAG , Op0 , Op1 , SDLoc ( N ) , VT , Subtarget ) ) return MAdd ; if ( SDValue MAdd = matchPMADDWD_2 ( DAG , Op0 , Op1 , SDLoc ( N ) , VT , Subtarget ) ) return MAdd ; if ( ( VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> ) && Subtarget . hasSSSE3 ( ) && isHorizontalBinOp ( Op0 , Op1 , DAG , Subtarget , true ) ) { auto HADDBuilder = [ ] ( SelectionDAG & DAG , const SDLoc & DL , ArrayRef < SDValue > Ops ) { return DAG . getNode ( <STR_LIT> , DL , Ops [ <NUM_LIT> ] . getValueType ( ) , Ops ) ; } ; return SplitOpsAndApply ( DAG , Subtarget , SDLoc ( N ) , VT , { Op0 , Op1 } , HADDBuilder ) ; } if ( VT . isVector ( ) ) { const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; if ( Op0 . getOpcode ( ) == <STR_LIT> && Op0 . getOperand ( <NUM_LIT> ) . getValueType ( ) . getVectorElementType ( ) == <STR_LIT> && TLI . isTypeLegal ( Op0 . getOperand ( <NUM_LIT> ) . getValueType ( ) ) ) { SDLoc DL ( N ) ; SDValue SExt = DAG . getNode ( <STR_LIT> , DL , VT , Op0 . getOperand ( <NUM_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , DL , VT , Op1 , SExt ) ; } if ( Op1 . getOpcode ( ) == <STR_LIT> && Op1 . getOperand ( <NUM_LIT> ) . getValueType ( ) . getVectorElementType ( ) == <STR_LIT> && TLI . isTypeLegal ( Op1 . getOperand ( <NUM_LIT> ) . getValueType ( ) ) ) { SDLoc DL ( N


<s> } if ( auto * VTy = dyn_cast < VectorType > ( Ty ) ) { unsigned Num = cast < FixedVectorType > ( VTy ) -> getNumElements ( ) ; unsigned Cost = getArithmeticInstrCost ( Opcode , VTy -> getScalarType ( ) , CostKind , Opd1Info , Opd2Info , Opd1PropInfo , Opd2PropInfo , Args , CxtI ) ; return getScalarizationOverhead ( VTy , Args ) + Num * Cost ; } return OpCost ; } std :: pair < int , MVT > LT = TLI -> getTypeLegalizationCost ( DL , Ty ) ; int ISD = TLI -> InstructionOpcodeToISD ( Opcode ) ; unsigned NElts = LT . second . isVector ( ) ? LT . second . getVectorNumElements ( ) : <NUM_LIT> ; <STR_LIT> SLT = LT . second . getScalarType ( ) . SimpleTy ; switch ( ISD ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( SLT == <STR_LIT> ) return get64BitInstrCost ( CostKind ) * LT . first * NElts ; if ( ST -> has16BitInsts ( ) && SLT == <STR_LIT> ) NElts = ( NElts + <NUM_LIT> ) / <NUM_LIT> ; return getFullRateInstrCost ( ) * LT . first * NElts ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( SLT == <STR_LIT> ) { return <NUM_LIT> * getFullRateInstrCost ( ) * LT . first * NElts ; } if ( ST -> has16BitInsts ( ) && SLT == <STR_LIT> ) NElts = ( NElts + <NUM_LIT> ) / <NUM_LIT> ; return LT . first * NElts * getFullRateInstrCost ( ) ; case <STR_LIT> : { const int QuarterRateCost = getQuarterRateInstrCost ( CostKind ) ; if ( SLT == <STR_LIT> ) { const int FullRateCost = getFullRateInstrCost ( ) ; return ( <NUM_LIT> * QuarterRateCost + ( <NUM_LIT> * <NUM_LIT> ) * FullRateCost ) * LT . first * NElts ; } if ( ST -> has16BitInsts ( ) && SLT == <STR_LIT> ) NElts = ( NElts + <NUM_LIT> ) / <NUM_LIT> ; return QuarterRateCost * NElts * LT . first ; } case <STR_LIT> : if ( CxtI && CxtI -> hasOneUse ( ) ) if ( const auto * FAdd = dyn_cast < BinaryOperator > ( * CxtI -> user_begin ( ) ) ) { const int OPC = TLI -> InstructionOpcodeToISD ( FAdd -> getOpcode ( ) ) ; if ( OPC == <STR_LIT> || OPC == <STR_LIT> ) { if ( ST -> hasMadMacF32Insts ( ) && SLT == <STR_LIT> && ! HasFP32Denormals ) return TargetTransformInfo :: TCC_Free ; if ( ST -> has16BitInsts ( ) && SLT == <STR_LIT> && ! HasFP64FP16Denormals ) return TargetTransformInfo :: TCC_Free ; const TargetOptions & Options = TLI -> getTargetMachine ( ) . Options ; if ( Options . AllowFPOpFusion == FPOpFusion :: Fast || Options . UnsafeFPMath || ( FAdd -> hasAllowContract ( ) && CxtI -> hasAllowContract ( ) ) ) return TargetTransformInfo :: TCC_Free ; } } LLVM_FALLTHROUGH ; case


<s> DebugLoc dl = MI -> getDebugLoc ( ) ; MachineBasicBlock * loopMBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * exitMBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; F -> insert ( It , loopMBB ) ; F -> insert ( It , exitMBB ) ; exitMBB -> splice ( exitMBB -> begin ( ) , BB , std :: next ( MachineBasicBlock :: iterator ( MI ) ) , BB -> end ( ) ) ; exitMBB -> transferSuccessorsAndUpdatePHIs ( BB ) ; MachineRegisterInfo & RegInfo = F -> getRegInfo ( ) ; unsigned TmpReg = ( ! BinOpcode ) ? incr : RegInfo . createVirtualRegister ( is64bit ? ( const TargetRegisterClass * ) & <STR_LIT> : ( const TargetRegisterClass * ) & <STR_LIT> ) ; BB -> addSuccessor ( loopMBB ) ; BB = loopMBB ; BuildMI ( BB , dl , TII -> get ( is64bit ? <STR_LIT> : <STR_LIT> ) , dest ) . addReg ( ptrA ) . addReg ( ptrB ) ; if ( BinOpcode ) BuildMI ( BB , dl , TII -> get ( BinOpcode ) , TmpReg ) . addReg ( incr ) . addReg ( dest ) ; BuildMI ( BB , dl , TII -> get ( is64bit ? <STR_LIT> : <STR_LIT> ) ) . addReg ( TmpReg ) . addReg ( ptrA ) . addReg ( ptrB ) ; BuildMI ( BB , dl , TII -> get ( <STR_LIT> ) ) . addImm ( <STR_LIT> ) .

addReg ( <STR_LIT> ) . addMBB ( loopMBB ) ;


<s> StringRef IDVal = DirectiveID . getString ( ) ; if ( IDVal == <STR_LIT> ) return parseDirectiveAttribute (


<s> static MCDisassembler * create<ISA_LIT>Disassembler ( const Target & T , const MCSubtargetInfo & STI , MCContext & Ctx ) { return new <ISA_LIT>Disassembler ( STI , Ctx


<s> Indent = <NUM_LIT> ; SelectRoot ( * CurDAG ) ; DOUT ( llvm :: dbgs ( )


<s> void emitHandlerDataLocNotes ( ) const { for ( const SMLoc & Loc : HandlerDataLocs ) Parser . Note (


<s> default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( NumIssued == <NUM_LIT> ) return Hazard ; break ; case <STR_LIT> : if ( NumIssued >= <NUM_LIT> ) return Hazard ; break ; case <STR_LIT> : break ; } if ( HasCTRSet && ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) ) return NoopHazard ; if ( isLoad && NumStores ) { unsigned LoadSize ; switch ( Opcode ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : LoadSize = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : LoadSize = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : LoadSize = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : LoadSize = <NUM_LIT> ; break ; case


<s> else error ( <STR_LIT> <STR_LIT> , type ) ; } return <NUM_LIT> ; } return <NUM_LIT> ; } if ( ! decl ) return <NUM_LIT> ; cgraph_node * target = cgraph_node :: get ( decl ) ; if ( target ) target = target -> function_symbol ( ) ; if ( target && ( target_opts_for_fn ( target -> decl ) -> x_ix86_fpmath & FPMATH_SSE ) && opt_for_fn ( target -> decl , optimize ) && ! ( profile_flag && ! flag_fentry ) ) { cgraph_local_info * i = & target -> local ; if ( i && i -> local && i -> can_change_signature ) { if ( ! TARGET_SSE && warn ) { error ( <STR_LIT> <STR_LIT> , decl ) ; return <NUM_LIT> ; } return TARGET_SSE2_P ( target_opts_for_fn ( target -> decl ) ->


<s> Inst . addOperand ( MCOperand :: createImm ( Field << <NUM_LIT> ) ) ; return MCDisassembler ::


<s> if ( Op . hasOneUse ( ) && <STR_LIT> ( Op . getNode ( ) ) ) { Op = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; Op = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op ) ; } else return DAG . getNode ( <STR_LIT> , DL , DAG . getVTList ( VT , <STR_LIT> ) , Op , Op ) . getValue ( <NUM_LIT> ) ; } else if ( VT == <STR_LIT> ) Op = DAG . getTargetExtractSubreg ( <STR_LIT> , DL , <STR_LIT> , Op ) ; assert ( Op . getValueType ( ) == <STR_LIT>


<s> if ( scalar ) { fc = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> | fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) | fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ; unsigned Rm = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; if ( ! Check ( S , DecodeGPRwithZRRegisterClass ( Inst , Rm , Address , Decoder ) ) ) return MCDisassembler :: Fail ; } else { fc = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> | fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) | fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ; unsigned Qm = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> | fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; if ( ! Check ( S , DecodeMQPRRegisterClass ( Inst , Qm , Address , Decoder ) ) ) return MCDisassembler :: Fail ; } if ( ! Check ( S , predicate_decoder ( Inst , fc , Address , Decoder ) ) ) return MCDisassembler :: Fail ; Inst . addOperand ( MCOperand :: createImm ( <STR_LIT> ) ) ; Inst . addOperand ( MCOperand :: createReg ( <NUM_LIT> ) ) ; Inst . addOperand ( MCOperand :: createImm ( <NUM_LIT>


<s> InstructionCost <ISA_LIT>TTIImpl :: getGSScalarCost ( unsigned Opcode , Type * SrcVTy , bool VariableMask , Align Alignment , unsigned AddressSpace ) { unsigned VF = cast < FixedVectorType > ( SrcVTy ) -> getNumElements ( ) ; APInt DemandedElts = APInt :: getAllOnes ( VF ) ; TTI :: TargetCostKind CostKind = TTI :: TCK_RecipThroughput ; InstructionCost MaskUnpackCost = <NUM_LIT> ; if ( VariableMask ) { auto * MaskTy = FixedVectorType :: get ( Type :: getInt1Ty ( SrcVTy -> getContext ( ) ) , VF ) ; MaskUnpackCost = getScalarizationOverhead ( MaskTy , DemandedElts ,


<s> if ( checkSig ( ErrorLoc , * Sig ) ) return true ; } else if ( Name == <STR_LIT> ) { const MCSymbolRefExpr * SymRef ; if ( getSymRef ( ErrorLoc , Inst , SymRef ) ) return true ; const auto * WasmSym = cast < MCSymbolWasm > ( & SymRef -> getSymbol ( ) ) ; const auto * Sig = WasmSym -> getSignature ( ) ; if ( ! Sig || WasmSym -> getType ( ) != <STR_LIT> ) return typeError ( ErrorLoc , StringRef ( <STR_LIT> ) + WasmSym -> getName ( ) + <STR_LIT> ) ; Stack . insert ( Stack . end ( ) , Sig -> Params . begin ( ) , Sig -> Params . end ( ) ) ; } else if ( Name == <STR_LIT> ) { auto VT = static_cast < <STR_LIT> > ( Inst . getOperand ( <NUM_LIT> ) . getImm ( ) ) ; Stack . push_back ( VT ) ; } else { auto RegOpc = <STR_LIT> ( Opc ) ; assert ( RegOpc != - <NUM_LIT> && <STR_LIT> ) ; const auto & II = MII . get ( RegOpc ) ; for ( unsigned I = II . getNumOperands ( ) ; I > II . getNumDefs ( ) ; I -- ) { const auto & Op = II . OpInfo [ I - <NUM_LIT> ] ; if ( Op . OperandType == MCOI :: OPERAND_REGISTER ) { auto VT = <STR_LIT> ( Op . RegClass ) ; if ( popType ( ErrorLoc , VT ) ) return true ; } } for ( unsigned I = <NUM_LIT> ; I < II . getNumDefs ( ) ; I ++ ) { const auto & Op = II . OpInfo [ I ] ; assert ( Op . OperandType == MCOI


<s> LSDAEncoding = dwarf :: DW_EH_PE_pcrel | dwarf :: DW_EH_PE_sdata4 ; PersonalityEncoding = dwarf :: DW_EH_PE_indirect | dwarf :: DW_EH_PE_pcrel | dwarf :: DW_EH_PE_sdata4 ; TTypeEncoding = dwarf :: DW_EH_PE_indirect | dwarf ::


<s> bool <ISA_LIT>InstrInfo :: SubsumesPredicate ( const SmallVectorImpl < MachineOperand > & Pred1 , const SmallVectorImpl < MachineOperand > & Pred2 ) const { assert ( Pred1 . size ( ) == <NUM_LIT> && <STR_LIT> ) ; assert ( Pred2 . size ( ) == <NUM_LIT> && <STR_LIT> ) ; if ( Pred1 [ <NUM_LIT> ] . getReg ( ) == <STR_LIT> || Pred1 [ <NUM_LIT> ] . getReg ( ) == <STR_LIT> ) return false ; if ( Pred2 [ <NUM_LIT> ] . getReg ( ) == <STR_LIT> || Pred2 [ <NUM_LIT> ] . getReg ( ) ==


<s> unsigned Tmp = std :: min ( Tmp0 , Tmp1 ) ; if ( Tmp > ( SrcBits - VTBits ) ) return Tmp - ( SrcBits - VTBits ) ; return <NUM_LIT> ; } case <STR_LIT> : { SDValue Src = Op . getOperand ( <NUM_LIT> ) ; APInt ShiftVal = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getAPIntValue ( ) ; if ( ShiftVal . uge ( VTBits ) ) return VTBits ; unsigned Tmp = DAG . ComputeNumSignBits ( Src , DemandedElts , Depth + <NUM_LIT> ) ; if ( ShiftVal . uge ( Tmp ) ) return <NUM_LIT> ; return Tmp - ShiftVal . getZExtValue ( ) ; } case <STR_LIT> : { SDValue Src = Op . getOperand ( <NUM_LIT> ) ; APInt ShiftVal = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getAPIntValue ( ) ; if ( ShiftVal . uge ( VTBits - <NUM_LIT> ) ) return VTBits ; unsigned Tmp = DAG . ComputeNumSignBits ( Src , DemandedElts , Depth + <NUM_LIT> ) ; ShiftVal += Tmp ; return ShiftVal . uge ( VTBits ) ? VTBits : ShiftVal . getZExtValue ( ) ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> std :: pair < SDValue , SDValue > <ISA_LIT>SelectionDAGInfo :: EmitTargetCodeForMemchr ( SelectionDAG & DAG , const SDLoc & DL , SDValue Chain , SDValue Src , SDValue Char , SDValue Length , MachinePointerInfo SrcPtrInfo ) const { EVT PtrVT = Src . getValueType ( ) ; SDVTList VTs = DAG . getVTList ( PtrVT , <STR_LIT> , <STR_LIT> ) ; Length = DAG . getZExtOrTrunc ( Length , DL , PtrVT ) ; Char = DAG . getZExtOrTrunc ( Char , DL , <STR_LIT> ) ; Char = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Char , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; SDValue Limit = DAG . getNode ( <STR_LIT> , DL , PtrVT


<s> void <ISA_LIT>16InstrInfo :: adjustStackPtrBigUnrestricted ( unsigned SP , int64_t Amount , MachineBasicBlock &

MBB , MachineBasicBlock :: iterator I ) const {


<s> getDirectBrEncoding ( const MCInst & MI , unsigned OpNo , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { const MCOperand & MO = MI . getOperand ( OpNo ) ; if ( MO . isReg ( ) || MO . isImm ( ) ) return getMachineOpValue ( MI , MO , Fixups , STI ) ; Fixups . push_back ( MCFixup :: create ( <NUM_LIT> , MO . getExpr ( ) , ( ( MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> ) ? ( MCFixupKind ) <STR_LIT> : ( MCFixupKind ) <STR_LIT> ) ) ) ; return <NUM_LIT>


<s> case ImmTyDFMT : OS << <STR_LIT> ; break ; case ImmTyNFMT : OS << <STR_LIT> ; break ; case ImmTyClamp<ISA_LIT> : OS << <STR_LIT> ; break ; case ImmTyOMod<ISA_LIT> : OS << <STR_LIT> ; break ; case ImmTyDppCtrl : OS << <STR_LIT> ; break ; case ImmTyDppRowMask : OS << <STR_LIT> ; break ; case ImmTyDppBankMask : OS << <STR_LIT> ; break ; case ImmTyDppBoundCtrl : OS << <STR_LIT> ; break ; case ImmTySdwaDstSel : OS << <STR_LIT> ; break ; case ImmTySdwaSrc0Sel : OS << <STR_LIT> ; break ; case ImmTySdwaSrc1Sel : OS << <STR_LIT> ; break ; case ImmTySdwaDstUnused : OS << <STR_LIT> ; break ; case ImmTyDMask : OS << <STR_LIT> ; break ; case ImmTyUNorm : OS << <STR_LIT> ; break ; case ImmTyDA : OS << <STR_LIT> ; break ; case ImmTyR128 : OS << <STR_LIT> ; break ; case ImmTyLWE : OS << <STR_LIT> ; break ; case ImmTyOff : OS << <STR_LIT> ; break ; case ImmTyExpTgt : OS << <STR_LIT> ; break ; case ImmTyExpCompr : OS << <STR_LIT> ; break ; case ImmTyExpVM : OS << <STR_LIT> ; break ; case ImmTyHwreg : OS << <STR_LIT> ; break ; case ImmTySendMsg : OS << <STR_LIT> ; break ; case ImmTyInterpSlot : OS << <STR_LIT> ; break ; case ImmTyInterpAttr : OS << <STR_LIT> ; break ; case ImmTyAttrChan : OS << <STR_LIT> ; break ; case ImmTyOpSel : OS << <STR_LIT> ; break ; case ImmTyOpSelHi : OS << <STR_LIT> ; break ; case ImmTyNegLo : OS <<


<s> break ; } while ( num_args > <NUM_LIT> && h . mode [ num_args ] == VOIDmode ) num_args -- ; ret_type = builtin_mode_to_type [ h . mode [ <NUM_LIT> ] ] [ h . uns_p [ <NUM_LIT> ] ] ; if ( ! ret_type && h . uns_p [ <NUM_LIT> ] ) ret_type = builtin_mode_to_type [ h . mode [ <NUM_LIT> ] ] [ <NUM_LIT> ] ; if ( ! ret_type ) fatal_error ( input_location , <STR_LIT> <STR_LIT> , name , GET_MODE_NAME ( h . mode [ <NUM_LIT> ] ) ) ; for ( i = <NUM_LIT> ; i < ( int ) ARRAY_SIZE ( arg_type ) ; i ++ ) arg_type [ i ] = NULL_TREE ; for ( i = <NUM_LIT> ; i < num_args ; i ++ ) { int m = ( int ) h . mode [ i + <NUM_LIT> ] ; int uns_p = h . uns_p [ i + <NUM_LIT> ] ; arg_type [ i ] = builtin_mode_to_type [ m ] [ uns_p ] ; if ( ! arg_type [ i ] && uns_p ) arg_type [ i ] = builtin_mode_to_type [ m ] [ <NUM_LIT> ] ; if ( ! arg_type [ i ] ) fatal_error ( input_location , <STR_LIT> <STR_LIT> , name , i , GET_MODE_NAME ( m ) ) ; } builtin_hash_struct * * found = builtin_hash_table -> find_slot ( & h , INSERT ) ; if ( * found == NULL ) { h2 = ggc_alloc < builtin_hash_struct > ( ) ; * h2 = h ; * found = h2 ; h2 -> type = build_function_type_list ( ret_type , arg_type [ <NUM_LIT> ] , arg_type [ <NUM_LIT> ] , arg_type [ <NUM_LIT> ] , NULL_TREE ) ; } return ( * found )


<s> bool <ISA_LIT>PreTileConfig :: runOnMachineFunction ( MachineFunction & mf ) { MF = & mf ; MRI = & mf . getRegInfo ( ) ; ST = & mf . getSubtarget < <ISA_LIT>Subtarget > ( ) ; TRI = ST -> getRegisterInfo ( ) ; TII = mf . getSubtarget ( )


<s> SDValue VecOnes = DAG . getConstant ( <NUM_LIT> , DL , InVT ) ; Operands [ <NUM_LIT> ] = DAG . getNode ( <STR_LIT> , DL , InVT , Operands [ <NUM_LIT> ] , VecOnes ) ; Operands [ <NUM_LIT> ] = DAG . getNode ( <STR_LIT> , DL , VT , Operands [ <NUM_LIT> ] ) ; return DAG . getNode ( <STR_LIT> , DL , VT , Operands [ <NUM_LIT> ] . getOperand ( <NUM_LIT> ) , Operands [ <NUM_LIT> ] ) ; } if ( Operands [ <NUM_LIT> ] . getOpcode ( ) == <STR_LIT> ) std :: swap ( Operands [ <NUM_LIT> ] , Operands [ <NUM_LIT> ] ) ; else if ( Operands [ <NUM_LIT> ] . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; Operands [ <NUM_LIT> ] = Operands [ <NUM_LIT> ] . getOperand ( <NUM_LIT> ) ; Operands [ <NUM_LIT> ] = Operands [ <NUM_LIT> ] . getOperand ( <NUM_LIT> ) ; for ( int i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) { if ( ! IsConstVectorInRange ( Operands [ i ] , <NUM_LIT> , <NUM_LIT> ) ) continue ; std :: swap ( Operands [ i ] , Operands [ <NUM_LIT> ] ) ; for ( int j = <NUM_LIT> ; j < <NUM_LIT> ; ++ j ) if ( Operands [ j ] . getOpcode ( ) != <STR_LIT> || Operands [ j ] . getOperand ( <NUM_LIT> ) . getValueType ( ) != VT ) return SDValue ( ) ; return DAG . getNode ( <STR_LIT> , DL , VT , Operands [ <NUM_LIT> ] . getOperand ( <NUM_LIT> ) , Operands [ <NUM_LIT>


<s> case <STR_LIT> : case <STR_LIT> : { KnownBits LHSKnown = DAG . computeKnownBits ( Op . getOperand ( <NUM_LIT> ) , Depth + <NUM_LIT> ) ; KnownBits RHSKnown = DAG . computeKnownBits ( Op . getOperand ( <NUM_LIT> ) , Depth + <NUM_LIT> ) ; unsigned TrailZ = LHSKnown . countMinTrailingZeros ( ) + RHSKnown . countMinTrailingZeros ( ) ; Known . Zero . setLowBits ( std :: min ( TrailZ , <NUM_LIT> ) ) ; unsigned LHSValBits = <NUM_LIT> - std :: max ( LHSKnown . countMinSignBits ( ) , <NUM_LIT> ) ; unsigned RHSValBits = <NUM_LIT> - std :: max ( RHSKnown . countMinSignBits ( ) , <NUM_LIT> ) ; unsigned MaxValBits = std :: min ( LHSValBits + RHSValBits , <NUM_LIT> ) ; if ( MaxValBits >= <NUM_LIT> ) break ; bool Negative = false ; if ( Opc == <STR_LIT> ) { bool LHSNegative = ! ! ( LHSKnown . One & ( <NUM_LIT> << <NUM_LIT> ) ) ; bool LHSPositive = ! ! ( LHSKnown . Zero & ( <NUM_LIT> << <NUM_LIT> ) ) ; bool RHSNegative = ! ! ( RHSKnown . One & ( <NUM_LIT> << <NUM_LIT> ) ) ; bool RHSPositive = ! ! ( RHSKnown . Zero & ( <NUM_LIT> << <NUM_LIT> ) ) ; if ( ( ! LHSNegative && ! LHSPositive ) || ( ! RHSNegative && ! RHSPositive ) ) break ; Negative = ( LHSNegative && RHSPositive ) || ( LHSPositive && RHSNegative ) ; } if ( Negative ) Known . One . setHighBits ( <NUM_LIT> - MaxValBits ) ; else Known . Zero . setHighBits ( <NUM_LIT> - MaxValBits ) ; break ; } case <STR_LIT> : { ConstantSDNode * CMask = dyn_cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) ; if ( ! CMask ) return ; KnownBits LHSKnown = DAG . computeKnownBits ( Op . getOperand ( <NUM_LIT> ) , Depth + <NUM_LIT> ) ; KnownBits RHSKnown = DAG . computeKnownBits ( Op . getOperand ( <NUM_LIT> ) , Depth + <NUM_LIT> ) ; unsigned Sel = CMask -> getZExtValue ( ) ; for ( unsigned I = <NUM_LIT> ; I < <NUM_LIT> ; I += <NUM_LIT> ) { unsigned SelBits = Sel & <NUM_LIT> ; if ( SelBits < <NUM_LIT> ) { SelBits *=


<s> if ( Op . isReg ( ) ) { printRegName ( O , Op . getReg ( ) ) ; return ; } if ( Op . isImm ( ) ) { O << Op . getImm ( ) ; return ; } assert ( Op . isExpr ( )


<s> FastISel * <STR_LIT> ( FunctionLoweringInfo & FuncInfo , const TargetLibraryInfo * LibInfo ) { const <ISA_LIT>Subtarget & Subtarget = FuncInfo . MF -> getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( Subtarget . is64BitELFABI ( ) ) return

new <ISA_LIT>FastISel ( FuncInfo , LibInfo ) ;


<s> const MCInstrDesc & Desc = MII . get ( Opc ) ; if ( ( Desc . TSFlags & <STR_LIT> ) == <NUM_LIT> ) return true ; const <STR_LIT> * Info = <STR_LIT> ( Opc ) ; const <STR_LIT> * BaseOpcode = <STR_LIT> ( Info -> BaseOpcode ) ; if ( ! BaseOpcode -> MSAA ) return true ; int DimIdx = <STR_LIT> ( Opc , <STR_LIT> :: dim ) ; assert ( DimIdx != - <NUM_LIT> ) ; unsigned Dim = Inst . getOperand ( DimIdx )


<s> bool d16PreservesUnusedBits ( ) const { return hasD16LoadStore ( ) && ! TargetID .


<s> SMLoc S = Parser . getTok ( ) . getLoc ( ) ; const AsmToken & Tok = Parser . getTok ( ) ; if ( ! Tok . is ( AsmToken :: Identifier ) ) return MatchOperand_NoMatch ; StringRef Mask = Tok . getString ( ) ; if ( isMClass ( ) ) { std :: string Name = Mask . lower ( ) ; unsigned FlagsVal = StringSwitch < unsigned > ( Name ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Default ( ~ <NUM_LIT> ) ; if ( FlagsVal == ~ <NUM_LIT> ) return MatchOperand_NoMatch ; if ( ! hasThumb2DSP ( ) && ( FlagsVal & <NUM_LIT> ) ) return MatchOperand_NoMatch ; if ( ! hasV7Ops ( ) && FlagsVal >= <NUM_LIT> && FlagsVal <= <NUM_LIT> ) return MatchOperand_NoMatch ; Parser . Lex ( ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateMSRMask ( FlagsVal , S ) ) ; return


<s> } unsigned Rotate = ( DestIsHigh != SrcIsHigh ? <NUM_LIT> : <NUM_LIT> ) ; BuildMI ( MBB , MBBI , DL , get ( Opcode ) , DestReg ) . addReg ( DestReg , RegState :: Undef ) . addReg ( SrcReg , getKillRegState (

KillSrc ) ) . addImm ( <NUM_LIT> - Size ) . addImm ( <NUM_LIT> + <NUM_LIT> ) . addImm ( Rotate ) ;


<s> int FI = std :: numeric_limits < int > :: max ( ) ; if ( Arg . getOpcode ( ) == <STR_LIT> ) { unsigned VR = cast < RegisterSDNode > ( Arg . getOperand ( <NUM_LIT> ) ) -> getReg ( ) ; if ( ! Register :: isVirtualRegister ( VR ) ) return false ; MachineInstr * Def = MRI -> getVRegDef ( VR ) ; if ( ! Def ) return false ; if ( ! Flags . isByVal ( ) ) { if ( ! TII -> isLoadFromStackSlot ( * Def , FI ) ) return false ; } else { return false ; } } else if ( LoadSDNode * Ld = dyn_cast


<s> return StringSwitch < unsigned > ( RegName ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> )

. Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( <NUM_LIT> ) ;


<s> } else { Opcode = ( isU6 ) ? <STR_LIT> : <STR_LIT> ; } BuildMI ( MBB , MBBI , dl , TII . get ( Opcode ) ) . addImm ( FrameSize ) ; if ( emitFrameMoves ) { std :: vector < MachineMove > & Moves = MMI -> getFrameMoves ( ) ; MCSymbol * FrameLabel = MMI -> getContext ( ) . CreateTempSymbol ( ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) ) . addSym ( FrameLabel ) ; MachineLocation SPDst ( MachineLocation :: VirtualFP ) ; MachineLocation SPSrc ( MachineLocation :: VirtualFP , - FrameSize * <NUM_LIT> ) ; Moves . push_back ( MachineMove ( FrameLabel , SPDst , SPSrc ) ) ; if ( LRSavedOnEntry ) { MachineLocation CSDst ( MachineLocation :: VirtualFP , <NUM_LIT> ) ; MachineLocation CSSrc ( <STR_LIT> ) ; Moves . push_back ( MachineMove ( FrameLabel , CSDst , CSSrc ) ) ; } } if ( saveLR ) { int LRSpillOffset = MFI -> getObjectOffset ( XFI -> getLRSpillSlot ( ) ) ; storeToStack ( MBB , MBBI , <STR_LIT> , LRSpillOffset + FrameSize * <NUM_LIT> , dl , TII ) ; MBB . addLiveIn ( <STR_LIT> ) ; if ( emitFrameMoves ) { MCSymbol * SaveLRLabel = MMI -> getContext ( ) . CreateTempSymbol ( ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) ) . addSym ( SaveLRLabel ) ; MachineLocation CSDst ( MachineLocation :: VirtualFP , LRSpillOffset ) ; MachineLocation CSSrc ( <STR_LIT> ) ; MMI -> getFrameMoves ( ) . push_back ( MachineMove ( SaveLRLabel , CSDst , CSSrc ) ) ; } } } if ( FP ) { int FPSpillOffset = MFI -> getObjectOffset ( XFI -> getFPSpillSlot ( ) ) ; storeToStack ( MBB , MBBI , <STR_LIT> , FPSpillOffset + FrameSize * <NUM_LIT> , dl , TII ) ; MBB . addLiveIn ( <STR_LIT> ) ; if ( emitFrameMoves ) { MCSymbol * SaveR10Label = MMI -> getContext ( ) . CreateTempSymbol ( ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) ) . addSym ( SaveR10Label ) ; MachineLocation CSDst ( MachineLocation :: VirtualFP , FPSpillOffset ) ; MachineLocation CSSrc ( <STR_LIT>


<s> if ( I == MBB . end ( ) ) return <NUM_LIT> ; if ( ! isUncondBranchOpcode ( I -> getOpcode ( ) ) && ! isCondBranchOpcode ( I -> getOpcode ( ) ) ) return <NUM_LIT> ; I -> eraseFromParent ( ) ; I = MBB . end ( ) ; if ( I == MBB . begin ( ) ) return <NUM_LIT> ; -- I ; if ( ! isCondBranchOpcode ( I -> getOpcode ( ) ) ) return <NUM_LIT> ; I -> eraseFromParent


<s> loadRegFromStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned DestReg , int FI , const TargetRegisterClass * RC ) const { DebugLoc DL = DebugLoc :: getUnknownLoc ( ) ; if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; if ( RC == <STR_LIT> ) { MachineFunction & MF = * MBB . getParent ( ) ; <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; if ( AFI -> isThumbFunction ( ) ) BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) ; else AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addReg ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ) ; } else if ( RC == <STR_LIT> ) { AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) ) ; } else { assert ( RC == <STR_LIT> && <STR_LIT> ) ; AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) .


<s> FOREACH_FUNCTION_ARGS ( m_fntype , type , iter ) { if ( type == void_type_node || i >= m_nargs ) break ; if ( i >= m_base_arg && TREE_CODE ( type ) == ENUMERAL_TYPE && ! require_immediate_enum ( i - m_base_arg , type ) ) return false ; i +=


<s> bool addRegAssignmentOptimized ( ) override { llvm_unreachable (


<s> unsigned CPI = CPEMI -> getOperand ( <NUM_LIT> ) . getIndex ( ) ; std :: vector < CPEntry > & CPEs = CPEntries [ CPI ] ; for ( unsigned i = <NUM_LIT> , e = CPEs . size ( ) ; i != e ; ++ i ) { if ( CPEs [ i ] . CPEMI == CPEMI ) continue ; if ( CPEs [ i ] . CPEMI == NULL ) continue ; if ( isCPEntryInRange ( UserMI , UserOffset , CPEs [ i ] . CPEMI , U . getLongFormMaxDisp ( ) , U . NegOk ) ) { DEBUG ( dbgs ( ) << <STR_LIT> << CPI << <STR_LIT> << CPEs [ i ] . CPI << <STR_LIT> ) ; U . CPEMI = CPEs [


<s> MachineInstrBuilder MIB = BuildMI ( * MBB , MI , MI . getDebugLoc ( ) , get ( NewOpcode ) ) . add ( Dest ) . addReg ( <NUM_LIT> ) . addReg ( Src . getReg ( ) , getKillRegState ( Src . isKill ( ) ) , Src . getSubReg ( ) ) . addImm ( Start ) . addImm ( End + <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; if ( LV ) { unsigned NumOps = MI . getNumOperands ( ) ; for ( unsigned I = <NUM_LIT> ; I < NumOps ; ++ I ) { MachineOperand & Op = MI . getOperand ( I ) ; if ( Op . isReg ( ) && Op . isKill ( ) ) LV -> replaceKillInstruction ( Op . getReg ( ) , MI , * MIB ) ; } } if ( LIS ) LIS -> ReplaceMachineInstrInMaps


<s> printDisp ( MI , opNum + <STR_LIT> , O ) ; O << <STR_LIT>


<s> switch ( CC ) { case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> :


<s> if ( Subtarget . is<ISA_LIT>64 ( ) && Directive < <STR_LIT> ) Directive = <STR_LIT> ; assert ( Directive <= <STR_LIT> && <STR_LIT> ) ; if ( OutStreamer . hasRawTextSupport ( ) ) OutStreamer . EmitRawText ( <STR_LIT> + Twine ( CPUDirectives [ Directive ] ) ) ; const TargetLoweringObjectFileMachO & TLOFMacho = static_cast < const TargetLoweringObjectFileMachO & > ( getObjFileLowering ( ) ) ; OutStreamer . SwitchSection ( TLOFMacho . getTextCoalSection ( ) ) ; if ( TM . getRelocationModel ( ) == Reloc :: PIC_ ) { OutStreamer . SwitchSection ( OutContext . getMachOSection ( <STR_LIT> , <STR_LIT> , MCSectionMachO :: S_SYMBOL_STUBS | MCSectionMachO :: S_ATTR_PURE_INSTRUCTIONS , <NUM_LIT> , SectionKind :: getText ( ) ) ) ; } else if ( TM . getRelocationModel ( ) == Reloc :: DynamicNoPIC ) { OutStreamer . SwitchSection ( OutContext . getMachOSection ( <STR_LIT> , <STR_LIT> , MCSectionMachO :: S_SYMBOL_STUBS | MCSectionMachO :: S_ATTR_PURE_INSTRUCTIONS , <NUM_LIT> , SectionKind :: getText ( ) ) ) ; } OutStreamer . SwitchSection ( getObjFileLowering ( )


<s> bool isMemVZ32 ( ) const { return Kind == Memory && ( ! Mem . Size || Mem . Size == <NUM_LIT> ) &&

getMemIndexReg ( ) >= <STR_LIT> && getMemIndexReg ( ) <= <STR_LIT> ;


<s> return __builtin_ia32_vcvtph2qq128_mask ( __B , _mm_setzero_si128 ( )


<s> HOST_WIDE_INT multiple ; return ( constant_multiple_p ( offset , GET_MODE_SIZE ( mode ) , & multiple ) && IN_RANGE ( multiple


<s> void <ISA_LIT>PassConfig :: addPreEmitPass ( ) { <ISA_LIT>TargetMachine & TM = get<ISA_LIT>TargetMachine ( ) ; addPass ( create<ISA_LIT>DelaySlotFillerPass ( TM ) ) ; addPass ( create<ISA_LIT>HazardSchedule ( ) ) ; addPass ( create<ISA_LIT>LongBranchPass ( TM ) ) ; addPass ( create<ISA_LIT>ConstantIslandPass


<s> unsigned Rd = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; Rd |= fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ; unsigned Rn = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned Rm = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned align = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned size = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; if ( size == <NUM_LIT> && align == <NUM_LIT> ) return MCDisassembler :: Fail ; align *= ( <NUM_LIT> << size ) ; switch ( Inst . getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( ! Check ( S , DecodeDPairRegisterClass ( Inst , Rd , Address , Decoder ) ) ) return MCDisassembler :: Fail ; break ; default : if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , Rd , Address , Decoder ) ) ) return MCDisassembler :: Fail ; break ; } if ( Rm != <NUM_LIT> ) { if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rn , Address , Decoder ) ) ) return MCDisassembler :: Fail ; } if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rn , Address , Decoder ) ) ) return MCDisassembler :: Fail ; Inst . addOperand ( MCOperand :: CreateImm ( align ) ) ; if ( Rm != <NUM_LIT> && Rm != <NUM_LIT> && ! Check ( S , DecodeGPRRegisterClass

( Inst , Rm , Address , Decoder ) ) ) return MCDisassembler :: Fail ;


<s> static SDValue addIPMSequence ( const SDLoc & DL , SDValue Glue , SelectionDAG & DAG ) { SDValue IPM = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Glue ) ; SDValue SRL = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , IPM , DAG . getConstant ( <STR_LIT> , DL , <STR_LIT> ) ) ; SDValue ROTL = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , SRL , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; return ROTL


<s> if ( regno == SP_REGNUM ) return mode == Pmode || mode == ptr_mode ; if ( regno == FRAME_POINTER_REGNUM || regno == ARG_POINTER_REGNUM ) return mode == Pmode ; if ( GP_REGNUM_P ( regno ) ) { if ( vec_flags & VEC_ANY_SVE ) return false ; if ( known_le ( GET_MODE_SIZE ( mode ) , <NUM_LIT> ) ) return true ; if ( known_le ( GET_MODE_SIZE ( mode ) , <NUM_LIT> ) ) return ( regno & <NUM_LIT>


<s> static std :: unique_ptr < AMDGPUOperand > CreateToken ( StringRef Str , SMLoc Loc ) { auto Res = llvm :: make_unique < AMDGPUOperand > ( Token ) ; Res -> Tok . Data = Str . data ( ) ; Res -> Tok . Length = Str .


<s> MCAsmBackend * llvm :: create<ISA_LIT>beAsmBackend ( const Target & T , const MCSubtargetInfo & STI , const MCRegisterInfo & MRI


<s> SDValue getAddrNonPICSym64 ( NodeTy * N , const SDLoc & DL , EVT Ty , SelectionDAG & DAG ) const { assert ( ! ABI . IsCheriPureCap ( ) ) ; assert ( ! Ty . isFatPointer ( ) ) ; SDValue Hi = getTargetNode ( N , Ty , DAG , <STR_LIT> ) ; SDValue Lo = getTargetNode ( N , Ty , DAG , <STR_LIT> ) ; SDValue Highest = DAG . getNode ( <STR_LIT> , DL , Ty , getTargetNode ( N , Ty , DAG , <STR_LIT> ) ) ; SDValue Higher = getTargetNode ( N , Ty , DAG , <STR_LIT> ) ; SDValue HigherPart = DAG . getNode ( <STR_LIT> , DL , Ty , Highest , DAG . getNode ( <STR_LIT> , DL , Ty , Higher ) ) ; SDValue Cst = DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; SDValue Shift = DAG . getNode ( <STR_LIT> , DL , Ty , HigherPart , Cst ) ; SDValue Add = DAG . getNode ( <STR_LIT> , DL , Ty , Shift , DAG . getNode ( <STR_LIT> , DL , Ty , Hi ) ) ; SDValue Shift2 = DAG . getNode ( <STR_LIT> , DL , Ty , Add , Cst ) ; return DAG . getNode ( <STR_LIT> , DL , Ty , Shift2 , DAG . getNode ( <STR_LIT> , DL , Ty ,


<s> SET_PREV_INSN ( queue ) = insn ; queue = next_queue ; } in_bundle = false ; } else if ( GET_MODE ( insn ) == SImode ) in_bundle = true ; } else if ( NOTE_P ( insn ) && NOTE_KIND ( insn ) == NOTE_INSN_VAR_LOCATION ) { if ( in_bundle ) { rtx_insn * prev = PREV_INSN ( insn ) ; SET_PREV_INSN ( next ) = prev ; SET_NEXT_INSN ( prev ) = next ; SET_PREV_INSN ( insn ) = queue ; queue =


<s> return __builtin_mve_vrshrq_m_n_sv8hi ( __arm_vuninitializedq_s16 ( ) ,


<s> virtual const <ISA_LIT>Subtarget * getSubtargetImpl ( ) const { return & Subtarget


<s> bool isCompute ( CallingConv :: ID cc ) { return ! isShader ( cc ) || cc


<s> uint64_t Disp = ( ( Field << <NUM_LIT> ) & <NUM_LIT> ) | ( ( Field >> <NUM_LIT> ) & <NUM_LIT> ) ; assert ( Base < <NUM_LIT> && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: CreateReg ( Base == <NUM_LIT> ? <NUM_LIT> : Regs [ Base ] ) ) ; Inst . addOperand ( MCOperand :: CreateImm ( SignExtend64 <


<s> default : return false ; case TargetOpcode :: G_VAARG : return legalizeVaArg ( MI , MRI , MIRBuilder ) ; case TargetOpcode :: G_LOAD : case TargetOpcode :: G_STORE : return legalizeLoadStore ( MI , MRI , MIRBuilder , Observer ) ; case TargetOpcode :: G_SHL : case TargetOpcode :: G_ASHR : case TargetOpcode :: G_LSHR : return legalizeShlAshrLshr ( MI , MRI


<s> FunctionPass * llvm :: create<ISA_LIT>FlagsCopyLoweringPass ( ) { return new <ISA_LIT>FlagsCopyLoweringPass (


<s> if ( ! Addr || ! Addr -> isFI ( ) ) return <STR_LIT> ; assert ( ! MI . memoperands_empty ( ) && ( * MI . memoperands_begin ( ) ) -> getAddrSpace ( ) == <ISA_LIT>AS :: PRIVATE_ADDRESS ) ; FrameIndex = Addr -> getIndex ( ) ; return getNamedOperand ( MI , <STR_LIT> :: vdata


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) : LLVMTargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL ) , DL ( <STR_LIT> ) , Subtarget ( TT , CPU , FS ) , InstrInfo ( Subtarget ) , TLInfo ( * this ) , TSInfo ( * this ) , FrameLowering ( Subtarget ) , InstrItins ( & Subtarget . getInstrItineraryData ( ) ) { setMCUseCFI ( false ) ; initAsmInfo (


<s> static MCDisassembler * create<ISA_LIT>64Disassembler ( const Target & T , const

MCSubtargetInfo & STI , MCContext & Ctx ) {


<s> assert ( ( Divisor . isPowerOf2 ( ) || Divisor . isNegatedPowerOf2 ( ) ) && <STR_LIT> ) ; if ( ! Subtarget . hasCMov ( ) ) return SDValue ( ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( VT != <STR_LIT> && VT != <STR_LIT> && ! ( Subtarget . is64Bit ( ) && VT == <STR_LIT> ) ) return SDValue ( ) ; unsigned Lg2 = Divisor . countTrailingZeros ( ) ; if ( Lg2 == <NUM_LIT> ) return SDValue ( ) ; SDLoc DL ( N ) ; SDValue N0 = N -> getOperand ( <NUM_LIT> ) ; SDValue Zero = DAG . getConstant ( <NUM_LIT> , DL , VT ) ; APInt Lg2Mask = APInt :: getLowBitsSet ( VT . getSizeInBits ( ) , Lg2 ) ; SDValue Pow2MinusOne = DAG . getConstant ( Lg2Mask , DL , VT ) ; SDValue Cmp = DAG . getSetCC ( DL , <STR_LIT> , N0 , Zero , <STR_LIT> ) ; SDValue Add = DAG . getNode ( <STR_LIT> , DL , VT , N0 , Pow2MinusOne ) ; SDValue CMov = DAG . getNode ( <STR_LIT> , DL , VT , Cmp , Add , N0 ) ; Created . push_back ( Cmp . getNode ( ) ) ; Created . push_back ( Add .


<s> return __builtin_shuffle ( __a , __b , (

uint32x2_t ) { <NUM_LIT> , <NUM_LIT> } ) ;


<s> while ( InsertPos -> getOpcode ( ) == <STR_LIT> || InsertPos -> getOpcode ( ) == <STR_LIT> ) ++ InsertPos ; } else { InsertPos = Header -> getFirstTerminator ( ) ; while ( InsertPos != Header -> begin ( ) && <STR_LIT> ( * std :: prev ( InsertPos ) , MFI ) && std :: prev ( InsertPos ) -> getOpcode ( ) != <STR_LIT> && std :: prev ( InsertPos ) -> getOpcode ( ) != <STR_LIT> && std :: prev ( InsertPos ) -> getOpcode ( ) != <STR_LIT> ) -- InsertPos ; } assert ( InsertPos != Header -> end ( ) ) ; MachineInstr * Begin = BuildMI ( * Header , InsertPos , Header -> findDebugLoc ( InsertPos ) , TII . get ( <STR_LIT> ) ) . addImm ( int64_t ( <STR_LIT> :: Void ) ) ; InsertPos = MBB . begin ( ) ; while ( InsertPos != MBB . end ( ) && InsertPos -> getOpcode ( ) == <STR_LIT> && LoopTops [ & * InsertPos ] -> getParent (

) -> getNumber ( ) >= Header -> getNumber ( ) ) ++ InsertPos ;


<s>
<ISA_LIT>FunctionInfo
*
AFI
=
MF
.
getInfo
<
<ISA_LIT>FunctionInfo
>
(
)
;
unsigned
UnspilledCSGPR
=
<STR_LIT>
;
unsigned
UnspilledCSGPRPaired
=
<STR_LIT>
;
MachineFrameInfo
&
MFI
=
MF
.
getFrameInfo
(
)
;
const
MCPhysReg
*
CSRegs
=
RegInfo
->
getCalleeSavedRegs
(
&
MF
)
;
unsigned
BasePointerReg
=
RegInfo
->
hasBasePointer
(
MF
)
RegInfo
->
getBaseRegister
(
)
:
(
unsigned
)
<STR_LIT>
;
unsigned
SpillEstimate
=
SavedRegs
.
count
(
)
;
for
(
unsigned
i
=
<NUM_LIT>
;
CSRegs
[
i
]
;
++
i
)
{
unsigned
Reg
=
CSRegs
[
i
]
;
unsigned
PairedReg
=
CSRegs
[
i
^
<NUM_LIT>
]
;
if
(
Reg
==
BasePointerReg
)
SpillEstimate
++
;
if
(
produceCompactUnwindFrame
(
MF
)
&&
!
SavedRegs
.
test
(
PairedReg
)
)
SpillEstimate
++
;
}
SpillEstimate
+=
<NUM_LIT>
;
unsigned
StackEstimate
=
MFI
.
estimateStackSize
(
MF
)
+
<NUM_LIT>
*
SpillEstimate
;
if
(
hasFP
(
MF
)
||
windowsRequiresStackProbe
(
MF
,
StackEstimate
)
)
{
SavedRegs
.
set
(
<STR_LIT>
)
;
SavedRegs
.
set
(
<STR_LIT>
)
;
}
unsigned
ExtraCSSpill
=
<NUM_LIT>
;
for
(
unsigned
i
=
<NUM_LIT>
;
CSRegs
[
i
]
;
++
i
)
{
const
unsigned
Reg
=
CSRegs
[
i
]
;
if
(
Reg
==
BasePointerReg
)
SavedRegs
.
set
(
Reg
)
;
bool
RegUsed
=
SavedRegs
.
test
(
Reg
)
;
unsigned
PairedReg
=
CSRegs
[
i
^
<NUM_LIT>
]
;
if
(
!
RegUsed
)
{
if
(
<STR_LIT>
.
contains
(
Reg
)
&&
!
RegInfo
->
isReservedReg
(
MF
,
Reg
)
)
{
UnspilledCSGPR
=
Reg
;
UnspilledCSGPRPaired
=
PairedReg
;
}
continue
;
}
if
(
produceCompactUnwindFrame
(
MF
)
&&
!
SavedRegs
.
test
(
PairedReg
)
)
{
SavedRegs
.
set
(
PairedReg
)
;
if
(
<STR_LIT>
.
contains
(
PairedReg
)
&&
!
RegInfo
->
isReservedReg
(
MF
,
PairedReg
)
)
ExtraCSSpill
=
PairedReg
;
}
}
DEBUG
(
dbgs
(
)
<<
<STR_LIT>
;
for
(
unsigned
Reg
:
SavedRegs
.
set_bits
(
)
)
dbgs
(
)
<<
' '
<<
printReg
(
Reg
,
RegInfo
)
;
dbgs
(
)
<<


<s> if ( ! MigrateTrue && ! MigrateFalse ) return <NUM_LIT> ; if ( ! MigrateTrue && TrueMBB && TrueMBB -> pred_size ( ) > <NUM_LIT> ) MigrateTrue = true ; if ( ! MigrateFalse && FalseMBB && FalseMBB -> pred_size ( ) > <NUM_LIT> ) MigrateFalse = true ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; showImproveSimpleJumpintoIf ( HeadMBB , TrueMBB , FalseMBB , LandBlk , <NUM_LIT> ) ; ) ; const TargetRegisterClass * I32RC = TRI -> getCFGStructurizerRegClass ( <STR_LIT> ) ; if ( ! MigrateTrue || ! MigrateFalse ) { return <NUM_LIT> ; } int NumNewBlk = <NUM_LIT> ; bool LandBlkHasOtherPred = ( LandBlk -> pred_size ( ) > <NUM_LIT> ) ; MachineBasicBlock :: iterator I = insertInstrBefore ( LandBlk , <STR_LIT> ) ; if ( LandBlkHasOtherPred ) { report_fatal_error ( <STR_LIT> ) ; unsigned CmpResReg = HeadMBB -> getParent ( ) -> getRegInfo ( ) .


<s> void <ISA_LIT>InstPrinter :: printSrcMemOperand ( const MCInst * MI , unsigned OpNo , raw_ostream & O , const char * Modifier ) { const MCOperand & Base = MI -> getOperand ( OpNo ) ; const MCOperand & Disp = MI -> getOperand ( OpNo + <NUM_LIT> ) ; if ( ! Base . getReg ( ) ) O << '&' ; if ( Disp . isExpr ( ) ) O << * Disp . getExpr (