<s> bool NegA = N -> getOpcode ( ) != <STR_LIT> && invertIfNegative ( A ) ; bool NegB = invertIfNegative ( B ) ; bool NegC = N -> getOpcode ( ) != <STR_LIT> && invertIfNegative ( C ) ; bool NegMul = ( NegA != NegB ) ; unsigned NewOpcode ; if ( ! NegMul ) NewOpcode = ( ! NegC ) ? <STR_LIT> : <STR_LIT> ; else NewOpcode = ( ! NegC ) ? <STR_LIT> : <STR_LIT> ; if ( N -> getOpcode ( ) == <STR_LIT> ) { switch ( NewOpcode ) { case <STR_LIT> : NewOpcode = <STR_LIT> ; break ; case <STR_LIT> : NewOpcode = <STR_LIT> ; break ; case <STR_LIT> : NewOpcode = <STR_LIT> ; break ; case <STR_LIT> : NewOpcode = <STR_LIT> ; break ; } } else if ( N -> getOpcode ( ) == <STR_LIT> ) { switch ( NewOpcode ) { case <STR_LIT> : NewOpcode = <STR_LIT> ; break ; case <STR_LIT> : NewOpcode = <STR_LIT> ; break ; case <STR_LIT> : NewOpcode = <STR_LIT> ; break ; case <STR_LIT> : NewOpcode = <STR_LIT> ; break ; } } else if ( N -> getOpcode ( ) == <STR_LIT> ) { switch ( NewOpcode ) { case <STR_LIT> : NewOpcode = <STR_LIT> ; break ; case <STR_LIT> : NewOpcode = <STR_LIT> ; break ; case <STR_LIT> : NewOpcode = <STR_LIT> ; break ; case <STR_LIT> : NewOpcode =


<s> if ( ( ( mask2 == <NUM_LIT> || ( mask2 & ix86_isa_flags2 ) != <NUM_LIT> ) && ( mask == <NUM_LIT> || ( mask & ix86_isa_flags ) != <NUM_LIT> ) ) || ( ( mask & OPTION_MASK_ISA_MMX ) != <NUM_LIT> && TARGET_MMX_WITH_SSE ) || ( mask2 == OPTION_MASK_ISA2_AVXVNNI ) || ( mask2 == OPTION_MASK_ISA2_AVXIFMA ) || ( mask2 == ( OPTION_MASK_ISA2_AVXNECONVERT | OPTION_MASK_ISA2_AVX512BF16 ) ) || ( lang_hooks . builtin_function == lang_hooks . builtin_function_ext_scope ) ) { tree type = ix86_get_builtin_func_type ( tcode ) ; decl = add_builtin_function ( name , type , code , BUILT_IN_MD , NULL , NULL_TREE ) ; ix86_builtins [ ( int ) code ] = decl ; ix86_builtins_isa [ ( int ) code ] . set_and_not_built_p = false ; } else { deferred_isa_values |= mask ; deferred_isa_values2 |= mask2 ; ix86_builtins [ ( int ) code ] = NULL_TREE ; ix86_builtins_isa [ ( int ) code ] . tcode = tcode ; ix86_builtins_isa [ ( int ) code ] . name = name ; ix86_builtins_isa [ ( int ) code ] . const_p = false ; ix86_builtins_isa [ ( int ) code ] . pure_p = false ; ix86_builtins_isa [ ( int ) code ] . set_and_not_built_p


<s> MVT PtrVT = TLI . getPointerTy ( ) ; EVT IdxVT = EVT :: getEVT ( Idx -> getType ( ) , false ) ; if ( IdxVT . bitsLT ( PtrVT ) ) { IdxN = emitIntExt ( IdxVT . getSimpleVT ( ) , IdxN , PtrVT , false ) ; IdxNIsKill = true ; } else if ( IdxVT . bitsGT ( PtrVT ) ) llvm_unreachable


<s> const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; unsigned Value = CE -> getValue (


<s> else stmt_cost = ix86_cost -> add ; break ; case TRUNC_DIV_EXPR : case CEIL_DIV_EXPR : case FLOOR_DIV_EXPR : case ROUND_DIV_EXPR : case TRUNC_MOD_EXPR : case CEIL_MOD_EXPR : case FLOOR_MOD_EXPR : case RDIV_EXPR : case ROUND_MOD_EXPR : case EXACT_DIV_EXPR : stmt_cost = ix86_division_cost ( ix86_cost , mode ) ; break ; case RSHIFT_EXPR : case LSHIFT_EXPR : case LROTATE_EXPR : case RROTATE_EXPR : { tree op2 = gimple_assign_rhs2 ( stmt_info -> stmt ) ; stmt_cost = ix86_shift_rotate_cost ( ix86_cost , mode , TREE_CODE ( op2 ) == INTEGER_CST , cst_and_fits_in_hwi ( op2 ) ? int_cst_value ( op2 ) : - <NUM_LIT> , true , false , false , NULL , NULL ) ; } break ; case NOP_EXPR : if ( tree_nop_conversion_p ( TREE_TYPE ( gimple_assign_lhs ( stmt_info -> stmt ) ) , TREE_TYPE ( gimple_assign_rhs1 ( stmt_info -> stmt ) ) ) ) stmt_cost = <NUM_LIT> ; break ; case BIT_IOR_EXPR : case ABS_EXPR : case ABSU_EXPR : case MIN_EXPR : case MAX_EXPR : case BIT_XOR_EXPR : case BIT_AND_EXPR : case BIT_NOT_EXPR : if ( SSE_FLOAT_MODE_P ( mode ) && TARGET_SSE_MATH ) stmt_cost = ix86_cost -> sse_op ; else if ( VECTOR_MODE_P ( mode ) ) stmt_cost = ix86_vec_cost ( mode , ix86_cost -> sse_op ) ; else stmt_cost = ix86_cost -> add ; break ; default : break ; } } combined_fn cfn ; if ( ( kind == vector_stmt || kind == scalar_stmt ) && stmt_info && stmt_info -> stmt && ( cfn = gimple_call_combined_fn ( stmt_info -> stmt ) ) != CFN_LAST ) switch ( cfn ) { case CFN_FMA : stmt_cost = ix86_vec_cost ( mode , mode == SFmode ? ix86_cost -> fmass : ix86_cost -> fmasd ) ; break ; default : break ; } if ( ( kind == vec_construct || kind == vec_to_scalar ) && stmt_info && ( STMT_VINFO_TYPE ( stmt_info ) == load_vec_info_type || STMT_VINFO_TYPE ( stmt_info ) == store_vec_info_type ) && STMT_VINFO_MEMORY_ACCESS_TYPE ( stmt_info ) == VMAT_ELEMENTWISE && TREE_CODE ( DR_STEP ( STMT_VINFO_DATA_REF ( stmt_info ) ) ) != INTEGER_CST ) { stmt_cost = ix86_builtin_vectorization_cost ( kind , vectype , misalign ) ; stmt_cost *= ( TYPE_VECTOR_SUBPARTS ( vectype ) + <NUM_LIT> ) ; } if ( stmt_cost == - <NUM_LIT> ) stmt_cost = ix86_builtin_vectorization_cost ( kind , vectype , misalign ) ; if ( TARGET_BONNELL && kind == vector_stmt && vectype && GET_MODE_INNER ( TYPE_MODE ( vectype ) ) == DFmode ) stmt_cost *= <NUM_LIT> ; if ( where == vect_body && stmt_info && stmt_in_inner_loop_p ( stmt_info ) ) count *= <NUM_LIT> ; retval = ( unsigned ) ( count * stmt_cost ) ; if ( ( TARGET_SILVERMONT || TARGET_GOLDMONT || TARGET_GOLDMONT_PLUS || TARGET_TREMONT || TARGET_INTEL ) && stmt_info && stmt_info -> stmt ) { tree lhs_op = gimple_get_lhs ( stmt_info -> stmt ) ; if ( lhs_op && TREE_CODE ( TREE_TYPE ( lhs_op ) ) == INTEGER_TYPE ) retval = ( retval * <NUM_LIT> ) / <NUM_LIT> ; } cost [ where ] += retval ; return retval


<s> Value * <ISA_LIT>IREmitter :: visitVCLTZ ( const SDNode


<s>
const
TargetRegisterClass
*
RC
=
TRI
->
getMinimalPhysRegClass
(
S
->
Reg
)
;
int
FI
=
MFI
->
CreateFixedSpillStackObject
(
RC
->
getSize
(
)
,
S
->
Offset
)
;
MinOffset
=
std
::
min
(
MinOffset
,
S
->
Offset
)
;
CSI
.
push_back
(
CalleeSavedInfo
(
S
->
Reg
,
FI
)
)
;
SRegs
[
S
->
Reg
]
=
false
;
}
for
(
int
x
=
SRegs
.
find_first
(
)
;
x
>=
<NUM_LIT>
;
x
=
SRegs
.
find_next
(
x
)
)
{
unsigned
R
=
x
;
const
TargetRegisterClass
*
RC
=
TRI
->
getMinimalPhysRegClass
(
R
)
;
int
Off
=
MinOffset
RC
->
getSize
(
)
;
unsigned
Align
=
std
::
min
(
RC
->
getAlignment
(
)
,
getStackAlignment
(
)
)
;
assert
(
isPowerOf2_32
(
Align
)
)
;
Off
&=
Align
;
int
FI
=
MFI
->
CreateFixedSpillStackObject
(
RC
->
getSize
(
)
,
Off
)
;
MinOffset
=
std
::
min
(
MinOffset
,
Off
)
;
CSI
.
push_back
(
CalleeSavedInfo
(
R
,
FI
)
)
;
SRegs
[
R
]
=
false
;
}
DEBUG
(
{
dbgs
(
)
<<
<STR_LIT>
;
for
(
unsigned
i
=
<NUM_LIT>
,
n
=
CSI
.
size
(
)
;
i
<
n
;
++
i
)
{
int
FI
=
CSI
[
i
]
.
getFrameIdx
(
)
;
int
Off
=
MFI
->
getObjectOffset
(
FI
)
;
dbgs
(
)
<<
' '
<<
PrintReg
(
CSI
[
i
]
.
getReg
(
)
,
TRI
)
<<
<STR_LIT>
<<
FI
<<
<STR_LIT>
;
if
(
Off
>=
<NUM_LIT>
)
dbgs
(
)
<<
'+'
;
dbgs
(
)
<<
Off


<s> case CmpInst :: Predicate :: BAD_FCMP_PREDICATE : ExtraCost = <NUM_LIT> ; break ; default : break ; } } } static const CostTblEntry SLMCostTbl [ ] = { { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , } ; static const CostTblEntry AVX512BWCostTbl [ ] = { { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , } ; static const CostTblEntry AVX512CostTbl [ ] = { { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , } ; static const CostTblEntry AVX2CostTbl [ ] = { { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , } ; static const CostTblEntry AVX1CostTbl [ ] = { { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , } ; static const CostTblEntry SSE42CostTbl [ ] = { { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , } ; static const CostTblEntry SSE41CostTbl [ ] = { { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , } ; static const CostTblEntry SSE2CostTbl


<s> for ( rn = <NUM_LIT> ; rn < FIRST_PSEUDO_REGISTER ; rn ++ ) if ( class_contents [ rclass ] [ <NUM_LIT> ] & ( <NUM_LIT> << rn ) ) if ( ! m32c_hard_regno_mode_ok ( rn , to ) ) return false ; if ( to == QImode ) return ( class_contents [ rclass

] [ <NUM_LIT> ] & <NUM_LIT> ) == <NUM_LIT> ;


<s> return ( __m128i ) __builtin_ia32_pmovsdb128_mask ( ( __v4si ) __A , ( __v16qi )


<s> ConstantSDNode * CN = <NUM_LIT> ; if ( ( Addr . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) && ( CN = dyn_cast < ConstantSDNode > ( Addr . getOperand ( <NUM_LIT> ) ) ) && ( CN -> getSExtValue ( ) % <NUM_LIT> == <NUM_LIT> ) ) { Base = Addr . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ; Offset = CurDAG -> getTargetConstant ( CN -> getSExtValue ( ) , <STR_LIT> ) ; return


<s> setBooleanContents ( ZeroOrOneBooleanContent ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; if ( ! Subtarget . isXS1A ( ) ) { setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; } if ( Subtarget . isXS1A ( ) ) { setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; } setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setLoadExtAction ( <STR_LIT> , <STR_LIT> , Promote ) ; setLoadExtAction ( <STR_LIT> , <STR_LIT> , Promote ) ; setLoadExtAction ( <STR_LIT> , <STR_LIT> , Promote ) ; setLoadExtAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setLoadExtAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT>


<s> static bool isLegalMUBUFImmOffset ( const ConstantSDNode


<s> virtual MVT getScalarShiftAmountTy ( EVT LHSTy ) const { return


<s> reportParseError ( <STR_LIT> ) ; return false ; } AssemblerOptions . back ( ) -> setReorder ( ) ; getTargetStreamer ( ) .


<s> bool <ISA_LIT>PassConfig :: addPreISel ( ) { if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableGlobalMerge ) addPass ( createGlobalMergePass (


<s> LLVM_DEBUG ( { if ( ! CurrentPacketMIs . empty ( ) ) { dbgs ( ) << <STR_LIT> ; unsigned Idx =


<s> return ( CC == CallingConv :: Fast || CC == CallingConv :: GHC || CC == CallingConv :: <ISA_LIT>_RegCall || CC == CallingConv :: HiPE || CC == CallingConv :: HHVM || CC ==

CallingConv :: Tail || CC == CallingConv :: SwiftTail ) ;


<s> bool isScalarVecReg ( unsigned Reg ) { return ( isRegInClass ( Reg , & <STR_LIT> ) || isRegInClass ( Reg ,


<s> if ( priority != DEFAULT_INIT_PRIORITY ) { char buf [ <NUM_LIT> ] ; sprintf ( buf , <STR_LIT> , is_ctor ? <STR_LIT> : <STR_LIT> , priority ) ; s = get_section ( buf , SECTION_WRITE


<s> inline vector unsigned short vec_vadduhs ( vector unsigned short a1 , vector unsigned short


<s> if ( ! VCTPs . empty ( ) ) { dbgs ( ) << <STR_LIT> ; for ( auto * MI : VCTPs ) dbgs ( ) << <STR_LIT> << * MI ; } if ( ! FoundAllComponents ( ) ) dbgs ( ) << <STR_LIT> ; else if ( ! ( Start && Dec && End ) )


<s> for ( MachineBasicBlock :: iterator miE = BB -> end ( ) ; miI != miE ; ++ miI ) { const MachineInstr & mi = * miI ; if ( mi . readsRegister ( <STR_LIT> ) ) return false ; if ( mi . definesRegister ( <STR_LIT> ) ) break ; } if ( miI == BB -> end ( ) ) for ( const auto * SBB : BB -> successors ( ) ) if ( SBB -> isLiveIn ( <STR_LIT> ) ) return false ; SelectItr -> addRegisterKilled ( <STR_LIT> , TRI ) ; return


<s> unsigned rv = <NUM_LIT> ; if ( MO . isReg ( ) ) { rv = get<ISA_LIT>RegNumber ( MO . getReg ( ) ) ; } else if ( MO . isImm ( ) ) { rv = MO . getImm ( ) ; } else if ( MO . isGlobal ( ) || MO . isSymbol ( ) || MO . isCPI ( ) ) { DOUT ( llvm :: dbgs ( ) << MO << <STR_LIT> << MI << <STR_LIT> ; unsigned Reloc = <NUM_LIT> ; int Offset = <NUM_LIT> ; bool useGOT = false ; switch ( MI . getOpcode ( ) ) { case <STR_LIT> : Reloc = <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Reloc = <STR_LIT> ; break ; case <STR_LIT> : Reloc = <STR_LIT> ; break ; case


<s> bool <ISA_LIT>ALFWriter :: shouldSetCondFlags ( const MachineInstr & MI ) { const TargetRegisterInfo * TRI = MI . getParent ( ) -> getParent ( ) -> getSubtarget ( ) . getRegisterInfo ( ) ; bool setsStatusFlags = false


<s> return ( uint64x2_t ) __builtin_neon_vsubluv2si ( ( int32x2_t )


<s> EVT VT = Op . getValueType ( ) ; EVT HalfVT = VT . getHalfSizedIntegerVT ( * DAG . getContext ( ) ) ; SDValue one = DAG . getConstant ( <NUM_LIT> , HalfVT ) ; SDValue zero = DAG . getConstant ( <NUM_LIT> , HalfVT ) ; SDValue LHS = Op . getOperand ( <NUM_LIT> ) ; SDValue LHS_Lo = DAG . getNode ( <STR_LIT> , DL , HalfVT , LHS , zero ) ; SDValue LHS_Hi = DAG . getNode ( <STR_LIT> , DL , HalfVT , LHS , one ) ; SDValue RHS = Op . getOperand ( <NUM_LIT> ) ; SDValue RHS_Lo = DAG . getNode ( <STR_LIT> , DL , HalfVT , RHS , zero ) ; SDValue RHS_Hi = DAG . getNode ( <STR_LIT> , DL , HalfVT , RHS , one ) ; if ( VT == <STR_LIT> && DAG . MaskedValueIsZero ( RHS , APInt :: getHighBitsSet ( <NUM_LIT> , <NUM_LIT> ) ) && DAG . MaskedValueIsZero ( LHS , APInt :: getHighBitsSet ( <NUM_LIT> , <NUM_LIT> ) ) ) { SDValue Res = DAG . getNode ( <STR_LIT> , DL , DAG . getVTList ( HalfVT , HalfVT ) , LHS_Lo , RHS_Lo ) ; SDValue DIV = DAG . getNode ( <STR_LIT> , DL , VT , Res . getValue ( <NUM_LIT> ) , zero ) ; SDValue REM = DAG . getNode ( <STR_LIT> , DL , VT , Res . getValue ( <NUM_LIT> ) , zero ) ; Results . push_back ( DIV ) ; Results . push_back


<s> BB -> addSuccessor ( copy0MBB ) ; BB -> addSuccessor ( sinkMBB ) ; BuildMI ( BB , dl , TII -> get ( Opc2 ) ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; BuildMI ( BB , dl , TII -> get ( Opc1 ) ) . addMBB ( sinkMBB ) ; BB = copy0MBB ; BB -> addSuccessor ( sinkMBB ) ; BB = sinkMBB ; BuildMI ( * BB , BB -> begin ( ) , dl , TII -> get ( <STR_LIT> ) , MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addMBB (

thisMBB ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addMBB ( copy0MBB ) ;


<s> emitKernelArg ( DL , Int16Ty , Align ( <NUM_LIT> ) , <STR_LIT> , Offset , Args ) ; emitKernelArg ( DL , Int16Ty , Align ( <NUM_LIT> ) , <STR_LIT> , Offset , Args ) ; emitKernelArg ( DL , Int16Ty , Align ( <NUM_LIT> ) , <STR_LIT> , Offset , Args ) ; emitKernelArg ( DL , Int16Ty , Align ( <NUM_LIT> ) , <STR_LIT> , Offset , Args ) ; emitKernelArg ( DL , Int16Ty , Align ( <NUM_LIT> ) , <STR_LIT> , Offset , Args ) ; Offset += <NUM_LIT> ; Offset += <NUM_LIT> ; emitKernelArg ( DL , Int64Ty , Align ( <NUM_LIT> ) , <STR_LIT> , Offset , Args ) ; emitKernelArg ( DL , Int64Ty , Align ( <NUM_LIT> ) , <STR_LIT> , Offset , Args ) ; emitKernelArg ( DL , Int64Ty , Align ( <NUM_LIT> ) , <STR_LIT> , Offset , Args ) ; emitKernelArg ( DL , Int16Ty , Align ( <NUM_LIT> ) , <STR_LIT> , Offset , Args ) ; Offset += <NUM_LIT> ; auto Int8PtrTy = Type :: getInt8PtrTy ( Func . getContext ( ) , <ISA_LIT>AS :: GLOBAL_ADDRESS ) ; if ( M -> getNamedMetadata ( <STR_LIT> ) ) { emitKernelArg ( DL , Int8PtrTy , Align ( <NUM_LIT> ) , <STR_LIT> , Offset , Args ) ; } else Offset += <NUM_LIT> ; if ( ! Func . hasFnAttribute ( <STR_LIT> ) ) { emitKernelArg ( DL , Int8PtrTy , Align ( <NUM_LIT> ) , <STR_LIT> , Offset , Args ) ; } else Offset += <NUM_LIT>


<s> const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( Expr ) ; if ( ! CE || CE -> getValue ( ) < <NUM_LIT> || CE -> getValue ( ) > <NUM_LIT> ) { Error ( Loc , <STR_LIT> ) ; return MatchOperand_ParseFail ; } int Val = CE -> getValue ( ) ; if ( Parser . getTok ( ) . isNot ( AsmToken :: RCurly ) ) return MatchOperand_ParseFail ; SMLoc E = Parser . getTok (


<s> if ( ( TheTriple . getArch ( ) == Triple :: mips64el ) || ( TheTriple . getArch ( ) == Triple :: mips64 ) ) { CodePointerSize = CalleeSaveStackSlotSize = <NUM_LIT> ; } if ( ( TheTriple . getArch ( ) == Triple :: mipsel ) || ( TheTriple . getArch ( ) == Triple :: mips ) ) { PrivateGlobalPrefix = <STR_LIT> ; PrivateLabelPrefix = <STR_LIT> ; } AlignmentIsInBytes = false ; Data16bitsDirective = <STR_LIT> ; Data32bitsDirective = <STR_LIT> ; Data64bitsDirective = <STR_LIT> ; CommentString =


<s> unsigned NumElems = VT . getVectorNumElements ( ) ; EVT StVT = Mst -> getMemoryVT ( ) ; SDLoc dl ( Mst ) ; assert ( StVT != VT && <STR_LIT> ) ; unsigned FromSz = VT . getVectorElementType ( ) . getSizeInBits ( ) ; unsigned ToSz = StVT . getVectorElementType ( ) . getSizeInBits ( ) ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; if ( TLI . isTruncStoreLegal ( VT , StVT ) ) return SDValue ( ) ; assert ( isPowerOf2_32 ( NumElems * FromSz * ToSz ) && <STR_LIT> ) ; assert ( ( ( NumElems * FromSz ) % ToSz ) == <NUM_LIT> && <STR_LIT> ) ; unsigned SizeRatio = FromSz / ToSz ; assert ( SizeRatio * NumElems * ToSz == VT . getSizeInBits ( ) ) ; EVT WideVecVT = EVT :: getVectorVT ( * DAG . getContext ( ) , StVT . getScalarType ( ) , NumElems * SizeRatio ) ; assert ( WideVecVT . getSizeInBits ( ) == VT . getSizeInBits ( ) ) ; SDValue WideVec = DAG . getBitcast ( WideVecVT , Mst -> getValue ( ) ) ; SmallVector < int , <NUM_LIT> > ShuffleVec ( NumElems * SizeRatio , - <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i != NumElems ; ++ i ) ShuffleVec [ i ] = i * SizeRatio ; assert ( DAG . getTargetLoweringInfo ( ) . isTypeLegal ( WideVecVT ) && <STR_LIT> ) ; SDValue TruncatedVal = DAG . getVectorShuffle ( WideVecVT , dl , WideVec , DAG . getUNDEF ( WideVecVT ) , & ShuffleVec [ <NUM_LIT> ] ) ; SDValue NewMask ; SDValue Mask = Mst -> getMask ( ) ; if ( Mask . getValueType ( ) == VT ) { NewMask = DAG . getBitcast ( WideVecVT , Mask ) ; for ( unsigned i = <NUM_LIT> ; i != NumElems ; ++ i ) ShuffleVec [ i ] = i * SizeRatio ; for ( unsigned i = NumElems ; i != NumElems * SizeRatio ; ++ i ) ShuffleVec [ i ] = NumElems * SizeRatio ; NewMask = DAG . getVectorShuffle ( WideVecVT , dl , NewMask , DAG . getConstant ( <NUM_LIT> , dl , WideVecVT ) , & ShuffleVec [ <NUM_LIT> ] ) ; } else { assert ( Mask . getValueType ( ) . getVectorElementType ( ) == <STR_LIT> ) ; unsigned WidenNumElts = NumElems * SizeRatio ; unsigned MaskNumElts = VT . getVectorNumElements ( ) ; EVT NewMaskVT = EVT :: getVectorVT ( * DAG . getContext ( ) , <STR_LIT> , WidenNumElts ) ; unsigned NumConcat = WidenNumElts / MaskNumElts ; SmallVector < SDValue , <NUM_LIT> > Ops ( NumConcat ) ; SDValue ZeroVal = DAG . getConstant ( <NUM_LIT> , dl , Mask . getValueType ( ) ) ; Ops [ <NUM_LIT> ] = Mask ; for ( unsigned i = <NUM_LIT> ; i != NumConcat ; ++


<s> else if ( V1 . getValueSizeInBits ( ) < Width ) V1 = insertSubVector ( DAG . getUNDEF ( VT ) , V1 , <NUM_LIT> , DAG , SDLoc ( BV ) , Width ) ; unsigned NumElts = VT . getVectorNumElements ( ) ; APInt DemandedElts = APInt :: getAllOnesValue ( NumElts ) ; for ( unsigned i = <NUM_LIT> ; i != NumElts ; ++ i ) if ( BV -> getOperand ( i ) . isUndef ( ) ) DemandedElts . clearBit ( i ) ; unsigned HalfNumElts = NumElts / <NUM_LIT> ; if ( VT . is256BitVector ( ) && DemandedElts . lshr ( HalfNumElts ) == <NUM_LIT> ) { MVT HalfVT = <STR_LIT> ( VT . getScalarType ( ) , HalfNumElts ) ; V0 = extractSubVector ( V0 , <NUM_LIT> , DAG , SDLoc ( BV ) , <NUM_LIT> ) ; V1 = extractSubVector ( V1 , <NUM_LIT> , DAG , SDLoc ( BV ) , <NUM_LIT> ) ; SDValue Half = DAG . getNode ( HOpcode , SDLoc ( BV ) , HalfVT , V0 , V1 ) ; return insertSubVector ( DAG . getUNDEF ( VT ) , Half , <NUM_LIT> , DAG , SDLoc ( BV ) , <NUM_LIT> ) ; } return DAG . getNode ( HOpcode , SDLoc ( BV ) , VT , V0


<s> MCInst Inst ; Inst . setOpcode ( <STR_LIT> ) ; addOpsFromMDNode ( cast < MDNode > ( Node -> getOperand ( i ) ) , Inst , MAI ) ; outputMCInst ( Inst ) ; } } for ( auto FI = M . begin ( ) , E = M . end ( ) ; FI != E ; ++ FI ) { const Function & F = * FI ; if ( F . isDeclaration ( ) ) continue ; Register FReg = MAI -> getFuncReg ( F . getGlobalIdentifier ( ) ) ; assert ( FReg . isValid ( ) ) ; if ( MDNode * Node = F . getMetadata ( <STR_LIT> ) ) outputExecutionModeFromMDNode ( FReg , Node , ExecutionMode


<s> bool <ISA_LIT>RegisterInfo :: trackLivenessAfterRegAlloc ( const MachineFunction & MF )


<s> int <ISA_LIT>InstrInfo :: getOpcodeForSide ( int Opcode , int Side ) const { DenseMap < unsigned * , std :: pair < unsigned , unsigned > > :: const_iterator I = Pseudo2ClusteredTable . find ( ( unsigned * ) Opcode ) ; if ( I == Pseudo2ClusteredTable . end ( ) ) return - <NUM_LIT> ; if ( Side == <NUM_LIT> ) return I -> second


<s> MCTargetStreamer * TS = OutStreamer -> getTargetStreamer ( ) ; assert ( TS && <STR_LIT> ) ; return static_cast < <ISA_LIT>TargetStreamer * > ( TS


<s> assert ( isEqual ( getLiveRegsBefore ( * NonDbgMI , * LIS ) , LRS ) ) ; RPTracker . reset ( * I , & LRS ) ; } for ( ; ; ) { I = RPTracker . getNext ( ) ; if ( Regions [ CurRegion ] . first == I || NonDbgMI == I ) { LiveIns [ CurRegion ] = RPTracker . getLiveRegs ( ) ; RPTracker . clearMaxPressure ( ) ; } if ( Regions [ CurRegion ] . second == I ) { Pressure [ CurRegion ] = RPTracker . moveMaxPressure ( ) ; if ( CurRegion -- == RegionIdx ) break ; } RPTracker . advanceToNext ( ) ; RPTracker . advanceBeforeNext ( ) ; } if ( OnlySucc ) { if ( I != MBB -> end ( ) ) { RPTracker . advanceToNext ( ) ; RPTracker . advance ( MBB -> end ( ) ) ; } RPTracker . reset ( * OnlySucc -> begin ( ) , &


<s> TargetRegistry :: RegisterMCDisassembler ( getThe<ISA_LIT>64Target


<s> unsigned Idx = <NUM_LIT> ; for ( Function :: const_arg_iterator I = F -> arg_begin ( ) , E = F -> arg_end ( ) ; I != E ; ++ I , ++ Idx ) { if ( Idx > <NUM_LIT> ) return false ; if ( F -> getAttributes ( ) . hasAttribute ( Idx , Attribute :: ByVal ) || F -> getAttributes ( ) . hasAttribute ( Idx , Attribute :: InReg ) || F -> getAttributes ( ) . hasAttribute ( Idx , Attribute :: StructRet ) || F -> getAttributes ( ) . hasAttribute ( Idx , Attribute :: Nest ) ) return false ; Type * ArgTy = I -> getType ( ) ; if ( ArgTy -> isStructTy ( ) || ArgTy -> isArrayTy ( ) || ArgTy -> isVectorTy ( ) ) return false ; EVT ArgVT = TLI . getValueType ( ArgTy ) ; if ( ! ArgVT . isSimple ( ) ) return false ; switch ( ArgVT . getSimpleVT ( ) . SimpleTy ) { case <STR_LIT> : case <STR_LIT> : break ; default : return false ; } } static const uint16_t GPR32ArgRegs [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; static const uint16_t GPR64ArgRegs [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; Idx = <NUM_LIT> ; const TargetRegisterClass * RC32 = TLI . getRegClassFor ( <STR_LIT> ) ; const TargetRegisterClass * RC64 = TLI . getRegClassFor ( <STR_LIT> ) ; for ( Function :: const_arg_iterator I = F -> arg_begin ( ) , E = F -> arg_end ( ) ; I != E ; ++ I , ++ Idx ) { if ( I -> use_empty ( ) ) continue ; bool is32Bit = TLI . getValueType ( I -> getType ( ) ) == <STR_LIT> ; const TargetRegisterClass * RC = is32Bit ? RC32 : RC64 ; unsigned SrcReg = is32Bit ? GPR32ArgRegs [ Idx ] : GPR64ArgRegs [ Idx ] ; unsigned DstReg = FuncInfo . MF -> addLiveIn ( SrcReg , RC ) ; unsigned ResultReg = createResultReg ( RC ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( TargetOpcode :: COPY ) , ResultReg ) . addReg ( DstReg , getKillRegState ( true ) ) ; UpdateValueMap ( I , ResultReg


<s> const <ISA_LIT>InstrInfo * getInstrInfo ( )


<s> static SDValue performMULCombine ( SDNode * N , SelectionDAG & DAG , const TargetLowering :: DAGCombinerInfo & DCI , const <ISA_LIT>SETargetLowering * TL ) { EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ) if ( ! VT . isVector ( ) ) return genConstMult ( N -> getOperand ( <NUM_LIT> ) , C -> getAPIntValue ( ) , SDLoc ( N ) , VT , TL -> getScalarShiftAmountTy ( DAG . getDataLayout ( ) , VT ) , DAG ) ; return SDValue ( N , <NUM_LIT>


<s> EVT EltVT = VT . getVectorElementType ( ) ; int EltBits = EltVT . getSizeInBits


<s> return ( __mmask8 ) __builtin_ia32_cmppd512_mask ( ( __v8df ) __X , ( __v8df )


<s> if ( sh_cfun_interrupt_handler_p ( ) && !


<s> gep_type_iterator GTI = gep_type_begin ( U ) ; for ( User :: const_op_iterator i = U -> op_begin ( ) + <NUM_LIT> , e = U -> op_end ( ) ; i != e ; ++ i , ++ GTI ) { const Value * Op = * i ; if ( StructType * STy = dyn_cast < StructType > ( * GTI ) ) { const StructLayout * SL = DL . getStructLayout ( STy ) ; unsigned Idx = cast < ConstantInt > ( Op ) -> getZExtValue ( ) ; TmpOffset += SL -> getElementOffset ( Idx ) ; } else { uint64_t S = DL . getTypeAllocSize ( GTI . getIndexedType ( ) ) ; for ( ; ; ) { if ( const ConstantInt * CI = dyn_cast < ConstantInt > ( Op ) ) { TmpOffset += CI -> getSExtValue ( ) * S ; break ; } if ( canFoldAddIntoGEP ( U , Op ) ) { ConstantInt * CI = cast < ConstantInt > ( cast < AddOperator > ( Op ) -> getOperand ( <NUM_LIT> ) ) ; TmpOffset += CI -> getSExtValue ( ) * S ; Op = cast < AddOperator > ( Op ) -> getOperand ( <NUM_LIT> ) ; continue ; } goto unsupported_gep ; } } } Addr . setOffset ( TmpOffset ) ; if ( ComputeAddress ( U -> getOperand ( <NUM_LIT> ) , Addr ) ) return true ; Addr = SavedAddr ; unsupported_gep : break ; } case Instruction :: Alloca : { const AllocaInst * AI = cast < AllocaInst > ( Obj ) ; DenseMap < const AllocaInst * , int > :: iterator SI = FuncInfo . StaticAllocaMap . find ( AI ) ; if ( SI != FuncInfo . StaticAllocaMap . end ( ) ) { Addr . setKind ( Address :: FrameIndexBase ) ; Addr . setFI ( SI -> second ) ; return true ; } break ; } } if ( ! Addr . isValid ( ) ) Addr . setReg ( getRegForValue ( Obj ) ) ; return Addr . isValid (


<s> bool GCNPassConfig :: addGlobalInstructionSelect ( ) { addPass ( new InstructionSelect ( ) ) ; addPass ( create<ISA_LIT>AddIMGInitPass ( ) ) ; return false


<s> SMLoc S = Parser . getTok ( ) . getLoc ( ) ; const AsmToken & Tok = Parser . getTok ( ) ; if ( ! Tok . is ( AsmToken :: Identifier ) ) return Error (


<s> InstructionSelector :: ComplexRendererFns <ISA_LIT>InstructionSelector :: selectAddrModeXRO ( MachineOperand & Root , unsigned SizeInBytes ) const { MachineRegisterInfo & MRI = Root . getParent ( ) -> getMF ( ) -> getRegInfo ( ) ; if ( isBaseWithConstantOffset ( Root , MRI ) ) return None ; auto AddrModeFns = selectAddrModeShiftedExtendXReg ( Root , SizeInBytes ) ; if ( AddrModeFns ) return


<s> void decodeWaitcnt ( IsaVersion Version , unsigned Waitcnt , unsigned & Vmcnt , unsigned & Expcnt , unsigned & Lgkmcnt ) { Vmcnt = decodeVmcnt (


<s> if ( rclass == NO_REGS && TARGET_SHMEDIA && ( CONST_DOUBLE_P ( x ) || GET_CODE ( x ) == SYMBOL_REF || PIC_ADDR_P ( x ) ) ) return GENERAL_REGS ; return rclass


<s> Value * <ISA_LIT>IREmitter :: visitVSHL (


<s> ( * TUL ) [ <STR_LIT> ] = UnitsAndLanes ( CVI_XLANE , <NUM_LIT> ) ; ( * TUL ) [ <STR_LIT> ] = UnitsAndLanes ( CVI_XLANE , <NUM_LIT> ) ; ( * TUL ) [ <STR_LIT> ] = UnitsAndLanes ( CVI_SHIFT , <NUM_LIT> ) ; ( * TUL ) [ <STR_LIT> ] = UnitsAndLanes ( CVI_XLANE | CVI_SHIFT , <NUM_LIT> ) ; ( * TUL ) [ <STR_LIT> ] = ( CPU == <STR_LIT> ) ? UnitsAndLanes ( CVI_SHIFT , <NUM_LIT> ) : UnitsAndLanes ( CVI_XLANE | CVI_SHIFT | CVI_MPY0 | CVI_MPY1 , <NUM_LIT> ) ; ( * TUL ) [ <STR_LIT> ] = UnitsAndLanes ( CVI_XLANE | CVI_SHIFT | CVI_MPY0 | CVI_MPY1 , <NUM_LIT> ) ; ( * TUL ) [ <STR_LIT> ] = UnitsAndLanes ( CVI_NONE , <NUM_LIT> ) ; ( * TUL ) [ <STR_LIT> ] = UnitsAndLanes ( CVI_XLANE , <NUM_LIT> ) ; ( * TUL ) [ <STR_LIT> ] = UnitsAndLanes ( CVI_XLANE | CVI_SHIFT | CVI_MPY0 | CVI_MPY1 , <NUM_LIT> ) ; ( * TUL ) [ <STR_LIT> ] = UnitsAndLanes ( CVI_NONE ,


<s> MCOperand <ISA_LIT>Disassembler :: decodeOperand_AV_128 ( unsigned Val ) const { return decodeSrcOp ( OPW128


<s> void <ISA_LIT>InstructionSelector :: initM0 ( MachineInstr & I ) const { MachineBasicBlock * BB = I . getParent ( ) ; MachineFunction * MF = BB -> getParent ( ) ; MachineRegisterInfo & MRI = MF -> getRegInfo ( ) ; const LLT PtrTy = MRI . getType ( I . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; unsigned AS = PtrTy . getAddressSpace ( ) ; if ( ( AS == <ISA_LIT>AS :: LOCAL_ADDRESS || AS == <ISA_LIT>AS :: REGION_ADDRESS ) && STI


<s> static void WarnSize ( int Offset , MachineFunction & MF , DebugLoc & DL ) { if ( Offset <= - <NUM_LIT> ) { auto F = MF . getFunction ( ) ; DiagnosticInfoUnsupported DiagStackSize ( * F , <STR_LIT> <STR_LIT> , DL ) ; F -> getContext ( ) .


<s> SDValue R600TargetLowering :: LowerFPTOUINT ( SDValue Op , SelectionDAG & DAG ) const { SDLoc DL (


<s> bool isFPCloseToIncomingSP ( ) const


<s> const MachineOperand & IndexReg = MI -> getOperand ( Op + <NUM_LIT> ) ; const MachineOperand & DispSpec = MI -> getOperand ( Op + <NUM_LIT> ) ; bool HasBaseReg = BaseReg . getReg ( ) != <NUM_LIT> ; if ( HasBaseReg && Modifier && ! strcmp ( Modifier , <STR_LIT> ) && BaseReg . getReg ( ) == <STR_LIT> ) HasBaseReg = false ; bool HasParenPart = IndexReg . getReg ( ) || HasBaseReg ; if ( DispSpec . isImm ( ) ) { int DispVal = DispSpec . getImm ( ) ; if ( DispVal || ! HasParenPart ) O << DispVal ; } else { assert ( DispSpec . isGlobal ( ) || DispSpec . isCPI ( ) || DispSpec . isJTI ( ) || DispSpec . isSymbol ( ) ) ; printSymbolOperand ( MI -> getOperand ( Op + <NUM_LIT> ) , O ) ; } if ( Modifier && strcmp ( Modifier , <STR_LIT> ) == <NUM_LIT> ) O << <STR_LIT> ; if ( HasParenPart ) { assert ( IndexReg . getReg ( ) != <STR_LIT> && <STR_LIT> ) ; O << '(' ; if ( HasBaseReg ) printOperand ( MI , Op , O , Modifier ) ; if ( IndexReg . getReg ( ) ) { O << ',' ; printOperand ( MI , Op + <NUM_LIT> , O , Modifier ) ; unsigned ScaleVal = MI -> getOperand ( Op + <NUM_LIT> ) . getImm ( ) ; if ( ScaleVal != <NUM_LIT> ) O << ',' << ScaleVal ; } O <<


<s> void relaxInstruction ( MCInst const & , MCInst & ) const override { llvm_unreachable ( <STR_LIT>


<s> rtx u = XEXP ( * x , i ) ; if ( GET_CODE ( u ) == ZERO_EXTEND ) u = XEXP ( u , <NUM_LIT> ) ; if ( GET_CODE ( u ) == UNSPEC && XINT ( u , <NUM_LIT> ) == UNSPEC_TP ) { addr_space_t as = DEFAULT_TLS_SEG_REG ; * x = XEXP ( * x , <NUM_LIT> - i ) ; * loc = replace_equiv_address_nv ( * loc , addr , true ) ; set_mem_addr_space ( * loc , as ) ; return ; } } x = & XEXP ( * x ,


<s> return [ = ] ( const LegalityQuery & Query ) { const LLT Ty = Query . Types [ TypeIdx ] ; const LLT EltTy = Ty . getScalarType ( ) ; return EltTy . getSizeInBits ( ) == <NUM_LIT> && Ty . getNumElements (


<s> if ( VT == <STR_LIT> && Subtarget . hasAVX512 ( ) && ! Subtarget . hasBWI ( ) ) return <NUM_LIT> ; return TargetLowering :: getNumRegistersForCallingConv (


<s> while ( I != MBB . begin ( ) ) { -- I ; if ( I -> isDebugValue ( ) ) continue ; if ( I -> getOpcode ( ) != <STR_LIT> && I -> getOpcode ( ) != <STR_LIT> && I -> getOpcode ( ) != <STR_LIT> ) break ; I -> eraseFromParent ( ) ; I = MBB . end


<s> expand_set_cint64 ( op0 , op1 ) ; } else { rtx temp = create_temp_reg_if_possible ( Pmode , op0 ) ; if ( TARGET_32BIT ) { emit_insn ( gen_mov_address_32bit_step1 ( temp , op1 ) ) ; emit_insn ( gen_mov_address_32bit_step2 ( op0 ,


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) : LLVMTargetMachine ( T , <STR_LIT> , TT , CPU ,

FS , Options , getEffectiveRelocModel ( RM ) , CM , OL ) , TLOF ( make_unique < <ISA_LIT>TargetObjectFile > ( ) ) , Subtarget ( TT , CPU , FS , * this ) {


<s> if ( GVMap . empty ( ) ) { return false ; } for ( Module :: iterator I = M . begin ( ) , E = M . end ( ) ; I != E ; ++ I ) { if ( I -> isDeclaration ( ) ) { continue ; } IRBuilder < > Builder ( I -> getEntryBlock ( ) . getFirstNonPHIOrDbg ( ) ) ; for ( Function :: iterator BBI = I -> begin ( ) , BBE = I -> end ( ) ; BBI != BBE ; ++ BBI ) { for ( BasicBlock :: iterator II = BBI -> begin ( ) , IE = BBI -> end ( ) ; II != IE ; ++ II ) { for ( unsigned i = <NUM_LIT> , e = II -> getNumOperands ( ) ; i < e ; ++ i ) { Value * Operand = II -> getOperand ( i ) ; if ( isa < Constant > ( Operand ) ) { II -> setOperand ( i , remapConstant ( & M , I , cast < Constant > ( Operand ) , Builder ) ) ; } } } } ConstantToValueMap . clear ( ) ; } for ( Module :: named_metadata_iterator I = M . named_metadata_begin ( ) , E = M . named_metadata_end ( ) ; I != E ; I ++ ) { remapNamedMDNode ( & M , I ) ; } for ( GVMapTy :: iterator I = GVMap . begin ( ) , E = GVMap . end ( ) ; I != E ; ) { GlobalVariable * GV = I -> first ; GlobalVariable * NewGV = I -> second ; ++ I ; Constant * BitCastNewGV = ConstantExpr :: getBitCast ( NewGV , GV -> getType ( ) ) ; for ( Value :: use_iterator UI = GV -> use_begin ( ) , UE = GV -> use_end ( ) ; UI != UE ; ) { Use & U = ( UI ++ ) . getUse ( ) ; U . set ( BitCastNewGV ) ; } std :: string Name = GV -> getName ( ) ; GV -> removeDeadConstantUsers ( ) ; GV -> eraseFromParent ( ) ; NewGV -> setName ( Name ) ; } GVMap . clear ( ) ; return true


<s> if ( next_cum . words < MAX_ARGUMENT_SLOTS ) { int n = MAX_ARGUMENT_SLOTS - next_cum . words ; * pretend_size = n *


<s> else if ( Rs == Rt ) MI . setOpcode ( <STR_LIT> ) ; else { HasRs = true ; MI . setOpcode ( <STR_LIT> ) ; } if ( HasRs ) MI . addOperand ( MCOperand :: createReg ( getReg ( Decoder , <STR_LIT> , Rs ) ) ) ; MI . addOperand ( MCOperand :: createReg ( getReg ( Decoder , <STR_LIT>


<s> break ; default : break ; } if ( uses_spr ) { machine_mode mode = ( TARGET_POWERPC64 ) ? DImode : SImode ; op [ nopnds ++ ] = gen_rtx_CONST_INT ( mode , htm_spr_num ( fcode ) ) ; op [ nopnds ++ ] = gen_rtx_REG ( mode , htm_spr_regno ( fcode ) ) ; } else if ( attr & RS6000_BTC_CR ) { cr = gen_reg_rtx ( CCmode ) ; op [ nopnds ++ ] = cr ; } if ( flag_checking ) { int expected_nopnds = <NUM_LIT> ; if ( ( attr & RS6000_BTC_TYPE_MASK ) == RS6000_BTC_UNARY ) expected_nopnds = <NUM_LIT> ; else if ( ( attr & RS6000_BTC_TYPE_MASK ) == RS6000_BTC_BINARY ) expected_nopnds = <NUM_LIT> ; else if ( ( attr & RS6000_BTC_TYPE_MASK ) == RS6000_BTC_TERNARY ) expected_nopnds = <NUM_LIT> ; if ( ! ( attr & RS6000_BTC_VOID ) ) expected_nopnds += <NUM_LIT> ; if ( uses_spr ) expected_nopnds += <NUM_LIT> ; gcc_assert ( nopnds == expected_nopnds && nopnds <= MAX_HTM_OPERANDS ) ; } switch ( nopnds ) { case <NUM_LIT> : pat = GEN_FCN ( icode ) ( op [ <NUM_LIT> ] ) ; break ; case <NUM_LIT> : pat = GEN_FCN ( icode ) ( op [ <NUM_LIT> ] , op [ <NUM_LIT> ] ) ; break ; case <NUM_LIT> : pat = GEN_FCN ( icode ) ( op [ <NUM_LIT> ] , op [ <NUM_LIT> ] , op [ <NUM_LIT> ] ) ; break ; case <NUM_LIT> : pat = GEN_FCN ( icode ) ( op [ <NUM_LIT> ] , op [ <NUM_LIT> ] , op [ <NUM_LIT> ] , op [ <NUM_LIT> ] ) ; break ; default : gcc_unreachable ( ) ; } if ( ! pat ) return NULL_RTX ; emit_insn ( pat ) ; if ( attr & RS6000_BTC_CR ) { if ( fcode == HTM_BUILTIN_TBEGIN ) { rtx scratch = gen_reg_rtx ( SImode ) ; emit_insn ( gen_rtx_SET ( scratch , gen_rtx_EQ ( SImode , cr , const0_rtx ) ) ) ; emit_insn ( gen_rtx_SET ( target , gen_rtx_XOR ( SImode , scratch , GEN_INT ( <NUM_LIT> ) ) ) ) ; } else { rtx scratch1 = gen_reg_rtx ( SImode ) ; rtx scratch2 = gen_reg_rtx ( SImode ) ; rtx subreg = simplify_gen_subreg ( CCmode , scratch1 , SImode , <NUM_LIT> ) ; emit_insn ( gen_movcc ( subreg ,


<s> bool hasFlatScratchSTMode ( ) const { return hasFlatScratchInsts ( ) && hasGFX10_3Insts


<s> } TargetPassConfig :: addIRPasses ( ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None ) { addPass ( createInterleavedLoadCombinePass ( ) ) ; addPass ( createInterleavedAccessPass ( ) ) ; } if ( TM -> getOptLevel ( ) == CodeGenOpt :: Aggressive && EnableGEPOpt ) { addPass ( createSeparateConstOffsetFromGEPPass ( true ) ) ; addPass ( createEarlyCSEPass ( )


<s> return createMacroFusionDAGMutation (


<s> unsigned Reg = MF . addLiveIn ( VA . getLocReg ( ) , & <STR_LIT> ) ; SDValue Register = DAG . getCopyFromReg ( Chain , DL , Reg , VT ) ; InVals . push_back ( Register ) ; continue ; } PointerType * PtrTy = PointerType :: get ( VT . getTypeForEVT ( * DAG . getContext ( ) ) , <ISA_LIT>AS :: CONSTANT_BUFFER_0 ) ; <STR_LIT> Ext = <STR_LIT> ; if ( MemVT . getScalarSizeInBits ( ) != VT . getScalarSizeInBits ( ) ) { Ext = <STR_LIT> ; } unsigned ValBase = ArgLocs [ In . getOrigArgIndex ( ) ] . getLocMemOffset ( ) ; unsigned PartOffset = VA . getLocMemOffset ( ) ; unsigned Offset = <NUM_LIT> + VA . getLocMemOffset ( ) ; MachinePointerInfo PtrInfo ( UndefValue :: get ( PtrTy ) ,


<s> SDLoc dl ( Op ) ; assert ( ( ! N -> isCompressingStore ( ) || Subtarget . hasAVX512 ( ) ) && <STR_LIT> ) ; assert ( ( ! N -> isCompressingStore ( ) || ScalarVT . getSizeInBits ( ) >= <NUM_LIT> ) && <STR_LIT> ) ; if ( ! N -> isCompressingStore ( ) && VT . getVectorNumElements ( ) <= <NUM_LIT> ) return Op ; assert ( Subtarget . hasAVX512 ( ) && ! Subtarget . hasVLX ( ) && ! VT . is512BitVector ( ) && <STR_LIT> ) ; assert ( ( ScalarVT . getSizeInBits ( ) >= <NUM_LIT> || ( Subtarget . hasBWI ( ) && ( ScalarVT == <STR_LIT> || ScalarVT == <STR_LIT> ) ) ) && <STR_LIT> ) ; unsigned NumEltsInWideVec = <NUM_LIT> / VT . getScalarSizeInBits ( ) ; MVT WideDataVT = <STR_LIT> ( ScalarVT , NumEltsInWideVec ) ; MVT MaskEltTy = Mask . getSimpleValueType ( ) . getScalarType ( ) ; assert ( ( MaskEltTy == <STR_LIT> || VT . getVectorNumElements ( ) <= <NUM_LIT> ) && <STR_LIT> ) ; MVT WideMaskVT = <STR_LIT> ( MaskEltTy , NumEltsInWideVec ) ; DataToStore = ExtendToType ( DataToStore , WideDataVT , DAG ) ; Mask = ExtendToType ( Mask , WideMaskVT , DAG , true ) ; if ( MaskEltTy != <STR_LIT> ) Mask = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> ( <STR_LIT> , NumEltsInWideVec ) , Mask ) ; return DAG . getMaskedStore ( N -> getChain ( ) , dl , DataToStore , N -> getBasePtr ( ) , Mask , N -> getMemoryVT ( ) , N -> getMemOperand ( ) , N -> isTruncatingStore


<s> } if ( const <ISA_LIT>MCExpr * SymbolRefExpr = dyn_cast < <ISA_LIT>MCExpr > ( Imm . Value ) ) return SymbolRefExpr -> getKind ( ) == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_ABS_LO ; if ( const MCBinaryExpr * BinaryExpr = dyn_cast < MCBinaryExpr > ( Imm . Value ) ) if ( const <ISA_LIT>MCExpr * SymbolRefExpr = dyn_cast < <ISA_LIT>MCExpr > ( BinaryExpr -> getLHS ( ) ) ) return SymbolRefExpr -> getKind ( ) == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_ABS_LO ; return false


<s> ( IsF128 ? APFloat :: IEEEquad : APFloat :: IEEEsingle ) ; const unsigned SizeInBits = VT . getSizeInBits ( ) ; SmallVector < Constant * , <NUM_LIT> > CV ( VT == <STR_LIT> ? <NUM_LIT> : ( IsF128 ? <NUM_LIT> : <NUM_LIT> ) , ConstantFP :: get ( * Context , APFloat ( Sem , APInt ( SizeInBits , <NUM_LIT> ) ) ) ) ; CV [ <NUM_LIT> ] = ConstantFP :: get ( * Context , APFloat ( Sem , APInt :: getHighBitsSet ( SizeInBits , <NUM_LIT> ) ) ) ; Constant * C = ConstantVector :: get ( CV ) ; auto PtrVT = TLI . getPointerTy ( DAG . getDataLayout ( ) ) ; SDValue CPIdx = DAG . getConstantPool ( C , PtrVT , <NUM_LIT> ) ; MVT LogicVT = ( VT == <STR_LIT> ) ? <STR_LIT> : ( IsF128 ? <STR_LIT> : <STR_LIT> ) ; SDValue Mask1 = DAG . getLoad ( LogicVT , dl , DAG . getEntryNode ( ) , CPIdx , MachinePointerInfo :: getConstantPool ( DAG . getMachineFunction ( ) ) , <NUM_LIT> ) ; if ( ! IsF128 ) Op1 = DAG . getNode ( <STR_LIT> , dl , LogicVT , Op1 ) ; SDValue SignBit = DAG . getNode ( <STR_LIT> , dl , LogicVT , Op1 , Mask1 ) ; if ( ConstantFPSDNode * Op0CN = dyn_cast < ConstantFPSDNode > ( Op0 ) ) { APFloat APF = Op0CN -> getValueAPF ( ) ; if ( APF . isPosZero ( ) ) return IsF128 ? SignBit : DAG . getNode ( <STR_LIT> , dl , SrcVT , SignBit , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ; APF . clearSign ( ) ; CV [ <NUM_LIT> ] = ConstantFP :: get ( * Context , APF ) ; } else { CV [ <NUM_LIT> ] = ConstantFP :: get ( * Context , APFloat ( Sem , APInt :: getLowBitsSet ( SizeInBits , SizeInBits - <NUM_LIT> ) ) ) ; } C = ConstantVector :: get ( CV ) ; CPIdx = DAG . getConstantPool ( C , PtrVT , <NUM_LIT> ) ; SDValue Val = DAG . getLoad ( LogicVT , dl , DAG . getEntryNode ( ) , CPIdx , MachinePointerInfo :: getConstantPool ( DAG . getMachineFunction ( ) ) , <NUM_LIT> ) ; if ( ! isa < ConstantFPSDNode > ( Op0 ) ) { if ( ! IsF128 ) Op0 = DAG . getNode


<s> EmitProgramInfo<ISA_LIT> ( MF ) ; } DisasmLines . clear ( ) ; HexLines . clear ( ) ; DisasmLineMaxLen = <NUM_LIT> ; EmitFunctionBody ( ) ; if ( isVerbose ( ) ) { MCSectionELF * CommentSection = Context . getELFSection ( <STR_LIT> , ELF :: SHT_PROGBITS , <NUM_LIT> ) ; OutStreamer -> SwitchSection ( CommentSection ) ; if ( STM . getGeneration ( ) >= <ISA_LIT>Subtarget :: SOUTHERN_ISLANDS ) { OutStreamer -> emitRawComment ( <STR_LIT> , false ) ; OutStreamer -> emitRawComment ( <STR_LIT> + Twine ( KernelInfo . CodeLen ) , false ) ; OutStreamer -> emitRawComment ( <STR_LIT> + Twine ( KernelInfo . NumSGPR ) , false ) ; OutStreamer -> emitRawComment ( <STR_LIT> + Twine ( KernelInfo . NumVGPR ) , false ) ; OutStreamer -> emitRawComment ( <STR_LIT> + Twine ( KernelInfo . FloatMode ) , false ) ; OutStreamer -> emitRawComment ( <STR_LIT> + Twine ( KernelInfo . IEEEMode ) , false ) ; OutStreamer -> emitRawComment ( <STR_LIT> + Twine ( KernelInfo . ScratchSize ) , false ) ; OutStreamer -> emitRawComment ( <STR_LIT> + Twine ( KernelInfo . LDSSize ) + <STR_LIT> , false ) ; OutStreamer -> emitRawComment ( <STR_LIT> + Twine ( KernelInfo . SGPRBlocks ) , false ) ; OutStreamer -> emitRawComment ( <STR_LIT> + Twine ( KernelInfo . VGPRBlocks ) , false ) ; OutStreamer -> emitRawComment ( <STR_LIT> + Twine ( KernelInfo . NumSGPRsForWavesPerEU ) , false ) ; OutStreamer -> emitRawComment ( <STR_LIT> + Twine ( KernelInfo . NumVGPRsForWavesPerEU ) , false ) ; OutStreamer -> emitRawComment ( <STR_LIT> + Twine ( KernelInfo . ReservedVGPRFirst )


<s> <ISA_LIT>Subtarget :: <ISA_LIT>Subtarget ( const Triple & TT , const std :: string & CPU , const std :: string & FS , <ISA_LIT>TargetMachine & TM ) : <ISA_LIT>GenSubtargetInfo ( TT , CPU ,

FS ) , InstrInfo ( ) , FrameLowering ( ) , TLInfo ( TM ) , TSInfo ( ) , ELFArch ( false ) , m_FeatureSetDummy ( false ) {


<s> case <STR_LIT> : return LowerBR_CC ( Op , DAG ) ; case <STR_LIT> : return LowerSELECT_CC ( Op , DAG ) ; case <STR_LIT> : return LowerGlobalAddress ( Op , DAG ) ; case <STR_LIT> : return LowerExternalSymbol


<s> if ( ! isa < Instruction > ( V ) ) return true ; if ( generateSignBits ( V ) ) return false ; return ! isa < OverflowingBinaryOperator >


<s> { rtx operands [ <NUM_LIT> ] ; split_di ( & operand , <NUM_LIT> , operands , operands + <NUM_LIT> ) ; emit_insn ( gen_rtx_SET ( VOIDmode , gen_rtx_MEM ( SImode , gen_rtx_PRE_DEC ( Pmode , stack_pointer_rtx ) ) , operands [ <NUM_LIT> ] ) ) ; emit_insn ( gen_rtx_SET ( VOIDmode , gen_rtx_MEM ( SImode , gen_rtx_PRE_DEC ( Pmode , stack_pointer_rtx ) ) , operands [ <NUM_LIT> ] ) ) ; } break ; case HImode : operand = gen_lowpart ( SImode , operand ) ; case SImode


<s> copyPhysReg ( MBB , MBBI , DL , DstReg , SrcReg , KillSrc , MachineInstr :: NoFlags


<s> __inline__ static unsigned long long sh_media_MADD_L ( unsigned long long mm , unsigned long long mn ) { unsigned long long res ; __asm__ ( <STR_LIT> : <STR_LIT> ( res ) : <STR_LIT>


<s> FunctionPass * llvm :: createCleanupLocalDynamicTLSPass ( ) { return new LDTLSCleanup ( )


<s> case CPU_PPC7400 : case CPU_PPC8540 : case CPU_PPC8548 : case CPU_CELL : case CPU_PPCE300C2 : case CPU_PPCE300C3 : case CPU_PPCE500MC : case CPU_PPCE500MC64 : case CPU_PPCE5500 : case CPU_PPCE6500 : case CPU_TITAN : return <NUM_LIT> ; case CPU_PPC476 : case CPU_PPC604 : case CPU_PPC604E : case CPU_PPC620 : case CPU_PPC630 : return <NUM_LIT> ; case CPU_POWER4 : case CPU_POWER5 : case CPU_POWER6 : case CPU_POWER7 : return <NUM_LIT> ; case CPU_POWER8 : return <NUM_LIT> ; case CPU_POWER9 : return <NUM_LIT> ; default : return <NUM_LIT>


<s> Inst . addOperand ( MCOperand :: createImm ( ( Imm +


<s> MulCandidate ( Instruction * I , ValueList & lhs , ValueList & rhs


<s> bool <STR_LIT> ( ShuffleVectorSDNode * N , unsigned UnitSize , unsigned ShuffleKind , SelectionDAG & DAG ) { if ( DAG . getSubtarget ( ) . getDataLayout ( ) -> isLittleEndian ( ) ) { if ( ShuffleKind == <NUM_LIT> ) return isVMerge ( N , UnitSize , <NUM_LIT> , <NUM_LIT> ) ; else if ( ShuffleKind == <NUM_LIT> ) return isVMerge ( N , UnitSize , <NUM_LIT> , <NUM_LIT> ) ; else return false ; } else { if ( ShuffleKind == <NUM_LIT> ) return isVMerge ( N , UnitSize , <NUM_LIT> , <NUM_LIT> ) ; else if ( ShuffleKind == <NUM_LIT> ) return isVMerge ( N , UnitSize , <NUM_LIT> , <NUM_LIT> ) ; else return false


<s> SetupMachineFunction ( MF ) ; const Function & F = MF . getFunction ( ) ; const TargetMachine & TM = MF . getTarget ( ) ; for ( auto * GV : AFI -> getGlobalsPromotedToConstantPool ( ) ) PromotedGlobals . insert ( GV ) ; unsigned OptimizationGoal ; if ( F . hasFnAttribute ( Attribute :: OptimizeNone ) ) OptimizationGoal = <NUM_LIT> ; else if ( F . optForMinSize ( ) ) OptimizationGoal = <NUM_LIT> ; else if ( F . optForSize ( ) ) OptimizationGoal = <NUM_LIT> ; else if ( TM . getOptLevel ( ) == CodeGenOpt :: Aggressive ) OptimizationGoal = <NUM_LIT> ; else if ( TM . getOptLevel ( ) > CodeGenOpt :: None ) OptimizationGoal = <NUM_LIT> ; else OptimizationGoal =


<s> if ( ! NumVGScaledBytes ) return MCCFIInstruction :: createOffset ( nullptr , DwarfReg , NumBytes ) ; std :: string CommentBuffer ; llvm :: raw_string_ostream Comment ( CommentBuffer ) ; Comment << printReg ( Reg , & TRI ) << <STR_LIT> ; SmallString < <NUM_LIT> > OffsetExpr ; appendVGScaledOffsetExpr ( OffsetExpr , NumBytes , NumVGScaledBytes , TRI . getDwarfRegNum ( <STR_LIT> , true ) , Comment ) ; SmallString < <NUM_LIT> > CfaExpr ; CfaExpr . push_back ( dwarf :: DW_CFA_expression ) ; uint8_t buffer [


<s> const uint32_t * <ISA_LIT>RegisterInfo :: getCallPreservedMask ( const MachineFunction & MF , CallingConv :: ID CC ) const { const <ISA_LIT>Subtarget & Subtarget = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; bool HasSSE = Subtarget . hasSSE1 ( ) ; bool HasAVX = Subtarget . hasAVX ( ) ; bool HasAVX512 = Subtarget . hasAVX512 ( ) ; switch ( CC ) { case CallingConv :: GHC : case CallingConv :: HiPE : return CSR_NoRegs_RegMask ; case CallingConv :: AnyReg : if ( HasAVX ) return CSR_64_AllRegs_AVX_RegMask ; return CSR_64_AllRegs_RegMask ; case CallingConv :: PreserveMost : return CSR_64_RT_MostRegs_RegMask ; case CallingConv :: PreserveAll : if ( HasAVX ) return CSR_64_RT_AllRegs_AVX_RegMask ; return CSR_64_RT_AllRegs_RegMask ; case CallingConv :: CXX_FAST_TLS : if ( Is64Bit ) return CSR_64_TLS_Darwin_RegMask ; break ; case CallingConv :: Intel_OCL_BI : { if ( HasAVX512 && IsWin64 ) return CSR_Win64_Intel_OCL_BI_AVX512_RegMask ; if ( HasAVX512 && Is64Bit ) return CSR_64_Intel_OCL_BI_AVX512_RegMask ; if ( HasAVX && IsWin64 ) return CSR_Win64_Intel_OCL_BI_AVX_RegMask ; if ( HasAVX && Is64Bit ) return CSR_64_Intel_OCL_BI_AVX_RegMask ; if ( ! HasAVX && ! IsWin64 && Is64Bit ) return CSR_64_Intel_OCL_BI_RegMask ; break ; } case CallingConv :: HHVM : return CSR_64_HHVM_RegMask ; case CallingConv :: <ISA_LIT>_RegCall : if ( Is64Bit


<s> if ( fndecl == NULL_TREE ) { if ( old_tree != target_option_current_node ) ix86_reset_previous_fndecl ( ) ; return ; } ix86_set_func_type ( fndecl ) ; ix86_set_indirect_branch_type ( fndecl ) ; tree new_tree = DECL_FUNCTION_SPECIFIC_TARGET ( fndecl ) ; if ( new_tree == NULL_TREE ) new_tree = target_option_default_node ; if ( old_tree != new_tree ) { cl_target_option_restore ( & global_options , TREE_TARGET_OPTION ( new_tree ) ) ; if ( TREE_TARGET_GLOBALS ( new_tree ) ) restore_target_globals ( TREE_TARGET_GLOBALS ( new_tree ) ) ; else if ( new_tree == target_option_default_node ) restore_target_globals ( & default_target_globals ) ; else TREE_TARGET_GLOBALS ( new_tree ) = save_target_globals_default_opts ( ) ; } ix86_previous_fndecl = fndecl ; static bool prev_no_caller_saved_registers ; if ( TARGET_64BIT && ( call_used_regs [ SI_REG ] == ( cfun -> machine -> call_abi == MS_ABI ) ) ) reinit_regs ( ) ; else if ( prev_no_caller_saved_registers != cfun -> machine -> no_caller_saved_registers ) reinit_regs ( ) ; if ( cfun -> machine -> func_type != TYPE_NORMAL || cfun -> machine -> no_caller_saved_registers ) { const char * isa ; if ( TARGET_SSE ) isa = <STR_LIT> ; else if ( TARGET_MMX ) isa = <STR_LIT> ; else if ( TARGET_80387 ) isa = <STR_LIT> ; else isa = NULL ; if ( isa != NULL ) { if ( cfun -> machine -> func_type != TYPE_NORMAL ) sorry ( cfun -> machine -> func_type == TYPE_EXCEPTION ? G_ ( <STR_LIT> <STR_LIT> ) : G_ (


<s> return ( ( qword ) ( vec_cmpgt ( ( vec_uchar16 ) ( a ) , vec_splat ( ( vec_uchar16 ) ( si_from_uchar ( b ) ) , <NUM_LIT>


<s> Value * <ISA_LIT>IREmitter :: visitVMULLs ( const SDNode * N ) { llvm_unreachable ( <STR_LIT> ) ;


<s> rtx align_rtx = operands [ <NUM_LIT> ] ; int constp = GET_CODE ( bytes_rtx ) == CONST_INT ; HOST_WIDE_INT bytes = constp ? INTVAL ( bytes_rtx ) : <NUM_LIT> ; int align = INTVAL ( align_rtx ) ; int leftover ; rtx src_reg ; rtx dst_reg ; if ( constp && bytes <= <NUM_LIT> ) return <NUM_LIT> ; dst_reg = copy_addr_to_reg ( XEXP ( orig_dst , <NUM_LIT> ) ) ; src_reg = copy_addr_to_reg ( XEXP ( orig_src , <NUM_LIT> ) ) ; if ( align > UNITS_PER_WORD ) align = UNITS_PER_WORD ; if ( optimize_size || ! constp || align != UNITS_PER_WORD ) { block_move_call ( dst_reg , src_reg , bytes_rtx ) ; return <NUM_LIT> ; } leftover = bytes %


<s> void <ISA_LIT>HazardRecognizer :: Reset ( ) { LastMI =


<s> if ( ! isRegMaskId ( RA . Reg ) ) return ! isRegMaskId ( RB . Reg ) ? aliasRR ( RA , RB ) : aliasRM ( RA , RB ) ; return ! isRegMaskId ( RB . Reg ) ? aliasRM ( RB , RA ) : aliasMM (


<s> t = get_attr_type ( insn ) ; return is_fmac_op ( t ) || ( fmul_ok &&


<s> assert ( Kind == k_MatrixRegister && <STR_LIT>


<s> AluKind AK = getAluKind ( QSrc [ i ] ) ; AvailableAlus [ AK ] . push_back ( QSrc [


<s> const_rtx x = * iter ; if ( GET_CODE ( x ) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL ( x ) != <NUM_LIT> ) { if ( arm_disable_literal_pool ) sorry ( <STR_LIT> <STR_LIT> ) ; return true


<s> MIB . addReg ( MIB . getReg ( <NUM_LIT> ) , getUndefRegState ( MIB -> getOperand ( <NUM_LIT> ) . isUndef ( ) ) ) ; MIB . addImm ( ShiftAmt ) ; return true


<s> if ( RegNo > <NUM_LIT> ) return Fail ; unsigned Register = VectorDecoderTable


<s> return __builtin_loongson_pandn_uh ( s , t


<s> QDst . insert ( QDst . end ( ) , QSrc . begin ( ) , QSrc . end ( ) ) ; QSrc . clear ( )


<s> int unsignedp ; rtx entry_parm ; if ( type == NULL || type == error_mark_node ) return true ; if ( TYPE_MODE ( type ) == VOIDmode ) return false ; if ( TREE_CODE ( type ) == COMPLEX_TYPE ) return ( rs6000_parm_needs_stack ( args_so_far , TREE_TYPE ( type ) ) || rs6000_parm_needs_stack ( args_so_far , TREE_TYPE ( type ) ) ) ; if ( ( TREE_CODE ( type ) == UNION_TYPE || TREE_CODE ( type ) == RECORD_TYPE ) && TYPE_TRANSPARENT_AGGR ( type ) ) type = TREE_TYPE ( first_field ( type ) ) ; if ( pass_by_reference ( get_cumulative_args ( args_so_far ) , TYPE_MODE ( type ) , type , true ) ) type = build_pointer_type ( type ) ; unsignedp = TYPE_UNSIGNED ( type ) ; mode = promote_mode ( type , TYPE_MODE ( type ) , & unsignedp ) ; if ( rs6000_must_pass_in_stack ( mode , type ) ) return true ; entry_parm = rs6000_function_arg ( args_so_far , mode , type , true ) ; if ( entry_parm == NULL ) return true ; if ( GET_CODE ( entry_parm ) == PARALLEL && XEXP ( XVECEXP ( entry_parm , <NUM_LIT> , <NUM_LIT> ) , <NUM_LIT> ) == NULL_RTX ) return true ; if ( rs6000_arg_partial_bytes ( args_so_far , mode , type , true ) !=


<s> Index = AM . IndexReg ; if ( AM . GV ) Disp = CurDAG -> getTargetGlobalAddress ( AM . GV , DebugLoc ( ) , <STR_LIT> , AM . Disp , AM . SymbolFlags ) ; else if ( AM . CP ) Disp = CurDAG -> getTargetConstantPool ( AM . CP , <STR_LIT> , AM . Align , AM . Disp , AM . SymbolFlags ) ; else if ( AM . ES ) { assert ( ! AM . Disp && <STR_LIT> ) ; Disp = CurDAG -> getTargetExternalSymbol ( AM . ES , <STR_LIT> , AM . SymbolFlags ) ; } else if ( AM . JT != - <NUM_LIT> ) { assert ( ! AM . Disp && <STR_LIT> ) ; Disp = CurDAG -> getTargetJumpTable ( AM . JT , <STR_LIT> , AM . SymbolFlags ) ; } else if ( AM . BlockAddr ) Disp = CurDAG -> getTargetBlockAddress ( AM . BlockAddr , <STR_LIT> , AM .


<s> return ( ElemWidth == <NUM_LIT> && ST -> has16BitInsts ( ) ) ? <NUM_LIT>


<s> } int64_t ImmVal = ValAndVReg -> Value . getSExtValue ( ) ; if ( OffsetOpc == TargetOpcode :: G_MUL ) { if ( ! isPowerOf2_32 ( ImmVal ) ) return None ; ImmVal = Log2_32 ( ImmVal ) ; } if ( ( ImmVal & <NUM_LIT> ) != ImmVal ) return None ; if ( ImmVal != LegalShiftVal ) return None ; unsigned SignExtend = <NUM_LIT> ; if ( WantsExt ) { if ( ! LookedThroughZExt ) { MachineInstr * ExtInst = getDefIgnoringCopies ( OffsetReg , MRI ) ; auto Ext = getExtendTypeForInst ( * ExtInst , MRI , true ) ; if ( Ext == <STR_LIT> ) return None ; SignExtend = isSignExtendShiftType ( Ext ) ? <NUM_LIT> : <NUM_LIT> ; if ( SignExtend && Ext != <STR_LIT> ) return None ; OffsetReg = ExtInst -> getOperand ( <NUM_LIT> ) . getReg ( ) ; } MachineIRBuilder MIB ( * MRI . getVRegDef ( Root . getReg ( ) ) ) ; OffsetReg = moveScalarRegClass ( OffsetReg , <STR_LIT> , MIB ) ; } return { { [ = ] ( MachineInstrBuilder & MIB ) { MIB . addUse ( Base . getReg ( ) ) ; } , [ = ] ( MachineInstrBuilder & MIB ) { MIB . addUse ( OffsetReg ) ; } , [ = ]


<s> if ( ! isVreg1 ( DstReg ) ) continue ; if ( MRI -> use_empty ( DstReg ) ) { DeadCopies . push_back ( & MI ) ; continue ; } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << MI ) ; MRI -> setRegClass ( DstReg , IsWave32 ? & <STR_LIT> : & <STR_LIT> ) ; if ( MI . getOpcode ( ) == <STR_LIT> ) continue ; DebugLoc DL = MI . getDebugLoc ( ) ; Register SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; assert ( ! MI . getOperand ( <NUM_LIT> ) . getSubReg ( ) ) ; if ( ! Register :: isVirtualRegister ( SrcReg ) || ( ! isLaneMaskReg ( SrcReg ) && ! isVreg1 ( SrcReg ) ) ) { assert ( TII -> getRegisterInfo ( ) . getRegSizeInBits ( SrcReg , * MRI ) == <NUM_LIT> ) ; unsigned TmpReg = createLaneMaskReg ( * MF ) ; BuildMI ( MBB , MI , DL , TII -> get ( <STR_LIT> ) , TmpReg ) . addReg ( SrcReg ) . addImm ( <NUM_LIT> ) ; MI . getOperand ( <NUM_LIT> ) . setReg ( TmpReg ) ; SrcReg = TmpReg ; } MachineBasicBlock * PostDomBound = & MBB ; for ( MachineInstr & Use : MRI -> use_instructions ( DstReg ) ) { PostDomBound = PDT -> findNearestCommonDominator ( PostDomBound , Use . getParent ( ) ) ; } unsigned FoundLoopLevel = LF . findLoop ( PostDomBound ) ; if ( FoundLoopLevel ) { SSAUpdater . Initialize


<s> for ( const set_info * set : sets ) if ( set -> bb ( ) -> index ( ) == bb -> index ( ) ) return true ; return false


<s> default : return <NUM_LIT> ; case AsmToken :: Plus : case AsmToken :: Minus : case AsmToken :: Integer : if ( getParser ( ) . ParseExpression ( EVal ) ) return <NUM_LIT> ; int64_t ans ; EVal -> EvaluateAsAbsolute ( ans ) ; return <STR_LIT> ( EVal , S , E


<s> RegisterTargetMachine < <ISA_LIT>TargetMachine > X


<s> int Idx = <STR_LIT> ( MI . getOpcode ( ) , <STR_LIT> :: sbase ) ; if ( Idx == - <NUM_LIT> ) return false ; const auto RCID = MI . getDesc ( ) . OpInfo [ Idx ]


<s> const std :: vector < MachineJumpTableEntry > & JT = MJTI -> getJumpTables ( ) ; const std :: vector < MachineBasicBlock * > & JTBBs = JT [ JTI ] . MBBs ; bool ByteOffset = false , HalfWordOffset = false ; if ( MI -> getOpcode ( ) == <STR_LIT> ) ByteOffset = true ; else if ( MI -> getOpcode ( ) == <STR_LIT> ) HalfWordOffset = true ; for ( unsigned i = <NUM_LIT> , e = JTBBs . size ( ) ; i != e ; ++ i ) { MachineBasicBlock * MBB =


<s> int Next = Bits . find_next ( v2x ( Prev


<s> if ( MOI . isAtomic ( ) ) { if ( MOI . getOrdering ( ) == AtomicOrdering :: Acquire || MOI . getOrdering ( ) == AtomicOrdering :: Release || MOI . getOrdering ( ) == AtomicOrdering :: AcquireRelease || MOI . getOrdering ( ) == AtomicOrdering :: SequentiallyConsistent ) Changed |= CC -> insertWait ( MI , MOI . getScope ( ) , MOI . getOrderingAddrSpace ( ) , <STR_LIT> | <STR_LIT> , MOI . getIsCrossAddressSpaceOrdering ( ) , Position :: BEFORE ) ; if ( MOI . getOrdering ( ) == AtomicOrdering :: Acquire || MOI . getOrdering ( ) == AtomicOrdering :: AcquireRelease || MOI . getOrdering ( ) == AtomicOrdering :: SequentiallyConsistent ) Changed |= CC -> insertCacheInvalidate ( MI , MOI . getScope

( ) , MOI . getOrderingAddrSpace ( ) , Position :: BEFORE ) ;


<s> case CONST : x = XEXP ( x , <NUM_LIT> ) ; return ( ( GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == SYMBOL_REF || GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == LABEL_REF ) && GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == CONST_INT ) ; default : return <NUM_LIT>


<s> for ( int i = <NUM_LIT> ; i != NumElts ; ++ i ) { int MaskElt = SVOp -> getMaskElt ( i ) ; if ( MaskElt < <NUM_LIT> ) continue ; MaskElt %= LaneSize ; unsigned Shamt = i ; if ( NumElts == <NUM_LIT> )


<s> const MILOHContainer & getLOHContainer


<s> case <STR_LIT> : case <STR_LIT> : { unsigned BitWidth = Known . getBitWidth ( ) ; EVT VT = cast < MemIntrinsicSDNode > ( Op ) -> getMemoryVT ( ) ; unsigned MemBits = VT . getScalarSizeInBits ( ) ; Known . Zero |= APInt :: getHighBitsSet ( BitWidth , BitWidth - MemBits ) ; return ; } } break ; } case <STR_LIT> : case <STR_LIT> : { unsigned IntNo = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; switch ( IntNo ) { default : break ; case <STR_LIT> : case <STR_LIT> : { MVT VT = Op . getOperand ( <NUM_LIT> ) . getValueType ( ) . getSimpleVT ( ) ; unsigned BitWidth = Known . getBitWidth ( ) ; if ( VT == <STR_LIT> || VT == <STR_LIT> ) { assert ( BitWidth >= <NUM_LIT> && <STR_LIT> ) ; APInt Mask = APInt :: getHighBitsSet ( BitWidth , BitWidth - <NUM_LIT> ) ; Known . Zero |= Mask ; } else if ( VT == <STR_LIT> ||


<s> const MCInstrDesc & Desc = MII . get ( Opcode ) ; unsigned ConstantBusUseCount = <NUM_LIT> ; if ( Desc . TSFlags & ( <STR_LIT> | <STR_LIT> | <STR_LIT> | <STR_LIT> | <STR_LIT> | <STR_LIT> ) ) { if ( <STR_LIT> ( Opcode , <STR_LIT> :: imm ) != - <NUM_LIT> ) { ++ ConstantBusUseCount ; } unsigned SGPRUsed = findImplicitSGPRReadInVOP ( Inst ) ; if ( SGPRUsed != <STR_LIT> ) { ++ ConstantBusUseCount ; } const int Src0Idx = <STR_LIT> ( Opcode , <STR_LIT> :: src0 ) ; const int Src1Idx = <STR_LIT> ( Opcode


<s> void addVectorIndexHOperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: CreateImm ( getVectorIndex ( )


<s> for ( unsigned i = <NUM_LIT> ; i != e ; ++ i ) if ( ! isUndefOrEqual ( N -> getMaskElt ( i ) , i ) ) return false ; for ( unsigned i = <NUM_LIT> ; i != e ; ++ i ) if ( ! isUndefOrEqual ( N -> getMaskElt ( e + i ) ,


<s> static HOST_WIDE_INT get_jump_table_size ( rtx insn ) { if ( JUMP_TABLES_IN_TEXT_SECTION || <NUM_LIT> ) { rtx body = PATTERN ( insn ) ; int elt = GET_CODE ( body ) ==


<s> unsigned NumEltsPer128BitChunk = NumElts / Num128BitChunks ; unsigned NumEltsPer64BitChunk = NumEltsPer128BitChunk / <NUM_LIT> ; assert ( ( NumEltsPer128BitChunk % <NUM_LIT> == <NUM_LIT> ) && <STR_LIT> ) ; for ( unsigned j = <NUM_LIT> ; j != NumElts ; j += NumEltsPer128BitChunk ) { for ( unsigned i = <NUM_LIT> ; i != NumEltsPer128BitChunk ; ++ i ) { int LIdx = LMask [ i + j ] , RIdx = RMask [ i + j ] ; if ( LIdx < <NUM_LIT> || RIdx < <NUM_LIT> || ( ! A . getNode ( ) && ( LIdx < ( int ) NumElts || RIdx < ( int ) NumElts ) ) || ( ! B . getNode ( ) && ( LIdx >= ( int ) NumElts || RIdx >= ( int ) NumElts ) ) ) continue ; if ( ! ( ( RIdx & <NUM_LIT> ) == <NUM_LIT> && ( LIdx + <NUM_LIT> ) == RIdx ) && ! ( ( LIdx & <NUM_LIT> ) == <NUM_LIT> && ( RIdx + <NUM_LIT> ) == LIdx && IsCommutative ) ) return false ; int Base = LIdx & ~ <NUM_LIT> ; int Index = ( ( Base % NumEltsPer128BitChunk ) / <NUM_LIT> ) + ( ( Base % NumElts ) & ~ ( NumEltsPer128BitChunk - <NUM_LIT> ) ) ; if ( ( B && Base >= ( int ) NumElts ) || ( ! B && i >= NumEltsPer64BitChunk ) ) Index += NumEltsPer64BitChunk ; PostShuffleMask [ i + j ] = Index ; } } SDValue NewLHS = A . getNode ( ) ? A : B ; SDValue NewRHS = B . getNode ( ) ? B : A ; bool IsIdentityPostShuffle = isSequentialOrUndefInRange ( PostShuffleMask , <NUM_LIT> , NumElts , <NUM_LIT> ) ; if ( IsIdentityPostShuffle ) PostShuffleMask . clear ( ) ; if ( ! IsIdentityPostShuffle && ! Subtarget . hasAVX2 ( ) && VT . isFloatingPoint ( ) && isMultiLaneShuffleMask ( <NUM_LIT> , VT . getScalarSizeInBits ( ) , PostShuffleMask ) ) return false ; if ( ! shouldUseHorizontalOp ( NewLHS == NewRHS && ( NumShuffles < <NUM_LIT> || ! IsIdentityPostShuffle ) , DAG , Subtarget ) ) return false ; LHS = DAG . getBitcast ( VT , NewLHS


<s> void assignValueToAddress ( unsigned ValVReg , unsigned Addr , uint64_t Size , MachinePointerInfo & MPO , CCValAssign & VA ) override { auto MMO = MIRBuilder . getMF ( ) . getMachineMemOperand ( MPO , MachineMemOperand :: MOLoad | MachineMemOperand :: MOInvariant ,


<s> static unsigned CalculateStackSlotSize ( EVT ArgVT , <STR_LIT> Flags , unsigned PtrByteSize ) { unsigned ArgSize = ArgVT . getSizeInBits ( ) / <NUM_LIT> ; if ( Flags . isByVal ( ) ) ArgSize = Flags . getByValSize ( ) ; ArgSize = ( ( ArgSize + PtrByteSize - <NUM_LIT> ) / PtrByteSize ) * PtrByteSize ; return


<s> return __builtin_aarch64_lbtruncv2dfv2di (


<s> const TargetFrameLowering * TFI = getFrameLowering ( MF ) ; BitVector Reserved = this -> Reserved ; if ( TFI -> hasFP ( MF ) ) reserveAllSubregs ( & Reserved , getFrameRegister ( MF ) ) ; return Reserved


<s> int MinValue = getMinValue ( ) ; int MaxValue = getMaxValue ( ) ; const MCOperand & MO = getOperand ( ExtOpNum ) ; if ( MO . isExpr (


<s> unsigned <ISA_LIT>TargetLowering :: getFunctionAlignment ( const Function * F ) const { return F -> hasFnAttr ( Attribute :: OptimizeForSize )


<s> return StringSwitch < unsigned > ( Name . lower ( ) ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT>

) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( <NUM_LIT> ) ;


<s> unsigned NumElts = VT . getVectorNumElements ( ) ; unsigned NumLanes = VT . getSizeInBits ( ) / <NUM_LIT> ; if ( NumLanes == <NUM_LIT> ) NumLanes = <NUM_LIT> ; unsigned NumLaneElts = NumElts


<s> return ( int16x4_t ) __builtin_neon_vqnegv4hi


<s> const CapabilityList & getMinimalCapabilities ( ) const {


<s> const AsmToken & Tok = Parser . getTok ( ) ; if ( Tok . getString ( ) == <STR_LIT> ) { return parseSetReorderDirective ( ) ; } else if ( Tok . getString ( ) ==


<s> case MCSymbolRefExpr :: VK_None : break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GPREL : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_CALL : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOT : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_ABS_HI : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_ABS_LO : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_TLSGD : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOTTPREL : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_TPREL_HI : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_TPREL_LO : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GPOFF_HI : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GPOFF_LO : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_DISP : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_PAGE : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_OFST : OS << <STR_LIT> ; break ; } OS << SRE -> getSymbol ( ) ; if ( Offset ) { if ( Offset > <NUM_LIT> ) OS << '+' ; OS << Offset


<s> static void addOperands ( MachineInstrBuilder & MIB , ArrayRef < MachineOperand > MOs , int PtrOffset = <NUM_LIT> ) { unsigned NumAddrOps = MOs . size ( ) ; if ( NumAddrOps < <NUM_LIT> ) { for ( unsigned i = <NUM_LIT> ; i != NumAddrOps ; ++ i ) MIB . addOperand ( MOs [ i ] ) ; addOffset ( MIB , PtrOffset ) ; } else { assert ( MOs . size ( ) == <NUM_LIT> && <STR_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i != NumAddrOps ; ++ i ) { const MachineOperand & MO = MOs [ i ] ; if ( i == <NUM_LIT> && PtrOffset != <NUM_LIT> ) { assert ( ( MO . isImm ( ) || MO . isGlobal ( ) ) && <STR_LIT> ) ; if ( MO . isImm (


<s> void addRegOrImmOperands ( MCInst & Inst , unsigned N ) const { if ( isReg ( ) )


<s> bool isITCondCodeRestrictedFP ( ) const { if ( ! isITCondCode ( ) ) return false ; <STR_LIT> CC = getCondCode ( ) ; return CC == <STR_LIT> || CC == <STR_LIT> || CC == <STR_LIT> || CC == <STR_LIT> || CC


<s> auto SrcVT = TLI -> getValueType ( DL , Src ) ; TTI :: TargetCostKind CostKind = TTI :: TCK_RecipThroughput ; if ( ! VecLT . second . isVector ( ) || ! TLI -> isTypeLegal ( DstVT ) ) return Cost + getCastInstrCost ( Opcode , Dst , Src , TTI :: CastContextHint :: None , CostKind ) ; if ( DstVT . getFixedSizeInBits ( ) < SrcVT . getFixedSizeInBits ( ) ) return Cost + getCastInstrCost ( Opcode , Dst , Src , TTI :: CastContextHint :: None , CostKind ) ; switch ( Opcode ) { default : llvm_unreachable ( <STR_LIT> ) ; case Instruction :: SExt : return Cost ; case Instruction :: ZExt : if ( DstVT . getSizeInBits ( ) != <NUM_LIT> || SrcVT .

getSizeInBits ( ) == <NUM_LIT> ) return Cost ;


<s> case PROCESSOR_PENTIUM : case PROCESSOR_LAKEMONT : return <NUM_LIT> ; case PROCESSOR_PENTIUMPRO : case PROCESSOR_K6 : return <NUM_LIT> ; case PROCESSOR_BDVER1 : case PROCESSOR_BDVER2 : case PROCESSOR_BDVER3 : case PROCESSOR_BDVER4 : return <NUM_LIT> ; case PROCESSOR_CORE2 : case PROCESSOR_NEHALEM : case PROCESSOR_SANDYBRIDGE : case PROCESSOR_HASWELL : case PROCESSOR_BONNELL


<s> else assert ( <NUM_LIT> && <STR_LIT> ) ; MachineInstrBuilder MIB = BuildMI ( MF , DL , get ( Opc ) ) ; for ( unsigned i = <NUM_LIT> , e = Addr . size ( ) ; i != e ; ++ i )


<s> if ( DAG . getMachineFunction ( ) . getFunction ( ) . optForMinSize ( ) ) return false ; return true


<s> Reg = TRI -> getEncodingValue ( Reg ) / <NUM_LIT> ; unsigned StartBit = <STR_LIT> . getNumRegs ( ) ; if ( Reg + StartBit >= RegsUsed . size ( ) ) return <NUM_LIT> ; if ( Size > <NUM_LIT> ) Size /= <NUM_LIT> ; unsigned Mask = ( <NUM_LIT> << Size ) - <NUM_LIT> ; unsigned Used = <NUM_LIT> ; for ( unsigned I = <NUM_LIT> ; I < Size ; ++ I ) if ( RegsUsed . test ( StartBit + Reg + I ) ) Used |= <NUM_LIT> << I ; RegsUsed . set ( StartBit + Reg , StartBit + Reg + Size ) ; Mask &= ~ Used ; Mask <<= ( Bank == - <NUM_LIT> ) ? Reg % NUM_SGPR_BANKS : unsigned ( Bank - SGPR_BANK_OFFSET ) ; Mask = ( Mask | ( Mask >> NUM_SGPR_BANKS ) ) & SGPR_BANK_SHIFTED_MASK ; return Mask


<s> SDValue ArgVal = DAG . getNode ( <STR_LIT> , SL , IntVT , Extract ) ; ArgVal = DAG . getNode ( <STR_LIT> , SL , MemVT , ArgVal ) ; ArgVal = convertArgType ( DAG , VT , MemVT , SL , ArgVal , Signed , Arg ) ; return DAG . getMergeValues ( { ArgVal , Load . getValue ( <NUM_LIT> ) } , SL ) ; } SDValue Ptr = lowerKernArgParameterPtr ( DAG , SL , Chain , Offset ) ; SDValue Load = DAG . getLoad ( MemVT , SL , Chain , Ptr , PtrInfo , Alignment , MachineMemOperand :: MODereferenceable | MachineMemOperand :: MOInvariant ) ; SDValue Val = convertArgType ( DAG , VT , MemVT , SL


<s> unsigned HOST_WIDE_INT offset ; int extra ; rtx addr = XEXP ( op , <NUM_LIT> ) ; if ( TARGET_UPDATE && ( GET_CODE ( addr ) == PRE_INC || GET_CODE ( addr ) == PRE_DEC ) && mode_supports_pre_incdec_p ( mode ) && legitimate_indirect_address_p ( XEXP ( addr , <NUM_LIT> ) , false ) ) return true ; if ( address_is_prefixed ( addr , mode , NON_PREFIXED_DS ) ) return true ; if ( TARGET_MACHO && GET_CODE ( addr ) == LO_SUM ) return darwin_rs6000_legitimate_lo_sum_const_p ( XEXP


<s> RS . forward ( MachineBasicBlock :: iterator ( G -> getStart ( ) ) ) ; unsigned RegClassID = G -> getStart ( ) -> getDesc ( ) . OpInfo [ <NUM_LIT> ] . RegClass ; BitVector AvailableRegs = RS . getRegsAvailable ( TRI -> getRegClass ( RegClassID ) ) ; for ( MachineBasicBlock :: iterator I = G -> getStart ( ) , E = G -> getEnd ( ) ; I != E ; ++ I ) { RS . forward ( I ) ; AvailableRegs &= RS . getRegsAvailable ( TRI -> getRegClass ( RegClassID ) ) ; for ( auto J : I -> operands ( ) ) { if ( J . isRegMask ( ) ) AvailableRegs . clearBitsNotInMask ( J . getRegMask ( ) ) ; if ( J . isReg ( ) && J . isDef ( ) && AvailableRegs [ J .


<s> SDValue <ISA_LIT>TargetLowering :: LowerVAARG ( SDValue Op , SelectionDAG & DAG ) { assert ( Subtarget -> is64Bit ( ) && <STR_LIT> ) ; SDValue Chain = Op . getOperand ( <NUM_LIT> ) ; SDValue SrcPtr = Op . getOperand ( <NUM_LIT>


<s> assert ( m_pRelocator != NULL ) ; return m_pRelocator


<s> return ( ( RegNo >= <STR_LIT> && RegNo <= <STR_LIT> ) || ( RegNo >= <STR_LIT> &&

RegNo <= <STR_LIT> ) || ( RegNo >= <STR_LIT> && RegNo <= <STR_LIT> ) ) ;


<s> MachineInstr * <ISA_LIT>InstructionSelector :: emitADD ( Register DefReg , MachineOperand & LHS , MachineOperand & RHS , MachineIRBuilder & MIRBuilder ) const { const std :: array < std :: array < unsigned , <NUM_LIT> > , <NUM_LIT> > OpcTable { { { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , {


<s> std :: unique_ptr < PBQPRAConstraint > <ISA_LIT>Subtarget :: getCustomPBQPConstraints ( ) const { if ( ! isCortexA57 ( ) ) return nullptr ; return llvm :: make_unique < A57ChainingConstraint


<s> HasV5TEOps = false ; HasV6Ops = false ; HasV6MOps = false ; HasV6T2Ops = false ; HasV7Ops = false ; HasV8Ops = false ; HasVFPv2 = false ; HasVFPv3 = false ; HasVFPv4 = false ; HasFP<ISA_LIT>v8 = false ; HasNEON = false ; MinSize = false ; UseNEONForSinglePrecisionFP = false ; UseMulOps = UseFusedMulOps ; SlowFPVMLx = false ; HasVMLxForwarding = false ; SlowFPBrcc = false ; InThumbMode = false ; HasThumb2 = false ; No<ISA_LIT> = false ; PostRAScheduler = false ; IsR9Reserved = ReserveR9 ; UseMovt = false ; SupportsTailCall = false ; HasFP16 = false ; HasD16 = false ; HasHardwareDivide = false ; HasHardwareDivideIn<ISA_LIT> = false ; HasT2ExtractPack = false ; HasDataBarrier = false ; Pref32BitThumb = false ; AvoidCPSRPartialUpdate = false ; AvoidMOVsShifterOperand = false ; HasRAS = false ; HasMPExtension =


<s> case <STR_LIT> : case <STR_LIT> : cerr << <STR_LIT> ; abort ( ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : cerr << <STR_LIT> << <STR_LIT> ; abort ( ) ; case <STR_LIT> : if ( N . hasOneUse ( ) ) { SDValue Op0 = N . getOperand ( <NUM_LIT> ) ; switch ( Op0 . getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : Base = Op0 ; Index = Zero ; return true ; case <STR_LIT> : { GlobalAddressSDNode * GSDN = cast < GlobalAddressSDNode > ( Op0 ) ; GlobalValue * GV = GSDN -> getGlobal ( ) ; if ( GV -> getAlignment ( ) == <NUM_LIT> ) { Base = Op0 ; Index = Zero ; return true ; } break ; } } } break ; } return false


<s> if ( Rotation == <NUM_LIT> ) Rotation = CandidateRotation ; else if ( Rotation != CandidateRotation ) return SDValue ( ) ; SDValue MaskV = Mask [ l + i ] < NumElts ? V1 : V2 ; SDValue & TargetV = StartIdx < <NUM_LIT> ? Hi : Lo ; if ( ! TargetV ) TargetV = MaskV ; else if ( TargetV != MaskV ) return SDValue ( ) ; } } assert ( Rotation != <NUM_LIT> && <STR_LIT> ) ; assert ( ( Lo || Hi ) && <STR_LIT> ) ; if ( ! Lo ) Lo = Hi ; else if ( ! Hi ) Hi = Lo ; MVT ByteVT = <STR_LIT> ( <STR_LIT> , <NUM_LIT> * NumLanes ) ; Lo = DAG . getBitcast ( ByteVT , Lo ) ; Hi = DAG . getBitcast ( ByteVT , Hi ) ; int Scale = <NUM_LIT> / NumLaneElts ; if ( Subtarget . hasSSSE3 ( ) ) { assert ( ( ! VT . is512BitVector ( ) || Subtarget . hasBWI ( ) ) && <STR_LIT> ) ; return DAG . getBitcast ( VT , DAG . getNode ( <STR_LIT> , DL , ByteVT , Lo , Hi , DAG . getConstant ( Rotation * Scale , DL , <STR_LIT> ) ) ) ; } assert ( VT . is128BitVector ( ) && <STR_LIT> ) ; assert ( Mask . size ( )


<s> Iterator & down ( ) { Pos = DS . nextDown ( Pos )


<s> Insn = ( Bytes [ <NUM_LIT> ] << <NUM_LIT> ) | ( Bytes [ <NUM_LIT> ] << <NUM_LIT> ) | ( Bytes [ <NUM_LIT> ] <<

<NUM_LIT> ) | ( Bytes [ <NUM_LIT> ] << <NUM_LIT> ) ;


<s> MachineInstr & MI = * II ; MachineBasicBlock & MBB = * MI . getParent ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const <ISA_LIT>Subtarget & Subtarget = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; const TargetInstrInfo & TII = * Subtarget . getInstrInfo ( ) ; unsigned maxCallFrameSize = MFI . getMaxCallFrameSize ( ) ; DebugLoc dl = MI . getDebugLoc


<s> static MCInstrInfo * create<ISA_LIT>MCInstrInfo ( ) { MCInstrInfo * X = new MCInstrInfo ( ) ; Init<ISA_LIT>MCInstrInfo ( X )


<s> const MachineFunction & MF = DAG . getMachineFunction ( ) ; DiagnosticInfoUnsupported NoTrap ( * MF . getFunction ( ) , <STR_LIT> , Op . getDebugLoc ( ) , DS_Warning ) ; DAG . getContext ( ) -> diagnose ( NoTrap ) ; return DAG . getNode ( <STR_LIT> , SDLoc ( Op ) , <STR_LIT> ,


<s> if ( hasStackRealignment ( MF ) ) return true ; if ( MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . hasSVE ( ) ) { const <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; if ( ! AFI -> hasCalculatedStackSizeSVE ( ) || AFI -> getStackSizeSVE ( ) ) return true ; } return MFI . getLocalFrameSize


<s> assert ( VA . getValNo ( ) == NextVA . getValNo ( ) && <STR_LIT> ) ; assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; assert ( NextVA . isRegLoc ( ) && <STR_LIT> ) ; Register NewRegs [ ] = { MRI . createGenericVirtualRegister ( LLT :: scalar ( <NUM_LIT> ) ) , MRI . createGenericVirtualRegister ( LLT :: scalar ( <NUM_LIT> ) ) } ; assignValueToReg ( NewRegs [ <NUM_LIT> ] , VA . getLocReg (


<s> return decodeUImmOperand < <NUM_LIT> >


<s> bool <ISA_LIT>ShortenInst :: runOnMachineFunction ( MachineFunction & F ) { TII = static_cast < const <ISA_LIT>InstrInfo * > ( F . getTarget ( ) . getInstrInfo ( ) ) ; bool Changed =


<s> static rtx_code_label * ix86_expand_aligntest ( rtx variable , int value , bool epilogue ) { rtx_code_label * label = gen_label_rtx ( ) ; rtx tmpcount = gen_reg_rtx ( GET_MODE ( variable ) ) ; if ( GET_MODE ( variable ) == DImode ) emit_insn ( gen_anddi3 ( tmpcount , variable , GEN_INT ( value ) ) ) ; else emit_insn ( gen_andsi3 ( tmpcount , variable , GEN_INT ( value ) ) ) ; emit_cmp_and_jump_insns ( tmpcount , const0_rtx , EQ , <NUM_LIT> , GET_MODE ( variable ) , <NUM_LIT> , label ) ; if ( epilogue ) predict_jump ( REG_BR_PROB_BASE


<s> } if ( this -> get<ISA_LIT>TargetMachine ( ) . getSubtargetImpl ( ) -> fixFSMULD ( ) ) { addPass ( new FixFSMULD ( get<ISA_LIT>TargetMachine ( ) ) ) ; } if ( this -> get<ISA_LIT>TargetMachine ( ) . getSubtargetImpl


<s> void addLO32DSPAsmRegOperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> &&


<s> auto CmpMI = MIRBuilder . buildInstr ( Opc , { ZReg } , { LHS . getReg ( ) } ) ; if ( ImmFns ) { for ( auto & RenderFn : * ImmFns ) RenderFn ( CmpMI ) ; } else { CmpMI . addUse ( RHS . getReg ( ) ) ; } constrainSelectedInstRegOperands ( * CmpMI , TII


<s> if ( F -> hasFnAttribute ( <STR_LIT> ) || F -> hasFnAttribute ( <STR_LIT> ) ) { MachineFunction * MF = MMI -> getMachineFunction ( F ) ; assert ( MF ) ; <ISA_LIT>MachineFunctionInfo * PMFI = MF -> getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; PMFI -> setSinglePath ( ) ; NumSPTotal ++ ; W . push_back ( MF ) ; } } while ( ! W . empty ( ) ) { MachineFunction * MF = W . front ( ) ; W . pop_front (


<s> return isPowerOf2_32 ( LMUL ) && LMUL <= <NUM_LIT> && ( ! Fractional ||


<s> if ( ( CmpI -> getOpcode ( ) == <STR_LIT> || CmpI -> getOpcode ( ) == <STR_LIT> ) && ( OI -> getOpcode ( ) == <STR_LIT> || OI -> getOpcode ( ) == <STR_LIT> ) && ( ( OI -> getOperand ( <NUM_LIT> ) . getReg ( ) == SrcReg && OI -> getOperand ( <NUM_LIT> ) . getReg ( ) == SrcReg2 ) || ( OI -> getOperand ( <NUM_LIT> ) . getReg ( ) == SrcReg2 && OI -> getOperand

( <NUM_LIT> ) . getReg ( ) == SrcReg ) ) ) return true ;


<s> Target & llvm :: getThe<ISA_LIT>Target ( ) { static Target


<s> return new <ISA_LIT>PassConfig ( * this , PM


<s> switch ( VT . getSimpleVT ( ) . SimpleTy ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; } unsigned ResTyElts = ( NumVecs == <NUM_LIT> ) ? <NUM_LIT> : NumVecs ; if ( ! is64BitVector ) ResTyElts *= <NUM_LIT> ; EVT ResTy = EVT :: getVectorVT ( * CurDAG -> getContext ( ) , <STR_LIT> , ResTyElts ) ; std :: vector < EVT > ResTys ; ResTys . push_back ( ResTy ) ; if ( isUpdating ) ResTys . push_back ( <STR_LIT> ) ; ResTys . push_back ( <STR_LIT> ) ; SDValue Pred = getAL ( CurDAG , dl ) ; SDValue Reg0 = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; SDNode * VLdDup ; if ( is64BitVector || NumVecs == <NUM_LIT> ) { SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . push_back ( MemAddr ) ; Ops . push_back ( Align ) ; unsigned Opc = is64BitVector ? DOpcodes [ OpcodeIndex ] : QOpcodes0 [ OpcodeIndex ] ; if ( isUpdating ) { SDValue Inc = N -> getOperand ( <NUM_LIT> ) ; bool IsImmUpdate = isPerfectIncrement ( Inc , VT . getVectorElementType ( ) , NumVecs ) ; if ( NumVecs <= <NUM_LIT> && ! IsImmUpdate ) Opc = getVLDSTRegisterUpdateOpcode ( Opc ) ; if ( ! IsImmUpdate ) Ops . push_back ( Inc ) ; else if ( NumVecs > <NUM_LIT> ) Ops . push_back ( Reg0 ) ; } Ops . push_back ( Pred ) ; Ops . push_back ( Reg0 ) ; Ops . push_back ( Chain ) ; VLdDup = CurDAG -> getMachineNode ( Opc , dl , ResTys , Ops ) ; } else if ( NumVecs == <NUM_LIT> ) { const SDValue OpsA [ ] = { MemAddr , Align , Pred , Reg0 , Chain } ; SDNode * VLdA = CurDAG -> getMachineNode ( QOpcodes0 [ OpcodeIndex ] , dl , ResTys , OpsA ) ; Chain = SDValue ( VLdA , <NUM_LIT> ) ; const SDValue OpsB [ ] = { MemAddr , Align , Pred


<s> static MCAsmInfo * create<ISA_LIT>MCAsmInfo ( const Target & T , StringRef TT ) { MCAsmInfo * MAI = new <ISA_LIT>MCAsmInfo ( T , TT ) ; MachineLocation Dst ( MachineLocation :: VirtualFP ) ; MachineLocation Src ( <STR_LIT> , <NUM_LIT>


<s> SMLoc getEndLoc ( ) const override { return


<s> if ( MO . getReg ( ) == <NUM_LIT> ) return <NUM_LIT> ; return MO .


<s> if ( ! new_reg ) { new_reg = gen_reg_rtx ( GET_MODE ( and_base ) ) ; and_mask = XEXP ( and_op , <NUM_LIT> ) ; } rtx copy = gen_rtx_SET ( new_reg , and_base ) ; rtx_insn * new_insn = emit_insn_after ( copy , and_insn ) ; set_block_for_insn ( new_insn , BLOCK_FOR_INSN ( and_insn ) ) ; df_insn_rescan ( new_insn ) ; } XEXP ( mem , <NUM_LIT> ) = gen_rtx_AND ( GET_MODE ( new_reg ) , new_reg , and_mask ) ; SET_SRC ( body ) =


<s> bool GCNTTIImpl :: isSourceOfDivergence ( const Value * V ) const { if ( const Argument * A = dyn_cast < Argument > ( V ) ) return ! isArgPassedInSGPR ( A ) ; if ( const LoadInst * Load = dyn_cast < LoadInst > ( V ) ) return Load -> getPointerAddressSpace ( ) == ST -> get<ISA_LIT>AS ( ) . PRIVATE_ADDRESS ; if ( isa < AtomicRMWInst > ( V ) || isa < AtomicCmpXchgInst > ( V ) ) return true ; if ( const IntrinsicInst * Intrinsic = dyn_cast < IntrinsicInst > ( V ) ) return <STR_LIT> ( Intrinsic -> getIntrinsicID ( ) ) ; if ( isa < CallInst > ( V ) || isa < InvokeInst > (


<s> AM . Scale = <NUM_LIT> ; } } if ( TM . getCodeModel ( ) == CodeModel :: Small && Subtarget -> is64Bit ( ) && AM . Scale == <NUM_LIT> && AM . BaseType == <ISA_LIT>ISelAddressMode :: RegBase && AM . Base_Reg . getNode ( ) == <NUM_LIT> && AM . IndexReg . getNode ( ) == <NUM_LIT> && AM . SymbolFlags == <STR_LIT> && AM . hasSymbolicDisplacement ( ) ) AM . Base_Reg = CurDAG -> getRegister ( <STR_LIT> , <STR_LIT> ) ; return


<s> AsmPrinter :: EmitGlobalVariable ( GV ) ; return ; } if ( GV -> isDeclaration ( ) || GV -> getLinkage ( ) == GlobalValue :: PrivateLinkage ) { AsmPrinter :: EmitGlobalVariable ( GV ) ; return ; } if ( <STR_LIT> ( GV ) ) return ; <ISA_LIT>TargetStreamer * TS = static_cast < <ISA_LIT>TargetStreamer * > ( OutStreamer -> getTargetStreamer ( ) ) ; if ( isModuleLinkage ( GV ) ) { TS -> Emit<ISA_LIT>HsaModuleScopeGlobal ( GV -> getName ( ) ) ; } else { TS -> Emit<ISA_LIT>HsaProgramScopeGlobal ( GV


<s> int <ISA_LIT>RegisterInfo :: getFrameIndexOffset ( MachineFunction & MF , int FI ) const { const TargetFrameInfo & TFI = * MF . getTarget ( ) . getFrameInfo ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; <ISA_LIT>MachineFunctionInfo * <ISA_LIT>MFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; int Offset = MFI -> getObjectOffset ( FI ) + MFI -> getOffsetAdjustment ( ) ; uint64_t StackSize = MFI -> getStackSize ( ) ; if ( FI < <NUM_LIT> ) StackSize -= <ISA_LIT>MFI -> getCalleeSavedFrameSize ( ) ; Offset += StackSize - TFI . getOffsetOfLocalArea ( ) ; if ( StackSize || MFI -> hasCalls ( ) ) Offset -= TFI . getOffsetOfLocalArea ( ) ; return Offset


<s> for ( auto * Entry : Pred -> successors ( ) ) { if ( ! Entries . count ( Entry ) || Map . count ( std :: make_pair ( InLoop . count ( Pred ) , Entry ) ) ) continue ; if ( EntryToLayoutPred . count ( std :: make_pair ( PredInLoop , Entry ) ) && EntryToLayoutPred [ std :: make_pair ( PredInLoop , Entry ) ] != Pred ) continue ; MachineBasicBlock * Routing = MF . CreateMachineBasicBlock ( ) ; MF . insert ( Pred -> isLayoutSuccessor ( Entry ) ? MachineFunction :: iterator ( Entry ) : MF . end ( ) , Routing ) ; Blocks . insert ( Routing ) ; BuildMI ( Routing , DebugLoc ( ) , TII . get ( <STR_LIT> ) , Reg ) . addImm ( Indices [ Entry ] ) ; BuildMI ( Routing , DebugLoc ( ) , TII . get ( <STR_LIT> ) ) . addMBB ( Dispatch ) ; Routing -> addSuccessor ( Dispatch ) ; Map [ std :: make_pair ( PredInLoop , Entry ) ] = Routing ; } } for ( auto * Pred : AllPreds ) { bool PredInLoop = InLoop . count ( Pred ) ; for ( MachineInstr & Term : Pred -> terminators ( ) ) for ( auto & Op : Term . explicit_uses ( ) ) if ( Op . isMBB ( ) && Indices . count ( Op . getMBB ( ) ) ) Op . setMBB ( Map [ std :: make_pair ( PredInLoop , Op . getMBB ( ) ) ] ) ; for ( auto * Succ : Pred -> successors ( ) ) { if ( ! Entries . count ( Succ ) ) continue ; auto * Routing = Map [ std :: make_pair ( PredInLoop , Succ ) ] ; Pred -> replaceSuccessor ( Succ ,


<s> } else { if ( LHS . getOpcode ( ) != <STR_LIT> ) A = LHS ; for ( unsigned i = <NUM_LIT> ; i != NumElts ; ++ i ) LMask [ i ] = i ; } SDValue C , D ; SmallVector < int , <NUM_LIT> > RMask ( NumElts ) ; if ( RHS . getOpcode ( ) == <STR_LIT> ) { if ( RHS . getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> ) C = RHS . getOperand ( <NUM_LIT> ) ; if ( RHS . getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> ) D = RHS . getOperand ( <NUM_LIT> ) ; ArrayRef < int > Mask = cast < ShuffleVectorSDNode > ( RHS . getNode ( ) ) -> getMask ( ) ; std :: copy ( Mask . begin ( ) , Mask . end ( ) , RMask . begin ( ) ) ; } else { if ( RHS . getOpcode ( ) != <STR_LIT> ) C = RHS ; for ( unsigned i = <NUM_LIT> ; i != NumElts ; ++ i ) RMask [ i ] = i ; } if ( ! ( A == C && B == D ) && ! ( A == D && B == C ) ) return false ; if ( ! A . getNode ( ) && ! B . getNode ( ) ) return false ; if ( A != C ) CommuteVectorShuffleMask ( RMask , NumElts ) ; for ( unsigned i = <NUM_LIT> ; i != NumElts ; ++ i ) { int LIdx = LMask [ i ] , RIdx = RMask [ i ] ; if ( LIdx < <NUM_LIT> || RIdx < <NUM_LIT> || ( ! A . getNode ( ) && ( LIdx < ( int ) NumElts || RIdx < ( int ) NumElts ) ) || ( ! B . getNode ( )

&& ( LIdx >= ( int ) NumElts || RIdx >= ( int ) NumElts ) ) ) continue ;


<s> bool <ISA_LIT>AsmParser :: ParseRegister ( unsigned & RegNo , SMLoc & StartLoc , SMLoc & EndLoc ) { return Error ( StartLoc ,


<s> static void frv_start_packet ( void ) { enum frv_insn_group group ; memset ( frv_packet . regstate , <NUM_LIT> , sizeof ( frv_packet . regstate ) ) ; frv_packet . num_mems = <NUM_LIT> ; frv_packet . num_insns = <NUM_LIT> ; for ( group = GROUP_I ; group <


<s> OperandMatchResultTy <ISA_LIT>AsmParser :: parseOptionalOpr ( OperandVector & Operands ) { OperandMatchResultTy res ; for ( const OptionalOperand & Op : <ISA_LIT>OptionalOperandTable ) { if ( Op . IsBit ) { res = parseNamedBit ( Op . Name , Operands , Op . Type ) ; } else if ( Op . Type == <ISA_LIT>Operand :: ImmTyOMod<ISA_LIT> ) { res = parseOModOperand ( Operands ) ; } else if ( Op . Type == <ISA_LIT>Operand :: ImmTySdwaDstSel || Op . Type == <ISA_LIT>Operand :: ImmTySdwaSrc0Sel || Op . Type == <ISA_LIT>Operand :: ImmTySdwaSrc1Sel ) { res = parseSDWASel ( Operands , Op . Name , Op . Type ) ; } else if ( Op . Type == <ISA_LIT>Operand :: ImmTySdwaDstUnused ) { res = parseSDWADstUnused ( Operands ) ; } else if ( Op . Type == <ISA_LIT>Operand :: ImmTyOpSel || Op . Type == <ISA_LIT>Operand :: ImmTyOpSelHi || Op . Type == <ISA_LIT>Operand :: ImmTyNegLo || Op . Type == <ISA_LIT>Operand :: ImmTyNegHi ) { res = parseOperandArrayWithPrefix ( Op . Name , Operands , Op . Type , Op . ConvertResult ) ; } else if ( Op . Type == <ISA_LIT>Operand :: ImmTyDim ) { res = parseDim ( Operands ) ; } else if ( Op . Type == <ISA_LIT>Operand :: ImmTyCPol ) { res = parseCPol ( Operands ) ; } else { res = parseIntWithPrefix ( Op . Name , Operands , Op . Type , Op . ConvertResult ) ; if ( Op . Type == <ISA_LIT>Operand ::

ImmTyBLGP && res == MatchOperand_NoMatch ) {


<s> for ( MachineBasicBlock & MBB : MF ) { for ( MachineInstr & MI : llvm :: make_early_inc_range ( MBB ) ) { if ( MI . getOpcode ( ) == <STR_LIT> ) { DebugLoc DL = MI . getDebugLoc ( ) ; Register Dst = MI . getOperand ( <NUM_LIT> )


<s> if ( ( MovY -> getOpcode ( ) != <STR_LIT> && MovY -> getOpcode ( ) != <STR_LIT> ) || ! MovY -> getOperand ( <NUM_LIT> ) . isReg ( ) || MovY -> getOperand ( <NUM_LIT> ) . getReg ( ) != T || MovY -> getOperand ( <NUM_LIT> ) . getSubReg ( ) != Tsub || MovY -> hasRegisterImplicitUseOperand ( <STR_LIT> ) ) continue ; Register Y = MovY -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Ysub = MovY -> getOperand ( <NUM_LIT> ) . getSubReg ( ) ; if ( ! TRI . isVGPR ( MRI , Y ) ) continue ; MachineInstr * MovX = nullptr ; for ( auto IY = MovY -> getIterator ( ) , I = std :: next ( MovT . getIterator ( ) ) ; I != IY ; ++ I ) { if ( instReadsReg ( & * I , X , Xsub , TRI ) || instModifiesReg ( & * I , Y , Ysub , TRI ) || instModifiesReg ( & * I , T , Tsub , TRI ) || ( MovX && instModifiesReg ( & * I , X , Xsub , TRI ) ) ) { MovX = nullptr ; break ; } if ( ! instReadsReg ( & * I , Y , Ysub , TRI ) ) { if ( ! MovX && instModifiesReg ( & * I , X , Xsub , TRI ) ) { MovX = nullptr ; break ; } continue ; } if ( MovX || ( I -> getOpcode ( ) != <STR_LIT> && I -> getOpcode ( ) != <STR_LIT> ) || I -> getOperand ( <NUM_LIT> ) . getReg ( ) != X || I -> getOperand ( <NUM_LIT> ) . getSubReg ( ) != Xsub ) { MovX = nullptr ; break ; } if ( I -> hasRegisterImplicitUseOperand ( <STR_LIT> ) ) continue ; if ( Size > <NUM_LIT> && ( I -> getNumImplicitOperands ( ) > ( I -> isCopy ( ) ? <NUM_LIT> : <NUM_LIT> ) ) ) continue ; MovX = & * I ; } if ( ! MovX ) continue ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << MovT << * MovX << * MovY ) ; for ( unsigned I = <NUM_LIT> ; I < Size ; ++ I ) { TargetInstrInfo :: RegSubRegPair X1 , Y1 ; X1 = getSubRegForIndex ( X , Xsub , I , TRI , MRI ) ; Y1 = getSubRegForIndex ( Y , Ysub , I , TRI , MRI ) ; MachineBasicBlock & MBB = * MovT . getParent ( ) ; auto MIB = BuildMI ( MBB , MovX -> getIterator ( ) , MovT . getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addDef ( X1 . Reg , <NUM_LIT> , X1 . SubReg ) . addDef ( Y1 . Reg , <NUM_LIT> , Y1 . SubReg ) .

addReg ( Y1 . Reg , <NUM_LIT> , Y1 . SubReg ) . addReg ( X1 . Reg , <NUM_LIT> , X1 . SubReg ) . getInstr ( ) ;


<s> void <ISA_LIT>MCCodeEmitter :: encodeInstruction ( const MCInst & MC , raw_ostream & OS , SmallVectorImpl < MCFixup

> & Fixups , const MCSubtargetInfo & STI ) const {


<s> LE . write < uint8_t > ( Value >> <NUM_LIT> ) ; if ( IsLittleEndian ) LE . write < uint8_t > ( ( Value >> <NUM_LIT> ) & <NUM_LIT> ) ; else LE . write < uint8_t > ( SwapBits ( ( Value >> <NUM_LIT> ) & <NUM_LIT> ) ) ; LE . write < uint16_t > ( <NUM_LIT> ) ; if ( IsLittleEndian ) LE . write < uint32_t > ( Value & <NUM_LIT> ) ; else BE . write < uint32_t > ( Value & <NUM_LIT> ) ; const MCOperand & MO = MI . getOperand ( <NUM_LIT> ) ; uint64_t Imm = MO . isImm ( ) ? MO . getImm ( ) : <NUM_LIT> ; LE . write < uint8_t > ( <NUM_LIT> ) ; LE . write < uint8_t > ( <NUM_LIT> ) ; LE . write < uint16_t > ( <NUM_LIT> ) ; if ( IsLittleEndian ) LE . write < uint32_t > ( Imm >> <NUM_LIT> ) ; else BE . write < uint32_t > ( Imm >> <NUM_LIT> ) ; } else { uint64_t Value = getBinaryCodeForInstr ( MI , Fixups , STI ) ; LE . write < uint8_t > ( Value >> <NUM_LIT> ) ; if ( IsLittleEndian ) { LE . write < uint8_t > ( ( Value >> <NUM_LIT> ) & <NUM_LIT> ) ; LE . write < uint16_t > ( ( Value >> <NUM_LIT> )


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: createReg ( Memory .


<s> return buildAUTIA ( MBB , DL , MI ) . addReg ( Ptr , RegState ::


<s> static SDValue getTargetShuffleNode ( unsigned Opc , DebugLoc dl , EVT VT , SDValue V1 , SDValue V2 , SelectionDAG & DAG ) { switch ( Opc ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> FOR_BB_INSNS ( bb , insn ) if ( CALL_P ( insn ) ) callee_abis . note_callee_abi ( insn_callee_abi ( insn ) ) ; HARD_REG_SET extra_caller_saves = callee_abis . caller_save_regs ( * crtl -> abi ) ; for ( unsigned regno = <NUM_LIT> ; regno <= LAST_SAVED_REGNUM ; regno ++ ) if ( ! fixed_regs [ regno ] && ! crtl -> abi -> clobbers_full_reg_p ( regno ) && ( TEST_HARD_REG_BIT ( extra_caller_saves , regno ) || bitmap_bit_p ( in , regno ) || bitmap_bit_p ( gen , regno ) || bitmap_bit_p ( kill , regno ) ) ) { bitmap_set_bit ( components , regno ) ; poly_int64 offset = cfun -> machine -> frame . reg_offset [ regno ] ; unsigned regno2 = multiple_p ( offset , <NUM_LIT> ) ? regno + <NUM_LIT> :


<s> MI . getOperand ( <NUM_LIT> ) . ChangeToRegister ( AddrTmp , false , false , true ) ; } MIB = BuildMI ( * thisMBB , MI , DL , TII -> get ( PtrLoadOpc ) , FP ) ; for ( unsigned i = <NUM_LIT> ; i < <STR_LIT> ; ++ i ) { const MachineOperand & MO = MI . getOperand ( i ) ; if ( MO . isReg ( ) ) MIB . addReg ( MO . getReg ( ) ) ; else MIB . add ( MO ) ; } MIB . setMemRefs ( MMOs ) ; MIB = BuildMI ( * thisMBB , MI , DL , TII -> get ( PtrLoadOpc ) , Tmp ) ; for ( unsigned i = <NUM_LIT> ; i < <STR_LIT> ; ++ i ) { const MachineOperand & MO = MI . getOperand ( i ) ; if ( i == <STR_LIT> ) MIB . addDisp ( MO , LabelOffset ) ; else if ( MO . isReg ( ) ) MIB . addReg ( MO . getReg ( ) ) ; else MIB . add ( MO ) ; } MIB . setMemRefs ( MMOs ) ; MIB = BuildMI ( * thisMBB , MI , DL , TII -> get ( PtrLoadOpc ) , SP ) ; for ( unsigned i = <NUM_LIT> ; i < <STR_LIT> ; ++ i ) { if ( i == <STR_LIT> ) MIB . addDisp ( MI . getOperand ( i ) , SPOffset ) ; else MIB . add ( MI . getOperand ( i ) ) ; } MIB . setMemRefs ( MMOs


<s> static tree rs6000_init_stack_protect_guard ( void ) { if ( rs6000_stack_protector_guard == SSP_GLOBAL ) return default_stack_protect_guard ( ) ; return NULL_TREE


<s> MCCodeEmitter * llvm :: create<ISA_LIT>MCCodeEmitter ( const MCInstrInfo & MCII , const MCRegisterInfo & MRI , MCContext & Ctx ) { return new <ISA_LIT>MCCodeEmitter ( MCII


<s> unsigned <ISA_LIT>AsmParser :: validateTargetOperandClass ( MCParsedAsmOperand & AsmOp , unsigned Kind ) { <ISA_LIT>Operand & Op = static_cast < <ISA_LIT>Operand & > ( AsmOp ) ; if ( ! Op . isReg ( ) ) return Match_InvalidOperand ; unsigned Reg = Op . getReg ( ) ; bool IsRegFPR32 = <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( Reg ) ; bool IsRegFPR32C = <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( Reg ) ; if ( ( IsRegFPR32 && Kind == MCK_FPR64 ) || ( IsRegFPR32C && Kind == MCK_FPR64C ) ) { Op . Reg . RegNum = convertFPR32ToFPR64 ( Reg ) ; return Match_Success ; } return


<s> if ( I -> mayStore ( ) ) { DebugLoc DL3 = MBB -> findDebugLoc ( I ) ; int storeOpcode = I -> getOpcode ( ) ; int loadOpcode = <NUM_LIT> ; int cmpOpcode = <NUM_LIT> ; switch ( storeOpcode ) { case <STR_LIT> : { loadOpcode = <STR_LIT> ; cmpOpcode = <STR_LIT> ; break ; } case <STR_LIT> : { loadOpcode = <STR_LIT> ; cmpOpcode = <STR_LIT> ; break ; } case <STR_LIT> : { loadOpcode = <STR_LIT> ; cmpOpcode = <STR_LIT> ; break ; } case <STR_LIT> : { loadOpcode = <STR_LIT> ; cmpOpcode = <STR_LIT> ; break ; } case <STR_LIT> : { loadOpcode = <STR_LIT> ; cmpOpcode = <STR_LIT> ; break ; } default : { errs ( ) << <STR_LIT> ; check = false ; } } if ( check ) { assert ( loadOpcode != <NUM_LIT> ) ; assert ( cmpOpcode != <NUM_LIT> ) ; MachineInstr * MIload = BuildMI ( MF , DL3 , TII -> get ( loadOpcode ) ) ; MIload -> setFlags


<s> case <STR_LIT> : return PerformCMOVCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformAddCombine ( N , DAG , Subtarget ) ; case <STR_LIT> : return PerformSubCombine ( N , DAG , Subtarget ) ; case <STR_LIT> : return PerformADCCombine ( N , DAG , DCI ) ; case <STR_LIT> : return PerformMulCombine ( N , DAG , DCI ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return PerformShiftCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformAndCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformOrCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformXorCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformLOADCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformSTORECombine ( N , DAG , Subtarget ) ; case <STR_LIT> : return PerformSINT_TO_FPCombine ( N , DAG , this ) ; case <STR_LIT> : return PerformFADDCombine ( N , DAG , Subtarget ) ; case <STR_LIT> : return PerformFSUBCombine ( N , DAG , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : return PerformFORCombine ( N , DAG ) ; case <STR_LIT> : case <STR_LIT> : return PerformFMinFMaxCombine ( N , DAG ) ; case <STR_LIT> : return PerformFANDCombine ( N , DAG ) ; case <STR_LIT> : return PerformFANDNCombine ( N , DAG ) ; case <STR_LIT> : return PerformBTCombine ( N , DAG , DCI ) ; case <STR_LIT> : return PerformVZEXT_MOVLCombine ( N , DAG ) ; case <STR_LIT> : case <STR_LIT> : return PerformZExtCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformSExtCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformSIGN_EXTEND_INREGCombine ( N , DAG , Subtarget ) ; case <STR_LIT> : return PerformTruncateCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformISDSETCCCombine ( N , DAG , Subtarget ) ; case <STR_LIT> : return PerformSETCCCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformBrCondCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return performVZEXTCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return PerformShuffleCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformFMACombine ( N , DAG , Subtarget ) ; case <STR_LIT> : return PerformINTRINSIC_WO_CHAINCombine ( N , DAG , Subtarget ) ; case <STR_LIT> : return PerformINSERTPSCombine ( N , DAG , Subtarget ) ; case <STR_LIT> : return PerformBUILD_VECTORCombine ( N , DAG , Subtarget ) ; } return SDValue (


<s> assert ( BB . isMBB ( ) && <STR_LIT> ) ; auto MBB = BB . getMBB ( ) ; Info [ MBB ] . Instructions . push_back


<s> for ( i = <NUM_LIT> ; i < nregs ; i ++ ) { rtx tem = adjust_address_nv ( x , reg_mode , i * GET_MODE_SIZE ( reg_mode ) ) ; if ( reload_completed ) { if ( ! strict_memory_address_p ( reg_mode , XEXP ( tem , <NUM_LIT> ) ) ) tem = NULL_RTX ; else tem = simplify_gen_subreg ( reg_mode , x , BLKmode ,


<s> static bool arc_symbol_binds_local_p ( const_rtx x ) { return ( SYMBOL_REF_DECL ( x ) ? targetm . binds_local_p ( SYMBOL_REF_DECL


<s> static MCOperand GetSymbolRef ( const MachineOperand & MO , const MCSymbol * Symbol , <ISA_LIT>AsmPrinter & Printer ) { MCContext & MC = Printer . OutContext ; const MCExpr * ME ; ME = MCSymbolRefExpr :: Create ( Symbol


<s> assert ( RemapSwizzle . empty ( ) ) ; SDValue NewBldVec [ <NUM_LIT> ] = { VectorEntry . getOperand ( <NUM_LIT> ) , VectorEntry . getOperand ( <NUM_LIT> ) , VectorEntry . getOperand ( <NUM_LIT> ) , VectorEntry . getOperand ( <NUM_LIT> ) } ; for ( unsigned i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) { if ( NewBldVec [ i ] . getOpcode ( ) == <STR_LIT> ) RemapSwizzle [ i ] = <NUM_LIT> ; if ( ConstantFPSDNode * C = dyn_cast < ConstantFPSDNode > ( NewBldVec [ i ] ) ) { if ( C -> isZero ( ) ) { RemapSwizzle [ i ] = <NUM_LIT> ; NewBldVec [ i ] = DAG . getUNDEF ( <STR_LIT> ) ; } else if ( C -> isExactlyValue ( <NUM_LIT> ) ) { RemapSwizzle [ i ]