<s> op [ <NUM_LIT> ] = gen_rtx_SYMBOL_REF ( Pmode , <STR_LIT> ) ; if ( flag_pic ) { op [ <NUM_LIT> ] = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( <NUM_LIT> , op [ <NUM_LIT> ] ) , UNSPEC_PLT ) ; op [ <NUM_LIT> ] = gen_rtx_CONST ( Pmode , op [ <NUM_LIT> ] ) ; } if ( TARGET_64BIT ) { output_asm_insn ( <STR_LIT> , op ) ; output_asm_insn ( <STR_LIT> , op ) ; output_asm_insn ( <STR_LIT> , op ) ; output_asm_insn ( <STR_LIT> , op ) ; } else if ( TARGET_CPU_ZARCH ) { output_asm_insn ( <STR_LIT> , op ) ; output_asm_insn ( <STR_LIT> , op ) ; output_asm_insn ( <STR_LIT> , op ) ; output_asm_insn ( <STR_LIT> , op ) ; } else if ( ! flag_pic ) { op [ <NUM_LIT> ] = gen_label_rtx ( ) ; output_asm_insn ( <STR_LIT> , op ) ; output_asm_insn ( <STR_LIT> , op ) ; output_asm_insn ( <STR_LIT> , op ) ; output_asm_insn ( <STR_LIT> , op ) ; targetm . asm_out . internal_label ( file , <STR_LIT> , CODE_LABEL_NUMBER ( op [ <NUM_LIT> ] ) ) ; output_asm_insn ( <STR_LIT> , op ) ; output_asm_insn ( <STR_LIT> , op


<s> uint32_t size = pSD . getSection ( ) . size ( ) ; if ( pSD . getSection ( ) . type ( ) == llvm :: ELF :: SHT_NOBITS ) { frag = new FillFragment ( <NUM_LIT> , <NUM_LIT> , size ) ; } else { llvm :: StringRef region = pInput . memArea ( ) -> request ( offset , size ) ; if ( region . size ( ) == <NUM_LIT> ) { frag = new FillFragment ( <NUM_LIT> , <NUM_LIT> ,


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT>


<s> vec_uchar16 d ; d = vec_and ( ( vec_uchar16 ) ( a ) ,


<s> bool <ISA_LIT>MCInstrInfo :: isSoloAX ( MCInstrInfo const & MCII , MCInst const


<s> } unsigned Opcode = decodeThumbSideEffect ( IsThumb2 , insn ) ; if ( Thumb2PreloadOpcodeNoPCI ( Opcode ) && slice ( insn , <NUM_LIT> , <NUM_LIT> ) == <NUM_LIT> ) Opcode = T2Morph2Preload2PCI ( Opcode ) ; <ISA_LIT>Format Format = <ISA_LIT>Formats [ Opcode ] ; Size = IsThumb2 ? <NUM_LIT> : <NUM_LIT> ; DEBUG ( { errs ( ) << <STR_LIT> << Opcode << <STR_LIT> << <STR_LIT> ( Opcode ) << <STR_LIT> << stringFor<ISA_LIT>Format ( Format ) << '(' << ( int ) Format << <STR_LIT> ; showBitVector ( errs ( ) , insn ) ; } ) ; <ISA_LIT>BasicMCBuilder * Builder = CreateMCBuilder ( Opcode , Format ) ; if ( ! Builder ) return false ; Builder -> SetSession ( const_cast < Session * > ( & SO ) ) ; if ( ! Builder -> Build ( MI , insn ) ) return false ; delete Builder


<s> RegisterTargetMachine < <ISA_LIT>TargetMachine > X


<s> switch ( MI . getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return


<s> bool IsGDS = PtrTy . getAddressSpace ( ) == <ISA_LIT>AS :: REGION_ADDRESS ; unsigned Offset ; std :: tie ( PtrBase , Offset ) = selectDS1Addr1OffsetImpl ( MI . getOperand ( <NUM_LIT> ) ) ; if ( ! isDSOffsetLegal ( PtrBase , Offset ) ) { PtrBase = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Offset = <NUM_LIT> ; } MachineBasicBlock * MBB = MI . getParent ( ) ; const DebugLoc & DL = MI . getDebugLoc ( ) ; const unsigned Opc = IsAppend ? <STR_LIT> : <STR_LIT> ; BuildMI ( * MBB , & MI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( PtrBase ) ; if ( ! RBI . constrainGenericRegister ( PtrBase , <STR_LIT> , * MRI ) ) return false ; auto MIB = BuildMI ( * MBB , & MI , DL , TII . get ( Opc ) , MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) . addImm ( Offset ) . addImm ( IsGDS ? - <NUM_LIT> : <NUM_LIT> ) . cloneMemRefs ( MI ) ; MI . eraseFromParent


<s> CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; rounded_size = ( ( mode == BLKmode ) ? int_size_in_bytes ( type ) : GET_MODE_SIZE ( mode ) ) ; if ( rounded_size & <NUM_LIT> ) rounded_size ++ ; ( * cum ) +=


<s> static bool isSpvIntrinsic ( MachineInstr & MI , <STR_LIT> IntrinsicID ) { if ( MI . getOpcode ( ) == TargetOpcode :: G_INTRINSIC_W_SIDE_EFFECTS && MI . getIntrinsicID ( ) == IntrinsicID


<s> static void x86_print_call_or_nop ( FILE * file , const char * target ) { if ( flag_nop_mcount ) fprintf ( file , <STR_LIT> ) ; else fprintf ( file , <STR_LIT> , target


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , Optional < CodeModel :: Model > CM , CodeGenOpt :: Level OL , bool JIT ) : LLVMTargetMachine ( T , computeDataLayout ( TT ) , TT , CPU , FS , Options , getEffectiveRelocModel ( TT , RM ) , getEffectiveCodeModel ( CM , CodeModel :: Small ) , OL ) , TLOF ( make_unique < TargetLoweringObjectFileELF > ( ) ) , Subtarget ( TT , CPU , FS , * this ) { initAsmInfo (


<s> GVSym -> setContainingCsect ( Csect ) ; const DataLayout & DL = GV -> getParent ( ) -> getDataLayout ( ) ; if ( GVKind . isCommon ( ) || GVKind . isBSSLocal ( ) ) { unsigned Align = GV -> getAlignment ( ) ? GV -> getAlignment ( ) : DL . getPreferredAlignment ( GV ) ; uint64_t Size = DL . getTypeAllocSize ( GV -> getType ( ) -> getElementType ( ) ) ; if ( GVKind . isBSSLocal ( ) ) OutStreamer -> EmitXCOFFLocalCommonSymbol ( GVSym , Size , Csect -> getQualNameSymbol ( ) , Align ) ; else OutStreamer -> EmitCommonSymbol ( Csect -> getQualNameSymbol ( ) , Size , Align ) ; return ; } MCSymbol * EmittedInitSym = GVSym ; EmitLinkage ( GV , EmittedInitSym


<s> return CurDAG -> getTargetConstant ( Imm -


<s> if ( Val == <NUM_LIT> || Val == <NUM_LIT> ) return MCDisassembler :: Fail ; const FeatureBitset & featureBits = ( ( const MCDisassembler * ) Decoder ) -> getSubtargetInfo ( ) . getFeatureBits ( ) ; if ( featureBits [ <STR_LIT> ] && ! ( Val == <NUM_LIT> || Val == <NUM_LIT> ) ) return MCDisassembler :: Fail ; if ( featureBits [ <STR_LIT> ] && ( ( Val & <NUM_LIT> ) == <NUM_LIT> || ( Val & <NUM_LIT> ) == <NUM_LIT> || ( Val & <NUM_LIT> ) == <NUM_LIT> ) ) return MCDisassembler :: Fail ; Inst . addOperand ( MCOperand :: createImm ( Val ) ) ; return MCDisassembler :: Success


<s> rtx loop_label , tmp ; if ( optimize_size || optimize < <NUM_LIT> ) return false ; gcc_assert ( MEM_P ( str ) ) ; gcc_assert ( CONST_INT_P ( target_char ) || REG_P ( target_char ) ) ; base_reg = copy_to_mode_reg ( SImode , XEXP ( str , <NUM_LIT> ) ) ; loop_label = gen_label_rtx ( ) ; ffb_result = gen_reg_rtx ( Pmode ) ; tmp = gen_reg_rtx ( SImode ) ; backup_base_reg = gen_reg_rtx ( SImode ) ; emit_move_insn ( backup_base_reg , base_reg ) ; emit_label ( loop_label ) ; emit_insn ( gen_unaligned_load_update_base_w ( base_reg , tmp , base_reg ) ) ; emit_insn ( gen_unspec_ffb ( ffb_result , tmp , target_char ) ) ; emit_cmp_and_jump_insns ( ffb_result , const0_rtx , EQ , NULL , SImode , <NUM_LIT> , loop_label ) ; target_char_ptr = expand_binop ( Pmode , add_optab , base_reg , ffb_result , NULL_RTX , <NUM_LIT> , OPTAB_WIDEN ) ; length = expand_binop ( Pmode , sub_optab , target_char_ptr , backup_base_reg , NULL_RTX , <NUM_LIT> , OPTAB_WIDEN ) ; emit_move_insn ( result , length


<s> UseScaled = false ; ScaleFactor = <NUM_LIT> ; } static const unsigned OpcTable [ <NUM_LIT> ] [ <NUM_LIT> ] = { { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } } ; unsigned Opc ; const TargetRegisterClass * RC ; bool VTIsi1 = false ; bool UseRegOffset = Addr . isRegBase ( ) && ! Addr . getOffset ( ) && Addr . getReg ( ) && Addr . getOffsetReg ( ) ; unsigned Idx = UseRegOffset ? <NUM_LIT> : UseScaled ? <NUM_LIT> : <NUM_LIT> ; if ( Addr . getExtendType ( ) == <STR_LIT> || Addr . getExtendType ( ) == <STR_LIT> ) Idx ++ ; switch ( VT . SimpleTy ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : VTIsi1 = true ; case <STR_LIT> : Opc = OpcTable [ Idx ] [ <NUM_LIT> ] ; RC = & <STR_LIT> ; break ; case <STR_LIT> : Opc = OpcTable [ Idx ] [ <NUM_LIT> ] ; RC = & <STR_LIT> ; break ; case <STR_LIT> : Opc = OpcTable [ Idx ] [ <NUM_LIT> ] ; RC = & <STR_LIT> ; break ; case <STR_LIT> : Opc = OpcTable [ Idx ] [ <NUM_LIT> ] ; RC = & <STR_LIT> ; break ; case <STR_LIT> : Opc = OpcTable [ Idx ] [ <NUM_LIT>


<s> bool isMemV10 ( ) const { return Kind ==


<s> Inst . addOperand ( MCOperand :: createReg ( getMemBaseNum ( )


<s> if ( CC == <STR_LIT> ) if ( SDValue Flags = combineCarryThroughADD ( CCR ) ) return Flags ; if ( SDValue R = checkBoolTestSetCCCombine ( CCR , CC ) ) return


<s> const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const MachineModuleInfo & MMI = MF . getMMI ( ) ; return ( MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) || TRI -> needsStackRealignment ( MF ) || MFI . hasVarSizedObjects ( ) || MFI . isFrameAddressTaken ( ) || MFI . hasOpaqueSPAdjustment ( ) || MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) -> getForceFramePointer ( ) || MMI . callsUnwindInit ( ) || MMI . hasEHFunclets ( ) ||

MMI . callsEHReturn ( ) || MFI . hasStackMap ( ) || MFI . hasPatchPoint ( ) || MFI . hasCopyImplyingStackAdjustment ( ) ) ;


<s> bool <ISA_LIT>TargetLowering :: CanLowerReturn ( CallingConv :: ID CallConv , MachineFunction & MF , bool IsVarArg , const SmallVectorImpl < <STR_LIT> > & Outs , LLVMContext & Context ) const { SmallVector < CCValAssign , <NUM_LIT> > RVLocs ; CCState CCInfo ( CallConv , IsVarArg , MF , RVLocs , Context ) ; if ( MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . useHVXOps ( ) ) return CCInfo .

CheckReturn ( Outs , RetCC_<ISA_LIT>_HVX ) ;


<s> return ; } for ( MachineBasicBlock * Succ : MBB -> successors ( ) ) if (

Succ != MBB ) findReturns ( Succ , Cycles ) ;


<s> case <STR_LIT> : case <STR_LIT> : Opcode = <STR_LIT> ; break ; } SDVTList VTs = CurDAG -> getVTList ( <STR_LIT> ) ; SDValue Ops [ ] = { Address , ImmOperand , Predicate , Base , Modifier , Offset , Chain } ; SDNode * Result = CurDAG -> getMachineNode ( Opcode , dl , VTs , Ops ) ; MachineMemOperand * MemOp = cast < MemIntrinsicSDNode > ( N ) -> getMemOperand ( ) ; CurDAG -> setNodeMemRefs ( cast < MachineSDNode > (


<s> for ( int i = Pos , e = Pos + Size ; i != e ; ++ i ) if ( ! isUndefOrInRange ( Mask [ i ] , Low , Hi


<s> Result . Named . VM = ! ! ( TSFlags & <STR_LIT> ) ; Result . Named . EXP = ! ! ( TSFlags & <STR_LIT> && ( MI . getOpcode ( ) == AMDGPU :: EXP || MI . getDesc ( ) . mayStore ( ) ) ) ; if ( TSFlags & <STR_LIT> ) { MachineOperand & Op = MI . getOperand ( <NUM_LIT> ) ; assert ( Op . isReg ( ) && <STR_LIT> ) ; unsigned Reg = Op . getReg ( ) ; unsigned Size = TRI -> getMinimalPhysRegClass ( Reg ) -> getSize ( ) ; Result . Named . LGKM = Size > <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ; } else


<s> static enum machine_mode rs6000_eh_return_filter_mode ( void ) { return TARGET_32BIT ? SImode


<s> BlockToSetOfInstrsPerColor Out , In , ReachableUses ; BlockToInstrPerColor Gen ; BlockToRegSet Kill ; initReachingDef ( MF , ColorOpToReachedUses , Gen , Kill , ReachableUses , RegToId , DummyOp ,


<s> static SDValue combineSelectAndUseCommutative ( SDNode * N , SelectionDAG & DAG , bool AllOnes ) { SDValue N0 = N -> getOperand ( <NUM_LIT> ) ; SDValue N1 = N -> getOperand ( <NUM_LIT> ) ; if ( SDValue Result = combineSelectAndUse ( N , N0 , N1 , DAG ,


<s> RegisterTargetMachine < <ISA_LIT>LETargetMachine > X ( getThe<ISA_LIT>LETarget ( ) ) ; RegisterTargetMachine < <ISA_LIT>LETargetMachine > A ( getTheThumbLETarget ( ) ) ; RegisterTargetMachine < <ISA_LIT>BETargetMachine > Y ( getThe<ISA_LIT>BETarget ( ) ) ; RegisterTargetMachine < <ISA_LIT>BETargetMachine > B ( getTheThumbBETarget ( ) ) ; PassRegistry & Registry = * PassRegistry :: getPassRegistry ( ) ; initializeGlobalISel ( Registry ) ; initialize<ISA_LIT>LoadStoreOptPass (


<s> assert ( Kind == k_Register && <STR_LIT> ) ; assert ( N == <NUM_LIT> && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: createReg (


<s> void alpha_split_lock_test_and_set_12 ( enum machine_mode mode , rtx dest , rtx addr , rtx val , rtx align , rtx scratch ) { rtx label , mem , width , mask , x ; mem = gen_rtx_MEM ( DImode , align ) ; MEM_VOLATILE_P ( mem ) = <NUM_LIT> ; emit_insn ( gen_memory_barrier ( ) ) ; label = gen_rtx_LABEL_REF ( DImode , gen_label_rtx ( ) ) ; emit_label ( XEXP ( label , <NUM_LIT> ) ) ; emit_load_locked ( DImode , scratch , mem ) ; width = GEN_INT ( GET_MODE_BITSIZE ( mode ) ) ; mask = GEN_INT ( mode == QImode ? <NUM_LIT> : <NUM_LIT> ) ; if ( WORDS_BIG_ENDIAN ) { emit_insn ( gen_extxl_be ( dest , scratch , width , addr ) ) ; emit_insn ( gen_mskxl_be ( scratch , scratch , mask , addr ) ) ; } else { emit_insn ( gen_extxl_le ( dest , scratch , width , addr ) ) ; emit_insn ( gen_mskxl_le ( scratch , scratch , mask , addr ) ) ; } emit_insn ( gen_iordi3 ( scratch , scratch , val


<s> const <ISA_LIT>RegisterInfo * RI = MF . getSubtarget < GCNSubtarget > ( ) . getRegisterInfo ( ) ; FrameReg = RI -> getFrameRegister


<s> if ( N -> getAddressSpace ( ) == <ISA_LIT>AS :: CONSTANT_ADDRESS ) if ( Subtarget -> getGeneration ( ) <

<ISA_LIT>Subtarget :: SOUTHERN_ISLANDS || N -> getMemoryVT ( ) . bitsLT ( <STR_LIT> ) ) return true ;


<s> case UNGT : case UNGE : break ; case EQ : case NE : case UNORDERED : case ORDERED : if ( TARGET_AVX ) break ; if ( ! dest || ! rtx_equal_p ( dest , * pop1 ) ) break ; case GE : case GT : case UNLE : case UNLT : std :: swap ( * pop0 , * pop1 ) ; code = swap_condition ( code ) ; break ; default : gcc_unreachable ( )


<s> if ( ! NoAliases ) Res = uncompressInst ( UncompressedMI , * MI , MRI , STI ) ; if ( Res ) NewMI = const_cast < MCInst * > ( &


<s> MachineBasicBlock :: iterator MBBI = MBB . end ( ) ; DebugLoc DL ; if ( ! MBB . empty ( ) ) { MBBI = MBB . getFirstTerminator ( ) ; if ( MBBI == MBB . end ( ) ) MBBI = MBB . getLastNonDebugInstr ( ) ; DL = MBBI -> getDebugLoc ( ) ; if ( ! MBBI -> isTerminator ( ) ) MBBI = std :: next ( MBBI ) ; while ( MBBI != MBB . begin ( ) && std :: prev ( MBBI ) -> getFlag ( MachineInstr :: FrameDestroy ) ) -- MBBI ; } const auto & CSI = getNonLibcallCSI ( MFI . getCalleeSavedInfo ( ) ) ; auto LastFrameDestroy = MBBI ; if ( ! CSI . empty ( ) ) LastFrameDestroy = std :: prev ( MBBI , CSI . size ( ) ) ; uint64_t StackSize = MFI . getStackSize ( ) ; uint64_t RealStackSize = StackSize + RVFI -> getLibCallStackSize ( ) ; uint64_t FPOffset = RealStackSize - RVFI


<s> const <ISA_LIT>RegisterInfo * RI = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getRegisterInfo ( ) ; FrameReg = RI -> getFrameRegister


<s> for ( i = <NUM_LIT> ; i < issue_rate ; i ++ ) { sd_iterator_def sd_it ; dep_t dep ; rtx insn = group_insns [ i ] ; if ( ! insn ) continue ; FOR_EACH_DEP ( insn , SD_LIST_RES_FORW , sd_it ,


<s> Old . ChangeToImmediate ( Fold . ImmToFold & <NUM_LIT> ) ; return true ; } break ; default : break ; } } } } if ( ( Fold . isImm ( ) || Fold . isFI ( ) || Fold . isGlobal ( ) ) && Fold . needsShrink ( ) ) { MachineBasicBlock * MBB = MI -> getParent ( ) ; auto Liveness = MBB -> computeRegisterLiveness ( & TRI , <STR_LIT> , MI , <NUM_LIT> ) ; if ( Liveness != MachineBasicBlock :: LQR_Dead ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << MI << <STR_LIT> ) ; return false ; } MachineRegisterInfo & MRI = MBB -> getParent ( ) -> getRegInfo ( ) ; int Op32 = Fold . getShrinkOpcode ( ) ; MachineOperand & Dst0 = MI -> getOperand ( <NUM_LIT> ) ; MachineOperand & Dst1 = MI -> getOperand ( <NUM_LIT> ) ; assert ( Dst0 . isDef ( ) && Dst1 . isDef ( ) ) ; bool HaveNonDbgCarryUse = ! MRI . use_nodbg_empty ( Dst1 . getReg ( ) ) ; const TargetRegisterClass * Dst0RC = MRI . getRegClass ( Dst0 . getReg ( ) ) ; Register NewReg0 = MRI . createVirtualRegister ( Dst0RC ) ; MachineInstr * Inst32 = TII . buildShrunkInst ( * MI , Op32 ) ; if ( HaveNonDbgCarryUse ) { BuildMI ( * MBB , MI , MI -> getDebugLoc ( ) , TII . get ( <STR_LIT> ) , Dst1 . getReg ( ) ) . addReg ( <STR_LIT> , RegState :: Kill ) ; } Dst0 . setReg ( NewReg0 ) ; for ( unsigned I = MI -> getNumOperands ( ) - <NUM_LIT> ; I > <NUM_LIT> ; -- I ) MI -> removeOperand ( I ) ; MI -> setDesc ( TII . get ( <STR_LIT> ) ) ; if ( Fold . isCommuted ( ) ) TII . commuteInstruction ( * Inst32 , false ) ; return true ; } assert ( ! Fold . needsShrink ( ) && <STR_LIT> ) ; if ( Fold . isImm ( ) ) { if ( Old . isTied ( ) ) { int NewMFMAOpc = <STR_LIT> ( MI -> getOpcode ( ) ) ; if ( NewMFMAOpc == - <NUM_LIT> ) return false ; MI -> setDesc ( TII . get ( NewMFMAOpc ) ) ; MI -> untieRegOperand ( <NUM_LIT> ) ; } Old . ChangeToImmediate ( Fold . ImmToFold ) ; return true ; } if ( Fold . isGlobal ( ) ) { Old . ChangeToGA ( Fold . OpToFold -> getGlobal ( ) , Fold . OpToFold -> getOffset ( ) , Fold . OpToFold -> getTargetFlags ( ) ) ; return true ; } if ( Fold . isFI ( ) ) { Old . ChangeToFrameIndex ( Fold . FrameIndexToFold ) ; return true


<s> static MCSymbolizer * create<ISA_LIT>ExternalSymbolizer ( StringRef TT , LLVMOpInfoCallback GetOpInfo , LLVMSymbolLookupCallback SymbolLookUp , void * DisInfo , MCContext * Ctx , MCRelocationInfo * RelInfo ) { return new llvm :: <ISA_LIT>ExternalSymbolizer ( * Ctx , std :: unique_ptr < MCRelocationInfo >

( RelInfo ) , GetOpInfo , SymbolLookUp , DisInfo ) ;


<s> ShiftElts = IsLE ? LittleEndianShifts [ M0 & <NUM_LIT> ] : BigEndianShifts [ M0 & <NUM_LIT> ] ; InsertAtByte = IsLE ? <NUM_LIT> : <NUM_LIT> ; Swap = M0 < <NUM_LIT> ; return true ; } if ( ( M1 > <NUM_LIT> && M0 == <NUM_LIT> && M2 == <NUM_LIT> && M3 == <NUM_LIT> ) || ( M1 < <NUM_LIT> && M0 == <NUM_LIT> && M2 == <NUM_LIT> && M3 == <NUM_LIT> ) ) { ShiftElts = IsLE ? LittleEndianShifts [ M1 & <NUM_LIT> ] : BigEndianShifts [ M1 & <NUM_LIT> ] ; InsertAtByte = IsLE ? <NUM_LIT> : <NUM_LIT> ; Swap = M1 < <NUM_LIT> ; return true ; } if ( ( M2 > <NUM_LIT> && M0 == <NUM_LIT> && M1 == <NUM_LIT> && M3 == <NUM_LIT> ) || ( M2 < <NUM_LIT> && M0 == <NUM_LIT> && M1 == <NUM_LIT> && M3 == <NUM_LIT> ) ) { ShiftElts = IsLE ? LittleEndianShifts [ M2 & <NUM_LIT> ] : BigEndianShifts [ M2 & <NUM_LIT> ] ; InsertAtByte = IsLE ? <NUM_LIT> : <NUM_LIT> ; Swap = M2 < <NUM_LIT> ; return true ; } if ( ( M3 > <NUM_LIT> && M0 == <NUM_LIT> && M1 == <NUM_LIT> && M2 == <NUM_LIT> ) || ( M3 < <NUM_LIT> && M0 == <NUM_LIT> && M1 == <NUM_LIT> && M2 == <NUM_LIT> ) ) { ShiftElts = IsLE ? LittleEndianShifts [ M3 & <NUM_LIT> ] : BigEndianShifts [ M3 & <NUM_LIT> ] ; InsertAtByte = IsLE ? <NUM_LIT> : <NUM_LIT> ; Swap = M3 < <NUM_LIT> ; return true ; } if ( N -> getOperand ( <NUM_LIT> ) . isUndef ( ) ) { ShiftElts = <NUM_LIT> ; Swap = true ; unsigned XXINSERTWSrcElem = IsLE ? <NUM_LIT> : <NUM_LIT> ; if ( M0 == XXINSERTWSrcElem && M1 == <NUM_LIT> && M2 == <NUM_LIT> && M3 == <NUM_LIT> ) { InsertAtByte = IsLE ? <NUM_LIT> : <NUM_LIT> ; return true ; } if ( M0 == <NUM_LIT> && M1 == XXINSERTWSrcElem && M2 == <NUM_LIT> && M3 == <NUM_LIT> ) { InsertAtByte = IsLE ? <NUM_LIT> : <NUM_LIT> ; return true ; } if ( M0 == <NUM_LIT> && M1 == <NUM_LIT> && M2 == XXINSERTWSrcElem && M3 == <NUM_LIT> ) { InsertAtByte = IsLE ? <NUM_LIT> : <NUM_LIT> ; return true ; } if ( M0 == <NUM_LIT> && M1 == <NUM_LIT> && M2 == <NUM_LIT> &&


<s> bool isu1Imm ( ) const { return CheckImmRange ( <NUM_LIT> , <NUM_LIT> , false , false , false


<s> status = DecodeI64RegisterClass ( MI , sy , Address , Decoder ) ; if ( status != MCDisassembler :: Success ) return status ; } else { MI . addOperand ( MCOperand :: createImm ( SignExtend32 < <NUM_LIT> > ( sy ) ) ) ; } MI . addOperand ( MCOperand :: createImm ( simm32 ) ) ; return MCDisassembler ::


<s> bytes = INTVAL ( bytes_rtx ) ; if ( bytes <= <NUM_LIT> ) return <NUM_LIT> ; if ( TARGET_ALTIVEC && ( align >= <NUM_LIT> || TARGET_EFFICIENT_UNALIGNED_VSX ) ) clear_step = <NUM_LIT> ; else if ( TARGET_POWERPC64 && ( align >= <NUM_LIT> || ! STRICT_ALIGNMENT ) ) clear_step = <NUM_LIT> ; else clear_step = <NUM_LIT> ; if ( optimize_size && bytes > <NUM_LIT> * clear_step ) return <NUM_LIT> ; if ( ! optimize_size && bytes > <NUM_LIT> * clear_step ) return <NUM_LIT> ; for ( offset = <NUM_LIT> ; bytes > <NUM_LIT> ; offset += clear_bytes , bytes -= clear_bytes ) { machine_mode mode = BLKmode ; rtx dest ; if ( bytes >= <NUM_LIT> && TARGET_ALTIVEC && ( align >= <NUM_LIT> || TARGET_EFFICIENT_UNALIGNED_VSX ) ) { clear_bytes = <NUM_LIT> ; mode = V4SImode ; } else if ( bytes >= <NUM_LIT> && TARGET_POWERPC64 && ( align >= <NUM_LIT> || ! STRICT_ALIGNMENT ) ) { clear_bytes = <NUM_LIT> ; mode = DImode ; if ( offset == <NUM_LIT> && align < <NUM_LIT> ) { rtx addr ; addr = XEXP ( orig_dest , <NUM_LIT> ) ; if ( ( GET_CODE ( addr ) == PLUS || GET_CODE ( addr ) == LO_SUM ) && GET_CODE ( XEXP ( addr , <NUM_LIT> ) ) == CONST_INT && ( INTVAL ( XEXP ( addr , <NUM_LIT> ) ) & <NUM_LIT> ) != <NUM_LIT> ) { addr = copy_addr_to_reg ( addr ) ; orig_dest = replace_equiv_address ( orig_dest , addr ) ; } } } else if ( bytes >= <NUM_LIT> && ( align >= <NUM_LIT> || ! STRICT_ALIGNMENT ) ) { clear_bytes = <NUM_LIT> ; mode = SImode


<s> static int bfin_arg_partial_bytes ( cumulative_args_t cum , const function_arg_info & arg ) { int bytes = arg . promoted_size_in_bytes ( ) ; int bytes_left = get_cumulative_args ( cum ) -> nregs * UNITS_PER_WORD ; if ( bytes == - <NUM_LIT> )


<s> bool <ISA_LIT>AsmParser :: parseDirectiveSEHEpilogStart (


<s> static SDValue tryAdvSIMDModImm8 ( unsigned NewOp , SDValue Op , SelectionDAG & DAG , const APInt & Bits ) { if ( Bits . getHiBits ( <NUM_LIT> ) == Bits . getLoBits ( <NUM_LIT> ) ) { uint64_t Value = Bits . zextOrTrunc ( <NUM_LIT> ) . getZExtValue ( ) ; EVT VT = Op . getValueType ( ) ; MVT MovTy = ( VT . getSizeInBits ( ) == <NUM_LIT> ) ? <STR_LIT> : <STR_LIT> ; if ( <STR_LIT> ( Value ) ) { Value = <STR_LIT> ( Value ) ; SDLoc dl ( Op ) ; SDValue Mov = DAG . getNode ( NewOp , dl , MovTy , DAG . getConstant ( Value , dl , <STR_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Mov ) ; } } return SDValue (


<s> virtual bool track ( const TargetRegisterClass * RC ) const { return true


<s> for ( auto * U : V -> users ( ) ) Worklist . push_back ( U ) ; while ( ! Worklist . empty ( ) ) { auto * U = Worklist . pop_back_val ( ) ; if ( isa < ConstantExpr > ( U ) ) { for ( auto * UU : U -> users ( ) ) Worklist . push_back ( UU ) ; continue ; } auto * I = dyn_cast < Instruction > ( U ) ; if ( ! I || I -> getParent ( ) -> getParent ( ) != F


<s> V1 = DAG . getBitcast ( <STR_LIT> , V1 ) ; int WidenedMask [ <NUM_LIT> ] = { std :: max ( Mask [ <NUM_LIT> ] , <NUM_LIT> ) * <NUM_LIT> , std :: max ( Mask [ <NUM_LIT> ] , <NUM_LIT> ) * <NUM_LIT> + <NUM_LIT> , std :: max ( Mask [ <NUM_LIT> ] , <NUM_LIT> ) * <NUM_LIT> , std :: max ( Mask [ <NUM_LIT> ] , <NUM_LIT> ) * <NUM_LIT> + <NUM_LIT> } ; return DAG . getBitcast ( <STR_LIT> , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , getV4<ISA_LIT>ShuffleImm8ForMask ( WidenedMask , DL , DAG ) ) ) ; } assert ( Mask [ <NUM_LIT> ] != - <NUM_LIT> && <STR_LIT> ) ; assert ( Mask [ <NUM_LIT> ] != - <NUM_LIT> && <STR_LIT> ) ; assert ( Mask [ <NUM_LIT> ] < <NUM_LIT> && <STR_LIT> ) ; assert ( Mask [ <NUM_LIT> ] >= <NUM_LIT> && <STR_LIT> ) ; auto GetPackNode = [ ] ( SDValue V ) { V = peekThroughBitcasts ( V ) ; return V . getOpcode ( ) == <STR_LIT> ? V : SDValue ( ) ; } ; if ( SDValue V1Pack = GetPackNode ( V1 ) ) if ( SDValue V2Pack = GetPackNode ( V2 ) ) { EVT PackVT = V1Pack . getValueType ( ) ; if ( PackVT == V2Pack . getValueType ( ) ) return DAG . getBitcast ( <STR_LIT> , DAG . getNode ( <STR_LIT> , DL , PackVT , Mask [ <NUM_LIT> ] == <NUM_LIT> ? V1Pack . getOperand ( <NUM_LIT> ) : V1Pack . getOperand ( <NUM_LIT> ) , Mask [ <NUM_LIT> ] == <NUM_LIT> ? V2Pack . getOperand ( <NUM_LIT> ) : V2Pack . getOperand ( <NUM_LIT> ) ) ) ; } if ( SDValue Shift = lowerVectorShuffleAsShift ( DL , <STR_LIT> , V1 , V2 , Mask , Zeroable , Subtarget , DAG ) ) return Shift ; if ( SDValue Insertion = lowerVectorShuffleAsElementInsertion ( DL , <STR_LIT> , V1 , V2 , Mask , Zeroable , Subtarget , DAG ) ) return Insertion ; int InverseMask [ <NUM_LIT> ] = { Mask [ <NUM_LIT> ] ^ <NUM_LIT> , Mask [ <NUM_LIT> ] ^ <NUM_LIT> } ; if ( SDValue Insertion = lowerVectorShuffleAsElementInsertion ( DL , <STR_LIT> , V2 , V1 , InverseMask , Zeroable , Subtarget , DAG ) ) return Insertion ; bool IsBlendSupported = Subtarget . hasSSE41 ( ) ; if ( IsBlendSupported ) if ( SDValue Blend = lowerVectorShuffleAsBlend ( DL , <STR_LIT> , V1 , V2 , Mask , Zeroable , Subtarget , DAG ) ) return Blend ; if ( SDValue V = lowerVectorShuffleWithUNPCK ( DL , <STR_LIT> , Mask , V1 , V2 , DAG ) ) return V ; if ( Subtarget . hasSSSE3 ( ) ) if ( SDValue Rotate = lowerVectorShuffleAsByteRotate ( DL , <STR_LIT> ,

V1 , V2 , Mask , Subtarget , DAG ) ) return Rotate ;


<s> MCOperand CallTargetMCOp ; unsigned CallOpcode ; switch ( CallTarget . getType ( ) ) { case MachineOperand :: MO_GlobalAddress : case MachineOperand :: MO_ExternalSymbol : CallTargetMCOp = MCIL . LowerSymbolOperand ( CallTarget , MCIL . GetSymbolFromOperand ( CallTarget ) ) ; CallOpcode = <STR_LIT> ; break ; case MachineOperand :: MO_Immediate : CallTargetMCOp = MCOperand :: createImm ( CallTarget . getImm ( ) ) ; CallOpcode = <STR_LIT> ; break ; case MachineOperand :: MO_Register : if ( Subtarget -> useRetpolineIndirectCalls ( ) ) report_fatal_error ( <STR_LIT> <STR_LIT> ) ; CallTargetMCOp = MCOperand :: createReg ( CallTarget . getReg ( ) ) ; CallOpcode = <STR_LIT> ; break ; default : llvm_unreachable ( <STR_LIT> ) ; break ; } MCInst CallInst ; CallInst . setOpcode ( CallOpcode ) ; CallInst . addOperand ( CallTargetMCOp ) ; OutStreamer -> EmitInstruction ( CallInst , getSubtargetInfo ( ) ) ; } auto & Ctx = OutStreamer -> getContext ( ) ; MCSymbol * MILabel = Ctx . createTempSymbol ( ) ; OutStreamer -> EmitLabel ( MILabel )


<s> for ( unsigned i = <NUM_LIT> , e = RVLocs . size ( ) ; i != e ; ++ i ) { CCValAssign & VA = RVLocs [ i ] ; if ( VA . getLocReg ( ) == <STR_LIT> || VA . getLocReg ( ) == <STR_LIT> ) return false ; } } if ( ! CCState :: resultsCompatible ( CalleeCC , CallerCC , MF , C , Ins , RetCC_<ISA_LIT> , RetCC_<ISA_LIT> ) ) return false ; const <ISA_LIT>RegisterInfo * TRI = Subtarget . getRegisterInfo ( ) ; const uint32_t * CallerPreserved = TRI -> getCallPreservedMask ( MF , CallerCC ) ; if ( ! CCMatch ) { const uint32_t * CalleePreserved = TRI -> getCallPreservedMask ( MF , CalleeCC ) ; if ( ! TRI -> regmaskSubsetEqual ( CallerPreserved , CalleePreserved ) ) return false ; } unsigned StackArgsSize = <NUM_LIT> ; if ( ! Outs . empty ( ) ) { SmallVector < CCValAssign , <NUM_LIT> > ArgLocs ; CCState CCInfo ( CalleeCC , isVarArg , MF , ArgLocs , C ) ; if ( IsCalleeWin64 ) CCInfo . AllocateStack ( <NUM_LIT> , Align ( <NUM_LIT> ) ) ; CCInfo . AnalyzeCallOperands ( Outs , CC_<ISA_LIT> ) ; StackArgsSize = CCInfo . getNextStackOffset ( ) ; if ( CCInfo . getNextStackOffset ( ) ) { MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const MachineRegisterInfo * MRI = & MF . getRegInfo ( ) ; const <ISA_LIT>InstrInfo * TII = Subtarget . getInstrInfo ( ) ; for ( unsigned i = <NUM_LIT> , e = ArgLocs . size ( ) ; i != e ; ++ i ) { CCValAssign & VA = ArgLocs [ i ] ; SDValue Arg = OutVals [ i ] ; <STR_LIT> Flags = Outs [ i ] . Flags ; if ( VA . getLocInfo ( ) == CCValAssign :: Indirect ) return false ; if ( ! VA . isRegLoc ( ) ) { if ( ! MatchingStackOffset ( Arg , VA . getLocMemOffset ( ) , Flags , MFI , MRI , TII , VA ) ) return false ; } } } bool PositionIndependent = isPositionIndependent ( ) ; if ( ! Subtarget . is64Bit ( ) && ( ( ! isa < GlobalAddressSDNode > ( Callee ) && ! isa < ExternalSymbolSDNode > ( Callee ) ) || PositionIndependent ) ) { unsigned NumInRegs = <NUM_LIT> ; unsigned MaxInRegs = PositionIndependent


<s> static void visium_function_arg_advance ( cumulative_args_t pcum_v , const function_arg_info & arg ) { int size = ( GET_MODE_SIZE ( arg . mode ) + UNITS_PER_WORD - <NUM_LIT> ) / UNITS_PER_WORD ; int stack_size = <NUM_LIT> ; CUMULATIVE_ARGS * ca = get_cumulative_args ( pcum_v ) ; if ( TARGET_FPU && ( ( GET_MODE_CLASS ( arg . mode ) == MODE_FLOAT && GET_MODE_SIZE ( arg . mode ) <= UNITS_PER_HWFPVALUE ) || ( GET_MODE_CLASS ( arg . mode ) == MODE_COMPLEX_FLOAT && GET_MODE_SIZE ( arg . mode ) <= UNITS_PER_HWFPVALUE * <NUM_LIT> ) ) ) { if ( ca -> frcount + size <= MAX_ARGS_IN_FP_REGISTERS ) ca -> frcount += size ; else { stack_size = size ; ca -> frcount = MAX_ARGS_IN_FP_REGISTERS ; } } else { if ( ca -> grcount + size <= MAX_ARGS_IN_GP_REGISTERS ) ca


<s> static bool pa_pass_by_reference ( cumulative_args_t ca ATTRIBUTE_UNUSED , machine_mode mode , const_tree type , bool named ATTRIBUTE_UNUSED ) { HOST_WIDE_INT size ; if ( type ) size = int_size_in_bytes ( type ) ; else size = GET_MODE_SIZE ( mode ) ; if ( TARGET_64BIT ) return


<s> switch ( Op . getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : return lowerATOMIC_FENCE ( Op , DAG ) ; case <STR_LIT> : return lowerBlockAddress ( Op , DAG ) ; case <STR_LIT> : return lowerConstantPool ( Op , DAG ) ; case <STR_LIT> : return lowerDYNAMIC_STACKALLOC ( Op , DAG ) ; case <STR_LIT> : return lowerGlobalAddress ( Op , DAG ) ; case <STR_LIT> : return lowerGlobalTLSAddress ( Op , DAG ) ; case <STR_LIT> : return lowerLOAD ( Op , DAG ) ; case <STR_LIT> : return lowerSTORE ( Op , DAG ) ; case <STR_LIT> : return lowerVASTART ( Op


<s> unsigned getInlineAsmMemConstraint ( const std :: string & ConstraintCode ) const override { if ( ConstraintCode == <STR_LIT> ) return


<s> return __arm_vrmlsldavhxq_s32 ( __a ,


<s> for ( ; ; ) { int t = get_jump_cycle ( n ) ; if ( t <= clock_var ) break ; retval = n ; n


<s> for ( auto & Op : MI . operands ( ) ) if ( Op . isGlobal ( ) || Op . isSymbol ( )


<s> size_t j = <NUM_LIT> ; uint64_t MergedSize = <NUM_LIT> ; std :: vector < Type * > Tys ; std :: vector < Constant * > Inits ; for ( j = i ; j != e ; ++ j ) { Type * Ty = Globals [ j ] -> getType ( ) -> getElementType ( ) ; MergedSize += TD -> getTypeAllocSize ( Ty ) ; if ( MergedSize > MaxOffset ) { break ; } Tys . push_back ( Ty ) ; Inits . push_back ( Globals [ j ] -> getInitializer ( ) ) ; } StructType * MergedTy = StructType :: get ( M . getContext ( ) , Tys ) ; Constant * MergedInit = ConstantStruct :: get ( MergedTy , Inits ) ; GlobalVariable * MergedGV = new GlobalVariable ( M , MergedTy , isConst , GlobalValue :: InternalLinkage , MergedInit , <STR_LIT> ) ; for ( size_t k = i ; k < j ; ++ k ) { Constant * Idx [ <NUM_LIT> ] = { ConstantInt :: get ( Int32Ty , <NUM_LIT> ) , ConstantInt :: get ( Int32Ty , k - i ) } ; Constant * GEP = ConstantExpr :: getInBoundsGetElementPtr ( MergedGV , Idx ) ; Globals [ k ] -> replaceAllUsesWith ( GEP


<s> bool <ISA_LIT>BaseRegisterInfo :: canSimplifyCallFramePseudos ( MachineFunction & MF ) const { return hasReservedCallFrame ( MF ) || MF . getFrameInfo ( ) -> hasVarSizedObjects


<s> if ( dwarf_regs_mask & ( <NUM_LIT> << i ) ) num_dwarf_regs ++ ; } gcc_assert ( num_regs && num_regs <= <NUM_LIT> ) ; gcc_assert ( ( dwarf_regs_mask & ~ mask ) == <NUM_LIT> ) ; par = gen_rtx_PARALLEL ( VOIDmode , rtvec_alloc ( num_regs ) ) ; dwarf = gen_rtx_SEQUENCE ( VOIDmode , rtvec_alloc ( num_dwarf_regs + <NUM_LIT> ) ) ; dwarf_par_index = <NUM_LIT> ; for ( i = <NUM_LIT> ; i <= LAST_ARM_REGNUM ; i ++ ) { if ( mask & ( <NUM_LIT> << i ) ) { reg = gen_rtx_REG ( SImode , i ) ; XVECEXP ( par , <NUM_LIT> , <NUM_LIT> ) = gen_rtx_SET ( gen_frame_mem ( BLKmode , gen_rtx_PRE_MODIFY ( Pmode , stack_pointer_rtx , plus_constant ( Pmode , stack_pointer_rtx , - <NUM_LIT> * num_regs ) ) ) , gen_rtx_UNSPEC ( BLKmode , gen_rtvec ( <NUM_LIT> , reg ) , UNSPEC_PUSH_MULT ) ) ; if ( dwarf_regs_mask & ( <NUM_LIT> << i ) ) { tmp = gen_rtx_SET ( gen_frame_mem ( SImode , stack_pointer_rtx ) , reg ) ; RTX_FRAME_RELATED_P ( tmp ) = <NUM_LIT> ; XVECEXP ( dwarf , <NUM_LIT> , dwarf_par_index ++ ) = tmp ; } break ; } } for ( j = <NUM_LIT> , i ++ ; j < num_regs ; i ++ ) { if ( mask & ( <NUM_LIT> << i ) ) { reg = gen_rtx_REG ( SImode , i ) ; XVECEXP ( par , <NUM_LIT> , j ) = gen_rtx_USE ( VOIDmode , reg ) ; if ( dwarf_regs_mask & ( <NUM_LIT> << i ) ) { tmp = gen_rtx_SET ( gen_frame_mem ( SImode , plus_constant ( Pmode , stack_pointer_rtx , <NUM_LIT> * j ) ) , reg ) ; RTX_FRAME_RELATED_P ( tmp ) = <NUM_LIT> ; XVECEXP ( dwarf , <NUM_LIT> , dwarf_par_index ++ ) = tmp ; } j ++


<s> if ( RC1 [ B1 + i ] . Type == BitTracker :: BitValue :: Ref && RC1 [ B1 + i ] . RefI . Reg == <NUM_LIT> ) return false ; if ( RC2 [ B2 + i ] . Type == BitTracker :: BitValue :: Ref && RC2 [ B2 + i ] . RefI . Reg == <NUM_LIT> ) return false ; if ( RC1 [ B1 + i ] != RC2 [ B2 + i ] ) return false ; } return true


<s> delete static_cast < <ISA_LIT>Section * > ( LSDASection ) ; delete static_cast < <ISA_LIT>Section * > ( EHFrameSection ) ; delete static_cast < <ISA_LIT>Section * > ( DwarfAbbrevSection ) ; delete static_cast < <ISA_LIT>Section * > ( DwarfInfoSection ) ; delete static_cast < <ISA_LIT>Section * > ( DwarfLineSection ) ; delete static_cast < <ISA_LIT>Section * > ( DwarfFrameSection ) ; delete static_cast < <ISA_LIT>Section * > ( DwarfPubTypesSection ) ; delete static_cast < const <ISA_LIT>Section * > ( DwarfDebugInlineSection ) ; delete static_cast < <ISA_LIT>Section * > ( DwarfStrSection ) ; delete static_cast < <ISA_LIT>Section * > ( DwarfLocSection ) ; delete static_cast < <ISA_LIT>Section * > ( DwarfARangesSection ) ; delete static_cast < <ISA_LIT>Section * > ( DwarfRangesSection ) ; delete static_cast < <ISA_LIT>Section * > (


<s> case SYMBOL_TLS_IE : case SYMBOL_TLS_LE : return <NUM_LIT> ; case SYMBOL_TLSGD : case SYMBOL_TLSLDM : return <NUM_LIT> ; case SYMBOL_PCREL64 : return <NUM_LIT> ; case


<s> MVT EltVT = VT . getVectorElementType ( ) . getSimpleVT ( ) ; EVT NewVT = <STR_LIT> ( EltVT , NumElems / <NUM_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , VT , DAG . getNode ( Op . getOpcode ( ) , dl , NewVT , LHS1 , RHS1 , CC ) , DAG . getNode ( Op . getOpcode ( ) ,


<s> MachineBasicBlock :: iterator <ISA_LIT>FrameLowering :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { assert ( ! I -> getOperand ( <NUM_LIT> ) . getImm ( ) && hasFP ( MF ) && <STR_LIT> ) ; const auto * TII = MF . getSubtarget < <ISA_LIT>Subtarget > ( )


<s> void <ISA_LIT>InstPrinter :: printAM2PreOrOffsetIndexOp ( const MCInst * MI , unsigned Op , raw_ostream & O ) { const MCOperand & MO1 = MI -> getOperand ( Op ) ; const MCOperand & MO2 = MI -> getOperand ( Op + <NUM_LIT> ) ; const MCOperand & MO3 = MI -> getOperand ( Op + <NUM_LIT> ) ; O << <STR_LIT> << getRegisterName ( MO1 . getReg ( ) ) ; if ( ! MO2 . getReg ( ) ) { if ( <STR_LIT> ( MO3 . getImm ( ) ) ) O << <STR_LIT> << <STR_LIT> ( <STR_LIT> ( MO3 . getImm ( ) ) ) << <STR_LIT> ( MO3 . getImm ( ) ) ; O << <STR_LIT>


<s> default : return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : unsigned Width ; return getMemOpBaseRegImmOfsWidth ( LdSt , BaseReg , Offset , Width


<s> if ( WinEH :: FrameInfo * CurFrame = getCurrentWinFrameInfo ( )

) EHStreamer . EmitUnwindInfo ( * this , CurFrame ) ;


<s> MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; <ISA_LIT>MachineFunctionInfo * FuncInfo = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; const bool SpillVGPRToAGPR = ST . hasMAIInsts ( ) && FuncInfo -> hasSpilledVGPRs ( ) && EnableSpillVGPRToAGPR ; if ( SpillVGPRToAGPR ) { BitVector SpillFIs ( MFI . getObjectIndexEnd ( ) , false ) ; bool SeenDbgInstr = false ; for ( MachineBasicBlock & MBB : MF ) { MachineBasicBlock :: iterator Next ; for ( auto I = MBB . begin ( ) , E = MBB . end ( ) ; I != E ; I = Next ) { MachineInstr & MI = * I ; Next = std :: next ( I ) ; if ( MI . isDebugInstr ( ) ) SeenDbgInstr = true ; if ( TII -> isVGPRSpill ( MI ) ) { unsigned FIOp = <STR_LIT> ( MI . getOpcode ( ) , <STR_LIT> :: vaddr ) ; int FI = MI . getOperand ( FIOp ) . getIndex ( ) ; Register VReg = TII -> getNamedOperand ( MI , <STR_LIT> :: vdata ) -> getReg ( ) ; if ( FuncInfo -> allocateVGPRSpillToAGPR ( MF , FI , TRI -> isAGPR ( MRI , VReg ) ) ) { RS -> enterBasicBlock ( MBB ) ; TRI -> eliminateFrameIndex ( MI , <NUM_LIT> , FIOp , RS ) ; SpillFIs . set ( FI ) ; continue ; } } } } for ( MachineBasicBlock & MBB : MF


<s> if ( Val -> getType ( ) -> getPrimitiveSizeInBits ( ) == <NUM_LIT> ) { <STR_LIT> Int = IsRelease ? <STR_LIT> : <STR_LIT> ; Function * Strex = <STR_LIT> ( M , Int ) ; Type * Int32Ty = Type :: getInt32Ty ( M -> getContext ( ) ) ; Value * Lo = Builder . CreateTrunc ( Val , Int32Ty , <STR_LIT> ) ; Value * Hi = Builder . CreateTrunc ( Builder . CreateLShr ( Val , <NUM_LIT> ) , Int32Ty , <STR_LIT> ) ; if ( ! Subtarget -> isLittle ( ) ) std


<s> SDValue PackedOp = Op . getOperand ( <NUM_LIT> ) ; EVT OutVT = Op . getValueType ( ) ; EVT InVT = PackedOp . getValueType ( ) ; unsigned ToBits = OutVT . getVectorElementType ( ) . getSizeInBits (


<s> const <ISA_LIT>TargetLowering & TLI = * getTLI < <ISA_LIT>TargetLowering > ( ) ; CCAssignFn * AssignFnFixed ; CCAssignFn * AssignFnVarArg ; std :: tie ( AssignFnFixed , AssignFnVarArg ) = getAssignFnsForCC ( CalleeCC , TLI ) ; SmallVector < CCValAssign , <NUM_LIT> > OutLocs ; CCState OutInfo ( CalleeCC , false , MF , OutLocs , CallerF . getContext ( ) ) ; if ( ! analyzeArgInfo ( OutInfo , OutArgs , * AssignFnFixed , * AssignFnVarArg ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } const <ISA_LIT>FunctionInfo * FuncInfo = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; if ( OutInfo . getNextStackOffset ( ) > FuncInfo -> getBytesInStackArgArea ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } auto TRI = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getRegisterInfo ( ) ; const uint32_t * CallerPreservedMask = TRI -> getCallPreservedMask ( MF , CallerCC ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; if ( Info . IsVarArg ) { for ( unsigned i = <NUM_LIT> ; i < OutLocs . size ( ) ; ++ i ) { auto & ArgLoc = OutLocs


<s> if ( CSI . empty ( ) ) return false ; MachineFunction & MF = * MBB . getParent ( ) ; <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; bool isVarArg = AFI -> getArgRegsSaveSize ( ) > <NUM_LIT> ; unsigned NumAlignedDPRCS2Regs = AFI -> getNumAlignedDPRCS2Regs ( ) ; if ( NumAlignedDPRCS2Regs ) emitAlignedDPRCS2Restores ( MBB , MI , NumAlignedDPRCS2Regs , CSI , TRI ) ; unsigned PopOpc = AFI -> isThumbFunction ( ) ? <STR_LIT> : <STR_LIT> ; unsigned LdrOpc = AFI -> isThumbFunction ( ) ? <STR_LIT> : <STR_LIT> ; unsigned FltOpc = <STR_LIT> ; emitPopInst ( MBB , MI , CSI , FltOpc , <NUM_LIT> , isVarArg , true , & is<ISA_LIT>Area3Register , NumAlignedDPRCS2Regs ) ; emitPopInst ( MBB , MI , CSI , PopOpc , LdrOpc , isVarArg , false , & is<ISA_LIT>Area2Register , <NUM_LIT> ) ; emitPopInst ( MBB , MI , CSI , PopOpc , LdrOpc , isVarArg , false

, & is<ISA_LIT>Area1Register , <NUM_LIT> ) ;


<s> Op -> RegShiftedReg . SrcReg = SrcReg ; Op -> RegShiftedReg . ShiftReg = ShiftReg ; Op -> RegShiftedReg . ShiftImm = ShiftImm ; Op -> StartLoc = S ; Op -> EndLoc =


<s> dc = vec_sel ( vec_sub ( bc , ac ) , vec_sub ( ac , bc ) , vec_cmpgt ( ac , bc ) ) ; return ( ( qword ) ( dc


<s> MachineRegisterInfo & MRI = MBB . getParent ( ) -> getRegInfo ( ) ; MachineBasicBlock :: iterator MII = Inst ; DebugLoc DL = Inst -> getDebugLoc ( ) ; MachineOperand & Dest = Inst -> getOperand ( <NUM_LIT> ) ; MachineOperand & Src = Inst -> getOperand ( <NUM_LIT> ) ; const MCInstrDesc & InstDesc = get ( <STR_LIT> ) ; const TargetRegisterClass * SrcRC = Src . isReg ( ) ? MRI . getRegClass ( Src . getReg ( ) ) : & <STR_LIT> ; unsigned MidReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; unsigned ResultReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; const TargetRegisterClass * SrcSubRC = RI . getSubRegClass ( SrcRC , <STR_LIT> ) ; MachineOperand SrcRegSub0 = buildExtractSubRegOrImm ( MII , MRI , Src , SrcRC , <STR_LIT> , SrcSubRC ) ; MachineOperand SrcRegSub1 = buildExtractSubRegOrImm ( MII , MRI , Src , SrcRC , <STR_LIT> , SrcSubRC ) ; BuildMI ( MBB , MII , DL , InstDesc , MidReg ) . addOperand ( SrcRegSub0 ) . addImm ( <NUM_LIT> ) ; BuildMI ( MBB , MII , DL , InstDesc , ResultReg ) . addOperand ( SrcRegSub1 ) . addReg ( MidReg ) ; MRI . replaceRegWith ( Dest . getReg ( ) , ResultReg ) ; addUsersToMoveToVALUWorklist ( ResultReg , MRI , Worklist


<s> const GCNSubtarget & ST = DAG . getMachineFunction ( ) . getSubtarget < GCNSubtarget > ( ) ; int64_t OffsetVal = <NUM_LIT> ; if ( ST . hasFlatInstOffsets ( ) && ( ! ST . hasFlatSegmentOffsetBug ( ) || findMemSDNode ( N ) -> getAddressSpace ( ) != <ISA_LIT>AS :: FLAT_ADDRESS ) && DAG . isBaseWithConstantOffset ( Addr ) ) { SDValue N0 = Addr . getOperand ( <NUM_LIT> ) ; SDValue N1 = Addr . getOperand ( <NUM_LIT> ) ; int64_t COffsetVal = cast < ConstantSDNode > ( N1 ) -> getSExtValue ( ) ; if ( ST . getGeneration ( ) >= <ISA_LIT>Subtarget :: GFX10 ) { if ( ( IsSigned && isInt < <NUM_LIT> > ( COffsetVal ) ) || ( ! IsSigned && isUInt < <NUM_LIT> > ( COffsetVal ) ) ) { Addr = N0 ; OffsetVal = COffsetVal ; } } else { if ( ( IsSigned && isInt < <NUM_LIT> > ( COffsetVal ) ) || ( ! IsSigned && isUInt < <NUM_LIT> > ( COffsetVal ) ) ) { Addr = N0 ; OffsetVal = COffsetVal ; } } } VAddr = Addr ; Offset = DAG . getTargetConstant ( OffsetVal , SDLoc ( ) , <STR_LIT> ) ; SLC = DAG . getTargetConstant ( <NUM_LIT> , SDLoc


<s> void <ISA_LIT>MCExpr :: visitUsedExpr ( MCStreamer & Streamer ) const { Streamer . visitUsedExpr ( * getSubExpr


<s> Modified = false ; for ( MachineLoop * I : LI ) for ( auto L = df_begin ( I ) , LE = df_end ( I ) ; L != LE ; ++ L ) if ( L -> empty (


<s> uint64_t getStackValueStoreSize ( const DataLayout & , const CCValAssign & VA


<s> case <STR_LIT> : return LowerFRAMEADDR ( Op , DAG ) ; case <STR_LIT> : return LowerRETURNADDR ( Op , DAG ) ; case <STR_LIT> : return LowerINSERT_VECTOR_ELT ( Op , DAG ) ; case <STR_LIT> : return LowerEXTRACT_VECTOR_ELT ( Op , DAG ) ; case <STR_LIT> : return LowerBUILD_VECTOR ( Op , DAG ) ; case <STR_LIT> : return LowerVECTOR_SHUFFLE ( Op , DAG ) ; case <STR_LIT> : return LowerEXTRACT_SUBVECTOR ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerVectorSRA_SRL_SHL ( Op , DAG ) ; case <STR_LIT> : return LowerShiftLeftParts ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerShiftRightParts ( Op , DAG ) ; case <STR_LIT> : return LowerCTPOP ( Op , DAG ) ; case <STR_LIT> : return LowerFCOPYSIGN ( Op , DAG ) ; case <STR_LIT> : return LowerVectorAND ( Op , DAG ) ; case <STR_LIT> : return LowerVectorOR ( Op , DAG ) ; case <STR_LIT> : return LowerXOR ( Op , DAG ) ; case <STR_LIT> : return LowerPREFETCH ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerINT_TO_FP ( Op , DAG ) ; case <STR_LIT> : case


<s> return ( uint16x8_t ) __builtin_neon_vld1_dupv8hi ( ( const


<s> if ( regno == RETURN_ADDR_REGNUM ) return true ; if ( epilogue_completed && cfun -> machine -> interrupt_handler_p ) { if ( df_regs_ever_live_p ( regno ) || ( ! crtl -> is_leaf && call_used_or_fixed_reg_p (


<s> } else if ( Op0 -> getMachineOpcode ( ) == <STR_LIT> ) { if ( idx != <STR_LIT> ) return SDValue ( ) ; idx = <NUM_LIT> ; } if ( Op0 -> getOperand ( <NUM_LIT> ) -> getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; SDValue Source = Op0 -> getOperand ( <NUM_LIT> ) -> getOperand ( <NUM_LIT> ) ; EVT SVT = Source -> getValueType ( <NUM_LIT> ) ; if ( ! SVT . isVector ( ) || SVT . getVectorNumElements ( ) != VT . getVectorNumElements ( ) * <NUM_LIT> ) return SDValue ( ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; SDLoc dl ( N ) ; unsigned NumElements = VT . getVectorNumElements ( ) ; if ( idx ) { SDValue HalfIdx = DAG . getConstant ( NumElements , dl , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl


<s> for ( unsigned opNum = <NUM_LIT> ; opNum < PacketMI -> getNumOperands ( ) ; opNum ++ ) { if ( PacketMI -> getOperand ( opNum ) . isReg ( ) ) predRegNumSrc = PacketMI -> getOperand ( opNum ) . getReg ( ) ; predRegClass = QRI -> getMinimalPhysRegClass ( predRegNumSrc ) ; if ( predRegClass == & <STR_LIT> ) { break ; } } assert ( ( predRegClass == & <STR_LIT> ) && ( <STR_LIT> ) ) ; for ( unsigned opNum = <NUM_LIT> ; opNum < MI -> getNumOperands ( ) ; opNum ++ ) { if ( MI -> getOperand ( opNum ) . isReg ( ) ) predRegNumDst = MI -> getOperand ( opNum ) . getReg ( ) ; predRegClass = QRI -> getMinimalPhysRegClass ( predRegNumDst ) ; if ( predRegClass == & <STR_LIT> ) { break ; } } assert ( ( predRegClass == & <STR_LIT> ) && ( <STR_LIT> ) ) ; if ( ( predRegNumDst != predRegNumSrc ) || QII -> isDotNewInst ( PacketMI ) != QII -> isDotNewInst ( MI ) || getPredicateSense ( MI , QII ) != getPredicateSense ( PacketMI , QII ) ) { return false ; } } std :: vector < MachineInstr * > :: iterator VI ; std :: vector < MachineInstr * > :: iterator VE ; unsigned StartCheck = <NUM_LIT> ; for ( VI = CurrentPacketMIs . begin ( ) , VE = CurrentPacketMIs . end ( ) ; ( VI != VE ) ; ++ VI ) { SUnit * TempSU = MIToSUnit . find ( * VI ) -> second ; MachineInstr * TempMI = TempSU -> getInstr ( ) ; if ( TempMI != PacketMI && ! StartCheck ) continue ; StartCheck = <NUM_LIT> ; if ( TempMI == PacketMI ) continue ; for ( unsigned opNum = <NUM_LIT> ; opNum < MI -> getNumOperands ( ) ; opNum


<s> RegisterRef RR = { I -> first , <NUM_LIT> } ; uint16_t PhiFlags = NodeAttrs :: PhiRef | NodeAttrs :: Preserving ; NodeAddr < DefNode * > DA = newDef ( PA , RR , PhiFlags ) ; PA . Addr -> addMember ( DA , * this ) ; } BlockRefsMap PhiM ; auto Blocks = Func . Addr -> members ( * this ) ; for ( NodeAddr < BlockNode * > BA : Blocks

) recordDefsForDF ( PhiM , RefM , BA ) ;


<s> assert ( User && <STR_LIT> ) ; if ( User -> getOpcode ( ) != Instruction :: FSub && User -> getOpcode ( ) != Instruction :: FAdd ) return true ; const TargetOptions & Options = getTargetMachine ( ) . Options ; const Function * F = I -> getFunction ( ) ; const DataLayout & DL = F -> getParent ( ) ->


<s> rtx mmix_return_addr_rtx ( int count , rtx frame ATTRIBUTE_UNUSED ) { return count == <NUM_LIT> ? ( MMIX_CFUN_NEEDS_SAVED_EH_RETURN_ADDRESS ? validize_mem ( gen_rtx_MEM ( Pmode , plus_constant ( frame_pointer_rtx , - <NUM_LIT> ) ) )

: get_hard_reg_initial_val ( Pmode , MMIX_INCOMING_RETURN_ADDRESS_REGNUM ) ) : NULL_RTX ;


<s> static StringRef get_amd_kernel_code_t_FieldName ( int index ) { return get_amd_kernel_code_t_FldNames ( ) [


<s> for ( ; R . isValid ( ) ; ++ R ) Reserved . set (


<s> unsigned getPointerSize ( ) const { StringRef Name = TheTarget . getName ( ) ; if ( Name == <STR_LIT> ) return <NUM_LIT> ; assert ( Name == <STR_LIT> && <STR_LIT> ) ; return <NUM_LIT>


<s> for ( auto * Val : DeletionSet ) { SmallVector < User * , <NUM_LIT> > Users ; PopulateEraseUsers ( Val , Users ) ; Users . push_back


<s> unsigned SplatBitSize ; bool HasAnyUndefs ; if ( ! Node -> isConstantSplat ( SplatValue , SplatUndef , SplatBitSize , HasAnyUndefs , <NUM_LIT> , ! Subtarget . isLittle ( ) ) ) return false ; Imm = SplatValue ; return true


<s> bool ok_for_simple_arith_logic_operands ( rtx * , enum machine_mode ) { return ! visium_flags_exposed


<s> static MCStreamer * create<ISA_LIT>MCStreamer ( const Target & T , StringRef TT , MCContext & Ctx , MCAsmBackend & MAB , raw_ostream & _OS , MCCodeEmitter * _Emitter , bool RelaxAll , bool NoExecStack ) { return createELFStreamer ( Ctx , <NUM_LIT> , MAB , _OS , _Emitter , RelaxAll , NoExecStack ) ; return createELFStreamer ( Ctx , MAB , _OS , _Emitter , RelaxAll


<s> case E_DImode : case E_SFmode : case E_DFmode : if ( ! reload_in_progress && ! reload_completed && ! register_operand ( dest , mode ) && ! reg_or_0_operand ( src , mode ) ) src = copy_to_mode_reg ( mode , src ) ; break ; default : gcc_unreachable (


<s> MachineBasicBlock :: iterator PI = doMergeWithPrevious ? std :: prev ( MBBI ) : MBBI ; MachineBasicBlock :: iterator NI = doMergeWithPrevious ? nullptr : std :: next ( MBBI ) ; unsigned Opc = PI -> getOpcode ( ) ; int Offset = <NUM_LIT> ; if ( ( Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ) && PI -> getOperand ( <NUM_LIT> ) . getReg ( ) == StackPtr ) { Offset += PI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; MBB . erase ( PI ) ; if ( ! doMergeWithPrevious ) MBBI =


<s> bool <ISA_LIT>DAGToDAGISel :: isFlatStore (


<s> if ( ! isShiftOrExtend ( ) ) return false ; <STR_LIT> Ext = ShiftExtend . ShiftType ; if ( RmSize == <NUM_LIT> && ! ( Ext == <STR_LIT> || Ext == <STR_LIT> ) ) return false ; if ( RmSize == <NUM_LIT> && ! ( Ext == <STR_LIT> || Ext == <STR_LIT> ) ) return false ; return ShiftExtend . Amount == Log2_32 ( MemSize ) || ShiftExtend .


<s> SDValue Ext = ! V . isUndef ( ) ? DAG . getZExtOrTrunc ( V , dl , <STR_LIT> ) : DAG . getUNDEF ( <STR_LIT> ) ; for ( unsigned B = <NUM_LIT> ; B != BitBytes ; ++ B ) Bytes . push_back ( Ext ) ; } } else { for ( unsigned I = <NUM_LIT> ; I != VecLen ; I += <NUM_LIT> ) { unsigned B = <NUM_LIT> ; for ( ; B != <NUM_LIT> ; ++ B ) { if ( ! Values [ I + B ] . isUndef ( ) ) break ; } SDValue F = Values [ I + B ] ; AllT &= IsTrue ( F ) ; AllF &= IsFalse ( F ) ; SDValue Ext = ( B < <NUM_LIT> ) ? DAG . getZExtOrTrunc ( F , dl , <STR_LIT> ) : DAG . getUNDEF ( <STR_LIT> ) ; Bytes . push_back ( Ext ) ; for ( ; B != <NUM_LIT> ; ++ B ) assert ( Values [ I + B ] . isUndef ( ) || Values [ I + B ] == F ) ; } } if ( AllT ) return DAG . getNode ( <STR_LIT> , dl , VecTy ) ; if ( AllF ) return DAG . getNode ( <STR_LIT> , dl , VecTy ) ; MVT ByteTy = <STR_LIT> ( <STR_LIT> ,


<s> uint8x16_t result ; __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) ,


<s> switch ( E -> getKind ( ) ) { case MCExpr :: Target : case MCExpr :: Constant : return nullptr ; case MCExpr :: SymbolRef : { const MCSymbolRefExpr * SRE = cast < MCSymbolRefExpr > ( E ) ; switch ( SRE -> getKind ( ) ) { case MCSymbolRefExpr :: VK_<ISA_LIT>_LO : Variant = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_LO ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_HI : Variant = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_HI ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_HA : Variant = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_HA ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_HIGHER : Variant = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_HIGHER ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_HIGHERA : Variant = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_HIGHERA ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_HIGHEST : Variant = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_HIGHEST ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_HIGHESTA : Variant = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_HIGHESTA ; break ; default : return nullptr ; } return MCSymbolRefExpr :: create ( & SRE -> getSymbol ( ) , Context ) ; } case MCExpr :: Unary : { const MCUnaryExpr * UE = cast < MCUnaryExpr > ( E ) ; const MCExpr * Sub = ExtractModifierFromExpr ( UE -> getSubExpr ( ) , Variant ) ; if ( ! Sub ) return nullptr ; return MCUnaryExpr :: create ( UE -> getOpcode ( ) , Sub , Context ) ; } case MCExpr :: Binary : { const MCBinaryExpr * BE = cast < MCBinaryExpr > ( E ) ; <ISA_LIT>MCExpr :: VariantKind LHSVariant , RHSVariant ; const MCExpr * LHS = ExtractModifierFromExpr ( BE -> getLHS ( ) , LHSVariant ) ; const MCExpr * RHS = ExtractModifierFromExpr ( BE -> getRHS ( ) , RHSVariant ) ; if ( ! LHS && ! RHS ) return nullptr ; if ( ! LHS ) LHS = BE -> getLHS ( ) ; if ( ! RHS ) RHS = BE ->


<s> return ( __m128i ) __builtin_ia32_pmovsqb128_mask ( ( __v2di ) __A , ( __v16qi ) _mm_undefined_si128 ( ) , ( __mmask8


<s> IRB . SetInsertPoint ( CI ) ; Value * Env = IRB . CreatePtrToInt ( CI -> getArgOperand ( <NUM_LIT> ) , getAddrIntType ( M ) , <STR_LIT> ) ; IRB . CreateCall ( EmLongjmpF , { Env , CI -> getArgOperand ( <NUM_LIT> ) } ) ; ToErase . push_back ( CI ) ; } } for ( auto * I : ToErase ) I -> eraseFromParent


<s> return true ; } } if ( AllowFloatDomain && EltSizeInBits == <NUM_LIT> && ( ( MaskVT . is128BitVector ( ) && Subtarget . hasSSE2 ( ) ) || ( MaskVT . is256BitVector ( ) && Subtarget . hasAVX ( ) ) || ( MaskVT . is512BitVector ( ) && Subtarget . hasAVX512 ( ) ) ) ) { if ( matchShuffleWithSHUFPD ( MaskVT , V1 , V2 , PermuteImm , Mask ) ) { Shuffle = <STR_LIT> ; ShuffleVT = <STR_LIT> ( <STR_LIT> , MaskVT . getSizeInBits ( ) / <NUM_LIT> ) ; return true ; } } if ( AllowFloatDomain && EltSizeInBits == <NUM_LIT> && ( ( MaskVT . is128BitVector ( ) && Subtarget . hasSSE1 ( ) ) || ( MaskVT . is256BitVector ( ) && Subtarget . hasAVX ( ) ) || ( MaskVT . is512BitVector ( ) && Subtarget . hasAVX512 ( ) ) ) ) { SmallVector < int , <NUM_LIT> > RepeatedMask ; if ( isRepeatedTargetShuffleMask ( <NUM_LIT> , MaskVT , Mask , RepeatedMask ) ) { auto MatchHalf = [ & ] ( unsigned Offset , int & S0 , int & S1 ) { int M0 = RepeatedMask [ Offset ] ; int M1 = RepeatedMask [ Offset + <NUM_LIT> ] ; if ( isUndefInRange ( RepeatedMask , Offset , <NUM_LIT> ) ) { return DAG . getUNDEF ( MaskVT ) ; } else if ( isUndefOrZeroInRange ( RepeatedMask , Offset , <NUM_LIT> ) ) { S0 = ( SM_SentinelUndef == M0 ? - <NUM_LIT> : <NUM_LIT> ) ; S1 = ( SM_SentinelUndef == M1 ? - <NUM_LIT> : <NUM_LIT> ) ; return getZeroVector ( MaskVT , Subtarget , DAG , DL ) ; } else if ( isUndefOrInRange ( M0 , <NUM_LIT> , <NUM_LIT> ) && isUndefOrInRange ( M1 , <NUM_LIT> , <NUM_LIT> ) ) { S0 = ( SM_SentinelUndef == M0 ? - <NUM_LIT> : M0 & <NUM_LIT> ) ; S1 = ( SM_SentinelUndef == M1 ? - <NUM_LIT> : M1 & <NUM_LIT> ) ; return V1 ; } else if ( isUndefOrInRange ( M0 , <NUM_LIT> , <NUM_LIT> ) && isUndefOrInRange ( M1 , <NUM_LIT> , <NUM_LIT> ) ) { S0 = ( SM_SentinelUndef == M0 ? - <NUM_LIT> : M0 & <NUM_LIT> ) ; S1 = ( SM_SentinelUndef == M1 ? - <NUM_LIT> : M1 & <NUM_LIT> ) ; return V2 ; } return SDValue ( ) ; } ; int ShufMask [ <NUM_LIT> ] = { - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> } ; SDValue Lo = MatchHalf ( <NUM_LIT> , ShufMask [ <NUM_LIT> ] , ShufMask [ <NUM_LIT> ] ) ; SDValue Hi = MatchHalf ( <NUM_LIT> , ShufMask [ <NUM_LIT> ] , ShufMask [ <NUM_LIT> ] ) ; if ( Lo && Hi ) { V1 = Lo ; V2 = Hi ; Shuffle = <STR_LIT> ; ShuffleVT = <STR_LIT> ( <STR_LIT> , MaskVT . getSizeInBits ( ) / <NUM_LIT> ) ; PermuteImm = getV4<ISA_LIT>ShuffleImm ( ShufMask ) ; return true ; } } } return false


<s> unsigned <ISA_LIT>TTI :: getMaximumUnrollFactor ( ) const { if ( ST -> isCortexA57 ( ) || ST -> isCyclone (


<s> FunctionPass * llvm :: create<ISA_LIT>ExpandPseudoPass ( ) { return new <ISA_LIT>ExpandPseudo


<s> const char * getPassName ( ) const { return <STR_LIT>


<s> Inst . addOperand ( MCOperand :: createImm ( SignExtend64 < N > ( Imm << <NUM_LIT> ) ) ) ; return MCDisassembler


<s> const <ISA_LIT>MachineFunctionInfo * MFI = B . getMF ( ) . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; if ( ! MFI -> isEntryFunction ( ) ) { return legalizePreloadedArgIntrin ( MI , MRI , B , <STR_LIT> ) ; } Register DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( ! getImplicitArgPtr ( DstReg , MRI , B ) ) return false ; MI . eraseFromParent ( ) ; return true


<s> OperandMatchResultTy <ISA_LIT>AsmParser :: parseDim ( OperandVector & Operands ) { if ( ! isGFX10Plus ( ) ) return MatchOperand_NoMatch ; SMLoc S = getLoc ( ) ; if ( ! trySkipId ( <STR_LIT> , AsmToken :: Colon ) ) return MatchOperand_NoMatch ; unsigned Encoding ; SMLoc Loc = getLoc ( ) ; if ( ! parseDimId ( Encoding ) ) { Error ( Loc , <STR_LIT> ) ; return MatchOperand_ParseFail


<s> if ( Subtarget -> has<ISA_LIT>64 ( ) && ( Op . getValueType ( ) == <STR_LIT> ) ) return

LowerFABS64 ( Op , DAG , Subtarget -> has<ISA_LIT>32r2 ( ) ) ;


<s> if ( ! SrcEVT . isSimple ( ) ) return false ; MVT SrcVT = SrcEVT . getSimpleVT ( ) ; if ( SrcVT == <STR_LIT> && Subtarget -> useCRBits ( ) ) return false ; long Imm = <NUM_LIT> ; bool UseImm = false ; const bool HasSPE = Subtarget -> hasSPE ( ) ; if ( const ConstantInt * ConstInt = dyn_cast < ConstantInt > ( SrcValue2 ) ) { if ( SrcVT == <STR_LIT> || SrcVT == <STR_LIT> || SrcVT == <STR_LIT> || SrcVT == <STR_LIT> || SrcVT == <STR_LIT> ) { const APInt & CIVal = ConstInt -> getValue ( ) ; Imm = ( IsZExt ) ? ( long ) CIVal . getZExtValue ( ) : ( long ) CIVal . getSExtValue ( ) ; if ( ( IsZExt && isUInt < <NUM_LIT> > ( Imm ) ) || ( ! IsZExt && isInt < <NUM_LIT> > ( Imm ) ) ) UseImm = true ; } } unsigned SrcReg1 = getRegForValue ( SrcValue1 ) ; if ( SrcReg1 == <NUM_LIT> ) return false ; unsigned SrcReg2 = <NUM_LIT> ; if ( ! UseImm ) { SrcReg2 = getRegForValue ( SrcValue2 ) ; if ( SrcReg2 == <NUM_LIT> ) return false ; } unsigned CmpOpc ; bool NeedsExt = false ; auto RC1 = MRI . getRegClass ( SrcReg1 ) ; auto RC2 = SrcReg2 != <NUM_LIT> ? MRI . getRegClass ( SrcReg2 ) : nullptr ; switch ( SrcVT . SimpleTy ) { default : return false ; case <STR_LIT> : if ( HasSPE ) { switch ( Pred ) { default : return false ; case <STR_LIT> : CmpOpc = <STR_LIT> ; break ; case <STR_LIT> : CmpOpc = <STR_LIT> ; break ; case <STR_LIT> : CmpOpc = <STR_LIT> ; break ; } } else { CmpOpc = <STR_LIT> ; if ( isVSSRCRegClass ( RC1 ) ) SrcReg1 = copyRegToRegClass ( & <STR_LIT> , SrcReg1 ) ; if ( RC2 && isVSSRCRegClass ( RC2 ) ) SrcReg2 = copyRegToRegClass ( & <STR_LIT> , SrcReg2 ) ; } break ; case <STR_LIT> : if ( HasSPE ) { switch ( Pred ) { default : return false ; case <STR_LIT> : CmpOpc = <STR_LIT> ; break ; case <STR_LIT> : CmpOpc = <STR_LIT> ; break ; case <STR_LIT> : CmpOpc = <STR_LIT> ; break ; } } else if ( isVSFRCRegClass ( RC1 ) || ( RC2 && isVSFRCRegClass ( RC2 ) ) ) { CmpOpc = <STR_LIT> ; } else { CmpOpc = <STR_LIT> ; } break ; case <STR_LIT> : case


<s> bool <ISA_LIT>SEFrameLowering :: hasReservedCallFrame ( const MachineFunction & MF ) const { const MachineFrameInfo * MFI = MF .


<s> bool IsLogical = ( Compare -> getDesc ( ) . TSFlags & <STR_LIT> ) != <NUM_LIT> ; if ( Value == <NUM_LIT> && ! IsLogical && removeIPMBasedCompare ( Compare , SrcReg , MRI , TM . getRegisterInfo ( ) ) ) return true ; return false


<s> int rv ; saved_first = crtl -> emit . x_first_insn ; saved_last = crtl -> emit . x_last_insn ; for ( seq = crtl -> emit . sequence_stack ; seq && seq -> next ; seq = seq -> next ) ; if ( seq ) { crtl -> emit . x_first_insn = seq -> first ; crtl -> emit . x_last_insn


<s> return LHS . isReg ( ) && RHS . isReg ( ) && LHS . getReg ( ) == RHS . getReg ( ) && LHS . getSubReg (


<s> <ISA_LIT>FunctionInfo * <ISA_LIT>FI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; MachineBasicBlock :: iterator MBBI = MBB . begin ( ) ; DebugLoc DL = MBBI != MBB . end ( ) ? MBBI -> getDebugLoc ( ) : DebugLoc ( ) ; <ISA_LIT>FI -> adjustLoadArgsFI ( MFI ) ; <ISA_LIT>FI -> adjustStoreVarArgsFI ( MFI ) ; unsigned StackSize = MFI -> getStackSize ( ) ; if ( StackSize == <NUM_LIT> && ! MFI -> adjustsStack ( ) ) return ; int FPOffset = <ISA_LIT>FI -> getFPStackOffset ( ) ; int RAOffset = <ISA_LIT>FI -> getRAStackOffset ( ) ; BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( - StackSize ) ; if ( MFI -> adjustsStack


<s> case MCBinaryExpr :: Opcode :: Add : OS << <STR_LIT> ; break ; case MCBinaryExpr :: Opcode :: Sub : OS << <STR_LIT> ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } printExpr ( BinExp -> getRHS ( ) , OS ) ; break ; case MCExpr :: ExprKind :: Constant : OS << dyn_cast < MCConstantExpr > ( Expr ) ->


<s> static const char * mips16_call_stub_mode_suffix ( machine_mode mode ) { if ( mode == SFmode ) return <STR_LIT> ; else if ( mode == DFmode ) return <STR_LIT> ; else if ( mode == SCmode )


<s> OperandMatchResultTy parseGRH32 ( OperandVector & Operands ) { return parseRegister ( Operands , GRH32Reg


<s> std :: pair < unsigned , unsigned > Default ( <NUM_LIT> , getMaxWavesPerEU ( ) ) ; std :: pair < unsigned , unsigned > FlatWorkGroupSizes = getFlatWorkGroupSizes ( F ) ; unsigned MinImpliedByFlatWorkGroupSize = getMaxWavesPerEU ( FlatWorkGroupSizes . second ) ; bool RequestedFlatWorkGroupSize = false ; if ( F . hasFnAttribute ( <STR_LIT> ) || F . hasFnAttribute ( <STR_LIT> ) ) { Default . first = MinImpliedByFlatWorkGroupSize ; RequestedFlatWorkGroupSize = true ; } std :: pair < unsigned , unsigned > Requested = <STR_LIT> ( F , <STR_LIT> , Default , true ) ; if ( Requested . second && Requested . first > Requested . second


<s> for ( auto * I : Lds ) Loads . push_back (


<s> const uint32_t * <ISA_LIT>RegisterInfo :: getCallPreservedMask ( const MachineFunction & MF , CallingConv :: ID CC ) const { const <ISA_LIT>Subtarget & Subtarget = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( CC == CallingConv :: AnyReg ) return Subtarget . hasVector ( ) ? CSR_<ISA_LIT>_AllRegs_Vector_RegMask : CSR_<ISA_LIT>_AllRegs_RegMask ; if ( MF . getSubtarget ( ) . getTargetLowering ( ) -> supportSwiftError ( ) && MF . getFunction ( )

. getAttributes ( ) . hasAttrSomewhere ( Attribute :: SwiftError ) ) return CSR_<ISA_LIT>_SwiftError_RegMask ;


<s> bool <ISA_LIT>TTI :: hasBranchDivergence ( ) const { return true


<s> bool <ISA_LIT>PassConfig :: addLegalizeMachineIR ( ) { addPass ( new Legalizer ( )


<s> return __builtin_mve_vrshrnbq_n_uv4si ( __a ,


<s> unsigned Opcode = Inst . getOpcode ( ) ; bool NeedsDisjointWritebackTransfer = false ; switch ( Opcode ) { default : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : DecodeGPR64spRegisterClass ( Inst , Rn , Addr , Decoder ) ; break ; } switch ( Opcode ) { default : return Fail ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : NeedsDisjointWritebackTransfer = true ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : DecodeGPR64RegisterClass ( Inst , Rt , Addr , Decoder ) ; DecodeGPR64RegisterClass ( Inst , Rt2 , Addr , Decoder ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : NeedsDisjointWritebackTransfer = true ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : DecodeGPR32RegisterClass ( Inst , Rt , Addr , Decoder ) ; DecodeGPR32RegisterClass ( Inst , Rt2 , Addr , Decoder ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : DecodeFPR128RegisterClass ( Inst , Rt , Addr , Decoder ) ; DecodeFPR128RegisterClass ( Inst , Rt2 , Addr , Decoder ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : DecodeFPR64RegisterClass ( Inst , Rt , Addr , Decoder ) ; DecodeFPR64RegisterClass ( Inst , Rt2 , Addr , Decoder ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : DecodeFPR32RegisterClass ( Inst , Rt , Addr , Decoder ) ; DecodeFPR32RegisterClass ( Inst , Rt2 , Addr , Decoder ) ; break ; } DecodeGPR64spRegisterClass ( Inst , Rn


<s> const <ISA_LIT>FrameLowering * TFI = getFrameLowering ( MF ) ; const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const Function * F = MF . getFunction ( ) ; unsigned StackAlign = TFI -> getStackAlignment ( ) ; bool requiresRealignment = ( ( MFI -> getMaxAlignment ( ) > StackAlign ) || F -> hasFnAttribute (


<s> if ( ImmMO . isGlobal ( ) ) { const DataLayout & DL = ImmMO . getGlobal ( ) -> getParent ( ) -> getDataLayout ( ) ; if ( ImmMO . getGlobal ( ) -> getPointerAlignment ( DL ) < III . ImmMustBeMultipleOf ) return false ; } return true ; } if ( ImmMO . isImm ( ) ) { APInt ActualValue ( <NUM_LIT> , ImmMO . getImm ( ) + BaseImm , true ) ; if ( III . SignedImm && ! ActualValue . isSignedIntN ( III . ImmWidth ) ) return false ; if ( ! III . SignedImm && ! ActualValue . isIntN ( III . ImmWidth ) ) return false ; Imm = SignExtend64 < <NUM_LIT> > ( ImmMO . getImm ( ) + BaseImm ) ; if ( Imm % III . ImmMustBeMultipleOf ) return false ; if ( III . TruncateImmTo ) Imm &= ( ( <NUM_LIT> << III . TruncateImmTo ) - <NUM_LIT> ) ; } else return false


<s> x = strip_offset_and_salt ( x , & offset ) ; if ( ! offset . is_constant ( ) && aarch64_offset_temporaries ( true , offset ) > <NUM_LIT> ) return false ; if ( maybe_ne ( offset , <NUM_LIT> ) && SYMBOL_REF_P ( x ) && SYMBOL_REF_ANCHOR_P ( x ) ) return false ; if ( SYMBOL_REF_P ( x ) && ! SYMBOL_REF_TLS_MODEL ( x ) ) return true ; if ( LABEL_REF_P ( x ) ) return true ; return false


<s> NumHex = <NUM_LIT> ; APF . convert ( APFloat :: IEEEdouble , APFloat :: rmNearestTiesToEven , & Ignored ) ; break ; } APInt API = APF . bitcastToAPInt ( ) ; std :: string HexStr ( utohexstr ( API . getZExtValue ( ) ) ) ; if ( HexStr . length ( ) < NumHex ) OS << std :: string ( NumHex - HexStr . length ( ) , '0' ) ; OS << utohexstr ( API .


<s> static <ISA_LIT>Operand * MorphToMEMri ( unsigned Base , <ISA_LIT>Operand * Op ) { const MCExpr * Imm = Op -> getImm ( ) ; Op -> Kind = k_MemoryImm ; Op -> Mem . Base = Base ; Op -> Mem .


<s> HSACodeProps . mWavefrontSize = STM . getWavefrontSize ( ) ; HSACodeProps . mNumSGPRs = ProgramInfo . NumSGPR ; HSACodeProps . mNumVGPRs = ProgramInfo . NumVGPR ; HSACodeProps . mMaxFlatWorkGroupSize = MFI . getMaxFlatWorkGroupSize ( ) ; HSACodeProps . mIsDynamicCallStack = ProgramInfo . DynamicCallStack ; HSACodeProps . mIsXNACKEnabled = STM . isXNACKEnabled ( ) ; HSACodeProps . mNumSpilledSGPRs = MFI . getNumSpilledSGPRs ( ) ; HSACodeProps . mNumSpilledVGPRs = MFI . getNumSpilledVGPRs ( ) ; return HSACodeProps


<s> rtvec v ; vmode = GET_MODE ( target ) ; gcc_assert ( GET_MODE_NUNITS ( vmode ) == <NUM_LIT> ) ; dmode = mode_for_vector ( GET_MODE_INNER ( vmode ) , <NUM_LIT> ) ; x = gen_rtx_VEC_CONCAT ( dmode , op0 , op1 ) ; v = gen_rtvec ( <NUM_LIT> , GEN_INT ( perm0 ) , GEN_INT ( perm1 ) ) ; x = gen_rtx_VEC_SELECT ( vmode , x , gen_rtx_PARALLEL ( VOIDmode , v ) ) ; emit_insn ( gen_rtx_SET ( VOIDmode , target , x ) ) ; } return true


<s> return __builtin_aarch64_smaxpv8qi ( a ,


<s> const char * tmps ; SWAP_INT ( fixed_regs [ i ] , fixed_regs [ i + <NUM_LIT> ] ) ; SWAP_INT ( call_used_regs [ i ] , call_used_regs [


<s> virtual bool hasRelocationAddend ( )


<s> else FrameObjOffset = ByVal . Address ; EVT PtrTy = getPointerTy ( ) ; int FI = MFI -> CreateFixedObject ( FrameObjSize , FrameObjOffset , true ) ; SDValue FIN = DAG . getFrameIndex ( FI , PtrTy ) ; InVals . push_back ( FIN ) ; if ( ! ByVal . NumRegs ) return ; MVT RegTy = <STR_LIT> ( CC . regSize ( ) * <NUM_LIT> ) ; const TargetRegisterClass * RC = getRegClassFor ( RegTy ) ; for ( unsigned I = <NUM_LIT> ; I < ByVal . NumRegs ; ++ I ) { unsigned ArgReg = CC . intArgRegs ( ) [ ByVal . FirstIdx + I ] ; unsigned VReg = addLiveIn ( MF , ArgReg , RC ) ; unsigned Offset = I * CC . regSize ( ) ; SDValue StorePtr = DAG . getNode ( <STR_LIT> , DL , PtrTy , FIN , DAG . getConstant ( Offset , PtrTy ) ) ; SDValue Store = DAG . getStore ( Chain , DL , DAG . getRegister ( VReg , RegTy ) , StorePtr

, MachinePointerInfo ( FuncArg , Offset ) , false , false , <NUM_LIT> ) ;


<s> const <ISA_LIT>Subtarget & Subtarget = MF -> getSubtarget < <ISA_LIT>Subtarget > ( ) ; const <ISA_LIT>InstrInfo * TII = Subtarget . getInstrInfo ( ) ; bool SeenFI = false ; for ( const MachineOperand & MO : MI . operands ( ) ) { if ( MO . isFI ( ) ) { if ( SeenFI ) llvm_unreachable ( <STR_LIT> ) ; SeenFI = true ; } } MachineOperand * FIOp = TII -> getNamedOperand ( MI , <STR_LIT> :: vaddr ) ; assert ( FIOp && FIOp -> isFI ( ) && <STR_LIT> ) ; assert ( TII -> isMUBUF ( MI ) ) ; MachineOperand * OffsetOp = TII -> getNamedOperand ( MI , <STR_LIT> :: offset ) ; int64_t NewOffset = OffsetOp -> getImm ( ) + Offset ; if ( isUInt < <NUM_LIT> > ( NewOffset ) ) { FIOp -> ChangeToRegister ( BaseReg , false


<s> unsigned NumElts = VT . getVectorNumElements ( ) ; if ( M [ <NUM_LIT> ] < <NUM_LIT> ) return false ; Imm = M [ <NUM_LIT> ] ; unsigned ExpectedElt = Imm ; for ( unsigned i = <NUM_LIT> ; i < NumElts ; ++ i ) { ++ ExpectedElt ; if ( ExpectedElt == NumElts ) ExpectedElt = <NUM_LIT> ; if ( M [ i ] < <NUM_LIT> ) continue ; if ( ExpectedElt != static_cast < unsigned > ( M [ i ]


<s> printIfSet ( MI , OpNo , O . indent ( <NUM_LIT> - O . GetNumBytesInBuffer ( ) ) , <STR_LIT>


<s> bool <ISA_LIT>PassConfig :: addPreEmitPass ( ) { if ( getOptLevel ( ) != CodeGenOpt :: None ) addPass ( create<ISA_LIT>ElimComparePass ( get<ISA_LIT>TargetMachine ( ) ) ) ; addPass ( create<ISA_LIT>LongBranchPass ( get<ISA_LIT>TargetMachine ( )


<s> return isTargetWatchABI ( ) || ( isSwift ( ) && ! MF . getFunction (


<s> const MCInstrDesc & Desc = TII -> get ( GetNonPseudoCallIndirectOpcode ( MI ) ) ; MI . setDesc ( Desc ) ; SmallVector < MachineOperand , <NUM_LIT> > Ops ; Ops . push_back ( MachineOperand :: CreateImm ( <NUM_LIT> ) ) ; Ops . push_back ( MachineOperand :: CreateImm ( <NUM_LIT> ) ) ; for ( const MachineOperand & MO : make_range ( MI . operands_begin ( ) + MI . getDesc ( ) . getNumDefs ( ) + <NUM_LIT> , MI . operands_begin ( ) + MI . getNumExplicitOperands ( ) ) ) Ops . push_back ( MO ) ; Ops . push_back ( MI . getOperand ( MI . getDesc ( ) . getNumDefs ( ) ) ) ; while ( MI . getNumOperands ( ) > MI . getDesc ( ) . getNumDefs ( ) ) MI . RemoveOperand ( MI . getNumOperands ( )


<s> return TYPE_MODE ( op_info -> args [ <NUM_LIT> ] . get_tree_type ( type .


<s> unsigned SrcReg = Reg + VA . getValNo ( ) ; Register DestReg = VA . getLocReg ( ) ; if ( ! MRI . getRegClass ( SrcReg ) -> contains ( DestReg ) ) return false ; EVT RVEVT = TLI . getValueType ( DL , RV -> getType ( ) ) ; if ( ! RVEVT . isSimple ( ) ) return false ; if ( RVEVT . isVector ( ) && RVEVT . getVectorElementCount ( ) . isVector ( ) && ! Subtarget -> isLittleEndian ( ) ) return false ; MVT RVVT = RVEVT . getSimpleVT ( ) ; if ( RVVT == <STR_LIT> ) return false ; MVT DestVT = VA . getValVT ( ) ; if ( RVVT != DestVT ) { if ( RVVT != <STR_LIT> && RVVT != <STR_LIT> && RVVT != <STR_LIT> ) return false ; if ( ! Outs [ <NUM_LIT> ] . Flags . isZExt ( ) && ! Outs [ <NUM_LIT> ] . Flags . isSExt ( ) ) return false ; bool IsZExt = Outs [ <NUM_LIT> ] . Flags . isZExt ( ) ; SrcReg = emitIntExt ( RVVT , SrcReg ,


<s> } MachineBasicBlock :: const_instr_iterator I = MI -> getIterator ( ) ; MachineBasicBlock :: const_instr_iterator E = MI -> getParent ( ) -> instr_end ( ) ; do { if ( emitPseudoExpansionLowering ( * OutStreamer , & * I ) ) continue ; if ( I -> getOpcode ( ) == <STR_LIT> || I -> getOpcode ( ) == <STR_LIT> || I -> getOpcode ( ) == <STR_LIT> || I -> getOpcode ( ) == <STR_LIT> || I -> getOpcode ( ) == <STR_LIT> || I -> getOpcode ( ) == <STR_LIT> ) { emitPseudoIndirectBranch ( * OutStreamer , & * I ) ; continue ; } if ( I -> isPseudo ( ) && ! Subtarget -> in<ISA_LIT>16Mode ( ) && ! isLongBranchPseudo ( I -> getOpcode ( ) ) ) llvm_unreachable ( <STR_LIT> ) ; MCInst TmpInst0 ; MCInstLowering . Lower ( & * I , TmpInst0 ) ; EmitToStreamer ( * OutStreamer , TmpInst0 ) ; } while ( ( ++ I != E ) && I ->


<s> const int this_slotno = data -> slotno + bitpos / BITS_PER_WORD ; machine_mode mode = DECL_MODE ( field ) ; int nregs , nslots ; if ( VECTOR_TYPE_P ( TREE_TYPE ( field ) ) && mode == BLKmode ) { mode = TYPE_MODE ( TREE_TYPE ( TREE_TYPE ( field ) ) ) ; nregs = TYPE_VECTOR_SUBPARTS ( TREE_TYPE ( field ) ) ; } else if ( TREE_CODE ( TREE_TYPE ( field ) ) == COMPLEX_TYPE ) { mode = TYPE_MODE ( TREE_TYPE ( TREE_TYPE ( field ) ) ) ; nregs = <NUM_LIT> ; } else nregs = <NUM_LIT> ; nslots = CEIL_NWORDS ( nregs * GET_MODE_SIZE ( mode ) ) ; if ( nslots > SPARC_FP_ARG_MAX - this_slotno ) { nslots = SPARC_FP_ARG_MAX - this_slotno ; nregs = ( nslots * UNITS_PER_WORD ) / GET_MODE_SIZE ( mode ) ; data -> stack = <NUM_LIT> ; if ( nregs <= <NUM_LIT> )


<s> int64_t Offset = Node -> getOffset ( ) ; EVT PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; SDValue Result = DAG . getTargetBlockAddress ( BA , PtrVT ,


<s> const ShuffleVectorInst * Shuffle = cast < ShuffleVectorInst > ( I ) ; auto * Ty = cast < VectorType > ( Shuffle -> getType ( ) ) ; auto * SrcTy = cast < VectorType > ( Shuffle -> getOperand ( <NUM_LIT> ) -> getType ( ) ) ; int SubIndex ; if ( Shuffle -> isExtractSubvectorMask ( SubIndex ) ) return getShuffleCost ( TTI :: SK_ExtractSubvector , SrcTy , SubIndex , Ty ) ; if ( Shuffle -> changesLength ( ) ) return BaseT :: getUserCost ( U , Operands , CostKind ) ; if ( Shuffle -> isIdentity ( ) ) return <NUM_LIT> ; if ( Shuffle -> isReverse ( ) ) return getShuffleCost ( TTI :: SK_Reverse , Ty , <NUM_LIT> , nullptr ) ; if ( Shuffle -> isSelect ( ) ) return getShuffleCost ( TTI :: SK_Select , Ty , <NUM_LIT> , nullptr ) ; if ( Shuffle -> isTranspose ( ) ) return getShuffleCost ( TTI :: SK_Transpose , Ty , <NUM_LIT> , nullptr ) ; if ( Shuffle -> isZeroEltSplat ( ) ) return getShuffleCost ( TTI :: SK_Broadcast , Ty , <NUM_LIT> , nullptr ) ; if ( Shuffle -> isSingleSource ( ) ) return getShuffleCost ( TTI :: SK_PermuteSingleSrc , Ty , <NUM_LIT> , nullptr ) ; return getShuffleCost ( TTI :: SK_PermuteTwoSrc , Ty , <NUM_LIT> , nullptr ) ; } case Instruction :: ZExt : case Instruction :: SExt : case Instruction :: FPToUI : case Instruction :: FPTo<ISA_LIT> : case Instruction :: FPExt : case Instruction :: PtrToInt : case Instruction :: IntToPtr : case Instruction :: <ISA_LIT>ToFP : case Instruction :: UIToFP : case Instruction :: Trunc : case Instruction :: FPTrunc : case Instruction :: BitCast : case Instruction :: AddrSpaceCast : { return getCastInstrCost ( I -> getOpcode ( ) , I -> getType ( ) , I -> getOperand ( <NUM_LIT> ) -> getType ( ) , I ) ; } case Instruction :: Add : case Instruction :: FAdd : case Instruction :: Sub : case Instruction :: FSub : case Instruction :: Mul : case Instruction :: FMul : case Instruction


<s> if ( TARGET_ELF && RS6000_SYMBOL_REF_TLS_P ( x ) ) return <NUM_LIT> ; if ( legitimate_indirect_address_p ( x , reg_ok_strict ) ) return <NUM_LIT> ; if ( TARGET_UPDATE && ( GET_CODE ( x ) == PRE_INC || GET_CODE ( x ) == PRE_DEC ) && mode_supports_pre_incdec_p ( mode ) && legitimate_indirect_address_p ( XEXP ( x , <NUM_LIT> ) , reg_ok_strict ) ) return <NUM_LIT> ; if ( virtual_stack_registers_memory_p ( x ) ) return <NUM_LIT> ; if ( reg_offset_p && legitimate_small_data_p ( mode , x ) ) return <NUM_LIT> ; if ( reg_offset_p && legitimate_constant_pool_address_p ( x , mode , reg_ok_strict || lra_in_progress ) ) return <NUM_LIT> ; if ( reg_offset_p && reg_addr [ mode ] . fused_toc && GET_CODE ( x ) == UNSPEC && XINT ( x , <NUM_LIT> ) == UNSPEC_FUSION_ADDIS ) return <NUM_LIT> ; if ( mode == TImode && TARGET_QUAD_MEMORY && TARGET_VSX_TIMODE ) return <NUM_LIT> ; if ( ! reg_ok_strict && reg_offset_p && GET_CODE ( x ) == PLUS && GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == REG && ( XEXP ( x , <NUM_LIT> ) == virtual_stack_vars_rtx || XEXP ( x , <NUM_LIT> ) == arg_pointer_rtx ) && GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == CONST_INT ) return <NUM_LIT> ; if ( rs6000_legitimate_offset_address_p ( mode , x , reg_ok_strict , false ) ) return <NUM_LIT> ; if ( ! FLOAT128_2REG_P ( mode ) && ( ( TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT ) || TARGET_POWERPC64 || ( mode != DFmode && mode != DDmode ) || ( TARGET_E500_DOUBLE && mode != DDmode ) ) && ( TARGET_POWERPC64 || mode != DImode ) && ( mode != TImode || VECTOR_MEM_VSX_P ( TImode ) ) && mode != PTImode && ! avoiding_indexed_address_p ( mode ) && legitimate_indexed_address_p ( x , reg_ok_strict ) ) return <NUM_LIT> ; if ( TARGET_UPDATE && GET_CODE ( x ) == PRE_MODIFY && mode_supports_pre_modify_p ( mode ) && legitimate_indirect_address_p ( XEXP ( x , <NUM_LIT> ) , reg_ok_strict ) && ( rs6000_legitimate_offset_address_p ( mode , XEXP ( x , <NUM_LIT> ) , reg_ok_strict , false ) || ( ! avoiding_indexed_address_p ( mode ) && legitimate_indexed_address_p ( XEXP ( x , <NUM_LIT> ) , reg_ok_strict ) ) ) && rtx_equal_p ( XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) , XEXP ( x , <NUM_LIT> ) ) ) return <NUM_LIT> ; if ( reg_offset_p && legitimate_lo_sum_address_p ( mode , x ,


<s> void <ISA_LIT>Subtarget :: initializeEnvironment ( ) { <ISA_LIT>SSELevel = NoSSE ; <ISA_LIT>3DNowLevel = NoThreeDNow ; HasX87 = false ; HasNOPL = false ; HasCMov = false ; Has<ISA_LIT>_64 = false ; HasPOPCNT = false ; HasSSE4A = false ; HasAES = false ; HasVAES = false ; HasFXSR = false ; HasXSAVE = false ; HasXSAVEOPT = false ; HasXSAVEC = false ; HasXSAVES = false ; HasPCLMUL = false ; HasVPCLMULQDQ = false ; HasGFNI = false ; HasFMA = false ; HasFMA4 = false ; HasXOP = false ; HasTBM = false ; HasLWP = false ; HasMOVBE = false ; HasRDRAND = false ; HasF16C = false ; HasFSGSBase = false ; HasLZCNT = false ; HasBMI = false ; HasBMI2 = false ; HasVBMI = false ; HasVBMI2 = false ; HasIFMA = false ; HasRTM = false ; HasERI = false ; HasCDI = false ; HasPFI = false ; HasDQI = false ; HasVPOPCNTDQ = false ; HasBWI = false ; HasVLX = false ; HasADX = false ; HasPKU = false ; HasVNNI = false ; HasBITALG = false ; HasSHA = false ; HasPREFETCHWT1 = false ; HasPRFCHW = false ; HasRDSEED = false ; HasLAHFSAHF = false ; HasMWAITX = false ; HasCLZERO = false ; HasMPX = false ; HasSHSTK = false ; HasIBT = false ; HasSGX = false ; HasCLFLUSHOPT = false ; HasCLWB = false ; HasRDPID =


<s> MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; auto * RVFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; Register FPReg = getFPReg ( STI ) ; Register SPReg = getSPReg ( STI ) ; if ( MF . getFunction ( ) . getCallingConv ( ) == CallingConv :: GHC ) return ; MachineBasicBlock :: iterator MBBI = MBB . end ( ) ; DebugLoc DL ; if ( ! MBB . empty ( ) ) { MBBI = MBB . getFirstTerminator ( ) ; if ( MBBI == MBB . end ( ) ) MBBI = MBB . getLastNonDebugInstr ( ) ; DL = MBBI -> getDebugLoc ( ) ; if ( ! MBBI -> isTerminator ( ) ) MBBI = std :: next ( MBBI ) ; while ( MBBI != MBB . begin ( ) && std :: prev ( MBBI ) -> getFlag ( MachineInstr :: FrameDestroy ) ) -- MBBI ; } const auto & CSI = getNonLibcallCSI ( MF , MFI . getCalleeSavedInfo ( ) ) ; auto LastFrameDestroy = MBBI ; if ( ! CSI . empty ( ) ) LastFrameDestroy = std :: prev ( MBBI , CSI . size ( ) ) ; uint64_t StackSize = MFI . getStackSize ( ) + RVFI -> getRVVPadding ( ) ; uint64_t RealStackSize = StackSize + RVFI -> getLibCallStackSize ( ) ; uint64_t FPOffset = RealStackSize - RVFI -> getVarArgsSaveSize ( ) ; uint64_t RVVStackSize = RVFI -> getRVVStackSize ( ) ; if ( RI -> hasStackRealignment ( MF ) || MFI . hasVarSizedObjects ( ) ) { assert ( hasFP ( MF ) && <STR_LIT> ) ; adjustReg ( MBB , LastFrameDestroy , DL , SPReg , FPReg , - FPOffset , MachineInstr :: FrameDestroy ) ; } else { if ( RVVStackSize ) adjustStackForRVV ( MF , MBB , LastFrameDestroy , DL , RVVStackSize , MachineInstr :: FrameDestroy ) ; } uint64_t FirstSPAdjustAmount = getFirstSPAdjustAmount ( MF ) ; if ( FirstSPAdjustAmount ) { uint64_t SecondSPAdjustAmount = MFI . getStackSize ( ) - FirstSPAdjustAmount ; assert ( SecondSPAdjustAmount > <NUM_LIT> && <STR_LIT> ) ; adjustReg ( MBB , LastFrameDestroy , DL , SPReg , SPReg , SecondSPAdjustAmount ,


<s> if ( ! Check ( S , DecoderGPRRegisterClass ( Inst , Rd , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! tryAddingSymbolicOperand ( Address , imm , false , <NUM_LIT> , Inst , Decoder ) ) Inst . addOperand ( MCOperand :: CreateImm ( imm ) ) ; if ( ! Check ( S , DecodePredicateOperand ( Inst , pred , Address , Decoder ) ) ) return MCDisassembler :: Fail ; return


<s> bool <ISA_LIT>SinglePathInfo :: isMaybe ( const MachineFunction & MF ) { return MF . getFunction ( ) -> hasFnAttribute


<s> num_matches = <NUM_LIT> ; last_match_type = match_type ; last_match_fntype_index = type_index ; last_match_index = bindex ; } else if ( match_type == last_match_type ) num_matches ++ ; } if ( last_match_type == INT_MAX ) { error_at ( loc , <STR_LIT> , IDENTIFIER_POINTER ( DECL_NAME ( ob_fndecl ) ) ) ; return error_mark_node ; } else if ( num_matches > <NUM_LIT> ) { error_at ( loc , <STR_LIT> , IDENTIFIER_POINTER ( DECL_NAME ( ob_fndecl ) ) ) ; return error_mark_node ; } if ( bt_for_overloaded_builtin_var [ last_match_index ] == S390_BUILTIN_MAX ) target_builtin_decl = ob_fndecl ; else target_builtin_decl = s390_builtin_decls [ bt_for_overloaded_builtin_var [ last_match_index ] ] ; all_op_flags = opflags_overloaded_builtin_var [ last_match_index ] ; return_type = s390_builtin_types [ s390_builtin_ov_types [ last_match_fntype_index ] [ <NUM_LIT> ] ] ; for ( i = <NUM_LIT> ; i < ob_args_num ; i ++ ) { unsigned int op_flags = all_op_flags & ( ( <NUM_LIT> << O_SHIFT ) - <NUM_LIT> ) ; tree arg = ( * arglist ) [ i ] ; tree type = s390_builtin_types [ s390_builtin_ov_types [ last_match_fntype_index ] [ i + <NUM_LIT> ] ] ; all_op_flags = all_op_flags >> O_SHIFT ; if ( op_flags == O_ELEM ) { int n_elem = s390_vec_n_elem ( target_builtin_decl ) ; gcc_assert ( n_elem > <NUM_LIT> ) ; gcc_assert ( type == integer_type_node ) ; ( * arglist ) [ i ] = build2 ( BIT_AND_EXPR , integer_type_node , fold_convert ( integer_type_node , arg ) , build_int_cst ( NULL_TREE , n_elem - <NUM_LIT> ) ) ; } if ( TREE_CODE ( arg ) != INTEGER_CST || ! O_IMM_P ( op_flags ) ) continue ; if ( ( TYPE_UNSIGNED ( type ) && ! int_fits_type_p ( arg , c_common_unsigned_type ( type ) ) ) || ( ! TYPE_UNSIGNED ( type ) && ! int_fits_type_p ( arg , c_common_signed_type ( type ) ) ) ) { error ( <STR_LIT> <STR_LIT> , i + <NUM_LIT> , target_builtin_decl ) ; return error_mark_node ; } if ( TREE_CODE ( arg ) == INTEGER_CST && ! s390_const_operand_ok ( arg , i + <NUM_LIT> , op_flags , target_builtin_decl ) ) return error_mark_node ; } if ( bt_for_overloaded_builtin_var [ last_match_index ] == S390_BUILTIN_MAX ) return s390_expand_overloaded_builtin ( loc , ob_fcode , arglist , return_type ) ; s390_adjust_builtin_arglist ( ob_fcode , target_builtin_decl , & arglist ) ; if ( VOID_TYPE_P ( return_type ) ) return build_function_call_vec (

loc , vNULL , target_builtin_decl , arglist , NULL ) ;


<s> static bool shouldForceImediateOperand ( StringRef Name , unsigned OperandIdx ) { switch ( OperandIdx ) { case <NUM_LIT> : return Name == <STR_LIT> || Name == <STR_LIT> ; case <NUM_LIT> : return Name ==


<s> const uint32_t * <ISA_LIT>RegisterInfo :: getCallPreservedMask ( const MachineFunction & MF , CallingConv :: ID ) const { return <ISA_LIT>CSR_RegMask


<s> for ( Module :: iterator F = M . begin ( ) , E = M . end ( ) ; F != E ; ++ F ) { if ( F -> isDeclaration ( ) ) continue ; DEBUG ( dbgs ( ) << <STR_LIT> << F -> getName ( ) << <STR_LIT> ) ; if ( usingMask ) { if ( functionIndex == <ISA_LIT>32FunctionMask . length ( ) ) functionIndex = <NUM_LIT> ; if ( <ISA_LIT>32FunctionMask [ functionIndex ] ==


<s> int AMDGPUCFGStructurizer :: getContinueZeroOpcode ( int OldOpcode ) { switch ( OldOpcode ) { case AMDGPU :: JUMP_COND : case AMDGPU :: JUMP : return


<s> rtl_opt_pass * make_pass_arc_ifcvt ( gcc :: context


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: CreateReg (


<s> MachineFunction & MF = DAG . getMachineFunction ( ) ; <ISA_LIT>FunctionInfo * <ISA_LIT>FI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; unsigned Reg = <ISA_LIT>FI -> getSRetReturnReg ( ) ; if ( ! Reg ) llvm_unreachable ( <STR_LIT> ) ; SDValue Val = DAG . getCopyFromReg ( Chain , dl , Reg , getPointerTy ( ) ) ; Chain = DAG . getCopyToReg ( Chain , dl , <STR_LIT> , Val , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; } if ( Flag . getNode ( ) ) return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Chain , DAG . getRegister ( <STR_LIT> , <STR_LIT> ) , Flag ) ; else return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Chain , DAG . getRegister ( <STR_LIT> ,


<s> SDNode * N = Op . getNode ( ) ; assert ( N -> getOperand ( <NUM_LIT> ) . getValueType ( ) == <STR_LIT> && <STR_LIT> ) ; SDValue Value = N -> getOperand ( <NUM_LIT> ) ; Value = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Value ) ; SDValue FPHalfs = DAG . getConstantFP ( <NUM_LIT> , dl , <STR_LIT> ) ; Value = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Value , FPHalfs , FPHalfs ) ; Value = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getConstant ( <STR_LIT> , dl , <STR_LIT> ) , Value ) ; MachineFrameInfo * FrameInfo = DAG . getMachineFunction ( ) . getFrameInfo ( ) ; int FrameIdx = FrameInfo -> CreateStackObject ( <NUM_LIT> , <NUM_LIT> , false ) ; MachinePointerInfo PtrInfo = MachinePointerInfo :: getFixedStack ( DAG . getMachineFunction ( ) , FrameIdx ) ; EVT PtrVT = getPointerTy ( DAG


<s> auto MaxMask = MRI . getMaxLaneMaskForVReg ( MO . getReg ( ) ) ; if ( MaxMask == LaneBitmask :: getLane ( <NUM_LIT> ) ) return MaxMask ; auto <ISA_LIT> = LIS . getInstructionIndex ( * MO . getParent


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case


<s> uint64_t Disp = getMachineOpValue ( MI , MI . getOperand ( OpNum + <NUM_LIT> ) , Fixups , STI ) ; uint64_t Len = getMachineOpValue ( MI , MI . getOperand ( OpNum + <NUM_LIT> ) , Fixups , STI ) ; assert ( isUInt < <NUM_LIT> > ( Base ) && isUInt < <NUM_LIT> > ( Disp ) && isUInt < <NUM_LIT> > ( Len ) ) ; return ( Len << <NUM_LIT> ) | ( Base << <NUM_LIT>


<s> return ( uint16x8_t ) __builtin_neon_vreinterpretv8hiti ( (


<s> bool isReg ( ) const override { return Kind ==


<s> bool <ISA_LIT>LegalizerInfo :: legalizeIntrinsic ( LegalizerHelper & Helper


<s> MIB = BuildMI ( LoadCmpBB , DL , TII -> get ( LdrexOp ) , Dest . getReg ( ) ) ; MIB . addReg ( AddrReg ) ; if ( LdrexOp == <STR_LIT> ) MIB . addImm ( <NUM_LIT> ) ; MIB . add ( predOps ( <STR_LIT> ) ) ; unsigned CMPrr = IsThumb ? <STR_LIT> : <STR_LIT> ; BuildMI ( LoadCmpBB , DL , TII -> get ( CMPrr ) ) . addReg ( Dest . getReg ( ) , getKillRegState ( Dest . isDead ( ) ) ) . addReg ( DesiredReg ) . add ( predOps ( <STR_LIT> ) ) ; unsigned Bcc = IsThumb ? <STR_LIT> : <STR_LIT> ; BuildMI ( LoadCmpBB , DL , TII -> get ( Bcc ) ) . addMBB ( DoneBB ) . addImm ( <STR_LIT> ) . addReg ( <STR_LIT> , RegState :: Kill ) ; LoadCmpBB -> addSuccessor ( DoneBB ) ; LoadCmpBB -> addSuccessor ( StoreBB ) ; MIB = BuildMI ( StoreBB , DL , TII -> get ( StrexOp ) , TempReg ) . addReg ( NewReg ) . addReg ( AddrReg ) ; if ( StrexOp == <STR_LIT> ) MIB . addImm ( <NUM_LIT> ) ; MIB . add ( predOps ( <STR_LIT> ) ) ; unsigned CMPri = IsThumb ? <STR_LIT> : <STR_LIT> ; BuildMI ( StoreBB , DL , TII -> get ( CMPri ) ) . addReg ( TempReg , RegState :: Kill ) . addImm ( <NUM_LIT> ) . add ( predOps ( <STR_LIT> ) ) ; BuildMI ( StoreBB , DL , TII -> get ( Bcc ) ) . addMBB ( LoadCmpBB ) . addImm ( <STR_LIT> ) . addReg ( <STR_LIT> , RegState :: Kill ) ; StoreBB -> addSuccessor ( LoadCmpBB ) ; StoreBB -> addSuccessor ( DoneBB ) ; DoneBB -> splice ( DoneBB -> end ( ) , & MBB , MI , MBB . end ( ) ) ; DoneBB -> transferSuccessors ( & MBB ) ; MBB . addSuccessor ( LoadCmpBB ) ; NextMBBI = MBB . end ( ) ; MI . eraseFromParent ( ) ; const MachineRegisterInfo & MRI = MBB . getParent ( ) -> getRegInfo ( ) ; LivePhysRegs LiveRegs ; computeLiveIns ( LiveRegs , MRI , * DoneBB ) ; computeLiveIns ( LiveRegs , MRI , * StoreBB ) ; computeLiveIns ( LiveRegs , MRI , * LoadCmpBB ) ; StoreBB -> clearLiveIns ( ) ; computeLiveIns ( LiveRegs , MRI , * StoreBB ) ; LoadCmpBB -> clearLiveIns ( ) ; computeLiveIns ( LiveRegs , MRI ,


<s> assert ( AllParams . count ( Param ) == <NUM_LIT>


<s> const uint32_t FirstWord = ( NumWords << <NUM_LIT> ) | OpCode ; OSE . write < uint32_t > ( FirstWord ) ; if ( hasType ( MI , MCII ) ) emitTypedInstrOperands ( MI , OSE ) ; else emitUntypedInstrOperands ( MI , OSE


<s> inline unsigned getRegAsVR128 ( unsigned Reg ) { return VR128Regs [ getFirstReg (


<s> assert ( FPReg == <STR_LIT> && <STR_LIT> ) ; FlushPendingOffset ( ) ; FPReg = Reg ; FPOffset = SPOffset + Offset ; const MCRegisterInfo * MRI = getContext ( ) . getRegisterInfo ( ) ; UnwindOpAsm . EmitSetSP ( MRI -> getEncodingValue ( FPReg


<s> PrivateGlobalPrefix = <STR_LIT> ; PointerSize = <NUM_LIT> ; ExceptionsType = ExceptionHandling :: WinEH ; } else { ExceptionsType = ExceptionHandling :: DwarfCFI ; } AssemblerDialect = AsmWriterFlavor ; TextAlignFillValue =


<s> SDValue Hi = DAG . getTargetConstantPool ( C , <STR_LIT> , N -> getAlign ( ) , N -> getOffset ( ) , OpFlagHi ) ; SDValue Lo = DAG . getTargetConstantPool ( C , <STR_LIT> , N -> getAlign ( ) , N -> getOffset ( ) , OpFlagLo ) ; Hi = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Hi ) ; Lo = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Lo ) ; SDValue Result = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Hi , Lo ) ; return Result


<s> if ( F -> isVarArg ( ) ) return false ; CallingConv :: ID CC = F -> getCallingConv ( ) ; if ( CC != CallingConv :: C ) return false ; if ( ! Subtarget -> is64Bit ( ) ) return false ; unsigned Idx = <NUM_LIT> ; for ( Function :: const_arg_iterator I = F -> arg_begin ( ) , E = F -> arg_end ( ) ; I != E ; ++ I , ++ Idx ) { if ( Idx > <NUM_LIT> ) return false ; if ( F -> getAttributes ( ) . hasAttribute ( Idx , Attribute :: ByVal ) || F -> getAttributes ( ) . hasAttribute ( Idx , Attribute :: InReg ) || F -> getAttributes ( ) . hasAttribute ( Idx , Attribute :: StructRet ) || F -> getAttributes ( ) . hasAttribute ( Idx , Attribute :: Nest ) ) return false ; Type * ArgTy = I -> getType ( ) ; if ( ArgTy -> isStructTy ( ) || ArgTy -> isArrayTy ( ) || ArgTy -> isVectorTy ( ) ) return false ; EVT ArgVT = TLI . getValueType ( ArgTy ) ; if ( ! ArgVT . isSimple ( ) ) return false ; switch ( ArgVT . getSimpleVT ( ) . SimpleTy ) { case <STR_LIT> : case <STR_LIT> : break ; default : return false ; } } static const uint16_t GPR32ArgRegs [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; static const uint16_t GPR64ArgRegs [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; Idx = <NUM_LIT> ; const TargetRegisterClass * RC32 = TLI . getRegClassFor ( <STR_LIT> ) ; const TargetRegisterClass * RC64 = TLI . getRegClassFor ( <STR_LIT> ) ; for ( Function :: const_arg_iterator I = F -> arg_begin ( ) , E = F -> arg_end ( ) ; I != E ; ++ I , ++ Idx ) { bool is32Bit = TLI . getValueType ( I -> getType ( ) ) == <STR_LIT> ; const TargetRegisterClass * RC = is32Bit ? RC32 : RC64 ; unsigned SrcReg = is32Bit ? GPR32ArgRegs [ Idx


<s> int Opcode = getV_CMPOpcode ( Pred , Size ) ; if ( Opcode == - <NUM_LIT> ) return false ; MachineInstr * ICmp = BuildMI ( * BB , & I , DL , TII . get ( Opcode ) , I . getOperand ( <NUM_LIT> ) . getReg ( ) ) . add ( I . getOperand ( <NUM_LIT> ) ) . add ( I . getOperand ( <NUM_LIT> ) ) ; RBI . constrainGenericRegister ( ICmp -> getOperand ( <NUM_LIT> ) . getReg ( ) , * TRI . getBoolRC ( ) , MRI ) ; bool Ret = constrainSelectedInstRegOperands ( * ICmp , TII , TRI , RBI ) ; I . eraseFromParent ( ) ; return


<s> SmallVector < CCValAssign , <NUM_LIT> > RVLocs ; CCState CCInfo ( CallConv , isVarArg , MF , RVLocs , Context ) ; if ( ! CCInfo . CheckReturn ( Outs , RetCC_<ISA_LIT> ) ) return false ; if ( CCInfo . getNextStackOffset ( ) != <NUM_LIT> && isVarArg ) return


<s> break ; case <STR_LIT> :: V60 : Result . push_back ( <STR_LIT> ) ; break ; case <STR_LIT> :: V62 : Result . push_back ( <STR_LIT> ) ; break ; case <STR_LIT> :: V65 : Result . push_back ( <STR_LIT> ) ; break ; case <STR_LIT> :: V66 : Result . push_back ( <STR_LIT> ) ; break ; case <STR_LIT> :: V67 : Result . push_back ( <STR_LIT> ) ; break ; case <STR_LIT> :: V68 : Result . push_back ( <STR_LIT> ) ; break ; case <STR_LIT> :: V69 : Result . push_back ( <STR_LIT>


<s> __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) _blsmsk_u32 ( unsigned int __X ) { return __blsmsk_u32 (


<s> int NewOpcode ; if ( RC == & <STR_LIT> ) NewOpcode = QII -> GetDotNewPredOp ( MI , MBPI ) ; else NewOpcode = QII -> GetDotNewOp ( MI ) ; MI -> setDesc ( QII -> get (


<s> SDValue <ISA_LIT>TargetLowering :: LowerCONCAT_VECTORS ( SDValue Op , SelectionDAG & DAG ) const { assert ( Op . getValueType ( ) . isScalableVector ( ) &&

isTypeLegal ( Op . getValueType ( ) ) && <STR_LIT> ) ;


<s> int ar2_reg_operand ( rtx op , enum machine_mode mode ) { return c4x_arn_reg_operand ( op , mode ,


<s> BuildMI ( MBB , I , dl , get ( <STR_LIT> ) , DestReg ) .

addImm ( <NUM_LIT> ) . addFrameIndex ( FI ) ;


<s> const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; if ( ! CE )


<s> if ( AM . GV ) Disp = CurDAG -> getTargetGlobalAddress ( AM . GV , SDLoc ( ) , <STR_LIT> , AM . Disp , AM . SymbolFlags ) ; else if ( AM . CP ) Disp = CurDAG -> getTargetConstantPool ( AM . CP , <STR_LIT> , AM . Align , AM . Disp , AM . SymbolFlags ) ; else if ( AM . ES ) { assert ( ! AM . Disp && <STR_LIT> ) ; Disp = CurDAG -> getTargetExternalSymbol ( AM . ES , <STR_LIT> , AM . SymbolFlags ) ; } else if ( AM . JT != -


<s> for ( SmallVectorImpl < MachineBasicBlock * > :: iterator It = ContMBB . begin ( ) , E = ContMBB . end ( ) ; It != E ; ++ It ) { ( * It ) -> removeSuccessor ( LoopHeader ) ; } numLoopcontPatternMatch += NumCont ; return


<s> assert ( ( CmpVT == <STR_LIT> || CmpVT == <STR_LIT> || CmpVT == <STR_LIT> || CmpVT == <STR_LIT> ) && <STR_LIT> ) ; if ( CmpVT == <STR_LIT> && ! Subtarget . isAtom ( ) && ! DAG . getMachineFunction ( ) . getFunction ( ) . hasMinSize ( ) ) { ConstantSDNode * COp0 = dyn_cast < ConstantSDNode > ( Op0 ) ; ConstantSDNode * COp1 = dyn_cast < ConstantSDNode > ( Op1 ) ; if ( ( COp0 && ! COp0 -> getAPIntValue ( ) . isSignedIntN ( <NUM_LIT> ) ) || ( COp1 && ! COp1 -> getAPIntValue ( ) . isSignedIntN ( <NUM_LIT> ) ) ) { unsigned ExtendOp = is<ISA_LIT>CCSigned ( <ISA_LIT>CC ) ? <STR_LIT> : <STR_LIT> ; if ( <ISA_LIT>CC == <STR_LIT> || <ISA_LIT>CC == <STR_LIT> ) { if ( Op0 . getOpcode ( ) == <STR_LIT> ) { SDValue In = Op0 . getOperand ( <NUM_LIT> ) ; unsigned EffBits = In . getScalarValueSizeInBits ( ) - DAG . ComputeNumSignBits ( In ) + <NUM_LIT> ; if ( EffBits <= <NUM_LIT> ) ExtendOp = <STR_LIT> ; } else if ( Op1 . getOpcode ( ) == <STR_LIT> ) { SDValue In = Op1 .


<s> LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << Exit -> getNumber ( ) << <STR_LIT> << ( * ( Entry -> pred_begin ( ) ) ) -> getNumber ( ) << <STR_LIT> ) ; int NumSources = <NUM_LIT> ; auto SE = PHIInfo . sources_end ( DestReg ) ; for ( auto SRI = PHIInfo . sources_begin ( DestReg ) ; SRI != SE ; ++ SRI ) { NumSources ++ ; } if ( NumSources == <NUM_LIT> ) { auto SRI = PHIInfo . sources_begin ( DestReg ) ; unsigned SourceReg = ( * SRI ) . first ; replaceRegisterWith ( DestReg , SourceReg ) ; } else { const DebugLoc & DL = Entry -> findDebugLoc ( Entry -> begin ( ) ) ; MachineInstrBuilder MIB = BuildMI ( * Entry , Entry -> instr_begin ( ) , DL , TII -> get ( TargetOpcode :: PHI ) , DestReg ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << printReg ( DestReg , TRI ) << <STR_LIT> ) ; unsigned CurrentBackedgeReg = <NUM_LIT> ; for ( auto SRI = PHIInfo . sources_begin ( DestReg ) ; SRI != SE ; ++ SRI ) { unsigned SourceReg = ( * SRI ) . first ; if ( CurrentRegion -> contains ( ( * SRI ) . second ) ) { if ( CurrentBackedgeReg == <NUM_LIT> ) { CurrentBackedgeReg = SourceReg ; } else { MachineInstr * PHIDefInstr = getDefInstr ( SourceReg ) ; MachineBasicBlock * PHIDefMBB = PHIDefInstr -> getParent ( ) ; const TargetRegisterClass * RegClass = MRI -> getRegClass ( CurrentBackedgeReg ) ; unsigned NewBackedgeReg = MRI -> createVirtualRegister ( RegClass ) ; MachineInstrBuilder BackedgePHI = BuildMI ( * PHIDefMBB , PHIDefMBB -> instr_begin ( ) , DL , TII -> get ( TargetOpcode :: PHI ) , NewBackedgeReg ) ; BackedgePHI . addReg ( CurrentBackedgeReg


<s> EVT PtrVT = Op . getValueType ( ) ; JumpTableSDNode * JT = cast < JumpTableSDNode > ( Op ) ; SDValue JTI = DAG . getTargetJumpTable ( JT -> getIndex ( ) , PtrVT ) ; DebugLoc dl = Op . getDebugLoc ( ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , JTI , DAG . getGLOBAL_OFFSET_TABLE ( <STR_LIT> ) ) ; SDValue Lo = DAG . getNode ( <STR_LIT> ,


<s> case k_Barrier : { bool Valid ; StringRef Name = <STR_LIT> ( ) . toString ( getBarrier ( ) , Valid ) ; if ( Valid ) OS << <STR_LIT> << Name << <STR_LIT> ; else OS << <STR_LIT> << getBarrier ( ) << <STR_LIT> ; break ; } case k_Immediate : getImm ( ) -> print ( OS ) ; break ; case k_ShiftedImm : { unsigned Shift = getShiftedImmShift ( ) ; OS << <STR_LIT> ; getShiftedImmVal ( ) -> print ( OS ) ; OS << <STR_LIT> << <STR_LIT> ( Shift ) << <STR_LIT> ; break ; } case k_CondCode : OS << <STR_LIT> << getCondCode ( ) << <STR_LIT> ; break ; case k_Register : OS << <STR_LIT> << getReg ( ) << <STR_LIT> ; break ; case k_VectorList : { OS << <STR_LIT> ; unsigned Reg = getVectorListStart ( ) ; for ( unsigned i = <NUM_LIT> , e = getVectorListCount ( ) ; i != e ; ++ i ) OS << Reg + i << <STR_LIT> ; OS << <STR_LIT> ; break ; } case k_VectorIndex : OS << <STR_LIT> << getVectorIndex ( ) << <STR_LIT> ; break ; case k_SysReg : OS << <STR_LIT> << getSysReg (


<s> Inst . addOperand ( MCOperand :: createImm ( <NUM_LIT> - Val ) ) ; return MCDisassembler