<s> } SmallVector < SDValue , <NUM_LIT> > Ops ; for ( unsigned i = <NUM_LIT> ; i < NumElts ; ++ i ) Ops . push_back ( N -> getOperand ( i + <NUM_LIT> ) ) ; Ops . push_back ( CurDAG -> getTargetConstant ( OffsetVal , DL , <STR_LIT> ) ) ; Ops . push_back ( Chain ) ; unsigned Opcode = <NUM_LIT> ; switch ( NumElts ) { default : return false ; case <NUM_LIT> : switch ( Mem -> getMemoryVT ( ) . getSimpleVT ( ) . SimpleTy ) { default : return false ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; } break ; case <NUM_LIT> : switch ( Mem -> getMemoryVT ( ) . getSimpleVT ( ) . SimpleTy ) { default : return false ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; } break ; case <NUM_LIT> : switch ( Mem -> getMemoryVT ( ) . getSimpleVT ( ) . SimpleTy ) { default : return false ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT>


<s> Function * F = I . getParent ( ) -> getParent ( ) ; Value * Idx = Constant :: getIntegerValue ( Type :: getInt32Ty ( Ptr -> getContext ( ) ) , APInt ( <NUM_LIT> , <NUM_LIT> ) ) ; PtrI = GetElementPtrInst :: Create ( Ptr -> getType ( ) -> getPointerElementType ( ) , Ptr , ArrayRef < Value * > ( Idx ) , Twine ( <STR_LIT> ) , F -> getEntryBlock ( ) . getFirstNonPHI ( ) ) ; } I . replaceUsesOfWith ( Ptr , PtrI ) ; } } if ( PtrI


<s> static MCInstrInfo * createAMDGPUMCInstrInfo ( ) { MCInstrInfo * X = new MCInstrInfo ( ) ; InitAMDGPUMCInstrInfo ( X )


<s> bool runOnMachineFunction ( MachineFunction & MF ) override { Subtarget = & MF . getTarget ( ) . getSubtarget < <ISA_LIT>Subtarget > ( ) ; SelectionDAGISel :: runOnMachineFunction ( MF ) ; return


<s> bool <ISA_LIT>FastISel :: SelectIndirectBr ( const Instruction * I ) { unsigned AddrReg = getRegForValue ( I -> getOperand ( <NUM_LIT> ) ) ; if ( AddrReg == <NUM_LIT> ) return false ; unsigned Opc = isThumb2 ? <STR_LIT> : <STR_LIT> ; assert ( isThumb2 || Subtarget -> hasV4TOps ( ) ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) ) . addReg ( AddrReg ) ) ; const IndirectBrInst * IB = cast < IndirectBrInst > ( I


<s> if ( MCSym . getInt ( ) ) OutStreamer . EmitIntValue ( <NUM_LIT> , is<ISA_LIT>64 ? <NUM_LIT> : <NUM_LIT> ) ; else OutStreamer . EmitValue ( MCSymbolRefExpr :: Create ( MCSym . getPointer ( ) , OutContext ) , is<ISA_LIT>64 ? <NUM_LIT> : <NUM_LIT> ) ; } Stubs . clear ( ) ; OutStreamer . AddBlankLine ( ) ; } Stubs = MMIMacho . GetHiddenGVStubList ( ) ; if ( ! Stubs . empty ( ) ) { OutStreamer . SwitchSection ( getObjFileLowering ( ) . getDataSection ( ) ) ; EmitAlignment ( is<ISA_LIT>64 ? <NUM_LIT> : <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> , e = Stubs . size ( ) ; i != e ; ++ i ) { OutStreamer . EmitLabel ( Stubs [ i ] . first ) ; OutStreamer . EmitValue ( MCSymbolRefExpr :: Create ( Stubs [ i ] . second . getPointer ( ) , OutContext ) , is<ISA_LIT>64 ? <NUM_LIT> : <NUM_LIT> ) ; } Stubs . clear ( ) ; OutStreamer . AddBlankLine ( ) ; } OutStreamer . EmitAssemblerFlag ( MCAF_SubsectionsViaSymbols ) ; return AsmPrinter :: doFinalization ( M )


<s> static ScheduleDAGInstrs * create<ISA_LIT>PostMachineScheduler ( MachineSchedContext * C ) { const <ISA_LIT>Subtarget & ST = C -> MF -> getSubtarget < <ISA_LIT>Subtarget > ( ) ; ScheduleDAGMI * DAG = new ScheduleDAGMI ( C , ST . use<ISA_LIT>PostRASchedStrategy ( ) ? std :: make_unique < <ISA_LIT>PostRASchedStrategy > ( C ) : std :: make_unique < PostGenericScheduler > ( C ) , true ) ; if ( ST . hasStoreFusion ( ) ) DAG -> addMutation ( createStoreClusterDAGMutation ( DAG -> TII , DAG -> TRI ) ) ; if ( ST . hasFusion ( ) ) DAG -> addMutation (

createPowerPCMacroFusionDAGMutation ( ) ) ;


<s> ptr -> x_rs6000_isa_flags = opts -> x_rs6000_isa_flags ; ptr -> x_rs6000_isa_flags_explicit =


<s> if ( ! FuncInfo . CanLowerReturn ) return false ; const Function * F = FuncInfo . Fn ; if ( F -> isVarArg ( ) ) return false ; CallingConv :: ID CC = F -> getCallingConv ( ) ; if ( CC != CallingConv :: C ) return false ; if ( Subtarget -> isCallingConvWin64 ( CC ) ) return false ; if ( ! Subtarget -> is64Bit ( ) ) return false ; unsigned Idx = <NUM_LIT> ; for ( Function :: const_arg_iterator I = F -> arg_begin ( ) , E = F -> arg_end ( ) ; I != E ; ++ I , ++ Idx ) { if ( Idx > <NUM_LIT> ) return false ; if ( F -> getAttributes ( ) . hasAttribute ( Idx , Attribute :: ByVal ) || F -> getAttributes ( ) . hasAttribute ( Idx , Attribute :: InReg ) || F -> getAttributes ( ) . hasAttribute ( Idx , Attribute :: StructRet ) || F -> getAttributes ( ) . hasAttribute ( Idx , Attribute :: Nest ) ) return false ; Type * ArgTy = I -> getType ( ) ; if ( ArgTy -> isStructTy ( ) || ArgTy -> isArrayTy ( ) || ArgTy -> isVectorTy ( ) ) return false ; EVT ArgVT = TLI . getValueType ( ArgTy ) ; if ( ! ArgVT . isSimple ( ) ) return false ; switch ( ArgVT . getSimpleVT ( ) . SimpleTy ) { case <STR_LIT> : case


<s> bool <ISA_LIT>AsmPrinter :: PrintAsmMemoryOperand ( const MachineInstr * MI , unsigned OpNum , unsigned AsmVariant , const char * ExtraCode , raw_ostream & O ) { assert ( OpNum + <NUM_LIT> < MI -> getNumOperands ( ) && <STR_LIT> ) ; const MachineOperand & BaseMO = MI -> getOperand ( OpNum ) ; const MachineOperand & OffsetMO = MI -> getOperand ( OpNum + <NUM_LIT> ) ; assert ( BaseMO . isReg ( ) && <STR_LIT> ) ; assert ( OffsetMO . isImm ( ) &&


<s> int unspec = ( e . type_suffix ( <NUM_LIT> ) . unsigned_p ? m_unspec_for_uint : m_unspec_for_sint ) ; machine_mode pred_mode = e . vector_mode


<s> } case Instruction :: IntToPtr : { if ( TLI . getValueType ( DL , U -> getOperand ( <NUM_LIT> ) -> getType ( ) ) == TLI . getPointerTy ( DL ) ) return computeAddress ( U -> getOperand ( <NUM_LIT> ) , Addr ) ; break ; } case Instruction :: PtrToInt : { if ( TLI . getValueType ( DL , U -> getType ( ) ) == TLI . getPointerTy ( DL ) ) return computeAddress ( U -> getOperand ( <NUM_LIT> ) , Addr ) ; break ; } case Instruction :: GetElementPtr : { Address SavedAddr = Addr ; uint64_t TmpOffset = Addr . getOffset ( ) ; if ( ! cast < GEPOperator > ( U ) -> isInBounds ( ) ) goto unsupported_gep ; for ( gep_type_iterator GTI = gep_type_begin ( U ) , E = gep_type_end ( U ) ; GTI != E ; ++ GTI ) { const Value * Op = GTI . getOperand ( ) ; if ( StructType * STy = GTI . getStructTypeOrNull ( ) ) { const StructLayout * SL = DL . getStructLayout ( STy ) ; unsigned Idx = cast < ConstantInt > ( Op ) -> getZExtValue ( ) ; TmpOffset += SL -> getElementOffset ( Idx ) ; } else { uint64_t S = DL . getTypeAllocSize ( GTI . getIndexedType ( ) ) ; for ( ; ; ) { if ( const ConstantInt * CI = dyn_cast < ConstantInt > ( Op ) ) { TmpOffset += CI -> getSExtValue ( ) * S ; break ; } if ( S == <NUM_LIT> && Addr . isRegBase ( ) && Addr . getReg ( ) == <NUM_LIT> ) { Addr . setReg ( getRegForValue ( Op ) ) ; break ; } if ( canFoldAddIntoGEP ( U , Op ) ) { ConstantInt * CI = cast < ConstantInt > ( cast < AddOperator > ( Op ) -> getOperand ( <NUM_LIT> ) ) ; TmpOffset += CI -> getSExtValue ( ) * S ; Op = cast < AddOperator > ( Op ) -> getOperand ( <NUM_LIT> ) ; continue ; } goto unsupported_gep ; } } } if ( int64_t ( TmpOffset ) >= <NUM_LIT> ) { Addr . setOffset


<s> return DecodeVecShiftRImm ( Inst , Imm ,


<s> return false ; } } if ( DestRC == <STR_LIT> ) { AddDefaultCC ( AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg ) ) ) ; } else if ( DestRC == <STR_LIT> ) { AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg ) ) ; } else if ( ( DestRC == <STR_LIT> ) || ( DestRC == <STR_LIT> ) ) { AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg ) ) ; } else if ( DestRC == <STR_LIT>


<s> void <ISA_LIT>InstPrinter :: printMemOperandEA ( const MCInst * MI , int opNum , raw_ostream & O ) { printOperand ( MI , opNum , O ) ; O << <STR_LIT>


<s> if ( needsStackRealignment ( MF ) && MFI -> hasVarSizedObjects (


<s> return ( ( qword ) ( vec_xor ( ( vec_uchar16 ) ( a ) ,


<s> void <ISA_LIT>InstrInfo :: storeRegToStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , unsigned SrcReg , bool isKill , int FrameIndex , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { BuildMI ( MBB , MI , MI -> getDebugLoc ( ) , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addFrameIndex ( FrameIndex )


<s> return ( Attributes & <ISA_LIT>FMA3KZeroMasked ) !=


<s> if ( b & <NUM_LIT> ) a >>= <NUM_LIT> ; for ( i = ( b & <NUM_LIT> ) ; i > <NUM_LIT> ; -- i ) a >>= <NUM_LIT> ; return


<s> EVT <ISA_LIT>TargetLowering :: getSetCCResultType ( const DataLayout & DL , LLVMContext & Context , EVT VT ) const { if ( VT . isVector ( ) ) { return EVT :: getVectorVT ( Context , <STR_LIT> , VT . getVectorNumElements ( ) ) ; } return <STR_LIT> ::


<s> case TargetOpcode :: EXTRACT_SUBREG : case TargetOpcode :: INSERT_SUBREG : case TargetOpcode :: SUBREG_TO_REG : case TargetOpcode :: REG_SEQUENCE : case TargetOpcode :: IMPLICIT_DEF : case TargetOpcode :: COPY : case TargetOpcode :: INLINEASM : break ; } MachineFunction & MF = * SU -> getInstr ( ) -> getParent ( ) -> getParent ( ) ; auto & QII = * MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getInstrInfo ( ) ; for ( unsigned i = <NUM_LIT> , e = Packet . size ( ) ; i != e ; ++ i ) { if ( Packet [ i ] -> Succs . size ( ) == <NUM_LIT> ) continue ; if ( QII . mayBeCurLoad ( Packet [ i ] -> getInstr ( ) ) ) continue ; for ( SUnit :: const_succ_iterator I = Packet [ i ] -> Succs . begin ( ) , E = Packet [ i ] -> Succs . end ( ) ; I != E ; ++ I ) { if ( I -> isCtrl ( ) ) continue ; if ( I -> getSUnit ( ) == SU ) return false ; } } return true


<s> unsigned getScratchWaveOffsetReg ( )


<s> if ( NumOperands != <NUM_LIT> || ( Ty != MRI . getType ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ) || ( Ty != MRI . getType ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ) ) llvm_unreachable ( <STR_LIT> ) ; auto Mapping = getValueMapping ( getPartialMappingIdx ( Ty , isFP ) , <NUM_LIT> ) ; return InstructionMapping { DefaultMappingID , <NUM_LIT> , Mapping ,


<s> return ( __m128h ) __builtin_ia32_getexpph128_mask ( ( __v8hf ) __A , (

__v8hf ) _mm_setzero_ph ( ) , ( __mmask8 ) __U ) ;


<s> const TargetRegisterClass * RegClass ; if ( IsVFPPushPop ) { RegsNeeded = NumBytes / <NUM_LIT> ; RegClass = & <STR_LIT> ; } else { RegsNeeded = NumBytes / <NUM_LIT> ; RegClass = & <STR_LIT> ; } SmallVector < MachineOperand , <NUM_LIT> > RegList ; unsigned FirstRegEnc = - <NUM_LIT> ; const TargetRegisterInfo * TRI = MF . getRegInfo ( ) . getTargetRegisterInfo ( ) ; for ( int i = MI -> getNumOperands ( ) - <NUM_LIT> ; i >= RegListIdx ; -- i ) { MachineOperand & MO = MI -> getOperand ( i ) ; RegList . push_back ( MO ) ; if ( MO . isReg ( ) && ! MO . isImplicit ( ) && TRI -> getEncodingValue ( MO . getReg ( ) ) < FirstRegEnc ) FirstRegEnc = TRI -> getEncodingValue ( MO . getReg ( ) ) ; } const MCPhysReg * CSRegs = TRI -> getCalleeSavedRegs ( & MF ) ; for ( int CurRegEnc = FirstRegEnc - <NUM_LIT> ; CurRegEnc >= <NUM_LIT> && RegsNeeded ; -- CurRegEnc ) { unsigned CurReg = RegClass -> getRegister ( CurRegEnc ) ; if ( IsT1PushPop && CurRegEnc > TRI -> getEncodingValue ( <STR_LIT> ) ) continue ; if ( ! IsPop ) { RegList . push_back ( MachineOperand :: CreateReg ( CurReg , false , false , false , false , true ) ) ; -- RegsNeeded ; continue ; } if ( isCalleeSavedRegister ( CurReg , CSRegs ) || MI -> getParent ( ) -> computeRegisterLiveness ( TRI , CurReg , MI ) != MachineBasicBlock :: LQR_Dead ) { if ( IsVFPPushPop ) return false ; else continue ; } RegList . push_back ( MachineOperand :: CreateReg ( CurReg , true , false , false , true ) ) ; -- RegsNeeded ; } if ( RegsNeeded > <NUM_LIT> ) return false ; for ( int i = MI -> getNumOperands ( ) - <NUM_LIT> ; i >= RegListIdx ; -- i


<s> static bool bpf_rtx_costs ( rtx x ATTRIBUTE_UNUSED , enum machine_mode mode ATTRIBUTE_UNUSED , int outer_code ATTRIBUTE_UNUSED , int opno ATTRIBUTE_UNUSED , int * total ATTRIBUTE_UNUSED , bool speed ATTRIBUTE_UNUSED ) { return


<s> virtual const <ISA_LIT>RegisterInfo & getRegisterInfo ( ) const { return RI


<s> bool <ISA_LIT>RegisterInfo :: isConstantPhysReg ( MCRegister PhysReg ) const { return


<s> SDValue InputVT = DAG . getValueType ( SrcVT ) ; if ( SrcVT . isFloatingPoint ( ) ) InputVT = DAG . getValueType ( HwSrcVt ) ; SDVTList VTs = DAG . getVTList ( <STR_LIT> ) ; SDValue SrcNew ; if ( Src . getValueType ( ) . isFloatingPoint ( ) ) SrcNew = DAG . getNode ( <STR_LIT> , DL , HwSrcVt , Src ) ; else SrcNew = DAG . getNode ( <STR_LIT> , DL , HwSrcVt , Src ) ; SDValue Ops [ ] = { N -> getOperand ( <NUM_LIT> ) , SrcNew , N -> getOperand ( <NUM_LIT> ) , Base , Offset , InputVT } ; return DAG . getNode ( Opcode , DL ,


<s> static DecodeStatus DecodeFPR128RegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t Addr , const void * Decoder ) { if ( RegNo > <NUM_LIT> ) return Fail ; unsigned Register = FPR128DecoderTable


<s> static unsigned getRelaxedOpcodeArith ( const MCInst & Inst ) { unsigned Op = Inst . getOpcode ( )


<s> std :: string CPUString = Subtarget -> getCPUString ( ) ; if ( CPUString != <STR_LIT> ) O << <STR_LIT> << CPUString << '\n' ; if ( Subtarget -> hasVFP2 ( ) ) O << <STR_LIT> << <STR_LIT> << <STR_LIT> ; if ( ! UnsafeFPMath ) O << <STR_LIT> << <STR_LIT> << <STR_LIT> << <STR_LIT> << <STR_LIT> << <STR_LIT> ; if ( FiniteOnlyFPMath ( ) ) O << <STR_LIT> << <STR_LIT> << <STR_LIT> ; else O << <STR_LIT> << <STR_LIT> << <STR_LIT> ; O << <STR_LIT> << <STR_LIT> << <STR_LIT> << <STR_LIT> <<


<s> _mm_cvttsd_u64 ( __m128d __A ) { return ( unsigned long long ) __builtin_ia32_vcvttsd2usi64 ( ( __v2df


<s> SDLoc dl ( N ) ; if ( ! Subtarget . hasAVX512 ( ) || ! VT . isVector ( ) || N0 -> getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; EVT SVT = VT . getVectorElementType ( ) ; if ( SVT != <STR_LIT> && SVT != <STR_LIT> && SVT != <STR_LIT> && SVT != <STR_LIT> && SVT != <STR_LIT> && SVT != <STR_LIT> ) return SDValue ( ) ; unsigned Size = VT . getSizeInBits ( ) ; if ( Size > <NUM_LIT> ) return SDValue ( ) ; <STR_LIT> CC = cast < CondCodeSDNode > ( N0 -> getOperand ( <NUM_LIT> ) ) -> get ( ) ; if ( <STR_LIT> ( CC ) ) return SDValue ( ) ; EVT N00VT = N0 . getOperand ( <NUM_LIT> ) . getValueType ( ) ; EVT MatchingVecType = N00VT . changeVectorElementTypeToInteger ( ) ; if ( Size != MatchingVecType . getSizeInBits ( ) ) return SDValue ( ) ; SDValue Res = DAG . getSetCC ( dl , VT , N0 . getOperand ( <NUM_LIT>

) , N0 . getOperand ( <NUM_LIT> ) , CC ) ;


<s> static const uint16_t CalleeSavedRegs [ ] =


<s> auto * TPC = getAnalysisIfAvailable < TargetPassConfig > ( ) ; if ( ! TPC ) return false ; auto & TM = TPC -> getTM < <ISA_LIT>TargetMachine > ( ) ; ST = TM . getSubtargetImpl ( F ) ; DL = & F . getParent ( ) -> getDataLayout ( ) ; bool MadeChange = false ; for ( auto & BB : F ) { for ( auto & I : BB ) { auto * BO = dyn_cast < BinaryOperator > ( & I ) ; if ( ! BO ) continue ; if ( ! isVectorReductionOp ( * BO ) ) continue ; if ( BO -> getOpcode ( ) == Instruction :: Add ) { if ( tryMAddPattern ( BO ) ) { MadeChange = true ; continue ; } if ( trySADPattern ( BO ) ) { MadeChange =


<s> static const char * SerializedPrefetchPrefix = <STR_LIT> ; const ErrorOr < PrefetchHints > T = getPrefetchHints ( TopSamples , MI ) ; if ( ! T ) return false ; int16_t max_index = - <NUM_LIT> ; for ( const auto & S_V : * T ) { StringRef Name = S_V . getKey ( ) ; if ( Name . consume_front ( SerializedPrefetchPrefix ) ) { int64_t D = static_cast < int64_t > ( S_V . second ) ; unsigned IID = <NUM_LIT> ; for ( const auto & HintType : HintTypes ) { if ( Name . startswith ( HintType . first ) ) { Name = Name . drop_front ( HintType . first . size ( ) ) ; IID = HintType . second ; break ; } } if ( IID == <NUM_LIT> ) return false ; uint8_t index = <NUM_LIT> ; Name . consumeInteger ( <NUM_LIT> , index ) ; if ( index >= Prefetches . size ( ) ) Prefetches . resize ( index + <NUM_LIT> ) ; Prefetches [ index ] = { IID , D } ; max_index = std :: max ( max_index , static_cast < int16_t > ( index ) ) ; } } assert ( max_index + <NUM_LIT> >= <NUM_LIT> && <STR_LIT> ) ; assert ( static_cast < size_t > ( max_index + <NUM_LIT> ) == Prefetches . size ( ) &&


<s> void <ISA_LIT>FormMemoryClauses :: collectRegUses ( const MachineInstr & MI , RegUse & Defs , RegUse & Uses ) const { for ( const MachineOperand & MO : MI . operands ( ) ) { if ( ! MO . isReg ( ) ) continue ; Register Reg = MO . getReg ( ) ; if ( ! Reg ) continue ; LaneBitmask Mask = Register :: isVirtualRegister ( Reg ) ? TRI -> getSubRegIndexLaneMask ( MO . getSubReg ( ) ) : LaneBitmask :: getAll ( ) ; RegUse & Map = MO . isDef ( ) ? Defs : Uses ; auto Loc = Map . find ( Reg ) ; unsigned State = getMopState ( MO ) ; if ( Loc == Map . end ( ) ) { Map [ Reg ] = std :: make_pair ( State , Mask ) ; } else { Loc -> second . first


<s> bool <ISA_LIT>InstrumentFunctions :: runOnFunction ( Function & F ) { if ( ShouldInstrument ( F ) ) { BuildEntryBlock ( F


<s> return MI -> getOperand ( <NUM_LIT> ) . getMBB


<s> Value * <ISA_LIT>IREmitter :: visitADD ( const SDNode * N ) { return IREmitter :: visitADD ( N


<s> int offset_to_frame ; int align_mask ; for ( regno = <NUM_LIT> ; regno < FIRST_PSEUDO_REGISTER ; regno ++ ) if ( need_to_save_reg ( regno ) ) reg_save_size += UNITS_PER_WORD ; offset_to_frame = crtl -> args . pretend_args_size + reg_save_size ; align_mask = ( STACK_BOUNDARY / BITS_PER_UNIT ) - <NUM_LIT> ; reg_save_size += ( - offset_to_frame ) & align_mask ; return reg_save_size


<s> static inline unsigned getT1Rd ( uint32_t insn ) { return slice ( insn , <NUM_LIT> , <NUM_LIT> ) <<

<NUM_LIT> | slice ( insn , <NUM_LIT> , <NUM_LIT> ) ;


<s> if ( RegNum > <NUM_LIT> ) return - <NUM_LIT> ; return getReg ( <STR_LIT> , RegNum )


<s> SGPRExcessLimit = Context -> RegClassInfo -> getNumAllocatableRegs ( & <STR_LIT> ) - ErrorMargin ; VGPRExcessLimit = Context -> RegClassInfo -> getNumAllocatableRegs ( & <STR_LIT> ) - ErrorMargin ; if ( TargetOccupancy ) { SGPRCriticalLimit = ST . getMaxNumSGPRs ( TargetOccupancy , true ) ; VGPRCriticalLimit = ST . getMaxNumVGPRs ( TargetOccupancy ) ; } else { SGPRCriticalLimit = SRI -> getRegPressureSetLimit ( DAG -> MF , SRI -> getSGPRPressureSet ( ) ) ; VGPRCriticalLimit = SRI -> getRegPressureSetLimit ( DAG -> MF , SRI -> getVGPRPressureSet ( ) ) ; } SGPRCriticalLimit -=


<s> return new <ISA_LIT>SETargetLowering ( TM , STI


<s> switch ( ScalarBits ) { case <NUM_LIT> : { unsigned ScalarCost = getArithmeticInstrCost ( Opcode , Ty -> getScalarType ( ) ) ; unsigned Cost = ( VF * ScalarCost ) + getScalarizationOverhead ( Ty , Args ) ; if ( VF == <NUM_LIT> ) Cost *= <NUM_LIT> ; return Cost ; } case <NUM_LIT> : case <NUM_LIT> : return NumVectors ; default : break ; } } if ( Opcode == Instruction :: FRem ) { unsigned Cost = ( VF * LIBCALL_COST ) + getScalarizationOverhead ( Ty , Args ) ; if ( VF == <NUM_LIT> && ScalarBits == <NUM_LIT> ) Cost *= <NUM_LIT> ; return Cost ; } } else { if ( Opcode == Instruction :: FAdd || Opcode == Instruction :: FSub || Opcode == Instruction :: FMul || Opcode == Instruction :: FDiv ) return <NUM_LIT> ; if ( Opcode == Instruction :: FRem ) return LIBCALL_COST ; if ( Opcode == Instruction :: LShr || Opcode == Instruction :: AShr ) return ( ScalarBits >= <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ) ; if ( Opcode == Instruction :: Or ) return


<s> if ( promoteConstantOffsetToImm ( MI , Visited , AnchorList ) ) Modified = true ; if ( MI . hasOrderedMemoryRef ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << MI ) ; ++ BlockI ; break ; } const InstClassEnum InstClass = getInstClass ( MI . getOpcode ( ) , * TII ) ; if ( InstClass == UNKNOWN ) continue ; CombineInfo CI ; CI . setMI ( MI , * TII , * STM ) ; CI . Order = Order ++ ; if ( ! CI . hasMergeableAddress (


<s> bool canSimplifyCallFramePseudos ( const MachineFunction & MF


<s> return ( __m256i ) __builtin_ia32_maskloadq256 ( ( const __v4di * ) __X ,


<s> for ( MachineRegisterInfo :: use_instr_nodbg_iterator I = MRI -> use_instr_nodbg_begin ( Reg ) , E = MRI -> use_instr_nodbg_end ( ) ; I != E ; ++ I ) { MachineInstr * MI = & * I ; unsigned CmpReg1 = <NUM_LIT> , CmpReg2 = <NUM_LIT> ; int CmpMask = <NUM_LIT> , CmpValue = <NUM_LIT> ; if ( ! TII -> analyzeCompare ( * MI , CmpReg1 , CmpReg2 , CmpMask , CmpValue ) ) continue ; MachineBasicBlock * TBB = <NUM_LIT> , * FBB = <NUM_LIT> ; SmallVector < MachineOperand , <NUM_LIT> > Cond ; if ( TII -> analyzeBranch ( * MI -> getParent ( ) , TBB , FBB , Cond , false ) ) continue ; Comparison :: Kind Cmp = getComparisonKind ( MI -> getOpcode ( ) , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> ) ; if ( Cmp == <NUM_LIT> ) continue ; if ( TII -> predOpcodeHasNot ( Cond ) ^ ( TBB != MBB ) ) Cmp = Comparison :: getNegatedComparison ( Cmp ) ; if ( CmpReg2 != <NUM_LIT> && CmpReg2 == Reg ) Cmp = Comparison :: getSwappedComparison ( Cmp ) ; if ( Comparison :: isSigned ( Cmp ) ) return false ; if ( ( Cmp & Comparison :: G ) || Cmp == Comparison :: NE ) return false ; } if ( ! Def -> isCopy ( ) && ! Def -> isPHI ( ) ) return false ; return


<s> NonKernelOnly = true ; return <STR_LIT> ; case <STR_LIT> : NonKernelOnly = true ; return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT>


<s> return new <ISA_LIT>CleanupVSETVLI (


<s> if ( TARGET_NEON && ( VALID_NEON_DREG_MODE ( mode1 ) || VALID_NEON_QREG_MODE ( mode1 ) || VALID_NEON_STRUCT_MODE ( mode1 ) ) && ( VALID_NEON_DREG_MODE ( mode2 ) || VALID_NEON_QREG_MODE ( mode2 ) || VALID_NEON_STRUCT_MODE ( mode2 ) ) ) return true ; return false


<s> static bool const_in_range ( rtx x , int minv , int maxv ) { return ( GET_CODE ( x ) == CONST_INT && INTVAL ( x


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : break ; default : llvm_unreachable ( <STR_LIT> ) ; } } if ( ( AddrSpace & <STR_LIT> ) != <STR_LIT> ) { switch ( Scope ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : LGKMCnt = IsCrossAddrSpaceOrdering ; break ; case <STR_LIT> : case <STR_LIT> : break ; default : llvm_unreachable ( <STR_LIT> ) ; } } if ( ( AddrSpace & <STR_LIT> ) != <STR_LIT> ) { switch ( Scope ) { case <STR_LIT> : case <STR_LIT> : EXPCnt = IsCrossAddrSpaceOrdering ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : break ; default : llvm_unreachable ( <STR_LIT> ) ; } } if ( VMCnt || LGKMCnt || EXPCnt ) { unsigned WaitCntImmediate = <STR_LIT> ( IV , VMCnt ? <NUM_LIT> : getVmcntBitMask ( IV ) , EXPCnt ? <NUM_LIT> :

getExpcntBitMask ( IV ) , LGKMCnt ? <NUM_LIT> : getLgkmcntBitMask ( IV ) ) ;


<s> StringRef getToken ( ) const { assert ( Kind == k_Token && <STR_LIT> ) ; return StringRef ( Tok . Data , Tok


<s> Align alignment = ( LocVT == <STR_LIT> ) ? Align ( <NUM_LIT> ) : Align ( <NUM_LIT> ) ; unsigned Offset = State . AllocateStack ( size , alignment ) ; unsigned Reg = <NUM_LIT> ; if ( LocVT == <STR_LIT> && Offset < <NUM_LIT> * <NUM_LIT> ) Reg = <STR_LIT> + Offset / <NUM_LIT> ; else if ( LocVT == <STR_LIT> && Offset < <NUM_LIT> * <NUM_LIT> ) Reg = <STR_LIT> + Offset / <NUM_LIT> ; else if ( LocVT == <STR_LIT> && Offset < <NUM_LIT> * <NUM_LIT> ) Reg = <STR_LIT> + Offset / <NUM_LIT> ; else if ( LocVT == <STR_LIT> && Offset < <NUM_LIT> * <NUM_LIT> ) Reg = <STR_LIT> + Offset / <NUM_LIT> ; if ( Reg ) { State . addLoc ( CCValAssign :: getReg ( ValNo , ValVT , Reg , LocVT , LocInfo ) ) ; return true ; } if ( LocVT == <STR_LIT> ) Offset


<s> StringRef Name = Tok . getString ( ) ; if ( Name . equals_insensitive ( <STR_LIT> ) ) { Parser . Lex ( ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateMatrixRegister ( <STR_LIT> , <NUM_LIT> , MatrixKind :: Array , S , getLoc ( ) , getContext ( ) ) ) ; if ( getLexer ( ) . is ( AsmToken :: LBrac ) ) { if ( parseOperand ( Operands , false , false ) ) return MatchOperand_NoMatch ; } return MatchOperand_Success ; } unsigned Reg = matchRegisterNameAlias ( Name , RegKind :: Matrix ) ; if ( ! Reg ) return MatchOperand_NoMatch ; size_t DotPosition = Name . find ( '.' ) ; assert ( DotPosition != StringRef :: npos && <STR_LIT> ) ; StringRef Head = Name . take_front ( DotPosition ) ; StringRef Tail = Name . drop_front ( DotPosition ) ; StringRef RowOrColumn = Head . take_back ( ) ; MatrixKind Kind = StringSwitch < MatrixKind > ( RowOrColumn ) . Case ( <STR_LIT> , MatrixKind :: Row ) . Case ( <STR_LIT> , MatrixKind :: Col ) . Default ( MatrixKind :: Tile ) ; const auto & KindRes = parseVectorKind ( Tail , RegKind :: Matrix ) ; if ( ! KindRes ) { TokError ( <STR_LIT> )


<s> } if ( shouldEmitFixup ( GV ) ) return buildPCRelGlobalAddress ( DAG , GV , DL , GSD -> getOffset ( ) , PtrVT ) ; else if ( shouldEmitPCReloc ( GV ) ) return buildPCRelGlobalAddress ( DAG , GV , DL , GSD -> getOffset ( ) , PtrVT , <ISA_LIT>InstrInfo :: MO_REL32 ) ; SDValue GOTAddr = buildPCRelGlobalAddress ( DAG , GV , DL , <NUM_LIT> , PtrVT , <ISA_LIT>InstrInfo :: MO_GOTPCREL32 ) ; Type * Ty = PtrVT . getTypeForEVT ( * DAG . getContext ( ) ) ; PointerType * PtrTy = PointerType :: get ( Ty , <ISA_LIT>AS :: CONSTANT_ADDRESS ) ; const DataLayout & DataLayout = DAG . getDataLayout ( ) ; Align Alignment = DataLayout .


<s> EVT AVT = <STR_LIT> ; if ( Subtarget -> is64Bit ( ) && ( ( Align & <NUM_LIT> ) == <NUM_LIT> ) ) AVT = <STR_LIT> ; unsigned UBytes = AVT . getSizeInBits ( ) / <NUM_LIT> ; unsigned CountVal = SizeVal / UBytes ; SDValue Count = DAG . getIntPtrConstant ( CountVal ) ; unsigned BytesLeft = SizeVal % UBytes ; SDValue InFlag ( <NUM_LIT> , <NUM_LIT> ) ; Chain = DAG . getCopyToReg ( Chain , dl , Subtarget -> is64Bit ( ) ? <STR_LIT> : <STR_LIT> , Count , InFlag ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; Chain = DAG . getCopyToReg ( Chain , dl , Subtarget -> is64Bit ( ) ? <STR_LIT> : <STR_LIT> , Dst , InFlag ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; Chain = DAG . getCopyToReg ( Chain , dl , Subtarget -> is64Bit ( ) ? <STR_LIT> : <STR_LIT> , Src , InFlag ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; SDVTList Tys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . push_back ( Chain ) ; Ops . push_back ( DAG . getValueType ( AVT ) ) ; Ops . push_back ( InFlag ) ; SDValue RepMovs = DAG . getNode ( <STR_LIT> , dl , Tys , & Ops [ <NUM_LIT> ] , Ops . size ( ) ) ; SmallVector < SDValue , <NUM_LIT> > Results ; Results . push_back ( RepMovs ) ; if ( BytesLeft


<s> return DAG . getNode ( <STR_LIT> , DL , N -> getVTList ( ) , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , Cond , Flags ) ; } return SDValue ( )


<s> bool needsRelocateWithSymbol ( const MCSymbol & Sym , unsigned


<s> void getAnalysisUsage ( AnalysisUsage &


<s> rtx op0 , op1 ; switch ( GET_CODE ( x ) ) { case SYMBOL_REF : case CONST : fputs ( <STR_LIT> , stream ) ; output_addr_const ( stream , x ) ; fputs ( <STR_LIT> , stream ) ; break ; case REG : if ( TARGET_REDUCED_REGS && REGNO ( x ) == STATIC_CHAIN_REGNUM ) sorry ( <STR_LIT> ) ; fprintf ( stream , <STR_LIT> , reg_names [ REGNO ( x ) ] ) ; break ; case PLUS : op0 = XEXP ( x , <NUM_LIT> ) ; op1 = XEXP ( x , <NUM_LIT> ) ; if ( TARGET_REDUCED_REGS && REG_P ( op0 ) && REGNO ( op0 ) == STATIC_CHAIN_REGNUM ) sorry ( <STR_LIT> ) ; if ( TARGET_REDUCED_REGS && REG_P ( op1 ) && REGNO ( op1 ) == STATIC_CHAIN_REGNUM ) sorry ( <STR_LIT> ) ; if ( REG_P ( op0 ) && CONST_INT_P ( op1 ) ) { fprintf ( stream , <STR_LIT> , reg_names [ REGNO ( op0 ) ] , ( int ) INTVAL ( op1 ) ) ; } else if ( REG_P ( op0 ) && REG_P ( op1 ) ) { fprintf ( stream , <STR_LIT> , reg_names [ REGNO ( op0 ) ] , reg_names [ REGNO ( op1 ) ] ) ; } else if ( GET_CODE ( op0 ) == MULT && REG_P ( op1 ) ) { int sv ; if ( INTVAL ( XEXP ( op0 , <NUM_LIT> ) ) == <NUM_LIT> ) sv = <NUM_LIT> ; else if ( INTVAL ( XEXP ( op0 , <NUM_LIT> ) ) == <NUM_LIT> ) sv = <NUM_LIT> ; else if ( INTVAL ( XEXP ( op0 , <NUM_LIT> ) )


<s> if ( FuncInfo . MBB -> isLayoutSuccessor ( TBB ) ) { std :: swap ( TBB , FBB ) ; <ISA_LIT>Pred = <STR_LIT> ( <ISA_LIT>Pred ) ; } unsigned CondReg = createResultReg ( & <STR_LIT> ) ; if ( ! <ISA_LIT>EmitCmp ( CI -> getOperand ( <NUM_LIT> ) , CI -> getOperand ( <NUM_LIT> ) , CI -> isUnsigned ( ) , CondReg ) ) return false ; BuildMI ( * BrBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) ) . addImm ( <ISA_LIT>Pred ) . addReg ( CondReg ) . addMBB ( TBB ) ; fastEmitBranch ( FBB , DbgLoc ) ; FuncInfo . MBB -> addSuccessor ( TBB ) ; return true ; } } else if ( const ConstantInt * CI = dyn_cast < ConstantInt >


<s> } else if ( Subtarget . is64Bit ( ) ) { Subtarget . setPICStyle ( PICStyles :: RIPRel ) ; } else if ( Subtarget . isTargetCygMing ( ) ) { Subtarget . setPICStyle ( PICStyles :: None ) ; } else if ( Subtarget . isTargetDarwin ( ) ) { if ( getRelocationModel ( ) == Reloc :: PIC_ ) Subtarget . setPICStyle ( PICStyles :: StubPIC ) ; else { assert ( getRelocationModel ( ) == Reloc :: DynamicNoPIC ) ; Subtarget . setPICStyle ( PICStyles :: StubDynamicNoPIC ) ; } } else if ( Subtarget . isTargetELF ( ) ) { Subtarget . setPICStyle ( PICStyles :: GOT ) ; } if ( Options . FloatABIType == FloatABI :: Default ) this

-> Options . FloatABIType = FloatABI :: Hard ;


<s> uint32_t <ISA_LIT>MCCodeEmitter :: getSIMDShift16OpValue ( const MCInst & MI , unsigned OpIdx , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { const MCOperand & MO = MI . getOperand ( OpIdx ) ; assert ( MO . isImm ( )


<s> if ( <ISA_LIT>Features [ <STR_LIT> ] || <ISA_LIT>Features [ <STR_LIT> ] ) { return SPUInstrLayout ; } llvm_unreachable ( <STR_LIT>


<s> virtual unsigned int execute ( function *


<s> if ( Subtarget . in<ISA_LIT>16HardFloat ( ) ) { bool LookupHelper = true ; if ( ExternalSymbolSDNode * S = dyn_cast < ExternalSymbolSDNode > ( CLI . Callee ) ) { <ISA_LIT>16Libcall Find = { RTLIB :: UNKNOWN_LIBCALL , S -> getSymbol ( ) } ; if ( std :: binary_search ( std :: begin ( HardFloatLibCalls ) , std :: end ( HardFloatLibCalls ) , Find ) ) LookupHelper = false ; else { const char * Symbol = S -> getSymbol ( ) ; <ISA_LIT>16IntrinsicHelperType IntrinsicFind = { Symbol , <STR_LIT> } ; const <STR_LIT> * Signature = <STR_LIT> ( Symbol ) ; if ( ! IsPICCall && ( Signature && ( FuncInfo -> StubsNeeded . find ( Symbol ) == FuncInfo -> StubsNeeded . end ( ) ) ) ) { FuncInfo -> StubsNeeded [ Symbol ] = Signature ; if ( <NUM_LIT> || ( Signature -> RetSig != <STR_LIT> ) ) FuncInfo -> setSaveS2 ( ) ; } const <ISA_LIT>16IntrinsicHelperType * Helper = llvm :: lower_bound ( <ISA_LIT>16IntrinsicHelper , IntrinsicFind ) ; if ( Helper != std :: end ( <ISA_LIT>16IntrinsicHelper ) && * Helper == IntrinsicFind ) { <ISA_LIT>16HelperFunction = Helper -> Helper ; Need<ISA_LIT>16Helper = true ; LookupHelper = false ; } } } else if ( GlobalAddressSDNode * G = dyn_cast < GlobalAddressSDNode > ( CLI . Callee ) ) { <ISA_LIT>16Libcall Find = { RTLIB :: UNKNOWN_LIBCALL , G -> getGlobal ( ) -> getName ( ) . data ( ) } ; if ( std :: binary_search ( std :: begin ( HardFloatLibCalls ) ,


<s> return ( __m64 ) __builtin_arm_wsllhi ( (


<s> if ( Parser . getTok ( ) . is ( AsmToken :: Hash ) ) { Parser . Lex ( ) ; } if ( parseSymbolicImmVal ( Expr ) ) return MatchOperand_ParseFail ; <ISA_LIT>MCExpr :: VariantKind ELFRefKind ; MCSymbolRefExpr :: VariantKind DarwinRefKind ; int64_t Addend ; if ( classifySymbolRef ( Expr , ELFRefKind , DarwinRefKind , Addend ) ) { if ( DarwinRefKind == MCSymbolRefExpr :: VK_None && ELFRefKind == <ISA_LIT>MCExpr :: VK_INVALID ) { Expr = <ISA_LIT>MCExpr :: create ( Expr , <ISA_LIT>MCExpr :: VK_ABS_PAGE , getContext ( ) ) ; } else if ( ( DarwinRefKind == MCSymbolRefExpr :: VK_GOTPAGE || DarwinRefKind == MCSymbolRefExpr

:: VK_TLVPPAGE ) && Addend != <NUM_LIT> ) {


<s> FuncId = static_cast < EFuncId > ( manglingRulesMap . lookup ( FullName


<s> do { tree field = TYPE_FIELDS ( type ) ; while ( field != NULL && ( TREE_CODE ( field ) != FIELD_DECL || DECL_FIELD_ABI_IGNORED ( field ) ) ) field = DECL_CHAIN ( field ) ; if ( ! field ) break ; if ( DECL_PACKED ( field ) ) return align ; type = TREE_TYPE ( field ) ; while ( TREE_CODE ( type ) == ARRAY_TYPE ) type = TREE_TYPE ( type ) ; } while ( AGGREGATE_TYPE_P ( type ) ) ; if ( ! AGGREGATE_TYPE_P ( type ) && type != error_mark_node ) align = MAX ( align , TYPE_ALIGN ( type ) ) ; return align


<s> char * aarch64_output_sve_scalar_inc_dec ( rtx offset ) { poly_int64 offset_value = rtx_to_poly_int64 ( offset ) ; gcc_assert ( offset_value . coeffs [ <NUM_LIT> ] == offset_value . coeffs [ <NUM_LIT> ] ) ; if ( offset_value . coeffs [ <NUM_LIT> ] > <NUM_LIT> ) return aarch64_output_sve_cnt_immediate ( <STR_LIT> , <STR_LIT> ,

AARCH64_SV_ALL , offset_value . coeffs [ <NUM_LIT> ] , <NUM_LIT> ) ;


<s> assert ( <NUM_LIT> && <STR_LIT> ) ; case <NUM_LIT> : break ; case <STR_LIT> : Expr = MCSymbolRefExpr :: Create ( Symbol , MCSymbolRefExpr :: VK_None , Ctx ) ; Expr = <ISA_LIT>MCExpr :: CreateLower16 ( Expr , Ctx ) ; break ; case <STR_LIT> : Expr = MCSymbolRefExpr :: Create ( Symbol , MCSymbolRefExpr :: VK_None , Ctx ) ; Expr = <ISA_LIT>MCExpr :: CreateUpper16 ( Expr , Ctx ) ; break ; } break ; } case <STR_LIT> : Expr = MCSymbolRefExpr :: Create ( Symbol , MCSymbolRefExpr :: VK_<ISA_LIT>_PLT , Ctx ) ; break ; } if ( ! MO . isJTI ( ) && MO . getOffset ( ) ) Expr = MCBinaryExpr :: CreateAdd ( Expr , MCConstantExpr :: Create ( MO . getOffset ( ) , Ctx ) , Ctx ) ; return MCOperand :: CreateExpr (


<s> for ( MCRegAliasIterator AI ( Reg , & TRI , true ) ; AI . isValid ( ) ; ++ AI

) UsedRegs [ * AI / <NUM_LIT> ] |= <NUM_LIT> << ( * AI & <NUM_LIT> ) ;


<s> <STR_LIT> CC = cast < CondCodeSDNode > ( N -> getOperand ( <NUM_LIT> ) ) -> get ( ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( ! Subtarget -> hasMVEIntegerOps ( ) || ! DCI . DAG . getTargetLoweringInfo ( ) . isTypeLegal ( VT ) ) return SDValue ( ) ; if ( CC == <STR_LIT> ) { std :: swap ( Op0 , Op1 ) ; CC = <STR_LIT> ; } if ( CC != <STR_LIT> || VT . getScalarSizeInBits ( ) != <NUM_LIT> || Op0 . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; for ( unsigned I = <NUM_LIT> ; I < VT . getVectorNumElements ( ) ; I ++ ) { if ( ! Op0 . getOperand ( I ) . isUndef ( ) && ! ( isa < ConstantSDNode > ( Op0 . getOperand ( I ) ) && Op0 . getConstantOperandVal ( I ) == I ) ) return SDValue ( ) ; } SDValue Op1S = DCI . DAG . getSplatValue ( Op1 ) ; if ( ! Op1S ) return SDValue ( ) ; unsigned Opc ; switch ( VT . getVectorNumElements ( ) ) { case <NUM_LIT> : Opc = <STR_LIT> ; break ; case <NUM_LIT>


<s> assert ( MBBI != Entry -> end ( ) && MBBI -> getOpcode ( ) == <STR_LIT> ) ; MBBI -> eraseFromParent ( ) ; bool RemovedAllMTVRSAVEs = true ; for ( MachineFunction :: iterator I = MF -> begin ( ) , E = MF -> end ( ) ; I != E ; ++ I ) { if ( ! I -> empty ( ) && I -> back ( ) . isReturn ( ) ) { bool FoundIt = false ; for ( MBBI = I -> end ( ) ; MBBI != I -> begin ( ) ; ) { -- MBBI ; if ( MBBI -> getOpcode ( ) == <STR_LIT> ) { MBBI -> eraseFromParent ( ) ; FoundIt = true ; break ; } } RemovedAllMTVRSAVEs &=


<s> if ( ! F || F -> isDeclaration ( ) ) continue ; const TargetSubtargetInfo * ST = TM . getSubtargetImpl ( * F ) ; <ISA_LIT>PerfHint Analyzer ( FIM , ST


<s> cum -> arg_words += ( ( int_size_in_bytes ( type ) + UNITS_PER_WORD - <NUM_LIT> ) / UNITS_PER_WORD ) ; break ; case E_SFmode : cum -> arg_words ++ ; if ( ! cum -> gp_reg_found && cum -> arg_number <= <NUM_LIT> ) cum -> fp_code += <NUM_LIT> << ( ( cum -> arg_number - <NUM_LIT> ) * <NUM_LIT> ) ; break ; case E_DFmode : cum -> arg_words += <NUM_LIT> ; if ( ! cum -> gp_reg_found && cum -> arg_number <= <NUM_LIT> ) cum -> fp_code += <NUM_LIT> << ( ( cum -> arg_number - <NUM_LIT> ) * <NUM_LIT> ) ; break ; case E_DImode : cum -> gp_reg_found = <NUM_LIT> ; cum -> arg_words += <NUM_LIT> ; break ; case E_QImode : case E_HImode : case E_SImode : case E_TImode : cum -> gp_reg_found = <NUM_LIT> ; cum -> arg_words


<s> case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT>


<s> int64_t Offset = <NUM_LIT> ; if ( ! selectMUBUFAddr64Impl ( Root , VAddr , RSrcReg , SOffset , Offset ) ) return { } ; return { { [ = ] ( MachineInstrBuilder & MIB ) { MIB . addReg ( RSrcReg ) ; } , [ = ] ( MachineInstrBuilder & MIB ) { MIB . addReg ( VAddr ) ; } , [ = ] ( MachineInstrBuilder & MIB ) { if ( SOffset ) MIB . addReg ( SOffset ) ; else MIB . addImm ( <NUM_LIT> ) ; } , [ = ] ( MachineInstrBuilder & MIB ) { MIB . addImm ( Offset ) ; } , addZeroImm , addZeroImm


) _mm_undefined_ps ( ) , ( __mmask8 ) - <NUM_LIT> ) ;


<s> void setVariadicFPRIdx ( int Idx ) { VariadicFPRIdx =


<s> assert ( MO . isImm ( ) && <STR_LIT> ) ; O << MO . getImm ( )


<s> EVT ValTy = Op . getValueType ( ) ; bool HasGotOfst = ( GV -> hasInternalLinkage ( ) || ( GV -> hasLocalLinkage ( ) && ! isa < Function > ( GV ) ) ) ; unsigned GotFlag = Has<ISA_LIT>64 ? ( HasGotOfst ? <STR_LIT> : <STR_LIT> ) : ( HasGotOfst ? <STR_LIT> : <STR_LIT> ) ; SDValue GA = DAG . getTargetGlobalAddress ( GV , dl , ValTy , <NUM_LIT> , GotFlag ) ; GA = DAG . getNode ( <STR_LIT> , dl , ValTy , GetGlobalReg ( DAG , ValTy ) , GA ) ; SDValue ResNode = DAG . getLoad ( ValTy , dl , DAG . getEntryNode ( ) , GA , MachinePointerInfo ( ) , false , false , false , <NUM_LIT> ) ; if ( ! HasGotOfst ) return ResNode ; SDValue GALo = DAG . getTargetGlobalAddress ( GV , dl , ValTy , <NUM_LIT> , Has<ISA_LIT>64 ?


<s> if ( ! is<ISA_LIT>Register ( ( insn >> <NUM_LIT> ) & <NUM_LIT> ) ) return UNSUPPORTED ; return get<ISA_LIT>RegisterFromNumbering ( ( insn >> <NUM_LIT> ) & <NUM_LIT>


<s> MachineBasicBlock & MBB = * MI . getParent ( ) ; DebugLoc DL = MI . getDebugLoc ( ) ; unsigned Dst = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Src = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; BuildMI ( MBB , MBB . getFirstNonPHI ( ) , DL , TII -> get ( <STR_LIT> ) , Dst ) . addReg ( Src ) ; if ( ExecModified ) { BuildMI ( MBB , & MI , DL , TII -> get ( <STR_LIT> ) , Dst ) . addReg ( <STR_LIT> ) . addReg ( Dst ) ; } BuildMI ( MBB , & MI , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( Dst ) ; Skip ( MI , MI . getOperand ( <NUM_LIT> ) ) ; BuildMI ( MBB , & MI , DL , TII -> get ( <STR_LIT> ) ) . addOperand ( MI . getOperand ( <NUM_LIT> ) ) . addReg ( Dst ) ; MI . eraseFromParent (


<s> case 'J' : case 'K' : case 'L' : case 'M' : case 'N' : case 'O' : if ( isa < ConstantInt > ( CallOperandVal ) ) weight = CW_Constant ; break ; } return


<s> return ( __mmask32 ) __builtin_ia32_kandsi ( ( __mmask32 ) __A , (


<s> unsigned <ISA_LIT>MCCodeEmitter :: getMachineOpValue ( const MCInst & MI , const MCOperand & MO , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { if ( MO . isReg ( ) ) return MRI . getEncodingValue ( MO . getReg ( ) ) ; if ( MO . isImm ( ) ) return static_cast < unsigned > ( MO . getImm ( ) ) ; assert ( MO . isExpr ( ) ) ; const MCExpr * Expr = MO . getExpr ( ) ; assert ( Expr -> getKind ( ) == MCExpr :: SymbolRef ) ; if ( MI . getOpcode ( ) == <STR_LIT> ) Fixups . push_back ( MCFixup :: create ( <NUM_LIT> ,


<s> SDValue BasePtr = LD -> getBasePtr ( ) ; Align Alignment = LD -> getOriginalAlign ( ) ; MachineMemOperand :: Flags MMOFlags = LD -> getMemOperand ( ) -> getFlags ( ) ; AAMDNodes AAInfo = LD -> getAAInfo ( ) ; SDValue Offset = DAG . getUNDEF ( BasePtr . getValueType ( ) ) ; EVT NewFromVT = EVT :: getVectorVT ( C , EVT :: getIntegerVT ( C , FromEltVT . getScalarSizeInBits ( ) ) , NumElements ) ; EVT NewToVT = EVT :: getVectorVT ( C , EVT :: getIntegerVT ( C , ToEltVT . getScalarSizeInBits ( ) ) , NumElements ) ; SmallVector < SDValue , <NUM_LIT> > Loads ; SmallVector < SDValue , <NUM_LIT> > Chains ; for ( unsigned i = <NUM_LIT> ; i < FromVT . getVectorNumElements ( ) / NumElements ; i ++ ) { unsigned NewOffset = ( i * NewFromVT . getSizeInBits ( ) ) / <NUM_LIT> ; SDValue NewPtr = DAG . getObjectPtrOffset ( DL , BasePtr , TypeSize :: Fixed ( NewOffset ) ) ; SDValue NewLoad = DAG . getLoad ( <STR_LIT> , NewExtType , NewToVT , DL , Ch , NewPtr , Offset , LD -> getPointerInfo ( ) . getWithOffset ( NewOffset ) , NewFromVT , Alignment , MMOFlags , AAInfo ) ; Loads . push_back ( NewLoad ) ; Chains . push_back ( SDValue ( NewLoad . getNode ( ) , <NUM_LIT> ) ) ; } SDValue NewChain = DAG . getNode ( <STR_LIT> , DL


<s> Instruction & Inst = * I ; if ( const ReturnInst * RI = dyn_cast < ReturnInst > ( I ) ) { Value * RVal = RI -> getReturnValue ( ) ; if ( ! RVal ) continue ; Type * T = RVal -> getType ( ) ; FPReturnVariant RV = whichFPReturnVariant ( T ) ; if ( RV == NoFPRet ) continue ; static const char * Helper [ NoFPRet ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; const char * Name = Helper [ RV ] ; AttributeSet A ; Value * Params [ ] = { RVal } ; Modified = true ; A = A . addAttribute ( C , AttributeSet :: FunctionIndex , <STR_LIT> ) ; A = A . addAttribute ( C , AttributeSet :: FunctionIndex , Attribute :: ReadNone ) ; A = A . addAttribute ( C , AttributeSet :: FunctionIndex , Attribute :: NoInline ) ; Value * F = ( M -> getOrInsertFunction ( Name , A , MyVoid , T , NULL ) ) ; CallInst :: Create ( F , Params , <STR_LIT> , & Inst ) ; } else if ( const CallInst * CI = dyn_cast < CallInst > ( I ) ) { if ( Subtarget . getRelocationModel ( ) != Reloc :: PIC_ ) { Function * F_ = CI -> getCalledFunction ( ) ; if ( F_ && ! isIntrinsicInline ( F_ ) &&


<s> virtual bool ShouldShrinkFPConstant ( MVT VT ) const { return ! <ISA_LIT>ScalarSSEf64 || VT ==


<s> bool isSuitableForJumpTable ( const SwitchInst * SI , uint64_t NumCases , uint64_t Range ) const override { return false


<s> return ( __m512i ) __builtin_ia32_vcvttph2w512_mask_round ( __A , ( __v32hi ) _mm512_setzero_si512 ( ) , ( __mmask32 ) -


<s> int BitOffset = BroadcastIdx * NumEltBits ; SDValue V = V1 ; for ( ; ; ) { switch ( V . getOpcode ( ) ) { case <STR_LIT> : { V = V . getOperand ( <NUM_LIT> ) ; continue ; } case <STR_LIT> : { int OpBitWidth = V . getOperand ( <NUM_LIT> ) . getValueSizeInBits ( ) ; int OpIdx = BitOffset / OpBitWidth ; V = V . getOperand ( OpIdx ) ; BitOffset %= OpBitWidth ; continue ; } case <STR_LIT> : { SDValue VOuter = V . getOperand ( <NUM_LIT> ) , VInner = V . getOperand ( <NUM_LIT> ) ; auto ConstantIdx = dyn_cast < ConstantSDNode > ( V . getOperand ( <NUM_LIT> ) ) ; if ( ! ConstantIdx ) break ; int EltBitWidth = VOuter . getScalarValueSizeInBits ( ) ; int Idx = ( int ) ConstantIdx -> getZExtValue ( ) ; int NumSubElts = ( int ) VInner . getSimpleValueType ( ) . getVectorNumElements ( ) ; int BeginOffset = Idx * EltBitWidth ; int EndOffset = BeginOffset + NumSubElts * EltBitWidth ; if ( BeginOffset <= BitOffset && BitOffset < EndOffset ) { BitOffset -= BeginOffset ; V = VInner ; } else { V = VOuter ; } continue ; } } break ; } assert ( ( BitOffset % NumEltBits ) == <NUM_LIT> && <STR_LIT> ) ; BroadcastIdx = BitOffset / NumEltBits ; bool BitCastSrc = V . getScalarValueSizeInBits ( ) != NumEltBits ; if ( BitCastSrc && VT . isInteger ( ) ) if ( SDValue TruncBroadcast = lowerShuffleAsTruncBroadcast ( DL , VT , V , BroadcastIdx , Subtarget , DAG ) ) return TruncBroadcast ; MVT BroadcastVT = VT ; if ( ! BitCastSrc && ( ( V . getOpcode ( ) == <STR_LIT> && V . hasOneUse ( ) ) || ( V . getOpcode ( ) == <STR_LIT> && BroadcastIdx == <NUM_LIT> ) ) ) { V = V . getOperand ( BroadcastIdx ) ; if ( ! BroadcastFromReg && ! isShuffleFoldableLoad ( V ) ) return SDValue ( ) ; } else if ( <STR_LIT> ( V . getNode ( ) ) && cast <


<s> } } else if ( SubIndices [ <NUM_LIT> ] == <STR_LIT> ) { if ( Size == <NUM_LIT> && SubIndices [ <NUM_LIT> ] == <STR_LIT> ) { NewSubIdx = <STR_LIT> ; return true ; } } else if ( SubIndices [ <NUM_LIT> ] == <STR_LIT> ) { if ( Size >= <NUM_LIT> && SubIndices [ <NUM_LIT> ] == <STR_LIT> ) { if ( Size >= <NUM_LIT> ) NewSubIdx = <STR_LIT> ; return true ; } } else if ( SubIndices [ <NUM_LIT> ] == <STR_LIT> ) { if ( Size >= <NUM_LIT> && SubIndices [ <NUM_LIT> ] == <STR_LIT> ) { NewSubIdx = <STR_LIT> ; return true ; } } else if ( SubIndices [ <NUM_LIT> ] == <STR_LIT> ) { if ( Size == <NUM_LIT> && SubIndices [ <NUM_LIT> ] == <STR_LIT> ) { NewSubIdx = <STR_LIT> ; return true ; } } else if ( SubIndices [ <NUM_LIT> ] == <STR_LIT> ) { if ( Size == <NUM_LIT> && SubIndices [ <NUM_LIT> ] == <STR_LIT> ) { NewSubIdx = <STR_LIT> ; return true ; } } else if ( SubIndices [ <NUM_LIT> ] == <STR_LIT> ) { if ( SubIndices [ <NUM_LIT> ] == <STR_LIT> ) { if ( Size >= <NUM_LIT> ) NewSubIdx = <STR_LIT> ; return true ; } } else if ( SubIndices [ <NUM_LIT> ] == <STR_LIT> ) { if ( Size >= <NUM_LIT> && SubIndices [ <NUM_LIT> ] == <STR_LIT> ) { NewSubIdx =


<s> } assert ( DCI . isBeforeLegalize ( ) && <STR_LIT> ) ; unsigned NElts = SrcVT . getVectorNumElements ( ) ; if ( ! SrcVT . isSimple ( ) && NElts != <NUM_LIT> ) return SDValue ( ) ; if ( <STR_LIT> ( Src . getNode ( ) ) && Src . hasOneUse ( ) ) { EVT LoadVT = getEquivalentMemType ( * DAG . getContext ( ) , SrcVT ) ; EVT RegVT = getEquivalentLoadRegType ( * DAG . getContext ( ) , SrcVT ) ; EVT FloatVT = EVT :: getVectorVT ( * DAG . getContext ( ) , <STR_LIT> , NElts ) ; LoadSDNode * Load = cast < LoadSDNode > ( Src ) ; unsigned AS = Load -> getAddressSpace ( ) ; unsigned Align = Load -> getAlignment ( ) ; Type * Ty = LoadVT . getTypeForEVT ( * DAG . getContext ( ) ) ; unsigned ABIAlignment = getDataLayout ( ) -> getABITypeAlignment ( Ty ) ; if ( Align < ABIAlignment && ! allowsMisalignedMemoryAccesses ( LoadVT , AS , Align , nullptr ) ) { return SDValue ( ) ; } SDValue NewLoad = DAG . getExtLoad ( <STR_LIT> , DL , RegVT , Load -> getChain ( ) , Load -> getBasePtr ( )

, LoadVT , Load -> getMemOperand ( ) ) ;


<s> if ( SymName . startswith ( <STR_LIT> ) ) return ; auto CWS = cast < MCSectionWasm > ( getStreamer ( ) . getCurrentSection ( ) . first ) ; if ( ! CWS || ! CWS -> getKind ( ) . isText ( ) ) return ; auto SecName = <STR_LIT>


<s> FOR_EACH_VEC_ELT ( * ( sec -> relocs ) ,

i , bpfcr ) output_asm_btfext_core_reloc ( bpfcr ) ;


<s> if ( BasePtrIncConstantSCEV ) IsConstantInc = true ; if ( ! IncNode ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return std :: make_pair ( nullptr , nullptr ) ; } if ( Form == UpdateForm && ! IsConstantInc && ! EnableUpdateFormForNonConstInc ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return std :: make_pair ( nullptr , nullptr ) ; } const SCEV * BasePtrStartSCEV = nullptr ; if ( CanPreInc ) { assert ( SE -> isLoopInvariant ( BasePtrIncSCEV , L ) && <STR_LIT> ) ; BasePtrStartSCEV = SE -> getMinusSCEV ( BasePtrSCEV -> getStart ( ) , IsConstantInc ? BasePtrIncConstantSCEV : BasePtrIncSCEV ) ; } else BasePtrStartSCEV = BasePtrSCEV -> getStart ( ) ; if ( alreadyPrepared ( L , BaseMemI , BasePtrStartSCEV , BasePtrIncSCEV , Form ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return std :: make_pair ( nullptr , nullptr ) ; } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * BasePtrStartSCEV << <STR_LIT> ) ; BasicBlock * Header = L -> getHeader ( ) ; unsigned HeaderLoopPredCount = pred_size ( Header ) ; BasicBlock * LoopPredecessor = L -> getLoopPredecessor ( ) ; PHINode * NewPHI = PHINode :: Create ( I8PtrTy , HeaderLoopPredCount , getInstrName ( BaseMemI , PHINodeNameSuffix ) , Header -> getFirstNonPHI ( ) ) ; Value * BasePtrStart = SCEVE . expandCodeFor ( BasePtrStartSCEV , I8PtrTy , LoopPredecessor -> getTerminator ( ) ) ; for ( auto PI : predecessors ( Header ) ) { if ( PI != LoopPredecessor ) continue ; NewPHI -> addIncoming ( BasePtrStart , LoopPredecessor ) ; } Instruction * PtrInc = nullptr ; Instruction * NewBasePtr = nullptr ; if ( CanPreInc ) { Instruction * InsPoint = & * Header


<s> void addMemRegOffsetOperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT> ) ; unsigned Val = <STR_LIT> ( Memory . isNegative ? <STR_LIT> : <STR_LIT> , Memory . ShiftImm ,


<s> bool <ISA_LIT>DAGToDAGISel :: hasAllNBitUsers ( SDNode * Node , unsigned Bits ) const { assert ( ( Node -> getOpcode ( ) == <STR_LIT> || Node -> getOpcode ( ) == <STR_LIT> || Node -> getOpcode ( ) == <STR_LIT> || Node -> getOpcode ( ) == <STR_LIT> || Node -> getOpcode ( ) == <STR_LIT> || Node -> getOpcode ( ) == <STR_LIT> || isa < ConstantSDNode > ( Node ) ) && <STR_LIT> ) ; for ( auto UI = Node -> use_begin ( ) , UE = Node -> use_end ( ) ; UI != UE ; ++ UI ) { SDNode * User = * UI ; if ( ! User -> isMachineOpcode ( ) ) return false ; switch ( User -> getMachineOpcode (


<s> OpIdx = <NUM_LIT> ; unsigned Base = getRegisterEnum ( B , <STR_LIT> , decodeRn ( insn ) ) ; if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ) { MI . addOperand ( MCOperand :: CreateReg ( Base ) ) ; ++ OpIdx ; } MI . addOperand ( MCOperand :: CreateReg ( Base ) ) ; <STR_LIT> SubMode = getAMSubModeForBits ( getPUBits ( insn ) ) ; if ( SubMode != <STR_LIT> && SubMode != <STR_LIT> ) { DEBUG ( errs ( ) << <STR_LIT> ) ; return false ; } unsigned char Imm8 = insn & <NUM_LIT> ; MI . addOperand ( MCOperand :: CreateImm ( <STR_LIT> ( SubMode , Imm8 ) ) ) ; int64_t CondVal = insn >> <STR_LIT> ; MI . addOperand ( MCOperand :: CreateImm ( CondVal == <NUM_LIT> ? <NUM_LIT> : CondVal ) ) ; MI . addOperand ( MCOperand :: CreateReg ( <STR_LIT> ) ) ; OpIdx += <NUM_LIT> ; bool isSPVFP = ( Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ) ? true : false ; unsigned RegClassID = isSPVFP ? <STR_LIT> : <STR_LIT> ; unsigned RegD = decodeVFPRd ( insn , isSPVFP


<s> std :: unique_ptr < MCObjectTargetWriter > llvm

:: create<ISA_LIT>ELFObjectWriter ( uint8_t OSABI ) {


<s> unsigned OpFlags = Subtarget -> ClassifyGlobalReference ( GV , TM ) ; EVT DestEVT = TLI . getValueType ( DL , GV -> getType ( ) , true ) ; if ( ! DestEVT . isSimple ( ) ) return <NUM_LIT> ; unsigned ADRPReg = createResultReg ( & <STR_LIT> ) ; unsigned ResultReg ; if ( OpFlags & <STR_LIT> ) { BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , ADRPReg ) . addGlobalAddress ( GV , <NUM_LIT> , <STR_LIT> | OpFlags ) ; unsigned LdrOpc ; if ( Subtarget -> isTargetILP32 ( ) ) { ResultReg = createResultReg ( & <STR_LIT> ) ; LdrOpc = <STR_LIT> ; } else { ResultReg = createResultReg ( & <STR_LIT> ) ; LdrOpc = <STR_LIT> ; } BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( LdrOpc ) , ResultReg ) . addReg ( ADRPReg )

. addGlobalAddress ( GV , <NUM_LIT> , <STR_LIT> | <STR_LIT> | <STR_LIT> | OpFlags ) ;


<s> const TargetRegisterClass * <ISA_LIT>RegisterInfo :: getPointerRegClass ( const MachineFunction


<s> V0 = RegInfo . createVirtualRegister ( RC ) ; V1 = RegInfo . createVirtualRegister ( RC ) ; V2 = RegInfo . createVirtualRegister ( RC ) ; BuildMI ( MBB , I , DL , TII . get ( <STR_LIT> ) , V0 ) . addExternalSymbol ( <STR_LIT> , <STR_LIT> ) ; BuildMI ( MBB , I , DL , TII . get ( <STR_LIT> ) , V1 )


<s> } Len /= EltSize ; Idx /= EltSize ; for ( int i = <NUM_LIT> ; i != Len ; ++ i ) ShuffleMask . push_back ( i + Idx ) ; for ( int i = Len ; i != ( int ) HalfElts ; ++ i ) ShuffleMask


<s> unsigned MinGPR = <STR_LIT> ; unsigned MinG8R = <STR_LIT> ; unsigned MinFPR = <STR_LIT> ; unsigned MinVR = Subtarget . hasSPE ( ) ? <STR_LIT> : <STR_LIT> ; bool HasGPSaveArea = false ; bool HasG8SaveArea = false ; bool HasFPSaveArea = false ; bool HasVRSaveArea = false ; SmallVector < CalleeSavedInfo , <NUM_LIT> > GPRegs ; SmallVector < CalleeSavedInfo , <NUM_LIT> > G8Regs ; SmallVector < CalleeSavedInfo , <NUM_LIT> > FPRegs ; SmallVector < CalleeSavedInfo , <NUM_LIT> > VRegs ; for ( const CalleeSavedInfo & I : CSI ) { Register Reg = I . getReg ( ) ; assert ( ( ! MF . getInfo < <ISA_LIT>FunctionInfo > ( ) -> mustSaveTOC ( ) || ( Reg != <STR_LIT> && Reg != <STR_LIT> ) ) && <STR_LIT> ) ; if ( <STR_LIT> . contains ( Reg ) ) { HasGPSaveArea = true ; GPRegs . push_back ( I ) ; if ( Reg < MinGPR ) { MinGPR = Reg ; } } else if ( <STR_LIT> . contains ( Reg ) ) { HasG8SaveArea = true ; G8Regs . push_back ( I ) ; if ( Reg < MinG8R ) { MinG8R = Reg ; } } else if ( <STR_LIT> . contains ( Reg ) ) { HasFPSaveArea = true ; FPRegs . push_back ( I ) ; if ( Reg < MinFPR ) { MinFPR = Reg ; } } else if ( <STR_LIT> . contains ( Reg ) || <STR_LIT> . contains ( Reg ) ) { ; } else if ( <STR_LIT> . contains ( Reg ) || <STR_LIT> . contains ( Reg ) ) { HasVRSaveArea = true ; VRegs . push_back ( I ) ; if ( Reg < MinVR ) { MinVR = Reg ; } } else { llvm_unreachable ( <STR_LIT> ) ; } } <ISA_LIT>FunctionInfo * PFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; const TargetRegisterInfo * TRI = Subtarget . getRegisterInfo ( ) ; int64_t LowerBound = <NUM_LIT> ; int TCSPDelta = <NUM_LIT> ; if ( MF . getTarget ( ) . Options . GuaranteedTailCallOpt && ( TCSPDelta = PFI -> getTailCallSPDelta ( ) ) < <NUM_LIT> ) { LowerBound =


<s> assert ( MI . getOpcode ( ) == <STR_LIT> ) ; return cast < Function > ( MI . getOperand ( <NUM_LIT> ) . getGlobal


<s> const Triple & TT = TM . getTargetTriple ( ) ; if ( TT . isOSBinFormatMachO ( ) ) { OutStreamer -> EmitAssemblerFlag ( MCAF_SubsectionsViaSymbols ) ; SM . serializeToStackMapSection ( ) ; } if ( TT . isOSBinFormatCOFF ( ) ) { const auto & TLOF = static_cast < const TargetLoweringObjectFileCOFF & > ( getObjFileLowering ( ) ) ; std :: string Flags ; raw_string_ostream OS ( Flags ) ; for ( const auto & Function : M ) TLOF . emitLinkerFlagsForGlobal ( OS , & Function ) ; for ( const auto & Global : M . globals ( ) ) TLOF . emitLinkerFlagsForGlobal


<s> rtx reg = gen_rtx_REG ( Pmode , regno ) ; rtx lr = gen_rtx_REG ( Pmode , LR_REGNO ) ; rtx_insn * insn = emit_move_insn ( lr ,


<s> void WaitcntBrackets :: determineWait ( InstCounterType T , uint32_t ScoreToWait , <STR_LIT> & Wait ) const { const uint32_t LB = getScoreLB ( T ) ; const uint32_t UB = getScoreUB ( T ) ; if ( ( UB >= ScoreToWait ) && ( ScoreToWait > LB ) ) { if ( ( T == VM_CNT || T == LGKM_CNT ) && hasPendingFlat ( ) && ! ST -> hasFlatLgkmVMemCountInOrder ( ) ) { addWait ( Wait , T , <NUM_LIT> ) ; } else if ( counterOutOfOrder ( T ) ) { addWait ( Wait , T , <NUM_LIT> ) ; } else


<s> unsigned <ISA_LIT>ABIInfo :: GetPtrAddiuOp


<s> if ( SourceVecs [ i ] . getValueType ( ) . getVectorElementType ( ) != VT . getVectorElementType ( ) ) return SDValue ( ) ; assert ( SourceVecs [ i ] . getValueType ( ) . getVectorNumElements ( ) == <NUM_LIT> * NumElts && <STR_LIT> ) ; if ( MaxElts [ i ] - MinElts [ i ] >= NumElts ) { return SDValue ( ) ; } if ( MinElts [ i ] >= NumElts ) { VEXTOffsets [ i ] = NumElts ; ShuffleSrcs [ i ] = DAG . getNode ( <STR_LIT> , dl , VT , SourceVecs [ i ] , DAG . getIntPtrConstant ( NumElts ) ) ; } else if ( MaxElts [ i ] < NumElts ) { VEXTOffsets [ i ] = <NUM_LIT> ; ShuffleSrcs [ i ] = DAG . getNode ( <STR_LIT> , dl , VT , SourceVecs [ i ] , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; } else { VEXTOffsets [ i ] = MinElts [ i ] ; SDValue VEXTSrc1 = DAG . getNode ( <STR_LIT> , dl , VT , SourceVecs [ i ] , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; SDValue VEXTSrc2 = DAG . getNode ( <STR_LIT> , dl , VT , SourceVecs [ i ] , DAG . getIntPtrConstant ( NumElts ) ) ; unsigned Imm = VEXTOffsets [ i ] * getExtFactor ( VEXTSrc1 ) ; ShuffleSrcs [ i ] = DAG . getNode ( <STR_LIT> , dl , VT , VEXTSrc1 , VEXTSrc2 , DAG . getConstant ( Imm , <STR_LIT> ) ) ; } } SmallVector < int , <NUM_LIT> > Mask ; for ( unsigned i = <NUM_LIT> ; i < NumElts ; ++ i ) { SDValue Entry = Op . getOperand ( i ) ; if ( Entry . getOpcode ( ) == <STR_LIT> ) { Mask . push_back ( - <NUM_LIT> ) ; continue ; } SDValue ExtractVec = Entry . getOperand ( <NUM_LIT> ) ; int ExtractElt = cast < ConstantSDNode > ( Op . getOperand ( i ) . getOperand ( <NUM_LIT> ) ) -> getSExtValue ( ) ; if ( ExtractVec == SourceVecs [ <NUM_LIT> ] ) { Mask . push_back ( ExtractElt - VEXTOffsets [ <NUM_LIT> ] ) ; } else


<s> const TargetAsmInfo * <ISA_LIT>TargetMachine :: createTargetAsmInfo ( ) const { if ( Subtarget . isFlavorIntel ( ) ) return new <ISA_LIT>WinTargetAsmInfo ( * this ) ; else switch ( Subtarget .


<s> return <STR_LIT> ; } virtual bool runOnMachineFunction ( MachineFunction & MF ) ; virtual void EmitConstantPool ( ) override { bool UsingConstantPools = ( Subtarget -> in<ISA_LIT>16Mode ( ) && Subtarget -> useConstantIslands ( ) ) ; if ( ! UsingConstantPools ) AsmPrinter :: EmitConstantPool ( ) ; } void EmitInstruction ( const MachineInstr * MI ) ; void printSavedRegsBitmask ( ) ; void emitFrameDirective ( ) ; const char * getCurrentABIString ( ) const ; virtual void EmitFunctionEntryLabel ( ) ; virtual void EmitFunctionBodyStart ( ) ; virtual void EmitFunctionBodyEnd ( ) ; virtual bool isBlockOnlyReachableByFallthrough ( const MachineBasicBlock * MBB ) const ; bool PrintAsmOperand ( const MachineInstr * MI , unsigned OpNo , unsigned AsmVariant , const char * ExtraCode , raw_ostream & O ) ; bool PrintAsmMemoryOperand ( const MachineInstr * MI , unsigned OpNum , unsigned AsmVariant , const char * ExtraCode , raw_ostream & O ) ; void printOperand ( const MachineInstr * MI , int opNum , raw_ostream & O ) ; void printUnsignedImm ( const MachineInstr * MI , int opNum , raw_ostream & O ) ; void printUnsignedImm8 ( const MachineInstr * MI , int opNum , raw_ostream & O ) ; void printMemOperand ( const MachineInstr * MI , int opNum , raw_ostream & O ) ; void printMemOperandEA ( const MachineInstr * MI , int opNum , raw_ostream & O ) ; void printFCCOperand ( const MachineInstr * MI , int opNum , raw_ostream & O , const char * Modifier = <NUM_LIT> ) ; void EmitStartOfAsmFile ( Module & M ) ; void EmitEndOfAsmFile ( Module & M ) ; void PrintDebugValueComment ( const MachineInstr * MI ,


<s> EVT IntEltVT = SplatVT . getVectorElementType ( ) ; EVT BoolVT = EVT :: getIntegerVT ( * DAG . getContext ( ) , <NUM_LIT> ) ; EVT PredVT = SplatVT . changeVectorElementType ( BoolVT ) ; SDValue Splat = DAG . getNode ( <STR_LIT> , DL , SplatVT , DAG . getNode ( <STR_LIT> , DL , IntEltVT , InElem ) ) ; SDValue SplatIdx = DAG . getNode ( <STR_LIT> , DL , SplatVT , DAG . getZExtOrTrunc ( InIdx , DL , IntEltVT ) ) ; SDValue Zero = DAG . getConstant ( <NUM_LIT> , DL , IntEltVT ) ; SDValue One = DAG . getConstant ( <NUM_LIT> , DL , IntEltVT ) ; SDValue Seq = DAG . getNode ( <STR_LIT> , DL , SplatVT , Zero , One ) ; SDValue Cmp = DAG . getNode ( <STR_LIT> , DL , PredVT , SplatIdx , Seq , DAG .


<s> unsigned rD = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned rS = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; int imm14 = SignExtend32 < <NUM_LIT> > ( ( Insn >> <NUM_LIT> ) & <NUM_LIT> ) ; rD = get<ISA_LIT>RegisterFromNumbering ( rD ) ; rS = get<ISA_LIT>RegisterFromNumbering ( rS ) ; Inst . addOperand ( MCOperand ::


<s> bool MVEVPTBlock :: InsertVPTBlocks ( MachineBasicBlock & Block ) { bool Modified = false ; MachineBasicBlock :: instr_iterator MBIter = Block . instr_begin ( ) ; MachineBasicBlock :: instr_iterator EndIter = Block . instr_end ( ) ; while ( MBIter != EndIter ) { MachineInstr * MI = & * MBIter ; unsigned PredReg = <NUM_LIT> ; DebugLoc dl = MI -> getDebugLoc ( ) ; <STR_LIT> Pred = getVPTInstrPredicate ( * MI , PredReg ) ; assert ( Pred != <STR_LIT> && <STR_LIT> ) ; if ( Pred == <STR_LIT> ) { ++ MBIter ; continue ; } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; MI -> dump ( ) ) ; int VPTInstCnt = <NUM_LIT> ; <STR_LIT> NextPred ; ++ MBIter ; while ( MBIter != EndIter && VPTInstCnt < <NUM_LIT> ) { NextPred = getVPTInstrPredicate ( * MBIter , PredReg ) ; assert ( NextPred != <STR_LIT> && <STR_LIT> ) ; if ( NextPred != Pred ) break ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; MBIter -> dump ( ) ) ; ++ VPTInstCnt ; ++ MBIter ; } ; unsigned BlockMask = <NUM_LIT> ; switch ( VPTInstCnt ) { case <NUM_LIT> : BlockMask = VPTMaskValue :: T ; break ; case <NUM_LIT> : BlockMask = VPTMaskValue :: TT ; break ; case <NUM_LIT> : BlockMask = VPTMaskValue :: TTT ; break ; case <NUM_LIT> : BlockMask = VPTMaskValue :: TTTT ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } ; MachineInstrBuilder MIBuilder ; unsigned NewOpcode ; MachineInstr * VCMP = findVCMPToFoldIntoVPST ( MI , TRI , NewOpcode ) ; if ( VCMP ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; VCMP -> dump ( ) ) ; MIBuilder = BuildMI ( Block , MI , dl , TII -> get ( NewOpcode ) ) ; MIBuilder . addImm ( BlockMask ) ; MIBuilder . add ( VCMP -> getOperand


<s> auto TmpReg = MRI -> createGenericVirtualRegister ( LLT :: scalar ( <NUM_LIT> ) ) ; auto tmpStructTy = GR . getPairStruct ( elem0Ty , elem0Ty , MIRBuilder ) ; bool Success = MIRBuilder . buildInstr ( NewOpcode ) . addDef ( TmpReg ) . addUse ( GR . get<ISA_LIT>TypeID ( tmpStructTy ) ) . addUse ( I . getOperand ( <NUM_LIT> ) . getReg ( ) ) . addUse ( I . getOperand ( <NUM_LIT> ) . getReg ( ) ) . constrainAllUses ( TII , TRI , RBI ) ; auto elem0Reg = MRI -> createGenericVirtualRegister ( LLT :: scalar ( <NUM_LIT> ) ) ; Success &= MIRBuilder . buildInstr ( OpCompositeExtract ) . addDef ( elem0Reg ) . addUse ( GR . get<ISA_LIT>TypeID ( elem0Ty ) ) . addUse ( TmpReg ) . addImm ( <NUM_LIT> ) . constrainAllUses ( TII , TRI , RBI ) ; auto elem1Reg = MRI -> createGenericVirtualRegister ( LLT :: scalar ( <NUM_LIT> ) ) ; Success &= MIRBuilder . buildInstr ( OpCompositeExtract ) . addDef ( elem1Reg ) . addUse ( GR . get<ISA_LIT>TypeID ( elem0Ty ) ) . addUse ( TmpReg ) . addImm ( <NUM_LIT> ) . constrainAllUses ( TII , TRI , RBI ) ; auto BoolReg = MRI -> createGenericVirtualRegister ( LLT


<s> unsigned Mask = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> ; i < Bits . size ( ) ; ++ i ) { if ( ! Bits [ i ] . hasValue ( ) || Bits [ i ] . getValue ( ) != VRI . V ) continue ; if ( RLAmt [ i ] != VRI . RLAmt ) continue ; Mask |= ( <NUM_LIT> << i ) ; } unsigned ANDIMask = ( Mask & UINT16_MAX ) , ANDISMask = Mask >> <NUM_LIT> ; assert ( ( ANDIMask != <NUM_LIT> || ANDISMask != <NUM_LIT> ) && <STR_LIT> ) ; bool NeedsRotate = VRI . RLAmt != <NUM_LIT> ; unsigned NumAndInsts = ( unsigned ) NeedsRotate + ( unsigned ) ( ANDIMask != <NUM_LIT> ) + ( unsigned ) ( ANDISMask != <NUM_LIT> ) + ( unsigned ) ( ANDIMask != <NUM_LIT> && ANDISMask != <NUM_LIT> ) + ( unsigned ) ( bool ) Res ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << VRI . V . getNode ( ) << <STR_LIT> << VRI . RLAmt << <STR_LIT> << <STR_LIT> << NumAndInsts << <STR_LIT> << VRI . NumGroups << <STR_LIT> ) ; if ( NumAndInsts >= VRI . NumGroups ) continue ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; if ( InstCnt ) * InstCnt += NumAndInsts ; SDValue VRot ; if ( VRI . RLAmt ) { SDValue Ops [ ] = { TruncateToInt32 ( VRI . V , dl ) , getI32Imm ( VRI . RLAmt , dl ) , getI32Imm ( <NUM_LIT> , dl ) , getI32Imm ( <NUM_LIT> , dl ) } ; VRot = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , Ops ) , <NUM_LIT> ) ; } else { VRot = TruncateToInt32 ( VRI . V , dl


<s> if ( RegNo > <NUM_LIT> ) return MCDisassembler :: Fail ; unsigned Reg = GPRDecoderTable


<s> bool isUImm9Lsb0 ( ) const { return ( isConstantImm ( ) && isShiftedUInt < <NUM_LIT> , <NUM_LIT> > ( getConstantImm (


<s> want_long = <NUM_LIT> ; } if ( final_sequence && ! INSN_ANNULLED_BRANCH_P ( insn ) && ( get_attr_cond ( insn ) != COND_USE || ! reg_set_p ( gen_rtx_REG ( CCmode , CC_REG ) , XVECEXP ( final_sequence , <NUM_LIT> , <NUM_LIT> ) ) ) ) { prev = as_a < rtx_insn * > ( XVECEXP ( final_sequence , <NUM_LIT> , <NUM_LIT> ) ) ; gcc_assert ( ! prev_real_insn ( insn ) || ! arc_hazard ( prev_real_insn ( insn ) , prev ) ) ; cfun -> machine -> force_short_suffix = ! want_long ; rtx save_pred = current_insn_predicate ; final_scan_insn ( prev , asm_out_file , optimize , <NUM_LIT> , NULL ) ; cfun -> machine -> force_short_suffix = - <NUM_LIT> ; prev -> set_deleted ( ) ; current_output_insn = insn ; current_insn_predicate = save_pred ; } else if ( want_long ) fputs ( <STR_LIT> ,


<s> if ( CLI . RetTy -> isVoidTy ( ) ) RetVT = <STR_LIT> ; else if ( ! isTypeLegal ( CLI . RetTy , RetVT ) ) return false ; for ( auto Flag : CLI . OutFlags ) if ( Flag . isInReg ( ) || Flag . isSRet ( ) || Flag . isNest ( ) || Flag . isByVal ( ) || Flag . isSwiftSelf ( ) || Flag . isSwiftError ( ) ) return false ; SmallVector < MVT , <NUM_LIT> > OutVTs ; OutVTs . reserve ( CLI . OutVals . size ( ) ) ; for ( auto * Val : CLI . OutVals ) { MVT VT ; if ( ! isTypeLegal ( Val -> getType ( ) , VT ) && ! ( VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> ) ) return false ; if ( VT . isVector ( ) || VT . getSizeInBits ( ) > <NUM_LIT> ) return false ; OutVTs . push_back ( VT ) ; } Address Addr ; if ( Callee && ! computeCallAddress ( Callee , Addr ) ) return false ; unsigned NumBytes ; if ( ! processCallArgs ( CLI , OutVTs , NumBytes ) ) return false ; MachineInstrBuilder MIB ; if ( CM == CodeModel :: Small ) { const MCInstrDesc & II = TII . get ( Addr . getReg ( ) ? <STR_LIT> : <STR_LIT> ) ; MIB = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , II ) ; if ( Symbol ) MIB . addSym ( Symbol , <NUM_LIT> ) ; else if ( Addr . getGlobalValue ( ) ) MIB . addGlobalAddress ( Addr . getGlobalValue ( ) , <NUM_LIT> , <NUM_LIT> ) ; else if ( Addr . getReg ( ) ) { unsigned Reg = constrainOperandRegClass ( II , Addr . getReg ( ) , <NUM_LIT> ) ; MIB . addReg ( Reg ) ; } else return false ; } else { unsigned CallReg = <NUM_LIT> ; if ( Symbol ) { unsigned ADRPReg = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , ADRPReg ) . addSym ( Symbol , <STR_LIT> | <STR_LIT> ) ; CallReg = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , CallReg ) . addReg ( ADRPReg ) . addSym ( Symbol , <STR_LIT> | <STR_LIT> | <STR_LIT> ) ; } else if ( Addr . getGlobalValue ( ) ) CallReg =

materializeGV ( Addr . getGlobalValue ( ) ) ;


<s> const <ISA_LIT>Z80RegisterInfo * getRegisterInfo ( ) const override { return & InstrInfo . getRegisterInfo (


<s> void <ISA_LIT>InstPrinter :: printT2SOOperand ( const MCInst * MI , unsigned OpNum , raw_ostream & O ) { const MCOperand & MO1 = MI -> getOperand ( OpNum ) ; const MCOperand & MO2 = MI -> getOperand ( OpNum + <NUM_LIT> ) ; unsigned Reg = MO1 . getReg


<s> return new <ISA_LIT>EncodeLiteralsPass (


<s> unsigned Reg = NewDesc . ImplicitUses [ i ] ; Inst -> addOperand ( MachineOperand :: CreateReg ( Reg , false , true ) ) ; } } if ( NewDesc . ImplicitDefs ) { for ( unsigned i = <NUM_LIT> ; NewDesc . ImplicitDefs [ i ] ; ++ i ) { unsigned Reg = NewDesc . ImplicitDefs [


<s> explicit <ISA_LIT>AsmPrinter ( TargetMachine & TM , MCStreamer & Streamer ) : AsmPrinter ( TM , Streamer ) { Subtarget = & TM . getSubtarget < <ISA_LIT>Subtarget


<s> if ( TARGET_VX && GET_MODE_SIZE ( GET_MODE ( op ) ) == <NUM_LIT> && ( satisfies_constraint_j00 ( op ) || satisfies_constraint_jm1 ( op ) || satisfies_constraint_jKK ( op ) || satisfies_constraint_jxx ( op

) || satisfies_constraint_jyy ( op ) ) ) return true ;


<s> StaticCtorSection = <NUM_LIT> ; StaticDtorSection = <NUM_LIT> ; LSDASection = <NUM_LIT> ; EHFrameSection = <NUM_LIT> ; DwarfAbbrevSection = <NUM_LIT> ; DwarfInfoSection = <NUM_LIT> ; DwarfLineSection = <NUM_LIT> ; DwarfFrameSection = <NUM_LIT> ; DwarfPubTypesSection = <NUM_LIT> ; DwarfDebugInlineSection = <NUM_LIT> ; DwarfStrSection = <NUM_LIT> ; DwarfLocSection = <NUM_LIT> ; DwarfARangesSection = <NUM_LIT> ; DwarfRangesSection = <NUM_LIT> ; DwarfMacroInfoSection =


<s> return ( __mmask8 ) __builtin_ia32_cmpps128_mask ( ( __v4sf ) __X , ( __v4sf )


<s> if ( ! isRunOfOnes64 ( Imm64 , MB , ME ) ) return false ; unsigned OnesOnLeft = ME + <NUM_LIT> ; unsigned ZerosInBetween = ( MB - ME + <NUM_LIT> ) & <NUM_LIT> ; Val = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , Loc , <STR_LIT> , Val , getI64Imm ( OnesOnLeft , Loc

) , getI64Imm ( ZerosInBetween , Loc ) ) , <NUM_LIT> ) ;


<s> static bool reg_available_p ( const insn_info * insn , const vector_insn_info & info ) { if ( info . has_avl_reg ( ) && ! info . get_avl_source ( ) ) return false ; insn_info * def_insn = info . get_avl_source ( ) -> insn ( ) ; if ( def_insn -> bb ( ) == insn -> bb

( ) ) return before_p ( def_insn , insn ) ;


<s> Q . push_back ( V ) ; S . insert ( V


<s> inline static unsigned getTruncatedShiftCount ( MachineInstr * MI , unsigned ShiftAmtOperandIdx ) { unsigned ShiftCountMask = ( MI -> getDesc ( ) . TSFlags & <STR_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; unsigned Imm = MI -> getOperand ( ShiftAmtOperandIdx ) . getImm ( ) ; return Imm


<s> SRI . isValid ( ) ; ++ SRI ) if ( ! MCSubRegIterator ( * SRI , & RI ) . isValid ( ) ) Uses . insert ( * SRI ) ; if ( <ISA_LIT>MCInstrInfo :: IsReverseVecRegPair ( R ) ) ReversePairs . insert


<s> rtx hi = gen_highpart ( DImode , x ) ; rtx tmp = gen_reg_rtx ( V2DImode ) ; emit_insn ( gen_vec_concatv2di ( tmp ,


<s> const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; if ( ! DCI . isBeforeLegalize ( ) && ! TLI . isTypeLegal ( VT . getVectorElementType ( ) ) ) return SDValue ( ) ; if ( Subtarget -> hasAVX ( ) && VT . getSizeInBits ( ) == <NUM_LIT> && N -> getOpcode ( ) == <STR_LIT> ) return PerformShuffleCombine256 ( N , DAG , DCI , Subtarget -> hasAVX2 ( ) ) ; if ( VT . getSizeInBits ( ) != <NUM_LIT> ) return SDValue (


<s> static void arm_setup_incoming_varargs ( CUMULATIVE_ARGS * cum , enum machine_mode mode ATTRIBUTE_UNUSED , tree type ATTRIBUTE_UNUSED , int * pretend_size , int second_time ATTRIBUTE_UNUSED ) { cfun -> machine -> uses_anonymous_args = <NUM_LIT> ; if ( cum -> nregs < NUM_ARG_REGS ) * pretend_size

= ( NUM_ARG_REGS - cum -> nregs ) * UNITS_PER_WORD ;


<s> unsigned getInlineAsmMemConstraint ( StringRef ConstraintCode ) const override { if ( ConstraintCode == <STR_LIT> ) return InlineAsm :: Constraint_v ; return TargetLowering :: getInlineAsmMemConstraint ( ConstraintCode


<s> Init = createAString ( <STR_LIT> + std :: to_string ( index ) + <STR_LIT> + LoadStore + <STR_LIT> + printH ( p_SEL -> getAddExpr ( init , innerValueMin ) ) + <STR_LIT> , Int8Ty ) ; ATy = ArrayType :: get ( Int8Ty , Init . size ( ) ) ; llvm :: GlobalVariable * GV2 = new llvm :: GlobalVariable ( * p_M , ATy , false , GlobalValue :: ExternalLinkage , ConstantArray :: get ( ATy , Init ) , Name , GV1 ) ; Init = createAString ( <STR_LIT> + std :: to_string ( index ) + <STR_LIT> + LoadStore + <STR_LIT> + printH ( p_SEL -> getAddExpr ( init , innerValueMax ) ) + <STR_LIT> , Int8Ty ) ; ATy = ArrayType :: get ( Int8Ty , Init . size ( ) ) ; llvm :: GlobalVariable * GV3 = new llvm :: GlobalVariable ( * p_M , ATy , false , GlobalValue :: ExternalLinkage , ConstantArray :: get ( ATy , Init ) , Name , GV2 ) ; GV0 -> setSection ( <STR_LIT> ) ; GV1 -> setSection ( <STR_LIT> ) ; GV2 -> setSection ( <STR_LIT>


<s> BitVector Reserved ( getNumRegs ( ) ) ; const <ISA_LIT>FrameLowering * TFI = getFrameLowering ( MF ) ; if ( TFI -> hasFP ( MF ) ) { Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; } Reserved . set ( <STR_LIT> )


<s> long long Value = MI -> getOperand ( OpNo ) . getImm ( ) ; assert ( isInt < <NUM_LIT> > ( Value ) && <STR_LIT>


<s> for ( auto & PredMI : Insts ) { if ( PredMI . Predicates . count ( VCTP ) || isVCTP ( PredMI . MI ) ) continue ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * PredMI . MI << <STR_LIT> ; for ( auto * MI : PredMI . Predicates ) dbgs ( ) << <STR_LIT> << * MI ) ; return false ; } } if ( ! ValidateLiveOuts ( ) ) return false ; Register NumElements = VCTP -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( RDA . hasLocalDefBefore ( VCTP , NumElements ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } MachineBasicBlock * InsertBB = StartInsertPt -> getParent ( ) ; if ( ! RDA . isReachingDefLiveOut ( StartInsertPt , NumElements ) ) { if ( auto * ElemDef = RDA . getLocalLiveOutMIDef ( InsertBB , NumElements ) ) { if ( RDA . isSafeToMoveForwards ( ElemDef , StartInsertPt ) ) { ElemDef -> removeFromParent ( ) ; InsertBB -> insert ( MachineBasicBlock :: iterator ( StartInsertPt ) , ElemDef ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * ElemDef ) ; } else if ( RDA . isSafeToMoveBackwards ( StartInsertPt , ElemDef ) ) { StartInsertPt -> removeFromParent ( ) ; InsertBB -> insertAfter ( MachineBasicBlock :: iterator ( ElemDef ) , StartInsertPt ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * ElemDef ) ; } else { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << <STR_LIT> ) ; return false ; } } } auto CannotProvideElements = [ this ] ( MachineBasicBlock * MBB , Register NumElements ) { if ( RDA . hasLocalDefBefore ( & MBB -> back ( ) , NumElements ) ) return true ; if ( MBB -> pred_size ( ) > <NUM_LIT> ) return true ; return false ; } ; MachineBasicBlock * MBB = MLI . findLoopPreheader ( & ML , true ) ; if ( ! MBB ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } while ( MBB != InsertBB ) { if ( CannotProvideElements ( MBB , NumElements )


<s> case unaligned_store : return <NUM_LIT> ; case cond_branch_taken : return <NUM_LIT> ; case vec_construct : return TYPE_VECTOR_SUBPARTS ( vectype ) - <NUM_LIT> ; default : gcc_unreachable (


<s> const TargetRegisterInfo * TRI = MBB . getParent ( ) -> getSubtarget ( ) . getRegisterInfo ( ) ; MachineInstr & MI = * MBBI ; for ( unsigned Offset = <NUM_LIT> ; Offset < N ; ++ Offset ) { int ImmOffset = MI . getOperand ( <NUM_LIT> ) . getImm ( ) + Offset ; bool Kill = ( Offset + <NUM_LIT> == N ) ? MI . getOperand ( <NUM_LIT> ) . isKill ( ) : false ; assert ( ImmOffset >= - <NUM_LIT> && ImmOffset < <NUM_LIT> && <STR_LIT> ) ; BuildMI ( MBB , MBBI , MI . getDebugLoc ( ) , TII -> get ( Opc ) ) . addReg ( TRI -> getSubReg ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) , <STR_LIT> + Offset ) , Opc == <STR_LIT> ? RegState :: Define : <NUM_LIT> ) . addReg ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) , getKillRegState ( Kill ) ) . addImm ( ImmOffset ) ; } MI . eraseFromParent ( ) ; return true


<s> EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; case <STR_LIT> : EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT>


<s> if ( TARGET_OLDABI ) return ( VECTOR_FLOAT_TYPE_P ( type ) || TYPE_MODE ( type ) == BLKmode ) ; return ( ! IN_RANGE ( int_size_in_bytes ( type ) , <NUM_LIT> ,


<s> } } TFI . emitPrologue ( MF , MF . front ( ) ) ; for ( MachineFunction :: iterator I = MF . begin ( ) , E = MF . end ( ) ; I != E ; ++ I ) { if ( I -> isReturnBlock ( ) ) TFI . emitEpilogue ( MF , * I ) ; } return


<s> MachineFrameInfo & MFFrame = MF . getFrameInfo ( ) ; int Offset = getBackchainOffset ( MF ) - <STR_LIT> ; FI = MFFrame . CreateFixedObject ( <NUM_LIT> , Offset , false ) ; ZFI -> setFramePointerSaveIndex (


<s> if ( ! TARGET_64BIT && TARGET_ZARCH && GET_MODE_SIZE ( mode ) > <NUM_LIT> && ( ! flag_pic || regno != PIC_OFFSET_TABLE_REGNUM ) && ( ( regno >= <NUM_LIT> && regno <= <NUM_LIT> ) || regno == <NUM_LIT>


<s> MO . setImm ( OPCODE_IS_NOT_ZERO_INT ) ; break ; case OPCODE_IS_NOT_ZERO_INT : MO . setImm ( OPCODE_IS_ZERO_INT ) ; break ; case OPCODE_IS_ZERO : MO . setImm ( OPCODE_IS_NOT_ZERO ) ; break ; case OPCODE_IS_NOT_ZERO : MO . setImm ( OPCODE_IS_ZERO ) ; break ; default : return true ; } MachineOperand & MO2 = Cond [ <NUM_LIT> ] ; switch ( MO2 . getReg ( ) ) { case <STR_LIT> : MO2 . setReg ( <STR_LIT> ) ; break ; case <STR_LIT> : MO2 . setReg ( <STR_LIT> ) ; break ; default : return


<s> if ( Opcode == <NUM_LIT> ) Opcode = <STR_LIT> ; SDValue Condition = DAG . getConstant ( Predicate , DL , MVT_CC ) ; <STR_LIT> InvOutCC = <STR_LIT> ( OutCC ) ; unsigned NZCV = <STR_LIT> ( InvOutCC ) ; SDValue NZCVOp = DAG . getConstant ( NZCV , DL , <STR_LIT> ) ; return DAG . getNode ( Opcode , DL , MVT_CC , LHS , RHS , NZCVOp


<s> break ; case <STR_LIT> : for ( unsigned i = <NUM_LIT> ; i != NumElts ; ++ i ) { SDValue CurrentOp = SrcOp -> getOperand ( i ) ; if ( CurrentOp -> isUndef ( ) ) { Elts . push_back ( CurrentOp ) ; continue ; } auto * ND = cast < ConstantSDNode > ( CurrentOp ) ; const APInt & C = ND -> getAPIntValue ( ) ; Elts . push_back ( DAG . getConstant ( C . lshr ( ShiftAmt ) , dl , ElementType ) ) ; } break ; case <STR_LIT> : for ( unsigned i = <NUM_LIT> ; i != NumElts ; ++ i ) { SDValue CurrentOp = SrcOp -> getOperand ( i ) ; if ( CurrentOp -> isUndef ( ) ) { Elts . push_back ( CurrentOp ) ; continue ; } auto * ND = cast < ConstantSDNode > ( CurrentOp ) ; const APInt & C = ND -> getAPIntValue ( ) ; Elts . push_back ( DAG . getConstant ( C . ashr ( ShiftAmt ) , dl


<s> std :: pair < InstructionCost , MVT > LT = TLI -> getTypeLegalizationCost ( DL , Src ) ; assert ( ( Opcode == Instruction :: Load || Opcode == Instruction :: Store ) && <STR_LIT> ) ; InstructionCost Cost = BaseT :: getMemoryOpCost ( Opcode , Src , Alignment , AddressSpace , CostKind ) ; if ( CostKind != TTI :: TCK_RecipThroughput ) return Cost ; Cost *= CostFactor ; bool IsAltivecType = ST -> hasAltivec ( ) && ( LT . second == <STR_LIT> || LT . second == <STR_LIT> || LT . second == <STR_LIT> || LT . second == <STR_LIT> ) ; bool IsVSXType = ST -> hasVSX ( ) && ( LT . second == <STR_LIT> || LT . second == <STR_LIT> ) ; unsigned MemBytes = Src -> getPrimitiveSizeInBits ( ) ; if ( Opcode == Instruction :: Load && ST -> hasVSX ( ) && IsAltivecType && ( MemBytes == <NUM_LIT> || ( ST -> hasP8Vector ( ) && MemBytes == <NUM_LIT> ) ) ) return <NUM_LIT> ; unsigned SrcBytes = LT . second .


<s> return DecodeGPRSeqPairsClassRegisterClass ( Inst , <STR_LIT> , RegNo ,


<s> return _U_Qfcnvfxt_quad_to_sgl ( a )


<s> return create<ISA_LIT>ELFObjectWriter ( MCELFObjectTargetWriter :: getOSABI ( OSType


<s> case IES_RSHIFT : case IES_MULTIPLY : case IES_DIVIDE : case IES_MOD : case IES_LPAREN : case IES_INIT : case IES_LBRAC : State = IES_LPAREN ; IC . pushOperator ( IC_LPAREN ) ; break ; } PrevState =


<s> OS . EmitIntValue ( GPRInfoSet ? GPROffset : <NUM_LIT> , <NUM_LIT> ) ; OS . EmitIntValue ( FPRInfoSet ? FPRBitMask : <NUM_LIT> , <NUM_LIT> ) ; OS . EmitIntValue ( FPRInfoSet ? FPROffset : <NUM_LIT> , <NUM_LIT> ) ; OS . EmitIntValue ( FrameInfoSet ? FrameOffset : <NUM_LIT> , <NUM_LIT> ) ; OS . EmitIntValue ( FrameInfoSet ? FrameReg : <NUM_LIT> , <NUM_LIT> ) ; OS . EmitIntValue ( FrameInfoSet ? ReturnReg : <NUM_LIT> , <NUM_LIT> ) ; GPRInfoSet = FPRInfoSet = FrameInfoSet = false


<s> unsigned getError ( ) const { return


<s> sbitmap protected_bbs ; rtx_insn * insn , * end ; rtx unprotected_region ; if ( TARGET_MIPS16 ) { sorry ( <STR_LIT> , <STR_LIT> ) ; return ; } calculate_dominance_info ( CDI_DOMINATORS ) ; protected_bbs = sbitmap_alloc ( last_basic_block_for_fn ( cfun ) ) ; bitmap_clear ( protected_bbs ) ; rev_post_order = XNEWVEC ( int , last_basic_block_for_fn ( cfun ) ) ; n = pre_and_rev_post_order_compute ( NULL , rev_post_order , false ) ; for ( i = <NUM_LIT> ; i < n ; i ++ ) { bb = BASIC_BLOCK_FOR_FN ( cfun , rev_post_order [ i ] ) ; if ( r10k_protected_bb_p ( bb , protected_bbs ) ) unprotected_region = NULL_RTX ; else unprotected_region = pc_rtx ; end = NEXT_INSN ( BB_END ( bb ) ) ; for ( insn = BB_HEAD ( bb ) ; insn != end ; insn = NEXT_INSN ( insn ) ) { if ( unprotected_region && USEFUL_INSN_P ( insn ) ) { if ( recog_memoized ( insn ) == CODE_FOR_mips_cache ) unprotected_region = NULL_RTX ; else { if ( unprotected_region == pc_rtx ) unprotected_region = insn ; if ( r10k_needs_protection_p ( insn ) ) { emit_insn_before ( gen_r10k_cache_barrier ( ) , as_a < rtx_insn * > ( unprotected_region ) ) ; unprotected_region = NULL_RTX


<s> return ( __m256 ) __builtin_ia32_loadups256_mask ( ( __v8sf * ) __P ,


<s> MIB . add ( OldMI -> getOperand ( <NUM_LIT> ) ) ; MIB . add ( OldMI -> getOperand ( <NUM_LIT> ) ) ; MIB . add ( ImmOp ) ; MIB . add ( OldMI -> getOperand ( <NUM_LIT> ) ) ; OpStart = <NUM_LIT> ; Changed = true ; } else if ( HII -> getAddrMode ( * OldMI ) == <STR_LIT> ) { short NewOpCode = HII -> changeAddrMode_io_abs ( * OldMI ) ; assert ( NewOpCode >= <NUM_LIT> && <STR_LIT> ) ; MIB = BuildMI ( * BB , InsertPt , OldMI -> getDebugLoc ( ) , HII -> get ( NewOpCode ) ) ; const GlobalValue * GV = ImmOp . getGlobal ( ) ; int64_t Offset = ImmOp . getOffset ( ) + OldMI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; MIB . addGlobalAddress ( GV , Offset , ImmOp .


<s> EnumerateValue ( & GV ) ; EnumerateType ( GV . getValueType ( ) ) ; } for ( const Function & F : M ) { EnumerateValue ( & F ) ; EnumerateType ( F . getValueType ( ) ) ; EnumerateAttributes ( F . getAttributes ( ) ) ; } for ( const GlobalAlias & GA : M . aliases ( ) ) { EnumerateValue ( & GA ) ; EnumerateType ( GA . getValueType ( ) ) ; } for ( const GlobalIFunc & GIF : M . ifuncs ( ) ) { EnumerateValue ( & GIF ) ; EnumerateType ( GIF . getValueType ( ) ) ; } unsigned FirstConstant = Values . size ( ) ; for ( const GlobalVariable & GV : M . globals ( ) ) { if ( GV . hasInitializer ( ) ) EnumerateValue ( GV . getInitializer ( ) ) ; if ( GV . hasAttributes ( ) ) EnumerateAttributes ( GV . getAttributesAsList ( AttributeList :: FunctionIndex ) ) ; } for ( const GlobalAlias & GA : M . aliases ( ) ) EnumerateValue ( GA . getAliasee ( ) ) ; for ( const GlobalIFunc & GIF : M . ifuncs ( ) ) EnumerateValue ( GIF . getResolver ( ) ) ; for ( const Function & F : M ) for ( const Use & U : F . operands ( ) ) EnumerateValue ( U . get ( ) ) ; EnumerateType ( Type :: getMetadataTy ( M . getContext ( ) ) ) ; EnumerateValueSymbolTable ( M . getValueSymbolTable


<s> vdupq_lane_p16 ( poly16x4_t __a , const int __b ) { return ( poly16x8_t ) __builtin_neon_vdup_lanev8hi ( (


<s> if ( avr_log . rtx_costs ) { rtx set = single_set ( insn ) ; if ( set ) fprintf ( asm_out_file , <STR_LIT> , set_src_cost ( SET_SRC ( set ) , GET_MODE ( SET_DEST ( set ) ) , optimize_insn_for_speed_p ( ) ) ) ; else fprintf ( asm_out_file , <STR_LIT> , rtx_cost ( PATTERN ( insn ) , VOIDmode

, INSN , <NUM_LIT> , optimize_insn_for_speed_p ( ) ) ) ;


<s> void <ISA_LIT>IntelInstPrinter :: printInst ( const MCInst * MI ) { printInstruction ( MI )


<s> case MCK_1 : ImmVal = <NUM_LIT> ; break ; case MCK_2 : ImmVal = <NUM_LIT> ; break ; case MCK_3 : ImmVal = <NUM_LIT> ; break ; case MCK_4 : ImmVal = <NUM_LIT> ; break ; case MCK_5 : ImmVal = <NUM_LIT> ; break ; case MCK_6 : ImmVal = <NUM_LIT> ; break ; case MCK_7 : ImmVal = <NUM_LIT> ; break ; default : return Match_InvalidOperand ; } <ISA_LIT>Operand & Op = static_cast < <ISA_LIT>Operand & > ( AsmOp ) ; if ( Op . isU3Imm ( ) && Op . getImm ( ) == ImmVal


<s> } APInt MaskedHighBits = APInt :: getHighBitsSet ( X . getValueSizeInBits ( ) , MaskLZ ) ; APInt KnownZero , KnownOne ; DAG . ComputeMaskedBits ( X , MaskedHighBits , KnownZero , KnownOne ) ; if ( MaskedHighBits != KnownZero ) return true ; EVT VT = N . getValueType ( ) ; if ( ReplacingAnyExtend ) { assert ( X . getValueType ( ) != VT ) ; SDValue NewX = DAG . getNode ( <STR_LIT> , X . getDebugLoc ( ) , VT , X ) ; InsertDAGNode ( DAG , N , NewX ) ; X = NewX ; } DebugLoc DL = N . getDebugLoc ( ) ; SDValue NewSRLAmt = DAG . getConstant ( ShiftAmt + AMShiftAmt , <STR_LIT> ) ; SDValue NewSRL = DAG . getNode ( <STR_LIT> , DL , VT , X , NewSRLAmt ) ; SDValue NewSHLAmt = DAG . getConstant ( AMShiftAmt , <STR_LIT> ) ; SDValue NewSHL = DAG . getNode ( <STR_LIT> , DL , VT , NewSRL , NewSHLAmt ) ; InsertDAGNode ( DAG , N , NewSRLAmt ) ; InsertDAGNode ( DAG , N , NewSRL ) ; InsertDAGNode ( DAG , N , NewSHLAmt ) ; InsertDAGNode ( DAG , N , NewSHL ) ; DAG . ReplaceAllUsesWith ( N , NewSHL ) ; AM . Scale = <NUM_LIT> << AMShiftAmt ; AM . IndexReg = NewSRL


<s> return ( Val == FloatToBits ( <NUM_LIT> ) ) || ( Val == FloatToBits ( <NUM_LIT> ) ) || ( Val == FloatToBits ( - <NUM_LIT> ) ) || ( Val == FloatToBits ( <NUM_LIT> ) ) || ( Val == FloatToBits ( - <NUM_LIT> ) ) || ( Val == FloatToBits ( <NUM_LIT> ) ) || ( Val == FloatToBits ( - <NUM_LIT> ) ) || ( Val == FloatToBits ( <NUM_LIT> ) ) || ( Val ==

FloatToBits ( - <NUM_LIT> ) ) || ( Val == <NUM_LIT> && HasInv2Pi ) ;


<s> bool <ISA_LIT>FastISel :: SelectRet ( const Instruction * I ) { const ReturnInst * Ret = cast < ReturnInst > ( I ) ; const Function & F = * I -> getParent ( ) -> getParent ( ) ; if ( ! FuncInfo . CanLowerReturn ) return false ; CallingConv :: ID CC = F . getCallingConv ( ) ; if ( Ret -> getNumOperands ( ) > <NUM_LIT> ) { SmallVector < <STR_LIT> , <NUM_LIT> > Outs ; GetReturnInfo ( F . getReturnType ( ) , F . getAttributes ( ) , Outs , TLI ) ; SmallVector < CCValAssign , <NUM_LIT> > ValLocs ; CCState CCInfo ( CC , F . isVarArg ( ) , * FuncInfo . MF , TM , ValLocs , I -> getContext ( ) ) ; CCInfo . AnalyzeReturn ( Outs , CCAssignFnForCall ( CC , true , F . isVarArg ( ) ) ) ; const Value * RV = Ret -> getOperand ( <NUM_LIT> ) ; unsigned Reg = getRegForValue ( RV ) ; if ( Reg == <NUM_LIT> ) return false ; if ( ValLocs . size ( ) != <NUM_LIT> ) return false ; CCValAssign & VA = ValLocs [ <NUM_LIT> ] ; if ( VA . getLocInfo ( ) != CCValAssign :: Full ) return false ; if ( ! VA . isRegLoc ( ) ) return false ; unsigned SrcReg = Reg + VA . getValNo ( ) ; EVT RVEVT = TLI . getValueType ( RV -> getType ( ) ) ; if ( ! RVEVT . isSimple ( ) ) return false ; MVT RVVT = RVEVT . getSimpleVT ( ) ; MVT DestVT = VA . getValVT ( ) ; if ( RVVT


<s> bool isDSOffset0 ( ) const { assert ( isImm (


<s> case <STR_LIT> : TestOpc = <STR_LIT> ; break ; } if ( TestOpc ) { unsigned OpReg = getRegForValue ( TI -> getOperand ( <NUM_LIT> ) ) ; if ( OpReg == <NUM_LIT> ) return false ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TestOpc ) ) . addReg ( OpReg ) . addImm ( <NUM_LIT> ) ; unsigned JmpOpc = <STR_LIT> ; if ( FuncInfo . MBB -> isLayoutSuccessor ( TrueMBB ) ) { std :: swap ( TrueMBB , FalseMBB ) ; JmpOpc = <STR_LIT> ; } BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( JmpOpc ) ) . addMBB ( TrueMBB ) ; fastEmitBranch ( FalseMBB , DbgLoc ) ; uint32_t BranchWeight = <NUM_LIT> ; if ( FuncInfo . BPI ) BranchWeight = FuncInfo . BPI -> getEdgeWeight ( BI -> getParent ( ) , TrueMBB -> getBasicBlock ( ) ) ; FuncInfo . MBB -> addSuccessor ( TrueMBB , BranchWeight ) ; return true ; } } } else if ( fold<ISA_LIT>XALUIntrinsic ( CC , BI , BI -> getCondition ( ) ) ) { unsigned TmpReg = getRegForValue ( BI -> getCondition ( ) ) ; if ( TmpReg == <NUM_LIT> ) return false ; unsigned BranchOpc = <STR_LIT> ( CC ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( BranchOpc ) ) . addMBB ( TrueMBB ) ; fastEmitBranch ( FalseMBB , DbgLoc ) ; uint32_t BranchWeight = <NUM_LIT> ; if ( FuncInfo . BPI ) BranchWeight = FuncInfo . BPI -> getEdgeWeight ( BI -> getParent ( ) , TrueMBB -> getBasicBlock ( ) ) ; FuncInfo . MBB -> addSuccessor ( TrueMBB , BranchWeight ) ; return true ; } unsigned OpReg = getRegForValue ( BI -> getCondition ( ) ) ; if ( OpReg == <NUM_LIT> ) return false ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) ) . addReg ( OpReg ) . addImm ( <NUM_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) ) . addMBB ( TrueMBB ) ; fastEmitBranch ( FalseMBB , DbgLoc ) ; uint32_t BranchWeight = <NUM_LIT> ; if ( FuncInfo . BPI ) BranchWeight = FuncInfo . BPI -> getEdgeWeight ( BI -> getParent ( ) , TrueMBB -> getBasicBlock ( ) ) ; FuncInfo . MBB -> addSuccessor ( TrueMBB , BranchWeight


<s> else FullFS = <STR_LIT> ; } ParseSubtargetFeatures ( CPUName , FullFS ) ; if ( hasSSE42 ( ) || hasSSE4A ( ) ) IsUAMem16Slow = false ; InstrItins = getInstrItineraryForCPU ( CPUName ) ; if ( In64BitMode ) ToggleFeature ( <STR_LIT> ) ; else if ( In32BitMode ) ToggleFeature ( <STR_LIT> ) ; else if ( In16BitMode ) ToggleFeature ( <STR_LIT> ) ; else llvm_unreachable ( <STR_LIT> ) ; DEBUG ( dbgs ( ) << <STR_LIT> << <ISA_LIT>SSELevel << <STR_LIT> << <ISA_LIT>3DNowLevel << <STR_LIT> << Has<ISA_LIT>_64 << <STR_LIT> ) ; assert ( ( ! In64BitMode || Has<ISA_LIT>_64 ) && <STR_LIT> ) ; if ( StackAlignOverride ) stackAlignment = StackAlignOverride ; else if ( isTargetDarwin ( ) || isTargetLinux ( ) || isTargetSolaris ( ) || isTargetKFreeBSD ( ) || In64BitMode ) stackAlignment = <NUM_LIT> ; if ( <ISA_LIT>ProcFamily == IntelSkylake || hasAVX512 ( ) ) GatherOverhead = <NUM_LIT> ; if ( hasAVX512 ( ) ) ScatterOverhead


<s> unsigned getOriginalCPIdx ( unsigned CloneIdx ) const { DenseMap < unsigned , unsigned > :: const_iterator I = CPEClones . find ( CloneIdx ) ; if ( I != CPEClones . end ( ) ) return I -> second ; else return -


<s> inline unsigned getAM3IdxMode ( unsigned AM3Opc ) { return ( AM3Opc


<s> rtx perm [ <NUM_LIT> ] ; int addend = high_p ? <NUM_LIT> : nelts ; for ( int i = <NUM_LIT> ; i < nelts ; i ++ ) perm [ i ] = GEN_INT ( ( i + addend ) / <NUM_LIT> + ( i % <NUM_LIT> ) * nelts ) ; return gen_rtx_PARALLEL ( VOIDmode , gen_rtvec_v ( nelts


<s> assert ( ( curpos + Num ) <= size ) ; for ( int i = <NUM_LIT> ; i < Num ; ++ i ) { buffer [ curpos ] =


<s> static SDValue lowerV2I64Shuffle ( const SDLoc & DL , ArrayRef < int > Mask , const APInt & Zeroable , SDValue V1 , SDValue V2 , const <ISA_LIT>Subtarget & Subtarget , SelectionDAG & DAG ) { assert ( V1 . getSimpleValueType ( ) == <STR_LIT> && <STR_LIT> ) ; assert ( V2 . getSimpleValueType ( ) == <STR_LIT> && <STR_LIT> ) ; assert ( Mask . size ( ) == <NUM_LIT> && <STR_LIT> ) ; if ( V2 . isUndef ( ) ) { if ( SDValue Broadcast = lowerShuffleAsBroadcast ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return Broadcast ; V1 = DAG . getBitcast ( <STR_LIT> , V1 ) ; int WidenedMask [ <NUM_LIT> ] = { std :: max ( Mask [ <NUM_LIT> ] , <NUM_LIT> ) * <NUM_LIT> , std :: max ( Mask [ <NUM_LIT> ] , <NUM_LIT> ) * <NUM_LIT> + <NUM_LIT> , std :: max ( Mask [ <NUM_LIT> ] , <NUM_LIT> ) * <NUM_LIT> , std :: max ( Mask [ <NUM_LIT> ] , <NUM_LIT> ) * <NUM_LIT> + <NUM_LIT> } ; return DAG . getBitcast ( <STR_LIT> , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , getV4<ISA_LIT>ShuffleImm8ForMask


<s> if ( regno2 == INVALID_REGNUM ) return aarch64_pushwb_single_reg ( mode , regno1 , adjustment ) ; rtx reg1 = gen_rtx_REG ( mode , regno1 ) ; rtx reg2 = gen_rtx_REG ( mode , regno2 ) ; insn = emit_insn ( aarch64_gen_storewb_pair ( mode , stack_pointer_rtx , reg1 , reg2 , adjustment ) ) ; RTX_FRAME_RELATED_P ( XVECEXP ( PATTERN ( insn )

, <NUM_LIT> , <NUM_LIT> ) ) = <NUM_LIT> ;


<s> bool isVectorList ( ) const { return Kind == k_VectorList && VectorList . Layout == Layout && VectorList .


<s> default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : RC = & <STR_LIT> ; break ; case <STR_LIT> : RC = & <STR_LIT> ; break ; case <STR_LIT> : RC = & <STR_LIT> ; break ; } unsigned VReg = RegInfo . createVirtualRegister ( RC ) ; RegInfo . addLiveIn ( VA . getLocReg ( )


<s> gcc_assert ( REG_P ( reg ) ) ; emit_insn ( gen_add3_insn ( reg , reg , size_rtx ) ) ; addr = reg ; } else if ( GET_CODE ( addr ) == PRE_MODIFY ) { rtx reg = XEXP ( addr , <NUM_LIT> ) ; rtx expr = XEXP ( addr , <NUM_LIT> ) ; gcc_assert ( REG_P ( reg ) ) ; gcc_assert ( GET_CODE ( expr ) == PLUS ) ; emit_insn ( gen_add3_insn ( reg , XEXP ( expr , <NUM_LIT> ) , XEXP ( expr , <NUM_LIT> ) ) ) ; addr = reg ; } x = replace_equiv_address ( x , copy_addr_to_reg (


<s> bool isBank6 ( ) const { return isConstantImm ( ) && getConstantImm (


<s> unsigned SEH = MRI -> getEncodingValue ( Reg ) ; MRI -> mapLLVMRegToSEHReg ( Reg ,


<s> void \ read_only_private_data_section ( ) \ { \ if ( in_section != read_only_private_data ) \ { \ fprintf ( asm_out_file , <STR_LIT> , \ xcoff_private_data_section_name ) ; \ in_section =


<s> auto & MBB = * CI . First -> getParent ( ) ; auto ClauseMI = BuildMI ( MBB , * CI . First , DebugLoc ( ) , <ISA_LIT>I -> get ( <STR_LIT> ) ) . addImm (


<s> return DAG . getConstant ( Offset , SDLoc ( Op ) , Op . getValueType ( ) ) ; } } const Function & Fn = * DAG . getMachineFunction ( ) . getFunction ( ) ; DiagnosticInfoUnsupported BadInit ( Fn , <STR_LIT> , SDLoc ( Op ) . getDebugLoc ( ) ) ; DAG . getContext ( ) -> diagnose ( BadInit


<s> BranchInstrs . push_back ( LastInst ) ; if ( ! getAnalyzableBrOpc ( LastOpc ) ) return LastInst -> isIndirectBranch ( ) ? BT_Indirect : BT_None ; unsigned SecondLastOpc = <NUM_LIT> ; MachineInstr * SecondLastInst = nullptr ; if ( ++ I != REnd ) { SecondLastInst = & * I ; SecondLastOpc = getAnalyzableBrOpc ( SecondLastInst -> getOpcode ( ) ) ; if ( isUnpredicatedTerminator ( * SecondLastInst ) && ! SecondLastOpc ) return BT_None ; } if ( ! SecondLastOpc ) { if ( LastInst -> isUnconditionalBranch ( ) ) { TBB = LastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; return BT_Uncond ; } AnalyzeCondBr ( LastInst , LastOpc , TBB , Cond ) ; return BT_Cond


<s> if ( ArgTy -> isStructTy ( ) || ArgTy -> isArrayTy ( ) ) return false ; EVT ArgVT = TLI . getValueType ( DL , ArgTy ) ; if ( ! ArgVT . isSimple ( ) ) return false ; MVT VT = ArgVT . getSimpleVT ( ) . SimpleTy ; if ( VT . isFloatingPoint ( ) && ! Subtarget -> hasFPARMv8 ( ) ) return false ; if ( VT . isVector ( ) && ( ! Subtarget -> hasNEON ( ) || ! Subtarget -> isLittleEndian ( ) ) ) return false ; if ( VT >= <STR_LIT> && VT <= <STR_LIT> ) ++ GPRCnt ; else if ( ( VT >= <STR_LIT> && VT <= <STR_LIT> ) || VT . is64BitVector ( ) || VT . is128BitVector ( ) ) ++ FPRCnt ; else return false ; if ( GPRCnt > <NUM_LIT> || FPRCnt > <NUM_LIT> ) return false ; } static const MCPhysReg Registers [ <NUM_LIT> ] [ <NUM_LIT> ] = { { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } } ; unsigned GPRIdx = <NUM_LIT> ; unsigned FPRIdx = <NUM_LIT> ; for ( auto const & Arg : F -> args ( ) ) { MVT VT = TLI . getSimpleValueType ( DL , Arg . getType ( ) ) ; unsigned SrcReg ; const TargetRegisterClass * RC ; if ( VT >= <STR_LIT> && VT <= <STR_LIT> ) { SrcReg = Registers [ <NUM_LIT> ] [ GPRIdx ++


<s> SDValue ChainIn = Op -> getOperand ( <NUM_LIT> ) ; SDValue Address = Op -> getOperand ( <NUM_LIT> ) ; SDValue Offset = Op -> getOperand ( <NUM_LIT> ) ; EVT ResTy = Op -> getValueType ( <NUM_LIT> ) ; EVT PtrTy = Address -> getValueType ( <NUM_LIT> ) ; Address = DAG . getNode ( <STR_LIT> , DL , PtrTy , Address , Offset ) ; return DAG . getLoad ( ResTy , DL , ChainIn ,

Address , MachinePointerInfo ( ) , <NUM_LIT> ) ;


<s> static int neon_pair_endian_lane_map ( machine_mode mode , int lane ) { int nelem = GET_MODE_NUNITS ( mode ) ; if ( BYTES_BIG_ENDIAN ) lane = neon_endian_lane_map ( mode , lane & ( nelem -


<s> if ( Function * F = dyn_cast < Function > ( Callee ) ) R -> setCallingConv ( F ->


<s> Parser . Lex ( ) ; if ( Parser . getTok ( ) . isNot ( AsmToken :: EndOfStatement ) ) return Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; setFeatureBits ( <STR_LIT> , <STR_LIT> ) ; return false ; } if ( Option == <STR_LIT> ) { getTargetStreamer ( ) . emitDirectiveOptionNoRVC ( ) ; Parser . Lex ( ) ; if ( Parser . getTok ( ) . isNot ( AsmToken :: EndOfStatement ) ) return Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; clearFeatureBits ( <STR_LIT> , <STR_LIT> ) ; return false ; } if ( Option == <STR_LIT> ) { getTargetStreamer ( ) . emitDirectiveOptionPIC ( ) ; Parser . Lex ( ) ; if ( Parser . getTok ( ) . isNot ( AsmToken :: EndOfStatement ) ) return Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; ParserOptions . IsPicEnabled = true ; return false ; } if ( Option == <STR_LIT> ) { getTargetStreamer ( ) . emitDirectiveOptionNoPIC ( ) ; Parser . Lex ( ) ; if ( Parser . getTok ( ) . isNot ( AsmToken :: EndOfStatement ) ) return Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; ParserOptions . IsPicEnabled = false ; return false ; } if ( Option == <STR_LIT> ) { getTargetStreamer ( ) .


<s> void Initialize ( const MachineFunction & MF , bool


<s> unsigned WrapperKind = <STR_LIT> ; if ( model == TLSModel :: LocalExec ) { OperandFlags = is64Bit ? <STR_LIT> : <STR_LIT> ; } else if ( is64Bit ) { assert ( model == TLSModel :: InitialExec ) ; OperandFlags = <STR_LIT> ; WrapperKind = <STR_LIT> ; } else { assert ( model == TLSModel :: InitialExec ) ; OperandFlags = <STR_LIT> ; } SDValue TGA = DAG . getTargetGlobalAddress ( GA -> getGlobal ( ) , dl , GA -> getValueType ( <NUM_LIT> ) , GA -> getOffset ( ) , OperandFlags ) ; SDValue Offset = DAG . getNode ( WrapperKind , dl , PtrVT , TGA ) ; if ( model == TLSModel :: InitialExec ) Offset = DAG . getLoad ( PtrVT , dl , DAG . getEntryNode ( ) , Offset , MachinePointerInfo :: getGOT ( ) , false


<s> halfthree = rs6000_load_constant_and_splat ( mode , dconst3_2 ) ; emit_insn ( gen_rtx_SET ( VOIDmode , x0 , gen_rtx_UNSPEC ( mode , gen_rtvec ( <NUM_LIT> , src ) , UNSPEC_RSQRT ) ) ) ; rs6000_emit_msub ( y , src , halfthree , src ) ; for ( i = <NUM_LIT> ; i < passes ; i ++ ) { rtx x1 = gen_reg_rtx ( mode ) ; rtx u = gen_reg_rtx ( mode ) ; rtx v = gen_reg_rtx ( mode ) ; emit_insn ( gen_mul ( u , x0 , x0 ) ) ; rs6000_emit_nmsub ( v , y , u , halfthree ) ; emit_insn ( gen_mul ( x1 , x0


<s> if ( Type == <STR_LIT> ) return <STR_LIT> :: I32 ; if ( Type == <STR_LIT> ) return <STR_LIT> :: I64 ; if ( Type == <STR_LIT> ) return <STR_LIT> :: F32 ; if ( Type == <STR_LIT> ) return <STR_LIT> :: F64 ; if ( Type == <STR_LIT> || Type == <STR_LIT> || Type == <STR_LIT> || Type == <STR_LIT> || Type == <STR_LIT> || Type == <STR_LIT> || Type == <STR_LIT> ) return <STR_LIT> :: V128 ; if ( Type == <STR_LIT> ) return <STR_LIT> :: EXNREF ; if ( Type == <STR_LIT> ) return <STR_LIT> :: EXTERNREF ; return Optional < <STR_LIT> > (


<s> return ( MFI . getStackSize ( ) ) && needsFP (