<s> bool insertCSRRestoresInBlock ( MachineBasicBlock & MBB , const CSIVect & CSI , const <ISA_LIT>RegisterInfo & HRI ) const ; void updateEntryPaths ( MachineFunction & MF , MachineBasicBlock & SaveB ) const ; bool updateExitPaths ( MachineBasicBlock & MBB , MachineBasicBlock & RestoreB , BitVector & DoneT , BitVector & DoneF , BitVector & Path ) const ; void insertCFIInstructionsAt ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator At ) const ; void adjustForCalleeSavedRegsSpillCall ( MachineFunction & MF ) const ; bool expandCopy ( MachineBasicBlock & B , MachineBasicBlock :: iterator It , MachineRegisterInfo & MRI , const <ISA_LIT>InstrInfo & HII , SmallVectorImpl < unsigned > & NewRegs ) const ; bool expandStoreInt ( MachineBasicBlock & B , MachineBasicBlock :: iterator It , MachineRegisterInfo & MRI , const <ISA_LIT>InstrInfo & HII , SmallVectorImpl < unsigned > & NewRegs ) const ; bool expandLoadInt ( MachineBasicBlock & B , MachineBasicBlock :: iterator It , MachineRegisterInfo & MRI , const <ISA_LIT>InstrInfo & HII , SmallVectorImpl < unsigned > & NewRegs ) const ; bool expandStoreVecPred ( MachineBasicBlock & B , MachineBasicBlock :: iterator It , MachineRegisterInfo & MRI , const <ISA_LIT>InstrInfo & HII , SmallVectorImpl < unsigned > & NewRegs ) const ; bool expandLoadVecPred ( MachineBasicBlock & B , MachineBasicBlock :: iterator It , MachineRegisterInfo & MRI , const <ISA_LIT>InstrInfo & HII , SmallVectorImpl < unsigned > & NewRegs ) const ; bool expandStoreVec2 ( MachineBasicBlock & B , MachineBasicBlock :: iterator It , MachineRegisterInfo & MRI , const <ISA_LIT>InstrInfo & HII , SmallVectorImpl < unsigned > & NewRegs ) const ; bool expandLoadVec2 ( MachineBasicBlock & B , MachineBasicBlock :: iterator It , MachineRegisterInfo & MRI , const <ISA_LIT>InstrInfo & HII , SmallVectorImpl < unsigned > & NewRegs ) const ; bool expandStoreVec ( MachineBasicBlock & B , MachineBasicBlock :: iterator It , MachineRegisterInfo & MRI , const <ISA_LIT>InstrInfo & HII , SmallVectorImpl < unsigned > & NewRegs ) const ; bool expandLoadVec ( MachineBasicBlock & B , MachineBasicBlock :: iterator It , MachineRegisterInfo & MRI , const <ISA_LIT>InstrInfo & HII , SmallVectorImpl < unsigned > & NewRegs ) const ; bool expandSpillMacros ( MachineFunction & MF , SmallVectorImpl < unsigned > & NewRegs ) const ; unsigned findPhysReg ( MachineFunction & MF , <ISA_LIT>BlockRanges :: IndexRange & FIR , <ISA_LIT>BlockRanges :: InstrIndexMap & IndexMap , <ISA_LIT>BlockRanges :: RegToRangeMap & DeadMap , const TargetRegisterClass * RC ) const ; void optimizeSpillSlots ( MachineFunction & MF , SmallVectorImpl < unsigned > & VRegs ) const ; void findShrunkPrologEpilog ( MachineFunction & MF , MachineBasicBlock * & PrologB , MachineBasicBlock * & EpilogB ) const ; void addCalleeSaveRegistersAsImpOperand ( MachineInstr * MI , const CSIVect & CSI , bool IsDef , bool IsKill ) const ; bool shouldInlineCSR ( const MachineFunction & MF , const CSIVect & CSI ) const ; bool useSpillFunction ( const MachineFunction & MF , const CSIVect & CSI ) const ; bool useRestoreFunction ( const MachineFunction & MF , const CSIVect & CSI ) const ; bool mayOverflowFrameOffset ( MachineFunction & MF


<s> void <ISA_LIT>DbgInfo :: PopulateEnumTypeInfo ( DIType Ty , unsigned short & TypeNo ) { TypeNo = TypeNo


<s> if ( HeadCond . empty ( ) || ! parseCond ( HeadCond , HeadCmp ) ) { continue ; } <STR_LIT> TrueCmp ; if ( TrueCond . empty ( ) || ! parseCond ( TrueCond , TrueCmp ) ) { continue ; } const int HeadImm = ( int ) HeadCmpMI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; const int TrueImm = ( int ) TrueCmpMI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; DEBUG ( dbgs ( ) << <STR_LIT> << <STR_LIT> ( HeadCmp ) << '\n' ) ; DEBUG ( dbgs ( ) << <STR_LIT> << HeadImm << '\n' ) ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; DEBUG ( dbgs ( ) << <STR_LIT> << <STR_LIT> ( TrueCmp ) << '\n' ) ; DEBUG ( dbgs ( ) << <STR_LIT> << TrueImm << '\n' ) ; if ( ( ( HeadCmp == <STR_LIT> && TrueCmp == <STR_LIT> ) || ( HeadCmp == <STR_LIT> && TrueCmp == <STR_LIT> ) ) && std :: abs ( TrueImm - HeadImm ) == <NUM_LIT> ) { CmpInfo HeadCmpInfo = adjustCmp ( HeadCmpMI , HeadCmp ) ; CmpInfo TrueCmpInfo = adjustCmp ( TrueCmpMI , TrueCmp


<s> switch ( opcode ) { case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case


<s> return ( ( MFI -> getMaxAlignment ( ) > StackAlign ) || F -> getFnAttributes


<s> emit_insn ( gen_zero_extendqisi2 ( reg [ <NUM_LIT> ] , sub_reg ) ) ; while ( width > <NUM_LIT> ) { offset = offset + offset_adj ; shift ++ ; width -- ; mem [ <NUM_LIT> ] = gen_rtx_MEM ( QImode , plus_constant ( Pmode , operands [ <NUM_LIT> ] , offset ) ) ; emit_move_insn ( temp_sub_reg , mem [ <NUM_LIT> ] ) ; emit_insn ( gen_ashlsi3 ( temp_reg , temp_reg , GEN_INT ( shift * <NUM_LIT> ) ) ) ; emit_insn ( gen_iorsi3 ( reg [ <NUM_LIT> ] , reg [ <NUM_LIT> ] , temp_reg ) ) ; } if ( mode == DImode ) { reg [ <NUM_LIT> ] = reg [ <NUM_LIT> ] ; shift =


<s> TargetRegistry :: RegisterAsmTargetStreamer ( * T , create<ISA_LIT>AsmTargetStreamer ) ; TargetRegistry :: RegisterMCSubtargetInfo ( * T , create<ISA_LIT>MCSubtargetInfo ) ; TargetRegistry :: RegisterMCInstPrinter ( * T , create<ISA_LIT>MCInstPrinter ) ; TargetRegistry :: RegisterMCAsmBackend ( * T


<s> virtual const <ISA_LIT>RegisterInfo *


<s> void <ISA_LIT>TargetStreamer :: emitMovSP ( unsigned Reg , int64_t Offset ) { llvm_unreachable ( <STR_LIT> )


<s> <ISA_LIT>TargetStreamer & TS = getTargetStreamer ( ) ; if ( Subtarget -> isTargetNaCl ( ) ) EmitAlignment ( std :: max ( MF -> getAlignment ( ) , MIPS_NACL_BUNDLE_ALIGN ) ) ; TS . emitDirectiveSetNoMicro<ISA_LIT> (


<s> return true ; } else if ( ( IMMOffset = dyn_cast < ConstantSDNode > ( Addr ) ) && isInt < <NUM_LIT> > ( IMMOffset -> getZExtValue ( ) ) ) { Base = CurDAG -> getCopyFromReg ( CurDAG -> getEntryNode ( ) , SDLoc (

CurDAG -> getEntryNode ( ) ) , AMDGPU :: ZERO , <STR_LIT> ) ;


<s> static const uint16_t CU64BitRegs [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } ; const uint16_t * CURegs = ( Is64Bit ? CU64BitRegs : CU32BitRegs ) ; uint32_t RegEnc = <NUM_LIT> ; for ( int I = CU_NUM_SAVED_REGS - <NUM_LIT> , Idx = <NUM_LIT> ; I != - <NUM_LIT> ; -- I ) { unsigned Reg = SavedRegs [ I ] ; if ( Reg == <NUM_LIT> ) continue ; int CURegNum = getCompactUnwindRegNum ( CURegs


<s> bool <ISA_LIT>DAGToDAGISel :: selectVSplatSimm5 ( SDValue N , SDValue & SplatVal ) { return selectVSplatSimmHelper ( N , SplatVal , * CurDAG , * Subtarget , [ ] ( int64_t Imm ) { return isInt


<s> <ISA_LIT>RegisterInfo :: <ISA_LIT>RegisterInfo ( <ISA_LIT>TargetMachine & tm , const TargetInstrInfo & tii ) : <ISA_LIT>GenRegisterInfo ( <STR_LIT> ) , TM ( tm ) , TII ( tii ) { StackAlign = TM . getFrameLowering ( )


<s> return MatchOperand_ParseFail ; } Operands . push_back ( <ISA_LIT>Operand :: CreatePSBHint ( PSB -> Encoding , Tok . getString ( ) , S , getContext ( ) ) ) ; Lex ( ) ; return MatchOperand_Success


<s> std :: string Sym = addPrefix ( Sym1 ) ; size_t func_name_end = Sym . find (


<s> return Error ( RefineErrorLoc ( IDLoc , Operands , ErrorInfo ) , <STR_LIT> ) ; case Match_UImm5_0 : return Error ( RefineErrorLoc ( IDLoc , Operands , ErrorInfo ) , <STR_LIT> ) ; case Match_SImm5_0 : return Error ( RefineErrorLoc ( IDLoc , Operands , ErrorInfo ) , <STR_LIT> ) ; case Match_UImm5_1 : return Error ( RefineErrorLoc ( IDLoc , Operands , ErrorInfo ) , <STR_LIT> ) ; case Match_UImm5_32 : return Error ( RefineErrorLoc ( IDLoc , Operands , ErrorInfo ) , <STR_LIT> ) ; case Match_UImm5_33 : return Error ( RefineErrorLoc ( IDLoc , Operands , ErrorInfo ) , <STR_LIT> ) ; case Match_UImm5_0_Report_UImm6 : return Error ( RefineErrorLoc ( IDLoc , Operands , ErrorInfo ) , <STR_LIT> ) ; case Match_UImm5_Lsl2 : return Error ( RefineErrorLoc ( IDLoc , Operands , ErrorInfo ) , <STR_LIT> ) ; case Match_UImmRange2_64 : return Error ( RefineErrorLoc ( IDLoc , Operands , ErrorInfo ) , <STR_LIT> ) ; case Match_UImm6_0 : return Error ( RefineErrorLoc ( IDLoc , Operands , ErrorInfo ) , <STR_LIT> ) ; case Match_UImm6_Lsl2 : return Error ( RefineErrorLoc ( IDLoc , Operands , ErrorInfo ) , <STR_LIT> ) ; case Match_SImm6_0 : return Error ( RefineErrorLoc ( IDLoc , Operands , ErrorInfo ) , <STR_LIT> ) ; case Match_UImm7_0 : return Error ( RefineErrorLoc ( IDLoc , Operands , ErrorInfo ) , <STR_LIT> ) ; case Match_UImm7_N1 : return Error ( RefineErrorLoc ( IDLoc , Operands , ErrorInfo ) , <STR_LIT> ) ; case Match_SImm7_Lsl2 : return Error ( RefineErrorLoc ( IDLoc , Operands , ErrorInfo ) , <STR_LIT> ) ; case Match_UImm8_0 : return Error ( RefineErrorLoc ( IDLoc , Operands , ErrorInfo ) , <STR_LIT> ) ; case Match_UImm10_0 : return Error ( RefineErrorLoc ( IDLoc , Operands , ErrorInfo ) , <STR_LIT> ) ; case Match_SImm10_0 : return Error ( RefineErrorLoc ( IDLoc , Operands , ErrorInfo ) , <STR_LIT> ) ; case Match_SImm11_0 : return Error ( RefineErrorLoc ( IDLoc , Operands , ErrorInfo ) , <STR_LIT> ) ; case Match_UImm16 : case Match_UImm16_Relaxed : return Error ( RefineErrorLoc ( IDLoc , Operands , ErrorInfo ) , <STR_LIT> ) ; case Match_SImm16 : case Match_SImm16_Relaxed : return Error ( RefineErrorLoc ( IDLoc , Operands , ErrorInfo ) , <STR_LIT> ) ; case Match_UImm20_0 : return Error ( RefineErrorLoc ( IDLoc , Operands , ErrorInfo ) , <STR_LIT> ) ; case Match_UImm26_0 : return Error ( RefineErrorLoc ( IDLoc , Operands , ErrorInfo ) ,


<s> unsigned <ISA_LIT>FastISel :: emitUMULL_rr ( MVT RetVT , unsigned Op0 , unsigned Op1 ) { if ( RetVT != <STR_LIT>


<s> else OutStreamer . EmitValue ( MCSymbolRefExpr :: create ( MCSym . getPointer ( ) , OutStreamer . getContext (


<s> bool Swap = false ; unsigned LittleEndianShifts [ ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; unsigned BigEndianShifts [ ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; ArrayRef < int > Mask = N -> getMask ( ) ; int OriginalOrder [ ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; bool FoundCandidate = false ; unsigned VINSERTBSrcElem = IsLE ? <NUM_LIT> : <NUM_LIT> ; for ( unsigned i = <NUM_LIT> ; i < BytesInVector ;


<s> CI . setMI ( NewMI , * TII , * STM ) ; OptimizeListAgain |= ( CI . Width + Paired . Width ) < <NUM_LIT> ; break ; } case BUFFER_LOAD : { MachineBasicBlock :: iterator NewMI = mergeBufferLoadPair ( CI , Paired ) ; CI . setMI ( NewMI , * TII , * STM ) ; OptimizeListAgain |= ( CI . Width + Paired . Width ) < <NUM_LIT> ; break ; } case BUFFER_STORE : { MachineBasicBlock :: iterator NewMI = mergeBufferStorePair ( CI , Paired ) ; CI . setMI ( NewMI , * TII , * STM ) ; OptimizeListAgain |= ( CI . Width + Paired . Width ) < <NUM_LIT> ; break ; } case MIMG : { MachineBasicBlock :: iterator NewMI = mergeImagePair ( CI , Paired ) ; CI . setMI ( NewMI , * TII , * STM ) ; OptimizeListAgain |= ( CI . Width + Paired . Width ) < <NUM_LIT> ; break ; } case TBUFFER_LOAD : { MachineBasicBlock :: iterator NewMI = mergeTBufferLoadPair ( CI , Paired ) ; CI . setMI ( NewMI , * TII , * STM ) ; OptimizeListAgain |= ( CI . Width + Paired . Width ) < <NUM_LIT> ; break ; } case TBUFFER_STORE : { MachineBasicBlock :: iterator NewMI = mergeTBufferStorePair (


<s> Inst . addOperand ( MCOperand :: createImm ( Imm ) ) ; return MCDisassembler ::


<s> SDValue DIVREM = DAG . getNode ( <STR_LIT> , DL , DAG . getVTList ( HalfVT , HalfVT ) , LHS_Lo , RHS_Lo ) ; SDValue Res [ <NUM_LIT> ] = { DAG . getNode ( <STR_LIT> , DL , VT , DIVREM . getValue ( <NUM_LIT> ) ) , DAG . getNode ( <STR_LIT> , DL , VT , DIVREM . getValue ( <NUM_LIT> ) ) } ; return DAG . getMergeValues ( Res , DL ) ; } SDValue LHSign = DAG . getSelectCC ( DL , LHS , Zero , NegOne , Zero , <STR_LIT> ) ; SDValue RHSign = DAG . getSelectCC ( DL , RHS , Zero , NegOne , Zero , <STR_LIT> ) ; SDValue DSign = DAG . getNode ( <STR_LIT> , DL , VT , LHSign , RHSign ) ; SDValue RSign = LHSign ; LHS = DAG . getNode ( <STR_LIT> , DL , VT , LHS , LHSign ) ; RHS = DAG . getNode ( <STR_LIT> , DL , VT , RHS , RHSign ) ; LHS = DAG . getNode ( <STR_LIT> , DL , VT , LHS , LHSign ) ; RHS = DAG . getNode ( <STR_LIT> , DL , VT , RHS , RHSign ) ; SDValue Div = DAG . getNode ( <STR_LIT> , DL , DAG . getVTList ( VT , VT ) , LHS , RHS ) ; SDValue Rem = Div . getValue ( <NUM_LIT> ) ; Div = DAG . getNode ( <STR_LIT> , DL , VT , Div , DSign ) ; Rem = DAG . getNode ( <STR_LIT> , DL , VT , Rem , RSign ) ; Div = DAG . getNode ( <STR_LIT> , DL , VT , Div , DSign ) ; Rem = DAG . getNode ( <STR_LIT> , DL , VT , Rem , RSign ) ; SDValue Res [ <NUM_LIT>


<s> static bool rs6000_member_type_forces_blk ( const_tree field , machine_mode mode ) { return ( ( TARGET_SPE && TREE_CODE ( TREE_TYPE ( field ) ) == VECTOR_TYPE ) ||

( TARGET_E500_DOUBLE && mode == DFmode ) ) ;


<s> LO16 = LO16 . addImm ( Lo16 ) ; HI16 = HI16 . addImm ( Hi16 ) ; } else if ( MO . isGlobal ( ) ) { const GlobalValue * GV = MO . getGlobal ( ) ; unsigned TF = MO . getTargetFlags ( ) ; LO16 = LO16 . addGlobalAddress ( GV , MO . getOffset ( ) , TF | <STR_LIT> ) ; HI16 = HI16 . addGlobalAddress ( GV , MO . getOffset ( ) , TF | <STR_LIT> ) ; } else if ( MO . isCPI ( ) ) { int i = MO . getIndex ( ) ; unsigned TF = MO . getTargetFlags ( ) ; LO16 = LO16 . addConstantPoolIndex ( i , MO . getOffset ( ) , TF | <STR_LIT> ) ; HI16 = HI16 . addConstantPoolIndex ( i , MO . getOffset ( ) , TF | <STR_LIT> ) ; } else if ( MO . isJTI ( ) ) { unsigned TF = MO . getTargetFlags ( ) ; LO16 = LO16 . addJumpTableIndex ( MO . getIndex ( ) , TF | <STR_LIT> ) ; HI16 = HI16 . addJumpTableIndex ( MO . getIndex ( ) , TF | <STR_LIT> ) ; } else { assert ( <NUM_LIT> && <STR_LIT> ) ; } if ( ShouldUseMOV16PIC ) { AddPICADD_MOVi16_PICID ( MI , MBB , MBBI , ! isThumb2 , PredReg , Pred , DstReg , DstIsDead , LO16 , HI16 ) ; } LO16 -> setMemRefs ( MI . memoperands_begin ( ) , MI . memoperands_end ( ) ) ; HI16 -> setMemRefs ( MI . memoperands_begin ( ) , MI . memoperands_end ( ) ) ; LO16 . addImm ( Pred ) . addReg ( PredReg ) ; HI16 . addImm ( Pred )


<s> if ( MI . isCall ( ) ) { if ( doesNotReturn ( MI ) ) return true ; for ( auto I : MBB -> successors ( ) ) if ( I -> isEHPad


create<ISA_LIT>OpLoweringLegacyPass ( ) {


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ( MI -> getNumOperands ( ) - MI -> getDesc ( ) . getNumOperands ( ) + <NUM_LIT> ) * <NUM_LIT> ; case <STR_LIT> : case


<s> SDValue <ISA_LIT>TargetLowering :: lowerFixedLengthVectorLoadToRVV ( SDValue Op , SelectionDAG & DAG ) const { SDLoc DL ( Op ) ; auto * Load = cast < LoadSDNode > ( Op ) ; assert ( allowsMemoryAccessForAlignment ( * DAG . getContext ( ) , DAG . getDataLayout ( ) , Load -> getMemoryVT ( ) , * Load -> getMemOperand ( ) ) && <STR_LIT> ) ; MVT VT = Op . getSimpleValueType ( ) ; MVT ContainerVT = getContainerForFixedLengthVector ( VT ) ; SDValue VL = DAG . getConstant ( VT . getVectorNumElements ( ) , DL , Subtarget . getXLenVT ( ) ) ; SDVTList VTs = DAG . getVTList ( { ContainerVT , <STR_LIT> } ) ; SDValue NewLoad = DAG . getMemIntrinsicNode ( <STR_LIT> , DL , VTs , { Load -> getChain ( ) , Load -> getBasePtr ( ) , VL } , Load -> getMemoryVT ( ) , Load -> getMemOperand ( ) ) ; SDValue Result = convertFromScalableVector ( VT , NewLoad , DAG , Subtarget ) ; return DAG . getMergeValues ( { Result , Load -> getChain ( ) } ,


<s> void <ISA_LIT>AsmPrinter :: printT2AddrModeImm8s4Operand ( const MachineInstr * MI , int OpNum ) { const MachineOperand & MO1 = MI -> getOperand ( OpNum ) ; const MachineOperand & MO2 = MI -> getOperand ( OpNum + <NUM_LIT> ) ; O << <STR_LIT> << getRegisterName ( MO1 . getReg ( ) ) ; int32_t OffImm = ( int32_t ) MO2 . getImm ( ) / <NUM_LIT> ; if ( OffImm < <NUM_LIT> ) O << <STR_LIT> << - OffImm * <NUM_LIT> ; else if ( OffImm > <NUM_LIT> ) O << <STR_LIT> << OffImm * <NUM_LIT> ; O << <STR_LIT>


<s> } SDValue One = DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; SDValue Zero = DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; SDValue ThirtyTwoV = DAG . getConstant ( <NUM_LIT> , DL , VecVT ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , SplatVal , Zero ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , SplatVal , One ) ; Lo = DAG . getNode ( <STR_LIT> , DL , VecVT , Lo ) ; Lo = DAG . getNode ( <STR_LIT> , DL , VecVT , Lo , ThirtyTwoV ) ; Lo = DAG . getNode ( <STR_LIT> , DL , VecVT


<s> bool Abs = Imm . Modifiers & <NUM_LIT> ; if ( Imm . IsFPImm ) { APFloat F ( BitsToFloat ( Val ) ) ; if ( Abs ) { F . clearSign ( ) ; } if ( Negate ) { F . changeSign ( ) ; } Val = F . bitcastToAPInt ( ) . getZExtValue ( ) ; } else


<s> return TargetIRAnalysis ( [ this ] ( Function & F ) { return TargetTransformInfo ( <ISA_LIT>TTIImpl ( this ,


<s> const MCBinaryExpr * BE = cast < MCBinaryExpr > ( Expr ) ; fixELFSymbolsInTLSFixupsImpl ( BE -> getLHS ( ) , Asm ) ; fixELFSymbolsInTLSFixupsImpl ( BE -> getRHS ( ) , Asm ) ; break ; } case MCExpr :: SymbolRef : { const MCSymbolRefExpr & SymRef = * cast <


, __m128h __C , const int __D , const int __E ) {


<s> bool <ISA_LIT>PassConfig :: addIRTranslator


<s> return T . getArch ( ) == Triple :: ppc64le || T . getArch


<s> assert ( Pred != <STR_LIT> && <STR_LIT> ) ; if ( Pred == <STR_LIT> ) { ++ MBIter ; continue ; } <STR_LIT> BlockMask = CreateVPTBlock ( MBIter , EndIter , DeadInstructions ) ; MachineInstrBuilder MIBuilder ; unsigned NewOpcode ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << ( unsigned ) BlockMask << <STR_LIT> ) ; if ( MachineInstr * VCMP = findVCMPToFoldIntoVPST ( MI , TRI , NewOpcode ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; VCMP -> dump ( ) ) ; MIBuilder = BuildMI ( Block , MI , DL , TII -> get ( NewOpcode ) ) ; MIBuilder . addImm ( ( uint64_t ) BlockMask ) ; MIBuilder . add ( VCMP -> getOperand ( <NUM_LIT> ) ) ; MIBuilder . add ( VCMP -> getOperand ( <NUM_LIT> ) ) ; MIBuilder . add ( VCMP -> getOperand ( <NUM_LIT> ) ) ; for ( MachineInstr & MI : make_range ( VCMP -> getIterator ( ) , MI -> getIterator ( ) ) ) { MI . clearRegisterKills ( VCMP -> getOperand ( <NUM_LIT> ) . getReg ( ) , TRI ) ; MI . clearRegisterKills ( VCMP -> getOperand ( <NUM_LIT> ) . getReg ( ) , TRI ) ; } VCMP -> eraseFromParent ( ) ; } else { MIBuilder = BuildMI ( Block , MI , DL , TII -> get ( <STR_LIT> ) ) ; MIBuilder . addImm ( ( uint64_t ) BlockMask ) ; } finalizeBundle ( Block , MachineBasicBlock :: instr_iterator ( MIBuilder . getInstr ( ) ) , MBIter ) ; Modified = true ; } for ( MachineInstr * DeadMI : DeadInstructions ) { if ( DeadMI -> isInsideBundle ( ) ) DeadMI -> eraseFromBundle ( ) ; else DeadMI -> eraseFromParent ( ) ; } return


<s> if ( isHVXVectorType ( Ty , true ) ) return Align


<s> break ; case <STR_LIT> : JTOpcode = <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : JTOpcode = <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : JTOpcode = <STR_LIT> ; break ; } unsigned NumOps = MI -> getDesc ( ) . getNumOperands ( ) ; MachineOperand JTOp = MI -> getOperand ( NumOps - ( MI -> isPredicable ( ) ? <NUM_LIT> : <NUM_LIT> ) ) ; unsigned JTI = JTOp . getIndex ( ) ; unsigned Size = JT [ JTI ] . MBBs . size ( ) * sizeof ( uint32_t ) ; MachineBasicBlock * JumpTableBB = MF -> CreateMachineBasicBlock ( ) ; MF -> insert ( std :: next ( MachineFunction :: iterator ( MBB ) ) , JumpTableBB ) ; MachineInstr * CPEMI = BuildMI ( * JumpTableBB , JumpTableBB -> begin ( ) , DebugLoc ( ) , TII -> get ( JTOpcode ) ) . addImm ( i ++ ) . addJumpTableIndex ( JTI ) . addImm ( Size ) ; CPEMIs . push_back ( CPEMI ) ; CPEntries . emplace_back ( <NUM_LIT> , CPEntry ( CPEMI , JTI ) ) ; JumpTableEntryIndices . insert ( std :: make_pair ( JTI , CPEntries . size ( ) - <NUM_LIT> ) ) ; if ( ! LastCorrectlyNumberedBB ) LastCorrectlyNumberedBB = & MBB ; } if ( LastCorrectlyNumberedBB ) MF -> RenumberBlocks (


<s> EVT CmpVT = LHS . getValueType ( ) . changeVectorElementTypeToInteger ( ) ; SDLoc dl ( Op ) ; if ( LHS . getValueType ( ) . getVectorElementType ( ) . isInteger ( ) ) { assert ( LHS . getValueType ( ) == RHS . getValueType ( ) ) ; <STR_LIT> <ISA_LIT>CC = changeIntCCTo<ISA_LIT>CC ( CC ) ; SDValue Cmp = EmitVectorComparison ( LHS , RHS , <ISA_LIT>CC , false , CmpVT , dl , DAG ) ; return DAG . getSExtOrTrunc ( Cmp , dl , Op . getValueType ( ) ) ; } const bool FullFP16 = DAG . getSubtarget < <ISA_LIT>Subtarget > ( ) . hasFullFP16 ( ) ; if ( ! FullFP16 && LHS . getValueType ( ) . getVectorElementType ( ) == <STR_LIT> ) { if ( LHS . getValueType ( ) . getVectorNumElements ( ) == <NUM_LIT> ) { LHS = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , LHS ) ; RHS = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , RHS ) ; SDValue NewSetcc = DAG . getSetCC ( dl , <STR_LIT> , LHS , RHS , CC ) ; DAG . ReplaceAllUsesWith ( Op , NewSetcc ) ; CmpVT = <STR_LIT> ; } else return SDValue ( ) ; } assert ( ( ! FullFP16 && LHS . getValueType ( ) . getVectorElementType ( ) != <STR_LIT> ) || LHS . getValueType ( ) . getVectorElementType ( ) != <STR_LIT> ) ; <STR_LIT> CC1 , CC2 ; bool ShouldInvert ; changeVectorFPCCTo<ISA_LIT>CC ( CC , CC1 , CC2 , ShouldInvert ) ; bool NoNaNs = getTargetMachine ( ) . Options . NoNaNsFPMath ; SDValue Cmp = EmitVectorComparison ( LHS , RHS , CC1 ,


<s> if ( ! Stubs . empty ( ) ) { OutStreamer -> SwitchSection ( TLOFMacho . getThreadLocalPointerSection ( ) ) ; EmitAlignment ( <NUM_LIT> ) ; for ( auto & Stub : Stubs ) emitNonLazySymbolPointer ( * OutStreamer , Stub . first , Stub . second ) ; Stubs . clear ( ) ; OutStreamer -> AddBlankLine ( ) ; } OutStreamer -> EmitAssemblerFlag ( MCAF_SubsectionsViaSymbols ) ; } if ( TT . isOSBinFormatCOFF ( ) ) { const auto & TLOF = static_cast < const TargetLoweringObjectFileCOFF & > ( getObjFileLowering ( ) ) ; std :: string Flags ; raw_string_ostream OS ( Flags ) ; for ( const auto & Function : M ) TLOF . emitLinkerFlagsForGlobal ( OS , & Function , * Mang ) ; for ( const auto & Global : M . globals ( ) ) TLOF . emitLinkerFlagsForGlobal ( OS , & Global , * Mang ) ; for ( const auto & Alias : M . aliases ( ) ) TLOF . emitLinkerFlagsForGlobal ( OS , & Alias , * Mang ) ; OS . flush (


<s> Args . push_back ( Entry ) ; } SDValue Callee = DAG . getExternalSymbol ( getLibcallName ( LC ) , getPointerTy ( DAG . getDataLayout ( ) ) ) ; Type * RetTy = ( Type * ) StructType :: get ( Ty , Ty , nullptr ) ; SDLoc dl ( Op ) ; TargetLowering :: CallLoweringInfo CLI ( DAG ) ; CLI . setDebugLoc ( dl ) . setChain ( InChain ) . setLibCallee ( getLibcallCallingConv ( LC ) , RetTy , Callee , std :: move ( Args ) ) . setInRegister ( ) . setSExtResult ( isSigned ) . setZExtResult ( ! isSigned ) ; std :: pair < SDValue , SDValue > CallInfo = LowerCallTo ( CLI ) ; return CallInfo . first


<s> void * getAdjustedAnalysisPointer ( const void * ID ) override { if ( ID == & TargetTransformInfo :: ID ) return ( TargetTransformInfo * ) this ; return


<s> Inst . addOperand ( MCOperand :: CreateReg ( getFCCReg


<s> PointerSize = <NUM_LIT> ; CalleeSaveStackSlotSize = <NUM_LIT> ; IsLittleEndian = false ; CommentString = <STR_LIT> ; ZeroDirective =


<s> LIS = & getAnalysis < LiveIntervals > ( ) ; char GlobalFlags = analyzeFunction ( MF ) ; unsigned LiveMaskReg = <NUM_LIT> ; unsigned Exec = ST -> isWave32 ( ) ? <STR_LIT> : <STR_LIT> ; if ( ! ( GlobalFlags & StateWQM ) ) { lowerLiveMaskQueries ( Exec ) ; if ( ! ( GlobalFlags & StateWWM ) && LowerToCopyInstrs . empty ( ) && LowerToMovInstrs . empty ( ) ) return ! LiveMaskQueries . empty ( ) ; } else { MachineBasicBlock & Entry = MF . front ( ) ; MachineBasicBlock :: iterator EntryMI = Entry . getFirstNonPHI ( ) ; if ( GlobalFlags & StateExact || ! LiveMaskQueries . empty ( ) ) { LiveMaskReg = MRI -> createVirtualRegister ( TRI -> getBoolRC ( ) ) ; MachineInstr * MI = BuildMI ( Entry , EntryMI , DebugLoc ( ) , TII -> get ( <STR_LIT> ) , LiveMaskReg ) . addReg ( Exec ) ; LIS -> InsertMachineInstrInMaps ( * MI ) ; } lowerLiveMaskQueries ( LiveMaskReg ) ; if ( GlobalFlags == StateWQM ) { BuildMI ( Entry , EntryMI , DebugLoc ( ) , TII -> get ( ST -> isWave32 ( ) ? <STR_LIT> : <STR_LIT> ) , Exec ) . addReg ( Exec ) ; lowerCopyInstrs ( ) ; return true ; } } LLVM_DEBUG ( printInfo ( ) ) ; lowerCopyInstrs ( ) ; for ( auto BII : Blocks ) processBlock ( * BII . first , LiveMaskReg , BII . first == & * MF . begin ( ) ) ; LIS -> removeRegUnit ( * MCRegUnitIterator ( <STR_LIT> , TRI


<s> HOST_WIDE_INT ret ; ret = alpha_sa_size ( ) ; ret += ALPHA_ROUND ( crtl -> outgoing_args_size ) ; switch ( from ) { case FRAME_POINTER_REGNUM : break ; case ARG_POINTER_REGNUM : ret += ( ALPHA_ROUND ( get_frame_size ( ) + crtl -> args . pretend_args_size ) - crtl -> args . pretend_args_size ) ; break ; default : gcc_unreachable ( ) ; } return


<s> DebugLoc DL ; if ( I != MBB . end ( ) && ! I -> isDebugInstr ( ) ) DL = I -> getDebugLoc ( ) ; MachineFunction * MF = MBB . getParent ( ) ; const MachineFrameInfo & MFI = MF -> getFrameInfo


<s> return new ( Ctx ) <ISA_LIT>MCExpr ( Kind ,


<s> return SECONDARY_MEMORY_NEEDED ( from , to , mode


<s> __builtin_aarch64_simd_xi __o ; __o = __builtin_aarch64_ld4rv8qi ( ( const __builtin_aarch64_simd_qi * ) __a ) ; ret . val [ <NUM_LIT> ] = ( int8x8_t ) __builtin_aarch64_get_dregxiv8qi ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( int8x8_t ) __builtin_aarch64_get_dregxiv8qi ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( int8x8_t )


<s> AU . addRequiredID ( LCSSAID ) ; AU . addRequired < AAResultsWrapperPass > ( ) ; AU . addRequired < ScalarEvolutionWrapperPass > (


<s> void <ISA_LIT>Relocator :: addCopyReloc ( ResolveInfo & pSym ) { Relocation & rel_entry = * getTarget ( ) . getRelaDyn ( ) . create ( ) ; rel_entry . setType ( llvm


<s> MachineFunction & MF = DAG . getMachineFunction ( ) ; <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; const TargetRegisterClass * RC ; if ( AFI -> isThumb1OnlyFunction ( ) ) RC = & <STR_LIT> ; else RC = & <STR_LIT> ; unsigned Reg = MF . addLiveIn ( VA . getLocReg ( ) , RC ) ; SDValue ArgValue = DAG . getCopyFromReg ( Root , dl , Reg , <STR_LIT> ) ; SDValue ArgValue2 ; if ( NextVA . isMemLoc ( ) ) { MachineFrameInfo * MFI = MF . getFrameInfo (


<s> value_rtx = convert_to_mode ( Pmode , value_rtx , <NUM_LIT> ) ; emit_library_call ( sym , LCT_NORMAL , VOIDmode , <NUM_LIT> , dst_reg , Pmode , value_rtx , Pmode , convert_to_mode ( TYPE_MODE ( sizetype ) , GEN_INT ( bytes >> <NUM_LIT> ) , TYPE_UNSIGNED ( sizetype ) ) , TYPE_MODE ( sizetype ) ) ; if ( rem == <NUM_LIT>


<s> static inline bool isValidDecodeLogicalImmediate ( uint64_t val , unsigned regSize ) { unsigned N = ( val >> <NUM_LIT> ) & <NUM_LIT> ; unsigned imms = val & <NUM_LIT> ; if ( regSize == <NUM_LIT> && N


<s> if ( AI -> isFloatingPointOperation ( ) ) return AtomicExpansionKind :: CmpXChg ; unsigned Size = AI -> getType ( ) -> getPrimitiveSizeInBits


<s> if ( Src . getValueType ( ) == <STR_LIT> && Op . getValueType ( ) ==

<STR_LIT> ) return LowerINT_TO_FP64 ( Op , DAG , true ) ;


<s> BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) , Ws1 ) . addImm ( <NUM_LIT> ) ; BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) , Ws2 ) . addReg ( Ws1 ) ; BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) , MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg (

Ws2 ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ;


<s> HOST_WIDE_INT l ; if ( CONST_INT_P ( x ) ) xx = INTVAL ( x ) ; else output_operand_lossage ( <STR_LIT> ) ; if ( bits_set [ xx & <NUM_LIT> ] <= <NUM_LIT> ) { if ( ( ~ xx & ~ ( HOST_WIDE_INT ) <NUM_LIT> ) == <NUM_LIT> ) xx &= <NUM_LIT> ; else if ( ( ~ xx & ~ ( HOST_WIDE_INT ) <NUM_LIT> ) == <NUM_LIT> ) xx &= <NUM_LIT> ; l = exact_log2 ( xx ) ; } else { if ( ( xx & ~ ( HOST_WIDE_INT ) <NUM_LIT> ) == <NUM_LIT> ) xx |= ~ ( HOST_WIDE_INT ) <NUM_LIT> ; else if ( ( xx & ~ ( HOST_WIDE_INT ) <NUM_LIT> ) == <NUM_LIT> ) xx |= ~ ( HOST_WIDE_INT ) <NUM_LIT> ; l = exact_log2 ( ~ xx ) ; } if ( l == - <NUM_LIT> ) output_operand_lossage ( <STR_LIT> ) ; fprintf ( file , IMMEDIATE_PREFIX HOST_WIDE_INT_PRINT_DEC , l ) ; return ; } case 'C' : if ( GET_CODE ( x ) == SYMBOL_REF ) assemble_name ( file , XSTR ( x , <NUM_LIT> ) ) ; else if ( LABEL_P ( x ) ) output_asm_label ( x ) ; else xstormy16_print_operand_address ( file , x ) ; return ; case 'o' : case 'O' : { HOST_WIDE_INT xx = <NUM_LIT> ; if ( CONST_INT_P ( x ) ) xx = INTVAL ( x ) ; else output_operand_lossage ( <STR_LIT> ) ; if ( code == 'O' ) xx = - xx ; fprintf ( file , IMMEDIATE_PREFIX HOST_WIDE_INT_PRINT_DEC , xx


<s> for ( auto & MBB : MF ) Blocks . push_back ( & MBB ) ; if ( collectCmovCandidates ( Blocks , AllCmovGroups , true ) ) { for ( auto & Group : AllCmovGroups ) { if ( ! llvm :: any_of ( Group , [ & ] ( MachineInstr * I ) { return I -> mayLoad ( ) ; } ) ) continue ; Changed = true ; convertCmovInstsToBranches ( Group ) ; } } } SmallVector < MachineLoop * , <NUM_LIT> > Loops ( MLI . begin ( ) , MLI . end ( ) ) ; for ( int i = <NUM_LIT> ; i < ( int ) Loops . size ( ) ; ++ i ) for ( MachineLoop * Child : Loops [ i ] -> getSubLoops ( ) ) Loops . push_back ( Child ) ; for ( MachineLoop * CurrLoop : Loops ) { if ( ! CurrLoop -> getSubLoops ( ) . empty ( ) ) continue ; CmovGroups CmovInstGroups ; if ( ! collectCmovCandidates ( CurrLoop -> getBlocks ( ) , CmovInstGroups ) ) continue ; if ( ! checkForProfitableCmovCandidates ( CurrLoop -> getBlocks ( ) , CmovInstGroups ) ) continue ; Changed = true ; for ( auto & Group : CmovInstGroups ) convertCmovInstsToBranches ( Group ) ; } return Changed


<s> } ) ; if ( UA . Addr -> getFlags ( ) & NodeAttrs :: PhiRef ) { NodeAddr < PhiNode * > PA = UA . Addr -> getOwner ( * DFG ) ; NodeId id = PA . Id ; const Liveness :: RefMap & phiUse = LV -> getRealUses ( id ) ; DEBUG ( dbgs ( ) << <STR_LIT> << Print < Liveness :: RefMap > ( phiUse , * DFG ) << <STR_LIT> ) ; if ( phiUse . size ( ) > <NUM_LIT> ) { for ( auto I : phiUse ) { if ( DR != I . first ) continue ; auto phiUseSet = I . second ; for ( auto phiUI : phiUseSet ) { NodeAddr < UseNode * > phiUA = DFG -> addr < UseNode * > ( phiUI ) ; UNodeList . push_back ( phiUA ) ; } } } } else UNodeList . push_back


<s> static std :: unique_ptr < AMDGPUOperand > CreateReg ( unsigned RegNo , SMLoc S , SMLoc E , const MCRegisterInfo * TRI , bool ForceVOP3 ) { auto Op = llvm :: make_unique <


<s> static SDValue narrowLoadToVZLoad ( LoadSDNode * LN , MVT MemVT , MVT VT , SelectionDAG & DAG ) { if ( ! LN -> isSimple ( ) ) return SDValue ( ) ; SDVTList Tys = DAG . getVTList ( VT , <STR_LIT> ) ; SDValue Ops [ ] = { LN -> getChain ( ) , LN -> getBasePtr ( ) } ; return DAG . getMemIntrinsicNode ( <STR_LIT> , SDLoc ( LN ) , Tys , Ops , MemVT , LN -> getPointerInfo ( ) , LN -> getOriginalAlign ( ) , LN

-> getMemOperand ( ) -> getFlags ( ) ) ;


<s> RegisterTarget < Triple :: arcompact > X (


<s> SDValue OffsetPtr = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , BasePtr , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; SDValue NewLD2 = DAG . getLoad ( <STR_LIT> , DL , NewLD1 . getValue ( <NUM_LIT> ) , OffsetPtr , LD -> getPointerInfo ( ) , std :: min ( <NUM_LIT> , LD -> getAlignment ( ) / <NUM_LIT> ) , LD -> getMemOperand ( ) -> getFlags ( ) ) ; DAG . ReplaceAllUsesOfValueWith ( SDValue ( LD , <NUM_LIT> ) , NewLD2 . getValue ( <NUM_LIT> ) ) ; if ( DCI . DAG . getDataLayout ( ) . isBigEndian ( ) ) std :: swap ( NewLD1 , NewLD2 ) ; SDValue Result = DCI . CombineTo ( N , NewLD1 , NewLD2 ) ; return


<s> return std :: any_of ( std :: begin ( ArchList ) , std :: end ( ArchList ) , [ HexArch ] ( Val V )


<s> cached_match = target_mcu ; if ( strncasecmp ( target_mcu , <STR_LIT> , <NUM_LIT> ) == <NUM_LIT> ) return cached_result = true ; if ( strncasecmp ( target_mcu , <STR_LIT> , <NUM_LIT> ) == <NUM_LIT> ) return cached_result = true ; if ( strncasecmp ( target_mcu , <STR_LIT> , <NUM_LIT> ) == <NUM_LIT> ) return cached_result = true ; msp430_extract_mcu_data ( target_mcu ) ; if ( extracted_mcu_data . name != NULL ) return cached_result = extracted_mcu_data . hwmpy == <NUM_LIT> ; return cached_result =


<s> static bool eliminate_mem_intrinsic ( Function & F , IntrinsicInst * II , StringRef name , L should_eliminate_call ) { assert ( II -> arg_size ( ) >= <NUM_LIT> ) ; auto arg0 = II -> getArgOperand ( <NUM_LIT> ) ; auto arg2 = II -> getArgOperand ( <NUM_LIT> ) ; assert ( cast < PointerType > ( arg0 -> getType ( ) ) -> getAddressSpace ( ) == <NUM_LIT> ) ; assert ( arg0 -> getType ( ) -> getContainedType ( <NUM_LIT> ) -> isIntegerTy ( <NUM_LIT> ) ) ; assert ( arg2 -> getType ( ) -> isIntegerTy ( <NUM_LIT> ) || arg2 ->

getType ( ) -> isIntegerTy ( <NUM_LIT> ) ) ;


<s> rtx base , index ; switch ( GET_CODE ( x ) ) { case CONST : case SYMBOL_REF : case LABEL_REF : return speed ? <NUM_LIT> : <NUM_LIT> ; case REG : case SUBREG : case POST_INC : return <NUM_LIT> ; case POST_MODIFY : i = ( CONST_INT_P ( XEXP ( x , <NUM_LIT> ) ) ? INTVAL ( XEXP ( x , <NUM_LIT> ) ) : <NUM_LIT> ) ; if ( IN_RANGE ( i , - <NUM_LIT> , <NUM_LIT> ) ) return speed ? <NUM_LIT> : <NUM_LIT> ; if ( speed ) return <NUM_LIT> ; if ( IN_RANGE ( i , - <NUM_LIT> , <NUM_LIT> ) ) return <NUM_LIT> ; return <NUM_LIT> ; case


<s> case <STR_LIT> : case <STR_LIT> : if ( ( Idx == <NUM_LIT> ) && Imm . getBitWidth ( ) <= <NUM_LIT> && isInt < <NUM_LIT> > ( Imm . getSExtValue ( ) ) ) return TCC_Free ; break ; } return <ISA_LIT>TTI :: getIntImmCost (


<s> static <ISA_LIT>Operand :: Ptr CreateImm ( const <ISA_LIT>AsmParser * AsmParser , int64_t Val , SMLoc Loc , ImmTy Type = ImmTyNone , bool


<s> if ( HasAVX ) return CSR_64_AllRegs_AVX_SaveList ; return CSR_64_AllRegs_SaveList ; case CallingConv :: PreserveMost : return CSR_64_RT_MostRegs_SaveList ; case CallingConv :: PreserveAll : if ( HasAVX ) return CSR_64_RT_AllRegs_AVX_SaveList ; return CSR_64_RT_AllRegs_SaveList ; case CallingConv :: CXX_FAST_TLS : if ( Is64Bit ) return MF -> getInfo < <ISA_LIT>MachineFunctionInfo > ( ) -> isSplitCSR ( ) ? CSR_64_CXX_TLS_Darwin_PE_SaveList : CSR_64_TLS_Darwin_SaveList ; break ; case CallingConv :: Intel_OCL_BI : { if ( HasAVX512 && IsWin64 ) return CSR_Win64_Intel_OCL_BI_AVX512_SaveList ; if ( HasAVX512 && Is64Bit ) return CSR_64_Intel_OCL_BI_AVX512_SaveList ; if ( HasAVX && IsWin64 ) return CSR_Win64_Intel_OCL_BI_AVX_SaveList ; if ( HasAVX && Is64Bit ) return CSR_64_Intel_OCL_BI_AVX_SaveList ; if ( ! HasAVX && ! IsWin64 && Is64Bit ) return CSR_64_Intel_OCL_BI_SaveList ; break ; } case CallingConv :: HHVM : return CSR_64_HHVM_SaveList ; case CallingConv :: <ISA_LIT>_RegCall : if ( Is64Bit ) { if ( IsWin64 ) { return ( HasSSE ? CSR_Win64_RegCall_SaveList : CSR_Win64_RegCall_NoSSE_SaveList ) ; } else { return ( HasSSE ? CSR_SysV64_RegCall_SaveList : CSR_SysV64_RegCall_NoSSE_SaveList ) ; } } else { return ( HasSSE ? CSR_32_RegCall_SaveList : CSR_32_RegCall_NoSSE_SaveList ) ; } case CallingConv :: Cold : if ( Is64Bit ) return CSR_64_MostRegs_SaveList ; break ; case CallingConv :: <ISA_LIT>_64_Win64 : if ( ! HasSSE ) return CSR_Win64_NoSSE_SaveList ; return CSR_Win64_SaveList ; case CallingConv :: <ISA_LIT>_64_SysV : if ( CallsEHReturn ) return CSR_64EHRet_SaveList ; return CSR_64_SaveList ; case CallingConv :: <ISA_LIT>_INTR : if ( Is64Bit ) { if ( HasAVX512 )


<s> if ( llvm :: any_of ( F . args ( ) , [ ] ( const Argument & A ) { return isa < ScalableVectorType > ( A . getType ( ) ) ; } ) ) return true ; const auto & ST = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( ! ST . hasNEON ( ) || ! ST . hasFPARMv8 ( ) ) { LLVM_DEBUG ( dbgs (


<s> bool <ISA_LIT>Shuffler :: ValidResourceUsage ( <ISA_LIT>PacketSummary const & Summary ) { Optional < <ISA_LIT>Packet > ShuffledPacket = tryAuction ( Summary ) ; if ( ! ShuffledPacket ) { reportError ( <STR_LIT> ) ; return false ; } else { Packet = * ShuffledPacket ; } llvm :: stable_sort ( * this , <STR_LIT> ) ; HVXInstsT hvxInsts ; hvxInsts . clear ( ) ; for ( const_iterator I = cbegin ( ) ; I != cend ( ) ; ++ I ) { struct CVIUnits inst ; inst . Units = I -> CVI . getUnits ( ) ; inst . Lanes = I -> CVI . getLanes ( ) ; if ( inst . Units == <NUM_LIT> ) continue ; hvxInsts . push_back ( inst ) ; } if ( hvxInsts . size ( ) > <NUM_LIT> ) { unsigned startIdx , usedUnits ; startIdx = usedUnits = <NUM_LIT> ; if ( ! checkHVXPipes ( hvxInsts , startIdx , usedUnits ) ) { reportError ( Twine ( <STR_LIT> ) ) ; return false


<s> if ( auto PreHeader = L -> getLoopPreheader ( ) ) if ( ! VisitedBlocks . count ( PreHeader ) ) Worklist . push_back ( PreHeader ) ; while ( ! Worklist . empty ( ) ) { auto BB = Worklist . pop_back_val ( ) ; LoopOptimized |= Optimize_PreWhileConversion ( BB ) ; LoopOptimized |= Optimize_PostWhileConversion ( BB ) ; LoopOptimized |= Transform_StructAddressing ( BB ) ; VisitedBlocks . insert ( BB ) ; } ++ NumVisited ; if ( LoopOptimized ) ++


<s> bool <ISA_LIT>AddressTypePromotion :: runOnFunction ( Function & F ) { if ( skipFunction ( F ) ) return false ; if ( F . isDeclaration ( ) ) return false ; Func =


<s> void mips16_expand_set_fcsr ( rtx newval ) { if ( ! mips16_set_fcsr_stub ) mips16_set_fcsr_stub = new mips16_set_fcsr_one_only_stub ( ) ; rtx fn = mips16_stub_call_address


<s> cbranch_trace ( rtx_insn * insn ) : cbranch_insn ( insn ) , condition_rtx_in_insn ( NULL ) , cbranch_type ( unknown_branch_condition ) , setcc ( ) { if ( is_conditional_insn ( cbranch_insn ) ) condition_rtx_in_insn = & XEXP ( XEXP ( PATTERN ( cbranch_insn ) , <NUM_LIT> ) , <NUM_LIT> ) ; else if ( rtx x = pc_set ( cbranch_insn ) ) condition_rtx_in_insn = & XEXP (


<s> static __inline void si_stqx ( qword a , qword b , qword c ) { vec_st ( ( vec_uchar16 ) ( a ) , si_to_uint ( ( qword ) ( vec_add ( ( vec_uint4 ) ( b ) , ( vec_uint4 ) (

c ) ) ) ) , ( vector unsigned char * ) ( <NUM_LIT> ) ) ;


<s> bool IsConstantInc = false ; const SCEV * BasePtrIncSCEV = BasePtrSCEV -> getStepRecurrence ( * SE ) ; Value * IncNode = getNodeForInc ( L , BaseMemI , BasePtrIncSCEV ) ; const SCEVConstant * BasePtrIncConstantSCEV = dyn_cast < SCEVConstant > ( BasePtrIncSCEV ) ; if ( BasePtrIncConstantSCEV ) IsConstantInc = true ; if ( ! IncNode ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return std :: make_pair ( nullptr , nullptr ) ; } const SCEV * BasePtrStartSCEV = nullptr ; if ( CanPreInc ) { assert ( SE -> isLoopInvariant ( BasePtrIncSCEV , L ) && <STR_LIT> ) ; BasePtrStartSCEV = SE -> getMinusSCEV ( BasePtrSCEV -> getStart ( ) , IsConstantInc ? BasePtrIncConstantSCEV : BasePtrIncSCEV ) ; } else BasePtrStartSCEV = BasePtrSCEV -> getStart ( ) ; if ( alreadyPrepared ( L , BaseMemI , BasePtrStartSCEV , BasePtrIncSCEV , Form ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return std :: make_pair ( nullptr , nullptr ) ; } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * BasePtrStartSCEV << <STR_LIT> ) ; BasicBlock * Header = L -> getHeader ( ) ; unsigned HeaderLoopPredCount = pred_size ( Header ) ; BasicBlock * LoopPredecessor = L -> getLoopPredecessor ( ) ; PHINode * NewPHI = PHINode :: Create ( I8PtrTy , HeaderLoopPredCount , getInstrName ( BaseMemI , PHINodeNameSuffix ) , Header -> getFirstNonPHI ( ) ) ; Value * BasePtrStart = SCEVE . expandCodeFor ( BasePtrStartSCEV , I8PtrTy , LoopPredecessor -> getTerminator ( ) ) ; for ( auto PI : predecessors ( Header ) ) { if ( PI != LoopPredecessor ) continue ; NewPHI -> addIncoming ( BasePtrStart , LoopPredecessor ) ; } Instruction * PtrInc = nullptr ; Instruction * NewBasePtr


<s> assert ( M . getSimpleValueType ( ) . SimpleTy == C . getSimpleValueType ( ) . SimpleTy && <STR_LIT> ) ; return OR ( XOR ( ADD ( AND ( M , C ) , C ) , C


<s> struct constant_pool * curr_pool = NULL ; rtx insn ; for ( curr_pool = pool_list ; curr_pool ; curr_pool = curr_pool -> next ) { rtx barrier = PREV_INSN ( curr_pool -> pool_insn ) ; rtx jump = barrier ? PREV_INSN ( barrier ) : NULL_RTX ; rtx label = NEXT_INSN ( curr_pool -> pool_insn ) ; if ( jump && GET_CODE ( jump ) == JUMP_INSN && barrier && GET_CODE ( barrier ) == BARRIER && label && GET_CODE ( label ) == CODE_LABEL && GET_CODE ( PATTERN ( jump ) ) == SET && SET_DEST ( PATTERN ( jump ) ) == pc_rtx && GET_CODE ( SET_SRC ( PATTERN ( jump ) ) ) == LABEL_REF && XEXP ( SET_SRC ( PATTERN ( jump ) ) , <NUM_LIT> ) == label ) { remove_insn ( jump ) ; remove_insn ( barrier ) ; remove_insn ( label ) ; } remove_insn ( curr_pool -> pool_insn ) ; } for ( insn = get_insns ( ) ; insn ; ) { rtx next_insn = NEXT_INSN ( insn


<s> bool isImm8s4 ( ) const { if ( Kind != k_Immediate ) return false ; const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; if ( ! CE ) return


<s> bool <ISA_LIT>FrameLowering :: enableShrinkWrapping ( const MachineFunction & MF ) const { if ( STI . hasV8_1MMainlineOps ( ) && MF . getInfo < <ISA_LIT>FunctionInfo > ( ) -> isCmseNSEntryFunction ( ) ) return false ; if ( MF . getInfo < <ISA_LIT>FunctionInfo > ( ) -> shouldSignReturnAddress ( true ) ) return false ; return


<s> case TargetOpcode :: G_ZEXT : return <STR_LIT> ; case TargetOpcode :: G_ANYEXT : return <STR_LIT> ; default : llvm_unreachable ( <STR_LIT>


<s> MachineBasicBlock * B = & MBB ; do { if ( ! Visited . insert ( B ) . second ) return MBB . end ( ) ; auto E = B -> end ( ) ; for ( ; It != E ; ++ It ) { if ( It -> getOpcode ( ) == <STR_LIT> ) continue ; if ( TII -> mayReadEXEC ( * MRI , * It ) ) break ; } if ( It != E ) return It ; if ( B -> succ_size ( ) != <NUM_LIT> ) return MBB . end ( ) ; MachineBasicBlock * Succ = * B -> succ_begin ( ) ; It = Succ -> begin ( ) ; B = Succ ; } while ( true


<s> void setReg ( unsigned Val ) { Contents . RegNum =


<s> StringRef getPassName ( ) const override { return


<s> unsigned Reg = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * MBB , MI , MI . getDebugLoc ( ) , TII -> get ( <STR_LIT> )

, Reg ) . add ( Base ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) ;


<s> for ( unsigned Reg : RegClassInfo . getOrder ( & RegClass ) ) if ( LiveRegs . available ( MF -> getRegInfo ( ) , Reg ) ) return Reg ; return <NUM_LIT>


<s> if ( StackSize == <NUM_LIT> && ! MFI -> adjustsStack ( ) ) return ; MachineModuleInfo & MMI = MF . getMMI ( ) ; const MCRegisterInfo * MRI = MMI . getContext ( ) . getRegisterInfo ( ) ; MachineLocation DstML , SrcML ; TII . makeFrame ( <STR_LIT> , StackSize , MBB , MBBI ) ; unsigned CFIIndex = MMI . addFrameInst ( MCCFIInstruction :: createDefCfaOffset ( nullptr , - StackSize ) ) ; BuildMI ( MBB , MBBI , dl , TII . get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; const std :: vector < CalleeSavedInfo > & CSI = MFI -> getCalleeSavedInfo ( ) ; if ( CSI . size ( ) ) { const std :: vector < CalleeSavedInfo > & CSI = MFI -> getCalleeSavedInfo ( ) ; for ( std :: vector < CalleeSavedInfo > :: const_iterator I = CSI . begin ( ) , E = CSI . end ( ) ; I != E ; ++ I ) { int64_t Offset = MFI -> getObjectOffset ( I -> getFrameIdx ( ) ) ; unsigned Reg = I -> getReg ( ) ; unsigned DReg = MRI -> getDwarfRegNum (


<s> static bool is128BitUnpackShuffleMask ( ArrayRef < int > Mask ) { MVT EltVT = <STR_LIT> ( <NUM_LIT> / Mask . size ( ) ) ; MVT VT = <STR_LIT> ( EltVT , Mask . size ( ) ) ; for ( unsigned i = <NUM_LIT> ; i != <NUM_LIT> ; ++ i ) { SmallVector < int , <NUM_LIT>


<s> const uint16_t * table = lookup ( MI . getOpcode ( ) , dom ) ; if ( ! table ) { assert ( ( Subtarget . hasAVX2 ( ) || Domain < <NUM_LIT> )


<s> unsigned Reg = CCSI . getReg ( ) ; assert ( TRI -> getRegSizeInBits ( * TRI -> getMinimalPhysRegClass ( Reg ) ) == <NUM_LIT> && <STR_LIT> ) ; BuildMI ( MBB , MI , DL , TII


<s> pure_scalable_type_info :: analysis_result pure_scalable_type_info :: analyze ( const_tree type ) { gcc_assert ( pieces . is_empty ( ) ) ; if ( type == error_mark_node ) return NO_ABI_IDENTITY ; if ( TYPE_SIZE ( type ) && integer_zerop ( TYPE_SIZE ( type ) ) ) return NO_ABI_IDENTITY ; piece p =


<s> unsigned NumElts = InVT . getVectorNumElements ( ) ; if ( InVT . getVectorElementType ( ) == <STR_LIT> ) { MVT NewVT = <STR_LIT> ( <STR_LIT> , NumElts ) ; SDLoc dl ( Op ) ; return DAG . getNode ( Op . getOpcode ( ) , dl , Op . getValueType ( ) , DAG . getNode ( <STR_LIT> , dl , NewVT , Op . getOperand ( <NUM_LIT> ) ) ) ; } if ( VT . getSizeInBits ( ) < InVT . getSizeInBits ( ) ) { SDLoc dl ( Op ) ; SDValue Cv = DAG . getNode ( Op . getOpcode ( ) , dl , InVT . changeVectorElementTypeToInteger ( ) , Op . getOperand ( <NUM_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Cv ) ; } if ( VT . getSizeInBits ( ) > InVT . getSizeInBits ( ) ) { SDLoc dl ( Op ) ; MVT ExtVT = <STR_LIT> ( <STR_LIT> ( VT . getScalarSizeInBits ( ) ) , VT . getVectorNumElements ( ) ) ; SDValue Ext = DAG . getNode ( <STR_LIT> , dl , ExtVT , Op . getOperand


<s> default : llvm_unreachable ( <STR_LIT> ) ; case 'i' : Imm |= <STR_LIT> ; break ; case 'o' : Imm |= <STR_LIT> ; break ; case 'r' : Imm |= <STR_LIT> ; break ; case 'w' : Imm


<s> __builtin_ia32_pmovusqb512mem_mask ( ( unsigned long long * ) __P , ( __v8di


<s> DEBUG ( errs ( ) << <STR_LIT> << * CI << <STR_LIT> << * opr0 << <STR_LIT> ) ; replaceCall ( opr0 ) ; return true ; } if ( ci_opr1 == <NUM_LIT> ) { std :: vector < const Type * > ParamsTys ; ParamsTys . push_back ( opr0 -> getType ( ) ) ; Module * M = CI -> getModule ( ) ; if ( Constant * FPExpr = getFunction ( M , <ISA_LIT>LibFunc ( <ISA_LIT>LibFunc :: EI_SQRT , FInfo ) ) ) { DEBUG ( errs ( ) << <STR_LIT> << * CI << <STR_LIT> << * opr0 << <STR_LIT> ) ; Value * nval = CreateCallEx ( B , FPExpr , opr0 , <STR_LIT> ) ; replaceCall ( nval ) ; return true ; } } else if ( ci_opr1 == <NUM_LIT> ) { Module * M = CI -> getModule


<s> MVT EltVT = VT . getVectorElementType ( ) ; unsigned VecSize = VT . getSizeInBits ( ) ; const int LUT [ <NUM_LIT> ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; int NumByteElts = VecSize / <NUM_LIT> ; MVT ByteVecVT = <STR_LIT> ( <STR_LIT> , NumByteElts ) ; SDValue In = DAG . getBitcast ( ByteVecVT , Op ) ; SmallVector < SDValue , <NUM_LIT> > LUTVec ; for ( int i = <NUM_LIT> ; i < NumByteElts ; ++ i ) LUTVec . push_back ( DAG . getConstant ( LUT [ i % <NUM_LIT> ] , DL , <STR_LIT> ) ) ; SDValue InRegLUT = DAG . getNode ( <STR_LIT> , DL , ByteVecVT , LUTVec ) ; SmallVector < SDValue , <NUM_LIT> > Mask0F ( NumByteElts , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; SDValue M0F = DAG . getNode ( <STR_LIT> , DL , ByteVecVT , Mask0F ) ; SmallVector < SDValue , <NUM_LIT> > Four ( NumByteElts , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; SDValue FourV = DAG . getNode ( <STR_LIT> , DL , ByteVecVT , Four ) ; SDValue HighNibbles = DAG . getNode ( <STR_LIT> , DL , ByteVecVT , In , FourV ) ; SDValue LowNibbles = DAG . getNode ( <STR_LIT> , DL , ByteVecVT , In , M0F ) ; SDValue HighPopCnt = DAG . getNode ( <STR_LIT> , DL ,


<s> state -> insns_left = state -> issue_rate ; memset ( & state -> last_set , <NUM_LIT> , sizeof ( state -> last_set ) ) ; state_reset ( state ->


<s> uint32_t getPacketBits ( MCInst const & HMI ) { unsigned const ParseFieldOffset = <NUM_LIT> ; ParseField Field = <ISA_LIT>MCInstrInfo :: isPacketEnd ( HMI ) ? ParseField ::


<s> bool vl_vtype_info :: same_vtype_p ( const vl_vtype_info & other ) const { return get_sew ( ) == other . get_sew ( ) && get_vlmul ( ) == other . get_vlmul ( ) && get_ta ( ) == other

. get_ta ( ) && get_ma ( ) == other . get_ma ( ) ;


<s> if ( EltVT == <STR_LIT> && ! Subtarget . is64Bit ( ) ) { EltVT = <STR_LIT> ; MaskVT = <STR_LIT> ( EltVT , Mask . size ( ) ) ; } MVT LogicVT = VT ; if ( EltVT == <STR_LIT> || EltVT == <STR_LIT> ) { Zero = DAG . getConstantFP ( <NUM_LIT> , DL , EltVT ) ; APFloat AllOnesValue = APFloat :: getAllOnesValue ( SelectionDAG :: EVTToAPFloatSemantics ( EltVT ) , EltVT . getSizeInBits ( ) ) ; AllOnes = DAG . getConstantFP ( AllOnesValue , DL , EltVT ) ; LogicVT = <STR_LIT> ( EltVT == <STR_LIT> ? <STR_LIT> : <STR_LIT> , Mask . size ( ) ) ; } else { Zero = DAG . getConstant ( <NUM_LIT> , DL , EltVT ) ; AllOnes = DAG . getAllOnesConstant ( DL , EltVT ) ; } SmallVector < SDValue , <NUM_LIT> > VMaskOps ( Mask . size ( ) , Zero ) ; SDValue V ; for ( int i = <NUM_LIT> , Size = Mask . size ( ) ; i < Size ; ++ i ) { if ( Zeroable [ i ] ) continue ; if ( Mask [ i ] % Size != i ) return SDValue ( ) ; if ( ! V ) V = Mask [ i ] < Size ? V1 : V2 ; else if ( V != ( Mask [ i ] < Size ? V1 : V2 ) ) return SDValue ( ) ; VMaskOps [ i ] = AllOnes ; } if ( ! V )


<s> getTargetStreamer ( ) . emitARM64WinCFIMachineFrame


<s> MVT getScalarShiftAmountTy ( const DataLayout & , EVT LHSTy ) const override { return <STR_LIT>


<s> switch ( SETCC ) { default : return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case


<s> return recog_memoized ( insn ) >= <NUM_LIT> && get_attr_cannot_copy


<s> ScheduleDAGInstrs * createPostMachineScheduler ( MachineSchedContext * C


<s> name += skip ; } if ( verbatim ) fputs ( name , stream ) ; else asm_fprintf ( stream ,


<s> MCObjectWriter * llvm :: create<ISA_LIT>MachObjectWriter ( raw_ostream & OS , uint32_t CPUType , uint32_t CPUSubtype ) { return createMachObjectWriter ( new <ISA_LIT>MachObjectWriter ( CPUType , CPUSubtype


<s> __inline__ static void sh_media_FVCOPY_S ( const void * fvg ,


<s> static inline uint32_t helper_reencode_ldst_pos_imm ( uint32_t pInst , uint32_t pImm ) { return ( pInst & ~ ( get_mask ( <NUM_LIT> ) << <NUM_LIT> ) )

| ( ( pImm & get_mask ( <NUM_LIT> ) ) << <NUM_LIT> ) ;


<s> bool nios2_large_constant_p ( rtx x ) { return ( nios2_symbolic_constant_p ( x ) || nios2_large_unspec_reloc_p ( x ) || ( CONST_INT_P ( x ) &&


<s> void <ISA_LIT>SEInstrInfo :: expandExtractElementF64 ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , bool FP64 ) const { unsigned DstReg = I -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned SrcReg = I -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned N = I -> getOperand ( <NUM_LIT> ) . getImm ( ) ; DebugLoc dl = I -> getDebugLoc ( ) ; assert ( N < <NUM_LIT> && <STR_LIT> ) ; unsigned SubIdx = N ? <STR_LIT> : <STR_LIT> ; unsigned SubReg = getRegisterInfo ( ) . getSubReg ( SrcReg , SubIdx ) ; assert ( ! ( Subtarget . isABI_FPXX ( ) && ! Subtarget . has<ISA_LIT>32r2 ( ) ) ) ; assert ( ! ( Subtarget . isFP64bit ( ) &&


<s> return new <ISA_LIT>AsmBackend ( TT . isArch64Bit ( )


<s> static void avr_option_override ( void ) { flag_delete_null_pointer_checks = <NUM_LIT> ; if ( avr_strict_X ) flag_caller_saves = <NUM_LIT> ; maybe_set_param_value ( PARAM_ALLOW_STORE_DATA_RACES , <NUM_LIT> , global_options . x_param_values , global_options_set . x_param_values ) ; if ( ( flag_unwind_tables || flag_non_call_exceptions || flag_asynchronous_unwind_tables ) && ! ACCUMULATE_OUTGOING_ARGS ) { flag_omit_frame_pointer = <NUM_LIT> ; } if ( flag_pic == <NUM_LIT> ) warning ( OPT_fpic , <STR_LIT> ) ; if ( flag_pic == <NUM_LIT> ) warning ( OPT_fPIC , <STR_LIT> ) ; if ( flag_pie == <NUM_LIT> ) warning ( OPT_fpie , <STR_LIT> ) ; if ( flag_pie == <NUM_LIT> ) warning ( OPT_fPIE , <STR_LIT> ) ; if ( ! avr_set_core_architecture ( ) ) return ; avr_addr . sreg = <NUM_LIT> + avr_arch -> sfr_offset ; avr_addr . rampz = <NUM_LIT> + avr_arch -> sfr_offset ; avr_addr . rampy = <NUM_LIT> + avr_arch -> sfr_offset ; avr_addr . rampx = <NUM_LIT>


<s> for ( i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) fixed_regs [ i ] = <NUM_LIT> ; } if ( TARGET_ES0 && strcmp ( lang_hooks . name , <STR_LIT> ) && strcmp ( lang_hooks .

name , <STR_LIT> ) ) error ( <STR_LIT> ) ;


<s> <ISA_LIT>MCAsmStreamer :: <ISA_LIT>MCAsmStreamer ( MCContext & Ctx , std :: unique_ptr < formatted_raw_ostream > os , bool isVerboseAsm , MCInstPrinter * printer , bool showInst ) : MCStreamer ( Ctx ) , OSOwner ( std :: move ( os ) ) , OS ( * OSOwner ) , MAI ( Ctx . getAsmInfo ( ) ) , InstPrinter ( printer ) , CommentStream ( CommentToEmit ) , IsVerboseAsm ( isVerboseAsm ) , ShowInst ( showInst ) { assert ( InstPrinter )


<s> return ( int8x8_t ) __builtin_neon_vreinterpretv8qiv8qi ( (


<s> int64_t IntVal ; if ( ! MatchRegisterName ( Parser . getTok ( ) , RegNo , IntVal ) ) { Parser . Lex ( ) ; Op = <ISA_LIT>Operand :: CreateImm ( IntVal , S , E , is<ISA_LIT>64 ( ) ) ; Operands . push_back ( Op ) ; return false ; } return Error ( S , <STR_LIT> ) ; case AsmToken :: LParen : case AsmToken :: Plus : case AsmToken :: Minus : case AsmToken :: Integer : case AsmToken :: Identifier : case AsmToken :: Dot : case AsmToken :: Dollar : if ( ! getParser ( ) . parseExpression ( EVal ) ) break ; default : return Error ( S , <STR_LIT> ) ; } if ( const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( EVal ) ) Op = <ISA_LIT>Operand :: CreateImm ( CE -> getValue ( ) , S , E , is<ISA_LIT>64 ( ) ) ; else Op = <ISA_LIT>Operand :: CreateExpr ( EVal , S , E , is<ISA_LIT>64 ( ) ) ; Operands . push_back ( Op ) ; if ( getLexer ( ) . is ( AsmToken :: LParen ) ) { Parser . Lex ( ) ; S = Parser . getTok ( ) . getLoc ( ) ; int64_t IntVal ; switch ( getLexer ( ) . getKind ( ) ) { case AsmToken :: Percent : Parser . Lex ( ) ; unsigned RegNo ; if ( MatchRegisterName ( Parser . getTok ( ) , RegNo , IntVal ) ) return Error ( S , <STR_LIT> ) ; Parser . Lex ( ) ; break ; case AsmToken :: Integer : if ( getParser ( ) . parseAbsoluteExpression ( IntVal ) || IntVal < <NUM_LIT> || IntVal > <NUM_LIT> ) return


<s> unsigned ImmReg = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( CI -> isZero ( ) ? <STR_LIT> : <STR_LIT> ) , ImmReg ) ; return ImmReg ; } if ( VT != <STR_LIT> && VT != <STR_LIT> && VT != <STR_LIT> && VT != <STR_LIT> && VT != <STR_LIT> ) return <NUM_LIT> ; const TargetRegisterClass * RC = ( ( VT == <STR_LIT> ) ? & <STR_LIT> :


<s> assert ( getTargetMachine ( ) . getCodeModel ( ) == CodeModel :: Small ) ; EVT PtrVT = getPointerTy ( ) ; DebugLoc dl = Op . getDebugLoc ( ) ; const GlobalAddressSDNode * GN = cast < GlobalAddressSDNode > ( Op ) ; const GlobalValue * GV = GN -> getGlobal ( ) ; unsigned Alignment = GV -> getAlignment ( ) ; Reloc :: Model RelocM = getTargetMachine ( ) . getRelocationModel ( ) ; if ( GV -> isWeakForLinker ( ) && GV -> isDeclaration ( ) && RelocM == Reloc :: Static ) { SDValue PoolAddr ; PoolAddr = DAG . getNode ( <STR_LIT> , dl , PtrVT , DAG . getTargetConstantPool ( GV , PtrVT , <NUM_LIT> , <NUM_LIT> , <STR_LIT> ) , DAG . getTargetConstantPool ( GV , PtrVT , <NUM_LIT> , <NUM_LIT> , <STR_LIT> ) , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDValue GlobalAddr = DAG . getLoad ( PtrVT , dl , DAG . getEntryNode ( ) , PoolAddr , MachinePointerInfo :: getConstantPool ( ) , false , true , true , <NUM_LIT> ) ; if ( GN -> getOffset ( ) != <NUM_LIT> ) return DAG . getNode ( <STR_LIT> , dl , PtrVT , GlobalAddr , DAG . getConstant ( GN -> getOffset ( ) , PtrVT ) ) ; return GlobalAddr ; } if ( Alignment == <NUM_LIT> ) { const PointerType * GVPtrTy = cast < PointerType > ( GV -> getType ( ) ) ; if ( GVPtrTy -> getElementType ( ) -> isSized ( ) ) { Alignment = getDataLayout ( ) -> getABITypeAlignment ( GVPtrTy -> getElementType ( ) ) ; } else { Alignment = <NUM_LIT> ; } } unsigned char HiFixup , LoFixup ; bool UseGOT = Subtarget -> GVIsIndirectSymbol ( GV , RelocM ) ; if ( UseGOT ) { HiFixup = <STR_LIT> ; LoFixup =


<s> for ( i = R16_REG ; i <= R25_REG ; i ++ ) fixed_regs [ i ] = call_used_regs [ i ] = <NUM_LIT> ; } if ( TARGET_HS ) for ( regno = R1_REG ; regno < R32_REG ; regno += <NUM_LIT> ) arc_hard_regno_modes [ regno ] = S_MODES ; for ( i = <NUM_LIT> ; i < FIRST_PSEUDO_REGISTER ; i ++ ) if ( i < ILINK1_REG ) { if ( ( TARGET_Q_CLASS || TARGET_RRQ_CLASS ) && ( ( i <= R3_REG ) || ( ( i >= R12_REG ) && ( i <= R15_REG ) ) ) ) arc_regno_reg_class [ i ] = ARCOMPACT16_REGS ; else arc_regno_reg_class [ i ] = GENERAL_REGS ; } else if ( i < LP_COUNT ) arc_regno_reg_class [ i ] = GENERAL_REGS ; else arc_regno_reg_class [ i ] = NO_REGS ; arc_regno_reg_class [ CC_REG ] = NO_REGS ; arc_regno_reg_class [ FRAME_POINTER_REGNUM ] = GENERAL_REGS ; arc_regno_reg_class [ ARG_POINTER_REGNUM ] = GENERAL_REGS ; if ( TARGET_DPFP ) for ( i = R40_REG ; i < R44_REG ; ++ i ) { arc_regno_reg_class [ i ] = DOUBLE_REGS ; if ( ! TARGET_ARGONAUT_SET ) CLEAR_HARD_REG_BIT ( reg_class_contents [ GENERAL_REGS ] , i ) ; } else { arc_regno_reg_class [ R40_REG ] = ALL_REGS ; arc_regno_reg_class [ R41_REG ] = ALL_REGS ; arc_regno_reg_class [ R42_REG ] = ALL_REGS ; arc_regno_reg_class [ R43_REG ] = ALL_REGS ; fixed_regs [ R40_REG ] = <NUM_LIT> ; fixed_regs [ R41_REG ] = <NUM_LIT> ; fixed_regs [ R42_REG ] = <NUM_LIT> ; fixed_regs [ R43_REG ] = <NUM_LIT> ; arc_hard_regno_modes [ R40_REG ] = <NUM_LIT> ; arc_hard_regno_modes [ R42_REG ] = <NUM_LIT> ; } if ( TARGET_SIMD_SET ) { gcc_assert ( ARC_FIRST_SIMD_VR_REG == <NUM_LIT> ) ; gcc_assert ( ARC_LAST_SIMD_VR_REG == <NUM_LIT> ) ; for ( i = ARC_FIRST_SIMD_VR_REG ; i <= ARC_LAST_SIMD_VR_REG ; i ++ ) arc_regno_reg_class [ i ] = SIMD_VR_REGS ; gcc_assert ( ARC_FIRST_SIMD_DMA_CONFIG_REG == <NUM_LIT> ) ; gcc_assert ( ARC_FIRST_SIMD_DMA_CONFIG_IN_REG == <NUM_LIT> ) ; gcc_assert ( ARC_FIRST_SIMD_DMA_CONFIG_OUT_REG == <NUM_LIT> ) ; gcc_assert ( ARC_LAST_SIMD_DMA_CONFIG_REG == <NUM_LIT> ) ; for ( i = ARC_FIRST_SIMD_DMA_CONFIG_REG ; i <= ARC_LAST_SIMD_DMA_CONFIG_REG ; i ++ ) arc_regno_reg_class [ i ] = SIMD_DMA_CONFIG_REGS ; } arc_regno_reg_class [ PCL_REG ] = NO_REGS ; if ( ( TARGET_V2 && ( TARGET_FP_DP_FUSED || TARGET_FP_SP_FUSED ) ) ||


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return


<s> return new <ISA_LIT>ELFStreamer ( Context , MAB , OS , Emitter


<s> DiagnosticInfoUnsupported Diag ( * MI -> getParent ( ) -> getParent ( ) ->


<s> bool <ISA_LIT>PreAllocLoadStoreOpt :: RescheduleLoadStoreInstrs ( MachineBasicBlock * MBB ) { bool RetVal = false ; DenseMap < MachineInstr * , unsigned > MI2LocMap ; DenseMap < unsigned , SmallVector < MachineInstr * , <NUM_LIT> > > Base2LdsMap ; DenseMap < unsigned , SmallVector < MachineInstr * , <NUM_LIT> > > Base2StsMap ; SmallVector < unsigned , <NUM_LIT> > LdBases ; SmallVector < unsigned , <NUM_LIT> > StBases ; unsigned Loc = <NUM_LIT> ; MachineBasicBlock :: iterator MBBI = MBB -> begin ( ) ; MachineBasicBlock :: iterator E = MBB -> end ( ) ; while ( MBBI != E ) { for ( ; MBBI != E ; ++ MBBI ) { MachineInstr * MI = MBBI ; const MCInstrDesc & MCID = MI -> getDesc ( ) ; if ( MCID . isCall ( ) || MCID . isTerminator ( ) ) { ++ MBBI ; break ; } if ( ! MI -> isDebugValue ( ) ) MI2LocMap [ MI ] = ++ Loc ; if ( ! isMemoryOp ( MI ) ) continue ; unsigned PredReg = <NUM_LIT> ; if ( llvm :: getInstrPredicate ( MI , PredReg ) != <STR_LIT> ) continue ; int Opc = MI -> getOpcode ( ) ; bool isLd = isi32Load ( Opc ) || Opc == <STR_LIT> || Opc == <STR_LIT> ; unsigned Base = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; int Offset = getMemoryOpOffset ( MI ) ; bool StopHere = false ; if ( isLd ) { DenseMap < unsigned , SmallVector < MachineInstr * , <NUM_LIT> > > :: iterator BI = Base2LdsMap .


<s> const ConstantArray * InitList = dyn_cast < ConstantArray > ( GV -> getInitializer ( ) ) ; if ( ! InitList


<s> bool <ISA_LIT>FastISel :: <ISA_LIT>EmitStore ( EVT VT , unsigned SrcReg , Address & Addr , unsigned Alignment ) { unsigned StrOpc ; bool useAM3 = false ; switch ( VT . getSimpleVT ( ) . SimpleTy ) { default : return false ; case <STR_LIT> : { unsigned Res = createResultReg ( isThumb2 ? <STR_LIT> : <STR_LIT> ) ; unsigned Opc = isThumb2 ? <STR_LIT> : <STR_LIT> ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( Opc ) , Res ) . addReg ( SrcReg ) . addImm ( <NUM_LIT> ) ) ; SrcReg = Res ; } case <STR_LIT> : if ( isThumb2 ) { if ( Addr . Offset < <NUM_LIT> && Addr . Offset > - <NUM_LIT> && Subtarget -> hasV6T2Ops ( ) ) StrOpc = <STR_LIT> ; else StrOpc = <STR_LIT> ; } else { StrOpc = <STR_LIT> ; } break ; case <STR_LIT> : if ( isThumb2 ) { if ( Addr . Offset < <NUM_LIT> && Addr . Offset > - <NUM_LIT> && Subtarget -> hasV6T2Ops ( ) ) StrOpc = <STR_LIT> ; else StrOpc = <STR_LIT> ; } else { StrOpc = <STR_LIT> ; useAM3 = true ; } break ; case <STR_LIT> : if ( isThumb2 ) { if ( Addr . Offset < <NUM_LIT> && Addr . Offset > - <NUM_LIT> && Subtarget -> hasV6T2Ops ( ) ) StrOpc = <STR_LIT> ; else StrOpc = <STR_LIT> ; } else { StrOpc = <STR_LIT> ; } break ; case <STR_LIT> : if ( ! Subtarget -> hasVFP2 ( ) ) return false ; if ( Alignment && Alignment < <NUM_LIT> ) { unsigned MoveReg = createResultReg ( TLI . getRegClassFor ( <STR_LIT> ) ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( <STR_LIT> ) , MoveReg ) . addReg ( SrcReg ) ) ; SrcReg = MoveReg ; VT = <STR_LIT> ; StrOpc = isThumb2 ? <STR_LIT> : <STR_LIT> ; } else { StrOpc = <STR_LIT> ; } break ; case <STR_LIT> : if ( ! Subtarget -> hasVFP2 ( ) ) return false ; if ( Alignment && Alignment < <NUM_LIT> ) return false ; StrOpc =


<s> bool hasArithmeticCbzFusion ( ) const { return


<s> dbgs ( ) << <STR_LIT> ; dbgs ( ) << <STR_LIT> << Print < RefMap > ( LiveIn , DFG ) << '\n' ; dbgs ( ) << <STR_LIT> << Print < RegisterAggr > ( LiveMap [ B ] , DFG ) << '\n' ; } RefMap LiveInCopy = LiveIn ; LiveIn . clear ( ) ; for ( const std :: pair < RegisterId , NodeRefSet > & LE : LiveInCopy ) { RegisterRef LRef ( LE . first ) ; NodeRefSet & NewDefs = LiveIn [ LRef . Reg ] ; const NodeRefSet & OldDefs = LE . second ; for ( NodeRef OR : OldDefs ) { auto DA = DFG . addr < DefNode * > ( OR . first ) ; NodeAddr < InstrNode * > IA = DA . Addr -> getOwner ( DFG ) ; NodeAddr < BlockNode * > BA = IA . Addr -> getOwner ( DFG ) ; if ( B != BA . Addr -> getCode ( ) ) { NewDefs . insert ( OR ) ; continue ; } RegisterAggr RRs ( TRI ) ; LRef . Mask = OR . second ; if ( ! DFG . IsPreservingDef ( DA ) ) { assert ( ! ( IA . Addr -> getFlags ( ) & NodeAttrs :: Phi ) ) ; if ( RRs . insert ( DA . Addr -> getRegRef ( DFG ) ) . hasCoverOf ( LRef ) ) continue ; } for ( NodeAddr < DefNode * > TA : getAllReachingDefs ( DA ) ) { NodeAddr < InstrNode * > ITA = TA . Addr -> getOwner ( DFG ) ; NodeAddr < BlockNode * > BTA = ITA . Addr -> getOwner ( DFG ) ; if ( BTA . Addr -> getCode ( ) != B ) { RegisterAggr L ( TRI ) ; L . insert ( LRef ) . clear ( RRs ) ; assert ( ! L . empty ( ) ) ; NewDefs . insert ( { TA . Id , L . begin ( ) -> second } ) ; break ; } if ( ! ( TA . Addr -> getFlags ( ) & NodeAttrs :: Preserving ) ) RRs . insert ( TA . Addr -> getRegRef ( DFG ) ) ; if ( RRs . hasCoverOf ( LRef ) ) break ; } } } emptify ( LiveIn ) ; if ( Trace ) { dbgs ( ) << <STR_LIT> ; dbgs ( ) << <STR_LIT> << Print < RefMap > ( LiveIn , DFG ) << '\n' ; dbgs ( ) << <STR_LIT> << Print < RegisterAggr > ( LiveMap [ B ] , DFG


<s> if ( type && ! AGGREGATE_TYPE_P ( type ) ) alignment = TYPE_ALIGN ( TYPE_MAIN_VARIANT


<s> static SDValue lowerV16F32VectorShuffle ( SDValue Op , SDValue V1 , SDValue V2 , const <ISA_LIT>Subtarget * Subtarget , SelectionDAG & DAG ) { SDLoc DL ( Op ) ; assert ( V1 . getSimpleValueType ( ) == <STR_LIT> && <STR_LIT> ) ; assert ( V2 . getSimpleValueType ( ) == <STR_LIT> && <STR_LIT> ) ; ShuffleVectorSDNode * SVOp = cast < ShuffleVectorSDNode > ( Op ) ; ArrayRef < int > Mask = SVOp -> getMask ( ) ; assert ( Mask . size ( ) == <NUM_LIT> && <STR_LIT> ) ; if ( SDValue Unpck = lowerVectorShuffleWithUNPCK ( DL , <STR_LIT> , Mask , V1 ,


<s> case <STR_LIT> : switch ( Modifier ) { case MCSymbolRefExpr :: VK_TLSCALL : Type = ELF :: R_<ISA_LIT>_THM_TLS_CALL ; break ; default : Type = ELF :: R_<ISA_LIT>_THM_CALL ; break ; } break ; } } else { switch ( ( unsigned ) Fixup . getKind ( ) ) { default : report_fatal_error ( <STR_LIT> ) ; return ELF :: R_<ISA_LIT>_NONE ; case FK_Data_1 : switch ( Modifier ) { default : llvm_unreachable ( <STR_LIT> ) ; case MCSymbolRefExpr :: VK_None : Type = ELF :: R_<ISA_LIT>_ABS8 ; break ; } break ; case FK_Data_2 : switch ( Modifier ) { default : llvm_unreachable ( <STR_LIT> ) ; case MCSymbolRefExpr :: VK_None : Type = ELF :: R_<ISA_LIT>_ABS16 ; break ; } break ; case FK_Data_4 : switch ( Modifier ) { default : llvm_unreachable ( <STR_LIT> ) ; case MCSymbolRefExpr :: VK_<ISA_LIT>_NONE : Type = ELF :: R_<ISA_LIT>_NONE ; break ; case MCSymbolRefExpr :: VK_GOT : Type = ELF :: R_<ISA_LIT>_GOT_BREL ; break ; case MCSymbolRefExpr :: VK_TLSGD : Type = ELF :: R_<ISA_LIT>_TLS_GD32 ; break ; case MCSymbolRefExpr :: VK_TPOFF : Type = ELF :: R_<ISA_LIT>_TLS_LE32 ; break ; case MCSymbolRefExpr :: VK_GOTTPOFF : Type = ELF :: R_<ISA_LIT>_TLS_IE32 ; break ; case MCSymbolRefExpr :: VK_None : Type = ELF :: R_<ISA_LIT>_ABS32 ; break ; case MCSymbolRefExpr :: VK_GOTOFF : Type = ELF :: R_<ISA_LIT>_GOTOFF32 ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_PREL : Type = ELF :: R_<ISA_LIT>_GOT_PREL ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_TARGET1 : Type = ELF :: R_<ISA_LIT>_TARGET1 ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_TARGET2 : Type = ELF :: R_<ISA_LIT>_TARGET2 ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_PREL31 : Type = ELF :: R_<ISA_LIT>_PREL31 ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_SBREL : Type = ELF :: R_<ISA_LIT>_SBREL32 ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_TLSLDO : Type = ELF :: R_<ISA_LIT>_TLS_LDO32 ; break ; case MCSymbolRefExpr :: VK_TLSCALL : Type = ELF :: R_<ISA_LIT>_TLS_CALL ; break ; case MCSymbolRefExpr :: VK_TLSDESC : Type = ELF :: R_<ISA_LIT>_TLS_GOTDESC ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_TLSDESCSEQ : Type = ELF :: R_<ISA_LIT>_TLS_DESCSEQ ; break ; } break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case


<s> EVT <ISA_LIT>TargetLowering :: getSetCCResultType ( const DataLayout & DL , LLVMContext & Context , EVT VT ) const { if ( ! VT . isVector


<s> BuildMI ( MBB , MI , DL , get ( AMDGPU :: S_ADD_U32 ) , RegLo ) . addReg ( RegLo ) . addTargetIndex ( AMDGPU :: TI_CONSTDATA_START ) . addReg ( AMDGPU :: SCC , RegState :: Define | RegState :: Implicit ) ; BuildMI ( MBB , MI , DL , get ( AMDGPU :: S_ADDC_U32 ) , RegHi ) . addReg ( RegHi ) . addImm ( <NUM_LIT> ) . addReg ( AMDGPU :: SCC , RegState :: Define | RegState :: Implicit ) . addReg ( AMDGPU :: SCC , RegState :: Implicit ) ; MI -> eraseFromParent ( ) ; break ; } case AMDGPU :: SGPR_USE : MI -> eraseFromParent ( ) ; break ; case AMDGPU :: V_MOV_B64_PSEUDO : { unsigned Dst = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned DstLo = RI . getSubReg ( Dst , AMDGPU :: sub0 ) ; unsigned DstHi = RI . getSubReg ( Dst , AMDGPU :: sub1 ) ; const MachineOperand & SrcOp = MI -> getOperand ( <NUM_LIT> ) ; assert ( ! SrcOp . isFPImm ( ) ) ; if ( SrcOp . isImm ( ) ) { APInt Imm ( <NUM_LIT> , SrcOp . getImm ( ) ) ; BuildMI ( MBB , MI , DL , get ( AMDGPU :: V_MOV_B32_e32 ) , DstLo ) . addImm ( Imm . getLoBits ( <NUM_LIT> ) . getZExtValue ( ) ) . addReg ( Dst , RegState :: Implicit ) ; BuildMI ( MBB , MI , DL , get ( AMDGPU :: V_MOV_B32_e32 ) , DstHi ) . addImm ( Imm . getHiBits ( <NUM_LIT> ) . getZExtValue ( ) ) . addReg ( Dst , RegState :: Implicit ) ; }


<s> if ( CPU == <STR_LIT> ) report_fatal_error ( Twine ( <STR_LIT> ) + ( Is64Bit ? <STR_LIT> : <STR_LIT> ) ) ; if ( TuneCPU . empty ( ) ) TuneCPU = CPU ; ParseSubtargetFeatures ( CPU , TuneCPU , FS ) ; if ( Is64Bit ) { XLenVT = <STR_LIT>


<s> return ( Subtarget . getFeatureBits ( ) & <STR_LIT> ) !=


<s> if ( recog_memoized ( succ ) == CODE_FOR_doloop_end_i && ( JUMP_P ( pred ) || CALL_P ( pred ) || GET_CODE ( PATTERN (

pred ) ) == SEQUENCE ) ) return <NUM_LIT> ;


<s> StringRef IVIdx = F -> getFnAttribute ( <STR_LIT> ) . getValueAsString ( ) ; MCSection * IV = OutStreamer -> getContext ( ) . getELFSection ( <STR_LIT> + IVIdx , ELF :: SHT_PROGBITS , ELF :: SHF_ALLOC | ELF


<s> SDLoc DL ( N ) ; switch ( IID ) { default : llvm_unreachable ( <STR_LIT> ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { if ( auto * CN = dyn_cast < ConstantSDNode > ( Comparator . getOperand ( <NUM_LIT> ) ) ) { int64_t ImmVal = CN -> getSExtValue ( ) ; if ( ImmVal >= - <NUM_LIT> && ImmVal <= <NUM_LIT> ) Imm = DAG . getConstant ( ImmVal , DL , <STR_LIT> ) ; else return SDValue ( ) ; } break ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { if ( auto * CN = dyn_cast < ConstantSDNode > ( Comparator . getOperand ( <NUM_LIT> ) ) ) { uint64_t ImmVal = CN -> getZExtValue ( ) ; if ( ImmVal <= <NUM_LIT> ) Imm = DAG . getConstant ( ImmVal , DL , <STR_LIT> ) ; else return SDValue ( ) ; } break ; } } SDValue Splat = DAG . getNode ( <STR_LIT> , DL , CmpVT , Imm ) ; SDValue ID = DAG . getTargetConstant ( ReplacementIID , DL , <STR_LIT> ) ; SDValue Op0 , Op1 ; if ( Invert ) { Op0 = Splat ; Op1 = N -> getOperand ( <NUM_LIT> ) ; } else { Op0 = N -> getOperand ( <NUM_LIT> ) ; Op1 = Splat ; } return DAG . getNode ( <STR_LIT> , DL , VT , ID


<s> const MachineOperand & MO = MI -> getOperand ( i ) ; if ( ! MO . isReg ( ) || ! MO . isDef ( ) ) continue ; unsigned R = MO . getReg ( ) ; if ( R == <STR_LIT> || R == <STR_LIT> || R == <STR_LIT> || R == <STR_LIT> ) return true ; } return


<s> DCI . CombineTo ( OrigOp . getNode ( ) , DAG . getNode ( Opcode , DL , VT , Op0 , Op1 , Op2 ) ) ; return true ; } ; unsigned Opcode = Op . getOpcode ( ) ; switch ( Opcode ) { case <STR_LIT> : { if ( EltVT . getSizeInBits ( ) != <NUM_LIT> && EltVT . getSizeInBits ( ) != <NUM_LIT> ) return false ; if ( VT . isInteger ( ) != Op . getSimpleValueType ( ) . isInteger ( ) ) return false ; return BitcastAndCombineShuffle ( Opcode , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; } case <STR_LIT>


<s> static DecodeStatus readInstruction32 ( const MemoryObject & region , uint64_t address , uint64_t & size , uint32_t & insn , bool isBigEndian ) { uint8_t Bytes [ <NUM_LIT> ] ; if ( region . readBytes ( address , <NUM_LIT> , ( uint8_t * ) Bytes , NULL ) == - <NUM_LIT> ) { size = <NUM_LIT> ; return MCDisassembler ::


<s> <ISA_LIT>CallFrameOptimization ( ) : MachineFunctionPass


<s> if ( ExitingBlocks . size ( ) > <NUM_LIT> ) return ; if ( ST -> hasBranchPredictor ( ) && L -> getNumBlocks ( ) > <NUM_LIT> ) return ; unsigned Cost = <NUM_LIT> ; for ( auto * BB : L -> getBlocks ( ) ) { for ( auto & I : * BB ) { if ( isa < CallInst > ( I ) || isa < InvokeInst > ( I ) ) { ImmutableCallSite CS ( & I ) ; if ( const Function * F = CS . getCalledFunction ( ) ) { if ( ! isLoweredToCall ( F ) ) continue ; } return ; } SmallVector < const Value * , <NUM_LIT> > Operands ( I . value_op_begin ( ) , I . value_op_end ( ) ) ; Cost += getUserCost ( & I , Operands ) ; } } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << Cost << <STR_LIT> ) ; UP . Partial = true ; UP . Runtime = true ; UP . UnrollRemainder = true ; UP . DefaultUnrollRuntimeCount = <NUM_LIT> ; UP . UnrollAndJam = true


<s> uint64_t MinOffset = - <NUM_LIT> ; for ( SDNode * N : GN -> uses ( ) ) { if ( N -> getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; auto * C = dyn_cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ; if ( ! C ) C = dyn_cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ; if ( ! C ) return SDValue ( ) ; MinOffset = std :: min ( MinOffset , C ->


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Commute = true ; LLVM_FALLTHROUGH ; case <STR_LIT> : { SDValue N0 = Op . getOperand ( <NUM_LIT> ) ; SDValue N1 = Op . getOperand ( <NUM_LIT> ) ; if ( ! Commute && MayFoldLoad ( N1 ) ) return false ; if ( MayFoldLoad ( N0 ) && ( ! isa < ConstantSDNode > ( N1 ) || MayFoldIntoStore ( Op ) ) ) return false ; if ( MayFoldLoad ( N1 ) && ( ! isa < ConstantSDNode > ( N0 ) || MayFoldIntoStore ( Op ) ) ) return false ; Promote =


<s> sym = XEXP ( XEXP ( sym , <NUM_LIT> ) , <NUM_LIT> ) ; } gcc_assert ( SPARC_SYMBOL_REF_TLS_P ( sym ) ) ; sym = legitimize_tls_address ( sym ) ; if ( addend ) { sym = gen_rtx_PLUS ( mode , sym , addend ) ; sym = force_operand ( sym , operands [ <NUM_LIT> ] ) ; } operands [ <NUM_LIT> ] = sym ; } if ( flag_pic && CONSTANT_P ( operands [ <NUM_LIT> ] ) ) { if ( pic_address_needs_scratch ( operands [ <NUM_LIT> ] ) ) operands [ <NUM_LIT> ] = legitimize_pic_address ( operands [ <NUM_LIT> ] , mode , <NUM_LIT> ) ; if ( GET_CODE ( operands [ <NUM_LIT> ] ) == LABEL_REF && mode == SImode ) { emit_insn ( gen_movsi_pic_label_ref ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ) ; return true ; } if ( GET_CODE ( operands [ <NUM_LIT> ] ) == LABEL_REF && mode == DImode ) { gcc_assert ( TARGET_ARCH64 ) ; emit_insn ( gen_movdi_pic_label_ref ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ) ; return true ; } if ( symbolic_operand ( operands [ <NUM_LIT> ] , mode ) ) { operands [ <NUM_LIT> ] = legitimize_pic_address ( operands [ <NUM_LIT> ] , mode , ( reload_in_progress ? operands [ <NUM_LIT> ] : NULL_RTX ) ) ; return false ; } } if ( CONSTANT_P ( operands [ <NUM_LIT> ] ) && REG_P ( operands [ <NUM_LIT> ] ) && ( SPARC_FP_REG_P ( REGNO ( operands [ <NUM_LIT> ] ) ) || SCALAR_FLOAT_MODE_P ( mode ) || VECTOR_MODE_P ( mode ) ) ) { if ( operands [ <NUM_LIT> ] == const0_rtx ) operands [ <NUM_LIT> ] = CONST0_RTX ( mode ) ; if ( ( TARGET_VIS || REGNO ( operands [ <NUM_LIT> ] ) < SPARC_FIRST_FP_REG ) && const_zero_operand ( operands [ <NUM_LIT> ] , mode ) ) return false ; if ( REGNO ( operands [ <NUM_LIT> ] ) < SPARC_FIRST_FP_REG && ( mode == SFmode || ( mode == DFmode && ( reload_completed || reload_in_progress ) ) ) ) return false ; operands [ <NUM_LIT> ] = force_const_mem ( mode , operands [ <NUM_LIT> ] ) ; if ( ! reload_in_progress ) operands [ <NUM_LIT> ] = validize_mem ( operands [ <NUM_LIT> ] ) ; return false ; } if ( ! CONSTANT_P ( operands [ <NUM_LIT> ] ) || GET_CODE ( operands [ <NUM_LIT> ] ) == HIGH || input_operand ( operands [ <NUM_LIT> ] , mode ) ) return false ; switch ( mode ) { case QImode : break ; case HImode : case


<s> case MachineOperand :: MO_Immediate : llvm_report_error ( <STR_LIT> ) ; return ; case MachineOperand :: MO_MachineBasicBlock : printBasicBlockLabel ( MO . getMBB ( ) ) ; return ; case MachineOperand :: MO_JumpTableIndex : O << TAI -> getPrivateGlobalPrefix ( ) << <STR_LIT> << getFunctionNumber ( ) << '_' << MO . getIndex ( ) ; return ; case MachineOperand :: MO_ConstantPoolIndex : O << TAI -> getPrivateGlobalPrefix ( ) << <STR_LIT> << getFunctionNumber ( ) << '_' << MO . getIndex ( ) ; return ; case MachineOperand :: MO_ExternalSymbol : if ( TM . getRelocationModel ( ) != Reloc :: Static ) { std :: string Name ( TAI -> getGlobalPrefix ( ) ) ; Name += MO . getSymbolName ( ) ; GVStubs . insert ( Name ) ; O << <STR_LIT> << Name << <STR_LIT> ; return ; } O << TAI -> getGlobalPrefix ( ) << MO . getSymbolName ( ) ; return ; case MachineOperand :: MO_GlobalAddress


<s> bool hasStdExtZksed ( ) const { return


<s> tryParseRegisterOperand ( SmallVectorImpl < MCParsedAsmOperand * > & Operands , bool is64BitReg ) { SMLoc S = Parser . getTok ( ) . getLoc ( ) ; int RegNo = - <NUM_LIT>


<s> Inst . addOperand ( MCOperand :: CreateImm ( getFPImm ( )


<s> } MachineInstr * NewMI = BuildMI ( MBB , InsPt , DL , TII -> get ( Opcode ) , Exec ) . addReg ( Exec ) . add ( MI . getOperand ( <NUM_LIT> ) ) ; LoweredEndCf . insert ( NewMI ) ; if ( LIS ) LIS -> ReplaceMachineInstrInMaps ( MI , * NewMI ) ; MI . eraseFromParent ( ) ; if ( LIS ) LIS -> handleMove ( * NewMI ) ; return


<s> assert ( MI . getOperand ( OpNo + <NUM_LIT> ) . isReg ( ) ) ; unsigned RegBits = getMachineOpValue ( MI , MI . getOperand ( OpNo + <NUM_LIT> ) , Fixups ) << <NUM_LIT> ; const MCOperand & MO = MI . getOperand ( OpNo ) ; if ( MO . isImm ( ) ) return ( ( getMachineOpValue ( MI , MO , Fixups ) >> <NUM_LIT> ) & <NUM_LIT> ) | RegBits ; Fixups . push_back ( MCFixup :: Create ( <NUM_LIT> , MO . getExpr ( ) , ( MCFixupKind )


<s> SDValue Arg = ShAmtOp . getOperand ( i ) ; if ( Arg . getOpcode ( ) == <STR_LIT> ) continue ; if ( Arg != BaseShAmt ) { return SDValue ( ) ; } } } else if ( ShAmtOp . getOpcode ( ) == <STR_LIT> && isSplatMask ( ShAmtOp . getOperand ( <NUM_LIT> ) . getNode ( ) ) ) { BaseShAmt = DAG . getNode ( <STR_LIT> , DL , EltVT , ShAmtOp , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; } else return SDValue ( ) ; if ( EltVT . bitsGT ( <STR_LIT> ) ) BaseShAmt = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , BaseShAmt ) ; else if ( EltVT . bitsLT ( <STR_LIT> ) ) BaseShAmt = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , BaseShAmt ) ; SDValue ValOp = N -> getOperand ( <NUM_LIT> ) ; switch ( N -> getOpcode ( ) ) { default : assert ( <NUM_LIT> && <STR_LIT> ) ; break ; case <STR_LIT> : if ( VT == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , DL , VT , DAG . getConstant ( <STR_LIT> , <STR_LIT> ) , ValOp , BaseShAmt ) ; if ( VT == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , DL , VT , DAG . getConstant ( <STR_LIT> , <STR_LIT> ) , ValOp , BaseShAmt ) ; if ( VT == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , DL , VT , DAG . getConstant ( <STR_LIT> , <STR_LIT> ) , ValOp , BaseShAmt ) ; break ; case


<s> IsGlobalInSmallSection ( const GlobalValue * GV , const TargetMachine & TM , SectionKind Kind


<s> void DecodePSHUFHWMask ( unsigned NumElts , unsigned Imm , SmallVectorImpl < int > & ShuffleMask ) { for ( unsigned l = <NUM_LIT> ; l != NumElts ;


<s> static rtx rx_function_value ( const_tree ret_type , const_tree fn_decl_or_type ATTRIBUTE_UNUSED , bool outgoing ATTRIBUTE_UNUSED ) { machine_mode mode = TYPE_MODE ( ret_type ) ; if ( GET_MODE_SIZE ( mode ) > <NUM_LIT> && GET_MODE_SIZE ( mode ) < <NUM_LIT> && ! COMPLEX_MODE_P ( mode ) && ! VECTOR_TYPE_P ( ret_type ) && !

VECTOR_MODE_P ( mode ) ) return gen_rtx_REG ( SImode , FUNC_RETURN_REGNUM ) ;


<s> SDValue <ISA_LIT>TargetLowering :: LowerFormalArguments ( SDValue Chain , CallingConv :: ID CallConv , bool IsVarArg , const SmallVectorImpl < <STR_LIT> > & Ins , const SDLoc & DL , SelectionDAG & DAG , SmallVectorImpl < SDValue > & InVals ) const { if ( ! CallingConvSupported ( CallConv ) ) fail ( DL , DAG , <STR_LIT> ) ; MachineFunction & MF = DAG . getMachineFunction ( ) ; auto * MFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; MF . getRegInfo ( ) . addLiveIn ( <STR_LIT> ) ; for ( const <STR_LIT> & In : Ins ) { if ( In . Flags . isInAlloca ( ) ) fail ( DL , DAG , <STR_LIT> ) ; if ( In . Flags . isNest ( ) ) fail ( DL , DAG , <STR_LIT> ) ; if ( In . Flags . isInConsecutiveRegs ( ) ) fail ( DL , DAG , <STR_LIT> ) ; if ( In . Flags . isInConsecutiveRegsLast ( ) ) fail ( DL


<s> MachineRegisterInfo & RegInfo = MBB . getParent ( ) -> getRegInfo ( ) ; unsigned Size = STI . isABI_N64 ( ) ? <NUM_LIT> : <NUM_LIT> ; unsigned LUi = STI . isABI_N64 ( ) ? <STR_LIT> : <STR_LIT> ; unsigned ZEROReg = STI . isABI_N64 ( ) ? <STR_LIT> : <STR_LIT> ; const TargetRegisterClass * RC = STI . isABI_N64 ( ) ? & <STR_LIT> : & <STR_LIT> ; bool LastInstrIsADDiu = NewImm ; const <ISA_LIT>AnalyzeImmediate :: InstSeq & Seq = AnalyzeImm . Analyze ( Imm , Size , LastInstrIsADDiu ) ; <ISA_LIT>AnalyzeImmediate :: InstSeq :: const_iterator Inst = Seq . begin ( ) ; assert ( Seq . size ( ) && ( ! LastInstrIsADDiu || ( Seq . size ( ) > <NUM_LIT> ) ) ) ; unsigned Reg = RegInfo . createVirtualRegister ( RC ) ; if ( Inst -> Opc == LUi ) BuildMI ( MBB , II , DL , get ( LUi ) , Reg ) . addImm ( SignExtend64 < <NUM_LIT> > ( Inst -> ImmOpnd ) ) ; else BuildMI ( MBB , II , DL , get ( Inst -> Opc ) , Reg ) . addReg ( ZEROReg ) . addImm ( SignExtend64 < <NUM_LIT> > ( Inst -> ImmOpnd ) ) ; for ( ++ Inst ; Inst != Seq . end ( ) - LastInstrIsADDiu ; ++ Inst ) BuildMI ( MBB , II , DL , get ( Inst -> Opc ) , Reg ) . addReg ( Reg , RegState :: Kill


<s> for ( SDNode :: use_iterator UI = InputVector . getNode ( ) -> use_begin ( ) , UE = InputVector . getNode ( ) -> use_end ( ) ; UI != UE ; ++ UI ) { if ( UI . getUse ( ) . getResNo ( ) != InputVector . getResNo ( ) ) return SDValue ( ) ; SDNode * Extract = * UI ; if ( Extract -> getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; if ( Extract -> getValueType ( <NUM_LIT> ) != <STR_LIT> ) return SDValue ( ) ; if ( ! Extract -> hasOneUse ( ) ) return SDValue ( ) ; if ( Extract -> use_begin ( ) -> getOpcode ( ) != <STR_LIT> && Extract -> use_begin ( ) -> getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; if ( ! isa < ConstantSDNode > ( Extract -> getOperand ( <NUM_LIT> ) ) ) return SDValue ( ) ; ExtractedElements |= <NUM_LIT> << Extract -> getConstantOperandVal ( <NUM_LIT> ) ; Uses . push_back ( Extract ) ; } if ( ExtractedElements != <NUM_LIT> ) return SDValue ( ) ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; SDValue Vals [ <NUM_LIT> ] ; if ( TLI . isOperationLegal ( <STR_LIT> , <STR_LIT> ) ) { SDValue Cst = DAG . getBitcast ( <STR_LIT> , InputVector ) ; auto & DL = DAG . getDataLayout ( ) ; EVT VecIdxTy = DAG . getTargetLoweringInfo ( ) . getVectorIdxTy ( DL ) ; SDValue BottomHalf = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Cst , DAG . getConstant ( <NUM_LIT> , dl , VecIdxTy ) ) ; SDValue TopHalf = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Cst , DAG . getConstant ( <NUM_LIT> , dl , VecIdxTy ) ) ; SDValue ShAmt = DAG . getConstant ( <NUM_LIT> , dl , DAG . getTargetLoweringInfo ( ) . getShiftAmountTy ( <STR_LIT> , DL ) ) ; Vals [ <NUM_LIT> ] = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , BottomHalf ) ; Vals [ <NUM_LIT> ] = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , BottomHalf , ShAmt ) ) ; Vals [ <NUM_LIT> ] = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , TopHalf ) ; Vals [ <NUM_LIT> ] = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , TopHalf , ShAmt ) ) ; } else { SDValue StackPtr = DAG . CreateStackTemporary ( SrcVT ) ; SDValue Ch = DAG . getStore ( DAG . getEntryNode ( ) , dl

, InputVector , StackPtr , MachinePointerInfo ( ) ) ;


<s> UP . UpperBound = true ; if ( ! ST -> isMClass ( ) ) return BasicTTIImplBase :: getUnrollingPreferences ( L , SE , UP ) ; UP . OptSizeThreshold = <NUM_LIT> ; UP . PartialOptSizeThreshold = <NUM_LIT> ; if ( L -> getHeader ( ) -> getParent ( ) -> hasOptSize ( ) ) return ; SmallVector < BasicBlock * , <NUM_LIT> > ExitingBlocks ; L -> getExitingBlocks ( ExitingBlocks ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << <STR_LIT> << L -> getNumBlocks ( ) << <STR_LIT> << <STR_LIT> << ExitingBlocks . size ( ) << <STR_LIT> ) ; if ( ExitingBlocks . size ( ) > <NUM_LIT> ) return ; if ( ST -> hasBranchPredictor ( ) && L -> getNumBlocks ( ) > <NUM_LIT> ) return ; if ( getBooleanLoopAttribute ( L , <STR_LIT> ) ) return ; InstructionCost Cost =


<s> int GCNHazardRecognizer :: checkGetRegHazards ( MachineInstr * GetRegInstr ) { const <ISA_LIT>InstrInfo * TII = ST . getInstrInfo ( ) ; unsigned GetRegHWReg = getHWReg ( TII , *


<s> int best = <NUM_LIT> ; int cost , best_cost = <NUM_LIT> ; int best_right = <NUM_LIT> , best_len = <NUM_LIT> ; int i ; int can_ext ; if ( left < <NUM_LIT> || left > <NUM_LIT> ) return <NUM_LIT> ; if ( CONST_INT_P ( mask_rtx ) ) mask = ( unsigned HOST_WIDE_INT ) INTVAL ( mask_rtx ) >> left ; else mask = ( unsigned HOST_WIDE_INT ) GET_MODE_MASK ( SImode ) >> left ; lsb = ( ( mask ^ ( mask - <NUM_LIT> ) ) >> <NUM_LIT> ) + <NUM_LIT> ; right = exact_log2 ( lsb ) ; mask2 = ~ ( mask + lsb - <NUM_LIT> ) ; lsb2 = ( ( mask2 ^ ( mask2 - <NUM_LIT> ) ) >> <NUM_LIT> ) + <NUM_LIT> ; if ( ! mask2 ) best_cost = ashl_lshr_seq [ right ] . insn_count + ashl_lshr_seq [ right + left ] . insn_count ; else if ( ! right && mask2 == ~ ( lsb2 - <NUM_LIT> ) ) { int late_right = exact_log2 ( lsb2 ) ; best_cost = ashl_lshr_seq [ left + late_right ] . insn_count + ashl_lshr_seq [ late_right ] . insn_count ; } if ( mask2 == ~ ( lsb2 - <NUM_LIT> ) ) { int width , first ; for ( width = <NUM_LIT> ; width <= <NUM_LIT> ; width += <NUM_LIT> ) { if ( lsb2 == ( unsigned HOST_WIDE_INT ) <NUM_LIT> << width ) { cost = <NUM_LIT> + ext_ashl_lshr_seq [ right ] . insn_count

+ ext_ashl_lshr_seq [ left + right ] . insn_count ;


<s> if ( AFI -> isThumbFunction ( ) && MFI -> hasVarSizedObjects ( ) ) { if ( AFI -> isThumb2Function ( ) && MFI -> getLocalFrameSize ( ) < <NUM_LIT> ) return false ; return true


<s> BTFTypeFunc :: BTFTypeFunc ( StringRef FuncName , uint32_t ProtoTypeId , uint32_t Scope )


<s> const MCExpr * Expr = nullptr ; if ( DispOp . isImm ( ) ) { if ( FixupKind != FK_PCRel_1 && FixupKind != FK_PCRel_2 && FixupKind != FK_PCRel_4 ) { EmitConstant ( DispOp . getImm ( ) + ImmOffset , Size , CurByte , OS ) ; return ; } Expr = MCConstantExpr :: create ( DispOp . getImm ( ) , Ctx ) ; } else { Expr = DispOp . getExpr ( ) ; } if ( ( FixupKind == FK_Data_4 || FixupKind == FK_Data_8 || FixupKind == MCFixupKind ( <STR_LIT> ) ) ) { GlobalOffsetTableExprKind Kind = StartsWithGlobalOffsetTable ( Expr ) ; if ( Kind != GOT_None ) { assert ( ImmOffset == <NUM_LIT> ) ; if ( Size == <NUM_LIT> ) { FixupKind = MCFixupKind ( <STR_LIT> ) ; } else { assert ( Size == <NUM_LIT> ) ; FixupKind = MCFixupKind ( <STR_LIT> ) ; } if ( Kind == GOT_Normal ) ImmOffset = CurByte ; } else if ( Expr -> getKind ( ) == MCExpr :: SymbolRef ) { if ( HasSecRelSymbolRef ( Expr ) ) { FixupKind = MCFixupKind ( FK_SecRel_4 ) ; } } else if ( Expr -> getKind ( ) ==


<s> unsigned int JmpOpcode ; resolveComparison ( MBB , MI , DL , ConditionCode , MI . getOperand ( <NUM_LIT> ) , MI . getOperand ( <NUM_LIT> ) , JmpOpcode , false ) ; BuildMI ( MBB , MI , DL , get ( JmpOpcode ) ) . add ( MI . getOperand ( <NUM_LIT> ) ) ; break ; } case <STR_LIT> : { auto ConditionCode = <STR_LIT> ( MI . getOperand ( <NUM_LIT> ) . getImm ( ) ) ; unsigned int JmpOpcode ; resolveComparison ( MBB , MI , DL , ConditionCode , MI . getOperand ( <NUM_LIT> ) , MI . getOperand ( <NUM_LIT> ) , JmpOpcode , true ) ; BuildMI ( MBB , MI , DL , get ( JmpOpcode ) ) . add ( MI . getOperand ( <NUM_LIT> ) ) ; break ; } case <STR_LIT> : { MachineOperand & dst = MI . getOperand ( <NUM_LIT> ) ; MachineOperand & src = MI . getOperand ( <NUM_LIT> ) ; MachineOperand & imm = MI . getOperand ( <NUM_LIT> ) ; assert ( imm . isImm ( ) && <STR_LIT>


<s> void <ISA_LIT>PassConfig :: addPreLegalizeMachineIR ( ) { bool IsOptNone = getOptLevel ( )


<s> TargetLoweringObjectFile :: Initialize ( ctx , TM ) ; TextSection = new <ISA_LIT>Section ( MCSection :: SV_ELF , SectionKind :: getText ( ) ) ; DataSection = new <ISA_LIT>Section ( MCSection :: SV_ELF , SectionKind :: getData ( ) ) ; BSSSection = new <ISA_LIT>Section ( MCSection :: SV_ELF , SectionKind :: getBSS ( ) ) ; ReadOnlySection = new <ISA_LIT>Section ( MCSection :: SV_ELF , SectionKind :: getReadOnly ( ) ) ; StaticCtorSection = new <ISA_LIT>Section ( MCSection :: SV_ELF , SectionKind :: getMetadata ( ) ) ; StaticDtorSection = new <ISA_LIT>Section ( MCSection :: SV_ELF , SectionKind :: getMetadata ( ) ) ; LSDASection = new <ISA_LIT>Section ( MCSection :: SV_ELF , SectionKind :: getMetadata ( ) ) ; EHFrameSection = new <ISA_LIT>Section ( MCSection :: SV_ELF , SectionKind :: getMetadata ( ) ) ; DwarfAbbrevSection = new <ISA_LIT>Section ( MCSection :: SV_ELF , SectionKind :: getMetadata ( ) ) ; DwarfInfoSection = new <ISA_LIT>Section ( MCSection :: SV_ELF , SectionKind :: getMetadata ( ) ) ; DwarfLineSection = new <ISA_LIT>Section ( MCSection :: SV_ELF , SectionKind :: getMetadata ( ) ) ; DwarfFrameSection = new <ISA_LIT>Section ( MCSection :: SV_ELF , SectionKind :: getMetadata ( ) ) ; DwarfPubTypesSection = new <ISA_LIT>Section ( MCSection :: SV_ELF , SectionKind :: getMetadata ( ) ) ; DwarfDebugInlineSection = new <ISA_LIT>Section ( MCSection :: SV_ELF , SectionKind :: getMetadata ( ) ) ; DwarfStrSection = new <ISA_LIT>Section ( MCSection :: SV_ELF , SectionKind ::


<s> case CONST_DOUBLE : * total = <NUM_LIT> ; return true ; case AND : * total = COSTS_N_INSNS ( mcore_and_cost ( x ) ) ; return true ; case IOR : * total = COSTS_N_INSNS ( mcore_ior_cost ( x ) ) ; return true


<s> if ( TargetRegisterInfo :: isPhysicalRegister ( Reg ) ) return MIB . addReg ( TRI -> getSubReg ( Reg , SubIdx ) , State ) ; return MIB . addReg ( Reg


<s> addPass ( create<ISA_LIT>OptimizeLiveIntervals ( ) ) ; addPass ( create<ISA_LIT>MemIntrinsicResults ( ) ) ; addPass ( create<ISA_LIT>RegStackify ( ) ) ; addPass ( create<ISA_LIT>RegColoring ( ) ) ; } addPass ( create<ISA_LIT>ExplicitLocals ( ) ) ; addPass ( create<ISA_LIT>CFGSort ( ) ) ; addPass ( create<ISA_LIT>CFGStackify ( ) ) ; addPass ( create<ISA_LIT>LowerBrUnless ( ) ) ; if ( getOptLevel ( ) != CodeGenOpt ::

None ) addPass ( create<ISA_LIT>Peephole ( ) ) ;


<s> bool hasZeroCycleZeroingFPWorkaround ( ) const { return HasZeroCycleZeroingFPWorkaround


<s> for ( unsigned i = <NUM_LIT> , ie = ( unsigned ) SU -> Preds . size ( ) ; i != ie ; ++ i ) { const MCInstrDesc * PredMCID = DAG -> getInstrDesc ( SU -> Preds [ i ] . getSUnit ( ) ) ; if ( ! PredMCID || PredMCID -> getSchedClass ( ) != <STR_LIT> :: IIC_SprMTSPR ) continue ; if ( SU -> Preds [ i ] . isCtrl ( ) ) continue ; for ( unsigned j = <NUM_LIT> , je = CurGroup . size ( ) ; j != je ; ++ j ) if ( SU -> Preds [ i ] . getSUnit ( ) ==


<s> bool NeedSplit = ( BMI != MI ) || ! BBHasFallthrough ( MBB ) ; if ( BMI != MI ) { if ( std :: next ( MachineBasicBlock :: iterator ( MI ) ) == std :: prev ( MBB -> getLastNonDebugInstr ( ) ) && BMI -> getOpcode ( ) == <STR_LIT> ) { MachineBasicBlock * NewDest = BMI -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; if ( isBlockInRange ( MI , NewDest , getBranchDisplacementBits ( MI -> getOpcode ( ) ) ) ) { DEBUG ( dbgs ( ) << <STR_LIT> << * BMI ) ; BMI -> getOperand ( <NUM_LIT> ) . setMBB ( DestBB ) ; unsigned OpNum = ( MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; MI -> getOperand ( OpNum ) . setMBB ( NewDest ) ; MI -> setDesc ( TII -> get ( getOppositeConditionOpcode ( MI -> getOpcode ( ) ) ) ) ; if ( MI -> getOpcode ( ) == <STR_LIT> ) invertBccCondition ( MI ) ; return true ; } } } if ( NeedSplit ) { MachineBasicBlock * TBB , * FBB ; SmallVector < MachineOperand , <NUM_LIT> > Cond


<s> SDValue Or = N ; if ( Or . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) { SDValue Srl = Or . getOperand ( <NUM_LIT> ) ; if ( isa < ConstantSDNode > ( Srl . getOperand ( <NUM_LIT> ) ) && isa < ConstantSDNode > ( Or . getOperand ( <NUM_LIT> ) ) ) { uint32_t VC1 = Or . getConstantOperandVal ( <NUM_LIT>


<s> const unsigned NumElts = VVT . getVectorNumElements ( ) ; MVT EltVT = VVT . getVectorElementType ( ) ; if ( VVT . is512BitVector ( ) ) { if ( Subtarget . hasAVX512 ( ) ) if ( EltVT == <STR_LIT> || EltVT == <STR_LIT> || EltVT == <STR_LIT> || EltVT == <STR_LIT> ) switch ( NumElts ) { case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; } if ( Subtarget . hasBWI ( ) ) if ( EltVT ==


<s> return Is64Bit && ( ! TargetTriple . isX32 ( ) && ! TargetTriple . isOSNaCl


<s> void \ fini_section ( ) \ { \ if ( ( ! TARGET_ELF ) && in_section != in_fini ) \ { \ fprintf ( asm_out_file , <STR_LIT> , FINI_SECTION_ASM_OP ) ;


<s> static MCInstPrinter * create<ISA_LIT>MCInstPrinter ( const Triple & T , unsigned SyntaxVariant , const MCAsmInfo & MAI , const MCInstrInfo


<s> if ( tryOptCompareBranchFedByICmp ( I , ICmp , MIB ) ) return true ; MachineBasicBlock * DestMBB = I . getOperand ( <NUM_LIT> ) . getMBB ( ) ; auto PredOp = ICmp . getOperand ( <NUM_LIT> ) ; emitIntegerCompare ( ICmp . getOperand ( <NUM_LIT> ) , ICmp . getOperand ( <NUM_LIT> ) , PredOp , MIB ) ; const <STR_LIT> CC = changeICMPPredTo<ISA_LIT>CC ( static_cast < CmpInst :: Predicate > ( PredOp . getPredicate ( ) ) ) ; MIB . buildInstr ( <STR_LIT> , { } , { } )


<s> if ( Val == <NUM_LIT> ) imm = INT32_MIN ; else if ( ! ( Val & <NUM_LIT> )


<s> __asm__ ( <STR_LIT> : <STR_LIT> ( res ) :


<s> if ( ( is2Addr && Entry . PredCC2 == <NUM_LIT> ) || ( ! is2Addr && Entry . PredCC1 == <NUM_LIT> ) ) { if ( Pred == <STR_LIT> ) { if ( ! HasCC ) { if ( ! LiveCPSR ) { HasCC = true ; CCDead = true ; return true ; } return false ; } } else { if ( HasCC


<s> return PO + UnknownPadding ( LogAlign


<s> void ApplyFixup ( const MCFixup & Fixup , char * Data , unsigned DataSize , uint64_t


<s> return ( __m128d ) __builtin_ia32_loadsd_mask ( __P ,


<s> unsigned getLocalMemorySize ( ) const


<s> bool has65C02 ( ) const { return Has65C02Insns


<s> Op -> Mem . Base = <NUM_LIT> ; Op -> Mem . IndexReg = <NUM_LIT> ; Op -> Mem . Index = nullptr ; Op -> Mem . Offset = Imm ; return


<s> SrcMBB = * SrcMBB -> succ_begin ( ) ; if ( SrcMBB == DstMBB ) return SinglePath_InPath ; if ( ! AllowSideEntry && SrcMBB -> pred_size ( ) > <NUM_LIT> )


<s> rounded = vec_rint ( __A ) ; temp = vec_cts ( rounded , <NUM_LIT> ) ; result = ( __vector unsigned long long ) vec_pack ( temp , temp ) ; return ( __m64 ) ( ( __vector long long ) result ) [


<s> if ( getTargetMachine ( ) . getRelocationModel ( ) != Reloc :: PIC_ && ! IsN64 ) return getAddrNonPIC ( Op


<s> if ( <ISA_LIT>ScalarSSEf64 && I -> getType ( ) -> isDoubleTy ( ) ) { const Value * V = I -> getOperand ( <NUM_LIT> ) ; if ( V -> getType ( ) -> isFloatTy ( ) ) { unsigned OpReg = getRegForValue ( V ) ; if ( OpReg == <NUM_LIT> ) return false ; unsigned ResultReg = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( <STR_LIT> ) , ResultReg ) . addReg ( OpReg ) ; UpdateValueMap ( I , ResultReg ) ; return true


<s> if ( Reg == <STR_LIT> ) return <NUM_LIT> ; if ( Reg . isVirtual ( ) ) { auto * Def = MRI . getUniqueVRegDef ( Reg ) ; switch ( Def -> getOpcode ( ) ) { default : return None ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> for ( SDValue Elt : Op -> ops ( ) ) { SDValue LHS = Elt . getOperand ( <NUM_LIT> ) ; SDValue RHS = Elt . getOperand ( <NUM_LIT> ) ; if ( ! isa < ConstantSDNode > ( RHS ) ) return SDValue ( ) ; LHSElts . push_back ( LHS ) ; RHSElts . push_back ( RHS ) ; } SDValue LHS = DAG . getBuildVector ( VT , DL , LHSElts ) ; SDValue RHS = DAG . getBuildVector ( VT , DL , RHSElts ) ; return DAG . getNode ( Opcode , DL


<s> bool <ISA_LIT>RegisterInfo :: hasBasePointer ( const MachineFunction & MF ) const { return false


<s> ~ <ISA_LIT>ResourceModel ( ) { delete ResourcesModel


<s> const TargetRegisterClass * RC ; switch ( VT . getSimpleVT ( ) . SimpleTy ) { default : return false ; case <STR_LIT> : case <STR_LIT> : if ( isThumb2 ) { if ( Addr . Offset < <NUM_LIT> && Addr . Offset > - <NUM_LIT> && Subtarget -> hasV6T2Ops ( ) ) Opc = isZExt ? <STR_LIT> : <STR_LIT> ; else Opc = isZExt ? <STR_LIT> : <STR_LIT> ; } else { if ( isZExt ) { Opc = <STR_LIT> ; } else { Opc = <STR_LIT> ; useAM3 = true ; } } RC = & <STR_LIT> ; break ; case <STR_LIT> : if ( Alignment && Alignment < <NUM_LIT> && ! Subtarget -> allowsUnalignedMem ( ) ) return false ; if ( isThumb2 ) { if ( Addr . Offset < <NUM_LIT> && Addr . Offset > - <NUM_LIT> && Subtarget -> hasV6T2Ops ( ) ) Opc = isZExt ? <STR_LIT> : <STR_LIT> ; else Opc = isZExt ? <STR_LIT> : <STR_LIT> ; } else { Opc = isZExt ? <STR_LIT> : <STR_LIT> ; useAM3 = true ; } RC = & <STR_LIT> ; break ; case <STR_LIT> : if ( Alignment && Alignment < <NUM_LIT> && ! Subtarget -> allowsUnalignedMem ( ) ) return false ; if ( isThumb2 ) { if ( Addr . Offset < <NUM_LIT> && Addr . Offset > - <NUM_LIT> && Subtarget -> hasV6T2Ops ( ) ) Opc = <STR_LIT> ; else Opc


<s> for ( ; ; ) { const MCExpr * Value ; if ( getParser ( ) . ParseExpression ( Value ) ) return true ; getParser ( ) . getStreamer ( ) . EmitValue ( Value , Size , <NUM_LIT> ) ; if ( getLexer ( ) . is ( AsmToken :: EndOfStatement ) ) break ; if ( getLexer ( ) . isNot ( AsmToken :: Comma


<s> static const char * isa_str ( const struct loongarch_isa * isa , char separator ) { APPEND_STRING ( loongarch_isa_base_strings [ isa -> base ] ) APPEND1 ( separator ) if ( isa -> fpu == ISA_EXT_NOFPU ) { APPEND_STRING ( <STR_LIT> OPTSTR_ISA_EXT_FPU ) } else { APPEND_STRING ( OPTSTR_ISA_EXT_FPU ) APPEND_STRING ( loongarch_isa_ext_strings [ isa


<s> input = gen_rtx_REG ( vecmode , REGNO ( input ) ) ; emit_move_insn ( value , CONST0_RTX ( vecmode ) ) ; if ( vecmode == V4SFmode ) emit_insn ( gen_sse_movss ( value , value , input ) ) ; else emit_insn ( gen_sse2_movsd ( value , value , input ) ) ; } emit_move_insn ( large , two31 ) ; emit_move_insn ( zero_or_two31 , MEM_P ( two31 ) ? large : two31 ) ; x = gen_rtx_fmt_ee ( LE , vecmode , large , value ) ; emit_insn ( gen_rtx_SET ( large , x ) ) ; x = gen_rtx_AND ( vecmode , zero_or_two31 , large ) ; emit_insn ( gen_rtx_SET ( zero_or_two31


<s> int64_t Val = ~ MCE -> getValue ( ) & <NUM_LIT> ; return <STR_LIT> ( Val ,


<s> SDValue Offset = DAG . getConstant ( TD -> getPointerSize ( ) , Subtarget -> is64Bit ( ) ? <STR_LIT> : <STR_LIT> ) ; return DAG . getLoad ( getPointerTy ( ) , dl , DAG . getEntryNode ( ) , DAG . getNode ( <STR_LIT> , dl , getPointerTy ( ) , FrameAddr , Offset ) , MachinePointerInfo ( ) , false , false , false , <NUM_LIT> ) ; } SDValue RetAddrFI = getReturnAddressFrameIndex ( DAG ) ; return DAG . getLoad ( getPointerTy ( ) , dl , DAG . getEntryNode ( ) , RetAddrFI ,


<s> bool isImm7 ( ) const { return isImmediate < - <NUM_LIT> , <NUM_LIT> > (


<s> bool isSImm12Lsb0 ( ) const { return isBareSimmNLsb0 < <NUM_LIT> > (


<s> return { ObjectOffset + ( int ) MFI . getStackSize ( )


<s> OutStreamer -> emitInt32 ( R_00B860_COMPUTE_TMPRING_<ISA_LIT>ZE ) ; OutStreamer -> emitInt32 ( S_00B860_WAVE<ISA_LIT>ZE ( CurrentProgramInfo . ScratchBlocks ) ) ; } else { OutStreamer -> emitInt32 ( RsrcReg ) ; OutStreamer -> emitIntValue ( S_00B028_VGPRS ( CurrentProgramInfo . VGPRBlocks ) | S_00B028_SGPRS ( CurrentProgramInfo . SGPRBlocks ) , <NUM_LIT> ) ; OutStreamer -> emitInt32 ( R_0286E8_SPI_TMPRING_<ISA_LIT>ZE ) ; OutStreamer -> emitIntValue ( S_0286E8_WAVE<ISA_LIT>ZE ( CurrentProgramInfo . ScratchBlocks ) , <NUM_LIT> ) ; } if ( MF . getFunction ( ) . getCallingConv ( ) == CallingConv :: <ISA_LIT>_PS ) { OutStreamer -> emitInt32 ( R_00B02C_SPI_SHADER_PGM_RSRC2_PS ) ; OutStreamer -> emitInt32 ( S_00B02C_EXTRA_LDS_<ISA_LIT>ZE ( CurrentProgramInfo . LDSBlocks


<s> MCObjectWriter * createObjectWriter ( raw_pwrite_stream &


<s> Type * StructType = PType -> getElementType ( ) ; unsigned AS = Func -> getParent ( ) -> getDataLayout ( ) . getAllocaAddrSpace ( ) ; AllocaInst * AllocA = new AllocaInst ( StructType , AS , Arg -> getName ( ) , FirstInst ) ; AllocA -> setAlignment ( Func -> getParamAlignment ( Arg -> getArgNo ( ) ) ) ; Arg -> replaceAllUsesWith ( AllocA ) ; Value * ArgInParam = new AddrSpaceCastInst ( Arg , PointerType :: get ( StructType , ADDRESS_SPACE_PARAM ) ,


<s> Out . EmitInstruction ( Inst , * STI


<s> static DecodeStatus decodeUImmOperand ( MCInst & Inst , uint64_t Imm , int64_t Address , const MCDisassembler * Decoder ) { assert ( isUInt < N > ( Imm ) && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: createImm (