<s> MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const unsigned SlotSize = TM . getRegisterInfo ( ) -> getSlotSize ( ) ; const bool Is64Bit = STI . is64Bit ( ) ; DebugLoc DL ; const unsigned HipeLeafWords = <NUM_LIT> ; const unsigned CCRegisteredArgs = Is64Bit ? <NUM_LIT> : <NUM_LIT> ; const unsigned Guaranteed = HipeLeafWords * SlotSize ; unsigned CallerStkArity = MF . getFunction ( ) -> arg_size ( ) > CCRegisteredArgs ? MF . getFunction ( ) -> arg_size ( ) - CCRegisteredArgs : <NUM_LIT> ; unsigned MaxStack = MFI -> getStackSize ( ) + CallerStkArity * SlotSize + SlotSize ; assert ( STI . isTargetLinux ( ) && <STR_LIT> ) ; if ( MFI -> hasCalls ( ) ) { unsigned MoreStackForCalls = <NUM_LIT> ; for ( MachineFunction :: iterator MBBI = MF . begin ( ) , MBBE = MF . end ( ) ; MBBI != MBBE ; ++ MBBI ) for ( MachineBasicBlock :: iterator MI = MBBI -> begin ( ) , ME = MBBI -> end ( ) ; MI != ME ; ++ MI ) { if ( ! MI -> isCall ( ) ) continue ; const MachineOperand & MO = MI -> getOperand ( <NUM_LIT> ) ; if ( ! MO . isGlobal ( ) ) continue ; const Function * F = dyn_cast < Function > ( MO . getGlobal ( ) ) ; if ( ! F ) continue ; if ( F -> getName ( ) . find ( <STR_LIT> ) != StringRef :: npos || F -> getName ( ) . find ( <STR_LIT> ) != StringRef :: npos || F -> getName ( ) . find_first_of ( <STR_LIT> ) == StringRef :: npos ) continue ; unsigned CalleeStkArity = F -> arg_size ( ) > CCRegisteredArgs ? F -> arg_size ( ) - CCRegisteredArgs : <NUM_LIT> ; if ( HipeLeafWords - <NUM_LIT> > CalleeStkArity ) MoreStackForCalls = std :: max ( MoreStackForCalls , ( HipeLeafWords - <NUM_LIT> - CalleeStkArity ) * SlotSize ) ; } MaxStack += MoreStackForCalls ; } if ( MaxStack > Guaranteed ) { MachineBasicBlock & prologueMBB = MF . front ( ) ; MachineBasicBlock * stackCheckMBB = MF . CreateMachineBasicBlock ( ) ; MachineBasicBlock * incStackMBB = MF . CreateMachineBasicBlock ( ) ; for ( MachineBasicBlock :: livein_iterator I = prologueMBB . livein_begin ( ) , E = prologueMBB . livein_end ( ) ; I != E ; I ++ ) { stackCheckMBB -> addLiveIn ( * I ) ; incStackMBB -> addLiveIn ( *


<s> bool <ISA_LIT>DAGToDAGISel :: SelectAddrRRI12 ( SDValue Op , SDValue Addr , SDValue & Base , SDValue & Disp , SDValue & Index ) { <ISA_LIT>RRIAddressMode AM20 , AM12 ; bool Done = false ; if ( ! Addr . hasOneUse ( ) ) { unsigned Opcode = Addr . getOpcode ( ) ; if ( Opcode != <STR_LIT> && Opcode != <STR_LIT> ) { for ( SDNode :: use_iterator UI = Addr . getNode ( ) -> use_begin ( ) , UE = Addr . getNode ( ) -> use_end ( ) ; UI != UE ; ++ UI ) { if ( UI -> getOpcode ( ) == <STR_LIT> ) { MatchAddressBase ( Addr , AM12 ) ; Done = true ; break ; } } } } if ( ! Done && MatchAddress ( Addr , AM12 , true ) ) return false ; if ( ! Done && ! MatchAddress ( Addr , AM20 , false ) ) if ( AM12 . Disp == <NUM_LIT> && AM20 . Disp != <NUM_LIT> ) return false ; DOUT ( llvm :: dbgs ( ) << <STR_LIT> ; DEBUG ( AM12 . dump ( ) ) ; EVT VT = Addr . getValueType (


<s> int result = findInRangeCPEntry ( U , UserOffset ) ; if ( result == <NUM_LIT> ) return false ; else if ( result == <NUM_LIT> ) return true ; MachineBasicBlock * NewIsland = MF -> CreateMachineBasicBlock ( ) ; MachineBasicBlock * NewMBB ; water_iterator IP ; if ( findAvailableWater ( U , UserOffset , IP ) ) { DEBUG ( dbgs ( ) << <STR_LIT> ) ; MachineBasicBlock * WaterBB = * IP ; if ( NewWaterList . erase ( WaterBB ) ) NewWaterList . insert ( NewIsland ) ; NewMBB = & * ++ WaterBB -> getIterator ( ) ; } else { if ( ! NoLoadRelaxation ) { result = findLongFormInRangeCPEntry ( U , UserOffset ) ; if ( result != <NUM_LIT> ) return true ; } DEBUG ( dbgs ( ) << <STR_LIT> ) ; createNewWater ( CPUserIndex , UserOffset , NewMBB ) ; MachineBasicBlock * WaterBB = & * -- NewMBB -> getIterator ( ) ; IP = find ( WaterList , WaterBB ) ; if ( IP != WaterList . end ( ) ) NewWaterList . erase ( WaterBB ) ; NewWaterList . insert ( NewIsland ) ; } if ( IP != WaterList . end ( ) ) WaterList . erase ( IP ) ; MF -> insert ( NewMBB -> getIterator ( ) , NewIsland ) ; updateForInsertedWaterBlock ( NewIsland ) ; decrementCPEReferenceCount ( CPI , CPEMI ) ; unsigned ID = createPICLabelUId ( ) ; U . HighWaterMark = NewIsland ; U . CPEMI = BuildMI ( NewIsland , DebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addImm ( ID ) . addConstantPoolIndex ( CPI ) . addImm ( Size ) ; CPEntries [ CPI ] . push_back ( CPEntry ( U . CPEMI ,


<s> bool needsTwoConstNR ( ) const { return NeedsTwoConstNR


<s> SDValue Ops [ ] = { M -> getOperand ( <NUM_LIT> ) , M -> getOperand ( <NUM_LIT> ) , M -> getOperand ( <NUM_LIT> ) } ; return DAG . getMemIntrinsicNode ( Opc , SDLoc ( Op ) , M -> getVTList ( ) , Ops , M -> getMemoryVT ( ) , M -> getMemOperand ( ) ) ; } case <STR_LIT> : case <STR_LIT> : { SDValue Ops [ ] = { Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) } ; MachineFunction & MF = DAG . getMachineFunction ( ) ; <ISA_LIT>MachineFunctionInfo * MFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; unsigned Opc = ( IntrID == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; EVT VT = Op . getValueType ( ) ; EVT IntVT = VT . changeTypeToInteger ( ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo ( MFI -> getBufferPSV ( ) ) , MachineMemOperand :: MOLoad , VT . getStoreSize ( ) , VT . getStoreSize ( ) ) ; return DAG . getMemIntrinsicNode ( Opc , DL , Op -> getVTList ( ) , Ops , IntVT , MMO ) ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { const ConstantSDNode * DMask = dyn_cast < ConstantSDNode > ( Op . getOperand (


<s> O << <STR_LIT> ; printLeaMemReference ( MI


<s> static int microblaze_adjust_cost ( rtx_insn * , int dep_type , rtx_insn * ,


<s> static const char * rs6000_xcoff_strip_name_encoding ( const char * name ) { size_t len ; if ( * name ==


<s> rval = gen_reg_rtx ( SImode ) ; oldval = convert_modes ( SImode , mode , oldval , true ) ; case SImode : if ( ! arm_add_operand ( oldval , SImode ) ) oldval = force_reg ( SImode , oldval ) ; break ; case DImode : if ( ! cmpdi_operand ( oldval , mode ) ) oldval = force_reg ( mode , oldval ) ; break ; default : gcc_unreachable ( ) ; } switch ( mode ) { case QImode : gen = gen_atomic_compare_and_swapqi_1 ; break ; case HImode : gen = gen_atomic_compare_and_swaphi_1 ; break ; case SImode : gen = gen_atomic_compare_and_swapsi_1 ; break ; case DImode : gen = gen_atomic_compare_and_swapdi_1 ; break ; default : gcc_unreachable ( ) ; } emit_insn ( gen ( rval , mem , oldval , newval , is_weak ,


<s> Reg = State . AllocateReg ( IntRegs , IntRegsSize ) ; if ( Reg == <STR_LIT> || Reg == <STR_LIT> ) Reg = State . AllocateReg ( IntRegs , IntRegsSize ) ; State . AllocateReg ( IntRegs , IntRegsSize ) ; LocVT = <STR_LIT> ; } else if ( ValVT . isFloatingPoint ( ) && ! AllocateFloatsInIntReg ) { if ( ValVT == <STR_LIT> ) { Reg = State . AllocateReg ( F32Regs , FloatRegsSize ) ; State . AllocateReg ( IntRegs , IntRegsSize ) ; } else { Reg = State . AllocateReg ( F64Regs , FloatRegsSize ) ; unsigned Reg2 = State . AllocateReg ( IntRegs , IntRegsSize ) ; if ( Reg2 == <STR_LIT> || Reg2 == <STR_LIT> ) State . AllocateReg ( IntRegs , IntRegsSize ) ; State . AllocateReg ( IntRegs , IntRegsSize ) ; } } else llvm_unreachable ( <STR_LIT> ) ; unsigned SizeInBytes = ValVT . getSizeInBits ( ) >> <NUM_LIT> ; unsigned Offset = State . AllocateStack ( SizeInBytes , OrigAlign ) ; if ( ! Reg ) State . addLoc ( CCValAssign :: getMem

( ValNo , ValVT , Offset , LocVT , LocInfo ) ) ;


<s> static bool isMMIO_ST ( SUnit * SU ) { assert ( SU -> getInstr ( ) && <STR_LIT> ) ; const MCInstrDesc & MC = SU -> getInstr ( ) -> getDesc ( ) ; if ( ! <ISA_LIT>II :: isStoreInst ( MC ) || ( <ISA_LIT>II :: getSlotOpCode ( MC ) !=


<s> if ( ( MEM_P ( x ) || ( ( GET_CODE ( x ) == SUBREG || REG_P ( x ) ) && ( true_regnum ( x ) == - <NUM_LIT> || true_regnum ( x ) >= FIRST_PSEUDO_REGISTER ) ) ) && ! reg_class_subset_p ( rclass , EIGHT_REGS ) ) return EIGHT_REGS ; return NO_REGS


<s> return std :: make_tuple ( ImplicitBufferPtr ? & ImplicitBufferPtr : nullptr , & <STR_LIT> , LLT :: pointer ( <ISA_LIT>AS :: CONSTANT_ADDRESS , <NUM_LIT> ) ) ; case <STR_LIT> : return std :: make_tuple ( WorkGroupIDX ? & WorkGroupIDX : nullptr , & <STR_LIT> , LLT :: scalar ( <NUM_LIT> ) ) ; case <STR_LIT> : return std :: make_tuple ( WorkGroupIDY ? & WorkGroupIDY : nullptr , & <STR_LIT> , LLT :: scalar ( <NUM_LIT> ) ) ; case <STR_LIT> : return std :: make_tuple ( WorkGroupIDZ ? & WorkGroupIDZ : nullptr , & <STR_LIT> , LLT :: scalar ( <NUM_LIT> ) ) ; case <STR_LIT> : return std :: make_tuple ( PrivateSegmentWaveByteOffset ? & PrivateSegmentWaveByteOffset : nullptr , & <STR_LIT> , LLT :: scalar ( <NUM_LIT> ) ) ; case <STR_LIT> : return std :: make_tuple ( KernargSegmentPtr ? & KernargSegmentPtr : nullptr , & <STR_LIT> , LLT :: pointer ( <ISA_LIT>AS :: CONSTANT_ADDRESS , <NUM_LIT> ) ) ; case <STR_LIT> : return std :: make_tuple ( ImplicitArgPtr ? & ImplicitArgPtr : nullptr , & <STR_LIT> , LLT :: pointer ( <ISA_LIT>AS :: CONSTANT_ADDRESS , <NUM_LIT> ) ) ; case <STR_LIT> : return std :: make_tuple ( DispatchID ? & DispatchID : nullptr , & <STR_LIT> , LLT :: scalar ( <NUM_LIT> ) ) ; case <STR_LIT> : return std :: make_tuple ( FlatScratchInit ? & FlatScratchInit : nullptr , & <STR_LIT> , LLT :: scalar ( <NUM_LIT> ) ) ; case <STR_LIT> : return std :: make_tuple ( DispatchPtr ? & DispatchPtr : nullptr , & <STR_LIT> , LLT :: pointer ( <ISA_LIT>AS :: CONSTANT_ADDRESS , <NUM_LIT> ) ) ; case <STR_LIT>


<s> if ( RegNo > <NUM_LIT> ) return MCDisassembler :: Fail ; unsigned Register = QQQQPRDecoderTable [ RegNo ] ; Inst . addOperand ( MCOperand :: createReg


<s> bool useMemOps ( ) const { return UseMemOps


<s> if ( UseMI . isInlineAsm ( ) ) { return getDefOperandLatency ( ItinData , DefMI , DefIdx ) ; } return TargetInstrInfo :: getOperandLatency ( ItinData , DefMI , DefIdx


<s> } aarch64_emit_store_exclusive ( mode , scratch , mem , newval , model_rtx ) ; if ( ! is_weak ) { if ( aarch64_track_speculation ) { rtx cc_reg = aarch64_gen_compare_reg ( NE , scratch , const0_rtx ) ; x = gen_rtx_NE ( GET_MODE ( cc_reg ) , cc_reg , const0_rtx ) ; } else x = gen_rtx_NE ( VOIDmode , scratch , const0_rtx ) ; x = gen_rtx_IF_THEN_ELSE ( VOIDmode , x , gen_rtx_LABEL_REF ( Pmode , label1 ) , pc_rtx ) ; aarch64_emit_unlikely_jump ( gen_rtx_SET ( pc_rtx , x ) ) ; } else { cond = gen_rtx_REG ( CCmode , CC_REGNUM ) ; x = gen_rtx_COMPARE ( CCmode , scratch , const0_rtx ) ; emit_insn ( gen_rtx_SET ( cond , x ) ) ; } emit_label ( label2 ) ; if ( strong_zero_p ) { cond = gen_rtx_REG ( CCmode , CC_REGNUM ) ; x = gen_rtx_COMPARE ( CCmode , rval , const0_rtx ) ; emit_insn ( gen_rtx_SET ( cond ,


<s> BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , KillFlag ) . addMemOperand ( MMO ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , KillFlag ) . addMemOperand ( MMO ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , KillFlag ) . addMemOperand ( MMO ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { unsigned Opc = Align < <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; BuildMI ( MBB , I , DL , get ( Opc ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , KillFlag ) . addMemOperand ( MMO ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { unsigned Opc = Align < <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; BuildMI ( MBB , I , DL , get ( Opc ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , KillFlag ) . addMemOperand ( MMO ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { unsigned Opc = Align < <NUM_LIT>


<s> static MCDisassembler * create<ISA_LIT>Disassembler ( const Target & T , const MCSubtargetInfo & STI , MCContext & Ctx ) { return new <ISA_LIT>Disassembler ( STI , Ctx ,


<s> MachineFunction * MF = BB -> getParent ( ) ; auto * FuncInfo = MF -> getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; FuncInfo -> addAllocaAdjustInst ( & MI


<s> uint32_t <ISA_LIT>MCCodeEmitter :: get<ISA_LIT>BLTargetOpValue ( const MCInst & MI , unsigned OpIdx , SmallVectorImpl < MCFixup > & Fixups ) const { const MCOperand MO = MI . getOperand ( OpIdx ) ; if ( MO . isExpr ( ) ) { if ( HasConditionalBranch ( MI ) ) return :: getBranchTargetOpValue ( MI , OpIdx , <STR_LIT> , Fixups ) ; return :: getBranchTargetOpValue ( MI , OpIdx , <STR_LIT> , Fixups ) ; } return MO . getImm (


<s> void <ISA_LIT>MCInstLower :: Initialize ( Mangler * M ,


<s> MCSubtargetInfo & NewSTI = OutStreamer -> getContext ( ) . getSubtargetCopy ( * TM . getMCSubtargetInfo ( ) ) ; NewSTI . setFeatureBits ( MF . getSubtarget ( ) . getFeatureBits ( ) ) ; MCSTI = & NewSTI ; STI = & MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; SetupMachineFunction ( MF ) ; emitFunctionBody ( ) ; return false


<s> bool ix86_function_ms_hook_prologue ( const_tree fn ) { if ( fn && lookup_attribute ( <STR_LIT> , DECL_ATTRIBUTES ( fn ) ) ) { if ( decl_function_context ( fn ) != NULL_TREE ) error_at ( DECL_SOURCE_LOCATION ( fn ) , <STR_LIT> <STR_LIT> ) ; else return true ; } return false


<s> enum attr_iscompact iscompact ; struct machine_function * machine ; if ( check_attr > <NUM_LIT> ) { iscompact = get_attr_iscompact ( insn ) ; if ( iscompact == ISCOMPACT_FALSE


<s> static DecodeStatus DecodeT2ShifterImmOperand ( MCInst & Inst , uint32_t Val ,

uint64_t Address , const MCDisassembler * Decoder ) {


<s> if ( INTVAL ( locality ) <= <NUM_LIT> ) return GEN_INT ( INTVAL ( write ) + <NUM_LIT> ) ; if ( INTVAL ( locality ) <= <NUM_LIT> ) return


<s> Value * <ISA_LIT>IREmitter :: visitTESTNM ( const SDNode


<s> const MCExpr * Val ; if ( ! isParsingInlineAsm ( ) ) { if ( getParser ( ) . parsePrimaryExpr ( Val , End ) ) { return Error ( Tok . getLoc ( ) , <STR_LIT> ) ; } else if ( SM . onIdentifierExpr ( Val , Identifier , Info , false , ErrMsg ) ) { return Error ( IdentLoc , ErrMsg ) ; } else break ; } if ( unsigned OpKind = IdentifyIntelInlineAsmOperator ( Identifier ) ) { if ( OpKind == IOK_OFFSET ) return Error ( IdentLoc , <STR_LIT> <STR_LIT> ) ; if ( int64_t Val = ParseIntelInlineAsmOperator ( OpKind ) ) { if ( SM . onInteger ( Val , ErrMsg ) ) return Error ( IdentLoc , ErrMsg ) ; } else return true ; break ; } if ( Identifier . count ( '.' ) && PrevTK == AsmToken :: RBrac ) { if ( ParseIntelDotOperator ( SM , End ) ) return true ; break ; } if ( ParseIntelInlineAsmIdentifier ( Val , Identifier , Info , false , End ) ) return true ; else if ( SM . onIdentifierExpr ( Val , Identifier , Info , true , ErrMsg ) ) return Error ( IdentLoc , ErrMsg ) ; break ; } case AsmToken :: Integer : { SMLoc Loc = getTok ( ) . getLoc ( ) ; int64_t IntVal = getTok ( ) . getIntVal ( ) ; End = consumeToken ( ) ; UpdateLocLex = false ; if ( getLexer ( ) . getKind ( ) == AsmToken :: Identifier ) { StringRef IDVal = getTok ( ) . getString ( ) ; if ( IDVal == <STR_LIT> || IDVal == <STR_LIT> ) { MCSymbol * Sym = getContext ( ) . getDirectionalLocalSymbol ( IntVal , IDVal == <STR_LIT> ) ; MCSymbolRefExpr :: VariantKind Variant = MCSymbolRefExpr :: VK_None ; const MCExpr * Val = MCSymbolRefExpr :: create ( Sym , Variant , getContext ( ) ) ; if ( IDVal == <STR_LIT> && Sym -> isUndefined ( ) ) return Error ( Loc , <STR_LIT> ) ; StringRef Identifier = Sym -> getName ( ) ; InlineAsmIdentifierInfo Info ; if ( SM . onIdentifierExpr ( Val , Identifier , Info , isParsingInlineAsm ( ) , ErrMsg ) ) return Error ( Loc , ErrMsg ) ; End = consumeToken ( ) ; } else { if ( SM . onInteger ( IntVal , ErrMsg ) ) return Error ( Loc , ErrMsg ) ; } } else { if ( SM . onInteger ( IntVal , ErrMsg ) ) return Error ( Loc , ErrMsg ) ; } break ; } case AsmToken ::


<s> return BuildMI ( MBB , MBBI , DL , TII -> get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex (

MF . addFrameInst ( CFIInst ) ) . setMIFlag ( MachineInstr :: FrameSetup ) ;


<s> virtual const char * getPassName ( )


<s> SDLoc DL ( Node ) ; const GlobalValue * GV = Node -> getGlobal ( ) ; int64_t Offset = Node -> getOffset ( ) ; EVT PtrVT = getPointerTy ( ) ; Reloc :: Model RM = TM . getRelocationModel ( ) ; CodeModel :: Model CM = TM . getCodeModel ( ) ; SDValue Result ; if ( Subtarget . isPC32DBLSymbol ( GV , RM , CM ) ) { uint64_t Anchor = Offset & ~ uint64_t ( <NUM_LIT> ) ; Result = DAG . getTargetGlobalAddress ( GV , DL , PtrVT , Anchor ) ; Result = DAG . getNode ( <STR_LIT> , DL , PtrVT , Result ) ; Offset -= Anchor


<s> bool isCK803S ( ) const { return <ISA_LIT>ProcFamily ==


<s> MI . setDesc ( B . getTII ( ) . get ( <STR_LIT> ) ) ; MI . RemoveOperand ( <NUM_LIT> ) ; const unsigned MemSize = ( Size + <NUM_LIT> ) / <NUM_LIT> ; const unsigned MemAlign = <NUM_LIT> ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo ( ) , MachineMemOperand :: MOLoad | MachineMemOperand :: MODereferenceable | MachineMemOperand :: MOInvariant , MemSize , MemAlign ) ; MI . addMemOperand ( MF , MMO ) ; if ( ! isPowerOf2_32 ( Size ) ) { LegalizerHelper Helper ( MF , * this


<s> MachineBasicBlock :: iterator MBBI = MBB . begin ( ) , E = MBB . end ( ) ; while ( MBBI


<s> if ( ! AFI -> isThumbFunction ( ) ) return false ; bool Modified = false ; for ( MachineFunction :: iterator MFI = Fn . begin ( ) , E = Fn . end ( ) ; MFI != E ; ++ MFI ) { MachineBasicBlock & MBB = * MFI ; Modified |= InsertITBlocks (


<s> int min_fpr ; int max_fpr ; if ( ! cfun -> stdarg || ! TARGET_HARD_FLOAT || ! cfun -> va_list_fpr_size || crtl -> args . info . fprs >= FP_ARG_NUM_REG ) return ; min_fpr = crtl -> args . info . fprs ; max_fpr = min_fpr + cfun


<s> if ( mode == BLKmode ) words = int_size_in_bytes ( type ) ; else words = GET_MODE_SIZE ( mode ) ; return ( words + UNITS_PER_WORD -


<s> SDValue TargetJT = DAG . getTargetJumpTable ( JT -> getIndex ( ) , <STR_LIT> ) ; unsigned NumEntries = MJTI -> getJumpTables ( ) [ JTI ] . MBBs . size ( ) ; if ( NumEntries <= <NUM_LIT> ) { return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Chain , TargetJT , Index ) ; } assert ( ( NumEntries >> <NUM_LIT> ) ==


<s> Instruction * Inst2Replace = ReuseCandidate . Inst2Replace ; Instruction * BEInst = ReuseCandidate . BackedgeInst ; int NumOperands = Inst2Replace -> getNumOperands ( ) ; std :: map < Instruction * , DepChain * > DepChains ; int Iterations = - <NUM_LIT> ; BasicBlock * LoopPH = CurLoop -> getLoopPreheader ( ) ; for ( int i = <NUM_LIT> ; i < NumOperands ; ++ i ) { Instruction * I = dyn_cast < Instruction > ( Inst2Replace -> getOperand ( i ) ) ; if ( ! I ) continue ; else { Instruction * J = cast < Instruction > ( BEInst -> getOperand ( i ) ) ; DepChain * D = getDepChainBtwn ( I , J ) ; assert ( D && <STR_LIT> ) ; if ( Iterations == - <NUM_LIT> ) Iterations = D -> iterations ( ) ; assert ( Iterations == D -> iterations ( ) && <STR_LIT> ) ; DepChains [ I ] = D ; } } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; SmallVector < Instruction * , <NUM_LIT> > InstsInPreheader ; for ( int i = <NUM_LIT> ; i < Iterations ; ++ i ) { Instruction * InstInPreheader = Inst2Replace -> clone ( ) ; SmallVector < Value * , <NUM_LIT> > Ops ; for ( int j = <NUM_LIT> ; j < NumOperands ; ++ j ) { Instruction * I = dyn_cast < Instruction > ( Inst2Replace -> getOperand ( j ) ) ; if ( ! I ) continue ; DepChain & D = * DepChains [ I ] ; Value * ValInPreheader = findValueInBlock ( D [ i ] , LoopPH ) ; InstInPreheader -> setOperand ( j , ValInPreheader


<s> auto MMO = * MI -> memoperands_begin ( ) ; const <ISA_LIT>Subtarget & STI = static_cast < const <ISA_LIT>Subtarget & > ( MI -> getMF ( ) -> getSubtarget ( ) ) ; if ( MMO -> getSize ( ) == <NUM_LIT> && ( ! STI . systemSupportsUnalignedAccess ( ) && MMO -> getSize ( ) > MMO -> getAlignment ( ) )


<s> if ( ( TREE_CODE ( type ) == UNION_TYPE || TREE_CODE ( type ) == RECORD_TYPE ) && TYPE_TRANSPARENT_AGGR ( type ) ) type = TREE_TYPE ( first_field ( type ) ) ; if ( pass_by_reference ( get_cumulative_args ( args_so_far ) , TYPE_MODE ( type ) , type , true ) ) type = build_pointer_type ( type ) ; unsignedp = TYPE_UNSIGNED ( type ) ; mode = promote_mode ( type , TYPE_MODE ( type ) , & unsignedp ) ; if ( rs6000_must_pass_in_stack ( mode , type ) ) return true ; entry_parm = rs6000_function_arg ( args_so_far , mode , type , true ) ; if ( entry_parm == NULL )


<s> Register Ins = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; LLT VecTy = MRI . getType ( Vec ) ; LLT EltTy = VecTy . getElementType ( ) ; assert ( EltTy == MRI . getType ( Ins ) ) ; B . setInstr ( MI ) ; if ( IdxVal . getValue ( ) < VecTy . getNumElements ( ) ) B . buildInsert ( Dst , Vec , Ins , IdxVal . getValue ( ) * EltTy . getSizeInBits ( ) ) ; else B . buildUndef ( Dst ) ; MI . eraseFromParent ( ) ; return


<s> const MCOperand & MO2 = MI -> getOperand ( Op + <NUM_LIT> ) ; O << <STR_LIT> << getRegisterName ( MO1 . getReg ( ) ) <<

<STR_LIT> << getRegisterName ( MO2 . getReg ( ) ) << <STR_LIT> ;


<s> bool allowIllegalIntegerIV ( ) const { return true


<s> <ISA_LIT>FunctionInfo & AFI = * MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; for ( const MachineBasicBlock & MBB : MF ) { memset ( LOHInfos , <NUM_LIT> , sizeof ( LOHInfos ) ) ; for ( const MachineBasicBlock * Succ : MBB . successors ( ) ) { for ( const auto & LI : Succ -> liveins ( ) ) { int RegIdx = mapRegToGPRIndex ( LI . PhysReg ) ; if ( RegIdx >= <NUM_LIT> ) LOHInfos [ RegIdx ] . OneUser = true ; } } for ( const MachineInstr & MI : make_range ( MBB . rbegin ( ) , MBB . rend ( ) ) ) { unsigned Opcode = MI . getOpcode


<s> else if ( MO . isImm ( ) ) return static_cast < unsigned > ( MO . getImm ( ) ) ; else if ( MO . isFPImm ( ) ) return static_cast < unsigned > ( MO . getFPImm ( ) -> getValueAPF ( ) . bitcastToAPInt ( ) . getHiBits ( <NUM_LIT> ) . getLimitedValue ( ) ) ; else if ( MO . isGlobal ( ) ) emitGlobalAddress ( MO . getGlobal ( ) , <STR_LIT> , true , false ) ; else if ( MO . isSymbol ( ) ) emitExternalSymbolAddress ( MO . getSymbolName ( ) , <STR_LIT> ) ; else if ( MO . isCPI ( ) ) { const MCInstrDesc & MCID = MI . getDesc ( ) ; unsigned Reloc = ( ( MCID . TSFlags & <STR_LIT> ) == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; emitConstPoolAddress ( MO . getIndex ( ) , Reloc


<s> const TargetRegisterClass * AddrRegClass = getRegClassFor ( Is64Bit ? <STR_LIT> : <STR_LIT> ) ; unsigned mallocPtrVReg = MRI . createVirtualRegister ( AddrRegClass ) , bumpSPPtrVReg = MRI . createVirtualRegister ( AddrRegClass ) , tmpSPVReg = MRI . createVirtualRegister ( AddrRegClass ) , SPLimitVReg = MRI . createVirtualRegister ( AddrRegClass ) , sizeVReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) , physSPReg = Is64Bit ? <STR_LIT> : <STR_LIT> ; MachineFunction :: iterator MBBIter = BB ; ++ MBBIter ; MF -> insert ( MBBIter , bumpMBB ) ; MF -> insert ( MBBIter , mallocMBB ) ; MF -> insert ( MBBIter , continueMBB ) ; continueMBB -> splice ( continueMBB -> begin ( ) , BB , llvm :: next ( MachineBasicBlock :: iterator ( MI ) ) , BB -> end ( ) ) ; continueMBB -> transferSuccessorsAndUpdatePHIs ( BB ) ; BuildMI ( BB , DL , TII -> get ( TargetOpcode :: COPY ) , tmpSPVReg ) . addReg ( physSPReg ) ; BuildMI ( BB , DL , TII -> get ( Is64Bit ? <STR_LIT> : <STR_LIT> ) , SPLimitVReg ) . addReg ( tmpSPVReg ) . addReg ( sizeVReg ) ; BuildMI ( BB , DL , TII -> get ( Is64Bit ? <STR_LIT> : <STR_LIT> ) ) . addReg ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) . addImm ( TlsOffset ) . addReg ( TlsReg ) . addReg ( SPLimitVReg ) ; BuildMI ( BB , DL , TII -> get ( <STR_LIT> ) ) . addMBB ( mallocMBB ) ; BuildMI ( bumpMBB , DL , TII -> get ( TargetOpcode :: COPY ) , physSPReg ) . addReg ( SPLimitVReg ) ; BuildMI ( bumpMBB , DL , TII -> get ( TargetOpcode

:: COPY ) , bumpSPPtrVReg ) . addReg ( SPLimitVReg ) ;


<s> Register DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; bool DstIsDead = MI . getOperand ( <NUM_LIT> ) . isDead ( ) ; bool DstIsKill = MI . getOperand ( <NUM_LIT> ) . isKill ( ) ; bool ImpIsDead = MI . getOperand ( <NUM_LIT> ) . isDead ( ) ; TRI -> splitReg ( DstReg , DstLoReg , DstHiReg ) ; buildMI ( MBB , MBBI , <STR_LIT> ) . addReg ( DstLoReg , RegState :: Define | getDeadRegState ( DstIsDead ) ) . addReg ( DstHiReg ) ; buildMI ( MBB , MBBI , <STR_LIT> ) . addReg ( DstLoReg , RegState :: Define | getDeadRegState ( DstIsDead ) ) . addReg ( DstLoReg , RegState :: Kill ) ; auto MI0 = buildMI ( MBB , MBBI , <STR_LIT> ) . addReg ( DstLoReg , RegState :: Define | getDeadRegState ( DstIsDead ) ) . addReg ( DstLoReg , getKillRegState ( DstIsKill ) ) . addImm ( <NUM_LIT> ) ; MI0 -> getOperand ( <NUM_LIT> ) . setIsDead ( ) ; auto MIBHI = buildMI ( MBB , MBBI , <STR_LIT> ) . addReg ( DstHiReg , RegState :: Define | getDeadRegState ( DstIsDead ) ) . addReg ( DstHiReg , getKillRegState ( DstIsKill ) ) . addReg ( DstHiReg , getKillRegState ( DstIsKill ) ) ; if ( ImpIsDead ) MIBHI -> getOperand (


<s> if ( Offset % Size != <NUM_LIT> ) return None ; auto GV = Adrp . getOperand ( <NUM_LIT> ) . getGlobal ( ) ; if ( GV -> isThreadLocal ( ) ) return None ; auto & MF = * RootDef . getParent ( ) -> getParent ( ) ; if ( GV -> getPointerAlignment ( MF . getDataLayout ( ) ) < Size ) return None ; unsigned OpFlags = STI . ClassifyGlobalReference ( GV , MF . getTarget ( ) ) ; MachineIRBuilder MIRBuilder ( RootDef ) ; Register AdrpReg = Adrp . getOperand ( <NUM_LIT> ) . getReg ( ) ; return { { [ = ] ( MachineInstrBuilder & MIB ) { MIB . addUse ( AdrpReg ) ; } , [ = ] ( MachineInstrBuilder


<s> if ( Subtarget . isDarwinABI ( ) ) return Subtarget . is<ISA_LIT>64 ( ) ? CSR_Darwin64_RegMask : CSR_Darwin32_RegMask ; return Subtarget . is<ISA_LIT>64 ( ) ?


<s> static inline void aarch64_sub_sp ( rtx temp1 , rtx temp2 , poly_int64 delta , bool frame_related_p ) { aarch64_add_offset ( Pmode , stack_pointer_rtx , stack_pointer_rtx , - delta , temp1 , temp2


<s> return static_cast < const <ISA_LIT>TargetMachine & > ( TM


<s> case GTU : return reg_or_0_operand ( cmp1 , VOIDmode ) ; case GE : case GEU : return ! TARGET_MIPS16 && cmp1 == const1_rtx ; case LT : case


<s> void <ISA_LIT>InstPrinter :: printDecoration ( const MCInst * MI , unsigned OpNo , raw_ostream & O ) { if ( OpNo < MI -> getNumOperands ( ) ) { <STR_LIT> e = static_cast < <STR_LIT> > ( MI -> getOperand


<s> bool hasMemNoShuf ( ) const { return HasMemNoShuf


<s> PM -> add ( create<ISA_LIT>MFInfoExtract ( get<ISA_LIT>TargetMachine ( ) , getOptLevel ( ) ) ) ; PM -> add ( create<ISA_LIT>FPRoundingModePass ( get<ISA_LIT>TargetMachine ( )


<s> if ( ! MO . isReg ( ) ) continue ; unsigned R = MO . getReg ( ) - <STR_LIT> ; if ( R < <NUM_LIT> ) { if ( MF -> getFunction ( ) . getCallingConv ( ) != CallingConv :: <ISA_LIT>_RegCall ) { assert ( MO . isDef ( ) && MO . isImplicit ( ) ) ; } STReturns |= <NUM_LIT> << R ; } } unsigned N = countTrailingOnes ( STReturns ) ; assert ( STReturns == <NUM_LIT> || ( isMask_32 ( STReturns ) && N <= <NUM_LIT> ) ) ; while ( StackTop > <NUM_LIT> ) popReg ( ) ; for ( unsigned I = <NUM_LIT> ; I < N ; ++ I ) pushReg ( N - I -


<s> const MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; Mapping = InstructionMapping { <NUM_LIT> , <NUM_LIT> , nullptr , MI . getNumOperands ( ) } ; SmallVector < const ValueMapping * , <NUM_LIT> > OpdsMapping ( MI . getNumOperands ( ) ) ; switch ( MI . getOpcode ( ) ) { default : break ; case <STR_LIT> : { unsigned Size = MRI . getType ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) . getSizeInBits ( ) ; OpdsMapping [ <NUM_LIT> ] = <STR_LIT> ( <STR_LIT> , Size ) ; Mapping . setOperandsMapping ( getOperandsMapping ( OpdsMapping ) ) ; return Mapping ; } case <STR_LIT> : { for ( unsigned i = <NUM_LIT> , e = MI . getNumOperands ( ) ; i != e ; ++ i ) { if ( ! MI . getOperand ( i ) . isReg ( ) ) continue ; unsigned Size = MRI . getType ( MI . getOperand ( i ) . getReg ( ) ) . getSizeInBits ( ) ; OpdsMapping [ i ] = <STR_LIT> ( <STR_LIT> , Size ) ; } Mapping . setOperandsMapping ( getOperandsMapping ( OpdsMapping ) ) ; return Mapping ; } case <STR_LIT> : { assert ( MI . getOperand ( <NUM_LIT> ) . isReg ( ) ) ; unsigned Size = MRI . getType ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) . getSizeInBits ( ) ; const ValueMapping * ValMapping = <STR_LIT> ( <STR_LIT> , Size ) ; const ValueMapping * PtrMapping = <STR_LIT> ( <STR_LIT> , <NUM_LIT> ) ; OpdsMapping [ <NUM_LIT> ] = ValMapping ; OpdsMapping [ <NUM_LIT> ] = PtrMapping ; Mapping . setOperandsMapping ( getOperandsMapping ( OpdsMapping ) ) ; return Mapping ; } case <STR_LIT> : return getInstrMappingForLoad ( MI ) ; } unsigned BankID = <STR_LIT> ; Mapping = InstructionMapping { <NUM_LIT> , <NUM_LIT> , nullptr , MI . getNumOperands ( ) } ; unsigned Size = <NUM_LIT> ; for ( unsigned Idx = <NUM_LIT> ; Idx < MI . getNumOperands ( ) ; ++ Idx ) { if ( MI . getOperand ( Idx ) . isReg ( ) ) Size = getSizeInBits ( MI . getOperand (


<s> void <ISA_LIT>InstrInfo :: storeRegToStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , unsigned SrcReg , bool isKill , int FrameIdx , const TargetRegisterClass * RC ) const { MachineFunction & MF = * MBB . getParent ( ) ; SmallVector < MachineInstr * , <NUM_LIT> >


<s> for ( const MachineOperand & Op : MI . uses ( ) ) if ( Op . isFI ( ) ) return true ; return


<s> if ( getLexer ( ) . getKind ( ) != AsmToken :: Identifier ) return MatchOperand_NoMatch ; StringRef Str = Parser . getTok ( ) . getString ( ) ; int Slot = StringSwitch < int > ( Str ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Default ( - <NUM_LIT> ) ; SMLoc S = Parser . getTok ( )


<s> OperandMatchResultTy Res = tryParseScalarRegister ( RegNum ) ; if ( Res != MatchOperand_Success ) return Res ; if ( ! ParseShiftExtend || getTok ( ) . isNot ( AsmToken :: Comma ) ) { Operands . push_back ( <ISA_LIT>Operand :: CreateReg ( RegNum , RegKind :: Scalar , StartLoc , getLoc ( ) , getContext ( ) , EqTy ) ) ; return MatchOperand_Success ; } Lex ( )


<s> case LT : case GE : return y == const0_rtx ? CC_NZmode : CCmode ; case GTU : case GEU : case LTU : case LEU : return y == const0_rtx ? CC_NZmode


<s> if ( MI -> modifiesRegister ( CalleeSavedReg , TRI ) ) return true ; } return false


<s> MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const TargetRegisterInfo * RegInfo = MF . getTarget ( ) . getRegisterInfo ( ) ; bool LRUsed = MF . getRegInfo ( ) . isPhysRegUsed ( <STR_LIT> ) ; const TargetRegisterClass * RC = & <STR_LIT> ; <ISA_LIT>FunctionInfo * XFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; if ( LRUsed ) { MF . getRegInfo ( )


<s> TargetRegistry :: RegisterMCInstrInfo ( The<ISA_LIT>Target , create<ISA_LIT>MCInstrInfo ) ; TargetRegistry :: RegisterMCInstPrinter ( The<ISA_LIT>Target , create<ISA_LIT>MCInstPrinter


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) : LLVMTargetMachine ( T , TT . isArch64Bit ( ) ? <STR_LIT> : <STR_LIT> , TT , CPU , FS ,

Options , RM , CM , OL ) , TLOF ( make_unique < <ISA_LIT>TargetObjectFile > ( ) ) {


<s> bool <ISA_LIT>TargetLowering :: canMergeStoresTo ( unsigned AddressSpace , EVT MemVT , const SelectionDAG & DAG ) const { bool NoFloat = DAG . getMachineFunction ( ) . getFunction ( ) . hasFnAttribute ( Attribute :: NoImplicitFloat ) ; if ( NoFloat ) { unsigned MaxIntSize = Subtarget . is64Bit ( ) ? <NUM_LIT> : <NUM_LIT> ; return ( MemVT . getSizeInBits ( ) <= MaxIntSize ) ; } if ( MemVT . getSizeInBits ( ) > Subtarget . getPreferVectorWidth ( ) ) return false ; return


<s> Register Data = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; const unsigned Opc = MRI -> getType ( Data ) . isVector ( ) ? <STR_LIT> : <STR_LIT> ; auto MIB = BuildMI ( * MBB , & MI , DL , TII . get ( Opc ) ) . addReg ( Addr . first ) . addReg ( Data ) . addImm ( Addr . second ) . addImm ( <NUM_LIT> ) . cloneMemRefs ( MI ) ; MI . eraseFromParent ( ) ; return constrainSelectedInstRegOperands ( * MIB , TII


<s> assert ( std :: is_sorted ( std :: begin ( NEONLdStTable ) , std :: end ( NEONLdStTable ) ) && <STR_LIT> ) ; TableChecked = true ; } auto I = std :: lower_bound ( std :: begin ( NEONLdStTable ) , std :: end ( NEONLdStTable )


<s> static void report_non_ice ( location_t location , tree


<s> Header . amd_machine_version_stepping = ISA . Stepping ; Header . kernel_code_entry_byte_offset = sizeof ( Header ) ; Header . wavefront_size = <NUM_LIT> ; Header . call_convention = - <NUM_LIT> ; Header . kernarg_segment_alignment = <NUM_LIT> ; Header . group_segment_alignment =


<s> bool hasImplicitBufferPtr ( ) const { return


<s> HOST_WIDE_INT len , pos ; if ( ! ISA_HAS_EXT_INS || ! register_operand ( op , VOIDmode ) || GET_MODE_BITSIZE ( GET_MODE ( op ) ) > BITS_PER_WORD ) return false ; len = INTVAL ( size ) ; pos = INTVAL ( position ) ; if ( len <= <NUM_LIT> || len >= GET_MODE_BITSIZE ( GET_MODE ( op ) ) || pos < <NUM_LIT> || pos + len > GET_MODE_BITSIZE (


<s> instr2 . setOpcode ( <STR_LIT> ) ; instr2 . addOperand ( target ) ; instr2 . addOperand ( base ) ; instr2 . addOperand ( name ) ; instr3 . setOpcode ( <STR_LIT> ) ; instr3 . addOperand ( target ) ; instr3 . addOperand ( atReg ) ; instr3 . addOperand ( MCOperand :: CreateImm ( <NUM_LIT> ) ) ; instr3 . addOperand ( MCOperand :: CreateImm ( <NUM_LIT> ) ) ; break ; } case <STR_LIT> : { assert ( base . getReg ( ) != target . getReg ( ) ) ; two_instructions = true ; MCOperand adj_name = LowerOperand ( unloweredName , <NUM_LIT> ) ; instr1 . setOpcode ( <STR_LIT> ) ; instr1 . addOperand ( target ) ; instr1 . addOperand ( base ) ; instr1 . addOperand ( adj_name ) ; instr2 . setOpcode ( <STR_LIT> ) ; instr2 . addOperand ( target ) ; instr2 . addOperand ( base ) ; instr2 . addOperand ( name ) ; break ; } case <STR_LIT> : { MCOperand adj_name = LowerOperand ( unloweredName , <NUM_LIT> ) ; instr1 . setOpcode ( <STR_LIT> ) ; instr1 . addOperand ( target ) ; instr1 . addOperand ( base ) ; instr1 . addOperand ( name ) ; instr2 . setOpcode ( <STR_LIT> ) ; instr2 . addOperand ( atReg ) ; instr2 . addOperand ( target ) ; instr2 . addOperand ( MCOperand :: CreateImm ( <NUM_LIT> ) ) ; instr3 . setOpcode ( <STR_LIT> ) ; instr3 . addOperand ( atReg ) ; instr3 . addOperand ( base ) ; instr3 . addOperand ( adj_name ) ; break ; } default : assert ( <NUM_LIT> && <STR_LIT> ) ; } MCInsts . push_back (


<s> bool addPassesToEmitMachineCode ( PassManagerBase & , JITCodeEmitter & , bool = true ) override { return true


<s> t_naked = lookup_attribute ( <STR_LIT> , DECL_ATTRIBUTES ( func ) ) ; t_no_prologue = lookup_attribute ( <STR_LIT> , DECL_ATTRIBUTES ( func ) ) ; return ( ( t_naked != NULL_TREE ) ||


<s> void setBytesToPopOnReturn ( unsigned


<s> SDValue N0 = N -> getOperand ( <NUM_LIT> ) , N1 = N -> getOperand ( <NUM_LIT> ) ; if ( N0 . getOpcode ( ) == <STR_LIT> && N0 . getNode ( ) -> hasOneUse ( ) ) { SDValue Result = combineSelectAndUse ( N , N0 , N1 , DCI ) ; if ( Result . getNode ( ) ) return Result ; } if ( N1 . getOpcode ( ) == <STR_LIT> && N1 . getNode ( ) -> hasOneUse (


<s> const MachineRegisterInfo * MRI = & MF . getRegInfo ( ) ; const <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; const <ISA_LIT>FrameLowering * TFI = getFrameLowering ( MF ) ; if ( ! TargetRegisterInfo :: canRealignStack (


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case


<s> const MCOperand & Op = Inst . getOperand ( i ) ; if ( Op . isExpr ( ) ) hasExp = true ; if ( Op . isReg ( ) && Op . getReg (


<s> const LLT ValTy = MRI . getType ( ValReg ) ; if ( ! ValTy . isVector ( ) || ! ValTy . getElementType ( ) . isPointer ( ) || ValTy . getElementType ( ) . getAddressSpace ( ) != <NUM_LIT> ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } MIRBuilder . setInstrAndDebugLoc ( MI ) ; unsigned PtrSize = ValTy . getElementType ( ) . getSizeInBits ( ) ; const LLT NewTy = LLT :: vector ( ValTy . getNumElements ( ) , PtrSize ) ; auto & MMO = * * MI . memoperands_begin ( ) ; if ( MI . getOpcode ( ) == TargetOpcode :: G_STORE


<s> return true ; } else { if ( MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> ) { return true


<s> if ( DECL_P ( td ) ) td = TREE_TYPE ( td ) ; if ( td == error_mark_node ) return false ; return lookup_attribute ( <STR_LIT> , TYPE_ATTRIBUTES (


<s> const unsigned DiviserReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; const LLT RegTy = MRI . getType ( DstReg ) ; assert ( RegTy == MRI . getType ( DividentReg ) && RegTy == MRI . getType ( DiviserReg ) && <STR_LIT> ) ; const RegisterBank & RegRB = * RBI . getRegBank ( DstReg , MRI , TRI ) ; const static struct SDivEntry { unsigned SizeInBits ; unsigned QuotientReg ; unsigned DividentRegUpper ; unsigned DividentRegLower ; unsigned OpSignExtend ; unsigned OpCopy ; unsigned OpDiv ; } OpTable [ ] = { { <NUM_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> , <STR_LIT> , <STR_LIT> } , { <NUM_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , TargetOpcode :: COPY , <STR_LIT> } , { <NUM_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , TargetOpcode :: COPY , <STR_LIT> } , { <NUM_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , TargetOpcode :: COPY , <STR_LIT> } } ; if ( RegRB . getID ( ) != <STR_LIT> ) return false ; auto SDivEntryIt = std :: find_if ( std :: begin ( OpTable ) , std :: end ( OpTable ) , [ RegTy ] ( const SDivEntry & El ) { return El . SizeInBits == RegTy . getSizeInBits ( ) ; } ) ; if ( SDivEntryIt == std :: end ( OpTable ) ) return false ; const TargetRegisterClass * RegRC = getRegClass ( RegTy , RegRB ) ; if ( ! RBI . constrainGenericRegister ( DividentReg , * RegRC , MRI ) || ! RBI . constrainGenericRegister ( DiviserReg , * RegRC , MRI ) || ! RBI . constrainGenericRegister ( DstReg , * RegRC , MRI ) ) { DEBUG ( dbgs ( ) << <STR_LIT> << TII . getName ( I . getOpcode ( ) ) << <STR_LIT> ) ; return false ; } BuildMI ( * I . getParent ( ) , I , I . getDebugLoc ( ) , TII . get ( SDivEntryIt -> OpCopy ) , SDivEntryIt -> DividentRegLower ) . addReg ( DividentReg ) ; if ( SDivEntryIt -> DividentRegUpper != <STR_LIT> ) BuildMI ( * I . getParent ( ) , I , I . getDebugLoc ( ) , TII . get (


<s> Chain = ( depth || AlwaysFlush ) ? getFLUSHW ( Op , DAG ) : DAG . getEntryNode ( ) ; FrameAddr = DAG . getCopyFromReg ( Chain , dl , FrameReg , VT ) ; unsigned Offset = ( Subtarget -> is64Bit ( ) ) ? ( stackBias + <NUM_LIT> ) : <NUM_LIT> ; while ( depth -- ) { SDValue Ptr = DAG . getNode ( <STR_LIT> , dl , VT , FrameAddr ,

DAG . getIntPtrConstant ( Offset , dl ) ) ;


<s> for ( unsigned i = <NUM_LIT> , e = CSI . size ( ) ; i != e ; ++ i ) { unsigned RegNum = <ISA_LIT>RegisterInfo :: getRegisterNumbering ( CSI [ i ] . getReg ( ) ) ; if ( CSI [ i ] . getRegClass ( ) == <STR_LIT> ) CPUBitmask |= ( <NUM_LIT> << RegNum ) ; } if ( RI . hasFP ( * MF ) ) CPUBitmask |= ( <NUM_LIT> << <ISA_LIT>RegisterInfo :: getRegisterNumbering ( RI . getFrameRegister (


<s> bool <ISA_LIT>InstrInfo :: isPredicable ( MachineInstr * MI ) const { bool isPred = MI -> getDesc ( ) . isPredicable ( ) ; if ( ! isPred ) return false ; const int Opc = MI -> getOpcode ( ) ; switch ( Opc ) { case <STR_LIT> : return isInt < <NUM_LIT> > ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; case <STR_LIT> : return isShiftedUInt < <NUM_LIT> , <NUM_LIT> > ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; case <STR_LIT> : case <STR_LIT> : return isShiftedUInt < <NUM_LIT> , <NUM_LIT> > ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; case <STR_LIT> : case <STR_LIT> : return isShiftedUInt < <NUM_LIT> , <NUM_LIT> > ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; case <STR_LIT> : case <STR_LIT> : return isUInt < <NUM_LIT> > ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; case <STR_LIT> : return isShiftedUInt < <NUM_LIT> , <NUM_LIT> > ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; case <STR_LIT> : return isShiftedUInt < <NUM_LIT> , <NUM_LIT> > ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; case <STR_LIT> : case <STR_LIT> : return isShiftedUInt < <NUM_LIT> , <NUM_LIT> > ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; case <STR_LIT> : case <STR_LIT> : return isUInt < <NUM_LIT> > ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; case <STR_LIT> : return isShiftedInt < <NUM_LIT> , <NUM_LIT> > ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; case <STR_LIT> : return isShiftedInt < <NUM_LIT> , <NUM_LIT> > ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; case <STR_LIT> : case <STR_LIT> : return isShiftedInt < <NUM_LIT> , <NUM_LIT> > ( MI -> getOperand (


<s> unsigned getNumberOfRegisters ( bool Vector ) { if ( Vector ) { return <NUM_LIT> ; } return <NUM_LIT>


<s> <ISA_LIT>PassConfig :: addInstSelector ( ) ; addPass ( & <ISA_LIT>FixSGPRCopiesID ) ; addPass ( create<ISA_LIT>LowerI1CopiesPass


<s> MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; unsigned i = <NUM_LIT> ; while ( ! MI . getOperand ( i ) . isFI ( ) ) { ++ i ; assert ( i < MI . getNumOperands ( ) && <STR_LIT> ) ; } LLVM_DEBUG ( errs ( ) << <STR_LIT> << MF . getFunction ( ) . getName ( ) << <STR_LIT> ; errs ( ) << <STR_LIT> << MI ) ; int FrameIndex = MI . getOperand ( i ) . getIndex ( ) ; uint64_t stackSize = MF . getFrameInfo ( ) . getStackSize ( ) ; int64_t spOffset = MF . getFrameInfo ( )


<s> if ( ! I -> hasOneUse ( ) ) return false ; auto * Sub = cast < Instruction > ( * I -> users ( ) . begin ( ) ) ; return Sub -> getOpcode ( ) == Instruction :: FSub && Sub -> getOperand ( <NUM_LIT> ) == I ; } ; auto IsFMS = [ & ] ( Instruction * I ) { if ( match ( I -> getOperand ( <NUM_LIT> ) , m_FNeg ( m_Value ( ) ) ) || match ( I -> getOperand ( <NUM_LIT> ) , m_FNeg ( m_Value ( ) ) ) ) return true ; return false ; } ; auto IsSinker = [ & ] ( Instruction * I , int Operand ) { switch ( I -> getOpcode ( ) ) { case Instruction :: Add : case Instruction :: Mul : case Instruction :: FAdd : case Instruction :: ICmp : case Instruction :: FCmp : return true ; case Instruction :: FMul : return ! IsFMSMul ( I ) ; case Instruction :: Sub : case Instruction :: FSub : case Instruction :: Shl : case Instruction :: LShr : case Instruction :: AShr


<s> return selectBrCondImm ( MI ) ; case <STR_LIT> : return selectSbc ( MI ) ; case <STR_LIT> : return selectFrameIndex ( MI ) ; case <STR_LIT> : case <STR_LIT> : return selectAddr ( MI ) ; case <STR_LIT> : case <STR_LIT> : return selectStore ( MI ) ; case <STR_LIT> : case <STR_LIT> : return selectLshrShlE ( MI ) ; case <STR_LIT> : return selectMergeValues ( MI ) ; case <STR_LIT> : return selectTrunc ( MI ) ; case <STR_LIT> : case <STR_LIT> : return selectAddE ( MI ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return selectIncDecMB ( MI


<s> if ( Start -> getOpcode ( ) == <STR_LIT> ) { TPNumElements = Start -> getOperand ( <NUM_LIT> ) ; StartInsertPt = Start ; StartInsertBB = Start -> getParent ( ) ; } else { TPNumElements = VCTP -> getOperand ( <NUM_LIT> ) ; MCRegister NumElements = TPNumElements . getReg ( ) . asMCReg ( ) ; if ( RDA . hasLocalDefBefore ( VCTP , NumElements ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } if ( StartInsertPt != StartInsertBB -> end ( ) && ! RDA . isReachingDefLiveOut ( & * StartInsertPt , NumElements ) ) { if ( auto * ElemDef = RDA . getLocalLiveOutMIDef ( StartInsertBB , NumElements ) ) { if ( RDA . isSafeToMoveForwards ( ElemDef , & * StartInsertPt ) ) { ElemDef -> removeFromParent ( ) ; StartInsertBB -> insert ( StartInsertPt , ElemDef ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * ElemDef ) ; } else if ( RDA . isSafeToMoveBackwards ( & * StartInsertPt , ElemDef ) ) { StartInsertPt -> removeFromParent ( ) ; StartInsertBB -> insertAfter ( MachineBasicBlock :: iterator ( ElemDef ) , & * StartInsertPt ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * ElemDef ) ; } else { MachineOperand Operand = ElemDef -> getOperand ( <NUM_LIT> ) ; if ( isMovRegOpcode ( ElemDef -> getOpcode ( ) ) && RDA . getUniqueReachingMIDef ( ElemDef , Operand . getReg ( ) . asMCReg ( ) ) == RDA . getUniqueReachingMIDef ( & * StartInsertPt , Operand . getReg ( ) . asMCReg ( ) ) ) { TPNumElements = Operand ; NumElements = TPNumElements . getReg ( ) ; } else { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << <STR_LIT> ) ; return false ; } } } } auto CannotProvideElements = [ this ] ( MachineBasicBlock * MBB , MCRegister NumElements ) { if ( MBB -> empty ( ) ) return false ; if ( RDA . hasLocalDefBefore ( & MBB -> back ( ) , NumElements ) ) return true ; if ( MBB -> pred_size ( ) > <NUM_LIT> ) return true ; return false ; } ; MachineBasicBlock * MBB = Preheader ; while ( MBB && MBB != StartInsertBB ) { if ( CannotProvideElements ( MBB


<s> static bool isSmallTypeLdMerge ( MachineInstr * MI )


<s> if ( ConstantOpNo == III . OpNoForForwarding ) { if ( SpecialShift32 || SpecialShift64 ) { LoadImmediateInfo LII ; LII . Imm = <NUM_LIT> ; LII . SetCR = SetCR ; LII . Is64Bit = SpecialShift64 ; uint64_t ShAmt = Imm & ( SpecialShift32 ? <NUM_LIT> : <NUM_LIT> ) ; if ( Imm & ( SpecialShift32 ? <NUM_LIT> : <NUM_LIT> ) ) replaceInstrWithLI ( MI , LII ) ; else if ( ! SetCR && ShAmt == <NUM_LIT> && ! PostRA ) { MI . RemoveOperand ( <NUM_LIT> ) ; MI . setDesc ( get ( <STR_LIT> ) ) ; } else { if ( SpecialShift32 ) { uint64_t SH = RightShift ? <NUM_LIT> - ShAmt : ShAmt ; uint64_t MB = RightShift ? ShAmt : <NUM_LIT> ; uint64_t ME = RightShift ? <NUM_LIT> : <NUM_LIT> - ShAmt ; replaceInstrOperandWithImm ( MI , III . OpNoForForwarding , SH ) ; MachineInstrBuilder ( * MI . getParent ( ) -> getParent ( ) , MI ) . addImm ( MB ) . addImm ( ME ) ; } else { uint64_t SH = RightShift ? <NUM_LIT> - ShAmt : ShAmt ; uint64_t ME = RightShift ? ShAmt : <NUM_LIT> - ShAmt ; replaceInstrOperandWithImm ( MI , III . OpNoForForwarding , SH ) ; MachineInstrBuilder ( * MI . getParent ( ) -> getParent ( ) , MI ) . addImm ( ME ) ; } } } else replaceInstrOperandWithImm ( MI , ConstantOpNo , Imm ) ; } else if ( III . IsCommutative ) { replaceInstrOperandWithImm ( MI , ConstantOpNo , Imm


<s> static void microblaze_asm_output_mi_thunk ( FILE * file , tree thunk_fndecl ATTRIBUTE_UNUSED , HOST_WIDE_INT delta , HOST_WIDE_INT vcall_offset , tree function ) { rtx this_rtx , funexp ; rtx_insn * insn ; reload_completed = <NUM_LIT> ; epilogue_completed = <NUM_LIT> ; emit_note ( NOTE_INSN_PROLOGUE_END ) ; if ( aggregate_value_p ( TREE_TYPE ( TREE_TYPE ( function ) ) , function ) ) this_rtx = gen_rtx_REG ( Pmode , ( MB_ABI_FIRST_ARG_REGNUM + <NUM_LIT> ) ) ; else this_rtx = gen_rtx_REG ( Pmode , MB_ABI_FIRST_ARG_REGNUM ) ; if ( delta ) emit_insn ( gen_addsi3 ( this_rtx , this_rtx , GEN_INT ( delta ) ) ) ; if ( vcall_offset ) { rtx vcall_offset_rtx = GEN_INT ( vcall_offset ) ; rtx temp1 = gen_rtx_REG ( Pmode , MB_ABI_TEMP1_REGNUM ) ; emit_move_insn ( temp1 , gen_rtx_MEM ( Pmode , this_rtx ) ) ; rtx loc = gen_rtx_PLUS ( Pmode , temp1 , vcall_offset_rtx ) ; emit_move_insn ( temp1 , gen_rtx_MEM ( Pmode , loc ) ) ; emit_insn ( gen_addsi3 ( this_rtx , this_rtx , temp1 ) ) ; } if ( ! TREE_USED ( function ) ) { assemble_external ( function ) ; TREE_USED ( function ) = <NUM_LIT> ; } funexp = XEXP ( DECL_RTL ( function ) , <NUM_LIT> ) ; rtx temp2 = gen_rtx_REG ( Pmode , MB_ABI_TEMP2_REGNUM ) ; if ( flag_pic ) emit_move_insn ( temp2 , expand_pic_symbol_ref ( Pmode , funexp ) ) ; else emit_move_insn ( temp2 , funexp ) ; emit_insn ( gen_indirect_jump ( temp2 ) ) ; insn = get_insns ( ) ; shorten_branches ( insn ) ; final_start_function ( insn , file , <NUM_LIT> ) ; final ( insn , file , <NUM_LIT> ) ; final_end_function ( )


<s> NaCl<ISA_LIT>AsmBackend ( const Target & T , const StringRef TT , uint8_t _OSABI , bool isLittle ) : ELF<ISA_LIT>AsmBackend ( T , TT , _OSABI , isLittle ) , STI ( <ISA_LIT>_MC :: create<ISA_LIT>MCSubtargetInfo ( TT , <STR_LIT> , <STR_LIT> ) ) { assert ( isLittle && <STR_LIT> ) ; State . SaveCount = <NUM_LIT> ; State . I = <NUM_LIT>


<s> if ( CRBit == <STR_LIT> || CRBit == <STR_LIT> || CRBit == <STR_LIT> || CRBit == <STR_LIT> || CRBit == <STR_LIT> || CRBit == <STR_LIT> || CRBit == <STR_LIT> || CRBit == <STR_LIT> ) Ret = <NUM_LIT> ; if ( CRBit == <STR_LIT> || CRBit == <STR_LIT> || CRBit == <STR_LIT> || CRBit == <STR_LIT> || CRBit == <STR_LIT> || CRBit == <STR_LIT> || CRBit == <STR_LIT> || CRBit == <STR_LIT> ) Ret = <NUM_LIT> ; if ( CRBit == <STR_LIT> || CRBit == <STR_LIT> || CRBit == <STR_LIT> || CRBit == <STR_LIT> || CRBit == <STR_LIT> || CRBit == <STR_LIT> || CRBit == <STR_LIT> || CRBit == <STR_LIT> ) Ret = <NUM_LIT> ; if ( CRBit == <STR_LIT> || CRBit == <STR_LIT> || CRBit == <STR_LIT> || CRBit == <STR_LIT> || CRBit == <STR_LIT> || CRBit == <STR_LIT> || CRBit == <STR_LIT> || CRBit == <STR_LIT> ) Ret = <NUM_LIT> ; assert ( Ret != <NUM_LIT> && <STR_LIT> ) ; return Ret


<s> static bool or1k_return_in_memory ( const_tree type , const_tree ) { const HOST_WIDE_INT size = int_size_in_bytes ( type


<s> const LLT S32 = LLT :: scalar ( <NUM_LIT> ) ; assert ( MRI . getType ( Src ) == S64 && MRI . getType ( Dst ) == S64 ) ; auto Unmerge = B . buildUnmerge ( { S32 , S32 } , Src ) ; auto CvtHi = Signed ? B . build<ISA_LIT>TOFP ( S64 , Unmerge . getReg ( <NUM_LIT> ) ) : B . buildUITOFP ( S64 , Unmerge . getReg ( <NUM_LIT> ) ) ; auto CvtLo = B . buildUITOFP ( S64 , Unmerge . getReg ( <NUM_LIT> ) ) ; auto ThirtyTwo = B . buildConstant (


<s> if ( ! isInt < <NUM_LIT> > ( Addr . Offset ) ) UseOffset = false ; if ( ! UseOffset && Addr . BaseType == Address :: FrameIndexBase ) { unsigned ResultReg = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , ResultReg ) . addFrameIndex ( Addr . Base . FI ) . addImm ( <NUM_LIT> ) ; Addr . Base . Reg = ResultReg ; Addr . BaseType = Address :: RegBase ; } if ( ! UseOffset ) { IntegerType * OffsetTy = ( ( VT == <STR_LIT> ) ? Type :: getInt32Ty ( * Context ) : Type :: getInt64Ty ( * Context ) ) ; const ConstantInt * Offset = ConstantInt :: getSigned ( OffsetTy , ( int64_t ) ( Addr . Offset ) ) ; IndexReg = <ISA_LIT>MaterializeInt ( Offset , <STR_LIT> ) ; assert ( IndexReg && <STR_LIT>


<s> std :: vector < MachineBasicBlock * > order ; for ( df_iterator < MachineBasicBlock * > I = df_begin ( & MF . front ( ) ) , E = df_end ( & MF . front ( ) ) ; I != E ; ++ I ) { order . push_back ( * I ) ; } std :: vector < MachineBasicBlock * > :: iterator I = order . begin ( ) , E = order . end ( ) ; MachineBasicBlock * BaseMBB = * I ; auto BaseBlock = RootScope -> findBlockOf ( BaseMBB ) ; DEBUG_TRACE ( dbgs ( ) << <STR_LIT> << BaseMBB -> getNumber ( ) << <STR_LIT> ) ; while ( ++ I != E ) { MachineBasicBlock * MBB = * I ; if ( MBB -> pred_size ( ) == <NUM_LIT> ) { DEBUG_TRACE ( dbgs ( ) << <STR_LIT> << MBB -> getNumber ( ) << <STR_LIT> ) ; BaseMBB -> splice ( BaseMBB -> end ( ) , MBB , MBB -> begin ( ) , MBB -> end ( ) ) ; BaseMBB -> removeSuccessor ( MBB ) ; BaseMBB -> transferSuccessors ( MBB ) ; MF . erase ( MBB ) ; auto MBBBlock = RootScope -> findBlockOf ( MBB ) ; if ( BaseBlock ) { if ( MBBBlock ) { RootScope -> merge ( BaseBlock , MBBBlock ) ; } } else { if ( MBBBlock ) { MBBBlock -> replaceMbb ( BaseMBB ) ; } } if ( BaseMBB -> succ_size ( ) > <NUM_LIT> ) { BaseMBB = * ( ++ I ) ; DEBUG_TRACE ( dbgs ( ) << <STR_LIT> << BaseMBB -> getNumber ( ) << <STR_LIT> ) ; } } else { BaseMBB = MBB ; DEBUG_TRACE ( dbgs ( ) << <STR_LIT> <<


<s> MachineFunction :: iterator EntryBlkIter = ++ EntryBlk -> getIterator ( ) ; MachineBasicBlock * GuardedRegsBlk = Func -> CreateMachineBasicBlock ( LLVMBlk ) ; MachineBasicBlock * TailBlk = Func -> CreateMachineBasicBlock ( LLVMBlk ) ; Func -> insert ( EntryBlkIter , GuardedRegsBlk ) ; Func -> insert ( EntryBlkIter , TailBlk ) ; TailBlk -> splice ( TailBlk -> begin ( ) , EntryBlk , std :: next ( MachineBasicBlock :: iterator ( VAStartPseudoInstr ) ) , EntryBlk -> end ( ) ) ; TailBlk -> transferSuccessorsAndUpdatePHIs ( EntryBlk ) ; uint64_t FrameOffset = VAStartPseudoInstr -> getOperand ( <NUM_LIT> ) . getImm ( ) ; uint64_t VarArgsRegsOffset = VAStartPseudoInstr -> getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned MOVOpc = STI -> hasAVX ( ) ? <STR_LIT> : <STR_LIT> ; for ( int64_t OpndIdx = <NUM_LIT> , RegIdx = <NUM_LIT> ; OpndIdx < VAStartPseudoInstr -> getNumOperands ( ) - <NUM_LIT> ; OpndIdx ++ , RegIdx ++ ) { auto NewMI = BuildMI ( GuardedRegsBlk , DL ,


<s> const TargetRegisterClass * <ISA_LIT>RegisterInfo :: getSGPRClassForBitWidth ( unsigned BitWidth ) { if ( BitWidth <= <NUM_LIT> ) return & <STR_LIT> ; if ( BitWidth <= <NUM_LIT> ) return & <STR_LIT> ; if ( BitWidth <= <NUM_LIT> ) return & <STR_LIT> ; if ( BitWidth <= <NUM_LIT> ) return & <STR_LIT> ; if ( BitWidth <= <NUM_LIT> ) return & <STR_LIT> ; if ( BitWidth <= <NUM_LIT> ) return & <STR_LIT> ; if ( BitWidth <= <NUM_LIT> ) return &


<s> if ( isZero ( Elt ) ) return true ; if ( ConstantFPSDNode * CFP = dyn_cast < ConstantFPSDNode > ( Elt ) ) return CFP -> getValueAPF ( ) . isPosZero ( ) ; return


<s> SDValue ExtractedFromVec = Op . getOperand ( i ) . getOperand ( <NUM_LIT> ) ; SDValue ExtIdx = Op . getOperand ( i ) . getOperand ( <NUM_LIT> ) ; if ( ! isa < ConstantSDNode > ( ExtIdx ) ) return SDValue ( ) ; int Idx = getUnderlyingExtractedFromVec ( ExtractedFromVec , ExtIdx ) ; if ( ExtractedFromVec . getValueType ( ) != VT ) return SDValue ( ) ; if ( ! VecIn1 . getNode ( ) ) VecIn1 = ExtractedFromVec ; else if ( VecIn1 != ExtractedFromVec ) { if ( ! VecIn2 . getNode ( ) ) VecIn2 = ExtractedFromVec ; else if ( VecIn2 != ExtractedFromVec ) return SDValue ( ) ; } if ( ExtractedFromVec == VecIn1 ) Mask [ i ] = Idx ; else if ( ExtractedFromVec == VecIn2 ) Mask [ i ] = Idx + NumElems ; } if ( ! VecIn1 . getNode ( ) ) return SDValue ( ) ; VecIn2 = VecIn2 . getNode ( ) ? VecIn2 : DAG . getUNDEF ( VT ) ; SDValue NV = DAG . getVectorShuffle ( VT , DL , VecIn1 , VecIn2 , & Mask [ <NUM_LIT> ] ) ; for ( unsigned i = <NUM_LIT> , e = InsertIndices . size ( ) ; i != e ; ++ i ) { unsigned Idx = InsertIndices [ i ] ; NV = DAG . getNode ( <STR_LIT> , DL , VT , NV , Op . getOperand ( Idx ) , DAG .


<s> if ( ! GVar || ! GVar -> hasInitializer ( ) ) return false ; return ! isa < UndefValue > ( GVar ->


<s> errs ( ) << <STR_LIT> << Disp << '\n' ; if ( GV ) { errs ( ) << <STR_LIT> ; GV -> dump ( ) ; } else if ( CP ) { errs ( ) << <STR_LIT> ; CP -> dump ( ) ; errs ( ) << <STR_LIT> <<


<s> if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) { for ( ; ; ) { const MCExpr * Value ; if ( getParser ( ) . parseExpression ( Value ) ) { Parser . eatToEndOfStatement ( ) ; return false ; } getParser ( ) . getStreamer ( ) . EmitValue ( Value , Size , L ) ; if ( getLexer ( ) . is ( AsmToken :: EndOfStatement ) ) break ; if ( getLexer ( ) . isNot ( AsmToken :: Comma ) ) { Error ( L , <STR_LIT> ) ; return false ; } Parser . Lex ( ) ; } } Parser . Lex (


<s> <ISA_LIT>Subtarget :: <ISA_LIT>Subtarget ( const Triple & TT , StringRef CPU , StringRef FS , const <ISA_LIT>TargetMachine & TM , unsigned StackAlignOverride ) : <ISA_LIT>GenSubtargetInfo ( TT , CPU , FS ) , <ISA_LIT>ProcFamily ( Others ) , PICStyle ( PICStyles :: None ) , TM ( TM ) , TargetTriple ( TT ) , StackAlignOverride ( StackAlignOverride ) , In64BitMode ( TargetTriple . getArch ( ) == Triple :: x86_64 ) , In32BitMode ( TargetTriple . getArch ( ) == Triple :: x86 && TargetTriple . getEnvironment ( ) != Triple :: CODE16 ) , In16BitMode ( TargetTriple . getArch ( ) == Triple :: x86 && TargetTriple . getEnvironment ( ) == Triple :: CODE16 ) , InstrInfo ( initializeSubtargetDependencies ( CPU , FS ) ) , TLInfo ( TM , * this ) , FrameLowering ( * this , getStackAlignment ( ) ) { if ( ! isPositionIndependent ( ) ) setPICStyle ( PICStyles :: None ) ; else if ( is64Bit ( ) ) setPICStyle ( PICStyles :: RIPRel ) ; else if ( isTargetCOFF ( ) ) setPICStyle ( PICStyles :: None ) ; else if ( isTargetDarwin ( ) ) setPICStyle


<s> assert ( Amt < <NUM_LIT> && <STR_LIT> ) ; return ( Val >> Amt ) | ( Val << ( (


<s> EmitValue ( PersonalityRef , <NUM_LIT> ) ; } assert ( ( Opcodes . size ( ) % <NUM_LIT> ) == <NUM_LIT> && <STR_LIT> ) ; for ( unsigned I = <NUM_LIT> ; I != Opcodes . size ( ) ; I += <NUM_LIT> ) { uint64_t Intval = Opcodes [ I ] | Opcodes [ I + <NUM_LIT> ] << <NUM_LIT> | Opcodes [ I + <NUM_LIT> ] << <NUM_LIT> | Opcodes [ I + <NUM_LIT> ] << <NUM_LIT> ; EmitIntValue ( Intval , <NUM_LIT> ) ; } if ( NoHandlerData && ! Personality ) EmitIntValue ( <NUM_LIT> ,


<s> auto NumeratorScaled = B . buildIntrinsic ( <STR_LIT> , { S32 , S1 } , false ) . addUse ( LHS ) . addUse ( RHS ) . addUse ( LHS ) . setMIFlags ( Flags ) ; auto ApproxRcp = B . buildIntrinsic ( <STR_LIT> , { S32 } , false ) . addUse ( DenominatorScaled . getReg ( <NUM_LIT> ) ) . setMIFlags ( Flags ) ; auto NegDivScale0 = B . buildFNeg ( S32 , DenominatorScaled , Flags ) ; if ( ! Mode . FP32Denormals ) toggleSPDenormMode ( true , B , ST , Mode ) ; auto Fma0 = B . buildFMA ( S32 , NegDivScale0 , ApproxRcp , One , Flags ) ; auto Fma1 = B . buildFMA ( S32 , Fma0 , ApproxRcp , ApproxRcp , Flags ) ; auto Mul = B . buildFMul ( S32 , NumeratorScaled , Fma1 , Flags ) ; auto Fma2 = B . buildFMA ( S32 , NegDivScale0 , Mul , NumeratorScaled , Flags ) ; auto Fma3 = B . buildFMA ( S32 , Fma2 , Fma1 , Mul , Flags ) ; auto Fma4 = B . buildFMA ( S32 , NegDivScale0 , Fma3 , NumeratorScaled , Flags ) ; if ( ! Mode . FP32Denormals ) toggleSPDenormMode ( false , B , ST


<s> case SFmode : return gen_aarch64_rsqrts_sf3 ; case V2DFmode : return gen_aarch64_rsqrts_v2df3 ; case V2SFmode : return


<s> return <STR_LIT> ; case CmpInst :: FCMP_ORD : return <STR_LIT> ; case CmpInst :: FCMP_UNO : return <STR_LIT> ; case CmpInst :: FCMP_UGE : return <STR_LIT> ; case CmpInst :: ICMP_SLT : case CmpInst :: FCMP_ULT : return <STR_LIT> ; case CmpInst :: ICMP_SLE : case CmpInst :: FCMP_ULE : return <STR_LIT> ; case CmpInst :: FCMP_UNE : case CmpInst :: ICMP_NE : return <STR_LIT>


<s> } else { rtx tmp ; emit_insn ( gen_load_tp_soft ( ) ) ; tmp = gen_rtx_REG ( SImode


<s> WeakRefDirective = <STR_LIT> ; PCSymbol = <STR_LIT> ; HasLEB128 = true ; SupportsDebugInformation = true ; ExceptionsType = ExceptionHandling :: DwarfCFI ; if ( T . getOS ( ) == Triple :: OpenBSD && T . getArch

( ) == Triple :: x86 ) Data64bitsDirective = <NUM_LIT> ;


<s> if ( DEBUGME ) { errs ( ) << <STR_LIT> ; } loopInfo = CFGTraits :: getLoopInfo ( pass ) ; if ( DEBUGME ) { errs ( ) << <STR_LIT> ; PrintLoopinfo ( * loopInfo , errs ( ) ) ; } orderBlocks ( ) ; if ( DEBUGME ) { errs ( ) << <STR_LIT> ; printOrderedBlocks ( errs ( ) ) ; } SmallVector < BlockT * , DEFAULT_VEC_SLOTS > retBlks ; for ( typename LoopInfoT :: iterator iter = loopInfo -> begin ( ) , iterEnd = loopInfo -> end ( ) ; iter != iterEnd ; ++ iter ) { LoopT * loopRep = ( * iter ) ; BlockTSmallerVector exitingBlks ; loopRep -> getExitingBlocks


<s> BB != BB_E ; ++ BB ) { MachineBasicBlock & MBB = * BB ; MachineBasicBlock :: iterator I = MBB . begin ( ) ; if ( I != MBB . end ( ) && I -> getOpcode ( ) == <STR_LIT> ) continue ; for ( MachineBasicBlock :: iterator E = MBB . end ( ) ; I != E ; ) { if ( isALU ( * I ) ) I = MakeALUClause ( MBB , I ) ; else ++


<s> const MachineOperand & DispSpec = MI -> getOperand ( Op + <NUM_LIT> ) ; bool HasBaseReg = BaseReg . getReg ( ) != <NUM_LIT> ; if ( HasBaseReg && Modifier && ! strcmp ( Modifier , <STR_LIT> ) && BaseReg . getReg ( ) == <STR_LIT> ) HasBaseReg = false ; bool HasParenPart = IndexReg . getReg ( ) || HasBaseReg ; if ( DispSpec . isImm ( ) ) { int DispVal = DispSpec . getImm ( ) ; if ( DispVal || ! HasParenPart ) O << DispVal ; } else { assert ( DispSpec . isGlobal ( ) || DispSpec . isCPI ( ) || DispSpec . isJTI ( ) || DispSpec . isSymbol ( ) ) ; printSymbolOperand ( MI -> getOperand ( Op + <NUM_LIT> ) ) ; } if ( HasParenPart ) { assert ( IndexReg . getReg ( ) != <STR_LIT> && <STR_LIT> ) ; O << '(' ; if ( HasBaseReg ) printOperand ( MI , Op , Modifier ) ; if ( IndexReg . getReg ( ) ) { O << ',' ; printOperand ( MI , Op


<s> bool <ISA_LIT>RegisterInfo :: trackLivenessAfterRegAlloc ( const MachineFunction & MF


<s> switch ( FixupKind ) { case FK_PCRel_4 : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return COFF :: IMAGE_REL_AMD64_REL32 ; case FK_Data_4 : case <STR_LIT> : case <STR_LIT> : if ( Modifier == MCSymbolRefExpr :: VK_COFF_IMGREL32 ) return COFF :: IMAGE_REL_AMD64_ADDR32NB ; if ( Modifier == MCSymbolRefExpr :: VK_SECREL ) return COFF :: IMAGE_REL_AMD64_SECREL ; return COFF :: IMAGE_REL_AMD64_ADDR32 ; case FK_Data_8 : return COFF :: IMAGE_REL_AMD64_ADDR64 ; case FK_SecRel_2 : return COFF :: IMAGE_REL_AMD64_SECTION ; case FK_SecRel_4 : return COFF :: IMAGE_REL_AMD64_SECREL ; default : llvm_unreachable ( <STR_LIT> ) ; } } else if ( getMachine ( ) == COFF :: IMAGE_FILE_MACHINE_I386 ) { switch ( FixupKind


<s> if ( opCanUseLiteralConstant ( OpType ) ) return true ; return OpType == AMDGPU ::


<s> bool <ISA_LIT>BitSimplify :: replaceSubWithSub ( unsigned OldR , unsigned OldSR , unsigned NewR , unsigned NewSR , MachineRegisterInfo & MRI ) { if ( ! TargetRegisterInfo :: isVirtualRegister ( OldR ) || ! TargetRegisterInfo :: isVirtualRegister ( NewR ) ) return false ; auto Begin = MRI . use_begin ( OldR ) , End = MRI . use_end ( ) ; decltype ( End ) NextI ; for ( auto I = Begin ; I !=


<s> Opc = IsASHR ? <STR_LIT> : <STR_LIT> ; NegOpc = <STR_LIT> ; } else if ( Ty == LLT :: vector ( <NUM_LIT> , <NUM_LIT> ) ) { Opc = IsASHR ? <STR_LIT> : <STR_LIT> ; NegOpc = <STR_LIT> ; } else if ( Ty == LLT :: vector ( <NUM_LIT> , <NUM_LIT> ) ) { Opc = IsASHR ? <STR_LIT> : <STR_LIT> ; NegOpc = <STR_LIT> ; } else if ( Ty == LLT :: vector ( <NUM_LIT> , <NUM_LIT> ) ) { Opc = IsASHR ? <STR_LIT> : <STR_LIT> ; NegOpc = <STR_LIT> ; } else if ( Ty == LLT :: vector ( <NUM_LIT> , <NUM_LIT> ) ) { Opc = IsASHR ? <STR_LIT> : <STR_LIT> ; NegOpc = <STR_LIT> ; } else if ( Ty == LLT :: vector ( <NUM_LIT> , <NUM_LIT> ) ) { Opc = IsASHR ? <STR_LIT> : <STR_LIT> ; NegOpc = <STR_LIT>


<s> int64_t Value2 = Value >> <NUM_LIT> ; if ( ( ( Value & ( int64_t ) maskTrailingZeros < uint64_t > ( <NUM_LIT> ) ) == Value ) && ( ( Value2 >= <NUM_LIT> && Value2 <= <NUM_LIT> ) || ( Value2 >= - <NUM_LIT> && Value2 <= - <NUM_LIT> ) ) ) return true ; return false


<s> SDValue <ISA_LIT>TargetLowering :: LowerBlockAddress ( SDValue Op , SelectionDAG & DAG ) const { BlockAddressSDNode * BA = cast < BlockAddressSDNode > ( Op ) ; if ( getTargetMachine ( ) . getCodeModel ( ) == CodeModel :: Large && ! Subtarget -> isTargetMachO ( ) ) { return getAddrLarge ( BA , DAG ) ; } else


<s> return __builtin_mve_vcmpleq_m_sv4si ( __a ,


<s> B . buildTrunc ( OrigRegs [ <NUM_LIT> ] , Widened ) ; } return ; } if ( LLTy . isVector ( ) && PartLLT . isVector ( ) ) { assert ( OrigRegs . size ( ) == <NUM_LIT> ) ; assert ( LLTy . getElementType ( ) == PartLLT . getElementType ( ) ) ; mergeVectorRegsToResultRegs ( B , OrigRegs , Regs ) ; return ; } assert ( LLTy . isVector ( ) && ! PartLLT . isVector ( ) ) ; LLT DstEltTy = LLTy . getElementType ( ) ; LLT RealDstEltTy = MRI . getType ( OrigRegs [ <NUM_LIT> ] ) . getElementType ( ) ; assert ( DstEltTy . getSizeInBits ( ) == RealDstEltTy . getSizeInBits ( ) ) ; if ( DstEltTy == PartLLT ) { if ( RealDstEltTy . isPointer ( ) ) { for ( Register Reg : Regs ) MRI . setType ( Reg , RealDstEltTy ) ; } B . buildBuildVector ( OrigRegs [ <NUM_LIT> ] , Regs ) ; } else if ( DstEltTy . getSizeInBits ( ) > PartLLT . getSizeInBits ( ) ) { SmallVector < Register , <NUM_LIT> > EltMerges ; int PartsPerElt = DstEltTy . getSizeInBits ( ) / PartLLT . getSizeInBits ( ) ; assert ( DstEltTy . getSizeInBits ( ) % PartLLT . getSizeInBits ( ) == <NUM_LIT> ) ; for ( int I = <NUM_LIT> , NumElts = LLTy . getNumElements ( ) ; I != NumElts ; ++ I ) { auto Merge = B . buildMerge ( RealDstEltTy , Regs . take_front ( PartsPerElt ) ) ; MRI . setType ( Merge . getReg ( <NUM_LIT> ) , RealDstEltTy ) ; EltMerges . push_back ( Merge .


<s> if ( SyntaxVariant == <NUM_LIT> ) return new <ISA_LIT>InstPrinter ( MAI


<s> __vector signed short w ; w = ( __vector signed short ) vec_splats ( __w ) ; return ( __builtin_unpack_vector_int128 ( ( __vector __int128_t ) w , <NUM_LIT> ) ) ; __m64_union res


<s> void ConvergingVLIWScheduler :: schedNode ( SUnit * SU , bool IsTopNode ) { if ( IsTopNode ) { Top . bumpNode (


<s> if ( MO . isImplicit ( ) ) break ; return MCOperand :: CreateReg ( MO . getReg ( ) ) ; case MachineOperand :: MO_Immediate : return MCOperand :: CreateImm ( MO . getImm ( ) + offset ) ; case MachineOperand :: MO_MachineBasicBlock : case MachineOperand :: MO_GlobalAddress : case MachineOperand ::


<s> __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT> ( b ) , <STR_LIT> ( c ) : ) ; return result


<s> s390_expand_cs_tdsi ( mode , btarget , vtarget , mem , cmp , new_rtx , is_weak ) ; break ; case HImode : case QImode : s390_expand_cs_hqi ( mode , btarget , vtarget , mem , cmp , new_rtx , is_weak ) ; break ; default : gcc_unreachable (


<s> SDValue Chain = Op . getOperand ( <NUM_LIT> ) ; SDValue Size = Op . getOperand ( <NUM_LIT> ) ; SDValue Words = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Size , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDValue Flag ; Chain = DAG . getCopyToReg ( Chain , DL , <STR_LIT> , Words , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; SDVTList NodeTys = DAG . getVTList (


<s> if ( Subtarget . getTargetTriple ( ) . isOSMSVCRT ( ) ) return M . getFunction ( <STR_LIT> ) ; return TargetLowering :: getSSPStackGuardCheck (


<s> if ( RetVT != <STR_LIT> && RetVT != <STR_LIT> ) return false ; bool UseImm = false ; if ( const auto * CFP = dyn_cast < ConstantFP > ( RHS ) ) if ( CFP -> isZero ( ) && ! CFP -> isNegative ( ) ) UseImm = true ; Register LHSReg = getRegForValue ( LHS ) ; if ( ! LHSReg ) return false ; if ( UseImm ) { unsigned Opc = ( RetVT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) ) . addReg ( LHSReg ) ; return true ; } Register RHSReg = getRegForValue ( RHS


<s> if ( MI . isInlineAsm ( ) ) return MJ . isInlineAsm ( ) || MJ . isBranch ( ) || MJ . isBarrier ( ) || MJ . isCall ( ) || MJ . isTerminator ( ) ; switch ( MI . getOpcode ( ) ) { case ( <STR_LIT> ) : case ( <STR_LIT> ) : case ( <STR_LIT> ) : case ( <STR_LIT>


<s> O << markup ( <STR_LIT> ) << <STR_LIT> << formatImm ( MI -> getOperand ( OpNum

) . getImm ( ) * <NUM_LIT> ) << markup ( <STR_LIT> ) ;


<s> DEBUG ( dbgs ( ) << <STR_LIT> ) ; TII = MF . getTarget ( ) . getInstrInfo


<s> virtual const char * getPassName ( ) const { return <STR_LIT>


<s> static void ReadByValArg ( MachineFunction & MF , SDValue Chain , DebugLoc dl , std :: vector < SDValue > & OutChains , SelectionDAG & DAG , unsigned NumWords , SDValue FIN , const CCValAssign & VA , const <STR_LIT> & Flags ) { unsigned LocMem = VA . getLocMemOffset ( ) ; unsigned FirstWord = LocMem / <NUM_LIT> ; for ( unsigned i = <NUM_LIT> ; i < NumWords ; ++ i ) { unsigned CurWord = FirstWord + i ; if ( CurWord >= O32IntRegsSize ) break ; unsigned SrcReg = O32IntRegs [


<s> static void mips_emit_binary ( enum rtx_code code , rtx target , rtx op0 , rtx


<s> MVT VT = Op . getSimpleValueType ( ) ; SDLoc DL ( Op ) ; SDValue R = Op . getOperand ( <NUM_LIT> ) ; SDValue Amt = Op . getOperand ( <NUM_LIT> ) ; assert ( VT . isVector ( ) && <STR_LIT> ) ; assert ( Subtarget -> hasXOP ( ) && <STR_LIT> ) ; assert ( ( Op . getOpcode ( ) == <STR_LIT> ) && <STR_LIT> ) ; if ( VT . getSizeInBits ( ) == <NUM_LIT> ) return Lower256IntArith ( Op , DAG ) ; assert ( VT . getSizeInBits ( ) == <NUM_LIT> && <STR_LIT> ) ; if ( auto * BVAmt = dyn_cast < BuildVectorSDNode > ( Amt ) ) { if ( auto * RotateConst = BVAmt -> getConstantSplatNode (


<s> for ( auto R : Regions ) { if ( R -> MaxPressure . getOccupancy ( ST ) >= NewOcc ) break ; DEBUG ( printRegion ( dbgs ( ) , R -> Begin , R -> End , LIS , <NUM_LIT> ) ; printLivenessInfo ( dbgs ( ) , R -> Begin , R -> End , LIS ) ) ; BuildDAG DAG ( * R , * this ) ; const auto MinSchedule = makeMinRegSchedule ( DAG . getTopRoots ( ) , *


<s> Builder . addExtension ( PassManagerBuilder :: EP_ModuleOptimizerEarly , [ & ] ( const PassManagerBuilder & , legacy :: PassManagerBase & PM ) { PM . add ( create<ISA_LIT>UnifyMetadataPass ( )


<s> } assert ( VTList . NumVTs == <NUM_LIT> ) ; SDVTList WidenedVTList = DAG . getVTList ( WidenedVT , VTList . VTs [ <NUM_LIT> ] ) ; auto NewOp = DAG . getMemIntrinsicNode ( Opcode , DL , WidenedVTList , Ops , WidenedMemVT , MMO ) ; if ( WidenedVT != VT ) { auto Extract = DAG . getNode ( <STR_LIT> , DL , VT ,

NewOp , DAG . getVectorIdxConstant ( <NUM_LIT> , DL ) ) ;


<s> bool <ISA_LIT>TargetLowering :: canReuseLoadAddress ( SDValue Op , EVT MemVT , ReuseLoadInfo & RLI , SelectionDAG & DAG , <STR_LIT> ET ) const { if ( Op -> isStrictFPOpcode ( ) ) return false ; SDLoc dl ( Op ) ; bool ValidFPToUint = Op . getOpcode ( ) == <STR_LIT> && ( Subtarget . hasFPCVT ( ) || Op . getValueType ( ) == <STR_LIT> ) ; if ( ET == <STR_LIT> && ( ValidFPToUint || Op . getOpcode ( ) == <STR_LIT> ) && isOperationLegalOrCustom ( Op . getOpcode ( ) , Op . getOperand ( <NUM_LIT> ) . getValueType ( ) ) ) { LowerFP_TO_INTForReuse ( Op , RLI , DAG , dl ) ; return true ; } LoadSDNode * LD = dyn_cast < LoadSDNode > ( Op ) ; if ( ! LD || LD -> getExtensionType ( ) != ET || LD

-> isVolatile ( ) || LD -> isNonTemporal ( ) ) return false ;


<s> if ( ! Root . isReg ( ) ) return None ; MachineRegisterInfo & MRI = Root . getParent ( ) -> getParent ( ) -> getParent ( ) -> getRegInfo ( ) ; MachineInstr * ShiftInst = MRI . getVRegDef ( Root . getReg ( ) ) ; if ( ! ShiftInst ) return None ; <STR_LIT> ShType = getShiftTypeForInst ( * ShiftInst ) ; if ( ShType == <STR_LIT> ) return None ; if ( ! isWorthFoldingIntoExtendedReg ( * ShiftInst , MRI ) ) return None ; MachineOperand & ShiftRHS = ShiftInst -> getOperand ( <NUM_LIT> ) ; auto Immed = getImmedFromMO ( ShiftRHS ) ; if ( ! Immed ) return None ; MachineOperand & ShiftLHS = ShiftInst -> getOperand ( <NUM_LIT> ) ; Register ShiftReg = ShiftLHS . getReg ( ) ; unsigned NumBits = MRI . getType ( ShiftReg ) . getSizeInBits


<s> const InstrItineraryData * getInstrItineraryData ( ) const


<s> <ISA_LIT>Operand * Op = new <ISA_LIT>Operand ( k_Register , Ctx ) ; Op -> Reg . RegNum = RegNum ; Op -> Reg . isVector = isVector ; Op -> StartLoc = S ; Op -> EndLoc = E ; return


<s> bool <ISA_LIT>ShortenInst :: shortenSelect ( MachineInstr & MI , unsigned Opcode ) { if ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) == MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) { MI . setDesc ( TII -> get ( Opcode ) ) ; MI . tieOperands (


<s> Value * <ISA_LIT>IREmitter :: visitMEMBARRIER_MCR ( const SDNode * N ) { llvm_unreachable ( <STR_LIT> ) ; return


<s> InstructionSelector :: ComplexRendererFns <ISA_LIT>InstructionSelector :: selectArithImmed ( MachineOperand & Root ) const { auto MaybeImmed = getImmedFromMO ( Root


<s> static SDValue combineShift ( SDNode * N , SelectionDAG & DAG , TargetLowering :: DAGCombinerInfo & DCI , const <ISA_LIT>Subtarget & Subtarget ) { if ( N -> getOpcode ( ) == <STR_LIT> ) if ( SDValue V = combineShiftLeft ( N


<s> if ( model != TLSModel :: LocalDynamic ) return Ret ; SDValue TGAHi = DAG . getTargetGlobalAddress ( GV , DL , PtrVT , <NUM_LIT> , <STR_LIT> ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , DL , PtrVT , TGAHi ) ; SDValue TGALo = DAG . getTargetGlobalAddress ( GV , DL , PtrVT , <NUM_LIT> , <STR_LIT> ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , DL , PtrVT , TGALo ) ; SDValue Add = DAG . getNode ( <STR_LIT> , DL , PtrVT , Hi , Ret ) ; return DAG . getNode ( <STR_LIT> , DL , PtrVT , Add , Lo ) ; } SDValue Offset ; if ( model == TLSModel :: InitialExec ) { SDValue TGA = DAG . getTargetGlobalAddress ( GV , DL , PtrVT , <NUM_LIT> , <STR_LIT> ) ; TGA = DAG . getNode ( <STR_LIT> , DL , PtrVT , getGlobalReg ( DAG , PtrVT ) , TGA ) ; Offset = DAG . getLoad ( PtrVT , DL , DAG . getEntryNode ( ) , TGA , MachinePointerInfo ( ) , false , false , false , <NUM_LIT> ) ; } else


<s> LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << MBB


<s> __builtin_ia32_pmovusdb512mem_mask ( ( __v16qi * ) __P , (


<s> unsigned DstReg = Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned SrcReg = Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned TmpReg = Inst . getOperand ( <NUM_LIT> )


<s> BuildMI ( & MBB , DL , TII -> get ( <STR_LIT> ) ) . addMBB ( & NextBB ) ; MachineBasicBlock :: iterator Insert = SkipBB -> begin ( ) ; BuildMI ( * SkipBB , Insert , DL , TII -> get ( <STR_LIT> ) ) . addImm ( <NUM_LIT> ) . addReg ( <STR_LIT> , RegState :: Undef ) . addReg ( <STR_LIT> , RegState :: Undef ) . addReg ( <STR_LIT> , RegState :: Undef ) . addReg ( <STR_LIT> , RegState :: Undef ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; BuildMI ( * SkipBB , Insert , DL , TII -> get


<s> } for ( auto I = MRI -> use_nodbg_begin ( Reg ) , E = MRI -> use_nodbg_end ( ) ; I != E ; ++ I ) { auto * UseMI = I -> getParent ( ) ; if ( UseMI -> isPHI ( ) && I -> readsReg ( ) ) { if ( Visited . contains ( UseMI -> getParent ( ) ) ) PHIIncoming . insert ( UseMI -> getOperand ( I . getOperandNo ( ) + <NUM_LIT> ) . getMBB ( ) ) ; } } Visited . clear ( ) ; for ( MachineBasicBlock * MBB : depth_first_ext ( ThenEntry , Visited ) ) { if ( MBB == Flow ) break ; SmallVector < MachineInstr * > Uses ; findNonPHIUsesInBlock ( Reg , MBB , Uses ) ; if ( Uses . size ( ) == <NUM_LIT> ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << printMBBReference ( * MBB ) << '\n'


<s> static __inline vec_uchar16 spu_cntb ( vec_char16 a ) { return ( ( vec_uchar16 ) ( si_cntb ( (


<s> SDValue <ISA_LIT>TargetLowering :: EmitOffset ( int64_t Amount , const SDLoc & DL , SDValue


<s> if ( parseRegisterInRange ( Reg , <STR_LIT> , <STR_LIT> , <STR_LIT> ) || parseComma ( )

|| parseImmExpr ( Offset ) ) return true ;


<s> return & darwin64Offsets ; } else { static const SpillSlot darwinOffsets = { <STR_LIT> , - <NUM_LIT> } ; return & darwinOffsets ; } } if ( ! Subtarget . isSVR4ABI ( ) ) { NumEntries = <NUM_LIT> ; return nullptr ; } static const SpillSlot Offsets [ ] = { { <STR_LIT> , - <NUM_LIT> } , { <STR_LIT> , - <NUM_LIT> } , { <STR_LIT> , - <NUM_LIT> } , { <STR_LIT> , - <NUM_LIT> } , { <STR_LIT> , - <NUM_LIT> } , { <STR_LIT> , - <NUM_LIT> } , { <STR_LIT> , - <NUM_LIT> } , { <STR_LIT> , - <NUM_LIT> } , { <STR_LIT> , - <NUM_LIT> } , { <STR_LIT> , - <NUM_LIT> } , { <STR_LIT> , - <NUM_LIT> } , { <STR_LIT> , - <NUM_LIT> } , { <STR_LIT> , - <NUM_LIT> } , { <STR_LIT> , - <NUM_LIT> } , { <STR_LIT> , - <NUM_LIT> } , { <STR_LIT> , - <NUM_LIT> } , { <STR_LIT> , - <NUM_LIT> } , { <STR_LIT> , - <NUM_LIT> } , { <STR_LIT> , - <NUM_LIT> } , { <STR_LIT> , - <NUM_LIT> } , { <STR_LIT> , - <NUM_LIT> } , { <STR_LIT> , - <NUM_LIT> } , { <STR_LIT> , - <NUM_LIT> } , { <STR_LIT> , - <NUM_LIT> } , { <STR_LIT> , - <NUM_LIT> } , { <STR_LIT> , - <NUM_LIT> } , { <STR_LIT> , - <NUM_LIT> } , { <STR_LIT> , - <NUM_LIT> } , { <STR_LIT> , - <NUM_LIT> } , { <STR_LIT> , - <NUM_LIT> } , { <STR_LIT> , - <NUM_LIT> } , { <STR_LIT> , - <NUM_LIT> } , { <STR_LIT> , - <NUM_LIT> } , { <STR_LIT> , - <NUM_LIT> } , { <STR_LIT> , - <NUM_LIT> } , { <STR_LIT> , - <NUM_LIT> } , { <STR_LIT> , - <NUM_LIT> } , { <STR_LIT> , - <NUM_LIT> } , { <STR_LIT> , - <NUM_LIT> } , { <STR_LIT> , - <NUM_LIT> } , { <STR_LIT> , - <NUM_LIT> } , { <STR_LIT> , - <NUM_LIT> } , { <STR_LIT> , - <NUM_LIT> } , { <STR_LIT> , - <NUM_LIT> } , { <STR_LIT> , - <NUM_LIT> } , { <STR_LIT> , - <NUM_LIT> } , { <STR_LIT> , - <NUM_LIT> } , { <STR_LIT> , - <NUM_LIT> } , { <STR_LIT> , - <NUM_LIT> } , { <STR_LIT> , - <NUM_LIT> } } ; static const SpillSlot Offsets64 [


<s> Instruction * <ISA_LIT>EmitIntrinsics :: visitInsertValueInst ( InsertValueInst & I ) { SmallVector < Type * , <NUM_LIT> > Types = { I . getInsertedValueOperand ( ) -> getType ( ) } ; SmallVector < Value * > Args ; for ( auto & Op : I . operands ( ) ) if ( isa < UndefValue > ( Op ) ) Args . push_back ( UndefValue :: get ( IRB -> getInt32Ty ( ) ) ) ; else Args . push_back ( Op ) ; for ( auto & Op : I . indices ( ) ) Args . push_back ( IRB ->


<s> LLT S64 = LLT :: scalar ( <NUM_LIT> ) ; if ( DstTy == S16 ) return legalizeFDIV16 ( MI , MRI , B ) ; if ( DstTy == S32 ) return legalizeFDIV32 ( MI , MRI , B ) ; if ( DstTy == S64 ) return legalizeFDIV64 ( MI , MRI


<s> SDValue TFI = CurDAG -> getTargetFrameIndex ( FI , N -> getValueType ( <NUM_LIT> ) ) ; unsigned Opc = N -> getValueType ( <NUM_LIT> ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; if ( SN -> hasOneUse ( ) ) CurDAG -> SelectNodeTo ( SN , Opc , N ->

getValueType ( <NUM_LIT> ) , TFI , getSmallIPtrImm ( Offset , dl ) ) ;


<s> op12 = gen_rtx_CONST ( HImode , op12 ) ; } else { op10 = msp430_subreg ( HImode , operands [ <NUM_LIT> ] , SImode , <NUM_LIT> ) ; op12 = msp430_subreg ( HImode , operands [ <NUM_LIT> ] , SImode , <NUM_LIT> ) ; } if ( rtx_equal_p ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ) { operands [ <NUM_LIT> ] = op02 ; operands [ <NUM_LIT> ] = op12 ; operands [ <NUM_LIT> ] = op00 ; operands [ <NUM_LIT> ] = op10 ; } else if ( rtx_equal_p ( op00 , op12 ) || ( REG_P ( op00 ) && reg_mentioned_p ( op00 , op10 ) ) || ( REG_P ( op10 ) && reg_mentioned_p ( op10 , op00 ) ) ) { operands [ <NUM_LIT> ]


<s> limitOccupancy ( ST . getOccupancyWithLocalMemSize ( getLDSSize ( ) , MF . getFunction (


<s> void addNEONi16splatOperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT> ) ; const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; unsigned Value = CE -> getValue


<s> unsigned DestReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; const <ISA_LIT>InstrInfo * TII = ST . getInstrInfo ( ) ; MachineRegisterInfo & MRI = MBB -> getParent ( ) -> getRegInfo ( ) ; unsigned TempGPR32 = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * MBB , ++ II , DL , TII -> get ( <STR_LIT> ) , DestReg ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( BRIG_TYPE_B1 ) . addImm ( BRIG_TYPE_U32 ) . addReg ( TempGPR32 , RegState :: Kill ) ; MI . setDesc ( TII -> get ( <STR_LIT> ) ) ; MI . getOperand ( <NUM_LIT> ) . setReg ( TempGPR32 ) ; MI . getOperand ( <NUM_LIT> ) . setIsDef ( ) ; MachineOperand * TypeOp = TII -> getNamedOperand ( MI , <STR_LIT> ::


<s> unsigned <ISA_LIT>InstrInfo :: getUndefRegClearance ( const MachineInstr & MI , unsigned & OpNum , const TargetRegisterInfo * TRI ) const { if ( ! hasUndefRegUpdate ( MI . getOpcode ( ) , OpNum ) ) return <NUM_LIT> ; const MachineOperand & MO = MI . getOperand ( OpNum ) ; if ( MO . isUndef ( ) && Register :: isPhysicalRegister ( MO . getReg ( ) ) ) { return UndefRegClearance ; } return <NUM_LIT>


<s> return BuildMI ( * I . getParent ( ) , I , I . getDebugLoc ( ) , TII . get ( <STR_LIT> ) ) . addDef ( ResVReg ) . addUse (

GR . get<ISA_LIT>TypeID ( ResType ) ) . addImm ( static_cast < uint32_t > ( <STR_LIT> :: Function ) ) . constrainAllUses ( TII , TRI , RBI ) ;


<s> if ( OptLevel != CodeGenOpt :: None && ! DisableIfConversion && ! Subtarget . isThumb ( ) )

PM . add ( createIfConverterPass ( ) ) ;


<s> switch ( MI . getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true


<s> if ( TM -> getOptLevel ( ) != CodeGenOpt :: None ) addPass ( createGlobalMergePass ( TM ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None ) addPass ( create<ISA_LIT>AddressTypePromotionPass ( ) ) ; addPass ( createAtomicExpandLoadLinkedPass ( TM


<s> unsigned <ISA_LIT>MachineFunctionInfo :: getGlobalBaseReg ( ) { return GlobalBaseReg =


<s> bool SPRRegs = <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( Reg ) ; bool DPRRegs = <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( Reg ) ; unsigned Binary = <NUM_LIT> ; if ( SPRRegs || DPRRegs ) { unsigned RegNo = CTX . getRegisterInfo ( ) -> getEncodingValue ( Reg ) ; unsigned NumRegs = ( MI . getNumOperands ( ) - Op ) & <NUM_LIT> ; Binary |= ( RegNo & <NUM_LIT> ) << <NUM_LIT> ; if ( SPRRegs ) Binary |= NumRegs


<s> if ( Options . EABIVersion == EABI :: Default || Options . EABIVersion == EABI :: Unknown ) { if ( ( TargetTriple . getEnvironment ( ) == Triple :: GNUEABI || TargetTriple . getEnvironment ( ) == Triple :: GNUEABIHF || TargetTriple . getEnvironment ( ) == Triple :: MuslEABI || TargetTriple . getEnvironment ( ) == Triple :: MuslEABIHF ) && ! ( TargetTriple . isOSWindows ( ) || TargetTriple . isOSDarwin ( ) ) ) this -> Options . EABIVersion = EABI :: GNU ; else this -> Options . EABIVersion =


<s> <ISA_LIT>TargetStreamer & getTargetStreamer ( ) { MCTargetStreamer & TS = * getParser ( )

. getStreamer ( ) . getTargetStreamer ( ) ;


<s> Symbols . push_back ( GVar ) ; numSymbols ++


<s> DebugLoc DL = MI . getDebugLoc ( ) ; unsigned Reg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Vcc = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; BuildMI ( MBB , & MI , DL , TII -> get ( <STR_LIT> ) , Reg ) . addReg ( Vcc ) ; BuildMI ( MBB , & MI , DL , TII -> get ( <STR_LIT> ) , Reg ) . addReg ( <STR_LIT> ) . addReg ( Reg ) ; Skip ( MI , MI . getOperand


<s> if ( TM . getCodeModel ( ) == CodeModel :: Small || ! ObjType -> isSized ( ) || DL . getTypeAllocSize ( ObjType ) < CodeModelLargeSize ) { if ( Kind . isReadOnly ( ) ) return UseCPRel ? ReadOnlySection : DataRelROSection ; if ( Kind . isBSS ( ) || Kind . isCommon ( ) ) return BSSSection ; if ( Kind . isData ( ) ) return DataSection ; if ( Kind . isReadOnlyWithRel ( ) ) return DataRelROSection ; } else { if ( Kind . isReadOnly ( ) ) return UseCPRel ? ReadOnlySectionLarge : DataRelROSectionLarge ; if ( Kind . isBSS ( ) || Kind . isCommon ( ) ) return BSSSectionLarge ; if ( Kind . isData ( ) ) return DataSectionLarge ; if ( Kind . isReadOnlyWithRel ( ) ) return DataRelROSectionLarge ; } assert ( ( Kind . isThreadLocal ( ) || Kind . isCommon ( ) ) && <STR_LIT> ) ; report_fatal_error ( <STR_LIT> )


<s> break ; case AARCH64_PARSE_INVALID_ARG : error ( <STR_LIT> , str ) ; aarch64_print_hint_for_core ( str ) ; break ; case AARCH64_PARSE_INVALID_FEATURE : error ( <STR_LIT> , invalid_extension . c_str ( ) , str ) ; aarch64_print_hint_for_extensions ( invalid_extension ) ; break ; default : gcc_unreachable (


<s> unsigned Offset = Fixup . getOffset ( ) ; for ( unsigned i = <NUM_LIT> ; i != <NUM_LIT> ; ++ i ) { unsigned Idx = IsLittleEndian ?


<s> MachineFunction & MF = * MBB . getParent ( ) ; MachineFrameInfo & MFI = * MF . getFrameInfo ( ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( FrameIdx ) , MachineMemOperand :: MOLoad , MFI . getObjectSize ( FrameIdx ) , MFI . getObjectAlignment ( FrameIdx ) ) ; if ( RC == & <STR_LIT> ) BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) ) . addReg ( DestReg ) . addFrameIndex ( FrameIdx ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ; else if ( RC == & <STR_LIT> ) BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) ) .


<s> bool Changed = false ; CRLogicalOpInfo CRI = AllCRLogicalOps [ Idx ] ; if ( CRI . IsBinary && CRI . ContainedInBlock && CRI . SingleUse && CRI . FeedsBR && CRI . DefsSingleUse ) { Changed = splitBlockOnBinaryCROp ( CRI ) ; if ( Changed ) NumBlocksSplitOnBinaryCROp ++ ; } return


<s> static MCInstrInfo * create<ISA_LIT>MCInstrInfo ( ) { MCInstrInfo * X = new MCInstrInfo ( ) ; Init<ISA_LIT>MCInstrInfo ( X ) ; return X


<s> Align Alignment = DL . getPrefTypeAlign ( CFP -> getType ( ) ) ; unsigned Idx = MCP . getConstantPoolIndex ( cast < Constant > ( CFP ) , Alignment ) ; const bool HasSPE = Subtarget -> hasSPE ( ) ; const TargetRegisterClass * RC ; if ( HasSPE ) RC = ( ( VT == <STR_LIT> ) ? & <STR_LIT> : & <STR_LIT> ) ; else RC = ( ( VT == <STR_LIT> ) ? & <STR_LIT> : & <STR_LIT> ) ; unsigned DestReg = createResultReg ( RC ) ; CodeModel :: Model CModel = TM . getCodeModel ( ) ; MachineMemOperand * MMO = FuncInfo . MF -> getMachineMemOperand ( MachinePointerInfo :: getConstantPool ( * FuncInfo . MF ) , MachineMemOperand :: MOLoad , ( VT == <STR_LIT> ) ? <NUM_LIT> : <NUM_LIT> , Alignment ) ; unsigned Opc ; if ( HasSPE ) Opc = ( ( VT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ) ; else Opc = ( ( VT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ) ; unsigned TmpReg = createResultReg ( & <STR_LIT> ) ; <ISA_LIT>FuncInfo -> setUsesTOCBasePtr ( ) ; if ( CModel == CodeModel :: Small ) { BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , TmpReg ) . addConstantPoolIndex ( Idx ) . addReg ( <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , DestReg ) . addImm ( <NUM_LIT> ) . addReg ( TmpReg ) . addMemOperand ( MMO ) ; } else


<s> unsigned <ISA_LIT>InstrInfo :: getInstSizeInBytes ( const MachineInstr & MI ) const { unsigned Opc = MI . getOpcode ( ) ; const MCInstrDesc & Desc = getMCOpcodeFromPseudo ( Opc ) ; unsigned DescSize = Desc . getSize ( ) ; if ( DescSize != <NUM_LIT> && DescSize != <NUM_LIT> ) return DescSize ; if ( isFixedSize ( MI ) ) return DescSize ; if ( isVALU ( MI ) || isSALU ( MI ) ) { int Src0Idx = <STR_LIT> ( Opc , <STR_LIT> :: src0 ) ; if ( Src0Idx == - <NUM_LIT> ) return <NUM_LIT> ; if ( isLiteralConstantLike ( MI . getOperand ( Src0Idx ) , Desc . OpInfo [ Src0Idx ] ) ) return <NUM_LIT> ; int Src1Idx = <STR_LIT> ( Opc , <STR_LIT> :: src1 ) ; if ( Src1Idx == - <NUM_LIT> ) return <NUM_LIT> ; if ( isLiteralConstantLike ( MI . getOperand ( Src1Idx ) , Desc . OpInfo [ Src1Idx ] ) ) return <NUM_LIT> ; return <NUM_LIT> ; } if ( DescSize == <NUM_LIT> ) return <NUM_LIT> ; switch ( Opc ) { case TargetOpcode :: IMPLICIT_DEF : case TargetOpcode :: KILL : case TargetOpcode :: DBG_VALUE : case TargetOpcode :: EH_LABEL : return <NUM_LIT> ; case TargetOpcode


<s> TargetRegistry :: RegisterMCDisassembler ( getThe<ISA_LIT>Target ( ) ,


<s> case Match_InvalidFPImm : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryIndexedSImm9 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryIndexed4SImm7 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryIndexed8SImm7 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryIndexed16SImm7 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryWExtend8 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryWExtend16 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryWExtend32 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryWExtend64 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryWExtend128 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryXExtend8 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryXExtend16 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryXExtend32 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryXExtend64 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryXExtend128 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryIndexed1 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryIndexed2 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryIndexed4 : return Error ( Loc , <STR_LIT> ) ; case


<s> bool <ISA_LIT>TargetLowering :: mayBeEmittedAsTailCall ( CallInst * CI ) const { if ( ! Subtarget -> supportsTailCall ( ) ) return false ; auto Attr = CI -> getParent ( ) -> getParent ( ) -> getFnAttribute ( <STR_LIT> ) ; if ( ! CI -> isTailCall ( ) || Attr . getValueAsString ( ) == <STR_LIT> ) return false ; return true


<s> bool isVolatile = ST -> isVolatile ( ) ; bool isNonTemporal = ST -> isNonTemporal ( ) ; Tmp3 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Tmp3 ) ; SDValue Result = DAG . getStore ( Tmp1 , dl , Tmp3 , Tmp2 , ST -> getPointerInfo ( ) , isVolatile , isNonTemporal , Alignment ) ; return Result


<s> unsigned <ISA_LIT>InstrInfo :: isStoreToStackSlot ( const MachineInstr * MI , int & FrameIndex ) const { switch ( MI -> getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : { if ( ( MI -> getOperand ( <NUM_LIT> ) . isFI ( ) ) && ( MI -> getOperand ( <NUM_LIT> ) . isImm ( ) ) && ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) ) { FrameIndex = MI -> getOperand ( <NUM_LIT> ) . getIndex ( ) ; return MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; } break ; } default : break ; } return <NUM_LIT>


<s> bool sh_expand_strlen ( rtx * operands ) { rtx addr1 = operands [ <NUM_LIT> ] ; rtx current_addr = copy_addr_to_reg ( XEXP ( addr1 , <NUM_LIT> ) ) ; rtx start_addr = gen_reg_rtx ( Pmode ) ; rtx tmp0 = gen_reg_rtx ( SImode ) ; rtx tmp1 = gen_reg_rtx ( SImode ) ; rtx_code_label * L_return = gen_label_rtx ( ) ; rtx_code_label * L_loop_byte = gen_label_rtx ( ) ; rtx jump ; rtx_code_label * L_loop_long = gen_label_rtx ( ) ; rtx_code_label * L_end_loop_long = gen_label_rtx ( ) ; int align = INTVAL ( operands [ <NUM_LIT> ] ) ; emit_move_insn ( operands [ <NUM_LIT> ] , GEN_INT ( - <NUM_LIT> ) ) ; emit_move_insn ( start_addr , current_addr ) ; if ( align < <NUM_LIT> ) { emit_insn ( gen_tstsi_t ( current_addr , GEN_INT ( <NUM_LIT> ) ) ) ; jump = emit_jump_insn ( gen_branch_false ( L_loop_byte ) ) ; add_int_reg_note ( jump , REG_BR_PROB , prob_likely ) ; } emit_move_insn ( tmp0 , operands [ <NUM_LIT> ] ) ; addr1 = adjust_automodify_address ( addr1 , SImode , current_addr , <NUM_LIT> ) ; emit_label ( L_loop_long ) ; emit_move_insn ( tmp1 , addr1 ) ; emit_move_insn ( current_addr , plus_constant ( Pmode , current_addr , <NUM_LIT> ) ) ; emit_insn ( gen_cmpstr_t ( tmp0 , tmp1 ) ) ; jump = emit_jump_insn ( gen_branch_false ( L_loop_long ) ) ; add_int_reg_note ( jump , REG_BR_PROB , prob_likely ) ; emit_label ( L_end_loop_long ) ; emit_move_insn ( current_addr , plus_constant ( Pmode , current_addr , - <NUM_LIT> ) ) ; addr1 = adjust_address ( addr1 , QImode , <NUM_LIT> ) ; for ( int i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) { emit_insn ( gen_extendqisi2 ( tmp1 , addr1 ) ) ; emit_move_insn ( current_addr , plus_constant ( Pmode , current_addr , <NUM_LIT> ) ) ; emit_insn ( gen_cmpeqsi_t ( tmp1 , const0_rtx ) ) ; jump = emit_jump_insn ( gen_branch_true ( L_return ) ) ; add_int_reg_note ( jump , REG_BR_PROB , prob_likely ) ; } emit_barrier_after ( jump ) ; emit_label ( L_loop_byte ) ; emit_insn ( gen_extendqisi2 ( tmp1 , addr1 ) ) ; emit_move_insn ( current_addr , plus_constant ( Pmode , current_addr , <NUM_LIT> ) ) ; emit_insn ( gen_cmpeqsi_t ( tmp1 , const0_rtx ) ) ; jump = emit_jump_insn ( gen_branch_false ( L_loop_byte ) ) ; add_int_reg_note ( jump , REG_BR_PROB , prob_likely ) ; emit_label ( L_return ) ; emit_insn ( gen_addsi3 ( start_addr , start_addr , GEN_INT ( <NUM_LIT> )


<s> static MCStreamer * createMCStreamer ( const Triple & TT , MCContext & Context , std :: unique_ptr < MCAsmBackend > && MAB , std :: unique_ptr < MCObjectWriter > && OW , std :: unique_ptr < MCCodeEmitter > && Emitter , bool RelaxAll ) { return createELFStreamer ( Context , std :: move ( MAB ) , std :: move ( OW ) , std :: move (


<s> FunctionPass * llvm :: create<ISA_LIT>FlagsCopyLoweringPass


<s> if ( TARGET_ALTIVEC && ALTIVEC_VECTOR_MODE ( mode ) && GET_CODE ( x ) == AND && GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == CONST_INT && INTVAL ( XEXP ( x , <NUM_LIT> ) ) == - <NUM_LIT> ) x = XEXP ( x , <NUM_LIT> ) ; if ( RS6000_SYMBOL_REF_TLS_P ( x ) ) return <NUM_LIT> ; if ( legitimate_indirect_address_p ( x , reg_ok_strict ) ) return <NUM_LIT> ; if ( ( GET_CODE ( x ) == PRE_INC || GET_CODE ( x ) == PRE_DEC ) && ! ALTIVEC_VECTOR_MODE ( mode ) && ! SPE_VECTOR_MODE ( mode ) && ! ( TARGET_E500_DOUBLE && ( mode == DFmode || mode == DImode ) ) && TARGET_UPDATE && legitimate_indirect_address_p ( XEXP ( x , <NUM_LIT> ) , reg_ok_strict ) ) return <NUM_LIT> ; if ( rs6000_legitimate_small_data_p ( mode , x ) ) return <NUM_LIT> ; if ( legitimate_constant_pool_address_p ( x


<s> const TargetRegisterClass * RC = MRI . getRegClass ( DstReg ) ; assert ( TRI -> isTypeLegalForClass ( * RC , <STR_LIT> ) && <STR_LIT> ) ; ( void ) TRI ; unsigned mainDstReg = MRI . createVirtualRegister ( RC ) ; unsigned restoreDstReg = MRI . createVirtualRegister ( RC ) ; const BasicBlock * BB = MBB -> getBasicBlock ( ) ; MachineFunction :: iterator It = ++ MBB -> getIterator ( ) ; MachineBasicBlock * thisMBB = MBB ; MachineBasicBlock * mainMBB = MF -> CreateMachineBasicBlock ( BB ) ; MachineBasicBlock * restoreMBB = MF -> CreateMachineBasicBlock ( BB ) ; MachineBasicBlock * sinkMBB = MF -> CreateMachineBasicBlock ( BB ) ; MF -> insert ( It , mainMBB ) ; MF -> insert ( It , restoreMBB ) ; MF -> insert ( It , sinkMBB ) ; restoreMBB -> setHasAddressTaken ( ) ; sinkMBB -> splice ( sinkMBB -> begin ( ) , MBB , std :: next ( MachineBasicBlock :: iterator ( MI ) ) , MBB -> end ( ) ) ; sinkMBB -> transferSuccessorsAndUpdatePHIs ( MBB ) ; unsigned LabelReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; unsigned LabelReg2 = MRI . createVirtualRegister ( & <STR_LIT> ) ; unsigned BufReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; const unsigned FP = <STR_LIT> ; MIB = BuildMI ( thisMBB , DL , TII -> get ( <STR_LIT> ) ) . addReg ( BufReg ) . addImm ( <NUM_LIT> ) . addReg ( FP ) ; MIB = BuildMI ( thisMBB , DL , TII -> get ( <STR_LIT> ) ) . addReg ( LabelReg , RegState :: Define ) . addMBB ( restoreMBB , <ISA_LIT>MCExpr :: VK_<ISA_LIT>_HI ) ; MIB = BuildMI ( thisMBB , DL , TII -> get ( <STR_LIT> ) ) . addReg ( LabelReg2 , RegState :: Define ) . addReg ( LabelReg , RegState :: Kill ) . addMBB ( restoreMBB , <ISA_LIT>MCExpr :: VK_<ISA_LIT>_LO ) ; MIB = BuildMI ( thisMBB , DL , TII -> get ( <STR_LIT> ) ) . addReg ( BufReg ) . addImm ( RegSize ) . addReg ( LabelReg2 , RegState :: Kill ) ; const unsigned <ISA_LIT> = <STR_LIT> ; MIB = BuildMI ( thisMBB , DL , TII -> get ( <STR_LIT> ) ) . addReg ( BufReg ) . addImm ( <NUM_LIT> * RegSize ) . addReg ( <ISA_LIT> ) ; MIB = BuildMI ( thisMBB , DL , TII -> get ( <STR_LIT> ) ) . addReg ( BufReg ) . addImm ( <NUM_LIT> * RegSize ) . addReg ( <STR_LIT> ) ; MIB = BuildMI ( thisMBB , DL , TII -> get ( <STR_LIT> ) ) . addMBB ( restoreMBB ) . addImm ( <STR_LIT> ) ; MIB = BuildMI ( thisMBB , DL , TII -> get ( <STR_LIT> ) ) . addMBB ( mainMBB )


<s> bool is64Bit = T . getArch ( ) == Triple :: ppc64 || T . getArch ( ) == Triple :: ppc64le ; std :: string Ret ; if ( T . getArch ( ) == Triple :: ppc64le ) Ret = <STR_LIT> ; else Ret = <STR_LIT> ; Ret += DataLayout :: getManglingComponent (


<s> DirectXTargetMachine & getDirectXTargetMachine ( ) const { return getTM < DirectXTargetMachine


<s> if ( GET_CODE ( body ) != SET ) return false ; rtx src = SET_SRC ( body ) ; if ( GET_CODE ( src ) != SUBREG ) return false ; rtx inner = XEXP ( src , <NUM_LIT> ) ; return ( GET_CODE ( inner ) ==


<s> const RegisterBank * DstRB = RBI . getRegBank ( DstReg , * MRI , TRI ) ; const bool IsVGPR = DstRB -> getID ( ) == <STR_LIT> ; I . setDesc ( TII . get ( IsVGPR ? <STR_LIT> : <STR_LIT> ) ) ; if ( IsVGPR ) I . addOperand ( * MF , MachineOperand :: CreateReg ( <STR_LIT> , false , true ) ) ; return RBI . constrainGenericRegister ( DstReg , IsVGPR ? <STR_LIT> : <STR_LIT> , *


<s> assert ( FIST . getNode ( ) && <STR_LIT> ) ; if ( StackSlot . getNode ( ) ) return DAG . getLoad ( Op . getValueType ( ) , SDLoc ( Op

) , FIST , StackSlot , MachinePointerInfo ( ) , false , false , false , <NUM_LIT> ) ;


<s> return TargetFrameLowering :: noFramePointerElim ( MF ) || MF . getSubtarget

< <ISA_LIT>Subtarget > ( ) . useFastISel ( ) ;


<s> SDLoc DL ( Op ) ; MVT XLenVT = Subtarget . getXLenVT ( ) ; SDVTList ResultVTs = DAG . getVTList ( XLenVT , XLenVT ) ; return DAG . getNode ( <STR_LIT> , DL , ResultVTs


<s> WhichResult = ( M [ <NUM_LIT> ] == <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ) ; unsigned Idx = WhichResult * NumElts / <NUM_LIT> ; for ( unsigned i = <NUM_LIT> ; i != NumElts ; i += <NUM_LIT> ) { if ( ( M [ i ] >= <NUM_LIT> && ( unsigned ) M [ i ] != Idx ) || ( M [ i + <NUM_LIT> ] >= <NUM_LIT> && ( unsigned ) M [ i + <NUM_LIT> ] != Idx + NumElts ) ) return false ; Idx +=


<s> CCAssignFn * <ISA_LIT>FastISel :: CCAssignFnForCall ( unsigned CC , bool isTaillCall ) { if ( Subtarget -> is64Bit ( ) ) { if ( Subtarget -> isTargetWin64 ( ) ) return CC_<ISA_LIT>_Win64_C ; else if ( CC == CallingConv :: Fast && isTaillCall ) return CC_<ISA_LIT>_64_TailCall ; else return CC_<ISA_LIT>_64_C ; } if ( CC == CallingConv :: <ISA_LIT>_FastCall ) return CC_<ISA_LIT>_32_FastCall ; else if ( CC == CallingConv :: Fast ) return


<s> double value ; __asm ( <STR_LIT> : <STR_LIT> ( value ) : <STR_LIT> ( x )


<s> bool <ISA_LIT>PassConfig :: addInstSelector ( ) { PM . add ( create<ISA_LIT>ISelDag ( get<ISA_LIT>TargetMachine


<s> if ( IsStore ) { Src = Ldst . getOperand ( BasePos - <NUM_LIT> ) ; Ldst . RemoveOperand ( BasePos - <NUM_LIT> ) ; } Ldst . setDesc ( AST -> getInstrInfo ( ) -> get ( NewOpcode ) ) ; Ldst . addOperand ( MachineOperand :: CreateReg ( NewBase , true ) ) ; if ( IsStore ) Ldst . addOperand ( Src ) ; Ldst . addOperand ( MachineOperand :: CreateReg ( BaseReg , false ) ) ; Ldst . addOperand ( NewOffset )


<s> Chain * G = new Chain ( MI , Idx , getColor ( DestReg ) ) ; ActiveChains [ DestReg ] = G ; AllChains . insert ( G ) ; } else if ( isMla ( MI ) ) { unsigned DestReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned AccumReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; maybeKillChain ( MI -> getOperand ( <NUM_LIT> ) , Idx , ActiveChains ) ; maybeKillChain ( MI -> getOperand ( <NUM_LIT> ) , Idx , ActiveChains ) ; if ( DestReg != AccumReg ) maybeKillChain ( MI -> getOperand ( <NUM_LIT> ) , Idx , ActiveChains ) ; if ( ActiveChains . find ( AccumReg ) != ActiveChains . end ( ) ) { DEBUG ( dbgs ( ) << <STR_LIT> << TRI -> getName ( AccumReg ) << <STR_LIT>


<s> bool <ISA_LIT>FrameLowering :: enableShrinkWrapping ( const MachineFunction & MF )


<s> return __builtin_mve_vshrq_m_n_uv8hi ( __arm_vuninitializedq_u16 ( ) , __a


<s> for ( SDNode :: use_iterator I = LoadVal -> use_begin ( ) ; ! I . atEnd ( ) ; ++ I ) { if ( ! <STR_LIT> ( * I


<s> static void printUImmOperand ( const MCInst * MI ,


<s> bool <ISA_LIT>HazardRecognizer :: atIssueLimit (


<s> return ( lookup_attribute ( <STR_LIT> , TYPE_ATTRIBUTES ( type ) ) != NULL ) || ( lookup_attribute ( <STR_LIT> ,


<s> if ( TargetInstrInfo :: isSchedulingBoundary ( MI , MBB , MF ) ) return true ; return isSEHInstruction (


<s> NumDataVectors = <NUM_LIT> ; NumPredicateVectors = Offset . getScalable ( ) / <NUM_LIT> ; if ( NumPredicateVectors % <NUM_LIT> == <NUM_LIT> || NumPredicateVectors < - <NUM_LIT> || NumPredicateVectors > <NUM_LIT> ) { NumDataVectors = NumPredicateVectors / <NUM_LIT> ; NumPredicateVectors -= NumDataVectors