<s> if ( GlobalAddressSDNode * G = dyn_cast < GlobalAddressSDNode > ( Callee ) ) { const GlobalValue * GV = G -> getGlobal ( ) ; const Triple & TT = getTargetMachine ( ) . getTargetTriple ( ) ; if ( GV -> hasExternalWeakLinkage ( ) && ( ! TT . isOSWindows ( ) || TT . isOSBinFormatELF ( ) || TT . isOSBinFormatMachO ( ) ) ) return false ; } assert ( ( ! isVarArg || CalleeCC == CallingConv :: C ) && <STR_LIT> ) ; LLVMContext & C = * DAG . getContext ( ) ; if ( isVarArg && ! Outs . empty ( ) ) { SmallVector < CCValAssign , <NUM_LIT> > ArgLocs ; CCState CCInfo ( CalleeCC , isVarArg , MF , ArgLocs , C ) ; CCInfo . AnalyzeCallOperands ( Outs , CCAssignFnForCall ( CalleeCC , true ) ) ; for ( const CCValAssign & ArgLoc : ArgLocs ) if ( ! ArgLoc . isRegLoc ( ) ) return false ; } if ( ! CCState :: resultsCompatible ( CalleeCC , CallerCC , MF , C , Ins , CCAssignFnForCall ( CalleeCC , isVarArg ) , CCAssignFnForCall ( CallerCC , isVarArg ) ) ) return false ; const <ISA_LIT>RegisterInfo * TRI = Subtarget -> getRegisterInfo ( ) ; const uint32_t * CallerPreserved = TRI ->

getCallPreservedMask ( MF , CallerCC ) ;


<s> Vd |= ( fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ) ; unsigned Vm = ( fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ) ; Vm |= ( fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ) ; unsigned imm = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned cmode = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned op = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; DecodeStatus S = MCDisassembler :: Success ; if ( ! ( imm & <NUM_LIT> ) ) { if ( cmode == <NUM_LIT> ) { if ( op == <NUM_LIT> ) return MCDisassembler :: Fail ; Inst . setOpcode ( <STR_LIT> ) ; } if ( hasFullFP16 ) { if ( cmode == <NUM_LIT> ) { if ( op == <NUM_LIT> ) { Inst . setOpcode ( <STR_LIT> ) ; } else { Inst . setOpcode ( <STR_LIT> ) ; } } if ( cmode == <NUM_LIT> ) { if ( op == <NUM_LIT>


<s> bool SVEIntrinsicOpts :: optimizeConvertFromSVBool ( IntrinsicInst * I ) { assert ( I -> getIntrinsicID ( ) == <STR_LIT> && <STR_LIT> ) ; if ( isa < PHINode > ( I -> getArgOperand ( <NUM_LIT>


<s> return BaseType == FrameIndexBase || BaseReg . getNode ( ) !=


<s> CCVals [ CC ] = CCV ; if ( ! CCV -> hasName ( ) ) CCV -> setName ( ( Twine ( getCCName ( CC ) ) + <STR_LIT> + utostr ( CCAssignments [ CC ]


<s> bool <ISA_LIT>InstrInfo :: isBaseImmOffset ( const MachineInstr & MI )


<s> if ( CF != NCM . end ( ) ) { NodeVect & Cs = CF -> second ; for ( GepNode * C : Cs ) recalculatePlacementRec


<s> return isUInt < <NUM_LIT> > ( Imm -> getZExtValue


<s> std :: string Msg = <STR_LIT> ; uint64_t Mask = <NUM_LIT> ; for ( unsigned I = <NUM_LIT> ; I < sizeof ( ErrorInfo ) * <NUM_LIT> - <NUM_LIT> ; ++ I ) { if ( ErrorInfo & Mask ) { Msg += <STR_LIT> ; Msg += getSubtargetFeatureName ( ErrorInfo & Mask ) ; } Mask <<= <NUM_LIT> ; } return Error ( IDLoc , Msg ) ; } case Match_InvalidOperand : { SMLoc ErrorLoc = IDLoc ; if ( ErrorInfo != ~ <NUM_LIT> ) { if ( ErrorInfo >= Operands . size ( )


<s> if ( next == NULL ) return false ; return INSN_P ( next ) && GET_CODE (


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; } llvm_unreachable (


<s> return <STR_LIT> ( MI . getOpcode ( ) )


<s> Value * <ISA_LIT>IREmitter :: visitVTBL2 ( const SDNode * N ) { llvm_unreachable ( <STR_LIT> ) ;


<s> if ( ! MI -> hasOptionalDef ( ) || ! MCID -> OpInfo [ ccOutIdx ] . isOptionalDef ( ) ) { assert ( ! NewOpc && <STR_LIT> ) ; return ; } bool definesCPSR = false ; bool deadCPSR = false ; for ( unsigned i = MCID -> getNumOperands ( ) , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) { const MachineOperand & MO = MI -> getOperand ( i ) ; if ( MO . isReg ( ) && MO . isDef ( ) && MO . getReg ( )


<s> bool isImmUnsignedi8 ( ) const { if ( ! isImm ( ) ) return false ; const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; if ( ! CE ) return false ; return isImmUnsignedi8Value ( CE -> getValue


<s> FunctionPass * llvm :: create<ISA_LIT>ISelDag ( <ISA_LIT>TargetMachine & TM , CodeGenOpt :: Level OptLevel ) { return new <ISA_LIT>DAGToDAGISel ( TM ,


<s> return static_cast < const <ISA_LIT>TargetMachine & > ( TM


<s> EVT VT = Op . getValueType ( ) ; if ( VT == <STR_LIT> ) return LowerFROUND32 ( Op , DAG ) ; if ( VT == <STR_LIT> ) return LowerFROUND64 ( Op , DAG ) ; llvm_unreachable ( <STR_LIT>


<s> UserStack . push_back ( U ) ; while ( ! UserStack . empty ( ) ) { auto * UU = UserStack . pop_back_val ( ) ; if ( ! VisitedUsers . insert ( UU ) . second ) continue ; if ( isa < GlobalValue > ( UU ) ) continue ; if ( isa < Constant > ( UU ) ) { append_range ( UserStack , UU -> users ( ) ) ; continue ; } auto * I = cast < Instruction > ( UU ) ; Function * F = I -> getFunction ( ) ; if ( CollectKernelInsts ) { if ( ! llvm :: <STR_LIT> ( F ) ) { continue ; } } else { if ( llvm :: <STR_LIT> ( F ) ) { continue ; } } FunctionToInsts . insert ( std :: make_pair ( F , SmallPtrSet < Instruction * , <NUM_LIT> >


<s> void <ISA_LIT>AsmPrinter :: printThumbAddrModeS2Operand ( const MachineInstr * MI , int Op , raw_ostream & O ) { printThumbAddrModeRI5Operand ( MI , Op , O ,


<s> } if ( STI . isRWPI ( ) && ! isReadOnly ) { auto Offset = MRI . createVirtualRegister ( & <STR_LIT> ) ; MachineInstrBuilder OffsetMIB ; if ( UseMovt ) { OffsetMIB = BuildMI ( MBB , * MIB , MIB -> getDebugLoc ( ) , TII . get ( <STR_LIT> ) , Offset ) ; OffsetMIB . addGlobalAddress ( GV , <NUM_LIT> , <STR_LIT> ) ; } else { OffsetMIB = BuildMI ( MBB , * MIB , MIB -> getDebugLoc ( ) , TII . get ( <STR_LIT> ) , Offset ) ; addOpsForConstantPoolLoad ( OffsetMIB , GV , true ) ; } if ( ! constrainSelectedInstRegOperands ( * OffsetMIB , TII , TRI , RBI ) ) return false ; MIB -> setDesc ( TII . get ( <STR_LIT> ) ) ; MIB -> RemoveOperand ( <NUM_LIT> ) ; MIB . addReg ( <STR_LIT> ) . addReg ( Offset ) . add ( predOps ( <STR_LIT> ) ) . add ( condCodeOp ( ) ) ; return constrainSelectedInstRegOperands ( * MIB , TII , TRI , RBI ) ; } if ( STI . isTargetELF ( ) ) { if ( UseMovt ) { MIB -> setDesc ( TII . get ( <STR_LIT> ) ) ; } else { MIB -> setDesc ( TII . get ( <STR_LIT> ) ) ; MIB -> RemoveOperand ( <NUM_LIT> ) ; addOpsForConstantPoolLoad ( MIB , GV , false ) ; } } else if ( STI . isTargetMachO ( ) ) { if ( UseMovt ) MIB -> setDesc ( TII . get ( <STR_LIT>


<s> assert ( Subtarget . is64Bit ( ) && Subtarget . hasStdExtF ( ) && <STR_LIT> ) ; SDLoc DL ( Op ) ; SDValue Op0 = Op . getOperand ( <NUM_LIT> ) ; if ( Op . getValueType ( ) != <STR_LIT> || Op0 . getValueType ( ) != <STR_LIT> ) return SDValue ( ) ; SDValue NewOp0 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op0 ) ; SDValue FPConv = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , NewOp0 ) ; return FPConv ; } case <STR_LIT>


<s> std :: set < unsigned > getBlockPredicates ( ) const { std :: set < unsigned > result ; for ( auto const & pair :


<s> machine_mode mode = GET_MODE ( operands [ <NUM_LIT> ] ) ; if ( rtx shifts = aarch64_convert_mult_to_shift ( operands [ <NUM_LIT> ] , code ) ) { rtx product = expand_binop ( mode , vashl_optab , operands [ <NUM_LIT> ] , shifts , NULL_RTX , true , OPTAB_DIRECT ) ; force_expand_binop ( mode , code == PLUS ? add_optab : sub_optab , operands [ <NUM_LIT> ] , product , operands [ <NUM_LIT> ] , true , OPTAB_DIRECT ) ; return true ; } operands [ <NUM_LIT> ] = force_reg ( mode , operands [ <NUM_LIT> ] ) ; return


<s> static bool isAndOrOfSetCCs ( SDValue Op , unsigned & Opc ) { Opc = Op . getOpcode ( ) ; if ( Opc != <STR_LIT> && Opc != <STR_LIT> ) return false ; return ( <STR_LIT> ( Op . getOperand ( <NUM_LIT> ) . getOpcode ( ) ) && Op . getOperand ( <NUM_LIT> ) . hasOneUse ( ) && <STR_LIT> ( Op . getOperand

( <NUM_LIT> ) . getOpcode ( ) ) && Op . getOperand ( <NUM_LIT> ) . hasOneUse ( ) ) ;


<s> if ( ! aarch64_classify_address ( & addr , op ,


<s> switch ( cast < Operator > ( V ) . getOpcode ( ) ) { case Instruction :: PHI : case Instruction :: BitCast : case Instruction :: AddrSpaceCast : case Instruction :: GetElementPtr : return true


<s> return getShaderType ( ) == ShaderType :: COMPUTE ? <NUM_LIT> : ST . getWavefrontSize


<s> if ( ! Op1 . isSymbol ( ) ) return false ; StringRef Name ( Op1 . getSymbolName ( ) ) ; bool CallReturnsInput = Name == TLI . getLibcallName ( RTLIB :: MEMCPY ) || Name == TLI . getLibcallName ( RTLIB :: MEMMOVE ) || Name == TLI . getLibcallName ( RTLIB :: MEMSET ) ; if ( ! CallReturnsInput ) return false ; LibFunc Func ; if ( ! LibInfo . getLibFunc ( Name , Func ) ) return false ; unsigned FromReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned ToReg = MI . getOperand (


<s> FrameReg = RegInfo -> getFrameRegister ( MF ) ; return FPOffset ; } else if ( hasMovingSP ) { assert ( RegInfo -> hasBasePointer ( MF ) && <STR_LIT> ) ; if ( AFI -> isThumb2Function ( ) ) { if ( FPOffset >= - <NUM_LIT> && FPOffset < <NUM_LIT> ) { FrameReg = RegInfo -> getFrameRegister ( MF ) ; return FPOffset ; } } } else if ( AFI -> isThumb2Function ( ) ) { if ( Offset >= <NUM_LIT> && ( Offset & <NUM_LIT> ) == <NUM_LIT> && Offset <= <NUM_LIT> ) return Offset ; if ( FPOffset >= - <NUM_LIT> && FPOffset < <NUM_LIT> ) { FrameReg = RegInfo -> getFrameRegister ( MF ) ; return FPOffset ; } } else if ( Offset > ( FPOffset < <NUM_LIT> ? - FPOffset : FPOffset ) ) { FrameReg = RegInfo -> getFrameRegister ( MF


<s> Target & llvm :: getTheThumbBETarget ( ) { static Target TheThumbBETarget ; return


<s> return __arm_vclsq_m_s32 ( __inactive ,


<s> for ( auto MII = MF . begin ( ) -> begin ( ) , MIE = MF . begin ( ) -> end ( ) ; MII != MIE ; ) { MachineInstr * MI = & * MII ++ ; if ( MI -> isImplicitDef ( ) && MI -> getOperand ( <NUM_LIT> ) . isDead ( ) ) { LiveInterval & LI = LIS . getInterval ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; LIS . removeVRegDefAt ( LI , LIS . getInstructionIndex ( * MI ) . getRegSlot ( ) ) ; LIS . RemoveMachineInstrFromMaps ( * MI ) ; MI -> eraseFromParent ( ) ; } } return


<s> return ( int ) __builtin_c6x_saddu4 ( ( __uv4qi ) src1


<s> NodeId getReachingDef ( ) const { return Ref .


<s> Inst . addOperand ( MCOperand :: createImm


<s> if ( ( from == FP_REGS && to != FP_REGS ) || ( from != FP_REGS && to == FP_REGS ) ) return <NUM_LIT> ; else if ( from == HIGH_REGS || to == HIGH_REGS ) return optimize_size ? <NUM_LIT> : <NUM_LIT> ; else return <NUM_LIT>


<s> bool CustomListScheduler :: DelayForLiveRegsBottomUp ( SUnit * SU , SmallVector < unsigned , <NUM_LIT> > & LRegs ) { return false


<s> MCAssembler & MCA = getStreamer ( ) . getAssembler ( ) ; Pic = MCA . getContext ( ) . getObjectFileInfo ( ) -> isPositionIndependent ( ) ; const FeatureBitset & Features = STI . getFeatureBits ( ) ; unsigned EFlags = MCA . getELFHeaderEFlags ( ) ; ABI = <ISA_LIT>ABIInfo ( STI . getTargetTriple ( ) . getArch ( ) == Triple :: ArchType :: mipsel || STI . getTargetTriple ( ) . getArch ( ) == Triple :: ArchType :: mips ? <ISA_LIT>ABIInfo :: O32 ( ) : <ISA_LIT>ABIInfo :: N64 ( ) ) ; if ( Features [ <STR_LIT> ] ) EFlags |= ELF :: EF_MIPS_ARCH_64R6 ; else if ( Features [ <STR_LIT> ] || Features [ <STR_LIT> ] || Features [ <STR_LIT> ] ) EFlags |= ELF :: EF_MIPS_ARCH_64R2 ; else if ( Features [ <STR_LIT> ] ) EFlags |= ELF :: EF_MIPS_ARCH_64 ; else if ( Features [ <STR_LIT> ] ) EFlags |= ELF :: EF_MIPS_ARCH_5 ; else if ( Features [ <STR_LIT> ] ) EFlags |= ELF :: EF_MIPS_ARCH_4 ; else if ( Features [ <STR_LIT> ] ) EFlags


<s> if ( ! ProcessCallArgs ( Args , ArgRegs , ArgVTs , ArgFlags , RegArgs , CC , NumBytes ) ) return false ; MachineInstrBuilder MIB ; unsigned CallOpc = <ISA_LIT>SelectCallOp ( NULL ) ; if ( isThumb2 ) MIB = AddDefaultPred ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( CallOpc ) ) ) . addExternalSymbol ( TLI . getLibcallName ( Call ) ) ; else MIB = AddDefaultPred ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( CallOpc ) ) . addExternalSymbol ( TLI . getLibcallName ( Call ) ) ) ; for ( unsigned i = <NUM_LIT> , e = RegArgs . size ( ) ; i != e ; ++ i ) MIB . addReg ( RegArgs [ i ] ) ; SmallVector < unsigned , <NUM_LIT> > UsedRegs ; if ( ! FinishCall ( RetVT , UsedRegs , I , CC , NumBytes ) ) return false ; static_cast < MachineInstr * > ( MIB )

-> setPhysRegsDeadExcept ( UsedRegs , TRI ) ;


<s> SDValue <ISA_LIT>TargetLowering :: LowerELFTLSDescCallSeq ( SDValue SymAddr , const SDLoc & DL , SelectionDAG & DAG ) const { EVT PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; SDValue Chain = DAG . getEntryNode ( ) ; SDVTList NodeTys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; Chain = DAG . getNode ( <STR_LIT> , DL , NodeTys


<s> LLVMContext & Ctx = F . getContext ( ) ; IntegerType * I16 = Type :: getInt16Ty ( Ctx ) ; FunctionType * FnType = FunctionType :: get ( Type :: getVoidTy ( Ctx ) , { Type :: getInt8PtrTy ( Ctx ) , I16 } , false ) ; Constant * Fn = F . getParent ( ) -> getOrInsertFunction ( SymName , FnType ) ; Value * FunctionName = CreateStringPtr ( BB


<s> bool <ISA_LIT>ExpandPseudo :: ExpandMI ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI ) { MachineInstr & MI = * MBBI ; unsigned Opcode = MI . getOpcode ( ) ; DebugLoc DL = MBBI -> getDebugLoc ( ) ; switch ( Opcode ) { default : return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { bool isMem = Opcode == <STR_LIT> || Opcode == <STR_LIT> ; MachineOperand & JumpTarget = MBBI -> getOperand ( <NUM_LIT> ) ; MachineOperand & StackAdjust = MBBI -> getOperand ( isMem ? <NUM_LIT> : <NUM_LIT> ) ; assert ( StackAdjust . isImm ( ) && <STR_LIT> ) ; int StackAdj = StackAdjust . getImm ( ) ; if ( StackAdj ) { StackAdj += <ISA_LIT>FL -> mergeSPUpdates ( MBB , MBBI , true ) ; <ISA_LIT>FL -> emitSPUpdate ( MBB , MBBI , StackAdj , true ) ; } bool IsWin64 = STI -> isTargetWin64 ( ) ; if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) { unsigned Op = ( Opcode == <STR_LIT> ) ? <STR_LIT> : ( IsWin64 ? <STR_LIT> : <STR_LIT> ) ; MachineInstrBuilder MIB = BuildMI ( MBB , MBBI , DL , TII -> get ( Op ) ) ; if ( JumpTarget . isGlobal ( ) ) MIB . addGlobalAddress ( JumpTarget . getGlobal ( ) , JumpTarget . getOffset ( ) , JumpTarget . getTargetFlags ( ) ) ; else { assert ( JumpTarget . isSymbol ( ) ) ; MIB . addExternalSymbol ( JumpTarget . getSymbolName ( ) , JumpTarget . getTargetFlags ( ) ) ; } } else if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) { unsigned Op = ( Opcode == <STR_LIT> ) ? <STR_LIT> : ( IsWin64 ? <STR_LIT> : <STR_LIT> ) ; MachineInstrBuilder MIB = BuildMI ( MBB , MBBI , DL , TII -> get ( Op ) ) ; for ( unsigned i = <NUM_LIT> ; i != <NUM_LIT> ; ++ i ) MIB . addOperand ( MBBI -> getOperand ( i ) ) ; } else if ( Opcode == <STR_LIT> ) { BuildMI ( MBB , MBBI , DL , TII -> get ( IsWin64 ? <STR_LIT> : <STR_LIT> ) ) . addReg ( JumpTarget . getReg ( ) , RegState :: Kill ) ; } else { BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) ) . addReg ( JumpTarget . getReg ( ) , RegState :: Kill ) ; } MachineInstr * NewMI = std :: prev ( MBBI ) ; NewMI -> copyImplicitOps ( * MBBI -> getParent ( ) -> getParent ( ) , MBBI ) ; MBB . erase ( MBBI ) ; return true ; } case <STR_LIT> : case <STR_LIT> : { MachineOperand & DestAddr = MBBI -> getOperand ( <NUM_LIT> ) ; assert ( DestAddr . isReg ( ) && <STR_LIT> ) ; const bool Uses64BitFramePtr = STI -> isTarget64BitLP64 (


<s> switch ( BitWidth ) { case <NUM_LIT> : return & <STR_LIT> ; case <NUM_LIT> : return & <STR_LIT> ; case <NUM_LIT> : return & <STR_LIT> ; case <NUM_LIT> : return & <STR_LIT> ; case <NUM_LIT> : return & <STR_LIT> ; case <NUM_LIT> : return & <STR_LIT> ; case <NUM_LIT> : return & <STR_LIT> ; case <NUM_LIT> : return & <STR_LIT> ; case <NUM_LIT> : return & <STR_LIT>


<s> MI . clear ( ) ; MI . setOpcode ( <STR_LIT> ) ; MI . addOperand ( MCOperand :: createImm ( <NUM_LIT> ) ) ; while ( Result == Success && Complete == false ) { if ( Bytes . size ( ) < HEXAGON_INSTR_SIZE ) return MCDisassembler :: Fail ; MCInst * Inst = new ( getContext ( ) ) MCInst ; Result = getSingleInstruction ( * Inst , MI , Bytes , Address , os ,


<s> Alignment = ST -> getAlignment ( ) ; isLoad = false ; } else return false ; if ( VT . isVector ( ) ) { if ( ! Subtarget . hasQPX ( ) || ( VT != <STR_LIT> && VT != <STR_LIT> ) ) { return false ; } else if ( SelectAddressRegRegOnly ( Ptr , Offset , Base , DAG ) ) { AM = <STR_LIT> ; return true ; } } if ( SelectAddressRegReg ( Ptr , Base , Offset , DAG ) ) { bool Swap = false ; if ( isa < FrameIndexSDNode > ( Base ) || isa < RegisterSDNode > ( Base ) ) Swap = true ; else if ( ! isLoad ) { SDValue Val = cast < StoreSDNode > ( N ) -> getValue ( ) ; if ( Val == Base || Base . getNode ( ) -> isPredecessorOf ( Val . getNode ( ) ) ) Swap = true ; } if ( Swap ) std :: swap ( Base , Offset ) ; AM = <STR_LIT> ; return true ; } if ( VT != <STR_LIT> ) { if ( ! SelectAddressRegImm ( Ptr , Offset , Base , DAG , <NUM_LIT> ) ) return false ; } else { if ( Alignment < <NUM_LIT> ) return false ; if ( ! SelectAddressRegImm ( Ptr , Offset , Base , DAG , <NUM_LIT> ) ) return false ; } if ( LoadSDNode * LD = dyn_cast < LoadSDNode > ( N ) ) { if ( LD -> getValueType ( <NUM_LIT> ) == <STR_LIT> && LD -> getMemoryVT ( ) == <STR_LIT> && LD -> getExtensionType ( ) == <STR_LIT> && isa < ConstantSDNode > ( Offset ) ) return false ; } AM =


<s> rtx label2 = gen_label_rtx ( ) ; rtx tmp = gen_reg_rtx ( XFmode ) ; rtx tmp2 = gen_reg_rtx ( XFmode ) ; emit_insn ( gen_absxf2 ( tmp , op1 ) ) ; emit_insn ( gen_cmpxf ( tmp , CONST_DOUBLE_FROM_REAL_VALUE ( REAL_VALUE_ATOF ( <STR_LIT> , XFmode ) , XFmode ) ) ) ; emit_jump_insn ( gen_bge ( label1 ) ) ; emit_move_insn ( tmp2 , standard_80387_constant_rtx ( <NUM_LIT> ) ) ; emit_insn ( gen_fyl2xp1_xf3 ( op0 , tmp2 , op1


<s> void <ISA_LIT>MCInstLower :: lowerInstruction ( const MachineInstr & MI , MCInst & OutMI ) const { OutMI . setOpcode ( MI . getOpcode ( ) ) ; for ( MachineOperand const & MO : MI . operands ( ) ) { MCOperand MCOp


<s> static unsigned int rx_function_arg_boundary ( machine_mode mode ATTRIBUTE_UNUSED , const_tree type ATTRIBUTE_UNUSED ) { if ( TARGET_GCC_ABI ) return STACK_BOUNDARY ; if ( type ) { if ( DECL_P ( type ) ) return DECL_ALIGN


<s> EmitW64Tables ( ) ; MCWinCOFFStreamer :: FinishImpl


<s> } bool ReverseVEXT , isV_UNDEF ; unsigned Imm , WhichResult ; unsigned EltSize = VT . getScalarSizeInBits ( ) ; if ( EltSize >= <NUM_LIT> || ShuffleVectorSDNode :: isSplatMask ( & M [ <NUM_LIT> ] , VT ) || ShuffleVectorInst :: isIdentityMask ( M ) || isVREVMask ( M , VT , <NUM_LIT> ) || isVREVMask ( M , VT , <NUM_LIT> ) || isVREVMask ( M , VT , <NUM_LIT> ) ) return true ; else if ( Subtarget -> hasNEON ( ) && ( isVEXTMask ( M , VT , ReverseVEXT , Imm ) || isVTBLMask ( M

, VT ) || isNEONTwoResultShuffleMask ( M , VT , WhichResult , isV_UNDEF ) ) ) return true ;


<s> void replaceConstantUsesInFunction ( ConstantExpr * C , const Function * F ) { SetVector < Instruction * >


<s> else if ( ( unsigned int ) align_functions < max_align ) align = align_functions ; else align = max_align ; ofs = prev_in_use = <NUM_LIT> ; i = get_insns ( ) ; if ( GET_CODE ( i ) == NOTE ) i = next_nonnote_insn ( i ) ; ldgp = alpha_function_needs_gp ? <NUM_LIT> : <NUM_LIT> ; while ( i ) { next = ( * next_group ) ( i , & in_use , & len ) ; if ( GET_CODE ( i ) == CODE_LABEL ) { unsigned int new_align = <NUM_LIT> << label_to_alignment ( i ) ; if ( new_align >= align ) { align = new_align < max_align ? new_align : max_align ; ofs = <NUM_LIT> ; } else if ( ofs & ( new_align - <NUM_LIT> ) ) ofs = ( ofs | ( new_align - <NUM_LIT> ) ) + <NUM_LIT> ; gcc_assert ( ! len ) ; } else if ( in_use == <NUM_LIT> ) { if ( len < <NUM_LIT> ) { ofs = <NUM_LIT> ; align = <NUM_LIT> ; len = <NUM_LIT> ; } } else if ( ( int ) align < len ) { unsigned int new_log_align = len > <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ; rtx prev , where ; where = prev = prev_nonnote_insn ( i ) ; if ( ! where || GET_CODE ( where ) != CODE_LABEL ) where = i ; if ( ! ( TARGET_EXPLICIT_RELOCS && prev && GET_CODE ( prev ) == CALL_INSN ) ) { emit_insn_before ( gen_realign ( GEN_INT ( new_log_align ) ) , where ) ; align = <NUM_LIT> << new_log_align ; ofs = <NUM_LIT> ; } } else if ( ldgp > <NUM_LIT> ) ldgp -= len ; else if ( ofs + len > ( int ) align ) { int nop_count = ( align - ofs ) / <NUM_LIT> ; rtx where ; where = prev_nonnote_insn ( i ) ; if ( where ) { if ( GET_CODE ( where ) == CODE_LABEL ) { rtx where2 = prev_nonnote_insn ( where ) ; if ( where2 && GET_CODE ( where2 ) == JUMP_INSN ) where = where2 ; } else if ( GET_CODE ( where ) == INSN ) where = i ; } else where = i ; do emit_insn_before ( ( * next_nop )


<s> using namespace <ISA_LIT>II ; static const std :: pair < unsigned , const char * > TargetFlags [ ] = { { MO_COFFSTUB , <STR_LIT> } , { MO_GOT , <STR_LIT> } , { MO_NC , <STR_LIT> } , { MO_S , <STR_LIT>

} , { MO_TLS , <STR_LIT> } , { MO_DLLIMPORT , <STR_LIT> } } ;


<s> SDLoc SL ( N ) ; SDValue Src = N0 . getOperand ( <NUM_LIT> ) ; EVT SrcVT = Src . getValueType ( ) ; SDValue IntFAbs = DAG . getNode ( <STR_LIT> , SL , SrcVT , Src , DAG . getConstant ( <NUM_LIT>


<s> unsigned short <ISA_LIT>MCInstrInfo :: getNewValueOp2 ( MCInstrInfo const & MCII , MCInst const & MCI ) { const uint64_t F = <ISA_LIT>MCInstrInfo :: getDesc


<s> static uint8_t name ( struct InternalInstruction * insn , \ OperandType type , \ uint8_t index , \ uint8_t * valid ) { \ * valid = <NUM_LIT> ; \ switch ( type ) { \ default : \ debug ( <STR_LIT> ) ; \ * valid = <NUM_LIT> ; \ return <NUM_LIT> ; \ case TYPE_Rv : \ return base + index ; \ case TYPE_R8 : \ if ( insn -> rexPrefix && \ index >= <NUM_LIT> && index <= <NUM_LIT> ) { \ return prefix ## _SPL + ( index - <NUM_LIT> ) ; \ } else { \ return prefix ## _AL + index ; \ } \ case TYPE_R16 : \ return prefix ## _AX + index ; \ case TYPE_R32 : \ return prefix ## _EAX + index ; \ case TYPE_R64 : \ return prefix ## _RAX + index ; \ case TYPE_XMM512 : \ return prefix ## _ZMM0 + index ; \ case TYPE_XMM256 : \ return prefix ## _YMM0 + index ; \ case TYPE_XMM128 : \ case TYPE_XMM64 : \ case TYPE_XMM32 : \ case TYPE_XMM : \ return prefix ## _XMM0 + index ; \ case TYPE_VK1 : \ case TYPE_VK8 : \ case TYPE_VK16 : \ if ( index > <NUM_LIT> ) \ * valid = <NUM_LIT> ; \ return prefix ## _K0 + index ; \ case TYPE_MM64 : \ return prefix ## _MM0 + ( index & <NUM_LIT> ) ; \ case TYPE_SEGMENTREG : \ if ( index > <NUM_LIT>

) \ * valid = <NUM_LIT> ; \ return prefix ## _ES + index ; \ case TYPE_DEBUGREG : \ return prefix ## _DR0 + index ; \ case TYPE_CONTROLREG : \ return prefix ## _CR0 + index ; \ } \ }


<s> MI . addOperand ( MCOperand :: createReg ( getReg ( Decoder , <STR_LIT> , Rs ) ) ) ; MI . addOperand ( MCOperand :: createImm ( Imm ) ) ; return MCDisassembler :: Success


<s> clonei -> vecsize_float = <NUM_LIT> ; break ; case 'd' : clonei -> vecsize_int = <NUM_LIT> ; clonei -> vecsize_float = <NUM_LIT> ; break ; case 'e' : clonei -> vecsize_int = <NUM_LIT> ; clonei -> vecsize_float = <NUM_LIT> ; if ( TYPE_MODE ( base_type ) == QImode ) clonei -> mask_mode = DImode ; else clonei -> mask_mode = SImode ; break ; } if ( clonei -> simdlen == <NUM_LIT> ) { if ( SCALAR_INT_MODE_P ( TYPE_MODE ( base_type ) ) ) clonei -> simdlen = clonei -> vecsize_int ; else clonei -> simdlen = clonei -> vecsize_float ; clonei -> simdlen = clonei -> simdlen / GET_MODE_BITSIZE ( TYPE_MODE ( base_type ) ) ; } else if ( clonei -> simdlen > <NUM_LIT> ) { tree ctype = ret_type ; if ( TREE_CODE ( ret_type ) == VOID_TYPE ) ctype = base_type ; int cnt = GET_MODE_BITSIZE ( TYPE_MODE ( ctype ) ) * clonei -> simdlen ; if ( SCALAR_INT_MODE_P ( TYPE_MODE ( ctype ) ) ) cnt /= clonei -> vecsize_int ; else cnt /= clonei -> vecsize_float ; if ( cnt > ( TARGET_64BIT ? <NUM_LIT> : <NUM_LIT> ) ) { if ( explicit_p ) warning_at ( DECL_SOURCE_LOCATION ( node -> decl ) , <NUM_LIT>

, <STR_LIT> , clonei -> simdlen . to_constant ( ) ) ;


<s> if ( Is<ISA_LIT>64 && has64BitSupport ( ) ) Use64BitRegs = true ; if ( isDarwin ( ) ) HasLazyResolverStubs = true ; IsQPXStackUnaligned = QPXStackUnaligned ; StackAlignment = getPlatformStackAlignment ( ) ; IsLittleEndian = ( TargetTriple . getArch ( ) == Triple


<s> Register DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; bool DstIsDead = MI . getOperand ( <NUM_LIT> ) . isDead ( ) ; bool DstIsKill = MI . getOperand ( <NUM_LIT> ) . isKill ( ) ; bool ImpIsDead = MI . getOperand ( <NUM_LIT> ) . isDead ( ) ; buildMI ( MBB , MBBI , <STR_LIT> ) . addReg ( DstReg , RegState :: Define | getDeadRegState ( DstIsDead ) ) . addReg ( DstReg , getKillRegState ( DstIsKill ) ) -> getOperand ( <NUM_LIT> ) . setIsUndef ( true ) ; buildMI ( MBB , MBBI , <STR_LIT> ) . addReg ( DstReg , RegState :: Define | getDeadRegState ( DstIsDead ) ) . addReg ( DstReg , getKillRegState ( DstIsKill ) ) . addReg ( DstReg , getKillRegState ( DstIsKill ) ) ; auto MIRRC = buildMI ( MBB , MBBI , <STR_LIT> ) . addReg ( DstReg , RegState :: Define | getDeadRegState ( DstIsDead ) ) . addReg ( DstReg , getKillRegState ( DstIsKill ) ) ; if ( ImpIsDead ) MIRRC -> getOperand ( <NUM_LIT> )


<s> bool ISASupported = ! Subtarget -> has<ISA_LIT>32r6 ( ) && ! Subtarget -> inMicro<ISA_LIT>Mode ( ) && Subtarget -> has<ISA_LIT>32 ( ) ; TargetSupported = ISASupported && TM . isPositionIndependent ( ) && ( static_cast < const <ISA_LIT>TargetMachine & > ( TM ) .


<s> return MF -> getFunction ( ) . getCallingConv ( ) == CallingConv :: CXX_FAST_TLS

&& MF -> getFunction ( ) . hasFnAttribute ( Attribute :: NoUnwind ) ;


<s> <ISA_LIT>TargetMachine & getTM ( ) { return static_cast < <ISA_LIT>TargetMachine & > ( TM


<s> void LLVMInitialize<ISA_LIT>Target ( ) { RegisterTargetMachine < <ISA_LIT>TargetMachine > X ( getThe<ISA_LIT>Target ( )


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return


<s> BitVector Reserved ( getNumRegs ( ) ) ; markSuperRegs ( Reserved , <STR_LIT> ) ; markSuperRegs ( Reserved , <STR_LIT> ) ; if ( TFI -> hasFP ( MF ) || TT . isOSDarwin ( ) ) markSuperRegs ( Reserved , <STR_LIT> ) ; if ( MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . isX18Reserved ( ) ) markSuperRegs ( Reserved , <STR_LIT> ) ; if ( MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . isX20Reserved ( ) ) markSuperRegs


<s> __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT> ( b ) , <STR_LIT> ( c ) : ) ; return result


<s> do { DEBUG ( errs ( ) << <STR_LIT> << MF . getFunction ( ) -> getName ( ) << <STR_LIT> ) ; MCE . startFunction ( MF ) ; for ( MachineFunction :: iterator MBB = MF . begin ( ) , E = MF . end ( ) ; MBB != E ; ++ MBB ) { MCE . StartMachineBasicBlock ( MBB ) ; for ( MachineBasicBlock :: const_iterator I = MBB -> begin ( ) , E = MBB -> end ( ) ; I != E ; ++ I ) emitInstruction ( * I ) ; } } while ( MCE . finishFunction ( MF ) ) ; return


<s> return isMemNoOffset ( false , <NUM_LIT>


<s> for ( unsigned i = <NUM_LIT> ; i < CSI . size ( ) ; ++ i ) { if ( TRI -> regsOverlap ( CSI [ i ] . getReg ( ) , FPReg ) ) { CSI . erase ( CSI . begin ( ) + i ) ; break ; } } } for ( unsigned i = CSI . size ( ) ; i != <NUM_LIT> ; -- i ) { unsigned Reg = CSI [ i - <NUM_LIT> ] . getReg ( ) ; if ( ! <STR_LIT> . contains ( Reg ) && ! <STR_LIT> . contains ( Reg ) ) continue ; SpillSlotOffset -= SlotSize ; CalleeSavedFrameSize += SlotSize ; int SlotIndex = MFI . CreateFixedSpillStackObject ( SlotSize , SpillSlotOffset ) ; CSI [ i - <NUM_LIT> ] . setFrameIdx ( SlotIndex ) ; } <ISA_LIT>FI -> setCalleeSavedFrameSize ( CalleeSavedFrameSize ) ; MFI . setCVBytesOfCalleeSavedRegisters ( CalleeSavedFrameSize ) ; for ( unsigned i = CSI . size ( ) , Size = <NUM_LIT> ; i != <NUM_LIT> ; -- i ) { unsigned Reg = CSI [ i - <NUM_LIT> ] . getReg ( ) ; if ( ! <STR_LIT> . contains ( Reg ) ) continue ; if ( Size == <NUM_LIT> ) { unsigned Align = TRI -> getSpillAlignment ( <STR_LIT> ) ; int Remainder = SpillSlotOffset % Align ; if ( Remainder < <NUM_LIT> ) SpillSlotOffset -= Align + Remainder ; else SpillSlotOffset -= Remainder ; MFI . ensureMaxAlignment (


<s> RegToRegMap :: iterator F = G2P . find ( Reg ) ; if ( F != G2P . end ( ) ) return F -> second ; LLVM_DEBUG ( dbgs ( ) << __func__ << <STR_LIT> << PrintRegister ( Reg , * TRI ) ) ; MachineInstr * DefI = MRI -> getVRegDef ( Reg . R ) ; assert ( DefI ) ; unsigned Opc = DefI -> getOpcode ( ) ; if ( Opc == <STR_LIT> || Opc == TargetOpcode :: COPY ) { assert ( DefI -> getOperand ( <NUM_LIT> ) . isDef ( ) && DefI -> getOperand ( <NUM_LIT> ) . isUse ( ) ) ; RegisterSubReg PR = DefI -> getOperand ( <NUM_LIT> ) ; G2P . insert ( std :: make_pair ( Reg , PR ) ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << PrintRegister ( PR , * TRI ) << '\n' ) ; return PR ; } MachineBasicBlock & B = * DefI -> getParent ( ) ; DebugLoc DL = DefI -> getDebugLoc ( ) ; const TargetRegisterClass * PredRC = &


<s> bool hasCalculatedTID ( ) const { return TIDReg != <NUM_LIT>


<s> SmallVector < CCValAssign , <NUM_LIT> > RVLocs ; CCState CCInfo ( CallConv , isVarArg , DAG . getMachineFunction ( ) , getTargetMachine ( ) , RVLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeCallResult ( Ins , RetCC_<ISA_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i ) { Chain = DAG . getCopyFromReg ( Chain , dl , RVLocs [ i ] . getLocReg ( ) , RVLocs [ i ] . getValVT ( ) , InFlag ) . getValue ( <NUM_LIT> ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; InVals . push_back ( Chain . getValue ( <NUM_LIT>


<s> StackAlignment = Align ( <NUM_LIT> ) ; CPUDirective = <STR_LIT> ; HasMFOCRF = false ; Has64BitSupport = false ; Use64BitRegs = false ; UseCRBits = false ; HasHardFloat = false ; HasAltivec = false ; HasSPE = false ; HasFPU = false ; HasQPX = false ; HasVSX = false ; NeedsTwoConstNR = false ; HasP8Vector = false ; HasP8Altivec = false ; HasP8Crypto = false ; HasP9Vector = false ; HasP9Altivec = false ; HasFCPSGN = false ; HasFSQRT = false ; HasFRE = false ; HasFRES = false ; HasFRSQRTE = false ; HasFRSQRTES = false ; HasRecipPrec = false ; HasSTFIWX = false ; HasLFIWAX = false ; HasFPRND = false ; HasFPCVT = false ; HasISEL = false ; HasBPERMD = false ; HasExtDiv = false ; HasCMPB = false ; HasLDBRX = false ; IsBookE = false ; HasOnlyMSYNC = false ; Is<ISA_LIT>4xx = false ; Is<ISA_LIT>6xx = false ; IsE500 = false ; FeatureMFTB = false ; AllowsUnalignedFPAccess = false ; DeprecatedDST = false ; HasLazyResolverStubs = false ; HasICBT = false ; HasInvariantFunctionDescriptors = false ; HasPartwordAtomics = false ; HasDirectMove = false ; IsQPXStackUnaligned = false


<s> return new <ISA_LIT>AsmPrinter ( TM , std


<s> RegisterMCAsmParser < <ISA_LIT>AsmParser > Y ( getThe<ISA_LIT>64Target


<s> UseNEONForSinglePrecisionFP = false ; UseMulOps = UseFusedMulOps ; SlowFPVMLx = false ; HasVMLxForwarding = false ; SlowFPBrcc = false ; InThumbMode = false ; UseSoftFloat = false ; HasThumb2 = false ; No<ISA_LIT> = false ; ReserveR9 = false ; NoMovt = false ; SupportsTailCall = false ; HasFP16 = false ; HasD16 = false ; HasHardwareDivide = false ; HasHardwareDivideIn<ISA_LIT> = false ; HasT2ExtractPack = false ; HasDataBarrier = false ; Pref32BitThumb = false ; AvoidCPSRPartialUpdate = false ; AvoidMOVsShifterOperand = false ; HasRAS =


<s> static MCInstrInfo * create<ISA_LIT>MCInstrInfo ( ) { MCInstrInfo * Info = new MCInstrInfo ( ) ; Init<ISA_LIT>MCInstrInfo ( Info ) ; return


<s> bool SelectAddrImm ( SDValue N , SDValue & Disp , SDValue &


<s> LineReader ( std :: string filename ) { theCurLine = <NUM_LIT> ; fstr . open ( filename .


<s> for ( auto & I : * BB ) { if ( I . getType ( ) -> isVectorTy ( ) ) return ; if ( isa < CallInst > ( I ) || isa < InvokeInst > ( I ) ) { if ( const Function * F = cast < CallBase > ( I ) . getCalledFunction ( ) ) { if ( ! isLoweredToCall ( F ) ) continue ; } return ; } } } if ( ST -> getProcFamily ( ) != <ISA_LIT>Subtarget :: Others && ! ST -> getSchedModel (


<s> static bool isImmSExti16i8Value ( uint64_t Value ) { return ( ( Value <= <NUM_LIT> ) || ( <NUM_LIT> <= Value && Value <= <NUM_LIT>

) || ( <NUM_LIT> <= Value && Value <= <NUM_LIT> ) ) ;


<s> switch ( lmul ) { case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT>


<s> void <ISA_LIT>InstPrinter :: printPCLabel ( const MCInst * MI ,


<s> static inline bool is<ISA_LIT>_64ExtendedReg ( unsigned RegNo ) { switch ( RegNo ) { default : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case


<s> default : assert ( <NUM_LIT> && <STR_LIT> ) ; return SDValue ( ) ; } SmallVector < SDValue , <NUM_LIT> > Ops ( <NUM_LIT> ) ; Ops [ <NUM_LIT> ] = Value ; Ops [ <NUM_LIT> ] = Amt ; SDValue Call = Make<ISA_LIT>Libcall ( CallCode , N -> getValueType ( <NUM_LIT> ) , & Ops [ <NUM_LIT> ] , <NUM_LIT> , true , DAG , N -> getDebugLoc ( ) ) ; return Call


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , Reloc :: Model RM , CodeModel :: Model CM ,


<s> MachineLoop * LoopRep = MLI -> getLoopFor ( MBB ) ; while ( LoopRep && LoopRep -> getHeader ( ) == MBB ) { MachineBasicBlock * LoopLand = getLoopLandInfo ( LoopRep ) ; if ( ! LoopLand ) return true ; if ( ! isRetiredBlock ( LoopLand ) ) return true ; LoopRep = LoopRep -> getParentLoop


<s> SDLoc dl ( Op ) ; SDValue Chain = Op . getOperand ( <NUM_LIT> ) ; <STR_LIT> CC = cast < CondCodeSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> get ( ) ; SDValue LHS = Op . getOperand ( <NUM_LIT> ) ; SDValue RHS = Op . getOperand ( <NUM_LIT> ) ; SDValue DestBB = Op . getOperand ( <NUM_LIT> ) ; if ( LHS . getValueType ( ) == <STR_LIT> ) { softenSetCCOperands ( DAG , <STR_LIT> , LHS , RHS , CC , dl ) ; if ( ! RHS . getNode ( ) ) { RHS = DAG . getConstant ( <NUM_LIT> , LHS . getValueType ( ) ) ; CC = <STR_LIT> ; } } if ( LHS . getValueType ( ) . isInteger ( ) ) { SDValue A64cc ; SDValue CmpOp = getSelectableIntSetCC ( LHS , RHS , CC , A64cc , DAG , dl ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Chain , CmpOp , A64cc , DestBB ) ; } <STR_LIT> CondCode , Alternative =


<s> if ( MO . isImm ( ) ) return MO . getImm ( ) ; assert ( MO . isExpr ( ) && <STR_LIT> ) ; Fixups . push_back ( MCFixup :: Create ( <NUM_LIT> , MO . getExpr ( ) , MCFixupKind ( <STR_LIT> )


<s> emitInlineJumpTable ( MI . getOperand ( <NUM_LIT> ) . getIndex ( ) ) ; return ; } unsigned Binary = getBinaryCodeForInstr ( MI ) ; Binary |= II -> getPredicate ( & MI ) << <STR_LIT> ; if ( TID . Opcode == <STR_LIT> || TID . Opcode == <STR_LIT> ) Binary |= <ISA_LIT>RegisterInfo :: getRegisterNumbering ( <STR_LIT> ) ; else Binary |= getMachineOpValue ( MI


<s> static MCCodeGenInfo * create<ISA_LIT>MCCodeGenInfo ( StringRef TT , Reloc :: Model RM , CodeModel :: Model CM ) { MCCodeGenInfo * X = new MCCodeGenInfo ( ) ; if ( RM == Reloc :: Default ) RM = Reloc :: Static ; X -> InitMCCodeGenInfo ( RM , CM


<s> void printDstIdx16 ( const MCInst * MI , unsigned


<s> if ( TRI -> isSubRegisterEq ( Reg , MaxReg ) ) break ; if ( ! MRI -> isAllocatable ( Reg ) || getPhysRegBank ( Reg , SubReg ) != Bank ) continue ; for ( unsigned I = <NUM_LIT> ; CSRegs [ I ] ; ++ I ) if ( TRI -> isSubRegisterEq ( Reg , CSRegs [ I ] ) && ! LRM -> isPhysRegUsed ( CSRegs [ I ] ) ) return MCRegister :: from ( <STR_LIT> ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << printReg ( Reg ) << '\n' ) ; if ( ! LRM -> checkInterference ( LI , Reg ) )


<s> HOST_WIDE_INT lower = INTVAL ( XEXP ( ad , <NUM_LIT> ) ) & <NUM_LIT> ; HOST_WIDE_INT upper = INTVAL ( XEXP ( ad , <NUM_LIT> ) ) ^ lower ; rtx cst , tem , new ; cst = GEN_INT ( upper ) ; if ( ! legitimate_reload_constant_p ( cst ) ) cst = force_const_mem ( Pmode , cst ) ; tem = gen_rtx_PLUS ( Pmode , XEXP ( ad , <NUM_LIT> ) , cst ) ; new = gen_rtx_PLUS ( Pmode , tem , GEN_INT ( lower ) ) ; push_reload ( XEXP ( tem , <NUM_LIT> ) , <NUM_LIT> , & XEXP ( tem , <NUM_LIT> ) , <NUM_LIT> , BASE_REG_CLASS , Pmode , VOIDmode , <NUM_LIT> , <NUM_LIT> , opnum , ( enum reload_type ) type ) ; return new ; } return NULL_RTX


<s> static SDValue lowerVECTOR_SHUFFLE_ILVEV ( SDValue Op , EVT ResTy , SmallVector < int , <NUM_LIT> > Indices , SelectionDAG & DAG ) { assert ( ( Indices . size ( ) % <NUM_LIT> ) == <NUM_LIT> ) ; int WsIdx = <NUM_LIT> ; int WtIdx = ResTy . getVectorNumElements ( ) ; for ( unsigned i = <NUM_LIT> ; i < Indices . size ( ) ; i += <NUM_LIT> ) { if ( Indices [ i ] != - <NUM_LIT> && Indices [ i ] != WsIdx ) return SDValue ( ) ; if ( Indices [ i + <NUM_LIT> ] != - <NUM_LIT> && Indices [ i +

<NUM_LIT> ] != WtIdx ) return SDValue ( ) ;


<s> gcc_assert ( epilogue_completed ) ; s390_regs_ever_clobbered ( clobbered_regs ) ; for ( i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) clobbered_regs [ i ] = clobbered_regs [ i ] && ! global_not_special_regno_p ( i ) ; clobbered_regs [ RETURN_REGNUM ] |= ( TARGET_TPF_PROFILING || cfun_frame_layout . save_return_addr_p || crtl -> calls_eh_return ) ; memset ( cfun_frame_layout . gpr_save_slots , SAVE_SLOT_NONE , <NUM_LIT> ) ; for ( i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) if ( !

clobbered_regs [ i ] ) cfun_gpr_save_slot ( i ) = SAVE_SLOT_NONE ;


<s> DEBUG ( dbgs ( ) << <STR_LIT> ; Node -> dump ( CurDAG ) ; dbgs ( ) << '\n' ) ; if ( Node -> isMachineOpcode ( ) ) { DEBUG ( dbgs ( ) << <STR_LIT> ; Node -> dump ( CurDAG ) ; dbgs ( )


<s> for ( User :: const_op_iterator i = U -> op_begin ( ) + <NUM_LIT> , e = U -> op_end ( ) ; i != e ; ++ i , ++ GTI ) { const Value * Op = * i ; if ( StructType * STy = dyn_cast < StructType > ( * GTI ) ) { const StructLayout * SL = TD . getStructLayout ( STy ) ; unsigned Idx = cast < ConstantInt > ( Op ) -> getZExtValue ( ) ; TmpOffset += SL -> getElementOffset ( Idx ) ; } else { uint64_t S = TD . getTypeAllocSize ( GTI . getIndexedType ( ) ) ; for ( ; ; ) { if ( const ConstantInt * CI = dyn_cast < ConstantInt > ( Op ) ) { TmpOffset += CI -> getSExtValue ( ) * S ; break ; } if ( isa < AddOperator > ( Op ) && ( ! isa < Instruction > ( Op ) || FuncInfo . MBBMap [ cast < Instruction > ( Op ) -> getParent ( ) ] == FuncInfo . MBB ) && isa < ConstantInt > ( cast < AddOperator > ( Op ) -> getOperand ( <NUM_LIT> ) ) ) { ConstantInt * CI = cast < ConstantInt > ( cast < AddOperator > ( Op ) -> getOperand ( <NUM_LIT> ) ) ; TmpOffset += CI -> getSExtValue ( ) * S ; Op = cast < AddOperator > ( Op ) -> getOperand ( <NUM_LIT> ) ; continue ; } goto unsupported_gep


<s> return ggc_cleared_alloc < machine_function > (


<s> MxCond = <STR_LIT> ; break ; case <STR_LIT> : MxOpcode = <STR_LIT> ; MxCond = <STR_LIT> ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } if ( Inverted ) MxCond = <STR_LIT> ( ( <STR_LIT> ) MxCond ) ; if ( CondOpcode == <STR_LIT> ) VTs = DAG . getVTList ( LHS . getValueType ( ) , LHS . getValueType ( ) , <STR_LIT> ) ; else VTs = DAG . getVTList ( LHS . getValueType ( ) , <STR_LIT> ) ; SDValue MxOp = DAG . getNode ( MxOpcode , DL , VTs , LHS , RHS ) ; if ( CondOpcode == <STR_LIT> ) Cond = MxOp . getValue ( <NUM_LIT> ) ; else Cond = MxOp . getValue ( <NUM_LIT> ) ; CC = DAG . getConstant ( MxCond , DL , <STR_LIT> ) ; AddTest = false ; } else { unsigned CondOpc ; if ( Cond . hasOneUse ( ) && isAndOrOfSetCCs ( Cond , CondOpc ) ) { SDValue Cmp = Cond . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ; if ( CondOpc == <STR_LIT> ) { if ( Cmp == Cond . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) && is<ISA_LIT>LogicalCmp ( Cmp ) ) { CC = Cond . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ; Chain = DAG . getNode ( <STR_LIT> , DL , Op . getValueType ( ) , Chain , Dest , CC , Cmp ) ; CC = Cond . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ; Cond = Cmp ; AddTest = false ; } } else { if ( Cmp == Cond . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) && is<ISA_LIT>LogicalCmp ( Cmp ) && Op . getNode ( ) -> hasOneUse ( ) ) { <STR_LIT> CCode = ( <STR_LIT> ) Cond . getOperand ( <NUM_LIT> ) . getConstantOperandVal ( <NUM_LIT> ) ; CCode = <STR_LIT> ( CCode ) ; CC = DAG . getConstant ( CCode , DL , <STR_LIT> ) ; SDNode * User = * Op . getNode ( ) -> use_begin ( ) ; if ( User -> getOpcode ( ) == <STR_LIT> ) { SDValue FalseBB = User -> getOperand ( <NUM_LIT> ) ; SDNode * NewBR = DAG . UpdateNodeOperands ( User , User -> getOperand ( <NUM_LIT> ) , Dest ) ; assert ( NewBR == User ) ; ( void ) NewBR ; Dest = FalseBB ; Chain = DAG . getNode ( <STR_LIT> , DL , Op . getValueType ( ) , Chain , Dest , CC , Cmp ) ; <STR_LIT> CCode = ( <STR_LIT> ) Cond . getOperand ( <NUM_LIT> ) .


<s> bool LaneCrossing [ <NUM_LIT> ] = { false , false } ; for ( int i = <NUM_LIT> ; i < Size ; ++ i ) if ( Mask [ i ] >= <NUM_LIT> && ( Mask [ i ] % Size ) / LaneSize != i / LaneSize ) LaneCrossing [ ( Mask [ i ] % Size ) / LaneSize ] = true ; if ( ! LaneCrossing [ <NUM_LIT> ] || ! LaneCrossing [ <NUM_LIT> ] ) return splitAndLowerVectorShuffle ( DL , VT , V1 , V2 , Mask , DAG ) ; } else { bool LaneUsed [ <NUM_LIT> ] = { false , false } ; for ( int i = <NUM_LIT> ; i < Size ; ++ i ) if ( Mask [ i ] >= <NUM_LIT> ) LaneUsed [ ( Mask [ i ] / LaneSize ) ] = true ; if ( ! LaneUsed [ <NUM_LIT> ] || ! LaneUsed [ <NUM_LIT> ] ) return splitAndLowerVectorShuffle ( DL , VT , V1 , V2 , Mask , DAG ) ; } assert ( V2 . isUndef ( ) && <STR_LIT> ) ; SmallVector < int , <NUM_LIT> > FlippedBlendMask ( Size ) ; for ( int i = <NUM_LIT> ; i < Size ; ++ i ) FlippedBlendMask [ i ] = Mask [ i ] < <NUM_LIT> ? - <NUM_LIT> : ( ( ( Mask [ i ] % Size

) / LaneSize == i / LaneSize ) ? Mask [ i ] : Mask [ i ] % LaneSize + ( i / LaneSize ) * LaneSize + Size ) ;


<s> msgpack :: MapDocNode <ISA_LIT>PALMetadata :: getShaderFunction ( StringRef Name ) { auto Functions =


<s>
const
MCSectionELF
*
CommentSection
=
Context
.
getELFSection
(
<STR_LIT>
,
ELF
::
SHT_PROGBITS
,
<NUM_LIT>
,
SectionKind
::
getReadOnly
(
)
)
;
OutStreamer
.
SwitchSection
(
CommentSection
)
;
if
(
STM
.
getGeneration
(
)
>=
AMDGPUSubtarget
::
SOUTHERN_ISLANDS
)
{
OutStreamer
.
emitRawComment
(
<STR_LIT>
,
false
)
;
OutStreamer
.
emitRawComment
(
<STR_LIT>
+
Twine
(
KernelInfo
.
CodeLen
)
,
false
)
;
OutStreamer
.
emitRawComment
(
<STR_LIT>
+
Twine
(
KernelInfo
.
NumSGPR
)
,
false
)
;
OutStreamer
.
emitRawComment
(
<STR_LIT>
+
Twine
(
KernelInfo
.
NumVGPR
)
,
false
)
;
}
else
{
R600MachineFunctionInfo
*
MFI
=
MF
.
getInfo
<
R600MachineFunctionInfo
>
(
)
;
OutStreamer
.
emitRawComment
(
Twine
(
<STR_LIT>
+
Twine
(
MFI
->
StackSize
)
)
)
;
}
}
if
(
STM
.
dumpCode
(
)
)
{
MF
.
dump
(
)
;
if
(
DisasmEnabled
)
{
OutStreamer
.
SwitchSection
(
Context
.
getELFSection
(
<STR_LIT>
,
ELF
::
SHT_NOTE
,
<NUM_LIT>
,
SectionKind
::
getReadOnly
(
)
)
)
;
for
(
size_t
i
=
<NUM_LIT>
;
i
<
DisasmLines
.
size
(
)
;
++
i
)
{
std
::
string
Comment
(
DisasmLineMaxLen
DisasmLines
[
i
]
.
size
(
)
,
' '
)
;
Comment
+=
<STR_LIT>
+
HexLines
[
i
]


<s> if ( i386_pe_dllimport_name_p ( oldname ) ) { warning ( <NUM_LIT> , <STR_LIT> , decl ) ; oldname += strlen ( DLL_IMPORT_PREFIX ) ; } else if ( i386_pe_dllexport_name_p ( oldname ) ) return ; newname = alloca ( strlen ( DLL_EXPORT_PREFIX ) + strlen ( oldname ) + <NUM_LIT> ) ; sprintf ( newname , <STR_LIT> , DLL_EXPORT_PREFIX , oldname ) ; idp = get_identifier ( newname ) ; symref = gen_rtx_SYMBOL_REF ( Pmode , IDENTIFIER_POINTER ( idp ) ) ; SYMBOL_REF_DECL ( symref ) = decl ; XEXP ( DECL_RTL ( decl )


<s> } } else { ImmInstrInfo III ; unsigned Opc = MI . getOpcode ( ) ; bool ConvertibleImmForm = Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ; if ( ! instrHasImmForm ( MI , III , true ) && ! ConvertibleImmForm ) return nullptr ; if ( ( Opc == <STR_LIT> || Opc == <STR_LIT> ) && MI . getOperand ( <NUM_LIT> ) . getReg ( ) == MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) return nullptr ; for ( int i = <NUM_LIT> , e = MI . getNumOperands ( ) ; i < e ; i ++ ) { MachineOperand & MO = MI . getOperand ( i ) ; SeenIntermediateUse = false ; if ( MO . isReg ( ) && MO . isUse ( ) && ! MO . isImplicit ( ) ) { MachineBasicBlock :: reverse_iterator E = MI . getParent ( ) -> rend ( ) , It = MI ; It ++ ; unsigned Reg = MI . getOperand ( i ) . getReg ( ) ; if ( <STR_LIT> . contains ( Reg ) ) Reg = Reg - <STR_LIT> + <STR_LIT> ; for ( ; It != E ; ++ It ) { if ( It -> modifiesRegister ( Reg , & getRegisterInfo ( ) ) ) { switch ( It -> getOpcode ( ) ) { default : break ; case


<s> const MCInstrDesc & MCID = MI . getDesc ( ) ; unsigned Binary = getBinaryCodeForInstr ( MI ) ; if ( MCID . Opcode == <STR_LIT> || MCID . Opcode == <STR_LIT> ) { emitWordLE ( Binary ) ; return ; } Binary |= II -> getPredicate ( & MI ) << <STR_LIT> ; Binary |= getAddrModeSBit ( MI , MCID ) ; unsigned NumDefs = MCID . getNumDefs ( ) ; unsigned OpIdx = <NUM_LIT> ; if ( NumDefs ) Binary |= getMachineOpValue ( MI , OpIdx ++ ) << <STR_LIT> ; else if ( ImplicitRd ) Binary |= ( II -> getRegisterInfo ( ) . getEncodingValue ( ImplicitRd ) << <STR_LIT> ) ; if ( MCID . Opcode == <STR_LIT> ) { unsigned Lo16 = getMovi32Value ( MI , MI . getOperand ( OpIdx ) , <STR_LIT> ) ; Binary |= Lo16 & <NUM_LIT> ; Binary |= ( ( Lo16 >> <NUM_LIT> ) & <NUM_LIT> ) << <NUM_LIT> ; emitWordLE ( Binary ) ; return ; } else if ( MCID . Opcode == <STR_LIT> ) { unsigned Hi16 = ( getMovi32Value ( MI , MI . getOperand ( OpIdx ) , <STR_LIT> ) >> <NUM_LIT> ) ; Binary |= Hi16 & <NUM_LIT> ; Binary |= ( ( Hi16 >> <NUM_LIT> ) & <NUM_LIT> ) << <NUM_LIT> ; emitWordLE ( Binary ) ; return ; } else if ( ( MCID . Opcode == <STR_LIT> ) || ( MCID . Opcode == <STR_LIT> ) ) { uint32_t v = ~ MI . getOperand ( <NUM_LIT> ) . getImm (


<s> unsigned NF = Node -> getNumOperands ( ) - <NUM_LIT> ; EVT VT = Node -> getOperand ( <NUM_LIT> ) -> getValueType ( <NUM_LIT> ) ; unsigned ScalarSize = VT . getScalarSizeInBits ( ) ; MVT XLenVT = Subtarget -> getXLenVT ( ) ; <ISA_LIT>VLMUL LMUL = getLMUL ( VT ) ; SDValue SEW = CurDAG -> getTargetConstant ( ScalarSize , DL , XLenVT ) ; SmallVector < SDValue , <NUM_LIT> > Regs ( Node -> op_begin ( ) + <NUM_LIT> , Node -> op_begin ( ) + <NUM_LIT> + NF ) ; SDValue StoreVal = createTuple ( * CurDAG , Regs , NF , LMUL ) ; SDValue Operands [ ] = { StoreVal , Node -> getOperand ( <NUM_LIT> + NF ) , Node -> getOperand ( <NUM_LIT> + NF ) , Node -> getOperand ( <NUM_LIT> + NF ) , SEW , Node -> getOperand ( <NUM_LIT> ) } ; EVT IndexVT = Node -> getOperand ( <NUM_LIT> + NF ) -> getValueType ( <NUM_LIT> ) ; <ISA_LIT>VLMUL IndexLMUL = getLMUL ( IndexVT ) ; unsigned IndexScalarSize = IndexVT . getScalarSizeInBits ( ) ; const <STR_LIT> * P = <STR_LIT> ( IntNo , IndexScalarSize , static_cast < unsigned > ( LMUL ) , static_cast < unsigned > ( IndexLMUL ) ) ; SDNode * Store = CurDAG -> getMachineNode ( P -> Pseudo , DL , Node -> getValueType ( <NUM_LIT> ) , Operands ) ; ReplaceNode ( Node


<s> rtx gen_compare_reg ( rtx cmp ) { return gen_compare_reg_1 ( GET_CODE ( cmp ) , XEXP ( cmp ,

<NUM_LIT> ) , XEXP ( cmp , <NUM_LIT> ) ) ;


<s> assert ( elementTy -> isSingleValueType ( ) && <STR_LIT> ) ; uint64_t arraySize = ( elementTy -> getPrimitiveSizeInBits ( ) >> <NUM_LIT> ) * numElements ; decl += utostr ( arraySize ) ; } decl += <STR_LIT> ; if ( gv -> hasInitializer ( ) ) { const Constant * C = gv -> getInitializer ( ) ; if ( const ConstantArray * CA = dyn_cast < ConstantArray > ( C ) ) { decl += <STR_LIT> ; for ( unsigned i = <NUM_LIT> , e = C -> getNumOperands ( ) ; i != e ; ++ i ) { if ( i > <NUM_LIT> ) decl += <STR_LIT> ; decl += <STR_LIT> + utohexstr ( cast < ConstantInt > ( CA -> getOperand ( i ) ) -> getZExtValue ( ) ) ; } decl += <STR_LIT> ; } } } else { decl += getTypeName ( gv -> getType


<s> static const unsigned GPREven3 [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; static const unsigned GPROdd3 [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; static const unsigned GPREven4 [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; static const unsigned GPROdd4 [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; static const unsigned GPREven5 [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; static const unsigned GPROdd5 [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; static const unsigned GPREven6 [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; static const unsigned GPROdd6 [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; if ( HintType == <STR_LIT> ) { if ( isPhysicalRegister ( HintReg ) && getRegisterPairEven ( HintReg , MF ) == <NUM_LIT> ) return std :: make_pair ( RC -> allocation_order_begin ( MF ) , RC -> allocation_order_end ( MF ) ) ; if ( ! TFI -> hasFP ( MF ) ) { if ( ! STI . isR9Reserved ( ) ) return std :: make_pair ( GPREven1 , GPREven1 + ( sizeof ( GPREven1 ) / sizeof ( unsigned ) ) ) ; else return std :: make_pair ( GPREven4 , GPREven4 + ( sizeof ( GPREven4 ) / sizeof ( unsigned ) ) ) ; } else if ( FramePtr == <STR_LIT> ) { if ( ! STI . isR9Reserved ( ) ) return std :: make_pair ( GPREven2 , GPREven2 + ( sizeof ( GPREven2 ) / sizeof ( unsigned ) ) ) ; else return std :: make_pair ( GPREven5 , GPREven5 + ( sizeof ( GPREven5 ) / sizeof ( unsigned ) ) ) ; } else { if ( ! STI . isR9Reserved ( ) ) return std :: make_pair ( GPREven3 , GPREven3 + ( sizeof ( GPREven3 ) / sizeof ( unsigned ) ) ) ; else return std :: make_pair ( GPREven6 , GPREven6 + ( sizeof ( GPREven6 ) / sizeof ( unsigned )


<s> OperandMatchResultTy <ISA_LIT>AsmParser :: parseMemBarrierOptOperand ( OperandVector & Operands ) { MCAsmParser & Parser = getParser ( ) ; SMLoc S = Parser . getTok ( ) . getLoc ( ) ; const AsmToken & Tok = Parser . getTok ( ) ; unsigned Opt ; if ( Tok . is ( AsmToken :: Identifier ) ) { StringRef OptStr = Tok . getString ( ) ; Opt = StringSwitch < unsigned > ( OptStr . slice ( <NUM_LIT> , OptStr . size ( ) ) . lower ( ) ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( ~ <NUM_LIT> ) ; if ( ! hasV8Ops ( ) && ( Opt == <STR_LIT> || Opt == <STR_LIT> || Opt == <STR_LIT> || Opt == <STR_LIT> ) ) Opt = ~ <NUM_LIT> ; if ( Opt == ~ <NUM_LIT> ) return MatchOperand_NoMatch ; Parser . Lex ( ) ; } else if ( Tok . is ( AsmToken :: Hash ) || Tok . is ( AsmToken :: Dollar ) || Tok . is ( AsmToken :: Integer ) ) { if ( Parser . getTok ( ) . isNot ( AsmToken :: Integer ) ) Parser . Lex ( ) ; SMLoc Loc = Parser . getTok ( ) . getLoc ( ) ; const MCExpr * MemBarrierID ; if ( getParser ( ) . parseExpression ( MemBarrierID ) ) { Error ( Loc , <STR_LIT> ) ; return MatchOperand_ParseFail ; } const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( MemBarrierID ) ; if ( ! CE ) { Error ( Loc , <STR_LIT> ) ; return MatchOperand_ParseFail ; } int Val = CE -> getValue ( ) ; if ( Val & ~ <NUM_LIT> ) { Error ( Loc , <STR_LIT> ) ; return MatchOperand_ParseFail ; } Opt = <STR_LIT> +


<s> if ( ! isTypeLegal ( I -> getOperand ( <NUM_LIT> ) -> getType ( ) , VT ) ) return false ; unsigned ResultReg = createResultReg ( & <STR_LIT> ) ; unsigned SetCCOpc ; bool SwapArgs ; switch ( CI -> getPredicate ( ) ) { case CmpInst :: FCMP_OEQ : { if ( ! <ISA_LIT>FastEmitCompare ( CI -> getOperand ( <NUM_LIT> ) , CI -> getOperand ( <NUM_LIT> ) , VT ) ) return false ; unsigned EReg = createResultReg ( & <STR_LIT> ) ; unsigned NPReg = createResultReg ( & <STR_LIT> ) ; BuildMI ( MBB , DL , TII . get ( <STR_LIT> ) , EReg ) ; BuildMI ( MBB , DL , TII . get ( <STR_LIT> ) , NPReg ) ; BuildMI ( MBB , DL , TII . get ( <STR_LIT> ) , ResultReg ) . addReg ( NPReg ) . addReg ( EReg ) ; UpdateValueMap ( I , ResultReg ) ; return true ; } case CmpInst :: FCMP_UNE : { if ( ! <ISA_LIT>FastEmitCompare ( CI -> getOperand ( <NUM_LIT> ) , CI -> getOperand ( <NUM_LIT> ) , VT ) ) return false ; unsigned NEReg = createResultReg ( & <STR_LIT> ) ; unsigned PReg = createResultReg ( & <STR_LIT> ) ; BuildMI ( MBB , DL , TII . get ( <STR_LIT> ) , NEReg ) ; BuildMI ( MBB , DL , TII . get ( <STR_LIT> ) , PReg ) ; BuildMI ( MBB , DL , TII . get ( <STR_LIT> ) , ResultReg ) . addReg ( PReg ) . addReg ( NEReg ) ; UpdateValueMap ( I , ResultReg ) ; return true ; } case CmpInst :: FCMP_OGT : SwapArgs = false ; SetCCOpc = <STR_LIT> ; break ; case CmpInst :: FCMP_OGE : SwapArgs = false ; SetCCOpc = <STR_LIT> ; break ; case CmpInst :: FCMP_OLT : SwapArgs = true ; SetCCOpc = <STR_LIT> ; break ; case CmpInst :: FCMP_OLE : SwapArgs = true ; SetCCOpc = <STR_LIT> ; break ; case CmpInst :: FCMP_ONE : SwapArgs = false ; SetCCOpc = <STR_LIT> ; break ; case CmpInst :: FCMP_ORD : SwapArgs = false ; SetCCOpc = <STR_LIT> ; break ; case CmpInst :: FCMP_UNO : SwapArgs = false ; SetCCOpc = <STR_LIT> ; break ; case CmpInst :: FCMP_UEQ : SwapArgs = false ; SetCCOpc = <STR_LIT> ;


<s> bool isNEONi16splatNot ( ) const { if ( ! isImm ( ) ) return false ; const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; if ( ! CE ) return false ; unsigned Value = CE -> getValue


<s> OutVT = <STR_LIT> ; } unsigned SubSizeInBits = SrcSizeInBits / <NUM_LIT> ; InVT = EVT :: getVectorVT ( Ctx , InVT , SubSizeInBits / InVT . getSizeInBits ( ) ) ; OutVT = EVT :: getVectorVT ( Ctx , OutVT , SubSizeInBits / OutVT . getSizeInBits ( ) ) ; SDValue Lo = extractSubVector ( In , <NUM_LIT> , DAG , DL , SubSizeInBits ) ; SDValue Hi = extractSubVector ( In , NumElems / <NUM_LIT> , DAG , DL , SubSizeInBits ) ; if ( SrcVT . is256BitVector ( ) && DstVT . is128BitVector ( ) ) { Lo = DAG . getBitcast ( InVT , Lo ) ; Hi = DAG . getBitcast (


<s> int smalloffset_mem_p ( rtx op ) { if ( GET_CODE ( op ) == MEM ) { rtx addr = XEXP ( op , <NUM_LIT> ) ; if ( GET_CODE ( addr ) == REG ) return BASE_REG_P ( addr , <NUM_LIT> ) ; if ( GET_CODE ( addr ) == PLUS ) { rtx offset = XEXP ( addr ,


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { const MachineOperand OpFI = MI . getOperand ( <NUM_LIT> ) ; if ( ! OpFI . isFI ( ) ) return <NUM_LIT> ; const MachineOperand OpOff = MI . getOperand ( <NUM_LIT> ) ; if ( ! OpOff . isImm ( ) || OpOff . getImm ( ) != <NUM_LIT> ) return <NUM_LIT> ; FrameIndex = OpFI . getIndex ( ) ; return MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; } case <STR_LIT> : case <STR_LIT>


<s> set = single_set ( insn ) ; if ( set && ! MEM_P ( SET_DEST ( set ) ) && reg_overlap_mentioned_p ( reg , SET_DEST ( set ) ) ) return true ; while ( ( insn = NEXT_INSN ( insn ) ) ) { rtx set ; if ( ! INSN_P ( insn ) ) continue ; code = GET_CODE ( insn ) ; if ( code == CODE_LABEL ) return <NUM_LIT> ; if ( code == JUMP_INSN ) return false ; else if ( code == INSN && GET_CODE ( PATTERN ( insn ) ) == SEQUENCE ) { rtx_sequence * seq = as_a < rtx_sequence * > ( PATTERN ( insn ) ) ; int i ; int retval = <NUM_LIT> ; for ( i = <NUM_LIT> ; i < seq -> len ( ) ; i ++ ) { rtx_insn * this_insn = seq -> insn ( i ) ; rtx set = single_set ( this_insn ) ; if ( CALL_P ( this_insn ) ) code = CALL_INSN ; else if ( JUMP_P ( this_insn ) ) { if ( INSN_ANNULLED_BRANCH_P ( this_insn ) ) return false ; code =


<s> auto * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; bool UsesWinAAPCS = isTargetWindows ( MF ) ; if ( UsesWinAAPCS && hasFP ( MF ) && AFI -> hasSwiftAsyncContext ( ) ) { int FrameIdx = MFI . CreateStackObject ( <NUM_LIT> , Align ( <NUM_LIT> ) , true ) ; AFI -> setSwiftAsyncContextFrameIdx ( FrameIdx ) ; if ( ( unsigned ) FrameIdx < MinCSFrameIndex ) MinCSFrameIndex = FrameIdx ; if ( ( unsigned ) FrameIdx > MaxCSFrameIndex ) MaxCSFrameIndex = FrameIdx ; } for ( auto & CS : CSI ) { Register Reg = CS . getReg ( ) ; const TargetRegisterClass * RC = RegInfo -> getMinimalPhysRegClass ( Reg ) ; unsigned Size = RegInfo -> getSpillSize ( * RC ) ; Align Alignment ( RegInfo -> getSpillAlign ( * RC ) ) ; int FrameIdx = MFI . CreateStackObject ( Size , Alignment , true ) ; CS . setFrameIdx (


<s> printAddrRegExtendOperand ( MI , OpNum , O , MemSize ,


<s> <ISA_LIT>TOCRegDeps ( ) : MachineFunctionPass ( ID ) { initialize<ISA_LIT>TOCRegDepsPass ( * PassRegistry ::


<s> rtx parts [ <NUM_LIT> ] ; int i , words ; unsigned regno = REGNO ( reg ) ; machine_mode mode = GET_MODE ( reg ) ; if ( TARGET_SPE && regno < <NUM_LIT> && ( SPE_VECTOR_MODE ( GET_MODE ( reg ) ) || ( TARGET_E500_DOUBLE && FLOAT_MODE_P ( mode ) && mode != SFmode && mode != SDmode && mode != SCmode ) ) ) ; else return NULL_RTX ; regno = REGNO ( reg ) ; words = ( GET_MODE_SIZE ( mode ) + UNITS_PER_FP_WORD - <NUM_LIT> ) / UNITS_PER_FP_WORD ; gcc_assert ( words <= <NUM_LIT> ) ; for ( i = <NUM_LIT> ; i < words ; i ++ , regno ++ ) { if ( BYTES_BIG_ENDIAN ) { parts [ <NUM_LIT> * i ] = gen_rtx_REG ( SImode , regno + FIRST_SPE_HIGH_REGNO ) ; parts [ <NUM_LIT> * i + <NUM_LIT> ] = gen_rtx_REG ( SImode , regno ) ; } else { parts [ <NUM_LIT> * i ] = gen_rtx_REG ( SImode , regno ) ; parts [ <NUM_LIT> * i + <NUM_LIT> ] = gen_rtx_REG ( SImode , regno + FIRST_SPE_HIGH_REGNO ) ; } } return gen_rtx_PARALLEL ( VOIDmode , gen_rtvec_v ( words


<s> OperandMatchResultTy <ISA_LIT>AsmParser :: ParseSImm19Value ( OperandVector & Operands ) { return ParseImmediate ( Operands ,


<s> switch ( MO . getTargetFlags ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : Kind = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ; break ; case <STR_LIT> : Kind = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_CALL ; break ; case <STR_LIT> : Kind = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_LO ; break ; case <STR_LIT> : Kind = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_HI ; break ; case <STR_LIT> : Kind = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_PCREL_LO ; break ; case


<s> return new <ISA_LIT>FrameAnalyzer ( )


<s> case ImmTyR128A16 : OS << <STR_LIT> ; break ; case ImmTyLWE : OS << <STR_LIT> ; break ; case ImmTyOff : OS << <STR_LIT> ; break ; case ImmTyExpTgt : OS << <STR_LIT> ; break ; case ImmTyExpCompr : OS << <STR_LIT> ; break ; case ImmTyExpVM : OS << <STR_LIT> ; break ; case ImmTyHwreg : OS << <STR_LIT> ; break ; case ImmTySendMsg : OS << <STR_LIT> ; break ; case ImmTyInterpSlot : OS << <STR_LIT> ; break ; case ImmTyInterpAttr : OS << <STR_LIT> ; break ; case ImmTyAttrChan : OS << <STR_LIT> ; break ; case ImmTyOpSel : OS << <STR_LIT> ; break ; case ImmTyOpSelHi : OS << <STR_LIT> ; break ; case ImmTyNegLo : OS << <STR_LIT> ; break ; case ImmTyNegHi : OS << <STR_LIT> ; break ; case ImmTySwizzle : OS << <STR_LIT> ; break ; case ImmTyGprIdxMode : OS << <STR_LIT> ; break ; case ImmTyHigh : OS << <STR_LIT> ; break ; case ImmTyBLGP : OS << <STR_LIT> ; break ; case ImmTyCBSZ : OS << <STR_LIT> ; break ; case ImmTyABID : OS << <STR_LIT> ; break ; case ImmTyEndpgm : OS << <STR_LIT> ;


<s> if ( UseNonLazyBind && F && F -> hasFnAttribute ( Attribute :: NonLazyBind ) && ! TM .

shouldAssumeDSOLocal ( * GV -> getParent ( ) , GV ) ) return <STR_LIT> ;


<s> EVT <ISA_LIT>TargetLowering :: getSetCCResultType (


<s> auto Op = MI -> getOperand ( OpNum ) ; auto CC = ( <STR_LIT> ) Op . getImm ( ) ; const char * Str = condCodeToString ( CC ) ; O << Str


<s> if ( mode == VOIDmode ) mode = DImode ; if ( TARGET_BIG_ENDIAN ? ! high_p : high_p ) byte = UNITS_PER_WORD ; else byte = <NUM_LIT> ; if ( MEM_P ( op ) ) { rtx addr = XEXP ( op , <NUM_LIT> ) ; if ( GET_CODE ( addr ) == PLUS || REG_P ( addr ) ) return

adjust_address ( op , word_mode , byte ) ;


<s> StringRef getPassName ( ) const override { return <STR_LIT>


<s> DEBUG ( dbgs ( ) << <STR_LIT> << NoBRIters << '\n' ) ; bool BRChange = false ; for ( unsigned i = <NUM_LIT> , e = ImmBranches . size ( ) ; i != e ; ++ i ) BRChange |= fixupImmediateBr ( ImmBranches [ i ] ) ; if ( BRChange && ++ NoBRIters > <NUM_LIT> ) report_fatal_error ( <STR_LIT> ) ; DEBUG ( dumpBBs ( ) ) ; if ( ! BRChange ) break ; MadeChange = true ; } verify ( )


<s> else { strcpy ( filename_buff , filespec ) ; decc$to_vms ( filespec , translate_unix , <NUM_LIT> , <NUM_LIT> ) ; strcpy ( new_host_filespec , filename_buff


<s> return __builtin_ia32_ucomieq ( ( __v4sf ) __A ,


<s> rtx_insn * x = emit_insn ( gen_addhi3 ( stack_pointer_rtx , stack_pointer_rtx , GEN_INT ( sign * size ) ) ) ; if ( size < <NUM_LIT> ) F ( x , <NUM_LIT> ) ; } else F ( emit_insn ( gen_addsi3 ( stack_pointer_rtx , stack_pointer_rtx , GEN_INT ( sign * size )


<s> return new <ISA_LIT>MCELFStreamer ( Context , MAB ,


<s> vec_uint4 v ; unsigned short s [ <NUM_LIT> ] ; } shmask ; shmask . v = ( ( vec_uint4 ) { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ; shmask . s [ ( ( si_to_uint ( a ) + ( unsigned int ) ( imm ) ) >> <NUM_LIT> ) & <NUM_LIT>


<s> case TargetStackID :: Default : case TargetStackID :: <ISA_LIT>Vector : case TargetStackID ::


<s> getGlobalAddressWrapper ( SDValue GA , const GlobalValue * GV , SelectionDAG & DAG ) { DebugLoc dl = GA . getDebugLoc ( ) ; if ( isa < Function > ( GV ) ) { return DAG . getNode ( <STR_LIT> , dl , <STR_LIT>


<s> SDValue <ISA_LIT>TargetLowering :: LowerGlobalAddress ( SDValue Op , SelectionDAG & DAG ) const { const GlobalValue * GV = cast < GlobalAddressSDNode > ( Op ) -> getGlobal ( ) ; int64_t Offset = cast < GlobalAddressSDNode > ( Op ) -> getOffset ( ) ; return LowerGlobalAddress ( GV , SDLoc ( Op )


<s> void printi64mem ( const MachineInstr * MI , unsigned OpNo ) { O << <STR_LIT> ; printMemReference ( MI


<s> SDLoc dl ( N ) ; LHS = DAG . getVectorShuffle ( <STR_LIT> , dl , LHS . getOperand ( <NUM_LIT> ) , LHS . getOperand ( <NUM_LIT> ) , { <NUM_LIT> , - <NUM_LIT> , <NUM_LIT> , - <NUM_LIT> } ) ; LHS = DAG . getBitcast ( <STR_LIT> , LHS ) ; return DAG . getNode ( N -> getOpcode ( ) , dl , <STR_LIT> , LHS , RHS ) ; } if ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT> && RHS . hasOneUse ( ) && ( RHS . getOpcode ( ) == <STR_LIT> || RHS . getOpcode ( ) == <STR_LIT> ) && RHS . getOperand ( <NUM_LIT> ) . getValueType ( ) == <STR_LIT> ) { SDLoc dl ( N ) ; RHS = DAG . getVectorShuffle ( <STR_LIT> , dl , RHS . getOperand ( <NUM_LIT> ) , RHS . getOperand ( <NUM_LIT> ) , { <NUM_LIT> , - <NUM_LIT> , <NUM_LIT> , - <NUM_LIT> } ) ; RHS = DAG . getBitcast ( <STR_LIT> , RHS


<s> switch ( RegNo ) { case <STR_LIT> : res = <NUM_LIT> ; break ; case <STR_LIT> : res = <NUM_LIT> ; break ; case <STR_LIT> : res = <NUM_LIT> ; break ; case <STR_LIT> : res = <NUM_LIT> ; break ; case <STR_LIT> : res = <NUM_LIT> ; break ; case <STR_LIT> : res = <NUM_LIT> ; break ; case <STR_LIT> : res = <NUM_LIT> ; break ; case <STR_LIT> : res = <NUM_LIT> ;


<s> getKillRegState ( KillSrc ) ; return ; } else if ( <STR_LIT> . contains ( SrcReg ) && <STR_LIT> . contains ( DestReg ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg ) ; getKillRegState ( KillSrc ) ; return ; } unsigned Opc ; if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) || <STR_LIT> . contains ( DestReg , SrcReg ) ) Opc = ( Subtarget . hasP9Vector ( ) ) ? <STR_LIT> : <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opc = <STR_LIT> ; else llvm_unreachable ( <STR_LIT> ) ; const MCInstrDesc & MCID = get ( Opc ) ; if ( MCID . getNumOperands ( ) == <NUM_LIT> ) BuildMI ( MBB , I , DL , MCID , DestReg

) . addReg ( SrcReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ;


<s> void Emitter < CodeEmitter > :: emitBranchInstruction ( const MachineInstr & MI ) { const TargetInstrDesc & TID = MI . getDesc ( ) ; if ( TID . Opcode == <STR_LIT> ) abort ( ) ; unsigned Binary = getBinaryCodeForInstr (


<s> <STR_LIT> :: OFFSET_SRC_PRIVATE_BASE ; unsigned WidthM1 = AS == <ISA_LIT>AS :: LOCAL_ADDRESS ? <STR_LIT> :: WIDTH_M1_SRC_SHARED_BASE : <STR_LIT> :: WIDTH_M1_SRC_PRIVATE_BASE ; unsigned Encoding = <STR_LIT> :: ID_MEM_BASES << <STR_LIT> :: ID_SHIFT_ | Offset << <STR_LIT> :: OFFSET_SHIFT_ | WidthM1 << <STR_LIT> :: WIDTH_M1_SHIFT_ ; SDValue EncodingImm = DAG . getTargetConstant ( Encoding , DL , <STR_LIT> ) ; SDValue ApertureReg = SDValue ( DAG . getMachineNode ( <STR_LIT> , DL , <STR_LIT> , EncodingImm ) , <NUM_LIT> ) ; SDValue ShiftAmount = DAG . getTargetConstant ( WidthM1 + <NUM_LIT> , DL , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , ApertureReg , ShiftAmount ) ; } MachineFunction & MF = DAG . getMachineFunction ( ) ; <ISA_LIT>MachineFunctionInfo * Info = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; Register UserSGPR = Info -> getQueuePtrUserSGPR ( ) ; assert ( UserSGPR != <STR_LIT> ) ; SDValue QueuePtr = CreateLiveInRegister ( DAG , & <STR_LIT> , UserSGPR , <STR_LIT> ) ; uint32_t StructOffset = ( AS == <ISA_LIT>AS :: LOCAL_ADDRESS ) ? <NUM_LIT> : <NUM_LIT> ; SDValue Ptr = DAG . getObjectPtrOffset ( DL , QueuePtr , TypeSize :: Fixed ( StructOffset ) ) ; MachinePointerInfo PtrInfo ( <ISA_LIT>AS :: CONSTANT_ADDRESS ) ; return DAG . getLoad ( <STR_LIT> , DL , QueuePtr . getValue ( <NUM_LIT> ) , Ptr , PtrInfo , commonAlignment ( Align ( <NUM_LIT> ) , StructOffset ) , MachineMemOperand

:: MODereferenceable | MachineMemOperand :: MOInvariant ) ;


<s> static inline bool is<ISA_LIT>LowRegister ( unsigned Reg ) { using namespace <ISA_LIT> ; switch ( Reg ) { case R0 : case R1 : case R2 : case R3 : case R4 : case R5 : case R6 : case R7 : return true ; default : return


<s> static MCStreamer * createMCStreamer ( const Triple & T , MCContext & Context , std :: unique_ptr < MCAsmBackend > && MAB , std :: unique_ptr < MCObjectWriter > && OW , std :: unique_ptr < MCCodeEmitter > && Emitter , bool RelaxAll ) { if ( ! T . isOSBinFormatELF (


<s> void addShifterOperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT> ) ; unsigned Imm = <STR_LIT> ( getShiftExtendType (


<s> if ( MF ) { const Function * F = MF -> getFunction ( ) ; ghcCall = ( F ? F -> getCallingConv (


<s> Chain ( MachineInstr * MI , unsigned Idx , Color C ) : StartInst ( MI ) , LastInst ( MI ) , KillInst ( nullptr ) , StartInstIdx ( Idx ) , LastInstIdx ( Idx ) , KillInstIdx ( <NUM_LIT> ) , LastColor ( C ) { Insts . insert (


<s> unsigned n = riscv_save_libcall_count ( mask ) ; ssize_t bytes = snprintf ( s , sizeof ( s )


<s> for ( auto & Op : MI -> operands ( ) ) { if ( ! Op . isReg ( ) || ! Op . isDef ( ) ) continue ; if ( HasDef ) return false ; HasDef = true ; } for ( auto & Mo : MI -> memoperands ( ) ) if ( Mo -> isVolatile ( ) || Mo -> isAtomic ( ) ) return false ; return


<s> const TargetInstrInfo * TII = TM . getSubtargetImpl ( ) -> getInstrInfo ( ) ; if ( Subtarget -> isTargetCygMing ( ) ) { unsigned CallOp = Subtarget -> is64Bit ( )


<s> if ( * regset == <NUM_LIT> ) { if ( CDX_LDSTWM_VALID_REGS_0 & ( <NUM_LIT> << regno ) ) * regset = CDX_LDSTWM_VALID_REGS_0 ; else if ( CDX_LDSTWM_VALID_REGS_1 & ( <NUM_LIT> << regno ) ) * regset = CDX_LDSTWM_VALID_REGS_1 ; else return false ; return true


<s> bool <ISA_LIT>16RegisterInfo :: requiresFrameIndexScavenging ( const MachineFunction


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , const std :: string & TT , const std :: string & FS ) : LLVMTargetMachine ( T , TT ) , Subtarget ( TT , FS ) , DataLayout ( <STR_LIT> <STR_LIT> ) , InstrInfo ( * this ) , TLInfo ( * this ) , TSInfo ( * this ) , FrameLowering ( Subtarget ) { if ( getRelocationModel ( ) == Reloc :: Default ) setRelocationModel


<s> assert ( MI -> getOperand ( OpNo ) . isReg ( ) && <STR_LIT> ) ; const MCOperand & OffsetOp = MI -> getOperand ( OpNo + <NUM_LIT> ) ; printOperand ( MI , OpNo , O ) ; if ( OffsetOp . isImm ( ) ) { int64_t Offset = OffsetOp . getImm ( ) ; if ( Offset >= <NUM_LIT> ) O << '+' ; O << Offset ; } else if ( OffsetOp . isExpr (


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( SLT == <STR_LIT> ) { return <NUM_LIT> * getFullRateInstrCost ( ) * LT . first * NElts ; } if ( ST -> has16BitInsts ( ) && SLT == <STR_LIT> ) NElts = ( NElts + <NUM_LIT> ) / <NUM_LIT> ; return LT . first * NElts * getFullRateInstrCost ( ) ; case <STR_LIT> : { const int QuarterRateCost = getQuarterRateInstrCost ( ) ; if ( SLT == <STR_LIT> ) { const int FullRateCost = getFullRateInstrCost ( ) ; return ( <NUM_LIT> * QuarterRateCost + ( <NUM_LIT> * <NUM_LIT> ) * FullRateCost ) * LT . first * NElts ; } if ( ST -> has16BitInsts ( ) && SLT == <STR_LIT> ) NElts = ( NElts + <NUM_LIT> ) / <NUM_LIT> ; return QuarterRateCost * NElts * LT . first ; } case <STR_LIT> : if ( CxtI && CxtI -> hasOneUse ( ) ) if ( const auto * FAdd = dyn_cast < BinaryOperator > ( * CxtI -> user_begin ( ) ) ) { const int OPC = TLI -> InstructionOpcodeToISD ( FAdd -> getOpcode ( ) ) ; if ( OPC == <STR_LIT> || OPC == <STR_LIT> ) { if ( ST -> hasMadMacF32Insts ( ) && SLT == <STR_LIT> && ! HasFP32Denormals ) return TargetTransformInfo :: TCC_Free ; if ( ST -> has16BitInsts ( ) && SLT == <STR_LIT> && ! HasFP64FP16Denormals ) return TargetTransformInfo :: TCC_Free ; const TargetOptions & Options = TLI -> getTargetMachine ( ) . Options ; if ( Options . AllowFPOpFusion == FPOpFusion :: Fast || Options . UnsafeFPMath || ( FAdd -> hasAllowContract ( ) && CxtI -> hasAllowContract ( ) ) ) return TargetTransformInfo :: TCC_Free ; } } LLVM_FALLTHROUGH ; case <STR_LIT> : case <STR_LIT> : if ( SLT == <STR_LIT> ) return LT . first * NElts * get64BitInstrCost ( ) ; if ( ST -> has16BitInsts ( ) && SLT == <STR_LIT> ) NElts = ( NElts + <NUM_LIT> ) / <NUM_LIT> ; if ( SLT == <STR_LIT> || SLT == <STR_LIT> ) return LT . first * NElts * getFullRateInstrCost ( ) ; break ; case <STR_LIT> : case <STR_LIT> : if ( SLT == <STR_LIT> ) { int Cost = <NUM_LIT> * get64BitInstrCost ( ) + <NUM_LIT> * getQuarterRateInstrCost ( ) ; if ( ! ST -> hasUsableDivScaleConditionOutput ( ) ) Cost += <NUM_LIT>


<s> const <ISA_LIT>Subtarget & STI = MI -> getMF ( ) -> getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( MMO -> getSize ( ) == <NUM_LIT> && ( ! STI . systemSupportsUnalignedAccess ( ) && MMO -> getAlign ( ) < MMO -> getSize ( ) ) ) return true ; } return false


<s> const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; if ( ! DCI . isBeforeLegalizeOps ( ) && <STR_LIT> ( In . getNode ( ) ) && In . hasOneUse ( ) ) { auto * Ld = cast < LoadSDNode > ( In ) ; if ( Ld -> isSimple ( ) ) { MVT SVT = In . getSimpleValueType ( ) . getVectorElementType ( ) ; <STR_LIT> Ext = N -> getOpcode ( ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; EVT MemVT = EVT :: getVectorVT ( * DAG . getContext ( ) , SVT , VT . getVectorNumElements ( ) ) ; if ( TLI . isLoadExtLegal ( Ext , VT , MemVT ) ) { SDValue Load = DAG . getExtLoad ( Ext , SDLoc ( N ) , VT , Ld -> getChain ( ) , Ld -> getBasePtr ( ) , Ld -> getPointerInfo ( ) , MemVT , Ld -> getOriginalAlign ( ) , Ld -> getMemOperand ( ) -> getFlags ( ) ) ; DAG . ReplaceAllUsesOfValueWith ( SDValue ( Ld , <NUM_LIT> ) , Load . getValue ( <NUM_LIT> ) ) ; return Load ; } } } if ( Subtarget . hasAVX ( ) && N -> getOpcode ( )


<s> static const unsigned SpillOffsetTable [ ] [ <NUM_LIT> ] = { { <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> } } ; RegSpillOffsets . grow ( <STR_LIT>


<s> assert ( Op . getOperand ( <NUM_LIT> ) . isUndef ( ) && <STR_LIT> ) ; EVT VTs [ ] = { Op . getValueType ( ) , <STR_LIT> } ; SDValue Ops [ ] = { Op . getOperand ( <NUM_LIT> ) , Ptr } ; return DAG . getNode ( <STR_LIT> , DL


<s> temp . val [ <NUM_LIT> ] = vcombine_u16 ( val . val [ <NUM_LIT> ] , vcreate_u16 ( __AARCH64_UINT64_C ( <NUM_LIT> ) ) ) ; temp . val [ <NUM_LIT> ] = vcombine_u16 ( val . val [ <NUM_LIT> ] , vcreate_u16 ( __AARCH64_UINT64_C ( <NUM_LIT> ) ) ) ; __o = __builtin_aarch64_set_qregciv8hi ( __o , ( int16x8_t ) temp . val [ <NUM_LIT> ] , <NUM_LIT> ) ; __o = __builtin_aarch64_set_qregciv8hi ( __o , ( int16x8_t ) temp . val [ <NUM_LIT> ] , <NUM_LIT> ) ; __o = __builtin_aarch64_set_qregciv8hi ( __o , ( int16x8_t ) temp . val [ <NUM_LIT>


<s> const Type * InitTy = GV -> getInitializer ( ) -> getType ( ) ; GlobalVariable * ClonedGV = new GlobalVariable ( InitTy , false , GV -> getLinkage ( ) , GV -> getInitializer ( ) ) ; ClonedGV -> setName ( PAN :: getCloneVarName ( FnName , VarName ) ) ; Globals . push_back


<s> int <ISA_LIT>FunctionInfo :: createLRSpillSlot ( MachineFunction & MF ) { if ( LRSpillSlotSet ) { return LRSpillSlot ; } const TargetRegisterClass & RC = <STR_LIT> ; const TargetRegisterInfo & TRI = * MF . getSubtarget ( ) . getRegisterInfo ( ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; if ( ! MF . getFunction ( ) . isVarArg ( ) ) { LRSpillSlot = MFI . CreateFixedObject ( TRI . getSpillSize ( RC ) , <NUM_LIT> , true ) ; } else { LRSpillSlot = MFI . CreateStackObject ( TRI . getSpillSize ( RC

) , TRI . getSpillAlignment ( RC ) , true ) ;


<s> case AMDGPU :: BRANCH_COND_f32 : return AMDGPU :: IF_LOGICALZ_f32 ; default : llvm_unreachable ( <STR_LIT> ) ; } return - <NUM_LIT>


<s> static DecodeStatus DecodeCR64BitRegisterClass ( MCInst & Inst , uint64_t RegNo , uint64_t Address , const MCDisassembler * Decoder ) { return decodeRegisterClass ( Inst , RegNo


<s> tree fn = ( tree ) decl ; struct cgraph_node * node = NULL ; struct cgraph_node * default_node = NULL ; struct cgraph_function_version_info * node_v = NULL ; struct cgraph_function_version_info * first_v = NULL ; tree dispatch_decl = NULL ; struct cgraph_function_version_info * default_version_info = NULL ; gcc_assert ( fn != NULL && DECL_FUNCTION_VERSIONED ( fn ) ) ; node = cgraph_node :: get ( fn ) ; gcc_assert ( node != NULL ) ; node_v = node -> function_version ( ) ; gcc_assert ( node_v != NULL ) ; if ( node_v -> dispatcher_resolver != NULL ) return node_v -> dispatcher_resolver ; first_v = node_v ; while ( first_v -> prev != NULL ) first_v = first_v -> prev ; default_version_info = first_v ; while ( default_version_info != NULL ) { if ( is_function_default_version ( default_version_info -> this_node -> decl ) ) break ; default_version_info = default_version_info -> next ; } if ( default_version_info == NULL ) return NULL ; if ( first_v != default_version_info ) { default_version_info -> prev -> next = default_version_info -> next ; if ( default_version_info -> next ) default_version_info -> next -> prev = default_version_info -> prev ; first_v -> prev = default_version_info ; default_version_info -> next = first_v ; default_version_info -> prev = NULL ; } default_node = default_version_info -> this_node ; if ( targetm . has_ifunc_p ( ) ) { struct cgraph_function_version_info * it_v = NULL ; struct cgraph_node * dispatcher_node = NULL ; struct cgraph_function_version_info * dispatcher_version_info = NULL ; dispatch_decl = make_dispatcher_decl ( default_node -> decl ) ; dispatcher_node = cgraph_node :: get_create ( dispatch_decl


<s> builtin_types [ type ] . scalar_ptr = build_pointer_type ( eltype ) ; builtin_types [ type ] . scalar_const_ptr = build_const_pointer ( eltype ) ; if ( ! riscv_v_ext_vector_mode_p ( mode ) ) return ; tree vectype = build_vector_type_for_mode ( eltype , mode ) ; gcc_assert ( VECTOR_MODE_P ( TYPE_MODE ( vectype ) ) && TYPE_MODE ( vectype ) == mode && TYPE_MODE_RAW ( vectype ) == mode && TYPE_ALIGN ( vectype ) <= <NUM_LIT> && known_eq ( tree_to_poly_uint64 ( TYPE_SIZE ( vectype ) ) , GET_MODE_BITSIZE ( mode ) ) ) ; vectype = build_distinct_type_copy ( vectype ) ; gcc_assert ( vectype == TYPE_MAIN_VARIANT ( vectype ) ) ; SET_TYPE_STRUCTURAL_EQUALITY ( vectype ) ; TYPE_ARTIFICIAL ( vectype ) = <NUM_LIT> ; TYPE_INDIVISIBLE_P ( vectype ) = <NUM_LIT> ; add_vector_type_attribute ( vectype , vector_types [ type ] . mangled_name ) ; make_type_sizeless ( vectype ) ; abi_vector_types [ type ] =


<s> return castRequiresQueuePtr ( ASC -> getSrcAddressSpace ( )


<s> static unsigned translateShiftImm ( unsigned imm ) { if ( imm == <NUM_LIT> ) return <NUM_LIT> ; return


<s> BitVector <ISA_LIT>RegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; const TargetFrameLowering * TFI = MF . getTarget ( ) . getFrameLowering ( ) ; if ( TFI -> hasFP ( MF ) ) { Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT>


<s> setAvailableFeatures ( ComputeAvailableFeatures ( STI .


<s> if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) return Error ( L , <STR_LIT> ) ; Parser . Lex ( ) ; if ( ! hasThumb ( ) ) return Error (


<s> uint32_t FixupOffset = Layout . getFragmentOffset ( Fragment ) + Fixup . getOffset ( ) ; if ( Fixup . getTargetKind ( ) == <STR_LIT> ) FixupOffset &= ~ uint32_t ( <NUM_LIT> ) ; return FixupOffset


<s> assert ( i < <STR_LIT> && <STR_LIT> ) ; return UserReservedRegister [ i ]


<s> return ( __m64 ) __builtin_ia32_psignd ( ( __v2si ) __X , (


<s> if ( strncmp ( name , <STR_LIT> , <NUM_LIT> ) == <NUM_LIT> ) { if ( decl && TREE_CODE ( decl ) == VAR_DECL && DECL_INITIAL ( decl ) ==


<s> bool legitimate_pic_operand_p ( rtx x ) { if ( pic_address_needs_scratch ( x ) ) return false ; if ( SPARC_SYMBOL_REF_TLS_P ( x ) || ( GET_CODE ( x ) == CONST && GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == PLUS && SPARC_SYMBOL_REF_TLS_P ( XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) ) ) ) return false ; return true


<s> BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) ) . add ( MI . getOperand ( <NUM_LIT> ) ) ; break ; } case <STR_LIT> : { auto Dst = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; auto TrueValue = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; auto FalseValue = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) ) . addImm ( <NUM_LIT> ) ; BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) ) . addReg ( Dst ) . addReg ( <STR_LIT> ) . addReg ( FalseValue ) ; BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) ) . addImm ( <NUM_LIT> ) ; BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) ) . addReg ( Dst ) . addReg ( <STR_LIT> ) . addReg ( TrueValue ) ; break ; } case <STR_LIT> : { auto Dst = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; auto ConditionCode = <STR_LIT> ( MI . getOperand ( <NUM_LIT> ) . getImm ( ) ) ; auto TrueValue = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; auto FalseValue = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; resolveComparison ( MBB , MI , DL , ConditionCode , MI . getOperand ( <NUM_LIT> ) , MI . getOperand ( <NUM_LIT> ) ) ; BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) ) . addImm ( <NUM_LIT> ) ; BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) ) . addReg ( Dst ) . addReg ( <STR_LIT> ) . addReg ( FalseValue ) ; BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) ) . addImm ( <NUM_LIT> ) ; BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) ) . addReg ( Dst ) . addReg ( <STR_LIT> ) . addReg ( TrueValue ) ; break ; } case <STR_LIT> : { MachineOperand & op = MI . getOperand ( <NUM_LIT> ) ; if ( op . isMBB ( ) ) { MachineBasicBlock * dst = op . getMBB ( ) ; BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) ) . addMBB ( dst ) ; }


<s> if ( ! SomeVT . isVector ( ) ) return false ; return SomeVT . getVectorElementType ( )


<s> O << <STR_LIT> ; printMemOffset ( MI , OpNo


<s> if ( isLiteralConstant ( MO , OpSize ) ) return true ; if ( ! MO . isReg ( ) || ! MO . isUse ( ) ) return false ; if ( TargetRegisterInfo :: isVirtualRegister ( MO . getReg ( ) ) ) return RI . isSGPRClass ( MRI . getRegClass


<s> case TYPE_R16 : case TYPE_R32 : case TYPE_R64 : case TYPE_Rv : case TYPE_MM64 : case TYPE_XMM : case TYPE_XMM32 : case TYPE_XMM64 : case TYPE_XMM128 : case TYPE_XMM256 : case TYPE_XMM512 : case TYPE_VK1 : case TYPE_VK8 : case TYPE_VK16 : case TYPE_DEBUGREG : case TYPE_CONTROLREG : return translateRMRegister ( mcInst , insn ) ; case TYPE_M : case TYPE_M8 : case TYPE_M16 : case TYPE_M32 : case TYPE_M64 : case TYPE_M128 : case TYPE_M256 : case TYPE_M512 : case


<s> size_t len = <NUM_LIT> ; sysctlbyname ( <STR_LIT> , & l1_line , & len , NULL , <NUM_LIT> ) ; l1_sizekb = <NUM_LIT> ; l1_assoc =


<s> for ( const MDOperand & Op : Node -> operands ( ) ) { const ConstantInt * CI = mdconst :: extract < ConstantInt > ( Op ) ; V . push_back ( CI -> getZExtValue


<s> if ( IsATT ) O << '%' ; O << <ISA_LIT>ATTInstPrinter :: getRegisterName ( MO . getReg ( ) ) ; return ; } case MachineOperand :: MO_Immediate : if ( IsATT ) O << '$' ; O << MO . getImm ( ) ; return ; case MachineOperand :: MO_ConstantPoolIndex : case MachineOperand :: MO_GlobalAddress : { if ( IsATT ) O << '$' ; PrintSymbolOperand ( MO ,


<s> <STR_LIT> :: Kernel :: CodeProps :: Metadata <ISA_LIT>AsmPrinter :: getHSACodeProps ( const MachineFunction & MF , const <ISA_LIT>ProgramInfo & ProgramInfo ) const { const <ISA_LIT>Subtarget & STM = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; const <ISA_LIT>MachineFunctionInfo & MFI = * MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; HSAMD :: Kernel :: CodeProps :: Metadata HSACodeProps ; HSACodeProps . mKernargSegmentSize = STM . getKernArgSegmentSize ( MF , MFI . getABIArgOffset ( ) ) ; HSACodeProps . mGroupSegmentFixedSize = ProgramInfo . LDSSize ; HSACodeProps . mPrivateSegmentFixedSize = ProgramInfo . ScratchSize ; HSACodeProps . mKernargSegmentAlign = std :: max ( uint32_t ( <NUM_LIT> ) , MFI . getMaxKernArgAlign ( ) ) ; HSACodeProps . mWavefrontSize = STM . getWavefrontSize ( ) ; HSACodeProps . mNumSGPRs = CurrentProgramInfo . NumSGPR ; HSACodeProps . mNumVGPRs = CurrentProgramInfo . NumVGPR ; HSACodeProps . mMaxFlatWorkGroupSize = MFI . getMaxFlatWorkGroupSize ( ) ; HSACodeProps . mIsDynamicCallStack =


<s> SDValue <ISA_LIT>TargetLowering :: LowerFixedLengthVectorIntExtendToSVE ( SDValue Op , SelectionDAG & DAG ) const { EVT VT = Op . getValueType ( ) ; assert ( VT . isFixedLengthVector ( ) && <STR_LIT> ) ; SDLoc DL ( Op ) ; SDValue Val = Op . getOperand ( <NUM_LIT> ) ; EVT ContainerVT = getContainerForFixedLengthVector ( DAG , Val . getValueType ( ) ) ; Val = convertToScalableVector ( DAG , ContainerVT , Val ) ; bool Signed = Op . getOpcode ( ) == <STR_LIT> ; unsigned ExtendOpc = Signed ? <STR_LIT> : <STR_LIT> ; switch ( ContainerVT . getSimpleVT ( ) . SimpleTy ) { default : llvm_unreachable ( <STR_LIT> )


<s> unsigned <ISA_LIT>MCCodeEmitter :: fixMulHigh ( const MCInst & MI , unsigned EncodedValue , const MCSubtargetInfo & STI ) const { EncodedValue |= <NUM_LIT> << <NUM_LIT> ; return EncodedValue


<s> MachineInstr & MI = * II ; const MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ; const MachineFrameInfo * MFI = & MF . getFrameInfo ( ) ; unsigned FI = MI . getOperand ( FIOperandNum ) . getIndex ( ) ; unsigned ImmOpIdx = <NUM_LIT> ; switch ( MI . getOpcode ( ) ) { default : return ; case <STR_LIT> : case <STR_LIT> : ImmOpIdx = FIOperandNum + <NUM_LIT> ; break ; } MachineOperand & ImmOp = MI . getOperand


<s> bool GCNPassConfig :: addRegAssignAndRewriteOptimized ( ) { if ( ! usingDefaultRegAlloc ( ) ) report_fatal_error ( RegAllocOptNotSupportedMessage ) ; addPass ( createSGPRAllocPass ( true ) ) ; addPass ( createVirtRegRewriter ( false ) ) ; addPass ( & <ISA_LIT>LowerSGPRSpillsID ) ; addPass ( createVGPRAllocPass ( true


<s> for ( const SDep & PI : SU -> Preds ) { unsigned PredReadyCycle = PI . getSUnit ( ) -> TopReadyCycle ; unsigned MinLatency = PI . getLatency ( ) ; Top . MaxMinLatency = std :: max ( MinLatency , Top . MaxMinLatency ) ; if ( SU -> TopReadyCycle < PredReadyCycle + MinLatency ) SU -> TopReadyCycle = PredReadyCycle + MinLatency ; } Top . releaseNode ( SU , SU


<s> unsigned long long Reg ; std :: pair < bool , bool > R = parsePhysicalReg ( C , Prefix , Reg ) ; if ( ! R . first ) return std :: make_pair ( <NUM_LIT> , nullptr ) ; if ( ( Prefix == <STR_LIT> || Prefix == <STR_LIT> ) ) { if ( R . second ) return std :: make_pair ( <NUM_LIT> , nullptr ) ; RC = TRI -> getRegClass ( Prefix == <STR_LIT> ? <STR_LIT> : <STR_LIT> ) ; return std :: make_pair ( * ( RC -> begin ( ) ) , RC ) ; } else if ( Prefix . compare ( <NUM_LIT> , <NUM_LIT> , <STR_LIT> ) == <NUM_LIT> ) { if ( R . second ) return std :: make_pair ( <NUM_LIT> , nullptr ) ; Reg = StringSwitch < unsigned long long > ( Prefix ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( <NUM_LIT> ) ; if ( ! Reg ) return std :: make_pair ( <NUM_LIT> , nullptr


<s> Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT>


<s> case ImmTyDppCtrl : OS << <STR_LIT> ; break ; case ImmTyDppRowMask : OS << <STR_LIT> ; break ; case ImmTyDppBankMask : OS << <STR_LIT> ; break ; case ImmTyDppBoundCtrl : OS << <STR_LIT> ; break ; case ImmTySdwaDstSel : OS << <STR_LIT> ; break ; case ImmTySdwaSrc0Sel : OS << <STR_LIT> ; break ; case ImmTySdwaSrc1Sel : OS << <STR_LIT> ; break ; case ImmTySdwaDstUnused : OS << <STR_LIT> ; break ; case ImmTyDMask : OS << <STR_LIT> ; break ; case ImmTyUNorm : OS << <STR_LIT> ; break ; case ImmTyDA : OS << <STR_LIT> ; break ; case ImmTyR128 : OS << <STR_LIT> ; break ; case ImmTyLWE : OS << <STR_LIT> ; break ; case ImmTyOff : OS << <STR_LIT> ; break ; case ImmTyExpTgt : OS << <STR_LIT> ; break ; case ImmTyExpCompr : OS << <STR_LIT> ; break ; case ImmTyExpVM : OS << <STR_LIT> ; break ; case ImmTyHwreg : OS << <STR_LIT> ; break ; case ImmTySendMsg : OS << <STR_LIT> ; break ; case ImmTyInterpSlot : OS <<


<s> break ; case ENCODING_IB : if ( Opcode != <STR_LIT> && Opcode != <STR_LIT> && Opcode != <STR_LIT> && Opcode != <STR_LIT> && Opcode != <STR_LIT> && Opcode != <STR_LIT> && Opcode != <STR_LIT> && Opcode != <STR_LIT> && Opcode != <STR_LIT> && Opcode != <STR_LIT> && Opcode != <STR_LIT> && Opcode != <STR_LIT> && Opcode != <STR_LIT> && Opcode != <STR_LIT> && Opcode != <STR_LIT> && Opcode != <STR_LIT> && Opcode != <STR_LIT> ) type = TYPE_MOFFS8 ; break ; case ENCODING_IW : type = TYPE_MOFFS16 ; break ; case ENCODING_ID : type = TYPE_MOFFS32 ; break ; case ENCODING_IO : type = TYPE_MOFFS64 ; break ; } } switch ( type ) { case TYPE_XMM128 : mcInst . addOperand ( MCOperand :: CreateReg ( <STR_LIT> + ( immediate >> <NUM_LIT> ) ) ) ; return ; case TYPE_XMM256 : mcInst . addOperand ( MCOperand :: CreateReg ( <STR_LIT> + ( immediate >> <NUM_LIT> ) ) ) ; return ; case


<s> static bool isSGetReg ( unsigned Opcode ) { return Opcode ==


<s> MaxInstLength = <NUM_LIT> ; SeparatorString = <STR_LIT> ; CommentString = <STR_LIT> ; InlineAsmStart = <STR_LIT> ; InlineAsmEnd = <STR_LIT> ; ZeroDirective = <STR_LIT> ; AsciiDirective = <STR_LIT> ; AscizDirective = <STR_LIT> ; Data8bitsDirective = <STR_LIT> ; Data16bitsDirective = <STR_LIT> ; Data32bitsDirective = <STR_LIT> ; Data64bitsDirective = <STR_LIT> ; SunStyleELFSectionSwitchSyntax = true ; UsesELFSectionDirectiveForBSS = true ; GlobalDirective = <STR_LIT> ; HasSetDirective = false ; HasAggressiveSymbolFolding = true ; COMMDirectiveAlignmentIsInBytes = false


<s> getSymbol ( MO . getGlobal ( ) ) -> print ( O , MAI ) ; if ( Offset )


<s> EVT PtrVT = Op . getValueType ( ) ; SDValue Res ; if ( CP -> isMachineConstantPoolEntry ( ) ) { Res = DAG . getTargetConstantPool ( CP -> getMachineCPVal ( ) , PtrVT , CP -> getAlignment


<s> IsThumb = true ; if ( Len >= <NUM_LIT> && TT [ <NUM_LIT> ] == 'v' ) Idx = <NUM_LIT> ; } if ( Idx ) { unsigned SubVer = TT [ Idx ] ; if ( SubVer > '4' && SubVer <= '9' ) { if ( SubVer >= '6' ) <ISA_LIT>ArchVersion = V6 ; else if ( SubVer == '5' ) { <ISA_LIT>ArchVersion = V5T ; if ( Len >= Idx + <NUM_LIT> && TT [ Idx + <NUM_LIT> ] == 't' && TT [ Idx + <NUM_LIT> ] == 'e' ) <ISA_LIT>ArchVersion = V5TE ; } } } if ( Len >= <NUM_LIT> ) { if ( TT . find ( <STR_LIT> ) != std :: string :: npos ) TargetType = isDarwin ; } else if ( TT . empty ( ) ) { TargetType =


<s> case AMDGPU :: <ISA_LIT>_ELSE : Else ( MI ) ; break ; case AMDGPU :: <ISA_LIT>_BREAK : Break ( MI ) ; break ; case AMDGPU :: <ISA_LIT>_IF_BREAK : IfBreak ( MI ) ; break ; case AMDGPU :: <ISA_LIT>_ELSE_BREAK : ElseBreak ( MI ) ; break ; case AMDGPU :: <ISA_LIT>_LOOP : ++ Depth ; Loop ( MI ) ; break ; case AMDGPU :: <ISA_LIT>_END_CF : if ( -- Depth == <NUM_LIT> && HaveKill ) { SkipIfDead ( MI ) ; HaveKill = false ; } EndCf ( MI ) ; break ; case AMDGPU :: <ISA_LIT>_KILL : if ( Depth == <NUM_LIT> ) SkipIfDead ( MI ) ; else HaveKill = true ; Kill ( MI ) ; break ; case AMDGPU :: S_BRANCH : Branch ( MI ) ; break ; case AMDGPU :: <ISA_LIT>_INDIRECT_SRC : IndirectSrc ( MI ) ; break ; case AMDGPU :: <ISA_LIT>_INDIRECT_DST_V2 : case AMDGPU :: <ISA_LIT>_INDIRECT_DST_V4 : case AMDGPU :: <ISA_LIT>_INDIRECT_DST_V8 : case AMDGPU :: <ISA_LIT>_INDIRECT_DST_V16


<s> const <ISA_LIT>Subtarget & Subtarget = DAG . getMachineFunction ( ) . getSubtarget < <ISA_LIT>Subtarget > ( ) ; ConstantSDNode * ConstantSize = dyn_cast < ConstantSDNode > ( Size ) ; if ( Subtarget . hasMVEIntegerOps ( ) && shouldGenerateInlineTPLoop ( Subtarget , DAG , ConstantSize , Alignment , true ) ) return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Chain , Dst , Src , DAG . getZExtOrTrunc ( Size , dl , <STR_LIT> ) ) ; if ( Alignment < Align ( <NUM_LIT> ) ) return SDValue ( ) ; if ( ! ConstantSize ) return EmitSpecializedLibcall ( DAG , dl , Chain , Dst , Src , Size , Alignment . value ( ) , RTLIB :: MEMCPY ) ; uint64_t SizeVal = ConstantSize -> getZExtValue ( ) ; if ( ! AlwaysInline && SizeVal > Subtarget . getMaxInlineSizeThreshold ( ) ) return EmitSpecializedLibcall ( DAG , dl , Chain , Dst , Src , Size , Alignment . value ( ) , RTLIB :: MEMCPY ) ; unsigned BytesLeft = SizeVal & <NUM_LIT> ; unsigned NumMemOps = SizeVal >> <NUM_LIT> ; unsigned EmittedNumMemOps = <NUM_LIT> ; EVT VT = <STR_LIT> ; unsigned VTSize = <NUM_LIT> ; unsigned i = <NUM_LIT> ; const unsigned MaxLoadsInLDM = Subtarget . isThumb1Only ( ) ? <NUM_LIT> : <NUM_LIT> ; SDValue TFOps [ <NUM_LIT> ] ; SDValue Loads [ <NUM_LIT> ] ; uint64_t SrcOff = <NUM_LIT> , DstOff = <NUM_LIT> ; unsigned NumMEMCPYs = ( NumMemOps + MaxLoadsInLDM - <NUM_LIT> ) / MaxLoadsInLDM ; if ( NumMEMCPYs > <NUM_LIT> && Subtarget . hasMinSize ( ) ) { return SDValue ( ) ; } SDVTList VTs = DAG . getVTList ( <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> ) ; for ( unsigned I = <NUM_LIT> ; I != NumMEMCPYs ; ++ I ) { unsigned NextEmittedNumMemOps = NumMemOps * ( I + <NUM_LIT> ) / NumMEMCPYs ; unsigned NumRegs = NextEmittedNumMemOps - EmittedNumMemOps ; Dst = DAG . getNode ( <STR_LIT> , dl , VTs , Chain , Dst , Src , DAG . getConstant ( NumRegs , dl , <STR_LIT> ) ) ; Src = Dst . getValue ( <NUM_LIT> ) ; Chain = Dst . getValue ( <NUM_LIT> ) ; DstPtrInfo = DstPtrInfo . getWithOffset ( NumRegs * VTSize ) ; SrcPtrInfo = SrcPtrInfo . getWithOffset ( NumRegs * VTSize ) ; EmittedNumMemOps = NextEmittedNumMemOps ; } if ( BytesLeft == <NUM_LIT>


<s> SmallString < <NUM_LIT> > Str ; raw_svector_ostream OS ( Str ) ; printInstruction ( MI , OS )


<s> if ( UseImm ) { unsigned Opc = isThumb2 ? <STR_LIT> : <STR_LIT> ; unsigned ImmReg = createResultReg ( TLI . getRegClassFor ( <STR_LIT> ) ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( Opc ) , ImmReg ) . addImm ( Imm ) ) ; return ImmReg ; } } if ( VT != <STR_LIT> ) return false ; unsigned DestReg = createResultReg ( TLI . getRegClassFor ( VT ) ) ; unsigned Align = TD . getPrefTypeAlignment ( C -> getType ( ) ) ; if ( Align == <NUM_LIT> ) { Align = TD . getTypeAllocSize ( C -> getType ( ) ) ; } unsigned Idx = MCP . getConstantPoolIndex ( C , Align ) ; if ( isThumb2 ) AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII

. get ( <STR_LIT> ) , DestReg ) . addConstantPoolIndex ( Idx ) ) ;


<s> case REG : operands [ i + <NUM_LIT> ] = gen_rtx_REG ( HImode , REGNO ( operands [ i ] ) ) ; break ; case CONST_INT : operands [ i + <NUM_LIT> ] = GEN_INT ( ( INTVAL ( operands [ i ] ) & <NUM_LIT> ) + ( ( char ) INTVAL ( operands [ i + <NUM_LIT> ] ) ) * <NUM_LIT> ) ; break ; case


<s> <ISA_LIT>GenSubtargetInfo ( TT , GPU , FS ) , <ISA_LIT>Subtarget ( TT ) , TargetTriple ( TT ) , Gen ( SOUTHERN_ISLANDS ) , IsaVersion ( ISAVersion0_0_0 ) , InstrItins ( getInstrItineraryForCPU ( GPU ) ) , LDSBankCount ( <NUM_LIT> ) , MaxPrivateElementSize ( <NUM_LIT> ) , FastFMAF32 ( false ) , HalfRate64Ops ( false ) , FP64FP16Denormals ( false ) , DX10Clamp ( false ) , FlatForGlobal ( false ) , AutoWaitcntBeforeBarrier ( false ) , CodeObjectV3 ( false ) , UnalignedScratchAccess ( false ) , UnalignedBufferAccess ( false ) , HasApertureRegs ( false ) , EnableXNACK ( false ) , TrapHandler ( false ) , DebuggerInsertNops ( false ) , DebuggerEmitPrologue ( false ) , EnableHugePrivateBuffer ( false ) , EnableLoadStoreOpt ( false ) , EnableUnsafeDSOffsetFolding ( false ) , Enable<ISA_LIT>Scheduler ( false ) , EnableDS128 ( false ) , EnablePRTStrictNull ( false ) , DumpCode ( false ) , FP64 ( false ) , GCN3Encoding ( false ) , CIInsts ( false ) , VIInsts ( false ) , GFX9Insts ( false ) , SGPRInitBug ( false ) , HasSMemRealTime ( false ) , HasIntClamp ( false ) , HasFmaMixInsts ( false ) , HasMovrel ( false ) , HasVGPRIndexMode ( false ) , HasScalarStores ( false ) , HasScalarAtomics ( false ) , HasSDWAOmod ( false ) , HasSDWAScalar ( false ) , HasSDWASdst ( false ) , HasSDWAMac ( false ) , HasSDWAOutModsVOPC ( false ) , HasDPP ( false ) , HasR128A16 ( false ) , HasDLInsts ( false ) , HasDotInsts ( false ) , EnableSRAMECC ( false ) , FlatAddressSpace ( false ) , FlatInstOffsets ( false ) , FlatGlobalInsts ( false ) , FlatScratchInsts ( false ) , AddNoCarryInsts ( false ) , HasUnpackedD16VMem ( false ) , ScalarizeGlobal ( false ) , FeatureDisable ( false ) , InstrInfo ( initializeSubtargetDependencies ( TT , GPU , FS ) ) , TLInfo ( TM , * this ) , FrameLowering ( TargetFrameLowering :: StackGrowsUp , getStackAlignment ( ) , <NUM_LIT> ) { CallLoweringInfo . reset ( new <ISA_LIT>CallLowering ( * getTargetLowering ( ) ) ) ; Legalizer . reset ( new <ISA_LIT>LegalizerInfo (