<s> In = extractSubVector ( In , <NUM_LIT> , DAG , DL , std :: max ( <NUM_LIT> , ( unsigned ) VT . getSizeInBits ( ) / Scale ) ) ; InVT = In . getValueType ( ) ; } if ( VT . getVectorNumElements ( ) != InVT . getVectorNumElements ( ) ) Opcode = getOpcode_EXTEND_VECTOR_INREG ( Opcode ) ; return DAG . getNode ( Opcode , DL , VT


<s> SDValue SizeNode = DAG . getConstant ( Flags . getByValSize ( ) , dl , <STR_LIT> ) ; return DAG . getMemcpy ( Chain , dl , Dst , Src , SizeNode , Flags . getNonZeroByValAlign ( ) , false , true , false , MachinePointerInfo ( )


<s> LastMappingSymbols [ getPreviousSection ( ) . first ] = LastEMS ; LastEMS = LastMappingSymbols . lookup


<s> return ( __mmask8 ) __builtin_ia32_ptestmq128 ( ( __v2di ) __A , ( __v2di ) __B , (


<s> if ( type > <NUM_LIT> ) { return Relocator :: Unknown ; } return ApplyFunctions [ type ] . func ( pRelocation , * this


<s> std :: tie ( RegOp , OMod ) = isOMod ( MI ) ; if ( OMod == <STR_LIT> || ! RegOp -> isReg ( ) || RegOp -> getSubReg ( ) != <STR_LIT> || ! MRI -> hasOneNonDBGUser ( RegOp -> getReg ( ) ) ) return false ; MachineInstr * Def = MRI -> getVRegDef ( RegOp -> getReg ( ) ) ; MachineOperand * DefOMod = TII -> getNamedOperand ( * Def , <STR_LIT> :: omod ) ; if ( ! DefOMod || DefOMod -> getImm ( ) != <STR_LIT> ) return false ; if ( TII -> hasModifiersSet ( * Def , <STR_LIT> :: clamp ) ) return false ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << MI << <STR_LIT> << *


<s> SpillGPRRegs . HighGPR = High ; SpillGPRRegs . GPROffset = Offs


<s> bool AMDGPUInstrInfo :: DefinesPredicate ( MachineInstr * MI , std :: vector < MachineOperand > & Pred ) const { return false


<s> } FixedVectorType * PtrTy = cast < FixedVectorType > ( Ptr -> getType ( ) ) ; if ( PtrTy -> getNumElements ( ) != <NUM_LIT> || MemoryTy -> getScalarSizeInBits ( ) == <NUM_LIT> ) return nullptr ; Value * Zero = ConstantInt :: get ( Builder . getInt32Ty ( ) , <NUM_LIT> ) ; Value * BasePtr = Builder . CreateIntToPtr ( Zero , Builder . getInt8PtrTy ( ) ) ; Offsets = Builder . CreatePtrToInt ( Ptr , FixedVectorType :: get ( Builder . getInt32Ty ( ) ,


<s> virtual const <ISA_LIT>65816Subtarget * getSubtargetImpl ( ) const { return & Subtarget


<s> MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; MFI . setHasCopyImplyingStackAdjustment ( true ) ; } TargetLoweringBase :: finalizeLowering ( MF


<s> FunctionPass * llvm :: create<ISA_LIT>OptimizePICCallPass ( <ISA_LIT>TargetMachine & TM ) { return new OptimizePICCall


<s> else if ( ( mode == VOIDmode && UHWORD_INT ( INTVAL ( x ) ) ) || ( mode != VOIDmode && const_uhword_operand ( x , mode ) ) ) { * total = COSTS_N_INSNS ( <NUM_LIT> ) ; return true ; } else if ( outer_code == MEM && ctable_addr_operand ( x , VOIDmode ) ) { * total = COSTS_N_INSNS ( <NUM_LIT> ) ; return true ; } else { * total = COSTS_N_INSNS ( <NUM_LIT> ) ; return true ; } case LABEL_REF : case SYMBOL_REF : case CONST : { * total = COSTS_N_INSNS ( <NUM_LIT> ) ; return true ; } case CONST_DOUBLE : { * total = COSTS_N_INSNS ( <NUM_LIT> ) ; return true ; } case CONST_WIDE_INT : { gcc_unreachable ( ) ; return true ; } case SET : { int factor ; mode = GET_MODE ( SET_DEST ( x ) ) ; factor = CEIL ( GET_MODE_SIZE ( mode ) , GET_MODE_SIZE ( SImode ) ) ; * total = factor * COSTS_N_INSNS ( <NUM_LIT> ) ; return false ; } case MULT : { * total = COSTS_N_INSNS ( <NUM_LIT> ) ; return false ; } case PLUS : { rtx op0 = XEXP ( x , <NUM_LIT> ) ; rtx op1 = XEXP ( x , <NUM_LIT> ) ; machine_mode op1_mode = GET_MODE


<s> case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : if ( ( int ) CI -> getSExtValue ( ) == CI -> getSExtValue ( ) ) Opc = <STR_LIT> ; break ; } if ( Opc ) { addFullAddress ( BuildMI ( MBB , DL , TII . get ( Opc ) ) , AM ) . addImm ( CI -> getSExtValue ( ) ) ; return true ; } } unsigned ValReg = getRegForValue ( Val ) ; if ( ValReg == <NUM_LIT> ) return


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT>


<s> __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) ,


<s> return ; case <STR_LIT> : O << <STR_LIT> ; return ; case <STR_LIT> : O << <STR_LIT> ; return ; case <STR_LIT> : O << <STR_LIT> ; return ; case <STR_LIT> : O << <STR_LIT> ; return ; case <STR_LIT> : O << <STR_LIT> ; return ; case <STR_LIT> : O << <STR_LIT> ; return ; case <STR_LIT> : O << <STR_LIT> ; return ; case <STR_LIT> : O << <STR_LIT> ; return ; case <STR_LIT> : O << <STR_LIT> ; return ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : llvm_unreachable ( <STR_LIT> ) ; default : break ; } unsigned RegIdx = MRI . getEncodingValue ( RegNo ) & ( ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) ; unsigned NumRegs ; if ( MRI . getRegClass ( <STR_LIT> ) . contains ( RegNo ) ) { O << 'v' ; NumRegs = <NUM_LIT> ; } else if ( MRI . getRegClass ( <STR_LIT> ) . contains ( RegNo ) ) { O << 's' ; NumRegs = <NUM_LIT> ; } else if ( MRI . getRegClass ( <STR_LIT> ) . contains ( RegNo ) ) { O << 'v' ; NumRegs = <NUM_LIT> ; } else if ( MRI . getRegClass ( <STR_LIT> ) . contains ( RegNo ) ) { O << 's' ; NumRegs = <NUM_LIT> ; } else if ( MRI . getRegClass ( <STR_LIT> ) . contains ( RegNo ) ) { O << 'v' ; NumRegs = <NUM_LIT> ; } else if ( MRI . getRegClass ( <STR_LIT> ) . contains ( RegNo ) ) { O << 's' ; NumRegs = <NUM_LIT> ; } else if ( MRI . getRegClass ( <STR_LIT> ) .


<s> bool isAdd = true ; const MCOperand & MO = MI . getOperand ( OpIdx ) ; if ( ! MO . isReg ( ) ) { Reg = get<ISA_LIT>RegisterNumbering ( <STR_LIT> ) ; Imm8 = <NUM_LIT> ; isAdd = false ; assert ( MO . isExpr ( ) && <STR_LIT> ) ; const MCExpr * Expr = MO . getExpr ( ) ; MCFixupKind Kind = MCFixupKind ( <STR_LIT>


<s> else if ( CONST_INT_P ( y_hi ) ) insn = emit_insn ( gen_cmpsi3_imm_carryin_CC_NVout ( scratch , x_hi , y_hi , cmp1 ) ) ; else insn = emit_insn ( gen_cmpsi3_carryin_CC_NVout ( scratch , x_hi , y_hi , cmp1 ) ) ; return SET_DEST ( single_set ( insn ) ) ; } case LE : case GT : { gcc_assert ( arm_const_double_prefer_rsbs_rsc ( y ) ) ; if ( ! const_ok_for_arm ( INTVAL ( y_lo ) ) ) y_lo = force_reg ( SImode , y_lo ) ; rtx cmp1 = gen_rtx_LTU ( DImode , arm_gen_compare_reg ( LTU , y_lo , x_lo , scratch ) , const0_rtx ) ; rtx_insn * insn = emit_insn ( gen_rscsi3_CC_NVout_scratch ( scratch , y_hi , x_hi , cmp1 ) ) ; return SET_DEST ( single_set ( insn ) ) ; } case LTU : case GEU : { if ( y_lo == const0_rtx ) { if ( ! arm_add_operand ( y_hi , SImode ) ) y_hi = force_reg ( SImode , y_hi ) ; return arm_gen_compare_reg ( code , x_hi , y_hi , NULL_RTX ) ; } if ( ! arm_add_operand ( y_lo , SImode ) ) y_lo = force_reg ( SImode , y_lo ) ; rtx cmp1 = gen_rtx_LTU ( DImode , arm_gen_compare_reg ( LTU , x_lo , y_lo , NULL_RTX ) , const0_rtx ) ; if ( ! scratch ) scratch = gen_rtx_SCRATCH ( SImode ) ; if ( ! arm_not_operand ( y_hi , SImode ) ) y_hi = force_reg ( SImode , y_hi ) ; rtx_insn * insn ; if ( y_hi == const0_rtx ) insn = emit_insn ( gen_cmpsi3_0_carryin_CC_Bout ( scratch , x_hi , cmp1 ) ) ; else if ( CONST_INT_P ( y_hi ) ) { y_hi = GEN_INT ( UINTVAL ( y_hi ) & <NUM_LIT> ) ; insn = emit_insn ( gen_cmpsi3_imm_carryin_CC_Bout ( scratch , x_hi , y_hi , cmp1 ) ) ; } else insn = emit_insn ( gen_cmpsi3_carryin_CC_Bout ( scratch , x_hi , y_hi , cmp1 ) ) ; return SET_DEST ( single_set ( insn ) ) ; } case LEU : case GTU : { gcc_assert ( arm_const_double_prefer_rsbs_rsc ( y ) ) ; if ( ! const_ok_for_arm ( INTVAL ( y_lo ) ) ) y_lo = force_reg ( SImode , y_lo ) ; rtx cmp1 = gen_rtx_LTU ( DImode , arm_gen_compare_reg ( LTU , y_lo , x_lo , scratch )


<s> MachineBasicBlock * TmpLB = const_cast < MachineBasicBlock * > ( LB ) ; SmallVector < MachineOperand , <NUM_LIT> > Cond ; bool BadLB = TII -> analyzeBranch ( * TmpLB , TB , FB , Cond , false ) ; if ( BadLB || Cond . size ( ) != <NUM_LIT> ) return ; if ( ! TII -> PredOpcodeHasJMP_c ( Cond [ <NUM_LIT> ] . getImm ( ) ) ) return ; if ( TB != HB && FB != HB ) return ; assert ( Cond [ <NUM_LIT> ] . isReg ( ) && <STR_LIT> ) ; unsigned PR = Cond [ <NUM_LIT> ] . getReg ( ) ; assert ( MRI -> getRegClass ( PR ) == & <STR_LIT> ) ; unsigned CmpR1 = <NUM_LIT> , CmpR2 = <NUM_LIT> ; const MachineInstr * CmpI = MRI -> getVRegDef ( PR ) ; while ( CmpI -> getOpcode ( ) == <STR_LIT> ) CmpI = MRI -> getVRegDef ( CmpI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; int Mask = <NUM_LIT> , Val = <NUM_LIT> ; bool OkCI = TII -> analyzeCompare ( * CmpI , CmpR1 , CmpR2 , Mask , Val ) ; if ( ! OkCI ) return ; if ( CmpR1 && MRI -> getRegClass ( CmpR1 ) != DoubleRC ) CmpR1 = <NUM_LIT> ; if ( CmpR2 && MRI -> getRegClass ( CmpR2 ) != DoubleRC ) CmpR2 = <NUM_LIT> ; if ( ! CmpR1 &&


<s> if ( getRelaxedOpcodeBranch ( Inst , false ) != Inst . getOpcode ( ) ) return true ; if ( getRelaxedOpcodeArith ( Inst ) == Inst . getOpcode ( ) ) return false ; unsigned RelaxableOp = Inst . getNumOperands ( ) - <NUM_LIT> ; if ( Inst . getOperand ( RelaxableOp ) . isExpr ( ) ) return true ; return false


<s> MCCodeEmitter * llvm :: create<ISA_LIT>MCCodeEmitter ( const MCInstrInfo & MCII , const MCSubtargetInfo & STI , MCContext & Ctx ) { return new <ISA_LIT>MCCodeEmitter ( MCII , STI , Ctx


<s> return ( __m128i ) __builtin_ia32_pcmpeqw128 ( ( __v8hi ) __A ,


<s> } Carry = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Carry , DAG . getConstant ( CCValid , DL , <STR_LIT> ) , DAG . getConstant ( CCMask , DL , <STR_LIT> ) ) ; SDVTList VTs = DAG . getVTList ( VT , <STR_LIT> ) ; SDValue Result = DAG . getNode ( BaseOp , DL , VTs , LHS , RHS , Carry ) ; SDValue SetCC = emitSETCC ( DAG , DL , Result . getValue ( <NUM_LIT> ) , CCValid , CCMask ) ; if ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT> ) SetCC = DAG . getNode ( <STR_LIT> , DL ,


<s> const <ISA_LIT>MCExpr * <ISA_LIT>MCExpr :: create ( const MCExpr * Expr , VariantKind Kind , MCContext & Ctx ) { return new ( Ctx ) <ISA_LIT>MCExpr ( Expr ,


<s> addVectorLoadStoreOperands ( Node , Log2SEW , DL , CurOp , IsMasked , false , Operands , true ) ; const <STR_LIT> * P = <STR_LIT> ( NF , IsMasked , false , true , Log2SEW , static_cast < unsigned > ( LMUL ) ) ; MachineSDNode * Load = CurDAG -> getMachineNode ( P -> Pseudo , DL , <STR_LIT> , <STR_LIT> , <STR_LIT> , Operands ) ; SDNode * ReadVL = CurDAG -> getMachineNode ( <STR_LIT> , DL , XLenVT , SDValue ( Load , <NUM_LIT> ) ) ; if ( auto * MemOp = dyn_cast < MemSDNode > ( Node ) ) CurDAG -> setNodeMemRefs ( Load , { MemOp -> getMemOperand ( ) } ) ; SDValue SuperReg = SDValue ( Load , <NUM_LIT>


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , const std :: string & TT , const std :: string & FS ) : LLVMTargetMachine ( T , TT ) , Subtarget ( TT , FS ) , DataLayout ( <STR_LIT> <STR_LIT> ) , InstrInfo ( * this ) , TLInfo ( * this ) , TSInfo ( * this ) , FrameInfo ( TargetFrameInfo

:: StackGrowsDown , <NUM_LIT> , - <NUM_LIT> ) {


<s> } else { if ( ContainerVT . isInteger ( ) ) PassThru = DAG . getConstant ( <NUM_LIT> , DL , ContainerVT ) ; else PassThru = DAG . getConstantFP ( <NUM_LIT> , DL , ContainerVT ) ; if ( isZerosVector ( Load -> getPassThru ( ) . getNode ( ) ) ) IsPassThruZeroOrUndef = true ; } auto NewLoad = DAG . getMaskedLoad ( ContainerVT , DL , Load -> getChain ( ) , Load -> getBasePtr ( ) , Load -> getOffset ( ) , Mask , PassThru , Load -> getMemoryVT ( ) , Load -> getMemOperand ( ) , Load -> getAddressingMode ( ) , Load -> getExtensionType ( ) ) ; if ( ! IsPassThruZeroOrUndef


<s> EVT PartVT = TLI . getRegisterType ( Context , VT ) ; Type * PartTy = PartVT . getTypeForEVT ( Context ) ; for ( unsigned i = <NUM_LIT> ; i < NumParts ; ++ i ) { ArgInfo Info = ArgInfo { MRI . createGenericVirtualRegister ( getLLTForType ( * PartTy , DL ) ) , PartTy , OrigArg . Flags } ; SplitArgs . push_back ( Info ) ; SplitRegs . push_back ( Info . Reg ) ; } PerformArgSplit ( SplitRegs ) ; return


<s>
UnspilledCSGPR
=
Reg
;
UnspilledCSGPRPaired
=
PairedReg
;
}
continue
;
}
if
(
produceCompactUnwindFrame
(
MF
)
&&
PairedReg
!=
<STR_LIT>
&&
!
SavedRegs
.
test
(
PairedReg
)
)
{
SavedRegs
.
set
(
PairedReg
)
;
if
(
<STR_LIT>
.
contains
(
PairedReg
)
&&
!
RegInfo
->
isReservedReg
(
MF
,
PairedReg
)
)
ExtraCSSpill
=
PairedReg
;
}
}
unsigned
CSStackSize
=
<NUM_LIT>
;
const
TargetRegisterInfo
*
TRI
=
MF
.
getSubtarget
(
)
.
getRegisterInfo
(
)
;
const
MachineRegisterInfo
&
MRI
=
MF
.
getRegInfo
(
)
;
for
(
unsigned
Reg
:
SavedRegs
.
set_bits
(
)
)
CSStackSize
+=
TRI
->
getRegSizeInBits
(
Reg
,
MRI
)
/
<NUM_LIT>
;
unsigned
NumSavedRegs
=
SavedRegs
.
count
(
)
;
unsigned
EstimatedStackSize
=
MFI
.
estimateStackSize
(
MF
)
;
if
(
hasFP
(
MF
)
||
windowsRequiresStackProbe
(
MF
,
EstimatedStackSize
+
CSStackSize
+
<NUM_LIT>
)
)
{
SavedRegs
.
set
(
<STR_LIT>
)
;
SavedRegs
.
set
(
<STR_LIT>
)
;
}
LLVM_DEBUG
(
dbgs
(
)
<<
<STR_LIT>
;
for
(
unsigned
Reg
:
SavedRegs
.
set_bits
(
)
)
dbgs
(
)
<<
' '
<<
printReg
(
Reg
,
RegInfo
)
;
dbgs
(
)
<<
<STR_LIT>
;
)
;
bool
CanEliminateFrame
=
SavedRegs
.
count
(
)
==
<NUM_LIT>
;
unsigned
EstimatedStackSizeLimit
=
estimateRSStackSizeLimit
(
MF
)
;
bool
BigStack
=
(
EstimatedStackSize
+
CSStackSize
)
>
EstimatedStackSizeLimit
;
if
(
BigStack
||
!
CanEliminateFrame
||
RegInfo
->
cannotEliminateFrame
(
MF
)
)
AFI
->
setHasStackFrame
(
true
)
;
if
(
BigStack
)
{
if
(
!
ExtraCSSpill
&&
UnspilledCSGPR
!=
<STR_LIT>
)
{
LLVM_DEBUG
(
dbgs
(
)
<<
<STR_LIT>
<<
printReg
(
UnspilledCSGPR
,
RegInfo
)
<<
<STR_LIT>
)
;
SavedRegs
.
set
(
UnspilledCSGPR
)
;
if
(
produceCompactUnwindFrame
(
MF
)
)
SavedRegs
.
set
(
UnspilledCSGPRPaired
)
;
ExtraCSSpill
=
UnspilledCSGPRPaired
;
}
if
(
!
ExtraCSSpill
||
MF
.
getRegInfo
(
)
.
isPhysRegUsed
(
ExtraCSSpill
)
)
{
const
TargetRegisterInfo
*
TRI
=
MF
.
getSubtarget
(
)
.
getRegisterInfo
(
)
;
const
TargetRegisterClass
&
RC
=
<STR_LIT>
;
unsigned
Size
=
TRI
->
getSpillSize
(
RC
)
;
unsigned
Align
=
TRI
->
getSpillAlignment
(
RC
)
;
int
FI
=
MFI
.
CreateStackObject
(


<s> NewMIs . push_back ( addFrameReference ( BuildMI ( MF , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) , FrameIdx ) ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { NewMIs . push_back ( addFrameReference ( BuildMI ( MF , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) , FrameIdx ) ) ; return true ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { NewMIs . push_back ( addFrameReference ( BuildMI ( MF , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) , FrameIdx ) ) ; return true ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { NewMIs . push_back ( addFrameReference ( BuildMI ( MF , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) , FrameIdx ) ) ; NonRI = true ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { NewMIs . push_back ( addFrameReference ( BuildMI ( MF , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) , FrameIdx ) ) ; NonRI = true ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { NewMIs . push_back ( addFrameReference ( BuildMI ( MF , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) , FrameIdx ) ) ; NonRI = true ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { assert ( TM . getSubtargetImpl ( ) -> isDarwin ( ) && <STR_LIT>


<s> static const MCPhysReg GeneralSubRegDecoderTable [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , } ; return DecodeRegisterClass ( Inst ,


<s> <ISA_LIT>TargetMachine & get<ISA_LIT>TargetMachine ( ) const { return getTM < <ISA_LIT>TargetMachine >


<s> rtx elt ; bool b ; op = gen_lowpart ( related_int_vector_mode ( GET_MODE ( op ) ) . require ( ) , op ) ; gcc_assert ( ! ! start == ! ! end ) ; if ( ! const_vec_duplicate_p ( op , & elt ) || ! CONST_INT_P ( elt ) ) return false ; size = GET_MODE_UNIT_BITSIZE ( GET_MODE ( op ) ) ; if ( size > <NUM_LIT> ) return


<s> Info . setScratchRSrcReg ( PrivateSegmentBufferReg ) ; if ( MFI . hasCalls ( ) ) { unsigned ReservedOffsetReg = TRI . reservedPrivateSegmentWaveByteOffsetReg ( MF ) ; Info . setScratchWaveOffsetReg ( ReservedOffsetReg ) ; } else { unsigned PrivateSegmentWaveByteOffsetReg = Info . getPreloadedReg ( <STR_LIT> ) ; Info . setScratchWaveOffsetReg ( PrivateSegmentWaveByteOffsetReg ) ; } } else { unsigned ReservedBufferReg = TRI . reservedPrivateSegmentBufferReg ( MF ) ; unsigned ReservedOffsetReg = TRI . reservedPrivateSegmentWaveByteOffsetReg ( MF ) ; Info . setScratchRSrcReg ( ReservedBufferReg ) ; Info . setScratchWaveOffsetReg ( ReservedOffsetReg ) ; } } else { unsigned ReservedBufferReg = TRI . reservedPrivateSegmentBufferReg ( MF ) ; Info . setScratchRSrcReg ( ReservedBufferReg ) ; if ( HasStackObjects && ! MFI . hasCalls ( ) ) { unsigned ScratchWaveOffsetReg = Info . getPreloadedReg ( <STR_LIT> ) ; Info . setScratchWaveOffsetReg ( ScratchWaveOffsetReg ) ; }


<s> unsigned <ISA_LIT>MCCodeEmitter :: fixLoadStoreExclusive ( const MCInst & MI , unsigned

EncodedValue , const MCSubtargetInfo & STI ) const {


<s> if ( mips_ls2 . alu1_turn_p ) { if ( cpu_unit_reservation_p ( curr_state , mips_ls2 . alu1_core_unit_code ) ) mips_ls2 . alu1_turn_p = false ; } else { if ( cpu_unit_reservation_p ( curr_state , mips_ls2 . alu2_core_unit_code ) ) mips_ls2 . alu1_turn_p = true ; } if ( mips_ls2 . falu1_turn_p ) { if ( cpu_unit_reservation_p ( curr_state , mips_ls2 . falu1_core_unit_code ) ) mips_ls2 . falu1_turn_p = false ; } else { if ( cpu_unit_reservation_p ( curr_state , mips_ls2 . falu2_core_unit_code ) ) mips_ls2 . falu1_turn_p


<s> gcc_assert ( MEM_P ( mem ) ) ; addr = XEXP ( mem , <NUM_LIT> ) ; switch ( GET_CODE ( addr ) ) { case PRE_DEC : templ = <STR_LIT> ; ops [ <NUM_LIT> ] = XEXP ( addr , <NUM_LIT> ) ; ops [ <NUM_LIT> ] = reg ; break ; case POST_INC : templ = <STR_LIT> ; ops [ <NUM_LIT> ] = XEXP ( addr , <NUM_LIT> ) ; ops [ <NUM_LIT> ] = reg ; break ; default : templ = <STR_LIT> ; ops [ <NUM_LIT> ] = reg ; ops [ <NUM_LIT> ] = mem ; break ; } sprintf ( buff , templ , load ? <STR_LIT> : <STR_LIT> , dp ? <STR_LIT> : sp ? <STR_LIT> : <STR_LIT> , dp ? <STR_LIT> : <STR_LIT> , integer_p ? <STR_LIT> : <STR_LIT> ) ; output_asm_insn ( buff , ops


<s> unsigned Reg = StringSwitch < unsigned > ( RegName ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( <NUM_LIT> ) ; if ( Reg ) return Reg ; report_fatal_error ( Twine ( <STR_LIT> + StringRef ( RegName ) + <STR_LIT>


<s> return ( __m128 ) __builtin_ia32_gathersiv4sf ( ( __v4sf ) src , base , ( __v4si ) index


<s> i = strlen ( const_str ) ; str = ( char * ) alloca ( i + <NUM_LIT> ) ; memcpy ( str , const_str , i + <NUM_LIT> ) ; while ( <NUM_LIT> ) { dash = strchr ( str , '-' ) ; if ( ! dash ) { warning ( <NUM_LIT> , <STR_LIT> ) ; return ; } * dash = '\0' ; comma = strchr ( dash + <NUM_LIT> , ',' ) ; if ( comma ) * comma = '\0' ; first = decode_reg_name ( str ) ; if ( first < <NUM_LIT> ) { warning ( <NUM_LIT> , <STR_LIT> , str ) ; return ; } last = decode_reg_name ( dash + <NUM_LIT> ) ; if ( last < <NUM_LIT> ) { warning ( <NUM_LIT> , <STR_LIT> , dash + <NUM_LIT> ) ; return ; } * dash =


<s> for ( SDNode * U : DAG . getEntryNode ( ) . getNode ( ) -> uses ( ) ) { if ( LoadSDNode * L = dyn_cast < LoadSDNode > ( U ) ) { if ( FrameIndexSDNode * FI = dyn_cast < FrameIndexSDNode > ( L -> getBasePtr ( ) ) ) { if ( FI -> getIndex ( ) < <NUM_LIT> ) { int64_t InFirstByte = MFI . getObjectOffset ( FI -> getIndex ( ) ) ; int64_t InLastByte = InFirstByte ; InLastByte += MFI . getObjectSize ( FI


<s> bool <ISA_LIT>AsmParser :: parseDirectiveCPU ( SMLoc L ) { StringRef CPU = getParser ( ) . parseStringToEndOfStatement ( ) . trim ( ) ; getTargetStreamer ( ) . emitTextAttribute


<s> explicit <ISA_LIT>FunctionInfo ( MachineFunction & MF ) : ReturnStackOffsetSet ( false ) , VarArgsFrameIndex ( <NUM_LIT> ) , VarArgFrameBytes ( <NUM_LIT> ) , ReturnStackOffset ( - <NUM_LIT> ) , MaxCallStackReq ( <NUM_LIT> ) { MF . setAlignment


<s> if ( Imm & ( <NUM_LIT> << ( Bits - <NUM_LIT> ) ) ) Imm |= ~ ( ( <NUM_LIT> << Bits ) - <NUM_LIT> ) ; Inst . addOperand ( MCOperand ::


<s> bool <ISA_LIT>AsmParser :: AddNextRegisterToList ( unsigned & Reg , unsigned & RegWidth , RegisterKind RegKind , unsigned Reg1 , unsigned RegNum ) { switch ( RegKind ) { case IS_SPECIAL : if ( Reg == <STR_LIT> && Reg1 == <STR_LIT> ) { Reg = <STR_LIT> ; RegWidth = <NUM_LIT> ; return true ; } if ( Reg == <STR_LIT> &&


<s> return <STR_LIT> ( <NUM_LIT> , SMLoc ( )


<s> SDValue TrueV = Op . getOperand ( <NUM_LIT> ) ; SDValue FalseV = Op . getOperand ( <NUM_LIT> ) ; <STR_LIT> CC = cast < CondCodeSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> get ( ) ; SDLoc dl ( Op ) ; DebugLoc dl = Op . getDebugLoc ( ) ; NegateCC ( LHS , RHS , CC ) ; SDValue TargetCC = DAG . getConstant ( CC , <STR_LIT> ) ; SDVTList VTs = DAG . getVTList ( Op . getValueType ( ) , <STR_LIT> ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . push_back (


<s> gen_shrd = mode == DImode ? gen_x86_shrd : gen_x86_64_shrd ; if ( ! rtx_equal_p ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ) emit_move_insn ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ; emit_insn ( gen_shrd ( low [ <NUM_LIT> ] , high [ <NUM_LIT> ] , GEN_INT ( count ) ) ) ; emit_insn ( gen_ashr3 ( high [ <NUM_LIT> ] , high [ <NUM_LIT> ] , GEN_INT ( count ) ) ) ; } } else { gen_shrd = mode == DImode ? gen_x86_shrd : gen_x86_64_shrd ; if ( ! rtx_equal_p ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ) emit_move_insn ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ; split_double_mode ( mode , operands , <NUM_LIT> , low , high ) ; emit_insn ( gen_shrd ( low [ <NUM_LIT> ] , high [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ) ; emit_insn ( gen_ashr3 ( high [ <NUM_LIT> ] , high [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ) ; if ( TARGET_CMOVE && scratch ) { rtx ( * gen_x86_shift_adj_1 ) ( rtx , rtx , rtx , rtx ) = mode == DImode ? gen_x86_shiftsi_adj_1 : gen_x86_shiftdi_adj_1 ; emit_move_insn ( scratch , high [ <NUM_LIT> ] ) ; emit_insn ( gen_ashr3 ( scratch , scratch , GEN_INT ( half_width - <NUM_LIT> ) ) ) ; emit_insn ( gen_x86_shift_adj_1 ( low [ <NUM_LIT> ] , high [ <NUM_LIT> ] , operands [ <NUM_LIT> ]


<s> unsigned <ISA_LIT>CodeGenPrepare :: numBitsUnsigned ( Value


<s> CC = ( CC == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; C = ( VT == <STR_LIT> ) ? ( uint32_t ) ( C - <NUM_LIT> ) : C - <NUM_LIT> ; RHS = DAG . getConstant ( C , dl , VT ) ; } break ; case <STR_LIT> : case <STR_LIT> : if ( ( VT == <STR_LIT> && C != INT32_MAX && isLegalArithImmed ( ( uint32_t ) ( C + <NUM_LIT> ) ) ) || ( VT == <STR_LIT> && C != INT64_MAX && isLegalArithImmed ( C + <NUM_LIT> ) ) ) { CC = ( CC == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; C = ( VT == <STR_LIT> ) ? ( uint32_t ) ( C + <NUM_LIT> ) : C + <NUM_LIT> ; RHS = DAG . getConstant ( C , dl , VT ) ; } break ; case <STR_LIT> : case <STR_LIT> : if ( ( VT == <STR_LIT> && C != UINT32_MAX && isLegalArithImmed ( ( uint32_t ) ( C + <NUM_LIT> ) ) ) || ( VT == <STR_LIT> && C != UINT64_MAX && isLegalArithImmed ( C + <NUM_LIT> ) ) ) { CC = ( CC == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; C = ( VT == <STR_LIT> ) ? ( uint32_t ) ( C + <NUM_LIT> ) : C + <NUM_LIT> ; RHS = DAG . getConstant ( C , dl , VT ) ; } break ; } } } SDValue Cmp ; <STR_LIT> <ISA_LIT>CC ; if ( ( CC == <STR_LIT> || CC == <STR_LIT> ) && isa < ConstantSDNode > ( RHS ) ) { const ConstantSDNode * RHSC = cast < ConstantSDNode > ( RHS ) ; if ( ( RHSC -> getZExtValue ( ) >> <NUM_LIT> == <NUM_LIT> ) && isa < LoadSDNode > ( LHS ) && cast < LoadSDNode > ( LHS ) -> getExtensionType ( ) == <STR_LIT> && cast < LoadSDNode > ( LHS ) -> getMemoryVT ( ) == <STR_LIT> && LHS . getNode ( ) -> hasNUsesOfValue ( <NUM_LIT> , <NUM_LIT> ) ) { int16_t ValueofRHS = cast < ConstantSDNode > ( RHS ) -> getZExtValue ( ) ; if ( ValueofRHS < <NUM_LIT> && isLegalArithImmed (


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) : LLVMTargetMachine ( T ,

computeDataLayout ( TT ) , TT , CPU , FS , Options , getEffectiveRelocModel ( TT , RM ) , CM , OL ) , TLOF ( make_unique < TargetLoweringObjectFileELF > ( ) ) {


<s> <ISA_LIT>Instr ( MCInstrInfo const & MCII , MCInst const * id , MCInst const * Extender , unsigned s , bool x = false ) : ID ( id ) , Extender ( Extender ) , Core (

s ) , CVI ( MCII , s , id ) , SoloException ( x ) { }


<s> return parseNamedBit ( <STR_LIT> , Operands


<s> * expandedp = false ; return NULL_RTX ; } * expandedp = true ; arg0 = CALL_EXPR_ARG ( exp , <NUM_LIT> ) ; op0 = expand_normal ( arg0 ) ; tmode = insn_data [ icode ] . operand [ <NUM_LIT> ] . mode ; mode0 = insn_data [ icode ] . operand [ <NUM_LIT> ] . mode ; if ( target == <NUM_LIT> || GET_MODE ( target ) != tmode || ! ( * insn_data [ icode ] . operand [ <NUM_LIT> ] . predicate ) ( target , tmode )


<s> if ( CSKY_VREG_P ( dstreg ) ) return <NUM_LIT> ; return <NUM_LIT> ; } else if ( GET_CODE ( src ) == CONST_INT || GET_CODE ( src ) == CONST_DOUBLE ) { split_double ( src , operands + <NUM_LIT> , operands + <NUM_LIT> ) ; if ( CSKY_CONST_OK_FOR_N ( INTVAL ( operands [ <NUM_LIT> ] ) + <NUM_LIT> ) && CSKY_CONST_OK_FOR_N ( INTVAL ( operands [ <NUM_LIT> ] ) + <NUM_LIT> ) && REGNO ( operands [ <NUM_LIT> ] ) < <NUM_LIT> ) return <NUM_LIT> ; else return <NUM_LIT> ; } } else if ( GET_CODE ( dst ) == MEM && GET_CODE ( src ) == REG ) { rtx memexp = XEXP ( dst , <NUM_LIT> ) ; int srcreg = REGNO ( src ) ; int offset = - <NUM_LIT> ; if ( CSKY_VREG_P ( srcreg ) ) return <NUM_LIT> ; if ( GET_CODE ( memexp ) == REG ) offset = <NUM_LIT> ; else if ( GET_CODE ( memexp ) == PLUS ) { if ( GET_CODE ( XEXP ( memexp , <NUM_LIT> ) ) == REG ) offset = INTVAL ( XEXP ( memexp , <NUM_LIT> ) ) ; else if ( GET_CODE ( XEXP ( memexp , <NUM_LIT> ) ) == REG ) offset = INTVAL ( XEXP ( memexp , <NUM_LIT> ) ) ; else gcc_unreachable (


<s> return ( __mmask16 ) __builtin_ia32_ucmpb128_mask ( ( __v16qi ) __A , ( __v16qi )


<s> const TargetInstrInfo & TII = * Subtarget . getInstrInfo ( ) ; MachineBasicBlock :: iterator I ( MI ) ; BuildMI ( * BB , I , MI . getDebugLoc ( ) , TII . get ( <STR_LIT>

) ) . add ( MI . getOperand ( <NUM_LIT> ) ) . addReg ( <STR_LIT> ) ;


<s> void function_builder :: add_unique_function ( const function_instance & instance , tree return_type , vec < tree > & argument_types , uint64_t required_extensions , bool force_direct_overloads ) { char * name = get_name ( instance , false ) ; tree fntype = build_function_type_array ( return_type , argument_types . length ( ) , argument_types . address ( ) ) ; tree attrs = get_attributes ( instance ) ; registered_function & rfn = add_function ( instance , name , fntype , attrs , required_extensions , false , false ) ; hashval_t hash = instance . hash ( ) ; registered_function * * rfn_slot = function_table -> find_slot_with_hash ( instance , hash , INSERT ) ; gcc_assert ( ! *


<s> MCSymbolData & Data = getOrCreateSymbolData ( Sym ) ; MCELF :: setOther ( Data , Val >> <NUM_LIT>


<s> LLVM_DEBUG ( dumpCurrGroup ( <STR_LIT> ) ) ; LLVM_DEBUG ( CurGroupDbg = <STR_LIT> ; ) ; GrpCount ++ ; CurrGroupSize = <NUM_LIT> ; CurrGroupHas4RegOps = false ; for ( unsigned i = <NUM_LIT> ; i < SchedModel -> getNumProcResourceKinds ( ) ; ++ i ) if ( ProcResourceCounters [ i ] > <NUM_LIT> ) ProcResourceCounters [ i ] -- ; if ( CriticalResourceIdx != UINT_MAX && ( ProcResourceCounters [ CriticalResourceIdx ] <= ProcResCostLim ) ) CriticalResourceIdx = UINT_MAX ; LLVM_DEBUG ( dumpState ( )


<s> return <ISA_LIT>GenRegisterInfo :: getDwarfRegNumFull ( RegNum ,


<s> bool is<ISA_LIT>64 = TM . getSubtargetImpl ( ) -> is<ISA_LIT>64 ( ) ; if ( ! FBB ) { if ( Cond . empty ( ) ) BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addMBB ( TBB ) ; else if ( Cond [ <NUM_LIT> ] . getReg ( ) == <STR_LIT> || Cond [ <NUM_LIT> ] . getReg ( ) == <STR_LIT> ) BuildMI ( & MBB , DL , get ( Cond [ <NUM_LIT> ] . getImm ( ) ? ( is<ISA_LIT>64 ? <STR_LIT> : <STR_LIT> ) : ( is<ISA_LIT>64 ? <STR_LIT> : <STR_LIT> ) ) ) . addMBB ( TBB ) ; else if ( Cond [ <NUM_LIT> ] . getImm ( ) == <STR_LIT> ) BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addOperand ( Cond [ <NUM_LIT> ] ) . addMBB ( TBB ) ; else if ( Cond [ <NUM_LIT> ] . getImm ( ) == <STR_LIT> ) BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addOperand ( Cond [ <NUM_LIT> ] ) . addMBB ( TBB ) ; else BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addImm ( Cond [ <NUM_LIT> ] . getImm ( ) ) . addOperand ( Cond [ <NUM_LIT> ] ) . addMBB ( TBB ) ; return <NUM_LIT> ; } if ( Cond [ <NUM_LIT> ] . getReg ( ) == <STR_LIT> || Cond [ <NUM_LIT> ] . getReg ( ) == <STR_LIT> ) BuildMI ( & MBB , DL , get ( Cond [ <NUM_LIT> ] . getImm ( ) ?


<s> addr = XEXP ( orig_mem , <NUM_LIT> ) ; mem = gen_rtx_MEM ( DImode , align ) ; MEM_VOLATILE_P ( mem ) = MEM_VOLATILE_P ( orig_mem ) ; if ( MEM_ALIAS_SET ( orig_mem ) == ALIAS_SET_MEMORY_BARRIER ) set_mem_alias_set ( mem , ALIAS_SET_MEMORY_BARRIER ) ; alpha_pre_atomic_barrier ( model ) ; label = gen_rtx_LABEL_REF ( DImode , gen_label_rtx ( ) ) ; emit_label ( XEXP ( label , <NUM_LIT> ) ) ; emit_insn ( gen_load_locked ( DImode , scratch , mem ) ) ; width = GEN_INT ( GET_MODE_BITSIZE ( mode ) ) ; mask = GEN_INT ( mode == QImode ? <NUM_LIT> :


<s> if ( SpecReg == <STR_LIT> ) { FlagsVal = StringSwitch < unsigned > ( Flags ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Default ( ~ <NUM_LIT> ) ; if ( FlagsVal == ~ <NUM_LIT> ) { if ( ! Flags . empty ( ) ) return MatchOperand_NoMatch ; else FlagsVal = <NUM_LIT> ; } } else if ( SpecReg == <STR_LIT> || SpecReg == <STR_LIT> ) { if ( Flags == <STR_LIT> ) Flags = <STR_LIT> ; for ( int i = <NUM_LIT> , e = Flags . size ( ) ; i != e ; ++ i ) { unsigned Flag = StringSwitch < unsigned > ( Flags . substr ( i , <NUM_LIT> ) ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Default ( ~ <NUM_LIT> ) ; if ( FlagsVal == ~ <NUM_LIT> || ( FlagsVal & Flag ) ) return MatchOperand_NoMatch ; FlagsVal |= Flag ; } } else return MatchOperand_NoMatch ; if ( ! FlagsVal ) FlagsVal = <NUM_LIT> ; if ( SpecReg == <STR_LIT> ) FlagsVal |= <NUM_LIT> ; Parser . Lex (


<s> return <ISA_LIT>GenRegisterInfo :: getDwarfRegNumFull ( RegNum , <NUM_LIT>


<s> SDValue <ISA_LIT>TargetLowering :: lowerOR ( SDValue Op , SelectionDAG & DAG ) const { assert ( Op . getValueType ( ) == <STR_LIT> && <STR_LIT> ) ; SDValue Ops [ ] = { Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) } ; APInt KnownZero [ <NUM_LIT> ] , KnownOne [ <NUM_LIT> ] ; DAG . ComputeMaskedBits ( Ops [ <NUM_LIT> ] , KnownZero [ <NUM_LIT> ] , KnownOne [ <NUM_LIT> ] ) ; DAG . ComputeMaskedBits ( Ops [ <NUM_LIT> ] , KnownZero [ <NUM_LIT> ] , KnownOne [ <NUM_LIT> ] ) ; uint64_t Masks [ ] = { KnownZero [ <NUM_LIT> ] . getZExtValue ( ) , KnownZero [ <NUM_LIT> ] . getZExtValue ( ) } ; unsigned High , Low ; if ( ( Masks [ <NUM_LIT> ] >> <NUM_LIT> ) == <NUM_LIT> && uint32_t ( Masks [ <NUM_LIT> ] ) == <NUM_LIT> ) High = <NUM_LIT> , Low = <NUM_LIT> ; else if ( ( Masks [ <NUM_LIT> ] >> <NUM_LIT> ) == <NUM_LIT> && uint32_t ( Masks [ <NUM_LIT> ] ) == <NUM_LIT> ) High = <NUM_LIT> , Low = <NUM_LIT> ; else return Op ; SDValue LowOp = Ops [ Low ] ; SDValue HighOp = Ops [ High ] ; if ( HighOp . getOpcode ( ) ==


<s> current_file = temp_node ; break ; } if ( temp_node == <NUM_LIT> ) { temp_node = ( file_node * ) ( alloca ( sizeof ( file_node ) ) ) ; temp_node -> next = <NUM_LIT> ; temp_node -> name = ( char * ) ( alloca ( strlen ( file_name ) + <NUM_LIT> ) ) ; strcpy ( temp_node -> name , file_name ) ; temp_node -> head = temp_node -> current_line = <NUM_LIT> ; if ( file_head ) tail_node


<s> DispatchPtr -> addDereferenceableAttr ( AttributeList :: ReturnIndex , <NUM_LIT> ) ; Type * I32Ty = Type :: getInt32Ty ( Mod -> getContext ( ) ) ; Value * CastDispatchPtr = Builder . CreateBitCast ( DispatchPtr , PointerType :: get ( I32Ty , <ISA_LIT>AS :: CONSTANT_ADDRESS ) ) ; Value * GEPXY = Builder . CreateConstInBoundsGEP1_64 ( I32Ty , CastDispatchPtr , <NUM_LIT> ) ; LoadInst * LoadXY = Builder . CreateAlignedLoad ( I32Ty , GEPXY , Align ( <NUM_LIT> ) ) ; Value * GEPZU = Builder . CreateConstInBoundsGEP1_64 ( I32Ty , CastDispatchPtr , <NUM_LIT> ) ; LoadInst * LoadZU = Builder . CreateAlignedLoad ( I32Ty , GEPZU , Align ( <NUM_LIT> ) ) ; MDNode * MD = MDNode :: get ( Mod -> getContext ( ) , None ) ; LoadXY -> setMetadata ( LLVMContext :: MD_invariant_load , MD


<s> I . addOperand ( MCOperand :: createExpr ( MCSymbolRefExpr :: create ( Symbol , OutContext ) ) ) ; OutStreamer -> emitInstruction ( I ,


<s> unsigned CFSize = FFI -> getMaxCallFrameSize ( ) ; if ( CFSize >= ( ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) / <NUM_LIT> ) return false ; return ! MF . getFrameInfo ( ) -> hasVarSizedObjects


<s> Value * <ISA_LIT>IREmitter :: visittCALL (


<s> const unsigned NumRegIndex = NumRegs - <NUM_LIT> ; assert ( NumRegIndex < array_lengthof ( SubRegFromChannelTable ) && <STR_LIT> ) ; assert ( Channel < array_lengthof (

SubRegFromChannelTable [ <NUM_LIT> ] ) ) ;


<s> I . setDesc ( TII . get ( HasCarryIn ? CarryOpc : NoCarryOpc ) ) ; I . addOperand ( * MF , MachineOperand :: CreateReg ( <STR_LIT> , false , true ) ) ; I . addOperand ( * MF , MachineOperand :: CreateImm ( <NUM_LIT> ) ) ; return constrainSelectedInstRegOperands ( I , TII , TRI , RBI ) ; } Register Src0Reg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register Src1Reg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( HasCarryIn ) { BuildMI ( * BB , & I , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( I . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; } unsigned NoCarryOpc = IsAdd ? <STR_LIT> : <STR_LIT> ; unsigned CarryOpc = IsAdd ? <STR_LIT> : <STR_LIT> ; BuildMI ( * BB , & I , DL , TII . get ( HasCarryIn ? CarryOpc : NoCarryOpc ) , Dst0Reg ) . add ( I . getOperand ( <NUM_LIT> ) ) . add ( I . getOperand ( <NUM_LIT> ) ) ; BuildMI ( * BB , & I , DL , TII . get ( <STR_LIT> ) , Dst1Reg ) . addReg ( <STR_LIT> ) ; if ( ! MRI -> getRegClassOrNull ( Dst1Reg ) ) MRI -> setRegClass ( Dst1Reg , & <STR_LIT> ) ; if ( ! RBI . constrainGenericRegister ( Dst0Reg , <STR_LIT> , * MRI ) || ! RBI . constrainGenericRegister ( Src0Reg , <STR_LIT> , * MRI ) || ! RBI . constrainGenericRegister ( Src1Reg , <STR_LIT> , * MRI ) ) return false ; if ( HasCarryIn && ! RBI . constrainGenericRegister ( I . getOperand ( <NUM_LIT> ) . getReg ( ) , <STR_LIT>


<s> const <ISA_LIT>RegisterInfo & getRegisterInfo ( ) const { return RI


<s> assert ( N != nullptr ) ; N -> Height = <NUM_LIT> + std :: max ( height ( N -> Left ) , height ( N -> Right ) ) ; if ( N -> Left ) N -> MaxEnd = std :: max ( N -> MaxEnd ,


<s> void addMemOperands ( MCInst & Inst , unsigned N ) const { assert ( Kind == k_Mem && <STR_LIT>


<s> const Function * Func = MBB . getParent ( ) -> getFunction ( ) ; const std :: string FuncName = Func -> getName ( ) ; const char * tmpName = ESNames :: createESName ( PAN :: getTempdataLabel ( FuncName ) ) ; if ( RC == <STR_LIT> ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addImm ( PTLI -> GetTmpOffsetForFI ( FI , <NUM_LIT> , * MBB . getParent ( ) ) ) . addExternalSymbol ( tmpName ) . addImm ( <NUM_LIT> ) ; } else if ( RC


<s> SubusRHS = Op1 ; SDValue MaxLHS = Op0 . getOperand ( <NUM_LIT> ) ; SDValue MaxRHS = Op0 . getOperand ( <NUM_LIT> ) ; if ( MaxLHS == Op1 ) SubusLHS = MaxRHS ; else if ( MaxRHS == Op1 ) SubusLHS = MaxLHS ; else return SDValue ( ) ; } else if ( Op1 . getOpcode ( ) == <STR_LIT> ) { SubusLHS = Op0 ; SDValue MinLHS = Op1 . getOperand ( <NUM_LIT> ) ; SDValue MinRHS = Op1 . getOperand ( <NUM_LIT> ) ; if ( MinLHS == Op0 ) SubusRHS = MinRHS ; else if ( MinRHS == Op0 ) SubusRHS = MinLHS ; else return SDValue ( ) ; } else return SDValue ( ) ; if ( EltVT == <STR_LIT> || EltVT == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , VT , SubusLHS , SubusRHS ) ; assert ( ( VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> ) && <STR_LIT> ) ; KnownBits Known = DAG . computeKnownBits ( SubusLHS ) ; unsigned NumZeros = Known . countMinLeadingZeros ( ) ; if ( ( VT == <STR_LIT> && NumZeros < <NUM_LIT> ) ||

NumZeros < <NUM_LIT> ) return SDValue ( ) ;


<s> EmitLabel ( Start ) ; MCSymbol * Symbol = getContext ( ) . GetOrCreateSymbol ( Name + <STR_LIT> + Twine ( MappingSymbolCounter ++ ) ) ; MCSymbolData & SD = getAssembler ( ) . getOrCreateSymbolData ( * Symbol ) ; MCELF :: SetType ( SD , ELF :: STT_NOTYPE ) ; MCELF :: SetBinding ( SD , ELF :: STB_LOCAL ) ; SD . setExternal ( false ) ; AssignSection ( Symbol , getCurrentSection ( ) . first ) ; const MCExpr * Value = MCSymbolRefExpr :: Create ( Start , getContext ( ) ) ; Symbol -> setVariableValue (


<s> rtx e0 ; rtx e1 ; unsigned reg ; e0 = XEXP ( p , <NUM_LIT> ) ; e1 = XEXP ( p , <NUM_LIT> ) ; switch ( GET_CODE ( e0 ) ) { case MEM : if ( GET_CODE ( XEXP ( e0 , <NUM_LIT> ) ) != PRE_DEC || ! REG_P ( XEXP ( XEXP ( e0 , <NUM_LIT> ) , <NUM_LIT> ) ) || REGNO ( XEXP ( XEXP ( e0 , <NUM_LIT> ) , <NUM_LIT> ) ) != SP_REGNUM ) abort ( ) ; asm_fprintf ( out_file , <STR_LIT> ) ; if ( IS_VFP_REGNUM ( REGNO ( e1 ) ) ) asm_fprintf ( out_file , <STR_LIT> , ( REGNO ( e1 ) - FIRST_VFP_REGNUM ) / <NUM_LIT> ) ; else asm_fprintf ( out_file , <STR_LIT> , REGNO ( e1 ) ) ; break ; case REG : if ( REGNO ( e0 ) == SP_REGNUM ) { if ( GET_CODE ( e1 ) != PLUS || ! REG_P ( XEXP ( e1 , <NUM_LIT> ) ) || REGNO ( XEXP ( e1 , <NUM_LIT> ) ) != SP_REGNUM || ! CONST_INT_P ( XEXP ( e1 , <NUM_LIT> ) ) ) abort ( ) ; asm_fprintf ( out_file , <STR_LIT> , - INTVAL ( XEXP ( e1 , <NUM_LIT> ) ) ) ; } else if ( REGNO ( e0 ) == HARD_FRAME_POINTER_REGNUM ) { HOST_WIDE_INT offset ; if ( GET_CODE ( e1 ) == PLUS ) { if ( ! REG_P ( XEXP ( e1 , <NUM_LIT> ) ) || ! CONST_INT_P ( XEXP ( e1 , <NUM_LIT> ) ) ) abort ( ) ; reg = REGNO ( XEXP ( e1 , <NUM_LIT> ) ) ; offset = INTVAL ( XEXP ( e1 , <NUM_LIT> ) ) ; asm_fprintf ( out_file , <STR_LIT> , HARD_FRAME_POINTER_REGNUM , reg , offset ) ; } else if ( REG_P ( e1 ) ) { reg = REGNO ( e1 ) ; asm_fprintf ( out_file , <STR_LIT> , HARD_FRAME_POINTER_REGNUM , reg ) ; } else abort ( ) ; } else if ( REG_P ( e1 ) && REGNO ( e1 ) == SP_REGNUM ) { asm_fprintf ( out_file , <STR_LIT> , REGNO ( e0 ) ) ; } else if ( GET_CODE ( e1 ) == PLUS && REG_P ( XEXP ( e1 , <NUM_LIT> ) ) && REGNO ( XEXP ( e1 , <NUM_LIT> ) ) == SP_REGNUM && CONST_INT_P ( XEXP ( e1 , <NUM_LIT> ) ) ) { asm_fprintf ( out_file , <STR_LIT> , REGNO ( e0 ) , ( int ) INTVAL ( XEXP ( e1 , <NUM_LIT> ) ) ) ; } else abort (


<s> if ( GENERAL_REGNO_P ( regno ) && ! call_really_used_regs [ regno ] && cfun_gpr_save_slot ( regno ) == <NUM_LIT> )


<s> unsigned <ISA_LIT>RegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { return <NUM_LIT>


<s> auto & MRI = * MIRBuilder . getMRI ( ) ; const RegClassOrRegBank & RegClassOrBank = MRI . getRegClassOrRegBank ( Dst ) ; unsigned Size ; if ( const auto * RC = RegClassOrBank . dyn_cast < const TargetRegisterClass * > ( ) ) Size = TRI . getRegSizeInBits ( * RC ) ; else Size = MRI . getType ( Dst ) . getSizeInBits ( ) ; assert ( Size <= <NUM_LIT> && <STR_LIT> ) ; static const unsigned OpcTable [ <NUM_LIT> ] = { <STR_LIT> , <STR_LIT> } ; unsigned Opc = OpcTable [ Size == <NUM_LIT> ] ; auto CSINC = MIRBuilder . buildInstr ( Opc , { Dst } , { Src1 , Src2 } ) . addImm ( Pred ) ; constrainSelectedInstRegOperands ( * CSINC , TII , TRI , RBI ) ; return & * CSINC


<s> OptForSize = MF . getFunction ( ) -> optForSize ( ) ; OptForMinSize = MF . getFunction ( ) -> optForMinSize ( ) ; AvailableFeatures = computeAvailableFeatures ( & MF , & STI


<s> if ( splittable_const_int_operand ( src , mode ) ) { mips_move_integer ( dest , dest , INTVAL ( src ) ) ; return ; } if ( mips_split_symbol ( dest , src , MAX_MACHINE_MODE , & src ) ) { emit_insn ( gen_rtx_SET ( dest , src ) ) ; return ; } if ( mips_tls_symbol_p ( src ) ) { mips_emit_move ( dest , mips_legitimize_tls_address ( src ) ) ; return ; } split_const ( src , & base , & offset ) ; if ( offset != const0_rtx && ( targetm . cannot_force_const_mem ( mode , src ) || ( ! TARGET_MIPS16 && can_create_pseudo_p ( ) ) ) ) { base = mips_force_temporary ( dest ,


<s> return false ; default : break ; } } const auto checkNoAlias = [ AA , Ptr ] ( auto I ) -> bool { return I && AA -> isNoAlias ( I -> getPointerOperand ( ) , Ptr ) ; } ; if ( checkNoAlias ( dyn_cast < AtomicCmpXchgInst > ( DefInst ) ) || checkNoAlias ( dyn_cast < AtomicRMWInst


<s> if ( any_condjump_p ( curr ) ) return false ; if ( ! arm_macro_fusion_p ( ) ) return false ; if ( current_tune -> fusible_ops & tune_params :: FUSE_AES_AESMC && aarch_crypto_can_dual_issue ( prev , curr ) ) return true ; if ( current_tune -> fusible_ops & tune_params :: FUSE_MOVW_MOVT ) { set_dest = SET_DEST ( curr_set ) ; if ( GET_MODE ( set_dest ) != SImode ) return false ; if ( GET_CODE ( set_dest ) == ZERO_EXTRACT ) { if ( CONST_INT_P ( SET_SRC ( curr_set ) ) && CONST_INT_P ( SET_SRC ( prev_set ) ) && REG_P ( XEXP ( set_dest , <NUM_LIT> ) ) && REG_P ( SET_DEST ( prev_set ) ) && REGNO ( XEXP ( set_dest ,

<NUM_LIT> ) ) == REGNO ( SET_DEST ( prev_set ) ) ) return true ;


<s> uint8_t <STR_LIT> ( ) { if ( FpABI == FpABIKind :: XX ) return ( uint8_t ) AFL_REG_32 ; return ( uint8_t


<s> printUnsignedImm ( const MCInst * MI , int opNum , raw_ostream & O ) { const MCOperand & MO = MI -> getOperand ( opNum ) ; if ( MO . isImm ( ) ) O << ( uint32_t ) MO . getImm


<s> if ( Subtarget -> isTargetEnvMacho ( ) ) { if ( is64Bit ) return new <ISA_LIT>64_MachoTargetObjectFile ( ) ; return new TargetLoweringObjectFileMachO ( ) ; } if ( Subtarget -> isTargetELF (


<s> unsigned <ISA_LIT>FastISel :: TargetMaterializeAlloca ( const AllocaInst * AI ) { if ( ! FuncInfo . StaticAllocaMap . count ( AI ) ) return <NUM_LIT> ; MVT VT ; if ( ! isLoadTypeLegal ( AI -> getType ( ) , VT ) ) return false ; DenseMap < const AllocaInst * , int > :: iterator SI = FuncInfo . StaticAllocaMap . find (


<s> bool <ISA_LIT>DAGToDAGISel :: SelectAddr ( SDValue Addr , SDValue & Base , SDValue & Offset ) { if ( FrameIndexSDNode * FIN = dyn_cast < FrameIndexSDNode > ( Addr ) ) { Base = CurDAG -> getTargetFrameIndex ( FIN -> getIndex ( ) , getTargetLowering ( ) -> getPointerTy ( ) ) ; Offset = CurDAG -> getTargetConstant ( <NUM_LIT> , <STR_LIT> ) ; return true ; } if ( Addr . getOpcode ( ) == <STR_LIT> || Addr . getOpcode ( ) == <STR_LIT> || Addr . getOpcode ( ) == <STR_LIT> ) { return


<s> JQ = Builder . CreateOr ( JQ , One ) ; } Value * IA = Num ; Value * IB = Den ; Value * FA = IsSigned ? Builder . Create<ISA_LIT>ToFP ( IA , F32Ty ) : Builder . CreateUIToFP ( IA , F32Ty ) ; Value * FB = IsSigned ? Builder . Create<ISA_LIT>ToFP ( IB , F32Ty ) : Builder . CreateUIToFP ( IB , F32Ty ) ; Value * RCP = Builder . CreateFDiv ( ConstantFP :: get ( F32Ty , <NUM_LIT> ) , FB ) ; Value * FQM = Builder . CreateFMul ( FA , RCP ) ; CallInst * FQ = Builder . CreateIntrinsic ( <STR_LIT> , { FQM } ) ; FQ -> copyFastMathFlags ( Builder . getFastMathFlags ( ) ) ; Value * FQNeg = Builder . CreateFNeg ( FQ ) ; Value * FR = Builder . CreateIntrinsic ( <STR_LIT> , { FQNeg , FB , FA } , FQ ) ; Value * IQ = IsSigned ? Builder . CreateFPTo<ISA_LIT> ( FQ , I32Ty ) : Builder . CreateFPToUI ( FQ , I32Ty ) ; FR = Builder . CreateIntrinsic ( <STR_LIT> , { FR } , FQ ) ; FB = Builder . CreateIntrinsic ( <STR_LIT> , { FB } , FQ ) ; Value * CV = Builder . CreateFCmpOGE ( FR , FB ) ; JQ = Builder . CreateSelect ( CV , JQ , Builder . getInt32 ( <NUM_LIT> ) ) ; Value * Div = Builder . CreateAdd ( IQ , JQ ) ; Value * Res = Div ; if ( ! IsDiv ) { Value * Rem = Builder . CreateMul ( Div ,


<s> if ( ! isImm ( ) ) return false ; const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; if ( ! CE ) return false ; uint64_t Value = CE -> getValue (


<s> Value * NewFDiv = nullptr ; if ( VectorType * VT = dyn_cast < VectorType > ( FDiv . getType ( ) ) ) { NewFDiv = UndefValue :: get ( VT ) ; for ( unsigned I = <NUM_LIT> , E = VT -> getNumElements ( ) ; I != E ; ++ I ) { Value * NumEltI = Builder . CreateExtractElement ( Num , I ) ; Value * DenEltI = Builder . CreateExtractElement ( Den , I ) ; Value * NewElt = nullptr ; if ( UseFDivFast && ! shouldKeepFDivF32 ( NumEltI , FastUnsafeRcpLegal , HasFP32Denormals ) ) { Function * Decl = <STR_LIT> ( Mod , <STR_LIT> ) ; NewElt = Builder . CreateCall ( Decl , { NumEltI , DenEltI } , <STR_LIT> , FPMath ) ; } if ( ! NewElt ) NewElt = performRCPOpt ( NumEltI , DenEltI , FastUnsafeRcpLegal , Builder , FPMath , Mod , HasFP32Denormals , NeedHighAccuracy ) ; if ( ! NewElt ) NewElt = Builder . CreateFDiv ( NumEltI , DenEltI , <STR_LIT> , FPMath ) ; NewFDiv = Builder . CreateInsertElement ( NewFDiv , NewElt , I ) ; } } else { if ( UseFDivFast && ! shouldKeepFDivF32 ( Num , FastUnsafeRcpLegal , HasFP32Denormals ) ) { Function * Decl = <STR_LIT> ( Mod , <STR_LIT> ) ; NewFDiv = Builder . CreateCall ( Decl , { Num , Den } , <STR_LIT> , FPMath ) ; } if ( ! NewFDiv


<s> virtual const char * getPassName ( ) const { return <STR_LIT>


<s> <ISA_LIT>LowerLiteralConstantsPass ( TargetMachine


<s> if ( EltType == <STR_LIT> || EltType == <STR_LIT> || EltType == <STR_LIT> ) return <STR_LIT> ; if ( EltType == <STR_LIT> || EltType == <STR_LIT> ) return <STR_LIT> ; if ( EltType == <STR_LIT> || EltType == <STR_LIT> ) return <STR_LIT> ; llvm_unreachable ( <STR_LIT> )


<s> } if ( LHS . getValueType ( ) == <STR_LIT> ) { SDValue <ISA_LIT>cc ; SDValue Cmp = get<ISA_LIT>Cmp ( LHS , RHS , CC , <ISA_LIT>cc , DAG , dl ) ; SDValue CCR = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Chain , Dest , <ISA_LIT>cc , CCR , Cmp ) ; } assert ( LHS . getValueType ( ) == <STR_LIT> || LHS . getValueType ( ) == <STR_LIT> ) ; if ( getTargetMachine ( ) . Options . UnsafeFPMath && ( CC == <STR_LIT> || CC == <STR_LIT> || CC == <STR_LIT> || CC == <STR_LIT> ) ) { SDValue Result = OptimizeVFPBrcond ( Op , DAG ) ; if ( Result . getNode ( ) ) return Result ; } <STR_LIT> CondCode , CondCode2 ; FPCCTo<ISA_LIT>CC ( CC , CondCode , CondCode2 ) ; SDValue <ISA_LIT>cc = DAG . getConstant ( CondCode , <STR_LIT> ) ; SDValue Cmp = getVFPCmp ( LHS ,


<s> LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << MBB . getNumber ( ) << <STR_LIT> ) ; return resolveCrossBlockLatency ( MBB , & MBB , topdown , deep , <NUM_LIT> , check_only , ignore_loop_instr


<s> if ( flag_stack_clash_protection && maybe_ne ( cfun -> machine -> frame . below_hard_fp_saved_regs_size , <NUM_LIT> ) && known_eq ( offset , <NUM_LIT> ) ) continue ; if ( frame_pointer_needed ) offset -= cfun -> machine -> frame . below_hard_fp_saved_regs_size ; else offset += crtl -> outgoing_args_size ; if ( aarch64_sve_mode_p ( mode ) ? offset_9bit_signed_scaled_p ( mode , offset ) : offset_12bit_unsigned_scaled_p ( mode , offset ) ) bitmap_set_bit ( components , regno ) ; } if ( frame_pointer_needed ) bitmap_clear_bit ( components , HARD_FRAME_POINTER_REGNUM ) ; if ( cfun -> machine -> frame . spare_pred_reg != INVALID_REGNUM ) bitmap_clear_bit ( components , cfun

-> machine -> frame . spare_pred_reg ) ;


<s> bool <ISA_LIT>FastISel :: SelectIndirectBr ( const Instruction * I ) { Register AddrReg = getRegForValue ( I -> getOperand ( <NUM_LIT> ) ) ; if ( AddrReg == <NUM_LIT> ) return false ; unsigned Opc = isThumb2 ? <STR_LIT> : <STR_LIT> ; assert ( isThumb2 || Subtarget ->


<s> SDNode * Node = Op . getNode ( ) ; EVT VT = Node -> getValueType ( <NUM_LIT> ) ; SDValue InChain = Node -> getOperand ( <NUM_LIT> ) ; SDValue VAListPtr = Node -> getOperand ( <NUM_LIT> ) ; EVT PtrVT = VAListPtr . getValueType ( ) ; const Value * SV = cast < SrcValueSDNode > ( Node -> getOperand ( <NUM_LIT> ) ) -> getValue ( ) ; SDLoc dl ( Node ) ; SDValue VAList = DAG . getLoad ( PtrVT , dl , InChain , VAListPtr , MachinePointerInfo ( SV ) , false , false , false , <NUM_LIT> ) ; SDValue nextPtr = DAG . getNode ( <STR_LIT> , dl , PtrVT , VAList , DAG . getIntPtrConstant ( VT . getSizeInBits


<s> } else { Offset = N . getOperand ( <NUM_LIT> ) ; SignExtend = CurDAG -> getTargetConstant ( <NUM_LIT> , <STR_LIT> ) ; } unsigned LegalShiftVal = Log2_32 ( Size ) ; unsigned ShiftVal = CSD -> getZExtValue ( ) ; if ( ShiftVal != <NUM_LIT> && ShiftVal != LegalShiftVal ) return false ; if ( isWorthFolding ( N ) ) return true ; return false


<s> bool <ISA_LIT>NaClRewritePass :: ApplyStackSFI ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI ) { TraceLog ( <STR_LIT> , MBB , MBBI ) ; assert ( Is64Bit ) ; MachineInstr & MI = * MBBI ; if ( ! IsStackChange ( MI , TRI ) ) return false ; if ( IsPushPop ( MI ) ) return false ; if ( MI . getDesc ( ) . isCall ( ) ) return false ; unsigned Opc = MI . getOpcode ( ) ; DebugLoc DL = MI . getDebugLoc ( ) ; unsigned DestReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; assert ( DestReg == <STR_LIT> || DestReg == <STR_LIT> ) ; unsigned NewOpc = <NUM_LIT> ; switch ( Opc ) { case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; } if ( NewOpc ) { BuildMI ( MBB , MBBI , DL , TII -> get ( NewOpc ) ) . addImm ( MI . getOperand ( <NUM_LIT> ) . getImm ( ) ) . addReg ( FlagUseZeroBasedSandbox ? <NUM_LIT> : <STR_LIT> ) ; MI . eraseFromParent ( ) ; return true ; } if ( Opc == <STR_LIT> && MI . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) { MI . getOperand ( <NUM_LIT> ) . setReg ( <STR_LIT> ) ; MI . getOperand ( <NUM_LIT> ) . setReg ( <STR_LIT> ) ; MI . setDesc ( TII -> get ( <STR_LIT> ) ) ; Opc = <STR_LIT> ; } if ( Opc == <STR_LIT> && MI . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) { return true ; } assert ( Opc != <STR_LIT> &&


<s> unsigned <ISA_LIT>MCCodeEmitter :: getMemSrcValue ( const MCInst & MI , unsigned OpIdx , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo &


<s> MCStreamer & S = getParser ( ) . getStreamer ( ) ; if ( S . getTargetStreamer ( ) == nullptr ) new <ISA_LIT>TargetStreamer ( S ) ; setAvailableFeatures ( ComputeAvailableFeatures ( STI . getFeatureBits (


<s> <STR_LIT> Pred = getInstrPredicate ( MI , PredReg ) ; if ( OddRegNum > EvenRegNum && OffImm == <NUM_LIT> ) { unsigned NewOpc = ( isLd ) ? ( isT2 ? <STR_LIT> : <STR_LIT> ) : ( isT2 ? <STR_LIT> : <STR_LIT> ) ; if ( isLd ) { BuildMI ( MBB , MBBI , MBBI -> getDebugLoc ( ) , TII -> get ( NewOpc ) ) . addReg ( BaseReg , getKillRegState ( BaseKill ) ) . addImm ( Pred ) . addReg ( PredReg ) . addReg ( EvenReg , getDefRegState ( isLd ) | getDeadRegState ( EvenDeadKill ) ) . addReg ( OddReg , getDefRegState ( isLd ) | getDeadRegState ( OddDeadKill ) ) ; ++ NumLDRD2LDM ; } else { BuildMI ( MBB , MBBI , MBBI -> getDebugLoc ( ) , TII -> get ( NewOpc ) ) . addReg ( BaseReg , getKillRegState ( BaseKill ) ) . addImm ( Pred ) . addReg ( PredReg ) . addReg ( EvenReg , getKillRegState ( EvenDeadKill ) | getUndefRegState ( EvenUndef ) ) . addReg ( OddReg , getKillRegState ( OddDeadKill ) | getUndefRegState ( OddUndef ) ) ; ++ NumSTRD2STM ; } NewBBI = llvm :: prior ( MBBI ) ; } else { unsigned NewOpc = ( isLd ) ? ( isT2 ? ( OffImm < <NUM_LIT> ? <STR_LIT> : <STR_LIT> ) : <STR_LIT> ) : ( isT2 ? ( OffImm < <NUM_LIT> ? <STR_LIT> : <STR_LIT> ) : <STR_LIT> ) ; DebugLoc dl = MBBI -> getDebugLoc ( ) ; if ( isLd && ( BaseKill || OffKill ) && ( TRI -> regsOverlap ( EvenReg , BaseReg ) ) ) { assert ( ! TRI -> regsOverlap ( OddReg , BaseReg ) ) ; InsertLDR_STR ( MBB , MBBI , OffImm + <NUM_LIT> , isLd , dl , NewOpc , OddReg , OddDeadKill , false , BaseReg , false , BaseUndef , false , OffUndef , Pred , PredReg , TII , isT2 ) ; NewBBI = llvm :: prior ( MBBI ) ; InsertLDR_STR ( MBB , MBBI , OffImm , isLd , dl , NewOpc , EvenReg , EvenDeadKill , false , BaseReg , BaseKill , BaseUndef , OffKill , OffUndef , Pred , PredReg , TII , isT2 ) ; } else { if ( OddReg == EvenReg && EvenDeadKill ) { EvenDeadKill = false ; OddDeadKill = true ; } if ( EvenReg == BaseReg ) EvenDeadKill = false ; InsertLDR_STR ( MBB , MBBI , OffImm , isLd , dl , NewOpc , EvenReg , EvenDeadKill , EvenUndef , BaseReg , false , BaseUndef , false , OffUndef ,


<s> SDValue Sub = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , StackPointer , Size ) ; SDValue ArgAdjust = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Sub , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDValue CopyChain = DAG . getCopyToReg ( Chain , dl , TM . getRegisterInfo ( ) -> getStackRegister ( ) , Sub ) ; SDValue Ops [ <NUM_LIT> ] = { ArgAdjust


<s> ArgListEntry Entry ; Entry . Node = SRet ; Entry . Ty = RetTy -> getPointerTo ( ) ; Entry . isSExt = false ; Entry . isZExt = false ; Entry . isSRet = true ; Args . push_back ( Entry ) ; Entry . Node = Arg ; Entry . Ty = ArgTy ; Entry . isSExt = false ; Entry . isZExt = false ; Args . push_back ( Entry ) ; const char * LibcallName = ( ArgVT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; SDValue Callee = DAG . getExternalSymbol ( LibcallName , getPointerTy ( ) ) ; TargetLowering :: CallLoweringInfo CLI ( DAG ) ; CLI . setDebugLoc ( dl ) . setChain ( DAG . getEntryNode ( ) ) . setCallee ( CallingConv :: C , Type :: getVoidTy ( * DAG . getContext ( ) ) , Callee , std :: move ( Args ) , <NUM_LIT> ) . setDiscardResult ( ) ; std :: pair < SDValue , SDValue > CallResult = LowerCallTo ( CLI ) ; SDValue LoadSin = DAG . getLoad ( ArgVT , dl , CallResult . second , SRet , MachinePointerInfo ( ) , false , false , false , <NUM_LIT> ) ; SDValue Add = DAG . getNode ( <STR_LIT> , dl , getPointerTy ( ) , SRet , DAG . getIntPtrConstant ( ArgVT . getStoreSize ( ) ) ) ; SDValue LoadCos = DAG . getLoad ( ArgVT , dl , LoadSin . getValue ( <NUM_LIT> ) , Add , MachinePointerInfo ( ) , false , false , false , <NUM_LIT> ) ; SDVTList Tys = DAG . getVTList (


<s> int64_t MaskImm = ( Size == <NUM_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; BuildMI ( BB , DL , TII -> get ( <STR_LIT> ) , MaskLSB2 ) . addReg ( <STR_LIT> ) . addImm ( - <NUM_LIT> ) ; BuildMI ( BB , DL , TII -> get ( <STR_LIT> ) , AlignedAddr ) . addReg ( Ptr ) . addReg ( MaskLSB2 ) ; BuildMI ( BB , DL , TII -> get ( <STR_LIT> ) , PtrLSB2 ) . addReg ( Ptr ) . addImm ( <NUM_LIT> ) ; if ( Subtarget . isLittle ( ) ) { BuildMI ( BB , DL , TII -> get ( <STR_LIT> ) , ShiftAmt ) . addReg ( PtrLSB2 ) . addImm ( <NUM_LIT> ) ; } else { unsigned Off = RegInfo . createVirtualRegister ( RC ) ; BuildMI ( BB , DL , TII -> get ( <STR_LIT> ) , Off ) . addReg ( PtrLSB2 ) . addImm ( ( Size == <NUM_LIT> ) ? <NUM_LIT> : <NUM_LIT> ) ; BuildMI ( BB , DL , TII -> get ( <STR_LIT> ) , ShiftAmt ) . addReg ( Off ) . addImm ( <NUM_LIT> ) ; } BuildMI ( BB , DL , TII -> get ( <STR_LIT> ) , MaskUpper ) . addReg ( <STR_LIT> ) . addImm ( MaskImm ) ; BuildMI ( BB , DL , TII -> get ( <STR_LIT> ) , Mask ) . addReg ( MaskUpper ) . addReg ( ShiftAmt ) ; BuildMI ( BB , DL , TII -> get ( <STR_LIT> ) , Mask2 ) . addReg ( <STR_LIT> ) . addReg ( Mask ) ; BuildMI ( BB , DL , TII -> get ( <STR_LIT> ) , MaskedCmpVal ) . addReg ( CmpVal ) . addImm ( MaskImm ) ; BuildMI ( BB , DL , TII -> get ( <STR_LIT> ) , ShiftedCmpVal ) . addReg ( MaskedCmpVal ) . addReg ( ShiftAmt ) ; BuildMI ( BB , DL , TII -> get ( <STR_LIT> ) , MaskedNewVal ) . addReg ( NewVal ) . addImm ( MaskImm ) ; BuildMI ( BB , DL , TII -> get ( <STR_LIT> ) , ShiftedNewVal ) . addReg ( MaskedNewVal ) . addReg ( ShiftAmt ) ; BB = loop1MBB ; BuildMI ( BB , DL , TII -> get ( <STR_LIT> ) , OldVal ) . addReg ( AlignedAddr ) . addImm ( <NUM_LIT> ) ; BuildMI ( BB , DL , TII -> get ( <STR_LIT> ) , MaskedOldVal0 ) . addReg ( OldVal ) .


<s> return TargetTriple . getOS ( ) == Triple


<s> MachineFunction :: iterator I = ++ BB -> getIterator ( ) ; MachineBasicBlock * HeadMBB = BB ; MachineFunction * F = BB -> getParent ( ) ; MachineBasicBlock * TailMBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * IfFalseMBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; F -> insert ( I , IfFalseMBB ) ; F -> insert ( I , TailMBB ) ; for ( MachineInstr * DebugInstr : SelectDebugValues ) { TailMBB -> push_back ( DebugInstr -> removeFromParent ( ) ) ; } TailMBB -> splice ( TailMBB -> end ( ) , HeadMBB , std :: next ( LastSelectPseudo -> getIterator ( ) ) , HeadMBB -> end ( ) ) ; TailMBB -> transferSuccessorsAndUpdatePHIs ( HeadMBB ) ; HeadMBB -> addSuccessor ( IfFalseMBB ) ; HeadMBB -> addSuccessor ( TailMBB ) ; BuildMI ( HeadMBB , DL , TII . getBrCond ( CC ) ) . addReg ( LHS ) . addReg ( RHS ) . addMBB ( TailMBB ) ; IfFalseMBB -> addSuccessor ( TailMBB ) ; auto SelectMBBI = MI . getIterator ( ) ; auto SelectEnd = std :: next ( LastSelectPseudo -> getIterator ( ) ) ; auto InsertionPoint = TailMBB -> begin ( ) ; while ( SelectMBBI != SelectEnd ) { auto Next = std :: next ( SelectMBBI ) ; if ( isSelectPseudo ( * SelectMBBI ) ) { BuildMI ( * TailMBB , InsertionPoint , SelectMBBI -> getDebugLoc ( ) , TII . get ( <STR_LIT> ) , SelectMBBI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( SelectMBBI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addMBB ( HeadMBB ) . addReg ( SelectMBBI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addMBB ( IfFalseMBB ) ; SelectMBBI -> eraseFromParent ( ) ; } SelectMBBI = Next ; } F -> getProperties ( ) . reset ( MachineFunctionProperties :: Property


<s> getT2AddrModeImm8OpValue ( const MCInst & MI , unsigned OpNum , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { const MCOperand & MO1 = MI . getOperand ( OpNum ) ; const MCOperand & MO2 = MI . getOperand ( OpNum + <NUM_LIT> ) ; unsigned Value = CTX . getRegisterInfo ( ) -> getEncodingValue ( MO1 . getReg ( ) ) ; Value <<= <NUM_LIT> ; int32_t tmp = ( int32_t ) MO2 . getImm ( ) ; if ( tmp < <NUM_LIT> ) tmp = abs ( tmp ) ; else Value |= <NUM_LIT> ; Value |= tmp &


<s> MachineInstr * MI = MF -> getRegInfo ( ) . getVRegDef ( R ) ; if ( ! MI ) continue ; Reg2Entry [ & MI -> getOperand ( <NUM_LIT> ) ]


<s> while ( Instruction != MBB . begin ( ) ) { -- Instruction ; if ( Instruction -> isDebugInstr ( ) ) continue ; if ( ! isUnpredicatedTerminator ( * Instruction ) ) break ; if ( ! Instruction -> isBranch ( ) ) return true ; if ( Instruction -> getOpcode ( ) == <STR_LIT> ) { if ( ! AllowModify ) { TrueBlock = Instruction -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; continue ; } while ( std :: next ( Instruction ) != MBB . end ( ) ) { std :: next ( Instruction ) -> eraseFromParent ( ) ; } Condition . clear ( ) ; FalseBlock = nullptr ; if ( MBB . isLayoutSuccessor ( Instruction -> getOperand ( <NUM_LIT> ) . getMBB ( ) ) ) { TrueBlock = nullptr ; Instruction -> eraseFromParent ( ) ; Instruction = MBB . end ( )


<s> FunctionPass * llvm :: create<ISA_LIT>CodePrinterPass ( raw_ostream & o , TargetMachine & tm , CodeGenOpt


<s> } else cfun -> machine -> no_drap_save_restore = true ; frame_pointer_needed = false ; stack_realign = false ; crtl -> max_used_stack_slot_alignment = incoming_stack_boundary ; crtl -> stack_alignment_needed = incoming_stack_boundary ; crtl -> stack_alignment_estimated = incoming_stack_boundary ; if ( crtl -> preferred_stack_boundary > incoming_stack_boundary ) crtl -> preferred_stack_boundary = incoming_stack_boundary ; df_finish_pass ( true ) ; df_scan_alloc ( NULL ) ; df_scan_blocks ( ) ; df_compute_regs_ever_live ( true ) ; df_analyze ( ) ; if ( flag_var_tracking ) { df_ref ref , next ; for ( ref = DF_REG_USE_CHAIN ( HARD_FRAME_POINTER_REGNUM ) ; ref ; ref = next ) { next = DF_REF_NEXT_REG ( ref ) ; if ( ! DF_REF_INSN_INFO ( ref ) ) continue ; rtx_insn * insn = DF_REF_INSN ( ref ) ; while ( next && DF_REF_INSN ( next ) == insn ) next = DF_REF_NEXT_REG ( next ) ; if ( DEBUG_INSN_P ( insn ) ) { bool changed = false ; for ( ; ref != next ; ref =


<s> void BlackfinRegisterInfo :: loadConstant ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , DebugLoc DL , unsigned Reg , int value ) const { if ( isInt < <NUM_LIT> > ( value ) ) { BuildMI ( MBB , I , DL , TII . get ( <STR_LIT> ) , Reg ) . addImm ( value ) ; return ; } if ( isUInt < <NUM_LIT> > ( value ) ) { BuildMI ( MBB , I , DL , TII . get ( <STR_LIT> ) , Reg ) . addImm


<s> unsigned <ISA_LIT>RegisterInfo :: getRARegister ( ) const { return <STR_LIT>


<s> assert ( DefMI ) ; if ( ! DefMI -> mayLoad ( ) || DefMI -> getNumOperands ( ) < <NUM_LIT> ) return true ; unsigned Flags = DefMI -> getOperand ( <NUM_LIT> ) . getTargetFlags ( ) ; if ( Flags != <STR_LIT> && Flags != <STR_LIT> ) return true ; assert ( DefMI ->


<s> static DecodeStatus DecodeMVE_MEM_3_pre ( MCInst & Inst , unsigned Val , uint64_t Address , const void *


<s> if ( SeenFI ) llvm_unreachable ( <STR_LIT> ) ; SeenFI = true ; } } MachineOperand * FIOp = TII -> getNamedOperand ( MI , <STR_LIT> :: vaddr ) ; assert ( FIOp && FIOp -> isFI ( ) && <STR_LIT> ) ; assert ( TII -> isMUBUF ( MI ) ) ; MachineOperand * OffsetOp = TII -> getNamedOperand ( MI , <STR_LIT> :: offset ) ; int64_t NewOffset = OffsetOp -> getImm ( ) + Offset ; if ( isUInt < <NUM_LIT> > ( NewOffset ) ) { FIOp -> ChangeToRegister ( BaseReg


<s> if ( CC == CallingConv :: Cold ) { return TM . is<ISA_LIT>64 ( ) ? ( Subtarget . hasAltivec ( ) ? CSR_SVR64_ColdCC_Altivec_RegMask : CSR_SVR64_ColdCC_RegMask ) : ( Subtarget . hasAltivec ( ) ? CSR_SVR32_ColdCC_Altivec_RegMask : ( Subtarget . hasSPE ( ) ? CSR_SVR32_ColdCC_SPE_RegMask : CSR_SVR32_ColdCC_RegMask ) ) ; } return TM . is<ISA_LIT>64 ( ) ? ( Subtarget . hasAltivec ( ) ? CSR_<ISA_LIT>64_Altivec_RegMask : CSR_<ISA_LIT>64_RegMask ) : ( Subtarget . hasAltivec ( ) ? CSR_SVR432_Altivec_RegMask : ( Subtarget . hasSPE

( ) ? CSR_SVR432_SPE_RegMask : CSR_SVR432_RegMask ) ) ;


<s> void <ISA_LIT>ELFStreamer :: EmitValueImpl ( const MCExpr * Value , unsigned Size , SMLoc Loc ) { MCELFStreamer :: EmitValueImpl ( Value , Size , Loc ) ; Labels . clear


<s> bool <ISA_LIT>TTIImpl :: isFCmpOrdCheaperThanFCmpZero (


<s> static MCCodeGenInfo * create<ISA_LIT>MCCodeGenInfo ( StringRef TT , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level


<s> case <NUM_LIT> : EltLog2Size = <NUM_LIT> ; InsertOp = <STR_LIT> ; InsveOp = <STR_LIT> ; VecRC = & <STR_LIT> ; break ; case <NUM_LIT> : EltLog2Size = <NUM_LIT> ; InsertOp = <STR_LIT> ; InsveOp = <STR_LIT> ; VecRC = & <STR_LIT> ; break ; case <NUM_LIT> : EltLog2Size = <NUM_LIT> ; InsertOp = <STR_LIT> ; InsveOp = <STR_LIT> ; VecRC = & <STR_LIT> ; break ; case <NUM_LIT> : EltLog2Size = <NUM_LIT> ; InsertOp = <STR_LIT> ; InsveOp = <STR_LIT> ; VecRC = & <STR_LIT> ; break ; } if ( IsFP ) { unsigned Wt = RegInfo . createVirtualRegister ( VecRC ) ; BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) , Wt ) . addImm ( <NUM_LIT> ) . addReg ( SrcValReg ) . addImm ( EltSizeInBytes == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ) ; SrcValReg = Wt ; } if ( EltSizeInBytes != <NUM_LIT> ) { unsigned LaneTmp1 = RegInfo . createVirtualRegister ( GPRRC ) ; BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) , LaneTmp1 ) . addReg ( LaneReg ) . addImm ( EltLog2Size ) ; LaneReg = LaneTmp1 ; } unsigned WdTmp1 = RegInfo . createVirtualRegister ( VecRC ) ; BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) , WdTmp1 ) . addReg ( SrcVecReg ) . addReg ( SrcVecReg ) . addReg ( LaneReg ) ; unsigned WdTmp2 = RegInfo . createVirtualRegister ( VecRC ) ; if ( IsFP ) { BuildMI ( * BB , MI , DL , TII -> get ( InsveOp ) , WdTmp2 ) . addReg ( WdTmp1 ) . addImm ( <NUM_LIT> ) . addReg ( SrcValReg ) . addImm ( <NUM_LIT> ) ; } else { BuildMI ( * BB , MI , DL , TII -> get ( InsertOp ) , WdTmp2 ) . addReg (

WdTmp1 ) . addReg ( SrcValReg ) . addImm ( <NUM_LIT> ) ;


<s> if ( MO . isImplicit ( ) ) { break ; } return MCOperand :: createReg ( MO . getReg ( ) ) ; case MachineOperand :: MO_Immediate : return MCOperand :: createImm ( MO . getImm ( ) + offset ) ; case MachineOperand :: MO_MachineBasicBlock : case MachineOperand :: MO_GlobalAddress : case MachineOperand :: MO_ExternalSymbol : case MachineOperand :: MO_JumpTableIndex : case MachineOperand :: MO_ConstantPoolIndex : case MachineOperand :: MO_BlockAddress : return LowerSymbolOperand ( MO , MOTy , offset ) ; case MachineOperand :: MO_RegisterMask : break ; } return MCOperand (


<s> SDValue NewN0 = DAG . getNode ( <STR_LIT> , DL , ReducedVT , N0 ) ; SDValue NewN1 = DAG . getNode ( <STR_LIT> , DL , ReducedVT , N1 ) ; if ( ExperimentalVectorWideningLegalization || NumElts >= OpsVT . getVectorNumElements ( ) ) { SDValue MulLo = DAG . getNode ( <STR_LIT> , DL , ReducedVT , NewN0 , NewN1 ) ; if ( Mode == MULU8 || Mode == MULS8 ) return DAG . getNode ( ( Mode == MULU8 ) ? <STR_LIT> : <STR_LIT> , DL , VT , MulLo ) ; MVT ResVT = <STR_LIT> ( <STR_LIT> , NumElts / <NUM_LIT> ) ; SDValue MulHi = DAG . getNode ( Mode == MULS16 ? <STR_LIT> : <STR_LIT> , DL , ReducedVT , NewN0 , NewN1 ) ; SmallVector < int , <NUM_LIT> > ShuffleMask ( NumElts ) ; for ( unsigned i = <NUM_LIT> , e = NumElts / <NUM_LIT> ; i < e ; i ++ ) { ShuffleMask [ <NUM_LIT> * i ] = i ; ShuffleMask [ <NUM_LIT> * i + <NUM_LIT> ] = i + NumElts ; } SDValue ResLo = DAG . getVectorShuffle ( ReducedVT , DL , MulLo , MulHi , ShuffleMask ) ; ResLo = DAG . getBitcast ( ResVT , ResLo ) ; for ( unsigned i = <NUM_LIT> , e = NumElts / <NUM_LIT> ; i < e ; i ++ ) { ShuffleMask [ <NUM_LIT> * i ] = i + NumElts / <NUM_LIT> ; ShuffleMask [ <NUM_LIT> * i + <NUM_LIT> ] = i + NumElts * <NUM_LIT> / <NUM_LIT> ; } SDValue ResHi = DAG . getVectorShuffle ( ReducedVT , DL


<s> default : return AtomicExpansionKind :: CmpXChg ; case AtomicRMWInst :: BinOp :: And : case AtomicRMWInst :: BinOp :: Or : case AtomicRMWInst :: BinOp :: Xor : case AtomicRMWInst :: BinOp :: Xchg : switch ( ITy -> getBitWidth ( ) ) { case <NUM_LIT> : case <NUM_LIT> : return AtomicExpansionKind :: CmpXChg ; case <NUM_LIT> : return AtomicExpansionKind :: None ; case <NUM_LIT> : if ( STI . hasAtomBitwise64 ( ) ) return AtomicExpansionKind :: None ; return AtomicExpansionKind :: CmpXChg ; default : llvm_unreachable ( <STR_LIT> ) ; } case AtomicRMWInst :: BinOp :: Add : case AtomicRMWInst :: BinOp :: Sub : case AtomicRMWInst :: BinOp :: Max : case AtomicRMWInst :: BinOp :: Min : case AtomicRMWInst :: BinOp :: UMax : case AtomicRMWInst :: BinOp :: UMin : switch ( ITy -> getBitWidth ( ) ) { case <NUM_LIT>


<s> offset = GEN_INT ( delta ) ; if ( ( delta < - <NUM_LIT> || delta > <NUM_LIT> ) && ( TARGET_COLDFIRE || USE_MOVQ ( delta ) ) ) { emit_move_insn ( gen_rtx_REG ( Pmode , D0_REG ) , offset ) ; offset = gen_rtx_REG ( Pmode , D0_REG ) ; } emit_insn ( gen_add3_insn ( copy_rtx ( this_slot ) , copy_rtx ( this_slot ) , offset ) ) ; } if ( vcall_offset != <NUM_LIT> ) { emit_move_insn ( tmp , this_slot ) ; emit_move_insn ( tmp , gen_rtx_MEM ( Pmode , tmp ) ) ; addr = plus_constant ( Pmode , tmp , vcall_offset ) ; if ( ! m68k_legitimate_address_p ( Pmode , addr , true ) ) { emit_insn ( gen_rtx_SET ( VOIDmode , tmp , addr ) ) ; addr = tmp ; } emit_move_insn ( gen_rtx_REG ( Pmode , D0_REG ) , gen_rtx_MEM ( Pmode ,


<s> Tensor1Info . Name += IndexStr ; Input . push_back ( Tensor1Info ) ; } if ( Tensor1Info . Type == TensorType :: Output ) { Tensor1Info . Name += <STR_LIT> ; Tensor1Info . Name += IndexStr ; Output . push_back ( Tensor1Info ) ; } break ; } else if ( auto * InstrPtr = dyn_cast < Instruction > ( GenAddrUser ) ) { if ( InstrPtr -> getParent ( ) != I -> getParent ( ) ) { bool FindOneUse = false ; for ( const Use & IUse : I -> uses ( ) ) { User * IUser = IUse . getUser ( ) ; if ( InstrPtr = dyn_cast < Instruction > ( IUser ) ) { if ( InstrPtr -> getParent ( ) == I -> getParent ( ) ) { I = InstrPtr ; if ( std :: find ( PreventCycle . begin ( ) , PreventCycle . end ( ) , InstrPtr ) != PreventCycle . end ( ) ) break ; else PreventCycle . push_back ( InstrPtr ) ; IntrinsUsage = true ; FindOneUse =


<s> bool <ISA_LIT>RewriteOutArguments :: doInitialization ( Module &


<s> Type * IntTy8 = Type :: getInt8Ty ( II . getContext ( ) ) ; auto * ShufTy = FixedVectorType :: get ( IntTy8 , <NUM_LIT> ) ; SmallVector < int , <NUM_LIT> > ShuffleMask ; for ( int i = <NUM_LIT> ; i != ( int ) Length ; ++ i ) ShuffleMask . push_back ( i + Index ) ; for ( int i = Length ; i != <NUM_LIT> ; ++ i ) ShuffleMask . push_back ( i + <NUM_LIT> ) ; for ( int i = <NUM_LIT> ; i != <NUM_LIT> ; ++ i ) ShuffleMask . push_back ( - <NUM_LIT> ) ; Value * SV = Builder . CreateShuffleVector ( Builder . CreateBitCast ( Op0 , ShufTy ) , ConstantAggregateZero :: get ( ShufTy ) , ShuffleMask ) ; return Builder . CreateBitCast ( SV , II . getType ( ) ) ; } if ( CI0 ) { APInt Elt = CI0 ->


<s> return ITStates . size ( ) == <NUM_LIT>


<s> Base = getReg ( Decoder , <STR_LIT> , Base ) ; Inst . addOperand ( MCOperand :: createReg ( Reg ) ) ; Inst . addOperand ( MCOperand :: createReg ( Base ) ) ; Inst . addOperand ( MCOperand :: createImm ( Offset ) ) ; return MCDisassembler ::


<s> if ( x && GET_CODE ( x ) == REG ) { int regno = REGNO


<s> MI . setDesc ( get ( LII . Is64Bit ? <STR_LIT> : <STR_LIT> ) ) ; MachineInstrBuilder ( * MI . getParent ( ) -> getParent ( ) , MI ) . addImm ( LII . Imm ) . addReg ( <STR_LIT> , RegState :: ImplicitDefine ) ; return ; } else MI . setDesc ( get ( LII . Is64Bit ? <STR_LIT> : <STR_LIT> ) ) ; MachineInstrBuilder ( * MI . getParent ( ) -> getParent ( ) , MI ) .


<s> if ( ! TCycles ) return false ; const unsigned ScalingUpFactor = <NUM_LIT> ; unsigned TUnpredCost = Probability . scale ( TCycles * ScalingUpFactor ) ; unsigned FUnpredCost = Probability . getCompl ( ) . scale ( FCycles * ScalingUpFactor ) ; unsigned UnpredCost = TUnpredCost + FUnpredCost ; UnpredCost += <NUM_LIT> * ScalingUpFactor ; UnpredCost += Subtarget . getMispredictionPenalty ( ) * ScalingUpFactor


<s> if ( Narrow -> getOpcode ( ) != <STR_LIT> && Narrow -> getOpcode ( ) != <STR_LIT> && Narrow -> getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; SDValue N0 = Narrow -> getOperand ( <NUM_LIT> ) ; SDValue N1 = Narrow -> getOperand ( <NUM_LIT> ) ; SDLoc DL ( Narrow ) ; if ( N0 . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; EVT WideVT = N0 -> getOperand ( <NUM_LIT> ) -> getValueType ( <NUM_LIT> ) ; if ( WideVT != VT ) return SDValue ( ) ; bool RHSTrunc = N1 . getOpcode ( ) == <STR_LIT> ; bool RHSConst = ( isSplatVector ( N1 . getNode ( ) ) && isa < ConstantSDNode > ( N1 -> getOperand ( <NUM_LIT> ) ) ) ; if ( ! RHSTrunc && ! RHSConst ) return SDValue ( ) ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; if ( ! TLI . isOperationLegalOrPromote ( Narrow -> getOpcode ( ) , WideVT ) ) return SDValue ( ) ; N0 = N0 -> getOperand ( <NUM_LIT>


<s> if ( MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) && MFI . adjustsStack (


<s> unsigned elt = neon_pair_endian_lane_map ( d -> vmode , i + high ) & mask ; if ( d -> perm [ neon_pair_endian_lane_map ( d -> vmode , <NUM_LIT> * i + is_swapped ) ] != elt ) return false ; elt = neon_pair_endian_lane_map ( d -> vmode , i + nelt + high ) & mask ; if ( d -> perm [ neon_pair_endian_lane_map ( d -> vmode , <NUM_LIT> * i + ! is_swapped ) ] != elt ) return false ; } if ( d -> testing_p ) return true ; in0 = d -> op0


<s> HardwareLoopInfo HWLoopInfo ( L ) ; if ( ! HWLoopInfo . canAnalyze ( * LI ) ) return false ; if ( ! isHardwareLoopProfitable ( L , * SE , * AC , LibInfo , HWLoopInfo ) ) return false ; if ( ! HWLoopInfo . isHardwareLoopCandidate ( * SE , * LI , * DT ) ) return false ; * BI = HWLoopInfo


<s> return false ; case 'L' : if ( ! MI -> getOperand ( OpNo ) . isReg ( ) || OpNo + <NUM_LIT> == MI -> getNumOperands ( ) || ! MI -> getOperand ( OpNo + <NUM_LIT> ) . isReg ( ) ) return true ; ++ OpNo ; break ; case 'I' : if ( MI -> getOperand ( OpNo ) . isImm ( ) ) OS << <STR_LIT> ; return false ; } } printOperand ( MI , OpNo , OS


<s> if ( mode2 == XFmode ) return mode1 == SFmode || mode1 == DFmode ; if ( mode2 == DFmode ) return mode1 == SFmode ; if ( GET_MODE_SIZE ( mode2 ) == <NUM_LIT> && ix86_hard_regno_mode_ok ( FIRST_SSE_REG , mode2 ) ) return ( GET_MODE_SIZE ( mode1 ) == <NUM_LIT> && ix86_hard_regno_mode_ok ( FIRST_SSE_REG , mode1 ) ) ; if ( GET_MODE_SIZE ( mode2 ) == <NUM_LIT> && ix86_hard_regno_mode_ok ( FIRST_SSE_REG , mode2 ) ) return ( GET_MODE_SIZE ( mode1 ) == <NUM_LIT> && ix86_hard_regno_mode_ok ( FIRST_SSE_REG , mode1 ) ) ; if ( GET_MODE_SIZE ( mode2 ) == <NUM_LIT> && ix86_hard_regno_mode_ok ( FIRST_MMX_REG , mode2 ) ) return ( GET_MODE_SIZE ( mode1 ) == <NUM_LIT> && ix86_hard_regno_mode_ok ( FIRST_MMX_REG , mode1 ) ) ; return false


<s> rtx msp430_function_arg ( cumulative_args_t cap , machine_mode mode , const_tree type , bool named ) { CUMULATIVE_ARGS * ca = get_cumulative_args ( cap ) ; msp430_evaluate_arg ( cap , mode , type , named ) ; if ( ca -> reg_count ) return gen_rtx_REG


<s> const MCInstrDesc & Desc = OldMI . getDesc ( ) ; for ( unsigned i = Desc . getNumOperands ( ) , e = OldMI . getNumOperands ( ) ; i != e ; ++ i ) { const MachineOperand & MO = OldMI . getOperand ( i ) ; assert ( MO . isReg ( ) && MO . getReg ( ) ) ; if ( MO . isUse ( ) ) UseMI . addOperand ( MO ) ; else DefMI . addOperand ( MO


<s> const unsigned ScratchReg = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , II ) . addDef ( ResultReg1 ) . addDef ( ScratchReg ) . addUse ( AddrReg ) . addUse ( DesiredReg ) . addUse ( NewReg ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( CmpOpc ) ) . addDef ( VT == <STR_LIT> ? <STR_LIT> : <STR_LIT> ) . addUse ( ResultReg1 ) . addUse ( DesiredReg ) . addImm ( <NUM_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) ) . addDef ( ResultReg2 ) . addUse ( <STR_LIT>

) . addUse ( <STR_LIT> ) . addImm ( <STR_LIT> ) ;


<s> Arg = DAG . getNode ( <STR_LIT> , DL , RegVT , Arg ) ; break ; case CCValAssign :: BCvt : Arg = DAG . getNode ( <STR_LIT> , DL , RegVT , Arg ) ; break ; } if ( VA . isMemLoc ( ) ) { HasStackArgs = true ; break ; } RegsToPass . push_back ( std :: make_pair ( VA . getLocReg ( ) , Arg ) ) ; } if ( HasStackArgs ) { SmallVector < SDValue , <NUM_LIT> > MemOpChains ; for ( ; AI != AE ; AI ++ ) { CCValAssign & VA = ArgLocs [ AI ] ; SDValue Arg = OutVals [ AI ] ; assert ( VA . isMemLoc ( ) ) ; SDValue PtrOff = DAG . getNode ( <STR_LIT> , DL , getPointerTy ( DAG . getDataLayout ( ) ) , DAG . getRegister ( <STR_LIT> , getPointerTy ( DAG . getDataLayout ( ) ) ) , DAG . getIntPtrConstant ( VA . getLocMemOffset ( ) + <NUM_LIT> , DL ) ) ; MemOpChains . push_back ( DAG . getStore ( Chain , DL , Arg , PtrOff , MachinePointerInfo :: getStack ( MF , VA . getLocMemOffset ( ) ) ) ) ; } if ( ! MemOpChains . empty ( ) ) Chain = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , MemOpChains ) ; } SDValue InFlag ; for ( auto Reg : RegsToPass ) { Chain = DAG . getCopyToReg ( Chain , DL , Reg . first , Reg . second , InFlag ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; } SDVTList NodeTys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . push_back ( Chain ) ; Ops . push_back (


<s> static tree rs6000_builtin_mask_for_load ( void ) { if ( ( TARGET_ALTIVEC && ! TARGET_VSX ) || ( TARGET_VSX && !

TARGET_EFFICIENT_UNALIGNED_VSX ) ) return altivec_builtin_mask_for_load ;


) _mm512_setzero_ps ( ) , ( __mmask16 ) - <NUM_LIT> ) ;


<s> bool <ISA_LIT>BaseTargetMachine :: addCodeEmitter ( PassManagerBase & PM , CodeGenOpt :: Level


<s> RegisterTargetMachine < ThumbTargetMachine > Y (


<s> if ( Log2Size != <NUM_LIT> ) return false ; if ( ! Symbol . isInSection ( ) ) return true ; const MCSectionMachO & RefSec = cast < MCSectionMachO > ( Symbol . getSection ( ) ) ; if ( RefSec . getType ( ) == MachO ::


<s> MCELFStreamer & <ISA_LIT>TargetELFStreamer :: getStreamer ( ) { return static_cast < MCELFStreamer &


<s> if ( STI . getFeatureBits ( ) [ <STR_LIT> ] ) return <NUM_LIT> ; if ( STI . getFeatureBits ( ) [ <STR_LIT> ] ) return <NUM_LIT> ; if ( STI . getFeatureBits ( ) [ <STR_LIT> ] ) return <NUM_LIT> ; return <NUM_LIT>


<s> const <STR_LIT> & Flags = Ins [ <NUM_LIT> ] . Flags ; if ( ! Flags . isSRet ( ) ) return NotStructReturn ; if ( Flags . isInReg ( ) || IsMCU


<s> updateMask ( M ) ; return true ; } else if ( Type == Descending && O == Start - <NUM_LIT> ) { Start -= <NUM_LIT> ; updateMask ( M ) ; return true ; } else if ( Type == Ascending && O == Stop + <NUM_LIT> ) { Stop += <NUM_LIT>


<s> static bool matchRegisterNameHelper ( MCRegister & RegNo , StringRef Name ) { RegNo = MatchRegisterName ( Name ) ; if ( RegNo == <STR_LIT> ) RegNo = MatchRegisterAltName ( Name ) ; return RegNo


<s> raw_string_ostream ISAVersionStream ( ISAVersionString ) ; IsaInfo :: streamIsaVersion ( getGlobalSTI ( ) , ISAVersionStream ) ; getTargetStreamer ( ) -> EmitISAVersion ( ISAVersionStream . str ( ) ) ; } if ( TM . getTargetTriple ( ) . getOS ( ) == Triple :: AMDHSA ) { HSAMetadataStream -> end ( ) ; bool Success = HSAMetadataStream -> emitTo ( * getTargetStreamer ( ) ) ; ( void )


<s> static const int INSTR_DISTANCE_THRESHOLD = <NUM_LIT> ; CurInst = I ; bool Found ; Found = getPreviousInstr ( CurInst , MFI ) ; while ( Found && I != CurInst ) { if ( CurInst -> isCall ( ) || CurInst -> isInlineAsm ( ) ) break ; if ( InstrDistance > INSTR_DISTANCE_THRESHOLD ) break ; if ( usesRegister ( p , CurInst ) == RU_Write ) { return CurInst ; } InstrDistance += TII -> getInstrLatency ( MF -> getSubtarget ( ) .

getInstrItineraryData ( ) , * CurInst ) ;


<s> return ( __m256i ) __builtin_ia32_vpdpbusd_v8si ( ( __v8si ) __A , ( __v8si )


<s> int64_t Inc = IncVal -> getSExtValue ( ) ; if ( Inc != <NUM_LIT> && Inc != <NUM_LIT> && Inc != <NUM_LIT> && Inc != <NUM_LIT> ) return false ; Offset = Op -> getOperand (


<s> CallSite CS ( CI ) ; CallingConv :: ID CalleeCC = CS . getCallingConv ( ) ; if ( ! mayTailCallThisCC ( CalleeCC ) ) return


<s> default : return false ; case <STR_LIT> :: MxPCD32 : case <STR_LIT> :: MxPCD16 : case <STR_LIT> :: MxPCD8 : case <STR_LIT> :: MxPCI32 : case <STR_LIT>


<s> setSchedulingPreference ( Sched :: Source ) ; setBooleanContents ( ZeroOrOneBooleanContent ) ; setBooleanVectorContents ( ZeroOrOneBooleanContent ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; for ( MVT VT : <STR_LIT> ( ) ) { setLoadExtAction ( <STR_LIT> , VT , <STR_LIT> , Promote ) ; setLoadExtAction ( <STR_LIT> , VT , <STR_LIT> , Promote ) ; setLoadExtAction ( <STR_LIT> , VT , <STR_LIT> , Promote ) ; setLoadExtAction ( <STR_LIT> , VT , <STR_LIT> , Expand ) ; setLoadExtAction ( <STR_LIT> , VT , <STR_LIT> , Expand ) ; } setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand


<s> static DecodeStatus DecodeIntRegsLow8RegisterClass ( MCInst & Inst , unsigned RegNo ,

uint64_t Address , const MCDisassembler * Decoder ) {


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL , bool is64bit ) : LLVMTargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL ) , Subtarget ( TT , CPU , FS , is64bit ) , DL ( Subtarget . getDataLayout ( ) ) , InstrInfo ( * this ) , TLInfo ( * this ) , TSInfo ( * this ) , FrameLowering ( * this , is64bit ) { initAsmInfo (


<s> unsigned fpr_base = return_p ? FP_RETURN : FP_ARG_FIRST ; unsigned gpr_base = return_p ? GP_RETURN : GP_ARG_FIRST ; unsigned alignment = riscv_function_arg_boundary ( mode , type ) ; memset ( info , <NUM_LIT> , sizeof ( * info ) ) ; info -> gpr_offset = cum -> num_gprs ; info -> fpr_offset = cum -> num_fprs ; if ( named ) { riscv_aggregate_field fields [ <NUM_LIT> ] ; unsigned fregno = fpr_base + info -> fpr_offset ; unsigned gregno = gpr_base + info -> gpr_offset ; if ( ( info -> num_fprs = riscv_pass_aggregate_in_fpr_pair_p ( type , fields ) ) && info -> fpr_offset + info -> num_fprs <= MAX_ARGS_IN_REGISTERS ) switch ( info -> num_fprs ) { case <NUM_LIT> : return riscv_pass_fpr_single ( mode , fregno , TYPE_MODE ( fields [ <NUM_LIT> ] . type ) , fields [ <NUM_LIT> ] . offset ) ; case <NUM_LIT> : return riscv_pass_fpr_pair ( mode , fregno , TYPE_MODE ( fields [ <NUM_LIT> ] . type ) , fields [ <NUM_LIT> ] . offset , fregno + <NUM_LIT> , TYPE_MODE ( fields [ <NUM_LIT> ] . type ) , fields [ <NUM_LIT> ] . offset ) ; default : gcc_unreachable ( ) ; } if ( ( info -> num_fprs = riscv_pass_mode_in_fpr_p ( mode ) ) && info -> fpr_offset + info -> num_fprs <= MAX_ARGS_IN_REGISTERS ) switch ( GET_MODE_CLASS ( mode ) ) { case MODE_FLOAT : return gen_rtx_REG ( mode , fregno


<s> if ( Ins != MBB -> end ( ) ) DL = Ins -> getDebugLoc ( ) ; const MachineFunction & MF = * MBB -> getParent ( ) ; const TargetInstrInfo & TII = * Subtarget . getInstrInfo ( ) ; const MCInstrDesc & MCID = TII . get ( ADDriOpc ) ; MachineRegisterInfo & MRI = MBB -> getParent ( ) -> getRegInfo ( ) ; MRI . constrainRegClass ( BaseReg , TII . getRegClass ( MCID , <NUM_LIT> , this , MF ) ) ; BuildMI ( * MBB , Ins , DL , MCID , BaseReg ) . addFrameIndex ( FrameIdx )


<s> return Opcode == Instruction :: Load ? SVEGatherOverhead :


<s> if ( MBB . isLayoutSuccessor ( I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ) ) { TBB = <NUM_LIT> ; I -> eraseFromParent ( ) ; I = MBB . end ( ) ; continue ; } } TBB = I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; continue ; } assert ( I -> getOpcode ( ) == <STR_LIT> && <STR_LIT> ) ; <STR_LIT> BranchCode = static_cast < <STR_LIT> > ( I -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; if ( BranchCode == <STR_LIT> ) { return true ; } if ( Cond . empty ( ) ) { FBB = TBB ; TBB = I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; Cond . push_back ( MachineOperand :: CreateImm ( BranchCode ) ) ; continue ; } assert ( Cond . size ( ) == <NUM_LIT> ) ; assert ( TBB ) ; if ( TBB != I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ) { return


<s> const <ISA_LIT>MachineFunctionInfo * MFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; if ( MFI -> isEntryFunction ( ) ) return ; const GCNSubtarget & ST = MF . getSubtarget < GCNSubtarget > ( ) ; const <ISA_LIT>RegisterInfo * TRI = ST . getRegisterInfo ( ) ; SavedRegs . reset ( MFI -> getStackPtrOffsetReg ( ) ) ; const BitVector AllSavedRegs


<s> unsigned Opc = MI -> getOpcode ( ) ; const MCInstrDesc & D = HII -> get ( Opc ) ; if ( const MCPhysReg * R = D . ImplicitDefs ) while ( * R ) expandReg ( * R ++ , Defs ) ; if ( const MCPhysReg * R = D . ImplicitUses ) while ( * R ) expandReg ( * R ++ , Uses ) ; for ( ConstMIOperands Mo ( MI ) ; Mo . isValid ( ) ; ++ Mo ) { if ( ! Mo -> isReg ( ) || Mo -> isImplicit ( ) ) continue ; unsigned R = Mo -> getReg ( ) ; BitVector & Set = Mo -> isDef (


<s> EVT getOptimalMemOpType ( uint64_t Size , unsigned DstAlign , unsigned SrcAlign , bool IsMemset ,

bool ZeroMemset , bool MemcpyStrSrc , MachineFunction & MF ) const override {


<s> void <ISA_LIT>InstrInfo :: storeRegToStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , Register SrcReg , bool isKill , int FrameIndex , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { MachineFunction * MF = MBB . getParent ( ) ; <ISA_LIT>MachineFunctionInfo * MFI = MF -> getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; MachineFrameInfo & FrameInfo = MF -> getFrameInfo ( ) ; const DebugLoc & DL = MBB . findDebugLoc ( MI ) ; MachinePointerInfo PtrInfo = MachinePointerInfo :: getFixedStack ( * MF , FrameIndex ) ; MachineMemOperand * MMO = MF -> getMachineMemOperand ( PtrInfo , MachineMemOperand :: MOStore , FrameInfo . getObjectSize ( FrameIndex ) , FrameInfo . getObjectAlign ( FrameIndex ) ) ; unsigned SpillSize = TRI -> getSpillSize ( * RC ) ; if ( RI . isSGPRClass ( RC ) ) { MFI -> setHasSpilledSGPRs ( ) ; assert ( SrcReg != <STR_LIT> && <STR_LIT>


<s> static rtx sh_legitimize_address ( rtx x , rtx oldx , machine_mode mode ) { if ( flag_pic ) x = legitimize_pic_address ( oldx , mode , NULL_RTX ) ; if ( ( TARGET_FPU_DOUBLE && mode == DFmode ) || ( TARGET_SH2E && mode == SFmode ) ) return x ; if ( GET_CODE ( x ) == PLUS && CONST_INT_P ( XEXP ( x , <NUM_LIT> ) ) && BASE_REGISTER_RTX_P ( XEXP ( x , <NUM_LIT> ) ) ) { struct disp_adjust adj = sh_find_mov_disp_adjust ( mode , INTVAL ( XEXP ( x , <NUM_LIT> ) ) ) ; if ( adj . offset_adjust != NULL_RTX && adj . mov_disp != NULL_RTX ) { rtx sum = expand_binop ( Pmode , add_optab , XEXP ( x , <NUM_LIT> ) , adj . offset_adjust , NULL_RTX , <NUM_LIT> , OPTAB_LIB_WIDEN ) ; return gen_rtx_PLUS ( Pmode , sum , adj . mov_disp ) ; } } return x


<s> const BlockAddress * <ISA_LIT>ConstantPoolValue ::


<s> MachineBasicBlock * copy0MBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * sinkMBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; F -> insert ( It , copy0MBB ) ; F -> insert ( It , sinkMBB ) ; sinkMBB -> splice ( sinkMBB -> begin ( ) , BB , std :: next ( MachineBasicBlock :: iterator ( MI ) ) , BB -> end ( ) ) ; sinkMBB -> transferSuccessorsAndUpdatePHIs ( BB ) ; BB -> addSuccessor ( copy0MBB ) ; BB -> addSuccessor ( sinkMBB ) ; BuildMI ( BB , dl , TII . get ( <STR_LIT> ) ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addMBB ( sinkMBB ) ; BB = copy0MBB


<s> return isa < PointerType > ( Ty ) && Ty -> getPointerAddressSpace ( )


<s> std :: vector < std :: string > mov_x1_to ( Ab b ) { return D ( <STR_LIT> , <STR_LIT> , R (


<s> { MO_GOT , <STR_LIT> } , { MO_SBREL , <STR_LIT> } , { MO_DLLIMPORT , <STR_LIT> } , { MO_SECREL , <STR_LIT> } , { MO_NONLAZY , <STR_LIT> } } ; return makeArrayRef (


<s> int regi = pru_function_arg_regi ( cum_v , arg . mode ,


<s> unsigned <ISA_LIT>PCLabelIndex = AFI -> createConstPoolEntryUId ( ) ; EVT PtrVT = getPointerTy ( ) ; DebugLoc dl = Op . getDebugLoc ( ) ; unsigned PCAdj = Subtarget -> isThumb ( ) ? <NUM_LIT> : <NUM_LIT> ; <ISA_LIT>ConstantPoolValue * CPV = new <ISA_LIT>ConstantPoolValue ( * DAG . getContext ( ) , <STR_LIT> , <ISA_LIT>PCLabelIndex , PCAdj ) ; SDValue CPAddr = DAG . getTargetConstantPool ( CPV , PtrVT , <NUM_LIT> ) ; CPAddr = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , CPAddr ) ; SDValue Result = DAG . getLoad ( PtrVT , dl , DAG . getEntryNode ( ) , CPAddr , PseudoSourceValue :: getConstantPool ( ) , <NUM_LIT> , false , false


<s> fputs ( <STR_LIT> , file ) ; break ; } case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : if ( ! ANY_FP_REG_P ( x ) ) putc ( code == <NUM_LIT> && TARGET_64BIT ? 'r' : 'e' , file ) ; case <NUM_LIT> : case <NUM_LIT> : normal : fputs ( hi_reg_name [ REGNO ( x ) ] , file ) ; break ; case <NUM_LIT> : if ( REGNO ( x ) >= ARRAY_SIZE ( qi_reg_name ) ) goto normal ; fputs ( qi_reg_name [ REGNO ( x ) ] , file ) ; break ; case <NUM_LIT> : if ( REGNO ( x ) >= ARRAY_SIZE ( qi_high_reg_name ) ) goto normal ; fputs ( qi_high_reg_name [ REGNO ( x ) ] , file ) ; break ; default : gcc_unreachable ( )


<s> <ISA_LIT>MCAsmInfo :: <ISA_LIT>MCAsmInfo ( const Triple & TheTriple ) { if ( ( TheTriple . getArch ( ) == Triple :: mips ) || ( TheTriple . getArch ( ) == Triple :: mips64 ) ) IsLittleEndian = false ; if ( ( TheTriple . getArch ( ) == Triple :: mips64el ) || ( TheTriple . getArch ( ) == Triple :: mips64 ) ) { PointerSize = CalleeSaveStackSlotSize = <NUM_LIT> ; } if ( ( TheTriple . getArch ( ) == Triple :: mipsel ) || ( TheTriple . getArch ( ) == Triple :: mips ) ) { PrivateGlobalPrefix = <STR_LIT> ; PrivateLabelPrefix = <STR_LIT> ; } AlignmentIsInBytes = false ; Data16bitsDirective = <STR_LIT> ; Data32bitsDirective = <STR_LIT> ; Data64bitsDirective = <STR_LIT> ; CommentString = <STR_LIT> ; ZeroDirective = <STR_LIT> ; GPRel32Directive = <STR_LIT> ; GPRel64Directive = <STR_LIT> ; UseAssignmentForEHBegin = true ; SupportsDebugInformation = true ; ExceptionsType = ExceptionHandling :: DwarfCFI ; DwarfRegNumForCFI = true ; if ( TheTriple . getArch ( ) == Triple :: mips || TheTriple . getArch ( ) == Triple :: mipsel )


<s> return decodeUImmOperand < <NUM_LIT> > ( Inst ,


<s> bool <ISA_LIT>CallLowering :: lowerCall ( MachineIRBuilder & MIRBuilder , CallingConv :: ID CallConv , const MachineOperand & Callee , const ArgInfo & OrigRet , ArrayRef < ArgInfo > OrigArgs ) const { MachineFunction & MF = MIRBuilder . getMF ( ) ; const auto & TLI = * getTLI < <ISA_LIT>TargetLowering > ( ) ; const auto & DL = MF . getDataLayout ( ) ; const auto & STI = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; const TargetRegisterInfo * TRI = STI . getRegisterInfo ( ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; if ( STI . genLongCalls ( ) ) return false ; auto CallSeqStart = MIRBuilder . buildInstr ( <STR_LIT> ) ; bool isDirect = ! Callee . isReg ( ) ; auto CallOpcode = isDirect ? <STR_LIT> : STI . hasV5TOps ( ) ? <STR_LIT> : STI . hasV4TOps ( ) ? <STR_LIT> : <STR_LIT> ; auto MIB = MIRBuilder . buildInstrNoInsert ( CallOpcode ) . add ( Callee ) . addRegMask ( TRI -> getCallPreservedMask ( MF , CallConv ) ) ; if ( Callee . isReg ( ) ) { auto CalleeReg = Callee . getReg ( ) ; if ( CalleeReg && ! TRI -> isPhysicalRegister ( CalleeReg ) ) MIB -> getOperand ( <NUM_LIT> ) . setReg ( constrainOperandRegClass ( MF , * TRI , MRI , * STI . getInstrInfo ( ) , * STI . getRegBankInfo ( ) , * MIB . getInstr ( ) , MIB -> getDesc ( ) , Callee , <NUM_LIT> ) ) ; } SmallVector < ArgInfo , <NUM_LIT> > ArgInfos ; for ( auto Arg : OrigArgs ) { if ( ! isSupportedType ( DL , TLI , Arg . Ty ) ) return false ; if ( ! Arg . IsFixed ) return false ; if ( Arg . Flags . isByVal ( ) ) return false ; SmallVector < unsigned , <NUM_LIT> > Regs ; splitToValueTypes ( Arg , ArgInfos , MF , [ & ] ( unsigned Reg , uint64_t Offset ) { Regs . push_back ( Reg


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { MCInst TmpInst ; TmpInst . setOpcode ( getRealIndexedOpcode ( MI -> getOpcode ( ) ) ) ; TmpInst . addOperand ( MCOperand :: CreateReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ) ; TmpInst . addOperand ( MCOperand :: CreateReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ) ; TmpInst . addOperand ( MCOperand :: CreateImm ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ) ; EmitToStreamer ( OutStreamer , TmpInst ) ; return ; } case <STR_LIT> : { MCInst TmpInst ; TmpInst . setOpcode ( <STR_LIT> ) ; TmpInst . addOperand ( MCOperand :: CreateReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ) ; EmitToStreamer ( OutStreamer , TmpInst ) ; return ; } case <STR_LIT> : { MCOperand Dest ; MCInstLowering . lowerOperand ( MI -> getOperand ( <NUM_LIT> ) , Dest ) ; MCInst TmpInst ; TmpInst . setOpcode ( <STR_LIT> ) ; TmpInst . addOperand ( Dest ) ; EmitToStreamer ( OutStreamer , TmpInst ) ; return ; } case <STR_LIT> : { MCOperand Callee , Sym ; MCInstLowering . lowerOperand ( MI -> getOperand ( <NUM_LIT> ) , Callee ) ; MCInstLowering . lowerOperand ( MI -> getOperand ( <NUM_LIT> ) , Sym ) ; MCInst TLSDescCall ; TLSDescCall . setOpcode ( <STR_LIT> ) ; TLSDescCall . addOperand ( Sym ) ; EmitToStreamer ( OutStreamer


<s> switch ( Predicate ) { default : break ; case CmpInst :: FCMP_OEQ : SETFOpc = & SETFOpcTable [ <NUM_LIT> ] [ <NUM_LIT> ] ; break ; case CmpInst :: FCMP_UNE : SETFOpc = & SETFOpcTable [ <NUM_LIT> ] [ <NUM_LIT> ] ; break ; } ResultReg = createResultReg ( & <STR_LIT> ) ; if ( SETFOpc ) { if ( ! <ISA_LIT>FastEmitCompare ( LHS , RHS , VT , I -> getDebugLoc ( ) ) ) return false ; unsigned FlagReg1 = createResultReg ( & <STR_LIT> ) ; unsigned FlagReg2 = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( SETFOpc [ <NUM_LIT> ] ) , FlagReg1 ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( SETFOpc [ <NUM_LIT> ] ) , FlagReg2 ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( SETFOpc [ <NUM_LIT> ] ) , ResultReg ) . addReg ( FlagReg1 ) . addReg ( FlagReg2 ) ; updateValueMap ( I , ResultReg ) ; return true ; } <STR_LIT> CC ; bool


<s> const MachineOperand & MO = MI -> getOperand ( opNum ) ; if ( MO . getType ( ) == MachineOperand :: MO_Immediate ) O << ( unsigned int ) MO . getImm ( ) ; else printOperand ( MI , opNum


<s> if ( Imm == <NUM_LIT> || Imm == <NUM_LIT> ) return <NUM_LIT> ; return std :: min ( getIntImmCost ( Imm , Ty , CostKind ) , getIntImmCost ( ~ Imm , Ty , CostKind ) ) ; } if ( Opcode == Instruction :: Add ) return std :: min ( getIntImmCost ( Imm , Ty , CostKind ) , getIntImmCost ( - Imm , Ty , CostKind ) ) ; if ( Opcode == Instruction :: ICmp && Imm . isNegative ( ) && Ty -> getIntegerBitWidth ( ) == <NUM_LIT> ) { int64_t NegImm = - Imm . getSExtValue ( ) ; if ( ST -> isThumb2 ( ) && NegImm < <NUM_LIT> << <NUM_LIT> ) return <NUM_LIT> ; if ( ST -> isThumb ( ) && NegImm < <NUM_LIT> << <NUM_LIT> ) return <NUM_LIT> ; } if ( Opcode == Instruction :: Xor && Imm . isAllOnes ( ) ) return <NUM_LIT> ; if ( Inst && ( ( ST -> hasV6Ops ( ) && ! ST -> isThumb ( ) ) || ST -> isThumb2 ( ) ) && Ty -> getIntegerBitWidth ( ) <= <NUM_LIT> ) { if ( isSSATMinMaxPattern ( Inst , Imm ) || ( isa < ICmpInst > ( Inst ) && Inst -> hasOneUse ( ) && isSSATMinMaxPattern ( cast < Instruction > ( * Inst ->

user_begin ( ) ) , Imm ) ) ) return <NUM_LIT> ;


<s> do { if ( statep ) arc_ccfsm_post_advance ( insn , statep ) ; insn = NEXT_INSN ( insn ) ; if ( ! insn || BARRIER_P ( insn ) ) return NULL ; if ( statep ) arc_ccfsm_advance ( insn , statep ) ; } while ( NOTE_P ( insn ) || ( cfun -> machine -> arc_reorg_started && LABEL_P ( insn ) && ! label_to_alignment ( insn ) ) || ( NONJUMP_INSN_P ( insn ) && ( GET_CODE ( PATTERN ( insn ) ) == USE || GET_CODE ( PATTERN ( insn ) ) == CLOBBER ) ) ) ; if ( ! LABEL_P ( insn ) ) { gcc_assert ( INSN_P ( insn ) ) ; pat = PATTERN ( insn ) ; if ( GET_CODE ( pat ) == ADDR_VEC || GET_CODE ( pat ) == ADDR_DIFF_VEC ) return NULL ; if ( GET_CODE ( pat ) == SEQUENCE ) return as_a < rtx_insn * > ( XVECEXP ( pat , <NUM_LIT> , <NUM_LIT> ) ) ; } return insn


<s> if ( M -> modifiesRegister ( SReg , TRI ) ) return Changed ; ReadsSreg |= M -> readsRegister ( SReg , TRI ) ; } if ( M == E || ! M -> isMoveImmediate ( ) || ! M -> getOperand ( <NUM_LIT> ) . isImm ( ) || ( M -> getOperand ( <NUM_LIT> ) . getImm ( ) != - <NUM_LIT> && M -> getOperand ( <NUM_LIT> ) . getImm ( ) != <NUM_LIT> ) ) return Changed ; MaskValue = M -> getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( ! ReadsSreg && Op2 . isKill ( ) ) { A -> getOperand ( <NUM_LIT> ) . ChangeToImmediate ( MaskValue ) ; M -> eraseFromParent ( ) ; } } else if ( Op2 . isImm ( ) ) { MaskValue = Op2 . getImm ( ) ; } else { llvm_unreachable ( <STR_LIT> ) ; } assert ( MaskValue == <NUM_LIT> || MaskValue == - <NUM_LIT> ) ; if ( A -> getOpcode ( ) == AndN2 ) MaskValue = ~ MaskValue ; if ( ! ReadsCond && A -> registerDefIsDead ( <STR_LIT> ) && MI . killsRegister ( CondReg , TRI ) ) A -> eraseFromParent ( ) ; bool IsVCCZ = MI . getOpcode ( ) == <STR_LIT> ; if ( SReg == ExecReg ) { if ( IsVCCZ ) { MI . eraseFromParent ( ) ; return true ; } MI . setDesc ( TII -> get ( <STR_LIT> ) ) ; } else if ( IsVCCZ && MaskValue == <NUM_LIT> ) { MachineBasicBlock * Parent = MI . getParent ( ) ; SmallVector < MachineInstr * , <NUM_LIT> > ToRemove ; bool Found = false ; for ( MachineInstr & Term : Parent -> terminators ( ) ) { if ( Found ) { if ( Term . isBranch ( ) ) ToRemove . push_back ( & Term ) ; } else { Found = Term . isIdenticalTo ( MI ) ; } } assert ( Found && <STR_LIT> ) ; for ( auto BranchMI : ToRemove ) { MachineOperand & Dst = BranchMI -> getOperand ( <NUM_LIT> ) ; assert ( Dst . isMBB ( ) && <STR_LIT> ) ; Parent -> removeSuccessor ( Dst . getMBB ( ) ) ; BranchMI -> eraseFromParent ( ) ; } if ( MachineBasicBlock * Succ = Parent -> getFallThrough ( ) ) { Parent -> removeSuccessor ( Succ ) ; } MI . setDesc ( TII -> get ( <STR_LIT> ) ) ; } else if ( ! IsVCCZ && MaskValue == <NUM_LIT> ) { MachineOperand & Dst = MI . getOperand ( <NUM_LIT> ) ; assert ( Dst . isMBB (


<s> unsigned internalKnownBits ( ) const { unsigned Bits = Unalign ? Unalign : KnownBits ; if ( Size & ( ( <NUM_LIT> << Bits ) - <NUM_LIT> ) ) Bits = CountTrailingZeros_32 ( Size ) ; return Bits


<s> SmallDenseSet < unsigned > SGPRsUsed ; Register SGPRReg = findUsedSGPR ( MI , VOP3Idx ) ; if ( SGPRReg != <STR_LIT> ) { SGPRsUsed . insert ( SGPRReg ) ; -- ConstantBusLimit ; } for ( unsigned i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) { int Idx = VOP3Idx [ i ] ; if ( Idx == - <NUM_LIT> ) break ; MachineOperand & MO = MI . getOperand ( Idx ) ; if ( ! MO . isReg ( ) ) { if ( ! isLiteralConstantLike ( MO , get ( Opc ) . OpInfo [ Idx ] ) ) continue ; if ( LiteralLimit > <NUM_LIT> && ConstantBusLimit > <NUM_LIT> ) { -- LiteralLimit ; -- ConstantBusLimit ; continue ; } -- LiteralLimit ; -- ConstantBusLimit ; legalizeOpWithMove ( MI , Idx ) ; continue ; } if ( RI . hasAGPRs ( MRI . getRegClass ( MO . getReg ( ) ) ) && ! isOperandLegal ( MI , Idx , & MO ) ) { legalizeOpWithMove ( MI , Idx ) ; continue ; } if ( ! RI . isSGPRClass ( MRI . getRegClass ( MO . getReg ( ) ) ) ) continue ; if ( SGPRsUsed . count ( MO . getReg ( ) ) ) continue ; if ( ConstantBusLimit >


<s> const uint64_t ChunkVal = Chunk -> first ; const unsigned Count = Chunk -> second ; uint64_t Encoding = <NUM_LIT> ; if ( ( Count != <NUM_LIT> && Count != <NUM_LIT> ) || ! canUseOrr ( ChunkVal , Encoding ) ) continue ; const bool CountThree = Count == <NUM_LIT> ; Insn . push_back ( { <STR_LIT> , <NUM_LIT> , Encoding } ) ; unsigned ShiftAmt = <NUM_LIT> ; uint64_t Imm16 = <NUM_LIT> ; for ( ; ShiftAmt < <NUM_LIT>


<s> bool Changed = false ; SmallSetVector < Function * , <NUM_LIT> > Functions ; for ( auto & F : M . getFunctionList ( ) ) { if ( ! F . isDeclaration ( ) ) continue ; switch ( F . getIntrinsicID ( ) ) { case <STR_LIT> : case <STR_LIT> : case


<s> return try_constant_tricks ( value , & x


<s> else return false ; * ref = XVECEXP ( * ref , <NUM_LIT> , <NUM_LIT> ) ; break ; default : return false ; } if ( ! REG_P ( * ref ) || GET_MODE ( * ref ) != Pmode ) return false ; if ( REGNO ( * ref ) == STACK_POINTER_REGNUM || REGNO ( * ref ) == FRAME_POINTER_REGNUM || ( ( reload_completed || reload_in_progress ) && frame_pointer_needed && REGNO ( * ref ) == HARD_FRAME_POINTER_REGNUM ) || REGNO ( * ref ) == ARG_POINTER_REGNUM || ( flag_pic && REGNO ( * ref )

== PIC_OFFSET_TABLE_REGNUM ) ) * is_ptr = * is_base_ptr = true ;


<s> void <ISA_LIT>ParamManager :: addParamName ( std :: string Name , unsigned Index ) { char * name = ( char * ) malloc (