<s> if ( ! BaseOp . isReg ( ) || BaseOp . getReg ( ) != AddDefR ) return false ; MachineOperand OffsetOp = MID . mayLoad ( ) ? MI -> getOperand ( <NUM_LIT> ) : MI -> getOperand ( <NUM_LIT> ) ; if ( ! OffsetOp . isImm ( ) ) return false ; int64_t newOffset = OffsetOp . getImm ( ) + AddMI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( ! isValidOffset ( MI , newOffset ) ) return false ; Register BaseReg = AddMI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( ! isSafeToExtLR ( AddSN , AddMI , BaseReg , UNodeList ) ) return false ; } bool Changed = false ; for ( auto I = UNodeList . rbegin ( ) , E = UNodeList . rend ( ) ; I != E ; ++ I ) { NodeAddr < UseNode * > UseN = * I ; assert ( ! ( UseN . Addr -> getFlags ( ) & NodeAttrs :: PhiRef ) && <STR_LIT> ) ; NodeAddr < StmtNode * > OwnerN = UseN . Addr -> getOwner ( * DFG ) ; MachineInstr * UseMI = OwnerN . Addr -> getCode ( ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << UseMI -> getParent ( ) -> getNumber ( ) << <STR_LIT> << * UseMI << <STR_LIT> ) ; Changed |= updateAddUses ( AddMI ,


<s> MDPtr = dyn_cast < MDNode > ( LoopMD -> getOperand ( i ) ) ; if ( ! MDPtr ) continue ; MDString * S = dyn_cast < MDString > ( MDPtr -> getOperand ( <NUM_LIT> ) ) ; if ( ! S ) continue ; if ( S -> getString ( ) . equals ( <STR_LIT> ) ) { assert ( MDPtr -> getNumOperands ( ) == <NUM_LIT> && <STR_LIT> ) ; unsigned Count = mdconst :: extract < ConstantInt > ( MDPtr -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; assert ( Count >= <NUM_LIT> && <STR_LIT> ) ; return Count ; } } return <NUM_LIT>


<s> unsigned <ISA_LIT>CodeEmitter :: getJumpTargetOpValue ( const MachineInstr & MI , unsigned OpNo ) const { return


<s> assert ( VT . isInteger ( ) && <STR_LIT> ) ; assert ( V0VT . isVector ( ) && <STR_LIT> ) ; EVT V0EltVT = V0VT . getVectorElementType ( ) ; if ( ! V0EltVT . isInteger ( ) ) return SDValue ( ) ; const unsigned EltSize = EltVT . getSizeInBits ( ) ; const unsigned V0EltSize = V0EltVT . getSizeInBits ( ) ; if ( V0EltSize <= EltSize ) return SDValue ( ) ; assert ( ( ( V0EltSize % EltSize ) == <NUM_LIT> ) && <STR_LIT> ) ; const unsigned V0Opc = V0 . getOpcode ( ) ; const unsigned Scale =


<s> switch ( VA . getLocInfo ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case CCValAssign :: Full : break ; case CCValAssign :: SExt : Arg = DAG . getNode ( <STR_LIT> , dl , VA . getLocVT ( ) , Arg ) ; break ; case CCValAssign :: ZExt : Arg = DAG . getNode ( <STR_LIT> , dl , VA . getLocVT ( ) , Arg ) ; break ; case CCValAssign :: AExt : Arg = DAG . getNode ( <STR_LIT> , dl , VA . getLocVT ( ) , Arg ) ; break ; } if ( VA . isRegLoc ( ) ) { RegsToPass . push_back ( std :: make_pair ( VA . getLocReg ( ) , Arg ) ) ; } else { assert ( VA . isMemLoc ( ) ) ; int Offset = VA . getLocMemOffset ( ) ; MemOpChains . push_back ( DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Chain , Arg , DAG . getConstant ( Offset / <NUM_LIT> , <STR_LIT> ) ) ) ; } } if ( ! MemOpChains . empty ( ) ) Chain = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , & MemOpChains [ <NUM_LIT> ] , MemOpChains . size ( ) ) ; SDValue InFlag ; for ( unsigned i = <NUM_LIT> , e = RegsToPass . size ( ) ; i != e ; ++ i ) { Chain = DAG . getCopyToReg ( Chain , dl , RegsToPass [ i ] . first , RegsToPass [ i ] . second , InFlag ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; } if ( GlobalAddressSDNode * G = dyn_cast < GlobalAddressSDNode > ( Callee ) ) Callee = DAG . getTargetGlobalAddress ( G -> getGlobal


<s> return getMachineOpValue ( MI , MI . getOperand ( OpNo ) ,


<s> unsigned <ISA_LIT>TTIImpl :: getMinVectorRegisterBitWidth


<s> bool notLoop = true ; if ( std :: find ( BBlist . begin ( ) , BBlist . end ( ) , BB ) != BBlist . end ( ) ) notLoop = false ; BBlist . push_back ( BB ) ; nodeContainsSwitchBranch ( BB ) ; int cycle = getBBCycles ( VMMB , false ) ; workingNode = new CostLeaf ( BB ) ; workingNode -> setMachineBB ( VMMB ) ; MachineLoop * loop = MLI . getLoopFor ( VMMB ) ; <ISA_LIT>_DEBUG ( <STR_LIT> + to_string ( VMMB -> getNumber ( ) ) + <STR_LIT> ) ; if ( isSwitchNode ( BB ) ) { <ISA_LIT>_DEBUG ( <STR_LIT> ) workingNode ->


<s> int OffsetStride = IsUnscaled ? getMemScale ( FirstMI ) : <NUM_LIT> ; bool IsPromotableZeroStore = isPromotableZeroStoreInst ( FirstMI ) ; ModifiedRegUnits . clear ( ) ; UsedRegUnits . clear ( ) ; SmallVector < MachineInstr * , <NUM_LIT> > MemInsns ; for ( unsigned Count = <NUM_LIT> ; MBBI != E && Count < Limit ; ++ MBBI ) { MachineInstr & MI = * MBBI ; if ( ! MI . isTransient ( ) ) ++ Count ; Flags . setSExtIdx ( - <NUM_LIT> ) ; if ( areCandidatesToMergeOrPair ( FirstMI , MI , Flags , TII ) && getLdStOffsetOp ( MI ) . isImm ( ) ) { assert ( MI . mayLoadOrStore ( ) && <STR_LIT> ) ; Register MIBaseReg = getLdStBaseOp ( MI ) . getReg ( ) ; int MIOffset = getLdStOffsetOp ( MI ) . getImm ( ) ; bool MIIsUnscaled = TII -> isUnscaledLdSt ( MI ) ; if ( IsUnscaled != MIIsUnscaled ) { int MemSize = getMemScale ( MI ) ; if ( MIIsUnscaled ) { if ( MIOffset % MemSize ) { LiveRegUnits :: accumulateUsedDefed ( MI , ModifiedRegUnits , UsedRegUnits , TRI ) ; MemInsns . push_back ( & MI ) ; continue ; } MIOffset /= MemSize ; } else { MIOffset *= MemSize ; } } if ( BaseReg == MIBaseReg && ( ( Offset == MIOffset + OffsetStride ) || ( Offset + OffsetStride == MIOffset ) ) ) { int MinOffset = Offset < MIOffset ? Offset : MIOffset ; if ( FindNarrowMerge ) { if ( ( ! IsUnscaled && alignTo ( MinOffset , <NUM_LIT> ) != MinOffset ) || ( IsPromotableZeroStore && Reg != getLdStRegOp ( MI ) . getReg ( ) ) ) { LiveRegUnits :: accumulateUsedDefed ( MI , ModifiedRegUnits , UsedRegUnits , TRI ) ; MemInsns . push_back ( & MI ) ; continue ; } } else { if ( ! inBoundsForPair ( IsUnscaled , MinOffset , OffsetStride ) ) { LiveRegUnits :: accumulateUsedDefed ( MI , ModifiedRegUnits ,


<s> static MCInstrInfo * create<ISA_LIT>MCInstrInfo ( ) { MCInstrInfo * X = new MCInstrInfo ( ) ; Init<ISA_LIT>MCInstrInfo ( X ) ; return X


<s> unsigned StackPtrReg = FuncInfo -> getStackPtrOffsetReg ( ) ; if ( StackPtrReg == <STR_LIT> ) return ; const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; uint32_t NumBytes = MFI . getStackSize ( ) ; DebugLoc DL ; if ( NumBytes != <NUM_LIT> && hasSP ( MF ) ) { uint32_t RoundedSize = FuncInfo -> isStackRealigned ( ) ? NumBytes + MFI . getMaxAlignment ( ) : NumBytes ; BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) , StackPtrReg ) . addReg ( StackPtrReg ) . addImm (

RoundedSize * ST . getWavefrontSize ( ) ) ;


<s> EVT VT = Op . getValueType ( ) ; assert ( VT . is256BitVector ( ) && Op . getOpcode ( ) == <STR_LIT> && <STR_LIT> ) ; unsigned NumElems = VT . getVectorNumElements ( ) ; DebugLoc dl = Op . getDebugLoc ( ) ; SDValue CC = Op . getOperand ( <NUM_LIT> ) ; SDValue LHS = Op . getOperand ( <NUM_LIT> ) ; SDValue LHS1 = Extract128BitVector ( LHS , <NUM_LIT> , DAG , dl ) ; SDValue LHS2 = Extract128BitVector ( LHS , NumElems / <NUM_LIT> , DAG , dl ) ; SDValue RHS = Op . getOperand


<s> if ( Mask . getOpcode ( ) == <STR_LIT> ) { SmallVector < SDValue , <NUM_LIT> > NewOps ( N -> op_begin ( ) , N ->


<s> uint32_t RotValue = GetCMulRotation ( N -> getOperand ( <NUM_LIT> ) ) ; Ops . push_back ( CurDAG -> getTargetConstant ( RotValue , Loc , <STR_LIT> ) ) ; if ( Predicated ) AddMVEPredicateToOps ( Ops , Loc , N -> getOperand ( <NUM_LIT> ) ) ; else AddEmptyMVEPredicateToOps ( Ops , Loc ) ; EVT VT = N -> getValueType (


<s> ErrorLoc = ( ( <ISA_LIT>Operand * ) Operands [ ErrorInfo ] ) -> getStartLoc ( ) ; if ( ErrorLoc == SMLoc ( ) ) ErrorLoc = IDLoc ; } return Error ( ErrorLoc , <STR_LIT> ) ; } case Match_MnemonicFail : return Error ( IDLoc , <STR_LIT> ) ; case Match_ConversionFail : return true ; case Match_RequiresNotITBlock : return Error ( IDLoc , <STR_LIT> ) ; case Match_RequiresITBlock : return Error ( IDLoc , <STR_LIT>


<s> MachineBasicBlock & MBB = * MI . getParent ( ) ; RegScavenger RS ; RS . enterBasicBlock ( MBB ) ; RS . forward ( MI ) ; BitVector Candidates = TRI -> getAllocatableSet ( * MBB . getParent ( ) , & <STR_LIT> ) ; for ( MachineOperand & MO : MI . operands (


<s> SDValue OneSubA = DAG . getNode ( <STR_LIT> , DL , VT , DAG . getConstantFP ( <NUM_LIT> , DL , <STR_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; SDValue OneSubAC = DAG . getNode ( <STR_LIT> , DL , VT , OneSubA , Op . getOperand ( <NUM_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , DL , VT , DAG . getNode ( <STR_LIT> , DL , VT , Op . getOperand ( <NUM_LIT> ) , Op .

getOperand ( <NUM_LIT> ) ) , OneSubAC ) ;


<s> } if ( MI -> getOpcode ( ) == <STR_LIT> ) { unsigned LabelId = ( unsigned ) MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned CPIdx = ( unsigned ) MI -> getOperand ( <NUM_LIT> ) . getIndex ( ) ; if ( ! InConstantPool ) { OutStreamer . EmitDataRegion ( MCDR_DataRegion ) ; InConstantPool = true ; } OutStreamer . EmitLabel ( GetCPISymbol ( LabelId ) ) ; const MachineConstantPoolEntry & MCPE = MCP -> getConstants ( ) [ CPIdx ] ; if ( MCPE . isMachineConstantPoolEntry ( ) ) EmitMachineConstantPoolValue ( MCPE . Val . MachineCPVal ) ; else EmitGlobalConstant ( MCPE . Val . ConstVal ) ; return ; } MachineBasicBlock :: const_instr_iterator I = MI ; MachineBasicBlock :: const_instr_iterator E = MI -> getParent ( ) ->


<s> EmitInstruction ( Out , MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( - <NUM_LIT> ) ) ; if ( RegCtx . AddressReg != <STR_LIT> ) { EmitInstruction ( Out , MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( RegCtx . addressReg ( <STR_LIT> ) ) ) ; } const std :: string & Fn = FuncName ( AccessSize , IsWrite ) ; MCSymbol * FnSym = Ctx . GetOrCreateSymbol ( StringRef ( Fn ) ) ; const MCSymbolRefExpr * FnExpr = MCSymbolRefExpr :: Create ( FnSym , MCSymbolRefExpr :: VK_PLT , Ctx ) ; EmitInstruction ( Out , MCInstBuilder ( <STR_LIT>


<s> const unsigned MMOpc = Subtarget . has<ISA_LIT>32r6 ( ) ? <STR_LIT> : <STR_LIT> ; const unsigned Opc = Subtarget . inMicro<ISA_LIT>Mode ( ) ? MMOpc : <STR_LIT> ; return BuildMI ( MBB , MI , DL , get ( Opc ) , <STR_LIT> ) . addReg ( <STR_LIT> )


<s> void <ISA_LIT>AsmParser :: createAddu ( unsigned DstReg , unsigned SrcReg , unsigned TrgReg , SmallVectorImpl < MCInst > & Instructions ) { MCInst AdduInst ; AdduInst . setOpcode ( <STR_LIT> ) ; AdduInst . addOperand ( MCOperand :: createReg ( DstReg ) ) ; AdduInst . addOperand ( MCOperand :: createReg ( SrcReg ) ) ; AdduInst . addOperand ( MCOperand :: createReg ( TrgReg ) ) ; Instructions . push_back (


<s> if ( ! TargetRegisterInfo :: isVirtualRegister ( SrcReg ) ) { TII -> moveToVALU ( MI ) ; break ; } MachineInstr * DefMI = MRI . getVRegDef ( SrcReg ) ; unsigned SMovOp ; int64_t Imm ; if ( isSafeToFoldImmIntoCopy ( & MI , DefMI , TII , SMovOp , Imm ) ) { MI . getOperand ( <NUM_LIT> ) . ChangeToImmediate ( Imm ) ; MI . addImplicitDefUseOperands ( MF ) ; MI . setDesc ( TII -> get ( SMovOp ) ) ; break ; } TII -> moveToVALU ( MI ) ; } else if ( isSGPRToVGPRCopy ( SrcRC , DstRC , * TRI ) ) { tryChangeVGPRtoSGPRinCopy ( MI , TRI , TII ) ; } break ; } case <STR_LIT> : { unsigned Reg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( ! TRI -> isSGPRClass ( MRI . getRegClass ( Reg ) ) ) break ; bool HasVGPROperand = phiHasVGPROperands ( MI , MRI , TRI , TII ) ; if ( ! HasVGPROperand ) { bool Uniform = true ; MachineBasicBlock * Join = MI . getParent ( ) ; for ( auto & O : MI . explicit_operands ( ) ) { if ( O . isMBB ( ) ) { MachineBasicBlock * Source = O . getMBB ( ) ; SetVector < MachineBasicBlock * > & SourcePDF = PDF [ Source ] ; SetVector < MachineBasicBlock * > & JoinPDF = PDF [ Join ] ; SetVector < MachineBasicBlock * > CDList ; for ( auto & I : SourcePDF ) { if ( ! JoinPDF . count ( I ) || MDT -> dominates ( Join , I ) ) { if ( hasTerminatorThatModifiesExec ( * I , * TRI ) ) Uniform = false ; } } } } if ( Uniform ) { DEBUG ( dbgs ( ) << <STR_LIT> << MI << '\n' ) ; break ; } } SmallSet < unsigned , <NUM_LIT> > Visited ; if ( HasVGPROperand || ! phiHasBreakDef ( MI , MRI , Visited ) ) { DEBUG ( dbgs ( ) << <STR_LIT> << MI ) ; TII -> moveToVALU ( MI ) ; } break ; } case <STR_LIT> : if ( TRI -> hasVGPRs ( TII -> getOpRegClass ( MI , <NUM_LIT> ) ) || ! hasVGPROperands ( MI , TRI ) ) { foldVGPRCopyIntoRegSequence ( MI , TRI , TII , MRI ) ; continue ; } DEBUG ( dbgs ( ) << <STR_LIT> << MI ) ; TII -> moveToVALU ( MI ) ; break ; case <STR_LIT> : { const TargetRegisterClass * DstRC , * Src0RC , * Src1RC ; DstRC = MRI . getRegClass ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; Src0RC = MRI . getRegClass ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; Src1RC = MRI . getRegClass ( MI . getOperand ( <NUM_LIT> )


<s> inline bool AreGprs64bit ( ) const { return IsN32 ( )


<s> return ( __m256 ) __builtin_ia32_vpermilps256 ( (


<s> const MCExpr * Val = getImm ( ) ; return static_cast < const MCConstantExpr * > ( Val ) ->


<s> rtx pat = gen_rtx_SET ( operands [ <NUM_LIT> ] , gen_rtx_fmt_ee ( code , GET_MODE ( operands [ <NUM_LIT> ] ) , x , const0_rtx ) ) ; if ( mode == SImode || ( code == NE && TARGET_VIS3 ) ) { rtx clobber = gen_rtx_CLOBBER ( VOIDmode , gen_rtx_REG ( mode == SImode ? CCmode : CCXmode , SPARC_ICC_REG ) ) ; pat = gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( <NUM_LIT> , pat , clobber ) ) ; } emit_insn ( pat ) ; return true ; } if ( TARGET_ARCH64 && mode == DImode && ! ( ( code == LTU || code == GTU ) && TARGET_VIS3 ) && gen_v9_scc ( operands [ <NUM_LIT> ] , code , x , y ) ) return true ; if ( code == GTU || code == LEU


<s> const <ISA_LIT>TargetMachine & RTM = static_cast < const <ISA_LIT>TargetMachine & > ( TM ) ; const <ISA_LIT>Subtarget STI ( TT , CPU , CPU , FS , <STR_LIT> , RTM ) ; RTS . emitTargetAttributes ( STI


<s> return xmalloc ( sizeof ( rs6000_sched_context_def


<s> MachineFunctionProperties <ISA_LIT>DelaySlotFiller :: getRequiredProperties ( )


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case


<s> return & * MIB ; } ; auto RemoveDeadBranch = [ ] ( MachineInstr * I ) { MachineBasicBlock * BB = I -> getParent ( ) ; MachineInstr * Terminator = & BB -> instr_back ( ) ; if ( Terminator -> isUnconditionalBranch ( ) && I != Terminator ) { MachineBasicBlock * Succ = Terminator -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; if ( BB -> isLayoutSuccessor ( Succ ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * Terminator ) ; Terminator -> eraseFromParent ( ) ; } } } ; if ( Revert ) { if ( Start -> getOpcode ( ) == <STR_LIT> ) RevertWhile ( Start ) ; else Start -> eraseFromParent ( ) ; bool FlagsAlreadySet = RevertLoopDec ( Dec , true ) ; RevertLoopEnd ( End , FlagsAlreadySet ) ; } else { Start = ExpandLoopStart ( ML , Start , InsertPt ) ; RemoveDeadBranch ( Start ) ; End = ExpandLoopEnd ( ML , Dec , End


<s> const <ISA_LIT>RegisterInfo & HRI = * Subtarget . getRegisterInfo ( ) ; SmallVector < unsigned , <NUM_LIT> > DefsA ; SmallVector < unsigned , <NUM_LIT> > DefsB ; SmallVector < unsigned , <NUM_LIT> > UsesA ; SmallVector < unsigned , <NUM_LIT> > UsesB ; parseOperands ( ProdMI , DefsA , UsesA ) ; parseOperands ( ConsMI , DefsB , UsesB ) ; for ( auto & RegA : DefsA ) for ( auto & RegB : UsesB ) { if ( RegA == RegB ) return true ; if ( Register :: isPhysicalRegister ( RegA ) ) for ( MCSubRegIterator SubRegs ( RegA , & HRI ) ; SubRegs . isValid ( ) ; ++ SubRegs ) if ( RegB == * SubRegs ) return true ; if ( Register :: isPhysicalRegister ( RegB ) ) for ( MCSubRegIterator SubRegs ( RegB , & HRI ) ; SubRegs . isValid ( ) ; ++ SubRegs ) if ( RegA ==


<s> if ( ! isOperationLegalOrCustom ( <STR_LIT> , ResVT ) ) return false ; return ( Index == <NUM_LIT> || Index ==


<s> maskcmp = true ; cmp_mode = nbits > <NUM_LIT> ? int_mode_for_size ( nbits , <NUM_LIT> ) . require ( ) : E_QImode ; } else cmp_mode = cmp_ops_mode ; cmp_op0 = force_reg ( cmp_ops_mode , cmp_op0 ) ; bool ( * op1_predicate ) ( rtx , machine_mode ) = VECTOR_MODE_P ( cmp_ops_mode ) ? vector_operand : nonimmediate_operand ; if ( ! op1_predicate ( cmp_op1 , cmp_ops_mode ) ) cmp_op1 = force_reg ( cmp_ops_mode , cmp_op1 ) ; if ( optimize || ( maskcmp && cmp_mode != mode ) || ( op_true && reg_overlap_mentioned_p ( dest , op_true ) ) || ( op_false && reg_overlap_mentioned_p ( dest , op_false ) ) ) dest = gen_reg_rtx ( maskcmp ? cmp_mode : mode ) ; if ( maskcmp ) { bool ok = ix86_expand_mask_vec_cmp ( dest , code , cmp_op0 , cmp_op1 ) ; gcc_assert ( ok ) ; return dest


<s> emitCommonHeader ( ) ; OS . emitInt32 ( <STR_LIT> ) ; uint32_t TypeLen = <NUM_LIT> , StrLen ; for ( const auto & TypeEntry : TypeEntries ) TypeLen += TypeEntry -> getSize ( ) ; StrLen = StringTable . getSize ( ) ; OS . emitInt32 ( <NUM_LIT> ) ; OS . emitInt32 ( TypeLen ) ; OS . emitInt32 ( TypeLen ) ; OS . emitInt32 ( StrLen ) ; for ( const auto & TypeEntry : TypeEntries ) TypeEntry -> emitType ( OS ) ; uint32_t StringOffset = <NUM_LIT> ; for ( const auto & S : StringTable . getTable ( ) ) { OS . AddComment ( <STR_LIT> + std :: to_string ( StringOffset ) ) ; OS . emitBytes ( S ) ; OS . emitBytes ( StringRef ( <STR_LIT> , <NUM_LIT> ) ) ; StringOffset += S . size (


<s> const MachineRegisterInfo * MRI = & DefMI . getParent ( ) -> getParent ( ) -> getRegInfo ( ) ; IsRegCR = MRI -> getRegClass ( Reg ) -> hasSuperClassEq ( & <STR_LIT> ) || MRI -> getRegClass ( Reg ) -> hasSuperClassEq ( & <STR_LIT> ) ; } else { IsRegCR = <STR_LIT> . contains ( Reg ) || <STR_LIT> . contains ( Reg ) ; } if ( UseMI . isBranch ( ) && IsRegCR ) { if ( Latency < <NUM_LIT> ) Latency = getInstrLatency ( ItinData , DefMI ) ; unsigned Directive = Subtarget . getCPUDirective ( ) ; switch ( Directive )


<s> if ( VT == <STR_LIT> || ! isTypeLegal ( I -> getType ( ) , VT ) ) return false ; unsigned Opc = <NUM_LIT> ; const TargetRegisterClass * RC = NULL ; if ( VT . getSimpleVT ( ) == <STR_LIT> ) { Opc = <STR_LIT> ; RC = & <STR_LIT> ; } else if ( VT . getSimpleVT ( ) == <STR_LIT> ) { Opc = <STR_LIT> ; RC = & <STR_LIT> ; } else if ( VT . getSimpleVT ( ) ==


<s> bool <ISA_LIT>AsmParser :: parseDirectiveSetFP ( SMLoc L ) { MCAsmParser & Parser = getParser ( ) ; if ( check ( ! UC . hasFnStart ( ) , L , <STR_LIT> ) || check ( UC . hasHandlerData ( ) , L , <STR_LIT> ) ) return true ; SMLoc FPRegLoc = Parser . getTok ( ) . getLoc ( ) ; int FPReg = tryParseRegister ( ) ; if ( check ( FPReg == - <NUM_LIT> , FPRegLoc , <STR_LIT> ) || Parser . parseToken ( AsmToken :: Comma , <STR_LIT> ) ) return true ; SMLoc SPRegLoc = Parser . getTok ( ) . getLoc ( ) ; int SPReg = tryParseRegister ( ) ; if ( check ( SPReg == - <NUM_LIT> , SPRegLoc , <STR_LIT> ) || check ( SPReg != <STR_LIT> && SPReg != UC . getFPReg ( ) , SPRegLoc , <STR_LIT> ) ) return true ; UC . saveFPReg ( FPReg ) ; int64_t Offset = <NUM_LIT> ; if ( Parser . parseOptionalToken ( AsmToken :: Comma ) ) { if ( Parser . getTok ( ) . isNot ( AsmToken :: Hash ) && Parser . getTok ( ) . isNot ( AsmToken :: Dollar ) ) return Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; Parser . Lex ( ) ; const MCExpr * OffsetExpr ; SMLoc ExLoc = Parser . getTok ( ) . getLoc ( ) ; SMLoc EndLoc ; if ( getParser ( ) . parseExpression ( OffsetExpr , EndLoc ) ) return Error ( ExLoc , <STR_LIT> ) ; const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( OffsetExpr ) ; if ( check ( ! CE , ExLoc ,


<s> initialize<ISA_LIT>VSXFMAMutatePass ( * PassRegistry :: getPassRegistry ( ) ) ; insertPass ( VSXFMAMutateEarly ? & RegisterCoalescerID : & MachineSchedulerID , & <ISA_LIT>VSXFMAMutateID ) ; return


<s> case <STR_LIT> : break ; OPCODE ( RET_FLAG ) ; OPCODE ( CALL ) ; OPCODE ( SIBCALL ) ; OPCODE ( TLS_GDCALL ) ; OPCODE ( TLS_LDCALL ) ; OPCODE ( PCREL_WRAPPER ) ; OPCODE ( PCREL_OFFSET ) ; OPCODE ( IABS ) ; OPCODE ( ICMP ) ; OPCODE ( FCMP ) ; OPCODE ( TM ) ; OPCODE ( BR_CCMASK ) ; OPCODE ( SELECT_CCMASK ) ; OPCODE ( ADJDYNALLOC ) ; OPCODE ( POPCNT ) ; OPCODE ( SMUL_LOHI ) ; OPCODE ( UMUL_LOHI ) ; OPCODE ( SDIVREM ) ; OPCODE ( UDIVREM ) ; OPCODE ( MVC ) ; OPCODE ( MVC_LOOP ) ; OPCODE ( NC ) ; OPCODE ( NC_LOOP ) ; OPCODE ( OC ) ; OPCODE ( OC_LOOP ) ; OPCODE ( XC ) ; OPCODE ( XC_LOOP ) ; OPCODE ( CLC ) ; OPCODE ( CLC_LOOP ) ; OPCODE ( STPCPY ) ; OPCODE ( STRCMP ) ; OPCODE ( SEARCH_STRING ) ; OPCODE ( IPM ) ; OPCODE ( MEMBARRIER ) ; OPCODE ( TBEGIN ) ; OPCODE ( TBEGIN_NOFLOAT ) ; OPCODE ( TEND ) ; OPCODE ( BYTE_MASK ) ; OPCODE ( ROTATE_MASK ) ; OPCODE ( REPLICATE ) ; OPCODE ( JOIN_DWORDS ) ; OPCODE ( SPLAT ) ; OPCODE ( MERGE_HIGH ) ; OPCODE ( MERGE_LOW ) ; OPCODE ( SHL_DOUBLE ) ; OPCODE ( PERMUTE_DWORDS ) ; OPCODE ( PERMUTE ) ; OPCODE ( PACK ) ; OPCODE ( PACKS_CC ) ; OPCODE ( PACKLS_CC ) ; OPCODE ( UNPACK_HIGH ) ; OPCODE ( UNPACKL_HIGH ) ; OPCODE ( UNPACK_LOW ) ; OPCODE ( UNPACKL_LOW ) ; OPCODE ( VSHL_BY_SCALAR ) ; OPCODE ( VSRL_BY_SCALAR ) ; OPCODE ( VSRA_BY_SCALAR ) ; OPCODE ( VSUM ) ; OPCODE ( VICMPE ) ; OPCODE ( VICMPH ) ; OPCODE ( VICMPHL ) ; OPCODE ( VICMPES ) ; OPCODE ( VICMPHS ) ; OPCODE ( VICMPHLS ) ; OPCODE ( VFCMPE ) ; OPCODE ( VFCMPH ) ; OPCODE ( VFCMPHE ) ; OPCODE ( VFCMPES ) ; OPCODE ( VFCMPHS ) ; OPCODE ( VFCMPHES ) ; OPCODE ( VFTCI ) ; OPCODE ( VEXTEND ) ; OPCODE ( VROUND ) ; OPCODE ( VTM ) ; OPCODE ( VFAE_CC ) ; OPCODE ( VFAEZ_CC ) ; OPCODE ( VFEE_CC ) ; OPCODE ( VFEEZ_CC ) ; OPCODE ( VFENE_CC ) ; OPCODE ( VFENEZ_CC ) ; OPCODE ( VISTR_CC ) ; OPCODE ( VSTRC_CC ) ; OPCODE ( VSTRCZ_CC ) ; OPCODE ( TDC ) ; OPCODE ( ATOMIC_SWAPW ) ; OPCODE ( ATOMIC_LOADW_ADD ) ; OPCODE ( ATOMIC_LOADW_SUB ) ; OPCODE ( ATOMIC_LOADW_AND ) ; OPCODE ( ATOMIC_LOADW_OR ) ; OPCODE ( ATOMIC_LOADW_XOR ) ; OPCODE ( ATOMIC_LOADW_NAND ) ; OPCODE ( ATOMIC_LOADW_MIN ) ; OPCODE ( ATOMIC_LOADW_MAX ) ; OPCODE ( ATOMIC_LOADW_UMIN ) ; OPCODE ( ATOMIC_LOADW_UMAX ) ; OPCODE ( ATOMIC_CMP_SWAPW )


<s> case REG : case SUBREG : info -> type = ADDRESS_REG ; info -> reg = x ; info -> offset = const0_rtx ; return riscv_valid_base_register_p ( info -> reg , mode , strict_p ) ; case PLUS : info -> type = ADDRESS_REG ; info -> reg = XEXP ( x , <NUM_LIT> ) ; info -> offset = XEXP ( x , <NUM_LIT> ) ; return ( riscv_valid_base_register_p ( info -> reg , mode , strict_p ) && riscv_valid_offset_p ( info -> offset


<s> } unsigned Start , End ; if ( TII -> isRxSBGMask ( Value , BitsPerElement , Start , End ) ) { Start -= <NUM_LIT> - BitsPerElement ; End -= <NUM_LIT> - BitsPerElement ; MVT VecVT = <STR_LIT> ( <STR_LIT> ( BitsPerElement ) , <STR_LIT> / BitsPerElement ) ; SDValue Op = DAG . getNode ( <STR_LIT> , DL , VecVT , DAG . getConstant ( Start , DL , <STR_LIT> ) , DAG . getConstant ( End , DL , <STR_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , DL , VT , Op


<s> const <ISA_LIT>InstrInfo * getInstrInfo ( ) const override { return &


<s> void emitARM64WinCFISaveFReg ( unsigned Reg , int Offset ) override { OS << <STR_LIT> << Reg << <STR_LIT> << Offset


<s> if ( delta != <NUM_LIT> ) { if ( delta > maxoff || delta < - maxoff ) { fprintf ( file , <STR_LIT> , reg0 , ( long ) delta ) ; fprintf ( file , <STR_LIT> , thiz , thiz , reg0 ) ; } else fprintf ( file , <STR_LIT> , ( delta > <NUM_LIT> ? <STR_LIT> : <STR_LIT> ) , thiz , thiz , ( long ) ( delta > <NUM_LIT> ? delta : - delta ) ) ; } if ( vcall_offset != <NUM_LIT> ) { fprintf ( file , <STR_LIT> , reg0 , thiz ) ; if ( vcall_offset > maxoff || vcall_offset < - maxoff ) { fprintf ( file , <STR_LIT> , reg1 , ( long ) vcall_offset ) ; fprintf ( file , <STR_LIT> , reg0 , reg0 , reg1 ) ; } else fprintf ( file , <STR_LIT> , ( vcall_offset > <NUM_LIT> ? <STR_LIT> : <STR_LIT> ) , reg0 , reg0 , ( long ) ( vcall_offset > <NUM_LIT> ? vcall_offset : - vcall_offset ) ) ; fprintf ( file , <STR_LIT> , reg0 , reg0 ) ; fprintf ( file , <STR_LIT> , thiz , thiz , reg0 ) ; } if ( CSKY_TARGET_ARCH ( CK801 ) ) { if ( vcall_offset > maxoff || vcall_offset < - maxoff ) { fprintf ( file , <STR_LIT> ) ; fprintf ( file , <STR_LIT> ) ; fprintf ( file , <STR_LIT>


<s> unsigned Zero = MRI . createVirtualRegister ( PtrRC ) ; unsigned Drop = MRI . createVirtualRegister ( PtrRC ) ; const auto * TII = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getInstrInfo ( ) ; BuildMI ( MBB , InsertAddr , DL , TII -> get ( <STR_LIT> ) , Zero ) . addImm ( <NUM_LIT> ) ; auto * MMO = new MachineMemOperand ( MachinePointerInfo ( MF . getPSVManager ( ) . getExternalSymbolCallEntry ( ES ) ) , MachineMemOperand :: MOStore , <NUM_LIT> , <NUM_LIT> ) ; BuildMI ( MBB , InsertStore , DL , TII -> get ( <STR_LIT> ) , Drop ) . addExternalSymbol ( SPSymbol ) . addReg ( Zero )

. addImm ( <NUM_LIT> ) . addReg ( SrcReg ) . addMemOperand ( MMO ) ;


<s> void or1k_expand_compare ( rtx * operands ) { rtx sr_f = gen_rtx_REG ( BImode , SR_F_REGNUM ) ; if ( ! TARGET_SFIMM ) XEXP ( operands [ <NUM_LIT> ] , <NUM_LIT> ) = force_reg ( SImode , XEXP ( operands [ <NUM_LIT> ] , <NUM_LIT> ) ) ; PUT_MODE ( operands [ <NUM_LIT> ]


<s> switch ( getFLAGS ( insn ) ) { default : return UNSUPPORTED ; case <NUM_LIT> :


<s> unsigned Reg = MRI . createVirtualRegister ( & <STR_LIT> ) ; MachineInstrBuilder ( * MI . getParent ( ) -> getParent ( ) , MI ) . addReg ( Reg , RegState :: ImplicitDefine | RegState :: Dead ) ; LLVM_DEBUG ( MI . dump


<s> for ( i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) if ( cfun_gpr_save_slot ( i ) != SAVE_SLOT_NONE ) return false ; if ( ! TARGET_64BIT && ( cfun_fpr_save_p ( FPR4_REGNUM ) || cfun_fpr_save_p ( FPR6_REGNUM ) )


<s> explicit <ISA_LIT>AsmPrinter ( TargetMachine & TM , MCStreamer & Streamer ) : AsmPrinter ( TM , Streamer ) , MCP ( nullptr ) , InConstantPool ( false ) , MCInstLowering ( * this ) { Subtarget = & TM . getSubtarget < <ISA_LIT>Subtarget >


<s> if ( ! compute_int_layout ( bitpos , data , & nregs ) ) return ; if ( intoffset % BITS_PER_WORD != <NUM_LIT> ) mode = smallest_mode_for_size ( BITS_PER_WORD - intoffset % BITS_PER_WORD , MODE_INT ) ; else mode = word_mode ; const int this_slotno = data -> slotno + intoffset / BITS_PER_WORD ; unsigned int regno = data -> regbase + this_slotno ; intoffset /=


<s> if ( saved_regs & ( <NUM_LIT> << regno ) ) { if ( TARGET_H8300S ) { if ( ( TARGET_H8300SX || ( regno & <NUM_LIT> ) == <NUM_LIT> ) && ( ( saved_regs << <NUM_LIT> >> regno ) & <NUM_LIT> ) == <NUM_LIT> ) n_regs = <NUM_LIT> ; else if ( ( TARGET_H8300SX || ( regno & <NUM_LIT> ) == <NUM_LIT> ) && ( ( saved_regs << <NUM_LIT> >> regno ) & <NUM_LIT> ) == <NUM_LIT> ) n_regs = <NUM_LIT> ; else if ( ( TARGET_H8300SX || ( regno & <NUM_LIT> ) == <NUM_LIT> ) && ( ( saved_regs << <NUM_LIT> >> regno ) & <NUM_LIT> ) == <NUM_LIT> ) n_regs = <NUM_LIT> ; } if ( TARGET_H8300SX && ! sibcall_p && ! frame_pointer_needed && frame_size == <NUM_LIT> && ( saved_regs & ( ( <NUM_LIT> << ( regno - n_regs + <NUM_LIT> ) ) - <NUM_LIT> ) ) == <NUM_LIT> ) returned_p = true ; h8300_push_pop ( regno - n_regs + <NUM_LIT> , n_regs , true , returned_p ) ; } } if ( frame_pointer_needed ) { if ( TARGET_H8300SX && ! sibcall_p


<s> if ( ! Op . getImm ( ) -> evaluateAsAbsolute ( Res ) || Res > <NUM_LIT> ) { Error ( Op . getStartLoc ( ) , <STR_LIT> ) ; return


<s> Register ExtReg = extendRegister ( ValVReg , VA ) ; MIRBuilder . buildCopy ( PhysReg , ExtReg ) ; MIB . addUse ( PhysReg , RegState


<s> MF -> insert ( It , loopMBB ) ; MF -> insert ( It , exitMBB ) ; exitMBB -> splice ( exitMBB -> begin ( ) , BB , llvm :: next ( MachineBasicBlock :: iterator ( MI ) ) , BB -> end ( ) ) ; exitMBB -> transferSuccessorsAndUpdatePHIs ( BB ) ; MachineRegisterInfo & RegInfo = MF -> getRegInfo ( ) ; unsigned scratch = RegInfo . createVirtualRegister ( <STR_LIT> ) ; unsigned scratch2 = ( ! BinOpcode ) ? incr : RegInfo . createVirtualRegister ( <STR_LIT> ) ; BB -> addSuccessor ( loopMBB ) ; BB = loopMBB ; AddDefaultPred ( BuildMI ( BB , dl , TII -> get ( ldrOpc ) , dest ) . addReg ( ptr ) ) ; if ( BinOpcode ) { if ( BinOpcode == <STR_LIT> || BinOpcode == <STR_LIT> ) AddDefaultPred ( BuildMI ( BB , dl , TII -> get ( BinOpcode ) , scratch2 ) . addReg ( incr ) . addReg ( dest ) ) . addReg ( <NUM_LIT> ) ; else AddDefaultPred ( BuildMI ( BB , dl , TII -> get ( BinOpcode ) , scratch2 ) . addReg ( dest ) . addReg ( incr ) ) . addReg ( <NUM_LIT> ) ; } AddDefaultPred ( BuildMI ( BB , dl , TII -> get ( strOpc ) , scratch ) . addReg ( scratch2 )


<s> return __builtin_neon_vbfcvtsf ( __a )


<s> initializeSubtargetDependencies ( StringRef CPU , Triple TT , StringRef FS , const <ISA_LIT>TargetMachine & TM ) { std :: string CPUName = select<ISA_LIT>CPU ( TT , CPU ) ; IsM68000 = true ; InstrItins = getInstrItineraryForCPU ( CPUName ) ; stackAlignment = <NUM_LIT> ; return *


<s> uint32_t N = L . IsSpecial ? sizeof L . Properties : L . Size * sizeof ( const Constant * ) ; memcpy ( Values , L . Values , N ) ; Kind = L .


<s> if ( TailCallReturnAddrDelta < <NUM_LIT> ) { BuildStackAdjustment ( MBB , MBBI , DL , TailCallReturnAddrDelta , false ) . setMIFlag ( MachineInstr :: FrameSetup ) ; } uint64_t NumBytes = <NUM_LIT> ; int stackGrowth = - SlotSize ; if ( HasFP ) { uint64_t FrameSize = StackSize - SlotSize ; if ( MMFI -> getRestoreBasePointer ( ) ) FrameSize += SlotSize ; NumBytes = FrameSize - MMFI -> getCalleeSavedFrameSize ( ) ; if ( TRI -> needsStackRealignment ( MF ) ) NumBytes = alignTo ( NumBytes , MaxAlign ) ; MFI . setOffsetAdjustment ( - NumBytes ) ; BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) ) . addReg ( MachineFramePtr , RegState :: Kill ) . setMIFlag ( MachineInstr :: FrameSetup ) ; if ( NeedsDwarfCFI ) { assert ( StackSize ) ; BuildCFI ( MBB , MBBI , DL , MCCFIInstruction :: createDefCfaOffset ( nullptr , <NUM_LIT> * stackGrowth ) ) ; int DwarfFramePtr = TRI -> getDwarfRegNum ( MachineFramePtr , true ) ; assert ( DwarfFramePtr > <NUM_LIT> ) ; BuildCFI ( MBB , MBBI , DL , MCCFIInstruction :: createOffset ( nullptr , DwarfFramePtr , <NUM_LIT> * stackGrowth ) ) ; } BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) , FramePtr ) . addReg ( StackPtr ) . setMIFlag ( MachineInstr :: FrameSetup ) ; if ( NeedsDwarfCFI ) { unsigned DwarfFramePtr = TRI -> getDwarfRegNum ( MachineFramePtr , true ) ; BuildCFI ( MBB , MBBI , DL , MCCFIInstruction :: createDefCfaRegister ( nullptr , DwarfFramePtr ) ) ; } for ( MachineBasicBlock & EveryMBB : MF ) EveryMBB . addLiveIn ( MachineFramePtr ) ; } else { NumBytes = StackSize - MMFI -> getCalleeSavedFrameSize ( ) ; } bool PushedRegs = false ; int StackOffset = <NUM_LIT> * stackGrowth ; while ( MBBI != MBB . end ( ) && MBBI -> getFlag ( MachineInstr :: FrameSetup

) && MBBI -> getOpcode ( ) == <STR_LIT> ) {


<s> return isVectorLaneType ( * getLaneType ( DataType )


<s> case LibFunc_fmaxf : case LibFunc_fmaxl : Opcode = <STR_LIT> ; break ; } } if ( Opcode ) { EVT EVTy = TLI -> getValueType ( DL , CI -> getArgOperand ( <NUM_LIT> ) -> getType ( ) , true ) ; if ( EVTy == <STR_LIT> ) return true ; if ( TLI -> isOperationLegalOrCustom ( Opcode , EVTy ) ) continue ; else if ( EVTy . isVector ( ) && TLI -> isOperationLegalOrCustom ( Opcode , EVTy . getScalarType ( ) ) ) continue ; return true ; } } return true ; } else if ( isa < BinaryOperator > ( J ) && J -> getType ( ) -> getScalarType ( ) -> is<ISA_LIT>_FP128Ty ( ) ) { return true ; } else if ( isa < UIToFPInst > ( J ) || isa < SIToFPInst > ( J ) || isa < FPToUIInst > ( J ) || isa < FPToSIInst > ( J ) ) { CastInst * CI = cast < CastInst > ( J ) ; if ( CI -> getSrcTy ( ) -> getScalarType ( ) -> is<ISA_LIT>_FP128Ty ( ) || CI -> getDestTy ( ) -> getScalarType ( ) -> is<ISA_LIT>_FP128Ty ( ) || isLargeIntegerTy ( ! TM . is<ISA_LIT>64 ( ) , CI -> getSrcTy ( ) -> getScalarType ( ) ) || isLargeIntegerTy ( ! TM . is<ISA_LIT>64 ( ) , CI -> getDestTy ( ) -> getScalarType ( ) ) ) return true ; } else if ( isLargeIntegerTy ( ! TM . is<ISA_LIT>64 ( ) , J -> getType ( ) -> getScalarType ( ) ) && ( J -> getOpcode ( ) == Instruction :: UDiv || J -> getOpcode ( ) == Instruction :: SDiv || J -> getOpcode ( ) == Instruction :: URem || J -> getOpcode ( ) == Instruction :: SRem ) ) { return true ; } else if ( ! TM . is<ISA_LIT>64 ( ) && isLargeIntegerTy ( false , J -> getType ( ) -> getScalarType ( ) ) && ( J -> getOpcode ( ) == Instruction :: Shl || J -> getOpcode ( ) == Instruction :: AShr || J -> getOpcode ( ) == Instruction :: LShr ) ) { return true ; } else if ( isa < IndirectBrInst > ( J ) || isa < InvokeInst > ( J ) ) { return true ; } else if ( SwitchInst * SI = dyn_cast < SwitchInst > ( J ) ) { if ( SI -> getNumCases ( ) + <NUM_LIT> >= ( unsigned ) TLI -> getMinimumJumpTableEntries ( ) ) return true ; } if ( J -> getOpcode ( ) == Instruction :: FRem ) return true ; if ( ST -> useSoftFloat ( ) ) { switch ( J -> getOpcode ( ) ) { case Instruction :: FAdd : case Instruction :: FSub : case Instruction :: FMul : case Instruction ::


<s> unsigned getPrefLoopLogAlignment ( ) const


<s> int CURegNum = getCompactUnwindRegNum ( Reg ) ; if ( CURegNum == - <NUM_LIT> ) return ~ <NUM_LIT> ; RegEnc |= ( CURegNum & <NUM_LIT> ) << ( Idx ++ * <NUM_LIT> ) ; } assert ( ( RegEnc & <NUM_LIT> ) == RegEnc && <STR_LIT> ) ; return


<s> MachineInstr * <ISA_LIT>InstructionSelector :: emitADDS ( Register Dst , MachineOperand & LHS , MachineOperand & RHS , MachineIRBuilder & MIRBuilder ) const { const std :: array < std :: array < unsigned , <NUM_LIT> > , <NUM_LIT> > OpcTable { { { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } } } ; return emitAddSub ( OpcTable , Dst ,


<s> addPass ( new InstructionSelect ( getOptLevel ( ) ) ) ; return


<s> else Opc = ( DestVT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; } else { if ( Signed ) Opc = ( DestVT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; else Opc = ( DestVT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; } unsigned ResultReg = createResultReg ( DestVT == <STR_LIT> ? & <STR_LIT> : & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , ResultReg ) . addReg ( SrcReg ) ; updateValueMap ( I


<s> DebugLoc dl ; <ISA_LIT>FunctionInfo * AFI = MBB . getParent ( ) -> getInfo < <ISA_LIT>FunctionInfo > ( ) ; int BOpc = ! AFI -> isThumbFunction ( ) ? <STR_LIT> : ( AFI -> isThumb2Function ( ) ? <STR_LIT> : <STR_LIT> ) ; int BccOpc = ! AFI -> isThumbFunction ( ) ? <STR_LIT> : ( AFI -> isThumb2Function ( ) ? <STR_LIT> : <STR_LIT> ) ; assert ( TBB && <STR_LIT> ) ; assert ( ( Cond . size ( ) == <NUM_LIT> || Cond . size ( ) == <NUM_LIT> ) && <STR_LIT> ) ; if ( FBB == <NUM_LIT>


<s> if ( e -> src -> index == ENTRY_BLOCK_PTR_FOR_FN ( cfun ) -> index ) continue ; if ( vsetvl_insn_p ( prop . get_insn ( ) -> rtl ( ) ) && propagate_avl_across_demands_p ( prop , block_info . reaching_out ) ) continue ; if ( block_info . reaching_out . unknown_p ( ) ) continue ; else if ( block_info . reaching_out . hard_empty_p ( ) ) continue ; else if ( block_info . reaching_out . empty_p ( ) ) { enum fusion_type type = get_backward_fusion_type ( crtl -> ssa -> bb ( e -> src ) , prop ) ; if ( type == INVALID_FUSION ) continue ; block_info . reaching_out = prop ; block_info . reaching_out . set_dirty ( type ) ; if ( prop . has_avl_reg ( ) && ! vlmax_avl_p ( prop . get_avl ( ) ) ) { hash_set < set_info * > sets = get_all_sets ( prop . get_avl_source ( ) , true , true , true ) ; set_info * set = get_same_bb_set ( sets , e -> src ) ; if ( set ) block_info . reaching_out . set_avl_info ( avl_info ( prop . get_avl ( ) , set ) ) ; } block_info . local_dem = block_info . reaching_out ; block_info . probability = curr_block_info . probability ; changed_p = true ; } else if ( block_info . reaching_out . dirty_p ( ) ) { vector_insn_info new_info ; if ( block_info . reaching_out . compatible_p ( prop ) ) { if ( block_info . reaching_out . available_p ( prop ) ) continue ; new_info = block_info . reaching_out . merge ( prop , GLOBAL_MERGE ) ; new_info . set_dirty ( block_info . reaching_out . dirty_with_killed_avl_p ( ) ) ; block_info . probability += curr_block_info . probability ; } else { if ( curr_block_info . probability > block_info . probability ) { enum fusion_type type = get_backward_fusion_type ( crtl -> ssa -> bb ( e -> src ) , prop ) ; if ( type == INVALID_FUSION ) continue ; new_info = prop ; new_info . set_dirty ( type ) ; block_info . probability = curr_block_info . probability ; } else continue ; } if ( propagate_avl_across_demands_p ( prop , block_info . reaching_out ) ) { rtx reg = new_info . get_avl_reg_rtx ( ) ; if ( find_reg_killed_by ( crtl -> ssa -> bb ( e -> src ) , reg ) ) new_info . set_dirty ( true ) ; } block_info . local_dem


<s> case VK_TPREL_G1_NC : return <STR_LIT> ; case VK_TPREL_G0 : return <STR_LIT> ; case VK_TPREL_G0_NC : return <STR_LIT> ; case VK_TPREL_HI12 : return <STR_LIT> ; case VK_TPREL_LO12 : return <STR_LIT> ; case VK_TPREL_LO12_NC : return <STR_LIT> ; case VK_TLSDESC_LO12 : return <STR_LIT> ; case VK_ABS_PAGE : return <STR_LIT> ; case VK_ABS_PAGE_NC : return <STR_LIT> ; case VK_GOT : return <STR_LIT> ; case VK_GOT_PAGE : return <STR_LIT> ; case VK_GOT_LO12 : return <STR_LIT> ; case VK_GOTTPREL : return <STR_LIT> ; case VK_GOTTPREL_PAGE : return <STR_LIT> ; case VK_GOTTPREL_LO12_NC : return <STR_LIT> ; case VK_GOTTPREL_G1 : return


<s> } break ; case TYPE_DIV : switch ( get_attr_size ( insn ) ) { case SIZE_32 : cost = COSTS_N_INSNS ( n - <NUM_LIT> ) + rs6000_cost -> divsi ; break ; case SIZE_64 : cost = COSTS_N_INSNS ( n - <NUM_LIT> ) + rs6000_cost -> divdi ; break ; default : gcc_unreachable ( ) ; } break ; case TYPE_FP : cost = n * rs6000_cost -> fp ; break ; case TYPE_DMUL : cost = n * rs6000_cost -> dmul ; break ; case TYPE_SDIV : cost = n * rs6000_cost -> sdiv ; break ; case TYPE_DDIV : cost = n * rs6000_cost -> ddiv ; break ; case TYPE_SYNC : case TYPE_LOAD_L : case TYPE_MFCR : case


<s> StringRef FPU = getParser ( ) . parseStringToEndOfStatement ( ) . trim ( ) ; unsigned ID = StringSwitch < unsigned > ( FPU ) . Default ( <STR_LIT> ) ; if ( ID == <STR_LIT> ) { Error ( L , <STR_LIT> ) ; return


<s> case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; } } else if ( Is == IS_SGPR ) { switch ( RegWidth ) { default : return - <NUM_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; } } else if ( Is == IS_AGPR ) { switch ( RegWidth ) { default : return - <NUM_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT>


<s> SDLoc DL ( N ) ; if ( VT != <STR_LIT> && VT != <STR_LIT> && VT != <STR_LIT> ) return SDValue ( ) ; if ( N0 . getOpcode ( ) == <STR_LIT> && <STR_LIT> ( N0 . getOperand ( <NUM_LIT> ) . getNode ( ) ) ) return DAG . getNode ( <STR_LIT> , DL , VT , N0 . getOperand (


<s> default : assert ( <NUM_LIT> && <STR_LIT> ) ; case CallingConv :: C : case CallingConv :: Fast : return LowerCCCArguments ( Op


<s> SDLoc dl ( Op ) ; assert ( VT . isVector ( ) && InVT . isVector ( ) && <STR_LIT> ) ; assert ( VT . getVectorNumElements ( ) == VT . getVectorNumElements ( ) && <STR_LIT> ) ; assert ( ( VT . getVectorElementType ( ) == <STR_LIT> || VT . getVectorElementType ( ) == <STR_LIT> || VT . getVectorElementType ( ) == <STR_LIT> ) && <STR_LIT> ) ; assert ( ( InVT . getVectorElementType ( ) == <STR_LIT> || InVT . getVectorElementType ( ) == <STR_LIT> || InVT . getVectorElementType ( ) == <STR_LIT> ) && <STR_LIT> ) ; if ( InVT == <STR_LIT> ) { if ( ! ExperimentalVectorWideningLegalization || VT != <STR_LIT> ) return SDValue ( ) ; In = DAG . getNode ( <STR_LIT> , SDLoc ( Op ) , <STR_LIT> , In , DAG . getUNDEF ( <STR_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , dl , VT , In ) ; } if ( Subtarget . hasInt256 ( ) ) return Op ; MVT HalfVT = <STR_LIT> ( VT . getVectorElementType ( ) , VT . getVectorNumElements ( ) / <NUM_LIT> ) ; SDValue OpLo = DAG . getNode ( <STR_LIT> , dl , HalfVT


<s> unsigned TempGPR32 = MRI . createVirtualRegister ( & <STR_LIT> ) ; DebugLoc DL = MI . getDebugLoc ( ) ; BuildMI ( * MBB , II , DL , TII -> get ( <STR_LIT> ) , TempGPR32 ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( BRIG_TYPE_U32 ) . addImm ( BRIG_TYPE_B1 ) . addOperand ( MI . getOperand ( <NUM_LIT> ) ) ; MI . setDesc ( TII -> get ( <STR_LIT> ) ) ; MI . getOperand ( <NUM_LIT> ) . setReg ( TempGPR32 ) ; MI . getOperand ( <NUM_LIT> ) . setIsKill ( ) ; MachineOperand * TypeOp = TII -> getNamedOperand ( MI , <STR_LIT> :: TypeLength ) ; TypeOp -> setImm


<s> llvm_unreachable ( <STR_LIT> ) ; return


<s> static rtx sparc_function_incoming_arg ( cumulative_args_t cum , const function_arg_info & arg ) { return sparc_function_arg_1 ( cum , arg , true


<s> SDValue Lo = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , InChain , DAG . getNode ( <STR_LIT>


<s> enum aarch64_parse_opt_result res = aarch64_parse_branch_protection ( const_str , & str ) ; if ( res == AARCH64_PARSE_INVALID_ARG ) error ( <STR_LIT> , str ) ; else if ( res == AARCH64_PARSE_MISSING_ARG ) error ( <STR_LIT> ) ; free (


<s> if ( const MCBinaryExpr * BinOp = dyn_cast < MCBinaryExpr > ( Expr ) ) return IsFunctionExpr ( BinOp -> getLHS ( ) ) != IsFunctionExpr ( BinOp -> getRHS ( ) ) ; if ( const MCUnaryExpr * UnOp = dyn_cast < MCUnaryExpr > ( Expr ) ) return IsFunctionExpr ( UnOp -> getSubExpr ( ) ) ; return


<s> MachineFunction * <ISA_LIT>SPMark :: getCallTargetMF ( const MachineInstr * MI ) const { auto F = getCallTarget ( MI ) ; MachineFunction * MF


<s> if ( TM . getRelocationModel ( ) == Reloc :: PIC_ ) { MF -> getInfo < <ISA_LIT>FunctionInfo > ( ) -> setEmitNOAT ( ) ; uint64_t Address = <NUM_LIT> ; for ( I = MBBInfos . begin ( ) ; I != E ; Address += I -> Size , ++ I ) I -> Address = Address ; } for ( I = MBBInfos . begin ( ) ; I != E ; ++ I ) if ( I -> HasLongBranch ) expandToLongBranch ( * I ) ; MF -> RenumberBlocks ( ) ; return true


<s> extract = high_p ? gen_vec_extract_hi_v16hi : gen_vec_extract_lo_v16hi ; break ; case V16SImode : if ( unsigned_p ) unpack = gen_avx512f_zero_extendv8siv8di2 ; else unpack = gen_avx512f_sign_extendv8siv8di2 ; halfmode = V8SImode ; extract = high_p ? gen_vec_extract_hi_v16si : gen_vec_extract_lo_v16si ; break ; case V8SImode : if ( unsigned_p ) unpack = gen_avx2_zero_extendv4siv4di2 ; else unpack = gen_avx2_sign_extendv4siv4di2 ; halfmode = V4SImode ; extract = high_p ? gen_vec_extract_hi_v8si : gen_vec_extract_lo_v8si ; break ; case V16QImode : if ( unsigned_p ) unpack = gen_sse4_1_zero_extendv8qiv8hi2 ; else unpack = gen_sse4_1_sign_extendv8qiv8hi2 ; break ; case V8HImode : if ( unsigned_p ) unpack = gen_sse4_1_zero_extendv4hiv4si2 ; else unpack = gen_sse4_1_sign_extendv4hiv4si2 ; break ; case V4SImode : if ( unsigned_p ) unpack = gen_sse4_1_zero_extendv2siv2di2 ; else unpack = gen_sse4_1_sign_extendv2siv2di2 ; break ; default : gcc_unreachable ( ) ; } if ( GET_MODE_SIZE ( imode ) >= <NUM_LIT> ) { tmp = gen_reg_rtx ( halfmode ) ; emit_insn ( extract ( tmp , src ) ) ; } else if ( high_p ) { tmp = gen_reg_rtx ( V1TImode ) ; emit_insn ( gen_sse2_lshrv1ti3 ( tmp , gen_lowpart ( V1TImode , src ) , GEN_INT ( <NUM_LIT> ) ) ) ; tmp = gen_lowpart ( imode , tmp ) ; } else tmp = src ; emit_insn ( unpack ( dest , tmp ) ) ; } else { rtx ( * unpack ) ( rtx , rtx , rtx ) ; switch ( imode ) { case V16QImode : if ( high_p )


<s> void BTFDebug :: visitDerivedType ( const DIDerivedType * DTy ) { unsigned Tag = DTy -> getTag ( ) ; if ( Tag == dwarf :: DW_TAG_pointer_type || Tag == dwarf :: DW_TAG_typedef || Tag == dwarf :: DW_TAG_const_type || Tag == dwarf :: DW_TAG_volatile_type || Tag == dwarf :: DW_TAG_restrict_type ) { auto TypeEntry = llvm :: make_unique < BTFTypeDerived > ( DTy , Tag ) ; addType ( std :: move ( TypeEntry ) , DTy ) ; } else if ( Tag != dwarf :: DW_TAG_member ) { return ; } visitTypeEntry ( DTy -> getBaseType ( )


<s> Register Lo = MRI . createVirtualRegister ( & <STR_LIT> ) ; Register Hi = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * BB , I , DL , TII -> get ( <STR_LIT> ) ) . addDef ( Bitcast ) . addUse ( StoreVal ) ; BuildMI ( * BB , I , DL , TII -> get ( <STR_LIT> ) ) . addDef ( Lo ) . addUse ( Bitcast ) . addImm ( <NUM_LIT> ) ; BuildMI ( * BB , I , DL , TII -> get ( <STR_LIT> ) ) . addDef ( Hi ) . addUse ( Bitcast ) . addImm ( <NUM_LIT> ) ; BuildMI ( * BB , I , DL , TII -> get ( <STR_LIT> ) ) . addUse ( Lo ) . addUse ( Address ) . addImm ( Imm + ( IsLittle ? <NUM_LIT> : <NUM_LIT> ) ) ; BuildMI ( * BB , I , DL , TII -> get ( <STR_LIT> ) ) . addUse ( Lo ) . addUse ( Address ) . addImm ( Imm + ( IsLittle ? <NUM_LIT> : <NUM_LIT> ) ) ; BuildMI ( * BB , I , DL , TII -> get ( <STR_LIT> ) ) . addUse ( Hi ) . addUse ( Address ) . addImm ( Imm + ( IsLittle ? <NUM_LIT> : <NUM_LIT> ) ) ; BuildMI ( * BB , I , DL , TII -> get ( <STR_LIT> ) ) . addUse ( Hi ) . addUse ( Address ) . addImm ( Imm + ( IsLittle ? <NUM_LIT> : <NUM_LIT> ) ) ; } MI . eraseFromParent ( ) ; return


<s> assert ( Flags . getValueType ( ) == <STR_LIT> && <STR_LIT> ) ; for ( SDNode :: use_iterator UI = Flags -> use_begin ( ) , UE = Flags -> use_end ( ) ; UI != UE ; ++ UI ) { SDNode * User = * UI


<s> static bool mmix_pass_by_reference ( const CUMULATIVE_ARGS * argsp , enum machine_mode mode , tree type , bool named ATTRIBUTE_UNUSED ) { if ( targetm . calls . must_pass_in_stack ( mode , type ) ) return true ; if ( MMIX_FUNCTION_ARG_SIZE ( mode , type ) > <NUM_LIT> && ! TARGET_LIBFUNC && ( ! argsp || !


<s> emitFrameDirective ( ) ; if ( OutStreamer . hasRawTextSupport ( ) ) { SmallString < <NUM_LIT> > Str ; raw_svector_ostream OS ( Str ) ; printSavedRegsBitmask ( OS ) ; OutStreamer . EmitRawText ( OS . str ( ) ) ; OutStreamer . EmitRawText ( StringRef ( <STR_LIT> ) ) ; OutStreamer . EmitRawText ( StringRef ( <STR_LIT>


<s> static int mips_address_cost ( rtx addr , machine_mode mode , addr_space_t as

ATTRIBUTE_UNUSED , bool speed ATTRIBUTE_UNUSED ) {


<s> ParamStr << DAG . getMachineFunction ( ) . getName ( ) << <STR_LIT> << idx ; ParamStr . flush ( ) ; std :: string * SavedStr = nvTM -> getManagedStrPool ( ) -> getManagedString ( ParamSym . c_str ( ) ) ; return DAG . getTargetExternalSymbol ( SavedStr -> c_str ( ) ,


<s> bool isFPImm ( ) const { return Kind ==


<s> virtual bool isVirtualSection ( ) const { return false


<s> auto PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; SDValue Callee = DAG . getExternalSymbol ( LibCall , PtrVT ) ; Type * RetTy = Type :: getInt32Ty ( * DAG . getContext ( ) ) ; ArgListTy Args ; SDValue Chain = DAG . getEntryNode ( ) ; Chain = LowerF128_LibCallArg ( Chain , Args , LHS , DL , DAG ) ; Chain = LowerF128_LibCallArg ( Chain , Args , RHS , DL , DAG ) ; TargetLowering :: CallLoweringInfo CLI ( DAG ) ; CLI . setDebugLoc ( DL ) . setChain ( Chain ) . setCallee ( CallingConv :: C , RetTy , Callee , std :: move ( Args ) , <NUM_LIT> ) ; std :: pair < SDValue , SDValue > CallInfo = LowerCallTo ( CLI ) ; SDValue Result = CallInfo . first ; switch ( <ISA_LIT>CC ) { default : { SDValue RHS = DAG . getTargetConstant ( <NUM_LIT> , DL , Result . getValueType ( ) ) ; <ISA_LIT>CC = <STR_LIT> ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Result , RHS ) ; } case <STR_LIT> : { SDValue Mask = DAG . getTargetConstant ( <NUM_LIT> , DL , Result . getValueType ( ) ) ; Result = DAG . getNode ( <STR_LIT> , DL , Result . getValueType ( ) , Result , Mask ) ; SDValue RHS = DAG . getTargetConstant ( <NUM_LIT> , DL , Result . getValueType ( ) ) ; <ISA_LIT>CC = <STR_LIT> ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Result , RHS ) ; } case <STR_LIT> : { SDValue RHS = DAG . getTargetConstant ( <NUM_LIT> , DL , Result . getValueType ( ) ) ; <ISA_LIT>CC = <STR_LIT> ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Result , RHS ) ; } case <STR_LIT> : { SDValue RHS = DAG . getTargetConstant ( <NUM_LIT> , DL , Result . getValueType ( ) ) ; <ISA_LIT>CC = <STR_LIT> ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Result , RHS ) ; } case <STR_LIT> : { SDValue RHS = DAG . getTargetConstant ( <NUM_LIT> , DL , Result . getValueType ( ) ) ; <ISA_LIT>CC = <STR_LIT> ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Result , RHS ) ; } case <STR_LIT> : { SDValue RHS = DAG . getTargetConstant ( <NUM_LIT> , DL , Result . getValueType ( ) ) ; <ISA_LIT>CC = <STR_LIT> ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Result , RHS ) ; } case <STR_LIT> : { SDValue RHS = DAG . getTargetConstant ( <NUM_LIT> , DL , Result . getValueType ( ) ) ; <ISA_LIT>CC = <STR_LIT>


<s> DebugLoc dl = Op . getDebugLoc ( ) ; unsigned Reg = <NUM_LIT> ; unsigned size = <NUM_LIT> ; switch ( T . getSimpleVT ( ) . SimpleTy ) { default : assert ( false && <STR_LIT> ) ; case <STR_LIT> : Reg = <STR_LIT> ; size = <NUM_LIT> ; break ; case <STR_LIT> : Reg = <STR_LIT> ; size = <NUM_LIT> ; break ; case <STR_LIT> : Reg = <STR_LIT> ; size = <NUM_LIT> ; break ; case <STR_LIT> : assert ( Subtarget -> is64Bit ( ) && <STR_LIT> ) ; Reg = <STR_LIT> ; size = <NUM_LIT> ; break ; } SDValue cpIn = DAG . getCopyToReg ( Op . getOperand ( <NUM_LIT> ) , dl , Reg , Op . getOperand ( <NUM_LIT> ) , SDValue ( ) ) ; SDValue Ops [ ] = { cpIn . getValue ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , DAG . getTargetConstant ( size , <STR_LIT> ) , cpIn . getValue ( <NUM_LIT> ) } ; SDVTList Tys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SDValue Result = DAG . getNode ( <STR_LIT> , dl , Tys , Ops , <NUM_LIT> ) ; SDValue cpOut = DAG . getCopyFromReg ( Result . getValue ( <NUM_LIT> ) , dl , Reg , T , Result


<s> static bool getIndexedAddressParts ( SDNode * Ptr , EVT VT , bool isSEXTLoad , SDValue & Base , SDValue & Offset , bool & isInc , SelectionDAG & DAG ) { if ( Ptr -> getOpcode ( ) != <STR_LIT> ) return false ; auto & HST = static_cast < const <ISA_LIT>Subtarget & > ( DAG . getSubtarget ( ) ) ; bool UseHVX = HST . useHVXOps (


<s> MCSuperRegIterator SRI ( Reg , TRI ) ; assert ( SRI . isValid ( ) && <STR_LIT> ) ; unsigned SuperReg = * SRI ; ++


<s> Inst . addOperand ( MCOperand :: createImm ( MCE -> getValue (


<s> unsigned CmpOp = Size == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; MRI . constrainRegClass ( dest , TRCsp ) ; BuildMI ( BB , dl , TII -> get ( CmpOp ) ) . addReg ( dest ) . addReg ( oldval ) . addImm ( <NUM_LIT> ) ; BuildMI ( BB , dl , TII -> get ( <STR_LIT> ) ) . addImm ( <STR_LIT> ) . addMBB ( exitMBB ) ; BB -> addSuccessor ( loop2MBB ) ; BB -> addSuccessor ( exitMBB ) ; BB = loop2MBB ; unsigned stxr_status = MRI . createVirtualRegister ( & <STR_LIT> ) ; MRI . constrainRegClass ( stxr_status , & <STR_LIT> ) ; BuildMI ( BB , dl , TII -> get ( strOpc ) , stxr_status ) . addReg ( newval ) . addReg ( ptr ) ; BuildMI ( BB , dl , TII -> get ( <STR_LIT> ) ) . addReg ( stxr_status ) . addImm ( <NUM_LIT> ) ; BuildMI ( BB , dl , TII -> get ( <STR_LIT> ) ) . addImm ( <STR_LIT> ) . addMBB ( loop1MBB ) ; BB -> addSuccessor


<s> break ; } SDValue Test ( DAG . getMachineNode ( Opc , DL , <STR_LIT> , Arg ) , <NUM_LIT> ) ; SDValue FNSTSW = SDValue ( DAG . getMachineNode ( <STR_LIT> , DL , <STR_LIT> , Test ) , <NUM_LIT> ) ; SDValue Extract = DAG . getTargetExtractSubreg ( <STR_LIT> , DL , <STR_LIT> , FNSTSW ) ; Extract = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Extract , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; return DAG . getSetCC ( DL , ResultVT , Extract , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) , <STR_LIT>


<s> if ( TBB && TBB != MBB ) { assert ( ( FBB == nullptr || FBB == MBB ) && <STR_LIT> ) ; assert ( Cond . size ( ) == <NUM_LIT> && Cond [ <NUM_LIT> ] . isReg ( ) && <STR_LIT> ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; auto * RangeCheck = MRI . getVRegDef ( Cond [ <NUM_LIT> ] . getReg ( ) ) ; assert ( RangeCheck != nullptr ) ; if ( RangeCheck -> getOpcode ( ) != <STR_LIT> ) return nullptr ; MI . RemoveOperand ( MI . getNumExplicitOperands ( ) - <NUM_LIT> ) ; MI . addOperand ( MF , MachineOperand :: CreateMBB ( TBB ) ) ; } TII . removeBranch ( * HeaderMBB ,


<s> pcmpeqh_s ( int16x4_t s , int16x4_t t ) { return __builtin_loongson_pcmpeqh_s ( s ,


<s> assert ( ( ( ( ( intptr_t ) Fn - JCE . getCurrentPCValue ( ) - <NUM_LIT> ) << <NUM_LIT> ) >> <NUM_LIT> ) == ( ( intptr_t ) Fn - JCE . getCurrentPCValue ( ) - <NUM_LIT> ) && <STR_LIT> ) ; JCE . emitWordLE ( ( intptr_t ) Fn - JCE .


<s> if ( CONST == GET_CODE ( x ) ) x = XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) ; if ( SYMBOL_REF_P ( x ) ) return SYMBOL_REF_FLAGS ( x ) &


<s> void <ISA_LIT>InstPrinter :: printIfSet ( const MCInst * MI , unsigned OpNo , raw_ostream

& O , StringRef Asm , StringRef Default ) {


<s> <ISA_LIT>CVIResource :: SetupTUL ( & TUL , STI . getCPU


<s> unsigned NumBits2 = Ty2 -> getPrimitiveSizeInBits ( ) ; if ( NumBits1 <= NumBits2 ) return false ; return true


<s> FOR_EACH_SUBRTX ( iter , array , PATTERN ( insn ) , ALL ) { const_rtx x =


<s> OPCODE ( CLC_LOOP ) ; OPCODE ( STPCPY ) ; OPCODE ( STRCMP ) ; OPCODE ( SEARCH_STRING ) ; OPCODE ( IPM ) ; OPCODE ( SERIALIZE ) ; OPCODE ( MEMBARRIER ) ; OPCODE ( TBEGIN ) ; OPCODE ( TBEGIN_NOFLOAT ) ; OPCODE ( TEND ) ; OPCODE ( BYTE_MASK ) ; OPCODE ( ROTATE_MASK ) ; OPCODE ( REPLICATE ) ; OPCODE ( JOIN_DWORDS ) ; OPCODE ( SPLAT ) ; OPCODE ( MERGE_HIGH ) ; OPCODE ( MERGE_LOW ) ; OPCODE ( SHL_DOUBLE ) ; OPCODE ( PERMUTE_DWORDS ) ; OPCODE ( PERMUTE ) ; OPCODE ( PACK ) ; OPCODE ( PACKS_CC ) ; OPCODE ( PACKLS_CC ) ; OPCODE ( UNPACK_HIGH ) ; OPCODE ( UNPACKL_HIGH ) ; OPCODE ( UNPACK_LOW ) ; OPCODE ( UNPACKL_LOW ) ; OPCODE ( VSHL_BY_SCALAR ) ; OPCODE ( VSRL_BY_SCALAR ) ; OPCODE ( VSRA_BY_SCALAR ) ; OPCODE ( VSUM ) ; OPCODE ( VICMPE ) ; OPCODE ( VICMPH ) ; OPCODE ( VICMPHL ) ; OPCODE ( VICMPES ) ; OPCODE (


<s> MCII ( mcii ) , Ctx ( Ctx_ ) , STI ( sti ) , IsLittleEndian


<s> return new ( Ctx ) <ISA_LIT>MCExpr ( Kind


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , const std :: string & TT , const std :: string & FS , bool is64Bit ) : LLVMTargetMachine ( T , TT ) , Subtarget ( TT , FS , is64Bit ) , DataLayout ( Subtarget . getTargetDataString ( ) ) , InstrInfo ( * this ) , FrameInfo ( * this , is64Bit ) , JITInfo ( * this , is64Bit ) , TLInfo ( * this ) , InstrItins ( Subtarget . getInstrItineraryData ( ) ) , MachOWriterInfo ( * this ) { if ( getRelocationModel ( ) == Reloc :: Default ) { if ( Subtarget . isDarwin ( ) ) setRelocationModel (


<s> bool isHiImm16And ( ) { if ( ! isImm ( ) ) return false ; const MCConstantExpr * ConstExpr = dyn_cast < MCConstantExpr > ( Imm . Value ) ; if ( ConstExpr ) { int64_t Value = ConstExpr ->


<s> SDValue Ret = DAG . getCopyFromReg ( Chain , DL , <STR_LIT> , PtrVT , InFlag ) ; if ( model != TLSModel :: LocalDynamic ) return Ret ; SDValue Hi = DAG . getNode ( <STR_LIT> , DL , PtrVT , withTargetFlags ( Op , <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_LDO_HIX22 , DAG ) ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , DL , PtrVT , withTargetFlags ( Op , <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_LDO_LOX10 , DAG ) ) ; HiLo = DAG . getNode ( <STR_LIT> , DL , PtrVT , Hi , Lo ) ; return DAG . getNode ( <STR_LIT> , DL , PtrVT , Ret , HiLo , withTargetFlags ( Op , <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_LDO_ADD , DAG ) ) ; } if ( model == TLSModel :: InitialExec ) { unsigned ldTF = ( ( PtrVT == <STR_LIT> ) ? <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_IE_LDX : <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_IE_LD ) ; SDValue Base = DAG . getNode ( <STR_LIT> , DL , PtrVT ) ; MachineFrameInfo * MFI = DAG . getMachineFunction ( ) . getFrameInfo ( ) ; MFI -> setHasCalls ( true ) ; SDValue TGA = makeHiLoPair ( Op , <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_IE_HI22 , <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_IE_LO10 , DAG ) ; SDValue Ptr = DAG . getNode ( <STR_LIT> , DL , PtrVT , Base , TGA ) ; SDValue Offset = DAG . getNode ( <STR_LIT> , DL , PtrVT , Ptr , withTargetFlags ( Op , ldTF , DAG ) ) ; return DAG . getNode ( <STR_LIT> , DL , PtrVT , DAG . getRegister ( <STR_LIT> , PtrVT ) , Offset , withTargetFlags ( Op , <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_IE_ADD , DAG ) ) ; } assert ( model == TLSModel :: LocalExec ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , DL , PtrVT , withTargetFlags ( Op , <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_LE_HIX22 , DAG ) ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , DL , PtrVT , withTargetFlags ( Op , <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_LE_LOX10 , DAG ) ) ; SDValue Offset = DAG . getNode ( <STR_LIT> ,


<s> VariantKind getKind ( ) const { return Kind


<s> default : break ; case <STR_LIT> : ++ Depth ; If ( MI ) ; break ; case <STR_LIT> : Else ( MI ) ; break ; case <STR_LIT> : Break ( MI ) ; break ; case <STR_LIT> : IfBreak ( MI ) ; break ; case <STR_LIT> : ElseBreak ( MI ) ; break ; case <STR_LIT> : ++ Depth ; Loop ( MI ) ; break ; case <STR_LIT> : if ( -- Depth == <NUM_LIT> && HaveKill ) { SkipIfDead ( MI ) ; HaveKill = false ; } EndCf ( MI ) ; break ; case <STR_LIT> : if ( Depth == <NUM_LIT> ) SkipIfDead ( MI ) ; else HaveKill = true ; Kill ( MI ) ; break ; case <STR_LIT> : Branch ( MI ) ; break ; case <STR_LIT> : IndirectSrc ( MI ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : IndirectDst ( MI ) ; break ; } } } if ( NeedWQM && MFI -> getShaderType ( ) == ShaderType :: PIXEL ) { MachineBasicBlock & MBB = MF . front ( ) ; BuildMI ( MBB , MBB . getFirstNonPHI ( ) , DebugLoc ( ) , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) ; } if ( NeedFlat && MFI


<s> if ( <STR_LIT> != RB . getID ( ) ) return TargetOpcode :: G_ADD ; if ( Ty == LLT :: vector ( <NUM_LIT> , <NUM_LIT> ) ) { if ( STI . hasAVX512 ( ) && STI . hasVLX ( ) ) { return <STR_LIT> ; } else if ( STI . hasAVX ( ) ) { return <STR_LIT>


<s> unsigned CC = Cond [ <NUM_LIT> ] . getImm ( ) ; if ( IsIntegerCC ( CC ) ) BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addMBB ( TBB ) . addImm ( CC ) ; else BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addMBB ( TBB ) . addImm ( CC ) ; if ( ! FBB )


<s> if ( BYTES_BIG_ENDIAN ) return false ; for ( i = <NUM_LIT> ; i < nelt ; next ++ , i ++ ) { if ( next == <NUM_LIT> * nelt ) return false ; if ( d -> one_vector_p && ( next == nelt ) ) { if ( ( nelt == <NUM_LIT> ) && ( d -> vmode != V2DImode ) ) return false ; else next = <NUM_LIT> ; } if ( d -> perm [ i ] != next ) return false ; } location = d -> perm [ <NUM_LIT>


<s> return DAG . getBitcast ( VT , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , V2 , DAG . getConstant ( BlendMask , DL , <STR_LIT> ) ) ) ; } case <STR_LIT> : { assert ( Subtarget . hasAVX2 ( ) && <STR_LIT> ) ; SmallVector < int , <NUM_LIT> > RepeatedMask ; if ( is128BitLaneRepeatedShuffleMask ( <STR_LIT> , Mask , RepeatedMask ) ) { assert ( RepeatedMask . size ( ) == <NUM_LIT> && <STR_LIT> ) ; BlendMask = <NUM_LIT> ; for ( int i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) if ( RepeatedMask [ i ] >= <NUM_LIT> ) BlendMask |= <NUM_LIT> << i ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , V2 , DAG . getConstant ( BlendMask , DL , <STR_LIT> ) ) ; } LLVM_FALLTHROUGH ; } case <STR_LIT> : case <STR_LIT> : { assert ( ( VT . is128BitVector ( ) || Subtarget . hasAVX2 ( ) ) && <STR_LIT> ) ; if ( SDValue Masked = lowerVectorShuffleAsBitMask ( DL , VT , V1 , V2 , Mask , Zeroable , DAG ) ) return Masked ; int Scale = VT . getScalarSizeInBits ( ) / <NUM_LIT> ; MVT BlendVT = <STR_LIT> ( <STR_LIT> , VT . getSizeInBits ( ) / <NUM_LIT> ) ; SmallVector < SDValue , <NUM_LIT> > VSELECTMask ; for ( int i = <NUM_LIT> , Size = Mask . size ( ) ; i < Size ; ++ i ) for ( int j = <NUM_LIT> ; j < Scale ; ++ j ) VSELECTMask . push_back ( Mask [ i ] < <NUM_LIT> ? DAG . getUNDEF ( <STR_LIT> ) : DAG . getConstant ( Mask [ i ] < Size ? - <NUM_LIT> : <NUM_LIT> , DL , <STR_LIT> ) ) ; V1 = DAG . getBitcast ( BlendVT


<s> } } } i ++ ; } } if ( ( formula . length ( ) == <NUM_LIT> ) && ( form_inst -> getOpcode ( ) == Instruction :: ICmp ) ) { int cmp_index = - <NUM_LIT> ; int intrins_index = - <NUM_LIT> ; formula = <STR_LIT> ; ICmpInst * CI = dyn_cast < ICmpInst > ( form_inst ) ; ICmpInst :: Predicate Pred = CI -> getPredicate ( ) ; std :: string type = getPredType ( Pred ) ; if ( type . length ( ) > <NUM_LIT> ) { formula += type ; } for ( unsigned j = <NUM_LIT> ; j < CI -> getNumOperands ( ) ; j ++ ) { if ( auto * intrins = dyn_cast < IntrinsicInst > ( CI -> getOperand ( j ) ) ) { <STR_LIT> inid = intrins -> getIntrinsicID ( ) ; std :: string type = getLDLOperand ( inid ) ; if ( type . length ( ) > <NUM_LIT> ) { formula += type ; if ( auto * intrins_int = dyn_cast < llvm :: ConstantInt > ( intrins -> getOperand ( <NUM_LIT> ) ) ) { intrins_index = intrins_int ->


<s> if ( unsigned MOReg = MO . getReg ( ) ) { if ( TRI -> regsOverlap ( MOReg , Reg ) ) { if ( MO . isUse ( ) ) Ref . Use = true ; else if ( MO . isDef ( )


<s> SmallVector < unsigned , <NUM_LIT> > RetRegs ; CallingConv :: ID CC = F . getCallingConv ( ) ; if ( Ret -> getNumOperands ( ) > <NUM_LIT> ) { SmallVector < <STR_LIT> , <NUM_LIT> > Outs ; GetReturnInfo ( CC , F . getReturnType ( ) , F . getAttributes ( ) , Outs , TLI , DL ) ; SmallVector < CCValAssign , <NUM_LIT> > ValLocs ; CCState CCInfo ( CC , F . isVarArg ( ) , * FuncInfo . MF , ValLocs , I -> getContext ( ) ) ; CCInfo . AnalyzeReturn ( Outs , CCAssignFnForCall ( CC , true , F . isVarArg ( ) ) ) ; const Value * RV = Ret -> getOperand ( <NUM_LIT> ) ; unsigned Reg = getRegForValue ( RV ) ; if ( Reg == <NUM_LIT> ) return false ; if ( ValLocs . size ( ) != <NUM_LIT> ) return false ; CCValAssign & VA = ValLocs [ <NUM_LIT> ] ; if ( VA . getLocInfo ( ) != CCValAssign :: Full ) return false ; if ( ! VA . isRegLoc ( ) ) return false ; unsigned SrcReg = Reg + VA . getValNo ( ) ; EVT RVEVT = TLI . getValueType ( DL , RV -> getType ( ) ) ; if ( ! RVEVT . isSimple ( ) ) return false ; MVT RVVT = RVEVT . getSimpleVT ( ) ; MVT DestVT = VA . getValVT


<s> static DecodeStatus DecodePredicateOperand ( MCInst & Inst , unsigned Val , uint64_t Address , const void * Decoder ) { if ( Val == <NUM_LIT> ) return MCDisassembler :: Fail ; if ( Inst . getOpcode ( ) == <STR_LIT> && Val == <NUM_LIT> ) return MCDisassembler :: Fail ; Inst . addOperand ( MCOperand :: createImm ( Val ) ) ; if ( Val == <STR_LIT> ) { Inst . addOperand ( MCOperand :: createReg ( <NUM_LIT> ) ) ; } else Inst . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ; return MCDisassembler :: Success


<s> const Function * F = MF . getFunction ( ) ; emitFunctionParamList ( F


<s> else if ( VT == <STR_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; break ; case 'w' : if ( VT == <STR_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; else if ( VT == <STR_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; else if ( VT == <STR_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; else if ( VT . getSizeInBits ( ) == <NUM_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; else if ( VT == <STR_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; else if ( VT . getSizeInBits ( ) == <NUM_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; break ; } } return TargetLowering :: getRegForInlineAsmConstraint (


<s> else if ( Opc == <STR_LIT> ) Ty = Type :: getDoubleTy ( MF . getFunction ( ) -> getContext ( ) ) ; else if ( Opc == <STR_LIT> || Opc == <STR_LIT> ) Ty = VectorType :: get ( Type :: getInt32Ty ( MF . getFunction ( ) -> getContext ( ) ) , <NUM_LIT> ) ; else Ty = VectorType :: get ( Type :: getInt32Ty ( MF . getFunction ( ) -> getContext ( ) ) , <NUM_LIT> ) ; bool IsAllOnes = ( Opc == <STR_LIT> || Opc == <STR_LIT> ) ; const Constant * C = IsAllOnes ? Constant :: getAllOnesValue ( Ty ) : Constant :: getNullValue ( Ty ) ; unsigned CPI = MCP . getConstantPoolIndex ( C , Alignment ) ; MOs . push_back ( MachineOperand :: CreateReg ( PICBase , false ) ) ; MOs . push_back ( MachineOperand :: CreateImm ( <NUM_LIT> ) ) ; MOs . push_back ( MachineOperand :: CreateReg ( <NUM_LIT> , false ) ) ; MOs . push_back ( MachineOperand :: CreateCPI ( CPI , <NUM_LIT> ) ) ; MOs . push_back ( MachineOperand :: CreateReg ( <NUM_LIT> , false ) ) ; break ; } default : { if ( ( LoadMI -> getOpcode ( ) == <STR_LIT> || LoadMI -> getOpcode ( ) == <STR_LIT> ) && MF . getRegInfo ( ) . getRegClass ( LoadMI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) -> getSize ( ) > <NUM_LIT> ) return NULL ; if ( ( LoadMI -> getOpcode ( ) == <STR_LIT> || LoadMI -> getOpcode ( ) == <STR_LIT> ) && MF . getRegInfo ( ) . getRegClass ( LoadMI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) -> getSize ( ) > <NUM_LIT> ) return NULL ; for ( unsigned i = NumOps - <STR_LIT> ; i != NumOps ; ++ i ) MOs . push_back ( LoadMI -> getOperand ( i ) ) ; break ; } } return foldMemoryOperandImpl ( MF , MI , Ops [ <NUM_LIT> ]


<s> SDValue Chain = N -> getOperand ( <NUM_LIT> ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; bool is64BitVector = VT . is64BitVector ( ) ; Align = GetVLDSTAlign ( Align , NumVecs , is64BitVector ) ; unsigned OpcodeIndex ; switch ( VT . getSimpleVT ( ) . SimpleTy ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; assert ( NumVecs == <NUM_LIT> && <STR_LIT> ) ; break ; } EVT ResTy ; if ( NumVecs == <NUM_LIT> ) ResTy = VT ; else { unsigned ResTyElts = ( NumVecs == <NUM_LIT> ) ? <NUM_LIT> : NumVecs ; if ( ! is64BitVector ) ResTyElts *= <NUM_LIT> ; ResTy = EVT :: getVectorVT ( * CurDAG -> getContext ( ) , <STR_LIT> , ResTyElts ) ; } std :: vector < EVT > ResTys ; ResTys . push_back ( ResTy ) ; if ( isUpdating ) ResTys . push_back ( <STR_LIT> ) ; ResTys . push_back ( <STR_LIT> ) ; SDValue Pred = getAL ( CurDAG ) ; SDValue Reg0 = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; SDNode * VLd ; SmallVector < SDValue , <NUM_LIT> > Ops ; if ( is64BitVector || NumVecs <= <NUM_LIT> ) { unsigned Opc = ( is64BitVector ? DOpcodes [ OpcodeIndex ] : QOpcodes0 [ OpcodeIndex ] ) ; Ops . push_back ( MemAddr ) ; Ops . push_back ( Align ) ; if ( isUpdating ) { SDValue Inc = N -> getOperand ( AddrOpIdx + <NUM_LIT> ) ; if ( ( NumVecs == <NUM_LIT> || NumVecs == <NUM_LIT> ) && ! isa < ConstantSDNode > ( Inc . getNode ( ) ) ) Opc = getVLDSTRegisterUpdateOpcode ( Opc ) ; if ( ( NumVecs != <NUM_LIT> && NumVecs != <NUM_LIT> && Opc != <STR_LIT> ) || ! isa < ConstantSDNode > ( Inc . getNode ( ) ) ) Ops . push_back ( isa < ConstantSDNode > ( Inc . getNode ( ) ) ? Reg0 : Inc ) ; } Ops . push_back ( Pred ) ; Ops . push_back ( Reg0 ) ; Ops . push_back (


<s> initialize<ISA_LIT>InlinerPass ( * PassRegistry :: getPassRegistry ( ) ) ; Params = getInlineParams


<s> const uint64_t F = <ISA_LIT>MCInstrInfo :: getDesc ( MCII


<s> void setTextFragment ( RegionFragment * pFragment


<s> unsigned EncodedImm = MI -> getOperand ( OpNum ) . getImm ( ) ; unsigned EltBits ; uint64_t Val = <STR_LIT> (


<s> LoopRep -> getExitingBlocks ( ExitingMBBs ) ; if ( ExitingMBBs . size ( ) == <NUM_LIT> ) { MachineBasicBlock * DummyExitBlk = normalizeInfiniteLoopExit ( LoopRep ) ; if ( DummyExitBlk ) RetBlks . push_back ( DummyExitBlk ) ; } } for ( SmallVectorImpl < MachineBasicBlock * > :: const_iterator It = OrderedBlks . begin ( ) , E = OrderedBlks . end ( ) ; It != E ; ++ It ) { MachineBasicBlock * MBB = * It ; removeUnconditionalBranch ( MBB ) ; removeRedundantConditionalBranch ( MBB )


<s> for ( unsigned Idx = <NUM_LIT> ; Idx < MRI -> getNumVirtRegs ( ) ; ++ Idx ) { Register Reg = Register :: index2VirtReg ( Idx ) ; if ( ! isGPR ( MRI -> getRegClass ( Reg ) ) ) continue ; if ( EnclosedEdges . count ( Reg ) ) continue ; Closure C ( ClosureID ++ , { MaskDomain } ) ; buildClosure ( C , Reg ) ; if ( ! C . empty ( ) && C . isLegal ( MaskDomain ) ) Closures . push_back ( std :: move ( C ) ) ; } for ( Closure & C : Closures ) { LLVM_DEBUG ( C . dump ( MRI ) ) ; if ( isReassignmentProfitable ( C , MaskDomain ) ) { reassign ( C , MaskDomain ) ; ++ NumClosuresConverted ; Changed = true


<s> return generateImmOutOfRangeError ( Operands , ErrorInfo , - ( <NUM_LIT> << <NUM_LIT> ) , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> , <STR_LIT> ) ; case Match_InvalidCLUIImm : return generateImmOutOfRangeError ( Operands , ErrorInfo , <NUM_LIT> , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> , <STR_LIT> ) ; case Match_InvalidUImm7Lsb00 : return generateImmOutOfRangeError ( Operands , ErrorInfo , <NUM_LIT> , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> , <STR_LIT> ) ; case Match_InvalidUImm8Lsb00 : return generateImmOutOfRangeError ( Operands , ErrorInfo , <NUM_LIT> , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> , <STR_LIT> ) ; case Match_InvalidUImm8Lsb000 : return generateImmOutOfRangeError ( Operands , ErrorInfo , <NUM_LIT> , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> , <STR_LIT> ) ; case Match_InvalidSImm9Lsb0 : return generateImmOutOfRangeError ( Operands , ErrorInfo , - ( <NUM_LIT> << <NUM_LIT> ) , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> , <STR_LIT> ) ; case Match_InvalidUImm9Lsb000 : return generateImmOutOfRangeError ( Operands , ErrorInfo , <NUM_LIT> , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> , <STR_LIT> ) ; case Match_InvalidUImm10Lsb00NonZero : return generateImmOutOfRangeError ( Operands , ErrorInfo , <NUM_LIT> , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> , <STR_LIT> ) ; case Match_InvalidSImm10Lsb0000NonZero : return generateImmOutOfRangeError ( Operands , ErrorInfo , - ( <NUM_LIT> << <NUM_LIT> ) , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> , <STR_LIT> ) ; case Match_InvalidSImm12 : return generateImmOutOfRangeError ( Operands , ErrorInfo , - ( <NUM_LIT> << <NUM_LIT> ) , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> , <STR_LIT> <STR_LIT> ) ; case Match_InvalidSImm12Lsb0 : return generateImmOutOfRangeError ( Operands , ErrorInfo , - ( <NUM_LIT> << <NUM_LIT> ) , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> , <STR_LIT> ) ; case Match_InvalidSImm13Lsb0 : return generateImmOutOfRangeError ( Operands , ErrorInfo , - ( <NUM_LIT> << <NUM_LIT> ) , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> , <STR_LIT> ) ; case Match_InvalidUImm20LUI : return generateImmOutOfRangeError ( Operands , ErrorInfo , <NUM_LIT> , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> , <STR_LIT> <STR_LIT> <STR_LIT> ) ; case Match_InvalidUImm20AUIPC : return generateImmOutOfRangeError ( Operands , ErrorInfo , <NUM_LIT> , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> , <STR_LIT> <STR_LIT> <STR_LIT> ) ; case Match_InvalidSImm21Lsb0JAL : return generateImmOutOfRangeError ( Operands , ErrorInfo , - ( <NUM_LIT> << <NUM_LIT> ) , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> , <STR_LIT> ) ; case Match_InvalidCSRSystemRegister : { return generateImmOutOfRangeError ( Operands , ErrorInfo , <NUM_LIT> , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> , <STR_LIT> <STR_LIT> ) ; } case Match_InvalidFenceArg : { SMLoc ErrorLoc = ( ( <ISA_LIT>Operand & ) * Operands [ ErrorInfo ] ) . getStartLoc ( ) ; return Error ( ErrorLoc


<s> if ( Offset % Size != <NUM_LIT> ) return false ; int Count = Offset / Size ; switch ( VT . getSimpleVT ( ) . SimpleTy ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return isInt < <NUM_LIT> > ( Count


<s> return false ; case <STR_LIT> : { DebugLoc DL = MI -> getDebugLoc ( ) ; MachineBasicBlock & MBB = * MI -> getParent ( ) ; const unsigned DstReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; const bool DstIsDead = MI -> getOperand ( <NUM_LIT> ) . isDead ( ) ; const MachineOperand & MO = MI -> getOperand ( <NUM_LIT> ) ; auto LO16 = BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , DstReg ) ; auto HI16 = BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) ) . addReg ( DstReg , RegState :: Define | getDeadRegState ( DstIsDead ) ) . addReg ( DstReg ) ; if ( MO . isImm ( ) ) { const unsigned Imm = MO . getImm ( ) ; const unsigned Lo16 = Imm & <NUM_LIT> ; const unsigned Hi16 = ( Imm >> <NUM_LIT> ) & <NUM_LIT> ; LO16 = LO16 . addImm ( Lo16 ) ; HI16 = HI16 . addImm ( Hi16 ) ; }


<s> ReplInstrMCID . push_back ( & TII -> get ( <STR_LIT> ) ) ; ReplInstrMCID . push_back ( & TII -> get ( <STR_LIT> ) ) ; if ( shouldReplaceInst ( MF , OriginalMCID , ReplInstrMCID ) ) return false ; break ; case Interleave : std :: string Subtarget = SchedModel . getSubtargetInfo ( ) -> getCPU ( ) ; if ( InterlEarlyExit . find ( Subtarget ) != InterlEarlyExit . end ( ) ) return InterlEarlyExit [ Subtarget ] ; for ( auto & I : IRT ) { OriginalMCID = & TII -> get ( I . OrigOpc ) ; for ( auto & Repl : I . ReplOpc ) ReplInstrMCID . push_back ( & TII -> get ( Repl ) ) ; if ( shouldReplaceInst ( MF , OriginalMCID


<s> ablock * selectRegion ( ablock_set & regions ) { ablock * minID = NULL ; for ( ablock_set :: iterator i ( regions . begin ( ) ) , ie ( regions . end ( ) ) ; i != ie ; i ++ ) { if ( ! minID || minID -> ID > ( * i ) ->


<s> } SDValue FrameAddr = getFRAMEADDR ( depth - <NUM_LIT> , Op , DAG , Subtarget ) ; unsigned Offset = ( Subtarget -> is64Bit ( ) ) ? <NUM_LIT> : <NUM_LIT> ; SDValue Ptr = DAG . getNode ( <STR_LIT> , dl , VT , FrameAddr , DAG . getIntPtrConstant ( Offset , dl ) ) ; RetAddr = DAG . getLoad ( VT , dl , DAG . getEntryNode ( ) , Ptr , MachinePointerInfo ( ) , false , false , false , <NUM_LIT> ) ; return RetAddr


<s> assert ( MI -> getOperand ( <NUM_LIT> ) . isReg ( ) &&

MI -> getOperand ( <NUM_LIT> ) . isImm ( ) && <STR_LIT> ) ;


<s> if ( Sym -> getType ( ) == <STR_LIT> ) { if ( Sym -> isUndefined ( ) ) getTargetStreamer ( ) -> emitGlobalType ( Sym ) ; } else if ( Sym -> getType ( ) == <STR_LIT> ) getTargetStreamer ( ) -> emitTagType ( Sym ) ; else if ( Sym -> getType ( ) == <STR_LIT> ) getTargetStreamer ( ) -> emitTableType ( Sym ) ; } DenseSet < MCSymbol * > InvokeSymbols ; for ( const auto & F : M ) { if ( F . isIntrinsic ( ) ) continue ; if ( F . isDeclarationForLinker ( ) ) { SmallVector < MVT , <NUM_LIT> > Results ; SmallVector < MVT , <NUM_LIT> > Params ; computeSignatureVTs ( F . getFunctionType ( ) , & F , F , TM , Params , Results ) ; auto Signature = signatureFromMVTs ( Results , Params ) ; bool InvokeDetected = false ; auto * Sym = getMCSymbolForFunction ( & F , <STR_LIT> || <STR_LIT> , Signature . get ( ) , InvokeDetected ) ; if ( InvokeDetected && ! InvokeSymbols . insert ( Sym ) . second ) continue ; Sym -> setType ( <STR_LIT> ) ; if ( ! Sym -> getSignature ( ) ) { Sym -> setSignature ( Signature . get ( ) ) ; addSignature ( std :: move ( Signature ) ) ; } else { Signature . reset ( ) ; } getTargetStreamer ( ) -> emitFunctionType ( Sym ) ; if ( F . hasFnAttribute ( <STR_LIT> ) ) { StringRef Name = F . getFnAttribute ( <STR_LIT> ) . getValueAsString ( ) ; Sym -> setImportModule ( storeName ( Name ) ) ; getTargetStreamer ( ) -> emitImportModule ( Sym , Name ) ; } if ( F . hasFnAttribute ( <STR_LIT> ) ) { StringRef Name = InvokeDetected ? Sym -> getName ( ) : F . getFnAttribute ( <STR_LIT> ) . getValueAsString ( ) ; Sym -> setImportName ( storeName ( Name ) ) ; getTargetStreamer ( ) -> emitImportName ( Sym , Name ) ; } } if ( F . hasFnAttribute ( <STR_LIT> ) ) { auto * Sym = cast < MCSymbolWasm > ( getSymbol ( & F ) ) ; StringRef Name = F . getFnAttribute ( <STR_LIT> ) . getValueAsString ( ) ; Sym -> setExportName ( storeName ( Name


<s> if ( ( lsb & shift_mask ) == <NUM_LIT> ) return <NUM_LIT> ; return c == - lsb && lsb != <NUM_LIT> ; } else if ( GET_CODE ( andop ) == CONST_DOUBLE && ( GET_MODE ( andop ) == VOIDmode || GET_MODE ( andop ) == DImode ) ) { HOST_WIDE_INT low , lsb , shift_mask_low ; low = CONST_DOUBLE_LOW ( andop ) ; if ( HOST_BITS_PER_WIDE_INT < <NUM_LIT> ) { HOST_WIDE_INT high , shift_mask_high ; high = CONST_DOUBLE_HIGH ( andop ) ; if ( low == <NUM_LIT> ) { shift_mask_high = ~ <NUM_LIT> ; if ( INTVAL ( shiftop ) > <NUM_LIT> ) shift_mask_high <<= INTVAL ( shiftop ) - <NUM_LIT> ; lsb = high & - high ; if ( ( lsb & shift_mask_high ) == <NUM_LIT> ) return <NUM_LIT> ; return high ==


<s> ELF<ISA_LIT>AsmBackend ( const Target & T , Triple :: OSType _OSType ) : <ISA_LIT>AsmBackend ( T ) , OSType ( _OSType ) { HasScatteredSymbols = true ; HasReliableSymbolDifference = true


<s> static rtx generate_set_vrsave ( rtx reg , rs6000_stack_t * info , int epiloguep ) { int nclobs , i ; rtx insn , clobs [ TOTAL_ALTIVEC_REGS + <NUM_LIT> ] ; rtx vrsave = gen_rtx_REG ( SImode , VRSAVE_REGNO ) ; clobs [ <NUM_LIT> ] = gen_rtx_SET ( vrsave , gen_rtx_UNSPEC_VOLATILE ( SImode , gen_rtvec ( <NUM_LIT> , reg , vrsave ) , UNSPECV_SET_VRSAVE ) ) ; nclobs = <NUM_LIT> ; for ( i = FIRST_ALTIVEC_REGNO ; i <= LAST_ALTIVEC_REGNO ; ++ i ) if ( info -> vrsave_mask & ALTIVEC_REG_BIT ( i ) ) { if ( ! epiloguep || call_used_regs [ i ] ) clobs [ nclobs ++ ] = gen_rtx_CLOBBER ( VOIDmode , gen_rtx_REG ( V4SImode , i ) ) ; else { rtx reg = gen_rtx_REG ( V4SImode , i ) ; clobs [ nclobs ++ ] = gen_rtx_SET ( reg , gen_rtx_UNSPEC ( V4SImode , gen_rtvec ( <NUM_LIT> , reg ) , <NUM_LIT> ) ) ; } } insn = gen_rtx_PARALLEL ( VOIDmode , rtvec_alloc ( nclobs ) ) ; for ( i = <NUM_LIT> ; i < nclobs ; ++ i ) XVECEXP

( insn , <NUM_LIT> , i ) = clobs [ i ] ;


<s> static MCInstPrinter * create<ISA_LIT>MCInstPrinter ( const Triple & T , unsigned SyntaxVariant , const MCAsmInfo & MAI , const

MCInstrInfo & MII , const MCRegisterInfo & MRI ) {


<s> __builtin_ia32_scatterpfqpd ( mask , ( __v8di ) index , ( long long const * ) addr , scale ,


<s> return decodeRegisterClass ( Inst , RegNo ,


<s> extern __inline void __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) _tile_loadconfig ( const void * __config ) { __asm__ volatile ( <STR_LIT> :: <STR_LIT> ( * ( ( const void * *


<s> const <ISA_LIT>Subtarget & getSubtarget (


<s> StringRef CPU = STI . getCPU ( ) ; if ( TheTriple . isOSBinFormatMachO ( ) ) return new Darwin<ISA_LIT>_32AsmBackend ( T , MRI , CPU ) ; if ( TheTriple . isOSWindows ( ) && TheTriple . isOSBinFormatCOFF ( ) ) return new Windows<ISA_LIT>AsmBackend (


<s> static DecodeStatus DecodeScalar8RegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t Address , const void * Decoder ) { if ( RegNo > <NUM_LIT> ) return MCDisassembler :: Fail ; return DecodeAllRegRegisterClass ( Inst , RegNo , Address , Decoder


<s> V2 = ( Undef2 ? DAG . getUNDEF ( VT ) : ( IsUnary ? V1 : V2 ) ) ; V1 = ( Undef1 ? DAG . getUNDEF ( VT ) : V1 ) ; return true ; } if ( IsUnary && ( Zero1 || Zero2 ) ) { if ( ( Subtarget . hasSSE41 ( ) || VT == <STR_LIT> || VT == <STR_LIT> ) && isSequentialOrUndefOrZeroInRange ( TargetMask , <NUM_LIT> , NumElts , <NUM_LIT> ) ) return false ; bool MatchLo = true , MatchHi = true ; for ( int i = <NUM_LIT> ; ( i != NumElts ) && ( MatchLo || MatchHi ) ; ++ i ) { int M = TargetMask [ i ] ; if ( ( ( ( i & <NUM_LIT> ) == <NUM_LIT> ) && Zero1 ) || ( ( ( i & <NUM_LIT> ) == <NUM_LIT> ) && Zero2 ) || ( M == SM_SentinelUndef ) ) continue ; MatchLo &= ( M == Unpckl [ i ] ) ; MatchHi &= ( M == Unpckh [ i ] ) ; } if ( MatchLo || MatchHi ) { UnpackOpcode = MatchLo ? <STR_LIT> : <STR_LIT> ; V2 = Zero2 ? getZeroVector ( VT , Subtarget , DAG , DL ) : V1 ; V1 = Zero1 ? getZeroVector ( VT , Subtarget , DAG , DL ) : V1 ; return true ; } } if ( ! IsUnary ) { ShuffleVectorSDNode :: commuteMask ( Unpckl ) ; if ( isTargetShuffleEquivalent ( VT , TargetMask , Unpckl ) ) { UnpackOpcode = <STR_LIT> ; std :: swap ( V1 , V2 ) ; return true ; } ShuffleVectorSDNode :: commuteMask ( Unpckh ) ; if ( isTargetShuffleEquivalent ( VT , TargetMask , Unpckh ) ) { UnpackOpcode = <STR_LIT> ; std :: swap ( V1 , V2 ) ; return


<s> int i ; ix86_varargs_gpr_size = <NUM_LIT> ; ix86_varargs_fpr_size = <NUM_LIT> ; for ( i = cum -> regno ; i < X86_64_MS_REGPARM_MAX ; i ++ ) { rtx reg , mem ; mem = gen_rtx_MEM ( Pmode , plus_constant ( Pmode , virtual_incoming_args_rtx , i * UNITS_PER_WORD ) ) ; MEM_NOTRAP_P ( mem ) = <NUM_LIT> ; set_mem_alias_set ( mem , set ) ; reg = gen_rtx_REG ( Pmode , x86_64_ms_abi_int_parameter_registers [ i ] ) ; emit_move_insn ( mem , reg


<s> MCSection * CS = getStreamer ( ) . getCurrentSectionOnly ( ) ; MCSection * ReadOnlySection = getContext ( ) . getELFSection ( <STR_LIT> , ELF :: SHT_PROGBITS , ELF :: SHF_ALLOC ) ; MCSymbol * Sym = getContext ( ) . createTempSymbol ( ) ; const MCExpr * LoSym = MCSymbolRefExpr :: create ( Sym , MCSymbolRefExpr :: VK_None , getContext ( ) ) ; const <ISA_LIT>MCExpr * LoExpr = <ISA_LIT>MCExpr :: create ( <ISA_LIT>MCExpr :: MEK_LO , LoSym , getContext ( ) ) ; getStreamer ( ) . SwitchSection ( ReadOnlySection ) ; getStreamer ( ) . EmitLabel ( Sym , IDLoc ) ; getStreamer ( ) . EmitValueToAlignment ( <NUM_LIT> ) ; getStreamer ( ) . EmitIntValue ( ImmOp64 , <NUM_LIT> ) ; getStreamer ( ) . SwitchSection ( CS ) ; if ( emitPartialAddress ( TOut , IDLoc , Sym ) ) return true ; if ( isABI_N64 ( ) ) TOut . emitRRX ( <STR_LIT> , TmpReg , TmpReg , MCOperand :: createExpr ( LoExpr ) , IDLoc , STI ) ; else TOut . emitRRX ( <STR_LIT> , TmpReg , TmpReg , MCOperand :: createExpr ( LoExpr ) , IDLoc , STI ) ; if ( isABI_N32 ( ) || isABI_N64 ( ) ) TOut . emitRRI ( <STR_LIT> , FirstReg , TmpReg , <NUM_LIT> , IDLoc , STI ) ; else { TOut . emitRRI ( <STR_LIT> , FirstReg , TmpReg , <NUM_LIT> ,


<s> bool Fast ; if ( RegVT . is256BitVector ( ) && ! DCI . isBeforeLegalizeOps ( ) && Ext == <STR_LIT> && ( ( Ld -> isNonTemporal ( ) && ! Subtarget . hasInt256 ( ) && Ld -> getAlignment ( ) >= <NUM_LIT> ) || ( TLI . allowsMemoryAccess ( * DAG . getContext ( ) , DAG . getDataLayout ( ) , RegVT , * Ld -> getMemOperand ( ) , & Fast ) && ! Fast ) ) ) { unsigned NumElems = RegVT . getVectorNumElements ( ) ; if ( NumElems < <NUM_LIT> ) return SDValue ( ) ; unsigned HalfOffset = <NUM_LIT> ; SDValue Ptr1 = Ld -> getBasePtr ( ) ; SDValue Ptr2 = DAG . getMemBasePlusOffset ( Ptr1 , HalfOffset , dl ) ; EVT HalfVT = EVT :: getVectorVT ( * DAG . getContext ( ) , MemVT . getScalarType ( ) , NumElems / <NUM_LIT> ) ; SDValue Load1 = DAG . getLoad ( HalfVT , dl , Ld -> getChain ( ) , Ptr1 , Ld -> getPointerInfo ( ) , Ld -> getOriginalAlign ( ) , Ld -> getMemOperand ( ) -> getFlags ( ) ) ; SDValue Load2 = DAG . getLoad ( HalfVT , dl , Ld -> getChain ( ) , Ptr2 , Ld -> getPointerInfo ( ) . getWithOffset ( HalfOffset ) , Ld -> getOriginalAlign ( ) , Ld -> getMemOperand ( ) -> getFlags ( ) ) ; SDValue TF = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Load1 . getValue ( <NUM_LIT> ) , Load2 . getValue ( <NUM_LIT> ) ) ; SDValue NewVec = DAG . getNode ( <STR_LIT> , dl , RegVT , Load1 , Load2 ) ; return DCI . CombineTo ( N , NewVec , TF , true ) ; } if ( Ext == <STR_LIT> && ! Subtarget . hasAVX512 ( ) && RegVT . isVector ( ) && RegVT . getScalarType ( ) == <STR_LIT> && DCI . isBeforeLegalize ( ) ) { unsigned NumElts = RegVT . getVectorNumElements ( ) ; EVT IntVT = EVT :: getIntegerVT ( * DAG . getContext ( ) , NumElts ) ; if ( TLI . isTypeLegal (


<s> unsigned Reg , SaveReg1 , SaveReg2 ; std :: tie ( Reg , SaveReg1 , SaveReg2 ) = Regs ; if ( <STR_LIT> . contains ( Reg ) ) BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) , Reg ) . addReg ( SaveReg1 ) . addReg ( SaveReg2 ) . add ( predOps ( <STR_LIT> ) ) ; else if ( <STR_LIT> . contains ( Reg ) ) BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) , Reg ) . addReg ( SaveReg1 ) . add ( predOps ( <STR_LIT> ) ) ; } for ( unsigned Reg : NonclearedFPRegs ) { if ( <STR_LIT> . contains ( Reg ) ) { if ( STI -> isLittle ( ) ) { BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) , Reg ) . addReg ( <STR_LIT> ) . addImm ( ( Reg - <STR_LIT> ) * <NUM_LIT> ) . add ( predOps ( <STR_LIT> ) ) ; } else { unsigned SReg0 = TRI -> getSubReg ( Reg , <STR_LIT> ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) , SReg0 ) . addReg ( <STR_LIT> ) . addImm ( ( Reg - <STR_LIT> ) * <NUM_LIT> ) . add ( predOps ( <STR_LIT> ) ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) , SReg0 + <NUM_LIT> ) . addReg ( <STR_LIT> ) . addImm ( ( Reg - <STR_LIT> ) * <NUM_LIT> + <NUM_LIT> ) . add ( predOps ( <STR_LIT> ) ) ; } } else if ( <STR_LIT> . contains ( Reg ) ) { BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) , Reg ) . addReg ( <STR_LIT> ) . addImm ( Reg - <STR_LIT> ) . add ( predOps ( <STR_LIT> ) ) ; } } if ( passesFPReg ) { BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) , SpareReg ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . add ( predOps ( <STR_LIT> ) ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) , SpareReg ) . addReg ( SpareReg ) . addImm ( <NUM_LIT> ) .

add ( predOps ( <STR_LIT> ) ) . add ( condCodeOp ( ) ) ;


<s> O << <STR_LIT> ; MachineModuleInfo * MMI = getAnalysisIfAvailable < MachineModuleInfo > ( ) ; assert ( MMI ) ; DwarfWriter * DW = getAnalysisIfAvailable < DwarfWriter > ( ) ; assert ( DW && <STR_LIT> ) ; DW -> BeginModule ( & M , MMI , O , this , TAI ) ; for ( Module :: global_iterator I = M . global_begin ( ) , E = M . global_end ( ) ; I != E ; ++ I ) { I -> setSection ( TAI -> SectionForGlobal ( I ) -> getName ( ) ) ; } EmitFunctionDecls ( M ) ; EmitUndefinedVars ( M ) ; EmitDefinedVars ( M ) ; EmitIData ( M


<s> ImmOp = Src1 ; RegOp = Src0 ; } else return std :: make_pair ( nullptr , <STR_LIT> ) ; int OMod = getOModValue ( Op , ImmOp -> getImm ( ) ) ; if ( OMod == <STR_LIT> || TII -> hasModifiersSet ( MI , <STR_LIT> :: src0_modifiers ) || TII -> hasModifiersSet ( MI , <STR_LIT> :: src1_modifiers ) || TII -> hasModifiersSet ( MI , <STR_LIT> :: omod ) || TII -> hasModifiersSet ( MI , <STR_LIT> :: clamp ) ) return std :: make_pair ( nullptr , <STR_LIT> ) ; return std :: make_pair ( RegOp , OMod ) ; } case <STR_LIT> : case <STR_LIT> : { if ( ( Op == <STR_LIT> && MFI -> getMode ( ) . FP32Denormals ) || ( Op == <STR_LIT> && MFI -> getMode ( ) . FP64FP16Denormals ) ) return std :: make_pair ( nullptr , <STR_LIT> ) ; const MachineOperand * Src0 = TII -> getNamedOperand (


<s> return ( __m512i ) __builtin_ia32_pbroadcastq512 ( ( __v2di ) __A , ( __v8di ) _mm512_undefined_epi32 ( )


<s> O << <STR_LIT> << Twine :: utohexstr ( MO . getImm ( ) ) ; return false ; case 'x' : if ( ( MO . getType ( ) ) != MachineOperand :: MO_Immediate ) return true ; O << <STR_LIT> << Twine :: utohexstr ( MO . getImm ( ) & <NUM_LIT> ) ; return false ; case 'd' : if ( ( MO . getType ( ) ) != MachineOperand :: MO_Immediate ) return true ; O << MO . getImm ( ) ; return false ; case 'm' : if ( ( MO . getType ( ) ) != MachineOperand :: MO_Immediate ) return true ; O << MO . getImm ( ) - <NUM_LIT> ; return false ; case 'y' : if ( ( MO . getType ( ) ) != MachineOperand :: MO_Immediate ) return true ; if ( ! isPowerOf2_64 ( MO . getImm ( ) ) ) return true ; O << Log2_64 ( MO . getImm ( ) ) ; return false ; case 'z' : if ( MO . getType ( ) == MachineOperand :: MO_Immediate && MO . getImm ( ) == <NUM_LIT> ) { O << <STR_LIT> ; return false ; } break ; case 'D' : case 'L' : case 'M' : { if ( OpNum == <NUM_LIT> ) return true ; const MachineOperand & FlagsOP = MI -> getOperand ( OpNum - <NUM_LIT> ) ; if ( ! FlagsOP . isImm ( ) ) return true ; unsigned Flags = FlagsOP . getImm ( ) ; unsigned NumVals = InlineAsm :: getNumOperandRegisters ( Flags ) ; if ( NumVals != <NUM_LIT> ) { if ( Subtarget -> isGP64bit ( ) && NumVals == <NUM_LIT> && MO . isReg ( ) ) { unsigned Reg = MO . getReg ( ) ; O << '$' << <ISA_LIT>InstPrinter :: getRegisterName ( Reg ) ; return false ; } return true ; } unsigned RegOp = OpNum ; if ( ! Subtarget -> isGP64bit ( ) ) { switch ( ExtraCode [ <NUM_LIT> ] ) { case 'M' : RegOp = ( Subtarget -> isLittle ( ) ) ? OpNum + <NUM_LIT> : OpNum ; break ; case 'L' : RegOp = ( Subtarget -> isLittle ( ) ) ? OpNum : OpNum + <NUM_LIT> ; break ; case 'D' : RegOp = OpNum +


<s> if ( GET_CODE ( x ) != MEM ) return false ; addr = XEXP ( x , <NUM_LIT> ) ; return ( nios2_large_constant_p ( addr ) || nios2_plus_large_constant_p


<s> assert ( Prefix == <STR_LIT> ) ; RC = getRegClassFor ( ( VT == <STR_LIT> ) ? <STR_LIT> : VT ) ; assert ( Reg < RC -> getNumRegs ( ) ) ; return std :: make_pair ( * ( RC -> begin ( ) +


<s> if ( SDValue R = FlattenVectorShuffle ( cast < ShuffleVectorSDNode > ( N ) , DAG ) ) return R ; SDValue Op0 = N -> getOperand ( <NUM_LIT> ) ; SDValue Op1 = N -> getOperand ( <NUM_LIT> ) ; if ( Op0 . getOpcode ( ) != <STR_LIT> || Op1 . getOpcode ( ) != <STR_LIT> || Op0 . getNumOperands ( ) != <NUM_LIT> || Op1 . getNumOperands ( ) != <NUM_LIT> ) return SDValue ( ) ; SDValue Concat0Op1 = Op0 . getOperand ( <NUM_LIT> ) ; SDValue Concat1Op1 = Op1 . getOperand ( <NUM_LIT> ) ; if ( ! Concat0Op1 . isUndef ( ) || ! Concat1Op1 . isUndef ( ) ) return SDValue ( ) ; const TargetLowering & TLI = DAG .


<s> const char * output_64bit_and ( rtx * operands ) { if ( GET_CODE ( operands [ <NUM_LIT> ] ) == CONST_INT && INTVAL ( operands [ <NUM_LIT> ] ) != <NUM_LIT> ) { unsigned HOST_WIDE_INT mask = INTVAL ( operands [ <NUM_LIT> ] ) ; int ls0 , ls1 , ms0 , p , len ; for ( ls0 = <NUM_LIT> ; ls0 < HOST_BITS_PER_WIDE_INT ; ls0 ++ ) if ( ( mask & ( ( unsigned HOST_WIDE_INT ) <NUM_LIT> << ls0 ) ) == <NUM_LIT> ) break ; for ( ls1 = ls0 ; ls1 < HOST_BITS_PER_WIDE_INT ; ls1 ++ ) if ( ( mask & ( ( unsigned HOST_WIDE_INT ) <NUM_LIT> << ls1


<s> return ACPV0 -> hasSameValue ( ACPV1 ) ; } else if ( ! is<ISA_LIT>CP0 && ! is<ISA_LIT>CP1 ) { return MCPE0 . Val . ConstVal == MCPE1 . Val . ConstVal ; } return false ; } else if ( Opcode == <STR_LIT> ) { if ( MI1 -> getOpcode ( ) != Opcode ) return false ; if ( MI0 -> getNumOperands ( ) != MI1 -> getNumOperands ( ) ) return false ; unsigned Addr0 = MI0 -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Addr1 = MI1 -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( Addr0 != Addr1 ) { if ( ! MRI || ! TargetRegisterInfo :: isVirtualRegister ( Addr0 ) || ! TargetRegisterInfo :: isVirtualRegister ( Addr1 ) ) return false ; MachineInstr * Def0 = MRI -> getVRegDef ( Addr0 ) ; MachineInstr * Def1 = MRI -> getVRegDef ( Addr1 ) ; if ( ! produceSameValue ( Def0 , Def1 , MRI ) ) return false ; } for ( unsigned i = <NUM_LIT> , e = MI0 -> getNumOperands ( ) ; i != e ; ++ i ) { const MachineOperand & MO0 = MI0 -> getOperand ( i ) ; const MachineOperand & MO1 = MI1 -> getOperand (


( __v8df ) _mm512_undefined_pd ( ) , ( __mmask8 ) - <NUM_LIT> , _MM_FROUND_CUR_DIRECTION ) ;


<s> int CCValidVal = CCValid -> getZExtValue ( ) ; int CCMaskVal = CCMask -> getZExtValue ( ) ; SDValue Chain = N -> getOperand ( <NUM_LIT> ) ; SDValue CCReg = N -> getOperand ( <NUM_LIT> ) ; if ( combineCCMask ( CCReg , CCValidVal , CCMaskVal ) ) return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , N -> getValueType ( <NUM_LIT> ) , Chain , DAG . getTargetConstant ( CCValidVal , SDLoc ( N ) , <STR_LIT> ) , DAG . getTargetConstant ( CCMaskVal , SDLoc ( N ) , <STR_LIT> ) , N -> getOperand ( <NUM_LIT> ) , CCReg ) ; return SDValue (


<s> printAddress ( MI -> getOperand ( OpNum ) . getReg ( ) , MI -> getOperand ( OpNum + <NUM_LIT> ) . getImm ( ) ,

MI -> getOperand ( OpNum + <NUM_LIT> ) . getReg ( ) , O ) ;


<s> TmpInst . setOpcode ( MI -> getOpcode ( ) ) ; TmpInst . addOperand ( MCOperand :: createReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ) ; if ( MI -> getOpcode ( ) == <STR_LIT> ) TmpInst . addOperand ( MCOperand :: createReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ) ; TmpInst . addOperand ( MCOperand :: createExpr ( DotExpr ) ) ; OutStreamer -> EmitInstruction ( TmpInst , STI ) ; return ; } case <STR_LIT> : { MCInst TmpInst ; MCSymbol * PICBase = MF -> getPICBaseSymbol ( ) ; TmpInst . setOpcode ( <STR_LIT> ) ; TmpInst . addOperand ( MCOperand :: createExpr ( MCSymbolRefExpr :: create ( PICBase , OutContext ) ) ) ; OutStreamer -> EmitInstruction ( TmpInst , STI ) ; TmpInst . setOpcode ( <STR_LIT> ) ; TmpInst . getOperand ( <NUM_LIT> ) = MCOperand :: createImm ( <NUM_LIT> ) ; OutStreamer -> EmitInstruction ( TmpInst , STI ) ; OutStreamer -> EmitLabel ( PICBase ) ; return ; } } if ( MI -> isInsideBundle ( ) ) OutStreamer -> AddComment ( <STR_LIT> ) ; if ( ( Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ) && ( ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) || ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) || ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) ) ) OutStreamer -> AddComment ( <STR_LIT> ) ; MCInst TmpInst ; MCInstLowering . Lower ( MI ,


<s> Align Alignment = cast < ConstantInt > ( I -> getArgOperand ( <NUM_LIT> ) ) -> getAlignValue ( ) ; auto * Ty = cast < FixedVectorType > ( Input -> getType ( ) ) ; if ( ! isLegalTypeAndAlignment ( Ty -> getNumElements ( ) , Ty -> getScalarSizeInBits ( ) , Alignment ) ) return nullptr ; lookThroughBitcast ( Ptr ) ; assert ( Ptr -> getType ( ) -> isVectorTy ( ) && <STR_LIT> ) ; IRBuilder < > Builder ( I -> getContext ( ) ) ; Builder . SetInsertPoint ( I ) ; Builder . SetCurrentDebugLocation ( I -> getDebugLoc ( ) ) ; Value * Store = tryCreateMaskedScatterOffset ( I , Ptr ,


<s> if ( ! Visited . insert ( MemAddr ) . second ) return false ; const auto * GV = dyn_cast < GlobalValue > ( MemAddr ) ; if ( ! GV ) { if ( const auto * CV = dyn_cast < Constant > ( MemAddr ) ) for ( const auto & CO : CV -> operands ( ) ) if ( memAddrUsesCTR ( CO , TM , Visited ) ) return true ; return false ; } if ( ! GV -> isThreadLocal ( ) ) return false ; TLSModel :: Model Model = TM . getTLSModel (


<s> Subtarget = & Fn . getSubtarget < <ISA_LIT>Subtarget > ( ) ; const bool Modified = AsmPrinter :: runOnMachineFunction ( Fn ) ; emitXRayTable (


<s> void <ISA_LIT>InstPrinter :: printRegName ( raw_ostream &


<s> void MVEGatherScatterLowering :: pushOutMul ( PHINode * & Phi , Value * IncrementPerRound , Value * OffsSecondOperand , unsigned LoopIncrement , IRBuilder < > & Builder ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; Instruction * InsertionPoint = & cast < Instruction > ( Phi -> getIncomingBlock ( LoopIncrement == <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ) -> back ( ) ) ; Value * StartIndex = BinaryOperator :: Create ( Instruction :: Mul , Phi -> getIncomingValue ( LoopIncrement == <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ) , OffsSecondOperand , <STR_LIT> , InsertionPoint ) ; Instruction * Product = BinaryOperator :: Create ( Instruction :: Mul , IncrementPerRound ,


<s> static MCCodeGenInfo * create<ISA_LIT>MCCodeGenInfo ( StringRef TT , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) { MCCodeGenInfo * X = new MCCodeGenInfo ( ) ; X -> InitMCCodeGenInfo ( RM ,


<s> UnsizedMemOp -> Mem . Size = getPointerWidth ( ) ; break ; } } } SmallVector < unsigned , <NUM_LIT> > Match ; FeatureBitset ErrorInfoMissingFeatures ; FeatureBitset MissingFeatures ; if ( Mnemonic == <STR_LIT> && Operands . size ( ) == <NUM_LIT> ) { auto * <ISA_LIT>Op = static_cast < <ISA_LIT>Operand * > ( Operands [ <NUM_LIT> ] . get ( ) ) ; if ( <ISA_LIT>Op -> isImm ( ) ) { const auto * CE = dyn_cast < MCConstantExpr > ( <ISA_LIT>Op -> getImm ( ) ) ; unsigned Size = getPointerWidth ( ) ; if ( CE && ( isIntN ( Size , CE -> getValue ( ) ) || isUIntN ( Size , CE -> getValue ( ) ) ) ) { SmallString < <NUM_LIT> > Tmp ; Tmp += Base ; Tmp += ( is64BitMode ( ) ) ? <STR_LIT> : ( is32BitMode ( ) ) ? <STR_LIT> : ( is16BitMode ( ) ) ? <STR_LIT> : <STR_LIT> ; Op . setTokenValue ( Tmp ) ; Match . push_back ( MatchInstruction ( Operands , Inst , ErrorInfo , MissingFeatures , MatchingInlineAsm , false ) ) ; Op . setTokenValue ( Base ) ; } } } if ( UnsizedMemOp && UnsizedMemOp -> isMemUnsized ( ) ) { static const unsigned MopSizes [ ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; for ( unsigned Size : MopSizes ) { UnsizedMemOp -> Mem . Size = Size ; uint64_t ErrorInfoIgnore ; unsigned LastOpcode = Inst . getOpcode ( ) ; unsigned M = MatchInstruction ( Operands , Inst , ErrorInfoIgnore , MissingFeatures , MatchingInlineAsm , isParsingIntelSyntax ( ) ) ; if ( Match . empty ( ) || LastOpcode != Inst . getOpcode ( ) ) Match . push_back ( M ) ; if ( Match . back ( ) == Match_MissingFeature ) ErrorInfoMissingFeatures = MissingFeatures ; } UnsizedMemOp -> Mem . Size = <NUM_LIT> ; } if ( Match . empty ( ) ) { Match . push_back ( MatchInstruction ( Operands , Inst , ErrorInfo , MissingFeatures , MatchingInlineAsm , isParsingIntelSyntax ( ) ) ) ; if ( Match . back ( ) == Match_MissingFeature ) ErrorInfoMissingFeatures = MissingFeatures ; } if ( UnsizedMemOp ) UnsizedMemOp -> Mem . Size = <NUM_LIT> ; if ( Match . back ( ) == Match_MnemonicFail ) { return Error ( IDLoc , <STR_LIT> + Mnemonic + <STR_LIT> , Op . getLocRange ( ) , MatchingInlineAsm ) ; } unsigned NumSuccessfulMatches = std :: count ( std :: begin ( Match ) , std :: end ( Match ) , Match_Success ) ; if ( UnsizedMemOp && NumSuccessfulMatches > <NUM_LIT> && UnsizedMemOp -> getMemFrontendSize ( ) ) { UnsizedMemOp -> Mem . Size = UnsizedMemOp -> getMemFrontendSize ( ) ; unsigned M = MatchInstruction ( Operands , Inst , ErrorInfo , MissingFeatures ,


<s> Register LiveIn = MRI . getLiveInVirtReg ( Reg ) ; if ( LiveIn ) return LiveIn ; Register NewReg = MRI . createGenericVirtualRegister ( Ty ) ; MRI . addLiveIn ( Reg , NewReg


<s> const MCSymbol * <ISA_LIT>ObjectWriter :: ExplicitRelSym ( const MCAssembler & Asm , const MCValue & Target , const MCFragment & F , const MCFixup & Fixup , bool IsPCRel ) const { if ( ! Target . isAbsolute ( ) && Target . getSymA ( ) -> getKind ( ) != MCSymbolRefExpr :: VK_None &&

IsPCRel ) return & Target . getSymA ( ) -> getSymbol ( ) . AliasedSymbol ( ) ;