GCC,nvptx,0,fclose ( in ) ; GCC,nvptx,1,if (output_fn_ptr && (omp_requires & GOMP_REQUIRES_REVERSE_OFFLOAD) != 0) { GCC,nvptx,2,if ( omp_requires_file ) maybe_unlink ( omp_requires_file ) ; GCC,nvptx,3, GCC,nvptx,4,stmt->sym = sym ? sym[0] : NULL; GCC,nvptx,5, GCC,nvptx,6,free_array_of_ptrs ( ( void * * ) paths ) ; GCC,nvptx,7,if ( GCC,nvptx,8,stmt ) ; GCC,nvptx,9, GCC,nvptx,10,return prev; GCC,nvptx,11,for ( ; *ptr; ptr++ ) { GCC,nvptx,12,"static void write_stmt ( FILE * out , const Stmt * stmt ) { if ( ( stmt -> vis & V_mask ) != V_comment ) { write_tokens ( out , stmt -> tokens , stmt -> len , ( stmt -> vis & V_mask ) == V_pred ) ; fputs ( stmt -> vis & V_no_eol ? : ""\n"" , out ) ; } }" GCC,nvptx,13,for ( ; stmts ; stmts = stmts -> next ) write_stmt(stmts); GCC,nvptx,14,for ( ; stmts ; stmts = stmts -> next ) write_stmt(stmts); GCC,nvptx,15,"fputs(, out);" GCC,nvptx,16,"fputs ( , out ) ;" GCC,nvptx,17, GCC,nvptx,18,"argv_obstack , ) ;" GCC,nvptx,19,"fprintf(out, ""var_ids = ["");" GCC,nvptx,20, GCC,nvptx,21,"""unlink failed: %s"", file ); } }" GCC,nvptx,22,static void mkoffload_cleanup ( void *data ) { struct offload_thread *thread = (struct offload_thread *)data; pthread_mutex_lock (&thread->lock); thread->state = OFFLOAD_THREAD_STATE_EXITING; pthread_mutex_unlock (&thread->lock); pthread_cond_signal (&thread->cond); } GCC,nvptx,23,nextval - curval; GCC,nvptx,24,"fprintf ( out , ) ;" GCC,nvptx,25,alloc ) ; } } GCC,nvptx,26,buffer[base] = '\0'; GCC,nvptx,27, GCC,nvptx,28,"cpp_define_formatted ( parse_in , , ""PTX_VERSION_MAJOR"", major ) ; cpp_define_formatted ( parse_in , , ""PTX_VERSION_MINOR"", minor ) ;" GCC,nvptx,29,"split ; fprintf ( file , , i , mode , split ) ; } } fprintf ( file , ) ; if ( cfun -> machine -> has_simtreg ) fprintf ( file , ) ; if ( cfun -> machine -> has_simtreg ) fprintf ( file , ) ; if ( cfun -> machine -> has_simtreg ) fprintf ( file , ) ; if ( cfun -> machine -> has_simtreg )" GCC,nvptx,30,"( cfun -> machine -> axis_predicate [ ] ) ) ; if ( cfun -> machine -> axis_predicate [ ] ) nvptx_init_axis_predicate ( file , REGNO ( cfun -> machine -> axis_predicate [ ] ) ) ; if ( cfun -> machine -> axis_predicate [ ] ) nvptx_init_axis_predicate ( file , REGNO ( cfun -> machine -> axis_predicate [" GCC,nvptx,31,emit_insn ( pat ) ; GCC,nvptx,32,"case NVPTX_BUILTIN_CMP_SWAP : case NVPTX_BUILTIN_CMP_SWAPLL : return nvptx_expand_cmp_swap ( exp , target , mode , ignore ) ;" GCC,nvptx,33,vector_red_partition = ; GCC,nvptx,34,target_flags |= TARGET_GOMP; GCC,nvptx,35,"for ( ; args ; args = TREE_CHAIN ( args ) , not_atomic_weak_arg -- ) {" GCC,nvptx,36,static machine_mode arg_promotion ( machine_mode mode ) { switch (mode) { case machine_mode::MM_VOID: return machine_mode::MM_VOID; case machine_mode::MM_INTEGER: return machine_mode::MM_INTEGER; case machine_mode::MM_FLOAT: return machine_mode::MM_FLOAT; case machine_mode::MM_DOUBLE: return machine_mode::MM_DOUBLE; GCC,nvptx,37,type ) ; GCC,nvptx,38, GCC,nvptx,39, GCC,nvptx,40,"fprintf(asm_out_file, ""\n"");" GCC,nvptx,41, GCC,nvptx,42,"args_so_far, arg, REG_EXPR, pc_rtx ) ; else cfun -> machine -> call_args = alloc_EXPR_LIST ( args_so_far, arg, MEM_EXPR, pc_rtx ) ; }" GCC,nvptx,43,"void nvptx_declare_object_name ( FILE * file , const char * name , const_tree decl ) { if ( decl && DECL_SIZE ( decl ) ) { tree type = TREE_TYPE ( decl ) ; unsigned HOST_WIDE_INT size ; init_output_initializer ( file , name , type , TREE_PUBLIC ( decl ) ) ; size = tree_to_uhwi ( DECL_SIZE_UNIT ( decl ) ) ; const char * section = nvptx_section_for_decl ( decl ) ; f" GCC,nvptx,44,free_EXPR_LIST_list ( & cfun -> x_stmt_list); GCC,nvptx,45,static void nvptx_end_call_args ( void ) { cfun -> machine -> start_call = NULL; } GCC,nvptx,46,"callee ) ; } } else { write_func_decl_from_insn ( func_decls , retval , pat , callee ) ; } return pat ; }" GCC,nvptx,47,"callee ) ; } } else { write_func_decl_from_insn ( func_decls , retval , pat , callee ) ; } return pat ; }" GCC,nvptx,48, GCC,nvptx,49, GCC,nvptx,50, GCC,nvptx,51,"fputs ( , asm_out_file ) ;" GCC,nvptx,52, GCC,nvptx,53,return gen_reg_rtx ( mode ); GCC,nvptx,54,return boundary; GCC,nvptx,55,nvptx_function_begin GCC,nvptx,56,"return gen_rtx_UNSPEC ( mode , gen_rtvec ( , GEN_INT ( ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) )" GCC,nvptx,57,"static rtx nvptx_function_value ( const_tree type , const_tree func ATTRIBUTE_UNUSED , bool outgoing ) { int unsignedp = TYPE_UNSIGNED ( type ) ; machine_mode orig_mode = TYPE_MODE ( type ) ; machine_mode mode = promote_function_mode ( type , orig_mode , & unsignedp , NULL_TREE , ) ; if ( outgoing ) return gen_rtx_REG ( mode , REGNO ( XEXP ( DECL_RT" GCC,nvptx,58, GCC,nvptx,59,return p; GCC,nvptx,60,"static rtx nvptx_libcall_value ( machine_mode mode , const_rtx ) { if ( cfun -> machine -> start_call == NULL_RTX ) return gen_rtx_REG ( mode , NVPTX_REG_O0 ); }" GCC,nvptx,61, GCC,nvptx,62,"return nvptx_convert_symbolic_operand (orig_op, as);" GCC,nvptx,63, GCC,nvptx,64,"fprintf ( asm_out_file , ) ; if ( result != NULL_RTX ) return ; return ;" GCC,nvptx,65,if (TYPE_MODE (result_type) != TYPE_MODE (result_type)) GCC,nvptx,66,mode ) ) ; } GCC,nvptx,67,"return ! PASS_IN_REG_P (mode, REGNO (operands[1]));" GCC,nvptx,68,"case MINUS: off = XEXP ( x , 1 ) ; break ; case REG: off = x ; break ; default: gcc_unreachable () ; } fprintf ( file , ""["" ) ; print_address_operand ( file , off ) ; fprintf ( file , ""]"" ) ; }" GCC,nvptx,69, GCC,nvptx,70,"static void nvptx_print_operand_address ( FILE * file , rtx addr ) { if (GET_CODE (addr) == REG) { fprintf (file, ""%s"", reg_names[REGNO (addr)]); } else if (GET_CODE (addr) == PLUS) { fprintf (file, ""%s"", reg_names[REGNO (XEXP (addr, 0))]); fprintf (file, ""%s"", reg_names[REGNO (X" GCC,nvptx,71, GCC,nvptx,72,if (promote) { GCC,nvptx,73,return false; GCC,nvptx,74,"tree * slot = declared_fndecls_htab->find_slot(decl, INSERT); if (*slot == NULL) { const char *name = get_fnname_from_decl(decl); name = nvptx_name_replacement(name);" GCC,nvptx,75,) { } } GCC,nvptx,76,"if (nvptx_record_fndecl(decl)) return; tree *slot = needed_fndecls_htab->find_slot(decl, INSERT);" GCC,nvptx,77,if (recog_data.operand_type[i] != OP_OUT) { GCC,nvptx,78,"struct reg_replace qiregs , hiregs , siregs , diregs ; rtx_insn * insn , * next ; compute_bb_for_insn ( ) ; df_clear_flags ( DF_LR_RUN_DCE ) ; df_analyze ( ) ; thread_prologue_and_epilogue_insns ( ) ; qiregs . n_allocated = ; hiregs . n_allocated = " GCC,nvptx,79,return false; GCC,nvptx,80,return ; GCC,nvptx,81,return false; GCC,nvptx,82,if ( ! DECL_STATIC_CHAIN ( fndecl ) ) return NULL ; GCC,nvptx,83,if ( GET_CODE ( obj ) == SUBREG ) obj = SUBREG_REG ( obj ) ; GCC,nvptx,84,last_arg_reg ) ; GCC,nvptx,85,"output_address(gen_int_mode(init_part, decl_chunk_mode));" GCC,nvptx,86,end_decl_field ( ) ; GCC,nvptx,87,) { if ( argtypes == NULL && ! AGGREGATE_TYPE_P ( type ) ) { if ( mode == SFmode ) { if ( args_from_decl ) args = TREE_CHAIN ( args ) ; else args = TREE_VALUE ( args ) ; } } } GCC,nvptx,88," , attrs ) != NULL_TREE ); ```" GCC,nvptx,89,"write_function_decl_and_comment(s, name, decl);" GCC,nvptx,90,"static void write_function_decl_and_comment ( std :: stringstream & s , const char * name , const_tree decl ) { s << ; if ( TREE_PUBLIC ( decl ) ) s << ""public ""; else s << ""private ""; s << name << "" ( "" << ; write_function_decl_and_comment ( s , name , decl ) ; }" GCC,nvptx,91,s << ; GCC,nvptx,92,type ) ; } return s.str ( ) ; } GCC,nvptx,93,block ) ; GCC,nvptx,94,FOR_EACH_BB_FN (block) { GCC,nvptx,95, GCC,nvptx,96, GCC,nvptx,97, GCC,nvptx,98, GCC,nvptx,99, GCC,nvptx,100,op ) ) ; GCC,nvptx,101,emit_insn ( gen_nvptx_join ( op ) ) GCC,nvptx,102, GCC,nvptx,103,"write_worker_buffer(asm_out_file, worker_red_sym, worker_red_align, worker_red_size);" GCC,nvptx,104, GCC,nvptx,105,static rtx GCC,nvptx,106,"static void nvptx_function_arg_advance ( cumulative_args_t cum_v , machine_mode mode , const_tree type )" GCC,nvptx,107,"return gen_rtx_UNSPEC ( mode , gen_rtvec ( , GEN_INT ( cum -> [NUM_LIT] ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) )" GCC,nvptx,108,"type ) ); if ( outgoing && mode == SFmode ) return gen_rtx_REG ( mode, FIRST_SF_REGNUM ); else if ( outgoing && mode == DFmode ) return gen_rtx_REG ( mode, FIRST_DF_REGNUM ); else if ( outgoing && mode == SCmode ) return gen_rtx_REG ( mode, FIRST_SC_REGNUM ); else if ( outgoing && mode == DCmode ) return gen_rtx_REG" GCC,nvptx,109, GCC,nvptx,110,"src0 , src1 ) ; break ; case SImode : res = gen_packsswb2 ( dst , src0 , src1 ) ; break ; case HImode : res = gen_packuswb2 ( dst , src0 , src1 ) ; break ; case QImode : res = gen_packuswb2 ( dst , src0 , src1 ) ; break ; default : abort () ; } return res ; }" GCC,nvptx,111,return res; GCC,nvptx,112,"enum machine_mode mode, rtx op) { rtx result = gen_reg_rtx (mode); emit_insn (gen_rtx_SET (result, gen_rtx_fmt_ee (mode, op))); return result; }" GCC,nvptx,113,"} break ; default : { rtx addr = data -> ptr ; if ( ! addr ) { unsigned align = GET_MODE_ALIGNMENT ( mode ) / BITS_PER_UNIT ; if ( align > worker_bcast_align ) worker_bcast_align = align ; data -> offset = ( data -> offset + align - 1 ) & ~ ( align - 1 ) ; addr = data -> base ; if ( data -> offset ) addr = gen_rtx_PLUS ( Pmode , addr , GEN_INT ( data -> offset ) ) ; } addr =" GCC,nvptx,114, GCC,nvptx,115,"tree call = build_call_expr ( fndecl, 3, size, align, offset );" GCC,nvptx,116,default : gcc_unreachable (); GCC,nvptx,117,"gsi_insert_seq_before (&gsi, seq, GSI_SAME_STMT);" GCC,nvptx,118, GCC,nvptx,119, GCC,nvptx,120,changed = true; GCC,nvptx,121, GCC,nvptx,122,gimple_seq unlock_seq = NULL; GCC,nvptx,123,basic_block pre_bb = gsi_bb (*gsi); GCC,nvptx,124,"static int labelno ; bool needs_tgt = register_operand (callee, Pmode); rtx pat = PATTERN (insn); int arg_end = XVECLEN (pat, 0); tree decl = NULL_TREE; fprintf (asm_out_file, ""call\t""); if (result != NULL) fprintf (asm_out_file, ""%s, %s"", nvptx_ptx_type_from_mode (GET_MODE (result), false), reg_names[" GCC,nvptx,125, GCC,nvptx,126, GCC,nvptx,127, GCC,nvptx,128,"emit_insn_after ( cpy, insn ) ;" GCC,nvptx,129,"fprintf ( asm_out_file , """" ) ;" GCC,nvptx,130,regstat_free_n_sets_and_refs ( max_regs ); GCC,nvptx,131,else { cond_branch = SET_SRC ( tail_branch ) ; if ( GET_CODE ( cond_branch ) != IF_THEN_ELSE ) cond_branch = NULL_RTX ; } } if ( tail == head ) { if ( ! head || ! INSN_P ( head ) ) return ; switch ( recog_memoized ( head ) ) { default : break ; case CODE_FOR_nvptx_fork : case CODE_FOR_nvptx_forked : case GCC,nvptx,132, GCC,nvptx,133,"ptr , data . offset ) ;" GCC,nvptx,134,"return gen_nvptx_barsync ( GEN_INT ( after ), GEN_INT ( 0" GCC,nvptx,135,data -> offset ) ) ; } else { return NULL_RTX ; } } GCC,nvptx,136,"static void write_worker_buffer ( FILE * file , rtx sym , unsigned int buffer_size ) { char * buffer = XNEWVEC ( char , buffer_size ); unsigned int written = 0; unsigned int total_written = 0; while ( written < buffer_size ) { unsigned int to_write = buffer_size - written; unsigned int n = write_worker ( file , sym , buffer + written , to_write ); if ( n == 0 ) break; written" GCC,nvptx,137, GCC,nvptx,138,if ( split != VOIDmode ) mode = split; GCC,nvptx,139, GCC,nvptx,140, GCC,nvptx,141,case QImode : { GCC,nvptx,142,dims[GOMP_DIM_VECTOR] = PTX_VECTOR_LENGTH; GCC,nvptx,143,if (fn_level <= GOMP_DIM_VECTOR && fn_level >= -NUM_LIT && dims[GOMP_DIM_VECTOR] >= NUM_LIT && dims[GOMP_DIM_VECTOR] != PTX_VECTOR_LENGTH) { GCC,nvptx,144,"diagnose_openacc_conflict ( TARGET_UNIFORM_SIMT , ) ;" GCC,nvptx,145, GCC,nvptx,146, GCC,nvptx,147, GCC,nvptx,148, GCC,nvptx,149,simtsz = HOST_WIDE_INT_M1U; GCC,nvptx,150, GCC,nvptx,151,"data -> ptr , GEN_INT ( GET_MODE_SIZE ( GET_MODE ( reg ) ) ) ) ) ) ; res = gen_sequence ( ) ; } return res ; }" GCC,nvptx,152,res = get_insns(); GCC,nvptx,153,"gimple_seq_add_stmt ( & seq , cond_stmt ) ;" GCC,nvptx,154,"gimple_seq_add_stmt ( & seq , cond_stmt ) ;" GCC,nvptx,155,static void nvptx_option_override ( void ) { GCC,nvptx,156,"par -> forked_block , par -> forked_insn ) ;" GCC,nvptx,157,end_sequence ( ) ; GCC,nvptx,158,"emit_insn ( gen_br_true_uni ( pred , label ) ) ;" GCC,nvptx,159,delete pars; GCC,nvptx,160,unsigned mask = 0; mask = oacc_get_fn_attrib ( current_function_decl ) ; GCC,nvptx,161,"return nvptx_propagate ( is_call , block , insn , PM_read_write , vprop_gen , ) ;" GCC,nvptx,162, GCC,nvptx,163,insn->getCode() == CODE_FOR_return ) { } Explanation: GCC,nvptx,164,"` is a placeholder for a numerical literal, which coul" GCC,nvptx,165,"static enum ptx_version default_ptx_version_option ( void ) { enum ptx_version first = first_ptx_version_supporting_sm ( ( enum ptx_isa ) ptx_isa_option ) ; enum ptx_version res = first ; res = MAX ( res, ( enum ptx_version ) ptx_version_option ) ; return res ; }" GCC,nvptx,166,return res; GCC,nvptx,167,"""Invalid option for OpenACC flag"" );" GCC,nvptx,168,"static void diagnose_openacc_conflict ( bool optval ) { if ( optval ) { error (""OpenACC and OpenMP are not compatible""); } }" GCC,nvptx,169,"static bool equal ( tree a , tree b ) { if ( a == nullptr && b == nullptr ) { return true; } if ( a == nullptr || b == nullptr ) { return false; } if ( a->data != b->data ) { return false; } return equal ( a->left , b->left ) && equal ( a->right , b->right ); }" GCC,nvptx,170,case PTX_ISA_SM80: return PTX_VERSION_7_0; GCC,nvptx,171,if ( TREE_CODE ( type ) != RECORD GCC,nvptx,172,if ( TREE_CODE ( last_field_type ) != ARRAY_TYPE ) return false ; GCC,nvptx,173,"FOR_ALL_BB_FN ( block , cfun ) { block -> flags |= BB_DIRTY; } Explanation:" GCC,nvptx,174, GCC,nvptx,175, GCC,nvptx,176,size_t len = strlen(ASM_COMMENT_START) + strlen(sep) + strlen(ASM_COMMENT_END); GCC,nvptx,177,"static rtx gen_comment ( const char * s ) { const char * sep = "" "" ; size_t len = strlen ( ASM_COMMENT_START ) + strlen ( sep ) + strlen ( s ) + 1 ; char * comment = ( char * ) alloca ( len ) ; snprintf ( comment , len , ""%s %s %s"", ASM_COMMENT_START , sep , s ) ; return gen_rtx_ASM_INPUT_loc ( VOIDmode , ggc_strdup ( comment ) , DECL_" GCC,nvptx,178, GCC,nvptx,179, GCC,nvptx,180,static hashval_t hash ( tree *t ) { if (t == NULL) { return 0; } else { return hash (t->left) + hash (t->right); } } GCC,nvptx,181,bool seq_routine_p = (partition_level == OMP_ATTRIB_LEVEL_SEQ); GCC,nvptx,182,else max_workers = oa.num_workers; GCC,nvptx,183,max_workers = oa.num_workers; GCC,nvptx,184,"fprintf ( file , ( size ? : ) , POINTER_SIZE , reg_names [ regno ] ) ;" GCC,nvptx,185,"fprintf ( file , , bits , reg_sspslot , reg_stack ) ;" GCC,nvptx,186,return GET_MODE_INNER ( mode ); GCC,nvptx,187,if (mode == TImode) return TImode; GCC,nvptx,188,dims[GOMP_DIM_VECTOR] = PTX_WARP_SIZE; GCC,nvptx,189,dims[GOMP_DIM_WORKER] = dims[GOMP_DIM_VECTOR] / PTX_WARP_SIZE; GCC,nvptx,190,"static void nvptx_asm_declare_constant_name ( FILE * file , const char * name , const_tree exp , HOST_WIDE_INT obj_size ) { write_var_marker ( file , true , false , name ) ; fprintf ( file , ) ; tree type = TREE_TYPE ( exp ) ; nvptx_assemble_decl_begin ( file , name , , type ) ; fprintf ( file , ) ; nvptx_assemble" GCC,nvptx,191,if (TREE_CODE (name) != FUNCTION_DECL) { GCC,nvptx,192,init_frag . remaining = ( size + elt_size - 1 ) / elt_size ; GCC,nvptx,193, GCC,nvptx,194, GCC,nvptx,195,The GCC,nvptx,196, GCC,nvptx,197,if (init_frag.offset == init_frag.size) GCC,nvptx,198,init_frag . offset * BITS_PER_UNIT ) ; GCC,nvptx,199, GCC,nvptx,200, GCC,nvptx,201,static bool nvptx_can_change_mode_class (machine_mode mode) { return mode == QImode || mode == HImode || mode == SImode || mode == DImode || mode == TImode; } GCC,nvptx,202,"return gen_nvptx_barsync ( lock , GEN_INT ( threads [0] ) );" GCC,nvptx,203, GCC,nvptx,204,decl ) ) ; GCC,nvptx,205, GCC,nvptx,206,gcc_assert ( block -> preds -> length ( ) == ) ; GCC,nvptx,207,"fprintf ( dump_file , ) ;" GCC,nvptx,208, GCC,nvptx,209,op ) ) ; } GCC,nvptx,210,if (mask & (GOMP_DIM_MASK(GOMP_DIM_WORKER) | GOMP_DIM_ GCC,nvptx,211,1. `free_EXPR_LIST_list(&cfun->machine->call_list);` GCC,nvptx,212, GCC,nvptx,213,"gcc_assert (vec_pos = XVECLEN (pat, ));" GCC,nvptx,214,"rtx mem = gen_rtx_MEM (mode, src);" GCC,nvptx,215,cmp ) ) ; return pred ; } GCC,nvptx,216, GCC,nvptx,217, GCC,nvptx,218,"SImode, EXPAND_NORMAL ) ;" GCC,nvptx,219,"rtx pat = nvptx_gen_shuffle ( target , src , idx , ( nvptx_shuffle_kind ) INTVAL ( op ) ) ;" GCC,nvptx,220, GCC,nvptx,221,} GCC,nvptx,222, GCC,nvptx,223,cum->count GCC,nvptx,224,"static void nvptx_function_arg_advance ( cumulative_args_t cum_v , const function_arg_info & ) { CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v );" GCC,nvptx,225,"fprintf(file, ""Hello, world!\n"");" GCC,nvptx,226,"arg . end_marker_p ( ) || ! arg . named ) return NULL_RTX ; return gen_rtx_UNSPEC ( arg . mode , gen_rtvec ( , GEN_INT ( cum -> count ) ) ) ; }" GCC,nvptx,227, GCC,nvptx,228,"static bool nvptx_function_ok_for_sibcall (tree fn, tree call)" GCC,nvptx,229,"case E_SImode: res = gen_pack_ss ( dst, src0, src1 ); break; case E_HImode: res = gen_pack_sh ( dst, src0, src1 ); break; case E_QImode: res = gen_pack_sq ( dst, src0, src1 ); break; default: gcc_unreachable (); } return res; }" GCC,nvptx,230,return res; GCC,nvptx,231,"return nvptx_gen_shuffle ( reg , reg , const0_rtx );" GCC,nvptx,232, GCC,nvptx,233, GCC,nvptx,234, GCC,nvptx,235, GCC,nvptx,236,return pred ? pred : gen_reg_rtx; GCC,nvptx,237, GCC,nvptx,238,return build_fold_addr_expr ( v ) ; GCC,nvptx,239,return decl; GCC,nvptx,240, GCC,nvptx,241,unsigned axis = TREE_INT_CST_LOW ( arg ) ; GCC,nvptx,242,"static void nvptx_goacc_reduction_fini ( gcall * call , offload_attrs * oa ) { gimple_stmt_iterator gsi = gsi_for_stmt ( call ) ; tree lhs = gimple_call_lhs ( call ) ; tree ref_to_res = gimple_call_arg ( call , 0 ) ; tree var = gimple_call_arg ( call , 1 ) ; int level = TREE_INT_CST_LOW ( gimple_call_arg ( call" GCC,nvptx,243,"gsi_insert_seq_before (&gsi, seq, GSI_SAME_STMT);" GCC,nvptx,244,gsi_next ( & gsi ) ; GCC,nvptx,245,"gimple_seq_add_stmt (&seq, tid_call);" GCC,nvptx,246,TREE_THIS_VOLATILE ( ref ) = ; GCC,nvptx,247,"gimple_stmt_iterator gsi = gsi_for_stmt ( call ) ; tree lhs = gimple_call_lhs ( call ) ; tree var = gimple_call_arg ( call , ) ; int level = TREE_INT_CST_LOW ( gimple_call_arg ( call , ) ) ; gimple_seq seq = NULL ; push_gimplify_context ( true ) ; if ( level == GOMP_DIM_WORKER || ( level == GO" GCC,nvptx,248,return false; GCC,nvptx,249,"tree decl = * node ; if ( TREE_CODE ( decl ) != VAR_DECL ) { error ( , name ) ; * no_add_attrs = true ; } else if ( ! ( TREE_PUBLIC ( decl ) || TREE_STATIC ( decl ) ) ) { error ( , name ) ; * no_add_attrs = true ; }" GCC,nvptx,250,"static unsigned int nvptx_hard_regno_nregs (unsigned int regno, machine_mode mode)" GCC,nvptx,251,"if (strcmp(name, """") == && cfun->machine->red_partition) {" GCC,nvptx,252,"DEF ( MEMBAR_SYS , , ( VOID , VOID , NULL_TREE ) ) ;" GCC,nvptx,253, GCC,nvptx,254,"fprintf ( file , ) ;" GCC,nvptx,255,case LABEL_REF: GCC,nvptx,256,"static rtx nvptx_libcall_value ( machine_mode mode , const_rtx ) { if ( ! cfun || ! cfun -> machine -> doing_call ) return gen_rtx_REG ( mode , NVPTX_RETURN_REGNUM ) ; return gen_reg_rtx ( mode ) ; }" GCC,nvptx,257,"return type == long_double_type_node; } return default_libc_has_function ( fn_class , type , fn_code ); }" GCC,nvptx,258,if ( type != NULL_TREE ) return type == NULL_TREE; GCC,nvptx,259,mode ); GCC,nvptx,260,return false; } GCC,nvptx,261, GCC,nvptx,262,tree acc_out = make_ssa_name ( var_type ) ; GCC,nvptx,263, GCC,nvptx,264,"This code snippet is initializing the `axis_dim_init_p` field of the `machine` structure of the `cfun` structure. The `!` operator is used to negate the value of the `axis_dim_init_p` field, so if it is already initialized, the code will not execute." GCC,nvptx,265,return cfun->machine->axis_dim_init_p->max_workers; GCC,nvptx,266,"Once the axis dimensions have been initialized," GCC,nvptx,267,"gcc_assert ( GET_CODE ( x ) == MEM ) ; const_rtx addr = XEXP ( x , ) ; subrtx_iterator :: array_type array ; FOR_EACH_SUBRTX ( iter , array , addr , ALL ) if ( SYMBOL_REF_P ( *iter ) ) { }" GCC,nvptx,268,return DATA_AREA_GENER GCC,nvptx,269,area == DATA_AREA_CONSTANT; GCC,nvptx,270,"static bool nvptx_modes_tieable_p (machine_mode mode1, machine_mode mode2) { return (mode1 == mode2) || (GET_MODE_CLASS (mode1) == MODE_FLOAT && GET_MODE_CLASS (mode2) == MODE_FLOAT && GET_MODE_SIZE (mode1) == GET_MODE_SIZE (mode2)); }" GCC,nvptx,271,"if (strcmp(name, ""John"") == 0) {" GCC,nvptx,272, ) return ; GCC,nvptx,273,bool worker = mask & GOMP_DIM_MASK ( GOMP_DIM_WORKER ) ; GCC,nvptx,274,return worker || large_vector; GCC,nvptx,275, GCC,nvptx,276, GCC,nvptx,277,"diagnose_openacc_conflict ( TARGET_UNIFORM_SIMT , ) ;" GCC,nvptx,278,size_t len ) GCC,nvptx,279,"void nvptx_output_ascii ( FILE * file, const char * str, unsigned HOST_WIDE_INT len ) {" GCC,nvptx,280, GCC,nvptx,281,] ; GCC,nvptx,282,return ; GCC,nvptx,283,src_regno ] ); } } GCC,nvptx,284,"nvptx_output_softstack_switch(asm_out_file, true, dest, size, align);" GCC,nvptx,285, GCC,nvptx,286,"static bool nvptx_pass_by_reference ( cumulative_args_t , const function_arg_info & arg ) { return pass_in_memory ( arg . mode , arg . type ); }" GCC,nvptx,287,"static bool nvptx_pass_by_reference ( cumulative_args_t , const function_type_info_t &fn_type_info) { if (fn_type_info.has_fixed_address_space()) { return false; } if (fn_type_info.has" GCC,nvptx,288,"pat, 0, 0 ) ;" GCC,nvptx,289,return V4SImode; GCC,nvptx,290,"UNORDERED : fputs ( , file ) ; break ; case ORDERED : fputs ( , file ) ; break ; default : gcc_unreachable ( ) ; } break ; case 'C' : fputs ( , file ) ; break ; case 'F' : fputs ( , file ) ; break ; case 'P' : fputs ( , file ) ; break ; case 'Q' : fputs ( <" GCC,nvptx,291,"* `nvptx_shared_propagate`: This is a function that is used to propagate shared variables in the NVPTX target. It takes several arguments, including a boolean indicating whether or" GCC,nvptx,292,"static machine_mode nvptx_promote_function_mode ( const_tree type , machine_mode mode , int * ARG_UNUSED ( punsignedp ) , const_tree funtype , int for_return ) { return promote_arg ( mode , for_return || ! type || TYPE_ARG_TYPES ( funtype ) ) ; }" GCC,nvptx,293, GCC,nvptx,294,case E_HFmode : return ; GCC,nvptx,295,"tree * slot = declared_fndecls_htab->find_slot(decl, INSERT);" GCC,nvptx,296,"const char * name = get_fnname_from_decl ( decl ) ; write_fn_proto ( func_decls , false , name ) ;" GCC,nvptx,297, GCC,nvptx,298, GCC,nvptx,299, GCC,nvptx,300,"fprintf(asm_out_file, );" GCC,nvptx,301,"tree type = TREE_TYPE ( var ) ; tree size = TYPE_SIZE ( type ) ; if ( size == TYPE_SIZE ( unsigned_type_node ) || size == TYPE_SIZE ( long_long_unsigned_type_node ) ) return nvptx_lockless_update ( loc , gsi , ptr , var , op ) ; else return nvptx_lockfull_update ( loc , gsi , ptr , var , op ) ;" GCC,nvptx,302,regstat_free_n_sets_and_refs ( ); GCC,nvptx,303,if (TARGET_UNIFORM_SIMT) GCC,nvptx,304,"static void nvptx_reorg_subreg ( void ) { struct reg_replace qiregs , hiregs , siregs , diregs ; rtx_insn * insn , * next ; qiregs . n_allocated = ; hiregs . n_allocated = ; siregs . n_allocated = ; diregs . n_allocated = ; qiregs . mode" GCC,nvptx,305,i ] == ' ' ) { } else { } GCC,nvptx,306,"return pass_in_memory ( TYPE_MODE ( type ) , type , true );" GCC,nvptx,307,"type) { if (TREE_CODE (type) == RECORD_TYPE && TYPE_MODE (type) == BLKmode && TYPE_SIZE (type) && !nvptx_ms_bitfield_layout_p (type)) { return true; } /* For nvptx, we always return vectors in memory if they are" GCC,nvptx,308,src ) ) ; GCC,nvptx,309, GCC,nvptx,310,Here are some of the issues with the code: GCC,nvptx,311, GCC,nvptx,312,"emit_insn_after (init, insn);" GCC,nvptx,313,if (cond_branch) { GCC,nvptx,314,"static void nvptx_skip_par ( unsigned mask , parallel * par ) { basic_block tail = par -> join_block ; gcc_assert ( tail -> preds -> next == NULL ) ; }" GCC,nvptx,315,map->get_or_insert(block) = elt; GCC,nvptx,316,return cum -> fntype == NULL_TREE || cum -> fntype == void_type_node; GCC,nvptx,317,True; GCC,nvptx,318, GCC,nvptx,319, GCC,nvptx,320,return true; GCC,nvptx,321,static bool nvptx_vector_mode_supported (machine_mode mode) { return (mode == V2DFmode || mode == V4SFmode || mode == V8HImode || mode == V16QImode); } GCC,nvptx,322,static bool nvptx_vector_mode_supported (machine_mode mode) { return (mode == V2DFmode || mode == V4SFmode || mode == V8HImode || mode == V16QImode); } GCC,nvptx,323,return l % PTX_WARP_SIZE == 0; GCC,nvptx,324,static bool nvptx_welformed_vector_length_p ( int l ) { gcc_assert ( l > ) ; return l % PTX_WARP_SIZE == 0; } GCC,nvptx,325,"asm_out_file , ) ; } }" GCC,nvptx,326,if (GET_MODE_SIZE (mode) > UNITS_PER_WORD) return true; GCC,nvptx,327,switch (ix) { case GOMP_DIM_MAX: oa->mask |= GOMP_DIM_MASK(ix); break; default: oa->mask &= ~GOMP_DIM_MASK(ix); break; } GCC,nvptx,328, GCC,nvptx,329,); } GCC,nvptx,330,case PTX_VERSION_6_3: GCC,nvptx,331,"fprintf(dump_file, ""Found matching bracket for %s at position %d\n"", pseudo.first, ix);" GCC,nvptx,332, GCC,nvptx,333,"static char const * const areas [ ] = { ""North"", ""East"", ""South"", ""West"" };" GCC,nvptx,334,void set_color ( auto_vec < unsigned > & color_counts ) { GCC,nvptx,335,"colors, unsigned color) { for (auto & c : colors) { c = color; } }" GCC,nvptx,336,"static const char * sm_version_to_string ( enum ptx_isa sm ) { switch ( sm ) { case PTX_ISA_1_0: return ""1.0""; case PTX_ISA_1_1: return ""1.1""; case PTX_ISA_1_2: return ""1.2""; case PTX_ISA_1_3: return ""1.3""; case PTX_ISA_1_4: return ""1.4"";" GCC,nvptx,337,return maybe_split_mode(mode) != VOIDmode; GCC,nvptx,338,if (seen_vector_label) { GCC,nvptx,339,seen_vector_jump ) ) ; gcc_assert ( ! ( worker_label && seen_worker_jump ) ) ; if ( seen_vector_label || seen_worker_label ) { gcc_assert ( ! ( vector_label && ! seen_vector_jump ) ) ; gcc_assert ( ! ( worker_label && ! seen_worker_jump ) ) ; if ( seen_vector_label || seen_worker_label ) { gcc_assert ( ! ( vector_label && ! seen_vector_jump ) ) ; gcc_assert ( ! ( worker_label GCC,nvptx,340,seen_worker_label ) ; break ; case CODE_FOR_nvptx_barrier : gcc_assert ( ! seen_vector_label && ! seen_worker_label ) ; break ; default : break ; } } } GCC,nvptx,341,"reg, pm, count, data, vector );" GCC,nvptx,342,"static rtx warp_prop_gen ( rtx reg , propagate_mask pm , unsigned ARG_UNUSED ( count ) , void * ARG_UNUSED ( data ) , bool ARG_UNUSED ( vector ) ) { if ( ! ( pm & PM_read_write ) ) { return reg; } else { return NULL_RTX; } }" GCC,nvptx,343,if (NOTE_P(insn) || DEBUG_INSN_P(insn)) { ... } GCC,nvptx,344, GCC,nvptx,345, GCC,nvptx,346, GCC,nvptx,347,"gcc_assert ( CONST0_RTX ( GET_MODE ( reg ) ) ) ; start_sequence ( ) ; emit_move_insn ( reg , CONST0_RTX ( GET_MODE ( reg ) ) ) ; rtx_insn * inits = get_insns ( ) ; end_sequence ( ) ; if ( dump_file && ( dump_flags & TDF_DETAILS ) ) for ( rtx_insn * init = inits ; init != NULL ; init = NEXT_INSN ( init ) ) fprintf ( dump_file" GCC,nvptx,348,"end_sequence ( ) ; bitmap_set_bit ( DF_MIR_IN ( bb ) , ix ) ; bitmap_set_bit ( DF_LIVE_IN ( bb ) , ix ) ; } } }" GCC,nvptx,349, GCC,nvptx,350,"if ( name [ ] == '*' ) name ++ ; if ( is_defn ) write_fn_proto_1 ( s , false , name );" GCC,nvptx,351, GCC,nvptx,352,"if ( stdarg_p ( fntype ) ) argno = write_arg_type ( s , - , argno , type , prototyped ) ;" GCC,nvptx,353, GCC,nvptx,354,char *replaced_dots = NULL; GCC,nvptx,355,Here is a breakdown of the code: GCC,nvptx,356,sfx = ; GCC,nvptx,357,parallel :: ~ parallel = do GCC,riscv,0, GCC,riscv,1,"return ""Invalid type"";" GCC,riscv,2, GCC,riscv,3, GCC,riscv,4, GCC,riscv,5,else { GCC,riscv,6,"void riscv_atomic_assign_expand_fenv ( tree * hold , tree * clear , tree * update ) { if ( ! ( TARGET_HARD_FLOAT || TARGET_ZFINX ) ) return ; tree frflags = GET_BUILTIN_DECL ( CODE_FOR_riscv_frflags ) ; tree fsflags = GET_BUILTIN_DECL ( CODE_FOR_riscv_fsflags ) ; tree old_flags = create_tmp_var_raw ( RISCV_ATYPE_USI" GCC,riscv,7, GCC,riscv,8,"RISCV_BUILTIN_COMPLEX : return riscv_expand_builtin_complex ( d -> icode , target , exp , true ) ; } } } }" GCC,riscv,9,riscv_builtins[i]; GCC,riscv,10,static void riscv_init_builtin_types ( void ) { if ( ! float16_type_node ) { riscv_float16_type_node = make_node ( REAL_TYPE ) ; TYPE_PRECISION ( riscv_float16_type_node ) = 16 ; } } GCC,riscv,11,"void riscv_atomic_assign_expand_fenv ( tree * hold , tree * clear , tree * update ) { if ( ! TARGET_HARD_FLOAT ) return ; tree frflags = GET_BUILTIN_DECL ( CODE_FOR_riscv_frflags ) ; }" GCC,riscv,12,"RISCV_BUILTIN_TYPE_MD: return riscv_expand_builtin_direct ( d -> icode , target , exp , true ) ; case RISCV_BUILTIN_TYPE_MD_NO_TARGET: return riscv_expand_builtin_direct ( d -> icode , target , exp , false ) ; default: gcc_unreachable () ; } }" GCC,riscv,13,"rtx riscv_expand_builtin ( tree exp , rtx target , rtx subtarget ATTRIBUTE_UNUSED , machine_mode mode ATTRIBUTE_UNUSED , int ignore ATTRIBUTE_UNUSED ) { tree fndecl = TREE_OPERAND ( CALL_EXPR_FN ( exp ) , ) ; unsigned int fcode = DECL_FUNCTION_CODE ( fndecl ) ; const struct riscv_builtin_description * d = & riscv_built" GCC,riscv,14, GCC,riscv,15,type ) { case RISCV_FTYPE_VOID: types[ (int)type ] = void_type_node; break; case RISCV_FTYPE_INT: types[ (int)type ] = integer_type_node; break; case RISCV_FTYPE_FLOAT: types[ (int)type ] = float_type_node; break; case RISCV_FTYPE_DOUBLE: types[ (int)type ] = double_type_node; break; case GCC,riscv,16,".value : const0_rtx ; } static rtx riscv_expand_builtin_direct ( tree exp , rtx target , bool has_target_p ) { enum insn_code icode = INTVAL ( CALL_EXPR_ARG ( exp , 0 ) ) ; unsigned int n_ops = TREE_OPERAND_LENGTH ( exp ) - 1 ; struct expand_operand ops [ n_ops ] ; unsigned int i = 0 ; for ( ; i < n_ops ; i ++ ) { riscv_prepare_builtin" GCC,riscv,17, GCC,riscv,18, GCC,riscv,19,"tree riscv_builtin_decl ( unsigned int code , bool initialize_p ) { tree decl = NULL_TREE; switch (code) { case RISCV_BUILTIN_ADD: decl = riscv_builtin_add_decl; break; case RISCV_BUILTIN_SUB: decl = riscv_builtin_sub_decl; break; case RISCV_BUILTIN_MUL: decl = riscv" GCC,riscv,20, GCC,riscv,21,"for ( int argno = ; argno < call_expr_nargs ( exp ) ; argno ++ ) riscv_prepare_builtin_arg ( & ops [ opno ++ ] , exp , argno ) ; return riscv_expand_builtin_insn ( icode , opno , ops , exp ) ;" GCC,riscv,22,error ( ) ; GCC,riscv,23, GCC,riscv,24,"static void riscv_prepare_builtin_arg ( struct expand_operand * op , tree type , tree arg) { if (TREE_CODE (arg) == ERROR_MARK) { op->error = 1; return; } if (TREE_CODE (arg) == INTEGER_CST) { op->type = OP_CONST; op->data.const_value = integer_constant_value (arg); return; }" GCC,riscv,25,"create_input_operand ( op , expand_normal ( arg ) , TYPE_MODE ( TREE_TYPE ( arg ) ) );" GCC,riscv,26,return (major * 100) + (minor * 10) + patch; GCC,riscv,27,#include GCC,riscv,28,"abi = """";" GCC,riscv,29,"{ , riscv_d_handle_target_float_abi } , { , riscv_d_handle_target_float_abi } }" GCC,riscv,30,void riscv_d_register_ GCC,riscv,31, GCC,riscv,32,return op1_val * op2_val; GCC,riscv,33, GCC,riscv,34,"I'm sorry, but I don't understand what you're referring to with ""run_poly_int_selftests"" and ""run_const_vector_selftests."" Could you please provide more context or clarify your question?" GCC,riscv,35,"void riscv_run_selftests (void) { printf(""Selftests completed successfully\n""); }" GCC,riscv,36,end_sequence ( ) ; GCC,riscv,37, GCC,riscv,38,") ; rtx_insn * insn = get_last_insn ( ) ; rtx src = XEXP ( SET_SRC ( PATTERN ( insn ) ) , ) ; ASSERT_TRUE ( rtx_equal_p ( src , gen_rtx_VEC_DUPLICATE ( mode , XEXP ( src , ) ) ) ) ; end_sequence ( ) ; } } }" GCC,riscv,39,"get_last_insn ( ) ; rtx src = XEXP ( SET_SRC ( PATTERN ( insn ) ) , ) ; ASSERT_TRUE ( rtx_equal_p ( src , gen_rtx_VEC_DUPLICATE ( mode , XEXP ( src , ) ) ) ) ; end_sequence ( ) ; } }" GCC,riscv,40,"ASSERT_TRUE(known_eq(calculate_x_in_sequence(dest), poly_val));" GCC,riscv,41,"static void run_poly_int_selftests ( void ) { std :: vector < poly_int64 > worklist = { BYTES_PER_RISCV_VECTOR , BYTES_PER_RISCV_VECTOR * , BYTES_PER_RISCV_VECTOR * , - BYTES_PER_RISCV_VECTOR * , - BYTES_PER_RISCV_VECTOR * ) ) ; if ( i == ) { if ( XEXP ( pat , ) == CONST0_RTX ( GET_MODE ( XEXP ( pat , ) ) ) ) continue ; } if ( REG_N_REFS ( regno ) < ) ;" GCC,riscv,54,return new pass_shorten_memrefs (getAnalysis ().getLoopInfo ()); GCC,riscv,55,rtl_opt_pass * make_pass_shorten_memrefs ( gcc :: context * ctxt ) { return new pass_shorten_memrefs ( ctxt ); } GCC,riscv,56,"* `if (dump_file) fprintf(dump_file, );`: This line checks if `dump_file` is non-NULL, and if so, it prints a string literal to the file. The string literal is not specified" GCC,riscv,57,"} if ( ! INSN_P ( insn ) ) continue ; if ( CALL_P ( insn ) ) ++ call_count ; else if ( insn == prologue_matched ) ; else { df_ref use ; FOR_EACH_INSN_USE ( use , insn" GCC,riscv,58,if ( ! good_use ) GCC,riscv,59,( target ) ) ) return ; if ( GET_CODE ( target ) == SYMBOL_REF && ! SYMBOL_REF_SMALL_P ( target ) ) return ; if ( GET_CODE ( target ) == SYMBOL_REF && ! SYMBOL_REF_LOCAL_P ( target ) ) return ; if ( GET_CODE ( target ) == REG && ! REG_OK_FOR_SIBCALL_P ( REGNO ( target ) ) ) return ; if ( GET_CODE ( target ) == SYMBOL_REF && ! SYMBOL GCC,riscv,60, GCC,riscv,61,"This is the end of the code snippet. The `begin()` and `end()` functions are used to iterate over the elements of the `riscv_subset_t` array. The `begin()` function returns a pointer to the first element of the array, and the `end()` function returns a pointer to the last element of the array." GCC,riscv,62,{ return &subsets[0]; } GCC,riscv,63,const riscv_subset_t * end ( ) const { return NULL; } GCC,riscv,64,const riscv_subset_t * end ( ) { GCC,riscv,65,{ return m_xlen; } GCC,riscv,66,{ return m_xlen; } GCC,riscv,67,bool apply_mask_policy_p ( ) const override { return true; } GCC,riscv,68,{ return (m_tail_policy != NULL); } GCC,riscv,69,{ return (m_tail_policy != NULL); } GCC,riscv,70,PRED_TYPE_tu_p; } GCC,riscv,71,machine_mode mode = GET_MODE (e.target); GCC,riscv,72, GCC,riscv,73, GCC,riscv,74,"assign , GSI_NEW_STMT ) ; return repl ; } }" GCC,riscv,75,Here is an example of how you GCC,riscv,76,int clause_idx = 0; clause_idx < group.num_clauses; ++clause_idx ) { for ( unsigned int lit_idx = 0; lit_idx < group.num_lits; ++lit_idx ) { if ( group.preds[pred_idx] == group.clauses[clause_idx].pred_type ) { } } } GCC,riscv,77,for ( unsigned int pred_idx = ; group . preds [ pred_idx ] != NUM_PRED_TYPES ; ++ pred_idx ) GCC,riscv,78, GCC,riscv,79, GCC,riscv,80, GCC,riscv,81,"add_input_operand ( mode , CONSTM1_RTX ( mode ) );" GCC,riscv,82,"create_fixed_operand ( & m_ops [ opno ++ ] , operand_type , operand_value );" GCC,riscv,83,"mode, op );" GCC,riscv,84,set_mem_align ( mem GCC,riscv,85,"inline void function_expander :: add_output_operand ( machine_mode mode, rtx op) { output_operands.push_back (op); op->mode = mode; } output_operands.push_back (op); op->mode" GCC,riscv,86,"add_input_operand (mode, gen_scalar_move_mask (mode, 0xff));" GCC,riscv,87,"add_input_operand ( mode , RVV_VUNDEF ( mode ) );" GCC,riscv,88,"void function_expander :: add_vundef_operand ( machine_mode mode ) { add_input_operand ( mode , RVV_VUNDEF ( mode ) ) ; }" GCC,riscv,89,for (unsigned int i = ; instance.op_info->args[i]. GCC,riscv,90,argument_types.size() ; i < instance.get_arity() ; ++i ) { argument_types.push_back(instance.get_argument_type(i)); } } GCC,riscv,91, GCC,riscv,92,for (int i = 0; i < op_info->num_args; i++) { GCC,riscv,93,void function_builder :: append_base_name ( const char * name ) { append_name ( ) ; append_name ( name ) ; } GCC,riscv,94,argument_types.quick_push(mask_type); GCC,riscv,95, GCC,riscv,96,return TYPE_MODE ( TREE_TYPE ( m_args [0] ) ) ); GCC,riscv,97,if (code >= vec_safe_length(registered_functions)) { GCC,riscv,98,return flags; GCC,riscv,99,return flags | CP_READ_FPCR | CP_RAISE_FP_EXCEPTIONS; GCC,riscv,100,virtual bool check (const std::string& str) { if (str.empty()) { return false; } for (const char& c : str) { if (!std::isdigit(c)) { return false; } } return true; } GCC,riscv,101,"return function_checker ( location , rfn . instance , fndecl , TREE_TYPE ( rfn . decl ) , nargs , args ) ;" GCC,riscv,102, GCC,riscv,103,return true; GCC,riscv,104,const value_type& other) const { return value.first == other.first && value.second == other.second; } GCC,riscv,105,key; GCC,riscv,106,registered_function & rfn = * ( * ( ( tree_code_class ( code ) == TREE_CODE_CLASS ( TREE_CODE_BUILTIN_TEMPLATE ) ) ? & GCC,riscv,107,return (char *) obstack_finish(&m_string_obstack); GCC,riscv,108,"virtual gimple * fold (gimple *, gimple *, gimple *, gimple *, gimple *, gimple *, gimple *, gimple *, gimple *, gimple *, gimple *, gimple *, gimple *, gimple *, gimple *, gimple *, gimple *, gimple *, gimple *, gimple *, gimple *, gimple *, gimple *, gimple *" GCC,riscv,109,m_obstack ); GCC,riscv,110,exp ( target_in ) GCC,riscv,111,inline bool function_call_info :: function_returns_void_p ( ) { return TREE_TYPE ( TREE_TYPE ( fndecl ) ) == void_type_node; } GCC,riscv,112,return TREE_TYPE ( TREE_TYPE ( fndecl ) ) ); GCC,riscv,113,"error ( ""cannot generate insn for %d"", icode );" GCC,riscv,114, GCC,riscv,115,"tree function_instance :: get_arg_type (tree type, int index) { tree arg_type = NULL_TREE; if (TREE_CODE (type) == METHOD_TYPE) { if (index == 0) { arg_type = TREE_TYPE (type); } else { arg_type = TREE_VALUE (TREE_PURPOSE (type)); } } else if (TREE_CODE (type) == FUNCTION_TYPE) { arg_type" GCC,riscv,116,function_instance instance = get_read_vl_instance(); GCC,riscv,117,"return function_instance(, bases::read_vl, shapes::read_vl)" GCC,riscv,118,for (unsigned int i = 0; all_ops[i].index GCC,riscv,119, GCC,riscv,120,return op_info -> ret . get_tree_type ( type . index ( 0 ) ); GCC,riscv,121,"1. If `op_info` is an object that contains information about the operation, and `type` is a string that represents the type of the operation, you could use the `get_tree_type` method to retrieve the return type of the operation. For example:" GCC,riscv,122,return builtin_types[VECTOR_TYPE_vuint8mf8_t]; GCC,riscv,123,return true; Explanation: GCC,riscv,124,return builtin_types[type_idx]; GCC,riscv,125,"return gen_int_mode ( get_prefer_tail_policy ( ) , Pmode ) ;" GCC,riscv,126, GCC,riscv,127, GCC,riscv,128,stmt ) ; GCC,riscv,129, GCC,riscv,130,function_table = new hash_table < registered_function_hasher > ( 1024 ) ; GCC,riscv,131,return value -> instance; GCC,riscv,132,return TYPE_MODE (op_info->args[].get_tree_type(type)); GCC,riscv,133,return TYPE_MODE ( op_info -> args [ ] . get_tree_type ( type . mode ); GCC,riscv,134, GCC,riscv,135,"return lookup_attribute ( , TYPE_ATTRIBUTES ( ) );" GCC,riscv,136,if (type == error_mark_node) { GCC,riscv,137,"TYPE_ATTRIBUTES ( type ) = tree_cons ( get_identifier ( ) , NULL_TREE , TYPE_ATTRIBUTES ( type ) );" GCC,riscv,138,const char * mangle_builtin_type ( const_tree type ) { GCC,riscv,139,if (TYPE_NAME (type) && TREE_CODE (TYPE_NAME (type)) == TYPE_DECL) GCC,riscv,140, GCC,riscv,141,CP_READ_STATE ) ; } GCC,riscv,142,return (flags & CP_READ_FPCR) != 0; GCC,riscv,143,abi_vector_types[type] = vectype; GCC,riscv,144,static void register_builtin_types ( ) { GCC,riscv,145,( * group . shape ) -> build GCC,riscv,146, GCC,riscv,147,"void function_checker :: report_out_of_range ( unsigned int argno , HOST_WIDE_INT actual , HOST_WIDE_INT min , HOST_WIDE_INT max ) void function_checker :: report_out_of_range ( unsigned int argno , HOST_WIDE_INT actual , HOST_WIDE_INT min , HOST_WIDE_INT max )" GCC,riscv,148,return type == RVV_BASE_vlmul_ext_x16; GCC,riscv,149,"HOST_WIDE_INT_C ( min ), HOST_WIDE_INT_C ( max ) ) ; }" GCC,riscv,150,gcc_assert ( argno < m_nargs ) ; GCC,riscv,151,( ) const { return TYPE_MODE ( TREE_TYPE ( TREE_TYPE ( TREE_TYPE ( TREE_TYPE ( TREE_TYPE ( TREE_TYPE ( TREE_TYPE ( TREE_TYPE ( TREE_TYPE ( TREE_TYPE ( TREE_TYPE ( TREE_TYPE ( TREE_TYPE ( TREE_TYPE ( TREE_TYPE ( TREE_TYPE ( TREE_TYPE ( TREE_TYPE ( TREE_TYPE ( TREE_TYPE ( TREE_TYPE ( TREE_TYPE ( TREE_TYPE ( TREE GCC,riscv,152,"memcpy(m_old_have_regs_of_mode, have_regs_of_mode, sizeof(have_regs_of_mode));" GCC,riscv,153,#define 10 GCC,riscv,154, GCC,riscv,155,"if ( type == error_mark_node ) return NULL_TREE ; return lookup_attribute ( , TYPE_ATTRIBUTES );" GCC,riscv,156,op2 ) ; GCC,riscv,157, GCC,riscv,158,int arg_offset = ; if ( base -> use_mask_predication_p ( ) ) { if ( use_real_mask_p ( pred ) ) add_input_operand ( arg_offset ++ ) ; else add_all_one_mask_operand ( mask_mode ( ) ) ; } if ( ! function_returns_void GCC,riscv,159, GCC,riscv,160, GCC,riscv,161,pred == PRED_TYPE_tumu GCC,riscv,162,static bool use_real_merge_p (const struct merge_options *o) GCC,riscv,163, GCC,riscv,164,function_builder :: ~ function_builder ( ~ function_builder ( ~ function_builder ( ~ function_builder ( ~ function_builder ( ~ function_builder ( ~ function_builder ( ~ function_builder ( ~ function_builder ( ~ function_builder ( ~ function_builder ( ~ function_builder ( ~ function_builder ( ~ function_builder ( ~ function_builder ( GCC,riscv,165," rvv_switcher ( ) { memcpy ( have_regs_of_mode , m_old_have_regs_of_mode , sizeof ( have_regs_of_mode ) ); }" GCC,riscv,166,"memcpy(have_regs_of_mode, m" GCC,riscv,167,"if ( bitmap_empty_p ( bitdata ) ) return false ; int ratio = - ; unsigned int bb_index ; sbitmap_iterator sbi ; EXECUTE_IF_SET_IN_BITMAP ( bitdata , , bb_" GCC,riscv,168, GCC,riscv,169,return false; GCC,riscv,170,"static bool any_set_in_bb_p ( hash_set < set_info * > sets , const bb_info * bb ) { for ( const set_info * set : sets ) if ( set -> bb == bb ) return true; return false; }" GCC,riscv,171,) ) ) return false ; } return true ; } } return false ; } GCC,riscv,172, GCC,riscv,173, GCC,riscv,174,"static bool avl_unavailable_p ( const vector_insn_info & info1 , const vector_insn_info & info2 )" GCC,riscv,175,return !info2.compatible_avl_p(); GCC,riscv,176,block_info.local_dem = block_info.reaching_out; GCC,riscv,177, GCC,riscv,178,return insn1.compare_with(insn2) < 0; GCC,riscv,179,"static unsigned calculate_sew ( vlmul_type vlmul , unsigned int xlen ) { switch (vlmul) { case VLMUL_1: return xlen; case VLMUL_1_2: return xlen / 2; case VLMUL_1_4: return xlen / 4; case VLMUL_1_8: return xlen / 8; default: return 0; } }" GCC,riscv,180,"static unsigned calculate_sew ( vlmul_type vlmul , unsigned vsew ) { switch (vlmul) { case VL_MUL_1: return vsew; case VL_MUL_2: return vsew * 2; case VL_MUL_4: return vsew * 4; case VL_MUL_8: return vsew * 8; default: return vsew; }" GCC,riscv,181,"static vlmul_type calculate_vlmul ( unsigned int sew , unsigned int ratio ) { for ( const vlmul_type vlmul : ALL_LMUL ) if ( calculate_ratio ( sew , vlmul ) == ratio ) return vlmul; }" GCC,riscv,182, GCC,riscv,183, GCC,riscv,184, GCC,riscv,185, GCC,riscv,186, GCC,riscv,187,if ( demand_p ( DEMAND_NONZERO_AVL ) && other . has_non_zero_avl ( ) ) GCC,riscv,188,if ( ! demand_p ( DEMAND_AVL ) ) return true ; GCC,riscv,189,if ( ! new_prob . initialized_p ( ) ) GCC,riscv,190, GCC,riscv,191, GCC,riscv,192,"void vector_infos_manager :: create_bitmap_vectors ( void ) { vector_antic = sbitmap_vector_alloc ( last_basic_block_for_fn ( cfun ) , vector_exprs . length ( ) ) ; vector_transp = sbitmap_vector_alloc ( last_basic_block_for_fn ( cfun ) , vector_exprs . length ( ) ) ; vector_comp = sbitmap_vector_alloc ( last_basic_block_for_fn ( cfun ) , vector_exprs . length" GCC,riscv,193,void vector_infos_manager :: create_expr ( vector_insn_info & info ) { GCC,riscv,194,); } GCC,riscv,195,m_demands [ type ] GCC,riscv,196,{ switch (type) { case DEMAND_TYPE_A: return true; case DEMAND_TYPE_B: return false; default: return false; } } GCC,riscv,197,class Demand { GCC,riscv,198,const vector_insn_info & info2 ) { return info1.lmul != info2.lmul; } GCC,riscv,199,vector_insn_info & info2) { return info1.mask_policy != info2.mask_policy; } GCC,riscv,200,"static bool different_ratio_p ( const vector_insn_info & info1 , const vector_insn_info & info2 ) { return info1 . get_ratio ( ) != info2 . get_ratio ( ); }" GCC,riscv,201,return info1.get_ratio() != info2.get_ratio(); GCC,riscv,202,return info1.get_sew() != info2.get_sew(); GCC,riscv,203,return info1.get_ta() != info2.get_ta(); GCC,riscv,204,return m_state == State::Running; GCC,riscv,205,return m_state == State::Running; GCC,riscv,206,"fprintf(file, )" GCC,riscv,207,remove_insn (rinsn); GCC,riscv,208,const vector& v) { return v.size() == 0; } GCC,riscv,209,return ; GCC,riscv,210,i ) ) { count ++ ; } return count ; } GCC,riscv,211,for ( size_t i = ; i < vector_exprs . length ( ) ; i ++ ) if ( bitmap_bit_p ( i ) ) { } GCC,riscv,212,return first_insn; GCC,riscv,213,static bool fault_first_load_p (rtx_insn *rinsn) { if (rinsn == NULL) return false; if (rinsn->code == CODE_FOR_fault_first_load) return true; return false; } GCC,riscv,214, GCC,riscv,215,"static insn_info * find_reg_killed_by ( const bb_info * bb , rtx x ) {" GCC,riscv,216,return info1.get_ratio() GCC,riscv,217,"static unsigned first_sew ( const vector_insn_info & info1 , const vector_insn_info & info2 ) { if (info1.sew == info2.sew) return info1.sew; else return std::min(info1.sew, info2.sew); }" GCC,riscv,218,const vector_insn_info & info2 ) { if (info1.first_sew != info2.first_sew) { return info1.first_sew < info2.first_sew; } return false; } GCC,riscv,219,return info1.get_sew() < array; GCC,riscv,220,return info1.get_sew() < info2.get_sew(); GCC,riscv,221,return info1.value; GCC,riscv,222,if ( local_dem . dirty_p ( ) ) continue ; GCC,riscv,223, GCC,riscv,224,gcc_assert ( has_vtype_op ( insn -> rtl ( ) ) ) ; GCC,riscv,225, GCC,riscv,226,vector_edge_list = nullptr ; GCC,riscv,227,demand ( DEMAND_MASK_POLICY ) ; GCC,riscv,228,if ( info1 . demand_p ( DEMAND_TAIL_POLICY ) ) { set_ta ( info1 . get_ta ( ) ) ; demand ( DEMAND_TAIL_POLICY ) ; } else if ( info2 . demand_p ( DEMAND_TAIL_POLICY ) ) { set_ta ( info2 . get_ta ( ) ) ; demand ( DEMAND_TAIL_POLICY ) ; } GCC,riscv,229,virtual bool gate(int x) = 0; GCC,riscv,230,else GCC,riscv,231,auto_vec available_list; GCC,riscv,232,auto_vec available_list; GCC,riscv,233,) ; GCC,riscv,234,"> ( set ) , real_p , phi_p , param_p );" GCC,riscv,235,rtx get_avl(struct rtx *rt) { GCC,riscv,236,const avl_info & get_avl_info ( ) const { return m_avl; } GCC,riscv,237, GCC,riscv,238, GCC,riscv,239,return i; GCC,riscv,240,return (bool) (get_prefer_mask_policy() & ) || (get_prefer_mask GCC,riscv,241,static bool get_default_ta ( ) { return ( bool ) ( get_prefer_tail_policy ( ) & || ( get_prefer_tail_policy ( ) == TAIL_POLICY_DEFAULT ); GCC,riscv,242,return ( bool ) ( get_prefer_tail_policy ( ) & || ( get_prefer_tail_policy ( ) >> 1 ) & 1 ); GCC,riscv,243,return vector_exprs.length() - 1; GCC,riscv,244,"for ( const insn_info * i = insn -> next_nondebug_insn ( ) ; real_insn_and_same_bb_p ( i , bb ) ; i = i -> next_nondebug_insn ( ) ) { if ( find_access ( i -> defs ( ) , VL_REGNUM ) ) return nullptr ; if ( read_vl_insn_p ( i -> rtl ( ) ) ) return nullptr ; } return nullptr ;" GCC,riscv,245,static vector_insn_info get_hard_empty ( ) { vector_insn_info info; info.insn = NULL; info.type = VECTOR_INSN_EMPTY; return info; } GCC,riscv,246,static vector_insn_info get_hard_empty ( ) { vector_insn_info vec; vec.clear(); return vec; } GCC,riscv,247,bool get_ma ( ) const { return ma; } GCC,riscv,248,uint8_t get_ratio ( ) const { return m_ratio; } GCC,riscv,249,bool get_ta ( ) const { return ta; } GCC,riscv,250,"return SET_DEST ( XVECEXP ( PATTERN ( rinsn ), 0, 0 ) ); Explanation: Next, the function extracts the first operand of the instruction using the `XVE" GCC,riscv,251,"return recog_data.operand[get_attr_vl_op_idx(rinsn)] ; } return SET_DEST(XVECEXP(PATTERN(rinsn), 0, 0)); }" GCC,riscv,252,else set = nullptr; GCC,riscv,253,if ( ! info2 . demand_p ( DEMAND GCC,riscv,254,return false; GCC,riscv,255,bool hard_empty_p ( ) const { GCC,riscv,256,bool has_avl_imm ( ) const { return m_avl . has_avl_imm (); } GCC,riscv,257,bool has_avl_no_reg ( ) const { return m_avl . has_avl_no_reg (); } GCC,riscv,258,{ return m_avl_reg != nullptr; } GCC,riscv,259,bool has_non_zero_avl ( ) const { return m_avl.size() > 0; } GCC,riscv,260,bool has_non_zero_avl ( ) const { return m_avl . has_non_zero_avl ( ); } GCC,riscv,261, GCC,riscv,262,static bool has_vl_op ( rtx_insn *insn) { return GET_CODE (insn) == VEC_OP; } GCC,riscv,263,"static bool has_vsetvl_killed_avl_p ( const bb_info * bb , const vector_insn_info & info ) { if ( info . dirty_with_killed_avl_p ( ) ) { rtx avl = info . get_avl ( ) ; if ( vlmax_avl_p ( avl ) ) return find_reg_killed_by ( bb , info . get_avl_reg_rtx ( ) ) != nullptr ; for ( const insn_info * insn : bb" GCC,riscv,264,static bool has_vtype_op ( rtx_insn * rinsn ) { return recog_memoized ( rinsn ) >= 0 && get_attr_has_vtype_op ( rinsn ); } GCC,riscv,265,static bool ignore_vlmul_insn_p ( rtx_insn * rinsn ) { return get_attr_type ( rinsn ) == TYPE_VIMOVVX || get_attr_type ( rinsn ) == TYPE_VFMOVVF || get_attr_type ( rinsn ) == TYPE_VMOVVX; } GCC,riscv,266,vector_insn_info & info2 ) { return ( info1.insn_type != info2.insn_type ) || ( info1.insn_type == INSN_TYPE_AVL && info1.avl_mode != info2.avl_mode ); } GCC,riscv,267,"static bool incompatible_avl_p ( const vector_insn_info & info1 , const vector_insn_info & info2 ) { return (info1.avl != info2.avl); }" GCC,riscv,268,if ( insn -> is_bb_head ( ) && ( types & BB_HEAD_SET ) ) return true ; GCC,riscv,269, GCC,riscv,270, GCC,riscv,271,return false; GCC,riscv,272,"return new pass_vsetvl ( ctxt, vsetvl ); Explanation:" GCC,riscv,273,return ma == INVALID_ATTRIBUTE ? get_default_ma() : IS_AGNOSTIC; GCC,riscv,274,return true; GCC,riscv,275,.m_source; GCC,riscv,276, GCC,riscv,277,return; GCC,riscv,278,rtl ( ) ) ) return ; if ( has_vl_op ( insn -> rtl ( ) ) ) m_demands [ DEMAND_AVL ] = true ; if ( get_attr_ratio ( insn -> rtl ( ) ) != INVALID_ATTRIBUTE ) m_demands [ DEMAND_RATIO ] = true ; else { m_demands [ DEMAND_SEW ] = true ; if ( ! ignore_vlmul_insn_p ( insn -> rtl ( ) ) ) m_demands [ GCC,riscv,279,const vector_insn_info & info2 ) { if (info1.insn_type != info2.insn_type) { return false; } if (info1.insn_type == VECTOR_INSN_TYPE_LOAD) { return info1.load_offset == info2.load_offset; } else if (info1.insn_type == VECTOR_INSN_TYPE_STORE) { return info1.store_offset == info2.store_offset GCC,riscv,280,if ( need_commit ) commit_edge_insertions ( m_vector_manager ) ; GCC,riscv,281,if (info2.demand_p(DEMAND_NONZERO_AVL)) { GCC,riscv,282,"fprintf ( dump_file , , m_vector_manager -> vector_exprs . length ( ) ) ; } }" GCC,riscv,283,"static unsigned ratio_for_second_sew_first_vlmul ( const vector_insn_info & info1 , const vector_insn_info & info2 ) { if (info1.sew == info2.sew && info1.vlmul == info2.vlmul) { return 1; } if (info1.sew == info2.sew && info1.vlmul == 1 && info2.vlmul == 2) { return 2; } if (info1" GCC,riscv,284, GCC,riscv,285,#include GCC,riscv,286,bool real_dirty_p (const struct buffer_head *bh) GCC,riscv,287,insn -> bb == bb; GCC,riscv,288,"static bool real_insn_and_same_bb_p ( const insn_info * insn , const insn_info * other_insn ) { return (insn->type == INSN_REAL && other_insn->type == INSN_REAL && insn->bb == other_insn->bb); }" GCC,riscv,289,"return def_insn->reg_available_p(insn, info);" GCC,riscv,290, GCC,riscv,291,return get_avl() == other.get_avl() && get_avl_source() == other.get_avl_source(); GCC,riscv,292, GCC,riscv,293,bool vl_vtype_info :: same_vtype_p ( const vl_vtype_info & other ) const { return get_sew ( ) == other . get_sew ( ) && get_vlmul ( ) == other . get_vlmul ( ) && get_ta ( ) == other . get_ta ( ); } GCC,riscv,294,static bool scalar_move_insn_p ( rtx_insn * rinsn ) { rtx_insn * set = rinsn->set; rtx_insn * dest = set->dest; rtx_insn * src = set->src; if (dest->type == REG && src->type == REG) { return true; } return false; } GCC,riscv,295,"static bool second_lmul_less_than_first_lmul_p ( const vector_insn_info & info1 , const vector_insn_info & info2 ) { return compare_lmul ( info2 . get_vlmul ( ) , info1 . get_vlmul ( ) ) == -1; }" GCC,riscv,296,"static bool second_lmul_less_than_first_lmul_p ( const vector_insn_info & info1 , const vector_insn_info & info2 ) { return info1.lmul < info2.lmul; }" GCC,riscv,297,return info2.get_ratio(); GCC,riscv,298,"static unsigned second_ratio ( const vector_insn_info & , const vector_insn_info & info2 ) { return info2 . get_ratio (); }" GCC,riscv,299,"return calculate_sew(info1.get_vlmul(), info2.get_ratio());" GCC,riscv,300,info1.get_vlmul()); GCC,riscv,301, GCC,riscv,302, GCC,riscv,303,return info2.get_sew() GCC,riscv,304,); } GCC,riscv,305,return info2.vlmul; GCC,riscv,306, GCC,riscv,307,This code defines a function called `set_dirty` that takes a single parameter of type `bool`. The function sets the `m_dirty` member variable to the value of the `dirty` parameter. GCC,riscv,308,void set_dirty ( bool dirty_with_killed_avl_p ) { if ( dirty_with_killed_avl_p ) dirty_with_killed_avl = true; } GCC,riscv,309,void set_empty() { empty = true; } GCC,riscv,310,void set_hard_empty ( ) { m_state = HARD_EMPTY; } GCC,riscv,311,ma; GCC,riscv,312, GCC,riscv,313,"m_ta = [1, 2, 3, 4, 5]" GCC,riscv,314,ta; GCC,riscv,315,void set_unknown (int value) { unknown = value; } GCC,riscv,316,void set_unknown ( ) { GCC,riscv,317,m_state = State.Running; GCC,riscv,318,"return source_equal_p ( insn1 , insn2 );" GCC,riscv,319, GCC,riscv,320,Here's a breakdown of the code: GCC,riscv,321, GCC,riscv,322,return; GCC,riscv,323,return m_state == State::Running; GCC,riscv,324, GCC,riscv,325,return false; GCC,riscv,326,return m_state == VALID || m_state == INVALID; GCC,riscv,327,rinsn ) == TYPE_VECTOR; } GCC,riscv,328, GCC,riscv,329,vector_block_infos[bb->index()].parse_block(bb); GCC,riscv,330,== CODE_FOR_vlmax_avldi || INSN_CODE ( rinsn ) == CODE_FOR_vlmax_avlss || INSN_CODE ( rinsn ) == CODE_FOR_vlmax_avlfs || INSN_CODE ( rinsn ) == CODE_FOR_vlmax_avlts; } GCC,riscv,331,return x GCC,riscv,332,"return calculate_vlmul(info1.get_sew(), info2.get_ratio());" GCC,riscv,333,return ( INSN_CODE ( rinsn ) == CODE_FOR_vsetvldi || INSN_CODE ( rinsn ) == CODE_FOR_vsetvldf ); GCC,riscv,334,"add_input_operand ( CONSTM1_RTX ( mode ) ," GCC,riscv,335, GCC,riscv,336,"void add_avl_type_operand ( avl_type type ) { add_input_operand ( gen_int_mode ( type , Pmode ) , NULL ); }" GCC,riscv,337,"create_input_operand ( & m_ops [ m_opno ++ ] , ""input"" + std::to_string ( m_opno ) );" GCC,riscv,338,"void add_input_operand ( rtx x , int n )" GCC,riscv,339, GCC,riscv,340,"void add_policy_operand ( enum tail_policy vta , enum mask_policy vma ) { rtx tail_policy_rtx = gen_int_mode ( vta , Pmode ); }" GCC,riscv,341,"void add_vundef_operand ( machine_mode mode ) { add_input_operand ( RVV_VUNDEF ( mode ) , ""vundef"" ); }" GCC,riscv,342,LMUL_4 : ratio = sew / 4; break; GCC,riscv,343,min_size; } GCC,riscv,344,return (vector_bits / elt_size); GCC,riscv,345,"return ( const_vec_duplicate_p ( x , & elt ) && CONST_INT_P ( elt ) && INTVAL ( elt ) == 1 ); Explanation:" GCC,riscv,346, GCC,riscv,347,"e.add_output_operand(dest, mode);" GCC,riscv,348,"emit_insn ( gen_vlmax_avl ( Pmode , vl , gen_int_mode ( ratio , SImode ) ) ) ;" GCC,riscv,349,m_ops ) ; } GCC,riscv,350,if (CONST_INT_P (vl) && !satisfies_constraint_K (vl)) GCC,riscv,351, GCC,riscv,352,"gen_vsetvl_no_side_effects (Pmode, vl, avl, gen_int_mode (sew, Pmode), gen_int_mode (get_vlmul (vmode), Pmode), const0_rtx);" GCC,riscv,353,const2_rtx ) ; GCC,riscv,354,"return gen_int_mode ( type, mode, operands, 1 );" GCC,riscv,355,int get_ma ( rtx ma ) { if ( INTVAL ( ma ) >= 0 ) return INTVAL ( ma ); else return -INTVAL ( ma ); } GCC,riscv,356,return INTVAL ( ma ); GCC,riscv,357,enum mask_policy get_prefer_mask_policy ( ) { return MASK_ANY; } enum mask_policy get_pre GCC,riscv,358,static unsigned get_sew ( machine_mode mode ) { unsigned int sew = GET_MODE_CLASS ( mode ) == MODE_VECTOR_BOOL ? 1 : GET_MODE_UNIT_SIZE ( mode ); return sew; } GCC,riscv,359,return sew; GCC,riscv,360,int get_ta ( rtx ta ) { if ( INTVAL ( ta ) == TAIL_ANY ) return INVALID_ATTRIBUTE ; return INTVAL ( ta ) ; } GCC,riscv,361, GCC,riscv,362,return opt_machine_mode(); GCC,riscv,363,"DImode ) ; emit_insn ( gen_no_side_effects_vsetvl_rtx ( demote_mode , i64vl , RVV_VLMAX ) ) ; } } However, based on the context of the code, it appears that is a constant value that is used to scale the value of the AVL" GCC,riscv,364,case LT : case LTU GCC,riscv,365,"if ( ! register_operand ( src , mode ) && ! register_operand ( dest , mode ) ) { rtx tmp = gen_reg_rtx ( mode ) ; if ( MEM_P ( src ) ) emit_vlmax_op ( code_for_pred_mov [INST] if ( ! register_operand ( src , mode ) && ! register_operand ( dest , mode ) ) { rtx tmp = gen_reg_rtx ( mode ) ; if ( MEM_P ( src ) ) emit_vlmax_op ( code_for_" GCC,riscv,366,return true; GCC,riscv,367,"-32, 31 );" GCC,riscv,368, GCC,riscv,369,"CONST0_RTX ( Pmode ) ; } else if ( register_operand ( ops [ ] , mode ) && rtx_equal_p ( ops [ ] , CONST1_RTX ( GET_MODE ( ops [ ] ) ) ) ) { merge = gen_highpart ( demote_mode , ops [ ] ) ; ta = ops [ ] ; } else { merge = gen_rtx_VEC" GCC,riscv,370,"However, based on the variable names and the fact that the code is using bitwise operations, it's possible that the code is attempting to perform some kind of bitwise manipulation or calculation. The `mask` variable is being assigned a value of ``, which suggests that it may be a bitmask or a literal value that is being used to perform a bitwise operation. The `fmask" GCC,riscv,371, GCC,riscv,372,n += (GET_MODE_SIZE (mode) + 7) / 8; GCC,riscv,373, GCC,riscv,374,single_insns ); GCC,riscv,375,"static void riscv_block_move_loop ( rtx dest , rtx src , unsigned HOST_WIDE_INT length , unsigned HOST_WIDE_INT bytes" GCC,riscv,376,label ) ; GCC,riscv,377, GCC,riscv,378, GCC,riscv,379,"return ( reload_completed && known_eq ( cfun -> machine -> frame . total_size , ) && ! cfun -> machine -> frame_needed );" GCC,riscv,380,"return (riscv_valid_base_register_p(info->reg, mode, strict_p) && riscv_valid_offset_p(info->offset, mode));" GCC,riscv,381,case CONST_INT: GCC,riscv,382,"return riscv_hard_regno_nregs ( V_REG_FIRST, mode );" GCC,riscv,383, GCC,riscv,384,if ( ! TARGET_VECTOR ) { for ( int regno = FP_REG_FIRST ; regno <= FP_REG_LAST ; regno ++ ) call_used_regs [ regno ] = < GCC,riscv,385, GCC,riscv,386,riscv_bytes_per_vector_chunk = TARGET_MIN_VLEN; GCC,riscv,387,"static section * riscv_elf_select_rtx_section ( machine_mode mode , rtx x , unsigned HOST_WIDE_INT align ) { section * s = default_elf_select_rtx_section ( mode , x , align ) ; if ( riscv_size_ok_for_small_data_p ( GET_MODE_SIZE ( mode ) . to_constant ( ) ) ) { s = riscv_elf_select_small_data_section ( mode , x , align ) ; } return s ;" GCC,riscv,388,static void riscv_emit_epilogue_components ( sbitmap components ) { } GCC,riscv,389,case EXCESS_PRECISION_TYPE_FLOAT16 : return FLT_EVAL_METHOD_PROMOTE_TO_FLOAT16; GCC,riscv,390, GCC,riscv,391,rtx tmp1 = gen_reg_rtx ( mode ) ; GCC,riscv,392,REG_NOTES (insn) = dwarf; GCC,riscv,393,"if (known_gt(step1, )) {" GCC,riscv,394,"op2 ) ; riscv_emit_move ( op0 , pat ) ; }" GCC,riscv,395,"riscv_adjust_frame_size ( frame , size ) ; It appears that the code is checking if the size of the frame is greater" GCC,riscv,396,"riscv_emit_stack_tie ( ) ; } if ( known_gt ( size , ) ) { poly_int64 scalable_frame ( , ) ; if ( ! size . is_constant ( ) ) { poly_int64 scalable_frame = size ; scalable_frame . coeffs [ ] = size . coeffs [ ] ; riscv_v_adjust_scalable_frame ( stack_pointer_" GCC,riscv,397, GCC,riscv,398, GCC,riscv,399, GCC,riscv,400,( elt_size ) ; } return n ; } default : gcc_unreachable () ; } } GCC,riscv,401,if ( ! extended && n == 10 ) { GCC,riscv,402, GCC,riscv,403,offset -= GET_MODE_SIZE(mode).to_constant(); GCC,riscv,404,"regno ) && ! fixed_regs[regno] && ! call_used_regs[regno] ) { bitmap_set_bit ( components , regno ) ; } return components ; }" GCC,riscv,405,return false; GCC,riscv,406, GCC,riscv,407, GCC,riscv,408,return true; GCC,riscv,409,"int div_factor = ; emit_move_insn ( tmp , gen_int_mode ( BYTES_PER_RISCV_VECTOR , mode ) ) ; if ( BYTES_PER_RISCV_VECTOR . is_constant ( ) ) { gcc_assert ( value . is_constant ( ) ) ; riscv_emit_move ( dest , GEN_INT ( value . to_constant ( ) ) ) ; return ; } else if ( ( factor % vlenb ) == ) div" GCC,riscv,410,static bool riscv_libgcc_floating_mode_supported_p ( scalar_float_mode mode ) { switch (mode) { case SFmode: case DFmode: return true; default: return false; } } GCC,riscv,411, GCC,riscv,412, GCC,riscv,413,if ( TREE_CODE ( type ) == REAL_TYPE && TYPE_PRECISION ( type ) == ) return ; if ( TYPE_NAME ( type ) != NULL ) { const char * res = ( TYPE_NAME ( type ) ) ; return res ; } } GCC,riscv,414,"riscv_emit_set ( dest, x ) ;" GCC,riscv,415,"codes[i].value, mode );" GCC,riscv,416,"return ""error"";" GCC,riscv,417, GCC,riscv,418,return (code == 200); GCC,riscv,419,return (code == 200); GCC,riscv,420, GCC,riscv,421, GCC,riscv,422, GCC,riscv,423,return GET_MODE_NUNITS (mode) * BITS_PER_UNIT; GCC,riscv,424,return BYTES_PER_SCALAR; GCC,riscv,425,init_optabs ( ); GCC,riscv,426,init_optabs ( ); GCC,riscv,427, GCC,riscv,428,return ( ! riscv_v_ext_vector_mode_p ( mode ) && GET_MODE_SIZE ( mode ) . to_constant ( ) > UNITS_PER_WORD && ( class1 == FP_REGS ) != ( class2 == FP_REGS ) ); GCC,riscv,429,"components , regno ) ) cfun -> machine -> reg_is_wrapped_separately [ regno ] = true ; }" GCC,riscv,430,regno ) ) cfun->machine->reg_is_wrapped_separately[regno] = true; GCC,riscv,431, GCC,riscv,432, GCC,riscv,433,bool riscv_sh GCC,riscv,434,Here are some GCC,riscv,435,"static HOST_WIDE_INT riscv_stack_align ( HOST_WIDE_INT align, HOST_WIDE_INT size) { if (align < 0) align = 0; if (size < 0) size = 0; if (align > size) return align; else return size; }" GCC,riscv,436,static HOST_WIDE_INT riscv_stack_align ( HOST_WIDE_INT value ) { return value & ~(HOST_WIDE_INT)(RISCV_STACK_ALIGN - 1); } GCC,riscv,437,"return wi::umin(min_size, ).to_uhwi;" GCC,riscv,438,"widest_int::from_constant (, SIGNED) );" GCC,riscv,439,return false; GCC,riscv,440,if ( TARGET_VECTOR ) return riscv_v_ext_vector_mode_p GCC,riscv,441,"static bool riscv_verify_type_context ( location_t loc , type_context_kind context , const_tree type ) { if (context == TYPE_CONTEXT_NONE) return true; if (context == TYPE_CONTEXT_NORMAL) return riscv_verify_type_context_normal (loc, type); if (context == TYPE_CONTEXT_RESTRICT) return riscv_verify_type_context_restrict (loc, type); if" GCC,riscv,442,"return ( loc , context )" GCC,riscv,443,If ` GCC,riscv,444, GCC,riscv,445,return riscv_vector_chunks * scale; GCC,riscv,446,"return riscv_v_ext_vector_mode_p ( mode ) ? riscv_v_adjust_precision ( mode, scale ) : mode;" GCC,riscv,447,REG_NOTES (insn) = dwarf; GCC,riscv,448,return false; GCC,riscv,449,return false; GCC,riscv,450,HARD_REG_SET riscv_zero_call_used_regs ( HARD_REG_SET need_zeroed_hardregs ) { HARD_REG_SET zeroed_hardregs; CLEAR_HARD_REG_SET ( zeroed_hardregs ); if ( TARGET_VECTOR ) zeroed_hardregs |= vector_zero_call_used_regs ( need_zeroed_hardregs ); return zeroed_hardregs; } GCC,riscv,451, GCC,riscv,452,regno ] ) { GCC,riscv,453,"static int riscv_address_cost ( rtx addr , enum machine_mode mode , addr_space_t as ATTRIBUTE_UNUSED , bool speed ATTRIBUTE_UNUSED ) { return riscv_address_insns ( addr , mode , false ) ; }" GCC,riscv,454,"int riscv_address_insns(uint64_t addr, int mode, int size) {" GCC,riscv,455, GCC,riscv,456,n += (GET_MODE_SIZE (mode) + 7) / 8; GCC,riscv,457,saved_size ) ) ; GCC,riscv,458,"rtx dwarf = NULL_RTX; rtx adjust_sp_rtx, reg, mem, insn; int saved_size = cfun->machine->frame.save_libcall_adjustment; int offset; for (int regno = GP_REG_FIRST; regno <= GP_REG_LAST - ; regno++) { if (BITSET_P(cfun->machine->frame.mask, regno - GP_REG_FIRST)) { if (regno == RET" GCC,riscv,459, GCC,riscv,460,"riscv_get_arg_info(&arg, get_cumulative_args(cum), mode, type, named, false);" GCC,riscv,461,if (tls_referenced_p (x)) GCC,riscv,462, GCC,riscv,463,return reload_completed && cfun->machine->frame != NULL; GCC,riscv,464,case REG: GCC,riscv,465,case REG: GCC,riscv,466, GCC,riscv,467, GCC,riscv,468,frame->arg_pointer_offset = offset + crtl->args; GCC,riscv,469, GCC,riscv,470, GCC,riscv,471, GCC,riscv,472, GCC,riscv,473,"insn = gen_add3_insn ( stack_pointer_rtx , stack_pointer_rtx , GEN_INT ( - step1 ) ) ; RTX_FRAME_RELATED_P ( emit_insn ( insn ) ) = ; size -= step1 ; riscv_for_each_saved_reg ( size , riscv_save_reg ) ; } frame -> mask = mask ; if ( frame_pointer_needed ) { insn = gen_" GCC,riscv,474,"default_file_start ( ) ; fprintf ( asm_out_file , , ( flag_pic ? : ) );" GCC,riscv,475,static void riscv_file_start ( void ) { GCC,riscv,476,return max_first_step; GCC,riscv,477, GCC,riscv,478,return x; GCC,riscv,479,"static rtx riscv_force_binary ( enum machine_mode mode , enum rtx_code code , rtx x , rtx y ) { rtx result = gen_rtx_fmt_ee ( code , mode , x , y ); return result; }" GCC,riscv,480,y ); } GCC,riscv,481,"offset = cfun -> machine -> frame . fp_sp_offset - sp_offset ; for ( int regno = FP_REG_FIRST ; regno <= FP_REG_LAST ; regno ++ ) if ( BITSET_P ( cfun -> machine -> frame . fmask , regno - FP_REG_FIRST ) ) { enum machine_mode mode = TARGET_DOUBLE_FLOAT ? DFmode : SFmode ; riscv_save_restore_reg ( mode , regno , offset , fn ) ;" GCC,riscv,482,alignment ) ; GCC,riscv,483,if ( TARGET_SAVE_RESTORE ) return TARGET_SAVE_RESTORE; GCC,riscv,484,"} memset ( & args , , sizeof args ) ; return riscv_get_arg_info ( & info , & args , mode , type , true , true ) ;" GCC,riscv,485,"MODE_VECTOR_FLOAT : return riscv_pass_fpr_pair ( mode , fregno , GET_MODE_INNER ( mode ) , , fregno + , GET_MODE_INNER ( mode ) , ) ; default : gcc_unreachable ( ) ; } } if ( ( info -> num_gprs = riscv_pass_aggregate_in_gpr_pair_p ( type , fields ) ) && info -> gpr_offset" GCC,riscv,486,"memset(info, 0, sizeof(*info));" GCC,riscv,487,mode ) != MODE_COMPLEX_FLOAT ) return false ; } return true ; } GCC,riscv,488, GCC,riscv,489,return ( GET_MODE_SIZE ( mode ) + UNITS_PER_FP_REG - ); GCC,riscv,490,"static bool riscv_legitimate_address_p ( enum machine_mode mode , rtx x , bool strict_p ) { struct riscv_address_info addr ; return riscv_classify_address ( & addr , x ) && riscv_legitimate_address_outer_p ( mode , addr , strict_p ); }" GCC,riscv,491,struct riscv_address_info addr; GCC,riscv,492,rtx x) { if (GET_CODE (x) == CONST_INT) { HOST_WIDE_INT val = INTVAL (x); if (val >= 0 && val < 64) return true; } return false; } GCC,riscv,493, GCC,riscv,494,return x; GCC,riscv,495,"riscv_emit_move(dest, riscv_legitimize_tls_address(src));" GCC,riscv,496, GCC,riscv,497, GCC,riscv,498,"return (tune_info -> memory_cost + memory_move_secondary_cost(mode, rclass));" GCC,riscv,499,"x = GEN_INT (codes[NUM_LIT].value); First, you should check the documentation for the `GEN_INT` function to see what it does and how" GCC,riscv,500,"x = GEN_INT ( codes [ ] . value ) ; for ( i = ; i < num_ops ; i ++ ) { if ( ! can_create_pseudo_p ( ) ) x = riscv_emit_set ( temp , x ) ; else x = force_reg ( mode , x ) ; x = gen_rtx_fmt_ee ( codes [ i ] . code , mode , x , GEN_INT ( codes [ i ] . value ) )" GCC,riscv,501,"reload_completed = ; emit_note ( NOTE_INSN_PROLOGUE_END ) ; fnaddr = gen_rtx_MEM ( FUNCTION_MODE , XEXP ( DECL_RTL ( function ) , ) ) ; temp1 = gen_rtx_REG ( Pmode , RISCV_PROLOGUE_TEMP_REGNUM ) ; temp2 = gen_rtx_REG ( Pmode , STATIC_CHAIN_" GCC,riscv,502,"static const struct riscv_cpu_info * riscv_parse_cpu ( const char * cpu_string ) { for ( unsigned i = 0; i < ARRAY_SIZE ( riscv_cpu_info_table ); i ++ ) if ( strcmp ( riscv_cpu_info_table [ i ] . name , cpu_string ) == 0 ) return riscv_cpu_info_table + i ; error ( ""Unknown CPU string %s"", cpu_string ); }" GCC,riscv,503, GCC,riscv,504,continue; GCC,riscv,505,struct riscv_arg_info info ; GCC,riscv,506, GCC,riscv,507,GEN_INT ( offset2 ) ) ) ); } GCC,riscv,508,"static rtx riscv_pass_fpr_single ( enum machine_mode type_mode , unsigned regno , enum machine_mode value_mode ) { rtx x = gen_rtx_REG ( value_mode , regno ); return x; }" GCC,riscv,509,] ) ; break ; } } GCC,riscv,510,"output_operand_lossage ( , letter ) ; fputs ( reg_names [ GP_REG_FIRST ] , file ) ; break ; }" GCC,riscv,511, GCC,riscv,512, GCC,riscv,513, GCC,riscv,514,regno = reg_renumber[regno]; GCC,riscv,515, GCC,riscv,516,bool might_clobber = crtl->saves_all_registers || df_regs_ever_live_ GCC,riscv,517, GCC,riscv,518,"fn ( gen_rtx_REG ( mode , regno ) , mem );" GCC,riscv,519,"set_mem_alias_set ( mem , get_varargs_alias_set ( ) ) ; emit_insn ( gen_rtx_USE ( VOIDmode , mem ) ) ; } }" GCC,riscv,520,return true; GCC,riscv,521, GCC,riscv,522,"static rtx riscv_unspec_offset_high ( rtx temp , rtx addr , enum riscv_symbol_type symbol_type ) { addr = gen_rtx_HIGH ( Pmode , riscv_unspec_address ( temp , addr , symbol_type ) ); }" GCC,riscv,523,static bool riscv_use_save_libcall ( const struct riscv_frame_info *frame_info) { if (frame_info->abi == RISCV_ABI_LP64D || frame_info->abi == RISCV_ABI_LP64) { return true; } else { return false; } } GCC,riscv,524, GCC,riscv,525,if ( ! strict_p && GET_CODE ( x ) == SUBREG ) GCC,riscv,526,mode ) ); GCC,riscv,527,if ( riscv_symbol_insns ( sym_type ) == ) return false ; if ( ! riscv_split_symbol_type ( sym_type ) ) return false ; GCC,riscv,528, GCC,riscv,529,operand ) ) ) if ( GET_MODE_SIZE ( mode ) > UNITS_PER_WORD && ! SMALL_OPERAND ( INTVAL ( operand ) ) ) GCC,riscv,530, GCC,riscv,531,return n; GCC,riscv,532,"riscv_get_arg_info(&arg, get_cumulative_args(cum), mode, type, named);" GCC,riscv,533, GCC,riscv,534,"case MEM : info -> type = ADDRESS_MEM ; info -> reg = x ; info -> offset = const0_rtx ; return riscv_valid_memory_address_p ( info -> reg , mode , strict_p ) ; default : info -> type = ADDRESS_INVALID ; info -> reg = x ; info -> offset = const0_rtx ; return false ; }" GCC,riscv,535,frame -> arg_pointer_offset = offset - crtl -> args . pretend_args_size ; GCC,riscv,536,riscv_emit_stack_tie ( ) ; GCC,riscv,537,RTX_FRAME_RELATED_P ( insn ) = ; } GCC,riscv,538, GCC,riscv,539,static void riscv_file_start ( void ) { GCC,riscv,540, GCC,riscv,541,cum->num_fprs = info.fpr_offset; GCC,riscv,542,cum->num_fprs = info.num_fprs; GCC,riscv,543,if ( TARGET_SAVE_RESTORE ) return false ; GCC,riscv,544,"return gen_rtx_REG ( mode, gpr_base + info );" GCC,riscv,545, GCC,riscv,546,"static rtx riscv_legitimize_address ( rtx x , rtx oldx ATTRIBUTE_UNUSED , machine_mode mode ) { rtx addr ; if ( riscv_tls_symbol_p ( x ) ) return riscv_legitimize_tls_address ( x ) ; if ( riscv_split_symbol ( NULL , x , mode , & addr ) ) return addr ; return x ; }" GCC,riscv,547,return; } GCC,riscv,548,return true; GCC,riscv,549,x = GEN_INT ( codes [ ] . value ) ; GCC,riscv,550,"if ( riscv_preferred_stack_boundary_arg ) { int min = ctz_hwi ( STACK_BOUNDARY / ) ; int max = ; if ( ! IN_RANGE ( riscv_preferred_stack_boundary_arg , min , max ) ) error ( , riscv_preferred_stack_boundary_arg , ) ; }" GCC,riscv,551,"if ( src_code == REG && FP_REG_P ( REGNO ( src ) ) ) { if ( dest_code == REG && FP_REG_P ( REGNO ( dest ) ) ) return dbl_p ? ""movsd"" : ""movss"" ; if ( dest_code == MEM ) return dbl_p ? ""movsd"" : ""movss"" ; } } if ( src_code == MEM && FP_REG_P ( REGNO ( dest ) ) ) { if ( dest_code == REG ) return" GCC,riscv,552,"return ""riscv_move_1_insn_fn"";" GCC,riscv,553,"x = gen_rtx_PARALLEL ( type_mode , gen_rtvec ( , x ) ) ;" GCC,riscv,554,cfun->machine->naked_p = riscv_naked_function_p; GCC,riscv,555,if ( decl == NULL_TREE || current_function_decl == NULL_TREE || current_function_decl == error_mark_node || ! cfun -> machine ) return ; cfun -> machine -> naked_p = riscv_naked_function_p ( decl ); GCC,riscv,556, GCC,riscv,557, GCC,riscv,558, GCC,riscv,559,return false; GCC,riscv,560, GCC,riscv,561,bool riscv_epilogue_uses ( unsigned int regno GCC,riscv,562,return call_saved && might_clobber; GCC,riscv,563, GCC,riscv,564,"mode , false ) + 1 ;" GCC,riscv,565,"int riscv_address_insns ( rtx x , machine_mode mode , bool might_split_p ) { struct riscv_address_info addr = { } ; int n = ; if ( ! riscv_classify_address ( & addr , x , mode , false ) ) { return ; } if ( mode != BLKmode && might_split_p ) n += ( GET_MODE_SIZE ( mode ) + UNITS_PER_WORD - ) / UNITS_PER" GCC,riscv,566,offset ) ; GCC,riscv,567, GCC,riscv,568, GCC,riscv,569, GCC,riscv,570,"dwarf = alloc_reg_note ( REG_CFA_ADJUST_CFA , adjust_sp_rtx , dwarf ) ;" GCC,riscv,571,<< 32) : 0; } GCC,riscv,572,"static int riscv_binary_cost ( rtx x , int single_insns , int double_insns ) { if ( GET_MODE_SIZE ( GET_MODE ( x ) ) == UNITS_PER_WORD * ) return COSTS_N_INSNS ( double_insns ) ; return COSTS_N_INSNS ( single_insns ) ; }" GCC,riscv,573, GCC,riscv,574,"src , offset , NULL_RTX ) ) ; } for ( i = 0 ; i < length / delta ; i ++ ) { riscv_emit_move ( adjust_address ( dest , i * delta , NULL_RTX ) , regs [ i ] ) ; } }" GCC,riscv,575,"void move_by_pieces (dest, src, length, align)" GCC,riscv,576,if (cost > && (low_part < || mode == HImode)) { GCC,riscv,577,RTL_CONST_CALL_P (insn) = 1; GCC,riscv,578,1. `emit_insn ( riscv_got_load_ GCC,riscv,579,static bool riscv_cannot_copy_insn_p ( rtx_insn *insn) { return (GET_CODE (insn) == CALL_INSN || GET_CODE (insn) == JUMP_INSN || GET_CODE (insn) == BARRIER || GET_CODE (insn) == CODE_LABEL || GET_CODE (insn) == NOTE || GET_CODE (insn) == INSN || GET_CODE (insn) GCC,riscv,580, GCC,riscv,581, GCC,riscv,582,"static bool riscv_can_change_mode_class ( machine_mode , machine_mode , reg_class_t rclass ) { return ! reg_classes_intersect_p ( FP_REGS, rclass ); }" GCC,riscv,583,return (to == HARD_FRAME_POINTER_REGNUM || to == STACK_POINTER_REGNUM); GCC,riscv,584,return ( reload_completed && cfun -> machine -> frame . total_size == && cfun -> machine -> frame . total_size == cfun -> machine -> frame . total_size); GCC,riscv,585,bool riscv_can_use_return_insn ( void ) { return ( reload_completed && cfun -> machine -> frame . total_size == && ! cfun -> machine -> frame . initial_sp_offset ); } GCC,riscv,586,return RISCV_SYMBOL_TLS; GCC,riscv,587,return riscv_classify_symbol ( x ); GCC,riscv,588,static unsigned char riscv_class_max_nregs ( reg_class GCC,riscv,589,FP_REG_FIRST + ) ) ); GCC,riscv,590,frame->arg_pointer_offset = offset - crtl->args.pretend_args_size; GCC,riscv,591, GCC,riscv,592,&& ( TREE_CODE ( exp ) == STRING_CST || TREE_CODE ( exp ) == CONSTRUCTOR ) && ( riscv_align GCC,riscv,593, GCC,riscv,594,") ; s = get_section ( name , SECTION_WRITE | SECTION_CODE | SECTION_LINKONCE , NULL ) ; } } return s ; }" GCC,riscv,595, GCC,riscv,596,"return riscv_emit_set ( dest , gen_rtx_fmt_ee ( code , GET_MODE ( dest ) , x , y ) );" GCC,riscv,597,rtx y) GCC,riscv,598,"* op0 = riscv_force_binary (word_mode, fp_code, cmp_op0, cmp_op1);" GCC,riscv,599,"riscv_emit_int_order_test ( code , invert_ptr , target , cmp0 , cmp1 ) ; } else { rtx inv_target = riscv_force_binary ( GET_MODE ( target ) , code , cmp0 , cmp1 ) ; riscv_emit_int_order_test ( inv_code , invert_ptr , inv_target , cmp1 , cmp0 ) ; } } }" GCC,riscv,600,"static rtx riscv_emit_set ( rtx dest, rtx src, machine_mode mode, rtx cond) { rtx result; result = gen_rtx_SET (dest, src); if (cond != NULL_RTX) { result = gen_rtx_IF_THEN_ELSE (mode, cond, result, pc_rtx); } return result; }" GCC,riscv,601,"static rtx riscv_emit_set ( rtx target , rtx src ) { emit_insn ( gen_rtx_SET ( target , src ) ); }" GCC,riscv,602,if ( regno == RETURN_ADDR_REGNUM ) return true ; if ( epilogue_completed && cfun -> machine -> interrupt_handler_p ) { if ( df_regs_ever_live_p ( regno ) || ( ! crtl -> is_leaf && call_used_or_fixed_reg_p ( regno ) ) ) return true ; return false ; } GCC,riscv,603,"emit_jump_insn (gen_condjump (condition, label));" GCC,riscv,604, GCC,riscv,605,"( step2 ) ) ) ; rtx dwarf = NULL_RTX ; rtx cfa_adjust_rtx = gen_rtx_PLUS ( Pmode , stack_pointer_rtx , GEN_INT ( step2 ) ) ; dwarf = alloc_reg_note ( REG_CFA_DEF_CFA , cfa_adjust_rtx , dwarf ) ; RTX_FRAME_RELATED_P ( insn ) = ; REG_NOTES ( insn ) =" GCC,riscv,606,"void riscv_expand_float_scc ( rtx target , enum rtx_code code , rtx op0 , rtx op1 ) { riscv_emit_float_compare ( & code , & op0 , & op1 ) ; rtx cmp = riscv_force_binary ( word_mode , code , op0 , op1 ) ; }" GCC,riscv,607,if (code == EQ || code == NE) { GCC,riscv,608,RTX_FRAME_RELATED_P ( insn ) = 1; GCC,riscv,609, GCC,riscv,610,COSTS_N_INSNS ( ) ; if ( GET_MODE ( op ) == SImode ) return COSTS_N_INSNS ( ) ; if ( GET_MODE ( op ) == DImode ) return COSTS_N_INSNS ( ) ; return COSTS_N_INSNS ( ) ; } } } GCC,riscv,611, GCC,riscv,612,"return riscv_flatten_aggregate_field ( type , fields , );" GCC,riscv,613,"return riscv_flatten_aggregate_field ( type , fields , , , ignore_zero_width_bit_field_p );" GCC,riscv,614,"n = riscv_flatten_aggregate_field ( TREE_TYPE ( f ) , fields , n , pos , ignore_zero_width_bit_field_p ) ; } if ( n < ) return - ; } return n ; case ARRAY_TYPE : { HOST_WIDE_INT n_elts ; riscv_aggregate_field subfields [ ] ; tree index = TYPE_DOMAIN ( type ) ;" GCC,riscv,615,"static rtx riscv_force_binary ( machine_mode mode , enum rtx_code code , rtx x , rtx y ) { return riscv_emit_binary ( code , gen_reg_rtx ( mode ) , x , y ); }" GCC,riscv,616,if ( can_create_pseudo_p ( ) && ! in_splitter ) return create_pseudo_register ( ); GCC,riscv,617,"for ( unsigned int regno = FP_REG_FIRST ; regno <= FP_REG_LAST ; regno ++ ) if ( BITSET_P ( cfun -> machine -> frame . mask , regno - FP_REG_FIRST ) ) { bool handle_reg = TRUE ; if ( epilogue && ! maybe_eh_return && crtl -> calls_eh_return ) { unsigned int i , regnum ; for ( i = ; ( regnum = EH_RETURN_DATA_REGNO ( i" GCC,riscv,618,RTX_FRAME_RELATED_P (set)); GCC,riscv,619,struct riscv_arg_info info; GCC,riscv,620, GCC,riscv,621,cum->num_fprs = info.fpr_offset + info.fpr_size; GCC,riscv,622,alignment ) ; GCC,riscv,623, GCC,riscv,624, GCC,riscv,625,) ; GCC,riscv,626,") ; case MODE_COMPLEX_FLOAT : return gen_rtx_REG ( mode , fregno [/INST] ) ; default : gcc_unreachable ( ) ; } if ( ( info -> num_gprs = riscv_pass_mode_in_gpr_p ( mode ) ) && info -> gpr_offset + info -> num_gprs <= MAX_ARGS_IN_REGISTERS ) switch ( GET_MODE_CLASS ( mode ) ) { case MODE_INT : return gen_rtx_REG" GCC,riscv,627, GCC,riscv,628,"return gen_got_load_tls_gdsi ( dest , sym );" GCC,riscv,629,"else return gen_got_load_tls_gdhi ( dest , sym );" GCC,riscv,630,"return gen_got_load_tls_iesi ( dest , sym );" GCC,riscv,631,"if ( Pmode == DImode ) return gen_got_load_tls_iedi ( dest , sym ) ; else return gen_got_load_tls_iesi ( dest , sym ) ;" GCC,riscv,632,") return false ; } else if ( GET_CODE ( elt ) != UNSPEC_VOLATILE || GET_CODE ( XVECEXP ( elt , , ) ) != CONST_INT ) return false ; } return true ; }" GCC,riscv,633, GCC,riscv,634, GCC,riscv,635, GCC,riscv,636,to_regno ATTRIBUTE_UNUSED ) GCC,riscv,637, GCC,riscv,638,else if (from == ARG_POINTER_REGNUM) src = cfun->machine->frame.arg_pointer_offset; GCC,riscv,639,machine_function * GCC,riscv,640,static struct machine_function * riscv_init_machine_status ( void ) { return ggc_cleared_alloc < machine_function > ( sizeof ( struct machine_function ) ); } GCC,riscv,641,"static bool riscv_interrupt_type_p ( tree type ) { return lookup_attribute ( ""interrupt"" , TYPE_ATTRIBUTES ( type ) ); }" GCC,riscv,642,if (TREE_CODE(x) == VAR_DECL && DECL_SECTION_NAME(x)) { GCC,riscv,643,static int riscv_issue_rate ( void ) { return tune_param [UNDEFINED]; } GCC,riscv,644,return tune_param[0] GCC,riscv,645,"static bool riscv_legitimate_address_p ( machine_mode mode , rtx x , bool strict_p ) { struct riscv_address_info info; memset (&info, 0, sizeof (info)); riscv_analyze_address (x, &info); return riscv_legitimate_address_p_1 (mode, &info, strict_p); }" GCC,riscv,646,"static bool riscv_legitimate_constant_p ( machine_mode mode ATTRIBUTE_UNUSED , rtx x ) { return riscv_const_insns ( x ); }" GCC,riscv,647,"addr ) ; } return x ; } Next, it checks if `x` is a split symbol, and if so, it calls `riscv" GCC,riscv,648,return reg; GCC,riscv,649, GCC,riscv,650,"tp = gen_rtx_REG ( Pmode , THREAD_POINTER_REGNUM ) ; tmp = gen_reg_rtx ( Pmode ) ; emit_insn ( riscv_got_load_tls_ie ( tmp , loc ) ) ; dest = gen_reg_rtx ( Pmode ) ; emit_insn ( gen_add3_insn ( dest , tmp , tp ) ) ; break ; case TLS_MODEL_LOCAL_EXEC : tmp = riscv_unspec_offset_high ( NULL , gen_rtx" GCC,riscv,651,case TLS_MODEL_LOCAL_EXEC: GCC,riscv,652,case MEMMODEL_RELAXED : return false; GCC,riscv,653,"tune_param -> memory_cost + memory_move_secondary_cost ( mode , tune_param -> secondary_memory_cost , tune_param -> secondary_memory_cost_threshold , tune_param -> secondary_memory_cost_multiplier ) );" GCC,riscv,654,= 32; GCC,riscv,655,mode2 ) == MODE_FLOAT ) ); } GCC,riscv,656,"x = GEN_INT ( codes [ ] . value ) ; for ( i = ; i < num_ops ; i ++ ) { if ( ! can_create_pseudo ) x = riscv_emit_set ( temp , x ) ; else x = force_reg ( mode , x ) ; } } }" GCC,riscv,657,"return NULL_TREE != lookup_attribute(, DECL_ATTRIBUTES(func_decl));" GCC,riscv,658,return new_cost < old_cost; GCC,riscv,659,bool speed = optimize_bb_for_speed_p ( BLOCK_FOR_INSN ( insn ) ) ; GCC,riscv,660,"if ( OPTION_SET_P ( riscv_stack_protector_guard_reg_str ) ) { const char * str = riscv_stack_protector_guard_reg_str ; int reg = decode_reg_name ( str ) ; if ( ! IN_RANGE ( reg , GP_REG_FIRST + , GP_REG_LAST ) ) error ( ) ; }" GCC,riscv,661,unsigned n = riscv_save_libcall_count(mask); GCC,riscv,662, GCC,riscv,663, GCC,riscv,664, GCC,riscv,665,"return ""ld"";" GCC,riscv,666,"const char * riscv_output_return ( ) { if ( cfun -> machine -> naked_p ) return ; return ""ret""; }" GCC,riscv,667,"const char * riscv_output_return ( ) { if ( cfun -> machine -> naked_p ) { return ""ret""; } else { return ""jr ra""; } }" GCC,riscv,668,".name, tune_string ) == 0 ) return &riscv_tune_info_table [ i ] ; return NULL ; }" GCC,riscv,669, GCC,riscv,670, GCC,riscv,671, GCC,riscv,672,"output_addr_const ( file , newop ) ; break ; } default : fprintf ( file , , INTVAL ( op ) ) ; break ; } }" GCC,riscv,673, GCC,riscv,674, GCC,riscv,675,return mode; GCC,riscv,676, GCC,riscv,677, GCC,riscv,678,if ( ! strict_p ) return true ; GCC,riscv,679,static void riscv_reorg ( void ) { GCC,riscv,680,"dwarf = alloc_reg_note ( REG_CFA_DEF_CFA , cfa_adjust_rtx , dwarf ) ;" GCC,riscv,681, GCC,riscv,682,"rtx riscv_return_addr ( int count , rtx frame ATTRIBUTE_UNUSED ) { if ( count != ) { return NULL_RTX; } else { return gen_rtx_REG ( Pmode , RISCV_LINK_REGNUM ); } }" GCC,riscv,683,"args , arg ) ; ```" GCC,riscv,684,"static unsigned riscv_save_libcall_count ( unsigned mask ) { for ( unsigned n = GP_REG_LAST ; n > GP_REG_FIRST ; n -- ) if ( BITSET_P ( mask, n ) ) return n; return 0; }" GCC,riscv,685,riscv_set_frame_expr ( riscv_frame_set ( mem [frame_size] ) ) ); GCC,riscv,686,"fn (gen_rtx_REG (mode, regno), mem);" GCC,riscv,687,rclass) { if (mode == VOIDmode) return false; if (mode == BLKmode) return true; if (GET_MODE_SIZE (mode) > GET_MODE_SIZE (SImode)) return true; if (GET_MODE_SIZE (mode) == GET_MODE_SIZE (SImode)) return false; if (GET_MODE_SIZE (mode) < GET_MODE_SIZE (SImode)) return false; GCC,riscv,688,"gp_saved = MAX_ARGS_IN_REGISTERS - local_cum . num_gprs ; if ( ! no_rtl && gp_saved > ) { rtx ptr = plus_constant ( Pmode , virtual_incoming_args_rtx , REG_PARM_STACK_SPACE ( cfun -> decl ) - gp_saved * UNITS_PER_WORD ) ; rtx mem = gen_frame_mem ( BLKmode ," GCC,riscv,689, GCC,riscv,690,"return g_switch_value && IN_RANGE ( size , 0, 1024 ); Explanation:" GCC,riscv,691,"return riscv_slow_unaligned_access_p (mode, align);" GCC,riscv,692, GCC,riscv,693, GCC,riscv,694,"void riscv_split_doubleword_move ( rtx dest , rtx src ) { rtx low_dest ; low_dest = riscv_subword ( dest , false ) ; if ( REG_P ( low_dest ) && reg_overlap_mentioned_p ( low_dest , src ) ) { rtx high_dest = riscv_subword ( dest , true ) ; if ( REG_P ( high_dest ) && reg_overlap_mentioned_p ( high_dest , src ) ) { rtx tmp = gen_reg_rt" GCC,riscv,695,"unsigned HOST_WIDE_INT hival = sext_hwi ( ( val - loval ) >> , ) ;" GCC,riscv,696,return cost; GCC,riscv,697,return cost; GCC,riscv,698,"* low_out = gen_rtx_LO_SUM ( Pmode, high, addr );" GCC,riscv,699,GEN_INT ( seqno ) ) ) ; return temp ; } GCC,riscv,700,symbol_type == SYMBOL_TLS_IE; GCC,riscv,701,"Assuming that the `UNSPEC_ADDRESS_P` macro returns a non-zero value if the address is a special address, and the `UNSPEC_ADDRESS` macro returns the constant value from the address," GCC,riscv,702,"return adjust_address (op, word_mode, byte);" GCC,riscv,703,"static rtx riscv_swap_instruction ( rtx inst ) { gcc_assert ( GET_MODE ( inst ) == SImode ); return gen_rtx_PARALLEL ( SImode, gen_rtvec ( 2, gen_rtx_SET (VOIDmode, gen_rtx_REG ( SImode, RISCV_TMP_REGNUM ), gen_rtx_REG ( SImode, RISCV_TMP_REGNUM )), gen_rtx_" GCC,riscv,704,"static rtx riscv_swap_instruction ( rtx inst ) { gcc_assert ( GET_MODE ( inst ) == SImode ) ; if ( BYTES_BIG_ENDIAN ) inst = expand_unop ( SImode , bswap_optab , inst ) ; return inst ; }" GCC,riscv,705,"if ( Pmode == DImode ) return gen_tls_add_tp_ledi ( dest , base , tp , sym ) ; else return gen_tls_add_tp_lesi ( dest , base , sym ) ;" GCC,riscv,706, GCC,riscv,707,return SYMBOL_REF_P ( x ) && SYMBOL_REF_TLS_MODEL ( x ) == TLS_MODEL_GLOBAL_DYNAMIC; GCC,riscv,708,"static bool riscv_tls_symbol_p ( const_rtx x ) { if (GET_CODE (x) == SYMBOL_REF) { const char *name = XSTR (x, 0); if (strncmp (name, ""TLS"", 3) == 0) return true; } return false; }" GCC,riscv,709,") ; riscv_emit_move ( mem , riscv_swap_instruction ( jr_lo_func ) ) ; }" GCC,riscv,710,"prefix = one_only ? ""RODATA."" : ""RODATA"";" GCC,riscv,711,"break ; default : break ; } if ( prefix ) { const char * name , * linkonce ; char * string ; name = IDENTIFIER_POINTER ( DECL_ASSEMBLER_NAME ( decl ) ) ; name = targetm . strip_name_encoding ( name ) ; linkonce = one_only ? : ; string = ACONCAT ( ( linkonce , prefix , , name , NULL ) ) ; set_decl" GCC,riscv,712,&offset ); GCC,riscv,713,"if ( offset != const0_rtx ) base = gen_rtx_PLUS ( Pmode , base , offset ) ; return gen_rtx_CONST ( Pmode , base ) ;" GCC,riscv,714,"static rtx riscv_unspec_address_offset ( rtx base , rtx offset , enum riscv_symbol_type symbol_type ) { base = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( 2 , base , offset ) ); }" GCC,riscv,715,"temp , addr , symbol_type ) ); return riscv_unspec_offset ( temp , addr , symbol_type ); }" GCC,riscv,716,if ( ! strict_p GCC,riscv,717,"static bool riscv_valid_lo_sum_p ( enum riscv_symbol_type sym_type , machine_mode mode , rtx x ) { int align , size ; if ( riscv_symbol_insns ( sym_type ) == ) return false ; if ( ! riscv_split_symbol_type ( sym_type ) ) return false ; if ( mode == BLKmode ) { rtx offset ; split_const ( x , & x , & offset ) ; if ( ! SYMBOL_REF_P ( x ) ) return false" GCC,riscv,718,mode ) ; size = GET_MODE_SIZE ( mode ) ; } return true ; } GCC,riscv,719,return true; GCC,riscv,720,static void riscv_va_start (tree valist) GCC,riscv,721,return ! riscv_naked_function_p ( decl ); GCC,riscv,722,"target, 0, OPTAB_LIB_WIDEN);" GCC,riscv,723,case RVV_VXRM: __asm__ __volatile__ ( : ( rv ) : : ) ; break ; GCC,riscv,724,STR_LIT> ) ; break ; case RVV_VXRM : __asm__ __volatile__ ( : : ( value ) : ) ; break ; default : break ; } } GCC,riscv,725,"addr , ) ; * offset = XEXP ( addr , ) ; return true ; } return false ; }" GCC,riscv,726, GCC,riscv,727, GCC,riscv,728, GCC,riscv,729,"void th_mempair_order_operands ( rtx operands [ ] , bool load_p , machine_mode mode ) { int mem_op = load_p ? : ; bool reversed = false; }" GCC,riscv,730,imm2 ) ; GCC,riscv,731,"mem2 ) ; if ( mode == SImode ) format = ""lw"" ; else format = ""ld"" ; } split_plus ( XEXP ( mem1 , 0 ) , & base1 , & offset1 ) ; split_plus ( XEXP ( mem2 , 0 ) , & base2 , & offset2 ) ; gcc_assert ( rtx_equal_p ( base1 , base2 ) ) ; auto size1 = MEM_SIZE ( mem1 ) ; auto size2 = MEM_SIZE ( mem2 ) ; gcc_assert ( known_eq" GCC,riscv,732, GCC,riscv,733,operands [ ] ) ) ; GCC,riscv,734,) ); GCC,arc,0,builtin_define ( TARGET_BIG_ENDIAN ? : ) ; GCC,arc,1,builtin_define ( TARGET_BIG_ENDIAN ? : ) ; GCC,arc,2, GCC,arc,3,"builtin_define_with_int_value ( , arc_lpcwidth )" GCC,arc,4, GCC,arc,5,builtin_define ( ) ; } GCC,arc,6,"if ( def_p ) cpp_define ( pfile , name ) ; else cpp_undef ( pfile , name );" GCC,arc,7,"static void def_or_undef_macro ( cpp_reader * pfile , const char * name , bool def_p ) { if ( def_p ) cpp_define ( pfile , name ) ; else cpp_undef ( pfile , name ); }" GCC,arc,8,") ) Answer: \begin{code} case LABEL_REF : case SYMBOL_REF : case CONST : if ( TARGET_NPS_CMEM && cmem_address ( addr , SImode ) ) return ; return COSTS_N_INSNS ( ) ; case PLUS : { rtx plus0 = XEXP ( addr , ) ; rtx plus1 = XEXP ( addr , ) ;" GCC,arc,9, GCC,arc,10, GCC,arc,11,"if ( arc_lpcwidth != 0 && arc_must_save_register ( LP_COUNT , cfun , true ) ) { rtx reg0 = gen_rtx_REG ( SImode , R0_REG ) ; size_to_deallocate -= pop_reg ( reg0 ) ; emit_move_insn ( gen_rtx_REG ( SImode , LP_COUNT ) , reg0 ) ; size_to_deallocate -= pop_reg ( reg0 ) ; } } if ( size_to_deallocate ) { emit_ins" GCC,arc,12,int neg_intval = -intval; GCC,arc,13,if ( save_fp ) GCC,arc,14, GCC,arc,15,"intval0 = INTVAL ( XVECEXP ( operands [ 0 ] , 0 , 0 ) ) << 16 ;" GCC,arc,16, GCC,arc,17,"if (arc_hazard(insn, succ0) || arc_check_release31a(insn, succ0))" GCC,arc,18,current_insn_set_cc_p = last_insn_set_cc_p; GCC,arc,19, GCC,arc,20,arc_ccfsm_state += ; current_insn_set_cc_p = ; GCC,arc,21,{ } GCC,arc,22,current_frame_info.gmask = gmask; GCC,arc,23,args ) ; GCC,arc,24, GCC,arc,25,"fprintf(FILE, , XSTR(SYMREF, ));" GCC,arc,26, GCC,arc,27,case JUMP_INSN : GCC,arc,28,arc_punct_chars['~'] = ; GCC,arc,29, GCC,arc,30, GCC,arc,31,"fprintf (file, HOST_WIDE_INT_PRINT_DEC , sp_str, sp_str, size - restored);" GCC,arc,32,It GCC,arc,33, GCC,arc,34,if ( AGGREGATE_TYPE_P ( type ) ) return true ; else { HOST_WIDE_INT size = int_size_in_bytes ( type ) ; return ( size == -1 ) ; } GCC,arc,35,type ); if ( AGGREGATE_TYPE_P ( type ) ) return true ; else { HOST_WIDE_INT size = int_size_in_bytes ( type ); if ( AGGREGATE_TYPE_P ( type ) ) return true ; else { HOST_WIDE_INT size = int_size_in_bytes ( type ); if ( AGGREGATE_TYPE_P ( type ) ) return true ; else { HOST_WIDE_INT size = int_size_in_bytes ( type ); if ( AG GCC,arc,36,case LSHIFTRT: GCC,arc,37, GCC,arc,38,"fprintf(file, , op, reg_names[regno], base_reg, offset);" GCC,arc,39,int first_anon_arg; gcc_assert(mode != BLKmode); first_anon_arg = *cum + ((GET_MODE_SIZE(mode) + UNITS_PER_WORD - ) / UNITS_PER_WORD); if (first_anon_arg < MAX_ARC_PARM_REGS && !no_rtl) { int first_reg_offset = first_anon_arg; int size = MAX_ARC_PARM_REGS - first_reg_offset; int GCC,arc,40, GCC,arc,41,CONST_DOUBLE && LEGITIMATE_CONSTANT_P ( op ) ) ); GCC,arc,42,"int call_operand ( rtx op , enum machine_mode mode ) {" GCC,arc,43,return ( GET_CODE ( op ) == CONST_INT && ( INTVAL ( op ) >= ( 0 ) && ( INTVAL ( op ) <= ( 31 ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) GCC,arc,44,CONST_INT && INTVAL ( op ) <= ) ) ; GCC,arc,45,"int const_uint32_operand ( rtx op , enum machine_mode mode ATTRIBUTE_UNUSED ) { return ( GET_CODE ( op ) == CONST_INT && ( INTVAL ( op ) >= 0 && INTVAL ( op ) <= 0xFFFFFFFF ); }" GCC,arc,46, GCC,arc,47, GCC,arc,48,"op , ) , Pmode ) ) { return 0 ; } return 1 ; } }" GCC,arc,49,REG : return ; default : return ; } } GCC,arc,50, GCC,arc,51, GCC,arc,52,op ) ) { return 1; } else if ( GET_CODE ( op ) == MEM && MEM_NOTRAP_P ( op ) ) { return 1; } else if ( GET_CODE ( op ) == MEM && MEM_NONVOLATILE_P ( op ) ) { return 1; } else if ( GET_CODE ( op ) == MEM && MEM_NONIMM_P ( op ) ) { return 1; } else if ( GET_CODE ( op ) == MEM && MEM_NONVOL GCC,arc,53, GCC,arc,54,COND_SET_ZNC : last_insn_set_cc_p = true; break; default : last_insn_set_cc_p = false; break; } } GCC,arc,55,return SMALL_INT ( INTVAL ( op ) ) ; GCC,arc,56,Here is GCC,arc,57,"int symbolic_memory_operand ( rtx op , enum machine_mode mode ATTRIBUTE_UNUSED ) { if ( GET_CODE ( op ) == SUBREG ) op = SUBREG_REG ( op ) ; if ( GET_CODE ( op ) != MEM ) return ; op = XEXP ( op , ) ; return ( GET_CODE ( op ) == SYMBOL_REF || GET_CODE ( op ) == CONST || GET_CODE (" GCC,arc,58,op ) == LABEL_REF ); GCC,arc,59,": return ( ! RTX_OK_FOR_OFFSET_P ( SImode , plus1 ) ? COSTS_N_INSNS ( ) : speed ? : ( satisfies_constraint_Rcq ( plus0 ) && satisfies_constraint_O ( plus1 ) ) ? : ) ; case MULT : return ( ! RTX_OK_FOR_OFFSET_P ( SImode , plus1 ) ? COSTS_N_INSNS (" GCC,arc,60,return len + ; GCC,arc,61,insn ) ; return ( ( LABEL_P ( prev ) || ( TARGET_ARC600 && ( JUMP_P ( prev ) || CALL_P ( prev ) || ( NONJUMP_INSN_P ( prev ) && GET_CODE ( PATTERN ( prev ) ) == SEQUENCE ) ) ) ) ? len + : len ) ; } if ( TARGET_PAD_RETURN && JUMP_P ( insn ) && GET_CODE ( PATTERN ( GCC,arc,62,"static int arc_arg_partial_bytes ( cumulative_args_t cum_v , machine_mode mode , tree type , bool named ATTRIBUTE_UNUSED ) { CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; int bytes = ( mode == BLKmode ? int_size_in_bytes ( type ) : ( int ) GET_MODE_SIZE ( mode ) ) ; int words = ( bytes + UNITS_PER_WORD - 1 ) / UNITS_PER_WORD ; return" GCC,arc,63,ret = GPR_REST_ARG_REGS ( arg_num ) ; GCC,arc,64,switch_to_section( GCC,arc,65,insn ); GCC,arc,66,if ( NONJUMP_INSN_P ( insn ) ? ( GET_CODE ( PATTERN ( insn ) ) == USE || GET_CODE ( PATTERN ( insn ) ) == CLOBBER ) : JUMP_P ( insn ) ) GCC,arc,67,"static bool arc_can_eliminate ( const int from ATTRIBUTE_UNUSED , const int to ATTRIBUTE_UNUSED ) { return false; }" GCC,arc,68,"static bool arc_can_eliminate ( const int from ATTRIBUTE_UNUSED , const int to ATTRIBUTE_UNUSED ) { return false; }" GCC,arc,69, GCC,arc,70, GCC,arc,71, GCC,arc,72,frame_info->gmask = gmask; GCC,arc,73, GCC,arc,74,static bool arc_decl_anon_ns_mem_p ( const_tree decl ) { while ( ) { if ( decl == NULL_TREE || decl == error_mark_node ) return false ; if ( TREE_CODE ( decl ) == NAMESPACE_DECL && DECL_NAME ( decl ) == NULL_TREE ) return true ; decl = DECL_CONTEXT ( decl ) ; } return false ; } GCC,arc,75, GCC,arc,76,int arc_decl_pretend_args ( tree decl ) { gcc_assert ( decl == current_function_decl ); GCC,arc,77, GCC,arc,78,"GET_CODE ( XEXP ( x , ) ) == CONST &&" GCC,arc,79,SYMBOL_REF_FLAGS (symbol) = flags; GCC,arc,80,return regno == arc_return_address_regs[cfun->machine->fn_type]; GCC,arc,81,"addr, first_offset ) ) ; } if ( size_to_deallocate > 0 ) { frame_stack_add ( size_to_deallocate ) ; } if ( epilogue_delay_slots ) { emit_jump_insn ( gen_epilogue_delay_slots ( size_to_deallocate ) ) ; } emit_jump_insn ( gen_epilogue_return ( ) ) ; epilogue_done : ; }" GCC,arc,82,return false; GCC,arc,83, GCC,arc,84,"( - frame_size_to_allocate ) ) ; emit_insn ( gen_rtx_SET ( stack_pointer_rtx , addr ) ) ; }" GCC,arc,85, GCC,arc,86, GCC,arc,87,static bool arc_frame_pointer_required ( void ) { return cfun -> uses_frame_pointer; } GCC,arc,88,static bool arc_frame_pointer_required (void) { #if defined(__ARC__) && defined(__ARC_FP_REGISTERS) return true; #else return false; #endif } GCC,arc,89, GCC,arc,90,"static void arc_function_arg_advance ( cumulative_args_t cum_v , machine_mode mode , const_tree type , bool named ATTRIBUTE_UNUSED ) {" GCC,arc,91, GCC,arc,92,} else if (strcmp(TREE_STRING_POINTER( GCC,arc,93,if ( recog_memoized ( succ ) == CODE_FOR_doloop_end_i && ( JUMP_P ( pred ) || CALL_P ( pred ) || GET_CODE ( PATTERN ( pred ) ) == RETURN ) ) GCC,arc,94,"if ( flag_delayed_branch ) { opt_pass * pass_arc_predicate_delay_insns = make_pass_arc_predicate_delay_insns ( g ) ; struct register_pass_info arc_predicate_delay_insns_info = { pass_arc_predicate_delay_insns , , , PASS_POS_INSERT_BEFORE } ; register_pass ( & arc_predicate_delay_insns" GCC,arc,95, GCC,arc,96,stack_adjustment ) ); GCC,arc,97,"void_ftype_usint_usint , ARC_BUILTIN_CORE_WRITE ) ; def_mbuiltin ( , , void_ftype_usint_usint , ARC_BUILTIN_CORE_WRITE ) ; def_mbuiltin ( , , void_ftype_usint_usint , ARC_BUILTIN_CORE_WRITE ) ; def_mbuiltin ( " GCC,arc,98, GCC,arc,99,machine->force_short_suffix = -NUM_LIT; GCC,arc,100,arc_mode_class[i] = << (int) XF_MODE; GCC,arc,101,int GCC,arc,102,if ( TREE_THIS_VOLATILE ( decl ) ) GCC,arc,103,return align_ GCC,arc,104,return false; GCC,arc,105,case LABEL_REF: case SYMBOL_REF: return false; GCC,arc,106,"} return ( GET_CODE ( addr ) == UNSPEC && XVECLEN ( addr , ) == && XINT ( addr , ) == ARC_UNSPEC_GOT && GET_CODE ( XVECEXP ( addr , , 0 ) ) == SYMBOL_REF );" GCC,arc,107, GCC,arc,108,"Pmode , inner ) ; else inner = gen_rtx_PLUS ( Pmode , XEXP ( addr , ) , inner ) ; addr = gen_rtx_PLUS ( Pmode , XEXP ( addr , ) , inner ) ; } else if ( GET_CODE ( addr ) == PLUS && REG_P ( XEXP ( addr , ) ) && ( INTVAL ( XEXP ( addr , ) ) & " GCC,arc,109,"if ( GET_CODE ( addr ) == CONST ) { addr = XEXP ( addr , ) ; if ( GET_CODE ( addr ) == UNSPEC ) { pat = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( , addr ) , ARC_UNSPEC_GOT ) ; pat = gen_rtx_CONST ( Pmode , pat ) ; pat = gen_const_mem ( Pmode , pat ) ; if ( oldx == " GCC,arc,110,static bool arc_lra_p ( void ) { GCC,arc,111, GCC,arc,112,int intval = (REG_P (operands []) ? ; } if ( final_sequence && ! INSN_ANNULLED_BRANCH_P ( insn ) && ( get_attr_cond ( insn ) != COND_USE || ! reg_set_p ( gen_rtx_REG ( CCmode , CC_REG ) , XVECEXP ( final_sequence , , ) ) ) ) { prev = as_a < rtx_insn * >" GCC,arc,116,return ( type != && ( TREE_CODE ( TYPE_SIZE ( type ) ) != INTEGER_CST || TREE_ADDRESSABLE ( type ) ) ); GCC,arc,117,"static bool arc_pass_by_reference (cumulative_args_t ca_v, machine_mode mode)" GCC,arc,118,"enum reg_class arc_preferred_reload_class ( rtx x, enum reg_class cl ) {" GCC,arc,119,return (cl == CHEAP_CORE_REGS) || (cl == WRITABLE_CORE_REGS); GCC,arc,120, GCC,arc,121, GCC,arc,122,afi->save_return_addr : 0; GCC,arc,123, GCC,arc,124,"if ( GET_CODE ( x ) == PLUS ) { if ( GET_CODE ( XEXP ( x , 0 ) ) == CONST_INT ) x = XEXP ( x , 1 ); }" GCC,arc,125,"* total = (rtx_cost(XEXP(op0, 0), SET, 0, speed) + rtx_cost(XEXP(op0, 1), SET, 0, speed));" GCC,arc,126,"offset ) ) ; addr = plus_constant ( Pmode , base_reg , offset ) ; } mem = gen_frame_mem ( SImode , addr ) ; insn = gen_rtx_SET ( VOIDmode , mem , reg ) ; frame_insn ( insn ) ; offset += UNITS_PER_WORD ; } } } }" GCC,arc,127, GCC,arc,128,if ( ( cl == LPCOUNT_REG || cl == WRITABLE_CORE_REGS ) && in_p && MEM_P ) GCC,arc,129,machine_mode mode = GET_MODE ( x ) ; rtx x1 ; if ( GET_MODE_CLASS ( mode ) == MO GCC,arc,130,if (first_anon_arg < MAX_ARC_PARM_REGS) { GCC,arc,131,"void arc_set_default_type_attributes ( tree type, tree attributes ) { type->default_type_attributes = attributes; }" GCC,arc,132, GCC,arc,133,"static rtx arc_trampoline_adjust_address ( rtx addr ) { return plus_constant ( Pmode , addr , 4 ); }" GCC,arc,134,if ( ( mode == V4SImode ) || ( mode == V8HImode ) ) GCC,arc,135, GCC,arc,136,"pat, 0, 0 ) ) : SET_DEST ( pat ) ) ; return dest ; }" GCC,arc,137, GCC,arc,138,case CONST_INT: return true; default: return false; } } GCC,arc,139,"""1"";" GCC,arc,140,"fatal_error ( input_location , ""Invalid operand for constant"" ) ;" GCC,arc,141,size = GET_MODE_SIZE ( mode ) ; GCC,arc,142,"pat = gen_rtx_SET ( VOIDmode, dst, gen_rtx_fmt_ee ( GET_CODE ( src ), GET_MODE ( src ), src1, src0 ) ) ; } } if ( RTX_FRAME_RELATED_P ( insn ) ) { gcc_assert ( annulled [INST] The code snippet is checking if the instruction is a commutative operation, and if it is, it is checking if the first operand is a register and the second operand is the" GCC,arc,143, ] ) ; } GCC,arc,144,rtx temp = reload_in_progress ? operands[NUM_LIT] : gen_reg_rtx (Pmode); GCC,arc,145,"static void emit_store_direct ( rtx block , int offset , rtx value ) { rtx addr = gen_rtx_PLUS ( Pmode , block , GEN_INT ( offset ) ); emit_move_insn ( addr , value ); }" GCC,arc,146,"SImode, value ) ) ); } Next, the function forces `value` to" GCC,arc,147,"iter->second; Inside the loop, the code is using the `const_rtx` type to store the current element of the array. The `" GCC,arc,148,"src , int n , int dir , int size , int align ) { if (n <= 0) return dst; if (dir == 1) { if (size == 8) emit_insn (gen_movdi (dst, src)); else if (size == 4) emit_insn (gen_movsi (dst, src)); else if (size == 2) emit_insn (gen_movhi (dst, src)); else if (size ==" GCC,arc,149,src)); GCC,arc,150,"tmp ; } if ( GET_MODE_CLASS ( cmode ) == MODE_FLOAT && TARGET_OPTFPE ) { rtx op0 = gen_rtx_REG ( cmode , ) ; rtx op1 = gen_rtx_REG ( cmode , GET_MODE_SIZE ( cmode ) / UNITS_PER_WORD ) ; switch ( code ) { case NE : case EQ : case GT : case UNLE : case GE : case UNLT : case UNEQ : case LTGT : case" GCC,arc,151, GCC,arc,152, GCC,arc,153, GCC,arc,154,"mode ) ; if ( pat ) { pat = change_address ( operands [ ] , mode , pat ) ; MEM_COPY_ATTRIBUTES ( pat , operands [ ] ) ; operands [ ] = pat ; } } } if ( MEM_P ( operands [ ] ) && ! cse_not_expected ) { rtx pat = XEXP ( operands [ ] , )" GCC,arc,155, GCC,arc,156,"XSTR ( XVECEXP ( u , , ) , ) ) : s1 -> code ) ) ;" GCC,arc,157, GCC,arc,158, GCC,arc,159,args ) ; GCC,arc,160, GCC,arc,161,"stack_pointer_rtx ) ; cfa_adjust = - UNITS_PER_WORD ; first_offset = ; } else { addr = gen_rtx_PRE_DEC ( Pmode , stack_pointer_rtx ) ; cfa_adjust = - UNITS_PER_WORD ; first_offset = ; } emit_insn ( gen_movsi ( ra , addr ) ) ; if ( cfa_adjust ) { cfa_adjust = - cfa_adjust ; emit_" GCC,arc,162,"( ra_offs ) ; cfa_adjust = ra_offs ; first_offset = ; size_to_deallocate -= cfun -> machine -> frame_info . reg_size ; } else if ( ! ra_offs && size_to_deallocate == UNITS_PER_WORD ) { addr = gen_rtx_POST_INC ( Pmode , addr ) ; cfa_adjust = GET_MODE_SIZE ( Pmode ) ; size_to_deallocate = ; } insn =" GCC,arc,163,"src_addr = plus_constant ( Pmode , src_addr , piece ) ;" GCC,arc,164, GCC,arc,165,* no_add_attrs = true ; GCC,arc,166, GCC,arc,167,arc_init_reg_tables(); GCC,arc,168,if ( flag_no_common == ) flag_no_common = !flag_no_common; GCC,arc,169,"base ) ) ; if ( index ) { fprintf ( file , , index ) ; } fprintf ( file , , base ) ; break ; case MULT : index = XEXP ( addr , ) ; base = XEXP ( addr , ) ; gcc_assert ( OBJECT_P ( base ) ) ; fprintf ( file , , index ) ; fprintf ( file , , base ) ; break ; default : gcc" GCC,arc,170, GCC,arc,171,"DFmode , ) ; emit_insn ( gen_rtx_SET ( dest , gen_rtx_UNSPEC_VOLATILE ( Pmode , gen_rtvec ( , srcHigh , srcLow ) , VUNSPEC_ARC_SR_HIGH ) ) ) ; emit_insn ( gen_rtx_SET ( dest , gen_rtx_UNSPEC_VOLATILE ( Pmode , gen_rtvec ( " GCC,arc,172,"add_int_reg_note (insn, REG_BR_PROB, 100);" GCC,arc,173, GCC,arc,174, GCC,arc,175, GCC,arc,176,operands [ ] ) ; if ( pat != operands [ ] ) { operands [ ] = pat ; } } } } } GCC,arc,177,"case SYMBOL_REF : case CONST : if ( TARGET_NPS_CMEM && cmem_address ( addr , SImode ) ) return ; return COSTS_N_INSNS ( ) ; case PLUS : { register rtx plus0 = XEXP ( addr , ) ; register rtx plus1 = XEXP ( addr , ) ; if ( GET_CODE ( plus" GCC,arc,178,static unsigned int arc_autovectorize_vector_sizes (void) { unsigned int vector_sizes = 0; vector_sizes |= 1 << 16; vector_sizes |= 1 << 32; vector_sizes |= 1 << 64; return vector_sizes; } GCC,arc,179,return TARGET_PLUS_QMA GCC,arc,180,fail = TRUE ; GCC,arc,181," ) , ) ) == UNSPEC && XINT ( u , ) == ARC_UNSPEC_GOTOFF ) return XVECEXP ( u , , ) ; else return x ; }" GCC,arc,182,"1. The function first checks if `x` is a `PLUS` expression with a specific structure. If it is, it extracts the `REG` and `CONST` parts of the expression and stores them in `gp`" GCC,arc,183, GCC,arc,184,"pat = gen_rtx_SET ( baseptr_rtx , pat ) ;" GCC,arc,185,register_pass ( & arc_ifcvt4_info ) ; GCC,arc,186,register_pass ( &arc_ifcvt5_info ); GCC,arc,187,case MODE_VECTOR_INT : if ( GET_MODE_SIZE ( m ) == ) arc_mode_class [ i ] = ( << ( int ) S_MODE ) ; else if ( GET_MODE_SIZE ( m ) == ) arc_mode_class [ i ] = ( << ( int ) D_MODE ) ; else arc_mode_class [ i ] = ( << ( int ) V_MODE ) ; break ; case MO GCC,arc,188,CODE_FOR_doloop_end_i ) return align_labels_log ; } return align_labels_log ; } GCC,arc,189,if ( ( GET_MODE_SIZE ( mode ) != ) && CONSTANT_P ( x ) ) { GCC,arc,190,") ; if ( GET_CODE ( x ) == PLUS ) { if ( flag_pic ? GET_CODE ( XEXP ( x , ) ) != CONST_INT : ! arc_legitimate_constant_p ( mode , XEXP ( x , ) ) ) return false ; x = XEXP ( x , ) ; } } if ( GET_CODE ( x ) == SYMBOL_REF ) return true ; if ( GET_CODE ( x ) == LABEL_REF )" GCC,arc,191, GCC,arc,192,bool arc_legitimate_pc_offset_p ( rtx addr ) { if ( GET_CODE ( addr ) != CONST ) return false ; return arc_needs_pcl_p ( addr ) ; } GCC,arc,193, GCC,arc,194,return new_x; GCC,arc,195,"base_name = DTPOFF_ZERO_SYM ; if ( decl && bss_initializer_p ( decl ) ) base_name = ; base = gen_rtx_SYMBOL_REF ( Pmode , base_name ) ; if ( strcmp ( base_name , DTPOFF_ZERO_SYM ) == ) { if ( ! flag_pic ) goto local_exec ; v = gen_rtvec ( ] , temp , Pmode ) ; } }" GCC,arc,209,); } GCC,arc,210,frame_info->gmask = gmask; GCC,arc,211,gcc_assert ( crtl -> args.pretend_args_size == 0 ) ; GCC,arc,212,if ( ! fixed_regs [ regno ] ) GCC,arc,213,"stack_pointer_rtx ; insn = frame_move_inc ( ra , gen_frame_mem ( Pmode , addr ) , stack_pointer_rtx , ) ; add_reg_note ( insn , REG_CFA_RESTORE , ra ) ; add_reg_note ( insn , REG_CFA_DEF_CFA , plus_constant ( SImode , stack_pointer_rtx , cfa_adjust ) ) ; size_to_deallocate -= UNITS_PER_WORD ;" GCC,arc,214,"dst_addr , size , ) ; src_addr = force_offsettable ( XEXP ( operands [ ] , ) , size , ) ; src_addr = force_offsettable ( XEXP ( operands [ ] , ) , size , ) ; src_addr = force_offsettable ( XEXP ( operands [ ] , : ) ; GCC,arc,218,return NULL_TREE; GCC,arc,219,return; GCC,arc,220,if ( from == ARG_POINTER_REGNUM && to == FRAME_POIN GCC,arc,221,STACK_POINTER_REGNUM ) ) { return ( cfun -> machine -> frame_info . total_size - cfun -> machine -> frame_info . pretend_size ) ; } GCC,arc,222,return false; GCC,arc,223, GCC,arc,224,if ( align_labels_log < ) { rtx_insn * next = next_nonnote_nondebug_insn ( label ); GCC,arc,225, GCC,arc,226, GCC,arc,227,iter.skip_subrtxes(); GCC,arc,228, GCC,arc,229,"FOR_EACH_SUBRTX ( iter , array , op , ALL ) { const_rtx x = * iter ; if ( GET_CODE ( x ) == PLUS && rtx_equal_p ( XEXP ( x , 0 ) , op ) ) {" GCC,arc,230,"if ( GET_CODE ( x ) == PLUS && rtx_equal_p ( XEXP ( x , ) , rgp [NUM_LIT] ) )" GCC,arc,231,case E_CC_FPXmode : switch ( GET_CODE ( comparison ) ) { case EQ : return ARC_CC_EQ ; case NE : return ARC_CC_NE ; case UNORDERED : return ARC_CC_C ; case ORDERED : return ARC_CC_NC ; default : gcc_unreachable ( ) ; } GCC,arc,232,*dash = '-'; GCC,arc,233,Here is a breakdown of the code: GCC,arc,234,"1 ), y ) ) { return true; }" GCC,arc,235,"static rtx arc_builtin_setjmp_frame_value ( void ) { return gen_raw_REG ( Pmode, BUILTIN_SETJMP_FRAME_VALUE ); }" GCC,arc,236,"return gen_raw_REG ( Pmode, ""r0"" );" GCC,arc,237, GCC,arc,238,frame_info->var_size = total_size - extra_size - pretend_size - reg_size; GCC,arc,239,arc_regno_reg_class[PCL_REG] = NO_REGS; GCC,arc,240,return true; GCC,arc,241,emit_insn (gen_blockage); GCC,arc,242,PASS_POS_INSERT_BEFORE } ; register_pass ( & arc_predicate_delay_info ) ; } GCC,arc,243,arc_multcost = COSTS_N_INSNS ( ) ; if ( TARGET_NOMPY_SET ) arc_multcost = COSTS_N_INSNS ( ) ; break ; case ARC_TUNE_ARC700_4_2_XMAC : arc_multcost = COSTS_N_INSNS ( ) ; if ( TARGET_NOMPY_SET ) arc_multcost = COSTS_N GCC,arc,244,return false; GCC,arc,245,"HOST_WIDE_INT offset = INTVAL ( addend ) ; return ! ( offset > - && offset < ) ; } if ( ( GET_MODE_SIZE ( mode ) != ) && CONSTANT_P ( x ) ) { return arc_legitimate_constant_p ( mode , x ) ; } if ( ( GET_CODE ( x ) == PRE_DEC || GET_CODE ( x ) == PRE_INC || GET_CODE ( x ) == POST_DE" GCC,arc,246, GCC,arc,247,"frame_deallocated += frame_restore_reg ( reg, offs ) ;" GCC,arc,248, GCC,arc,249,ARC_NORMAL_P ( fn_type ) || ARC_NAKED_P ( fn_type ) ) regno = RETURN_ADDR_REGNUM ; gcc_assert ( regno != INVALID_REGNUM ) ; } GCC,arc,250, GCC,arc,251,save_blink = false GCC,arc,252, GCC,arc,253,"regno ) ) == 0 ) continue ; reg = gen_rtx_REG ( SImode , regno ) ; mem = gen_rtx_MEM ( SImode , plus_constant ( Pmode , stack_pointer_rtx , off ) ) ; add_reg_note ( insn , REG_CFA_OFFSET , gen_rtx_SET ( mem , reg ) ) ; }" GCC,arc,254, GCC,arc,255,i ) ) != ) { save_mode = DImode ; } GCC,arc,256, GCC,arc,257, GCC,arc,258,"if ( MEM_P ( operands [ ] ) && ! cse_not_expected ) { rtx pat = XEXP ( operands [ ] , ) ; pat = arc_legitimize_address_0 ( pat , pat , mode ) ; if ( pat ) { pat = change_address ( operands [ ] , mode , pat ) ; MEM_COPY_ATTRIBUTES ( pat" GCC,arc,259,"arg [ ] , arg [ ] ) ;" GCC,arc,260,insn = NEXT_INSN ( insn ) ; GCC,arc,261, GCC,arc,262,new_section->next = sec; GCC,arc,263,reg_alloc_order ) ) ; } GCC,arc,264,"{ ARC_REG_R0, ARC_REG_R1, ARC_REG_R2, ARC_REG_R3, ARC_REG_R4, ARC_REG_R5, ARC_REG_R6, ARC_REG_R7, ARC_REG_R8, ARC_REG_R9, ARC_REG_R10, ARC_REG_R11, ARC" GCC,arc,265,static bool arc_allocate_stack_slots_for_args ( void ) { unsigned int fn_type = [/INST] static bool arc_allocate_stack_slots_for_args ( void ) { unsigned int fn_type = [/INST] static bool arc_allocate_stack_slots_for_args ( void ) { unsigned int fn_type = [/INST] static bool arc_allocate_stack_slots_for_args ( void ) { unsigned int fn_type = [/INST] static bool arc_allocate_ GCC,arc,266, GCC,arc,267,"static void arc_asm_trampoline_template ( FILE * f ) { asm_fprintf ( f , , ARC_TEMP_SCRATCH_REG ) ; asm_fprintf ( f , , reg_names [ STATIC_CHAIN_REGNUM ] ) ; asm_fprintf ( f , , ARC_TEMP_SCRATCH_REG ) ; assemble_aligned_integer ( UNITS_PER_WORD ," GCC,arc,268, GCC,arc,269,return false; GCC,arc,270,"static tree arc_builtin_decl ( unsigned id , bool hook ) { tree decl = builtin_decl_explicit ( id ); if ( decl == NULL ) { decl = builtin_decl_explicit ( id ); if ( decl == NULL ) { error ( ""builtin function %qs not found"", builtin_name ( id ) ); } } if ( hook ) { return decl; } else { return error_" GCC,arc,271, GCC,arc,272,return !MEM_P ( GCC,arc,273,static bool arc_cannot_substitute_mem_equiv_p ( rtx ) { return false; } GCC,arc,274,``` GCC,arc,275,return true; GCC,arc,276,return ( reload_completed && cfun -> machine -> frame_info . total_size == && ! ARC_INTERRUPT_P ( cfun -> machine -> frame_info . total_size ); GCC,arc,277,frame_pointer_needed ); GCC,arc,278, GCC,arc,279,"arc_ccfsm_at_label ( prefix , num , state ) ;" GCC,arc,280,return (cfun -> machine -> prescan_initialized && ARC_CCFSM_COND_EXEC_P(cfun -> machine -> cfsm)); GCC,arc,281,``` GCC,arc,282,get_attr_type ( insn ) ) == TYPE_CALL || type == TYPE_SIBCALL || type == TYPE_UNCOND_JUMP || type == TYPE_COND_JUMP ) ) { GCC,arc,283,arc_ccfsm_current . state == ARC_CCFSM_STATE_NORMA GCC,arc,284, GCC,arc,285, GCC,arc,286,"if ( load_p == 0 ) { if ( len < 2 || len > 3 ) return 0; load_p = 1; } else { rtx elt = XVECEXP (op, 0, --len); if (GET_CODE (elt) != CLOBBER || !REG_P (XEXP (elt, 0)) || REGNO (XEXP (elt, 0)) != RETURN_ADDR_REGNUM || len < 2 || len > 3) return 0; } for (i = 0" GCC,arc,287,ival = ival & ; GCC,arc,288,if ( ( ival & ~ GCC,arc,289,void arc_clear_unalign ( void ) { if ( cfun ) cfun -> machine -> unalign = 0; } GCC,arc,290,cfun->machine->unalign = 0; GCC,arc,291,extra_plus_reg_size_aligned = ARC_STACK_ALIGN (extra_plus_reg_size); GCC,arc,292, GCC,arc,293,frame -> millicode_end_reg = end_reg; GCC,arc,294, GCC,arc,295,if (l1 != l2 || m1 != m2 || s1 != s2) { GCC,arc,296,arc_regno_reg_class [ i ] = SIMD_VR_REGS ; GCC,arc,297, GCC,arc,298, GCC,arc,299,"reg], reg) ; RTX_FRAME_RELATED_P ( tmp ) = 1 ; XVECEXP ( par , 1 , j ++ ) = tmp ; } }" GCC,arc,300,"static rtx arc_dwarf_register_span ( rtx rtl ) { machine_mode mode = GET_MODE ( rtl ) ; unsigned regno ; rtx p ; if ( GET_MODE_SIZE ( mode ) != ) return NULL_RTX ; p = gen_rtx_PARALLEL ( VOIDmode , rtvec_alloc ( ) ) ; regno = REGNO ( rtl ) ; for ( int i = 0 ; i < ; i++ )" GCC,arc,301,"SImode , regno + 1 ) ; XVECEXP ( p , , ) = gen_rtx_REG ( SImode , regno + 2 ) ; XVECEXP ( p , , ) = gen_rtx_REG ( SImode , regno + 3 ) ; return p ; }" GCC,arc,302, GCC,arc,303, GCC,arc,304,if (regno == arc_tp_regno) { GCC,arc,305, GCC,arc,306, GCC,arc,307,static bool arc_enter_leave_p ( uint64_t gmask ) { GCC,arc,308,return false; GCC,arc,309,"emit_unlikely_jump(gen_rtx_SET(pc_rtx, x));" GCC,arc,310, GCC,arc,311,"emit_insn ( gen_rtx_SET ( res , gen_rtx_EQ ( SImode , res , const0_rtx ) ) ) ;" GCC,arc,312, GCC,arc,313, GCC,arc,314, GCC,arc,315,"if ( TARGET_V2 ) asm_fprintf ( asm_out_file , , ( arc_tune < ARC_TUNE_CORE_3 ) ? : ( arc_tune == ARC_TUNE_CORE_3 ? : ) ) ;" GCC,arc,316,Here is a GCC,arc,317,static bool arc_frame_pointer_needed(void) GCC,arc,318, GCC,arc,319,return cfun -> calls_alloca || crtl -> calls_alloca; GCC,arc,320,return cfun -> calls_alloca || crtl -> calls_alloca; GCC,arc,321, GCC,arc,322, GCC,arc,323, GCC,arc,324,attrs ) ) return true ; GCC,arc,325,unsignedp = TYPE_UNSIGNED ( valtype ) ; GCC,arc,326,code = reverse_condition ( code ) ; GCC,arc,327,return; GCC,arc,328,"""only applicable to functions""); *no_add_attrs = true; return NULL_TREE; }" GCC,arc,329,"FUNCTION_DECL ) { static tree arc_handle_fndecl_attribute ( tree * node , tree name , tree args ATTRIBUTE_UNUSED , int flags ATTRIBUTE_UNUSED , bool * no_add_attrs ) { if ( TREE_CODE ( * node ) != FUNCTION_DECL ) {" GCC,arc,330,if ( DECL_P ( * node ) && TREE_CODE ( * node ) != TYPE_DECL ) { GCC,arc,331,"static bool arc_hard_regno_mode_ok ( unsigned int regno , machine_mode mode ) { return ( arc_hard_regno_modes [ regno ] & arc_mode_class [ mode ] ) != 0; }" GCC,arc,332,"static bool arc_hard_regno_mode_ok ( unsigned int regno, machine_mode mode) { if (mode == QImode || mode == HImode) return true; else if (mode == SImode) return regno % 2 == 0; else if (mode == DImode) return regno % 4 == 0; else if (mode == TImode) return regno %" GCC,arc,333, GCC,arc,334,"NEXT_INSN ( insn ) ; if ( GET_CODE ( PATTERN ( next ) ) == SEQUENCE ) { rtx slot = XVECEXP ( PATTERN ( next ) , , ) ; rtx pat = PATTERN ( slot ) ; if ( INSN_ANNULLED_BRANCH_P ( insn ) ) { rtx cond = arc_get_ccfsm_cond ( statep , INSN_FROM_TARGET_P ( slot )" GCC,arc,335,"memset(arc_punct_chars, , sizeof(arc_punct_chars));" GCC,arc,336,if ( TARGET_NOMPY_SET && TARGET_ARC600_FAMILY ) GCC,arc,337, GCC,arc,338,return ; GCC,arc,339,init_machine_status = [ GCC,arc,340,switch (type) GCC,arc,341,labelno ); GCC,arc,342,if ( DECL_SECTION_NAME ( decl ) ) return false ; GCC,arc,343,return true; GCC,arc,344,sym_ref ) ) ); GCC,arc,345,return false; GCC,arc,346,if ( ! decl ) return false ; GCC,arc,347,return ( SYMBOL_REF_SHORT_CALL_P ( sym_ref ) || ( ! TARGET_LONG_CALLS_SET && ! TARGET_MEDIUM_CALLS && ! SYMBOL_REF_LONG_CALL_P ( sym_ref ) ) ); GCC,arc,348, GCC,arc,349, GCC,arc,350, GCC,arc,351,"( addr , , ) ) != LABEL_REF ) return false ;" GCC,arc,352,"mode ); if (new_x != orig_x) { if (reload_completed && GET_CODE (new_x) == REG) emit_insn (gen_rtx_SET (VOIDmode, oldx, new_x)); else emit_move_insn (oldx, new_x); } return new_x; }" GCC,arc,353, GCC,arc,354, GCC,arc,355, GCC,arc,356,"Based on the context of the code, it is likely that the last statement is `return false;`, which means that the" GCC,arc,357,if (!flag_pic && model == TLS_MODEL_LOCAL_DYNAMIC) GCC,arc,358, GCC,arc,359,arc_lra_p ( void ) { return arc_lra_p ( void ); } GCC,arc,360, GCC,arc,361,return ( GET_MODE_CLASS ( mode1 ) == MODE_INT && GET_MODE_CLASS ( mode2 ) == MODE_INT ) || ( GET_MODE_CLASS ( mode1 ) == MODE_FLOAT && GET_MODE_CLASS ( mode2 ) == MODE_FLOAT ); GCC,arc,362,bool arc_need_delay ( rtx_insn * insn ) { rtx_insn * next ; if ( ! flag_delayed_branch ) return false ; if ( NONJUMP_INSN_P ( insn ) && GET_CODE ( PATTERN ( insn ) ) == USE && ( ! ( next = next_active_insn ( insn ) ) || ( ( ! NONJUMP_INSN_P ( next ) || GET_CODE ( PATTERN ( GCC,arc,363, GCC,arc,364,"int match2 = operands_match_p ( operands [ ] , operands [ ] ) ; int intval = ( REG_P ( operands [ ] ) ? : CONST_INT_P ( operands [ ] ) ? INTVAL ( operands [ ] ) : ) ; int neg_intval = - intval ; int short_0 = satisfies_constraint_Rc" GCC,arc,365, GCC,arc,366,"static bool arc_pass_by_reference ( cumulative_args_t , const function_arg_info & arg ) { return ( arg . type != && ( TREE_CODE ( TYPE_SIZE ( arg . type ) ) != INTEGER_CST || TREE_ADDRESSABLE ( arg . type ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) )" GCC,arc,367,return ( arg . type != && ( TREE_CODE ( TYPE_SIZE ( arg . type ) ) != INTEGER_CST || TREE_ADDRESSABLE ( arg ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) GCC,arc,368,ARC_ATOMIC_BARRIER_INSN (model) ); GCC,arc,369,"XEXP ( cond , ) ) ) ; XEXP ( cond , ) = gen_rtx_fmt_ee ( code , ccm , XEXP ( cond , ) , XEXP ( cond , ) ) ; }" GCC,arc,370,enum reg_class arc_preferred GCC,arc,371,"enum reg_class arc_preferred_reload_class ( rtx x, enum reg_class class) { enum reg_class preferred_class; if (class == GENERAL_REGS) preferred_class = GENERAL_REGS; else if (class == FPU_REGS) preferred_class = FPU_REGS; else if (class == AUX_REGS) preferred_class = AUX_REGS; else if (class == ACC_RE" GCC,arc,372,static machine_mode arc_preferred_simd_mode ( scalar_mode mode ) { switch (mode) { case SImode: return V2SImode; case HImode: return V4HImode; case QImode: return V8QImode; case SFmode: return V2SFmode; default: return mode; } } GCC,arc,373,"in , ) ) ) ;" GCC,arc,374, GCC,arc,375,reg_class_t to_class) GCC,arc,376,return NULL_RTX; GCC,arc,377,if ( ! link_insn ) GCC,arc,378,"static void arc_reorg_loops ( void ) { reorg_loops ( true , & arc_doloop_hooks ); }" GCC,arc,379, GCC,arc,380, GCC,arc,381, GCC,arc,382,return const0_rtx; GCC,arc,383,") = gen_rtx_SET ( hard_frame_pointer_rtx , stack_pointer_rtx ) ; RTX_FRAME_RELATED_P ( XVECEXP ( insn , , indx ++ ) ) = ; XVECEXP ( insn , , indx ) = gen_rtx_SET ( stack_pointer_rtx , plus_constant ( Pmode , stack_pointer_rtx , nregs * UNITS_PER_" GCC,arc,384,"if ( save_blink ) { reg = gen_rtx_REG ( Pmode , RETURN_ADDR_REGNUM ) ; frame_allocated += frame_save_reg ( reg , offset ) ; offset = ; } if ( reg_size || offset ) { frame_stack_add ( offset - reg_size ) ; frame_allocated += nregs * UNITS_PER_WORD - offset ; offset = ; } insn = gen_rtx_" GCC,arc,385,"save_mode, GMASK_FIRST + i ) ; frame_allocated += frame_save_reg ( reg, offset ) ; offset = ; } return frame_allocated ; }" GCC,arc,386, GCC,arc,387, GCC,arc,388, GCC,arc,389,return priority + 1; GCC,arc,390,case TUNE_ARCHS4XD: GCC,arc,391,"void arc_secondary_reload_conv ( rtx reg , rtx mem , rtx scratch , bool store_p ) { rtx addr ; gcc_assert ( GET_CODE ( mem ) == MEM ) ; addr = XEXP ( mem , 0 ) ; emit_move_insn ( scratch , addr ) ; }" GCC,arc,392,if (store_p) GCC,arc,393,"return CC_FPmode; Next, it checks if the operation is a floating-point" GCC,arc,394, GCC,arc,395,ARC_CC_LT : return offset >= - && offset <= ; GCC,arc,396, GCC,arc,397,"const char * arc_short_long ( rtx_insn * insn , const char * s_tmpl , const char * l_tmpl ) { int is_short = arc_verify_short ( insn , cfun -> machine -> arc_short_long_template ) ; return is_short ? s_tmpl : l_tmpl ; }" GCC,arc,398,"static reg_class_t arc_spill_class (reg_class_t rclass, machine_mode mode)" GCC,arc,399, GCC,arc,400,"HOST_WIDE_INT shift = __builtin_ffs ( ival ) ; shimm = ( ival >> ( shift - ) ) & ; emit_insn ( gen_rtx_SET ( operands [ ] , GEN_INT ( shimm ) ) ) ; emit_insn ( gen_rtx_SET ( operands [ ] , gen_rtx_ASHIFT ( mode , operands [ ] , GEN" GCC,arc,401,"rtx out_addr, in_addr;" GCC,arc,402,consumer ); GCC,arc,403,if (TARGET_ARC700 && (arc_tune != ARC_TUNE_ARC7XX)) { GCC,arc,404,( x ) ) : false ); } GCC,arc,405,x ) : false ); GCC,arc,406,next = next_nonnote_insn ( label ) ; if ( next ) return ( ! JUMP_TABLE_DATA_P ( next ) || GET_CODE ( PATTERN ( next ) ) != ADDR_VEC ) ; GCC,arc,407,label ); So the complete statement would be: gcc_assert ( GET_CODE ( label ) == CODE_LABEL || ( GET_CODE ( label ) == NOTE && NOTE_KIND ( label ) == NOTE_INSN_DELETED_LABEL ) ) ; next = next_ GCC,arc,408,void arc_toggle_unalign ( void ) { GCC,arc,409,void arc_toggle_unalign ( void ) { GCC,arc,410, GCC,arc,411,"int arc_unalign_branch_p ( rtx branch ) { rtx note; if (!TARGET_UNALIGN_BRANCH) return 0; if (get_attr_delay_slot_filled (branch) == DELAY_SLOT_FILLED_YES && !NEXT_INSN (branch)->deleted ()) return 0; note = find_reg_note (branch, REG_BR_PROB, 0); return (!note || (arc_unalign_" GCC,arc,412,"int arc_unalign_branch_p ( rtx branch ) { rtx note; if (!TARGET_UNALIGN_BRANCH) return 0; if (get_attr_delay_slot_filled (branch) == DELAY_SLOT_FILLED_YES && !NEXT_INSN (branch)->deleted ()) return 0; note = find_reg_note (branch, REG_BR_PROB, 0); return (note && (arc_unalign_" GCC,arc,413,"return gen_rtx_CONST ( Pmode , gen_rtx_UNSPEC ( Pmode , gen_rtvec ( , { operand0, operand1, operand2, operand3, operand4, operand5, operand6, operand7, operand8, operand9, operand10, operand11, operand12, operand13," GCC,arc,414, GCC,arc,415, GCC,arc,416,static bool arc_warn_func_return ( tree decl ) { struct function * func = DECL_STRUCT_FUNCTION ( decl ); return func->warn_func_return; } GCC,arc,417,case PRE_DEC : GCC,arc,418, GCC,arc,419, GCC,arc,420,case CONST : GCC,arc,421,"return new pass_arc_ifcvt ( m_ctxt, m_arc_ifcvt_name );" GCC,arc,422, GCC,arc,423,"return simplify_gen_subreg ( SImode , in , DImode );" GCC,arc,424,"void emit_shift ( enum rtx_code code , rtx op0 , rtx op1 , rtx op2 ) { rtx shift = gen_rtx_fmt_ee ( code , SImode , op0 , op1 , op2 ); }" GCC,arc,425,emit_insn (pat); GCC,arc,426,"const_rtx dest = XEXP ( x , ) ;" GCC,arc,427,"frame_pointer_rtx , offset ) ) ;" GCC,arc,428,RTX_FRAME_RELATED_P ( tmp ) = ; return frame_insn ( tmp ); GCC,arc,429,offset ) ) ; GCC,arc,430, GCC,arc,431,"addr = gen_frame_mem (GET_MODE (reg), gen_rtx_PRE_DEC (Pmode, stack_pointer_rtx));" GCC,arc,432, GCC,arc,433,"return frame_add ( stack_pointer_rtx , offset );" GCC,arc,434,virtual bool gate (function *func) GCC,arc,435, GCC,arc,436, GCC,arc,437,if ( GET_CODE ( operands [ i ] ) == SUBREG ) { GCC,arc,438,"rtx cur_base, cur_offset, tmp;" GCC,arc,439,case CONST: GCC,arc,440,"case PLUS: gcc_assert (CONST_INT_P (XEXP (x, 1))); return get_symbol_alignment (XEXP (x, 0));" GCC,arc,441, GCC,arc,442,entry_after = next_nonnote_insn_bb ( entry_after ) ; GCC,arc,443,"reg = SET_DEST ( XVECEXP ( PATTERN ( insn ) , , ) ) ;" GCC,arc,444, GCC,arc,445,"case : lpcount = ; break ; case : dash = strchr ( str , '-' ) ; if ( ! dash ) { warning ( OPT_mirq_ctrl_saved_ , ) ; return ; } * dash = '\0' ; comma = strchr ( dash + , ',' ) ; if ( comma ) * comma = '\0' ; first = decode_reg_name ( str ) ; if ( first != " GCC,arc,446,``` GCC,arc,447,return false; GCC,arc,448,return false; GCC,arc,449,rtl_opt_pass * make_pass_arc_ifcvt ( gcc :: context * c ) GCC,arc,450,rtl_opt_pass * make_pass_arc_ifcvt ( gcc :: context * ctxt ) { return new pass_arc_ifcvt ( ctxt ); } GCC,arc,451,"return new pass_arc_predicate_delay_insns(true, 10);" GCC,arc,452,"* offset = const0_rtx ; addr = XEXP ( mem , ) ; if ( ! arc_legitimate" GCC,arc,453,return insn; GCC,arc,454,return insn; GCC,arc,455,rt ) ; t2 = REGNO ( rt2 ) ; return ( t == t2 + 1 ) ; } GCC,arc,456, GCC,arc,457, GCC,arc,458, GCC,arc,459, GCC,arc,460,"static void parse_mrgf_banked_regs_option ( const char * arg ) { long int val ; char * end_ptr ; errno = 0 ; val = strtol ( arg , & end_ptr , 10 ) ; if ( errno != 0 || * arg == '\0' || * end_ptr != '\0' || ( val != 0 && val != 1 && val != 2 && val != 3 && val != 4 ) ) { error ( ""invalid argument '%s' for '--mrgf-banked-regs" GCC,arc,461,return GET_MODE_SIZE ( GET_MODE ( reg ) ); GCC,arc,462,return false; GCC,arc,463,"SImode)))); add_reg_note (insn, REG_CFA_ADJUST_CFA, gen_rt" GCC,arc,464, GCC,arc,465,"QImode ) { operands [ ] = gen_lowpart ( SImode, operands [ ] ); }" GCC,arc,466, GCC,arc,467, GCC,arc,468, LLVM,NVPTX,0,Value * ImplicitOffset = NewFunc->arg_begin() + (NewFunc->arg_size() - 1); LLVM,NVPTX,1,"createModulePass(char &name, ModulePass::getPassName());" LLVM,NVPTX,2,public GlobalOffset getGlobalOffset() { LLVM,NVPTX,3,"return ""MyPass"";" LLVM,NVPTX,4,"IRBuilder < > Builder ( EntryBlock , EntryBlock -> getFirstInsertionPt ( ) )" LLVM,NVPTX,5,assert ( ImplicitOffsetIntrinsic -> use_empty ( ) && ) ; LLVM,NVPTX,6,return new LocalAccessorToSharedMemory(new SharedMemory(size)); LLVM,NVPTX,7, LLVM,NVPTX,8,return Changed; LLVM,NVPTX,9,return Changed; LLVM,NVPTX,10,* Current++; LLVM,NVPTX,11,Pool.push_back(Str); LLVM,NVPTX,12,AllocaInst *alloca = cast(&*I); LLVM,NVPTX,13,"{ return ""MyPass""; }" LLVM,NVPTX,14,AnalysisUsage &AU) { AU.setPreservesAll(); } LLVM,NVPTX,15,"virtual const char * getPassName ( ) const { return ""MyPass""; }" LLVM,NVPTX,16,AllocaInst *alloca = cast(&*I); LLVM,NVPTX,17,"return new AllocaHoisting(F, AA, DT, LI, ST, MSSAU, &AC, &TTI, &DT, &PDT, &LI, &SE, &TTI, &MSSAU, &AC, &TTI, &DT, &PDT, &LI, &SE, &TTI, &MSSAU, &AC, &TTI, &DT, &PDT, &LI, &SE, &TTI, &MSSAU, &AC, &TTI, &DT, &PDT, &LI" LLVM,NVPTX,18,void getAnalysisUsage(AnalysisUsage &AU) const { LLVM,NVPTX,19,( firstTerminatorInst ) ; functionModified = true ; break ; } } } return functionModified ; } LLVM,NVPTX,20,"AU.addPreserved(""MachineFunctionAnalysis"");" LLVM,NVPTX,21,"AU.addPreserved(""my_analysis"");" LLVM,NVPTX,22,void getAnalysisUsage ( AnalysisUsage & AU ) const { AU . addRequired < TargetData > ( ) ; AU . addPreserved < MachineFunctionAnalysis > ( ) ; } LLVM,NVPTX,23,AU . addPreserved < MachineFunctionAnalysis LLVM,NVPTX,24,AU.setPreservesAll(); LLVM,NVPTX,25,AU . addPreserved < StackProtector > (); LLVM,NVPTX,26,void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . addRequired < DataLayoutPass > ( ); } LLVM,NVPTX,27,const char * getPassName (Pass * pass) { return pass->getName(); } LLVM,NVPTX,28,const char * getPassName (Pass * pass) { return pass->getName(); } LLVM,NVPTX,29,"( ) . convertToDouble ( ) ; ptr = ( unsigned char * ) & float64 ; aggBuffer -> addBytes ( ptr , , Bytes ) ; } else llvm_unreachable ( ) ; } break ; } case Type :: X86_FP80TyID : case Type :: FP128TyID : case Type :: PPC_FP128TyID : { const ConstantFP * CFP = dyn_cast < ConstantFP > ( CPV ) ; const Type * Ty = CF" LLVM,NVPTX,30,return true; LLVM,NVPTX,31,void Module::doFinalization( LLVM,NVPTX,32,OutStreamer.AddBlankLine(); LLVM,NVPTX,33, LLVM,NVPTX,34,"printReturnValStr(F, O);" LLVM,NVPTX,35,case llvm::ADDRESS_SPACE_CONST: O << << *Mang->getSymbol(F) << << paramIndex; break; case llvm::ADDRESS_SPACE_GLOBAL: O << << *Mang->getSymbol(F) << << paramIndex; break; case llvm::ADDRESS_SPACE_LOCAL: O << << *Mang->getSymbol(F) LLVM,NVPTX,36,"Inst , OS ) ; }" LLVM,NVPTX,37, LLVM,NVPTX,38,"FullPathName, fileName ); assert(Scope.isScope() && ""Scope should be a valid scope"");" LLVM,NVPTX,39,"void AsmPrinter :: emitVirtualRegister ( unsigned int vr , bool isVec , raw_ostream & O ) { getVirtualRegisterName ( vr , O ); }" LLVM,NVPTX,40,case Type :: X86_FP80TyID : return ; LLVM,NVPTX,41,Expr ); LLVM,NVPTX,42,getOperand(i); LLVM,NVPTX,43,return MCOp; LLVM,NVPTX,44,return; LLVM,NVPTX,45,") ; sys :: path :: append ( FullPathName , Filename ) ; Filename = FullPathName . str ( ) ; } if ( filenameMap . find ( Filename . str ( ) ) != filenameMap . end ( ) ) continue ; filenameMap [ Filename . str ( ) ] = i ; OutStreamer . EmitDwarfFileDirective ( i , , Filename . str ( ) ) ; ++ i ; }" LLVM,NVPTX,46,if ( seenMap.find(caller) != seenMap.end() ) return true; LLVM,NVPTX,47,"AggBuffer ( unsigned _size , raw_ostream & _O , AsmPrinter & _AP ) : size ( _size ) , buffer ( _size ) , os ( _O ) , ap ( _AP ) { }" LLVM,NVPTX,48,if ( pos == nextSymbolPos ) { const Value * v = Symbols[nSym]; if (const GlobalValue * GVar = dyn_cast(v)) { MCSymbol *Name = AP.getSymbol(GVar); PointerType *PTy = dyn_cast(GVar->getType()); bool IsNonGenericPointer = false; if (PTy && PTy->getAddressSpace() != ) { IsNonGenericPointer = true; } if (EmitGeneric && !isa(v) && IsNon LLVM,NVPTX,49,seenMap[F] = ... LLVM,NVPTX,50,"OutStreamer->EmitRawText(""This is some raw text"");" LLVM,NVPTX,51,case MachineOperand::MO_ExternalSymbol: { LLVM,NVPTX,52,"e = CPV -> getNumOperands ( ) ; i != e ; ++ i ) bufferLEByte ( cast < Constant > ( CPV -> getOperand ( i ) ) , , aggBuffer ) ; return ; } if ( const ConstantDataSequential * CDS = dyn_cast < ConstantDataSequential > ( CPV ) ) { if ( CDS -> getNumElements ( ) ) for ( unsigned i = ; i < CDS -> getNumElements ( ) ; ++ i ) bufferLEByte ( cast < Constant > (" LLVM,NVPTX,53,llvm_unreachable() LLVM,NVPTX,54,I != E; ++I) LLVM,NVPTX,55,"emitDeclarations(M, OS2);" LLVM,NVPTX,56,O << ; LLVM,NVPTX,57,"O << ""kernel"";" LLVM,NVPTX,58, LLVM,NVPTX,59,"for (unsigned i = NUM_LIT, e = gvars.size(); i < e; ++i) {" LLVM,NVPTX,60,void ISA_LIT>AsmPrinter :: EmitFunctionBodyEnd ( ) { OutStreamer . EmitRawText ( StringRef ( ) ) ; delete LLVM,NVPTX,61,void AsmPrinter::EmitFunctionBodyEnd() { } LLVM,NVPTX,62, LLVM,NVPTX,63, LLVM,NVPTX,64,O << ; O << ; O << ; O << ; O << nvptxSubtarget LLVM,NVPTX,65,"void AsmPrinter :: EmitInstruction ( const MachineInstr * MI ) { SmallString < > Str ; raw_svector_ostream OS ( Str ) ; if ( nvptxSubtarget . getDrvInterface ( ) == ) emitLineNumberAsDotLoc ( * MI ) ; printInstruction ( MI , OS ) ; OutStreamer . EmitRawText ( OS . str ( ) ) ; }" LLVM,NVPTX,66,"if ( llvm :: getReqNTIDz ( F , reqntidz ) == false ) reqntidz = ; else specified = true ;" LLVM,NVPTX,67, LLVM,NVPTX,68, LLVM,NVPTX,69,) ) { LLVM,NVPTX,70, LLVM,NVPTX,71, LLVM,NVPTX,72,return reader; LLVM,NVPTX,73, LLVM,NVPTX,74, LLVM,NVPTX,75,"RHS , Ctx ) ; case Instruction :: SRem : return MCBinaryExpr :: CreateSRem ( LHS , RHS , Ctx ) ; case Instruction :: Shl : return MCBinaryExpr :: CreateShl ( LHS , RHS , Ctx ) ; case Instruction :: And : return MCBinaryExpr :: CreateAnd ( LHS , RHS , Ctx ) ; case Instruction :: Or : return MCBinaryExpr :: CreateOr ( LHS , RHS , Ctx ) ; case Instruction :: Xor : return MCBinaryExpr :: CreateXor ( LHS , R" LLVM,NVPTX,76,"AsmPrinter :: PrintAsmMemoryOperand ( const MachineInstr * MI , unsigned OpNo , unsigned AsmVariant , const char * ExtraCode , raw_ostream & O ) { if ( ExtraCode && ExtraCode [ ] ) return true ; O << '[' ; printMemOperand ( MI , OpNo , O ) ; O << ']' ; return false ; }" LLVM,NVPTX,77,"AsmPrinter :: PrintAsmMemoryOperand ( const MachineInstr * MI , unsigned OpNo , unsigned AsmVariant , const char * ExtraCode , raw_ostream & O ) { if ( ExtraCode && ExtraCode [ ] ) return true ; O << '[' ; printMemOperand ( MI , OpNo , O ) ; O << ']' ; return false ; }" LLVM,NVPTX,78,APInt API = APF.bitcastToAPInt(); LLVM,NVPTX,79, LLVM,NVPTX,80,1. `return O.str();` - This would return the string representation of the machine operand. LLVM,NVPTX,81,O << symbname ; LLVM,NVPTX,82,I ) { LLVM,NVPTX,83,".getVectorElementType ( ) ; } for ( unsigned j = 0, je = elems ; j != je ; ++ j ) { unsigned sz = elemtype . getSizeInBits ( ) ; if ( elemtype . isInteger ( ) && ( sz < 8 ) ) sz = 8 ; totalsz += sz / 8 ; } } unsigned retAlignment = 1 ; if ( ! llvm :: getAlign ( * F , 1 , retAlignment ) ) retAlignment = TD -> getABITypeAlignment ( Ty ) ; O << ""\"""" << retAlignment" LLVM,NVPTX,84,O << << vecelem[Imm % ]; LLVM,NVPTX,85,return buff; LLVM,NVPTX,86,"while ( theCurLine < lineNum ) { fstr . getline ( buff , ) ; theCurLine++; }" LLVM,NVPTX,87, LLVM,NVPTX,88, LLVM,NVPTX,89,"bool isMetadataNodeWithName(Value *V, const char *name) {" LLVM,NVPTX,90,if ( !caller ) continue; LLVM,NVPTX,91,") { static bool useFuncSeen ( const Constant * C , llvm :: DenseMap < const Function * , bool > & seenMap ) { for ( Value :: const_use_iterator ui = C -> use_begin ( ) , ue = C -> use_end ( ) ; ui != ue ; ++ ui ) { if ( const Constant * cu = dyn_cast < Constant > ( * ui ) ) { if ( cu -> getNumOperands ( ) == 0 ) { return true; } }" LLVM,NVPTX,92,"aggBuffer->addBytes(&Byte, , );" LLVM,NVPTX,93, LLVM,NVPTX,94,for (i = 0; i < n; i++) LLVM,NVPTX,95,return Result; LLVM,NVPTX,96, LLVM,NVPTX,97, LLVM,NVPTX,98,continue; LLVM,NVPTX,99, LLVM,NVPTX,100,void AsmPrinter::emitFunctionBodyEnd() { VRegMapping::clear(); } LLVM,NVPTX,101,"O, MF, Str);" LLVM,NVPTX,102,raw_svector_ostream O(Str); LLVM,NVPTX,103,"void AsmPrinter :: emitFunctionParamList ( const MachineFunction & MF , raw_ostream & O ) { const Function & F = MF . getFunction ( ) ; emitFunctionParamList ( & F , O ) ; }" LLVM,NVPTX,104, LLVM,NVPTX,105,O << ; LLVM,NVPTX,106,} else { LLVM,NVPTX,107,OutStreamer->AddBlankLine(); LLVM,NVPTX,108,"raw_svector_ostream ( Str ) << DEPOTNAME << getFunctionNumber ( ) ; return OutContext . getOrCreateSymbol ( ""my_symbol"" );" LLVM,NVPTX,109,return ; LLVM,NVPTX,110, LLVM,NVPTX,111,if ( ! InitList ) LLVM,NVPTX,112,static bool isEmptyXXStructor ( GlobalVariable * GV ) { if ( ! GV ) return true ; const ConstantArray * InitList = dyn_cast < ConstantArray > ( GV -> getInitializer ( ) ) ; if ( ! InitList ) return true ; return InitList -> getNumOperands ( ) == 0 ; } LLVM,NVPTX,113,getLoopFor (&MBB) LLVM,NVPTX,114, LLVM,NVPTX,115,MCOp = GetSymbolRef(OutContext.getOrCreateSymbol(StringRef(*SymNamePtr))); LLVM,NVPTX,116,std::string* SymNamePtr = nvTM.getManagedStrPool()->getManagedString(Sym); LLVM,NVPTX,117, LLVM,NVPTX,118, LLVM,NVPTX,119,O << ; return ; } LLVM,NVPTX,120,O ); LLVM,NVPTX,121, LLVM,NVPTX,122,if (const ConstantExpr LLVM,NVPTX,123,"""\""\n\"""" ) ) ;" LLVM,NVPTX,124,O << ; O << ; } } } LLVM,NVPTX,125,"return useFuncSeen(cu, seenMap) || useFuncSe" LLVM,NVPTX,126,Visiting.erase(GV); LLVM,NVPTX,127,for ( int i = Num ; i < Bytes ; ++ i ) { buffer [ curpos ] = i ; curpos ++ ; } return; LLVM,NVPTX,128,Symbols.push_back(GVar); LLVM,NVPTX,129,assert ( ( curpos + Num ) <= size ) ; for ( int i = 0 ; i < Num ; ++ i ) { buffer [ curpos ] = LLVM,NVPTX,130,"AggBuffer ( unsigned _size , raw_ostream & _O , AsmPrinter & _AP ) : O ( _O ) , AP ( _AP ) { buffer = new unsigned char [_size];" LLVM,NVPTX,131,getTargetStreamer() ) -> closeLastSection(); LLVM,NVPTX,132,for (const GlobalVariable *GV : gvars) { LLVM,NVPTX,133, LLVM,NVPTX,134,"O << ; getSymbol ( GVar ) -> print ( O , MAI ) ; O << ; return ; } if ( ETy -> isFloatingPointTy ( ) || ETy -> isIntOrPtrTy ( ) ) { O << " LLVM,NVPTX,135,The LLVM,NVPTX,136,return true; LLVM,NVPTX,137,O ) ; break ; } } } LLVM,NVPTX,138,"for ( const User * U : F -> users ( ) ) { if ( const Constant * C = dyn_cast < Constant > ( U ) ) { if ( usedInGlobalVarDef ( C ) ) { emitDeclaration ( F , O ) ; break ; } if ( useFuncSeen ( C , seenMap ) ) { emitDeclaration ( F , O ) ; break ; } } if ( ! isa < Instruction > ( U ) ) continue ; const Instruction * instr = cast < Instruction > ( U ) ;" LLVM,NVPTX,139, LLVM,NVPTX,140,"if ( InterleaveSrc ) this->emitSrcInText(fileName, [/INSERT_CODE_HERE]);" LLVM,NVPTX,141, LLVM,NVPTX,142,return reader; LLVM,NVPTX,143,if ( ! reader ) { reader = new LineReader ( filename ) ; } if ( reader -> fileName ( ) != filename ) { delete reader ; reader = new LineReader ( filename ) ; } LLVM,NVPTX,144, LLVM,NVPTX,145, LLVM,NVPTX,146,OutContext ) ) ; break ; } break ; } break ; case MachineOperand :: MO_Immediate : { const ConstantInt * Cnt = MO . getImm ( ) ; const APInt & Val = Cnt -> getValue ( ) ; switch ( Cnt -> getType ( ) -> getTypeID ( ) ) { default : report_fatal_error ( ) ; break ; case Type :: IntegerTyID : MCOp = MCOperand :: createImm ( Val ) ; break ; } break ; } break ; case MachineOperand :: MO_ LLVM,NVPTX,147,"O << ; getSymbol ( GVar ) -> print ( O , MAI ) ; O << ; O << ElementSize / ; } } } } else { if ( ! GVar -> getInitializer ( ) -> isNullValue ( ) && ! isa < UndefValue > ( GVar -> getInitializer ( ) ) ) { report_fatal_error ( + GVar -> getName ( ) + + Twine ( PTy -> getAddressSpace" LLVM,NVPTX,148,"if ( Ty -> isFloatingPointTy ( ) || Ty -> isIntegerTy ( ) ) { unsigned size = 32; if (auto *ITy = dyn_cast(Ty)) { size = ITy->getBitWidth(); if (size < 32) size = 32; } else { assert(Ty->isFloatingPointTy() && ""Invalid type""); size = Ty->getPrimitiveSizeInBits(); } O << ""i"" << size; } else if (isa :: GLOBAL: O << ; break; case :: SHARED: O << ; break; case addZeros(s); LLVM,NVPTX,159,"oneFunc , flag );" LLVM,NVPTX,160,OutStreamer.EmitRawText(StringRef(M.getModuleInlineAsm())); LLVM,NVPTX,161, LLVM,NVPTX,162,OutStreamer . EmitRawText ( StringRef ( ) ) ; VRegMapping . clear ( ) ; LLVM,NVPTX,163,O ); LLVM,NVPTX,164,O << * MF; LLVM,NVPTX,165, LLVM,NVPTX,166,O << ; break ; case llvm :: ADDRESS_SPACE_GLOBAL [/INST] O << ; break ; case llvm :: ADDRESS_SPACE_SHARED [/INST] O << ; break ; case llvm :: ADDRESS_SPACE_LOCAL [/INST] O << ; break ; case llvm :: ADDRESS_SPACE_PRIVATE [/INST] O << ; break ; case ll LLVM,NVPTX,167, LLVM,NVPTX,168,M.global_end(); I != E; ++I) { const GlobalVariable *GV = &*I; if (GVVisited.count(GV)) continue; GVVisiting.insert(GV); for (User::const_op_iterator U = GV->op_begin(); U != GV->op_end(); ++U) { const Value *V = *U; if (const GlobalVariable *GV2 = dyn_cast(V)) { if (GVVisiting.count(GV2)) { LLVM,NVPTX,169, LLVM,NVPTX,170, LLVM,NVPTX,171,"EmitToStreamer(OutStreamer, Inst);" LLVM,NVPTX,172, LLVM,NVPTX,173,DebugLoc curLoc = MI->getDebugLoc(); LLVM,NVPTX,174,O << ; LLVM,NVPTX,175,else O << << GVar -> getAlignment ( ) ; if ( ETy -> isSingleValueType ( ) ) { O << ; O << getPTXFundamentalTypeStr ( ETy ) ; O << ; O << * getSymbol ( GVar ) ; return ; } int64_t ElementSize = ; switch ( ETy -> getTypeID ( ) ) { case Type :: StructTyID : case Type :: ArrayTyID : case Type :: VectorTyID : ElementSize LLVM,NVPTX,176,temp << reader -> readLine ( line ) ; temp << ; this -> OutStreamer . EmitRawText ( Twine ( temp . str () ) ) ; LLVM,NVPTX,177, LLVM,NVPTX,178,return false; LLVM,NVPTX,179,bool AsmPrinter::isImageType(const Type *Ty) { LLVM,NVPTX,180,RegisterAsmPrinter < AsmPrinter > X; LLVM,NVPTX,181,"return LowerConstant(cast(CE->getOperand(0)), AP);" LLVM,NVPTX,182,true ; } return false ; } LLVM,NVPTX,183,"AP . nvptxSubtarget . is64Bit ( ) ? 8 : 4 ) ; } else { O << * ( v , [/INST] AP . nvptxSubtarget . is64Bit ( ) ? 8 : 4 ) ; } } else { O << ; } } }" LLVM,NVPTX,184,case MachineOperand::MO_GlobalAddress: O << *getSymbol(MO.getGlobal()) LLVM,NVPTX,185,2 LLVM,NVPTX,186,( ) ) { elems = vtparts [ i ] . getVectorNumElements ( ) ; elemtype = vtparts [ i ] . getVectorElementType ( ) ; } O << << elems << << TLI -> getTypeName ( elemtype ) << ; if ( i + 1 != e ) O << ; } } } LLVM,NVPTX,187,( GVar ) ; O << ; } else { O << * getSymbol ( GVar ) ; } return ; } if ( const ConstantPointerNull * CPNull = dyn_cast < ConstantPointerNull > ( v ) ) { O << ; return ; } if ( const UndefValue * UV = dyn_cast < UndefValue > ( v ) ) { O << ; return ; } if ( const ConstantInt * CI = dyn_cast < ConstantInt > ( v ) ) { O << CI LLVM,NVPTX,188,[PYTHON] void AsmPrinter :: recordAndEmitFilenames ( Module & M ) { DebugInfoFinder DbgFinder ; DbgFinder . processModule ( M ) ; unsigned i = 0 ; for ( DICompileUnit DIUnit : DbgFinder . compile_units ( ) ) { StringRef Filename ( DIUnit . getFilename ( ) ) ; StringRef Dirname ( DIUnit . getDirectory ( ) ) ; SmallString < 128 > FullPathName = Dirname ; if ( ! Dirname . empty ( LLVM,NVPTX,189, LLVM,NVPTX,190, LLVM,NVPTX,191,return true; LLVM,NVPTX,192,if ( const Instruction * instr = dyn_cast < Instruction > ( U ) ) { if ( instr -> getParent ( ) && instr -> getParent ( ) -> getParent ( ) ) { const Function * curFunc = instr -> getParent ( ) -> getParent ( ) ; if ( oneFunc && ( curFunc != oneFunc ) ) return false ; oneFunc = curFunc ; } } } LLVM,NVPTX,193,"VisitGlobalVariableForEmission(GV, Order, Visited, Visiting);" LLVM,NVPTX,194,"for ( DenseSet < const GlobalVariable * > :: iterator I = Others . begin ( ) , E = Others . end ( ) ; I != E ; ++ I )" LLVM,NVPTX,195,"delete [ ] is a JavaScript operator that deletes a property from an object. The syntax for using delete is as follows: delete object.property; For example: let person = { name: ""John"", age: 30 }; delete person.age; console.log(person);" LLVM,NVPTX,196, LLVM,NVPTX,197,"O << << sz << << totalsz << ; } else llvm_unreachable ( ) ; } else { SmallVector < EVT , > vtparts ; ComputeValueVTs ( * TLI , DL , Ty , vtparts ) ; unsigned idx = ; for ( unsigned i = , e = vtparts" LLVM,NVPTX,198,i = 0; LLVM,NVPTX,199, LLVM,NVPTX,200,O << ; O << ; O << ; unsigned PTXVersion = STI . getPTXVersion ( ) ; O << < LLVM,NVPTX,201,if (isLoopHeaderOfNoUnroll(MBB)) { LLVM,NVPTX,202,"void AsmPrinter :: EmitBasicBlockStart ( const MachineBasicBlock & MBB ) { OS << ""BB"" << MBB.getNumber() << "":\n""; for (auto &Inst : MBB) { EmitInstruction(Inst); } }" LLVM,NVPTX,203,OutStreamer.AddBlankLine(); LLVM,NVPTX,204,"( TD , ETy ) ; alignStruct = std::max ( alignStruct , align ) ; } return alignStruct ; } return TD -> getABITypeAlignment ( Ty ) ; }" LLVM,NVPTX,205, LLVM,NVPTX,206,size = Ty -> getPrimitiveSizeInBits ( ) ; } O << << size << ; } else if ( isa < PointerType > ( Ty ) ) { O << << TLI -> getPointerTy ( ) . getSizeInBits ( ) << ; } else if ( ( Ty -> getTypeID ( ) == Type :: StructTyID ) || isa < VectorType > ( Ty ) ) { unsigned tot LLVM,NVPTX,207,O << << rcname << << rcStr << << ( n + ) << << std::endl; LLVM,NVPTX,208,oneFunc = curFunc; LLVM,NVPTX,209, LLVM,NVPTX,210,"O << << sz << ; printParamName ( I , paramIndex , O ) ; continue ; } unsigned align = PAL . getParamAlignment ( paramIndex + ) ; if ( align == ) align = TD -> getABITypeAlignment ( ETy ) ; unsigned sz = TD -> getTypeAllocSize ( ETy ) ; O << << align << ; printParamName ( I , paramIndex , O ) ; continue" LLVM,NVPTX,211,CleanNameStream << C; } LLVM,NVPTX,212, LLVM,NVPTX,213,"RHS , Ctx ) ; case Instruction :: Sub : return MCBinaryExpr :: CreateSub ( LHS , RHS , Ctx ) ; case Instruction :: Mul : return MCBinaryExpr :: CreateMul ( LHS , RHS , Ctx ) ; case Instruction :: SDiv : return MCBinaryExpr :: CreateSDiv ( LHS , RHS , Ctx ) ; case Instruction :: SRem : return MCBinaryExpr :: CreateSRem ( LHS , RHS , Ctx ) ; case Instruction :: Shl : return MCBinaryExpr :: CreateShl ( LHS ," LLVM,NVPTX,214,"case MachineOperand::MO_ConstantPoolIndex: MCOp = MCOperand::CreateExpr(MCSymbolRefExpr::Create(MO.getCP (), OutContext)); break;" LLVM,NVPTX,215,"const MachineOperand & MO = MI->getOperand(opNum); switch (MO.getType()) { case MachineOperand::MO_Register: if (TargetRegisterInfo::isPhysicalRegister(MO.getReg())) { if (MO.getReg() == ) O << DEPOTNAME << getFunctionNumber(O); else O << InstPrinter::getRegisterName(MO.getReg()); } else { emitVirtualRegister(MO.getReg(), O);" LLVM,NVPTX,216, LLVM,NVPTX,217,"if ( ( nvptxSubtarget . getDrvInterface ( ) == ""nvptx"" ) || ( nvptxSubtarget . getDrvInterface ( ) == ""nvptx64"" ) )" LLVM,NVPTX,218,OutStreamer.AddComment(); LLVM,NVPTX,219,emitInlineAsm ( M . getModuleInlineAsm ( ) ) ; } LLVM,NVPTX,220, LLVM,NVPTX,221,if (static_castTargetMachine&>(TM).getDrvInterface()) LLVM,NVPTX,222,temp << reader->readLine(); LLVM,NVPTX,223,temp << reader->readLine(line); LLVM,NVPTX,224,break; } LLVM,NVPTX,225,O << << * getSymbol ( GVar ) << ; LLVM,NVPTX,226,"ETy -> getPointerElementType ( ) ) ; break ; default : llvm_unreachable ( ""Invalid type for global variable"" ) ; } O << << ElementSize ; if ( GVar -> hasInitializer ( ) ) { if ( ( PTy -> getAddressSpace ( ) == llvm :: ADDRESS_SPACE_GLOBAL ) || ( PTy -> getAddressSpace ( ) == llvm :: ADDRESS_SPACE_CONST ) ) { const Constant * Initializer = GVar -> getInitializer ( ) ; if ( ! Initializer" LLVM,NVPTX,227,"void AsmPrinter::printParamName(int paramIndex, const char* paramName) { m_out << paramName; }" LLVM,NVPTX,228,O << << vtparts [ i ] . getSizeInBits ( ) << ; if ( i + 1 != e ) O << ; } } LLVM,NVPTX,229, LLVM,NVPTX,230, LLVM,NVPTX,231,} unsigned int numVRs = MRI -> getNumVirtRegs ( ) ; for ( unsigned i = ; i < numVRs ; i ++ LLVM,NVPTX,232,"O << << ( int ) getOpenCLAlignment ( DL , ETy ) ;" LLVM,NVPTX,233,return Ret; LLVM,NVPTX,234,"O << ""ret "" << size << "" "" << totalsz << "" "" << retAlignment;" LLVM,NVPTX,235,"AggBuffer ( unsigned _size , raw_ostream & _O , AsmPrinter & _AP ) : O ( _O ) , AP ( _AP ) {" LLVM,NVPTX,236,delete[] gv_array; LLVM,NVPTX,237,static_castTargetStreamer*>(OutStreamer->getTargetStreamer())->EmitRawText(); LLVM,NVPTX,238,return Result; LLVM,NVPTX,239, LLVM,NVPTX,240,"O, MF, Str);" LLVM,NVPTX,241, LLVM,NVPTX,242, LLVM,NVPTX,243,"CurrentFnSym -> print ( O , MAI ) ; emitFunctionParamList ( * MF , O ) ; if ( isKernelFunction ( * F ) ) emitKernelFunctionDirectives ( * F , O ) ; OutStreamer -> EmitRawText ( O . str ( ) ) ; VRegMapping . clear ( ) ; OutStreamer -> EmitRawText ( StringRef ( ) ) ;" LLVM,NVPTX,244,OutStreamer->AddBlankLine(); LLVM,NVPTX,245,"void AsmPrinter::EmitInstruction(const MachineInstr *MI) { MCInst Inst; lowerToMCInst(MI, Inst); EmitToStreamer(*OutStreamer, Inst); }" LLVM,NVPTX,246, LLVM,NVPTX,247, LLVM,NVPTX,248,"case Instruction::Add: { const MCExpr *LHS = lowerConstantForGV(CE->getOperand(0), ProcessingGeneric); const MCExpr *RHS = lowerConstantForGV(CE->getOperand(1), ProcessingGeneric); switch (CE->getOpcode()) { case Instruction::Add: return MCBinaryExpr::createAdd(LHS, RHS, Ctx); case Instruction::Sub: return MCBinaryExpr::createSub(LHS, RHS, Ctx); case Instruction::Mul:" LLVM,NVPTX,249,case Instruction::IntToPtr: { LLVM,NVPTX,250, LLVM,NVPTX,251, LLVM,NVPTX,252,bool Result = AsmPrinter::runOnMachine LLVM,NVPTX,253, LLVM,NVPTX,254,"if ( GlobalVariable * GV = dyn_cast < GlobalVariable > ( V ) ) Globals . insert ( GV ) ; else { if ( User * U = dyn_cast < User > ( V ) ) { for ( unsigned i = 0 , e = U -> getNumOperands ( ) ; i != e ; ++ i ) { DiscoverDependentGlobals ( U -> getOperand ( i ) ) ; } } } } } } } }" LLVM,NVPTX,255,Here LLVM,NVPTX,256, LLVM,NVPTX,257,Here is a possible completion of the last statement: O << << std::endl; LLVM,NVPTX,258,"return MCBinaryExpr::Create(LHS, RHS, Ctx);" LLVM,NVPTX,259,"else if ( ! strcmp ( Modifier , ) ) { if ( Imm == :: V2 ) O << ; else if ( Imm == [/INST] This statement is checking if the modifier string is equal to a specific string literal, and if the immediate value i" LLVM,NVPTX,260,Visited.insert(GV);` LLVM,NVPTX,261, LLVM,NVPTX,262,"void AsmPrinter::EmitFunctionBodyStart() { VRegMapping.clear(); OutStreamer->EmitRawText(StringRef("""")); setAndEmitFunctionVirtualRegisters(*MF); SmallString Str;" LLVM,NVPTX,263,OutStreamer->EmitRawText(O.str()); LLVM,NVPTX,264,O << TM LLVM,NVPTX,265,const Subtarget & STI = * static_cast < const Subtarget * > ( NTM.getSubtargetImpl() ); LLVM,NVPTX,266,Globals.push_back(&I); LLVM,NVPTX,267, LLVM,NVPTX,268,return; LLVM,NVPTX,269,void AsmPrinter :: EmitBasicBlockStart ( const MachineBasicBlock &MBB ) { } LLVM,NVPTX,270, LLVM,NVPTX,271,OutStreamer->EmitRawText(StringRef()); LLVM,NVPTX,272, LLVM,NVPTX,273,"O << << sz << ; printParamName ( I , paramIndex , O ) ; if ( j < je - ) O << ; ++ paramIndex ; } if ( i < e - ) O << ; } -- paramIndex ; }" LLVM,NVPTX,274, LLVM,NVPTX,275,for (unsigned i = 0; i < TRI->getNumRegClasses(); i++) { LLVM,NVPTX,276,break; LLVM,NVPTX,277,switch (MI.getOpcode()) { LLVM,NVPTX,278,O << ; LLVM,NVPTX,279,GlobalsEmitted = true; LLVM,NVPTX,280,getOptimalAlignForParam(Ty); LLVM,NVPTX,281,} else { LLVM,NVPTX,282,"O << ""ret "" << vtparts[0] << "" "" << vtparts[1] << "" "" << vtparts[2] << "" "" << vtparts[3] << "" "" << vtparts[4] << "" "" << vtparts[5] << "" "" << vtparts[6] << "" "" << vtparts[7] << "" "" << vtparts[8] << "" "" << vtparts[9] << "" "" << vtparts[10] << "" """ LLVM,NVPTX,283, LLVM,NVPTX,284,"O << << sz << ; printParamName ( I , paramIndex , O ) ; if ( j < je - 1 ) O << ; continue ; } } } }" LLVM,NVPTX,285, LLVM,NVPTX,286,") ; Op = ConstantExpr :: getIntegerCast ( Op , Ty , false ) ; return lowerConstantForGV ( Op , ProcessingGeneric ) ; } }" LLVM,NVPTX,287,case Instruction :: GetElementPtr: { LLVM,NVPTX,288,report_fatal_error ( ) ; return true ; } if ( ! isEmptyXXStructor ( LLVM,NVPTX,289,filenameMap.end() ) { filenameMap[fileName] = curLoc; } LLVM,NVPTX,290,"OutStreamer.EmitDwarfFileDirective(i, , Filename);" LLVM,NVPTX,291,for (int i = 0; i < filenameMap.size(); i++) { LLVM,NVPTX,292,"-> getType ( ) ; Op = ConstantExpr :: getIntegerCast ( Op , Ty , true ) ; return LowerConstant ( Op , AP ) ; } } }" LLVM,NVPTX,293, LLVM,NVPTX,294,case MachineOperand::MO_MachineBasicBlock: LLVM,NVPTX,295,"ConvertDoubleToBytes ( ptr , float64 ) ; aggBuffer -> addBytes ( ptr , , Bytes ) ; } else llvm_unreachable ( ) ; } } } }" LLVM,NVPTX,296,return GlobalsEmitted; LLVM,NVPTX,297, LLVM,NVPTX,298,"return MCBinaryExpr::CreateOr(LHS, RHS, Ctx);" LLVM,NVPTX,299, LLVM,NVPTX,300,} if ( ! isEmptyXXStructor ( M . getNamedGlobal ( ) ) ) { report_fatal_error ( ) ; return true ; } if ( ! isEmptyXXStructor ( M . getNamedGlobal ( ) LLVM,NVPTX,301,} LLVM,NVPTX,302,O << << totalsz << ; LLVM,NVPTX,303,O << << idx ; if ( j < je - 1 ) O << ; } } } } } LLVM,NVPTX,304,return ret; LLVM,NVPTX,305,delete[] gv_array; LLVM,NVPTX,306, LLVM,NVPTX,307,if ( ! M . getModuleInlineAsm ( ) ) LLVM,NVPTX,308,O << ; } LLVM,NVPTX,309, LLVM,NVPTX,310, LLVM,NVPTX,311, LLVM,NVPTX,312, LLVM,NVPTX,313,"printParamName(I, paramIndex, O);" LLVM,NVPTX,314, LLVM,NVPTX,315,"] . getVectorElementType ( ) ; } for ( unsigned j = , je = elems ; j != je ; ++ j ) { unsigned sz = elemtype . getSizeInBits ( ) ; if ( elemtype . isInteger ( ) && ( sz < ) ) sz = ; totalsz += sz / ; } } unsigned retAlignment = ; if ( ! llvm :: getAlign ( * F , , retAlignment" LLVM,NVPTX,316,"i ] ; if ( vtparts [ i ] . isVector ( ) ) { elems = vtparts [ i ] . getVectorNumElements ( ) ; elemtype = vtparts [ i ] . getVectorElementType ( ) ; } for ( unsigned j = 0 , je = elems ; j != je ; ++ j ) { unsigned sz = elemtype . getSizeInBits ( ) ; if ( elemtype . isInteger ( ) && ( sz < 32 ) ) sz = 32 ; totalsz += sz / 8 ; } } unsigned retAlignment =" LLVM,NVPTX,317,"O << << Ty -> getPrimitiveSizeInBits ( ) << ; printParamName ( I , paramIndex , O ) ; continue ; }" LLVM,NVPTX,318,O << ; if ( [/INST] The last statement of the code snippet is: LLVM,NVPTX,319,"( ) , ProcessingGeneric ) ; return MCBinaryExpr :: createAdd ( LHS , RHS , Ctx ) ; }" LLVM,NVPTX,320,"O << ""["" << sz << ""]"" << idx;" LLVM,NVPTX,321,"( ) ; if ( Op -> getType ( ) -> isPointerTy ( ) ) return lowerConstantForGV ( Op , ProcessingGeneric ) ; std :: string S ; raw_string_ostream OS ( S ) ; OS << ; CE -> printAsOperand ( OS , false , ! MF ? : MF -> getFunction ( ) -> getParent ( ) ) ; report_fatal_error ( OS . str ( ) ) ; } case Instruction :: PtrToInt : return lowerConstantFor" LLVM,NVPTX,322,case Instruction::ZExt: LLVM,NVPTX,323,"MO_ExternalSymbol : { const char * symbname = MO . getSymbolName ( ) ; if ( strstr ( symbname , ) == symbname ) { unsigned index ; sscanf ( symbname + , , & index ) ; printParamName ( index , O ) ; } else if ( strstr ( symbname , ) == symbname ) { unsigned index ; sscanf ( symbname + , ) LLVM,NVPTX,327,TD->getTypeAllocSize(ETy); LLVM,NVPTX,328,"O << ""]"";" LLVM,NVPTX,329,"unsigned retAlignment = ; if ( ! llvm :: getAlign ( * F , , retAlignment ) ) retAlignment = TD -> getABITypeAlignment ( Ty ) ; O << << retAlignment << << totalsz <<" LLVM,NVPTX,330,"Type :: VectorTyID : ElementSize = TD -> getTypeAllocSize ( ETy ) ; break ; default : llvm_unreachable ( ""Invalid type for global variable!"" ) ; } O << << ElementSize ; O << ; O << * getSymbol ( GVar ) ; return ; }" LLVM,NVPTX,331,"O << "".align "" << (int) TD->getPrefTypeAlignment(ETy);" LLVM,NVPTX,332,"return MCBinaryExpr::Create(Opcode, LHS, RHS, Ctx);" LLVM,NVPTX,333,return true; LLVM,NVPTX,334,case : LLVM,NVPTX,335,"getType ( ) ) ; for ( unsigned i = , e = CPV -> getNumOperands ( ) ; i != e ; ++ i ) bufferLEByte ( cast < Constant > ( CPV -> getOperand ( i ) ) , , aggBuffer ) ; return ; } } if ( isa < ConstantArray > ( CPV ) ) { if ( CPV -> getNumOperands ( ) ) for ( unsigned i = , e = CPV -> getNumOperands ( ) ; i != e ;" LLVM,NVPTX,336,if (!gv->hasInternalLinkage()) return false; LLVM,NVPTX,337, LLVM,NVPTX,338,p[i] = (unsigned char) (i % 256); LLVM,NVPTX,339, LLVM,NVPTX,340,if (const GlobalVariable *GV = dyn_cast(V)) LLVM,NVPTX,341, LLVM,NVPTX,342,OutStreamer->AddBlankLine(); LLVM,NVPTX,343,void AsmPrinter :: EmitBasicBlockStart ( const MachineBasicBlock & MBB ) const { AsmPrinter :: EmitBasicBlockStart ( MBB ) ; if ( isLoopHeaderOfNoUnroll ( MBB ) ) OutStreamer -> EmitLoopHeader ( MBB ) ; } LLVM,NVPTX,344,"""loop_header_unroll_disable"" ) ); if ( isLoopHeaderOfNoUnroll ( MBB ) ) OutStreamer -> EmitRawText ( StringRef ( ""loop_header_unroll_disable"" ) );" LLVM,NVPTX,345,"( ) ; if ( caller -> isDeclaration ( ) ) continue ; if ( seenMap [ caller ] ) continue ; seenMap [ caller ] = true ; emitDeclaration ( F , O ) ; } } }" LLVM,NVPTX,346,OutStreamer -> EmitRawText ( StringRef ( ) ); LLVM,NVPTX,347,OutStreamer -> EmitRawText ( StringRef str ); LLVM,NVPTX,348,void AsmPrinter :: EmitFunctionBodyStart ( ) { VRegMapping . clear ( ) ; OutStreamer -> EmitRawText ( StringRef ( ) ) ; setAndEmitFunctionVirtualRegisters ( * MF ) ; SmallString < > Str ; raw_svector_ostream O ( Str ) ; } LLVM,NVPTX,349, LLVM,NVPTX,350,emitFunctionParamList(F); LLVM,NVPTX,351,unsigned RegNo = MI->getOperand()->getReg(); LLVM,NVPTX,352,O << << mincta << ; LLVM,NVPTX,353,return; LLVM,NVPTX,354, LLVM,NVPTX,355,break; LLVM,NVPTX,356, LLVM,NVPTX,357,"os) { os << ""%"" << vr; }" LLVM,NVPTX,358,void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . addRequired < MachineLoopInfo > ( ); } LLVM,NVPTX,359,case Type::DoubleTyID: LLVM,NVPTX,360,return reader; LLVM,NVPTX,361,return reader; LLVM,NVPTX,362,Expr ); LLVM,NVPTX,363,const MCExpr * Expr = Symbol->GetExpr(); LLVM,NVPTX,364, LLVM,NVPTX,365,return PI != TypeNameMap.end() && (PI->second.compare() || !PI->second.compare()); LLVM,NVPTX,366,"iterator it = ImageTypes.find(Ty); return it != ImageTypes.end() && it->second != ""image"";" LLVM,NVPTX,367, LLVM,NVPTX,368,MachineLoopInfo & LI = getAnalysis(); LLVM,NVPTX,369,c_str ( ) ) ; } LLVM,NVPTX,370,RegisterAsmPrinter < AsmPrinter > Y ( TheTarget64 ); LLVM,NVPTX,371,RegisterAsmPrinter < AsmPrinter > X (); LLVM,NVPTX,372,return Base + Offset; LLVM,NVPTX,373,return false; LLVM,NVPTX,374,std::string *SymNamePtr LLVM,NVPTX,375,"bool AsmPrinter::lowerOperand(const MachineOperand &MO, MCOperand &MCOp) {" LLVM,NVPTX,376,OutMI.addOperand(MCOp); LLVM,NVPTX,377,unsigned int nextSymbolPos = symbolPosInBuffer[nSym]; LLVM,NVPTX,378,"AsmPrinter :: PrintAsmMemoryOperand ( const MachineInstr * MI , unsigned OpNo , unsigned AsmVariant , const char * ExtraCode , raw_ostream & O ) { if ( ExtraCode && ExtraCode [ ] ) return true ; O << '[' ; printMemOperand ( MI , OpNo , O ) ; O << ']' ; return false ; }" LLVM,NVPTX,379,if (ExtraCode[NUM_LIT] != NUM_LIT[/INST] The last statement of this code snippet is: LLVM,NVPTX,380,} else { LLVM,NVPTX,381,case MCBinaryExpr::Add: LLVM,NVPTX,382, LLVM,NVPTX,383,"if ( MO . getReg ( ) == ""rax"" )" LLVM,NVPTX,384,"void AsmPrinter::printParamName(int paramIndex, const char* paramName) { m_out << paramName; }" LLVM,NVPTX,385,"CurrentFnSym -> print ( O ," LLVM,NVPTX,386,const Function *F = MF.getFunction(); LLVM,NVPTX,387, LLVM,NVPTX,388, LLVM,NVPTX,389, LLVM,NVPTX,390,for (DISubprogram *SP : DbgFinder.subprograms()) { LLVM,NVPTX,391,return AsmPrinter::runOnMachineFunction(F); LLVM,NVPTX,392,F ); LLVM,NVPTX,393,if (n) { LLVM,NVPTX,394,unsigned int numVRs = MRI->getNumVirtRegs(); LLVM,NVPTX,395,for (const User *U : C->users()) { LLVM,NVPTX,396,if ( const Instruction * instr = dyn_cast < Instruction > ( U ) ) { if ( instr -> getParent ( ) && instr -> getParent ( ) -> getParent ( ) ) { const Function * curFunc = instr -> getParent ( ) -> getParent ( ) ; if ( oneFunc && ( curFunc != oneFunc ) ) return false ; oneFunc = curFunc ; } } } LLVM,NVPTX,397,} else if ( const Instruction * I = dyn_cast < Instruction > ( U ) ) { const BasicBlock * bb = I -> getParent ( ) ; if ( ! bb ) continue ; const Function * caller = bb -> getParent ( ) ; if ( ! caller ) continue ; if ( seenMap . find ( caller ) != seenMap . end ( ) ) { LLVM,NVPTX,398,"LineReader reader = new LineReader(""path/to/file.txt"");" LLVM,NVPTX,399,~ LineReader ( ) { fstr . close ( ); } LLVM,NVPTX,400,class AsmPrinter { LLVM,NVPTX,401, LLVM,NVPTX,402,ValidNameStream << C; LLVM,NVPTX,403, LLVM,NVPTX,404,F.setName(cleanUpName(F.getName())); LLVM,NVPTX,405, LLVM,NVPTX,406,"llvm::createAtomicLowerPass(llvm::Module &M, llvm::TargetMachine *TM, llvm::TargetLibraryInfo *TLI, llvm::TargetTransformInfo *TTI, llvm::PassBuilder::OptimizationLevel OptLevel)" LLVM,NVPTX,407,void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . setPreservesCFG ( true ); } LLVM,NVPTX,408,"StringRef getPassName() const override { return ""MyPass""; } Explanation:" LLVM,NVPTX,409,return Changed; LLVM,NVPTX,410,return (SrcTy->getAddressSpace() != AddressSpace::ADDRESS_SPACE_GENERIC && DestTy->getAddressSpace() != AddressSpace::ADDRESS_SPACE_GENERIC); LLVM,NVPTX,411,"MI -> setOperand ( Idx , Cast -> getOperand ( 0 ) ) ) ; } } }" LLVM,NVPTX,412,return true; LLVM,NVPTX,413,"getType ( ) , , GEPI ) ) ; } }" LLVM,NVPTX,414,if ( DisableFavorNonGeneric ) return false ; LLVM,NVPTX,415,if (DisableFavorNonGeneric) LLVM,NVPTX,416,return false; LLVM,NVPTX,417,return false; LLVM,NVPTX,418,"Operator * Cast = cast < Operator > ( BC -> getOperand ( ) ) ; Value * Src = Cast -> getOperand ( ) ; Type * TypeOfNewCast = PointerType :: get ( BC -> getType ( ) -> getPointerElementType ( ) , Src -> getType ( ) -> getPointerAddressSpace ( ) ) ; if ( BitCastInst * BCI = dyn_cast < BitCastInst > ( BC ) ) { Value * NewCast = new BitCastInst ( Src , TypeOfNew" LLVM,NVPTX,419,GEP->replaceAllUsesWith(NewASC); LLVM,NVPTX,420,"getOperand(0) ), Indices, """", GEPI ); NewGEP->setIsInBounds(GEP->isInBounds()); NewGEP->takeName(GEP); NewASC = new AddrSpaceCastInst(NewGEP, GEP->getType(), """", GEPI); GEP->replaceAllUsesWith(NewASC); }" LLVM,NVPTX,421, LLVM,NVPTX,422, LLVM,NVPTX,423,return nullptr; LLVM,NVPTX,424,"TypeOfNewCast ) ; NewBC = new AddrSpaceCastInst ( NewCast , BC -> getType ( ) , , BCI ) ; NewBC -> takeName ( BC ) ; BC -> replaceAllUsesWith ( NewBC ) ; } return NewBC ; }" LLVM,NVPTX,425,"isInBounds ( ) ) ; NewASC = new AddrSpaceCastInst ( NewGEP , GEP -> getType ( ) , , GEPI ) ; NewASC -> takeName ( GEP ) ; GEP -> replaceAllUsesWith ( NewASC ) ; }" LLVM,NVPTX,426,if (SrcTy->getElementType() != DestTy->getElement LLVM,NVPTX,427, LLVM,NVPTX,428,return Changed; LLVM,NVPTX,429,"> ( I ) ) { Changed |= optimizeMemoryInstruction ( I , ) ; } } } return Changed ; }" LLVM,NVPTX,430,return; LLVM,NVPTX,431,"MachineInstr & MI ) { Register FP = MF.getFramePointer(); Register SP = MF.getStackPointer(); int Offset = MI.getOperand(0).getImm(); MachineInstrBuilder MIB(MI); MIB.createStore(SP, FP, Offset" LLVM,NVPTX,432,"unsigned MovDepotOpcode = (Is64Bit ? : ); if (!MR.use_empty()) { MI = BuildMI(MBB, MI, dl, MF.getSubtarget().get" LLVM,NVPTX,433,return MF.hasFP(); LLVM,NVPTX,434,bool FrameLowering :: hasFP ( const MachineFunction &MF) const { return MF.hasFP(); } LLVM,NVPTX,435,"MachineBasicBlock::iteratorFrameLowering::eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, MachineBasicBlock::iterator I) const { return MBB.erase(I); }" LLVM,NVPTX,436,"MachineBasicBlock::iterator eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, MachineBasicBlock::iterator I) { if (!I->isCallFramePseudoInstruction()) { return I; } CallFrameInst *CFI = dyn_cast(I); eliminateCallFramePseudoInstr(MF" LLVM,NVPTX,437,"void ISA_LITFrameLowering::emitPrologue(MachineFunction &MF, MachineBasicBlock &MBB) const { if (MF.getFrameInfo().hasStackObjects()) { assert(&MF.front() == &MBB && """"); MachineInstr *MI = &MBB.front(); MachineRegisterInfo &MR = MF.getRegInfo(); const ISA_LITRegisterInfo *NRI = MF.getSubtarget().getRegisterInfo(); DebugLoc dl = Debug" LLVM,NVPTX,438,TargetFrameLowering::getDwarfFrameBase(const MachineFunction &MF) { return DwarfFrameBase::getDwarfFrameBase(MF); } LLVM,NVPTX,439, LLVM,NVPTX,440,"unsigned CvtaLocalOpcode = ( Is64Bit ? : ) ; unsigned MovDepotOpcode = ( Is64Bit ? : ) ; if ( ! MR . use_empty ( ) ) { MI = BuildMI ( MBB , MI , dl , MF . getSubtarget ( ) . getInstrInfo ( ) -> get ( CvtaLocalOpcode )" LLVM,NVPTX,441, LLVM,NVPTX,442, LLVM,NVPTX,443,"void FrameLowering::eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, MachineBasicBlock::iterator I) {" LLVM,NVPTX,444,I ); LLVM,NVPTX,445,"BuildMI(MBB, MI, dl, MF.getSubtarget().getInstrInfo()->get(), LocalReg).addImm(MF.getFunctionNumber());" LLVM,NVPTX,446,"int FrameLowering::getFrameIndexReference(const MachineFunction &MF, int FI, Register &FrameReg) const { const MachineFrameInfo &MFI = MF.getFrameInfo(); FrameReg = MFI.getFrameIndexReference(FI); }" LLVM,NVPTX,447,return true; LLVM,NVPTX,448,ParamTypes.push_back(GVType); LLVM,NVPTX,449,"Type *ResultType = PointerType::get(Type::getInt8Ty(Context), llvm::ADDRESS_SPACE_GENERIC);" LLVM,NVPTX,450,return NewValue; LLVM,NVPTX,451,N->dropAllReferences();` LLVM,NVPTX,452,"assert(GVMap.empty() && ""GVMap should be empty after replacement"");" LLVM,NVPTX,453,else { LLVM,NVPTX,454,return CVTA; LLVM,NVPTX,455,"for (GVMapTy::iterator I = GVMap.begin(), E = GVMap.end(); I != E;) {" LLVM,NVPTX,456,VM.clear(); LLVM,NVPTX,457,GVMap.erase(I); LLVM,NVPTX,458,"First, you will need to define the ""CVTAFunction""" LLVM,NVPTX,459,return NewValue; LLVM,NVPTX,460,return NewValue; LLVM,NVPTX,461, LLVM,NVPTX,462,GVMap.clear(); LLVM,NVPTX,463,[PYTHON] def complete_code(code): # Check if the last statement is complete if code.endswith(';'): return code # Remove any trailing whitespace code = code.rstrip() # Add the closing parenthesis and semicolon return f'{code});' [/INST] [PYTHON] def get_indentation(line): return len(line) - len(line.lstrip()) [/PYTHON] LLVM,NVPTX,464,"return Builder.CreateCast(Instruction::CastOps(C->getOpcode()), NewOperands[], C->getType());" LLVM,NVPTX,465, LLVM,NVPTX,466,GVMap.clear(); LLVM,NVPTX,467,"GVMap.find ( G ) ; if ( I != GVMap.end ( ) ) { NewOperand = I -> second ; } } } } if ( NewOperand != Operand ) { OperandChanged = true ; } NewOperands.push_back ( NewOperand ) ; } } if ( OperandChanged ) { N = MDNode :: get ( M , NewOperands ) ; } return N ; }" LLVM,NVPTX,468,return false; LLVM,NVPTX,469,"for (Module::iterator I = M.begin(), E = M.end(); I != E; ++I) {" LLVM,NVPTX,470,return CVTA; LLVM,NVPTX,471,"Function * CVTAFunction = Builder.CreateFunction(M, ""llvm.memcpy.p0i8.p0i8"", ParamTypes);" LLVM,NVPTX,472,GVMap.erase(GV); LLVM,NVPTX,473,I++ LLVM,NVPTX,474,); LLVM,NVPTX,475,AddressSpace::Generic ) ) ; } } return NewValue ; } LLVM,NVPTX,476,VM[GV] = NewGV; LLVM,NVPTX,477, LLVM,NVPTX,478,return false; LLVM,NVPTX,479,getContext ( ) ) ) ; return true ; } return false ; } LLVM,NVPTX,480,return false; LLVM,NVPTX,481,"bool replaceWithConstant(TextureHandle* TexHandle, ConstantInt* I) {" LLVM,NVPTX,482,"void ImageOptimizer :: replaceWith ( Instruction * From , ConstantInt * To ) { for ( CallInst :: use_iterator UI = From -> use_begin ( ) , UE = From -> use_end ( ) ; UI != UE ; ++ UI ) { if ( BranchInst * BI = dyn_cast < BranchInst > ( * UI ) ) { if ( BI -> isUnconditional ( ) ) continue ; BasicBlock * Dest ; if ( To -> isZero ( ) ) Dest = BI -> getSuccessor ( 0 ) ; else Dest = BI -> getSuccess" LLVM,NVPTX,483, LLVM,NVPTX,484, LLVM,NVPTX,485,"return CE->getWithOperands(NewOperands, TargetType, false, NewOperands[0]->getType());" LLVM,NVPTX,486,"PostorderStack , &Visited ) ; } } while ( !PostorderStack.empty() ) { std :: pair < Value * , bool > Pair = PostorderStack.back() ; PostorderStack.pop_back() ; if ( Pair.second ) { continue ; } Pair.second = true ; Value * V = Pair.first ; for ( User * U : V -> users() ) { if ( isa < Instruction > ( U ) && ( cast < Instruction > ( U ) ) . getParent() == &F ) { PostorderStack.push_back" LLVM,NVPTX,487,Visited ) ; } } return Postorder ; } LLVM,NVPTX,488,FunctionPass * llvm :: createInferAddressSpacesPass ( ) { LLVM,NVPTX,489, LLVM,NVPTX,490,") } ; default : llvm_unreachable ( ""Invalid opcode"" ) ; } } }" LLVM,NVPTX,491,"Optional NewAS = updateAddressSpace(*V, *InferredAddrSpace);" LLVM,NVPTX,492,return true; LLVM,NVPTX,493,if ( LLVM,NVPTX,494,InferredAddrSpace ); LLVM,NVPTX,495,InferredAddrSpace ) ; LLVM,NVPTX,496,return NewAS; LLVM,NVPTX,497,RawOutputStream &OS) { OS << ISA_LIT->getMnemonic(MI->getOpcode()) << '\t'; for (unsigned i = 0; i < MI->getNumOperands(); ++i) { const MCOperand &MO = MI->getOperand(i); if (MO.isReg()) { OS << '%' << ISA_ LLVM,NVPTX,498,"if ( ! strcmp ( Modifier , ) ) {" LLVM,NVPTX,499, LLVM,NVPTX,500,unsigned Reg = Op.getReg(); LLVM,NVPTX,501,unsigned VReg = RegNo & 0x1F; LLVM,NVPTX,502,"printOperands(MI, OS);" LLVM,NVPTX,503,"int64_t Imm = MO . getImm ( ) ; if ( strcmp ( Modifier , ) == ) { if ( Imm & :: FTZ_FLAG ) O << ; } else if ( strcmp ( Modifier , ) == ) { if ( Imm & :: SAT_FLAG ) O << ; } else if ( strcmp ( Mod" LLVM,NVPTX,504,unsigned VReg = RegNo & 0x1F; LLVM,NVPTX,505,"MRI , MAI , MII , STI ) { }" LLVM,NVPTX,506,"default: O << ""Unknown operator""; break;" LLVM,NVPTX,507, LLVM,NVPTX,508,default: LLVM,NVPTX,509,Annot ); LLVM,NVPTX,510,"printAnnotation ( OS , MI ) ;" LLVM,NVPTX,511,STR_LIT> ) ) { LLVM,NVPTX,512, LLVM,NVPTX,513,O << Sym.getName(); LLVM,NVPTX,514,else if (DestRC == &) LLVM,NVPTX,515,"return BuildMI(&MBB, DL, get()).addReg(Cond[].getReg()).addMBB(TBB);" LLVM,NVPTX,516," ? : ) ; } else { llvm_unreachable ( ""Unknown register class!"" ) ; }" LLVM,NVPTX,517, LLVM,NVPTX,518,"BuildMI(&MBB, DL, get()).addReg(Cond[].getReg()).addMBB(TBB);" LLVM,NVPTX,519,I -> eraseFromParent ( ) ; I = MBB . end ( ) ; if ( I == MBB . begin ( ) ) return ; -- I ; if ( I -> getOpcode ( ) != ) return ; I -> er LLVM,NVPTX,520,return ; LLVM,NVPTX,521,Cond[0].getReg() ) . addMBB(TBB); LLVM,NVPTX,522,Here is a possible completion of the code LLVM,NVPTX,523,return false; LLVM,NVPTX,524,Op = ; } LLVM,NVPTX,525, LLVM,NVPTX,526,else { LLVM,NVPTX,527,"const TargetRegisterClass * DestRC = MRI.getRegClass(DestReg); if (DestRC != SrcRC) report_fatal_error(""Invalid register class""); if (DestRC == &TargetRegisterClass::GPR) BuildMI(MBB, I, DL, get(Target" LLVM,NVPTX,528, LLVM,NVPTX,529,"assert ( Cond.size() == 1 ) && ""Invalid number of branch operands!"";" LLVM,NVPTX,530, LLVM,NVPTX,531, LLVM,NVPTX,532,return MI.getOperand().getImm(); LLVM,NVPTX,533, ) . getMBB ( ) ; Cond . push_back ( SecondLastInst -> getOperand ( ) ) ; FBB = LastInst -> getOperand ( ) . getMBB ( ) ; return false ; } if ( SecondLastInst -> getOpcode ( ) == && LastInst -> getOpcode ( ) == ) { TBB = SecondLastInst -> getOperand ( ) . getMBB ( ) ; Cond LLVM,NVPTX,534, LLVM,NVPTX,535,if (DestReg.contains(SrcReg) && SrcReg.contains(DestReg)) { LLVM,NVPTX,536,return MI.getOperand(); LLVM,NVPTX,537,const ISA_LIT>RegisterInfo & getRegisterInfo ( ) const { return registerInfo; } LLVM,NVPTX,538,if (FBB == ) { LLVM,NVPTX,539, LLVM,NVPTX,540, LLVM,NVPTX,541,unsigned InstrInfo :: RemoveBranch ( MachineBasicBlock & MBB ) const { LLVM,NVPTX,542,return IsKernelFn && GV -> onlyReadsMemory ( ) && GV -> hasNoAliasAttr ( ) ; LLVM,NVPTX,543,"StringRef getPassName() const override { return ""MyPass""; } Explanation:" LLVM,NVPTX,544,"StringRef getPassName () const override { return ""MyPass""; }" LLVM,NVPTX,545,Subtarget = & static_cast < const Subtarget & > ( MF . getSubtarget ( ) ); LLVM,NVPTX,546, LLVM,NVPTX,547,"return TL -> allowFMA( * MF, TL );" LLVM,NVPTX,548,"static bool canLowerToLDG ( MemSDNode * N , const Subtarget & Subtarget , unsigned CodeAddrSpace , MachineFunction * F ) { if ( ! Subtarget . hasLDG ( ) || CodeAddrSpace != :: GLOBAL ) return false ; if ( N -> isInvariant ( ) ) return true ; bool IsKernelFn = isKernelFunction ( F -> getFunction ( ) ) ; SmallVector < const Value * , > Objs ; getUnderlyingObjects ( N ->" LLVM,NVPTX,549,if (auto *A = dyn_cast(V)) { LLVM,NVPTX,550,"return new DAGToDAGISel(TM, OptLevel);" LLVM,NVPTX,551,return :: PARAM; LLVM,NVPTX,552,Here is a possible completion LLVM,NVPTX,553,return Subtarget -> getTargetLowering (); LLVM,NVPTX,554,return Subtarget -> getTargetLowering ( ) -> getDivF32Level ( ); LLVM,NVPTX,555,MVT::i32); } LLVM,NVPTX,556,"const char * getPassName ( ) const override { return ""MyPass""; }" LLVM,NVPTX,557,return CmpMode::EQ; LLVM,NVPTX,558,"DAGToDAGISel :: DAGToDAGISel ( TargetMachine & tm , CodeGenOpt :: Level OptLevel ) : SelectionDAGISel ( tm , OptLevel ) , TM ( tm ) { doMulWide = ( OptLevel > 2 ); }" LLVM,NVPTX,559,Subtarget = &MF.getSubtargetSubtarget>( ); LLVM,NVPTX,560,"Offset , Size , AccessSize , Alignment , Direction , Extension , Reverse , Signed , Action );" LLVM,NVPTX,561,Offset ); LLVM,NVPTX,562,"Offset , Size , AccessSize , Alignment , Direction , Extension , Reverse , Signed , Action );" LLVM,NVPTX,563,"bool DAGToDAGISel :: SelectADDRri64 ( SDNode * OpNode , SDValue Addr , SDValue & Base , SDValue & Offset ) { return SelectADDRri_imp ( OpNode , Addr , Base , Offset , 64 ); }" LLVM,NVPTX,564, LLVM,NVPTX,565,"SDValue & Offset ) { if (Addr.getNode()) { Base = Addr; Offset = DAG.getUNDEFNode(); return true; } SDValue AddrNode = DAG.getNode(ISD::ADDR, Add" LLVM,NVPTX,566,"return SelectADDRsi_imp ( OpNode , Addr , Base ," LLVM,NVPTX,567,"bool DAGToDAGISel :: SelectADDRsi64 ( SDNode * OpNode , SDValue Addr , SDValue & Base , SDValue & Offset ) { return SelectADDRsi_imp ( OpNode , Addr , Base , Offset ); }" LLVM,NVPTX,568,"bool DAGToDAGISel::SelectADDRsi64(SDNode *OpNode, SDValue Addr, SDValue &Base) {" LLVM,NVPTX,569,) ? : ) : ; break ; case ADDRESS_SPACE_CONST : Opc = TM . is64Bit ( ) ? ( useShortPointers ( ) ? : ) : ; break ; case ADDRESS_SPACE_LOCAL : Opc = TM . is64Bit ( ) ? ( useShortPointers ( ) ? : ) : LLVM,NVPTX,570, LLVM,NVPTX,571, LLVM,NVPTX,572,"if (SelectADDRri(Op.getNode(), Op, Op0, Op1)) {" LLVM,NVPTX,573, LLVM,NVPTX,574,Assuming that the `` placeholders represent the name of the LLVM,NVPTX,575,"CurDAG->getMachineNode(, DL, , , N->getOperand(), N->getOperand(), CurDAG->getTargetConstant(PTXCmpMode, DL));" LLVM,NVPTX,576, LLVM,NVPTX,577,"void DAGToDAGISel::SelectTexSurfHandle(SDNode *N) { SDValue Wrapper = N->getOperand(0); SDValue SurfHandle = Wrapper->getOperand(0); SDValue TexHandle = Wrapper->getOperand(1); SDValue SurfIndex = Wrapper->getOperand(2); SDValue TexIndex = Wrapper->getOperand(3); SDValue SurfHandle = DAG->getConstant(SurfIndex, MVT::i3" LLVM,NVPTX,578,if (N->getValueType() != ) return false; LLVM,NVPTX,579, LLVM,NVPTX,580,return true; LLVM,NVPTX,581,return true; LLVM,NVPTX,582,"SDVTList VTs; if (VecSize == ) { VTs = CurDAG -> getVTList (EltVT, ); } else { VTs = CurDAG -> getVTList (EltVT, VecSize); } return true;" LLVM,NVPTX,583, LLVM,NVPTX,584,"ReplaceNode(N, Ret);" LLVM,NVPTX,585,bool useF32FTZ(Subtarget *Subtarget) { LLVM,NVPTX,586,return Subtarget -> getTargetLowering (); LLVM,NVPTX,587,return TM; LLVM,NVPTX,588, LLVM,NVPTX,589,do_DIVF32_PREC = UsePrecDivF32; LLVM,NVPTX,590, LLVM,NVPTX,591,"Base = CurDAG -> getTargetFrameIndex ( FIN -> getIndex ( ) , mvt ) ; Offset = CurDAG -> getTargetConstant ( , mvt ) ; return true ; } if ( Addr . getOpcode ( ) == || Addr . getOpcode ( ) == ) return false ; if ( Addr . getOpcode ( ) == ) { if ( SelectDirectAddr ( Addr . getOperand ( [0] ) ) ) {" LLVM,NVPTX,592,"SDValue base = Addr.getOperand(); if (SelectDirectAddr(base, Base)) { Offset = CurDAG->getTargetConstant(CN->getZExtValue(), ...); }" LLVM,NVPTX,593," , , , , , , ) ; break ; case : Opcode = pickOpcodeForVT ( EltVT . getSimpleVT ( ) . SimpleTy , , , , None , , , ) ; break ; } case : { Opcode = ; SDValue CvtNone = CurDAG -> getTargetConstant ( :: NONE , DL , ) ; SDNode * Cvt = CurDAG -> getMachineNode ( , DL , , Ops [ ] , CvtNone ) ; Ops [ ] = SDValue (" LLVM,NVPTX,595,"Ops [ ] = SDValue ( Cvt , ) ;" LLVM,NVPTX,596, LLVM,NVPTX,597,"return SelectDirectAddr ( Addr , 0 );" LLVM,NVPTX,598,} unsigned int PointerSize = CurDAG->getDataLayout()->getPointerSizeInBits(MemSD->getAddressSpace()); LLVM,NVPTX,599,"* The function appears to take a single argument, `SourceVT`, which is a vector type." LLVM,NVPTX,600, LLVM,NVPTX,601, LLVM,NVPTX,602, LLVM,NVPTX,603,return false; LLVM,NVPTX,604,return false; LLVM,NVPTX,605, LLVM,NVPTX,606,"unsigned IID = cast < ConstantSDNode > ( N -> getOperand ( ) ) -> getZExtValue ( ) ; switch ( IID ) { default : return nullptr ; case : return SelectTexSurfHandle ( N , IID ) ; }" LLVM,NVPTX,607,switch (MemVT.getSimpleVT().SimpleTy) { LLVM,NVPTX,608,default : return nullptr ; LLVM,NVPTX,609, LLVM,NVPTX,610,return UsePrecSqrtF32.getNumOccurrences() > allowFMA(); LLVM,NVPTX,612, LLVM,NVPTX,613, LLVM,NVPTX,614,GLOBAL; LLVM,NVPTX,615, LLVM,NVPTX,616, LLVM,NVPTX,617,"case : Opcode = ; break ; case : Opcode = ; break ; case : Opcode = ; break ; case : Opcode = ; break ; case : Opcode = ; break ; default : return nullptr ; } } SDValue Ops [ ] = { N1 , getI32Imm ( is" LLVM,NVPTX,618, LLVM,NVPTX,619, LLVM,NVPTX,620,return false; LLVM,NVPTX,621,return :: LOCAL; LLVM,NVPTX,622,"virtual const char * getPassName () const override { return ""My Pass Name""; }" LLVM,NVPTX,623,allowFMA = ( FMAContractLevel >= ) || UseFMADInstruction ; LLVM,NVPTX,624, LLVM,NVPTX,625, LLVM,NVPTX,626,return true; } LLVM,NVPTX,627,"getOperand ( 0 ) ) ) { Base = CN . getAPIntVal ( ) ; Offset = APInt ( 32 , 0 ) ; return true ; } } return false ; }" LLVM,NVPTX,628,return true; LLVM,NVPTX,629, LLVM,NVPTX,630,case llvm::ADDRESS_SPACE_LOCAL: return :: LOCAL; break; default: return :: GLOBAL; break; } } LLVM,NVPTX,631,return :: PARAM; LLVM,NVPTX,632,case : switch ( RetVT . getSimpleVT ( ) . SimpleTy ) { default : return NULL ; case : Opcode = ; break ; case : Opcode = ; break ; LLVM,NVPTX,633,"SDValue Ops[2] = { Op1, Chain };" LLVM,NVPTX,634,"DAGToDAGISel :: DAGToDAGISel ( TargetMachine & tm , CodeGenOpt :: Level OptLevel ) : SelectionDAGISel ( tm , OptLevel ) { doMulWide = ( OptLevel > 2 ); }" LLVM,NVPTX,635,"return CurDAG->getMachineNode(Opc, SDLoc(N), N->getValueType(), Src);" LLVM,NVPTX,636, LLVM,NVPTX,637, LLVM,NVPTX,638,"Opc, Ops, Chain, N->getDebugLoc());" LLVM,NVPTX,639,ADDRESS_SPACE_SHARED : Opc = TM . is64Bit ( ) ? : ; break ; case ADDRESS_SPACE_CONST : Opc = TM . is64Bit ( ) ? : ; break ; case ADDRESS_SPACE_LOCAL : Opc = TM . is64Bit ( ) ? : ; break ; } return CurDAG -> getMachineNode ( Op LLVM,NVPTX,640,The LLVM,NVPTX,641, LLVM,NVPTX,642,return Variants[Variant]; LLVM,NVPTX,643, LLVM,NVPTX,644,HAS_CONST_VALUE; LLVM,NVPTX,645, LLVM,NVPTX,646,return true; LLVM,NVPTX,647,"SmallVector> Objs;" LLVM,NVPTX,648,case : switch ( Mem -> getMemoryVT ( ) . getSimpleVT ( ) . SimpleTy ) { default : return false ; case : Opcode = ; break ; case : Opcode = ; break ; case : Opcode = ; break ; case : Opcode = ; break ; case LLVM,NVPTX,649, LLVM,NVPTX,650,return TL -> allowFMA(); LLVM,NVPTX,651,isa < Constant > ( V ) ; } ) ; LLVM,NVPTX,652,"static bool canLowerToLDG ( MemSDNode * N , const Subtarget & Subtarget , unsigned CodeAddrSpace , MachineFunction * F ) { if ( ! Subtarget . hasLDG ( ) || CodeAddrSpace != :: GLOBAL ) return false ; if ( N -> isInvariant ( ) ) return true ; bool IsKernelFn = isKernelFunction ( F -> getFunction ( ) ) ; SmallVector < Value * , > Objs ; GetUnderlyingObjects ( const_cast" LLVM,NVPTX,653,"SDValue getI32Imm(unsigned Imm) { return CurDAG->getTargetConstant(Imm, MVT::i32); }" LLVM,NVPTX,654,"SDLocTy::getI32ImmTy(CurDAG->getContext()), false, false); }" LLVM,NVPTX,655,"SDValue Ops[ ] = {getI32Imm(isVolatile, dl), getI32Imm(CodeAddrSpace, dl), getI32Imm(vecType, dl), getI32Imm(fromType, dl), getI32Imm(fromTypeWidth, dl), Base, Offset, Chain}; LD = CurDAG->getMachineNode(Opcode.getValue(), dl, TargetVT, , Ops); }" LLVM,NVPTX,656,return true; LLVM,NVPTX,657,return false; LLVM,NVPTX,658,for (unsigned j = Idx + ; j < Idx + NumElts; j++) { LLVM,NVPTX,659,EltVT ); LLVM,NVPTX,660, LLVM,NVPTX,661,if (DirectCallee) { LLVM,NVPTX,662, LLVM,NVPTX,663,ExtraSteps = ; LLVM,NVPTX,664,"( ""llvm.x86.f32.recip.a"" );" LLVM,NVPTX,665,"static bool isImageOrSamplerVal(const Value *arg, const Module *context) { static const char *const specialTypes[] = { ""opencl.image2d_t"", ""opencl.image3d_t"", ""opencl.sampler_t"" }; Type *Ty = arg->getType(); auto *PTy = dyn_cast(Ty); if (!PTy) return false; if (!context) return false; auto *STy = dyn_" LLVM,NVPTX,666,"return std::find(std::begin(specialTypes), std::end(specialTypes), STy->getName()) != std::end(specialTypes);" LLVM,NVPTX,667,switch (expression) { LLVM,NVPTX,668,switch (expression) { LLVM,NVPTX,669,if (!(Op->getValueType() == && isa(Op->getOperand()) && isa(Op->getOperand()))) LLVM,NVPTX,670,APInt E1 = cast < ConstantFPSDNode > ( Op -> getOperand ( ) ) -> getValueAPF ( ) . bitcastToAPInt ( ) ; LLVM,NVPTX,671,"return DAG . getBuildVector ( Node -> getValueType ( ), dl, Ops );" LLVM,NVPTX,672, LLVM,NVPTX,673, LLVM,NVPTX,674,"SmallVector < SDValue , > Ops(Opcode, MemSD, Chain, Align, PrefAlign, NeedExt, StoreF16x2);" LLVM,NVPTX,675,"E0, E1 ) ; Ops.push_back(V2); } } return DAG.getNode(Opcode, DL, ValVT, Ops);" LLVM,NVPTX,676,return Result; LLVM,NVPTX,677,"if (SDValue Result = PerformADDCombineWithOperands(N, N0, N1, DCI, Subtarget, OptLevel)) return Result;" LLVM,NVPTX,678,"Val = DCI.DAG.getNode(, SDLoc(N), AExt.getValueType(), Val);" LLVM,NVPTX,679, LLVM,NVPTX,680, LLVM,NVPTX,681,"SDValue B = N -> getOperand ( ) ; if ( CCType != || A . getValueType ( ) != ) return SDValue ( ) ; SDLoc DL ( N ) ; SDValue CCNode = DCI . DAG . getNode ( , DL , DCI . DAG . getVTList ( , ) , { A , B , N ->" LLVM,NVPTX,682, LLVM,NVPTX,683,"OtherOps.push_back(DAG.getIntPtrConstant(LD->getExtensionType(), DL));" LLVM,NVPTX,684,return F->getFnAttribute()->getValueAsString() == ; LLVM,NVPTX,685,delete static_cast < Section * > ( DwarfRangesSection ) ; LLVM,NVPTX,686,if (MF.getTarget().Options.UnsafeFPMath) return true; LLVM,NVPTX,687,ValueVTs.push_back(VT); LLVM,NVPTX,688,"for (unsigned j = 0; j < NumElts; ++j) { ValueVTs.push_back(EVT::getVectorVT(VT.getVectorElementType(), 1)); Offsets->push_back(Off + j * VT.getVectorElementType().getScalarSizeInBits() / 8); } } else { ValueVTs.push_back(VT); Offsets->push_back(Off); } }" LLVM,NVPTX,689,if ( isa < Function > ( CalleeV ) ) { Function * CalleeF = cast < LLVM,NVPTX,690, LLVM,NVPTX,691,switch (AM.getMode()) { LLVM,NVPTX,692,"for (unsigned parti = , parte = VTs.size(); parti != parte; ++parti) {" LLVM,NVPTX,693, LLVM,NVPTX,694,"RoundedA = DAG.getNode(, SL, VT, IsLarge, A, RoundedA);" LLVM,NVPTX,695,"SDValue AdjustedA = DAG . getNode ( ISD::FP_EXTEND, SL, VT, A );" LLVM,NVPTX,696,"RoundedA = DAG.getNode(, SL, VT, IsSmall, DAG.getConstantFP(, SL, VT), RoundedA); RoundedA = DAG.getNode(, SL, VT" LLVM,NVPTX,697,"auto PtrVT = getPointerTy(DAG.getDataLayout(), GAN->getAddressSpace());" LLVM,NVPTX,698, LLVM,NVPTX,699,return SDValue(); LLVM,NVPTX,700, LLVM,NVPTX,701,"Op = DAG.getStore(RetTy, dl, Chain, StoreOperands[0], StoreOperands[1], StoreOperands[2]);" LLVM,NVPTX,702,"StoreOperands.push_back(DAG.getStore(Chain, dl, RetVal, StoreOperands[1], StoreOperands[2], RetVal.getValueSizeInBits()));" LLVM,NVPTX,703,"return LowerSTOREVector(Op, DAG);" LLVM,NVPTX,704,return false; LLVM,NVPTX,705,"bool TargetLowering::allowFMA(MachineFunction &MF, CodeGenOpt::Level OptLevel) const {" LLVM,NVPTX,706,if (FMAContractLevelOpt.getNumOccurrences() > ) { LLVM,NVPTX,707, LLVM,NVPTX,708,Off ) ; } } } LLVM,NVPTX,709,``` LLVM,NVPTX,710, LLVM,NVPTX,711, LLVM,NVPTX,712,return TargetLoweringBase::getPreferredVectorAction(VT); LLVM,NVPTX,713,O << ; LLVM,NVPTX,714,"if (TypeName == ""special_type1"" || TypeName == ""special_type2"") {" LLVM,NVPTX,715,EVT OrigVT = Op . getOperand ( ) . getValueType ( ) ; if ( OrigVT . getSizeInBits ( ) <= OptSize ) { S = Signed ; return true ; } } else if ( Op . getOpcode ( ) == ) { S = Unsigned ; return false ; } } } LLVM,NVPTX,716,static bool IsPTXVectorType ( MVT VT ) { LLVM,NVPTX,717,"if ( Constraint . length ( ) > ) return ; else TargetLowering :: LowerAsmOperandForConstraint ( Op , Constraint . substr ( 0 , ) ) ;" LLVM,NVPTX,718,"i ) ; Ops . push_back ( SubOp ) ; } return DAG . getNode ( ISD::CONCAT_VECTORS , dl , Ops ) ; }" LLVM,NVPTX,719,"const GlobalValue * GV = cast(Op)->getGlobal(); auto PtrVT = getPointerTy(DAG, GV->getType()->getPointerElementType());" LLVM,NVPTX,720,Here is LLVM,NVPTX,721,"return DAG.getLoad(Op.getOperand(0), Op.getOperand(1), Op.getOperand(2), Op.getOperand(3), Op.getOperand(4), Op.getOperand(5), Op.getOperand(6), Op.getOperand(7), Op.getOperand(8), Op.getOperand(9), Op.getOperand(10), Op.getOperand(11), Op.getOperand(12), Op.getOperand(13), Op.getOper" LLVM,NVPTX,722, LLVM,NVPTX,723,"return DAG.getMergeValues(Ops, dl);" LLVM,NVPTX,724,"DAG.getTruncateNode(Select, DL, );" LLVM,NVPTX,725,"DL, Select, Op0.getValueType());" LLVM,NVPTX,726, LLVM,NVPTX,727,"SDValue Ops[2] = {Lo, Hi};" LLVM,NVPTX,728,else return SDValue; LLVM,NVPTX,729,"return LowerSTOREVector ( Op, DAG );" LLVM,NVPTX,730,"SDValue Result = DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2, ST->getPointerInfo());" LLVM,NVPTX,731, LLVM,NVPTX,732,return SDValue ( ) ; } LLVM,NVPTX,733,"static SDValue PerformADDCombine ( SDNode * N , TargetLowering :: DAGCombinerInfo & DCI , const Subtarget & Subtarget , CodeGenOpt :: Level OptLevel ) { SDValue N0 = N -> getOperand ( ) ; SDValue N1 = N -> getOperand ( ) ; SDValue Result = PerformADDCombineWithOperands ( N , N0 , N1 , DCI , Subtarget , OptLevel ) ; if ( Result . getNode ( 0" LLVM,NVPTX,734,"return PerformADDCombineWithOperands(N, N1, N0, DCI, Subtarget, OptLevel);" LLVM,NVPTX,735,return SDValue();` LLVM,NVPTX,736,if (Val->isMachineOpcode() && Val->getMachineOpcode() == ) { LLVM,NVPTX,737,return SDValue(Ret.getNode()); LLVM,NVPTX,738, LLVM,NVPTX,739,"OtherOps . append ( N -> op_begin ( ) + , N -> op_end ( ) ) ;" LLVM,NVPTX,740,SDValue LoadChain = NewLD.getValue(i); LLVM,NVPTX,741,"default : report_fatal_error ( ) ; case : ReplaceLoadVector ( N , DAG , Results ) ; return ; case : report_fatal_error ( ) ; return ;" LLVM,NVPTX,742,"MCSection *TargetObjectFile :: SelectSectionForGlobal ( const GlobalValue * GV, SectionKind Kind, Mangler * Mangler) { if (GV->hasSection()) { return GV->getSection(); } if (GV->hasComdat()) { return getComdatSection(GV->getComdat(), Kind); } if (GV->" LLVM,NVPTX,743,return getDataSection(); LLVM,NVPTX,744,return SDValue ( ) ; LLVM,NVPTX,745,delete static_cast < Section * > ( DwarfRangesSection ) ; LLVM,NVPTX,746,bool isFMAFasterThan LLVM,NVPTX,747,if (VT.isVector()) { LLVM,NVPTX,748,if (VT.isVector()) { LLVM,NVPTX,749,virtual MVT getShiftAmountTy ( EVT LHSTy ) const { return LHSTy.getShiftAmountTy(); } LLVM,NVPTX,750,O << << OIdx << ; if ( first ) { first = false ; } else { O << ; } if ( Ty -> isFloatingPointTy ( ) || ( Ty -> isIntegerTy ( ) && ! Ty -> isIntegerTy ( ) ) ) { unsigned size = ; if ( auto * ITy = dyn_cast < IntegerType > ( Ty ) ) { size = ITy -> getBitWidth ( ) ; } else { assert ( LLVM,NVPTX,751,O << << sz << ; LLVM,NVPTX,752, LLVM,NVPTX,753,"O << << sz << ; O << ; O << << sz << ; SmallVector < EVT , > vtparts ; ComputeValueVTs ( * this , DL , Ty , vtparts ) ; if ( unsigned len = vtparts . size ( ) ) OIdx += len - ; continue ; } assert ( ( get" LLVM,NVPTX,754,"O << ; bool first = true ; unsigned OIdx = ; for ( unsigned i = , e = Args . size ( ) ; i != e ; ++ i , ++ OIdx ) { Type * Ty = Args [ i ] . Ty ; if ( ! first ) { O << ; } first = false ; if ( ! Outs [ OIdx ] . Flags . isByVal ( )" LLVM,NVPTX,755,return MF.getDenormalMode(APFloat::IEEEsingle(x)); LLVM,NVPTX,756,``` LLVM,NVPTX,757, LLVM,NVPTX,758,O << ; LLVM,NVPTX,759,return TargetLowering::getRegForInlineAsmConstraint(Constraint); LLVM,NVPTX,760,"void TargetLowering :: LowerAsmOperandForConstraint ( SDValue Op , std :: string & Constraint , std :: vector < SDValue > & Ops , SelectionDAG & DAG ) const { if ( Constraint . length ( ) > ) return ; else TargetLowering :: LowerAsmOperandForConstraint ( Op , Constraint , Ops , DAG ) ; }" LLVM,NVPTX,761,"LowerOperation ( SDValue Op , SelectionDAG & DAG ) const { switch ( Op . getOpcode ( ) ) { case : return SDValue ( ) ; case : return SDValue ( ) ; case : return LowerGlobalAddress ( Op , DAG ) ; case : return Op ; case : case : return Op ; case : return LowerCONCAT_VECTORS ( Op , DAG ) ;" LLVM,NVPTX,762, LLVM,NVPTX,763, LLVM,NVPTX,764, LLVM,NVPTX,765,if (VT.isVector()) { LLVM,NVPTX,766,return F.getFnAttribute(); LLVM,NVPTX,767,if ( ! VT . isScalableVector ( ) && VT . getVectorNumElements ( ) != && VT . getVectorNumElements ( ) != 0 ) LLVM,NVPTX,768,O << << sz << ; LLVM,NVPTX,769,"O << "" "" << sz << "" "" << align << "" "" << DL.getTypeStoreSize(Ty) << "" "";" LLVM,NVPTX,770,return false; LLVM,NVPTX,771,if ( ! PTy ) LLVM,NVPTX,772, LLVM,NVPTX,773,"case : Op = DAG . getNode ( , dl , , StoreOperands ) ; break ; case : Op = DAG . getNode ( , dl , , StoreOperands ) ; break ; case : Op = DAG . getNode ( , dl , , StoreOperands ) ; break ; default : llvm_unre" LLVM,NVPTX,774,return SDValue(); LLVM,NVPTX,775,if (VT.isVector()) LLVM,NVPTX,776,"SDValue NewLD = DAG . getMemIntrinsicNode ( Opcode , DL , LdResVTs , OtherOps , LD -> getMemoryVT ( ) , LD -> getMemOperand ( ) ) ;" LLVM,NVPTX,777, LLVM,NVPTX,778,if (VT.isVector()) { LLVM,NVPTX,779,"if ( VT . isVector ( ) ) return EVT :: getVectorVT ( Ctx , , VT . getVectorNumElements ( ) ) ; return ;" LLVM,NVPTX,780,"return std::find(specialTypes, specialTypes + 3, STy->getName()) != specialTypes + 3;" LLVM,NVPTX,781,"const std::string TypeName = STy && !STy->isLiteral() ? STy->getName() : """";" LLVM,NVPTX,782,true ; } } return false ; } LLVM,NVPTX,783,"getOperand ( i ) ; Ops . push_back ( SubOp ) ; } return DAG . getNode ( ISA_LIT , dl , Ops ) ; }" LLVM,NVPTX,784, LLVM,NVPTX,785, LLVM,NVPTX,786, LLVM,NVPTX,787,"SDValue Ops[2] = {FalseVal, TrueVal};" LLVM,NVPTX,788,"return DAG.getMergeValues(Ops, dl);" LLVM,NVPTX,789, LLVM,NVPTX,790,"Ops . push_back ( N -> getOperand ( i ) ) ; } SDValue Res = DAG . getNode ( Opcode , DL , ValVT , Ops , NeedExt ) ; return Res ; }" LLVM,NVPTX,791,SDVTList LdResVTs; LLVM,NVPTX,792,delete DwarfStrSection; LLVM,NVPTX,793,delete DwarfRangesSection; LLVM,NVPTX,794,O << << sz << ; LLVM,NVPTX,795,Here are some possible string literal values that could complete the last statement: LLVM,NVPTX,796,"NeedTrunc = true ; } In the default case, the" LLVM,NVPTX,797,} LLVM,NVPTX,798,return AtomicExpansionKind :: AtomicExpansionKind; LLVM,NVPTX,799,Offsets->push_back(Off + j * VT.getVectorElementType().getPrimitiveSizeInBits() / 8); LLVM,NVPTX,800, LLVM,NVPTX,801,O << << PTy -> getAddressSpace ( ) << ; O << ; O << << PTy -> getSizeInBits ( ) << ; O << ; O << << PTy -> getSizeInBits ( ) << ; O << ; O << << PTy -> getSizeInBits ( ) << < LLVM,NVPTX,802,"case 'c' : return std::make_pair(, &);" LLVM,NVPTX,803,return ; LLVM,NVPTX,804,Info . writeMem = true; LLVM,NVPTX,805, LLVM,NVPTX,806, LLVM,NVPTX,807, LLVM,NVPTX,808,"assert ( ResVT . isSimple ( ) && ""Invalid type for load vector"" ) ; switch ( ResVT . getSimpleVT ( ) . SimpleTy ) { default : return ; case MVT :: i8 : case MVT :: i16 : case MVT :: i32 : case MVT :: i64 : case MVT :: i128 : case MVT :: f32 : case MVT :: f64 : case MVT :: f80 : case MVT :: f128 : case MVT" LLVM,NVPTX,809, LLVM,NVPTX,810,if (VT.isVector()) { LLVM,NVPTX,811,"if (VT.isVector()) return ""vector"";" LLVM,NVPTX,812,virtual MVT getScalarShiftAmountTy ( EVT LHSTy ) const { return MVT::getIntegerTypeForBitwidth(LHSTy.getScalarSizeInBits()); } LLVM,NVPTX,813,virtual MVT getScalarShiftAmountTy ( EVT LHSTy ) const { return MVT::getIntegerTypeForBitwidth(LHSTy.getScalarSizeInBits()); } LLVM,NVPTX,814, LLVM,NVPTX,815, LLVM,NVPTX,816, LLVM,NVPTX,817,"return TargetObjectFile::SelectSectionForGlobal(GV, Kind, Mangler);" LLVM,NVPTX,818,"return TargetObjectFile::SelectSectionForGlobal(GV, Kind, Mang, TM);" LLVM,NVPTX,819,O << << sz << ; O << ; LLVM,NVPTX,820,switch (expression) { LLVM,NVPTX,821, LLVM,NVPTX,822,virtual EVT getSetCCResultType ( EVT VT ) const { return VT; } LLVM,NVPTX,823, LLVM,NVPTX,824,"EVT theValType = theVal.getValueType(); unsigned numElems = 1; if (theValType.isVector()) numElems = theValType.getVectorNumElements(); for (unsigned j = 0, je = numElems; j != je; ++j) { SDValue tmpval = theVal; if (theValType.isVector()) tmpval = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, theVal, DAG.getIntPtr" LLVM,NVPTX,825,isIntegerTy ( ) ) { O << << ( argAlignment ? argAlignment -> value ( ) : ) << << DL . getTypeAllocSize ( Ty ) << ; } else { llvm_unreachable ( ) ; } O << ; } else { O << << PtrVT . getSizeInBits ( ) << LLVM,NVPTX,826,else { LLVM,NVPTX,827, LLVM,NVPTX,828, LLVM,NVPTX,829,"&name) { if (name.empty()) { return InlineAsmMemConstraint::NoConstraint; } if (name == ""=m"" || name == ""m"" || name == ""=r"" || name == ""r"") { return InlineAsmMemConstraint::Memory; } if (name == ""=rm" LLVM,NVPTX,830,unsigned getInlineAsmMemConstraint ( const std :: string & ConstraintCode ) const override { return InlineAsm [ConstraintCode]; } LLVM,NVPTX,831,opIsLive = true; LLVM,NVPTX,832,"return PerformMULCombine(N, DCI, nvptxSubtarget, OptLevel);" LLVM,NVPTX,833,return false; LLVM,NVPTX,834,return false; LLVM,NVPTX,835, LLVM,NVPTX,836,"assert (Node->getValueType() == && ); SDValue newLD = DAG.getLoad(, dl, LD->getChain(), LD->getBasePtr(), LD->getPointerInfo" LLVM,NVPTX,837, LLVM,NVPTX,838,bool isNonTemporal = ST->isNonTemporal(); LLVM,NVPTX,839, LLVM,NVPTX,840, LLVM,NVPTX,841,"for (std::size_t I = NUM_LIT, OpsCount = N->ops().size(); I != O" LLVM,NVPTX,842, LLVM,NVPTX,843,O << << DL . getPointerSizeInBits ( ) << ; O << ; continue ; } const VectorType * VTy = dyn_cast < VectorType > ( Ty ) ; assert ( VTy && ) ; O << << VTy -> getNumElements ( ) << ; O << ; continue ; } const DataLayout * DL = & CS -> getModule ( ) -> getDataLayout LLVM,NVPTX,844,delete DwarfRangesSection; LLVM,NVPTX,845,default : return AtomicExpansionKind :: CmpXChg ; LLVM,NVPTX,846,O << << sz << ; LLVM,NVPTX,847, LLVM,NVPTX,848,if ( ! STy || STy -> isLiteral ( ) ) LLVM,NVPTX,849,"j * Offsets [ VecIdx ] , dl , PtrVT ) ) ; InVals . push_back ( Elt ) ; } } } }" LLVM,NVPTX,850, LLVM,NVPTX,851, LLVM,NVPTX,852,return VT.getScalarType() LLVM,NVPTX,853,switch (expression) { LLVM,NVPTX,854, LLVM,NVPTX,855, LLVM,NVPTX,856,"SDValue newLD = DAG.getLoad(, dl, LD.getChain(), LD.getBasePtr(), LD.getPointerInfo(), LD.isVolatile(), LD.isNonTemporal(), LD.isInvariant());" LLVM,NVPTX,857,return NewSt; LLVM,NVPTX,858,return; LLVM,NVPTX,859,Res ); LLVM,NVPTX,860, LLVM,NVPTX,861,return ; LLVM,NVPTX,862,const char *TargetLowering::getTargetNodeName(unsigned Opcode) const { LLVM,NVPTX,863,Info . opc = ; Info . memVT = ; Info . ptrVal = I . getArgOperand ( ) ; Info . offset = ; Info . vol = ; Info . readMem = LLVM,NVPTX,864,case : LLVM,NVPTX,865, LLVM,NVPTX,866,"( ) ) ; Value * srcValue = Constant :: getNullValue ( PointerType :: get ( ObjectVT . getTypeForEVT ( F -> getContext ( ) ) , llvm :: ADDRESS_SPACE_PARAM ) ) ; SDValue p = DAG . getLoad ( ObjectVT , dl , Root , Arg , MachinePointerInfo ( srcValue ) , false , false , false , TD -> getABITypeAlignment ( ObjectVT . getTypeForEVT ( F -> getContext ( ) ) ) ) ; if ( p . getNode ( ) ) p" LLVM,NVPTX,867,SDNode *Node = Op.getNode(); LLVM,NVPTX,868,return Result; LLVM,NVPTX,869,"setOperationAction(, , Legal);" LLVM,NVPTX,870,"Inside the loop, it checks if `first` is `true`, and if so" LLVM,NVPTX,871,return MF.getDenormalMode(APFloat::IEEEsingle()); LLVM,NVPTX,872,O << << getDataLayout ( ) -> getPointerSizeInBits ( ) << ; LLVM,NVPTX,873, LLVM,NVPTX,874,return SDValue ( ); LLVM,NVPTX,875,unsigned PrefAlign = TD -> getPrefTypeAlignment ( ResVT . getTypeForEVT ( * DAG . getContext ( ) ) ) ; if ( Align < PrefAlign ) { return ; } EVT EltVT = ResVT . getVectorElementType ( ) ; unsigned NumElts = ResVT . getVectorNumElements ( ) ; bool NeedTrunc = false ; if LLVM,NVPTX,876, LLVM,NVPTX,877,else { LLVM,NVPTX,878,"return TLI -> getOperationAction(Opcode, ValVT);" LLVM,NVPTX,879,"OtherOps.push_back(DAG.getIntPtrConstant(LD->getExtensionType(), DL));" LLVM,NVPTX,880,"return std::make_pair(, &);" LLVM,NVPTX,881,unsigned NumSubElem = VVT.getVectorNumElements(); LLVM,NVPTX,882,return Chain; LLVM,NVPTX,883,assert ( LD -> getExtensionType ( ) == ) ; assert ( Node -> getValueType ( ) == && ) ; SDValue newLD = DAG . getLoad ( , Chain, DAG.getConstant(isABI ? sizesofar : idx, ), tmpval);" LLVM,NVPTX,886, LLVM,NVPTX,887,Results.push_back(BuildVec); LLVM,NVPTX,888,ScalarRes.push_back(Res); LLVM,NVPTX,889,O << << sz << ; LLVM,NVPTX,890,DL . getPointerSize ( ) ; } else if ( isa < VectorType > ( Ty ) ) { sz = cast < VectorType > ( Ty ) -> getBitWidth ( ) ; } else if ( isa < ArrayType > ( Ty ) ) { sz = cast < ArrayType > ( Ty ) -> getBitWidth ( ) ; } else if ( isa < StructType > ( Ty ) ) { sz = cast < StructType > ( Ty ) -> getBitWidth ( ) ; } else { assert ( 0 && ) ; } O << , , Legal ) ;" LLVM,NVPTX,892,"for (unsigned j = 0, je = vtparts.size(); j != je; ++j) {" LLVM,NVPTX,893,bool enableAggressiveFMAFusion ( EVT VT ) { LLVM,NVPTX,894,bool enableAggressiveFMAFusion ( EVT VT ) { LLVM,NVPTX,895,return LLVM,NVPTX,896,"return getExtSymb(DAG, , );" LLVM,NVPTX,897, LLVM,NVPTX,898,"MVT getScalarShiftAmountTy ( const DataLayout & , EVT ) const override { return MVT::i32; }" LLVM,NVPTX,899,"DL, const Value *V) { Type *Ty = V->getType(); if (Ty->isVectorTy()) { Ty = Ty->getVectorElementType(); } if (Ty->isIntegerTy()) { return DL.getTypeSizeInBits(Ty); }" LLVM,NVPTX,900,"return EVT::getVectorVT(Ctx, VT);" LLVM,NVPTX,901,"return getSetCCResultType(DL, Ctx, VT);" LLVM,NVPTX,902,{ if (!target.hasFMA()) { return false; } if (target.getFMALatency() < target.getFMulLatency() + target.getFAddLatency()) { return true; } else { return false; } } LLVM,NVPTX,903,"if ( ! context ) return false ; auto * STy = dyn_cast < StructType > ( PTy -> getElementType ( ) ) ; const std :: string TypeName = STy && ! STy -> isLiteral ( ) ? STy -> getName ( ) : ; for ( int i = , e = array_lengthof ( specialTypes ) ; i != e ; ++ i ) if ( TypeName == specialTypes [i] ) return true ; return false ;" LLVM,NVPTX,904,return SrcTy -> getPrimitiveSizeInBits ( ) == NUM_LIT && DstTy -> getPrimitiveSizeInBits ( ) == NUM_LIT; LLVM,NVPTX,905, LLVM,NVPTX,906,"LoopBuilder.CreateCondBr(LoopBuilder.CreateICmpULT(NewIndex, ConstantInt::get(TypeOfCopyLen, )));" LLVM,NVPTX,907,return true; LLVM,NVPTX,908,( IntrCall ) ; } } } } } } LLVM,NVPTX,909,Memset ) ; } } return true ; } LLVM,NVPTX,910,"newind, loopBB ); Here is a breakdown of the code:" LLVM,NVPTX,911,"virtual const char * getPassName () const override { return ""My Pass Name""; }" LLVM,NVPTX,912,"i ] ; Value * srcAddr = cpy -> getSource ( ) ; Value * dstAddr = cpy -> getDest ( ) ; Value * len = cpy -> getLength ( ) ; convertTransferToLoop ( cpy , srcAddr , dstAddr , len , cpy -> isVolatile ( ) , cpy -> isVolatile ( ) , Context , F ) ; cpy -> eraseFromParent ( ) ; } for ( unsigned i = , e = aggrMemsets . size ( ) ; i != e ; ++ i ) {" LLVM,NVPTX,913, LLVM,NVPTX,914,getZExtValue ( ) >= MaxAggrCopySize ) { aggrMemsets . push_back ( memsetintr ) ; } } else { aggrMemsets . push_back ( memsetintr ) ; } } } } } LLVM,NVPTX,915, LLVM,NVPTX,916,"ind -> addIncoming ( ConstantInt :: get ( len -> getType ( ) , 1 ) , origBB ) ; loop . CreateStore ( val , loop . CreateGEP ( val -> getType ( ) , dstAddr , ind ) , false ) ; Value * newind = loop . CreateAdd ( ind , ConstantInt :: get ( ind -> getType ( ) , 1 ) ) ; ind -> addIncoming ( newind , loopBB ) ; loop . CreateCondBr ( loop . CreateICmp ( ICmpInst :: ICMP_NE , ind , len ) , loopBB ," LLVM,NVPTX,917,"Value * newind = loop.CreateAdd(ind, ConstantInt::get(indType, 1));" LLVM,NVPTX,918,if (LoadInst *load = dyn_cast(II)) { LLVM,NVPTX,919,"for (unsigned i = 0, e = aggrLoads.size(); i != e; ++i) {" LLVM,NVPTX,920,return false; LLVM,NVPTX,921,"Memmove , TTI ) ; } MemCall -> eraseFromParent ( ) ; } return true ; }" LLVM,NVPTX,922,return true; LLVM,NVPTX,923,"ind -> addIncoming ( newind , loopBB ) ;" LLVM,NVPTX,924,"ind->addIncoming(newind, loopBB);" LLVM,NVPTX,925, LLVM,NVPTX,926,"DstAddr = Builder.CreateBitCast(DstAddr, PointerType::get(SetValue->getType(), dstAS));" LLVM,NVPTX,927, LLVM,NVPTX,928,"const char * getPassName ( ) const override { return ""MyPass""; }" LLVM,NVPTX,929,"( MemCall ) ) { convertMemMoveToLoop ( Memmove , Memmove -> getRawSource ( ) , Memmove -> getRawDest ( ) , Memmove -> getLength ( ) , Memmove -> isVolatile ( ) , Memmove -> isVolatile ( ) , Context , F ) ; } MemCall -> eraseFromParent ( ) ; } return true ; }" LLVM,NVPTX,930,"MemCall ) ) { Value * SrcAddr = Memcpy -> getOperand ( ) ; Value * DstAddr = Memcpy -> getOperand ( ) ; unsigned NumLoads = DL . getTypeStoreSize ( Memcpy -> getType ( ) ) ; Value * CopyLen = ConstantInt :: get ( Type :: getInt32Ty ( Context ) , NumLoads ) ; convertMemCpyToLoop ( Memcpy , SrcAddr , DstAddr , CopyLen , Memcpy -> isVolatile (" LLVM,NVPTX,931,BasicBlockPass * llvm :: createLowerAllocaPass ( ) { return new LowerAlloca ( ) ; } LLVM,NVPTX,932,Here is LLVM,NVPTX,933,"{ return ""MyPassword""; }" LLVM,NVPTX,934,createFunctionPassManager() { return new FunctionPassManager(); } LLVM,NVPTX,935,NewASCToGeneric ) ; continue ; } } } } } } To LLVM,NVPTX,936,".getUser()) ; if (GI && GI->getPointerOperand() == allocaInst && !GI->isVolatile()) { GI->setOperand(GI->getPointerOperandIndex(), NewASCToGeneric); continue; } } } } return Changed; }" LLVM,NVPTX,937,} } } } } LLVM,NVPTX,938, LLVM,NVPTX,939,return true; LLVM,NVPTX,940,"Value * PtrInGeneric = new AddrSpaceCastInst ( PtrInGlobal , Ptr -> getType ( ) , ) ;" LLVM,NVPTX,941,for (Argument& Arg : F.args()) { LLVM,NVPTX,942,"AllocaInst * AllocA = new AllocaInst(StructType, AS, Arg->getName(), FirstInst);" LLVM,NVPTX,943,"""PType->getElementType()->isIntegerTy() && PType->getElementType()->getIntegerBitWidth() == 32"" );" LLVM,NVPTX,944,"LoadInst * LI = new LoadInst ( ArgInParam , Arg , FirstInst ) ;" LLVM,NVPTX,945,"void LowerArgs::handleByValParam(Argument *Arg) { Function *Func = Arg->getParent(); Instruction *FirstInst = &(Func->getEntryBlock().front()); PointerType *PType = dyn_cast(Arg->getType()); assert(PType && ""Argument is not a pointer type""); Type *StructType = PType->getElementType(); unsigned AS = Func->getParent()->getDataLayout()->getAllocaAddrSpace(); AllocaInst *AllocA = new" LLVM,NVPTX,946,return true; LLVM,NVPTX,947,return; LLVM,NVPTX,948,AllocA -> setAlignment ( Func -> getParamAlign ( Arg -> getArgNo ( ) ) . getValueOr ( DL . getAllocaAlign ( ) ) ) ; LLVM,NVPTX,949, LLVM,NVPTX,950,return true; LLVM,NVPTX,951,"ArgInParam = new AddrSpaceCastInst(Arg, PointerType::get(StructType, ADDRESS_SPACE_PARAM), FirstInst);" LLVM,NVPTX,952,"assert(PType && ""Parameter is not a pointer type"");" LLVM,NVPTX,953,unsigned AS = DL . getPointerSize ( ) ; LLVM,NVPTX,954,Instruction *I) { I->eraseFromParent(); }); LLVM,NVPTX,955,AllocA ) ; LLVM,NVPTX,956,Ptr -> replaceAllUsesWith ( PtrInGeneric ) ; LLVM,NVPTX,957,for (Argument & Arg : F.args()) { LLVM,NVPTX,958, LLVM,NVPTX,959,Arg -> replaceAllUsesWith ( ArgInGeneric ) ; LLVM,NVPTX,960, LLVM,NVPTX,961,InsertPt = Arg->getParent()->getEntryBlock().begin(); LLVM,NVPTX,962,return new LowerKernelArgs ( LLVM,NVPTX,963,Value * ArgInParam = new AddrSpaceCastInst LLVM,NVPTX,964, LLVM,NVPTX,965,const char * getPassName (Pass * pass) { return pass->getName(); } LLVM,NVPTX,966,FirstInst ); LLVM,NVPTX,967,"CallInst * CallCVT = CallInst :: Create ( CvtFunc , BitcastArgs , Arg -> getName ( ) , FirstInst ) ;" LLVM,NVPTX,968,return true; LLVM,NVPTX,969,if ( ! isKernelFunction ( F ) ) LLVM,NVPTX,970,return ImageHandleList.size() - 1; LLVM,NVPTX,971,Data8bitsDirective = ; Data16bitsDirective = nullptr ; Data32bitsDirective = ; Data64bitsDirective = ; ZeroDirective = ; AsciiDirective = nullptr ; AscizDirective = nullptr ; Supports LLVM,NVPTX,972,"return SectionName.startsWith("".note.""); }" LLVM,NVPTX,973,"return SectionName.startsWith("".debug_"");" LLVM,NVPTX,974,HasFunctionAlignment = false ; HasDotTypeDotSizeDirective = false ; HiddenDeclarationVisibilityAttr = HiddenVisibilityAttr = MCSA_Invalid ; ProtectedVisibilityAttr = MCSA_Invalid ; Data8bitsDirective = ; Data16bitsDirective = nullptr ; Data32bitsDirective = ; Data64bitsDirective = ; ZeroDirective = ; AsciiDirective = null LLVM,NVPTX,975,SupportsDebugInformation = true ; HasFunctionAlignment = false ; HasDotTypeDotSizeDirective = false ; HiddenDeclarationVisibilityAttr = HiddenVisibilityAttr = MCSA_Invalid ; ProtectedVisibilityAttr = MCSA_Invalid ; Data8bitsDirective = ; Data16bitsDirective = nullptr ; Data32bitsDirective = ; LLVM,NVPTX,976,PointerSize = CalleeSaveStackSlotSize = 8; LLVM,NVPTX,977, LLVM,NVPTX,978, LLVM,NVPTX,979,SupportsDebugInformation = CompileForDebugging ; LLVM,NVPTX,980,InlineAsmEnd = ; SupportsDebugInformation = CompileForDebugging ; HasFunctionAlignment = false ; HasDotTypeDotSizeDirective = false ; Data8bitsDirective = ; Data16bitsDirective = ; Data32bitsDirective = ; Data64bitsDirective = ; ZeroDirective = ; AsciiDirective LLVM,NVPTX,981,HasDotTypeDotSizeDirective = false; LLVM,NVPTX,982,InlineAsmStart = ; InlineAsmEnd = ; SupportsDebugInformation = CompileForDebugging ; HasDotTypeDotSizeDirective = false ; Data8bitsDirective = ; Data16bitsDirective = ; Data32bitsDirective = ; Data64bitsDirective = ; LLVM,NVPTX,983,PointerSize = CalleeSaveStackSlotSize = 8; LLVM,NVPTX,984,InlineAsmStart = ; InlineAsmEnd = ; SupportsDebugInformation = CompileForDebugging ; HasFunctionAlignment = false ; HasDotTypeDotSizeDirective = false ; HiddenDeclarationVisibilityAttr = HiddenVisibilityAttr = MCSA_Invalid ; ProtectedVisibilityAttr = MCSA_Invalid ; Data8bitsDirective = ; Data16bitsDirective = LLVM,NVPTX,985,if (TheTriple.getArch() == Triple::nvptx64) { LLVM,NVPTX,986,Triple TheTriple(TT); LLVM,NVPTX,987,"CommentString = ""//"" ; PrivateGlobalPrefix = ""_"" ; AllowPeriodsInName = false ; HasSetDirective = false ; HasSingleParameterDotFile = false ; InlineAsmStart = ""asm"" ; InlineAsmEnd = ""end"" ; SupportsDebugInformation = CompileForDebugging ; HasDotTypeDotSizeDirective = false ; Data8bitsDirective = ""db"" ; Data16bitsDirective = ""dw"" ;" LLVM,NVPTX,988, LLVM,NVPTX,989,ProtectedVisibilityAttr = MCSA_Invalid ; Data8bitsDirective = ; Data16bitsDirective = nullptr ; Data32bitsDirective = LLVM,NVPTX,990,"HasDotTypeDotSizeDirective = false ; Data8bitsDirective = ""db"" ; Data16bitsDirective = ""dw"" ; Data32bitsDirective = ""dd"" ; Data64bitsDirective = ""dq"" ; ZeroDirective = ""dz"" ; AsciiDirective = ""ascii"" ; AscizDirective = ""asciz""" LLVM,NVPTX,991,static bool classof ( const MCExpr *E ) { return E->getKind() == MCExpr::SymbolRef; } LLVM,NVPTX,992,"return create ( VK__SINGLE_PREC_FLOAT , Flt , VK__SINGLE_PREC_FLOAT , Flt );" LLVM,NVPTX,993, LLVM,NVPTX,994,Res = MCValue(); return true; } LLVM,NVPTX,995,return m_kind; LLVM,NVPTX,996,"const GenericMCSymbolRefExpr * GenericMCSymbolRefExpr :: create ( const MCSymbolRefExpr * SymExpr , MCContext & Ctx ) { return new ( Ctx ) GenericMCSymbolRefExpr ( SymExpr , Ctx ); }" LLVM,NVPTX,997,"return new ( Ctx ) GenericMCSymbolRefExpr ( Symbol, Ctx );" LLVM,NVPTX,998,"return create ( VK__DOUBLE_PREC_FLOAT , Flt , Flt , Flt , Flt , Flt , Flt , Flt , Flt , Flt , Flt , Flt , Flt , Flt , Flt , Flt , Flt , Flt , Flt , Flt , Flt , Flt , Flt , Flt , Flt , Flt , Flt , Flt , Flt , Flt , Flt , Flt , Flt , Flt , Flt ," LLVM,NVPTX,999,static const FloatMCExpr * createConstantFPHalf ( const APFloat &value ) { return new FloatMCExpr ( value ); } LLVM,NVPTX,1000,"void GenericMCSymbolRefExpr::printImpl(raw_ostream &OS, const MCAsmInfo *MAI) { OS << getSymbol().getName(); if (getKind() == MCSymbolRefExpr::Kind::PCRel) { OS << ""@PCREL""; } }" LLVM,NVPTX,1001,MCSection * findAssociatedSection ( ) const override { return m_associatedSection; } LLVM,NVPTX,1002,"const ISA_LITFloatMCExpr * ISA_LITFloatMCExpr :: create ( VariantKind Kind , APFloat Flt , MCContext & Ctx )" LLVM,NVPTX,1003,OS << HexStr; LLVM,NVPTX,1004,"return Create ( VK__DOUBLE_PREC_FLOAT , Flt , VK__DOUBLE_PREC_FLOAT ); return Create ( VK__DOUBLE_PREC_FLOAT , Flt , VK__DOUBLE_PREC" LLVM,NVPTX,1005,"return Create ( VK__SINGLE_PREC_FLOAT , Flt , Ctx );" LLVM,NVPTX,1006,const MCSection * FindAssociatedSection(const MCObject *Object) const override { LLVM,NVPTX,1007,OS << utohexstr(API.getZExtValue()) << '0'; LLVM,NVPTX,1008, LLVM,NVPTX,1009,MRI ) ; else return nullptr ; } LLVM,NVPTX,1010,"return new InstPrinter ( MAI , MII , MRI ) ;" LLVM,NVPTX,1011,"InitMCRegisterInfo(X, );" LLVM,NVPTX,1012,"static MCSubtargetInfo * createMCSubtargetInfo ( const Triple & TT , StringRef CPU , StringRef FS ) { return createMCSubtargetInfoImpl ( TT , CPU , FS ); }" LLVM,NVPTX,1013,"static MCSubtargetInfo * createMCSubtargetInfo ( const Triple & TT , StringRef CPU , StringRef FS ) { return createMCSubtargetInfoImpl ( TT , CPU , FS ); }" LLVM,NVPTX,1014,"static MCTargetStreamer * createTargetAsmStreamer ( MCStreamer & S ," LLVM,NVPTX,1015,"static MCTargetStreamer * createTargetAsmStreamer ( MCStreamer & S ," LLVM,NVPTX,1016, LLVM,NVPTX,1017,"return createMCSubtargetInfoImpl(TT, CPU);" LLVM,NVPTX,1018,MCRegisterInfo *X = new MCRegisterInfo(); LLVM,NVPTX,1019,"InitMCRegisterInfo ( X , ... );" LLVM,NVPTX,1020,"static MCCodeGenInfo * createMCCodeGenInfo ( const Triple & TT , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt ) {" LLVM,NVPTX,1021,createMCSubtargetInfo ) ; LLVM,NVPTX,1022, LLVM,NVPTX,1023,"CM , OL ) ; return X ; }" LLVM,NVPTX,1024,"static MCInstPrinter * createMCInstPrinter ( const Target & T , unsigned SyntaxVariant , const MCAsmInfo & MAI , const MCInstrInfo & MII , const MCRegisterInfo & MRI , const MCSubtargetInfo & STI ) { if ( SyntaxVariant == ) return new InstPrinter ( MAI , MII , MRI , STI ); }" LLVM,NVPTX,1025,"static MCCodeGenInfo * createMCCodeGenInfo ( StringRef TT , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level ) {" LLVM,NVPTX,1026,"TargetRegistry :: RegisterMCRegInfo ( TheTarget64 , createMCRegisterInfo ) ;" LLVM,NVPTX,1027,MCInstrInfo(); LLVM,NVPTX,1028, LLVM,NVPTX,1029,"static MCSubtargetInfo * createMCSubtargetInfo ( StringRef TT, StringRef CPU)" LLVM,NVPTX,1030,"MCSubtargetInfo * X = new MCSubtargetInfo ( TT , CPU , FS );" LLVM,NVPTX,1031,"TargetRegistry::RegisterMCSubtargetInfo(TheTarget64, createMCSubtargetInfo);" LLVM,NVPTX,1032,"auto & MIB = BuildMI(MF, Root.getDebugLoc(), TII->get(Prev.getOpcode()), Root.getOperand().getReg());" LLVM,NVPTX,1033,if (MRI.hasOneNonDBGUse(Prev.getOperand().getReg()) && ) { LLVM,NVPTX,1034, LLVM,NVPTX,1035,Here is LLVM,NVPTX,1036,return BaseAddrOp.isReg() && BaseAddrOp.getReg() == ; LLVM,NVPTX,1037, LLVM,NVPTX,1038,auto BlockIter = MBB.begin(); LLVM,NVPTX,1039,return Op.getRegInfo(); LLVM,NVPTX,1040,auto &MBB = *Root.getParent(); LLVM,NVPTX,1041,Changed = true ; } } } const RegisterInfo * NRI = MF . getSubtarget < Subtarget > LLVM,NVPTX,1042,Root.eraseFromParentAndMarkDBGValuesForRemoval(); LLVM,NVPTX,1043,"MachineInstrBuilder MIB = BuildMI ( MF , Root . getDebugLoc ( ) , TII -> get ( Prev . getOpcode ( ) ) , Root . getOperand ( ) . getReg ( ) ) . addReg ( NRI -> getFrameLocalRegister ( MF ) ) . add ( Prev . getOperand ( ) ) ; MBB . insert ( ( MachineBasicBlock :: iterator ( MIB ) ) ) ;" LLVM,NVPTX,1044,AU.setPreservesAll(); LLVM,NVPTX,1045,void getAnalysisUsage ( AnalysisUsage & AU ) const override { LLVM,NVPTX,1046,MachineInstr *GenericAddrDef = nullptr; LLVM,NVPTX,1047,initializePeepholePass ( * PassRegistry :: getPassRegistry () ); LLVM,NVPTX,1048,initializePeepholePass ( * PassRegistry :: getPassRegistry () ); LLVM,NVPTX,1049, LLVM,NVPTX,1050,"MaxAlign = std::max(MaxAlign, Align); Offset = (Offset + Align - ) / Align * Align; if (StackGrowsDown) { DEBUG(dbgs() << << FrameIdx" LLVM,NVPTX,1051,StackAlign = TFI . getStackAlignment ( ) ; LLVM,NVPTX,1052,return new MachineFunctionPass(new PrologEpilogPass()); LLVM,NVPTX,1053, LLVM,NVPTX,1054,Offset = (Offset + Align - 1) / Align * Align; LLVM,NVPTX,1055,"MFI.setObjectOffset(FrameIdx, Offset);" LLVM,NVPTX,1056,"for (unsigned i = 0, e = MFI.getObjectIndexEnd(); i != e; ++i) {" LLVM,NVPTX,1057, LLVM,NVPTX,1058, LLVM,NVPTX,1059,Offset = (Offset + Align - 1) / Align * Align; LLVM,NVPTX,1060,Offset += MFI . getMaxCallFrameSize ( ) ; LLVM,NVPTX,1061,return Modified; LLVM,NVPTX,1062,"MaxAlign = std::max(MaxAlign, Alignment);" LLVM,NVPTX,1063,"MI.getDebugExpressionOp().setMetadata(""dbg"", DIExpr);" LLVM,NVPTX,1064,TargetFrameLowering::FrameIndex FI = TFI.getFrameIndexReference(*MI->getOperand(i).getFI()); LLVM,NVPTX,1065,return Modified; LLVM,NVPTX,1066,TFI.emitPrologue(MF); LLVM,NVPTX,1067,.isReg ( ) ) continue; unsigned Reg = MI -> getOperand ( i ) . getReg ( ) ; if ( TRI . isFramePointerReg ( Reg ) ) continue; if ( TRI . isStackPointerReg ( Reg ) ) continue; if ( TRI . isLinkRegister ( Reg ) ) continue; if ( TRI . isArgumentRegister ( Reg ) ) continue; if ( TRI . isReturnValueRegister ( Reg ) ) continue; if ( LLVM,NVPTX,1068, LLVM,NVPTX,1069,MI.getOperand(i).setIsDebug(true); LLVM,NVPTX,1070, LLVM,NVPTX,1071, LLVM,NVPTX,1072,initializeProxyRegErasurePass ( * PassRegistry :: getPassRegistry ( ) ); LLVM,NVPTX,1073,"void ISA_LITProxyRegErasure :: replaceRegisterUsage ( MachineInstr & Instr , MachineOperand & From , MachineOperand & To ) { for ( auto & Op : Instr . uses ( ) ) { if ( Op . isReg ( ) && Op . getReg ( ) == From . getReg ( ) ) { Op . setReg ( To . getReg ( ) ) ; } } }" LLVM,NVPTX,1074,"void ISA_LITProxyRegErasure::replaceRegisterUsage(MachineInstr &Instr, MachineOperand &From, MachineOperand &To) { for (auto &Op : Instr.uses()) { if (Op.isReg() && Op.getReg() == From.getReg()) { Op.setReg(To.getReg()); } } }" LLVM,NVPTX,1075, LLVM,NVPTX,1076,for (auto* MI : RemoveList) { MI->eraseFromParent(); } LLVM,NVPTX,1077,return getStrPool()->getManagedString(O.str().c_str()); LLVM,NVPTX,1078,return const_cast(&ManagedStrPool[0]); LLVM,NVPTX,1079, LLVM,NVPTX,1080,return ; } else if ( RC == & ) { return ; } else if ( RC == & ) { return ; } else if ( RC == & ) { return ; } else if ( LLVM,NVPTX,1081,"} else if (RC == &"""") {" LLVM,NVPTX,1082,if ( RC == & RegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { return ""rsp""; }" LLVM,NVPTX,1085,"For example, on x86-64, the callee-saved registers are typically `rbx`, `r12`, `r13`, `r14`, and `r15" LLVM,NVPTX,1086,std::string get LLVM,NVPTX,1087, LLVM,NVPTX,1088,return rA; LLVM,NVPTX,1089, LLVM,NVPTX,1090,{ return CalleeSavedRegClasses; } LLVM,NVPTX,1091,"getDwarfRegNum ( unsigned RegNum , bool isEH ) const { return isEH ? RegNum : RegNum + 1; }" LLVM,NVPTX,1092,return ; } } else if ( RC == & ) { return ; } else if ( RC == & ) { return ; } else if ( RC == & ) { return ; } else if ( RC == & ) { return ; } else { return ; } } LLVM,NVPTX,1093, LLVM,NVPTX,1094, LLVM,NVPTX,1095,"static const MCPhysReg CalleeSavedRegs[] = { MCPhysReg::RAX, MCPhysReg::RCX, MCPhysReg::RDX, MCPhysReg::RSI, MCPhysReg::RDI, MCPhysReg::R8, MCPhysReg::R9, MCPhysReg::R10, MCPhysReg::R11, MCPhysReg::RBX," LLVM,NVPTX,1096,unsigned RegisterInfo::getFrameRegister(const MachineFunction &MF) const { return MF.getFrameRegister(); } LLVM,NVPTX,1097,"if (RC == &""Hello"") {" LLVM,NVPTX,1098,return ; LLVM,NVPTX,1099,return CalleeSavedRegClasses; LLVM,NVPTX,1100,"eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj, RegScavenger *RS) const {" LLVM,NVPTX,1101, LLVM,NVPTX,1102, LLVM,NVPTX,1103,return getRegClassName(RC->getID()); LLVM,NVPTX,1104,return ; } } else if ( RC == & ) { return ; } else if ( RC == & ) { return ; } else if ( RC == & ) { return ; } else if ( RC == & ) { return ; } else if ( RC == & ) { return ; } else if LLVM,NVPTX,1105,"if (RC->getID() == ""string_literal_6"") return true;" LLVM,NVPTX,1106,"return RC == &""OK"" ? ""OK"" : RC == &""ERROR"" ? ""ERROR"" : ""UNKNOWN"";" LLVM,NVPTX,1107,const MCPhysReg * RegisterInfo :: getCalleeSavedRegs ( const MachineFunction * ) const { LLVM,NVPTX,1108,const TargetMachine & TM = static_cast < const TargetMachine & > ( MF . getTarget ( ) ) ; LLVM,NVPTX,1109,return TM.is64Bit(); LLVM,NVPTX,1110, LLVM,NVPTX,1111,"if (RC == &""Hello"") return ""Hello"";" LLVM,NVPTX,1112,"if ( RC == &""A"" ) return ""Apple"" ;" LLVM,NVPTX,1113,return ReservedRegs; LLVM,NVPTX,1114,"StringRef getPassName() const override { return ""MyPass""; } Explanation:" LLVM,NVPTX,1115,return true; LLVM,NVPTX,1116,default: llvm_unreachable() LLVM,NVPTX,1117,return true; LLVM,NVPTX,1118, LLVM,NVPTX,1119,return Changed; LLVM,NVPTX,1120, LLVM,NVPTX,1121,"This code snippet is defining a class that inherits from a base class that has a pure virtual function called `getPassName()`. The class is overriding this function and returning a string literal ""MyPass""." LLVM,NVPTX,1122,InstrsToRemove.clear(); LLVM,NVPTX,1123,"""MyPass"";" LLVM,NVPTX,1124, LLVM,NVPTX,1125,"void ReplaceImageHandles::replaceImageHandle(MachineOperand &Op," LLVM,NVPTX,1126,if ( findIndexForHandle LLVM,NVPTX,1127,MachineInstr & MI = *I; LLVM,NVPTX,1128,virtual bool isBaseAddressKnownZero ( ) const { return true; } LLVM,NVPTX,1129,virtual bool isVirtualSection ( ) const { return false; } LLVM,NVPTX,1130,virtual bool UseCodeAlign (const COR_ILMETHOD_SECT_SMALL& header) { return (header.Kind == CorILMethod_Sect_EHTable || header.Kind == CorILMethod_Sect_FatFormat || header.Kind == CorILMethod_Sect_MoreSects); } LLVM,NVPTX,1131,"""begin"";" LLVM,NVPTX,1132,virtual std::string getLabelBeginName() { LLVM,NVPTX,1133,"virtual std::string getLabelEndName() const override { return ""End""; }" LLVM,NVPTX,1134,bool isVirtualSection (const Section& section) { return section.isVirtual(); } LLVM,NVPTX,1135,AU . addPreserved < MachineFunctionAnalysis > (MFA); LLVM,NVPTX,1136, LLVM,NVPTX,1137,AU . addPreserved < MachineFunctionAnalysis > (MFA); LLVM,NVPTX,1138,for (unsigned i = 0; i != SplitPoints.size(); i++) { changed = true; Instruction *inst = SplitPoints[i]; LLVM,NVPTX,1139,return hasFP16Math() && NoF16Math; LLVM,NVPTX,1140,"TargetName = std::string(CPU.empty() ? """" : CPU);" LLVM,NVPTX,1141,const TargetFrameLowering * getFrameLowering ( ) const override { return & FrameLowering; } LLVM,NVPTX,1142,{ return &InstrInfo; } LLVM,NVPTX,1143,"const char* ptx) { if (ptx.find(""ptx"") != std::string::npos) { std::string version = ptx.substr(ptx.find(""ptx"") + 3); int versionNumber = std::stoi(version); return versionNumber; } else {" LLVM,NVPTX,1144,const ISA_LIT RegisterInfo * getRegisterInfo() { } LLVM,NVPTX,1145,{ return m_selectionDAGInfo; } const TargetSelectionDAGInfo * getSelectionDAGInfo ( ) const override { return m_selectionDAGInfo; } const TargetSelectionDAGInfo * getSelectionDAGInfo ( ) const override { return m_selectionDAG LLVM,NVPTX,1146,const TargetSelectionDAGInfo * getSelectionDAGInfo ( ) const override { return & TSInfo; } LLVM,NVPTX,1147,const unsigned int SmVersion = 1; LLVM,NVPTX,1148,{ return m_smVersion; } LLVM,NVPTX,1149, LLVM,NVPTX,1150, LLVM,NVPTX,1151,return SmVersion; LLVM,NVPTX,1152, LLVM,NVPTX,1153, LLVM,NVPTX,1154, LLVM,NVPTX,1155, LLVM,NVPTX,1156,return SmVersion; LLVM,NVPTX,1157, LLVM,NVPTX,1158,{ return (m_flags & F32_FTZ) != 0; } LLVM,NVPTX,1159,{ return (m_flags & FMAF32) != 0; } LLVM,NVPTX,1160,bool hasFMAF64() { LLVM,NVPTX,1161,bool hasFMAF64 ( ) const { return SmVersion >= 6.2; } Explanation: LLVM,NVPTX,1162, LLVM,NVPTX,1163,inline bool hasHWROT32() { LLVM,NVPTX,1164,return false; LLVM,NVPTX,1165,"if (TM.getDrvInterface() == """") return SmVersion;" LLVM,NVPTX,1166, LLVM,NVPTX,1167,bool hasLDG (int x) { LLVM,NVPTX,1168,return ( ( SmVersion >= ) && ( SmVersion < ( + 1) ) ); LLVM,NVPTX,1169,( ( SmVersion >= ) && ( SmVersion < ) ) ); } LLVM,NVPTX,1170,inline bool hasROT32 ( ) { LLVM,NVPTX,1171,inline bool hasROT64 ( ) const { return SmVersion >= 64; } LLVM,NVPTX,1172,return SmVersion; LLVM,NVPTX,1173,inline bool hasSWROT32 ( ) const { return ( ( SmVersion >= 32 ) && ( SmVersion < 64 ) ); } LLVM,NVPTX,1174,inline bool hasSWROT32 ( ) const { return ( ( SmVersion >= 32 ) && ( SmVersion < 64 ) ); } LLVM,NVPTX,1175,bool hasVote (string voterId) { return votes.containsKey(voterId); } LLVM,NVPTX,1176,bool hasAtomScope (const std::string& atom) { return atomScopes.count(atom) > 0; } LLVM,NVPTX,1177, LLVM,NVPTX,1178,if (is64Bit()) { LLVM,NVPTX,1179,inline bool hasROT32 ( ) const { return hasHWROT32 ( ) || hasSWROT32 ( ); } LLVM,NVPTX,1180, LLVM,NVPTX,1181, LLVM,NVPTX,1182,"TargetName = std::string(CPU.empty() ? """" : CPU); ParseSubtargetFeatures(TargetName, FS); if (PTXVersion == ) { PTXVersion = ; }" LLVM,NVPTX,1183, LLVM,NVPTX,1184,const SelectionDAGTargetInfo * getSelectionDAGInfo ( ) const override { return &selectionDAGTargetInfo; } LLVM,NVPTX,1185,return &TSInfo; LLVM,NVPTX,1186,bool hasAtomAddF64 ( ) { LLVM,NVPTX,1187,return SmVersion; LLVM,NVPTX,1188,bool hasAtomMinMax64 ( ) const { return SmVersion >= ; } LLVM,NVPTX,1189,bool Atom::hasAtomScope() { LLVM,NVPTX,1190,bool hasFP16Math ( ) const { return SmVersion >= 5.0; } LLVM,NVPTX,1191, LLVM,NVPTX,1192,"Subtarget::Subtarget(const std::string &TT, const std::string &CPU, const std::string &FS, const TargetMachine &TM, bool is64Bit)" LLVM,NVPTX,1193, LLVM,NVPTX,1194, LLVM,NVPTX,1195,DataLayout; } LLVM,NVPTX,1196, LLVM,NVPTX,1197,const InstrInfo * getInstrInfo ( ) { return &instrInfo; } LLVM,NVPTX,1198, LLVM,NVPTX,1199,return &TLInfo; LLVM,NVPTX,1200,static Target TheTarget64; LLVM,NVPTX,1201,"RegisterTarget < Triple :: nvptx > X ( getTheTarget32 ( ) , );" LLVM,NVPTX,1202,"void LLVMInitializeTargetInfo ( ) { RegisterTarget < Triple :: nvptx > X ( getTheTarget32 ( ) , , , ) ; RegisterTarget < Triple :: nvptx64 > Y ( getTheTarget64 ( ) , , , ) ; }" LLVM,NVPTX,1203,RegisterTarget < Triple :: nvptx64 > Y ( getTheTarget64 ( LLVM,NVPTX,1204,"void LLVMInitializeTargetInfo ( ) { RegisterTarget < Triple :: nvptx > X ( TheTarget32 , , ) ; RegisterTarget < Triple :: nvptx64 > Y ( TheTarget64 , , ) ; }" LLVM,NVPTX,1205,createInferAddressSpacesPass ( ) ) ; addPass ( createAtomicLowerPass ( ) ) ; LLVM,NVPTX,1206,FastRegAlloc::ID ); } LLVM,NVPTX,1207,addPass(createImageOptimizerPass()); LLVM,NVPTX,1208,addPass ( & LiveVariablesID ) ; addPass ( & MachineLoopInfoID ) ; addPass ( & PHIEliminationID ) ; addPass ( & TwoAddressInstructionPassID ) ; addPass ( & RegisterCoalescerID ) ; addPass ( & DeadCodeEliminationID ) ; addPass ( & ConstantPropagationID ) ; addPass ( & InstructionCombiningID ) ; addPass ( & ReassociationID ) ; addPass ( & ScalarReplAggregationID ) ; addPass ( & SCCPID ) ; addPass LLVM,NVPTX,1209,addPass(createPrologEpilogPass()); LLVM,NVPTX,1210,void ISA_LITPassConfig :: addPreRegAlloc ( ) { addPass ( createProxyRegErasurePass ( ) ); } LLVM,NVPTX,1211,"""Unreachable code executed, aborting!"");" LLVM,NVPTX,1212,"llvm_unreachable(""This function should never return"");" LLVM,NVPTX,1213,addPass(createSeparateConstOffsetFromGEPPass()); LLVM,NVPTX,1214,"The last statement of the code snippet is `PM.addExtension(PassManagerBuilder::EP_EarlyAsPossible, [&](const PassManagerBuilder &PM) {`. This statement adds an early as possible extension to the pass manager builder using the `addExtension` method. The extension is defined as a lambda function that takes a `const PassManagerBuilder" LLVM,NVPTX,1215,"void TargetMachine::adjustPassManager(PassManagerBuilder &Builder) { Builder.addExtension(PassManagerBuilder::EP_EarlyAsPossible, [&](const PassManagerBuilder &, legacy::PassManagerBase &PM) { PM.add(createNVVMReflectPass(Subtarget.getSmVersion())); }); }" LLVM,NVPTX,1216,"static std :: string computeDataLayout ( bool is64Bit , bool UseShortPointers ) { std :: string Ret; if (is64Bit) { Ret = ""64-bit""; } else { Ret = ""32-bit""; } if (UseShortPointers) { Ret += "" with short pointers""; } else { Ret += "" with long pointers""; } return Ret; }" LLVM,NVPTX,1217,if ( ! is64Bit ) Ret += ; else if ( UseShortPointers ) Ret += ; LLVM,NVPTX,1218, LLVM,NVPTX,1219,TargetTransformInfo TargetMachine :: getTargetTransformInfo () const { return TargetTransformInfo TargetMachine (this); } LLVM,NVPTX,1220,createEarlyCSEPass ( ) ); } LLVM,NVPTX,1221,return false; LLVM,NVPTX,1222,addEarlyCSEOrGVNPass(); LLVM,NVPTX,1223, LLVM,NVPTX,1224,"createPeephole ( ) , false ) ;" LLVM,NVPTX,1225,); Here is an example of how you LLVM,NVPTX,1226, LLVM,NVPTX,1227, LLVM,NVPTX,1228, LLVM,NVPTX,1229,void LLVMInitializeTarget ( ) { LLVM,NVPTX,1230,RegisterTargetMachine < TargetMachine32 > X ( TheTarget32 ) ; LLVM,NVPTX,1231,"TargetMachine :: TargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL , bool is64bit ) : LLVMTargetMachine ( T , computeDataLayout ( is64bit ) ," LLVM,NVPTX,1232,return &Subtarget; LLVM,NVPTX,1233,bool is64Bit() { LLVM,NVPTX,1234,bool is64Bit() { LLVM,NVPTX,1235,void LLVMInitializeTarget ( ) { LLVM,NVPTX,1236,RegisterTargetMachine < TargetMachine64 > Y ( TheTarget64 ); LLVM,NVPTX,1237,createPromoteMemoryToRegisterPass ( ) ) ; LLVM,NVPTX,1238,void PassConfig :: addAddressSpaceInferencePasses ( ) { addPass ( createSROAPass ( ) ) ; addPass ( createAddressSpaceLowerAllocaPass ( ) ) ; addPass ( createInferAddressSpacesPass ( ) ) ; } LLVM,NVPTX,1239,disablePass ( & LiveDebugValuesID ) ; LLVM,NVPTX,1240, LLVM,NVPTX,1241,PM.add(createNVVMReflectPass()); LLVM,NVPTX,1242,initializeLowerArgsPass ( PR ) ; LLVM,NVPTX,1243,"TargetMachine :: TargetMachine ( const Target & T , const Triple & TT , StringRef" LLVM,NVPTX,1244,addPass ( create LLVM,NVPTX,1245,"virtual bool addPassesToEmitMachineCode(PassManagerBase &PM, JITCodeEmitter &JCE, bool = true) {" LLVM,NVPTX,1246,"virtual bool addPassesToEmitMC ( PassManagerBase & , MCContext * & , raw_ostream & , bool = false )" LLVM,NVPTX,1247,"virtual bool addPassesToEmitMC ( PassManagerBase & , MCContext * & , raw_ostream & , bool = true ) { return false; }" LLVM,NVPTX,1248,DataLayout; LLVM,NVPTX,1249,virtual const TargetFrameLowering * getFrameLowering ( ) const { return & FrameLowering; } LLVM,NVPTX,1250,virtual const InstrInfo LLVM,NVPTX,1251,m_managedStrPool ); LLVM,NVPTX,1252,switch (II->getIntrinsicID()) { LLVM,NVPTX,1253,virtual const ISA_LIT RegisterInfo * getRegisterInfo () const = 0; LLVM,NVPTX,1254,virtual const TargetSelectionDAGInfo * getSelectionDAGInfo ( ) const { return & TSInfo; } LLVM,NVPTX,1255,virtual const ISA_LIT>Subtarget * getSubtargetImpl ( ) const { return & Subtarget; } LLVM,NVPTX,1256,virtual const Subtarget * getSubtargetImpl ( ) const { return &Subtarget; } Explanation: LLVM,NVPTX,1257,"const Target &T, const TargetOptions &Opts) const override { if (T.getArch() == Triple::aarch64) { return new AArch64TargetLowering(T, Opts); } else if (T.getArch() == Triple::arm) { return new ARMTargetLowering(T, Opts); } else if (T.getArch() == Triple::x86) { return new X86TargetLowering(T, Opts); } else if (T" LLVM,NVPTX,1258,virtual const VectorTargetTransformInfo * getVectorTargetTransformInfo ( ) const { return &m_vectorTargetTransformInfo; } LLVM,NVPTX,1259,createPromoteMemoryToRegisterPass ( ) ) ; LLVM,NVPTX,1260,void PassConfig::addAddressSpaceInferencePasses() { LLVM,NVPTX,1261,PM . add ( createNVVMIntrRangePass ( Subtarget . getSmVersion ( ) ) ) ; LLVM,NVPTX,1262,"bool addPassesToEmitMC ( PassManagerBase & , MCContext * & , raw_pwrite_stream & , bool = true ) override { return true; }" LLVM,NVPTX,1263, LLVM,NVPTX,1264,bool isMachineVerifierClean ( LLVM,NVPTX,1265,{ return sizeof(int) < sizeof(char*); } LLVM,NVPTX,1266,bool useShortPointers ( ) const { return sizeof(void*) <= 4; } Explanation: LLVM,NVPTX,1267,if ( ! is64Bit ) Ret += ; Ret += ; LLVM,NVPTX,1268,static CodeModel::Model getEffectiveCodeModel(Optional CM) { LLVM,NVPTX,1269,static CodeModel :: Model getEffectiveCodeModel ( Optional < CodeModel :: Model > model) { LLVM,NVPTX,1270,void PassConfig :: addIRPasses ( ) { disablePass ( & PrologEpilogCodeInserterID ) ; disablePass ( & MachineCopyPropagationID ) ; disablePass ( & BranchFolderPassID ) ; disablePass ( & TailDuplicateID ) ; addPass ( createImageOptimizerPass ( ) ) ; TargetPassConfig :: addIRPasses ( ) ; addPass ( createAssignValidGlobalNamesPass ( ) ) ; LLVM,NVPTX,1271,initializeNVVMReflectPass(*PassRegistry::getPassRegistry()); LLVM,NVPTX,1272,PassRegistry :: getPassRegistry ( ) ) ; LLVM,NVPTX,1273,DL ( new DataLayout ( T.getDataLayout ( ) ) ) ) LLVM,NVPTX,1274,"CM , OL , is64bit ) {" LLVM,NVPTX,1275,const ISA_LIT>RegisterInfo * getRegisterInfo () { return ®isterInfo; } LLVM,NVPTX,1276, LLVM,NVPTX,1277, LLVM,NVPTX,1278,addPass([&]() { LLVM,NVPTX,1279,addPass(createEarlyCSEPass()); LLVM,NVPTX,1280,addPass(createEarlyCSEPass()); LLVM,NVPTX,1281, LLVM,NVPTX,1282,RegisterTargetMachine < TargetMachine64 > Y ( TheTarget64 ) ; LLVM,NVPTX,1283,"TargetMachine :: TargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL , bool is64bit ) : LLVMTargetMachine ( T , TT , CPU , FS ) {" LLVM,NVPTX,1284,addPass(createLowerArgsPass(&getTargetMachine())); LLVM,NVPTX,1285, LLVM,NVPTX,1286, LLVM,NVPTX,1287,"""Optimization not yet implemented"" ); }" LLVM,NVPTX,1288, LLVM,NVPTX,1289,"TLOF ( llvm :: make_unique < TargetObjectFile > ( ) ) , Subtarget ( TT , CPU , FS , * this ) { if ( TT . getOS ( ) == Triple :: NVCL ) drvInterface ( llvm :: make_unique < DriverInterface > ( ) ) , is64bit ( is64bit ) , UseShortPointers ( UseShortPointersOpt ) , TLOF ( llvm :: make" LLVM,NVPTX,1290, LLVM,NVPTX,1291,"if ( ! ST . is64Bit ( ) ) Ret += ""This is a 32-bit system."";" LLVM,NVPTX,1292,"CM , OL , is64bit ) {" LLVM,NVPTX,1293,{ LLVM,NVPTX,1294,addPass(createInlinePass( & getTargetMachine ( ) ) ) ; LLVM,NVPTX,1295, LLVM,NVPTX,1296, LLVM,NVPTX,1297,addPass(createLowerKernelArgsPass(&getTargetMachine())); LLVM,NVPTX,1298, LLVM,NVPTX,1299,initializeLowerAllocaPass ( * PassRegistry :: getPassRegistry ( ) ) ; LLVM,NVPTX,1300, LLVM,NVPTX,1301, LLVM,NVPTX,1302,initializeLowerAggrCopiesPass(PR); LLVM,NVPTX,1303,initializeLowerAllocaPass ( PR ) ; LLVM,NVPTX,1304, LLVM,NVPTX,1305,return false; LLVM,NVPTX,1306,initializeGenericToNVVMPass(PassRegistry::getPassRegistry()); LLVM,NVPTX,1307,"""RegAllocPass && !RegAllocPass->getPreserveFP()"");" LLVM,NVPTX,1308,disablePass ( & BranchFolderPassID ) ; LLVM,NVPTX,1309,"void PassConfig :: addOptimizedRegAlloc ( FunctionPass * RegAllocPass ) { RegAllocPass->setPassName(""Optimized Register Allocation""); RegAllocPass->setPassType(PassType::REG_ALLOC); RegAllocPass->setPassDescription(""Optimize register allocation for the function""); addPass(RegAllocPass); }" LLVM,NVPTX,1310,FunctionPass * PassConfig :: createTargetRegisterAllocator () { return new TargetRegisterAllocator(); } LLVM,NVPTX,1311,return &targetData; LLVM,NVPTX,1312,"TargetMachine :: TargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL , bool is64bit ) : LLVMTargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL ) , Subtarget ( TT , CPU , FS , is64bit" LLVM,NVPTX,1313,{ LLVM,NVPTX,1314,addPass(createDeadCodeEliminationPass()); LLVM,NVPTX,1315,void LLVMInitializeTarget ( ) { LLVM,NVPTX,1316,PassRegistry :: getPassRegistry ( ) ) ; LLVM,NVPTX,1317,initAsmInfo(); LLVM,NVPTX,1318,PM.add(createTargetTransformInfoPass(this)); LLVM,NVPTX,1319,PM.add(createTargetTransformInfoPass(this)); LLVM,NVPTX,1320,initAsmInfo(); LLVM,NVPTX,1321,addPass(createAssignValidGlobalNamesPass()); LLVM,NVPTX,1322,if ( !DisableRequireStructuredCFG ) { LLVM,NVPTX,1323,Triple::OSType::Unknown ) { UseShortPointers = false; } LLVM,NVPTX,1324,void PassConfig::addIRPasses() { TargetPassConfig::addIRPasses(); addPass(createGenericToNVVMPass()); } LLVM,NVPTX,1325,( * PassRegistry :: getPassRegistry ( ) ) ; LLVM,NVPTX,1326,disablePass(&MachineCopyPropagationID); LLVM,NVPTX,1327,disablePass ( & TailDuplicateID ) ; LLVM,NVPTX,1328, LLVM,NVPTX,1329,disablePass ( & MachineCopyPropagationID ) ; LLVM,NVPTX,1330,void PassConfig :: addIRPasses ( ) { disablePass ( & PrologEpilogCodeInserterID ) ; disablePass ( & MachineCopyPropagationID ) ; disablePass ( & TailDuplicateID ) ; disablePass ( & StackMapLivenessID ) ; disablePass ( & LiveDebugValuesID ) ; disablePass ( & PostRASchedulerID ) ; disablePass ( & FuncletLayoutID ) ; disablePass ( & PatchableFunctionID ) ; addPass ( createN LLVM,NVPTX,1331,PassRegistry::getPassRegistry(); LLVM,NVPTX,1332,addPass(createInferAddressSpacesPass()); LLVM,NVPTX,1333, LLVM,NVPTX,1334,initializeLowerArgsPass(PR); LLVM,NVPTX,1335, LLVM,NVPTX,1336,addPass(createLocalAccessorToSharedMemoryPass()); LLVM,NVPTX,1337,initializeAllocaHoistingPass(PR); LLVM,NVPTX,1338, LLVM,NVPTX,1339,CodeGenOpt::None ) { addPass(createInstructionCombiningPass()); addPass(createReassociatePass()); addPass(createGVNPass()); addPass(createDeadStoreEliminationPass()); addPass(createAggressiveDCEPass()); addPass(createCFGSimplificationPass()); addPass(creategetTargetLowering ( ); } LLVM,NVPTX,1349,const ISA_LIT>TargetLowering * getTargetLowering ( ) const override { return getSubtargetImpl ( ) -> getTargetLowering ( ); } LLVM,NVPTX,1350,"MCSection * getExplicitSectionGlobal ( const GlobalValue * GV , SectionKind Kind , Mangler & Mang ) {" LLVM,NVPTX,1351,"DwarfDebugInlineSection = new Section ( MCSection :: SV_ELF , SectionKind :: getMetadata ( ) ) ;" LLVM,NVPTX,1352, LLVM,NVPTX,1353,DwarfRangesSection = nullptr; LLVM,NVPTX,1354,"MCSection * getExplicitSectionGlobal ( const GlobalObject * GO , SectionKind Kind , const TargetMachine & TM ) const override { return TM.getExplicitSectionGlobal(GO, Kind); }" LLVM,NVPTX,1355,"MCSection * getSectionForConstant ( const DataLayout & DL , SectionKind Kind , const Constant * C , Align & Alignment ) const override { std::string sectionName = getSectionNameForConstant(C); Alignment = getAlignmentForConstant(C); return getSection(sectionName, Kind, Alignment); }" LLVM,NVPTX,1356,"MCSection * getSectionForConstant ( const DataLayout & DL , SectionKind Kind , const Constant * C , Align & Alignment ) const override { std::string sectionName = getSectionNameForConstant(C); Alignment = getAlignmentForConstant(C); return getSection(sectionName, Kind, Alignment); }" LLVM,NVPTX,1357,MCInst & inst ) { inst.setOpcode(ctx.getOpcode()); inst.setOperands(ctx.getOperands()); inst.setAddress(ctx.getAddress()); inst.setSize(ctx.getSize()); inst.setFlags(ctx.getFlags()); } LLVM,NVPTX,1358,MCSection * getSectionForConstant ( const DataLayout & LLVM,NVPTX,1359, LLVM,NVPTX,1360,DwarfLocSection = nullptr ; LLVM,NVPTX,1361,DwarfMacroInfoSection = ; LLVM,NVPTX,1362,return ReadOnlySection; LLVM,NVPTX,1363,"EHFrameSection = new Section ( MCSection :: SV_ELF , SectionKind :: getEHFrame ( ) ) ;" LLVM,NVPTX,1364,"DwarfRangesSection = new Section ( MCSection :: SV_ELF , SectionKind :: getMetadata ( ) ) ; DwarfMacinfoSection = new Section ( MCSection :: SV_ELF , SectionKind :: getMetadata ( ) ) ;" LLVM,NVPTX,1365,delete DwarfMacroInfoSection; LLVM,NVPTX,1366,delete DwarfStrOffSection; LLVM,NVPTX,1367,"ReadOnlySection = new Section ( MCSection :: SV_ELF , SectionKind :: getReadOnly ( ) ) ;" LLVM,NVPTX,1368,"switch (Kind) { case SectionKind::Text: return &TextSection; case SectionKind::Data: return &DataSection; case SectionKind::BSS: return &BSSSection; case SectionKind::Common: return &CommonSection; default: llvm_unreachable(""Invalid section kind""); } }" LLVM,NVPTX,1369,return DataSection; LLVM,NVPTX,1370,DwarfPubNamesSection = nullptr; LLVM,NVPTX,1371,"if (isDwarfSection(FI, Section))" LLVM,NVPTX,1372,for (const std::string& S : DwarfFiles) LLVM,NVPTX,1373,DwarfFiles.clear();` LLVM,NVPTX,1374,"Section->PrintSwitchToSection(getStreamer(), FI->getTargetTriple(), OS, SubSection);" LLVM,NVPTX,1375,"OS << "".file\n"";" LLVM,NVPTX,1376,void TargetStreamer::closeLastSection() { if (m_lastSection) { m_lastSection->close(); m_lastSection = nullptr; } } LLVM,NVPTX,1377, LLVM,NVPTX,1378,void ISA_LITTargetStreamer::outputDwarfFileDirectives() { for (const std::string& S : DwarfFiles) { getStreamer()->emitRawText(S); } } LLVM,NVPTX,1379,getStreamer().emitRawText(S); LLVM,NVPTX,1380,Str ); LLVM,NVPTX,1381,"if (isDwarfSection(FI, CurSection))" LLVM,NVPTX,1382,void TargetStreamer :: closeLastSection ( ) { if ( HasSections ) getStreamer ( ) -> closeLastSection ( ); } LLVM,NVPTX,1383,for (unsigned I = 0; I < NumChunks; ++I) { LLVM,NVPTX,1384, LLVM,NVPTX,1385, LLVM,NVPTX,1386, LLVM,NVPTX,1387,const ISA_LIT *Subtarget * getST ( ) { return &st; } LLVM,NVPTX,1388,class MyClass { LLVM,NVPTX,1389,const ISA_LIT>TargetLowering * getTLI ( ) const { return TLI; } LLVM,NVPTX,1390,const ISA_LIT>TargetLowering * getTLI ( ) const { return TLI; } LLVM,NVPTX,1391,"SE , UP );" LLVM,NVPTX,1392,bool hasBranchDivergence(Node* node) { LLVM,NVPTX,1393,bool hasBranchDivergence (Instruction* I) { LLVM,NVPTX,1394,return II -> getIntrinsicID(II); LLVM,NVPTX,1395,"bool isLegalToVectorizeLoadChain ( unsigned ChainSizeInBytes , Align Alignment , unsigned AddrSpace ) const {" LLVM,NVPTX,1396,"bool isLegalToVectorizeStoreChain ( unsigned ChainSizeInBytes , Align Alignment , unsigned AddrSpace ) const { return isLegalToVectorizeLoadChain ( ChainSizeInBytes , Alignment ) && isLegalToVectorizeStore ( ChainSizeInBytes , Alignment , AddrSpace ); }" LLVM,NVPTX,1397,"return isLegalToVectorizeLoadChain(ChainSizeInBytes, Alignment, AddrSpace) &&" LLVM,NVPTX,1398,"void TTIImpl::getPeelingPreferences(Loop *L, ScalarEvolution &SE, TTI::PeelingPreferences &PP) { BaseT::getPeelingPreferences(L, SE, PP); }" LLVM,NVPTX,1399,"BaseT :: getPeelingPreferences ( L , SE )" LLVM,NVPTX,1400,return TypeSize::getFixed(10); LLVM,NVPTX,1401,TypeSize getRegisterBitWidth ( TargetTransformInfo :: RegisterKind K ) const { return TypeSize :: getFixed ( ); } LLVM,NVPTX,1402,"void TTIImpl :: getUnrollingPreferences ( Loop * L , ScalarEvolution & SE , TTI :: UnrollingPreferences & UP ) { const SCEV * TripCount = SE.getTripCount(L); const SCEV * UnrollFactor = SE.getUnrollFactor(L); const SCEV * UnrollCount = SE.getUnrollCount(L);" LLVM,NVPTX,1403,UP.Partial = true; LLVM,NVPTX,1404,"return { Instruction :: FDiv , FTZ_Any } ; case : return { Instruction :: FDiv , FTZ_MustBeOff } ; case : return { Instruction :: FDiv , FTZ_MustBeOn } ; case : return { Instruction :: FRem , FTZ_Any } ; case : return { Instruction :: FRem , FTZ_MustBeOff } ; case getIntrinsicID(); LLVM,NVPTX,1406,static bool readsLaneId ( const IntrinsicInst * II ) { return II->getIntrinsicID() == Intrinsic::readlane; } LLVM,NVPTX,1407,int ISD = TLI -> InstructionOpcodeToISD ( Opcode ) ; LLVM,NVPTX,1408,"ISD = TLI -> InstructionOpcodeToISD ( Opcode ) ; switch ( ISD ) { default : return BaseT :: getArithmeticInstrCost ( Opcode , Ty , Opd1Info , Opd2Info , Opd1PropInfo , Opd2PropInfo ) ; case ISD::MUL : case ISD::ADD : case ISD::SUB : case ISD::AND : return BaseT :: getArithmeticInstrCost ( Opcode , Ty , Opd1Info , Opd2Info , Opd1PropInfo , Opd2PropInfo" LLVM,NVPTX,1409, LLVM,NVPTX,1410,bool canHaveNonUndefGlobalInitializerInAddressSpace ( unsigned AS ) const { LLVM,NVPTX,1411,"TargetMachine *TM, const DataLayout *DL) { return new ImmutablePassTargetTransformInfoPass(TM, DL); }" LLVM,NVPTX,1412,ImmutablePass * llvm :: createTargetTransformInfoPass ( const TargetMachine * TM ) { return new TTI ( TM ); } LLVM,NVPTX,1413,void getAnalysisUsage ( AnalysisUsage & AU ) const override { LLVM,NVPTX,1414, LLVM,NVPTX,1415, LLVM,NVPTX,1416, LLVM,NVPTX,1417,pushTTIStack(this); LLVM,NVPTX,1418,"areInlineCompatible(const Function *Caller, const Function *Callee) const { return Caller->getCallingConv() == Callee->getCallingConv() && Caller->getAttributes() == Callee->getAttributes() && Caller->getParamAttrs() == Callee->getParamAttrs() && Caller->getRetAttrs() == Callee->getRetAttrs(); }" LLVM,NVPTX,1419,def get_address_space(self): LLVM,NVPTX,1420,return AddressSpace::Instance(); LLVM,NVPTX,1421, LLVM,NVPTX,1422,unsigned getMinVectorRegisterBitWidth () { #if defined(__AVX512F__) return 512; #elif defined(__AVX__) return 256; #elif defined(__SSE__) return 128; #else return 0; #endif } LLVM,NVPTX,1423,unsigned getNumberOfRegisters ( bool Vector ) const { return Vector ? 16 : 32; } LLVM,NVPTX,1424,Here is an example of how you could complete the last LLVM,NVPTX,1425,"void TTIImpl::getUnrollingPreferences(Loop *L, TTI::UnrollingPreferences &UP) { BaseT::getUnrollingPreferences(L, UP); UP.Partial = UP.Runtime = true; UP.PartialThreshold = UP.Threshold; }" LLVM,NVPTX,1426,ChainSizeInBytes; LLVM,NVPTX,1427,"bool isLegalToVectorizeStoreChain ( unsigned ChainSizeInBytes , unsigned Alignment , unsigned AddrSpace ) const { return isLegalToVectorizeLoadChain ( ChainSizeInBytes , Alignment ) && isLegalToVectorizeStoreChain ( ChainSizeInBytes , Alignment , AddrSpace ); }" LLVM,NVPTX,1428,"static bool isNVVMAtomic ( const IntrinsicInst * II ) { switch ( II -> getIntrinsicID ( ) ) { default : return false ; case ""nvvm.atomic.load"" : case ""nvvm.atomic.store"" : case ""nvvm.atomic.exchange"" : case ""nvvm.atomic.compare.exchange"" : case ""nvvm.atomic.fetch.add"" : case ""nvvm.atomic.fetch.sub"" : case ""nvvm.atomic.fetch.and"" : case ""nvvm" LLVM,NVPTX,1429, LLVM,NVPTX,1430, LLVM,NVPTX,1431, LLVM,NVPTX,1432,if ( ( * annotationCache ) [ m ] [ gv ] [ prop ] == ( * annotationCache ) [ m ] [ gv ] . end ( ) LLVM,NVPTX,1433,"""max-nreg"" , x ) ; }" LLVM,NVPTX,1434,"return findOneNVVMAnnotation ( & F , , );" LLVM,NVPTX,1435,"return findOneNVVMAnnotation(&F, ""my_annotation"");" LLVM,NVPTX,1436,"return findOneNVVMAnnotation(&F, ""my_annotation"");" LLVM,NVPTX,1437,x ); } LLVM,NVPTX,1438,"""reqntidx"", x); }" LLVM,NVPTX,1439,int & NTIDy) { if (F.getReturnType() == Type::getVoidTy(F.getContext())) { return false; } if (F.getReturnType()->isPointerTy()) { Type *Pointe LLVM,NVPTX,1440,"val.getName() == ""sampler"");" LLVM,NVPTX,1441,return std::string(val.getName()); LLVM,NVPTX,1442,return std::string(val.getName()); LLVM,NVPTX,1443,"return std::string(val.begin(), val.end());" LLVM,NVPTX,1444,bool isImage ( const Value & val ) { return isImageReadOnly ( val ) || isImageWriteOnly ( val ) || isImageReadWrite ( val ); } Explanation: LLVM,NVPTX,1445,"const Function * func = arg -> getParent ( ) ; std :: vector < unsigned > annot ; if ( findAllNVVMAnnotation ( func , ""nvvm.annotations"" ) ) { annot = getAnnotations ( func , ""nvvm.annotations"" ) ; }" LLVM,NVPTX,1446, LLVM,NVPTX,1447,bool isImageWriteOnly ( const Value & val ) { if ( const Argument * arg = dyn_cast < Argument > ( val ) ) { return arg->hasNoAliases() && arg->onlyWrittenInCaller(); } return false; } LLVM,NVPTX,1448,return false; LLVM,NVPTX,1449,"if ( const Argument * arg = dyn_cast < Argument > ( & val ) ) { const Function * func = arg -> getParent ( ) ; std :: vector < unsigned > annots ; if ( findAllNVVMAnnotations ( func , AnnotationName , annots ) ) { for ( unsigned annot : annots ) { assert ( ( annot == ) && ) ; return true ; } } } } return false ;" LLVM,NVPTX,1450,``` LLVM,NVPTX,1451,"bool isSurface ( const Value & val ) { if ( const GlobalValue * gv = dyn_cast < GlobalValue > ( & val ) ) { unsigned annot ; if ( findOneNVVMAnnotation ( gv , ""surface"" , annot ) ) { return true ; } } return false ; }" LLVM,NVPTX,1452,NamedMDNode *NMD = m->getNamedMetadata(llvm::NamedMDForAnnotations); LLVM,NVPTX,1453,return; LLVM,NVPTX,1454,"for (Function::iterator it = F->begin(), ie = F->end(); it != ie; ++it) {" LLVM,NVPTX,1455,if ((*annotationCache).find(m) == (*annotationCache).end()) { LLVM,NVPTX,1456, LLVM,NVPTX,1457,) { align = v & ; return true ; } } } } return false ; } LLVM,NVPTX,1458,"""nvvmir.annotations"") != nullptr;" LLVM,NVPTX,1459,"bool llvm :: getMaxNTIDz ( const Function & F , unsigned & z ) {" LLVM,NVPTX,1460,"return ( llvm :: findOneNVVMAnnotation ( & F , llvm :: PropertyAnnotationNames [ ""llvm.nvvm.annotations"" ] ) );" LLVM,NVPTX,1461,return getMinCTASm(F); LLVM,NVPTX,1462, LLVM,NVPTX,1463,"return llvm::findOneNVVMAnnotation(&F, llvm::PropertyAnnotationNames::N" LLVM,NVPTX,1464,"bool llvm::getReqNTIDx(const Function &F, unsigned &x) {" LLVM,NVPTX,1465,"llvm::PropertyAnnotationNames::ReqNTIDY, y ) ); }" LLVM,NVPTX,1466,"llvm::PropertyAnnotationNames::ReqNTIDz, z ); }" LLVM,NVPTX,1467,"PropertyAnnotationNames::ReqNTIDz ], z ) ); }" LLVM,NVPTX,1468,bool llvm::isImage(const llvm::Value& val) { LLVM,NVPTX,1469,bool llvm::isImageReadOnly(const llvm::Value& val) { LLVM,NVPTX,1470,return false; LLVM,NVPTX,1471,return false; LLVM,NVPTX,1472,return true; LLVM,NVPTX,1473,if ( const GlobalValue * gv = dyn_cast < GlobalValue > ( & val ) ) { LLVM,NVPTX,1474,tmp1 ) ; LLVM,NVPTX,1475,( * annotationCache ) LLVM,NVPTX,1476,annotationCache -> erase(annotation); LLVM,NVPTX,1477,"annotationCache -> erase (annotationCache -> begin (), annotationCache -> end ());" LLVM,NVPTX,1478, LLVM,NVPTX,1479,retval = ( * annotationCache ) [ m ] [ gv ] [ prop ] [ ] ; LLVM,NVPTX,1480, LLVM,NVPTX,1481,") { if (val.IsObject()) { const rapidjson::Value& sampler = val[""sampler""]; if (sampler.IsString()) { return sampler.GetString(); } } return """"; }" LLVM,NVPTX,1482,"assert ( val.hasName() && val.getName() == ""John"" );" LLVM,NVPTX,1483,assert ( val . hasName ( ) == true ); LLVM,NVPTX,1484,(*annotationCache)[m][gv] = tmp; LLVM,NVPTX,1485,retval; LLVM,NVPTX,1486,"( * annotationCache ) [ m ] [ gv ] . end ( ) ) { retval.clear(); return false; } const std::vector &annots = ( * annotationCache ) [ m ] [ gv ] [ prop ]; retval.insert(retval.end(), annots.begin(), annots.end()); return true; }" LLVM,NVPTX,1487,else if ((*annotationCache)[m].find(gv) == (*annotationCache)[m].end()) LLVM,NVPTX,1488,retval = ( * annotationCache ) [ m ] [ gv ] [ prop ] [ ] ; LLVM,NVPTX,1489,if ( ( * annotationCache ) . find ( m ) == ( * annotationCache ) . end ( ) ) LLVM,NVPTX,1490,const Function * func = arg->getParent(); LLVM,NVPTX,1491,unsigned annot; LLVM,NVPTX,1492,tmp.push_back(entity); LLVM,NVPTX,1493,if (tmp.empty()) return; LLVM,NVPTX,1494, LLVM,NVPTX,1495,( 1 << ) - 1 ; return true ; } } } } return false ; } LLVM,NVPTX,1496,"assert ( ( md -> getNumOperands ( ) % ) == && ) ; for ( unsigned i = , e = md -> getNumOperands ( ) ; i != e ; i += ) { const MDString * prop = dyn_cast < MDString > ( md -> getOperand ( i ) ) ;" LLVM,NVPTX,1497,retval[keyname] = Val->getZExtValue(); LLVM,NVPTX,1498,} else if (const GEPOperator *GEP = dyn_cast(V)) { V = GEP->getPointerOperand()->stripPointerCasts(); continue; } else if (const PHINode *PN = dyn_cast(V LLVM,NVPTX,1499, LLVM,NVPTX,1500,void llvm::clearAnnotationCache(const llvm::Module& M) { M.clearAnnotationCache(); } LLVM,NVPTX,1501,return; LLVM,NVPTX,1502,F->end ( ) ; ++ it ) { } LLVM,NVPTX,1503,"Instruction * I = getInst ( base , instName ) ; if ( I ) I -> dump ( std::cout ) ;" LLVM,NVPTX,1504,"void llvm::dumpInst(Value *base, char *instName) {" LLVM,NVPTX,1505,if ( ( * annotationCache ) [ m ] [ gv ] . find ( prop ) == ( * annotationCache ) [ m ] [ gv ] . end ( ) ) LLVM,NVPTX,1506,return true; LLVM,NVPTX,1507,"if ( strcmp ( I -> getName ( ) . data ( ) , instName ) == 0 ) {" LLVM,NVPTX,1508,"return llvm::findOneNVVMAnnotation(&F, llvm::PropertyAnnotationNames::N" LLVM,NVPTX,1509,"PropertyAnnotationNames::MaxNTIDY ], y ) ); }" LLVM,NVPTX,1510,"bool llvm :: getMaxNTIDz ( const Function & F , unsigned & z ) {" LLVM,NVPTX,1511,x ) ); } LLVM,NVPTX,1512,return I->getParent(); LLVM,NVPTX,1513, LLVM,NVPTX,1514,int & NTIDx) { if (F.hasExactDefinition()) { NTIDx = F.getExactDefinition().getReqNTIDx(); return true; } return false; } LLVM,NVPTX,1515, LLVM,NVPTX,1516,return getReqNTIDy(F); LLVM,NVPTX,1517,unsigned & NTIDy) { if (F.hasKnownRequiredNTIDy()) { NTIDy = F.getKnownRequiredNTIDy(); return true; } Type *FTy = F.getFunctionType LLVM,NVPTX,1518,"bool llvm::getReqNTIDz(const Function& F, unsigned& NTIDz) {" LLVM,NVPTX,1519,"assert ( val.hasName() && val.getName() == """" );" LLVM,NVPTX,1520,std::string getSamplerName(std::string samplerName) { LLVM,NVPTX,1521,return val.getName(); LLVM,NVPTX,1522,return val.getName(); LLVM,NVPTX,1523,"assert ( val.hasName() && val.getName().equals(""John Doe"") );" LLVM,NVPTX,1524,"return ( id == ""apple"" ) || ( id == ""banana"" ) || ( id == ""orange"" ) || ( id == ""grape"" );" LLVM,NVPTX,1525,return ll LLVM,NVPTX,1526,return ll LLVM,NVPTX,1527, LLVM,NVPTX,1528, LLVM,NVPTX,1529, LLVM,NVPTX,1530,return false; LLVM,NVPTX,1531,"Result.push_back(A); while (T Val = va_arg(Args, T)) { }" LLVM,NVPTX,1532, LLVM,NVPTX,1533, LLVM,NVPTX,1534,getOpcode ( ) != ) ) { return false; } return true; LLVM,NVPTX,1535,return true; LLVM,NVPTX,1536,{ LLVM,NVPTX,1537,getAnalysis().getTLI(F)); } LLVM,NVPTX,1538,getAnalysis().getTLI(F)); } LLVM,NVPTX,1539,"{ ConstantInt * LowConstant = ConstantInt::get(Int32Ty, Low); ConstantInt * HighConstant = ConstantInt::get(Int32Ty, High); Metadata * RangeMetadata = MDNode::get(Context, {LowConstant, HighConstant}); C->setMetadata(""range"", RangeMetadata); return true; }" LLVM,NVPTX,1540, LLVM,NVPTX,1541, LLVM,NVPTX,1542,return true; LLVM,NVPTX,1543,IntrRangePass(unsigned int IntrinsicID) { return new IntrRangePass(IntrinsicID); } LLVM,NVPTX,1544,"return new NVVMIntrRange(SmVersion.SM75, SmVersion.SM86);" LLVM,NVPTX,1545, LLVM,NVPTX,1546, LLVM,NVPTX,1547,initializeNVVMReflectPass ( * PassRegistry :: getPassRegistry ( ) ); LLVM,NVPTX,1548, LLVM,NVPTX,1549,getOperand(0); LLVM,NVPTX,1550,initializeNVVMReflectPass ( * PassRegistry :: getPassRegistry () ); LLVM,NVPTX,1551,assert(isa(Sym) && ); LLVM,NVPTX,1552,AU.setPreservesAll(true); LLVM,NVPTX,1553,AU . setPreservesAll ( true ) LLVM,NVPTX,1554, LLVM,NVPTX,1555, LLVM,NVPTX,1556,return PreservedAnalyses::all(); LLVM,NVPTX,1557,bool NVVMReflect :: runOnFunction ( Function & F ) { return runNVVMReflect ( F ); } LLVM,NVPTX,1558,return runNVVMReflect(F); LLVM,NVPTX,1559, LLVM,NVPTX,1560,ReflectVal = VarMap[ReflectArg]; LLVM,NVPTX,1561,"assert(isa(Operand) && ""Operand must be a constant data sequential"");" LLVM,NVPTX,1562,"Call->replaceAllUsesWith(ConstantInt::get(Call->getType(), ReflectVal));" LLVM,NVPTX,1563,Call) ; LLVM,NVPTX,1564,"begin ( ) ; I != Mapping . end ( ) ; ++I ) { Function * F = I->first; int ID = I->second; ReflectFunction (F, ID); } }" LLVM,NVPTX,1565,length ( ) - ) ; ToRemove . push_back ( Reflect ) ; } LLVM,NVPTX,1566,ToRemove.push_back ( &I ) ; } LLVM,NVPTX,1567,return new NVVMReflect(NVVMReflect.java:108) LLVM,NVPTX,1568,initializeNVVMReflectPass(*PassRegistry::getPassRegistry()); LLVM,NVPTX,1569,ID ) { } LLVM,NVPTX,1570,ToRemove.push_back(Call); LLVM,NVPTX,1571, LLVM,NVPTX,1572,"const Value * Sym = GEP->getOperand(0); assert(isa(Sym) && ""Sym is not a constant""); const Constant * SymStr = cast(Sym); assert(isa(SymStr->getOperand(0)) && ""Sym" LLVM,NVPTX,1573,"<std::string, std::string> &annotations) { return new NVVMReflectPass(annotations); }" LLVM,NVPTX,1574,AU . setPreservesAll ( true ) LLVM,NVPTX,1575,I != E; ++I LLVM,NVPTX,1576,return Res; LLVM,NVPTX,1577,"SmallVector < StringRef , > NameValPair ; NameValList [ j ] . split ( NameValPair , ) ; assert ( NameValPair . size ( ) == && ) ; std :: stringstream ValStream ( NameValPair [ addOperand(oper) LLVM,NVPTX,1580,otherOperands.push_back(copy->getOperand(i)); LLVM,NVPTX,1581,e ; ++ i ) copy -> addOperand ( otherOperands [ i ] ) ; } LLVM,NVPTX,1582,"void VectorElementize :: createVecBuild ( MachineFunction & F , MachineInstr * Instr , std :: vector < MachineInstr * > & copies ) { unsigned numcopies = numCopiesNeeded ( Instr ) ; unsigned destregnum = Instr -> getOperand ( ) . getReg () ; for ( unsigned i = 0 ; i < numcopies ; i++ ) { copies.push_back ( F.createInstr ( Instr ) ) ; } for ( unsigned i = 0" LLVM,NVPTX,1583,"copies . push_back ( F . CloneMachineInstr ( Instr ) ) ; MachineInstrBuilder copy ( F , copies [ ] ) ; copy -> setDesc ( InstrInfo -> get ( getScalarVersion ( copy ) ) ) ; MachineOperand dest = copy -> getOperand ( ) ; unsigned regnum = dest . getReg ( ) ; SmallVector < unsigned , > scalarRegs = getScalarRegisters ( regnum ) ;" LLVM,NVPTX,1584, LLVM,NVPTX,1585,copies.push_back(copy); LLVM,NVPTX,1586,for (unsigned i = 0; i < numcopies; ++i) { LLVM,NVPTX,1587,MachineOperand dest = copy->getOperand(0); LLVM,NVPTX,1588,"void VectorElementize::createStoreCopy(MachineFunction& F, MachineInstr* Instr, std::vector& copies) { copies.push_back(F.CloneMachineInstr(Instr)); MachineInstr* copy = copies[copies.size() - 1]; copy->setDesc(InstrInfo->get(getScalarVersion(copy))); MachineOperand src = copy->getOperand(0); unsigned regnum = src.getReg(); SmallVector scalarRegs =" LLVM,NVPTX,1589,i ] ) ; copy -> addOperand ( Instr -> getOperand ( [ i + 1 ] ) ) ; copy -> addOperand ( Instr -> getOperand ( [ i + 2 ] ) ) ; copy -> addOperand ( Instr -> getOperand ( [ i + 3 ] ) ) ; copy -> addOperand ( Instr -> getOperand ( [ i + 4 ] ) ) ; copy -> addOperand ( Instr -> getOperand ( [ i + 5 ] ) ) ; copy -> addOperand ( Instr -> getOperand ( LLVM,NVPTX,1590,"void VectorElementize::createVecDest(MachineFunction& F, MachineInstr* Instr, std::vector& copies) { copies.push_back(F.CloneMachineInstr(Instr)); MachineInstr* copy = copies[copies.size() - 1]; copy->setDesc(InstrInfo->get(getScalarVersion(copy))); MachineOperand dest = copy->getOperand(0); unsigned regnum = dest.getReg(); SmallVector" LLVM,NVPTX,1591,"copy->addOperand(MachineOperand::CreateReg(scalarRegs[i], true));" LLVM,NVPTX,1592,copies.push_back(copy[which.getImm()]); LLVM,NVPTX,1593,copy ) ; } } LLVM,NVPTX,1594,"DebugLoc DL = Instr -> getDebugLoc ( ) ; for ( unsigned i = ; i < numcopies ; i ++ ) { MachineInstr * copy = BuildMI ( F , DL , InstrInfo -> get ( getScalarVersion ( Instr ) ) , dest [ i ] ) ; if ( i != elem ) copy -> addOperand ( MachineOperand :: CreateReg ( src [ i ] , false ) ) ; else copy -> addOperand ( Instr -> getOperand [ i" LLVM,NVPTX,1595, LLVM,NVPTX,1596, LLVM,NVPTX,1597,return new VectorElementizePass(tm); LLVM,NVPTX,1598, LLVM,NVPTX,1599,"virtual const char * getPassName () const override { return ""My Pass Name""; }" LLVM,NVPTX,1600,return VectorToScalarMap[regnum]; LLVM,NVPTX,1601,unsigned TSFlags = (mi->getDesc().TSFlags); LLVM,NVPTX,1602,if ( ( mi -> getOpcode ( ) == ) || ( mi -> getOpcode ( ) == ) ) ) ) ) LLVM,NVPTX,1603, LLVM,NVPTX,1604,return isVectorRegClass(RC); LLVM,NVPTX,1605,bool VectorElementize::isVectorRegister(unsigned reg) { LLVM,NVPTX,1606,) ) ; return getVectorSize ( MRI -> getRegClass ( Instr -> getOperand ( ) . getReg ( ) ) ) ; } else { assert ( ISVECSTORE ( Instr [/INST] ) ) ; return getVectorSize ( MRI -> getRegClass ( Instr -> getOperand ( ) . getReg ( ) ) ) ; } } LLVM,NVPTX,1607,if (!oper.isDef()) continue; LLVM,NVPTX,1608, LLVM,RISCV,0,return (Val & ~ ); LLVM,RISCV,1,static inline bool isImmHL ( uint64_t imm) { return (imm & 0xFF00000000000000) == 0; } Here's how the function works: LLVM,RISCV,2,static inline bool isImmHL ( uint64_t Val ) { return ( Val & ~ 0xFFF ) == 0; } Explanation: LLVM,RISCV,3,return ( Val & ~0xFF ) == 0; LLVM,RISCV,4,"""fixupNeedsRelaxation() called on an unknown fixup kind!"" ); Here's a possible completion: bool fixupNeedsRelaxation ( const MCFixup & Fixup , uint64_t Value , const MCRelaxableFragment * DF , const MCAsm" LLVM,RISCV,5,MCAsmLayout & Layout ) { if (Fixup.getKind() == MCFixupKind_reloc_branch_thumb) { uint64_t CurSize = DF->getContents().size(); uint64_t Offset = Fixup.getOffset(); if (Offset == Cur LLVM,RISCV,6,bool requiresDiffExpressionRelocations() const override { LLVM,RISCV,7, LLVM,RISCV,8,"ForceRelocs = [ { ""name"": ""ForceReloc1"", ""type"": ""ForceReloc"", ""parameters"": { ""force"": 1000, ""relocation"": 0.5 } }, { ""name"": ""ForceReloc2"", ""type"": ""ForceReloc"", ""parameters"": { ""force"": 500, ""relocation"": 0.25 } } ];" LLVM,RISCV,9, LLVM,RISCV,10,") , ) ; if ( Value & ) Ctx . reportError ( Fixup . getLoc ( ) , ) ; unsigned Sbit = ( Value >> ) & ; unsigned Hi8 = ( Value >> ) & ; unsigned Mid1 = ( Value >> ) & ; unsigned Lo10 = ( Value >> ) & ELFObjectWriter ( OS ," LLVM,RISCV,13, LLVM,RISCV,14, LLVM,RISCV,15,bool mayNeedRelaxation ( const MCInst & Inst ) { LLVM,RISCV,16,"void relaxInstruction ( const MCInst & Inst , const MCSubtargetInfo & STI , MCInst & Res ) const override {" LLVM,RISCV,17, LLVM,RISCV,18,return false; LLVM,RISCV,19,llvm_unreachable(); case FK_Data_1: case FK_Data_2: case FK_Data_4: case FK_Data_8: return Value; case : case : return Value & LLVM,RISCV,20,"unsigned NumBytes = alignTo ( Info . TargetSize + Info . TargetOffset , 8 ) ;" LLVM,RISCV,21,function getTargetABI(arr) { LLVM,RISCV,22,const MCTargetOptions & getTargetOptions() const; LLVM,RISCV,23,const MCTargetOptions & getTargetOptions ( ) { return TargetOptions; } LLVM,RISCV,24,return getRelaxedOpcode(Inst.getOpcode()); LLVM,RISCV,25,public boolean willForceRelocations() { LLVM,RISCV,26,MCAsmBackend ( ) LLVM,RISCV,27,ARMTargetParser::FeatureBitForceRelocs); LLVM,RISCV,28,bool willForceRelocations ( ) const { return ForceRelocs || STI . getFeatureBits ( ) [ ] ; } LLVM,RISCV,29,"array_lengthof ( Infos ) ) && ""Invalid kind!""); The" LLVM,RISCV,30,const static MCFixupKindInfo Infos[] = { LLVM,RISCV,31,return Value; LLVM,RISCV,32,uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TT.getOS()); LLVM,RISCV,33,"return new AsmBackend(T, STI, MRI, Options);" LLVM,RISCV,34,Value = Layout . getSymbolOffset ( SA ) + AUIPCTarget . getConstant ( ) ; LLVM,RISCV,35, LLVM,RISCV,36, LLVM,RISCV,37,Fixup ) ) ) ) ; } ; LLVM,RISCV,38,"STR_LIT> } ) ; } else { llvm_unreachable ( ""Invalid encoding"" ) ; } return false ; }" LLVM,RISCV,39,Inst = std::move(Res); LLVM,RISCV,40,Res . addOperand ( Inst . getOperand ( ) ) ; break ; LLVM,RISCV,41, LLVM,RISCV,42,"Ctx , 0 , Ctx . getTarget ( ) ) ; return true ; }" LLVM,RISCV,43, LLVM,RISCV,44,"return writeNopData(OS, Count, HasStdExtC, MinNopLen);" LLVM,RISCV,45, LLVM,RISCV,46, LLVM,RISCV,47,"case : const MCFixup * T = cast < MCExpr > ( Fixup . getValue ( ) ) -> getPCRelHiFixup ( ) ; if ( ! T ) { Asm . getContext ( ) . reportError ( Fixup . getLoc ( ) , ) ; return false ; } switch ( ( unsigned ) T -> getKind ( ) ) { default : llvm_unreachable ( )" LLVM,RISCV,48,return true; LLVM,RISCV,49,"Fixup, FixedValue, NopBytes );" LLVM,RISCV,50,"uint64_t Value , bool IsPCRel )" LLVM,RISCV,51,{ return NumFixupKinds; } LLVM,RISCV,52,"""Invalid instruction"" ); } The" LLVM,RISCV,53,"bool shouldForceRelocation ( const MCAssembler & Asm , const MCFixup & Fixup ) {" LLVM,RISCV,54, LLVM,RISCV,55,const static MCFixupKindInfo Infos[] = { LLVM,RISCV,56, LLVM,RISCV,57, LLVM,RISCV,58, LLVM,RISCV,59,return Value; LLVM,RISCV,60, LLVM,RISCV,61,case FK_Data_8 : LLVM,RISCV,62,return STI.getFeatureBits(); LLVM,RISCV,63,(8 * (i - 1)) ) & 0xFF ) ; } LLVM,RISCV,64,Value <<= Info . getAdjustmentBits(); LLVM,RISCV,65,"return createELFObjectWriter ( OS ," LLVM,RISCV,66,"Asm.applyFixup(Fixup, Target, Data);" LLVM,RISCV,67, LLVM,RISCV,68,assert(Offset + NumBytes <= Data.size() && ); LLVM,RISCV,69,"return new AsmBackend(OSABI, TT.isArch64Bit());" LLVM,RISCV,70,if (Kind < FirstTargetFixupKind) LLVM,RISCV,71,If LLVM,RISCV,72,) & ; LLVM,RISCV,73,default : llvm_unreachable ( ) ; LLVM,RISCV,74,Optional < MCFixupKind > AsmBackend :: getFixupKind ( StringRef Name ) const { if ( STI . getTargetTriple ( ) . isOSBinFormatELF ( ) ) { return Optional < MCFixupKind > ( MCFixupKind ( Name ) ); } else { return Optional < MCFixupKind > ( ); } } LLVM,RISCV,75,"{ , , , MCFixupKindInfo :: FKF_IsPCRel }" LLVM,RISCV,76,FirstTargetFixupKind ] ; } LLVM,RISCV,77,return false; LLVM,RISCV,78,case : return Offset > || Offset < - ; LLVM,RISCV,79, LLVM,RISCV,80,"uint64_t Value , bool IsPCRel )" LLVM,RISCV,81,Size = MinNopLen; LLVM,RISCV,82, LLVM,RISCV,83,"return Asm.getWriter().recordRelocation(Asm, Layout, &AF, Fixup, NopBytes, FixedValue);" LLVM,RISCV,84,return Infos [Kind - FirstTargetFixupKind]; LLVM,RISCV,85,unsigned Lo4 = (Value >> 4) & 0xF; LLVM,RISCV,86,"void AsmBackend::applyFixup(const MCAssembler &Asm, const MCFixup &Fixup, const MCValue &Target, MutableArrayRef Data, uint64_t Value, uint64_t FixupOffset) { }" LLVM,RISCV,87, LLVM,RISCV,88,"return createELFObjectWriter(OSABI, Is64Bit);" LLVM,RISCV,89,"const Triple & TT = STI . getTargetTriple ( ) ; uint8_t OSABI = MCELFObjectTargetWriter :: getOSABI ( TT . getOS ( ) ) ; return new AsmBackend ( STI , OSABI , TT );" LLVM,RISCV,90,const Triple & TT = STI.getTargetTriple(); LLVM,RISCV,91, LLVM,RISCV,92,unsigned AsmBackend :: getRelaxedOpcode ( unsigned Op ) const { switch ( Op ) { default : return Op ; case : return ; case : return ; case : return ; } } LLVM,RISCV,93,STI ) const { if (Inst.getOpcode() == X86::CALL32r || Inst.getOpcode() == X86::CALL64r || Inst.getOpcode() == X86::BRAnys || Inst.getOpcode() == X86::BRLr) { return true; } if (Inst LLVM,RISCV,94,llvm_unreachable ( ) ; case : Res . setOpcode ( ) ; Res . addOperand ( Inst . getOperand ( ) ) ; Res . addOperand ( MCOperand :: createReg ( ) ) ; Res . addOperand ( Inst . getOperand ( ) ) ; break ; case : Res . setOpcode ( ) ; LLVM,RISCV,95,"case : const MCFixup *T = cast(Fixup.getValue())->getPCRelHiFixup(); if (!T) { Asm.getContext().reportError(Fixup.getLoc(), );" LLVM,RISCV,96,MinNopLen; LLVM,RISCV,97,if ( Expr == ) Inst . addOperand ( MCOperand :: createImm ( ) ) ; else if ( const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( Expr ) ) Inst . addOperand ( MCOperand :: createImm ( CE -> getValue ( ) ) ) ; else Inst . addOperand ( MCOperand :: createExpr ( Expr ) ) ; LLVM,RISCV,98,createImm ( CE->getValue () ) ) ; else if ( const MCBinaryExpr * BE = dyn_cast < MCBinaryExpr > ( Expr ) ) { switch ( BE->getOpcode () ) { case MCBinaryExpr :: Add: Inst . addOperand ( MCOperand :: createReg ( BE->getLHS () ) ) ; Inst . addOperand ( MCOperand :: createReg ( BE->getRHS () ) ) ; break ; case MCBinaryExpr :: And: Inst . addOperand ( MCOperand :: LLVM,RISCV,99,"void addImmOperands ( MCInst & Inst , unsigned N ) const { assert ( N == && ) ; addExpr ( Inst , getImm ( ) [0] ) ; }" LLVM,RISCV,100,"Inst . addOperand ( MCOperand :: createReg ( getReg ( ) , 0 ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) )" LLVM,RISCV,101,assert ( N == && ) ; Inst . addOperand ( MCOperand :: createReg ( getReg ( ) ) ) ; LLVM,RISCV,102, LLVM,RISCV,103, LLVM,RISCV,104,Op -> Mem . Disp = Disp ; LLVM,RISCV,105,"static std::unique_ptr createReg(RegisterKind Kind, unsigned Num, SMLoc StartLoc, SMLoc EndLoc) { auto Op = make_unique(KindReg, StartLoc, EndLoc); Op->Reg.Kind = Kind; Op->Reg.Num = Num; return Op; }" LLVM,RISCV,106,"SMLoc EndLoc ) { switch (Kind) { case RegisterKind::GPR: return std::make_unique(Num, StartLoc, EndLoc); case RegisterKind::FPR: return std::make_unique(Num, StartLoc, EndLoc); default: llvm_unreachable(""Invalid register kind""); } }" LLVM,RISCV,107,Op->Token.Data = Str.data(); LLVM,RISCV,108,unsigned getReg() const override { LLVM,RISCV,109,assert ( Kind == KindReg && (GetRegKind(Reg) == Kind)); LLVM,RISCV,110,from ER64Reg import isReg LLVM,RISCV,111,return isReg(FP128Reg) && (FP128Reg[0] & 0xF000) == 0xF0 LLVM,RISCV,112, LLVM,RISCV,113, LLVM,RISCV,114, LLVM,RISCV,115,return isReg(x) && isReg(y) && isReg(z); Explanation: LLVM,RISCV,116,"bool isGR32 (int x, int y) {" LLVM,RISCV,117,function isReg(reg) { LLVM,RISCV,118,"return Kind == KindImm && inRange ( Imm, 0, 15 ); Explanation:" LLVM,RISCV,119,"bool isValid ( Kind kind, int imm, int reg, int minValue, int maxValue, int minReg, int maxReg ) {" LLVM,RISCV,120,"bool isMem ( RegisterKind RegKind , bool HasIndex ) {" LLVM,RISCV,121,"return isMem(RegKind, HasIndex) && inRange(RegKind, HasIndex, MemLoc);" LLVM,RISCV,122,"return isMem(RegKind, HasIndex) && inRange(Mem.Disp, , [/INST] return isMem(RegKind, HasIndex) && inRange(Mem.Disp, , Mem.Scale); Explanation:" LLVM,RISCV,123,"bool isMemDisp20 (RegisterKind RegKind, RegisterNumber RegNum, Int64 MemDisp)" LLVM,RISCV,124,bool isPairFP128 ( ) const { return isReg ( 0x0C ); } Explanation: LLVM,RISCV,125,bool isPairFP64 ( ) const { return isReg ( PairFP64Reg ); } LLVM,RISCV,126,return isReg(PairFP64Reg); LLVM,RISCV,127,return isReg(PairGR128Reg) && (PairGR128Reg.getType() == RegType.PairGR128); LLVM,RISCV,128, LLVM,RISCV,129,return isReg(x) && isReg(y) && isReg(z); Explanation: LLVM,RISCV,130,"bool isPairGR64 (int a, int b) {" LLVM,RISCV,131,bool isPCReg (int reg) { LLVM,RISCV,132,bool isPCRReg ( ) { LLVM,RISCV,133,bool isReg (RegisterKind RegKind) { LLVM,RISCV,134,bool isS12Imm ( ) { LLVM,RISCV,135, LLVM,RISCV,136, LLVM,RISCV,137,"return isImm( - ( << ) , ( << ) ) )" LLVM,RISCV,138,"return isImm(-(1 << 2), (1 << 2) - 1);" LLVM,RISCV,139,if (isS64Imm(0x LLVM,RISCV,140,bool isToken ( ) const override { return Kind == TokenKind::Token; } LLVM,RISCV,141, LLVM,RISCV,142,return isImm ( ) LLVM,RISCV,143,"return isImm(123, (123 << 2));" LLVM,RISCV,144,"bool isU32Imm ( ) const { return isImm ( 32, ( 1 << 32 ) ); }" LLVM,RISCV,145,bool isU4Imm ( ) const { return isImm ( 4 ); } LLVM,RISCV,146,RegisterMCAsmParser < AsmParser > Y; LLVM,RISCV,147,"For example, if you want to display the error message ""Invalid operand"", you could complete the last statement of" LLVM,RISCV,148,"SMLoc ErrorLoc = IDLoc; return Error(IDLoc, Msg);" LLVM,RISCV,149,OperandMatchResultTy parseFP32 ( OperandVector &Operands) { if (Operands.size() != 1 || !Operands[0].isFP32()) { return OperandMatchResultTy::NoMatch; } float Value = Operands[0].getFP32(); if (!std::isfinite( LLVM,RISCV,150,"return parseRegister(Operands, 'x', GR64Regs, ISA_LIT);" LLVM,RISCV,151,OperandMatchResultTy parseGR64 ( OperandVector &operands) { OperandMatchResultTy result; result.matched = false; result.operand = NULL; if (operands.size() == 0) { return result; } Operand *op = operands[0]; if (op->type != Operand::REGISTER) { return result; } Register reg = op->reg; if (reg.type != Register::GPR LLVM,RISCV,152, ) ; LLVM,RISCV,153,return Expr; LLVM,RISCV,154,OperandMatchResultTy parsePairFP128(OperandVector &Operands) { LLVM,RISCV,155,"OperandMatchResultTy parsePairFP64(OperandVector &ops, unsigned opcode) { if (ops.size() != 2) return OperandMatchResult::NoMatch; if (!ops[0].isReg() || !ops[1].isReg()) return OperandMatchResult::NoMatch; if (ops[0].getType() != ops[" LLVM,RISCV,156,"OperandMatchResultTy parsePairFP64 ( OperandVector &Operands, unsigned Idx) { OperandMatchResultTy Res = parsePair(Operands, Idx); if (Res.hasValue()) { auto &Pair = Res.getValue(); if (Pair.first->getType() != Type::getDoubleTy(Context) || Pair.second->getType() != Type::getDoubleTy(Context)) { return OperandMatchResultTy::getError(""Expected a pair of double values""); }" LLVM,RISCV,157,"return parseRegister(Operands, 'x', PairGR128Regs[0]);" LLVM,RISCV,158,OperandMatchResultTy parsePairGR128 ( OperandVector &operands) { OperandMatchResultTy result; result.matched = false; if (operands.size() != 2) { return result; } Operand &op1 = operands[0]; Operand &op2 = operands[1]; if (op1.type != OperandType::Register || op2.type != OperandType::Register) { return result; } LLVM,RISCV,159,"return parseRegister ( Operands , 'x' , 0 );" LLVM,RISCV,160,"OperandMatchResultTy parsePairGR64 ( OperandVector &Operands, OperandMatchStateTy &State) { if (Operands.size() != 2) { return OperandMatchResultTy::NoMatch; } if (!Operands[0].isReg() || !Operands[1].isReg()) { return OperandMatchResultTy::NoMatch; }" LLVM,RISCV,161,"Parser . eatToEndOfStatement ( ) ; return Error ( Loc , ) ; } if ( Parser . getTok ( ) . isNot ( AsmToken :: RParen ) ) { SMLoc Loc = getLexer ( ) . getLoc ( ) ; Parser . eatToEndOfStatement ( ) ; return Error ( Loc , ) ; }" LLVM,RISCV,162,"return parseRegister(Operands, 'p', PCReg, Operand[0" LLVM,RISCV,163,"return parseRegister(Operands, 'p', PCReg, Instruction);" LLVM,RISCV,164,"if (Tok.getIdentifier().equals_lower(""PCR"")) {" LLVM,RISCV,165,StartLoc = Reg.StartLoc; LLVM,RISCV,166,void ISA_LIT::Operand::print(raw_ostream &OS) { } LLVM,RISCV,167,"AsmParser ( const MCSubtargetInfo & sti , MCAsmParser & parser , const MCInstrInfo & MII , const MCTargetOptions & Options ) : MCTargetAsmParser ( Options , sti ) , STI ( sti ) , Parser ( parser ) { MCAsmParserExtension :: Initialize ( MII ); }" LLVM,RISCV,168,"AsmParser ( const MCSubtargetInfo & sti , MCAsmParser & parser , const MCInstrInfo & MII , const MCTargetOptions & Options ) : MCTargetAsmParser ( Options , sti ) , STI ( sti ) , Parser ( parser ) { MCAsmParserExtension :: Initialize ( Parser ) ; setAvailableFeatures ( ComputeAvailableFeatures ( STI . getFeatureBits ( ) ) ) ; }" LLVM,RISCV,169,createImm (1) Inst . addOperand ( MCOperand :: createImm (1) ) LLVM,RISCV,170,"int64_t Imm = ; MCExpr :: VariantKind VK = MCExpr :: VK__None ; bool IsConstant = evaluateConstantImm ( Expr , Imm , VK );" LLVM,RISCV,171,case 'p' : Imm |= ; break ; } } Inst . addOperand ( MCOperand :: createExpr ( SE ) ) ; Inst . addOperand ( MCOperand :: createImm ( Imm ) ) ; return ; } LLVM,RISCV,172,Inst . addOperand ( MCOperand :: createImm ( 1234 ) ) ) ) ; LLVM,RISCV,173,"void addImmOperands ( MCInst & Inst , unsigned N ) const { assert ( N == );" LLVM,RISCV,174,assert ( N == && ) ; Inst . addOperand ( MCOperand :: createReg ( getReg ( N ) ) ) ; LLVM,RISCV,175,createReg ( N ) ) ; LLVM,RISCV,176,"assert ( N == && ) ; int64_t Imm = ; if ( Kind == KindTy :: Immediate ) { MCExpr :: VariantKind VK = MCExpr :: VK__None ; bool IsConstantImm = evaluateConstantImm ( getImm ( ) , Imm , VK ) ; ( void ) IsConstantImm ; assert ( IsConstantImm &&" LLVM,RISCV,177,Kind = MCExpr :: VK__None ; if ( const MCExpr * RE = dyn_cast < MCExpr * > ( Expr ) ) { Kind = RE->getKind ( ) ; return true ; } return false ; } LLVM,RISCV,178,if (getSTI().getFeatureBits()[Feature]) { LLVM,RISCV,179,Reg <= ); LLVM,RISCV,180,"static std::unique_ptr createReg(unsigned RegNo, SMLoc S, SMLoc E, bool IsRV64, bool IsGPRAsFPR = false) { auto Op = std::make_unique(KindTy::Register); Op->Reg.RegNum = RegNo; Op->Reg.IsRV64 = IsRV64; Op->Reg.IsGPRAsFPR = IsGPRAsFPR;" LLVM,RISCV,181,Op -> StartLoc = 0; LLVM,RISCV,182,Op -> StartLoc() LLVM,RISCV,183,E ; Op -> EndLoc = E ; LLVM,RISCV,184,S; LLVM,RISCV,185, LLVM,RISCV,186,"emitToStreamer(Out, MCInstBuilder().addOperand(TmpReg).addExpr(SymbolHi));" LLVM,RISCV,187,"emitToStreamer(Out, MCInstBuilder().addOperand(TmpReg).addExpr(SymbolHi));" LLVM,RISCV,188,VKHi = MCExpr :: VK_RISCV_HI; LLVM,RISCV,189, LLVM,RISCV,190,MCOperand DestReg = Inst.getOperand(); LLVM,RISCV,191,"VAR_LIT> , MCInst :: MayLoad , MCInst :: MayStore , MCInst :: MayStore | MCInst :: MayLoad , MCInst :: MayStore | MCInst :: MayLoad , MCInst :: MayStore | MCInst :: MayLoad , MCInst :: MayStore | MCInst :: MayLoad , MCInst :: MayStore | MCInst :: MayLoad , MCInst :: MayStore | MCInst :: MayLoad , MCInst :: MayStore | MCInst :: MayLoad , MCInst :: MayStore | MCInst :: MayLoad , MCInst :: MayStore | MCInst :: MayLoad ," LLVM,RISCV,192,"SecondOpcode , isRV64 ( ) ? : , MCExpr :: VK__TLS_GOT_LO , MCExpr :: VK__TLS_GOT_LO , MCExpr :: VK__TLS_GOT_LO , MCExpr :: VK__" LLVM,RISCV,193,"void AsmParser :: emitPseudoExtend ( MCInst & Inst , bool SignExtend , int64_t Width , SMLoc IDLoc , MCStreamer & Out ) { MCOperand DestReg = Inst . getOperand ( 0 ) ; MCOperand SourceReg = Inst . getOperand ( 1 ) ; unsigned SecondOpcode = SignExtend ? : ; int64_t ShAmt = ( isRV64 ( ) ? AsmParser :: emitPseudoExtend ( MCInst & Inst , bool SignExtend , int64_t Width , SMLoc IDLoc , MCStreamer & Out ) { MCOperand DestReg = Inst . getOperand ( ) ; MCOperand SourceReg = Inst . getOperand ( ) ; unsigned SecondOpcode = SignExtend ? : ; Out . emitInstruction ( Inst , IDLoc )" LLVM,RISCV,195,MCInst CInst; LLVM,RISCV,196,"} else { assert ( Inst . getNumOperands ( ) == ) ; emitToStreamer ( Out , MCInstBuilder ( Opcode ) . addOperand ( Inst . getOperand ( ) ) . addOperand ( Inst . getOperand ( ) ) . addOperand ( Inst . getOperand ( ) ) ) ; }" LLVM,RISCV,197, LLVM,RISCV,198,Upper ) LLVM,RISCV,199,bool getFeatureBits ( uint64_t Feature ) { return getSTI ( ) . getFeatureBits ( ) [Feature]; } LLVM,RISCV,200,.getLoc ( ); LLVM,RISCV,201,SMLoc getLoc ( ) const { return getParser ( ) . getTok ( ) . getLoc ( ); } LLVM,RISCV,202,Here are a few possibilities: LLVM,RISCV,203,assert ( Kind == KindTy :: Register && ) ; return Reg . RegNum . id ( Reg . RegNum . id ( Reg . RegNum . id ( Reg . RegNum . id ( Reg . RegNum . id ( Reg . RegNum . id ( Reg . RegNum . id ( Reg . RegNum . id ( Reg . RegNum . id ( Reg . RegNum . id ( Reg . RegNum . id ( Reg . RegNum . id ( Reg . RegNum . id ( Reg . RegNum . id ( Reg . RegNum . id ( Reg . RegNum LLVM,RISCV,204,FRM = SE -> getSymbol ( ) . getName ( ) ; LLVM,RISCV,205,FRM = SE -> getSymbol ( ) . getName ( ) ; LLVM,RISCV,206,return StartLoc; LLVM,RISCV,207,"StringRef getSysReg ( ) const { assert ( Kind == KindTy :: SystemRegister && ) ; return StringRef ( SysReg . Data , SysReg . Size ) ; }" LLVM,RISCV,208,MCTargetStreamer & TS = * getParser ( ) . getStreamer ( ); LLVM,RISCV,209,unsigned getVType ( ) const { assert ( Kind == KindTy ); return Kind; } LLVM,RISCV,210, LLVM,RISCV,211,return IsValid && IsConstantImm; LLVM,RISCV,212, LLVM,RISCV,213, LLVM,RISCV,214,"VK = evaluateConstantImm(getImm(), Imm);" LLVM,RISCV,215,"return AsmParser::classifySymbolRef(getImm(), VK) && (VK == MCExpr::VK_None);" LLVM,RISCV,216,if ( ! isImm ( ) ) return false ; LLVM,RISCV,217,{ return (m_registers[0] == 0x00000000) && (m_registers[1] == 0x00000000) && (m_registers[2] == 0x00000000) && (m_registers[3] == 0x00000000) && (m_registers[4] == 0x00000000) && (m_registers[5] == 0x0 LLVM,RISCV,218,bool isCSRSystemRegister ( ) const { return isSystemRegister ( ) && (getRegisterNumber ( ) >= 16 && getRegisterNumber ( ) <= 31); } Explanation: LLVM,RISCV,219,char Prev = '\0' ; for ( char c : Str ) { if ( c != 'i' && c != 'o' && c != 'r' && c != 'w' ) return false ; if ( c <= Prev ) return false ; Prev = c ; } return true ; LLVM,RISCV,220, LLVM,RISCV,221,return Str; LLVM,RISCV,222,if (!SVal || SVal->getKind() != MCExpr::Expr_SymbolRef) LLVM,RISCV,223, LLVM,RISCV,224,return Kind == KindTy::Register && MCRegisterClasses::; LLVM,RISCV,225, LLVM,RISCV,226,{ return m_isImm; } LLVM,RISCV,227,{ return m_isImm; } LLVM,RISCV,228,int64_t Imm; LLVM,RISCV,229, LLVM,RISCV,230,VK ); return IsConstantImm && Imm == 0; } LLVM,RISCV,231,"return AsmParser :: classifySymbolRef ( getImm ( ) , VK ) && VK == AsmParser :: VK__PseudoJump;" LLVM,RISCV,232,return VK == MCExpr::VK_PseudoJumpSymbol; LLVM,RISCV,233, LLVM,RISCV,234,"bool isReg (string str) { return regex_match(str, regex(""^[a-zA-Z0-9_]+$"")); }" LLVM,RISCV,235,return IsConstantImm && Imm >= INT64_C ( ) && Imm <= INT64_C ( ); LLVM,RISCV,236,bool isRV64 (int x) { LLVM,RISCV,237,if (IsConstantImm) LLVM,RISCV,238,if ( !IsValid ) IsValid = AsmParser::classifySymbolRef(getImm()[0]); LLVM,RISCV,239, LLVM,RISCV,240, LLVM,RISCV,241,{ return (this->imm13 & 0x1) == 0; } LLVM,RISCV,242,bool isSImm21Lsb0JAL ( ) { LLVM,RISCV,243,return IsConstantImm && isInt < > ( Imm ) && VK; LLVM,RISCV,244, LLVM,RISCV,245, LLVM,RISCV,246,VK = VK_SImm5Plus1; LLVM,RISCV,247,if ( ! LLVM,RISCV,248, LLVM,RISCV,249,{ return (this->imm9 & 0x1) == 0; } LLVM,RISCV,250,bool isSystemRegister ( ) const { return Kind == KindTy::System; } LLVM,RISCV,251, LLVM,RISCV,252,"return IsConstantImm && isShiftedUInt < , > ( Imm ) && ( Imm != ) && VK == MCExpr ;" LLVM,RISCV,253,"For example, if you want to check whether the immediate value is a constant and whether it is a shifted unsigned integer with a maximum value of 32 bits, you could use the following" LLVM,RISCV,254,return IsConstantImm && isUInt < > ( Imm ) && VK == VK_UINT; LLVM,RISCV,255,return IsValid && ( VK == MCExpr :: VK__HI ); LLVM,RISCV,256, LLVM,RISCV,257,int64_t Imm; LLVM,RISCV,258,"ISA_LIT>MCExpr :: VK__None ; if ( ! isImm ( ) ) return false ; bool IsConstantImm = evaluateConstantImm ( getImm ( ) , VK ) ; return IsConstantImm ;" LLVM,RISCV,259,return IsConstantImm && isUInt < > ( Imm ) && VK; LLVM,RISCV,260,return (Imm & 0x01) == 0; LLVM,RISCV,261,return VK; LLVM,RISCV,262,VK_Imm; LLVM,RISCV,263,Here is the LLVM,RISCV,264,"Next, the code evaluates" LLVM,RISCV,265,bool isV0Reg ( ) const { return Kind == KindTy :: Register && Reg == 0; } LLVM,RISCV,266,return true; } LLVM,RISCV,267, LLVM,RISCV,268,"bool IsConstantImm = evaluateConstantImm(getImm(), Imm, VK);" LLVM,RISCV,269,MCExpr :: VariantKind VK = MCExpr :: VK__None ; if ( ! isImm ( ) ) return false ; bool IsConstantImm = evaluateConstantImm ( getImm ( ) ) ; LLVM,RISCV,270,RegisterMCAsmParser < AsmParser > X; LLVM,RISCV,271, LLVM,RISCV,272,RegNo = MatchRegisterName(Name); LLVM,RISCV,273,SMLoc E = SMLoc::getFromPointer(S.getPointer() + Identifier.size()); LLVM,RISCV,274, LLVM,RISCV,275,return MatchOperand_ParseFail; LLVM,RISCV,276, LLVM,RISCV,277,return parseDirectiveInsn(DirectiveID.getLoc()); LLVM,RISCV,278,"if ( IsIntegerValue ) getTargetStreamer ( ) . emitAttribute ( Tag , IntegerValue ) ; else if ( Tag != ) getTargetStreamer ( ) . emitTextAttribute ( Tag , StringValue ) ; else { StringRef Arch = StringValue ; for ( auto Feature : FeatureKV ) if ( llvm :: ( Feature . Key ) ) clearFeatureBits ( Feature . Value , Feature . Key ) ; auto ParseResult = ll" LLVM,RISCV,279, LLVM,RISCV,280,switch (token.type) { LLVM,RISCV,281, LLVM,RISCV,282,return false; LLVM,RISCV,283,if (getLexer().is(AsmToken::Identifier) && getLexer().peekTok().is(AsmToken::Comma)) { LLVM,RISCV,284,return MatchOperand_Success ; } LLVM,RISCV,285,"Error ( getLoc ( ) , ) ; return MatchOperand_ParseFail ; } getParser ( ) . Lex ( ) ; if ( getLexer ( ) . getKind ( ) != AsmToken :: LParen ) { Error ( getLoc ( ) , ) ; return MatchOperand_ParseFail ; } getParser ( ) . Lex ( ) ; const MCExpr * SubExpr ; if ( getParser ( ) . parseParenExpression ( SubExpr ) ) { Error ( get" LLVM,RISCV,286, LLVM,RISCV,287, LLVM,RISCV,288,return false; LLVM,RISCV,289,"case KindTy::Memory: OS << """" << MemName(getMem()) << """"; break; default: OS << """" << ""Unknown"" << """"; break; }" LLVM,RISCV,290,void pushFeatureBits ( ) { LLVM,RISCV,291,if ( ! ( getSTI ( ) . getFeatureBits ( ) [ FeatureBits.STI_FEATURE_BITS_MASK ] ) ) LLVM,RISCV,292,"OperandMatchResultTy AsmParser :: tryParseRegister ( unsigned & RegNo , SMLoc & StartLoc , SMLoc & EndLoc ) { const AsmToken & Tok = getParser(); if (Tok.isNot(AsmToken::Identifier)) { return OperandMatchResult::Failure; } if (Tok.getString() == ""r0"") { RegNo = 0; } else if (Tok.getString() == ""r1"") { RegNo = 1; } else if" LLVM,RISCV,293,if ( Op . Reg . RegNum == ) { LLVM,RISCV,294,"for ( & Inst : Seq ) { if ( Inst . Opc == ) { emitToStreamer ( Out , MCInstBuilder ( ) . addReg ( DestReg ) . addImm ( Inst . Imm ) . build () ); } } }" LLVM,RISCV,295,"void AsmParser::emitLoadStoreSymbol(MCInst &Inst, unsigned Opcode, SMLoc IDLoc, MCStreamer &Out, bool HasTmpReg) { MCOperand DestReg = Inst.getOperand(0); unsigned SymbolOpIdx = HasTmpReg ? 1 : 0; unsigned TmpRegOpIdx = HasTmpReg ? 2 : 1; MCOperand TmpReg = Inst.getOperand(TmpRegOpIdx); }" LLVM,RISCV,296, LLVM,RISCV,297,assert(Inst.getOperand().getReg() == && ); LLVM,RISCV,298,return MatchOperand_Success; LLVM,RISCV,299, LLVM,RISCV,300,( Imm ) ) ; } LLVM,RISCV,301,createImm (Imm) ); LLVM,RISCV,302,Imm ) ) ; } LLVM,RISCV,303,return; LLVM,RISCV,304,if (auto CE = dyn_cast(Val)) { LLVM,RISCV,305,MCExpr::VariantKind::VK_Constant) { Imm = RE->getImm(); Ret = true; } return Ret; } LLVM,RISCV,306,"return AsmParser :: classifySymbolRef ( getImm ( ) , VK , Imm ) && VK == MCExpr;" LLVM,RISCV,307,return false; LLVM,RISCV,308,return IsConstantImm && ( Imm != ) LLVM,RISCV,309,"bool IsConstantImm = evaluateConstantImm(Imm, VK);" LLVM,RISCV,310,"return IsConstantImm && ( Imm != ) && isShiftedInt < , > ( Imm ) && VK == [VK_CONSTANT_IMM];" LLVM,RISCV,311,bool isSImm21Lsb0 (int value) { LLVM,RISCV,312,bool isSImm21Lsb0 ( ) { LLVM,RISCV,313,"if ( ! IsConstantImm ) IsValid = AsmParser :: classifySymbolRef ( getImm ( ) , VK , Imm ) ; else IsValid = isInt < NUM_LIT > ( Imm ) ; return IsValid && ( VK == MCExpr :: VK_ > (Imm); LLVM,RISCV,317,int64_t Imm; LLVM,RISCV,318,if ( ! isImm ( ) ) return false ; LLVM,RISCV,319, LLVM,RISCV,320,"bool IsConstantImm = evaluateConstantImm(Imm, VK);" LLVM,RISCV,321,"Imm, VK, IsConstantImm );" LLVM,RISCV,322,return (isRV64() && isUInt<32>(Imm)) || ... LLVM,RISCV,323, LLVM,RISCV,324, LLVM,RISCV,325,( Res ) ) { return MatchOperand_Match; } else { return MatchOperand_ParseFail; } LLVM,RISCV,326,getParser().eatToEndOfStatement(); LLVM,RISCV,327, LLVM,RISCV,328,if (parseImmediate(Operands) == MatchOperand_Success) { LLVM,RISCV,329,switch (Kind) { LLVM,RISCV,330,case Immediate: Imm = o . Imm; break; LLVM,RISCV,331,"static bool shouldForceImediateOperand ( StringRef Name , unsigned OperandIdx ) { switch ( OperandIdx ) { case : return Name == || Name == ; case : return Name == ; } }" LLVM,RISCV,332,Here's a breakdown of the code: LLVM,RISCV,333,"emitToStreamer ( Out , MCInstBuilder ( SecondOpcode ) . addOperand ( DestReg ) . addOperand ( RefToLinkTmpLabel ) ) ;" LLVM,RISCV,334,"void AsmParser::emitLoadAddress(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out) { MCOperand DestReg = Inst.getOperand(0); const MCExpr *Symbol = Inst.getOperand(1).getExpr(); unsigned SecondOpcode; MCOperand::VariantKind VKHi; if (getContext().getObjectFileInfo()->isPositionIndependent()) { SecondOpcode = isRV64() ? : ; VK" LLVM,RISCV,335,"void AsmParser :: emitLoadAddress ( MCInst & Inst , SMLoc IDLoc , MCStreamer & Out ) { MCOperand DestReg = Inst . getOperand ( ) ; const MCExpr * Symbol = Inst . getOperand ( ) . getExpr ( ) ; unsigned SecondOpcode = Inst . getOpcode ( ) ;" LLVM,RISCV,336," Seq ; ( Value , isRV64 ( ) , Seq ) ; Register SrcReg = ; for ( & Inst : Seq ) { if ( Inst . Opc == ) { emitToStreamer ( Out , MCInstBuilder ( ) . addReg ( DestReg ) . addImm ( Inst . Imm ) ) ; } else { emitToStreamer (" LLVM,RISCV,337,SysReg.Length ); LLVM,RISCV,338,"IsValid = isShiftedInt, Imm, VK>" LLVM,RISCV,339,"return AsmParser::classifySymbolRef(getImm(), VK, Imm) && (VK == MCExpr::VK_ISA_LITERAL_CALL || VK == MCExpr::VK" LLVM,RISCV,340,Imm ) ) ) { VK = MCExpr::VK_ISA_LIT_Imm; } LLVM,RISCV,341,"For example, if the I" LLVM,RISCV,342,if ( !IsValid ) IsValid = AsmParser::classifySymbolRef(getImm()); LLVM,RISCV,343,int64_t Imm; MCExpr::VariantKind VK = MCExpr::VK__None; if (!isImm() || evaluateConstantImm(getImm())) { VK = MCExpr::VK__Imm; } LLVM,RISCV,344,Here is the completed LLVM,RISCV,345, LLVM,RISCV,346,return MatchOperand_ParseFail; LLVM,RISCV,347,"getLexer ( ) . UnLex ( LParen ) ; return MatchOperand_NoMatch ; } if ( HadParens ) Operands . push_back ( Operand :: createToken ( , FirstS , isRV64 ( ) ) ) ; SMLoc S = getLoc ( ) ; SMLoc E = SMLoc :: getFromPointer ( S . getPointer ( ) - ) ; getLexer ( ) . Lex ( ) ; Operands . push_back (" LLVM,RISCV,348,"case : emitLoadStoreSymbol ( Inst , , IDLoc , Out , true ) ; return false ;" LLVM,RISCV,349,StartLoc = o.StartLoc; LLVM,RISCV,350,StartLoc = o . StartLoc ; EndLoc = o . EndLoc ; switch ( Kind ) { LLVM,RISCV,351,StringRef Name = getLexer().get LLVM,RISCV,352,Operand & Op = static_cast < Operand & > ( AsmOp ) ; if ( ! Op . isReg ( ) ) return Match_InvalidOperand ; Register Reg = Op . getReg ( ) ; bool IsRegFPR64 = MCRegisterClasses [ ] . contains ( Reg ) ; bool IsRegFPR64C = MCRegisterClasses [ NumInstrsCompressed; S.EmitInstruction(CInst); } else { S.EmitInstruction(Inst); }" LLVM,RISCV,356,"return generateImmOutOfRangeError ( Operands , ErrorInfo , , ( << ) - , ) ; } case Match_InvalidFenceArg : { SMLoc ErrorLoc = ( ( Operand & ) * Operands [ ErrorInfo ] ) . getStartLoc ( ) ; return Error ( ErrorLoc , ""invalid fence argument"" ) ; } case Match_InvalidCSRSystemRegister :" LLVM,RISCV,357,return false; LLVM,RISCV,358, LLVM,RISCV,359,"bool isSImm12 ( ) const { MCExpr :: VariantKind VK ; int64_t Imm ; bool IsValid ; if ( ! isImm ( ) ) return false ; bool IsConstantImm = evaluateConstantImm ( getImm ( ) , Imm , VK ) ; if ( ! IsConstantImm ) IsValid = AsmParser :: classifySymbolRef ( getImm ( ) , IsValid ) ; return IsValid ; }" LLVM,RISCV,360,return IsValid && ( ( IsConstantImm && VK == MCExpr :: VK__None ) || VK == MCExpr :: VK__LO || VK == << ) - ) ; case Match_InvalidSImm9 : return generateImmOutOfRangeError ( Operands , ErrorInfo , - ( << ) , ( << ) - ) ; case Match_InvalidSImm10 : return generateImmOutOfRangeError ( Operands , ErrorInfo , - ( << ; LLVM,RISCV,366,return MatchOperand_NoMatch; LLVM,RISCV,367, LLVM,RISCV,368, LLVM,RISCV,369,"bool IsConstantImm = evaluateConstantImm(Imm, VK);" LLVM,RISCV,370,"return IsConstantImm && isShiftedInt < 16, 16 > ( Imm ) && VK == VK_Integer;" LLVM,RISCV,371, LLVM,RISCV,372,MCExpr::VK_ISA_None); LLVM,RISCV,373, LLVM,RISCV,374, LLVM,RISCV,375,"bool IsConstantImm = evaluateConstantImm(Imm, VK);" LLVM,RISCV,376,"MCExpr :: VariantKind VK ; bool IsConstantImm = evaluateConstantImm ( Imm , VK ) ;" LLVM,RISCV,377,"Imm , 9 , 0 , 0 , 0 ) ; }" LLVM,RISCV,378,``` LLVM,RISCV,379,"ErrorLoc = ( ( Operand & ) * Operands [ ErrorInfo ] ) . getStartLoc ( ) ; if ( ErrorLoc == SMLoc ( ) ) ErrorLoc = IDLoc ; } return Error ( ErrorLoc , ) ; } case Match_InvalidUImmLog2XLen : if ( isRV64 ( ) ) return generateImmOutOfRangeError ( Operands , ErrorInfo , , ( << ) - createReg(unsigned RegNo, SMLoc S, SMLoc E, bool IsRV64) {" LLVM,RISCV,388,Op->IsRV64 = IsRV64; LLVM,RISCV,389,"int numElements, unsigned int elementSize, unsigned int numLanes) { static std :: unique_ptr < Operand > createVType ( unsigned int numElements, unsigned int elementSize, unsigned int numLanes) { return std :: make_unique < Operand > (numElements, elementSize, numLanes); }" LLVM,RISCV,390,"emitToStreamer ( Out , MCInstBuilder ( Opcode ) . addOperand ( Inst . getOperand ( ) ) . addOperand ( Inst . getOperand ( ) ) . addOperand ( Inst . getOperand ( ) ) . addOperand ( Inst . getOperand ( ) ) ) ; } else if ( Inst . getNumOperands ( ) == && Inst . getOperand ( ) . get" LLVM,RISCV,391,"emitToStreamer ( Out , MCInstBuilder ( ) . addOperand ( Inst . getOperand ( ) ) . addOperand ( Inst . getOperand ( ) ) . addReg ( ) ) ;" LLVM,RISCV,392,"return isVType(value) && value.type === ""VNode"" && value.tag === ""div"";" LLVM,RISCV,393,std::unique_ptr OptionalImmOp; LLVM,RISCV,394,Res = Sym->getVariableValue(false); const MCExpr * Res = Sym->getVariableValue(false); LLVM,RISCV,395,return Res; LLVM,RISCV,396,case AsmToken::Identifier: LLVM,RISCV,397,return MatchOperand_ParseFail; LLVM,RISCV,398,"After that, the code is checking the kind of the current token using the `getKind` function" LLVM,RISCV,399, LLVM,RISCV,400,return MatchOperand_NoMatch; LLVM,RISCV,401,"Parser.addAliasForDirective(, ); setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits())); auto ABIName = StringRef(Options.ABIName); if (ABIName.endswith( EndLoc = E; LLVM,RISCV,403,Op -> StartLoc = Token.Start(); LLVM,RISCV,404,"if ( !IsConstantImm ) IsValid = AsmParser::classifySymbolRef(getImm(), VK, );" LLVM,RISCV,405,return IsValid && (VK == MCExpr::VK_ISA_LIT_None); LLVM,RISCV,406, LLVM,RISCV,407,VK__None || VK == MCExpr :: VK__Mem); LLVM,RISCV,408,return IsConstantImm && isUInt < > ( Imm ) && (Imm & (1 << (5 - 1))) == 0; LLVM,RISCV,409, LLVM,RISCV,410,return MatchOperand_ParseFail; LLVM,RISCV,411, LLVM,RISCV,412,getParser().Lex() LLVM,RISCV,413,"OperandMatchResultTy AsmParser :: parseMemOpBaseReg ( OperandVector & Operands ) { if ( getLexer ( ) . isNot ( AsmToken :: LParen ) ) { Error ( getLoc ( ) , ) ; return MatchOperand_ParseFail ; } getParser ( ) . Lex ( ) ; Operands . push_back ( Operand :: createToken ( , getLoc ( ) ) ) ; if ( parseRegister ( Operands )" LLVM,RISCV,414, LLVM,RISCV,415,return MatchOperand_ParseFail; LLVM,RISCV,416,return MatchOperand_Match; LLVM,RISCV,417,Operand ( const Operand & o ) : MCParsedAsmOperand ( ) { LLVM,RISCV,418,"case Match_InvalidUImm9Lsb000: return generateImmOutOfRangeError(Operands, ErrorInfo, , ( << ) - , );" LLVM,RISCV,419,return IsValid && ( ( IsConstantImm && VK == MCExpr :: VK__None ) || VK == MCExpr :: VK__LO ); LLVM,RISCV,420,return isSImm6 ( ) ; } LLVM,RISCV,421,"bool IsConstantImm = evaluateConstantImm(Imm, VK);" LLVM,RISCV,422,"if ( ! isImm ( ) ) return false ; bool IsConstantImm = evaluateConstantImm ( Imm , VK ) ; if ( ! IsConstantImm ) { IsValid = AsmParser :: classifySymbolRef ( getImm ( ) ) ; } }" LLVM,RISCV,423,VK__HI ; } LLVM,RISCV,424,return IsValid && VK == MCExpr::VK_LUI; LLVM,RISCV,425,"return Error ( Loc, ""unexpected token in argument list"" );" LLVM,RISCV,426,"generateImmOutOfRangeError ( Operands , ErrorInfo , - ( << ) , ( << ) - ) ;" LLVM,RISCV,427,"case Match_InvalidSImm12Lsb0 : return generateImmOutOfRangeError ( Operands , ErrorInfo , - ( << ) , ( << ) - , ) ;" LLVM,RISCV,428,"""expected end of statement"" );" LLVM,RISCV,429,"emitLoadImm(Reg, Imm);" LLVM,RISCV,430,"SrcReg ) . addImm ( Inst . Imm ) . finalize ( ) ) ; } else if ( Inst . Opc == ) { emitToStreamer ( Out , MCInstBuilder ( ) . addReg ( [/INST] SrcReg ) . addImm ( Inst . Imm ) . finalize ( ) ) ; } else { llvm_unreachable ( ""Invalid opcode"" ) ; } } }" LLVM,RISCV,431, LLVM,RISCV,432,return true; LLVM,RISCV,433,Inst . addOperand ( MCOperand :: createImm ( Imm + 1 ) ) ) ; } LLVM,RISCV,434,"MCExpr :: VariantKind VK = MCExpr :: VK__None ; bool IsConstant = evaluateConstantImm ( getImm ( ) , Imm , VK ) ; assert ( IsConstant && Imm.isConstant ( ) ) ;""" LLVM,RISCV,435,"if ( TargetFlags == ) return false ; unsigned DestReg = Inst . getOperand ( ) . getReg ( ) ; unsigned CheckReg ; SMLoc Loc = Operands [ ] -> getStartLoc ( ) ; if ( TargetFlags & ) { CheckReg = Inst . getOperand ( ) . getReg ( ) ; if ( DestReg == CheckReg ) return Error ( Loc , VType . Encoding = (SewLog2 << 2) | LmulLog2; LLVM,RISCV,438,if (TailAgnostic) { LLVM,RISCV,439,switch ( Lmul ) { LLVM,RISCV,440,switch (expression) { LLVM,RISCV,441,return Buf.str; LLVM,RISCV,442,return Buf.str; LLVM,RISCV,443,switch (Match) { LLVM,RISCV,444,return MatchOperand_Success; LLVM,RISCV,445,"if ( ! getLexer ( ) . is ( AsmToken :: Comma ) ) return MatchOperand_NoMatch ; getLexer ( ) . Lex ( ) ; Name = getLexer ( ) . getTok ( ) . getIdentifier ( ) ; bool TailAgnostic ; if ( Name . consume_front ( ) ) { TailAgnostic = true ; } APInt Lmul ( , Name , ) ; if ( Lmul != " LLVM,RISCV,446,Here LLVM,RISCV,447,return Match_Success; LLVM,RISCV,448,assert ( N == && ) ; Inst . addOperand ( MCOperand :: createImm ( ) ) ; LLVM,RISCV,449,assert ( N == && ) ; Inst . addOperand ( MCOperand :: createImm ( ) ) ; LLVM,RISCV,450,"const MCExpr * RefToLinkTmpLabel = MCExpr :: create ( MCSymbolRefExpr :: create ( TmpLabel , Ctx ) );" LLVM,RISCV,451,"const MCExpr * RefToLinkTmpLabel = MCExpr :: create ( MCSymbolRefExpr :: create ( TmpLabel , Ctx ) , MCExpr :: VK__PCREL_LO , Ctx ) ; emitToStreamer ( Out , MCInstBuilder ( SecondOpcode ) . addOperand ( DestReg ) . addOperand ( TmpReg ) . addExpr ( RefToLinkTmpLabel ) ) ;" LLVM,RISCV,452, LLVM,RISCV,453,"emitAuipccInstPair ( DestReg , DestReg , Symbol , MCExpr :: VK_PCREL_HI , ""auipcc"" ) ;" LLVM,RISCV,454,"void AsmParser :: emitCapLoadTLSIEAddress ( MCInst & Inst , SMLoc IDLoc , MCStreamer & Out ) { MCOperand DestReg = Inst . getOperand ( ) ; MCOperand TmpReg = Inst . getOperand ( ) ; Out . emitRRI6 ( , DestReg , TmpReg , IDLoc ) ; }" LLVM,RISCV,455,return getCheriCapabilitySize ( ) const override { assert ( isCheri ( ) ); } LLVM,RISCV,456,assert ( Kind == KindTy :: SpecialCapRegister || Kind == KindTy :: GeneralCapRegister ); LLVM,RISCV,457,"""SpecialCapRegister"" );" LLVM,RISCV,458,VK.isImm(); LLVM,RISCV,459,return getSTI().getFeatureBits(); LLVM,RISCV,460,return Kind == KindTy :: Register && MCRegisterClasses [ LLVM,RISCV,461,"return AsmParser :: classifySymbolRef ( getImm ( ) , VK ) && VK;" LLVM,RISCV,462,bool isTPRelCIncOffsetSymbol ( ) const { LLVM,RISCV,463,"Imm, VK, IsConstantImm);" LLVM,RISCV,464,if ( ! isImm ( ) ) return false ; LLVM,RISCV,465,int64_t Imm; LLVM,RISCV,466, LLVM,RISCV,467, LLVM,RISCV,468,E ) ) ) ; return MatchOperand_Success ; } LLVM,RISCV,469,getTargetStreamer().emitDirectiveOptionNoPIC(); LLVM,RISCV,470,return false; LLVM,RISCV,471,if (getParser().parseExpression(Res)) LLVM,RISCV,472,return MatchOperand_ParseFail; LLVM,RISCV,473,OS << << getSpecialCapReg ( ) << ; break ; case KindTy :: SpecialRegister : OS << << getSpecialReg ( ) << ; break ; case KindTy :: Memory : OS << << getMem ( ) << ; break ; case KindTy :: Label : OS << << getLabel ( ) << ; break ; case KindTy :: Constant : OS << << RegName ( getReg ( ) ) << << getAddr ( ) ; break ; default : llvm_unreachable ( ""Unknown kind!"" ) ; } }" LLVM,RISCV,475,"case : emitLoadStoreSymbol ( Inst , , IDLoc , Out , true ) ; return false ;" LLVM,RISCV,476,return IsValid && (VK == MCExpr::VK__PCREL_HI || VK == MCExpr::VK__GOT_HI); LLVM,RISCV,477,"IDLoc , Out ) ; return false ; }" LLVM,RISCV,478,Inst . addOperand ( MCOperand :: createReg ( getVecReg ( AsmPrinter . VT_128 ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) LLVM,RISCV,479,assert(N == && !.empty()); LLVM,RISCV,480,Inst . addOperand ( MCOperand :: createImm ( Vtypei . Encoding ) ) ) ; LLVM,RISCV,481, LLVM,RISCV,482, LLVM,RISCV,483,assert ( Kind == KindTy :: TYPES ); LLVM,RISCV,484,"assert ( Kind == KindTy :: VTypeImm && ) ; Twine vtypei ( getSEW ( Vtypei . Sew ) ) ; vtypei . concat ( Twine ( ""V"" ) ) ;" LLVM,RISCV,485,{ return false; } if (isVectorRegister()) { } else { } LLVM,RISCV,486, LLVM,RISCV,487,if ( parseImmediate ( Operands ) == MatchOperand_Success ) { LLVM,RISCV,488,"if ( HadParens ) Operands . push_back ( Operand :: createToken ( , FirstS , isRV64 ( ) ) ) ;" LLVM,RISCV,489,StringRef Name = getLexer().getTok().getIdentifier(); LLVM,RISCV,490,return MatchOperand_Match; LLVM,RISCV,491,getLexer().Lex(); LLVM,RISCV,492, LLVM,RISCV,493, LLVM,RISCV,494,E ; LLVM,RISCV,495,":: VK_Invalid ) { Error ( getLoc ( ) , ) ; return MatchOperand_ParseFail ; } Operands . push_back ( MCOperand :: createExpr ( MCExpr :: create ( VK , Identifier , getContext ( ) ) ) ) ; return MatchOperand_Success ; }" LLVM,RISCV,496,"Operands.push_back(Operand::createToken(, FirstS));" LLVM,RISCV,497,case : return ; case : return ; case : return ; case : return ; case : return ; case LLVM,RISCV,498,return IsConstantImm && IsInRange && VK == MCExpr :: VK__LO; LLVM,RISCV,499,"static bool matchRegisterNameHelper ( bool IsRV32E , Register & RegNo , StringRef Name ) { RegNo = MatchRegisterName ( IsRV32E , Name ); }" LLVM,RISCV,500,contains ( Reg ) ; bool IsRegFPR32C = MCRegisterClasses [ ] . contains ( Reg ) ; bool IsRegFPR32C = MCRegisterClasses [ ] . contains ( Reg ) ; bool IsRegFPR32C = MCRegisterClasses [ ] . contains ( Reg ) ; bool IsRegFPR32C = MCRegisterClasses [ ); LLVM,RISCV,502,Res = VType.Encoding = ( (Flmul & ) << ) | ( (SewLog2 & ) << ); LLVM,RISCV,510,default: LLVM,RISCV,511,if ( ! isImm ( ) ) return false ; LLVM,RISCV,512,MCExpr :: VariantKind VK = MCExpr :: VK__None ; if ( ! isImm ( ) ) { LLVM,RISCV,513,return IsValid && VK == MCExpr :: VK__None; LLVM,RISCV,514,Imm ) ) return false ; if ( Imm < 0 ) return false ; if ( Imm >= 64 ) return false ; return true ; } LLVM,RISCV,515,return IsValid && IsConstantImm; LLVM,RISCV,516, LLVM,RISCV,517, LLVM,RISCV,518, LLVM,RISCV,519,return isImm ( ) LLVM,RISCV,520,return isU32Imm(value); LLVM,RISCV,521,``` LLVM,RISCV,522, LLVM,RISCV,523,return IsConstantImm && ( Imm == ); LLVM,RISCV,524,return IsConstantImm && isInt < > ( Imm ) && isInt < > ( Imm ) == 0; LLVM,RISCV,525,return VK; LLVM,RISCV,526,bool isUImm8 ( ) const { int64_t Imm ; MCExpr :: VariantKind VK ; if ( ! isImm ( Imm ) ) return false ; if ( Imm < 0 ) return false ; if ( Imm > 255 ) return false ; return true ; } LLVM,RISCV,527,"static std::unique_ptr createVType(APInt Sew, APInt Lmul, SMLoc S, bool IsRV64) { auto Op = std::make_unique(KindTy::VType); Sew.ashrInPlace(Lmul.getBitWidth() - 1); Op->setSew(Sew); Op->setLmul(Lmul); Op->setS(S); Op->setIsRV64(Is" LLVM,RISCV,528,default: return ; LLVM,RISCV,529, LLVM,RISCV,530,case : return ; LLVM,RISCV,531,return MatchOperand_Success; LLVM,RISCV,532,") > ) { unsigned Src3Reg = Inst . getOperand ( ) . getReg ( ) ; if ( DestReg == Src3Reg ) return Error ( Loc , ) ; if ( TargetFlags == ) { if ( DestReg + == Src3Reg ) return Error ( Loc , ) ; } } } return true ; }" LLVM,RISCV,533,"Error ( Loc , ) ; } }" LLVM,RISCV,534,return IsConstantImm && isUInt < > ( Imm ); LLVM,RISCV,535, LLVM,RISCV,536,if (parseImmediate(Operands)) LLVM,RISCV,537,case 'w': LLVM,RISCV,538,default : llvm_unreachable ( ) ; case 'i' : Imm |= ; break ; case 'o' : Imm |= ; break ; case 'r' : Imm |= ; break ; case 'w' : Imm |= ; break LLVM,RISCV,539,"static std::unique_ptr createImm(const MCExpr* Val, SMLoc S, SMLoc E, bool IsRV64) { auto Op = make_unique(Val, S, E, IsRV64); return Op; }" LLVM,RISCV,540, LLVM,RISCV,541,return Op; LLVM,RISCV,542,return Op; LLVM,RISCV,543,"S.EmitInstruction((Res ? CInst : Inst), S.getContext());" LLVM,RISCV,544,assert ( Kind == Immediate || Kind == Deferred ); LLVM,RISCV,545,assert (Kind == SystemRegister.Kind); LLVM,RISCV,546,return Token; LLVM,RISCV,547,"If `IsConstantImm` is false, then the `IsValid`" LLVM,RISCV,548,return true; LLVM,RISCV,549,{ return (this->age < 18); } LLVM,RISCV,550,return 42; LLVM,RISCV,551,{ return true; } LLVM,RISCV,552,ISA_LIT>MCExpr :: VariantKind VK ; int64_t Imm ; bool IsValid ; if ( ! isImm ( ) ) return false ; bool IsConstantImm = evaluateConstantImm ( getImm ( ) ) ; if ( ! IsConstantImm ) return false ; return true ; } LLVM,RISCV,553,return IsConstantImm && isInt < > ( Imm ) && VK; LLVM,RISCV,554,public enum RegisterType { LLVM,RISCV,555,{ return (m_type == SystemRegister); } LLVM,RISCV,556,bool isToken ( ) const override { return Kind == TokenKind::Token; } LLVM,RISCV,557,return IsConstantImm && isShiftedUInt LLVM,RISCV,558,return true; LLVM,RISCV,559,"if ( ! isImm ( ) ) return false ; bool IsConstantImm = evaluateConstantImm ( getImm ( ) , Imm , VK ) ; if ( ! IsConstantImm ) { IsValid = AsmParser :: classifySymbolRef ( getImm ( ) , VK , IsValid ) ; }" LLVM,RISCV,560,return IsValid && VK == MCExpr::VK_LUI; LLVM,RISCV,561,return IsConstantImm && isUInt < > ( Imm ) && (Imm < ); LLVM,RISCV,562,return IsConstantImm && isUInt < > ( Imm ); LLVM,RISCV,563,return IsConstantImm && isUInt < > ( Imm ) && (Imm < ); LLVM,RISCV,564,return Imm != 0; LLVM,RISCV,565,"return IsConstantImm && isShiftedUInt < 10, 20 > (" LLVM,RISCV,566,"return IsConstantImm && isShiftedUInt < , > ( Imm ) && VK;" LLVM,RISCV,567,if ( ! isImm ( ) ) return false ; LLVM,RISCV,568,RegisterMCAsmParser < AsmParser > X ( getThe32Target ( ) ) ; LLVM,RISCV,569,RegisterMCAsmParser < AsmParser > Y ( getThe64Target (Target)); LLVM,RISCV,570,return MatchOperand_ParseSuccess; LLVM,RISCV,571,bool AsmParser::ParseDirective(AsmToken Directive LLVM,RISCV,572," is a placeholder for a string literal, so the complete statement would be: StringRef IDVal = DirectiveID.getString(); if (IDVal == ""my_directive"") return parseDirectiveOption;" LLVM,RISCV,573,return false; LLVM,RISCV,574,"Operands.push_back(Operand::createToken(Name, NameLoc, isRV64()));" LLVM,RISCV,575,"} getParser ( ) . Lex ( ) ; if ( getLexer ( ) . getKind ( ) != AsmToken :: LParen ) { Error ( getLoc ( ) , ) ; return MatchOperand_ParseFail ; } getParser ( ) . Lex ( ) ; const MCExpr * SubExpr ; if" LLVM,RISCV,576,) ) ) ; return MatchOperand_Success ; } LLVM,RISCV,577,if (FeatureBitStack.empty()) return true; LLVM,RISCV,578,case SystemRegister : OS << << getSystemRegister() << ; break ; LLVM,RISCV,579,FeatureBitStack . push_back ( getSTI ( ) . getFeatureBit ( ) ); LLVM,RISCV,580,FeatureBitStack.push_back(getSTI()); LLVM,RISCV,581, LLVM,RISCV,582,"AsmParser ( const MCSubtargetInfo & STI , MCAsmParser & Parser , const MCInstrInfo & MII , const MCTargetOptions & Options ) : MCTargetAsmParser ( Options , STI , MII ) { Parser . addAliasForDirective ( , ); }" LLVM,RISCV,583,return Match_InvalidOperand; LLVM,RISCV,584,"void AsmPrinter::EmitInstruction(const MachineInstr *MI) { MCInstLower Lower(MF->getContext(), *MI); Lower.emitInstruction(MI); }" LLVM,RISCV,585,"Lower . lower ( MI , LoweredMI ) ;" LLVM,RISCV,586,"static MCSymbolRefExpr::VariantKind getModifierVariantKind( Modifier) { switch (Modifier) { case : return MCSymbolRefExpr::VK_NTPOFF; default: llvm_unreachable(""Unknown modifier""); } }" LLVM,RISCV,587,void LLVMInitializeAsmPrinter ( ) { LLVM,RISCV,588, LLVM,RISCV,589,OS << '%' << InstPrinter :: getRegisterName ( MI -> getOperand ( opNum ) . getReg ( ) ) ; LLVM,RISCV,590,OS << '%' << InstPrinter :: getRegisterName ( MI -> getOperand ( opNum ) . getReg ( ) ) ; LLVM,RISCV,591,) ; break ; case MachineOperand :: MO_Memory : { MCInstLower Lower ( MF -> getContext ( ) ) ; break ; } } } LLVM,RISCV,592,default : llvm_unreachable ( ) ; LLVM,RISCV,593,return AsmPrinter::runOnMachineFunction(MF); LLVM,RISCV,594,"if (emitPseudoExpansionLowering(*OutStreamer, MI)) return;" LLVM,RISCV,595,"AsmPrinter :: EmitToStreamer ( * OutStreamer , Res );" LLVM,RISCV,596,"AsmPrinter::EmitToStreamer(*OutStreamer, Inst);" LLVM,RISCV,597,"emitPseudoExpansionLowering(*OutStreamer, MI);" LLVM,RISCV,598, LLVM,RISCV,599,RegisterAsmPrinter < AsmPrinter > X ( getThe32Target ( ) ) ; LLVM,RISCV,600,if ( AsmVariant != ) report_fatal_error ( ) ; if ( ! ExtraCode ) { const MachineOperand & MO = MI -> getOperand ( OpNo LLVM,RISCV,601,( ) ; } else { OS << << InstPrinter :: getRegisterName ( MO . getReg ( ) ) ; } } LLVM,RISCV,602,return RTS; LLVM,RISCV,603,StringRef CPU = TM . getTargetCPU ( ) ; LLVM,RISCV,604,StringRef FS = TM . getTargetFeatureString ( ) ; LLVM,RISCV,605,"void AsmPrinter::printOperand(const MachineInstr *MI, int OpNo, raw_ostream &O) { const MachineOperand &MO = MI->getOperand(OpNo); switch (MO.getTargetFlags()) { case MachineOperand::MO_None: O << """"; break; case MachineOperand::MO_Register: O << getRegisterName(MO.getReg()); break; case MachineOperand::MO_Immediate: O << MO.getImm" LLVM,RISCV,606,StringRef CPU = TM.getTargetCPU(); LLVM,RISCV,607,RTS.emitTargetAttributes(STI); LLVM,RISCV,608, LLVM,RISCV,609,TargetStreamer & RTS = static_cast(*OutStreamer->getTargetStreamer()); LLVM,RISCV,610,RTS.emitDirectiveOptionPop(); LLVM,RISCV,611, LLVM,RISCV,612, LLVM,RISCV,613,"AsmPrinter :: PrintAsmOperand ( MI , OpNo , ExtraCode , OS ) ; return true ; } } return false ; }" LLVM,RISCV,614,"bool lowerOperand ( const MachineOperand & MO , MCOperand & MI ) { if ( MO.isReg() ) { MI.setReg( MO.getReg() ); } else if ( MO.isImm() ) { MI.setImm( MO.getImm() ); } else if ( MO.isMem() ) { MI.setMem( MO.getMem() ); } else { return false; } return true; }" LLVM,RISCV,615,RTS.emitELFFileFooter(M); LLVM,RISCV,616,RTS.setELFOSABI(ELFOSABI::ELFOSABI_NONE); LLVM,RISCV,617, LLVM,RISCV,618,"EmitToStreamer(OutStreamer, TmpInst);" LLVM,RISCV,619, LLVM,RISCV,620,void AsmPrinter::emitStartOfAsmFile(Module &M) { } LLVM,RISCV,621,if (TM.getTargetTriple().isOSBinFormatELF()) { LLVM,RISCV,622,if (Res) { LLVM,RISCV,623,"void AsmPrinter::EmitToStreamer(MCStreamer &S, const MCInst &Inst) { MCInst CInst = Inst; }" LLVM,RISCV,624,Here is LLVM,RISCV,625,"RegisterAsmPrinter < AsmPrinter > Y ( ""x86"", []() { return new X86Asm" LLVM,RISCV,626,LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAsmPrinter ( ) { LLVM,RISCV,627,"return LowerMachineOperandToMCOperand ( MO , MCOp , MCInst );" LLVM,RISCV,628,"return LowerMachineOperandToMCOperand(MO, MCOp, *);" LLVM,RISCV,629,return true ; } LLVM,RISCV,630,return false; LLVM,RISCV,631,if (isRV32Only && ActiveFeatures[]) return false; LLVM,RISCV,632,return TargetABI; LLVM,RISCV,633,"> ( VLMUL ) , false ) ;" LLVM,RISCV,634,inline static unsigned encodeSEW ( unsigned SEW ) { LLVM,RISCV,635,assert ( isValidSEW ( SEW ) && ) ; return Log2_32 ( SEW ) - LLVM,RISCV,636, LLVM,RISCV,637,"isValidVLMUL ( VLMUL ) ); unsigned VType :: encodeVTYPE ( VLMUL , unsigned SEW , bool TailAgnostic , bool MaskAgnostic ) { assert ( isValidSEW ( SEW ) && isValidVLMUL ( VLMUL ) ); unsigned result = 0; result |= ( VLMUL << VType :: VLMUL_SH" LLVM,RISCV,638,return isCheriPureCapABI ( TargetABI ) ? : ; LLVM,RISCV,639,ConstraintShift); LLVM,RISCV,640,ConstraintShift); LLVM,RISCV,641,return TargetABI; LLVM,RISCV,642,static inline bool isRVVWideningReduction ( uint64_t TSFlags ) { return TSFlags & (1 << 11); } LLVM,RISCV,643,if ( isMaskAgnostic ( VType ) ) LLVM,RISCV,644,static inline bool UsesMaskPolicy (uint64_t TSFlags) { return (TSFlags & TSFlagsMaskPolicy) != 0; } LLVM,RISCV,645,if (TT.isArch64Bit() && !FeatureBits[]) { LLVM,RISCV,646,OS << << Sew; LLVM,RISCV,647,if (TailAgnostic) VTypeI |= (1 << 12); LLVM,RISCV,648,return static_cast(value); LLVM,RISCV,649,int getSEWIndex ( ) const { return static_cast < int8_t > ( m_sewIndex ); } LLVM,RISCV,650,int getVLIndex ( ) const { return static_cast < int8_t > ( VLIndex [0] ); } LLVM,RISCV,651, LLVM,RISCV,652, LLVM,RISCV,653,unsigned VSEW = (VType >> 16) & 0xFFFF; LLVM,RISCV,654,unsigned Offset = ; if ( hasVecPolicyOp ( TSFlags ) ) Offset = Offset + 1; LLVM,RISCV,655,return Desc.getNumOperands() - Offset; LLVM,RISCV,656,unsigned Offset = 0; LLVM,RISCV,657,Register getBPReg() { LLVM,RISCV,658,Register getSCSPReg ( ) { return SCSP_REG; } LLVM,RISCV,659,Register getSCSPReg (Register reg LLVM,RISCV,660,unsigned VLMUL = VType & ; LLVM,RISCV,661,unsigned VSEW = ( VType >> 16 ) & 0x0000FFFF; LLVM,RISCV,662,errs ( ) << << ABIName << ; } else if ( ABIName . startswith ( ) && IsRV64 ) { errs ( ) << ; TargetAB LLVM,RISCV,663, LLVM,RISCV,664,bool writesElement0 ( ) const { return WritesElement0(); } LLVM,RISCV,665,if ( ! ABIName . empty ( ) && TargetABI == ABI_Unknown ) { LLVM,RISCV,666,if ( MaskAgnostic ) VTypeI |= ; LLVM,RISCV,667,if ( MaskAgnostic ) VTypeI |= ; LLVM,RISCV,668,"return llvm::join(FeatureVector, "","");" LLVM,RISCV,669, LLVM,RISCV,670,return ABI_Unknown; LLVM,RISCV,671,``` LLVM,RISCV,672,return << (VSEW); LLVM,RISCV,673,assert ( VSEW < VLM); LLVM,RISCV,674,return (TSFlags & ForceTailAgnosticMask) != 0; LLVM,RISCV,675,MCRegister getBPReg ( ) { return MCRegister::BP; } LLVM,RISCV,676,static inline VConstraintType getConstraint (VConstraintType type) { switch (type) { case VConstraintType::None: return VConstraintType::None; case VConstraintType::Equal: return VConstraintType::Equal; case VConstraintType::NotEqual: return VConstraintType::NotEqual; case VConstraintType::LessThan: return VConstraintType::LessThan; case VConstraintType::LessThanOrEqual: return VConstraintType::LessThanOr LLVM,RISCV,677,static inline VConstraintType getConstraint ( uint64_t constraintId ) { switch (constraintId) { case 0: return VConstraintType::None; case 1: return VConstraintType::LessThan; case 2: return VConstraintType::LessThanOrEqualTo; case 3: return VConstraintType::GreaterThan; case 4: return VConstraintType::GreaterThanOrEqualTo; case 5: LLVM,RISCV,678,return static_cast(TSFlags & VLMulMask) >> VLMulShift; LLVM,RISCV,679,return static_cast < VLMUL > ( ( TSFlags & VLMUL_MASK ) >> VLMUL_SHIFT ); LLVM,RISCV,680,MCRegister getSCSPReg (int reg) { MCRegister result; result.reg = reg; result.value = 0; return result; } LLVM,RISCV,681,MCRegister getSCSPReg ( ) { return SCSP.status; } LLVM,RISCV,682,inline static unsigned getSEW ( unsigned int sew_log2) { return 1 << sew_log2; } LLVM,RISCV,683,Default ( ABI_UNKNOWN ); LLVM,RISCV,684,inline static getVLMUL ( unsigned VType ) { unsigned VLMUL = (VType >> 2) & 0x3; LLVM,RISCV,685,return TSFlags & 0x00000001; LLVM,RISCV,686,return TSFlags & 0x00000001; LLVM,RISCV,687,return TSFlags & 0x00000001; LLVM,RISCV,688,static inline bool hasVecPolicyOp ( uint64_t TSFlags ) { LLVM,RISCV,689,inline static bool isMaskAgnostic ( unsigned VType ) { return VType & 1; } LLVM,RISCV,690, LLVM,RISCV,691,int lmul) { return (lmul >= 1 && lmul <= 8); } LLVM,RISCV,692,return isPowerOf2_32(LMUL) && LMUL <= && (!Fractional || LMUL <= 32); LLVM,RISCV,693,default: LLVM,RISCV,694,.Default(RoundingMode::NearestTiesToEven); LLVM,RISCV,695,"void validate ( const Triple & TT , const FeatureBitset & FeatureBits ) { if ( TT . isArch64Bit ( ) && FeatureBits [ ""arch64bit"" ] ) { } }" LLVM,RISCV,696,EverMadeChange |= MadeChange; LLVM,RISCV,697, LLVM,RISCV,698, LLVM,RISCV,699,BSel ( ) : MachineFunctionPass ( ID ) { initializeBSelPass ( * PassRegistry :: getPassRegistry ( ) ); } LLVM,RISCV,700,EverMadeChange |= MadeChange; LLVM,RISCV,701,"bool CallLowering :: lowerCall ( MachineIRBuilder & MIRBuilder , CallLoweringInfo & Info ) const { return MIRBuilder.lowerCall(Info); }" LLVM,RISCV,702,return false; LLVM,RISCV,703,"bool CallLowering::lowerFormalArguments(MachineIRBuilder &MIRBuilder, const Function &F, ArrayRef Args) { if (F.getNumFormalArguments() == 0) { return false; } SmallVector LoweredArgs; for (auto" LLVM,RISCV,704,"bool CallLowering::lowerFormalArguments(MachineIRBuilder &MIRBuilder, const Function &F, ArrayRef Args) { for (Argument *Arg : Args) { } return true; }" LLVM,RISCV,705,MI; Here's a breakdown of the code: LLVM,RISCV,706, LLVM,RISCV,707, LLVM,RISCV,708, LLVM,RISCV,709,return MachineFunctionProperties().set(MachineFunctionProperties::Property::kIsPure); LLVM,RISCV,710,"if (AVLReg == ""v0"") {" LLVM,RISCV,711,int64_t VTYPEImm = MI.getOperand().getImm(); if (PrevVTYPEImm != VTYPEImm) return false; if (MI.getOpcode() == ) { if (PrevVSETVLI->getOpcode() != ) return false; return PrevVSETVLI->getOperand().getImm() == MI.getOperand().get LLVM,RISCV,712,initializeCleanupVSETVLIPass(PassRegistry::getPassRegistry()); LLVM,RISCV,713,"MachineInstr * PrevVSETVLI = nullptr ; for ( auto MII = MBB . begin ( ) , MIE = MBB . end ( ) ; MII != MIE ; ) { MachineInstr & MI = * MII ++ ; if ( MI . getOpcode ( ) != && MI . getOpcode ( ) != ) { if ( PrevVSETVLI && ( MI . isCall ( ) || MI . modifiesRegister ( ) || MI" LLVM,RISCV,714,return Changed; LLVM,RISCV,715,const Subtarget & ST = MF.getSubtarget(); LLVM,RISCV,716,return Length - 1; LLVM,RISCV,717,return Align ( cc128_get_required_alignment ( Size ) ) ; LLVM,RISCV,718,"If `IsRV64` is false, the function returns the alignment required for a" LLVM,RISCV,719,"return static_cast(llvm::alignTo(Size, cc64_get_required_alignment(Size)));" LLVM,RISCV,720,"return new ConstantPoolValue(GV, Modifier.PUBLIC);" LLVM,RISCV,721,"return new ConstantPoolValue(GV, Modifier.PUBLIC);" LLVM,RISCV,722,void ConstantPoolValue::print(raw_ostream &O) const { O << GV; } LLVM,RISCV,723,"getType () , gv -> getAlignment () , gv -> getVisibility () , modifier ) { }" LLVM,RISCV,724, LLVM,RISCV,725,void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . addRequired < MachineLoopInfo > ( ); } LLVM,RISCV,726,AU.addRequired(); LLVM,RISCV,727,"{ return ""MyPass""; }" LLVM,RISCV,728, LLVM,RISCV,729,"static DecodeStatus DecodeFPR32CRegisterClass ( MCInst & Inst , uint64_t RegNo , uint64_t Address , const void * Decoder ) { if ( RegNo >= ) { return MCDisassembler :: Fail; } }" LLVM,RISCV,730,"Address, uint64_t Size, uint64_t AccessSize) { return DecodeStatus::Success; }" LLVM,RISCV,731,Inst.addOperand(MCOperand::createReg(Reg)); LLVM,RISCV,732,return MCDisassembler :: Success ; LLVM,RISCV,733,Register Reg = + RegNo ; LLVM,RISCV,734,"static DecodeStatus DecodeFPR64RegisterClass ( MCInst & Inst , uint64_t RegNo , uint64_t Address , const void * Decoder ) { if ( RegNo >= 32 ) return MCDisassembler :: Fail ; Register Reg = RegNo + 32 ;" LLVM,RISCV,735,"static DecodeStatus DecodeFPR64RegisterClass ( MCInst & Inst , uint64_t RegNo , uint64_t Address , const void * Decoder ) { if ( RegNo >= ) return MCDisassembler::Fail;" LLVM,RISCV,736,Register Reg = + RegNo ; Inst . addOperand ( MCOperand :: createReg ( Reg ) ) ; LLVM,RISCV,737,createReg ( RegNo ) ; Inst . addOperand ( MCOperand :: createReg ( RegNo ) ; Inst . addOperand ( MCOperand :: createReg ( RegNo ) ; Inst . addOperand ( MCOperand :: createReg ( RegNo ) ; Inst . addOperand ( MCOperand :: createReg ( RegNo ) ; Inst . addOperand ( MCOperand :: createReg ( RegNo ) ; Inst . addOperand ( MCOperand :: createReg ( RegNo ) ; Inst . addOperand ( MCOperand :: create LLVM,RISCV,738,return MCDisassembler :: Success; LLVM,RISCV,739,"static DecodeStatus decodeRVCInstrRdRs1Rs2 ( MCInst & Inst , unsigned Insn , uint64_t Address , const void * Decoder ) { unsigned Rd = fieldFromInstruction ( Insn , 7 , 7 ) ; unsigned Rs2 = fieldFromInstruction ( Insn , 2 , 2 ) ; DecodeGPRRegisterClass ( Inst , Rd , Address , Decoder ) ; Inst . addOperand ( Inst . getOperand ( Rd ) ) ; Inst . addOperand" LLVM,RISCV,740,"Inst.addOperand(Inst.getOperand()) ; uint64_t UImm6 = fieldFromInstruction(Insn, , ) << | fieldFromInstruction(Insn, , ) ; DecodeStatus Result = decodeUImmOperand < > ( Inst , UImm6 , Address , Decoder ) ; ( void ) Result ; assert ( Result == MCDisassembler ::" LLVM,RISCV,741,"DecodeGPRRegisterClass ( Inst , Rs2 , Address , Decoder ) ;" LLVM,RISCV,742,"unsigned Rs2 = fieldFromInstruction ( Insn , , ) ;" LLVM,RISCV,743,assert (Result == MCDisassembler::Success && ); LLVM,RISCV,744,"static DecodeStatus decodeRVCInstrSImm(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) { uint64_t SImm6 = fieldFromInstruction(Insn, 6, 6) << 6 | fieldFromInstruction(Insn, 5, 5); DecodeStatus Result = decodeSImmOperand<6>(Inst, SImm6, Address, Decoder); (void)Result; return Result; }" LLVM,RISCV,745,"return new Disassembler(STI, Ctx, T.createMCInstrInfo());" LLVM,RISCV,746,"static MCDisassembler * createDisassembler ( const Target & T , const MCSubtargetInfo & STI , MCContext & Ctx ) { return new Disassembler ( STI , Ctx , T ); }" LLVM,RISCV,747, LLVM,RISCV,748,void *Decoder) { if (RegNo > 15) return DecodeStatus::Fail; Inst.addOperand(MCOperand::createReg(ARM64_FPR16RegClassID + RegNo)); return DecodeStatus::Success; } LLVM,RISCV,749,if ( RegNo >= ) return MCDisassembler :: Fail ; LLVM,RISCV,750,"TargetRegistry::RegisterMCDisassembler(getThe64Target(), createDisassembler());" LLVM,RISCV,751,"if (Inst.getOpcode() == ) { DecodeGPCRRegisterClass(Inst, , Address, Decoder); }" LLVM,RISCV,752,return DecodeStatus::Fail; LLVM,RISCV,753,void *Decoder) { if (RegNo > 31) return DecodeStatus::Fail; Inst.addOperand(MCOperand::createReg(X86::FPR32RegClassID::FPR32Reg_0 + RegNo)); return DecodeStatus::OK; } LLVM,RISCV,754,if ( RegNo >= ) return MCDisassembler :: Fail ; MCRegister Reg = + RegNo ; Inst . addOperand ( MCOperand :: createReg ( Reg ) ) ; LLVM,RISCV,755,"static DecodeStatus DecodeFPR64RegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder) {" LLVM,RISCV,756,MCDisassembler::Fail; LLVM,RISCV,757,Inst.addOperand(MCOperand::createReg(Reg)); LLVM,RISCV,758,"static DecodeStatus DecodeGPRCRegisterClass ( MCInst & Inst , uint64_t RegNo , uint64_t Address , const void * Decoder ) { if ( RegNo >= ) return MCDisassembler :: Fail ; MCRegister Reg = + RegNo ; Inst . addOperand ( MCOperand :: createReg ( Reg ) ) ; return MCDisassembler :: Success ; }" LLVM,RISCV,759,bool IsRV32E = FeatureBits[]; LLVM,RISCV,760, LLVM,RISCV,761,"static DecodeStatus DecodeVRM2RegisterClass ( MCInst & Inst , uint64_t RegNo , uint64_t Address , const void * Decoder ) {" LLVM,RISCV,762, LLVM,RISCV,763, LLVM,RISCV,764,createReg ( Reg ) ) ; Inst.addOperand(MCOperand::createReg(Reg LLVM,RISCV,765,if ( RegNo >= ) return MCDisassembler :: Fail ; MCRegister Reg = + RegNo ; Inst . addOperand ( MCOperand :: createReg ( Reg ) ) ; LLVM,RISCV,766,Size = ; LLVM,RISCV,767,return MCDisassembler :: Success ; LLVM,RISCV,768,"static DecodeStatus DecodeVGRRegisterClass ( MCInst & Inst , uint64_t RegNo , uint64_t Address , const void * Decoder ) {" LLVM,RISCV,769,return MCDisassembler :: Success ; LLVM,RISCV,770,Inst.addOperand(MCOperand::createReg(Reg)); LLVM,RISCV,771,return MCDisassembler :: Success ; LLVM,RISCV,772,"static DecodeStatus decodeSImmOperand ( MCInst & Inst , uint64_t Imm ) { int64_t SignExtended = SignExtend64 (Imm, 12); Inst.addOperand (MCOperand::createImm (SignExtended)); return DecodeStatus::Success; }" LLVM,RISCV,773,"static DecodeStatus decodeUImmOperand ( MCInst & Inst , uint64_t Imm , int64_t Address , const void * Decoder ) { assert ( isUInt < N > ( Imm ) );" LLVM,RISCV,774,"return decodeInstruction ( DecoderTable32 , MI , Inst );" LLVM,RISCV,775,Inst.addOperand(MCOperand::createReg(RegNo)); LLVM,RISCV,776,return DecodeStatus::Success LLVM,RISCV,777,"return decodeUImmOperand < N > ( Inst , 0);" LLVM,RISCV,778,MCDisassembler :: Fail; LLVM,RISCV,779,Inst . addOperand ( MCOperand :: createReg ( Reg ) ) ; LLVM,RISCV,780,Size = ; LLVM,RISCV,781,"return DecodeGPRRegisterClass ( Inst , RegNo , Address , RegClass );" LLVM,RISCV,782,"static DecodeStatus DecodePulpV2RegisterClass ( MCInst & Inst , uint64_t RegNo , uint64_t Address , const void * Decoder ) { return DecodeGPRRegisterClass ( Inst , RegNo , Address , Decoder ); }" LLVM,RISCV,783,"return DecodeGPRRegisterClass ( Inst , RegNo , Address , RegClass );" LLVM,RISCV,784, LLVM,RISCV,785,Register Reg = FPR32DecoderTable[RegNo]; LLVM,RISCV,786,return MCDisassembler :: Success ; LLVM,RISCV,787,return MCDisassembler :: Success ; LLVM,RISCV,788,Inst.addOperand(MCOperand::createReg(Reg)); LLVM,RISCV,789,Register Reg = FPR64DecoderTable[RegNo]; LLVM,RISCV,790,if ( RegNo > ) LLVM,RISCV,791, LLVM,RISCV,792,") == ) { DecodeGPRRegisterClass ( Inst , , Address , Decoder ) ; }" LLVM,RISCV,793,"static DecodeStatus decodeCLUIImmOperand ( MCInst & Inst , uint64_t Imm , int64_t Address , const MCDisassembler * Decoder ) { assert ( isUInt < > ( Imm ) && ( Imm ) );" LLVM,RISCV,794,createReg (Reg)); LLVM,RISCV,795,MCRegister Reg = MCRegister::createReg(RegNo); Explanation: LLVM,RISCV,796,MCRegister Reg = + RegNo; LLVM,RISCV,797,createReg ( Reg ) ) ; return MCDisassembler :: Success ; } LLVM,RISCV,798,if ( RegNo >= ) return MCDisassembler :: Fail ; MCRegister Reg = LLVM,RISCV,799,"static DecodeStatus DecodeGPRCRegisterClass ( MCInst & Inst , uint64_t RegNo , uint64_t Address , const MCDisassembler * Decoder ) { if ( RegNo >= ) return MCDisassembler :: Fail ; MCRegister Reg = + RegNo ; Inst . addOperand ( MCOperand :: createReg ( Reg ) ) ; return MCDisassembler :: Success ; }" LLVM,RISCV,800,if ( RegNo >= ) return MCDisassembler :: Fail ; MCRegister Reg = LLVM,RISCV,801,return MCDisassembler :: Success ; } LLVM,RISCV,802,"static DecodeStatus DecodeGPRNoX0X2RegisterClass ( MCInst & Inst , uint64_t RegNo , uint64_t Address , const MCDisassembler * Decoder ) { if ( RegNo == 0 ) { Inst.addOperand(MCOperand::createReg(X86::X0)); return DecodeStatus::Success; } if ( RegNo == 2 ) { Inst.addOperand(MCOperand::createReg(X86::X2)); return Decode" LLVM,RISCV,803,void *Decoder) { if (RegNo > 31) return DecodeStatus::Fail; switch (RegNo) { case 0: Inst.addOperand(MCOperand::createReg(X86::GPR64Regs[0])); return DecodeStatus::Success; case 1: Inst.addOperand(MCOperand::createReg(X86::GPR6 LLVM,RISCV,804, LLVM,RISCV,805,MCRegister Reg = DecodeGPR64Register (RegNo); LLVM,RISCV,806,Inst . addOperand ( MCOperand :: createReg ( Reg ) ) ; LLVM,RISCV,807,"static DecodeStatus decodeRVCInstrRdRs1Rs2 ( MCInst & Inst , unsigned Insn , uint64_t Address , const MCDisassembler * Decoder ) { unsigned Rd = fieldFromInstruction ( Insn , 7 , 5 ); unsigned Rs1 = fieldFromInstruction ( Insn , 15 , 3 ); unsigned Rs2 = fieldFromInstruction ( Insn , 20 , 3 ); if ( Rd == 0 ) { return DecodeStatus" LLVM,RISCV,808,Success; LLVM,RISCV,809,"static DecodeStatus decodeRVCInstrRdRs2 ( MCInst & Inst , unsigned Insn , uint64_t Address , const MCDisassembler * Decoder ) { unsigned Rd = fieldFromInstruction ( Insn , , ) ; unsigned Rs2 = fieldFromInstruction ( Insn , , ) ; DecodeGPRRegisterClass ( Inst , Rd , Address ) ; DecodeGPRRegisterClass (" LLVM,RISCV,810,"uint64_t SImm6 = fieldFromInstruction ( Insn , , ) << | fieldFromInstruction ( Insn , , ) ;" LLVM,RISCV,811,"if ( Imm == ) return MCDisassembler :: Fail ; return decodeSImmOperand < N > ( Inst, Size, Val ) ;" LLVM,RISCV,812,( Imm ) ) ) ; return MCDisassembler :: Success ; } LLVM,RISCV,813,Inst.addOperand(MCOperand::createImm(SignExtend64(Imm << ))); LLVM,RISCV,814, LLVM,RISCV,815,"static DecodeStatus decodeUImmNonZeroOperand ( MCInst & Inst , uint64_t Imm , int64_t Address , const MCDisassembler * Decoder ) { if ( Imm == ) return MCDisassembler :: Fail ; return decodeUImmOperand < N > ( Inst , Imm , Address , Decoder ); }" LLVM,RISCV,816,Inst.addOperand(MCOperand::createReg(Reg)); LLVM,RISCV,817, LLVM,RISCV,818,"Reg ) ) ; return MCDisassembler :: Success ; } Next, the function checks if the register number is a multiple of a constant value. If it is not, the function returns `MCDis" LLVM,RISCV,819,return MCDisassembler::Fail; LLVM,RISCV,820,"static DecodeStatus DecodeVRRegisterClass ( MCInst & Inst , uint64_t RegNo , uint64_t Size ) { if (RegNo >= 32) return DecodeStatus::Fail; Inst.addOperand(MCOperand::createReg(X86::VR0 + RegNo)); return DecodeStatus::Success; }" LLVM,RISCV,821,"static MCDisassembler * createDisassembler ( const Target & T , const MCSubtargetInfo & STI , MCContext & Ctx ) { return new Disassembler ( STI , Ctx ); }" LLVM,RISCV,822,Inst.addOperand(MCOperand::createImm(Imm)); LLVM,RISCV,823,createReg ( Reg ) ) ; return MCDisassembler :: Success ; } LLVM,RISCV,824, LLVM,RISCV,825,"static DecodeStatus DecodeFPR64RegisterClass ( MCInst & Inst , uint64_t RegNo , uint64_t Address , const void * Decoder ) {" LLVM,RISCV,826,return MCDisassembler :: Success ; LLVM,RISCV,827,DecodeStatus::Fail; LLVM,RISCV,828,assert ( isUInt < > ( Imm ) && ) ; if ( ! llvm :: ( Imm ) ) { LLVM,RISCV,829,if ( RegNo > ) return MC LLVM,RISCV,830,Inst.addOperand(MCOperand::createReg(Reg)); LLVM,RISCV,831,"static DecodeStatus DecodeGPRNoX0X2RegisterClass ( MCInst & Inst , uint64_t RegNo , uint64_t Address , const void * Decoder ) { if ( RegNo == ) { return MCDisassembler :: Fail ; } return DecodeGPRNoX0RegisterClass ( Inst , RegNo , Address , Decoder ) ; }" LLVM,RISCV,832,"static DecodeStatus DecodeGPRNoX0X2RegisterClass ( MCInst & Inst , uint64_t RegNo , uint64_t Address , const void * Decoder ) { if ( RegNo == 0 || RegNo == 2 ) { Inst.addOperand(MCOperand::createReg(X86::GPRNoX0X2[RegNo])); return DecodeStatus::Success; } else { return DecodeStatus::Fail; } }" LLVM,RISCV,833,return MCDisassembler::Success; LLVM,RISCV,834,return MCDisassembler :: Success ; LLVM,RISCV,835,"static DecodeStatus decodeSImmOperand ( MCInst & Inst , uint64_t Imm , int64_t Address , const void * Decoder ) { assert ( isUInt < N > ( Imm ) ); int64_t SignedImm = SignExtend64 ( Imm, N ); Inst.addOperand ( MCOperand::createImm ( SignedImm ) ); return DecodeStatus::Success;" LLVM,RISCV,836,return MCDisassembler::Success; LLVM,RISCV,837, LLVM,RISCV,838,"static DecodeStatus decodeUImmOperand ( MCInst & Inst , uint64_t Imm , int64_t Address , const void * Decoder ) { assert ( isUInt < N > ( Imm ) );" LLVM,RISCV,839,LLVM_DEBUG ( dbgs ( ) << ) ; LLVM,RISCV,840, LLVM,RISCV,841,return llvm::make_uniqueELFObjectWriter>(); LLVM,RISCV,842,return llvm::make_unique( LLVM,RISCV,843, LLVM,RISCV,844,"bool needsRelocateWithSymbol(const MCSymbol &Sym, unsigned int RelocType) {" LLVM,RISCV,845, LLVM,RISCV,846, LLVM,RISCV,847,"std::unique_ptr llvm::createELFObjectWriter(raw_pwrite_stream& OS, bool IsLittleEndian, bool Is64Bit)" LLVM,RISCV,848,``` LLVM,RISCV,849,"createELFObjectWriter(MOTW, OS, Is64Bit);" LLVM,RISCV,850,"MCObjectWriter * llvm :: createELFObjectWriter ( raw_pwrite_stream & OS , uint8_t OSABI , bool IsELF64 ) {" LLVM,RISCV,851,"""unknown fixup kind in getRelocType"" ); }" LLVM,RISCV,852,return ELF::R__32; LLVM,RISCV,853, LLVM,RISCV,854,case : return ELF :: R__TPREL_LO12_S ; LLVM,RISCV,855, LLVM,RISCV,856, LLVM,RISCV,857,default : llvm_unreachable ( ) ; } } switch ( Kind ) { default : llvm_unreachable ( ) ; case FK_Data_4 : if ( Expr -> getKind ( ) == MCExpr :: Target && cast < MCExpr > ( Expr ) -> getKind ( ) == MCExpr :: VK__32_PCREL ) return ELF :: R_ : return ELF :: R__CALL; LLVM,RISCV,860,case FK_Data_Add_8: return ELF::R__ADD64; LLVM,RISCV,861, LLVM,RISCV,862, LLVM,RISCV,863, LLVM,RISCV,864,return S; LLVM,RISCV,865,"setAttributeItem ( Attribute , Value )" LLVM,RISCV,866,"setAttributeItems ( Attribute , IntValue , StringValue , BooleanValue )" LLVM,RISCV,867,"setAttributeItems ( Attribute , IntValue , StringValue , true );" LLVM,RISCV,868,"var element = document.getElementById(""myElement"");" LLVM,RISCV,869,"void TargetELFStreamer::emitTextAttribute(unsigned Attribute, StringRef Value) { }" LLVM,RISCV,870, LLVM,RISCV,871,DF->getContents()->resize(DF->getContents()->size() + 4)); LLVM,RISCV,872, LLVM,RISCV,873,const size_t ContentsSize = calculateContentSize(); LLVM,RISCV,874,"return std::make_pair(, ); The" LLVM,RISCV,875,"case : return std :: make_pair ( , ) ;" LLVM,RISCV,876,MCELFStreamer & TargetELFStreamer :: getStreamer (MCELFStreamer &Streamer) { return Streamer; } LLVM,RISCV,877,return static_cast < MCELFStreamer & > (this->createELFStreamer()); LLVM,RISCV,878,"RHS = MCSymbolRefExpr::create(&B, C);" LLVM,RISCV,879,. isInSection ( ) ? B . getSection ( ) . hasInstructions ( ) : ! B . getName ( ) . empty ( ) ) ; LLVM,RISCV,880,( ) override { static_cast < TargetStreamer * > ( getTargetStreamer ( ) )->reset ( ); } LLVM,RISCV,881,"MAB.setTargetABI( (STI.getTargetTriple(), Features, MAB.getTargetABI()));" LLVM,RISCV,882,MCA.setELFHeaderEFlags(EFlags); LLVM,RISCV,883, LLVM,RISCV,884,const FeatureBitset & Features = STI . getFeatureBits ( ) ; unsigned EFlags = MCA . getELFHeaderEFlags ( ) ; if ( Features [ ] ) EFlags |= ELF :: EF__RVC ; MCA . setELFHeaderEFlags ( EFlags ) ; LLVM,RISCV,885,MCDataFragment * DF = new MCDataFragment(); LLVM,RISCV,886,"emitCheriIntcapGeneric(Expr, CapSize, Loc);" LLVM,RISCV,887, LLVM,RISCV,888,if (Features[]) EFlags |= ELF::EF__RVC; LLVM,RISCV,889,"void setAttributeItem ( unsigned Attribute , StringRef Value , bool OverwriteExisting ) { if ( AttributeItem * Item = getAttributeItem ( Attribute ) ) { if ( ! OverwriteExisting ) return ; Item -> Type = AttributeType :: Text ; Item -> StringValue = std :: string ( Value ) ; return ; } Contents . push_back ( { AttributeType :: Text , Attribute , , std :: string ( Value ) } ) ; }" LLVM,RISCV,890, LLVM,RISCV,891,NextMBBI = MBB.end(); LLVM,RISCV,892, LLVM,RISCV,893,BuildMI(LoopTailMB LLVM,RISCV,894,"if ( Width == ) return getLRForRMW64 ( PtrIsCap , Ordering ) ;" LLVM,RISCV,895,"return getLRForRMW64(PtrIsCap, Ordering);" LLVM,RISCV,896,"assert ( PtrIsCap ) ; switch ( Ordering ) { default : llvm_unreachable ( ""Invalid atomic ordering"" ) ; case AtomicOrdering :: Monotonic : return ""Monotonic"" ; case AtomicOrdering :: Acquire : return ""Acquire"" ; }" LLVM,RISCV,897,return PtrIsCap ? : ; LLVM,RISCV,898, LLVM,RISCV,899,llvm_unreachable ( ) ; case AtomicOrdering :: Monotonic : return PtrIsCap ? : ; case AtomicOrdering :: Acquire : return PtrIsCap ? : ; case AtomicOrdering :: Release : return PtrIsCap ? < LLVM,RISCV,900, LLVM,RISCV,901,AcqRel : return ; LLVM,RISCV,902, LLVM,RISCV,903, LLVM,RISCV,904,"static unsigned getSCForRMW64 ( bool PtrIsCap , AtomicOrdering" LLVM,RISCV,905,case AtomicOrdering :: Release : return PtrIsCap ? : ; LLVM,RISCV,906,( PtrIsCap ? : ) : ( PtrIsCap ? : ) ; LLVM,RISCV,907,return new ExpandAtomicPseudo ( ); LLVM,RISCV,908,return new ExpandAtomicPseudo ( ); LLVM,RISCV,909, LLVM,RISCV,910, LLVM,RISCV,911,LoopMBB->addSuccessor(DoneMBB); LLVM,RISCV,912, LLVM,RISCV,913,"BuildMI(LoopHeadMBB, DL, TII->get(), Scratch2Reg).addReg(IncrReg);" LLVM,RISCV,914,"case : return expandAtomicCmpXchg ( MBB , MBBI , false , [" LLVM,RISCV,915, LLVM,RISCV,916, LLVM,RISCV,917,default: LLVM,RISCV,918,case AtomicOrdering :: SequentiallyConsistent : return ; LLVM,RISCV,919,"{ return ""MyPass""; }" LLVM,RISCV,920,"StringRef getPassName() const override { return ""MyPass""; } Explanation:" LLVM,RISCV,921,"static unsigned getSCForRMW ( AtomicOrdering Ordering , int Width ) { if ( Width == 1 ) return 0; if ( Width == 2 ) return 1; if ( Width == 4 ) return 2; if ( Width == 8 ) return 3; if ( Width == 16 ) return 4; if ( Width == 32 ) return 5; if ( Width == 64 ) return 6; if ( Width == 128 ) return 7; if ( Width == 256 ) return 8; if (" LLVM,RISCV,922,case AtomicOrdering :: SequentiallyConsistent : return ; LLVM,RISCV,923,case AtomicOrdering :: AcquireRelease : return ; LLVM,RISCV,924,Here is a LLVM,RISCV,925,PassRegistry::getPassRegistry()->registerPass LLVM,RISCV,926,initializeExpandAtomicPseudoPass ( * PassRegistry :: getPassRegistry () ); LLVM,RISCV,927,TII = static_cast < const InstrInfo * > ( MF . getSubtarget ( ) ) ; LLVM,RISCV,928,bool ExpandAtomicPseudo :: runOnMachineFunction ( MachineFunction & MF ) { LLVM,RISCV,929,Pass *llvm::createExpandCoreVHwlpPseudoPass() { return new ExpandCoreVHwlpPseudoPass(); } LLVM,RISCV,930,Pass *llvm::createExpandCoreVHwlpPseudoPass() { return new ExpandCoreVHwlpPseudoPass(); } LLVM,RISCV,931,"{ return ""MyPass""; }" LLVM,RISCV,932,"BuildMI ( * Preheader , HwlpSetup , DL , TII -> get ( ) ) . addImm ( LoopNum ) . addImm ( count ) . addSym ( LastInstrSymbol ) ;" LLVM,RISCV,933,return Changed; LLVM,RISCV,934,"return expandReadCSRs ( MBB , MBBI , );" LLVM,RISCV,935,"It then creates a new machine basic block and inserts it after the current block. It builds two new machine instructions, one for the temporary register and one for the destination register. The temporary register instruction" LLVM,RISCV,936, LLVM,RISCV,937,1. `return LLVM,RISCV,938,"bool ExpandPseudo :: expandCapLoadTLSGDCap ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI , MachineBasicBlock :: iterator & NextMBBI ) { return expandAuipccInstPair ( MBB , MBBI , NextMBBI , MRI::CAP_LOAD_TLSGD_CAP ); }" LLVM,RISCV,939, LLVM,RISCV,940,return true; LLVM,RISCV,941, LLVM,RISCV,942,llvm_unreachable() LLVM,RISCV,943, LLVM,RISCV,944, LLVM,RISCV,945, LLVM,RISCV,946, LLVM,RISCV,947, LLVM,RISCV,948,assert ( ( MBBI -> getOpcode ( ) == || MBBI -> getOpcode ( ) == ) && ) ; LLVM,RISCV,949,"assert ( Desc . getNumOperands ( ) == && ) ; Register DstReg = MBBI -> getOperand ( ) . getReg ( ) ; bool DstIsDead = MBBI -> getOperand ( ) . isDead ( ) ; BuildMI ( MBB , MBBI , DL , Desc ) . addReg ( DstReg , RegState :: Define | getDeadRegState ( Dst" LLVM,RISCV,950, LLVM,RISCV,951,assert (Width == && ); LLVM,RISCV,952, LLVM,RISCV,953,MBBI->eraseFromParent(); LLVM,RISCV,954,NewMBB->end() LLVM,RISCV,955,"return expandAtomicBinOp(MBB, MBBI, AtomicRMWInst::Add, true, , NextMBBI);" LLVM,RISCV,956, LLVM,RISCV,957,return; LLVM,RISCV,958,return true; LLVM,RISCV,959,"Xchg: BuildMI ( LoopMBB , DL , TII -> get ( getLRForRMW32 ( Ordering ) ) , DestReg ) . addReg ( AddrReg ) . addReg ( ScratchReg ) . addImm ( 1 ) ; break ; case AtomicRMWInst :: Add: BuildMI ( LoopMBB , DL , TII -> get ( getLRForRMW32 ( Ordering ) ) , DestReg ) . addReg ( AddrReg ) . addReg ( ScratchReg ) . addImm ( 1" LLVM,RISCV,960,( ) . getImm ( ) ) ; LLVM,RISCV,961, LLVM,RISCV,962,NextMBBI = MBB.end(); LLVM,RISCV,963, LLVM,RISCV,964,"BuildMI (MBB, DL, TII -> get (), DestReg) . addReg (OldValReg)" LLVM,RISCV,965, LLVM,RISCV,966,"case : return expandLoadAddress ( MBB , MBBI , NextMBBI ) ;" LLVM,RISCV,967,"Sub: BuildMI(LoopMBB, DL, TII->get(), ScratchReg) .addReg(DestReg) .addReg(IncrReg); break;" LLVM,RISCV,968,"BuildMI ( LoopMBB , DL , TII -> get ( ) ) . addReg ( ScratchReg ) ." LLVM,RISCV,969,"case : return expandAtomicMinMaxOp ( MBB , MBBI , AtomicRMWInst :: UMin , true , , NextMBBI ) ;" LLVM,RISCV,970,"case : return expandAtomicBinOp ( MBB , MBBI , AtomicRMWInst :: Sub , true , , NextMBBI ) ;" LLVM,RISCV,971,"return expandAtomicMinMaxOp ( MBB , MBBI , AtomicRMWInst :: Max , true , , NextMBBI ) ;" LLVM,RISCV,972,FunctionPass * createExpandPseudoPass ( ) { return new ExpandPseudo ( ); } LLVM,RISCV,973,NewMBB->setLabelMustBeEmitted(); LLVM,RISCV,974, LLVM,RISCV,975, LLVM,RISCV,976,"return expandAuipcInstPair(MBB, MBBI, NextMBBI);" LLVM,RISCV,977,"bool ExpandPseudo :: expandLoadTLSGDAddress ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI , MachineBasicBlock :: iterator & NextMBBI ) { return expandAuipcInstPair ( MBB , MBBI , NextMBBI , TLSGD_LO_REG , TLSGD_HI_REG ); }" LLVM,RISCV,978,return Modified; LLVM,RISCV,979,"ExpandPseudo :: expandVSetVL ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI ) { assert ( MBBI -> getNumOperands ( ) == && ) ; DebugLoc DL = MBBI -> getDebugLoc ( ) ; assert ( MBBI -> getOpcode ( ) == && ) ; const MCInstrDesc & Desc = TII -> get ( MBBI -> getOpcode ( ) ) ;" LLVM,RISCV,980,"BuildMI(MBB, MBBI, DL, Desc)" LLVM,RISCV,981,StringRef getPassName() const override { return _EXPAND_PSEUDO_NAME; } LLVM,RISCV,982,initializeExpandPseudoPass ( * PassRegistry :: getPassRegistry () ); LLVM,RISCV,983,"#include ""llvm/IR/Function.h""" LLVM,RISCV,984,uint64_t MaxSPOffset = MF.getInfoFunctionInfo>()->getIncomingArgSize() + MFI; LLVM,RISCV,985,unsigned FrameLowering::ehDataReg(unsigned I) const { static const unsigned EhDataReg[] = { }; return EhDataReg[I]; } LLVM,RISCV,986,if (FI->getCallsEhReturn()) { LLVM,RISCV,987,return MF.getTarget().Options.DisableFramePointerElim(MF) || MFI.getTarget().Options.DisableFramePointerElim(MF); LLVM,RISCV,988,"BuildMI(MBB, MBBI, DL, TII->get(Opc), SPReg).addReg(SPReg).addReg(FactorRegister, RegState);" LLVM,RISCV,989, LLVM,RISCV,990,bool FrameLowering :: canUseAsEpilogue ( const MachineBasicBlock & MBB ) const { LLVM,RISCV,991,if (hasBP(MF)) SavedRegs.set(()); MachineFrameInfo &MFI = MF.getFrameInfo(); if (MF.getFunction().hasFnAttribute() && MFI.hasCalls()) { static const LLVM,RISCV,992,RVFI->setRVVStackSize(FrameSize); LLVM,RISCV,993, LLVM,RISCV,994,"BuildMI (MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION)) .addCFIIndex(CFIIndex) .setMIFlag(MachineInstr::FrameSetup); }" LLVM,RISCV,995, LLVM,RISCV,996,if (RVFI->getLibCallStackSize()) return ; LLVM,RISCV,997, LLVM,RISCV,998,static Register getFPReg ( const Subtarget & STI ) { return STI.getFPReg(); } LLVM,RISCV,999, LLVM,RISCV,1000, LLVM,RISCV,1001,static Register getSPReg ( const Subtarget & STI ) { return SP; } LLVM,RISCV,1002,static Register getSPReg ( const Subtarget & STI ) { return STI.getStackPointerRegister(); } LLVM,RISCV,1003,return TargetStackID :: getStackIDForScalableVectors(); LLVM,RISCV,1004,bool FrameLowering :: hasReservedCallFrame ( const MachineFunction & MF ) const { return ! MF . getFrameInfo ( ) . hasVarSizedObjects ( ) && ! ( hasFP ( MF ) && MF . getFrameInfo ( ) . hasSavedRegisters ( ) ); } LLVM,RISCV,1005,case TargetStackID :: NoAlloc : case TargetStackID :: Fixed : return true ; LLVM,RISCV,1006,RVFI->setCalleeSavedStackSize(Size); LLVM,RISCV,1007,if ( MI != MBB . end ( ) && MI -> getOpcode ( ) == TargetOpcode::CALL ) LLVM,RISCV,1008,return true; LLVM,RISCV,1009,Opc = Val; LLVM,RISCV,1010, LLVM,RISCV,1011,return MBB.erase(MI); LLVM,RISCV,1012,"assert(hasFP(MF) && ""Frame pointer is not available"");" LLVM,RISCV,1013, LLVM,RISCV,1014, LLVM,RISCV,1015,static unsigned getFPReg ( const Subtarget & STI ) { return STI.getFPReg(); } LLVM,RISCV,1016,"static unsigned getSPReg ( const void* p ) { unsigned sp; asm volatile ( ""mov %0, sp"" : ""=r"" ( sp ) ); return sp; }" LLVM,RISCV,1017,static unsigned getSPReg ( const Subtarget & STI ) { return STI.getSPReg(); } LLVM,RISCV,1018,return TargetStackID :: Vector; LLVM,RISCV,1019,switch (TargetStackID) { LLVM,RISCV,1020,Align Alignment = RegInfo->getSpillAlignment(RC); LLVM,RISCV,1021, LLVM,RISCV,1022, LLVM,RISCV,1023,MachineInstr::FrameDestroy); LLVM,RISCV,1024,) { LLVM,RISCV,1025,RVFI->setCalleeSavedStackSize(Size); LLVM,RISCV,1026,RVFI->setCalleeSavedStackSize(Size); LLVM,RISCV,1027,return MFI.hasVarSizedObjects() && TRI->hasStackRealignment(); LLVM,RISCV,1028,return false; LLVM,RISCV,1029,"( ) . getSubtarget < Subtarget > ( ) . hasStdExtV ( ) ) return false ; return any_of ( MF , [ & TII ] ( const MachineBasicBlock & MBB ) { return TII . hasStdExtV ( MBB . getParent ( ) ) ; } ) ;" LLVM,RISCV,1030,if (CSI.empty()) return true; LLVM,RISCV,1031,Align StackAlign = getStackAlign(MFI.getStackAlign()); LLVM,RISCV,1032,uint64_t FrameSize = MFI.getStackSize(); LLVM,RISCV,1033,if ( FirstSPAdjustAmount ) { LLVM,RISCV,1034,"adjustReg(MBB, MBBI, DL, SPReg, SPReg, StackSize, MachineInstr::FrameDestroy);" LLVM,RISCV,1035,"FrameSize = alignTo(FrameSize, StackAlign);" LLVM,RISCV,1036,uint64_t FirstSPAdjustAmount = getFirstSPAdjustAmount(MF); LLVM,RISCV,1037, LLVM,RISCV,1038, LLVM,RISCV,1039,uint64_t StackAlign = getStackAlignment(); LLVM,RISCV,1040,const std::vector& CSI = MFI.getCalleeSavedInfo(); LLVM,RISCV,1041,Offset += MF.getFrameInfo().getStackSize(); LLVM,RISCV,1042, LLVM,RISCV,1043,return !RS.isRegUsed(); LLVM,RISCV,1044,return false; LLVM,RISCV,1045, LLVM,RISCV,1046,uint64_t FramePointerOffset = RealStackSize - RVFI->getLibCallStackSize(); LLVM,RISCV,1047,.getTargetTriple ( ) ) ) { LLVM,RISCV,1048, LLVM,RISCV,1049, LLVM,RISCV,1050,Offset += RVFI->getLibCallStackSize(); LLVM,RISCV,1051,Here is a possible completion of LLVM,RISCV,1052, LLVM,RISCV,1053,if (FirstSPAdjustAmount) { LLVM,RISCV,1054,return Offset; LLVM,RISCV,1055, LLVM,RISCV,1056, LLVM,RISCV,1057, LLVM,RISCV,1058, LLVM,RISCV,1059, LLVM,RISCV,1060, LLVM,RISCV,1061, LLVM,RISCV,1062, LLVM,RISCV,1063,else if ( RI -> needsStackRealignment ( MF ) && ! MFI . isFixedObjectIndex ( FI ) ) { LLVM,RISCV,1064, LLVM,RISCV,1065,if (FirstSPAdjustAmount) { uint64_t SecondSPAdjustAmount = MFI.getStackSize() - FirstSPAdjustAmount; assert(SecondSPAdjustAmount > 0); } LLVM,RISCV,1066,FrameLowering::hasFP() const { return m_hasFP; } LLVM,RISCV,1067,CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; } LLVM,RISCV,1068,"DL , MF , RegInfo , RC ) ;" LLVM,RISCV,1069,const TargetRegisterClass * RC = & RegInfo->getRegClassForKind(TargetRegisterKind::General); LLVM,RISCV,1070, LLVM,RISCV,1071, LLVM,RISCV,1072,"if ( hasFP(MF) ) { const RegisterInfo * RI = STI . getRegisterInfo ( ) ; if ( RI -> hasStackRealignment ) { adjustReg ( MBB , MBBI , DL , FPReg , SPReg , RVFI -> getStackRealignment ( ) , MachineInstr :: FrameSetup ) ; unsigned CFIIndex = MF . addFrameInst ( MCCFIInstruction :: cfiDefCfaOffset ( nullptr , RVFI -> getStackRealignment (" LLVM,RISCV,1073,"llvm_unreachable(""Unhandled TargetStackID"");" LLVM,RISCV,1074, LLVM,RISCV,1075,"void FrameLowering :: determineCalleeSaves ( MachineFunction & MF , BitVector & SavedRegs , RegScavenger * RS ) const { TargetFrameLowering :: determineCalleeSaves ( MF , SavedRegs , RS ) ; if ( hasFP ( MF ) ) { SavedRegs . set ( ) ; SavedRegs . set ( ) ; } }" LLVM,RISCV,1076, LLVM,RISCV,1077,"assert(hasFP(MF) && ""Stack realignment requires a frame pointer"");" LLVM,RISCV,1078,if ( hasFP ( MF ) ) { if ( STI . isRegisterReservedByUser ( FPReg ) ) MF . getFunction ( ) . getContext ( ) . diagnose ( DiagnosticInfoUnsupported { MF LLVM,RISCV,1079, LLVM,RISCV,1080, LLVM,RISCV,1081,"void FrameLowering :: determineCalleeSaves ( MachineFunction & MF , BitVector & SavedRegs , RegScavenger * RS ) const {" LLVM,RISCV,1082,const ISA_LIT RegisterInfo * RI = STI . getRegisterInfo ( ) ; LLVM,RISCV,1083, LLVM,RISCV,1084,uint64_t StackSize = MFI . getStackSize ( ) ; LLVM,RISCV,1085,unsigned FPReg = getFPReg(STI); LLVM,RISCV,1086,MinCSFI = CSI[].getFrameIdx(); LLVM,RISCV,1087, LLVM,RISCV,1088,"uint64_t StackSize = MFI.getStackSize(); if (StackSize == && !MFI.adjustsStack()) return; adjustReg(MBB, MBBI, DL, SPReg, SPReg, -StackSize, MachineInstr::FrameSetup); unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createDefCfaOffset(nullptr, -StackSize)); BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_" LLVM,RISCV,1089,Entry . first ) ; if ( Offset < 0 ) continue ; int64_t OffsetFromSP = Offset + StackSize ; if ( OffsetFromSP < 0 ) continue ; if ( OffsetFromSP >= 0 ) { LLVM,RISCV,1090,for (const auto &Entry : CSI) { LLVM,RISCV,1091,"BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION)).addCFIIndex(CFIIndex);" LLVM,RISCV,1092, LLVM,RISCV,1093,Here are some possible ways to complete the last statement: LLVM,RISCV,1094,"void FrameLowering :: emitPrologue ( MachineFunction & MF , MachineBasicBlock & MBB ) const { assert ( & MF . front ( ) == & MBB && ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; auto * RVFI = MF . getInfo < MachineFunctionInfo > ( ) ; MachineBasicBlock :: iterator MBBI = MBB . begin ( ) ; const InstrInfo * TII = ST" LLVM,RISCV,1095,"adjustReg(MBB, MBBI, DL, SPReg, SPReg, StackSize);" LLVM,RISCV,1096, LLVM,RISCV,1097,return true; LLVM,RISCV,1098,bool FrameLowering :: shouldEnableVectorUnit ( MachineFunction & MF ) const { LLVM,RISCV,1099,return MFI.hasBP() || TRI->hasBP(); LLVM,RISCV,1100, LLVM,RISCV,1101, LLVM,RISCV,1102, LLVM,RISCV,1103, LLVM,RISCV,1104, LLVM,RISCV,1105, LLVM,RISCV,1106,for (const auto &Entry : CSI) { LLVM,RISCV,1107, LLVM,RISCV,1108, LLVM,RISCV,1109,else { LLVM,RISCV,1110,case : LLVM,RISCV,1111,"static SmallVector < CalleeSavedInfo , > getNonLibcallCSI ( const std :: vector < CalleeSavedInfo > & CSI ) { SmallVector < CalleeSavedInfo , > NonLibcallCSI ; for ( auto & CS : CSI ) if ( CS . getFrameIdx ( ) >= ) NonLibcallCSI . push_back ( CS ) ; return NonLibcallCSI ; }" LLVM,RISCV,1112,return NonLibcallCSI; LLVM,RISCV,1113,return MFI.hasVarSizedObjects() && TRI->needsStackRealignment(); LLVM,RISCV,1114,return MFI.hasBasePointer(TRI); LLVM,RISCV,1115,|| MFI.hasFP(); LLVM,RISCV,1116,return !MF.getFrameInfo().hasVarSizedObjects(); LLVM,RISCV,1117,bool FrameLowering::hasReservedCallFrame(const MachineFunction &MF) { LLVM,RISCV,1118,RS->addScavengingFrameIndex(RegScavFI); LLVM,RISCV,1119,const TargetRegisterClass * RC = & ; if ( ! isInt < > ( MFI . estimateStackSize ( MF ) ) ) { int RegScavFI = MFI . CreateStackObject ( RegInfo -> getSpillSize ( * LLVM,RISCV,1120,"TII.loadRegFromStackSlot(MBB, MI, Reg, CS.getFrameIdx(), RC, TRI);" LLVM,RISCV,1121,"bool FrameLowering::spillCalleeSavedRegisters(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, ArrayRef CSI, const TargetRegisterInfo *TRI) const {" LLVM,RISCV,1122, LLVM,RISCV,1123,"for (unsigned i = 0, e = GEP->getNumOperands(); i != e; ++i, ++GTI) {" LLVM,RISCV,1124,assert ( StridedAddrs [ GEP ] == P && ) ; LLVM,RISCV,1125,for (auto *II : Scatters) LLVM,RISCV,1126,FunctionPass * llvm :: createGatherScatterLoweringPass ( ) { return new GatherScatterLowering ( ); } LLVM,RISCV,1127,return new GatherScatterLowering(); LLVM,RISCV,1128,AU . addRequired < LoopInfoWrapperPass > ( ) ; LLVM,RISCV,1129,"{ return ""My Pass""; }" LLVM,RISCV,1130,return false; LLVM,RISCV,1131,"return std::make_pair(Stride, Prev);" LLVM,RISCV,1132,return false; LLVM,RISCV,1133,"static std :: pair < Value * , Value * > matchStridedStart ( Value * Start , IRBuilder < > & Builder ) { auto * StartC = dyn_cast < Constant > ( Start ) ; if ( StartC ) return matchStridedConstant ( StartC ) ; auto * BO = dyn_cast < BinaryOperator > ( Start ) ; if ( ! BO || BO -> getOpcode ( ) != Instruction :: Add ) return std :: make_pair ( nullptr , nullptr ) ; unsigned OtherIndex = " LLVM,RISCV,1134,getType ( ) ) ) { Scatters . push_back ( II ) ; } } } LLVM,RISCV,1135,return true; LLVM,RISCV,1136,Call -> takeName ( II ) ; LLVM,RISCV,1137,if (InstrInfo.StoreOp && VLMul == InstrInfo.VLMul && SEW == InstrInfo.SEW) return true; LLVM,RISCV,1138,assert ( isValid ( ) && ) ; if ( ! Other . isValid ( ) ) { LLVM,RISCV,1139,if ( CurInfo . isCompatible ( Require ) ) return false ; if ( ! CurInfo . isUnknown ( ) && Require . hasAVLReg ( ) && Require . getAVLReg ( ) . isVirtual ( ) && ! CurInfo . hasSEWLMULRatioOnly ( ) && Require . hasSameVTYPE ( CurInfo ) ) { if ( MachineInstr * DefMI = MRI -> getVRegDef ( Require . getAVLReg ( ) ) ) { if ( DefMI -> getOpcode ( ) == LLVM,RISCV,1140, LLVM,RISCV,1141,return InstrInfo; LLVM,RISCV,1142,PrevVSETVLIMI = nullptr; LLVM,RISCV,1143,Register AVLReg = Require.getAVLReg(); LLVM,RISCV,1144,InstrInfo.setAVLReg(); LLVM,RISCV,1145,false ; LLVM,RISCV,1146,return false; LLVM,RISCV,1147, LLVM,RISCV,1148,"This completes the last statement of the code snippet, which checks if the `m_policy` member variable of the current object is equal to the `m_policy` member variable of the `Other` object." LLVM,RISCV,1149,bool hasSameSEW ( const VSETVLIInfo & Other ) const { LLVM,RISCV,1150, LLVM,RISCV,1151,return MI.getOpcode() == || MI.getOpcode() == || MI.getOpcode() == ; LLVM,RISCV,1152, LLVM,RISCV,1153, LLVM,RISCV,1154,") ; } while ( ! WorkList . empty ( ) ) { MachineBasicBlock * MBB = WorkList . pop ( ) ; for ( MachineBasicBlock :: iterator II = MBB - > begin ( ) ; II != MBB - > end ( ) ; ++ II ) { MachineInstr & MI = * II ; if ( MI . getOpcode ( ) == VSET_VLI ) { const MachineInstr * VLMI = MI . getOperand ( 0 ) . getInstr ( ) ; assert ( VLMI && """ LLVM,RISCV,1155,PrevVSETVLIMI = nullptr; LLVM,RISCV,1156, LLVM,RISCV,1157,if (SEWLMULRatioOnly) return false; LLVM,RISCV,1158, LLVM,RISCV,1159, LLVM,RISCV,1160,TailAgnostic = false ; LLVM,RISCV,1161,return TailAgnostic == InstrInfo.TailAgnostic && MaskAgnostic == InstrInfo.MaskAgnostic; LLVM,RISCV,1162,return true; LLVM,RISCV,1163,"void setVTYPE ( L , unsigned S , bool TA ) void setVTYPE ( L , unsigned S , bool TA )" LLVM,RISCV,1164,InInfo.isValid() LLVM,RISCV,1165,else { LLVM,RISCV,1166,InstrInfo.setAVLImm(Imm); LLVM,RISCV,1167,if (MI.isCall() || MI.isInlineAsm() || MI.readsRegister()) LLVM,RISCV,1168,"CurInfo = computeInfoForInstr(MI, TSFlags, MRI);" LLVM,RISCV,1169,"LLVM_DEBUG(dbgs() << ""Updating exit block info for "" << MBB.getName() << "" from "" << OldInfo << "" to "" << AvailableInfo << ""\n"");" LLVM,RISCV,1170,VSETVLIInfo AvailableInfo ; for ( MachineBasicBlock * P : MBB . predecessors ( ) ) { const VSETVLIInfo & PredInfo = BlockInfo [ P -> getNumber ( ) ] . Exit ; if ( PredInfo . isUnknown ( ) ) { if ( UnavailablePred ) return ; UnavailablePred = P ; } else if ( ! AvailableInfo . isValid ( ) ) { AvailableInfo = PredInfo ; } else if ( AvailableInfo != PredInfo ) { return ; } } if ( ! UnavailablePred || ! AvailableInfo . isValid LLVM,RISCV,1171,if (UseStrictAsserts && CurInfo.isValid()) LLVM,RISCV,1172,return ( MI . getDesc ( ) LLVM,RISCV,1173,return ( MI . getDesc() ); LLVM,RISCV,1174, LLVM,RISCV,1175,Require.MaskAgnostic; return Require.MaskAgnostic; LLVM,RISCV,1176, LLVM,RISCV,1177,"static bool hasFixedResult ( const VSETVLIInfo & Info , const Subtarget & ST ) { if ( ! Info . hasAVLImm ( ) ) return == Info . getAVLReg ( ) ; unsigned AVL = Info . getAVLImm ( ) ; return AVL == Info . getAVLReg ( ) ; }" LLVM,RISCV,1178, LLVM,RISCV,1179,return false; LLVM,RISCV,1180,if ( ! hasSameAVL ( Require ) ) return false ; if ( ! Require . StoreOp && ( TailAgnostic != Require . TailAgnostic || MaskAgnostic != Require . MaskAgnostic ) ) return false ; LLVM,RISCV,1181,assert ( == MI . getOperand ( ) . getReg ( ) ) ; return == MI . getOperand ( ) . getReg ( ); LLVM,RISCV,1182,static bool isVLPreservingConfig ( const MachineInstr & MI ) { if ( MI . getOpcode ( ) != ) return false ; assert ( == MI . getOperand ( ) . getImm ( ) ) ; return true ; } LLVM,RISCV,1183,OS << << ( bool ) StoreOp; LLVM,RISCV,1184,"assert ( BlockInfo . empty ( ) && ""BlockInfo is not empty"" ) ; BlockInfo . resize ( MF . getNumBlockIDs ( ) ) ; for ( MachineBasicBlock & MBB : MF ) doLocalPrepass ( MBB ) ; bool HaveVectorOp = false ; for ( const MachineBasicBlock & MBB : MF ) { HaveVectorOp |= computeVLVTYPEChanges ( MBB ) ; BlockData & BBInfo = BlockInfo [ MBB . getNumber ( ) ] ;" LLVM,RISCV,1185,return InstrInfo; LLVM,RISCV,1186, LLVM,RISCV,1187,"return std::tie(VLMul, SEW, TailAgnostic, MaskAgnostic) == std::tie(Other.VLMul, Other.SEW, Other.TailAgnostic, Other.MaskAgnostic);" LLVM,RISCV,1188,bool hasSameVTYPE ( const VSETVLIInfo & Other ) const { LLVM,RISCV,1189,"BuildMI ( MBB , MI , DL , TII -> get ( ) ) . addReg ( DestReg , RegState :: Define | RegState :: Dead ) . addReg ( , RegState :: Kill )" LLVM,RISCV,1190, LLVM,RISCV,1191,if (hasAVLImm() != Other.hasAVLImm()) return false; LLVM,RISCV,1192,"void setVTYPE ( L , unsigned S , bool TA , bool MA ) { assert ( isValid ( ) && ! isUnknown ( ) && ) ; VLMul = S; }" LLVM,RISCV,1193,BBInfo.Change = LLVM,RISCV,1194,"return ; } if ( Info . hasAVLImm ( ) ) { BuildMI ( MBB , MI , DL , TII -> get ( ) ) . addReg ( , RegState :: Define | RegState :: Dead ) . addImm ( Info . getAVLImm ( ) ) . addImm ( Info . encodeVTYPE ( ) ) ; return ; } Register AVLReg = Info . getAVLReg ( ) ; if ( AVLReg == ) { if ( PrevInfo" LLVM,RISCV,1195,if ( MachineInstr * DefMI = MRI -> getVRegDef ( Require . getAVLReg ( ) ) ) { if ( DefMI -> getOpcode ( ) == || DefMI -> getOpcode ( ) == ) { VSETVLIInfo DefInfo = getInfoForVSETVLI ( * DefMI ) ; if ( DefInfo . hasSameAVL ( CurInfo ) && DefInfo . LLVM,RISCV,1196,Register InReg = PHI->getOperand(PHIOp).getReg(); LLVM,RISCV,1197,return InstrInfo; LLVM,RISCV,1198, LLVM,RISCV,1199,VSETVLIInfo InInfo; LLVM,RISCV,1200, LLVM,RISCV,1201,"if ((TSFlags)) { HadVectorOp = true; VSETVLIInfo NewInfo = computeInfoForInstr(MI, TSFlags, MRI); if (!BBInfo.Change.isValid()) { BBInfo.Change = NewInfo; } }" LLVM,RISCV,1202,FunctionPass * llvm :: createInsertVSETVLIPass ( ) { return new InsertVSETVLI ( ) ; } LLVM,RISCV,1203,"static MachineInstr * elideCopies ( MachineInstr * MI , const MachineRegisterInfo * MRI ) { while ( true ) { if ( ! MI -> isFullCopy ( ) ) return MI; } }" LLVM,RISCV,1204,PrevVSETVLIMI = nullptr; LLVM,RISCV,1205,if ( MI . getOpcode ( ) == || MI . getOpcode ( ) == || MI . getOpcode ( ) == ) { assert ( MI . getOperand ( ) . getReg ( ) == && MI . getOperand ( ) . getReg ( ) == && ) ; MI . getOperand ( VType :: encodeVTYPE ( VLMul , SEW , TailAgnostic , VLMax );" LLVM,RISCV,1207,return NewInfo; LLVM,RISCV,1208,isEmpty ( ) ); return (unsigned) (getSEW ( ) / getLMUL ( )); } LLVM,RISCV,1209,static VSETVLIInfo getUnknown() { LLVM,RISCV,1210,bool hasAVLReg (int reg) { return (reg >= 0 && reg <= 31); } LLVM,RISCV,1211,return false; LLVM,RISCV,1212,bool hasSameVLMAX ( const VSETVLIInfo & Other ) const { LLVM,RISCV,1213,"return std::tie(VLMul, SEW, TailAgnostic, MaskAgnostic) == std::tie(Other.VLMul, Other.SEW, Other.TailAgnostic, Other.MaskAgnostic);" LLVM,RISCV,1214,{ return m_hasSEWLMULRatioOnly; } LLVM,RISCV,1215, LLVM,RISCV,1216,return Other; LLVM,RISCV,1217, LLVM,RISCV,1218,assert ( EEW == InstrInfo . SEW && ) ; if ( isUnknown ( ) || hasSEWLMULRatioOnly ( ) ) return false ; if ( ! hasSameAVL ( InstrInfo ) ) return false ; if ( ! InstrInfo . StoreOp && ( TailAgnostic != InstrInfo . TailAgnostic || MaskAgnostic ) ) return false ; LLVM,RISCV,1219,bool isUnknown ( ) const { return State == State::Unknown; } LLVM,RISCV,1220,bool isUnknown ( ) const { return State == Unknown; } LLVM,RISCV,1221,bool isValid ( ) const { return State != State::Invalid; } LLVM,RISCV,1222,return State != State.Terminated; LLVM,RISCV,1223,return DefInfo.hasAVLReg() && DefInfo.getAVLReg().isVirtual(); LLVM,RISCV,1224,return true; LLVM,RISCV,1225,if ( ! PBBInfo . isInsertedVSETVLPHIOpt ( ) ) return true ; LLVM,RISCV,1226,MBB ) ; } } return true ; } LLVM,RISCV,1227,void setAVLImm(unsigned Imm[]) { LLVM,RISCV,1228,void setAVLImm ( unsigned Imm ) { AVLImm = Imm ; State = AVL_IMM; } Explanation: LLVM,RISCV,1229,AVLReg = Reg ; State = [AVLReg] ; LLVM,RISCV,1230,void setAVLReg ( Register Reg ) { AVLReg = Reg; } LLVM,RISCV,1231,State = [ LLVM,RISCV,1232, LLVM,RISCV,1233,"void InstPrinter :: printBDAddrOperand ( const MCInst * MI , int OpNum , raw_ostream & O ) { printAddress ( MI -> getOperand ( OpNum ) . getReg ( ) , MI -> getOperand ( OpNum + 1 ) . getImm ( ) ); }" LLVM,RISCV,1234,"&OStream) { const MCOperand &MO = MI->getOperand(OpNum); if (MO.isReg()) { OStream << getRegisterName(MO.getReg()); } else { OStream << ""0x"" << formatHex(MO.getImm()); } }" LLVM,RISCV,1235,"&OStream) { const MCOperand &MO = MI->getOperand(OpNum); if (MO.isReg()) { OStream << getRegisterName(MO.getReg()); } else { OStream << ""0x"" << formatHex(MO.getImm()); } }" LLVM,RISCV,1236,"void InstPrinter :: printBDXAddrOperand ( const MCInst * MI , int OpNum , raw_ostream & O ) { printAddress ( MI -> getOperand ( OpNum ) . getReg ( ) , MI -> getOperand ( OpNum ) . getImm ( ) , O ); }" LLVM,RISCV,1237,"printOperand ( MI , MI->getOperand ( 0 ) );" LLVM,RISCV,1238," , , , , , , , , " LLVM,RISCV,1239,O << CondNames[Imm - ]; LLVM,RISCV,1240,; } LLVM,RISCV,1241,OS << getRegisterName ( MI -> getOperand ( opNum + ) . getReg () ); LLVM,RISCV,1242,OS << getRegisterName ( M LLVM,RISCV,1243,"uint8_t reg = MI->getOperand(opNum).getReg(); uint8_t isSrc = MI->getOperand(opNum).isSrcReg(); uint8_t isDst = MI->getOperand(opNum).isDstReg(); if (isSrc) { OS << ""src:""; } else if (isDst) { OS << ""dst:""; } OS << ""r"" << (int)reg; if (MI->getOperand(" LLVM,RISCV,1244,OS << getRegisterName(MI->getOperand(opNum).getReg()); LLVM,RISCV,1245,RegNo ); } LLVM,RISCV,1246,O << getRegisterName(RegNo); LLVM,RISCV,1247,int64_t Value = MI -> getOperand ( OpNum ) . getImm ( ); LLVM,RISCV,1248,":: printS20ImmOperand ( const MCInst * MI , int OpNum , raw_ostream & O ) { if ( MI -> getOperand ( OpNum ) . isImm ( ) ) { int64_t Value = MI -> getOperand ( OpNum ) . getImm ( ) ; assert ( isInt < > ( Value ) && ) ; O << Value ; } }" LLVM,RISCV,1249, LLVM,RISCV,1250,int64_t Value = MI->getOperand(OpNum).getImm(); assert(isUInt(Value)); LLVM,RISCV,1251,"O << ""0""; } else printOperand ( MI , OpNum , O ); }" LLVM,RISCV,1252,assert(isUInt(Value)); LLVM,RISCV,1253, LLVM,RISCV,1254,"(Value) && ""Immediate operand value out of range"");" LLVM,RISCV,1255, LLVM,RISCV,1256, LLVM,RISCV,1257, LLVM,RISCV,1258,assert(MO.isImm() && ); LLVM,RISCV,1259,"printAnnotation(O, Annot);" LLVM,RISCV,1260, LLVM,RISCV,1261,"void InstPrinter :: printSpecialCapRegister ( const MCInst * MI , unsigned OpNo , const MCSubtargetInfo & STI , raw_ostream & O ) { unsigned Imm = MI -> getOperand ( OpNo ) . getImm ( ) ; auto SpecialCapReg = ( Imm ) ; O << SpecialCapReg ; }" LLVM,RISCV,1262,O << Imm; LLVM,RISCV,1263,if ( Opt == ) { NoAliases = true ; return true ; } if ( Opt == ) { ArchRegNames = [/INST] if ( Opt == ) { NoAliases = true ; return true ; } if ( Opt == ) { ArchRegNames = [/INST] if ( Opt == ) { NoAliases = true ; return true ; } if ( Opt == ) { ArchRegNames = LLVM,RISCV,1264, LLVM,RISCV,1265, LLVM,RISCV,1266,"bool uncompressInst(MCInst& UncompressedMI, const MCInst& MI, bool NoAliases)" LLVM,RISCV,1267,; } LLVM,RISCV,1268,"if (NoAliases || !printAliasInstr(NewMI, STI, O))" LLVM,RISCV,1269,getReg ( ) ) ; return ; } } LLVM,RISCV,1270,"void InstPrinter::printVTypeImm(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O) { unsigned Imm = MI->getOperand(OpNo).getImm(); unsigned Ediv = (Imm >> 13) & 7; unsigned Sew = (Imm >> 10) & 7; unsigned Lmul = Imm & 7; Sew = 1 << (Sew + 3); Lmul = 1" LLVM,RISCV,1271, LLVM,RISCV,1272,"if (NoAliases || !printAliasInstr(MI, O))" LLVM,RISCV,1273, LLVM,RISCV,1274,if (MC.isReg()) O << getRegisterName(MC.getReg()); LLVM,RISCV,1275,"else llvm_unreachable(""Unexpected machine code"");" LLVM,RISCV,1276,"O << ""i"" << Value; } else printOperand ( MI , OpNum , O ); }" LLVM,RISCV,1277, LLVM,RISCV,1278,; } } LLVM,RISCV,1279,O << Value; LLVM,RISCV,1280,"""0x"" << hex << Value << dec;" LLVM,RISCV,1281,"""0x"" << hex << Value << dec;" LLVM,RISCV,1282, LLVM,RISCV,1283,if ( ( FenceArg & LLVM,RISCV,1284,if (Res) LLVM,RISCV,1285,"if ( NoAliases || ! printAliasInstr ( MI , STI , O ) ) printInstruction ( MI , STI , O ) ; printAnnotation ( O , Annot ) ;" LLVM,RISCV,1286,"if (NoAliases || !printAliasInstr(MI, STI, O))" LLVM,RISCV,1287,return false; } LLVM,RISCV,1288,"return getRegisterName(RegNo, ArchRegNames ? : );" LLVM,RISCV,1289, LLVM,RISCV,1290,auto SysReg = ( Imm ) ; LLVM,RISCV,1291, LLVM,RISCV,1292, LLVM,RISCV,1293,auto FRMArg = static_cast(MI->getOperand(OpNo).getImm()); LLVM,RISCV,1294,NewMI = const_cast (UncompressedMI); LLVM,RISCV,1295,"printInstruction(NewMI, Address, O);" LLVM,RISCV,1296,"( ) ; return ; } if ( MO . isFPImm ( ) ) { O << MO . getFPImm ( ) ; return ; } if ( MO . isExpr ( ) ) { O << MO . getExpr ( ) ; return ; } O << ""?"" ; }" LLVM,RISCV,1297, LLVM,RISCV,1298,return MIB.addImm(Offset).addFrameIndex(FI); LLVM,RISCV,1299,assert(TBB); LLVM,RISCV,1300, LLVM,RISCV,1301,return false; } LLVM,RISCV,1302, LLVM,RISCV,1303,"unsigned InstrInfo :: getOpcodeForOffset ( unsigned Opcode , int64_t Offset ) const { int64_t Offset2 = Offset ; if ( isInt < > ( Offset ) && isInt < <" LLVM,RISCV,1304,"case | : BuildMI ( MBB , I , DL , get ( ) ) . addMBB ( TBB ) . addReg ( Cond [ ] . getReg ( ) ) . addReg ( Cond [" LLVM,RISCV,1305, LLVM,RISCV,1306,case : case : Cond[].setImm( | ); Target = &MI->getOperand(); return true; LLVM,RISCV,1307,"unsigned InstrInfo :: isLoadFromStackSlot ( const MachineInstr * MI , int & FrameIndex ) const { return isSimpleMove ( MI , FrameIndex , SP ); }" LLVM,RISCV,1308,To LLVM,RISCV,1309,"return isSimpleMove(MI, MI.getOperand(0).getReg());" LLVM,RISCV,1310,"Next, the function checks if the immediate value is an integer within a certain range (the specific range is" LLVM,RISCV,1311, LLVM,RISCV,1312,const MachineOperand * Target ; LLVM,RISCV,1313, LLVM,RISCV,1314,if ( getMemOperandWith LLVM,RISCV,1315,return LowOffset + WidthA <= HighOffset; LLVM,RISCV,1316, LLVM,RISCV,1317, LLVM,RISCV,1318,I = NF - 1; LLVM,RISCV,1319,"std::pair myPair(1, 2);" LLVM,RISCV,1320,"mov eax, DstReg" LLVM,RISCV,1321,int NumOp = MI . getNumExplicitOperands ( ) ; return MI . getOperand ( NumOp - 1 ) ; LLVM,RISCV,1322,"NF [/NUM_LIT] + ) ; } default : llvm_unreachable ( ""Unknown opcode"" ) ; } }" LLVM,RISCV,1323, LLVM,RISCV,1324,if (RepeatedSequenceLocs.size() < NUM_LIT) return outliner::OutlinedFunction; LLVM,RISCV,1325,"ArrayRef < std :: pair < unsigned , const char * >> InstrInfo :: getSerializableDirectMachineOperandTargetFlags ( ) const { using namespace II ; static const std :: pair < unsigned , const char * > TargetFlags [ ] = { { MO_CALL , } , { MO_PLT , } , { MO_LO , } , { MO_HI , } , { MO_PCREL_" LLVM,RISCV,1326, LLVM,RISCV,1327,return CondMI; LLVM,RISCV,1328,RS->enterBasicBlockEnd(MBB); LLVM,RISCV,1329,"It = MBB.insert(It, BuildMI(MF, DebugLoc(), get(), ).addGlobalAddress(M.getNamedValue(MF.getName())));" LLVM,RISCV,1330, LLVM,RISCV,1331, LLVM,RISCV,1332, LLVM,RISCV,1333,return true; LLVM,RISCV,1334,return true; LLVM,RISCV,1335, LLVM,RISCV,1336,return true; LLVM,RISCV,1337,"bool InstrInfo::isRVVSpill(const MachineInstr &MI, bool CheckFIs) const {" LLVM,RISCV,1338,switch (input) { LLVM,RISCV,1339, LLVM,RISCV,1340,"unsigned InstrInfo :: isStoreToStackSlot ( const MachineInstr & MI , int & FrameIndex ) const { switch ( MI . getOpcode ( ) ) { default : return false ; case : case : case : case : case : case : case : break ; } if ( MI . getOperand ( ) . isFI ( ) && MI" LLVM,RISCV,1341,else llvm_unreachable ( ) ; LLVM,RISCV,1342,"static void parseCondBranch ( MachineInstr & LastInst , MachineBasicBlock * & Target , SmallVectorImpl < MachineOperand > & Cond ) { assert ( LastInst . getDesc ( ) . isConditionalBranch ( ) );" LLVM,RISCV,1343,return ; LLVM,RISCV,1344,auto CC = static_cast < > ( Cond [ ] . getImm ( ) ) ; Cond [ ] . setImm ( getOppositeBranchCondition ( CC ) ) ; LLVM,RISCV,1345, LLVM,RISCV,1346,return get(Opcode).getSize(); LLVM,RISCV,1347,unsigned FrameOverhead = ; LLVM,RISCV,1348,return outliner::InstrType::Illegal; LLVM,RISCV,1349, LLVM,RISCV,1350,auto II = MBB.end(); LLVM,RISCV,1351,case : LLVM,RISCV,1352, LLVM,RISCV,1353,return MI->getOperand()->getReg(); LLVM,RISCV,1354, LLVM,RISCV,1355,Register SrcReg = ; LLVM,RISCV,1356, LLVM,RISCV,1357,"void InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, Register SrcReg, bool IsKill, int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const { DebugLoc DL; if (I != MBB.end()) DL = I->getDebugLoc(); unsigned Opcode; if (.hasSubClassEq(RC)) Opcode = TRI->getRegSizeInBits(isCallOrInvoke()) { if (MI->getCalleeFunction()->hasFnAttr(Attribute::NoUnwind)) { return true; } } if (MI->isLoadOrStore()) { LLVM,RISCV,1367, LLVM,RISCV,1368,"LuiMI.addMBB(DestBB, ""branch"");" LLVM,RISCV,1369, LLVM,RISCV,1370, LLVM,RISCV,1371, LLVM,RISCV,1372,"void InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned DstReg, int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const { DebugLoc DL = I->getDebugLoc(); }" LLVM,RISCV,1373,"if ( . hasSubClassEq ( RC ) ) BuildMI ( MBB , I , DL , get ( ) );" LLVM,RISCV,1374, LLVM,RISCV,1375,"void InstrInfo :: storeRegToStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned SrcReg , bool IsKill , int StackSlot ) void InstrInfo :: storeRegTo" LLVM,RISCV,1376,:: CALL : case TargetOpcode :: INLINEASM : return ; } } } LLVM,RISCV,1377, LLVM,RISCV,1378,Opcode = TRI -> getRegSizeInBits ( ) == ? : ; LLVM,RISCV,1379, LLVM,RISCV,1380,"void InstrInfo :: insertIndirectBranch ( MachineBasicBlock & MBB , MachineBasicBlock & DestBB , MachineBasicBlock & RestoreBB , const DebugLoc & DL , int64_t BrOffset , RegScavenger * RS ) const { assert ( RS && ) ; assert ( MBB . empty ( ) && ) ; assert ( MBB . pred_size ( ) == ) ; MachineFunction * MF = MBB . getParent ( )" LLVM,RISCV,1381,"if ( MI . getOperand ( ) . isReg ( ) && MI . getOperand ( ) . isReg ( ) && MI . getOperand ( ) . getReg ( ) == MI . getOperand ( ) . getReg ( ) ) return DestSourcePair { MI . getOperand ( ) . getReg ( ), MI . getOperand ( ) . getReg ( ) };" LLVM,RISCV,1382,"Kill ) . addReg ( SrcReg , RegState :: Kill ) . setMIFlag ( Flag ) ; }" LLVM,RISCV,1383,"Opc , DstReg , SrcReg , NF , LMul , IsScalableVector , UseVMV_V_V , UseVMV_V_I ) ; return MIB ; } else { llvm_unreachable ( ) ; } }" LLVM,RISCV,1384, LLVM,RISCV,1385,return outliner::InstrType::Illegal; LLVM,RISCV,1386,return outliner::InstrType::Illegal; LLVM,RISCV,1387,return; LLVM,RISCV,1388, LLVM,RISCV,1389,return MF.getFunction LLVM,RISCV,1390,bool InstrInfo :: shouldOutlineFromFunctionByDefault ( MachineFunction & MF ) const { return MF . getFunction ( ) . hasMinSize ( ) ; } LLVM,RISCV,1391,isVector = true ; } else if ( . hasSubClassEq ( RC ) ) { Opcode = ; isVector = true ; } else if ( . hasSubClassEq ( RC ) ) { Opcode = ; isVector = true ; } else llvm_unreachable ( ) ; if LLVM,RISCV,1392,RVFI->setOpcode(Opcode); LLVM,RISCV,1393, LLVM,RISCV,1394,getImm ( ) ; } } } return None ; } LLVM,RISCV,1395,if ( Reg == ) return ; if ( Reg . isVirtual ( ) ) { auto * Def = MRI . getUniqueVRegDef ( Reg ) ; switch ( Def -> getOpcode ( ) ) { default : return None ; case > InstrInfo :: getSerializableDirectMachineOperandTargetFlags ( ) const { using namespace II ; static const std :: pair < unsigned , const char * > TargetFlags [ ] = { { MO_CALL , } , { MO_PLT , } , { MO_LO , } , { MO_HI , } , { MO_PCREL_" LLVM,RISCV,1398,return MI; LLVM,RISCV,1399,"TBB ) ; } else { MachineInstr & MI = * BuildMI ( & MBB , DL , get ( PseudoOpcode ) ) . addImm ( Cond [ 0 ] ) ; if ( Cond . size ( ) == ) MI . addImm ( Cond [ 1 ] ) ; } return & MI ; }" LLVM,RISCV,1400, LLVM,RISCV,1401,case : case : case : return MI . getOperand ( ) . isReg ( ) && MI . getOperand ( ) . isReg ( ) && MI . getOperand ( ) . getReg ( ) == MI . getOperand ( ) . getReg ( ) ; LLVM,RISCV,1402, LLVM,RISCV,1403,"switch ( BranchOp ) { default : llvm_unreachable ( ""Invalid branch opcode"" ) ; case : case : case : case : case <" LLVM,RISCV,1404,switch (MI.getOpcode()) { LLVM,RISCV,1405, LLVM,RISCV,1406, LLVM,RISCV,1407,if (.hasSubClassEq(RC)) { LLVM,RISCV,1408,Opcode = ; IsZvlsseg = false ; } else { llvm_unreachable ( ) ; } } } LLVM,RISCV,1409,return ; LLVM,RISCV,1410, LLVM,RISCV,1411,"if ( NumTerminators == && std :: prev ( I ) -> getDesc ( ) . isConditionalBranch ( ) && I -> getDesc ( ) . isUnconditionalBranch ( ) ) { parseCondBranch ( * std :: prev ( I ) , TBB , Cond ) ; FBB = getBranchDestBlock ( * I ) ; return false ; }" LLVM,RISCV,1412, LLVM,RISCV,1413,return false; LLVM,RISCV,1414, LLVM,RISCV,1415,"llvm_unreachable("""");" LLVM,RISCV,1416,return MI.getOperand().getReg(); LLVM,RISCV,1417,"InstrInfo :: isLoadFromStackSlot ( const MachineInstr & MI , int & FrameIndex ) const { switch ( MI . getOpcode ( ) ) { default : return false ; case : case : case : case : case : case : case : case : case : case : break ; } if" LLVM,RISCV,1418,``` LLVM,RISCV,1419, LLVM,RISCV,1420, LLVM,RISCV,1421,if ( I != MBB.end() ) DL = I->getDebugLoc(); LLVM,RISCV,1422,"void InstrInfo :: storeRegToStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned SrcReg , bool IsKill , int FI , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { DebugLoc DL ; if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ;" LLVM,RISCV,1423,"RS->scavengeRegisterBackwards(, LuiMI, );" LLVM,RISCV,1424, LLVM,RISCV,1425,int64_t NumOfVReg = Amount / ; LLVM,RISCV,1426,if (.hasSubClassEq(RC)) { LLVM,RISCV,1427,"BuildMI(MBB, I, DL, get(Opcode), DstReg).addFrameIndex(FI);" LLVM,RISCV,1428, LLVM,RISCV,1429,if (.hasSubClassEq(RC)) { LLVM,RISCV,1430,SrcReg = Inst.SrcReg; LLVM,RISCV,1431, LLVM,RISCV,1432,} case TargetOpcode :: EH_LABEL : case TargetOpcode :: IMPLICIT_DEF : case TargetOpcode :: KILL : case TargetOpcode :: DBG_VALUE : return ; case : case getMBB(); LLVM,RISCV,1434, LLVM,RISCV,1435,return false; LLVM,RISCV,1436, LLVM,RISCV,1437, LLVM,RISCV,1438, LLVM,RISCV,1439,"case | : BuildMI ( MBB , I , DL , get ( ) ) . addMBB ( TBB ) . addReg ( Cond [ ] . getReg ( ) ) . addReg ( Cond [ ] . getReg ( ) ) ; break ;" LLVM,RISCV,1440, LLVM,RISCV,1441,unsigned InstrInfo :: isLoadFromStackSlot ( const MachineInstr &MI) const { if (MI.getOpcode() == TargetOpcode::LOAD) { const MachineOperand &Src = MI.getOperand(0); if (Src.isStackSlot()) { return Src.getStackSlot().getSlotNumber(); } } return -1; } LLVM,RISCV,1442,"unsigned InstrInfo :: isStoreToStackSlot ( const MachineInstr & MI , int & FrameIndex ) const { return isSimpleMove ( MI , FrameIndex , ""STACK_SLOT"" ); }" LLVM,RISCV,1443,"unsigned InstrInfo :: isStoreToStackSlot ( const MachineInstr &MI, int &SlotIndex) {" LLVM,RISCV,1444,switch (expression) { LLVM,RISCV,1445, LLVM,RISCV,1446,const MachineOperand *ThisTarget; LLVM,RISCV,1447,"void InstrInfo :: loadRegFromStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned DstReg , int FI , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { DebugLoc DL ; if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ;" LLVM,RISCV,1448,"BuildMI(MBB, I, DL, get(Opcode), DstReg);" LLVM,RISCV,1449, LLVM,RISCV,1450, LLVM,RISCV,1451, LLVM,RISCV,1452,return MI; LLVM,RISCV,1453, LLVM,RISCV,1454, LLVM,RISCV,1455,"BuildMI(MBB, MBBI, DL, get(STR_LIT), DstReg)" LLVM,RISCV,1456,Target = LastInst . getOperand ( ) . getMBB ( ) ; Cond . push_back ( MachineOperand :: CreateImm ( LastInst . getOpcode ( ) ) ) ; Cond . push_back ( LastInst . getOperand ( ) ) ; LLVM,RISCV,1457,"Next, the function iterates over the instructions in the basic block, starting from" LLVM,RISCV,1458,It's LLVM,RISCV,1459, LLVM,RISCV,1460,return false; LLVM,RISCV,1461, LLVM,RISCV,1462, LLVM,RISCV,1463,); } LLVM,RISCV,1464,static const char * getName ( ) { return DEBUG_TYPE; } LLVM,RISCV,1465,"return false; } Next, the method calls the `" LLVM,RISCV,1466,"return new ISelDag(TM, CodeGenOpt);" LLVM,RISCV,1467, LLVM,RISCV,1468,"return expandOffset(AM, IsBase, Op0, cast(Op1));" LLVM,RISCV,1469,AM.Offset = TestOffset; LLVM,RISCV,1470,"Base = AM . Base ; if ( ! Base . getNode ( ) ) Base = CurDAG -> getRegister ( , VT ) ; else if ( Base . getOpcode" LLVM,RISCV,1471,"return CurDAG -> getTargetConstant ( Imm , DL , CurDAG -> getDataLayout ());" LLVM,RISCV,1472, LLVM,RISCV,1473,"static bool isValidOffset ( OffR , int66_t Val ) { assert ( selectOffset ( OffR , Val ) && ( Val >= 0 && Val < OffR.size ( ) ) ); }" LLVM,RISCV,1474,void DAGToDAGISel::processFunctionAfterISel(Function &F) { } LLVM,RISCV,1475,return ret; LLVM,RISCV,1476,runOnMachineFunction(MF); LLVM,RISCV,1477,"Inside the `case` statement for the `STR_LIT` value, the code creates a new `SDValue`" LLVM,RISCV,1478,"if (Addr.getOpcode() == && expandOffset(AM, true, SDValue(), cast)) {" LLVM,RISCV,1479,return false; LLVM,RISCV,1480, LLVM,RISCV,1481, LLVM,RISCV,1482,"bool selectRegAddr ( SDValue Addr , SDValue & Base ) { Base = Addr; }" LLVM,RISCV,1483, LLVM,RISCV,1484, LLVM,RISCV,1485,"bool selectRVVSimm5 ( SDValue N , SDValue [" LLVM,RISCV,1486,"bool selectShiftMask32 ( SDValue N , SDValue & ShAmt ) { return selectShiftMask ( N , , 32 ); }" LLVM,RISCV,1487,"bool selectShiftMask32 ( SDValue N , SDValue & ShAmt ) {" LLVM,RISCV,1488, LLVM,RISCV,1489, LLVM,RISCV,1490,"( ) ; I < E ; I ++ ) { if ( I == MaskOpIdx || I == * TailPolicyOpIdx ) continue ; Ops . push_back ( N -> getOperand ( I ) ) ; } return DAG . getNode ( I -> UnmaskedPseudo , N . getVT ( ) , Ops , N . getLoc ( ) ) ; }" LLVM,RISCV,1491,bool hasAllHUsers (SDNode *node) { LLVM,RISCV,1492,"bool hasAllWUsers ( SDNode * Node ) const { return hasAllNBitUsers ( Node , Node->getNumUsers() ); }" LLVM,RISCV,1493, LLVM,RISCV,1494, LLVM,RISCV,1495, LLVM,RISCV,1496,"if ( C && isUInt < > ( C -> getZExtValue ( ) ) ) { VL = CurDAG -> getTargetConstant ( C -> getZExtValue ( ) , SDLoc ( N ) , N -> getValueType ( ) ) ; } else if ( C && C -> isAllOnesValue ( ) ) { VL = CurDAG -> getTargetConstant ( C -> getZExtValue ( ) , SDLoc ( N ) , N -> getValueType ( ) )" LLVM,RISCV,1497, LLVM,RISCV,1498,") ; Opcode = ; } else { VLOperand = CurDAG -> getRegister ( , XLenVT ) ; Opcode = ; } SDValue ChainOp = HasChain ? CurDAG -> getRegister ( , XLenVT ) : CurDAG -> getUNDEF ( XLenVT ) ; SDValue NewNode = CurDAG -> getNode ( Opcode , DL , VTs , { VTypeIOp , VLOperand ," LLVM,RISCV,1499, LLVM,RISCV,1500,return true; LLVM,RISCV,1501,return SplatVal; LLVM,RISCV,1502, LLVM,RISCV,1503, LLVM,RISCV,1504, LLVM,RISCV,1505, LLVM,RISCV,1506, LLVM,RISCV,1507, LLVM,RISCV,1508, LLVM,RISCV,1509,unsigned MaskOpIdx = I->MaskOpIdx; LLVM,RISCV,1510, LLVM,RISCV,1511, LLVM,RISCV,1512,"SDValue VTypeOp = CurDAG->getTargetConstant(VType, DL, XLenVT);" LLVM,RISCV,1513, LLVM,RISCV,1514, LLVM,RISCV,1515,assert ( isa < ConstantSDNode > ( N -> getOperand ( ) . getOperand ( ) ) ) ; LLVM,RISCV,1516, LLVM,RISCV,1517,"XLenVT , SrcReg , SDImm ) ; else Result = CurDAG -> getMachineNode ( , DL , SrcReg , SDImm ) ; } return Result ; }" LLVM,RISCV,1518,if (N.getOpcode() == && cast (N.getOperand()) -> getVT() .bitsLE()) { LLVM,RISCV,1519, LLVM,RISCV,1520,NF; LLVM,RISCV,1521, LLVM,RISCV,1522,Operands.push_back(StoreVal); LLVM,RISCV,1523,"ReplaceNode(Node, Store);" LLVM,RISCV,1524,Operands.push_back(StoreVal); LLVM,RISCV,1525, LLVM,RISCV,1526,"LLVM_DEBUG(dbgs() << ""New base: "");" LLVM,RISCV,1527,return false; LLVM,RISCV,1528,function doPeepholeLoadStoreADDI(instruction) { LLVM,RISCV,1529,"Base = CurDAG -> getTargetFrameIndex ( FIN -> getIndex ( ) , FIN -> getIndex ( ) );" LLVM,RISCV,1530," ) ; ReplaceNode ( Node , CurDAG -> getShiftLeft ( DL , VT , Op0 , CurDAG -> getConstant ( ShAmt , DL , MaskVT ) ) ) ; return ; } break ; } default : break ; } }" LLVM,RISCV,1531, LLVM,RISCV,1532,return false; LLVM,RISCV,1533,case : { LLVM,RISCV,1534,"( ) ; SDValue Op1 = Node -> getOperand ( ) ; if ( Op0 . getOpcode ( ) == && Op1 . getOpcode ( ) == ) { SDValue ShAmt = cast < ConstantSDNode > ( Op1 . getNode ( ) ) -> getZExtValue ( ) ; SDValue ShAmtVal = CurDAG -> getTargetConstant ( ShAmt , SDLoc ( Node ) , XLenVT ) ; CurDAG" LLVM,RISCV,1535,return true; LLVM,RISCV,1536,SDValue Or = N ; if ( Or . getOperand ( ) . getOpcode ( ) == ) { SDValue Srl = Or . getOperand ( ) ; if ( isa < ConstantSDNode > ( Srl . getOperand ( ) ) && isa < ConstantSDNode > ( Or . getOperand ( ) ) ) { uint32_t VC1 = Or LLVM,RISCV,1537,"Offset2 = GA->getGlobal()->getPointerOffset(DL); If (Offset1 + Offset2 < 0) continue; ImmOperand = CurDAG->getTargetConstant(Offset1 + Offset2, SDLoc(ImmOperand), ImmOperand.getValueType()); Base = GA->getGlobal(); break;" LLVM,RISCV,1538,void DAGToDAGISel::PostprocessISelDAG() { doPeepholeLoadStoreOffset(); } LLVM,RISCV,1539, LLVM,RISCV,1540, LLVM,RISCV,1541,return false; LLVM,RISCV,1542, LLVM,RISCV,1543, LLVM,RISCV,1544,"Base = CurDAG -> getTargetFrameIndex ( FIN -> getIndex ( ) , Subtarget -> typeForCapabilities ( ) ) ; return true ; } } return false ; }" LLVM,RISCV,1545,case : if (UI.getOperandNo() != || Bits < ) return false; break; LLVM,RISCV,1546,return true; LLVM,RISCV,1547, LLVM,RISCV,1548,LLVM_DEBUG ( dbgs ( ) << ) ; LLVM,RISCV,1549,"default: return ""default"";" LLVM,RISCV,1550,"return LMUL == ""LMUL"" ? ""LMUL"" + Index : ""RMUL"" + Index;" LLVM,RISCV,1551,assert ( N -> getOperand ( ) . getOpcode ( ) == ) ; assert ( isa < ConstantSDNode > ( N -> getOperand ( ) ) ) ; assert ( isa < ConstantSDNode > ( N -> getOperand ( ) . getOperand ( ) ) ) ; SDValue Shl = N -> getOperand ( ) ; if ( Subtarget -> is64Bit ( ) ) { uint LLVM,RISCV,1552, LLVM,RISCV,1553, ) ) ) ; LLVM,RISCV,1554,"ReplaceUses ( SDValue ( Node , NF ) , SDValue ( Load , ) ) ;" LLVM,RISCV,1555,DAGToDAGISel::selectVLSEGFFMask(SDNode *Node) { SDLoc DL(Node); unsigned IntNo = cast(Node->getOperand(2))->getZExtValue(); unsigned NF = Node->getNumValues() - 2; EVT VT = Node->getValueType(2); unsigned ScalarSize = VT.getScalarSizeInBits(); MVT XLenVT = Subtarget->getXLenVT(); );" LLVM,RISCV,1558, LLVM,RISCV,1559, LLVM,RISCV,1560,CurDAG->RemoveDeadNode(Node); LLVM,RISCV,1561, LLVM,RISCV,1562,"bool DAGToDAGISel :: selectVSplat ( SDValue N , SDValue & SplatVal ) { if ( N . getOpcode ( ) != && N . getOpcode ( ) != ) return false ; SplatVal = N . getOperand ( 0 ) ; return true ; }" LLVM,RISCV,1563,assert (XLenVT == N.getOperand().getSimpleValueType() && ); LLVM,RISCV,1564,"int64_t SplatImm = cast < ConstantSDNode > ( N . getOperand ( ) ) -> getSExtValue ( ) ; if ( ! isUInt < > ( SplatImm ) ) return false ; SplatVal = CurDAG -> getTargetConstant ( SplatImm , SDLoc ( N ) ) ;" LLVM,RISCV,1565, LLVM,RISCV,1566, LLVM,RISCV,1567,"SmallVector> Regs(Node->op_begin() + , Node->op_begin() + + NF);" LLVM,RISCV,1568, LLVM,RISCV,1569,"SDNode * Store = CurDAG->getMachineNode(P->Pseudo, DL, Node->getValueType(), Operands);" LLVM,RISCV,1570,"ReplaceNode(Node, Store);" LLVM,RISCV,1571,case : if (UI.getOperandNo() != || Bits < ) return false; break; LLVM,RISCV,1572,"bool DAGToDAGISel::hasAllNBitUsers(SDNode* Node, unsigned Bits) const { assert((Node->getOpcode() == ISD::BITCAST || Node->getOpcode() == ISD::TRUNCATE || Node->getOpcode() == ISD::SRL || Node->getOpcode() == ISD::SRA || Node->getOpcode() == ISD::SHL || Node->getOpcode() == ISD::ANY_EXTEND || isa) CurDAG->UpdateNodeOperands(N, Base.getOperand(), ImmOperand, N->getOperand());" LLVM,RISCV,1574,CurDAG->RemoveDeadNodes(); LLVM,RISCV,1575, LLVM,RISCV,1576,"1. Check the documentation for the `doPeepholeBuildPairF64SplitF64` function to see if it is a built-in function in the language you are using. If it is, you may need" LLVM,RISCV,1577,"XLenVT, TFI, Imm ) ) ; return ; } }" LLVM,RISCV,1578,if ( Node -> isMachineOpcode ( ) ) { LLVM_DEBUG ( dbgs ( ) << ; Node -> dump ( CurDAG ) ; dbgs ( ) << ) ; Node -> setNodeId ( - ) ; return ; } EVT VT = Node -> getValueType ( ) ; if ( Opcode == && VT == XLenVT ) { auto * ConstNode = cast < ConstantSDNode > ( Node ) ; if ( LLVM,RISCV,1579,Bits < ) return false ; break ; case : if ( UI . getOperandNo ( ) != || Bits < ) return false ; break ; case : if ( UI . getOperandNo ( ) != || Bits < ) return false ; break ; case : if ( UI . getOperandNo ( ) != || Bits < < LLVM,RISCV,1580,"Result = CurDAG->getMemIntrinsicNode(, DL, VTs, Ops, , MPI, Align(), MachineMemOperand::MOLoad);" LLVM,RISCV,1581, LLVM,RISCV,1582,"( Node ) , ) ; ReplaceNode ( Node , CurDAG -> getMachineNode ( , DL , VT , Op0 , ShAmtVal ) ) ; return ; } } break ; } case : { SDValue Op0 = Node -> getOperand ( ) ; SDValue Op1 = Node -> getOperand ( ) ; SDValue Op2 = Node -> getOperand ( ) ; SDValue ShAmt =" LLVM,RISCV,1583,"ReplaceNode ( Node , CurDAG -> getMachineNode ( ISD::SHL, DL, VT, Op0, ShAmtVal ) ) ; return ; } } }" LLVM,RISCV,1584,if (C && C->isNullValue()) { LLVM,RISCV,1585,auto *C = dyn_cast(N); LLVM,RISCV,1586,"return RI5CY_pclip_check(CurDAG, Dest, SRC1, SRC2);" LLVM,RISCV,1587,"bool DAGToDAGISel :: SelectPCLIP ( SDValue Dest , SDValue & SRC1 ," LLVM,RISCV,1588, LLVM,RISCV,1589,"bool DAGToDAGISel :: SelectPCLIPU ( SDValue Dest , SDValue & SRC1 , SDValue SRC2 ) { if (!isPCLIPUOp(SRC1.getOpcode())) { return false; } if (!Dest.isRegister()) { return false; } if (!SRC1.isRegister() || !SRC2.is" LLVM,RISCV,1590,CurDAG->RemoveDeadNode(Node); LLVM,RISCV,1591,SelectCode(Or.getNode()); LLVM,RISCV,1592, LLVM,RISCV,1593,SDLoc DL ( Node ) ; EVT VT = Node -> getValueType ( ) ; switch ( Opcode ) { case : { if ( auto * ConstOp = dyn_cast < ConstantSDNode > ( Node -> getOperand ( ) ) ) { if ( ! ( ConstOp -> hasOneUse ( ) ) ) break ; int64_t Imm = ConstOp -> getSExtValue ( ) ; if ( ! ( - <= Imm && Imm LLVM,RISCV,1594,bool DAGToDAGISel :: MatchSLLIUW ( SDNode * N ) const { LLVM,RISCV,1595,assert ( N -> getOperand ( ) . getOpcode ( ) == ) ; assert ( isa < ConstantSDNode > ( N -> getOperand ( ) ) ) ; assert ( isa < ConstantSDNode > ( N -> getOperand ( ) . getOperand ( ) ) ) ; LLVM,RISCV,1596,"signExtend ) Opcode = ; else if ( ! simm12 && signExtend ) Opcode = ; else Opcode = ; break ; case : Opcode = ; break ; default : llvm_unreachable ( ""Unexpected type!"" ) ; } ReplaceNode ( Node , CurDAG -> getMachineNode ( Opcode , DL , Load -> getMemoryVT ( ) , Chain , Base , Offset , Load ->" LLVM,RISCV,1597,bool DAGToDAGISel :: SelectLoopDecrement ( SDValue LoopDecrement ) { return ( LoopDecrement -> getOpcode ( ) == && LoopDecrement -> getOperand ( 0 ) -> getOpcode ( ) == ); } LLVM,RISCV,1598,CurDAG->RemoveDeadNodes(); LLVM,RISCV,1599,Glue ) ; } Operands . push_back ( Chain ) ; } LLVM,RISCV,1600, LLVM,RISCV,1601,return new DAGToDAGISel(TM); LLVM,RISCV,1602, LLVM,RISCV,1603,return false; LLVM,RISCV,1604, LLVM,RISCV,1605,case : case : case : case : case : { unsigned Opc ; switch ( N0 . getMachineOpcode ( ) ) { default : llvm_unreachable ( ) ; case : Opc = ; break ; case : Opc = ; break ; case : Opc = LLVM,RISCV,1606,"{ return ""MyPass""; }" LLVM,RISCV,1607,Subtarget = &MF.getSubtargetSubtarget>( ); LLVM,RISCV,1608,Subtarget = &MF.getSubtarget(); LLVM,RISCV,1609, LLVM,RISCV,1610,return SrcReg; LLVM,RISCV,1611,if (auto *C = dyn_cast(N)) { int64_t ImmVal = SignExtend64(C->getSExtValue()); return ImmVal; } LLVM,RISCV,1612,return false; LLVM,RISCV,1613,"bool DAGToDAGISel::selectShiftMask(SDValue N, unsigned ShiftWidth, SDValue &Sh" LLVM,RISCV,1614, LLVM,RISCV,1615,if (C && isUInt(C->getZExtValue())) { LLVM,RISCV,1616,"MachineSDNode * Load = CurDAG->getMachineNode(P->Pseudo, DL, , , Operands);" LLVM,RISCV,1617,"CurDAG->addNode(Load, MemOp);" LLVM,RISCV,1618, LLVM,RISCV,1619,"SDValue SuperReg = SDValue(Load, [...]);" LLVM,RISCV,1620,"bool DAGToDAGISel :: selectVSplatSimm5 ( SDValue N , SDValue & SplatVal ) { return selectVSplatSimmHelper ( N , SplatVal , * CurDAG , * Subtarget , [ ] ( int64_t Imm ) { return isInt<5> ( Imm ); } ); }" LLVM,RISCV,1621,return false; LLVM,RISCV,1622,return false; LLVM,RISCV,1623,SplatImm ) ) return false ; return true ; LLVM,RISCV,1624, LLVM,RISCV,1625,return LHSTy . getSizeInBits ( ) <= ? LHSTy . getSizeInBits ( ) : ; LLVM,RISCV,1626,"EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context) {" LLVM,RISCV,1627,bool isFMAFasterThanFM LLVM,RISCV,1628,bool isFMAFasterThanFM LLVM,RISCV,1629,LiveIntervals & LiveIn) { MF.addLiveIn (PReg); LiveIn.addLiveIn (PReg); return LiveIn; } LLVM,RISCV,1630,"RVLocs , Context ) ; for ( const CCValAssign & RVLoc : RVLocs ) { if ( RVLoc.isByValArgument ( ) ) { return false ; } } return true ; }" LLVM,RISCV,1631, LLVM,RISCV,1632,"if ( VA . isExtInLoc ( ) ) Value = DAG . getNode ( , DL , VA . getValVT ( ) , Value ) ; else if ( VA . getLocInfo ( ) == CCValAssign :: Indirect ) Value = DAG . getLoad" LLVM,RISCV,1633,if (VA.getLocInfo() == CCValAssign::Indirect) LLVM,RISCV,1634,switch ( VA . getLocInfo ( ) ) { LLVM,RISCV,1635,"return DAG . getNode ( , DL , )" LLVM,RISCV,1636, LLVM,RISCV,1637, LLVM,RISCV,1638,return ; LLVM,RISCV,1639, LLVM,RISCV,1640, LLVM,RISCV,1641, LLVM,RISCV,1642,return; LLVM,RISCV,1643,return Imm.isLegal(); LLVM,RISCV,1644,"DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op), Op.getValueType()));" LLVM,RISCV,1645,case NotAtomic: LLVM,RISCV,1646,SDValue Result = DAG.getTargetBlockAddress LLVM,RISCV,1647,SDValue Result; LLVM,RISCV,1648,"VaArgOffset , true ) ;" LLVM,RISCV,1649,"getSExtValue ( ) == 0 ) && ""offset not yet supported"" ); SDLoc DL ( Op . getDebugLoc ( ) ); SDValue Chain ( DAG . getFramePointer ( ) ); return DAG . getNode ( ISD::FRAMEADDR , DL , Op . getValueType ( ) , Chain , Op . getOperand ( ) ); }" LLVM,RISCV,1650, LLVM,RISCV,1651, LLVM,RISCV,1652, LLVM,RISCV,1653,"SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), PtrVT);" LLVM,RISCV,1654, LLVM,RISCV,1655, LLVM,RISCV,1656, LLVM,RISCV,1657,MachineFunction & MF = DAG . getMachineFunction(); LLVM,RISCV,1658,"SDValue Cond = DAG . getNode ( , DL , getSetCCResultType ( DAG . getDataLayout ( ) , * DAG . getContext ( ) , Ty ) , Op . getOperand ( ) , Op . getOperand ( ) , Op . getOperand ( ) ) ; return DAG . getNode ( , DL , Op . getValueType ( ) ," LLVM,RISCV,1659, LLVM,RISCV,1660,SDValue TargetLowering LLVM,RISCV,1661,const Value * SV = cast < SrcValueSDNode > ( Op . getOperand ( ) ) . getSrcValue() ; LLVM,RISCV,1662, LLVM,RISCV,1663, LLVM,RISCV,1664,"if ( CC_ ( MF . getDataLayout ( ) , i , ArgVT , ArgVT , CCValAssign :: Full , ArgFlags , CCInfo , Outs [ i ] . IsFixed , IsRet , OrigTy ) ) {" LLVM,RISCV,1665, LLVM,RISCV,1666,"SDValue BALo = DAG.getTargetBlockAddress(BA, Ty, Offset, ""blockaddress"");" LLVM,RISCV,1667, LLVM,RISCV,1668,"SDValue MNHi = SDValue(DAG.getMachineNode(""machinenode_name"", DL, [...]));" LLVM,RISCV,1669,Offset ) ) ; FrameAddr = Ptr ; } LLVM,RISCV,1670,"SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), DL, FrameReg, VT); unsigned Depth = cast(Op.getOperand(1))->getZExtValue(); while (Depth--) { int Offset = - (XLenInBytes * ); SDValue Ptr = DAG.getNode(ISA_LIT::ADD64rr, DL, VT, FrameAddr, DAG.getIntPtrConstant(Offset," LLVM,RISCV,1671, LLVM,RISCV,1672,"return lowerGlobalAddress(Op, DAG);" LLVM,RISCV,1673,"case : return LowerFRAMEADDR(Op, DAG);" LLVM,RISCV,1674, LLVM,RISCV,1675,"setOperationAction(, , Legal);" LLVM,RISCV,1676, LLVM,RISCV,1677, LLVM,RISCV,1678,else if (Ins[i].isOrigArg()) LLVM,RISCV,1679, LLVM,RISCV,1680, LLVM,RISCV,1681,"if ( LocVT == || LocVT == ) { unsigned Offset5 = State . AllocateStack ( , ) ; State . addLoc ( CCValAssign :: getMem ( ValNo , ValVT , Offset5 , LocVT , LocInfo ) ) ; return false ; } }" LLVM,RISCV,1682, LLVM,RISCV,1683,"NewOp1 , NewRes ) ;" LLVM,RISCV,1684, LLVM,RISCV,1685,return; LLVM,RISCV,1686, LLVM,RISCV,1687,assert ( MI . getOpcode ( ) == && ) ; MachineFunction & MF = * BB -> getParent ( ) ; DebugLoc DL = MI . getDebugLoc ( ) ; const TargetInstrInfo & TII = * MF . getSubtarget ( ) . getInstrInfo ( ) ; const TargetRegisterInfo * RI = MF . getSubtarget ( ) . getRegisterInfo ( ) ; Register LoReg = MI . getOperand ( ) . getReg ( ) ; LLVM,RISCV,1688,C_Address LLVM,RISCV,1689, LLVM,RISCV,1690, LLVM,RISCV,1691,unsigned TargetLowering::getExceptionSelectorRegister(const Constant *c) { if (c->getType()->isIntegerTy()) { return 0; } else if (c->getType()->isPointerTy()) { return 1; } else { return 2; } } LLVM,RISCV,1692, LLVM,RISCV,1693,llvm_unreachable ( ) ; LLVM,RISCV,1694,"static SDValue getTargetNode(ConstantPoolSDNode *N, SDLoc DL, EVT Ty, SelectionDAG &DAG) {" LLVM,RISCV,1695, LLVM,RISCV,1696, LLVM,RISCV,1697, ) -> getName ( ) ; LLVM,RISCV,1698,return (VT == && Subtarget.hasStdExtF()) || (VT == && Subtarget.hasStdExtF()); LLVM,RISCV,1699,APInt ShiftedC1Int = C1Int << C2->getAPIntValue(); if (ShiftedC1Int.getMinSignedBits() <= && isLegalAddImmediate(ShiftedC1Int.getSExtValue())) return true; if (C1Int.getMinSignedBits() <= && isLegalAddImmediate(C1Int.getSExtValue())) return false; LLVM,RISCV,1700, LLVM,RISCV,1701,"RetOps.push_back(DAG.getRegister(RegHi, ));" LLVM,RISCV,1702, LLVM,RISCV,1703, LLVM,RISCV,1704,return STI.isRegisterReservedByUser(Reg); } ) ) ) { } LLVM,RISCV,1705,"void TargetLowering::validateCCReservedRegs(const SmallVectorImpl> &Regs, MachineFunction &MF) const {" LLVM,RISCV,1706,LocInfo ) ) ; } return false ; } LLVM,RISCV,1707,RVFI->setVarArgsFrameIndex(FI); LLVM,RISCV,1708, LLVM,RISCV,1709,"RetOps.push_back(DAG.getRegister(RegHi, ));" LLVM,RISCV,1710,"bool shouldNormalizeToSelectSequence(LLVMContext &Context, EVT VT) {" LLVM,RISCV,1711, LLVM,RISCV,1712, LLVM,RISCV,1713, LLVM,RISCV,1714,return true; LLVM,RISCV,1715,return false; LLVM,RISCV,1716,"IntNo ) { case ISA_INTRINSIC_WO_CHAIN::ID::SLOW_UNALIGNED_LOAD: return LowerSlowUnalignedLoad(Op, DAG, IntNo); case ISA_INTRINSIC_WO_CHAIN::ID::SLOW_UNALIGNED_STORE: return LowerSlowUnalignedStore(Op, DAG, IntNo); case ISA_INTRINSIC_WO_CHAIN::ID::ASSUME_ALIGNED" LLVM,RISCV,1717,"SDValue TargetLowering :: LowerINTRINSIC_WO_CHAIN ( SDValue Op , SelectionDAG & DAG ) const { unsigned IntNo = cast < ConstantSDNode > ( Op . getOperand ( ) ) -> getZExtValue ( ) ; SDLoc DL ( Op );" LLVM,RISCV,1718, LLVM,RISCV,1719, LLVM,RISCV,1720, LLVM,RISCV,1721,"return CC_Assign2XLen(XLen, State, VA, AF, ValNo, ValVT, LocVT, ArgFlags);" LLVM,RISCV,1722, LLVM,RISCV,1723,if (C1Cost < ShiftedC1Cost) LLVM,RISCV,1724,return false; LLVM,RISCV,1725,if (Op0.getValueType() != ) { LLVM,RISCV,1726, LLVM,RISCV,1727,"return CC_Assign2XLen(XLen, State, VA, AF, ValNo, ValVT, LocVT, ArgFlags);" LLVM,RISCV,1728,"return CC_Assign2XLen(XLen, State, VA, AF, ValNo, ValVT, LocVT, ArgFlags);" LLVM,RISCV,1729,HeadMBB->addSuccessor(IfFalseMBB); LLVM,RISCV,1730,DebugLoc DL = MI.getDebugLoc(); LLVM,RISCV,1731, LLVM,RISCV,1732,"if (VA.isRegLoc()) { RegsToPass.push_back(std::make_pair(VA.getLocReg(), ArgValue)); } else { assert(VA.isMemLoc() && ""Unexpected memory location""); if (!StackPtr.getNode()) StackPtr = DAG.getCopyFromReg(Chain, DL, , PtrVT); S" LLVM,RISCV,1733,RVFI->setVarArgsFrameIndex(FI); LLVM,RISCV,1734,RetOps[VA.getLocInfo().getReg()] = Val; LLVM,RISCV,1735,setMinimumJumpTableEntries(4); LLVM,RISCV,1736,unsigned NumArgs = Ins.size(); LLVM,RISCV,1737,"[PYTHON] def get_mask_argument(mf, isa, subtarget, ins, num_args, cc_info, is_ret): first_mask_argument = None if subtarget.has_v_instructions(): first_mask_argument = pre_assign_mask(ins) for i in range(num_args): arg_vt = ins[i].vt arg_flags = ins[i].flags arg_ty = None if is_ret: arg_" LLVM,RISCV,1738,"bool TargetLowering::CanLowerReturn(CallingConv::ID CallConv, MachineFunction& MF," LLVM,RISCV,1739,"return CC_Assign2XLen(XLen, State, VA, AF, ValNo, ValVT, LocVT, ArgFlags);" LLVM,RISCV,1740,if (VT == && Subtarget.hasStdExtF() && !Subtarget.hasStdExtZfhmin()) { LLVM,RISCV,1741,"TargetLowering::getNumRegistersForCallingConv(LLVMContext& Context, CallingConv::ID CC, EVT VT) const { if (VT == && Subtarget.hasStdExtF() && !Subtarget.hasStdExtF()) { return 0; } return 1; }" LLVM,RISCV,1742,"return VT.changeVectorElementTypeToInteger(Context, , VT.getVectorElementCount());" LLVM,RISCV,1743,return Subtarget . hasStdExtZbb ( ) && ! isa < ConstantSDNode > ( SDValue ( Op ) ) ; LLVM,RISCV,1744,4 LLVM,RISCV,1745,return Subtarget.hasVInstructionsF64(); LLVM,RISCV,1746,"SDValue Result = DAG.getNode(ISD::BITCAST, DL, IntVT, Bitcast);" LLVM,RISCV,1747,"Shifted = DAG.getNode(, DL, XLenVT, Shift, RM);" LLVM,RISCV,1748, LLVM,RISCV,1749,MVT XLenVT = Subtarget.getXLenVT(); LLVM,RISCV,1750, LLVM,RISCV,1751,return Shifted; LLVM,RISCV,1752,MVT OpVT = ScalarOp.getSimpleValueType(); LLVM,RISCV,1753,"return SDValue ( CA, CB );" LLVM,RISCV,1754,if (LMul > Subtarget.getMaxLMulForFixedLengthVectors()) return false; LLVM,RISCV,1755, LLVM,RISCV,1756,RetOps.push_back(DAG.getRegister(RegHi)); LLVM,RISCV,1757,if (RC == & ) { LLVM,RISCV,1758,FirstMaskArgument = preAssignMask(Ins); LLVM,RISCV,1759,) ; LLVM,RISCV,1760,"CCState CCInfo ( CallConv , IsVarArg , MF , RVLocs , Context ) ; Optional < unsigned > FirstMaskArgument ; if ( Subtarget . hasStdExtV ( ) ) FirstMaskArgument = preAssignMask ( Outs ) ; for ( unsigned i = 0 , e = Outs . size ( ) ; i != e ; ++ i ) { MVT VT = Outs [ i ] . VT ; ""ArgFlags"" = Outs [ i ] . Flags ; ""AB" LLVM,RISCV,1761, LLVM,RISCV,1762,"return SDValue (Src, ShAmt1 + ShAmt2);" LLVM,RISCV,1763,NarrowSize ) ) return SDValue ( ) ; } else { if ( DAG . ComputeNumSignBits ( Op1 ) < ( ScalarBits [/INST] NarrowSize ) ) return SDValue ( ) ; } } else { return SDValue ( ) ; } LLVM,RISCV,1764,"DL, NarrowVT, Op0, VL );" LLVM,RISCV,1765,RHS -> Op ) ; } return SDValue ( ) ; } LLVM,RISCV,1766," ) , RHS -> Op , DAG . getConstant ( RHS -> ShAmt , DL , ) ) ; }" LLVM,RISCV,1767,return SDValue(); LLVM,RISCV,1768,AllOnes ) ) return Result; } LLVM,RISCV,1769,"N0 , DAG , AllOnes ) ) return Result ;" LLVM,RISCV,1770,"However, the code" LLVM,RISCV,1771,x = (x & ) << LLVM,RISCV,1772,case : LLVM,RISCV,1773, LLVM,RISCV,1774,bool convertSetCCLogicToBitwiseLogic ( EVT VT ) { LLVM,RISCV,1775,bool convertSetCCLogicToBitwiseLogic ( EVT VT ) { LLVM,RISCV,1776, LLVM,RISCV,1777,case CCValAssign::BCvt: if (VA.getLocVT().isInteger() && VA.getValVT() == ) ... LLVM,RISCV,1778, LLVM,RISCV,1779, LLVM,RISCV,1780, LLVM,RISCV,1781, LLVM,RISCV,1782,"VecVT ); unsigned SubVecRegClassID = getRegClassIDForVecVT ( SubVecVT ); unsigned NumSubVecs = VecVT.getSizeInBits() / SubVecVT.getSizeInBits(); std::pair SubRegs[NumSubVecs]; for (unsigned i = 0; i < NumSubVecs; i++) { SubRegs[i].first = InsertExtractIdx + i * SubVecVT.getSizeInBits(); SubRegs" LLVM,RISCV,1783,Register LoReg = MI.getOperand().getReg(); LLVM,RISCV,1784,"Result, Type::getIntNTy(CI->getContext(), XLen));" LLVM,RISCV,1785,"Value * Result = Builder . CreateCall ( MaskedCmpXchg , { AlignedAddr , CmpVal , NewVal , Mask , Ordering } ) ;" LLVM,RISCV,1786,"MF.insert(It, DoneMBB);" LLVM,RISCV,1787,) { LLVM,RISCV,1788,return; LLVM,RISCV,1789,"TII.storeRegToStackSlot(*BB, MI, SrcReg, MI.getOperand().getReg());" LLVM,RISCV,1790,"Instruction * TargetLowering :: emitTrailingFence ( IRBuilderBase & Builder , Instruction * Inst , AtomicOrdering Ord ) const { if ( isa < LoadInst > ( Inst ) && isAcquireOrStronger ( Ord ) ) return Builder . CreateFence ( Ord , Inst , nullptr , nullptr ); }" LLVM,RISCV,1791, LLVM,RISCV,1792,"return DAG.getStore(Store->getChain(), DL, StoredVal, Store->getBasePtr(), Store->getPointerInfo(), Store->getOriginalAlign(), Store->getMemOperand());" LLVM,RISCV,1793,Other.ShAmt; LLVM,RISCV,1794,bool formsPairWith(const BitmanipPat& other) { LLVM,RISCV,1795, LLVM,RISCV,1796,MVT TargetLowering :: getContainerForFixedLengthVector ( MVT TargetLowering :: getContainerForFixedLengthVector ( MVT TargetLowering :: getContainerForFixedLengthVector ( MVT TargetLowering :: getContainerForFixedLengthVector ( MVT TargetLowering :: getContainer LLVM,RISCV,1797,"XLenVT, DL, SDLoc ( ) ) : DAG . getNode ( ISD::EXTRACT_VECTOR_ELT, XLenVT, VecVT, DAG . getConstant ( 0, DL, SDLoc ( ) ) );" LLVM,RISCV,1798, LLVM,RISCV,1799,Args.push_back(Entry); LLVM,RISCV,1800, LLVM,RISCV,1801, LLVM,RISCV,1802,const Register &TargetLowering :: getExceptionSelectorRegister ( const Constant * PersonalityFn ) { } return ExceptionSelectorRegister; LLVM,RISCV,1803," getExtendForAtomicOps ( ) const override { return ""atomic""; }" LLVM,RISCV,1804," getExtendForAtomicOps ( ) const override { return ""atomic""; }" LLVM,RISCV,1805,if ( ConstraintCode . size ( ) == ) { switch ( ConstraintCode [ ] ) { case 'A': if ( ConstraintCode . size ( ) == ) { switch ( ConstraintCode [ ] ) { case 'A': if ( ConstraintCode . size ( ) == ) { switch ( ConstraintCode [ && ); LLVM,RISCV,1809, LLVM,RISCV,1810,``` LLVM,RISCV,1811,"static Align getPrefTypeAlign ( EVT VT , SelectionDAG & SD ) { Align PrefTypeAlign = getPrefTypeAlign ( VT ); if ( PrefTypeAlign != SD.getAlign () ) { SD.setAlign ( PrefTypeAlign ); }" LLVM,RISCV,1812,if (VT.getVectorElementType() == ) return ; return getRegClassIDForLMUL(getLMUL(VT)); LLVM,RISCV,1813, LLVM,RISCV,1814,"MVT TargetLowering :: getRegisterTypeForCallingConv ( LLVMContext & Context , CallingConv :: ID CC , EVT VT ) const {" LLVM,RISCV,1815,VT ); LLVM,RISCV,1816,"static SDValue getRVVFPExtendOrRound(SDValue Op, MVT VT, MVT ContainerVT, SDLoc DL, SelectionDAG &DAG, const Subtarget &Subtarget) {" LLVM,RISCV,1817,case : return ; LLVM,RISCV,1818,If `VT LLVM,RISCV,1819, LLVM,RISCV,1820, LLVM,RISCV,1821, LLVM,RISCV,1822, LLVM,RISCV,1823,"return DAG.getTargetJumpTable(N->getIndex(), Ty, Flags);" LLVM,RISCV,1824,return true; LLVM,RISCV,1825,return VPExplicitVectorLengthTy; LLVM,RISCV,1826,hasStdExtZfh ( ) ) || ( VT == && Subtarget . hasStdExtF ( ) ) || ( VT == && Subtarget . hasStdExtZfh ( ) ) ) LLVM,RISCV,1827,return Subtarget.hasStdExtZbb(); LLVM,RISCV,1828,``` LLVM,RISCV,1829,bool TargetLowering::isCheapToSpeculateCttz() const { return Subtarget.hasStdExtZbb(); } LLVM,RISCV,1830,( ) ) ) return true ; } return false ; } LLVM,RISCV,1831,auto IsCalleeStructRet = Outs.empty() ? false : Outs[].Flags.isSRet(); LLVM,RISCV,1832,"if (!TRI->regmaskSubsetEqual(CalleePreserved, CallerPreserved)) return false;" LLVM,RISCV,1833,if (VT == && !Subtarget.hasStdExtZfh()) return false; LLVM,RISCV,1834,return false; LLVM,RISCV,1835,return (C1 * C2).isSignedIntN(); LLVM,RISCV,1836,return false; LLVM,RISCV,1837,return false; LLVM,RISCV,1838,if ( ! SeqStepNum ) SeqStepNum = ValDiff ; else if ( ValDiff != SeqStepNum ) return None ; if ( ! SeqStepDenom ) SeqStepDenom = IdxDiff ; else if ( IdxDiff != * SeqStepDenom ) return None ; } LLVM,RISCV,1839,"SDValue NegX = DAG . getNode ( , DL , ContainerVT , SplatZero , X , Mask , VL ) ;" LLVM,RISCV,1840,BlockAddressSDNode * N = cast < BlockAddressSDNode > ( Op ) ; LLVM,RISCV,1841,BlockAddressSDNode * N = cast < BlockAddressSDNode > ( Op ) ; LLVM,RISCV,1842,"return getAddr(N, DAG);" LLVM,RISCV,1843, LLVM,RISCV,1844, LLVM,RISCV,1845,"SDValue result = lowerFixedLengthVectorFCOPYSIGNToRVV(Op, DAG, Subtarget);" LLVM,RISCV,1846,"return DAG . getMergeValues ( { Result , Load -> getChain ( ) } ," LLVM,RISCV,1847,"MaskOpc , true ) ;" LLVM,RISCV,1848,return lowerToScalableOp; LLVM,RISCV,1849,"SDValue Op1 = convertToScalableVector ( ContainerVT , Op . getOperand ( ) , DAG , Subtarget ) ; SDValue Op2 = convertToScalableVector ( ContainerVT , Op . getOperand ( ) , DAG , Subtarget ) ; SDLoc DL ( Op ) ; SDValue Mask , VL ; std :: tie ( Mask , VL ) = getDefaultVLOps ( VT , ContainerVT , DL , D" LLVM,RISCV,1850,"SDValue VL = DAG.getConstant(VT.getVectorNumElements(), DL);" LLVM,RISCV,1851,"return convertFromScalableVector(VT, Cmp, DAG);" LLVM,RISCV,1852,"return DAG.getMemIntrinsicNode(, DL, DAG.getVTList(), {Store->getChain(), NewValue, Store->getBasePtr()});" LLVM,RISCV,1853,"SDValue Reduction = DAG.getNode(RVVOpcode, DL, M1VT, DAG.getUNDEF(M1VT), ScalarSplat, VL" LLVM,RISCV,1854, LLVM,RISCV,1855,Here LLVM,RISCV,1856,static const int Table = (int(RoundingMode::NearestTiesToEven) << * ) | (int(RoundingMode::TowardZero) << * ) | (int(RoundingMode:: LLVM,RISCV,1857, LLVM,RISCV,1858,"return DAG.getMemIntrinsicNode(, DL, Store->getVTList(), Ops, Store->getMemoryVT(), Store->getMemOperand());" LLVM,RISCV,1859,"return DAG . getNode ( , DL , VT , SelectCond , SplattedVal , Vec , VL ) ; }" LLVM,RISCV,1860,"return DAG . getMergeValues ( { Result , Chain } , DL ) ; } }" LLVM,RISCV,1861, LLVM,RISCV,1862, LLVM,RISCV,1863, LLVM,RISCV,1864,"assert(VT.getVectorElementCount() == IndexVT.getVectorElementCount() && ""Vector element count mismatch"");" LLVM,RISCV,1865, LLVM,RISCV,1866, LLVM,RISCV,1867, LLVM,RISCV,1868,RetOps[] = Chain; if (Glue.getNode()) { RetOps.push_back(Glue); } unsigned RetOpc = ; const Function &Func = DAG.getMachineFunction().getFunction(); LLVM,RISCV,1869, LLVM,RISCV,1870,"DAG . getNode ( , DL , VT , CondV , FalseV ) ; } } return DAG . getNode ( , DL , VT , CondV , TrueV , FalseV ) ; }" LLVM,RISCV,1871,"return DAG.getNode(, DL, Op.getValueType(), Ops);" LLVM,RISCV,1872, LLVM,RISCV,1873, LLVM,RISCV,1874,"SDValue TargetLowering::lowerShiftLeftParts(SDValue Op, SelectionDAG &DAG) const {" LLVM,RISCV,1875, LLVM,RISCV,1876, LLVM,RISCV,1877,unsigned Opc = VT.isFloatingPoint ? ISD::FP_TO_FP : ISD::FP_TO_INT; LLVM,RISCV,1878,"SDValue result = DAG.getNode(NewOpc, DL, VT, Ops);" LLVM,RISCV,1879,return Vec; LLVM,RISCV,1880, LLVM,RISCV,1881, LLVM,RISCV,1882,assert(SplatVal.getValueType() == XLenVT && ); LLVM,RISCV,1883,"SplatZero = DAG . getNode ( , DL , ContainerVT , [" LLVM,RISCV,1884, LLVM,RISCV,1885, LLVM,RISCV,1886, LLVM,RISCV,1887, LLVM,RISCV,1888,"Vec ) ; } Here is a possible completion of the last statement: Vec = convertToScalableVector(ContainerVT, Vec);" LLVM,RISCV,1889, LLVM,RISCV,1890, LLVM,RISCV,1891,"static Optional < BitmanipPat > matchSHFLPat ( SDValue Op ) { static const uint64_t BitmanipMasks [ ] = { , , , , }; return matchBitmanipPat ( Op, BitmanipMasks ); }" LLVM,RISCV,1892,static Optional < BitmanipPat > matchSHFLPat ( SDValue Op ) { static const uint64_t BitmanipMasks [ ] = { LLVM,RISCV,1893,Here are a few things you could do to complete the function: LLVM,RISCV,1894,return ! Subtarget . useRVVForFixedLengthVectors ( ) || ( VT . isFixedLengthVector ( ) && VT . getVectorElementType ( ) == VT . getScalarType ( ) ); LLVM,RISCV,1895,"DAG, Subtarget );" LLVM,RISCV,1896,if (!Subtarget.is64Bit()) LLVM,RISCV,1897,"if (auto GORC = combineORToGORC(SDValue(N, ), DAG, Subtarget)) return GORC;" LLVM,RISCV,1898,"DAG , Subtarget );" LLVM,RISCV,1899,DAG ); LLVM,RISCV,1900,"static SDValue performXORCombine(SDNode *N, SelectionDAG &DAG) {" LLVM,RISCV,1901,"bool shouldExpandShift ( SelectionDAG & DAG , SDNode * N ) const override {" LLVM,RISCV,1902,return true; LLVM,RISCV,1903,"if (ABI == ""strict"" && Type == ""string"") return false;" LLVM,RISCV,1904,bool TargetLowering::shouldRemoveExtendFromGSIndex(const GSIndex& index) const { if (index.isStateless()) { return true; } return false; } LLVM,RISCV,1905,"bool TargetLowering::shouldSignExtendTypeInLibCall(EVT Type, EVT Hint) { if (Type == EVT::sext) { return true; } else if (Type == EVT::zext) { return false; } else { return Hint == EVT::sext; } }" LLVM,RISCV,1906,return OpIdx.index() == 0 || OpIdx.index() == 1; LLVM,RISCV,1907,bool IsSinker(Instruction *I) { LLVM,RISCV,1908,"return DAG.getNode(, DL, VT, Lo, Hi, );" LLVM,RISCV,1909,"SDValue Hi = DAG.getNode(, DL, , Scalar, DAG.getConstant(, DL, ));" LLVM,RISCV,1910, LLVM,RISCV,1911,if ( ! TLO . LegalOps ) return false ; EVT VT = Op . getValueType ( ) ; if ( VT . isVector ( ) ) return false ; if ( Op . getOpcode ( ) != ) return false ; ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Op . getOperand ( ) ) ; if ( ! C ) return false ; const APInt & Mask = C -> getAPIntValue ( ) ; APInt ShrunkMask = Mask & Dem LLVM,RISCV,1912,"Next, the function checks if the subtarget has the `StdExtZbb` or `Std" LLVM,RISCV,1913, LLVM,RISCV,1914,assert(VA.getLocVT() == VT::i64 && VA.getValVT() == VT::i64 && VA.isMemLoc()); LLVM,RISCV,1915,"case CCValAssign::Indirect: Val = DAG.getStore(FIN, ValVT, VA.getLocMemOffset(), true); ExtType = VA.getLocInfo().getExtType(); break;" LLVM,RISCV,1916,"const TargetRegisterClass * RC = TLI . getRegClassFor ( LocVT , D" LLVM,RISCV,1917,bool TargetLowering::useRVVForFixedLengthVectorVT(MVT VT) const { return ::useRVVForFixedLengthVectorVT(VT); } LLVM,RISCV,1918,"void TargetLowering :: validateCCReservedRegs ( const SmallVectorImpl < std :: pair < llvm :: Register , llvm :: SDValue >> & Regs , MachineFunction & MF ) const {" LLVM,RISCV,1919,"F.getContext().diagnose(DiagnosticInfoISAReservedReg(F.getSubprogram(), Regs));" LLVM,RISCV,1920,"auto Idx = ( Opc , :: frm ) ;" LLVM,RISCV,1921,Created . push_back ( Sel . getNode ( ) ) ; LLVM,RISCV,1922,SDValue VL = N->getOperand(); LLVM,RISCV,1923,Op0 = Op0.getOperand(0); LLVM,RISCV,1924, LLVM,RISCV,1925, LLVM,RISCV,1926, LLVM,RISCV,1927, LLVM,RISCV,1928,return MachineJumpTableInfo :: EK_Custom32; LLVM,RISCV,1929,switch ( IntNo ) { LLVM,RISCV,1930,case : LLVM,RISCV,1931,const * II = ( IntNo ) ; if ( ! II ) return SDValue ( ) ; return Op . getOperand ( II -> VLOperand + + ) ; LLVM,RISCV,1932,bool TargetLowering :: hasAndNotCompare ( SDValue Y ) const { EVT VT = Y [0]; return VT == MVT::i1; } LLVM,RISCV,1933,hasStdExtZbq ( ) ); LLVM,RISCV,1934, LLVM,RISCV,1935,hasStdExtF ( ) ) return false ; if ( VT == && ! Subtarget . hasStdExtD ( ) ) return false ; if ( VT == && ! Subtarget . hasStdExtH ( ) ) return false ; if ( VT == && ! Subtarget . hasStdExtA ( ) ) return false ; if ( VT == && ! Subtarget . hasStdExtQ ( ) ) return false ; if ( VT == Subtarget &Subtarget) {" LLVM,RISCV,1943,"It looks like the method is being called with the following arguments: However, the" LLVM,RISCV,1944,assert (Scalar.getValueType().bitsLE(XLenVT)); The LLVM,RISCV,1945, LLVM,RISCV,1946,"SDValue Val = DAG.getNode(MaskOpc, DL, ContainerVT, Op1, Op2);" LLVM,RISCV,1947,"SDValue Val = DAG.getNode(MaskOpc, DL, ContainerVT, Op1, Op2, VL);" LLVM,RISCV,1948, LLVM,RISCV,1949,unsigned IntID = IsUnmasked ? 0 : 1; LLVM,RISCV,1950,"return DAG . getMemIntrinsicNode ( , DL , DAG . getVTList ( ) , Ops ) ;" LLVM,RISCV,1951,"return DAG.getNode(, DL, VT, Scalar, VL);" LLVM,RISCV,1952, LLVM,RISCV,1953,``` LLVM,RISCV,1954, LLVM,RISCV,1955,return -1; LLVM,RISCV,1956, LLVM,RISCV,1957, LLVM,RISCV,1958,"return TLI.getOperationName(Opc, DstVT, Src.getValueType());" LLVM,RISCV,1959, LLVM,RISCV,1960,EVT ValueVT = Val.getValueType(); LLVM,RISCV,1961, LLVM,RISCV,1962,"Op1 = DAG . getNode ( ExtOpc , DL , NarrowVT , Op1 , Mask , VL ) ;" LLVM,RISCV,1963,SeqAddend ) return None ; } if ( ! SeqStepNum || ! SeqStepDenom || ! SeqAddend ) return None ; LLVM,RISCV,1964, ; LLVM,RISCV,1965,"case AtomicRMWInst :: UMin : return ""umin"" ;" LLVM,RISCV,1966,Info.flags = MachineMemOperand::MOLoad | MachineMemOperand::MOOffset; LLVM,RISCV,1967,setOperationAction( || Size == ) return AtomicExpansionKind :: MaskedIntrinsic ; return AtomicExpansionKind :: None; LLVM,RISCV,1970,switch (expression) { LLVM,RISCV,1971, LLVM,RISCV,1972,assert LLVM,RISCV,1973, LLVM,RISCV,1974, LLVM,RISCV,1975,{ return m_capabilitySetAddress != nullptr; } LLVM,RISCV,1976,"getType() } ; Function * F = Intrinsic::getDeclaration(Builder.GetInsertBlock()->getModule(), Intrinsic::masked_atomic_cmpxchg, Tys); Value * Args[ ] = { AlignedAddr , CmpVal , NewVal , Mask , Ordering } ; return Builder.CreateCall(F, Args); }" LLVM,RISCV,1977, LLVM,RISCV,1978,CCValAssign::Full ) ) ; } return true ; } LLVM,RISCV,1979,"LocVT , LocInfo ) ) ; return false ; } } if ( LocVT == ) { static const MCPhysReg FPR128List [ ] = { , , , , , , , , , , , ," LLVM,RISCV,1980,"inline static unsigned computeVLMAX ( unsigned VectorBits , unsigned EltSize ) {" LLVM,RISCV,1981,return ScalarOperand != ; LLVM,RISCV,1982,return ScalarOperand != null; LLVM,RISCV,1983,Here are a few possible ways to complete the statement: LLVM,RISCV,1984, LLVM,RISCV,1985,"PendingLocs) { VA = It; AF = PendingArgFlags[It]; PendingLocs.clear(); PendingArgFlags.clear(); return CC_Assign2XLen(XLen, State, VA, AF, ValNo, ValVT, LocVT, ArgFlags); }" LLVM,RISCV,1986,RetOps[] = Chain; LLVM,RISCV,1987, LLVM,RISCV,1988,"return LowerINTRINSIC_W_CHAIN(Op, TargetLowering, SelectionDAG);" LLVM,RISCV,1989,"SDValue TargetLowering :: LowerINTRINSIC_W_CHAIN ( SDValue Op , SelectionDAG & DAG ) {" LLVM,RISCV,1990, LLVM,RISCV,1991,"VL = DAG.getConstant(VT.getVectorNumElements(), DL, XLenVT);" LLVM,RISCV,1992,Ops.push_back(VL); LLVM,RISCV,1993, LLVM,RISCV,1994,"SDValue Res = splatPartsI64WithVL(DL, ContainerVT, Lo, Hi, ...);" LLVM,RISCV,1995,"while (getTypeAction(*DAG.getContext(), VecEVT) == TargetLowering::TypeSplitVector) {" LLVM,RISCV,1996, LLVM,RISCV,1997,"def combineSelectAndUseCommutative(N, DAG):" LLVM,RISCV,1998,"SDValue performADDCombine(SDNode *N, SDValue Op1, SDValue Op2) { if (!N->isValid()) { return SDValue(); } if (N->getNumOperands() != 2) { return SDValue(); } if (N->getOpcode() != SDValue::ADD) { return SDValue(); }" LLVM,RISCV,1999,return true; LLVM,RISCV,2000,"return DAG . getNeutralElement ( Opc , SDLoc ( V ) , V . getSimpleValueType ( ) , N );" LLVM,RISCV,2001," WOpcode = getWOpcodeByIntr ( IntNo ) ; SmallVector < SDValue , > NewOps ; for ( SDValue Op : drop_begin ( N -> ops ( ) ) ) NewOps . push_back ( DAG . getNode ( , DL , , Op ) ) ; SDValue NewRes = DAG . getNode ( WOpcode ," LLVM,RISCV,2002,for (MachineInstr * SelectMBBI : SelectDebugValues) { LLVM,RISCV,2003, LLVM,RISCV,2004,"VecVT ); SDValue Mask = DAG.getConstant(1, DL, MaskVT); return DAG.getNode(ISD::AND, DL, MaskVT, Mask, VL);" LLVM,RISCV,2005,"SDValue getAllOnesMask(MVT VecVT, SDValue VL, SDLoc DL) { SDValue AllOnes = DAG.getConstant(VecVT, VL, DL); for (unsigned i = 0; i < VL; i++) { AllOnes.setElement(i, DAG.getConstant(1, DL));" LLVM,RISCV,2006, LLVM,RISCV,2007,"return { Mask, VL };" LLVM,RISCV,2008,static MVT getMaskTypeFor ( EVT VecVT ) { assert ( VecVT . isVector () ); LLVM,RISCV,2009,"return ( , EC );" LLVM,RISCV,2010, LLVM,RISCV,2011, LLVM,RISCV,2012,bool TargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode* GA) const { return GA->getGlobal()->isThreadLocal(); } LLVM,RISCV,2013,return true; LLVM,RISCV,2014, LLVM,RISCV,2015,"return convertFromScalableVector(VT, Cmp, DAG, Subtarget);" LLVM,RISCV,2016,"assert(N->getOffset() == && """ LLVM,RISCV,2017,LocalDynamic: LLVM,RISCV,2018,"Subtarget ) ; } } else { assert ( VT . isScalableVector ( ) && ) ; IndexVT = ( IndexVT . getVectorElementType ( ) , VT . getVectorElementCount ( ) ) ; Index = convertToScalableVector ( IndexVT , Index , DAG , Subtarget ) ; if ( ! IsUnmasked ) { MVT MaskVT = getMaskTypeFor ( VT ) ; Mask = convertToScalableVector ( MaskVT , Mask , DAG" LLVM,RISCV,2019, LLVM,RISCV,2020,bool IsUnmasked = (Mask.getNode() == nullptr); LLVM,RISCV,2021,return Result; LLVM,RISCV,2022,"Vec = DAG . getBitcast ( VT , Vec ) ;" LLVM,RISCV,2023,The LLVM,RISCV,2024, LLVM,RISCV,2025,"Based on the function name `getAllOnesMask`, it appears that the function is intended to create a mask with all ones for a given vector type `VecVT` and" LLVM,RISCV,2026,"SDValue Zero = DAG.getConstant(0, DL, XLenVT);" LLVM,RISCV,2027, LLVM,RISCV,2028,"if (SDValue V = combineBinOpToReduce(N, DAG))" LLVM,RISCV,2029,DAG ); LLVM,RISCV,2030,SDValue N0 = N -> getOperand ( ) ; LLVM,RISCV,2031, LLVM,RISCV,2032,"shouldProduceAndByConstByHoistingConstFromShiftsLHSOfAnd ( SDValue X , ConstantSDNode * XC , ConstantSDNode * CC , SDValue Y , unsigned OldShiftOpcode , unsigned NewShiftOpcode , SelectionDAG & DAG ) const { if ( XC && OldShiftOpcode == && XC -> isOne ( ) ) return false ; if ( NewShiftOpcode == && CC [/INST] Complete the last statement of this code" LLVM,RISCV,2033,{ return false; } LLVM,RISCV,2034,case : if ( ! Subtarget . hasVInstructionsF64 ( ) ) return false ; break ; LLVM,RISCV,2035,return false; LLVM,RISCV,2036,"LLVM_DEBUG(dbgs() << ""Mask argument "" << i << "" is not compatible with the calling convention\n"");" LLVM,RISCV,2037,It ) ; } LLVM,RISCV,2038," ) { unsigned Offset8 = State . AllocateStack ( , Align ( ) ) ; State . addLoc ( CCValAssign :: getMem ( ValNo , ValVT , Offset8 , LocVT , LocInfo ) ) ; return false ; }" LLVM,RISCV,2039,if (SwapSelectOps) LLVM,RISCV,2040,return SDValue(); LLVM,RISCV,2041,const APInt &Imm = ConstNode->getAPIntValue(); if ((Imm + ).isPowerOf2() || (Imm - ).isPowerOf2() || ( - Imm).isPowerOf2() || (- - Imm).isPowerOf2()) return true; if (Subtarget.hasStdExtM() && VT.getSizeInBits() >= Subtarget.getXLen()) return false; LLVM,RISCV,2042,return false; LLVM,RISCV,2043, LLVM,RISCV,2044, LLVM,RISCV,2045,"SDValue TargetLowering :: lowerFixedLengthVectorLoadToRVV ( SDValue Op , SelectionDAG & DAG ) const {" LLVM,RISCV,2046, LLVM,RISCV,2047,MVT VT = StoreVal.getSimpleValueType(); LLVM,RISCV,2048,"Idx - ArgRegs.size() ) ; VaArgOffset = CCInfo.getNextStackOffset() - VarArgsSaveSize ; } RVFI->VarArgsSaveArea = MFI.getObjectForOffset(VaArgOffset, XLenInBytes, RegInfo.getPointerAlignment());" LLVM,RISCV,2049,"SDValue Result = DAG.getMemIntrinsicNode(Intrinsic::masked_load, DL, VTs, Ops, MGN->getMemoryVT());" LLVM,RISCV,2050,"Index = convertToScalableVector(IndexVT, Index, DAG, Subtarget);" LLVM,RISCV,2051,"return DAG . getNode ( , DL , Op . getValueType ( ) , Ops ) ;" LLVM,RISCV,2052,"StepVec = DAG.getNode(ISD::SRA, DL, VT, StepVec, StepVal);" LLVM,RISCV,2053,StepVal ) ; } } return StepVec ; } LLVM,RISCV,2054,"MaskVT.getScalarType() ) ; SDValue Mask = DAG.getBuildVector(MaskContainerVT, DL, MaskVals); Gather = DAG.getNode(GatherOpc, DL, ContainerVT, Gather, Mask, VL); return Gather; }" LLVM,RISCV,2055,"assert(useRVVForFixedLengthVectorVT(OpVT) && ""Use RVV for fixed length vector VT"");" LLVM,RISCV,2056, LLVM,RISCV,2057,"static SDValue performXORCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const Subtarget &Subtarget) { SelectionDAG &DAG = DCI.getDAG(); }" LLVM,RISCV,2058, LLVM,RISCV,2059, LLVM,RISCV,2060,"if ( PrevElt ) { int64_t Diff = SignExtend64 ( Val - PrevElt -> first , EltSizeInBits ) ; if ( Diff % ( Idx - PrevElt -> second ) != ) return None ; int64_t Step = Diff / ( Idx - PrevElt -> second ) ; if ( Step == ) return None ; if ( ! SeqStep ) SeqStep = Step ; else if ( Step != SeqStep ) return None ; } if (" LLVM,RISCV,2061, LLVM,RISCV,2062,return SDValue ( ) ; LLVM,RISCV,2063,return MinVLen >= VT.getVectorNumElements(); LLVM,RISCV,2064,case : return ; LLVM,RISCV,2065,return C1Cost < ShiftedC1Cost; LLVM,RISCV,2066,) == MVT::i32 ) { LLVM,RISCV,2067,"SDLoc DL ( Op ) ; EVT MaskVT = Op . getValueType ( ) ; assert ( MaskVT . isVector ( ) && MaskVT . getVectorElementType ( ) == && ) ; SDValue Src = Op . getOperand ( ) ; MVT VecVT = Src . getSimpleValueType ( ) ; SDValue Mask , VL ; if ( IsVPTrunc ) { Mask = Op . getOperand ( VType::encodeVTYPE(Multiplier, ElementWidth, true, false));" LLVM,RISCV,2072,if (Subtarget.hasStdExtV()) LLVM,RISCV,2073,"bool TargetLowering::CanLowerReturn(CallingConv::ID CallConv, MachineFunction& MF, bool IsVarArg, const SmallVectorImpl& Outs, LLVMContext& Context) const {" LLVM,RISCV,2074,return true; LLVM,RISCV,2075,ArgVRM8s ) ; } else if ( RC == & ) { Reg = State . AllocateReg ( ArgVRM16s ) ; } else if ( RC == & ) { Reg = State . AllocateReg ( ArgVRM32s ) ; } else if ( RC == & ) { Reg = State . AllocateReg ( ArgVRM64s ) ; } else if ( RC == & ) { Reg = State . Al LLVM,RISCV,2076, LLVM,RISCV,2077, LLVM,RISCV,2078,if (VT.isScalarInteger()) { LLVM,RISCV,2079,"return addVSetVL ( MI , BB , VLIndex , SEWIndex , RVV -> VLMul ) ; } switch ( MI . getOpcode ( ) ) { default : llvm_unreachable ( ) ; case : assert ( ! Subtarget . is64Bit ( ) && ) ; return emitReadCycleWidePseudo ( MI , BB ) ; case : case : case : return ; LLVM,RISCV,2081, LLVM,RISCV,2082,NODE_NAME_CASE ( READ_CYCLE_WIDE ) LLVM,RISCV,2083,"OutChains . push_back ( Chain ) ; Chain = DAG . getNode ( , DL , OutChains ) ; }" LLVM,RISCV,2084,"DL , PtrVT , Op . getOperand ( 0 ) ) ; } } } }" LLVM,RISCV,2085,"return LowerINTRINSIC_WO_CHAIN ( Op , DAG ) ;" LLVM,RISCV,2086, LLVM,RISCV,2087,RetOps[] = Chain; LLVM,RISCV,2088, LLVM,RISCV,2089,"getNode ( ISD::SETNE, DL, Op.getValueType(), Ops ); }" LLVM,RISCV,2090,if (Src.getOpcode() == && isa(Src.getOperand())) { LLVM,RISCV,2091,"return SDValue(N, );" LLVM,RISCV,2092, LLVM,RISCV,2093,"MVT VT = N -> getSimpleValueType ( ) ; unsigned NarrowSize = VT . getScalarSizeInBits ( ) / ; MVT NarrowVT = ( ( NarrowSize ) , VT . getVectorElementCount ( ) ) ; SDValue Mask = N -> getOperand ( ) ; SDValue VL = N -> getOperand ( <" LLVM,RISCV,2094,WOpc = IsAdd ? : ; LLVM,RISCV,2095,SDValue Src = N -> getOperand ( ) ; if ( Src . getOpcode ( ) != N -> getOpcode ( ) ) return SDValue ( ) ; if ( ! isa < ConstantSDNode > ( N -> getOperand ( ) ) || ! isa < ConstantSDNode > ( Src . getOperand ( ) ) ) return SDValue ( ) ; unsigned ShAmt1 = N -> getConstantOperandVal LLVM,RISCV,2096,CombinedShAmt = ShAmt1 + ShAmt2; LLVM,RISCV,2097,Op0 = Op0.getOperand(); LLVM,RISCV,2098,"return DAG.getNode(, DL, VT, Res, DAG[/INST] The code snippet is incomplete and the last statement is not complete. It seems to be a part of a function that is trying to perform some bitwise operations on a value. The function is using the `DAG` object to create a new node with the result of the bitwise operation. The `DAG` object is a data structure that represents a directed acyclic graph, and it is used to represent the control flow of" LLVM,RISCV,2099, LLVM,RISCV,2100, LLVM,RISCV,2101,"Info . memVT = getValueType ( DL , I . getType ( ) -> getScalarType ( ) ) ; Info . align = Align ( DL . getTypeSizeInBits ( I . getType ( ) -> getScalarType ( ) ) / ) ; Info . size = MemoryLocation :: UnknownSize ; Info . flags |= MachineMemOperand :: MOLoad ; return true ;" LLVM,RISCV,2102,X ); if (C && C->getBitOffset() == 0 && C->getBitWidth() == 1) { return true; } return false; } LLVM,RISCV,2103, LLVM,RISCV,2104,if (StartIdx == ) return -; LLVM,RISCV,2105,"bool TargetLowering::isShuffleMaskLegal(ArrayRef M, EVT VT) const { if (ShuffleVectorSDNode::isSplatMask(M.data(), M.size())) { return true; } for (int i = 0; i < M.size(); i++) { if (M[i] >= VT.getVectorNumElements()) { return false; } }" LLVM,RISCV,2106,"SDValue NegX = DAG.getNode(ISD::SUB, DL, ContainerVT, SplatZero, X, Mask);" LLVM,RISCV,2107,"X = convertToScalableVector(ContainerVT, X, DAG, Subtarget); SDValue Mask, VL; std::tie(Mask, VL) = getDefaultVLOps(VT, ContainerVT, DL, DAG, Subtarget); SDValue SplatZero" LLVM,RISCV,2108, LLVM,RISCV,2109,"return DAG . getMemIntrinsicNode ( , DL , DAG . getVTList ( ) , { Store -> getChain ( ) , IntID , NewValue , Store } ) ;" LLVM,RISCV,2110,"return DAG . getNode ( ISD::VECREDUCE_STRIDED, DL, VecEltVT, Reduction, DAG );" LLVM,RISCV,2111,MVT VecVT = VectorVal.getSimpleValueType(); LLVM,RISCV,2112, LLVM,RISCV,2113,DL ); LLVM,RISCV,2114,"Truncated = DAG . getNode ( , DL , VT , Truncated , Src ) ;" LLVM,RISCV,2115, LLVM,RISCV,2116, LLVM,RISCV,2117,"VT, XLenMinus1, Shamt);" LLVM,RISCV,2118,"SDValue HiFalse = DAG . getNode ( ShiftRightOp , DL , VT , Lo , Shamt ) ;" LLVM,RISCV,2119, LLVM,RISCV,2120,if (VecVT.isFixedLengthVector()) { LLVM,RISCV,2121, LLVM,RISCV,2122,return StepVec; LLVM,RISCV,2123,"SDValue NeutralElem = DAG.getNeutralElement(BaseOpc, DL, VecEltVT, Mask, VL);" LLVM,RISCV,2124,"SDValue SplatTrueVal = DAG.getConstant(ExtTrueVal, DL, XLenVT);" LLVM,RISCV,2125, LLVM,RISCV,2126, LLVM,RISCV,2127, LLVM,RISCV,2128,"SDValue Indices = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, IntVT, VID);" LLVM,RISCV,2129, LLVM,RISCV,2130,"SDValue VLMax = DAG . getNode ( , DL , XLenVT , DAG . getConstant ( MinElts , DL , XLenVT ) ) ;" LLVM,RISCV,2131,"DstEltSize ) ) { MVT IntVT = ( ( DstEltSize / ) , DstVT . getVectorElementCount ( ) ) ; Src = DAG . getNode ( ISDExtOpc , DL , IntVT , { Src , Mask , VL } ) ; } Result = DAG . getNode ( ISDOpc , DL , DstVT , { S" LLVM,RISCV,2132,"SDValue Elt0 = DAG . getNode ( , DL , ResVT , Reduction ) ;" LLVM,RISCV,2133,MVT ContainerVT = VT; LLVM,RISCV,2134,"return convertFromScalableVector(VT, Gather);" LLVM,RISCV,2135,"return DAG.getNode(ISD::BITREVERSE, SDLoc(N), Src);" LLVM,RISCV,2136, LLVM,RISCV,2137,) { LLVM,RISCV,2138, LLVM,RISCV,2139,"ArgVR2s [0] ) ; break ; case : Reg = State . AllocateReg ( ArgVR4s [0] ) ; break ; case : Reg = State . AllocateReg ( ArgVR8s [0] ) ; break ; default : llvm_unreachable ( ""Unsupported vector type"" ) ; } } else Reg = State . AllocateReg ( ArgGPRs ) ; if ( ! Reg ) { unsigned StackOffset = State . AllocateStack ( : vtypei |= ; break; default: llvm_unreachable(); } BuildMI(*BB, MI, MI.getDebugLoc(), TII->get()," LLVM,RISCV,2143,assert ( MI.getOpcode() == && ) ; MachineFunction & MF = *BB->getParent(); DebugLoc DL = MI.getDebugLoc(); const TargetInstrInfo & TII = *MF.getSubtarget().getInstrInfo(); const TargetRegisterInfo * RI = MF.getSubtarget().getRegisterInfo(); Register LoReg = MI.getOperand().getReg(); Register HiReg = MI.getOper LLVM,RISCV,2144,switch (expression) { LLVM,RISCV,2145, LLVM,RISCV,2146,"SDValue TargetLowering :: lowerEXTRACT_VECTOR_ELT ( SDValue Op , SelectionDAG & DAG ) const { SDLoc DL ( Op ) ; SDValue Idx = Op . getOperand ( ) ; if ( isNullConstant ( Idx ) ) return Op ; SDValue Vec = Op . getOperand ( ) ; EVT EltVT = Op . getValueType ( ) ; EVT VecVT = Vec . getValueType ( )" LLVM,RISCV,2147,EII -> ExtendedOperand ] ; LLVM,RISCV,2148,"return DAG.getNode(, DL, Op.getValueType(), {Op.getOperand(), Op.getOperand(), Promote, Op.getOperand()});" LLVM,RISCV,2149,case : { assert(Subtarget.is64Bit() && Subtarget.hasStdExtF() && ); SDLoc DL(Op); SDValue Op0 = Op.getOperand(0); SDValue Op1 = Op.getOperand(1); SDValue Op2 = Op.getOperand(2); SDValue Op3 = Op.getOperand(3); SDValue Op4 = Op.getOperand(4); SDValue LLVM,RISCV,2150,"return lowerIntrinsicWithChain (Op, DAG);" LLVM,RISCV,2151, LLVM,RISCV,2152,"[PYTHON] def unpack_from_mem_loc(dag, chain, va, dl): mf = dag.get_machine_function() mfi = mf.get_frame_info() loc_vt = va.get_loc_vt() val_vt = va.get_val_vt() ptr_vt = dag.get_data_layout().get_pointer_size_in_bits(num_lit) fi = mfi.create_fixed_object(val_vt.get" LLVM,RISCV,2153,else { return false; } LLVM,RISCV,2154,"if (LocVT == || LocVT == ) { unsigned Offset5 = State.AllocateStack(, Align()); State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset5, LocVT, LocInfo)); return false; }" LLVM,RISCV,2155, LLVM,RISCV,2156,"Result = Builder . CreateTrunc ( Result , Builder . getInt32Ty ( ) ) ;" LLVM,RISCV,2157, LLVM,RISCV,2158,"Value * Result = Builder.CreateCall(LrwOpScwLoop, {AlignedAddr, Incr, Mask, ShiftAmt, Ordering});" LLVM,RISCV,2159,"Result = Builder.CreateCall(LrwOpScwLoop, {AlignedAddr, Incr, Mask, SextShamt, Ordering});" LLVM,RISCV,2160, LLVM,RISCV,2161,if ( ! ( Subtarget . getTargetABI ( ) ) ) return Align ( 1 ); LLVM,RISCV,2162,const GlobalValue *GV = N->getGlobal(); LLVM,RISCV,2163,uint32_t TargetLowering::getExceptionPointerAS() { LLVM,RISCV,2164,"EVT TargetLowering :: getSetCCResultType ( const DataLayout & DL , LLVMContext & Context , EVT VT ) const { if ( ! VT . isVector ( ) ) return getPointerTy ( DL . getIntPtrType ( Context ) ) ; }" LLVM,RISCV,2165, LLVM,RISCV,2166,if ( ! ( Subtarget . getTargetABI ( ) ) ) LLVM,RISCV,2167,"TailPaddingAmount TargetLowering :: getTailPaddingForPreciseBounds ( uint64_t Size ) const { if ( ! ( Subtarget . getTargetABI ( ) ) ) return TailPaddingAmount :: None ; return ( Size , Subtarget . getTargetABI ( ) . getTargetPreciseBounds ( ) ) ; }" LLVM,RISCV,2168,"SDValue getTargetNode(ExternalSymbolSDNode *N, SDLoc DL, EVT Ty, SDValueChain &Chain) { SDValue TargetNode = N->getTargetNode(Ty, Chain); if (!TargetNode.isConstant()) return TargetNode; SDValue NewTargetNode = DAG.getConstant(" LLVM,RISCV,2169,"SDValue getTargetNode(ExternalSymbolSDNode* N, SDLoc DL, EVT Ty, SelectionDAG& DAG, TargetLowering& TLI) { StringRef Name = N->getSymbolName(); const TargetLowering::TargetGlobalAddressInfo& GAI = TLI.getTargetGlobalAddressInfo(Name); SDValue TargetNode = DAG.getTargetGlobalAddress(" LLVM,RISCV,2170, LLVM,RISCV,2171, LLVM,RISCV,2172,EVT Ty = Op->getValueType(); LLVM,RISCV,2173,ConstantPoolSDNode * N = cast < ConstantPoolSDNode > ( Op ) ; LLVM,RISCV,2174,GlobalAddressSDNode * N = cast < GlobalAddressSDNode > ( Op ) ; LLVM,RISCV,2175,"ScalarHi ) ; } else if ( IntNo == ) { Vec = DAG . getNode ( , DL , I32VT , Vec [/INST] ScalarLo ) ; } else if ( IntNo == ) { Vec = DAG . getNode ( , DL , I32VT , Vec [/INST] ScalarHi ) ; } else if ( IntNo == ) { Vec = DAG" LLVM,RISCV,2176,"JumpTableSDNode * N = cast < JumpTableSDNode > ( Op ); const JumpTableData & JTD = N->getJumpTableData(); SDValue NewJumpTable = DAG.getJumpTable(JTD); ReplaceValueWith(SDValue(N, 0), NewJumpTable); return NewJumpTable;" LLVM,RISCV,2177, LLVM,RISCV,2178,"return DAG.getNode(, DL, Op.getValueType(), CondV, FalseV);" LLVM,RISCV,2179, LLVM,RISCV,2180,for (SDNode *SetCC : SetCCs) { LLVM,RISCV,2181,if ( ( Size == || Size == ) && ! ( Subtarget . getTargetABI ) ) LLVM,RISCV,2182, LLVM,RISCV,2183, ABI = Subtarget . getTargetABI ( ) ; if ( ( ABI == || ABI == ) ) LLVM,RISCV,2184,"AI ) ) ) { If all of these conditions are true, then the code will execute the" LLVM,RISCV,2185,"return TargetLowering::supportsAtomicOperation(DL, AI, ValueTy, PointerTy);" LLVM,RISCV,2186, LLVM,RISCV,2187,bool hasSplatOperand ( ) const { return SplatOperand != nullptr; } LLVM,RISCV,2188, LLVM,RISCV,2189, LLVM,RISCV,2190,if (Reg == ) Reg = LLVM,RISCV,2191,"SDValue TargetLowering :: lowerBUILD_VECTOR ( SDValue Op , SelectionDAG & DAG ) const {" LLVM,RISCV,2192,else if (VT == ) LLVM,RISCV,2193, LLVM,RISCV,2194,Ops . push_back ( DAG . getRegisterMask ( Mask ) ) ; LLVM,RISCV,2195, LLVM,RISCV,2196,"setOperationAction(, XLenVT, Expand);" LLVM,RISCV,2197, LLVM,RISCV,2198,"RetOps.push_back(DAG.getRegister(RegHi, ));" LLVM,RISCV,2199,"if ( CC_ ( MF . getDataLayout ( ) , i , ArgVT , ArgVT , CCValAssign :: Full , ArgFlags , CCInfo , Outs [ i ] . IsFixed , IsRet ) ) { DEBUG ( dbgs ( ) << <<" LLVM,RISCV,2200, LLVM,RISCV,2201,RVLocs ); LLVM,RISCV,2202,"EVT PtrVT = getPointerTy(DAG.getDataLayout()); if (IsVarArg) report_fatal_error(""""); SmallVector> ArgLocs; CCState CCInfo(CallConv, IsVarArg, MF, ArgLocs, *DAG.getContext()); analyzeInputArgs(MF, CCInfo, Ins, false); for (unsigned i = , e = ArgLocs.size(); i != e" LLVM,RISCV,2203, LLVM,RISCV,2204,if (isPositionIndependent()) { LLVM,RISCV,2205,"return DAG.getBlockAddress(N->getFunction(), N->getBasicBlock());" LLVM,RISCV,2206,"SDValue TargetLowering :: lowerConstantPool ( SDValue Op ," LLVM,RISCV,2207,if (isPositionIndependent()) { LLVM,RISCV,2208, LLVM,RISCV,2209, LLVM,RISCV,2210, LLVM,RISCV,2211, LLVM,RISCV,2212,"return addVSetVL ( MI , BB , VLIndex , SEWIndex , VLMul , ForceTailAgnostic ) ;" LLVM,RISCV,2213,"return DAG.getNode(ISD::SPLAT_PARTS_I64_Through_Stack, DL, VecVT, Lo, Hi, DAG.getRegister(, ));" LLVM,RISCV,2214, LLVM,RISCV,2215,"static SDValue splatPartsI64WithVL ( const SDLoc & DL , MVT VT , SDValue Lo , SDValue Hi , SDValue VL , SelectionDAG & DAG ) { if ( isa < ConstantSDNode > ( Lo ) && isa < ConstantSDNode > ( Hi ) ) { int32_t LoC = cast < ConstantSDNode > ( Lo ) -> getSExtValue ( ) ; int32_t HiC = cast < ConstantSDNode > ( Hi ) -> getSExtValue ( ) ; return D" LLVM,RISCV,2216,assert ( Subtarget . is64Bit ( ) && Subtarget . hasStdExtF ( ) && ) ; SDLoc DL ( Op ) ; SDValue Op0 = Op . getOperand ( ) ; if ( Op . getValueType ( ) != || Op0 . getValueType ( ) != ) return SDValue ( ) ; SDValue NewOp0 = DAG . getNode ( LLVM,RISCV,2217,"case : SDValue NewSplitF64 = DAG.getNode(, DL, DAG.getVTList(, ), Op0.getOperand());" LLVM,RISCV,2218, LLVM,RISCV,2219, LLVM,RISCV,2220, LLVM,RISCV,2221,return SDValue ( ) ; LLVM,RISCV,2222,case : case : case : assert(N->getValueType() == && Subtarget.is64Bit() && Subtarget.hasStdExtM() && ); if (N->getOperand()->getOpcode() == || N->getOperand()->getOpcode() == : return lowerShiftRightParts ( Op , DAG , false );" LLVM,RISCV,2231,if (!Res.getNode()) return; LLVM,RISCV,2232, LLVM,RISCV,2233,return finalResult; LLVM,RISCV,2234,return num.getValue(pos).getSExtValue(); LLVM,RISCV,2235, LLVM,RISCV,2236,setMinFunctionAlignment(FunctionAlignment); LLVM,RISCV,2237, LLVM,RISCV,2238, LLVM,RISCV,2239,case : case : case : case : { bool IsStrict = N->isStrictFPOpcode(); assert(N->getValueType() == && Subtarget LLVM,RISCV,2240,DestReg ) ; } LLVM,RISCV,2241,"MIB.addReg(MI.getOperand(VLIndex).getReg(), RegState::Define | RegState::Dead);" LLVM,RISCV,2242,} LLVM,RISCV,2243,"return addVSetVL ( MI , BB , VLIndex , SEWIndex , VLMul , WritesElement0 ) ; }" LLVM,RISCV,2244, LLVM,RISCV,2245,"DAG ) ; case : return lowerEXTRACT_VECTOR_ELT ( Op , DAG ) ; case : return lowerVECTOR_SHUFFLE ( Op , DAG ) ; case : return lowerBUILD_VECTOR ( Op , DAG ) ; case : return lowerSCALAR_TO_VECTOR ( Op , DAG ) ; case : return lowerCONCAT_VECTORS ( Op , DAG )" LLVM,RISCV,2246, LLVM,RISCV,2247, LLVM,RISCV,2248, LLVM,RISCV,2249,"DAG.getConstant(0, DL, Subtarget.getXLenVT()) );" LLVM,RISCV,2250,SDLoc DL ( Op ) ; EVT MaskVT = Op . getValueType ( ) ; assert ( MaskVT . isVector ( ) && MaskVT . getVectorElementType ( ) == && ) ; SDValue Src = Op . getOperand ( ) ; EVT VecVT = Src . getValueType ( ) ; bool IsRV32E64 = ! Subtarget . is64Bit ( ) && VecVT . getVectorElementType LLVM,RISCV,2251,"return DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Src);" LLVM,RISCV,2252,"return DCI.CombineTo(N, Op0.getOperand(), Op0.getOperand());" LLVM,RISCV,2253,"bool TargetLowering::allowsMisalignedMemoryAccesses(EVT VT, unsigned AddrSpace, unsigned Align, MachineMemOperand::Flags Flags) {" LLVM,RISCV,2254,if ( LoadSDNode * LD = dyn_cast < LoadSDNode > ( N ) ) { Base = LD -> getBasePtr ( ) ; } else if ( StoreSDNode * ST = dyn_cast < StoreSDNode > ( N ) ) { Base = ST -> getBasePtr ( ) ; } else { return false ; } if ( Base == Op -> getOperand ( ) ) { Offset = Op -> getOperand ( ) ; } else if ( Base == Op -> getOperand ( begin(), DL, TII->get(TargetOpcode::COPY), VReg)" LLVM,RISCV,2263, LLVM,RISCV,2264,"lowerADD ( SDValue Op , SelectionDAG & DAG ) {" LLVM,RISCV,2265, LLVM,RISCV,2266,"return DAG.getNode(, DL, , Op.getOperand(), DAG.getConstant(pred, DL, Subtarget.isRV64() ? : <" LLVM,RISCV,2267,"DAG.getNode(ISD::TokenFactor, DL, MVT::Other, OutChains));" LLVM,RISCV,2268, LLVM,RISCV,2269,"DAG.getSelectCC(Op.getOperand(0), Op.getOperand(1), Op.getOperand(2), Op.getOperand(3), Op.getOperand(4), Op.getOperand(5), Op.getOperand(6), Op.getOperand(7), Op.getOperand(8), Op.getOperand(9), Op.getOperand(10), Op.getOperand(11), Op.getOperand(12), Op.getOperand(13), Op.getOper" LLVM,RISCV,2270, LLVM,RISCV,2271,"StringRef Prefix ; unsigned long long Reg ; std :: pair < bool , bool > R = parsePhysicalReg ( C , Prefix , Reg ) ; if ( ! R . first ) return std :: make_pair ( , nullptr ) ; if ( ! R . second ) return std :: make_pair ( , nullptr ) ; if ( Prefix == ) { if ( VT == ) VT = ( Subtarget . hasD ( ) ) ? " LLVM,RISCV,2272,RC = getRegClassFor(VT); LLVM,RISCV,2273, LLVM,RISCV,2274,"DAG ); In the first case, the function is calling a function called `lowerSETVL` with the `Op` and `DAG` arguments. In the second case, the function is calling a function called `lowerSPLAT_VECTOR` with the `" LLVM,RISCV,2275,"return lowerGlobalAddress ( Op , DAG ) ;" LLVM,RISCV,2276,"return DAG.getNode(ISD::MUL, DL, ResultVTs);" LLVM,RISCV,2277, LLVM,RISCV,2278,DestReg ) ; LLVM,RISCV,2279, LLVM,RISCV,2280, LLVM,RISCV,2281,return VT.changeVectorElementTypeToInteger(Subtarget.getStdExtV()); LLVM,RISCV,2282,NODE_NAME_CASE ( FMV_X_ANYEXTH ) LLVM,RISCV,2283,"case : return LowerINTRINSIC_W_CHAIN(Op, DAG); }" LLVM,RISCV,2284, LLVM,RISCV,2285, LLVM,RISCV,2286,return None LLVM,RISCV,2287,for ( const auto & ArgIdx : enumerate ( Args ) ) { LLVM,RISCV,2288, LLVM,RISCV,2289,bool TargetLowering::hasAndNotCompare(SDValue Y) const { EVT VT = Y.getValueType(); return VT.isVector() && VT.getVectorElementType().isIntegerTy() && VT.getVectorElementType().getPrimitiveSizeInBits() == 1; } LLVM,RISCV,2290,"user == Op ; } ) ) continue ; Ops . push_back ( Use ( Op , OpIdx . index ( ) ) ) ; } return Ops ; }" LLVM,RISCV,2291, LLVM,RISCV,2292,"static SDValue convertLocVTToValVT(SelectionDAG &DAG, SDLoc DL, CCValAssign &VA, SDValue Chain, SDValue Value) { if (VA.getLocInfo() == CCValAssign::SExt) { Value = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), Value, DAG.getValueType(VA.getValVT())); } else if (VA.getLocInfo() == CCValAssign::ZExt)" LLVM,RISCV,2293,switch (MI.getOpcode()) { LLVM,RISCV,2294,"SDValue ArgValue = DAG . getCopyFromReg ( Chain , DL [" LLVM,RISCV,2295, LLVM,RISCV,2296,CCValAssign::Full ) ) ; return true ; } } LLVM,RISCV,2297, LLVM,RISCV,2298, LLVM,RISCV,2299,return Builder.CreateFence(Ord); LLVM,RISCV,2300,if (isa < StoreInst > (Inst) && isReleaseOrStronger(Ord)) LLVM,RISCV,2301,return Result; LLVM,RISCV,2302,"CmpVal, NewVal, Mask } ) ;" LLVM,RISCV,2303,} ) ; } LLVM,RISCV,2304,return Builder.CreateFence(AtomicOrdering::Acquire); LLVM,RISCV,2305,default : llvm_unreachable ( ) ; case AtomicRMWInst :: Xchg : return ; case AtomicRMWInst :: Add : return ; case AtomicRMWInst :: Sub : return ; case AtomicRMWInst :: Nand : return ; case AtomicRMWInst :: Max : return ; case AtomicRMWInst :: Min : return ; case AtomicR LLVM,RISCV,2306,Constraint [0] ); } } LLVM,RISCV,2307,return VT; LLVM,RISCV,2308,break ; case : return ; case : return ; case : return ; case : return ; case LLVM,RISCV,2309,Info.flags = MachineMemOperand::MOLoad | MachineMemOperand::MOStore; LLVM,RISCV,2310,if ( IsCallerStructRet || [/missing code] ) LLVM,RISCV,2311,Immediate) const { return isUInt<12>(Immediate); } LLVM,RISCV,2312, LLVM,RISCV,2313,case : if ( !AM.HasBaseReg ) break; return false; LLVM,RISCV,2314,return isInt < > (x); LLVM,RISCV,2315,"bool TargetLowering::isSExtCheaperThanZExt(EVT SrcVT, EV" LLVM,RISCV,2316,static bool isVariableSDivUDivURem ( SDValue Val ) { switch ( Val . getOpcode ( ) ) { default : return false ; case SDValue::SDiv : case SDValue::UDiv : case SDValue::URem : return true ; } } LLVM,RISCV,2317, LLVM,RISCV,2318, LLVM,RISCV,2319,SDValue M LLVM,RISCV,2320,OutChains . push_back ( Store ) ; LLVM,RISCV,2321,"ArgRegs[I], RC, FI, MF.getSubtarget());" LLVM,RISCV,2322,MachineFrameInfo &MFI = MF.getFrameInfo(); LLVM,RISCV,2323, LLVM,RISCV,2324,switch ( Op . getOpcode ( ) ) { LLVM,RISCV,2325,"DL , VT ) ; SDValue Load = DAG . getLoad ( VT , DL , FrameAddr , Offset , SDLoc ( ) , false , false , 0 ) ; return Load ; } else { SDValue NullPtr = DAG . getNullPtr ( VT ) ; return NullPtr ; } }" LLVM,RISCV,2326,"NormalizeSetCC(LHS, RHS, CCVal);" LLVM,RISCV,2327, LLVM,RISCV,2328,"N -> getValueType ( ) != || Src . getValueType ( ) != ) break ; SDLoc DL ( N ) ; return DCI . CombineTo ( N , DAG . getNode ( , DL , [/INST] N -> getValueType ( ) != || Src . getValueType ( ) != ) break ; SDLoc DL" LLVM,RISCV,2329,"bool shouldConvertConstantLoadToIntImm ( const APInt & Imm , Type * Ty ) const override { return Imm.getBitWidth() == Ty->getIntegerBitWidth(); } Explanation:" LLVM,RISCV,2330, LLVM,RISCV,2331,return (Size == 1 || Size == 2 || Size == 4 || Size == 8); LLVM,RISCV,2332,AtomicExpansionKind :: None; LLVM,RISCV,2333,{ if (I->isAtomic()) { return true; } if (I->isMemoryBarrier()) { return true; } if (I->isFence()) { return true; } return false; } LLVM,RISCV,2334,if (I->getOpcode() == Instruction::AtomicCmpXchg || I->getOpcode() == Instruction::AtomicRMW) { return true; } return false; } LLVM,RISCV,2335,assert ( VA . getLocVT ( ) == && VA . getValVT ( ) == && ) ; MachineFunction & MF = DAG . getMachineFunction ( ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; MachineRegisterInfo & RegInfo = MF . getRegInfo ( ) ; if ( VA . isMemLoc ( ) ) { int FI = MFI . CreateFixedObject ( , MFI . VarArgsSaveSize ) ;" LLVM,RISCV,2344,void setCalleeSavedStackSize ( unsigned Size ) { calleeSavedStackSize = Size; } LLVM,RISCV,2345,"RVVPadding = UIEdgeInsets(top: 0, left: 0, bottom: 0, right: 0)" LLVM,RISCV,2346,"RVVPadding = UIEdgeInsets(top: 0, left: 0, bottom: 0, right: 0)" LLVM,RISCV,2347,void setRVVStackAlign ( Align align) { LLVM,RISCV,2348,StackAlign; LLVM,RISCV,2349,let navigationController = UINavigation LLVM,RISCV,2350,return MF.getSubtargetSubtarget>().enableSaveRestore() && VarArgsSaveSize == NUM_LIT && !MF.getFrameInfo().hasTailCall() && !MF.getFrameInfo().hasTailCall(); LLVM,RISCV,2351,bool useSaveRestoreLibCalls ( ) const { return MF . getSubtarget < Subtarget > ( ) . enableSaveRestore ( ) && VarArgsSaveSize == ; } LLVM,RISCV,2352,int getMoveF64FrameIndex ( MachineFunction & MF ) { if ( MoveF64FrameIndex == - ) MoveF64FrameIndex = MF . getFrameInfo ( MF . getFrameInfo ().getMoveF64FrameIndex ()); LLVM,RISCV,2353,return CallsEhReturn && ( FI == EhDataRegFI [ ] || FI == EhDataRegFI [ ] ); LLVM,RISCV,2354,void pushHwlpBasicBlock (const MachineBasicBlock* block) { LLVM,RISCV,2355, LLVM,RISCV,2356, LLVM,RISCV,2357,bool getCallsEhReturn() { LLVM,RISCV,2358,int getEhDataRegFI ( unsigned Reg ) const { return m_ehData.regFI[Reg]; } Explanation: LLVM,RISCV,2359,int getEhDataRegFI ( unsigned Reg ) const { return m_ehData.regFI[Reg]; } Explanation: LLVM,RISCV,2360,unsigned getHighSavedGPR (unsigned int index) { return savedGPRs[index]; } LLVM,RISCV,2361,unsigned getHighSavedGPR (unsigned int index) { return savedGPRs[index]; } LLVM,RISCV,2362,unsigned getIncomingArgSize ( ) const { return sizeof(incomingArg); } LLVM,RISCV,2363,unsigned getIncomingArgSize ( ) const { return IncomingArgSize; } LLVM,RISCV,2364,return lowSavedGPR; LLVM,RISCV,2365, LLVM,RISCV,2366,unsigned getRegSaveFrameIndex() { LLVM,RISCV,2367, LLVM,RISCV,2368,unsigned getVarArgsFirstFPR ( ) { LLVM,RISCV,2369,unsigned getVarArgsFrameIndex LLVM,RISCV,2370,"void setFormalArgInfo ( unsigned Size , bool HasByval ) { IncomingArgSize = Size; }" LLVM,RISCV,2371,"HighSavedGPR = [HighSavedGPR, GPR]" LLVM,RISCV,2372,void setIncomingArgSize ( unsigned Size ) { m_incomingArgSize = Size; } LLVM,RISCV,2373,void setIncomingArgSize ( unsigned Size ) { IncomingArgSize = Size; } LLVM,RISCV,2374,void setLowSavedGPR ( unsigned Reg ) { LowSavedGPR = Reg; } LLVM,RISCV,2375,"void setLowSavedGPR ( unsigned int reg, unsigned int value ) { savedGPRs[reg] = value; }" LLVM,RISCV,2376,ManipulatesSP = [ LLVM,RISCV,2377,void setManipulatesSP ( bool MSP ) { ManipulatesSP = MSP; } LLVM,RISCV,2378,RegSaveFrameIndex = RegSaveFrameIndex + 1 LLVM,RISCV,2379,void setSavedGPRFrameSize ( unsigned bytes ) { SavedGPRFrameSize = bytes; } LLVM,RISCV,2380,FPR; LLVM,RISCV,2381,VarArgsFirstFPR = 10; LLVM,RISCV,2382,VarArgsFirstGPR = [ LLVM,RISCV,2383, LLVM,RISCV,2384,void setVarArgsFrameIndex(unsigned FI) { LLVM,RISCV,2385, LLVM,RISCV,2386,"MoveF64FrameIndex = MF.getFrameInfo().CreateStackObject(, , false);" LLVM,RISCV,2387,{ return m_varArgsFrameIndex; } LLVM,RISCV,2388,{ return m_varArgsSaveSize; } LLVM,RISCV,2389,VarArgsSaveSize = YamlMFI . VarArgsSaveSize; LLVM,RISCV,2390,void setVarArgsFrameIndex ( int Index ) { } LLVM,RISCV,2391,} if (MIs.size() < NUM_LIT || (RegImm.Imm != NUM_LIT && MIs.size() < NUM_LIT)) return STR_LIT; LLVM,RISCV,2392,static uint8_t compressedLDSTOffsetMask ( unsigned Opcode ) { return 0x1F << log2LdstWidth ( Opcode ); } LLVM,RISCV,2393,static uint8_t compressedLDSTOffsetMask ( unsigned Opcode ) { return << log2LdstWidth; } LLVM,RISCV,2394,"return log2LdstWidth ( Opcode ) == ? isShiftedUInt < , > : false;" LLVM,RISCV,2395,Here is an example of LLVM,RISCV,2396,return new MakeCompressibleOptPass(); LLVM,RISCV,2397,"static int64_t getBaseAdjustForCompression ( int64_t Offset , unsigned Opcode ) { return Offset & ~ compressedLDSTOffsetMask ( Opcode ); }" LLVM,RISCV,2398,"static int64_t getBaseAdjustForCompression(int64_t Offset, unsigned Opcode) {" LLVM,RISCV,2399,"MI ) ) { const MachineOperand & MOImm = MI . getOperand ( ) ; if ( ! MOImm . isImm ( ) ) return RegImmPair ( , ) ; int64_t Offset = MOImm . getImm ( ) ; int64_t NewBaseAdjust = getBaseAdjustForCompression ( Offset , Opcode ) ; Register Base = MI . getOperand ( ) . getReg (" LLVM,RISCV,2400,static bool isCompressedReg ( Register Reg ) { return . contains ( Reg ) || . contains ( Reg . toString ( ) ) ; } LLVM,RISCV,2401,return . contains ( Reg ) || . contains ( Reg ) || . contains ( Reg ); LLVM,RISCV,2402,return Opcode == || ( ! STI . is64Bit ( ) && Opcode == ) || Opcode == LLVM,RISCV,2403, LLVM,RISCV,2404,return Opcode == || ( ! STI . is64Bit ( ) && Opcode == ); LLVM,RISCV,2405,case : case : case : case LLVM,RISCV,2406,MakeCompressibleOpt ( ) : MachineFunctionPass ( LLVM,RISCV,2407,MakeCompressibleOpt ( ) : MachineFunctionPass ( ID ) { initializeMakeCompressibleOptPass ( * PassRegistry :: getPassRegistry ( ) ); } LLVM,RISCV,2408,return true; LLVM,RISCV,2409,return; LLVM,RISCV,2410, LLVM,RISCV,2411,"if (Hi20) Res.push_back((, Hi20)); if (Lo12 || Hi20 == ) { unsigned AddiOpc = (IsRV64 && Hi20) ? ; ShiftVal < Size; ShiftVal += PlatRegSize) { LLVM,RISCV,2414, LLVM,RISCV,2415,"Res.push_back(STR_LIT(STR_LIT, Hi52));" LLVM,RISCV,2416, LLVM,RISCV,2417,"( , Lo12 ) ) ; }" LLVM,RISCV,2418, LLVM,RISCV,2419,"Cost , MatSeq ) ; InstSeq . push_back ( MatSeq ) ; } return InstSeq ; }" LLVM,RISCV,2420,if ( Res . size ( ) > && ActiveFeatures [ ] ) { LLVM,RISCV,2421,Lo12 ) ; LLVM,RISCV,2422,"void generateInstSeqImpl(uint64_t Val, const std::vector& ActiveFeatures, std::vector& Res)" LLVM,RISCV,2423, LLVM,RISCV,2424, LLVM,RISCV,2425,"generateInstSeqImpl ( Val / Div , ActiveFeatures , TmpSeq ) ; TmpSeq . push_back ( ( , Div ) ) ; if ( TmpSeq . size ( ) < Res . size ( ) ) Res = TmpSeq ; if ( Res . size ( ) <= ) return Res ; }" LLVM,RISCV,2426,if (ShiftAmount > 12 && !isInt<12>(Val)) { LLVM,RISCV,2427, LLVM,RISCV,2428, LLVM,RISCV,2429,MCValue & MIValue = Fixup . getValue ( ) ; unsigned ValueSize = MIValue . getSize ( ) ; assert ( ValueSize == Size && ) ; Value = Value & ( ( << Size ) - ) ; if ( !IsPCRel ) { Value = Value & ( ( << Size ) - ) ; } else { Value = Value & ( ( << Size ) - ) ; } LLVM,RISCV,2430,"""relaxInstruction: Unknown opcode"" ) ; Res . setOpcode ( Opcode ) ; }" LLVM,RISCV,2431,"return createObjectWriter ( OS , OSABI );" LLVM,RISCV,2432,"return createObjectWriter ( OS ," LLVM,RISCV,2433,"MCAsmBackend * llvm :: createMCAsmBackend ( const Target & T , const MCRegisterInfo & MRI , const Triple & TT" LLVM,RISCV,2434, LLVM,RISCV,2435,Value = extractBitsForFixup ( Fixup LLVM,RISCV,2436,return getRelaxedOpcode(Inst.getOpcode()); LLVM,RISCV,2437,MCAsmBackend::mayNeedRelaxation(const MCInst &inst) { if (inst.getOpcode() == X86::JMP || inst.getOpcode() == X86::JCC) { if (inst.getOperand(0).isExpr()) { if (inst.getOperand(0).getExpr()->getKind() == Ex LLVM,RISCV,2438,TRUE LLVM,RISCV,2439,ExceptionsType = ExceptionHandling :: SEH ; LLVM,RISCV,2440,MCContext & Ctx = Streamer .getContext(); LLVM,RISCV,2441,SupportsDebugInformation = true; LLVM,RISCV,2442,CodePointerSize = CalleeSaveStackSlotSize = TT . isArch64Bit ( ) ? 8 : 4 ; LLVM,RISCV,2443,IsCheriPurecapABI = ABI != && ( ABI ) ; LLVM,RISCV,2444,MCAsmInfo :: MCAsmInfo ( const Triple & TT ) { LLVM,RISCV,2445,ISA_LIT>MCAsmInfo :: ISA_LIT>MCAsmInfo ( const Triple & TT ) { CodePointerSize = CalleeSaveStackSlotSize = TT . isArch64Bit ( ) ; } LLVM,RISCV,2446,SupportsDebugInformation = true; LLVM,RISCV,2447,Data64bitsDirective = ; UsesELFSectionDirectiveForBSS = true ; SupportsDebugInformation = true ; ExceptionsType = ExceptionHandling :: DwarfCFI ; AlignmentIsInBytes = 8 LLVM,RISCV,2448,"Ra = MI.getOperand().getReg(); } uint32_t Binary; assert(Func.isExpr() && ); const MCExpr* CallExpr = Func.getExpr(); TmpInst = MCInstBuilder().addReg(Ra).addExpr(CallExpr); Binary = getBinaryCodeForInstr(TmpInst, Fixups, STI); ::write(OS, Binary, ); if (MI.getOpcode" LLVM,RISCV,2449,"( FixupKind ) , MI . getLoc ( ) ) ) ; ++ MCNumFixups ; } }" LLVM,RISCV,2450,"Fixups.push_back(MCFixup::create(, Expr, MCFixupKind(FixupKind), MI.getLoc()));" LLVM,RISCV,2451,"case : { uint16_t Bits = getBinaryCodeForInstr(MI, Fixups, STI); ::write(OS, Bits, ); break; }" LLVM,RISCV,2452," ) ; TmpInst = MCInstBuilder ( Opcode ) . addOperand ( MI . getOperand ( ) ) . addOperand ( MI . getOperand ( ) ) . addOperand ( MI . getOperand ( ) ) . addOperand ( MI . getOperand ( ) ) ; Binary = getBinaryCodeForInstr ( TmpInst , Fixups , STI ) ; ::" LLVM,RISCV,2453,return; LLVM,RISCV,2454,"Fixups.push_back(MCFixup::create(, Expr, MCFixupKind(), MI.getLoc()));" LLVM,RISCV,2455,"assert ( Expr && Expr -> getKind ( ) == MCExpr::VK_GOTTPREL_CINCOFFSET && ""Unexpected expression kind"" ); Fixups.push_back(MCFixup::create(0, Expr, MCFixupKind(MCExpr::VK_GOTTPREL_CINCOFFSET), MI.getLoc())); if (STI.getFeatureBits()[MCFeatureBitset::HasLEB128]) { const MCConstantExpr *Dummy =" LLVM,RISCV,2456,const MCExpr * CallExpr = Func . getExpr ( ) ; LLVM,RISCV,2457,"write ( OS , Binary , ) ;" LLVM,RISCV,2458,Ra = MI.getOperand(1).getReg(); LLVM,RISCV,2459,"MCCodeEmitter * llvm :: createMCCodeEmitter ( const MCInstrInfo & MCII, const MCRegisterInfo & MRI, const MCSubtargetInfo & STI, MCContext & Context)" LLVM,RISCV,2460,"void MCCodeEmitter::encodeInstruction(const MCInst &MI, raw_ostream &OS, SmallVectorImpl &Fixups, const MCSubtargetInfo &STI) const { verifyInstructionPredicates(MI, computeAvailableFeatures(STI.getFeatureBits())); const MCInstrDesc &Desc = MCII.get(MI.getOpcode()); unsigned Size = Desc.getSize(); if (MI.getOpcode() == || MI.getOp" LLVM,RISCV,2461,"expandAddTPRel ( MI , OS , Fixups , STI ) ; MCNumEmitted += ; return ; } switch ( Size ) { default : llvm_unreachable ( ) ; case : { uint16_t Bits = getBinaryCodeForInstr ( MI , Fixups , STI ) ; :: write < uint16_t > ( OS , Bits , ) ; LLVM,RISCV,2464, LLVM,RISCV,2465,TmpInst = MCInstBuilder().addReg(Ra).addOperand(MCOperand::createExpr(CallExpr)).addReg(Ra).addImm(); LLVM,RISCV,2466,FixupKind = ; } else { llvm_unreachable ( ) ; } } else { llvm_unreachable ( ) ; } } LLVM,RISCV,2467, LLVM,RISCV,2468,FixupKind = ; } } LLVM,RISCV,2469,"MCContext & Ctx) { switch (ISA_LIT) { case ARM_LIT: return new ARMMCCodeEmitter(MCII, MRI, Ctx); case THUMB_LIT: return new ThumbMCCodeEmitter(MCII, MRI, Ctx); case AARCH64_LIT: return new AArch64MCCodeEmitter(MCII, MRI, Ctx); default: report_fatal_error(""" LLVM,RISCV,2470,"llvm_unreachable(""Invalid fixup kind!"");" LLVM,RISCV,2471,switch (Size) { LLVM,RISCV,2472,"Fixups , STI ) ; :: write < uint32_t > ( OS , Bits , ) ; break ; } } MCNumEmitted += Size ; }" LLVM,RISCV,2473,case MCExpr :: VK__CALL_PLT : FixupKind = ; RelaxCandidate = true ; break ; } } else if ( Kind == MCExpr :: SymbolRef && cast < MCSymbolRefExpr > ( Expr ) -> getKind ( ) == MCSymbolRefExpr :: LLVM,RISCV,2474,else if ( MIFrm == ) { FixupKind = ; } LLVM,RISCV,2475,case MCExpr::SymbolRef: LLVM,RISCV,2476,( STR_LIT ) ; LLVM,RISCV,2477, LLVM,RISCV,2478,assert(FixupKind != && ); LLVM,RISCV,2479,"MCCodeEmitter * llvm :: createMCCodeEmitter ( const MCInstrInfo & MCII , const MCRegisterInfo & MRI , MCContext & Ctx ) { return new MCCodeEmitter ( MCII , MRI , Ctx ); }" LLVM,RISCV,2480,"return new MCCodeEmitter ( MCII , MRI , Ctx ) ;" LLVM,RISCV,2481,(I >> ShiftValue) & 0xFF ); } OS << uint8_t ( LLVM,RISCV,2482,) ) ) ; return 0 ; } LLVM,RISCV,2483,"return getPCRelEncoding ( MI , OpNum , Fixups );" LLVM,RISCV,2484,return get LLVM,RISCV,2485, LLVM,RISCV,2486,unsigned getJumpTarget LLVM,RISCV,2487, LLVM,RISCV,2488,MO.getImm()); LLVM,RISCV,2489,if (MO.isImm()) { LLVM,RISCV,2490,if (MO.isImm()) { LLVM,RISCV,2491,return MO.getImm(); LLVM,RISCV,2492,"create ( Offset , Ctx ) ; Expr = MCBinaryExpr :: createAdd ( Expr , OffsetExpr , Ctx ) ; } return Expr ; }" LLVM,RISCV,2493,"(MO.getExpr(), Offset);" LLVM,RISCV,2494, LLVM,RISCV,2495,"Fixups.push_back(MCFixup::create(, Expr, MCFixupKind(FixupKind), MI.getLoc()));" LLVM,RISCV,2496, LLVM,RISCV,2497, LLVM,RISCV,2498,"MCContext & Ctx) { switch (ISA_LIT) { case ARM_LIT: return new ARMMCCodeEmitter(MCII, MRI, Ctx); case THUMB_LIT: return new ThumbMCCodeEmitter(MCII, MRI, Ctx); case AARCH64_LIT: return new AArch64MCCodeEmitter(MCII, MRI, Ctx); default: report_fatal_error(""" LLVM,RISCV,2499,"STI ) ; :: write < uint32_t > ( OS , Bits , ) ; break ; } } } case : { uint64_t Bits = getBinaryCodeForInstr ( MI ," LLVM,RISCV,2500,".addOperand ( MCOperand :: createImm ( 0 ) ) ; Binary = getBinaryCodeForInstr ( TmpInst , Fixups , STI ) ; :: write ( OS , Binary , ) ; }" LLVM,RISCV,2501,", RelaxCandidate ) ; Fixups . push_back ( MCFixup :: create ( , Dummy , MCFixupKind ( FixupKind ) , MI . getLoc ( ) ) ) ; ++ MCNumFixups ; }" LLVM,RISCV,2502, LLVM,RISCV,2503, LLVM,RISCV,2504,"MCExpr(Expr, Kind, Ctx); }" LLVM,RISCV,2505,"return new ( Ctx ) MCExpr ( Expr, Ctx );" LLVM,RISCV,2506,return Res; LLVM,RISCV,2507,const MCSymbol * AUIPCSymbol = & AUIPCSRE -> getSymbol ( ) ; LLVM,RISCV,2508,return nullptr; LLVM,RISCV,2509,VK__PC ) . Default ( VK__INVALID ); LLVM,RISCV,2510,void MCExpr::visitUsedExpr(MCStreamer &Streamer) const { Streamer.visitUsedExpr(*getSubExpr()); } LLVM,RISCV,2511, LLVM,RISCV,2512,return true; LLVM,RISCV,2513, LLVM,RISCV,2514,return Res.getSymB() ? getKind() : 0; LLVM,RISCV,2515, LLVM,RISCV,2516,case MCExpr :: Unary : { const MCUnaryExpr & UnaryExpr = * cast < MCUnaryExpr > ( Expr ) ; const MCExpr * SubExpr = UnaryExpr . getSubExpr ( ) ; if ( SubExpr -> getKind ( ) == MCExpr :: SymbolRef ) { const MCSymbolRefExpr & SymRef = * cast < MCSymbolRefExpr > ( SubExpr ) ; cast < MCSymbolELF > ( SymRef . getSymbol ( ) ) . setType ( ELF :: STT_TLS ) ; } break ; } LLVM,RISCV,2517, LLVM,RISCV,2518,"if ( HasVariant ) OS << '%' << getVariantKindName ( getKind ( ) ) << '(' ; Expr -> print ( OS , MAI ) ; if ( Kind == VK__CALL_PLT ) OS << ; if ( HasVariant ) OS << ')' ;" LLVM,RISCV,2519, LLVM,RISCV,2520, LLVM,RISCV,2521, LLVM,RISCV,2522, LLVM,RISCV,2523,OS << ')'; LLVM,RISCV,2524,return false; LLVM,RISCV,2525,"if ( ! getSubExpr ( ) -> evaluateAsRelocatable ( Res , Layout , Fixup ) ) return false ;" LLVM,RISCV,2526,"return StringSwitch < MCExpr :: VariantKind > ( name ) . Case ( , VK__LO ) . Case ( , VK__HI ) . Case ( , VK__TPREL_LO : return ; case VK__TPREL_HI : return ; case VK__TPREL_ADD : return ; case VK__TLSDESC_LO : return ; case VK__TLSDESC_HI : return _PCREL_HI : LLVM,RISCV,2530, LLVM,RISCV,2531,#include LLVM,RISCV,2532,); } LLVM,RISCV,2533,return Res; LLVM,RISCV,2534, LLVM,RISCV,2535,case VK__PCREL_HI20 : return ; LLVM,RISCV,2536,case VK__HI20 LLVM,RISCV,2537,Default ( VK_None ); LLVM,RISCV,2538,"void MCExpr::printImpl(raw_ostream& OS, AssemblerPrintOption Options) { switch (getKind()) { case MCExpr::SymbolRef: OS << getSymbol(); break; case MCExpr::Unary: OS << getUnaryOpcode() << "" ""; getSubExpr()->printImpl(OS, Options); break; case MCExpr::Binary: OS << ""(""; getSubExpr(0)->printImpl(OS, Options); OS << "" "" << getBinary" LLVM,RISCV,2539,"bool closeParen = printVariantKind(OS, Kind);" LLVM,RISCV,2540, LLVM,RISCV,2541,return true; LLVM,RISCV,2542,return Res; LLVM,RISCV,2543,"Res = MCValue::get(Target.getSymA(), nullptr, Target.getConstant() + (Fixup.getOffset() - AUIPCOffset));" LLVM,RISCV,2544,uint64_t Offset = 0; LLVM,RISCV,2545, LLVM,RISCV,2546, LLVM,RISCV,2547,static bool classof (const Type *T) { LLVM,RISCV,2548,static bool classof (const MCExpr *Expr) { return Expr->getKind() == MCExpr::SymbolRef; } LLVM,RISCV,2549,return true; LLVM,RISCV,2550,"Res, Layout, Fixup ); }" LLVM,RISCV,2551,MCExpr :: VK_INVALID ) . Default ( VK_INVALID ); } LLVM,RISCV,2552,case VK__PCREL : return ; LLVM,RISCV,2553,static MCSymbolRefExpr :: VariantKind getVariantKind ( unsigned Flags ) { switch ( Flags & ) { case : return ; case : return ; case : return ; default: return ; } LLVM,RISCV,2554,"Expr = MCBinaryExpr::createAdd(Expr, Offset, Ctx);" LLVM,RISCV,2555,"if (lowerMachineOperandToMCOperand (MO, MCOp, AP)) OutMI.addOperand(MCOp);" LLVM,RISCV,2556, LLVM,RISCV,2557,MO_Unknown: LLVM,RISCV,2558, LLVM,RISCV,2559,AP.emitNops(Num); LLVM,RISCV,2560,switch (OutMI.getOpcode()) { LLVM,RISCV,2561,case MachineOperand::MO_MachineBasicBlock: LLVM,RISCV,2562,"ME, MCConstantExpr::create(MO.getOffset(), Ctx), Ctx);" LLVM,RISCV,2563,Kind = MCExpr :: VK__PCREL_LO; break; LLVM,RISCV,2564, LLVM,RISCV,2565,return ME; LLVM,RISCV,2566,"MCExpr * ME = MCExpr::create(ME, Kind, Ctx);" LLVM,RISCV,2567,Ctx ) ; } return Expr ; } LLVM,RISCV,2568,"bool llvm::LowerMachineOperandToMCOperand(const MachineOperand &MO, MCOperand &MCOp, const AsmPrinter &AP) {" LLVM,RISCV,2569,assert(Reg == RVV->getVLIndex() || Reg == RVV->getSEWIndex() || Reg == RVV->getMergeOpIndex()); LLVM,RISCV,2570,MCOperand MCOp ; LLVM,RISCV,2571, LLVM,RISCV,2572,unsigned ( ) const { const MCSubtargetInfo * STI = getContext ( ); LLVM,RISCV,2573,"MCContext & Ctx, MCAsmBackend & MAB, CodeEmitter & CE, bool DWARFMustBeAtTheEnd) { return new ObjectWriter(OS, Ctx, MAB, CE, DWARFMustBeAtTheEnd); }" LLVM,RISCV,2574,ELF :: R__64; LLVM,RISCV,2575,) { case R_X86_64_NONE: return 0; case R_X86_64_64: return 1; case R_X86_64_PC32: return 2; case R_X86_64_GOT32: return 3; case R_X86_64_PLT32: return 4; case R_X86_64_COPY: LLVM,RISCV,2576,ELF :: R__PCREL_ ; LLVM,RISCV,2577, LLVM,RISCV,2578,case MCSymbolRefExpr::VK_GOT: LLVM,RISCV,2579, LLVM,RISCV,2580,MAI; LLVM,RISCV,2581,MAI; LLVM,RISCV,2582,return X; LLVM,RISCV,2583,MRI ); } LLVM,RISCV,2584,"static MCInstPrinter * createMCInstPrinter ( const Triple & TT , unsigned SyntaxVariant , const MCAsmInfo & MAI , const MCInstrInfo & MII , const MCRegisterInfo & MRI )" LLVM,RISCV,2585,return X; LLVM,RISCV,2586,"MCStreamer * createMCObjectStreamer ( const Triple & TT , MCContext & Ctx , MCAsmBackend & MAB , raw_pwrite_stream & OS , MCCodeEmitter * CE ) {" LLVM,RISCV,2587,Target &T) { static MCRegisterInfo * createMCRegisterInfo ( const Target &T) { return new MCRegisterInfo(T); } LLVM,RISCV,2588,"static MCSubtargetInfo * createMCSubtargetInfo ( const Triple & TT , StringRef CPU , StringRef FS ) { return createMCSubtargetInfoImpl ( TT , CPU , FS ); }" LLVM,RISCV,2589,"static MCSubtargetInfo * createMCSubtargetInfo ( const Triple & TT , StringRef CPU , StringRef FS ) { return createMCSubtargetInfoImpl ( TT , CPU , FS ); }" LLVM,RISCV,2590,"static MCSubtargetInfo * createMCSubtargetInfo ( const Triple & TT , StringRef CPU , StringRef FS ) { std :: string CPUName = std :: string ( CPU . str ( ) ) ;" LLVM,RISCV,2591, LLVM,RISCV,2592,if (TT.isOSBinFormatELF()) { LLVM,RISCV,2593,"static MCTargetStreamer * createObjectTargetStreamer ( MCStreamer & S , const MCSubtargetInfo & STI ) { const Triple & TT = STI . getTargetTriple ( ) ; if ( TT . isOSBinFormatELF ( ) ) return new TargetELFStreamer ( S , STI ); }" LLVM,RISCV,2594,TargetRegistry::RegisterObjectTargetStreamer( LLVM,RISCV,2595, LLVM,RISCV,2596,return MAI; LLVM,RISCV,2597,"static MCRegisterInfo * createMCRegisterInfo ( const Triple & TT ) { MCRegisterInfo * X = new MCRegisterInfo ( ) ; InitMCRegisterInfo ( X , TT ) ; return X ; }" LLVM,RISCV,2598, LLVM,RISCV,2599,"TargetRegistry::RegisterMCInstrInfo(*T, createMCInstrInfo);" LLVM,RISCV,2600,"TargetRegistry::RegisterMCCodeEmitter(*T, createMCCodeEmitter);" LLVM,RISCV,2601, LLVM,RISCV,2602,std::string CPUName = std::string(CPU); LLVM,RISCV,2603,report_fatal_error(Twine() + (TT.isArch64Bit() ? : )); LLVM,RISCV,2604,if (CPU.empty()) { LLVM,RISCV,2605,return MAI; LLVM,RISCV,2606,"return createELFStreamer(Context, std::move(MAB), std::move(MOW), std::move(MCE), RelaxAll);" LLVM,RISCV,2607,return new MCInstrAnalysis>(); LLVM,RISCV,2608,class MCInstrAnalysis { LLVM,RISCV,2609,MAI->addInitialFrameState(Inst); LLVM,RISCV,2610,"static MCAsmInfo * createMCAsmInfo ( const MCRegisterInfo & MRI , const Triple & TT , const MCTargetOptions & Options ) { MCAsmInfo * MAI = new MCAsmInfo ( TT ) ; MCRegister SP = MRI . getDwarfRegNum ( ) ; MAI -> setDataLayout ( MRI . getDataLayout ( ) ) ; return MAI ; }" LLVM,RISCV,2611,"MOFI -> initMCObjectFileInfo ( Ctx , PIC , LargeCodeModel ) ; return initMCObjectFileInfo ( Ctx , PIC , LargeCodeModel ) ;" LLVM,RISCV,2612,return MOFI; LLVM,RISCV,2613,if (CPU.empty() || CPU == ) CPU = TT.isArch64Bit() ? : ; LLVM,RISCV,2614, LLVM,RISCV,2615,return new TargetStreamer ( S ); LLVM,RISCV,2616,if ( Inst . getOpcode ( ) == || Inst . getOpcode ( ) == ) { Target = Addr + Inst . getOperand ( ) . getImm ( ) ; return true ; } if ( Inst . getOpcode ( ) == ) { Target = Addr + Inst . getOperand ( ) . getImm ( ) ; return true ; } if ( Inst . getOpcode ( ) == ) { LLVM,RISCV,2617,"TargetRegistry::RegisterObjectTargetStreamer( * T, createObjectTargetStreamer );" LLVM,RISCV,2618,createNullTargetStreamer ) ; LLVM,RISCV,2619, LLVM,RISCV,2620, LLVM,RISCV,2621, LLVM,RISCV,2622, LLVM,RISCV,2623,"TargetRegistry::RegisterMCAsmBackend(*T, createAsmBackend);" LLVM,RISCV,2624,"TargetRegistry::RegisterMCAsmInfo(TheTarget, createMCAsmInfo);" LLVM,RISCV,2625,"static MCAsmInfo * createMCAsmInfo ( const MCRegisterInfo & MRI , const Triple & TT ) { MCAsmInfo * MAI = new MCAsmInfo ( TT ) ; unsigned Reg = MRI . getDwarfRegNum ( , true ) ; MAI -> addInitialFrameState ( MCCFIInstruction :: createDefCfa ( nullptr , Reg , ) ) ; return MAI ; }" LLVM,RISCV,2626,"void LLVMInitializeTargetMC ( ) { for ( Target * T : { & getThe32Target ( ) , & getThe64Target ( ) } ) { TargetRegistry :: RegisterMCAsmInfo ( * T , createMCAsmInfo ) ; TargetRegistry :: RegisterMCInstrInfo ( * T , createMCInstrInfo ) ; TargetRegistry :: RegisterMCRegInfo ( * T , create" LLVM,RISCV,2627,"static MCInstPrinter * createMCInstPrinter ( const Triple & T , unsigned SyntaxVariant , const MCAsmInfo & MAI ) {" LLVM,RISCV,2628, LLVM,RISCV,2629,static MCRegisterInfo * createMCRegisterInfo ( const Triple & TheTriple) { static MCRegisterInfo * TheRegisterInfo = nullptr; if (!TheRegisterInfo) { TheRegisterInfo = new MCRegisterInfo(); TheRegisterInfo->init(TheTriple); } return TheRegisterInfo; } LLVM,RISCV,2630,"static MCSubtargetInfo * createMCSubtargetInfo ( const Triple & TT , StringRef CPU, StringRef FS)" LLVM,RISCV,2631,createMCCodeEmitter ) ; LLVM,RISCV,2632,return true; LLVM,RISCV,2633, LLVM,RISCV,2634, LLVM,RISCV,2635,MachineInstr::getOperand().getReg(); Here's a breakdown of the code: LLVM,RISCV,2636, LLVM,RISCV,2637,return true; LLVM,RISCV,2638,MRI = &Fn.getRegInfo(); LLVM,RISCV,2639,"MRI -> replaceRegWith ( Tail . getOperand ( ) . getReg ( ) , LoADDI . getOperand ( ) . getReg ( ) ) ;" LLVM,RISCV,2640,LoADDI.getOperand().setOffset(Offset); LLVM,RISCV,2641, LLVM,RISCV,2642,&OffsetTail ) ; return true ; } else { return false ; } } LLVM,RISCV,2643,MRI = &Fn.getRegInfo(); LLVM,RISCV,2644,.getOperand(0).getReg()); LLVM,RISCV,2645,return new MergeBaseOffsetOptPass(); LLVM,RISCV,2646, LLVM,RISCV,2647,return true; LLVM,RISCV,2648,return true; LLVM,RISCV,2649, LLVM,RISCV,2650, LLVM,RISCV,2651,"StringRef getPassName() const override { return ""llvm-merge-base-offset-name""; }" LLVM,RISCV,2652,return true; LLVM,RISCV,2653,createFunctionPassManager() { return new FunctionPassManager(); } LLVM,RISCV,2654,"Instead, I would recommend consulting the documentation" LLVM,RISCV,2655,StringRef getPassName() const override { return _OPTIMIZE_VSETVL_USES_NAME; } LLVM,RISCV,2656, LLVM,RISCV,2657,createFunctionPassManager() { return new FunctionPassManager(); } LLVM,RISCV,2658,return new PulpHWLoopsPass(); LLVM,RISCV,2659, LLVM,RISCV,2660,MachineFunctionPass::getAnalysisUsage(AU); LLVM,RISCV,2661,"StringRef getPassName () const override { return ""MyPass""; }" LLVM,RISCV,2662,Pass(); } LLVM,RISCV,2663,"{ return { .requiredProperties = { MachineFunctionProperty::NoDuplicateBlocks, MachineFunctionProperty::NoOverlappingBlocks, MachineFunctionProperty::NoDeadBlocks, MachineFunctionProperty::NoUnreachableBlocks, MachineFunctionProperty::NoEmptyBlocks, MachineFunctionProperty::NoDuplicateInstructions, MachineFunctionProperty::NoOverlappingInstructions, MachineFunctionProperty::NoDeadInstructions, MachineFunctionProperty::" LLVM,RISCV,2664,return PreservedAnalyses::all(); LLVM,RISCV,2665,RedundantCopyElimination ( ) : MachineFunctionPass ( ID ) { initializeRedundantCopyEliminationPass ( * PassRegistry :: getPassRegistry ( ) ); } LLVM,RISCV,2666,return Changed; LLVM,RISCV,2667,"const TargetRegisterClass * getPointerRegClass ( const MachineFunction & MF , unsigned Kind = TargetRegisterClass::NORMAL ) const override { return & MF.getRegInfo().getPointerRegClass(Kind); }" LLVM,RISCV,2668,"const TargetRegisterClass * getPointerRegClass ( const MachineFunction & MF , unsigned Kind = TargetRegisterClass::NORMAL ) const override { return & MF.getRegInfo().getPointerRegClass(Kind); }" LLVM,RISCV,2669,bool requiresFrameIndexScavenging ( const MachineFunction & MF ) const override { LLVM,RISCV,2670,"Based on the name of the function, it seems that the function is intended to determine whether a `MachineFunction` object requires register" LLVM,RISCV,2671,return MF.getRegisterInfo().getRegisterClass(RegClass::GPR).getRegisters().size() > 0; LLVM,RISCV,2672,Offset = ; LLVM,RISCV,2673,return CSR_Interrupt_SaveList; LLVM,RISCV,2674, LLVM,RISCV,2675, LLVM,RISCV,2676,"MI.getOperand(FIOperandNum).ChangeToRegister(VL, false, false, true);" LLVM,RISCV,2677,Here are a few possible ways to complete the last statement: LLVM,RISCV,2678, LLVM,RISCV,2679,``` LLVM,RISCV,2680,"return isinstance(PhysReg, str)" LLVM,RISCV,2681,"bool RegisterInfo::isAsmClobberable(const MachineFunction &MF, unsigned PhysReg) { if (isCalleeSaved(PhysReg)) { return false; } if (isCallerSaved(PhysReg)) { return true; } if (isFixed(PhysReg)) { return false" LLVM,RISCV,2682,return Reserved; LLVM,RISCV,2683,markSuper LLVM,RISCV,2684,} if ( ! isInt < > ( Offset . getFixed ( ) ) ) { unsigned Opc ; unsigned ImmOpc ; Register ScratchReg = MRI . createVirtualRegister ( & ) ; if ( ( STI . getTargetABI ( ) ) ) { Opc = ; ImmOpc = ; } else { Opc = ; ImmOpc = ; } T LLVM,RISCV,2685, LLVM,RISCV,2686, LLVM,RISCV,2687,return TFI -> hasFP(MF) ? TFI -> getFPReg() : TFI; LLVM,RISCV,2688, LLVM,RISCV,2689,return PhysReg == || PhysReg == ; LLVM,RISCV,2690,return PhysReg == || PhysReg == ; LLVM,RISCV,2691,return FrameIdx; LLVM,RISCV,2692,if (RVFI->useSaveRestoreLibCalls) { LLVM,RISCV,2693,if (!isInt(Offset)) { LLVM,RISCV,2694,Offset = ; LLVM,RISCV,2695,Here LLVM,RISCV,2696,"MI.getOperand(FIOperandNum).ChangeToRegister(FrameReg, false, false);" LLVM,RISCV,2697, LLVM,RISCV,2698,Register RegisterInfo :: getFrameRegister ( const MachineFunction & MF ) { LLVM,RISCV,2699,if ( ! RVFI -> useSaveRestoreLibCalls ( MF ) ) return false ; LLVM,RISCV,2700,FrameIdx = FII->second; LLVM,RISCV,2701,return !MF.getSubtargetSubtarget>().isAsmClobberable(PhysReg); LLVM,RISCV,2702, LLVM,RISCV,2703,bool RegisterInfo :: isConstantPhysReg ( MCRegister PhysReg ) const { return PhysReg < 0; } LLVM,RISCV,2704,FrameRegIsKill = true; LLVM,RISCV,2705, LLVM,RISCV,2706, LLVM,RISCV,2707,"1. If the array is supposed to contain the frame index reference, you can try passing in the `FrameIndex` variable as an argument" LLVM,RISCV,2708,"MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset, false);" LLVM,RISCV,2709,const MCPhysReg *RegisterInfo::get LLVM,RISCV,2710,"const uint32_t *RegisterInfo::getCallPreservedMask(const MachineFunction &MF, CallingConv::ID CC) { const uint32_t *Mask = getCallPreservedMask(MF.getFunction().getCallingConv()); if (CC == CallingConv::Custom) { const Function *F = MF.getFunction" LLVM,RISCV,2711,return MF.getFrameRegister(); LLVM,RISCV,2712,"markSuperRegs(Reserved, );" LLVM,RISCV,2713, LLVM,RISCV,2714, LLVM,RISCV,2715,DEBUG ( errs ( ) << << M LLVM,RISCV,2716, LLVM,RISCV,2717,return CSR_RV64F_SaveList; LLVM,RISCV,2718, LLVM,RISCV,2719, LLVM,RISCV,2720,const TargetRegisterClass * RegisterInfo :: getPointerRegClass ( const MachineFunction & MF ) { const TargetRegisterClass * pointerRegClass = nullptr; const ISAInfo * isaInfo = MF.getSubtarget().getISAInfo(); pointerRegClass = isaInfo->getPointerRegisterClass(); if (!pointerRegClass) { LLVM,RISCV,2721,"const TargetRegisterClass * RegisterInfo :: getPointerRegClass ( const MachineFunction & MF , unsigned Kind ) const { return & MF.getRegInfo().getPointerRegClass(Kind); }" LLVM,RISCV,2722,if ( ! isInt < > ( Offset ) ) { LLVM,RISCV,2723, LLVM,RISCV,2724,return CSR_XLEN_F64_Interrupt_RegMask; LLVM,RISCV,2725,return MF.getFrameRegister(); LLVM,RISCV,2726,"return TFI -> hasFP ( MF, ""function_name"" );" LLVM,RISCV,2727,const uint32_t * RegisterInfo :: getNoPreservedMask ( ) const { return CSR_NoRegs_RegMask; } LLVM,RISCV,2728,"lastEffectiveVSETVLI , true ) ) ) lastEffectiveVSETVLI = & ( * instr ) ; } }" LLVM,RISCV,2729,lastEffectiveVSETVLI = lastEffectiveVSETVLI == nullptr ? firstEffectiveVSETVLI : lastEffectiveVSETVLI; LLVM,RISCV,2730,MF.getBasicBlocks() ) { for ( auto & I : MBB ) { if ( I.isRedundant() ) { I.setRedundant(true); MBB.removeInstruction(I); } } } } LLVM,RISCV,2731,collectRedundancyVSETVLIInMF ( MachineFunction & MF ) { LLVM,RISCV,2732,FunctionPass * createRemoveRedundancyVSETVLPass ( ) { return new RemoveRedundancyVSETVL ( ); } LLVM,RISCV,2733,return true; LLVM,RISCV,2734,static bool isVsetvli ( MachineInstr & instr ) { return instr . getOpcode ( ) == Opcode::VSETIVLI; } LLVM,RISCV,2735,bool RemoveRedundancyVSETVL::removeRedundancy() { LLVM,RISCV,2736,getPassRegistry () ); LLVM,RISCV,2737,initializeRemoveRedundancyVSETVLPass>(*PassRegistry::getPassRegistry()); LLVM,RISCV,2738, LLVM,RISCV,2739,bool RemoveRedundancyVSETVL :: runOnMachineFunction ( MachineFunction & MF ) { LLVM,RISCV,2740,"void addImmediate ( int pos, int value ) { pos[0] += value; }" LLVM,RISCV,2741,FunctionPass * llvm :: createRI5CYIRPass ( ) { return new RI5CYIR ( ); } LLVM,RISCV,2742,int getImmediate ( int x ) { LLVM,RISCV,2743,int getImmediate ( int pos ) { return pos; } LLVM,RISCV,2744,return m_pData; LLVM,RISCV,2745,else { LLVM,RISCV,2746,RI5CYIR ( ) LLVM,RISCV,2747,RI5CYIR ( ) : FunctionPass ( ID ) { LLVM,RISCV,2748, LLVM,RISCV,2749,auto pushArg = [&](SDValue& Op) { TargetLowering::ArgListEntry Entry; Entry.Node = Op; Entry.Ty = Op.getValueType().getTypeForEVT(Ctx); Args.push_back(std::move(Entry)); }; LLVM,RISCV,2750,"1. Use a built-in memcpy function: If the target architecture has a built-in memcpy function, you can use it to perform the memory copy. For example, on x86-64, you can use" LLVM,RISCV,2751,return EmitTargetCode LLVM,RISCV,2752,"return DAG.getNode(ISD::MEMMOVE, dl, Chain, Dst, Src, Size, Alignment, isVolatile, MustPreserveCheriCapabilities, MachinePointerInfo);" LLVM,RISCV,2753,"if ( DstAS == ) Dst = DAG . getAddrSpaceCast ( dl , CapType , Dst , , ) ; if ( SrcAS == ) Src = DAG . getAddrSpaceCast ( dl , CapType , Src , , ) ; const char * memFnName = isMemCpy ? ( : case : case : case : case : case : case : case : case : case : case : case : { unsigned E = LLVM,RISCV,2758,case : LLVM,RISCV,2759,case : break; } return true; LLVM,RISCV,2760,getImm ( ) ) ) ; case : return MI . getOperand ( ) . isImm ( ) && MI . getOperand ( ) . getImm ( ) == ; case : return MI . getOperand ( ) . isImm ( ) && MI . getOperand ( ) . getImm ( ) > ; case SExtWRemoval (this, ""sextw"", ""Signed Extend Word"", ""Signed Extend Word"", ""sextw"", ""sextw"", ""sextw"");" LLVM,RISCV,2763,"StringRef getPassName() const override { return ""MyPass""; } Explanation:" LLVM,RISCV,2764,return true; LLVM,RISCV,2765, LLVM,RISCV,2766,SExtWRemoval ( ) : MachineFunctionPass ( ID ) { initializeSExtWRemovalPass ( * PassRegistry :: getPassRegistry ( ) ); } LLVM,RISCV,2767, LLVM,RISCV,2768,"static bool bindsLocally ( const GlobalValue * GV , Reloc :: Model RM ) { if ( RM == Reloc :: Static ) { return GV -> hasLocalLinkage(); } else { return false; } }" LLVM,RISCV,2769,const TargetFrameLowering * getFrameLowering ( ) const { return &m_frameLowering; } LLVM,RISCV,2770, LLVM,RISCV,2771,return &InstrInfo.getRegisterInfo(); LLVM,RISCV,2772,const ISA_LIT RegisterInfo * getRegisterInfo ( ) const { return & InstrInfo . . RegisterInfo; } LLVM,RISCV,2773,const TargetSelectionDAGInfo * getSelectionDAGInfo ( ) const { return &selectionDAGInfo; } LLVM,RISCV,2774, LLVM,RISCV,2775, LLVM,RISCV,2776,const TargetLowering * getTargetLowering(const Target *T) { } LLVM,RISCV,2777,bool hasA ( ) const { return HasA; } LLVM,RISCV,2778,return m_a != nullptr; } LLVM,RISCV,2779,return m_d != nullptr; } LLVM,RISCV,2780,return m_d != nullptr; } LLVM,RISCV,2781,{ return f != nullptr; } LLVM,RISCV,2782,{ return f != nullptr; } LLVM,RISCV,2783,{ return m_data.size() > 0; } LLVM,RISCV,2784,{ return m_data.size() > 0; } LLVM,RISCV,2785,bool hasX ( ) const { return x != 0; } LLVM,RISCV,2786,bool hasX ( ) const { return x != 0; } LLVM,RISCV,2787, LLVM,RISCV,2788,return RM == Reloc::PC32DBL && (CM == CodeModel::Small || CM == CodeModel::Kernel); LLVM,RISCV,2789,return true; LLVM,RISCV,2790,return m_bitwidth == 32; } LLVM,RISCV,2791,"This will return the value of the `m_rv32` member variable, which is a boolean indicating whether the instruction is in the RV32 instruction set." LLVM,RISCV,2792,bool isRV64 ( ) const { return ArchVersion == 64; } LLVM,RISCV,2793, LLVM,RISCV,2794,bool enableDefaultUnroll (bool enable) { LLVM,RISCV,2795,bool enableDefaultUnroll ( ) { LLVM,RISCV,2796,bool enableUnalignedScalarMem ( ) const { return true; } LLVM,RISCV,2797,assert ( hasVInstructions ( ) && hasVInstructions ( ) ); LLVM,RISCV,2798,const ISA_LIT FrameLowering * getFrameLowering ( ) { return &frameLowering; } LLVM,RISCV,2799,const ISA_LIT FrameLowering * getFrameLowering ( ) { return &frameLowering; } LLVM,RISCV,2800,return hasVInstructions() ? MaxInterleaveFactor : 1; LLVM,RISCV,2801,return hasVInstructions ( ) ? MaxInterleaveFactor : 1; LLVM,RISCV,2802,unsigned getMaxVLen ( ) const { return } LLVM,RISCV,2803,"unsigned getMinVLen (unsigned char *data, unsigned size) { unsigned min_len = size; for (unsigned i = 0; i < size; i++) { if (data[i] == 0) { min_len = i; break; } } return min_len; }" LLVM,RISCV,2804,: VLen; LLVM,RISCV,2805,return VLen == ? getMinVLen(VLen) : getMaxVLen(VLen); LLVM,RISCV,2806,return VLen == ? getMinVLen ( ) : getMaxVLen ( ); LLVM,RISCV,2807,const ISA_LIT RegisterInfo * getRegisterInfo() { } LLVM,RISCV,2808,{ return &m_registerInfo; } LLVM,RISCV,2809,{ return xlen; } unsigned getYLen ( ) { return ylen; } unsigned getZLen ( ) { return zlen; } unsigned getXLen ( ) { return xlen; } unsigned getYLen ( ) { return ylen; } unsigned getZLen ( ) { return zlen; } unsigned getXLen ( ) { return xlen; } unsigned getYLen ( ) { return ylen; LLVM,RISCV,2810,MVT getXLenVT ( ) const { return XLenVT; } LLVM,RISCV,2811,bool hasStdExtA ( ) { LLVM,RISCV,2812,bool hasStdExtD ( ) { LLVM,RISCV,2813,"bool hasStdExtD (const string& ext) { return ext.size() > 3 && ext.substr(ext.size() - 3) == "".d""; }" LLVM,RISCV,2814,bool hasStdExtF ( ) const { return std::is_standard_layout_v && std::is_trivially_copyable_v; } Explanation: LLVM,RISCV,2815,bool hasStdExtF ( ) const { return std::is_standard_layout_v && std::is_trivially_copyable_v; } Explanation: LLVM,RISCV,2816,bool hasStdExtM ( ) const { return m_hasStdExt; } LLVM,RISCV,2817,bool hasStdExtV ( ) { LLVM,RISCV,2818,bool hasStdExtZba ( ) const { LLVM,RISCV,2819,{ return (m_stdExtZbc != nullptr); } LLVM,RISCV,2820,bool hasStdExtZbe ( ) const { return HasStdExtZbe; } LLVM,RISCV,2821,# LLVM,RISCV,2822,bool hasStdExtZbkc ( ) { LLVM,RISCV,2823, LLVM,RISCV,2824,bool hasStdExtZbr ( ) const { return HasStdExtZbr; } LLVM,RISCV,2825,bool hasStdExtZbs (bool); LLVM,RISCV,2826, LLVM,RISCV,2827,#include LLVM,RISCV,2828,bool hasStdExtZfinx ( ) const { return m_hasStdExtZfinx; } LLVM,RISCV,2829,bool hasStdExtZhinx ( ) const { return m_stdExtZhinx; } LLVM,RISCV,2830, LLVM,RISCV,2831,class MyClass { LLVM,RISCV,2832,"bool hasStdExtZihintpause ( ) const { return std::is_base_of::value; } Explanation:" LLVM,RISCV,2833,bool hasStdExtZknd(const std::string& extName) const { LLVM,RISCV,2834,bool hasStdExtZkne() const { LLVM,RISCV,2835,{ return false; } LLVM,RISCV,2836,bool hasStdExtZkr() const { LLVM,RISCV,2837,bool hasStdExtZksed ( ) const { return m_hasStdExtZksed; } LLVM,RISCV,2838,bool hasStdExtZksh ( ) const { return m_hasStdExtZksh; } LLVM,RISCV,2839,bool hasStdExtZvfh ( ) const { return m_hasStdExtZvfh; } LLVM,RISCV,2840,"{ return std::is_base_of::value; }" LLVM,RISCV,2841,bool hasStdExtZvl ( ) { LLVM,RISCV,2842,bool hasVInstructions() const { LLVM,RISCV,2843,bool hasVInstructionsAnyF ( ) const { return hasVInstructionsF32 || hasVInstructionsF64; } LLVM,RISCV,2844,function hasVInstructionsF32() { LLVM,RISCV,2845,return HasStdExtZvfh && this.extension === 'zvfh'; LLVM,RISCV,2846,bool hasVInstructionsF16 ( ) { LLVM,RISCV,2847,const std::vector& instructions) { for (const Instruction& instruction : instructions) { if (instruction.getOpcode() == Opcode::V) { return true; } } return false; } LLVM,RISCV,2848,return HasStdExtZve64d(n) LLVM,RISCV,2849,bool hasVInstructionsI64 ( ) const { return m_hasVInstructionsI64; } LLVM,RISCV,2850,bool is64Bit() const { LLVM,RISCV,2851,return UserReservedRegister[i]; LLVM,RISCV,2852,return (m_isa & RV32E) != 0; LLVM,RISCV,2853,"return MaxBuildIntsCost == ? getSchedModel ( ) . LoadLatency + : std :: max < unsigned > ( MaxBuildIntsCost , );" LLVM,RISCV,2854,return MaxBuildIntsCost == ? getSchedModel ( ) . LoadLatency + : getSchedModel ( ) . LoadLatency; LLVM,RISCV,2855,"unsigned > ( RVVVectorLMULMax, RVVVectorLMULMax ), 1 ) ) ; }" LLVM,RISCV,2856,assert ( ( RVVVectorBitsMin == || ( RVVVectorBitsMin >= && RVVVectorBitsMin <= && isPowerOf2_32 ( RVVVectorBitsMin ) ) ) && ) ; assert ( ( RVVVectorBitsMax >= RVVVectorBitsMin || RVVVectorBitsMax == ) ) ; LLVM,RISCV,2857,bool hasStdExtB ( ) const { return HasStdExtB; } LLVM,RISCV,2858,{ return false; } LLVM,RISCV,2859,TuneCPU = CPU; LLVM,RISCV,2860,return true; LLVM,RISCV,2861,bool Subtarget :: enableSubRegLiveness () const { return true; } LLVM,RISCV,2862,if (RVVVectorBitsMax == ) { LLVM,RISCV,2863,"assert ( RVVVectorBitsMax >= RVVVectorBitsMin && ""RVVVectorBitsMax must be greater than or equal to RVVVectorBitsMin"" );" LLVM,RISCV,2864,unsigned Min = RVVVectorBitsMin; LLVM,RISCV,2865,return RVVVectorLMULMax; LLVM,RISCV,2866,assert ( hasStdExtV ( ) && ) ; assert ( RVVVectorLMULMax <= 128 && isPowerOf2_32 ( RVVVectorLMULMax ) ) ; LLVM,RISCV,2867,"Next, the function calls a function called `ParseSub" LLVM,RISCV,2868, LLVM,RISCV,2869,RegBankInfo.reset(RBI); LLVM,RISCV,2870, LLVM,RISCV,2871,"return PowerOf2Floor(std::max(std::min(RVVVectorELENMax, ELEN)));" LLVM,RISCV,2872,bool hasC910 ( ) const { return HasC910; } LLVM,RISCV,2873,bool hasStdExtZvqmac ( ) const { return m_hasStdExtZvqmac; } LLVM,RISCV,2874,InstSelector . reset ( createInstructionSelector ( * static_cast < const TargetMachine * > ( & TM ) ) ) ; LLVM,RISCV,2875,bool enableCheriRVCInstrs ( ) const { return EnableCheriRVCInstrs; } LLVM,RISCV,2876,bool hasCheri ( ) { LLVM,RISCV,2877,bool isCapMode ( ) const { return m_capMode; } LLVM,RISCV,2878,InstSelector . reset LLVM,RISCV,2879, LLVM,RISCV,2880,assert ( RVVVectorELENMax <= 1024 && RVVVectorELENMax >= 128 && isPowerOf2_32 ( RVVVectorELENMax ) ); LLVM,RISCV,2881, LLVM,RISCV,2882,assert ( hasVInstructions ( ) && ) ; assert ( ( RVVVectorBitsMin == || ( RVVVectorBitsMin >= && RVVVectorBitsMax <= && isPowerOf2_32 ( RVVVectorBitsMin ) ) ) && ) ; assert ( ( RVVVectorBitsMax >= RVVVectorBitsMin || RVVVectorBitsMax == LLVM,RISCV,2883,"assert ( ( RVVVectorBitsMax >= RVVVectorBitsMin || RVVVectorBitsMax == ) && ) ; unsigned Min = RVVVectorBitsMin ; if ( RVVVectorBitsMax != ) Min = std :: min ( RVVVectorBitsMax, RVVVectorBitsMin ) ;" LLVM,RISCV,2884,bool hasStdExtP (const string& ext) { return ext.size() > 0 && ext[0] == '.'; } LLVM,RISCV,2885,return ZvlLen != ExtZvl; LLVM,RISCV,2886,if (ZvlLen.length != []) { LLVM,RISCV,2887,return (HasStdExtV || HasStdExtZve32f); LLVM,RISCV,2888,return ( HasStdExtV || HasStdExtZve32f ); LLVM,RISCV,2889,bool hasVInstructionsF64 ( ) const { return HasStdExtV || ( HasStdExtZve64d && HasStdExtZve64f ); } Explanation: LLVM,RISCV,2890,bool hasVInstructionsI64 ( ) const { LLVM,RISCV,2891,bool hasNonStdExtPulp() const { LLVM,RISCV,2892, LLVM,RISCV,2893, LLVM,RISCV,2894,return (m_reg == 5 && m_cycles == 1); } LLVM,RISCV,2895,{ } LLVM,RISCV,2896,bool hasExtXCoreVAlu LLVM,RISCV,2897,bool hasExtXCoreVHwlp (const char* ext) { LLVM,RISCV,2898,class MyClass { LLVM,RISCV,2899,bool hasExtXCoreVMem ( ) { LLVM,RISCV,2900,return HasStdExtV && hasStdExtZfh; LLVM,RISCV,2901,bool hasVInstructionsF32 ( ) const { return HasStdExtV && hasStdExtF ( ) && hasStdExtF32 ( ); } LLVM,RISCV,2902,return HasStdExtV && hasStdExtF; LLVM,RISCV,2903,bool hasVInstructionsF64 ( ) const { return HasStdExtV && hasStdExtD; } LLVM,RISCV,2904,bool hasVInstructionsI64 ( ) const { LLVM,RISCV,2905,"TARGET_MACHINE ) , * RBI ) ) ;" LLVM,RISCV,2906,RVVVectorBitsMax ) ; LLVM,RISCV,2907,return PowerOf2Floor(Min); LLVM,RISCV,2908,const CallLowering * Subtarget :: getCallLowering ( ) const { return CallLoweringInfo . getCallLowering ( ); } LLVM,RISCV,2909,return CallLoweringInfo.get(call.getInstruction()); LLVM,RISCV,2910,InstructionSelector * Subtarget :: getInstructionSelector() { return new InstructionSelector(this); } LLVM,RISCV,2911,return Legalizer.get(); LLVM,RISCV,2912,"getMaxVLForVectors ( ) ) , getMinVLForVectors ( ) ) ) ; }" LLVM,RISCV,2913,return hasStdExtV() ? MaxInterleaveFactor : 0; LLVM,RISCV,2914, LLVM,RISCV,2915,"(x, y), 1));" LLVM,RISCV,2916,"return RegBankInfo.get(""RB_0"")" LLVM,RISCV,2917,return RegBankInfo.get(registryName); LLVM,RISCV,2918,bool hasStdExtZvamo() { LLVM,RISCV,2919,return HasStdExtZvlsseg; LLVM,RISCV,2920, LLVM,RISCV,2921,"if (CPU == ""x86"") {" LLVM,RISCV,2922,bool Subtarget :: useRVVForFixedLengthVectors () const { return false; } LLVM,RISCV,2923,return hasStdExtV() && getMinRVVVectorSizeInBits(); LLVM,RISCV,2924,"RegisterTarget < Triple :: riscv32 > X ( getThe32Target ( ) , , ) ;" LLVM,RISCV,2925,return The32Target; LLVM,RISCV,2926,static Target The32Target; LLVM,RISCV,2927,The64Target; LLVM,RISCV,2928,RegisterTarget < Triple :: riscv64 > Y ( getThe64Target ( LLVM,RISCV,2929,"RegisterTarget < Triple :: riscv32 > X ( getThe32Target ( ) , , , ) ;" LLVM,RISCV,2930, LLVM,RISCV,2931,return The32Target; LLVM,RISCV,2932, LLVM,RISCV,2933,return llvm::getThe64Target(); LLVM,RISCV,2934, LLVM,RISCV,2935,"void LLVMInitializeTargetInfo ( ) { RegisterTarget < Triple :: riscv , false > A ( TheTarget , ); }" LLVM,RISCV,2936,addPass ( create LLVM,RISCV,2937,Pass *P) { PreEmitPasses.push_back(P); } LLVM,RISCV,2938,Pass *P) { PreEmitPasses.push_back(P); } LLVM,RISCV,2939, LLVM,RISCV,2940,return new PassConfig ( [/INST: return new PassConfig ( [/INST: return new PassConfig ( [/INST: return new PassConfig ( [/INST: return new PassConfig ( [/INST: return new PassConfig ( [/INST: return new PassConfig ( [/INST: return new PassConfig ( [/INST: return new PassConfig ( [/INST: return new PassConfig ( [/INST LLVM,RISCV,2941, LLVM,RISCV,2942,return &SubtargetImpl::getSubtargetImpl(); LLVM,RISCV,2943, LLVM,RISCV,2944,RegisterTargetMachine(64TargetMachine); LLVM,RISCV,2945,"TLOF ( make_unique < TargetObjectFile > ( ) ) , Subtarget ( TT , CPU , FS , * this ) { initAsmInfo ( ) }" LLVM,RISCV,2946, LLVM,RISCV,2947,{ return &Subtarget; } LLVM,RISCV,2948,const auto * MFI = MF.getInfoMachineFunctionInfo>(); LLVM,RISCV,2949,return new yaml::MachineFunctionInfo(); LLVM,RISCV,2950,return new yaml::ISA_LITMachineFunctionInfo( LLVM,RISCV,2951, LLVM,RISCV,2952, LLVM,RISCV,2953,bool IsRV64() { LLVM,RISCV,2954,PFS.MF.getInfoMachineFunctionInfo>().initializeBaseYamlFields(YamlMFI); LLVM,RISCV,2955,if ( TT . isArch64Bit ( ) ) { LLVM,RISCV,2956, LLVM,RISCV,2957, LLVM,RISCV,2958, LLVM,RISCV,2959,RegisterTargetMachine < TargetMachine > Y ( getThe64Target() ); LLVM,RISCV,2960,"It also calls the `initAsmInfo` method, which is" LLVM,RISCV,2961,"TargetMachine :: TargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , Optional < CodeModel :: Model > CM , CodeGenOpt :: Level OL , bool JIT ) : LLVMTargetMachine (" LLVM,RISCV,2962,"TargetMachine :: TargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , Optional < CodeModel :: Model > CM , CodeGenOpt :: Level OL , bool JIT ) : LLVMTargetMachine (" LLVM,RISCV,2963,if (TT.isArch64Bit()) { LLVM,RISCV,2964,static std :: string computeDataLayout ( const Triple & TT ) { if ( TT . isArch64Bit ( ) ) { return ; } else { assert ( TT . isArch32Bit ( ) ) ; return ; } } LLVM,RISCV,2965,"return new TargetPassConfig(this, TargetPassConfig.TargetPass.BASIC);" LLVM,RISCV,2966,"return new TargetPassConfig ( { target: 'http://localhost:3000', secure: false, changeOrigin: true, ws: true, logLevel: 'info', headers: { 'Access-Control-Allow-Origin': '*', 'Access-Control-Allow-Methods': 'GET, POST, PUT, DELETE, PATCH, OPTIONS', 'Access-Control-Allow-Headers': 'X-Requested-With, content-type, Authorization' }" LLVM,RISCV,2967,bool PassConfig :: addGlobalInstructionSelect ( ) { addPass ( new InstructionSelect ( ) ); return true; } LLVM,RISCV,2968,void PassConfig :: addPreRegAlloc ( ) { if ( TM -> getOptLevel ( ) != CodeGenOpt :: None ) { addPass ( createMergeBaseOffsetOptPass ( ) ); } } LLVM,RISCV,2969,createMergeBaseOffsetOptPass ( ) ) ; addPass ( createCleanupVSETVLIPass ( ) ) ; } LLVM,RISCV,2970,"PassRegistry::registerPass(getThe32Target());" LLVM,RISCV,2971,initializeMergeBaseOffsetOptPass( * PR ) ; LLVM,RISCV,2972,addPass ( new IRTranslator ()); LLVM,RISCV,2973,return true; LLVM,RISCV,2974,return ; } else { assert ( TT . isArch32Bit ( ) ); } } LLVM,RISCV,2975,void LLVMInitializeTarget ( ) { RegisterTargetMachine < TargetMachine > X ( getThe32Target ( ) ) ; RegisterTargetMachine < TargetMachine > Y ( getThe64Target ( ) ) ; auto PR = PassRegistry :: getPassRegistry ( ) ; } LLVM,RISCV,2976,"TLOF ( std :: make_unique < ELFTargetObjectFile > ( ) ) , Subtarget ( TT , CPU , FS , Options . MCOptions . getABIName ( ) , * this ) { initAsmInfo ( ) }" LLVM,RISCV,2977,"LLVMTargetMachine ( T , computeDataLayout ( TT ) , TT , CPU , FS , Options , getEffectiveRelocModel ( TT , RM , CM , OL , JIT ) )" LLVM,RISCV,2978,void ISA_LITPassConfig :: addIRPasses ( ) { addPass ( createAtomicExpandPass ( ) ) ; addPass ( createISALiteralLoweringPass ( ) ) ; TargetPassConfig :: addIRPasses ( ) ; } LLVM,RISCV,2979,addPass(new IRTranslator(getOptLevel(3))); LLVM,RISCV,2980,bool PassConfig :: addLegalizeMachineIR ( ) { addPass ( new Legalizer ( ) ); return true; } LLVM,RISCV,2981,if (TM->getTargetTriple()->getArch() == Triple::x86) { LLVM,RISCV,2982,TM -> getOptLevel ( ) != CodeGenOpt :: None && TM -> getOptLevel ( ) != CodeGenOpt :: Debug) { TM -> addPostRegAlloc ( ); LLVM,RISCV,2983,addPass(createInsertVSETVLIPass()); LLVM,RISCV,2984,void PassConfig :: addPreRegAlloc ( ) { if ( TM -> getOptLevel ( ) != CodeGenOpt :: None ) addPass ( createMergeBaseOffsetOptPass ( ) ) ; addPass ( createInsertVSETVLIPass ( ) ) ; } LLVM,RISCV,2985,return false; LLVM,RISCV,2986, LLVM,RISCV,2987,I = SubtargetMap[Key]; LLVM,RISCV,2988,Attribute CPUAttr = F . getFnAttribute ( ) ; Attribute TuneAttr = F . getFnAttribute ( ) ; Attribute FSAttr = F . getFnAttribute ( ) ; std :: string CPU = CPUAttr . isValid ( ) ? CPUAttr . getValueAsString ( ) . str ( ) : TargetCPU ; std :: string TuneCPU = TuneAttr . isValid ( ) ? TuneAttr . getValueAsString ( ) . LLVM,RISCV,2989,const TargetTransformInfo &TargetMachine :: getTargetTransformInfo ( const Function & F ) const { return F.getTargetTransformInfo (); } LLVM,RISCV,2990, LLVM,RISCV,2991,"bool TargetMachine :: isNoopAddrSpaceCast ( unsigned SrcAS , unsigned DstAS ) const { return SrcAS == DstAS; }" LLVM,RISCV,2992,return SrcAS == DstAS; LLVM,RISCV,2993,initialize LLVM,RISCV,2994, LLVM,RISCV,2995,"TargetMachine::TargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Optional RM, Optional CM, CodeGenOpt::Level OL, bool JIT) : LLVMTargetMachine(T, computeDataLayout(TT), TT, CPU, FS, Options);" LLVM,RISCV,2996,createPreEmitPass ( ) ); LLVM,RISCV,2997,RegisterTargetMachine < TargetMachine > Y ( getThe64Target ( ) ) ; LLVM,RISCV,2998, LLVM,RISCV,2999,Attribute FSAttr = F.getFnAttribute(); LLVM,RISCV,3000,initializeRemoveRedundancyVSETVLPass( * PR ) ; LLVM,RISCV,3001, LLVM,RISCV,3002,"bool TargetMachine::isNoopAddrSpaceCast(unsigned SrcAS, unsigned DstAS) const { const bool SrcIsCheri = isCheriPointer(SrcAS, [/INST] bool TargetMachine::isNoopAddrSpaceCast(unsigned SrcAS, unsigned DstAS) const { const bool SrcIsCheri = isCheriPointer(SrcAS, [/INST] bool TargetMachine::isNoopAddrSpaceCast(unsigned SrcAS, unsigned DstAS) const { const bool SrcIs" LLVM,RISCV,3003,DestIsCheri ) if ( ( SrcIsCheri || DestIsCheri ) && ( SrcIsCheri != DestIsCheri ) ) LLVM,RISCV,3004, LLVM,RISCV,3005, LLVM,RISCV,3006,"TT , CPU , FS , Options , RM , CM , OL ) { }" LLVM,RISCV,3007,addPass(createExpandPseudoPass()); LLVM,RISCV,3008,return false; LLVM,RISCV,3009, LLVM,RISCV,3010,addPass ( createMergeBaseOffsetOptPass ( ) ) ; LLVM,RISCV,3011, LLVM,RISCV,3012,if ( TargetABI != && ModuleTargetABI -> getString ( ) != TargetABI ) LLVM,RISCV,3013,initializeGlobalISel(*PR); LLVM,RISCV,3014, LLVM,RISCV,3015,RegisterTargetMachine < TargetMachine > Y ( getThe64Target ( ) ) ; LLVM,RISCV,3016,TargetPassConfig targetPassConfig; LLVM,RISCV,3017,return * RM.getValue(); LLVM,RISCV,3018,TLOF ( make_unique < TargetObjectFile > ( ) ) LLVM,RISCV,3019,bool PassConfig::addInstSelector() { LLVM,RISCV,3020,addPass(createISelDag(getTargetMachine())); LLVM,RISCV,3021,void PassConfig :: addIRPasses ( ) { addPass ( createAtomicExpandPass ( ) ) ; TargetPassConfig :: addIRPasses ( ) ; } LLVM,RISCV,3022,void ISA_LITPassConfig::addIRPasses() { addPass(createAtomicExpandPass()); } LLVM,RISCV,3023,void PassConfig::setPass(const Pass* pass) { } LLVM,RISCV,3024,addPass(createExpandPseudoPass(new ISA_L LLVM,RISCV,3025,addPass(createMergeBaseOffsetOptPass( LLVM,RISCV,3026,void PassConfig :: addPreRegAlloc ( ) { LLVM,RISCV,3027,if ( ! RM . hasValue ( ) ) { LLVM,RISCV,3028,for ( const auto & MFE : ModuleFlags ) { StringRef Key = MFE . Key -> getString ( ) ; if ( Key == ) { SSThreshold = mdconst :: extract < ConstantInt > ( MFE . Val ) ; } } } LLVM,RISCV,3029,"return getSectionForConstant(DL, Kind, C);" LLVM,RISCV,3030,"MCSection *ELFTargetObjectFile::getSectionForConstant(const DataLayout &DL, SectionKind Kind, const Constant *C) { if (const GlobalValue *GV = dyn_cast(C)) { if (GV->isFunction()) return getTextSection(); if (GV->isVariable()) return getDataSection();" LLVM,RISCV,3031, LLVM,RISCV,3032,return isInSmallSection ( DL . getTypeAllocSize ( CN ) ); LLVM,RISCV,3033,"return DL.isConstantInSmallSection(this, Constant);" LLVM,RISCV,3034,return isInSmallSection(GVA->getParent()->getDataLayout()); LLVM,RISCV,3035,"bool ELFTargetObjectFile::isInSmallSection(uint64_t Size, uint64_t Address) { return (Address >= SmallDataSectionStart && Address < SmallDataSectionEnd); }" LLVM,RISCV,3036,"return TargetLoweringObjectFileELF::SelectSectionForGlobal(GO, Kind);" LLVM,RISCV,3037, LLVM,RISCV,3038, LLVM,RISCV,3039,const TargetMachine & RTM = static_cast < const TargetMachine & >(RTM); LLVM,RISCV,3040,& > (RTM); Explanation: LLVM,RISCV,3041,if ( ! getContext ( ) . getAsmInfo ( ) -> isCheriPurecapABI ( ) ) LLVM,RISCV,3042,Here's a breakdown of the code: LLVM,RISCV,3043,"MCSection * ELFTargetObjectFile :: getSectionForConstant ( const DataLayout & DL , SectionKind Kind , const Constant * C , unsigned & Align ) const { if ( isConstantInSmallSection ( DL , C ) ) { return getSmallSection ( Kind , Align ); } else { return getCommonSection ( Kind , Align ); } }" LLVM,RISCV,3044,"SmallDataSection = getContext().getELFSection("""", ELF::SHT_PROGBITS, ELF::" LLVM,RISCV,3045,"void ISA_LITELFTargetObjectFile::Initialize(MCContext &Ctx, const TargetMachine &TM) { TargetLoweringObjectFileELF::Initialize(Ctx, TM); }" LLVM,RISCV,3046,"void TargetAsmStreamer::emitDirectiveOptionNoRelax() { m_streamer.emitDirectiveOption(""-no-relax""); }" LLVM,RISCV,3047,OS << << endl; LLVM,RISCV,3048,"OS << ""Hello, world!"";" LLVM,RISCV,3049,"OS << ""Hello, world!"";" LLVM,RISCV,3050,OS << << endl; LLVM,RISCV,3051,void TargetAsmStreamer::emitDirectiveOptionRVC() { } LLVM,RISCV,3052, LLVM,RISCV,3053,"void TargetAsmStreamer::emitTextAttribute(unsigned ID, const char *Name) {" LLVM,RISCV,3054,assert(ABI != && ); LLVM,RISCV,3055,void TargetStreamer::setTargetABI(StringRef TargetABI) { } LLVM,RISCV,3056,void TargetAsmStreamer::emitDirectiveOptionCapMode() { } LLVM,RISCV,3057,if (STI.hasFeature()) Arch += ; LLVM,RISCV,3058,if ( STI . hasFeature ( ) ) Arch = , ); std::string Arch = ; if (STI.hasFeature( )) Arch = ; if (STI.hasFeature( " LLVM,RISCV,3060, LLVM,RISCV,3061,if (STI.hasFeature()) Arch += ; LLVM,RISCV,3062,if (STI.hasFeature()) Arch += ; LLVM,RISCV,3063,else Arch += ; LLVM,RISCV,3064,if (STI.hasFeature()) Arch += ; LLVM,RISCV,3065,return ( LT.first - ) LLVM,RISCV,3066,return ; LLVM,RISCV,3067,return ST -> getMaxInterleaveFactor(ST); LLVM,RISCV,3068,return BaseT::getMaxVScale(); LLVM,RISCV,3069,if (ST -> hasVInstructions ( ) && MaxVectorSizeInBits != ) { LLVM,RISCV,3070,return (LT.first - ) + BaseCost; LLVM,RISCV,3071,"BaseT :: getPeelingPreferences ( L , SE , PP )" LLVM,RISCV,3072,"void TTIImpl::getPeelingPreferences(Loop *L, ScalarEvolution &SE) {" LLVM,RISCV,3073,return TypeSize :: getFixed ( ST -> hasStdExtV ( ) ? ST -> getXLen ( ) : ST -> getXLen ( ) / 2 ) ; LLVM,RISCV,3074, LLVM,RISCV,3075, LLVM,RISCV,3076,"InstructionCost TTIImpl :: getSpliceCost ( VectorType * Tp , int Index ) { std :: pair < InstructionCost , MVT > LT = TLI -> getTypeLegalizationCost ( DL , Tp -> getElementType ( Index ) );" LLVM,RISCV,3077, LLVM,RISCV,3078,"LLVM_DEBUG(dbgs() << ""Cost: "" << Cost << "" Partial: "" << UP.Partial << "" Runtime: "" << UP.Runtime);" LLVM,RISCV,3079,"return VPLegalization ( VPLegalization :: Legal , VPLegalization :: [])" LLVM,RISCV,3080,"return VPLegalization ( VPLegalization :: Legal , [" LLVM,RISCV,3081,"bool isLegalMaskedGather(Type *DataType, Align Alignment) {" LLVM,RISCV,3082,if ( ! ST->hasStdExtV() ) return false; LLVM,RISCV,3083,"bool isLegalMaskedScatter ( Type * DataType, Type * MaskType ) { if (DataType != INT && DataType != FLOAT) { return false; } if (MaskType != INT && MaskType != FLOAT) { return false; } if (DataType == INT && MaskType == FLOAT) {" LLVM,RISCV,3084,"bool isLegalMaskedStore ( Type * DataType , Align Alignment ) { return isLegalMaskedLoadStore ( DataType , Alignment ); }" LLVM,RISCV,3085,Here is an example of how LLVM,RISCV,3086, LLVM,RISCV,3087,bool supportsScalableVectors() const { LLVM,RISCV,3088,bool LLVM,RISCV,3089,if (isa(DataType) && ST->getMinRVVVectorSizeInBits() == ) LLVM,RISCV,3090,"bool isLegalMaskedLoadStore ( Type * DataType , Align Alignment ) {" LLVM,RISCV,3091,return true; LLVM,RISCV,3092,"const DataLayout & DL = getDataLayout ( ) ; return ( Imm , DL . getTypeSizeInBits ( Ty ) ) ;" LLVM,RISCV,3093,return VF == ? : ST; LLVM,RISCV,3094,unsigned getMaxInterleaveFactor ( unsigned VF ) { LLVM,RISCV,3095,"{ unsigned getMinVectorRegisterBitWidth ( ) { unsigned minVectorRegisterBitWidth = 0; for (unsigned i = 0; i < getNumberOfVectorRegisters(); i++) { minVectorRegisterBitWidth = std::min(minVectorRegisterBitWidth, getVectorRegisterBitWidth(i)); } return minVectorRegisterBitWidth; }" LLVM,RISCV,3096, LLVM,RISCV,3097,return TLI -> isLegalElementTypeForRVV ( DataType -> getScalarType ( ) ); LLVM,RISCV,3098, LLVM,RISCV,3099,getScalarType() ); LLVM,RISCV,3100,return false; LLVM,RISCV,3101,return false; LLVM,RISCV,3102,bool supportsScalableVectors ( ) const { LLVM,RISCV,3103,"int TTIImpl::getIntImmCost(IID, unsigned Idx, const APInt &Imm, Type *Ty) {" LLVM,RISCV,3104,"int TTIImpl :: getIntImmCost ( IID , unsigned Idx , int Imm )" LLVM,RISCV,3105,return ST -> hasStdExtV() ? ST -> LLVM,RISCV,3106,if (isa(DataType) && DataType->getScalarSizeInBits() > ST->getMaxE LLVM,RISCV,3107,return hasInnerHardwareLoop; LLVM,RISCV,3108,return true; LLVM,RISCV,3109,return ST -> hasNonStdExtPulp && ST -> hasNonStdExtPulp -> isPulp; LLVM,RISCV,3110, LLVM,RISCV,3111,InstructionCost Cost = ; LLVM,RISCV,3112,return TTI::TCC_Free; LLVM,RISCV,3113,if ( Instruction :: isCommutative ( Opcode ) || ImmArgIdx == 0 ) { LLVM,RISCV,3114,"int TTIImpl::getIntImmCostInst(unsigned Opcode, unsigned Idx, const APInt& Imm, Type* Ty, TTI::TargetCostKind CostKind, Instruction* Inst) { assert(Ty->isIntegerTy() && ""Ty must be an integer type""); if (Imm == 0) return TTI::TCC_Free; bool Takes12BitImm = false; unsigned ImmArgIdx = ~0; switch (Opcode) { case Instruction::GetElement" LLVM,RISCV,3115,"ISA_LIT>TTIImpl::getIntImmCostIntrin( IID, unsigned Idx, const APInt &Imm, Type *Ty, int Cost) { }" LLVM,RISCV,3116,) { LLVM,RISCV,3117,return true; LLVM,RISCV,3118,if (F -> getName() . startswith()) { LLVM,RISCV,3119,return TTI :: TCC_Free ; LLVM,RISCV,3120,"TypeSize Size = Ty -> getPrimitiveSizeInBits ( ) ; if ( Ty -> isVectorTy ( ) ) { if ( Size . isScalable ( ) && ST -> hasVInstructions ( ) ) return divideCeil ( Size . getScalableSizeInBits ( ) , ST -> getVInstructionWidth ( ) ) ; }" LLVM,RISCV,3121,"LLVM_DEBUG(dbgs() << ""Cost: "" << Cost << "" Partial: "" << UP.Partial << "" Runtime: "" << UP.Runtime << ""\n"");" LLVM,RISCV,3122,"InstructionCost TTIImpl :: getArithmeticReductionCost ( unsigned Opcode , VectorType * VTy , Optional < FastMathFlags > FMF , TTI :: TargetCostKind CostKind ) { if ( ! isa < FixedVectorType > ( VTy ) ) return BaseT :: getArithmeticReductionCost ( Opcode , VTy , FMF , CostKind ) ; if ( VTy -> getElementType ( ) -> isIntegerTy ( ) ) return BaseT :: getArithmeticReductionCost (" LLVM,RISCV,3123,"return BaseT::getArithmeticReductionCost(Opcode, VTy, FMF, CostKind);" LLVM,RISCV,3124, LLVM,RISCV,3125,unsigned VL = cast < FixedVectorType > ( Ty ) -> getNumElements ( ); LLVM,RISCV,3126, LLVM,RISCV,3127,return true; LLVM,RISCV,3128,return true; LLVM,RISCV,3129,return isLegalElementTypeForRVV(DataType->getScalarType()); LLVM,RISCV,3130, LLVM,RISCV,3131,"case RecurKind::Mul: After that, it checks the recurrence kind and" LLVM,RISCV,3132,if ( Takes12BitImm ) { if ( Instruction :: isCommutative ( Opcode ) || Idx == ImmArgIdx ) { if ( getTLI ( ) -> isLegalAddImmediate ( Imm . getSExtValue ( LLVM,RISCV,3133,return TLI -> isLegalElementTypeForRVV ( DataType -> getScalarType ( ) ); LLVM,RISCV,3134,getScalarType ( ) ) ; LLVM,RISCV,3135,getScalarType() ); LLVM,RISCV,3136,return false; LLVM,RISCV,3137,The LLVM,RISCV,3138,"return BaseT :: getGatherScatterOpCost ( Opcode , DataTy , Ptr , VariableMask , Alignment , CostKind , I ) ;" LLVM,RISCV,3139,"TTIImpl::getIntImmCost(const APInt &Imm, Type *Ty, TTI::TargetCostKind CostKind) { assert(Ty->isIntegerTy() && ""Ty must be an integer type""); if (Imm == 0) return TTI::TCC_Free; const DataLayout &DL = getDataLayout(); return TTI::TCC_Basic; }" LLVM,RISCV,3140,"return getIntImmCost(Imm, ...);" LLVM,RISCV,3141,TTI :: PSK_Software; LLVM,RISCV,3142,TargetTransformInfo :: PopcntSupportKind TTIImpl :: getPopcntSupport ( unsigned TyWidth ) { assert ( isPowerOf2_32 ( TyWidth ) && TyWidth <= 64 ); LLVM,RISCV,3143,const ISA_LIT Subtarget * getST ( ) const { return &ST; } LLVM,RISCV,3144,const TargetLowering * getTLI () LLVM,RISCV,3145,default : return false ; LLVM,ARC,0, LLVM,ARC,1,return static_castTargetStreamer&>(*OutStreamer->getTargetStreamer()); LLVM,ARC,2,MachineFunction &MF) { if (!MF.getFunction().hasValidISA()) { return false; } const ISAInfo &ISA = MF.getFunction().getISA(); AsmPrinter Printer(ISA); Printer.print(MF); return true; } LLVM,ARC,3,TmpInst ) ; } LLVM,ARC,4,"StringRef getPassName() const override { return ""MyPass""; } Explanation:" LLVM,ARC,5,RegisterAsmPrinter < AsmPrinter > X; LLVM,ARC,6,MF.ensureAlignment(Align(4)); LLVM,ARC,7,MI->eraseFromParent(); LLVM,ARC,8, LLVM,ARC,9, LLVM,ARC,10,"insert ( std :: make_pair ( & MBB , PC ) ) ; for ( auto & MI : MBB ) { unsigned Size = TII -> getInstSizeInBytes ( MI ) ; if ( Size > || Size == ) { DEBUG ( dbgs ( ) << << MI << ) ; } else { MaxSize += Size ; } if ( MI . isBranch ( ) ) { Branches . push_back ( & MI ) ; } } }" LLVM,ARC,11,unsigned MaxSize = ; LLVM,ARC,12,getPassRegistry () ); LLVM,ARC,13, LLVM,ARC,14, LLVM,ARC,15,int getValue(string input) { LLVM,ARC,16,Instruction::Opcode::RET) { } LLVM,ARC,17,"{ return ""My Pass""; }" LLVM,ARC,18,"If that's the case, the last statement should be: return ! ( MI -> getOpcode ( ) != """" );" LLVM,ARC,19, LLVM,ARC,20, LLVM,ARC,21,MI->eraseFromParent(); LLVM,ARC,22,"BuildMI(MI->getParent(), MI, MI->getDebugLoc(), TII->get())" LLVM,ARC,23,PC += Size LLVM,ARC,24,"DecodeSymbolicOperandOff(Inst, Address, SignExtend32(InsnS));" LLVM,ARC,25, LLVM,ARC,26,} unsigned Reg = GPR32DecoderTable[RegNo]; LLVM,ARC,27,return MCDisassembler::Success; } LLVM,ARC,28, LLVM,ARC,29,"unsigned S9 = Insn & ; unsigned R = ( Insn & ( & ~ ) ) >> ; DecodeGPR32RegisterClass ( Inst , R , Address , Dec ) ; Inst . addOperand ( MCOperand :: createImm ( SignExtend32 < ) ) ;" LLVM,ARC,30,DecodeStatus::Success; LLVM,ARC,31,"Decoder ) ; } ; if ( DecodeRegisterOrImm ( h , g ) == MCDisassembler :: Fail ) { return MCDisassembler :: Fail ; } return MCDisassembler :: Success ; }" LLVM,ARC,32,"static_assert ( B > , ) ; Inst . addOperand ( MCOperand :: createImm ( SignExtend32 < B > ( maskTrailingOnes < decltype ( InsnS ) > ( B ) ) ) ) ;" LLVM,ARC,33,LImm = ( Insn >> ) & 0xFFFFFFFF; LLVM,ARC,34,"static void DecodeSymbolicOperandOff ( MCInst & Inst , uint64_t Address , uint64_t Offset , const void * Decoder ) { uint64_t nextAddress = Address + Offset;" LLVM,ARC,35,"static void DecodeSymbolicOperandOff ( MCInst & Inst , uint64_t Address , uint64_t Offset , const void * Decoder ) { uint64_t nextAddress = Address + Offset;" LLVM,ARC,36,"return decodeInstruction(DecoderTable16, Instr, Insn16, Address, this);" LLVM,ARC,37, LLVM,ARC,38,TargetRegistry :: RegisterMCDisassembler ( getTheTarget ( ) ); LLVM,ARC,39,"Field U6Field = fieldFromInstruction ( Insn , , ) ; Inst . addOperand ( MCOperand :: createImm ( U6Field ) ) ; Field CCField = fieldFromInstruction ( Insn , , ) ; Inst . addOperand ( MCOperand :: createReg ( CCField ) ) ;" LLVM,ARC,40,"createReg ( Value ) ) ; } else { Inst . addOperand ( MCOperand :: createImm ( Value ) ) ; } } ; Field H = fieldFromInstruction ( Insn , , ) | ( fieldFromInstruction ( Insn , , ) << ) ; Field G = fieldFromInstruction ( Insn , , ) | ( fieldFromInstruction (" LLVM,ARC,41,MCDisassembler::Success; LLVM,ARC,42,"Field U6 = fieldFromInstruction(Insn, , );" LLVM,ARC,43,"return ( nullptr != Disassembler && Disassembler -> tryAddingSymbolicOperand ( Inst , Value , Address , true , , false ) );" LLVM,ARC,44,"static void DecodeSymbolicOperandOff ( MCInst & Inst , uint64_t Address , uint64_t Size ) { uint64_t Offset = 0; uint64_t Value = 0; uint64_t Shift = 0; uint64_t Mask = 0; uint64_t BaseReg = 0; uint64_t IndexReg = 0; uint64_t Scale" LLVM,ARC,45,uint64_t NextAddress = Address + Offset; LLVM,ARC,46, LLVM,ARC,47,"int64_t Size , MCStreamer & Streamer ) { return false; }" LLVM,ARC,48, LLVM,ARC,49,"static MCDisassembler :: DecodeStatus DecodeBranchTargetS21 ( MCInst & Inst , unsigned S , uint64_t Address , const void * Decoder ) { Inst . addOperand ( MCOperand :: createImm ( SignExtend32 < > ( S ) ) ) ) ) ; return MCDisassembler :: Success ; }" LLVM,ARC,50,Inst . addOperand ( MCOperand :: createImm ( SignExtend32 < > ( LLVM,ARC,51,"static MCDisassembler :: DecodeStatus DecodeBranchTargetS25 ( MCInst & Inst , unsigned S , uint64_t Address , const void * Decoder ) { Inst . addOperand ( MCOperand :: createImm ( SignExtend32 < > ( S ) ) ) ) ) ; return MCDisassembler :: Success ; }" LLVM,ARC,52,Inst . addOperand ( MCOperand :: createImm ( SignExtend32 < > ( S [ LLVM,ARC,53,unsigned Reg = GPR32DecoderTable[RegNo]; LLVM,ARC,54,return MCDisassembler::Success; LLVM,ARC,55, LLVM,ARC,56,Inst.addOperand(MCOperand::createImm(SignExtend32(NUM_LIT & InsnS12))); LLVM,ARC,57, LLVM,ARC,58, LLVM,ARC,59,return Fail; LLVM,ARC,60,createReg ( DstA ) ) ) ; LLVM,ARC,61,"static DecodeStatus DecodeMoveHRegInstruction ( MCInst & Inst , uint64_t Insn , uint64_t Address , const void * Decoder ) { DEBUG ( dbgs ( ) << ""DecodeMoveHRegInstruction: "" << Inst.getName ( ) << "" "" << Insn << "" "" << Address << "" "" << Decoder << "" "" << Inst.getOpcode ( ) << "" "" << Inst.getOperand ( 0 ).getReg ( ) << "" "" << Inst.getOperand ( 1 ).getReg ( ) << """ LLVM,ARC,62,createImm ( LImm ) ) ; LLVM,ARC,63,"& Ctx ) { return new Disassembler ( T , STI , Ctx ); }" LLVM,ARC,64,"static unsigned decodeAField ( unsigned Insn ) { return fieldFromInstruction ( Insn , , ); }" LLVM,ARC,65,"static unsigned decodeBField ( unsigned Insn ) { return ( fieldFromInstruction ( Insn , , ) << ) | fieldFromInstruction ( Insn , , ); }" LLVM,ARC,66,"return ( fieldFromInstruction ( Insn , , ) << ) | ( fieldFromInstruction ( Insn , , ) >> );" LLVM,ARC,67,"DecodeSymbolicOperandOff ( Inst , Address , SignExtend32 < B > ( B.getOperand ( 1 ) ) ) );" LLVM,ARC,68,"return DecodeSymbolicOperandOff(Inst, Address, SignExtend32(InsnS), Decoder);" LLVM,ARC,69,"return fieldFromInstruction ( Insn , )" LLVM,ARC,70,static unsigned decodeCField ( unsigned cField ) { unsigned result = 0; result = (cField & 0x0000000F) >> 0; result |= (cField & 0x000000F0) >> 4; result |= (cField & 0x00000F00) >> 8; result |= (cField & 0x0000F000) >> 12; result |= (cField LLVM,ARC,71,"static_assert(B > 0, ""B must be positive"");" LLVM,ARC,72,Inst.addOperand(MCOperand::createImm(InsnS < max ? InsnS : max)); LLVM,ARC,73,"static DecodeStatus DecodeGBR32ShortRegister ( MCInst & Inst , unsigned RegNo , uint64_t Address , const MCDisassembler * Decoder ) { if ( RegNo > ) RegNo += ; return DecodeGPR32RegisterClass ( Inst , RegNo , Address , Decoder ); }" LLVM,ARC,74, LLVM,ARC,75,return MCDisassembler::Fail; } unsigned Reg = GPR32DecoderTable[RegNo]; Inst.addOperand(MCOperand::createReg(Reg)); LLVM,ARC,76,Inst.addOperand(MCOperand::createImm((uint32_t)(Insn >> ))); LLVM,ARC,77,"( Insn & ( 0x00000000 & ~ 0x00000000 ) ) >> 0 ) ; DecodeGPR32RegisterClass ( Inst , R , Address , Dec ) ; Inst . addOperand ( MCOperand :: createImm ( SignExtend32 < ( Insn & ( 0x00000000 & ~ 0x00000000 ) ) >> 0 ) ) ;" LLVM,ARC,78, LLVM,ARC,79, LLVM,ARC,80,return MCDisassembler::Success; LLVM,ARC,81,"static DecodeStatus DecodeSOPwithRU6 ( MCInst & Inst , uint64_t Insn , uint64_t Address , const MCDisassembler * Decoder ) { unsigned DstB = decodeBField ( Insn );" LLVM,ARC,82,Inst.addOperand(MCOperand::createImm(LImm)); LLVM,ARC,83, LLVM,ARC,84,return false; LLVM,ARC,85,"if ( Bytes.size() >= 6 ) { uint64_t Insn48; if ( !readInstruction48(Bytes, Address, Size, Insn48) ) { return Fail; } } else { return Fail; }" LLVM,ARC,86,"TargetRegistry :: RegisterMCDisassembler ( getTheTarget (), createMCDisassembler ());" LLVM,ARC,87,Insn = ( Bytes [ ] << ) | ( Bytes [ ] << ) LLVM,ARC,88,Insn = ( Bytes [3] << 24) | ( Bytes [2] << 16) | ( Bytes [1] << 8) | Bytes [0]; LLVM,ARC,89, LLVM,ARC,90,Insn = ( ( uint64_t ) Bytes [ ] << ) | ( ( uint64_t ) Bytes [ ] << ) | ( ( uint64_t ) Bytes [ ] << ) | ( ( uint64_t ) Bytes [ ] << ) | ( ( uint64_t ) Bytes [ ) ; LLVM,ARC,94, LLVM,ARC,95,"while ( MBBI != E ) { MachineBasicBlock :: iterator NMBBI = std :: next ( MBBI ) ; switch ( MBBI -> getOpcode ( ) ) { case : case : case : expandStore ( MF , MBBI ) ; Expanded = true ; break ; case : expandCTLZ ( MF , MBBI ) ; Expanded = true ; break ; default : break ; } } }" LLVM,ARC,96, LLVM,ARC,97,createFunctionPassManager() { return new FunctionPassManager(); } LLVM,ARC,98,"MBBI , NMBBI ) ; break ; default : MBBI = NMBBI ; break ; } }" LLVM,ARC,99, LLVM,ARC,100, LLVM,ARC,101,"void FrameLowering::processFunctionBeforeFrameFinalized(MachineFunction &MF, RegScavenger *RS) const {" LLVM,ARC,102, LLVM,ARC,103,Last > 0) { LLVM,ARC,104,return Last; LLVM,ARC,105,"AmountAboveFunclet ) ) Opc = ; else if ( isInt < > ( * [/INST] AmountAboveFunclet ) ) Opc = ; BuildMI ( MBB , MBBI , MBB . findDebugLoc ( MBBI ) , TII -> get ( Opc ) , ) . addReg ( ) . addImm ( * AmountAboveFunclet" LLVM,ARC,106, LLVM,ARC,107, LLVM,ARC,108, LLVM,ARC,109,return false; LLVM,ARC,110,for (const auto &Entry : CSI) LLVM,ARC,111, LLVM,ARC,112,"return MFI.CreateFixedSpillStackObject(, CurOffset, true);" LLVM,ARC,113,if (hasFP(MF)) { LLVM,ARC,114,"BuildMI(MBB, MBBI, MBB.findDebugLoc(MBBI), TII->get()).addExternalSymbol(load_funclet_name[Last - ]);" LLVM,ARC,115,AdjOp = Positive ? : ; LLVM,ARC,116, LLVM,ARC,117, LLVM,ARC,118,"DEBUG ( dbgs ( ) << ""Parent: "" << MBB . getParent ( ) );" LLVM,ARC,119, LLVM,ARC,120, LLVM,ARC,121,return HasFP; LLVM,ARC,122,"void ISA_LITFrameLowering::adjustStackToMatchRecords(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, bool Allocate) const { MachineFunction &MF = *MBB.getParent(); int ScalarAlloc = MF.getFrameInfo().getStackSize(); if (Allocate) { } else { } }" LLVM,ARC,123,CurOffset -= ; LLVM,ARC,124, LLVM,ARC,125,"AbsAmount = Amount; Positive = true; } LLVM_DEBUG(dbgs() << ""Amount: "" << Amount << "" AbsAmount: "" << AbsAmount << "" Positive: "" << Positive); assert((AbsAmount % 2 == 0) && ""AbsAmount must be" LLVM,ARC,126,I++ ) { if ( I->Reg == reg ) { return I; } } return V.end(); LLVM,ARC,127,return V.end(); LLVM,ARC,128, LLVM,ARC,129,bool FrameLowering:: LLVM,ARC,130,"void printOperand ( const MCInst * MI , uint64_t OpNum ) { const MCOperand * Op = MI->getOperand(OpNum); if (Op->isReg()) { printRegName(Op->getReg()); } else if (Op->isImm()) { printImm(Op->getImm()); } else if (Op->isFPImm()) { printFPImm(Op->getFPImm()); } else { printOperand(Op" LLVM,ARC,131,case : return ; LLVM,ARC,132,switch (expression) { LLVM,ARC,133,O << CondCodeToString ( ( ) MI -> getOperand ( OpNum ) . getImm ( ) ); LLVM,ARC,134,"printU6ShiftedBy ( , MI , OpNum , );" LLVM,ARC,135,"errs() << ""Invalid operand value: "" << MI->getOpcode() << "" "" << Value;" LLVM,ARC,136,static const char *BRCondCodeToString(BRCC) { LLVM,ARC,137,Offset = SRE->getOffset() + CE->getValue(); LLVM,ARC,138,switch (expression) { LLVM,ARC,139, LLVM,ARC,140,DEBUG ( dbgs ( ) << << cc << ) ; return; LLVM,ARC,141,const MCOperand & Op = MI->getOperand(OpNum); assert(Op.isImm()); LLVM,ARC,142, LLVM,ARC,143, LLVM,ARC,144,"Annot , STI ) ; }" LLVM,ARC,145,getImm ( ) ; LLVM,ARC,146,"getImm ( ) ; printImm ( O , Op . getImm ( ) ) ; return ; } if ( Op . isMem ( ) ) { printMemOperand ( O , Op . getMem ( ) ) ; return ; } if ( Op . isFPImm ( ) ) { printFPImmOperand ( O , Op . getFPImm ( ) ) ; return ; } if ( Op . isInst ( ) ) { printInstOperand ( O , Op . getInst ( ) ) ; return ; }" LLVM,ARC,147,"void InstPrinter :: printPredicateOperand ( const MCInst * MI , unsigned OpNum , raw_ostream & O ) { const MCOperand & Op = MI -> getOperand ( OpNum ); if ( Op.isReg () ) { O << getRegisterName ( Op.getReg () ); } else if ( Op.isImm () ) { O << Op.getImm (); } else { O << ""?""; } }" LLVM,ARC,148,assert(Op.isImm() && LLVM,ARC,149,} LLVM,ARC,150,} LLVM,ARC,151,if ( !isPredicated( *I ) && ( isUncondBranchOpcode( I->getOpcode( ) ) || isJumpOpcode( I->getOpcode( ) ) || I->isReturn( ) ) ) { Cond.clear(); } LLVM,ARC,152, LLVM,ARC,153,MachineFunction &MF = *MBB.getParent(); LLVM,ARC,154,"assert ( TRI->getSpillSize(*RC) == MFI.getObjectSize(FrameIndex) && ""Spill size and stack slot size do not match"");" LLVM,ARC,155, LLVM,ARC,156, LLVM,ARC,157,assert ( MMO && ) ; LLVM,ARC,158, LLVM,ARC,159,return true; LLVM,ARC,160,MI ) ) { BasePos = ; OffsetPos = ; } return true ; } LLVM,ARC,161,const char * AsmStr LLVM,ARC,162, LLVM,ARC,163,bool InstrInfo :: isPostIncrement ( const MachineInstr & MI ) const { const MCInstrDesc & MID = MI . getDesc ( ) ; const uint64_t F = MID . getFlags ( ) ; return ( F & MCIDecode::PostIncrement ) != 0 ; } LLVM,ARC,164,"It appears that the code is trying to extract a specific bit field from a 64-bit unsigned integer. The `MID` variable is a 64-bit unsigned integer, and the `TSFlags` variable is a 32-bit unsigned integer. The `TSF_AddrModeOff` and `TSF_AddModeMask` variables are likely bit masks used to extract" LLVM,ARC,165, LLVM,ARC,166, LLVM,ARC,167,"void InstrInfo :: loadRegFromStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , Register DestReg , int FrameIndex , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { DebugLoc DL = MBB . findDebugLoc ( I ) ; MachineFunction & MF = * MBB . getParent ( ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixed" LLVM,ARC,168,"BuildMI(MBB, I, DL, get())" LLVM,ARC,169, LLVM,ARC,170,MachineFrameInfo & MFI = MF.getFrameInfo(); LLVM,ARC,171,} else if (isCondBranchOpcode(I->getOpcode())) { LLVM,ARC,172, LLVM,ARC,173, LLVM,ARC,174,switch (expression) { LLVM,ARC,175,return RI; } LLVM,ARC,176,"static bool isCondBranchOpcode ( int Opc ) { return Opc == || Opc == ""b"" || Opc == ""bl"" || Opc == ""bx"" || Opc == ""blx""; }" LLVM,ARC,177,return Opc == || Opc == ; LLVM,ARC,178,static bool isJumpOpcode ( int Opc ) { return Opc == 0xE9; } LLVM,ARC,179,return Opc == 0; Explanation: LLVM,ARC,180,"static bool isLoad ( int Opcode ) { return Opcode == ""STR_LIT"" || Opcode ==" LLVM,ARC,181,return false; LLVM,ARC,182,return Opcode == || Opcode == || Opcode == ; LLVM,ARC,183,if (MI.getOperand().isFI() && MI.getOperand().isImm()) { LLVM,ARC,184,"MachineBasicBlock::iterator InstrInfo::loadImmediate(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned Reg, uint64_t Value) const { DebugLoc dl = MBB.findDebugLoc(MI); if (isInt(Value)) { return loadImmediate(MBB, MI, Reg, Value, dl);" LLVM,ARC,185, LLVM,ARC,186,if (Cond[].getImm() == GetOppositeBranchCondition(()) { LLVM,ARC,187, LLVM,ARC,188, LLVM,ARC,189, LLVM,ARC,190,if (Addr.getOpcode() == ) { Base = Addr.getOperand(); } LLVM,ARC,191,return false; LLVM,ARC,192,return false; } LLVM,ARC,193,return true; LLVM,ARC,194, LLVM,ARC,195,return true; LLVM,ARC,196,return false; LLVM,ARC,197,llvm_unr LLVM,ARC,198,getByValSize ( ) ; LLVM,ARC,199,"DAG ) ; case : return LowerSETCC ( Op , DAG ) ; case : return LowerSTORE_FLAG ( Op , DAG ) ; case : return LowerLOAD_FLAG ( Op , DAG ) ; default : llvm_unreachable ( ""Unknown operator"" ) ; } }" LLVM,ARC,200,"setOperationAction ( , , Custom ) ; setOperationAction ( , , Legal ) ; setOperationAction ( , , Expand ) ; setOperationAction ( , , Expand ) ; setOperation" LLVM,ARC,201, LLVM,ARC,202, LLVM,ARC,203, LLVM,ARC,204, LLVM,ARC,205,switch (expression) { LLVM,ARC,206,"bool TargetLowering::isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AS, Instruction *I) const { return AM.Scale == 1; }" LLVM,ARC,207,e ] . second ) ; } LLVM,ARC,208,MFI.setFrameAddressIsTaken(true); LLVM,ARC,209, LLVM,ARC,210,"DAG ) ; case : return LowerSETCC ( Op , DAG ) ; case : return LowerSTORE_FLAG ( Op , DAG ) ; case : return LowerLOAD_FLAG ( Op , DAG ) ; default : llvm_unreachable ( ""Unknown operator"" ) ; } }" LLVM,ARC,211,if ( ! MemOpChains . empty ( ) ) Chain = DAG . getNode () LLVM,ARC,212, LLVM,ARC,213,return SR; LLVM,ARC,214,const Value * SV = cast(Op.getOperand(0)); LLVM,ARC,215, LLVM,ARC,216,"SDValue TargetLowering :: PerformDAGCombine ( SDNode * N , DAGCombinerInfo & DCI ) const {" LLVM,ARC,217,"explicit FunctionInfo ( MachineFunction & MF ) : ReturnStackOffsetSet ( false ) , VarArgsFrameIndex ( )" LLVM,ARC,218,"explicit FunctionInfo ( MachineFunction & MF ) : ReturnStackOffsetSet ( false ) , VarArgsFrameIndex ( ) , ReturnStackOffset ( - ) , MaxCallStackReq ( 0 )" LLVM,ARC,219,"explicit FunctionInfo ( MachineFunction & MF ) : ReturnStackOffsetSet ( false ) , VarArgsFrameIndex ( ) , VarArgFrameBytes ( ) , ReturnStackOffset ( - ) , MaxCallStackReq ( ) { MF . setAlignment ( );" LLVM,ARC,220,"explicit FunctionInfo ( MachineFunction & MF ) : ReturnStackOffsetSet ( false ) , VarArgsFrameIndex ( ) , VarArgFrameBytes ( ) , ReturnStackOffset ( -1 )" LLVM,ARC,221,"assert ( ReturnStackOffsetSet && ""ReturnStackOffsetSet is not set"" );" LLVM,ARC,222,"assert ( ReturnStackOffsetSet && ""ReturnStackOffsetSet is not set"" );" LLVM,ARC,223,return frameIndex; LLVM,ARC,224,ReturnStackOffsetSet = true; LLVM,ARC,225,ReturnStackOffset = value; ReturnStackOffsetSet = true; LLVM,ARC,226, LLVM,ARC,227, LLVM,ARC,228,Data32bitsDirective = ; Data64bitsDirective = nullptr ; ZeroDirective = ; CommentString = ; UsesELFSectionDirectiveForBSS = true ; LLVM,ARC,229,DwarfRegNumForCFI = 0; LLVM,ARC,230,"void MCInstLower::Lower(const MachineInstr *MI, MCInst &OutMI) const { OutMI.setOpcode(MI->getOpcode()); OutMI.setOperand(0, MI->getOperand(0)); OutMI.setOperand(1, MI->getOperand(1)); OutMI.setOperand(2, MI->getOperand(2)); OutMI.setOperand(3, MI->getOperand(3)); OutMI.setOperand(4" LLVM,ARC,231,OutMI.setOpcode(MI->getOpcode()); LLVM,ARC,232,switch ( MOTy ) { LLVM,ARC,233,"assert(Symbol && ""Symbol not found"");" LLVM,ARC,234,"return createMCSubtargetInfoImpl ( TT , CPU , CPU , Fusion." LLVM,ARC,235,"return createMCSubtargetInfoImpl ( TT , CPU , CPU , Fusion." LLVM,ARC,236,"TargetRegistry::RegisterMCInstPrinter(TheTarget, createMCInstPrinter);" LLVM,ARC,237,"MCAsmInfo * MAI = new MCAsmInfo ( TT ) ; MCCFIInstruction Inst = MCCFIInstruction :: createDefCfa ( nullptr ," LLVM,ARC,238,return MAI; LLVM,ARC,239,"static MCInstPrinter * createMCInstPrinter ( const Triple & T , unsigned SyntaxVariant , const MCAsmInfo & MAI , const MCInstrInfo & MII , const MCRegisterInfo & MRI ) { return new InstPrinter ( MAI , MII , MRI ); }" LLVM,ARC,240,Here is an example of how you LLVM,ARC,241,auto *X = new MCRegisterInfo(); LLVM,ARC,242,"return createMCSubtargetInfoImpl(TT, CPU, FS);" LLVM,ARC,243,"TargetRegistry::RegisterTargetAsmStreamer(TheTarget, createTargetAsmStreamer);" LLVM,ARC,244,"TargetRegistry::RegisterMCInstPrinter(TheTarget, createMCInstPrinter);" LLVM,ARC,245,Ldst.addOperand(NewOffset); LLVM,ARC,246,"Ldst.addOperand(MachineOperand::CreateReg(BaseReg, false));" LLVM,ARC,247, LLVM,ARC,248, LLVM,ARC,249,return Result; LLVM,ARC,250, LLVM,ARC,251, LLVM,ARC,252,Register R = Add -> getOperand ( ) . getReg ( 0 ); LLVM,ARC,253, LLVM,ARC,254,return Changed; LLVM,ARC,255,".getOpcode ( ) ) ; Ldst . setOpcode ( NewOpcode ) ; Ldst . setOperand ( , Add . getOperand ( ) ) ; Ldst . setOperand ( , Add . getOperand ( ) ) ; Ldst . setOperand ( , Add . getOperand ( ) ) ; Ldst . setOperand ( , Add . getOperand (" LLVM,ARC,256, LLVM,ARC,257,return true; LLVM,ARC,258,"unsigned BasePos , OffPos ; if ( ! AII -> getBaseAndOffsetPosition ( * Ldst , BasePos , OffPos ) ) { LLVM_DEBUG ( dbgs ( ) << ) ; return nullptr ; } unsigned BaseReg = Ldst -> getOperand ( BasePos ) . getReg ( ) ; if ( Ldst -> mayStore ( ) && Ldst -> getOperand ( ) . isReg ( ) ) { unsigned StReg = Ldst -> getOperand" LLVM,ARC,259, LLVM,ARC,260,"Ldst.addOperand(MachineOperand::CreateReg(BaseReg, false));" LLVM,ARC,261,return new OptAddrMode(); LLVM,ARC,262,"llvm_unreachable(""Invalid load/store offset"");" LLVM,ARC,263,"assert ( isValidIncrementOffset ( NewOffset ) && ""Invalid increment offset"" ) ; BasePos = 0 ; OffPos = 1 ; } else if ( AII -> getBaseAndOffsetPosition ( * MI , BasePos , OffPos ) ) { MachineOperand & MO = MI -> getOperand ( OffPos ) ; assert ( MO . isImm ( ) ) ;" LLVM,ARC,264,AU . addRequired < MachineDominatorTree > ( ) ; LLVM,ARC,265,AU . addRequired < MachineDominatorTree > ( ) ; LLVM,ARC,266,case : Amount = Sign * MI.getOperand().getImm(); break; LLVM,ARC,267,return isValidLoadStoreOffset(Offset); LLVM,ARC,268,"static bool isValidLoadStoreOffset ( int64_t offset, int64_t size ) { return (offset >= 0 && offset + size <= 16); }" LLVM,ARC,269,"bool OptAddrMode :: noUseOfAddBeforeLoadOrStore ( const MachineInstr * Add , const MachineInstr * Ldst ) { unsigned R = Add -> getOperand ( 0 ) -> getReg ( ) ; if ( Ldst -> getOpcode ( ) == Ldst ) { return false ; } if ( Ldst -> getOpcode ( ) == Ldst ) { return false ; } if ( Ldst ->" LLVM,ARC,270,"For each instruction, the function checks if it is a debug" LLVM,ARC,271,return OptAddrModeImpl::runOnMachineFunction(MF); LLVM,ARC,272, LLVM,ARC,273, LLVM,ARC,274, LLVM,ARC,275,unsigned RegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { const FrameLowering * TFI = getFrameLowering ( MF ); return TFI->getFrameRegister ( MF ); } LLVM,ARC,276,return TFI->hasFP(MF) ? TFI->getFP(MF) : nullptr; LLVM,ARC,277, LLVM,ARC,278,case : LLVM,ARC,279,return false; LLVM,ARC,280, LLVM,ARC,281,"BuildMI(MBB, II, dl, TII.get(MI.getOpcode()), Reg).addReg(BaseReg, KillState).addImm(Offset).addMemOperand(*MI.memoperands_begin());" LLVM,ARC,282, LLVM,ARC,283,const MCPhysReg *RegisterInfo::get LLVM,ARC,284, LLVM,ARC,285, LLVM,ARC,286,return MF.getMMI().hasDebugInfo() || MF.getFunction(MF.getFunctionName()); LLVM,ARC,287,"BuildMI(MBB, II, dl, TII.get(isUInt(Offset) ? STR_LIT : STR_LIT))" LLVM,ARC,288,* if (MF.getSubtarget().hasRegisterScavenger()) { * return true; * } * return false; * } LLVM,ARC,289,return true; LLVM,ARC,290,const ISA_LIT::FrameLowering * getFrameLowering() const override { LLVM,ARC,291,const ISA_LIT>FrameLowering * getFrameLowering ( ) const override { return & [ISA_LIT]>FrameLowering::instance ( ); } LLVM,ARC,292,const InstrInfo * getInstrInfo ( ) const override { return &InstrInfo; } LLVM,ARC,293,"const InstrInfo * getInstrInfo (const InstrInfo * instrInfo, uint32_t opcode) { if (instrInfo == NULL) { return NULL; } for (int i = 0; i < instrInfo->numInstrs; i++) { if (instrInfo->instrs[i].opcode == opcode) { return &instrInfo->instrs[i]; } } return NULL; }" LLVM,ARC,294,return &InstrInfo.getRegisterInfo(Inst); LLVM,ARC,295,const SelectionDAGTargetInfo * getSelectionDAGInfo (const SelectionDAGTargetInfo * info) { const SelectionDAGTargetInfo * result = nullptr; if (info != nullptr) { result = info; } else { result = new SelectionDAGTargetInfo(); } return result; } LLVM,ARC,296,const TargetLowering * getTargetLowering ( ) const override { return &TargetLowering; } LLVM,ARC,297,bool hasNorm (const Vector3D& v) { return v.x * v.x + v.y * v.y + v.z * v.z > 0; } LLVM,ARC,298,"RegisterTarget(getTheTarget(), , );" LLVM,ARC,299,return llvm::getTheTarget(); LLVM,ARC,300,RegisterTarget < Triple :: arc > X ( getTheTarget ( LLVM,ARC,301,"LLVMTargetMachine ( T , , TT , CPU , FS , Options , getRelocModel ( RM ) , getEffectiveCodeModel ( CM , CodeModel :: Small ) , OL )" LLVM,ARC,302,"TargetMachine::TargetMachine(const Target& T, const Triple& TT, StringRef CPU" LLVM,ARC,303,return RM.getValueOr(RM.getDefaultValue()); LLVM,ARC,304,void ISA_LITPassConfig::addPreRegAlloc() { addPass(createExpandPseudosPass>()); } LLVM,ARC,305,addPass(createExpandPseudosPass()); LLVM,ARC,306,initAsmInfo(); LLVM,ARC,307,static CodeModel::Model getEffectiveCodeModel(Optional CM) { if (CM) return *CM; else return CodeModel::Model(); } LLVM,ARC,308,return CodeModel::Small; LLVM,ARC,309,"TargetMachine :: TargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , Optional < CodeModel :: Model > CM , CodeGenOpt :: Level OL , bool JIT ) : LLVMTargetMachine ( T , " LLVM,ARC,310,RegisterTargetMachine < TargetMachine > X ( getTheTarget ( ) ); LLVM,ARC,311,"RegisterTargetMachine < TargetMachine > X ( getTheTarget ( ""target_name"" ) );" LLVM,ARC,312, LLVM,ARC,313,if (F.empty()) { return; } return; } LLVM,ARC,314,"bool PassConfig :: addInstSelector ( ) { addPass ( createISelDag ( getTargetMachine ( ) , getInstrInfo ( ) , getSubtarget ( ) , getTTI ( ) , getDL ( ) , getAC ( ) , getDT ( ) , getPB ( )" LLVM,ARC,315,void PassConfig :: addPreEmitPass ( ) { addPass ( createBranchFinalizePass ( ) ); } LLVM,ARC,316,void PassConfig :: addPreEmitPass ( ) { addPass ( createBranchFinalizePass ( ) ); } LLVM,ARC,317,void PassConfig::setPass(const Pass* pass) { } LLVM,ARC,318,void PassConfig::setPass(const Pass* pass) { } LLVM,ARC,319,return *this; LLVM,ARC,320,return getTM < TargetMachine > (TargetMachine::getHostCPUName()); LLVM,ARC,321, LLVM,ARC,322,TargetLoweringObjectFile * getObjFileLowering ( ) const override { return TLOF.get ( ); } LLVM,ARC,323,``` LLVM,ARC,324,const ISA_LIT>Subtarget * getSubtargetImpl ( const Function & ) const override { return &ISA_LIT>Subtarget; } LLVM,ARC,325,const ISA_LIT Subtarget * getSubtargetImpl ( const Function & ) const override { return & Subtarget; } LLVM,ARC,326,TargetTransformInfo TargetMachine :: getTargetTransformInfo ( const Function &F ) const { return TargetTransformInfo TargetMachine ( F ); } LLVM,ARC,327,const TargetLowering * getTLI ( ) { return &TLI; }